1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 304 MLX5_CMD_OP_MAX 305 }; 306 307 /* Valid range for general commands that don't work over an object */ 308 enum { 309 MLX5_CMD_OP_GENERAL_START = 0xb00, 310 MLX5_CMD_OP_GENERAL_END = 0xd00, 311 }; 312 313 struct mlx5_ifc_flow_table_fields_supported_bits { 314 u8 outer_dmac[0x1]; 315 u8 outer_smac[0x1]; 316 u8 outer_ether_type[0x1]; 317 u8 outer_ip_version[0x1]; 318 u8 outer_first_prio[0x1]; 319 u8 outer_first_cfi[0x1]; 320 u8 outer_first_vid[0x1]; 321 u8 outer_ipv4_ttl[0x1]; 322 u8 outer_second_prio[0x1]; 323 u8 outer_second_cfi[0x1]; 324 u8 outer_second_vid[0x1]; 325 u8 reserved_at_b[0x1]; 326 u8 outer_sip[0x1]; 327 u8 outer_dip[0x1]; 328 u8 outer_frag[0x1]; 329 u8 outer_ip_protocol[0x1]; 330 u8 outer_ip_ecn[0x1]; 331 u8 outer_ip_dscp[0x1]; 332 u8 outer_udp_sport[0x1]; 333 u8 outer_udp_dport[0x1]; 334 u8 outer_tcp_sport[0x1]; 335 u8 outer_tcp_dport[0x1]; 336 u8 outer_tcp_flags[0x1]; 337 u8 outer_gre_protocol[0x1]; 338 u8 outer_gre_key[0x1]; 339 u8 outer_vxlan_vni[0x1]; 340 u8 outer_geneve_vni[0x1]; 341 u8 outer_geneve_oam[0x1]; 342 u8 outer_geneve_protocol_type[0x1]; 343 u8 outer_geneve_opt_len[0x1]; 344 u8 reserved_at_1e[0x1]; 345 u8 source_eswitch_port[0x1]; 346 347 u8 inner_dmac[0x1]; 348 u8 inner_smac[0x1]; 349 u8 inner_ether_type[0x1]; 350 u8 inner_ip_version[0x1]; 351 u8 inner_first_prio[0x1]; 352 u8 inner_first_cfi[0x1]; 353 u8 inner_first_vid[0x1]; 354 u8 reserved_at_27[0x1]; 355 u8 inner_second_prio[0x1]; 356 u8 inner_second_cfi[0x1]; 357 u8 inner_second_vid[0x1]; 358 u8 reserved_at_2b[0x1]; 359 u8 inner_sip[0x1]; 360 u8 inner_dip[0x1]; 361 u8 inner_frag[0x1]; 362 u8 inner_ip_protocol[0x1]; 363 u8 inner_ip_ecn[0x1]; 364 u8 inner_ip_dscp[0x1]; 365 u8 inner_udp_sport[0x1]; 366 u8 inner_udp_dport[0x1]; 367 u8 inner_tcp_sport[0x1]; 368 u8 inner_tcp_dport[0x1]; 369 u8 inner_tcp_flags[0x1]; 370 u8 reserved_at_37[0x9]; 371 372 u8 geneve_tlv_option_0_data[0x1]; 373 u8 reserved_at_41[0x4]; 374 u8 outer_first_mpls_over_udp[0x4]; 375 u8 outer_first_mpls_over_gre[0x4]; 376 u8 inner_first_mpls[0x4]; 377 u8 outer_first_mpls[0x4]; 378 u8 reserved_at_55[0x2]; 379 u8 outer_esp_spi[0x1]; 380 u8 reserved_at_58[0x2]; 381 u8 bth_dst_qp[0x1]; 382 u8 reserved_at_5b[0x5]; 383 384 u8 reserved_at_60[0x18]; 385 u8 metadata_reg_c_7[0x1]; 386 u8 metadata_reg_c_6[0x1]; 387 u8 metadata_reg_c_5[0x1]; 388 u8 metadata_reg_c_4[0x1]; 389 u8 metadata_reg_c_3[0x1]; 390 u8 metadata_reg_c_2[0x1]; 391 u8 metadata_reg_c_1[0x1]; 392 u8 metadata_reg_c_0[0x1]; 393 }; 394 395 struct mlx5_ifc_flow_table_prop_layout_bits { 396 u8 ft_support[0x1]; 397 u8 reserved_at_1[0x1]; 398 u8 flow_counter[0x1]; 399 u8 flow_modify_en[0x1]; 400 u8 modify_root[0x1]; 401 u8 identified_miss_table_mode[0x1]; 402 u8 flow_table_modify[0x1]; 403 u8 reformat[0x1]; 404 u8 decap[0x1]; 405 u8 reserved_at_9[0x1]; 406 u8 pop_vlan[0x1]; 407 u8 push_vlan[0x1]; 408 u8 reserved_at_c[0x1]; 409 u8 pop_vlan_2[0x1]; 410 u8 push_vlan_2[0x1]; 411 u8 reformat_and_vlan_action[0x1]; 412 u8 reserved_at_10[0x1]; 413 u8 sw_owner[0x1]; 414 u8 reformat_l3_tunnel_to_l2[0x1]; 415 u8 reformat_l2_to_l3_tunnel[0x1]; 416 u8 reformat_and_modify_action[0x1]; 417 u8 ignore_flow_level[0x1]; 418 u8 reserved_at_16[0x1]; 419 u8 table_miss_action_domain[0x1]; 420 u8 termination_table[0x1]; 421 u8 reformat_and_fwd_to_table[0x1]; 422 u8 reserved_at_1a[0x2]; 423 u8 ipsec_encrypt[0x1]; 424 u8 ipsec_decrypt[0x1]; 425 u8 sw_owner_v2[0x1]; 426 u8 reserved_at_1f[0x1]; 427 428 u8 termination_table_raw_traffic[0x1]; 429 u8 reserved_at_21[0x1]; 430 u8 log_max_ft_size[0x6]; 431 u8 log_max_modify_header_context[0x8]; 432 u8 max_modify_header_actions[0x8]; 433 u8 max_ft_level[0x8]; 434 435 u8 reserved_at_40[0x20]; 436 437 u8 reserved_at_60[0x18]; 438 u8 log_max_ft_num[0x8]; 439 440 u8 reserved_at_80[0x18]; 441 u8 log_max_destination[0x8]; 442 443 u8 log_max_flow_counter[0x8]; 444 u8 reserved_at_a8[0x10]; 445 u8 log_max_flow[0x8]; 446 447 u8 reserved_at_c0[0x40]; 448 449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 452 }; 453 454 struct mlx5_ifc_odp_per_transport_service_cap_bits { 455 u8 send[0x1]; 456 u8 receive[0x1]; 457 u8 write[0x1]; 458 u8 read[0x1]; 459 u8 atomic[0x1]; 460 u8 srq_receive[0x1]; 461 u8 reserved_at_6[0x1a]; 462 }; 463 464 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 465 u8 smac_47_16[0x20]; 466 467 u8 smac_15_0[0x10]; 468 u8 ethertype[0x10]; 469 470 u8 dmac_47_16[0x20]; 471 472 u8 dmac_15_0[0x10]; 473 u8 first_prio[0x3]; 474 u8 first_cfi[0x1]; 475 u8 first_vid[0xc]; 476 477 u8 ip_protocol[0x8]; 478 u8 ip_dscp[0x6]; 479 u8 ip_ecn[0x2]; 480 u8 cvlan_tag[0x1]; 481 u8 svlan_tag[0x1]; 482 u8 frag[0x1]; 483 u8 ip_version[0x4]; 484 u8 tcp_flags[0x9]; 485 486 u8 tcp_sport[0x10]; 487 u8 tcp_dport[0x10]; 488 489 u8 reserved_at_c0[0x18]; 490 u8 ttl_hoplimit[0x8]; 491 492 u8 udp_sport[0x10]; 493 u8 udp_dport[0x10]; 494 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 498 }; 499 500 struct mlx5_ifc_nvgre_key_bits { 501 u8 hi[0x18]; 502 u8 lo[0x8]; 503 }; 504 505 union mlx5_ifc_gre_key_bits { 506 struct mlx5_ifc_nvgre_key_bits nvgre; 507 u8 key[0x20]; 508 }; 509 510 struct mlx5_ifc_fte_match_set_misc_bits { 511 u8 gre_c_present[0x1]; 512 u8 reserved_at_1[0x1]; 513 u8 gre_k_present[0x1]; 514 u8 gre_s_present[0x1]; 515 u8 source_vhca_port[0x4]; 516 u8 source_sqn[0x18]; 517 518 u8 source_eswitch_owner_vhca_id[0x10]; 519 u8 source_port[0x10]; 520 521 u8 outer_second_prio[0x3]; 522 u8 outer_second_cfi[0x1]; 523 u8 outer_second_vid[0xc]; 524 u8 inner_second_prio[0x3]; 525 u8 inner_second_cfi[0x1]; 526 u8 inner_second_vid[0xc]; 527 528 u8 outer_second_cvlan_tag[0x1]; 529 u8 inner_second_cvlan_tag[0x1]; 530 u8 outer_second_svlan_tag[0x1]; 531 u8 inner_second_svlan_tag[0x1]; 532 u8 reserved_at_64[0xc]; 533 u8 gre_protocol[0x10]; 534 535 union mlx5_ifc_gre_key_bits gre_key; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_at_b8[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved_at_d8[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_at_e0[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_at_100[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_at_120[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_at_140[0x8]; 555 u8 bth_dst_qp[0x18]; 556 u8 reserved_at_160[0x20]; 557 u8 outer_esp_spi[0x20]; 558 u8 reserved_at_1a0[0x60]; 559 }; 560 561 struct mlx5_ifc_fte_match_mpls_bits { 562 u8 mpls_label[0x14]; 563 u8 mpls_exp[0x3]; 564 u8 mpls_s_bos[0x1]; 565 u8 mpls_ttl[0x8]; 566 }; 567 568 struct mlx5_ifc_fte_match_set_misc2_bits { 569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 570 571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 572 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 574 575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 576 577 u8 metadata_reg_c_7[0x20]; 578 579 u8 metadata_reg_c_6[0x20]; 580 581 u8 metadata_reg_c_5[0x20]; 582 583 u8 metadata_reg_c_4[0x20]; 584 585 u8 metadata_reg_c_3[0x20]; 586 587 u8 metadata_reg_c_2[0x20]; 588 589 u8 metadata_reg_c_1[0x20]; 590 591 u8 metadata_reg_c_0[0x20]; 592 593 u8 metadata_reg_a[0x20]; 594 595 u8 reserved_at_1a0[0x60]; 596 }; 597 598 struct mlx5_ifc_fte_match_set_misc3_bits { 599 u8 inner_tcp_seq_num[0x20]; 600 601 u8 outer_tcp_seq_num[0x20]; 602 603 u8 inner_tcp_ack_num[0x20]; 604 605 u8 outer_tcp_ack_num[0x20]; 606 607 u8 reserved_at_80[0x8]; 608 u8 outer_vxlan_gpe_vni[0x18]; 609 610 u8 outer_vxlan_gpe_next_protocol[0x8]; 611 u8 outer_vxlan_gpe_flags[0x8]; 612 u8 reserved_at_b0[0x10]; 613 614 u8 icmp_header_data[0x20]; 615 616 u8 icmpv6_header_data[0x20]; 617 618 u8 icmp_type[0x8]; 619 u8 icmp_code[0x8]; 620 u8 icmpv6_type[0x8]; 621 u8 icmpv6_code[0x8]; 622 623 u8 geneve_tlv_option_0_data[0x20]; 624 625 u8 reserved_at_140[0xc0]; 626 }; 627 628 struct mlx5_ifc_fte_match_set_misc4_bits { 629 u8 prog_sample_field_value_0[0x20]; 630 631 u8 prog_sample_field_id_0[0x20]; 632 633 u8 prog_sample_field_value_1[0x20]; 634 635 u8 prog_sample_field_id_1[0x20]; 636 637 u8 prog_sample_field_value_2[0x20]; 638 639 u8 prog_sample_field_id_2[0x20]; 640 641 u8 prog_sample_field_value_3[0x20]; 642 643 u8 prog_sample_field_id_3[0x20]; 644 645 u8 reserved_at_100[0x100]; 646 }; 647 648 struct mlx5_ifc_cmd_pas_bits { 649 u8 pa_h[0x20]; 650 651 u8 pa_l[0x14]; 652 u8 reserved_at_34[0xc]; 653 }; 654 655 struct mlx5_ifc_uint64_bits { 656 u8 hi[0x20]; 657 658 u8 lo[0x20]; 659 }; 660 661 enum { 662 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 663 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 664 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 665 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 666 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 667 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 668 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 669 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 670 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 671 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 672 }; 673 674 struct mlx5_ifc_ads_bits { 675 u8 fl[0x1]; 676 u8 free_ar[0x1]; 677 u8 reserved_at_2[0xe]; 678 u8 pkey_index[0x10]; 679 680 u8 reserved_at_20[0x8]; 681 u8 grh[0x1]; 682 u8 mlid[0x7]; 683 u8 rlid[0x10]; 684 685 u8 ack_timeout[0x5]; 686 u8 reserved_at_45[0x3]; 687 u8 src_addr_index[0x8]; 688 u8 reserved_at_50[0x4]; 689 u8 stat_rate[0x4]; 690 u8 hop_limit[0x8]; 691 692 u8 reserved_at_60[0x4]; 693 u8 tclass[0x8]; 694 u8 flow_label[0x14]; 695 696 u8 rgid_rip[16][0x8]; 697 698 u8 reserved_at_100[0x4]; 699 u8 f_dscp[0x1]; 700 u8 f_ecn[0x1]; 701 u8 reserved_at_106[0x1]; 702 u8 f_eth_prio[0x1]; 703 u8 ecn[0x2]; 704 u8 dscp[0x6]; 705 u8 udp_sport[0x10]; 706 707 u8 dei_cfi[0x1]; 708 u8 eth_prio[0x3]; 709 u8 sl[0x4]; 710 u8 vhca_port_num[0x8]; 711 u8 rmac_47_32[0x10]; 712 713 u8 rmac_31_0[0x20]; 714 }; 715 716 struct mlx5_ifc_flow_table_nic_cap_bits { 717 u8 nic_rx_multi_path_tirs[0x1]; 718 u8 nic_rx_multi_path_tirs_fts[0x1]; 719 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 720 u8 reserved_at_3[0x4]; 721 u8 sw_owner_reformat_supported[0x1]; 722 u8 reserved_at_8[0x18]; 723 724 u8 encap_general_header[0x1]; 725 u8 reserved_at_21[0xa]; 726 u8 log_max_packet_reformat_context[0x5]; 727 u8 reserved_at_30[0x6]; 728 u8 max_encap_header_size[0xa]; 729 u8 reserved_at_40[0x1c0]; 730 731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 732 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 734 735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 736 737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 738 739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 740 741 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 742 743 u8 reserved_at_e00[0x1200]; 744 745 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 746 747 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 748 749 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 750 751 u8 reserved_at_20c0[0x5f40]; 752 }; 753 754 enum { 755 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 756 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 757 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 758 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 759 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 760 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 761 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 762 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 763 }; 764 765 struct mlx5_ifc_flow_table_eswitch_cap_bits { 766 u8 fdb_to_vport_reg_c_id[0x8]; 767 u8 reserved_at_8[0xd]; 768 u8 fdb_modify_header_fwd_to_table[0x1]; 769 u8 reserved_at_16[0x1]; 770 u8 flow_source[0x1]; 771 u8 reserved_at_18[0x2]; 772 u8 multi_fdb_encap[0x1]; 773 u8 egress_acl_forward_to_vport[0x1]; 774 u8 fdb_multi_path_to_table[0x1]; 775 u8 reserved_at_1d[0x3]; 776 777 u8 reserved_at_20[0x1e0]; 778 779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 780 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 784 785 u8 reserved_at_800[0x1000]; 786 787 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 788 789 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 790 791 u8 sw_steering_uplink_icm_address_rx[0x40]; 792 793 u8 sw_steering_uplink_icm_address_tx[0x40]; 794 795 u8 reserved_at_1900[0x6700]; 796 }; 797 798 enum { 799 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 800 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 801 }; 802 803 struct mlx5_ifc_e_switch_cap_bits { 804 u8 vport_svlan_strip[0x1]; 805 u8 vport_cvlan_strip[0x1]; 806 u8 vport_svlan_insert[0x1]; 807 u8 vport_cvlan_insert_if_not_exist[0x1]; 808 u8 vport_cvlan_insert_overwrite[0x1]; 809 u8 reserved_at_5[0x3]; 810 u8 esw_uplink_ingress_acl[0x1]; 811 u8 reserved_at_9[0x10]; 812 u8 esw_functions_changed[0x1]; 813 u8 reserved_at_1a[0x1]; 814 u8 ecpf_vport_exists[0x1]; 815 u8 counter_eswitch_affinity[0x1]; 816 u8 merged_eswitch[0x1]; 817 u8 nic_vport_node_guid_modify[0x1]; 818 u8 nic_vport_port_guid_modify[0x1]; 819 820 u8 vxlan_encap_decap[0x1]; 821 u8 nvgre_encap_decap[0x1]; 822 u8 reserved_at_22[0x1]; 823 u8 log_max_fdb_encap_uplink[0x5]; 824 u8 reserved_at_21[0x3]; 825 u8 log_max_packet_reformat_context[0x5]; 826 u8 reserved_2b[0x6]; 827 u8 max_encap_header_size[0xa]; 828 829 u8 reserved_at_40[0xb]; 830 u8 log_max_esw_sf[0x5]; 831 u8 esw_sf_base_id[0x10]; 832 833 u8 reserved_at_60[0x7a0]; 834 835 }; 836 837 struct mlx5_ifc_qos_cap_bits { 838 u8 packet_pacing[0x1]; 839 u8 esw_scheduling[0x1]; 840 u8 esw_bw_share[0x1]; 841 u8 esw_rate_limit[0x1]; 842 u8 reserved_at_4[0x1]; 843 u8 packet_pacing_burst_bound[0x1]; 844 u8 packet_pacing_typical_size[0x1]; 845 u8 reserved_at_7[0x1]; 846 u8 nic_sq_scheduling[0x1]; 847 u8 nic_bw_share[0x1]; 848 u8 nic_rate_limit[0x1]; 849 u8 packet_pacing_uid[0x1]; 850 u8 reserved_at_c[0x14]; 851 852 u8 reserved_at_20[0xb]; 853 u8 log_max_qos_nic_queue_group[0x5]; 854 u8 reserved_at_30[0x10]; 855 856 u8 packet_pacing_max_rate[0x20]; 857 858 u8 packet_pacing_min_rate[0x20]; 859 860 u8 reserved_at_80[0x10]; 861 u8 packet_pacing_rate_table_size[0x10]; 862 863 u8 esw_element_type[0x10]; 864 u8 esw_tsar_type[0x10]; 865 866 u8 reserved_at_c0[0x10]; 867 u8 max_qos_para_vport[0x10]; 868 869 u8 max_tsar_bw_share[0x20]; 870 871 u8 reserved_at_100[0x700]; 872 }; 873 874 struct mlx5_ifc_debug_cap_bits { 875 u8 core_dump_general[0x1]; 876 u8 core_dump_qp[0x1]; 877 u8 reserved_at_2[0x7]; 878 u8 resource_dump[0x1]; 879 u8 reserved_at_a[0x16]; 880 881 u8 reserved_at_20[0x2]; 882 u8 stall_detect[0x1]; 883 u8 reserved_at_23[0x1d]; 884 885 u8 reserved_at_40[0x7c0]; 886 }; 887 888 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 889 u8 csum_cap[0x1]; 890 u8 vlan_cap[0x1]; 891 u8 lro_cap[0x1]; 892 u8 lro_psh_flag[0x1]; 893 u8 lro_time_stamp[0x1]; 894 u8 reserved_at_5[0x2]; 895 u8 wqe_vlan_insert[0x1]; 896 u8 self_lb_en_modifiable[0x1]; 897 u8 reserved_at_9[0x2]; 898 u8 max_lso_cap[0x5]; 899 u8 multi_pkt_send_wqe[0x2]; 900 u8 wqe_inline_mode[0x2]; 901 u8 rss_ind_tbl_cap[0x4]; 902 u8 reg_umr_sq[0x1]; 903 u8 scatter_fcs[0x1]; 904 u8 enhanced_multi_pkt_send_wqe[0x1]; 905 u8 tunnel_lso_const_out_ip_id[0x1]; 906 u8 reserved_at_1c[0x2]; 907 u8 tunnel_stateless_gre[0x1]; 908 u8 tunnel_stateless_vxlan[0x1]; 909 910 u8 swp[0x1]; 911 u8 swp_csum[0x1]; 912 u8 swp_lso[0x1]; 913 u8 cqe_checksum_full[0x1]; 914 u8 tunnel_stateless_geneve_tx[0x1]; 915 u8 tunnel_stateless_mpls_over_udp[0x1]; 916 u8 tunnel_stateless_mpls_over_gre[0x1]; 917 u8 tunnel_stateless_vxlan_gpe[0x1]; 918 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 919 u8 tunnel_stateless_ip_over_ip[0x1]; 920 u8 insert_trailer[0x1]; 921 u8 reserved_at_2b[0x1]; 922 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 923 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 924 u8 reserved_at_2e[0x2]; 925 u8 max_vxlan_udp_ports[0x8]; 926 u8 reserved_at_38[0x6]; 927 u8 max_geneve_opt_len[0x1]; 928 u8 tunnel_stateless_geneve_rx[0x1]; 929 930 u8 reserved_at_40[0x10]; 931 u8 lro_min_mss_size[0x10]; 932 933 u8 reserved_at_60[0x120]; 934 935 u8 lro_timer_supported_periods[4][0x20]; 936 937 u8 reserved_at_200[0x600]; 938 }; 939 940 enum { 941 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 942 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 943 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 944 }; 945 946 struct mlx5_ifc_roce_cap_bits { 947 u8 roce_apm[0x1]; 948 u8 reserved_at_1[0x3]; 949 u8 sw_r_roce_src_udp_port[0x1]; 950 u8 reserved_at_5[0x19]; 951 u8 qp_ts_format[0x2]; 952 953 u8 reserved_at_20[0x60]; 954 955 u8 reserved_at_80[0xc]; 956 u8 l3_type[0x4]; 957 u8 reserved_at_90[0x8]; 958 u8 roce_version[0x8]; 959 960 u8 reserved_at_a0[0x10]; 961 u8 r_roce_dest_udp_port[0x10]; 962 963 u8 r_roce_max_src_udp_port[0x10]; 964 u8 r_roce_min_src_udp_port[0x10]; 965 966 u8 reserved_at_e0[0x10]; 967 u8 roce_address_table_size[0x10]; 968 969 u8 reserved_at_100[0x700]; 970 }; 971 972 struct mlx5_ifc_sync_steering_in_bits { 973 u8 opcode[0x10]; 974 u8 uid[0x10]; 975 976 u8 reserved_at_20[0x10]; 977 u8 op_mod[0x10]; 978 979 u8 reserved_at_40[0xc0]; 980 }; 981 982 struct mlx5_ifc_sync_steering_out_bits { 983 u8 status[0x8]; 984 u8 reserved_at_8[0x18]; 985 986 u8 syndrome[0x20]; 987 988 u8 reserved_at_40[0x40]; 989 }; 990 991 struct mlx5_ifc_device_mem_cap_bits { 992 u8 memic[0x1]; 993 u8 reserved_at_1[0x1f]; 994 995 u8 reserved_at_20[0xb]; 996 u8 log_min_memic_alloc_size[0x5]; 997 u8 reserved_at_30[0x8]; 998 u8 log_max_memic_addr_alignment[0x8]; 999 1000 u8 memic_bar_start_addr[0x40]; 1001 1002 u8 memic_bar_size[0x20]; 1003 1004 u8 max_memic_size[0x20]; 1005 1006 u8 steering_sw_icm_start_address[0x40]; 1007 1008 u8 reserved_at_100[0x8]; 1009 u8 log_header_modify_sw_icm_size[0x8]; 1010 u8 reserved_at_110[0x2]; 1011 u8 log_sw_icm_alloc_granularity[0x6]; 1012 u8 log_steering_sw_icm_size[0x8]; 1013 1014 u8 reserved_at_120[0x20]; 1015 1016 u8 header_modify_sw_icm_start_address[0x40]; 1017 1018 u8 reserved_at_180[0x680]; 1019 }; 1020 1021 struct mlx5_ifc_device_event_cap_bits { 1022 u8 user_affiliated_events[4][0x40]; 1023 1024 u8 user_unaffiliated_events[4][0x40]; 1025 }; 1026 1027 struct mlx5_ifc_virtio_emulation_cap_bits { 1028 u8 desc_tunnel_offload_type[0x1]; 1029 u8 eth_frame_offload_type[0x1]; 1030 u8 virtio_version_1_0[0x1]; 1031 u8 device_features_bits_mask[0xd]; 1032 u8 event_mode[0x8]; 1033 u8 virtio_queue_type[0x8]; 1034 1035 u8 max_tunnel_desc[0x10]; 1036 u8 reserved_at_30[0x3]; 1037 u8 log_doorbell_stride[0x5]; 1038 u8 reserved_at_38[0x3]; 1039 u8 log_doorbell_bar_size[0x5]; 1040 1041 u8 doorbell_bar_offset[0x40]; 1042 1043 u8 max_emulated_devices[0x8]; 1044 u8 max_num_virtio_queues[0x18]; 1045 1046 u8 reserved_at_a0[0x60]; 1047 1048 u8 umem_1_buffer_param_a[0x20]; 1049 1050 u8 umem_1_buffer_param_b[0x20]; 1051 1052 u8 umem_2_buffer_param_a[0x20]; 1053 1054 u8 umem_2_buffer_param_b[0x20]; 1055 1056 u8 umem_3_buffer_param_a[0x20]; 1057 1058 u8 umem_3_buffer_param_b[0x20]; 1059 1060 u8 reserved_at_1c0[0x640]; 1061 }; 1062 1063 enum { 1064 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1065 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1066 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1067 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1068 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1069 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1070 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1071 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1072 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1073 }; 1074 1075 enum { 1076 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1077 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1078 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1079 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1080 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1081 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1082 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1083 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1084 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1085 }; 1086 1087 struct mlx5_ifc_atomic_caps_bits { 1088 u8 reserved_at_0[0x40]; 1089 1090 u8 atomic_req_8B_endianness_mode[0x2]; 1091 u8 reserved_at_42[0x4]; 1092 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1093 1094 u8 reserved_at_47[0x19]; 1095 1096 u8 reserved_at_60[0x20]; 1097 1098 u8 reserved_at_80[0x10]; 1099 u8 atomic_operations[0x10]; 1100 1101 u8 reserved_at_a0[0x10]; 1102 u8 atomic_size_qp[0x10]; 1103 1104 u8 reserved_at_c0[0x10]; 1105 u8 atomic_size_dc[0x10]; 1106 1107 u8 reserved_at_e0[0x720]; 1108 }; 1109 1110 struct mlx5_ifc_odp_cap_bits { 1111 u8 reserved_at_0[0x40]; 1112 1113 u8 sig[0x1]; 1114 u8 reserved_at_41[0x1f]; 1115 1116 u8 reserved_at_60[0x20]; 1117 1118 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1119 1120 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1121 1122 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1123 1124 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1125 1126 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1127 1128 u8 reserved_at_120[0x6E0]; 1129 }; 1130 1131 struct mlx5_ifc_calc_op { 1132 u8 reserved_at_0[0x10]; 1133 u8 reserved_at_10[0x9]; 1134 u8 op_swap_endianness[0x1]; 1135 u8 op_min[0x1]; 1136 u8 op_xor[0x1]; 1137 u8 op_or[0x1]; 1138 u8 op_and[0x1]; 1139 u8 op_max[0x1]; 1140 u8 op_add[0x1]; 1141 }; 1142 1143 struct mlx5_ifc_vector_calc_cap_bits { 1144 u8 calc_matrix[0x1]; 1145 u8 reserved_at_1[0x1f]; 1146 u8 reserved_at_20[0x8]; 1147 u8 max_vec_count[0x8]; 1148 u8 reserved_at_30[0xd]; 1149 u8 max_chunk_size[0x3]; 1150 struct mlx5_ifc_calc_op calc0; 1151 struct mlx5_ifc_calc_op calc1; 1152 struct mlx5_ifc_calc_op calc2; 1153 struct mlx5_ifc_calc_op calc3; 1154 1155 u8 reserved_at_c0[0x720]; 1156 }; 1157 1158 struct mlx5_ifc_tls_cap_bits { 1159 u8 tls_1_2_aes_gcm_128[0x1]; 1160 u8 tls_1_3_aes_gcm_128[0x1]; 1161 u8 tls_1_2_aes_gcm_256[0x1]; 1162 u8 tls_1_3_aes_gcm_256[0x1]; 1163 u8 reserved_at_4[0x1c]; 1164 1165 u8 reserved_at_20[0x7e0]; 1166 }; 1167 1168 struct mlx5_ifc_ipsec_cap_bits { 1169 u8 ipsec_full_offload[0x1]; 1170 u8 ipsec_crypto_offload[0x1]; 1171 u8 ipsec_esn[0x1]; 1172 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1173 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1174 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1175 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1176 u8 reserved_at_7[0x4]; 1177 u8 log_max_ipsec_offload[0x5]; 1178 u8 reserved_at_10[0x10]; 1179 1180 u8 min_log_ipsec_full_replay_window[0x8]; 1181 u8 max_log_ipsec_full_replay_window[0x8]; 1182 u8 reserved_at_30[0x7d0]; 1183 }; 1184 1185 enum { 1186 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1187 MLX5_WQ_TYPE_CYCLIC = 0x1, 1188 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1189 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1190 }; 1191 1192 enum { 1193 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1194 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1195 }; 1196 1197 enum { 1198 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1199 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1200 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1201 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1202 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1203 }; 1204 1205 enum { 1206 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1207 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1208 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1209 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1210 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1211 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1212 }; 1213 1214 enum { 1215 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1216 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1217 }; 1218 1219 enum { 1220 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1221 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1222 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1223 }; 1224 1225 enum { 1226 MLX5_CAP_PORT_TYPE_IB = 0x0, 1227 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1228 }; 1229 1230 enum { 1231 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1232 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1233 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1234 }; 1235 1236 enum { 1237 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1238 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1239 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1240 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1241 }; 1242 1243 enum { 1244 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1245 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1246 }; 1247 1248 #define MLX5_FC_BULK_SIZE_FACTOR 128 1249 1250 enum mlx5_fc_bulk_alloc_bitmask { 1251 MLX5_FC_BULK_128 = (1 << 0), 1252 MLX5_FC_BULK_256 = (1 << 1), 1253 MLX5_FC_BULK_512 = (1 << 2), 1254 MLX5_FC_BULK_1024 = (1 << 3), 1255 MLX5_FC_BULK_2048 = (1 << 4), 1256 MLX5_FC_BULK_4096 = (1 << 5), 1257 MLX5_FC_BULK_8192 = (1 << 6), 1258 MLX5_FC_BULK_16384 = (1 << 7), 1259 }; 1260 1261 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1262 1263 enum { 1264 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1265 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1266 }; 1267 1268 enum { 1269 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1270 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1271 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1272 }; 1273 1274 enum { 1275 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1276 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1277 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1278 }; 1279 1280 struct mlx5_ifc_cmd_hca_cap_bits { 1281 u8 reserved_at_0[0x1f]; 1282 u8 vhca_resource_manager[0x1]; 1283 1284 u8 reserved_at_20[0x3]; 1285 u8 event_on_vhca_state_teardown_request[0x1]; 1286 u8 event_on_vhca_state_in_use[0x1]; 1287 u8 event_on_vhca_state_active[0x1]; 1288 u8 event_on_vhca_state_allocated[0x1]; 1289 u8 event_on_vhca_state_invalid[0x1]; 1290 u8 reserved_at_28[0x8]; 1291 u8 vhca_id[0x10]; 1292 1293 u8 reserved_at_40[0x40]; 1294 1295 u8 log_max_srq_sz[0x8]; 1296 u8 log_max_qp_sz[0x8]; 1297 u8 event_cap[0x1]; 1298 u8 reserved_at_91[0x7]; 1299 u8 prio_tag_required[0x1]; 1300 u8 reserved_at_99[0x2]; 1301 u8 log_max_qp[0x5]; 1302 1303 u8 reserved_at_a0[0x3]; 1304 u8 ece_support[0x1]; 1305 u8 reserved_at_a4[0x5]; 1306 u8 reg_c_preserve[0x1]; 1307 u8 reserved_at_aa[0x1]; 1308 u8 log_max_srq[0x5]; 1309 u8 reserved_at_b0[0x1]; 1310 u8 uplink_follow[0x1]; 1311 u8 ts_cqe_to_dest_cqn[0x1]; 1312 u8 reserved_at_b3[0xd]; 1313 1314 u8 max_sgl_for_optimized_performance[0x8]; 1315 u8 log_max_cq_sz[0x8]; 1316 u8 relaxed_ordering_write_umr[0x1]; 1317 u8 relaxed_ordering_read_umr[0x1]; 1318 u8 reserved_at_d2[0x7]; 1319 u8 virtio_net_device_emualtion_manager[0x1]; 1320 u8 virtio_blk_device_emualtion_manager[0x1]; 1321 u8 log_max_cq[0x5]; 1322 1323 u8 log_max_eq_sz[0x8]; 1324 u8 relaxed_ordering_write[0x1]; 1325 u8 relaxed_ordering_read[0x1]; 1326 u8 log_max_mkey[0x6]; 1327 u8 reserved_at_f0[0x8]; 1328 u8 dump_fill_mkey[0x1]; 1329 u8 reserved_at_f9[0x2]; 1330 u8 fast_teardown[0x1]; 1331 u8 log_max_eq[0x4]; 1332 1333 u8 max_indirection[0x8]; 1334 u8 fixed_buffer_size[0x1]; 1335 u8 log_max_mrw_sz[0x7]; 1336 u8 force_teardown[0x1]; 1337 u8 reserved_at_111[0x1]; 1338 u8 log_max_bsf_list_size[0x6]; 1339 u8 umr_extended_translation_offset[0x1]; 1340 u8 null_mkey[0x1]; 1341 u8 log_max_klm_list_size[0x6]; 1342 1343 u8 reserved_at_120[0xa]; 1344 u8 log_max_ra_req_dc[0x6]; 1345 u8 reserved_at_130[0xa]; 1346 u8 log_max_ra_res_dc[0x6]; 1347 1348 u8 reserved_at_140[0x6]; 1349 u8 release_all_pages[0x1]; 1350 u8 reserved_at_147[0x2]; 1351 u8 roce_accl[0x1]; 1352 u8 log_max_ra_req_qp[0x6]; 1353 u8 reserved_at_150[0xa]; 1354 u8 log_max_ra_res_qp[0x6]; 1355 1356 u8 end_pad[0x1]; 1357 u8 cc_query_allowed[0x1]; 1358 u8 cc_modify_allowed[0x1]; 1359 u8 start_pad[0x1]; 1360 u8 cache_line_128byte[0x1]; 1361 u8 reserved_at_165[0x4]; 1362 u8 rts2rts_qp_counters_set_id[0x1]; 1363 u8 reserved_at_16a[0x2]; 1364 u8 vnic_env_int_rq_oob[0x1]; 1365 u8 sbcam_reg[0x1]; 1366 u8 reserved_at_16e[0x1]; 1367 u8 qcam_reg[0x1]; 1368 u8 gid_table_size[0x10]; 1369 1370 u8 out_of_seq_cnt[0x1]; 1371 u8 vport_counters[0x1]; 1372 u8 retransmission_q_counters[0x1]; 1373 u8 debug[0x1]; 1374 u8 modify_rq_counter_set_id[0x1]; 1375 u8 rq_delay_drop[0x1]; 1376 u8 max_qp_cnt[0xa]; 1377 u8 pkey_table_size[0x10]; 1378 1379 u8 vport_group_manager[0x1]; 1380 u8 vhca_group_manager[0x1]; 1381 u8 ib_virt[0x1]; 1382 u8 eth_virt[0x1]; 1383 u8 vnic_env_queue_counters[0x1]; 1384 u8 ets[0x1]; 1385 u8 nic_flow_table[0x1]; 1386 u8 eswitch_manager[0x1]; 1387 u8 device_memory[0x1]; 1388 u8 mcam_reg[0x1]; 1389 u8 pcam_reg[0x1]; 1390 u8 local_ca_ack_delay[0x5]; 1391 u8 port_module_event[0x1]; 1392 u8 enhanced_error_q_counters[0x1]; 1393 u8 ports_check[0x1]; 1394 u8 reserved_at_1b3[0x1]; 1395 u8 disable_link_up[0x1]; 1396 u8 beacon_led[0x1]; 1397 u8 port_type[0x2]; 1398 u8 num_ports[0x8]; 1399 1400 u8 reserved_at_1c0[0x1]; 1401 u8 pps[0x1]; 1402 u8 pps_modify[0x1]; 1403 u8 log_max_msg[0x5]; 1404 u8 reserved_at_1c8[0x4]; 1405 u8 max_tc[0x4]; 1406 u8 temp_warn_event[0x1]; 1407 u8 dcbx[0x1]; 1408 u8 general_notification_event[0x1]; 1409 u8 reserved_at_1d3[0x2]; 1410 u8 fpga[0x1]; 1411 u8 rol_s[0x1]; 1412 u8 rol_g[0x1]; 1413 u8 reserved_at_1d8[0x1]; 1414 u8 wol_s[0x1]; 1415 u8 wol_g[0x1]; 1416 u8 wol_a[0x1]; 1417 u8 wol_b[0x1]; 1418 u8 wol_m[0x1]; 1419 u8 wol_u[0x1]; 1420 u8 wol_p[0x1]; 1421 1422 u8 stat_rate_support[0x10]; 1423 u8 reserved_at_1f0[0x1]; 1424 u8 pci_sync_for_fw_update_event[0x1]; 1425 u8 reserved_at_1f2[0x6]; 1426 u8 init2_lag_tx_port_affinity[0x1]; 1427 u8 reserved_at_1fa[0x3]; 1428 u8 cqe_version[0x4]; 1429 1430 u8 compact_address_vector[0x1]; 1431 u8 striding_rq[0x1]; 1432 u8 reserved_at_202[0x1]; 1433 u8 ipoib_enhanced_offloads[0x1]; 1434 u8 ipoib_basic_offloads[0x1]; 1435 u8 reserved_at_205[0x1]; 1436 u8 repeated_block_disabled[0x1]; 1437 u8 umr_modify_entity_size_disabled[0x1]; 1438 u8 umr_modify_atomic_disabled[0x1]; 1439 u8 umr_indirect_mkey_disabled[0x1]; 1440 u8 umr_fence[0x2]; 1441 u8 dc_req_scat_data_cqe[0x1]; 1442 u8 reserved_at_20d[0x2]; 1443 u8 drain_sigerr[0x1]; 1444 u8 cmdif_checksum[0x2]; 1445 u8 sigerr_cqe[0x1]; 1446 u8 reserved_at_213[0x1]; 1447 u8 wq_signature[0x1]; 1448 u8 sctr_data_cqe[0x1]; 1449 u8 reserved_at_216[0x1]; 1450 u8 sho[0x1]; 1451 u8 tph[0x1]; 1452 u8 rf[0x1]; 1453 u8 dct[0x1]; 1454 u8 qos[0x1]; 1455 u8 eth_net_offloads[0x1]; 1456 u8 roce[0x1]; 1457 u8 atomic[0x1]; 1458 u8 reserved_at_21f[0x1]; 1459 1460 u8 cq_oi[0x1]; 1461 u8 cq_resize[0x1]; 1462 u8 cq_moderation[0x1]; 1463 u8 reserved_at_223[0x3]; 1464 u8 cq_eq_remap[0x1]; 1465 u8 pg[0x1]; 1466 u8 block_lb_mc[0x1]; 1467 u8 reserved_at_229[0x1]; 1468 u8 scqe_break_moderation[0x1]; 1469 u8 cq_period_start_from_cqe[0x1]; 1470 u8 cd[0x1]; 1471 u8 reserved_at_22d[0x1]; 1472 u8 apm[0x1]; 1473 u8 vector_calc[0x1]; 1474 u8 umr_ptr_rlky[0x1]; 1475 u8 imaicl[0x1]; 1476 u8 qp_packet_based[0x1]; 1477 u8 reserved_at_233[0x3]; 1478 u8 qkv[0x1]; 1479 u8 pkv[0x1]; 1480 u8 set_deth_sqpn[0x1]; 1481 u8 reserved_at_239[0x3]; 1482 u8 xrc[0x1]; 1483 u8 ud[0x1]; 1484 u8 uc[0x1]; 1485 u8 rc[0x1]; 1486 1487 u8 uar_4k[0x1]; 1488 u8 reserved_at_241[0x9]; 1489 u8 uar_sz[0x6]; 1490 u8 reserved_at_250[0x8]; 1491 u8 log_pg_sz[0x8]; 1492 1493 u8 bf[0x1]; 1494 u8 driver_version[0x1]; 1495 u8 pad_tx_eth_packet[0x1]; 1496 u8 reserved_at_263[0x3]; 1497 u8 mkey_by_name[0x1]; 1498 u8 reserved_at_267[0x4]; 1499 1500 u8 log_bf_reg_size[0x5]; 1501 1502 u8 reserved_at_270[0x6]; 1503 u8 lag_dct[0x2]; 1504 u8 lag_tx_port_affinity[0x1]; 1505 u8 reserved_at_279[0x2]; 1506 u8 lag_master[0x1]; 1507 u8 num_lag_ports[0x4]; 1508 1509 u8 reserved_at_280[0x10]; 1510 u8 max_wqe_sz_sq[0x10]; 1511 1512 u8 reserved_at_2a0[0x10]; 1513 u8 max_wqe_sz_rq[0x10]; 1514 1515 u8 max_flow_counter_31_16[0x10]; 1516 u8 max_wqe_sz_sq_dc[0x10]; 1517 1518 u8 reserved_at_2e0[0x7]; 1519 u8 max_qp_mcg[0x19]; 1520 1521 u8 reserved_at_300[0x10]; 1522 u8 flow_counter_bulk_alloc[0x8]; 1523 u8 log_max_mcg[0x8]; 1524 1525 u8 reserved_at_320[0x3]; 1526 u8 log_max_transport_domain[0x5]; 1527 u8 reserved_at_328[0x3]; 1528 u8 log_max_pd[0x5]; 1529 u8 reserved_at_330[0xb]; 1530 u8 log_max_xrcd[0x5]; 1531 1532 u8 nic_receive_steering_discard[0x1]; 1533 u8 receive_discard_vport_down[0x1]; 1534 u8 transmit_discard_vport_down[0x1]; 1535 u8 reserved_at_343[0x5]; 1536 u8 log_max_flow_counter_bulk[0x8]; 1537 u8 max_flow_counter_15_0[0x10]; 1538 1539 1540 u8 reserved_at_360[0x3]; 1541 u8 log_max_rq[0x5]; 1542 u8 reserved_at_368[0x3]; 1543 u8 log_max_sq[0x5]; 1544 u8 reserved_at_370[0x3]; 1545 u8 log_max_tir[0x5]; 1546 u8 reserved_at_378[0x3]; 1547 u8 log_max_tis[0x5]; 1548 1549 u8 basic_cyclic_rcv_wqe[0x1]; 1550 u8 reserved_at_381[0x2]; 1551 u8 log_max_rmp[0x5]; 1552 u8 reserved_at_388[0x3]; 1553 u8 log_max_rqt[0x5]; 1554 u8 reserved_at_390[0x3]; 1555 u8 log_max_rqt_size[0x5]; 1556 u8 reserved_at_398[0x3]; 1557 u8 log_max_tis_per_sq[0x5]; 1558 1559 u8 ext_stride_num_range[0x1]; 1560 u8 reserved_at_3a1[0x2]; 1561 u8 log_max_stride_sz_rq[0x5]; 1562 u8 reserved_at_3a8[0x3]; 1563 u8 log_min_stride_sz_rq[0x5]; 1564 u8 reserved_at_3b0[0x3]; 1565 u8 log_max_stride_sz_sq[0x5]; 1566 u8 reserved_at_3b8[0x3]; 1567 u8 log_min_stride_sz_sq[0x5]; 1568 1569 u8 hairpin[0x1]; 1570 u8 reserved_at_3c1[0x2]; 1571 u8 log_max_hairpin_queues[0x5]; 1572 u8 reserved_at_3c8[0x3]; 1573 u8 log_max_hairpin_wq_data_sz[0x5]; 1574 u8 reserved_at_3d0[0x3]; 1575 u8 log_max_hairpin_num_packets[0x5]; 1576 u8 reserved_at_3d8[0x3]; 1577 u8 log_max_wq_sz[0x5]; 1578 1579 u8 nic_vport_change_event[0x1]; 1580 u8 disable_local_lb_uc[0x1]; 1581 u8 disable_local_lb_mc[0x1]; 1582 u8 log_min_hairpin_wq_data_sz[0x5]; 1583 u8 reserved_at_3e8[0x2]; 1584 u8 vhca_state[0x1]; 1585 u8 log_max_vlan_list[0x5]; 1586 u8 reserved_at_3f0[0x3]; 1587 u8 log_max_current_mc_list[0x5]; 1588 u8 reserved_at_3f8[0x3]; 1589 u8 log_max_current_uc_list[0x5]; 1590 1591 u8 general_obj_types[0x40]; 1592 1593 u8 sq_ts_format[0x2]; 1594 u8 rq_ts_format[0x2]; 1595 u8 steering_format_version[0x4]; 1596 u8 create_qp_start_hint[0x18]; 1597 1598 u8 reserved_at_460[0x3]; 1599 u8 log_max_uctx[0x5]; 1600 u8 reserved_at_468[0x2]; 1601 u8 ipsec_offload[0x1]; 1602 u8 log_max_umem[0x5]; 1603 u8 max_num_eqs[0x10]; 1604 1605 u8 reserved_at_480[0x1]; 1606 u8 tls_tx[0x1]; 1607 u8 tls_rx[0x1]; 1608 u8 log_max_l2_table[0x5]; 1609 u8 reserved_at_488[0x8]; 1610 u8 log_uar_page_sz[0x10]; 1611 1612 u8 reserved_at_4a0[0x20]; 1613 u8 device_frequency_mhz[0x20]; 1614 u8 device_frequency_khz[0x20]; 1615 1616 u8 reserved_at_500[0x20]; 1617 u8 num_of_uars_per_page[0x20]; 1618 1619 u8 flex_parser_protocols[0x20]; 1620 1621 u8 max_geneve_tlv_options[0x8]; 1622 u8 reserved_at_568[0x3]; 1623 u8 max_geneve_tlv_option_data_len[0x5]; 1624 u8 reserved_at_570[0x10]; 1625 1626 u8 reserved_at_580[0x33]; 1627 u8 log_max_dek[0x5]; 1628 u8 reserved_at_5b8[0x4]; 1629 u8 mini_cqe_resp_stride_index[0x1]; 1630 u8 cqe_128_always[0x1]; 1631 u8 cqe_compression_128[0x1]; 1632 u8 cqe_compression[0x1]; 1633 1634 u8 cqe_compression_timeout[0x10]; 1635 u8 cqe_compression_max_num[0x10]; 1636 1637 u8 reserved_at_5e0[0x10]; 1638 u8 tag_matching[0x1]; 1639 u8 rndv_offload_rc[0x1]; 1640 u8 rndv_offload_dc[0x1]; 1641 u8 log_tag_matching_list_sz[0x5]; 1642 u8 reserved_at_5f8[0x3]; 1643 u8 log_max_xrq[0x5]; 1644 1645 u8 affiliate_nic_vport_criteria[0x8]; 1646 u8 native_port_num[0x8]; 1647 u8 num_vhca_ports[0x8]; 1648 u8 reserved_at_618[0x6]; 1649 u8 sw_owner_id[0x1]; 1650 u8 reserved_at_61f[0x1]; 1651 1652 u8 max_num_of_monitor_counters[0x10]; 1653 u8 num_ppcnt_monitor_counters[0x10]; 1654 1655 u8 max_num_sf[0x10]; 1656 u8 num_q_monitor_counters[0x10]; 1657 1658 u8 reserved_at_660[0x20]; 1659 1660 u8 sf[0x1]; 1661 u8 sf_set_partition[0x1]; 1662 u8 reserved_at_682[0x1]; 1663 u8 log_max_sf[0x5]; 1664 u8 apu[0x1]; 1665 u8 reserved_at_689[0x7]; 1666 u8 log_min_sf_size[0x8]; 1667 u8 max_num_sf_partitions[0x8]; 1668 1669 u8 uctx_cap[0x20]; 1670 1671 u8 reserved_at_6c0[0x4]; 1672 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1673 u8 flex_parser_id_icmp_dw1[0x4]; 1674 u8 flex_parser_id_icmp_dw0[0x4]; 1675 u8 flex_parser_id_icmpv6_dw1[0x4]; 1676 u8 flex_parser_id_icmpv6_dw0[0x4]; 1677 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1678 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1679 1680 u8 reserved_at_6e0[0x10]; 1681 u8 sf_base_id[0x10]; 1682 1683 u8 reserved_at_700[0x80]; 1684 u8 vhca_tunnel_commands[0x40]; 1685 u8 reserved_at_7c0[0x40]; 1686 }; 1687 1688 enum mlx5_flow_destination_type { 1689 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1690 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1691 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1692 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1693 1694 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1695 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1696 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1697 }; 1698 1699 enum mlx5_flow_table_miss_action { 1700 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1701 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1702 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1703 }; 1704 1705 struct mlx5_ifc_dest_format_struct_bits { 1706 u8 destination_type[0x8]; 1707 u8 destination_id[0x18]; 1708 1709 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1710 u8 packet_reformat[0x1]; 1711 u8 reserved_at_22[0xe]; 1712 u8 destination_eswitch_owner_vhca_id[0x10]; 1713 }; 1714 1715 struct mlx5_ifc_flow_counter_list_bits { 1716 u8 flow_counter_id[0x20]; 1717 1718 u8 reserved_at_20[0x20]; 1719 }; 1720 1721 struct mlx5_ifc_extended_dest_format_bits { 1722 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1723 1724 u8 packet_reformat_id[0x20]; 1725 1726 u8 reserved_at_60[0x20]; 1727 }; 1728 1729 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1730 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1731 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1732 }; 1733 1734 struct mlx5_ifc_fte_match_param_bits { 1735 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1736 1737 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1738 1739 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1740 1741 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1742 1743 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1744 1745 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1746 1747 u8 reserved_at_c00[0x400]; 1748 }; 1749 1750 enum { 1751 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1752 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1753 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1754 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1755 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1756 }; 1757 1758 struct mlx5_ifc_rx_hash_field_select_bits { 1759 u8 l3_prot_type[0x1]; 1760 u8 l4_prot_type[0x1]; 1761 u8 selected_fields[0x1e]; 1762 }; 1763 1764 enum { 1765 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1766 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1767 }; 1768 1769 enum { 1770 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1771 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1772 }; 1773 1774 struct mlx5_ifc_wq_bits { 1775 u8 wq_type[0x4]; 1776 u8 wq_signature[0x1]; 1777 u8 end_padding_mode[0x2]; 1778 u8 cd_slave[0x1]; 1779 u8 reserved_at_8[0x18]; 1780 1781 u8 hds_skip_first_sge[0x1]; 1782 u8 log2_hds_buf_size[0x3]; 1783 u8 reserved_at_24[0x7]; 1784 u8 page_offset[0x5]; 1785 u8 lwm[0x10]; 1786 1787 u8 reserved_at_40[0x8]; 1788 u8 pd[0x18]; 1789 1790 u8 reserved_at_60[0x8]; 1791 u8 uar_page[0x18]; 1792 1793 u8 dbr_addr[0x40]; 1794 1795 u8 hw_counter[0x20]; 1796 1797 u8 sw_counter[0x20]; 1798 1799 u8 reserved_at_100[0xc]; 1800 u8 log_wq_stride[0x4]; 1801 u8 reserved_at_110[0x3]; 1802 u8 log_wq_pg_sz[0x5]; 1803 u8 reserved_at_118[0x3]; 1804 u8 log_wq_sz[0x5]; 1805 1806 u8 dbr_umem_valid[0x1]; 1807 u8 wq_umem_valid[0x1]; 1808 u8 reserved_at_122[0x1]; 1809 u8 log_hairpin_num_packets[0x5]; 1810 u8 reserved_at_128[0x3]; 1811 u8 log_hairpin_data_sz[0x5]; 1812 1813 u8 reserved_at_130[0x4]; 1814 u8 log_wqe_num_of_strides[0x4]; 1815 u8 two_byte_shift_en[0x1]; 1816 u8 reserved_at_139[0x4]; 1817 u8 log_wqe_stride_size[0x3]; 1818 1819 u8 reserved_at_140[0x4c0]; 1820 1821 struct mlx5_ifc_cmd_pas_bits pas[]; 1822 }; 1823 1824 struct mlx5_ifc_rq_num_bits { 1825 u8 reserved_at_0[0x8]; 1826 u8 rq_num[0x18]; 1827 }; 1828 1829 struct mlx5_ifc_mac_address_layout_bits { 1830 u8 reserved_at_0[0x10]; 1831 u8 mac_addr_47_32[0x10]; 1832 1833 u8 mac_addr_31_0[0x20]; 1834 }; 1835 1836 struct mlx5_ifc_vlan_layout_bits { 1837 u8 reserved_at_0[0x14]; 1838 u8 vlan[0x0c]; 1839 1840 u8 reserved_at_20[0x20]; 1841 }; 1842 1843 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1844 u8 reserved_at_0[0xa0]; 1845 1846 u8 min_time_between_cnps[0x20]; 1847 1848 u8 reserved_at_c0[0x12]; 1849 u8 cnp_dscp[0x6]; 1850 u8 reserved_at_d8[0x4]; 1851 u8 cnp_prio_mode[0x1]; 1852 u8 cnp_802p_prio[0x3]; 1853 1854 u8 reserved_at_e0[0x720]; 1855 }; 1856 1857 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1858 u8 reserved_at_0[0x60]; 1859 1860 u8 reserved_at_60[0x4]; 1861 u8 clamp_tgt_rate[0x1]; 1862 u8 reserved_at_65[0x3]; 1863 u8 clamp_tgt_rate_after_time_inc[0x1]; 1864 u8 reserved_at_69[0x17]; 1865 1866 u8 reserved_at_80[0x20]; 1867 1868 u8 rpg_time_reset[0x20]; 1869 1870 u8 rpg_byte_reset[0x20]; 1871 1872 u8 rpg_threshold[0x20]; 1873 1874 u8 rpg_max_rate[0x20]; 1875 1876 u8 rpg_ai_rate[0x20]; 1877 1878 u8 rpg_hai_rate[0x20]; 1879 1880 u8 rpg_gd[0x20]; 1881 1882 u8 rpg_min_dec_fac[0x20]; 1883 1884 u8 rpg_min_rate[0x20]; 1885 1886 u8 reserved_at_1c0[0xe0]; 1887 1888 u8 rate_to_set_on_first_cnp[0x20]; 1889 1890 u8 dce_tcp_g[0x20]; 1891 1892 u8 dce_tcp_rtt[0x20]; 1893 1894 u8 rate_reduce_monitor_period[0x20]; 1895 1896 u8 reserved_at_320[0x20]; 1897 1898 u8 initial_alpha_value[0x20]; 1899 1900 u8 reserved_at_360[0x4a0]; 1901 }; 1902 1903 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1904 u8 reserved_at_0[0x80]; 1905 1906 u8 rppp_max_rps[0x20]; 1907 1908 u8 rpg_time_reset[0x20]; 1909 1910 u8 rpg_byte_reset[0x20]; 1911 1912 u8 rpg_threshold[0x20]; 1913 1914 u8 rpg_max_rate[0x20]; 1915 1916 u8 rpg_ai_rate[0x20]; 1917 1918 u8 rpg_hai_rate[0x20]; 1919 1920 u8 rpg_gd[0x20]; 1921 1922 u8 rpg_min_dec_fac[0x20]; 1923 1924 u8 rpg_min_rate[0x20]; 1925 1926 u8 reserved_at_1c0[0x640]; 1927 }; 1928 1929 enum { 1930 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1931 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1932 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1933 }; 1934 1935 struct mlx5_ifc_resize_field_select_bits { 1936 u8 resize_field_select[0x20]; 1937 }; 1938 1939 struct mlx5_ifc_resource_dump_bits { 1940 u8 more_dump[0x1]; 1941 u8 inline_dump[0x1]; 1942 u8 reserved_at_2[0xa]; 1943 u8 seq_num[0x4]; 1944 u8 segment_type[0x10]; 1945 1946 u8 reserved_at_20[0x10]; 1947 u8 vhca_id[0x10]; 1948 1949 u8 index1[0x20]; 1950 1951 u8 index2[0x20]; 1952 1953 u8 num_of_obj1[0x10]; 1954 u8 num_of_obj2[0x10]; 1955 1956 u8 reserved_at_a0[0x20]; 1957 1958 u8 device_opaque[0x40]; 1959 1960 u8 mkey[0x20]; 1961 1962 u8 size[0x20]; 1963 1964 u8 address[0x40]; 1965 1966 u8 inline_data[52][0x20]; 1967 }; 1968 1969 struct mlx5_ifc_resource_dump_menu_record_bits { 1970 u8 reserved_at_0[0x4]; 1971 u8 num_of_obj2_supports_active[0x1]; 1972 u8 num_of_obj2_supports_all[0x1]; 1973 u8 must_have_num_of_obj2[0x1]; 1974 u8 support_num_of_obj2[0x1]; 1975 u8 num_of_obj1_supports_active[0x1]; 1976 u8 num_of_obj1_supports_all[0x1]; 1977 u8 must_have_num_of_obj1[0x1]; 1978 u8 support_num_of_obj1[0x1]; 1979 u8 must_have_index2[0x1]; 1980 u8 support_index2[0x1]; 1981 u8 must_have_index1[0x1]; 1982 u8 support_index1[0x1]; 1983 u8 segment_type[0x10]; 1984 1985 u8 segment_name[4][0x20]; 1986 1987 u8 index1_name[4][0x20]; 1988 1989 u8 index2_name[4][0x20]; 1990 }; 1991 1992 struct mlx5_ifc_resource_dump_segment_header_bits { 1993 u8 length_dw[0x10]; 1994 u8 segment_type[0x10]; 1995 }; 1996 1997 struct mlx5_ifc_resource_dump_command_segment_bits { 1998 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1999 2000 u8 segment_called[0x10]; 2001 u8 vhca_id[0x10]; 2002 2003 u8 index1[0x20]; 2004 2005 u8 index2[0x20]; 2006 2007 u8 num_of_obj1[0x10]; 2008 u8 num_of_obj2[0x10]; 2009 }; 2010 2011 struct mlx5_ifc_resource_dump_error_segment_bits { 2012 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2013 2014 u8 reserved_at_20[0x10]; 2015 u8 syndrome_id[0x10]; 2016 2017 u8 reserved_at_40[0x40]; 2018 2019 u8 error[8][0x20]; 2020 }; 2021 2022 struct mlx5_ifc_resource_dump_info_segment_bits { 2023 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2024 2025 u8 reserved_at_20[0x18]; 2026 u8 dump_version[0x8]; 2027 2028 u8 hw_version[0x20]; 2029 2030 u8 fw_version[0x20]; 2031 }; 2032 2033 struct mlx5_ifc_resource_dump_menu_segment_bits { 2034 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2035 2036 u8 reserved_at_20[0x10]; 2037 u8 num_of_records[0x10]; 2038 2039 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2040 }; 2041 2042 struct mlx5_ifc_resource_dump_resource_segment_bits { 2043 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2044 2045 u8 reserved_at_20[0x20]; 2046 2047 u8 index1[0x20]; 2048 2049 u8 index2[0x20]; 2050 2051 u8 payload[][0x20]; 2052 }; 2053 2054 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2055 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2056 }; 2057 2058 struct mlx5_ifc_menu_resource_dump_response_bits { 2059 struct mlx5_ifc_resource_dump_info_segment_bits info; 2060 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2061 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2062 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2063 }; 2064 2065 enum { 2066 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2067 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2068 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2069 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2070 }; 2071 2072 struct mlx5_ifc_modify_field_select_bits { 2073 u8 modify_field_select[0x20]; 2074 }; 2075 2076 struct mlx5_ifc_field_select_r_roce_np_bits { 2077 u8 field_select_r_roce_np[0x20]; 2078 }; 2079 2080 struct mlx5_ifc_field_select_r_roce_rp_bits { 2081 u8 field_select_r_roce_rp[0x20]; 2082 }; 2083 2084 enum { 2085 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2086 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2087 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2088 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2089 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2090 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2091 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2092 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2093 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2094 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2095 }; 2096 2097 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2098 u8 field_select_8021qaurp[0x20]; 2099 }; 2100 2101 struct mlx5_ifc_phys_layer_cntrs_bits { 2102 u8 time_since_last_clear_high[0x20]; 2103 2104 u8 time_since_last_clear_low[0x20]; 2105 2106 u8 symbol_errors_high[0x20]; 2107 2108 u8 symbol_errors_low[0x20]; 2109 2110 u8 sync_headers_errors_high[0x20]; 2111 2112 u8 sync_headers_errors_low[0x20]; 2113 2114 u8 edpl_bip_errors_lane0_high[0x20]; 2115 2116 u8 edpl_bip_errors_lane0_low[0x20]; 2117 2118 u8 edpl_bip_errors_lane1_high[0x20]; 2119 2120 u8 edpl_bip_errors_lane1_low[0x20]; 2121 2122 u8 edpl_bip_errors_lane2_high[0x20]; 2123 2124 u8 edpl_bip_errors_lane2_low[0x20]; 2125 2126 u8 edpl_bip_errors_lane3_high[0x20]; 2127 2128 u8 edpl_bip_errors_lane3_low[0x20]; 2129 2130 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2131 2132 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2133 2134 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2135 2136 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2137 2138 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2139 2140 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2141 2142 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2143 2144 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2145 2146 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2147 2148 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2149 2150 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2151 2152 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2153 2154 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2155 2156 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2157 2158 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2159 2160 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2161 2162 u8 rs_fec_corrected_blocks_high[0x20]; 2163 2164 u8 rs_fec_corrected_blocks_low[0x20]; 2165 2166 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2167 2168 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2169 2170 u8 rs_fec_no_errors_blocks_high[0x20]; 2171 2172 u8 rs_fec_no_errors_blocks_low[0x20]; 2173 2174 u8 rs_fec_single_error_blocks_high[0x20]; 2175 2176 u8 rs_fec_single_error_blocks_low[0x20]; 2177 2178 u8 rs_fec_corrected_symbols_total_high[0x20]; 2179 2180 u8 rs_fec_corrected_symbols_total_low[0x20]; 2181 2182 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2183 2184 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2185 2186 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2187 2188 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2189 2190 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2191 2192 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2193 2194 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2195 2196 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2197 2198 u8 link_down_events[0x20]; 2199 2200 u8 successful_recovery_events[0x20]; 2201 2202 u8 reserved_at_640[0x180]; 2203 }; 2204 2205 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2206 u8 time_since_last_clear_high[0x20]; 2207 2208 u8 time_since_last_clear_low[0x20]; 2209 2210 u8 phy_received_bits_high[0x20]; 2211 2212 u8 phy_received_bits_low[0x20]; 2213 2214 u8 phy_symbol_errors_high[0x20]; 2215 2216 u8 phy_symbol_errors_low[0x20]; 2217 2218 u8 phy_corrected_bits_high[0x20]; 2219 2220 u8 phy_corrected_bits_low[0x20]; 2221 2222 u8 phy_corrected_bits_lane0_high[0x20]; 2223 2224 u8 phy_corrected_bits_lane0_low[0x20]; 2225 2226 u8 phy_corrected_bits_lane1_high[0x20]; 2227 2228 u8 phy_corrected_bits_lane1_low[0x20]; 2229 2230 u8 phy_corrected_bits_lane2_high[0x20]; 2231 2232 u8 phy_corrected_bits_lane2_low[0x20]; 2233 2234 u8 phy_corrected_bits_lane3_high[0x20]; 2235 2236 u8 phy_corrected_bits_lane3_low[0x20]; 2237 2238 u8 reserved_at_200[0x5c0]; 2239 }; 2240 2241 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2242 u8 symbol_error_counter[0x10]; 2243 2244 u8 link_error_recovery_counter[0x8]; 2245 2246 u8 link_downed_counter[0x8]; 2247 2248 u8 port_rcv_errors[0x10]; 2249 2250 u8 port_rcv_remote_physical_errors[0x10]; 2251 2252 u8 port_rcv_switch_relay_errors[0x10]; 2253 2254 u8 port_xmit_discards[0x10]; 2255 2256 u8 port_xmit_constraint_errors[0x8]; 2257 2258 u8 port_rcv_constraint_errors[0x8]; 2259 2260 u8 reserved_at_70[0x8]; 2261 2262 u8 link_overrun_errors[0x8]; 2263 2264 u8 reserved_at_80[0x10]; 2265 2266 u8 vl_15_dropped[0x10]; 2267 2268 u8 reserved_at_a0[0x80]; 2269 2270 u8 port_xmit_wait[0x20]; 2271 }; 2272 2273 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2274 u8 transmit_queue_high[0x20]; 2275 2276 u8 transmit_queue_low[0x20]; 2277 2278 u8 no_buffer_discard_uc_high[0x20]; 2279 2280 u8 no_buffer_discard_uc_low[0x20]; 2281 2282 u8 reserved_at_80[0x740]; 2283 }; 2284 2285 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2286 u8 wred_discard_high[0x20]; 2287 2288 u8 wred_discard_low[0x20]; 2289 2290 u8 ecn_marked_tc_high[0x20]; 2291 2292 u8 ecn_marked_tc_low[0x20]; 2293 2294 u8 reserved_at_80[0x740]; 2295 }; 2296 2297 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2298 u8 rx_octets_high[0x20]; 2299 2300 u8 rx_octets_low[0x20]; 2301 2302 u8 reserved_at_40[0xc0]; 2303 2304 u8 rx_frames_high[0x20]; 2305 2306 u8 rx_frames_low[0x20]; 2307 2308 u8 tx_octets_high[0x20]; 2309 2310 u8 tx_octets_low[0x20]; 2311 2312 u8 reserved_at_180[0xc0]; 2313 2314 u8 tx_frames_high[0x20]; 2315 2316 u8 tx_frames_low[0x20]; 2317 2318 u8 rx_pause_high[0x20]; 2319 2320 u8 rx_pause_low[0x20]; 2321 2322 u8 rx_pause_duration_high[0x20]; 2323 2324 u8 rx_pause_duration_low[0x20]; 2325 2326 u8 tx_pause_high[0x20]; 2327 2328 u8 tx_pause_low[0x20]; 2329 2330 u8 tx_pause_duration_high[0x20]; 2331 2332 u8 tx_pause_duration_low[0x20]; 2333 2334 u8 rx_pause_transition_high[0x20]; 2335 2336 u8 rx_pause_transition_low[0x20]; 2337 2338 u8 rx_discards_high[0x20]; 2339 2340 u8 rx_discards_low[0x20]; 2341 2342 u8 device_stall_minor_watermark_cnt_high[0x20]; 2343 2344 u8 device_stall_minor_watermark_cnt_low[0x20]; 2345 2346 u8 device_stall_critical_watermark_cnt_high[0x20]; 2347 2348 u8 device_stall_critical_watermark_cnt_low[0x20]; 2349 2350 u8 reserved_at_480[0x340]; 2351 }; 2352 2353 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2354 u8 port_transmit_wait_high[0x20]; 2355 2356 u8 port_transmit_wait_low[0x20]; 2357 2358 u8 reserved_at_40[0x100]; 2359 2360 u8 rx_buffer_almost_full_high[0x20]; 2361 2362 u8 rx_buffer_almost_full_low[0x20]; 2363 2364 u8 rx_buffer_full_high[0x20]; 2365 2366 u8 rx_buffer_full_low[0x20]; 2367 2368 u8 rx_icrc_encapsulated_high[0x20]; 2369 2370 u8 rx_icrc_encapsulated_low[0x20]; 2371 2372 u8 reserved_at_200[0x5c0]; 2373 }; 2374 2375 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2376 u8 dot3stats_alignment_errors_high[0x20]; 2377 2378 u8 dot3stats_alignment_errors_low[0x20]; 2379 2380 u8 dot3stats_fcs_errors_high[0x20]; 2381 2382 u8 dot3stats_fcs_errors_low[0x20]; 2383 2384 u8 dot3stats_single_collision_frames_high[0x20]; 2385 2386 u8 dot3stats_single_collision_frames_low[0x20]; 2387 2388 u8 dot3stats_multiple_collision_frames_high[0x20]; 2389 2390 u8 dot3stats_multiple_collision_frames_low[0x20]; 2391 2392 u8 dot3stats_sqe_test_errors_high[0x20]; 2393 2394 u8 dot3stats_sqe_test_errors_low[0x20]; 2395 2396 u8 dot3stats_deferred_transmissions_high[0x20]; 2397 2398 u8 dot3stats_deferred_transmissions_low[0x20]; 2399 2400 u8 dot3stats_late_collisions_high[0x20]; 2401 2402 u8 dot3stats_late_collisions_low[0x20]; 2403 2404 u8 dot3stats_excessive_collisions_high[0x20]; 2405 2406 u8 dot3stats_excessive_collisions_low[0x20]; 2407 2408 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2409 2410 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2411 2412 u8 dot3stats_carrier_sense_errors_high[0x20]; 2413 2414 u8 dot3stats_carrier_sense_errors_low[0x20]; 2415 2416 u8 dot3stats_frame_too_longs_high[0x20]; 2417 2418 u8 dot3stats_frame_too_longs_low[0x20]; 2419 2420 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2421 2422 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2423 2424 u8 dot3stats_symbol_errors_high[0x20]; 2425 2426 u8 dot3stats_symbol_errors_low[0x20]; 2427 2428 u8 dot3control_in_unknown_opcodes_high[0x20]; 2429 2430 u8 dot3control_in_unknown_opcodes_low[0x20]; 2431 2432 u8 dot3in_pause_frames_high[0x20]; 2433 2434 u8 dot3in_pause_frames_low[0x20]; 2435 2436 u8 dot3out_pause_frames_high[0x20]; 2437 2438 u8 dot3out_pause_frames_low[0x20]; 2439 2440 u8 reserved_at_400[0x3c0]; 2441 }; 2442 2443 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2444 u8 ether_stats_drop_events_high[0x20]; 2445 2446 u8 ether_stats_drop_events_low[0x20]; 2447 2448 u8 ether_stats_octets_high[0x20]; 2449 2450 u8 ether_stats_octets_low[0x20]; 2451 2452 u8 ether_stats_pkts_high[0x20]; 2453 2454 u8 ether_stats_pkts_low[0x20]; 2455 2456 u8 ether_stats_broadcast_pkts_high[0x20]; 2457 2458 u8 ether_stats_broadcast_pkts_low[0x20]; 2459 2460 u8 ether_stats_multicast_pkts_high[0x20]; 2461 2462 u8 ether_stats_multicast_pkts_low[0x20]; 2463 2464 u8 ether_stats_crc_align_errors_high[0x20]; 2465 2466 u8 ether_stats_crc_align_errors_low[0x20]; 2467 2468 u8 ether_stats_undersize_pkts_high[0x20]; 2469 2470 u8 ether_stats_undersize_pkts_low[0x20]; 2471 2472 u8 ether_stats_oversize_pkts_high[0x20]; 2473 2474 u8 ether_stats_oversize_pkts_low[0x20]; 2475 2476 u8 ether_stats_fragments_high[0x20]; 2477 2478 u8 ether_stats_fragments_low[0x20]; 2479 2480 u8 ether_stats_jabbers_high[0x20]; 2481 2482 u8 ether_stats_jabbers_low[0x20]; 2483 2484 u8 ether_stats_collisions_high[0x20]; 2485 2486 u8 ether_stats_collisions_low[0x20]; 2487 2488 u8 ether_stats_pkts64octets_high[0x20]; 2489 2490 u8 ether_stats_pkts64octets_low[0x20]; 2491 2492 u8 ether_stats_pkts65to127octets_high[0x20]; 2493 2494 u8 ether_stats_pkts65to127octets_low[0x20]; 2495 2496 u8 ether_stats_pkts128to255octets_high[0x20]; 2497 2498 u8 ether_stats_pkts128to255octets_low[0x20]; 2499 2500 u8 ether_stats_pkts256to511octets_high[0x20]; 2501 2502 u8 ether_stats_pkts256to511octets_low[0x20]; 2503 2504 u8 ether_stats_pkts512to1023octets_high[0x20]; 2505 2506 u8 ether_stats_pkts512to1023octets_low[0x20]; 2507 2508 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2509 2510 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2511 2512 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2513 2514 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2515 2516 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2517 2518 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2519 2520 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2521 2522 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2523 2524 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2525 2526 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2527 2528 u8 reserved_at_540[0x280]; 2529 }; 2530 2531 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2532 u8 if_in_octets_high[0x20]; 2533 2534 u8 if_in_octets_low[0x20]; 2535 2536 u8 if_in_ucast_pkts_high[0x20]; 2537 2538 u8 if_in_ucast_pkts_low[0x20]; 2539 2540 u8 if_in_discards_high[0x20]; 2541 2542 u8 if_in_discards_low[0x20]; 2543 2544 u8 if_in_errors_high[0x20]; 2545 2546 u8 if_in_errors_low[0x20]; 2547 2548 u8 if_in_unknown_protos_high[0x20]; 2549 2550 u8 if_in_unknown_protos_low[0x20]; 2551 2552 u8 if_out_octets_high[0x20]; 2553 2554 u8 if_out_octets_low[0x20]; 2555 2556 u8 if_out_ucast_pkts_high[0x20]; 2557 2558 u8 if_out_ucast_pkts_low[0x20]; 2559 2560 u8 if_out_discards_high[0x20]; 2561 2562 u8 if_out_discards_low[0x20]; 2563 2564 u8 if_out_errors_high[0x20]; 2565 2566 u8 if_out_errors_low[0x20]; 2567 2568 u8 if_in_multicast_pkts_high[0x20]; 2569 2570 u8 if_in_multicast_pkts_low[0x20]; 2571 2572 u8 if_in_broadcast_pkts_high[0x20]; 2573 2574 u8 if_in_broadcast_pkts_low[0x20]; 2575 2576 u8 if_out_multicast_pkts_high[0x20]; 2577 2578 u8 if_out_multicast_pkts_low[0x20]; 2579 2580 u8 if_out_broadcast_pkts_high[0x20]; 2581 2582 u8 if_out_broadcast_pkts_low[0x20]; 2583 2584 u8 reserved_at_340[0x480]; 2585 }; 2586 2587 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2588 u8 a_frames_transmitted_ok_high[0x20]; 2589 2590 u8 a_frames_transmitted_ok_low[0x20]; 2591 2592 u8 a_frames_received_ok_high[0x20]; 2593 2594 u8 a_frames_received_ok_low[0x20]; 2595 2596 u8 a_frame_check_sequence_errors_high[0x20]; 2597 2598 u8 a_frame_check_sequence_errors_low[0x20]; 2599 2600 u8 a_alignment_errors_high[0x20]; 2601 2602 u8 a_alignment_errors_low[0x20]; 2603 2604 u8 a_octets_transmitted_ok_high[0x20]; 2605 2606 u8 a_octets_transmitted_ok_low[0x20]; 2607 2608 u8 a_octets_received_ok_high[0x20]; 2609 2610 u8 a_octets_received_ok_low[0x20]; 2611 2612 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2613 2614 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2615 2616 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2617 2618 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2619 2620 u8 a_multicast_frames_received_ok_high[0x20]; 2621 2622 u8 a_multicast_frames_received_ok_low[0x20]; 2623 2624 u8 a_broadcast_frames_received_ok_high[0x20]; 2625 2626 u8 a_broadcast_frames_received_ok_low[0x20]; 2627 2628 u8 a_in_range_length_errors_high[0x20]; 2629 2630 u8 a_in_range_length_errors_low[0x20]; 2631 2632 u8 a_out_of_range_length_field_high[0x20]; 2633 2634 u8 a_out_of_range_length_field_low[0x20]; 2635 2636 u8 a_frame_too_long_errors_high[0x20]; 2637 2638 u8 a_frame_too_long_errors_low[0x20]; 2639 2640 u8 a_symbol_error_during_carrier_high[0x20]; 2641 2642 u8 a_symbol_error_during_carrier_low[0x20]; 2643 2644 u8 a_mac_control_frames_transmitted_high[0x20]; 2645 2646 u8 a_mac_control_frames_transmitted_low[0x20]; 2647 2648 u8 a_mac_control_frames_received_high[0x20]; 2649 2650 u8 a_mac_control_frames_received_low[0x20]; 2651 2652 u8 a_unsupported_opcodes_received_high[0x20]; 2653 2654 u8 a_unsupported_opcodes_received_low[0x20]; 2655 2656 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2657 2658 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2659 2660 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2661 2662 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2663 2664 u8 reserved_at_4c0[0x300]; 2665 }; 2666 2667 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2668 u8 life_time_counter_high[0x20]; 2669 2670 u8 life_time_counter_low[0x20]; 2671 2672 u8 rx_errors[0x20]; 2673 2674 u8 tx_errors[0x20]; 2675 2676 u8 l0_to_recovery_eieos[0x20]; 2677 2678 u8 l0_to_recovery_ts[0x20]; 2679 2680 u8 l0_to_recovery_framing[0x20]; 2681 2682 u8 l0_to_recovery_retrain[0x20]; 2683 2684 u8 crc_error_dllp[0x20]; 2685 2686 u8 crc_error_tlp[0x20]; 2687 2688 u8 tx_overflow_buffer_pkt_high[0x20]; 2689 2690 u8 tx_overflow_buffer_pkt_low[0x20]; 2691 2692 u8 outbound_stalled_reads[0x20]; 2693 2694 u8 outbound_stalled_writes[0x20]; 2695 2696 u8 outbound_stalled_reads_events[0x20]; 2697 2698 u8 outbound_stalled_writes_events[0x20]; 2699 2700 u8 reserved_at_200[0x5c0]; 2701 }; 2702 2703 struct mlx5_ifc_cmd_inter_comp_event_bits { 2704 u8 command_completion_vector[0x20]; 2705 2706 u8 reserved_at_20[0xc0]; 2707 }; 2708 2709 struct mlx5_ifc_stall_vl_event_bits { 2710 u8 reserved_at_0[0x18]; 2711 u8 port_num[0x1]; 2712 u8 reserved_at_19[0x3]; 2713 u8 vl[0x4]; 2714 2715 u8 reserved_at_20[0xa0]; 2716 }; 2717 2718 struct mlx5_ifc_db_bf_congestion_event_bits { 2719 u8 event_subtype[0x8]; 2720 u8 reserved_at_8[0x8]; 2721 u8 congestion_level[0x8]; 2722 u8 reserved_at_18[0x8]; 2723 2724 u8 reserved_at_20[0xa0]; 2725 }; 2726 2727 struct mlx5_ifc_gpio_event_bits { 2728 u8 reserved_at_0[0x60]; 2729 2730 u8 gpio_event_hi[0x20]; 2731 2732 u8 gpio_event_lo[0x20]; 2733 2734 u8 reserved_at_a0[0x40]; 2735 }; 2736 2737 struct mlx5_ifc_port_state_change_event_bits { 2738 u8 reserved_at_0[0x40]; 2739 2740 u8 port_num[0x4]; 2741 u8 reserved_at_44[0x1c]; 2742 2743 u8 reserved_at_60[0x80]; 2744 }; 2745 2746 struct mlx5_ifc_dropped_packet_logged_bits { 2747 u8 reserved_at_0[0xe0]; 2748 }; 2749 2750 enum { 2751 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2752 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2753 }; 2754 2755 struct mlx5_ifc_cq_error_bits { 2756 u8 reserved_at_0[0x8]; 2757 u8 cqn[0x18]; 2758 2759 u8 reserved_at_20[0x20]; 2760 2761 u8 reserved_at_40[0x18]; 2762 u8 syndrome[0x8]; 2763 2764 u8 reserved_at_60[0x80]; 2765 }; 2766 2767 struct mlx5_ifc_rdma_page_fault_event_bits { 2768 u8 bytes_committed[0x20]; 2769 2770 u8 r_key[0x20]; 2771 2772 u8 reserved_at_40[0x10]; 2773 u8 packet_len[0x10]; 2774 2775 u8 rdma_op_len[0x20]; 2776 2777 u8 rdma_va[0x40]; 2778 2779 u8 reserved_at_c0[0x5]; 2780 u8 rdma[0x1]; 2781 u8 write[0x1]; 2782 u8 requestor[0x1]; 2783 u8 qp_number[0x18]; 2784 }; 2785 2786 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2787 u8 bytes_committed[0x20]; 2788 2789 u8 reserved_at_20[0x10]; 2790 u8 wqe_index[0x10]; 2791 2792 u8 reserved_at_40[0x10]; 2793 u8 len[0x10]; 2794 2795 u8 reserved_at_60[0x60]; 2796 2797 u8 reserved_at_c0[0x5]; 2798 u8 rdma[0x1]; 2799 u8 write_read[0x1]; 2800 u8 requestor[0x1]; 2801 u8 qpn[0x18]; 2802 }; 2803 2804 struct mlx5_ifc_qp_events_bits { 2805 u8 reserved_at_0[0xa0]; 2806 2807 u8 type[0x8]; 2808 u8 reserved_at_a8[0x18]; 2809 2810 u8 reserved_at_c0[0x8]; 2811 u8 qpn_rqn_sqn[0x18]; 2812 }; 2813 2814 struct mlx5_ifc_dct_events_bits { 2815 u8 reserved_at_0[0xc0]; 2816 2817 u8 reserved_at_c0[0x8]; 2818 u8 dct_number[0x18]; 2819 }; 2820 2821 struct mlx5_ifc_comp_event_bits { 2822 u8 reserved_at_0[0xc0]; 2823 2824 u8 reserved_at_c0[0x8]; 2825 u8 cq_number[0x18]; 2826 }; 2827 2828 enum { 2829 MLX5_QPC_STATE_RST = 0x0, 2830 MLX5_QPC_STATE_INIT = 0x1, 2831 MLX5_QPC_STATE_RTR = 0x2, 2832 MLX5_QPC_STATE_RTS = 0x3, 2833 MLX5_QPC_STATE_SQER = 0x4, 2834 MLX5_QPC_STATE_ERR = 0x6, 2835 MLX5_QPC_STATE_SQD = 0x7, 2836 MLX5_QPC_STATE_SUSPENDED = 0x9, 2837 }; 2838 2839 enum { 2840 MLX5_QPC_ST_RC = 0x0, 2841 MLX5_QPC_ST_UC = 0x1, 2842 MLX5_QPC_ST_UD = 0x2, 2843 MLX5_QPC_ST_XRC = 0x3, 2844 MLX5_QPC_ST_DCI = 0x5, 2845 MLX5_QPC_ST_QP0 = 0x7, 2846 MLX5_QPC_ST_QP1 = 0x8, 2847 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2848 MLX5_QPC_ST_REG_UMR = 0xc, 2849 }; 2850 2851 enum { 2852 MLX5_QPC_PM_STATE_ARMED = 0x0, 2853 MLX5_QPC_PM_STATE_REARM = 0x1, 2854 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2855 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2856 }; 2857 2858 enum { 2859 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2860 }; 2861 2862 enum { 2863 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2864 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2865 }; 2866 2867 enum { 2868 MLX5_QPC_MTU_256_BYTES = 0x1, 2869 MLX5_QPC_MTU_512_BYTES = 0x2, 2870 MLX5_QPC_MTU_1K_BYTES = 0x3, 2871 MLX5_QPC_MTU_2K_BYTES = 0x4, 2872 MLX5_QPC_MTU_4K_BYTES = 0x5, 2873 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2874 }; 2875 2876 enum { 2877 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2878 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2879 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2880 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2881 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2882 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2883 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2884 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2885 }; 2886 2887 enum { 2888 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2889 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2890 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2891 }; 2892 2893 enum { 2894 MLX5_QPC_CS_RES_DISABLE = 0x0, 2895 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2896 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2897 }; 2898 2899 enum { 2900 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2901 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2902 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2903 }; 2904 2905 struct mlx5_ifc_qpc_bits { 2906 u8 state[0x4]; 2907 u8 lag_tx_port_affinity[0x4]; 2908 u8 st[0x8]; 2909 u8 reserved_at_10[0x3]; 2910 u8 pm_state[0x2]; 2911 u8 reserved_at_15[0x1]; 2912 u8 req_e2e_credit_mode[0x2]; 2913 u8 offload_type[0x4]; 2914 u8 end_padding_mode[0x2]; 2915 u8 reserved_at_1e[0x2]; 2916 2917 u8 wq_signature[0x1]; 2918 u8 block_lb_mc[0x1]; 2919 u8 atomic_like_write_en[0x1]; 2920 u8 latency_sensitive[0x1]; 2921 u8 reserved_at_24[0x1]; 2922 u8 drain_sigerr[0x1]; 2923 u8 reserved_at_26[0x2]; 2924 u8 pd[0x18]; 2925 2926 u8 mtu[0x3]; 2927 u8 log_msg_max[0x5]; 2928 u8 reserved_at_48[0x1]; 2929 u8 log_rq_size[0x4]; 2930 u8 log_rq_stride[0x3]; 2931 u8 no_sq[0x1]; 2932 u8 log_sq_size[0x4]; 2933 u8 reserved_at_55[0x3]; 2934 u8 ts_format[0x2]; 2935 u8 reserved_at_5a[0x1]; 2936 u8 rlky[0x1]; 2937 u8 ulp_stateless_offload_mode[0x4]; 2938 2939 u8 counter_set_id[0x8]; 2940 u8 uar_page[0x18]; 2941 2942 u8 reserved_at_80[0x8]; 2943 u8 user_index[0x18]; 2944 2945 u8 reserved_at_a0[0x3]; 2946 u8 log_page_size[0x5]; 2947 u8 remote_qpn[0x18]; 2948 2949 struct mlx5_ifc_ads_bits primary_address_path; 2950 2951 struct mlx5_ifc_ads_bits secondary_address_path; 2952 2953 u8 log_ack_req_freq[0x4]; 2954 u8 reserved_at_384[0x4]; 2955 u8 log_sra_max[0x3]; 2956 u8 reserved_at_38b[0x2]; 2957 u8 retry_count[0x3]; 2958 u8 rnr_retry[0x3]; 2959 u8 reserved_at_393[0x1]; 2960 u8 fre[0x1]; 2961 u8 cur_rnr_retry[0x3]; 2962 u8 cur_retry_count[0x3]; 2963 u8 reserved_at_39b[0x5]; 2964 2965 u8 reserved_at_3a0[0x20]; 2966 2967 u8 reserved_at_3c0[0x8]; 2968 u8 next_send_psn[0x18]; 2969 2970 u8 reserved_at_3e0[0x8]; 2971 u8 cqn_snd[0x18]; 2972 2973 u8 reserved_at_400[0x8]; 2974 u8 deth_sqpn[0x18]; 2975 2976 u8 reserved_at_420[0x20]; 2977 2978 u8 reserved_at_440[0x8]; 2979 u8 last_acked_psn[0x18]; 2980 2981 u8 reserved_at_460[0x8]; 2982 u8 ssn[0x18]; 2983 2984 u8 reserved_at_480[0x8]; 2985 u8 log_rra_max[0x3]; 2986 u8 reserved_at_48b[0x1]; 2987 u8 atomic_mode[0x4]; 2988 u8 rre[0x1]; 2989 u8 rwe[0x1]; 2990 u8 rae[0x1]; 2991 u8 reserved_at_493[0x1]; 2992 u8 page_offset[0x6]; 2993 u8 reserved_at_49a[0x3]; 2994 u8 cd_slave_receive[0x1]; 2995 u8 cd_slave_send[0x1]; 2996 u8 cd_master[0x1]; 2997 2998 u8 reserved_at_4a0[0x3]; 2999 u8 min_rnr_nak[0x5]; 3000 u8 next_rcv_psn[0x18]; 3001 3002 u8 reserved_at_4c0[0x8]; 3003 u8 xrcd[0x18]; 3004 3005 u8 reserved_at_4e0[0x8]; 3006 u8 cqn_rcv[0x18]; 3007 3008 u8 dbr_addr[0x40]; 3009 3010 u8 q_key[0x20]; 3011 3012 u8 reserved_at_560[0x5]; 3013 u8 rq_type[0x3]; 3014 u8 srqn_rmpn_xrqn[0x18]; 3015 3016 u8 reserved_at_580[0x8]; 3017 u8 rmsn[0x18]; 3018 3019 u8 hw_sq_wqebb_counter[0x10]; 3020 u8 sw_sq_wqebb_counter[0x10]; 3021 3022 u8 hw_rq_counter[0x20]; 3023 3024 u8 sw_rq_counter[0x20]; 3025 3026 u8 reserved_at_600[0x20]; 3027 3028 u8 reserved_at_620[0xf]; 3029 u8 cgs[0x1]; 3030 u8 cs_req[0x8]; 3031 u8 cs_res[0x8]; 3032 3033 u8 dc_access_key[0x40]; 3034 3035 u8 reserved_at_680[0x3]; 3036 u8 dbr_umem_valid[0x1]; 3037 3038 u8 reserved_at_684[0xbc]; 3039 }; 3040 3041 struct mlx5_ifc_roce_addr_layout_bits { 3042 u8 source_l3_address[16][0x8]; 3043 3044 u8 reserved_at_80[0x3]; 3045 u8 vlan_valid[0x1]; 3046 u8 vlan_id[0xc]; 3047 u8 source_mac_47_32[0x10]; 3048 3049 u8 source_mac_31_0[0x20]; 3050 3051 u8 reserved_at_c0[0x14]; 3052 u8 roce_l3_type[0x4]; 3053 u8 roce_version[0x8]; 3054 3055 u8 reserved_at_e0[0x20]; 3056 }; 3057 3058 union mlx5_ifc_hca_cap_union_bits { 3059 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3060 struct mlx5_ifc_odp_cap_bits odp_cap; 3061 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3062 struct mlx5_ifc_roce_cap_bits roce_cap; 3063 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3064 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3065 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3066 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3067 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3068 struct mlx5_ifc_qos_cap_bits qos_cap; 3069 struct mlx5_ifc_debug_cap_bits debug_cap; 3070 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3071 struct mlx5_ifc_tls_cap_bits tls_cap; 3072 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3073 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3074 u8 reserved_at_0[0x8000]; 3075 }; 3076 3077 enum { 3078 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3079 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3080 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3081 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3082 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3083 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3084 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3085 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3086 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3087 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3088 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3089 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3090 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3091 }; 3092 3093 enum { 3094 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3095 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3096 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3097 }; 3098 3099 struct mlx5_ifc_vlan_bits { 3100 u8 ethtype[0x10]; 3101 u8 prio[0x3]; 3102 u8 cfi[0x1]; 3103 u8 vid[0xc]; 3104 }; 3105 3106 struct mlx5_ifc_flow_context_bits { 3107 struct mlx5_ifc_vlan_bits push_vlan; 3108 3109 u8 group_id[0x20]; 3110 3111 u8 reserved_at_40[0x8]; 3112 u8 flow_tag[0x18]; 3113 3114 u8 reserved_at_60[0x10]; 3115 u8 action[0x10]; 3116 3117 u8 extended_destination[0x1]; 3118 u8 reserved_at_81[0x1]; 3119 u8 flow_source[0x2]; 3120 u8 reserved_at_84[0x4]; 3121 u8 destination_list_size[0x18]; 3122 3123 u8 reserved_at_a0[0x8]; 3124 u8 flow_counter_list_size[0x18]; 3125 3126 u8 packet_reformat_id[0x20]; 3127 3128 u8 modify_header_id[0x20]; 3129 3130 struct mlx5_ifc_vlan_bits push_vlan_2; 3131 3132 u8 ipsec_obj_id[0x20]; 3133 u8 reserved_at_140[0xc0]; 3134 3135 struct mlx5_ifc_fte_match_param_bits match_value; 3136 3137 u8 reserved_at_1200[0x600]; 3138 3139 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3140 }; 3141 3142 enum { 3143 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3144 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3145 }; 3146 3147 struct mlx5_ifc_xrc_srqc_bits { 3148 u8 state[0x4]; 3149 u8 log_xrc_srq_size[0x4]; 3150 u8 reserved_at_8[0x18]; 3151 3152 u8 wq_signature[0x1]; 3153 u8 cont_srq[0x1]; 3154 u8 reserved_at_22[0x1]; 3155 u8 rlky[0x1]; 3156 u8 basic_cyclic_rcv_wqe[0x1]; 3157 u8 log_rq_stride[0x3]; 3158 u8 xrcd[0x18]; 3159 3160 u8 page_offset[0x6]; 3161 u8 reserved_at_46[0x1]; 3162 u8 dbr_umem_valid[0x1]; 3163 u8 cqn[0x18]; 3164 3165 u8 reserved_at_60[0x20]; 3166 3167 u8 user_index_equal_xrc_srqn[0x1]; 3168 u8 reserved_at_81[0x1]; 3169 u8 log_page_size[0x6]; 3170 u8 user_index[0x18]; 3171 3172 u8 reserved_at_a0[0x20]; 3173 3174 u8 reserved_at_c0[0x8]; 3175 u8 pd[0x18]; 3176 3177 u8 lwm[0x10]; 3178 u8 wqe_cnt[0x10]; 3179 3180 u8 reserved_at_100[0x40]; 3181 3182 u8 db_record_addr_h[0x20]; 3183 3184 u8 db_record_addr_l[0x1e]; 3185 u8 reserved_at_17e[0x2]; 3186 3187 u8 reserved_at_180[0x80]; 3188 }; 3189 3190 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3191 u8 counter_error_queues[0x20]; 3192 3193 u8 total_error_queues[0x20]; 3194 3195 u8 send_queue_priority_update_flow[0x20]; 3196 3197 u8 reserved_at_60[0x20]; 3198 3199 u8 nic_receive_steering_discard[0x40]; 3200 3201 u8 receive_discard_vport_down[0x40]; 3202 3203 u8 transmit_discard_vport_down[0x40]; 3204 3205 u8 reserved_at_140[0xa0]; 3206 3207 u8 internal_rq_out_of_buffer[0x20]; 3208 3209 u8 reserved_at_200[0xe00]; 3210 }; 3211 3212 struct mlx5_ifc_traffic_counter_bits { 3213 u8 packets[0x40]; 3214 3215 u8 octets[0x40]; 3216 }; 3217 3218 struct mlx5_ifc_tisc_bits { 3219 u8 strict_lag_tx_port_affinity[0x1]; 3220 u8 tls_en[0x1]; 3221 u8 reserved_at_2[0x2]; 3222 u8 lag_tx_port_affinity[0x04]; 3223 3224 u8 reserved_at_8[0x4]; 3225 u8 prio[0x4]; 3226 u8 reserved_at_10[0x10]; 3227 3228 u8 reserved_at_20[0x100]; 3229 3230 u8 reserved_at_120[0x8]; 3231 u8 transport_domain[0x18]; 3232 3233 u8 reserved_at_140[0x8]; 3234 u8 underlay_qpn[0x18]; 3235 3236 u8 reserved_at_160[0x8]; 3237 u8 pd[0x18]; 3238 3239 u8 reserved_at_180[0x380]; 3240 }; 3241 3242 enum { 3243 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3244 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3245 }; 3246 3247 enum { 3248 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3249 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3250 }; 3251 3252 enum { 3253 MLX5_RX_HASH_FN_NONE = 0x0, 3254 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3255 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3256 }; 3257 3258 enum { 3259 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3260 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3261 }; 3262 3263 struct mlx5_ifc_tirc_bits { 3264 u8 reserved_at_0[0x20]; 3265 3266 u8 disp_type[0x4]; 3267 u8 tls_en[0x1]; 3268 u8 reserved_at_25[0x1b]; 3269 3270 u8 reserved_at_40[0x40]; 3271 3272 u8 reserved_at_80[0x4]; 3273 u8 lro_timeout_period_usecs[0x10]; 3274 u8 lro_enable_mask[0x4]; 3275 u8 lro_max_ip_payload_size[0x8]; 3276 3277 u8 reserved_at_a0[0x40]; 3278 3279 u8 reserved_at_e0[0x8]; 3280 u8 inline_rqn[0x18]; 3281 3282 u8 rx_hash_symmetric[0x1]; 3283 u8 reserved_at_101[0x1]; 3284 u8 tunneled_offload_en[0x1]; 3285 u8 reserved_at_103[0x5]; 3286 u8 indirect_table[0x18]; 3287 3288 u8 rx_hash_fn[0x4]; 3289 u8 reserved_at_124[0x2]; 3290 u8 self_lb_block[0x2]; 3291 u8 transport_domain[0x18]; 3292 3293 u8 rx_hash_toeplitz_key[10][0x20]; 3294 3295 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3296 3297 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3298 3299 u8 reserved_at_2c0[0x4c0]; 3300 }; 3301 3302 enum { 3303 MLX5_SRQC_STATE_GOOD = 0x0, 3304 MLX5_SRQC_STATE_ERROR = 0x1, 3305 }; 3306 3307 struct mlx5_ifc_srqc_bits { 3308 u8 state[0x4]; 3309 u8 log_srq_size[0x4]; 3310 u8 reserved_at_8[0x18]; 3311 3312 u8 wq_signature[0x1]; 3313 u8 cont_srq[0x1]; 3314 u8 reserved_at_22[0x1]; 3315 u8 rlky[0x1]; 3316 u8 reserved_at_24[0x1]; 3317 u8 log_rq_stride[0x3]; 3318 u8 xrcd[0x18]; 3319 3320 u8 page_offset[0x6]; 3321 u8 reserved_at_46[0x2]; 3322 u8 cqn[0x18]; 3323 3324 u8 reserved_at_60[0x20]; 3325 3326 u8 reserved_at_80[0x2]; 3327 u8 log_page_size[0x6]; 3328 u8 reserved_at_88[0x18]; 3329 3330 u8 reserved_at_a0[0x20]; 3331 3332 u8 reserved_at_c0[0x8]; 3333 u8 pd[0x18]; 3334 3335 u8 lwm[0x10]; 3336 u8 wqe_cnt[0x10]; 3337 3338 u8 reserved_at_100[0x40]; 3339 3340 u8 dbr_addr[0x40]; 3341 3342 u8 reserved_at_180[0x80]; 3343 }; 3344 3345 enum { 3346 MLX5_SQC_STATE_RST = 0x0, 3347 MLX5_SQC_STATE_RDY = 0x1, 3348 MLX5_SQC_STATE_ERR = 0x3, 3349 }; 3350 3351 enum { 3352 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3353 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3354 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3355 }; 3356 3357 struct mlx5_ifc_sqc_bits { 3358 u8 rlky[0x1]; 3359 u8 cd_master[0x1]; 3360 u8 fre[0x1]; 3361 u8 flush_in_error_en[0x1]; 3362 u8 allow_multi_pkt_send_wqe[0x1]; 3363 u8 min_wqe_inline_mode[0x3]; 3364 u8 state[0x4]; 3365 u8 reg_umr[0x1]; 3366 u8 allow_swp[0x1]; 3367 u8 hairpin[0x1]; 3368 u8 reserved_at_f[0xb]; 3369 u8 ts_format[0x2]; 3370 u8 reserved_at_1c[0x4]; 3371 3372 u8 reserved_at_20[0x8]; 3373 u8 user_index[0x18]; 3374 3375 u8 reserved_at_40[0x8]; 3376 u8 cqn[0x18]; 3377 3378 u8 reserved_at_60[0x8]; 3379 u8 hairpin_peer_rq[0x18]; 3380 3381 u8 reserved_at_80[0x10]; 3382 u8 hairpin_peer_vhca[0x10]; 3383 3384 u8 reserved_at_a0[0x20]; 3385 3386 u8 reserved_at_c0[0x8]; 3387 u8 ts_cqe_to_dest_cqn[0x18]; 3388 3389 u8 reserved_at_e0[0x10]; 3390 u8 packet_pacing_rate_limit_index[0x10]; 3391 u8 tis_lst_sz[0x10]; 3392 u8 qos_queue_group_id[0x10]; 3393 3394 u8 reserved_at_120[0x40]; 3395 3396 u8 reserved_at_160[0x8]; 3397 u8 tis_num_0[0x18]; 3398 3399 struct mlx5_ifc_wq_bits wq; 3400 }; 3401 3402 enum { 3403 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3404 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3405 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3406 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3407 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3408 }; 3409 3410 enum { 3411 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3412 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3413 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3414 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3415 }; 3416 3417 struct mlx5_ifc_scheduling_context_bits { 3418 u8 element_type[0x8]; 3419 u8 reserved_at_8[0x18]; 3420 3421 u8 element_attributes[0x20]; 3422 3423 u8 parent_element_id[0x20]; 3424 3425 u8 reserved_at_60[0x40]; 3426 3427 u8 bw_share[0x20]; 3428 3429 u8 max_average_bw[0x20]; 3430 3431 u8 reserved_at_e0[0x120]; 3432 }; 3433 3434 struct mlx5_ifc_rqtc_bits { 3435 u8 reserved_at_0[0xa0]; 3436 3437 u8 reserved_at_a0[0x5]; 3438 u8 list_q_type[0x3]; 3439 u8 reserved_at_a8[0x8]; 3440 u8 rqt_max_size[0x10]; 3441 3442 u8 rq_vhca_id_format[0x1]; 3443 u8 reserved_at_c1[0xf]; 3444 u8 rqt_actual_size[0x10]; 3445 3446 u8 reserved_at_e0[0x6a0]; 3447 3448 struct mlx5_ifc_rq_num_bits rq_num[]; 3449 }; 3450 3451 enum { 3452 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3453 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3454 }; 3455 3456 enum { 3457 MLX5_RQC_STATE_RST = 0x0, 3458 MLX5_RQC_STATE_RDY = 0x1, 3459 MLX5_RQC_STATE_ERR = 0x3, 3460 }; 3461 3462 enum { 3463 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3464 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3465 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3466 }; 3467 3468 struct mlx5_ifc_rqc_bits { 3469 u8 rlky[0x1]; 3470 u8 delay_drop_en[0x1]; 3471 u8 scatter_fcs[0x1]; 3472 u8 vsd[0x1]; 3473 u8 mem_rq_type[0x4]; 3474 u8 state[0x4]; 3475 u8 reserved_at_c[0x1]; 3476 u8 flush_in_error_en[0x1]; 3477 u8 hairpin[0x1]; 3478 u8 reserved_at_f[0xb]; 3479 u8 ts_format[0x2]; 3480 u8 reserved_at_1c[0x4]; 3481 3482 u8 reserved_at_20[0x8]; 3483 u8 user_index[0x18]; 3484 3485 u8 reserved_at_40[0x8]; 3486 u8 cqn[0x18]; 3487 3488 u8 counter_set_id[0x8]; 3489 u8 reserved_at_68[0x18]; 3490 3491 u8 reserved_at_80[0x8]; 3492 u8 rmpn[0x18]; 3493 3494 u8 reserved_at_a0[0x8]; 3495 u8 hairpin_peer_sq[0x18]; 3496 3497 u8 reserved_at_c0[0x10]; 3498 u8 hairpin_peer_vhca[0x10]; 3499 3500 u8 reserved_at_e0[0xa0]; 3501 3502 struct mlx5_ifc_wq_bits wq; 3503 }; 3504 3505 enum { 3506 MLX5_RMPC_STATE_RDY = 0x1, 3507 MLX5_RMPC_STATE_ERR = 0x3, 3508 }; 3509 3510 struct mlx5_ifc_rmpc_bits { 3511 u8 reserved_at_0[0x8]; 3512 u8 state[0x4]; 3513 u8 reserved_at_c[0x14]; 3514 3515 u8 basic_cyclic_rcv_wqe[0x1]; 3516 u8 reserved_at_21[0x1f]; 3517 3518 u8 reserved_at_40[0x140]; 3519 3520 struct mlx5_ifc_wq_bits wq; 3521 }; 3522 3523 struct mlx5_ifc_nic_vport_context_bits { 3524 u8 reserved_at_0[0x5]; 3525 u8 min_wqe_inline_mode[0x3]; 3526 u8 reserved_at_8[0x15]; 3527 u8 disable_mc_local_lb[0x1]; 3528 u8 disable_uc_local_lb[0x1]; 3529 u8 roce_en[0x1]; 3530 3531 u8 arm_change_event[0x1]; 3532 u8 reserved_at_21[0x1a]; 3533 u8 event_on_mtu[0x1]; 3534 u8 event_on_promisc_change[0x1]; 3535 u8 event_on_vlan_change[0x1]; 3536 u8 event_on_mc_address_change[0x1]; 3537 u8 event_on_uc_address_change[0x1]; 3538 3539 u8 reserved_at_40[0xc]; 3540 3541 u8 affiliation_criteria[0x4]; 3542 u8 affiliated_vhca_id[0x10]; 3543 3544 u8 reserved_at_60[0xd0]; 3545 3546 u8 mtu[0x10]; 3547 3548 u8 system_image_guid[0x40]; 3549 u8 port_guid[0x40]; 3550 u8 node_guid[0x40]; 3551 3552 u8 reserved_at_200[0x140]; 3553 u8 qkey_violation_counter[0x10]; 3554 u8 reserved_at_350[0x430]; 3555 3556 u8 promisc_uc[0x1]; 3557 u8 promisc_mc[0x1]; 3558 u8 promisc_all[0x1]; 3559 u8 reserved_at_783[0x2]; 3560 u8 allowed_list_type[0x3]; 3561 u8 reserved_at_788[0xc]; 3562 u8 allowed_list_size[0xc]; 3563 3564 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3565 3566 u8 reserved_at_7e0[0x20]; 3567 3568 u8 current_uc_mac_address[][0x40]; 3569 }; 3570 3571 enum { 3572 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3573 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3574 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3575 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3576 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3577 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3578 }; 3579 3580 struct mlx5_ifc_mkc_bits { 3581 u8 reserved_at_0[0x1]; 3582 u8 free[0x1]; 3583 u8 reserved_at_2[0x1]; 3584 u8 access_mode_4_2[0x3]; 3585 u8 reserved_at_6[0x7]; 3586 u8 relaxed_ordering_write[0x1]; 3587 u8 reserved_at_e[0x1]; 3588 u8 small_fence_on_rdma_read_response[0x1]; 3589 u8 umr_en[0x1]; 3590 u8 a[0x1]; 3591 u8 rw[0x1]; 3592 u8 rr[0x1]; 3593 u8 lw[0x1]; 3594 u8 lr[0x1]; 3595 u8 access_mode_1_0[0x2]; 3596 u8 reserved_at_18[0x8]; 3597 3598 u8 qpn[0x18]; 3599 u8 mkey_7_0[0x8]; 3600 3601 u8 reserved_at_40[0x20]; 3602 3603 u8 length64[0x1]; 3604 u8 bsf_en[0x1]; 3605 u8 sync_umr[0x1]; 3606 u8 reserved_at_63[0x2]; 3607 u8 expected_sigerr_count[0x1]; 3608 u8 reserved_at_66[0x1]; 3609 u8 en_rinval[0x1]; 3610 u8 pd[0x18]; 3611 3612 u8 start_addr[0x40]; 3613 3614 u8 len[0x40]; 3615 3616 u8 bsf_octword_size[0x20]; 3617 3618 u8 reserved_at_120[0x80]; 3619 3620 u8 translations_octword_size[0x20]; 3621 3622 u8 reserved_at_1c0[0x19]; 3623 u8 relaxed_ordering_read[0x1]; 3624 u8 reserved_at_1d9[0x1]; 3625 u8 log_page_size[0x5]; 3626 3627 u8 reserved_at_1e0[0x20]; 3628 }; 3629 3630 struct mlx5_ifc_pkey_bits { 3631 u8 reserved_at_0[0x10]; 3632 u8 pkey[0x10]; 3633 }; 3634 3635 struct mlx5_ifc_array128_auto_bits { 3636 u8 array128_auto[16][0x8]; 3637 }; 3638 3639 struct mlx5_ifc_hca_vport_context_bits { 3640 u8 field_select[0x20]; 3641 3642 u8 reserved_at_20[0xe0]; 3643 3644 u8 sm_virt_aware[0x1]; 3645 u8 has_smi[0x1]; 3646 u8 has_raw[0x1]; 3647 u8 grh_required[0x1]; 3648 u8 reserved_at_104[0xc]; 3649 u8 port_physical_state[0x4]; 3650 u8 vport_state_policy[0x4]; 3651 u8 port_state[0x4]; 3652 u8 vport_state[0x4]; 3653 3654 u8 reserved_at_120[0x20]; 3655 3656 u8 system_image_guid[0x40]; 3657 3658 u8 port_guid[0x40]; 3659 3660 u8 node_guid[0x40]; 3661 3662 u8 cap_mask1[0x20]; 3663 3664 u8 cap_mask1_field_select[0x20]; 3665 3666 u8 cap_mask2[0x20]; 3667 3668 u8 cap_mask2_field_select[0x20]; 3669 3670 u8 reserved_at_280[0x80]; 3671 3672 u8 lid[0x10]; 3673 u8 reserved_at_310[0x4]; 3674 u8 init_type_reply[0x4]; 3675 u8 lmc[0x3]; 3676 u8 subnet_timeout[0x5]; 3677 3678 u8 sm_lid[0x10]; 3679 u8 sm_sl[0x4]; 3680 u8 reserved_at_334[0xc]; 3681 3682 u8 qkey_violation_counter[0x10]; 3683 u8 pkey_violation_counter[0x10]; 3684 3685 u8 reserved_at_360[0xca0]; 3686 }; 3687 3688 struct mlx5_ifc_esw_vport_context_bits { 3689 u8 fdb_to_vport_reg_c[0x1]; 3690 u8 reserved_at_1[0x2]; 3691 u8 vport_svlan_strip[0x1]; 3692 u8 vport_cvlan_strip[0x1]; 3693 u8 vport_svlan_insert[0x1]; 3694 u8 vport_cvlan_insert[0x2]; 3695 u8 fdb_to_vport_reg_c_id[0x8]; 3696 u8 reserved_at_10[0x10]; 3697 3698 u8 reserved_at_20[0x20]; 3699 3700 u8 svlan_cfi[0x1]; 3701 u8 svlan_pcp[0x3]; 3702 u8 svlan_id[0xc]; 3703 u8 cvlan_cfi[0x1]; 3704 u8 cvlan_pcp[0x3]; 3705 u8 cvlan_id[0xc]; 3706 3707 u8 reserved_at_60[0x720]; 3708 3709 u8 sw_steering_vport_icm_address_rx[0x40]; 3710 3711 u8 sw_steering_vport_icm_address_tx[0x40]; 3712 }; 3713 3714 enum { 3715 MLX5_EQC_STATUS_OK = 0x0, 3716 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3717 }; 3718 3719 enum { 3720 MLX5_EQC_ST_ARMED = 0x9, 3721 MLX5_EQC_ST_FIRED = 0xa, 3722 }; 3723 3724 struct mlx5_ifc_eqc_bits { 3725 u8 status[0x4]; 3726 u8 reserved_at_4[0x9]; 3727 u8 ec[0x1]; 3728 u8 oi[0x1]; 3729 u8 reserved_at_f[0x5]; 3730 u8 st[0x4]; 3731 u8 reserved_at_18[0x8]; 3732 3733 u8 reserved_at_20[0x20]; 3734 3735 u8 reserved_at_40[0x14]; 3736 u8 page_offset[0x6]; 3737 u8 reserved_at_5a[0x6]; 3738 3739 u8 reserved_at_60[0x3]; 3740 u8 log_eq_size[0x5]; 3741 u8 uar_page[0x18]; 3742 3743 u8 reserved_at_80[0x20]; 3744 3745 u8 reserved_at_a0[0x18]; 3746 u8 intr[0x8]; 3747 3748 u8 reserved_at_c0[0x3]; 3749 u8 log_page_size[0x5]; 3750 u8 reserved_at_c8[0x18]; 3751 3752 u8 reserved_at_e0[0x60]; 3753 3754 u8 reserved_at_140[0x8]; 3755 u8 consumer_counter[0x18]; 3756 3757 u8 reserved_at_160[0x8]; 3758 u8 producer_counter[0x18]; 3759 3760 u8 reserved_at_180[0x80]; 3761 }; 3762 3763 enum { 3764 MLX5_DCTC_STATE_ACTIVE = 0x0, 3765 MLX5_DCTC_STATE_DRAINING = 0x1, 3766 MLX5_DCTC_STATE_DRAINED = 0x2, 3767 }; 3768 3769 enum { 3770 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3771 MLX5_DCTC_CS_RES_NA = 0x1, 3772 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3773 }; 3774 3775 enum { 3776 MLX5_DCTC_MTU_256_BYTES = 0x1, 3777 MLX5_DCTC_MTU_512_BYTES = 0x2, 3778 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3779 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3780 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3781 }; 3782 3783 struct mlx5_ifc_dctc_bits { 3784 u8 reserved_at_0[0x4]; 3785 u8 state[0x4]; 3786 u8 reserved_at_8[0x18]; 3787 3788 u8 reserved_at_20[0x8]; 3789 u8 user_index[0x18]; 3790 3791 u8 reserved_at_40[0x8]; 3792 u8 cqn[0x18]; 3793 3794 u8 counter_set_id[0x8]; 3795 u8 atomic_mode[0x4]; 3796 u8 rre[0x1]; 3797 u8 rwe[0x1]; 3798 u8 rae[0x1]; 3799 u8 atomic_like_write_en[0x1]; 3800 u8 latency_sensitive[0x1]; 3801 u8 rlky[0x1]; 3802 u8 free_ar[0x1]; 3803 u8 reserved_at_73[0xd]; 3804 3805 u8 reserved_at_80[0x8]; 3806 u8 cs_res[0x8]; 3807 u8 reserved_at_90[0x3]; 3808 u8 min_rnr_nak[0x5]; 3809 u8 reserved_at_98[0x8]; 3810 3811 u8 reserved_at_a0[0x8]; 3812 u8 srqn_xrqn[0x18]; 3813 3814 u8 reserved_at_c0[0x8]; 3815 u8 pd[0x18]; 3816 3817 u8 tclass[0x8]; 3818 u8 reserved_at_e8[0x4]; 3819 u8 flow_label[0x14]; 3820 3821 u8 dc_access_key[0x40]; 3822 3823 u8 reserved_at_140[0x5]; 3824 u8 mtu[0x3]; 3825 u8 port[0x8]; 3826 u8 pkey_index[0x10]; 3827 3828 u8 reserved_at_160[0x8]; 3829 u8 my_addr_index[0x8]; 3830 u8 reserved_at_170[0x8]; 3831 u8 hop_limit[0x8]; 3832 3833 u8 dc_access_key_violation_count[0x20]; 3834 3835 u8 reserved_at_1a0[0x14]; 3836 u8 dei_cfi[0x1]; 3837 u8 eth_prio[0x3]; 3838 u8 ecn[0x2]; 3839 u8 dscp[0x6]; 3840 3841 u8 reserved_at_1c0[0x20]; 3842 u8 ece[0x20]; 3843 }; 3844 3845 enum { 3846 MLX5_CQC_STATUS_OK = 0x0, 3847 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3848 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3849 }; 3850 3851 enum { 3852 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3853 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3854 }; 3855 3856 enum { 3857 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3858 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3859 MLX5_CQC_ST_FIRED = 0xa, 3860 }; 3861 3862 enum { 3863 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3864 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3865 MLX5_CQ_PERIOD_NUM_MODES 3866 }; 3867 3868 struct mlx5_ifc_cqc_bits { 3869 u8 status[0x4]; 3870 u8 reserved_at_4[0x2]; 3871 u8 dbr_umem_valid[0x1]; 3872 u8 apu_thread_cq[0x1]; 3873 u8 cqe_sz[0x3]; 3874 u8 cc[0x1]; 3875 u8 reserved_at_c[0x1]; 3876 u8 scqe_break_moderation_en[0x1]; 3877 u8 oi[0x1]; 3878 u8 cq_period_mode[0x2]; 3879 u8 cqe_comp_en[0x1]; 3880 u8 mini_cqe_res_format[0x2]; 3881 u8 st[0x4]; 3882 u8 reserved_at_18[0x8]; 3883 3884 u8 reserved_at_20[0x20]; 3885 3886 u8 reserved_at_40[0x14]; 3887 u8 page_offset[0x6]; 3888 u8 reserved_at_5a[0x6]; 3889 3890 u8 reserved_at_60[0x3]; 3891 u8 log_cq_size[0x5]; 3892 u8 uar_page[0x18]; 3893 3894 u8 reserved_at_80[0x4]; 3895 u8 cq_period[0xc]; 3896 u8 cq_max_count[0x10]; 3897 3898 u8 reserved_at_a0[0x18]; 3899 u8 c_eqn[0x8]; 3900 3901 u8 reserved_at_c0[0x3]; 3902 u8 log_page_size[0x5]; 3903 u8 reserved_at_c8[0x18]; 3904 3905 u8 reserved_at_e0[0x20]; 3906 3907 u8 reserved_at_100[0x8]; 3908 u8 last_notified_index[0x18]; 3909 3910 u8 reserved_at_120[0x8]; 3911 u8 last_solicit_index[0x18]; 3912 3913 u8 reserved_at_140[0x8]; 3914 u8 consumer_counter[0x18]; 3915 3916 u8 reserved_at_160[0x8]; 3917 u8 producer_counter[0x18]; 3918 3919 u8 reserved_at_180[0x40]; 3920 3921 u8 dbr_addr[0x40]; 3922 }; 3923 3924 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3925 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3926 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3927 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3928 u8 reserved_at_0[0x800]; 3929 }; 3930 3931 struct mlx5_ifc_query_adapter_param_block_bits { 3932 u8 reserved_at_0[0xc0]; 3933 3934 u8 reserved_at_c0[0x8]; 3935 u8 ieee_vendor_id[0x18]; 3936 3937 u8 reserved_at_e0[0x10]; 3938 u8 vsd_vendor_id[0x10]; 3939 3940 u8 vsd[208][0x8]; 3941 3942 u8 vsd_contd_psid[16][0x8]; 3943 }; 3944 3945 enum { 3946 MLX5_XRQC_STATE_GOOD = 0x0, 3947 MLX5_XRQC_STATE_ERROR = 0x1, 3948 }; 3949 3950 enum { 3951 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3952 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3953 }; 3954 3955 enum { 3956 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3957 }; 3958 3959 struct mlx5_ifc_tag_matching_topology_context_bits { 3960 u8 log_matching_list_sz[0x4]; 3961 u8 reserved_at_4[0xc]; 3962 u8 append_next_index[0x10]; 3963 3964 u8 sw_phase_cnt[0x10]; 3965 u8 hw_phase_cnt[0x10]; 3966 3967 u8 reserved_at_40[0x40]; 3968 }; 3969 3970 struct mlx5_ifc_xrqc_bits { 3971 u8 state[0x4]; 3972 u8 rlkey[0x1]; 3973 u8 reserved_at_5[0xf]; 3974 u8 topology[0x4]; 3975 u8 reserved_at_18[0x4]; 3976 u8 offload[0x4]; 3977 3978 u8 reserved_at_20[0x8]; 3979 u8 user_index[0x18]; 3980 3981 u8 reserved_at_40[0x8]; 3982 u8 cqn[0x18]; 3983 3984 u8 reserved_at_60[0xa0]; 3985 3986 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3987 3988 u8 reserved_at_180[0x280]; 3989 3990 struct mlx5_ifc_wq_bits wq; 3991 }; 3992 3993 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3994 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3995 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3996 u8 reserved_at_0[0x20]; 3997 }; 3998 3999 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4000 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4001 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4002 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4003 u8 reserved_at_0[0x20]; 4004 }; 4005 4006 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4007 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4008 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4009 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4010 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4011 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4012 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4013 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4014 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4015 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4016 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4017 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4018 u8 reserved_at_0[0x7c0]; 4019 }; 4020 4021 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4022 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4023 u8 reserved_at_0[0x7c0]; 4024 }; 4025 4026 union mlx5_ifc_event_auto_bits { 4027 struct mlx5_ifc_comp_event_bits comp_event; 4028 struct mlx5_ifc_dct_events_bits dct_events; 4029 struct mlx5_ifc_qp_events_bits qp_events; 4030 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4031 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4032 struct mlx5_ifc_cq_error_bits cq_error; 4033 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4034 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4035 struct mlx5_ifc_gpio_event_bits gpio_event; 4036 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4037 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4038 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4039 u8 reserved_at_0[0xe0]; 4040 }; 4041 4042 struct mlx5_ifc_health_buffer_bits { 4043 u8 reserved_at_0[0x100]; 4044 4045 u8 assert_existptr[0x20]; 4046 4047 u8 assert_callra[0x20]; 4048 4049 u8 reserved_at_140[0x40]; 4050 4051 u8 fw_version[0x20]; 4052 4053 u8 hw_id[0x20]; 4054 4055 u8 reserved_at_1c0[0x20]; 4056 4057 u8 irisc_index[0x8]; 4058 u8 synd[0x8]; 4059 u8 ext_synd[0x10]; 4060 }; 4061 4062 struct mlx5_ifc_register_loopback_control_bits { 4063 u8 no_lb[0x1]; 4064 u8 reserved_at_1[0x7]; 4065 u8 port[0x8]; 4066 u8 reserved_at_10[0x10]; 4067 4068 u8 reserved_at_20[0x60]; 4069 }; 4070 4071 struct mlx5_ifc_vport_tc_element_bits { 4072 u8 traffic_class[0x4]; 4073 u8 reserved_at_4[0xc]; 4074 u8 vport_number[0x10]; 4075 }; 4076 4077 struct mlx5_ifc_vport_element_bits { 4078 u8 reserved_at_0[0x10]; 4079 u8 vport_number[0x10]; 4080 }; 4081 4082 enum { 4083 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4084 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4085 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4086 }; 4087 4088 struct mlx5_ifc_tsar_element_bits { 4089 u8 reserved_at_0[0x8]; 4090 u8 tsar_type[0x8]; 4091 u8 reserved_at_10[0x10]; 4092 }; 4093 4094 enum { 4095 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4096 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4097 }; 4098 4099 struct mlx5_ifc_teardown_hca_out_bits { 4100 u8 status[0x8]; 4101 u8 reserved_at_8[0x18]; 4102 4103 u8 syndrome[0x20]; 4104 4105 u8 reserved_at_40[0x3f]; 4106 4107 u8 state[0x1]; 4108 }; 4109 4110 enum { 4111 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4112 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4113 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4114 }; 4115 4116 struct mlx5_ifc_teardown_hca_in_bits { 4117 u8 opcode[0x10]; 4118 u8 reserved_at_10[0x10]; 4119 4120 u8 reserved_at_20[0x10]; 4121 u8 op_mod[0x10]; 4122 4123 u8 reserved_at_40[0x10]; 4124 u8 profile[0x10]; 4125 4126 u8 reserved_at_60[0x20]; 4127 }; 4128 4129 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4130 u8 status[0x8]; 4131 u8 reserved_at_8[0x18]; 4132 4133 u8 syndrome[0x20]; 4134 4135 u8 reserved_at_40[0x40]; 4136 }; 4137 4138 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4139 u8 opcode[0x10]; 4140 u8 uid[0x10]; 4141 4142 u8 reserved_at_20[0x10]; 4143 u8 op_mod[0x10]; 4144 4145 u8 reserved_at_40[0x8]; 4146 u8 qpn[0x18]; 4147 4148 u8 reserved_at_60[0x20]; 4149 4150 u8 opt_param_mask[0x20]; 4151 4152 u8 reserved_at_a0[0x20]; 4153 4154 struct mlx5_ifc_qpc_bits qpc; 4155 4156 u8 reserved_at_800[0x80]; 4157 }; 4158 4159 struct mlx5_ifc_sqd2rts_qp_out_bits { 4160 u8 status[0x8]; 4161 u8 reserved_at_8[0x18]; 4162 4163 u8 syndrome[0x20]; 4164 4165 u8 reserved_at_40[0x40]; 4166 }; 4167 4168 struct mlx5_ifc_sqd2rts_qp_in_bits { 4169 u8 opcode[0x10]; 4170 u8 uid[0x10]; 4171 4172 u8 reserved_at_20[0x10]; 4173 u8 op_mod[0x10]; 4174 4175 u8 reserved_at_40[0x8]; 4176 u8 qpn[0x18]; 4177 4178 u8 reserved_at_60[0x20]; 4179 4180 u8 opt_param_mask[0x20]; 4181 4182 u8 reserved_at_a0[0x20]; 4183 4184 struct mlx5_ifc_qpc_bits qpc; 4185 4186 u8 reserved_at_800[0x80]; 4187 }; 4188 4189 struct mlx5_ifc_set_roce_address_out_bits { 4190 u8 status[0x8]; 4191 u8 reserved_at_8[0x18]; 4192 4193 u8 syndrome[0x20]; 4194 4195 u8 reserved_at_40[0x40]; 4196 }; 4197 4198 struct mlx5_ifc_set_roce_address_in_bits { 4199 u8 opcode[0x10]; 4200 u8 reserved_at_10[0x10]; 4201 4202 u8 reserved_at_20[0x10]; 4203 u8 op_mod[0x10]; 4204 4205 u8 roce_address_index[0x10]; 4206 u8 reserved_at_50[0xc]; 4207 u8 vhca_port_num[0x4]; 4208 4209 u8 reserved_at_60[0x20]; 4210 4211 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4212 }; 4213 4214 struct mlx5_ifc_set_mad_demux_out_bits { 4215 u8 status[0x8]; 4216 u8 reserved_at_8[0x18]; 4217 4218 u8 syndrome[0x20]; 4219 4220 u8 reserved_at_40[0x40]; 4221 }; 4222 4223 enum { 4224 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4225 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4226 }; 4227 4228 struct mlx5_ifc_set_mad_demux_in_bits { 4229 u8 opcode[0x10]; 4230 u8 reserved_at_10[0x10]; 4231 4232 u8 reserved_at_20[0x10]; 4233 u8 op_mod[0x10]; 4234 4235 u8 reserved_at_40[0x20]; 4236 4237 u8 reserved_at_60[0x6]; 4238 u8 demux_mode[0x2]; 4239 u8 reserved_at_68[0x18]; 4240 }; 4241 4242 struct mlx5_ifc_set_l2_table_entry_out_bits { 4243 u8 status[0x8]; 4244 u8 reserved_at_8[0x18]; 4245 4246 u8 syndrome[0x20]; 4247 4248 u8 reserved_at_40[0x40]; 4249 }; 4250 4251 struct mlx5_ifc_set_l2_table_entry_in_bits { 4252 u8 opcode[0x10]; 4253 u8 reserved_at_10[0x10]; 4254 4255 u8 reserved_at_20[0x10]; 4256 u8 op_mod[0x10]; 4257 4258 u8 reserved_at_40[0x60]; 4259 4260 u8 reserved_at_a0[0x8]; 4261 u8 table_index[0x18]; 4262 4263 u8 reserved_at_c0[0x20]; 4264 4265 u8 reserved_at_e0[0x13]; 4266 u8 vlan_valid[0x1]; 4267 u8 vlan[0xc]; 4268 4269 struct mlx5_ifc_mac_address_layout_bits mac_address; 4270 4271 u8 reserved_at_140[0xc0]; 4272 }; 4273 4274 struct mlx5_ifc_set_issi_out_bits { 4275 u8 status[0x8]; 4276 u8 reserved_at_8[0x18]; 4277 4278 u8 syndrome[0x20]; 4279 4280 u8 reserved_at_40[0x40]; 4281 }; 4282 4283 struct mlx5_ifc_set_issi_in_bits { 4284 u8 opcode[0x10]; 4285 u8 reserved_at_10[0x10]; 4286 4287 u8 reserved_at_20[0x10]; 4288 u8 op_mod[0x10]; 4289 4290 u8 reserved_at_40[0x10]; 4291 u8 current_issi[0x10]; 4292 4293 u8 reserved_at_60[0x20]; 4294 }; 4295 4296 struct mlx5_ifc_set_hca_cap_out_bits { 4297 u8 status[0x8]; 4298 u8 reserved_at_8[0x18]; 4299 4300 u8 syndrome[0x20]; 4301 4302 u8 reserved_at_40[0x40]; 4303 }; 4304 4305 struct mlx5_ifc_set_hca_cap_in_bits { 4306 u8 opcode[0x10]; 4307 u8 reserved_at_10[0x10]; 4308 4309 u8 reserved_at_20[0x10]; 4310 u8 op_mod[0x10]; 4311 4312 u8 other_function[0x1]; 4313 u8 reserved_at_41[0xf]; 4314 u8 function_id[0x10]; 4315 4316 u8 reserved_at_60[0x20]; 4317 4318 union mlx5_ifc_hca_cap_union_bits capability; 4319 }; 4320 4321 enum { 4322 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4323 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4324 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4325 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4326 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4327 }; 4328 4329 struct mlx5_ifc_set_fte_out_bits { 4330 u8 status[0x8]; 4331 u8 reserved_at_8[0x18]; 4332 4333 u8 syndrome[0x20]; 4334 4335 u8 reserved_at_40[0x40]; 4336 }; 4337 4338 struct mlx5_ifc_set_fte_in_bits { 4339 u8 opcode[0x10]; 4340 u8 reserved_at_10[0x10]; 4341 4342 u8 reserved_at_20[0x10]; 4343 u8 op_mod[0x10]; 4344 4345 u8 other_vport[0x1]; 4346 u8 reserved_at_41[0xf]; 4347 u8 vport_number[0x10]; 4348 4349 u8 reserved_at_60[0x20]; 4350 4351 u8 table_type[0x8]; 4352 u8 reserved_at_88[0x18]; 4353 4354 u8 reserved_at_a0[0x8]; 4355 u8 table_id[0x18]; 4356 4357 u8 ignore_flow_level[0x1]; 4358 u8 reserved_at_c1[0x17]; 4359 u8 modify_enable_mask[0x8]; 4360 4361 u8 reserved_at_e0[0x20]; 4362 4363 u8 flow_index[0x20]; 4364 4365 u8 reserved_at_120[0xe0]; 4366 4367 struct mlx5_ifc_flow_context_bits flow_context; 4368 }; 4369 4370 struct mlx5_ifc_rts2rts_qp_out_bits { 4371 u8 status[0x8]; 4372 u8 reserved_at_8[0x18]; 4373 4374 u8 syndrome[0x20]; 4375 4376 u8 reserved_at_40[0x20]; 4377 u8 ece[0x20]; 4378 }; 4379 4380 struct mlx5_ifc_rts2rts_qp_in_bits { 4381 u8 opcode[0x10]; 4382 u8 uid[0x10]; 4383 4384 u8 reserved_at_20[0x10]; 4385 u8 op_mod[0x10]; 4386 4387 u8 reserved_at_40[0x8]; 4388 u8 qpn[0x18]; 4389 4390 u8 reserved_at_60[0x20]; 4391 4392 u8 opt_param_mask[0x20]; 4393 4394 u8 ece[0x20]; 4395 4396 struct mlx5_ifc_qpc_bits qpc; 4397 4398 u8 reserved_at_800[0x80]; 4399 }; 4400 4401 struct mlx5_ifc_rtr2rts_qp_out_bits { 4402 u8 status[0x8]; 4403 u8 reserved_at_8[0x18]; 4404 4405 u8 syndrome[0x20]; 4406 4407 u8 reserved_at_40[0x20]; 4408 u8 ece[0x20]; 4409 }; 4410 4411 struct mlx5_ifc_rtr2rts_qp_in_bits { 4412 u8 opcode[0x10]; 4413 u8 uid[0x10]; 4414 4415 u8 reserved_at_20[0x10]; 4416 u8 op_mod[0x10]; 4417 4418 u8 reserved_at_40[0x8]; 4419 u8 qpn[0x18]; 4420 4421 u8 reserved_at_60[0x20]; 4422 4423 u8 opt_param_mask[0x20]; 4424 4425 u8 ece[0x20]; 4426 4427 struct mlx5_ifc_qpc_bits qpc; 4428 4429 u8 reserved_at_800[0x80]; 4430 }; 4431 4432 struct mlx5_ifc_rst2init_qp_out_bits { 4433 u8 status[0x8]; 4434 u8 reserved_at_8[0x18]; 4435 4436 u8 syndrome[0x20]; 4437 4438 u8 reserved_at_40[0x20]; 4439 u8 ece[0x20]; 4440 }; 4441 4442 struct mlx5_ifc_rst2init_qp_in_bits { 4443 u8 opcode[0x10]; 4444 u8 uid[0x10]; 4445 4446 u8 reserved_at_20[0x10]; 4447 u8 op_mod[0x10]; 4448 4449 u8 reserved_at_40[0x8]; 4450 u8 qpn[0x18]; 4451 4452 u8 reserved_at_60[0x20]; 4453 4454 u8 opt_param_mask[0x20]; 4455 4456 u8 ece[0x20]; 4457 4458 struct mlx5_ifc_qpc_bits qpc; 4459 4460 u8 reserved_at_800[0x80]; 4461 }; 4462 4463 struct mlx5_ifc_query_xrq_out_bits { 4464 u8 status[0x8]; 4465 u8 reserved_at_8[0x18]; 4466 4467 u8 syndrome[0x20]; 4468 4469 u8 reserved_at_40[0x40]; 4470 4471 struct mlx5_ifc_xrqc_bits xrq_context; 4472 }; 4473 4474 struct mlx5_ifc_query_xrq_in_bits { 4475 u8 opcode[0x10]; 4476 u8 reserved_at_10[0x10]; 4477 4478 u8 reserved_at_20[0x10]; 4479 u8 op_mod[0x10]; 4480 4481 u8 reserved_at_40[0x8]; 4482 u8 xrqn[0x18]; 4483 4484 u8 reserved_at_60[0x20]; 4485 }; 4486 4487 struct mlx5_ifc_query_xrc_srq_out_bits { 4488 u8 status[0x8]; 4489 u8 reserved_at_8[0x18]; 4490 4491 u8 syndrome[0x20]; 4492 4493 u8 reserved_at_40[0x40]; 4494 4495 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4496 4497 u8 reserved_at_280[0x600]; 4498 4499 u8 pas[][0x40]; 4500 }; 4501 4502 struct mlx5_ifc_query_xrc_srq_in_bits { 4503 u8 opcode[0x10]; 4504 u8 reserved_at_10[0x10]; 4505 4506 u8 reserved_at_20[0x10]; 4507 u8 op_mod[0x10]; 4508 4509 u8 reserved_at_40[0x8]; 4510 u8 xrc_srqn[0x18]; 4511 4512 u8 reserved_at_60[0x20]; 4513 }; 4514 4515 enum { 4516 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4517 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4518 }; 4519 4520 struct mlx5_ifc_query_vport_state_out_bits { 4521 u8 status[0x8]; 4522 u8 reserved_at_8[0x18]; 4523 4524 u8 syndrome[0x20]; 4525 4526 u8 reserved_at_40[0x20]; 4527 4528 u8 reserved_at_60[0x18]; 4529 u8 admin_state[0x4]; 4530 u8 state[0x4]; 4531 }; 4532 4533 enum { 4534 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4535 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4536 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4537 }; 4538 4539 struct mlx5_ifc_arm_monitor_counter_in_bits { 4540 u8 opcode[0x10]; 4541 u8 uid[0x10]; 4542 4543 u8 reserved_at_20[0x10]; 4544 u8 op_mod[0x10]; 4545 4546 u8 reserved_at_40[0x20]; 4547 4548 u8 reserved_at_60[0x20]; 4549 }; 4550 4551 struct mlx5_ifc_arm_monitor_counter_out_bits { 4552 u8 status[0x8]; 4553 u8 reserved_at_8[0x18]; 4554 4555 u8 syndrome[0x20]; 4556 4557 u8 reserved_at_40[0x40]; 4558 }; 4559 4560 enum { 4561 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4562 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4563 }; 4564 4565 enum mlx5_monitor_counter_ppcnt { 4566 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4567 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4568 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4569 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4570 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4571 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4572 }; 4573 4574 enum { 4575 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4576 }; 4577 4578 struct mlx5_ifc_monitor_counter_output_bits { 4579 u8 reserved_at_0[0x4]; 4580 u8 type[0x4]; 4581 u8 reserved_at_8[0x8]; 4582 u8 counter[0x10]; 4583 4584 u8 counter_group_id[0x20]; 4585 }; 4586 4587 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4588 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4589 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4590 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4591 4592 struct mlx5_ifc_set_monitor_counter_in_bits { 4593 u8 opcode[0x10]; 4594 u8 uid[0x10]; 4595 4596 u8 reserved_at_20[0x10]; 4597 u8 op_mod[0x10]; 4598 4599 u8 reserved_at_40[0x10]; 4600 u8 num_of_counters[0x10]; 4601 4602 u8 reserved_at_60[0x20]; 4603 4604 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4605 }; 4606 4607 struct mlx5_ifc_set_monitor_counter_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x40]; 4614 }; 4615 4616 struct mlx5_ifc_query_vport_state_in_bits { 4617 u8 opcode[0x10]; 4618 u8 reserved_at_10[0x10]; 4619 4620 u8 reserved_at_20[0x10]; 4621 u8 op_mod[0x10]; 4622 4623 u8 other_vport[0x1]; 4624 u8 reserved_at_41[0xf]; 4625 u8 vport_number[0x10]; 4626 4627 u8 reserved_at_60[0x20]; 4628 }; 4629 4630 struct mlx5_ifc_query_vnic_env_out_bits { 4631 u8 status[0x8]; 4632 u8 reserved_at_8[0x18]; 4633 4634 u8 syndrome[0x20]; 4635 4636 u8 reserved_at_40[0x40]; 4637 4638 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4639 }; 4640 4641 enum { 4642 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4643 }; 4644 4645 struct mlx5_ifc_query_vnic_env_in_bits { 4646 u8 opcode[0x10]; 4647 u8 reserved_at_10[0x10]; 4648 4649 u8 reserved_at_20[0x10]; 4650 u8 op_mod[0x10]; 4651 4652 u8 other_vport[0x1]; 4653 u8 reserved_at_41[0xf]; 4654 u8 vport_number[0x10]; 4655 4656 u8 reserved_at_60[0x20]; 4657 }; 4658 4659 struct mlx5_ifc_query_vport_counter_out_bits { 4660 u8 status[0x8]; 4661 u8 reserved_at_8[0x18]; 4662 4663 u8 syndrome[0x20]; 4664 4665 u8 reserved_at_40[0x40]; 4666 4667 struct mlx5_ifc_traffic_counter_bits received_errors; 4668 4669 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4670 4671 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4672 4673 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4674 4675 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4676 4677 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4678 4679 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4680 4681 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4682 4683 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4684 4685 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4686 4687 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4688 4689 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4690 4691 u8 reserved_at_680[0xa00]; 4692 }; 4693 4694 enum { 4695 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4696 }; 4697 4698 struct mlx5_ifc_query_vport_counter_in_bits { 4699 u8 opcode[0x10]; 4700 u8 reserved_at_10[0x10]; 4701 4702 u8 reserved_at_20[0x10]; 4703 u8 op_mod[0x10]; 4704 4705 u8 other_vport[0x1]; 4706 u8 reserved_at_41[0xb]; 4707 u8 port_num[0x4]; 4708 u8 vport_number[0x10]; 4709 4710 u8 reserved_at_60[0x60]; 4711 4712 u8 clear[0x1]; 4713 u8 reserved_at_c1[0x1f]; 4714 4715 u8 reserved_at_e0[0x20]; 4716 }; 4717 4718 struct mlx5_ifc_query_tis_out_bits { 4719 u8 status[0x8]; 4720 u8 reserved_at_8[0x18]; 4721 4722 u8 syndrome[0x20]; 4723 4724 u8 reserved_at_40[0x40]; 4725 4726 struct mlx5_ifc_tisc_bits tis_context; 4727 }; 4728 4729 struct mlx5_ifc_query_tis_in_bits { 4730 u8 opcode[0x10]; 4731 u8 reserved_at_10[0x10]; 4732 4733 u8 reserved_at_20[0x10]; 4734 u8 op_mod[0x10]; 4735 4736 u8 reserved_at_40[0x8]; 4737 u8 tisn[0x18]; 4738 4739 u8 reserved_at_60[0x20]; 4740 }; 4741 4742 struct mlx5_ifc_query_tir_out_bits { 4743 u8 status[0x8]; 4744 u8 reserved_at_8[0x18]; 4745 4746 u8 syndrome[0x20]; 4747 4748 u8 reserved_at_40[0xc0]; 4749 4750 struct mlx5_ifc_tirc_bits tir_context; 4751 }; 4752 4753 struct mlx5_ifc_query_tir_in_bits { 4754 u8 opcode[0x10]; 4755 u8 reserved_at_10[0x10]; 4756 4757 u8 reserved_at_20[0x10]; 4758 u8 op_mod[0x10]; 4759 4760 u8 reserved_at_40[0x8]; 4761 u8 tirn[0x18]; 4762 4763 u8 reserved_at_60[0x20]; 4764 }; 4765 4766 struct mlx5_ifc_query_srq_out_bits { 4767 u8 status[0x8]; 4768 u8 reserved_at_8[0x18]; 4769 4770 u8 syndrome[0x20]; 4771 4772 u8 reserved_at_40[0x40]; 4773 4774 struct mlx5_ifc_srqc_bits srq_context_entry; 4775 4776 u8 reserved_at_280[0x600]; 4777 4778 u8 pas[][0x40]; 4779 }; 4780 4781 struct mlx5_ifc_query_srq_in_bits { 4782 u8 opcode[0x10]; 4783 u8 reserved_at_10[0x10]; 4784 4785 u8 reserved_at_20[0x10]; 4786 u8 op_mod[0x10]; 4787 4788 u8 reserved_at_40[0x8]; 4789 u8 srqn[0x18]; 4790 4791 u8 reserved_at_60[0x20]; 4792 }; 4793 4794 struct mlx5_ifc_query_sq_out_bits { 4795 u8 status[0x8]; 4796 u8 reserved_at_8[0x18]; 4797 4798 u8 syndrome[0x20]; 4799 4800 u8 reserved_at_40[0xc0]; 4801 4802 struct mlx5_ifc_sqc_bits sq_context; 4803 }; 4804 4805 struct mlx5_ifc_query_sq_in_bits { 4806 u8 opcode[0x10]; 4807 u8 reserved_at_10[0x10]; 4808 4809 u8 reserved_at_20[0x10]; 4810 u8 op_mod[0x10]; 4811 4812 u8 reserved_at_40[0x8]; 4813 u8 sqn[0x18]; 4814 4815 u8 reserved_at_60[0x20]; 4816 }; 4817 4818 struct mlx5_ifc_query_special_contexts_out_bits { 4819 u8 status[0x8]; 4820 u8 reserved_at_8[0x18]; 4821 4822 u8 syndrome[0x20]; 4823 4824 u8 dump_fill_mkey[0x20]; 4825 4826 u8 resd_lkey[0x20]; 4827 4828 u8 null_mkey[0x20]; 4829 4830 u8 reserved_at_a0[0x60]; 4831 }; 4832 4833 struct mlx5_ifc_query_special_contexts_in_bits { 4834 u8 opcode[0x10]; 4835 u8 reserved_at_10[0x10]; 4836 4837 u8 reserved_at_20[0x10]; 4838 u8 op_mod[0x10]; 4839 4840 u8 reserved_at_40[0x40]; 4841 }; 4842 4843 struct mlx5_ifc_query_scheduling_element_out_bits { 4844 u8 opcode[0x10]; 4845 u8 reserved_at_10[0x10]; 4846 4847 u8 reserved_at_20[0x10]; 4848 u8 op_mod[0x10]; 4849 4850 u8 reserved_at_40[0xc0]; 4851 4852 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4853 4854 u8 reserved_at_300[0x100]; 4855 }; 4856 4857 enum { 4858 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4859 SCHEDULING_HIERARCHY_NIC = 0x3, 4860 }; 4861 4862 struct mlx5_ifc_query_scheduling_element_in_bits { 4863 u8 opcode[0x10]; 4864 u8 reserved_at_10[0x10]; 4865 4866 u8 reserved_at_20[0x10]; 4867 u8 op_mod[0x10]; 4868 4869 u8 scheduling_hierarchy[0x8]; 4870 u8 reserved_at_48[0x18]; 4871 4872 u8 scheduling_element_id[0x20]; 4873 4874 u8 reserved_at_80[0x180]; 4875 }; 4876 4877 struct mlx5_ifc_query_rqt_out_bits { 4878 u8 status[0x8]; 4879 u8 reserved_at_8[0x18]; 4880 4881 u8 syndrome[0x20]; 4882 4883 u8 reserved_at_40[0xc0]; 4884 4885 struct mlx5_ifc_rqtc_bits rqt_context; 4886 }; 4887 4888 struct mlx5_ifc_query_rqt_in_bits { 4889 u8 opcode[0x10]; 4890 u8 reserved_at_10[0x10]; 4891 4892 u8 reserved_at_20[0x10]; 4893 u8 op_mod[0x10]; 4894 4895 u8 reserved_at_40[0x8]; 4896 u8 rqtn[0x18]; 4897 4898 u8 reserved_at_60[0x20]; 4899 }; 4900 4901 struct mlx5_ifc_query_rq_out_bits { 4902 u8 status[0x8]; 4903 u8 reserved_at_8[0x18]; 4904 4905 u8 syndrome[0x20]; 4906 4907 u8 reserved_at_40[0xc0]; 4908 4909 struct mlx5_ifc_rqc_bits rq_context; 4910 }; 4911 4912 struct mlx5_ifc_query_rq_in_bits { 4913 u8 opcode[0x10]; 4914 u8 reserved_at_10[0x10]; 4915 4916 u8 reserved_at_20[0x10]; 4917 u8 op_mod[0x10]; 4918 4919 u8 reserved_at_40[0x8]; 4920 u8 rqn[0x18]; 4921 4922 u8 reserved_at_60[0x20]; 4923 }; 4924 4925 struct mlx5_ifc_query_roce_address_out_bits { 4926 u8 status[0x8]; 4927 u8 reserved_at_8[0x18]; 4928 4929 u8 syndrome[0x20]; 4930 4931 u8 reserved_at_40[0x40]; 4932 4933 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4934 }; 4935 4936 struct mlx5_ifc_query_roce_address_in_bits { 4937 u8 opcode[0x10]; 4938 u8 reserved_at_10[0x10]; 4939 4940 u8 reserved_at_20[0x10]; 4941 u8 op_mod[0x10]; 4942 4943 u8 roce_address_index[0x10]; 4944 u8 reserved_at_50[0xc]; 4945 u8 vhca_port_num[0x4]; 4946 4947 u8 reserved_at_60[0x20]; 4948 }; 4949 4950 struct mlx5_ifc_query_rmp_out_bits { 4951 u8 status[0x8]; 4952 u8 reserved_at_8[0x18]; 4953 4954 u8 syndrome[0x20]; 4955 4956 u8 reserved_at_40[0xc0]; 4957 4958 struct mlx5_ifc_rmpc_bits rmp_context; 4959 }; 4960 4961 struct mlx5_ifc_query_rmp_in_bits { 4962 u8 opcode[0x10]; 4963 u8 reserved_at_10[0x10]; 4964 4965 u8 reserved_at_20[0x10]; 4966 u8 op_mod[0x10]; 4967 4968 u8 reserved_at_40[0x8]; 4969 u8 rmpn[0x18]; 4970 4971 u8 reserved_at_60[0x20]; 4972 }; 4973 4974 struct mlx5_ifc_query_qp_out_bits { 4975 u8 status[0x8]; 4976 u8 reserved_at_8[0x18]; 4977 4978 u8 syndrome[0x20]; 4979 4980 u8 reserved_at_40[0x20]; 4981 u8 ece[0x20]; 4982 4983 u8 opt_param_mask[0x20]; 4984 4985 u8 reserved_at_a0[0x20]; 4986 4987 struct mlx5_ifc_qpc_bits qpc; 4988 4989 u8 reserved_at_800[0x80]; 4990 4991 u8 pas[][0x40]; 4992 }; 4993 4994 struct mlx5_ifc_query_qp_in_bits { 4995 u8 opcode[0x10]; 4996 u8 reserved_at_10[0x10]; 4997 4998 u8 reserved_at_20[0x10]; 4999 u8 op_mod[0x10]; 5000 5001 u8 reserved_at_40[0x8]; 5002 u8 qpn[0x18]; 5003 5004 u8 reserved_at_60[0x20]; 5005 }; 5006 5007 struct mlx5_ifc_query_q_counter_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_at_8[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_at_40[0x40]; 5014 5015 u8 rx_write_requests[0x20]; 5016 5017 u8 reserved_at_a0[0x20]; 5018 5019 u8 rx_read_requests[0x20]; 5020 5021 u8 reserved_at_e0[0x20]; 5022 5023 u8 rx_atomic_requests[0x20]; 5024 5025 u8 reserved_at_120[0x20]; 5026 5027 u8 rx_dct_connect[0x20]; 5028 5029 u8 reserved_at_160[0x20]; 5030 5031 u8 out_of_buffer[0x20]; 5032 5033 u8 reserved_at_1a0[0x20]; 5034 5035 u8 out_of_sequence[0x20]; 5036 5037 u8 reserved_at_1e0[0x20]; 5038 5039 u8 duplicate_request[0x20]; 5040 5041 u8 reserved_at_220[0x20]; 5042 5043 u8 rnr_nak_retry_err[0x20]; 5044 5045 u8 reserved_at_260[0x20]; 5046 5047 u8 packet_seq_err[0x20]; 5048 5049 u8 reserved_at_2a0[0x20]; 5050 5051 u8 implied_nak_seq_err[0x20]; 5052 5053 u8 reserved_at_2e0[0x20]; 5054 5055 u8 local_ack_timeout_err[0x20]; 5056 5057 u8 reserved_at_320[0xa0]; 5058 5059 u8 resp_local_length_error[0x20]; 5060 5061 u8 req_local_length_error[0x20]; 5062 5063 u8 resp_local_qp_error[0x20]; 5064 5065 u8 local_operation_error[0x20]; 5066 5067 u8 resp_local_protection[0x20]; 5068 5069 u8 req_local_protection[0x20]; 5070 5071 u8 resp_cqe_error[0x20]; 5072 5073 u8 req_cqe_error[0x20]; 5074 5075 u8 req_mw_binding[0x20]; 5076 5077 u8 req_bad_response[0x20]; 5078 5079 u8 req_remote_invalid_request[0x20]; 5080 5081 u8 resp_remote_invalid_request[0x20]; 5082 5083 u8 req_remote_access_errors[0x20]; 5084 5085 u8 resp_remote_access_errors[0x20]; 5086 5087 u8 req_remote_operation_errors[0x20]; 5088 5089 u8 req_transport_retries_exceeded[0x20]; 5090 5091 u8 cq_overflow[0x20]; 5092 5093 u8 resp_cqe_flush_error[0x20]; 5094 5095 u8 req_cqe_flush_error[0x20]; 5096 5097 u8 reserved_at_620[0x20]; 5098 5099 u8 roce_adp_retrans[0x20]; 5100 5101 u8 roce_adp_retrans_to[0x20]; 5102 5103 u8 roce_slow_restart[0x20]; 5104 5105 u8 roce_slow_restart_cnps[0x20]; 5106 5107 u8 roce_slow_restart_trans[0x20]; 5108 5109 u8 reserved_at_6e0[0x120]; 5110 }; 5111 5112 struct mlx5_ifc_query_q_counter_in_bits { 5113 u8 opcode[0x10]; 5114 u8 reserved_at_10[0x10]; 5115 5116 u8 reserved_at_20[0x10]; 5117 u8 op_mod[0x10]; 5118 5119 u8 reserved_at_40[0x80]; 5120 5121 u8 clear[0x1]; 5122 u8 reserved_at_c1[0x1f]; 5123 5124 u8 reserved_at_e0[0x18]; 5125 u8 counter_set_id[0x8]; 5126 }; 5127 5128 struct mlx5_ifc_query_pages_out_bits { 5129 u8 status[0x8]; 5130 u8 reserved_at_8[0x18]; 5131 5132 u8 syndrome[0x20]; 5133 5134 u8 embedded_cpu_function[0x1]; 5135 u8 reserved_at_41[0xf]; 5136 u8 function_id[0x10]; 5137 5138 u8 num_pages[0x20]; 5139 }; 5140 5141 enum { 5142 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5143 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5144 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5145 }; 5146 5147 struct mlx5_ifc_query_pages_in_bits { 5148 u8 opcode[0x10]; 5149 u8 reserved_at_10[0x10]; 5150 5151 u8 reserved_at_20[0x10]; 5152 u8 op_mod[0x10]; 5153 5154 u8 embedded_cpu_function[0x1]; 5155 u8 reserved_at_41[0xf]; 5156 u8 function_id[0x10]; 5157 5158 u8 reserved_at_60[0x20]; 5159 }; 5160 5161 struct mlx5_ifc_query_nic_vport_context_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_at_8[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_at_40[0x40]; 5168 5169 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5170 }; 5171 5172 struct mlx5_ifc_query_nic_vport_context_in_bits { 5173 u8 opcode[0x10]; 5174 u8 reserved_at_10[0x10]; 5175 5176 u8 reserved_at_20[0x10]; 5177 u8 op_mod[0x10]; 5178 5179 u8 other_vport[0x1]; 5180 u8 reserved_at_41[0xf]; 5181 u8 vport_number[0x10]; 5182 5183 u8 reserved_at_60[0x5]; 5184 u8 allowed_list_type[0x3]; 5185 u8 reserved_at_68[0x18]; 5186 }; 5187 5188 struct mlx5_ifc_query_mkey_out_bits { 5189 u8 status[0x8]; 5190 u8 reserved_at_8[0x18]; 5191 5192 u8 syndrome[0x20]; 5193 5194 u8 reserved_at_40[0x40]; 5195 5196 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5197 5198 u8 reserved_at_280[0x600]; 5199 5200 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5201 5202 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5203 }; 5204 5205 struct mlx5_ifc_query_mkey_in_bits { 5206 u8 opcode[0x10]; 5207 u8 reserved_at_10[0x10]; 5208 5209 u8 reserved_at_20[0x10]; 5210 u8 op_mod[0x10]; 5211 5212 u8 reserved_at_40[0x8]; 5213 u8 mkey_index[0x18]; 5214 5215 u8 pg_access[0x1]; 5216 u8 reserved_at_61[0x1f]; 5217 }; 5218 5219 struct mlx5_ifc_query_mad_demux_out_bits { 5220 u8 status[0x8]; 5221 u8 reserved_at_8[0x18]; 5222 5223 u8 syndrome[0x20]; 5224 5225 u8 reserved_at_40[0x40]; 5226 5227 u8 mad_dumux_parameters_block[0x20]; 5228 }; 5229 5230 struct mlx5_ifc_query_mad_demux_in_bits { 5231 u8 opcode[0x10]; 5232 u8 reserved_at_10[0x10]; 5233 5234 u8 reserved_at_20[0x10]; 5235 u8 op_mod[0x10]; 5236 5237 u8 reserved_at_40[0x40]; 5238 }; 5239 5240 struct mlx5_ifc_query_l2_table_entry_out_bits { 5241 u8 status[0x8]; 5242 u8 reserved_at_8[0x18]; 5243 5244 u8 syndrome[0x20]; 5245 5246 u8 reserved_at_40[0xa0]; 5247 5248 u8 reserved_at_e0[0x13]; 5249 u8 vlan_valid[0x1]; 5250 u8 vlan[0xc]; 5251 5252 struct mlx5_ifc_mac_address_layout_bits mac_address; 5253 5254 u8 reserved_at_140[0xc0]; 5255 }; 5256 5257 struct mlx5_ifc_query_l2_table_entry_in_bits { 5258 u8 opcode[0x10]; 5259 u8 reserved_at_10[0x10]; 5260 5261 u8 reserved_at_20[0x10]; 5262 u8 op_mod[0x10]; 5263 5264 u8 reserved_at_40[0x60]; 5265 5266 u8 reserved_at_a0[0x8]; 5267 u8 table_index[0x18]; 5268 5269 u8 reserved_at_c0[0x140]; 5270 }; 5271 5272 struct mlx5_ifc_query_issi_out_bits { 5273 u8 status[0x8]; 5274 u8 reserved_at_8[0x18]; 5275 5276 u8 syndrome[0x20]; 5277 5278 u8 reserved_at_40[0x10]; 5279 u8 current_issi[0x10]; 5280 5281 u8 reserved_at_60[0xa0]; 5282 5283 u8 reserved_at_100[76][0x8]; 5284 u8 supported_issi_dw0[0x20]; 5285 }; 5286 5287 struct mlx5_ifc_query_issi_in_bits { 5288 u8 opcode[0x10]; 5289 u8 reserved_at_10[0x10]; 5290 5291 u8 reserved_at_20[0x10]; 5292 u8 op_mod[0x10]; 5293 5294 u8 reserved_at_40[0x40]; 5295 }; 5296 5297 struct mlx5_ifc_set_driver_version_out_bits { 5298 u8 status[0x8]; 5299 u8 reserved_0[0x18]; 5300 5301 u8 syndrome[0x20]; 5302 u8 reserved_1[0x40]; 5303 }; 5304 5305 struct mlx5_ifc_set_driver_version_in_bits { 5306 u8 opcode[0x10]; 5307 u8 reserved_0[0x10]; 5308 5309 u8 reserved_1[0x10]; 5310 u8 op_mod[0x10]; 5311 5312 u8 reserved_2[0x40]; 5313 u8 driver_version[64][0x8]; 5314 }; 5315 5316 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5317 u8 status[0x8]; 5318 u8 reserved_at_8[0x18]; 5319 5320 u8 syndrome[0x20]; 5321 5322 u8 reserved_at_40[0x40]; 5323 5324 struct mlx5_ifc_pkey_bits pkey[]; 5325 }; 5326 5327 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5328 u8 opcode[0x10]; 5329 u8 reserved_at_10[0x10]; 5330 5331 u8 reserved_at_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 other_vport[0x1]; 5335 u8 reserved_at_41[0xb]; 5336 u8 port_num[0x4]; 5337 u8 vport_number[0x10]; 5338 5339 u8 reserved_at_60[0x10]; 5340 u8 pkey_index[0x10]; 5341 }; 5342 5343 enum { 5344 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5345 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5346 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5347 }; 5348 5349 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5350 u8 status[0x8]; 5351 u8 reserved_at_8[0x18]; 5352 5353 u8 syndrome[0x20]; 5354 5355 u8 reserved_at_40[0x20]; 5356 5357 u8 gids_num[0x10]; 5358 u8 reserved_at_70[0x10]; 5359 5360 struct mlx5_ifc_array128_auto_bits gid[]; 5361 }; 5362 5363 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5364 u8 opcode[0x10]; 5365 u8 reserved_at_10[0x10]; 5366 5367 u8 reserved_at_20[0x10]; 5368 u8 op_mod[0x10]; 5369 5370 u8 other_vport[0x1]; 5371 u8 reserved_at_41[0xb]; 5372 u8 port_num[0x4]; 5373 u8 vport_number[0x10]; 5374 5375 u8 reserved_at_60[0x10]; 5376 u8 gid_index[0x10]; 5377 }; 5378 5379 struct mlx5_ifc_query_hca_vport_context_out_bits { 5380 u8 status[0x8]; 5381 u8 reserved_at_8[0x18]; 5382 5383 u8 syndrome[0x20]; 5384 5385 u8 reserved_at_40[0x40]; 5386 5387 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5388 }; 5389 5390 struct mlx5_ifc_query_hca_vport_context_in_bits { 5391 u8 opcode[0x10]; 5392 u8 reserved_at_10[0x10]; 5393 5394 u8 reserved_at_20[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 other_vport[0x1]; 5398 u8 reserved_at_41[0xb]; 5399 u8 port_num[0x4]; 5400 u8 vport_number[0x10]; 5401 5402 u8 reserved_at_60[0x20]; 5403 }; 5404 5405 struct mlx5_ifc_query_hca_cap_out_bits { 5406 u8 status[0x8]; 5407 u8 reserved_at_8[0x18]; 5408 5409 u8 syndrome[0x20]; 5410 5411 u8 reserved_at_40[0x40]; 5412 5413 union mlx5_ifc_hca_cap_union_bits capability; 5414 }; 5415 5416 struct mlx5_ifc_query_hca_cap_in_bits { 5417 u8 opcode[0x10]; 5418 u8 reserved_at_10[0x10]; 5419 5420 u8 reserved_at_20[0x10]; 5421 u8 op_mod[0x10]; 5422 5423 u8 other_function[0x1]; 5424 u8 reserved_at_41[0xf]; 5425 u8 function_id[0x10]; 5426 5427 u8 reserved_at_60[0x20]; 5428 }; 5429 5430 struct mlx5_ifc_other_hca_cap_bits { 5431 u8 roce[0x1]; 5432 u8 reserved_at_1[0x27f]; 5433 }; 5434 5435 struct mlx5_ifc_query_other_hca_cap_out_bits { 5436 u8 status[0x8]; 5437 u8 reserved_at_8[0x18]; 5438 5439 u8 syndrome[0x20]; 5440 5441 u8 reserved_at_40[0x40]; 5442 5443 struct mlx5_ifc_other_hca_cap_bits other_capability; 5444 }; 5445 5446 struct mlx5_ifc_query_other_hca_cap_in_bits { 5447 u8 opcode[0x10]; 5448 u8 reserved_at_10[0x10]; 5449 5450 u8 reserved_at_20[0x10]; 5451 u8 op_mod[0x10]; 5452 5453 u8 reserved_at_40[0x10]; 5454 u8 function_id[0x10]; 5455 5456 u8 reserved_at_60[0x20]; 5457 }; 5458 5459 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5460 u8 status[0x8]; 5461 u8 reserved_at_8[0x18]; 5462 5463 u8 syndrome[0x20]; 5464 5465 u8 reserved_at_40[0x40]; 5466 }; 5467 5468 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5469 u8 opcode[0x10]; 5470 u8 reserved_at_10[0x10]; 5471 5472 u8 reserved_at_20[0x10]; 5473 u8 op_mod[0x10]; 5474 5475 u8 reserved_at_40[0x10]; 5476 u8 function_id[0x10]; 5477 u8 field_select[0x20]; 5478 5479 struct mlx5_ifc_other_hca_cap_bits other_capability; 5480 }; 5481 5482 struct mlx5_ifc_flow_table_context_bits { 5483 u8 reformat_en[0x1]; 5484 u8 decap_en[0x1]; 5485 u8 sw_owner[0x1]; 5486 u8 termination_table[0x1]; 5487 u8 table_miss_action[0x4]; 5488 u8 level[0x8]; 5489 u8 reserved_at_10[0x8]; 5490 u8 log_size[0x8]; 5491 5492 u8 reserved_at_20[0x8]; 5493 u8 table_miss_id[0x18]; 5494 5495 u8 reserved_at_40[0x8]; 5496 u8 lag_master_next_table_id[0x18]; 5497 5498 u8 reserved_at_60[0x60]; 5499 5500 u8 sw_owner_icm_root_1[0x40]; 5501 5502 u8 sw_owner_icm_root_0[0x40]; 5503 5504 }; 5505 5506 struct mlx5_ifc_query_flow_table_out_bits { 5507 u8 status[0x8]; 5508 u8 reserved_at_8[0x18]; 5509 5510 u8 syndrome[0x20]; 5511 5512 u8 reserved_at_40[0x80]; 5513 5514 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5515 }; 5516 5517 struct mlx5_ifc_query_flow_table_in_bits { 5518 u8 opcode[0x10]; 5519 u8 reserved_at_10[0x10]; 5520 5521 u8 reserved_at_20[0x10]; 5522 u8 op_mod[0x10]; 5523 5524 u8 reserved_at_40[0x40]; 5525 5526 u8 table_type[0x8]; 5527 u8 reserved_at_88[0x18]; 5528 5529 u8 reserved_at_a0[0x8]; 5530 u8 table_id[0x18]; 5531 5532 u8 reserved_at_c0[0x140]; 5533 }; 5534 5535 struct mlx5_ifc_query_fte_out_bits { 5536 u8 status[0x8]; 5537 u8 reserved_at_8[0x18]; 5538 5539 u8 syndrome[0x20]; 5540 5541 u8 reserved_at_40[0x1c0]; 5542 5543 struct mlx5_ifc_flow_context_bits flow_context; 5544 }; 5545 5546 struct mlx5_ifc_query_fte_in_bits { 5547 u8 opcode[0x10]; 5548 u8 reserved_at_10[0x10]; 5549 5550 u8 reserved_at_20[0x10]; 5551 u8 op_mod[0x10]; 5552 5553 u8 reserved_at_40[0x40]; 5554 5555 u8 table_type[0x8]; 5556 u8 reserved_at_88[0x18]; 5557 5558 u8 reserved_at_a0[0x8]; 5559 u8 table_id[0x18]; 5560 5561 u8 reserved_at_c0[0x40]; 5562 5563 u8 flow_index[0x20]; 5564 5565 u8 reserved_at_120[0xe0]; 5566 }; 5567 5568 enum { 5569 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5570 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5571 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5572 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5573 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5574 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5575 }; 5576 5577 struct mlx5_ifc_query_flow_group_out_bits { 5578 u8 status[0x8]; 5579 u8 reserved_at_8[0x18]; 5580 5581 u8 syndrome[0x20]; 5582 5583 u8 reserved_at_40[0xa0]; 5584 5585 u8 start_flow_index[0x20]; 5586 5587 u8 reserved_at_100[0x20]; 5588 5589 u8 end_flow_index[0x20]; 5590 5591 u8 reserved_at_140[0xa0]; 5592 5593 u8 reserved_at_1e0[0x18]; 5594 u8 match_criteria_enable[0x8]; 5595 5596 struct mlx5_ifc_fte_match_param_bits match_criteria; 5597 5598 u8 reserved_at_1200[0xe00]; 5599 }; 5600 5601 struct mlx5_ifc_query_flow_group_in_bits { 5602 u8 opcode[0x10]; 5603 u8 reserved_at_10[0x10]; 5604 5605 u8 reserved_at_20[0x10]; 5606 u8 op_mod[0x10]; 5607 5608 u8 reserved_at_40[0x40]; 5609 5610 u8 table_type[0x8]; 5611 u8 reserved_at_88[0x18]; 5612 5613 u8 reserved_at_a0[0x8]; 5614 u8 table_id[0x18]; 5615 5616 u8 group_id[0x20]; 5617 5618 u8 reserved_at_e0[0x120]; 5619 }; 5620 5621 struct mlx5_ifc_query_flow_counter_out_bits { 5622 u8 status[0x8]; 5623 u8 reserved_at_8[0x18]; 5624 5625 u8 syndrome[0x20]; 5626 5627 u8 reserved_at_40[0x40]; 5628 5629 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5630 }; 5631 5632 struct mlx5_ifc_query_flow_counter_in_bits { 5633 u8 opcode[0x10]; 5634 u8 reserved_at_10[0x10]; 5635 5636 u8 reserved_at_20[0x10]; 5637 u8 op_mod[0x10]; 5638 5639 u8 reserved_at_40[0x80]; 5640 5641 u8 clear[0x1]; 5642 u8 reserved_at_c1[0xf]; 5643 u8 num_of_counters[0x10]; 5644 5645 u8 flow_counter_id[0x20]; 5646 }; 5647 5648 struct mlx5_ifc_query_esw_vport_context_out_bits { 5649 u8 status[0x8]; 5650 u8 reserved_at_8[0x18]; 5651 5652 u8 syndrome[0x20]; 5653 5654 u8 reserved_at_40[0x40]; 5655 5656 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5657 }; 5658 5659 struct mlx5_ifc_query_esw_vport_context_in_bits { 5660 u8 opcode[0x10]; 5661 u8 reserved_at_10[0x10]; 5662 5663 u8 reserved_at_20[0x10]; 5664 u8 op_mod[0x10]; 5665 5666 u8 other_vport[0x1]; 5667 u8 reserved_at_41[0xf]; 5668 u8 vport_number[0x10]; 5669 5670 u8 reserved_at_60[0x20]; 5671 }; 5672 5673 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5674 u8 status[0x8]; 5675 u8 reserved_at_8[0x18]; 5676 5677 u8 syndrome[0x20]; 5678 5679 u8 reserved_at_40[0x40]; 5680 }; 5681 5682 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5683 u8 reserved_at_0[0x1b]; 5684 u8 fdb_to_vport_reg_c_id[0x1]; 5685 u8 vport_cvlan_insert[0x1]; 5686 u8 vport_svlan_insert[0x1]; 5687 u8 vport_cvlan_strip[0x1]; 5688 u8 vport_svlan_strip[0x1]; 5689 }; 5690 5691 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5692 u8 opcode[0x10]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 reserved_at_20[0x10]; 5696 u8 op_mod[0x10]; 5697 5698 u8 other_vport[0x1]; 5699 u8 reserved_at_41[0xf]; 5700 u8 vport_number[0x10]; 5701 5702 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5703 5704 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5705 }; 5706 5707 struct mlx5_ifc_query_eq_out_bits { 5708 u8 status[0x8]; 5709 u8 reserved_at_8[0x18]; 5710 5711 u8 syndrome[0x20]; 5712 5713 u8 reserved_at_40[0x40]; 5714 5715 struct mlx5_ifc_eqc_bits eq_context_entry; 5716 5717 u8 reserved_at_280[0x40]; 5718 5719 u8 event_bitmask[0x40]; 5720 5721 u8 reserved_at_300[0x580]; 5722 5723 u8 pas[][0x40]; 5724 }; 5725 5726 struct mlx5_ifc_query_eq_in_bits { 5727 u8 opcode[0x10]; 5728 u8 reserved_at_10[0x10]; 5729 5730 u8 reserved_at_20[0x10]; 5731 u8 op_mod[0x10]; 5732 5733 u8 reserved_at_40[0x18]; 5734 u8 eq_number[0x8]; 5735 5736 u8 reserved_at_60[0x20]; 5737 }; 5738 5739 struct mlx5_ifc_packet_reformat_context_in_bits { 5740 u8 reserved_at_0[0x5]; 5741 u8 reformat_type[0x3]; 5742 u8 reserved_at_8[0xe]; 5743 u8 reformat_data_size[0xa]; 5744 5745 u8 reserved_at_20[0x10]; 5746 u8 reformat_data[2][0x8]; 5747 5748 u8 more_reformat_data[][0x8]; 5749 }; 5750 5751 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5752 u8 status[0x8]; 5753 u8 reserved_at_8[0x18]; 5754 5755 u8 syndrome[0x20]; 5756 5757 u8 reserved_at_40[0xa0]; 5758 5759 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5760 }; 5761 5762 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5763 u8 opcode[0x10]; 5764 u8 reserved_at_10[0x10]; 5765 5766 u8 reserved_at_20[0x10]; 5767 u8 op_mod[0x10]; 5768 5769 u8 packet_reformat_id[0x20]; 5770 5771 u8 reserved_at_60[0xa0]; 5772 }; 5773 5774 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5775 u8 status[0x8]; 5776 u8 reserved_at_8[0x18]; 5777 5778 u8 syndrome[0x20]; 5779 5780 u8 packet_reformat_id[0x20]; 5781 5782 u8 reserved_at_60[0x20]; 5783 }; 5784 5785 enum mlx5_reformat_ctx_type { 5786 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5787 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5788 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5789 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5790 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5791 }; 5792 5793 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5794 u8 opcode[0x10]; 5795 u8 reserved_at_10[0x10]; 5796 5797 u8 reserved_at_20[0x10]; 5798 u8 op_mod[0x10]; 5799 5800 u8 reserved_at_40[0xa0]; 5801 5802 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5803 }; 5804 5805 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5806 u8 status[0x8]; 5807 u8 reserved_at_8[0x18]; 5808 5809 u8 syndrome[0x20]; 5810 5811 u8 reserved_at_40[0x40]; 5812 }; 5813 5814 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5815 u8 opcode[0x10]; 5816 u8 reserved_at_10[0x10]; 5817 5818 u8 reserved_20[0x10]; 5819 u8 op_mod[0x10]; 5820 5821 u8 packet_reformat_id[0x20]; 5822 5823 u8 reserved_60[0x20]; 5824 }; 5825 5826 struct mlx5_ifc_set_action_in_bits { 5827 u8 action_type[0x4]; 5828 u8 field[0xc]; 5829 u8 reserved_at_10[0x3]; 5830 u8 offset[0x5]; 5831 u8 reserved_at_18[0x3]; 5832 u8 length[0x5]; 5833 5834 u8 data[0x20]; 5835 }; 5836 5837 struct mlx5_ifc_add_action_in_bits { 5838 u8 action_type[0x4]; 5839 u8 field[0xc]; 5840 u8 reserved_at_10[0x10]; 5841 5842 u8 data[0x20]; 5843 }; 5844 5845 struct mlx5_ifc_copy_action_in_bits { 5846 u8 action_type[0x4]; 5847 u8 src_field[0xc]; 5848 u8 reserved_at_10[0x3]; 5849 u8 src_offset[0x5]; 5850 u8 reserved_at_18[0x3]; 5851 u8 length[0x5]; 5852 5853 u8 reserved_at_20[0x4]; 5854 u8 dst_field[0xc]; 5855 u8 reserved_at_30[0x3]; 5856 u8 dst_offset[0x5]; 5857 u8 reserved_at_38[0x8]; 5858 }; 5859 5860 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5861 struct mlx5_ifc_set_action_in_bits set_action_in; 5862 struct mlx5_ifc_add_action_in_bits add_action_in; 5863 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5864 u8 reserved_at_0[0x40]; 5865 }; 5866 5867 enum { 5868 MLX5_ACTION_TYPE_SET = 0x1, 5869 MLX5_ACTION_TYPE_ADD = 0x2, 5870 MLX5_ACTION_TYPE_COPY = 0x3, 5871 }; 5872 5873 enum { 5874 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5875 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5876 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5877 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5878 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5879 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5880 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5881 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5882 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5883 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5884 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5885 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5886 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5887 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5888 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5889 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5890 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5891 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5892 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5893 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5894 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5895 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5896 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5897 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5898 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5899 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5900 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5901 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5902 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5903 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5904 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5905 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5906 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5907 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5908 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5909 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5910 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5911 }; 5912 5913 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5914 u8 status[0x8]; 5915 u8 reserved_at_8[0x18]; 5916 5917 u8 syndrome[0x20]; 5918 5919 u8 modify_header_id[0x20]; 5920 5921 u8 reserved_at_60[0x20]; 5922 }; 5923 5924 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5925 u8 opcode[0x10]; 5926 u8 reserved_at_10[0x10]; 5927 5928 u8 reserved_at_20[0x10]; 5929 u8 op_mod[0x10]; 5930 5931 u8 reserved_at_40[0x20]; 5932 5933 u8 table_type[0x8]; 5934 u8 reserved_at_68[0x10]; 5935 u8 num_of_actions[0x8]; 5936 5937 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5938 }; 5939 5940 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5941 u8 status[0x8]; 5942 u8 reserved_at_8[0x18]; 5943 5944 u8 syndrome[0x20]; 5945 5946 u8 reserved_at_40[0x40]; 5947 }; 5948 5949 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5950 u8 opcode[0x10]; 5951 u8 reserved_at_10[0x10]; 5952 5953 u8 reserved_at_20[0x10]; 5954 u8 op_mod[0x10]; 5955 5956 u8 modify_header_id[0x20]; 5957 5958 u8 reserved_at_60[0x20]; 5959 }; 5960 5961 struct mlx5_ifc_query_modify_header_context_in_bits { 5962 u8 opcode[0x10]; 5963 u8 uid[0x10]; 5964 5965 u8 reserved_at_20[0x10]; 5966 u8 op_mod[0x10]; 5967 5968 u8 modify_header_id[0x20]; 5969 5970 u8 reserved_at_60[0xa0]; 5971 }; 5972 5973 struct mlx5_ifc_query_dct_out_bits { 5974 u8 status[0x8]; 5975 u8 reserved_at_8[0x18]; 5976 5977 u8 syndrome[0x20]; 5978 5979 u8 reserved_at_40[0x40]; 5980 5981 struct mlx5_ifc_dctc_bits dct_context_entry; 5982 5983 u8 reserved_at_280[0x180]; 5984 }; 5985 5986 struct mlx5_ifc_query_dct_in_bits { 5987 u8 opcode[0x10]; 5988 u8 reserved_at_10[0x10]; 5989 5990 u8 reserved_at_20[0x10]; 5991 u8 op_mod[0x10]; 5992 5993 u8 reserved_at_40[0x8]; 5994 u8 dctn[0x18]; 5995 5996 u8 reserved_at_60[0x20]; 5997 }; 5998 5999 struct mlx5_ifc_query_cq_out_bits { 6000 u8 status[0x8]; 6001 u8 reserved_at_8[0x18]; 6002 6003 u8 syndrome[0x20]; 6004 6005 u8 reserved_at_40[0x40]; 6006 6007 struct mlx5_ifc_cqc_bits cq_context; 6008 6009 u8 reserved_at_280[0x600]; 6010 6011 u8 pas[][0x40]; 6012 }; 6013 6014 struct mlx5_ifc_query_cq_in_bits { 6015 u8 opcode[0x10]; 6016 u8 reserved_at_10[0x10]; 6017 6018 u8 reserved_at_20[0x10]; 6019 u8 op_mod[0x10]; 6020 6021 u8 reserved_at_40[0x8]; 6022 u8 cqn[0x18]; 6023 6024 u8 reserved_at_60[0x20]; 6025 }; 6026 6027 struct mlx5_ifc_query_cong_status_out_bits { 6028 u8 status[0x8]; 6029 u8 reserved_at_8[0x18]; 6030 6031 u8 syndrome[0x20]; 6032 6033 u8 reserved_at_40[0x20]; 6034 6035 u8 enable[0x1]; 6036 u8 tag_enable[0x1]; 6037 u8 reserved_at_62[0x1e]; 6038 }; 6039 6040 struct mlx5_ifc_query_cong_status_in_bits { 6041 u8 opcode[0x10]; 6042 u8 reserved_at_10[0x10]; 6043 6044 u8 reserved_at_20[0x10]; 6045 u8 op_mod[0x10]; 6046 6047 u8 reserved_at_40[0x18]; 6048 u8 priority[0x4]; 6049 u8 cong_protocol[0x4]; 6050 6051 u8 reserved_at_60[0x20]; 6052 }; 6053 6054 struct mlx5_ifc_query_cong_statistics_out_bits { 6055 u8 status[0x8]; 6056 u8 reserved_at_8[0x18]; 6057 6058 u8 syndrome[0x20]; 6059 6060 u8 reserved_at_40[0x40]; 6061 6062 u8 rp_cur_flows[0x20]; 6063 6064 u8 sum_flows[0x20]; 6065 6066 u8 rp_cnp_ignored_high[0x20]; 6067 6068 u8 rp_cnp_ignored_low[0x20]; 6069 6070 u8 rp_cnp_handled_high[0x20]; 6071 6072 u8 rp_cnp_handled_low[0x20]; 6073 6074 u8 reserved_at_140[0x100]; 6075 6076 u8 time_stamp_high[0x20]; 6077 6078 u8 time_stamp_low[0x20]; 6079 6080 u8 accumulators_period[0x20]; 6081 6082 u8 np_ecn_marked_roce_packets_high[0x20]; 6083 6084 u8 np_ecn_marked_roce_packets_low[0x20]; 6085 6086 u8 np_cnp_sent_high[0x20]; 6087 6088 u8 np_cnp_sent_low[0x20]; 6089 6090 u8 reserved_at_320[0x560]; 6091 }; 6092 6093 struct mlx5_ifc_query_cong_statistics_in_bits { 6094 u8 opcode[0x10]; 6095 u8 reserved_at_10[0x10]; 6096 6097 u8 reserved_at_20[0x10]; 6098 u8 op_mod[0x10]; 6099 6100 u8 clear[0x1]; 6101 u8 reserved_at_41[0x1f]; 6102 6103 u8 reserved_at_60[0x20]; 6104 }; 6105 6106 struct mlx5_ifc_query_cong_params_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_at_8[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_at_40[0x40]; 6113 6114 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6115 }; 6116 6117 struct mlx5_ifc_query_cong_params_in_bits { 6118 u8 opcode[0x10]; 6119 u8 reserved_at_10[0x10]; 6120 6121 u8 reserved_at_20[0x10]; 6122 u8 op_mod[0x10]; 6123 6124 u8 reserved_at_40[0x1c]; 6125 u8 cong_protocol[0x4]; 6126 6127 u8 reserved_at_60[0x20]; 6128 }; 6129 6130 struct mlx5_ifc_query_adapter_out_bits { 6131 u8 status[0x8]; 6132 u8 reserved_at_8[0x18]; 6133 6134 u8 syndrome[0x20]; 6135 6136 u8 reserved_at_40[0x40]; 6137 6138 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6139 }; 6140 6141 struct mlx5_ifc_query_adapter_in_bits { 6142 u8 opcode[0x10]; 6143 u8 reserved_at_10[0x10]; 6144 6145 u8 reserved_at_20[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 reserved_at_40[0x40]; 6149 }; 6150 6151 struct mlx5_ifc_qp_2rst_out_bits { 6152 u8 status[0x8]; 6153 u8 reserved_at_8[0x18]; 6154 6155 u8 syndrome[0x20]; 6156 6157 u8 reserved_at_40[0x40]; 6158 }; 6159 6160 struct mlx5_ifc_qp_2rst_in_bits { 6161 u8 opcode[0x10]; 6162 u8 uid[0x10]; 6163 6164 u8 reserved_at_20[0x10]; 6165 u8 op_mod[0x10]; 6166 6167 u8 reserved_at_40[0x8]; 6168 u8 qpn[0x18]; 6169 6170 u8 reserved_at_60[0x20]; 6171 }; 6172 6173 struct mlx5_ifc_qp_2err_out_bits { 6174 u8 status[0x8]; 6175 u8 reserved_at_8[0x18]; 6176 6177 u8 syndrome[0x20]; 6178 6179 u8 reserved_at_40[0x40]; 6180 }; 6181 6182 struct mlx5_ifc_qp_2err_in_bits { 6183 u8 opcode[0x10]; 6184 u8 uid[0x10]; 6185 6186 u8 reserved_at_20[0x10]; 6187 u8 op_mod[0x10]; 6188 6189 u8 reserved_at_40[0x8]; 6190 u8 qpn[0x18]; 6191 6192 u8 reserved_at_60[0x20]; 6193 }; 6194 6195 struct mlx5_ifc_page_fault_resume_out_bits { 6196 u8 status[0x8]; 6197 u8 reserved_at_8[0x18]; 6198 6199 u8 syndrome[0x20]; 6200 6201 u8 reserved_at_40[0x40]; 6202 }; 6203 6204 struct mlx5_ifc_page_fault_resume_in_bits { 6205 u8 opcode[0x10]; 6206 u8 reserved_at_10[0x10]; 6207 6208 u8 reserved_at_20[0x10]; 6209 u8 op_mod[0x10]; 6210 6211 u8 error[0x1]; 6212 u8 reserved_at_41[0x4]; 6213 u8 page_fault_type[0x3]; 6214 u8 wq_number[0x18]; 6215 6216 u8 reserved_at_60[0x8]; 6217 u8 token[0x18]; 6218 }; 6219 6220 struct mlx5_ifc_nop_out_bits { 6221 u8 status[0x8]; 6222 u8 reserved_at_8[0x18]; 6223 6224 u8 syndrome[0x20]; 6225 6226 u8 reserved_at_40[0x40]; 6227 }; 6228 6229 struct mlx5_ifc_nop_in_bits { 6230 u8 opcode[0x10]; 6231 u8 reserved_at_10[0x10]; 6232 6233 u8 reserved_at_20[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 reserved_at_40[0x40]; 6237 }; 6238 6239 struct mlx5_ifc_modify_vport_state_out_bits { 6240 u8 status[0x8]; 6241 u8 reserved_at_8[0x18]; 6242 6243 u8 syndrome[0x20]; 6244 6245 u8 reserved_at_40[0x40]; 6246 }; 6247 6248 struct mlx5_ifc_modify_vport_state_in_bits { 6249 u8 opcode[0x10]; 6250 u8 reserved_at_10[0x10]; 6251 6252 u8 reserved_at_20[0x10]; 6253 u8 op_mod[0x10]; 6254 6255 u8 other_vport[0x1]; 6256 u8 reserved_at_41[0xf]; 6257 u8 vport_number[0x10]; 6258 6259 u8 reserved_at_60[0x18]; 6260 u8 admin_state[0x4]; 6261 u8 reserved_at_7c[0x4]; 6262 }; 6263 6264 struct mlx5_ifc_modify_tis_out_bits { 6265 u8 status[0x8]; 6266 u8 reserved_at_8[0x18]; 6267 6268 u8 syndrome[0x20]; 6269 6270 u8 reserved_at_40[0x40]; 6271 }; 6272 6273 struct mlx5_ifc_modify_tis_bitmask_bits { 6274 u8 reserved_at_0[0x20]; 6275 6276 u8 reserved_at_20[0x1d]; 6277 u8 lag_tx_port_affinity[0x1]; 6278 u8 strict_lag_tx_port_affinity[0x1]; 6279 u8 prio[0x1]; 6280 }; 6281 6282 struct mlx5_ifc_modify_tis_in_bits { 6283 u8 opcode[0x10]; 6284 u8 uid[0x10]; 6285 6286 u8 reserved_at_20[0x10]; 6287 u8 op_mod[0x10]; 6288 6289 u8 reserved_at_40[0x8]; 6290 u8 tisn[0x18]; 6291 6292 u8 reserved_at_60[0x20]; 6293 6294 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6295 6296 u8 reserved_at_c0[0x40]; 6297 6298 struct mlx5_ifc_tisc_bits ctx; 6299 }; 6300 6301 struct mlx5_ifc_modify_tir_bitmask_bits { 6302 u8 reserved_at_0[0x20]; 6303 6304 u8 reserved_at_20[0x1b]; 6305 u8 self_lb_en[0x1]; 6306 u8 reserved_at_3c[0x1]; 6307 u8 hash[0x1]; 6308 u8 reserved_at_3e[0x1]; 6309 u8 lro[0x1]; 6310 }; 6311 6312 struct mlx5_ifc_modify_tir_out_bits { 6313 u8 status[0x8]; 6314 u8 reserved_at_8[0x18]; 6315 6316 u8 syndrome[0x20]; 6317 6318 u8 reserved_at_40[0x40]; 6319 }; 6320 6321 struct mlx5_ifc_modify_tir_in_bits { 6322 u8 opcode[0x10]; 6323 u8 uid[0x10]; 6324 6325 u8 reserved_at_20[0x10]; 6326 u8 op_mod[0x10]; 6327 6328 u8 reserved_at_40[0x8]; 6329 u8 tirn[0x18]; 6330 6331 u8 reserved_at_60[0x20]; 6332 6333 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6334 6335 u8 reserved_at_c0[0x40]; 6336 6337 struct mlx5_ifc_tirc_bits ctx; 6338 }; 6339 6340 struct mlx5_ifc_modify_sq_out_bits { 6341 u8 status[0x8]; 6342 u8 reserved_at_8[0x18]; 6343 6344 u8 syndrome[0x20]; 6345 6346 u8 reserved_at_40[0x40]; 6347 }; 6348 6349 struct mlx5_ifc_modify_sq_in_bits { 6350 u8 opcode[0x10]; 6351 u8 uid[0x10]; 6352 6353 u8 reserved_at_20[0x10]; 6354 u8 op_mod[0x10]; 6355 6356 u8 sq_state[0x4]; 6357 u8 reserved_at_44[0x4]; 6358 u8 sqn[0x18]; 6359 6360 u8 reserved_at_60[0x20]; 6361 6362 u8 modify_bitmask[0x40]; 6363 6364 u8 reserved_at_c0[0x40]; 6365 6366 struct mlx5_ifc_sqc_bits ctx; 6367 }; 6368 6369 struct mlx5_ifc_modify_scheduling_element_out_bits { 6370 u8 status[0x8]; 6371 u8 reserved_at_8[0x18]; 6372 6373 u8 syndrome[0x20]; 6374 6375 u8 reserved_at_40[0x1c0]; 6376 }; 6377 6378 enum { 6379 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6380 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6381 }; 6382 6383 struct mlx5_ifc_modify_scheduling_element_in_bits { 6384 u8 opcode[0x10]; 6385 u8 reserved_at_10[0x10]; 6386 6387 u8 reserved_at_20[0x10]; 6388 u8 op_mod[0x10]; 6389 6390 u8 scheduling_hierarchy[0x8]; 6391 u8 reserved_at_48[0x18]; 6392 6393 u8 scheduling_element_id[0x20]; 6394 6395 u8 reserved_at_80[0x20]; 6396 6397 u8 modify_bitmask[0x20]; 6398 6399 u8 reserved_at_c0[0x40]; 6400 6401 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6402 6403 u8 reserved_at_300[0x100]; 6404 }; 6405 6406 struct mlx5_ifc_modify_rqt_out_bits { 6407 u8 status[0x8]; 6408 u8 reserved_at_8[0x18]; 6409 6410 u8 syndrome[0x20]; 6411 6412 u8 reserved_at_40[0x40]; 6413 }; 6414 6415 struct mlx5_ifc_rqt_bitmask_bits { 6416 u8 reserved_at_0[0x20]; 6417 6418 u8 reserved_at_20[0x1f]; 6419 u8 rqn_list[0x1]; 6420 }; 6421 6422 struct mlx5_ifc_modify_rqt_in_bits { 6423 u8 opcode[0x10]; 6424 u8 uid[0x10]; 6425 6426 u8 reserved_at_20[0x10]; 6427 u8 op_mod[0x10]; 6428 6429 u8 reserved_at_40[0x8]; 6430 u8 rqtn[0x18]; 6431 6432 u8 reserved_at_60[0x20]; 6433 6434 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6435 6436 u8 reserved_at_c0[0x40]; 6437 6438 struct mlx5_ifc_rqtc_bits ctx; 6439 }; 6440 6441 struct mlx5_ifc_modify_rq_out_bits { 6442 u8 status[0x8]; 6443 u8 reserved_at_8[0x18]; 6444 6445 u8 syndrome[0x20]; 6446 6447 u8 reserved_at_40[0x40]; 6448 }; 6449 6450 enum { 6451 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6452 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6453 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6454 }; 6455 6456 struct mlx5_ifc_modify_rq_in_bits { 6457 u8 opcode[0x10]; 6458 u8 uid[0x10]; 6459 6460 u8 reserved_at_20[0x10]; 6461 u8 op_mod[0x10]; 6462 6463 u8 rq_state[0x4]; 6464 u8 reserved_at_44[0x4]; 6465 u8 rqn[0x18]; 6466 6467 u8 reserved_at_60[0x20]; 6468 6469 u8 modify_bitmask[0x40]; 6470 6471 u8 reserved_at_c0[0x40]; 6472 6473 struct mlx5_ifc_rqc_bits ctx; 6474 }; 6475 6476 struct mlx5_ifc_modify_rmp_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_at_8[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_at_40[0x40]; 6483 }; 6484 6485 struct mlx5_ifc_rmp_bitmask_bits { 6486 u8 reserved_at_0[0x20]; 6487 6488 u8 reserved_at_20[0x1f]; 6489 u8 lwm[0x1]; 6490 }; 6491 6492 struct mlx5_ifc_modify_rmp_in_bits { 6493 u8 opcode[0x10]; 6494 u8 uid[0x10]; 6495 6496 u8 reserved_at_20[0x10]; 6497 u8 op_mod[0x10]; 6498 6499 u8 rmp_state[0x4]; 6500 u8 reserved_at_44[0x4]; 6501 u8 rmpn[0x18]; 6502 6503 u8 reserved_at_60[0x20]; 6504 6505 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6506 6507 u8 reserved_at_c0[0x40]; 6508 6509 struct mlx5_ifc_rmpc_bits ctx; 6510 }; 6511 6512 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6513 u8 status[0x8]; 6514 u8 reserved_at_8[0x18]; 6515 6516 u8 syndrome[0x20]; 6517 6518 u8 reserved_at_40[0x40]; 6519 }; 6520 6521 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6522 u8 reserved_at_0[0x12]; 6523 u8 affiliation[0x1]; 6524 u8 reserved_at_13[0x1]; 6525 u8 disable_uc_local_lb[0x1]; 6526 u8 disable_mc_local_lb[0x1]; 6527 u8 node_guid[0x1]; 6528 u8 port_guid[0x1]; 6529 u8 min_inline[0x1]; 6530 u8 mtu[0x1]; 6531 u8 change_event[0x1]; 6532 u8 promisc[0x1]; 6533 u8 permanent_address[0x1]; 6534 u8 addresses_list[0x1]; 6535 u8 roce_en[0x1]; 6536 u8 reserved_at_1f[0x1]; 6537 }; 6538 6539 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6540 u8 opcode[0x10]; 6541 u8 reserved_at_10[0x10]; 6542 6543 u8 reserved_at_20[0x10]; 6544 u8 op_mod[0x10]; 6545 6546 u8 other_vport[0x1]; 6547 u8 reserved_at_41[0xf]; 6548 u8 vport_number[0x10]; 6549 6550 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6551 6552 u8 reserved_at_80[0x780]; 6553 6554 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6555 }; 6556 6557 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6558 u8 status[0x8]; 6559 u8 reserved_at_8[0x18]; 6560 6561 u8 syndrome[0x20]; 6562 6563 u8 reserved_at_40[0x40]; 6564 }; 6565 6566 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_at_10[0x10]; 6569 6570 u8 reserved_at_20[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 other_vport[0x1]; 6574 u8 reserved_at_41[0xb]; 6575 u8 port_num[0x4]; 6576 u8 vport_number[0x10]; 6577 6578 u8 reserved_at_60[0x20]; 6579 6580 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6581 }; 6582 6583 struct mlx5_ifc_modify_cq_out_bits { 6584 u8 status[0x8]; 6585 u8 reserved_at_8[0x18]; 6586 6587 u8 syndrome[0x20]; 6588 6589 u8 reserved_at_40[0x40]; 6590 }; 6591 6592 enum { 6593 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6594 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6595 }; 6596 6597 struct mlx5_ifc_modify_cq_in_bits { 6598 u8 opcode[0x10]; 6599 u8 uid[0x10]; 6600 6601 u8 reserved_at_20[0x10]; 6602 u8 op_mod[0x10]; 6603 6604 u8 reserved_at_40[0x8]; 6605 u8 cqn[0x18]; 6606 6607 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6608 6609 struct mlx5_ifc_cqc_bits cq_context; 6610 6611 u8 reserved_at_280[0x60]; 6612 6613 u8 cq_umem_valid[0x1]; 6614 u8 reserved_at_2e1[0x1f]; 6615 6616 u8 reserved_at_300[0x580]; 6617 6618 u8 pas[][0x40]; 6619 }; 6620 6621 struct mlx5_ifc_modify_cong_status_out_bits { 6622 u8 status[0x8]; 6623 u8 reserved_at_8[0x18]; 6624 6625 u8 syndrome[0x20]; 6626 6627 u8 reserved_at_40[0x40]; 6628 }; 6629 6630 struct mlx5_ifc_modify_cong_status_in_bits { 6631 u8 opcode[0x10]; 6632 u8 reserved_at_10[0x10]; 6633 6634 u8 reserved_at_20[0x10]; 6635 u8 op_mod[0x10]; 6636 6637 u8 reserved_at_40[0x18]; 6638 u8 priority[0x4]; 6639 u8 cong_protocol[0x4]; 6640 6641 u8 enable[0x1]; 6642 u8 tag_enable[0x1]; 6643 u8 reserved_at_62[0x1e]; 6644 }; 6645 6646 struct mlx5_ifc_modify_cong_params_out_bits { 6647 u8 status[0x8]; 6648 u8 reserved_at_8[0x18]; 6649 6650 u8 syndrome[0x20]; 6651 6652 u8 reserved_at_40[0x40]; 6653 }; 6654 6655 struct mlx5_ifc_modify_cong_params_in_bits { 6656 u8 opcode[0x10]; 6657 u8 reserved_at_10[0x10]; 6658 6659 u8 reserved_at_20[0x10]; 6660 u8 op_mod[0x10]; 6661 6662 u8 reserved_at_40[0x1c]; 6663 u8 cong_protocol[0x4]; 6664 6665 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6666 6667 u8 reserved_at_80[0x80]; 6668 6669 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6670 }; 6671 6672 struct mlx5_ifc_manage_pages_out_bits { 6673 u8 status[0x8]; 6674 u8 reserved_at_8[0x18]; 6675 6676 u8 syndrome[0x20]; 6677 6678 u8 output_num_entries[0x20]; 6679 6680 u8 reserved_at_60[0x20]; 6681 6682 u8 pas[][0x40]; 6683 }; 6684 6685 enum { 6686 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6687 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6688 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6689 }; 6690 6691 struct mlx5_ifc_manage_pages_in_bits { 6692 u8 opcode[0x10]; 6693 u8 reserved_at_10[0x10]; 6694 6695 u8 reserved_at_20[0x10]; 6696 u8 op_mod[0x10]; 6697 6698 u8 embedded_cpu_function[0x1]; 6699 u8 reserved_at_41[0xf]; 6700 u8 function_id[0x10]; 6701 6702 u8 input_num_entries[0x20]; 6703 6704 u8 pas[][0x40]; 6705 }; 6706 6707 struct mlx5_ifc_mad_ifc_out_bits { 6708 u8 status[0x8]; 6709 u8 reserved_at_8[0x18]; 6710 6711 u8 syndrome[0x20]; 6712 6713 u8 reserved_at_40[0x40]; 6714 6715 u8 response_mad_packet[256][0x8]; 6716 }; 6717 6718 struct mlx5_ifc_mad_ifc_in_bits { 6719 u8 opcode[0x10]; 6720 u8 reserved_at_10[0x10]; 6721 6722 u8 reserved_at_20[0x10]; 6723 u8 op_mod[0x10]; 6724 6725 u8 remote_lid[0x10]; 6726 u8 reserved_at_50[0x8]; 6727 u8 port[0x8]; 6728 6729 u8 reserved_at_60[0x20]; 6730 6731 u8 mad[256][0x8]; 6732 }; 6733 6734 struct mlx5_ifc_init_hca_out_bits { 6735 u8 status[0x8]; 6736 u8 reserved_at_8[0x18]; 6737 6738 u8 syndrome[0x20]; 6739 6740 u8 reserved_at_40[0x40]; 6741 }; 6742 6743 struct mlx5_ifc_init_hca_in_bits { 6744 u8 opcode[0x10]; 6745 u8 reserved_at_10[0x10]; 6746 6747 u8 reserved_at_20[0x10]; 6748 u8 op_mod[0x10]; 6749 6750 u8 reserved_at_40[0x40]; 6751 u8 sw_owner_id[4][0x20]; 6752 }; 6753 6754 struct mlx5_ifc_init2rtr_qp_out_bits { 6755 u8 status[0x8]; 6756 u8 reserved_at_8[0x18]; 6757 6758 u8 syndrome[0x20]; 6759 6760 u8 reserved_at_40[0x20]; 6761 u8 ece[0x20]; 6762 }; 6763 6764 struct mlx5_ifc_init2rtr_qp_in_bits { 6765 u8 opcode[0x10]; 6766 u8 uid[0x10]; 6767 6768 u8 reserved_at_20[0x10]; 6769 u8 op_mod[0x10]; 6770 6771 u8 reserved_at_40[0x8]; 6772 u8 qpn[0x18]; 6773 6774 u8 reserved_at_60[0x20]; 6775 6776 u8 opt_param_mask[0x20]; 6777 6778 u8 ece[0x20]; 6779 6780 struct mlx5_ifc_qpc_bits qpc; 6781 6782 u8 reserved_at_800[0x80]; 6783 }; 6784 6785 struct mlx5_ifc_init2init_qp_out_bits { 6786 u8 status[0x8]; 6787 u8 reserved_at_8[0x18]; 6788 6789 u8 syndrome[0x20]; 6790 6791 u8 reserved_at_40[0x20]; 6792 u8 ece[0x20]; 6793 }; 6794 6795 struct mlx5_ifc_init2init_qp_in_bits { 6796 u8 opcode[0x10]; 6797 u8 uid[0x10]; 6798 6799 u8 reserved_at_20[0x10]; 6800 u8 op_mod[0x10]; 6801 6802 u8 reserved_at_40[0x8]; 6803 u8 qpn[0x18]; 6804 6805 u8 reserved_at_60[0x20]; 6806 6807 u8 opt_param_mask[0x20]; 6808 6809 u8 ece[0x20]; 6810 6811 struct mlx5_ifc_qpc_bits qpc; 6812 6813 u8 reserved_at_800[0x80]; 6814 }; 6815 6816 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_at_8[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_at_40[0x40]; 6823 6824 u8 packet_headers_log[128][0x8]; 6825 6826 u8 packet_syndrome[64][0x8]; 6827 }; 6828 6829 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6830 u8 opcode[0x10]; 6831 u8 reserved_at_10[0x10]; 6832 6833 u8 reserved_at_20[0x10]; 6834 u8 op_mod[0x10]; 6835 6836 u8 reserved_at_40[0x40]; 6837 }; 6838 6839 struct mlx5_ifc_gen_eqe_in_bits { 6840 u8 opcode[0x10]; 6841 u8 reserved_at_10[0x10]; 6842 6843 u8 reserved_at_20[0x10]; 6844 u8 op_mod[0x10]; 6845 6846 u8 reserved_at_40[0x18]; 6847 u8 eq_number[0x8]; 6848 6849 u8 reserved_at_60[0x20]; 6850 6851 u8 eqe[64][0x8]; 6852 }; 6853 6854 struct mlx5_ifc_gen_eq_out_bits { 6855 u8 status[0x8]; 6856 u8 reserved_at_8[0x18]; 6857 6858 u8 syndrome[0x20]; 6859 6860 u8 reserved_at_40[0x40]; 6861 }; 6862 6863 struct mlx5_ifc_enable_hca_out_bits { 6864 u8 status[0x8]; 6865 u8 reserved_at_8[0x18]; 6866 6867 u8 syndrome[0x20]; 6868 6869 u8 reserved_at_40[0x20]; 6870 }; 6871 6872 struct mlx5_ifc_enable_hca_in_bits { 6873 u8 opcode[0x10]; 6874 u8 reserved_at_10[0x10]; 6875 6876 u8 reserved_at_20[0x10]; 6877 u8 op_mod[0x10]; 6878 6879 u8 embedded_cpu_function[0x1]; 6880 u8 reserved_at_41[0xf]; 6881 u8 function_id[0x10]; 6882 6883 u8 reserved_at_60[0x20]; 6884 }; 6885 6886 struct mlx5_ifc_drain_dct_out_bits { 6887 u8 status[0x8]; 6888 u8 reserved_at_8[0x18]; 6889 6890 u8 syndrome[0x20]; 6891 6892 u8 reserved_at_40[0x40]; 6893 }; 6894 6895 struct mlx5_ifc_drain_dct_in_bits { 6896 u8 opcode[0x10]; 6897 u8 uid[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 reserved_at_40[0x8]; 6903 u8 dctn[0x18]; 6904 6905 u8 reserved_at_60[0x20]; 6906 }; 6907 6908 struct mlx5_ifc_disable_hca_out_bits { 6909 u8 status[0x8]; 6910 u8 reserved_at_8[0x18]; 6911 6912 u8 syndrome[0x20]; 6913 6914 u8 reserved_at_40[0x20]; 6915 }; 6916 6917 struct mlx5_ifc_disable_hca_in_bits { 6918 u8 opcode[0x10]; 6919 u8 reserved_at_10[0x10]; 6920 6921 u8 reserved_at_20[0x10]; 6922 u8 op_mod[0x10]; 6923 6924 u8 embedded_cpu_function[0x1]; 6925 u8 reserved_at_41[0xf]; 6926 u8 function_id[0x10]; 6927 6928 u8 reserved_at_60[0x20]; 6929 }; 6930 6931 struct mlx5_ifc_detach_from_mcg_out_bits { 6932 u8 status[0x8]; 6933 u8 reserved_at_8[0x18]; 6934 6935 u8 syndrome[0x20]; 6936 6937 u8 reserved_at_40[0x40]; 6938 }; 6939 6940 struct mlx5_ifc_detach_from_mcg_in_bits { 6941 u8 opcode[0x10]; 6942 u8 uid[0x10]; 6943 6944 u8 reserved_at_20[0x10]; 6945 u8 op_mod[0x10]; 6946 6947 u8 reserved_at_40[0x8]; 6948 u8 qpn[0x18]; 6949 6950 u8 reserved_at_60[0x20]; 6951 6952 u8 multicast_gid[16][0x8]; 6953 }; 6954 6955 struct mlx5_ifc_destroy_xrq_out_bits { 6956 u8 status[0x8]; 6957 u8 reserved_at_8[0x18]; 6958 6959 u8 syndrome[0x20]; 6960 6961 u8 reserved_at_40[0x40]; 6962 }; 6963 6964 struct mlx5_ifc_destroy_xrq_in_bits { 6965 u8 opcode[0x10]; 6966 u8 uid[0x10]; 6967 6968 u8 reserved_at_20[0x10]; 6969 u8 op_mod[0x10]; 6970 6971 u8 reserved_at_40[0x8]; 6972 u8 xrqn[0x18]; 6973 6974 u8 reserved_at_60[0x20]; 6975 }; 6976 6977 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6978 u8 status[0x8]; 6979 u8 reserved_at_8[0x18]; 6980 6981 u8 syndrome[0x20]; 6982 6983 u8 reserved_at_40[0x40]; 6984 }; 6985 6986 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6987 u8 opcode[0x10]; 6988 u8 uid[0x10]; 6989 6990 u8 reserved_at_20[0x10]; 6991 u8 op_mod[0x10]; 6992 6993 u8 reserved_at_40[0x8]; 6994 u8 xrc_srqn[0x18]; 6995 6996 u8 reserved_at_60[0x20]; 6997 }; 6998 6999 struct mlx5_ifc_destroy_tis_out_bits { 7000 u8 status[0x8]; 7001 u8 reserved_at_8[0x18]; 7002 7003 u8 syndrome[0x20]; 7004 7005 u8 reserved_at_40[0x40]; 7006 }; 7007 7008 struct mlx5_ifc_destroy_tis_in_bits { 7009 u8 opcode[0x10]; 7010 u8 uid[0x10]; 7011 7012 u8 reserved_at_20[0x10]; 7013 u8 op_mod[0x10]; 7014 7015 u8 reserved_at_40[0x8]; 7016 u8 tisn[0x18]; 7017 7018 u8 reserved_at_60[0x20]; 7019 }; 7020 7021 struct mlx5_ifc_destroy_tir_out_bits { 7022 u8 status[0x8]; 7023 u8 reserved_at_8[0x18]; 7024 7025 u8 syndrome[0x20]; 7026 7027 u8 reserved_at_40[0x40]; 7028 }; 7029 7030 struct mlx5_ifc_destroy_tir_in_bits { 7031 u8 opcode[0x10]; 7032 u8 uid[0x10]; 7033 7034 u8 reserved_at_20[0x10]; 7035 u8 op_mod[0x10]; 7036 7037 u8 reserved_at_40[0x8]; 7038 u8 tirn[0x18]; 7039 7040 u8 reserved_at_60[0x20]; 7041 }; 7042 7043 struct mlx5_ifc_destroy_srq_out_bits { 7044 u8 status[0x8]; 7045 u8 reserved_at_8[0x18]; 7046 7047 u8 syndrome[0x20]; 7048 7049 u8 reserved_at_40[0x40]; 7050 }; 7051 7052 struct mlx5_ifc_destroy_srq_in_bits { 7053 u8 opcode[0x10]; 7054 u8 uid[0x10]; 7055 7056 u8 reserved_at_20[0x10]; 7057 u8 op_mod[0x10]; 7058 7059 u8 reserved_at_40[0x8]; 7060 u8 srqn[0x18]; 7061 7062 u8 reserved_at_60[0x20]; 7063 }; 7064 7065 struct mlx5_ifc_destroy_sq_out_bits { 7066 u8 status[0x8]; 7067 u8 reserved_at_8[0x18]; 7068 7069 u8 syndrome[0x20]; 7070 7071 u8 reserved_at_40[0x40]; 7072 }; 7073 7074 struct mlx5_ifc_destroy_sq_in_bits { 7075 u8 opcode[0x10]; 7076 u8 uid[0x10]; 7077 7078 u8 reserved_at_20[0x10]; 7079 u8 op_mod[0x10]; 7080 7081 u8 reserved_at_40[0x8]; 7082 u8 sqn[0x18]; 7083 7084 u8 reserved_at_60[0x20]; 7085 }; 7086 7087 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7088 u8 status[0x8]; 7089 u8 reserved_at_8[0x18]; 7090 7091 u8 syndrome[0x20]; 7092 7093 u8 reserved_at_40[0x1c0]; 7094 }; 7095 7096 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7097 u8 opcode[0x10]; 7098 u8 reserved_at_10[0x10]; 7099 7100 u8 reserved_at_20[0x10]; 7101 u8 op_mod[0x10]; 7102 7103 u8 scheduling_hierarchy[0x8]; 7104 u8 reserved_at_48[0x18]; 7105 7106 u8 scheduling_element_id[0x20]; 7107 7108 u8 reserved_at_80[0x180]; 7109 }; 7110 7111 struct mlx5_ifc_destroy_rqt_out_bits { 7112 u8 status[0x8]; 7113 u8 reserved_at_8[0x18]; 7114 7115 u8 syndrome[0x20]; 7116 7117 u8 reserved_at_40[0x40]; 7118 }; 7119 7120 struct mlx5_ifc_destroy_rqt_in_bits { 7121 u8 opcode[0x10]; 7122 u8 uid[0x10]; 7123 7124 u8 reserved_at_20[0x10]; 7125 u8 op_mod[0x10]; 7126 7127 u8 reserved_at_40[0x8]; 7128 u8 rqtn[0x18]; 7129 7130 u8 reserved_at_60[0x20]; 7131 }; 7132 7133 struct mlx5_ifc_destroy_rq_out_bits { 7134 u8 status[0x8]; 7135 u8 reserved_at_8[0x18]; 7136 7137 u8 syndrome[0x20]; 7138 7139 u8 reserved_at_40[0x40]; 7140 }; 7141 7142 struct mlx5_ifc_destroy_rq_in_bits { 7143 u8 opcode[0x10]; 7144 u8 uid[0x10]; 7145 7146 u8 reserved_at_20[0x10]; 7147 u8 op_mod[0x10]; 7148 7149 u8 reserved_at_40[0x8]; 7150 u8 rqn[0x18]; 7151 7152 u8 reserved_at_60[0x20]; 7153 }; 7154 7155 struct mlx5_ifc_set_delay_drop_params_in_bits { 7156 u8 opcode[0x10]; 7157 u8 reserved_at_10[0x10]; 7158 7159 u8 reserved_at_20[0x10]; 7160 u8 op_mod[0x10]; 7161 7162 u8 reserved_at_40[0x20]; 7163 7164 u8 reserved_at_60[0x10]; 7165 u8 delay_drop_timeout[0x10]; 7166 }; 7167 7168 struct mlx5_ifc_set_delay_drop_params_out_bits { 7169 u8 status[0x8]; 7170 u8 reserved_at_8[0x18]; 7171 7172 u8 syndrome[0x20]; 7173 7174 u8 reserved_at_40[0x40]; 7175 }; 7176 7177 struct mlx5_ifc_destroy_rmp_out_bits { 7178 u8 status[0x8]; 7179 u8 reserved_at_8[0x18]; 7180 7181 u8 syndrome[0x20]; 7182 7183 u8 reserved_at_40[0x40]; 7184 }; 7185 7186 struct mlx5_ifc_destroy_rmp_in_bits { 7187 u8 opcode[0x10]; 7188 u8 uid[0x10]; 7189 7190 u8 reserved_at_20[0x10]; 7191 u8 op_mod[0x10]; 7192 7193 u8 reserved_at_40[0x8]; 7194 u8 rmpn[0x18]; 7195 7196 u8 reserved_at_60[0x20]; 7197 }; 7198 7199 struct mlx5_ifc_destroy_qp_out_bits { 7200 u8 status[0x8]; 7201 u8 reserved_at_8[0x18]; 7202 7203 u8 syndrome[0x20]; 7204 7205 u8 reserved_at_40[0x40]; 7206 }; 7207 7208 struct mlx5_ifc_destroy_qp_in_bits { 7209 u8 opcode[0x10]; 7210 u8 uid[0x10]; 7211 7212 u8 reserved_at_20[0x10]; 7213 u8 op_mod[0x10]; 7214 7215 u8 reserved_at_40[0x8]; 7216 u8 qpn[0x18]; 7217 7218 u8 reserved_at_60[0x20]; 7219 }; 7220 7221 struct mlx5_ifc_destroy_psv_out_bits { 7222 u8 status[0x8]; 7223 u8 reserved_at_8[0x18]; 7224 7225 u8 syndrome[0x20]; 7226 7227 u8 reserved_at_40[0x40]; 7228 }; 7229 7230 struct mlx5_ifc_destroy_psv_in_bits { 7231 u8 opcode[0x10]; 7232 u8 reserved_at_10[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 reserved_at_40[0x8]; 7238 u8 psvn[0x18]; 7239 7240 u8 reserved_at_60[0x20]; 7241 }; 7242 7243 struct mlx5_ifc_destroy_mkey_out_bits { 7244 u8 status[0x8]; 7245 u8 reserved_at_8[0x18]; 7246 7247 u8 syndrome[0x20]; 7248 7249 u8 reserved_at_40[0x40]; 7250 }; 7251 7252 struct mlx5_ifc_destroy_mkey_in_bits { 7253 u8 opcode[0x10]; 7254 u8 uid[0x10]; 7255 7256 u8 reserved_at_20[0x10]; 7257 u8 op_mod[0x10]; 7258 7259 u8 reserved_at_40[0x8]; 7260 u8 mkey_index[0x18]; 7261 7262 u8 reserved_at_60[0x20]; 7263 }; 7264 7265 struct mlx5_ifc_destroy_flow_table_out_bits { 7266 u8 status[0x8]; 7267 u8 reserved_at_8[0x18]; 7268 7269 u8 syndrome[0x20]; 7270 7271 u8 reserved_at_40[0x40]; 7272 }; 7273 7274 struct mlx5_ifc_destroy_flow_table_in_bits { 7275 u8 opcode[0x10]; 7276 u8 reserved_at_10[0x10]; 7277 7278 u8 reserved_at_20[0x10]; 7279 u8 op_mod[0x10]; 7280 7281 u8 other_vport[0x1]; 7282 u8 reserved_at_41[0xf]; 7283 u8 vport_number[0x10]; 7284 7285 u8 reserved_at_60[0x20]; 7286 7287 u8 table_type[0x8]; 7288 u8 reserved_at_88[0x18]; 7289 7290 u8 reserved_at_a0[0x8]; 7291 u8 table_id[0x18]; 7292 7293 u8 reserved_at_c0[0x140]; 7294 }; 7295 7296 struct mlx5_ifc_destroy_flow_group_out_bits { 7297 u8 status[0x8]; 7298 u8 reserved_at_8[0x18]; 7299 7300 u8 syndrome[0x20]; 7301 7302 u8 reserved_at_40[0x40]; 7303 }; 7304 7305 struct mlx5_ifc_destroy_flow_group_in_bits { 7306 u8 opcode[0x10]; 7307 u8 reserved_at_10[0x10]; 7308 7309 u8 reserved_at_20[0x10]; 7310 u8 op_mod[0x10]; 7311 7312 u8 other_vport[0x1]; 7313 u8 reserved_at_41[0xf]; 7314 u8 vport_number[0x10]; 7315 7316 u8 reserved_at_60[0x20]; 7317 7318 u8 table_type[0x8]; 7319 u8 reserved_at_88[0x18]; 7320 7321 u8 reserved_at_a0[0x8]; 7322 u8 table_id[0x18]; 7323 7324 u8 group_id[0x20]; 7325 7326 u8 reserved_at_e0[0x120]; 7327 }; 7328 7329 struct mlx5_ifc_destroy_eq_out_bits { 7330 u8 status[0x8]; 7331 u8 reserved_at_8[0x18]; 7332 7333 u8 syndrome[0x20]; 7334 7335 u8 reserved_at_40[0x40]; 7336 }; 7337 7338 struct mlx5_ifc_destroy_eq_in_bits { 7339 u8 opcode[0x10]; 7340 u8 reserved_at_10[0x10]; 7341 7342 u8 reserved_at_20[0x10]; 7343 u8 op_mod[0x10]; 7344 7345 u8 reserved_at_40[0x18]; 7346 u8 eq_number[0x8]; 7347 7348 u8 reserved_at_60[0x20]; 7349 }; 7350 7351 struct mlx5_ifc_destroy_dct_out_bits { 7352 u8 status[0x8]; 7353 u8 reserved_at_8[0x18]; 7354 7355 u8 syndrome[0x20]; 7356 7357 u8 reserved_at_40[0x40]; 7358 }; 7359 7360 struct mlx5_ifc_destroy_dct_in_bits { 7361 u8 opcode[0x10]; 7362 u8 uid[0x10]; 7363 7364 u8 reserved_at_20[0x10]; 7365 u8 op_mod[0x10]; 7366 7367 u8 reserved_at_40[0x8]; 7368 u8 dctn[0x18]; 7369 7370 u8 reserved_at_60[0x20]; 7371 }; 7372 7373 struct mlx5_ifc_destroy_cq_out_bits { 7374 u8 status[0x8]; 7375 u8 reserved_at_8[0x18]; 7376 7377 u8 syndrome[0x20]; 7378 7379 u8 reserved_at_40[0x40]; 7380 }; 7381 7382 struct mlx5_ifc_destroy_cq_in_bits { 7383 u8 opcode[0x10]; 7384 u8 uid[0x10]; 7385 7386 u8 reserved_at_20[0x10]; 7387 u8 op_mod[0x10]; 7388 7389 u8 reserved_at_40[0x8]; 7390 u8 cqn[0x18]; 7391 7392 u8 reserved_at_60[0x20]; 7393 }; 7394 7395 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7396 u8 status[0x8]; 7397 u8 reserved_at_8[0x18]; 7398 7399 u8 syndrome[0x20]; 7400 7401 u8 reserved_at_40[0x40]; 7402 }; 7403 7404 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7405 u8 opcode[0x10]; 7406 u8 reserved_at_10[0x10]; 7407 7408 u8 reserved_at_20[0x10]; 7409 u8 op_mod[0x10]; 7410 7411 u8 reserved_at_40[0x20]; 7412 7413 u8 reserved_at_60[0x10]; 7414 u8 vxlan_udp_port[0x10]; 7415 }; 7416 7417 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7418 u8 status[0x8]; 7419 u8 reserved_at_8[0x18]; 7420 7421 u8 syndrome[0x20]; 7422 7423 u8 reserved_at_40[0x40]; 7424 }; 7425 7426 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7427 u8 opcode[0x10]; 7428 u8 reserved_at_10[0x10]; 7429 7430 u8 reserved_at_20[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 reserved_at_40[0x60]; 7434 7435 u8 reserved_at_a0[0x8]; 7436 u8 table_index[0x18]; 7437 7438 u8 reserved_at_c0[0x140]; 7439 }; 7440 7441 struct mlx5_ifc_delete_fte_out_bits { 7442 u8 status[0x8]; 7443 u8 reserved_at_8[0x18]; 7444 7445 u8 syndrome[0x20]; 7446 7447 u8 reserved_at_40[0x40]; 7448 }; 7449 7450 struct mlx5_ifc_delete_fte_in_bits { 7451 u8 opcode[0x10]; 7452 u8 reserved_at_10[0x10]; 7453 7454 u8 reserved_at_20[0x10]; 7455 u8 op_mod[0x10]; 7456 7457 u8 other_vport[0x1]; 7458 u8 reserved_at_41[0xf]; 7459 u8 vport_number[0x10]; 7460 7461 u8 reserved_at_60[0x20]; 7462 7463 u8 table_type[0x8]; 7464 u8 reserved_at_88[0x18]; 7465 7466 u8 reserved_at_a0[0x8]; 7467 u8 table_id[0x18]; 7468 7469 u8 reserved_at_c0[0x40]; 7470 7471 u8 flow_index[0x20]; 7472 7473 u8 reserved_at_120[0xe0]; 7474 }; 7475 7476 struct mlx5_ifc_dealloc_xrcd_out_bits { 7477 u8 status[0x8]; 7478 u8 reserved_at_8[0x18]; 7479 7480 u8 syndrome[0x20]; 7481 7482 u8 reserved_at_40[0x40]; 7483 }; 7484 7485 struct mlx5_ifc_dealloc_xrcd_in_bits { 7486 u8 opcode[0x10]; 7487 u8 uid[0x10]; 7488 7489 u8 reserved_at_20[0x10]; 7490 u8 op_mod[0x10]; 7491 7492 u8 reserved_at_40[0x8]; 7493 u8 xrcd[0x18]; 7494 7495 u8 reserved_at_60[0x20]; 7496 }; 7497 7498 struct mlx5_ifc_dealloc_uar_out_bits { 7499 u8 status[0x8]; 7500 u8 reserved_at_8[0x18]; 7501 7502 u8 syndrome[0x20]; 7503 7504 u8 reserved_at_40[0x40]; 7505 }; 7506 7507 struct mlx5_ifc_dealloc_uar_in_bits { 7508 u8 opcode[0x10]; 7509 u8 reserved_at_10[0x10]; 7510 7511 u8 reserved_at_20[0x10]; 7512 u8 op_mod[0x10]; 7513 7514 u8 reserved_at_40[0x8]; 7515 u8 uar[0x18]; 7516 7517 u8 reserved_at_60[0x20]; 7518 }; 7519 7520 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7521 u8 status[0x8]; 7522 u8 reserved_at_8[0x18]; 7523 7524 u8 syndrome[0x20]; 7525 7526 u8 reserved_at_40[0x40]; 7527 }; 7528 7529 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7530 u8 opcode[0x10]; 7531 u8 uid[0x10]; 7532 7533 u8 reserved_at_20[0x10]; 7534 u8 op_mod[0x10]; 7535 7536 u8 reserved_at_40[0x8]; 7537 u8 transport_domain[0x18]; 7538 7539 u8 reserved_at_60[0x20]; 7540 }; 7541 7542 struct mlx5_ifc_dealloc_q_counter_out_bits { 7543 u8 status[0x8]; 7544 u8 reserved_at_8[0x18]; 7545 7546 u8 syndrome[0x20]; 7547 7548 u8 reserved_at_40[0x40]; 7549 }; 7550 7551 struct mlx5_ifc_dealloc_q_counter_in_bits { 7552 u8 opcode[0x10]; 7553 u8 reserved_at_10[0x10]; 7554 7555 u8 reserved_at_20[0x10]; 7556 u8 op_mod[0x10]; 7557 7558 u8 reserved_at_40[0x18]; 7559 u8 counter_set_id[0x8]; 7560 7561 u8 reserved_at_60[0x20]; 7562 }; 7563 7564 struct mlx5_ifc_dealloc_pd_out_bits { 7565 u8 status[0x8]; 7566 u8 reserved_at_8[0x18]; 7567 7568 u8 syndrome[0x20]; 7569 7570 u8 reserved_at_40[0x40]; 7571 }; 7572 7573 struct mlx5_ifc_dealloc_pd_in_bits { 7574 u8 opcode[0x10]; 7575 u8 uid[0x10]; 7576 7577 u8 reserved_at_20[0x10]; 7578 u8 op_mod[0x10]; 7579 7580 u8 reserved_at_40[0x8]; 7581 u8 pd[0x18]; 7582 7583 u8 reserved_at_60[0x20]; 7584 }; 7585 7586 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7587 u8 status[0x8]; 7588 u8 reserved_at_8[0x18]; 7589 7590 u8 syndrome[0x20]; 7591 7592 u8 reserved_at_40[0x40]; 7593 }; 7594 7595 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7596 u8 opcode[0x10]; 7597 u8 reserved_at_10[0x10]; 7598 7599 u8 reserved_at_20[0x10]; 7600 u8 op_mod[0x10]; 7601 7602 u8 flow_counter_id[0x20]; 7603 7604 u8 reserved_at_60[0x20]; 7605 }; 7606 7607 struct mlx5_ifc_create_xrq_out_bits { 7608 u8 status[0x8]; 7609 u8 reserved_at_8[0x18]; 7610 7611 u8 syndrome[0x20]; 7612 7613 u8 reserved_at_40[0x8]; 7614 u8 xrqn[0x18]; 7615 7616 u8 reserved_at_60[0x20]; 7617 }; 7618 7619 struct mlx5_ifc_create_xrq_in_bits { 7620 u8 opcode[0x10]; 7621 u8 uid[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 reserved_at_40[0x40]; 7627 7628 struct mlx5_ifc_xrqc_bits xrq_context; 7629 }; 7630 7631 struct mlx5_ifc_create_xrc_srq_out_bits { 7632 u8 status[0x8]; 7633 u8 reserved_at_8[0x18]; 7634 7635 u8 syndrome[0x20]; 7636 7637 u8 reserved_at_40[0x8]; 7638 u8 xrc_srqn[0x18]; 7639 7640 u8 reserved_at_60[0x20]; 7641 }; 7642 7643 struct mlx5_ifc_create_xrc_srq_in_bits { 7644 u8 opcode[0x10]; 7645 u8 uid[0x10]; 7646 7647 u8 reserved_at_20[0x10]; 7648 u8 op_mod[0x10]; 7649 7650 u8 reserved_at_40[0x40]; 7651 7652 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7653 7654 u8 reserved_at_280[0x60]; 7655 7656 u8 xrc_srq_umem_valid[0x1]; 7657 u8 reserved_at_2e1[0x1f]; 7658 7659 u8 reserved_at_300[0x580]; 7660 7661 u8 pas[][0x40]; 7662 }; 7663 7664 struct mlx5_ifc_create_tis_out_bits { 7665 u8 status[0x8]; 7666 u8 reserved_at_8[0x18]; 7667 7668 u8 syndrome[0x20]; 7669 7670 u8 reserved_at_40[0x8]; 7671 u8 tisn[0x18]; 7672 7673 u8 reserved_at_60[0x20]; 7674 }; 7675 7676 struct mlx5_ifc_create_tis_in_bits { 7677 u8 opcode[0x10]; 7678 u8 uid[0x10]; 7679 7680 u8 reserved_at_20[0x10]; 7681 u8 op_mod[0x10]; 7682 7683 u8 reserved_at_40[0xc0]; 7684 7685 struct mlx5_ifc_tisc_bits ctx; 7686 }; 7687 7688 struct mlx5_ifc_create_tir_out_bits { 7689 u8 status[0x8]; 7690 u8 icm_address_63_40[0x18]; 7691 7692 u8 syndrome[0x20]; 7693 7694 u8 icm_address_39_32[0x8]; 7695 u8 tirn[0x18]; 7696 7697 u8 icm_address_31_0[0x20]; 7698 }; 7699 7700 struct mlx5_ifc_create_tir_in_bits { 7701 u8 opcode[0x10]; 7702 u8 uid[0x10]; 7703 7704 u8 reserved_at_20[0x10]; 7705 u8 op_mod[0x10]; 7706 7707 u8 reserved_at_40[0xc0]; 7708 7709 struct mlx5_ifc_tirc_bits ctx; 7710 }; 7711 7712 struct mlx5_ifc_create_srq_out_bits { 7713 u8 status[0x8]; 7714 u8 reserved_at_8[0x18]; 7715 7716 u8 syndrome[0x20]; 7717 7718 u8 reserved_at_40[0x8]; 7719 u8 srqn[0x18]; 7720 7721 u8 reserved_at_60[0x20]; 7722 }; 7723 7724 struct mlx5_ifc_create_srq_in_bits { 7725 u8 opcode[0x10]; 7726 u8 uid[0x10]; 7727 7728 u8 reserved_at_20[0x10]; 7729 u8 op_mod[0x10]; 7730 7731 u8 reserved_at_40[0x40]; 7732 7733 struct mlx5_ifc_srqc_bits srq_context_entry; 7734 7735 u8 reserved_at_280[0x600]; 7736 7737 u8 pas[][0x40]; 7738 }; 7739 7740 struct mlx5_ifc_create_sq_out_bits { 7741 u8 status[0x8]; 7742 u8 reserved_at_8[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 reserved_at_40[0x8]; 7747 u8 sqn[0x18]; 7748 7749 u8 reserved_at_60[0x20]; 7750 }; 7751 7752 struct mlx5_ifc_create_sq_in_bits { 7753 u8 opcode[0x10]; 7754 u8 uid[0x10]; 7755 7756 u8 reserved_at_20[0x10]; 7757 u8 op_mod[0x10]; 7758 7759 u8 reserved_at_40[0xc0]; 7760 7761 struct mlx5_ifc_sqc_bits ctx; 7762 }; 7763 7764 struct mlx5_ifc_create_scheduling_element_out_bits { 7765 u8 status[0x8]; 7766 u8 reserved_at_8[0x18]; 7767 7768 u8 syndrome[0x20]; 7769 7770 u8 reserved_at_40[0x40]; 7771 7772 u8 scheduling_element_id[0x20]; 7773 7774 u8 reserved_at_a0[0x160]; 7775 }; 7776 7777 struct mlx5_ifc_create_scheduling_element_in_bits { 7778 u8 opcode[0x10]; 7779 u8 reserved_at_10[0x10]; 7780 7781 u8 reserved_at_20[0x10]; 7782 u8 op_mod[0x10]; 7783 7784 u8 scheduling_hierarchy[0x8]; 7785 u8 reserved_at_48[0x18]; 7786 7787 u8 reserved_at_60[0xa0]; 7788 7789 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7790 7791 u8 reserved_at_300[0x100]; 7792 }; 7793 7794 struct mlx5_ifc_create_rqt_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_at_8[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_at_40[0x8]; 7801 u8 rqtn[0x18]; 7802 7803 u8 reserved_at_60[0x20]; 7804 }; 7805 7806 struct mlx5_ifc_create_rqt_in_bits { 7807 u8 opcode[0x10]; 7808 u8 uid[0x10]; 7809 7810 u8 reserved_at_20[0x10]; 7811 u8 op_mod[0x10]; 7812 7813 u8 reserved_at_40[0xc0]; 7814 7815 struct mlx5_ifc_rqtc_bits rqt_context; 7816 }; 7817 7818 struct mlx5_ifc_create_rq_out_bits { 7819 u8 status[0x8]; 7820 u8 reserved_at_8[0x18]; 7821 7822 u8 syndrome[0x20]; 7823 7824 u8 reserved_at_40[0x8]; 7825 u8 rqn[0x18]; 7826 7827 u8 reserved_at_60[0x20]; 7828 }; 7829 7830 struct mlx5_ifc_create_rq_in_bits { 7831 u8 opcode[0x10]; 7832 u8 uid[0x10]; 7833 7834 u8 reserved_at_20[0x10]; 7835 u8 op_mod[0x10]; 7836 7837 u8 reserved_at_40[0xc0]; 7838 7839 struct mlx5_ifc_rqc_bits ctx; 7840 }; 7841 7842 struct mlx5_ifc_create_rmp_out_bits { 7843 u8 status[0x8]; 7844 u8 reserved_at_8[0x18]; 7845 7846 u8 syndrome[0x20]; 7847 7848 u8 reserved_at_40[0x8]; 7849 u8 rmpn[0x18]; 7850 7851 u8 reserved_at_60[0x20]; 7852 }; 7853 7854 struct mlx5_ifc_create_rmp_in_bits { 7855 u8 opcode[0x10]; 7856 u8 uid[0x10]; 7857 7858 u8 reserved_at_20[0x10]; 7859 u8 op_mod[0x10]; 7860 7861 u8 reserved_at_40[0xc0]; 7862 7863 struct mlx5_ifc_rmpc_bits ctx; 7864 }; 7865 7866 struct mlx5_ifc_create_qp_out_bits { 7867 u8 status[0x8]; 7868 u8 reserved_at_8[0x18]; 7869 7870 u8 syndrome[0x20]; 7871 7872 u8 reserved_at_40[0x8]; 7873 u8 qpn[0x18]; 7874 7875 u8 ece[0x20]; 7876 }; 7877 7878 struct mlx5_ifc_create_qp_in_bits { 7879 u8 opcode[0x10]; 7880 u8 uid[0x10]; 7881 7882 u8 reserved_at_20[0x10]; 7883 u8 op_mod[0x10]; 7884 7885 u8 reserved_at_40[0x8]; 7886 u8 input_qpn[0x18]; 7887 7888 u8 reserved_at_60[0x20]; 7889 u8 opt_param_mask[0x20]; 7890 7891 u8 ece[0x20]; 7892 7893 struct mlx5_ifc_qpc_bits qpc; 7894 7895 u8 reserved_at_800[0x60]; 7896 7897 u8 wq_umem_valid[0x1]; 7898 u8 reserved_at_861[0x1f]; 7899 7900 u8 pas[][0x40]; 7901 }; 7902 7903 struct mlx5_ifc_create_psv_out_bits { 7904 u8 status[0x8]; 7905 u8 reserved_at_8[0x18]; 7906 7907 u8 syndrome[0x20]; 7908 7909 u8 reserved_at_40[0x40]; 7910 7911 u8 reserved_at_80[0x8]; 7912 u8 psv0_index[0x18]; 7913 7914 u8 reserved_at_a0[0x8]; 7915 u8 psv1_index[0x18]; 7916 7917 u8 reserved_at_c0[0x8]; 7918 u8 psv2_index[0x18]; 7919 7920 u8 reserved_at_e0[0x8]; 7921 u8 psv3_index[0x18]; 7922 }; 7923 7924 struct mlx5_ifc_create_psv_in_bits { 7925 u8 opcode[0x10]; 7926 u8 reserved_at_10[0x10]; 7927 7928 u8 reserved_at_20[0x10]; 7929 u8 op_mod[0x10]; 7930 7931 u8 num_psv[0x4]; 7932 u8 reserved_at_44[0x4]; 7933 u8 pd[0x18]; 7934 7935 u8 reserved_at_60[0x20]; 7936 }; 7937 7938 struct mlx5_ifc_create_mkey_out_bits { 7939 u8 status[0x8]; 7940 u8 reserved_at_8[0x18]; 7941 7942 u8 syndrome[0x20]; 7943 7944 u8 reserved_at_40[0x8]; 7945 u8 mkey_index[0x18]; 7946 7947 u8 reserved_at_60[0x20]; 7948 }; 7949 7950 struct mlx5_ifc_create_mkey_in_bits { 7951 u8 opcode[0x10]; 7952 u8 uid[0x10]; 7953 7954 u8 reserved_at_20[0x10]; 7955 u8 op_mod[0x10]; 7956 7957 u8 reserved_at_40[0x20]; 7958 7959 u8 pg_access[0x1]; 7960 u8 mkey_umem_valid[0x1]; 7961 u8 reserved_at_62[0x1e]; 7962 7963 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7964 7965 u8 reserved_at_280[0x80]; 7966 7967 u8 translations_octword_actual_size[0x20]; 7968 7969 u8 reserved_at_320[0x560]; 7970 7971 u8 klm_pas_mtt[][0x20]; 7972 }; 7973 7974 enum { 7975 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7976 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7977 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7978 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7979 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7980 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7981 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7982 }; 7983 7984 struct mlx5_ifc_create_flow_table_out_bits { 7985 u8 status[0x8]; 7986 u8 icm_address_63_40[0x18]; 7987 7988 u8 syndrome[0x20]; 7989 7990 u8 icm_address_39_32[0x8]; 7991 u8 table_id[0x18]; 7992 7993 u8 icm_address_31_0[0x20]; 7994 }; 7995 7996 struct mlx5_ifc_create_flow_table_in_bits { 7997 u8 opcode[0x10]; 7998 u8 reserved_at_10[0x10]; 7999 8000 u8 reserved_at_20[0x10]; 8001 u8 op_mod[0x10]; 8002 8003 u8 other_vport[0x1]; 8004 u8 reserved_at_41[0xf]; 8005 u8 vport_number[0x10]; 8006 8007 u8 reserved_at_60[0x20]; 8008 8009 u8 table_type[0x8]; 8010 u8 reserved_at_88[0x18]; 8011 8012 u8 reserved_at_a0[0x20]; 8013 8014 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8015 }; 8016 8017 struct mlx5_ifc_create_flow_group_out_bits { 8018 u8 status[0x8]; 8019 u8 reserved_at_8[0x18]; 8020 8021 u8 syndrome[0x20]; 8022 8023 u8 reserved_at_40[0x8]; 8024 u8 group_id[0x18]; 8025 8026 u8 reserved_at_60[0x20]; 8027 }; 8028 8029 enum { 8030 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8031 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8032 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8033 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8034 }; 8035 8036 struct mlx5_ifc_create_flow_group_in_bits { 8037 u8 opcode[0x10]; 8038 u8 reserved_at_10[0x10]; 8039 8040 u8 reserved_at_20[0x10]; 8041 u8 op_mod[0x10]; 8042 8043 u8 other_vport[0x1]; 8044 u8 reserved_at_41[0xf]; 8045 u8 vport_number[0x10]; 8046 8047 u8 reserved_at_60[0x20]; 8048 8049 u8 table_type[0x8]; 8050 u8 reserved_at_88[0x18]; 8051 8052 u8 reserved_at_a0[0x8]; 8053 u8 table_id[0x18]; 8054 8055 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8056 8057 u8 reserved_at_c1[0x1f]; 8058 8059 u8 start_flow_index[0x20]; 8060 8061 u8 reserved_at_100[0x20]; 8062 8063 u8 end_flow_index[0x20]; 8064 8065 u8 reserved_at_140[0xa0]; 8066 8067 u8 reserved_at_1e0[0x18]; 8068 u8 match_criteria_enable[0x8]; 8069 8070 struct mlx5_ifc_fte_match_param_bits match_criteria; 8071 8072 u8 reserved_at_1200[0xe00]; 8073 }; 8074 8075 struct mlx5_ifc_create_eq_out_bits { 8076 u8 status[0x8]; 8077 u8 reserved_at_8[0x18]; 8078 8079 u8 syndrome[0x20]; 8080 8081 u8 reserved_at_40[0x18]; 8082 u8 eq_number[0x8]; 8083 8084 u8 reserved_at_60[0x20]; 8085 }; 8086 8087 struct mlx5_ifc_create_eq_in_bits { 8088 u8 opcode[0x10]; 8089 u8 uid[0x10]; 8090 8091 u8 reserved_at_20[0x10]; 8092 u8 op_mod[0x10]; 8093 8094 u8 reserved_at_40[0x40]; 8095 8096 struct mlx5_ifc_eqc_bits eq_context_entry; 8097 8098 u8 reserved_at_280[0x40]; 8099 8100 u8 event_bitmask[4][0x40]; 8101 8102 u8 reserved_at_3c0[0x4c0]; 8103 8104 u8 pas[][0x40]; 8105 }; 8106 8107 struct mlx5_ifc_create_dct_out_bits { 8108 u8 status[0x8]; 8109 u8 reserved_at_8[0x18]; 8110 8111 u8 syndrome[0x20]; 8112 8113 u8 reserved_at_40[0x8]; 8114 u8 dctn[0x18]; 8115 8116 u8 ece[0x20]; 8117 }; 8118 8119 struct mlx5_ifc_create_dct_in_bits { 8120 u8 opcode[0x10]; 8121 u8 uid[0x10]; 8122 8123 u8 reserved_at_20[0x10]; 8124 u8 op_mod[0x10]; 8125 8126 u8 reserved_at_40[0x40]; 8127 8128 struct mlx5_ifc_dctc_bits dct_context_entry; 8129 8130 u8 reserved_at_280[0x180]; 8131 }; 8132 8133 struct mlx5_ifc_create_cq_out_bits { 8134 u8 status[0x8]; 8135 u8 reserved_at_8[0x18]; 8136 8137 u8 syndrome[0x20]; 8138 8139 u8 reserved_at_40[0x8]; 8140 u8 cqn[0x18]; 8141 8142 u8 reserved_at_60[0x20]; 8143 }; 8144 8145 struct mlx5_ifc_create_cq_in_bits { 8146 u8 opcode[0x10]; 8147 u8 uid[0x10]; 8148 8149 u8 reserved_at_20[0x10]; 8150 u8 op_mod[0x10]; 8151 8152 u8 reserved_at_40[0x40]; 8153 8154 struct mlx5_ifc_cqc_bits cq_context; 8155 8156 u8 reserved_at_280[0x60]; 8157 8158 u8 cq_umem_valid[0x1]; 8159 u8 reserved_at_2e1[0x59f]; 8160 8161 u8 pas[][0x40]; 8162 }; 8163 8164 struct mlx5_ifc_config_int_moderation_out_bits { 8165 u8 status[0x8]; 8166 u8 reserved_at_8[0x18]; 8167 8168 u8 syndrome[0x20]; 8169 8170 u8 reserved_at_40[0x4]; 8171 u8 min_delay[0xc]; 8172 u8 int_vector[0x10]; 8173 8174 u8 reserved_at_60[0x20]; 8175 }; 8176 8177 enum { 8178 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8179 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8180 }; 8181 8182 struct mlx5_ifc_config_int_moderation_in_bits { 8183 u8 opcode[0x10]; 8184 u8 reserved_at_10[0x10]; 8185 8186 u8 reserved_at_20[0x10]; 8187 u8 op_mod[0x10]; 8188 8189 u8 reserved_at_40[0x4]; 8190 u8 min_delay[0xc]; 8191 u8 int_vector[0x10]; 8192 8193 u8 reserved_at_60[0x20]; 8194 }; 8195 8196 struct mlx5_ifc_attach_to_mcg_out_bits { 8197 u8 status[0x8]; 8198 u8 reserved_at_8[0x18]; 8199 8200 u8 syndrome[0x20]; 8201 8202 u8 reserved_at_40[0x40]; 8203 }; 8204 8205 struct mlx5_ifc_attach_to_mcg_in_bits { 8206 u8 opcode[0x10]; 8207 u8 uid[0x10]; 8208 8209 u8 reserved_at_20[0x10]; 8210 u8 op_mod[0x10]; 8211 8212 u8 reserved_at_40[0x8]; 8213 u8 qpn[0x18]; 8214 8215 u8 reserved_at_60[0x20]; 8216 8217 u8 multicast_gid[16][0x8]; 8218 }; 8219 8220 struct mlx5_ifc_arm_xrq_out_bits { 8221 u8 status[0x8]; 8222 u8 reserved_at_8[0x18]; 8223 8224 u8 syndrome[0x20]; 8225 8226 u8 reserved_at_40[0x40]; 8227 }; 8228 8229 struct mlx5_ifc_arm_xrq_in_bits { 8230 u8 opcode[0x10]; 8231 u8 reserved_at_10[0x10]; 8232 8233 u8 reserved_at_20[0x10]; 8234 u8 op_mod[0x10]; 8235 8236 u8 reserved_at_40[0x8]; 8237 u8 xrqn[0x18]; 8238 8239 u8 reserved_at_60[0x10]; 8240 u8 lwm[0x10]; 8241 }; 8242 8243 struct mlx5_ifc_arm_xrc_srq_out_bits { 8244 u8 status[0x8]; 8245 u8 reserved_at_8[0x18]; 8246 8247 u8 syndrome[0x20]; 8248 8249 u8 reserved_at_40[0x40]; 8250 }; 8251 8252 enum { 8253 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8254 }; 8255 8256 struct mlx5_ifc_arm_xrc_srq_in_bits { 8257 u8 opcode[0x10]; 8258 u8 uid[0x10]; 8259 8260 u8 reserved_at_20[0x10]; 8261 u8 op_mod[0x10]; 8262 8263 u8 reserved_at_40[0x8]; 8264 u8 xrc_srqn[0x18]; 8265 8266 u8 reserved_at_60[0x10]; 8267 u8 lwm[0x10]; 8268 }; 8269 8270 struct mlx5_ifc_arm_rq_out_bits { 8271 u8 status[0x8]; 8272 u8 reserved_at_8[0x18]; 8273 8274 u8 syndrome[0x20]; 8275 8276 u8 reserved_at_40[0x40]; 8277 }; 8278 8279 enum { 8280 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8281 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8282 }; 8283 8284 struct mlx5_ifc_arm_rq_in_bits { 8285 u8 opcode[0x10]; 8286 u8 uid[0x10]; 8287 8288 u8 reserved_at_20[0x10]; 8289 u8 op_mod[0x10]; 8290 8291 u8 reserved_at_40[0x8]; 8292 u8 srq_number[0x18]; 8293 8294 u8 reserved_at_60[0x10]; 8295 u8 lwm[0x10]; 8296 }; 8297 8298 struct mlx5_ifc_arm_dct_out_bits { 8299 u8 status[0x8]; 8300 u8 reserved_at_8[0x18]; 8301 8302 u8 syndrome[0x20]; 8303 8304 u8 reserved_at_40[0x40]; 8305 }; 8306 8307 struct mlx5_ifc_arm_dct_in_bits { 8308 u8 opcode[0x10]; 8309 u8 reserved_at_10[0x10]; 8310 8311 u8 reserved_at_20[0x10]; 8312 u8 op_mod[0x10]; 8313 8314 u8 reserved_at_40[0x8]; 8315 u8 dct_number[0x18]; 8316 8317 u8 reserved_at_60[0x20]; 8318 }; 8319 8320 struct mlx5_ifc_alloc_xrcd_out_bits { 8321 u8 status[0x8]; 8322 u8 reserved_at_8[0x18]; 8323 8324 u8 syndrome[0x20]; 8325 8326 u8 reserved_at_40[0x8]; 8327 u8 xrcd[0x18]; 8328 8329 u8 reserved_at_60[0x20]; 8330 }; 8331 8332 struct mlx5_ifc_alloc_xrcd_in_bits { 8333 u8 opcode[0x10]; 8334 u8 uid[0x10]; 8335 8336 u8 reserved_at_20[0x10]; 8337 u8 op_mod[0x10]; 8338 8339 u8 reserved_at_40[0x40]; 8340 }; 8341 8342 struct mlx5_ifc_alloc_uar_out_bits { 8343 u8 status[0x8]; 8344 u8 reserved_at_8[0x18]; 8345 8346 u8 syndrome[0x20]; 8347 8348 u8 reserved_at_40[0x8]; 8349 u8 uar[0x18]; 8350 8351 u8 reserved_at_60[0x20]; 8352 }; 8353 8354 struct mlx5_ifc_alloc_uar_in_bits { 8355 u8 opcode[0x10]; 8356 u8 reserved_at_10[0x10]; 8357 8358 u8 reserved_at_20[0x10]; 8359 u8 op_mod[0x10]; 8360 8361 u8 reserved_at_40[0x40]; 8362 }; 8363 8364 struct mlx5_ifc_alloc_transport_domain_out_bits { 8365 u8 status[0x8]; 8366 u8 reserved_at_8[0x18]; 8367 8368 u8 syndrome[0x20]; 8369 8370 u8 reserved_at_40[0x8]; 8371 u8 transport_domain[0x18]; 8372 8373 u8 reserved_at_60[0x20]; 8374 }; 8375 8376 struct mlx5_ifc_alloc_transport_domain_in_bits { 8377 u8 opcode[0x10]; 8378 u8 uid[0x10]; 8379 8380 u8 reserved_at_20[0x10]; 8381 u8 op_mod[0x10]; 8382 8383 u8 reserved_at_40[0x40]; 8384 }; 8385 8386 struct mlx5_ifc_alloc_q_counter_out_bits { 8387 u8 status[0x8]; 8388 u8 reserved_at_8[0x18]; 8389 8390 u8 syndrome[0x20]; 8391 8392 u8 reserved_at_40[0x18]; 8393 u8 counter_set_id[0x8]; 8394 8395 u8 reserved_at_60[0x20]; 8396 }; 8397 8398 struct mlx5_ifc_alloc_q_counter_in_bits { 8399 u8 opcode[0x10]; 8400 u8 uid[0x10]; 8401 8402 u8 reserved_at_20[0x10]; 8403 u8 op_mod[0x10]; 8404 8405 u8 reserved_at_40[0x40]; 8406 }; 8407 8408 struct mlx5_ifc_alloc_pd_out_bits { 8409 u8 status[0x8]; 8410 u8 reserved_at_8[0x18]; 8411 8412 u8 syndrome[0x20]; 8413 8414 u8 reserved_at_40[0x8]; 8415 u8 pd[0x18]; 8416 8417 u8 reserved_at_60[0x20]; 8418 }; 8419 8420 struct mlx5_ifc_alloc_pd_in_bits { 8421 u8 opcode[0x10]; 8422 u8 uid[0x10]; 8423 8424 u8 reserved_at_20[0x10]; 8425 u8 op_mod[0x10]; 8426 8427 u8 reserved_at_40[0x40]; 8428 }; 8429 8430 struct mlx5_ifc_alloc_flow_counter_out_bits { 8431 u8 status[0x8]; 8432 u8 reserved_at_8[0x18]; 8433 8434 u8 syndrome[0x20]; 8435 8436 u8 flow_counter_id[0x20]; 8437 8438 u8 reserved_at_60[0x20]; 8439 }; 8440 8441 struct mlx5_ifc_alloc_flow_counter_in_bits { 8442 u8 opcode[0x10]; 8443 u8 reserved_at_10[0x10]; 8444 8445 u8 reserved_at_20[0x10]; 8446 u8 op_mod[0x10]; 8447 8448 u8 reserved_at_40[0x38]; 8449 u8 flow_counter_bulk[0x8]; 8450 }; 8451 8452 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8453 u8 status[0x8]; 8454 u8 reserved_at_8[0x18]; 8455 8456 u8 syndrome[0x20]; 8457 8458 u8 reserved_at_40[0x40]; 8459 }; 8460 8461 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8462 u8 opcode[0x10]; 8463 u8 reserved_at_10[0x10]; 8464 8465 u8 reserved_at_20[0x10]; 8466 u8 op_mod[0x10]; 8467 8468 u8 reserved_at_40[0x20]; 8469 8470 u8 reserved_at_60[0x10]; 8471 u8 vxlan_udp_port[0x10]; 8472 }; 8473 8474 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8475 u8 status[0x8]; 8476 u8 reserved_at_8[0x18]; 8477 8478 u8 syndrome[0x20]; 8479 8480 u8 reserved_at_40[0x40]; 8481 }; 8482 8483 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8484 u8 rate_limit[0x20]; 8485 8486 u8 burst_upper_bound[0x20]; 8487 8488 u8 reserved_at_40[0x10]; 8489 u8 typical_packet_size[0x10]; 8490 8491 u8 reserved_at_60[0x120]; 8492 }; 8493 8494 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8495 u8 opcode[0x10]; 8496 u8 uid[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0x10]; 8502 u8 rate_limit_index[0x10]; 8503 8504 u8 reserved_at_60[0x20]; 8505 8506 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8507 }; 8508 8509 struct mlx5_ifc_access_register_out_bits { 8510 u8 status[0x8]; 8511 u8 reserved_at_8[0x18]; 8512 8513 u8 syndrome[0x20]; 8514 8515 u8 reserved_at_40[0x40]; 8516 8517 u8 register_data[][0x20]; 8518 }; 8519 8520 enum { 8521 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8522 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8523 }; 8524 8525 struct mlx5_ifc_access_register_in_bits { 8526 u8 opcode[0x10]; 8527 u8 reserved_at_10[0x10]; 8528 8529 u8 reserved_at_20[0x10]; 8530 u8 op_mod[0x10]; 8531 8532 u8 reserved_at_40[0x10]; 8533 u8 register_id[0x10]; 8534 8535 u8 argument[0x20]; 8536 8537 u8 register_data[][0x20]; 8538 }; 8539 8540 struct mlx5_ifc_sltp_reg_bits { 8541 u8 status[0x4]; 8542 u8 version[0x4]; 8543 u8 local_port[0x8]; 8544 u8 pnat[0x2]; 8545 u8 reserved_at_12[0x2]; 8546 u8 lane[0x4]; 8547 u8 reserved_at_18[0x8]; 8548 8549 u8 reserved_at_20[0x20]; 8550 8551 u8 reserved_at_40[0x7]; 8552 u8 polarity[0x1]; 8553 u8 ob_tap0[0x8]; 8554 u8 ob_tap1[0x8]; 8555 u8 ob_tap2[0x8]; 8556 8557 u8 reserved_at_60[0xc]; 8558 u8 ob_preemp_mode[0x4]; 8559 u8 ob_reg[0x8]; 8560 u8 ob_bias[0x8]; 8561 8562 u8 reserved_at_80[0x20]; 8563 }; 8564 8565 struct mlx5_ifc_slrg_reg_bits { 8566 u8 status[0x4]; 8567 u8 version[0x4]; 8568 u8 local_port[0x8]; 8569 u8 pnat[0x2]; 8570 u8 reserved_at_12[0x2]; 8571 u8 lane[0x4]; 8572 u8 reserved_at_18[0x8]; 8573 8574 u8 time_to_link_up[0x10]; 8575 u8 reserved_at_30[0xc]; 8576 u8 grade_lane_speed[0x4]; 8577 8578 u8 grade_version[0x8]; 8579 u8 grade[0x18]; 8580 8581 u8 reserved_at_60[0x4]; 8582 u8 height_grade_type[0x4]; 8583 u8 height_grade[0x18]; 8584 8585 u8 height_dz[0x10]; 8586 u8 height_dv[0x10]; 8587 8588 u8 reserved_at_a0[0x10]; 8589 u8 height_sigma[0x10]; 8590 8591 u8 reserved_at_c0[0x20]; 8592 8593 u8 reserved_at_e0[0x4]; 8594 u8 phase_grade_type[0x4]; 8595 u8 phase_grade[0x18]; 8596 8597 u8 reserved_at_100[0x8]; 8598 u8 phase_eo_pos[0x8]; 8599 u8 reserved_at_110[0x8]; 8600 u8 phase_eo_neg[0x8]; 8601 8602 u8 ffe_set_tested[0x10]; 8603 u8 test_errors_per_lane[0x10]; 8604 }; 8605 8606 struct mlx5_ifc_pvlc_reg_bits { 8607 u8 reserved_at_0[0x8]; 8608 u8 local_port[0x8]; 8609 u8 reserved_at_10[0x10]; 8610 8611 u8 reserved_at_20[0x1c]; 8612 u8 vl_hw_cap[0x4]; 8613 8614 u8 reserved_at_40[0x1c]; 8615 u8 vl_admin[0x4]; 8616 8617 u8 reserved_at_60[0x1c]; 8618 u8 vl_operational[0x4]; 8619 }; 8620 8621 struct mlx5_ifc_pude_reg_bits { 8622 u8 swid[0x8]; 8623 u8 local_port[0x8]; 8624 u8 reserved_at_10[0x4]; 8625 u8 admin_status[0x4]; 8626 u8 reserved_at_18[0x4]; 8627 u8 oper_status[0x4]; 8628 8629 u8 reserved_at_20[0x60]; 8630 }; 8631 8632 struct mlx5_ifc_ptys_reg_bits { 8633 u8 reserved_at_0[0x1]; 8634 u8 an_disable_admin[0x1]; 8635 u8 an_disable_cap[0x1]; 8636 u8 reserved_at_3[0x5]; 8637 u8 local_port[0x8]; 8638 u8 reserved_at_10[0xd]; 8639 u8 proto_mask[0x3]; 8640 8641 u8 an_status[0x4]; 8642 u8 reserved_at_24[0xc]; 8643 u8 data_rate_oper[0x10]; 8644 8645 u8 ext_eth_proto_capability[0x20]; 8646 8647 u8 eth_proto_capability[0x20]; 8648 8649 u8 ib_link_width_capability[0x10]; 8650 u8 ib_proto_capability[0x10]; 8651 8652 u8 ext_eth_proto_admin[0x20]; 8653 8654 u8 eth_proto_admin[0x20]; 8655 8656 u8 ib_link_width_admin[0x10]; 8657 u8 ib_proto_admin[0x10]; 8658 8659 u8 ext_eth_proto_oper[0x20]; 8660 8661 u8 eth_proto_oper[0x20]; 8662 8663 u8 ib_link_width_oper[0x10]; 8664 u8 ib_proto_oper[0x10]; 8665 8666 u8 reserved_at_160[0x1c]; 8667 u8 connector_type[0x4]; 8668 8669 u8 eth_proto_lp_advertise[0x20]; 8670 8671 u8 reserved_at_1a0[0x60]; 8672 }; 8673 8674 struct mlx5_ifc_mlcr_reg_bits { 8675 u8 reserved_at_0[0x8]; 8676 u8 local_port[0x8]; 8677 u8 reserved_at_10[0x20]; 8678 8679 u8 beacon_duration[0x10]; 8680 u8 reserved_at_40[0x10]; 8681 8682 u8 beacon_remain[0x10]; 8683 }; 8684 8685 struct mlx5_ifc_ptas_reg_bits { 8686 u8 reserved_at_0[0x20]; 8687 8688 u8 algorithm_options[0x10]; 8689 u8 reserved_at_30[0x4]; 8690 u8 repetitions_mode[0x4]; 8691 u8 num_of_repetitions[0x8]; 8692 8693 u8 grade_version[0x8]; 8694 u8 height_grade_type[0x4]; 8695 u8 phase_grade_type[0x4]; 8696 u8 height_grade_weight[0x8]; 8697 u8 phase_grade_weight[0x8]; 8698 8699 u8 gisim_measure_bits[0x10]; 8700 u8 adaptive_tap_measure_bits[0x10]; 8701 8702 u8 ber_bath_high_error_threshold[0x10]; 8703 u8 ber_bath_mid_error_threshold[0x10]; 8704 8705 u8 ber_bath_low_error_threshold[0x10]; 8706 u8 one_ratio_high_threshold[0x10]; 8707 8708 u8 one_ratio_high_mid_threshold[0x10]; 8709 u8 one_ratio_low_mid_threshold[0x10]; 8710 8711 u8 one_ratio_low_threshold[0x10]; 8712 u8 ndeo_error_threshold[0x10]; 8713 8714 u8 mixer_offset_step_size[0x10]; 8715 u8 reserved_at_110[0x8]; 8716 u8 mix90_phase_for_voltage_bath[0x8]; 8717 8718 u8 mixer_offset_start[0x10]; 8719 u8 mixer_offset_end[0x10]; 8720 8721 u8 reserved_at_140[0x15]; 8722 u8 ber_test_time[0xb]; 8723 }; 8724 8725 struct mlx5_ifc_pspa_reg_bits { 8726 u8 swid[0x8]; 8727 u8 local_port[0x8]; 8728 u8 sub_port[0x8]; 8729 u8 reserved_at_18[0x8]; 8730 8731 u8 reserved_at_20[0x20]; 8732 }; 8733 8734 struct mlx5_ifc_pqdr_reg_bits { 8735 u8 reserved_at_0[0x8]; 8736 u8 local_port[0x8]; 8737 u8 reserved_at_10[0x5]; 8738 u8 prio[0x3]; 8739 u8 reserved_at_18[0x6]; 8740 u8 mode[0x2]; 8741 8742 u8 reserved_at_20[0x20]; 8743 8744 u8 reserved_at_40[0x10]; 8745 u8 min_threshold[0x10]; 8746 8747 u8 reserved_at_60[0x10]; 8748 u8 max_threshold[0x10]; 8749 8750 u8 reserved_at_80[0x10]; 8751 u8 mark_probability_denominator[0x10]; 8752 8753 u8 reserved_at_a0[0x60]; 8754 }; 8755 8756 struct mlx5_ifc_ppsc_reg_bits { 8757 u8 reserved_at_0[0x8]; 8758 u8 local_port[0x8]; 8759 u8 reserved_at_10[0x10]; 8760 8761 u8 reserved_at_20[0x60]; 8762 8763 u8 reserved_at_80[0x1c]; 8764 u8 wrps_admin[0x4]; 8765 8766 u8 reserved_at_a0[0x1c]; 8767 u8 wrps_status[0x4]; 8768 8769 u8 reserved_at_c0[0x8]; 8770 u8 up_threshold[0x8]; 8771 u8 reserved_at_d0[0x8]; 8772 u8 down_threshold[0x8]; 8773 8774 u8 reserved_at_e0[0x20]; 8775 8776 u8 reserved_at_100[0x1c]; 8777 u8 srps_admin[0x4]; 8778 8779 u8 reserved_at_120[0x1c]; 8780 u8 srps_status[0x4]; 8781 8782 u8 reserved_at_140[0x40]; 8783 }; 8784 8785 struct mlx5_ifc_pplr_reg_bits { 8786 u8 reserved_at_0[0x8]; 8787 u8 local_port[0x8]; 8788 u8 reserved_at_10[0x10]; 8789 8790 u8 reserved_at_20[0x8]; 8791 u8 lb_cap[0x8]; 8792 u8 reserved_at_30[0x8]; 8793 u8 lb_en[0x8]; 8794 }; 8795 8796 struct mlx5_ifc_pplm_reg_bits { 8797 u8 reserved_at_0[0x8]; 8798 u8 local_port[0x8]; 8799 u8 reserved_at_10[0x10]; 8800 8801 u8 reserved_at_20[0x20]; 8802 8803 u8 port_profile_mode[0x8]; 8804 u8 static_port_profile[0x8]; 8805 u8 active_port_profile[0x8]; 8806 u8 reserved_at_58[0x8]; 8807 8808 u8 retransmission_active[0x8]; 8809 u8 fec_mode_active[0x18]; 8810 8811 u8 rs_fec_correction_bypass_cap[0x4]; 8812 u8 reserved_at_84[0x8]; 8813 u8 fec_override_cap_56g[0x4]; 8814 u8 fec_override_cap_100g[0x4]; 8815 u8 fec_override_cap_50g[0x4]; 8816 u8 fec_override_cap_25g[0x4]; 8817 u8 fec_override_cap_10g_40g[0x4]; 8818 8819 u8 rs_fec_correction_bypass_admin[0x4]; 8820 u8 reserved_at_a4[0x8]; 8821 u8 fec_override_admin_56g[0x4]; 8822 u8 fec_override_admin_100g[0x4]; 8823 u8 fec_override_admin_50g[0x4]; 8824 u8 fec_override_admin_25g[0x4]; 8825 u8 fec_override_admin_10g_40g[0x4]; 8826 8827 u8 fec_override_cap_400g_8x[0x10]; 8828 u8 fec_override_cap_200g_4x[0x10]; 8829 8830 u8 fec_override_cap_100g_2x[0x10]; 8831 u8 fec_override_cap_50g_1x[0x10]; 8832 8833 u8 fec_override_admin_400g_8x[0x10]; 8834 u8 fec_override_admin_200g_4x[0x10]; 8835 8836 u8 fec_override_admin_100g_2x[0x10]; 8837 u8 fec_override_admin_50g_1x[0x10]; 8838 }; 8839 8840 struct mlx5_ifc_ppcnt_reg_bits { 8841 u8 swid[0x8]; 8842 u8 local_port[0x8]; 8843 u8 pnat[0x2]; 8844 u8 reserved_at_12[0x8]; 8845 u8 grp[0x6]; 8846 8847 u8 clr[0x1]; 8848 u8 reserved_at_21[0x1c]; 8849 u8 prio_tc[0x3]; 8850 8851 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8852 }; 8853 8854 struct mlx5_ifc_mpein_reg_bits { 8855 u8 reserved_at_0[0x2]; 8856 u8 depth[0x6]; 8857 u8 pcie_index[0x8]; 8858 u8 node[0x8]; 8859 u8 reserved_at_18[0x8]; 8860 8861 u8 capability_mask[0x20]; 8862 8863 u8 reserved_at_40[0x8]; 8864 u8 link_width_enabled[0x8]; 8865 u8 link_speed_enabled[0x10]; 8866 8867 u8 lane0_physical_position[0x8]; 8868 u8 link_width_active[0x8]; 8869 u8 link_speed_active[0x10]; 8870 8871 u8 num_of_pfs[0x10]; 8872 u8 num_of_vfs[0x10]; 8873 8874 u8 bdf0[0x10]; 8875 u8 reserved_at_b0[0x10]; 8876 8877 u8 max_read_request_size[0x4]; 8878 u8 max_payload_size[0x4]; 8879 u8 reserved_at_c8[0x5]; 8880 u8 pwr_status[0x3]; 8881 u8 port_type[0x4]; 8882 u8 reserved_at_d4[0xb]; 8883 u8 lane_reversal[0x1]; 8884 8885 u8 reserved_at_e0[0x14]; 8886 u8 pci_power[0xc]; 8887 8888 u8 reserved_at_100[0x20]; 8889 8890 u8 device_status[0x10]; 8891 u8 port_state[0x8]; 8892 u8 reserved_at_138[0x8]; 8893 8894 u8 reserved_at_140[0x10]; 8895 u8 receiver_detect_result[0x10]; 8896 8897 u8 reserved_at_160[0x20]; 8898 }; 8899 8900 struct mlx5_ifc_mpcnt_reg_bits { 8901 u8 reserved_at_0[0x8]; 8902 u8 pcie_index[0x8]; 8903 u8 reserved_at_10[0xa]; 8904 u8 grp[0x6]; 8905 8906 u8 clr[0x1]; 8907 u8 reserved_at_21[0x1f]; 8908 8909 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8910 }; 8911 8912 struct mlx5_ifc_ppad_reg_bits { 8913 u8 reserved_at_0[0x3]; 8914 u8 single_mac[0x1]; 8915 u8 reserved_at_4[0x4]; 8916 u8 local_port[0x8]; 8917 u8 mac_47_32[0x10]; 8918 8919 u8 mac_31_0[0x20]; 8920 8921 u8 reserved_at_40[0x40]; 8922 }; 8923 8924 struct mlx5_ifc_pmtu_reg_bits { 8925 u8 reserved_at_0[0x8]; 8926 u8 local_port[0x8]; 8927 u8 reserved_at_10[0x10]; 8928 8929 u8 max_mtu[0x10]; 8930 u8 reserved_at_30[0x10]; 8931 8932 u8 admin_mtu[0x10]; 8933 u8 reserved_at_50[0x10]; 8934 8935 u8 oper_mtu[0x10]; 8936 u8 reserved_at_70[0x10]; 8937 }; 8938 8939 struct mlx5_ifc_pmpr_reg_bits { 8940 u8 reserved_at_0[0x8]; 8941 u8 module[0x8]; 8942 u8 reserved_at_10[0x10]; 8943 8944 u8 reserved_at_20[0x18]; 8945 u8 attenuation_5g[0x8]; 8946 8947 u8 reserved_at_40[0x18]; 8948 u8 attenuation_7g[0x8]; 8949 8950 u8 reserved_at_60[0x18]; 8951 u8 attenuation_12g[0x8]; 8952 }; 8953 8954 struct mlx5_ifc_pmpe_reg_bits { 8955 u8 reserved_at_0[0x8]; 8956 u8 module[0x8]; 8957 u8 reserved_at_10[0xc]; 8958 u8 module_status[0x4]; 8959 8960 u8 reserved_at_20[0x60]; 8961 }; 8962 8963 struct mlx5_ifc_pmpc_reg_bits { 8964 u8 module_state_updated[32][0x8]; 8965 }; 8966 8967 struct mlx5_ifc_pmlpn_reg_bits { 8968 u8 reserved_at_0[0x4]; 8969 u8 mlpn_status[0x4]; 8970 u8 local_port[0x8]; 8971 u8 reserved_at_10[0x10]; 8972 8973 u8 e[0x1]; 8974 u8 reserved_at_21[0x1f]; 8975 }; 8976 8977 struct mlx5_ifc_pmlp_reg_bits { 8978 u8 rxtx[0x1]; 8979 u8 reserved_at_1[0x7]; 8980 u8 local_port[0x8]; 8981 u8 reserved_at_10[0x8]; 8982 u8 width[0x8]; 8983 8984 u8 lane0_module_mapping[0x20]; 8985 8986 u8 lane1_module_mapping[0x20]; 8987 8988 u8 lane2_module_mapping[0x20]; 8989 8990 u8 lane3_module_mapping[0x20]; 8991 8992 u8 reserved_at_a0[0x160]; 8993 }; 8994 8995 struct mlx5_ifc_pmaos_reg_bits { 8996 u8 reserved_at_0[0x8]; 8997 u8 module[0x8]; 8998 u8 reserved_at_10[0x4]; 8999 u8 admin_status[0x4]; 9000 u8 reserved_at_18[0x4]; 9001 u8 oper_status[0x4]; 9002 9003 u8 ase[0x1]; 9004 u8 ee[0x1]; 9005 u8 reserved_at_22[0x1c]; 9006 u8 e[0x2]; 9007 9008 u8 reserved_at_40[0x40]; 9009 }; 9010 9011 struct mlx5_ifc_plpc_reg_bits { 9012 u8 reserved_at_0[0x4]; 9013 u8 profile_id[0xc]; 9014 u8 reserved_at_10[0x4]; 9015 u8 proto_mask[0x4]; 9016 u8 reserved_at_18[0x8]; 9017 9018 u8 reserved_at_20[0x10]; 9019 u8 lane_speed[0x10]; 9020 9021 u8 reserved_at_40[0x17]; 9022 u8 lpbf[0x1]; 9023 u8 fec_mode_policy[0x8]; 9024 9025 u8 retransmission_capability[0x8]; 9026 u8 fec_mode_capability[0x18]; 9027 9028 u8 retransmission_support_admin[0x8]; 9029 u8 fec_mode_support_admin[0x18]; 9030 9031 u8 retransmission_request_admin[0x8]; 9032 u8 fec_mode_request_admin[0x18]; 9033 9034 u8 reserved_at_c0[0x80]; 9035 }; 9036 9037 struct mlx5_ifc_plib_reg_bits { 9038 u8 reserved_at_0[0x8]; 9039 u8 local_port[0x8]; 9040 u8 reserved_at_10[0x8]; 9041 u8 ib_port[0x8]; 9042 9043 u8 reserved_at_20[0x60]; 9044 }; 9045 9046 struct mlx5_ifc_plbf_reg_bits { 9047 u8 reserved_at_0[0x8]; 9048 u8 local_port[0x8]; 9049 u8 reserved_at_10[0xd]; 9050 u8 lbf_mode[0x3]; 9051 9052 u8 reserved_at_20[0x20]; 9053 }; 9054 9055 struct mlx5_ifc_pipg_reg_bits { 9056 u8 reserved_at_0[0x8]; 9057 u8 local_port[0x8]; 9058 u8 reserved_at_10[0x10]; 9059 9060 u8 dic[0x1]; 9061 u8 reserved_at_21[0x19]; 9062 u8 ipg[0x4]; 9063 u8 reserved_at_3e[0x2]; 9064 }; 9065 9066 struct mlx5_ifc_pifr_reg_bits { 9067 u8 reserved_at_0[0x8]; 9068 u8 local_port[0x8]; 9069 u8 reserved_at_10[0x10]; 9070 9071 u8 reserved_at_20[0xe0]; 9072 9073 u8 port_filter[8][0x20]; 9074 9075 u8 port_filter_update_en[8][0x20]; 9076 }; 9077 9078 struct mlx5_ifc_pfcc_reg_bits { 9079 u8 reserved_at_0[0x8]; 9080 u8 local_port[0x8]; 9081 u8 reserved_at_10[0xb]; 9082 u8 ppan_mask_n[0x1]; 9083 u8 minor_stall_mask[0x1]; 9084 u8 critical_stall_mask[0x1]; 9085 u8 reserved_at_1e[0x2]; 9086 9087 u8 ppan[0x4]; 9088 u8 reserved_at_24[0x4]; 9089 u8 prio_mask_tx[0x8]; 9090 u8 reserved_at_30[0x8]; 9091 u8 prio_mask_rx[0x8]; 9092 9093 u8 pptx[0x1]; 9094 u8 aptx[0x1]; 9095 u8 pptx_mask_n[0x1]; 9096 u8 reserved_at_43[0x5]; 9097 u8 pfctx[0x8]; 9098 u8 reserved_at_50[0x10]; 9099 9100 u8 pprx[0x1]; 9101 u8 aprx[0x1]; 9102 u8 pprx_mask_n[0x1]; 9103 u8 reserved_at_63[0x5]; 9104 u8 pfcrx[0x8]; 9105 u8 reserved_at_70[0x10]; 9106 9107 u8 device_stall_minor_watermark[0x10]; 9108 u8 device_stall_critical_watermark[0x10]; 9109 9110 u8 reserved_at_a0[0x60]; 9111 }; 9112 9113 struct mlx5_ifc_pelc_reg_bits { 9114 u8 op[0x4]; 9115 u8 reserved_at_4[0x4]; 9116 u8 local_port[0x8]; 9117 u8 reserved_at_10[0x10]; 9118 9119 u8 op_admin[0x8]; 9120 u8 op_capability[0x8]; 9121 u8 op_request[0x8]; 9122 u8 op_active[0x8]; 9123 9124 u8 admin[0x40]; 9125 9126 u8 capability[0x40]; 9127 9128 u8 request[0x40]; 9129 9130 u8 active[0x40]; 9131 9132 u8 reserved_at_140[0x80]; 9133 }; 9134 9135 struct mlx5_ifc_peir_reg_bits { 9136 u8 reserved_at_0[0x8]; 9137 u8 local_port[0x8]; 9138 u8 reserved_at_10[0x10]; 9139 9140 u8 reserved_at_20[0xc]; 9141 u8 error_count[0x4]; 9142 u8 reserved_at_30[0x10]; 9143 9144 u8 reserved_at_40[0xc]; 9145 u8 lane[0x4]; 9146 u8 reserved_at_50[0x8]; 9147 u8 error_type[0x8]; 9148 }; 9149 9150 struct mlx5_ifc_mpegc_reg_bits { 9151 u8 reserved_at_0[0x30]; 9152 u8 field_select[0x10]; 9153 9154 u8 tx_overflow_sense[0x1]; 9155 u8 mark_cqe[0x1]; 9156 u8 mark_cnp[0x1]; 9157 u8 reserved_at_43[0x1b]; 9158 u8 tx_lossy_overflow_oper[0x2]; 9159 9160 u8 reserved_at_60[0x100]; 9161 }; 9162 9163 enum { 9164 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9165 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9166 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9167 }; 9168 9169 struct mlx5_ifc_mtutc_reg_bits { 9170 u8 reserved_at_0[0x1c]; 9171 u8 operation[0x4]; 9172 9173 u8 freq_adjustment[0x20]; 9174 9175 u8 reserved_at_40[0x40]; 9176 9177 u8 utc_sec[0x20]; 9178 9179 u8 reserved_at_a0[0x2]; 9180 u8 utc_nsec[0x1e]; 9181 9182 u8 time_adjustment[0x20]; 9183 }; 9184 9185 struct mlx5_ifc_pcam_enhanced_features_bits { 9186 u8 reserved_at_0[0x68]; 9187 u8 fec_50G_per_lane_in_pplm[0x1]; 9188 u8 reserved_at_69[0x4]; 9189 u8 rx_icrc_encapsulated_counter[0x1]; 9190 u8 reserved_at_6e[0x4]; 9191 u8 ptys_extended_ethernet[0x1]; 9192 u8 reserved_at_73[0x3]; 9193 u8 pfcc_mask[0x1]; 9194 u8 reserved_at_77[0x3]; 9195 u8 per_lane_error_counters[0x1]; 9196 u8 rx_buffer_fullness_counters[0x1]; 9197 u8 ptys_connector_type[0x1]; 9198 u8 reserved_at_7d[0x1]; 9199 u8 ppcnt_discard_group[0x1]; 9200 u8 ppcnt_statistical_group[0x1]; 9201 }; 9202 9203 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9204 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9205 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9206 9207 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9208 u8 pplm[0x1]; 9209 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9210 9211 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9212 u8 pbmc[0x1]; 9213 u8 pptb[0x1]; 9214 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9215 u8 ppcnt[0x1]; 9216 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9217 }; 9218 9219 struct mlx5_ifc_pcam_reg_bits { 9220 u8 reserved_at_0[0x8]; 9221 u8 feature_group[0x8]; 9222 u8 reserved_at_10[0x8]; 9223 u8 access_reg_group[0x8]; 9224 9225 u8 reserved_at_20[0x20]; 9226 9227 union { 9228 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9229 u8 reserved_at_0[0x80]; 9230 } port_access_reg_cap_mask; 9231 9232 u8 reserved_at_c0[0x80]; 9233 9234 union { 9235 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9236 u8 reserved_at_0[0x80]; 9237 } feature_cap_mask; 9238 9239 u8 reserved_at_1c0[0xc0]; 9240 }; 9241 9242 struct mlx5_ifc_mcam_enhanced_features_bits { 9243 u8 reserved_at_0[0x6b]; 9244 u8 ptpcyc2realtime_modify[0x1]; 9245 u8 reserved_at_6c[0x2]; 9246 u8 pci_status_and_power[0x1]; 9247 u8 reserved_at_6f[0x5]; 9248 u8 mark_tx_action_cnp[0x1]; 9249 u8 mark_tx_action_cqe[0x1]; 9250 u8 dynamic_tx_overflow[0x1]; 9251 u8 reserved_at_77[0x4]; 9252 u8 pcie_outbound_stalled[0x1]; 9253 u8 tx_overflow_buffer_pkt[0x1]; 9254 u8 mtpps_enh_out_per_adj[0x1]; 9255 u8 mtpps_fs[0x1]; 9256 u8 pcie_performance_group[0x1]; 9257 }; 9258 9259 struct mlx5_ifc_mcam_access_reg_bits { 9260 u8 reserved_at_0[0x1c]; 9261 u8 mcda[0x1]; 9262 u8 mcc[0x1]; 9263 u8 mcqi[0x1]; 9264 u8 mcqs[0x1]; 9265 9266 u8 regs_95_to_87[0x9]; 9267 u8 mpegc[0x1]; 9268 u8 mtutc[0x1]; 9269 u8 regs_84_to_68[0x11]; 9270 u8 tracer_registers[0x4]; 9271 9272 u8 regs_63_to_32[0x20]; 9273 u8 regs_31_to_0[0x20]; 9274 }; 9275 9276 struct mlx5_ifc_mcam_access_reg_bits1 { 9277 u8 regs_127_to_96[0x20]; 9278 9279 u8 regs_95_to_64[0x20]; 9280 9281 u8 regs_63_to_32[0x20]; 9282 9283 u8 regs_31_to_0[0x20]; 9284 }; 9285 9286 struct mlx5_ifc_mcam_access_reg_bits2 { 9287 u8 regs_127_to_99[0x1d]; 9288 u8 mirc[0x1]; 9289 u8 regs_97_to_96[0x2]; 9290 9291 u8 regs_95_to_64[0x20]; 9292 9293 u8 regs_63_to_32[0x20]; 9294 9295 u8 regs_31_to_0[0x20]; 9296 }; 9297 9298 struct mlx5_ifc_mcam_reg_bits { 9299 u8 reserved_at_0[0x8]; 9300 u8 feature_group[0x8]; 9301 u8 reserved_at_10[0x8]; 9302 u8 access_reg_group[0x8]; 9303 9304 u8 reserved_at_20[0x20]; 9305 9306 union { 9307 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9308 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9309 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9310 u8 reserved_at_0[0x80]; 9311 } mng_access_reg_cap_mask; 9312 9313 u8 reserved_at_c0[0x80]; 9314 9315 union { 9316 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9317 u8 reserved_at_0[0x80]; 9318 } mng_feature_cap_mask; 9319 9320 u8 reserved_at_1c0[0x80]; 9321 }; 9322 9323 struct mlx5_ifc_qcam_access_reg_cap_mask { 9324 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9325 u8 qpdpm[0x1]; 9326 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9327 u8 qdpm[0x1]; 9328 u8 qpts[0x1]; 9329 u8 qcap[0x1]; 9330 u8 qcam_access_reg_cap_mask_0[0x1]; 9331 }; 9332 9333 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9334 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9335 u8 qpts_trust_both[0x1]; 9336 }; 9337 9338 struct mlx5_ifc_qcam_reg_bits { 9339 u8 reserved_at_0[0x8]; 9340 u8 feature_group[0x8]; 9341 u8 reserved_at_10[0x8]; 9342 u8 access_reg_group[0x8]; 9343 u8 reserved_at_20[0x20]; 9344 9345 union { 9346 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9347 u8 reserved_at_0[0x80]; 9348 } qos_access_reg_cap_mask; 9349 9350 u8 reserved_at_c0[0x80]; 9351 9352 union { 9353 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9354 u8 reserved_at_0[0x80]; 9355 } qos_feature_cap_mask; 9356 9357 u8 reserved_at_1c0[0x80]; 9358 }; 9359 9360 struct mlx5_ifc_core_dump_reg_bits { 9361 u8 reserved_at_0[0x18]; 9362 u8 core_dump_type[0x8]; 9363 9364 u8 reserved_at_20[0x30]; 9365 u8 vhca_id[0x10]; 9366 9367 u8 reserved_at_60[0x8]; 9368 u8 qpn[0x18]; 9369 u8 reserved_at_80[0x180]; 9370 }; 9371 9372 struct mlx5_ifc_pcap_reg_bits { 9373 u8 reserved_at_0[0x8]; 9374 u8 local_port[0x8]; 9375 u8 reserved_at_10[0x10]; 9376 9377 u8 port_capability_mask[4][0x20]; 9378 }; 9379 9380 struct mlx5_ifc_paos_reg_bits { 9381 u8 swid[0x8]; 9382 u8 local_port[0x8]; 9383 u8 reserved_at_10[0x4]; 9384 u8 admin_status[0x4]; 9385 u8 reserved_at_18[0x4]; 9386 u8 oper_status[0x4]; 9387 9388 u8 ase[0x1]; 9389 u8 ee[0x1]; 9390 u8 reserved_at_22[0x1c]; 9391 u8 e[0x2]; 9392 9393 u8 reserved_at_40[0x40]; 9394 }; 9395 9396 struct mlx5_ifc_pamp_reg_bits { 9397 u8 reserved_at_0[0x8]; 9398 u8 opamp_group[0x8]; 9399 u8 reserved_at_10[0xc]; 9400 u8 opamp_group_type[0x4]; 9401 9402 u8 start_index[0x10]; 9403 u8 reserved_at_30[0x4]; 9404 u8 num_of_indices[0xc]; 9405 9406 u8 index_data[18][0x10]; 9407 }; 9408 9409 struct mlx5_ifc_pcmr_reg_bits { 9410 u8 reserved_at_0[0x8]; 9411 u8 local_port[0x8]; 9412 u8 reserved_at_10[0x10]; 9413 u8 entropy_force_cap[0x1]; 9414 u8 entropy_calc_cap[0x1]; 9415 u8 entropy_gre_calc_cap[0x1]; 9416 u8 reserved_at_23[0x1b]; 9417 u8 fcs_cap[0x1]; 9418 u8 reserved_at_3f[0x1]; 9419 u8 entropy_force[0x1]; 9420 u8 entropy_calc[0x1]; 9421 u8 entropy_gre_calc[0x1]; 9422 u8 reserved_at_43[0x1b]; 9423 u8 fcs_chk[0x1]; 9424 u8 reserved_at_5f[0x1]; 9425 }; 9426 9427 struct mlx5_ifc_lane_2_module_mapping_bits { 9428 u8 reserved_at_0[0x6]; 9429 u8 rx_lane[0x2]; 9430 u8 reserved_at_8[0x6]; 9431 u8 tx_lane[0x2]; 9432 u8 reserved_at_10[0x8]; 9433 u8 module[0x8]; 9434 }; 9435 9436 struct mlx5_ifc_bufferx_reg_bits { 9437 u8 reserved_at_0[0x6]; 9438 u8 lossy[0x1]; 9439 u8 epsb[0x1]; 9440 u8 reserved_at_8[0xc]; 9441 u8 size[0xc]; 9442 9443 u8 xoff_threshold[0x10]; 9444 u8 xon_threshold[0x10]; 9445 }; 9446 9447 struct mlx5_ifc_set_node_in_bits { 9448 u8 node_description[64][0x8]; 9449 }; 9450 9451 struct mlx5_ifc_register_power_settings_bits { 9452 u8 reserved_at_0[0x18]; 9453 u8 power_settings_level[0x8]; 9454 9455 u8 reserved_at_20[0x60]; 9456 }; 9457 9458 struct mlx5_ifc_register_host_endianness_bits { 9459 u8 he[0x1]; 9460 u8 reserved_at_1[0x1f]; 9461 9462 u8 reserved_at_20[0x60]; 9463 }; 9464 9465 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9466 u8 reserved_at_0[0x20]; 9467 9468 u8 mkey[0x20]; 9469 9470 u8 addressh_63_32[0x20]; 9471 9472 u8 addressl_31_0[0x20]; 9473 }; 9474 9475 struct mlx5_ifc_ud_adrs_vector_bits { 9476 u8 dc_key[0x40]; 9477 9478 u8 ext[0x1]; 9479 u8 reserved_at_41[0x7]; 9480 u8 destination_qp_dct[0x18]; 9481 9482 u8 static_rate[0x4]; 9483 u8 sl_eth_prio[0x4]; 9484 u8 fl[0x1]; 9485 u8 mlid[0x7]; 9486 u8 rlid_udp_sport[0x10]; 9487 9488 u8 reserved_at_80[0x20]; 9489 9490 u8 rmac_47_16[0x20]; 9491 9492 u8 rmac_15_0[0x10]; 9493 u8 tclass[0x8]; 9494 u8 hop_limit[0x8]; 9495 9496 u8 reserved_at_e0[0x1]; 9497 u8 grh[0x1]; 9498 u8 reserved_at_e2[0x2]; 9499 u8 src_addr_index[0x8]; 9500 u8 flow_label[0x14]; 9501 9502 u8 rgid_rip[16][0x8]; 9503 }; 9504 9505 struct mlx5_ifc_pages_req_event_bits { 9506 u8 reserved_at_0[0x10]; 9507 u8 function_id[0x10]; 9508 9509 u8 num_pages[0x20]; 9510 9511 u8 reserved_at_40[0xa0]; 9512 }; 9513 9514 struct mlx5_ifc_eqe_bits { 9515 u8 reserved_at_0[0x8]; 9516 u8 event_type[0x8]; 9517 u8 reserved_at_10[0x8]; 9518 u8 event_sub_type[0x8]; 9519 9520 u8 reserved_at_20[0xe0]; 9521 9522 union mlx5_ifc_event_auto_bits event_data; 9523 9524 u8 reserved_at_1e0[0x10]; 9525 u8 signature[0x8]; 9526 u8 reserved_at_1f8[0x7]; 9527 u8 owner[0x1]; 9528 }; 9529 9530 enum { 9531 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9532 }; 9533 9534 struct mlx5_ifc_cmd_queue_entry_bits { 9535 u8 type[0x8]; 9536 u8 reserved_at_8[0x18]; 9537 9538 u8 input_length[0x20]; 9539 9540 u8 input_mailbox_pointer_63_32[0x20]; 9541 9542 u8 input_mailbox_pointer_31_9[0x17]; 9543 u8 reserved_at_77[0x9]; 9544 9545 u8 command_input_inline_data[16][0x8]; 9546 9547 u8 command_output_inline_data[16][0x8]; 9548 9549 u8 output_mailbox_pointer_63_32[0x20]; 9550 9551 u8 output_mailbox_pointer_31_9[0x17]; 9552 u8 reserved_at_1b7[0x9]; 9553 9554 u8 output_length[0x20]; 9555 9556 u8 token[0x8]; 9557 u8 signature[0x8]; 9558 u8 reserved_at_1f0[0x8]; 9559 u8 status[0x7]; 9560 u8 ownership[0x1]; 9561 }; 9562 9563 struct mlx5_ifc_cmd_out_bits { 9564 u8 status[0x8]; 9565 u8 reserved_at_8[0x18]; 9566 9567 u8 syndrome[0x20]; 9568 9569 u8 command_output[0x20]; 9570 }; 9571 9572 struct mlx5_ifc_cmd_in_bits { 9573 u8 opcode[0x10]; 9574 u8 reserved_at_10[0x10]; 9575 9576 u8 reserved_at_20[0x10]; 9577 u8 op_mod[0x10]; 9578 9579 u8 command[][0x20]; 9580 }; 9581 9582 struct mlx5_ifc_cmd_if_box_bits { 9583 u8 mailbox_data[512][0x8]; 9584 9585 u8 reserved_at_1000[0x180]; 9586 9587 u8 next_pointer_63_32[0x20]; 9588 9589 u8 next_pointer_31_10[0x16]; 9590 u8 reserved_at_11b6[0xa]; 9591 9592 u8 block_number[0x20]; 9593 9594 u8 reserved_at_11e0[0x8]; 9595 u8 token[0x8]; 9596 u8 ctrl_signature[0x8]; 9597 u8 signature[0x8]; 9598 }; 9599 9600 struct mlx5_ifc_mtt_bits { 9601 u8 ptag_63_32[0x20]; 9602 9603 u8 ptag_31_8[0x18]; 9604 u8 reserved_at_38[0x6]; 9605 u8 wr_en[0x1]; 9606 u8 rd_en[0x1]; 9607 }; 9608 9609 struct mlx5_ifc_query_wol_rol_out_bits { 9610 u8 status[0x8]; 9611 u8 reserved_at_8[0x18]; 9612 9613 u8 syndrome[0x20]; 9614 9615 u8 reserved_at_40[0x10]; 9616 u8 rol_mode[0x8]; 9617 u8 wol_mode[0x8]; 9618 9619 u8 reserved_at_60[0x20]; 9620 }; 9621 9622 struct mlx5_ifc_query_wol_rol_in_bits { 9623 u8 opcode[0x10]; 9624 u8 reserved_at_10[0x10]; 9625 9626 u8 reserved_at_20[0x10]; 9627 u8 op_mod[0x10]; 9628 9629 u8 reserved_at_40[0x40]; 9630 }; 9631 9632 struct mlx5_ifc_set_wol_rol_out_bits { 9633 u8 status[0x8]; 9634 u8 reserved_at_8[0x18]; 9635 9636 u8 syndrome[0x20]; 9637 9638 u8 reserved_at_40[0x40]; 9639 }; 9640 9641 struct mlx5_ifc_set_wol_rol_in_bits { 9642 u8 opcode[0x10]; 9643 u8 reserved_at_10[0x10]; 9644 9645 u8 reserved_at_20[0x10]; 9646 u8 op_mod[0x10]; 9647 9648 u8 rol_mode_valid[0x1]; 9649 u8 wol_mode_valid[0x1]; 9650 u8 reserved_at_42[0xe]; 9651 u8 rol_mode[0x8]; 9652 u8 wol_mode[0x8]; 9653 9654 u8 reserved_at_60[0x20]; 9655 }; 9656 9657 enum { 9658 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9659 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9660 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9661 }; 9662 9663 enum { 9664 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9665 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9666 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9667 }; 9668 9669 enum { 9670 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9671 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9672 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9673 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9674 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9675 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9676 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9677 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9678 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9679 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9680 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9681 }; 9682 9683 struct mlx5_ifc_initial_seg_bits { 9684 u8 fw_rev_minor[0x10]; 9685 u8 fw_rev_major[0x10]; 9686 9687 u8 cmd_interface_rev[0x10]; 9688 u8 fw_rev_subminor[0x10]; 9689 9690 u8 reserved_at_40[0x40]; 9691 9692 u8 cmdq_phy_addr_63_32[0x20]; 9693 9694 u8 cmdq_phy_addr_31_12[0x14]; 9695 u8 reserved_at_b4[0x2]; 9696 u8 nic_interface[0x2]; 9697 u8 log_cmdq_size[0x4]; 9698 u8 log_cmdq_stride[0x4]; 9699 9700 u8 command_doorbell_vector[0x20]; 9701 9702 u8 reserved_at_e0[0xf00]; 9703 9704 u8 initializing[0x1]; 9705 u8 reserved_at_fe1[0x4]; 9706 u8 nic_interface_supported[0x3]; 9707 u8 embedded_cpu[0x1]; 9708 u8 reserved_at_fe9[0x17]; 9709 9710 struct mlx5_ifc_health_buffer_bits health_buffer; 9711 9712 u8 no_dram_nic_offset[0x20]; 9713 9714 u8 reserved_at_1220[0x6e40]; 9715 9716 u8 reserved_at_8060[0x1f]; 9717 u8 clear_int[0x1]; 9718 9719 u8 health_syndrome[0x8]; 9720 u8 health_counter[0x18]; 9721 9722 u8 reserved_at_80a0[0x17fc0]; 9723 }; 9724 9725 struct mlx5_ifc_mtpps_reg_bits { 9726 u8 reserved_at_0[0xc]; 9727 u8 cap_number_of_pps_pins[0x4]; 9728 u8 reserved_at_10[0x4]; 9729 u8 cap_max_num_of_pps_in_pins[0x4]; 9730 u8 reserved_at_18[0x4]; 9731 u8 cap_max_num_of_pps_out_pins[0x4]; 9732 9733 u8 reserved_at_20[0x24]; 9734 u8 cap_pin_3_mode[0x4]; 9735 u8 reserved_at_48[0x4]; 9736 u8 cap_pin_2_mode[0x4]; 9737 u8 reserved_at_50[0x4]; 9738 u8 cap_pin_1_mode[0x4]; 9739 u8 reserved_at_58[0x4]; 9740 u8 cap_pin_0_mode[0x4]; 9741 9742 u8 reserved_at_60[0x4]; 9743 u8 cap_pin_7_mode[0x4]; 9744 u8 reserved_at_68[0x4]; 9745 u8 cap_pin_6_mode[0x4]; 9746 u8 reserved_at_70[0x4]; 9747 u8 cap_pin_5_mode[0x4]; 9748 u8 reserved_at_78[0x4]; 9749 u8 cap_pin_4_mode[0x4]; 9750 9751 u8 field_select[0x20]; 9752 u8 reserved_at_a0[0x60]; 9753 9754 u8 enable[0x1]; 9755 u8 reserved_at_101[0xb]; 9756 u8 pattern[0x4]; 9757 u8 reserved_at_110[0x4]; 9758 u8 pin_mode[0x4]; 9759 u8 pin[0x8]; 9760 9761 u8 reserved_at_120[0x20]; 9762 9763 u8 time_stamp[0x40]; 9764 9765 u8 out_pulse_duration[0x10]; 9766 u8 out_periodic_adjustment[0x10]; 9767 u8 enhanced_out_periodic_adjustment[0x20]; 9768 9769 u8 reserved_at_1c0[0x20]; 9770 }; 9771 9772 struct mlx5_ifc_mtppse_reg_bits { 9773 u8 reserved_at_0[0x18]; 9774 u8 pin[0x8]; 9775 u8 event_arm[0x1]; 9776 u8 reserved_at_21[0x1b]; 9777 u8 event_generation_mode[0x4]; 9778 u8 reserved_at_40[0x40]; 9779 }; 9780 9781 struct mlx5_ifc_mcqs_reg_bits { 9782 u8 last_index_flag[0x1]; 9783 u8 reserved_at_1[0x7]; 9784 u8 fw_device[0x8]; 9785 u8 component_index[0x10]; 9786 9787 u8 reserved_at_20[0x10]; 9788 u8 identifier[0x10]; 9789 9790 u8 reserved_at_40[0x17]; 9791 u8 component_status[0x5]; 9792 u8 component_update_state[0x4]; 9793 9794 u8 last_update_state_changer_type[0x4]; 9795 u8 last_update_state_changer_host_id[0x4]; 9796 u8 reserved_at_68[0x18]; 9797 }; 9798 9799 struct mlx5_ifc_mcqi_cap_bits { 9800 u8 supported_info_bitmask[0x20]; 9801 9802 u8 component_size[0x20]; 9803 9804 u8 max_component_size[0x20]; 9805 9806 u8 log_mcda_word_size[0x4]; 9807 u8 reserved_at_64[0xc]; 9808 u8 mcda_max_write_size[0x10]; 9809 9810 u8 rd_en[0x1]; 9811 u8 reserved_at_81[0x1]; 9812 u8 match_chip_id[0x1]; 9813 u8 match_psid[0x1]; 9814 u8 check_user_timestamp[0x1]; 9815 u8 match_base_guid_mac[0x1]; 9816 u8 reserved_at_86[0x1a]; 9817 }; 9818 9819 struct mlx5_ifc_mcqi_version_bits { 9820 u8 reserved_at_0[0x2]; 9821 u8 build_time_valid[0x1]; 9822 u8 user_defined_time_valid[0x1]; 9823 u8 reserved_at_4[0x14]; 9824 u8 version_string_length[0x8]; 9825 9826 u8 version[0x20]; 9827 9828 u8 build_time[0x40]; 9829 9830 u8 user_defined_time[0x40]; 9831 9832 u8 build_tool_version[0x20]; 9833 9834 u8 reserved_at_e0[0x20]; 9835 9836 u8 version_string[92][0x8]; 9837 }; 9838 9839 struct mlx5_ifc_mcqi_activation_method_bits { 9840 u8 pending_server_ac_power_cycle[0x1]; 9841 u8 pending_server_dc_power_cycle[0x1]; 9842 u8 pending_server_reboot[0x1]; 9843 u8 pending_fw_reset[0x1]; 9844 u8 auto_activate[0x1]; 9845 u8 all_hosts_sync[0x1]; 9846 u8 device_hw_reset[0x1]; 9847 u8 reserved_at_7[0x19]; 9848 }; 9849 9850 union mlx5_ifc_mcqi_reg_data_bits { 9851 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9852 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9853 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9854 }; 9855 9856 struct mlx5_ifc_mcqi_reg_bits { 9857 u8 read_pending_component[0x1]; 9858 u8 reserved_at_1[0xf]; 9859 u8 component_index[0x10]; 9860 9861 u8 reserved_at_20[0x20]; 9862 9863 u8 reserved_at_40[0x1b]; 9864 u8 info_type[0x5]; 9865 9866 u8 info_size[0x20]; 9867 9868 u8 offset[0x20]; 9869 9870 u8 reserved_at_a0[0x10]; 9871 u8 data_size[0x10]; 9872 9873 union mlx5_ifc_mcqi_reg_data_bits data[]; 9874 }; 9875 9876 struct mlx5_ifc_mcc_reg_bits { 9877 u8 reserved_at_0[0x4]; 9878 u8 time_elapsed_since_last_cmd[0xc]; 9879 u8 reserved_at_10[0x8]; 9880 u8 instruction[0x8]; 9881 9882 u8 reserved_at_20[0x10]; 9883 u8 component_index[0x10]; 9884 9885 u8 reserved_at_40[0x8]; 9886 u8 update_handle[0x18]; 9887 9888 u8 handle_owner_type[0x4]; 9889 u8 handle_owner_host_id[0x4]; 9890 u8 reserved_at_68[0x1]; 9891 u8 control_progress[0x7]; 9892 u8 error_code[0x8]; 9893 u8 reserved_at_78[0x4]; 9894 u8 control_state[0x4]; 9895 9896 u8 component_size[0x20]; 9897 9898 u8 reserved_at_a0[0x60]; 9899 }; 9900 9901 struct mlx5_ifc_mcda_reg_bits { 9902 u8 reserved_at_0[0x8]; 9903 u8 update_handle[0x18]; 9904 9905 u8 offset[0x20]; 9906 9907 u8 reserved_at_40[0x10]; 9908 u8 size[0x10]; 9909 9910 u8 reserved_at_60[0x20]; 9911 9912 u8 data[][0x20]; 9913 }; 9914 9915 enum { 9916 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9917 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9918 }; 9919 9920 enum { 9921 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9922 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9923 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9924 }; 9925 9926 struct mlx5_ifc_mfrl_reg_bits { 9927 u8 reserved_at_0[0x20]; 9928 9929 u8 reserved_at_20[0x2]; 9930 u8 pci_sync_for_fw_update_start[0x1]; 9931 u8 pci_sync_for_fw_update_resp[0x2]; 9932 u8 rst_type_sel[0x3]; 9933 u8 reserved_at_28[0x8]; 9934 u8 reset_type[0x8]; 9935 u8 reset_level[0x8]; 9936 }; 9937 9938 struct mlx5_ifc_mirc_reg_bits { 9939 u8 reserved_at_0[0x18]; 9940 u8 status_code[0x8]; 9941 9942 u8 reserved_at_20[0x20]; 9943 }; 9944 9945 union mlx5_ifc_ports_control_registers_document_bits { 9946 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9947 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9948 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9949 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9950 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9951 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9952 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9953 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9954 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9955 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9956 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9957 struct mlx5_ifc_paos_reg_bits paos_reg; 9958 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9959 struct mlx5_ifc_peir_reg_bits peir_reg; 9960 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9961 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9962 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9963 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9964 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9965 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9966 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9967 struct mlx5_ifc_plib_reg_bits plib_reg; 9968 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9969 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9970 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9971 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9972 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9973 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9974 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9975 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9976 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9977 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9978 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9979 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9980 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9981 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9982 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9983 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9984 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9985 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9986 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9987 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9988 struct mlx5_ifc_pude_reg_bits pude_reg; 9989 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9990 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9991 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9992 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9993 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9994 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9995 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9996 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9997 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9998 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9999 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10000 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10001 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10002 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10003 u8 reserved_at_0[0x60e0]; 10004 }; 10005 10006 union mlx5_ifc_debug_enhancements_document_bits { 10007 struct mlx5_ifc_health_buffer_bits health_buffer; 10008 u8 reserved_at_0[0x200]; 10009 }; 10010 10011 union mlx5_ifc_uplink_pci_interface_document_bits { 10012 struct mlx5_ifc_initial_seg_bits initial_seg; 10013 u8 reserved_at_0[0x20060]; 10014 }; 10015 10016 struct mlx5_ifc_set_flow_table_root_out_bits { 10017 u8 status[0x8]; 10018 u8 reserved_at_8[0x18]; 10019 10020 u8 syndrome[0x20]; 10021 10022 u8 reserved_at_40[0x40]; 10023 }; 10024 10025 struct mlx5_ifc_set_flow_table_root_in_bits { 10026 u8 opcode[0x10]; 10027 u8 reserved_at_10[0x10]; 10028 10029 u8 reserved_at_20[0x10]; 10030 u8 op_mod[0x10]; 10031 10032 u8 other_vport[0x1]; 10033 u8 reserved_at_41[0xf]; 10034 u8 vport_number[0x10]; 10035 10036 u8 reserved_at_60[0x20]; 10037 10038 u8 table_type[0x8]; 10039 u8 reserved_at_88[0x18]; 10040 10041 u8 reserved_at_a0[0x8]; 10042 u8 table_id[0x18]; 10043 10044 u8 reserved_at_c0[0x8]; 10045 u8 underlay_qpn[0x18]; 10046 u8 reserved_at_e0[0x120]; 10047 }; 10048 10049 enum { 10050 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10051 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10052 }; 10053 10054 struct mlx5_ifc_modify_flow_table_out_bits { 10055 u8 status[0x8]; 10056 u8 reserved_at_8[0x18]; 10057 10058 u8 syndrome[0x20]; 10059 10060 u8 reserved_at_40[0x40]; 10061 }; 10062 10063 struct mlx5_ifc_modify_flow_table_in_bits { 10064 u8 opcode[0x10]; 10065 u8 reserved_at_10[0x10]; 10066 10067 u8 reserved_at_20[0x10]; 10068 u8 op_mod[0x10]; 10069 10070 u8 other_vport[0x1]; 10071 u8 reserved_at_41[0xf]; 10072 u8 vport_number[0x10]; 10073 10074 u8 reserved_at_60[0x10]; 10075 u8 modify_field_select[0x10]; 10076 10077 u8 table_type[0x8]; 10078 u8 reserved_at_88[0x18]; 10079 10080 u8 reserved_at_a0[0x8]; 10081 u8 table_id[0x18]; 10082 10083 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10084 }; 10085 10086 struct mlx5_ifc_ets_tcn_config_reg_bits { 10087 u8 g[0x1]; 10088 u8 b[0x1]; 10089 u8 r[0x1]; 10090 u8 reserved_at_3[0x9]; 10091 u8 group[0x4]; 10092 u8 reserved_at_10[0x9]; 10093 u8 bw_allocation[0x7]; 10094 10095 u8 reserved_at_20[0xc]; 10096 u8 max_bw_units[0x4]; 10097 u8 reserved_at_30[0x8]; 10098 u8 max_bw_value[0x8]; 10099 }; 10100 10101 struct mlx5_ifc_ets_global_config_reg_bits { 10102 u8 reserved_at_0[0x2]; 10103 u8 r[0x1]; 10104 u8 reserved_at_3[0x1d]; 10105 10106 u8 reserved_at_20[0xc]; 10107 u8 max_bw_units[0x4]; 10108 u8 reserved_at_30[0x8]; 10109 u8 max_bw_value[0x8]; 10110 }; 10111 10112 struct mlx5_ifc_qetc_reg_bits { 10113 u8 reserved_at_0[0x8]; 10114 u8 port_number[0x8]; 10115 u8 reserved_at_10[0x30]; 10116 10117 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10118 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10119 }; 10120 10121 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10122 u8 e[0x1]; 10123 u8 reserved_at_01[0x0b]; 10124 u8 prio[0x04]; 10125 }; 10126 10127 struct mlx5_ifc_qpdpm_reg_bits { 10128 u8 reserved_at_0[0x8]; 10129 u8 local_port[0x8]; 10130 u8 reserved_at_10[0x10]; 10131 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10132 }; 10133 10134 struct mlx5_ifc_qpts_reg_bits { 10135 u8 reserved_at_0[0x8]; 10136 u8 local_port[0x8]; 10137 u8 reserved_at_10[0x2d]; 10138 u8 trust_state[0x3]; 10139 }; 10140 10141 struct mlx5_ifc_pptb_reg_bits { 10142 u8 reserved_at_0[0x2]; 10143 u8 mm[0x2]; 10144 u8 reserved_at_4[0x4]; 10145 u8 local_port[0x8]; 10146 u8 reserved_at_10[0x6]; 10147 u8 cm[0x1]; 10148 u8 um[0x1]; 10149 u8 pm[0x8]; 10150 10151 u8 prio_x_buff[0x20]; 10152 10153 u8 pm_msb[0x8]; 10154 u8 reserved_at_48[0x10]; 10155 u8 ctrl_buff[0x4]; 10156 u8 untagged_buff[0x4]; 10157 }; 10158 10159 struct mlx5_ifc_sbcam_reg_bits { 10160 u8 reserved_at_0[0x8]; 10161 u8 feature_group[0x8]; 10162 u8 reserved_at_10[0x8]; 10163 u8 access_reg_group[0x8]; 10164 10165 u8 reserved_at_20[0x20]; 10166 10167 u8 sb_access_reg_cap_mask[4][0x20]; 10168 10169 u8 reserved_at_c0[0x80]; 10170 10171 u8 sb_feature_cap_mask[4][0x20]; 10172 10173 u8 reserved_at_1c0[0x40]; 10174 10175 u8 cap_total_buffer_size[0x20]; 10176 10177 u8 cap_cell_size[0x10]; 10178 u8 cap_max_pg_buffers[0x8]; 10179 u8 cap_num_pool_supported[0x8]; 10180 10181 u8 reserved_at_240[0x8]; 10182 u8 cap_sbsr_stat_size[0x8]; 10183 u8 cap_max_tclass_data[0x8]; 10184 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10185 }; 10186 10187 struct mlx5_ifc_pbmc_reg_bits { 10188 u8 reserved_at_0[0x8]; 10189 u8 local_port[0x8]; 10190 u8 reserved_at_10[0x10]; 10191 10192 u8 xoff_timer_value[0x10]; 10193 u8 xoff_refresh[0x10]; 10194 10195 u8 reserved_at_40[0x9]; 10196 u8 fullness_threshold[0x7]; 10197 u8 port_buffer_size[0x10]; 10198 10199 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10200 10201 u8 reserved_at_2e0[0x40]; 10202 }; 10203 10204 struct mlx5_ifc_qtct_reg_bits { 10205 u8 reserved_at_0[0x8]; 10206 u8 port_number[0x8]; 10207 u8 reserved_at_10[0xd]; 10208 u8 prio[0x3]; 10209 10210 u8 reserved_at_20[0x1d]; 10211 u8 tclass[0x3]; 10212 }; 10213 10214 struct mlx5_ifc_mcia_reg_bits { 10215 u8 l[0x1]; 10216 u8 reserved_at_1[0x7]; 10217 u8 module[0x8]; 10218 u8 reserved_at_10[0x8]; 10219 u8 status[0x8]; 10220 10221 u8 i2c_device_address[0x8]; 10222 u8 page_number[0x8]; 10223 u8 device_address[0x10]; 10224 10225 u8 reserved_at_40[0x10]; 10226 u8 size[0x10]; 10227 10228 u8 reserved_at_60[0x20]; 10229 10230 u8 dword_0[0x20]; 10231 u8 dword_1[0x20]; 10232 u8 dword_2[0x20]; 10233 u8 dword_3[0x20]; 10234 u8 dword_4[0x20]; 10235 u8 dword_5[0x20]; 10236 u8 dword_6[0x20]; 10237 u8 dword_7[0x20]; 10238 u8 dword_8[0x20]; 10239 u8 dword_9[0x20]; 10240 u8 dword_10[0x20]; 10241 u8 dword_11[0x20]; 10242 }; 10243 10244 struct mlx5_ifc_dcbx_param_bits { 10245 u8 dcbx_cee_cap[0x1]; 10246 u8 dcbx_ieee_cap[0x1]; 10247 u8 dcbx_standby_cap[0x1]; 10248 u8 reserved_at_3[0x5]; 10249 u8 port_number[0x8]; 10250 u8 reserved_at_10[0xa]; 10251 u8 max_application_table_size[6]; 10252 u8 reserved_at_20[0x15]; 10253 u8 version_oper[0x3]; 10254 u8 reserved_at_38[5]; 10255 u8 version_admin[0x3]; 10256 u8 willing_admin[0x1]; 10257 u8 reserved_at_41[0x3]; 10258 u8 pfc_cap_oper[0x4]; 10259 u8 reserved_at_48[0x4]; 10260 u8 pfc_cap_admin[0x4]; 10261 u8 reserved_at_50[0x4]; 10262 u8 num_of_tc_oper[0x4]; 10263 u8 reserved_at_58[0x4]; 10264 u8 num_of_tc_admin[0x4]; 10265 u8 remote_willing[0x1]; 10266 u8 reserved_at_61[3]; 10267 u8 remote_pfc_cap[4]; 10268 u8 reserved_at_68[0x14]; 10269 u8 remote_num_of_tc[0x4]; 10270 u8 reserved_at_80[0x18]; 10271 u8 error[0x8]; 10272 u8 reserved_at_a0[0x160]; 10273 }; 10274 10275 struct mlx5_ifc_lagc_bits { 10276 u8 reserved_at_0[0x1d]; 10277 u8 lag_state[0x3]; 10278 10279 u8 reserved_at_20[0x14]; 10280 u8 tx_remap_affinity_2[0x4]; 10281 u8 reserved_at_38[0x4]; 10282 u8 tx_remap_affinity_1[0x4]; 10283 }; 10284 10285 struct mlx5_ifc_create_lag_out_bits { 10286 u8 status[0x8]; 10287 u8 reserved_at_8[0x18]; 10288 10289 u8 syndrome[0x20]; 10290 10291 u8 reserved_at_40[0x40]; 10292 }; 10293 10294 struct mlx5_ifc_create_lag_in_bits { 10295 u8 opcode[0x10]; 10296 u8 reserved_at_10[0x10]; 10297 10298 u8 reserved_at_20[0x10]; 10299 u8 op_mod[0x10]; 10300 10301 struct mlx5_ifc_lagc_bits ctx; 10302 }; 10303 10304 struct mlx5_ifc_modify_lag_out_bits { 10305 u8 status[0x8]; 10306 u8 reserved_at_8[0x18]; 10307 10308 u8 syndrome[0x20]; 10309 10310 u8 reserved_at_40[0x40]; 10311 }; 10312 10313 struct mlx5_ifc_modify_lag_in_bits { 10314 u8 opcode[0x10]; 10315 u8 reserved_at_10[0x10]; 10316 10317 u8 reserved_at_20[0x10]; 10318 u8 op_mod[0x10]; 10319 10320 u8 reserved_at_40[0x20]; 10321 u8 field_select[0x20]; 10322 10323 struct mlx5_ifc_lagc_bits ctx; 10324 }; 10325 10326 struct mlx5_ifc_query_lag_out_bits { 10327 u8 status[0x8]; 10328 u8 reserved_at_8[0x18]; 10329 10330 u8 syndrome[0x20]; 10331 10332 struct mlx5_ifc_lagc_bits ctx; 10333 }; 10334 10335 struct mlx5_ifc_query_lag_in_bits { 10336 u8 opcode[0x10]; 10337 u8 reserved_at_10[0x10]; 10338 10339 u8 reserved_at_20[0x10]; 10340 u8 op_mod[0x10]; 10341 10342 u8 reserved_at_40[0x40]; 10343 }; 10344 10345 struct mlx5_ifc_destroy_lag_out_bits { 10346 u8 status[0x8]; 10347 u8 reserved_at_8[0x18]; 10348 10349 u8 syndrome[0x20]; 10350 10351 u8 reserved_at_40[0x40]; 10352 }; 10353 10354 struct mlx5_ifc_destroy_lag_in_bits { 10355 u8 opcode[0x10]; 10356 u8 reserved_at_10[0x10]; 10357 10358 u8 reserved_at_20[0x10]; 10359 u8 op_mod[0x10]; 10360 10361 u8 reserved_at_40[0x40]; 10362 }; 10363 10364 struct mlx5_ifc_create_vport_lag_out_bits { 10365 u8 status[0x8]; 10366 u8 reserved_at_8[0x18]; 10367 10368 u8 syndrome[0x20]; 10369 10370 u8 reserved_at_40[0x40]; 10371 }; 10372 10373 struct mlx5_ifc_create_vport_lag_in_bits { 10374 u8 opcode[0x10]; 10375 u8 reserved_at_10[0x10]; 10376 10377 u8 reserved_at_20[0x10]; 10378 u8 op_mod[0x10]; 10379 10380 u8 reserved_at_40[0x40]; 10381 }; 10382 10383 struct mlx5_ifc_destroy_vport_lag_out_bits { 10384 u8 status[0x8]; 10385 u8 reserved_at_8[0x18]; 10386 10387 u8 syndrome[0x20]; 10388 10389 u8 reserved_at_40[0x40]; 10390 }; 10391 10392 struct mlx5_ifc_destroy_vport_lag_in_bits { 10393 u8 opcode[0x10]; 10394 u8 reserved_at_10[0x10]; 10395 10396 u8 reserved_at_20[0x10]; 10397 u8 op_mod[0x10]; 10398 10399 u8 reserved_at_40[0x40]; 10400 }; 10401 10402 struct mlx5_ifc_alloc_memic_in_bits { 10403 u8 opcode[0x10]; 10404 u8 reserved_at_10[0x10]; 10405 10406 u8 reserved_at_20[0x10]; 10407 u8 op_mod[0x10]; 10408 10409 u8 reserved_at_30[0x20]; 10410 10411 u8 reserved_at_40[0x18]; 10412 u8 log_memic_addr_alignment[0x8]; 10413 10414 u8 range_start_addr[0x40]; 10415 10416 u8 range_size[0x20]; 10417 10418 u8 memic_size[0x20]; 10419 }; 10420 10421 struct mlx5_ifc_alloc_memic_out_bits { 10422 u8 status[0x8]; 10423 u8 reserved_at_8[0x18]; 10424 10425 u8 syndrome[0x20]; 10426 10427 u8 memic_start_addr[0x40]; 10428 }; 10429 10430 struct mlx5_ifc_dealloc_memic_in_bits { 10431 u8 opcode[0x10]; 10432 u8 reserved_at_10[0x10]; 10433 10434 u8 reserved_at_20[0x10]; 10435 u8 op_mod[0x10]; 10436 10437 u8 reserved_at_40[0x40]; 10438 10439 u8 memic_start_addr[0x40]; 10440 10441 u8 memic_size[0x20]; 10442 10443 u8 reserved_at_e0[0x20]; 10444 }; 10445 10446 struct mlx5_ifc_dealloc_memic_out_bits { 10447 u8 status[0x8]; 10448 u8 reserved_at_8[0x18]; 10449 10450 u8 syndrome[0x20]; 10451 10452 u8 reserved_at_40[0x40]; 10453 }; 10454 10455 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10456 u8 opcode[0x10]; 10457 u8 uid[0x10]; 10458 10459 u8 vhca_tunnel_id[0x10]; 10460 u8 obj_type[0x10]; 10461 10462 u8 obj_id[0x20]; 10463 10464 u8 reserved_at_60[0x20]; 10465 }; 10466 10467 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10468 u8 status[0x8]; 10469 u8 reserved_at_8[0x18]; 10470 10471 u8 syndrome[0x20]; 10472 10473 u8 obj_id[0x20]; 10474 10475 u8 reserved_at_60[0x20]; 10476 }; 10477 10478 struct mlx5_ifc_umem_bits { 10479 u8 reserved_at_0[0x80]; 10480 10481 u8 reserved_at_80[0x1b]; 10482 u8 log_page_size[0x5]; 10483 10484 u8 page_offset[0x20]; 10485 10486 u8 num_of_mtt[0x40]; 10487 10488 struct mlx5_ifc_mtt_bits mtt[]; 10489 }; 10490 10491 struct mlx5_ifc_uctx_bits { 10492 u8 cap[0x20]; 10493 10494 u8 reserved_at_20[0x160]; 10495 }; 10496 10497 struct mlx5_ifc_sw_icm_bits { 10498 u8 modify_field_select[0x40]; 10499 10500 u8 reserved_at_40[0x18]; 10501 u8 log_sw_icm_size[0x8]; 10502 10503 u8 reserved_at_60[0x20]; 10504 10505 u8 sw_icm_start_addr[0x40]; 10506 10507 u8 reserved_at_c0[0x140]; 10508 }; 10509 10510 struct mlx5_ifc_geneve_tlv_option_bits { 10511 u8 modify_field_select[0x40]; 10512 10513 u8 reserved_at_40[0x18]; 10514 u8 geneve_option_fte_index[0x8]; 10515 10516 u8 option_class[0x10]; 10517 u8 option_type[0x8]; 10518 u8 reserved_at_78[0x3]; 10519 u8 option_data_length[0x5]; 10520 10521 u8 reserved_at_80[0x180]; 10522 }; 10523 10524 struct mlx5_ifc_create_umem_in_bits { 10525 u8 opcode[0x10]; 10526 u8 uid[0x10]; 10527 10528 u8 reserved_at_20[0x10]; 10529 u8 op_mod[0x10]; 10530 10531 u8 reserved_at_40[0x40]; 10532 10533 struct mlx5_ifc_umem_bits umem; 10534 }; 10535 10536 struct mlx5_ifc_create_umem_out_bits { 10537 u8 status[0x8]; 10538 u8 reserved_at_8[0x18]; 10539 10540 u8 syndrome[0x20]; 10541 10542 u8 reserved_at_40[0x8]; 10543 u8 umem_id[0x18]; 10544 10545 u8 reserved_at_60[0x20]; 10546 }; 10547 10548 struct mlx5_ifc_destroy_umem_in_bits { 10549 u8 opcode[0x10]; 10550 u8 uid[0x10]; 10551 10552 u8 reserved_at_20[0x10]; 10553 u8 op_mod[0x10]; 10554 10555 u8 reserved_at_40[0x8]; 10556 u8 umem_id[0x18]; 10557 10558 u8 reserved_at_60[0x20]; 10559 }; 10560 10561 struct mlx5_ifc_destroy_umem_out_bits { 10562 u8 status[0x8]; 10563 u8 reserved_at_8[0x18]; 10564 10565 u8 syndrome[0x20]; 10566 10567 u8 reserved_at_40[0x40]; 10568 }; 10569 10570 struct mlx5_ifc_create_uctx_in_bits { 10571 u8 opcode[0x10]; 10572 u8 reserved_at_10[0x10]; 10573 10574 u8 reserved_at_20[0x10]; 10575 u8 op_mod[0x10]; 10576 10577 u8 reserved_at_40[0x40]; 10578 10579 struct mlx5_ifc_uctx_bits uctx; 10580 }; 10581 10582 struct mlx5_ifc_create_uctx_out_bits { 10583 u8 status[0x8]; 10584 u8 reserved_at_8[0x18]; 10585 10586 u8 syndrome[0x20]; 10587 10588 u8 reserved_at_40[0x10]; 10589 u8 uid[0x10]; 10590 10591 u8 reserved_at_60[0x20]; 10592 }; 10593 10594 struct mlx5_ifc_destroy_uctx_in_bits { 10595 u8 opcode[0x10]; 10596 u8 reserved_at_10[0x10]; 10597 10598 u8 reserved_at_20[0x10]; 10599 u8 op_mod[0x10]; 10600 10601 u8 reserved_at_40[0x10]; 10602 u8 uid[0x10]; 10603 10604 u8 reserved_at_60[0x20]; 10605 }; 10606 10607 struct mlx5_ifc_destroy_uctx_out_bits { 10608 u8 status[0x8]; 10609 u8 reserved_at_8[0x18]; 10610 10611 u8 syndrome[0x20]; 10612 10613 u8 reserved_at_40[0x40]; 10614 }; 10615 10616 struct mlx5_ifc_create_sw_icm_in_bits { 10617 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10618 struct mlx5_ifc_sw_icm_bits sw_icm; 10619 }; 10620 10621 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10622 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10623 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10624 }; 10625 10626 struct mlx5_ifc_mtrc_string_db_param_bits { 10627 u8 string_db_base_address[0x20]; 10628 10629 u8 reserved_at_20[0x8]; 10630 u8 string_db_size[0x18]; 10631 }; 10632 10633 struct mlx5_ifc_mtrc_cap_bits { 10634 u8 trace_owner[0x1]; 10635 u8 trace_to_memory[0x1]; 10636 u8 reserved_at_2[0x4]; 10637 u8 trc_ver[0x2]; 10638 u8 reserved_at_8[0x14]; 10639 u8 num_string_db[0x4]; 10640 10641 u8 first_string_trace[0x8]; 10642 u8 num_string_trace[0x8]; 10643 u8 reserved_at_30[0x28]; 10644 10645 u8 log_max_trace_buffer_size[0x8]; 10646 10647 u8 reserved_at_60[0x20]; 10648 10649 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10650 10651 u8 reserved_at_280[0x180]; 10652 }; 10653 10654 struct mlx5_ifc_mtrc_conf_bits { 10655 u8 reserved_at_0[0x1c]; 10656 u8 trace_mode[0x4]; 10657 u8 reserved_at_20[0x18]; 10658 u8 log_trace_buffer_size[0x8]; 10659 u8 trace_mkey[0x20]; 10660 u8 reserved_at_60[0x3a0]; 10661 }; 10662 10663 struct mlx5_ifc_mtrc_stdb_bits { 10664 u8 string_db_index[0x4]; 10665 u8 reserved_at_4[0x4]; 10666 u8 read_size[0x18]; 10667 u8 start_offset[0x20]; 10668 u8 string_db_data[]; 10669 }; 10670 10671 struct mlx5_ifc_mtrc_ctrl_bits { 10672 u8 trace_status[0x2]; 10673 u8 reserved_at_2[0x2]; 10674 u8 arm_event[0x1]; 10675 u8 reserved_at_5[0xb]; 10676 u8 modify_field_select[0x10]; 10677 u8 reserved_at_20[0x2b]; 10678 u8 current_timestamp52_32[0x15]; 10679 u8 current_timestamp31_0[0x20]; 10680 u8 reserved_at_80[0x180]; 10681 }; 10682 10683 struct mlx5_ifc_host_params_context_bits { 10684 u8 host_number[0x8]; 10685 u8 reserved_at_8[0x7]; 10686 u8 host_pf_disabled[0x1]; 10687 u8 host_num_of_vfs[0x10]; 10688 10689 u8 host_total_vfs[0x10]; 10690 u8 host_pci_bus[0x10]; 10691 10692 u8 reserved_at_40[0x10]; 10693 u8 host_pci_device[0x10]; 10694 10695 u8 reserved_at_60[0x10]; 10696 u8 host_pci_function[0x10]; 10697 10698 u8 reserved_at_80[0x180]; 10699 }; 10700 10701 struct mlx5_ifc_query_esw_functions_in_bits { 10702 u8 opcode[0x10]; 10703 u8 reserved_at_10[0x10]; 10704 10705 u8 reserved_at_20[0x10]; 10706 u8 op_mod[0x10]; 10707 10708 u8 reserved_at_40[0x40]; 10709 }; 10710 10711 struct mlx5_ifc_query_esw_functions_out_bits { 10712 u8 status[0x8]; 10713 u8 reserved_at_8[0x18]; 10714 10715 u8 syndrome[0x20]; 10716 10717 u8 reserved_at_40[0x40]; 10718 10719 struct mlx5_ifc_host_params_context_bits host_params_context; 10720 10721 u8 reserved_at_280[0x180]; 10722 u8 host_sf_enable[][0x40]; 10723 }; 10724 10725 struct mlx5_ifc_sf_partition_bits { 10726 u8 reserved_at_0[0x10]; 10727 u8 log_num_sf[0x8]; 10728 u8 log_sf_bar_size[0x8]; 10729 }; 10730 10731 struct mlx5_ifc_query_sf_partitions_out_bits { 10732 u8 status[0x8]; 10733 u8 reserved_at_8[0x18]; 10734 10735 u8 syndrome[0x20]; 10736 10737 u8 reserved_at_40[0x18]; 10738 u8 num_sf_partitions[0x8]; 10739 10740 u8 reserved_at_60[0x20]; 10741 10742 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10743 }; 10744 10745 struct mlx5_ifc_query_sf_partitions_in_bits { 10746 u8 opcode[0x10]; 10747 u8 reserved_at_10[0x10]; 10748 10749 u8 reserved_at_20[0x10]; 10750 u8 op_mod[0x10]; 10751 10752 u8 reserved_at_40[0x40]; 10753 }; 10754 10755 struct mlx5_ifc_dealloc_sf_out_bits { 10756 u8 status[0x8]; 10757 u8 reserved_at_8[0x18]; 10758 10759 u8 syndrome[0x20]; 10760 10761 u8 reserved_at_40[0x40]; 10762 }; 10763 10764 struct mlx5_ifc_dealloc_sf_in_bits { 10765 u8 opcode[0x10]; 10766 u8 reserved_at_10[0x10]; 10767 10768 u8 reserved_at_20[0x10]; 10769 u8 op_mod[0x10]; 10770 10771 u8 reserved_at_40[0x10]; 10772 u8 function_id[0x10]; 10773 10774 u8 reserved_at_60[0x20]; 10775 }; 10776 10777 struct mlx5_ifc_alloc_sf_out_bits { 10778 u8 status[0x8]; 10779 u8 reserved_at_8[0x18]; 10780 10781 u8 syndrome[0x20]; 10782 10783 u8 reserved_at_40[0x40]; 10784 }; 10785 10786 struct mlx5_ifc_alloc_sf_in_bits { 10787 u8 opcode[0x10]; 10788 u8 reserved_at_10[0x10]; 10789 10790 u8 reserved_at_20[0x10]; 10791 u8 op_mod[0x10]; 10792 10793 u8 reserved_at_40[0x10]; 10794 u8 function_id[0x10]; 10795 10796 u8 reserved_at_60[0x20]; 10797 }; 10798 10799 struct mlx5_ifc_affiliated_event_header_bits { 10800 u8 reserved_at_0[0x10]; 10801 u8 obj_type[0x10]; 10802 10803 u8 obj_id[0x20]; 10804 }; 10805 10806 enum { 10807 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10808 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10809 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10810 }; 10811 10812 enum { 10813 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10814 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10815 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10816 }; 10817 10818 enum { 10819 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10820 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10821 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10822 }; 10823 10824 struct mlx5_ifc_ipsec_obj_bits { 10825 u8 modify_field_select[0x40]; 10826 u8 full_offload[0x1]; 10827 u8 reserved_at_41[0x1]; 10828 u8 esn_en[0x1]; 10829 u8 esn_overlap[0x1]; 10830 u8 reserved_at_44[0x2]; 10831 u8 icv_length[0x2]; 10832 u8 reserved_at_48[0x4]; 10833 u8 aso_return_reg[0x4]; 10834 u8 reserved_at_50[0x10]; 10835 10836 u8 esn_msb[0x20]; 10837 10838 u8 reserved_at_80[0x8]; 10839 u8 dekn[0x18]; 10840 10841 u8 salt[0x20]; 10842 10843 u8 implicit_iv[0x40]; 10844 10845 u8 reserved_at_100[0x700]; 10846 }; 10847 10848 struct mlx5_ifc_create_ipsec_obj_in_bits { 10849 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10850 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10851 }; 10852 10853 enum { 10854 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10855 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10856 }; 10857 10858 struct mlx5_ifc_query_ipsec_obj_out_bits { 10859 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10860 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10861 }; 10862 10863 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10864 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10865 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10866 }; 10867 10868 struct mlx5_ifc_encryption_key_obj_bits { 10869 u8 modify_field_select[0x40]; 10870 10871 u8 reserved_at_40[0x14]; 10872 u8 key_size[0x4]; 10873 u8 reserved_at_58[0x4]; 10874 u8 key_type[0x4]; 10875 10876 u8 reserved_at_60[0x8]; 10877 u8 pd[0x18]; 10878 10879 u8 reserved_at_80[0x180]; 10880 u8 key[8][0x20]; 10881 10882 u8 reserved_at_300[0x500]; 10883 }; 10884 10885 struct mlx5_ifc_create_encryption_key_in_bits { 10886 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10887 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10888 }; 10889 10890 struct mlx5_ifc_sampler_obj_bits { 10891 u8 modify_field_select[0x40]; 10892 10893 u8 table_type[0x8]; 10894 u8 level[0x8]; 10895 u8 reserved_at_50[0xf]; 10896 u8 ignore_flow_level[0x1]; 10897 10898 u8 sample_ratio[0x20]; 10899 10900 u8 reserved_at_80[0x8]; 10901 u8 sample_table_id[0x18]; 10902 10903 u8 reserved_at_a0[0x8]; 10904 u8 default_table_id[0x18]; 10905 10906 u8 sw_steering_icm_address_rx[0x40]; 10907 u8 sw_steering_icm_address_tx[0x40]; 10908 10909 u8 reserved_at_140[0xa0]; 10910 }; 10911 10912 struct mlx5_ifc_create_sampler_obj_in_bits { 10913 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10914 struct mlx5_ifc_sampler_obj_bits sampler_object; 10915 }; 10916 10917 enum { 10918 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10919 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10920 }; 10921 10922 enum { 10923 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10924 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10925 }; 10926 10927 struct mlx5_ifc_tls_static_params_bits { 10928 u8 const_2[0x2]; 10929 u8 tls_version[0x4]; 10930 u8 const_1[0x2]; 10931 u8 reserved_at_8[0x14]; 10932 u8 encryption_standard[0x4]; 10933 10934 u8 reserved_at_20[0x20]; 10935 10936 u8 initial_record_number[0x40]; 10937 10938 u8 resync_tcp_sn[0x20]; 10939 10940 u8 gcm_iv[0x20]; 10941 10942 u8 implicit_iv[0x40]; 10943 10944 u8 reserved_at_100[0x8]; 10945 u8 dek_index[0x18]; 10946 10947 u8 reserved_at_120[0xe0]; 10948 }; 10949 10950 struct mlx5_ifc_tls_progress_params_bits { 10951 u8 next_record_tcp_sn[0x20]; 10952 10953 u8 hw_resync_tcp_sn[0x20]; 10954 10955 u8 record_tracker_state[0x2]; 10956 u8 auth_state[0x2]; 10957 u8 reserved_at_44[0x4]; 10958 u8 hw_offset_record_number[0x18]; 10959 }; 10960 10961 enum { 10962 MLX5_MTT_PERM_READ = 1 << 0, 10963 MLX5_MTT_PERM_WRITE = 1 << 1, 10964 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 10965 }; 10966 10967 #endif /* MLX5_IFC_H */ 10968