1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 92 MLX5_OBJ_TYPE_MKEY = 0xff01, 93 MLX5_OBJ_TYPE_QP = 0xff02, 94 MLX5_OBJ_TYPE_PSV = 0xff03, 95 MLX5_OBJ_TYPE_RMP = 0xff04, 96 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 97 MLX5_OBJ_TYPE_RQ = 0xff06, 98 MLX5_OBJ_TYPE_SQ = 0xff07, 99 MLX5_OBJ_TYPE_TIR = 0xff08, 100 MLX5_OBJ_TYPE_TIS = 0xff09, 101 MLX5_OBJ_TYPE_DCT = 0xff0a, 102 MLX5_OBJ_TYPE_XRQ = 0xff0b, 103 MLX5_OBJ_TYPE_RQT = 0xff0e, 104 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 105 MLX5_OBJ_TYPE_CQ = 0xff10, 106 }; 107 108 enum { 109 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 110 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 111 MLX5_CMD_OP_INIT_HCA = 0x102, 112 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 113 MLX5_CMD_OP_ENABLE_HCA = 0x104, 114 MLX5_CMD_OP_DISABLE_HCA = 0x105, 115 MLX5_CMD_OP_QUERY_PAGES = 0x107, 116 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 117 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 118 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 119 MLX5_CMD_OP_SET_ISSI = 0x10b, 120 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 121 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 122 MLX5_CMD_OP_ALLOC_SF = 0x113, 123 MLX5_CMD_OP_DEALLOC_SF = 0x114, 124 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 125 MLX5_CMD_OP_RESUME_VHCA = 0x116, 126 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 127 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 128 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 source_vhca_port[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 geneve_tlv_option_0_exist[0x1]; 375 u8 reserved_at_42[0x3]; 376 u8 outer_first_mpls_over_udp[0x4]; 377 u8 outer_first_mpls_over_gre[0x4]; 378 u8 inner_first_mpls[0x4]; 379 u8 outer_first_mpls[0x4]; 380 u8 reserved_at_55[0x2]; 381 u8 outer_esp_spi[0x1]; 382 u8 reserved_at_58[0x2]; 383 u8 bth_dst_qp[0x1]; 384 u8 reserved_at_5b[0x5]; 385 386 u8 reserved_at_60[0x18]; 387 u8 metadata_reg_c_7[0x1]; 388 u8 metadata_reg_c_6[0x1]; 389 u8 metadata_reg_c_5[0x1]; 390 u8 metadata_reg_c_4[0x1]; 391 u8 metadata_reg_c_3[0x1]; 392 u8 metadata_reg_c_2[0x1]; 393 u8 metadata_reg_c_1[0x1]; 394 u8 metadata_reg_c_0[0x1]; 395 }; 396 397 struct mlx5_ifc_flow_table_fields_supported_2_bits { 398 u8 reserved_at_0[0xe]; 399 u8 bth_opcode[0x1]; 400 u8 reserved_at_f[0x11]; 401 402 u8 reserved_at_20[0x60]; 403 }; 404 405 struct mlx5_ifc_flow_table_prop_layout_bits { 406 u8 ft_support[0x1]; 407 u8 reserved_at_1[0x1]; 408 u8 flow_counter[0x1]; 409 u8 flow_modify_en[0x1]; 410 u8 modify_root[0x1]; 411 u8 identified_miss_table_mode[0x1]; 412 u8 flow_table_modify[0x1]; 413 u8 reformat[0x1]; 414 u8 decap[0x1]; 415 u8 reserved_at_9[0x1]; 416 u8 pop_vlan[0x1]; 417 u8 push_vlan[0x1]; 418 u8 reserved_at_c[0x1]; 419 u8 pop_vlan_2[0x1]; 420 u8 push_vlan_2[0x1]; 421 u8 reformat_and_vlan_action[0x1]; 422 u8 reserved_at_10[0x1]; 423 u8 sw_owner[0x1]; 424 u8 reformat_l3_tunnel_to_l2[0x1]; 425 u8 reformat_l2_to_l3_tunnel[0x1]; 426 u8 reformat_and_modify_action[0x1]; 427 u8 ignore_flow_level[0x1]; 428 u8 reserved_at_16[0x1]; 429 u8 table_miss_action_domain[0x1]; 430 u8 termination_table[0x1]; 431 u8 reformat_and_fwd_to_table[0x1]; 432 u8 reserved_at_1a[0x2]; 433 u8 ipsec_encrypt[0x1]; 434 u8 ipsec_decrypt[0x1]; 435 u8 sw_owner_v2[0x1]; 436 u8 reserved_at_1f[0x1]; 437 438 u8 termination_table_raw_traffic[0x1]; 439 u8 reserved_at_21[0x1]; 440 u8 log_max_ft_size[0x6]; 441 u8 log_max_modify_header_context[0x8]; 442 u8 max_modify_header_actions[0x8]; 443 u8 max_ft_level[0x8]; 444 445 u8 reserved_at_40[0x6]; 446 u8 execute_aso[0x1]; 447 u8 reserved_at_47[0x19]; 448 449 u8 reserved_at_60[0x2]; 450 u8 reformat_insert[0x1]; 451 u8 reformat_remove[0x1]; 452 u8 reserver_at_64[0x14]; 453 u8 log_max_ft_num[0x8]; 454 455 u8 reserved_at_80[0x10]; 456 u8 log_max_flow_counter[0x8]; 457 u8 log_max_destination[0x8]; 458 459 u8 reserved_at_a0[0x18]; 460 u8 log_max_flow[0x8]; 461 462 u8 reserved_at_c0[0x40]; 463 464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 465 466 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 467 }; 468 469 struct mlx5_ifc_odp_per_transport_service_cap_bits { 470 u8 send[0x1]; 471 u8 receive[0x1]; 472 u8 write[0x1]; 473 u8 read[0x1]; 474 u8 atomic[0x1]; 475 u8 srq_receive[0x1]; 476 u8 reserved_at_6[0x1a]; 477 }; 478 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 480 u8 smac_47_16[0x20]; 481 482 u8 smac_15_0[0x10]; 483 u8 ethertype[0x10]; 484 485 u8 dmac_47_16[0x20]; 486 487 u8 dmac_15_0[0x10]; 488 u8 first_prio[0x3]; 489 u8 first_cfi[0x1]; 490 u8 first_vid[0xc]; 491 492 u8 ip_protocol[0x8]; 493 u8 ip_dscp[0x6]; 494 u8 ip_ecn[0x2]; 495 u8 cvlan_tag[0x1]; 496 u8 svlan_tag[0x1]; 497 u8 frag[0x1]; 498 u8 ip_version[0x4]; 499 u8 tcp_flags[0x9]; 500 501 u8 tcp_sport[0x10]; 502 u8 tcp_dport[0x10]; 503 504 u8 reserved_at_c0[0x10]; 505 u8 ipv4_ihl[0x4]; 506 u8 reserved_at_c4[0x4]; 507 508 u8 ttl_hoplimit[0x8]; 509 510 u8 udp_sport[0x10]; 511 u8 udp_dport[0x10]; 512 513 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 514 515 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 516 }; 517 518 struct mlx5_ifc_nvgre_key_bits { 519 u8 hi[0x18]; 520 u8 lo[0x8]; 521 }; 522 523 union mlx5_ifc_gre_key_bits { 524 struct mlx5_ifc_nvgre_key_bits nvgre; 525 u8 key[0x20]; 526 }; 527 528 struct mlx5_ifc_fte_match_set_misc_bits { 529 u8 gre_c_present[0x1]; 530 u8 reserved_at_1[0x1]; 531 u8 gre_k_present[0x1]; 532 u8 gre_s_present[0x1]; 533 u8 source_vhca_port[0x4]; 534 u8 source_sqn[0x18]; 535 536 u8 source_eswitch_owner_vhca_id[0x10]; 537 u8 source_port[0x10]; 538 539 u8 outer_second_prio[0x3]; 540 u8 outer_second_cfi[0x1]; 541 u8 outer_second_vid[0xc]; 542 u8 inner_second_prio[0x3]; 543 u8 inner_second_cfi[0x1]; 544 u8 inner_second_vid[0xc]; 545 546 u8 outer_second_cvlan_tag[0x1]; 547 u8 inner_second_cvlan_tag[0x1]; 548 u8 outer_second_svlan_tag[0x1]; 549 u8 inner_second_svlan_tag[0x1]; 550 u8 reserved_at_64[0xc]; 551 u8 gre_protocol[0x10]; 552 553 union mlx5_ifc_gre_key_bits gre_key; 554 555 u8 vxlan_vni[0x18]; 556 u8 bth_opcode[0x8]; 557 558 u8 geneve_vni[0x18]; 559 u8 reserved_at_d8[0x6]; 560 u8 geneve_tlv_option_0_exist[0x1]; 561 u8 geneve_oam[0x1]; 562 563 u8 reserved_at_e0[0xc]; 564 u8 outer_ipv6_flow_label[0x14]; 565 566 u8 reserved_at_100[0xc]; 567 u8 inner_ipv6_flow_label[0x14]; 568 569 u8 reserved_at_120[0xa]; 570 u8 geneve_opt_len[0x6]; 571 u8 geneve_protocol_type[0x10]; 572 573 u8 reserved_at_140[0x8]; 574 u8 bth_dst_qp[0x18]; 575 u8 reserved_at_160[0x20]; 576 u8 outer_esp_spi[0x20]; 577 u8 reserved_at_1a0[0x60]; 578 }; 579 580 struct mlx5_ifc_fte_match_mpls_bits { 581 u8 mpls_label[0x14]; 582 u8 mpls_exp[0x3]; 583 u8 mpls_s_bos[0x1]; 584 u8 mpls_ttl[0x8]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc2_bits { 588 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 589 590 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 591 592 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 593 594 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 595 596 u8 metadata_reg_c_7[0x20]; 597 598 u8 metadata_reg_c_6[0x20]; 599 600 u8 metadata_reg_c_5[0x20]; 601 602 u8 metadata_reg_c_4[0x20]; 603 604 u8 metadata_reg_c_3[0x20]; 605 606 u8 metadata_reg_c_2[0x20]; 607 608 u8 metadata_reg_c_1[0x20]; 609 610 u8 metadata_reg_c_0[0x20]; 611 612 u8 metadata_reg_a[0x20]; 613 614 u8 reserved_at_1a0[0x60]; 615 }; 616 617 struct mlx5_ifc_fte_match_set_misc3_bits { 618 u8 inner_tcp_seq_num[0x20]; 619 620 u8 outer_tcp_seq_num[0x20]; 621 622 u8 inner_tcp_ack_num[0x20]; 623 624 u8 outer_tcp_ack_num[0x20]; 625 626 u8 reserved_at_80[0x8]; 627 u8 outer_vxlan_gpe_vni[0x18]; 628 629 u8 outer_vxlan_gpe_next_protocol[0x8]; 630 u8 outer_vxlan_gpe_flags[0x8]; 631 u8 reserved_at_b0[0x10]; 632 633 u8 icmp_header_data[0x20]; 634 635 u8 icmpv6_header_data[0x20]; 636 637 u8 icmp_type[0x8]; 638 u8 icmp_code[0x8]; 639 u8 icmpv6_type[0x8]; 640 u8 icmpv6_code[0x8]; 641 642 u8 geneve_tlv_option_0_data[0x20]; 643 644 u8 gtpu_teid[0x20]; 645 646 u8 gtpu_msg_type[0x8]; 647 u8 gtpu_msg_flags[0x8]; 648 u8 reserved_at_170[0x10]; 649 650 u8 gtpu_dw_2[0x20]; 651 652 u8 gtpu_first_ext_dw_0[0x20]; 653 654 u8 gtpu_dw_0[0x20]; 655 656 u8 reserved_at_1e0[0x20]; 657 }; 658 659 struct mlx5_ifc_fte_match_set_misc4_bits { 660 u8 prog_sample_field_value_0[0x20]; 661 662 u8 prog_sample_field_id_0[0x20]; 663 664 u8 prog_sample_field_value_1[0x20]; 665 666 u8 prog_sample_field_id_1[0x20]; 667 668 u8 prog_sample_field_value_2[0x20]; 669 670 u8 prog_sample_field_id_2[0x20]; 671 672 u8 prog_sample_field_value_3[0x20]; 673 674 u8 prog_sample_field_id_3[0x20]; 675 676 u8 reserved_at_100[0x100]; 677 }; 678 679 struct mlx5_ifc_fte_match_set_misc5_bits { 680 u8 macsec_tag_0[0x20]; 681 682 u8 macsec_tag_1[0x20]; 683 684 u8 macsec_tag_2[0x20]; 685 686 u8 macsec_tag_3[0x20]; 687 688 u8 tunnel_header_0[0x20]; 689 690 u8 tunnel_header_1[0x20]; 691 692 u8 tunnel_header_2[0x20]; 693 694 u8 tunnel_header_3[0x20]; 695 696 u8 reserved_at_100[0x100]; 697 }; 698 699 struct mlx5_ifc_cmd_pas_bits { 700 u8 pa_h[0x20]; 701 702 u8 pa_l[0x14]; 703 u8 reserved_at_34[0xc]; 704 }; 705 706 struct mlx5_ifc_uint64_bits { 707 u8 hi[0x20]; 708 709 u8 lo[0x20]; 710 }; 711 712 enum { 713 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 714 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 715 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 716 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 717 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 718 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 719 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 720 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 721 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 722 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 723 }; 724 725 struct mlx5_ifc_ads_bits { 726 u8 fl[0x1]; 727 u8 free_ar[0x1]; 728 u8 reserved_at_2[0xe]; 729 u8 pkey_index[0x10]; 730 731 u8 reserved_at_20[0x8]; 732 u8 grh[0x1]; 733 u8 mlid[0x7]; 734 u8 rlid[0x10]; 735 736 u8 ack_timeout[0x5]; 737 u8 reserved_at_45[0x3]; 738 u8 src_addr_index[0x8]; 739 u8 reserved_at_50[0x4]; 740 u8 stat_rate[0x4]; 741 u8 hop_limit[0x8]; 742 743 u8 reserved_at_60[0x4]; 744 u8 tclass[0x8]; 745 u8 flow_label[0x14]; 746 747 u8 rgid_rip[16][0x8]; 748 749 u8 reserved_at_100[0x4]; 750 u8 f_dscp[0x1]; 751 u8 f_ecn[0x1]; 752 u8 reserved_at_106[0x1]; 753 u8 f_eth_prio[0x1]; 754 u8 ecn[0x2]; 755 u8 dscp[0x6]; 756 u8 udp_sport[0x10]; 757 758 u8 dei_cfi[0x1]; 759 u8 eth_prio[0x3]; 760 u8 sl[0x4]; 761 u8 vhca_port_num[0x8]; 762 u8 rmac_47_32[0x10]; 763 764 u8 rmac_31_0[0x20]; 765 }; 766 767 struct mlx5_ifc_flow_table_nic_cap_bits { 768 u8 nic_rx_multi_path_tirs[0x1]; 769 u8 nic_rx_multi_path_tirs_fts[0x1]; 770 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 771 u8 reserved_at_3[0x4]; 772 u8 sw_owner_reformat_supported[0x1]; 773 u8 reserved_at_8[0x18]; 774 775 u8 encap_general_header[0x1]; 776 u8 reserved_at_21[0xa]; 777 u8 log_max_packet_reformat_context[0x5]; 778 u8 reserved_at_30[0x6]; 779 u8 max_encap_header_size[0xa]; 780 u8 reserved_at_40[0x1c0]; 781 782 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 783 784 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 785 786 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 787 788 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 789 790 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 791 792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 793 794 u8 reserved_at_e00[0x700]; 795 796 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 797 798 u8 reserved_at_1580[0x280]; 799 800 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 801 802 u8 reserved_at_1880[0x780]; 803 804 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 805 806 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 807 808 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 809 810 u8 reserved_at_20c0[0x5f40]; 811 }; 812 813 struct mlx5_ifc_port_selection_cap_bits { 814 u8 reserved_at_0[0x10]; 815 u8 port_select_flow_table[0x1]; 816 u8 reserved_at_11[0xf]; 817 818 u8 reserved_at_20[0x1e0]; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 821 822 u8 reserved_at_400[0x7c00]; 823 }; 824 825 enum { 826 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 827 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 828 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 829 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 830 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 831 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 832 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 833 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 834 }; 835 836 struct mlx5_ifc_flow_table_eswitch_cap_bits { 837 u8 fdb_to_vport_reg_c_id[0x8]; 838 u8 reserved_at_8[0xd]; 839 u8 fdb_modify_header_fwd_to_table[0x1]; 840 u8 fdb_ipv4_ttl_modify[0x1]; 841 u8 flow_source[0x1]; 842 u8 reserved_at_18[0x2]; 843 u8 multi_fdb_encap[0x1]; 844 u8 egress_acl_forward_to_vport[0x1]; 845 u8 fdb_multi_path_to_table[0x1]; 846 u8 reserved_at_1d[0x3]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 851 852 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 853 854 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 855 856 u8 reserved_at_800[0x1000]; 857 858 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 859 860 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 861 862 u8 sw_steering_uplink_icm_address_rx[0x40]; 863 864 u8 sw_steering_uplink_icm_address_tx[0x40]; 865 866 u8 reserved_at_1900[0x6700]; 867 }; 868 869 enum { 870 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 871 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 872 }; 873 874 struct mlx5_ifc_e_switch_cap_bits { 875 u8 vport_svlan_strip[0x1]; 876 u8 vport_cvlan_strip[0x1]; 877 u8 vport_svlan_insert[0x1]; 878 u8 vport_cvlan_insert_if_not_exist[0x1]; 879 u8 vport_cvlan_insert_overwrite[0x1]; 880 u8 reserved_at_5[0x2]; 881 u8 esw_shared_ingress_acl[0x1]; 882 u8 esw_uplink_ingress_acl[0x1]; 883 u8 root_ft_on_other_esw[0x1]; 884 u8 reserved_at_a[0xf]; 885 u8 esw_functions_changed[0x1]; 886 u8 reserved_at_1a[0x1]; 887 u8 ecpf_vport_exists[0x1]; 888 u8 counter_eswitch_affinity[0x1]; 889 u8 merged_eswitch[0x1]; 890 u8 nic_vport_node_guid_modify[0x1]; 891 u8 nic_vport_port_guid_modify[0x1]; 892 893 u8 vxlan_encap_decap[0x1]; 894 u8 nvgre_encap_decap[0x1]; 895 u8 reserved_at_22[0x1]; 896 u8 log_max_fdb_encap_uplink[0x5]; 897 u8 reserved_at_21[0x3]; 898 u8 log_max_packet_reformat_context[0x5]; 899 u8 reserved_2b[0x6]; 900 u8 max_encap_header_size[0xa]; 901 902 u8 reserved_at_40[0xb]; 903 u8 log_max_esw_sf[0x5]; 904 u8 esw_sf_base_id[0x10]; 905 906 u8 reserved_at_60[0x7a0]; 907 908 }; 909 910 struct mlx5_ifc_qos_cap_bits { 911 u8 packet_pacing[0x1]; 912 u8 esw_scheduling[0x1]; 913 u8 esw_bw_share[0x1]; 914 u8 esw_rate_limit[0x1]; 915 u8 reserved_at_4[0x1]; 916 u8 packet_pacing_burst_bound[0x1]; 917 u8 packet_pacing_typical_size[0x1]; 918 u8 reserved_at_7[0x1]; 919 u8 nic_sq_scheduling[0x1]; 920 u8 nic_bw_share[0x1]; 921 u8 nic_rate_limit[0x1]; 922 u8 packet_pacing_uid[0x1]; 923 u8 log_esw_max_sched_depth[0x4]; 924 u8 reserved_at_10[0x10]; 925 926 u8 reserved_at_20[0xb]; 927 u8 log_max_qos_nic_queue_group[0x5]; 928 u8 reserved_at_30[0x10]; 929 930 u8 packet_pacing_max_rate[0x20]; 931 932 u8 packet_pacing_min_rate[0x20]; 933 934 u8 reserved_at_80[0x10]; 935 u8 packet_pacing_rate_table_size[0x10]; 936 937 u8 esw_element_type[0x10]; 938 u8 esw_tsar_type[0x10]; 939 940 u8 reserved_at_c0[0x10]; 941 u8 max_qos_para_vport[0x10]; 942 943 u8 max_tsar_bw_share[0x20]; 944 945 u8 reserved_at_100[0x20]; 946 947 u8 reserved_at_120[0x3]; 948 u8 log_meter_aso_granularity[0x5]; 949 u8 reserved_at_128[0x3]; 950 u8 log_meter_aso_max_alloc[0x5]; 951 u8 reserved_at_130[0x3]; 952 u8 log_max_num_meter_aso[0x5]; 953 u8 reserved_at_138[0x8]; 954 955 u8 reserved_at_140[0x6c0]; 956 }; 957 958 struct mlx5_ifc_debug_cap_bits { 959 u8 core_dump_general[0x1]; 960 u8 core_dump_qp[0x1]; 961 u8 reserved_at_2[0x7]; 962 u8 resource_dump[0x1]; 963 u8 reserved_at_a[0x16]; 964 965 u8 reserved_at_20[0x2]; 966 u8 stall_detect[0x1]; 967 u8 reserved_at_23[0x1d]; 968 969 u8 reserved_at_40[0x7c0]; 970 }; 971 972 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 973 u8 csum_cap[0x1]; 974 u8 vlan_cap[0x1]; 975 u8 lro_cap[0x1]; 976 u8 lro_psh_flag[0x1]; 977 u8 lro_time_stamp[0x1]; 978 u8 reserved_at_5[0x2]; 979 u8 wqe_vlan_insert[0x1]; 980 u8 self_lb_en_modifiable[0x1]; 981 u8 reserved_at_9[0x2]; 982 u8 max_lso_cap[0x5]; 983 u8 multi_pkt_send_wqe[0x2]; 984 u8 wqe_inline_mode[0x2]; 985 u8 rss_ind_tbl_cap[0x4]; 986 u8 reg_umr_sq[0x1]; 987 u8 scatter_fcs[0x1]; 988 u8 enhanced_multi_pkt_send_wqe[0x1]; 989 u8 tunnel_lso_const_out_ip_id[0x1]; 990 u8 tunnel_lro_gre[0x1]; 991 u8 tunnel_lro_vxlan[0x1]; 992 u8 tunnel_stateless_gre[0x1]; 993 u8 tunnel_stateless_vxlan[0x1]; 994 995 u8 swp[0x1]; 996 u8 swp_csum[0x1]; 997 u8 swp_lso[0x1]; 998 u8 cqe_checksum_full[0x1]; 999 u8 tunnel_stateless_geneve_tx[0x1]; 1000 u8 tunnel_stateless_mpls_over_udp[0x1]; 1001 u8 tunnel_stateless_mpls_over_gre[0x1]; 1002 u8 tunnel_stateless_vxlan_gpe[0x1]; 1003 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1004 u8 tunnel_stateless_ip_over_ip[0x1]; 1005 u8 insert_trailer[0x1]; 1006 u8 reserved_at_2b[0x1]; 1007 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1008 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1009 u8 reserved_at_2e[0x2]; 1010 u8 max_vxlan_udp_ports[0x8]; 1011 u8 reserved_at_38[0x6]; 1012 u8 max_geneve_opt_len[0x1]; 1013 u8 tunnel_stateless_geneve_rx[0x1]; 1014 1015 u8 reserved_at_40[0x10]; 1016 u8 lro_min_mss_size[0x10]; 1017 1018 u8 reserved_at_60[0x120]; 1019 1020 u8 lro_timer_supported_periods[4][0x20]; 1021 1022 u8 reserved_at_200[0x600]; 1023 }; 1024 1025 enum { 1026 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1027 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1028 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1029 }; 1030 1031 struct mlx5_ifc_roce_cap_bits { 1032 u8 roce_apm[0x1]; 1033 u8 reserved_at_1[0x3]; 1034 u8 sw_r_roce_src_udp_port[0x1]; 1035 u8 fl_rc_qp_when_roce_disabled[0x1]; 1036 u8 fl_rc_qp_when_roce_enabled[0x1]; 1037 u8 reserved_at_7[0x17]; 1038 u8 qp_ts_format[0x2]; 1039 1040 u8 reserved_at_20[0x60]; 1041 1042 u8 reserved_at_80[0xc]; 1043 u8 l3_type[0x4]; 1044 u8 reserved_at_90[0x8]; 1045 u8 roce_version[0x8]; 1046 1047 u8 reserved_at_a0[0x10]; 1048 u8 r_roce_dest_udp_port[0x10]; 1049 1050 u8 r_roce_max_src_udp_port[0x10]; 1051 u8 r_roce_min_src_udp_port[0x10]; 1052 1053 u8 reserved_at_e0[0x10]; 1054 u8 roce_address_table_size[0x10]; 1055 1056 u8 reserved_at_100[0x700]; 1057 }; 1058 1059 struct mlx5_ifc_sync_steering_in_bits { 1060 u8 opcode[0x10]; 1061 u8 uid[0x10]; 1062 1063 u8 reserved_at_20[0x10]; 1064 u8 op_mod[0x10]; 1065 1066 u8 reserved_at_40[0xc0]; 1067 }; 1068 1069 struct mlx5_ifc_sync_steering_out_bits { 1070 u8 status[0x8]; 1071 u8 reserved_at_8[0x18]; 1072 1073 u8 syndrome[0x20]; 1074 1075 u8 reserved_at_40[0x40]; 1076 }; 1077 1078 struct mlx5_ifc_device_mem_cap_bits { 1079 u8 memic[0x1]; 1080 u8 reserved_at_1[0x1f]; 1081 1082 u8 reserved_at_20[0xb]; 1083 u8 log_min_memic_alloc_size[0x5]; 1084 u8 reserved_at_30[0x8]; 1085 u8 log_max_memic_addr_alignment[0x8]; 1086 1087 u8 memic_bar_start_addr[0x40]; 1088 1089 u8 memic_bar_size[0x20]; 1090 1091 u8 max_memic_size[0x20]; 1092 1093 u8 steering_sw_icm_start_address[0x40]; 1094 1095 u8 reserved_at_100[0x8]; 1096 u8 log_header_modify_sw_icm_size[0x8]; 1097 u8 reserved_at_110[0x2]; 1098 u8 log_sw_icm_alloc_granularity[0x6]; 1099 u8 log_steering_sw_icm_size[0x8]; 1100 1101 u8 reserved_at_120[0x18]; 1102 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1103 1104 u8 header_modify_sw_icm_start_address[0x40]; 1105 1106 u8 reserved_at_180[0x40]; 1107 1108 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1109 1110 u8 memic_operations[0x20]; 1111 1112 u8 reserved_at_220[0x5e0]; 1113 }; 1114 1115 struct mlx5_ifc_device_event_cap_bits { 1116 u8 user_affiliated_events[4][0x40]; 1117 1118 u8 user_unaffiliated_events[4][0x40]; 1119 }; 1120 1121 struct mlx5_ifc_virtio_emulation_cap_bits { 1122 u8 desc_tunnel_offload_type[0x1]; 1123 u8 eth_frame_offload_type[0x1]; 1124 u8 virtio_version_1_0[0x1]; 1125 u8 device_features_bits_mask[0xd]; 1126 u8 event_mode[0x8]; 1127 u8 virtio_queue_type[0x8]; 1128 1129 u8 max_tunnel_desc[0x10]; 1130 u8 reserved_at_30[0x3]; 1131 u8 log_doorbell_stride[0x5]; 1132 u8 reserved_at_38[0x3]; 1133 u8 log_doorbell_bar_size[0x5]; 1134 1135 u8 doorbell_bar_offset[0x40]; 1136 1137 u8 max_emulated_devices[0x8]; 1138 u8 max_num_virtio_queues[0x18]; 1139 1140 u8 reserved_at_a0[0x60]; 1141 1142 u8 umem_1_buffer_param_a[0x20]; 1143 1144 u8 umem_1_buffer_param_b[0x20]; 1145 1146 u8 umem_2_buffer_param_a[0x20]; 1147 1148 u8 umem_2_buffer_param_b[0x20]; 1149 1150 u8 umem_3_buffer_param_a[0x20]; 1151 1152 u8 umem_3_buffer_param_b[0x20]; 1153 1154 u8 reserved_at_1c0[0x640]; 1155 }; 1156 1157 enum { 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1164 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1165 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1166 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1167 }; 1168 1169 enum { 1170 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1171 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1172 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1173 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1174 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1175 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1176 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1177 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1178 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1179 }; 1180 1181 struct mlx5_ifc_atomic_caps_bits { 1182 u8 reserved_at_0[0x40]; 1183 1184 u8 atomic_req_8B_endianness_mode[0x2]; 1185 u8 reserved_at_42[0x4]; 1186 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1187 1188 u8 reserved_at_47[0x19]; 1189 1190 u8 reserved_at_60[0x20]; 1191 1192 u8 reserved_at_80[0x10]; 1193 u8 atomic_operations[0x10]; 1194 1195 u8 reserved_at_a0[0x10]; 1196 u8 atomic_size_qp[0x10]; 1197 1198 u8 reserved_at_c0[0x10]; 1199 u8 atomic_size_dc[0x10]; 1200 1201 u8 reserved_at_e0[0x720]; 1202 }; 1203 1204 struct mlx5_ifc_odp_cap_bits { 1205 u8 reserved_at_0[0x40]; 1206 1207 u8 sig[0x1]; 1208 u8 reserved_at_41[0x1f]; 1209 1210 u8 reserved_at_60[0x20]; 1211 1212 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1213 1214 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1215 1216 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1217 1218 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1219 1220 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1221 1222 u8 reserved_at_120[0x6E0]; 1223 }; 1224 1225 struct mlx5_ifc_calc_op { 1226 u8 reserved_at_0[0x10]; 1227 u8 reserved_at_10[0x9]; 1228 u8 op_swap_endianness[0x1]; 1229 u8 op_min[0x1]; 1230 u8 op_xor[0x1]; 1231 u8 op_or[0x1]; 1232 u8 op_and[0x1]; 1233 u8 op_max[0x1]; 1234 u8 op_add[0x1]; 1235 }; 1236 1237 struct mlx5_ifc_vector_calc_cap_bits { 1238 u8 calc_matrix[0x1]; 1239 u8 reserved_at_1[0x1f]; 1240 u8 reserved_at_20[0x8]; 1241 u8 max_vec_count[0x8]; 1242 u8 reserved_at_30[0xd]; 1243 u8 max_chunk_size[0x3]; 1244 struct mlx5_ifc_calc_op calc0; 1245 struct mlx5_ifc_calc_op calc1; 1246 struct mlx5_ifc_calc_op calc2; 1247 struct mlx5_ifc_calc_op calc3; 1248 1249 u8 reserved_at_c0[0x720]; 1250 }; 1251 1252 struct mlx5_ifc_tls_cap_bits { 1253 u8 tls_1_2_aes_gcm_128[0x1]; 1254 u8 tls_1_3_aes_gcm_128[0x1]; 1255 u8 tls_1_2_aes_gcm_256[0x1]; 1256 u8 tls_1_3_aes_gcm_256[0x1]; 1257 u8 reserved_at_4[0x1c]; 1258 1259 u8 reserved_at_20[0x7e0]; 1260 }; 1261 1262 struct mlx5_ifc_ipsec_cap_bits { 1263 u8 ipsec_full_offload[0x1]; 1264 u8 ipsec_crypto_offload[0x1]; 1265 u8 ipsec_esn[0x1]; 1266 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1267 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1268 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1269 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1270 u8 reserved_at_7[0x4]; 1271 u8 log_max_ipsec_offload[0x5]; 1272 u8 reserved_at_10[0x10]; 1273 1274 u8 min_log_ipsec_full_replay_window[0x8]; 1275 u8 max_log_ipsec_full_replay_window[0x8]; 1276 u8 reserved_at_30[0x7d0]; 1277 }; 1278 1279 enum { 1280 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1281 MLX5_WQ_TYPE_CYCLIC = 0x1, 1282 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1283 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1284 }; 1285 1286 enum { 1287 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1288 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1289 }; 1290 1291 enum { 1292 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1293 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1294 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1295 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1296 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1297 }; 1298 1299 enum { 1300 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1301 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1302 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1303 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1304 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1306 }; 1307 1308 enum { 1309 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1310 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1311 }; 1312 1313 enum { 1314 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1315 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1316 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1317 }; 1318 1319 enum { 1320 MLX5_CAP_PORT_TYPE_IB = 0x0, 1321 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1322 }; 1323 1324 enum { 1325 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1326 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1327 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1328 }; 1329 1330 enum { 1331 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1332 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1333 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1334 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1335 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1336 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1337 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1338 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1339 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1340 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1341 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1342 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1343 }; 1344 1345 enum { 1346 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1347 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1348 }; 1349 1350 #define MLX5_FC_BULK_SIZE_FACTOR 128 1351 1352 enum mlx5_fc_bulk_alloc_bitmask { 1353 MLX5_FC_BULK_128 = (1 << 0), 1354 MLX5_FC_BULK_256 = (1 << 1), 1355 MLX5_FC_BULK_512 = (1 << 2), 1356 MLX5_FC_BULK_1024 = (1 << 3), 1357 MLX5_FC_BULK_2048 = (1 << 4), 1358 MLX5_FC_BULK_4096 = (1 << 5), 1359 MLX5_FC_BULK_8192 = (1 << 6), 1360 MLX5_FC_BULK_16384 = (1 << 7), 1361 }; 1362 1363 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1364 1365 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1366 1367 enum { 1368 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1369 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1370 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1371 }; 1372 1373 struct mlx5_ifc_cmd_hca_cap_bits { 1374 u8 reserved_at_0[0x1f]; 1375 u8 vhca_resource_manager[0x1]; 1376 1377 u8 hca_cap_2[0x1]; 1378 u8 create_lag_when_not_master_up[0x1]; 1379 u8 dtor[0x1]; 1380 u8 event_on_vhca_state_teardown_request[0x1]; 1381 u8 event_on_vhca_state_in_use[0x1]; 1382 u8 event_on_vhca_state_active[0x1]; 1383 u8 event_on_vhca_state_allocated[0x1]; 1384 u8 event_on_vhca_state_invalid[0x1]; 1385 u8 reserved_at_28[0x8]; 1386 u8 vhca_id[0x10]; 1387 1388 u8 reserved_at_40[0x40]; 1389 1390 u8 log_max_srq_sz[0x8]; 1391 u8 log_max_qp_sz[0x8]; 1392 u8 event_cap[0x1]; 1393 u8 reserved_at_91[0x2]; 1394 u8 isolate_vl_tc_new[0x1]; 1395 u8 reserved_at_94[0x4]; 1396 u8 prio_tag_required[0x1]; 1397 u8 reserved_at_99[0x2]; 1398 u8 log_max_qp[0x5]; 1399 1400 u8 reserved_at_a0[0x3]; 1401 u8 ece_support[0x1]; 1402 u8 reserved_at_a4[0x5]; 1403 u8 reg_c_preserve[0x1]; 1404 u8 reserved_at_aa[0x1]; 1405 u8 log_max_srq[0x5]; 1406 u8 reserved_at_b0[0x1]; 1407 u8 uplink_follow[0x1]; 1408 u8 ts_cqe_to_dest_cqn[0x1]; 1409 u8 reserved_at_b3[0x7]; 1410 u8 shampo[0x1]; 1411 u8 reserved_at_bb[0x5]; 1412 1413 u8 max_sgl_for_optimized_performance[0x8]; 1414 u8 log_max_cq_sz[0x8]; 1415 u8 relaxed_ordering_write_umr[0x1]; 1416 u8 relaxed_ordering_read_umr[0x1]; 1417 u8 reserved_at_d2[0x7]; 1418 u8 virtio_net_device_emualtion_manager[0x1]; 1419 u8 virtio_blk_device_emualtion_manager[0x1]; 1420 u8 log_max_cq[0x5]; 1421 1422 u8 log_max_eq_sz[0x8]; 1423 u8 relaxed_ordering_write[0x1]; 1424 u8 relaxed_ordering_read[0x1]; 1425 u8 log_max_mkey[0x6]; 1426 u8 reserved_at_f0[0x8]; 1427 u8 dump_fill_mkey[0x1]; 1428 u8 reserved_at_f9[0x2]; 1429 u8 fast_teardown[0x1]; 1430 u8 log_max_eq[0x4]; 1431 1432 u8 max_indirection[0x8]; 1433 u8 fixed_buffer_size[0x1]; 1434 u8 log_max_mrw_sz[0x7]; 1435 u8 force_teardown[0x1]; 1436 u8 reserved_at_111[0x1]; 1437 u8 log_max_bsf_list_size[0x6]; 1438 u8 umr_extended_translation_offset[0x1]; 1439 u8 null_mkey[0x1]; 1440 u8 log_max_klm_list_size[0x6]; 1441 1442 u8 reserved_at_120[0xa]; 1443 u8 log_max_ra_req_dc[0x6]; 1444 u8 reserved_at_130[0x9]; 1445 u8 vnic_env_cq_overrun[0x1]; 1446 u8 log_max_ra_res_dc[0x6]; 1447 1448 u8 reserved_at_140[0x5]; 1449 u8 release_all_pages[0x1]; 1450 u8 must_not_use[0x1]; 1451 u8 reserved_at_147[0x2]; 1452 u8 roce_accl[0x1]; 1453 u8 log_max_ra_req_qp[0x6]; 1454 u8 reserved_at_150[0xa]; 1455 u8 log_max_ra_res_qp[0x6]; 1456 1457 u8 end_pad[0x1]; 1458 u8 cc_query_allowed[0x1]; 1459 u8 cc_modify_allowed[0x1]; 1460 u8 start_pad[0x1]; 1461 u8 cache_line_128byte[0x1]; 1462 u8 reserved_at_165[0x4]; 1463 u8 rts2rts_qp_counters_set_id[0x1]; 1464 u8 reserved_at_16a[0x2]; 1465 u8 vnic_env_int_rq_oob[0x1]; 1466 u8 sbcam_reg[0x1]; 1467 u8 reserved_at_16e[0x1]; 1468 u8 qcam_reg[0x1]; 1469 u8 gid_table_size[0x10]; 1470 1471 u8 out_of_seq_cnt[0x1]; 1472 u8 vport_counters[0x1]; 1473 u8 retransmission_q_counters[0x1]; 1474 u8 debug[0x1]; 1475 u8 modify_rq_counter_set_id[0x1]; 1476 u8 rq_delay_drop[0x1]; 1477 u8 max_qp_cnt[0xa]; 1478 u8 pkey_table_size[0x10]; 1479 1480 u8 vport_group_manager[0x1]; 1481 u8 vhca_group_manager[0x1]; 1482 u8 ib_virt[0x1]; 1483 u8 eth_virt[0x1]; 1484 u8 vnic_env_queue_counters[0x1]; 1485 u8 ets[0x1]; 1486 u8 nic_flow_table[0x1]; 1487 u8 eswitch_manager[0x1]; 1488 u8 device_memory[0x1]; 1489 u8 mcam_reg[0x1]; 1490 u8 pcam_reg[0x1]; 1491 u8 local_ca_ack_delay[0x5]; 1492 u8 port_module_event[0x1]; 1493 u8 enhanced_error_q_counters[0x1]; 1494 u8 ports_check[0x1]; 1495 u8 reserved_at_1b3[0x1]; 1496 u8 disable_link_up[0x1]; 1497 u8 beacon_led[0x1]; 1498 u8 port_type[0x2]; 1499 u8 num_ports[0x8]; 1500 1501 u8 reserved_at_1c0[0x1]; 1502 u8 pps[0x1]; 1503 u8 pps_modify[0x1]; 1504 u8 log_max_msg[0x5]; 1505 u8 reserved_at_1c8[0x4]; 1506 u8 max_tc[0x4]; 1507 u8 temp_warn_event[0x1]; 1508 u8 dcbx[0x1]; 1509 u8 general_notification_event[0x1]; 1510 u8 reserved_at_1d3[0x2]; 1511 u8 fpga[0x1]; 1512 u8 rol_s[0x1]; 1513 u8 rol_g[0x1]; 1514 u8 reserved_at_1d8[0x1]; 1515 u8 wol_s[0x1]; 1516 u8 wol_g[0x1]; 1517 u8 wol_a[0x1]; 1518 u8 wol_b[0x1]; 1519 u8 wol_m[0x1]; 1520 u8 wol_u[0x1]; 1521 u8 wol_p[0x1]; 1522 1523 u8 stat_rate_support[0x10]; 1524 u8 reserved_at_1f0[0x1]; 1525 u8 pci_sync_for_fw_update_event[0x1]; 1526 u8 reserved_at_1f2[0x6]; 1527 u8 init2_lag_tx_port_affinity[0x1]; 1528 u8 reserved_at_1fa[0x3]; 1529 u8 cqe_version[0x4]; 1530 1531 u8 compact_address_vector[0x1]; 1532 u8 striding_rq[0x1]; 1533 u8 reserved_at_202[0x1]; 1534 u8 ipoib_enhanced_offloads[0x1]; 1535 u8 ipoib_basic_offloads[0x1]; 1536 u8 reserved_at_205[0x1]; 1537 u8 repeated_block_disabled[0x1]; 1538 u8 umr_modify_entity_size_disabled[0x1]; 1539 u8 umr_modify_atomic_disabled[0x1]; 1540 u8 umr_indirect_mkey_disabled[0x1]; 1541 u8 umr_fence[0x2]; 1542 u8 dc_req_scat_data_cqe[0x1]; 1543 u8 reserved_at_20d[0x2]; 1544 u8 drain_sigerr[0x1]; 1545 u8 cmdif_checksum[0x2]; 1546 u8 sigerr_cqe[0x1]; 1547 u8 reserved_at_213[0x1]; 1548 u8 wq_signature[0x1]; 1549 u8 sctr_data_cqe[0x1]; 1550 u8 reserved_at_216[0x1]; 1551 u8 sho[0x1]; 1552 u8 tph[0x1]; 1553 u8 rf[0x1]; 1554 u8 dct[0x1]; 1555 u8 qos[0x1]; 1556 u8 eth_net_offloads[0x1]; 1557 u8 roce[0x1]; 1558 u8 atomic[0x1]; 1559 u8 reserved_at_21f[0x1]; 1560 1561 u8 cq_oi[0x1]; 1562 u8 cq_resize[0x1]; 1563 u8 cq_moderation[0x1]; 1564 u8 reserved_at_223[0x3]; 1565 u8 cq_eq_remap[0x1]; 1566 u8 pg[0x1]; 1567 u8 block_lb_mc[0x1]; 1568 u8 reserved_at_229[0x1]; 1569 u8 scqe_break_moderation[0x1]; 1570 u8 cq_period_start_from_cqe[0x1]; 1571 u8 cd[0x1]; 1572 u8 reserved_at_22d[0x1]; 1573 u8 apm[0x1]; 1574 u8 vector_calc[0x1]; 1575 u8 umr_ptr_rlky[0x1]; 1576 u8 imaicl[0x1]; 1577 u8 qp_packet_based[0x1]; 1578 u8 reserved_at_233[0x3]; 1579 u8 qkv[0x1]; 1580 u8 pkv[0x1]; 1581 u8 set_deth_sqpn[0x1]; 1582 u8 reserved_at_239[0x3]; 1583 u8 xrc[0x1]; 1584 u8 ud[0x1]; 1585 u8 uc[0x1]; 1586 u8 rc[0x1]; 1587 1588 u8 uar_4k[0x1]; 1589 u8 reserved_at_241[0x9]; 1590 u8 uar_sz[0x6]; 1591 u8 port_selection_cap[0x1]; 1592 u8 reserved_at_248[0x1]; 1593 u8 umem_uid_0[0x1]; 1594 u8 reserved_at_250[0x5]; 1595 u8 log_pg_sz[0x8]; 1596 1597 u8 bf[0x1]; 1598 u8 driver_version[0x1]; 1599 u8 pad_tx_eth_packet[0x1]; 1600 u8 reserved_at_263[0x3]; 1601 u8 mkey_by_name[0x1]; 1602 u8 reserved_at_267[0x4]; 1603 1604 u8 log_bf_reg_size[0x5]; 1605 1606 u8 reserved_at_270[0x6]; 1607 u8 lag_dct[0x2]; 1608 u8 lag_tx_port_affinity[0x1]; 1609 u8 lag_native_fdb_selection[0x1]; 1610 u8 reserved_at_27a[0x1]; 1611 u8 lag_master[0x1]; 1612 u8 num_lag_ports[0x4]; 1613 1614 u8 reserved_at_280[0x10]; 1615 u8 max_wqe_sz_sq[0x10]; 1616 1617 u8 reserved_at_2a0[0x10]; 1618 u8 max_wqe_sz_rq[0x10]; 1619 1620 u8 max_flow_counter_31_16[0x10]; 1621 u8 max_wqe_sz_sq_dc[0x10]; 1622 1623 u8 reserved_at_2e0[0x7]; 1624 u8 max_qp_mcg[0x19]; 1625 1626 u8 reserved_at_300[0x10]; 1627 u8 flow_counter_bulk_alloc[0x8]; 1628 u8 log_max_mcg[0x8]; 1629 1630 u8 reserved_at_320[0x3]; 1631 u8 log_max_transport_domain[0x5]; 1632 u8 reserved_at_328[0x3]; 1633 u8 log_max_pd[0x5]; 1634 u8 reserved_at_330[0xb]; 1635 u8 log_max_xrcd[0x5]; 1636 1637 u8 nic_receive_steering_discard[0x1]; 1638 u8 receive_discard_vport_down[0x1]; 1639 u8 transmit_discard_vport_down[0x1]; 1640 u8 eq_overrun_count[0x1]; 1641 u8 reserved_at_344[0x1]; 1642 u8 invalid_command_count[0x1]; 1643 u8 quota_exceeded_count[0x1]; 1644 u8 reserved_at_347[0x1]; 1645 u8 log_max_flow_counter_bulk[0x8]; 1646 u8 max_flow_counter_15_0[0x10]; 1647 1648 1649 u8 reserved_at_360[0x3]; 1650 u8 log_max_rq[0x5]; 1651 u8 reserved_at_368[0x3]; 1652 u8 log_max_sq[0x5]; 1653 u8 reserved_at_370[0x3]; 1654 u8 log_max_tir[0x5]; 1655 u8 reserved_at_378[0x3]; 1656 u8 log_max_tis[0x5]; 1657 1658 u8 basic_cyclic_rcv_wqe[0x1]; 1659 u8 reserved_at_381[0x2]; 1660 u8 log_max_rmp[0x5]; 1661 u8 reserved_at_388[0x3]; 1662 u8 log_max_rqt[0x5]; 1663 u8 reserved_at_390[0x3]; 1664 u8 log_max_rqt_size[0x5]; 1665 u8 reserved_at_398[0x3]; 1666 u8 log_max_tis_per_sq[0x5]; 1667 1668 u8 ext_stride_num_range[0x1]; 1669 u8 roce_rw_supported[0x1]; 1670 u8 log_max_current_uc_list_wr_supported[0x1]; 1671 u8 log_max_stride_sz_rq[0x5]; 1672 u8 reserved_at_3a8[0x3]; 1673 u8 log_min_stride_sz_rq[0x5]; 1674 u8 reserved_at_3b0[0x3]; 1675 u8 log_max_stride_sz_sq[0x5]; 1676 u8 reserved_at_3b8[0x3]; 1677 u8 log_min_stride_sz_sq[0x5]; 1678 1679 u8 hairpin[0x1]; 1680 u8 reserved_at_3c1[0x2]; 1681 u8 log_max_hairpin_queues[0x5]; 1682 u8 reserved_at_3c8[0x3]; 1683 u8 log_max_hairpin_wq_data_sz[0x5]; 1684 u8 reserved_at_3d0[0x3]; 1685 u8 log_max_hairpin_num_packets[0x5]; 1686 u8 reserved_at_3d8[0x3]; 1687 u8 log_max_wq_sz[0x5]; 1688 1689 u8 nic_vport_change_event[0x1]; 1690 u8 disable_local_lb_uc[0x1]; 1691 u8 disable_local_lb_mc[0x1]; 1692 u8 log_min_hairpin_wq_data_sz[0x5]; 1693 u8 reserved_at_3e8[0x2]; 1694 u8 vhca_state[0x1]; 1695 u8 log_max_vlan_list[0x5]; 1696 u8 reserved_at_3f0[0x3]; 1697 u8 log_max_current_mc_list[0x5]; 1698 u8 reserved_at_3f8[0x3]; 1699 u8 log_max_current_uc_list[0x5]; 1700 1701 u8 general_obj_types[0x40]; 1702 1703 u8 sq_ts_format[0x2]; 1704 u8 rq_ts_format[0x2]; 1705 u8 steering_format_version[0x4]; 1706 u8 create_qp_start_hint[0x18]; 1707 1708 u8 reserved_at_460[0x3]; 1709 u8 log_max_uctx[0x5]; 1710 u8 reserved_at_468[0x2]; 1711 u8 ipsec_offload[0x1]; 1712 u8 log_max_umem[0x5]; 1713 u8 max_num_eqs[0x10]; 1714 1715 u8 reserved_at_480[0x1]; 1716 u8 tls_tx[0x1]; 1717 u8 tls_rx[0x1]; 1718 u8 log_max_l2_table[0x5]; 1719 u8 reserved_at_488[0x8]; 1720 u8 log_uar_page_sz[0x10]; 1721 1722 u8 reserved_at_4a0[0x20]; 1723 u8 device_frequency_mhz[0x20]; 1724 u8 device_frequency_khz[0x20]; 1725 1726 u8 reserved_at_500[0x20]; 1727 u8 num_of_uars_per_page[0x20]; 1728 1729 u8 flex_parser_protocols[0x20]; 1730 1731 u8 max_geneve_tlv_options[0x8]; 1732 u8 reserved_at_568[0x3]; 1733 u8 max_geneve_tlv_option_data_len[0x5]; 1734 u8 reserved_at_570[0x10]; 1735 1736 u8 reserved_at_580[0xb]; 1737 u8 log_max_dci_stream_channels[0x5]; 1738 u8 reserved_at_590[0x3]; 1739 u8 log_max_dci_errored_streams[0x5]; 1740 u8 reserved_at_598[0x8]; 1741 1742 u8 reserved_at_5a0[0x10]; 1743 u8 enhanced_cqe_compression[0x1]; 1744 u8 reserved_at_5b1[0x2]; 1745 u8 log_max_dek[0x5]; 1746 u8 reserved_at_5b8[0x4]; 1747 u8 mini_cqe_resp_stride_index[0x1]; 1748 u8 cqe_128_always[0x1]; 1749 u8 cqe_compression_128[0x1]; 1750 u8 cqe_compression[0x1]; 1751 1752 u8 cqe_compression_timeout[0x10]; 1753 u8 cqe_compression_max_num[0x10]; 1754 1755 u8 reserved_at_5e0[0x8]; 1756 u8 flex_parser_id_gtpu_dw_0[0x4]; 1757 u8 reserved_at_5ec[0x4]; 1758 u8 tag_matching[0x1]; 1759 u8 rndv_offload_rc[0x1]; 1760 u8 rndv_offload_dc[0x1]; 1761 u8 log_tag_matching_list_sz[0x5]; 1762 u8 reserved_at_5f8[0x3]; 1763 u8 log_max_xrq[0x5]; 1764 1765 u8 affiliate_nic_vport_criteria[0x8]; 1766 u8 native_port_num[0x8]; 1767 u8 num_vhca_ports[0x8]; 1768 u8 flex_parser_id_gtpu_teid[0x4]; 1769 u8 reserved_at_61c[0x2]; 1770 u8 sw_owner_id[0x1]; 1771 u8 reserved_at_61f[0x1]; 1772 1773 u8 max_num_of_monitor_counters[0x10]; 1774 u8 num_ppcnt_monitor_counters[0x10]; 1775 1776 u8 max_num_sf[0x10]; 1777 u8 num_q_monitor_counters[0x10]; 1778 1779 u8 reserved_at_660[0x20]; 1780 1781 u8 sf[0x1]; 1782 u8 sf_set_partition[0x1]; 1783 u8 reserved_at_682[0x1]; 1784 u8 log_max_sf[0x5]; 1785 u8 apu[0x1]; 1786 u8 reserved_at_689[0x4]; 1787 u8 migration[0x1]; 1788 u8 reserved_at_68e[0x2]; 1789 u8 log_min_sf_size[0x8]; 1790 u8 max_num_sf_partitions[0x8]; 1791 1792 u8 uctx_cap[0x20]; 1793 1794 u8 reserved_at_6c0[0x4]; 1795 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1796 u8 flex_parser_id_icmp_dw1[0x4]; 1797 u8 flex_parser_id_icmp_dw0[0x4]; 1798 u8 flex_parser_id_icmpv6_dw1[0x4]; 1799 u8 flex_parser_id_icmpv6_dw0[0x4]; 1800 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1801 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1802 1803 u8 max_num_match_definer[0x10]; 1804 u8 sf_base_id[0x10]; 1805 1806 u8 flex_parser_id_gtpu_dw_2[0x4]; 1807 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1808 u8 num_total_dynamic_vf_msix[0x18]; 1809 u8 reserved_at_720[0x14]; 1810 u8 dynamic_msix_table_size[0xc]; 1811 u8 reserved_at_740[0xc]; 1812 u8 min_dynamic_vf_msix_table_size[0x4]; 1813 u8 reserved_at_750[0x4]; 1814 u8 max_dynamic_vf_msix_table_size[0xc]; 1815 1816 u8 reserved_at_760[0x20]; 1817 u8 vhca_tunnel_commands[0x40]; 1818 u8 match_definer_format_supported[0x40]; 1819 }; 1820 1821 struct mlx5_ifc_cmd_hca_cap_2_bits { 1822 u8 reserved_at_0[0xa0]; 1823 1824 u8 max_reformat_insert_size[0x8]; 1825 u8 max_reformat_insert_offset[0x8]; 1826 u8 max_reformat_remove_size[0x8]; 1827 u8 max_reformat_remove_offset[0x8]; 1828 1829 u8 reserved_at_c0[0x160]; 1830 1831 u8 reserved_at_220[0x1]; 1832 u8 sw_vhca_id_valid[0x1]; 1833 u8 sw_vhca_id[0xe]; 1834 u8 reserved_at_230[0x10]; 1835 1836 u8 reserved_at_240[0xb]; 1837 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1838 u8 reserved_at_250[0x10]; 1839 1840 u8 reserved_at_260[0x5a0]; 1841 }; 1842 1843 enum mlx5_ifc_flow_destination_type { 1844 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1845 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1846 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1847 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1848 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1849 }; 1850 1851 enum mlx5_flow_table_miss_action { 1852 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1853 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1854 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1855 }; 1856 1857 struct mlx5_ifc_dest_format_struct_bits { 1858 u8 destination_type[0x8]; 1859 u8 destination_id[0x18]; 1860 1861 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1862 u8 packet_reformat[0x1]; 1863 u8 reserved_at_22[0xe]; 1864 u8 destination_eswitch_owner_vhca_id[0x10]; 1865 }; 1866 1867 struct mlx5_ifc_flow_counter_list_bits { 1868 u8 flow_counter_id[0x20]; 1869 1870 u8 reserved_at_20[0x20]; 1871 }; 1872 1873 struct mlx5_ifc_extended_dest_format_bits { 1874 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1875 1876 u8 packet_reformat_id[0x20]; 1877 1878 u8 reserved_at_60[0x20]; 1879 }; 1880 1881 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1882 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1883 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1884 }; 1885 1886 struct mlx5_ifc_fte_match_param_bits { 1887 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1888 1889 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1890 1891 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1892 1893 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1894 1895 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1896 1897 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1898 1899 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1900 1901 u8 reserved_at_e00[0x200]; 1902 }; 1903 1904 enum { 1905 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1906 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1907 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1908 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1909 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1910 }; 1911 1912 struct mlx5_ifc_rx_hash_field_select_bits { 1913 u8 l3_prot_type[0x1]; 1914 u8 l4_prot_type[0x1]; 1915 u8 selected_fields[0x1e]; 1916 }; 1917 1918 enum { 1919 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1920 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1921 }; 1922 1923 enum { 1924 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1925 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1926 }; 1927 1928 struct mlx5_ifc_wq_bits { 1929 u8 wq_type[0x4]; 1930 u8 wq_signature[0x1]; 1931 u8 end_padding_mode[0x2]; 1932 u8 cd_slave[0x1]; 1933 u8 reserved_at_8[0x18]; 1934 1935 u8 hds_skip_first_sge[0x1]; 1936 u8 log2_hds_buf_size[0x3]; 1937 u8 reserved_at_24[0x7]; 1938 u8 page_offset[0x5]; 1939 u8 lwm[0x10]; 1940 1941 u8 reserved_at_40[0x8]; 1942 u8 pd[0x18]; 1943 1944 u8 reserved_at_60[0x8]; 1945 u8 uar_page[0x18]; 1946 1947 u8 dbr_addr[0x40]; 1948 1949 u8 hw_counter[0x20]; 1950 1951 u8 sw_counter[0x20]; 1952 1953 u8 reserved_at_100[0xc]; 1954 u8 log_wq_stride[0x4]; 1955 u8 reserved_at_110[0x3]; 1956 u8 log_wq_pg_sz[0x5]; 1957 u8 reserved_at_118[0x3]; 1958 u8 log_wq_sz[0x5]; 1959 1960 u8 dbr_umem_valid[0x1]; 1961 u8 wq_umem_valid[0x1]; 1962 u8 reserved_at_122[0x1]; 1963 u8 log_hairpin_num_packets[0x5]; 1964 u8 reserved_at_128[0x3]; 1965 u8 log_hairpin_data_sz[0x5]; 1966 1967 u8 reserved_at_130[0x4]; 1968 u8 log_wqe_num_of_strides[0x4]; 1969 u8 two_byte_shift_en[0x1]; 1970 u8 reserved_at_139[0x4]; 1971 u8 log_wqe_stride_size[0x3]; 1972 1973 u8 reserved_at_140[0x80]; 1974 1975 u8 headers_mkey[0x20]; 1976 1977 u8 shampo_enable[0x1]; 1978 u8 reserved_at_1e1[0x4]; 1979 u8 log_reservation_size[0x3]; 1980 u8 reserved_at_1e8[0x5]; 1981 u8 log_max_num_of_packets_per_reservation[0x3]; 1982 u8 reserved_at_1f0[0x6]; 1983 u8 log_headers_entry_size[0x2]; 1984 u8 reserved_at_1f8[0x4]; 1985 u8 log_headers_buffer_entry_num[0x4]; 1986 1987 u8 reserved_at_200[0x400]; 1988 1989 struct mlx5_ifc_cmd_pas_bits pas[]; 1990 }; 1991 1992 struct mlx5_ifc_rq_num_bits { 1993 u8 reserved_at_0[0x8]; 1994 u8 rq_num[0x18]; 1995 }; 1996 1997 struct mlx5_ifc_mac_address_layout_bits { 1998 u8 reserved_at_0[0x10]; 1999 u8 mac_addr_47_32[0x10]; 2000 2001 u8 mac_addr_31_0[0x20]; 2002 }; 2003 2004 struct mlx5_ifc_vlan_layout_bits { 2005 u8 reserved_at_0[0x14]; 2006 u8 vlan[0x0c]; 2007 2008 u8 reserved_at_20[0x20]; 2009 }; 2010 2011 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2012 u8 reserved_at_0[0xa0]; 2013 2014 u8 min_time_between_cnps[0x20]; 2015 2016 u8 reserved_at_c0[0x12]; 2017 u8 cnp_dscp[0x6]; 2018 u8 reserved_at_d8[0x4]; 2019 u8 cnp_prio_mode[0x1]; 2020 u8 cnp_802p_prio[0x3]; 2021 2022 u8 reserved_at_e0[0x720]; 2023 }; 2024 2025 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2026 u8 reserved_at_0[0x60]; 2027 2028 u8 reserved_at_60[0x4]; 2029 u8 clamp_tgt_rate[0x1]; 2030 u8 reserved_at_65[0x3]; 2031 u8 clamp_tgt_rate_after_time_inc[0x1]; 2032 u8 reserved_at_69[0x17]; 2033 2034 u8 reserved_at_80[0x20]; 2035 2036 u8 rpg_time_reset[0x20]; 2037 2038 u8 rpg_byte_reset[0x20]; 2039 2040 u8 rpg_threshold[0x20]; 2041 2042 u8 rpg_max_rate[0x20]; 2043 2044 u8 rpg_ai_rate[0x20]; 2045 2046 u8 rpg_hai_rate[0x20]; 2047 2048 u8 rpg_gd[0x20]; 2049 2050 u8 rpg_min_dec_fac[0x20]; 2051 2052 u8 rpg_min_rate[0x20]; 2053 2054 u8 reserved_at_1c0[0xe0]; 2055 2056 u8 rate_to_set_on_first_cnp[0x20]; 2057 2058 u8 dce_tcp_g[0x20]; 2059 2060 u8 dce_tcp_rtt[0x20]; 2061 2062 u8 rate_reduce_monitor_period[0x20]; 2063 2064 u8 reserved_at_320[0x20]; 2065 2066 u8 initial_alpha_value[0x20]; 2067 2068 u8 reserved_at_360[0x4a0]; 2069 }; 2070 2071 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2072 u8 reserved_at_0[0x80]; 2073 2074 u8 rppp_max_rps[0x20]; 2075 2076 u8 rpg_time_reset[0x20]; 2077 2078 u8 rpg_byte_reset[0x20]; 2079 2080 u8 rpg_threshold[0x20]; 2081 2082 u8 rpg_max_rate[0x20]; 2083 2084 u8 rpg_ai_rate[0x20]; 2085 2086 u8 rpg_hai_rate[0x20]; 2087 2088 u8 rpg_gd[0x20]; 2089 2090 u8 rpg_min_dec_fac[0x20]; 2091 2092 u8 rpg_min_rate[0x20]; 2093 2094 u8 reserved_at_1c0[0x640]; 2095 }; 2096 2097 enum { 2098 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2099 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2100 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2101 }; 2102 2103 struct mlx5_ifc_resize_field_select_bits { 2104 u8 resize_field_select[0x20]; 2105 }; 2106 2107 struct mlx5_ifc_resource_dump_bits { 2108 u8 more_dump[0x1]; 2109 u8 inline_dump[0x1]; 2110 u8 reserved_at_2[0xa]; 2111 u8 seq_num[0x4]; 2112 u8 segment_type[0x10]; 2113 2114 u8 reserved_at_20[0x10]; 2115 u8 vhca_id[0x10]; 2116 2117 u8 index1[0x20]; 2118 2119 u8 index2[0x20]; 2120 2121 u8 num_of_obj1[0x10]; 2122 u8 num_of_obj2[0x10]; 2123 2124 u8 reserved_at_a0[0x20]; 2125 2126 u8 device_opaque[0x40]; 2127 2128 u8 mkey[0x20]; 2129 2130 u8 size[0x20]; 2131 2132 u8 address[0x40]; 2133 2134 u8 inline_data[52][0x20]; 2135 }; 2136 2137 struct mlx5_ifc_resource_dump_menu_record_bits { 2138 u8 reserved_at_0[0x4]; 2139 u8 num_of_obj2_supports_active[0x1]; 2140 u8 num_of_obj2_supports_all[0x1]; 2141 u8 must_have_num_of_obj2[0x1]; 2142 u8 support_num_of_obj2[0x1]; 2143 u8 num_of_obj1_supports_active[0x1]; 2144 u8 num_of_obj1_supports_all[0x1]; 2145 u8 must_have_num_of_obj1[0x1]; 2146 u8 support_num_of_obj1[0x1]; 2147 u8 must_have_index2[0x1]; 2148 u8 support_index2[0x1]; 2149 u8 must_have_index1[0x1]; 2150 u8 support_index1[0x1]; 2151 u8 segment_type[0x10]; 2152 2153 u8 segment_name[4][0x20]; 2154 2155 u8 index1_name[4][0x20]; 2156 2157 u8 index2_name[4][0x20]; 2158 }; 2159 2160 struct mlx5_ifc_resource_dump_segment_header_bits { 2161 u8 length_dw[0x10]; 2162 u8 segment_type[0x10]; 2163 }; 2164 2165 struct mlx5_ifc_resource_dump_command_segment_bits { 2166 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2167 2168 u8 segment_called[0x10]; 2169 u8 vhca_id[0x10]; 2170 2171 u8 index1[0x20]; 2172 2173 u8 index2[0x20]; 2174 2175 u8 num_of_obj1[0x10]; 2176 u8 num_of_obj2[0x10]; 2177 }; 2178 2179 struct mlx5_ifc_resource_dump_error_segment_bits { 2180 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2181 2182 u8 reserved_at_20[0x10]; 2183 u8 syndrome_id[0x10]; 2184 2185 u8 reserved_at_40[0x40]; 2186 2187 u8 error[8][0x20]; 2188 }; 2189 2190 struct mlx5_ifc_resource_dump_info_segment_bits { 2191 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2192 2193 u8 reserved_at_20[0x18]; 2194 u8 dump_version[0x8]; 2195 2196 u8 hw_version[0x20]; 2197 2198 u8 fw_version[0x20]; 2199 }; 2200 2201 struct mlx5_ifc_resource_dump_menu_segment_bits { 2202 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2203 2204 u8 reserved_at_20[0x10]; 2205 u8 num_of_records[0x10]; 2206 2207 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2208 }; 2209 2210 struct mlx5_ifc_resource_dump_resource_segment_bits { 2211 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2212 2213 u8 reserved_at_20[0x20]; 2214 2215 u8 index1[0x20]; 2216 2217 u8 index2[0x20]; 2218 2219 u8 payload[][0x20]; 2220 }; 2221 2222 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2223 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2224 }; 2225 2226 struct mlx5_ifc_menu_resource_dump_response_bits { 2227 struct mlx5_ifc_resource_dump_info_segment_bits info; 2228 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2229 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2230 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2231 }; 2232 2233 enum { 2234 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2235 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2236 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2237 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2238 }; 2239 2240 struct mlx5_ifc_modify_field_select_bits { 2241 u8 modify_field_select[0x20]; 2242 }; 2243 2244 struct mlx5_ifc_field_select_r_roce_np_bits { 2245 u8 field_select_r_roce_np[0x20]; 2246 }; 2247 2248 struct mlx5_ifc_field_select_r_roce_rp_bits { 2249 u8 field_select_r_roce_rp[0x20]; 2250 }; 2251 2252 enum { 2253 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2254 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2255 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2256 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2257 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2258 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2263 }; 2264 2265 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2266 u8 field_select_8021qaurp[0x20]; 2267 }; 2268 2269 struct mlx5_ifc_phys_layer_cntrs_bits { 2270 u8 time_since_last_clear_high[0x20]; 2271 2272 u8 time_since_last_clear_low[0x20]; 2273 2274 u8 symbol_errors_high[0x20]; 2275 2276 u8 symbol_errors_low[0x20]; 2277 2278 u8 sync_headers_errors_high[0x20]; 2279 2280 u8 sync_headers_errors_low[0x20]; 2281 2282 u8 edpl_bip_errors_lane0_high[0x20]; 2283 2284 u8 edpl_bip_errors_lane0_low[0x20]; 2285 2286 u8 edpl_bip_errors_lane1_high[0x20]; 2287 2288 u8 edpl_bip_errors_lane1_low[0x20]; 2289 2290 u8 edpl_bip_errors_lane2_high[0x20]; 2291 2292 u8 edpl_bip_errors_lane2_low[0x20]; 2293 2294 u8 edpl_bip_errors_lane3_high[0x20]; 2295 2296 u8 edpl_bip_errors_lane3_low[0x20]; 2297 2298 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2299 2300 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2301 2302 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2303 2304 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2305 2306 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2307 2308 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2309 2310 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2311 2312 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2313 2314 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2315 2316 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2317 2318 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2319 2320 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2321 2322 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2323 2324 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2325 2326 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2327 2328 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2329 2330 u8 rs_fec_corrected_blocks_high[0x20]; 2331 2332 u8 rs_fec_corrected_blocks_low[0x20]; 2333 2334 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2335 2336 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2337 2338 u8 rs_fec_no_errors_blocks_high[0x20]; 2339 2340 u8 rs_fec_no_errors_blocks_low[0x20]; 2341 2342 u8 rs_fec_single_error_blocks_high[0x20]; 2343 2344 u8 rs_fec_single_error_blocks_low[0x20]; 2345 2346 u8 rs_fec_corrected_symbols_total_high[0x20]; 2347 2348 u8 rs_fec_corrected_symbols_total_low[0x20]; 2349 2350 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2351 2352 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2353 2354 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2355 2356 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2357 2358 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2359 2360 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2361 2362 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2363 2364 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2365 2366 u8 link_down_events[0x20]; 2367 2368 u8 successful_recovery_events[0x20]; 2369 2370 u8 reserved_at_640[0x180]; 2371 }; 2372 2373 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2374 u8 time_since_last_clear_high[0x20]; 2375 2376 u8 time_since_last_clear_low[0x20]; 2377 2378 u8 phy_received_bits_high[0x20]; 2379 2380 u8 phy_received_bits_low[0x20]; 2381 2382 u8 phy_symbol_errors_high[0x20]; 2383 2384 u8 phy_symbol_errors_low[0x20]; 2385 2386 u8 phy_corrected_bits_high[0x20]; 2387 2388 u8 phy_corrected_bits_low[0x20]; 2389 2390 u8 phy_corrected_bits_lane0_high[0x20]; 2391 2392 u8 phy_corrected_bits_lane0_low[0x20]; 2393 2394 u8 phy_corrected_bits_lane1_high[0x20]; 2395 2396 u8 phy_corrected_bits_lane1_low[0x20]; 2397 2398 u8 phy_corrected_bits_lane2_high[0x20]; 2399 2400 u8 phy_corrected_bits_lane2_low[0x20]; 2401 2402 u8 phy_corrected_bits_lane3_high[0x20]; 2403 2404 u8 phy_corrected_bits_lane3_low[0x20]; 2405 2406 u8 reserved_at_200[0x5c0]; 2407 }; 2408 2409 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2410 u8 symbol_error_counter[0x10]; 2411 2412 u8 link_error_recovery_counter[0x8]; 2413 2414 u8 link_downed_counter[0x8]; 2415 2416 u8 port_rcv_errors[0x10]; 2417 2418 u8 port_rcv_remote_physical_errors[0x10]; 2419 2420 u8 port_rcv_switch_relay_errors[0x10]; 2421 2422 u8 port_xmit_discards[0x10]; 2423 2424 u8 port_xmit_constraint_errors[0x8]; 2425 2426 u8 port_rcv_constraint_errors[0x8]; 2427 2428 u8 reserved_at_70[0x8]; 2429 2430 u8 link_overrun_errors[0x8]; 2431 2432 u8 reserved_at_80[0x10]; 2433 2434 u8 vl_15_dropped[0x10]; 2435 2436 u8 reserved_at_a0[0x80]; 2437 2438 u8 port_xmit_wait[0x20]; 2439 }; 2440 2441 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2442 u8 transmit_queue_high[0x20]; 2443 2444 u8 transmit_queue_low[0x20]; 2445 2446 u8 no_buffer_discard_uc_high[0x20]; 2447 2448 u8 no_buffer_discard_uc_low[0x20]; 2449 2450 u8 reserved_at_80[0x740]; 2451 }; 2452 2453 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2454 u8 wred_discard_high[0x20]; 2455 2456 u8 wred_discard_low[0x20]; 2457 2458 u8 ecn_marked_tc_high[0x20]; 2459 2460 u8 ecn_marked_tc_low[0x20]; 2461 2462 u8 reserved_at_80[0x740]; 2463 }; 2464 2465 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2466 u8 rx_octets_high[0x20]; 2467 2468 u8 rx_octets_low[0x20]; 2469 2470 u8 reserved_at_40[0xc0]; 2471 2472 u8 rx_frames_high[0x20]; 2473 2474 u8 rx_frames_low[0x20]; 2475 2476 u8 tx_octets_high[0x20]; 2477 2478 u8 tx_octets_low[0x20]; 2479 2480 u8 reserved_at_180[0xc0]; 2481 2482 u8 tx_frames_high[0x20]; 2483 2484 u8 tx_frames_low[0x20]; 2485 2486 u8 rx_pause_high[0x20]; 2487 2488 u8 rx_pause_low[0x20]; 2489 2490 u8 rx_pause_duration_high[0x20]; 2491 2492 u8 rx_pause_duration_low[0x20]; 2493 2494 u8 tx_pause_high[0x20]; 2495 2496 u8 tx_pause_low[0x20]; 2497 2498 u8 tx_pause_duration_high[0x20]; 2499 2500 u8 tx_pause_duration_low[0x20]; 2501 2502 u8 rx_pause_transition_high[0x20]; 2503 2504 u8 rx_pause_transition_low[0x20]; 2505 2506 u8 rx_discards_high[0x20]; 2507 2508 u8 rx_discards_low[0x20]; 2509 2510 u8 device_stall_minor_watermark_cnt_high[0x20]; 2511 2512 u8 device_stall_minor_watermark_cnt_low[0x20]; 2513 2514 u8 device_stall_critical_watermark_cnt_high[0x20]; 2515 2516 u8 device_stall_critical_watermark_cnt_low[0x20]; 2517 2518 u8 reserved_at_480[0x340]; 2519 }; 2520 2521 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2522 u8 port_transmit_wait_high[0x20]; 2523 2524 u8 port_transmit_wait_low[0x20]; 2525 2526 u8 reserved_at_40[0x100]; 2527 2528 u8 rx_buffer_almost_full_high[0x20]; 2529 2530 u8 rx_buffer_almost_full_low[0x20]; 2531 2532 u8 rx_buffer_full_high[0x20]; 2533 2534 u8 rx_buffer_full_low[0x20]; 2535 2536 u8 rx_icrc_encapsulated_high[0x20]; 2537 2538 u8 rx_icrc_encapsulated_low[0x20]; 2539 2540 u8 reserved_at_200[0x5c0]; 2541 }; 2542 2543 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2544 u8 dot3stats_alignment_errors_high[0x20]; 2545 2546 u8 dot3stats_alignment_errors_low[0x20]; 2547 2548 u8 dot3stats_fcs_errors_high[0x20]; 2549 2550 u8 dot3stats_fcs_errors_low[0x20]; 2551 2552 u8 dot3stats_single_collision_frames_high[0x20]; 2553 2554 u8 dot3stats_single_collision_frames_low[0x20]; 2555 2556 u8 dot3stats_multiple_collision_frames_high[0x20]; 2557 2558 u8 dot3stats_multiple_collision_frames_low[0x20]; 2559 2560 u8 dot3stats_sqe_test_errors_high[0x20]; 2561 2562 u8 dot3stats_sqe_test_errors_low[0x20]; 2563 2564 u8 dot3stats_deferred_transmissions_high[0x20]; 2565 2566 u8 dot3stats_deferred_transmissions_low[0x20]; 2567 2568 u8 dot3stats_late_collisions_high[0x20]; 2569 2570 u8 dot3stats_late_collisions_low[0x20]; 2571 2572 u8 dot3stats_excessive_collisions_high[0x20]; 2573 2574 u8 dot3stats_excessive_collisions_low[0x20]; 2575 2576 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2577 2578 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2579 2580 u8 dot3stats_carrier_sense_errors_high[0x20]; 2581 2582 u8 dot3stats_carrier_sense_errors_low[0x20]; 2583 2584 u8 dot3stats_frame_too_longs_high[0x20]; 2585 2586 u8 dot3stats_frame_too_longs_low[0x20]; 2587 2588 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2589 2590 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2591 2592 u8 dot3stats_symbol_errors_high[0x20]; 2593 2594 u8 dot3stats_symbol_errors_low[0x20]; 2595 2596 u8 dot3control_in_unknown_opcodes_high[0x20]; 2597 2598 u8 dot3control_in_unknown_opcodes_low[0x20]; 2599 2600 u8 dot3in_pause_frames_high[0x20]; 2601 2602 u8 dot3in_pause_frames_low[0x20]; 2603 2604 u8 dot3out_pause_frames_high[0x20]; 2605 2606 u8 dot3out_pause_frames_low[0x20]; 2607 2608 u8 reserved_at_400[0x3c0]; 2609 }; 2610 2611 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2612 u8 ether_stats_drop_events_high[0x20]; 2613 2614 u8 ether_stats_drop_events_low[0x20]; 2615 2616 u8 ether_stats_octets_high[0x20]; 2617 2618 u8 ether_stats_octets_low[0x20]; 2619 2620 u8 ether_stats_pkts_high[0x20]; 2621 2622 u8 ether_stats_pkts_low[0x20]; 2623 2624 u8 ether_stats_broadcast_pkts_high[0x20]; 2625 2626 u8 ether_stats_broadcast_pkts_low[0x20]; 2627 2628 u8 ether_stats_multicast_pkts_high[0x20]; 2629 2630 u8 ether_stats_multicast_pkts_low[0x20]; 2631 2632 u8 ether_stats_crc_align_errors_high[0x20]; 2633 2634 u8 ether_stats_crc_align_errors_low[0x20]; 2635 2636 u8 ether_stats_undersize_pkts_high[0x20]; 2637 2638 u8 ether_stats_undersize_pkts_low[0x20]; 2639 2640 u8 ether_stats_oversize_pkts_high[0x20]; 2641 2642 u8 ether_stats_oversize_pkts_low[0x20]; 2643 2644 u8 ether_stats_fragments_high[0x20]; 2645 2646 u8 ether_stats_fragments_low[0x20]; 2647 2648 u8 ether_stats_jabbers_high[0x20]; 2649 2650 u8 ether_stats_jabbers_low[0x20]; 2651 2652 u8 ether_stats_collisions_high[0x20]; 2653 2654 u8 ether_stats_collisions_low[0x20]; 2655 2656 u8 ether_stats_pkts64octets_high[0x20]; 2657 2658 u8 ether_stats_pkts64octets_low[0x20]; 2659 2660 u8 ether_stats_pkts65to127octets_high[0x20]; 2661 2662 u8 ether_stats_pkts65to127octets_low[0x20]; 2663 2664 u8 ether_stats_pkts128to255octets_high[0x20]; 2665 2666 u8 ether_stats_pkts128to255octets_low[0x20]; 2667 2668 u8 ether_stats_pkts256to511octets_high[0x20]; 2669 2670 u8 ether_stats_pkts256to511octets_low[0x20]; 2671 2672 u8 ether_stats_pkts512to1023octets_high[0x20]; 2673 2674 u8 ether_stats_pkts512to1023octets_low[0x20]; 2675 2676 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2677 2678 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2679 2680 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2681 2682 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2683 2684 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2685 2686 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2687 2688 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2689 2690 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2691 2692 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2693 2694 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2695 2696 u8 reserved_at_540[0x280]; 2697 }; 2698 2699 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2700 u8 if_in_octets_high[0x20]; 2701 2702 u8 if_in_octets_low[0x20]; 2703 2704 u8 if_in_ucast_pkts_high[0x20]; 2705 2706 u8 if_in_ucast_pkts_low[0x20]; 2707 2708 u8 if_in_discards_high[0x20]; 2709 2710 u8 if_in_discards_low[0x20]; 2711 2712 u8 if_in_errors_high[0x20]; 2713 2714 u8 if_in_errors_low[0x20]; 2715 2716 u8 if_in_unknown_protos_high[0x20]; 2717 2718 u8 if_in_unknown_protos_low[0x20]; 2719 2720 u8 if_out_octets_high[0x20]; 2721 2722 u8 if_out_octets_low[0x20]; 2723 2724 u8 if_out_ucast_pkts_high[0x20]; 2725 2726 u8 if_out_ucast_pkts_low[0x20]; 2727 2728 u8 if_out_discards_high[0x20]; 2729 2730 u8 if_out_discards_low[0x20]; 2731 2732 u8 if_out_errors_high[0x20]; 2733 2734 u8 if_out_errors_low[0x20]; 2735 2736 u8 if_in_multicast_pkts_high[0x20]; 2737 2738 u8 if_in_multicast_pkts_low[0x20]; 2739 2740 u8 if_in_broadcast_pkts_high[0x20]; 2741 2742 u8 if_in_broadcast_pkts_low[0x20]; 2743 2744 u8 if_out_multicast_pkts_high[0x20]; 2745 2746 u8 if_out_multicast_pkts_low[0x20]; 2747 2748 u8 if_out_broadcast_pkts_high[0x20]; 2749 2750 u8 if_out_broadcast_pkts_low[0x20]; 2751 2752 u8 reserved_at_340[0x480]; 2753 }; 2754 2755 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2756 u8 a_frames_transmitted_ok_high[0x20]; 2757 2758 u8 a_frames_transmitted_ok_low[0x20]; 2759 2760 u8 a_frames_received_ok_high[0x20]; 2761 2762 u8 a_frames_received_ok_low[0x20]; 2763 2764 u8 a_frame_check_sequence_errors_high[0x20]; 2765 2766 u8 a_frame_check_sequence_errors_low[0x20]; 2767 2768 u8 a_alignment_errors_high[0x20]; 2769 2770 u8 a_alignment_errors_low[0x20]; 2771 2772 u8 a_octets_transmitted_ok_high[0x20]; 2773 2774 u8 a_octets_transmitted_ok_low[0x20]; 2775 2776 u8 a_octets_received_ok_high[0x20]; 2777 2778 u8 a_octets_received_ok_low[0x20]; 2779 2780 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2781 2782 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2783 2784 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2785 2786 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2787 2788 u8 a_multicast_frames_received_ok_high[0x20]; 2789 2790 u8 a_multicast_frames_received_ok_low[0x20]; 2791 2792 u8 a_broadcast_frames_received_ok_high[0x20]; 2793 2794 u8 a_broadcast_frames_received_ok_low[0x20]; 2795 2796 u8 a_in_range_length_errors_high[0x20]; 2797 2798 u8 a_in_range_length_errors_low[0x20]; 2799 2800 u8 a_out_of_range_length_field_high[0x20]; 2801 2802 u8 a_out_of_range_length_field_low[0x20]; 2803 2804 u8 a_frame_too_long_errors_high[0x20]; 2805 2806 u8 a_frame_too_long_errors_low[0x20]; 2807 2808 u8 a_symbol_error_during_carrier_high[0x20]; 2809 2810 u8 a_symbol_error_during_carrier_low[0x20]; 2811 2812 u8 a_mac_control_frames_transmitted_high[0x20]; 2813 2814 u8 a_mac_control_frames_transmitted_low[0x20]; 2815 2816 u8 a_mac_control_frames_received_high[0x20]; 2817 2818 u8 a_mac_control_frames_received_low[0x20]; 2819 2820 u8 a_unsupported_opcodes_received_high[0x20]; 2821 2822 u8 a_unsupported_opcodes_received_low[0x20]; 2823 2824 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2825 2826 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2827 2828 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2829 2830 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2831 2832 u8 reserved_at_4c0[0x300]; 2833 }; 2834 2835 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2836 u8 life_time_counter_high[0x20]; 2837 2838 u8 life_time_counter_low[0x20]; 2839 2840 u8 rx_errors[0x20]; 2841 2842 u8 tx_errors[0x20]; 2843 2844 u8 l0_to_recovery_eieos[0x20]; 2845 2846 u8 l0_to_recovery_ts[0x20]; 2847 2848 u8 l0_to_recovery_framing[0x20]; 2849 2850 u8 l0_to_recovery_retrain[0x20]; 2851 2852 u8 crc_error_dllp[0x20]; 2853 2854 u8 crc_error_tlp[0x20]; 2855 2856 u8 tx_overflow_buffer_pkt_high[0x20]; 2857 2858 u8 tx_overflow_buffer_pkt_low[0x20]; 2859 2860 u8 outbound_stalled_reads[0x20]; 2861 2862 u8 outbound_stalled_writes[0x20]; 2863 2864 u8 outbound_stalled_reads_events[0x20]; 2865 2866 u8 outbound_stalled_writes_events[0x20]; 2867 2868 u8 reserved_at_200[0x5c0]; 2869 }; 2870 2871 struct mlx5_ifc_cmd_inter_comp_event_bits { 2872 u8 command_completion_vector[0x20]; 2873 2874 u8 reserved_at_20[0xc0]; 2875 }; 2876 2877 struct mlx5_ifc_stall_vl_event_bits { 2878 u8 reserved_at_0[0x18]; 2879 u8 port_num[0x1]; 2880 u8 reserved_at_19[0x3]; 2881 u8 vl[0x4]; 2882 2883 u8 reserved_at_20[0xa0]; 2884 }; 2885 2886 struct mlx5_ifc_db_bf_congestion_event_bits { 2887 u8 event_subtype[0x8]; 2888 u8 reserved_at_8[0x8]; 2889 u8 congestion_level[0x8]; 2890 u8 reserved_at_18[0x8]; 2891 2892 u8 reserved_at_20[0xa0]; 2893 }; 2894 2895 struct mlx5_ifc_gpio_event_bits { 2896 u8 reserved_at_0[0x60]; 2897 2898 u8 gpio_event_hi[0x20]; 2899 2900 u8 gpio_event_lo[0x20]; 2901 2902 u8 reserved_at_a0[0x40]; 2903 }; 2904 2905 struct mlx5_ifc_port_state_change_event_bits { 2906 u8 reserved_at_0[0x40]; 2907 2908 u8 port_num[0x4]; 2909 u8 reserved_at_44[0x1c]; 2910 2911 u8 reserved_at_60[0x80]; 2912 }; 2913 2914 struct mlx5_ifc_dropped_packet_logged_bits { 2915 u8 reserved_at_0[0xe0]; 2916 }; 2917 2918 struct mlx5_ifc_default_timeout_bits { 2919 u8 to_multiplier[0x3]; 2920 u8 reserved_at_3[0x9]; 2921 u8 to_value[0x14]; 2922 }; 2923 2924 struct mlx5_ifc_dtor_reg_bits { 2925 u8 reserved_at_0[0x20]; 2926 2927 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2928 2929 u8 reserved_at_40[0x60]; 2930 2931 struct mlx5_ifc_default_timeout_bits health_poll_to; 2932 2933 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2934 2935 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2936 2937 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2938 2939 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2940 2941 struct mlx5_ifc_default_timeout_bits tear_down_to; 2942 2943 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2944 2945 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2946 2947 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2948 2949 u8 reserved_at_1c0[0x40]; 2950 }; 2951 2952 enum { 2953 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2954 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2955 }; 2956 2957 struct mlx5_ifc_cq_error_bits { 2958 u8 reserved_at_0[0x8]; 2959 u8 cqn[0x18]; 2960 2961 u8 reserved_at_20[0x20]; 2962 2963 u8 reserved_at_40[0x18]; 2964 u8 syndrome[0x8]; 2965 2966 u8 reserved_at_60[0x80]; 2967 }; 2968 2969 struct mlx5_ifc_rdma_page_fault_event_bits { 2970 u8 bytes_committed[0x20]; 2971 2972 u8 r_key[0x20]; 2973 2974 u8 reserved_at_40[0x10]; 2975 u8 packet_len[0x10]; 2976 2977 u8 rdma_op_len[0x20]; 2978 2979 u8 rdma_va[0x40]; 2980 2981 u8 reserved_at_c0[0x5]; 2982 u8 rdma[0x1]; 2983 u8 write[0x1]; 2984 u8 requestor[0x1]; 2985 u8 qp_number[0x18]; 2986 }; 2987 2988 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2989 u8 bytes_committed[0x20]; 2990 2991 u8 reserved_at_20[0x10]; 2992 u8 wqe_index[0x10]; 2993 2994 u8 reserved_at_40[0x10]; 2995 u8 len[0x10]; 2996 2997 u8 reserved_at_60[0x60]; 2998 2999 u8 reserved_at_c0[0x5]; 3000 u8 rdma[0x1]; 3001 u8 write_read[0x1]; 3002 u8 requestor[0x1]; 3003 u8 qpn[0x18]; 3004 }; 3005 3006 struct mlx5_ifc_qp_events_bits { 3007 u8 reserved_at_0[0xa0]; 3008 3009 u8 type[0x8]; 3010 u8 reserved_at_a8[0x18]; 3011 3012 u8 reserved_at_c0[0x8]; 3013 u8 qpn_rqn_sqn[0x18]; 3014 }; 3015 3016 struct mlx5_ifc_dct_events_bits { 3017 u8 reserved_at_0[0xc0]; 3018 3019 u8 reserved_at_c0[0x8]; 3020 u8 dct_number[0x18]; 3021 }; 3022 3023 struct mlx5_ifc_comp_event_bits { 3024 u8 reserved_at_0[0xc0]; 3025 3026 u8 reserved_at_c0[0x8]; 3027 u8 cq_number[0x18]; 3028 }; 3029 3030 enum { 3031 MLX5_QPC_STATE_RST = 0x0, 3032 MLX5_QPC_STATE_INIT = 0x1, 3033 MLX5_QPC_STATE_RTR = 0x2, 3034 MLX5_QPC_STATE_RTS = 0x3, 3035 MLX5_QPC_STATE_SQER = 0x4, 3036 MLX5_QPC_STATE_ERR = 0x6, 3037 MLX5_QPC_STATE_SQD = 0x7, 3038 MLX5_QPC_STATE_SUSPENDED = 0x9, 3039 }; 3040 3041 enum { 3042 MLX5_QPC_ST_RC = 0x0, 3043 MLX5_QPC_ST_UC = 0x1, 3044 MLX5_QPC_ST_UD = 0x2, 3045 MLX5_QPC_ST_XRC = 0x3, 3046 MLX5_QPC_ST_DCI = 0x5, 3047 MLX5_QPC_ST_QP0 = 0x7, 3048 MLX5_QPC_ST_QP1 = 0x8, 3049 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3050 MLX5_QPC_ST_REG_UMR = 0xc, 3051 }; 3052 3053 enum { 3054 MLX5_QPC_PM_STATE_ARMED = 0x0, 3055 MLX5_QPC_PM_STATE_REARM = 0x1, 3056 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3057 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3058 }; 3059 3060 enum { 3061 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3062 }; 3063 3064 enum { 3065 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3066 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3067 }; 3068 3069 enum { 3070 MLX5_QPC_MTU_256_BYTES = 0x1, 3071 MLX5_QPC_MTU_512_BYTES = 0x2, 3072 MLX5_QPC_MTU_1K_BYTES = 0x3, 3073 MLX5_QPC_MTU_2K_BYTES = 0x4, 3074 MLX5_QPC_MTU_4K_BYTES = 0x5, 3075 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3076 }; 3077 3078 enum { 3079 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3080 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3081 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3082 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3083 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3084 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3085 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3086 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3087 }; 3088 3089 enum { 3090 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3091 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3092 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3093 }; 3094 3095 enum { 3096 MLX5_QPC_CS_RES_DISABLE = 0x0, 3097 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3098 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3099 }; 3100 3101 enum { 3102 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3103 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3104 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3105 }; 3106 3107 struct mlx5_ifc_qpc_bits { 3108 u8 state[0x4]; 3109 u8 lag_tx_port_affinity[0x4]; 3110 u8 st[0x8]; 3111 u8 reserved_at_10[0x2]; 3112 u8 isolate_vl_tc[0x1]; 3113 u8 pm_state[0x2]; 3114 u8 reserved_at_15[0x1]; 3115 u8 req_e2e_credit_mode[0x2]; 3116 u8 offload_type[0x4]; 3117 u8 end_padding_mode[0x2]; 3118 u8 reserved_at_1e[0x2]; 3119 3120 u8 wq_signature[0x1]; 3121 u8 block_lb_mc[0x1]; 3122 u8 atomic_like_write_en[0x1]; 3123 u8 latency_sensitive[0x1]; 3124 u8 reserved_at_24[0x1]; 3125 u8 drain_sigerr[0x1]; 3126 u8 reserved_at_26[0x2]; 3127 u8 pd[0x18]; 3128 3129 u8 mtu[0x3]; 3130 u8 log_msg_max[0x5]; 3131 u8 reserved_at_48[0x1]; 3132 u8 log_rq_size[0x4]; 3133 u8 log_rq_stride[0x3]; 3134 u8 no_sq[0x1]; 3135 u8 log_sq_size[0x4]; 3136 u8 reserved_at_55[0x3]; 3137 u8 ts_format[0x2]; 3138 u8 reserved_at_5a[0x1]; 3139 u8 rlky[0x1]; 3140 u8 ulp_stateless_offload_mode[0x4]; 3141 3142 u8 counter_set_id[0x8]; 3143 u8 uar_page[0x18]; 3144 3145 u8 reserved_at_80[0x8]; 3146 u8 user_index[0x18]; 3147 3148 u8 reserved_at_a0[0x3]; 3149 u8 log_page_size[0x5]; 3150 u8 remote_qpn[0x18]; 3151 3152 struct mlx5_ifc_ads_bits primary_address_path; 3153 3154 struct mlx5_ifc_ads_bits secondary_address_path; 3155 3156 u8 log_ack_req_freq[0x4]; 3157 u8 reserved_at_384[0x4]; 3158 u8 log_sra_max[0x3]; 3159 u8 reserved_at_38b[0x2]; 3160 u8 retry_count[0x3]; 3161 u8 rnr_retry[0x3]; 3162 u8 reserved_at_393[0x1]; 3163 u8 fre[0x1]; 3164 u8 cur_rnr_retry[0x3]; 3165 u8 cur_retry_count[0x3]; 3166 u8 reserved_at_39b[0x5]; 3167 3168 u8 reserved_at_3a0[0x20]; 3169 3170 u8 reserved_at_3c0[0x8]; 3171 u8 next_send_psn[0x18]; 3172 3173 u8 reserved_at_3e0[0x3]; 3174 u8 log_num_dci_stream_channels[0x5]; 3175 u8 cqn_snd[0x18]; 3176 3177 u8 reserved_at_400[0x3]; 3178 u8 log_num_dci_errored_streams[0x5]; 3179 u8 deth_sqpn[0x18]; 3180 3181 u8 reserved_at_420[0x20]; 3182 3183 u8 reserved_at_440[0x8]; 3184 u8 last_acked_psn[0x18]; 3185 3186 u8 reserved_at_460[0x8]; 3187 u8 ssn[0x18]; 3188 3189 u8 reserved_at_480[0x8]; 3190 u8 log_rra_max[0x3]; 3191 u8 reserved_at_48b[0x1]; 3192 u8 atomic_mode[0x4]; 3193 u8 rre[0x1]; 3194 u8 rwe[0x1]; 3195 u8 rae[0x1]; 3196 u8 reserved_at_493[0x1]; 3197 u8 page_offset[0x6]; 3198 u8 reserved_at_49a[0x3]; 3199 u8 cd_slave_receive[0x1]; 3200 u8 cd_slave_send[0x1]; 3201 u8 cd_master[0x1]; 3202 3203 u8 reserved_at_4a0[0x3]; 3204 u8 min_rnr_nak[0x5]; 3205 u8 next_rcv_psn[0x18]; 3206 3207 u8 reserved_at_4c0[0x8]; 3208 u8 xrcd[0x18]; 3209 3210 u8 reserved_at_4e0[0x8]; 3211 u8 cqn_rcv[0x18]; 3212 3213 u8 dbr_addr[0x40]; 3214 3215 u8 q_key[0x20]; 3216 3217 u8 reserved_at_560[0x5]; 3218 u8 rq_type[0x3]; 3219 u8 srqn_rmpn_xrqn[0x18]; 3220 3221 u8 reserved_at_580[0x8]; 3222 u8 rmsn[0x18]; 3223 3224 u8 hw_sq_wqebb_counter[0x10]; 3225 u8 sw_sq_wqebb_counter[0x10]; 3226 3227 u8 hw_rq_counter[0x20]; 3228 3229 u8 sw_rq_counter[0x20]; 3230 3231 u8 reserved_at_600[0x20]; 3232 3233 u8 reserved_at_620[0xf]; 3234 u8 cgs[0x1]; 3235 u8 cs_req[0x8]; 3236 u8 cs_res[0x8]; 3237 3238 u8 dc_access_key[0x40]; 3239 3240 u8 reserved_at_680[0x3]; 3241 u8 dbr_umem_valid[0x1]; 3242 3243 u8 reserved_at_684[0xbc]; 3244 }; 3245 3246 struct mlx5_ifc_roce_addr_layout_bits { 3247 u8 source_l3_address[16][0x8]; 3248 3249 u8 reserved_at_80[0x3]; 3250 u8 vlan_valid[0x1]; 3251 u8 vlan_id[0xc]; 3252 u8 source_mac_47_32[0x10]; 3253 3254 u8 source_mac_31_0[0x20]; 3255 3256 u8 reserved_at_c0[0x14]; 3257 u8 roce_l3_type[0x4]; 3258 u8 roce_version[0x8]; 3259 3260 u8 reserved_at_e0[0x20]; 3261 }; 3262 3263 struct mlx5_ifc_shampo_cap_bits { 3264 u8 reserved_at_0[0x3]; 3265 u8 shampo_log_max_reservation_size[0x5]; 3266 u8 reserved_at_8[0x3]; 3267 u8 shampo_log_min_reservation_size[0x5]; 3268 u8 shampo_min_mss_size[0x10]; 3269 3270 u8 reserved_at_20[0x3]; 3271 u8 shampo_max_log_headers_entry_size[0x5]; 3272 u8 reserved_at_28[0x18]; 3273 3274 u8 reserved_at_40[0x7c0]; 3275 }; 3276 3277 union mlx5_ifc_hca_cap_union_bits { 3278 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3279 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3280 struct mlx5_ifc_odp_cap_bits odp_cap; 3281 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3282 struct mlx5_ifc_roce_cap_bits roce_cap; 3283 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3284 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3285 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3286 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3287 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3288 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3289 struct mlx5_ifc_qos_cap_bits qos_cap; 3290 struct mlx5_ifc_debug_cap_bits debug_cap; 3291 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3292 struct mlx5_ifc_tls_cap_bits tls_cap; 3293 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3294 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3295 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3296 u8 reserved_at_0[0x8000]; 3297 }; 3298 3299 enum { 3300 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3301 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3302 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3303 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3304 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3305 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3306 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3307 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3308 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3309 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3310 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3311 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3312 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3313 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3314 }; 3315 3316 enum { 3317 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3318 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3319 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3320 }; 3321 3322 struct mlx5_ifc_vlan_bits { 3323 u8 ethtype[0x10]; 3324 u8 prio[0x3]; 3325 u8 cfi[0x1]; 3326 u8 vid[0xc]; 3327 }; 3328 3329 enum { 3330 MLX5_FLOW_METER_COLOR_RED = 0x0, 3331 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3332 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3333 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3334 }; 3335 3336 enum { 3337 MLX5_EXE_ASO_FLOW_METER = 0x2, 3338 }; 3339 3340 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3341 u8 return_reg_id[0x4]; 3342 u8 aso_type[0x4]; 3343 u8 reserved_at_8[0x14]; 3344 u8 action[0x1]; 3345 u8 init_color[0x2]; 3346 u8 meter_id[0x1]; 3347 }; 3348 3349 union mlx5_ifc_exe_aso_ctrl { 3350 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3351 }; 3352 3353 struct mlx5_ifc_execute_aso_bits { 3354 u8 valid[0x1]; 3355 u8 reserved_at_1[0x7]; 3356 u8 aso_object_id[0x18]; 3357 3358 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3359 }; 3360 3361 struct mlx5_ifc_flow_context_bits { 3362 struct mlx5_ifc_vlan_bits push_vlan; 3363 3364 u8 group_id[0x20]; 3365 3366 u8 reserved_at_40[0x8]; 3367 u8 flow_tag[0x18]; 3368 3369 u8 reserved_at_60[0x10]; 3370 u8 action[0x10]; 3371 3372 u8 extended_destination[0x1]; 3373 u8 reserved_at_81[0x1]; 3374 u8 flow_source[0x2]; 3375 u8 reserved_at_84[0x4]; 3376 u8 destination_list_size[0x18]; 3377 3378 u8 reserved_at_a0[0x8]; 3379 u8 flow_counter_list_size[0x18]; 3380 3381 u8 packet_reformat_id[0x20]; 3382 3383 u8 modify_header_id[0x20]; 3384 3385 struct mlx5_ifc_vlan_bits push_vlan_2; 3386 3387 u8 ipsec_obj_id[0x20]; 3388 u8 reserved_at_140[0xc0]; 3389 3390 struct mlx5_ifc_fte_match_param_bits match_value; 3391 3392 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3393 3394 u8 reserved_at_1300[0x500]; 3395 3396 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3397 }; 3398 3399 enum { 3400 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3401 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3402 }; 3403 3404 struct mlx5_ifc_xrc_srqc_bits { 3405 u8 state[0x4]; 3406 u8 log_xrc_srq_size[0x4]; 3407 u8 reserved_at_8[0x18]; 3408 3409 u8 wq_signature[0x1]; 3410 u8 cont_srq[0x1]; 3411 u8 reserved_at_22[0x1]; 3412 u8 rlky[0x1]; 3413 u8 basic_cyclic_rcv_wqe[0x1]; 3414 u8 log_rq_stride[0x3]; 3415 u8 xrcd[0x18]; 3416 3417 u8 page_offset[0x6]; 3418 u8 reserved_at_46[0x1]; 3419 u8 dbr_umem_valid[0x1]; 3420 u8 cqn[0x18]; 3421 3422 u8 reserved_at_60[0x20]; 3423 3424 u8 user_index_equal_xrc_srqn[0x1]; 3425 u8 reserved_at_81[0x1]; 3426 u8 log_page_size[0x6]; 3427 u8 user_index[0x18]; 3428 3429 u8 reserved_at_a0[0x20]; 3430 3431 u8 reserved_at_c0[0x8]; 3432 u8 pd[0x18]; 3433 3434 u8 lwm[0x10]; 3435 u8 wqe_cnt[0x10]; 3436 3437 u8 reserved_at_100[0x40]; 3438 3439 u8 db_record_addr_h[0x20]; 3440 3441 u8 db_record_addr_l[0x1e]; 3442 u8 reserved_at_17e[0x2]; 3443 3444 u8 reserved_at_180[0x80]; 3445 }; 3446 3447 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3448 u8 counter_error_queues[0x20]; 3449 3450 u8 total_error_queues[0x20]; 3451 3452 u8 send_queue_priority_update_flow[0x20]; 3453 3454 u8 reserved_at_60[0x20]; 3455 3456 u8 nic_receive_steering_discard[0x40]; 3457 3458 u8 receive_discard_vport_down[0x40]; 3459 3460 u8 transmit_discard_vport_down[0x40]; 3461 3462 u8 async_eq_overrun[0x20]; 3463 3464 u8 comp_eq_overrun[0x20]; 3465 3466 u8 reserved_at_180[0x20]; 3467 3468 u8 invalid_command[0x20]; 3469 3470 u8 quota_exceeded_command[0x20]; 3471 3472 u8 internal_rq_out_of_buffer[0x20]; 3473 3474 u8 cq_overrun[0x20]; 3475 3476 u8 reserved_at_220[0xde0]; 3477 }; 3478 3479 struct mlx5_ifc_traffic_counter_bits { 3480 u8 packets[0x40]; 3481 3482 u8 octets[0x40]; 3483 }; 3484 3485 struct mlx5_ifc_tisc_bits { 3486 u8 strict_lag_tx_port_affinity[0x1]; 3487 u8 tls_en[0x1]; 3488 u8 reserved_at_2[0x2]; 3489 u8 lag_tx_port_affinity[0x04]; 3490 3491 u8 reserved_at_8[0x4]; 3492 u8 prio[0x4]; 3493 u8 reserved_at_10[0x10]; 3494 3495 u8 reserved_at_20[0x100]; 3496 3497 u8 reserved_at_120[0x8]; 3498 u8 transport_domain[0x18]; 3499 3500 u8 reserved_at_140[0x8]; 3501 u8 underlay_qpn[0x18]; 3502 3503 u8 reserved_at_160[0x8]; 3504 u8 pd[0x18]; 3505 3506 u8 reserved_at_180[0x380]; 3507 }; 3508 3509 enum { 3510 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3511 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3512 }; 3513 3514 enum { 3515 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3516 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3517 }; 3518 3519 enum { 3520 MLX5_RX_HASH_FN_NONE = 0x0, 3521 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3522 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3523 }; 3524 3525 enum { 3526 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3527 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3528 }; 3529 3530 struct mlx5_ifc_tirc_bits { 3531 u8 reserved_at_0[0x20]; 3532 3533 u8 disp_type[0x4]; 3534 u8 tls_en[0x1]; 3535 u8 reserved_at_25[0x1b]; 3536 3537 u8 reserved_at_40[0x40]; 3538 3539 u8 reserved_at_80[0x4]; 3540 u8 lro_timeout_period_usecs[0x10]; 3541 u8 packet_merge_mask[0x4]; 3542 u8 lro_max_ip_payload_size[0x8]; 3543 3544 u8 reserved_at_a0[0x40]; 3545 3546 u8 reserved_at_e0[0x8]; 3547 u8 inline_rqn[0x18]; 3548 3549 u8 rx_hash_symmetric[0x1]; 3550 u8 reserved_at_101[0x1]; 3551 u8 tunneled_offload_en[0x1]; 3552 u8 reserved_at_103[0x5]; 3553 u8 indirect_table[0x18]; 3554 3555 u8 rx_hash_fn[0x4]; 3556 u8 reserved_at_124[0x2]; 3557 u8 self_lb_block[0x2]; 3558 u8 transport_domain[0x18]; 3559 3560 u8 rx_hash_toeplitz_key[10][0x20]; 3561 3562 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3563 3564 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3565 3566 u8 reserved_at_2c0[0x4c0]; 3567 }; 3568 3569 enum { 3570 MLX5_SRQC_STATE_GOOD = 0x0, 3571 MLX5_SRQC_STATE_ERROR = 0x1, 3572 }; 3573 3574 struct mlx5_ifc_srqc_bits { 3575 u8 state[0x4]; 3576 u8 log_srq_size[0x4]; 3577 u8 reserved_at_8[0x18]; 3578 3579 u8 wq_signature[0x1]; 3580 u8 cont_srq[0x1]; 3581 u8 reserved_at_22[0x1]; 3582 u8 rlky[0x1]; 3583 u8 reserved_at_24[0x1]; 3584 u8 log_rq_stride[0x3]; 3585 u8 xrcd[0x18]; 3586 3587 u8 page_offset[0x6]; 3588 u8 reserved_at_46[0x2]; 3589 u8 cqn[0x18]; 3590 3591 u8 reserved_at_60[0x20]; 3592 3593 u8 reserved_at_80[0x2]; 3594 u8 log_page_size[0x6]; 3595 u8 reserved_at_88[0x18]; 3596 3597 u8 reserved_at_a0[0x20]; 3598 3599 u8 reserved_at_c0[0x8]; 3600 u8 pd[0x18]; 3601 3602 u8 lwm[0x10]; 3603 u8 wqe_cnt[0x10]; 3604 3605 u8 reserved_at_100[0x40]; 3606 3607 u8 dbr_addr[0x40]; 3608 3609 u8 reserved_at_180[0x80]; 3610 }; 3611 3612 enum { 3613 MLX5_SQC_STATE_RST = 0x0, 3614 MLX5_SQC_STATE_RDY = 0x1, 3615 MLX5_SQC_STATE_ERR = 0x3, 3616 }; 3617 3618 struct mlx5_ifc_sqc_bits { 3619 u8 rlky[0x1]; 3620 u8 cd_master[0x1]; 3621 u8 fre[0x1]; 3622 u8 flush_in_error_en[0x1]; 3623 u8 allow_multi_pkt_send_wqe[0x1]; 3624 u8 min_wqe_inline_mode[0x3]; 3625 u8 state[0x4]; 3626 u8 reg_umr[0x1]; 3627 u8 allow_swp[0x1]; 3628 u8 hairpin[0x1]; 3629 u8 reserved_at_f[0xb]; 3630 u8 ts_format[0x2]; 3631 u8 reserved_at_1c[0x4]; 3632 3633 u8 reserved_at_20[0x8]; 3634 u8 user_index[0x18]; 3635 3636 u8 reserved_at_40[0x8]; 3637 u8 cqn[0x18]; 3638 3639 u8 reserved_at_60[0x8]; 3640 u8 hairpin_peer_rq[0x18]; 3641 3642 u8 reserved_at_80[0x10]; 3643 u8 hairpin_peer_vhca[0x10]; 3644 3645 u8 reserved_at_a0[0x20]; 3646 3647 u8 reserved_at_c0[0x8]; 3648 u8 ts_cqe_to_dest_cqn[0x18]; 3649 3650 u8 reserved_at_e0[0x10]; 3651 u8 packet_pacing_rate_limit_index[0x10]; 3652 u8 tis_lst_sz[0x10]; 3653 u8 qos_queue_group_id[0x10]; 3654 3655 u8 reserved_at_120[0x40]; 3656 3657 u8 reserved_at_160[0x8]; 3658 u8 tis_num_0[0x18]; 3659 3660 struct mlx5_ifc_wq_bits wq; 3661 }; 3662 3663 enum { 3664 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3665 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3666 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3667 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3668 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3669 }; 3670 3671 enum { 3672 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3673 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3674 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3675 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3676 }; 3677 3678 struct mlx5_ifc_scheduling_context_bits { 3679 u8 element_type[0x8]; 3680 u8 reserved_at_8[0x18]; 3681 3682 u8 element_attributes[0x20]; 3683 3684 u8 parent_element_id[0x20]; 3685 3686 u8 reserved_at_60[0x40]; 3687 3688 u8 bw_share[0x20]; 3689 3690 u8 max_average_bw[0x20]; 3691 3692 u8 reserved_at_e0[0x120]; 3693 }; 3694 3695 struct mlx5_ifc_rqtc_bits { 3696 u8 reserved_at_0[0xa0]; 3697 3698 u8 reserved_at_a0[0x5]; 3699 u8 list_q_type[0x3]; 3700 u8 reserved_at_a8[0x8]; 3701 u8 rqt_max_size[0x10]; 3702 3703 u8 rq_vhca_id_format[0x1]; 3704 u8 reserved_at_c1[0xf]; 3705 u8 rqt_actual_size[0x10]; 3706 3707 u8 reserved_at_e0[0x6a0]; 3708 3709 struct mlx5_ifc_rq_num_bits rq_num[]; 3710 }; 3711 3712 enum { 3713 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3714 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3715 }; 3716 3717 enum { 3718 MLX5_RQC_STATE_RST = 0x0, 3719 MLX5_RQC_STATE_RDY = 0x1, 3720 MLX5_RQC_STATE_ERR = 0x3, 3721 }; 3722 3723 enum { 3724 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3725 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3726 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3727 }; 3728 3729 enum { 3730 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3731 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3732 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3733 }; 3734 3735 struct mlx5_ifc_rqc_bits { 3736 u8 rlky[0x1]; 3737 u8 delay_drop_en[0x1]; 3738 u8 scatter_fcs[0x1]; 3739 u8 vsd[0x1]; 3740 u8 mem_rq_type[0x4]; 3741 u8 state[0x4]; 3742 u8 reserved_at_c[0x1]; 3743 u8 flush_in_error_en[0x1]; 3744 u8 hairpin[0x1]; 3745 u8 reserved_at_f[0xb]; 3746 u8 ts_format[0x2]; 3747 u8 reserved_at_1c[0x4]; 3748 3749 u8 reserved_at_20[0x8]; 3750 u8 user_index[0x18]; 3751 3752 u8 reserved_at_40[0x8]; 3753 u8 cqn[0x18]; 3754 3755 u8 counter_set_id[0x8]; 3756 u8 reserved_at_68[0x18]; 3757 3758 u8 reserved_at_80[0x8]; 3759 u8 rmpn[0x18]; 3760 3761 u8 reserved_at_a0[0x8]; 3762 u8 hairpin_peer_sq[0x18]; 3763 3764 u8 reserved_at_c0[0x10]; 3765 u8 hairpin_peer_vhca[0x10]; 3766 3767 u8 reserved_at_e0[0x46]; 3768 u8 shampo_no_match_alignment_granularity[0x2]; 3769 u8 reserved_at_128[0x6]; 3770 u8 shampo_match_criteria_type[0x2]; 3771 u8 reservation_timeout[0x10]; 3772 3773 u8 reserved_at_140[0x40]; 3774 3775 struct mlx5_ifc_wq_bits wq; 3776 }; 3777 3778 enum { 3779 MLX5_RMPC_STATE_RDY = 0x1, 3780 MLX5_RMPC_STATE_ERR = 0x3, 3781 }; 3782 3783 struct mlx5_ifc_rmpc_bits { 3784 u8 reserved_at_0[0x8]; 3785 u8 state[0x4]; 3786 u8 reserved_at_c[0x14]; 3787 3788 u8 basic_cyclic_rcv_wqe[0x1]; 3789 u8 reserved_at_21[0x1f]; 3790 3791 u8 reserved_at_40[0x140]; 3792 3793 struct mlx5_ifc_wq_bits wq; 3794 }; 3795 3796 enum { 3797 VHCA_ID_TYPE_HW = 0, 3798 VHCA_ID_TYPE_SW = 1, 3799 }; 3800 3801 struct mlx5_ifc_nic_vport_context_bits { 3802 u8 reserved_at_0[0x5]; 3803 u8 min_wqe_inline_mode[0x3]; 3804 u8 reserved_at_8[0x15]; 3805 u8 disable_mc_local_lb[0x1]; 3806 u8 disable_uc_local_lb[0x1]; 3807 u8 roce_en[0x1]; 3808 3809 u8 arm_change_event[0x1]; 3810 u8 reserved_at_21[0x1a]; 3811 u8 event_on_mtu[0x1]; 3812 u8 event_on_promisc_change[0x1]; 3813 u8 event_on_vlan_change[0x1]; 3814 u8 event_on_mc_address_change[0x1]; 3815 u8 event_on_uc_address_change[0x1]; 3816 3817 u8 vhca_id_type[0x1]; 3818 u8 reserved_at_41[0xb]; 3819 u8 affiliation_criteria[0x4]; 3820 u8 affiliated_vhca_id[0x10]; 3821 3822 u8 reserved_at_60[0xd0]; 3823 3824 u8 mtu[0x10]; 3825 3826 u8 system_image_guid[0x40]; 3827 u8 port_guid[0x40]; 3828 u8 node_guid[0x40]; 3829 3830 u8 reserved_at_200[0x140]; 3831 u8 qkey_violation_counter[0x10]; 3832 u8 reserved_at_350[0x430]; 3833 3834 u8 promisc_uc[0x1]; 3835 u8 promisc_mc[0x1]; 3836 u8 promisc_all[0x1]; 3837 u8 reserved_at_783[0x2]; 3838 u8 allowed_list_type[0x3]; 3839 u8 reserved_at_788[0xc]; 3840 u8 allowed_list_size[0xc]; 3841 3842 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3843 3844 u8 reserved_at_7e0[0x20]; 3845 3846 u8 current_uc_mac_address[][0x40]; 3847 }; 3848 3849 enum { 3850 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3851 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3852 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3853 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3854 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3855 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3856 }; 3857 3858 struct mlx5_ifc_mkc_bits { 3859 u8 reserved_at_0[0x1]; 3860 u8 free[0x1]; 3861 u8 reserved_at_2[0x1]; 3862 u8 access_mode_4_2[0x3]; 3863 u8 reserved_at_6[0x7]; 3864 u8 relaxed_ordering_write[0x1]; 3865 u8 reserved_at_e[0x1]; 3866 u8 small_fence_on_rdma_read_response[0x1]; 3867 u8 umr_en[0x1]; 3868 u8 a[0x1]; 3869 u8 rw[0x1]; 3870 u8 rr[0x1]; 3871 u8 lw[0x1]; 3872 u8 lr[0x1]; 3873 u8 access_mode_1_0[0x2]; 3874 u8 reserved_at_18[0x8]; 3875 3876 u8 qpn[0x18]; 3877 u8 mkey_7_0[0x8]; 3878 3879 u8 reserved_at_40[0x20]; 3880 3881 u8 length64[0x1]; 3882 u8 bsf_en[0x1]; 3883 u8 sync_umr[0x1]; 3884 u8 reserved_at_63[0x2]; 3885 u8 expected_sigerr_count[0x1]; 3886 u8 reserved_at_66[0x1]; 3887 u8 en_rinval[0x1]; 3888 u8 pd[0x18]; 3889 3890 u8 start_addr[0x40]; 3891 3892 u8 len[0x40]; 3893 3894 u8 bsf_octword_size[0x20]; 3895 3896 u8 reserved_at_120[0x80]; 3897 3898 u8 translations_octword_size[0x20]; 3899 3900 u8 reserved_at_1c0[0x19]; 3901 u8 relaxed_ordering_read[0x1]; 3902 u8 reserved_at_1d9[0x1]; 3903 u8 log_page_size[0x5]; 3904 3905 u8 reserved_at_1e0[0x20]; 3906 }; 3907 3908 struct mlx5_ifc_pkey_bits { 3909 u8 reserved_at_0[0x10]; 3910 u8 pkey[0x10]; 3911 }; 3912 3913 struct mlx5_ifc_array128_auto_bits { 3914 u8 array128_auto[16][0x8]; 3915 }; 3916 3917 struct mlx5_ifc_hca_vport_context_bits { 3918 u8 field_select[0x20]; 3919 3920 u8 reserved_at_20[0xe0]; 3921 3922 u8 sm_virt_aware[0x1]; 3923 u8 has_smi[0x1]; 3924 u8 has_raw[0x1]; 3925 u8 grh_required[0x1]; 3926 u8 reserved_at_104[0xc]; 3927 u8 port_physical_state[0x4]; 3928 u8 vport_state_policy[0x4]; 3929 u8 port_state[0x4]; 3930 u8 vport_state[0x4]; 3931 3932 u8 reserved_at_120[0x20]; 3933 3934 u8 system_image_guid[0x40]; 3935 3936 u8 port_guid[0x40]; 3937 3938 u8 node_guid[0x40]; 3939 3940 u8 cap_mask1[0x20]; 3941 3942 u8 cap_mask1_field_select[0x20]; 3943 3944 u8 cap_mask2[0x20]; 3945 3946 u8 cap_mask2_field_select[0x20]; 3947 3948 u8 reserved_at_280[0x80]; 3949 3950 u8 lid[0x10]; 3951 u8 reserved_at_310[0x4]; 3952 u8 init_type_reply[0x4]; 3953 u8 lmc[0x3]; 3954 u8 subnet_timeout[0x5]; 3955 3956 u8 sm_lid[0x10]; 3957 u8 sm_sl[0x4]; 3958 u8 reserved_at_334[0xc]; 3959 3960 u8 qkey_violation_counter[0x10]; 3961 u8 pkey_violation_counter[0x10]; 3962 3963 u8 reserved_at_360[0xca0]; 3964 }; 3965 3966 struct mlx5_ifc_esw_vport_context_bits { 3967 u8 fdb_to_vport_reg_c[0x1]; 3968 u8 reserved_at_1[0x2]; 3969 u8 vport_svlan_strip[0x1]; 3970 u8 vport_cvlan_strip[0x1]; 3971 u8 vport_svlan_insert[0x1]; 3972 u8 vport_cvlan_insert[0x2]; 3973 u8 fdb_to_vport_reg_c_id[0x8]; 3974 u8 reserved_at_10[0x10]; 3975 3976 u8 reserved_at_20[0x20]; 3977 3978 u8 svlan_cfi[0x1]; 3979 u8 svlan_pcp[0x3]; 3980 u8 svlan_id[0xc]; 3981 u8 cvlan_cfi[0x1]; 3982 u8 cvlan_pcp[0x3]; 3983 u8 cvlan_id[0xc]; 3984 3985 u8 reserved_at_60[0x720]; 3986 3987 u8 sw_steering_vport_icm_address_rx[0x40]; 3988 3989 u8 sw_steering_vport_icm_address_tx[0x40]; 3990 }; 3991 3992 enum { 3993 MLX5_EQC_STATUS_OK = 0x0, 3994 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3995 }; 3996 3997 enum { 3998 MLX5_EQC_ST_ARMED = 0x9, 3999 MLX5_EQC_ST_FIRED = 0xa, 4000 }; 4001 4002 struct mlx5_ifc_eqc_bits { 4003 u8 status[0x4]; 4004 u8 reserved_at_4[0x9]; 4005 u8 ec[0x1]; 4006 u8 oi[0x1]; 4007 u8 reserved_at_f[0x5]; 4008 u8 st[0x4]; 4009 u8 reserved_at_18[0x8]; 4010 4011 u8 reserved_at_20[0x20]; 4012 4013 u8 reserved_at_40[0x14]; 4014 u8 page_offset[0x6]; 4015 u8 reserved_at_5a[0x6]; 4016 4017 u8 reserved_at_60[0x3]; 4018 u8 log_eq_size[0x5]; 4019 u8 uar_page[0x18]; 4020 4021 u8 reserved_at_80[0x20]; 4022 4023 u8 reserved_at_a0[0x14]; 4024 u8 intr[0xc]; 4025 4026 u8 reserved_at_c0[0x3]; 4027 u8 log_page_size[0x5]; 4028 u8 reserved_at_c8[0x18]; 4029 4030 u8 reserved_at_e0[0x60]; 4031 4032 u8 reserved_at_140[0x8]; 4033 u8 consumer_counter[0x18]; 4034 4035 u8 reserved_at_160[0x8]; 4036 u8 producer_counter[0x18]; 4037 4038 u8 reserved_at_180[0x80]; 4039 }; 4040 4041 enum { 4042 MLX5_DCTC_STATE_ACTIVE = 0x0, 4043 MLX5_DCTC_STATE_DRAINING = 0x1, 4044 MLX5_DCTC_STATE_DRAINED = 0x2, 4045 }; 4046 4047 enum { 4048 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4049 MLX5_DCTC_CS_RES_NA = 0x1, 4050 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4051 }; 4052 4053 enum { 4054 MLX5_DCTC_MTU_256_BYTES = 0x1, 4055 MLX5_DCTC_MTU_512_BYTES = 0x2, 4056 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4057 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4058 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4059 }; 4060 4061 struct mlx5_ifc_dctc_bits { 4062 u8 reserved_at_0[0x4]; 4063 u8 state[0x4]; 4064 u8 reserved_at_8[0x18]; 4065 4066 u8 reserved_at_20[0x8]; 4067 u8 user_index[0x18]; 4068 4069 u8 reserved_at_40[0x8]; 4070 u8 cqn[0x18]; 4071 4072 u8 counter_set_id[0x8]; 4073 u8 atomic_mode[0x4]; 4074 u8 rre[0x1]; 4075 u8 rwe[0x1]; 4076 u8 rae[0x1]; 4077 u8 atomic_like_write_en[0x1]; 4078 u8 latency_sensitive[0x1]; 4079 u8 rlky[0x1]; 4080 u8 free_ar[0x1]; 4081 u8 reserved_at_73[0xd]; 4082 4083 u8 reserved_at_80[0x8]; 4084 u8 cs_res[0x8]; 4085 u8 reserved_at_90[0x3]; 4086 u8 min_rnr_nak[0x5]; 4087 u8 reserved_at_98[0x8]; 4088 4089 u8 reserved_at_a0[0x8]; 4090 u8 srqn_xrqn[0x18]; 4091 4092 u8 reserved_at_c0[0x8]; 4093 u8 pd[0x18]; 4094 4095 u8 tclass[0x8]; 4096 u8 reserved_at_e8[0x4]; 4097 u8 flow_label[0x14]; 4098 4099 u8 dc_access_key[0x40]; 4100 4101 u8 reserved_at_140[0x5]; 4102 u8 mtu[0x3]; 4103 u8 port[0x8]; 4104 u8 pkey_index[0x10]; 4105 4106 u8 reserved_at_160[0x8]; 4107 u8 my_addr_index[0x8]; 4108 u8 reserved_at_170[0x8]; 4109 u8 hop_limit[0x8]; 4110 4111 u8 dc_access_key_violation_count[0x20]; 4112 4113 u8 reserved_at_1a0[0x14]; 4114 u8 dei_cfi[0x1]; 4115 u8 eth_prio[0x3]; 4116 u8 ecn[0x2]; 4117 u8 dscp[0x6]; 4118 4119 u8 reserved_at_1c0[0x20]; 4120 u8 ece[0x20]; 4121 }; 4122 4123 enum { 4124 MLX5_CQC_STATUS_OK = 0x0, 4125 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4126 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4127 }; 4128 4129 enum { 4130 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4131 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4132 }; 4133 4134 enum { 4135 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4136 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4137 MLX5_CQC_ST_FIRED = 0xa, 4138 }; 4139 4140 enum { 4141 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4142 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4143 MLX5_CQ_PERIOD_NUM_MODES 4144 }; 4145 4146 struct mlx5_ifc_cqc_bits { 4147 u8 status[0x4]; 4148 u8 reserved_at_4[0x2]; 4149 u8 dbr_umem_valid[0x1]; 4150 u8 apu_cq[0x1]; 4151 u8 cqe_sz[0x3]; 4152 u8 cc[0x1]; 4153 u8 reserved_at_c[0x1]; 4154 u8 scqe_break_moderation_en[0x1]; 4155 u8 oi[0x1]; 4156 u8 cq_period_mode[0x2]; 4157 u8 cqe_comp_en[0x1]; 4158 u8 mini_cqe_res_format[0x2]; 4159 u8 st[0x4]; 4160 u8 reserved_at_18[0x6]; 4161 u8 cqe_compression_layout[0x2]; 4162 4163 u8 reserved_at_20[0x20]; 4164 4165 u8 reserved_at_40[0x14]; 4166 u8 page_offset[0x6]; 4167 u8 reserved_at_5a[0x6]; 4168 4169 u8 reserved_at_60[0x3]; 4170 u8 log_cq_size[0x5]; 4171 u8 uar_page[0x18]; 4172 4173 u8 reserved_at_80[0x4]; 4174 u8 cq_period[0xc]; 4175 u8 cq_max_count[0x10]; 4176 4177 u8 c_eqn_or_apu_element[0x20]; 4178 4179 u8 reserved_at_c0[0x3]; 4180 u8 log_page_size[0x5]; 4181 u8 reserved_at_c8[0x18]; 4182 4183 u8 reserved_at_e0[0x20]; 4184 4185 u8 reserved_at_100[0x8]; 4186 u8 last_notified_index[0x18]; 4187 4188 u8 reserved_at_120[0x8]; 4189 u8 last_solicit_index[0x18]; 4190 4191 u8 reserved_at_140[0x8]; 4192 u8 consumer_counter[0x18]; 4193 4194 u8 reserved_at_160[0x8]; 4195 u8 producer_counter[0x18]; 4196 4197 u8 reserved_at_180[0x40]; 4198 4199 u8 dbr_addr[0x40]; 4200 }; 4201 4202 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4203 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4204 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4205 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4206 u8 reserved_at_0[0x800]; 4207 }; 4208 4209 struct mlx5_ifc_query_adapter_param_block_bits { 4210 u8 reserved_at_0[0xc0]; 4211 4212 u8 reserved_at_c0[0x8]; 4213 u8 ieee_vendor_id[0x18]; 4214 4215 u8 reserved_at_e0[0x10]; 4216 u8 vsd_vendor_id[0x10]; 4217 4218 u8 vsd[208][0x8]; 4219 4220 u8 vsd_contd_psid[16][0x8]; 4221 }; 4222 4223 enum { 4224 MLX5_XRQC_STATE_GOOD = 0x0, 4225 MLX5_XRQC_STATE_ERROR = 0x1, 4226 }; 4227 4228 enum { 4229 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4230 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4231 }; 4232 4233 enum { 4234 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4235 }; 4236 4237 struct mlx5_ifc_tag_matching_topology_context_bits { 4238 u8 log_matching_list_sz[0x4]; 4239 u8 reserved_at_4[0xc]; 4240 u8 append_next_index[0x10]; 4241 4242 u8 sw_phase_cnt[0x10]; 4243 u8 hw_phase_cnt[0x10]; 4244 4245 u8 reserved_at_40[0x40]; 4246 }; 4247 4248 struct mlx5_ifc_xrqc_bits { 4249 u8 state[0x4]; 4250 u8 rlkey[0x1]; 4251 u8 reserved_at_5[0xf]; 4252 u8 topology[0x4]; 4253 u8 reserved_at_18[0x4]; 4254 u8 offload[0x4]; 4255 4256 u8 reserved_at_20[0x8]; 4257 u8 user_index[0x18]; 4258 4259 u8 reserved_at_40[0x8]; 4260 u8 cqn[0x18]; 4261 4262 u8 reserved_at_60[0xa0]; 4263 4264 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4265 4266 u8 reserved_at_180[0x280]; 4267 4268 struct mlx5_ifc_wq_bits wq; 4269 }; 4270 4271 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4272 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4273 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4274 u8 reserved_at_0[0x20]; 4275 }; 4276 4277 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4278 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4279 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4280 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4281 u8 reserved_at_0[0x20]; 4282 }; 4283 4284 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4285 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4286 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4287 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4288 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4289 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4290 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4291 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4292 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4293 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4294 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4295 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4296 u8 reserved_at_0[0x7c0]; 4297 }; 4298 4299 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4300 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4301 u8 reserved_at_0[0x7c0]; 4302 }; 4303 4304 union mlx5_ifc_event_auto_bits { 4305 struct mlx5_ifc_comp_event_bits comp_event; 4306 struct mlx5_ifc_dct_events_bits dct_events; 4307 struct mlx5_ifc_qp_events_bits qp_events; 4308 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4309 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4310 struct mlx5_ifc_cq_error_bits cq_error; 4311 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4312 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4313 struct mlx5_ifc_gpio_event_bits gpio_event; 4314 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4315 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4316 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4317 u8 reserved_at_0[0xe0]; 4318 }; 4319 4320 struct mlx5_ifc_health_buffer_bits { 4321 u8 reserved_at_0[0x100]; 4322 4323 u8 assert_existptr[0x20]; 4324 4325 u8 assert_callra[0x20]; 4326 4327 u8 reserved_at_140[0x20]; 4328 4329 u8 time[0x20]; 4330 4331 u8 fw_version[0x20]; 4332 4333 u8 hw_id[0x20]; 4334 4335 u8 rfr[0x1]; 4336 u8 reserved_at_1c1[0x3]; 4337 u8 valid[0x1]; 4338 u8 severity[0x3]; 4339 u8 reserved_at_1c8[0x18]; 4340 4341 u8 irisc_index[0x8]; 4342 u8 synd[0x8]; 4343 u8 ext_synd[0x10]; 4344 }; 4345 4346 struct mlx5_ifc_register_loopback_control_bits { 4347 u8 no_lb[0x1]; 4348 u8 reserved_at_1[0x7]; 4349 u8 port[0x8]; 4350 u8 reserved_at_10[0x10]; 4351 4352 u8 reserved_at_20[0x60]; 4353 }; 4354 4355 struct mlx5_ifc_vport_tc_element_bits { 4356 u8 traffic_class[0x4]; 4357 u8 reserved_at_4[0xc]; 4358 u8 vport_number[0x10]; 4359 }; 4360 4361 struct mlx5_ifc_vport_element_bits { 4362 u8 reserved_at_0[0x10]; 4363 u8 vport_number[0x10]; 4364 }; 4365 4366 enum { 4367 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4368 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4369 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4370 }; 4371 4372 struct mlx5_ifc_tsar_element_bits { 4373 u8 reserved_at_0[0x8]; 4374 u8 tsar_type[0x8]; 4375 u8 reserved_at_10[0x10]; 4376 }; 4377 4378 enum { 4379 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4380 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4381 }; 4382 4383 struct mlx5_ifc_teardown_hca_out_bits { 4384 u8 status[0x8]; 4385 u8 reserved_at_8[0x18]; 4386 4387 u8 syndrome[0x20]; 4388 4389 u8 reserved_at_40[0x3f]; 4390 4391 u8 state[0x1]; 4392 }; 4393 4394 enum { 4395 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4396 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4397 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4398 }; 4399 4400 struct mlx5_ifc_teardown_hca_in_bits { 4401 u8 opcode[0x10]; 4402 u8 reserved_at_10[0x10]; 4403 4404 u8 reserved_at_20[0x10]; 4405 u8 op_mod[0x10]; 4406 4407 u8 reserved_at_40[0x10]; 4408 u8 profile[0x10]; 4409 4410 u8 reserved_at_60[0x20]; 4411 }; 4412 4413 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4414 u8 status[0x8]; 4415 u8 reserved_at_8[0x18]; 4416 4417 u8 syndrome[0x20]; 4418 4419 u8 reserved_at_40[0x40]; 4420 }; 4421 4422 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4423 u8 opcode[0x10]; 4424 u8 uid[0x10]; 4425 4426 u8 reserved_at_20[0x10]; 4427 u8 op_mod[0x10]; 4428 4429 u8 reserved_at_40[0x8]; 4430 u8 qpn[0x18]; 4431 4432 u8 reserved_at_60[0x20]; 4433 4434 u8 opt_param_mask[0x20]; 4435 4436 u8 reserved_at_a0[0x20]; 4437 4438 struct mlx5_ifc_qpc_bits qpc; 4439 4440 u8 reserved_at_800[0x80]; 4441 }; 4442 4443 struct mlx5_ifc_sqd2rts_qp_out_bits { 4444 u8 status[0x8]; 4445 u8 reserved_at_8[0x18]; 4446 4447 u8 syndrome[0x20]; 4448 4449 u8 reserved_at_40[0x40]; 4450 }; 4451 4452 struct mlx5_ifc_sqd2rts_qp_in_bits { 4453 u8 opcode[0x10]; 4454 u8 uid[0x10]; 4455 4456 u8 reserved_at_20[0x10]; 4457 u8 op_mod[0x10]; 4458 4459 u8 reserved_at_40[0x8]; 4460 u8 qpn[0x18]; 4461 4462 u8 reserved_at_60[0x20]; 4463 4464 u8 opt_param_mask[0x20]; 4465 4466 u8 reserved_at_a0[0x20]; 4467 4468 struct mlx5_ifc_qpc_bits qpc; 4469 4470 u8 reserved_at_800[0x80]; 4471 }; 4472 4473 struct mlx5_ifc_set_roce_address_out_bits { 4474 u8 status[0x8]; 4475 u8 reserved_at_8[0x18]; 4476 4477 u8 syndrome[0x20]; 4478 4479 u8 reserved_at_40[0x40]; 4480 }; 4481 4482 struct mlx5_ifc_set_roce_address_in_bits { 4483 u8 opcode[0x10]; 4484 u8 reserved_at_10[0x10]; 4485 4486 u8 reserved_at_20[0x10]; 4487 u8 op_mod[0x10]; 4488 4489 u8 roce_address_index[0x10]; 4490 u8 reserved_at_50[0xc]; 4491 u8 vhca_port_num[0x4]; 4492 4493 u8 reserved_at_60[0x20]; 4494 4495 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4496 }; 4497 4498 struct mlx5_ifc_set_mad_demux_out_bits { 4499 u8 status[0x8]; 4500 u8 reserved_at_8[0x18]; 4501 4502 u8 syndrome[0x20]; 4503 4504 u8 reserved_at_40[0x40]; 4505 }; 4506 4507 enum { 4508 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4509 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4510 }; 4511 4512 struct mlx5_ifc_set_mad_demux_in_bits { 4513 u8 opcode[0x10]; 4514 u8 reserved_at_10[0x10]; 4515 4516 u8 reserved_at_20[0x10]; 4517 u8 op_mod[0x10]; 4518 4519 u8 reserved_at_40[0x20]; 4520 4521 u8 reserved_at_60[0x6]; 4522 u8 demux_mode[0x2]; 4523 u8 reserved_at_68[0x18]; 4524 }; 4525 4526 struct mlx5_ifc_set_l2_table_entry_out_bits { 4527 u8 status[0x8]; 4528 u8 reserved_at_8[0x18]; 4529 4530 u8 syndrome[0x20]; 4531 4532 u8 reserved_at_40[0x40]; 4533 }; 4534 4535 struct mlx5_ifc_set_l2_table_entry_in_bits { 4536 u8 opcode[0x10]; 4537 u8 reserved_at_10[0x10]; 4538 4539 u8 reserved_at_20[0x10]; 4540 u8 op_mod[0x10]; 4541 4542 u8 reserved_at_40[0x60]; 4543 4544 u8 reserved_at_a0[0x8]; 4545 u8 table_index[0x18]; 4546 4547 u8 reserved_at_c0[0x20]; 4548 4549 u8 reserved_at_e0[0x13]; 4550 u8 vlan_valid[0x1]; 4551 u8 vlan[0xc]; 4552 4553 struct mlx5_ifc_mac_address_layout_bits mac_address; 4554 4555 u8 reserved_at_140[0xc0]; 4556 }; 4557 4558 struct mlx5_ifc_set_issi_out_bits { 4559 u8 status[0x8]; 4560 u8 reserved_at_8[0x18]; 4561 4562 u8 syndrome[0x20]; 4563 4564 u8 reserved_at_40[0x40]; 4565 }; 4566 4567 struct mlx5_ifc_set_issi_in_bits { 4568 u8 opcode[0x10]; 4569 u8 reserved_at_10[0x10]; 4570 4571 u8 reserved_at_20[0x10]; 4572 u8 op_mod[0x10]; 4573 4574 u8 reserved_at_40[0x10]; 4575 u8 current_issi[0x10]; 4576 4577 u8 reserved_at_60[0x20]; 4578 }; 4579 4580 struct mlx5_ifc_set_hca_cap_out_bits { 4581 u8 status[0x8]; 4582 u8 reserved_at_8[0x18]; 4583 4584 u8 syndrome[0x20]; 4585 4586 u8 reserved_at_40[0x40]; 4587 }; 4588 4589 struct mlx5_ifc_set_hca_cap_in_bits { 4590 u8 opcode[0x10]; 4591 u8 reserved_at_10[0x10]; 4592 4593 u8 reserved_at_20[0x10]; 4594 u8 op_mod[0x10]; 4595 4596 u8 other_function[0x1]; 4597 u8 reserved_at_41[0xf]; 4598 u8 function_id[0x10]; 4599 4600 u8 reserved_at_60[0x20]; 4601 4602 union mlx5_ifc_hca_cap_union_bits capability; 4603 }; 4604 4605 enum { 4606 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4607 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4608 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4609 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4610 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4611 }; 4612 4613 struct mlx5_ifc_set_fte_out_bits { 4614 u8 status[0x8]; 4615 u8 reserved_at_8[0x18]; 4616 4617 u8 syndrome[0x20]; 4618 4619 u8 reserved_at_40[0x40]; 4620 }; 4621 4622 struct mlx5_ifc_set_fte_in_bits { 4623 u8 opcode[0x10]; 4624 u8 reserved_at_10[0x10]; 4625 4626 u8 reserved_at_20[0x10]; 4627 u8 op_mod[0x10]; 4628 4629 u8 other_vport[0x1]; 4630 u8 reserved_at_41[0xf]; 4631 u8 vport_number[0x10]; 4632 4633 u8 reserved_at_60[0x20]; 4634 4635 u8 table_type[0x8]; 4636 u8 reserved_at_88[0x18]; 4637 4638 u8 reserved_at_a0[0x8]; 4639 u8 table_id[0x18]; 4640 4641 u8 ignore_flow_level[0x1]; 4642 u8 reserved_at_c1[0x17]; 4643 u8 modify_enable_mask[0x8]; 4644 4645 u8 reserved_at_e0[0x20]; 4646 4647 u8 flow_index[0x20]; 4648 4649 u8 reserved_at_120[0xe0]; 4650 4651 struct mlx5_ifc_flow_context_bits flow_context; 4652 }; 4653 4654 struct mlx5_ifc_rts2rts_qp_out_bits { 4655 u8 status[0x8]; 4656 u8 reserved_at_8[0x18]; 4657 4658 u8 syndrome[0x20]; 4659 4660 u8 reserved_at_40[0x20]; 4661 u8 ece[0x20]; 4662 }; 4663 4664 struct mlx5_ifc_rts2rts_qp_in_bits { 4665 u8 opcode[0x10]; 4666 u8 uid[0x10]; 4667 4668 u8 reserved_at_20[0x10]; 4669 u8 op_mod[0x10]; 4670 4671 u8 reserved_at_40[0x8]; 4672 u8 qpn[0x18]; 4673 4674 u8 reserved_at_60[0x20]; 4675 4676 u8 opt_param_mask[0x20]; 4677 4678 u8 ece[0x20]; 4679 4680 struct mlx5_ifc_qpc_bits qpc; 4681 4682 u8 reserved_at_800[0x80]; 4683 }; 4684 4685 struct mlx5_ifc_rtr2rts_qp_out_bits { 4686 u8 status[0x8]; 4687 u8 reserved_at_8[0x18]; 4688 4689 u8 syndrome[0x20]; 4690 4691 u8 reserved_at_40[0x20]; 4692 u8 ece[0x20]; 4693 }; 4694 4695 struct mlx5_ifc_rtr2rts_qp_in_bits { 4696 u8 opcode[0x10]; 4697 u8 uid[0x10]; 4698 4699 u8 reserved_at_20[0x10]; 4700 u8 op_mod[0x10]; 4701 4702 u8 reserved_at_40[0x8]; 4703 u8 qpn[0x18]; 4704 4705 u8 reserved_at_60[0x20]; 4706 4707 u8 opt_param_mask[0x20]; 4708 4709 u8 ece[0x20]; 4710 4711 struct mlx5_ifc_qpc_bits qpc; 4712 4713 u8 reserved_at_800[0x80]; 4714 }; 4715 4716 struct mlx5_ifc_rst2init_qp_out_bits { 4717 u8 status[0x8]; 4718 u8 reserved_at_8[0x18]; 4719 4720 u8 syndrome[0x20]; 4721 4722 u8 reserved_at_40[0x20]; 4723 u8 ece[0x20]; 4724 }; 4725 4726 struct mlx5_ifc_rst2init_qp_in_bits { 4727 u8 opcode[0x10]; 4728 u8 uid[0x10]; 4729 4730 u8 reserved_at_20[0x10]; 4731 u8 op_mod[0x10]; 4732 4733 u8 reserved_at_40[0x8]; 4734 u8 qpn[0x18]; 4735 4736 u8 reserved_at_60[0x20]; 4737 4738 u8 opt_param_mask[0x20]; 4739 4740 u8 ece[0x20]; 4741 4742 struct mlx5_ifc_qpc_bits qpc; 4743 4744 u8 reserved_at_800[0x80]; 4745 }; 4746 4747 struct mlx5_ifc_query_xrq_out_bits { 4748 u8 status[0x8]; 4749 u8 reserved_at_8[0x18]; 4750 4751 u8 syndrome[0x20]; 4752 4753 u8 reserved_at_40[0x40]; 4754 4755 struct mlx5_ifc_xrqc_bits xrq_context; 4756 }; 4757 4758 struct mlx5_ifc_query_xrq_in_bits { 4759 u8 opcode[0x10]; 4760 u8 reserved_at_10[0x10]; 4761 4762 u8 reserved_at_20[0x10]; 4763 u8 op_mod[0x10]; 4764 4765 u8 reserved_at_40[0x8]; 4766 u8 xrqn[0x18]; 4767 4768 u8 reserved_at_60[0x20]; 4769 }; 4770 4771 struct mlx5_ifc_query_xrc_srq_out_bits { 4772 u8 status[0x8]; 4773 u8 reserved_at_8[0x18]; 4774 4775 u8 syndrome[0x20]; 4776 4777 u8 reserved_at_40[0x40]; 4778 4779 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4780 4781 u8 reserved_at_280[0x600]; 4782 4783 u8 pas[][0x40]; 4784 }; 4785 4786 struct mlx5_ifc_query_xrc_srq_in_bits { 4787 u8 opcode[0x10]; 4788 u8 reserved_at_10[0x10]; 4789 4790 u8 reserved_at_20[0x10]; 4791 u8 op_mod[0x10]; 4792 4793 u8 reserved_at_40[0x8]; 4794 u8 xrc_srqn[0x18]; 4795 4796 u8 reserved_at_60[0x20]; 4797 }; 4798 4799 enum { 4800 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4801 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4802 }; 4803 4804 struct mlx5_ifc_query_vport_state_out_bits { 4805 u8 status[0x8]; 4806 u8 reserved_at_8[0x18]; 4807 4808 u8 syndrome[0x20]; 4809 4810 u8 reserved_at_40[0x20]; 4811 4812 u8 reserved_at_60[0x18]; 4813 u8 admin_state[0x4]; 4814 u8 state[0x4]; 4815 }; 4816 4817 enum { 4818 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4819 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4820 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4821 }; 4822 4823 struct mlx5_ifc_arm_monitor_counter_in_bits { 4824 u8 opcode[0x10]; 4825 u8 uid[0x10]; 4826 4827 u8 reserved_at_20[0x10]; 4828 u8 op_mod[0x10]; 4829 4830 u8 reserved_at_40[0x20]; 4831 4832 u8 reserved_at_60[0x20]; 4833 }; 4834 4835 struct mlx5_ifc_arm_monitor_counter_out_bits { 4836 u8 status[0x8]; 4837 u8 reserved_at_8[0x18]; 4838 4839 u8 syndrome[0x20]; 4840 4841 u8 reserved_at_40[0x40]; 4842 }; 4843 4844 enum { 4845 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4846 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4847 }; 4848 4849 enum mlx5_monitor_counter_ppcnt { 4850 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4851 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4852 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4853 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4854 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4855 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4856 }; 4857 4858 enum { 4859 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4860 }; 4861 4862 struct mlx5_ifc_monitor_counter_output_bits { 4863 u8 reserved_at_0[0x4]; 4864 u8 type[0x4]; 4865 u8 reserved_at_8[0x8]; 4866 u8 counter[0x10]; 4867 4868 u8 counter_group_id[0x20]; 4869 }; 4870 4871 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4872 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4873 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4874 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4875 4876 struct mlx5_ifc_set_monitor_counter_in_bits { 4877 u8 opcode[0x10]; 4878 u8 uid[0x10]; 4879 4880 u8 reserved_at_20[0x10]; 4881 u8 op_mod[0x10]; 4882 4883 u8 reserved_at_40[0x10]; 4884 u8 num_of_counters[0x10]; 4885 4886 u8 reserved_at_60[0x20]; 4887 4888 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4889 }; 4890 4891 struct mlx5_ifc_set_monitor_counter_out_bits { 4892 u8 status[0x8]; 4893 u8 reserved_at_8[0x18]; 4894 4895 u8 syndrome[0x20]; 4896 4897 u8 reserved_at_40[0x40]; 4898 }; 4899 4900 struct mlx5_ifc_query_vport_state_in_bits { 4901 u8 opcode[0x10]; 4902 u8 reserved_at_10[0x10]; 4903 4904 u8 reserved_at_20[0x10]; 4905 u8 op_mod[0x10]; 4906 4907 u8 other_vport[0x1]; 4908 u8 reserved_at_41[0xf]; 4909 u8 vport_number[0x10]; 4910 4911 u8 reserved_at_60[0x20]; 4912 }; 4913 4914 struct mlx5_ifc_query_vnic_env_out_bits { 4915 u8 status[0x8]; 4916 u8 reserved_at_8[0x18]; 4917 4918 u8 syndrome[0x20]; 4919 4920 u8 reserved_at_40[0x40]; 4921 4922 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4923 }; 4924 4925 enum { 4926 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4927 }; 4928 4929 struct mlx5_ifc_query_vnic_env_in_bits { 4930 u8 opcode[0x10]; 4931 u8 reserved_at_10[0x10]; 4932 4933 u8 reserved_at_20[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 other_vport[0x1]; 4937 u8 reserved_at_41[0xf]; 4938 u8 vport_number[0x10]; 4939 4940 u8 reserved_at_60[0x20]; 4941 }; 4942 4943 struct mlx5_ifc_query_vport_counter_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_at_8[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_at_40[0x40]; 4950 4951 struct mlx5_ifc_traffic_counter_bits received_errors; 4952 4953 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4954 4955 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4956 4957 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4958 4959 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4960 4961 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4962 4963 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4964 4965 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4966 4967 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4968 4969 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4970 4971 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4972 4973 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4974 4975 u8 reserved_at_680[0xa00]; 4976 }; 4977 4978 enum { 4979 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4980 }; 4981 4982 struct mlx5_ifc_query_vport_counter_in_bits { 4983 u8 opcode[0x10]; 4984 u8 reserved_at_10[0x10]; 4985 4986 u8 reserved_at_20[0x10]; 4987 u8 op_mod[0x10]; 4988 4989 u8 other_vport[0x1]; 4990 u8 reserved_at_41[0xb]; 4991 u8 port_num[0x4]; 4992 u8 vport_number[0x10]; 4993 4994 u8 reserved_at_60[0x60]; 4995 4996 u8 clear[0x1]; 4997 u8 reserved_at_c1[0x1f]; 4998 4999 u8 reserved_at_e0[0x20]; 5000 }; 5001 5002 struct mlx5_ifc_query_tis_out_bits { 5003 u8 status[0x8]; 5004 u8 reserved_at_8[0x18]; 5005 5006 u8 syndrome[0x20]; 5007 5008 u8 reserved_at_40[0x40]; 5009 5010 struct mlx5_ifc_tisc_bits tis_context; 5011 }; 5012 5013 struct mlx5_ifc_query_tis_in_bits { 5014 u8 opcode[0x10]; 5015 u8 reserved_at_10[0x10]; 5016 5017 u8 reserved_at_20[0x10]; 5018 u8 op_mod[0x10]; 5019 5020 u8 reserved_at_40[0x8]; 5021 u8 tisn[0x18]; 5022 5023 u8 reserved_at_60[0x20]; 5024 }; 5025 5026 struct mlx5_ifc_query_tir_out_bits { 5027 u8 status[0x8]; 5028 u8 reserved_at_8[0x18]; 5029 5030 u8 syndrome[0x20]; 5031 5032 u8 reserved_at_40[0xc0]; 5033 5034 struct mlx5_ifc_tirc_bits tir_context; 5035 }; 5036 5037 struct mlx5_ifc_query_tir_in_bits { 5038 u8 opcode[0x10]; 5039 u8 reserved_at_10[0x10]; 5040 5041 u8 reserved_at_20[0x10]; 5042 u8 op_mod[0x10]; 5043 5044 u8 reserved_at_40[0x8]; 5045 u8 tirn[0x18]; 5046 5047 u8 reserved_at_60[0x20]; 5048 }; 5049 5050 struct mlx5_ifc_query_srq_out_bits { 5051 u8 status[0x8]; 5052 u8 reserved_at_8[0x18]; 5053 5054 u8 syndrome[0x20]; 5055 5056 u8 reserved_at_40[0x40]; 5057 5058 struct mlx5_ifc_srqc_bits srq_context_entry; 5059 5060 u8 reserved_at_280[0x600]; 5061 5062 u8 pas[][0x40]; 5063 }; 5064 5065 struct mlx5_ifc_query_srq_in_bits { 5066 u8 opcode[0x10]; 5067 u8 reserved_at_10[0x10]; 5068 5069 u8 reserved_at_20[0x10]; 5070 u8 op_mod[0x10]; 5071 5072 u8 reserved_at_40[0x8]; 5073 u8 srqn[0x18]; 5074 5075 u8 reserved_at_60[0x20]; 5076 }; 5077 5078 struct mlx5_ifc_query_sq_out_bits { 5079 u8 status[0x8]; 5080 u8 reserved_at_8[0x18]; 5081 5082 u8 syndrome[0x20]; 5083 5084 u8 reserved_at_40[0xc0]; 5085 5086 struct mlx5_ifc_sqc_bits sq_context; 5087 }; 5088 5089 struct mlx5_ifc_query_sq_in_bits { 5090 u8 opcode[0x10]; 5091 u8 reserved_at_10[0x10]; 5092 5093 u8 reserved_at_20[0x10]; 5094 u8 op_mod[0x10]; 5095 5096 u8 reserved_at_40[0x8]; 5097 u8 sqn[0x18]; 5098 5099 u8 reserved_at_60[0x20]; 5100 }; 5101 5102 struct mlx5_ifc_query_special_contexts_out_bits { 5103 u8 status[0x8]; 5104 u8 reserved_at_8[0x18]; 5105 5106 u8 syndrome[0x20]; 5107 5108 u8 dump_fill_mkey[0x20]; 5109 5110 u8 resd_lkey[0x20]; 5111 5112 u8 null_mkey[0x20]; 5113 5114 u8 reserved_at_a0[0x60]; 5115 }; 5116 5117 struct mlx5_ifc_query_special_contexts_in_bits { 5118 u8 opcode[0x10]; 5119 u8 reserved_at_10[0x10]; 5120 5121 u8 reserved_at_20[0x10]; 5122 u8 op_mod[0x10]; 5123 5124 u8 reserved_at_40[0x40]; 5125 }; 5126 5127 struct mlx5_ifc_query_scheduling_element_out_bits { 5128 u8 opcode[0x10]; 5129 u8 reserved_at_10[0x10]; 5130 5131 u8 reserved_at_20[0x10]; 5132 u8 op_mod[0x10]; 5133 5134 u8 reserved_at_40[0xc0]; 5135 5136 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5137 5138 u8 reserved_at_300[0x100]; 5139 }; 5140 5141 enum { 5142 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5143 SCHEDULING_HIERARCHY_NIC = 0x3, 5144 }; 5145 5146 struct mlx5_ifc_query_scheduling_element_in_bits { 5147 u8 opcode[0x10]; 5148 u8 reserved_at_10[0x10]; 5149 5150 u8 reserved_at_20[0x10]; 5151 u8 op_mod[0x10]; 5152 5153 u8 scheduling_hierarchy[0x8]; 5154 u8 reserved_at_48[0x18]; 5155 5156 u8 scheduling_element_id[0x20]; 5157 5158 u8 reserved_at_80[0x180]; 5159 }; 5160 5161 struct mlx5_ifc_query_rqt_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_at_8[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_at_40[0xc0]; 5168 5169 struct mlx5_ifc_rqtc_bits rqt_context; 5170 }; 5171 5172 struct mlx5_ifc_query_rqt_in_bits { 5173 u8 opcode[0x10]; 5174 u8 reserved_at_10[0x10]; 5175 5176 u8 reserved_at_20[0x10]; 5177 u8 op_mod[0x10]; 5178 5179 u8 reserved_at_40[0x8]; 5180 u8 rqtn[0x18]; 5181 5182 u8 reserved_at_60[0x20]; 5183 }; 5184 5185 struct mlx5_ifc_query_rq_out_bits { 5186 u8 status[0x8]; 5187 u8 reserved_at_8[0x18]; 5188 5189 u8 syndrome[0x20]; 5190 5191 u8 reserved_at_40[0xc0]; 5192 5193 struct mlx5_ifc_rqc_bits rq_context; 5194 }; 5195 5196 struct mlx5_ifc_query_rq_in_bits { 5197 u8 opcode[0x10]; 5198 u8 reserved_at_10[0x10]; 5199 5200 u8 reserved_at_20[0x10]; 5201 u8 op_mod[0x10]; 5202 5203 u8 reserved_at_40[0x8]; 5204 u8 rqn[0x18]; 5205 5206 u8 reserved_at_60[0x20]; 5207 }; 5208 5209 struct mlx5_ifc_query_roce_address_out_bits { 5210 u8 status[0x8]; 5211 u8 reserved_at_8[0x18]; 5212 5213 u8 syndrome[0x20]; 5214 5215 u8 reserved_at_40[0x40]; 5216 5217 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5218 }; 5219 5220 struct mlx5_ifc_query_roce_address_in_bits { 5221 u8 opcode[0x10]; 5222 u8 reserved_at_10[0x10]; 5223 5224 u8 reserved_at_20[0x10]; 5225 u8 op_mod[0x10]; 5226 5227 u8 roce_address_index[0x10]; 5228 u8 reserved_at_50[0xc]; 5229 u8 vhca_port_num[0x4]; 5230 5231 u8 reserved_at_60[0x20]; 5232 }; 5233 5234 struct mlx5_ifc_query_rmp_out_bits { 5235 u8 status[0x8]; 5236 u8 reserved_at_8[0x18]; 5237 5238 u8 syndrome[0x20]; 5239 5240 u8 reserved_at_40[0xc0]; 5241 5242 struct mlx5_ifc_rmpc_bits rmp_context; 5243 }; 5244 5245 struct mlx5_ifc_query_rmp_in_bits { 5246 u8 opcode[0x10]; 5247 u8 reserved_at_10[0x10]; 5248 5249 u8 reserved_at_20[0x10]; 5250 u8 op_mod[0x10]; 5251 5252 u8 reserved_at_40[0x8]; 5253 u8 rmpn[0x18]; 5254 5255 u8 reserved_at_60[0x20]; 5256 }; 5257 5258 struct mlx5_ifc_query_qp_out_bits { 5259 u8 status[0x8]; 5260 u8 reserved_at_8[0x18]; 5261 5262 u8 syndrome[0x20]; 5263 5264 u8 reserved_at_40[0x40]; 5265 5266 u8 opt_param_mask[0x20]; 5267 5268 u8 ece[0x20]; 5269 5270 struct mlx5_ifc_qpc_bits qpc; 5271 5272 u8 reserved_at_800[0x80]; 5273 5274 u8 pas[][0x40]; 5275 }; 5276 5277 struct mlx5_ifc_query_qp_in_bits { 5278 u8 opcode[0x10]; 5279 u8 reserved_at_10[0x10]; 5280 5281 u8 reserved_at_20[0x10]; 5282 u8 op_mod[0x10]; 5283 5284 u8 reserved_at_40[0x8]; 5285 u8 qpn[0x18]; 5286 5287 u8 reserved_at_60[0x20]; 5288 }; 5289 5290 struct mlx5_ifc_query_q_counter_out_bits { 5291 u8 status[0x8]; 5292 u8 reserved_at_8[0x18]; 5293 5294 u8 syndrome[0x20]; 5295 5296 u8 reserved_at_40[0x40]; 5297 5298 u8 rx_write_requests[0x20]; 5299 5300 u8 reserved_at_a0[0x20]; 5301 5302 u8 rx_read_requests[0x20]; 5303 5304 u8 reserved_at_e0[0x20]; 5305 5306 u8 rx_atomic_requests[0x20]; 5307 5308 u8 reserved_at_120[0x20]; 5309 5310 u8 rx_dct_connect[0x20]; 5311 5312 u8 reserved_at_160[0x20]; 5313 5314 u8 out_of_buffer[0x20]; 5315 5316 u8 reserved_at_1a0[0x20]; 5317 5318 u8 out_of_sequence[0x20]; 5319 5320 u8 reserved_at_1e0[0x20]; 5321 5322 u8 duplicate_request[0x20]; 5323 5324 u8 reserved_at_220[0x20]; 5325 5326 u8 rnr_nak_retry_err[0x20]; 5327 5328 u8 reserved_at_260[0x20]; 5329 5330 u8 packet_seq_err[0x20]; 5331 5332 u8 reserved_at_2a0[0x20]; 5333 5334 u8 implied_nak_seq_err[0x20]; 5335 5336 u8 reserved_at_2e0[0x20]; 5337 5338 u8 local_ack_timeout_err[0x20]; 5339 5340 u8 reserved_at_320[0xa0]; 5341 5342 u8 resp_local_length_error[0x20]; 5343 5344 u8 req_local_length_error[0x20]; 5345 5346 u8 resp_local_qp_error[0x20]; 5347 5348 u8 local_operation_error[0x20]; 5349 5350 u8 resp_local_protection[0x20]; 5351 5352 u8 req_local_protection[0x20]; 5353 5354 u8 resp_cqe_error[0x20]; 5355 5356 u8 req_cqe_error[0x20]; 5357 5358 u8 req_mw_binding[0x20]; 5359 5360 u8 req_bad_response[0x20]; 5361 5362 u8 req_remote_invalid_request[0x20]; 5363 5364 u8 resp_remote_invalid_request[0x20]; 5365 5366 u8 req_remote_access_errors[0x20]; 5367 5368 u8 resp_remote_access_errors[0x20]; 5369 5370 u8 req_remote_operation_errors[0x20]; 5371 5372 u8 req_transport_retries_exceeded[0x20]; 5373 5374 u8 cq_overflow[0x20]; 5375 5376 u8 resp_cqe_flush_error[0x20]; 5377 5378 u8 req_cqe_flush_error[0x20]; 5379 5380 u8 reserved_at_620[0x20]; 5381 5382 u8 roce_adp_retrans[0x20]; 5383 5384 u8 roce_adp_retrans_to[0x20]; 5385 5386 u8 roce_slow_restart[0x20]; 5387 5388 u8 roce_slow_restart_cnps[0x20]; 5389 5390 u8 roce_slow_restart_trans[0x20]; 5391 5392 u8 reserved_at_6e0[0x120]; 5393 }; 5394 5395 struct mlx5_ifc_query_q_counter_in_bits { 5396 u8 opcode[0x10]; 5397 u8 reserved_at_10[0x10]; 5398 5399 u8 reserved_at_20[0x10]; 5400 u8 op_mod[0x10]; 5401 5402 u8 reserved_at_40[0x80]; 5403 5404 u8 clear[0x1]; 5405 u8 reserved_at_c1[0x1f]; 5406 5407 u8 reserved_at_e0[0x18]; 5408 u8 counter_set_id[0x8]; 5409 }; 5410 5411 struct mlx5_ifc_query_pages_out_bits { 5412 u8 status[0x8]; 5413 u8 reserved_at_8[0x18]; 5414 5415 u8 syndrome[0x20]; 5416 5417 u8 embedded_cpu_function[0x1]; 5418 u8 reserved_at_41[0xf]; 5419 u8 function_id[0x10]; 5420 5421 u8 num_pages[0x20]; 5422 }; 5423 5424 enum { 5425 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5426 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5427 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5428 }; 5429 5430 struct mlx5_ifc_query_pages_in_bits { 5431 u8 opcode[0x10]; 5432 u8 reserved_at_10[0x10]; 5433 5434 u8 reserved_at_20[0x10]; 5435 u8 op_mod[0x10]; 5436 5437 u8 embedded_cpu_function[0x1]; 5438 u8 reserved_at_41[0xf]; 5439 u8 function_id[0x10]; 5440 5441 u8 reserved_at_60[0x20]; 5442 }; 5443 5444 struct mlx5_ifc_query_nic_vport_context_out_bits { 5445 u8 status[0x8]; 5446 u8 reserved_at_8[0x18]; 5447 5448 u8 syndrome[0x20]; 5449 5450 u8 reserved_at_40[0x40]; 5451 5452 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5453 }; 5454 5455 struct mlx5_ifc_query_nic_vport_context_in_bits { 5456 u8 opcode[0x10]; 5457 u8 reserved_at_10[0x10]; 5458 5459 u8 reserved_at_20[0x10]; 5460 u8 op_mod[0x10]; 5461 5462 u8 other_vport[0x1]; 5463 u8 reserved_at_41[0xf]; 5464 u8 vport_number[0x10]; 5465 5466 u8 reserved_at_60[0x5]; 5467 u8 allowed_list_type[0x3]; 5468 u8 reserved_at_68[0x18]; 5469 }; 5470 5471 struct mlx5_ifc_query_mkey_out_bits { 5472 u8 status[0x8]; 5473 u8 reserved_at_8[0x18]; 5474 5475 u8 syndrome[0x20]; 5476 5477 u8 reserved_at_40[0x40]; 5478 5479 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5480 5481 u8 reserved_at_280[0x600]; 5482 5483 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5484 5485 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5486 }; 5487 5488 struct mlx5_ifc_query_mkey_in_bits { 5489 u8 opcode[0x10]; 5490 u8 reserved_at_10[0x10]; 5491 5492 u8 reserved_at_20[0x10]; 5493 u8 op_mod[0x10]; 5494 5495 u8 reserved_at_40[0x8]; 5496 u8 mkey_index[0x18]; 5497 5498 u8 pg_access[0x1]; 5499 u8 reserved_at_61[0x1f]; 5500 }; 5501 5502 struct mlx5_ifc_query_mad_demux_out_bits { 5503 u8 status[0x8]; 5504 u8 reserved_at_8[0x18]; 5505 5506 u8 syndrome[0x20]; 5507 5508 u8 reserved_at_40[0x40]; 5509 5510 u8 mad_dumux_parameters_block[0x20]; 5511 }; 5512 5513 struct mlx5_ifc_query_mad_demux_in_bits { 5514 u8 opcode[0x10]; 5515 u8 reserved_at_10[0x10]; 5516 5517 u8 reserved_at_20[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 reserved_at_40[0x40]; 5521 }; 5522 5523 struct mlx5_ifc_query_l2_table_entry_out_bits { 5524 u8 status[0x8]; 5525 u8 reserved_at_8[0x18]; 5526 5527 u8 syndrome[0x20]; 5528 5529 u8 reserved_at_40[0xa0]; 5530 5531 u8 reserved_at_e0[0x13]; 5532 u8 vlan_valid[0x1]; 5533 u8 vlan[0xc]; 5534 5535 struct mlx5_ifc_mac_address_layout_bits mac_address; 5536 5537 u8 reserved_at_140[0xc0]; 5538 }; 5539 5540 struct mlx5_ifc_query_l2_table_entry_in_bits { 5541 u8 opcode[0x10]; 5542 u8 reserved_at_10[0x10]; 5543 5544 u8 reserved_at_20[0x10]; 5545 u8 op_mod[0x10]; 5546 5547 u8 reserved_at_40[0x60]; 5548 5549 u8 reserved_at_a0[0x8]; 5550 u8 table_index[0x18]; 5551 5552 u8 reserved_at_c0[0x140]; 5553 }; 5554 5555 struct mlx5_ifc_query_issi_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x10]; 5562 u8 current_issi[0x10]; 5563 5564 u8 reserved_at_60[0xa0]; 5565 5566 u8 reserved_at_100[76][0x8]; 5567 u8 supported_issi_dw0[0x20]; 5568 }; 5569 5570 struct mlx5_ifc_query_issi_in_bits { 5571 u8 opcode[0x10]; 5572 u8 reserved_at_10[0x10]; 5573 5574 u8 reserved_at_20[0x10]; 5575 u8 op_mod[0x10]; 5576 5577 u8 reserved_at_40[0x40]; 5578 }; 5579 5580 struct mlx5_ifc_set_driver_version_out_bits { 5581 u8 status[0x8]; 5582 u8 reserved_0[0x18]; 5583 5584 u8 syndrome[0x20]; 5585 u8 reserved_1[0x40]; 5586 }; 5587 5588 struct mlx5_ifc_set_driver_version_in_bits { 5589 u8 opcode[0x10]; 5590 u8 reserved_0[0x10]; 5591 5592 u8 reserved_1[0x10]; 5593 u8 op_mod[0x10]; 5594 5595 u8 reserved_2[0x40]; 5596 u8 driver_version[64][0x8]; 5597 }; 5598 5599 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5600 u8 status[0x8]; 5601 u8 reserved_at_8[0x18]; 5602 5603 u8 syndrome[0x20]; 5604 5605 u8 reserved_at_40[0x40]; 5606 5607 struct mlx5_ifc_pkey_bits pkey[]; 5608 }; 5609 5610 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5611 u8 opcode[0x10]; 5612 u8 reserved_at_10[0x10]; 5613 5614 u8 reserved_at_20[0x10]; 5615 u8 op_mod[0x10]; 5616 5617 u8 other_vport[0x1]; 5618 u8 reserved_at_41[0xb]; 5619 u8 port_num[0x4]; 5620 u8 vport_number[0x10]; 5621 5622 u8 reserved_at_60[0x10]; 5623 u8 pkey_index[0x10]; 5624 }; 5625 5626 enum { 5627 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5628 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5629 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5630 }; 5631 5632 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5633 u8 status[0x8]; 5634 u8 reserved_at_8[0x18]; 5635 5636 u8 syndrome[0x20]; 5637 5638 u8 reserved_at_40[0x20]; 5639 5640 u8 gids_num[0x10]; 5641 u8 reserved_at_70[0x10]; 5642 5643 struct mlx5_ifc_array128_auto_bits gid[]; 5644 }; 5645 5646 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5647 u8 opcode[0x10]; 5648 u8 reserved_at_10[0x10]; 5649 5650 u8 reserved_at_20[0x10]; 5651 u8 op_mod[0x10]; 5652 5653 u8 other_vport[0x1]; 5654 u8 reserved_at_41[0xb]; 5655 u8 port_num[0x4]; 5656 u8 vport_number[0x10]; 5657 5658 u8 reserved_at_60[0x10]; 5659 u8 gid_index[0x10]; 5660 }; 5661 5662 struct mlx5_ifc_query_hca_vport_context_out_bits { 5663 u8 status[0x8]; 5664 u8 reserved_at_8[0x18]; 5665 5666 u8 syndrome[0x20]; 5667 5668 u8 reserved_at_40[0x40]; 5669 5670 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5671 }; 5672 5673 struct mlx5_ifc_query_hca_vport_context_in_bits { 5674 u8 opcode[0x10]; 5675 u8 reserved_at_10[0x10]; 5676 5677 u8 reserved_at_20[0x10]; 5678 u8 op_mod[0x10]; 5679 5680 u8 other_vport[0x1]; 5681 u8 reserved_at_41[0xb]; 5682 u8 port_num[0x4]; 5683 u8 vport_number[0x10]; 5684 5685 u8 reserved_at_60[0x20]; 5686 }; 5687 5688 struct mlx5_ifc_query_hca_cap_out_bits { 5689 u8 status[0x8]; 5690 u8 reserved_at_8[0x18]; 5691 5692 u8 syndrome[0x20]; 5693 5694 u8 reserved_at_40[0x40]; 5695 5696 union mlx5_ifc_hca_cap_union_bits capability; 5697 }; 5698 5699 struct mlx5_ifc_query_hca_cap_in_bits { 5700 u8 opcode[0x10]; 5701 u8 reserved_at_10[0x10]; 5702 5703 u8 reserved_at_20[0x10]; 5704 u8 op_mod[0x10]; 5705 5706 u8 other_function[0x1]; 5707 u8 reserved_at_41[0xf]; 5708 u8 function_id[0x10]; 5709 5710 u8 reserved_at_60[0x20]; 5711 }; 5712 5713 struct mlx5_ifc_other_hca_cap_bits { 5714 u8 roce[0x1]; 5715 u8 reserved_at_1[0x27f]; 5716 }; 5717 5718 struct mlx5_ifc_query_other_hca_cap_out_bits { 5719 u8 status[0x8]; 5720 u8 reserved_at_8[0x18]; 5721 5722 u8 syndrome[0x20]; 5723 5724 u8 reserved_at_40[0x40]; 5725 5726 struct mlx5_ifc_other_hca_cap_bits other_capability; 5727 }; 5728 5729 struct mlx5_ifc_query_other_hca_cap_in_bits { 5730 u8 opcode[0x10]; 5731 u8 reserved_at_10[0x10]; 5732 5733 u8 reserved_at_20[0x10]; 5734 u8 op_mod[0x10]; 5735 5736 u8 reserved_at_40[0x10]; 5737 u8 function_id[0x10]; 5738 5739 u8 reserved_at_60[0x20]; 5740 }; 5741 5742 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5743 u8 status[0x8]; 5744 u8 reserved_at_8[0x18]; 5745 5746 u8 syndrome[0x20]; 5747 5748 u8 reserved_at_40[0x40]; 5749 }; 5750 5751 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5752 u8 opcode[0x10]; 5753 u8 reserved_at_10[0x10]; 5754 5755 u8 reserved_at_20[0x10]; 5756 u8 op_mod[0x10]; 5757 5758 u8 reserved_at_40[0x10]; 5759 u8 function_id[0x10]; 5760 u8 field_select[0x20]; 5761 5762 struct mlx5_ifc_other_hca_cap_bits other_capability; 5763 }; 5764 5765 struct mlx5_ifc_flow_table_context_bits { 5766 u8 reformat_en[0x1]; 5767 u8 decap_en[0x1]; 5768 u8 sw_owner[0x1]; 5769 u8 termination_table[0x1]; 5770 u8 table_miss_action[0x4]; 5771 u8 level[0x8]; 5772 u8 reserved_at_10[0x8]; 5773 u8 log_size[0x8]; 5774 5775 u8 reserved_at_20[0x8]; 5776 u8 table_miss_id[0x18]; 5777 5778 u8 reserved_at_40[0x8]; 5779 u8 lag_master_next_table_id[0x18]; 5780 5781 u8 reserved_at_60[0x60]; 5782 5783 u8 sw_owner_icm_root_1[0x40]; 5784 5785 u8 sw_owner_icm_root_0[0x40]; 5786 5787 }; 5788 5789 struct mlx5_ifc_query_flow_table_out_bits { 5790 u8 status[0x8]; 5791 u8 reserved_at_8[0x18]; 5792 5793 u8 syndrome[0x20]; 5794 5795 u8 reserved_at_40[0x80]; 5796 5797 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5798 }; 5799 5800 struct mlx5_ifc_query_flow_table_in_bits { 5801 u8 opcode[0x10]; 5802 u8 reserved_at_10[0x10]; 5803 5804 u8 reserved_at_20[0x10]; 5805 u8 op_mod[0x10]; 5806 5807 u8 reserved_at_40[0x40]; 5808 5809 u8 table_type[0x8]; 5810 u8 reserved_at_88[0x18]; 5811 5812 u8 reserved_at_a0[0x8]; 5813 u8 table_id[0x18]; 5814 5815 u8 reserved_at_c0[0x140]; 5816 }; 5817 5818 struct mlx5_ifc_query_fte_out_bits { 5819 u8 status[0x8]; 5820 u8 reserved_at_8[0x18]; 5821 5822 u8 syndrome[0x20]; 5823 5824 u8 reserved_at_40[0x1c0]; 5825 5826 struct mlx5_ifc_flow_context_bits flow_context; 5827 }; 5828 5829 struct mlx5_ifc_query_fte_in_bits { 5830 u8 opcode[0x10]; 5831 u8 reserved_at_10[0x10]; 5832 5833 u8 reserved_at_20[0x10]; 5834 u8 op_mod[0x10]; 5835 5836 u8 reserved_at_40[0x40]; 5837 5838 u8 table_type[0x8]; 5839 u8 reserved_at_88[0x18]; 5840 5841 u8 reserved_at_a0[0x8]; 5842 u8 table_id[0x18]; 5843 5844 u8 reserved_at_c0[0x40]; 5845 5846 u8 flow_index[0x20]; 5847 5848 u8 reserved_at_120[0xe0]; 5849 }; 5850 5851 struct mlx5_ifc_match_definer_format_0_bits { 5852 u8 reserved_at_0[0x100]; 5853 5854 u8 metadata_reg_c_0[0x20]; 5855 5856 u8 metadata_reg_c_1[0x20]; 5857 5858 u8 outer_dmac_47_16[0x20]; 5859 5860 u8 outer_dmac_15_0[0x10]; 5861 u8 outer_ethertype[0x10]; 5862 5863 u8 reserved_at_180[0x1]; 5864 u8 sx_sniffer[0x1]; 5865 u8 functional_lb[0x1]; 5866 u8 outer_ip_frag[0x1]; 5867 u8 outer_qp_type[0x2]; 5868 u8 outer_encap_type[0x2]; 5869 u8 port_number[0x2]; 5870 u8 outer_l3_type[0x2]; 5871 u8 outer_l4_type[0x2]; 5872 u8 outer_first_vlan_type[0x2]; 5873 u8 outer_first_vlan_prio[0x3]; 5874 u8 outer_first_vlan_cfi[0x1]; 5875 u8 outer_first_vlan_vid[0xc]; 5876 5877 u8 outer_l4_type_ext[0x4]; 5878 u8 reserved_at_1a4[0x2]; 5879 u8 outer_ipsec_layer[0x2]; 5880 u8 outer_l2_type[0x2]; 5881 u8 force_lb[0x1]; 5882 u8 outer_l2_ok[0x1]; 5883 u8 outer_l3_ok[0x1]; 5884 u8 outer_l4_ok[0x1]; 5885 u8 outer_second_vlan_type[0x2]; 5886 u8 outer_second_vlan_prio[0x3]; 5887 u8 outer_second_vlan_cfi[0x1]; 5888 u8 outer_second_vlan_vid[0xc]; 5889 5890 u8 outer_smac_47_16[0x20]; 5891 5892 u8 outer_smac_15_0[0x10]; 5893 u8 inner_ipv4_checksum_ok[0x1]; 5894 u8 inner_l4_checksum_ok[0x1]; 5895 u8 outer_ipv4_checksum_ok[0x1]; 5896 u8 outer_l4_checksum_ok[0x1]; 5897 u8 inner_l3_ok[0x1]; 5898 u8 inner_l4_ok[0x1]; 5899 u8 outer_l3_ok_duplicate[0x1]; 5900 u8 outer_l4_ok_duplicate[0x1]; 5901 u8 outer_tcp_cwr[0x1]; 5902 u8 outer_tcp_ece[0x1]; 5903 u8 outer_tcp_urg[0x1]; 5904 u8 outer_tcp_ack[0x1]; 5905 u8 outer_tcp_psh[0x1]; 5906 u8 outer_tcp_rst[0x1]; 5907 u8 outer_tcp_syn[0x1]; 5908 u8 outer_tcp_fin[0x1]; 5909 }; 5910 5911 struct mlx5_ifc_match_definer_format_22_bits { 5912 u8 reserved_at_0[0x100]; 5913 5914 u8 outer_ip_src_addr[0x20]; 5915 5916 u8 outer_ip_dest_addr[0x20]; 5917 5918 u8 outer_l4_sport[0x10]; 5919 u8 outer_l4_dport[0x10]; 5920 5921 u8 reserved_at_160[0x1]; 5922 u8 sx_sniffer[0x1]; 5923 u8 functional_lb[0x1]; 5924 u8 outer_ip_frag[0x1]; 5925 u8 outer_qp_type[0x2]; 5926 u8 outer_encap_type[0x2]; 5927 u8 port_number[0x2]; 5928 u8 outer_l3_type[0x2]; 5929 u8 outer_l4_type[0x2]; 5930 u8 outer_first_vlan_type[0x2]; 5931 u8 outer_first_vlan_prio[0x3]; 5932 u8 outer_first_vlan_cfi[0x1]; 5933 u8 outer_first_vlan_vid[0xc]; 5934 5935 u8 metadata_reg_c_0[0x20]; 5936 5937 u8 outer_dmac_47_16[0x20]; 5938 5939 u8 outer_smac_47_16[0x20]; 5940 5941 u8 outer_smac_15_0[0x10]; 5942 u8 outer_dmac_15_0[0x10]; 5943 }; 5944 5945 struct mlx5_ifc_match_definer_format_23_bits { 5946 u8 reserved_at_0[0x100]; 5947 5948 u8 inner_ip_src_addr[0x20]; 5949 5950 u8 inner_ip_dest_addr[0x20]; 5951 5952 u8 inner_l4_sport[0x10]; 5953 u8 inner_l4_dport[0x10]; 5954 5955 u8 reserved_at_160[0x1]; 5956 u8 sx_sniffer[0x1]; 5957 u8 functional_lb[0x1]; 5958 u8 inner_ip_frag[0x1]; 5959 u8 inner_qp_type[0x2]; 5960 u8 inner_encap_type[0x2]; 5961 u8 port_number[0x2]; 5962 u8 inner_l3_type[0x2]; 5963 u8 inner_l4_type[0x2]; 5964 u8 inner_first_vlan_type[0x2]; 5965 u8 inner_first_vlan_prio[0x3]; 5966 u8 inner_first_vlan_cfi[0x1]; 5967 u8 inner_first_vlan_vid[0xc]; 5968 5969 u8 tunnel_header_0[0x20]; 5970 5971 u8 inner_dmac_47_16[0x20]; 5972 5973 u8 inner_smac_47_16[0x20]; 5974 5975 u8 inner_smac_15_0[0x10]; 5976 u8 inner_dmac_15_0[0x10]; 5977 }; 5978 5979 struct mlx5_ifc_match_definer_format_29_bits { 5980 u8 reserved_at_0[0xc0]; 5981 5982 u8 outer_ip_dest_addr[0x80]; 5983 5984 u8 outer_ip_src_addr[0x80]; 5985 5986 u8 outer_l4_sport[0x10]; 5987 u8 outer_l4_dport[0x10]; 5988 5989 u8 reserved_at_1e0[0x20]; 5990 }; 5991 5992 struct mlx5_ifc_match_definer_format_30_bits { 5993 u8 reserved_at_0[0xa0]; 5994 5995 u8 outer_ip_dest_addr[0x80]; 5996 5997 u8 outer_ip_src_addr[0x80]; 5998 5999 u8 outer_dmac_47_16[0x20]; 6000 6001 u8 outer_smac_47_16[0x20]; 6002 6003 u8 outer_smac_15_0[0x10]; 6004 u8 outer_dmac_15_0[0x10]; 6005 }; 6006 6007 struct mlx5_ifc_match_definer_format_31_bits { 6008 u8 reserved_at_0[0xc0]; 6009 6010 u8 inner_ip_dest_addr[0x80]; 6011 6012 u8 inner_ip_src_addr[0x80]; 6013 6014 u8 inner_l4_sport[0x10]; 6015 u8 inner_l4_dport[0x10]; 6016 6017 u8 reserved_at_1e0[0x20]; 6018 }; 6019 6020 struct mlx5_ifc_match_definer_format_32_bits { 6021 u8 reserved_at_0[0xa0]; 6022 6023 u8 inner_ip_dest_addr[0x80]; 6024 6025 u8 inner_ip_src_addr[0x80]; 6026 6027 u8 inner_dmac_47_16[0x20]; 6028 6029 u8 inner_smac_47_16[0x20]; 6030 6031 u8 inner_smac_15_0[0x10]; 6032 u8 inner_dmac_15_0[0x10]; 6033 }; 6034 6035 struct mlx5_ifc_match_definer_bits { 6036 u8 modify_field_select[0x40]; 6037 6038 u8 reserved_at_40[0x40]; 6039 6040 u8 reserved_at_80[0x10]; 6041 u8 format_id[0x10]; 6042 6043 u8 reserved_at_a0[0x160]; 6044 6045 u8 match_mask[16][0x20]; 6046 }; 6047 6048 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6049 u8 opcode[0x10]; 6050 u8 uid[0x10]; 6051 6052 u8 vhca_tunnel_id[0x10]; 6053 u8 obj_type[0x10]; 6054 6055 u8 obj_id[0x20]; 6056 6057 u8 reserved_at_60[0x3]; 6058 u8 log_obj_range[0x5]; 6059 u8 reserved_at_68[0x18]; 6060 }; 6061 6062 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6063 u8 status[0x8]; 6064 u8 reserved_at_8[0x18]; 6065 6066 u8 syndrome[0x20]; 6067 6068 u8 obj_id[0x20]; 6069 6070 u8 reserved_at_60[0x20]; 6071 }; 6072 6073 struct mlx5_ifc_create_match_definer_in_bits { 6074 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6075 6076 struct mlx5_ifc_match_definer_bits obj_context; 6077 }; 6078 6079 struct mlx5_ifc_create_match_definer_out_bits { 6080 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6081 }; 6082 6083 enum { 6084 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6085 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6086 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6087 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6088 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6089 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6090 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6091 }; 6092 6093 struct mlx5_ifc_query_flow_group_out_bits { 6094 u8 status[0x8]; 6095 u8 reserved_at_8[0x18]; 6096 6097 u8 syndrome[0x20]; 6098 6099 u8 reserved_at_40[0xa0]; 6100 6101 u8 start_flow_index[0x20]; 6102 6103 u8 reserved_at_100[0x20]; 6104 6105 u8 end_flow_index[0x20]; 6106 6107 u8 reserved_at_140[0xa0]; 6108 6109 u8 reserved_at_1e0[0x18]; 6110 u8 match_criteria_enable[0x8]; 6111 6112 struct mlx5_ifc_fte_match_param_bits match_criteria; 6113 6114 u8 reserved_at_1200[0xe00]; 6115 }; 6116 6117 struct mlx5_ifc_query_flow_group_in_bits { 6118 u8 opcode[0x10]; 6119 u8 reserved_at_10[0x10]; 6120 6121 u8 reserved_at_20[0x10]; 6122 u8 op_mod[0x10]; 6123 6124 u8 reserved_at_40[0x40]; 6125 6126 u8 table_type[0x8]; 6127 u8 reserved_at_88[0x18]; 6128 6129 u8 reserved_at_a0[0x8]; 6130 u8 table_id[0x18]; 6131 6132 u8 group_id[0x20]; 6133 6134 u8 reserved_at_e0[0x120]; 6135 }; 6136 6137 struct mlx5_ifc_query_flow_counter_out_bits { 6138 u8 status[0x8]; 6139 u8 reserved_at_8[0x18]; 6140 6141 u8 syndrome[0x20]; 6142 6143 u8 reserved_at_40[0x40]; 6144 6145 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6146 }; 6147 6148 struct mlx5_ifc_query_flow_counter_in_bits { 6149 u8 opcode[0x10]; 6150 u8 reserved_at_10[0x10]; 6151 6152 u8 reserved_at_20[0x10]; 6153 u8 op_mod[0x10]; 6154 6155 u8 reserved_at_40[0x80]; 6156 6157 u8 clear[0x1]; 6158 u8 reserved_at_c1[0xf]; 6159 u8 num_of_counters[0x10]; 6160 6161 u8 flow_counter_id[0x20]; 6162 }; 6163 6164 struct mlx5_ifc_query_esw_vport_context_out_bits { 6165 u8 status[0x8]; 6166 u8 reserved_at_8[0x18]; 6167 6168 u8 syndrome[0x20]; 6169 6170 u8 reserved_at_40[0x40]; 6171 6172 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6173 }; 6174 6175 struct mlx5_ifc_query_esw_vport_context_in_bits { 6176 u8 opcode[0x10]; 6177 u8 reserved_at_10[0x10]; 6178 6179 u8 reserved_at_20[0x10]; 6180 u8 op_mod[0x10]; 6181 6182 u8 other_vport[0x1]; 6183 u8 reserved_at_41[0xf]; 6184 u8 vport_number[0x10]; 6185 6186 u8 reserved_at_60[0x20]; 6187 }; 6188 6189 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6190 u8 status[0x8]; 6191 u8 reserved_at_8[0x18]; 6192 6193 u8 syndrome[0x20]; 6194 6195 u8 reserved_at_40[0x40]; 6196 }; 6197 6198 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6199 u8 reserved_at_0[0x1b]; 6200 u8 fdb_to_vport_reg_c_id[0x1]; 6201 u8 vport_cvlan_insert[0x1]; 6202 u8 vport_svlan_insert[0x1]; 6203 u8 vport_cvlan_strip[0x1]; 6204 u8 vport_svlan_strip[0x1]; 6205 }; 6206 6207 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6208 u8 opcode[0x10]; 6209 u8 reserved_at_10[0x10]; 6210 6211 u8 reserved_at_20[0x10]; 6212 u8 op_mod[0x10]; 6213 6214 u8 other_vport[0x1]; 6215 u8 reserved_at_41[0xf]; 6216 u8 vport_number[0x10]; 6217 6218 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6219 6220 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6221 }; 6222 6223 struct mlx5_ifc_query_eq_out_bits { 6224 u8 status[0x8]; 6225 u8 reserved_at_8[0x18]; 6226 6227 u8 syndrome[0x20]; 6228 6229 u8 reserved_at_40[0x40]; 6230 6231 struct mlx5_ifc_eqc_bits eq_context_entry; 6232 6233 u8 reserved_at_280[0x40]; 6234 6235 u8 event_bitmask[0x40]; 6236 6237 u8 reserved_at_300[0x580]; 6238 6239 u8 pas[][0x40]; 6240 }; 6241 6242 struct mlx5_ifc_query_eq_in_bits { 6243 u8 opcode[0x10]; 6244 u8 reserved_at_10[0x10]; 6245 6246 u8 reserved_at_20[0x10]; 6247 u8 op_mod[0x10]; 6248 6249 u8 reserved_at_40[0x18]; 6250 u8 eq_number[0x8]; 6251 6252 u8 reserved_at_60[0x20]; 6253 }; 6254 6255 struct mlx5_ifc_packet_reformat_context_in_bits { 6256 u8 reformat_type[0x8]; 6257 u8 reserved_at_8[0x4]; 6258 u8 reformat_param_0[0x4]; 6259 u8 reserved_at_10[0x6]; 6260 u8 reformat_data_size[0xa]; 6261 6262 u8 reformat_param_1[0x8]; 6263 u8 reserved_at_28[0x8]; 6264 u8 reformat_data[2][0x8]; 6265 6266 u8 more_reformat_data[][0x8]; 6267 }; 6268 6269 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6270 u8 status[0x8]; 6271 u8 reserved_at_8[0x18]; 6272 6273 u8 syndrome[0x20]; 6274 6275 u8 reserved_at_40[0xa0]; 6276 6277 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6278 }; 6279 6280 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6281 u8 opcode[0x10]; 6282 u8 reserved_at_10[0x10]; 6283 6284 u8 reserved_at_20[0x10]; 6285 u8 op_mod[0x10]; 6286 6287 u8 packet_reformat_id[0x20]; 6288 6289 u8 reserved_at_60[0xa0]; 6290 }; 6291 6292 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6293 u8 status[0x8]; 6294 u8 reserved_at_8[0x18]; 6295 6296 u8 syndrome[0x20]; 6297 6298 u8 packet_reformat_id[0x20]; 6299 6300 u8 reserved_at_60[0x20]; 6301 }; 6302 6303 enum { 6304 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6305 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6306 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6307 }; 6308 6309 enum mlx5_reformat_ctx_type { 6310 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6311 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6312 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6313 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6314 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6315 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6316 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6317 }; 6318 6319 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6320 u8 opcode[0x10]; 6321 u8 reserved_at_10[0x10]; 6322 6323 u8 reserved_at_20[0x10]; 6324 u8 op_mod[0x10]; 6325 6326 u8 reserved_at_40[0xa0]; 6327 6328 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6329 }; 6330 6331 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6332 u8 status[0x8]; 6333 u8 reserved_at_8[0x18]; 6334 6335 u8 syndrome[0x20]; 6336 6337 u8 reserved_at_40[0x40]; 6338 }; 6339 6340 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6341 u8 opcode[0x10]; 6342 u8 reserved_at_10[0x10]; 6343 6344 u8 reserved_20[0x10]; 6345 u8 op_mod[0x10]; 6346 6347 u8 packet_reformat_id[0x20]; 6348 6349 u8 reserved_60[0x20]; 6350 }; 6351 6352 struct mlx5_ifc_set_action_in_bits { 6353 u8 action_type[0x4]; 6354 u8 field[0xc]; 6355 u8 reserved_at_10[0x3]; 6356 u8 offset[0x5]; 6357 u8 reserved_at_18[0x3]; 6358 u8 length[0x5]; 6359 6360 u8 data[0x20]; 6361 }; 6362 6363 struct mlx5_ifc_add_action_in_bits { 6364 u8 action_type[0x4]; 6365 u8 field[0xc]; 6366 u8 reserved_at_10[0x10]; 6367 6368 u8 data[0x20]; 6369 }; 6370 6371 struct mlx5_ifc_copy_action_in_bits { 6372 u8 action_type[0x4]; 6373 u8 src_field[0xc]; 6374 u8 reserved_at_10[0x3]; 6375 u8 src_offset[0x5]; 6376 u8 reserved_at_18[0x3]; 6377 u8 length[0x5]; 6378 6379 u8 reserved_at_20[0x4]; 6380 u8 dst_field[0xc]; 6381 u8 reserved_at_30[0x3]; 6382 u8 dst_offset[0x5]; 6383 u8 reserved_at_38[0x8]; 6384 }; 6385 6386 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6387 struct mlx5_ifc_set_action_in_bits set_action_in; 6388 struct mlx5_ifc_add_action_in_bits add_action_in; 6389 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6390 u8 reserved_at_0[0x40]; 6391 }; 6392 6393 enum { 6394 MLX5_ACTION_TYPE_SET = 0x1, 6395 MLX5_ACTION_TYPE_ADD = 0x2, 6396 MLX5_ACTION_TYPE_COPY = 0x3, 6397 }; 6398 6399 enum { 6400 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6401 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6402 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6403 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6404 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6405 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6406 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6407 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6408 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6409 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6410 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6411 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6412 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6413 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6414 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6415 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6416 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6417 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6418 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6419 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6420 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6421 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6422 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6423 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6424 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6425 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6426 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6427 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6428 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6429 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6430 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6431 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6432 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6433 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6434 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6435 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6436 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6437 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6438 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6439 }; 6440 6441 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6442 u8 status[0x8]; 6443 u8 reserved_at_8[0x18]; 6444 6445 u8 syndrome[0x20]; 6446 6447 u8 modify_header_id[0x20]; 6448 6449 u8 reserved_at_60[0x20]; 6450 }; 6451 6452 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6453 u8 opcode[0x10]; 6454 u8 reserved_at_10[0x10]; 6455 6456 u8 reserved_at_20[0x10]; 6457 u8 op_mod[0x10]; 6458 6459 u8 reserved_at_40[0x20]; 6460 6461 u8 table_type[0x8]; 6462 u8 reserved_at_68[0x10]; 6463 u8 num_of_actions[0x8]; 6464 6465 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6466 }; 6467 6468 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6469 u8 status[0x8]; 6470 u8 reserved_at_8[0x18]; 6471 6472 u8 syndrome[0x20]; 6473 6474 u8 reserved_at_40[0x40]; 6475 }; 6476 6477 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6478 u8 opcode[0x10]; 6479 u8 reserved_at_10[0x10]; 6480 6481 u8 reserved_at_20[0x10]; 6482 u8 op_mod[0x10]; 6483 6484 u8 modify_header_id[0x20]; 6485 6486 u8 reserved_at_60[0x20]; 6487 }; 6488 6489 struct mlx5_ifc_query_modify_header_context_in_bits { 6490 u8 opcode[0x10]; 6491 u8 uid[0x10]; 6492 6493 u8 reserved_at_20[0x10]; 6494 u8 op_mod[0x10]; 6495 6496 u8 modify_header_id[0x20]; 6497 6498 u8 reserved_at_60[0xa0]; 6499 }; 6500 6501 struct mlx5_ifc_query_dct_out_bits { 6502 u8 status[0x8]; 6503 u8 reserved_at_8[0x18]; 6504 6505 u8 syndrome[0x20]; 6506 6507 u8 reserved_at_40[0x40]; 6508 6509 struct mlx5_ifc_dctc_bits dct_context_entry; 6510 6511 u8 reserved_at_280[0x180]; 6512 }; 6513 6514 struct mlx5_ifc_query_dct_in_bits { 6515 u8 opcode[0x10]; 6516 u8 reserved_at_10[0x10]; 6517 6518 u8 reserved_at_20[0x10]; 6519 u8 op_mod[0x10]; 6520 6521 u8 reserved_at_40[0x8]; 6522 u8 dctn[0x18]; 6523 6524 u8 reserved_at_60[0x20]; 6525 }; 6526 6527 struct mlx5_ifc_query_cq_out_bits { 6528 u8 status[0x8]; 6529 u8 reserved_at_8[0x18]; 6530 6531 u8 syndrome[0x20]; 6532 6533 u8 reserved_at_40[0x40]; 6534 6535 struct mlx5_ifc_cqc_bits cq_context; 6536 6537 u8 reserved_at_280[0x600]; 6538 6539 u8 pas[][0x40]; 6540 }; 6541 6542 struct mlx5_ifc_query_cq_in_bits { 6543 u8 opcode[0x10]; 6544 u8 reserved_at_10[0x10]; 6545 6546 u8 reserved_at_20[0x10]; 6547 u8 op_mod[0x10]; 6548 6549 u8 reserved_at_40[0x8]; 6550 u8 cqn[0x18]; 6551 6552 u8 reserved_at_60[0x20]; 6553 }; 6554 6555 struct mlx5_ifc_query_cong_status_out_bits { 6556 u8 status[0x8]; 6557 u8 reserved_at_8[0x18]; 6558 6559 u8 syndrome[0x20]; 6560 6561 u8 reserved_at_40[0x20]; 6562 6563 u8 enable[0x1]; 6564 u8 tag_enable[0x1]; 6565 u8 reserved_at_62[0x1e]; 6566 }; 6567 6568 struct mlx5_ifc_query_cong_status_in_bits { 6569 u8 opcode[0x10]; 6570 u8 reserved_at_10[0x10]; 6571 6572 u8 reserved_at_20[0x10]; 6573 u8 op_mod[0x10]; 6574 6575 u8 reserved_at_40[0x18]; 6576 u8 priority[0x4]; 6577 u8 cong_protocol[0x4]; 6578 6579 u8 reserved_at_60[0x20]; 6580 }; 6581 6582 struct mlx5_ifc_query_cong_statistics_out_bits { 6583 u8 status[0x8]; 6584 u8 reserved_at_8[0x18]; 6585 6586 u8 syndrome[0x20]; 6587 6588 u8 reserved_at_40[0x40]; 6589 6590 u8 rp_cur_flows[0x20]; 6591 6592 u8 sum_flows[0x20]; 6593 6594 u8 rp_cnp_ignored_high[0x20]; 6595 6596 u8 rp_cnp_ignored_low[0x20]; 6597 6598 u8 rp_cnp_handled_high[0x20]; 6599 6600 u8 rp_cnp_handled_low[0x20]; 6601 6602 u8 reserved_at_140[0x100]; 6603 6604 u8 time_stamp_high[0x20]; 6605 6606 u8 time_stamp_low[0x20]; 6607 6608 u8 accumulators_period[0x20]; 6609 6610 u8 np_ecn_marked_roce_packets_high[0x20]; 6611 6612 u8 np_ecn_marked_roce_packets_low[0x20]; 6613 6614 u8 np_cnp_sent_high[0x20]; 6615 6616 u8 np_cnp_sent_low[0x20]; 6617 6618 u8 reserved_at_320[0x560]; 6619 }; 6620 6621 struct mlx5_ifc_query_cong_statistics_in_bits { 6622 u8 opcode[0x10]; 6623 u8 reserved_at_10[0x10]; 6624 6625 u8 reserved_at_20[0x10]; 6626 u8 op_mod[0x10]; 6627 6628 u8 clear[0x1]; 6629 u8 reserved_at_41[0x1f]; 6630 6631 u8 reserved_at_60[0x20]; 6632 }; 6633 6634 struct mlx5_ifc_query_cong_params_out_bits { 6635 u8 status[0x8]; 6636 u8 reserved_at_8[0x18]; 6637 6638 u8 syndrome[0x20]; 6639 6640 u8 reserved_at_40[0x40]; 6641 6642 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6643 }; 6644 6645 struct mlx5_ifc_query_cong_params_in_bits { 6646 u8 opcode[0x10]; 6647 u8 reserved_at_10[0x10]; 6648 6649 u8 reserved_at_20[0x10]; 6650 u8 op_mod[0x10]; 6651 6652 u8 reserved_at_40[0x1c]; 6653 u8 cong_protocol[0x4]; 6654 6655 u8 reserved_at_60[0x20]; 6656 }; 6657 6658 struct mlx5_ifc_query_adapter_out_bits { 6659 u8 status[0x8]; 6660 u8 reserved_at_8[0x18]; 6661 6662 u8 syndrome[0x20]; 6663 6664 u8 reserved_at_40[0x40]; 6665 6666 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6667 }; 6668 6669 struct mlx5_ifc_query_adapter_in_bits { 6670 u8 opcode[0x10]; 6671 u8 reserved_at_10[0x10]; 6672 6673 u8 reserved_at_20[0x10]; 6674 u8 op_mod[0x10]; 6675 6676 u8 reserved_at_40[0x40]; 6677 }; 6678 6679 struct mlx5_ifc_qp_2rst_out_bits { 6680 u8 status[0x8]; 6681 u8 reserved_at_8[0x18]; 6682 6683 u8 syndrome[0x20]; 6684 6685 u8 reserved_at_40[0x40]; 6686 }; 6687 6688 struct mlx5_ifc_qp_2rst_in_bits { 6689 u8 opcode[0x10]; 6690 u8 uid[0x10]; 6691 6692 u8 reserved_at_20[0x10]; 6693 u8 op_mod[0x10]; 6694 6695 u8 reserved_at_40[0x8]; 6696 u8 qpn[0x18]; 6697 6698 u8 reserved_at_60[0x20]; 6699 }; 6700 6701 struct mlx5_ifc_qp_2err_out_bits { 6702 u8 status[0x8]; 6703 u8 reserved_at_8[0x18]; 6704 6705 u8 syndrome[0x20]; 6706 6707 u8 reserved_at_40[0x40]; 6708 }; 6709 6710 struct mlx5_ifc_qp_2err_in_bits { 6711 u8 opcode[0x10]; 6712 u8 uid[0x10]; 6713 6714 u8 reserved_at_20[0x10]; 6715 u8 op_mod[0x10]; 6716 6717 u8 reserved_at_40[0x8]; 6718 u8 qpn[0x18]; 6719 6720 u8 reserved_at_60[0x20]; 6721 }; 6722 6723 struct mlx5_ifc_page_fault_resume_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_at_8[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 reserved_at_40[0x40]; 6730 }; 6731 6732 struct mlx5_ifc_page_fault_resume_in_bits { 6733 u8 opcode[0x10]; 6734 u8 reserved_at_10[0x10]; 6735 6736 u8 reserved_at_20[0x10]; 6737 u8 op_mod[0x10]; 6738 6739 u8 error[0x1]; 6740 u8 reserved_at_41[0x4]; 6741 u8 page_fault_type[0x3]; 6742 u8 wq_number[0x18]; 6743 6744 u8 reserved_at_60[0x8]; 6745 u8 token[0x18]; 6746 }; 6747 6748 struct mlx5_ifc_nop_out_bits { 6749 u8 status[0x8]; 6750 u8 reserved_at_8[0x18]; 6751 6752 u8 syndrome[0x20]; 6753 6754 u8 reserved_at_40[0x40]; 6755 }; 6756 6757 struct mlx5_ifc_nop_in_bits { 6758 u8 opcode[0x10]; 6759 u8 reserved_at_10[0x10]; 6760 6761 u8 reserved_at_20[0x10]; 6762 u8 op_mod[0x10]; 6763 6764 u8 reserved_at_40[0x40]; 6765 }; 6766 6767 struct mlx5_ifc_modify_vport_state_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_at_8[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 reserved_at_40[0x40]; 6774 }; 6775 6776 struct mlx5_ifc_modify_vport_state_in_bits { 6777 u8 opcode[0x10]; 6778 u8 reserved_at_10[0x10]; 6779 6780 u8 reserved_at_20[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 other_vport[0x1]; 6784 u8 reserved_at_41[0xf]; 6785 u8 vport_number[0x10]; 6786 6787 u8 reserved_at_60[0x18]; 6788 u8 admin_state[0x4]; 6789 u8 reserved_at_7c[0x4]; 6790 }; 6791 6792 struct mlx5_ifc_modify_tis_out_bits { 6793 u8 status[0x8]; 6794 u8 reserved_at_8[0x18]; 6795 6796 u8 syndrome[0x20]; 6797 6798 u8 reserved_at_40[0x40]; 6799 }; 6800 6801 struct mlx5_ifc_modify_tis_bitmask_bits { 6802 u8 reserved_at_0[0x20]; 6803 6804 u8 reserved_at_20[0x1d]; 6805 u8 lag_tx_port_affinity[0x1]; 6806 u8 strict_lag_tx_port_affinity[0x1]; 6807 u8 prio[0x1]; 6808 }; 6809 6810 struct mlx5_ifc_modify_tis_in_bits { 6811 u8 opcode[0x10]; 6812 u8 uid[0x10]; 6813 6814 u8 reserved_at_20[0x10]; 6815 u8 op_mod[0x10]; 6816 6817 u8 reserved_at_40[0x8]; 6818 u8 tisn[0x18]; 6819 6820 u8 reserved_at_60[0x20]; 6821 6822 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6823 6824 u8 reserved_at_c0[0x40]; 6825 6826 struct mlx5_ifc_tisc_bits ctx; 6827 }; 6828 6829 struct mlx5_ifc_modify_tir_bitmask_bits { 6830 u8 reserved_at_0[0x20]; 6831 6832 u8 reserved_at_20[0x1b]; 6833 u8 self_lb_en[0x1]; 6834 u8 reserved_at_3c[0x1]; 6835 u8 hash[0x1]; 6836 u8 reserved_at_3e[0x1]; 6837 u8 packet_merge[0x1]; 6838 }; 6839 6840 struct mlx5_ifc_modify_tir_out_bits { 6841 u8 status[0x8]; 6842 u8 reserved_at_8[0x18]; 6843 6844 u8 syndrome[0x20]; 6845 6846 u8 reserved_at_40[0x40]; 6847 }; 6848 6849 struct mlx5_ifc_modify_tir_in_bits { 6850 u8 opcode[0x10]; 6851 u8 uid[0x10]; 6852 6853 u8 reserved_at_20[0x10]; 6854 u8 op_mod[0x10]; 6855 6856 u8 reserved_at_40[0x8]; 6857 u8 tirn[0x18]; 6858 6859 u8 reserved_at_60[0x20]; 6860 6861 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6862 6863 u8 reserved_at_c0[0x40]; 6864 6865 struct mlx5_ifc_tirc_bits ctx; 6866 }; 6867 6868 struct mlx5_ifc_modify_sq_out_bits { 6869 u8 status[0x8]; 6870 u8 reserved_at_8[0x18]; 6871 6872 u8 syndrome[0x20]; 6873 6874 u8 reserved_at_40[0x40]; 6875 }; 6876 6877 struct mlx5_ifc_modify_sq_in_bits { 6878 u8 opcode[0x10]; 6879 u8 uid[0x10]; 6880 6881 u8 reserved_at_20[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 sq_state[0x4]; 6885 u8 reserved_at_44[0x4]; 6886 u8 sqn[0x18]; 6887 6888 u8 reserved_at_60[0x20]; 6889 6890 u8 modify_bitmask[0x40]; 6891 6892 u8 reserved_at_c0[0x40]; 6893 6894 struct mlx5_ifc_sqc_bits ctx; 6895 }; 6896 6897 struct mlx5_ifc_modify_scheduling_element_out_bits { 6898 u8 status[0x8]; 6899 u8 reserved_at_8[0x18]; 6900 6901 u8 syndrome[0x20]; 6902 6903 u8 reserved_at_40[0x1c0]; 6904 }; 6905 6906 enum { 6907 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6908 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6909 }; 6910 6911 struct mlx5_ifc_modify_scheduling_element_in_bits { 6912 u8 opcode[0x10]; 6913 u8 reserved_at_10[0x10]; 6914 6915 u8 reserved_at_20[0x10]; 6916 u8 op_mod[0x10]; 6917 6918 u8 scheduling_hierarchy[0x8]; 6919 u8 reserved_at_48[0x18]; 6920 6921 u8 scheduling_element_id[0x20]; 6922 6923 u8 reserved_at_80[0x20]; 6924 6925 u8 modify_bitmask[0x20]; 6926 6927 u8 reserved_at_c0[0x40]; 6928 6929 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6930 6931 u8 reserved_at_300[0x100]; 6932 }; 6933 6934 struct mlx5_ifc_modify_rqt_out_bits { 6935 u8 status[0x8]; 6936 u8 reserved_at_8[0x18]; 6937 6938 u8 syndrome[0x20]; 6939 6940 u8 reserved_at_40[0x40]; 6941 }; 6942 6943 struct mlx5_ifc_rqt_bitmask_bits { 6944 u8 reserved_at_0[0x20]; 6945 6946 u8 reserved_at_20[0x1f]; 6947 u8 rqn_list[0x1]; 6948 }; 6949 6950 struct mlx5_ifc_modify_rqt_in_bits { 6951 u8 opcode[0x10]; 6952 u8 uid[0x10]; 6953 6954 u8 reserved_at_20[0x10]; 6955 u8 op_mod[0x10]; 6956 6957 u8 reserved_at_40[0x8]; 6958 u8 rqtn[0x18]; 6959 6960 u8 reserved_at_60[0x20]; 6961 6962 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6963 6964 u8 reserved_at_c0[0x40]; 6965 6966 struct mlx5_ifc_rqtc_bits ctx; 6967 }; 6968 6969 struct mlx5_ifc_modify_rq_out_bits { 6970 u8 status[0x8]; 6971 u8 reserved_at_8[0x18]; 6972 6973 u8 syndrome[0x20]; 6974 6975 u8 reserved_at_40[0x40]; 6976 }; 6977 6978 enum { 6979 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6980 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6981 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6982 }; 6983 6984 struct mlx5_ifc_modify_rq_in_bits { 6985 u8 opcode[0x10]; 6986 u8 uid[0x10]; 6987 6988 u8 reserved_at_20[0x10]; 6989 u8 op_mod[0x10]; 6990 6991 u8 rq_state[0x4]; 6992 u8 reserved_at_44[0x4]; 6993 u8 rqn[0x18]; 6994 6995 u8 reserved_at_60[0x20]; 6996 6997 u8 modify_bitmask[0x40]; 6998 6999 u8 reserved_at_c0[0x40]; 7000 7001 struct mlx5_ifc_rqc_bits ctx; 7002 }; 7003 7004 struct mlx5_ifc_modify_rmp_out_bits { 7005 u8 status[0x8]; 7006 u8 reserved_at_8[0x18]; 7007 7008 u8 syndrome[0x20]; 7009 7010 u8 reserved_at_40[0x40]; 7011 }; 7012 7013 struct mlx5_ifc_rmp_bitmask_bits { 7014 u8 reserved_at_0[0x20]; 7015 7016 u8 reserved_at_20[0x1f]; 7017 u8 lwm[0x1]; 7018 }; 7019 7020 struct mlx5_ifc_modify_rmp_in_bits { 7021 u8 opcode[0x10]; 7022 u8 uid[0x10]; 7023 7024 u8 reserved_at_20[0x10]; 7025 u8 op_mod[0x10]; 7026 7027 u8 rmp_state[0x4]; 7028 u8 reserved_at_44[0x4]; 7029 u8 rmpn[0x18]; 7030 7031 u8 reserved_at_60[0x20]; 7032 7033 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7034 7035 u8 reserved_at_c0[0x40]; 7036 7037 struct mlx5_ifc_rmpc_bits ctx; 7038 }; 7039 7040 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7041 u8 status[0x8]; 7042 u8 reserved_at_8[0x18]; 7043 7044 u8 syndrome[0x20]; 7045 7046 u8 reserved_at_40[0x40]; 7047 }; 7048 7049 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7050 u8 reserved_at_0[0x12]; 7051 u8 affiliation[0x1]; 7052 u8 reserved_at_13[0x1]; 7053 u8 disable_uc_local_lb[0x1]; 7054 u8 disable_mc_local_lb[0x1]; 7055 u8 node_guid[0x1]; 7056 u8 port_guid[0x1]; 7057 u8 min_inline[0x1]; 7058 u8 mtu[0x1]; 7059 u8 change_event[0x1]; 7060 u8 promisc[0x1]; 7061 u8 permanent_address[0x1]; 7062 u8 addresses_list[0x1]; 7063 u8 roce_en[0x1]; 7064 u8 reserved_at_1f[0x1]; 7065 }; 7066 7067 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7068 u8 opcode[0x10]; 7069 u8 reserved_at_10[0x10]; 7070 7071 u8 reserved_at_20[0x10]; 7072 u8 op_mod[0x10]; 7073 7074 u8 other_vport[0x1]; 7075 u8 reserved_at_41[0xf]; 7076 u8 vport_number[0x10]; 7077 7078 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7079 7080 u8 reserved_at_80[0x780]; 7081 7082 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7083 }; 7084 7085 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7086 u8 status[0x8]; 7087 u8 reserved_at_8[0x18]; 7088 7089 u8 syndrome[0x20]; 7090 7091 u8 reserved_at_40[0x40]; 7092 }; 7093 7094 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7095 u8 opcode[0x10]; 7096 u8 reserved_at_10[0x10]; 7097 7098 u8 reserved_at_20[0x10]; 7099 u8 op_mod[0x10]; 7100 7101 u8 other_vport[0x1]; 7102 u8 reserved_at_41[0xb]; 7103 u8 port_num[0x4]; 7104 u8 vport_number[0x10]; 7105 7106 u8 reserved_at_60[0x20]; 7107 7108 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7109 }; 7110 7111 struct mlx5_ifc_modify_cq_out_bits { 7112 u8 status[0x8]; 7113 u8 reserved_at_8[0x18]; 7114 7115 u8 syndrome[0x20]; 7116 7117 u8 reserved_at_40[0x40]; 7118 }; 7119 7120 enum { 7121 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7122 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7123 }; 7124 7125 struct mlx5_ifc_modify_cq_in_bits { 7126 u8 opcode[0x10]; 7127 u8 uid[0x10]; 7128 7129 u8 reserved_at_20[0x10]; 7130 u8 op_mod[0x10]; 7131 7132 u8 reserved_at_40[0x8]; 7133 u8 cqn[0x18]; 7134 7135 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7136 7137 struct mlx5_ifc_cqc_bits cq_context; 7138 7139 u8 reserved_at_280[0x60]; 7140 7141 u8 cq_umem_valid[0x1]; 7142 u8 reserved_at_2e1[0x1f]; 7143 7144 u8 reserved_at_300[0x580]; 7145 7146 u8 pas[][0x40]; 7147 }; 7148 7149 struct mlx5_ifc_modify_cong_status_out_bits { 7150 u8 status[0x8]; 7151 u8 reserved_at_8[0x18]; 7152 7153 u8 syndrome[0x20]; 7154 7155 u8 reserved_at_40[0x40]; 7156 }; 7157 7158 struct mlx5_ifc_modify_cong_status_in_bits { 7159 u8 opcode[0x10]; 7160 u8 reserved_at_10[0x10]; 7161 7162 u8 reserved_at_20[0x10]; 7163 u8 op_mod[0x10]; 7164 7165 u8 reserved_at_40[0x18]; 7166 u8 priority[0x4]; 7167 u8 cong_protocol[0x4]; 7168 7169 u8 enable[0x1]; 7170 u8 tag_enable[0x1]; 7171 u8 reserved_at_62[0x1e]; 7172 }; 7173 7174 struct mlx5_ifc_modify_cong_params_out_bits { 7175 u8 status[0x8]; 7176 u8 reserved_at_8[0x18]; 7177 7178 u8 syndrome[0x20]; 7179 7180 u8 reserved_at_40[0x40]; 7181 }; 7182 7183 struct mlx5_ifc_modify_cong_params_in_bits { 7184 u8 opcode[0x10]; 7185 u8 reserved_at_10[0x10]; 7186 7187 u8 reserved_at_20[0x10]; 7188 u8 op_mod[0x10]; 7189 7190 u8 reserved_at_40[0x1c]; 7191 u8 cong_protocol[0x4]; 7192 7193 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7194 7195 u8 reserved_at_80[0x80]; 7196 7197 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7198 }; 7199 7200 struct mlx5_ifc_manage_pages_out_bits { 7201 u8 status[0x8]; 7202 u8 reserved_at_8[0x18]; 7203 7204 u8 syndrome[0x20]; 7205 7206 u8 output_num_entries[0x20]; 7207 7208 u8 reserved_at_60[0x20]; 7209 7210 u8 pas[][0x40]; 7211 }; 7212 7213 enum { 7214 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7215 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7216 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7217 }; 7218 7219 struct mlx5_ifc_manage_pages_in_bits { 7220 u8 opcode[0x10]; 7221 u8 reserved_at_10[0x10]; 7222 7223 u8 reserved_at_20[0x10]; 7224 u8 op_mod[0x10]; 7225 7226 u8 embedded_cpu_function[0x1]; 7227 u8 reserved_at_41[0xf]; 7228 u8 function_id[0x10]; 7229 7230 u8 input_num_entries[0x20]; 7231 7232 u8 pas[][0x40]; 7233 }; 7234 7235 struct mlx5_ifc_mad_ifc_out_bits { 7236 u8 status[0x8]; 7237 u8 reserved_at_8[0x18]; 7238 7239 u8 syndrome[0x20]; 7240 7241 u8 reserved_at_40[0x40]; 7242 7243 u8 response_mad_packet[256][0x8]; 7244 }; 7245 7246 struct mlx5_ifc_mad_ifc_in_bits { 7247 u8 opcode[0x10]; 7248 u8 reserved_at_10[0x10]; 7249 7250 u8 reserved_at_20[0x10]; 7251 u8 op_mod[0x10]; 7252 7253 u8 remote_lid[0x10]; 7254 u8 reserved_at_50[0x8]; 7255 u8 port[0x8]; 7256 7257 u8 reserved_at_60[0x20]; 7258 7259 u8 mad[256][0x8]; 7260 }; 7261 7262 struct mlx5_ifc_init_hca_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_at_8[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_at_40[0x40]; 7269 }; 7270 7271 struct mlx5_ifc_init_hca_in_bits { 7272 u8 opcode[0x10]; 7273 u8 reserved_at_10[0x10]; 7274 7275 u8 reserved_at_20[0x10]; 7276 u8 op_mod[0x10]; 7277 7278 u8 reserved_at_40[0x20]; 7279 7280 u8 reserved_at_60[0x2]; 7281 u8 sw_vhca_id[0xe]; 7282 u8 reserved_at_70[0x10]; 7283 7284 u8 sw_owner_id[4][0x20]; 7285 }; 7286 7287 struct mlx5_ifc_init2rtr_qp_out_bits { 7288 u8 status[0x8]; 7289 u8 reserved_at_8[0x18]; 7290 7291 u8 syndrome[0x20]; 7292 7293 u8 reserved_at_40[0x20]; 7294 u8 ece[0x20]; 7295 }; 7296 7297 struct mlx5_ifc_init2rtr_qp_in_bits { 7298 u8 opcode[0x10]; 7299 u8 uid[0x10]; 7300 7301 u8 reserved_at_20[0x10]; 7302 u8 op_mod[0x10]; 7303 7304 u8 reserved_at_40[0x8]; 7305 u8 qpn[0x18]; 7306 7307 u8 reserved_at_60[0x20]; 7308 7309 u8 opt_param_mask[0x20]; 7310 7311 u8 ece[0x20]; 7312 7313 struct mlx5_ifc_qpc_bits qpc; 7314 7315 u8 reserved_at_800[0x80]; 7316 }; 7317 7318 struct mlx5_ifc_init2init_qp_out_bits { 7319 u8 status[0x8]; 7320 u8 reserved_at_8[0x18]; 7321 7322 u8 syndrome[0x20]; 7323 7324 u8 reserved_at_40[0x20]; 7325 u8 ece[0x20]; 7326 }; 7327 7328 struct mlx5_ifc_init2init_qp_in_bits { 7329 u8 opcode[0x10]; 7330 u8 uid[0x10]; 7331 7332 u8 reserved_at_20[0x10]; 7333 u8 op_mod[0x10]; 7334 7335 u8 reserved_at_40[0x8]; 7336 u8 qpn[0x18]; 7337 7338 u8 reserved_at_60[0x20]; 7339 7340 u8 opt_param_mask[0x20]; 7341 7342 u8 ece[0x20]; 7343 7344 struct mlx5_ifc_qpc_bits qpc; 7345 7346 u8 reserved_at_800[0x80]; 7347 }; 7348 7349 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7350 u8 status[0x8]; 7351 u8 reserved_at_8[0x18]; 7352 7353 u8 syndrome[0x20]; 7354 7355 u8 reserved_at_40[0x40]; 7356 7357 u8 packet_headers_log[128][0x8]; 7358 7359 u8 packet_syndrome[64][0x8]; 7360 }; 7361 7362 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7363 u8 opcode[0x10]; 7364 u8 reserved_at_10[0x10]; 7365 7366 u8 reserved_at_20[0x10]; 7367 u8 op_mod[0x10]; 7368 7369 u8 reserved_at_40[0x40]; 7370 }; 7371 7372 struct mlx5_ifc_gen_eqe_in_bits { 7373 u8 opcode[0x10]; 7374 u8 reserved_at_10[0x10]; 7375 7376 u8 reserved_at_20[0x10]; 7377 u8 op_mod[0x10]; 7378 7379 u8 reserved_at_40[0x18]; 7380 u8 eq_number[0x8]; 7381 7382 u8 reserved_at_60[0x20]; 7383 7384 u8 eqe[64][0x8]; 7385 }; 7386 7387 struct mlx5_ifc_gen_eq_out_bits { 7388 u8 status[0x8]; 7389 u8 reserved_at_8[0x18]; 7390 7391 u8 syndrome[0x20]; 7392 7393 u8 reserved_at_40[0x40]; 7394 }; 7395 7396 struct mlx5_ifc_enable_hca_out_bits { 7397 u8 status[0x8]; 7398 u8 reserved_at_8[0x18]; 7399 7400 u8 syndrome[0x20]; 7401 7402 u8 reserved_at_40[0x20]; 7403 }; 7404 7405 struct mlx5_ifc_enable_hca_in_bits { 7406 u8 opcode[0x10]; 7407 u8 reserved_at_10[0x10]; 7408 7409 u8 reserved_at_20[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 embedded_cpu_function[0x1]; 7413 u8 reserved_at_41[0xf]; 7414 u8 function_id[0x10]; 7415 7416 u8 reserved_at_60[0x20]; 7417 }; 7418 7419 struct mlx5_ifc_drain_dct_out_bits { 7420 u8 status[0x8]; 7421 u8 reserved_at_8[0x18]; 7422 7423 u8 syndrome[0x20]; 7424 7425 u8 reserved_at_40[0x40]; 7426 }; 7427 7428 struct mlx5_ifc_drain_dct_in_bits { 7429 u8 opcode[0x10]; 7430 u8 uid[0x10]; 7431 7432 u8 reserved_at_20[0x10]; 7433 u8 op_mod[0x10]; 7434 7435 u8 reserved_at_40[0x8]; 7436 u8 dctn[0x18]; 7437 7438 u8 reserved_at_60[0x20]; 7439 }; 7440 7441 struct mlx5_ifc_disable_hca_out_bits { 7442 u8 status[0x8]; 7443 u8 reserved_at_8[0x18]; 7444 7445 u8 syndrome[0x20]; 7446 7447 u8 reserved_at_40[0x20]; 7448 }; 7449 7450 struct mlx5_ifc_disable_hca_in_bits { 7451 u8 opcode[0x10]; 7452 u8 reserved_at_10[0x10]; 7453 7454 u8 reserved_at_20[0x10]; 7455 u8 op_mod[0x10]; 7456 7457 u8 embedded_cpu_function[0x1]; 7458 u8 reserved_at_41[0xf]; 7459 u8 function_id[0x10]; 7460 7461 u8 reserved_at_60[0x20]; 7462 }; 7463 7464 struct mlx5_ifc_detach_from_mcg_out_bits { 7465 u8 status[0x8]; 7466 u8 reserved_at_8[0x18]; 7467 7468 u8 syndrome[0x20]; 7469 7470 u8 reserved_at_40[0x40]; 7471 }; 7472 7473 struct mlx5_ifc_detach_from_mcg_in_bits { 7474 u8 opcode[0x10]; 7475 u8 uid[0x10]; 7476 7477 u8 reserved_at_20[0x10]; 7478 u8 op_mod[0x10]; 7479 7480 u8 reserved_at_40[0x8]; 7481 u8 qpn[0x18]; 7482 7483 u8 reserved_at_60[0x20]; 7484 7485 u8 multicast_gid[16][0x8]; 7486 }; 7487 7488 struct mlx5_ifc_destroy_xrq_out_bits { 7489 u8 status[0x8]; 7490 u8 reserved_at_8[0x18]; 7491 7492 u8 syndrome[0x20]; 7493 7494 u8 reserved_at_40[0x40]; 7495 }; 7496 7497 struct mlx5_ifc_destroy_xrq_in_bits { 7498 u8 opcode[0x10]; 7499 u8 uid[0x10]; 7500 7501 u8 reserved_at_20[0x10]; 7502 u8 op_mod[0x10]; 7503 7504 u8 reserved_at_40[0x8]; 7505 u8 xrqn[0x18]; 7506 7507 u8 reserved_at_60[0x20]; 7508 }; 7509 7510 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7511 u8 status[0x8]; 7512 u8 reserved_at_8[0x18]; 7513 7514 u8 syndrome[0x20]; 7515 7516 u8 reserved_at_40[0x40]; 7517 }; 7518 7519 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7520 u8 opcode[0x10]; 7521 u8 uid[0x10]; 7522 7523 u8 reserved_at_20[0x10]; 7524 u8 op_mod[0x10]; 7525 7526 u8 reserved_at_40[0x8]; 7527 u8 xrc_srqn[0x18]; 7528 7529 u8 reserved_at_60[0x20]; 7530 }; 7531 7532 struct mlx5_ifc_destroy_tis_out_bits { 7533 u8 status[0x8]; 7534 u8 reserved_at_8[0x18]; 7535 7536 u8 syndrome[0x20]; 7537 7538 u8 reserved_at_40[0x40]; 7539 }; 7540 7541 struct mlx5_ifc_destroy_tis_in_bits { 7542 u8 opcode[0x10]; 7543 u8 uid[0x10]; 7544 7545 u8 reserved_at_20[0x10]; 7546 u8 op_mod[0x10]; 7547 7548 u8 reserved_at_40[0x8]; 7549 u8 tisn[0x18]; 7550 7551 u8 reserved_at_60[0x20]; 7552 }; 7553 7554 struct mlx5_ifc_destroy_tir_out_bits { 7555 u8 status[0x8]; 7556 u8 reserved_at_8[0x18]; 7557 7558 u8 syndrome[0x20]; 7559 7560 u8 reserved_at_40[0x40]; 7561 }; 7562 7563 struct mlx5_ifc_destroy_tir_in_bits { 7564 u8 opcode[0x10]; 7565 u8 uid[0x10]; 7566 7567 u8 reserved_at_20[0x10]; 7568 u8 op_mod[0x10]; 7569 7570 u8 reserved_at_40[0x8]; 7571 u8 tirn[0x18]; 7572 7573 u8 reserved_at_60[0x20]; 7574 }; 7575 7576 struct mlx5_ifc_destroy_srq_out_bits { 7577 u8 status[0x8]; 7578 u8 reserved_at_8[0x18]; 7579 7580 u8 syndrome[0x20]; 7581 7582 u8 reserved_at_40[0x40]; 7583 }; 7584 7585 struct mlx5_ifc_destroy_srq_in_bits { 7586 u8 opcode[0x10]; 7587 u8 uid[0x10]; 7588 7589 u8 reserved_at_20[0x10]; 7590 u8 op_mod[0x10]; 7591 7592 u8 reserved_at_40[0x8]; 7593 u8 srqn[0x18]; 7594 7595 u8 reserved_at_60[0x20]; 7596 }; 7597 7598 struct mlx5_ifc_destroy_sq_out_bits { 7599 u8 status[0x8]; 7600 u8 reserved_at_8[0x18]; 7601 7602 u8 syndrome[0x20]; 7603 7604 u8 reserved_at_40[0x40]; 7605 }; 7606 7607 struct mlx5_ifc_destroy_sq_in_bits { 7608 u8 opcode[0x10]; 7609 u8 uid[0x10]; 7610 7611 u8 reserved_at_20[0x10]; 7612 u8 op_mod[0x10]; 7613 7614 u8 reserved_at_40[0x8]; 7615 u8 sqn[0x18]; 7616 7617 u8 reserved_at_60[0x20]; 7618 }; 7619 7620 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7621 u8 status[0x8]; 7622 u8 reserved_at_8[0x18]; 7623 7624 u8 syndrome[0x20]; 7625 7626 u8 reserved_at_40[0x1c0]; 7627 }; 7628 7629 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7630 u8 opcode[0x10]; 7631 u8 reserved_at_10[0x10]; 7632 7633 u8 reserved_at_20[0x10]; 7634 u8 op_mod[0x10]; 7635 7636 u8 scheduling_hierarchy[0x8]; 7637 u8 reserved_at_48[0x18]; 7638 7639 u8 scheduling_element_id[0x20]; 7640 7641 u8 reserved_at_80[0x180]; 7642 }; 7643 7644 struct mlx5_ifc_destroy_rqt_out_bits { 7645 u8 status[0x8]; 7646 u8 reserved_at_8[0x18]; 7647 7648 u8 syndrome[0x20]; 7649 7650 u8 reserved_at_40[0x40]; 7651 }; 7652 7653 struct mlx5_ifc_destroy_rqt_in_bits { 7654 u8 opcode[0x10]; 7655 u8 uid[0x10]; 7656 7657 u8 reserved_at_20[0x10]; 7658 u8 op_mod[0x10]; 7659 7660 u8 reserved_at_40[0x8]; 7661 u8 rqtn[0x18]; 7662 7663 u8 reserved_at_60[0x20]; 7664 }; 7665 7666 struct mlx5_ifc_destroy_rq_out_bits { 7667 u8 status[0x8]; 7668 u8 reserved_at_8[0x18]; 7669 7670 u8 syndrome[0x20]; 7671 7672 u8 reserved_at_40[0x40]; 7673 }; 7674 7675 struct mlx5_ifc_destroy_rq_in_bits { 7676 u8 opcode[0x10]; 7677 u8 uid[0x10]; 7678 7679 u8 reserved_at_20[0x10]; 7680 u8 op_mod[0x10]; 7681 7682 u8 reserved_at_40[0x8]; 7683 u8 rqn[0x18]; 7684 7685 u8 reserved_at_60[0x20]; 7686 }; 7687 7688 struct mlx5_ifc_set_delay_drop_params_in_bits { 7689 u8 opcode[0x10]; 7690 u8 reserved_at_10[0x10]; 7691 7692 u8 reserved_at_20[0x10]; 7693 u8 op_mod[0x10]; 7694 7695 u8 reserved_at_40[0x20]; 7696 7697 u8 reserved_at_60[0x10]; 7698 u8 delay_drop_timeout[0x10]; 7699 }; 7700 7701 struct mlx5_ifc_set_delay_drop_params_out_bits { 7702 u8 status[0x8]; 7703 u8 reserved_at_8[0x18]; 7704 7705 u8 syndrome[0x20]; 7706 7707 u8 reserved_at_40[0x40]; 7708 }; 7709 7710 struct mlx5_ifc_destroy_rmp_out_bits { 7711 u8 status[0x8]; 7712 u8 reserved_at_8[0x18]; 7713 7714 u8 syndrome[0x20]; 7715 7716 u8 reserved_at_40[0x40]; 7717 }; 7718 7719 struct mlx5_ifc_destroy_rmp_in_bits { 7720 u8 opcode[0x10]; 7721 u8 uid[0x10]; 7722 7723 u8 reserved_at_20[0x10]; 7724 u8 op_mod[0x10]; 7725 7726 u8 reserved_at_40[0x8]; 7727 u8 rmpn[0x18]; 7728 7729 u8 reserved_at_60[0x20]; 7730 }; 7731 7732 struct mlx5_ifc_destroy_qp_out_bits { 7733 u8 status[0x8]; 7734 u8 reserved_at_8[0x18]; 7735 7736 u8 syndrome[0x20]; 7737 7738 u8 reserved_at_40[0x40]; 7739 }; 7740 7741 struct mlx5_ifc_destroy_qp_in_bits { 7742 u8 opcode[0x10]; 7743 u8 uid[0x10]; 7744 7745 u8 reserved_at_20[0x10]; 7746 u8 op_mod[0x10]; 7747 7748 u8 reserved_at_40[0x8]; 7749 u8 qpn[0x18]; 7750 7751 u8 reserved_at_60[0x20]; 7752 }; 7753 7754 struct mlx5_ifc_destroy_psv_out_bits { 7755 u8 status[0x8]; 7756 u8 reserved_at_8[0x18]; 7757 7758 u8 syndrome[0x20]; 7759 7760 u8 reserved_at_40[0x40]; 7761 }; 7762 7763 struct mlx5_ifc_destroy_psv_in_bits { 7764 u8 opcode[0x10]; 7765 u8 reserved_at_10[0x10]; 7766 7767 u8 reserved_at_20[0x10]; 7768 u8 op_mod[0x10]; 7769 7770 u8 reserved_at_40[0x8]; 7771 u8 psvn[0x18]; 7772 7773 u8 reserved_at_60[0x20]; 7774 }; 7775 7776 struct mlx5_ifc_destroy_mkey_out_bits { 7777 u8 status[0x8]; 7778 u8 reserved_at_8[0x18]; 7779 7780 u8 syndrome[0x20]; 7781 7782 u8 reserved_at_40[0x40]; 7783 }; 7784 7785 struct mlx5_ifc_destroy_mkey_in_bits { 7786 u8 opcode[0x10]; 7787 u8 uid[0x10]; 7788 7789 u8 reserved_at_20[0x10]; 7790 u8 op_mod[0x10]; 7791 7792 u8 reserved_at_40[0x8]; 7793 u8 mkey_index[0x18]; 7794 7795 u8 reserved_at_60[0x20]; 7796 }; 7797 7798 struct mlx5_ifc_destroy_flow_table_out_bits { 7799 u8 status[0x8]; 7800 u8 reserved_at_8[0x18]; 7801 7802 u8 syndrome[0x20]; 7803 7804 u8 reserved_at_40[0x40]; 7805 }; 7806 7807 struct mlx5_ifc_destroy_flow_table_in_bits { 7808 u8 opcode[0x10]; 7809 u8 reserved_at_10[0x10]; 7810 7811 u8 reserved_at_20[0x10]; 7812 u8 op_mod[0x10]; 7813 7814 u8 other_vport[0x1]; 7815 u8 reserved_at_41[0xf]; 7816 u8 vport_number[0x10]; 7817 7818 u8 reserved_at_60[0x20]; 7819 7820 u8 table_type[0x8]; 7821 u8 reserved_at_88[0x18]; 7822 7823 u8 reserved_at_a0[0x8]; 7824 u8 table_id[0x18]; 7825 7826 u8 reserved_at_c0[0x140]; 7827 }; 7828 7829 struct mlx5_ifc_destroy_flow_group_out_bits { 7830 u8 status[0x8]; 7831 u8 reserved_at_8[0x18]; 7832 7833 u8 syndrome[0x20]; 7834 7835 u8 reserved_at_40[0x40]; 7836 }; 7837 7838 struct mlx5_ifc_destroy_flow_group_in_bits { 7839 u8 opcode[0x10]; 7840 u8 reserved_at_10[0x10]; 7841 7842 u8 reserved_at_20[0x10]; 7843 u8 op_mod[0x10]; 7844 7845 u8 other_vport[0x1]; 7846 u8 reserved_at_41[0xf]; 7847 u8 vport_number[0x10]; 7848 7849 u8 reserved_at_60[0x20]; 7850 7851 u8 table_type[0x8]; 7852 u8 reserved_at_88[0x18]; 7853 7854 u8 reserved_at_a0[0x8]; 7855 u8 table_id[0x18]; 7856 7857 u8 group_id[0x20]; 7858 7859 u8 reserved_at_e0[0x120]; 7860 }; 7861 7862 struct mlx5_ifc_destroy_eq_out_bits { 7863 u8 status[0x8]; 7864 u8 reserved_at_8[0x18]; 7865 7866 u8 syndrome[0x20]; 7867 7868 u8 reserved_at_40[0x40]; 7869 }; 7870 7871 struct mlx5_ifc_destroy_eq_in_bits { 7872 u8 opcode[0x10]; 7873 u8 reserved_at_10[0x10]; 7874 7875 u8 reserved_at_20[0x10]; 7876 u8 op_mod[0x10]; 7877 7878 u8 reserved_at_40[0x18]; 7879 u8 eq_number[0x8]; 7880 7881 u8 reserved_at_60[0x20]; 7882 }; 7883 7884 struct mlx5_ifc_destroy_dct_out_bits { 7885 u8 status[0x8]; 7886 u8 reserved_at_8[0x18]; 7887 7888 u8 syndrome[0x20]; 7889 7890 u8 reserved_at_40[0x40]; 7891 }; 7892 7893 struct mlx5_ifc_destroy_dct_in_bits { 7894 u8 opcode[0x10]; 7895 u8 uid[0x10]; 7896 7897 u8 reserved_at_20[0x10]; 7898 u8 op_mod[0x10]; 7899 7900 u8 reserved_at_40[0x8]; 7901 u8 dctn[0x18]; 7902 7903 u8 reserved_at_60[0x20]; 7904 }; 7905 7906 struct mlx5_ifc_destroy_cq_out_bits { 7907 u8 status[0x8]; 7908 u8 reserved_at_8[0x18]; 7909 7910 u8 syndrome[0x20]; 7911 7912 u8 reserved_at_40[0x40]; 7913 }; 7914 7915 struct mlx5_ifc_destroy_cq_in_bits { 7916 u8 opcode[0x10]; 7917 u8 uid[0x10]; 7918 7919 u8 reserved_at_20[0x10]; 7920 u8 op_mod[0x10]; 7921 7922 u8 reserved_at_40[0x8]; 7923 u8 cqn[0x18]; 7924 7925 u8 reserved_at_60[0x20]; 7926 }; 7927 7928 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7929 u8 status[0x8]; 7930 u8 reserved_at_8[0x18]; 7931 7932 u8 syndrome[0x20]; 7933 7934 u8 reserved_at_40[0x40]; 7935 }; 7936 7937 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7938 u8 opcode[0x10]; 7939 u8 reserved_at_10[0x10]; 7940 7941 u8 reserved_at_20[0x10]; 7942 u8 op_mod[0x10]; 7943 7944 u8 reserved_at_40[0x20]; 7945 7946 u8 reserved_at_60[0x10]; 7947 u8 vxlan_udp_port[0x10]; 7948 }; 7949 7950 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7951 u8 status[0x8]; 7952 u8 reserved_at_8[0x18]; 7953 7954 u8 syndrome[0x20]; 7955 7956 u8 reserved_at_40[0x40]; 7957 }; 7958 7959 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7960 u8 opcode[0x10]; 7961 u8 reserved_at_10[0x10]; 7962 7963 u8 reserved_at_20[0x10]; 7964 u8 op_mod[0x10]; 7965 7966 u8 reserved_at_40[0x60]; 7967 7968 u8 reserved_at_a0[0x8]; 7969 u8 table_index[0x18]; 7970 7971 u8 reserved_at_c0[0x140]; 7972 }; 7973 7974 struct mlx5_ifc_delete_fte_out_bits { 7975 u8 status[0x8]; 7976 u8 reserved_at_8[0x18]; 7977 7978 u8 syndrome[0x20]; 7979 7980 u8 reserved_at_40[0x40]; 7981 }; 7982 7983 struct mlx5_ifc_delete_fte_in_bits { 7984 u8 opcode[0x10]; 7985 u8 reserved_at_10[0x10]; 7986 7987 u8 reserved_at_20[0x10]; 7988 u8 op_mod[0x10]; 7989 7990 u8 other_vport[0x1]; 7991 u8 reserved_at_41[0xf]; 7992 u8 vport_number[0x10]; 7993 7994 u8 reserved_at_60[0x20]; 7995 7996 u8 table_type[0x8]; 7997 u8 reserved_at_88[0x18]; 7998 7999 u8 reserved_at_a0[0x8]; 8000 u8 table_id[0x18]; 8001 8002 u8 reserved_at_c0[0x40]; 8003 8004 u8 flow_index[0x20]; 8005 8006 u8 reserved_at_120[0xe0]; 8007 }; 8008 8009 struct mlx5_ifc_dealloc_xrcd_out_bits { 8010 u8 status[0x8]; 8011 u8 reserved_at_8[0x18]; 8012 8013 u8 syndrome[0x20]; 8014 8015 u8 reserved_at_40[0x40]; 8016 }; 8017 8018 struct mlx5_ifc_dealloc_xrcd_in_bits { 8019 u8 opcode[0x10]; 8020 u8 uid[0x10]; 8021 8022 u8 reserved_at_20[0x10]; 8023 u8 op_mod[0x10]; 8024 8025 u8 reserved_at_40[0x8]; 8026 u8 xrcd[0x18]; 8027 8028 u8 reserved_at_60[0x20]; 8029 }; 8030 8031 struct mlx5_ifc_dealloc_uar_out_bits { 8032 u8 status[0x8]; 8033 u8 reserved_at_8[0x18]; 8034 8035 u8 syndrome[0x20]; 8036 8037 u8 reserved_at_40[0x40]; 8038 }; 8039 8040 struct mlx5_ifc_dealloc_uar_in_bits { 8041 u8 opcode[0x10]; 8042 u8 uid[0x10]; 8043 8044 u8 reserved_at_20[0x10]; 8045 u8 op_mod[0x10]; 8046 8047 u8 reserved_at_40[0x8]; 8048 u8 uar[0x18]; 8049 8050 u8 reserved_at_60[0x20]; 8051 }; 8052 8053 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8054 u8 status[0x8]; 8055 u8 reserved_at_8[0x18]; 8056 8057 u8 syndrome[0x20]; 8058 8059 u8 reserved_at_40[0x40]; 8060 }; 8061 8062 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8063 u8 opcode[0x10]; 8064 u8 uid[0x10]; 8065 8066 u8 reserved_at_20[0x10]; 8067 u8 op_mod[0x10]; 8068 8069 u8 reserved_at_40[0x8]; 8070 u8 transport_domain[0x18]; 8071 8072 u8 reserved_at_60[0x20]; 8073 }; 8074 8075 struct mlx5_ifc_dealloc_q_counter_out_bits { 8076 u8 status[0x8]; 8077 u8 reserved_at_8[0x18]; 8078 8079 u8 syndrome[0x20]; 8080 8081 u8 reserved_at_40[0x40]; 8082 }; 8083 8084 struct mlx5_ifc_dealloc_q_counter_in_bits { 8085 u8 opcode[0x10]; 8086 u8 reserved_at_10[0x10]; 8087 8088 u8 reserved_at_20[0x10]; 8089 u8 op_mod[0x10]; 8090 8091 u8 reserved_at_40[0x18]; 8092 u8 counter_set_id[0x8]; 8093 8094 u8 reserved_at_60[0x20]; 8095 }; 8096 8097 struct mlx5_ifc_dealloc_pd_out_bits { 8098 u8 status[0x8]; 8099 u8 reserved_at_8[0x18]; 8100 8101 u8 syndrome[0x20]; 8102 8103 u8 reserved_at_40[0x40]; 8104 }; 8105 8106 struct mlx5_ifc_dealloc_pd_in_bits { 8107 u8 opcode[0x10]; 8108 u8 uid[0x10]; 8109 8110 u8 reserved_at_20[0x10]; 8111 u8 op_mod[0x10]; 8112 8113 u8 reserved_at_40[0x8]; 8114 u8 pd[0x18]; 8115 8116 u8 reserved_at_60[0x20]; 8117 }; 8118 8119 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8120 u8 status[0x8]; 8121 u8 reserved_at_8[0x18]; 8122 8123 u8 syndrome[0x20]; 8124 8125 u8 reserved_at_40[0x40]; 8126 }; 8127 8128 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8129 u8 opcode[0x10]; 8130 u8 reserved_at_10[0x10]; 8131 8132 u8 reserved_at_20[0x10]; 8133 u8 op_mod[0x10]; 8134 8135 u8 flow_counter_id[0x20]; 8136 8137 u8 reserved_at_60[0x20]; 8138 }; 8139 8140 struct mlx5_ifc_create_xrq_out_bits { 8141 u8 status[0x8]; 8142 u8 reserved_at_8[0x18]; 8143 8144 u8 syndrome[0x20]; 8145 8146 u8 reserved_at_40[0x8]; 8147 u8 xrqn[0x18]; 8148 8149 u8 reserved_at_60[0x20]; 8150 }; 8151 8152 struct mlx5_ifc_create_xrq_in_bits { 8153 u8 opcode[0x10]; 8154 u8 uid[0x10]; 8155 8156 u8 reserved_at_20[0x10]; 8157 u8 op_mod[0x10]; 8158 8159 u8 reserved_at_40[0x40]; 8160 8161 struct mlx5_ifc_xrqc_bits xrq_context; 8162 }; 8163 8164 struct mlx5_ifc_create_xrc_srq_out_bits { 8165 u8 status[0x8]; 8166 u8 reserved_at_8[0x18]; 8167 8168 u8 syndrome[0x20]; 8169 8170 u8 reserved_at_40[0x8]; 8171 u8 xrc_srqn[0x18]; 8172 8173 u8 reserved_at_60[0x20]; 8174 }; 8175 8176 struct mlx5_ifc_create_xrc_srq_in_bits { 8177 u8 opcode[0x10]; 8178 u8 uid[0x10]; 8179 8180 u8 reserved_at_20[0x10]; 8181 u8 op_mod[0x10]; 8182 8183 u8 reserved_at_40[0x40]; 8184 8185 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8186 8187 u8 reserved_at_280[0x60]; 8188 8189 u8 xrc_srq_umem_valid[0x1]; 8190 u8 reserved_at_2e1[0x1f]; 8191 8192 u8 reserved_at_300[0x580]; 8193 8194 u8 pas[][0x40]; 8195 }; 8196 8197 struct mlx5_ifc_create_tis_out_bits { 8198 u8 status[0x8]; 8199 u8 reserved_at_8[0x18]; 8200 8201 u8 syndrome[0x20]; 8202 8203 u8 reserved_at_40[0x8]; 8204 u8 tisn[0x18]; 8205 8206 u8 reserved_at_60[0x20]; 8207 }; 8208 8209 struct mlx5_ifc_create_tis_in_bits { 8210 u8 opcode[0x10]; 8211 u8 uid[0x10]; 8212 8213 u8 reserved_at_20[0x10]; 8214 u8 op_mod[0x10]; 8215 8216 u8 reserved_at_40[0xc0]; 8217 8218 struct mlx5_ifc_tisc_bits ctx; 8219 }; 8220 8221 struct mlx5_ifc_create_tir_out_bits { 8222 u8 status[0x8]; 8223 u8 icm_address_63_40[0x18]; 8224 8225 u8 syndrome[0x20]; 8226 8227 u8 icm_address_39_32[0x8]; 8228 u8 tirn[0x18]; 8229 8230 u8 icm_address_31_0[0x20]; 8231 }; 8232 8233 struct mlx5_ifc_create_tir_in_bits { 8234 u8 opcode[0x10]; 8235 u8 uid[0x10]; 8236 8237 u8 reserved_at_20[0x10]; 8238 u8 op_mod[0x10]; 8239 8240 u8 reserved_at_40[0xc0]; 8241 8242 struct mlx5_ifc_tirc_bits ctx; 8243 }; 8244 8245 struct mlx5_ifc_create_srq_out_bits { 8246 u8 status[0x8]; 8247 u8 reserved_at_8[0x18]; 8248 8249 u8 syndrome[0x20]; 8250 8251 u8 reserved_at_40[0x8]; 8252 u8 srqn[0x18]; 8253 8254 u8 reserved_at_60[0x20]; 8255 }; 8256 8257 struct mlx5_ifc_create_srq_in_bits { 8258 u8 opcode[0x10]; 8259 u8 uid[0x10]; 8260 8261 u8 reserved_at_20[0x10]; 8262 u8 op_mod[0x10]; 8263 8264 u8 reserved_at_40[0x40]; 8265 8266 struct mlx5_ifc_srqc_bits srq_context_entry; 8267 8268 u8 reserved_at_280[0x600]; 8269 8270 u8 pas[][0x40]; 8271 }; 8272 8273 struct mlx5_ifc_create_sq_out_bits { 8274 u8 status[0x8]; 8275 u8 reserved_at_8[0x18]; 8276 8277 u8 syndrome[0x20]; 8278 8279 u8 reserved_at_40[0x8]; 8280 u8 sqn[0x18]; 8281 8282 u8 reserved_at_60[0x20]; 8283 }; 8284 8285 struct mlx5_ifc_create_sq_in_bits { 8286 u8 opcode[0x10]; 8287 u8 uid[0x10]; 8288 8289 u8 reserved_at_20[0x10]; 8290 u8 op_mod[0x10]; 8291 8292 u8 reserved_at_40[0xc0]; 8293 8294 struct mlx5_ifc_sqc_bits ctx; 8295 }; 8296 8297 struct mlx5_ifc_create_scheduling_element_out_bits { 8298 u8 status[0x8]; 8299 u8 reserved_at_8[0x18]; 8300 8301 u8 syndrome[0x20]; 8302 8303 u8 reserved_at_40[0x40]; 8304 8305 u8 scheduling_element_id[0x20]; 8306 8307 u8 reserved_at_a0[0x160]; 8308 }; 8309 8310 struct mlx5_ifc_create_scheduling_element_in_bits { 8311 u8 opcode[0x10]; 8312 u8 reserved_at_10[0x10]; 8313 8314 u8 reserved_at_20[0x10]; 8315 u8 op_mod[0x10]; 8316 8317 u8 scheduling_hierarchy[0x8]; 8318 u8 reserved_at_48[0x18]; 8319 8320 u8 reserved_at_60[0xa0]; 8321 8322 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8323 8324 u8 reserved_at_300[0x100]; 8325 }; 8326 8327 struct mlx5_ifc_create_rqt_out_bits { 8328 u8 status[0x8]; 8329 u8 reserved_at_8[0x18]; 8330 8331 u8 syndrome[0x20]; 8332 8333 u8 reserved_at_40[0x8]; 8334 u8 rqtn[0x18]; 8335 8336 u8 reserved_at_60[0x20]; 8337 }; 8338 8339 struct mlx5_ifc_create_rqt_in_bits { 8340 u8 opcode[0x10]; 8341 u8 uid[0x10]; 8342 8343 u8 reserved_at_20[0x10]; 8344 u8 op_mod[0x10]; 8345 8346 u8 reserved_at_40[0xc0]; 8347 8348 struct mlx5_ifc_rqtc_bits rqt_context; 8349 }; 8350 8351 struct mlx5_ifc_create_rq_out_bits { 8352 u8 status[0x8]; 8353 u8 reserved_at_8[0x18]; 8354 8355 u8 syndrome[0x20]; 8356 8357 u8 reserved_at_40[0x8]; 8358 u8 rqn[0x18]; 8359 8360 u8 reserved_at_60[0x20]; 8361 }; 8362 8363 struct mlx5_ifc_create_rq_in_bits { 8364 u8 opcode[0x10]; 8365 u8 uid[0x10]; 8366 8367 u8 reserved_at_20[0x10]; 8368 u8 op_mod[0x10]; 8369 8370 u8 reserved_at_40[0xc0]; 8371 8372 struct mlx5_ifc_rqc_bits ctx; 8373 }; 8374 8375 struct mlx5_ifc_create_rmp_out_bits { 8376 u8 status[0x8]; 8377 u8 reserved_at_8[0x18]; 8378 8379 u8 syndrome[0x20]; 8380 8381 u8 reserved_at_40[0x8]; 8382 u8 rmpn[0x18]; 8383 8384 u8 reserved_at_60[0x20]; 8385 }; 8386 8387 struct mlx5_ifc_create_rmp_in_bits { 8388 u8 opcode[0x10]; 8389 u8 uid[0x10]; 8390 8391 u8 reserved_at_20[0x10]; 8392 u8 op_mod[0x10]; 8393 8394 u8 reserved_at_40[0xc0]; 8395 8396 struct mlx5_ifc_rmpc_bits ctx; 8397 }; 8398 8399 struct mlx5_ifc_create_qp_out_bits { 8400 u8 status[0x8]; 8401 u8 reserved_at_8[0x18]; 8402 8403 u8 syndrome[0x20]; 8404 8405 u8 reserved_at_40[0x8]; 8406 u8 qpn[0x18]; 8407 8408 u8 ece[0x20]; 8409 }; 8410 8411 struct mlx5_ifc_create_qp_in_bits { 8412 u8 opcode[0x10]; 8413 u8 uid[0x10]; 8414 8415 u8 reserved_at_20[0x10]; 8416 u8 op_mod[0x10]; 8417 8418 u8 reserved_at_40[0x8]; 8419 u8 input_qpn[0x18]; 8420 8421 u8 reserved_at_60[0x20]; 8422 u8 opt_param_mask[0x20]; 8423 8424 u8 ece[0x20]; 8425 8426 struct mlx5_ifc_qpc_bits qpc; 8427 8428 u8 reserved_at_800[0x60]; 8429 8430 u8 wq_umem_valid[0x1]; 8431 u8 reserved_at_861[0x1f]; 8432 8433 u8 pas[][0x40]; 8434 }; 8435 8436 struct mlx5_ifc_create_psv_out_bits { 8437 u8 status[0x8]; 8438 u8 reserved_at_8[0x18]; 8439 8440 u8 syndrome[0x20]; 8441 8442 u8 reserved_at_40[0x40]; 8443 8444 u8 reserved_at_80[0x8]; 8445 u8 psv0_index[0x18]; 8446 8447 u8 reserved_at_a0[0x8]; 8448 u8 psv1_index[0x18]; 8449 8450 u8 reserved_at_c0[0x8]; 8451 u8 psv2_index[0x18]; 8452 8453 u8 reserved_at_e0[0x8]; 8454 u8 psv3_index[0x18]; 8455 }; 8456 8457 struct mlx5_ifc_create_psv_in_bits { 8458 u8 opcode[0x10]; 8459 u8 reserved_at_10[0x10]; 8460 8461 u8 reserved_at_20[0x10]; 8462 u8 op_mod[0x10]; 8463 8464 u8 num_psv[0x4]; 8465 u8 reserved_at_44[0x4]; 8466 u8 pd[0x18]; 8467 8468 u8 reserved_at_60[0x20]; 8469 }; 8470 8471 struct mlx5_ifc_create_mkey_out_bits { 8472 u8 status[0x8]; 8473 u8 reserved_at_8[0x18]; 8474 8475 u8 syndrome[0x20]; 8476 8477 u8 reserved_at_40[0x8]; 8478 u8 mkey_index[0x18]; 8479 8480 u8 reserved_at_60[0x20]; 8481 }; 8482 8483 struct mlx5_ifc_create_mkey_in_bits { 8484 u8 opcode[0x10]; 8485 u8 uid[0x10]; 8486 8487 u8 reserved_at_20[0x10]; 8488 u8 op_mod[0x10]; 8489 8490 u8 reserved_at_40[0x20]; 8491 8492 u8 pg_access[0x1]; 8493 u8 mkey_umem_valid[0x1]; 8494 u8 reserved_at_62[0x1e]; 8495 8496 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8497 8498 u8 reserved_at_280[0x80]; 8499 8500 u8 translations_octword_actual_size[0x20]; 8501 8502 u8 reserved_at_320[0x560]; 8503 8504 u8 klm_pas_mtt[][0x20]; 8505 }; 8506 8507 enum { 8508 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8509 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8510 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8511 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8512 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8513 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8514 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8515 }; 8516 8517 struct mlx5_ifc_create_flow_table_out_bits { 8518 u8 status[0x8]; 8519 u8 icm_address_63_40[0x18]; 8520 8521 u8 syndrome[0x20]; 8522 8523 u8 icm_address_39_32[0x8]; 8524 u8 table_id[0x18]; 8525 8526 u8 icm_address_31_0[0x20]; 8527 }; 8528 8529 struct mlx5_ifc_create_flow_table_in_bits { 8530 u8 opcode[0x10]; 8531 u8 reserved_at_10[0x10]; 8532 8533 u8 reserved_at_20[0x10]; 8534 u8 op_mod[0x10]; 8535 8536 u8 other_vport[0x1]; 8537 u8 reserved_at_41[0xf]; 8538 u8 vport_number[0x10]; 8539 8540 u8 reserved_at_60[0x20]; 8541 8542 u8 table_type[0x8]; 8543 u8 reserved_at_88[0x18]; 8544 8545 u8 reserved_at_a0[0x20]; 8546 8547 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8548 }; 8549 8550 struct mlx5_ifc_create_flow_group_out_bits { 8551 u8 status[0x8]; 8552 u8 reserved_at_8[0x18]; 8553 8554 u8 syndrome[0x20]; 8555 8556 u8 reserved_at_40[0x8]; 8557 u8 group_id[0x18]; 8558 8559 u8 reserved_at_60[0x20]; 8560 }; 8561 8562 enum { 8563 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8564 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8565 }; 8566 8567 enum { 8568 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8569 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8570 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8571 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8572 }; 8573 8574 struct mlx5_ifc_create_flow_group_in_bits { 8575 u8 opcode[0x10]; 8576 u8 reserved_at_10[0x10]; 8577 8578 u8 reserved_at_20[0x10]; 8579 u8 op_mod[0x10]; 8580 8581 u8 other_vport[0x1]; 8582 u8 reserved_at_41[0xf]; 8583 u8 vport_number[0x10]; 8584 8585 u8 reserved_at_60[0x20]; 8586 8587 u8 table_type[0x8]; 8588 u8 reserved_at_88[0x4]; 8589 u8 group_type[0x4]; 8590 u8 reserved_at_90[0x10]; 8591 8592 u8 reserved_at_a0[0x8]; 8593 u8 table_id[0x18]; 8594 8595 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8596 8597 u8 reserved_at_c1[0x1f]; 8598 8599 u8 start_flow_index[0x20]; 8600 8601 u8 reserved_at_100[0x20]; 8602 8603 u8 end_flow_index[0x20]; 8604 8605 u8 reserved_at_140[0x10]; 8606 u8 match_definer_id[0x10]; 8607 8608 u8 reserved_at_160[0x80]; 8609 8610 u8 reserved_at_1e0[0x18]; 8611 u8 match_criteria_enable[0x8]; 8612 8613 struct mlx5_ifc_fte_match_param_bits match_criteria; 8614 8615 u8 reserved_at_1200[0xe00]; 8616 }; 8617 8618 struct mlx5_ifc_create_eq_out_bits { 8619 u8 status[0x8]; 8620 u8 reserved_at_8[0x18]; 8621 8622 u8 syndrome[0x20]; 8623 8624 u8 reserved_at_40[0x18]; 8625 u8 eq_number[0x8]; 8626 8627 u8 reserved_at_60[0x20]; 8628 }; 8629 8630 struct mlx5_ifc_create_eq_in_bits { 8631 u8 opcode[0x10]; 8632 u8 uid[0x10]; 8633 8634 u8 reserved_at_20[0x10]; 8635 u8 op_mod[0x10]; 8636 8637 u8 reserved_at_40[0x40]; 8638 8639 struct mlx5_ifc_eqc_bits eq_context_entry; 8640 8641 u8 reserved_at_280[0x40]; 8642 8643 u8 event_bitmask[4][0x40]; 8644 8645 u8 reserved_at_3c0[0x4c0]; 8646 8647 u8 pas[][0x40]; 8648 }; 8649 8650 struct mlx5_ifc_create_dct_out_bits { 8651 u8 status[0x8]; 8652 u8 reserved_at_8[0x18]; 8653 8654 u8 syndrome[0x20]; 8655 8656 u8 reserved_at_40[0x8]; 8657 u8 dctn[0x18]; 8658 8659 u8 ece[0x20]; 8660 }; 8661 8662 struct mlx5_ifc_create_dct_in_bits { 8663 u8 opcode[0x10]; 8664 u8 uid[0x10]; 8665 8666 u8 reserved_at_20[0x10]; 8667 u8 op_mod[0x10]; 8668 8669 u8 reserved_at_40[0x40]; 8670 8671 struct mlx5_ifc_dctc_bits dct_context_entry; 8672 8673 u8 reserved_at_280[0x180]; 8674 }; 8675 8676 struct mlx5_ifc_create_cq_out_bits { 8677 u8 status[0x8]; 8678 u8 reserved_at_8[0x18]; 8679 8680 u8 syndrome[0x20]; 8681 8682 u8 reserved_at_40[0x8]; 8683 u8 cqn[0x18]; 8684 8685 u8 reserved_at_60[0x20]; 8686 }; 8687 8688 struct mlx5_ifc_create_cq_in_bits { 8689 u8 opcode[0x10]; 8690 u8 uid[0x10]; 8691 8692 u8 reserved_at_20[0x10]; 8693 u8 op_mod[0x10]; 8694 8695 u8 reserved_at_40[0x40]; 8696 8697 struct mlx5_ifc_cqc_bits cq_context; 8698 8699 u8 reserved_at_280[0x60]; 8700 8701 u8 cq_umem_valid[0x1]; 8702 u8 reserved_at_2e1[0x59f]; 8703 8704 u8 pas[][0x40]; 8705 }; 8706 8707 struct mlx5_ifc_config_int_moderation_out_bits { 8708 u8 status[0x8]; 8709 u8 reserved_at_8[0x18]; 8710 8711 u8 syndrome[0x20]; 8712 8713 u8 reserved_at_40[0x4]; 8714 u8 min_delay[0xc]; 8715 u8 int_vector[0x10]; 8716 8717 u8 reserved_at_60[0x20]; 8718 }; 8719 8720 enum { 8721 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8722 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8723 }; 8724 8725 struct mlx5_ifc_config_int_moderation_in_bits { 8726 u8 opcode[0x10]; 8727 u8 reserved_at_10[0x10]; 8728 8729 u8 reserved_at_20[0x10]; 8730 u8 op_mod[0x10]; 8731 8732 u8 reserved_at_40[0x4]; 8733 u8 min_delay[0xc]; 8734 u8 int_vector[0x10]; 8735 8736 u8 reserved_at_60[0x20]; 8737 }; 8738 8739 struct mlx5_ifc_attach_to_mcg_out_bits { 8740 u8 status[0x8]; 8741 u8 reserved_at_8[0x18]; 8742 8743 u8 syndrome[0x20]; 8744 8745 u8 reserved_at_40[0x40]; 8746 }; 8747 8748 struct mlx5_ifc_attach_to_mcg_in_bits { 8749 u8 opcode[0x10]; 8750 u8 uid[0x10]; 8751 8752 u8 reserved_at_20[0x10]; 8753 u8 op_mod[0x10]; 8754 8755 u8 reserved_at_40[0x8]; 8756 u8 qpn[0x18]; 8757 8758 u8 reserved_at_60[0x20]; 8759 8760 u8 multicast_gid[16][0x8]; 8761 }; 8762 8763 struct mlx5_ifc_arm_xrq_out_bits { 8764 u8 status[0x8]; 8765 u8 reserved_at_8[0x18]; 8766 8767 u8 syndrome[0x20]; 8768 8769 u8 reserved_at_40[0x40]; 8770 }; 8771 8772 struct mlx5_ifc_arm_xrq_in_bits { 8773 u8 opcode[0x10]; 8774 u8 reserved_at_10[0x10]; 8775 8776 u8 reserved_at_20[0x10]; 8777 u8 op_mod[0x10]; 8778 8779 u8 reserved_at_40[0x8]; 8780 u8 xrqn[0x18]; 8781 8782 u8 reserved_at_60[0x10]; 8783 u8 lwm[0x10]; 8784 }; 8785 8786 struct mlx5_ifc_arm_xrc_srq_out_bits { 8787 u8 status[0x8]; 8788 u8 reserved_at_8[0x18]; 8789 8790 u8 syndrome[0x20]; 8791 8792 u8 reserved_at_40[0x40]; 8793 }; 8794 8795 enum { 8796 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8797 }; 8798 8799 struct mlx5_ifc_arm_xrc_srq_in_bits { 8800 u8 opcode[0x10]; 8801 u8 uid[0x10]; 8802 8803 u8 reserved_at_20[0x10]; 8804 u8 op_mod[0x10]; 8805 8806 u8 reserved_at_40[0x8]; 8807 u8 xrc_srqn[0x18]; 8808 8809 u8 reserved_at_60[0x10]; 8810 u8 lwm[0x10]; 8811 }; 8812 8813 struct mlx5_ifc_arm_rq_out_bits { 8814 u8 status[0x8]; 8815 u8 reserved_at_8[0x18]; 8816 8817 u8 syndrome[0x20]; 8818 8819 u8 reserved_at_40[0x40]; 8820 }; 8821 8822 enum { 8823 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8824 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8825 }; 8826 8827 struct mlx5_ifc_arm_rq_in_bits { 8828 u8 opcode[0x10]; 8829 u8 uid[0x10]; 8830 8831 u8 reserved_at_20[0x10]; 8832 u8 op_mod[0x10]; 8833 8834 u8 reserved_at_40[0x8]; 8835 u8 srq_number[0x18]; 8836 8837 u8 reserved_at_60[0x10]; 8838 u8 lwm[0x10]; 8839 }; 8840 8841 struct mlx5_ifc_arm_dct_out_bits { 8842 u8 status[0x8]; 8843 u8 reserved_at_8[0x18]; 8844 8845 u8 syndrome[0x20]; 8846 8847 u8 reserved_at_40[0x40]; 8848 }; 8849 8850 struct mlx5_ifc_arm_dct_in_bits { 8851 u8 opcode[0x10]; 8852 u8 reserved_at_10[0x10]; 8853 8854 u8 reserved_at_20[0x10]; 8855 u8 op_mod[0x10]; 8856 8857 u8 reserved_at_40[0x8]; 8858 u8 dct_number[0x18]; 8859 8860 u8 reserved_at_60[0x20]; 8861 }; 8862 8863 struct mlx5_ifc_alloc_xrcd_out_bits { 8864 u8 status[0x8]; 8865 u8 reserved_at_8[0x18]; 8866 8867 u8 syndrome[0x20]; 8868 8869 u8 reserved_at_40[0x8]; 8870 u8 xrcd[0x18]; 8871 8872 u8 reserved_at_60[0x20]; 8873 }; 8874 8875 struct mlx5_ifc_alloc_xrcd_in_bits { 8876 u8 opcode[0x10]; 8877 u8 uid[0x10]; 8878 8879 u8 reserved_at_20[0x10]; 8880 u8 op_mod[0x10]; 8881 8882 u8 reserved_at_40[0x40]; 8883 }; 8884 8885 struct mlx5_ifc_alloc_uar_out_bits { 8886 u8 status[0x8]; 8887 u8 reserved_at_8[0x18]; 8888 8889 u8 syndrome[0x20]; 8890 8891 u8 reserved_at_40[0x8]; 8892 u8 uar[0x18]; 8893 8894 u8 reserved_at_60[0x20]; 8895 }; 8896 8897 struct mlx5_ifc_alloc_uar_in_bits { 8898 u8 opcode[0x10]; 8899 u8 uid[0x10]; 8900 8901 u8 reserved_at_20[0x10]; 8902 u8 op_mod[0x10]; 8903 8904 u8 reserved_at_40[0x40]; 8905 }; 8906 8907 struct mlx5_ifc_alloc_transport_domain_out_bits { 8908 u8 status[0x8]; 8909 u8 reserved_at_8[0x18]; 8910 8911 u8 syndrome[0x20]; 8912 8913 u8 reserved_at_40[0x8]; 8914 u8 transport_domain[0x18]; 8915 8916 u8 reserved_at_60[0x20]; 8917 }; 8918 8919 struct mlx5_ifc_alloc_transport_domain_in_bits { 8920 u8 opcode[0x10]; 8921 u8 uid[0x10]; 8922 8923 u8 reserved_at_20[0x10]; 8924 u8 op_mod[0x10]; 8925 8926 u8 reserved_at_40[0x40]; 8927 }; 8928 8929 struct mlx5_ifc_alloc_q_counter_out_bits { 8930 u8 status[0x8]; 8931 u8 reserved_at_8[0x18]; 8932 8933 u8 syndrome[0x20]; 8934 8935 u8 reserved_at_40[0x18]; 8936 u8 counter_set_id[0x8]; 8937 8938 u8 reserved_at_60[0x20]; 8939 }; 8940 8941 struct mlx5_ifc_alloc_q_counter_in_bits { 8942 u8 opcode[0x10]; 8943 u8 uid[0x10]; 8944 8945 u8 reserved_at_20[0x10]; 8946 u8 op_mod[0x10]; 8947 8948 u8 reserved_at_40[0x40]; 8949 }; 8950 8951 struct mlx5_ifc_alloc_pd_out_bits { 8952 u8 status[0x8]; 8953 u8 reserved_at_8[0x18]; 8954 8955 u8 syndrome[0x20]; 8956 8957 u8 reserved_at_40[0x8]; 8958 u8 pd[0x18]; 8959 8960 u8 reserved_at_60[0x20]; 8961 }; 8962 8963 struct mlx5_ifc_alloc_pd_in_bits { 8964 u8 opcode[0x10]; 8965 u8 uid[0x10]; 8966 8967 u8 reserved_at_20[0x10]; 8968 u8 op_mod[0x10]; 8969 8970 u8 reserved_at_40[0x40]; 8971 }; 8972 8973 struct mlx5_ifc_alloc_flow_counter_out_bits { 8974 u8 status[0x8]; 8975 u8 reserved_at_8[0x18]; 8976 8977 u8 syndrome[0x20]; 8978 8979 u8 flow_counter_id[0x20]; 8980 8981 u8 reserved_at_60[0x20]; 8982 }; 8983 8984 struct mlx5_ifc_alloc_flow_counter_in_bits { 8985 u8 opcode[0x10]; 8986 u8 reserved_at_10[0x10]; 8987 8988 u8 reserved_at_20[0x10]; 8989 u8 op_mod[0x10]; 8990 8991 u8 reserved_at_40[0x38]; 8992 u8 flow_counter_bulk[0x8]; 8993 }; 8994 8995 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8996 u8 status[0x8]; 8997 u8 reserved_at_8[0x18]; 8998 8999 u8 syndrome[0x20]; 9000 9001 u8 reserved_at_40[0x40]; 9002 }; 9003 9004 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9005 u8 opcode[0x10]; 9006 u8 reserved_at_10[0x10]; 9007 9008 u8 reserved_at_20[0x10]; 9009 u8 op_mod[0x10]; 9010 9011 u8 reserved_at_40[0x20]; 9012 9013 u8 reserved_at_60[0x10]; 9014 u8 vxlan_udp_port[0x10]; 9015 }; 9016 9017 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9018 u8 status[0x8]; 9019 u8 reserved_at_8[0x18]; 9020 9021 u8 syndrome[0x20]; 9022 9023 u8 reserved_at_40[0x40]; 9024 }; 9025 9026 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9027 u8 rate_limit[0x20]; 9028 9029 u8 burst_upper_bound[0x20]; 9030 9031 u8 reserved_at_40[0x10]; 9032 u8 typical_packet_size[0x10]; 9033 9034 u8 reserved_at_60[0x120]; 9035 }; 9036 9037 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9038 u8 opcode[0x10]; 9039 u8 uid[0x10]; 9040 9041 u8 reserved_at_20[0x10]; 9042 u8 op_mod[0x10]; 9043 9044 u8 reserved_at_40[0x10]; 9045 u8 rate_limit_index[0x10]; 9046 9047 u8 reserved_at_60[0x20]; 9048 9049 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9050 }; 9051 9052 struct mlx5_ifc_access_register_out_bits { 9053 u8 status[0x8]; 9054 u8 reserved_at_8[0x18]; 9055 9056 u8 syndrome[0x20]; 9057 9058 u8 reserved_at_40[0x40]; 9059 9060 u8 register_data[][0x20]; 9061 }; 9062 9063 enum { 9064 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9065 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9066 }; 9067 9068 struct mlx5_ifc_access_register_in_bits { 9069 u8 opcode[0x10]; 9070 u8 reserved_at_10[0x10]; 9071 9072 u8 reserved_at_20[0x10]; 9073 u8 op_mod[0x10]; 9074 9075 u8 reserved_at_40[0x10]; 9076 u8 register_id[0x10]; 9077 9078 u8 argument[0x20]; 9079 9080 u8 register_data[][0x20]; 9081 }; 9082 9083 struct mlx5_ifc_sltp_reg_bits { 9084 u8 status[0x4]; 9085 u8 version[0x4]; 9086 u8 local_port[0x8]; 9087 u8 pnat[0x2]; 9088 u8 reserved_at_12[0x2]; 9089 u8 lane[0x4]; 9090 u8 reserved_at_18[0x8]; 9091 9092 u8 reserved_at_20[0x20]; 9093 9094 u8 reserved_at_40[0x7]; 9095 u8 polarity[0x1]; 9096 u8 ob_tap0[0x8]; 9097 u8 ob_tap1[0x8]; 9098 u8 ob_tap2[0x8]; 9099 9100 u8 reserved_at_60[0xc]; 9101 u8 ob_preemp_mode[0x4]; 9102 u8 ob_reg[0x8]; 9103 u8 ob_bias[0x8]; 9104 9105 u8 reserved_at_80[0x20]; 9106 }; 9107 9108 struct mlx5_ifc_slrg_reg_bits { 9109 u8 status[0x4]; 9110 u8 version[0x4]; 9111 u8 local_port[0x8]; 9112 u8 pnat[0x2]; 9113 u8 reserved_at_12[0x2]; 9114 u8 lane[0x4]; 9115 u8 reserved_at_18[0x8]; 9116 9117 u8 time_to_link_up[0x10]; 9118 u8 reserved_at_30[0xc]; 9119 u8 grade_lane_speed[0x4]; 9120 9121 u8 grade_version[0x8]; 9122 u8 grade[0x18]; 9123 9124 u8 reserved_at_60[0x4]; 9125 u8 height_grade_type[0x4]; 9126 u8 height_grade[0x18]; 9127 9128 u8 height_dz[0x10]; 9129 u8 height_dv[0x10]; 9130 9131 u8 reserved_at_a0[0x10]; 9132 u8 height_sigma[0x10]; 9133 9134 u8 reserved_at_c0[0x20]; 9135 9136 u8 reserved_at_e0[0x4]; 9137 u8 phase_grade_type[0x4]; 9138 u8 phase_grade[0x18]; 9139 9140 u8 reserved_at_100[0x8]; 9141 u8 phase_eo_pos[0x8]; 9142 u8 reserved_at_110[0x8]; 9143 u8 phase_eo_neg[0x8]; 9144 9145 u8 ffe_set_tested[0x10]; 9146 u8 test_errors_per_lane[0x10]; 9147 }; 9148 9149 struct mlx5_ifc_pvlc_reg_bits { 9150 u8 reserved_at_0[0x8]; 9151 u8 local_port[0x8]; 9152 u8 reserved_at_10[0x10]; 9153 9154 u8 reserved_at_20[0x1c]; 9155 u8 vl_hw_cap[0x4]; 9156 9157 u8 reserved_at_40[0x1c]; 9158 u8 vl_admin[0x4]; 9159 9160 u8 reserved_at_60[0x1c]; 9161 u8 vl_operational[0x4]; 9162 }; 9163 9164 struct mlx5_ifc_pude_reg_bits { 9165 u8 swid[0x8]; 9166 u8 local_port[0x8]; 9167 u8 reserved_at_10[0x4]; 9168 u8 admin_status[0x4]; 9169 u8 reserved_at_18[0x4]; 9170 u8 oper_status[0x4]; 9171 9172 u8 reserved_at_20[0x60]; 9173 }; 9174 9175 struct mlx5_ifc_ptys_reg_bits { 9176 u8 reserved_at_0[0x1]; 9177 u8 an_disable_admin[0x1]; 9178 u8 an_disable_cap[0x1]; 9179 u8 reserved_at_3[0x5]; 9180 u8 local_port[0x8]; 9181 u8 reserved_at_10[0xd]; 9182 u8 proto_mask[0x3]; 9183 9184 u8 an_status[0x4]; 9185 u8 reserved_at_24[0xc]; 9186 u8 data_rate_oper[0x10]; 9187 9188 u8 ext_eth_proto_capability[0x20]; 9189 9190 u8 eth_proto_capability[0x20]; 9191 9192 u8 ib_link_width_capability[0x10]; 9193 u8 ib_proto_capability[0x10]; 9194 9195 u8 ext_eth_proto_admin[0x20]; 9196 9197 u8 eth_proto_admin[0x20]; 9198 9199 u8 ib_link_width_admin[0x10]; 9200 u8 ib_proto_admin[0x10]; 9201 9202 u8 ext_eth_proto_oper[0x20]; 9203 9204 u8 eth_proto_oper[0x20]; 9205 9206 u8 ib_link_width_oper[0x10]; 9207 u8 ib_proto_oper[0x10]; 9208 9209 u8 reserved_at_160[0x1c]; 9210 u8 connector_type[0x4]; 9211 9212 u8 eth_proto_lp_advertise[0x20]; 9213 9214 u8 reserved_at_1a0[0x60]; 9215 }; 9216 9217 struct mlx5_ifc_mlcr_reg_bits { 9218 u8 reserved_at_0[0x8]; 9219 u8 local_port[0x8]; 9220 u8 reserved_at_10[0x20]; 9221 9222 u8 beacon_duration[0x10]; 9223 u8 reserved_at_40[0x10]; 9224 9225 u8 beacon_remain[0x10]; 9226 }; 9227 9228 struct mlx5_ifc_ptas_reg_bits { 9229 u8 reserved_at_0[0x20]; 9230 9231 u8 algorithm_options[0x10]; 9232 u8 reserved_at_30[0x4]; 9233 u8 repetitions_mode[0x4]; 9234 u8 num_of_repetitions[0x8]; 9235 9236 u8 grade_version[0x8]; 9237 u8 height_grade_type[0x4]; 9238 u8 phase_grade_type[0x4]; 9239 u8 height_grade_weight[0x8]; 9240 u8 phase_grade_weight[0x8]; 9241 9242 u8 gisim_measure_bits[0x10]; 9243 u8 adaptive_tap_measure_bits[0x10]; 9244 9245 u8 ber_bath_high_error_threshold[0x10]; 9246 u8 ber_bath_mid_error_threshold[0x10]; 9247 9248 u8 ber_bath_low_error_threshold[0x10]; 9249 u8 one_ratio_high_threshold[0x10]; 9250 9251 u8 one_ratio_high_mid_threshold[0x10]; 9252 u8 one_ratio_low_mid_threshold[0x10]; 9253 9254 u8 one_ratio_low_threshold[0x10]; 9255 u8 ndeo_error_threshold[0x10]; 9256 9257 u8 mixer_offset_step_size[0x10]; 9258 u8 reserved_at_110[0x8]; 9259 u8 mix90_phase_for_voltage_bath[0x8]; 9260 9261 u8 mixer_offset_start[0x10]; 9262 u8 mixer_offset_end[0x10]; 9263 9264 u8 reserved_at_140[0x15]; 9265 u8 ber_test_time[0xb]; 9266 }; 9267 9268 struct mlx5_ifc_pspa_reg_bits { 9269 u8 swid[0x8]; 9270 u8 local_port[0x8]; 9271 u8 sub_port[0x8]; 9272 u8 reserved_at_18[0x8]; 9273 9274 u8 reserved_at_20[0x20]; 9275 }; 9276 9277 struct mlx5_ifc_pqdr_reg_bits { 9278 u8 reserved_at_0[0x8]; 9279 u8 local_port[0x8]; 9280 u8 reserved_at_10[0x5]; 9281 u8 prio[0x3]; 9282 u8 reserved_at_18[0x6]; 9283 u8 mode[0x2]; 9284 9285 u8 reserved_at_20[0x20]; 9286 9287 u8 reserved_at_40[0x10]; 9288 u8 min_threshold[0x10]; 9289 9290 u8 reserved_at_60[0x10]; 9291 u8 max_threshold[0x10]; 9292 9293 u8 reserved_at_80[0x10]; 9294 u8 mark_probability_denominator[0x10]; 9295 9296 u8 reserved_at_a0[0x60]; 9297 }; 9298 9299 struct mlx5_ifc_ppsc_reg_bits { 9300 u8 reserved_at_0[0x8]; 9301 u8 local_port[0x8]; 9302 u8 reserved_at_10[0x10]; 9303 9304 u8 reserved_at_20[0x60]; 9305 9306 u8 reserved_at_80[0x1c]; 9307 u8 wrps_admin[0x4]; 9308 9309 u8 reserved_at_a0[0x1c]; 9310 u8 wrps_status[0x4]; 9311 9312 u8 reserved_at_c0[0x8]; 9313 u8 up_threshold[0x8]; 9314 u8 reserved_at_d0[0x8]; 9315 u8 down_threshold[0x8]; 9316 9317 u8 reserved_at_e0[0x20]; 9318 9319 u8 reserved_at_100[0x1c]; 9320 u8 srps_admin[0x4]; 9321 9322 u8 reserved_at_120[0x1c]; 9323 u8 srps_status[0x4]; 9324 9325 u8 reserved_at_140[0x40]; 9326 }; 9327 9328 struct mlx5_ifc_pplr_reg_bits { 9329 u8 reserved_at_0[0x8]; 9330 u8 local_port[0x8]; 9331 u8 reserved_at_10[0x10]; 9332 9333 u8 reserved_at_20[0x8]; 9334 u8 lb_cap[0x8]; 9335 u8 reserved_at_30[0x8]; 9336 u8 lb_en[0x8]; 9337 }; 9338 9339 struct mlx5_ifc_pplm_reg_bits { 9340 u8 reserved_at_0[0x8]; 9341 u8 local_port[0x8]; 9342 u8 reserved_at_10[0x10]; 9343 9344 u8 reserved_at_20[0x20]; 9345 9346 u8 port_profile_mode[0x8]; 9347 u8 static_port_profile[0x8]; 9348 u8 active_port_profile[0x8]; 9349 u8 reserved_at_58[0x8]; 9350 9351 u8 retransmission_active[0x8]; 9352 u8 fec_mode_active[0x18]; 9353 9354 u8 rs_fec_correction_bypass_cap[0x4]; 9355 u8 reserved_at_84[0x8]; 9356 u8 fec_override_cap_56g[0x4]; 9357 u8 fec_override_cap_100g[0x4]; 9358 u8 fec_override_cap_50g[0x4]; 9359 u8 fec_override_cap_25g[0x4]; 9360 u8 fec_override_cap_10g_40g[0x4]; 9361 9362 u8 rs_fec_correction_bypass_admin[0x4]; 9363 u8 reserved_at_a4[0x8]; 9364 u8 fec_override_admin_56g[0x4]; 9365 u8 fec_override_admin_100g[0x4]; 9366 u8 fec_override_admin_50g[0x4]; 9367 u8 fec_override_admin_25g[0x4]; 9368 u8 fec_override_admin_10g_40g[0x4]; 9369 9370 u8 fec_override_cap_400g_8x[0x10]; 9371 u8 fec_override_cap_200g_4x[0x10]; 9372 9373 u8 fec_override_cap_100g_2x[0x10]; 9374 u8 fec_override_cap_50g_1x[0x10]; 9375 9376 u8 fec_override_admin_400g_8x[0x10]; 9377 u8 fec_override_admin_200g_4x[0x10]; 9378 9379 u8 fec_override_admin_100g_2x[0x10]; 9380 u8 fec_override_admin_50g_1x[0x10]; 9381 9382 u8 reserved_at_140[0x140]; 9383 }; 9384 9385 struct mlx5_ifc_ppcnt_reg_bits { 9386 u8 swid[0x8]; 9387 u8 local_port[0x8]; 9388 u8 pnat[0x2]; 9389 u8 reserved_at_12[0x8]; 9390 u8 grp[0x6]; 9391 9392 u8 clr[0x1]; 9393 u8 reserved_at_21[0x1c]; 9394 u8 prio_tc[0x3]; 9395 9396 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9397 }; 9398 9399 struct mlx5_ifc_mpein_reg_bits { 9400 u8 reserved_at_0[0x2]; 9401 u8 depth[0x6]; 9402 u8 pcie_index[0x8]; 9403 u8 node[0x8]; 9404 u8 reserved_at_18[0x8]; 9405 9406 u8 capability_mask[0x20]; 9407 9408 u8 reserved_at_40[0x8]; 9409 u8 link_width_enabled[0x8]; 9410 u8 link_speed_enabled[0x10]; 9411 9412 u8 lane0_physical_position[0x8]; 9413 u8 link_width_active[0x8]; 9414 u8 link_speed_active[0x10]; 9415 9416 u8 num_of_pfs[0x10]; 9417 u8 num_of_vfs[0x10]; 9418 9419 u8 bdf0[0x10]; 9420 u8 reserved_at_b0[0x10]; 9421 9422 u8 max_read_request_size[0x4]; 9423 u8 max_payload_size[0x4]; 9424 u8 reserved_at_c8[0x5]; 9425 u8 pwr_status[0x3]; 9426 u8 port_type[0x4]; 9427 u8 reserved_at_d4[0xb]; 9428 u8 lane_reversal[0x1]; 9429 9430 u8 reserved_at_e0[0x14]; 9431 u8 pci_power[0xc]; 9432 9433 u8 reserved_at_100[0x20]; 9434 9435 u8 device_status[0x10]; 9436 u8 port_state[0x8]; 9437 u8 reserved_at_138[0x8]; 9438 9439 u8 reserved_at_140[0x10]; 9440 u8 receiver_detect_result[0x10]; 9441 9442 u8 reserved_at_160[0x20]; 9443 }; 9444 9445 struct mlx5_ifc_mpcnt_reg_bits { 9446 u8 reserved_at_0[0x8]; 9447 u8 pcie_index[0x8]; 9448 u8 reserved_at_10[0xa]; 9449 u8 grp[0x6]; 9450 9451 u8 clr[0x1]; 9452 u8 reserved_at_21[0x1f]; 9453 9454 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9455 }; 9456 9457 struct mlx5_ifc_ppad_reg_bits { 9458 u8 reserved_at_0[0x3]; 9459 u8 single_mac[0x1]; 9460 u8 reserved_at_4[0x4]; 9461 u8 local_port[0x8]; 9462 u8 mac_47_32[0x10]; 9463 9464 u8 mac_31_0[0x20]; 9465 9466 u8 reserved_at_40[0x40]; 9467 }; 9468 9469 struct mlx5_ifc_pmtu_reg_bits { 9470 u8 reserved_at_0[0x8]; 9471 u8 local_port[0x8]; 9472 u8 reserved_at_10[0x10]; 9473 9474 u8 max_mtu[0x10]; 9475 u8 reserved_at_30[0x10]; 9476 9477 u8 admin_mtu[0x10]; 9478 u8 reserved_at_50[0x10]; 9479 9480 u8 oper_mtu[0x10]; 9481 u8 reserved_at_70[0x10]; 9482 }; 9483 9484 struct mlx5_ifc_pmpr_reg_bits { 9485 u8 reserved_at_0[0x8]; 9486 u8 module[0x8]; 9487 u8 reserved_at_10[0x10]; 9488 9489 u8 reserved_at_20[0x18]; 9490 u8 attenuation_5g[0x8]; 9491 9492 u8 reserved_at_40[0x18]; 9493 u8 attenuation_7g[0x8]; 9494 9495 u8 reserved_at_60[0x18]; 9496 u8 attenuation_12g[0x8]; 9497 }; 9498 9499 struct mlx5_ifc_pmpe_reg_bits { 9500 u8 reserved_at_0[0x8]; 9501 u8 module[0x8]; 9502 u8 reserved_at_10[0xc]; 9503 u8 module_status[0x4]; 9504 9505 u8 reserved_at_20[0x60]; 9506 }; 9507 9508 struct mlx5_ifc_pmpc_reg_bits { 9509 u8 module_state_updated[32][0x8]; 9510 }; 9511 9512 struct mlx5_ifc_pmlpn_reg_bits { 9513 u8 reserved_at_0[0x4]; 9514 u8 mlpn_status[0x4]; 9515 u8 local_port[0x8]; 9516 u8 reserved_at_10[0x10]; 9517 9518 u8 e[0x1]; 9519 u8 reserved_at_21[0x1f]; 9520 }; 9521 9522 struct mlx5_ifc_pmlp_reg_bits { 9523 u8 rxtx[0x1]; 9524 u8 reserved_at_1[0x7]; 9525 u8 local_port[0x8]; 9526 u8 reserved_at_10[0x8]; 9527 u8 width[0x8]; 9528 9529 u8 lane0_module_mapping[0x20]; 9530 9531 u8 lane1_module_mapping[0x20]; 9532 9533 u8 lane2_module_mapping[0x20]; 9534 9535 u8 lane3_module_mapping[0x20]; 9536 9537 u8 reserved_at_a0[0x160]; 9538 }; 9539 9540 struct mlx5_ifc_pmaos_reg_bits { 9541 u8 reserved_at_0[0x8]; 9542 u8 module[0x8]; 9543 u8 reserved_at_10[0x4]; 9544 u8 admin_status[0x4]; 9545 u8 reserved_at_18[0x4]; 9546 u8 oper_status[0x4]; 9547 9548 u8 ase[0x1]; 9549 u8 ee[0x1]; 9550 u8 reserved_at_22[0x1c]; 9551 u8 e[0x2]; 9552 9553 u8 reserved_at_40[0x40]; 9554 }; 9555 9556 struct mlx5_ifc_plpc_reg_bits { 9557 u8 reserved_at_0[0x4]; 9558 u8 profile_id[0xc]; 9559 u8 reserved_at_10[0x4]; 9560 u8 proto_mask[0x4]; 9561 u8 reserved_at_18[0x8]; 9562 9563 u8 reserved_at_20[0x10]; 9564 u8 lane_speed[0x10]; 9565 9566 u8 reserved_at_40[0x17]; 9567 u8 lpbf[0x1]; 9568 u8 fec_mode_policy[0x8]; 9569 9570 u8 retransmission_capability[0x8]; 9571 u8 fec_mode_capability[0x18]; 9572 9573 u8 retransmission_support_admin[0x8]; 9574 u8 fec_mode_support_admin[0x18]; 9575 9576 u8 retransmission_request_admin[0x8]; 9577 u8 fec_mode_request_admin[0x18]; 9578 9579 u8 reserved_at_c0[0x80]; 9580 }; 9581 9582 struct mlx5_ifc_plib_reg_bits { 9583 u8 reserved_at_0[0x8]; 9584 u8 local_port[0x8]; 9585 u8 reserved_at_10[0x8]; 9586 u8 ib_port[0x8]; 9587 9588 u8 reserved_at_20[0x60]; 9589 }; 9590 9591 struct mlx5_ifc_plbf_reg_bits { 9592 u8 reserved_at_0[0x8]; 9593 u8 local_port[0x8]; 9594 u8 reserved_at_10[0xd]; 9595 u8 lbf_mode[0x3]; 9596 9597 u8 reserved_at_20[0x20]; 9598 }; 9599 9600 struct mlx5_ifc_pipg_reg_bits { 9601 u8 reserved_at_0[0x8]; 9602 u8 local_port[0x8]; 9603 u8 reserved_at_10[0x10]; 9604 9605 u8 dic[0x1]; 9606 u8 reserved_at_21[0x19]; 9607 u8 ipg[0x4]; 9608 u8 reserved_at_3e[0x2]; 9609 }; 9610 9611 struct mlx5_ifc_pifr_reg_bits { 9612 u8 reserved_at_0[0x8]; 9613 u8 local_port[0x8]; 9614 u8 reserved_at_10[0x10]; 9615 9616 u8 reserved_at_20[0xe0]; 9617 9618 u8 port_filter[8][0x20]; 9619 9620 u8 port_filter_update_en[8][0x20]; 9621 }; 9622 9623 struct mlx5_ifc_pfcc_reg_bits { 9624 u8 reserved_at_0[0x8]; 9625 u8 local_port[0x8]; 9626 u8 reserved_at_10[0xb]; 9627 u8 ppan_mask_n[0x1]; 9628 u8 minor_stall_mask[0x1]; 9629 u8 critical_stall_mask[0x1]; 9630 u8 reserved_at_1e[0x2]; 9631 9632 u8 ppan[0x4]; 9633 u8 reserved_at_24[0x4]; 9634 u8 prio_mask_tx[0x8]; 9635 u8 reserved_at_30[0x8]; 9636 u8 prio_mask_rx[0x8]; 9637 9638 u8 pptx[0x1]; 9639 u8 aptx[0x1]; 9640 u8 pptx_mask_n[0x1]; 9641 u8 reserved_at_43[0x5]; 9642 u8 pfctx[0x8]; 9643 u8 reserved_at_50[0x10]; 9644 9645 u8 pprx[0x1]; 9646 u8 aprx[0x1]; 9647 u8 pprx_mask_n[0x1]; 9648 u8 reserved_at_63[0x5]; 9649 u8 pfcrx[0x8]; 9650 u8 reserved_at_70[0x10]; 9651 9652 u8 device_stall_minor_watermark[0x10]; 9653 u8 device_stall_critical_watermark[0x10]; 9654 9655 u8 reserved_at_a0[0x60]; 9656 }; 9657 9658 struct mlx5_ifc_pelc_reg_bits { 9659 u8 op[0x4]; 9660 u8 reserved_at_4[0x4]; 9661 u8 local_port[0x8]; 9662 u8 reserved_at_10[0x10]; 9663 9664 u8 op_admin[0x8]; 9665 u8 op_capability[0x8]; 9666 u8 op_request[0x8]; 9667 u8 op_active[0x8]; 9668 9669 u8 admin[0x40]; 9670 9671 u8 capability[0x40]; 9672 9673 u8 request[0x40]; 9674 9675 u8 active[0x40]; 9676 9677 u8 reserved_at_140[0x80]; 9678 }; 9679 9680 struct mlx5_ifc_peir_reg_bits { 9681 u8 reserved_at_0[0x8]; 9682 u8 local_port[0x8]; 9683 u8 reserved_at_10[0x10]; 9684 9685 u8 reserved_at_20[0xc]; 9686 u8 error_count[0x4]; 9687 u8 reserved_at_30[0x10]; 9688 9689 u8 reserved_at_40[0xc]; 9690 u8 lane[0x4]; 9691 u8 reserved_at_50[0x8]; 9692 u8 error_type[0x8]; 9693 }; 9694 9695 struct mlx5_ifc_mpegc_reg_bits { 9696 u8 reserved_at_0[0x30]; 9697 u8 field_select[0x10]; 9698 9699 u8 tx_overflow_sense[0x1]; 9700 u8 mark_cqe[0x1]; 9701 u8 mark_cnp[0x1]; 9702 u8 reserved_at_43[0x1b]; 9703 u8 tx_lossy_overflow_oper[0x2]; 9704 9705 u8 reserved_at_60[0x100]; 9706 }; 9707 9708 enum { 9709 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9710 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9711 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9712 }; 9713 9714 struct mlx5_ifc_mtutc_reg_bits { 9715 u8 reserved_at_0[0x1c]; 9716 u8 operation[0x4]; 9717 9718 u8 freq_adjustment[0x20]; 9719 9720 u8 reserved_at_40[0x40]; 9721 9722 u8 utc_sec[0x20]; 9723 9724 u8 reserved_at_a0[0x2]; 9725 u8 utc_nsec[0x1e]; 9726 9727 u8 time_adjustment[0x20]; 9728 }; 9729 9730 struct mlx5_ifc_pcam_enhanced_features_bits { 9731 u8 reserved_at_0[0x68]; 9732 u8 fec_50G_per_lane_in_pplm[0x1]; 9733 u8 reserved_at_69[0x4]; 9734 u8 rx_icrc_encapsulated_counter[0x1]; 9735 u8 reserved_at_6e[0x4]; 9736 u8 ptys_extended_ethernet[0x1]; 9737 u8 reserved_at_73[0x3]; 9738 u8 pfcc_mask[0x1]; 9739 u8 reserved_at_77[0x3]; 9740 u8 per_lane_error_counters[0x1]; 9741 u8 rx_buffer_fullness_counters[0x1]; 9742 u8 ptys_connector_type[0x1]; 9743 u8 reserved_at_7d[0x1]; 9744 u8 ppcnt_discard_group[0x1]; 9745 u8 ppcnt_statistical_group[0x1]; 9746 }; 9747 9748 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9749 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9750 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9751 9752 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9753 u8 pplm[0x1]; 9754 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9755 9756 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9757 u8 pbmc[0x1]; 9758 u8 pptb[0x1]; 9759 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9760 u8 ppcnt[0x1]; 9761 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9762 }; 9763 9764 struct mlx5_ifc_pcam_reg_bits { 9765 u8 reserved_at_0[0x8]; 9766 u8 feature_group[0x8]; 9767 u8 reserved_at_10[0x8]; 9768 u8 access_reg_group[0x8]; 9769 9770 u8 reserved_at_20[0x20]; 9771 9772 union { 9773 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9774 u8 reserved_at_0[0x80]; 9775 } port_access_reg_cap_mask; 9776 9777 u8 reserved_at_c0[0x80]; 9778 9779 union { 9780 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9781 u8 reserved_at_0[0x80]; 9782 } feature_cap_mask; 9783 9784 u8 reserved_at_1c0[0xc0]; 9785 }; 9786 9787 struct mlx5_ifc_mcam_enhanced_features_bits { 9788 u8 reserved_at_0[0x5d]; 9789 u8 mcia_32dwords[0x1]; 9790 u8 reserved_at_5e[0xc]; 9791 u8 reset_state[0x1]; 9792 u8 ptpcyc2realtime_modify[0x1]; 9793 u8 reserved_at_6c[0x2]; 9794 u8 pci_status_and_power[0x1]; 9795 u8 reserved_at_6f[0x5]; 9796 u8 mark_tx_action_cnp[0x1]; 9797 u8 mark_tx_action_cqe[0x1]; 9798 u8 dynamic_tx_overflow[0x1]; 9799 u8 reserved_at_77[0x4]; 9800 u8 pcie_outbound_stalled[0x1]; 9801 u8 tx_overflow_buffer_pkt[0x1]; 9802 u8 mtpps_enh_out_per_adj[0x1]; 9803 u8 mtpps_fs[0x1]; 9804 u8 pcie_performance_group[0x1]; 9805 }; 9806 9807 struct mlx5_ifc_mcam_access_reg_bits { 9808 u8 reserved_at_0[0x1c]; 9809 u8 mcda[0x1]; 9810 u8 mcc[0x1]; 9811 u8 mcqi[0x1]; 9812 u8 mcqs[0x1]; 9813 9814 u8 regs_95_to_87[0x9]; 9815 u8 mpegc[0x1]; 9816 u8 mtutc[0x1]; 9817 u8 regs_84_to_68[0x11]; 9818 u8 tracer_registers[0x4]; 9819 9820 u8 regs_63_to_46[0x12]; 9821 u8 mrtc[0x1]; 9822 u8 regs_44_to_32[0xd]; 9823 9824 u8 regs_31_to_0[0x20]; 9825 }; 9826 9827 struct mlx5_ifc_mcam_access_reg_bits1 { 9828 u8 regs_127_to_96[0x20]; 9829 9830 u8 regs_95_to_64[0x20]; 9831 9832 u8 regs_63_to_32[0x20]; 9833 9834 u8 regs_31_to_0[0x20]; 9835 }; 9836 9837 struct mlx5_ifc_mcam_access_reg_bits2 { 9838 u8 regs_127_to_99[0x1d]; 9839 u8 mirc[0x1]; 9840 u8 regs_97_to_96[0x2]; 9841 9842 u8 regs_95_to_64[0x20]; 9843 9844 u8 regs_63_to_32[0x20]; 9845 9846 u8 regs_31_to_0[0x20]; 9847 }; 9848 9849 struct mlx5_ifc_mcam_reg_bits { 9850 u8 reserved_at_0[0x8]; 9851 u8 feature_group[0x8]; 9852 u8 reserved_at_10[0x8]; 9853 u8 access_reg_group[0x8]; 9854 9855 u8 reserved_at_20[0x20]; 9856 9857 union { 9858 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9859 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9860 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9861 u8 reserved_at_0[0x80]; 9862 } mng_access_reg_cap_mask; 9863 9864 u8 reserved_at_c0[0x80]; 9865 9866 union { 9867 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9868 u8 reserved_at_0[0x80]; 9869 } mng_feature_cap_mask; 9870 9871 u8 reserved_at_1c0[0x80]; 9872 }; 9873 9874 struct mlx5_ifc_qcam_access_reg_cap_mask { 9875 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9876 u8 qpdpm[0x1]; 9877 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9878 u8 qdpm[0x1]; 9879 u8 qpts[0x1]; 9880 u8 qcap[0x1]; 9881 u8 qcam_access_reg_cap_mask_0[0x1]; 9882 }; 9883 9884 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9885 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9886 u8 qpts_trust_both[0x1]; 9887 }; 9888 9889 struct mlx5_ifc_qcam_reg_bits { 9890 u8 reserved_at_0[0x8]; 9891 u8 feature_group[0x8]; 9892 u8 reserved_at_10[0x8]; 9893 u8 access_reg_group[0x8]; 9894 u8 reserved_at_20[0x20]; 9895 9896 union { 9897 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9898 u8 reserved_at_0[0x80]; 9899 } qos_access_reg_cap_mask; 9900 9901 u8 reserved_at_c0[0x80]; 9902 9903 union { 9904 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9905 u8 reserved_at_0[0x80]; 9906 } qos_feature_cap_mask; 9907 9908 u8 reserved_at_1c0[0x80]; 9909 }; 9910 9911 struct mlx5_ifc_core_dump_reg_bits { 9912 u8 reserved_at_0[0x18]; 9913 u8 core_dump_type[0x8]; 9914 9915 u8 reserved_at_20[0x30]; 9916 u8 vhca_id[0x10]; 9917 9918 u8 reserved_at_60[0x8]; 9919 u8 qpn[0x18]; 9920 u8 reserved_at_80[0x180]; 9921 }; 9922 9923 struct mlx5_ifc_pcap_reg_bits { 9924 u8 reserved_at_0[0x8]; 9925 u8 local_port[0x8]; 9926 u8 reserved_at_10[0x10]; 9927 9928 u8 port_capability_mask[4][0x20]; 9929 }; 9930 9931 struct mlx5_ifc_paos_reg_bits { 9932 u8 swid[0x8]; 9933 u8 local_port[0x8]; 9934 u8 reserved_at_10[0x4]; 9935 u8 admin_status[0x4]; 9936 u8 reserved_at_18[0x4]; 9937 u8 oper_status[0x4]; 9938 9939 u8 ase[0x1]; 9940 u8 ee[0x1]; 9941 u8 reserved_at_22[0x1c]; 9942 u8 e[0x2]; 9943 9944 u8 reserved_at_40[0x40]; 9945 }; 9946 9947 struct mlx5_ifc_pamp_reg_bits { 9948 u8 reserved_at_0[0x8]; 9949 u8 opamp_group[0x8]; 9950 u8 reserved_at_10[0xc]; 9951 u8 opamp_group_type[0x4]; 9952 9953 u8 start_index[0x10]; 9954 u8 reserved_at_30[0x4]; 9955 u8 num_of_indices[0xc]; 9956 9957 u8 index_data[18][0x10]; 9958 }; 9959 9960 struct mlx5_ifc_pcmr_reg_bits { 9961 u8 reserved_at_0[0x8]; 9962 u8 local_port[0x8]; 9963 u8 reserved_at_10[0x10]; 9964 9965 u8 entropy_force_cap[0x1]; 9966 u8 entropy_calc_cap[0x1]; 9967 u8 entropy_gre_calc_cap[0x1]; 9968 u8 reserved_at_23[0xf]; 9969 u8 rx_ts_over_crc_cap[0x1]; 9970 u8 reserved_at_33[0xb]; 9971 u8 fcs_cap[0x1]; 9972 u8 reserved_at_3f[0x1]; 9973 9974 u8 entropy_force[0x1]; 9975 u8 entropy_calc[0x1]; 9976 u8 entropy_gre_calc[0x1]; 9977 u8 reserved_at_43[0xf]; 9978 u8 rx_ts_over_crc[0x1]; 9979 u8 reserved_at_53[0xb]; 9980 u8 fcs_chk[0x1]; 9981 u8 reserved_at_5f[0x1]; 9982 }; 9983 9984 struct mlx5_ifc_lane_2_module_mapping_bits { 9985 u8 reserved_at_0[0x4]; 9986 u8 rx_lane[0x4]; 9987 u8 reserved_at_8[0x4]; 9988 u8 tx_lane[0x4]; 9989 u8 reserved_at_10[0x8]; 9990 u8 module[0x8]; 9991 }; 9992 9993 struct mlx5_ifc_bufferx_reg_bits { 9994 u8 reserved_at_0[0x6]; 9995 u8 lossy[0x1]; 9996 u8 epsb[0x1]; 9997 u8 reserved_at_8[0x8]; 9998 u8 size[0x10]; 9999 10000 u8 xoff_threshold[0x10]; 10001 u8 xon_threshold[0x10]; 10002 }; 10003 10004 struct mlx5_ifc_set_node_in_bits { 10005 u8 node_description[64][0x8]; 10006 }; 10007 10008 struct mlx5_ifc_register_power_settings_bits { 10009 u8 reserved_at_0[0x18]; 10010 u8 power_settings_level[0x8]; 10011 10012 u8 reserved_at_20[0x60]; 10013 }; 10014 10015 struct mlx5_ifc_register_host_endianness_bits { 10016 u8 he[0x1]; 10017 u8 reserved_at_1[0x1f]; 10018 10019 u8 reserved_at_20[0x60]; 10020 }; 10021 10022 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10023 u8 reserved_at_0[0x20]; 10024 10025 u8 mkey[0x20]; 10026 10027 u8 addressh_63_32[0x20]; 10028 10029 u8 addressl_31_0[0x20]; 10030 }; 10031 10032 struct mlx5_ifc_ud_adrs_vector_bits { 10033 u8 dc_key[0x40]; 10034 10035 u8 ext[0x1]; 10036 u8 reserved_at_41[0x7]; 10037 u8 destination_qp_dct[0x18]; 10038 10039 u8 static_rate[0x4]; 10040 u8 sl_eth_prio[0x4]; 10041 u8 fl[0x1]; 10042 u8 mlid[0x7]; 10043 u8 rlid_udp_sport[0x10]; 10044 10045 u8 reserved_at_80[0x20]; 10046 10047 u8 rmac_47_16[0x20]; 10048 10049 u8 rmac_15_0[0x10]; 10050 u8 tclass[0x8]; 10051 u8 hop_limit[0x8]; 10052 10053 u8 reserved_at_e0[0x1]; 10054 u8 grh[0x1]; 10055 u8 reserved_at_e2[0x2]; 10056 u8 src_addr_index[0x8]; 10057 u8 flow_label[0x14]; 10058 10059 u8 rgid_rip[16][0x8]; 10060 }; 10061 10062 struct mlx5_ifc_pages_req_event_bits { 10063 u8 reserved_at_0[0x10]; 10064 u8 function_id[0x10]; 10065 10066 u8 num_pages[0x20]; 10067 10068 u8 reserved_at_40[0xa0]; 10069 }; 10070 10071 struct mlx5_ifc_eqe_bits { 10072 u8 reserved_at_0[0x8]; 10073 u8 event_type[0x8]; 10074 u8 reserved_at_10[0x8]; 10075 u8 event_sub_type[0x8]; 10076 10077 u8 reserved_at_20[0xe0]; 10078 10079 union mlx5_ifc_event_auto_bits event_data; 10080 10081 u8 reserved_at_1e0[0x10]; 10082 u8 signature[0x8]; 10083 u8 reserved_at_1f8[0x7]; 10084 u8 owner[0x1]; 10085 }; 10086 10087 enum { 10088 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10089 }; 10090 10091 struct mlx5_ifc_cmd_queue_entry_bits { 10092 u8 type[0x8]; 10093 u8 reserved_at_8[0x18]; 10094 10095 u8 input_length[0x20]; 10096 10097 u8 input_mailbox_pointer_63_32[0x20]; 10098 10099 u8 input_mailbox_pointer_31_9[0x17]; 10100 u8 reserved_at_77[0x9]; 10101 10102 u8 command_input_inline_data[16][0x8]; 10103 10104 u8 command_output_inline_data[16][0x8]; 10105 10106 u8 output_mailbox_pointer_63_32[0x20]; 10107 10108 u8 output_mailbox_pointer_31_9[0x17]; 10109 u8 reserved_at_1b7[0x9]; 10110 10111 u8 output_length[0x20]; 10112 10113 u8 token[0x8]; 10114 u8 signature[0x8]; 10115 u8 reserved_at_1f0[0x8]; 10116 u8 status[0x7]; 10117 u8 ownership[0x1]; 10118 }; 10119 10120 struct mlx5_ifc_cmd_out_bits { 10121 u8 status[0x8]; 10122 u8 reserved_at_8[0x18]; 10123 10124 u8 syndrome[0x20]; 10125 10126 u8 command_output[0x20]; 10127 }; 10128 10129 struct mlx5_ifc_cmd_in_bits { 10130 u8 opcode[0x10]; 10131 u8 reserved_at_10[0x10]; 10132 10133 u8 reserved_at_20[0x10]; 10134 u8 op_mod[0x10]; 10135 10136 u8 command[][0x20]; 10137 }; 10138 10139 struct mlx5_ifc_cmd_if_box_bits { 10140 u8 mailbox_data[512][0x8]; 10141 10142 u8 reserved_at_1000[0x180]; 10143 10144 u8 next_pointer_63_32[0x20]; 10145 10146 u8 next_pointer_31_10[0x16]; 10147 u8 reserved_at_11b6[0xa]; 10148 10149 u8 block_number[0x20]; 10150 10151 u8 reserved_at_11e0[0x8]; 10152 u8 token[0x8]; 10153 u8 ctrl_signature[0x8]; 10154 u8 signature[0x8]; 10155 }; 10156 10157 struct mlx5_ifc_mtt_bits { 10158 u8 ptag_63_32[0x20]; 10159 10160 u8 ptag_31_8[0x18]; 10161 u8 reserved_at_38[0x6]; 10162 u8 wr_en[0x1]; 10163 u8 rd_en[0x1]; 10164 }; 10165 10166 struct mlx5_ifc_query_wol_rol_out_bits { 10167 u8 status[0x8]; 10168 u8 reserved_at_8[0x18]; 10169 10170 u8 syndrome[0x20]; 10171 10172 u8 reserved_at_40[0x10]; 10173 u8 rol_mode[0x8]; 10174 u8 wol_mode[0x8]; 10175 10176 u8 reserved_at_60[0x20]; 10177 }; 10178 10179 struct mlx5_ifc_query_wol_rol_in_bits { 10180 u8 opcode[0x10]; 10181 u8 reserved_at_10[0x10]; 10182 10183 u8 reserved_at_20[0x10]; 10184 u8 op_mod[0x10]; 10185 10186 u8 reserved_at_40[0x40]; 10187 }; 10188 10189 struct mlx5_ifc_set_wol_rol_out_bits { 10190 u8 status[0x8]; 10191 u8 reserved_at_8[0x18]; 10192 10193 u8 syndrome[0x20]; 10194 10195 u8 reserved_at_40[0x40]; 10196 }; 10197 10198 struct mlx5_ifc_set_wol_rol_in_bits { 10199 u8 opcode[0x10]; 10200 u8 reserved_at_10[0x10]; 10201 10202 u8 reserved_at_20[0x10]; 10203 u8 op_mod[0x10]; 10204 10205 u8 rol_mode_valid[0x1]; 10206 u8 wol_mode_valid[0x1]; 10207 u8 reserved_at_42[0xe]; 10208 u8 rol_mode[0x8]; 10209 u8 wol_mode[0x8]; 10210 10211 u8 reserved_at_60[0x20]; 10212 }; 10213 10214 enum { 10215 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10216 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10217 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10218 }; 10219 10220 enum { 10221 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10222 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10223 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10224 }; 10225 10226 enum { 10227 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10228 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10229 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10230 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10231 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10232 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10233 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10234 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10237 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10238 }; 10239 10240 struct mlx5_ifc_initial_seg_bits { 10241 u8 fw_rev_minor[0x10]; 10242 u8 fw_rev_major[0x10]; 10243 10244 u8 cmd_interface_rev[0x10]; 10245 u8 fw_rev_subminor[0x10]; 10246 10247 u8 reserved_at_40[0x40]; 10248 10249 u8 cmdq_phy_addr_63_32[0x20]; 10250 10251 u8 cmdq_phy_addr_31_12[0x14]; 10252 u8 reserved_at_b4[0x2]; 10253 u8 nic_interface[0x2]; 10254 u8 log_cmdq_size[0x4]; 10255 u8 log_cmdq_stride[0x4]; 10256 10257 u8 command_doorbell_vector[0x20]; 10258 10259 u8 reserved_at_e0[0xf00]; 10260 10261 u8 initializing[0x1]; 10262 u8 reserved_at_fe1[0x4]; 10263 u8 nic_interface_supported[0x3]; 10264 u8 embedded_cpu[0x1]; 10265 u8 reserved_at_fe9[0x17]; 10266 10267 struct mlx5_ifc_health_buffer_bits health_buffer; 10268 10269 u8 no_dram_nic_offset[0x20]; 10270 10271 u8 reserved_at_1220[0x6e40]; 10272 10273 u8 reserved_at_8060[0x1f]; 10274 u8 clear_int[0x1]; 10275 10276 u8 health_syndrome[0x8]; 10277 u8 health_counter[0x18]; 10278 10279 u8 reserved_at_80a0[0x17fc0]; 10280 }; 10281 10282 struct mlx5_ifc_mtpps_reg_bits { 10283 u8 reserved_at_0[0xc]; 10284 u8 cap_number_of_pps_pins[0x4]; 10285 u8 reserved_at_10[0x4]; 10286 u8 cap_max_num_of_pps_in_pins[0x4]; 10287 u8 reserved_at_18[0x4]; 10288 u8 cap_max_num_of_pps_out_pins[0x4]; 10289 10290 u8 reserved_at_20[0x24]; 10291 u8 cap_pin_3_mode[0x4]; 10292 u8 reserved_at_48[0x4]; 10293 u8 cap_pin_2_mode[0x4]; 10294 u8 reserved_at_50[0x4]; 10295 u8 cap_pin_1_mode[0x4]; 10296 u8 reserved_at_58[0x4]; 10297 u8 cap_pin_0_mode[0x4]; 10298 10299 u8 reserved_at_60[0x4]; 10300 u8 cap_pin_7_mode[0x4]; 10301 u8 reserved_at_68[0x4]; 10302 u8 cap_pin_6_mode[0x4]; 10303 u8 reserved_at_70[0x4]; 10304 u8 cap_pin_5_mode[0x4]; 10305 u8 reserved_at_78[0x4]; 10306 u8 cap_pin_4_mode[0x4]; 10307 10308 u8 field_select[0x20]; 10309 u8 reserved_at_a0[0x60]; 10310 10311 u8 enable[0x1]; 10312 u8 reserved_at_101[0xb]; 10313 u8 pattern[0x4]; 10314 u8 reserved_at_110[0x4]; 10315 u8 pin_mode[0x4]; 10316 u8 pin[0x8]; 10317 10318 u8 reserved_at_120[0x20]; 10319 10320 u8 time_stamp[0x40]; 10321 10322 u8 out_pulse_duration[0x10]; 10323 u8 out_periodic_adjustment[0x10]; 10324 u8 enhanced_out_periodic_adjustment[0x20]; 10325 10326 u8 reserved_at_1c0[0x20]; 10327 }; 10328 10329 struct mlx5_ifc_mtppse_reg_bits { 10330 u8 reserved_at_0[0x18]; 10331 u8 pin[0x8]; 10332 u8 event_arm[0x1]; 10333 u8 reserved_at_21[0x1b]; 10334 u8 event_generation_mode[0x4]; 10335 u8 reserved_at_40[0x40]; 10336 }; 10337 10338 struct mlx5_ifc_mcqs_reg_bits { 10339 u8 last_index_flag[0x1]; 10340 u8 reserved_at_1[0x7]; 10341 u8 fw_device[0x8]; 10342 u8 component_index[0x10]; 10343 10344 u8 reserved_at_20[0x10]; 10345 u8 identifier[0x10]; 10346 10347 u8 reserved_at_40[0x17]; 10348 u8 component_status[0x5]; 10349 u8 component_update_state[0x4]; 10350 10351 u8 last_update_state_changer_type[0x4]; 10352 u8 last_update_state_changer_host_id[0x4]; 10353 u8 reserved_at_68[0x18]; 10354 }; 10355 10356 struct mlx5_ifc_mcqi_cap_bits { 10357 u8 supported_info_bitmask[0x20]; 10358 10359 u8 component_size[0x20]; 10360 10361 u8 max_component_size[0x20]; 10362 10363 u8 log_mcda_word_size[0x4]; 10364 u8 reserved_at_64[0xc]; 10365 u8 mcda_max_write_size[0x10]; 10366 10367 u8 rd_en[0x1]; 10368 u8 reserved_at_81[0x1]; 10369 u8 match_chip_id[0x1]; 10370 u8 match_psid[0x1]; 10371 u8 check_user_timestamp[0x1]; 10372 u8 match_base_guid_mac[0x1]; 10373 u8 reserved_at_86[0x1a]; 10374 }; 10375 10376 struct mlx5_ifc_mcqi_version_bits { 10377 u8 reserved_at_0[0x2]; 10378 u8 build_time_valid[0x1]; 10379 u8 user_defined_time_valid[0x1]; 10380 u8 reserved_at_4[0x14]; 10381 u8 version_string_length[0x8]; 10382 10383 u8 version[0x20]; 10384 10385 u8 build_time[0x40]; 10386 10387 u8 user_defined_time[0x40]; 10388 10389 u8 build_tool_version[0x20]; 10390 10391 u8 reserved_at_e0[0x20]; 10392 10393 u8 version_string[92][0x8]; 10394 }; 10395 10396 struct mlx5_ifc_mcqi_activation_method_bits { 10397 u8 pending_server_ac_power_cycle[0x1]; 10398 u8 pending_server_dc_power_cycle[0x1]; 10399 u8 pending_server_reboot[0x1]; 10400 u8 pending_fw_reset[0x1]; 10401 u8 auto_activate[0x1]; 10402 u8 all_hosts_sync[0x1]; 10403 u8 device_hw_reset[0x1]; 10404 u8 reserved_at_7[0x19]; 10405 }; 10406 10407 union mlx5_ifc_mcqi_reg_data_bits { 10408 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10409 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10410 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10411 }; 10412 10413 struct mlx5_ifc_mcqi_reg_bits { 10414 u8 read_pending_component[0x1]; 10415 u8 reserved_at_1[0xf]; 10416 u8 component_index[0x10]; 10417 10418 u8 reserved_at_20[0x20]; 10419 10420 u8 reserved_at_40[0x1b]; 10421 u8 info_type[0x5]; 10422 10423 u8 info_size[0x20]; 10424 10425 u8 offset[0x20]; 10426 10427 u8 reserved_at_a0[0x10]; 10428 u8 data_size[0x10]; 10429 10430 union mlx5_ifc_mcqi_reg_data_bits data[]; 10431 }; 10432 10433 struct mlx5_ifc_mcc_reg_bits { 10434 u8 reserved_at_0[0x4]; 10435 u8 time_elapsed_since_last_cmd[0xc]; 10436 u8 reserved_at_10[0x8]; 10437 u8 instruction[0x8]; 10438 10439 u8 reserved_at_20[0x10]; 10440 u8 component_index[0x10]; 10441 10442 u8 reserved_at_40[0x8]; 10443 u8 update_handle[0x18]; 10444 10445 u8 handle_owner_type[0x4]; 10446 u8 handle_owner_host_id[0x4]; 10447 u8 reserved_at_68[0x1]; 10448 u8 control_progress[0x7]; 10449 u8 error_code[0x8]; 10450 u8 reserved_at_78[0x4]; 10451 u8 control_state[0x4]; 10452 10453 u8 component_size[0x20]; 10454 10455 u8 reserved_at_a0[0x60]; 10456 }; 10457 10458 struct mlx5_ifc_mcda_reg_bits { 10459 u8 reserved_at_0[0x8]; 10460 u8 update_handle[0x18]; 10461 10462 u8 offset[0x20]; 10463 10464 u8 reserved_at_40[0x10]; 10465 u8 size[0x10]; 10466 10467 u8 reserved_at_60[0x20]; 10468 10469 u8 data[][0x20]; 10470 }; 10471 10472 enum { 10473 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10474 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10475 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10476 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10477 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10478 }; 10479 10480 enum { 10481 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10482 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10483 }; 10484 10485 enum { 10486 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10487 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10488 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10489 }; 10490 10491 struct mlx5_ifc_mfrl_reg_bits { 10492 u8 reserved_at_0[0x20]; 10493 10494 u8 reserved_at_20[0x2]; 10495 u8 pci_sync_for_fw_update_start[0x1]; 10496 u8 pci_sync_for_fw_update_resp[0x2]; 10497 u8 rst_type_sel[0x3]; 10498 u8 reserved_at_28[0x4]; 10499 u8 reset_state[0x4]; 10500 u8 reset_type[0x8]; 10501 u8 reset_level[0x8]; 10502 }; 10503 10504 struct mlx5_ifc_mirc_reg_bits { 10505 u8 reserved_at_0[0x18]; 10506 u8 status_code[0x8]; 10507 10508 u8 reserved_at_20[0x20]; 10509 }; 10510 10511 struct mlx5_ifc_pddr_monitor_opcode_bits { 10512 u8 reserved_at_0[0x10]; 10513 u8 monitor_opcode[0x10]; 10514 }; 10515 10516 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10517 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10518 u8 reserved_at_0[0x20]; 10519 }; 10520 10521 enum { 10522 /* Monitor opcodes */ 10523 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10524 }; 10525 10526 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10527 u8 reserved_at_0[0x10]; 10528 u8 group_opcode[0x10]; 10529 10530 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10531 10532 u8 reserved_at_40[0x20]; 10533 10534 u8 status_message[59][0x20]; 10535 }; 10536 10537 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10538 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10539 u8 reserved_at_0[0x7c0]; 10540 }; 10541 10542 enum { 10543 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10544 }; 10545 10546 struct mlx5_ifc_pddr_reg_bits { 10547 u8 reserved_at_0[0x8]; 10548 u8 local_port[0x8]; 10549 u8 pnat[0x2]; 10550 u8 reserved_at_12[0xe]; 10551 10552 u8 reserved_at_20[0x18]; 10553 u8 page_select[0x8]; 10554 10555 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10556 }; 10557 10558 struct mlx5_ifc_mrtc_reg_bits { 10559 u8 time_synced[0x1]; 10560 u8 reserved_at_1[0x1f]; 10561 10562 u8 reserved_at_20[0x20]; 10563 10564 u8 time_h[0x20]; 10565 10566 u8 time_l[0x20]; 10567 }; 10568 10569 union mlx5_ifc_ports_control_registers_document_bits { 10570 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10571 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10572 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10573 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10574 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10575 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10576 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10577 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10578 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10579 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10580 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10581 struct mlx5_ifc_paos_reg_bits paos_reg; 10582 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10583 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10584 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10585 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10586 struct mlx5_ifc_peir_reg_bits peir_reg; 10587 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10588 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10589 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10590 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10591 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10592 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10593 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10594 struct mlx5_ifc_plib_reg_bits plib_reg; 10595 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10596 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10597 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10598 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10599 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10600 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10601 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10602 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10603 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10604 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10605 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10606 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10607 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10608 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10609 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10610 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10611 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10612 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10613 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10614 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10615 struct mlx5_ifc_pude_reg_bits pude_reg; 10616 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10617 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10618 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10619 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10620 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10621 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10622 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10623 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10624 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10625 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10626 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10627 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10628 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10629 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10630 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10631 u8 reserved_at_0[0x60e0]; 10632 }; 10633 10634 union mlx5_ifc_debug_enhancements_document_bits { 10635 struct mlx5_ifc_health_buffer_bits health_buffer; 10636 u8 reserved_at_0[0x200]; 10637 }; 10638 10639 union mlx5_ifc_uplink_pci_interface_document_bits { 10640 struct mlx5_ifc_initial_seg_bits initial_seg; 10641 u8 reserved_at_0[0x20060]; 10642 }; 10643 10644 struct mlx5_ifc_set_flow_table_root_out_bits { 10645 u8 status[0x8]; 10646 u8 reserved_at_8[0x18]; 10647 10648 u8 syndrome[0x20]; 10649 10650 u8 reserved_at_40[0x40]; 10651 }; 10652 10653 struct mlx5_ifc_set_flow_table_root_in_bits { 10654 u8 opcode[0x10]; 10655 u8 reserved_at_10[0x10]; 10656 10657 u8 reserved_at_20[0x10]; 10658 u8 op_mod[0x10]; 10659 10660 u8 other_vport[0x1]; 10661 u8 reserved_at_41[0xf]; 10662 u8 vport_number[0x10]; 10663 10664 u8 reserved_at_60[0x20]; 10665 10666 u8 table_type[0x8]; 10667 u8 reserved_at_88[0x7]; 10668 u8 table_of_other_vport[0x1]; 10669 u8 table_vport_number[0x10]; 10670 10671 u8 reserved_at_a0[0x8]; 10672 u8 table_id[0x18]; 10673 10674 u8 reserved_at_c0[0x8]; 10675 u8 underlay_qpn[0x18]; 10676 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10677 u8 reserved_at_e1[0xf]; 10678 u8 table_eswitch_owner_vhca_id[0x10]; 10679 u8 reserved_at_100[0x100]; 10680 }; 10681 10682 enum { 10683 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10684 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10685 }; 10686 10687 struct mlx5_ifc_modify_flow_table_out_bits { 10688 u8 status[0x8]; 10689 u8 reserved_at_8[0x18]; 10690 10691 u8 syndrome[0x20]; 10692 10693 u8 reserved_at_40[0x40]; 10694 }; 10695 10696 struct mlx5_ifc_modify_flow_table_in_bits { 10697 u8 opcode[0x10]; 10698 u8 reserved_at_10[0x10]; 10699 10700 u8 reserved_at_20[0x10]; 10701 u8 op_mod[0x10]; 10702 10703 u8 other_vport[0x1]; 10704 u8 reserved_at_41[0xf]; 10705 u8 vport_number[0x10]; 10706 10707 u8 reserved_at_60[0x10]; 10708 u8 modify_field_select[0x10]; 10709 10710 u8 table_type[0x8]; 10711 u8 reserved_at_88[0x18]; 10712 10713 u8 reserved_at_a0[0x8]; 10714 u8 table_id[0x18]; 10715 10716 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10717 }; 10718 10719 struct mlx5_ifc_ets_tcn_config_reg_bits { 10720 u8 g[0x1]; 10721 u8 b[0x1]; 10722 u8 r[0x1]; 10723 u8 reserved_at_3[0x9]; 10724 u8 group[0x4]; 10725 u8 reserved_at_10[0x9]; 10726 u8 bw_allocation[0x7]; 10727 10728 u8 reserved_at_20[0xc]; 10729 u8 max_bw_units[0x4]; 10730 u8 reserved_at_30[0x8]; 10731 u8 max_bw_value[0x8]; 10732 }; 10733 10734 struct mlx5_ifc_ets_global_config_reg_bits { 10735 u8 reserved_at_0[0x2]; 10736 u8 r[0x1]; 10737 u8 reserved_at_3[0x1d]; 10738 10739 u8 reserved_at_20[0xc]; 10740 u8 max_bw_units[0x4]; 10741 u8 reserved_at_30[0x8]; 10742 u8 max_bw_value[0x8]; 10743 }; 10744 10745 struct mlx5_ifc_qetc_reg_bits { 10746 u8 reserved_at_0[0x8]; 10747 u8 port_number[0x8]; 10748 u8 reserved_at_10[0x30]; 10749 10750 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10751 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10752 }; 10753 10754 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10755 u8 e[0x1]; 10756 u8 reserved_at_01[0x0b]; 10757 u8 prio[0x04]; 10758 }; 10759 10760 struct mlx5_ifc_qpdpm_reg_bits { 10761 u8 reserved_at_0[0x8]; 10762 u8 local_port[0x8]; 10763 u8 reserved_at_10[0x10]; 10764 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10765 }; 10766 10767 struct mlx5_ifc_qpts_reg_bits { 10768 u8 reserved_at_0[0x8]; 10769 u8 local_port[0x8]; 10770 u8 reserved_at_10[0x2d]; 10771 u8 trust_state[0x3]; 10772 }; 10773 10774 struct mlx5_ifc_pptb_reg_bits { 10775 u8 reserved_at_0[0x2]; 10776 u8 mm[0x2]; 10777 u8 reserved_at_4[0x4]; 10778 u8 local_port[0x8]; 10779 u8 reserved_at_10[0x6]; 10780 u8 cm[0x1]; 10781 u8 um[0x1]; 10782 u8 pm[0x8]; 10783 10784 u8 prio_x_buff[0x20]; 10785 10786 u8 pm_msb[0x8]; 10787 u8 reserved_at_48[0x10]; 10788 u8 ctrl_buff[0x4]; 10789 u8 untagged_buff[0x4]; 10790 }; 10791 10792 struct mlx5_ifc_sbcam_reg_bits { 10793 u8 reserved_at_0[0x8]; 10794 u8 feature_group[0x8]; 10795 u8 reserved_at_10[0x8]; 10796 u8 access_reg_group[0x8]; 10797 10798 u8 reserved_at_20[0x20]; 10799 10800 u8 sb_access_reg_cap_mask[4][0x20]; 10801 10802 u8 reserved_at_c0[0x80]; 10803 10804 u8 sb_feature_cap_mask[4][0x20]; 10805 10806 u8 reserved_at_1c0[0x40]; 10807 10808 u8 cap_total_buffer_size[0x20]; 10809 10810 u8 cap_cell_size[0x10]; 10811 u8 cap_max_pg_buffers[0x8]; 10812 u8 cap_num_pool_supported[0x8]; 10813 10814 u8 reserved_at_240[0x8]; 10815 u8 cap_sbsr_stat_size[0x8]; 10816 u8 cap_max_tclass_data[0x8]; 10817 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10818 }; 10819 10820 struct mlx5_ifc_pbmc_reg_bits { 10821 u8 reserved_at_0[0x8]; 10822 u8 local_port[0x8]; 10823 u8 reserved_at_10[0x10]; 10824 10825 u8 xoff_timer_value[0x10]; 10826 u8 xoff_refresh[0x10]; 10827 10828 u8 reserved_at_40[0x9]; 10829 u8 fullness_threshold[0x7]; 10830 u8 port_buffer_size[0x10]; 10831 10832 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10833 10834 u8 reserved_at_2e0[0x80]; 10835 }; 10836 10837 struct mlx5_ifc_qtct_reg_bits { 10838 u8 reserved_at_0[0x8]; 10839 u8 port_number[0x8]; 10840 u8 reserved_at_10[0xd]; 10841 u8 prio[0x3]; 10842 10843 u8 reserved_at_20[0x1d]; 10844 u8 tclass[0x3]; 10845 }; 10846 10847 struct mlx5_ifc_mcia_reg_bits { 10848 u8 l[0x1]; 10849 u8 reserved_at_1[0x7]; 10850 u8 module[0x8]; 10851 u8 reserved_at_10[0x8]; 10852 u8 status[0x8]; 10853 10854 u8 i2c_device_address[0x8]; 10855 u8 page_number[0x8]; 10856 u8 device_address[0x10]; 10857 10858 u8 reserved_at_40[0x10]; 10859 u8 size[0x10]; 10860 10861 u8 reserved_at_60[0x20]; 10862 10863 u8 dword_0[0x20]; 10864 u8 dword_1[0x20]; 10865 u8 dword_2[0x20]; 10866 u8 dword_3[0x20]; 10867 u8 dword_4[0x20]; 10868 u8 dword_5[0x20]; 10869 u8 dword_6[0x20]; 10870 u8 dword_7[0x20]; 10871 u8 dword_8[0x20]; 10872 u8 dword_9[0x20]; 10873 u8 dword_10[0x20]; 10874 u8 dword_11[0x20]; 10875 }; 10876 10877 struct mlx5_ifc_dcbx_param_bits { 10878 u8 dcbx_cee_cap[0x1]; 10879 u8 dcbx_ieee_cap[0x1]; 10880 u8 dcbx_standby_cap[0x1]; 10881 u8 reserved_at_3[0x5]; 10882 u8 port_number[0x8]; 10883 u8 reserved_at_10[0xa]; 10884 u8 max_application_table_size[6]; 10885 u8 reserved_at_20[0x15]; 10886 u8 version_oper[0x3]; 10887 u8 reserved_at_38[5]; 10888 u8 version_admin[0x3]; 10889 u8 willing_admin[0x1]; 10890 u8 reserved_at_41[0x3]; 10891 u8 pfc_cap_oper[0x4]; 10892 u8 reserved_at_48[0x4]; 10893 u8 pfc_cap_admin[0x4]; 10894 u8 reserved_at_50[0x4]; 10895 u8 num_of_tc_oper[0x4]; 10896 u8 reserved_at_58[0x4]; 10897 u8 num_of_tc_admin[0x4]; 10898 u8 remote_willing[0x1]; 10899 u8 reserved_at_61[3]; 10900 u8 remote_pfc_cap[4]; 10901 u8 reserved_at_68[0x14]; 10902 u8 remote_num_of_tc[0x4]; 10903 u8 reserved_at_80[0x18]; 10904 u8 error[0x8]; 10905 u8 reserved_at_a0[0x160]; 10906 }; 10907 10908 enum { 10909 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10910 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10911 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10912 }; 10913 10914 struct mlx5_ifc_lagc_bits { 10915 u8 fdb_selection_mode[0x1]; 10916 u8 reserved_at_1[0x14]; 10917 u8 port_select_mode[0x3]; 10918 u8 reserved_at_18[0x5]; 10919 u8 lag_state[0x3]; 10920 10921 u8 reserved_at_20[0x14]; 10922 u8 tx_remap_affinity_2[0x4]; 10923 u8 reserved_at_38[0x4]; 10924 u8 tx_remap_affinity_1[0x4]; 10925 }; 10926 10927 struct mlx5_ifc_create_lag_out_bits { 10928 u8 status[0x8]; 10929 u8 reserved_at_8[0x18]; 10930 10931 u8 syndrome[0x20]; 10932 10933 u8 reserved_at_40[0x40]; 10934 }; 10935 10936 struct mlx5_ifc_create_lag_in_bits { 10937 u8 opcode[0x10]; 10938 u8 reserved_at_10[0x10]; 10939 10940 u8 reserved_at_20[0x10]; 10941 u8 op_mod[0x10]; 10942 10943 struct mlx5_ifc_lagc_bits ctx; 10944 }; 10945 10946 struct mlx5_ifc_modify_lag_out_bits { 10947 u8 status[0x8]; 10948 u8 reserved_at_8[0x18]; 10949 10950 u8 syndrome[0x20]; 10951 10952 u8 reserved_at_40[0x40]; 10953 }; 10954 10955 struct mlx5_ifc_modify_lag_in_bits { 10956 u8 opcode[0x10]; 10957 u8 reserved_at_10[0x10]; 10958 10959 u8 reserved_at_20[0x10]; 10960 u8 op_mod[0x10]; 10961 10962 u8 reserved_at_40[0x20]; 10963 u8 field_select[0x20]; 10964 10965 struct mlx5_ifc_lagc_bits ctx; 10966 }; 10967 10968 struct mlx5_ifc_query_lag_out_bits { 10969 u8 status[0x8]; 10970 u8 reserved_at_8[0x18]; 10971 10972 u8 syndrome[0x20]; 10973 10974 struct mlx5_ifc_lagc_bits ctx; 10975 }; 10976 10977 struct mlx5_ifc_query_lag_in_bits { 10978 u8 opcode[0x10]; 10979 u8 reserved_at_10[0x10]; 10980 10981 u8 reserved_at_20[0x10]; 10982 u8 op_mod[0x10]; 10983 10984 u8 reserved_at_40[0x40]; 10985 }; 10986 10987 struct mlx5_ifc_destroy_lag_out_bits { 10988 u8 status[0x8]; 10989 u8 reserved_at_8[0x18]; 10990 10991 u8 syndrome[0x20]; 10992 10993 u8 reserved_at_40[0x40]; 10994 }; 10995 10996 struct mlx5_ifc_destroy_lag_in_bits { 10997 u8 opcode[0x10]; 10998 u8 reserved_at_10[0x10]; 10999 11000 u8 reserved_at_20[0x10]; 11001 u8 op_mod[0x10]; 11002 11003 u8 reserved_at_40[0x40]; 11004 }; 11005 11006 struct mlx5_ifc_create_vport_lag_out_bits { 11007 u8 status[0x8]; 11008 u8 reserved_at_8[0x18]; 11009 11010 u8 syndrome[0x20]; 11011 11012 u8 reserved_at_40[0x40]; 11013 }; 11014 11015 struct mlx5_ifc_create_vport_lag_in_bits { 11016 u8 opcode[0x10]; 11017 u8 reserved_at_10[0x10]; 11018 11019 u8 reserved_at_20[0x10]; 11020 u8 op_mod[0x10]; 11021 11022 u8 reserved_at_40[0x40]; 11023 }; 11024 11025 struct mlx5_ifc_destroy_vport_lag_out_bits { 11026 u8 status[0x8]; 11027 u8 reserved_at_8[0x18]; 11028 11029 u8 syndrome[0x20]; 11030 11031 u8 reserved_at_40[0x40]; 11032 }; 11033 11034 struct mlx5_ifc_destroy_vport_lag_in_bits { 11035 u8 opcode[0x10]; 11036 u8 reserved_at_10[0x10]; 11037 11038 u8 reserved_at_20[0x10]; 11039 u8 op_mod[0x10]; 11040 11041 u8 reserved_at_40[0x40]; 11042 }; 11043 11044 enum { 11045 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11046 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11047 }; 11048 11049 struct mlx5_ifc_modify_memic_in_bits { 11050 u8 opcode[0x10]; 11051 u8 uid[0x10]; 11052 11053 u8 reserved_at_20[0x10]; 11054 u8 op_mod[0x10]; 11055 11056 u8 reserved_at_40[0x20]; 11057 11058 u8 reserved_at_60[0x18]; 11059 u8 memic_operation_type[0x8]; 11060 11061 u8 memic_start_addr[0x40]; 11062 11063 u8 reserved_at_c0[0x140]; 11064 }; 11065 11066 struct mlx5_ifc_modify_memic_out_bits { 11067 u8 status[0x8]; 11068 u8 reserved_at_8[0x18]; 11069 11070 u8 syndrome[0x20]; 11071 11072 u8 reserved_at_40[0x40]; 11073 11074 u8 memic_operation_addr[0x40]; 11075 11076 u8 reserved_at_c0[0x140]; 11077 }; 11078 11079 struct mlx5_ifc_alloc_memic_in_bits { 11080 u8 opcode[0x10]; 11081 u8 reserved_at_10[0x10]; 11082 11083 u8 reserved_at_20[0x10]; 11084 u8 op_mod[0x10]; 11085 11086 u8 reserved_at_30[0x20]; 11087 11088 u8 reserved_at_40[0x18]; 11089 u8 log_memic_addr_alignment[0x8]; 11090 11091 u8 range_start_addr[0x40]; 11092 11093 u8 range_size[0x20]; 11094 11095 u8 memic_size[0x20]; 11096 }; 11097 11098 struct mlx5_ifc_alloc_memic_out_bits { 11099 u8 status[0x8]; 11100 u8 reserved_at_8[0x18]; 11101 11102 u8 syndrome[0x20]; 11103 11104 u8 memic_start_addr[0x40]; 11105 }; 11106 11107 struct mlx5_ifc_dealloc_memic_in_bits { 11108 u8 opcode[0x10]; 11109 u8 reserved_at_10[0x10]; 11110 11111 u8 reserved_at_20[0x10]; 11112 u8 op_mod[0x10]; 11113 11114 u8 reserved_at_40[0x40]; 11115 11116 u8 memic_start_addr[0x40]; 11117 11118 u8 memic_size[0x20]; 11119 11120 u8 reserved_at_e0[0x20]; 11121 }; 11122 11123 struct mlx5_ifc_dealloc_memic_out_bits { 11124 u8 status[0x8]; 11125 u8 reserved_at_8[0x18]; 11126 11127 u8 syndrome[0x20]; 11128 11129 u8 reserved_at_40[0x40]; 11130 }; 11131 11132 struct mlx5_ifc_umem_bits { 11133 u8 reserved_at_0[0x80]; 11134 11135 u8 reserved_at_80[0x1b]; 11136 u8 log_page_size[0x5]; 11137 11138 u8 page_offset[0x20]; 11139 11140 u8 num_of_mtt[0x40]; 11141 11142 struct mlx5_ifc_mtt_bits mtt[]; 11143 }; 11144 11145 struct mlx5_ifc_uctx_bits { 11146 u8 cap[0x20]; 11147 11148 u8 reserved_at_20[0x160]; 11149 }; 11150 11151 struct mlx5_ifc_sw_icm_bits { 11152 u8 modify_field_select[0x40]; 11153 11154 u8 reserved_at_40[0x18]; 11155 u8 log_sw_icm_size[0x8]; 11156 11157 u8 reserved_at_60[0x20]; 11158 11159 u8 sw_icm_start_addr[0x40]; 11160 11161 u8 reserved_at_c0[0x140]; 11162 }; 11163 11164 struct mlx5_ifc_geneve_tlv_option_bits { 11165 u8 modify_field_select[0x40]; 11166 11167 u8 reserved_at_40[0x18]; 11168 u8 geneve_option_fte_index[0x8]; 11169 11170 u8 option_class[0x10]; 11171 u8 option_type[0x8]; 11172 u8 reserved_at_78[0x3]; 11173 u8 option_data_length[0x5]; 11174 11175 u8 reserved_at_80[0x180]; 11176 }; 11177 11178 struct mlx5_ifc_create_umem_in_bits { 11179 u8 opcode[0x10]; 11180 u8 uid[0x10]; 11181 11182 u8 reserved_at_20[0x10]; 11183 u8 op_mod[0x10]; 11184 11185 u8 reserved_at_40[0x40]; 11186 11187 struct mlx5_ifc_umem_bits umem; 11188 }; 11189 11190 struct mlx5_ifc_create_umem_out_bits { 11191 u8 status[0x8]; 11192 u8 reserved_at_8[0x18]; 11193 11194 u8 syndrome[0x20]; 11195 11196 u8 reserved_at_40[0x8]; 11197 u8 umem_id[0x18]; 11198 11199 u8 reserved_at_60[0x20]; 11200 }; 11201 11202 struct mlx5_ifc_destroy_umem_in_bits { 11203 u8 opcode[0x10]; 11204 u8 uid[0x10]; 11205 11206 u8 reserved_at_20[0x10]; 11207 u8 op_mod[0x10]; 11208 11209 u8 reserved_at_40[0x8]; 11210 u8 umem_id[0x18]; 11211 11212 u8 reserved_at_60[0x20]; 11213 }; 11214 11215 struct mlx5_ifc_destroy_umem_out_bits { 11216 u8 status[0x8]; 11217 u8 reserved_at_8[0x18]; 11218 11219 u8 syndrome[0x20]; 11220 11221 u8 reserved_at_40[0x40]; 11222 }; 11223 11224 struct mlx5_ifc_create_uctx_in_bits { 11225 u8 opcode[0x10]; 11226 u8 reserved_at_10[0x10]; 11227 11228 u8 reserved_at_20[0x10]; 11229 u8 op_mod[0x10]; 11230 11231 u8 reserved_at_40[0x40]; 11232 11233 struct mlx5_ifc_uctx_bits uctx; 11234 }; 11235 11236 struct mlx5_ifc_create_uctx_out_bits { 11237 u8 status[0x8]; 11238 u8 reserved_at_8[0x18]; 11239 11240 u8 syndrome[0x20]; 11241 11242 u8 reserved_at_40[0x10]; 11243 u8 uid[0x10]; 11244 11245 u8 reserved_at_60[0x20]; 11246 }; 11247 11248 struct mlx5_ifc_destroy_uctx_in_bits { 11249 u8 opcode[0x10]; 11250 u8 reserved_at_10[0x10]; 11251 11252 u8 reserved_at_20[0x10]; 11253 u8 op_mod[0x10]; 11254 11255 u8 reserved_at_40[0x10]; 11256 u8 uid[0x10]; 11257 11258 u8 reserved_at_60[0x20]; 11259 }; 11260 11261 struct mlx5_ifc_destroy_uctx_out_bits { 11262 u8 status[0x8]; 11263 u8 reserved_at_8[0x18]; 11264 11265 u8 syndrome[0x20]; 11266 11267 u8 reserved_at_40[0x40]; 11268 }; 11269 11270 struct mlx5_ifc_create_sw_icm_in_bits { 11271 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11272 struct mlx5_ifc_sw_icm_bits sw_icm; 11273 }; 11274 11275 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11276 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11277 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11278 }; 11279 11280 struct mlx5_ifc_mtrc_string_db_param_bits { 11281 u8 string_db_base_address[0x20]; 11282 11283 u8 reserved_at_20[0x8]; 11284 u8 string_db_size[0x18]; 11285 }; 11286 11287 struct mlx5_ifc_mtrc_cap_bits { 11288 u8 trace_owner[0x1]; 11289 u8 trace_to_memory[0x1]; 11290 u8 reserved_at_2[0x4]; 11291 u8 trc_ver[0x2]; 11292 u8 reserved_at_8[0x14]; 11293 u8 num_string_db[0x4]; 11294 11295 u8 first_string_trace[0x8]; 11296 u8 num_string_trace[0x8]; 11297 u8 reserved_at_30[0x28]; 11298 11299 u8 log_max_trace_buffer_size[0x8]; 11300 11301 u8 reserved_at_60[0x20]; 11302 11303 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11304 11305 u8 reserved_at_280[0x180]; 11306 }; 11307 11308 struct mlx5_ifc_mtrc_conf_bits { 11309 u8 reserved_at_0[0x1c]; 11310 u8 trace_mode[0x4]; 11311 u8 reserved_at_20[0x18]; 11312 u8 log_trace_buffer_size[0x8]; 11313 u8 trace_mkey[0x20]; 11314 u8 reserved_at_60[0x3a0]; 11315 }; 11316 11317 struct mlx5_ifc_mtrc_stdb_bits { 11318 u8 string_db_index[0x4]; 11319 u8 reserved_at_4[0x4]; 11320 u8 read_size[0x18]; 11321 u8 start_offset[0x20]; 11322 u8 string_db_data[]; 11323 }; 11324 11325 struct mlx5_ifc_mtrc_ctrl_bits { 11326 u8 trace_status[0x2]; 11327 u8 reserved_at_2[0x2]; 11328 u8 arm_event[0x1]; 11329 u8 reserved_at_5[0xb]; 11330 u8 modify_field_select[0x10]; 11331 u8 reserved_at_20[0x2b]; 11332 u8 current_timestamp52_32[0x15]; 11333 u8 current_timestamp31_0[0x20]; 11334 u8 reserved_at_80[0x180]; 11335 }; 11336 11337 struct mlx5_ifc_host_params_context_bits { 11338 u8 host_number[0x8]; 11339 u8 reserved_at_8[0x7]; 11340 u8 host_pf_disabled[0x1]; 11341 u8 host_num_of_vfs[0x10]; 11342 11343 u8 host_total_vfs[0x10]; 11344 u8 host_pci_bus[0x10]; 11345 11346 u8 reserved_at_40[0x10]; 11347 u8 host_pci_device[0x10]; 11348 11349 u8 reserved_at_60[0x10]; 11350 u8 host_pci_function[0x10]; 11351 11352 u8 reserved_at_80[0x180]; 11353 }; 11354 11355 struct mlx5_ifc_query_esw_functions_in_bits { 11356 u8 opcode[0x10]; 11357 u8 reserved_at_10[0x10]; 11358 11359 u8 reserved_at_20[0x10]; 11360 u8 op_mod[0x10]; 11361 11362 u8 reserved_at_40[0x40]; 11363 }; 11364 11365 struct mlx5_ifc_query_esw_functions_out_bits { 11366 u8 status[0x8]; 11367 u8 reserved_at_8[0x18]; 11368 11369 u8 syndrome[0x20]; 11370 11371 u8 reserved_at_40[0x40]; 11372 11373 struct mlx5_ifc_host_params_context_bits host_params_context; 11374 11375 u8 reserved_at_280[0x180]; 11376 u8 host_sf_enable[][0x40]; 11377 }; 11378 11379 struct mlx5_ifc_sf_partition_bits { 11380 u8 reserved_at_0[0x10]; 11381 u8 log_num_sf[0x8]; 11382 u8 log_sf_bar_size[0x8]; 11383 }; 11384 11385 struct mlx5_ifc_query_sf_partitions_out_bits { 11386 u8 status[0x8]; 11387 u8 reserved_at_8[0x18]; 11388 11389 u8 syndrome[0x20]; 11390 11391 u8 reserved_at_40[0x18]; 11392 u8 num_sf_partitions[0x8]; 11393 11394 u8 reserved_at_60[0x20]; 11395 11396 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11397 }; 11398 11399 struct mlx5_ifc_query_sf_partitions_in_bits { 11400 u8 opcode[0x10]; 11401 u8 reserved_at_10[0x10]; 11402 11403 u8 reserved_at_20[0x10]; 11404 u8 op_mod[0x10]; 11405 11406 u8 reserved_at_40[0x40]; 11407 }; 11408 11409 struct mlx5_ifc_dealloc_sf_out_bits { 11410 u8 status[0x8]; 11411 u8 reserved_at_8[0x18]; 11412 11413 u8 syndrome[0x20]; 11414 11415 u8 reserved_at_40[0x40]; 11416 }; 11417 11418 struct mlx5_ifc_dealloc_sf_in_bits { 11419 u8 opcode[0x10]; 11420 u8 reserved_at_10[0x10]; 11421 11422 u8 reserved_at_20[0x10]; 11423 u8 op_mod[0x10]; 11424 11425 u8 reserved_at_40[0x10]; 11426 u8 function_id[0x10]; 11427 11428 u8 reserved_at_60[0x20]; 11429 }; 11430 11431 struct mlx5_ifc_alloc_sf_out_bits { 11432 u8 status[0x8]; 11433 u8 reserved_at_8[0x18]; 11434 11435 u8 syndrome[0x20]; 11436 11437 u8 reserved_at_40[0x40]; 11438 }; 11439 11440 struct mlx5_ifc_alloc_sf_in_bits { 11441 u8 opcode[0x10]; 11442 u8 reserved_at_10[0x10]; 11443 11444 u8 reserved_at_20[0x10]; 11445 u8 op_mod[0x10]; 11446 11447 u8 reserved_at_40[0x10]; 11448 u8 function_id[0x10]; 11449 11450 u8 reserved_at_60[0x20]; 11451 }; 11452 11453 struct mlx5_ifc_affiliated_event_header_bits { 11454 u8 reserved_at_0[0x10]; 11455 u8 obj_type[0x10]; 11456 11457 u8 obj_id[0x20]; 11458 }; 11459 11460 enum { 11461 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11462 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11463 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11464 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11465 }; 11466 11467 enum { 11468 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11469 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11470 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11471 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11472 }; 11473 11474 enum { 11475 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11476 }; 11477 11478 struct mlx5_ifc_ipsec_obj_bits { 11479 u8 modify_field_select[0x40]; 11480 u8 full_offload[0x1]; 11481 u8 reserved_at_41[0x1]; 11482 u8 esn_en[0x1]; 11483 u8 esn_overlap[0x1]; 11484 u8 reserved_at_44[0x2]; 11485 u8 icv_length[0x2]; 11486 u8 reserved_at_48[0x4]; 11487 u8 aso_return_reg[0x4]; 11488 u8 reserved_at_50[0x10]; 11489 11490 u8 esn_msb[0x20]; 11491 11492 u8 reserved_at_80[0x8]; 11493 u8 dekn[0x18]; 11494 11495 u8 salt[0x20]; 11496 11497 u8 implicit_iv[0x40]; 11498 11499 u8 reserved_at_100[0x700]; 11500 }; 11501 11502 struct mlx5_ifc_create_ipsec_obj_in_bits { 11503 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11504 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11505 }; 11506 11507 enum { 11508 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11509 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11510 }; 11511 11512 struct mlx5_ifc_query_ipsec_obj_out_bits { 11513 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11514 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11515 }; 11516 11517 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11518 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11519 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11520 }; 11521 11522 struct mlx5_ifc_encryption_key_obj_bits { 11523 u8 modify_field_select[0x40]; 11524 11525 u8 reserved_at_40[0x14]; 11526 u8 key_size[0x4]; 11527 u8 reserved_at_58[0x4]; 11528 u8 key_type[0x4]; 11529 11530 u8 reserved_at_60[0x8]; 11531 u8 pd[0x18]; 11532 11533 u8 reserved_at_80[0x180]; 11534 u8 key[8][0x20]; 11535 11536 u8 reserved_at_300[0x500]; 11537 }; 11538 11539 struct mlx5_ifc_create_encryption_key_in_bits { 11540 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11541 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11542 }; 11543 11544 enum { 11545 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11546 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11547 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11548 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11549 }; 11550 11551 struct mlx5_ifc_flow_meter_parameters_bits { 11552 u8 valid[0x1]; 11553 u8 bucket_overflow[0x1]; 11554 u8 start_color[0x2]; 11555 u8 both_buckets_on_green[0x1]; 11556 u8 reserved_at_5[0x1]; 11557 u8 meter_mode[0x2]; 11558 u8 reserved_at_8[0x18]; 11559 11560 u8 reserved_at_20[0x20]; 11561 11562 u8 reserved_at_40[0x3]; 11563 u8 cbs_exponent[0x5]; 11564 u8 cbs_mantissa[0x8]; 11565 u8 reserved_at_50[0x3]; 11566 u8 cir_exponent[0x5]; 11567 u8 cir_mantissa[0x8]; 11568 11569 u8 reserved_at_60[0x20]; 11570 11571 u8 reserved_at_80[0x3]; 11572 u8 ebs_exponent[0x5]; 11573 u8 ebs_mantissa[0x8]; 11574 u8 reserved_at_90[0x3]; 11575 u8 eir_exponent[0x5]; 11576 u8 eir_mantissa[0x8]; 11577 11578 u8 reserved_at_a0[0x60]; 11579 }; 11580 11581 struct mlx5_ifc_flow_meter_aso_obj_bits { 11582 u8 modify_field_select[0x40]; 11583 11584 u8 reserved_at_40[0x40]; 11585 11586 u8 reserved_at_80[0x8]; 11587 u8 meter_aso_access_pd[0x18]; 11588 11589 u8 reserved_at_a0[0x160]; 11590 11591 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11592 }; 11593 11594 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11595 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11596 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11597 }; 11598 11599 struct mlx5_ifc_sampler_obj_bits { 11600 u8 modify_field_select[0x40]; 11601 11602 u8 table_type[0x8]; 11603 u8 level[0x8]; 11604 u8 reserved_at_50[0xf]; 11605 u8 ignore_flow_level[0x1]; 11606 11607 u8 sample_ratio[0x20]; 11608 11609 u8 reserved_at_80[0x8]; 11610 u8 sample_table_id[0x18]; 11611 11612 u8 reserved_at_a0[0x8]; 11613 u8 default_table_id[0x18]; 11614 11615 u8 sw_steering_icm_address_rx[0x40]; 11616 u8 sw_steering_icm_address_tx[0x40]; 11617 11618 u8 reserved_at_140[0xa0]; 11619 }; 11620 11621 struct mlx5_ifc_create_sampler_obj_in_bits { 11622 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11623 struct mlx5_ifc_sampler_obj_bits sampler_object; 11624 }; 11625 11626 struct mlx5_ifc_query_sampler_obj_out_bits { 11627 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11628 struct mlx5_ifc_sampler_obj_bits sampler_object; 11629 }; 11630 11631 enum { 11632 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11633 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11634 }; 11635 11636 enum { 11637 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11638 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11639 }; 11640 11641 struct mlx5_ifc_tls_static_params_bits { 11642 u8 const_2[0x2]; 11643 u8 tls_version[0x4]; 11644 u8 const_1[0x2]; 11645 u8 reserved_at_8[0x14]; 11646 u8 encryption_standard[0x4]; 11647 11648 u8 reserved_at_20[0x20]; 11649 11650 u8 initial_record_number[0x40]; 11651 11652 u8 resync_tcp_sn[0x20]; 11653 11654 u8 gcm_iv[0x20]; 11655 11656 u8 implicit_iv[0x40]; 11657 11658 u8 reserved_at_100[0x8]; 11659 u8 dek_index[0x18]; 11660 11661 u8 reserved_at_120[0xe0]; 11662 }; 11663 11664 struct mlx5_ifc_tls_progress_params_bits { 11665 u8 next_record_tcp_sn[0x20]; 11666 11667 u8 hw_resync_tcp_sn[0x20]; 11668 11669 u8 record_tracker_state[0x2]; 11670 u8 auth_state[0x2]; 11671 u8 reserved_at_44[0x4]; 11672 u8 hw_offset_record_number[0x18]; 11673 }; 11674 11675 enum { 11676 MLX5_MTT_PERM_READ = 1 << 0, 11677 MLX5_MTT_PERM_WRITE = 1 << 1, 11678 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11679 }; 11680 11681 enum { 11682 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11683 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11684 }; 11685 11686 struct mlx5_ifc_suspend_vhca_in_bits { 11687 u8 opcode[0x10]; 11688 u8 uid[0x10]; 11689 11690 u8 reserved_at_20[0x10]; 11691 u8 op_mod[0x10]; 11692 11693 u8 reserved_at_40[0x10]; 11694 u8 vhca_id[0x10]; 11695 11696 u8 reserved_at_60[0x20]; 11697 }; 11698 11699 struct mlx5_ifc_suspend_vhca_out_bits { 11700 u8 status[0x8]; 11701 u8 reserved_at_8[0x18]; 11702 11703 u8 syndrome[0x20]; 11704 11705 u8 reserved_at_40[0x40]; 11706 }; 11707 11708 enum { 11709 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11710 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11711 }; 11712 11713 struct mlx5_ifc_resume_vhca_in_bits { 11714 u8 opcode[0x10]; 11715 u8 uid[0x10]; 11716 11717 u8 reserved_at_20[0x10]; 11718 u8 op_mod[0x10]; 11719 11720 u8 reserved_at_40[0x10]; 11721 u8 vhca_id[0x10]; 11722 11723 u8 reserved_at_60[0x20]; 11724 }; 11725 11726 struct mlx5_ifc_resume_vhca_out_bits { 11727 u8 status[0x8]; 11728 u8 reserved_at_8[0x18]; 11729 11730 u8 syndrome[0x20]; 11731 11732 u8 reserved_at_40[0x40]; 11733 }; 11734 11735 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11736 u8 opcode[0x10]; 11737 u8 uid[0x10]; 11738 11739 u8 reserved_at_20[0x10]; 11740 u8 op_mod[0x10]; 11741 11742 u8 reserved_at_40[0x10]; 11743 u8 vhca_id[0x10]; 11744 11745 u8 reserved_at_60[0x20]; 11746 }; 11747 11748 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11749 u8 status[0x8]; 11750 u8 reserved_at_8[0x18]; 11751 11752 u8 syndrome[0x20]; 11753 11754 u8 reserved_at_40[0x40]; 11755 11756 u8 required_umem_size[0x20]; 11757 11758 u8 reserved_at_a0[0x160]; 11759 }; 11760 11761 struct mlx5_ifc_save_vhca_state_in_bits { 11762 u8 opcode[0x10]; 11763 u8 uid[0x10]; 11764 11765 u8 reserved_at_20[0x10]; 11766 u8 op_mod[0x10]; 11767 11768 u8 reserved_at_40[0x10]; 11769 u8 vhca_id[0x10]; 11770 11771 u8 reserved_at_60[0x20]; 11772 11773 u8 va[0x40]; 11774 11775 u8 mkey[0x20]; 11776 11777 u8 size[0x20]; 11778 }; 11779 11780 struct mlx5_ifc_save_vhca_state_out_bits { 11781 u8 status[0x8]; 11782 u8 reserved_at_8[0x18]; 11783 11784 u8 syndrome[0x20]; 11785 11786 u8 actual_image_size[0x20]; 11787 11788 u8 reserved_at_60[0x20]; 11789 }; 11790 11791 struct mlx5_ifc_load_vhca_state_in_bits { 11792 u8 opcode[0x10]; 11793 u8 uid[0x10]; 11794 11795 u8 reserved_at_20[0x10]; 11796 u8 op_mod[0x10]; 11797 11798 u8 reserved_at_40[0x10]; 11799 u8 vhca_id[0x10]; 11800 11801 u8 reserved_at_60[0x20]; 11802 11803 u8 va[0x40]; 11804 11805 u8 mkey[0x20]; 11806 11807 u8 size[0x20]; 11808 }; 11809 11810 struct mlx5_ifc_load_vhca_state_out_bits { 11811 u8 status[0x8]; 11812 u8 reserved_at_8[0x18]; 11813 11814 u8 syndrome[0x20]; 11815 11816 u8 reserved_at_40[0x40]; 11817 }; 11818 11819 #endif /* MLX5_IFC_H */ 11820