1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4), 80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5), 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_UCTX = 0x0004, 85 MLX5_OBJ_TYPE_UMEM = 0x0005, 86 }; 87 88 enum { 89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 91 MLX5_CMD_OP_INIT_HCA = 0x102, 92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 93 MLX5_CMD_OP_ENABLE_HCA = 0x104, 94 MLX5_CMD_OP_DISABLE_HCA = 0x105, 95 MLX5_CMD_OP_QUERY_PAGES = 0x107, 96 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 97 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 98 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 99 MLX5_CMD_OP_SET_ISSI = 0x10b, 100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 108 MLX5_CMD_OP_CREATE_EQ = 0x301, 109 MLX5_CMD_OP_DESTROY_EQ = 0x302, 110 MLX5_CMD_OP_QUERY_EQ = 0x303, 111 MLX5_CMD_OP_GEN_EQE = 0x304, 112 MLX5_CMD_OP_CREATE_CQ = 0x400, 113 MLX5_CMD_OP_DESTROY_CQ = 0x401, 114 MLX5_CMD_OP_QUERY_CQ = 0x402, 115 MLX5_CMD_OP_MODIFY_CQ = 0x403, 116 MLX5_CMD_OP_CREATE_QP = 0x500, 117 MLX5_CMD_OP_DESTROY_QP = 0x501, 118 MLX5_CMD_OP_RST2INIT_QP = 0x502, 119 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 120 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 121 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 123 MLX5_CMD_OP_2ERR_QP = 0x507, 124 MLX5_CMD_OP_2RST_QP = 0x50a, 125 MLX5_CMD_OP_QUERY_QP = 0x50b, 126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 128 MLX5_CMD_OP_CREATE_PSV = 0x600, 129 MLX5_CMD_OP_DESTROY_PSV = 0x601, 130 MLX5_CMD_OP_CREATE_SRQ = 0x700, 131 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 132 MLX5_CMD_OP_QUERY_SRQ = 0x702, 133 MLX5_CMD_OP_ARM_RQ = 0x703, 134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 138 MLX5_CMD_OP_CREATE_DCT = 0x710, 139 MLX5_CMD_OP_DESTROY_DCT = 0x711, 140 MLX5_CMD_OP_DRAIN_DCT = 0x712, 141 MLX5_CMD_OP_QUERY_DCT = 0x713, 142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 143 MLX5_CMD_OP_CREATE_XRQ = 0x717, 144 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 145 MLX5_CMD_OP_QUERY_XRQ = 0x719, 146 MLX5_CMD_OP_ARM_XRQ = 0x71a, 147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 172 MLX5_CMD_OP_ALLOC_PD = 0x800, 173 MLX5_CMD_OP_DEALLOC_PD = 0x801, 174 MLX5_CMD_OP_ALLOC_UAR = 0x802, 175 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 177 MLX5_CMD_OP_ACCESS_REG = 0x805, 178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 181 MLX5_CMD_OP_MAD_IFC = 0x50d, 182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 184 MLX5_CMD_OP_NOP = 0x80d, 185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_CREATE_TIS = 0x912, 225 MLX5_CMD_OP_MODIFY_TIS = 0x913, 226 MLX5_CMD_OP_DESTROY_TIS = 0x914, 227 MLX5_CMD_OP_QUERY_TIS = 0x915, 228 MLX5_CMD_OP_CREATE_RQT = 0x916, 229 MLX5_CMD_OP_MODIFY_RQT = 0x917, 230 MLX5_CMD_OP_DESTROY_RQT = 0x918, 231 MLX5_CMD_OP_QUERY_RQT = 0x919, 232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 246 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 247 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 260 MLX5_CMD_OP_MAX 261 }; 262 263 struct mlx5_ifc_flow_table_fields_supported_bits { 264 u8 outer_dmac[0x1]; 265 u8 outer_smac[0x1]; 266 u8 outer_ether_type[0x1]; 267 u8 outer_ip_version[0x1]; 268 u8 outer_first_prio[0x1]; 269 u8 outer_first_cfi[0x1]; 270 u8 outer_first_vid[0x1]; 271 u8 outer_ipv4_ttl[0x1]; 272 u8 outer_second_prio[0x1]; 273 u8 outer_second_cfi[0x1]; 274 u8 outer_second_vid[0x1]; 275 u8 reserved_at_b[0x1]; 276 u8 outer_sip[0x1]; 277 u8 outer_dip[0x1]; 278 u8 outer_frag[0x1]; 279 u8 outer_ip_protocol[0x1]; 280 u8 outer_ip_ecn[0x1]; 281 u8 outer_ip_dscp[0x1]; 282 u8 outer_udp_sport[0x1]; 283 u8 outer_udp_dport[0x1]; 284 u8 outer_tcp_sport[0x1]; 285 u8 outer_tcp_dport[0x1]; 286 u8 outer_tcp_flags[0x1]; 287 u8 outer_gre_protocol[0x1]; 288 u8 outer_gre_key[0x1]; 289 u8 outer_vxlan_vni[0x1]; 290 u8 reserved_at_1a[0x5]; 291 u8 source_eswitch_port[0x1]; 292 293 u8 inner_dmac[0x1]; 294 u8 inner_smac[0x1]; 295 u8 inner_ether_type[0x1]; 296 u8 inner_ip_version[0x1]; 297 u8 inner_first_prio[0x1]; 298 u8 inner_first_cfi[0x1]; 299 u8 inner_first_vid[0x1]; 300 u8 reserved_at_27[0x1]; 301 u8 inner_second_prio[0x1]; 302 u8 inner_second_cfi[0x1]; 303 u8 inner_second_vid[0x1]; 304 u8 reserved_at_2b[0x1]; 305 u8 inner_sip[0x1]; 306 u8 inner_dip[0x1]; 307 u8 inner_frag[0x1]; 308 u8 inner_ip_protocol[0x1]; 309 u8 inner_ip_ecn[0x1]; 310 u8 inner_ip_dscp[0x1]; 311 u8 inner_udp_sport[0x1]; 312 u8 inner_udp_dport[0x1]; 313 u8 inner_tcp_sport[0x1]; 314 u8 inner_tcp_dport[0x1]; 315 u8 inner_tcp_flags[0x1]; 316 u8 reserved_at_37[0x9]; 317 318 u8 reserved_at_40[0x5]; 319 u8 outer_first_mpls_over_udp[0x4]; 320 u8 outer_first_mpls_over_gre[0x4]; 321 u8 inner_first_mpls[0x4]; 322 u8 outer_first_mpls[0x4]; 323 u8 reserved_at_55[0x2]; 324 u8 outer_esp_spi[0x1]; 325 u8 reserved_at_58[0x2]; 326 u8 bth_dst_qp[0x1]; 327 328 u8 reserved_at_5b[0x25]; 329 }; 330 331 struct mlx5_ifc_flow_table_prop_layout_bits { 332 u8 ft_support[0x1]; 333 u8 reserved_at_1[0x1]; 334 u8 flow_counter[0x1]; 335 u8 flow_modify_en[0x1]; 336 u8 modify_root[0x1]; 337 u8 identified_miss_table_mode[0x1]; 338 u8 flow_table_modify[0x1]; 339 u8 reformat[0x1]; 340 u8 decap[0x1]; 341 u8 reserved_at_9[0x1]; 342 u8 pop_vlan[0x1]; 343 u8 push_vlan[0x1]; 344 u8 reserved_at_c[0x1]; 345 u8 pop_vlan_2[0x1]; 346 u8 push_vlan_2[0x1]; 347 u8 reformat_and_vlan_action[0x1]; 348 u8 reserved_at_10[0x2]; 349 u8 reformat_l3_tunnel_to_l2[0x1]; 350 u8 reformat_l2_to_l3_tunnel[0x1]; 351 u8 reformat_and_modify_action[0x1]; 352 u8 reserved_at_14[0xb]; 353 u8 reserved_at_20[0x2]; 354 u8 log_max_ft_size[0x6]; 355 u8 log_max_modify_header_context[0x8]; 356 u8 max_modify_header_actions[0x8]; 357 u8 max_ft_level[0x8]; 358 359 u8 reserved_at_40[0x20]; 360 361 u8 reserved_at_60[0x18]; 362 u8 log_max_ft_num[0x8]; 363 364 u8 reserved_at_80[0x18]; 365 u8 log_max_destination[0x8]; 366 367 u8 log_max_flow_counter[0x8]; 368 u8 reserved_at_a8[0x10]; 369 u8 log_max_flow[0x8]; 370 371 u8 reserved_at_c0[0x40]; 372 373 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 374 375 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 376 }; 377 378 struct mlx5_ifc_odp_per_transport_service_cap_bits { 379 u8 send[0x1]; 380 u8 receive[0x1]; 381 u8 write[0x1]; 382 u8 read[0x1]; 383 u8 atomic[0x1]; 384 u8 srq_receive[0x1]; 385 u8 reserved_at_6[0x1a]; 386 }; 387 388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 389 u8 smac_47_16[0x20]; 390 391 u8 smac_15_0[0x10]; 392 u8 ethertype[0x10]; 393 394 u8 dmac_47_16[0x20]; 395 396 u8 dmac_15_0[0x10]; 397 u8 first_prio[0x3]; 398 u8 first_cfi[0x1]; 399 u8 first_vid[0xc]; 400 401 u8 ip_protocol[0x8]; 402 u8 ip_dscp[0x6]; 403 u8 ip_ecn[0x2]; 404 u8 cvlan_tag[0x1]; 405 u8 svlan_tag[0x1]; 406 u8 frag[0x1]; 407 u8 ip_version[0x4]; 408 u8 tcp_flags[0x9]; 409 410 u8 tcp_sport[0x10]; 411 u8 tcp_dport[0x10]; 412 413 u8 reserved_at_c0[0x18]; 414 u8 ttl_hoplimit[0x8]; 415 416 u8 udp_sport[0x10]; 417 u8 udp_dport[0x10]; 418 419 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 420 421 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 422 }; 423 424 struct mlx5_ifc_fte_match_set_misc_bits { 425 u8 reserved_at_0[0x8]; 426 u8 source_sqn[0x18]; 427 428 u8 source_eswitch_owner_vhca_id[0x10]; 429 u8 source_port[0x10]; 430 431 u8 outer_second_prio[0x3]; 432 u8 outer_second_cfi[0x1]; 433 u8 outer_second_vid[0xc]; 434 u8 inner_second_prio[0x3]; 435 u8 inner_second_cfi[0x1]; 436 u8 inner_second_vid[0xc]; 437 438 u8 outer_second_cvlan_tag[0x1]; 439 u8 inner_second_cvlan_tag[0x1]; 440 u8 outer_second_svlan_tag[0x1]; 441 u8 inner_second_svlan_tag[0x1]; 442 u8 reserved_at_64[0xc]; 443 u8 gre_protocol[0x10]; 444 445 u8 gre_key_h[0x18]; 446 u8 gre_key_l[0x8]; 447 448 u8 vxlan_vni[0x18]; 449 u8 reserved_at_b8[0x8]; 450 451 u8 reserved_at_c0[0x20]; 452 453 u8 reserved_at_e0[0xc]; 454 u8 outer_ipv6_flow_label[0x14]; 455 456 u8 reserved_at_100[0xc]; 457 u8 inner_ipv6_flow_label[0x14]; 458 459 u8 reserved_at_120[0x28]; 460 u8 bth_dst_qp[0x18]; 461 u8 reserved_at_160[0x20]; 462 u8 outer_esp_spi[0x20]; 463 u8 reserved_at_1a0[0x60]; 464 }; 465 466 struct mlx5_ifc_fte_match_mpls_bits { 467 u8 mpls_label[0x14]; 468 u8 mpls_exp[0x3]; 469 u8 mpls_s_bos[0x1]; 470 u8 mpls_ttl[0x8]; 471 }; 472 473 struct mlx5_ifc_fte_match_set_misc2_bits { 474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 475 476 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 477 478 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 479 480 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 481 482 u8 reserved_at_80[0x100]; 483 484 u8 metadata_reg_a[0x20]; 485 486 u8 reserved_at_1a0[0x60]; 487 }; 488 489 struct mlx5_ifc_cmd_pas_bits { 490 u8 pa_h[0x20]; 491 492 u8 pa_l[0x14]; 493 u8 reserved_at_34[0xc]; 494 }; 495 496 struct mlx5_ifc_uint64_bits { 497 u8 hi[0x20]; 498 499 u8 lo[0x20]; 500 }; 501 502 enum { 503 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 504 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 505 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 506 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 507 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 508 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 509 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 510 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 511 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 512 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 513 }; 514 515 struct mlx5_ifc_ads_bits { 516 u8 fl[0x1]; 517 u8 free_ar[0x1]; 518 u8 reserved_at_2[0xe]; 519 u8 pkey_index[0x10]; 520 521 u8 reserved_at_20[0x8]; 522 u8 grh[0x1]; 523 u8 mlid[0x7]; 524 u8 rlid[0x10]; 525 526 u8 ack_timeout[0x5]; 527 u8 reserved_at_45[0x3]; 528 u8 src_addr_index[0x8]; 529 u8 reserved_at_50[0x4]; 530 u8 stat_rate[0x4]; 531 u8 hop_limit[0x8]; 532 533 u8 reserved_at_60[0x4]; 534 u8 tclass[0x8]; 535 u8 flow_label[0x14]; 536 537 u8 rgid_rip[16][0x8]; 538 539 u8 reserved_at_100[0x4]; 540 u8 f_dscp[0x1]; 541 u8 f_ecn[0x1]; 542 u8 reserved_at_106[0x1]; 543 u8 f_eth_prio[0x1]; 544 u8 ecn[0x2]; 545 u8 dscp[0x6]; 546 u8 udp_sport[0x10]; 547 548 u8 dei_cfi[0x1]; 549 u8 eth_prio[0x3]; 550 u8 sl[0x4]; 551 u8 vhca_port_num[0x8]; 552 u8 rmac_47_32[0x10]; 553 554 u8 rmac_31_0[0x20]; 555 }; 556 557 struct mlx5_ifc_flow_table_nic_cap_bits { 558 u8 nic_rx_multi_path_tirs[0x1]; 559 u8 nic_rx_multi_path_tirs_fts[0x1]; 560 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 561 u8 reserved_at_3[0x1d]; 562 u8 encap_general_header[0x1]; 563 u8 reserved_at_21[0xa]; 564 u8 log_max_packet_reformat_context[0x5]; 565 u8 reserved_at_30[0x6]; 566 u8 max_encap_header_size[0xa]; 567 u8 reserved_at_40[0x1c0]; 568 569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 570 571 u8 reserved_at_400[0x200]; 572 573 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 574 575 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 576 577 u8 reserved_at_a00[0x200]; 578 579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 580 581 u8 reserved_at_e00[0x7200]; 582 }; 583 584 struct mlx5_ifc_flow_table_eswitch_cap_bits { 585 u8 reserved_at_0[0x1c]; 586 u8 fdb_multi_path_to_table[0x1]; 587 u8 reserved_at_1d[0x1]; 588 u8 multi_fdb_encap[0x1]; 589 u8 reserved_at_1e[0x1e1]; 590 591 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 592 593 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 594 595 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 596 597 u8 reserved_at_800[0x7800]; 598 }; 599 600 struct mlx5_ifc_e_switch_cap_bits { 601 u8 vport_svlan_strip[0x1]; 602 u8 vport_cvlan_strip[0x1]; 603 u8 vport_svlan_insert[0x1]; 604 u8 vport_cvlan_insert_if_not_exist[0x1]; 605 u8 vport_cvlan_insert_overwrite[0x1]; 606 u8 reserved_at_5[0x18]; 607 u8 merged_eswitch[0x1]; 608 u8 nic_vport_node_guid_modify[0x1]; 609 u8 nic_vport_port_guid_modify[0x1]; 610 611 u8 vxlan_encap_decap[0x1]; 612 u8 nvgre_encap_decap[0x1]; 613 u8 reserved_at_22[0x9]; 614 u8 log_max_packet_reformat_context[0x5]; 615 u8 reserved_2b[0x6]; 616 u8 max_encap_header_size[0xa]; 617 618 u8 reserved_40[0x7c0]; 619 620 }; 621 622 struct mlx5_ifc_qos_cap_bits { 623 u8 packet_pacing[0x1]; 624 u8 esw_scheduling[0x1]; 625 u8 esw_bw_share[0x1]; 626 u8 esw_rate_limit[0x1]; 627 u8 reserved_at_4[0x1]; 628 u8 packet_pacing_burst_bound[0x1]; 629 u8 packet_pacing_typical_size[0x1]; 630 u8 reserved_at_7[0x19]; 631 632 u8 reserved_at_20[0x20]; 633 634 u8 packet_pacing_max_rate[0x20]; 635 636 u8 packet_pacing_min_rate[0x20]; 637 638 u8 reserved_at_80[0x10]; 639 u8 packet_pacing_rate_table_size[0x10]; 640 641 u8 esw_element_type[0x10]; 642 u8 esw_tsar_type[0x10]; 643 644 u8 reserved_at_c0[0x10]; 645 u8 max_qos_para_vport[0x10]; 646 647 u8 max_tsar_bw_share[0x20]; 648 649 u8 reserved_at_100[0x700]; 650 }; 651 652 struct mlx5_ifc_debug_cap_bits { 653 u8 reserved_at_0[0x20]; 654 655 u8 reserved_at_20[0x2]; 656 u8 stall_detect[0x1]; 657 u8 reserved_at_23[0x1d]; 658 659 u8 reserved_at_40[0x7c0]; 660 }; 661 662 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 663 u8 csum_cap[0x1]; 664 u8 vlan_cap[0x1]; 665 u8 lro_cap[0x1]; 666 u8 lro_psh_flag[0x1]; 667 u8 lro_time_stamp[0x1]; 668 u8 reserved_at_5[0x2]; 669 u8 wqe_vlan_insert[0x1]; 670 u8 self_lb_en_modifiable[0x1]; 671 u8 reserved_at_9[0x2]; 672 u8 max_lso_cap[0x5]; 673 u8 multi_pkt_send_wqe[0x2]; 674 u8 wqe_inline_mode[0x2]; 675 u8 rss_ind_tbl_cap[0x4]; 676 u8 reg_umr_sq[0x1]; 677 u8 scatter_fcs[0x1]; 678 u8 enhanced_multi_pkt_send_wqe[0x1]; 679 u8 tunnel_lso_const_out_ip_id[0x1]; 680 u8 reserved_at_1c[0x2]; 681 u8 tunnel_stateless_gre[0x1]; 682 u8 tunnel_stateless_vxlan[0x1]; 683 684 u8 swp[0x1]; 685 u8 swp_csum[0x1]; 686 u8 swp_lso[0x1]; 687 u8 reserved_at_23[0xd]; 688 u8 max_vxlan_udp_ports[0x8]; 689 u8 reserved_at_38[0x6]; 690 u8 max_geneve_opt_len[0x1]; 691 u8 tunnel_stateless_geneve_rx[0x1]; 692 693 u8 reserved_at_40[0x10]; 694 u8 lro_min_mss_size[0x10]; 695 696 u8 reserved_at_60[0x120]; 697 698 u8 lro_timer_supported_periods[4][0x20]; 699 700 u8 reserved_at_200[0x600]; 701 }; 702 703 struct mlx5_ifc_roce_cap_bits { 704 u8 roce_apm[0x1]; 705 u8 reserved_at_1[0x1f]; 706 707 u8 reserved_at_20[0x60]; 708 709 u8 reserved_at_80[0xc]; 710 u8 l3_type[0x4]; 711 u8 reserved_at_90[0x8]; 712 u8 roce_version[0x8]; 713 714 u8 reserved_at_a0[0x10]; 715 u8 r_roce_dest_udp_port[0x10]; 716 717 u8 r_roce_max_src_udp_port[0x10]; 718 u8 r_roce_min_src_udp_port[0x10]; 719 720 u8 reserved_at_e0[0x10]; 721 u8 roce_address_table_size[0x10]; 722 723 u8 reserved_at_100[0x700]; 724 }; 725 726 struct mlx5_ifc_device_mem_cap_bits { 727 u8 memic[0x1]; 728 u8 reserved_at_1[0x1f]; 729 730 u8 reserved_at_20[0xb]; 731 u8 log_min_memic_alloc_size[0x5]; 732 u8 reserved_at_30[0x8]; 733 u8 log_max_memic_addr_alignment[0x8]; 734 735 u8 memic_bar_start_addr[0x40]; 736 737 u8 memic_bar_size[0x20]; 738 739 u8 max_memic_size[0x20]; 740 741 u8 reserved_at_c0[0x740]; 742 }; 743 744 enum { 745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 749 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 750 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 751 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 754 }; 755 756 enum { 757 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 758 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 759 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 760 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 761 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 762 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 763 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 764 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 765 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 766 }; 767 768 struct mlx5_ifc_atomic_caps_bits { 769 u8 reserved_at_0[0x40]; 770 771 u8 atomic_req_8B_endianness_mode[0x2]; 772 u8 reserved_at_42[0x4]; 773 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 774 775 u8 reserved_at_47[0x19]; 776 777 u8 reserved_at_60[0x20]; 778 779 u8 reserved_at_80[0x10]; 780 u8 atomic_operations[0x10]; 781 782 u8 reserved_at_a0[0x10]; 783 u8 atomic_size_qp[0x10]; 784 785 u8 reserved_at_c0[0x10]; 786 u8 atomic_size_dc[0x10]; 787 788 u8 reserved_at_e0[0x720]; 789 }; 790 791 struct mlx5_ifc_odp_cap_bits { 792 u8 reserved_at_0[0x40]; 793 794 u8 sig[0x1]; 795 u8 reserved_at_41[0x1f]; 796 797 u8 reserved_at_60[0x20]; 798 799 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 800 801 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 802 803 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 804 805 u8 reserved_at_e0[0x720]; 806 }; 807 808 struct mlx5_ifc_calc_op { 809 u8 reserved_at_0[0x10]; 810 u8 reserved_at_10[0x9]; 811 u8 op_swap_endianness[0x1]; 812 u8 op_min[0x1]; 813 u8 op_xor[0x1]; 814 u8 op_or[0x1]; 815 u8 op_and[0x1]; 816 u8 op_max[0x1]; 817 u8 op_add[0x1]; 818 }; 819 820 struct mlx5_ifc_vector_calc_cap_bits { 821 u8 calc_matrix[0x1]; 822 u8 reserved_at_1[0x1f]; 823 u8 reserved_at_20[0x8]; 824 u8 max_vec_count[0x8]; 825 u8 reserved_at_30[0xd]; 826 u8 max_chunk_size[0x3]; 827 struct mlx5_ifc_calc_op calc0; 828 struct mlx5_ifc_calc_op calc1; 829 struct mlx5_ifc_calc_op calc2; 830 struct mlx5_ifc_calc_op calc3; 831 832 u8 reserved_at_e0[0x720]; 833 }; 834 835 enum { 836 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 837 MLX5_WQ_TYPE_CYCLIC = 0x1, 838 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 839 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 840 }; 841 842 enum { 843 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 844 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 845 }; 846 847 enum { 848 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 849 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 850 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 851 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 852 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 853 }; 854 855 enum { 856 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 857 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 858 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 859 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 860 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 861 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 862 }; 863 864 enum { 865 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 866 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 867 }; 868 869 enum { 870 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 871 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 872 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 873 }; 874 875 enum { 876 MLX5_CAP_PORT_TYPE_IB = 0x0, 877 MLX5_CAP_PORT_TYPE_ETH = 0x1, 878 }; 879 880 enum { 881 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 882 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 883 MLX5_CAP_UMR_FENCE_NONE = 0x2, 884 }; 885 886 struct mlx5_ifc_cmd_hca_cap_bits { 887 u8 reserved_at_0[0x30]; 888 u8 vhca_id[0x10]; 889 890 u8 reserved_at_40[0x40]; 891 892 u8 log_max_srq_sz[0x8]; 893 u8 log_max_qp_sz[0x8]; 894 u8 reserved_at_90[0xb]; 895 u8 log_max_qp[0x5]; 896 897 u8 reserved_at_a0[0xb]; 898 u8 log_max_srq[0x5]; 899 u8 reserved_at_b0[0x10]; 900 901 u8 reserved_at_c0[0x8]; 902 u8 log_max_cq_sz[0x8]; 903 u8 reserved_at_d0[0xb]; 904 u8 log_max_cq[0x5]; 905 906 u8 log_max_eq_sz[0x8]; 907 u8 reserved_at_e8[0x2]; 908 u8 log_max_mkey[0x6]; 909 u8 reserved_at_f0[0x8]; 910 u8 dump_fill_mkey[0x1]; 911 u8 reserved_at_f9[0x2]; 912 u8 fast_teardown[0x1]; 913 u8 log_max_eq[0x4]; 914 915 u8 max_indirection[0x8]; 916 u8 fixed_buffer_size[0x1]; 917 u8 log_max_mrw_sz[0x7]; 918 u8 force_teardown[0x1]; 919 u8 reserved_at_111[0x1]; 920 u8 log_max_bsf_list_size[0x6]; 921 u8 umr_extended_translation_offset[0x1]; 922 u8 null_mkey[0x1]; 923 u8 log_max_klm_list_size[0x6]; 924 925 u8 reserved_at_120[0xa]; 926 u8 log_max_ra_req_dc[0x6]; 927 u8 reserved_at_130[0xa]; 928 u8 log_max_ra_res_dc[0x6]; 929 930 u8 reserved_at_140[0xa]; 931 u8 log_max_ra_req_qp[0x6]; 932 u8 reserved_at_150[0xa]; 933 u8 log_max_ra_res_qp[0x6]; 934 935 u8 end_pad[0x1]; 936 u8 cc_query_allowed[0x1]; 937 u8 cc_modify_allowed[0x1]; 938 u8 start_pad[0x1]; 939 u8 cache_line_128byte[0x1]; 940 u8 reserved_at_165[0xa]; 941 u8 qcam_reg[0x1]; 942 u8 gid_table_size[0x10]; 943 944 u8 out_of_seq_cnt[0x1]; 945 u8 vport_counters[0x1]; 946 u8 retransmission_q_counters[0x1]; 947 u8 debug[0x1]; 948 u8 modify_rq_counter_set_id[0x1]; 949 u8 rq_delay_drop[0x1]; 950 u8 max_qp_cnt[0xa]; 951 u8 pkey_table_size[0x10]; 952 953 u8 vport_group_manager[0x1]; 954 u8 vhca_group_manager[0x1]; 955 u8 ib_virt[0x1]; 956 u8 eth_virt[0x1]; 957 u8 vnic_env_queue_counters[0x1]; 958 u8 ets[0x1]; 959 u8 nic_flow_table[0x1]; 960 u8 eswitch_manager[0x1]; 961 u8 device_memory[0x1]; 962 u8 mcam_reg[0x1]; 963 u8 pcam_reg[0x1]; 964 u8 local_ca_ack_delay[0x5]; 965 u8 port_module_event[0x1]; 966 u8 enhanced_error_q_counters[0x1]; 967 u8 ports_check[0x1]; 968 u8 reserved_at_1b3[0x1]; 969 u8 disable_link_up[0x1]; 970 u8 beacon_led[0x1]; 971 u8 port_type[0x2]; 972 u8 num_ports[0x8]; 973 974 u8 reserved_at_1c0[0x1]; 975 u8 pps[0x1]; 976 u8 pps_modify[0x1]; 977 u8 log_max_msg[0x5]; 978 u8 reserved_at_1c8[0x4]; 979 u8 max_tc[0x4]; 980 u8 temp_warn_event[0x1]; 981 u8 dcbx[0x1]; 982 u8 general_notification_event[0x1]; 983 u8 reserved_at_1d3[0x2]; 984 u8 fpga[0x1]; 985 u8 rol_s[0x1]; 986 u8 rol_g[0x1]; 987 u8 reserved_at_1d8[0x1]; 988 u8 wol_s[0x1]; 989 u8 wol_g[0x1]; 990 u8 wol_a[0x1]; 991 u8 wol_b[0x1]; 992 u8 wol_m[0x1]; 993 u8 wol_u[0x1]; 994 u8 wol_p[0x1]; 995 996 u8 stat_rate_support[0x10]; 997 u8 reserved_at_1f0[0xc]; 998 u8 cqe_version[0x4]; 999 1000 u8 compact_address_vector[0x1]; 1001 u8 striding_rq[0x1]; 1002 u8 reserved_at_202[0x1]; 1003 u8 ipoib_enhanced_offloads[0x1]; 1004 u8 ipoib_basic_offloads[0x1]; 1005 u8 reserved_at_205[0x1]; 1006 u8 repeated_block_disabled[0x1]; 1007 u8 umr_modify_entity_size_disabled[0x1]; 1008 u8 umr_modify_atomic_disabled[0x1]; 1009 u8 umr_indirect_mkey_disabled[0x1]; 1010 u8 umr_fence[0x2]; 1011 u8 dc_req_scat_data_cqe[0x1]; 1012 u8 reserved_at_20d[0x2]; 1013 u8 drain_sigerr[0x1]; 1014 u8 cmdif_checksum[0x2]; 1015 u8 sigerr_cqe[0x1]; 1016 u8 reserved_at_213[0x1]; 1017 u8 wq_signature[0x1]; 1018 u8 sctr_data_cqe[0x1]; 1019 u8 reserved_at_216[0x1]; 1020 u8 sho[0x1]; 1021 u8 tph[0x1]; 1022 u8 rf[0x1]; 1023 u8 dct[0x1]; 1024 u8 qos[0x1]; 1025 u8 eth_net_offloads[0x1]; 1026 u8 roce[0x1]; 1027 u8 atomic[0x1]; 1028 u8 reserved_at_21f[0x1]; 1029 1030 u8 cq_oi[0x1]; 1031 u8 cq_resize[0x1]; 1032 u8 cq_moderation[0x1]; 1033 u8 reserved_at_223[0x3]; 1034 u8 cq_eq_remap[0x1]; 1035 u8 pg[0x1]; 1036 u8 block_lb_mc[0x1]; 1037 u8 reserved_at_229[0x1]; 1038 u8 scqe_break_moderation[0x1]; 1039 u8 cq_period_start_from_cqe[0x1]; 1040 u8 cd[0x1]; 1041 u8 reserved_at_22d[0x1]; 1042 u8 apm[0x1]; 1043 u8 vector_calc[0x1]; 1044 u8 umr_ptr_rlky[0x1]; 1045 u8 imaicl[0x1]; 1046 u8 reserved_at_232[0x4]; 1047 u8 qkv[0x1]; 1048 u8 pkv[0x1]; 1049 u8 set_deth_sqpn[0x1]; 1050 u8 reserved_at_239[0x3]; 1051 u8 xrc[0x1]; 1052 u8 ud[0x1]; 1053 u8 uc[0x1]; 1054 u8 rc[0x1]; 1055 1056 u8 uar_4k[0x1]; 1057 u8 reserved_at_241[0x9]; 1058 u8 uar_sz[0x6]; 1059 u8 reserved_at_250[0x8]; 1060 u8 log_pg_sz[0x8]; 1061 1062 u8 bf[0x1]; 1063 u8 driver_version[0x1]; 1064 u8 pad_tx_eth_packet[0x1]; 1065 u8 reserved_at_263[0x8]; 1066 u8 log_bf_reg_size[0x5]; 1067 1068 u8 reserved_at_270[0xb]; 1069 u8 lag_master[0x1]; 1070 u8 num_lag_ports[0x4]; 1071 1072 u8 reserved_at_280[0x10]; 1073 u8 max_wqe_sz_sq[0x10]; 1074 1075 u8 reserved_at_2a0[0x10]; 1076 u8 max_wqe_sz_rq[0x10]; 1077 1078 u8 max_flow_counter_31_16[0x10]; 1079 u8 max_wqe_sz_sq_dc[0x10]; 1080 1081 u8 reserved_at_2e0[0x7]; 1082 u8 max_qp_mcg[0x19]; 1083 1084 u8 reserved_at_300[0x18]; 1085 u8 log_max_mcg[0x8]; 1086 1087 u8 reserved_at_320[0x3]; 1088 u8 log_max_transport_domain[0x5]; 1089 u8 reserved_at_328[0x3]; 1090 u8 log_max_pd[0x5]; 1091 u8 reserved_at_330[0xb]; 1092 u8 log_max_xrcd[0x5]; 1093 1094 u8 nic_receive_steering_discard[0x1]; 1095 u8 receive_discard_vport_down[0x1]; 1096 u8 transmit_discard_vport_down[0x1]; 1097 u8 reserved_at_343[0x5]; 1098 u8 log_max_flow_counter_bulk[0x8]; 1099 u8 max_flow_counter_15_0[0x10]; 1100 1101 1102 u8 reserved_at_360[0x3]; 1103 u8 log_max_rq[0x5]; 1104 u8 reserved_at_368[0x3]; 1105 u8 log_max_sq[0x5]; 1106 u8 reserved_at_370[0x3]; 1107 u8 log_max_tir[0x5]; 1108 u8 reserved_at_378[0x3]; 1109 u8 log_max_tis[0x5]; 1110 1111 u8 basic_cyclic_rcv_wqe[0x1]; 1112 u8 reserved_at_381[0x2]; 1113 u8 log_max_rmp[0x5]; 1114 u8 reserved_at_388[0x3]; 1115 u8 log_max_rqt[0x5]; 1116 u8 reserved_at_390[0x3]; 1117 u8 log_max_rqt_size[0x5]; 1118 u8 reserved_at_398[0x3]; 1119 u8 log_max_tis_per_sq[0x5]; 1120 1121 u8 ext_stride_num_range[0x1]; 1122 u8 reserved_at_3a1[0x2]; 1123 u8 log_max_stride_sz_rq[0x5]; 1124 u8 reserved_at_3a8[0x3]; 1125 u8 log_min_stride_sz_rq[0x5]; 1126 u8 reserved_at_3b0[0x3]; 1127 u8 log_max_stride_sz_sq[0x5]; 1128 u8 reserved_at_3b8[0x3]; 1129 u8 log_min_stride_sz_sq[0x5]; 1130 1131 u8 hairpin[0x1]; 1132 u8 reserved_at_3c1[0x2]; 1133 u8 log_max_hairpin_queues[0x5]; 1134 u8 reserved_at_3c8[0x3]; 1135 u8 log_max_hairpin_wq_data_sz[0x5]; 1136 u8 reserved_at_3d0[0x3]; 1137 u8 log_max_hairpin_num_packets[0x5]; 1138 u8 reserved_at_3d8[0x3]; 1139 u8 log_max_wq_sz[0x5]; 1140 1141 u8 nic_vport_change_event[0x1]; 1142 u8 disable_local_lb_uc[0x1]; 1143 u8 disable_local_lb_mc[0x1]; 1144 u8 log_min_hairpin_wq_data_sz[0x5]; 1145 u8 reserved_at_3e8[0x3]; 1146 u8 log_max_vlan_list[0x5]; 1147 u8 reserved_at_3f0[0x3]; 1148 u8 log_max_current_mc_list[0x5]; 1149 u8 reserved_at_3f8[0x3]; 1150 u8 log_max_current_uc_list[0x5]; 1151 1152 u8 general_obj_types[0x40]; 1153 1154 u8 reserved_at_440[0x20]; 1155 1156 u8 reserved_at_460[0x10]; 1157 u8 max_num_eqs[0x10]; 1158 1159 u8 reserved_at_480[0x3]; 1160 u8 log_max_l2_table[0x5]; 1161 u8 reserved_at_488[0x8]; 1162 u8 log_uar_page_sz[0x10]; 1163 1164 u8 reserved_at_4a0[0x20]; 1165 u8 device_frequency_mhz[0x20]; 1166 u8 device_frequency_khz[0x20]; 1167 1168 u8 reserved_at_500[0x20]; 1169 u8 num_of_uars_per_page[0x20]; 1170 1171 u8 flex_parser_protocols[0x20]; 1172 u8 reserved_at_560[0x20]; 1173 1174 u8 reserved_at_580[0x3c]; 1175 u8 mini_cqe_resp_stride_index[0x1]; 1176 u8 cqe_128_always[0x1]; 1177 u8 cqe_compression_128[0x1]; 1178 u8 cqe_compression[0x1]; 1179 1180 u8 cqe_compression_timeout[0x10]; 1181 u8 cqe_compression_max_num[0x10]; 1182 1183 u8 reserved_at_5e0[0x10]; 1184 u8 tag_matching[0x1]; 1185 u8 rndv_offload_rc[0x1]; 1186 u8 rndv_offload_dc[0x1]; 1187 u8 log_tag_matching_list_sz[0x5]; 1188 u8 reserved_at_5f8[0x3]; 1189 u8 log_max_xrq[0x5]; 1190 1191 u8 affiliate_nic_vport_criteria[0x8]; 1192 u8 native_port_num[0x8]; 1193 u8 num_vhca_ports[0x8]; 1194 u8 reserved_at_618[0x6]; 1195 u8 sw_owner_id[0x1]; 1196 u8 reserved_at_61f[0x1e1]; 1197 }; 1198 1199 enum mlx5_flow_destination_type { 1200 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1201 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1202 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1203 1204 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1205 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1206 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1207 }; 1208 1209 struct mlx5_ifc_dest_format_struct_bits { 1210 u8 destination_type[0x8]; 1211 u8 destination_id[0x18]; 1212 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1213 u8 reserved_at_21[0xf]; 1214 u8 destination_eswitch_owner_vhca_id[0x10]; 1215 }; 1216 1217 struct mlx5_ifc_flow_counter_list_bits { 1218 u8 flow_counter_id[0x20]; 1219 1220 u8 reserved_at_20[0x20]; 1221 }; 1222 1223 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1224 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1225 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1226 u8 reserved_at_0[0x40]; 1227 }; 1228 1229 struct mlx5_ifc_fte_match_param_bits { 1230 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1231 1232 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1233 1234 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1235 1236 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1237 1238 u8 reserved_at_800[0x800]; 1239 }; 1240 1241 enum { 1242 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1243 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1244 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1245 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1246 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1247 }; 1248 1249 struct mlx5_ifc_rx_hash_field_select_bits { 1250 u8 l3_prot_type[0x1]; 1251 u8 l4_prot_type[0x1]; 1252 u8 selected_fields[0x1e]; 1253 }; 1254 1255 enum { 1256 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1257 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1258 }; 1259 1260 enum { 1261 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1262 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1263 }; 1264 1265 struct mlx5_ifc_wq_bits { 1266 u8 wq_type[0x4]; 1267 u8 wq_signature[0x1]; 1268 u8 end_padding_mode[0x2]; 1269 u8 cd_slave[0x1]; 1270 u8 reserved_at_8[0x18]; 1271 1272 u8 hds_skip_first_sge[0x1]; 1273 u8 log2_hds_buf_size[0x3]; 1274 u8 reserved_at_24[0x7]; 1275 u8 page_offset[0x5]; 1276 u8 lwm[0x10]; 1277 1278 u8 reserved_at_40[0x8]; 1279 u8 pd[0x18]; 1280 1281 u8 reserved_at_60[0x8]; 1282 u8 uar_page[0x18]; 1283 1284 u8 dbr_addr[0x40]; 1285 1286 u8 hw_counter[0x20]; 1287 1288 u8 sw_counter[0x20]; 1289 1290 u8 reserved_at_100[0xc]; 1291 u8 log_wq_stride[0x4]; 1292 u8 reserved_at_110[0x3]; 1293 u8 log_wq_pg_sz[0x5]; 1294 u8 reserved_at_118[0x3]; 1295 u8 log_wq_sz[0x5]; 1296 1297 u8 dbr_umem_valid[0x1]; 1298 u8 wq_umem_valid[0x1]; 1299 u8 reserved_at_122[0x1]; 1300 u8 log_hairpin_num_packets[0x5]; 1301 u8 reserved_at_128[0x3]; 1302 u8 log_hairpin_data_sz[0x5]; 1303 1304 u8 reserved_at_130[0x4]; 1305 u8 log_wqe_num_of_strides[0x4]; 1306 u8 two_byte_shift_en[0x1]; 1307 u8 reserved_at_139[0x4]; 1308 u8 log_wqe_stride_size[0x3]; 1309 1310 u8 reserved_at_140[0x4c0]; 1311 1312 struct mlx5_ifc_cmd_pas_bits pas[0]; 1313 }; 1314 1315 struct mlx5_ifc_rq_num_bits { 1316 u8 reserved_at_0[0x8]; 1317 u8 rq_num[0x18]; 1318 }; 1319 1320 struct mlx5_ifc_mac_address_layout_bits { 1321 u8 reserved_at_0[0x10]; 1322 u8 mac_addr_47_32[0x10]; 1323 1324 u8 mac_addr_31_0[0x20]; 1325 }; 1326 1327 struct mlx5_ifc_vlan_layout_bits { 1328 u8 reserved_at_0[0x14]; 1329 u8 vlan[0x0c]; 1330 1331 u8 reserved_at_20[0x20]; 1332 }; 1333 1334 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1335 u8 reserved_at_0[0xa0]; 1336 1337 u8 min_time_between_cnps[0x20]; 1338 1339 u8 reserved_at_c0[0x12]; 1340 u8 cnp_dscp[0x6]; 1341 u8 reserved_at_d8[0x4]; 1342 u8 cnp_prio_mode[0x1]; 1343 u8 cnp_802p_prio[0x3]; 1344 1345 u8 reserved_at_e0[0x720]; 1346 }; 1347 1348 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1349 u8 reserved_at_0[0x60]; 1350 1351 u8 reserved_at_60[0x4]; 1352 u8 clamp_tgt_rate[0x1]; 1353 u8 reserved_at_65[0x3]; 1354 u8 clamp_tgt_rate_after_time_inc[0x1]; 1355 u8 reserved_at_69[0x17]; 1356 1357 u8 reserved_at_80[0x20]; 1358 1359 u8 rpg_time_reset[0x20]; 1360 1361 u8 rpg_byte_reset[0x20]; 1362 1363 u8 rpg_threshold[0x20]; 1364 1365 u8 rpg_max_rate[0x20]; 1366 1367 u8 rpg_ai_rate[0x20]; 1368 1369 u8 rpg_hai_rate[0x20]; 1370 1371 u8 rpg_gd[0x20]; 1372 1373 u8 rpg_min_dec_fac[0x20]; 1374 1375 u8 rpg_min_rate[0x20]; 1376 1377 u8 reserved_at_1c0[0xe0]; 1378 1379 u8 rate_to_set_on_first_cnp[0x20]; 1380 1381 u8 dce_tcp_g[0x20]; 1382 1383 u8 dce_tcp_rtt[0x20]; 1384 1385 u8 rate_reduce_monitor_period[0x20]; 1386 1387 u8 reserved_at_320[0x20]; 1388 1389 u8 initial_alpha_value[0x20]; 1390 1391 u8 reserved_at_360[0x4a0]; 1392 }; 1393 1394 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1395 u8 reserved_at_0[0x80]; 1396 1397 u8 rppp_max_rps[0x20]; 1398 1399 u8 rpg_time_reset[0x20]; 1400 1401 u8 rpg_byte_reset[0x20]; 1402 1403 u8 rpg_threshold[0x20]; 1404 1405 u8 rpg_max_rate[0x20]; 1406 1407 u8 rpg_ai_rate[0x20]; 1408 1409 u8 rpg_hai_rate[0x20]; 1410 1411 u8 rpg_gd[0x20]; 1412 1413 u8 rpg_min_dec_fac[0x20]; 1414 1415 u8 rpg_min_rate[0x20]; 1416 1417 u8 reserved_at_1c0[0x640]; 1418 }; 1419 1420 enum { 1421 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1422 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1423 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1424 }; 1425 1426 struct mlx5_ifc_resize_field_select_bits { 1427 u8 resize_field_select[0x20]; 1428 }; 1429 1430 enum { 1431 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1432 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1433 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1434 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1435 }; 1436 1437 struct mlx5_ifc_modify_field_select_bits { 1438 u8 modify_field_select[0x20]; 1439 }; 1440 1441 struct mlx5_ifc_field_select_r_roce_np_bits { 1442 u8 field_select_r_roce_np[0x20]; 1443 }; 1444 1445 struct mlx5_ifc_field_select_r_roce_rp_bits { 1446 u8 field_select_r_roce_rp[0x20]; 1447 }; 1448 1449 enum { 1450 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1451 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1452 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1453 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1454 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1455 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1456 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1457 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1458 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1459 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1460 }; 1461 1462 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1463 u8 field_select_8021qaurp[0x20]; 1464 }; 1465 1466 struct mlx5_ifc_phys_layer_cntrs_bits { 1467 u8 time_since_last_clear_high[0x20]; 1468 1469 u8 time_since_last_clear_low[0x20]; 1470 1471 u8 symbol_errors_high[0x20]; 1472 1473 u8 symbol_errors_low[0x20]; 1474 1475 u8 sync_headers_errors_high[0x20]; 1476 1477 u8 sync_headers_errors_low[0x20]; 1478 1479 u8 edpl_bip_errors_lane0_high[0x20]; 1480 1481 u8 edpl_bip_errors_lane0_low[0x20]; 1482 1483 u8 edpl_bip_errors_lane1_high[0x20]; 1484 1485 u8 edpl_bip_errors_lane1_low[0x20]; 1486 1487 u8 edpl_bip_errors_lane2_high[0x20]; 1488 1489 u8 edpl_bip_errors_lane2_low[0x20]; 1490 1491 u8 edpl_bip_errors_lane3_high[0x20]; 1492 1493 u8 edpl_bip_errors_lane3_low[0x20]; 1494 1495 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1496 1497 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1498 1499 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1500 1501 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1502 1503 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1504 1505 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1506 1507 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1508 1509 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1510 1511 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1512 1513 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1514 1515 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1516 1517 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1518 1519 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1520 1521 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1522 1523 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1524 1525 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1526 1527 u8 rs_fec_corrected_blocks_high[0x20]; 1528 1529 u8 rs_fec_corrected_blocks_low[0x20]; 1530 1531 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1532 1533 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1534 1535 u8 rs_fec_no_errors_blocks_high[0x20]; 1536 1537 u8 rs_fec_no_errors_blocks_low[0x20]; 1538 1539 u8 rs_fec_single_error_blocks_high[0x20]; 1540 1541 u8 rs_fec_single_error_blocks_low[0x20]; 1542 1543 u8 rs_fec_corrected_symbols_total_high[0x20]; 1544 1545 u8 rs_fec_corrected_symbols_total_low[0x20]; 1546 1547 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1548 1549 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1550 1551 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1552 1553 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1554 1555 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1556 1557 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1558 1559 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1560 1561 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1562 1563 u8 link_down_events[0x20]; 1564 1565 u8 successful_recovery_events[0x20]; 1566 1567 u8 reserved_at_640[0x180]; 1568 }; 1569 1570 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1571 u8 time_since_last_clear_high[0x20]; 1572 1573 u8 time_since_last_clear_low[0x20]; 1574 1575 u8 phy_received_bits_high[0x20]; 1576 1577 u8 phy_received_bits_low[0x20]; 1578 1579 u8 phy_symbol_errors_high[0x20]; 1580 1581 u8 phy_symbol_errors_low[0x20]; 1582 1583 u8 phy_corrected_bits_high[0x20]; 1584 1585 u8 phy_corrected_bits_low[0x20]; 1586 1587 u8 phy_corrected_bits_lane0_high[0x20]; 1588 1589 u8 phy_corrected_bits_lane0_low[0x20]; 1590 1591 u8 phy_corrected_bits_lane1_high[0x20]; 1592 1593 u8 phy_corrected_bits_lane1_low[0x20]; 1594 1595 u8 phy_corrected_bits_lane2_high[0x20]; 1596 1597 u8 phy_corrected_bits_lane2_low[0x20]; 1598 1599 u8 phy_corrected_bits_lane3_high[0x20]; 1600 1601 u8 phy_corrected_bits_lane3_low[0x20]; 1602 1603 u8 reserved_at_200[0x5c0]; 1604 }; 1605 1606 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1607 u8 symbol_error_counter[0x10]; 1608 1609 u8 link_error_recovery_counter[0x8]; 1610 1611 u8 link_downed_counter[0x8]; 1612 1613 u8 port_rcv_errors[0x10]; 1614 1615 u8 port_rcv_remote_physical_errors[0x10]; 1616 1617 u8 port_rcv_switch_relay_errors[0x10]; 1618 1619 u8 port_xmit_discards[0x10]; 1620 1621 u8 port_xmit_constraint_errors[0x8]; 1622 1623 u8 port_rcv_constraint_errors[0x8]; 1624 1625 u8 reserved_at_70[0x8]; 1626 1627 u8 link_overrun_errors[0x8]; 1628 1629 u8 reserved_at_80[0x10]; 1630 1631 u8 vl_15_dropped[0x10]; 1632 1633 u8 reserved_at_a0[0x80]; 1634 1635 u8 port_xmit_wait[0x20]; 1636 }; 1637 1638 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1639 u8 transmit_queue_high[0x20]; 1640 1641 u8 transmit_queue_low[0x20]; 1642 1643 u8 reserved_at_40[0x780]; 1644 }; 1645 1646 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1647 u8 rx_octets_high[0x20]; 1648 1649 u8 rx_octets_low[0x20]; 1650 1651 u8 reserved_at_40[0xc0]; 1652 1653 u8 rx_frames_high[0x20]; 1654 1655 u8 rx_frames_low[0x20]; 1656 1657 u8 tx_octets_high[0x20]; 1658 1659 u8 tx_octets_low[0x20]; 1660 1661 u8 reserved_at_180[0xc0]; 1662 1663 u8 tx_frames_high[0x20]; 1664 1665 u8 tx_frames_low[0x20]; 1666 1667 u8 rx_pause_high[0x20]; 1668 1669 u8 rx_pause_low[0x20]; 1670 1671 u8 rx_pause_duration_high[0x20]; 1672 1673 u8 rx_pause_duration_low[0x20]; 1674 1675 u8 tx_pause_high[0x20]; 1676 1677 u8 tx_pause_low[0x20]; 1678 1679 u8 tx_pause_duration_high[0x20]; 1680 1681 u8 tx_pause_duration_low[0x20]; 1682 1683 u8 rx_pause_transition_high[0x20]; 1684 1685 u8 rx_pause_transition_low[0x20]; 1686 1687 u8 reserved_at_3c0[0x40]; 1688 1689 u8 device_stall_minor_watermark_cnt_high[0x20]; 1690 1691 u8 device_stall_minor_watermark_cnt_low[0x20]; 1692 1693 u8 device_stall_critical_watermark_cnt_high[0x20]; 1694 1695 u8 device_stall_critical_watermark_cnt_low[0x20]; 1696 1697 u8 reserved_at_480[0x340]; 1698 }; 1699 1700 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1701 u8 port_transmit_wait_high[0x20]; 1702 1703 u8 port_transmit_wait_low[0x20]; 1704 1705 u8 reserved_at_40[0x100]; 1706 1707 u8 rx_buffer_almost_full_high[0x20]; 1708 1709 u8 rx_buffer_almost_full_low[0x20]; 1710 1711 u8 rx_buffer_full_high[0x20]; 1712 1713 u8 rx_buffer_full_low[0x20]; 1714 1715 u8 rx_icrc_encapsulated_high[0x20]; 1716 1717 u8 rx_icrc_encapsulated_low[0x20]; 1718 1719 u8 reserved_at_200[0x5c0]; 1720 }; 1721 1722 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1723 u8 dot3stats_alignment_errors_high[0x20]; 1724 1725 u8 dot3stats_alignment_errors_low[0x20]; 1726 1727 u8 dot3stats_fcs_errors_high[0x20]; 1728 1729 u8 dot3stats_fcs_errors_low[0x20]; 1730 1731 u8 dot3stats_single_collision_frames_high[0x20]; 1732 1733 u8 dot3stats_single_collision_frames_low[0x20]; 1734 1735 u8 dot3stats_multiple_collision_frames_high[0x20]; 1736 1737 u8 dot3stats_multiple_collision_frames_low[0x20]; 1738 1739 u8 dot3stats_sqe_test_errors_high[0x20]; 1740 1741 u8 dot3stats_sqe_test_errors_low[0x20]; 1742 1743 u8 dot3stats_deferred_transmissions_high[0x20]; 1744 1745 u8 dot3stats_deferred_transmissions_low[0x20]; 1746 1747 u8 dot3stats_late_collisions_high[0x20]; 1748 1749 u8 dot3stats_late_collisions_low[0x20]; 1750 1751 u8 dot3stats_excessive_collisions_high[0x20]; 1752 1753 u8 dot3stats_excessive_collisions_low[0x20]; 1754 1755 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1756 1757 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1758 1759 u8 dot3stats_carrier_sense_errors_high[0x20]; 1760 1761 u8 dot3stats_carrier_sense_errors_low[0x20]; 1762 1763 u8 dot3stats_frame_too_longs_high[0x20]; 1764 1765 u8 dot3stats_frame_too_longs_low[0x20]; 1766 1767 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1768 1769 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1770 1771 u8 dot3stats_symbol_errors_high[0x20]; 1772 1773 u8 dot3stats_symbol_errors_low[0x20]; 1774 1775 u8 dot3control_in_unknown_opcodes_high[0x20]; 1776 1777 u8 dot3control_in_unknown_opcodes_low[0x20]; 1778 1779 u8 dot3in_pause_frames_high[0x20]; 1780 1781 u8 dot3in_pause_frames_low[0x20]; 1782 1783 u8 dot3out_pause_frames_high[0x20]; 1784 1785 u8 dot3out_pause_frames_low[0x20]; 1786 1787 u8 reserved_at_400[0x3c0]; 1788 }; 1789 1790 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1791 u8 ether_stats_drop_events_high[0x20]; 1792 1793 u8 ether_stats_drop_events_low[0x20]; 1794 1795 u8 ether_stats_octets_high[0x20]; 1796 1797 u8 ether_stats_octets_low[0x20]; 1798 1799 u8 ether_stats_pkts_high[0x20]; 1800 1801 u8 ether_stats_pkts_low[0x20]; 1802 1803 u8 ether_stats_broadcast_pkts_high[0x20]; 1804 1805 u8 ether_stats_broadcast_pkts_low[0x20]; 1806 1807 u8 ether_stats_multicast_pkts_high[0x20]; 1808 1809 u8 ether_stats_multicast_pkts_low[0x20]; 1810 1811 u8 ether_stats_crc_align_errors_high[0x20]; 1812 1813 u8 ether_stats_crc_align_errors_low[0x20]; 1814 1815 u8 ether_stats_undersize_pkts_high[0x20]; 1816 1817 u8 ether_stats_undersize_pkts_low[0x20]; 1818 1819 u8 ether_stats_oversize_pkts_high[0x20]; 1820 1821 u8 ether_stats_oversize_pkts_low[0x20]; 1822 1823 u8 ether_stats_fragments_high[0x20]; 1824 1825 u8 ether_stats_fragments_low[0x20]; 1826 1827 u8 ether_stats_jabbers_high[0x20]; 1828 1829 u8 ether_stats_jabbers_low[0x20]; 1830 1831 u8 ether_stats_collisions_high[0x20]; 1832 1833 u8 ether_stats_collisions_low[0x20]; 1834 1835 u8 ether_stats_pkts64octets_high[0x20]; 1836 1837 u8 ether_stats_pkts64octets_low[0x20]; 1838 1839 u8 ether_stats_pkts65to127octets_high[0x20]; 1840 1841 u8 ether_stats_pkts65to127octets_low[0x20]; 1842 1843 u8 ether_stats_pkts128to255octets_high[0x20]; 1844 1845 u8 ether_stats_pkts128to255octets_low[0x20]; 1846 1847 u8 ether_stats_pkts256to511octets_high[0x20]; 1848 1849 u8 ether_stats_pkts256to511octets_low[0x20]; 1850 1851 u8 ether_stats_pkts512to1023octets_high[0x20]; 1852 1853 u8 ether_stats_pkts512to1023octets_low[0x20]; 1854 1855 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1856 1857 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1858 1859 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1860 1861 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1862 1863 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1864 1865 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1866 1867 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1868 1869 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1870 1871 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1872 1873 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1874 1875 u8 reserved_at_540[0x280]; 1876 }; 1877 1878 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1879 u8 if_in_octets_high[0x20]; 1880 1881 u8 if_in_octets_low[0x20]; 1882 1883 u8 if_in_ucast_pkts_high[0x20]; 1884 1885 u8 if_in_ucast_pkts_low[0x20]; 1886 1887 u8 if_in_discards_high[0x20]; 1888 1889 u8 if_in_discards_low[0x20]; 1890 1891 u8 if_in_errors_high[0x20]; 1892 1893 u8 if_in_errors_low[0x20]; 1894 1895 u8 if_in_unknown_protos_high[0x20]; 1896 1897 u8 if_in_unknown_protos_low[0x20]; 1898 1899 u8 if_out_octets_high[0x20]; 1900 1901 u8 if_out_octets_low[0x20]; 1902 1903 u8 if_out_ucast_pkts_high[0x20]; 1904 1905 u8 if_out_ucast_pkts_low[0x20]; 1906 1907 u8 if_out_discards_high[0x20]; 1908 1909 u8 if_out_discards_low[0x20]; 1910 1911 u8 if_out_errors_high[0x20]; 1912 1913 u8 if_out_errors_low[0x20]; 1914 1915 u8 if_in_multicast_pkts_high[0x20]; 1916 1917 u8 if_in_multicast_pkts_low[0x20]; 1918 1919 u8 if_in_broadcast_pkts_high[0x20]; 1920 1921 u8 if_in_broadcast_pkts_low[0x20]; 1922 1923 u8 if_out_multicast_pkts_high[0x20]; 1924 1925 u8 if_out_multicast_pkts_low[0x20]; 1926 1927 u8 if_out_broadcast_pkts_high[0x20]; 1928 1929 u8 if_out_broadcast_pkts_low[0x20]; 1930 1931 u8 reserved_at_340[0x480]; 1932 }; 1933 1934 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1935 u8 a_frames_transmitted_ok_high[0x20]; 1936 1937 u8 a_frames_transmitted_ok_low[0x20]; 1938 1939 u8 a_frames_received_ok_high[0x20]; 1940 1941 u8 a_frames_received_ok_low[0x20]; 1942 1943 u8 a_frame_check_sequence_errors_high[0x20]; 1944 1945 u8 a_frame_check_sequence_errors_low[0x20]; 1946 1947 u8 a_alignment_errors_high[0x20]; 1948 1949 u8 a_alignment_errors_low[0x20]; 1950 1951 u8 a_octets_transmitted_ok_high[0x20]; 1952 1953 u8 a_octets_transmitted_ok_low[0x20]; 1954 1955 u8 a_octets_received_ok_high[0x20]; 1956 1957 u8 a_octets_received_ok_low[0x20]; 1958 1959 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1960 1961 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1962 1963 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1964 1965 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1966 1967 u8 a_multicast_frames_received_ok_high[0x20]; 1968 1969 u8 a_multicast_frames_received_ok_low[0x20]; 1970 1971 u8 a_broadcast_frames_received_ok_high[0x20]; 1972 1973 u8 a_broadcast_frames_received_ok_low[0x20]; 1974 1975 u8 a_in_range_length_errors_high[0x20]; 1976 1977 u8 a_in_range_length_errors_low[0x20]; 1978 1979 u8 a_out_of_range_length_field_high[0x20]; 1980 1981 u8 a_out_of_range_length_field_low[0x20]; 1982 1983 u8 a_frame_too_long_errors_high[0x20]; 1984 1985 u8 a_frame_too_long_errors_low[0x20]; 1986 1987 u8 a_symbol_error_during_carrier_high[0x20]; 1988 1989 u8 a_symbol_error_during_carrier_low[0x20]; 1990 1991 u8 a_mac_control_frames_transmitted_high[0x20]; 1992 1993 u8 a_mac_control_frames_transmitted_low[0x20]; 1994 1995 u8 a_mac_control_frames_received_high[0x20]; 1996 1997 u8 a_mac_control_frames_received_low[0x20]; 1998 1999 u8 a_unsupported_opcodes_received_high[0x20]; 2000 2001 u8 a_unsupported_opcodes_received_low[0x20]; 2002 2003 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2004 2005 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2006 2007 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2008 2009 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2010 2011 u8 reserved_at_4c0[0x300]; 2012 }; 2013 2014 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2015 u8 life_time_counter_high[0x20]; 2016 2017 u8 life_time_counter_low[0x20]; 2018 2019 u8 rx_errors[0x20]; 2020 2021 u8 tx_errors[0x20]; 2022 2023 u8 l0_to_recovery_eieos[0x20]; 2024 2025 u8 l0_to_recovery_ts[0x20]; 2026 2027 u8 l0_to_recovery_framing[0x20]; 2028 2029 u8 l0_to_recovery_retrain[0x20]; 2030 2031 u8 crc_error_dllp[0x20]; 2032 2033 u8 crc_error_tlp[0x20]; 2034 2035 u8 tx_overflow_buffer_pkt_high[0x20]; 2036 2037 u8 tx_overflow_buffer_pkt_low[0x20]; 2038 2039 u8 outbound_stalled_reads[0x20]; 2040 2041 u8 outbound_stalled_writes[0x20]; 2042 2043 u8 outbound_stalled_reads_events[0x20]; 2044 2045 u8 outbound_stalled_writes_events[0x20]; 2046 2047 u8 reserved_at_200[0x5c0]; 2048 }; 2049 2050 struct mlx5_ifc_cmd_inter_comp_event_bits { 2051 u8 command_completion_vector[0x20]; 2052 2053 u8 reserved_at_20[0xc0]; 2054 }; 2055 2056 struct mlx5_ifc_stall_vl_event_bits { 2057 u8 reserved_at_0[0x18]; 2058 u8 port_num[0x1]; 2059 u8 reserved_at_19[0x3]; 2060 u8 vl[0x4]; 2061 2062 u8 reserved_at_20[0xa0]; 2063 }; 2064 2065 struct mlx5_ifc_db_bf_congestion_event_bits { 2066 u8 event_subtype[0x8]; 2067 u8 reserved_at_8[0x8]; 2068 u8 congestion_level[0x8]; 2069 u8 reserved_at_18[0x8]; 2070 2071 u8 reserved_at_20[0xa0]; 2072 }; 2073 2074 struct mlx5_ifc_gpio_event_bits { 2075 u8 reserved_at_0[0x60]; 2076 2077 u8 gpio_event_hi[0x20]; 2078 2079 u8 gpio_event_lo[0x20]; 2080 2081 u8 reserved_at_a0[0x40]; 2082 }; 2083 2084 struct mlx5_ifc_port_state_change_event_bits { 2085 u8 reserved_at_0[0x40]; 2086 2087 u8 port_num[0x4]; 2088 u8 reserved_at_44[0x1c]; 2089 2090 u8 reserved_at_60[0x80]; 2091 }; 2092 2093 struct mlx5_ifc_dropped_packet_logged_bits { 2094 u8 reserved_at_0[0xe0]; 2095 }; 2096 2097 enum { 2098 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2099 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2100 }; 2101 2102 struct mlx5_ifc_cq_error_bits { 2103 u8 reserved_at_0[0x8]; 2104 u8 cqn[0x18]; 2105 2106 u8 reserved_at_20[0x20]; 2107 2108 u8 reserved_at_40[0x18]; 2109 u8 syndrome[0x8]; 2110 2111 u8 reserved_at_60[0x80]; 2112 }; 2113 2114 struct mlx5_ifc_rdma_page_fault_event_bits { 2115 u8 bytes_committed[0x20]; 2116 2117 u8 r_key[0x20]; 2118 2119 u8 reserved_at_40[0x10]; 2120 u8 packet_len[0x10]; 2121 2122 u8 rdma_op_len[0x20]; 2123 2124 u8 rdma_va[0x40]; 2125 2126 u8 reserved_at_c0[0x5]; 2127 u8 rdma[0x1]; 2128 u8 write[0x1]; 2129 u8 requestor[0x1]; 2130 u8 qp_number[0x18]; 2131 }; 2132 2133 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2134 u8 bytes_committed[0x20]; 2135 2136 u8 reserved_at_20[0x10]; 2137 u8 wqe_index[0x10]; 2138 2139 u8 reserved_at_40[0x10]; 2140 u8 len[0x10]; 2141 2142 u8 reserved_at_60[0x60]; 2143 2144 u8 reserved_at_c0[0x5]; 2145 u8 rdma[0x1]; 2146 u8 write_read[0x1]; 2147 u8 requestor[0x1]; 2148 u8 qpn[0x18]; 2149 }; 2150 2151 struct mlx5_ifc_qp_events_bits { 2152 u8 reserved_at_0[0xa0]; 2153 2154 u8 type[0x8]; 2155 u8 reserved_at_a8[0x18]; 2156 2157 u8 reserved_at_c0[0x8]; 2158 u8 qpn_rqn_sqn[0x18]; 2159 }; 2160 2161 struct mlx5_ifc_dct_events_bits { 2162 u8 reserved_at_0[0xc0]; 2163 2164 u8 reserved_at_c0[0x8]; 2165 u8 dct_number[0x18]; 2166 }; 2167 2168 struct mlx5_ifc_comp_event_bits { 2169 u8 reserved_at_0[0xc0]; 2170 2171 u8 reserved_at_c0[0x8]; 2172 u8 cq_number[0x18]; 2173 }; 2174 2175 enum { 2176 MLX5_QPC_STATE_RST = 0x0, 2177 MLX5_QPC_STATE_INIT = 0x1, 2178 MLX5_QPC_STATE_RTR = 0x2, 2179 MLX5_QPC_STATE_RTS = 0x3, 2180 MLX5_QPC_STATE_SQER = 0x4, 2181 MLX5_QPC_STATE_ERR = 0x6, 2182 MLX5_QPC_STATE_SQD = 0x7, 2183 MLX5_QPC_STATE_SUSPENDED = 0x9, 2184 }; 2185 2186 enum { 2187 MLX5_QPC_ST_RC = 0x0, 2188 MLX5_QPC_ST_UC = 0x1, 2189 MLX5_QPC_ST_UD = 0x2, 2190 MLX5_QPC_ST_XRC = 0x3, 2191 MLX5_QPC_ST_DCI = 0x5, 2192 MLX5_QPC_ST_QP0 = 0x7, 2193 MLX5_QPC_ST_QP1 = 0x8, 2194 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2195 MLX5_QPC_ST_REG_UMR = 0xc, 2196 }; 2197 2198 enum { 2199 MLX5_QPC_PM_STATE_ARMED = 0x0, 2200 MLX5_QPC_PM_STATE_REARM = 0x1, 2201 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2202 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2203 }; 2204 2205 enum { 2206 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2207 }; 2208 2209 enum { 2210 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2211 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2212 }; 2213 2214 enum { 2215 MLX5_QPC_MTU_256_BYTES = 0x1, 2216 MLX5_QPC_MTU_512_BYTES = 0x2, 2217 MLX5_QPC_MTU_1K_BYTES = 0x3, 2218 MLX5_QPC_MTU_2K_BYTES = 0x4, 2219 MLX5_QPC_MTU_4K_BYTES = 0x5, 2220 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2221 }; 2222 2223 enum { 2224 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2225 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2226 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2227 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2228 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2229 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2230 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2231 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2232 }; 2233 2234 enum { 2235 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2236 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2237 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2238 }; 2239 2240 enum { 2241 MLX5_QPC_CS_RES_DISABLE = 0x0, 2242 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2243 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2244 }; 2245 2246 struct mlx5_ifc_qpc_bits { 2247 u8 state[0x4]; 2248 u8 lag_tx_port_affinity[0x4]; 2249 u8 st[0x8]; 2250 u8 reserved_at_10[0x3]; 2251 u8 pm_state[0x2]; 2252 u8 reserved_at_15[0x3]; 2253 u8 offload_type[0x4]; 2254 u8 end_padding_mode[0x2]; 2255 u8 reserved_at_1e[0x2]; 2256 2257 u8 wq_signature[0x1]; 2258 u8 block_lb_mc[0x1]; 2259 u8 atomic_like_write_en[0x1]; 2260 u8 latency_sensitive[0x1]; 2261 u8 reserved_at_24[0x1]; 2262 u8 drain_sigerr[0x1]; 2263 u8 reserved_at_26[0x2]; 2264 u8 pd[0x18]; 2265 2266 u8 mtu[0x3]; 2267 u8 log_msg_max[0x5]; 2268 u8 reserved_at_48[0x1]; 2269 u8 log_rq_size[0x4]; 2270 u8 log_rq_stride[0x3]; 2271 u8 no_sq[0x1]; 2272 u8 log_sq_size[0x4]; 2273 u8 reserved_at_55[0x6]; 2274 u8 rlky[0x1]; 2275 u8 ulp_stateless_offload_mode[0x4]; 2276 2277 u8 counter_set_id[0x8]; 2278 u8 uar_page[0x18]; 2279 2280 u8 reserved_at_80[0x8]; 2281 u8 user_index[0x18]; 2282 2283 u8 reserved_at_a0[0x3]; 2284 u8 log_page_size[0x5]; 2285 u8 remote_qpn[0x18]; 2286 2287 struct mlx5_ifc_ads_bits primary_address_path; 2288 2289 struct mlx5_ifc_ads_bits secondary_address_path; 2290 2291 u8 log_ack_req_freq[0x4]; 2292 u8 reserved_at_384[0x4]; 2293 u8 log_sra_max[0x3]; 2294 u8 reserved_at_38b[0x2]; 2295 u8 retry_count[0x3]; 2296 u8 rnr_retry[0x3]; 2297 u8 reserved_at_393[0x1]; 2298 u8 fre[0x1]; 2299 u8 cur_rnr_retry[0x3]; 2300 u8 cur_retry_count[0x3]; 2301 u8 reserved_at_39b[0x5]; 2302 2303 u8 reserved_at_3a0[0x20]; 2304 2305 u8 reserved_at_3c0[0x8]; 2306 u8 next_send_psn[0x18]; 2307 2308 u8 reserved_at_3e0[0x8]; 2309 u8 cqn_snd[0x18]; 2310 2311 u8 reserved_at_400[0x8]; 2312 u8 deth_sqpn[0x18]; 2313 2314 u8 reserved_at_420[0x20]; 2315 2316 u8 reserved_at_440[0x8]; 2317 u8 last_acked_psn[0x18]; 2318 2319 u8 reserved_at_460[0x8]; 2320 u8 ssn[0x18]; 2321 2322 u8 reserved_at_480[0x8]; 2323 u8 log_rra_max[0x3]; 2324 u8 reserved_at_48b[0x1]; 2325 u8 atomic_mode[0x4]; 2326 u8 rre[0x1]; 2327 u8 rwe[0x1]; 2328 u8 rae[0x1]; 2329 u8 reserved_at_493[0x1]; 2330 u8 page_offset[0x6]; 2331 u8 reserved_at_49a[0x3]; 2332 u8 cd_slave_receive[0x1]; 2333 u8 cd_slave_send[0x1]; 2334 u8 cd_master[0x1]; 2335 2336 u8 reserved_at_4a0[0x3]; 2337 u8 min_rnr_nak[0x5]; 2338 u8 next_rcv_psn[0x18]; 2339 2340 u8 reserved_at_4c0[0x8]; 2341 u8 xrcd[0x18]; 2342 2343 u8 reserved_at_4e0[0x8]; 2344 u8 cqn_rcv[0x18]; 2345 2346 u8 dbr_addr[0x40]; 2347 2348 u8 q_key[0x20]; 2349 2350 u8 reserved_at_560[0x5]; 2351 u8 rq_type[0x3]; 2352 u8 srqn_rmpn_xrqn[0x18]; 2353 2354 u8 reserved_at_580[0x8]; 2355 u8 rmsn[0x18]; 2356 2357 u8 hw_sq_wqebb_counter[0x10]; 2358 u8 sw_sq_wqebb_counter[0x10]; 2359 2360 u8 hw_rq_counter[0x20]; 2361 2362 u8 sw_rq_counter[0x20]; 2363 2364 u8 reserved_at_600[0x20]; 2365 2366 u8 reserved_at_620[0xf]; 2367 u8 cgs[0x1]; 2368 u8 cs_req[0x8]; 2369 u8 cs_res[0x8]; 2370 2371 u8 dc_access_key[0x40]; 2372 2373 u8 reserved_at_680[0x3]; 2374 u8 dbr_umem_valid[0x1]; 2375 2376 u8 reserved_at_684[0xbc]; 2377 }; 2378 2379 struct mlx5_ifc_roce_addr_layout_bits { 2380 u8 source_l3_address[16][0x8]; 2381 2382 u8 reserved_at_80[0x3]; 2383 u8 vlan_valid[0x1]; 2384 u8 vlan_id[0xc]; 2385 u8 source_mac_47_32[0x10]; 2386 2387 u8 source_mac_31_0[0x20]; 2388 2389 u8 reserved_at_c0[0x14]; 2390 u8 roce_l3_type[0x4]; 2391 u8 roce_version[0x8]; 2392 2393 u8 reserved_at_e0[0x20]; 2394 }; 2395 2396 union mlx5_ifc_hca_cap_union_bits { 2397 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2398 struct mlx5_ifc_odp_cap_bits odp_cap; 2399 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2400 struct mlx5_ifc_roce_cap_bits roce_cap; 2401 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2402 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2403 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2404 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2405 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2406 struct mlx5_ifc_qos_cap_bits qos_cap; 2407 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2408 u8 reserved_at_0[0x8000]; 2409 }; 2410 2411 enum { 2412 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2413 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2414 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2415 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2416 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2417 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2418 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2419 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2420 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2421 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2422 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2423 }; 2424 2425 struct mlx5_ifc_vlan_bits { 2426 u8 ethtype[0x10]; 2427 u8 prio[0x3]; 2428 u8 cfi[0x1]; 2429 u8 vid[0xc]; 2430 }; 2431 2432 struct mlx5_ifc_flow_context_bits { 2433 struct mlx5_ifc_vlan_bits push_vlan; 2434 2435 u8 group_id[0x20]; 2436 2437 u8 reserved_at_40[0x8]; 2438 u8 flow_tag[0x18]; 2439 2440 u8 reserved_at_60[0x10]; 2441 u8 action[0x10]; 2442 2443 u8 reserved_at_80[0x8]; 2444 u8 destination_list_size[0x18]; 2445 2446 u8 reserved_at_a0[0x8]; 2447 u8 flow_counter_list_size[0x18]; 2448 2449 u8 packet_reformat_id[0x20]; 2450 2451 u8 modify_header_id[0x20]; 2452 2453 struct mlx5_ifc_vlan_bits push_vlan_2; 2454 2455 u8 reserved_at_120[0xe0]; 2456 2457 struct mlx5_ifc_fte_match_param_bits match_value; 2458 2459 u8 reserved_at_1200[0x600]; 2460 2461 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2462 }; 2463 2464 enum { 2465 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2466 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2467 }; 2468 2469 struct mlx5_ifc_xrc_srqc_bits { 2470 u8 state[0x4]; 2471 u8 log_xrc_srq_size[0x4]; 2472 u8 reserved_at_8[0x18]; 2473 2474 u8 wq_signature[0x1]; 2475 u8 cont_srq[0x1]; 2476 u8 reserved_at_22[0x1]; 2477 u8 rlky[0x1]; 2478 u8 basic_cyclic_rcv_wqe[0x1]; 2479 u8 log_rq_stride[0x3]; 2480 u8 xrcd[0x18]; 2481 2482 u8 page_offset[0x6]; 2483 u8 reserved_at_46[0x1]; 2484 u8 dbr_umem_valid[0x1]; 2485 u8 cqn[0x18]; 2486 2487 u8 reserved_at_60[0x20]; 2488 2489 u8 user_index_equal_xrc_srqn[0x1]; 2490 u8 reserved_at_81[0x1]; 2491 u8 log_page_size[0x6]; 2492 u8 user_index[0x18]; 2493 2494 u8 reserved_at_a0[0x20]; 2495 2496 u8 reserved_at_c0[0x8]; 2497 u8 pd[0x18]; 2498 2499 u8 lwm[0x10]; 2500 u8 wqe_cnt[0x10]; 2501 2502 u8 reserved_at_100[0x40]; 2503 2504 u8 db_record_addr_h[0x20]; 2505 2506 u8 db_record_addr_l[0x1e]; 2507 u8 reserved_at_17e[0x2]; 2508 2509 u8 reserved_at_180[0x80]; 2510 }; 2511 2512 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2513 u8 counter_error_queues[0x20]; 2514 2515 u8 total_error_queues[0x20]; 2516 2517 u8 send_queue_priority_update_flow[0x20]; 2518 2519 u8 reserved_at_60[0x20]; 2520 2521 u8 nic_receive_steering_discard[0x40]; 2522 2523 u8 receive_discard_vport_down[0x40]; 2524 2525 u8 transmit_discard_vport_down[0x40]; 2526 2527 u8 reserved_at_140[0xec0]; 2528 }; 2529 2530 struct mlx5_ifc_traffic_counter_bits { 2531 u8 packets[0x40]; 2532 2533 u8 octets[0x40]; 2534 }; 2535 2536 struct mlx5_ifc_tisc_bits { 2537 u8 strict_lag_tx_port_affinity[0x1]; 2538 u8 reserved_at_1[0x3]; 2539 u8 lag_tx_port_affinity[0x04]; 2540 2541 u8 reserved_at_8[0x4]; 2542 u8 prio[0x4]; 2543 u8 reserved_at_10[0x10]; 2544 2545 u8 reserved_at_20[0x100]; 2546 2547 u8 reserved_at_120[0x8]; 2548 u8 transport_domain[0x18]; 2549 2550 u8 reserved_at_140[0x8]; 2551 u8 underlay_qpn[0x18]; 2552 u8 reserved_at_160[0x3a0]; 2553 }; 2554 2555 enum { 2556 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2557 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2558 }; 2559 2560 enum { 2561 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2562 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2563 }; 2564 2565 enum { 2566 MLX5_RX_HASH_FN_NONE = 0x0, 2567 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2568 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2569 }; 2570 2571 enum { 2572 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2573 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2574 }; 2575 2576 struct mlx5_ifc_tirc_bits { 2577 u8 reserved_at_0[0x20]; 2578 2579 u8 disp_type[0x4]; 2580 u8 reserved_at_24[0x1c]; 2581 2582 u8 reserved_at_40[0x40]; 2583 2584 u8 reserved_at_80[0x4]; 2585 u8 lro_timeout_period_usecs[0x10]; 2586 u8 lro_enable_mask[0x4]; 2587 u8 lro_max_ip_payload_size[0x8]; 2588 2589 u8 reserved_at_a0[0x40]; 2590 2591 u8 reserved_at_e0[0x8]; 2592 u8 inline_rqn[0x18]; 2593 2594 u8 rx_hash_symmetric[0x1]; 2595 u8 reserved_at_101[0x1]; 2596 u8 tunneled_offload_en[0x1]; 2597 u8 reserved_at_103[0x5]; 2598 u8 indirect_table[0x18]; 2599 2600 u8 rx_hash_fn[0x4]; 2601 u8 reserved_at_124[0x2]; 2602 u8 self_lb_block[0x2]; 2603 u8 transport_domain[0x18]; 2604 2605 u8 rx_hash_toeplitz_key[10][0x20]; 2606 2607 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2608 2609 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2610 2611 u8 reserved_at_2c0[0x4c0]; 2612 }; 2613 2614 enum { 2615 MLX5_SRQC_STATE_GOOD = 0x0, 2616 MLX5_SRQC_STATE_ERROR = 0x1, 2617 }; 2618 2619 struct mlx5_ifc_srqc_bits { 2620 u8 state[0x4]; 2621 u8 log_srq_size[0x4]; 2622 u8 reserved_at_8[0x18]; 2623 2624 u8 wq_signature[0x1]; 2625 u8 cont_srq[0x1]; 2626 u8 reserved_at_22[0x1]; 2627 u8 rlky[0x1]; 2628 u8 reserved_at_24[0x1]; 2629 u8 log_rq_stride[0x3]; 2630 u8 xrcd[0x18]; 2631 2632 u8 page_offset[0x6]; 2633 u8 reserved_at_46[0x2]; 2634 u8 cqn[0x18]; 2635 2636 u8 reserved_at_60[0x20]; 2637 2638 u8 reserved_at_80[0x2]; 2639 u8 log_page_size[0x6]; 2640 u8 reserved_at_88[0x18]; 2641 2642 u8 reserved_at_a0[0x20]; 2643 2644 u8 reserved_at_c0[0x8]; 2645 u8 pd[0x18]; 2646 2647 u8 lwm[0x10]; 2648 u8 wqe_cnt[0x10]; 2649 2650 u8 reserved_at_100[0x40]; 2651 2652 u8 dbr_addr[0x40]; 2653 2654 u8 reserved_at_180[0x80]; 2655 }; 2656 2657 enum { 2658 MLX5_SQC_STATE_RST = 0x0, 2659 MLX5_SQC_STATE_RDY = 0x1, 2660 MLX5_SQC_STATE_ERR = 0x3, 2661 }; 2662 2663 struct mlx5_ifc_sqc_bits { 2664 u8 rlky[0x1]; 2665 u8 cd_master[0x1]; 2666 u8 fre[0x1]; 2667 u8 flush_in_error_en[0x1]; 2668 u8 allow_multi_pkt_send_wqe[0x1]; 2669 u8 min_wqe_inline_mode[0x3]; 2670 u8 state[0x4]; 2671 u8 reg_umr[0x1]; 2672 u8 allow_swp[0x1]; 2673 u8 hairpin[0x1]; 2674 u8 reserved_at_f[0x11]; 2675 2676 u8 reserved_at_20[0x8]; 2677 u8 user_index[0x18]; 2678 2679 u8 reserved_at_40[0x8]; 2680 u8 cqn[0x18]; 2681 2682 u8 reserved_at_60[0x8]; 2683 u8 hairpin_peer_rq[0x18]; 2684 2685 u8 reserved_at_80[0x10]; 2686 u8 hairpin_peer_vhca[0x10]; 2687 2688 u8 reserved_at_a0[0x50]; 2689 2690 u8 packet_pacing_rate_limit_index[0x10]; 2691 u8 tis_lst_sz[0x10]; 2692 u8 reserved_at_110[0x10]; 2693 2694 u8 reserved_at_120[0x40]; 2695 2696 u8 reserved_at_160[0x8]; 2697 u8 tis_num_0[0x18]; 2698 2699 struct mlx5_ifc_wq_bits wq; 2700 }; 2701 2702 enum { 2703 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2704 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2705 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2706 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2707 }; 2708 2709 struct mlx5_ifc_scheduling_context_bits { 2710 u8 element_type[0x8]; 2711 u8 reserved_at_8[0x18]; 2712 2713 u8 element_attributes[0x20]; 2714 2715 u8 parent_element_id[0x20]; 2716 2717 u8 reserved_at_60[0x40]; 2718 2719 u8 bw_share[0x20]; 2720 2721 u8 max_average_bw[0x20]; 2722 2723 u8 reserved_at_e0[0x120]; 2724 }; 2725 2726 struct mlx5_ifc_rqtc_bits { 2727 u8 reserved_at_0[0xa0]; 2728 2729 u8 reserved_at_a0[0x10]; 2730 u8 rqt_max_size[0x10]; 2731 2732 u8 reserved_at_c0[0x10]; 2733 u8 rqt_actual_size[0x10]; 2734 2735 u8 reserved_at_e0[0x6a0]; 2736 2737 struct mlx5_ifc_rq_num_bits rq_num[0]; 2738 }; 2739 2740 enum { 2741 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2742 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2743 }; 2744 2745 enum { 2746 MLX5_RQC_STATE_RST = 0x0, 2747 MLX5_RQC_STATE_RDY = 0x1, 2748 MLX5_RQC_STATE_ERR = 0x3, 2749 }; 2750 2751 struct mlx5_ifc_rqc_bits { 2752 u8 rlky[0x1]; 2753 u8 delay_drop_en[0x1]; 2754 u8 scatter_fcs[0x1]; 2755 u8 vsd[0x1]; 2756 u8 mem_rq_type[0x4]; 2757 u8 state[0x4]; 2758 u8 reserved_at_c[0x1]; 2759 u8 flush_in_error_en[0x1]; 2760 u8 hairpin[0x1]; 2761 u8 reserved_at_f[0x11]; 2762 2763 u8 reserved_at_20[0x8]; 2764 u8 user_index[0x18]; 2765 2766 u8 reserved_at_40[0x8]; 2767 u8 cqn[0x18]; 2768 2769 u8 counter_set_id[0x8]; 2770 u8 reserved_at_68[0x18]; 2771 2772 u8 reserved_at_80[0x8]; 2773 u8 rmpn[0x18]; 2774 2775 u8 reserved_at_a0[0x8]; 2776 u8 hairpin_peer_sq[0x18]; 2777 2778 u8 reserved_at_c0[0x10]; 2779 u8 hairpin_peer_vhca[0x10]; 2780 2781 u8 reserved_at_e0[0xa0]; 2782 2783 struct mlx5_ifc_wq_bits wq; 2784 }; 2785 2786 enum { 2787 MLX5_RMPC_STATE_RDY = 0x1, 2788 MLX5_RMPC_STATE_ERR = 0x3, 2789 }; 2790 2791 struct mlx5_ifc_rmpc_bits { 2792 u8 reserved_at_0[0x8]; 2793 u8 state[0x4]; 2794 u8 reserved_at_c[0x14]; 2795 2796 u8 basic_cyclic_rcv_wqe[0x1]; 2797 u8 reserved_at_21[0x1f]; 2798 2799 u8 reserved_at_40[0x140]; 2800 2801 struct mlx5_ifc_wq_bits wq; 2802 }; 2803 2804 struct mlx5_ifc_nic_vport_context_bits { 2805 u8 reserved_at_0[0x5]; 2806 u8 min_wqe_inline_mode[0x3]; 2807 u8 reserved_at_8[0x15]; 2808 u8 disable_mc_local_lb[0x1]; 2809 u8 disable_uc_local_lb[0x1]; 2810 u8 roce_en[0x1]; 2811 2812 u8 arm_change_event[0x1]; 2813 u8 reserved_at_21[0x1a]; 2814 u8 event_on_mtu[0x1]; 2815 u8 event_on_promisc_change[0x1]; 2816 u8 event_on_vlan_change[0x1]; 2817 u8 event_on_mc_address_change[0x1]; 2818 u8 event_on_uc_address_change[0x1]; 2819 2820 u8 reserved_at_40[0xc]; 2821 2822 u8 affiliation_criteria[0x4]; 2823 u8 affiliated_vhca_id[0x10]; 2824 2825 u8 reserved_at_60[0xd0]; 2826 2827 u8 mtu[0x10]; 2828 2829 u8 system_image_guid[0x40]; 2830 u8 port_guid[0x40]; 2831 u8 node_guid[0x40]; 2832 2833 u8 reserved_at_200[0x140]; 2834 u8 qkey_violation_counter[0x10]; 2835 u8 reserved_at_350[0x430]; 2836 2837 u8 promisc_uc[0x1]; 2838 u8 promisc_mc[0x1]; 2839 u8 promisc_all[0x1]; 2840 u8 reserved_at_783[0x2]; 2841 u8 allowed_list_type[0x3]; 2842 u8 reserved_at_788[0xc]; 2843 u8 allowed_list_size[0xc]; 2844 2845 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2846 2847 u8 reserved_at_7e0[0x20]; 2848 2849 u8 current_uc_mac_address[0][0x40]; 2850 }; 2851 2852 enum { 2853 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2854 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2855 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2856 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2857 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2858 }; 2859 2860 struct mlx5_ifc_mkc_bits { 2861 u8 reserved_at_0[0x1]; 2862 u8 free[0x1]; 2863 u8 reserved_at_2[0x1]; 2864 u8 access_mode_4_2[0x3]; 2865 u8 reserved_at_6[0x7]; 2866 u8 relaxed_ordering_write[0x1]; 2867 u8 reserved_at_e[0x1]; 2868 u8 small_fence_on_rdma_read_response[0x1]; 2869 u8 umr_en[0x1]; 2870 u8 a[0x1]; 2871 u8 rw[0x1]; 2872 u8 rr[0x1]; 2873 u8 lw[0x1]; 2874 u8 lr[0x1]; 2875 u8 access_mode_1_0[0x2]; 2876 u8 reserved_at_18[0x8]; 2877 2878 u8 qpn[0x18]; 2879 u8 mkey_7_0[0x8]; 2880 2881 u8 reserved_at_40[0x20]; 2882 2883 u8 length64[0x1]; 2884 u8 bsf_en[0x1]; 2885 u8 sync_umr[0x1]; 2886 u8 reserved_at_63[0x2]; 2887 u8 expected_sigerr_count[0x1]; 2888 u8 reserved_at_66[0x1]; 2889 u8 en_rinval[0x1]; 2890 u8 pd[0x18]; 2891 2892 u8 start_addr[0x40]; 2893 2894 u8 len[0x40]; 2895 2896 u8 bsf_octword_size[0x20]; 2897 2898 u8 reserved_at_120[0x80]; 2899 2900 u8 translations_octword_size[0x20]; 2901 2902 u8 reserved_at_1c0[0x1b]; 2903 u8 log_page_size[0x5]; 2904 2905 u8 reserved_at_1e0[0x20]; 2906 }; 2907 2908 struct mlx5_ifc_pkey_bits { 2909 u8 reserved_at_0[0x10]; 2910 u8 pkey[0x10]; 2911 }; 2912 2913 struct mlx5_ifc_array128_auto_bits { 2914 u8 array128_auto[16][0x8]; 2915 }; 2916 2917 struct mlx5_ifc_hca_vport_context_bits { 2918 u8 field_select[0x20]; 2919 2920 u8 reserved_at_20[0xe0]; 2921 2922 u8 sm_virt_aware[0x1]; 2923 u8 has_smi[0x1]; 2924 u8 has_raw[0x1]; 2925 u8 grh_required[0x1]; 2926 u8 reserved_at_104[0xc]; 2927 u8 port_physical_state[0x4]; 2928 u8 vport_state_policy[0x4]; 2929 u8 port_state[0x4]; 2930 u8 vport_state[0x4]; 2931 2932 u8 reserved_at_120[0x20]; 2933 2934 u8 system_image_guid[0x40]; 2935 2936 u8 port_guid[0x40]; 2937 2938 u8 node_guid[0x40]; 2939 2940 u8 cap_mask1[0x20]; 2941 2942 u8 cap_mask1_field_select[0x20]; 2943 2944 u8 cap_mask2[0x20]; 2945 2946 u8 cap_mask2_field_select[0x20]; 2947 2948 u8 reserved_at_280[0x80]; 2949 2950 u8 lid[0x10]; 2951 u8 reserved_at_310[0x4]; 2952 u8 init_type_reply[0x4]; 2953 u8 lmc[0x3]; 2954 u8 subnet_timeout[0x5]; 2955 2956 u8 sm_lid[0x10]; 2957 u8 sm_sl[0x4]; 2958 u8 reserved_at_334[0xc]; 2959 2960 u8 qkey_violation_counter[0x10]; 2961 u8 pkey_violation_counter[0x10]; 2962 2963 u8 reserved_at_360[0xca0]; 2964 }; 2965 2966 struct mlx5_ifc_esw_vport_context_bits { 2967 u8 reserved_at_0[0x3]; 2968 u8 vport_svlan_strip[0x1]; 2969 u8 vport_cvlan_strip[0x1]; 2970 u8 vport_svlan_insert[0x1]; 2971 u8 vport_cvlan_insert[0x2]; 2972 u8 reserved_at_8[0x18]; 2973 2974 u8 reserved_at_20[0x20]; 2975 2976 u8 svlan_cfi[0x1]; 2977 u8 svlan_pcp[0x3]; 2978 u8 svlan_id[0xc]; 2979 u8 cvlan_cfi[0x1]; 2980 u8 cvlan_pcp[0x3]; 2981 u8 cvlan_id[0xc]; 2982 2983 u8 reserved_at_60[0x7a0]; 2984 }; 2985 2986 enum { 2987 MLX5_EQC_STATUS_OK = 0x0, 2988 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2989 }; 2990 2991 enum { 2992 MLX5_EQC_ST_ARMED = 0x9, 2993 MLX5_EQC_ST_FIRED = 0xa, 2994 }; 2995 2996 struct mlx5_ifc_eqc_bits { 2997 u8 status[0x4]; 2998 u8 reserved_at_4[0x9]; 2999 u8 ec[0x1]; 3000 u8 oi[0x1]; 3001 u8 reserved_at_f[0x5]; 3002 u8 st[0x4]; 3003 u8 reserved_at_18[0x8]; 3004 3005 u8 reserved_at_20[0x20]; 3006 3007 u8 reserved_at_40[0x14]; 3008 u8 page_offset[0x6]; 3009 u8 reserved_at_5a[0x6]; 3010 3011 u8 reserved_at_60[0x3]; 3012 u8 log_eq_size[0x5]; 3013 u8 uar_page[0x18]; 3014 3015 u8 reserved_at_80[0x20]; 3016 3017 u8 reserved_at_a0[0x18]; 3018 u8 intr[0x8]; 3019 3020 u8 reserved_at_c0[0x3]; 3021 u8 log_page_size[0x5]; 3022 u8 reserved_at_c8[0x18]; 3023 3024 u8 reserved_at_e0[0x60]; 3025 3026 u8 reserved_at_140[0x8]; 3027 u8 consumer_counter[0x18]; 3028 3029 u8 reserved_at_160[0x8]; 3030 u8 producer_counter[0x18]; 3031 3032 u8 reserved_at_180[0x80]; 3033 }; 3034 3035 enum { 3036 MLX5_DCTC_STATE_ACTIVE = 0x0, 3037 MLX5_DCTC_STATE_DRAINING = 0x1, 3038 MLX5_DCTC_STATE_DRAINED = 0x2, 3039 }; 3040 3041 enum { 3042 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3043 MLX5_DCTC_CS_RES_NA = 0x1, 3044 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3045 }; 3046 3047 enum { 3048 MLX5_DCTC_MTU_256_BYTES = 0x1, 3049 MLX5_DCTC_MTU_512_BYTES = 0x2, 3050 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3051 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3052 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3053 }; 3054 3055 struct mlx5_ifc_dctc_bits { 3056 u8 reserved_at_0[0x4]; 3057 u8 state[0x4]; 3058 u8 reserved_at_8[0x18]; 3059 3060 u8 reserved_at_20[0x8]; 3061 u8 user_index[0x18]; 3062 3063 u8 reserved_at_40[0x8]; 3064 u8 cqn[0x18]; 3065 3066 u8 counter_set_id[0x8]; 3067 u8 atomic_mode[0x4]; 3068 u8 rre[0x1]; 3069 u8 rwe[0x1]; 3070 u8 rae[0x1]; 3071 u8 atomic_like_write_en[0x1]; 3072 u8 latency_sensitive[0x1]; 3073 u8 rlky[0x1]; 3074 u8 free_ar[0x1]; 3075 u8 reserved_at_73[0xd]; 3076 3077 u8 reserved_at_80[0x8]; 3078 u8 cs_res[0x8]; 3079 u8 reserved_at_90[0x3]; 3080 u8 min_rnr_nak[0x5]; 3081 u8 reserved_at_98[0x8]; 3082 3083 u8 reserved_at_a0[0x8]; 3084 u8 srqn_xrqn[0x18]; 3085 3086 u8 reserved_at_c0[0x8]; 3087 u8 pd[0x18]; 3088 3089 u8 tclass[0x8]; 3090 u8 reserved_at_e8[0x4]; 3091 u8 flow_label[0x14]; 3092 3093 u8 dc_access_key[0x40]; 3094 3095 u8 reserved_at_140[0x5]; 3096 u8 mtu[0x3]; 3097 u8 port[0x8]; 3098 u8 pkey_index[0x10]; 3099 3100 u8 reserved_at_160[0x8]; 3101 u8 my_addr_index[0x8]; 3102 u8 reserved_at_170[0x8]; 3103 u8 hop_limit[0x8]; 3104 3105 u8 dc_access_key_violation_count[0x20]; 3106 3107 u8 reserved_at_1a0[0x14]; 3108 u8 dei_cfi[0x1]; 3109 u8 eth_prio[0x3]; 3110 u8 ecn[0x2]; 3111 u8 dscp[0x6]; 3112 3113 u8 reserved_at_1c0[0x40]; 3114 }; 3115 3116 enum { 3117 MLX5_CQC_STATUS_OK = 0x0, 3118 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3119 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3120 }; 3121 3122 enum { 3123 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3124 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3125 }; 3126 3127 enum { 3128 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3129 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3130 MLX5_CQC_ST_FIRED = 0xa, 3131 }; 3132 3133 enum { 3134 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3135 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3136 MLX5_CQ_PERIOD_NUM_MODES 3137 }; 3138 3139 struct mlx5_ifc_cqc_bits { 3140 u8 status[0x4]; 3141 u8 reserved_at_4[0x2]; 3142 u8 dbr_umem_valid[0x1]; 3143 u8 reserved_at_7[0x1]; 3144 u8 cqe_sz[0x3]; 3145 u8 cc[0x1]; 3146 u8 reserved_at_c[0x1]; 3147 u8 scqe_break_moderation_en[0x1]; 3148 u8 oi[0x1]; 3149 u8 cq_period_mode[0x2]; 3150 u8 cqe_comp_en[0x1]; 3151 u8 mini_cqe_res_format[0x2]; 3152 u8 st[0x4]; 3153 u8 reserved_at_18[0x8]; 3154 3155 u8 reserved_at_20[0x20]; 3156 3157 u8 reserved_at_40[0x14]; 3158 u8 page_offset[0x6]; 3159 u8 reserved_at_5a[0x6]; 3160 3161 u8 reserved_at_60[0x3]; 3162 u8 log_cq_size[0x5]; 3163 u8 uar_page[0x18]; 3164 3165 u8 reserved_at_80[0x4]; 3166 u8 cq_period[0xc]; 3167 u8 cq_max_count[0x10]; 3168 3169 u8 reserved_at_a0[0x18]; 3170 u8 c_eqn[0x8]; 3171 3172 u8 reserved_at_c0[0x3]; 3173 u8 log_page_size[0x5]; 3174 u8 reserved_at_c8[0x18]; 3175 3176 u8 reserved_at_e0[0x20]; 3177 3178 u8 reserved_at_100[0x8]; 3179 u8 last_notified_index[0x18]; 3180 3181 u8 reserved_at_120[0x8]; 3182 u8 last_solicit_index[0x18]; 3183 3184 u8 reserved_at_140[0x8]; 3185 u8 consumer_counter[0x18]; 3186 3187 u8 reserved_at_160[0x8]; 3188 u8 producer_counter[0x18]; 3189 3190 u8 reserved_at_180[0x40]; 3191 3192 u8 dbr_addr[0x40]; 3193 }; 3194 3195 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3196 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3197 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3198 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3199 u8 reserved_at_0[0x800]; 3200 }; 3201 3202 struct mlx5_ifc_query_adapter_param_block_bits { 3203 u8 reserved_at_0[0xc0]; 3204 3205 u8 reserved_at_c0[0x8]; 3206 u8 ieee_vendor_id[0x18]; 3207 3208 u8 reserved_at_e0[0x10]; 3209 u8 vsd_vendor_id[0x10]; 3210 3211 u8 vsd[208][0x8]; 3212 3213 u8 vsd_contd_psid[16][0x8]; 3214 }; 3215 3216 enum { 3217 MLX5_XRQC_STATE_GOOD = 0x0, 3218 MLX5_XRQC_STATE_ERROR = 0x1, 3219 }; 3220 3221 enum { 3222 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3223 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3224 }; 3225 3226 enum { 3227 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3228 }; 3229 3230 struct mlx5_ifc_tag_matching_topology_context_bits { 3231 u8 log_matching_list_sz[0x4]; 3232 u8 reserved_at_4[0xc]; 3233 u8 append_next_index[0x10]; 3234 3235 u8 sw_phase_cnt[0x10]; 3236 u8 hw_phase_cnt[0x10]; 3237 3238 u8 reserved_at_40[0x40]; 3239 }; 3240 3241 struct mlx5_ifc_xrqc_bits { 3242 u8 state[0x4]; 3243 u8 rlkey[0x1]; 3244 u8 reserved_at_5[0xf]; 3245 u8 topology[0x4]; 3246 u8 reserved_at_18[0x4]; 3247 u8 offload[0x4]; 3248 3249 u8 reserved_at_20[0x8]; 3250 u8 user_index[0x18]; 3251 3252 u8 reserved_at_40[0x8]; 3253 u8 cqn[0x18]; 3254 3255 u8 reserved_at_60[0xa0]; 3256 3257 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3258 3259 u8 reserved_at_180[0x280]; 3260 3261 struct mlx5_ifc_wq_bits wq; 3262 }; 3263 3264 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3265 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3266 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3267 u8 reserved_at_0[0x20]; 3268 }; 3269 3270 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3271 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3272 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3273 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3274 u8 reserved_at_0[0x20]; 3275 }; 3276 3277 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3278 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3279 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3280 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3281 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3282 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3283 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3284 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3285 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3286 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3287 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3288 u8 reserved_at_0[0x7c0]; 3289 }; 3290 3291 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3292 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3293 u8 reserved_at_0[0x7c0]; 3294 }; 3295 3296 union mlx5_ifc_event_auto_bits { 3297 struct mlx5_ifc_comp_event_bits comp_event; 3298 struct mlx5_ifc_dct_events_bits dct_events; 3299 struct mlx5_ifc_qp_events_bits qp_events; 3300 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3301 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3302 struct mlx5_ifc_cq_error_bits cq_error; 3303 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3304 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3305 struct mlx5_ifc_gpio_event_bits gpio_event; 3306 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3307 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3308 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3309 u8 reserved_at_0[0xe0]; 3310 }; 3311 3312 struct mlx5_ifc_health_buffer_bits { 3313 u8 reserved_at_0[0x100]; 3314 3315 u8 assert_existptr[0x20]; 3316 3317 u8 assert_callra[0x20]; 3318 3319 u8 reserved_at_140[0x40]; 3320 3321 u8 fw_version[0x20]; 3322 3323 u8 hw_id[0x20]; 3324 3325 u8 reserved_at_1c0[0x20]; 3326 3327 u8 irisc_index[0x8]; 3328 u8 synd[0x8]; 3329 u8 ext_synd[0x10]; 3330 }; 3331 3332 struct mlx5_ifc_register_loopback_control_bits { 3333 u8 no_lb[0x1]; 3334 u8 reserved_at_1[0x7]; 3335 u8 port[0x8]; 3336 u8 reserved_at_10[0x10]; 3337 3338 u8 reserved_at_20[0x60]; 3339 }; 3340 3341 struct mlx5_ifc_vport_tc_element_bits { 3342 u8 traffic_class[0x4]; 3343 u8 reserved_at_4[0xc]; 3344 u8 vport_number[0x10]; 3345 }; 3346 3347 struct mlx5_ifc_vport_element_bits { 3348 u8 reserved_at_0[0x10]; 3349 u8 vport_number[0x10]; 3350 }; 3351 3352 enum { 3353 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3354 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3355 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3356 }; 3357 3358 struct mlx5_ifc_tsar_element_bits { 3359 u8 reserved_at_0[0x8]; 3360 u8 tsar_type[0x8]; 3361 u8 reserved_at_10[0x10]; 3362 }; 3363 3364 enum { 3365 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3366 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3367 }; 3368 3369 struct mlx5_ifc_teardown_hca_out_bits { 3370 u8 status[0x8]; 3371 u8 reserved_at_8[0x18]; 3372 3373 u8 syndrome[0x20]; 3374 3375 u8 reserved_at_40[0x3f]; 3376 3377 u8 state[0x1]; 3378 }; 3379 3380 enum { 3381 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3382 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3383 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3384 }; 3385 3386 struct mlx5_ifc_teardown_hca_in_bits { 3387 u8 opcode[0x10]; 3388 u8 reserved_at_10[0x10]; 3389 3390 u8 reserved_at_20[0x10]; 3391 u8 op_mod[0x10]; 3392 3393 u8 reserved_at_40[0x10]; 3394 u8 profile[0x10]; 3395 3396 u8 reserved_at_60[0x20]; 3397 }; 3398 3399 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3400 u8 status[0x8]; 3401 u8 reserved_at_8[0x18]; 3402 3403 u8 syndrome[0x20]; 3404 3405 u8 reserved_at_40[0x40]; 3406 }; 3407 3408 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3409 u8 opcode[0x10]; 3410 u8 uid[0x10]; 3411 3412 u8 reserved_at_20[0x10]; 3413 u8 op_mod[0x10]; 3414 3415 u8 reserved_at_40[0x8]; 3416 u8 qpn[0x18]; 3417 3418 u8 reserved_at_60[0x20]; 3419 3420 u8 opt_param_mask[0x20]; 3421 3422 u8 reserved_at_a0[0x20]; 3423 3424 struct mlx5_ifc_qpc_bits qpc; 3425 3426 u8 reserved_at_800[0x80]; 3427 }; 3428 3429 struct mlx5_ifc_sqd2rts_qp_out_bits { 3430 u8 status[0x8]; 3431 u8 reserved_at_8[0x18]; 3432 3433 u8 syndrome[0x20]; 3434 3435 u8 reserved_at_40[0x40]; 3436 }; 3437 3438 struct mlx5_ifc_sqd2rts_qp_in_bits { 3439 u8 opcode[0x10]; 3440 u8 uid[0x10]; 3441 3442 u8 reserved_at_20[0x10]; 3443 u8 op_mod[0x10]; 3444 3445 u8 reserved_at_40[0x8]; 3446 u8 qpn[0x18]; 3447 3448 u8 reserved_at_60[0x20]; 3449 3450 u8 opt_param_mask[0x20]; 3451 3452 u8 reserved_at_a0[0x20]; 3453 3454 struct mlx5_ifc_qpc_bits qpc; 3455 3456 u8 reserved_at_800[0x80]; 3457 }; 3458 3459 struct mlx5_ifc_set_roce_address_out_bits { 3460 u8 status[0x8]; 3461 u8 reserved_at_8[0x18]; 3462 3463 u8 syndrome[0x20]; 3464 3465 u8 reserved_at_40[0x40]; 3466 }; 3467 3468 struct mlx5_ifc_set_roce_address_in_bits { 3469 u8 opcode[0x10]; 3470 u8 reserved_at_10[0x10]; 3471 3472 u8 reserved_at_20[0x10]; 3473 u8 op_mod[0x10]; 3474 3475 u8 roce_address_index[0x10]; 3476 u8 reserved_at_50[0xc]; 3477 u8 vhca_port_num[0x4]; 3478 3479 u8 reserved_at_60[0x20]; 3480 3481 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3482 }; 3483 3484 struct mlx5_ifc_set_mad_demux_out_bits { 3485 u8 status[0x8]; 3486 u8 reserved_at_8[0x18]; 3487 3488 u8 syndrome[0x20]; 3489 3490 u8 reserved_at_40[0x40]; 3491 }; 3492 3493 enum { 3494 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3495 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3496 }; 3497 3498 struct mlx5_ifc_set_mad_demux_in_bits { 3499 u8 opcode[0x10]; 3500 u8 reserved_at_10[0x10]; 3501 3502 u8 reserved_at_20[0x10]; 3503 u8 op_mod[0x10]; 3504 3505 u8 reserved_at_40[0x20]; 3506 3507 u8 reserved_at_60[0x6]; 3508 u8 demux_mode[0x2]; 3509 u8 reserved_at_68[0x18]; 3510 }; 3511 3512 struct mlx5_ifc_set_l2_table_entry_out_bits { 3513 u8 status[0x8]; 3514 u8 reserved_at_8[0x18]; 3515 3516 u8 syndrome[0x20]; 3517 3518 u8 reserved_at_40[0x40]; 3519 }; 3520 3521 struct mlx5_ifc_set_l2_table_entry_in_bits { 3522 u8 opcode[0x10]; 3523 u8 reserved_at_10[0x10]; 3524 3525 u8 reserved_at_20[0x10]; 3526 u8 op_mod[0x10]; 3527 3528 u8 reserved_at_40[0x60]; 3529 3530 u8 reserved_at_a0[0x8]; 3531 u8 table_index[0x18]; 3532 3533 u8 reserved_at_c0[0x20]; 3534 3535 u8 reserved_at_e0[0x13]; 3536 u8 vlan_valid[0x1]; 3537 u8 vlan[0xc]; 3538 3539 struct mlx5_ifc_mac_address_layout_bits mac_address; 3540 3541 u8 reserved_at_140[0xc0]; 3542 }; 3543 3544 struct mlx5_ifc_set_issi_out_bits { 3545 u8 status[0x8]; 3546 u8 reserved_at_8[0x18]; 3547 3548 u8 syndrome[0x20]; 3549 3550 u8 reserved_at_40[0x40]; 3551 }; 3552 3553 struct mlx5_ifc_set_issi_in_bits { 3554 u8 opcode[0x10]; 3555 u8 reserved_at_10[0x10]; 3556 3557 u8 reserved_at_20[0x10]; 3558 u8 op_mod[0x10]; 3559 3560 u8 reserved_at_40[0x10]; 3561 u8 current_issi[0x10]; 3562 3563 u8 reserved_at_60[0x20]; 3564 }; 3565 3566 struct mlx5_ifc_set_hca_cap_out_bits { 3567 u8 status[0x8]; 3568 u8 reserved_at_8[0x18]; 3569 3570 u8 syndrome[0x20]; 3571 3572 u8 reserved_at_40[0x40]; 3573 }; 3574 3575 struct mlx5_ifc_set_hca_cap_in_bits { 3576 u8 opcode[0x10]; 3577 u8 reserved_at_10[0x10]; 3578 3579 u8 reserved_at_20[0x10]; 3580 u8 op_mod[0x10]; 3581 3582 u8 reserved_at_40[0x40]; 3583 3584 union mlx5_ifc_hca_cap_union_bits capability; 3585 }; 3586 3587 enum { 3588 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3589 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3590 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3591 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3592 }; 3593 3594 struct mlx5_ifc_set_fte_out_bits { 3595 u8 status[0x8]; 3596 u8 reserved_at_8[0x18]; 3597 3598 u8 syndrome[0x20]; 3599 3600 u8 reserved_at_40[0x40]; 3601 }; 3602 3603 struct mlx5_ifc_set_fte_in_bits { 3604 u8 opcode[0x10]; 3605 u8 reserved_at_10[0x10]; 3606 3607 u8 reserved_at_20[0x10]; 3608 u8 op_mod[0x10]; 3609 3610 u8 other_vport[0x1]; 3611 u8 reserved_at_41[0xf]; 3612 u8 vport_number[0x10]; 3613 3614 u8 reserved_at_60[0x20]; 3615 3616 u8 table_type[0x8]; 3617 u8 reserved_at_88[0x18]; 3618 3619 u8 reserved_at_a0[0x8]; 3620 u8 table_id[0x18]; 3621 3622 u8 reserved_at_c0[0x18]; 3623 u8 modify_enable_mask[0x8]; 3624 3625 u8 reserved_at_e0[0x20]; 3626 3627 u8 flow_index[0x20]; 3628 3629 u8 reserved_at_120[0xe0]; 3630 3631 struct mlx5_ifc_flow_context_bits flow_context; 3632 }; 3633 3634 struct mlx5_ifc_rts2rts_qp_out_bits { 3635 u8 status[0x8]; 3636 u8 reserved_at_8[0x18]; 3637 3638 u8 syndrome[0x20]; 3639 3640 u8 reserved_at_40[0x40]; 3641 }; 3642 3643 struct mlx5_ifc_rts2rts_qp_in_bits { 3644 u8 opcode[0x10]; 3645 u8 uid[0x10]; 3646 3647 u8 reserved_at_20[0x10]; 3648 u8 op_mod[0x10]; 3649 3650 u8 reserved_at_40[0x8]; 3651 u8 qpn[0x18]; 3652 3653 u8 reserved_at_60[0x20]; 3654 3655 u8 opt_param_mask[0x20]; 3656 3657 u8 reserved_at_a0[0x20]; 3658 3659 struct mlx5_ifc_qpc_bits qpc; 3660 3661 u8 reserved_at_800[0x80]; 3662 }; 3663 3664 struct mlx5_ifc_rtr2rts_qp_out_bits { 3665 u8 status[0x8]; 3666 u8 reserved_at_8[0x18]; 3667 3668 u8 syndrome[0x20]; 3669 3670 u8 reserved_at_40[0x40]; 3671 }; 3672 3673 struct mlx5_ifc_rtr2rts_qp_in_bits { 3674 u8 opcode[0x10]; 3675 u8 uid[0x10]; 3676 3677 u8 reserved_at_20[0x10]; 3678 u8 op_mod[0x10]; 3679 3680 u8 reserved_at_40[0x8]; 3681 u8 qpn[0x18]; 3682 3683 u8 reserved_at_60[0x20]; 3684 3685 u8 opt_param_mask[0x20]; 3686 3687 u8 reserved_at_a0[0x20]; 3688 3689 struct mlx5_ifc_qpc_bits qpc; 3690 3691 u8 reserved_at_800[0x80]; 3692 }; 3693 3694 struct mlx5_ifc_rst2init_qp_out_bits { 3695 u8 status[0x8]; 3696 u8 reserved_at_8[0x18]; 3697 3698 u8 syndrome[0x20]; 3699 3700 u8 reserved_at_40[0x40]; 3701 }; 3702 3703 struct mlx5_ifc_rst2init_qp_in_bits { 3704 u8 opcode[0x10]; 3705 u8 uid[0x10]; 3706 3707 u8 reserved_at_20[0x10]; 3708 u8 op_mod[0x10]; 3709 3710 u8 reserved_at_40[0x8]; 3711 u8 qpn[0x18]; 3712 3713 u8 reserved_at_60[0x20]; 3714 3715 u8 opt_param_mask[0x20]; 3716 3717 u8 reserved_at_a0[0x20]; 3718 3719 struct mlx5_ifc_qpc_bits qpc; 3720 3721 u8 reserved_at_800[0x80]; 3722 }; 3723 3724 struct mlx5_ifc_query_xrq_out_bits { 3725 u8 status[0x8]; 3726 u8 reserved_at_8[0x18]; 3727 3728 u8 syndrome[0x20]; 3729 3730 u8 reserved_at_40[0x40]; 3731 3732 struct mlx5_ifc_xrqc_bits xrq_context; 3733 }; 3734 3735 struct mlx5_ifc_query_xrq_in_bits { 3736 u8 opcode[0x10]; 3737 u8 reserved_at_10[0x10]; 3738 3739 u8 reserved_at_20[0x10]; 3740 u8 op_mod[0x10]; 3741 3742 u8 reserved_at_40[0x8]; 3743 u8 xrqn[0x18]; 3744 3745 u8 reserved_at_60[0x20]; 3746 }; 3747 3748 struct mlx5_ifc_query_xrc_srq_out_bits { 3749 u8 status[0x8]; 3750 u8 reserved_at_8[0x18]; 3751 3752 u8 syndrome[0x20]; 3753 3754 u8 reserved_at_40[0x40]; 3755 3756 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3757 3758 u8 reserved_at_280[0x600]; 3759 3760 u8 pas[0][0x40]; 3761 }; 3762 3763 struct mlx5_ifc_query_xrc_srq_in_bits { 3764 u8 opcode[0x10]; 3765 u8 reserved_at_10[0x10]; 3766 3767 u8 reserved_at_20[0x10]; 3768 u8 op_mod[0x10]; 3769 3770 u8 reserved_at_40[0x8]; 3771 u8 xrc_srqn[0x18]; 3772 3773 u8 reserved_at_60[0x20]; 3774 }; 3775 3776 enum { 3777 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3778 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3779 }; 3780 3781 struct mlx5_ifc_query_vport_state_out_bits { 3782 u8 status[0x8]; 3783 u8 reserved_at_8[0x18]; 3784 3785 u8 syndrome[0x20]; 3786 3787 u8 reserved_at_40[0x20]; 3788 3789 u8 reserved_at_60[0x18]; 3790 u8 admin_state[0x4]; 3791 u8 state[0x4]; 3792 }; 3793 3794 enum { 3795 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3796 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3797 }; 3798 3799 struct mlx5_ifc_query_vport_state_in_bits { 3800 u8 opcode[0x10]; 3801 u8 reserved_at_10[0x10]; 3802 3803 u8 reserved_at_20[0x10]; 3804 u8 op_mod[0x10]; 3805 3806 u8 other_vport[0x1]; 3807 u8 reserved_at_41[0xf]; 3808 u8 vport_number[0x10]; 3809 3810 u8 reserved_at_60[0x20]; 3811 }; 3812 3813 struct mlx5_ifc_query_vnic_env_out_bits { 3814 u8 status[0x8]; 3815 u8 reserved_at_8[0x18]; 3816 3817 u8 syndrome[0x20]; 3818 3819 u8 reserved_at_40[0x40]; 3820 3821 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3822 }; 3823 3824 enum { 3825 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3826 }; 3827 3828 struct mlx5_ifc_query_vnic_env_in_bits { 3829 u8 opcode[0x10]; 3830 u8 reserved_at_10[0x10]; 3831 3832 u8 reserved_at_20[0x10]; 3833 u8 op_mod[0x10]; 3834 3835 u8 other_vport[0x1]; 3836 u8 reserved_at_41[0xf]; 3837 u8 vport_number[0x10]; 3838 3839 u8 reserved_at_60[0x20]; 3840 }; 3841 3842 struct mlx5_ifc_query_vport_counter_out_bits { 3843 u8 status[0x8]; 3844 u8 reserved_at_8[0x18]; 3845 3846 u8 syndrome[0x20]; 3847 3848 u8 reserved_at_40[0x40]; 3849 3850 struct mlx5_ifc_traffic_counter_bits received_errors; 3851 3852 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3853 3854 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3855 3856 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3857 3858 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3859 3860 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3861 3862 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3863 3864 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3865 3866 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3867 3868 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3869 3870 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3871 3872 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3873 3874 u8 reserved_at_680[0xa00]; 3875 }; 3876 3877 enum { 3878 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3879 }; 3880 3881 struct mlx5_ifc_query_vport_counter_in_bits { 3882 u8 opcode[0x10]; 3883 u8 reserved_at_10[0x10]; 3884 3885 u8 reserved_at_20[0x10]; 3886 u8 op_mod[0x10]; 3887 3888 u8 other_vport[0x1]; 3889 u8 reserved_at_41[0xb]; 3890 u8 port_num[0x4]; 3891 u8 vport_number[0x10]; 3892 3893 u8 reserved_at_60[0x60]; 3894 3895 u8 clear[0x1]; 3896 u8 reserved_at_c1[0x1f]; 3897 3898 u8 reserved_at_e0[0x20]; 3899 }; 3900 3901 struct mlx5_ifc_query_tis_out_bits { 3902 u8 status[0x8]; 3903 u8 reserved_at_8[0x18]; 3904 3905 u8 syndrome[0x20]; 3906 3907 u8 reserved_at_40[0x40]; 3908 3909 struct mlx5_ifc_tisc_bits tis_context; 3910 }; 3911 3912 struct mlx5_ifc_query_tis_in_bits { 3913 u8 opcode[0x10]; 3914 u8 reserved_at_10[0x10]; 3915 3916 u8 reserved_at_20[0x10]; 3917 u8 op_mod[0x10]; 3918 3919 u8 reserved_at_40[0x8]; 3920 u8 tisn[0x18]; 3921 3922 u8 reserved_at_60[0x20]; 3923 }; 3924 3925 struct mlx5_ifc_query_tir_out_bits { 3926 u8 status[0x8]; 3927 u8 reserved_at_8[0x18]; 3928 3929 u8 syndrome[0x20]; 3930 3931 u8 reserved_at_40[0xc0]; 3932 3933 struct mlx5_ifc_tirc_bits tir_context; 3934 }; 3935 3936 struct mlx5_ifc_query_tir_in_bits { 3937 u8 opcode[0x10]; 3938 u8 reserved_at_10[0x10]; 3939 3940 u8 reserved_at_20[0x10]; 3941 u8 op_mod[0x10]; 3942 3943 u8 reserved_at_40[0x8]; 3944 u8 tirn[0x18]; 3945 3946 u8 reserved_at_60[0x20]; 3947 }; 3948 3949 struct mlx5_ifc_query_srq_out_bits { 3950 u8 status[0x8]; 3951 u8 reserved_at_8[0x18]; 3952 3953 u8 syndrome[0x20]; 3954 3955 u8 reserved_at_40[0x40]; 3956 3957 struct mlx5_ifc_srqc_bits srq_context_entry; 3958 3959 u8 reserved_at_280[0x600]; 3960 3961 u8 pas[0][0x40]; 3962 }; 3963 3964 struct mlx5_ifc_query_srq_in_bits { 3965 u8 opcode[0x10]; 3966 u8 reserved_at_10[0x10]; 3967 3968 u8 reserved_at_20[0x10]; 3969 u8 op_mod[0x10]; 3970 3971 u8 reserved_at_40[0x8]; 3972 u8 srqn[0x18]; 3973 3974 u8 reserved_at_60[0x20]; 3975 }; 3976 3977 struct mlx5_ifc_query_sq_out_bits { 3978 u8 status[0x8]; 3979 u8 reserved_at_8[0x18]; 3980 3981 u8 syndrome[0x20]; 3982 3983 u8 reserved_at_40[0xc0]; 3984 3985 struct mlx5_ifc_sqc_bits sq_context; 3986 }; 3987 3988 struct mlx5_ifc_query_sq_in_bits { 3989 u8 opcode[0x10]; 3990 u8 reserved_at_10[0x10]; 3991 3992 u8 reserved_at_20[0x10]; 3993 u8 op_mod[0x10]; 3994 3995 u8 reserved_at_40[0x8]; 3996 u8 sqn[0x18]; 3997 3998 u8 reserved_at_60[0x20]; 3999 }; 4000 4001 struct mlx5_ifc_query_special_contexts_out_bits { 4002 u8 status[0x8]; 4003 u8 reserved_at_8[0x18]; 4004 4005 u8 syndrome[0x20]; 4006 4007 u8 dump_fill_mkey[0x20]; 4008 4009 u8 resd_lkey[0x20]; 4010 4011 u8 null_mkey[0x20]; 4012 4013 u8 reserved_at_a0[0x60]; 4014 }; 4015 4016 struct mlx5_ifc_query_special_contexts_in_bits { 4017 u8 opcode[0x10]; 4018 u8 reserved_at_10[0x10]; 4019 4020 u8 reserved_at_20[0x10]; 4021 u8 op_mod[0x10]; 4022 4023 u8 reserved_at_40[0x40]; 4024 }; 4025 4026 struct mlx5_ifc_query_scheduling_element_out_bits { 4027 u8 opcode[0x10]; 4028 u8 reserved_at_10[0x10]; 4029 4030 u8 reserved_at_20[0x10]; 4031 u8 op_mod[0x10]; 4032 4033 u8 reserved_at_40[0xc0]; 4034 4035 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4036 4037 u8 reserved_at_300[0x100]; 4038 }; 4039 4040 enum { 4041 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4042 }; 4043 4044 struct mlx5_ifc_query_scheduling_element_in_bits { 4045 u8 opcode[0x10]; 4046 u8 reserved_at_10[0x10]; 4047 4048 u8 reserved_at_20[0x10]; 4049 u8 op_mod[0x10]; 4050 4051 u8 scheduling_hierarchy[0x8]; 4052 u8 reserved_at_48[0x18]; 4053 4054 u8 scheduling_element_id[0x20]; 4055 4056 u8 reserved_at_80[0x180]; 4057 }; 4058 4059 struct mlx5_ifc_query_rqt_out_bits { 4060 u8 status[0x8]; 4061 u8 reserved_at_8[0x18]; 4062 4063 u8 syndrome[0x20]; 4064 4065 u8 reserved_at_40[0xc0]; 4066 4067 struct mlx5_ifc_rqtc_bits rqt_context; 4068 }; 4069 4070 struct mlx5_ifc_query_rqt_in_bits { 4071 u8 opcode[0x10]; 4072 u8 reserved_at_10[0x10]; 4073 4074 u8 reserved_at_20[0x10]; 4075 u8 op_mod[0x10]; 4076 4077 u8 reserved_at_40[0x8]; 4078 u8 rqtn[0x18]; 4079 4080 u8 reserved_at_60[0x20]; 4081 }; 4082 4083 struct mlx5_ifc_query_rq_out_bits { 4084 u8 status[0x8]; 4085 u8 reserved_at_8[0x18]; 4086 4087 u8 syndrome[0x20]; 4088 4089 u8 reserved_at_40[0xc0]; 4090 4091 struct mlx5_ifc_rqc_bits rq_context; 4092 }; 4093 4094 struct mlx5_ifc_query_rq_in_bits { 4095 u8 opcode[0x10]; 4096 u8 reserved_at_10[0x10]; 4097 4098 u8 reserved_at_20[0x10]; 4099 u8 op_mod[0x10]; 4100 4101 u8 reserved_at_40[0x8]; 4102 u8 rqn[0x18]; 4103 4104 u8 reserved_at_60[0x20]; 4105 }; 4106 4107 struct mlx5_ifc_query_roce_address_out_bits { 4108 u8 status[0x8]; 4109 u8 reserved_at_8[0x18]; 4110 4111 u8 syndrome[0x20]; 4112 4113 u8 reserved_at_40[0x40]; 4114 4115 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4116 }; 4117 4118 struct mlx5_ifc_query_roce_address_in_bits { 4119 u8 opcode[0x10]; 4120 u8 reserved_at_10[0x10]; 4121 4122 u8 reserved_at_20[0x10]; 4123 u8 op_mod[0x10]; 4124 4125 u8 roce_address_index[0x10]; 4126 u8 reserved_at_50[0xc]; 4127 u8 vhca_port_num[0x4]; 4128 4129 u8 reserved_at_60[0x20]; 4130 }; 4131 4132 struct mlx5_ifc_query_rmp_out_bits { 4133 u8 status[0x8]; 4134 u8 reserved_at_8[0x18]; 4135 4136 u8 syndrome[0x20]; 4137 4138 u8 reserved_at_40[0xc0]; 4139 4140 struct mlx5_ifc_rmpc_bits rmp_context; 4141 }; 4142 4143 struct mlx5_ifc_query_rmp_in_bits { 4144 u8 opcode[0x10]; 4145 u8 reserved_at_10[0x10]; 4146 4147 u8 reserved_at_20[0x10]; 4148 u8 op_mod[0x10]; 4149 4150 u8 reserved_at_40[0x8]; 4151 u8 rmpn[0x18]; 4152 4153 u8 reserved_at_60[0x20]; 4154 }; 4155 4156 struct mlx5_ifc_query_qp_out_bits { 4157 u8 status[0x8]; 4158 u8 reserved_at_8[0x18]; 4159 4160 u8 syndrome[0x20]; 4161 4162 u8 reserved_at_40[0x40]; 4163 4164 u8 opt_param_mask[0x20]; 4165 4166 u8 reserved_at_a0[0x20]; 4167 4168 struct mlx5_ifc_qpc_bits qpc; 4169 4170 u8 reserved_at_800[0x80]; 4171 4172 u8 pas[0][0x40]; 4173 }; 4174 4175 struct mlx5_ifc_query_qp_in_bits { 4176 u8 opcode[0x10]; 4177 u8 reserved_at_10[0x10]; 4178 4179 u8 reserved_at_20[0x10]; 4180 u8 op_mod[0x10]; 4181 4182 u8 reserved_at_40[0x8]; 4183 u8 qpn[0x18]; 4184 4185 u8 reserved_at_60[0x20]; 4186 }; 4187 4188 struct mlx5_ifc_query_q_counter_out_bits { 4189 u8 status[0x8]; 4190 u8 reserved_at_8[0x18]; 4191 4192 u8 syndrome[0x20]; 4193 4194 u8 reserved_at_40[0x40]; 4195 4196 u8 rx_write_requests[0x20]; 4197 4198 u8 reserved_at_a0[0x20]; 4199 4200 u8 rx_read_requests[0x20]; 4201 4202 u8 reserved_at_e0[0x20]; 4203 4204 u8 rx_atomic_requests[0x20]; 4205 4206 u8 reserved_at_120[0x20]; 4207 4208 u8 rx_dct_connect[0x20]; 4209 4210 u8 reserved_at_160[0x20]; 4211 4212 u8 out_of_buffer[0x20]; 4213 4214 u8 reserved_at_1a0[0x20]; 4215 4216 u8 out_of_sequence[0x20]; 4217 4218 u8 reserved_at_1e0[0x20]; 4219 4220 u8 duplicate_request[0x20]; 4221 4222 u8 reserved_at_220[0x20]; 4223 4224 u8 rnr_nak_retry_err[0x20]; 4225 4226 u8 reserved_at_260[0x20]; 4227 4228 u8 packet_seq_err[0x20]; 4229 4230 u8 reserved_at_2a0[0x20]; 4231 4232 u8 implied_nak_seq_err[0x20]; 4233 4234 u8 reserved_at_2e0[0x20]; 4235 4236 u8 local_ack_timeout_err[0x20]; 4237 4238 u8 reserved_at_320[0xa0]; 4239 4240 u8 resp_local_length_error[0x20]; 4241 4242 u8 req_local_length_error[0x20]; 4243 4244 u8 resp_local_qp_error[0x20]; 4245 4246 u8 local_operation_error[0x20]; 4247 4248 u8 resp_local_protection[0x20]; 4249 4250 u8 req_local_protection[0x20]; 4251 4252 u8 resp_cqe_error[0x20]; 4253 4254 u8 req_cqe_error[0x20]; 4255 4256 u8 req_mw_binding[0x20]; 4257 4258 u8 req_bad_response[0x20]; 4259 4260 u8 req_remote_invalid_request[0x20]; 4261 4262 u8 resp_remote_invalid_request[0x20]; 4263 4264 u8 req_remote_access_errors[0x20]; 4265 4266 u8 resp_remote_access_errors[0x20]; 4267 4268 u8 req_remote_operation_errors[0x20]; 4269 4270 u8 req_transport_retries_exceeded[0x20]; 4271 4272 u8 cq_overflow[0x20]; 4273 4274 u8 resp_cqe_flush_error[0x20]; 4275 4276 u8 req_cqe_flush_error[0x20]; 4277 4278 u8 reserved_at_620[0x1e0]; 4279 }; 4280 4281 struct mlx5_ifc_query_q_counter_in_bits { 4282 u8 opcode[0x10]; 4283 u8 reserved_at_10[0x10]; 4284 4285 u8 reserved_at_20[0x10]; 4286 u8 op_mod[0x10]; 4287 4288 u8 reserved_at_40[0x80]; 4289 4290 u8 clear[0x1]; 4291 u8 reserved_at_c1[0x1f]; 4292 4293 u8 reserved_at_e0[0x18]; 4294 u8 counter_set_id[0x8]; 4295 }; 4296 4297 struct mlx5_ifc_query_pages_out_bits { 4298 u8 status[0x8]; 4299 u8 reserved_at_8[0x18]; 4300 4301 u8 syndrome[0x20]; 4302 4303 u8 reserved_at_40[0x10]; 4304 u8 function_id[0x10]; 4305 4306 u8 num_pages[0x20]; 4307 }; 4308 4309 enum { 4310 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4311 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4312 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4313 }; 4314 4315 struct mlx5_ifc_query_pages_in_bits { 4316 u8 opcode[0x10]; 4317 u8 reserved_at_10[0x10]; 4318 4319 u8 reserved_at_20[0x10]; 4320 u8 op_mod[0x10]; 4321 4322 u8 reserved_at_40[0x10]; 4323 u8 function_id[0x10]; 4324 4325 u8 reserved_at_60[0x20]; 4326 }; 4327 4328 struct mlx5_ifc_query_nic_vport_context_out_bits { 4329 u8 status[0x8]; 4330 u8 reserved_at_8[0x18]; 4331 4332 u8 syndrome[0x20]; 4333 4334 u8 reserved_at_40[0x40]; 4335 4336 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4337 }; 4338 4339 struct mlx5_ifc_query_nic_vport_context_in_bits { 4340 u8 opcode[0x10]; 4341 u8 reserved_at_10[0x10]; 4342 4343 u8 reserved_at_20[0x10]; 4344 u8 op_mod[0x10]; 4345 4346 u8 other_vport[0x1]; 4347 u8 reserved_at_41[0xf]; 4348 u8 vport_number[0x10]; 4349 4350 u8 reserved_at_60[0x5]; 4351 u8 allowed_list_type[0x3]; 4352 u8 reserved_at_68[0x18]; 4353 }; 4354 4355 struct mlx5_ifc_query_mkey_out_bits { 4356 u8 status[0x8]; 4357 u8 reserved_at_8[0x18]; 4358 4359 u8 syndrome[0x20]; 4360 4361 u8 reserved_at_40[0x40]; 4362 4363 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4364 4365 u8 reserved_at_280[0x600]; 4366 4367 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4368 4369 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4370 }; 4371 4372 struct mlx5_ifc_query_mkey_in_bits { 4373 u8 opcode[0x10]; 4374 u8 reserved_at_10[0x10]; 4375 4376 u8 reserved_at_20[0x10]; 4377 u8 op_mod[0x10]; 4378 4379 u8 reserved_at_40[0x8]; 4380 u8 mkey_index[0x18]; 4381 4382 u8 pg_access[0x1]; 4383 u8 reserved_at_61[0x1f]; 4384 }; 4385 4386 struct mlx5_ifc_query_mad_demux_out_bits { 4387 u8 status[0x8]; 4388 u8 reserved_at_8[0x18]; 4389 4390 u8 syndrome[0x20]; 4391 4392 u8 reserved_at_40[0x40]; 4393 4394 u8 mad_dumux_parameters_block[0x20]; 4395 }; 4396 4397 struct mlx5_ifc_query_mad_demux_in_bits { 4398 u8 opcode[0x10]; 4399 u8 reserved_at_10[0x10]; 4400 4401 u8 reserved_at_20[0x10]; 4402 u8 op_mod[0x10]; 4403 4404 u8 reserved_at_40[0x40]; 4405 }; 4406 4407 struct mlx5_ifc_query_l2_table_entry_out_bits { 4408 u8 status[0x8]; 4409 u8 reserved_at_8[0x18]; 4410 4411 u8 syndrome[0x20]; 4412 4413 u8 reserved_at_40[0xa0]; 4414 4415 u8 reserved_at_e0[0x13]; 4416 u8 vlan_valid[0x1]; 4417 u8 vlan[0xc]; 4418 4419 struct mlx5_ifc_mac_address_layout_bits mac_address; 4420 4421 u8 reserved_at_140[0xc0]; 4422 }; 4423 4424 struct mlx5_ifc_query_l2_table_entry_in_bits { 4425 u8 opcode[0x10]; 4426 u8 reserved_at_10[0x10]; 4427 4428 u8 reserved_at_20[0x10]; 4429 u8 op_mod[0x10]; 4430 4431 u8 reserved_at_40[0x60]; 4432 4433 u8 reserved_at_a0[0x8]; 4434 u8 table_index[0x18]; 4435 4436 u8 reserved_at_c0[0x140]; 4437 }; 4438 4439 struct mlx5_ifc_query_issi_out_bits { 4440 u8 status[0x8]; 4441 u8 reserved_at_8[0x18]; 4442 4443 u8 syndrome[0x20]; 4444 4445 u8 reserved_at_40[0x10]; 4446 u8 current_issi[0x10]; 4447 4448 u8 reserved_at_60[0xa0]; 4449 4450 u8 reserved_at_100[76][0x8]; 4451 u8 supported_issi_dw0[0x20]; 4452 }; 4453 4454 struct mlx5_ifc_query_issi_in_bits { 4455 u8 opcode[0x10]; 4456 u8 reserved_at_10[0x10]; 4457 4458 u8 reserved_at_20[0x10]; 4459 u8 op_mod[0x10]; 4460 4461 u8 reserved_at_40[0x40]; 4462 }; 4463 4464 struct mlx5_ifc_set_driver_version_out_bits { 4465 u8 status[0x8]; 4466 u8 reserved_0[0x18]; 4467 4468 u8 syndrome[0x20]; 4469 u8 reserved_1[0x40]; 4470 }; 4471 4472 struct mlx5_ifc_set_driver_version_in_bits { 4473 u8 opcode[0x10]; 4474 u8 reserved_0[0x10]; 4475 4476 u8 reserved_1[0x10]; 4477 u8 op_mod[0x10]; 4478 4479 u8 reserved_2[0x40]; 4480 u8 driver_version[64][0x8]; 4481 }; 4482 4483 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4484 u8 status[0x8]; 4485 u8 reserved_at_8[0x18]; 4486 4487 u8 syndrome[0x20]; 4488 4489 u8 reserved_at_40[0x40]; 4490 4491 struct mlx5_ifc_pkey_bits pkey[0]; 4492 }; 4493 4494 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4495 u8 opcode[0x10]; 4496 u8 reserved_at_10[0x10]; 4497 4498 u8 reserved_at_20[0x10]; 4499 u8 op_mod[0x10]; 4500 4501 u8 other_vport[0x1]; 4502 u8 reserved_at_41[0xb]; 4503 u8 port_num[0x4]; 4504 u8 vport_number[0x10]; 4505 4506 u8 reserved_at_60[0x10]; 4507 u8 pkey_index[0x10]; 4508 }; 4509 4510 enum { 4511 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4512 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4513 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4514 }; 4515 4516 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4517 u8 status[0x8]; 4518 u8 reserved_at_8[0x18]; 4519 4520 u8 syndrome[0x20]; 4521 4522 u8 reserved_at_40[0x20]; 4523 4524 u8 gids_num[0x10]; 4525 u8 reserved_at_70[0x10]; 4526 4527 struct mlx5_ifc_array128_auto_bits gid[0]; 4528 }; 4529 4530 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4531 u8 opcode[0x10]; 4532 u8 reserved_at_10[0x10]; 4533 4534 u8 reserved_at_20[0x10]; 4535 u8 op_mod[0x10]; 4536 4537 u8 other_vport[0x1]; 4538 u8 reserved_at_41[0xb]; 4539 u8 port_num[0x4]; 4540 u8 vport_number[0x10]; 4541 4542 u8 reserved_at_60[0x10]; 4543 u8 gid_index[0x10]; 4544 }; 4545 4546 struct mlx5_ifc_query_hca_vport_context_out_bits { 4547 u8 status[0x8]; 4548 u8 reserved_at_8[0x18]; 4549 4550 u8 syndrome[0x20]; 4551 4552 u8 reserved_at_40[0x40]; 4553 4554 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4555 }; 4556 4557 struct mlx5_ifc_query_hca_vport_context_in_bits { 4558 u8 opcode[0x10]; 4559 u8 reserved_at_10[0x10]; 4560 4561 u8 reserved_at_20[0x10]; 4562 u8 op_mod[0x10]; 4563 4564 u8 other_vport[0x1]; 4565 u8 reserved_at_41[0xb]; 4566 u8 port_num[0x4]; 4567 u8 vport_number[0x10]; 4568 4569 u8 reserved_at_60[0x20]; 4570 }; 4571 4572 struct mlx5_ifc_query_hca_cap_out_bits { 4573 u8 status[0x8]; 4574 u8 reserved_at_8[0x18]; 4575 4576 u8 syndrome[0x20]; 4577 4578 u8 reserved_at_40[0x40]; 4579 4580 union mlx5_ifc_hca_cap_union_bits capability; 4581 }; 4582 4583 struct mlx5_ifc_query_hca_cap_in_bits { 4584 u8 opcode[0x10]; 4585 u8 reserved_at_10[0x10]; 4586 4587 u8 reserved_at_20[0x10]; 4588 u8 op_mod[0x10]; 4589 4590 u8 reserved_at_40[0x40]; 4591 }; 4592 4593 struct mlx5_ifc_query_flow_table_out_bits { 4594 u8 status[0x8]; 4595 u8 reserved_at_8[0x18]; 4596 4597 u8 syndrome[0x20]; 4598 4599 u8 reserved_at_40[0x80]; 4600 4601 u8 reserved_at_c0[0x8]; 4602 u8 level[0x8]; 4603 u8 reserved_at_d0[0x8]; 4604 u8 log_size[0x8]; 4605 4606 u8 reserved_at_e0[0x120]; 4607 }; 4608 4609 struct mlx5_ifc_query_flow_table_in_bits { 4610 u8 opcode[0x10]; 4611 u8 reserved_at_10[0x10]; 4612 4613 u8 reserved_at_20[0x10]; 4614 u8 op_mod[0x10]; 4615 4616 u8 reserved_at_40[0x40]; 4617 4618 u8 table_type[0x8]; 4619 u8 reserved_at_88[0x18]; 4620 4621 u8 reserved_at_a0[0x8]; 4622 u8 table_id[0x18]; 4623 4624 u8 reserved_at_c0[0x140]; 4625 }; 4626 4627 struct mlx5_ifc_query_fte_out_bits { 4628 u8 status[0x8]; 4629 u8 reserved_at_8[0x18]; 4630 4631 u8 syndrome[0x20]; 4632 4633 u8 reserved_at_40[0x1c0]; 4634 4635 struct mlx5_ifc_flow_context_bits flow_context; 4636 }; 4637 4638 struct mlx5_ifc_query_fte_in_bits { 4639 u8 opcode[0x10]; 4640 u8 reserved_at_10[0x10]; 4641 4642 u8 reserved_at_20[0x10]; 4643 u8 op_mod[0x10]; 4644 4645 u8 reserved_at_40[0x40]; 4646 4647 u8 table_type[0x8]; 4648 u8 reserved_at_88[0x18]; 4649 4650 u8 reserved_at_a0[0x8]; 4651 u8 table_id[0x18]; 4652 4653 u8 reserved_at_c0[0x40]; 4654 4655 u8 flow_index[0x20]; 4656 4657 u8 reserved_at_120[0xe0]; 4658 }; 4659 4660 enum { 4661 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4662 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4663 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4664 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3, 4665 }; 4666 4667 struct mlx5_ifc_query_flow_group_out_bits { 4668 u8 status[0x8]; 4669 u8 reserved_at_8[0x18]; 4670 4671 u8 syndrome[0x20]; 4672 4673 u8 reserved_at_40[0xa0]; 4674 4675 u8 start_flow_index[0x20]; 4676 4677 u8 reserved_at_100[0x20]; 4678 4679 u8 end_flow_index[0x20]; 4680 4681 u8 reserved_at_140[0xa0]; 4682 4683 u8 reserved_at_1e0[0x18]; 4684 u8 match_criteria_enable[0x8]; 4685 4686 struct mlx5_ifc_fte_match_param_bits match_criteria; 4687 4688 u8 reserved_at_1200[0xe00]; 4689 }; 4690 4691 struct mlx5_ifc_query_flow_group_in_bits { 4692 u8 opcode[0x10]; 4693 u8 reserved_at_10[0x10]; 4694 4695 u8 reserved_at_20[0x10]; 4696 u8 op_mod[0x10]; 4697 4698 u8 reserved_at_40[0x40]; 4699 4700 u8 table_type[0x8]; 4701 u8 reserved_at_88[0x18]; 4702 4703 u8 reserved_at_a0[0x8]; 4704 u8 table_id[0x18]; 4705 4706 u8 group_id[0x20]; 4707 4708 u8 reserved_at_e0[0x120]; 4709 }; 4710 4711 struct mlx5_ifc_query_flow_counter_out_bits { 4712 u8 status[0x8]; 4713 u8 reserved_at_8[0x18]; 4714 4715 u8 syndrome[0x20]; 4716 4717 u8 reserved_at_40[0x40]; 4718 4719 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4720 }; 4721 4722 struct mlx5_ifc_query_flow_counter_in_bits { 4723 u8 opcode[0x10]; 4724 u8 reserved_at_10[0x10]; 4725 4726 u8 reserved_at_20[0x10]; 4727 u8 op_mod[0x10]; 4728 4729 u8 reserved_at_40[0x80]; 4730 4731 u8 clear[0x1]; 4732 u8 reserved_at_c1[0xf]; 4733 u8 num_of_counters[0x10]; 4734 4735 u8 flow_counter_id[0x20]; 4736 }; 4737 4738 struct mlx5_ifc_query_esw_vport_context_out_bits { 4739 u8 status[0x8]; 4740 u8 reserved_at_8[0x18]; 4741 4742 u8 syndrome[0x20]; 4743 4744 u8 reserved_at_40[0x40]; 4745 4746 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4747 }; 4748 4749 struct mlx5_ifc_query_esw_vport_context_in_bits { 4750 u8 opcode[0x10]; 4751 u8 reserved_at_10[0x10]; 4752 4753 u8 reserved_at_20[0x10]; 4754 u8 op_mod[0x10]; 4755 4756 u8 other_vport[0x1]; 4757 u8 reserved_at_41[0xf]; 4758 u8 vport_number[0x10]; 4759 4760 u8 reserved_at_60[0x20]; 4761 }; 4762 4763 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4764 u8 status[0x8]; 4765 u8 reserved_at_8[0x18]; 4766 4767 u8 syndrome[0x20]; 4768 4769 u8 reserved_at_40[0x40]; 4770 }; 4771 4772 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4773 u8 reserved_at_0[0x1c]; 4774 u8 vport_cvlan_insert[0x1]; 4775 u8 vport_svlan_insert[0x1]; 4776 u8 vport_cvlan_strip[0x1]; 4777 u8 vport_svlan_strip[0x1]; 4778 }; 4779 4780 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4781 u8 opcode[0x10]; 4782 u8 reserved_at_10[0x10]; 4783 4784 u8 reserved_at_20[0x10]; 4785 u8 op_mod[0x10]; 4786 4787 u8 other_vport[0x1]; 4788 u8 reserved_at_41[0xf]; 4789 u8 vport_number[0x10]; 4790 4791 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4792 4793 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4794 }; 4795 4796 struct mlx5_ifc_query_eq_out_bits { 4797 u8 status[0x8]; 4798 u8 reserved_at_8[0x18]; 4799 4800 u8 syndrome[0x20]; 4801 4802 u8 reserved_at_40[0x40]; 4803 4804 struct mlx5_ifc_eqc_bits eq_context_entry; 4805 4806 u8 reserved_at_280[0x40]; 4807 4808 u8 event_bitmask[0x40]; 4809 4810 u8 reserved_at_300[0x580]; 4811 4812 u8 pas[0][0x40]; 4813 }; 4814 4815 struct mlx5_ifc_query_eq_in_bits { 4816 u8 opcode[0x10]; 4817 u8 reserved_at_10[0x10]; 4818 4819 u8 reserved_at_20[0x10]; 4820 u8 op_mod[0x10]; 4821 4822 u8 reserved_at_40[0x18]; 4823 u8 eq_number[0x8]; 4824 4825 u8 reserved_at_60[0x20]; 4826 }; 4827 4828 struct mlx5_ifc_packet_reformat_context_in_bits { 4829 u8 reserved_at_0[0x5]; 4830 u8 reformat_type[0x3]; 4831 u8 reserved_at_8[0xe]; 4832 u8 reformat_data_size[0xa]; 4833 4834 u8 reserved_at_20[0x10]; 4835 u8 reformat_data[2][0x8]; 4836 4837 u8 more_reformat_data[0][0x8]; 4838 }; 4839 4840 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4841 u8 status[0x8]; 4842 u8 reserved_at_8[0x18]; 4843 4844 u8 syndrome[0x20]; 4845 4846 u8 reserved_at_40[0xa0]; 4847 4848 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4849 }; 4850 4851 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4852 u8 opcode[0x10]; 4853 u8 reserved_at_10[0x10]; 4854 4855 u8 reserved_at_20[0x10]; 4856 u8 op_mod[0x10]; 4857 4858 u8 packet_reformat_id[0x20]; 4859 4860 u8 reserved_at_60[0xa0]; 4861 }; 4862 4863 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 4864 u8 status[0x8]; 4865 u8 reserved_at_8[0x18]; 4866 4867 u8 syndrome[0x20]; 4868 4869 u8 packet_reformat_id[0x20]; 4870 4871 u8 reserved_at_60[0x20]; 4872 }; 4873 4874 enum { 4875 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 4876 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 4877 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 4878 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 4879 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 4880 }; 4881 4882 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 4883 u8 opcode[0x10]; 4884 u8 reserved_at_10[0x10]; 4885 4886 u8 reserved_at_20[0x10]; 4887 u8 op_mod[0x10]; 4888 4889 u8 reserved_at_40[0xa0]; 4890 4891 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 4892 }; 4893 4894 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 4895 u8 status[0x8]; 4896 u8 reserved_at_8[0x18]; 4897 4898 u8 syndrome[0x20]; 4899 4900 u8 reserved_at_40[0x40]; 4901 }; 4902 4903 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 4904 u8 opcode[0x10]; 4905 u8 reserved_at_10[0x10]; 4906 4907 u8 reserved_20[0x10]; 4908 u8 op_mod[0x10]; 4909 4910 u8 packet_reformat_id[0x20]; 4911 4912 u8 reserved_60[0x20]; 4913 }; 4914 4915 struct mlx5_ifc_set_action_in_bits { 4916 u8 action_type[0x4]; 4917 u8 field[0xc]; 4918 u8 reserved_at_10[0x3]; 4919 u8 offset[0x5]; 4920 u8 reserved_at_18[0x3]; 4921 u8 length[0x5]; 4922 4923 u8 data[0x20]; 4924 }; 4925 4926 struct mlx5_ifc_add_action_in_bits { 4927 u8 action_type[0x4]; 4928 u8 field[0xc]; 4929 u8 reserved_at_10[0x10]; 4930 4931 u8 data[0x20]; 4932 }; 4933 4934 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4935 struct mlx5_ifc_set_action_in_bits set_action_in; 4936 struct mlx5_ifc_add_action_in_bits add_action_in; 4937 u8 reserved_at_0[0x40]; 4938 }; 4939 4940 enum { 4941 MLX5_ACTION_TYPE_SET = 0x1, 4942 MLX5_ACTION_TYPE_ADD = 0x2, 4943 }; 4944 4945 enum { 4946 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4947 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4948 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4949 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4950 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4951 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4952 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4953 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4954 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4955 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4956 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4957 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4958 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4959 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4960 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4961 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4962 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4963 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4964 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4965 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4966 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4967 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4968 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4969 }; 4970 4971 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4972 u8 status[0x8]; 4973 u8 reserved_at_8[0x18]; 4974 4975 u8 syndrome[0x20]; 4976 4977 u8 modify_header_id[0x20]; 4978 4979 u8 reserved_at_60[0x20]; 4980 }; 4981 4982 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4983 u8 opcode[0x10]; 4984 u8 reserved_at_10[0x10]; 4985 4986 u8 reserved_at_20[0x10]; 4987 u8 op_mod[0x10]; 4988 4989 u8 reserved_at_40[0x20]; 4990 4991 u8 table_type[0x8]; 4992 u8 reserved_at_68[0x10]; 4993 u8 num_of_actions[0x8]; 4994 4995 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4996 }; 4997 4998 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4999 u8 status[0x8]; 5000 u8 reserved_at_8[0x18]; 5001 5002 u8 syndrome[0x20]; 5003 5004 u8 reserved_at_40[0x40]; 5005 }; 5006 5007 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5008 u8 opcode[0x10]; 5009 u8 reserved_at_10[0x10]; 5010 5011 u8 reserved_at_20[0x10]; 5012 u8 op_mod[0x10]; 5013 5014 u8 modify_header_id[0x20]; 5015 5016 u8 reserved_at_60[0x20]; 5017 }; 5018 5019 struct mlx5_ifc_query_dct_out_bits { 5020 u8 status[0x8]; 5021 u8 reserved_at_8[0x18]; 5022 5023 u8 syndrome[0x20]; 5024 5025 u8 reserved_at_40[0x40]; 5026 5027 struct mlx5_ifc_dctc_bits dct_context_entry; 5028 5029 u8 reserved_at_280[0x180]; 5030 }; 5031 5032 struct mlx5_ifc_query_dct_in_bits { 5033 u8 opcode[0x10]; 5034 u8 reserved_at_10[0x10]; 5035 5036 u8 reserved_at_20[0x10]; 5037 u8 op_mod[0x10]; 5038 5039 u8 reserved_at_40[0x8]; 5040 u8 dctn[0x18]; 5041 5042 u8 reserved_at_60[0x20]; 5043 }; 5044 5045 struct mlx5_ifc_query_cq_out_bits { 5046 u8 status[0x8]; 5047 u8 reserved_at_8[0x18]; 5048 5049 u8 syndrome[0x20]; 5050 5051 u8 reserved_at_40[0x40]; 5052 5053 struct mlx5_ifc_cqc_bits cq_context; 5054 5055 u8 reserved_at_280[0x600]; 5056 5057 u8 pas[0][0x40]; 5058 }; 5059 5060 struct mlx5_ifc_query_cq_in_bits { 5061 u8 opcode[0x10]; 5062 u8 reserved_at_10[0x10]; 5063 5064 u8 reserved_at_20[0x10]; 5065 u8 op_mod[0x10]; 5066 5067 u8 reserved_at_40[0x8]; 5068 u8 cqn[0x18]; 5069 5070 u8 reserved_at_60[0x20]; 5071 }; 5072 5073 struct mlx5_ifc_query_cong_status_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_at_8[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 reserved_at_40[0x20]; 5080 5081 u8 enable[0x1]; 5082 u8 tag_enable[0x1]; 5083 u8 reserved_at_62[0x1e]; 5084 }; 5085 5086 struct mlx5_ifc_query_cong_status_in_bits { 5087 u8 opcode[0x10]; 5088 u8 reserved_at_10[0x10]; 5089 5090 u8 reserved_at_20[0x10]; 5091 u8 op_mod[0x10]; 5092 5093 u8 reserved_at_40[0x18]; 5094 u8 priority[0x4]; 5095 u8 cong_protocol[0x4]; 5096 5097 u8 reserved_at_60[0x20]; 5098 }; 5099 5100 struct mlx5_ifc_query_cong_statistics_out_bits { 5101 u8 status[0x8]; 5102 u8 reserved_at_8[0x18]; 5103 5104 u8 syndrome[0x20]; 5105 5106 u8 reserved_at_40[0x40]; 5107 5108 u8 rp_cur_flows[0x20]; 5109 5110 u8 sum_flows[0x20]; 5111 5112 u8 rp_cnp_ignored_high[0x20]; 5113 5114 u8 rp_cnp_ignored_low[0x20]; 5115 5116 u8 rp_cnp_handled_high[0x20]; 5117 5118 u8 rp_cnp_handled_low[0x20]; 5119 5120 u8 reserved_at_140[0x100]; 5121 5122 u8 time_stamp_high[0x20]; 5123 5124 u8 time_stamp_low[0x20]; 5125 5126 u8 accumulators_period[0x20]; 5127 5128 u8 np_ecn_marked_roce_packets_high[0x20]; 5129 5130 u8 np_ecn_marked_roce_packets_low[0x20]; 5131 5132 u8 np_cnp_sent_high[0x20]; 5133 5134 u8 np_cnp_sent_low[0x20]; 5135 5136 u8 reserved_at_320[0x560]; 5137 }; 5138 5139 struct mlx5_ifc_query_cong_statistics_in_bits { 5140 u8 opcode[0x10]; 5141 u8 reserved_at_10[0x10]; 5142 5143 u8 reserved_at_20[0x10]; 5144 u8 op_mod[0x10]; 5145 5146 u8 clear[0x1]; 5147 u8 reserved_at_41[0x1f]; 5148 5149 u8 reserved_at_60[0x20]; 5150 }; 5151 5152 struct mlx5_ifc_query_cong_params_out_bits { 5153 u8 status[0x8]; 5154 u8 reserved_at_8[0x18]; 5155 5156 u8 syndrome[0x20]; 5157 5158 u8 reserved_at_40[0x40]; 5159 5160 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5161 }; 5162 5163 struct mlx5_ifc_query_cong_params_in_bits { 5164 u8 opcode[0x10]; 5165 u8 reserved_at_10[0x10]; 5166 5167 u8 reserved_at_20[0x10]; 5168 u8 op_mod[0x10]; 5169 5170 u8 reserved_at_40[0x1c]; 5171 u8 cong_protocol[0x4]; 5172 5173 u8 reserved_at_60[0x20]; 5174 }; 5175 5176 struct mlx5_ifc_query_adapter_out_bits { 5177 u8 status[0x8]; 5178 u8 reserved_at_8[0x18]; 5179 5180 u8 syndrome[0x20]; 5181 5182 u8 reserved_at_40[0x40]; 5183 5184 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5185 }; 5186 5187 struct mlx5_ifc_query_adapter_in_bits { 5188 u8 opcode[0x10]; 5189 u8 reserved_at_10[0x10]; 5190 5191 u8 reserved_at_20[0x10]; 5192 u8 op_mod[0x10]; 5193 5194 u8 reserved_at_40[0x40]; 5195 }; 5196 5197 struct mlx5_ifc_qp_2rst_out_bits { 5198 u8 status[0x8]; 5199 u8 reserved_at_8[0x18]; 5200 5201 u8 syndrome[0x20]; 5202 5203 u8 reserved_at_40[0x40]; 5204 }; 5205 5206 struct mlx5_ifc_qp_2rst_in_bits { 5207 u8 opcode[0x10]; 5208 u8 uid[0x10]; 5209 5210 u8 reserved_at_20[0x10]; 5211 u8 op_mod[0x10]; 5212 5213 u8 reserved_at_40[0x8]; 5214 u8 qpn[0x18]; 5215 5216 u8 reserved_at_60[0x20]; 5217 }; 5218 5219 struct mlx5_ifc_qp_2err_out_bits { 5220 u8 status[0x8]; 5221 u8 reserved_at_8[0x18]; 5222 5223 u8 syndrome[0x20]; 5224 5225 u8 reserved_at_40[0x40]; 5226 }; 5227 5228 struct mlx5_ifc_qp_2err_in_bits { 5229 u8 opcode[0x10]; 5230 u8 uid[0x10]; 5231 5232 u8 reserved_at_20[0x10]; 5233 u8 op_mod[0x10]; 5234 5235 u8 reserved_at_40[0x8]; 5236 u8 qpn[0x18]; 5237 5238 u8 reserved_at_60[0x20]; 5239 }; 5240 5241 struct mlx5_ifc_page_fault_resume_out_bits { 5242 u8 status[0x8]; 5243 u8 reserved_at_8[0x18]; 5244 5245 u8 syndrome[0x20]; 5246 5247 u8 reserved_at_40[0x40]; 5248 }; 5249 5250 struct mlx5_ifc_page_fault_resume_in_bits { 5251 u8 opcode[0x10]; 5252 u8 reserved_at_10[0x10]; 5253 5254 u8 reserved_at_20[0x10]; 5255 u8 op_mod[0x10]; 5256 5257 u8 error[0x1]; 5258 u8 reserved_at_41[0x4]; 5259 u8 page_fault_type[0x3]; 5260 u8 wq_number[0x18]; 5261 5262 u8 reserved_at_60[0x8]; 5263 u8 token[0x18]; 5264 }; 5265 5266 struct mlx5_ifc_nop_out_bits { 5267 u8 status[0x8]; 5268 u8 reserved_at_8[0x18]; 5269 5270 u8 syndrome[0x20]; 5271 5272 u8 reserved_at_40[0x40]; 5273 }; 5274 5275 struct mlx5_ifc_nop_in_bits { 5276 u8 opcode[0x10]; 5277 u8 reserved_at_10[0x10]; 5278 5279 u8 reserved_at_20[0x10]; 5280 u8 op_mod[0x10]; 5281 5282 u8 reserved_at_40[0x40]; 5283 }; 5284 5285 struct mlx5_ifc_modify_vport_state_out_bits { 5286 u8 status[0x8]; 5287 u8 reserved_at_8[0x18]; 5288 5289 u8 syndrome[0x20]; 5290 5291 u8 reserved_at_40[0x40]; 5292 }; 5293 5294 struct mlx5_ifc_modify_vport_state_in_bits { 5295 u8 opcode[0x10]; 5296 u8 reserved_at_10[0x10]; 5297 5298 u8 reserved_at_20[0x10]; 5299 u8 op_mod[0x10]; 5300 5301 u8 other_vport[0x1]; 5302 u8 reserved_at_41[0xf]; 5303 u8 vport_number[0x10]; 5304 5305 u8 reserved_at_60[0x18]; 5306 u8 admin_state[0x4]; 5307 u8 reserved_at_7c[0x4]; 5308 }; 5309 5310 struct mlx5_ifc_modify_tis_out_bits { 5311 u8 status[0x8]; 5312 u8 reserved_at_8[0x18]; 5313 5314 u8 syndrome[0x20]; 5315 5316 u8 reserved_at_40[0x40]; 5317 }; 5318 5319 struct mlx5_ifc_modify_tis_bitmask_bits { 5320 u8 reserved_at_0[0x20]; 5321 5322 u8 reserved_at_20[0x1d]; 5323 u8 lag_tx_port_affinity[0x1]; 5324 u8 strict_lag_tx_port_affinity[0x1]; 5325 u8 prio[0x1]; 5326 }; 5327 5328 struct mlx5_ifc_modify_tis_in_bits { 5329 u8 opcode[0x10]; 5330 u8 uid[0x10]; 5331 5332 u8 reserved_at_20[0x10]; 5333 u8 op_mod[0x10]; 5334 5335 u8 reserved_at_40[0x8]; 5336 u8 tisn[0x18]; 5337 5338 u8 reserved_at_60[0x20]; 5339 5340 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5341 5342 u8 reserved_at_c0[0x40]; 5343 5344 struct mlx5_ifc_tisc_bits ctx; 5345 }; 5346 5347 struct mlx5_ifc_modify_tir_bitmask_bits { 5348 u8 reserved_at_0[0x20]; 5349 5350 u8 reserved_at_20[0x1b]; 5351 u8 self_lb_en[0x1]; 5352 u8 reserved_at_3c[0x1]; 5353 u8 hash[0x1]; 5354 u8 reserved_at_3e[0x1]; 5355 u8 lro[0x1]; 5356 }; 5357 5358 struct mlx5_ifc_modify_tir_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_at_8[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 reserved_at_40[0x40]; 5365 }; 5366 5367 struct mlx5_ifc_modify_tir_in_bits { 5368 u8 opcode[0x10]; 5369 u8 uid[0x10]; 5370 5371 u8 reserved_at_20[0x10]; 5372 u8 op_mod[0x10]; 5373 5374 u8 reserved_at_40[0x8]; 5375 u8 tirn[0x18]; 5376 5377 u8 reserved_at_60[0x20]; 5378 5379 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5380 5381 u8 reserved_at_c0[0x40]; 5382 5383 struct mlx5_ifc_tirc_bits ctx; 5384 }; 5385 5386 struct mlx5_ifc_modify_sq_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_at_8[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_at_40[0x40]; 5393 }; 5394 5395 struct mlx5_ifc_modify_sq_in_bits { 5396 u8 opcode[0x10]; 5397 u8 uid[0x10]; 5398 5399 u8 reserved_at_20[0x10]; 5400 u8 op_mod[0x10]; 5401 5402 u8 sq_state[0x4]; 5403 u8 reserved_at_44[0x4]; 5404 u8 sqn[0x18]; 5405 5406 u8 reserved_at_60[0x20]; 5407 5408 u8 modify_bitmask[0x40]; 5409 5410 u8 reserved_at_c0[0x40]; 5411 5412 struct mlx5_ifc_sqc_bits ctx; 5413 }; 5414 5415 struct mlx5_ifc_modify_scheduling_element_out_bits { 5416 u8 status[0x8]; 5417 u8 reserved_at_8[0x18]; 5418 5419 u8 syndrome[0x20]; 5420 5421 u8 reserved_at_40[0x1c0]; 5422 }; 5423 5424 enum { 5425 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5426 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5427 }; 5428 5429 struct mlx5_ifc_modify_scheduling_element_in_bits { 5430 u8 opcode[0x10]; 5431 u8 reserved_at_10[0x10]; 5432 5433 u8 reserved_at_20[0x10]; 5434 u8 op_mod[0x10]; 5435 5436 u8 scheduling_hierarchy[0x8]; 5437 u8 reserved_at_48[0x18]; 5438 5439 u8 scheduling_element_id[0x20]; 5440 5441 u8 reserved_at_80[0x20]; 5442 5443 u8 modify_bitmask[0x20]; 5444 5445 u8 reserved_at_c0[0x40]; 5446 5447 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5448 5449 u8 reserved_at_300[0x100]; 5450 }; 5451 5452 struct mlx5_ifc_modify_rqt_out_bits { 5453 u8 status[0x8]; 5454 u8 reserved_at_8[0x18]; 5455 5456 u8 syndrome[0x20]; 5457 5458 u8 reserved_at_40[0x40]; 5459 }; 5460 5461 struct mlx5_ifc_rqt_bitmask_bits { 5462 u8 reserved_at_0[0x20]; 5463 5464 u8 reserved_at_20[0x1f]; 5465 u8 rqn_list[0x1]; 5466 }; 5467 5468 struct mlx5_ifc_modify_rqt_in_bits { 5469 u8 opcode[0x10]; 5470 u8 uid[0x10]; 5471 5472 u8 reserved_at_20[0x10]; 5473 u8 op_mod[0x10]; 5474 5475 u8 reserved_at_40[0x8]; 5476 u8 rqtn[0x18]; 5477 5478 u8 reserved_at_60[0x20]; 5479 5480 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5481 5482 u8 reserved_at_c0[0x40]; 5483 5484 struct mlx5_ifc_rqtc_bits ctx; 5485 }; 5486 5487 struct mlx5_ifc_modify_rq_out_bits { 5488 u8 status[0x8]; 5489 u8 reserved_at_8[0x18]; 5490 5491 u8 syndrome[0x20]; 5492 5493 u8 reserved_at_40[0x40]; 5494 }; 5495 5496 enum { 5497 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5498 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5499 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5500 }; 5501 5502 struct mlx5_ifc_modify_rq_in_bits { 5503 u8 opcode[0x10]; 5504 u8 uid[0x10]; 5505 5506 u8 reserved_at_20[0x10]; 5507 u8 op_mod[0x10]; 5508 5509 u8 rq_state[0x4]; 5510 u8 reserved_at_44[0x4]; 5511 u8 rqn[0x18]; 5512 5513 u8 reserved_at_60[0x20]; 5514 5515 u8 modify_bitmask[0x40]; 5516 5517 u8 reserved_at_c0[0x40]; 5518 5519 struct mlx5_ifc_rqc_bits ctx; 5520 }; 5521 5522 struct mlx5_ifc_modify_rmp_out_bits { 5523 u8 status[0x8]; 5524 u8 reserved_at_8[0x18]; 5525 5526 u8 syndrome[0x20]; 5527 5528 u8 reserved_at_40[0x40]; 5529 }; 5530 5531 struct mlx5_ifc_rmp_bitmask_bits { 5532 u8 reserved_at_0[0x20]; 5533 5534 u8 reserved_at_20[0x1f]; 5535 u8 lwm[0x1]; 5536 }; 5537 5538 struct mlx5_ifc_modify_rmp_in_bits { 5539 u8 opcode[0x10]; 5540 u8 uid[0x10]; 5541 5542 u8 reserved_at_20[0x10]; 5543 u8 op_mod[0x10]; 5544 5545 u8 rmp_state[0x4]; 5546 u8 reserved_at_44[0x4]; 5547 u8 rmpn[0x18]; 5548 5549 u8 reserved_at_60[0x20]; 5550 5551 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5552 5553 u8 reserved_at_c0[0x40]; 5554 5555 struct mlx5_ifc_rmpc_bits ctx; 5556 }; 5557 5558 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5559 u8 status[0x8]; 5560 u8 reserved_at_8[0x18]; 5561 5562 u8 syndrome[0x20]; 5563 5564 u8 reserved_at_40[0x40]; 5565 }; 5566 5567 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5568 u8 reserved_at_0[0x12]; 5569 u8 affiliation[0x1]; 5570 u8 reserved_at_e[0x1]; 5571 u8 disable_uc_local_lb[0x1]; 5572 u8 disable_mc_local_lb[0x1]; 5573 u8 node_guid[0x1]; 5574 u8 port_guid[0x1]; 5575 u8 min_inline[0x1]; 5576 u8 mtu[0x1]; 5577 u8 change_event[0x1]; 5578 u8 promisc[0x1]; 5579 u8 permanent_address[0x1]; 5580 u8 addresses_list[0x1]; 5581 u8 roce_en[0x1]; 5582 u8 reserved_at_1f[0x1]; 5583 }; 5584 5585 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5586 u8 opcode[0x10]; 5587 u8 reserved_at_10[0x10]; 5588 5589 u8 reserved_at_20[0x10]; 5590 u8 op_mod[0x10]; 5591 5592 u8 other_vport[0x1]; 5593 u8 reserved_at_41[0xf]; 5594 u8 vport_number[0x10]; 5595 5596 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5597 5598 u8 reserved_at_80[0x780]; 5599 5600 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5601 }; 5602 5603 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5604 u8 status[0x8]; 5605 u8 reserved_at_8[0x18]; 5606 5607 u8 syndrome[0x20]; 5608 5609 u8 reserved_at_40[0x40]; 5610 }; 5611 5612 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5613 u8 opcode[0x10]; 5614 u8 reserved_at_10[0x10]; 5615 5616 u8 reserved_at_20[0x10]; 5617 u8 op_mod[0x10]; 5618 5619 u8 other_vport[0x1]; 5620 u8 reserved_at_41[0xb]; 5621 u8 port_num[0x4]; 5622 u8 vport_number[0x10]; 5623 5624 u8 reserved_at_60[0x20]; 5625 5626 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5627 }; 5628 5629 struct mlx5_ifc_modify_cq_out_bits { 5630 u8 status[0x8]; 5631 u8 reserved_at_8[0x18]; 5632 5633 u8 syndrome[0x20]; 5634 5635 u8 reserved_at_40[0x40]; 5636 }; 5637 5638 enum { 5639 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5640 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5641 }; 5642 5643 struct mlx5_ifc_modify_cq_in_bits { 5644 u8 opcode[0x10]; 5645 u8 uid[0x10]; 5646 5647 u8 reserved_at_20[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 reserved_at_40[0x8]; 5651 u8 cqn[0x18]; 5652 5653 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5654 5655 struct mlx5_ifc_cqc_bits cq_context; 5656 5657 u8 reserved_at_280[0x40]; 5658 5659 u8 cq_umem_valid[0x1]; 5660 u8 reserved_at_2c1[0x5bf]; 5661 5662 u8 pas[0][0x40]; 5663 }; 5664 5665 struct mlx5_ifc_modify_cong_status_out_bits { 5666 u8 status[0x8]; 5667 u8 reserved_at_8[0x18]; 5668 5669 u8 syndrome[0x20]; 5670 5671 u8 reserved_at_40[0x40]; 5672 }; 5673 5674 struct mlx5_ifc_modify_cong_status_in_bits { 5675 u8 opcode[0x10]; 5676 u8 reserved_at_10[0x10]; 5677 5678 u8 reserved_at_20[0x10]; 5679 u8 op_mod[0x10]; 5680 5681 u8 reserved_at_40[0x18]; 5682 u8 priority[0x4]; 5683 u8 cong_protocol[0x4]; 5684 5685 u8 enable[0x1]; 5686 u8 tag_enable[0x1]; 5687 u8 reserved_at_62[0x1e]; 5688 }; 5689 5690 struct mlx5_ifc_modify_cong_params_out_bits { 5691 u8 status[0x8]; 5692 u8 reserved_at_8[0x18]; 5693 5694 u8 syndrome[0x20]; 5695 5696 u8 reserved_at_40[0x40]; 5697 }; 5698 5699 struct mlx5_ifc_modify_cong_params_in_bits { 5700 u8 opcode[0x10]; 5701 u8 reserved_at_10[0x10]; 5702 5703 u8 reserved_at_20[0x10]; 5704 u8 op_mod[0x10]; 5705 5706 u8 reserved_at_40[0x1c]; 5707 u8 cong_protocol[0x4]; 5708 5709 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5710 5711 u8 reserved_at_80[0x80]; 5712 5713 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5714 }; 5715 5716 struct mlx5_ifc_manage_pages_out_bits { 5717 u8 status[0x8]; 5718 u8 reserved_at_8[0x18]; 5719 5720 u8 syndrome[0x20]; 5721 5722 u8 output_num_entries[0x20]; 5723 5724 u8 reserved_at_60[0x20]; 5725 5726 u8 pas[0][0x40]; 5727 }; 5728 5729 enum { 5730 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5731 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5732 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5733 }; 5734 5735 struct mlx5_ifc_manage_pages_in_bits { 5736 u8 opcode[0x10]; 5737 u8 reserved_at_10[0x10]; 5738 5739 u8 reserved_at_20[0x10]; 5740 u8 op_mod[0x10]; 5741 5742 u8 reserved_at_40[0x10]; 5743 u8 function_id[0x10]; 5744 5745 u8 input_num_entries[0x20]; 5746 5747 u8 pas[0][0x40]; 5748 }; 5749 5750 struct mlx5_ifc_mad_ifc_out_bits { 5751 u8 status[0x8]; 5752 u8 reserved_at_8[0x18]; 5753 5754 u8 syndrome[0x20]; 5755 5756 u8 reserved_at_40[0x40]; 5757 5758 u8 response_mad_packet[256][0x8]; 5759 }; 5760 5761 struct mlx5_ifc_mad_ifc_in_bits { 5762 u8 opcode[0x10]; 5763 u8 reserved_at_10[0x10]; 5764 5765 u8 reserved_at_20[0x10]; 5766 u8 op_mod[0x10]; 5767 5768 u8 remote_lid[0x10]; 5769 u8 reserved_at_50[0x8]; 5770 u8 port[0x8]; 5771 5772 u8 reserved_at_60[0x20]; 5773 5774 u8 mad[256][0x8]; 5775 }; 5776 5777 struct mlx5_ifc_init_hca_out_bits { 5778 u8 status[0x8]; 5779 u8 reserved_at_8[0x18]; 5780 5781 u8 syndrome[0x20]; 5782 5783 u8 reserved_at_40[0x40]; 5784 }; 5785 5786 struct mlx5_ifc_init_hca_in_bits { 5787 u8 opcode[0x10]; 5788 u8 reserved_at_10[0x10]; 5789 5790 u8 reserved_at_20[0x10]; 5791 u8 op_mod[0x10]; 5792 5793 u8 reserved_at_40[0x40]; 5794 u8 sw_owner_id[4][0x20]; 5795 }; 5796 5797 struct mlx5_ifc_init2rtr_qp_out_bits { 5798 u8 status[0x8]; 5799 u8 reserved_at_8[0x18]; 5800 5801 u8 syndrome[0x20]; 5802 5803 u8 reserved_at_40[0x40]; 5804 }; 5805 5806 struct mlx5_ifc_init2rtr_qp_in_bits { 5807 u8 opcode[0x10]; 5808 u8 uid[0x10]; 5809 5810 u8 reserved_at_20[0x10]; 5811 u8 op_mod[0x10]; 5812 5813 u8 reserved_at_40[0x8]; 5814 u8 qpn[0x18]; 5815 5816 u8 reserved_at_60[0x20]; 5817 5818 u8 opt_param_mask[0x20]; 5819 5820 u8 reserved_at_a0[0x20]; 5821 5822 struct mlx5_ifc_qpc_bits qpc; 5823 5824 u8 reserved_at_800[0x80]; 5825 }; 5826 5827 struct mlx5_ifc_init2init_qp_out_bits { 5828 u8 status[0x8]; 5829 u8 reserved_at_8[0x18]; 5830 5831 u8 syndrome[0x20]; 5832 5833 u8 reserved_at_40[0x40]; 5834 }; 5835 5836 struct mlx5_ifc_init2init_qp_in_bits { 5837 u8 opcode[0x10]; 5838 u8 uid[0x10]; 5839 5840 u8 reserved_at_20[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 reserved_at_40[0x8]; 5844 u8 qpn[0x18]; 5845 5846 u8 reserved_at_60[0x20]; 5847 5848 u8 opt_param_mask[0x20]; 5849 5850 u8 reserved_at_a0[0x20]; 5851 5852 struct mlx5_ifc_qpc_bits qpc; 5853 5854 u8 reserved_at_800[0x80]; 5855 }; 5856 5857 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5858 u8 status[0x8]; 5859 u8 reserved_at_8[0x18]; 5860 5861 u8 syndrome[0x20]; 5862 5863 u8 reserved_at_40[0x40]; 5864 5865 u8 packet_headers_log[128][0x8]; 5866 5867 u8 packet_syndrome[64][0x8]; 5868 }; 5869 5870 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5871 u8 opcode[0x10]; 5872 u8 reserved_at_10[0x10]; 5873 5874 u8 reserved_at_20[0x10]; 5875 u8 op_mod[0x10]; 5876 5877 u8 reserved_at_40[0x40]; 5878 }; 5879 5880 struct mlx5_ifc_gen_eqe_in_bits { 5881 u8 opcode[0x10]; 5882 u8 reserved_at_10[0x10]; 5883 5884 u8 reserved_at_20[0x10]; 5885 u8 op_mod[0x10]; 5886 5887 u8 reserved_at_40[0x18]; 5888 u8 eq_number[0x8]; 5889 5890 u8 reserved_at_60[0x20]; 5891 5892 u8 eqe[64][0x8]; 5893 }; 5894 5895 struct mlx5_ifc_gen_eq_out_bits { 5896 u8 status[0x8]; 5897 u8 reserved_at_8[0x18]; 5898 5899 u8 syndrome[0x20]; 5900 5901 u8 reserved_at_40[0x40]; 5902 }; 5903 5904 struct mlx5_ifc_enable_hca_out_bits { 5905 u8 status[0x8]; 5906 u8 reserved_at_8[0x18]; 5907 5908 u8 syndrome[0x20]; 5909 5910 u8 reserved_at_40[0x20]; 5911 }; 5912 5913 struct mlx5_ifc_enable_hca_in_bits { 5914 u8 opcode[0x10]; 5915 u8 reserved_at_10[0x10]; 5916 5917 u8 reserved_at_20[0x10]; 5918 u8 op_mod[0x10]; 5919 5920 u8 reserved_at_40[0x10]; 5921 u8 function_id[0x10]; 5922 5923 u8 reserved_at_60[0x20]; 5924 }; 5925 5926 struct mlx5_ifc_drain_dct_out_bits { 5927 u8 status[0x8]; 5928 u8 reserved_at_8[0x18]; 5929 5930 u8 syndrome[0x20]; 5931 5932 u8 reserved_at_40[0x40]; 5933 }; 5934 5935 struct mlx5_ifc_drain_dct_in_bits { 5936 u8 opcode[0x10]; 5937 u8 uid[0x10]; 5938 5939 u8 reserved_at_20[0x10]; 5940 u8 op_mod[0x10]; 5941 5942 u8 reserved_at_40[0x8]; 5943 u8 dctn[0x18]; 5944 5945 u8 reserved_at_60[0x20]; 5946 }; 5947 5948 struct mlx5_ifc_disable_hca_out_bits { 5949 u8 status[0x8]; 5950 u8 reserved_at_8[0x18]; 5951 5952 u8 syndrome[0x20]; 5953 5954 u8 reserved_at_40[0x20]; 5955 }; 5956 5957 struct mlx5_ifc_disable_hca_in_bits { 5958 u8 opcode[0x10]; 5959 u8 reserved_at_10[0x10]; 5960 5961 u8 reserved_at_20[0x10]; 5962 u8 op_mod[0x10]; 5963 5964 u8 reserved_at_40[0x10]; 5965 u8 function_id[0x10]; 5966 5967 u8 reserved_at_60[0x20]; 5968 }; 5969 5970 struct mlx5_ifc_detach_from_mcg_out_bits { 5971 u8 status[0x8]; 5972 u8 reserved_at_8[0x18]; 5973 5974 u8 syndrome[0x20]; 5975 5976 u8 reserved_at_40[0x40]; 5977 }; 5978 5979 struct mlx5_ifc_detach_from_mcg_in_bits { 5980 u8 opcode[0x10]; 5981 u8 uid[0x10]; 5982 5983 u8 reserved_at_20[0x10]; 5984 u8 op_mod[0x10]; 5985 5986 u8 reserved_at_40[0x8]; 5987 u8 qpn[0x18]; 5988 5989 u8 reserved_at_60[0x20]; 5990 5991 u8 multicast_gid[16][0x8]; 5992 }; 5993 5994 struct mlx5_ifc_destroy_xrq_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_at_8[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_at_40[0x40]; 6001 }; 6002 6003 struct mlx5_ifc_destroy_xrq_in_bits { 6004 u8 opcode[0x10]; 6005 u8 uid[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x8]; 6011 u8 xrqn[0x18]; 6012 6013 u8 reserved_at_60[0x20]; 6014 }; 6015 6016 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6017 u8 status[0x8]; 6018 u8 reserved_at_8[0x18]; 6019 6020 u8 syndrome[0x20]; 6021 6022 u8 reserved_at_40[0x40]; 6023 }; 6024 6025 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6026 u8 opcode[0x10]; 6027 u8 uid[0x10]; 6028 6029 u8 reserved_at_20[0x10]; 6030 u8 op_mod[0x10]; 6031 6032 u8 reserved_at_40[0x8]; 6033 u8 xrc_srqn[0x18]; 6034 6035 u8 reserved_at_60[0x20]; 6036 }; 6037 6038 struct mlx5_ifc_destroy_tis_out_bits { 6039 u8 status[0x8]; 6040 u8 reserved_at_8[0x18]; 6041 6042 u8 syndrome[0x20]; 6043 6044 u8 reserved_at_40[0x40]; 6045 }; 6046 6047 struct mlx5_ifc_destroy_tis_in_bits { 6048 u8 opcode[0x10]; 6049 u8 uid[0x10]; 6050 6051 u8 reserved_at_20[0x10]; 6052 u8 op_mod[0x10]; 6053 6054 u8 reserved_at_40[0x8]; 6055 u8 tisn[0x18]; 6056 6057 u8 reserved_at_60[0x20]; 6058 }; 6059 6060 struct mlx5_ifc_destroy_tir_out_bits { 6061 u8 status[0x8]; 6062 u8 reserved_at_8[0x18]; 6063 6064 u8 syndrome[0x20]; 6065 6066 u8 reserved_at_40[0x40]; 6067 }; 6068 6069 struct mlx5_ifc_destroy_tir_in_bits { 6070 u8 opcode[0x10]; 6071 u8 uid[0x10]; 6072 6073 u8 reserved_at_20[0x10]; 6074 u8 op_mod[0x10]; 6075 6076 u8 reserved_at_40[0x8]; 6077 u8 tirn[0x18]; 6078 6079 u8 reserved_at_60[0x20]; 6080 }; 6081 6082 struct mlx5_ifc_destroy_srq_out_bits { 6083 u8 status[0x8]; 6084 u8 reserved_at_8[0x18]; 6085 6086 u8 syndrome[0x20]; 6087 6088 u8 reserved_at_40[0x40]; 6089 }; 6090 6091 struct mlx5_ifc_destroy_srq_in_bits { 6092 u8 opcode[0x10]; 6093 u8 uid[0x10]; 6094 6095 u8 reserved_at_20[0x10]; 6096 u8 op_mod[0x10]; 6097 6098 u8 reserved_at_40[0x8]; 6099 u8 srqn[0x18]; 6100 6101 u8 reserved_at_60[0x20]; 6102 }; 6103 6104 struct mlx5_ifc_destroy_sq_out_bits { 6105 u8 status[0x8]; 6106 u8 reserved_at_8[0x18]; 6107 6108 u8 syndrome[0x20]; 6109 6110 u8 reserved_at_40[0x40]; 6111 }; 6112 6113 struct mlx5_ifc_destroy_sq_in_bits { 6114 u8 opcode[0x10]; 6115 u8 uid[0x10]; 6116 6117 u8 reserved_at_20[0x10]; 6118 u8 op_mod[0x10]; 6119 6120 u8 reserved_at_40[0x8]; 6121 u8 sqn[0x18]; 6122 6123 u8 reserved_at_60[0x20]; 6124 }; 6125 6126 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6127 u8 status[0x8]; 6128 u8 reserved_at_8[0x18]; 6129 6130 u8 syndrome[0x20]; 6131 6132 u8 reserved_at_40[0x1c0]; 6133 }; 6134 6135 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6136 u8 opcode[0x10]; 6137 u8 reserved_at_10[0x10]; 6138 6139 u8 reserved_at_20[0x10]; 6140 u8 op_mod[0x10]; 6141 6142 u8 scheduling_hierarchy[0x8]; 6143 u8 reserved_at_48[0x18]; 6144 6145 u8 scheduling_element_id[0x20]; 6146 6147 u8 reserved_at_80[0x180]; 6148 }; 6149 6150 struct mlx5_ifc_destroy_rqt_out_bits { 6151 u8 status[0x8]; 6152 u8 reserved_at_8[0x18]; 6153 6154 u8 syndrome[0x20]; 6155 6156 u8 reserved_at_40[0x40]; 6157 }; 6158 6159 struct mlx5_ifc_destroy_rqt_in_bits { 6160 u8 opcode[0x10]; 6161 u8 uid[0x10]; 6162 6163 u8 reserved_at_20[0x10]; 6164 u8 op_mod[0x10]; 6165 6166 u8 reserved_at_40[0x8]; 6167 u8 rqtn[0x18]; 6168 6169 u8 reserved_at_60[0x20]; 6170 }; 6171 6172 struct mlx5_ifc_destroy_rq_out_bits { 6173 u8 status[0x8]; 6174 u8 reserved_at_8[0x18]; 6175 6176 u8 syndrome[0x20]; 6177 6178 u8 reserved_at_40[0x40]; 6179 }; 6180 6181 struct mlx5_ifc_destroy_rq_in_bits { 6182 u8 opcode[0x10]; 6183 u8 uid[0x10]; 6184 6185 u8 reserved_at_20[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 reserved_at_40[0x8]; 6189 u8 rqn[0x18]; 6190 6191 u8 reserved_at_60[0x20]; 6192 }; 6193 6194 struct mlx5_ifc_set_delay_drop_params_in_bits { 6195 u8 opcode[0x10]; 6196 u8 reserved_at_10[0x10]; 6197 6198 u8 reserved_at_20[0x10]; 6199 u8 op_mod[0x10]; 6200 6201 u8 reserved_at_40[0x20]; 6202 6203 u8 reserved_at_60[0x10]; 6204 u8 delay_drop_timeout[0x10]; 6205 }; 6206 6207 struct mlx5_ifc_set_delay_drop_params_out_bits { 6208 u8 status[0x8]; 6209 u8 reserved_at_8[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 reserved_at_40[0x40]; 6214 }; 6215 6216 struct mlx5_ifc_destroy_rmp_out_bits { 6217 u8 status[0x8]; 6218 u8 reserved_at_8[0x18]; 6219 6220 u8 syndrome[0x20]; 6221 6222 u8 reserved_at_40[0x40]; 6223 }; 6224 6225 struct mlx5_ifc_destroy_rmp_in_bits { 6226 u8 opcode[0x10]; 6227 u8 uid[0x10]; 6228 6229 u8 reserved_at_20[0x10]; 6230 u8 op_mod[0x10]; 6231 6232 u8 reserved_at_40[0x8]; 6233 u8 rmpn[0x18]; 6234 6235 u8 reserved_at_60[0x20]; 6236 }; 6237 6238 struct mlx5_ifc_destroy_qp_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 }; 6246 6247 struct mlx5_ifc_destroy_qp_in_bits { 6248 u8 opcode[0x10]; 6249 u8 uid[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 reserved_at_40[0x8]; 6255 u8 qpn[0x18]; 6256 6257 u8 reserved_at_60[0x20]; 6258 }; 6259 6260 struct mlx5_ifc_destroy_psv_out_bits { 6261 u8 status[0x8]; 6262 u8 reserved_at_8[0x18]; 6263 6264 u8 syndrome[0x20]; 6265 6266 u8 reserved_at_40[0x40]; 6267 }; 6268 6269 struct mlx5_ifc_destroy_psv_in_bits { 6270 u8 opcode[0x10]; 6271 u8 reserved_at_10[0x10]; 6272 6273 u8 reserved_at_20[0x10]; 6274 u8 op_mod[0x10]; 6275 6276 u8 reserved_at_40[0x8]; 6277 u8 psvn[0x18]; 6278 6279 u8 reserved_at_60[0x20]; 6280 }; 6281 6282 struct mlx5_ifc_destroy_mkey_out_bits { 6283 u8 status[0x8]; 6284 u8 reserved_at_8[0x18]; 6285 6286 u8 syndrome[0x20]; 6287 6288 u8 reserved_at_40[0x40]; 6289 }; 6290 6291 struct mlx5_ifc_destroy_mkey_in_bits { 6292 u8 opcode[0x10]; 6293 u8 reserved_at_10[0x10]; 6294 6295 u8 reserved_at_20[0x10]; 6296 u8 op_mod[0x10]; 6297 6298 u8 reserved_at_40[0x8]; 6299 u8 mkey_index[0x18]; 6300 6301 u8 reserved_at_60[0x20]; 6302 }; 6303 6304 struct mlx5_ifc_destroy_flow_table_out_bits { 6305 u8 status[0x8]; 6306 u8 reserved_at_8[0x18]; 6307 6308 u8 syndrome[0x20]; 6309 6310 u8 reserved_at_40[0x40]; 6311 }; 6312 6313 struct mlx5_ifc_destroy_flow_table_in_bits { 6314 u8 opcode[0x10]; 6315 u8 reserved_at_10[0x10]; 6316 6317 u8 reserved_at_20[0x10]; 6318 u8 op_mod[0x10]; 6319 6320 u8 other_vport[0x1]; 6321 u8 reserved_at_41[0xf]; 6322 u8 vport_number[0x10]; 6323 6324 u8 reserved_at_60[0x20]; 6325 6326 u8 table_type[0x8]; 6327 u8 reserved_at_88[0x18]; 6328 6329 u8 reserved_at_a0[0x8]; 6330 u8 table_id[0x18]; 6331 6332 u8 reserved_at_c0[0x140]; 6333 }; 6334 6335 struct mlx5_ifc_destroy_flow_group_out_bits { 6336 u8 status[0x8]; 6337 u8 reserved_at_8[0x18]; 6338 6339 u8 syndrome[0x20]; 6340 6341 u8 reserved_at_40[0x40]; 6342 }; 6343 6344 struct mlx5_ifc_destroy_flow_group_in_bits { 6345 u8 opcode[0x10]; 6346 u8 reserved_at_10[0x10]; 6347 6348 u8 reserved_at_20[0x10]; 6349 u8 op_mod[0x10]; 6350 6351 u8 other_vport[0x1]; 6352 u8 reserved_at_41[0xf]; 6353 u8 vport_number[0x10]; 6354 6355 u8 reserved_at_60[0x20]; 6356 6357 u8 table_type[0x8]; 6358 u8 reserved_at_88[0x18]; 6359 6360 u8 reserved_at_a0[0x8]; 6361 u8 table_id[0x18]; 6362 6363 u8 group_id[0x20]; 6364 6365 u8 reserved_at_e0[0x120]; 6366 }; 6367 6368 struct mlx5_ifc_destroy_eq_out_bits { 6369 u8 status[0x8]; 6370 u8 reserved_at_8[0x18]; 6371 6372 u8 syndrome[0x20]; 6373 6374 u8 reserved_at_40[0x40]; 6375 }; 6376 6377 struct mlx5_ifc_destroy_eq_in_bits { 6378 u8 opcode[0x10]; 6379 u8 reserved_at_10[0x10]; 6380 6381 u8 reserved_at_20[0x10]; 6382 u8 op_mod[0x10]; 6383 6384 u8 reserved_at_40[0x18]; 6385 u8 eq_number[0x8]; 6386 6387 u8 reserved_at_60[0x20]; 6388 }; 6389 6390 struct mlx5_ifc_destroy_dct_out_bits { 6391 u8 status[0x8]; 6392 u8 reserved_at_8[0x18]; 6393 6394 u8 syndrome[0x20]; 6395 6396 u8 reserved_at_40[0x40]; 6397 }; 6398 6399 struct mlx5_ifc_destroy_dct_in_bits { 6400 u8 opcode[0x10]; 6401 u8 uid[0x10]; 6402 6403 u8 reserved_at_20[0x10]; 6404 u8 op_mod[0x10]; 6405 6406 u8 reserved_at_40[0x8]; 6407 u8 dctn[0x18]; 6408 6409 u8 reserved_at_60[0x20]; 6410 }; 6411 6412 struct mlx5_ifc_destroy_cq_out_bits { 6413 u8 status[0x8]; 6414 u8 reserved_at_8[0x18]; 6415 6416 u8 syndrome[0x20]; 6417 6418 u8 reserved_at_40[0x40]; 6419 }; 6420 6421 struct mlx5_ifc_destroy_cq_in_bits { 6422 u8 opcode[0x10]; 6423 u8 uid[0x10]; 6424 6425 u8 reserved_at_20[0x10]; 6426 u8 op_mod[0x10]; 6427 6428 u8 reserved_at_40[0x8]; 6429 u8 cqn[0x18]; 6430 6431 u8 reserved_at_60[0x20]; 6432 }; 6433 6434 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6435 u8 status[0x8]; 6436 u8 reserved_at_8[0x18]; 6437 6438 u8 syndrome[0x20]; 6439 6440 u8 reserved_at_40[0x40]; 6441 }; 6442 6443 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6444 u8 opcode[0x10]; 6445 u8 reserved_at_10[0x10]; 6446 6447 u8 reserved_at_20[0x10]; 6448 u8 op_mod[0x10]; 6449 6450 u8 reserved_at_40[0x20]; 6451 6452 u8 reserved_at_60[0x10]; 6453 u8 vxlan_udp_port[0x10]; 6454 }; 6455 6456 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6457 u8 status[0x8]; 6458 u8 reserved_at_8[0x18]; 6459 6460 u8 syndrome[0x20]; 6461 6462 u8 reserved_at_40[0x40]; 6463 }; 6464 6465 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6466 u8 opcode[0x10]; 6467 u8 reserved_at_10[0x10]; 6468 6469 u8 reserved_at_20[0x10]; 6470 u8 op_mod[0x10]; 6471 6472 u8 reserved_at_40[0x60]; 6473 6474 u8 reserved_at_a0[0x8]; 6475 u8 table_index[0x18]; 6476 6477 u8 reserved_at_c0[0x140]; 6478 }; 6479 6480 struct mlx5_ifc_delete_fte_out_bits { 6481 u8 status[0x8]; 6482 u8 reserved_at_8[0x18]; 6483 6484 u8 syndrome[0x20]; 6485 6486 u8 reserved_at_40[0x40]; 6487 }; 6488 6489 struct mlx5_ifc_delete_fte_in_bits { 6490 u8 opcode[0x10]; 6491 u8 reserved_at_10[0x10]; 6492 6493 u8 reserved_at_20[0x10]; 6494 u8 op_mod[0x10]; 6495 6496 u8 other_vport[0x1]; 6497 u8 reserved_at_41[0xf]; 6498 u8 vport_number[0x10]; 6499 6500 u8 reserved_at_60[0x20]; 6501 6502 u8 table_type[0x8]; 6503 u8 reserved_at_88[0x18]; 6504 6505 u8 reserved_at_a0[0x8]; 6506 u8 table_id[0x18]; 6507 6508 u8 reserved_at_c0[0x40]; 6509 6510 u8 flow_index[0x20]; 6511 6512 u8 reserved_at_120[0xe0]; 6513 }; 6514 6515 struct mlx5_ifc_dealloc_xrcd_out_bits { 6516 u8 status[0x8]; 6517 u8 reserved_at_8[0x18]; 6518 6519 u8 syndrome[0x20]; 6520 6521 u8 reserved_at_40[0x40]; 6522 }; 6523 6524 struct mlx5_ifc_dealloc_xrcd_in_bits { 6525 u8 opcode[0x10]; 6526 u8 uid[0x10]; 6527 6528 u8 reserved_at_20[0x10]; 6529 u8 op_mod[0x10]; 6530 6531 u8 reserved_at_40[0x8]; 6532 u8 xrcd[0x18]; 6533 6534 u8 reserved_at_60[0x20]; 6535 }; 6536 6537 struct mlx5_ifc_dealloc_uar_out_bits { 6538 u8 status[0x8]; 6539 u8 reserved_at_8[0x18]; 6540 6541 u8 syndrome[0x20]; 6542 6543 u8 reserved_at_40[0x40]; 6544 }; 6545 6546 struct mlx5_ifc_dealloc_uar_in_bits { 6547 u8 opcode[0x10]; 6548 u8 reserved_at_10[0x10]; 6549 6550 u8 reserved_at_20[0x10]; 6551 u8 op_mod[0x10]; 6552 6553 u8 reserved_at_40[0x8]; 6554 u8 uar[0x18]; 6555 6556 u8 reserved_at_60[0x20]; 6557 }; 6558 6559 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6560 u8 status[0x8]; 6561 u8 reserved_at_8[0x18]; 6562 6563 u8 syndrome[0x20]; 6564 6565 u8 reserved_at_40[0x40]; 6566 }; 6567 6568 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6569 u8 opcode[0x10]; 6570 u8 reserved_at_10[0x10]; 6571 6572 u8 reserved_at_20[0x10]; 6573 u8 op_mod[0x10]; 6574 6575 u8 reserved_at_40[0x8]; 6576 u8 transport_domain[0x18]; 6577 6578 u8 reserved_at_60[0x20]; 6579 }; 6580 6581 struct mlx5_ifc_dealloc_q_counter_out_bits { 6582 u8 status[0x8]; 6583 u8 reserved_at_8[0x18]; 6584 6585 u8 syndrome[0x20]; 6586 6587 u8 reserved_at_40[0x40]; 6588 }; 6589 6590 struct mlx5_ifc_dealloc_q_counter_in_bits { 6591 u8 opcode[0x10]; 6592 u8 reserved_at_10[0x10]; 6593 6594 u8 reserved_at_20[0x10]; 6595 u8 op_mod[0x10]; 6596 6597 u8 reserved_at_40[0x18]; 6598 u8 counter_set_id[0x8]; 6599 6600 u8 reserved_at_60[0x20]; 6601 }; 6602 6603 struct mlx5_ifc_dealloc_pd_out_bits { 6604 u8 status[0x8]; 6605 u8 reserved_at_8[0x18]; 6606 6607 u8 syndrome[0x20]; 6608 6609 u8 reserved_at_40[0x40]; 6610 }; 6611 6612 struct mlx5_ifc_dealloc_pd_in_bits { 6613 u8 opcode[0x10]; 6614 u8 uid[0x10]; 6615 6616 u8 reserved_at_20[0x10]; 6617 u8 op_mod[0x10]; 6618 6619 u8 reserved_at_40[0x8]; 6620 u8 pd[0x18]; 6621 6622 u8 reserved_at_60[0x20]; 6623 }; 6624 6625 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6626 u8 status[0x8]; 6627 u8 reserved_at_8[0x18]; 6628 6629 u8 syndrome[0x20]; 6630 6631 u8 reserved_at_40[0x40]; 6632 }; 6633 6634 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6635 u8 opcode[0x10]; 6636 u8 reserved_at_10[0x10]; 6637 6638 u8 reserved_at_20[0x10]; 6639 u8 op_mod[0x10]; 6640 6641 u8 flow_counter_id[0x20]; 6642 6643 u8 reserved_at_60[0x20]; 6644 }; 6645 6646 struct mlx5_ifc_create_xrq_out_bits { 6647 u8 status[0x8]; 6648 u8 reserved_at_8[0x18]; 6649 6650 u8 syndrome[0x20]; 6651 6652 u8 reserved_at_40[0x8]; 6653 u8 xrqn[0x18]; 6654 6655 u8 reserved_at_60[0x20]; 6656 }; 6657 6658 struct mlx5_ifc_create_xrq_in_bits { 6659 u8 opcode[0x10]; 6660 u8 uid[0x10]; 6661 6662 u8 reserved_at_20[0x10]; 6663 u8 op_mod[0x10]; 6664 6665 u8 reserved_at_40[0x40]; 6666 6667 struct mlx5_ifc_xrqc_bits xrq_context; 6668 }; 6669 6670 struct mlx5_ifc_create_xrc_srq_out_bits { 6671 u8 status[0x8]; 6672 u8 reserved_at_8[0x18]; 6673 6674 u8 syndrome[0x20]; 6675 6676 u8 reserved_at_40[0x8]; 6677 u8 xrc_srqn[0x18]; 6678 6679 u8 reserved_at_60[0x20]; 6680 }; 6681 6682 struct mlx5_ifc_create_xrc_srq_in_bits { 6683 u8 opcode[0x10]; 6684 u8 uid[0x10]; 6685 6686 u8 reserved_at_20[0x10]; 6687 u8 op_mod[0x10]; 6688 6689 u8 reserved_at_40[0x40]; 6690 6691 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6692 6693 u8 reserved_at_280[0x60]; 6694 6695 u8 xrc_srq_umem_valid[0x1]; 6696 u8 reserved_at_2e1[0x1f]; 6697 6698 u8 reserved_at_300[0x580]; 6699 6700 u8 pas[0][0x40]; 6701 }; 6702 6703 struct mlx5_ifc_create_tis_out_bits { 6704 u8 status[0x8]; 6705 u8 reserved_at_8[0x18]; 6706 6707 u8 syndrome[0x20]; 6708 6709 u8 reserved_at_40[0x8]; 6710 u8 tisn[0x18]; 6711 6712 u8 reserved_at_60[0x20]; 6713 }; 6714 6715 struct mlx5_ifc_create_tis_in_bits { 6716 u8 opcode[0x10]; 6717 u8 uid[0x10]; 6718 6719 u8 reserved_at_20[0x10]; 6720 u8 op_mod[0x10]; 6721 6722 u8 reserved_at_40[0xc0]; 6723 6724 struct mlx5_ifc_tisc_bits ctx; 6725 }; 6726 6727 struct mlx5_ifc_create_tir_out_bits { 6728 u8 status[0x8]; 6729 u8 reserved_at_8[0x18]; 6730 6731 u8 syndrome[0x20]; 6732 6733 u8 reserved_at_40[0x8]; 6734 u8 tirn[0x18]; 6735 6736 u8 reserved_at_60[0x20]; 6737 }; 6738 6739 struct mlx5_ifc_create_tir_in_bits { 6740 u8 opcode[0x10]; 6741 u8 uid[0x10]; 6742 6743 u8 reserved_at_20[0x10]; 6744 u8 op_mod[0x10]; 6745 6746 u8 reserved_at_40[0xc0]; 6747 6748 struct mlx5_ifc_tirc_bits ctx; 6749 }; 6750 6751 struct mlx5_ifc_create_srq_out_bits { 6752 u8 status[0x8]; 6753 u8 reserved_at_8[0x18]; 6754 6755 u8 syndrome[0x20]; 6756 6757 u8 reserved_at_40[0x8]; 6758 u8 srqn[0x18]; 6759 6760 u8 reserved_at_60[0x20]; 6761 }; 6762 6763 struct mlx5_ifc_create_srq_in_bits { 6764 u8 opcode[0x10]; 6765 u8 uid[0x10]; 6766 6767 u8 reserved_at_20[0x10]; 6768 u8 op_mod[0x10]; 6769 6770 u8 reserved_at_40[0x40]; 6771 6772 struct mlx5_ifc_srqc_bits srq_context_entry; 6773 6774 u8 reserved_at_280[0x600]; 6775 6776 u8 pas[0][0x40]; 6777 }; 6778 6779 struct mlx5_ifc_create_sq_out_bits { 6780 u8 status[0x8]; 6781 u8 reserved_at_8[0x18]; 6782 6783 u8 syndrome[0x20]; 6784 6785 u8 reserved_at_40[0x8]; 6786 u8 sqn[0x18]; 6787 6788 u8 reserved_at_60[0x20]; 6789 }; 6790 6791 struct mlx5_ifc_create_sq_in_bits { 6792 u8 opcode[0x10]; 6793 u8 uid[0x10]; 6794 6795 u8 reserved_at_20[0x10]; 6796 u8 op_mod[0x10]; 6797 6798 u8 reserved_at_40[0xc0]; 6799 6800 struct mlx5_ifc_sqc_bits ctx; 6801 }; 6802 6803 struct mlx5_ifc_create_scheduling_element_out_bits { 6804 u8 status[0x8]; 6805 u8 reserved_at_8[0x18]; 6806 6807 u8 syndrome[0x20]; 6808 6809 u8 reserved_at_40[0x40]; 6810 6811 u8 scheduling_element_id[0x20]; 6812 6813 u8 reserved_at_a0[0x160]; 6814 }; 6815 6816 struct mlx5_ifc_create_scheduling_element_in_bits { 6817 u8 opcode[0x10]; 6818 u8 reserved_at_10[0x10]; 6819 6820 u8 reserved_at_20[0x10]; 6821 u8 op_mod[0x10]; 6822 6823 u8 scheduling_hierarchy[0x8]; 6824 u8 reserved_at_48[0x18]; 6825 6826 u8 reserved_at_60[0xa0]; 6827 6828 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6829 6830 u8 reserved_at_300[0x100]; 6831 }; 6832 6833 struct mlx5_ifc_create_rqt_out_bits { 6834 u8 status[0x8]; 6835 u8 reserved_at_8[0x18]; 6836 6837 u8 syndrome[0x20]; 6838 6839 u8 reserved_at_40[0x8]; 6840 u8 rqtn[0x18]; 6841 6842 u8 reserved_at_60[0x20]; 6843 }; 6844 6845 struct mlx5_ifc_create_rqt_in_bits { 6846 u8 opcode[0x10]; 6847 u8 uid[0x10]; 6848 6849 u8 reserved_at_20[0x10]; 6850 u8 op_mod[0x10]; 6851 6852 u8 reserved_at_40[0xc0]; 6853 6854 struct mlx5_ifc_rqtc_bits rqt_context; 6855 }; 6856 6857 struct mlx5_ifc_create_rq_out_bits { 6858 u8 status[0x8]; 6859 u8 reserved_at_8[0x18]; 6860 6861 u8 syndrome[0x20]; 6862 6863 u8 reserved_at_40[0x8]; 6864 u8 rqn[0x18]; 6865 6866 u8 reserved_at_60[0x20]; 6867 }; 6868 6869 struct mlx5_ifc_create_rq_in_bits { 6870 u8 opcode[0x10]; 6871 u8 uid[0x10]; 6872 6873 u8 reserved_at_20[0x10]; 6874 u8 op_mod[0x10]; 6875 6876 u8 reserved_at_40[0xc0]; 6877 6878 struct mlx5_ifc_rqc_bits ctx; 6879 }; 6880 6881 struct mlx5_ifc_create_rmp_out_bits { 6882 u8 status[0x8]; 6883 u8 reserved_at_8[0x18]; 6884 6885 u8 syndrome[0x20]; 6886 6887 u8 reserved_at_40[0x8]; 6888 u8 rmpn[0x18]; 6889 6890 u8 reserved_at_60[0x20]; 6891 }; 6892 6893 struct mlx5_ifc_create_rmp_in_bits { 6894 u8 opcode[0x10]; 6895 u8 uid[0x10]; 6896 6897 u8 reserved_at_20[0x10]; 6898 u8 op_mod[0x10]; 6899 6900 u8 reserved_at_40[0xc0]; 6901 6902 struct mlx5_ifc_rmpc_bits ctx; 6903 }; 6904 6905 struct mlx5_ifc_create_qp_out_bits { 6906 u8 status[0x8]; 6907 u8 reserved_at_8[0x18]; 6908 6909 u8 syndrome[0x20]; 6910 6911 u8 reserved_at_40[0x8]; 6912 u8 qpn[0x18]; 6913 6914 u8 reserved_at_60[0x20]; 6915 }; 6916 6917 struct mlx5_ifc_create_qp_in_bits { 6918 u8 opcode[0x10]; 6919 u8 uid[0x10]; 6920 6921 u8 reserved_at_20[0x10]; 6922 u8 op_mod[0x10]; 6923 6924 u8 reserved_at_40[0x40]; 6925 6926 u8 opt_param_mask[0x20]; 6927 6928 u8 reserved_at_a0[0x20]; 6929 6930 struct mlx5_ifc_qpc_bits qpc; 6931 6932 u8 reserved_at_800[0x60]; 6933 6934 u8 wq_umem_valid[0x1]; 6935 u8 reserved_at_861[0x1f]; 6936 6937 u8 pas[0][0x40]; 6938 }; 6939 6940 struct mlx5_ifc_create_psv_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_at_8[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_at_40[0x40]; 6947 6948 u8 reserved_at_80[0x8]; 6949 u8 psv0_index[0x18]; 6950 6951 u8 reserved_at_a0[0x8]; 6952 u8 psv1_index[0x18]; 6953 6954 u8 reserved_at_c0[0x8]; 6955 u8 psv2_index[0x18]; 6956 6957 u8 reserved_at_e0[0x8]; 6958 u8 psv3_index[0x18]; 6959 }; 6960 6961 struct mlx5_ifc_create_psv_in_bits { 6962 u8 opcode[0x10]; 6963 u8 reserved_at_10[0x10]; 6964 6965 u8 reserved_at_20[0x10]; 6966 u8 op_mod[0x10]; 6967 6968 u8 num_psv[0x4]; 6969 u8 reserved_at_44[0x4]; 6970 u8 pd[0x18]; 6971 6972 u8 reserved_at_60[0x20]; 6973 }; 6974 6975 struct mlx5_ifc_create_mkey_out_bits { 6976 u8 status[0x8]; 6977 u8 reserved_at_8[0x18]; 6978 6979 u8 syndrome[0x20]; 6980 6981 u8 reserved_at_40[0x8]; 6982 u8 mkey_index[0x18]; 6983 6984 u8 reserved_at_60[0x20]; 6985 }; 6986 6987 struct mlx5_ifc_create_mkey_in_bits { 6988 u8 opcode[0x10]; 6989 u8 reserved_at_10[0x10]; 6990 6991 u8 reserved_at_20[0x10]; 6992 u8 op_mod[0x10]; 6993 6994 u8 reserved_at_40[0x20]; 6995 6996 u8 pg_access[0x1]; 6997 u8 mkey_umem_valid[0x1]; 6998 u8 reserved_at_62[0x1e]; 6999 7000 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7001 7002 u8 reserved_at_280[0x80]; 7003 7004 u8 translations_octword_actual_size[0x20]; 7005 7006 u8 reserved_at_320[0x560]; 7007 7008 u8 klm_pas_mtt[0][0x20]; 7009 }; 7010 7011 struct mlx5_ifc_create_flow_table_out_bits { 7012 u8 status[0x8]; 7013 u8 reserved_at_8[0x18]; 7014 7015 u8 syndrome[0x20]; 7016 7017 u8 reserved_at_40[0x8]; 7018 u8 table_id[0x18]; 7019 7020 u8 reserved_at_60[0x20]; 7021 }; 7022 7023 struct mlx5_ifc_flow_table_context_bits { 7024 u8 reformat_en[0x1]; 7025 u8 decap_en[0x1]; 7026 u8 reserved_at_2[0x2]; 7027 u8 table_miss_action[0x4]; 7028 u8 level[0x8]; 7029 u8 reserved_at_10[0x8]; 7030 u8 log_size[0x8]; 7031 7032 u8 reserved_at_20[0x8]; 7033 u8 table_miss_id[0x18]; 7034 7035 u8 reserved_at_40[0x8]; 7036 u8 lag_master_next_table_id[0x18]; 7037 7038 u8 reserved_at_60[0xe0]; 7039 }; 7040 7041 struct mlx5_ifc_create_flow_table_in_bits { 7042 u8 opcode[0x10]; 7043 u8 reserved_at_10[0x10]; 7044 7045 u8 reserved_at_20[0x10]; 7046 u8 op_mod[0x10]; 7047 7048 u8 other_vport[0x1]; 7049 u8 reserved_at_41[0xf]; 7050 u8 vport_number[0x10]; 7051 7052 u8 reserved_at_60[0x20]; 7053 7054 u8 table_type[0x8]; 7055 u8 reserved_at_88[0x18]; 7056 7057 u8 reserved_at_a0[0x20]; 7058 7059 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7060 }; 7061 7062 struct mlx5_ifc_create_flow_group_out_bits { 7063 u8 status[0x8]; 7064 u8 reserved_at_8[0x18]; 7065 7066 u8 syndrome[0x20]; 7067 7068 u8 reserved_at_40[0x8]; 7069 u8 group_id[0x18]; 7070 7071 u8 reserved_at_60[0x20]; 7072 }; 7073 7074 enum { 7075 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7076 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7077 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7078 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7079 }; 7080 7081 struct mlx5_ifc_create_flow_group_in_bits { 7082 u8 opcode[0x10]; 7083 u8 reserved_at_10[0x10]; 7084 7085 u8 reserved_at_20[0x10]; 7086 u8 op_mod[0x10]; 7087 7088 u8 other_vport[0x1]; 7089 u8 reserved_at_41[0xf]; 7090 u8 vport_number[0x10]; 7091 7092 u8 reserved_at_60[0x20]; 7093 7094 u8 table_type[0x8]; 7095 u8 reserved_at_88[0x18]; 7096 7097 u8 reserved_at_a0[0x8]; 7098 u8 table_id[0x18]; 7099 7100 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7101 7102 u8 reserved_at_c1[0x1f]; 7103 7104 u8 start_flow_index[0x20]; 7105 7106 u8 reserved_at_100[0x20]; 7107 7108 u8 end_flow_index[0x20]; 7109 7110 u8 reserved_at_140[0xa0]; 7111 7112 u8 reserved_at_1e0[0x18]; 7113 u8 match_criteria_enable[0x8]; 7114 7115 struct mlx5_ifc_fte_match_param_bits match_criteria; 7116 7117 u8 reserved_at_1200[0xe00]; 7118 }; 7119 7120 struct mlx5_ifc_create_eq_out_bits { 7121 u8 status[0x8]; 7122 u8 reserved_at_8[0x18]; 7123 7124 u8 syndrome[0x20]; 7125 7126 u8 reserved_at_40[0x18]; 7127 u8 eq_number[0x8]; 7128 7129 u8 reserved_at_60[0x20]; 7130 }; 7131 7132 struct mlx5_ifc_create_eq_in_bits { 7133 u8 opcode[0x10]; 7134 u8 reserved_at_10[0x10]; 7135 7136 u8 reserved_at_20[0x10]; 7137 u8 op_mod[0x10]; 7138 7139 u8 reserved_at_40[0x40]; 7140 7141 struct mlx5_ifc_eqc_bits eq_context_entry; 7142 7143 u8 reserved_at_280[0x40]; 7144 7145 u8 event_bitmask[0x40]; 7146 7147 u8 reserved_at_300[0x580]; 7148 7149 u8 pas[0][0x40]; 7150 }; 7151 7152 struct mlx5_ifc_create_dct_out_bits { 7153 u8 status[0x8]; 7154 u8 reserved_at_8[0x18]; 7155 7156 u8 syndrome[0x20]; 7157 7158 u8 reserved_at_40[0x8]; 7159 u8 dctn[0x18]; 7160 7161 u8 reserved_at_60[0x20]; 7162 }; 7163 7164 struct mlx5_ifc_create_dct_in_bits { 7165 u8 opcode[0x10]; 7166 u8 uid[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 reserved_at_40[0x40]; 7172 7173 struct mlx5_ifc_dctc_bits dct_context_entry; 7174 7175 u8 reserved_at_280[0x180]; 7176 }; 7177 7178 struct mlx5_ifc_create_cq_out_bits { 7179 u8 status[0x8]; 7180 u8 reserved_at_8[0x18]; 7181 7182 u8 syndrome[0x20]; 7183 7184 u8 reserved_at_40[0x8]; 7185 u8 cqn[0x18]; 7186 7187 u8 reserved_at_60[0x20]; 7188 }; 7189 7190 struct mlx5_ifc_create_cq_in_bits { 7191 u8 opcode[0x10]; 7192 u8 uid[0x10]; 7193 7194 u8 reserved_at_20[0x10]; 7195 u8 op_mod[0x10]; 7196 7197 u8 reserved_at_40[0x40]; 7198 7199 struct mlx5_ifc_cqc_bits cq_context; 7200 7201 u8 reserved_at_280[0x60]; 7202 7203 u8 cq_umem_valid[0x1]; 7204 u8 reserved_at_2e1[0x59f]; 7205 7206 u8 pas[0][0x40]; 7207 }; 7208 7209 struct mlx5_ifc_config_int_moderation_out_bits { 7210 u8 status[0x8]; 7211 u8 reserved_at_8[0x18]; 7212 7213 u8 syndrome[0x20]; 7214 7215 u8 reserved_at_40[0x4]; 7216 u8 min_delay[0xc]; 7217 u8 int_vector[0x10]; 7218 7219 u8 reserved_at_60[0x20]; 7220 }; 7221 7222 enum { 7223 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7224 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7225 }; 7226 7227 struct mlx5_ifc_config_int_moderation_in_bits { 7228 u8 opcode[0x10]; 7229 u8 reserved_at_10[0x10]; 7230 7231 u8 reserved_at_20[0x10]; 7232 u8 op_mod[0x10]; 7233 7234 u8 reserved_at_40[0x4]; 7235 u8 min_delay[0xc]; 7236 u8 int_vector[0x10]; 7237 7238 u8 reserved_at_60[0x20]; 7239 }; 7240 7241 struct mlx5_ifc_attach_to_mcg_out_bits { 7242 u8 status[0x8]; 7243 u8 reserved_at_8[0x18]; 7244 7245 u8 syndrome[0x20]; 7246 7247 u8 reserved_at_40[0x40]; 7248 }; 7249 7250 struct mlx5_ifc_attach_to_mcg_in_bits { 7251 u8 opcode[0x10]; 7252 u8 uid[0x10]; 7253 7254 u8 reserved_at_20[0x10]; 7255 u8 op_mod[0x10]; 7256 7257 u8 reserved_at_40[0x8]; 7258 u8 qpn[0x18]; 7259 7260 u8 reserved_at_60[0x20]; 7261 7262 u8 multicast_gid[16][0x8]; 7263 }; 7264 7265 struct mlx5_ifc_arm_xrq_out_bits { 7266 u8 status[0x8]; 7267 u8 reserved_at_8[0x18]; 7268 7269 u8 syndrome[0x20]; 7270 7271 u8 reserved_at_40[0x40]; 7272 }; 7273 7274 struct mlx5_ifc_arm_xrq_in_bits { 7275 u8 opcode[0x10]; 7276 u8 reserved_at_10[0x10]; 7277 7278 u8 reserved_at_20[0x10]; 7279 u8 op_mod[0x10]; 7280 7281 u8 reserved_at_40[0x8]; 7282 u8 xrqn[0x18]; 7283 7284 u8 reserved_at_60[0x10]; 7285 u8 lwm[0x10]; 7286 }; 7287 7288 struct mlx5_ifc_arm_xrc_srq_out_bits { 7289 u8 status[0x8]; 7290 u8 reserved_at_8[0x18]; 7291 7292 u8 syndrome[0x20]; 7293 7294 u8 reserved_at_40[0x40]; 7295 }; 7296 7297 enum { 7298 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7299 }; 7300 7301 struct mlx5_ifc_arm_xrc_srq_in_bits { 7302 u8 opcode[0x10]; 7303 u8 uid[0x10]; 7304 7305 u8 reserved_at_20[0x10]; 7306 u8 op_mod[0x10]; 7307 7308 u8 reserved_at_40[0x8]; 7309 u8 xrc_srqn[0x18]; 7310 7311 u8 reserved_at_60[0x10]; 7312 u8 lwm[0x10]; 7313 }; 7314 7315 struct mlx5_ifc_arm_rq_out_bits { 7316 u8 status[0x8]; 7317 u8 reserved_at_8[0x18]; 7318 7319 u8 syndrome[0x20]; 7320 7321 u8 reserved_at_40[0x40]; 7322 }; 7323 7324 enum { 7325 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7326 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7327 }; 7328 7329 struct mlx5_ifc_arm_rq_in_bits { 7330 u8 opcode[0x10]; 7331 u8 uid[0x10]; 7332 7333 u8 reserved_at_20[0x10]; 7334 u8 op_mod[0x10]; 7335 7336 u8 reserved_at_40[0x8]; 7337 u8 srq_number[0x18]; 7338 7339 u8 reserved_at_60[0x10]; 7340 u8 lwm[0x10]; 7341 }; 7342 7343 struct mlx5_ifc_arm_dct_out_bits { 7344 u8 status[0x8]; 7345 u8 reserved_at_8[0x18]; 7346 7347 u8 syndrome[0x20]; 7348 7349 u8 reserved_at_40[0x40]; 7350 }; 7351 7352 struct mlx5_ifc_arm_dct_in_bits { 7353 u8 opcode[0x10]; 7354 u8 reserved_at_10[0x10]; 7355 7356 u8 reserved_at_20[0x10]; 7357 u8 op_mod[0x10]; 7358 7359 u8 reserved_at_40[0x8]; 7360 u8 dct_number[0x18]; 7361 7362 u8 reserved_at_60[0x20]; 7363 }; 7364 7365 struct mlx5_ifc_alloc_xrcd_out_bits { 7366 u8 status[0x8]; 7367 u8 reserved_at_8[0x18]; 7368 7369 u8 syndrome[0x20]; 7370 7371 u8 reserved_at_40[0x8]; 7372 u8 xrcd[0x18]; 7373 7374 u8 reserved_at_60[0x20]; 7375 }; 7376 7377 struct mlx5_ifc_alloc_xrcd_in_bits { 7378 u8 opcode[0x10]; 7379 u8 uid[0x10]; 7380 7381 u8 reserved_at_20[0x10]; 7382 u8 op_mod[0x10]; 7383 7384 u8 reserved_at_40[0x40]; 7385 }; 7386 7387 struct mlx5_ifc_alloc_uar_out_bits { 7388 u8 status[0x8]; 7389 u8 reserved_at_8[0x18]; 7390 7391 u8 syndrome[0x20]; 7392 7393 u8 reserved_at_40[0x8]; 7394 u8 uar[0x18]; 7395 7396 u8 reserved_at_60[0x20]; 7397 }; 7398 7399 struct mlx5_ifc_alloc_uar_in_bits { 7400 u8 opcode[0x10]; 7401 u8 reserved_at_10[0x10]; 7402 7403 u8 reserved_at_20[0x10]; 7404 u8 op_mod[0x10]; 7405 7406 u8 reserved_at_40[0x40]; 7407 }; 7408 7409 struct mlx5_ifc_alloc_transport_domain_out_bits { 7410 u8 status[0x8]; 7411 u8 reserved_at_8[0x18]; 7412 7413 u8 syndrome[0x20]; 7414 7415 u8 reserved_at_40[0x8]; 7416 u8 transport_domain[0x18]; 7417 7418 u8 reserved_at_60[0x20]; 7419 }; 7420 7421 struct mlx5_ifc_alloc_transport_domain_in_bits { 7422 u8 opcode[0x10]; 7423 u8 reserved_at_10[0x10]; 7424 7425 u8 reserved_at_20[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 reserved_at_40[0x40]; 7429 }; 7430 7431 struct mlx5_ifc_alloc_q_counter_out_bits { 7432 u8 status[0x8]; 7433 u8 reserved_at_8[0x18]; 7434 7435 u8 syndrome[0x20]; 7436 7437 u8 reserved_at_40[0x18]; 7438 u8 counter_set_id[0x8]; 7439 7440 u8 reserved_at_60[0x20]; 7441 }; 7442 7443 struct mlx5_ifc_alloc_q_counter_in_bits { 7444 u8 opcode[0x10]; 7445 u8 reserved_at_10[0x10]; 7446 7447 u8 reserved_at_20[0x10]; 7448 u8 op_mod[0x10]; 7449 7450 u8 reserved_at_40[0x40]; 7451 }; 7452 7453 struct mlx5_ifc_alloc_pd_out_bits { 7454 u8 status[0x8]; 7455 u8 reserved_at_8[0x18]; 7456 7457 u8 syndrome[0x20]; 7458 7459 u8 reserved_at_40[0x8]; 7460 u8 pd[0x18]; 7461 7462 u8 reserved_at_60[0x20]; 7463 }; 7464 7465 struct mlx5_ifc_alloc_pd_in_bits { 7466 u8 opcode[0x10]; 7467 u8 uid[0x10]; 7468 7469 u8 reserved_at_20[0x10]; 7470 u8 op_mod[0x10]; 7471 7472 u8 reserved_at_40[0x40]; 7473 }; 7474 7475 struct mlx5_ifc_alloc_flow_counter_out_bits { 7476 u8 status[0x8]; 7477 u8 reserved_at_8[0x18]; 7478 7479 u8 syndrome[0x20]; 7480 7481 u8 flow_counter_id[0x20]; 7482 7483 u8 reserved_at_60[0x20]; 7484 }; 7485 7486 struct mlx5_ifc_alloc_flow_counter_in_bits { 7487 u8 opcode[0x10]; 7488 u8 reserved_at_10[0x10]; 7489 7490 u8 reserved_at_20[0x10]; 7491 u8 op_mod[0x10]; 7492 7493 u8 reserved_at_40[0x40]; 7494 }; 7495 7496 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7497 u8 status[0x8]; 7498 u8 reserved_at_8[0x18]; 7499 7500 u8 syndrome[0x20]; 7501 7502 u8 reserved_at_40[0x40]; 7503 }; 7504 7505 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7506 u8 opcode[0x10]; 7507 u8 reserved_at_10[0x10]; 7508 7509 u8 reserved_at_20[0x10]; 7510 u8 op_mod[0x10]; 7511 7512 u8 reserved_at_40[0x20]; 7513 7514 u8 reserved_at_60[0x10]; 7515 u8 vxlan_udp_port[0x10]; 7516 }; 7517 7518 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7519 u8 status[0x8]; 7520 u8 reserved_at_8[0x18]; 7521 7522 u8 syndrome[0x20]; 7523 7524 u8 reserved_at_40[0x40]; 7525 }; 7526 7527 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7528 u8 opcode[0x10]; 7529 u8 reserved_at_10[0x10]; 7530 7531 u8 reserved_at_20[0x10]; 7532 u8 op_mod[0x10]; 7533 7534 u8 reserved_at_40[0x10]; 7535 u8 rate_limit_index[0x10]; 7536 7537 u8 reserved_at_60[0x20]; 7538 7539 u8 rate_limit[0x20]; 7540 7541 u8 burst_upper_bound[0x20]; 7542 7543 u8 reserved_at_c0[0x10]; 7544 u8 typical_packet_size[0x10]; 7545 7546 u8 reserved_at_e0[0x120]; 7547 }; 7548 7549 struct mlx5_ifc_access_register_out_bits { 7550 u8 status[0x8]; 7551 u8 reserved_at_8[0x18]; 7552 7553 u8 syndrome[0x20]; 7554 7555 u8 reserved_at_40[0x40]; 7556 7557 u8 register_data[0][0x20]; 7558 }; 7559 7560 enum { 7561 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7562 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7563 }; 7564 7565 struct mlx5_ifc_access_register_in_bits { 7566 u8 opcode[0x10]; 7567 u8 reserved_at_10[0x10]; 7568 7569 u8 reserved_at_20[0x10]; 7570 u8 op_mod[0x10]; 7571 7572 u8 reserved_at_40[0x10]; 7573 u8 register_id[0x10]; 7574 7575 u8 argument[0x20]; 7576 7577 u8 register_data[0][0x20]; 7578 }; 7579 7580 struct mlx5_ifc_sltp_reg_bits { 7581 u8 status[0x4]; 7582 u8 version[0x4]; 7583 u8 local_port[0x8]; 7584 u8 pnat[0x2]; 7585 u8 reserved_at_12[0x2]; 7586 u8 lane[0x4]; 7587 u8 reserved_at_18[0x8]; 7588 7589 u8 reserved_at_20[0x20]; 7590 7591 u8 reserved_at_40[0x7]; 7592 u8 polarity[0x1]; 7593 u8 ob_tap0[0x8]; 7594 u8 ob_tap1[0x8]; 7595 u8 ob_tap2[0x8]; 7596 7597 u8 reserved_at_60[0xc]; 7598 u8 ob_preemp_mode[0x4]; 7599 u8 ob_reg[0x8]; 7600 u8 ob_bias[0x8]; 7601 7602 u8 reserved_at_80[0x20]; 7603 }; 7604 7605 struct mlx5_ifc_slrg_reg_bits { 7606 u8 status[0x4]; 7607 u8 version[0x4]; 7608 u8 local_port[0x8]; 7609 u8 pnat[0x2]; 7610 u8 reserved_at_12[0x2]; 7611 u8 lane[0x4]; 7612 u8 reserved_at_18[0x8]; 7613 7614 u8 time_to_link_up[0x10]; 7615 u8 reserved_at_30[0xc]; 7616 u8 grade_lane_speed[0x4]; 7617 7618 u8 grade_version[0x8]; 7619 u8 grade[0x18]; 7620 7621 u8 reserved_at_60[0x4]; 7622 u8 height_grade_type[0x4]; 7623 u8 height_grade[0x18]; 7624 7625 u8 height_dz[0x10]; 7626 u8 height_dv[0x10]; 7627 7628 u8 reserved_at_a0[0x10]; 7629 u8 height_sigma[0x10]; 7630 7631 u8 reserved_at_c0[0x20]; 7632 7633 u8 reserved_at_e0[0x4]; 7634 u8 phase_grade_type[0x4]; 7635 u8 phase_grade[0x18]; 7636 7637 u8 reserved_at_100[0x8]; 7638 u8 phase_eo_pos[0x8]; 7639 u8 reserved_at_110[0x8]; 7640 u8 phase_eo_neg[0x8]; 7641 7642 u8 ffe_set_tested[0x10]; 7643 u8 test_errors_per_lane[0x10]; 7644 }; 7645 7646 struct mlx5_ifc_pvlc_reg_bits { 7647 u8 reserved_at_0[0x8]; 7648 u8 local_port[0x8]; 7649 u8 reserved_at_10[0x10]; 7650 7651 u8 reserved_at_20[0x1c]; 7652 u8 vl_hw_cap[0x4]; 7653 7654 u8 reserved_at_40[0x1c]; 7655 u8 vl_admin[0x4]; 7656 7657 u8 reserved_at_60[0x1c]; 7658 u8 vl_operational[0x4]; 7659 }; 7660 7661 struct mlx5_ifc_pude_reg_bits { 7662 u8 swid[0x8]; 7663 u8 local_port[0x8]; 7664 u8 reserved_at_10[0x4]; 7665 u8 admin_status[0x4]; 7666 u8 reserved_at_18[0x4]; 7667 u8 oper_status[0x4]; 7668 7669 u8 reserved_at_20[0x60]; 7670 }; 7671 7672 struct mlx5_ifc_ptys_reg_bits { 7673 u8 reserved_at_0[0x1]; 7674 u8 an_disable_admin[0x1]; 7675 u8 an_disable_cap[0x1]; 7676 u8 reserved_at_3[0x5]; 7677 u8 local_port[0x8]; 7678 u8 reserved_at_10[0xd]; 7679 u8 proto_mask[0x3]; 7680 7681 u8 an_status[0x4]; 7682 u8 reserved_at_24[0x3c]; 7683 7684 u8 eth_proto_capability[0x20]; 7685 7686 u8 ib_link_width_capability[0x10]; 7687 u8 ib_proto_capability[0x10]; 7688 7689 u8 reserved_at_a0[0x20]; 7690 7691 u8 eth_proto_admin[0x20]; 7692 7693 u8 ib_link_width_admin[0x10]; 7694 u8 ib_proto_admin[0x10]; 7695 7696 u8 reserved_at_100[0x20]; 7697 7698 u8 eth_proto_oper[0x20]; 7699 7700 u8 ib_link_width_oper[0x10]; 7701 u8 ib_proto_oper[0x10]; 7702 7703 u8 reserved_at_160[0x1c]; 7704 u8 connector_type[0x4]; 7705 7706 u8 eth_proto_lp_advertise[0x20]; 7707 7708 u8 reserved_at_1a0[0x60]; 7709 }; 7710 7711 struct mlx5_ifc_mlcr_reg_bits { 7712 u8 reserved_at_0[0x8]; 7713 u8 local_port[0x8]; 7714 u8 reserved_at_10[0x20]; 7715 7716 u8 beacon_duration[0x10]; 7717 u8 reserved_at_40[0x10]; 7718 7719 u8 beacon_remain[0x10]; 7720 }; 7721 7722 struct mlx5_ifc_ptas_reg_bits { 7723 u8 reserved_at_0[0x20]; 7724 7725 u8 algorithm_options[0x10]; 7726 u8 reserved_at_30[0x4]; 7727 u8 repetitions_mode[0x4]; 7728 u8 num_of_repetitions[0x8]; 7729 7730 u8 grade_version[0x8]; 7731 u8 height_grade_type[0x4]; 7732 u8 phase_grade_type[0x4]; 7733 u8 height_grade_weight[0x8]; 7734 u8 phase_grade_weight[0x8]; 7735 7736 u8 gisim_measure_bits[0x10]; 7737 u8 adaptive_tap_measure_bits[0x10]; 7738 7739 u8 ber_bath_high_error_threshold[0x10]; 7740 u8 ber_bath_mid_error_threshold[0x10]; 7741 7742 u8 ber_bath_low_error_threshold[0x10]; 7743 u8 one_ratio_high_threshold[0x10]; 7744 7745 u8 one_ratio_high_mid_threshold[0x10]; 7746 u8 one_ratio_low_mid_threshold[0x10]; 7747 7748 u8 one_ratio_low_threshold[0x10]; 7749 u8 ndeo_error_threshold[0x10]; 7750 7751 u8 mixer_offset_step_size[0x10]; 7752 u8 reserved_at_110[0x8]; 7753 u8 mix90_phase_for_voltage_bath[0x8]; 7754 7755 u8 mixer_offset_start[0x10]; 7756 u8 mixer_offset_end[0x10]; 7757 7758 u8 reserved_at_140[0x15]; 7759 u8 ber_test_time[0xb]; 7760 }; 7761 7762 struct mlx5_ifc_pspa_reg_bits { 7763 u8 swid[0x8]; 7764 u8 local_port[0x8]; 7765 u8 sub_port[0x8]; 7766 u8 reserved_at_18[0x8]; 7767 7768 u8 reserved_at_20[0x20]; 7769 }; 7770 7771 struct mlx5_ifc_pqdr_reg_bits { 7772 u8 reserved_at_0[0x8]; 7773 u8 local_port[0x8]; 7774 u8 reserved_at_10[0x5]; 7775 u8 prio[0x3]; 7776 u8 reserved_at_18[0x6]; 7777 u8 mode[0x2]; 7778 7779 u8 reserved_at_20[0x20]; 7780 7781 u8 reserved_at_40[0x10]; 7782 u8 min_threshold[0x10]; 7783 7784 u8 reserved_at_60[0x10]; 7785 u8 max_threshold[0x10]; 7786 7787 u8 reserved_at_80[0x10]; 7788 u8 mark_probability_denominator[0x10]; 7789 7790 u8 reserved_at_a0[0x60]; 7791 }; 7792 7793 struct mlx5_ifc_ppsc_reg_bits { 7794 u8 reserved_at_0[0x8]; 7795 u8 local_port[0x8]; 7796 u8 reserved_at_10[0x10]; 7797 7798 u8 reserved_at_20[0x60]; 7799 7800 u8 reserved_at_80[0x1c]; 7801 u8 wrps_admin[0x4]; 7802 7803 u8 reserved_at_a0[0x1c]; 7804 u8 wrps_status[0x4]; 7805 7806 u8 reserved_at_c0[0x8]; 7807 u8 up_threshold[0x8]; 7808 u8 reserved_at_d0[0x8]; 7809 u8 down_threshold[0x8]; 7810 7811 u8 reserved_at_e0[0x20]; 7812 7813 u8 reserved_at_100[0x1c]; 7814 u8 srps_admin[0x4]; 7815 7816 u8 reserved_at_120[0x1c]; 7817 u8 srps_status[0x4]; 7818 7819 u8 reserved_at_140[0x40]; 7820 }; 7821 7822 struct mlx5_ifc_pplr_reg_bits { 7823 u8 reserved_at_0[0x8]; 7824 u8 local_port[0x8]; 7825 u8 reserved_at_10[0x10]; 7826 7827 u8 reserved_at_20[0x8]; 7828 u8 lb_cap[0x8]; 7829 u8 reserved_at_30[0x8]; 7830 u8 lb_en[0x8]; 7831 }; 7832 7833 struct mlx5_ifc_pplm_reg_bits { 7834 u8 reserved_at_0[0x8]; 7835 u8 local_port[0x8]; 7836 u8 reserved_at_10[0x10]; 7837 7838 u8 reserved_at_20[0x20]; 7839 7840 u8 port_profile_mode[0x8]; 7841 u8 static_port_profile[0x8]; 7842 u8 active_port_profile[0x8]; 7843 u8 reserved_at_58[0x8]; 7844 7845 u8 retransmission_active[0x8]; 7846 u8 fec_mode_active[0x18]; 7847 7848 u8 rs_fec_correction_bypass_cap[0x4]; 7849 u8 reserved_at_84[0x8]; 7850 u8 fec_override_cap_56g[0x4]; 7851 u8 fec_override_cap_100g[0x4]; 7852 u8 fec_override_cap_50g[0x4]; 7853 u8 fec_override_cap_25g[0x4]; 7854 u8 fec_override_cap_10g_40g[0x4]; 7855 7856 u8 rs_fec_correction_bypass_admin[0x4]; 7857 u8 reserved_at_a4[0x8]; 7858 u8 fec_override_admin_56g[0x4]; 7859 u8 fec_override_admin_100g[0x4]; 7860 u8 fec_override_admin_50g[0x4]; 7861 u8 fec_override_admin_25g[0x4]; 7862 u8 fec_override_admin_10g_40g[0x4]; 7863 }; 7864 7865 struct mlx5_ifc_ppcnt_reg_bits { 7866 u8 swid[0x8]; 7867 u8 local_port[0x8]; 7868 u8 pnat[0x2]; 7869 u8 reserved_at_12[0x8]; 7870 u8 grp[0x6]; 7871 7872 u8 clr[0x1]; 7873 u8 reserved_at_21[0x1c]; 7874 u8 prio_tc[0x3]; 7875 7876 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7877 }; 7878 7879 struct mlx5_ifc_mpcnt_reg_bits { 7880 u8 reserved_at_0[0x8]; 7881 u8 pcie_index[0x8]; 7882 u8 reserved_at_10[0xa]; 7883 u8 grp[0x6]; 7884 7885 u8 clr[0x1]; 7886 u8 reserved_at_21[0x1f]; 7887 7888 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7889 }; 7890 7891 struct mlx5_ifc_ppad_reg_bits { 7892 u8 reserved_at_0[0x3]; 7893 u8 single_mac[0x1]; 7894 u8 reserved_at_4[0x4]; 7895 u8 local_port[0x8]; 7896 u8 mac_47_32[0x10]; 7897 7898 u8 mac_31_0[0x20]; 7899 7900 u8 reserved_at_40[0x40]; 7901 }; 7902 7903 struct mlx5_ifc_pmtu_reg_bits { 7904 u8 reserved_at_0[0x8]; 7905 u8 local_port[0x8]; 7906 u8 reserved_at_10[0x10]; 7907 7908 u8 max_mtu[0x10]; 7909 u8 reserved_at_30[0x10]; 7910 7911 u8 admin_mtu[0x10]; 7912 u8 reserved_at_50[0x10]; 7913 7914 u8 oper_mtu[0x10]; 7915 u8 reserved_at_70[0x10]; 7916 }; 7917 7918 struct mlx5_ifc_pmpr_reg_bits { 7919 u8 reserved_at_0[0x8]; 7920 u8 module[0x8]; 7921 u8 reserved_at_10[0x10]; 7922 7923 u8 reserved_at_20[0x18]; 7924 u8 attenuation_5g[0x8]; 7925 7926 u8 reserved_at_40[0x18]; 7927 u8 attenuation_7g[0x8]; 7928 7929 u8 reserved_at_60[0x18]; 7930 u8 attenuation_12g[0x8]; 7931 }; 7932 7933 struct mlx5_ifc_pmpe_reg_bits { 7934 u8 reserved_at_0[0x8]; 7935 u8 module[0x8]; 7936 u8 reserved_at_10[0xc]; 7937 u8 module_status[0x4]; 7938 7939 u8 reserved_at_20[0x60]; 7940 }; 7941 7942 struct mlx5_ifc_pmpc_reg_bits { 7943 u8 module_state_updated[32][0x8]; 7944 }; 7945 7946 struct mlx5_ifc_pmlpn_reg_bits { 7947 u8 reserved_at_0[0x4]; 7948 u8 mlpn_status[0x4]; 7949 u8 local_port[0x8]; 7950 u8 reserved_at_10[0x10]; 7951 7952 u8 e[0x1]; 7953 u8 reserved_at_21[0x1f]; 7954 }; 7955 7956 struct mlx5_ifc_pmlp_reg_bits { 7957 u8 rxtx[0x1]; 7958 u8 reserved_at_1[0x7]; 7959 u8 local_port[0x8]; 7960 u8 reserved_at_10[0x8]; 7961 u8 width[0x8]; 7962 7963 u8 lane0_module_mapping[0x20]; 7964 7965 u8 lane1_module_mapping[0x20]; 7966 7967 u8 lane2_module_mapping[0x20]; 7968 7969 u8 lane3_module_mapping[0x20]; 7970 7971 u8 reserved_at_a0[0x160]; 7972 }; 7973 7974 struct mlx5_ifc_pmaos_reg_bits { 7975 u8 reserved_at_0[0x8]; 7976 u8 module[0x8]; 7977 u8 reserved_at_10[0x4]; 7978 u8 admin_status[0x4]; 7979 u8 reserved_at_18[0x4]; 7980 u8 oper_status[0x4]; 7981 7982 u8 ase[0x1]; 7983 u8 ee[0x1]; 7984 u8 reserved_at_22[0x1c]; 7985 u8 e[0x2]; 7986 7987 u8 reserved_at_40[0x40]; 7988 }; 7989 7990 struct mlx5_ifc_plpc_reg_bits { 7991 u8 reserved_at_0[0x4]; 7992 u8 profile_id[0xc]; 7993 u8 reserved_at_10[0x4]; 7994 u8 proto_mask[0x4]; 7995 u8 reserved_at_18[0x8]; 7996 7997 u8 reserved_at_20[0x10]; 7998 u8 lane_speed[0x10]; 7999 8000 u8 reserved_at_40[0x17]; 8001 u8 lpbf[0x1]; 8002 u8 fec_mode_policy[0x8]; 8003 8004 u8 retransmission_capability[0x8]; 8005 u8 fec_mode_capability[0x18]; 8006 8007 u8 retransmission_support_admin[0x8]; 8008 u8 fec_mode_support_admin[0x18]; 8009 8010 u8 retransmission_request_admin[0x8]; 8011 u8 fec_mode_request_admin[0x18]; 8012 8013 u8 reserved_at_c0[0x80]; 8014 }; 8015 8016 struct mlx5_ifc_plib_reg_bits { 8017 u8 reserved_at_0[0x8]; 8018 u8 local_port[0x8]; 8019 u8 reserved_at_10[0x8]; 8020 u8 ib_port[0x8]; 8021 8022 u8 reserved_at_20[0x60]; 8023 }; 8024 8025 struct mlx5_ifc_plbf_reg_bits { 8026 u8 reserved_at_0[0x8]; 8027 u8 local_port[0x8]; 8028 u8 reserved_at_10[0xd]; 8029 u8 lbf_mode[0x3]; 8030 8031 u8 reserved_at_20[0x20]; 8032 }; 8033 8034 struct mlx5_ifc_pipg_reg_bits { 8035 u8 reserved_at_0[0x8]; 8036 u8 local_port[0x8]; 8037 u8 reserved_at_10[0x10]; 8038 8039 u8 dic[0x1]; 8040 u8 reserved_at_21[0x19]; 8041 u8 ipg[0x4]; 8042 u8 reserved_at_3e[0x2]; 8043 }; 8044 8045 struct mlx5_ifc_pifr_reg_bits { 8046 u8 reserved_at_0[0x8]; 8047 u8 local_port[0x8]; 8048 u8 reserved_at_10[0x10]; 8049 8050 u8 reserved_at_20[0xe0]; 8051 8052 u8 port_filter[8][0x20]; 8053 8054 u8 port_filter_update_en[8][0x20]; 8055 }; 8056 8057 struct mlx5_ifc_pfcc_reg_bits { 8058 u8 reserved_at_0[0x8]; 8059 u8 local_port[0x8]; 8060 u8 reserved_at_10[0xb]; 8061 u8 ppan_mask_n[0x1]; 8062 u8 minor_stall_mask[0x1]; 8063 u8 critical_stall_mask[0x1]; 8064 u8 reserved_at_1e[0x2]; 8065 8066 u8 ppan[0x4]; 8067 u8 reserved_at_24[0x4]; 8068 u8 prio_mask_tx[0x8]; 8069 u8 reserved_at_30[0x8]; 8070 u8 prio_mask_rx[0x8]; 8071 8072 u8 pptx[0x1]; 8073 u8 aptx[0x1]; 8074 u8 pptx_mask_n[0x1]; 8075 u8 reserved_at_43[0x5]; 8076 u8 pfctx[0x8]; 8077 u8 reserved_at_50[0x10]; 8078 8079 u8 pprx[0x1]; 8080 u8 aprx[0x1]; 8081 u8 pprx_mask_n[0x1]; 8082 u8 reserved_at_63[0x5]; 8083 u8 pfcrx[0x8]; 8084 u8 reserved_at_70[0x10]; 8085 8086 u8 device_stall_minor_watermark[0x10]; 8087 u8 device_stall_critical_watermark[0x10]; 8088 8089 u8 reserved_at_a0[0x60]; 8090 }; 8091 8092 struct mlx5_ifc_pelc_reg_bits { 8093 u8 op[0x4]; 8094 u8 reserved_at_4[0x4]; 8095 u8 local_port[0x8]; 8096 u8 reserved_at_10[0x10]; 8097 8098 u8 op_admin[0x8]; 8099 u8 op_capability[0x8]; 8100 u8 op_request[0x8]; 8101 u8 op_active[0x8]; 8102 8103 u8 admin[0x40]; 8104 8105 u8 capability[0x40]; 8106 8107 u8 request[0x40]; 8108 8109 u8 active[0x40]; 8110 8111 u8 reserved_at_140[0x80]; 8112 }; 8113 8114 struct mlx5_ifc_peir_reg_bits { 8115 u8 reserved_at_0[0x8]; 8116 u8 local_port[0x8]; 8117 u8 reserved_at_10[0x10]; 8118 8119 u8 reserved_at_20[0xc]; 8120 u8 error_count[0x4]; 8121 u8 reserved_at_30[0x10]; 8122 8123 u8 reserved_at_40[0xc]; 8124 u8 lane[0x4]; 8125 u8 reserved_at_50[0x8]; 8126 u8 error_type[0x8]; 8127 }; 8128 8129 struct mlx5_ifc_mpegc_reg_bits { 8130 u8 reserved_at_0[0x30]; 8131 u8 field_select[0x10]; 8132 8133 u8 tx_overflow_sense[0x1]; 8134 u8 mark_cqe[0x1]; 8135 u8 mark_cnp[0x1]; 8136 u8 reserved_at_43[0x1b]; 8137 u8 tx_lossy_overflow_oper[0x2]; 8138 8139 u8 reserved_at_60[0x100]; 8140 }; 8141 8142 struct mlx5_ifc_pcam_enhanced_features_bits { 8143 u8 reserved_at_0[0x6d]; 8144 u8 rx_icrc_encapsulated_counter[0x1]; 8145 u8 reserved_at_6e[0x8]; 8146 u8 pfcc_mask[0x1]; 8147 u8 reserved_at_77[0x3]; 8148 u8 per_lane_error_counters[0x1]; 8149 u8 rx_buffer_fullness_counters[0x1]; 8150 u8 ptys_connector_type[0x1]; 8151 u8 reserved_at_7d[0x1]; 8152 u8 ppcnt_discard_group[0x1]; 8153 u8 ppcnt_statistical_group[0x1]; 8154 }; 8155 8156 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8157 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8158 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8159 8160 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8161 u8 pplm[0x1]; 8162 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8163 8164 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8165 u8 pbmc[0x1]; 8166 u8 pptb[0x1]; 8167 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8168 }; 8169 8170 struct mlx5_ifc_pcam_reg_bits { 8171 u8 reserved_at_0[0x8]; 8172 u8 feature_group[0x8]; 8173 u8 reserved_at_10[0x8]; 8174 u8 access_reg_group[0x8]; 8175 8176 u8 reserved_at_20[0x20]; 8177 8178 union { 8179 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8180 u8 reserved_at_0[0x80]; 8181 } port_access_reg_cap_mask; 8182 8183 u8 reserved_at_c0[0x80]; 8184 8185 union { 8186 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8187 u8 reserved_at_0[0x80]; 8188 } feature_cap_mask; 8189 8190 u8 reserved_at_1c0[0xc0]; 8191 }; 8192 8193 struct mlx5_ifc_mcam_enhanced_features_bits { 8194 u8 reserved_at_0[0x74]; 8195 u8 mark_tx_action_cnp[0x1]; 8196 u8 mark_tx_action_cqe[0x1]; 8197 u8 dynamic_tx_overflow[0x1]; 8198 u8 reserved_at_77[0x4]; 8199 u8 pcie_outbound_stalled[0x1]; 8200 u8 tx_overflow_buffer_pkt[0x1]; 8201 u8 mtpps_enh_out_per_adj[0x1]; 8202 u8 mtpps_fs[0x1]; 8203 u8 pcie_performance_group[0x1]; 8204 }; 8205 8206 struct mlx5_ifc_mcam_access_reg_bits { 8207 u8 reserved_at_0[0x1c]; 8208 u8 mcda[0x1]; 8209 u8 mcc[0x1]; 8210 u8 mcqi[0x1]; 8211 u8 reserved_at_1f[0x1]; 8212 8213 u8 regs_95_to_87[0x9]; 8214 u8 mpegc[0x1]; 8215 u8 regs_85_to_68[0x12]; 8216 u8 tracer_registers[0x4]; 8217 8218 u8 regs_63_to_32[0x20]; 8219 u8 regs_31_to_0[0x20]; 8220 }; 8221 8222 struct mlx5_ifc_mcam_reg_bits { 8223 u8 reserved_at_0[0x8]; 8224 u8 feature_group[0x8]; 8225 u8 reserved_at_10[0x8]; 8226 u8 access_reg_group[0x8]; 8227 8228 u8 reserved_at_20[0x20]; 8229 8230 union { 8231 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8232 u8 reserved_at_0[0x80]; 8233 } mng_access_reg_cap_mask; 8234 8235 u8 reserved_at_c0[0x80]; 8236 8237 union { 8238 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8239 u8 reserved_at_0[0x80]; 8240 } mng_feature_cap_mask; 8241 8242 u8 reserved_at_1c0[0x80]; 8243 }; 8244 8245 struct mlx5_ifc_qcam_access_reg_cap_mask { 8246 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8247 u8 qpdpm[0x1]; 8248 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8249 u8 qdpm[0x1]; 8250 u8 qpts[0x1]; 8251 u8 qcap[0x1]; 8252 u8 qcam_access_reg_cap_mask_0[0x1]; 8253 }; 8254 8255 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8256 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8257 u8 qpts_trust_both[0x1]; 8258 }; 8259 8260 struct mlx5_ifc_qcam_reg_bits { 8261 u8 reserved_at_0[0x8]; 8262 u8 feature_group[0x8]; 8263 u8 reserved_at_10[0x8]; 8264 u8 access_reg_group[0x8]; 8265 u8 reserved_at_20[0x20]; 8266 8267 union { 8268 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8269 u8 reserved_at_0[0x80]; 8270 } qos_access_reg_cap_mask; 8271 8272 u8 reserved_at_c0[0x80]; 8273 8274 union { 8275 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8276 u8 reserved_at_0[0x80]; 8277 } qos_feature_cap_mask; 8278 8279 u8 reserved_at_1c0[0x80]; 8280 }; 8281 8282 struct mlx5_ifc_pcap_reg_bits { 8283 u8 reserved_at_0[0x8]; 8284 u8 local_port[0x8]; 8285 u8 reserved_at_10[0x10]; 8286 8287 u8 port_capability_mask[4][0x20]; 8288 }; 8289 8290 struct mlx5_ifc_paos_reg_bits { 8291 u8 swid[0x8]; 8292 u8 local_port[0x8]; 8293 u8 reserved_at_10[0x4]; 8294 u8 admin_status[0x4]; 8295 u8 reserved_at_18[0x4]; 8296 u8 oper_status[0x4]; 8297 8298 u8 ase[0x1]; 8299 u8 ee[0x1]; 8300 u8 reserved_at_22[0x1c]; 8301 u8 e[0x2]; 8302 8303 u8 reserved_at_40[0x40]; 8304 }; 8305 8306 struct mlx5_ifc_pamp_reg_bits { 8307 u8 reserved_at_0[0x8]; 8308 u8 opamp_group[0x8]; 8309 u8 reserved_at_10[0xc]; 8310 u8 opamp_group_type[0x4]; 8311 8312 u8 start_index[0x10]; 8313 u8 reserved_at_30[0x4]; 8314 u8 num_of_indices[0xc]; 8315 8316 u8 index_data[18][0x10]; 8317 }; 8318 8319 struct mlx5_ifc_pcmr_reg_bits { 8320 u8 reserved_at_0[0x8]; 8321 u8 local_port[0x8]; 8322 u8 reserved_at_10[0x2e]; 8323 u8 fcs_cap[0x1]; 8324 u8 reserved_at_3f[0x1f]; 8325 u8 fcs_chk[0x1]; 8326 u8 reserved_at_5f[0x1]; 8327 }; 8328 8329 struct mlx5_ifc_lane_2_module_mapping_bits { 8330 u8 reserved_at_0[0x6]; 8331 u8 rx_lane[0x2]; 8332 u8 reserved_at_8[0x6]; 8333 u8 tx_lane[0x2]; 8334 u8 reserved_at_10[0x8]; 8335 u8 module[0x8]; 8336 }; 8337 8338 struct mlx5_ifc_bufferx_reg_bits { 8339 u8 reserved_at_0[0x6]; 8340 u8 lossy[0x1]; 8341 u8 epsb[0x1]; 8342 u8 reserved_at_8[0xc]; 8343 u8 size[0xc]; 8344 8345 u8 xoff_threshold[0x10]; 8346 u8 xon_threshold[0x10]; 8347 }; 8348 8349 struct mlx5_ifc_set_node_in_bits { 8350 u8 node_description[64][0x8]; 8351 }; 8352 8353 struct mlx5_ifc_register_power_settings_bits { 8354 u8 reserved_at_0[0x18]; 8355 u8 power_settings_level[0x8]; 8356 8357 u8 reserved_at_20[0x60]; 8358 }; 8359 8360 struct mlx5_ifc_register_host_endianness_bits { 8361 u8 he[0x1]; 8362 u8 reserved_at_1[0x1f]; 8363 8364 u8 reserved_at_20[0x60]; 8365 }; 8366 8367 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8368 u8 reserved_at_0[0x20]; 8369 8370 u8 mkey[0x20]; 8371 8372 u8 addressh_63_32[0x20]; 8373 8374 u8 addressl_31_0[0x20]; 8375 }; 8376 8377 struct mlx5_ifc_ud_adrs_vector_bits { 8378 u8 dc_key[0x40]; 8379 8380 u8 ext[0x1]; 8381 u8 reserved_at_41[0x7]; 8382 u8 destination_qp_dct[0x18]; 8383 8384 u8 static_rate[0x4]; 8385 u8 sl_eth_prio[0x4]; 8386 u8 fl[0x1]; 8387 u8 mlid[0x7]; 8388 u8 rlid_udp_sport[0x10]; 8389 8390 u8 reserved_at_80[0x20]; 8391 8392 u8 rmac_47_16[0x20]; 8393 8394 u8 rmac_15_0[0x10]; 8395 u8 tclass[0x8]; 8396 u8 hop_limit[0x8]; 8397 8398 u8 reserved_at_e0[0x1]; 8399 u8 grh[0x1]; 8400 u8 reserved_at_e2[0x2]; 8401 u8 src_addr_index[0x8]; 8402 u8 flow_label[0x14]; 8403 8404 u8 rgid_rip[16][0x8]; 8405 }; 8406 8407 struct mlx5_ifc_pages_req_event_bits { 8408 u8 reserved_at_0[0x10]; 8409 u8 function_id[0x10]; 8410 8411 u8 num_pages[0x20]; 8412 8413 u8 reserved_at_40[0xa0]; 8414 }; 8415 8416 struct mlx5_ifc_eqe_bits { 8417 u8 reserved_at_0[0x8]; 8418 u8 event_type[0x8]; 8419 u8 reserved_at_10[0x8]; 8420 u8 event_sub_type[0x8]; 8421 8422 u8 reserved_at_20[0xe0]; 8423 8424 union mlx5_ifc_event_auto_bits event_data; 8425 8426 u8 reserved_at_1e0[0x10]; 8427 u8 signature[0x8]; 8428 u8 reserved_at_1f8[0x7]; 8429 u8 owner[0x1]; 8430 }; 8431 8432 enum { 8433 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8434 }; 8435 8436 struct mlx5_ifc_cmd_queue_entry_bits { 8437 u8 type[0x8]; 8438 u8 reserved_at_8[0x18]; 8439 8440 u8 input_length[0x20]; 8441 8442 u8 input_mailbox_pointer_63_32[0x20]; 8443 8444 u8 input_mailbox_pointer_31_9[0x17]; 8445 u8 reserved_at_77[0x9]; 8446 8447 u8 command_input_inline_data[16][0x8]; 8448 8449 u8 command_output_inline_data[16][0x8]; 8450 8451 u8 output_mailbox_pointer_63_32[0x20]; 8452 8453 u8 output_mailbox_pointer_31_9[0x17]; 8454 u8 reserved_at_1b7[0x9]; 8455 8456 u8 output_length[0x20]; 8457 8458 u8 token[0x8]; 8459 u8 signature[0x8]; 8460 u8 reserved_at_1f0[0x8]; 8461 u8 status[0x7]; 8462 u8 ownership[0x1]; 8463 }; 8464 8465 struct mlx5_ifc_cmd_out_bits { 8466 u8 status[0x8]; 8467 u8 reserved_at_8[0x18]; 8468 8469 u8 syndrome[0x20]; 8470 8471 u8 command_output[0x20]; 8472 }; 8473 8474 struct mlx5_ifc_cmd_in_bits { 8475 u8 opcode[0x10]; 8476 u8 reserved_at_10[0x10]; 8477 8478 u8 reserved_at_20[0x10]; 8479 u8 op_mod[0x10]; 8480 8481 u8 command[0][0x20]; 8482 }; 8483 8484 struct mlx5_ifc_cmd_if_box_bits { 8485 u8 mailbox_data[512][0x8]; 8486 8487 u8 reserved_at_1000[0x180]; 8488 8489 u8 next_pointer_63_32[0x20]; 8490 8491 u8 next_pointer_31_10[0x16]; 8492 u8 reserved_at_11b6[0xa]; 8493 8494 u8 block_number[0x20]; 8495 8496 u8 reserved_at_11e0[0x8]; 8497 u8 token[0x8]; 8498 u8 ctrl_signature[0x8]; 8499 u8 signature[0x8]; 8500 }; 8501 8502 struct mlx5_ifc_mtt_bits { 8503 u8 ptag_63_32[0x20]; 8504 8505 u8 ptag_31_8[0x18]; 8506 u8 reserved_at_38[0x6]; 8507 u8 wr_en[0x1]; 8508 u8 rd_en[0x1]; 8509 }; 8510 8511 struct mlx5_ifc_query_wol_rol_out_bits { 8512 u8 status[0x8]; 8513 u8 reserved_at_8[0x18]; 8514 8515 u8 syndrome[0x20]; 8516 8517 u8 reserved_at_40[0x10]; 8518 u8 rol_mode[0x8]; 8519 u8 wol_mode[0x8]; 8520 8521 u8 reserved_at_60[0x20]; 8522 }; 8523 8524 struct mlx5_ifc_query_wol_rol_in_bits { 8525 u8 opcode[0x10]; 8526 u8 reserved_at_10[0x10]; 8527 8528 u8 reserved_at_20[0x10]; 8529 u8 op_mod[0x10]; 8530 8531 u8 reserved_at_40[0x40]; 8532 }; 8533 8534 struct mlx5_ifc_set_wol_rol_out_bits { 8535 u8 status[0x8]; 8536 u8 reserved_at_8[0x18]; 8537 8538 u8 syndrome[0x20]; 8539 8540 u8 reserved_at_40[0x40]; 8541 }; 8542 8543 struct mlx5_ifc_set_wol_rol_in_bits { 8544 u8 opcode[0x10]; 8545 u8 reserved_at_10[0x10]; 8546 8547 u8 reserved_at_20[0x10]; 8548 u8 op_mod[0x10]; 8549 8550 u8 rol_mode_valid[0x1]; 8551 u8 wol_mode_valid[0x1]; 8552 u8 reserved_at_42[0xe]; 8553 u8 rol_mode[0x8]; 8554 u8 wol_mode[0x8]; 8555 8556 u8 reserved_at_60[0x20]; 8557 }; 8558 8559 enum { 8560 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8561 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8562 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8563 }; 8564 8565 enum { 8566 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8567 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8568 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8569 }; 8570 8571 enum { 8572 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8573 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8574 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8575 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8576 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8577 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8578 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8579 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8580 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8581 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8582 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8583 }; 8584 8585 struct mlx5_ifc_initial_seg_bits { 8586 u8 fw_rev_minor[0x10]; 8587 u8 fw_rev_major[0x10]; 8588 8589 u8 cmd_interface_rev[0x10]; 8590 u8 fw_rev_subminor[0x10]; 8591 8592 u8 reserved_at_40[0x40]; 8593 8594 u8 cmdq_phy_addr_63_32[0x20]; 8595 8596 u8 cmdq_phy_addr_31_12[0x14]; 8597 u8 reserved_at_b4[0x2]; 8598 u8 nic_interface[0x2]; 8599 u8 log_cmdq_size[0x4]; 8600 u8 log_cmdq_stride[0x4]; 8601 8602 u8 command_doorbell_vector[0x20]; 8603 8604 u8 reserved_at_e0[0xf00]; 8605 8606 u8 initializing[0x1]; 8607 u8 reserved_at_fe1[0x4]; 8608 u8 nic_interface_supported[0x3]; 8609 u8 reserved_at_fe8[0x18]; 8610 8611 struct mlx5_ifc_health_buffer_bits health_buffer; 8612 8613 u8 no_dram_nic_offset[0x20]; 8614 8615 u8 reserved_at_1220[0x6e40]; 8616 8617 u8 reserved_at_8060[0x1f]; 8618 u8 clear_int[0x1]; 8619 8620 u8 health_syndrome[0x8]; 8621 u8 health_counter[0x18]; 8622 8623 u8 reserved_at_80a0[0x17fc0]; 8624 }; 8625 8626 struct mlx5_ifc_mtpps_reg_bits { 8627 u8 reserved_at_0[0xc]; 8628 u8 cap_number_of_pps_pins[0x4]; 8629 u8 reserved_at_10[0x4]; 8630 u8 cap_max_num_of_pps_in_pins[0x4]; 8631 u8 reserved_at_18[0x4]; 8632 u8 cap_max_num_of_pps_out_pins[0x4]; 8633 8634 u8 reserved_at_20[0x24]; 8635 u8 cap_pin_3_mode[0x4]; 8636 u8 reserved_at_48[0x4]; 8637 u8 cap_pin_2_mode[0x4]; 8638 u8 reserved_at_50[0x4]; 8639 u8 cap_pin_1_mode[0x4]; 8640 u8 reserved_at_58[0x4]; 8641 u8 cap_pin_0_mode[0x4]; 8642 8643 u8 reserved_at_60[0x4]; 8644 u8 cap_pin_7_mode[0x4]; 8645 u8 reserved_at_68[0x4]; 8646 u8 cap_pin_6_mode[0x4]; 8647 u8 reserved_at_70[0x4]; 8648 u8 cap_pin_5_mode[0x4]; 8649 u8 reserved_at_78[0x4]; 8650 u8 cap_pin_4_mode[0x4]; 8651 8652 u8 field_select[0x20]; 8653 u8 reserved_at_a0[0x60]; 8654 8655 u8 enable[0x1]; 8656 u8 reserved_at_101[0xb]; 8657 u8 pattern[0x4]; 8658 u8 reserved_at_110[0x4]; 8659 u8 pin_mode[0x4]; 8660 u8 pin[0x8]; 8661 8662 u8 reserved_at_120[0x20]; 8663 8664 u8 time_stamp[0x40]; 8665 8666 u8 out_pulse_duration[0x10]; 8667 u8 out_periodic_adjustment[0x10]; 8668 u8 enhanced_out_periodic_adjustment[0x20]; 8669 8670 u8 reserved_at_1c0[0x20]; 8671 }; 8672 8673 struct mlx5_ifc_mtppse_reg_bits { 8674 u8 reserved_at_0[0x18]; 8675 u8 pin[0x8]; 8676 u8 event_arm[0x1]; 8677 u8 reserved_at_21[0x1b]; 8678 u8 event_generation_mode[0x4]; 8679 u8 reserved_at_40[0x40]; 8680 }; 8681 8682 struct mlx5_ifc_mcqi_cap_bits { 8683 u8 supported_info_bitmask[0x20]; 8684 8685 u8 component_size[0x20]; 8686 8687 u8 max_component_size[0x20]; 8688 8689 u8 log_mcda_word_size[0x4]; 8690 u8 reserved_at_64[0xc]; 8691 u8 mcda_max_write_size[0x10]; 8692 8693 u8 rd_en[0x1]; 8694 u8 reserved_at_81[0x1]; 8695 u8 match_chip_id[0x1]; 8696 u8 match_psid[0x1]; 8697 u8 check_user_timestamp[0x1]; 8698 u8 match_base_guid_mac[0x1]; 8699 u8 reserved_at_86[0x1a]; 8700 }; 8701 8702 struct mlx5_ifc_mcqi_reg_bits { 8703 u8 read_pending_component[0x1]; 8704 u8 reserved_at_1[0xf]; 8705 u8 component_index[0x10]; 8706 8707 u8 reserved_at_20[0x20]; 8708 8709 u8 reserved_at_40[0x1b]; 8710 u8 info_type[0x5]; 8711 8712 u8 info_size[0x20]; 8713 8714 u8 offset[0x20]; 8715 8716 u8 reserved_at_a0[0x10]; 8717 u8 data_size[0x10]; 8718 8719 u8 data[0][0x20]; 8720 }; 8721 8722 struct mlx5_ifc_mcc_reg_bits { 8723 u8 reserved_at_0[0x4]; 8724 u8 time_elapsed_since_last_cmd[0xc]; 8725 u8 reserved_at_10[0x8]; 8726 u8 instruction[0x8]; 8727 8728 u8 reserved_at_20[0x10]; 8729 u8 component_index[0x10]; 8730 8731 u8 reserved_at_40[0x8]; 8732 u8 update_handle[0x18]; 8733 8734 u8 handle_owner_type[0x4]; 8735 u8 handle_owner_host_id[0x4]; 8736 u8 reserved_at_68[0x1]; 8737 u8 control_progress[0x7]; 8738 u8 error_code[0x8]; 8739 u8 reserved_at_78[0x4]; 8740 u8 control_state[0x4]; 8741 8742 u8 component_size[0x20]; 8743 8744 u8 reserved_at_a0[0x60]; 8745 }; 8746 8747 struct mlx5_ifc_mcda_reg_bits { 8748 u8 reserved_at_0[0x8]; 8749 u8 update_handle[0x18]; 8750 8751 u8 offset[0x20]; 8752 8753 u8 reserved_at_40[0x10]; 8754 u8 size[0x10]; 8755 8756 u8 reserved_at_60[0x20]; 8757 8758 u8 data[0][0x20]; 8759 }; 8760 8761 union mlx5_ifc_ports_control_registers_document_bits { 8762 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8763 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8764 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8765 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8766 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8767 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8768 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8769 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8770 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8771 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8772 struct mlx5_ifc_paos_reg_bits paos_reg; 8773 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8774 struct mlx5_ifc_peir_reg_bits peir_reg; 8775 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8776 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8777 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8778 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8779 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8780 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8781 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8782 struct mlx5_ifc_plib_reg_bits plib_reg; 8783 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8784 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8785 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8786 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8787 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8788 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8789 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8790 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8791 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8792 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8793 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8794 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8795 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8796 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8797 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8798 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8799 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8800 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8801 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8802 struct mlx5_ifc_pude_reg_bits pude_reg; 8803 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8804 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8805 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8806 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8807 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8808 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8809 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8810 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8811 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8812 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8813 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8814 u8 reserved_at_0[0x60e0]; 8815 }; 8816 8817 union mlx5_ifc_debug_enhancements_document_bits { 8818 struct mlx5_ifc_health_buffer_bits health_buffer; 8819 u8 reserved_at_0[0x200]; 8820 }; 8821 8822 union mlx5_ifc_uplink_pci_interface_document_bits { 8823 struct mlx5_ifc_initial_seg_bits initial_seg; 8824 u8 reserved_at_0[0x20060]; 8825 }; 8826 8827 struct mlx5_ifc_set_flow_table_root_out_bits { 8828 u8 status[0x8]; 8829 u8 reserved_at_8[0x18]; 8830 8831 u8 syndrome[0x20]; 8832 8833 u8 reserved_at_40[0x40]; 8834 }; 8835 8836 struct mlx5_ifc_set_flow_table_root_in_bits { 8837 u8 opcode[0x10]; 8838 u8 reserved_at_10[0x10]; 8839 8840 u8 reserved_at_20[0x10]; 8841 u8 op_mod[0x10]; 8842 8843 u8 other_vport[0x1]; 8844 u8 reserved_at_41[0xf]; 8845 u8 vport_number[0x10]; 8846 8847 u8 reserved_at_60[0x20]; 8848 8849 u8 table_type[0x8]; 8850 u8 reserved_at_88[0x18]; 8851 8852 u8 reserved_at_a0[0x8]; 8853 u8 table_id[0x18]; 8854 8855 u8 reserved_at_c0[0x8]; 8856 u8 underlay_qpn[0x18]; 8857 u8 reserved_at_e0[0x120]; 8858 }; 8859 8860 enum { 8861 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8862 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8863 }; 8864 8865 struct mlx5_ifc_modify_flow_table_out_bits { 8866 u8 status[0x8]; 8867 u8 reserved_at_8[0x18]; 8868 8869 u8 syndrome[0x20]; 8870 8871 u8 reserved_at_40[0x40]; 8872 }; 8873 8874 struct mlx5_ifc_modify_flow_table_in_bits { 8875 u8 opcode[0x10]; 8876 u8 reserved_at_10[0x10]; 8877 8878 u8 reserved_at_20[0x10]; 8879 u8 op_mod[0x10]; 8880 8881 u8 other_vport[0x1]; 8882 u8 reserved_at_41[0xf]; 8883 u8 vport_number[0x10]; 8884 8885 u8 reserved_at_60[0x10]; 8886 u8 modify_field_select[0x10]; 8887 8888 u8 table_type[0x8]; 8889 u8 reserved_at_88[0x18]; 8890 8891 u8 reserved_at_a0[0x8]; 8892 u8 table_id[0x18]; 8893 8894 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8895 }; 8896 8897 struct mlx5_ifc_ets_tcn_config_reg_bits { 8898 u8 g[0x1]; 8899 u8 b[0x1]; 8900 u8 r[0x1]; 8901 u8 reserved_at_3[0x9]; 8902 u8 group[0x4]; 8903 u8 reserved_at_10[0x9]; 8904 u8 bw_allocation[0x7]; 8905 8906 u8 reserved_at_20[0xc]; 8907 u8 max_bw_units[0x4]; 8908 u8 reserved_at_30[0x8]; 8909 u8 max_bw_value[0x8]; 8910 }; 8911 8912 struct mlx5_ifc_ets_global_config_reg_bits { 8913 u8 reserved_at_0[0x2]; 8914 u8 r[0x1]; 8915 u8 reserved_at_3[0x1d]; 8916 8917 u8 reserved_at_20[0xc]; 8918 u8 max_bw_units[0x4]; 8919 u8 reserved_at_30[0x8]; 8920 u8 max_bw_value[0x8]; 8921 }; 8922 8923 struct mlx5_ifc_qetc_reg_bits { 8924 u8 reserved_at_0[0x8]; 8925 u8 port_number[0x8]; 8926 u8 reserved_at_10[0x30]; 8927 8928 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8929 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8930 }; 8931 8932 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8933 u8 e[0x1]; 8934 u8 reserved_at_01[0x0b]; 8935 u8 prio[0x04]; 8936 }; 8937 8938 struct mlx5_ifc_qpdpm_reg_bits { 8939 u8 reserved_at_0[0x8]; 8940 u8 local_port[0x8]; 8941 u8 reserved_at_10[0x10]; 8942 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8943 }; 8944 8945 struct mlx5_ifc_qpts_reg_bits { 8946 u8 reserved_at_0[0x8]; 8947 u8 local_port[0x8]; 8948 u8 reserved_at_10[0x2d]; 8949 u8 trust_state[0x3]; 8950 }; 8951 8952 struct mlx5_ifc_pptb_reg_bits { 8953 u8 reserved_at_0[0x2]; 8954 u8 mm[0x2]; 8955 u8 reserved_at_4[0x4]; 8956 u8 local_port[0x8]; 8957 u8 reserved_at_10[0x6]; 8958 u8 cm[0x1]; 8959 u8 um[0x1]; 8960 u8 pm[0x8]; 8961 8962 u8 prio_x_buff[0x20]; 8963 8964 u8 pm_msb[0x8]; 8965 u8 reserved_at_48[0x10]; 8966 u8 ctrl_buff[0x4]; 8967 u8 untagged_buff[0x4]; 8968 }; 8969 8970 struct mlx5_ifc_pbmc_reg_bits { 8971 u8 reserved_at_0[0x8]; 8972 u8 local_port[0x8]; 8973 u8 reserved_at_10[0x10]; 8974 8975 u8 xoff_timer_value[0x10]; 8976 u8 xoff_refresh[0x10]; 8977 8978 u8 reserved_at_40[0x9]; 8979 u8 fullness_threshold[0x7]; 8980 u8 port_buffer_size[0x10]; 8981 8982 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8983 8984 u8 reserved_at_2e0[0x40]; 8985 }; 8986 8987 struct mlx5_ifc_qtct_reg_bits { 8988 u8 reserved_at_0[0x8]; 8989 u8 port_number[0x8]; 8990 u8 reserved_at_10[0xd]; 8991 u8 prio[0x3]; 8992 8993 u8 reserved_at_20[0x1d]; 8994 u8 tclass[0x3]; 8995 }; 8996 8997 struct mlx5_ifc_mcia_reg_bits { 8998 u8 l[0x1]; 8999 u8 reserved_at_1[0x7]; 9000 u8 module[0x8]; 9001 u8 reserved_at_10[0x8]; 9002 u8 status[0x8]; 9003 9004 u8 i2c_device_address[0x8]; 9005 u8 page_number[0x8]; 9006 u8 device_address[0x10]; 9007 9008 u8 reserved_at_40[0x10]; 9009 u8 size[0x10]; 9010 9011 u8 reserved_at_60[0x20]; 9012 9013 u8 dword_0[0x20]; 9014 u8 dword_1[0x20]; 9015 u8 dword_2[0x20]; 9016 u8 dword_3[0x20]; 9017 u8 dword_4[0x20]; 9018 u8 dword_5[0x20]; 9019 u8 dword_6[0x20]; 9020 u8 dword_7[0x20]; 9021 u8 dword_8[0x20]; 9022 u8 dword_9[0x20]; 9023 u8 dword_10[0x20]; 9024 u8 dword_11[0x20]; 9025 }; 9026 9027 struct mlx5_ifc_dcbx_param_bits { 9028 u8 dcbx_cee_cap[0x1]; 9029 u8 dcbx_ieee_cap[0x1]; 9030 u8 dcbx_standby_cap[0x1]; 9031 u8 reserved_at_0[0x5]; 9032 u8 port_number[0x8]; 9033 u8 reserved_at_10[0xa]; 9034 u8 max_application_table_size[6]; 9035 u8 reserved_at_20[0x15]; 9036 u8 version_oper[0x3]; 9037 u8 reserved_at_38[5]; 9038 u8 version_admin[0x3]; 9039 u8 willing_admin[0x1]; 9040 u8 reserved_at_41[0x3]; 9041 u8 pfc_cap_oper[0x4]; 9042 u8 reserved_at_48[0x4]; 9043 u8 pfc_cap_admin[0x4]; 9044 u8 reserved_at_50[0x4]; 9045 u8 num_of_tc_oper[0x4]; 9046 u8 reserved_at_58[0x4]; 9047 u8 num_of_tc_admin[0x4]; 9048 u8 remote_willing[0x1]; 9049 u8 reserved_at_61[3]; 9050 u8 remote_pfc_cap[4]; 9051 u8 reserved_at_68[0x14]; 9052 u8 remote_num_of_tc[0x4]; 9053 u8 reserved_at_80[0x18]; 9054 u8 error[0x8]; 9055 u8 reserved_at_a0[0x160]; 9056 }; 9057 9058 struct mlx5_ifc_lagc_bits { 9059 u8 reserved_at_0[0x1d]; 9060 u8 lag_state[0x3]; 9061 9062 u8 reserved_at_20[0x14]; 9063 u8 tx_remap_affinity_2[0x4]; 9064 u8 reserved_at_38[0x4]; 9065 u8 tx_remap_affinity_1[0x4]; 9066 }; 9067 9068 struct mlx5_ifc_create_lag_out_bits { 9069 u8 status[0x8]; 9070 u8 reserved_at_8[0x18]; 9071 9072 u8 syndrome[0x20]; 9073 9074 u8 reserved_at_40[0x40]; 9075 }; 9076 9077 struct mlx5_ifc_create_lag_in_bits { 9078 u8 opcode[0x10]; 9079 u8 reserved_at_10[0x10]; 9080 9081 u8 reserved_at_20[0x10]; 9082 u8 op_mod[0x10]; 9083 9084 struct mlx5_ifc_lagc_bits ctx; 9085 }; 9086 9087 struct mlx5_ifc_modify_lag_out_bits { 9088 u8 status[0x8]; 9089 u8 reserved_at_8[0x18]; 9090 9091 u8 syndrome[0x20]; 9092 9093 u8 reserved_at_40[0x40]; 9094 }; 9095 9096 struct mlx5_ifc_modify_lag_in_bits { 9097 u8 opcode[0x10]; 9098 u8 reserved_at_10[0x10]; 9099 9100 u8 reserved_at_20[0x10]; 9101 u8 op_mod[0x10]; 9102 9103 u8 reserved_at_40[0x20]; 9104 u8 field_select[0x20]; 9105 9106 struct mlx5_ifc_lagc_bits ctx; 9107 }; 9108 9109 struct mlx5_ifc_query_lag_out_bits { 9110 u8 status[0x8]; 9111 u8 reserved_at_8[0x18]; 9112 9113 u8 syndrome[0x20]; 9114 9115 u8 reserved_at_40[0x40]; 9116 9117 struct mlx5_ifc_lagc_bits ctx; 9118 }; 9119 9120 struct mlx5_ifc_query_lag_in_bits { 9121 u8 opcode[0x10]; 9122 u8 reserved_at_10[0x10]; 9123 9124 u8 reserved_at_20[0x10]; 9125 u8 op_mod[0x10]; 9126 9127 u8 reserved_at_40[0x40]; 9128 }; 9129 9130 struct mlx5_ifc_destroy_lag_out_bits { 9131 u8 status[0x8]; 9132 u8 reserved_at_8[0x18]; 9133 9134 u8 syndrome[0x20]; 9135 9136 u8 reserved_at_40[0x40]; 9137 }; 9138 9139 struct mlx5_ifc_destroy_lag_in_bits { 9140 u8 opcode[0x10]; 9141 u8 reserved_at_10[0x10]; 9142 9143 u8 reserved_at_20[0x10]; 9144 u8 op_mod[0x10]; 9145 9146 u8 reserved_at_40[0x40]; 9147 }; 9148 9149 struct mlx5_ifc_create_vport_lag_out_bits { 9150 u8 status[0x8]; 9151 u8 reserved_at_8[0x18]; 9152 9153 u8 syndrome[0x20]; 9154 9155 u8 reserved_at_40[0x40]; 9156 }; 9157 9158 struct mlx5_ifc_create_vport_lag_in_bits { 9159 u8 opcode[0x10]; 9160 u8 reserved_at_10[0x10]; 9161 9162 u8 reserved_at_20[0x10]; 9163 u8 op_mod[0x10]; 9164 9165 u8 reserved_at_40[0x40]; 9166 }; 9167 9168 struct mlx5_ifc_destroy_vport_lag_out_bits { 9169 u8 status[0x8]; 9170 u8 reserved_at_8[0x18]; 9171 9172 u8 syndrome[0x20]; 9173 9174 u8 reserved_at_40[0x40]; 9175 }; 9176 9177 struct mlx5_ifc_destroy_vport_lag_in_bits { 9178 u8 opcode[0x10]; 9179 u8 reserved_at_10[0x10]; 9180 9181 u8 reserved_at_20[0x10]; 9182 u8 op_mod[0x10]; 9183 9184 u8 reserved_at_40[0x40]; 9185 }; 9186 9187 struct mlx5_ifc_alloc_memic_in_bits { 9188 u8 opcode[0x10]; 9189 u8 reserved_at_10[0x10]; 9190 9191 u8 reserved_at_20[0x10]; 9192 u8 op_mod[0x10]; 9193 9194 u8 reserved_at_30[0x20]; 9195 9196 u8 reserved_at_40[0x18]; 9197 u8 log_memic_addr_alignment[0x8]; 9198 9199 u8 range_start_addr[0x40]; 9200 9201 u8 range_size[0x20]; 9202 9203 u8 memic_size[0x20]; 9204 }; 9205 9206 struct mlx5_ifc_alloc_memic_out_bits { 9207 u8 status[0x8]; 9208 u8 reserved_at_8[0x18]; 9209 9210 u8 syndrome[0x20]; 9211 9212 u8 memic_start_addr[0x40]; 9213 }; 9214 9215 struct mlx5_ifc_dealloc_memic_in_bits { 9216 u8 opcode[0x10]; 9217 u8 reserved_at_10[0x10]; 9218 9219 u8 reserved_at_20[0x10]; 9220 u8 op_mod[0x10]; 9221 9222 u8 reserved_at_40[0x40]; 9223 9224 u8 memic_start_addr[0x40]; 9225 9226 u8 memic_size[0x20]; 9227 9228 u8 reserved_at_e0[0x20]; 9229 }; 9230 9231 struct mlx5_ifc_dealloc_memic_out_bits { 9232 u8 status[0x8]; 9233 u8 reserved_at_8[0x18]; 9234 9235 u8 syndrome[0x20]; 9236 9237 u8 reserved_at_40[0x40]; 9238 }; 9239 9240 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9241 u8 opcode[0x10]; 9242 u8 uid[0x10]; 9243 9244 u8 reserved_at_20[0x10]; 9245 u8 obj_type[0x10]; 9246 9247 u8 obj_id[0x20]; 9248 9249 u8 reserved_at_60[0x20]; 9250 }; 9251 9252 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9253 u8 status[0x8]; 9254 u8 reserved_at_8[0x18]; 9255 9256 u8 syndrome[0x20]; 9257 9258 u8 obj_id[0x20]; 9259 9260 u8 reserved_at_60[0x20]; 9261 }; 9262 9263 struct mlx5_ifc_umem_bits { 9264 u8 modify_field_select[0x40]; 9265 9266 u8 reserved_at_40[0x5b]; 9267 u8 log_page_size[0x5]; 9268 9269 u8 page_offset[0x20]; 9270 9271 u8 num_of_mtt[0x40]; 9272 9273 struct mlx5_ifc_mtt_bits mtt[0]; 9274 }; 9275 9276 struct mlx5_ifc_uctx_bits { 9277 u8 modify_field_select[0x40]; 9278 9279 u8 reserved_at_40[0x1c0]; 9280 }; 9281 9282 struct mlx5_ifc_create_umem_in_bits { 9283 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9284 struct mlx5_ifc_umem_bits umem; 9285 }; 9286 9287 struct mlx5_ifc_create_uctx_in_bits { 9288 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9289 struct mlx5_ifc_uctx_bits uctx; 9290 }; 9291 9292 struct mlx5_ifc_mtrc_string_db_param_bits { 9293 u8 string_db_base_address[0x20]; 9294 9295 u8 reserved_at_20[0x8]; 9296 u8 string_db_size[0x18]; 9297 }; 9298 9299 struct mlx5_ifc_mtrc_cap_bits { 9300 u8 trace_owner[0x1]; 9301 u8 trace_to_memory[0x1]; 9302 u8 reserved_at_2[0x4]; 9303 u8 trc_ver[0x2]; 9304 u8 reserved_at_8[0x14]; 9305 u8 num_string_db[0x4]; 9306 9307 u8 first_string_trace[0x8]; 9308 u8 num_string_trace[0x8]; 9309 u8 reserved_at_30[0x28]; 9310 9311 u8 log_max_trace_buffer_size[0x8]; 9312 9313 u8 reserved_at_60[0x20]; 9314 9315 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9316 9317 u8 reserved_at_280[0x180]; 9318 }; 9319 9320 struct mlx5_ifc_mtrc_conf_bits { 9321 u8 reserved_at_0[0x1c]; 9322 u8 trace_mode[0x4]; 9323 u8 reserved_at_20[0x18]; 9324 u8 log_trace_buffer_size[0x8]; 9325 u8 trace_mkey[0x20]; 9326 u8 reserved_at_60[0x3a0]; 9327 }; 9328 9329 struct mlx5_ifc_mtrc_stdb_bits { 9330 u8 string_db_index[0x4]; 9331 u8 reserved_at_4[0x4]; 9332 u8 read_size[0x18]; 9333 u8 start_offset[0x20]; 9334 u8 string_db_data[0]; 9335 }; 9336 9337 struct mlx5_ifc_mtrc_ctrl_bits { 9338 u8 trace_status[0x2]; 9339 u8 reserved_at_2[0x2]; 9340 u8 arm_event[0x1]; 9341 u8 reserved_at_5[0xb]; 9342 u8 modify_field_select[0x10]; 9343 u8 reserved_at_20[0x2b]; 9344 u8 current_timestamp52_32[0x15]; 9345 u8 current_timestamp31_0[0x20]; 9346 u8 reserved_at_80[0x180]; 9347 }; 9348 9349 #endif /* MLX5_IFC_H */ 9350