1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 85 }; 86 87 enum { 88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 90 }; 91 92 enum { 93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 94 }; 95 96 enum { 97 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 98 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 99 MLX5_CMD_OP_INIT_HCA = 0x102, 100 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 101 MLX5_CMD_OP_ENABLE_HCA = 0x104, 102 MLX5_CMD_OP_DISABLE_HCA = 0x105, 103 MLX5_CMD_OP_QUERY_PAGES = 0x107, 104 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 105 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 106 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 107 MLX5_CMD_OP_SET_ISSI = 0x10b, 108 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 109 MLX5_CMD_OP_CREATE_MKEY = 0x200, 110 MLX5_CMD_OP_QUERY_MKEY = 0x201, 111 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 112 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 113 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 114 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 115 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 116 MLX5_CMD_OP_CREATE_EQ = 0x301, 117 MLX5_CMD_OP_DESTROY_EQ = 0x302, 118 MLX5_CMD_OP_QUERY_EQ = 0x303, 119 MLX5_CMD_OP_GEN_EQE = 0x304, 120 MLX5_CMD_OP_CREATE_CQ = 0x400, 121 MLX5_CMD_OP_DESTROY_CQ = 0x401, 122 MLX5_CMD_OP_QUERY_CQ = 0x402, 123 MLX5_CMD_OP_MODIFY_CQ = 0x403, 124 MLX5_CMD_OP_CREATE_QP = 0x500, 125 MLX5_CMD_OP_DESTROY_QP = 0x501, 126 MLX5_CMD_OP_RST2INIT_QP = 0x502, 127 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 128 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 129 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 130 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 131 MLX5_CMD_OP_2ERR_QP = 0x507, 132 MLX5_CMD_OP_2RST_QP = 0x50a, 133 MLX5_CMD_OP_QUERY_QP = 0x50b, 134 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 135 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 136 MLX5_CMD_OP_CREATE_PSV = 0x600, 137 MLX5_CMD_OP_DESTROY_PSV = 0x601, 138 MLX5_CMD_OP_CREATE_SRQ = 0x700, 139 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 140 MLX5_CMD_OP_QUERY_SRQ = 0x702, 141 MLX5_CMD_OP_ARM_RQ = 0x703, 142 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 143 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 144 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 145 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 146 MLX5_CMD_OP_CREATE_DCT = 0x710, 147 MLX5_CMD_OP_DESTROY_DCT = 0x711, 148 MLX5_CMD_OP_DRAIN_DCT = 0x712, 149 MLX5_CMD_OP_QUERY_DCT = 0x713, 150 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 151 MLX5_CMD_OP_CREATE_XRQ = 0x717, 152 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 153 MLX5_CMD_OP_QUERY_XRQ = 0x719, 154 MLX5_CMD_OP_ARM_XRQ = 0x71a, 155 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 156 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 157 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 158 MLX5_CMD_OP_QUERY_HOST_PARAMS = 0x740, 159 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 160 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 161 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 162 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 163 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 164 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 165 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 166 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 167 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 168 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 169 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 170 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 171 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 172 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 173 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 174 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 175 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 176 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 177 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 178 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 179 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 180 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 181 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 182 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 183 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 184 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 185 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 186 MLX5_CMD_OP_ALLOC_PD = 0x800, 187 MLX5_CMD_OP_DEALLOC_PD = 0x801, 188 MLX5_CMD_OP_ALLOC_UAR = 0x802, 189 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 190 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 191 MLX5_CMD_OP_ACCESS_REG = 0x805, 192 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 193 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 194 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 195 MLX5_CMD_OP_MAD_IFC = 0x50d, 196 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 197 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 198 MLX5_CMD_OP_NOP = 0x80d, 199 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 200 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 201 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 202 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 203 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 204 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 205 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 206 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 207 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 208 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 209 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 210 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 211 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 212 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 213 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 214 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 215 MLX5_CMD_OP_CREATE_LAG = 0x840, 216 MLX5_CMD_OP_MODIFY_LAG = 0x841, 217 MLX5_CMD_OP_QUERY_LAG = 0x842, 218 MLX5_CMD_OP_DESTROY_LAG = 0x843, 219 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 220 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 221 MLX5_CMD_OP_CREATE_TIR = 0x900, 222 MLX5_CMD_OP_MODIFY_TIR = 0x901, 223 MLX5_CMD_OP_DESTROY_TIR = 0x902, 224 MLX5_CMD_OP_QUERY_TIR = 0x903, 225 MLX5_CMD_OP_CREATE_SQ = 0x904, 226 MLX5_CMD_OP_MODIFY_SQ = 0x905, 227 MLX5_CMD_OP_DESTROY_SQ = 0x906, 228 MLX5_CMD_OP_QUERY_SQ = 0x907, 229 MLX5_CMD_OP_CREATE_RQ = 0x908, 230 MLX5_CMD_OP_MODIFY_RQ = 0x909, 231 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 232 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 233 MLX5_CMD_OP_QUERY_RQ = 0x90b, 234 MLX5_CMD_OP_CREATE_RMP = 0x90c, 235 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 236 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 237 MLX5_CMD_OP_QUERY_RMP = 0x90f, 238 MLX5_CMD_OP_CREATE_TIS = 0x912, 239 MLX5_CMD_OP_MODIFY_TIS = 0x913, 240 MLX5_CMD_OP_DESTROY_TIS = 0x914, 241 MLX5_CMD_OP_QUERY_TIS = 0x915, 242 MLX5_CMD_OP_CREATE_RQT = 0x916, 243 MLX5_CMD_OP_MODIFY_RQT = 0x917, 244 MLX5_CMD_OP_DESTROY_RQT = 0x918, 245 MLX5_CMD_OP_QUERY_RQT = 0x919, 246 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 247 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 248 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 249 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 250 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 251 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 252 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 253 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 254 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 255 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 256 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 257 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 258 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 259 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 260 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 261 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 262 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 263 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 264 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 265 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 266 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 267 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 268 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 269 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 270 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 271 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 272 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 273 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 274 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 275 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 276 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 277 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 278 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 279 MLX5_CMD_OP_MAX 280 }; 281 282 /* Valid range for general commands that don't work over an object */ 283 enum { 284 MLX5_CMD_OP_GENERAL_START = 0xb00, 285 MLX5_CMD_OP_GENERAL_END = 0xd00, 286 }; 287 288 struct mlx5_ifc_flow_table_fields_supported_bits { 289 u8 outer_dmac[0x1]; 290 u8 outer_smac[0x1]; 291 u8 outer_ether_type[0x1]; 292 u8 outer_ip_version[0x1]; 293 u8 outer_first_prio[0x1]; 294 u8 outer_first_cfi[0x1]; 295 u8 outer_first_vid[0x1]; 296 u8 outer_ipv4_ttl[0x1]; 297 u8 outer_second_prio[0x1]; 298 u8 outer_second_cfi[0x1]; 299 u8 outer_second_vid[0x1]; 300 u8 reserved_at_b[0x1]; 301 u8 outer_sip[0x1]; 302 u8 outer_dip[0x1]; 303 u8 outer_frag[0x1]; 304 u8 outer_ip_protocol[0x1]; 305 u8 outer_ip_ecn[0x1]; 306 u8 outer_ip_dscp[0x1]; 307 u8 outer_udp_sport[0x1]; 308 u8 outer_udp_dport[0x1]; 309 u8 outer_tcp_sport[0x1]; 310 u8 outer_tcp_dport[0x1]; 311 u8 outer_tcp_flags[0x1]; 312 u8 outer_gre_protocol[0x1]; 313 u8 outer_gre_key[0x1]; 314 u8 outer_vxlan_vni[0x1]; 315 u8 outer_geneve_vni[0x1]; 316 u8 outer_geneve_oam[0x1]; 317 u8 outer_geneve_protocol_type[0x1]; 318 u8 outer_geneve_opt_len[0x1]; 319 u8 reserved_at_1e[0x1]; 320 u8 source_eswitch_port[0x1]; 321 322 u8 inner_dmac[0x1]; 323 u8 inner_smac[0x1]; 324 u8 inner_ether_type[0x1]; 325 u8 inner_ip_version[0x1]; 326 u8 inner_first_prio[0x1]; 327 u8 inner_first_cfi[0x1]; 328 u8 inner_first_vid[0x1]; 329 u8 reserved_at_27[0x1]; 330 u8 inner_second_prio[0x1]; 331 u8 inner_second_cfi[0x1]; 332 u8 inner_second_vid[0x1]; 333 u8 reserved_at_2b[0x1]; 334 u8 inner_sip[0x1]; 335 u8 inner_dip[0x1]; 336 u8 inner_frag[0x1]; 337 u8 inner_ip_protocol[0x1]; 338 u8 inner_ip_ecn[0x1]; 339 u8 inner_ip_dscp[0x1]; 340 u8 inner_udp_sport[0x1]; 341 u8 inner_udp_dport[0x1]; 342 u8 inner_tcp_sport[0x1]; 343 u8 inner_tcp_dport[0x1]; 344 u8 inner_tcp_flags[0x1]; 345 u8 reserved_at_37[0x9]; 346 347 u8 geneve_tlv_option_0_data[0x1]; 348 u8 reserved_at_41[0x4]; 349 u8 outer_first_mpls_over_udp[0x4]; 350 u8 outer_first_mpls_over_gre[0x4]; 351 u8 inner_first_mpls[0x4]; 352 u8 outer_first_mpls[0x4]; 353 u8 reserved_at_55[0x2]; 354 u8 outer_esp_spi[0x1]; 355 u8 reserved_at_58[0x2]; 356 u8 bth_dst_qp[0x1]; 357 358 u8 reserved_at_5b[0x25]; 359 }; 360 361 struct mlx5_ifc_flow_table_prop_layout_bits { 362 u8 ft_support[0x1]; 363 u8 reserved_at_1[0x1]; 364 u8 flow_counter[0x1]; 365 u8 flow_modify_en[0x1]; 366 u8 modify_root[0x1]; 367 u8 identified_miss_table_mode[0x1]; 368 u8 flow_table_modify[0x1]; 369 u8 reformat[0x1]; 370 u8 decap[0x1]; 371 u8 reserved_at_9[0x1]; 372 u8 pop_vlan[0x1]; 373 u8 push_vlan[0x1]; 374 u8 reserved_at_c[0x1]; 375 u8 pop_vlan_2[0x1]; 376 u8 push_vlan_2[0x1]; 377 u8 reformat_and_vlan_action[0x1]; 378 u8 reserved_at_10[0x1]; 379 u8 sw_owner[0x1]; 380 u8 reformat_l3_tunnel_to_l2[0x1]; 381 u8 reformat_l2_to_l3_tunnel[0x1]; 382 u8 reformat_and_modify_action[0x1]; 383 u8 reserved_at_15[0x2]; 384 u8 table_miss_action_domain[0x1]; 385 u8 reserved_at_18[0x8]; 386 u8 reserved_at_20[0x2]; 387 u8 log_max_ft_size[0x6]; 388 u8 log_max_modify_header_context[0x8]; 389 u8 max_modify_header_actions[0x8]; 390 u8 max_ft_level[0x8]; 391 392 u8 reserved_at_40[0x20]; 393 394 u8 reserved_at_60[0x18]; 395 u8 log_max_ft_num[0x8]; 396 397 u8 reserved_at_80[0x18]; 398 u8 log_max_destination[0x8]; 399 400 u8 log_max_flow_counter[0x8]; 401 u8 reserved_at_a8[0x10]; 402 u8 log_max_flow[0x8]; 403 404 u8 reserved_at_c0[0x40]; 405 406 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 407 408 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 409 }; 410 411 struct mlx5_ifc_odp_per_transport_service_cap_bits { 412 u8 send[0x1]; 413 u8 receive[0x1]; 414 u8 write[0x1]; 415 u8 read[0x1]; 416 u8 atomic[0x1]; 417 u8 srq_receive[0x1]; 418 u8 reserved_at_6[0x1a]; 419 }; 420 421 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 422 u8 smac_47_16[0x20]; 423 424 u8 smac_15_0[0x10]; 425 u8 ethertype[0x10]; 426 427 u8 dmac_47_16[0x20]; 428 429 u8 dmac_15_0[0x10]; 430 u8 first_prio[0x3]; 431 u8 first_cfi[0x1]; 432 u8 first_vid[0xc]; 433 434 u8 ip_protocol[0x8]; 435 u8 ip_dscp[0x6]; 436 u8 ip_ecn[0x2]; 437 u8 cvlan_tag[0x1]; 438 u8 svlan_tag[0x1]; 439 u8 frag[0x1]; 440 u8 ip_version[0x4]; 441 u8 tcp_flags[0x9]; 442 443 u8 tcp_sport[0x10]; 444 u8 tcp_dport[0x10]; 445 446 u8 reserved_at_c0[0x18]; 447 u8 ttl_hoplimit[0x8]; 448 449 u8 udp_sport[0x10]; 450 u8 udp_dport[0x10]; 451 452 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 453 454 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 455 }; 456 457 struct mlx5_ifc_nvgre_key_bits { 458 u8 hi[0x18]; 459 u8 lo[0x8]; 460 }; 461 462 union mlx5_ifc_gre_key_bits { 463 struct mlx5_ifc_nvgre_key_bits nvgre; 464 u8 key[0x20]; 465 }; 466 467 struct mlx5_ifc_fte_match_set_misc_bits { 468 u8 reserved_at_0[0x8]; 469 u8 source_sqn[0x18]; 470 471 u8 source_eswitch_owner_vhca_id[0x10]; 472 u8 source_port[0x10]; 473 474 u8 outer_second_prio[0x3]; 475 u8 outer_second_cfi[0x1]; 476 u8 outer_second_vid[0xc]; 477 u8 inner_second_prio[0x3]; 478 u8 inner_second_cfi[0x1]; 479 u8 inner_second_vid[0xc]; 480 481 u8 outer_second_cvlan_tag[0x1]; 482 u8 inner_second_cvlan_tag[0x1]; 483 u8 outer_second_svlan_tag[0x1]; 484 u8 inner_second_svlan_tag[0x1]; 485 u8 reserved_at_64[0xc]; 486 u8 gre_protocol[0x10]; 487 488 union mlx5_ifc_gre_key_bits gre_key; 489 490 u8 vxlan_vni[0x18]; 491 u8 reserved_at_b8[0x8]; 492 493 u8 geneve_vni[0x18]; 494 u8 reserved_at_d8[0x7]; 495 u8 geneve_oam[0x1]; 496 497 u8 reserved_at_e0[0xc]; 498 u8 outer_ipv6_flow_label[0x14]; 499 500 u8 reserved_at_100[0xc]; 501 u8 inner_ipv6_flow_label[0x14]; 502 503 u8 reserved_at_120[0xa]; 504 u8 geneve_opt_len[0x6]; 505 u8 geneve_protocol_type[0x10]; 506 507 u8 reserved_at_140[0x8]; 508 u8 bth_dst_qp[0x18]; 509 u8 reserved_at_160[0x20]; 510 u8 outer_esp_spi[0x20]; 511 u8 reserved_at_1a0[0x60]; 512 }; 513 514 struct mlx5_ifc_fte_match_mpls_bits { 515 u8 mpls_label[0x14]; 516 u8 mpls_exp[0x3]; 517 u8 mpls_s_bos[0x1]; 518 u8 mpls_ttl[0x8]; 519 }; 520 521 struct mlx5_ifc_fte_match_set_misc2_bits { 522 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 523 524 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 525 526 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 527 528 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 529 530 u8 reserved_at_80[0x100]; 531 532 u8 metadata_reg_a[0x20]; 533 534 u8 reserved_at_1a0[0x60]; 535 }; 536 537 struct mlx5_ifc_fte_match_set_misc3_bits { 538 u8 reserved_at_0[0x120]; 539 u8 geneve_tlv_option_0_data[0x20]; 540 u8 reserved_at_140[0xc0]; 541 }; 542 543 struct mlx5_ifc_cmd_pas_bits { 544 u8 pa_h[0x20]; 545 546 u8 pa_l[0x14]; 547 u8 reserved_at_34[0xc]; 548 }; 549 550 struct mlx5_ifc_uint64_bits { 551 u8 hi[0x20]; 552 553 u8 lo[0x20]; 554 }; 555 556 enum { 557 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 558 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 559 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 560 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 561 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 562 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 563 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 564 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 565 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 566 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 567 }; 568 569 struct mlx5_ifc_ads_bits { 570 u8 fl[0x1]; 571 u8 free_ar[0x1]; 572 u8 reserved_at_2[0xe]; 573 u8 pkey_index[0x10]; 574 575 u8 reserved_at_20[0x8]; 576 u8 grh[0x1]; 577 u8 mlid[0x7]; 578 u8 rlid[0x10]; 579 580 u8 ack_timeout[0x5]; 581 u8 reserved_at_45[0x3]; 582 u8 src_addr_index[0x8]; 583 u8 reserved_at_50[0x4]; 584 u8 stat_rate[0x4]; 585 u8 hop_limit[0x8]; 586 587 u8 reserved_at_60[0x4]; 588 u8 tclass[0x8]; 589 u8 flow_label[0x14]; 590 591 u8 rgid_rip[16][0x8]; 592 593 u8 reserved_at_100[0x4]; 594 u8 f_dscp[0x1]; 595 u8 f_ecn[0x1]; 596 u8 reserved_at_106[0x1]; 597 u8 f_eth_prio[0x1]; 598 u8 ecn[0x2]; 599 u8 dscp[0x6]; 600 u8 udp_sport[0x10]; 601 602 u8 dei_cfi[0x1]; 603 u8 eth_prio[0x3]; 604 u8 sl[0x4]; 605 u8 vhca_port_num[0x8]; 606 u8 rmac_47_32[0x10]; 607 608 u8 rmac_31_0[0x20]; 609 }; 610 611 struct mlx5_ifc_flow_table_nic_cap_bits { 612 u8 nic_rx_multi_path_tirs[0x1]; 613 u8 nic_rx_multi_path_tirs_fts[0x1]; 614 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 615 u8 reserved_at_3[0x1d]; 616 u8 encap_general_header[0x1]; 617 u8 reserved_at_21[0xa]; 618 u8 log_max_packet_reformat_context[0x5]; 619 u8 reserved_at_30[0x6]; 620 u8 max_encap_header_size[0xa]; 621 u8 reserved_at_40[0x1c0]; 622 623 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 624 625 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 626 627 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 628 629 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 630 631 u8 reserved_at_a00[0x200]; 632 633 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 634 635 u8 reserved_at_e00[0x7200]; 636 }; 637 638 struct mlx5_ifc_flow_table_eswitch_cap_bits { 639 u8 reserved_at_0[0x1a]; 640 u8 multi_fdb_encap[0x1]; 641 u8 reserved_at_1b[0x1]; 642 u8 fdb_multi_path_to_table[0x1]; 643 u8 reserved_at_1d[0x3]; 644 645 u8 reserved_at_20[0x1e0]; 646 647 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 648 649 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 650 651 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 652 653 u8 reserved_at_800[0x7800]; 654 }; 655 656 enum { 657 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 658 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 659 }; 660 661 struct mlx5_ifc_e_switch_cap_bits { 662 u8 vport_svlan_strip[0x1]; 663 u8 vport_cvlan_strip[0x1]; 664 u8 vport_svlan_insert[0x1]; 665 u8 vport_cvlan_insert_if_not_exist[0x1]; 666 u8 vport_cvlan_insert_overwrite[0x1]; 667 u8 reserved_at_5[0x16]; 668 u8 ecpf_vport_exists[0x1]; 669 u8 counter_eswitch_affinity[0x1]; 670 u8 merged_eswitch[0x1]; 671 u8 nic_vport_node_guid_modify[0x1]; 672 u8 nic_vport_port_guid_modify[0x1]; 673 674 u8 vxlan_encap_decap[0x1]; 675 u8 nvgre_encap_decap[0x1]; 676 u8 reserved_at_22[0x1]; 677 u8 log_max_fdb_encap_uplink[0x5]; 678 u8 reserved_at_21[0x3]; 679 u8 log_max_packet_reformat_context[0x5]; 680 u8 reserved_2b[0x6]; 681 u8 max_encap_header_size[0xa]; 682 683 u8 reserved_40[0x7c0]; 684 685 }; 686 687 struct mlx5_ifc_qos_cap_bits { 688 u8 packet_pacing[0x1]; 689 u8 esw_scheduling[0x1]; 690 u8 esw_bw_share[0x1]; 691 u8 esw_rate_limit[0x1]; 692 u8 reserved_at_4[0x1]; 693 u8 packet_pacing_burst_bound[0x1]; 694 u8 packet_pacing_typical_size[0x1]; 695 u8 reserved_at_7[0x19]; 696 697 u8 reserved_at_20[0x20]; 698 699 u8 packet_pacing_max_rate[0x20]; 700 701 u8 packet_pacing_min_rate[0x20]; 702 703 u8 reserved_at_80[0x10]; 704 u8 packet_pacing_rate_table_size[0x10]; 705 706 u8 esw_element_type[0x10]; 707 u8 esw_tsar_type[0x10]; 708 709 u8 reserved_at_c0[0x10]; 710 u8 max_qos_para_vport[0x10]; 711 712 u8 max_tsar_bw_share[0x20]; 713 714 u8 reserved_at_100[0x700]; 715 }; 716 717 struct mlx5_ifc_debug_cap_bits { 718 u8 reserved_at_0[0x20]; 719 720 u8 reserved_at_20[0x2]; 721 u8 stall_detect[0x1]; 722 u8 reserved_at_23[0x1d]; 723 724 u8 reserved_at_40[0x7c0]; 725 }; 726 727 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 728 u8 csum_cap[0x1]; 729 u8 vlan_cap[0x1]; 730 u8 lro_cap[0x1]; 731 u8 lro_psh_flag[0x1]; 732 u8 lro_time_stamp[0x1]; 733 u8 reserved_at_5[0x2]; 734 u8 wqe_vlan_insert[0x1]; 735 u8 self_lb_en_modifiable[0x1]; 736 u8 reserved_at_9[0x2]; 737 u8 max_lso_cap[0x5]; 738 u8 multi_pkt_send_wqe[0x2]; 739 u8 wqe_inline_mode[0x2]; 740 u8 rss_ind_tbl_cap[0x4]; 741 u8 reg_umr_sq[0x1]; 742 u8 scatter_fcs[0x1]; 743 u8 enhanced_multi_pkt_send_wqe[0x1]; 744 u8 tunnel_lso_const_out_ip_id[0x1]; 745 u8 reserved_at_1c[0x2]; 746 u8 tunnel_stateless_gre[0x1]; 747 u8 tunnel_stateless_vxlan[0x1]; 748 749 u8 swp[0x1]; 750 u8 swp_csum[0x1]; 751 u8 swp_lso[0x1]; 752 u8 reserved_at_23[0xd]; 753 u8 max_vxlan_udp_ports[0x8]; 754 u8 reserved_at_38[0x6]; 755 u8 max_geneve_opt_len[0x1]; 756 u8 tunnel_stateless_geneve_rx[0x1]; 757 758 u8 reserved_at_40[0x10]; 759 u8 lro_min_mss_size[0x10]; 760 761 u8 reserved_at_60[0x120]; 762 763 u8 lro_timer_supported_periods[4][0x20]; 764 765 u8 reserved_at_200[0x600]; 766 }; 767 768 struct mlx5_ifc_roce_cap_bits { 769 u8 roce_apm[0x1]; 770 u8 reserved_at_1[0x1f]; 771 772 u8 reserved_at_20[0x60]; 773 774 u8 reserved_at_80[0xc]; 775 u8 l3_type[0x4]; 776 u8 reserved_at_90[0x8]; 777 u8 roce_version[0x8]; 778 779 u8 reserved_at_a0[0x10]; 780 u8 r_roce_dest_udp_port[0x10]; 781 782 u8 r_roce_max_src_udp_port[0x10]; 783 u8 r_roce_min_src_udp_port[0x10]; 784 785 u8 reserved_at_e0[0x10]; 786 u8 roce_address_table_size[0x10]; 787 788 u8 reserved_at_100[0x700]; 789 }; 790 791 struct mlx5_ifc_device_mem_cap_bits { 792 u8 memic[0x1]; 793 u8 reserved_at_1[0x1f]; 794 795 u8 reserved_at_20[0xb]; 796 u8 log_min_memic_alloc_size[0x5]; 797 u8 reserved_at_30[0x8]; 798 u8 log_max_memic_addr_alignment[0x8]; 799 800 u8 memic_bar_start_addr[0x40]; 801 802 u8 memic_bar_size[0x20]; 803 804 u8 max_memic_size[0x20]; 805 806 u8 steering_sw_icm_start_address[0x40]; 807 808 u8 reserved_at_100[0x8]; 809 u8 log_header_modify_sw_icm_size[0x8]; 810 u8 reserved_at_110[0x2]; 811 u8 log_sw_icm_alloc_granularity[0x6]; 812 u8 log_steering_sw_icm_size[0x8]; 813 814 u8 reserved_at_120[0x20]; 815 816 u8 header_modify_sw_icm_start_address[0x40]; 817 818 u8 reserved_at_180[0x680]; 819 }; 820 821 enum { 822 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 823 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 824 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 825 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 826 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 827 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 828 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 829 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 830 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 831 }; 832 833 enum { 834 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 835 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 836 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 837 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 838 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 839 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 840 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 841 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 842 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 843 }; 844 845 struct mlx5_ifc_atomic_caps_bits { 846 u8 reserved_at_0[0x40]; 847 848 u8 atomic_req_8B_endianness_mode[0x2]; 849 u8 reserved_at_42[0x4]; 850 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 851 852 u8 reserved_at_47[0x19]; 853 854 u8 reserved_at_60[0x20]; 855 856 u8 reserved_at_80[0x10]; 857 u8 atomic_operations[0x10]; 858 859 u8 reserved_at_a0[0x10]; 860 u8 atomic_size_qp[0x10]; 861 862 u8 reserved_at_c0[0x10]; 863 u8 atomic_size_dc[0x10]; 864 865 u8 reserved_at_e0[0x720]; 866 }; 867 868 struct mlx5_ifc_odp_cap_bits { 869 u8 reserved_at_0[0x40]; 870 871 u8 sig[0x1]; 872 u8 reserved_at_41[0x1f]; 873 874 u8 reserved_at_60[0x20]; 875 876 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 877 878 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 879 880 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 881 882 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 883 884 u8 reserved_at_100[0x700]; 885 }; 886 887 struct mlx5_ifc_calc_op { 888 u8 reserved_at_0[0x10]; 889 u8 reserved_at_10[0x9]; 890 u8 op_swap_endianness[0x1]; 891 u8 op_min[0x1]; 892 u8 op_xor[0x1]; 893 u8 op_or[0x1]; 894 u8 op_and[0x1]; 895 u8 op_max[0x1]; 896 u8 op_add[0x1]; 897 }; 898 899 struct mlx5_ifc_vector_calc_cap_bits { 900 u8 calc_matrix[0x1]; 901 u8 reserved_at_1[0x1f]; 902 u8 reserved_at_20[0x8]; 903 u8 max_vec_count[0x8]; 904 u8 reserved_at_30[0xd]; 905 u8 max_chunk_size[0x3]; 906 struct mlx5_ifc_calc_op calc0; 907 struct mlx5_ifc_calc_op calc1; 908 struct mlx5_ifc_calc_op calc2; 909 struct mlx5_ifc_calc_op calc3; 910 911 u8 reserved_at_c0[0x720]; 912 }; 913 914 enum { 915 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 916 MLX5_WQ_TYPE_CYCLIC = 0x1, 917 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 918 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 919 }; 920 921 enum { 922 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 923 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 924 }; 925 926 enum { 927 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 928 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 929 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 930 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 931 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 932 }; 933 934 enum { 935 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 936 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 937 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 938 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 939 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 940 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 941 }; 942 943 enum { 944 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 945 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 946 }; 947 948 enum { 949 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 950 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 951 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 952 }; 953 954 enum { 955 MLX5_CAP_PORT_TYPE_IB = 0x0, 956 MLX5_CAP_PORT_TYPE_ETH = 0x1, 957 }; 958 959 enum { 960 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 961 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 962 MLX5_CAP_UMR_FENCE_NONE = 0x2, 963 }; 964 965 enum { 966 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 967 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 968 }; 969 970 struct mlx5_ifc_cmd_hca_cap_bits { 971 u8 reserved_at_0[0x30]; 972 u8 vhca_id[0x10]; 973 974 u8 reserved_at_40[0x40]; 975 976 u8 log_max_srq_sz[0x8]; 977 u8 log_max_qp_sz[0x8]; 978 u8 reserved_at_90[0x8]; 979 u8 prio_tag_required[0x1]; 980 u8 reserved_at_99[0x2]; 981 u8 log_max_qp[0x5]; 982 983 u8 reserved_at_a0[0xb]; 984 u8 log_max_srq[0x5]; 985 u8 reserved_at_b0[0x10]; 986 987 u8 reserved_at_c0[0x8]; 988 u8 log_max_cq_sz[0x8]; 989 u8 reserved_at_d0[0xb]; 990 u8 log_max_cq[0x5]; 991 992 u8 log_max_eq_sz[0x8]; 993 u8 reserved_at_e8[0x2]; 994 u8 log_max_mkey[0x6]; 995 u8 reserved_at_f0[0x8]; 996 u8 dump_fill_mkey[0x1]; 997 u8 reserved_at_f9[0x2]; 998 u8 fast_teardown[0x1]; 999 u8 log_max_eq[0x4]; 1000 1001 u8 max_indirection[0x8]; 1002 u8 fixed_buffer_size[0x1]; 1003 u8 log_max_mrw_sz[0x7]; 1004 u8 force_teardown[0x1]; 1005 u8 reserved_at_111[0x1]; 1006 u8 log_max_bsf_list_size[0x6]; 1007 u8 umr_extended_translation_offset[0x1]; 1008 u8 null_mkey[0x1]; 1009 u8 log_max_klm_list_size[0x6]; 1010 1011 u8 reserved_at_120[0xa]; 1012 u8 log_max_ra_req_dc[0x6]; 1013 u8 reserved_at_130[0xa]; 1014 u8 log_max_ra_res_dc[0x6]; 1015 1016 u8 reserved_at_140[0xa]; 1017 u8 log_max_ra_req_qp[0x6]; 1018 u8 reserved_at_150[0xa]; 1019 u8 log_max_ra_res_qp[0x6]; 1020 1021 u8 end_pad[0x1]; 1022 u8 cc_query_allowed[0x1]; 1023 u8 cc_modify_allowed[0x1]; 1024 u8 start_pad[0x1]; 1025 u8 cache_line_128byte[0x1]; 1026 u8 reserved_at_165[0xa]; 1027 u8 qcam_reg[0x1]; 1028 u8 gid_table_size[0x10]; 1029 1030 u8 out_of_seq_cnt[0x1]; 1031 u8 vport_counters[0x1]; 1032 u8 retransmission_q_counters[0x1]; 1033 u8 debug[0x1]; 1034 u8 modify_rq_counter_set_id[0x1]; 1035 u8 rq_delay_drop[0x1]; 1036 u8 max_qp_cnt[0xa]; 1037 u8 pkey_table_size[0x10]; 1038 1039 u8 vport_group_manager[0x1]; 1040 u8 vhca_group_manager[0x1]; 1041 u8 ib_virt[0x1]; 1042 u8 eth_virt[0x1]; 1043 u8 vnic_env_queue_counters[0x1]; 1044 u8 ets[0x1]; 1045 u8 nic_flow_table[0x1]; 1046 u8 eswitch_manager[0x1]; 1047 u8 device_memory[0x1]; 1048 u8 mcam_reg[0x1]; 1049 u8 pcam_reg[0x1]; 1050 u8 local_ca_ack_delay[0x5]; 1051 u8 port_module_event[0x1]; 1052 u8 enhanced_error_q_counters[0x1]; 1053 u8 ports_check[0x1]; 1054 u8 reserved_at_1b3[0x1]; 1055 u8 disable_link_up[0x1]; 1056 u8 beacon_led[0x1]; 1057 u8 port_type[0x2]; 1058 u8 num_ports[0x8]; 1059 1060 u8 reserved_at_1c0[0x1]; 1061 u8 pps[0x1]; 1062 u8 pps_modify[0x1]; 1063 u8 log_max_msg[0x5]; 1064 u8 reserved_at_1c8[0x4]; 1065 u8 max_tc[0x4]; 1066 u8 temp_warn_event[0x1]; 1067 u8 dcbx[0x1]; 1068 u8 general_notification_event[0x1]; 1069 u8 reserved_at_1d3[0x2]; 1070 u8 fpga[0x1]; 1071 u8 rol_s[0x1]; 1072 u8 rol_g[0x1]; 1073 u8 reserved_at_1d8[0x1]; 1074 u8 wol_s[0x1]; 1075 u8 wol_g[0x1]; 1076 u8 wol_a[0x1]; 1077 u8 wol_b[0x1]; 1078 u8 wol_m[0x1]; 1079 u8 wol_u[0x1]; 1080 u8 wol_p[0x1]; 1081 1082 u8 stat_rate_support[0x10]; 1083 u8 reserved_at_1f0[0xc]; 1084 u8 cqe_version[0x4]; 1085 1086 u8 compact_address_vector[0x1]; 1087 u8 striding_rq[0x1]; 1088 u8 reserved_at_202[0x1]; 1089 u8 ipoib_enhanced_offloads[0x1]; 1090 u8 ipoib_basic_offloads[0x1]; 1091 u8 reserved_at_205[0x1]; 1092 u8 repeated_block_disabled[0x1]; 1093 u8 umr_modify_entity_size_disabled[0x1]; 1094 u8 umr_modify_atomic_disabled[0x1]; 1095 u8 umr_indirect_mkey_disabled[0x1]; 1096 u8 umr_fence[0x2]; 1097 u8 dc_req_scat_data_cqe[0x1]; 1098 u8 reserved_at_20d[0x2]; 1099 u8 drain_sigerr[0x1]; 1100 u8 cmdif_checksum[0x2]; 1101 u8 sigerr_cqe[0x1]; 1102 u8 reserved_at_213[0x1]; 1103 u8 wq_signature[0x1]; 1104 u8 sctr_data_cqe[0x1]; 1105 u8 reserved_at_216[0x1]; 1106 u8 sho[0x1]; 1107 u8 tph[0x1]; 1108 u8 rf[0x1]; 1109 u8 dct[0x1]; 1110 u8 qos[0x1]; 1111 u8 eth_net_offloads[0x1]; 1112 u8 roce[0x1]; 1113 u8 atomic[0x1]; 1114 u8 reserved_at_21f[0x1]; 1115 1116 u8 cq_oi[0x1]; 1117 u8 cq_resize[0x1]; 1118 u8 cq_moderation[0x1]; 1119 u8 reserved_at_223[0x3]; 1120 u8 cq_eq_remap[0x1]; 1121 u8 pg[0x1]; 1122 u8 block_lb_mc[0x1]; 1123 u8 reserved_at_229[0x1]; 1124 u8 scqe_break_moderation[0x1]; 1125 u8 cq_period_start_from_cqe[0x1]; 1126 u8 cd[0x1]; 1127 u8 reserved_at_22d[0x1]; 1128 u8 apm[0x1]; 1129 u8 vector_calc[0x1]; 1130 u8 umr_ptr_rlky[0x1]; 1131 u8 imaicl[0x1]; 1132 u8 qp_packet_based[0x1]; 1133 u8 reserved_at_233[0x3]; 1134 u8 qkv[0x1]; 1135 u8 pkv[0x1]; 1136 u8 set_deth_sqpn[0x1]; 1137 u8 reserved_at_239[0x3]; 1138 u8 xrc[0x1]; 1139 u8 ud[0x1]; 1140 u8 uc[0x1]; 1141 u8 rc[0x1]; 1142 1143 u8 uar_4k[0x1]; 1144 u8 reserved_at_241[0x9]; 1145 u8 uar_sz[0x6]; 1146 u8 reserved_at_250[0x8]; 1147 u8 log_pg_sz[0x8]; 1148 1149 u8 bf[0x1]; 1150 u8 driver_version[0x1]; 1151 u8 pad_tx_eth_packet[0x1]; 1152 u8 reserved_at_263[0x8]; 1153 u8 log_bf_reg_size[0x5]; 1154 1155 u8 reserved_at_270[0xb]; 1156 u8 lag_master[0x1]; 1157 u8 num_lag_ports[0x4]; 1158 1159 u8 reserved_at_280[0x10]; 1160 u8 max_wqe_sz_sq[0x10]; 1161 1162 u8 reserved_at_2a0[0x10]; 1163 u8 max_wqe_sz_rq[0x10]; 1164 1165 u8 max_flow_counter_31_16[0x10]; 1166 u8 max_wqe_sz_sq_dc[0x10]; 1167 1168 u8 reserved_at_2e0[0x7]; 1169 u8 max_qp_mcg[0x19]; 1170 1171 u8 reserved_at_300[0x18]; 1172 u8 log_max_mcg[0x8]; 1173 1174 u8 reserved_at_320[0x3]; 1175 u8 log_max_transport_domain[0x5]; 1176 u8 reserved_at_328[0x3]; 1177 u8 log_max_pd[0x5]; 1178 u8 reserved_at_330[0xb]; 1179 u8 log_max_xrcd[0x5]; 1180 1181 u8 nic_receive_steering_discard[0x1]; 1182 u8 receive_discard_vport_down[0x1]; 1183 u8 transmit_discard_vport_down[0x1]; 1184 u8 reserved_at_343[0x5]; 1185 u8 log_max_flow_counter_bulk[0x8]; 1186 u8 max_flow_counter_15_0[0x10]; 1187 1188 1189 u8 reserved_at_360[0x3]; 1190 u8 log_max_rq[0x5]; 1191 u8 reserved_at_368[0x3]; 1192 u8 log_max_sq[0x5]; 1193 u8 reserved_at_370[0x3]; 1194 u8 log_max_tir[0x5]; 1195 u8 reserved_at_378[0x3]; 1196 u8 log_max_tis[0x5]; 1197 1198 u8 basic_cyclic_rcv_wqe[0x1]; 1199 u8 reserved_at_381[0x2]; 1200 u8 log_max_rmp[0x5]; 1201 u8 reserved_at_388[0x3]; 1202 u8 log_max_rqt[0x5]; 1203 u8 reserved_at_390[0x3]; 1204 u8 log_max_rqt_size[0x5]; 1205 u8 reserved_at_398[0x3]; 1206 u8 log_max_tis_per_sq[0x5]; 1207 1208 u8 ext_stride_num_range[0x1]; 1209 u8 reserved_at_3a1[0x2]; 1210 u8 log_max_stride_sz_rq[0x5]; 1211 u8 reserved_at_3a8[0x3]; 1212 u8 log_min_stride_sz_rq[0x5]; 1213 u8 reserved_at_3b0[0x3]; 1214 u8 log_max_stride_sz_sq[0x5]; 1215 u8 reserved_at_3b8[0x3]; 1216 u8 log_min_stride_sz_sq[0x5]; 1217 1218 u8 hairpin[0x1]; 1219 u8 reserved_at_3c1[0x2]; 1220 u8 log_max_hairpin_queues[0x5]; 1221 u8 reserved_at_3c8[0x3]; 1222 u8 log_max_hairpin_wq_data_sz[0x5]; 1223 u8 reserved_at_3d0[0x3]; 1224 u8 log_max_hairpin_num_packets[0x5]; 1225 u8 reserved_at_3d8[0x3]; 1226 u8 log_max_wq_sz[0x5]; 1227 1228 u8 nic_vport_change_event[0x1]; 1229 u8 disable_local_lb_uc[0x1]; 1230 u8 disable_local_lb_mc[0x1]; 1231 u8 log_min_hairpin_wq_data_sz[0x5]; 1232 u8 reserved_at_3e8[0x3]; 1233 u8 log_max_vlan_list[0x5]; 1234 u8 reserved_at_3f0[0x3]; 1235 u8 log_max_current_mc_list[0x5]; 1236 u8 reserved_at_3f8[0x3]; 1237 u8 log_max_current_uc_list[0x5]; 1238 1239 u8 general_obj_types[0x40]; 1240 1241 u8 reserved_at_440[0x20]; 1242 1243 u8 reserved_at_460[0x3]; 1244 u8 log_max_uctx[0x5]; 1245 u8 reserved_at_468[0x3]; 1246 u8 log_max_umem[0x5]; 1247 u8 max_num_eqs[0x10]; 1248 1249 u8 reserved_at_480[0x3]; 1250 u8 log_max_l2_table[0x5]; 1251 u8 reserved_at_488[0x8]; 1252 u8 log_uar_page_sz[0x10]; 1253 1254 u8 reserved_at_4a0[0x20]; 1255 u8 device_frequency_mhz[0x20]; 1256 u8 device_frequency_khz[0x20]; 1257 1258 u8 reserved_at_500[0x20]; 1259 u8 num_of_uars_per_page[0x20]; 1260 1261 u8 flex_parser_protocols[0x20]; 1262 1263 u8 max_geneve_tlv_options[0x8]; 1264 u8 reserved_at_568[0x3]; 1265 u8 max_geneve_tlv_option_data_len[0x5]; 1266 u8 reserved_at_570[0x10]; 1267 1268 u8 reserved_at_580[0x3c]; 1269 u8 mini_cqe_resp_stride_index[0x1]; 1270 u8 cqe_128_always[0x1]; 1271 u8 cqe_compression_128[0x1]; 1272 u8 cqe_compression[0x1]; 1273 1274 u8 cqe_compression_timeout[0x10]; 1275 u8 cqe_compression_max_num[0x10]; 1276 1277 u8 reserved_at_5e0[0x10]; 1278 u8 tag_matching[0x1]; 1279 u8 rndv_offload_rc[0x1]; 1280 u8 rndv_offload_dc[0x1]; 1281 u8 log_tag_matching_list_sz[0x5]; 1282 u8 reserved_at_5f8[0x3]; 1283 u8 log_max_xrq[0x5]; 1284 1285 u8 affiliate_nic_vport_criteria[0x8]; 1286 u8 native_port_num[0x8]; 1287 u8 num_vhca_ports[0x8]; 1288 u8 reserved_at_618[0x6]; 1289 u8 sw_owner_id[0x1]; 1290 u8 reserved_at_61f[0x1]; 1291 1292 u8 max_num_of_monitor_counters[0x10]; 1293 u8 num_ppcnt_monitor_counters[0x10]; 1294 1295 u8 reserved_at_640[0x10]; 1296 u8 num_q_monitor_counters[0x10]; 1297 1298 u8 reserved_at_660[0x40]; 1299 1300 u8 uctx_cap[0x20]; 1301 1302 u8 reserved_at_6c0[0x4]; 1303 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1304 u8 reserved_at_6c8[0x138]; 1305 }; 1306 1307 enum mlx5_flow_destination_type { 1308 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1309 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1310 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1311 1312 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1313 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1314 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1315 }; 1316 1317 enum mlx5_flow_table_miss_action { 1318 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1319 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1320 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1321 }; 1322 1323 struct mlx5_ifc_dest_format_struct_bits { 1324 u8 destination_type[0x8]; 1325 u8 destination_id[0x18]; 1326 1327 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1328 u8 packet_reformat[0x1]; 1329 u8 reserved_at_22[0xe]; 1330 u8 destination_eswitch_owner_vhca_id[0x10]; 1331 }; 1332 1333 struct mlx5_ifc_flow_counter_list_bits { 1334 u8 flow_counter_id[0x20]; 1335 1336 u8 reserved_at_20[0x20]; 1337 }; 1338 1339 struct mlx5_ifc_extended_dest_format_bits { 1340 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1341 1342 u8 packet_reformat_id[0x20]; 1343 1344 u8 reserved_at_60[0x20]; 1345 }; 1346 1347 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1348 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1349 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1350 u8 reserved_at_0[0x40]; 1351 }; 1352 1353 struct mlx5_ifc_fte_match_param_bits { 1354 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1355 1356 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1357 1358 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1359 1360 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1361 1362 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1363 1364 u8 reserved_at_a00[0x600]; 1365 }; 1366 1367 enum { 1368 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1369 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1370 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1371 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1372 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1373 }; 1374 1375 struct mlx5_ifc_rx_hash_field_select_bits { 1376 u8 l3_prot_type[0x1]; 1377 u8 l4_prot_type[0x1]; 1378 u8 selected_fields[0x1e]; 1379 }; 1380 1381 enum { 1382 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1383 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1384 }; 1385 1386 enum { 1387 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1388 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1389 }; 1390 1391 struct mlx5_ifc_wq_bits { 1392 u8 wq_type[0x4]; 1393 u8 wq_signature[0x1]; 1394 u8 end_padding_mode[0x2]; 1395 u8 cd_slave[0x1]; 1396 u8 reserved_at_8[0x18]; 1397 1398 u8 hds_skip_first_sge[0x1]; 1399 u8 log2_hds_buf_size[0x3]; 1400 u8 reserved_at_24[0x7]; 1401 u8 page_offset[0x5]; 1402 u8 lwm[0x10]; 1403 1404 u8 reserved_at_40[0x8]; 1405 u8 pd[0x18]; 1406 1407 u8 reserved_at_60[0x8]; 1408 u8 uar_page[0x18]; 1409 1410 u8 dbr_addr[0x40]; 1411 1412 u8 hw_counter[0x20]; 1413 1414 u8 sw_counter[0x20]; 1415 1416 u8 reserved_at_100[0xc]; 1417 u8 log_wq_stride[0x4]; 1418 u8 reserved_at_110[0x3]; 1419 u8 log_wq_pg_sz[0x5]; 1420 u8 reserved_at_118[0x3]; 1421 u8 log_wq_sz[0x5]; 1422 1423 u8 dbr_umem_valid[0x1]; 1424 u8 wq_umem_valid[0x1]; 1425 u8 reserved_at_122[0x1]; 1426 u8 log_hairpin_num_packets[0x5]; 1427 u8 reserved_at_128[0x3]; 1428 u8 log_hairpin_data_sz[0x5]; 1429 1430 u8 reserved_at_130[0x4]; 1431 u8 log_wqe_num_of_strides[0x4]; 1432 u8 two_byte_shift_en[0x1]; 1433 u8 reserved_at_139[0x4]; 1434 u8 log_wqe_stride_size[0x3]; 1435 1436 u8 reserved_at_140[0x4c0]; 1437 1438 struct mlx5_ifc_cmd_pas_bits pas[0]; 1439 }; 1440 1441 struct mlx5_ifc_rq_num_bits { 1442 u8 reserved_at_0[0x8]; 1443 u8 rq_num[0x18]; 1444 }; 1445 1446 struct mlx5_ifc_mac_address_layout_bits { 1447 u8 reserved_at_0[0x10]; 1448 u8 mac_addr_47_32[0x10]; 1449 1450 u8 mac_addr_31_0[0x20]; 1451 }; 1452 1453 struct mlx5_ifc_vlan_layout_bits { 1454 u8 reserved_at_0[0x14]; 1455 u8 vlan[0x0c]; 1456 1457 u8 reserved_at_20[0x20]; 1458 }; 1459 1460 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1461 u8 reserved_at_0[0xa0]; 1462 1463 u8 min_time_between_cnps[0x20]; 1464 1465 u8 reserved_at_c0[0x12]; 1466 u8 cnp_dscp[0x6]; 1467 u8 reserved_at_d8[0x4]; 1468 u8 cnp_prio_mode[0x1]; 1469 u8 cnp_802p_prio[0x3]; 1470 1471 u8 reserved_at_e0[0x720]; 1472 }; 1473 1474 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1475 u8 reserved_at_0[0x60]; 1476 1477 u8 reserved_at_60[0x4]; 1478 u8 clamp_tgt_rate[0x1]; 1479 u8 reserved_at_65[0x3]; 1480 u8 clamp_tgt_rate_after_time_inc[0x1]; 1481 u8 reserved_at_69[0x17]; 1482 1483 u8 reserved_at_80[0x20]; 1484 1485 u8 rpg_time_reset[0x20]; 1486 1487 u8 rpg_byte_reset[0x20]; 1488 1489 u8 rpg_threshold[0x20]; 1490 1491 u8 rpg_max_rate[0x20]; 1492 1493 u8 rpg_ai_rate[0x20]; 1494 1495 u8 rpg_hai_rate[0x20]; 1496 1497 u8 rpg_gd[0x20]; 1498 1499 u8 rpg_min_dec_fac[0x20]; 1500 1501 u8 rpg_min_rate[0x20]; 1502 1503 u8 reserved_at_1c0[0xe0]; 1504 1505 u8 rate_to_set_on_first_cnp[0x20]; 1506 1507 u8 dce_tcp_g[0x20]; 1508 1509 u8 dce_tcp_rtt[0x20]; 1510 1511 u8 rate_reduce_monitor_period[0x20]; 1512 1513 u8 reserved_at_320[0x20]; 1514 1515 u8 initial_alpha_value[0x20]; 1516 1517 u8 reserved_at_360[0x4a0]; 1518 }; 1519 1520 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1521 u8 reserved_at_0[0x80]; 1522 1523 u8 rppp_max_rps[0x20]; 1524 1525 u8 rpg_time_reset[0x20]; 1526 1527 u8 rpg_byte_reset[0x20]; 1528 1529 u8 rpg_threshold[0x20]; 1530 1531 u8 rpg_max_rate[0x20]; 1532 1533 u8 rpg_ai_rate[0x20]; 1534 1535 u8 rpg_hai_rate[0x20]; 1536 1537 u8 rpg_gd[0x20]; 1538 1539 u8 rpg_min_dec_fac[0x20]; 1540 1541 u8 rpg_min_rate[0x20]; 1542 1543 u8 reserved_at_1c0[0x640]; 1544 }; 1545 1546 enum { 1547 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1548 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1549 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1550 }; 1551 1552 struct mlx5_ifc_resize_field_select_bits { 1553 u8 resize_field_select[0x20]; 1554 }; 1555 1556 enum { 1557 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1558 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1559 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1560 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1561 }; 1562 1563 struct mlx5_ifc_modify_field_select_bits { 1564 u8 modify_field_select[0x20]; 1565 }; 1566 1567 struct mlx5_ifc_field_select_r_roce_np_bits { 1568 u8 field_select_r_roce_np[0x20]; 1569 }; 1570 1571 struct mlx5_ifc_field_select_r_roce_rp_bits { 1572 u8 field_select_r_roce_rp[0x20]; 1573 }; 1574 1575 enum { 1576 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1577 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1578 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1579 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1580 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1581 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1582 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1583 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1584 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1585 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1586 }; 1587 1588 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1589 u8 field_select_8021qaurp[0x20]; 1590 }; 1591 1592 struct mlx5_ifc_phys_layer_cntrs_bits { 1593 u8 time_since_last_clear_high[0x20]; 1594 1595 u8 time_since_last_clear_low[0x20]; 1596 1597 u8 symbol_errors_high[0x20]; 1598 1599 u8 symbol_errors_low[0x20]; 1600 1601 u8 sync_headers_errors_high[0x20]; 1602 1603 u8 sync_headers_errors_low[0x20]; 1604 1605 u8 edpl_bip_errors_lane0_high[0x20]; 1606 1607 u8 edpl_bip_errors_lane0_low[0x20]; 1608 1609 u8 edpl_bip_errors_lane1_high[0x20]; 1610 1611 u8 edpl_bip_errors_lane1_low[0x20]; 1612 1613 u8 edpl_bip_errors_lane2_high[0x20]; 1614 1615 u8 edpl_bip_errors_lane2_low[0x20]; 1616 1617 u8 edpl_bip_errors_lane3_high[0x20]; 1618 1619 u8 edpl_bip_errors_lane3_low[0x20]; 1620 1621 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1622 1623 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1624 1625 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1626 1627 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1628 1629 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1630 1631 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1632 1633 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1634 1635 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1636 1637 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1638 1639 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1640 1641 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1642 1643 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1644 1645 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1646 1647 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1648 1649 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1650 1651 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1652 1653 u8 rs_fec_corrected_blocks_high[0x20]; 1654 1655 u8 rs_fec_corrected_blocks_low[0x20]; 1656 1657 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1658 1659 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1660 1661 u8 rs_fec_no_errors_blocks_high[0x20]; 1662 1663 u8 rs_fec_no_errors_blocks_low[0x20]; 1664 1665 u8 rs_fec_single_error_blocks_high[0x20]; 1666 1667 u8 rs_fec_single_error_blocks_low[0x20]; 1668 1669 u8 rs_fec_corrected_symbols_total_high[0x20]; 1670 1671 u8 rs_fec_corrected_symbols_total_low[0x20]; 1672 1673 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1674 1675 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1676 1677 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1678 1679 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1680 1681 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1682 1683 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1684 1685 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1686 1687 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1688 1689 u8 link_down_events[0x20]; 1690 1691 u8 successful_recovery_events[0x20]; 1692 1693 u8 reserved_at_640[0x180]; 1694 }; 1695 1696 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1697 u8 time_since_last_clear_high[0x20]; 1698 1699 u8 time_since_last_clear_low[0x20]; 1700 1701 u8 phy_received_bits_high[0x20]; 1702 1703 u8 phy_received_bits_low[0x20]; 1704 1705 u8 phy_symbol_errors_high[0x20]; 1706 1707 u8 phy_symbol_errors_low[0x20]; 1708 1709 u8 phy_corrected_bits_high[0x20]; 1710 1711 u8 phy_corrected_bits_low[0x20]; 1712 1713 u8 phy_corrected_bits_lane0_high[0x20]; 1714 1715 u8 phy_corrected_bits_lane0_low[0x20]; 1716 1717 u8 phy_corrected_bits_lane1_high[0x20]; 1718 1719 u8 phy_corrected_bits_lane1_low[0x20]; 1720 1721 u8 phy_corrected_bits_lane2_high[0x20]; 1722 1723 u8 phy_corrected_bits_lane2_low[0x20]; 1724 1725 u8 phy_corrected_bits_lane3_high[0x20]; 1726 1727 u8 phy_corrected_bits_lane3_low[0x20]; 1728 1729 u8 reserved_at_200[0x5c0]; 1730 }; 1731 1732 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1733 u8 symbol_error_counter[0x10]; 1734 1735 u8 link_error_recovery_counter[0x8]; 1736 1737 u8 link_downed_counter[0x8]; 1738 1739 u8 port_rcv_errors[0x10]; 1740 1741 u8 port_rcv_remote_physical_errors[0x10]; 1742 1743 u8 port_rcv_switch_relay_errors[0x10]; 1744 1745 u8 port_xmit_discards[0x10]; 1746 1747 u8 port_xmit_constraint_errors[0x8]; 1748 1749 u8 port_rcv_constraint_errors[0x8]; 1750 1751 u8 reserved_at_70[0x8]; 1752 1753 u8 link_overrun_errors[0x8]; 1754 1755 u8 reserved_at_80[0x10]; 1756 1757 u8 vl_15_dropped[0x10]; 1758 1759 u8 reserved_at_a0[0x80]; 1760 1761 u8 port_xmit_wait[0x20]; 1762 }; 1763 1764 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1765 u8 transmit_queue_high[0x20]; 1766 1767 u8 transmit_queue_low[0x20]; 1768 1769 u8 reserved_at_40[0x780]; 1770 }; 1771 1772 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1773 u8 rx_octets_high[0x20]; 1774 1775 u8 rx_octets_low[0x20]; 1776 1777 u8 reserved_at_40[0xc0]; 1778 1779 u8 rx_frames_high[0x20]; 1780 1781 u8 rx_frames_low[0x20]; 1782 1783 u8 tx_octets_high[0x20]; 1784 1785 u8 tx_octets_low[0x20]; 1786 1787 u8 reserved_at_180[0xc0]; 1788 1789 u8 tx_frames_high[0x20]; 1790 1791 u8 tx_frames_low[0x20]; 1792 1793 u8 rx_pause_high[0x20]; 1794 1795 u8 rx_pause_low[0x20]; 1796 1797 u8 rx_pause_duration_high[0x20]; 1798 1799 u8 rx_pause_duration_low[0x20]; 1800 1801 u8 tx_pause_high[0x20]; 1802 1803 u8 tx_pause_low[0x20]; 1804 1805 u8 tx_pause_duration_high[0x20]; 1806 1807 u8 tx_pause_duration_low[0x20]; 1808 1809 u8 rx_pause_transition_high[0x20]; 1810 1811 u8 rx_pause_transition_low[0x20]; 1812 1813 u8 reserved_at_3c0[0x40]; 1814 1815 u8 device_stall_minor_watermark_cnt_high[0x20]; 1816 1817 u8 device_stall_minor_watermark_cnt_low[0x20]; 1818 1819 u8 device_stall_critical_watermark_cnt_high[0x20]; 1820 1821 u8 device_stall_critical_watermark_cnt_low[0x20]; 1822 1823 u8 reserved_at_480[0x340]; 1824 }; 1825 1826 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1827 u8 port_transmit_wait_high[0x20]; 1828 1829 u8 port_transmit_wait_low[0x20]; 1830 1831 u8 reserved_at_40[0x100]; 1832 1833 u8 rx_buffer_almost_full_high[0x20]; 1834 1835 u8 rx_buffer_almost_full_low[0x20]; 1836 1837 u8 rx_buffer_full_high[0x20]; 1838 1839 u8 rx_buffer_full_low[0x20]; 1840 1841 u8 rx_icrc_encapsulated_high[0x20]; 1842 1843 u8 rx_icrc_encapsulated_low[0x20]; 1844 1845 u8 reserved_at_200[0x5c0]; 1846 }; 1847 1848 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1849 u8 dot3stats_alignment_errors_high[0x20]; 1850 1851 u8 dot3stats_alignment_errors_low[0x20]; 1852 1853 u8 dot3stats_fcs_errors_high[0x20]; 1854 1855 u8 dot3stats_fcs_errors_low[0x20]; 1856 1857 u8 dot3stats_single_collision_frames_high[0x20]; 1858 1859 u8 dot3stats_single_collision_frames_low[0x20]; 1860 1861 u8 dot3stats_multiple_collision_frames_high[0x20]; 1862 1863 u8 dot3stats_multiple_collision_frames_low[0x20]; 1864 1865 u8 dot3stats_sqe_test_errors_high[0x20]; 1866 1867 u8 dot3stats_sqe_test_errors_low[0x20]; 1868 1869 u8 dot3stats_deferred_transmissions_high[0x20]; 1870 1871 u8 dot3stats_deferred_transmissions_low[0x20]; 1872 1873 u8 dot3stats_late_collisions_high[0x20]; 1874 1875 u8 dot3stats_late_collisions_low[0x20]; 1876 1877 u8 dot3stats_excessive_collisions_high[0x20]; 1878 1879 u8 dot3stats_excessive_collisions_low[0x20]; 1880 1881 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1882 1883 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1884 1885 u8 dot3stats_carrier_sense_errors_high[0x20]; 1886 1887 u8 dot3stats_carrier_sense_errors_low[0x20]; 1888 1889 u8 dot3stats_frame_too_longs_high[0x20]; 1890 1891 u8 dot3stats_frame_too_longs_low[0x20]; 1892 1893 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1894 1895 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1896 1897 u8 dot3stats_symbol_errors_high[0x20]; 1898 1899 u8 dot3stats_symbol_errors_low[0x20]; 1900 1901 u8 dot3control_in_unknown_opcodes_high[0x20]; 1902 1903 u8 dot3control_in_unknown_opcodes_low[0x20]; 1904 1905 u8 dot3in_pause_frames_high[0x20]; 1906 1907 u8 dot3in_pause_frames_low[0x20]; 1908 1909 u8 dot3out_pause_frames_high[0x20]; 1910 1911 u8 dot3out_pause_frames_low[0x20]; 1912 1913 u8 reserved_at_400[0x3c0]; 1914 }; 1915 1916 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1917 u8 ether_stats_drop_events_high[0x20]; 1918 1919 u8 ether_stats_drop_events_low[0x20]; 1920 1921 u8 ether_stats_octets_high[0x20]; 1922 1923 u8 ether_stats_octets_low[0x20]; 1924 1925 u8 ether_stats_pkts_high[0x20]; 1926 1927 u8 ether_stats_pkts_low[0x20]; 1928 1929 u8 ether_stats_broadcast_pkts_high[0x20]; 1930 1931 u8 ether_stats_broadcast_pkts_low[0x20]; 1932 1933 u8 ether_stats_multicast_pkts_high[0x20]; 1934 1935 u8 ether_stats_multicast_pkts_low[0x20]; 1936 1937 u8 ether_stats_crc_align_errors_high[0x20]; 1938 1939 u8 ether_stats_crc_align_errors_low[0x20]; 1940 1941 u8 ether_stats_undersize_pkts_high[0x20]; 1942 1943 u8 ether_stats_undersize_pkts_low[0x20]; 1944 1945 u8 ether_stats_oversize_pkts_high[0x20]; 1946 1947 u8 ether_stats_oversize_pkts_low[0x20]; 1948 1949 u8 ether_stats_fragments_high[0x20]; 1950 1951 u8 ether_stats_fragments_low[0x20]; 1952 1953 u8 ether_stats_jabbers_high[0x20]; 1954 1955 u8 ether_stats_jabbers_low[0x20]; 1956 1957 u8 ether_stats_collisions_high[0x20]; 1958 1959 u8 ether_stats_collisions_low[0x20]; 1960 1961 u8 ether_stats_pkts64octets_high[0x20]; 1962 1963 u8 ether_stats_pkts64octets_low[0x20]; 1964 1965 u8 ether_stats_pkts65to127octets_high[0x20]; 1966 1967 u8 ether_stats_pkts65to127octets_low[0x20]; 1968 1969 u8 ether_stats_pkts128to255octets_high[0x20]; 1970 1971 u8 ether_stats_pkts128to255octets_low[0x20]; 1972 1973 u8 ether_stats_pkts256to511octets_high[0x20]; 1974 1975 u8 ether_stats_pkts256to511octets_low[0x20]; 1976 1977 u8 ether_stats_pkts512to1023octets_high[0x20]; 1978 1979 u8 ether_stats_pkts512to1023octets_low[0x20]; 1980 1981 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1982 1983 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1984 1985 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1986 1987 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1988 1989 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1990 1991 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1992 1993 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1994 1995 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1996 1997 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1998 1999 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2000 2001 u8 reserved_at_540[0x280]; 2002 }; 2003 2004 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2005 u8 if_in_octets_high[0x20]; 2006 2007 u8 if_in_octets_low[0x20]; 2008 2009 u8 if_in_ucast_pkts_high[0x20]; 2010 2011 u8 if_in_ucast_pkts_low[0x20]; 2012 2013 u8 if_in_discards_high[0x20]; 2014 2015 u8 if_in_discards_low[0x20]; 2016 2017 u8 if_in_errors_high[0x20]; 2018 2019 u8 if_in_errors_low[0x20]; 2020 2021 u8 if_in_unknown_protos_high[0x20]; 2022 2023 u8 if_in_unknown_protos_low[0x20]; 2024 2025 u8 if_out_octets_high[0x20]; 2026 2027 u8 if_out_octets_low[0x20]; 2028 2029 u8 if_out_ucast_pkts_high[0x20]; 2030 2031 u8 if_out_ucast_pkts_low[0x20]; 2032 2033 u8 if_out_discards_high[0x20]; 2034 2035 u8 if_out_discards_low[0x20]; 2036 2037 u8 if_out_errors_high[0x20]; 2038 2039 u8 if_out_errors_low[0x20]; 2040 2041 u8 if_in_multicast_pkts_high[0x20]; 2042 2043 u8 if_in_multicast_pkts_low[0x20]; 2044 2045 u8 if_in_broadcast_pkts_high[0x20]; 2046 2047 u8 if_in_broadcast_pkts_low[0x20]; 2048 2049 u8 if_out_multicast_pkts_high[0x20]; 2050 2051 u8 if_out_multicast_pkts_low[0x20]; 2052 2053 u8 if_out_broadcast_pkts_high[0x20]; 2054 2055 u8 if_out_broadcast_pkts_low[0x20]; 2056 2057 u8 reserved_at_340[0x480]; 2058 }; 2059 2060 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2061 u8 a_frames_transmitted_ok_high[0x20]; 2062 2063 u8 a_frames_transmitted_ok_low[0x20]; 2064 2065 u8 a_frames_received_ok_high[0x20]; 2066 2067 u8 a_frames_received_ok_low[0x20]; 2068 2069 u8 a_frame_check_sequence_errors_high[0x20]; 2070 2071 u8 a_frame_check_sequence_errors_low[0x20]; 2072 2073 u8 a_alignment_errors_high[0x20]; 2074 2075 u8 a_alignment_errors_low[0x20]; 2076 2077 u8 a_octets_transmitted_ok_high[0x20]; 2078 2079 u8 a_octets_transmitted_ok_low[0x20]; 2080 2081 u8 a_octets_received_ok_high[0x20]; 2082 2083 u8 a_octets_received_ok_low[0x20]; 2084 2085 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2086 2087 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2088 2089 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2090 2091 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2092 2093 u8 a_multicast_frames_received_ok_high[0x20]; 2094 2095 u8 a_multicast_frames_received_ok_low[0x20]; 2096 2097 u8 a_broadcast_frames_received_ok_high[0x20]; 2098 2099 u8 a_broadcast_frames_received_ok_low[0x20]; 2100 2101 u8 a_in_range_length_errors_high[0x20]; 2102 2103 u8 a_in_range_length_errors_low[0x20]; 2104 2105 u8 a_out_of_range_length_field_high[0x20]; 2106 2107 u8 a_out_of_range_length_field_low[0x20]; 2108 2109 u8 a_frame_too_long_errors_high[0x20]; 2110 2111 u8 a_frame_too_long_errors_low[0x20]; 2112 2113 u8 a_symbol_error_during_carrier_high[0x20]; 2114 2115 u8 a_symbol_error_during_carrier_low[0x20]; 2116 2117 u8 a_mac_control_frames_transmitted_high[0x20]; 2118 2119 u8 a_mac_control_frames_transmitted_low[0x20]; 2120 2121 u8 a_mac_control_frames_received_high[0x20]; 2122 2123 u8 a_mac_control_frames_received_low[0x20]; 2124 2125 u8 a_unsupported_opcodes_received_high[0x20]; 2126 2127 u8 a_unsupported_opcodes_received_low[0x20]; 2128 2129 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2130 2131 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2132 2133 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2134 2135 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2136 2137 u8 reserved_at_4c0[0x300]; 2138 }; 2139 2140 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2141 u8 life_time_counter_high[0x20]; 2142 2143 u8 life_time_counter_low[0x20]; 2144 2145 u8 rx_errors[0x20]; 2146 2147 u8 tx_errors[0x20]; 2148 2149 u8 l0_to_recovery_eieos[0x20]; 2150 2151 u8 l0_to_recovery_ts[0x20]; 2152 2153 u8 l0_to_recovery_framing[0x20]; 2154 2155 u8 l0_to_recovery_retrain[0x20]; 2156 2157 u8 crc_error_dllp[0x20]; 2158 2159 u8 crc_error_tlp[0x20]; 2160 2161 u8 tx_overflow_buffer_pkt_high[0x20]; 2162 2163 u8 tx_overflow_buffer_pkt_low[0x20]; 2164 2165 u8 outbound_stalled_reads[0x20]; 2166 2167 u8 outbound_stalled_writes[0x20]; 2168 2169 u8 outbound_stalled_reads_events[0x20]; 2170 2171 u8 outbound_stalled_writes_events[0x20]; 2172 2173 u8 reserved_at_200[0x5c0]; 2174 }; 2175 2176 struct mlx5_ifc_cmd_inter_comp_event_bits { 2177 u8 command_completion_vector[0x20]; 2178 2179 u8 reserved_at_20[0xc0]; 2180 }; 2181 2182 struct mlx5_ifc_stall_vl_event_bits { 2183 u8 reserved_at_0[0x18]; 2184 u8 port_num[0x1]; 2185 u8 reserved_at_19[0x3]; 2186 u8 vl[0x4]; 2187 2188 u8 reserved_at_20[0xa0]; 2189 }; 2190 2191 struct mlx5_ifc_db_bf_congestion_event_bits { 2192 u8 event_subtype[0x8]; 2193 u8 reserved_at_8[0x8]; 2194 u8 congestion_level[0x8]; 2195 u8 reserved_at_18[0x8]; 2196 2197 u8 reserved_at_20[0xa0]; 2198 }; 2199 2200 struct mlx5_ifc_gpio_event_bits { 2201 u8 reserved_at_0[0x60]; 2202 2203 u8 gpio_event_hi[0x20]; 2204 2205 u8 gpio_event_lo[0x20]; 2206 2207 u8 reserved_at_a0[0x40]; 2208 }; 2209 2210 struct mlx5_ifc_port_state_change_event_bits { 2211 u8 reserved_at_0[0x40]; 2212 2213 u8 port_num[0x4]; 2214 u8 reserved_at_44[0x1c]; 2215 2216 u8 reserved_at_60[0x80]; 2217 }; 2218 2219 struct mlx5_ifc_dropped_packet_logged_bits { 2220 u8 reserved_at_0[0xe0]; 2221 }; 2222 2223 enum { 2224 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2225 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2226 }; 2227 2228 struct mlx5_ifc_cq_error_bits { 2229 u8 reserved_at_0[0x8]; 2230 u8 cqn[0x18]; 2231 2232 u8 reserved_at_20[0x20]; 2233 2234 u8 reserved_at_40[0x18]; 2235 u8 syndrome[0x8]; 2236 2237 u8 reserved_at_60[0x80]; 2238 }; 2239 2240 struct mlx5_ifc_rdma_page_fault_event_bits { 2241 u8 bytes_committed[0x20]; 2242 2243 u8 r_key[0x20]; 2244 2245 u8 reserved_at_40[0x10]; 2246 u8 packet_len[0x10]; 2247 2248 u8 rdma_op_len[0x20]; 2249 2250 u8 rdma_va[0x40]; 2251 2252 u8 reserved_at_c0[0x5]; 2253 u8 rdma[0x1]; 2254 u8 write[0x1]; 2255 u8 requestor[0x1]; 2256 u8 qp_number[0x18]; 2257 }; 2258 2259 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2260 u8 bytes_committed[0x20]; 2261 2262 u8 reserved_at_20[0x10]; 2263 u8 wqe_index[0x10]; 2264 2265 u8 reserved_at_40[0x10]; 2266 u8 len[0x10]; 2267 2268 u8 reserved_at_60[0x60]; 2269 2270 u8 reserved_at_c0[0x5]; 2271 u8 rdma[0x1]; 2272 u8 write_read[0x1]; 2273 u8 requestor[0x1]; 2274 u8 qpn[0x18]; 2275 }; 2276 2277 struct mlx5_ifc_qp_events_bits { 2278 u8 reserved_at_0[0xa0]; 2279 2280 u8 type[0x8]; 2281 u8 reserved_at_a8[0x18]; 2282 2283 u8 reserved_at_c0[0x8]; 2284 u8 qpn_rqn_sqn[0x18]; 2285 }; 2286 2287 struct mlx5_ifc_dct_events_bits { 2288 u8 reserved_at_0[0xc0]; 2289 2290 u8 reserved_at_c0[0x8]; 2291 u8 dct_number[0x18]; 2292 }; 2293 2294 struct mlx5_ifc_comp_event_bits { 2295 u8 reserved_at_0[0xc0]; 2296 2297 u8 reserved_at_c0[0x8]; 2298 u8 cq_number[0x18]; 2299 }; 2300 2301 enum { 2302 MLX5_QPC_STATE_RST = 0x0, 2303 MLX5_QPC_STATE_INIT = 0x1, 2304 MLX5_QPC_STATE_RTR = 0x2, 2305 MLX5_QPC_STATE_RTS = 0x3, 2306 MLX5_QPC_STATE_SQER = 0x4, 2307 MLX5_QPC_STATE_ERR = 0x6, 2308 MLX5_QPC_STATE_SQD = 0x7, 2309 MLX5_QPC_STATE_SUSPENDED = 0x9, 2310 }; 2311 2312 enum { 2313 MLX5_QPC_ST_RC = 0x0, 2314 MLX5_QPC_ST_UC = 0x1, 2315 MLX5_QPC_ST_UD = 0x2, 2316 MLX5_QPC_ST_XRC = 0x3, 2317 MLX5_QPC_ST_DCI = 0x5, 2318 MLX5_QPC_ST_QP0 = 0x7, 2319 MLX5_QPC_ST_QP1 = 0x8, 2320 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2321 MLX5_QPC_ST_REG_UMR = 0xc, 2322 }; 2323 2324 enum { 2325 MLX5_QPC_PM_STATE_ARMED = 0x0, 2326 MLX5_QPC_PM_STATE_REARM = 0x1, 2327 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2328 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2329 }; 2330 2331 enum { 2332 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2333 }; 2334 2335 enum { 2336 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2337 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2338 }; 2339 2340 enum { 2341 MLX5_QPC_MTU_256_BYTES = 0x1, 2342 MLX5_QPC_MTU_512_BYTES = 0x2, 2343 MLX5_QPC_MTU_1K_BYTES = 0x3, 2344 MLX5_QPC_MTU_2K_BYTES = 0x4, 2345 MLX5_QPC_MTU_4K_BYTES = 0x5, 2346 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2347 }; 2348 2349 enum { 2350 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2351 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2352 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2353 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2354 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2355 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2356 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2357 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2358 }; 2359 2360 enum { 2361 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2362 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2363 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2364 }; 2365 2366 enum { 2367 MLX5_QPC_CS_RES_DISABLE = 0x0, 2368 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2369 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2370 }; 2371 2372 struct mlx5_ifc_qpc_bits { 2373 u8 state[0x4]; 2374 u8 lag_tx_port_affinity[0x4]; 2375 u8 st[0x8]; 2376 u8 reserved_at_10[0x3]; 2377 u8 pm_state[0x2]; 2378 u8 reserved_at_15[0x1]; 2379 u8 req_e2e_credit_mode[0x2]; 2380 u8 offload_type[0x4]; 2381 u8 end_padding_mode[0x2]; 2382 u8 reserved_at_1e[0x2]; 2383 2384 u8 wq_signature[0x1]; 2385 u8 block_lb_mc[0x1]; 2386 u8 atomic_like_write_en[0x1]; 2387 u8 latency_sensitive[0x1]; 2388 u8 reserved_at_24[0x1]; 2389 u8 drain_sigerr[0x1]; 2390 u8 reserved_at_26[0x2]; 2391 u8 pd[0x18]; 2392 2393 u8 mtu[0x3]; 2394 u8 log_msg_max[0x5]; 2395 u8 reserved_at_48[0x1]; 2396 u8 log_rq_size[0x4]; 2397 u8 log_rq_stride[0x3]; 2398 u8 no_sq[0x1]; 2399 u8 log_sq_size[0x4]; 2400 u8 reserved_at_55[0x6]; 2401 u8 rlky[0x1]; 2402 u8 ulp_stateless_offload_mode[0x4]; 2403 2404 u8 counter_set_id[0x8]; 2405 u8 uar_page[0x18]; 2406 2407 u8 reserved_at_80[0x8]; 2408 u8 user_index[0x18]; 2409 2410 u8 reserved_at_a0[0x3]; 2411 u8 log_page_size[0x5]; 2412 u8 remote_qpn[0x18]; 2413 2414 struct mlx5_ifc_ads_bits primary_address_path; 2415 2416 struct mlx5_ifc_ads_bits secondary_address_path; 2417 2418 u8 log_ack_req_freq[0x4]; 2419 u8 reserved_at_384[0x4]; 2420 u8 log_sra_max[0x3]; 2421 u8 reserved_at_38b[0x2]; 2422 u8 retry_count[0x3]; 2423 u8 rnr_retry[0x3]; 2424 u8 reserved_at_393[0x1]; 2425 u8 fre[0x1]; 2426 u8 cur_rnr_retry[0x3]; 2427 u8 cur_retry_count[0x3]; 2428 u8 reserved_at_39b[0x5]; 2429 2430 u8 reserved_at_3a0[0x20]; 2431 2432 u8 reserved_at_3c0[0x8]; 2433 u8 next_send_psn[0x18]; 2434 2435 u8 reserved_at_3e0[0x8]; 2436 u8 cqn_snd[0x18]; 2437 2438 u8 reserved_at_400[0x8]; 2439 u8 deth_sqpn[0x18]; 2440 2441 u8 reserved_at_420[0x20]; 2442 2443 u8 reserved_at_440[0x8]; 2444 u8 last_acked_psn[0x18]; 2445 2446 u8 reserved_at_460[0x8]; 2447 u8 ssn[0x18]; 2448 2449 u8 reserved_at_480[0x8]; 2450 u8 log_rra_max[0x3]; 2451 u8 reserved_at_48b[0x1]; 2452 u8 atomic_mode[0x4]; 2453 u8 rre[0x1]; 2454 u8 rwe[0x1]; 2455 u8 rae[0x1]; 2456 u8 reserved_at_493[0x1]; 2457 u8 page_offset[0x6]; 2458 u8 reserved_at_49a[0x3]; 2459 u8 cd_slave_receive[0x1]; 2460 u8 cd_slave_send[0x1]; 2461 u8 cd_master[0x1]; 2462 2463 u8 reserved_at_4a0[0x3]; 2464 u8 min_rnr_nak[0x5]; 2465 u8 next_rcv_psn[0x18]; 2466 2467 u8 reserved_at_4c0[0x8]; 2468 u8 xrcd[0x18]; 2469 2470 u8 reserved_at_4e0[0x8]; 2471 u8 cqn_rcv[0x18]; 2472 2473 u8 dbr_addr[0x40]; 2474 2475 u8 q_key[0x20]; 2476 2477 u8 reserved_at_560[0x5]; 2478 u8 rq_type[0x3]; 2479 u8 srqn_rmpn_xrqn[0x18]; 2480 2481 u8 reserved_at_580[0x8]; 2482 u8 rmsn[0x18]; 2483 2484 u8 hw_sq_wqebb_counter[0x10]; 2485 u8 sw_sq_wqebb_counter[0x10]; 2486 2487 u8 hw_rq_counter[0x20]; 2488 2489 u8 sw_rq_counter[0x20]; 2490 2491 u8 reserved_at_600[0x20]; 2492 2493 u8 reserved_at_620[0xf]; 2494 u8 cgs[0x1]; 2495 u8 cs_req[0x8]; 2496 u8 cs_res[0x8]; 2497 2498 u8 dc_access_key[0x40]; 2499 2500 u8 reserved_at_680[0x3]; 2501 u8 dbr_umem_valid[0x1]; 2502 2503 u8 reserved_at_684[0xbc]; 2504 }; 2505 2506 struct mlx5_ifc_roce_addr_layout_bits { 2507 u8 source_l3_address[16][0x8]; 2508 2509 u8 reserved_at_80[0x3]; 2510 u8 vlan_valid[0x1]; 2511 u8 vlan_id[0xc]; 2512 u8 source_mac_47_32[0x10]; 2513 2514 u8 source_mac_31_0[0x20]; 2515 2516 u8 reserved_at_c0[0x14]; 2517 u8 roce_l3_type[0x4]; 2518 u8 roce_version[0x8]; 2519 2520 u8 reserved_at_e0[0x20]; 2521 }; 2522 2523 union mlx5_ifc_hca_cap_union_bits { 2524 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2525 struct mlx5_ifc_odp_cap_bits odp_cap; 2526 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2527 struct mlx5_ifc_roce_cap_bits roce_cap; 2528 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2529 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2530 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2531 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2532 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2533 struct mlx5_ifc_qos_cap_bits qos_cap; 2534 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2535 u8 reserved_at_0[0x8000]; 2536 }; 2537 2538 enum { 2539 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2540 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2541 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2542 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2543 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2544 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2545 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2546 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2547 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2548 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2549 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2550 }; 2551 2552 struct mlx5_ifc_vlan_bits { 2553 u8 ethtype[0x10]; 2554 u8 prio[0x3]; 2555 u8 cfi[0x1]; 2556 u8 vid[0xc]; 2557 }; 2558 2559 struct mlx5_ifc_flow_context_bits { 2560 struct mlx5_ifc_vlan_bits push_vlan; 2561 2562 u8 group_id[0x20]; 2563 2564 u8 reserved_at_40[0x8]; 2565 u8 flow_tag[0x18]; 2566 2567 u8 reserved_at_60[0x10]; 2568 u8 action[0x10]; 2569 2570 u8 extended_destination[0x1]; 2571 u8 reserved_at_80[0x7]; 2572 u8 destination_list_size[0x18]; 2573 2574 u8 reserved_at_a0[0x8]; 2575 u8 flow_counter_list_size[0x18]; 2576 2577 u8 packet_reformat_id[0x20]; 2578 2579 u8 modify_header_id[0x20]; 2580 2581 struct mlx5_ifc_vlan_bits push_vlan_2; 2582 2583 u8 reserved_at_120[0xe0]; 2584 2585 struct mlx5_ifc_fte_match_param_bits match_value; 2586 2587 u8 reserved_at_1200[0x600]; 2588 2589 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2590 }; 2591 2592 enum { 2593 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2594 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2595 }; 2596 2597 struct mlx5_ifc_xrc_srqc_bits { 2598 u8 state[0x4]; 2599 u8 log_xrc_srq_size[0x4]; 2600 u8 reserved_at_8[0x18]; 2601 2602 u8 wq_signature[0x1]; 2603 u8 cont_srq[0x1]; 2604 u8 reserved_at_22[0x1]; 2605 u8 rlky[0x1]; 2606 u8 basic_cyclic_rcv_wqe[0x1]; 2607 u8 log_rq_stride[0x3]; 2608 u8 xrcd[0x18]; 2609 2610 u8 page_offset[0x6]; 2611 u8 reserved_at_46[0x1]; 2612 u8 dbr_umem_valid[0x1]; 2613 u8 cqn[0x18]; 2614 2615 u8 reserved_at_60[0x20]; 2616 2617 u8 user_index_equal_xrc_srqn[0x1]; 2618 u8 reserved_at_81[0x1]; 2619 u8 log_page_size[0x6]; 2620 u8 user_index[0x18]; 2621 2622 u8 reserved_at_a0[0x20]; 2623 2624 u8 reserved_at_c0[0x8]; 2625 u8 pd[0x18]; 2626 2627 u8 lwm[0x10]; 2628 u8 wqe_cnt[0x10]; 2629 2630 u8 reserved_at_100[0x40]; 2631 2632 u8 db_record_addr_h[0x20]; 2633 2634 u8 db_record_addr_l[0x1e]; 2635 u8 reserved_at_17e[0x2]; 2636 2637 u8 reserved_at_180[0x80]; 2638 }; 2639 2640 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2641 u8 counter_error_queues[0x20]; 2642 2643 u8 total_error_queues[0x20]; 2644 2645 u8 send_queue_priority_update_flow[0x20]; 2646 2647 u8 reserved_at_60[0x20]; 2648 2649 u8 nic_receive_steering_discard[0x40]; 2650 2651 u8 receive_discard_vport_down[0x40]; 2652 2653 u8 transmit_discard_vport_down[0x40]; 2654 2655 u8 reserved_at_140[0xec0]; 2656 }; 2657 2658 struct mlx5_ifc_traffic_counter_bits { 2659 u8 packets[0x40]; 2660 2661 u8 octets[0x40]; 2662 }; 2663 2664 struct mlx5_ifc_tisc_bits { 2665 u8 strict_lag_tx_port_affinity[0x1]; 2666 u8 reserved_at_1[0x3]; 2667 u8 lag_tx_port_affinity[0x04]; 2668 2669 u8 reserved_at_8[0x4]; 2670 u8 prio[0x4]; 2671 u8 reserved_at_10[0x10]; 2672 2673 u8 reserved_at_20[0x100]; 2674 2675 u8 reserved_at_120[0x8]; 2676 u8 transport_domain[0x18]; 2677 2678 u8 reserved_at_140[0x8]; 2679 u8 underlay_qpn[0x18]; 2680 u8 reserved_at_160[0x3a0]; 2681 }; 2682 2683 enum { 2684 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2685 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2686 }; 2687 2688 enum { 2689 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2690 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2691 }; 2692 2693 enum { 2694 MLX5_RX_HASH_FN_NONE = 0x0, 2695 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2696 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2697 }; 2698 2699 enum { 2700 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2701 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2702 }; 2703 2704 struct mlx5_ifc_tirc_bits { 2705 u8 reserved_at_0[0x20]; 2706 2707 u8 disp_type[0x4]; 2708 u8 reserved_at_24[0x1c]; 2709 2710 u8 reserved_at_40[0x40]; 2711 2712 u8 reserved_at_80[0x4]; 2713 u8 lro_timeout_period_usecs[0x10]; 2714 u8 lro_enable_mask[0x4]; 2715 u8 lro_max_ip_payload_size[0x8]; 2716 2717 u8 reserved_at_a0[0x40]; 2718 2719 u8 reserved_at_e0[0x8]; 2720 u8 inline_rqn[0x18]; 2721 2722 u8 rx_hash_symmetric[0x1]; 2723 u8 reserved_at_101[0x1]; 2724 u8 tunneled_offload_en[0x1]; 2725 u8 reserved_at_103[0x5]; 2726 u8 indirect_table[0x18]; 2727 2728 u8 rx_hash_fn[0x4]; 2729 u8 reserved_at_124[0x2]; 2730 u8 self_lb_block[0x2]; 2731 u8 transport_domain[0x18]; 2732 2733 u8 rx_hash_toeplitz_key[10][0x20]; 2734 2735 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2736 2737 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2738 2739 u8 reserved_at_2c0[0x4c0]; 2740 }; 2741 2742 enum { 2743 MLX5_SRQC_STATE_GOOD = 0x0, 2744 MLX5_SRQC_STATE_ERROR = 0x1, 2745 }; 2746 2747 struct mlx5_ifc_srqc_bits { 2748 u8 state[0x4]; 2749 u8 log_srq_size[0x4]; 2750 u8 reserved_at_8[0x18]; 2751 2752 u8 wq_signature[0x1]; 2753 u8 cont_srq[0x1]; 2754 u8 reserved_at_22[0x1]; 2755 u8 rlky[0x1]; 2756 u8 reserved_at_24[0x1]; 2757 u8 log_rq_stride[0x3]; 2758 u8 xrcd[0x18]; 2759 2760 u8 page_offset[0x6]; 2761 u8 reserved_at_46[0x2]; 2762 u8 cqn[0x18]; 2763 2764 u8 reserved_at_60[0x20]; 2765 2766 u8 reserved_at_80[0x2]; 2767 u8 log_page_size[0x6]; 2768 u8 reserved_at_88[0x18]; 2769 2770 u8 reserved_at_a0[0x20]; 2771 2772 u8 reserved_at_c0[0x8]; 2773 u8 pd[0x18]; 2774 2775 u8 lwm[0x10]; 2776 u8 wqe_cnt[0x10]; 2777 2778 u8 reserved_at_100[0x40]; 2779 2780 u8 dbr_addr[0x40]; 2781 2782 u8 reserved_at_180[0x80]; 2783 }; 2784 2785 enum { 2786 MLX5_SQC_STATE_RST = 0x0, 2787 MLX5_SQC_STATE_RDY = 0x1, 2788 MLX5_SQC_STATE_ERR = 0x3, 2789 }; 2790 2791 struct mlx5_ifc_sqc_bits { 2792 u8 rlky[0x1]; 2793 u8 cd_master[0x1]; 2794 u8 fre[0x1]; 2795 u8 flush_in_error_en[0x1]; 2796 u8 allow_multi_pkt_send_wqe[0x1]; 2797 u8 min_wqe_inline_mode[0x3]; 2798 u8 state[0x4]; 2799 u8 reg_umr[0x1]; 2800 u8 allow_swp[0x1]; 2801 u8 hairpin[0x1]; 2802 u8 reserved_at_f[0x11]; 2803 2804 u8 reserved_at_20[0x8]; 2805 u8 user_index[0x18]; 2806 2807 u8 reserved_at_40[0x8]; 2808 u8 cqn[0x18]; 2809 2810 u8 reserved_at_60[0x8]; 2811 u8 hairpin_peer_rq[0x18]; 2812 2813 u8 reserved_at_80[0x10]; 2814 u8 hairpin_peer_vhca[0x10]; 2815 2816 u8 reserved_at_a0[0x50]; 2817 2818 u8 packet_pacing_rate_limit_index[0x10]; 2819 u8 tis_lst_sz[0x10]; 2820 u8 reserved_at_110[0x10]; 2821 2822 u8 reserved_at_120[0x40]; 2823 2824 u8 reserved_at_160[0x8]; 2825 u8 tis_num_0[0x18]; 2826 2827 struct mlx5_ifc_wq_bits wq; 2828 }; 2829 2830 enum { 2831 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2832 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2833 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2834 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2835 }; 2836 2837 struct mlx5_ifc_scheduling_context_bits { 2838 u8 element_type[0x8]; 2839 u8 reserved_at_8[0x18]; 2840 2841 u8 element_attributes[0x20]; 2842 2843 u8 parent_element_id[0x20]; 2844 2845 u8 reserved_at_60[0x40]; 2846 2847 u8 bw_share[0x20]; 2848 2849 u8 max_average_bw[0x20]; 2850 2851 u8 reserved_at_e0[0x120]; 2852 }; 2853 2854 struct mlx5_ifc_rqtc_bits { 2855 u8 reserved_at_0[0xa0]; 2856 2857 u8 reserved_at_a0[0x10]; 2858 u8 rqt_max_size[0x10]; 2859 2860 u8 reserved_at_c0[0x10]; 2861 u8 rqt_actual_size[0x10]; 2862 2863 u8 reserved_at_e0[0x6a0]; 2864 2865 struct mlx5_ifc_rq_num_bits rq_num[0]; 2866 }; 2867 2868 enum { 2869 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2870 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2871 }; 2872 2873 enum { 2874 MLX5_RQC_STATE_RST = 0x0, 2875 MLX5_RQC_STATE_RDY = 0x1, 2876 MLX5_RQC_STATE_ERR = 0x3, 2877 }; 2878 2879 struct mlx5_ifc_rqc_bits { 2880 u8 rlky[0x1]; 2881 u8 delay_drop_en[0x1]; 2882 u8 scatter_fcs[0x1]; 2883 u8 vsd[0x1]; 2884 u8 mem_rq_type[0x4]; 2885 u8 state[0x4]; 2886 u8 reserved_at_c[0x1]; 2887 u8 flush_in_error_en[0x1]; 2888 u8 hairpin[0x1]; 2889 u8 reserved_at_f[0x11]; 2890 2891 u8 reserved_at_20[0x8]; 2892 u8 user_index[0x18]; 2893 2894 u8 reserved_at_40[0x8]; 2895 u8 cqn[0x18]; 2896 2897 u8 counter_set_id[0x8]; 2898 u8 reserved_at_68[0x18]; 2899 2900 u8 reserved_at_80[0x8]; 2901 u8 rmpn[0x18]; 2902 2903 u8 reserved_at_a0[0x8]; 2904 u8 hairpin_peer_sq[0x18]; 2905 2906 u8 reserved_at_c0[0x10]; 2907 u8 hairpin_peer_vhca[0x10]; 2908 2909 u8 reserved_at_e0[0xa0]; 2910 2911 struct mlx5_ifc_wq_bits wq; 2912 }; 2913 2914 enum { 2915 MLX5_RMPC_STATE_RDY = 0x1, 2916 MLX5_RMPC_STATE_ERR = 0x3, 2917 }; 2918 2919 struct mlx5_ifc_rmpc_bits { 2920 u8 reserved_at_0[0x8]; 2921 u8 state[0x4]; 2922 u8 reserved_at_c[0x14]; 2923 2924 u8 basic_cyclic_rcv_wqe[0x1]; 2925 u8 reserved_at_21[0x1f]; 2926 2927 u8 reserved_at_40[0x140]; 2928 2929 struct mlx5_ifc_wq_bits wq; 2930 }; 2931 2932 struct mlx5_ifc_nic_vport_context_bits { 2933 u8 reserved_at_0[0x5]; 2934 u8 min_wqe_inline_mode[0x3]; 2935 u8 reserved_at_8[0x15]; 2936 u8 disable_mc_local_lb[0x1]; 2937 u8 disable_uc_local_lb[0x1]; 2938 u8 roce_en[0x1]; 2939 2940 u8 arm_change_event[0x1]; 2941 u8 reserved_at_21[0x1a]; 2942 u8 event_on_mtu[0x1]; 2943 u8 event_on_promisc_change[0x1]; 2944 u8 event_on_vlan_change[0x1]; 2945 u8 event_on_mc_address_change[0x1]; 2946 u8 event_on_uc_address_change[0x1]; 2947 2948 u8 reserved_at_40[0xc]; 2949 2950 u8 affiliation_criteria[0x4]; 2951 u8 affiliated_vhca_id[0x10]; 2952 2953 u8 reserved_at_60[0xd0]; 2954 2955 u8 mtu[0x10]; 2956 2957 u8 system_image_guid[0x40]; 2958 u8 port_guid[0x40]; 2959 u8 node_guid[0x40]; 2960 2961 u8 reserved_at_200[0x140]; 2962 u8 qkey_violation_counter[0x10]; 2963 u8 reserved_at_350[0x430]; 2964 2965 u8 promisc_uc[0x1]; 2966 u8 promisc_mc[0x1]; 2967 u8 promisc_all[0x1]; 2968 u8 reserved_at_783[0x2]; 2969 u8 allowed_list_type[0x3]; 2970 u8 reserved_at_788[0xc]; 2971 u8 allowed_list_size[0xc]; 2972 2973 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2974 2975 u8 reserved_at_7e0[0x20]; 2976 2977 u8 current_uc_mac_address[0][0x40]; 2978 }; 2979 2980 enum { 2981 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2982 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2983 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2984 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2985 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 2986 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2987 }; 2988 2989 struct mlx5_ifc_mkc_bits { 2990 u8 reserved_at_0[0x1]; 2991 u8 free[0x1]; 2992 u8 reserved_at_2[0x1]; 2993 u8 access_mode_4_2[0x3]; 2994 u8 reserved_at_6[0x7]; 2995 u8 relaxed_ordering_write[0x1]; 2996 u8 reserved_at_e[0x1]; 2997 u8 small_fence_on_rdma_read_response[0x1]; 2998 u8 umr_en[0x1]; 2999 u8 a[0x1]; 3000 u8 rw[0x1]; 3001 u8 rr[0x1]; 3002 u8 lw[0x1]; 3003 u8 lr[0x1]; 3004 u8 access_mode_1_0[0x2]; 3005 u8 reserved_at_18[0x8]; 3006 3007 u8 qpn[0x18]; 3008 u8 mkey_7_0[0x8]; 3009 3010 u8 reserved_at_40[0x20]; 3011 3012 u8 length64[0x1]; 3013 u8 bsf_en[0x1]; 3014 u8 sync_umr[0x1]; 3015 u8 reserved_at_63[0x2]; 3016 u8 expected_sigerr_count[0x1]; 3017 u8 reserved_at_66[0x1]; 3018 u8 en_rinval[0x1]; 3019 u8 pd[0x18]; 3020 3021 u8 start_addr[0x40]; 3022 3023 u8 len[0x40]; 3024 3025 u8 bsf_octword_size[0x20]; 3026 3027 u8 reserved_at_120[0x80]; 3028 3029 u8 translations_octword_size[0x20]; 3030 3031 u8 reserved_at_1c0[0x1b]; 3032 u8 log_page_size[0x5]; 3033 3034 u8 reserved_at_1e0[0x20]; 3035 }; 3036 3037 struct mlx5_ifc_pkey_bits { 3038 u8 reserved_at_0[0x10]; 3039 u8 pkey[0x10]; 3040 }; 3041 3042 struct mlx5_ifc_array128_auto_bits { 3043 u8 array128_auto[16][0x8]; 3044 }; 3045 3046 struct mlx5_ifc_hca_vport_context_bits { 3047 u8 field_select[0x20]; 3048 3049 u8 reserved_at_20[0xe0]; 3050 3051 u8 sm_virt_aware[0x1]; 3052 u8 has_smi[0x1]; 3053 u8 has_raw[0x1]; 3054 u8 grh_required[0x1]; 3055 u8 reserved_at_104[0xc]; 3056 u8 port_physical_state[0x4]; 3057 u8 vport_state_policy[0x4]; 3058 u8 port_state[0x4]; 3059 u8 vport_state[0x4]; 3060 3061 u8 reserved_at_120[0x20]; 3062 3063 u8 system_image_guid[0x40]; 3064 3065 u8 port_guid[0x40]; 3066 3067 u8 node_guid[0x40]; 3068 3069 u8 cap_mask1[0x20]; 3070 3071 u8 cap_mask1_field_select[0x20]; 3072 3073 u8 cap_mask2[0x20]; 3074 3075 u8 cap_mask2_field_select[0x20]; 3076 3077 u8 reserved_at_280[0x80]; 3078 3079 u8 lid[0x10]; 3080 u8 reserved_at_310[0x4]; 3081 u8 init_type_reply[0x4]; 3082 u8 lmc[0x3]; 3083 u8 subnet_timeout[0x5]; 3084 3085 u8 sm_lid[0x10]; 3086 u8 sm_sl[0x4]; 3087 u8 reserved_at_334[0xc]; 3088 3089 u8 qkey_violation_counter[0x10]; 3090 u8 pkey_violation_counter[0x10]; 3091 3092 u8 reserved_at_360[0xca0]; 3093 }; 3094 3095 struct mlx5_ifc_esw_vport_context_bits { 3096 u8 reserved_at_0[0x3]; 3097 u8 vport_svlan_strip[0x1]; 3098 u8 vport_cvlan_strip[0x1]; 3099 u8 vport_svlan_insert[0x1]; 3100 u8 vport_cvlan_insert[0x2]; 3101 u8 reserved_at_8[0x18]; 3102 3103 u8 reserved_at_20[0x20]; 3104 3105 u8 svlan_cfi[0x1]; 3106 u8 svlan_pcp[0x3]; 3107 u8 svlan_id[0xc]; 3108 u8 cvlan_cfi[0x1]; 3109 u8 cvlan_pcp[0x3]; 3110 u8 cvlan_id[0xc]; 3111 3112 u8 reserved_at_60[0x7a0]; 3113 }; 3114 3115 enum { 3116 MLX5_EQC_STATUS_OK = 0x0, 3117 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3118 }; 3119 3120 enum { 3121 MLX5_EQC_ST_ARMED = 0x9, 3122 MLX5_EQC_ST_FIRED = 0xa, 3123 }; 3124 3125 struct mlx5_ifc_eqc_bits { 3126 u8 status[0x4]; 3127 u8 reserved_at_4[0x9]; 3128 u8 ec[0x1]; 3129 u8 oi[0x1]; 3130 u8 reserved_at_f[0x5]; 3131 u8 st[0x4]; 3132 u8 reserved_at_18[0x8]; 3133 3134 u8 reserved_at_20[0x20]; 3135 3136 u8 reserved_at_40[0x14]; 3137 u8 page_offset[0x6]; 3138 u8 reserved_at_5a[0x6]; 3139 3140 u8 reserved_at_60[0x3]; 3141 u8 log_eq_size[0x5]; 3142 u8 uar_page[0x18]; 3143 3144 u8 reserved_at_80[0x20]; 3145 3146 u8 reserved_at_a0[0x18]; 3147 u8 intr[0x8]; 3148 3149 u8 reserved_at_c0[0x3]; 3150 u8 log_page_size[0x5]; 3151 u8 reserved_at_c8[0x18]; 3152 3153 u8 reserved_at_e0[0x60]; 3154 3155 u8 reserved_at_140[0x8]; 3156 u8 consumer_counter[0x18]; 3157 3158 u8 reserved_at_160[0x8]; 3159 u8 producer_counter[0x18]; 3160 3161 u8 reserved_at_180[0x80]; 3162 }; 3163 3164 enum { 3165 MLX5_DCTC_STATE_ACTIVE = 0x0, 3166 MLX5_DCTC_STATE_DRAINING = 0x1, 3167 MLX5_DCTC_STATE_DRAINED = 0x2, 3168 }; 3169 3170 enum { 3171 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3172 MLX5_DCTC_CS_RES_NA = 0x1, 3173 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3174 }; 3175 3176 enum { 3177 MLX5_DCTC_MTU_256_BYTES = 0x1, 3178 MLX5_DCTC_MTU_512_BYTES = 0x2, 3179 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3180 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3181 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3182 }; 3183 3184 struct mlx5_ifc_dctc_bits { 3185 u8 reserved_at_0[0x4]; 3186 u8 state[0x4]; 3187 u8 reserved_at_8[0x18]; 3188 3189 u8 reserved_at_20[0x8]; 3190 u8 user_index[0x18]; 3191 3192 u8 reserved_at_40[0x8]; 3193 u8 cqn[0x18]; 3194 3195 u8 counter_set_id[0x8]; 3196 u8 atomic_mode[0x4]; 3197 u8 rre[0x1]; 3198 u8 rwe[0x1]; 3199 u8 rae[0x1]; 3200 u8 atomic_like_write_en[0x1]; 3201 u8 latency_sensitive[0x1]; 3202 u8 rlky[0x1]; 3203 u8 free_ar[0x1]; 3204 u8 reserved_at_73[0xd]; 3205 3206 u8 reserved_at_80[0x8]; 3207 u8 cs_res[0x8]; 3208 u8 reserved_at_90[0x3]; 3209 u8 min_rnr_nak[0x5]; 3210 u8 reserved_at_98[0x8]; 3211 3212 u8 reserved_at_a0[0x8]; 3213 u8 srqn_xrqn[0x18]; 3214 3215 u8 reserved_at_c0[0x8]; 3216 u8 pd[0x18]; 3217 3218 u8 tclass[0x8]; 3219 u8 reserved_at_e8[0x4]; 3220 u8 flow_label[0x14]; 3221 3222 u8 dc_access_key[0x40]; 3223 3224 u8 reserved_at_140[0x5]; 3225 u8 mtu[0x3]; 3226 u8 port[0x8]; 3227 u8 pkey_index[0x10]; 3228 3229 u8 reserved_at_160[0x8]; 3230 u8 my_addr_index[0x8]; 3231 u8 reserved_at_170[0x8]; 3232 u8 hop_limit[0x8]; 3233 3234 u8 dc_access_key_violation_count[0x20]; 3235 3236 u8 reserved_at_1a0[0x14]; 3237 u8 dei_cfi[0x1]; 3238 u8 eth_prio[0x3]; 3239 u8 ecn[0x2]; 3240 u8 dscp[0x6]; 3241 3242 u8 reserved_at_1c0[0x40]; 3243 }; 3244 3245 enum { 3246 MLX5_CQC_STATUS_OK = 0x0, 3247 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3248 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3249 }; 3250 3251 enum { 3252 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3253 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3254 }; 3255 3256 enum { 3257 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3258 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3259 MLX5_CQC_ST_FIRED = 0xa, 3260 }; 3261 3262 enum { 3263 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3264 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3265 MLX5_CQ_PERIOD_NUM_MODES 3266 }; 3267 3268 struct mlx5_ifc_cqc_bits { 3269 u8 status[0x4]; 3270 u8 reserved_at_4[0x2]; 3271 u8 dbr_umem_valid[0x1]; 3272 u8 reserved_at_7[0x1]; 3273 u8 cqe_sz[0x3]; 3274 u8 cc[0x1]; 3275 u8 reserved_at_c[0x1]; 3276 u8 scqe_break_moderation_en[0x1]; 3277 u8 oi[0x1]; 3278 u8 cq_period_mode[0x2]; 3279 u8 cqe_comp_en[0x1]; 3280 u8 mini_cqe_res_format[0x2]; 3281 u8 st[0x4]; 3282 u8 reserved_at_18[0x8]; 3283 3284 u8 reserved_at_20[0x20]; 3285 3286 u8 reserved_at_40[0x14]; 3287 u8 page_offset[0x6]; 3288 u8 reserved_at_5a[0x6]; 3289 3290 u8 reserved_at_60[0x3]; 3291 u8 log_cq_size[0x5]; 3292 u8 uar_page[0x18]; 3293 3294 u8 reserved_at_80[0x4]; 3295 u8 cq_period[0xc]; 3296 u8 cq_max_count[0x10]; 3297 3298 u8 reserved_at_a0[0x18]; 3299 u8 c_eqn[0x8]; 3300 3301 u8 reserved_at_c0[0x3]; 3302 u8 log_page_size[0x5]; 3303 u8 reserved_at_c8[0x18]; 3304 3305 u8 reserved_at_e0[0x20]; 3306 3307 u8 reserved_at_100[0x8]; 3308 u8 last_notified_index[0x18]; 3309 3310 u8 reserved_at_120[0x8]; 3311 u8 last_solicit_index[0x18]; 3312 3313 u8 reserved_at_140[0x8]; 3314 u8 consumer_counter[0x18]; 3315 3316 u8 reserved_at_160[0x8]; 3317 u8 producer_counter[0x18]; 3318 3319 u8 reserved_at_180[0x40]; 3320 3321 u8 dbr_addr[0x40]; 3322 }; 3323 3324 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3325 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3326 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3327 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3328 u8 reserved_at_0[0x800]; 3329 }; 3330 3331 struct mlx5_ifc_query_adapter_param_block_bits { 3332 u8 reserved_at_0[0xc0]; 3333 3334 u8 reserved_at_c0[0x8]; 3335 u8 ieee_vendor_id[0x18]; 3336 3337 u8 reserved_at_e0[0x10]; 3338 u8 vsd_vendor_id[0x10]; 3339 3340 u8 vsd[208][0x8]; 3341 3342 u8 vsd_contd_psid[16][0x8]; 3343 }; 3344 3345 enum { 3346 MLX5_XRQC_STATE_GOOD = 0x0, 3347 MLX5_XRQC_STATE_ERROR = 0x1, 3348 }; 3349 3350 enum { 3351 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3352 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3353 }; 3354 3355 enum { 3356 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3357 }; 3358 3359 struct mlx5_ifc_tag_matching_topology_context_bits { 3360 u8 log_matching_list_sz[0x4]; 3361 u8 reserved_at_4[0xc]; 3362 u8 append_next_index[0x10]; 3363 3364 u8 sw_phase_cnt[0x10]; 3365 u8 hw_phase_cnt[0x10]; 3366 3367 u8 reserved_at_40[0x40]; 3368 }; 3369 3370 struct mlx5_ifc_xrqc_bits { 3371 u8 state[0x4]; 3372 u8 rlkey[0x1]; 3373 u8 reserved_at_5[0xf]; 3374 u8 topology[0x4]; 3375 u8 reserved_at_18[0x4]; 3376 u8 offload[0x4]; 3377 3378 u8 reserved_at_20[0x8]; 3379 u8 user_index[0x18]; 3380 3381 u8 reserved_at_40[0x8]; 3382 u8 cqn[0x18]; 3383 3384 u8 reserved_at_60[0xa0]; 3385 3386 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3387 3388 u8 reserved_at_180[0x280]; 3389 3390 struct mlx5_ifc_wq_bits wq; 3391 }; 3392 3393 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3394 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3395 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3396 u8 reserved_at_0[0x20]; 3397 }; 3398 3399 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3400 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3401 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3402 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3403 u8 reserved_at_0[0x20]; 3404 }; 3405 3406 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3407 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3408 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3409 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3410 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3411 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3412 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3413 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3414 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3415 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3416 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3417 u8 reserved_at_0[0x7c0]; 3418 }; 3419 3420 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3421 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3422 u8 reserved_at_0[0x7c0]; 3423 }; 3424 3425 union mlx5_ifc_event_auto_bits { 3426 struct mlx5_ifc_comp_event_bits comp_event; 3427 struct mlx5_ifc_dct_events_bits dct_events; 3428 struct mlx5_ifc_qp_events_bits qp_events; 3429 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3430 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3431 struct mlx5_ifc_cq_error_bits cq_error; 3432 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3433 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3434 struct mlx5_ifc_gpio_event_bits gpio_event; 3435 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3436 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3437 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3438 u8 reserved_at_0[0xe0]; 3439 }; 3440 3441 struct mlx5_ifc_health_buffer_bits { 3442 u8 reserved_at_0[0x100]; 3443 3444 u8 assert_existptr[0x20]; 3445 3446 u8 assert_callra[0x20]; 3447 3448 u8 reserved_at_140[0x40]; 3449 3450 u8 fw_version[0x20]; 3451 3452 u8 hw_id[0x20]; 3453 3454 u8 reserved_at_1c0[0x20]; 3455 3456 u8 irisc_index[0x8]; 3457 u8 synd[0x8]; 3458 u8 ext_synd[0x10]; 3459 }; 3460 3461 struct mlx5_ifc_register_loopback_control_bits { 3462 u8 no_lb[0x1]; 3463 u8 reserved_at_1[0x7]; 3464 u8 port[0x8]; 3465 u8 reserved_at_10[0x10]; 3466 3467 u8 reserved_at_20[0x60]; 3468 }; 3469 3470 struct mlx5_ifc_vport_tc_element_bits { 3471 u8 traffic_class[0x4]; 3472 u8 reserved_at_4[0xc]; 3473 u8 vport_number[0x10]; 3474 }; 3475 3476 struct mlx5_ifc_vport_element_bits { 3477 u8 reserved_at_0[0x10]; 3478 u8 vport_number[0x10]; 3479 }; 3480 3481 enum { 3482 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3483 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3484 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3485 }; 3486 3487 struct mlx5_ifc_tsar_element_bits { 3488 u8 reserved_at_0[0x8]; 3489 u8 tsar_type[0x8]; 3490 u8 reserved_at_10[0x10]; 3491 }; 3492 3493 enum { 3494 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3495 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3496 }; 3497 3498 struct mlx5_ifc_teardown_hca_out_bits { 3499 u8 status[0x8]; 3500 u8 reserved_at_8[0x18]; 3501 3502 u8 syndrome[0x20]; 3503 3504 u8 reserved_at_40[0x3f]; 3505 3506 u8 state[0x1]; 3507 }; 3508 3509 enum { 3510 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3511 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3512 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3513 }; 3514 3515 struct mlx5_ifc_teardown_hca_in_bits { 3516 u8 opcode[0x10]; 3517 u8 reserved_at_10[0x10]; 3518 3519 u8 reserved_at_20[0x10]; 3520 u8 op_mod[0x10]; 3521 3522 u8 reserved_at_40[0x10]; 3523 u8 profile[0x10]; 3524 3525 u8 reserved_at_60[0x20]; 3526 }; 3527 3528 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3529 u8 status[0x8]; 3530 u8 reserved_at_8[0x18]; 3531 3532 u8 syndrome[0x20]; 3533 3534 u8 reserved_at_40[0x40]; 3535 }; 3536 3537 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3538 u8 opcode[0x10]; 3539 u8 uid[0x10]; 3540 3541 u8 reserved_at_20[0x10]; 3542 u8 op_mod[0x10]; 3543 3544 u8 reserved_at_40[0x8]; 3545 u8 qpn[0x18]; 3546 3547 u8 reserved_at_60[0x20]; 3548 3549 u8 opt_param_mask[0x20]; 3550 3551 u8 reserved_at_a0[0x20]; 3552 3553 struct mlx5_ifc_qpc_bits qpc; 3554 3555 u8 reserved_at_800[0x80]; 3556 }; 3557 3558 struct mlx5_ifc_sqd2rts_qp_out_bits { 3559 u8 status[0x8]; 3560 u8 reserved_at_8[0x18]; 3561 3562 u8 syndrome[0x20]; 3563 3564 u8 reserved_at_40[0x40]; 3565 }; 3566 3567 struct mlx5_ifc_sqd2rts_qp_in_bits { 3568 u8 opcode[0x10]; 3569 u8 uid[0x10]; 3570 3571 u8 reserved_at_20[0x10]; 3572 u8 op_mod[0x10]; 3573 3574 u8 reserved_at_40[0x8]; 3575 u8 qpn[0x18]; 3576 3577 u8 reserved_at_60[0x20]; 3578 3579 u8 opt_param_mask[0x20]; 3580 3581 u8 reserved_at_a0[0x20]; 3582 3583 struct mlx5_ifc_qpc_bits qpc; 3584 3585 u8 reserved_at_800[0x80]; 3586 }; 3587 3588 struct mlx5_ifc_set_roce_address_out_bits { 3589 u8 status[0x8]; 3590 u8 reserved_at_8[0x18]; 3591 3592 u8 syndrome[0x20]; 3593 3594 u8 reserved_at_40[0x40]; 3595 }; 3596 3597 struct mlx5_ifc_set_roce_address_in_bits { 3598 u8 opcode[0x10]; 3599 u8 reserved_at_10[0x10]; 3600 3601 u8 reserved_at_20[0x10]; 3602 u8 op_mod[0x10]; 3603 3604 u8 roce_address_index[0x10]; 3605 u8 reserved_at_50[0xc]; 3606 u8 vhca_port_num[0x4]; 3607 3608 u8 reserved_at_60[0x20]; 3609 3610 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3611 }; 3612 3613 struct mlx5_ifc_set_mad_demux_out_bits { 3614 u8 status[0x8]; 3615 u8 reserved_at_8[0x18]; 3616 3617 u8 syndrome[0x20]; 3618 3619 u8 reserved_at_40[0x40]; 3620 }; 3621 3622 enum { 3623 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3624 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3625 }; 3626 3627 struct mlx5_ifc_set_mad_demux_in_bits { 3628 u8 opcode[0x10]; 3629 u8 reserved_at_10[0x10]; 3630 3631 u8 reserved_at_20[0x10]; 3632 u8 op_mod[0x10]; 3633 3634 u8 reserved_at_40[0x20]; 3635 3636 u8 reserved_at_60[0x6]; 3637 u8 demux_mode[0x2]; 3638 u8 reserved_at_68[0x18]; 3639 }; 3640 3641 struct mlx5_ifc_set_l2_table_entry_out_bits { 3642 u8 status[0x8]; 3643 u8 reserved_at_8[0x18]; 3644 3645 u8 syndrome[0x20]; 3646 3647 u8 reserved_at_40[0x40]; 3648 }; 3649 3650 struct mlx5_ifc_set_l2_table_entry_in_bits { 3651 u8 opcode[0x10]; 3652 u8 reserved_at_10[0x10]; 3653 3654 u8 reserved_at_20[0x10]; 3655 u8 op_mod[0x10]; 3656 3657 u8 reserved_at_40[0x60]; 3658 3659 u8 reserved_at_a0[0x8]; 3660 u8 table_index[0x18]; 3661 3662 u8 reserved_at_c0[0x20]; 3663 3664 u8 reserved_at_e0[0x13]; 3665 u8 vlan_valid[0x1]; 3666 u8 vlan[0xc]; 3667 3668 struct mlx5_ifc_mac_address_layout_bits mac_address; 3669 3670 u8 reserved_at_140[0xc0]; 3671 }; 3672 3673 struct mlx5_ifc_set_issi_out_bits { 3674 u8 status[0x8]; 3675 u8 reserved_at_8[0x18]; 3676 3677 u8 syndrome[0x20]; 3678 3679 u8 reserved_at_40[0x40]; 3680 }; 3681 3682 struct mlx5_ifc_set_issi_in_bits { 3683 u8 opcode[0x10]; 3684 u8 reserved_at_10[0x10]; 3685 3686 u8 reserved_at_20[0x10]; 3687 u8 op_mod[0x10]; 3688 3689 u8 reserved_at_40[0x10]; 3690 u8 current_issi[0x10]; 3691 3692 u8 reserved_at_60[0x20]; 3693 }; 3694 3695 struct mlx5_ifc_set_hca_cap_out_bits { 3696 u8 status[0x8]; 3697 u8 reserved_at_8[0x18]; 3698 3699 u8 syndrome[0x20]; 3700 3701 u8 reserved_at_40[0x40]; 3702 }; 3703 3704 struct mlx5_ifc_set_hca_cap_in_bits { 3705 u8 opcode[0x10]; 3706 u8 reserved_at_10[0x10]; 3707 3708 u8 reserved_at_20[0x10]; 3709 u8 op_mod[0x10]; 3710 3711 u8 reserved_at_40[0x40]; 3712 3713 union mlx5_ifc_hca_cap_union_bits capability; 3714 }; 3715 3716 enum { 3717 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3718 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3719 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3720 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3721 }; 3722 3723 struct mlx5_ifc_set_fte_out_bits { 3724 u8 status[0x8]; 3725 u8 reserved_at_8[0x18]; 3726 3727 u8 syndrome[0x20]; 3728 3729 u8 reserved_at_40[0x40]; 3730 }; 3731 3732 struct mlx5_ifc_set_fte_in_bits { 3733 u8 opcode[0x10]; 3734 u8 reserved_at_10[0x10]; 3735 3736 u8 reserved_at_20[0x10]; 3737 u8 op_mod[0x10]; 3738 3739 u8 other_vport[0x1]; 3740 u8 reserved_at_41[0xf]; 3741 u8 vport_number[0x10]; 3742 3743 u8 reserved_at_60[0x20]; 3744 3745 u8 table_type[0x8]; 3746 u8 reserved_at_88[0x18]; 3747 3748 u8 reserved_at_a0[0x8]; 3749 u8 table_id[0x18]; 3750 3751 u8 reserved_at_c0[0x18]; 3752 u8 modify_enable_mask[0x8]; 3753 3754 u8 reserved_at_e0[0x20]; 3755 3756 u8 flow_index[0x20]; 3757 3758 u8 reserved_at_120[0xe0]; 3759 3760 struct mlx5_ifc_flow_context_bits flow_context; 3761 }; 3762 3763 struct mlx5_ifc_rts2rts_qp_out_bits { 3764 u8 status[0x8]; 3765 u8 reserved_at_8[0x18]; 3766 3767 u8 syndrome[0x20]; 3768 3769 u8 reserved_at_40[0x40]; 3770 }; 3771 3772 struct mlx5_ifc_rts2rts_qp_in_bits { 3773 u8 opcode[0x10]; 3774 u8 uid[0x10]; 3775 3776 u8 reserved_at_20[0x10]; 3777 u8 op_mod[0x10]; 3778 3779 u8 reserved_at_40[0x8]; 3780 u8 qpn[0x18]; 3781 3782 u8 reserved_at_60[0x20]; 3783 3784 u8 opt_param_mask[0x20]; 3785 3786 u8 reserved_at_a0[0x20]; 3787 3788 struct mlx5_ifc_qpc_bits qpc; 3789 3790 u8 reserved_at_800[0x80]; 3791 }; 3792 3793 struct mlx5_ifc_rtr2rts_qp_out_bits { 3794 u8 status[0x8]; 3795 u8 reserved_at_8[0x18]; 3796 3797 u8 syndrome[0x20]; 3798 3799 u8 reserved_at_40[0x40]; 3800 }; 3801 3802 struct mlx5_ifc_rtr2rts_qp_in_bits { 3803 u8 opcode[0x10]; 3804 u8 uid[0x10]; 3805 3806 u8 reserved_at_20[0x10]; 3807 u8 op_mod[0x10]; 3808 3809 u8 reserved_at_40[0x8]; 3810 u8 qpn[0x18]; 3811 3812 u8 reserved_at_60[0x20]; 3813 3814 u8 opt_param_mask[0x20]; 3815 3816 u8 reserved_at_a0[0x20]; 3817 3818 struct mlx5_ifc_qpc_bits qpc; 3819 3820 u8 reserved_at_800[0x80]; 3821 }; 3822 3823 struct mlx5_ifc_rst2init_qp_out_bits { 3824 u8 status[0x8]; 3825 u8 reserved_at_8[0x18]; 3826 3827 u8 syndrome[0x20]; 3828 3829 u8 reserved_at_40[0x40]; 3830 }; 3831 3832 struct mlx5_ifc_rst2init_qp_in_bits { 3833 u8 opcode[0x10]; 3834 u8 uid[0x10]; 3835 3836 u8 reserved_at_20[0x10]; 3837 u8 op_mod[0x10]; 3838 3839 u8 reserved_at_40[0x8]; 3840 u8 qpn[0x18]; 3841 3842 u8 reserved_at_60[0x20]; 3843 3844 u8 opt_param_mask[0x20]; 3845 3846 u8 reserved_at_a0[0x20]; 3847 3848 struct mlx5_ifc_qpc_bits qpc; 3849 3850 u8 reserved_at_800[0x80]; 3851 }; 3852 3853 struct mlx5_ifc_query_xrq_out_bits { 3854 u8 status[0x8]; 3855 u8 reserved_at_8[0x18]; 3856 3857 u8 syndrome[0x20]; 3858 3859 u8 reserved_at_40[0x40]; 3860 3861 struct mlx5_ifc_xrqc_bits xrq_context; 3862 }; 3863 3864 struct mlx5_ifc_query_xrq_in_bits { 3865 u8 opcode[0x10]; 3866 u8 reserved_at_10[0x10]; 3867 3868 u8 reserved_at_20[0x10]; 3869 u8 op_mod[0x10]; 3870 3871 u8 reserved_at_40[0x8]; 3872 u8 xrqn[0x18]; 3873 3874 u8 reserved_at_60[0x20]; 3875 }; 3876 3877 struct mlx5_ifc_query_xrc_srq_out_bits { 3878 u8 status[0x8]; 3879 u8 reserved_at_8[0x18]; 3880 3881 u8 syndrome[0x20]; 3882 3883 u8 reserved_at_40[0x40]; 3884 3885 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3886 3887 u8 reserved_at_280[0x600]; 3888 3889 u8 pas[0][0x40]; 3890 }; 3891 3892 struct mlx5_ifc_query_xrc_srq_in_bits { 3893 u8 opcode[0x10]; 3894 u8 reserved_at_10[0x10]; 3895 3896 u8 reserved_at_20[0x10]; 3897 u8 op_mod[0x10]; 3898 3899 u8 reserved_at_40[0x8]; 3900 u8 xrc_srqn[0x18]; 3901 3902 u8 reserved_at_60[0x20]; 3903 }; 3904 3905 enum { 3906 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3907 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3908 }; 3909 3910 struct mlx5_ifc_query_vport_state_out_bits { 3911 u8 status[0x8]; 3912 u8 reserved_at_8[0x18]; 3913 3914 u8 syndrome[0x20]; 3915 3916 u8 reserved_at_40[0x20]; 3917 3918 u8 reserved_at_60[0x18]; 3919 u8 admin_state[0x4]; 3920 u8 state[0x4]; 3921 }; 3922 3923 enum { 3924 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3925 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3926 }; 3927 3928 struct mlx5_ifc_arm_monitor_counter_in_bits { 3929 u8 opcode[0x10]; 3930 u8 uid[0x10]; 3931 3932 u8 reserved_at_20[0x10]; 3933 u8 op_mod[0x10]; 3934 3935 u8 reserved_at_40[0x20]; 3936 3937 u8 reserved_at_60[0x20]; 3938 }; 3939 3940 struct mlx5_ifc_arm_monitor_counter_out_bits { 3941 u8 status[0x8]; 3942 u8 reserved_at_8[0x18]; 3943 3944 u8 syndrome[0x20]; 3945 3946 u8 reserved_at_40[0x40]; 3947 }; 3948 3949 enum { 3950 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3951 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3952 }; 3953 3954 enum mlx5_monitor_counter_ppcnt { 3955 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 3956 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 3957 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 3958 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 3959 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 3960 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 3961 }; 3962 3963 enum { 3964 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 3965 }; 3966 3967 struct mlx5_ifc_monitor_counter_output_bits { 3968 u8 reserved_at_0[0x4]; 3969 u8 type[0x4]; 3970 u8 reserved_at_8[0x8]; 3971 u8 counter[0x10]; 3972 3973 u8 counter_group_id[0x20]; 3974 }; 3975 3976 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 3977 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 3978 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 3979 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 3980 3981 struct mlx5_ifc_set_monitor_counter_in_bits { 3982 u8 opcode[0x10]; 3983 u8 uid[0x10]; 3984 3985 u8 reserved_at_20[0x10]; 3986 u8 op_mod[0x10]; 3987 3988 u8 reserved_at_40[0x10]; 3989 u8 num_of_counters[0x10]; 3990 3991 u8 reserved_at_60[0x20]; 3992 3993 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 3994 }; 3995 3996 struct mlx5_ifc_set_monitor_counter_out_bits { 3997 u8 status[0x8]; 3998 u8 reserved_at_8[0x18]; 3999 4000 u8 syndrome[0x20]; 4001 4002 u8 reserved_at_40[0x40]; 4003 }; 4004 4005 struct mlx5_ifc_query_vport_state_in_bits { 4006 u8 opcode[0x10]; 4007 u8 reserved_at_10[0x10]; 4008 4009 u8 reserved_at_20[0x10]; 4010 u8 op_mod[0x10]; 4011 4012 u8 other_vport[0x1]; 4013 u8 reserved_at_41[0xf]; 4014 u8 vport_number[0x10]; 4015 4016 u8 reserved_at_60[0x20]; 4017 }; 4018 4019 struct mlx5_ifc_query_vnic_env_out_bits { 4020 u8 status[0x8]; 4021 u8 reserved_at_8[0x18]; 4022 4023 u8 syndrome[0x20]; 4024 4025 u8 reserved_at_40[0x40]; 4026 4027 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4028 }; 4029 4030 enum { 4031 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4032 }; 4033 4034 struct mlx5_ifc_query_vnic_env_in_bits { 4035 u8 opcode[0x10]; 4036 u8 reserved_at_10[0x10]; 4037 4038 u8 reserved_at_20[0x10]; 4039 u8 op_mod[0x10]; 4040 4041 u8 other_vport[0x1]; 4042 u8 reserved_at_41[0xf]; 4043 u8 vport_number[0x10]; 4044 4045 u8 reserved_at_60[0x20]; 4046 }; 4047 4048 struct mlx5_ifc_query_vport_counter_out_bits { 4049 u8 status[0x8]; 4050 u8 reserved_at_8[0x18]; 4051 4052 u8 syndrome[0x20]; 4053 4054 u8 reserved_at_40[0x40]; 4055 4056 struct mlx5_ifc_traffic_counter_bits received_errors; 4057 4058 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4059 4060 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4061 4062 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4063 4064 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4065 4066 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4067 4068 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4069 4070 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4071 4072 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4073 4074 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4075 4076 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4077 4078 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4079 4080 u8 reserved_at_680[0xa00]; 4081 }; 4082 4083 enum { 4084 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4085 }; 4086 4087 struct mlx5_ifc_query_vport_counter_in_bits { 4088 u8 opcode[0x10]; 4089 u8 reserved_at_10[0x10]; 4090 4091 u8 reserved_at_20[0x10]; 4092 u8 op_mod[0x10]; 4093 4094 u8 other_vport[0x1]; 4095 u8 reserved_at_41[0xb]; 4096 u8 port_num[0x4]; 4097 u8 vport_number[0x10]; 4098 4099 u8 reserved_at_60[0x60]; 4100 4101 u8 clear[0x1]; 4102 u8 reserved_at_c1[0x1f]; 4103 4104 u8 reserved_at_e0[0x20]; 4105 }; 4106 4107 struct mlx5_ifc_query_tis_out_bits { 4108 u8 status[0x8]; 4109 u8 reserved_at_8[0x18]; 4110 4111 u8 syndrome[0x20]; 4112 4113 u8 reserved_at_40[0x40]; 4114 4115 struct mlx5_ifc_tisc_bits tis_context; 4116 }; 4117 4118 struct mlx5_ifc_query_tis_in_bits { 4119 u8 opcode[0x10]; 4120 u8 reserved_at_10[0x10]; 4121 4122 u8 reserved_at_20[0x10]; 4123 u8 op_mod[0x10]; 4124 4125 u8 reserved_at_40[0x8]; 4126 u8 tisn[0x18]; 4127 4128 u8 reserved_at_60[0x20]; 4129 }; 4130 4131 struct mlx5_ifc_query_tir_out_bits { 4132 u8 status[0x8]; 4133 u8 reserved_at_8[0x18]; 4134 4135 u8 syndrome[0x20]; 4136 4137 u8 reserved_at_40[0xc0]; 4138 4139 struct mlx5_ifc_tirc_bits tir_context; 4140 }; 4141 4142 struct mlx5_ifc_query_tir_in_bits { 4143 u8 opcode[0x10]; 4144 u8 reserved_at_10[0x10]; 4145 4146 u8 reserved_at_20[0x10]; 4147 u8 op_mod[0x10]; 4148 4149 u8 reserved_at_40[0x8]; 4150 u8 tirn[0x18]; 4151 4152 u8 reserved_at_60[0x20]; 4153 }; 4154 4155 struct mlx5_ifc_query_srq_out_bits { 4156 u8 status[0x8]; 4157 u8 reserved_at_8[0x18]; 4158 4159 u8 syndrome[0x20]; 4160 4161 u8 reserved_at_40[0x40]; 4162 4163 struct mlx5_ifc_srqc_bits srq_context_entry; 4164 4165 u8 reserved_at_280[0x600]; 4166 4167 u8 pas[0][0x40]; 4168 }; 4169 4170 struct mlx5_ifc_query_srq_in_bits { 4171 u8 opcode[0x10]; 4172 u8 reserved_at_10[0x10]; 4173 4174 u8 reserved_at_20[0x10]; 4175 u8 op_mod[0x10]; 4176 4177 u8 reserved_at_40[0x8]; 4178 u8 srqn[0x18]; 4179 4180 u8 reserved_at_60[0x20]; 4181 }; 4182 4183 struct mlx5_ifc_query_sq_out_bits { 4184 u8 status[0x8]; 4185 u8 reserved_at_8[0x18]; 4186 4187 u8 syndrome[0x20]; 4188 4189 u8 reserved_at_40[0xc0]; 4190 4191 struct mlx5_ifc_sqc_bits sq_context; 4192 }; 4193 4194 struct mlx5_ifc_query_sq_in_bits { 4195 u8 opcode[0x10]; 4196 u8 reserved_at_10[0x10]; 4197 4198 u8 reserved_at_20[0x10]; 4199 u8 op_mod[0x10]; 4200 4201 u8 reserved_at_40[0x8]; 4202 u8 sqn[0x18]; 4203 4204 u8 reserved_at_60[0x20]; 4205 }; 4206 4207 struct mlx5_ifc_query_special_contexts_out_bits { 4208 u8 status[0x8]; 4209 u8 reserved_at_8[0x18]; 4210 4211 u8 syndrome[0x20]; 4212 4213 u8 dump_fill_mkey[0x20]; 4214 4215 u8 resd_lkey[0x20]; 4216 4217 u8 null_mkey[0x20]; 4218 4219 u8 reserved_at_a0[0x60]; 4220 }; 4221 4222 struct mlx5_ifc_query_special_contexts_in_bits { 4223 u8 opcode[0x10]; 4224 u8 reserved_at_10[0x10]; 4225 4226 u8 reserved_at_20[0x10]; 4227 u8 op_mod[0x10]; 4228 4229 u8 reserved_at_40[0x40]; 4230 }; 4231 4232 struct mlx5_ifc_query_scheduling_element_out_bits { 4233 u8 opcode[0x10]; 4234 u8 reserved_at_10[0x10]; 4235 4236 u8 reserved_at_20[0x10]; 4237 u8 op_mod[0x10]; 4238 4239 u8 reserved_at_40[0xc0]; 4240 4241 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4242 4243 u8 reserved_at_300[0x100]; 4244 }; 4245 4246 enum { 4247 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4248 }; 4249 4250 struct mlx5_ifc_query_scheduling_element_in_bits { 4251 u8 opcode[0x10]; 4252 u8 reserved_at_10[0x10]; 4253 4254 u8 reserved_at_20[0x10]; 4255 u8 op_mod[0x10]; 4256 4257 u8 scheduling_hierarchy[0x8]; 4258 u8 reserved_at_48[0x18]; 4259 4260 u8 scheduling_element_id[0x20]; 4261 4262 u8 reserved_at_80[0x180]; 4263 }; 4264 4265 struct mlx5_ifc_query_rqt_out_bits { 4266 u8 status[0x8]; 4267 u8 reserved_at_8[0x18]; 4268 4269 u8 syndrome[0x20]; 4270 4271 u8 reserved_at_40[0xc0]; 4272 4273 struct mlx5_ifc_rqtc_bits rqt_context; 4274 }; 4275 4276 struct mlx5_ifc_query_rqt_in_bits { 4277 u8 opcode[0x10]; 4278 u8 reserved_at_10[0x10]; 4279 4280 u8 reserved_at_20[0x10]; 4281 u8 op_mod[0x10]; 4282 4283 u8 reserved_at_40[0x8]; 4284 u8 rqtn[0x18]; 4285 4286 u8 reserved_at_60[0x20]; 4287 }; 4288 4289 struct mlx5_ifc_query_rq_out_bits { 4290 u8 status[0x8]; 4291 u8 reserved_at_8[0x18]; 4292 4293 u8 syndrome[0x20]; 4294 4295 u8 reserved_at_40[0xc0]; 4296 4297 struct mlx5_ifc_rqc_bits rq_context; 4298 }; 4299 4300 struct mlx5_ifc_query_rq_in_bits { 4301 u8 opcode[0x10]; 4302 u8 reserved_at_10[0x10]; 4303 4304 u8 reserved_at_20[0x10]; 4305 u8 op_mod[0x10]; 4306 4307 u8 reserved_at_40[0x8]; 4308 u8 rqn[0x18]; 4309 4310 u8 reserved_at_60[0x20]; 4311 }; 4312 4313 struct mlx5_ifc_query_roce_address_out_bits { 4314 u8 status[0x8]; 4315 u8 reserved_at_8[0x18]; 4316 4317 u8 syndrome[0x20]; 4318 4319 u8 reserved_at_40[0x40]; 4320 4321 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4322 }; 4323 4324 struct mlx5_ifc_query_roce_address_in_bits { 4325 u8 opcode[0x10]; 4326 u8 reserved_at_10[0x10]; 4327 4328 u8 reserved_at_20[0x10]; 4329 u8 op_mod[0x10]; 4330 4331 u8 roce_address_index[0x10]; 4332 u8 reserved_at_50[0xc]; 4333 u8 vhca_port_num[0x4]; 4334 4335 u8 reserved_at_60[0x20]; 4336 }; 4337 4338 struct mlx5_ifc_query_rmp_out_bits { 4339 u8 status[0x8]; 4340 u8 reserved_at_8[0x18]; 4341 4342 u8 syndrome[0x20]; 4343 4344 u8 reserved_at_40[0xc0]; 4345 4346 struct mlx5_ifc_rmpc_bits rmp_context; 4347 }; 4348 4349 struct mlx5_ifc_query_rmp_in_bits { 4350 u8 opcode[0x10]; 4351 u8 reserved_at_10[0x10]; 4352 4353 u8 reserved_at_20[0x10]; 4354 u8 op_mod[0x10]; 4355 4356 u8 reserved_at_40[0x8]; 4357 u8 rmpn[0x18]; 4358 4359 u8 reserved_at_60[0x20]; 4360 }; 4361 4362 struct mlx5_ifc_query_qp_out_bits { 4363 u8 status[0x8]; 4364 u8 reserved_at_8[0x18]; 4365 4366 u8 syndrome[0x20]; 4367 4368 u8 reserved_at_40[0x40]; 4369 4370 u8 opt_param_mask[0x20]; 4371 4372 u8 reserved_at_a0[0x20]; 4373 4374 struct mlx5_ifc_qpc_bits qpc; 4375 4376 u8 reserved_at_800[0x80]; 4377 4378 u8 pas[0][0x40]; 4379 }; 4380 4381 struct mlx5_ifc_query_qp_in_bits { 4382 u8 opcode[0x10]; 4383 u8 reserved_at_10[0x10]; 4384 4385 u8 reserved_at_20[0x10]; 4386 u8 op_mod[0x10]; 4387 4388 u8 reserved_at_40[0x8]; 4389 u8 qpn[0x18]; 4390 4391 u8 reserved_at_60[0x20]; 4392 }; 4393 4394 struct mlx5_ifc_query_q_counter_out_bits { 4395 u8 status[0x8]; 4396 u8 reserved_at_8[0x18]; 4397 4398 u8 syndrome[0x20]; 4399 4400 u8 reserved_at_40[0x40]; 4401 4402 u8 rx_write_requests[0x20]; 4403 4404 u8 reserved_at_a0[0x20]; 4405 4406 u8 rx_read_requests[0x20]; 4407 4408 u8 reserved_at_e0[0x20]; 4409 4410 u8 rx_atomic_requests[0x20]; 4411 4412 u8 reserved_at_120[0x20]; 4413 4414 u8 rx_dct_connect[0x20]; 4415 4416 u8 reserved_at_160[0x20]; 4417 4418 u8 out_of_buffer[0x20]; 4419 4420 u8 reserved_at_1a0[0x20]; 4421 4422 u8 out_of_sequence[0x20]; 4423 4424 u8 reserved_at_1e0[0x20]; 4425 4426 u8 duplicate_request[0x20]; 4427 4428 u8 reserved_at_220[0x20]; 4429 4430 u8 rnr_nak_retry_err[0x20]; 4431 4432 u8 reserved_at_260[0x20]; 4433 4434 u8 packet_seq_err[0x20]; 4435 4436 u8 reserved_at_2a0[0x20]; 4437 4438 u8 implied_nak_seq_err[0x20]; 4439 4440 u8 reserved_at_2e0[0x20]; 4441 4442 u8 local_ack_timeout_err[0x20]; 4443 4444 u8 reserved_at_320[0xa0]; 4445 4446 u8 resp_local_length_error[0x20]; 4447 4448 u8 req_local_length_error[0x20]; 4449 4450 u8 resp_local_qp_error[0x20]; 4451 4452 u8 local_operation_error[0x20]; 4453 4454 u8 resp_local_protection[0x20]; 4455 4456 u8 req_local_protection[0x20]; 4457 4458 u8 resp_cqe_error[0x20]; 4459 4460 u8 req_cqe_error[0x20]; 4461 4462 u8 req_mw_binding[0x20]; 4463 4464 u8 req_bad_response[0x20]; 4465 4466 u8 req_remote_invalid_request[0x20]; 4467 4468 u8 resp_remote_invalid_request[0x20]; 4469 4470 u8 req_remote_access_errors[0x20]; 4471 4472 u8 resp_remote_access_errors[0x20]; 4473 4474 u8 req_remote_operation_errors[0x20]; 4475 4476 u8 req_transport_retries_exceeded[0x20]; 4477 4478 u8 cq_overflow[0x20]; 4479 4480 u8 resp_cqe_flush_error[0x20]; 4481 4482 u8 req_cqe_flush_error[0x20]; 4483 4484 u8 reserved_at_620[0x1e0]; 4485 }; 4486 4487 struct mlx5_ifc_query_q_counter_in_bits { 4488 u8 opcode[0x10]; 4489 u8 reserved_at_10[0x10]; 4490 4491 u8 reserved_at_20[0x10]; 4492 u8 op_mod[0x10]; 4493 4494 u8 reserved_at_40[0x80]; 4495 4496 u8 clear[0x1]; 4497 u8 reserved_at_c1[0x1f]; 4498 4499 u8 reserved_at_e0[0x18]; 4500 u8 counter_set_id[0x8]; 4501 }; 4502 4503 struct mlx5_ifc_query_pages_out_bits { 4504 u8 status[0x8]; 4505 u8 reserved_at_8[0x18]; 4506 4507 u8 syndrome[0x20]; 4508 4509 u8 embedded_cpu_function[0x1]; 4510 u8 reserved_at_41[0xf]; 4511 u8 function_id[0x10]; 4512 4513 u8 num_pages[0x20]; 4514 }; 4515 4516 enum { 4517 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4518 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4519 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4520 }; 4521 4522 struct mlx5_ifc_query_pages_in_bits { 4523 u8 opcode[0x10]; 4524 u8 reserved_at_10[0x10]; 4525 4526 u8 reserved_at_20[0x10]; 4527 u8 op_mod[0x10]; 4528 4529 u8 embedded_cpu_function[0x1]; 4530 u8 reserved_at_41[0xf]; 4531 u8 function_id[0x10]; 4532 4533 u8 reserved_at_60[0x20]; 4534 }; 4535 4536 struct mlx5_ifc_query_nic_vport_context_out_bits { 4537 u8 status[0x8]; 4538 u8 reserved_at_8[0x18]; 4539 4540 u8 syndrome[0x20]; 4541 4542 u8 reserved_at_40[0x40]; 4543 4544 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4545 }; 4546 4547 struct mlx5_ifc_query_nic_vport_context_in_bits { 4548 u8 opcode[0x10]; 4549 u8 reserved_at_10[0x10]; 4550 4551 u8 reserved_at_20[0x10]; 4552 u8 op_mod[0x10]; 4553 4554 u8 other_vport[0x1]; 4555 u8 reserved_at_41[0xf]; 4556 u8 vport_number[0x10]; 4557 4558 u8 reserved_at_60[0x5]; 4559 u8 allowed_list_type[0x3]; 4560 u8 reserved_at_68[0x18]; 4561 }; 4562 4563 struct mlx5_ifc_query_mkey_out_bits { 4564 u8 status[0x8]; 4565 u8 reserved_at_8[0x18]; 4566 4567 u8 syndrome[0x20]; 4568 4569 u8 reserved_at_40[0x40]; 4570 4571 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4572 4573 u8 reserved_at_280[0x600]; 4574 4575 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4576 4577 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4578 }; 4579 4580 struct mlx5_ifc_query_mkey_in_bits { 4581 u8 opcode[0x10]; 4582 u8 reserved_at_10[0x10]; 4583 4584 u8 reserved_at_20[0x10]; 4585 u8 op_mod[0x10]; 4586 4587 u8 reserved_at_40[0x8]; 4588 u8 mkey_index[0x18]; 4589 4590 u8 pg_access[0x1]; 4591 u8 reserved_at_61[0x1f]; 4592 }; 4593 4594 struct mlx5_ifc_query_mad_demux_out_bits { 4595 u8 status[0x8]; 4596 u8 reserved_at_8[0x18]; 4597 4598 u8 syndrome[0x20]; 4599 4600 u8 reserved_at_40[0x40]; 4601 4602 u8 mad_dumux_parameters_block[0x20]; 4603 }; 4604 4605 struct mlx5_ifc_query_mad_demux_in_bits { 4606 u8 opcode[0x10]; 4607 u8 reserved_at_10[0x10]; 4608 4609 u8 reserved_at_20[0x10]; 4610 u8 op_mod[0x10]; 4611 4612 u8 reserved_at_40[0x40]; 4613 }; 4614 4615 struct mlx5_ifc_query_l2_table_entry_out_bits { 4616 u8 status[0x8]; 4617 u8 reserved_at_8[0x18]; 4618 4619 u8 syndrome[0x20]; 4620 4621 u8 reserved_at_40[0xa0]; 4622 4623 u8 reserved_at_e0[0x13]; 4624 u8 vlan_valid[0x1]; 4625 u8 vlan[0xc]; 4626 4627 struct mlx5_ifc_mac_address_layout_bits mac_address; 4628 4629 u8 reserved_at_140[0xc0]; 4630 }; 4631 4632 struct mlx5_ifc_query_l2_table_entry_in_bits { 4633 u8 opcode[0x10]; 4634 u8 reserved_at_10[0x10]; 4635 4636 u8 reserved_at_20[0x10]; 4637 u8 op_mod[0x10]; 4638 4639 u8 reserved_at_40[0x60]; 4640 4641 u8 reserved_at_a0[0x8]; 4642 u8 table_index[0x18]; 4643 4644 u8 reserved_at_c0[0x140]; 4645 }; 4646 4647 struct mlx5_ifc_query_issi_out_bits { 4648 u8 status[0x8]; 4649 u8 reserved_at_8[0x18]; 4650 4651 u8 syndrome[0x20]; 4652 4653 u8 reserved_at_40[0x10]; 4654 u8 current_issi[0x10]; 4655 4656 u8 reserved_at_60[0xa0]; 4657 4658 u8 reserved_at_100[76][0x8]; 4659 u8 supported_issi_dw0[0x20]; 4660 }; 4661 4662 struct mlx5_ifc_query_issi_in_bits { 4663 u8 opcode[0x10]; 4664 u8 reserved_at_10[0x10]; 4665 4666 u8 reserved_at_20[0x10]; 4667 u8 op_mod[0x10]; 4668 4669 u8 reserved_at_40[0x40]; 4670 }; 4671 4672 struct mlx5_ifc_set_driver_version_out_bits { 4673 u8 status[0x8]; 4674 u8 reserved_0[0x18]; 4675 4676 u8 syndrome[0x20]; 4677 u8 reserved_1[0x40]; 4678 }; 4679 4680 struct mlx5_ifc_set_driver_version_in_bits { 4681 u8 opcode[0x10]; 4682 u8 reserved_0[0x10]; 4683 4684 u8 reserved_1[0x10]; 4685 u8 op_mod[0x10]; 4686 4687 u8 reserved_2[0x40]; 4688 u8 driver_version[64][0x8]; 4689 }; 4690 4691 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4692 u8 status[0x8]; 4693 u8 reserved_at_8[0x18]; 4694 4695 u8 syndrome[0x20]; 4696 4697 u8 reserved_at_40[0x40]; 4698 4699 struct mlx5_ifc_pkey_bits pkey[0]; 4700 }; 4701 4702 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4703 u8 opcode[0x10]; 4704 u8 reserved_at_10[0x10]; 4705 4706 u8 reserved_at_20[0x10]; 4707 u8 op_mod[0x10]; 4708 4709 u8 other_vport[0x1]; 4710 u8 reserved_at_41[0xb]; 4711 u8 port_num[0x4]; 4712 u8 vport_number[0x10]; 4713 4714 u8 reserved_at_60[0x10]; 4715 u8 pkey_index[0x10]; 4716 }; 4717 4718 enum { 4719 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4720 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4721 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4722 }; 4723 4724 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4725 u8 status[0x8]; 4726 u8 reserved_at_8[0x18]; 4727 4728 u8 syndrome[0x20]; 4729 4730 u8 reserved_at_40[0x20]; 4731 4732 u8 gids_num[0x10]; 4733 u8 reserved_at_70[0x10]; 4734 4735 struct mlx5_ifc_array128_auto_bits gid[0]; 4736 }; 4737 4738 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4739 u8 opcode[0x10]; 4740 u8 reserved_at_10[0x10]; 4741 4742 u8 reserved_at_20[0x10]; 4743 u8 op_mod[0x10]; 4744 4745 u8 other_vport[0x1]; 4746 u8 reserved_at_41[0xb]; 4747 u8 port_num[0x4]; 4748 u8 vport_number[0x10]; 4749 4750 u8 reserved_at_60[0x10]; 4751 u8 gid_index[0x10]; 4752 }; 4753 4754 struct mlx5_ifc_query_hca_vport_context_out_bits { 4755 u8 status[0x8]; 4756 u8 reserved_at_8[0x18]; 4757 4758 u8 syndrome[0x20]; 4759 4760 u8 reserved_at_40[0x40]; 4761 4762 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4763 }; 4764 4765 struct mlx5_ifc_query_hca_vport_context_in_bits { 4766 u8 opcode[0x10]; 4767 u8 reserved_at_10[0x10]; 4768 4769 u8 reserved_at_20[0x10]; 4770 u8 op_mod[0x10]; 4771 4772 u8 other_vport[0x1]; 4773 u8 reserved_at_41[0xb]; 4774 u8 port_num[0x4]; 4775 u8 vport_number[0x10]; 4776 4777 u8 reserved_at_60[0x20]; 4778 }; 4779 4780 struct mlx5_ifc_query_hca_cap_out_bits { 4781 u8 status[0x8]; 4782 u8 reserved_at_8[0x18]; 4783 4784 u8 syndrome[0x20]; 4785 4786 u8 reserved_at_40[0x40]; 4787 4788 union mlx5_ifc_hca_cap_union_bits capability; 4789 }; 4790 4791 struct mlx5_ifc_query_hca_cap_in_bits { 4792 u8 opcode[0x10]; 4793 u8 reserved_at_10[0x10]; 4794 4795 u8 reserved_at_20[0x10]; 4796 u8 op_mod[0x10]; 4797 4798 u8 reserved_at_40[0x40]; 4799 }; 4800 4801 struct mlx5_ifc_query_flow_table_out_bits { 4802 u8 status[0x8]; 4803 u8 reserved_at_8[0x18]; 4804 4805 u8 syndrome[0x20]; 4806 4807 u8 reserved_at_40[0x80]; 4808 4809 u8 reserved_at_c0[0x8]; 4810 u8 level[0x8]; 4811 u8 reserved_at_d0[0x8]; 4812 u8 log_size[0x8]; 4813 4814 u8 reserved_at_e0[0x120]; 4815 }; 4816 4817 struct mlx5_ifc_query_flow_table_in_bits { 4818 u8 opcode[0x10]; 4819 u8 reserved_at_10[0x10]; 4820 4821 u8 reserved_at_20[0x10]; 4822 u8 op_mod[0x10]; 4823 4824 u8 reserved_at_40[0x40]; 4825 4826 u8 table_type[0x8]; 4827 u8 reserved_at_88[0x18]; 4828 4829 u8 reserved_at_a0[0x8]; 4830 u8 table_id[0x18]; 4831 4832 u8 reserved_at_c0[0x140]; 4833 }; 4834 4835 struct mlx5_ifc_query_fte_out_bits { 4836 u8 status[0x8]; 4837 u8 reserved_at_8[0x18]; 4838 4839 u8 syndrome[0x20]; 4840 4841 u8 reserved_at_40[0x1c0]; 4842 4843 struct mlx5_ifc_flow_context_bits flow_context; 4844 }; 4845 4846 struct mlx5_ifc_query_fte_in_bits { 4847 u8 opcode[0x10]; 4848 u8 reserved_at_10[0x10]; 4849 4850 u8 reserved_at_20[0x10]; 4851 u8 op_mod[0x10]; 4852 4853 u8 reserved_at_40[0x40]; 4854 4855 u8 table_type[0x8]; 4856 u8 reserved_at_88[0x18]; 4857 4858 u8 reserved_at_a0[0x8]; 4859 u8 table_id[0x18]; 4860 4861 u8 reserved_at_c0[0x40]; 4862 4863 u8 flow_index[0x20]; 4864 4865 u8 reserved_at_120[0xe0]; 4866 }; 4867 4868 enum { 4869 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4870 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4871 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4872 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 4873 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 4874 }; 4875 4876 struct mlx5_ifc_query_flow_group_out_bits { 4877 u8 status[0x8]; 4878 u8 reserved_at_8[0x18]; 4879 4880 u8 syndrome[0x20]; 4881 4882 u8 reserved_at_40[0xa0]; 4883 4884 u8 start_flow_index[0x20]; 4885 4886 u8 reserved_at_100[0x20]; 4887 4888 u8 end_flow_index[0x20]; 4889 4890 u8 reserved_at_140[0xa0]; 4891 4892 u8 reserved_at_1e0[0x18]; 4893 u8 match_criteria_enable[0x8]; 4894 4895 struct mlx5_ifc_fte_match_param_bits match_criteria; 4896 4897 u8 reserved_at_1200[0xe00]; 4898 }; 4899 4900 struct mlx5_ifc_query_flow_group_in_bits { 4901 u8 opcode[0x10]; 4902 u8 reserved_at_10[0x10]; 4903 4904 u8 reserved_at_20[0x10]; 4905 u8 op_mod[0x10]; 4906 4907 u8 reserved_at_40[0x40]; 4908 4909 u8 table_type[0x8]; 4910 u8 reserved_at_88[0x18]; 4911 4912 u8 reserved_at_a0[0x8]; 4913 u8 table_id[0x18]; 4914 4915 u8 group_id[0x20]; 4916 4917 u8 reserved_at_e0[0x120]; 4918 }; 4919 4920 struct mlx5_ifc_query_flow_counter_out_bits { 4921 u8 status[0x8]; 4922 u8 reserved_at_8[0x18]; 4923 4924 u8 syndrome[0x20]; 4925 4926 u8 reserved_at_40[0x40]; 4927 4928 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4929 }; 4930 4931 struct mlx5_ifc_query_flow_counter_in_bits { 4932 u8 opcode[0x10]; 4933 u8 reserved_at_10[0x10]; 4934 4935 u8 reserved_at_20[0x10]; 4936 u8 op_mod[0x10]; 4937 4938 u8 reserved_at_40[0x80]; 4939 4940 u8 clear[0x1]; 4941 u8 reserved_at_c1[0xf]; 4942 u8 num_of_counters[0x10]; 4943 4944 u8 flow_counter_id[0x20]; 4945 }; 4946 4947 struct mlx5_ifc_query_esw_vport_context_out_bits { 4948 u8 status[0x8]; 4949 u8 reserved_at_8[0x18]; 4950 4951 u8 syndrome[0x20]; 4952 4953 u8 reserved_at_40[0x40]; 4954 4955 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4956 }; 4957 4958 struct mlx5_ifc_query_esw_vport_context_in_bits { 4959 u8 opcode[0x10]; 4960 u8 reserved_at_10[0x10]; 4961 4962 u8 reserved_at_20[0x10]; 4963 u8 op_mod[0x10]; 4964 4965 u8 other_vport[0x1]; 4966 u8 reserved_at_41[0xf]; 4967 u8 vport_number[0x10]; 4968 4969 u8 reserved_at_60[0x20]; 4970 }; 4971 4972 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_at_8[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_at_40[0x40]; 4979 }; 4980 4981 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4982 u8 reserved_at_0[0x1c]; 4983 u8 vport_cvlan_insert[0x1]; 4984 u8 vport_svlan_insert[0x1]; 4985 u8 vport_cvlan_strip[0x1]; 4986 u8 vport_svlan_strip[0x1]; 4987 }; 4988 4989 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4990 u8 opcode[0x10]; 4991 u8 reserved_at_10[0x10]; 4992 4993 u8 reserved_at_20[0x10]; 4994 u8 op_mod[0x10]; 4995 4996 u8 other_vport[0x1]; 4997 u8 reserved_at_41[0xf]; 4998 u8 vport_number[0x10]; 4999 5000 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5001 5002 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5003 }; 5004 5005 struct mlx5_ifc_query_eq_out_bits { 5006 u8 status[0x8]; 5007 u8 reserved_at_8[0x18]; 5008 5009 u8 syndrome[0x20]; 5010 5011 u8 reserved_at_40[0x40]; 5012 5013 struct mlx5_ifc_eqc_bits eq_context_entry; 5014 5015 u8 reserved_at_280[0x40]; 5016 5017 u8 event_bitmask[0x40]; 5018 5019 u8 reserved_at_300[0x580]; 5020 5021 u8 pas[0][0x40]; 5022 }; 5023 5024 struct mlx5_ifc_query_eq_in_bits { 5025 u8 opcode[0x10]; 5026 u8 reserved_at_10[0x10]; 5027 5028 u8 reserved_at_20[0x10]; 5029 u8 op_mod[0x10]; 5030 5031 u8 reserved_at_40[0x18]; 5032 u8 eq_number[0x8]; 5033 5034 u8 reserved_at_60[0x20]; 5035 }; 5036 5037 struct mlx5_ifc_packet_reformat_context_in_bits { 5038 u8 reserved_at_0[0x5]; 5039 u8 reformat_type[0x3]; 5040 u8 reserved_at_8[0xe]; 5041 u8 reformat_data_size[0xa]; 5042 5043 u8 reserved_at_20[0x10]; 5044 u8 reformat_data[2][0x8]; 5045 5046 u8 more_reformat_data[0][0x8]; 5047 }; 5048 5049 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_at_8[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 reserved_at_40[0xa0]; 5056 5057 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5058 }; 5059 5060 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5061 u8 opcode[0x10]; 5062 u8 reserved_at_10[0x10]; 5063 5064 u8 reserved_at_20[0x10]; 5065 u8 op_mod[0x10]; 5066 5067 u8 packet_reformat_id[0x20]; 5068 5069 u8 reserved_at_60[0xa0]; 5070 }; 5071 5072 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5073 u8 status[0x8]; 5074 u8 reserved_at_8[0x18]; 5075 5076 u8 syndrome[0x20]; 5077 5078 u8 packet_reformat_id[0x20]; 5079 5080 u8 reserved_at_60[0x20]; 5081 }; 5082 5083 enum { 5084 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5085 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5086 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5087 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5088 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5089 }; 5090 5091 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5092 u8 opcode[0x10]; 5093 u8 reserved_at_10[0x10]; 5094 5095 u8 reserved_at_20[0x10]; 5096 u8 op_mod[0x10]; 5097 5098 u8 reserved_at_40[0xa0]; 5099 5100 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5101 }; 5102 5103 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5104 u8 status[0x8]; 5105 u8 reserved_at_8[0x18]; 5106 5107 u8 syndrome[0x20]; 5108 5109 u8 reserved_at_40[0x40]; 5110 }; 5111 5112 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5113 u8 opcode[0x10]; 5114 u8 reserved_at_10[0x10]; 5115 5116 u8 reserved_20[0x10]; 5117 u8 op_mod[0x10]; 5118 5119 u8 packet_reformat_id[0x20]; 5120 5121 u8 reserved_60[0x20]; 5122 }; 5123 5124 struct mlx5_ifc_set_action_in_bits { 5125 u8 action_type[0x4]; 5126 u8 field[0xc]; 5127 u8 reserved_at_10[0x3]; 5128 u8 offset[0x5]; 5129 u8 reserved_at_18[0x3]; 5130 u8 length[0x5]; 5131 5132 u8 data[0x20]; 5133 }; 5134 5135 struct mlx5_ifc_add_action_in_bits { 5136 u8 action_type[0x4]; 5137 u8 field[0xc]; 5138 u8 reserved_at_10[0x10]; 5139 5140 u8 data[0x20]; 5141 }; 5142 5143 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5144 struct mlx5_ifc_set_action_in_bits set_action_in; 5145 struct mlx5_ifc_add_action_in_bits add_action_in; 5146 u8 reserved_at_0[0x40]; 5147 }; 5148 5149 enum { 5150 MLX5_ACTION_TYPE_SET = 0x1, 5151 MLX5_ACTION_TYPE_ADD = 0x2, 5152 }; 5153 5154 enum { 5155 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5156 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5157 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5158 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5159 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5160 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5161 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5162 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5163 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5164 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5165 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5166 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5167 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5168 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5169 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5170 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5171 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5172 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5173 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5174 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5175 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5176 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5177 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5178 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5179 }; 5180 5181 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5182 u8 status[0x8]; 5183 u8 reserved_at_8[0x18]; 5184 5185 u8 syndrome[0x20]; 5186 5187 u8 modify_header_id[0x20]; 5188 5189 u8 reserved_at_60[0x20]; 5190 }; 5191 5192 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5193 u8 opcode[0x10]; 5194 u8 reserved_at_10[0x10]; 5195 5196 u8 reserved_at_20[0x10]; 5197 u8 op_mod[0x10]; 5198 5199 u8 reserved_at_40[0x20]; 5200 5201 u8 table_type[0x8]; 5202 u8 reserved_at_68[0x10]; 5203 u8 num_of_actions[0x8]; 5204 5205 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5206 }; 5207 5208 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5209 u8 status[0x8]; 5210 u8 reserved_at_8[0x18]; 5211 5212 u8 syndrome[0x20]; 5213 5214 u8 reserved_at_40[0x40]; 5215 }; 5216 5217 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5218 u8 opcode[0x10]; 5219 u8 reserved_at_10[0x10]; 5220 5221 u8 reserved_at_20[0x10]; 5222 u8 op_mod[0x10]; 5223 5224 u8 modify_header_id[0x20]; 5225 5226 u8 reserved_at_60[0x20]; 5227 }; 5228 5229 struct mlx5_ifc_query_dct_out_bits { 5230 u8 status[0x8]; 5231 u8 reserved_at_8[0x18]; 5232 5233 u8 syndrome[0x20]; 5234 5235 u8 reserved_at_40[0x40]; 5236 5237 struct mlx5_ifc_dctc_bits dct_context_entry; 5238 5239 u8 reserved_at_280[0x180]; 5240 }; 5241 5242 struct mlx5_ifc_query_dct_in_bits { 5243 u8 opcode[0x10]; 5244 u8 reserved_at_10[0x10]; 5245 5246 u8 reserved_at_20[0x10]; 5247 u8 op_mod[0x10]; 5248 5249 u8 reserved_at_40[0x8]; 5250 u8 dctn[0x18]; 5251 5252 u8 reserved_at_60[0x20]; 5253 }; 5254 5255 struct mlx5_ifc_query_cq_out_bits { 5256 u8 status[0x8]; 5257 u8 reserved_at_8[0x18]; 5258 5259 u8 syndrome[0x20]; 5260 5261 u8 reserved_at_40[0x40]; 5262 5263 struct mlx5_ifc_cqc_bits cq_context; 5264 5265 u8 reserved_at_280[0x600]; 5266 5267 u8 pas[0][0x40]; 5268 }; 5269 5270 struct mlx5_ifc_query_cq_in_bits { 5271 u8 opcode[0x10]; 5272 u8 reserved_at_10[0x10]; 5273 5274 u8 reserved_at_20[0x10]; 5275 u8 op_mod[0x10]; 5276 5277 u8 reserved_at_40[0x8]; 5278 u8 cqn[0x18]; 5279 5280 u8 reserved_at_60[0x20]; 5281 }; 5282 5283 struct mlx5_ifc_query_cong_status_out_bits { 5284 u8 status[0x8]; 5285 u8 reserved_at_8[0x18]; 5286 5287 u8 syndrome[0x20]; 5288 5289 u8 reserved_at_40[0x20]; 5290 5291 u8 enable[0x1]; 5292 u8 tag_enable[0x1]; 5293 u8 reserved_at_62[0x1e]; 5294 }; 5295 5296 struct mlx5_ifc_query_cong_status_in_bits { 5297 u8 opcode[0x10]; 5298 u8 reserved_at_10[0x10]; 5299 5300 u8 reserved_at_20[0x10]; 5301 u8 op_mod[0x10]; 5302 5303 u8 reserved_at_40[0x18]; 5304 u8 priority[0x4]; 5305 u8 cong_protocol[0x4]; 5306 5307 u8 reserved_at_60[0x20]; 5308 }; 5309 5310 struct mlx5_ifc_query_cong_statistics_out_bits { 5311 u8 status[0x8]; 5312 u8 reserved_at_8[0x18]; 5313 5314 u8 syndrome[0x20]; 5315 5316 u8 reserved_at_40[0x40]; 5317 5318 u8 rp_cur_flows[0x20]; 5319 5320 u8 sum_flows[0x20]; 5321 5322 u8 rp_cnp_ignored_high[0x20]; 5323 5324 u8 rp_cnp_ignored_low[0x20]; 5325 5326 u8 rp_cnp_handled_high[0x20]; 5327 5328 u8 rp_cnp_handled_low[0x20]; 5329 5330 u8 reserved_at_140[0x100]; 5331 5332 u8 time_stamp_high[0x20]; 5333 5334 u8 time_stamp_low[0x20]; 5335 5336 u8 accumulators_period[0x20]; 5337 5338 u8 np_ecn_marked_roce_packets_high[0x20]; 5339 5340 u8 np_ecn_marked_roce_packets_low[0x20]; 5341 5342 u8 np_cnp_sent_high[0x20]; 5343 5344 u8 np_cnp_sent_low[0x20]; 5345 5346 u8 reserved_at_320[0x560]; 5347 }; 5348 5349 struct mlx5_ifc_query_cong_statistics_in_bits { 5350 u8 opcode[0x10]; 5351 u8 reserved_at_10[0x10]; 5352 5353 u8 reserved_at_20[0x10]; 5354 u8 op_mod[0x10]; 5355 5356 u8 clear[0x1]; 5357 u8 reserved_at_41[0x1f]; 5358 5359 u8 reserved_at_60[0x20]; 5360 }; 5361 5362 struct mlx5_ifc_query_cong_params_out_bits { 5363 u8 status[0x8]; 5364 u8 reserved_at_8[0x18]; 5365 5366 u8 syndrome[0x20]; 5367 5368 u8 reserved_at_40[0x40]; 5369 5370 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5371 }; 5372 5373 struct mlx5_ifc_query_cong_params_in_bits { 5374 u8 opcode[0x10]; 5375 u8 reserved_at_10[0x10]; 5376 5377 u8 reserved_at_20[0x10]; 5378 u8 op_mod[0x10]; 5379 5380 u8 reserved_at_40[0x1c]; 5381 u8 cong_protocol[0x4]; 5382 5383 u8 reserved_at_60[0x20]; 5384 }; 5385 5386 struct mlx5_ifc_query_adapter_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_at_8[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_at_40[0x40]; 5393 5394 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5395 }; 5396 5397 struct mlx5_ifc_query_adapter_in_bits { 5398 u8 opcode[0x10]; 5399 u8 reserved_at_10[0x10]; 5400 5401 u8 reserved_at_20[0x10]; 5402 u8 op_mod[0x10]; 5403 5404 u8 reserved_at_40[0x40]; 5405 }; 5406 5407 struct mlx5_ifc_qp_2rst_out_bits { 5408 u8 status[0x8]; 5409 u8 reserved_at_8[0x18]; 5410 5411 u8 syndrome[0x20]; 5412 5413 u8 reserved_at_40[0x40]; 5414 }; 5415 5416 struct mlx5_ifc_qp_2rst_in_bits { 5417 u8 opcode[0x10]; 5418 u8 uid[0x10]; 5419 5420 u8 reserved_at_20[0x10]; 5421 u8 op_mod[0x10]; 5422 5423 u8 reserved_at_40[0x8]; 5424 u8 qpn[0x18]; 5425 5426 u8 reserved_at_60[0x20]; 5427 }; 5428 5429 struct mlx5_ifc_qp_2err_out_bits { 5430 u8 status[0x8]; 5431 u8 reserved_at_8[0x18]; 5432 5433 u8 syndrome[0x20]; 5434 5435 u8 reserved_at_40[0x40]; 5436 }; 5437 5438 struct mlx5_ifc_qp_2err_in_bits { 5439 u8 opcode[0x10]; 5440 u8 uid[0x10]; 5441 5442 u8 reserved_at_20[0x10]; 5443 u8 op_mod[0x10]; 5444 5445 u8 reserved_at_40[0x8]; 5446 u8 qpn[0x18]; 5447 5448 u8 reserved_at_60[0x20]; 5449 }; 5450 5451 struct mlx5_ifc_page_fault_resume_out_bits { 5452 u8 status[0x8]; 5453 u8 reserved_at_8[0x18]; 5454 5455 u8 syndrome[0x20]; 5456 5457 u8 reserved_at_40[0x40]; 5458 }; 5459 5460 struct mlx5_ifc_page_fault_resume_in_bits { 5461 u8 opcode[0x10]; 5462 u8 reserved_at_10[0x10]; 5463 5464 u8 reserved_at_20[0x10]; 5465 u8 op_mod[0x10]; 5466 5467 u8 error[0x1]; 5468 u8 reserved_at_41[0x4]; 5469 u8 page_fault_type[0x3]; 5470 u8 wq_number[0x18]; 5471 5472 u8 reserved_at_60[0x8]; 5473 u8 token[0x18]; 5474 }; 5475 5476 struct mlx5_ifc_nop_out_bits { 5477 u8 status[0x8]; 5478 u8 reserved_at_8[0x18]; 5479 5480 u8 syndrome[0x20]; 5481 5482 u8 reserved_at_40[0x40]; 5483 }; 5484 5485 struct mlx5_ifc_nop_in_bits { 5486 u8 opcode[0x10]; 5487 u8 reserved_at_10[0x10]; 5488 5489 u8 reserved_at_20[0x10]; 5490 u8 op_mod[0x10]; 5491 5492 u8 reserved_at_40[0x40]; 5493 }; 5494 5495 struct mlx5_ifc_modify_vport_state_out_bits { 5496 u8 status[0x8]; 5497 u8 reserved_at_8[0x18]; 5498 5499 u8 syndrome[0x20]; 5500 5501 u8 reserved_at_40[0x40]; 5502 }; 5503 5504 struct mlx5_ifc_modify_vport_state_in_bits { 5505 u8 opcode[0x10]; 5506 u8 reserved_at_10[0x10]; 5507 5508 u8 reserved_at_20[0x10]; 5509 u8 op_mod[0x10]; 5510 5511 u8 other_vport[0x1]; 5512 u8 reserved_at_41[0xf]; 5513 u8 vport_number[0x10]; 5514 5515 u8 reserved_at_60[0x18]; 5516 u8 admin_state[0x4]; 5517 u8 reserved_at_7c[0x4]; 5518 }; 5519 5520 struct mlx5_ifc_modify_tis_out_bits { 5521 u8 status[0x8]; 5522 u8 reserved_at_8[0x18]; 5523 5524 u8 syndrome[0x20]; 5525 5526 u8 reserved_at_40[0x40]; 5527 }; 5528 5529 struct mlx5_ifc_modify_tis_bitmask_bits { 5530 u8 reserved_at_0[0x20]; 5531 5532 u8 reserved_at_20[0x1d]; 5533 u8 lag_tx_port_affinity[0x1]; 5534 u8 strict_lag_tx_port_affinity[0x1]; 5535 u8 prio[0x1]; 5536 }; 5537 5538 struct mlx5_ifc_modify_tis_in_bits { 5539 u8 opcode[0x10]; 5540 u8 uid[0x10]; 5541 5542 u8 reserved_at_20[0x10]; 5543 u8 op_mod[0x10]; 5544 5545 u8 reserved_at_40[0x8]; 5546 u8 tisn[0x18]; 5547 5548 u8 reserved_at_60[0x20]; 5549 5550 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5551 5552 u8 reserved_at_c0[0x40]; 5553 5554 struct mlx5_ifc_tisc_bits ctx; 5555 }; 5556 5557 struct mlx5_ifc_modify_tir_bitmask_bits { 5558 u8 reserved_at_0[0x20]; 5559 5560 u8 reserved_at_20[0x1b]; 5561 u8 self_lb_en[0x1]; 5562 u8 reserved_at_3c[0x1]; 5563 u8 hash[0x1]; 5564 u8 reserved_at_3e[0x1]; 5565 u8 lro[0x1]; 5566 }; 5567 5568 struct mlx5_ifc_modify_tir_out_bits { 5569 u8 status[0x8]; 5570 u8 reserved_at_8[0x18]; 5571 5572 u8 syndrome[0x20]; 5573 5574 u8 reserved_at_40[0x40]; 5575 }; 5576 5577 struct mlx5_ifc_modify_tir_in_bits { 5578 u8 opcode[0x10]; 5579 u8 uid[0x10]; 5580 5581 u8 reserved_at_20[0x10]; 5582 u8 op_mod[0x10]; 5583 5584 u8 reserved_at_40[0x8]; 5585 u8 tirn[0x18]; 5586 5587 u8 reserved_at_60[0x20]; 5588 5589 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5590 5591 u8 reserved_at_c0[0x40]; 5592 5593 struct mlx5_ifc_tirc_bits ctx; 5594 }; 5595 5596 struct mlx5_ifc_modify_sq_out_bits { 5597 u8 status[0x8]; 5598 u8 reserved_at_8[0x18]; 5599 5600 u8 syndrome[0x20]; 5601 5602 u8 reserved_at_40[0x40]; 5603 }; 5604 5605 struct mlx5_ifc_modify_sq_in_bits { 5606 u8 opcode[0x10]; 5607 u8 uid[0x10]; 5608 5609 u8 reserved_at_20[0x10]; 5610 u8 op_mod[0x10]; 5611 5612 u8 sq_state[0x4]; 5613 u8 reserved_at_44[0x4]; 5614 u8 sqn[0x18]; 5615 5616 u8 reserved_at_60[0x20]; 5617 5618 u8 modify_bitmask[0x40]; 5619 5620 u8 reserved_at_c0[0x40]; 5621 5622 struct mlx5_ifc_sqc_bits ctx; 5623 }; 5624 5625 struct mlx5_ifc_modify_scheduling_element_out_bits { 5626 u8 status[0x8]; 5627 u8 reserved_at_8[0x18]; 5628 5629 u8 syndrome[0x20]; 5630 5631 u8 reserved_at_40[0x1c0]; 5632 }; 5633 5634 enum { 5635 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5636 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5637 }; 5638 5639 struct mlx5_ifc_modify_scheduling_element_in_bits { 5640 u8 opcode[0x10]; 5641 u8 reserved_at_10[0x10]; 5642 5643 u8 reserved_at_20[0x10]; 5644 u8 op_mod[0x10]; 5645 5646 u8 scheduling_hierarchy[0x8]; 5647 u8 reserved_at_48[0x18]; 5648 5649 u8 scheduling_element_id[0x20]; 5650 5651 u8 reserved_at_80[0x20]; 5652 5653 u8 modify_bitmask[0x20]; 5654 5655 u8 reserved_at_c0[0x40]; 5656 5657 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5658 5659 u8 reserved_at_300[0x100]; 5660 }; 5661 5662 struct mlx5_ifc_modify_rqt_out_bits { 5663 u8 status[0x8]; 5664 u8 reserved_at_8[0x18]; 5665 5666 u8 syndrome[0x20]; 5667 5668 u8 reserved_at_40[0x40]; 5669 }; 5670 5671 struct mlx5_ifc_rqt_bitmask_bits { 5672 u8 reserved_at_0[0x20]; 5673 5674 u8 reserved_at_20[0x1f]; 5675 u8 rqn_list[0x1]; 5676 }; 5677 5678 struct mlx5_ifc_modify_rqt_in_bits { 5679 u8 opcode[0x10]; 5680 u8 uid[0x10]; 5681 5682 u8 reserved_at_20[0x10]; 5683 u8 op_mod[0x10]; 5684 5685 u8 reserved_at_40[0x8]; 5686 u8 rqtn[0x18]; 5687 5688 u8 reserved_at_60[0x20]; 5689 5690 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5691 5692 u8 reserved_at_c0[0x40]; 5693 5694 struct mlx5_ifc_rqtc_bits ctx; 5695 }; 5696 5697 struct mlx5_ifc_modify_rq_out_bits { 5698 u8 status[0x8]; 5699 u8 reserved_at_8[0x18]; 5700 5701 u8 syndrome[0x20]; 5702 5703 u8 reserved_at_40[0x40]; 5704 }; 5705 5706 enum { 5707 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5708 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5709 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5710 }; 5711 5712 struct mlx5_ifc_modify_rq_in_bits { 5713 u8 opcode[0x10]; 5714 u8 uid[0x10]; 5715 5716 u8 reserved_at_20[0x10]; 5717 u8 op_mod[0x10]; 5718 5719 u8 rq_state[0x4]; 5720 u8 reserved_at_44[0x4]; 5721 u8 rqn[0x18]; 5722 5723 u8 reserved_at_60[0x20]; 5724 5725 u8 modify_bitmask[0x40]; 5726 5727 u8 reserved_at_c0[0x40]; 5728 5729 struct mlx5_ifc_rqc_bits ctx; 5730 }; 5731 5732 struct mlx5_ifc_modify_rmp_out_bits { 5733 u8 status[0x8]; 5734 u8 reserved_at_8[0x18]; 5735 5736 u8 syndrome[0x20]; 5737 5738 u8 reserved_at_40[0x40]; 5739 }; 5740 5741 struct mlx5_ifc_rmp_bitmask_bits { 5742 u8 reserved_at_0[0x20]; 5743 5744 u8 reserved_at_20[0x1f]; 5745 u8 lwm[0x1]; 5746 }; 5747 5748 struct mlx5_ifc_modify_rmp_in_bits { 5749 u8 opcode[0x10]; 5750 u8 uid[0x10]; 5751 5752 u8 reserved_at_20[0x10]; 5753 u8 op_mod[0x10]; 5754 5755 u8 rmp_state[0x4]; 5756 u8 reserved_at_44[0x4]; 5757 u8 rmpn[0x18]; 5758 5759 u8 reserved_at_60[0x20]; 5760 5761 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5762 5763 u8 reserved_at_c0[0x40]; 5764 5765 struct mlx5_ifc_rmpc_bits ctx; 5766 }; 5767 5768 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5769 u8 status[0x8]; 5770 u8 reserved_at_8[0x18]; 5771 5772 u8 syndrome[0x20]; 5773 5774 u8 reserved_at_40[0x40]; 5775 }; 5776 5777 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5778 u8 reserved_at_0[0x12]; 5779 u8 affiliation[0x1]; 5780 u8 reserved_at_13[0x1]; 5781 u8 disable_uc_local_lb[0x1]; 5782 u8 disable_mc_local_lb[0x1]; 5783 u8 node_guid[0x1]; 5784 u8 port_guid[0x1]; 5785 u8 min_inline[0x1]; 5786 u8 mtu[0x1]; 5787 u8 change_event[0x1]; 5788 u8 promisc[0x1]; 5789 u8 permanent_address[0x1]; 5790 u8 addresses_list[0x1]; 5791 u8 roce_en[0x1]; 5792 u8 reserved_at_1f[0x1]; 5793 }; 5794 5795 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5796 u8 opcode[0x10]; 5797 u8 reserved_at_10[0x10]; 5798 5799 u8 reserved_at_20[0x10]; 5800 u8 op_mod[0x10]; 5801 5802 u8 other_vport[0x1]; 5803 u8 reserved_at_41[0xf]; 5804 u8 vport_number[0x10]; 5805 5806 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5807 5808 u8 reserved_at_80[0x780]; 5809 5810 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5811 }; 5812 5813 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5814 u8 status[0x8]; 5815 u8 reserved_at_8[0x18]; 5816 5817 u8 syndrome[0x20]; 5818 5819 u8 reserved_at_40[0x40]; 5820 }; 5821 5822 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5823 u8 opcode[0x10]; 5824 u8 reserved_at_10[0x10]; 5825 5826 u8 reserved_at_20[0x10]; 5827 u8 op_mod[0x10]; 5828 5829 u8 other_vport[0x1]; 5830 u8 reserved_at_41[0xb]; 5831 u8 port_num[0x4]; 5832 u8 vport_number[0x10]; 5833 5834 u8 reserved_at_60[0x20]; 5835 5836 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5837 }; 5838 5839 struct mlx5_ifc_modify_cq_out_bits { 5840 u8 status[0x8]; 5841 u8 reserved_at_8[0x18]; 5842 5843 u8 syndrome[0x20]; 5844 5845 u8 reserved_at_40[0x40]; 5846 }; 5847 5848 enum { 5849 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5850 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5851 }; 5852 5853 struct mlx5_ifc_modify_cq_in_bits { 5854 u8 opcode[0x10]; 5855 u8 uid[0x10]; 5856 5857 u8 reserved_at_20[0x10]; 5858 u8 op_mod[0x10]; 5859 5860 u8 reserved_at_40[0x8]; 5861 u8 cqn[0x18]; 5862 5863 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5864 5865 struct mlx5_ifc_cqc_bits cq_context; 5866 5867 u8 reserved_at_280[0x40]; 5868 5869 u8 cq_umem_valid[0x1]; 5870 u8 reserved_at_2c1[0x5bf]; 5871 5872 u8 pas[0][0x40]; 5873 }; 5874 5875 struct mlx5_ifc_modify_cong_status_out_bits { 5876 u8 status[0x8]; 5877 u8 reserved_at_8[0x18]; 5878 5879 u8 syndrome[0x20]; 5880 5881 u8 reserved_at_40[0x40]; 5882 }; 5883 5884 struct mlx5_ifc_modify_cong_status_in_bits { 5885 u8 opcode[0x10]; 5886 u8 reserved_at_10[0x10]; 5887 5888 u8 reserved_at_20[0x10]; 5889 u8 op_mod[0x10]; 5890 5891 u8 reserved_at_40[0x18]; 5892 u8 priority[0x4]; 5893 u8 cong_protocol[0x4]; 5894 5895 u8 enable[0x1]; 5896 u8 tag_enable[0x1]; 5897 u8 reserved_at_62[0x1e]; 5898 }; 5899 5900 struct mlx5_ifc_modify_cong_params_out_bits { 5901 u8 status[0x8]; 5902 u8 reserved_at_8[0x18]; 5903 5904 u8 syndrome[0x20]; 5905 5906 u8 reserved_at_40[0x40]; 5907 }; 5908 5909 struct mlx5_ifc_modify_cong_params_in_bits { 5910 u8 opcode[0x10]; 5911 u8 reserved_at_10[0x10]; 5912 5913 u8 reserved_at_20[0x10]; 5914 u8 op_mod[0x10]; 5915 5916 u8 reserved_at_40[0x1c]; 5917 u8 cong_protocol[0x4]; 5918 5919 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5920 5921 u8 reserved_at_80[0x80]; 5922 5923 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5924 }; 5925 5926 struct mlx5_ifc_manage_pages_out_bits { 5927 u8 status[0x8]; 5928 u8 reserved_at_8[0x18]; 5929 5930 u8 syndrome[0x20]; 5931 5932 u8 output_num_entries[0x20]; 5933 5934 u8 reserved_at_60[0x20]; 5935 5936 u8 pas[0][0x40]; 5937 }; 5938 5939 enum { 5940 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5941 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5942 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5943 }; 5944 5945 struct mlx5_ifc_manage_pages_in_bits { 5946 u8 opcode[0x10]; 5947 u8 reserved_at_10[0x10]; 5948 5949 u8 reserved_at_20[0x10]; 5950 u8 op_mod[0x10]; 5951 5952 u8 embedded_cpu_function[0x1]; 5953 u8 reserved_at_41[0xf]; 5954 u8 function_id[0x10]; 5955 5956 u8 input_num_entries[0x20]; 5957 5958 u8 pas[0][0x40]; 5959 }; 5960 5961 struct mlx5_ifc_mad_ifc_out_bits { 5962 u8 status[0x8]; 5963 u8 reserved_at_8[0x18]; 5964 5965 u8 syndrome[0x20]; 5966 5967 u8 reserved_at_40[0x40]; 5968 5969 u8 response_mad_packet[256][0x8]; 5970 }; 5971 5972 struct mlx5_ifc_mad_ifc_in_bits { 5973 u8 opcode[0x10]; 5974 u8 reserved_at_10[0x10]; 5975 5976 u8 reserved_at_20[0x10]; 5977 u8 op_mod[0x10]; 5978 5979 u8 remote_lid[0x10]; 5980 u8 reserved_at_50[0x8]; 5981 u8 port[0x8]; 5982 5983 u8 reserved_at_60[0x20]; 5984 5985 u8 mad[256][0x8]; 5986 }; 5987 5988 struct mlx5_ifc_init_hca_out_bits { 5989 u8 status[0x8]; 5990 u8 reserved_at_8[0x18]; 5991 5992 u8 syndrome[0x20]; 5993 5994 u8 reserved_at_40[0x40]; 5995 }; 5996 5997 struct mlx5_ifc_init_hca_in_bits { 5998 u8 opcode[0x10]; 5999 u8 reserved_at_10[0x10]; 6000 6001 u8 reserved_at_20[0x10]; 6002 u8 op_mod[0x10]; 6003 6004 u8 reserved_at_40[0x40]; 6005 u8 sw_owner_id[4][0x20]; 6006 }; 6007 6008 struct mlx5_ifc_init2rtr_qp_out_bits { 6009 u8 status[0x8]; 6010 u8 reserved_at_8[0x18]; 6011 6012 u8 syndrome[0x20]; 6013 6014 u8 reserved_at_40[0x40]; 6015 }; 6016 6017 struct mlx5_ifc_init2rtr_qp_in_bits { 6018 u8 opcode[0x10]; 6019 u8 uid[0x10]; 6020 6021 u8 reserved_at_20[0x10]; 6022 u8 op_mod[0x10]; 6023 6024 u8 reserved_at_40[0x8]; 6025 u8 qpn[0x18]; 6026 6027 u8 reserved_at_60[0x20]; 6028 6029 u8 opt_param_mask[0x20]; 6030 6031 u8 reserved_at_a0[0x20]; 6032 6033 struct mlx5_ifc_qpc_bits qpc; 6034 6035 u8 reserved_at_800[0x80]; 6036 }; 6037 6038 struct mlx5_ifc_init2init_qp_out_bits { 6039 u8 status[0x8]; 6040 u8 reserved_at_8[0x18]; 6041 6042 u8 syndrome[0x20]; 6043 6044 u8 reserved_at_40[0x40]; 6045 }; 6046 6047 struct mlx5_ifc_init2init_qp_in_bits { 6048 u8 opcode[0x10]; 6049 u8 uid[0x10]; 6050 6051 u8 reserved_at_20[0x10]; 6052 u8 op_mod[0x10]; 6053 6054 u8 reserved_at_40[0x8]; 6055 u8 qpn[0x18]; 6056 6057 u8 reserved_at_60[0x20]; 6058 6059 u8 opt_param_mask[0x20]; 6060 6061 u8 reserved_at_a0[0x20]; 6062 6063 struct mlx5_ifc_qpc_bits qpc; 6064 6065 u8 reserved_at_800[0x80]; 6066 }; 6067 6068 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6069 u8 status[0x8]; 6070 u8 reserved_at_8[0x18]; 6071 6072 u8 syndrome[0x20]; 6073 6074 u8 reserved_at_40[0x40]; 6075 6076 u8 packet_headers_log[128][0x8]; 6077 6078 u8 packet_syndrome[64][0x8]; 6079 }; 6080 6081 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6082 u8 opcode[0x10]; 6083 u8 reserved_at_10[0x10]; 6084 6085 u8 reserved_at_20[0x10]; 6086 u8 op_mod[0x10]; 6087 6088 u8 reserved_at_40[0x40]; 6089 }; 6090 6091 struct mlx5_ifc_gen_eqe_in_bits { 6092 u8 opcode[0x10]; 6093 u8 reserved_at_10[0x10]; 6094 6095 u8 reserved_at_20[0x10]; 6096 u8 op_mod[0x10]; 6097 6098 u8 reserved_at_40[0x18]; 6099 u8 eq_number[0x8]; 6100 6101 u8 reserved_at_60[0x20]; 6102 6103 u8 eqe[64][0x8]; 6104 }; 6105 6106 struct mlx5_ifc_gen_eq_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_at_8[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_at_40[0x40]; 6113 }; 6114 6115 struct mlx5_ifc_enable_hca_out_bits { 6116 u8 status[0x8]; 6117 u8 reserved_at_8[0x18]; 6118 6119 u8 syndrome[0x20]; 6120 6121 u8 reserved_at_40[0x20]; 6122 }; 6123 6124 struct mlx5_ifc_enable_hca_in_bits { 6125 u8 opcode[0x10]; 6126 u8 reserved_at_10[0x10]; 6127 6128 u8 reserved_at_20[0x10]; 6129 u8 op_mod[0x10]; 6130 6131 u8 embedded_cpu_function[0x1]; 6132 u8 reserved_at_41[0xf]; 6133 u8 function_id[0x10]; 6134 6135 u8 reserved_at_60[0x20]; 6136 }; 6137 6138 struct mlx5_ifc_drain_dct_out_bits { 6139 u8 status[0x8]; 6140 u8 reserved_at_8[0x18]; 6141 6142 u8 syndrome[0x20]; 6143 6144 u8 reserved_at_40[0x40]; 6145 }; 6146 6147 struct mlx5_ifc_drain_dct_in_bits { 6148 u8 opcode[0x10]; 6149 u8 uid[0x10]; 6150 6151 u8 reserved_at_20[0x10]; 6152 u8 op_mod[0x10]; 6153 6154 u8 reserved_at_40[0x8]; 6155 u8 dctn[0x18]; 6156 6157 u8 reserved_at_60[0x20]; 6158 }; 6159 6160 struct mlx5_ifc_disable_hca_out_bits { 6161 u8 status[0x8]; 6162 u8 reserved_at_8[0x18]; 6163 6164 u8 syndrome[0x20]; 6165 6166 u8 reserved_at_40[0x20]; 6167 }; 6168 6169 struct mlx5_ifc_disable_hca_in_bits { 6170 u8 opcode[0x10]; 6171 u8 reserved_at_10[0x10]; 6172 6173 u8 reserved_at_20[0x10]; 6174 u8 op_mod[0x10]; 6175 6176 u8 embedded_cpu_function[0x1]; 6177 u8 reserved_at_41[0xf]; 6178 u8 function_id[0x10]; 6179 6180 u8 reserved_at_60[0x20]; 6181 }; 6182 6183 struct mlx5_ifc_detach_from_mcg_out_bits { 6184 u8 status[0x8]; 6185 u8 reserved_at_8[0x18]; 6186 6187 u8 syndrome[0x20]; 6188 6189 u8 reserved_at_40[0x40]; 6190 }; 6191 6192 struct mlx5_ifc_detach_from_mcg_in_bits { 6193 u8 opcode[0x10]; 6194 u8 uid[0x10]; 6195 6196 u8 reserved_at_20[0x10]; 6197 u8 op_mod[0x10]; 6198 6199 u8 reserved_at_40[0x8]; 6200 u8 qpn[0x18]; 6201 6202 u8 reserved_at_60[0x20]; 6203 6204 u8 multicast_gid[16][0x8]; 6205 }; 6206 6207 struct mlx5_ifc_destroy_xrq_out_bits { 6208 u8 status[0x8]; 6209 u8 reserved_at_8[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 reserved_at_40[0x40]; 6214 }; 6215 6216 struct mlx5_ifc_destroy_xrq_in_bits { 6217 u8 opcode[0x10]; 6218 u8 uid[0x10]; 6219 6220 u8 reserved_at_20[0x10]; 6221 u8 op_mod[0x10]; 6222 6223 u8 reserved_at_40[0x8]; 6224 u8 xrqn[0x18]; 6225 6226 u8 reserved_at_60[0x20]; 6227 }; 6228 6229 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6230 u8 status[0x8]; 6231 u8 reserved_at_8[0x18]; 6232 6233 u8 syndrome[0x20]; 6234 6235 u8 reserved_at_40[0x40]; 6236 }; 6237 6238 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6239 u8 opcode[0x10]; 6240 u8 uid[0x10]; 6241 6242 u8 reserved_at_20[0x10]; 6243 u8 op_mod[0x10]; 6244 6245 u8 reserved_at_40[0x8]; 6246 u8 xrc_srqn[0x18]; 6247 6248 u8 reserved_at_60[0x20]; 6249 }; 6250 6251 struct mlx5_ifc_destroy_tis_out_bits { 6252 u8 status[0x8]; 6253 u8 reserved_at_8[0x18]; 6254 6255 u8 syndrome[0x20]; 6256 6257 u8 reserved_at_40[0x40]; 6258 }; 6259 6260 struct mlx5_ifc_destroy_tis_in_bits { 6261 u8 opcode[0x10]; 6262 u8 uid[0x10]; 6263 6264 u8 reserved_at_20[0x10]; 6265 u8 op_mod[0x10]; 6266 6267 u8 reserved_at_40[0x8]; 6268 u8 tisn[0x18]; 6269 6270 u8 reserved_at_60[0x20]; 6271 }; 6272 6273 struct mlx5_ifc_destroy_tir_out_bits { 6274 u8 status[0x8]; 6275 u8 reserved_at_8[0x18]; 6276 6277 u8 syndrome[0x20]; 6278 6279 u8 reserved_at_40[0x40]; 6280 }; 6281 6282 struct mlx5_ifc_destroy_tir_in_bits { 6283 u8 opcode[0x10]; 6284 u8 uid[0x10]; 6285 6286 u8 reserved_at_20[0x10]; 6287 u8 op_mod[0x10]; 6288 6289 u8 reserved_at_40[0x8]; 6290 u8 tirn[0x18]; 6291 6292 u8 reserved_at_60[0x20]; 6293 }; 6294 6295 struct mlx5_ifc_destroy_srq_out_bits { 6296 u8 status[0x8]; 6297 u8 reserved_at_8[0x18]; 6298 6299 u8 syndrome[0x20]; 6300 6301 u8 reserved_at_40[0x40]; 6302 }; 6303 6304 struct mlx5_ifc_destroy_srq_in_bits { 6305 u8 opcode[0x10]; 6306 u8 uid[0x10]; 6307 6308 u8 reserved_at_20[0x10]; 6309 u8 op_mod[0x10]; 6310 6311 u8 reserved_at_40[0x8]; 6312 u8 srqn[0x18]; 6313 6314 u8 reserved_at_60[0x20]; 6315 }; 6316 6317 struct mlx5_ifc_destroy_sq_out_bits { 6318 u8 status[0x8]; 6319 u8 reserved_at_8[0x18]; 6320 6321 u8 syndrome[0x20]; 6322 6323 u8 reserved_at_40[0x40]; 6324 }; 6325 6326 struct mlx5_ifc_destroy_sq_in_bits { 6327 u8 opcode[0x10]; 6328 u8 uid[0x10]; 6329 6330 u8 reserved_at_20[0x10]; 6331 u8 op_mod[0x10]; 6332 6333 u8 reserved_at_40[0x8]; 6334 u8 sqn[0x18]; 6335 6336 u8 reserved_at_60[0x20]; 6337 }; 6338 6339 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6340 u8 status[0x8]; 6341 u8 reserved_at_8[0x18]; 6342 6343 u8 syndrome[0x20]; 6344 6345 u8 reserved_at_40[0x1c0]; 6346 }; 6347 6348 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6349 u8 opcode[0x10]; 6350 u8 reserved_at_10[0x10]; 6351 6352 u8 reserved_at_20[0x10]; 6353 u8 op_mod[0x10]; 6354 6355 u8 scheduling_hierarchy[0x8]; 6356 u8 reserved_at_48[0x18]; 6357 6358 u8 scheduling_element_id[0x20]; 6359 6360 u8 reserved_at_80[0x180]; 6361 }; 6362 6363 struct mlx5_ifc_destroy_rqt_out_bits { 6364 u8 status[0x8]; 6365 u8 reserved_at_8[0x18]; 6366 6367 u8 syndrome[0x20]; 6368 6369 u8 reserved_at_40[0x40]; 6370 }; 6371 6372 struct mlx5_ifc_destroy_rqt_in_bits { 6373 u8 opcode[0x10]; 6374 u8 uid[0x10]; 6375 6376 u8 reserved_at_20[0x10]; 6377 u8 op_mod[0x10]; 6378 6379 u8 reserved_at_40[0x8]; 6380 u8 rqtn[0x18]; 6381 6382 u8 reserved_at_60[0x20]; 6383 }; 6384 6385 struct mlx5_ifc_destroy_rq_out_bits { 6386 u8 status[0x8]; 6387 u8 reserved_at_8[0x18]; 6388 6389 u8 syndrome[0x20]; 6390 6391 u8 reserved_at_40[0x40]; 6392 }; 6393 6394 struct mlx5_ifc_destroy_rq_in_bits { 6395 u8 opcode[0x10]; 6396 u8 uid[0x10]; 6397 6398 u8 reserved_at_20[0x10]; 6399 u8 op_mod[0x10]; 6400 6401 u8 reserved_at_40[0x8]; 6402 u8 rqn[0x18]; 6403 6404 u8 reserved_at_60[0x20]; 6405 }; 6406 6407 struct mlx5_ifc_set_delay_drop_params_in_bits { 6408 u8 opcode[0x10]; 6409 u8 reserved_at_10[0x10]; 6410 6411 u8 reserved_at_20[0x10]; 6412 u8 op_mod[0x10]; 6413 6414 u8 reserved_at_40[0x20]; 6415 6416 u8 reserved_at_60[0x10]; 6417 u8 delay_drop_timeout[0x10]; 6418 }; 6419 6420 struct mlx5_ifc_set_delay_drop_params_out_bits { 6421 u8 status[0x8]; 6422 u8 reserved_at_8[0x18]; 6423 6424 u8 syndrome[0x20]; 6425 6426 u8 reserved_at_40[0x40]; 6427 }; 6428 6429 struct mlx5_ifc_destroy_rmp_out_bits { 6430 u8 status[0x8]; 6431 u8 reserved_at_8[0x18]; 6432 6433 u8 syndrome[0x20]; 6434 6435 u8 reserved_at_40[0x40]; 6436 }; 6437 6438 struct mlx5_ifc_destroy_rmp_in_bits { 6439 u8 opcode[0x10]; 6440 u8 uid[0x10]; 6441 6442 u8 reserved_at_20[0x10]; 6443 u8 op_mod[0x10]; 6444 6445 u8 reserved_at_40[0x8]; 6446 u8 rmpn[0x18]; 6447 6448 u8 reserved_at_60[0x20]; 6449 }; 6450 6451 struct mlx5_ifc_destroy_qp_out_bits { 6452 u8 status[0x8]; 6453 u8 reserved_at_8[0x18]; 6454 6455 u8 syndrome[0x20]; 6456 6457 u8 reserved_at_40[0x40]; 6458 }; 6459 6460 struct mlx5_ifc_destroy_qp_in_bits { 6461 u8 opcode[0x10]; 6462 u8 uid[0x10]; 6463 6464 u8 reserved_at_20[0x10]; 6465 u8 op_mod[0x10]; 6466 6467 u8 reserved_at_40[0x8]; 6468 u8 qpn[0x18]; 6469 6470 u8 reserved_at_60[0x20]; 6471 }; 6472 6473 struct mlx5_ifc_destroy_psv_out_bits { 6474 u8 status[0x8]; 6475 u8 reserved_at_8[0x18]; 6476 6477 u8 syndrome[0x20]; 6478 6479 u8 reserved_at_40[0x40]; 6480 }; 6481 6482 struct mlx5_ifc_destroy_psv_in_bits { 6483 u8 opcode[0x10]; 6484 u8 reserved_at_10[0x10]; 6485 6486 u8 reserved_at_20[0x10]; 6487 u8 op_mod[0x10]; 6488 6489 u8 reserved_at_40[0x8]; 6490 u8 psvn[0x18]; 6491 6492 u8 reserved_at_60[0x20]; 6493 }; 6494 6495 struct mlx5_ifc_destroy_mkey_out_bits { 6496 u8 status[0x8]; 6497 u8 reserved_at_8[0x18]; 6498 6499 u8 syndrome[0x20]; 6500 6501 u8 reserved_at_40[0x40]; 6502 }; 6503 6504 struct mlx5_ifc_destroy_mkey_in_bits { 6505 u8 opcode[0x10]; 6506 u8 reserved_at_10[0x10]; 6507 6508 u8 reserved_at_20[0x10]; 6509 u8 op_mod[0x10]; 6510 6511 u8 reserved_at_40[0x8]; 6512 u8 mkey_index[0x18]; 6513 6514 u8 reserved_at_60[0x20]; 6515 }; 6516 6517 struct mlx5_ifc_destroy_flow_table_out_bits { 6518 u8 status[0x8]; 6519 u8 reserved_at_8[0x18]; 6520 6521 u8 syndrome[0x20]; 6522 6523 u8 reserved_at_40[0x40]; 6524 }; 6525 6526 struct mlx5_ifc_destroy_flow_table_in_bits { 6527 u8 opcode[0x10]; 6528 u8 reserved_at_10[0x10]; 6529 6530 u8 reserved_at_20[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 other_vport[0x1]; 6534 u8 reserved_at_41[0xf]; 6535 u8 vport_number[0x10]; 6536 6537 u8 reserved_at_60[0x20]; 6538 6539 u8 table_type[0x8]; 6540 u8 reserved_at_88[0x18]; 6541 6542 u8 reserved_at_a0[0x8]; 6543 u8 table_id[0x18]; 6544 6545 u8 reserved_at_c0[0x140]; 6546 }; 6547 6548 struct mlx5_ifc_destroy_flow_group_out_bits { 6549 u8 status[0x8]; 6550 u8 reserved_at_8[0x18]; 6551 6552 u8 syndrome[0x20]; 6553 6554 u8 reserved_at_40[0x40]; 6555 }; 6556 6557 struct mlx5_ifc_destroy_flow_group_in_bits { 6558 u8 opcode[0x10]; 6559 u8 reserved_at_10[0x10]; 6560 6561 u8 reserved_at_20[0x10]; 6562 u8 op_mod[0x10]; 6563 6564 u8 other_vport[0x1]; 6565 u8 reserved_at_41[0xf]; 6566 u8 vport_number[0x10]; 6567 6568 u8 reserved_at_60[0x20]; 6569 6570 u8 table_type[0x8]; 6571 u8 reserved_at_88[0x18]; 6572 6573 u8 reserved_at_a0[0x8]; 6574 u8 table_id[0x18]; 6575 6576 u8 group_id[0x20]; 6577 6578 u8 reserved_at_e0[0x120]; 6579 }; 6580 6581 struct mlx5_ifc_destroy_eq_out_bits { 6582 u8 status[0x8]; 6583 u8 reserved_at_8[0x18]; 6584 6585 u8 syndrome[0x20]; 6586 6587 u8 reserved_at_40[0x40]; 6588 }; 6589 6590 struct mlx5_ifc_destroy_eq_in_bits { 6591 u8 opcode[0x10]; 6592 u8 reserved_at_10[0x10]; 6593 6594 u8 reserved_at_20[0x10]; 6595 u8 op_mod[0x10]; 6596 6597 u8 reserved_at_40[0x18]; 6598 u8 eq_number[0x8]; 6599 6600 u8 reserved_at_60[0x20]; 6601 }; 6602 6603 struct mlx5_ifc_destroy_dct_out_bits { 6604 u8 status[0x8]; 6605 u8 reserved_at_8[0x18]; 6606 6607 u8 syndrome[0x20]; 6608 6609 u8 reserved_at_40[0x40]; 6610 }; 6611 6612 struct mlx5_ifc_destroy_dct_in_bits { 6613 u8 opcode[0x10]; 6614 u8 uid[0x10]; 6615 6616 u8 reserved_at_20[0x10]; 6617 u8 op_mod[0x10]; 6618 6619 u8 reserved_at_40[0x8]; 6620 u8 dctn[0x18]; 6621 6622 u8 reserved_at_60[0x20]; 6623 }; 6624 6625 struct mlx5_ifc_destroy_cq_out_bits { 6626 u8 status[0x8]; 6627 u8 reserved_at_8[0x18]; 6628 6629 u8 syndrome[0x20]; 6630 6631 u8 reserved_at_40[0x40]; 6632 }; 6633 6634 struct mlx5_ifc_destroy_cq_in_bits { 6635 u8 opcode[0x10]; 6636 u8 uid[0x10]; 6637 6638 u8 reserved_at_20[0x10]; 6639 u8 op_mod[0x10]; 6640 6641 u8 reserved_at_40[0x8]; 6642 u8 cqn[0x18]; 6643 6644 u8 reserved_at_60[0x20]; 6645 }; 6646 6647 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6648 u8 status[0x8]; 6649 u8 reserved_at_8[0x18]; 6650 6651 u8 syndrome[0x20]; 6652 6653 u8 reserved_at_40[0x40]; 6654 }; 6655 6656 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6657 u8 opcode[0x10]; 6658 u8 reserved_at_10[0x10]; 6659 6660 u8 reserved_at_20[0x10]; 6661 u8 op_mod[0x10]; 6662 6663 u8 reserved_at_40[0x20]; 6664 6665 u8 reserved_at_60[0x10]; 6666 u8 vxlan_udp_port[0x10]; 6667 }; 6668 6669 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6670 u8 status[0x8]; 6671 u8 reserved_at_8[0x18]; 6672 6673 u8 syndrome[0x20]; 6674 6675 u8 reserved_at_40[0x40]; 6676 }; 6677 6678 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6679 u8 opcode[0x10]; 6680 u8 reserved_at_10[0x10]; 6681 6682 u8 reserved_at_20[0x10]; 6683 u8 op_mod[0x10]; 6684 6685 u8 reserved_at_40[0x60]; 6686 6687 u8 reserved_at_a0[0x8]; 6688 u8 table_index[0x18]; 6689 6690 u8 reserved_at_c0[0x140]; 6691 }; 6692 6693 struct mlx5_ifc_delete_fte_out_bits { 6694 u8 status[0x8]; 6695 u8 reserved_at_8[0x18]; 6696 6697 u8 syndrome[0x20]; 6698 6699 u8 reserved_at_40[0x40]; 6700 }; 6701 6702 struct mlx5_ifc_delete_fte_in_bits { 6703 u8 opcode[0x10]; 6704 u8 reserved_at_10[0x10]; 6705 6706 u8 reserved_at_20[0x10]; 6707 u8 op_mod[0x10]; 6708 6709 u8 other_vport[0x1]; 6710 u8 reserved_at_41[0xf]; 6711 u8 vport_number[0x10]; 6712 6713 u8 reserved_at_60[0x20]; 6714 6715 u8 table_type[0x8]; 6716 u8 reserved_at_88[0x18]; 6717 6718 u8 reserved_at_a0[0x8]; 6719 u8 table_id[0x18]; 6720 6721 u8 reserved_at_c0[0x40]; 6722 6723 u8 flow_index[0x20]; 6724 6725 u8 reserved_at_120[0xe0]; 6726 }; 6727 6728 struct mlx5_ifc_dealloc_xrcd_out_bits { 6729 u8 status[0x8]; 6730 u8 reserved_at_8[0x18]; 6731 6732 u8 syndrome[0x20]; 6733 6734 u8 reserved_at_40[0x40]; 6735 }; 6736 6737 struct mlx5_ifc_dealloc_xrcd_in_bits { 6738 u8 opcode[0x10]; 6739 u8 uid[0x10]; 6740 6741 u8 reserved_at_20[0x10]; 6742 u8 op_mod[0x10]; 6743 6744 u8 reserved_at_40[0x8]; 6745 u8 xrcd[0x18]; 6746 6747 u8 reserved_at_60[0x20]; 6748 }; 6749 6750 struct mlx5_ifc_dealloc_uar_out_bits { 6751 u8 status[0x8]; 6752 u8 reserved_at_8[0x18]; 6753 6754 u8 syndrome[0x20]; 6755 6756 u8 reserved_at_40[0x40]; 6757 }; 6758 6759 struct mlx5_ifc_dealloc_uar_in_bits { 6760 u8 opcode[0x10]; 6761 u8 reserved_at_10[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 reserved_at_40[0x8]; 6767 u8 uar[0x18]; 6768 6769 u8 reserved_at_60[0x20]; 6770 }; 6771 6772 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6773 u8 status[0x8]; 6774 u8 reserved_at_8[0x18]; 6775 6776 u8 syndrome[0x20]; 6777 6778 u8 reserved_at_40[0x40]; 6779 }; 6780 6781 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6782 u8 opcode[0x10]; 6783 u8 uid[0x10]; 6784 6785 u8 reserved_at_20[0x10]; 6786 u8 op_mod[0x10]; 6787 6788 u8 reserved_at_40[0x8]; 6789 u8 transport_domain[0x18]; 6790 6791 u8 reserved_at_60[0x20]; 6792 }; 6793 6794 struct mlx5_ifc_dealloc_q_counter_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_at_8[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 reserved_at_40[0x40]; 6801 }; 6802 6803 struct mlx5_ifc_dealloc_q_counter_in_bits { 6804 u8 opcode[0x10]; 6805 u8 reserved_at_10[0x10]; 6806 6807 u8 reserved_at_20[0x10]; 6808 u8 op_mod[0x10]; 6809 6810 u8 reserved_at_40[0x18]; 6811 u8 counter_set_id[0x8]; 6812 6813 u8 reserved_at_60[0x20]; 6814 }; 6815 6816 struct mlx5_ifc_dealloc_pd_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_at_8[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_at_40[0x40]; 6823 }; 6824 6825 struct mlx5_ifc_dealloc_pd_in_bits { 6826 u8 opcode[0x10]; 6827 u8 uid[0x10]; 6828 6829 u8 reserved_at_20[0x10]; 6830 u8 op_mod[0x10]; 6831 6832 u8 reserved_at_40[0x8]; 6833 u8 pd[0x18]; 6834 6835 u8 reserved_at_60[0x20]; 6836 }; 6837 6838 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6839 u8 status[0x8]; 6840 u8 reserved_at_8[0x18]; 6841 6842 u8 syndrome[0x20]; 6843 6844 u8 reserved_at_40[0x40]; 6845 }; 6846 6847 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6848 u8 opcode[0x10]; 6849 u8 reserved_at_10[0x10]; 6850 6851 u8 reserved_at_20[0x10]; 6852 u8 op_mod[0x10]; 6853 6854 u8 flow_counter_id[0x20]; 6855 6856 u8 reserved_at_60[0x20]; 6857 }; 6858 6859 struct mlx5_ifc_create_xrq_out_bits { 6860 u8 status[0x8]; 6861 u8 reserved_at_8[0x18]; 6862 6863 u8 syndrome[0x20]; 6864 6865 u8 reserved_at_40[0x8]; 6866 u8 xrqn[0x18]; 6867 6868 u8 reserved_at_60[0x20]; 6869 }; 6870 6871 struct mlx5_ifc_create_xrq_in_bits { 6872 u8 opcode[0x10]; 6873 u8 uid[0x10]; 6874 6875 u8 reserved_at_20[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 reserved_at_40[0x40]; 6879 6880 struct mlx5_ifc_xrqc_bits xrq_context; 6881 }; 6882 6883 struct mlx5_ifc_create_xrc_srq_out_bits { 6884 u8 status[0x8]; 6885 u8 reserved_at_8[0x18]; 6886 6887 u8 syndrome[0x20]; 6888 6889 u8 reserved_at_40[0x8]; 6890 u8 xrc_srqn[0x18]; 6891 6892 u8 reserved_at_60[0x20]; 6893 }; 6894 6895 struct mlx5_ifc_create_xrc_srq_in_bits { 6896 u8 opcode[0x10]; 6897 u8 uid[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 reserved_at_40[0x40]; 6903 6904 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6905 6906 u8 reserved_at_280[0x60]; 6907 6908 u8 xrc_srq_umem_valid[0x1]; 6909 u8 reserved_at_2e1[0x1f]; 6910 6911 u8 reserved_at_300[0x580]; 6912 6913 u8 pas[0][0x40]; 6914 }; 6915 6916 struct mlx5_ifc_create_tis_out_bits { 6917 u8 status[0x8]; 6918 u8 reserved_at_8[0x18]; 6919 6920 u8 syndrome[0x20]; 6921 6922 u8 reserved_at_40[0x8]; 6923 u8 tisn[0x18]; 6924 6925 u8 reserved_at_60[0x20]; 6926 }; 6927 6928 struct mlx5_ifc_create_tis_in_bits { 6929 u8 opcode[0x10]; 6930 u8 uid[0x10]; 6931 6932 u8 reserved_at_20[0x10]; 6933 u8 op_mod[0x10]; 6934 6935 u8 reserved_at_40[0xc0]; 6936 6937 struct mlx5_ifc_tisc_bits ctx; 6938 }; 6939 6940 struct mlx5_ifc_create_tir_out_bits { 6941 u8 status[0x8]; 6942 u8 icm_address_63_40[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 icm_address_39_32[0x8]; 6947 u8 tirn[0x18]; 6948 6949 u8 icm_address_31_0[0x20]; 6950 }; 6951 6952 struct mlx5_ifc_create_tir_in_bits { 6953 u8 opcode[0x10]; 6954 u8 uid[0x10]; 6955 6956 u8 reserved_at_20[0x10]; 6957 u8 op_mod[0x10]; 6958 6959 u8 reserved_at_40[0xc0]; 6960 6961 struct mlx5_ifc_tirc_bits ctx; 6962 }; 6963 6964 struct mlx5_ifc_create_srq_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_at_8[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_at_40[0x8]; 6971 u8 srqn[0x18]; 6972 6973 u8 reserved_at_60[0x20]; 6974 }; 6975 6976 struct mlx5_ifc_create_srq_in_bits { 6977 u8 opcode[0x10]; 6978 u8 uid[0x10]; 6979 6980 u8 reserved_at_20[0x10]; 6981 u8 op_mod[0x10]; 6982 6983 u8 reserved_at_40[0x40]; 6984 6985 struct mlx5_ifc_srqc_bits srq_context_entry; 6986 6987 u8 reserved_at_280[0x600]; 6988 6989 u8 pas[0][0x40]; 6990 }; 6991 6992 struct mlx5_ifc_create_sq_out_bits { 6993 u8 status[0x8]; 6994 u8 reserved_at_8[0x18]; 6995 6996 u8 syndrome[0x20]; 6997 6998 u8 reserved_at_40[0x8]; 6999 u8 sqn[0x18]; 7000 7001 u8 reserved_at_60[0x20]; 7002 }; 7003 7004 struct mlx5_ifc_create_sq_in_bits { 7005 u8 opcode[0x10]; 7006 u8 uid[0x10]; 7007 7008 u8 reserved_at_20[0x10]; 7009 u8 op_mod[0x10]; 7010 7011 u8 reserved_at_40[0xc0]; 7012 7013 struct mlx5_ifc_sqc_bits ctx; 7014 }; 7015 7016 struct mlx5_ifc_create_scheduling_element_out_bits { 7017 u8 status[0x8]; 7018 u8 reserved_at_8[0x18]; 7019 7020 u8 syndrome[0x20]; 7021 7022 u8 reserved_at_40[0x40]; 7023 7024 u8 scheduling_element_id[0x20]; 7025 7026 u8 reserved_at_a0[0x160]; 7027 }; 7028 7029 struct mlx5_ifc_create_scheduling_element_in_bits { 7030 u8 opcode[0x10]; 7031 u8 reserved_at_10[0x10]; 7032 7033 u8 reserved_at_20[0x10]; 7034 u8 op_mod[0x10]; 7035 7036 u8 scheduling_hierarchy[0x8]; 7037 u8 reserved_at_48[0x18]; 7038 7039 u8 reserved_at_60[0xa0]; 7040 7041 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7042 7043 u8 reserved_at_300[0x100]; 7044 }; 7045 7046 struct mlx5_ifc_create_rqt_out_bits { 7047 u8 status[0x8]; 7048 u8 reserved_at_8[0x18]; 7049 7050 u8 syndrome[0x20]; 7051 7052 u8 reserved_at_40[0x8]; 7053 u8 rqtn[0x18]; 7054 7055 u8 reserved_at_60[0x20]; 7056 }; 7057 7058 struct mlx5_ifc_create_rqt_in_bits { 7059 u8 opcode[0x10]; 7060 u8 uid[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 reserved_at_40[0xc0]; 7066 7067 struct mlx5_ifc_rqtc_bits rqt_context; 7068 }; 7069 7070 struct mlx5_ifc_create_rq_out_bits { 7071 u8 status[0x8]; 7072 u8 reserved_at_8[0x18]; 7073 7074 u8 syndrome[0x20]; 7075 7076 u8 reserved_at_40[0x8]; 7077 u8 rqn[0x18]; 7078 7079 u8 reserved_at_60[0x20]; 7080 }; 7081 7082 struct mlx5_ifc_create_rq_in_bits { 7083 u8 opcode[0x10]; 7084 u8 uid[0x10]; 7085 7086 u8 reserved_at_20[0x10]; 7087 u8 op_mod[0x10]; 7088 7089 u8 reserved_at_40[0xc0]; 7090 7091 struct mlx5_ifc_rqc_bits ctx; 7092 }; 7093 7094 struct mlx5_ifc_create_rmp_out_bits { 7095 u8 status[0x8]; 7096 u8 reserved_at_8[0x18]; 7097 7098 u8 syndrome[0x20]; 7099 7100 u8 reserved_at_40[0x8]; 7101 u8 rmpn[0x18]; 7102 7103 u8 reserved_at_60[0x20]; 7104 }; 7105 7106 struct mlx5_ifc_create_rmp_in_bits { 7107 u8 opcode[0x10]; 7108 u8 uid[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0xc0]; 7114 7115 struct mlx5_ifc_rmpc_bits ctx; 7116 }; 7117 7118 struct mlx5_ifc_create_qp_out_bits { 7119 u8 status[0x8]; 7120 u8 reserved_at_8[0x18]; 7121 7122 u8 syndrome[0x20]; 7123 7124 u8 reserved_at_40[0x8]; 7125 u8 qpn[0x18]; 7126 7127 u8 reserved_at_60[0x20]; 7128 }; 7129 7130 struct mlx5_ifc_create_qp_in_bits { 7131 u8 opcode[0x10]; 7132 u8 uid[0x10]; 7133 7134 u8 reserved_at_20[0x10]; 7135 u8 op_mod[0x10]; 7136 7137 u8 reserved_at_40[0x40]; 7138 7139 u8 opt_param_mask[0x20]; 7140 7141 u8 reserved_at_a0[0x20]; 7142 7143 struct mlx5_ifc_qpc_bits qpc; 7144 7145 u8 reserved_at_800[0x60]; 7146 7147 u8 wq_umem_valid[0x1]; 7148 u8 reserved_at_861[0x1f]; 7149 7150 u8 pas[0][0x40]; 7151 }; 7152 7153 struct mlx5_ifc_create_psv_out_bits { 7154 u8 status[0x8]; 7155 u8 reserved_at_8[0x18]; 7156 7157 u8 syndrome[0x20]; 7158 7159 u8 reserved_at_40[0x40]; 7160 7161 u8 reserved_at_80[0x8]; 7162 u8 psv0_index[0x18]; 7163 7164 u8 reserved_at_a0[0x8]; 7165 u8 psv1_index[0x18]; 7166 7167 u8 reserved_at_c0[0x8]; 7168 u8 psv2_index[0x18]; 7169 7170 u8 reserved_at_e0[0x8]; 7171 u8 psv3_index[0x18]; 7172 }; 7173 7174 struct mlx5_ifc_create_psv_in_bits { 7175 u8 opcode[0x10]; 7176 u8 reserved_at_10[0x10]; 7177 7178 u8 reserved_at_20[0x10]; 7179 u8 op_mod[0x10]; 7180 7181 u8 num_psv[0x4]; 7182 u8 reserved_at_44[0x4]; 7183 u8 pd[0x18]; 7184 7185 u8 reserved_at_60[0x20]; 7186 }; 7187 7188 struct mlx5_ifc_create_mkey_out_bits { 7189 u8 status[0x8]; 7190 u8 reserved_at_8[0x18]; 7191 7192 u8 syndrome[0x20]; 7193 7194 u8 reserved_at_40[0x8]; 7195 u8 mkey_index[0x18]; 7196 7197 u8 reserved_at_60[0x20]; 7198 }; 7199 7200 struct mlx5_ifc_create_mkey_in_bits { 7201 u8 opcode[0x10]; 7202 u8 reserved_at_10[0x10]; 7203 7204 u8 reserved_at_20[0x10]; 7205 u8 op_mod[0x10]; 7206 7207 u8 reserved_at_40[0x20]; 7208 7209 u8 pg_access[0x1]; 7210 u8 mkey_umem_valid[0x1]; 7211 u8 reserved_at_62[0x1e]; 7212 7213 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7214 7215 u8 reserved_at_280[0x80]; 7216 7217 u8 translations_octword_actual_size[0x20]; 7218 7219 u8 reserved_at_320[0x560]; 7220 7221 u8 klm_pas_mtt[0][0x20]; 7222 }; 7223 7224 struct mlx5_ifc_create_flow_table_out_bits { 7225 u8 status[0x8]; 7226 u8 reserved_at_8[0x18]; 7227 7228 u8 syndrome[0x20]; 7229 7230 u8 reserved_at_40[0x8]; 7231 u8 table_id[0x18]; 7232 7233 u8 reserved_at_60[0x20]; 7234 }; 7235 7236 struct mlx5_ifc_flow_table_context_bits { 7237 u8 reformat_en[0x1]; 7238 u8 decap_en[0x1]; 7239 u8 reserved_at_2[0x2]; 7240 u8 table_miss_action[0x4]; 7241 u8 level[0x8]; 7242 u8 reserved_at_10[0x8]; 7243 u8 log_size[0x8]; 7244 7245 u8 reserved_at_20[0x8]; 7246 u8 table_miss_id[0x18]; 7247 7248 u8 reserved_at_40[0x8]; 7249 u8 lag_master_next_table_id[0x18]; 7250 7251 u8 reserved_at_60[0xe0]; 7252 }; 7253 7254 struct mlx5_ifc_create_flow_table_in_bits { 7255 u8 opcode[0x10]; 7256 u8 reserved_at_10[0x10]; 7257 7258 u8 reserved_at_20[0x10]; 7259 u8 op_mod[0x10]; 7260 7261 u8 other_vport[0x1]; 7262 u8 reserved_at_41[0xf]; 7263 u8 vport_number[0x10]; 7264 7265 u8 reserved_at_60[0x20]; 7266 7267 u8 table_type[0x8]; 7268 u8 reserved_at_88[0x18]; 7269 7270 u8 reserved_at_a0[0x20]; 7271 7272 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7273 }; 7274 7275 struct mlx5_ifc_create_flow_group_out_bits { 7276 u8 status[0x8]; 7277 u8 reserved_at_8[0x18]; 7278 7279 u8 syndrome[0x20]; 7280 7281 u8 reserved_at_40[0x8]; 7282 u8 group_id[0x18]; 7283 7284 u8 reserved_at_60[0x20]; 7285 }; 7286 7287 enum { 7288 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7289 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7290 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7291 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7292 }; 7293 7294 struct mlx5_ifc_create_flow_group_in_bits { 7295 u8 opcode[0x10]; 7296 u8 reserved_at_10[0x10]; 7297 7298 u8 reserved_at_20[0x10]; 7299 u8 op_mod[0x10]; 7300 7301 u8 other_vport[0x1]; 7302 u8 reserved_at_41[0xf]; 7303 u8 vport_number[0x10]; 7304 7305 u8 reserved_at_60[0x20]; 7306 7307 u8 table_type[0x8]; 7308 u8 reserved_at_88[0x18]; 7309 7310 u8 reserved_at_a0[0x8]; 7311 u8 table_id[0x18]; 7312 7313 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7314 7315 u8 reserved_at_c1[0x1f]; 7316 7317 u8 start_flow_index[0x20]; 7318 7319 u8 reserved_at_100[0x20]; 7320 7321 u8 end_flow_index[0x20]; 7322 7323 u8 reserved_at_140[0xa0]; 7324 7325 u8 reserved_at_1e0[0x18]; 7326 u8 match_criteria_enable[0x8]; 7327 7328 struct mlx5_ifc_fte_match_param_bits match_criteria; 7329 7330 u8 reserved_at_1200[0xe00]; 7331 }; 7332 7333 struct mlx5_ifc_create_eq_out_bits { 7334 u8 status[0x8]; 7335 u8 reserved_at_8[0x18]; 7336 7337 u8 syndrome[0x20]; 7338 7339 u8 reserved_at_40[0x18]; 7340 u8 eq_number[0x8]; 7341 7342 u8 reserved_at_60[0x20]; 7343 }; 7344 7345 struct mlx5_ifc_create_eq_in_bits { 7346 u8 opcode[0x10]; 7347 u8 uid[0x10]; 7348 7349 u8 reserved_at_20[0x10]; 7350 u8 op_mod[0x10]; 7351 7352 u8 reserved_at_40[0x40]; 7353 7354 struct mlx5_ifc_eqc_bits eq_context_entry; 7355 7356 u8 reserved_at_280[0x40]; 7357 7358 u8 event_bitmask[0x40]; 7359 7360 u8 reserved_at_300[0x580]; 7361 7362 u8 pas[0][0x40]; 7363 }; 7364 7365 struct mlx5_ifc_create_dct_out_bits { 7366 u8 status[0x8]; 7367 u8 reserved_at_8[0x18]; 7368 7369 u8 syndrome[0x20]; 7370 7371 u8 reserved_at_40[0x8]; 7372 u8 dctn[0x18]; 7373 7374 u8 reserved_at_60[0x20]; 7375 }; 7376 7377 struct mlx5_ifc_create_dct_in_bits { 7378 u8 opcode[0x10]; 7379 u8 uid[0x10]; 7380 7381 u8 reserved_at_20[0x10]; 7382 u8 op_mod[0x10]; 7383 7384 u8 reserved_at_40[0x40]; 7385 7386 struct mlx5_ifc_dctc_bits dct_context_entry; 7387 7388 u8 reserved_at_280[0x180]; 7389 }; 7390 7391 struct mlx5_ifc_create_cq_out_bits { 7392 u8 status[0x8]; 7393 u8 reserved_at_8[0x18]; 7394 7395 u8 syndrome[0x20]; 7396 7397 u8 reserved_at_40[0x8]; 7398 u8 cqn[0x18]; 7399 7400 u8 reserved_at_60[0x20]; 7401 }; 7402 7403 struct mlx5_ifc_create_cq_in_bits { 7404 u8 opcode[0x10]; 7405 u8 uid[0x10]; 7406 7407 u8 reserved_at_20[0x10]; 7408 u8 op_mod[0x10]; 7409 7410 u8 reserved_at_40[0x40]; 7411 7412 struct mlx5_ifc_cqc_bits cq_context; 7413 7414 u8 reserved_at_280[0x60]; 7415 7416 u8 cq_umem_valid[0x1]; 7417 u8 reserved_at_2e1[0x59f]; 7418 7419 u8 pas[0][0x40]; 7420 }; 7421 7422 struct mlx5_ifc_config_int_moderation_out_bits { 7423 u8 status[0x8]; 7424 u8 reserved_at_8[0x18]; 7425 7426 u8 syndrome[0x20]; 7427 7428 u8 reserved_at_40[0x4]; 7429 u8 min_delay[0xc]; 7430 u8 int_vector[0x10]; 7431 7432 u8 reserved_at_60[0x20]; 7433 }; 7434 7435 enum { 7436 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7437 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7438 }; 7439 7440 struct mlx5_ifc_config_int_moderation_in_bits { 7441 u8 opcode[0x10]; 7442 u8 reserved_at_10[0x10]; 7443 7444 u8 reserved_at_20[0x10]; 7445 u8 op_mod[0x10]; 7446 7447 u8 reserved_at_40[0x4]; 7448 u8 min_delay[0xc]; 7449 u8 int_vector[0x10]; 7450 7451 u8 reserved_at_60[0x20]; 7452 }; 7453 7454 struct mlx5_ifc_attach_to_mcg_out_bits { 7455 u8 status[0x8]; 7456 u8 reserved_at_8[0x18]; 7457 7458 u8 syndrome[0x20]; 7459 7460 u8 reserved_at_40[0x40]; 7461 }; 7462 7463 struct mlx5_ifc_attach_to_mcg_in_bits { 7464 u8 opcode[0x10]; 7465 u8 uid[0x10]; 7466 7467 u8 reserved_at_20[0x10]; 7468 u8 op_mod[0x10]; 7469 7470 u8 reserved_at_40[0x8]; 7471 u8 qpn[0x18]; 7472 7473 u8 reserved_at_60[0x20]; 7474 7475 u8 multicast_gid[16][0x8]; 7476 }; 7477 7478 struct mlx5_ifc_arm_xrq_out_bits { 7479 u8 status[0x8]; 7480 u8 reserved_at_8[0x18]; 7481 7482 u8 syndrome[0x20]; 7483 7484 u8 reserved_at_40[0x40]; 7485 }; 7486 7487 struct mlx5_ifc_arm_xrq_in_bits { 7488 u8 opcode[0x10]; 7489 u8 reserved_at_10[0x10]; 7490 7491 u8 reserved_at_20[0x10]; 7492 u8 op_mod[0x10]; 7493 7494 u8 reserved_at_40[0x8]; 7495 u8 xrqn[0x18]; 7496 7497 u8 reserved_at_60[0x10]; 7498 u8 lwm[0x10]; 7499 }; 7500 7501 struct mlx5_ifc_arm_xrc_srq_out_bits { 7502 u8 status[0x8]; 7503 u8 reserved_at_8[0x18]; 7504 7505 u8 syndrome[0x20]; 7506 7507 u8 reserved_at_40[0x40]; 7508 }; 7509 7510 enum { 7511 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7512 }; 7513 7514 struct mlx5_ifc_arm_xrc_srq_in_bits { 7515 u8 opcode[0x10]; 7516 u8 uid[0x10]; 7517 7518 u8 reserved_at_20[0x10]; 7519 u8 op_mod[0x10]; 7520 7521 u8 reserved_at_40[0x8]; 7522 u8 xrc_srqn[0x18]; 7523 7524 u8 reserved_at_60[0x10]; 7525 u8 lwm[0x10]; 7526 }; 7527 7528 struct mlx5_ifc_arm_rq_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x40]; 7535 }; 7536 7537 enum { 7538 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7539 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7540 }; 7541 7542 struct mlx5_ifc_arm_rq_in_bits { 7543 u8 opcode[0x10]; 7544 u8 uid[0x10]; 7545 7546 u8 reserved_at_20[0x10]; 7547 u8 op_mod[0x10]; 7548 7549 u8 reserved_at_40[0x8]; 7550 u8 srq_number[0x18]; 7551 7552 u8 reserved_at_60[0x10]; 7553 u8 lwm[0x10]; 7554 }; 7555 7556 struct mlx5_ifc_arm_dct_out_bits { 7557 u8 status[0x8]; 7558 u8 reserved_at_8[0x18]; 7559 7560 u8 syndrome[0x20]; 7561 7562 u8 reserved_at_40[0x40]; 7563 }; 7564 7565 struct mlx5_ifc_arm_dct_in_bits { 7566 u8 opcode[0x10]; 7567 u8 reserved_at_10[0x10]; 7568 7569 u8 reserved_at_20[0x10]; 7570 u8 op_mod[0x10]; 7571 7572 u8 reserved_at_40[0x8]; 7573 u8 dct_number[0x18]; 7574 7575 u8 reserved_at_60[0x20]; 7576 }; 7577 7578 struct mlx5_ifc_alloc_xrcd_out_bits { 7579 u8 status[0x8]; 7580 u8 reserved_at_8[0x18]; 7581 7582 u8 syndrome[0x20]; 7583 7584 u8 reserved_at_40[0x8]; 7585 u8 xrcd[0x18]; 7586 7587 u8 reserved_at_60[0x20]; 7588 }; 7589 7590 struct mlx5_ifc_alloc_xrcd_in_bits { 7591 u8 opcode[0x10]; 7592 u8 uid[0x10]; 7593 7594 u8 reserved_at_20[0x10]; 7595 u8 op_mod[0x10]; 7596 7597 u8 reserved_at_40[0x40]; 7598 }; 7599 7600 struct mlx5_ifc_alloc_uar_out_bits { 7601 u8 status[0x8]; 7602 u8 reserved_at_8[0x18]; 7603 7604 u8 syndrome[0x20]; 7605 7606 u8 reserved_at_40[0x8]; 7607 u8 uar[0x18]; 7608 7609 u8 reserved_at_60[0x20]; 7610 }; 7611 7612 struct mlx5_ifc_alloc_uar_in_bits { 7613 u8 opcode[0x10]; 7614 u8 reserved_at_10[0x10]; 7615 7616 u8 reserved_at_20[0x10]; 7617 u8 op_mod[0x10]; 7618 7619 u8 reserved_at_40[0x40]; 7620 }; 7621 7622 struct mlx5_ifc_alloc_transport_domain_out_bits { 7623 u8 status[0x8]; 7624 u8 reserved_at_8[0x18]; 7625 7626 u8 syndrome[0x20]; 7627 7628 u8 reserved_at_40[0x8]; 7629 u8 transport_domain[0x18]; 7630 7631 u8 reserved_at_60[0x20]; 7632 }; 7633 7634 struct mlx5_ifc_alloc_transport_domain_in_bits { 7635 u8 opcode[0x10]; 7636 u8 uid[0x10]; 7637 7638 u8 reserved_at_20[0x10]; 7639 u8 op_mod[0x10]; 7640 7641 u8 reserved_at_40[0x40]; 7642 }; 7643 7644 struct mlx5_ifc_alloc_q_counter_out_bits { 7645 u8 status[0x8]; 7646 u8 reserved_at_8[0x18]; 7647 7648 u8 syndrome[0x20]; 7649 7650 u8 reserved_at_40[0x18]; 7651 u8 counter_set_id[0x8]; 7652 7653 u8 reserved_at_60[0x20]; 7654 }; 7655 7656 struct mlx5_ifc_alloc_q_counter_in_bits { 7657 u8 opcode[0x10]; 7658 u8 uid[0x10]; 7659 7660 u8 reserved_at_20[0x10]; 7661 u8 op_mod[0x10]; 7662 7663 u8 reserved_at_40[0x40]; 7664 }; 7665 7666 struct mlx5_ifc_alloc_pd_out_bits { 7667 u8 status[0x8]; 7668 u8 reserved_at_8[0x18]; 7669 7670 u8 syndrome[0x20]; 7671 7672 u8 reserved_at_40[0x8]; 7673 u8 pd[0x18]; 7674 7675 u8 reserved_at_60[0x20]; 7676 }; 7677 7678 struct mlx5_ifc_alloc_pd_in_bits { 7679 u8 opcode[0x10]; 7680 u8 uid[0x10]; 7681 7682 u8 reserved_at_20[0x10]; 7683 u8 op_mod[0x10]; 7684 7685 u8 reserved_at_40[0x40]; 7686 }; 7687 7688 struct mlx5_ifc_alloc_flow_counter_out_bits { 7689 u8 status[0x8]; 7690 u8 reserved_at_8[0x18]; 7691 7692 u8 syndrome[0x20]; 7693 7694 u8 flow_counter_id[0x20]; 7695 7696 u8 reserved_at_60[0x20]; 7697 }; 7698 7699 struct mlx5_ifc_alloc_flow_counter_in_bits { 7700 u8 opcode[0x10]; 7701 u8 reserved_at_10[0x10]; 7702 7703 u8 reserved_at_20[0x10]; 7704 u8 op_mod[0x10]; 7705 7706 u8 reserved_at_40[0x40]; 7707 }; 7708 7709 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7710 u8 status[0x8]; 7711 u8 reserved_at_8[0x18]; 7712 7713 u8 syndrome[0x20]; 7714 7715 u8 reserved_at_40[0x40]; 7716 }; 7717 7718 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7719 u8 opcode[0x10]; 7720 u8 reserved_at_10[0x10]; 7721 7722 u8 reserved_at_20[0x10]; 7723 u8 op_mod[0x10]; 7724 7725 u8 reserved_at_40[0x20]; 7726 7727 u8 reserved_at_60[0x10]; 7728 u8 vxlan_udp_port[0x10]; 7729 }; 7730 7731 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7732 u8 status[0x8]; 7733 u8 reserved_at_8[0x18]; 7734 7735 u8 syndrome[0x20]; 7736 7737 u8 reserved_at_40[0x40]; 7738 }; 7739 7740 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7741 u8 opcode[0x10]; 7742 u8 reserved_at_10[0x10]; 7743 7744 u8 reserved_at_20[0x10]; 7745 u8 op_mod[0x10]; 7746 7747 u8 reserved_at_40[0x10]; 7748 u8 rate_limit_index[0x10]; 7749 7750 u8 reserved_at_60[0x20]; 7751 7752 u8 rate_limit[0x20]; 7753 7754 u8 burst_upper_bound[0x20]; 7755 7756 u8 reserved_at_c0[0x10]; 7757 u8 typical_packet_size[0x10]; 7758 7759 u8 reserved_at_e0[0x120]; 7760 }; 7761 7762 struct mlx5_ifc_access_register_out_bits { 7763 u8 status[0x8]; 7764 u8 reserved_at_8[0x18]; 7765 7766 u8 syndrome[0x20]; 7767 7768 u8 reserved_at_40[0x40]; 7769 7770 u8 register_data[0][0x20]; 7771 }; 7772 7773 enum { 7774 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7775 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7776 }; 7777 7778 struct mlx5_ifc_access_register_in_bits { 7779 u8 opcode[0x10]; 7780 u8 reserved_at_10[0x10]; 7781 7782 u8 reserved_at_20[0x10]; 7783 u8 op_mod[0x10]; 7784 7785 u8 reserved_at_40[0x10]; 7786 u8 register_id[0x10]; 7787 7788 u8 argument[0x20]; 7789 7790 u8 register_data[0][0x20]; 7791 }; 7792 7793 struct mlx5_ifc_sltp_reg_bits { 7794 u8 status[0x4]; 7795 u8 version[0x4]; 7796 u8 local_port[0x8]; 7797 u8 pnat[0x2]; 7798 u8 reserved_at_12[0x2]; 7799 u8 lane[0x4]; 7800 u8 reserved_at_18[0x8]; 7801 7802 u8 reserved_at_20[0x20]; 7803 7804 u8 reserved_at_40[0x7]; 7805 u8 polarity[0x1]; 7806 u8 ob_tap0[0x8]; 7807 u8 ob_tap1[0x8]; 7808 u8 ob_tap2[0x8]; 7809 7810 u8 reserved_at_60[0xc]; 7811 u8 ob_preemp_mode[0x4]; 7812 u8 ob_reg[0x8]; 7813 u8 ob_bias[0x8]; 7814 7815 u8 reserved_at_80[0x20]; 7816 }; 7817 7818 struct mlx5_ifc_slrg_reg_bits { 7819 u8 status[0x4]; 7820 u8 version[0x4]; 7821 u8 local_port[0x8]; 7822 u8 pnat[0x2]; 7823 u8 reserved_at_12[0x2]; 7824 u8 lane[0x4]; 7825 u8 reserved_at_18[0x8]; 7826 7827 u8 time_to_link_up[0x10]; 7828 u8 reserved_at_30[0xc]; 7829 u8 grade_lane_speed[0x4]; 7830 7831 u8 grade_version[0x8]; 7832 u8 grade[0x18]; 7833 7834 u8 reserved_at_60[0x4]; 7835 u8 height_grade_type[0x4]; 7836 u8 height_grade[0x18]; 7837 7838 u8 height_dz[0x10]; 7839 u8 height_dv[0x10]; 7840 7841 u8 reserved_at_a0[0x10]; 7842 u8 height_sigma[0x10]; 7843 7844 u8 reserved_at_c0[0x20]; 7845 7846 u8 reserved_at_e0[0x4]; 7847 u8 phase_grade_type[0x4]; 7848 u8 phase_grade[0x18]; 7849 7850 u8 reserved_at_100[0x8]; 7851 u8 phase_eo_pos[0x8]; 7852 u8 reserved_at_110[0x8]; 7853 u8 phase_eo_neg[0x8]; 7854 7855 u8 ffe_set_tested[0x10]; 7856 u8 test_errors_per_lane[0x10]; 7857 }; 7858 7859 struct mlx5_ifc_pvlc_reg_bits { 7860 u8 reserved_at_0[0x8]; 7861 u8 local_port[0x8]; 7862 u8 reserved_at_10[0x10]; 7863 7864 u8 reserved_at_20[0x1c]; 7865 u8 vl_hw_cap[0x4]; 7866 7867 u8 reserved_at_40[0x1c]; 7868 u8 vl_admin[0x4]; 7869 7870 u8 reserved_at_60[0x1c]; 7871 u8 vl_operational[0x4]; 7872 }; 7873 7874 struct mlx5_ifc_pude_reg_bits { 7875 u8 swid[0x8]; 7876 u8 local_port[0x8]; 7877 u8 reserved_at_10[0x4]; 7878 u8 admin_status[0x4]; 7879 u8 reserved_at_18[0x4]; 7880 u8 oper_status[0x4]; 7881 7882 u8 reserved_at_20[0x60]; 7883 }; 7884 7885 struct mlx5_ifc_ptys_reg_bits { 7886 u8 reserved_at_0[0x1]; 7887 u8 an_disable_admin[0x1]; 7888 u8 an_disable_cap[0x1]; 7889 u8 reserved_at_3[0x5]; 7890 u8 local_port[0x8]; 7891 u8 reserved_at_10[0xd]; 7892 u8 proto_mask[0x3]; 7893 7894 u8 an_status[0x4]; 7895 u8 reserved_at_24[0x1c]; 7896 7897 u8 ext_eth_proto_capability[0x20]; 7898 7899 u8 eth_proto_capability[0x20]; 7900 7901 u8 ib_link_width_capability[0x10]; 7902 u8 ib_proto_capability[0x10]; 7903 7904 u8 ext_eth_proto_admin[0x20]; 7905 7906 u8 eth_proto_admin[0x20]; 7907 7908 u8 ib_link_width_admin[0x10]; 7909 u8 ib_proto_admin[0x10]; 7910 7911 u8 ext_eth_proto_oper[0x20]; 7912 7913 u8 eth_proto_oper[0x20]; 7914 7915 u8 ib_link_width_oper[0x10]; 7916 u8 ib_proto_oper[0x10]; 7917 7918 u8 reserved_at_160[0x1c]; 7919 u8 connector_type[0x4]; 7920 7921 u8 eth_proto_lp_advertise[0x20]; 7922 7923 u8 reserved_at_1a0[0x60]; 7924 }; 7925 7926 struct mlx5_ifc_mlcr_reg_bits { 7927 u8 reserved_at_0[0x8]; 7928 u8 local_port[0x8]; 7929 u8 reserved_at_10[0x20]; 7930 7931 u8 beacon_duration[0x10]; 7932 u8 reserved_at_40[0x10]; 7933 7934 u8 beacon_remain[0x10]; 7935 }; 7936 7937 struct mlx5_ifc_ptas_reg_bits { 7938 u8 reserved_at_0[0x20]; 7939 7940 u8 algorithm_options[0x10]; 7941 u8 reserved_at_30[0x4]; 7942 u8 repetitions_mode[0x4]; 7943 u8 num_of_repetitions[0x8]; 7944 7945 u8 grade_version[0x8]; 7946 u8 height_grade_type[0x4]; 7947 u8 phase_grade_type[0x4]; 7948 u8 height_grade_weight[0x8]; 7949 u8 phase_grade_weight[0x8]; 7950 7951 u8 gisim_measure_bits[0x10]; 7952 u8 adaptive_tap_measure_bits[0x10]; 7953 7954 u8 ber_bath_high_error_threshold[0x10]; 7955 u8 ber_bath_mid_error_threshold[0x10]; 7956 7957 u8 ber_bath_low_error_threshold[0x10]; 7958 u8 one_ratio_high_threshold[0x10]; 7959 7960 u8 one_ratio_high_mid_threshold[0x10]; 7961 u8 one_ratio_low_mid_threshold[0x10]; 7962 7963 u8 one_ratio_low_threshold[0x10]; 7964 u8 ndeo_error_threshold[0x10]; 7965 7966 u8 mixer_offset_step_size[0x10]; 7967 u8 reserved_at_110[0x8]; 7968 u8 mix90_phase_for_voltage_bath[0x8]; 7969 7970 u8 mixer_offset_start[0x10]; 7971 u8 mixer_offset_end[0x10]; 7972 7973 u8 reserved_at_140[0x15]; 7974 u8 ber_test_time[0xb]; 7975 }; 7976 7977 struct mlx5_ifc_pspa_reg_bits { 7978 u8 swid[0x8]; 7979 u8 local_port[0x8]; 7980 u8 sub_port[0x8]; 7981 u8 reserved_at_18[0x8]; 7982 7983 u8 reserved_at_20[0x20]; 7984 }; 7985 7986 struct mlx5_ifc_pqdr_reg_bits { 7987 u8 reserved_at_0[0x8]; 7988 u8 local_port[0x8]; 7989 u8 reserved_at_10[0x5]; 7990 u8 prio[0x3]; 7991 u8 reserved_at_18[0x6]; 7992 u8 mode[0x2]; 7993 7994 u8 reserved_at_20[0x20]; 7995 7996 u8 reserved_at_40[0x10]; 7997 u8 min_threshold[0x10]; 7998 7999 u8 reserved_at_60[0x10]; 8000 u8 max_threshold[0x10]; 8001 8002 u8 reserved_at_80[0x10]; 8003 u8 mark_probability_denominator[0x10]; 8004 8005 u8 reserved_at_a0[0x60]; 8006 }; 8007 8008 struct mlx5_ifc_ppsc_reg_bits { 8009 u8 reserved_at_0[0x8]; 8010 u8 local_port[0x8]; 8011 u8 reserved_at_10[0x10]; 8012 8013 u8 reserved_at_20[0x60]; 8014 8015 u8 reserved_at_80[0x1c]; 8016 u8 wrps_admin[0x4]; 8017 8018 u8 reserved_at_a0[0x1c]; 8019 u8 wrps_status[0x4]; 8020 8021 u8 reserved_at_c0[0x8]; 8022 u8 up_threshold[0x8]; 8023 u8 reserved_at_d0[0x8]; 8024 u8 down_threshold[0x8]; 8025 8026 u8 reserved_at_e0[0x20]; 8027 8028 u8 reserved_at_100[0x1c]; 8029 u8 srps_admin[0x4]; 8030 8031 u8 reserved_at_120[0x1c]; 8032 u8 srps_status[0x4]; 8033 8034 u8 reserved_at_140[0x40]; 8035 }; 8036 8037 struct mlx5_ifc_pplr_reg_bits { 8038 u8 reserved_at_0[0x8]; 8039 u8 local_port[0x8]; 8040 u8 reserved_at_10[0x10]; 8041 8042 u8 reserved_at_20[0x8]; 8043 u8 lb_cap[0x8]; 8044 u8 reserved_at_30[0x8]; 8045 u8 lb_en[0x8]; 8046 }; 8047 8048 struct mlx5_ifc_pplm_reg_bits { 8049 u8 reserved_at_0[0x8]; 8050 u8 local_port[0x8]; 8051 u8 reserved_at_10[0x10]; 8052 8053 u8 reserved_at_20[0x20]; 8054 8055 u8 port_profile_mode[0x8]; 8056 u8 static_port_profile[0x8]; 8057 u8 active_port_profile[0x8]; 8058 u8 reserved_at_58[0x8]; 8059 8060 u8 retransmission_active[0x8]; 8061 u8 fec_mode_active[0x18]; 8062 8063 u8 rs_fec_correction_bypass_cap[0x4]; 8064 u8 reserved_at_84[0x8]; 8065 u8 fec_override_cap_56g[0x4]; 8066 u8 fec_override_cap_100g[0x4]; 8067 u8 fec_override_cap_50g[0x4]; 8068 u8 fec_override_cap_25g[0x4]; 8069 u8 fec_override_cap_10g_40g[0x4]; 8070 8071 u8 rs_fec_correction_bypass_admin[0x4]; 8072 u8 reserved_at_a4[0x8]; 8073 u8 fec_override_admin_56g[0x4]; 8074 u8 fec_override_admin_100g[0x4]; 8075 u8 fec_override_admin_50g[0x4]; 8076 u8 fec_override_admin_25g[0x4]; 8077 u8 fec_override_admin_10g_40g[0x4]; 8078 }; 8079 8080 struct mlx5_ifc_ppcnt_reg_bits { 8081 u8 swid[0x8]; 8082 u8 local_port[0x8]; 8083 u8 pnat[0x2]; 8084 u8 reserved_at_12[0x8]; 8085 u8 grp[0x6]; 8086 8087 u8 clr[0x1]; 8088 u8 reserved_at_21[0x1c]; 8089 u8 prio_tc[0x3]; 8090 8091 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8092 }; 8093 8094 struct mlx5_ifc_mpein_reg_bits { 8095 u8 reserved_at_0[0x2]; 8096 u8 depth[0x6]; 8097 u8 pcie_index[0x8]; 8098 u8 node[0x8]; 8099 u8 reserved_at_18[0x8]; 8100 8101 u8 capability_mask[0x20]; 8102 8103 u8 reserved_at_40[0x8]; 8104 u8 link_width_enabled[0x8]; 8105 u8 link_speed_enabled[0x10]; 8106 8107 u8 lane0_physical_position[0x8]; 8108 u8 link_width_active[0x8]; 8109 u8 link_speed_active[0x10]; 8110 8111 u8 num_of_pfs[0x10]; 8112 u8 num_of_vfs[0x10]; 8113 8114 u8 bdf0[0x10]; 8115 u8 reserved_at_b0[0x10]; 8116 8117 u8 max_read_request_size[0x4]; 8118 u8 max_payload_size[0x4]; 8119 u8 reserved_at_c8[0x5]; 8120 u8 pwr_status[0x3]; 8121 u8 port_type[0x4]; 8122 u8 reserved_at_d4[0xb]; 8123 u8 lane_reversal[0x1]; 8124 8125 u8 reserved_at_e0[0x14]; 8126 u8 pci_power[0xc]; 8127 8128 u8 reserved_at_100[0x20]; 8129 8130 u8 device_status[0x10]; 8131 u8 port_state[0x8]; 8132 u8 reserved_at_138[0x8]; 8133 8134 u8 reserved_at_140[0x10]; 8135 u8 receiver_detect_result[0x10]; 8136 8137 u8 reserved_at_160[0x20]; 8138 }; 8139 8140 struct mlx5_ifc_mpcnt_reg_bits { 8141 u8 reserved_at_0[0x8]; 8142 u8 pcie_index[0x8]; 8143 u8 reserved_at_10[0xa]; 8144 u8 grp[0x6]; 8145 8146 u8 clr[0x1]; 8147 u8 reserved_at_21[0x1f]; 8148 8149 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8150 }; 8151 8152 struct mlx5_ifc_ppad_reg_bits { 8153 u8 reserved_at_0[0x3]; 8154 u8 single_mac[0x1]; 8155 u8 reserved_at_4[0x4]; 8156 u8 local_port[0x8]; 8157 u8 mac_47_32[0x10]; 8158 8159 u8 mac_31_0[0x20]; 8160 8161 u8 reserved_at_40[0x40]; 8162 }; 8163 8164 struct mlx5_ifc_pmtu_reg_bits { 8165 u8 reserved_at_0[0x8]; 8166 u8 local_port[0x8]; 8167 u8 reserved_at_10[0x10]; 8168 8169 u8 max_mtu[0x10]; 8170 u8 reserved_at_30[0x10]; 8171 8172 u8 admin_mtu[0x10]; 8173 u8 reserved_at_50[0x10]; 8174 8175 u8 oper_mtu[0x10]; 8176 u8 reserved_at_70[0x10]; 8177 }; 8178 8179 struct mlx5_ifc_pmpr_reg_bits { 8180 u8 reserved_at_0[0x8]; 8181 u8 module[0x8]; 8182 u8 reserved_at_10[0x10]; 8183 8184 u8 reserved_at_20[0x18]; 8185 u8 attenuation_5g[0x8]; 8186 8187 u8 reserved_at_40[0x18]; 8188 u8 attenuation_7g[0x8]; 8189 8190 u8 reserved_at_60[0x18]; 8191 u8 attenuation_12g[0x8]; 8192 }; 8193 8194 struct mlx5_ifc_pmpe_reg_bits { 8195 u8 reserved_at_0[0x8]; 8196 u8 module[0x8]; 8197 u8 reserved_at_10[0xc]; 8198 u8 module_status[0x4]; 8199 8200 u8 reserved_at_20[0x60]; 8201 }; 8202 8203 struct mlx5_ifc_pmpc_reg_bits { 8204 u8 module_state_updated[32][0x8]; 8205 }; 8206 8207 struct mlx5_ifc_pmlpn_reg_bits { 8208 u8 reserved_at_0[0x4]; 8209 u8 mlpn_status[0x4]; 8210 u8 local_port[0x8]; 8211 u8 reserved_at_10[0x10]; 8212 8213 u8 e[0x1]; 8214 u8 reserved_at_21[0x1f]; 8215 }; 8216 8217 struct mlx5_ifc_pmlp_reg_bits { 8218 u8 rxtx[0x1]; 8219 u8 reserved_at_1[0x7]; 8220 u8 local_port[0x8]; 8221 u8 reserved_at_10[0x8]; 8222 u8 width[0x8]; 8223 8224 u8 lane0_module_mapping[0x20]; 8225 8226 u8 lane1_module_mapping[0x20]; 8227 8228 u8 lane2_module_mapping[0x20]; 8229 8230 u8 lane3_module_mapping[0x20]; 8231 8232 u8 reserved_at_a0[0x160]; 8233 }; 8234 8235 struct mlx5_ifc_pmaos_reg_bits { 8236 u8 reserved_at_0[0x8]; 8237 u8 module[0x8]; 8238 u8 reserved_at_10[0x4]; 8239 u8 admin_status[0x4]; 8240 u8 reserved_at_18[0x4]; 8241 u8 oper_status[0x4]; 8242 8243 u8 ase[0x1]; 8244 u8 ee[0x1]; 8245 u8 reserved_at_22[0x1c]; 8246 u8 e[0x2]; 8247 8248 u8 reserved_at_40[0x40]; 8249 }; 8250 8251 struct mlx5_ifc_plpc_reg_bits { 8252 u8 reserved_at_0[0x4]; 8253 u8 profile_id[0xc]; 8254 u8 reserved_at_10[0x4]; 8255 u8 proto_mask[0x4]; 8256 u8 reserved_at_18[0x8]; 8257 8258 u8 reserved_at_20[0x10]; 8259 u8 lane_speed[0x10]; 8260 8261 u8 reserved_at_40[0x17]; 8262 u8 lpbf[0x1]; 8263 u8 fec_mode_policy[0x8]; 8264 8265 u8 retransmission_capability[0x8]; 8266 u8 fec_mode_capability[0x18]; 8267 8268 u8 retransmission_support_admin[0x8]; 8269 u8 fec_mode_support_admin[0x18]; 8270 8271 u8 retransmission_request_admin[0x8]; 8272 u8 fec_mode_request_admin[0x18]; 8273 8274 u8 reserved_at_c0[0x80]; 8275 }; 8276 8277 struct mlx5_ifc_plib_reg_bits { 8278 u8 reserved_at_0[0x8]; 8279 u8 local_port[0x8]; 8280 u8 reserved_at_10[0x8]; 8281 u8 ib_port[0x8]; 8282 8283 u8 reserved_at_20[0x60]; 8284 }; 8285 8286 struct mlx5_ifc_plbf_reg_bits { 8287 u8 reserved_at_0[0x8]; 8288 u8 local_port[0x8]; 8289 u8 reserved_at_10[0xd]; 8290 u8 lbf_mode[0x3]; 8291 8292 u8 reserved_at_20[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_pipg_reg_bits { 8296 u8 reserved_at_0[0x8]; 8297 u8 local_port[0x8]; 8298 u8 reserved_at_10[0x10]; 8299 8300 u8 dic[0x1]; 8301 u8 reserved_at_21[0x19]; 8302 u8 ipg[0x4]; 8303 u8 reserved_at_3e[0x2]; 8304 }; 8305 8306 struct mlx5_ifc_pifr_reg_bits { 8307 u8 reserved_at_0[0x8]; 8308 u8 local_port[0x8]; 8309 u8 reserved_at_10[0x10]; 8310 8311 u8 reserved_at_20[0xe0]; 8312 8313 u8 port_filter[8][0x20]; 8314 8315 u8 port_filter_update_en[8][0x20]; 8316 }; 8317 8318 struct mlx5_ifc_pfcc_reg_bits { 8319 u8 reserved_at_0[0x8]; 8320 u8 local_port[0x8]; 8321 u8 reserved_at_10[0xb]; 8322 u8 ppan_mask_n[0x1]; 8323 u8 minor_stall_mask[0x1]; 8324 u8 critical_stall_mask[0x1]; 8325 u8 reserved_at_1e[0x2]; 8326 8327 u8 ppan[0x4]; 8328 u8 reserved_at_24[0x4]; 8329 u8 prio_mask_tx[0x8]; 8330 u8 reserved_at_30[0x8]; 8331 u8 prio_mask_rx[0x8]; 8332 8333 u8 pptx[0x1]; 8334 u8 aptx[0x1]; 8335 u8 pptx_mask_n[0x1]; 8336 u8 reserved_at_43[0x5]; 8337 u8 pfctx[0x8]; 8338 u8 reserved_at_50[0x10]; 8339 8340 u8 pprx[0x1]; 8341 u8 aprx[0x1]; 8342 u8 pprx_mask_n[0x1]; 8343 u8 reserved_at_63[0x5]; 8344 u8 pfcrx[0x8]; 8345 u8 reserved_at_70[0x10]; 8346 8347 u8 device_stall_minor_watermark[0x10]; 8348 u8 device_stall_critical_watermark[0x10]; 8349 8350 u8 reserved_at_a0[0x60]; 8351 }; 8352 8353 struct mlx5_ifc_pelc_reg_bits { 8354 u8 op[0x4]; 8355 u8 reserved_at_4[0x4]; 8356 u8 local_port[0x8]; 8357 u8 reserved_at_10[0x10]; 8358 8359 u8 op_admin[0x8]; 8360 u8 op_capability[0x8]; 8361 u8 op_request[0x8]; 8362 u8 op_active[0x8]; 8363 8364 u8 admin[0x40]; 8365 8366 u8 capability[0x40]; 8367 8368 u8 request[0x40]; 8369 8370 u8 active[0x40]; 8371 8372 u8 reserved_at_140[0x80]; 8373 }; 8374 8375 struct mlx5_ifc_peir_reg_bits { 8376 u8 reserved_at_0[0x8]; 8377 u8 local_port[0x8]; 8378 u8 reserved_at_10[0x10]; 8379 8380 u8 reserved_at_20[0xc]; 8381 u8 error_count[0x4]; 8382 u8 reserved_at_30[0x10]; 8383 8384 u8 reserved_at_40[0xc]; 8385 u8 lane[0x4]; 8386 u8 reserved_at_50[0x8]; 8387 u8 error_type[0x8]; 8388 }; 8389 8390 struct mlx5_ifc_mpegc_reg_bits { 8391 u8 reserved_at_0[0x30]; 8392 u8 field_select[0x10]; 8393 8394 u8 tx_overflow_sense[0x1]; 8395 u8 mark_cqe[0x1]; 8396 u8 mark_cnp[0x1]; 8397 u8 reserved_at_43[0x1b]; 8398 u8 tx_lossy_overflow_oper[0x2]; 8399 8400 u8 reserved_at_60[0x100]; 8401 }; 8402 8403 struct mlx5_ifc_pcam_enhanced_features_bits { 8404 u8 reserved_at_0[0x6d]; 8405 u8 rx_icrc_encapsulated_counter[0x1]; 8406 u8 reserved_at_6e[0x4]; 8407 u8 ptys_extended_ethernet[0x1]; 8408 u8 reserved_at_73[0x3]; 8409 u8 pfcc_mask[0x1]; 8410 u8 reserved_at_77[0x3]; 8411 u8 per_lane_error_counters[0x1]; 8412 u8 rx_buffer_fullness_counters[0x1]; 8413 u8 ptys_connector_type[0x1]; 8414 u8 reserved_at_7d[0x1]; 8415 u8 ppcnt_discard_group[0x1]; 8416 u8 ppcnt_statistical_group[0x1]; 8417 }; 8418 8419 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8420 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8421 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8422 8423 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8424 u8 pplm[0x1]; 8425 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8426 8427 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8428 u8 pbmc[0x1]; 8429 u8 pptb[0x1]; 8430 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8431 u8 ppcnt[0x1]; 8432 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8433 }; 8434 8435 struct mlx5_ifc_pcam_reg_bits { 8436 u8 reserved_at_0[0x8]; 8437 u8 feature_group[0x8]; 8438 u8 reserved_at_10[0x8]; 8439 u8 access_reg_group[0x8]; 8440 8441 u8 reserved_at_20[0x20]; 8442 8443 union { 8444 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8445 u8 reserved_at_0[0x80]; 8446 } port_access_reg_cap_mask; 8447 8448 u8 reserved_at_c0[0x80]; 8449 8450 union { 8451 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8452 u8 reserved_at_0[0x80]; 8453 } feature_cap_mask; 8454 8455 u8 reserved_at_1c0[0xc0]; 8456 }; 8457 8458 struct mlx5_ifc_mcam_enhanced_features_bits { 8459 u8 reserved_at_0[0x6e]; 8460 u8 pci_status_and_power[0x1]; 8461 u8 reserved_at_6f[0x5]; 8462 u8 mark_tx_action_cnp[0x1]; 8463 u8 mark_tx_action_cqe[0x1]; 8464 u8 dynamic_tx_overflow[0x1]; 8465 u8 reserved_at_77[0x4]; 8466 u8 pcie_outbound_stalled[0x1]; 8467 u8 tx_overflow_buffer_pkt[0x1]; 8468 u8 mtpps_enh_out_per_adj[0x1]; 8469 u8 mtpps_fs[0x1]; 8470 u8 pcie_performance_group[0x1]; 8471 }; 8472 8473 struct mlx5_ifc_mcam_access_reg_bits { 8474 u8 reserved_at_0[0x1c]; 8475 u8 mcda[0x1]; 8476 u8 mcc[0x1]; 8477 u8 mcqi[0x1]; 8478 u8 reserved_at_1f[0x1]; 8479 8480 u8 regs_95_to_87[0x9]; 8481 u8 mpegc[0x1]; 8482 u8 regs_85_to_68[0x12]; 8483 u8 tracer_registers[0x4]; 8484 8485 u8 regs_63_to_32[0x20]; 8486 u8 regs_31_to_0[0x20]; 8487 }; 8488 8489 struct mlx5_ifc_mcam_reg_bits { 8490 u8 reserved_at_0[0x8]; 8491 u8 feature_group[0x8]; 8492 u8 reserved_at_10[0x8]; 8493 u8 access_reg_group[0x8]; 8494 8495 u8 reserved_at_20[0x20]; 8496 8497 union { 8498 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8499 u8 reserved_at_0[0x80]; 8500 } mng_access_reg_cap_mask; 8501 8502 u8 reserved_at_c0[0x80]; 8503 8504 union { 8505 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8506 u8 reserved_at_0[0x80]; 8507 } mng_feature_cap_mask; 8508 8509 u8 reserved_at_1c0[0x80]; 8510 }; 8511 8512 struct mlx5_ifc_qcam_access_reg_cap_mask { 8513 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8514 u8 qpdpm[0x1]; 8515 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8516 u8 qdpm[0x1]; 8517 u8 qpts[0x1]; 8518 u8 qcap[0x1]; 8519 u8 qcam_access_reg_cap_mask_0[0x1]; 8520 }; 8521 8522 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8523 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8524 u8 qpts_trust_both[0x1]; 8525 }; 8526 8527 struct mlx5_ifc_qcam_reg_bits { 8528 u8 reserved_at_0[0x8]; 8529 u8 feature_group[0x8]; 8530 u8 reserved_at_10[0x8]; 8531 u8 access_reg_group[0x8]; 8532 u8 reserved_at_20[0x20]; 8533 8534 union { 8535 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8536 u8 reserved_at_0[0x80]; 8537 } qos_access_reg_cap_mask; 8538 8539 u8 reserved_at_c0[0x80]; 8540 8541 union { 8542 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8543 u8 reserved_at_0[0x80]; 8544 } qos_feature_cap_mask; 8545 8546 u8 reserved_at_1c0[0x80]; 8547 }; 8548 8549 struct mlx5_ifc_pcap_reg_bits { 8550 u8 reserved_at_0[0x8]; 8551 u8 local_port[0x8]; 8552 u8 reserved_at_10[0x10]; 8553 8554 u8 port_capability_mask[4][0x20]; 8555 }; 8556 8557 struct mlx5_ifc_paos_reg_bits { 8558 u8 swid[0x8]; 8559 u8 local_port[0x8]; 8560 u8 reserved_at_10[0x4]; 8561 u8 admin_status[0x4]; 8562 u8 reserved_at_18[0x4]; 8563 u8 oper_status[0x4]; 8564 8565 u8 ase[0x1]; 8566 u8 ee[0x1]; 8567 u8 reserved_at_22[0x1c]; 8568 u8 e[0x2]; 8569 8570 u8 reserved_at_40[0x40]; 8571 }; 8572 8573 struct mlx5_ifc_pamp_reg_bits { 8574 u8 reserved_at_0[0x8]; 8575 u8 opamp_group[0x8]; 8576 u8 reserved_at_10[0xc]; 8577 u8 opamp_group_type[0x4]; 8578 8579 u8 start_index[0x10]; 8580 u8 reserved_at_30[0x4]; 8581 u8 num_of_indices[0xc]; 8582 8583 u8 index_data[18][0x10]; 8584 }; 8585 8586 struct mlx5_ifc_pcmr_reg_bits { 8587 u8 reserved_at_0[0x8]; 8588 u8 local_port[0x8]; 8589 u8 reserved_at_10[0x10]; 8590 u8 entropy_force_cap[0x1]; 8591 u8 entropy_calc_cap[0x1]; 8592 u8 entropy_gre_calc_cap[0x1]; 8593 u8 reserved_at_23[0x1b]; 8594 u8 fcs_cap[0x1]; 8595 u8 reserved_at_3f[0x1]; 8596 u8 entropy_force[0x1]; 8597 u8 entropy_calc[0x1]; 8598 u8 entropy_gre_calc[0x1]; 8599 u8 reserved_at_43[0x1b]; 8600 u8 fcs_chk[0x1]; 8601 u8 reserved_at_5f[0x1]; 8602 }; 8603 8604 struct mlx5_ifc_lane_2_module_mapping_bits { 8605 u8 reserved_at_0[0x6]; 8606 u8 rx_lane[0x2]; 8607 u8 reserved_at_8[0x6]; 8608 u8 tx_lane[0x2]; 8609 u8 reserved_at_10[0x8]; 8610 u8 module[0x8]; 8611 }; 8612 8613 struct mlx5_ifc_bufferx_reg_bits { 8614 u8 reserved_at_0[0x6]; 8615 u8 lossy[0x1]; 8616 u8 epsb[0x1]; 8617 u8 reserved_at_8[0xc]; 8618 u8 size[0xc]; 8619 8620 u8 xoff_threshold[0x10]; 8621 u8 xon_threshold[0x10]; 8622 }; 8623 8624 struct mlx5_ifc_set_node_in_bits { 8625 u8 node_description[64][0x8]; 8626 }; 8627 8628 struct mlx5_ifc_register_power_settings_bits { 8629 u8 reserved_at_0[0x18]; 8630 u8 power_settings_level[0x8]; 8631 8632 u8 reserved_at_20[0x60]; 8633 }; 8634 8635 struct mlx5_ifc_register_host_endianness_bits { 8636 u8 he[0x1]; 8637 u8 reserved_at_1[0x1f]; 8638 8639 u8 reserved_at_20[0x60]; 8640 }; 8641 8642 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8643 u8 reserved_at_0[0x20]; 8644 8645 u8 mkey[0x20]; 8646 8647 u8 addressh_63_32[0x20]; 8648 8649 u8 addressl_31_0[0x20]; 8650 }; 8651 8652 struct mlx5_ifc_ud_adrs_vector_bits { 8653 u8 dc_key[0x40]; 8654 8655 u8 ext[0x1]; 8656 u8 reserved_at_41[0x7]; 8657 u8 destination_qp_dct[0x18]; 8658 8659 u8 static_rate[0x4]; 8660 u8 sl_eth_prio[0x4]; 8661 u8 fl[0x1]; 8662 u8 mlid[0x7]; 8663 u8 rlid_udp_sport[0x10]; 8664 8665 u8 reserved_at_80[0x20]; 8666 8667 u8 rmac_47_16[0x20]; 8668 8669 u8 rmac_15_0[0x10]; 8670 u8 tclass[0x8]; 8671 u8 hop_limit[0x8]; 8672 8673 u8 reserved_at_e0[0x1]; 8674 u8 grh[0x1]; 8675 u8 reserved_at_e2[0x2]; 8676 u8 src_addr_index[0x8]; 8677 u8 flow_label[0x14]; 8678 8679 u8 rgid_rip[16][0x8]; 8680 }; 8681 8682 struct mlx5_ifc_pages_req_event_bits { 8683 u8 reserved_at_0[0x10]; 8684 u8 function_id[0x10]; 8685 8686 u8 num_pages[0x20]; 8687 8688 u8 reserved_at_40[0xa0]; 8689 }; 8690 8691 struct mlx5_ifc_eqe_bits { 8692 u8 reserved_at_0[0x8]; 8693 u8 event_type[0x8]; 8694 u8 reserved_at_10[0x8]; 8695 u8 event_sub_type[0x8]; 8696 8697 u8 reserved_at_20[0xe0]; 8698 8699 union mlx5_ifc_event_auto_bits event_data; 8700 8701 u8 reserved_at_1e0[0x10]; 8702 u8 signature[0x8]; 8703 u8 reserved_at_1f8[0x7]; 8704 u8 owner[0x1]; 8705 }; 8706 8707 enum { 8708 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8709 }; 8710 8711 struct mlx5_ifc_cmd_queue_entry_bits { 8712 u8 type[0x8]; 8713 u8 reserved_at_8[0x18]; 8714 8715 u8 input_length[0x20]; 8716 8717 u8 input_mailbox_pointer_63_32[0x20]; 8718 8719 u8 input_mailbox_pointer_31_9[0x17]; 8720 u8 reserved_at_77[0x9]; 8721 8722 u8 command_input_inline_data[16][0x8]; 8723 8724 u8 command_output_inline_data[16][0x8]; 8725 8726 u8 output_mailbox_pointer_63_32[0x20]; 8727 8728 u8 output_mailbox_pointer_31_9[0x17]; 8729 u8 reserved_at_1b7[0x9]; 8730 8731 u8 output_length[0x20]; 8732 8733 u8 token[0x8]; 8734 u8 signature[0x8]; 8735 u8 reserved_at_1f0[0x8]; 8736 u8 status[0x7]; 8737 u8 ownership[0x1]; 8738 }; 8739 8740 struct mlx5_ifc_cmd_out_bits { 8741 u8 status[0x8]; 8742 u8 reserved_at_8[0x18]; 8743 8744 u8 syndrome[0x20]; 8745 8746 u8 command_output[0x20]; 8747 }; 8748 8749 struct mlx5_ifc_cmd_in_bits { 8750 u8 opcode[0x10]; 8751 u8 reserved_at_10[0x10]; 8752 8753 u8 reserved_at_20[0x10]; 8754 u8 op_mod[0x10]; 8755 8756 u8 command[0][0x20]; 8757 }; 8758 8759 struct mlx5_ifc_cmd_if_box_bits { 8760 u8 mailbox_data[512][0x8]; 8761 8762 u8 reserved_at_1000[0x180]; 8763 8764 u8 next_pointer_63_32[0x20]; 8765 8766 u8 next_pointer_31_10[0x16]; 8767 u8 reserved_at_11b6[0xa]; 8768 8769 u8 block_number[0x20]; 8770 8771 u8 reserved_at_11e0[0x8]; 8772 u8 token[0x8]; 8773 u8 ctrl_signature[0x8]; 8774 u8 signature[0x8]; 8775 }; 8776 8777 struct mlx5_ifc_mtt_bits { 8778 u8 ptag_63_32[0x20]; 8779 8780 u8 ptag_31_8[0x18]; 8781 u8 reserved_at_38[0x6]; 8782 u8 wr_en[0x1]; 8783 u8 rd_en[0x1]; 8784 }; 8785 8786 struct mlx5_ifc_query_wol_rol_out_bits { 8787 u8 status[0x8]; 8788 u8 reserved_at_8[0x18]; 8789 8790 u8 syndrome[0x20]; 8791 8792 u8 reserved_at_40[0x10]; 8793 u8 rol_mode[0x8]; 8794 u8 wol_mode[0x8]; 8795 8796 u8 reserved_at_60[0x20]; 8797 }; 8798 8799 struct mlx5_ifc_query_wol_rol_in_bits { 8800 u8 opcode[0x10]; 8801 u8 reserved_at_10[0x10]; 8802 8803 u8 reserved_at_20[0x10]; 8804 u8 op_mod[0x10]; 8805 8806 u8 reserved_at_40[0x40]; 8807 }; 8808 8809 struct mlx5_ifc_set_wol_rol_out_bits { 8810 u8 status[0x8]; 8811 u8 reserved_at_8[0x18]; 8812 8813 u8 syndrome[0x20]; 8814 8815 u8 reserved_at_40[0x40]; 8816 }; 8817 8818 struct mlx5_ifc_set_wol_rol_in_bits { 8819 u8 opcode[0x10]; 8820 u8 reserved_at_10[0x10]; 8821 8822 u8 reserved_at_20[0x10]; 8823 u8 op_mod[0x10]; 8824 8825 u8 rol_mode_valid[0x1]; 8826 u8 wol_mode_valid[0x1]; 8827 u8 reserved_at_42[0xe]; 8828 u8 rol_mode[0x8]; 8829 u8 wol_mode[0x8]; 8830 8831 u8 reserved_at_60[0x20]; 8832 }; 8833 8834 enum { 8835 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8836 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8837 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8838 }; 8839 8840 enum { 8841 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8842 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8843 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8844 }; 8845 8846 enum { 8847 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8848 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8849 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8850 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8851 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8852 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8853 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8854 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8855 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8856 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8857 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8858 }; 8859 8860 struct mlx5_ifc_initial_seg_bits { 8861 u8 fw_rev_minor[0x10]; 8862 u8 fw_rev_major[0x10]; 8863 8864 u8 cmd_interface_rev[0x10]; 8865 u8 fw_rev_subminor[0x10]; 8866 8867 u8 reserved_at_40[0x40]; 8868 8869 u8 cmdq_phy_addr_63_32[0x20]; 8870 8871 u8 cmdq_phy_addr_31_12[0x14]; 8872 u8 reserved_at_b4[0x2]; 8873 u8 nic_interface[0x2]; 8874 u8 log_cmdq_size[0x4]; 8875 u8 log_cmdq_stride[0x4]; 8876 8877 u8 command_doorbell_vector[0x20]; 8878 8879 u8 reserved_at_e0[0xf00]; 8880 8881 u8 initializing[0x1]; 8882 u8 reserved_at_fe1[0x4]; 8883 u8 nic_interface_supported[0x3]; 8884 u8 embedded_cpu[0x1]; 8885 u8 reserved_at_fe9[0x17]; 8886 8887 struct mlx5_ifc_health_buffer_bits health_buffer; 8888 8889 u8 no_dram_nic_offset[0x20]; 8890 8891 u8 reserved_at_1220[0x6e40]; 8892 8893 u8 reserved_at_8060[0x1f]; 8894 u8 clear_int[0x1]; 8895 8896 u8 health_syndrome[0x8]; 8897 u8 health_counter[0x18]; 8898 8899 u8 reserved_at_80a0[0x17fc0]; 8900 }; 8901 8902 struct mlx5_ifc_mtpps_reg_bits { 8903 u8 reserved_at_0[0xc]; 8904 u8 cap_number_of_pps_pins[0x4]; 8905 u8 reserved_at_10[0x4]; 8906 u8 cap_max_num_of_pps_in_pins[0x4]; 8907 u8 reserved_at_18[0x4]; 8908 u8 cap_max_num_of_pps_out_pins[0x4]; 8909 8910 u8 reserved_at_20[0x24]; 8911 u8 cap_pin_3_mode[0x4]; 8912 u8 reserved_at_48[0x4]; 8913 u8 cap_pin_2_mode[0x4]; 8914 u8 reserved_at_50[0x4]; 8915 u8 cap_pin_1_mode[0x4]; 8916 u8 reserved_at_58[0x4]; 8917 u8 cap_pin_0_mode[0x4]; 8918 8919 u8 reserved_at_60[0x4]; 8920 u8 cap_pin_7_mode[0x4]; 8921 u8 reserved_at_68[0x4]; 8922 u8 cap_pin_6_mode[0x4]; 8923 u8 reserved_at_70[0x4]; 8924 u8 cap_pin_5_mode[0x4]; 8925 u8 reserved_at_78[0x4]; 8926 u8 cap_pin_4_mode[0x4]; 8927 8928 u8 field_select[0x20]; 8929 u8 reserved_at_a0[0x60]; 8930 8931 u8 enable[0x1]; 8932 u8 reserved_at_101[0xb]; 8933 u8 pattern[0x4]; 8934 u8 reserved_at_110[0x4]; 8935 u8 pin_mode[0x4]; 8936 u8 pin[0x8]; 8937 8938 u8 reserved_at_120[0x20]; 8939 8940 u8 time_stamp[0x40]; 8941 8942 u8 out_pulse_duration[0x10]; 8943 u8 out_periodic_adjustment[0x10]; 8944 u8 enhanced_out_periodic_adjustment[0x20]; 8945 8946 u8 reserved_at_1c0[0x20]; 8947 }; 8948 8949 struct mlx5_ifc_mtppse_reg_bits { 8950 u8 reserved_at_0[0x18]; 8951 u8 pin[0x8]; 8952 u8 event_arm[0x1]; 8953 u8 reserved_at_21[0x1b]; 8954 u8 event_generation_mode[0x4]; 8955 u8 reserved_at_40[0x40]; 8956 }; 8957 8958 struct mlx5_ifc_mcqi_cap_bits { 8959 u8 supported_info_bitmask[0x20]; 8960 8961 u8 component_size[0x20]; 8962 8963 u8 max_component_size[0x20]; 8964 8965 u8 log_mcda_word_size[0x4]; 8966 u8 reserved_at_64[0xc]; 8967 u8 mcda_max_write_size[0x10]; 8968 8969 u8 rd_en[0x1]; 8970 u8 reserved_at_81[0x1]; 8971 u8 match_chip_id[0x1]; 8972 u8 match_psid[0x1]; 8973 u8 check_user_timestamp[0x1]; 8974 u8 match_base_guid_mac[0x1]; 8975 u8 reserved_at_86[0x1a]; 8976 }; 8977 8978 struct mlx5_ifc_mcqi_reg_bits { 8979 u8 read_pending_component[0x1]; 8980 u8 reserved_at_1[0xf]; 8981 u8 component_index[0x10]; 8982 8983 u8 reserved_at_20[0x20]; 8984 8985 u8 reserved_at_40[0x1b]; 8986 u8 info_type[0x5]; 8987 8988 u8 info_size[0x20]; 8989 8990 u8 offset[0x20]; 8991 8992 u8 reserved_at_a0[0x10]; 8993 u8 data_size[0x10]; 8994 8995 u8 data[0][0x20]; 8996 }; 8997 8998 struct mlx5_ifc_mcc_reg_bits { 8999 u8 reserved_at_0[0x4]; 9000 u8 time_elapsed_since_last_cmd[0xc]; 9001 u8 reserved_at_10[0x8]; 9002 u8 instruction[0x8]; 9003 9004 u8 reserved_at_20[0x10]; 9005 u8 component_index[0x10]; 9006 9007 u8 reserved_at_40[0x8]; 9008 u8 update_handle[0x18]; 9009 9010 u8 handle_owner_type[0x4]; 9011 u8 handle_owner_host_id[0x4]; 9012 u8 reserved_at_68[0x1]; 9013 u8 control_progress[0x7]; 9014 u8 error_code[0x8]; 9015 u8 reserved_at_78[0x4]; 9016 u8 control_state[0x4]; 9017 9018 u8 component_size[0x20]; 9019 9020 u8 reserved_at_a0[0x60]; 9021 }; 9022 9023 struct mlx5_ifc_mcda_reg_bits { 9024 u8 reserved_at_0[0x8]; 9025 u8 update_handle[0x18]; 9026 9027 u8 offset[0x20]; 9028 9029 u8 reserved_at_40[0x10]; 9030 u8 size[0x10]; 9031 9032 u8 reserved_at_60[0x20]; 9033 9034 u8 data[0][0x20]; 9035 }; 9036 9037 union mlx5_ifc_ports_control_registers_document_bits { 9038 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9039 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9040 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9041 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9042 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9043 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9044 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9045 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 9046 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9047 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9048 struct mlx5_ifc_paos_reg_bits paos_reg; 9049 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9050 struct mlx5_ifc_peir_reg_bits peir_reg; 9051 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9052 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9053 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9054 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9055 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9056 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9057 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9058 struct mlx5_ifc_plib_reg_bits plib_reg; 9059 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9060 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9061 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9062 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9063 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9064 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9065 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9066 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9067 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9068 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9069 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9070 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9071 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9072 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9073 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9074 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9075 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9076 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9077 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9078 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9079 struct mlx5_ifc_pude_reg_bits pude_reg; 9080 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9081 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9082 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9083 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9084 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9085 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9086 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9087 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9088 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9089 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9090 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9091 u8 reserved_at_0[0x60e0]; 9092 }; 9093 9094 union mlx5_ifc_debug_enhancements_document_bits { 9095 struct mlx5_ifc_health_buffer_bits health_buffer; 9096 u8 reserved_at_0[0x200]; 9097 }; 9098 9099 union mlx5_ifc_uplink_pci_interface_document_bits { 9100 struct mlx5_ifc_initial_seg_bits initial_seg; 9101 u8 reserved_at_0[0x20060]; 9102 }; 9103 9104 struct mlx5_ifc_set_flow_table_root_out_bits { 9105 u8 status[0x8]; 9106 u8 reserved_at_8[0x18]; 9107 9108 u8 syndrome[0x20]; 9109 9110 u8 reserved_at_40[0x40]; 9111 }; 9112 9113 struct mlx5_ifc_set_flow_table_root_in_bits { 9114 u8 opcode[0x10]; 9115 u8 reserved_at_10[0x10]; 9116 9117 u8 reserved_at_20[0x10]; 9118 u8 op_mod[0x10]; 9119 9120 u8 other_vport[0x1]; 9121 u8 reserved_at_41[0xf]; 9122 u8 vport_number[0x10]; 9123 9124 u8 reserved_at_60[0x20]; 9125 9126 u8 table_type[0x8]; 9127 u8 reserved_at_88[0x18]; 9128 9129 u8 reserved_at_a0[0x8]; 9130 u8 table_id[0x18]; 9131 9132 u8 reserved_at_c0[0x8]; 9133 u8 underlay_qpn[0x18]; 9134 u8 reserved_at_e0[0x120]; 9135 }; 9136 9137 enum { 9138 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9139 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9140 }; 9141 9142 struct mlx5_ifc_modify_flow_table_out_bits { 9143 u8 status[0x8]; 9144 u8 reserved_at_8[0x18]; 9145 9146 u8 syndrome[0x20]; 9147 9148 u8 reserved_at_40[0x40]; 9149 }; 9150 9151 struct mlx5_ifc_modify_flow_table_in_bits { 9152 u8 opcode[0x10]; 9153 u8 reserved_at_10[0x10]; 9154 9155 u8 reserved_at_20[0x10]; 9156 u8 op_mod[0x10]; 9157 9158 u8 other_vport[0x1]; 9159 u8 reserved_at_41[0xf]; 9160 u8 vport_number[0x10]; 9161 9162 u8 reserved_at_60[0x10]; 9163 u8 modify_field_select[0x10]; 9164 9165 u8 table_type[0x8]; 9166 u8 reserved_at_88[0x18]; 9167 9168 u8 reserved_at_a0[0x8]; 9169 u8 table_id[0x18]; 9170 9171 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9172 }; 9173 9174 struct mlx5_ifc_ets_tcn_config_reg_bits { 9175 u8 g[0x1]; 9176 u8 b[0x1]; 9177 u8 r[0x1]; 9178 u8 reserved_at_3[0x9]; 9179 u8 group[0x4]; 9180 u8 reserved_at_10[0x9]; 9181 u8 bw_allocation[0x7]; 9182 9183 u8 reserved_at_20[0xc]; 9184 u8 max_bw_units[0x4]; 9185 u8 reserved_at_30[0x8]; 9186 u8 max_bw_value[0x8]; 9187 }; 9188 9189 struct mlx5_ifc_ets_global_config_reg_bits { 9190 u8 reserved_at_0[0x2]; 9191 u8 r[0x1]; 9192 u8 reserved_at_3[0x1d]; 9193 9194 u8 reserved_at_20[0xc]; 9195 u8 max_bw_units[0x4]; 9196 u8 reserved_at_30[0x8]; 9197 u8 max_bw_value[0x8]; 9198 }; 9199 9200 struct mlx5_ifc_qetc_reg_bits { 9201 u8 reserved_at_0[0x8]; 9202 u8 port_number[0x8]; 9203 u8 reserved_at_10[0x30]; 9204 9205 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9206 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9207 }; 9208 9209 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9210 u8 e[0x1]; 9211 u8 reserved_at_01[0x0b]; 9212 u8 prio[0x04]; 9213 }; 9214 9215 struct mlx5_ifc_qpdpm_reg_bits { 9216 u8 reserved_at_0[0x8]; 9217 u8 local_port[0x8]; 9218 u8 reserved_at_10[0x10]; 9219 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9220 }; 9221 9222 struct mlx5_ifc_qpts_reg_bits { 9223 u8 reserved_at_0[0x8]; 9224 u8 local_port[0x8]; 9225 u8 reserved_at_10[0x2d]; 9226 u8 trust_state[0x3]; 9227 }; 9228 9229 struct mlx5_ifc_pptb_reg_bits { 9230 u8 reserved_at_0[0x2]; 9231 u8 mm[0x2]; 9232 u8 reserved_at_4[0x4]; 9233 u8 local_port[0x8]; 9234 u8 reserved_at_10[0x6]; 9235 u8 cm[0x1]; 9236 u8 um[0x1]; 9237 u8 pm[0x8]; 9238 9239 u8 prio_x_buff[0x20]; 9240 9241 u8 pm_msb[0x8]; 9242 u8 reserved_at_48[0x10]; 9243 u8 ctrl_buff[0x4]; 9244 u8 untagged_buff[0x4]; 9245 }; 9246 9247 struct mlx5_ifc_pbmc_reg_bits { 9248 u8 reserved_at_0[0x8]; 9249 u8 local_port[0x8]; 9250 u8 reserved_at_10[0x10]; 9251 9252 u8 xoff_timer_value[0x10]; 9253 u8 xoff_refresh[0x10]; 9254 9255 u8 reserved_at_40[0x9]; 9256 u8 fullness_threshold[0x7]; 9257 u8 port_buffer_size[0x10]; 9258 9259 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9260 9261 u8 reserved_at_2e0[0x40]; 9262 }; 9263 9264 struct mlx5_ifc_qtct_reg_bits { 9265 u8 reserved_at_0[0x8]; 9266 u8 port_number[0x8]; 9267 u8 reserved_at_10[0xd]; 9268 u8 prio[0x3]; 9269 9270 u8 reserved_at_20[0x1d]; 9271 u8 tclass[0x3]; 9272 }; 9273 9274 struct mlx5_ifc_mcia_reg_bits { 9275 u8 l[0x1]; 9276 u8 reserved_at_1[0x7]; 9277 u8 module[0x8]; 9278 u8 reserved_at_10[0x8]; 9279 u8 status[0x8]; 9280 9281 u8 i2c_device_address[0x8]; 9282 u8 page_number[0x8]; 9283 u8 device_address[0x10]; 9284 9285 u8 reserved_at_40[0x10]; 9286 u8 size[0x10]; 9287 9288 u8 reserved_at_60[0x20]; 9289 9290 u8 dword_0[0x20]; 9291 u8 dword_1[0x20]; 9292 u8 dword_2[0x20]; 9293 u8 dword_3[0x20]; 9294 u8 dword_4[0x20]; 9295 u8 dword_5[0x20]; 9296 u8 dword_6[0x20]; 9297 u8 dword_7[0x20]; 9298 u8 dword_8[0x20]; 9299 u8 dword_9[0x20]; 9300 u8 dword_10[0x20]; 9301 u8 dword_11[0x20]; 9302 }; 9303 9304 struct mlx5_ifc_dcbx_param_bits { 9305 u8 dcbx_cee_cap[0x1]; 9306 u8 dcbx_ieee_cap[0x1]; 9307 u8 dcbx_standby_cap[0x1]; 9308 u8 reserved_at_3[0x5]; 9309 u8 port_number[0x8]; 9310 u8 reserved_at_10[0xa]; 9311 u8 max_application_table_size[6]; 9312 u8 reserved_at_20[0x15]; 9313 u8 version_oper[0x3]; 9314 u8 reserved_at_38[5]; 9315 u8 version_admin[0x3]; 9316 u8 willing_admin[0x1]; 9317 u8 reserved_at_41[0x3]; 9318 u8 pfc_cap_oper[0x4]; 9319 u8 reserved_at_48[0x4]; 9320 u8 pfc_cap_admin[0x4]; 9321 u8 reserved_at_50[0x4]; 9322 u8 num_of_tc_oper[0x4]; 9323 u8 reserved_at_58[0x4]; 9324 u8 num_of_tc_admin[0x4]; 9325 u8 remote_willing[0x1]; 9326 u8 reserved_at_61[3]; 9327 u8 remote_pfc_cap[4]; 9328 u8 reserved_at_68[0x14]; 9329 u8 remote_num_of_tc[0x4]; 9330 u8 reserved_at_80[0x18]; 9331 u8 error[0x8]; 9332 u8 reserved_at_a0[0x160]; 9333 }; 9334 9335 struct mlx5_ifc_lagc_bits { 9336 u8 reserved_at_0[0x1d]; 9337 u8 lag_state[0x3]; 9338 9339 u8 reserved_at_20[0x14]; 9340 u8 tx_remap_affinity_2[0x4]; 9341 u8 reserved_at_38[0x4]; 9342 u8 tx_remap_affinity_1[0x4]; 9343 }; 9344 9345 struct mlx5_ifc_create_lag_out_bits { 9346 u8 status[0x8]; 9347 u8 reserved_at_8[0x18]; 9348 9349 u8 syndrome[0x20]; 9350 9351 u8 reserved_at_40[0x40]; 9352 }; 9353 9354 struct mlx5_ifc_create_lag_in_bits { 9355 u8 opcode[0x10]; 9356 u8 reserved_at_10[0x10]; 9357 9358 u8 reserved_at_20[0x10]; 9359 u8 op_mod[0x10]; 9360 9361 struct mlx5_ifc_lagc_bits ctx; 9362 }; 9363 9364 struct mlx5_ifc_modify_lag_out_bits { 9365 u8 status[0x8]; 9366 u8 reserved_at_8[0x18]; 9367 9368 u8 syndrome[0x20]; 9369 9370 u8 reserved_at_40[0x40]; 9371 }; 9372 9373 struct mlx5_ifc_modify_lag_in_bits { 9374 u8 opcode[0x10]; 9375 u8 reserved_at_10[0x10]; 9376 9377 u8 reserved_at_20[0x10]; 9378 u8 op_mod[0x10]; 9379 9380 u8 reserved_at_40[0x20]; 9381 u8 field_select[0x20]; 9382 9383 struct mlx5_ifc_lagc_bits ctx; 9384 }; 9385 9386 struct mlx5_ifc_query_lag_out_bits { 9387 u8 status[0x8]; 9388 u8 reserved_at_8[0x18]; 9389 9390 u8 syndrome[0x20]; 9391 9392 u8 reserved_at_40[0x40]; 9393 9394 struct mlx5_ifc_lagc_bits ctx; 9395 }; 9396 9397 struct mlx5_ifc_query_lag_in_bits { 9398 u8 opcode[0x10]; 9399 u8 reserved_at_10[0x10]; 9400 9401 u8 reserved_at_20[0x10]; 9402 u8 op_mod[0x10]; 9403 9404 u8 reserved_at_40[0x40]; 9405 }; 9406 9407 struct mlx5_ifc_destroy_lag_out_bits { 9408 u8 status[0x8]; 9409 u8 reserved_at_8[0x18]; 9410 9411 u8 syndrome[0x20]; 9412 9413 u8 reserved_at_40[0x40]; 9414 }; 9415 9416 struct mlx5_ifc_destroy_lag_in_bits { 9417 u8 opcode[0x10]; 9418 u8 reserved_at_10[0x10]; 9419 9420 u8 reserved_at_20[0x10]; 9421 u8 op_mod[0x10]; 9422 9423 u8 reserved_at_40[0x40]; 9424 }; 9425 9426 struct mlx5_ifc_create_vport_lag_out_bits { 9427 u8 status[0x8]; 9428 u8 reserved_at_8[0x18]; 9429 9430 u8 syndrome[0x20]; 9431 9432 u8 reserved_at_40[0x40]; 9433 }; 9434 9435 struct mlx5_ifc_create_vport_lag_in_bits { 9436 u8 opcode[0x10]; 9437 u8 reserved_at_10[0x10]; 9438 9439 u8 reserved_at_20[0x10]; 9440 u8 op_mod[0x10]; 9441 9442 u8 reserved_at_40[0x40]; 9443 }; 9444 9445 struct mlx5_ifc_destroy_vport_lag_out_bits { 9446 u8 status[0x8]; 9447 u8 reserved_at_8[0x18]; 9448 9449 u8 syndrome[0x20]; 9450 9451 u8 reserved_at_40[0x40]; 9452 }; 9453 9454 struct mlx5_ifc_destroy_vport_lag_in_bits { 9455 u8 opcode[0x10]; 9456 u8 reserved_at_10[0x10]; 9457 9458 u8 reserved_at_20[0x10]; 9459 u8 op_mod[0x10]; 9460 9461 u8 reserved_at_40[0x40]; 9462 }; 9463 9464 struct mlx5_ifc_alloc_memic_in_bits { 9465 u8 opcode[0x10]; 9466 u8 reserved_at_10[0x10]; 9467 9468 u8 reserved_at_20[0x10]; 9469 u8 op_mod[0x10]; 9470 9471 u8 reserved_at_30[0x20]; 9472 9473 u8 reserved_at_40[0x18]; 9474 u8 log_memic_addr_alignment[0x8]; 9475 9476 u8 range_start_addr[0x40]; 9477 9478 u8 range_size[0x20]; 9479 9480 u8 memic_size[0x20]; 9481 }; 9482 9483 struct mlx5_ifc_alloc_memic_out_bits { 9484 u8 status[0x8]; 9485 u8 reserved_at_8[0x18]; 9486 9487 u8 syndrome[0x20]; 9488 9489 u8 memic_start_addr[0x40]; 9490 }; 9491 9492 struct mlx5_ifc_dealloc_memic_in_bits { 9493 u8 opcode[0x10]; 9494 u8 reserved_at_10[0x10]; 9495 9496 u8 reserved_at_20[0x10]; 9497 u8 op_mod[0x10]; 9498 9499 u8 reserved_at_40[0x40]; 9500 9501 u8 memic_start_addr[0x40]; 9502 9503 u8 memic_size[0x20]; 9504 9505 u8 reserved_at_e0[0x20]; 9506 }; 9507 9508 struct mlx5_ifc_dealloc_memic_out_bits { 9509 u8 status[0x8]; 9510 u8 reserved_at_8[0x18]; 9511 9512 u8 syndrome[0x20]; 9513 9514 u8 reserved_at_40[0x40]; 9515 }; 9516 9517 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9518 u8 opcode[0x10]; 9519 u8 uid[0x10]; 9520 9521 u8 reserved_at_20[0x10]; 9522 u8 obj_type[0x10]; 9523 9524 u8 obj_id[0x20]; 9525 9526 u8 reserved_at_60[0x20]; 9527 }; 9528 9529 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9530 u8 status[0x8]; 9531 u8 reserved_at_8[0x18]; 9532 9533 u8 syndrome[0x20]; 9534 9535 u8 obj_id[0x20]; 9536 9537 u8 reserved_at_60[0x20]; 9538 }; 9539 9540 struct mlx5_ifc_umem_bits { 9541 u8 reserved_at_0[0x80]; 9542 9543 u8 reserved_at_80[0x1b]; 9544 u8 log_page_size[0x5]; 9545 9546 u8 page_offset[0x20]; 9547 9548 u8 num_of_mtt[0x40]; 9549 9550 struct mlx5_ifc_mtt_bits mtt[0]; 9551 }; 9552 9553 struct mlx5_ifc_uctx_bits { 9554 u8 cap[0x20]; 9555 9556 u8 reserved_at_20[0x160]; 9557 }; 9558 9559 struct mlx5_ifc_sw_icm_bits { 9560 u8 modify_field_select[0x40]; 9561 9562 u8 reserved_at_40[0x18]; 9563 u8 log_sw_icm_size[0x8]; 9564 9565 u8 reserved_at_60[0x20]; 9566 9567 u8 sw_icm_start_addr[0x40]; 9568 9569 u8 reserved_at_c0[0x140]; 9570 }; 9571 9572 struct mlx5_ifc_geneve_tlv_option_bits { 9573 u8 modify_field_select[0x40]; 9574 9575 u8 reserved_at_40[0x18]; 9576 u8 geneve_option_fte_index[0x8]; 9577 9578 u8 option_class[0x10]; 9579 u8 option_type[0x8]; 9580 u8 reserved_at_78[0x3]; 9581 u8 option_data_length[0x5]; 9582 9583 u8 reserved_at_80[0x180]; 9584 }; 9585 9586 struct mlx5_ifc_create_umem_in_bits { 9587 u8 opcode[0x10]; 9588 u8 uid[0x10]; 9589 9590 u8 reserved_at_20[0x10]; 9591 u8 op_mod[0x10]; 9592 9593 u8 reserved_at_40[0x40]; 9594 9595 struct mlx5_ifc_umem_bits umem; 9596 }; 9597 9598 struct mlx5_ifc_create_uctx_in_bits { 9599 u8 opcode[0x10]; 9600 u8 reserved_at_10[0x10]; 9601 9602 u8 reserved_at_20[0x10]; 9603 u8 op_mod[0x10]; 9604 9605 u8 reserved_at_40[0x40]; 9606 9607 struct mlx5_ifc_uctx_bits uctx; 9608 }; 9609 9610 struct mlx5_ifc_destroy_uctx_in_bits { 9611 u8 opcode[0x10]; 9612 u8 reserved_at_10[0x10]; 9613 9614 u8 reserved_at_20[0x10]; 9615 u8 op_mod[0x10]; 9616 9617 u8 reserved_at_40[0x10]; 9618 u8 uid[0x10]; 9619 9620 u8 reserved_at_60[0x20]; 9621 }; 9622 9623 struct mlx5_ifc_create_sw_icm_in_bits { 9624 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9625 struct mlx5_ifc_sw_icm_bits sw_icm; 9626 }; 9627 9628 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 9629 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9630 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 9631 }; 9632 9633 struct mlx5_ifc_mtrc_string_db_param_bits { 9634 u8 string_db_base_address[0x20]; 9635 9636 u8 reserved_at_20[0x8]; 9637 u8 string_db_size[0x18]; 9638 }; 9639 9640 struct mlx5_ifc_mtrc_cap_bits { 9641 u8 trace_owner[0x1]; 9642 u8 trace_to_memory[0x1]; 9643 u8 reserved_at_2[0x4]; 9644 u8 trc_ver[0x2]; 9645 u8 reserved_at_8[0x14]; 9646 u8 num_string_db[0x4]; 9647 9648 u8 first_string_trace[0x8]; 9649 u8 num_string_trace[0x8]; 9650 u8 reserved_at_30[0x28]; 9651 9652 u8 log_max_trace_buffer_size[0x8]; 9653 9654 u8 reserved_at_60[0x20]; 9655 9656 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9657 9658 u8 reserved_at_280[0x180]; 9659 }; 9660 9661 struct mlx5_ifc_mtrc_conf_bits { 9662 u8 reserved_at_0[0x1c]; 9663 u8 trace_mode[0x4]; 9664 u8 reserved_at_20[0x18]; 9665 u8 log_trace_buffer_size[0x8]; 9666 u8 trace_mkey[0x20]; 9667 u8 reserved_at_60[0x3a0]; 9668 }; 9669 9670 struct mlx5_ifc_mtrc_stdb_bits { 9671 u8 string_db_index[0x4]; 9672 u8 reserved_at_4[0x4]; 9673 u8 read_size[0x18]; 9674 u8 start_offset[0x20]; 9675 u8 string_db_data[0]; 9676 }; 9677 9678 struct mlx5_ifc_mtrc_ctrl_bits { 9679 u8 trace_status[0x2]; 9680 u8 reserved_at_2[0x2]; 9681 u8 arm_event[0x1]; 9682 u8 reserved_at_5[0xb]; 9683 u8 modify_field_select[0x10]; 9684 u8 reserved_at_20[0x2b]; 9685 u8 current_timestamp52_32[0x15]; 9686 u8 current_timestamp31_0[0x20]; 9687 u8 reserved_at_80[0x180]; 9688 }; 9689 9690 struct mlx5_ifc_host_params_context_bits { 9691 u8 host_number[0x8]; 9692 u8 reserved_at_8[0x8]; 9693 u8 host_num_of_vfs[0x10]; 9694 9695 u8 reserved_at_20[0x10]; 9696 u8 host_pci_bus[0x10]; 9697 9698 u8 reserved_at_40[0x10]; 9699 u8 host_pci_device[0x10]; 9700 9701 u8 reserved_at_60[0x10]; 9702 u8 host_pci_function[0x10]; 9703 9704 u8 reserved_at_80[0x180]; 9705 }; 9706 9707 struct mlx5_ifc_query_host_params_in_bits { 9708 u8 opcode[0x10]; 9709 u8 reserved_at_10[0x10]; 9710 9711 u8 reserved_at_20[0x10]; 9712 u8 op_mod[0x10]; 9713 9714 u8 reserved_at_40[0x40]; 9715 }; 9716 9717 struct mlx5_ifc_query_host_params_out_bits { 9718 u8 status[0x8]; 9719 u8 reserved_at_8[0x18]; 9720 9721 u8 syndrome[0x20]; 9722 9723 u8 reserved_at_40[0x40]; 9724 9725 struct mlx5_ifc_host_params_context_bits host_params_context; 9726 9727 u8 reserved_at_280[0x180]; 9728 }; 9729 9730 #endif /* MLX5_IFC_H */ 9731