1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_SHARED_RESOURCE_UID = 0xffff, 80 }; 81 82 enum { 83 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 84 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 85 MLX5_CMD_OP_INIT_HCA = 0x102, 86 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 87 MLX5_CMD_OP_ENABLE_HCA = 0x104, 88 MLX5_CMD_OP_DISABLE_HCA = 0x105, 89 MLX5_CMD_OP_QUERY_PAGES = 0x107, 90 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 91 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 92 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 93 MLX5_CMD_OP_SET_ISSI = 0x10b, 94 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 95 MLX5_CMD_OP_CREATE_MKEY = 0x200, 96 MLX5_CMD_OP_QUERY_MKEY = 0x201, 97 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 98 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 99 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 100 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 101 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 102 MLX5_CMD_OP_CREATE_EQ = 0x301, 103 MLX5_CMD_OP_DESTROY_EQ = 0x302, 104 MLX5_CMD_OP_QUERY_EQ = 0x303, 105 MLX5_CMD_OP_GEN_EQE = 0x304, 106 MLX5_CMD_OP_CREATE_CQ = 0x400, 107 MLX5_CMD_OP_DESTROY_CQ = 0x401, 108 MLX5_CMD_OP_QUERY_CQ = 0x402, 109 MLX5_CMD_OP_MODIFY_CQ = 0x403, 110 MLX5_CMD_OP_CREATE_QP = 0x500, 111 MLX5_CMD_OP_DESTROY_QP = 0x501, 112 MLX5_CMD_OP_RST2INIT_QP = 0x502, 113 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 114 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 115 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 116 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 117 MLX5_CMD_OP_2ERR_QP = 0x507, 118 MLX5_CMD_OP_2RST_QP = 0x50a, 119 MLX5_CMD_OP_QUERY_QP = 0x50b, 120 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 121 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 122 MLX5_CMD_OP_CREATE_PSV = 0x600, 123 MLX5_CMD_OP_DESTROY_PSV = 0x601, 124 MLX5_CMD_OP_CREATE_SRQ = 0x700, 125 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 126 MLX5_CMD_OP_QUERY_SRQ = 0x702, 127 MLX5_CMD_OP_ARM_RQ = 0x703, 128 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 129 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 130 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 131 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 132 MLX5_CMD_OP_CREATE_DCT = 0x710, 133 MLX5_CMD_OP_DESTROY_DCT = 0x711, 134 MLX5_CMD_OP_DRAIN_DCT = 0x712, 135 MLX5_CMD_OP_QUERY_DCT = 0x713, 136 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 137 MLX5_CMD_OP_CREATE_XRQ = 0x717, 138 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 139 MLX5_CMD_OP_QUERY_XRQ = 0x719, 140 MLX5_CMD_OP_ARM_XRQ = 0x71a, 141 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 142 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 143 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 144 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 145 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 146 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 147 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 148 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 149 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 150 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 151 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 152 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 153 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 154 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 156 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 157 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 158 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 159 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 160 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 161 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 162 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 163 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 164 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 165 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 166 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 167 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 168 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 169 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 170 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 171 MLX5_CMD_OP_ALLOC_PD = 0x800, 172 MLX5_CMD_OP_DEALLOC_PD = 0x801, 173 MLX5_CMD_OP_ALLOC_UAR = 0x802, 174 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 175 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 176 MLX5_CMD_OP_ACCESS_REG = 0x805, 177 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 178 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 179 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 180 MLX5_CMD_OP_MAD_IFC = 0x50d, 181 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 182 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 183 MLX5_CMD_OP_NOP = 0x80d, 184 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 185 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 186 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 187 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 188 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 189 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 190 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 191 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 192 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 193 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 194 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 195 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 196 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 197 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 198 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 199 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 200 MLX5_CMD_OP_CREATE_LAG = 0x840, 201 MLX5_CMD_OP_MODIFY_LAG = 0x841, 202 MLX5_CMD_OP_QUERY_LAG = 0x842, 203 MLX5_CMD_OP_DESTROY_LAG = 0x843, 204 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 205 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 206 MLX5_CMD_OP_CREATE_TIR = 0x900, 207 MLX5_CMD_OP_MODIFY_TIR = 0x901, 208 MLX5_CMD_OP_DESTROY_TIR = 0x902, 209 MLX5_CMD_OP_QUERY_TIR = 0x903, 210 MLX5_CMD_OP_CREATE_SQ = 0x904, 211 MLX5_CMD_OP_MODIFY_SQ = 0x905, 212 MLX5_CMD_OP_DESTROY_SQ = 0x906, 213 MLX5_CMD_OP_QUERY_SQ = 0x907, 214 MLX5_CMD_OP_CREATE_RQ = 0x908, 215 MLX5_CMD_OP_MODIFY_RQ = 0x909, 216 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 217 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 218 MLX5_CMD_OP_QUERY_RQ = 0x90b, 219 MLX5_CMD_OP_CREATE_RMP = 0x90c, 220 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 221 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 222 MLX5_CMD_OP_QUERY_RMP = 0x90f, 223 MLX5_CMD_OP_CREATE_TIS = 0x912, 224 MLX5_CMD_OP_MODIFY_TIS = 0x913, 225 MLX5_CMD_OP_DESTROY_TIS = 0x914, 226 MLX5_CMD_OP_QUERY_TIS = 0x915, 227 MLX5_CMD_OP_CREATE_RQT = 0x916, 228 MLX5_CMD_OP_MODIFY_RQT = 0x917, 229 MLX5_CMD_OP_DESTROY_RQT = 0x918, 230 MLX5_CMD_OP_QUERY_RQT = 0x919, 231 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 232 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 233 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 234 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 235 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 236 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 237 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 238 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 239 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 240 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 242 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 243 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 244 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 245 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 246 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 247 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 260 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 261 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 262 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 263 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 264 MLX5_CMD_OP_MAX 265 }; 266 267 /* Valid range for general commands that don't work over an object */ 268 enum { 269 MLX5_CMD_OP_GENERAL_START = 0xb00, 270 MLX5_CMD_OP_GENERAL_END = 0xd00, 271 }; 272 273 struct mlx5_ifc_flow_table_fields_supported_bits { 274 u8 outer_dmac[0x1]; 275 u8 outer_smac[0x1]; 276 u8 outer_ether_type[0x1]; 277 u8 outer_ip_version[0x1]; 278 u8 outer_first_prio[0x1]; 279 u8 outer_first_cfi[0x1]; 280 u8 outer_first_vid[0x1]; 281 u8 outer_ipv4_ttl[0x1]; 282 u8 outer_second_prio[0x1]; 283 u8 outer_second_cfi[0x1]; 284 u8 outer_second_vid[0x1]; 285 u8 reserved_at_b[0x1]; 286 u8 outer_sip[0x1]; 287 u8 outer_dip[0x1]; 288 u8 outer_frag[0x1]; 289 u8 outer_ip_protocol[0x1]; 290 u8 outer_ip_ecn[0x1]; 291 u8 outer_ip_dscp[0x1]; 292 u8 outer_udp_sport[0x1]; 293 u8 outer_udp_dport[0x1]; 294 u8 outer_tcp_sport[0x1]; 295 u8 outer_tcp_dport[0x1]; 296 u8 outer_tcp_flags[0x1]; 297 u8 outer_gre_protocol[0x1]; 298 u8 outer_gre_key[0x1]; 299 u8 outer_vxlan_vni[0x1]; 300 u8 reserved_at_1a[0x5]; 301 u8 source_eswitch_port[0x1]; 302 303 u8 inner_dmac[0x1]; 304 u8 inner_smac[0x1]; 305 u8 inner_ether_type[0x1]; 306 u8 inner_ip_version[0x1]; 307 u8 inner_first_prio[0x1]; 308 u8 inner_first_cfi[0x1]; 309 u8 inner_first_vid[0x1]; 310 u8 reserved_at_27[0x1]; 311 u8 inner_second_prio[0x1]; 312 u8 inner_second_cfi[0x1]; 313 u8 inner_second_vid[0x1]; 314 u8 reserved_at_2b[0x1]; 315 u8 inner_sip[0x1]; 316 u8 inner_dip[0x1]; 317 u8 inner_frag[0x1]; 318 u8 inner_ip_protocol[0x1]; 319 u8 inner_ip_ecn[0x1]; 320 u8 inner_ip_dscp[0x1]; 321 u8 inner_udp_sport[0x1]; 322 u8 inner_udp_dport[0x1]; 323 u8 inner_tcp_sport[0x1]; 324 u8 inner_tcp_dport[0x1]; 325 u8 inner_tcp_flags[0x1]; 326 u8 reserved_at_37[0x9]; 327 328 u8 reserved_at_40[0x5]; 329 u8 outer_first_mpls_over_udp[0x4]; 330 u8 outer_first_mpls_over_gre[0x4]; 331 u8 inner_first_mpls[0x4]; 332 u8 outer_first_mpls[0x4]; 333 u8 reserved_at_55[0x2]; 334 u8 outer_esp_spi[0x1]; 335 u8 reserved_at_58[0x2]; 336 u8 bth_dst_qp[0x1]; 337 338 u8 reserved_at_5b[0x25]; 339 }; 340 341 struct mlx5_ifc_flow_table_prop_layout_bits { 342 u8 ft_support[0x1]; 343 u8 reserved_at_1[0x1]; 344 u8 flow_counter[0x1]; 345 u8 flow_modify_en[0x1]; 346 u8 modify_root[0x1]; 347 u8 identified_miss_table_mode[0x1]; 348 u8 flow_table_modify[0x1]; 349 u8 reformat[0x1]; 350 u8 decap[0x1]; 351 u8 reserved_at_9[0x1]; 352 u8 pop_vlan[0x1]; 353 u8 push_vlan[0x1]; 354 u8 reserved_at_c[0x1]; 355 u8 pop_vlan_2[0x1]; 356 u8 push_vlan_2[0x1]; 357 u8 reformat_and_vlan_action[0x1]; 358 u8 reserved_at_10[0x2]; 359 u8 reformat_l3_tunnel_to_l2[0x1]; 360 u8 reformat_l2_to_l3_tunnel[0x1]; 361 u8 reformat_and_modify_action[0x1]; 362 u8 reserved_at_15[0xb]; 363 u8 reserved_at_20[0x2]; 364 u8 log_max_ft_size[0x6]; 365 u8 log_max_modify_header_context[0x8]; 366 u8 max_modify_header_actions[0x8]; 367 u8 max_ft_level[0x8]; 368 369 u8 reserved_at_40[0x20]; 370 371 u8 reserved_at_60[0x18]; 372 u8 log_max_ft_num[0x8]; 373 374 u8 reserved_at_80[0x18]; 375 u8 log_max_destination[0x8]; 376 377 u8 log_max_flow_counter[0x8]; 378 u8 reserved_at_a8[0x10]; 379 u8 log_max_flow[0x8]; 380 381 u8 reserved_at_c0[0x40]; 382 383 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 384 385 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 386 }; 387 388 struct mlx5_ifc_odp_per_transport_service_cap_bits { 389 u8 send[0x1]; 390 u8 receive[0x1]; 391 u8 write[0x1]; 392 u8 read[0x1]; 393 u8 atomic[0x1]; 394 u8 srq_receive[0x1]; 395 u8 reserved_at_6[0x1a]; 396 }; 397 398 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 399 u8 smac_47_16[0x20]; 400 401 u8 smac_15_0[0x10]; 402 u8 ethertype[0x10]; 403 404 u8 dmac_47_16[0x20]; 405 406 u8 dmac_15_0[0x10]; 407 u8 first_prio[0x3]; 408 u8 first_cfi[0x1]; 409 u8 first_vid[0xc]; 410 411 u8 ip_protocol[0x8]; 412 u8 ip_dscp[0x6]; 413 u8 ip_ecn[0x2]; 414 u8 cvlan_tag[0x1]; 415 u8 svlan_tag[0x1]; 416 u8 frag[0x1]; 417 u8 ip_version[0x4]; 418 u8 tcp_flags[0x9]; 419 420 u8 tcp_sport[0x10]; 421 u8 tcp_dport[0x10]; 422 423 u8 reserved_at_c0[0x18]; 424 u8 ttl_hoplimit[0x8]; 425 426 u8 udp_sport[0x10]; 427 u8 udp_dport[0x10]; 428 429 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 430 431 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 432 }; 433 434 struct mlx5_ifc_nvgre_key_bits { 435 u8 hi[0x18]; 436 u8 lo[0x8]; 437 }; 438 439 union mlx5_ifc_gre_key_bits { 440 struct mlx5_ifc_nvgre_key_bits nvgre; 441 u8 key[0x20]; 442 }; 443 444 struct mlx5_ifc_fte_match_set_misc_bits { 445 u8 reserved_at_0[0x8]; 446 u8 source_sqn[0x18]; 447 448 u8 source_eswitch_owner_vhca_id[0x10]; 449 u8 source_port[0x10]; 450 451 u8 outer_second_prio[0x3]; 452 u8 outer_second_cfi[0x1]; 453 u8 outer_second_vid[0xc]; 454 u8 inner_second_prio[0x3]; 455 u8 inner_second_cfi[0x1]; 456 u8 inner_second_vid[0xc]; 457 458 u8 outer_second_cvlan_tag[0x1]; 459 u8 inner_second_cvlan_tag[0x1]; 460 u8 outer_second_svlan_tag[0x1]; 461 u8 inner_second_svlan_tag[0x1]; 462 u8 reserved_at_64[0xc]; 463 u8 gre_protocol[0x10]; 464 465 union mlx5_ifc_gre_key_bits gre_key; 466 467 u8 vxlan_vni[0x18]; 468 u8 reserved_at_b8[0x8]; 469 470 u8 reserved_at_c0[0x20]; 471 472 u8 reserved_at_e0[0xc]; 473 u8 outer_ipv6_flow_label[0x14]; 474 475 u8 reserved_at_100[0xc]; 476 u8 inner_ipv6_flow_label[0x14]; 477 478 u8 reserved_at_120[0x28]; 479 u8 bth_dst_qp[0x18]; 480 u8 reserved_at_160[0x20]; 481 u8 outer_esp_spi[0x20]; 482 u8 reserved_at_1a0[0x60]; 483 }; 484 485 struct mlx5_ifc_fte_match_mpls_bits { 486 u8 mpls_label[0x14]; 487 u8 mpls_exp[0x3]; 488 u8 mpls_s_bos[0x1]; 489 u8 mpls_ttl[0x8]; 490 }; 491 492 struct mlx5_ifc_fte_match_set_misc2_bits { 493 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 494 495 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 496 497 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 498 499 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 500 501 u8 reserved_at_80[0x100]; 502 503 u8 metadata_reg_a[0x20]; 504 505 u8 reserved_at_1a0[0x60]; 506 }; 507 508 struct mlx5_ifc_cmd_pas_bits { 509 u8 pa_h[0x20]; 510 511 u8 pa_l[0x14]; 512 u8 reserved_at_34[0xc]; 513 }; 514 515 struct mlx5_ifc_uint64_bits { 516 u8 hi[0x20]; 517 518 u8 lo[0x20]; 519 }; 520 521 enum { 522 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 523 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 524 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 525 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 526 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 527 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 528 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 529 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 530 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 531 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 532 }; 533 534 struct mlx5_ifc_ads_bits { 535 u8 fl[0x1]; 536 u8 free_ar[0x1]; 537 u8 reserved_at_2[0xe]; 538 u8 pkey_index[0x10]; 539 540 u8 reserved_at_20[0x8]; 541 u8 grh[0x1]; 542 u8 mlid[0x7]; 543 u8 rlid[0x10]; 544 545 u8 ack_timeout[0x5]; 546 u8 reserved_at_45[0x3]; 547 u8 src_addr_index[0x8]; 548 u8 reserved_at_50[0x4]; 549 u8 stat_rate[0x4]; 550 u8 hop_limit[0x8]; 551 552 u8 reserved_at_60[0x4]; 553 u8 tclass[0x8]; 554 u8 flow_label[0x14]; 555 556 u8 rgid_rip[16][0x8]; 557 558 u8 reserved_at_100[0x4]; 559 u8 f_dscp[0x1]; 560 u8 f_ecn[0x1]; 561 u8 reserved_at_106[0x1]; 562 u8 f_eth_prio[0x1]; 563 u8 ecn[0x2]; 564 u8 dscp[0x6]; 565 u8 udp_sport[0x10]; 566 567 u8 dei_cfi[0x1]; 568 u8 eth_prio[0x3]; 569 u8 sl[0x4]; 570 u8 vhca_port_num[0x8]; 571 u8 rmac_47_32[0x10]; 572 573 u8 rmac_31_0[0x20]; 574 }; 575 576 struct mlx5_ifc_flow_table_nic_cap_bits { 577 u8 nic_rx_multi_path_tirs[0x1]; 578 u8 nic_rx_multi_path_tirs_fts[0x1]; 579 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 580 u8 reserved_at_3[0x1d]; 581 u8 encap_general_header[0x1]; 582 u8 reserved_at_21[0xa]; 583 u8 log_max_packet_reformat_context[0x5]; 584 u8 reserved_at_30[0x6]; 585 u8 max_encap_header_size[0xa]; 586 u8 reserved_at_40[0x1c0]; 587 588 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 589 590 u8 reserved_at_400[0x200]; 591 592 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 593 594 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 595 596 u8 reserved_at_a00[0x200]; 597 598 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 599 600 u8 reserved_at_e00[0x7200]; 601 }; 602 603 struct mlx5_ifc_flow_table_eswitch_cap_bits { 604 u8 reserved_at_0[0x1a]; 605 u8 multi_fdb_encap[0x1]; 606 u8 reserved_at_1b[0x1]; 607 u8 fdb_multi_path_to_table[0x1]; 608 u8 reserved_at_1d[0x3]; 609 610 u8 reserved_at_20[0x1e0]; 611 612 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 613 614 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 615 616 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 617 618 u8 reserved_at_800[0x7800]; 619 }; 620 621 enum { 622 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 623 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 624 }; 625 626 struct mlx5_ifc_e_switch_cap_bits { 627 u8 vport_svlan_strip[0x1]; 628 u8 vport_cvlan_strip[0x1]; 629 u8 vport_svlan_insert[0x1]; 630 u8 vport_cvlan_insert_if_not_exist[0x1]; 631 u8 vport_cvlan_insert_overwrite[0x1]; 632 u8 reserved_at_5[0x17]; 633 u8 counter_eswitch_affinity[0x1]; 634 u8 merged_eswitch[0x1]; 635 u8 nic_vport_node_guid_modify[0x1]; 636 u8 nic_vport_port_guid_modify[0x1]; 637 638 u8 vxlan_encap_decap[0x1]; 639 u8 nvgre_encap_decap[0x1]; 640 u8 reserved_at_22[0x1]; 641 u8 log_max_fdb_encap_uplink[0x5]; 642 u8 reserved_at_21[0x3]; 643 u8 log_max_packet_reformat_context[0x5]; 644 u8 reserved_2b[0x6]; 645 u8 max_encap_header_size[0xa]; 646 647 u8 reserved_40[0x7c0]; 648 649 }; 650 651 struct mlx5_ifc_qos_cap_bits { 652 u8 packet_pacing[0x1]; 653 u8 esw_scheduling[0x1]; 654 u8 esw_bw_share[0x1]; 655 u8 esw_rate_limit[0x1]; 656 u8 reserved_at_4[0x1]; 657 u8 packet_pacing_burst_bound[0x1]; 658 u8 packet_pacing_typical_size[0x1]; 659 u8 reserved_at_7[0x19]; 660 661 u8 reserved_at_20[0x20]; 662 663 u8 packet_pacing_max_rate[0x20]; 664 665 u8 packet_pacing_min_rate[0x20]; 666 667 u8 reserved_at_80[0x10]; 668 u8 packet_pacing_rate_table_size[0x10]; 669 670 u8 esw_element_type[0x10]; 671 u8 esw_tsar_type[0x10]; 672 673 u8 reserved_at_c0[0x10]; 674 u8 max_qos_para_vport[0x10]; 675 676 u8 max_tsar_bw_share[0x20]; 677 678 u8 reserved_at_100[0x700]; 679 }; 680 681 struct mlx5_ifc_debug_cap_bits { 682 u8 reserved_at_0[0x20]; 683 684 u8 reserved_at_20[0x2]; 685 u8 stall_detect[0x1]; 686 u8 reserved_at_23[0x1d]; 687 688 u8 reserved_at_40[0x7c0]; 689 }; 690 691 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 692 u8 csum_cap[0x1]; 693 u8 vlan_cap[0x1]; 694 u8 lro_cap[0x1]; 695 u8 lro_psh_flag[0x1]; 696 u8 lro_time_stamp[0x1]; 697 u8 reserved_at_5[0x2]; 698 u8 wqe_vlan_insert[0x1]; 699 u8 self_lb_en_modifiable[0x1]; 700 u8 reserved_at_9[0x2]; 701 u8 max_lso_cap[0x5]; 702 u8 multi_pkt_send_wqe[0x2]; 703 u8 wqe_inline_mode[0x2]; 704 u8 rss_ind_tbl_cap[0x4]; 705 u8 reg_umr_sq[0x1]; 706 u8 scatter_fcs[0x1]; 707 u8 enhanced_multi_pkt_send_wqe[0x1]; 708 u8 tunnel_lso_const_out_ip_id[0x1]; 709 u8 reserved_at_1c[0x2]; 710 u8 tunnel_stateless_gre[0x1]; 711 u8 tunnel_stateless_vxlan[0x1]; 712 713 u8 swp[0x1]; 714 u8 swp_csum[0x1]; 715 u8 swp_lso[0x1]; 716 u8 reserved_at_23[0xd]; 717 u8 max_vxlan_udp_ports[0x8]; 718 u8 reserved_at_38[0x6]; 719 u8 max_geneve_opt_len[0x1]; 720 u8 tunnel_stateless_geneve_rx[0x1]; 721 722 u8 reserved_at_40[0x10]; 723 u8 lro_min_mss_size[0x10]; 724 725 u8 reserved_at_60[0x120]; 726 727 u8 lro_timer_supported_periods[4][0x20]; 728 729 u8 reserved_at_200[0x600]; 730 }; 731 732 struct mlx5_ifc_roce_cap_bits { 733 u8 roce_apm[0x1]; 734 u8 reserved_at_1[0x1f]; 735 736 u8 reserved_at_20[0x60]; 737 738 u8 reserved_at_80[0xc]; 739 u8 l3_type[0x4]; 740 u8 reserved_at_90[0x8]; 741 u8 roce_version[0x8]; 742 743 u8 reserved_at_a0[0x10]; 744 u8 r_roce_dest_udp_port[0x10]; 745 746 u8 r_roce_max_src_udp_port[0x10]; 747 u8 r_roce_min_src_udp_port[0x10]; 748 749 u8 reserved_at_e0[0x10]; 750 u8 roce_address_table_size[0x10]; 751 752 u8 reserved_at_100[0x700]; 753 }; 754 755 struct mlx5_ifc_device_mem_cap_bits { 756 u8 memic[0x1]; 757 u8 reserved_at_1[0x1f]; 758 759 u8 reserved_at_20[0xb]; 760 u8 log_min_memic_alloc_size[0x5]; 761 u8 reserved_at_30[0x8]; 762 u8 log_max_memic_addr_alignment[0x8]; 763 764 u8 memic_bar_start_addr[0x40]; 765 766 u8 memic_bar_size[0x20]; 767 768 u8 max_memic_size[0x20]; 769 770 u8 reserved_at_c0[0x740]; 771 }; 772 773 enum { 774 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 775 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 776 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 777 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 778 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 779 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 780 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 781 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 782 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 783 }; 784 785 enum { 786 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 787 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 788 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 789 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 790 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 791 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 792 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 793 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 794 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 795 }; 796 797 struct mlx5_ifc_atomic_caps_bits { 798 u8 reserved_at_0[0x40]; 799 800 u8 atomic_req_8B_endianness_mode[0x2]; 801 u8 reserved_at_42[0x4]; 802 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 803 804 u8 reserved_at_47[0x19]; 805 806 u8 reserved_at_60[0x20]; 807 808 u8 reserved_at_80[0x10]; 809 u8 atomic_operations[0x10]; 810 811 u8 reserved_at_a0[0x10]; 812 u8 atomic_size_qp[0x10]; 813 814 u8 reserved_at_c0[0x10]; 815 u8 atomic_size_dc[0x10]; 816 817 u8 reserved_at_e0[0x720]; 818 }; 819 820 struct mlx5_ifc_odp_cap_bits { 821 u8 reserved_at_0[0x40]; 822 823 u8 sig[0x1]; 824 u8 reserved_at_41[0x1f]; 825 826 u8 reserved_at_60[0x20]; 827 828 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 829 830 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 831 832 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 833 834 u8 reserved_at_e0[0x720]; 835 }; 836 837 struct mlx5_ifc_calc_op { 838 u8 reserved_at_0[0x10]; 839 u8 reserved_at_10[0x9]; 840 u8 op_swap_endianness[0x1]; 841 u8 op_min[0x1]; 842 u8 op_xor[0x1]; 843 u8 op_or[0x1]; 844 u8 op_and[0x1]; 845 u8 op_max[0x1]; 846 u8 op_add[0x1]; 847 }; 848 849 struct mlx5_ifc_vector_calc_cap_bits { 850 u8 calc_matrix[0x1]; 851 u8 reserved_at_1[0x1f]; 852 u8 reserved_at_20[0x8]; 853 u8 max_vec_count[0x8]; 854 u8 reserved_at_30[0xd]; 855 u8 max_chunk_size[0x3]; 856 struct mlx5_ifc_calc_op calc0; 857 struct mlx5_ifc_calc_op calc1; 858 struct mlx5_ifc_calc_op calc2; 859 struct mlx5_ifc_calc_op calc3; 860 861 u8 reserved_at_c0[0x720]; 862 }; 863 864 enum { 865 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 866 MLX5_WQ_TYPE_CYCLIC = 0x1, 867 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 868 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 869 }; 870 871 enum { 872 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 873 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 874 }; 875 876 enum { 877 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 878 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 879 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 880 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 881 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 882 }; 883 884 enum { 885 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 886 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 887 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 888 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 889 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 890 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 891 }; 892 893 enum { 894 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 895 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 896 }; 897 898 enum { 899 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 900 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 901 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 902 }; 903 904 enum { 905 MLX5_CAP_PORT_TYPE_IB = 0x0, 906 MLX5_CAP_PORT_TYPE_ETH = 0x1, 907 }; 908 909 enum { 910 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 911 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 912 MLX5_CAP_UMR_FENCE_NONE = 0x2, 913 }; 914 915 enum { 916 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 917 }; 918 919 struct mlx5_ifc_cmd_hca_cap_bits { 920 u8 reserved_at_0[0x30]; 921 u8 vhca_id[0x10]; 922 923 u8 reserved_at_40[0x40]; 924 925 u8 log_max_srq_sz[0x8]; 926 u8 log_max_qp_sz[0x8]; 927 u8 reserved_at_90[0xb]; 928 u8 log_max_qp[0x5]; 929 930 u8 reserved_at_a0[0xb]; 931 u8 log_max_srq[0x5]; 932 u8 reserved_at_b0[0x10]; 933 934 u8 reserved_at_c0[0x8]; 935 u8 log_max_cq_sz[0x8]; 936 u8 reserved_at_d0[0xb]; 937 u8 log_max_cq[0x5]; 938 939 u8 log_max_eq_sz[0x8]; 940 u8 reserved_at_e8[0x2]; 941 u8 log_max_mkey[0x6]; 942 u8 reserved_at_f0[0x8]; 943 u8 dump_fill_mkey[0x1]; 944 u8 reserved_at_f9[0x2]; 945 u8 fast_teardown[0x1]; 946 u8 log_max_eq[0x4]; 947 948 u8 max_indirection[0x8]; 949 u8 fixed_buffer_size[0x1]; 950 u8 log_max_mrw_sz[0x7]; 951 u8 force_teardown[0x1]; 952 u8 reserved_at_111[0x1]; 953 u8 log_max_bsf_list_size[0x6]; 954 u8 umr_extended_translation_offset[0x1]; 955 u8 null_mkey[0x1]; 956 u8 log_max_klm_list_size[0x6]; 957 958 u8 reserved_at_120[0xa]; 959 u8 log_max_ra_req_dc[0x6]; 960 u8 reserved_at_130[0xa]; 961 u8 log_max_ra_res_dc[0x6]; 962 963 u8 reserved_at_140[0xa]; 964 u8 log_max_ra_req_qp[0x6]; 965 u8 reserved_at_150[0xa]; 966 u8 log_max_ra_res_qp[0x6]; 967 968 u8 end_pad[0x1]; 969 u8 cc_query_allowed[0x1]; 970 u8 cc_modify_allowed[0x1]; 971 u8 start_pad[0x1]; 972 u8 cache_line_128byte[0x1]; 973 u8 reserved_at_165[0xa]; 974 u8 qcam_reg[0x1]; 975 u8 gid_table_size[0x10]; 976 977 u8 out_of_seq_cnt[0x1]; 978 u8 vport_counters[0x1]; 979 u8 retransmission_q_counters[0x1]; 980 u8 debug[0x1]; 981 u8 modify_rq_counter_set_id[0x1]; 982 u8 rq_delay_drop[0x1]; 983 u8 max_qp_cnt[0xa]; 984 u8 pkey_table_size[0x10]; 985 986 u8 vport_group_manager[0x1]; 987 u8 vhca_group_manager[0x1]; 988 u8 ib_virt[0x1]; 989 u8 eth_virt[0x1]; 990 u8 vnic_env_queue_counters[0x1]; 991 u8 ets[0x1]; 992 u8 nic_flow_table[0x1]; 993 u8 eswitch_manager[0x1]; 994 u8 device_memory[0x1]; 995 u8 mcam_reg[0x1]; 996 u8 pcam_reg[0x1]; 997 u8 local_ca_ack_delay[0x5]; 998 u8 port_module_event[0x1]; 999 u8 enhanced_error_q_counters[0x1]; 1000 u8 ports_check[0x1]; 1001 u8 reserved_at_1b3[0x1]; 1002 u8 disable_link_up[0x1]; 1003 u8 beacon_led[0x1]; 1004 u8 port_type[0x2]; 1005 u8 num_ports[0x8]; 1006 1007 u8 reserved_at_1c0[0x1]; 1008 u8 pps[0x1]; 1009 u8 pps_modify[0x1]; 1010 u8 log_max_msg[0x5]; 1011 u8 reserved_at_1c8[0x4]; 1012 u8 max_tc[0x4]; 1013 u8 temp_warn_event[0x1]; 1014 u8 dcbx[0x1]; 1015 u8 general_notification_event[0x1]; 1016 u8 reserved_at_1d3[0x2]; 1017 u8 fpga[0x1]; 1018 u8 rol_s[0x1]; 1019 u8 rol_g[0x1]; 1020 u8 reserved_at_1d8[0x1]; 1021 u8 wol_s[0x1]; 1022 u8 wol_g[0x1]; 1023 u8 wol_a[0x1]; 1024 u8 wol_b[0x1]; 1025 u8 wol_m[0x1]; 1026 u8 wol_u[0x1]; 1027 u8 wol_p[0x1]; 1028 1029 u8 stat_rate_support[0x10]; 1030 u8 reserved_at_1f0[0xc]; 1031 u8 cqe_version[0x4]; 1032 1033 u8 compact_address_vector[0x1]; 1034 u8 striding_rq[0x1]; 1035 u8 reserved_at_202[0x1]; 1036 u8 ipoib_enhanced_offloads[0x1]; 1037 u8 ipoib_basic_offloads[0x1]; 1038 u8 reserved_at_205[0x1]; 1039 u8 repeated_block_disabled[0x1]; 1040 u8 umr_modify_entity_size_disabled[0x1]; 1041 u8 umr_modify_atomic_disabled[0x1]; 1042 u8 umr_indirect_mkey_disabled[0x1]; 1043 u8 umr_fence[0x2]; 1044 u8 dc_req_scat_data_cqe[0x1]; 1045 u8 reserved_at_20d[0x2]; 1046 u8 drain_sigerr[0x1]; 1047 u8 cmdif_checksum[0x2]; 1048 u8 sigerr_cqe[0x1]; 1049 u8 reserved_at_213[0x1]; 1050 u8 wq_signature[0x1]; 1051 u8 sctr_data_cqe[0x1]; 1052 u8 reserved_at_216[0x1]; 1053 u8 sho[0x1]; 1054 u8 tph[0x1]; 1055 u8 rf[0x1]; 1056 u8 dct[0x1]; 1057 u8 qos[0x1]; 1058 u8 eth_net_offloads[0x1]; 1059 u8 roce[0x1]; 1060 u8 atomic[0x1]; 1061 u8 reserved_at_21f[0x1]; 1062 1063 u8 cq_oi[0x1]; 1064 u8 cq_resize[0x1]; 1065 u8 cq_moderation[0x1]; 1066 u8 reserved_at_223[0x3]; 1067 u8 cq_eq_remap[0x1]; 1068 u8 pg[0x1]; 1069 u8 block_lb_mc[0x1]; 1070 u8 reserved_at_229[0x1]; 1071 u8 scqe_break_moderation[0x1]; 1072 u8 cq_period_start_from_cqe[0x1]; 1073 u8 cd[0x1]; 1074 u8 reserved_at_22d[0x1]; 1075 u8 apm[0x1]; 1076 u8 vector_calc[0x1]; 1077 u8 umr_ptr_rlky[0x1]; 1078 u8 imaicl[0x1]; 1079 u8 qp_packet_based[0x1]; 1080 u8 reserved_at_233[0x3]; 1081 u8 qkv[0x1]; 1082 u8 pkv[0x1]; 1083 u8 set_deth_sqpn[0x1]; 1084 u8 reserved_at_239[0x3]; 1085 u8 xrc[0x1]; 1086 u8 ud[0x1]; 1087 u8 uc[0x1]; 1088 u8 rc[0x1]; 1089 1090 u8 uar_4k[0x1]; 1091 u8 reserved_at_241[0x9]; 1092 u8 uar_sz[0x6]; 1093 u8 reserved_at_250[0x8]; 1094 u8 log_pg_sz[0x8]; 1095 1096 u8 bf[0x1]; 1097 u8 driver_version[0x1]; 1098 u8 pad_tx_eth_packet[0x1]; 1099 u8 reserved_at_263[0x8]; 1100 u8 log_bf_reg_size[0x5]; 1101 1102 u8 reserved_at_270[0xb]; 1103 u8 lag_master[0x1]; 1104 u8 num_lag_ports[0x4]; 1105 1106 u8 reserved_at_280[0x10]; 1107 u8 max_wqe_sz_sq[0x10]; 1108 1109 u8 reserved_at_2a0[0x10]; 1110 u8 max_wqe_sz_rq[0x10]; 1111 1112 u8 max_flow_counter_31_16[0x10]; 1113 u8 max_wqe_sz_sq_dc[0x10]; 1114 1115 u8 reserved_at_2e0[0x7]; 1116 u8 max_qp_mcg[0x19]; 1117 1118 u8 reserved_at_300[0x18]; 1119 u8 log_max_mcg[0x8]; 1120 1121 u8 reserved_at_320[0x3]; 1122 u8 log_max_transport_domain[0x5]; 1123 u8 reserved_at_328[0x3]; 1124 u8 log_max_pd[0x5]; 1125 u8 reserved_at_330[0xb]; 1126 u8 log_max_xrcd[0x5]; 1127 1128 u8 nic_receive_steering_discard[0x1]; 1129 u8 receive_discard_vport_down[0x1]; 1130 u8 transmit_discard_vport_down[0x1]; 1131 u8 reserved_at_343[0x5]; 1132 u8 log_max_flow_counter_bulk[0x8]; 1133 u8 max_flow_counter_15_0[0x10]; 1134 1135 1136 u8 reserved_at_360[0x3]; 1137 u8 log_max_rq[0x5]; 1138 u8 reserved_at_368[0x3]; 1139 u8 log_max_sq[0x5]; 1140 u8 reserved_at_370[0x3]; 1141 u8 log_max_tir[0x5]; 1142 u8 reserved_at_378[0x3]; 1143 u8 log_max_tis[0x5]; 1144 1145 u8 basic_cyclic_rcv_wqe[0x1]; 1146 u8 reserved_at_381[0x2]; 1147 u8 log_max_rmp[0x5]; 1148 u8 reserved_at_388[0x3]; 1149 u8 log_max_rqt[0x5]; 1150 u8 reserved_at_390[0x3]; 1151 u8 log_max_rqt_size[0x5]; 1152 u8 reserved_at_398[0x3]; 1153 u8 log_max_tis_per_sq[0x5]; 1154 1155 u8 ext_stride_num_range[0x1]; 1156 u8 reserved_at_3a1[0x2]; 1157 u8 log_max_stride_sz_rq[0x5]; 1158 u8 reserved_at_3a8[0x3]; 1159 u8 log_min_stride_sz_rq[0x5]; 1160 u8 reserved_at_3b0[0x3]; 1161 u8 log_max_stride_sz_sq[0x5]; 1162 u8 reserved_at_3b8[0x3]; 1163 u8 log_min_stride_sz_sq[0x5]; 1164 1165 u8 hairpin[0x1]; 1166 u8 reserved_at_3c1[0x2]; 1167 u8 log_max_hairpin_queues[0x5]; 1168 u8 reserved_at_3c8[0x3]; 1169 u8 log_max_hairpin_wq_data_sz[0x5]; 1170 u8 reserved_at_3d0[0x3]; 1171 u8 log_max_hairpin_num_packets[0x5]; 1172 u8 reserved_at_3d8[0x3]; 1173 u8 log_max_wq_sz[0x5]; 1174 1175 u8 nic_vport_change_event[0x1]; 1176 u8 disable_local_lb_uc[0x1]; 1177 u8 disable_local_lb_mc[0x1]; 1178 u8 log_min_hairpin_wq_data_sz[0x5]; 1179 u8 reserved_at_3e8[0x3]; 1180 u8 log_max_vlan_list[0x5]; 1181 u8 reserved_at_3f0[0x3]; 1182 u8 log_max_current_mc_list[0x5]; 1183 u8 reserved_at_3f8[0x3]; 1184 u8 log_max_current_uc_list[0x5]; 1185 1186 u8 general_obj_types[0x40]; 1187 1188 u8 reserved_at_440[0x20]; 1189 1190 u8 reserved_at_460[0x3]; 1191 u8 log_max_uctx[0x5]; 1192 u8 reserved_at_468[0x3]; 1193 u8 log_max_umem[0x5]; 1194 u8 max_num_eqs[0x10]; 1195 1196 u8 reserved_at_480[0x3]; 1197 u8 log_max_l2_table[0x5]; 1198 u8 reserved_at_488[0x8]; 1199 u8 log_uar_page_sz[0x10]; 1200 1201 u8 reserved_at_4a0[0x20]; 1202 u8 device_frequency_mhz[0x20]; 1203 u8 device_frequency_khz[0x20]; 1204 1205 u8 reserved_at_500[0x20]; 1206 u8 num_of_uars_per_page[0x20]; 1207 1208 u8 flex_parser_protocols[0x20]; 1209 u8 reserved_at_560[0x20]; 1210 1211 u8 reserved_at_580[0x3c]; 1212 u8 mini_cqe_resp_stride_index[0x1]; 1213 u8 cqe_128_always[0x1]; 1214 u8 cqe_compression_128[0x1]; 1215 u8 cqe_compression[0x1]; 1216 1217 u8 cqe_compression_timeout[0x10]; 1218 u8 cqe_compression_max_num[0x10]; 1219 1220 u8 reserved_at_5e0[0x10]; 1221 u8 tag_matching[0x1]; 1222 u8 rndv_offload_rc[0x1]; 1223 u8 rndv_offload_dc[0x1]; 1224 u8 log_tag_matching_list_sz[0x5]; 1225 u8 reserved_at_5f8[0x3]; 1226 u8 log_max_xrq[0x5]; 1227 1228 u8 affiliate_nic_vport_criteria[0x8]; 1229 u8 native_port_num[0x8]; 1230 u8 num_vhca_ports[0x8]; 1231 u8 reserved_at_618[0x6]; 1232 u8 sw_owner_id[0x1]; 1233 u8 reserved_at_61f[0x1]; 1234 1235 u8 max_num_of_monitor_counters[0x10]; 1236 u8 num_ppcnt_monitor_counters[0x10]; 1237 1238 u8 reserved_at_640[0x10]; 1239 u8 num_q_monitor_counters[0x10]; 1240 1241 u8 reserved_at_660[0x40]; 1242 1243 u8 uctx_cap[0x20]; 1244 1245 u8 reserved_at_6c0[0x140]; 1246 }; 1247 1248 enum mlx5_flow_destination_type { 1249 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1250 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1251 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1252 1253 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1254 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1255 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1256 }; 1257 1258 struct mlx5_ifc_dest_format_struct_bits { 1259 u8 destination_type[0x8]; 1260 u8 destination_id[0x18]; 1261 1262 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1263 u8 packet_reformat[0x1]; 1264 u8 reserved_at_22[0xe]; 1265 u8 destination_eswitch_owner_vhca_id[0x10]; 1266 }; 1267 1268 struct mlx5_ifc_flow_counter_list_bits { 1269 u8 flow_counter_id[0x20]; 1270 1271 u8 reserved_at_20[0x20]; 1272 }; 1273 1274 struct mlx5_ifc_extended_dest_format_bits { 1275 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1276 1277 u8 packet_reformat_id[0x20]; 1278 1279 u8 reserved_at_60[0x20]; 1280 }; 1281 1282 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1283 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1284 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1285 u8 reserved_at_0[0x40]; 1286 }; 1287 1288 struct mlx5_ifc_fte_match_param_bits { 1289 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1290 1291 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1292 1293 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1294 1295 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1296 1297 u8 reserved_at_800[0x800]; 1298 }; 1299 1300 enum { 1301 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1302 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1303 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1304 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1305 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1306 }; 1307 1308 struct mlx5_ifc_rx_hash_field_select_bits { 1309 u8 l3_prot_type[0x1]; 1310 u8 l4_prot_type[0x1]; 1311 u8 selected_fields[0x1e]; 1312 }; 1313 1314 enum { 1315 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1316 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1317 }; 1318 1319 enum { 1320 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1321 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1322 }; 1323 1324 struct mlx5_ifc_wq_bits { 1325 u8 wq_type[0x4]; 1326 u8 wq_signature[0x1]; 1327 u8 end_padding_mode[0x2]; 1328 u8 cd_slave[0x1]; 1329 u8 reserved_at_8[0x18]; 1330 1331 u8 hds_skip_first_sge[0x1]; 1332 u8 log2_hds_buf_size[0x3]; 1333 u8 reserved_at_24[0x7]; 1334 u8 page_offset[0x5]; 1335 u8 lwm[0x10]; 1336 1337 u8 reserved_at_40[0x8]; 1338 u8 pd[0x18]; 1339 1340 u8 reserved_at_60[0x8]; 1341 u8 uar_page[0x18]; 1342 1343 u8 dbr_addr[0x40]; 1344 1345 u8 hw_counter[0x20]; 1346 1347 u8 sw_counter[0x20]; 1348 1349 u8 reserved_at_100[0xc]; 1350 u8 log_wq_stride[0x4]; 1351 u8 reserved_at_110[0x3]; 1352 u8 log_wq_pg_sz[0x5]; 1353 u8 reserved_at_118[0x3]; 1354 u8 log_wq_sz[0x5]; 1355 1356 u8 dbr_umem_valid[0x1]; 1357 u8 wq_umem_valid[0x1]; 1358 u8 reserved_at_122[0x1]; 1359 u8 log_hairpin_num_packets[0x5]; 1360 u8 reserved_at_128[0x3]; 1361 u8 log_hairpin_data_sz[0x5]; 1362 1363 u8 reserved_at_130[0x4]; 1364 u8 log_wqe_num_of_strides[0x4]; 1365 u8 two_byte_shift_en[0x1]; 1366 u8 reserved_at_139[0x4]; 1367 u8 log_wqe_stride_size[0x3]; 1368 1369 u8 reserved_at_140[0x4c0]; 1370 1371 struct mlx5_ifc_cmd_pas_bits pas[0]; 1372 }; 1373 1374 struct mlx5_ifc_rq_num_bits { 1375 u8 reserved_at_0[0x8]; 1376 u8 rq_num[0x18]; 1377 }; 1378 1379 struct mlx5_ifc_mac_address_layout_bits { 1380 u8 reserved_at_0[0x10]; 1381 u8 mac_addr_47_32[0x10]; 1382 1383 u8 mac_addr_31_0[0x20]; 1384 }; 1385 1386 struct mlx5_ifc_vlan_layout_bits { 1387 u8 reserved_at_0[0x14]; 1388 u8 vlan[0x0c]; 1389 1390 u8 reserved_at_20[0x20]; 1391 }; 1392 1393 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1394 u8 reserved_at_0[0xa0]; 1395 1396 u8 min_time_between_cnps[0x20]; 1397 1398 u8 reserved_at_c0[0x12]; 1399 u8 cnp_dscp[0x6]; 1400 u8 reserved_at_d8[0x4]; 1401 u8 cnp_prio_mode[0x1]; 1402 u8 cnp_802p_prio[0x3]; 1403 1404 u8 reserved_at_e0[0x720]; 1405 }; 1406 1407 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1408 u8 reserved_at_0[0x60]; 1409 1410 u8 reserved_at_60[0x4]; 1411 u8 clamp_tgt_rate[0x1]; 1412 u8 reserved_at_65[0x3]; 1413 u8 clamp_tgt_rate_after_time_inc[0x1]; 1414 u8 reserved_at_69[0x17]; 1415 1416 u8 reserved_at_80[0x20]; 1417 1418 u8 rpg_time_reset[0x20]; 1419 1420 u8 rpg_byte_reset[0x20]; 1421 1422 u8 rpg_threshold[0x20]; 1423 1424 u8 rpg_max_rate[0x20]; 1425 1426 u8 rpg_ai_rate[0x20]; 1427 1428 u8 rpg_hai_rate[0x20]; 1429 1430 u8 rpg_gd[0x20]; 1431 1432 u8 rpg_min_dec_fac[0x20]; 1433 1434 u8 rpg_min_rate[0x20]; 1435 1436 u8 reserved_at_1c0[0xe0]; 1437 1438 u8 rate_to_set_on_first_cnp[0x20]; 1439 1440 u8 dce_tcp_g[0x20]; 1441 1442 u8 dce_tcp_rtt[0x20]; 1443 1444 u8 rate_reduce_monitor_period[0x20]; 1445 1446 u8 reserved_at_320[0x20]; 1447 1448 u8 initial_alpha_value[0x20]; 1449 1450 u8 reserved_at_360[0x4a0]; 1451 }; 1452 1453 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1454 u8 reserved_at_0[0x80]; 1455 1456 u8 rppp_max_rps[0x20]; 1457 1458 u8 rpg_time_reset[0x20]; 1459 1460 u8 rpg_byte_reset[0x20]; 1461 1462 u8 rpg_threshold[0x20]; 1463 1464 u8 rpg_max_rate[0x20]; 1465 1466 u8 rpg_ai_rate[0x20]; 1467 1468 u8 rpg_hai_rate[0x20]; 1469 1470 u8 rpg_gd[0x20]; 1471 1472 u8 rpg_min_dec_fac[0x20]; 1473 1474 u8 rpg_min_rate[0x20]; 1475 1476 u8 reserved_at_1c0[0x640]; 1477 }; 1478 1479 enum { 1480 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1481 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1482 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1483 }; 1484 1485 struct mlx5_ifc_resize_field_select_bits { 1486 u8 resize_field_select[0x20]; 1487 }; 1488 1489 enum { 1490 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1491 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1492 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1493 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1494 }; 1495 1496 struct mlx5_ifc_modify_field_select_bits { 1497 u8 modify_field_select[0x20]; 1498 }; 1499 1500 struct mlx5_ifc_field_select_r_roce_np_bits { 1501 u8 field_select_r_roce_np[0x20]; 1502 }; 1503 1504 struct mlx5_ifc_field_select_r_roce_rp_bits { 1505 u8 field_select_r_roce_rp[0x20]; 1506 }; 1507 1508 enum { 1509 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1510 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1511 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1512 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1513 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1514 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1515 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1516 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1517 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1518 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1519 }; 1520 1521 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1522 u8 field_select_8021qaurp[0x20]; 1523 }; 1524 1525 struct mlx5_ifc_phys_layer_cntrs_bits { 1526 u8 time_since_last_clear_high[0x20]; 1527 1528 u8 time_since_last_clear_low[0x20]; 1529 1530 u8 symbol_errors_high[0x20]; 1531 1532 u8 symbol_errors_low[0x20]; 1533 1534 u8 sync_headers_errors_high[0x20]; 1535 1536 u8 sync_headers_errors_low[0x20]; 1537 1538 u8 edpl_bip_errors_lane0_high[0x20]; 1539 1540 u8 edpl_bip_errors_lane0_low[0x20]; 1541 1542 u8 edpl_bip_errors_lane1_high[0x20]; 1543 1544 u8 edpl_bip_errors_lane1_low[0x20]; 1545 1546 u8 edpl_bip_errors_lane2_high[0x20]; 1547 1548 u8 edpl_bip_errors_lane2_low[0x20]; 1549 1550 u8 edpl_bip_errors_lane3_high[0x20]; 1551 1552 u8 edpl_bip_errors_lane3_low[0x20]; 1553 1554 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1555 1556 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1557 1558 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1559 1560 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1561 1562 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1563 1564 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1565 1566 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1567 1568 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1569 1570 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1571 1572 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1573 1574 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1575 1576 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1577 1578 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1579 1580 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1581 1582 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1583 1584 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1585 1586 u8 rs_fec_corrected_blocks_high[0x20]; 1587 1588 u8 rs_fec_corrected_blocks_low[0x20]; 1589 1590 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1591 1592 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1593 1594 u8 rs_fec_no_errors_blocks_high[0x20]; 1595 1596 u8 rs_fec_no_errors_blocks_low[0x20]; 1597 1598 u8 rs_fec_single_error_blocks_high[0x20]; 1599 1600 u8 rs_fec_single_error_blocks_low[0x20]; 1601 1602 u8 rs_fec_corrected_symbols_total_high[0x20]; 1603 1604 u8 rs_fec_corrected_symbols_total_low[0x20]; 1605 1606 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1607 1608 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1609 1610 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1611 1612 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1613 1614 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1615 1616 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1617 1618 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1619 1620 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1621 1622 u8 link_down_events[0x20]; 1623 1624 u8 successful_recovery_events[0x20]; 1625 1626 u8 reserved_at_640[0x180]; 1627 }; 1628 1629 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1630 u8 time_since_last_clear_high[0x20]; 1631 1632 u8 time_since_last_clear_low[0x20]; 1633 1634 u8 phy_received_bits_high[0x20]; 1635 1636 u8 phy_received_bits_low[0x20]; 1637 1638 u8 phy_symbol_errors_high[0x20]; 1639 1640 u8 phy_symbol_errors_low[0x20]; 1641 1642 u8 phy_corrected_bits_high[0x20]; 1643 1644 u8 phy_corrected_bits_low[0x20]; 1645 1646 u8 phy_corrected_bits_lane0_high[0x20]; 1647 1648 u8 phy_corrected_bits_lane0_low[0x20]; 1649 1650 u8 phy_corrected_bits_lane1_high[0x20]; 1651 1652 u8 phy_corrected_bits_lane1_low[0x20]; 1653 1654 u8 phy_corrected_bits_lane2_high[0x20]; 1655 1656 u8 phy_corrected_bits_lane2_low[0x20]; 1657 1658 u8 phy_corrected_bits_lane3_high[0x20]; 1659 1660 u8 phy_corrected_bits_lane3_low[0x20]; 1661 1662 u8 reserved_at_200[0x5c0]; 1663 }; 1664 1665 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1666 u8 symbol_error_counter[0x10]; 1667 1668 u8 link_error_recovery_counter[0x8]; 1669 1670 u8 link_downed_counter[0x8]; 1671 1672 u8 port_rcv_errors[0x10]; 1673 1674 u8 port_rcv_remote_physical_errors[0x10]; 1675 1676 u8 port_rcv_switch_relay_errors[0x10]; 1677 1678 u8 port_xmit_discards[0x10]; 1679 1680 u8 port_xmit_constraint_errors[0x8]; 1681 1682 u8 port_rcv_constraint_errors[0x8]; 1683 1684 u8 reserved_at_70[0x8]; 1685 1686 u8 link_overrun_errors[0x8]; 1687 1688 u8 reserved_at_80[0x10]; 1689 1690 u8 vl_15_dropped[0x10]; 1691 1692 u8 reserved_at_a0[0x80]; 1693 1694 u8 port_xmit_wait[0x20]; 1695 }; 1696 1697 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1698 u8 transmit_queue_high[0x20]; 1699 1700 u8 transmit_queue_low[0x20]; 1701 1702 u8 reserved_at_40[0x780]; 1703 }; 1704 1705 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1706 u8 rx_octets_high[0x20]; 1707 1708 u8 rx_octets_low[0x20]; 1709 1710 u8 reserved_at_40[0xc0]; 1711 1712 u8 rx_frames_high[0x20]; 1713 1714 u8 rx_frames_low[0x20]; 1715 1716 u8 tx_octets_high[0x20]; 1717 1718 u8 tx_octets_low[0x20]; 1719 1720 u8 reserved_at_180[0xc0]; 1721 1722 u8 tx_frames_high[0x20]; 1723 1724 u8 tx_frames_low[0x20]; 1725 1726 u8 rx_pause_high[0x20]; 1727 1728 u8 rx_pause_low[0x20]; 1729 1730 u8 rx_pause_duration_high[0x20]; 1731 1732 u8 rx_pause_duration_low[0x20]; 1733 1734 u8 tx_pause_high[0x20]; 1735 1736 u8 tx_pause_low[0x20]; 1737 1738 u8 tx_pause_duration_high[0x20]; 1739 1740 u8 tx_pause_duration_low[0x20]; 1741 1742 u8 rx_pause_transition_high[0x20]; 1743 1744 u8 rx_pause_transition_low[0x20]; 1745 1746 u8 reserved_at_3c0[0x40]; 1747 1748 u8 device_stall_minor_watermark_cnt_high[0x20]; 1749 1750 u8 device_stall_minor_watermark_cnt_low[0x20]; 1751 1752 u8 device_stall_critical_watermark_cnt_high[0x20]; 1753 1754 u8 device_stall_critical_watermark_cnt_low[0x20]; 1755 1756 u8 reserved_at_480[0x340]; 1757 }; 1758 1759 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1760 u8 port_transmit_wait_high[0x20]; 1761 1762 u8 port_transmit_wait_low[0x20]; 1763 1764 u8 reserved_at_40[0x100]; 1765 1766 u8 rx_buffer_almost_full_high[0x20]; 1767 1768 u8 rx_buffer_almost_full_low[0x20]; 1769 1770 u8 rx_buffer_full_high[0x20]; 1771 1772 u8 rx_buffer_full_low[0x20]; 1773 1774 u8 rx_icrc_encapsulated_high[0x20]; 1775 1776 u8 rx_icrc_encapsulated_low[0x20]; 1777 1778 u8 reserved_at_200[0x5c0]; 1779 }; 1780 1781 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1782 u8 dot3stats_alignment_errors_high[0x20]; 1783 1784 u8 dot3stats_alignment_errors_low[0x20]; 1785 1786 u8 dot3stats_fcs_errors_high[0x20]; 1787 1788 u8 dot3stats_fcs_errors_low[0x20]; 1789 1790 u8 dot3stats_single_collision_frames_high[0x20]; 1791 1792 u8 dot3stats_single_collision_frames_low[0x20]; 1793 1794 u8 dot3stats_multiple_collision_frames_high[0x20]; 1795 1796 u8 dot3stats_multiple_collision_frames_low[0x20]; 1797 1798 u8 dot3stats_sqe_test_errors_high[0x20]; 1799 1800 u8 dot3stats_sqe_test_errors_low[0x20]; 1801 1802 u8 dot3stats_deferred_transmissions_high[0x20]; 1803 1804 u8 dot3stats_deferred_transmissions_low[0x20]; 1805 1806 u8 dot3stats_late_collisions_high[0x20]; 1807 1808 u8 dot3stats_late_collisions_low[0x20]; 1809 1810 u8 dot3stats_excessive_collisions_high[0x20]; 1811 1812 u8 dot3stats_excessive_collisions_low[0x20]; 1813 1814 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1815 1816 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1817 1818 u8 dot3stats_carrier_sense_errors_high[0x20]; 1819 1820 u8 dot3stats_carrier_sense_errors_low[0x20]; 1821 1822 u8 dot3stats_frame_too_longs_high[0x20]; 1823 1824 u8 dot3stats_frame_too_longs_low[0x20]; 1825 1826 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1827 1828 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1829 1830 u8 dot3stats_symbol_errors_high[0x20]; 1831 1832 u8 dot3stats_symbol_errors_low[0x20]; 1833 1834 u8 dot3control_in_unknown_opcodes_high[0x20]; 1835 1836 u8 dot3control_in_unknown_opcodes_low[0x20]; 1837 1838 u8 dot3in_pause_frames_high[0x20]; 1839 1840 u8 dot3in_pause_frames_low[0x20]; 1841 1842 u8 dot3out_pause_frames_high[0x20]; 1843 1844 u8 dot3out_pause_frames_low[0x20]; 1845 1846 u8 reserved_at_400[0x3c0]; 1847 }; 1848 1849 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1850 u8 ether_stats_drop_events_high[0x20]; 1851 1852 u8 ether_stats_drop_events_low[0x20]; 1853 1854 u8 ether_stats_octets_high[0x20]; 1855 1856 u8 ether_stats_octets_low[0x20]; 1857 1858 u8 ether_stats_pkts_high[0x20]; 1859 1860 u8 ether_stats_pkts_low[0x20]; 1861 1862 u8 ether_stats_broadcast_pkts_high[0x20]; 1863 1864 u8 ether_stats_broadcast_pkts_low[0x20]; 1865 1866 u8 ether_stats_multicast_pkts_high[0x20]; 1867 1868 u8 ether_stats_multicast_pkts_low[0x20]; 1869 1870 u8 ether_stats_crc_align_errors_high[0x20]; 1871 1872 u8 ether_stats_crc_align_errors_low[0x20]; 1873 1874 u8 ether_stats_undersize_pkts_high[0x20]; 1875 1876 u8 ether_stats_undersize_pkts_low[0x20]; 1877 1878 u8 ether_stats_oversize_pkts_high[0x20]; 1879 1880 u8 ether_stats_oversize_pkts_low[0x20]; 1881 1882 u8 ether_stats_fragments_high[0x20]; 1883 1884 u8 ether_stats_fragments_low[0x20]; 1885 1886 u8 ether_stats_jabbers_high[0x20]; 1887 1888 u8 ether_stats_jabbers_low[0x20]; 1889 1890 u8 ether_stats_collisions_high[0x20]; 1891 1892 u8 ether_stats_collisions_low[0x20]; 1893 1894 u8 ether_stats_pkts64octets_high[0x20]; 1895 1896 u8 ether_stats_pkts64octets_low[0x20]; 1897 1898 u8 ether_stats_pkts65to127octets_high[0x20]; 1899 1900 u8 ether_stats_pkts65to127octets_low[0x20]; 1901 1902 u8 ether_stats_pkts128to255octets_high[0x20]; 1903 1904 u8 ether_stats_pkts128to255octets_low[0x20]; 1905 1906 u8 ether_stats_pkts256to511octets_high[0x20]; 1907 1908 u8 ether_stats_pkts256to511octets_low[0x20]; 1909 1910 u8 ether_stats_pkts512to1023octets_high[0x20]; 1911 1912 u8 ether_stats_pkts512to1023octets_low[0x20]; 1913 1914 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1915 1916 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1917 1918 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1919 1920 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1921 1922 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1923 1924 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1925 1926 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1927 1928 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1929 1930 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1931 1932 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1933 1934 u8 reserved_at_540[0x280]; 1935 }; 1936 1937 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1938 u8 if_in_octets_high[0x20]; 1939 1940 u8 if_in_octets_low[0x20]; 1941 1942 u8 if_in_ucast_pkts_high[0x20]; 1943 1944 u8 if_in_ucast_pkts_low[0x20]; 1945 1946 u8 if_in_discards_high[0x20]; 1947 1948 u8 if_in_discards_low[0x20]; 1949 1950 u8 if_in_errors_high[0x20]; 1951 1952 u8 if_in_errors_low[0x20]; 1953 1954 u8 if_in_unknown_protos_high[0x20]; 1955 1956 u8 if_in_unknown_protos_low[0x20]; 1957 1958 u8 if_out_octets_high[0x20]; 1959 1960 u8 if_out_octets_low[0x20]; 1961 1962 u8 if_out_ucast_pkts_high[0x20]; 1963 1964 u8 if_out_ucast_pkts_low[0x20]; 1965 1966 u8 if_out_discards_high[0x20]; 1967 1968 u8 if_out_discards_low[0x20]; 1969 1970 u8 if_out_errors_high[0x20]; 1971 1972 u8 if_out_errors_low[0x20]; 1973 1974 u8 if_in_multicast_pkts_high[0x20]; 1975 1976 u8 if_in_multicast_pkts_low[0x20]; 1977 1978 u8 if_in_broadcast_pkts_high[0x20]; 1979 1980 u8 if_in_broadcast_pkts_low[0x20]; 1981 1982 u8 if_out_multicast_pkts_high[0x20]; 1983 1984 u8 if_out_multicast_pkts_low[0x20]; 1985 1986 u8 if_out_broadcast_pkts_high[0x20]; 1987 1988 u8 if_out_broadcast_pkts_low[0x20]; 1989 1990 u8 reserved_at_340[0x480]; 1991 }; 1992 1993 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1994 u8 a_frames_transmitted_ok_high[0x20]; 1995 1996 u8 a_frames_transmitted_ok_low[0x20]; 1997 1998 u8 a_frames_received_ok_high[0x20]; 1999 2000 u8 a_frames_received_ok_low[0x20]; 2001 2002 u8 a_frame_check_sequence_errors_high[0x20]; 2003 2004 u8 a_frame_check_sequence_errors_low[0x20]; 2005 2006 u8 a_alignment_errors_high[0x20]; 2007 2008 u8 a_alignment_errors_low[0x20]; 2009 2010 u8 a_octets_transmitted_ok_high[0x20]; 2011 2012 u8 a_octets_transmitted_ok_low[0x20]; 2013 2014 u8 a_octets_received_ok_high[0x20]; 2015 2016 u8 a_octets_received_ok_low[0x20]; 2017 2018 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2019 2020 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2021 2022 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2023 2024 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2025 2026 u8 a_multicast_frames_received_ok_high[0x20]; 2027 2028 u8 a_multicast_frames_received_ok_low[0x20]; 2029 2030 u8 a_broadcast_frames_received_ok_high[0x20]; 2031 2032 u8 a_broadcast_frames_received_ok_low[0x20]; 2033 2034 u8 a_in_range_length_errors_high[0x20]; 2035 2036 u8 a_in_range_length_errors_low[0x20]; 2037 2038 u8 a_out_of_range_length_field_high[0x20]; 2039 2040 u8 a_out_of_range_length_field_low[0x20]; 2041 2042 u8 a_frame_too_long_errors_high[0x20]; 2043 2044 u8 a_frame_too_long_errors_low[0x20]; 2045 2046 u8 a_symbol_error_during_carrier_high[0x20]; 2047 2048 u8 a_symbol_error_during_carrier_low[0x20]; 2049 2050 u8 a_mac_control_frames_transmitted_high[0x20]; 2051 2052 u8 a_mac_control_frames_transmitted_low[0x20]; 2053 2054 u8 a_mac_control_frames_received_high[0x20]; 2055 2056 u8 a_mac_control_frames_received_low[0x20]; 2057 2058 u8 a_unsupported_opcodes_received_high[0x20]; 2059 2060 u8 a_unsupported_opcodes_received_low[0x20]; 2061 2062 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2063 2064 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2065 2066 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2067 2068 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2069 2070 u8 reserved_at_4c0[0x300]; 2071 }; 2072 2073 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2074 u8 life_time_counter_high[0x20]; 2075 2076 u8 life_time_counter_low[0x20]; 2077 2078 u8 rx_errors[0x20]; 2079 2080 u8 tx_errors[0x20]; 2081 2082 u8 l0_to_recovery_eieos[0x20]; 2083 2084 u8 l0_to_recovery_ts[0x20]; 2085 2086 u8 l0_to_recovery_framing[0x20]; 2087 2088 u8 l0_to_recovery_retrain[0x20]; 2089 2090 u8 crc_error_dllp[0x20]; 2091 2092 u8 crc_error_tlp[0x20]; 2093 2094 u8 tx_overflow_buffer_pkt_high[0x20]; 2095 2096 u8 tx_overflow_buffer_pkt_low[0x20]; 2097 2098 u8 outbound_stalled_reads[0x20]; 2099 2100 u8 outbound_stalled_writes[0x20]; 2101 2102 u8 outbound_stalled_reads_events[0x20]; 2103 2104 u8 outbound_stalled_writes_events[0x20]; 2105 2106 u8 reserved_at_200[0x5c0]; 2107 }; 2108 2109 struct mlx5_ifc_cmd_inter_comp_event_bits { 2110 u8 command_completion_vector[0x20]; 2111 2112 u8 reserved_at_20[0xc0]; 2113 }; 2114 2115 struct mlx5_ifc_stall_vl_event_bits { 2116 u8 reserved_at_0[0x18]; 2117 u8 port_num[0x1]; 2118 u8 reserved_at_19[0x3]; 2119 u8 vl[0x4]; 2120 2121 u8 reserved_at_20[0xa0]; 2122 }; 2123 2124 struct mlx5_ifc_db_bf_congestion_event_bits { 2125 u8 event_subtype[0x8]; 2126 u8 reserved_at_8[0x8]; 2127 u8 congestion_level[0x8]; 2128 u8 reserved_at_18[0x8]; 2129 2130 u8 reserved_at_20[0xa0]; 2131 }; 2132 2133 struct mlx5_ifc_gpio_event_bits { 2134 u8 reserved_at_0[0x60]; 2135 2136 u8 gpio_event_hi[0x20]; 2137 2138 u8 gpio_event_lo[0x20]; 2139 2140 u8 reserved_at_a0[0x40]; 2141 }; 2142 2143 struct mlx5_ifc_port_state_change_event_bits { 2144 u8 reserved_at_0[0x40]; 2145 2146 u8 port_num[0x4]; 2147 u8 reserved_at_44[0x1c]; 2148 2149 u8 reserved_at_60[0x80]; 2150 }; 2151 2152 struct mlx5_ifc_dropped_packet_logged_bits { 2153 u8 reserved_at_0[0xe0]; 2154 }; 2155 2156 enum { 2157 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2158 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2159 }; 2160 2161 struct mlx5_ifc_cq_error_bits { 2162 u8 reserved_at_0[0x8]; 2163 u8 cqn[0x18]; 2164 2165 u8 reserved_at_20[0x20]; 2166 2167 u8 reserved_at_40[0x18]; 2168 u8 syndrome[0x8]; 2169 2170 u8 reserved_at_60[0x80]; 2171 }; 2172 2173 struct mlx5_ifc_rdma_page_fault_event_bits { 2174 u8 bytes_committed[0x20]; 2175 2176 u8 r_key[0x20]; 2177 2178 u8 reserved_at_40[0x10]; 2179 u8 packet_len[0x10]; 2180 2181 u8 rdma_op_len[0x20]; 2182 2183 u8 rdma_va[0x40]; 2184 2185 u8 reserved_at_c0[0x5]; 2186 u8 rdma[0x1]; 2187 u8 write[0x1]; 2188 u8 requestor[0x1]; 2189 u8 qp_number[0x18]; 2190 }; 2191 2192 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2193 u8 bytes_committed[0x20]; 2194 2195 u8 reserved_at_20[0x10]; 2196 u8 wqe_index[0x10]; 2197 2198 u8 reserved_at_40[0x10]; 2199 u8 len[0x10]; 2200 2201 u8 reserved_at_60[0x60]; 2202 2203 u8 reserved_at_c0[0x5]; 2204 u8 rdma[0x1]; 2205 u8 write_read[0x1]; 2206 u8 requestor[0x1]; 2207 u8 qpn[0x18]; 2208 }; 2209 2210 struct mlx5_ifc_qp_events_bits { 2211 u8 reserved_at_0[0xa0]; 2212 2213 u8 type[0x8]; 2214 u8 reserved_at_a8[0x18]; 2215 2216 u8 reserved_at_c0[0x8]; 2217 u8 qpn_rqn_sqn[0x18]; 2218 }; 2219 2220 struct mlx5_ifc_dct_events_bits { 2221 u8 reserved_at_0[0xc0]; 2222 2223 u8 reserved_at_c0[0x8]; 2224 u8 dct_number[0x18]; 2225 }; 2226 2227 struct mlx5_ifc_comp_event_bits { 2228 u8 reserved_at_0[0xc0]; 2229 2230 u8 reserved_at_c0[0x8]; 2231 u8 cq_number[0x18]; 2232 }; 2233 2234 enum { 2235 MLX5_QPC_STATE_RST = 0x0, 2236 MLX5_QPC_STATE_INIT = 0x1, 2237 MLX5_QPC_STATE_RTR = 0x2, 2238 MLX5_QPC_STATE_RTS = 0x3, 2239 MLX5_QPC_STATE_SQER = 0x4, 2240 MLX5_QPC_STATE_ERR = 0x6, 2241 MLX5_QPC_STATE_SQD = 0x7, 2242 MLX5_QPC_STATE_SUSPENDED = 0x9, 2243 }; 2244 2245 enum { 2246 MLX5_QPC_ST_RC = 0x0, 2247 MLX5_QPC_ST_UC = 0x1, 2248 MLX5_QPC_ST_UD = 0x2, 2249 MLX5_QPC_ST_XRC = 0x3, 2250 MLX5_QPC_ST_DCI = 0x5, 2251 MLX5_QPC_ST_QP0 = 0x7, 2252 MLX5_QPC_ST_QP1 = 0x8, 2253 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2254 MLX5_QPC_ST_REG_UMR = 0xc, 2255 }; 2256 2257 enum { 2258 MLX5_QPC_PM_STATE_ARMED = 0x0, 2259 MLX5_QPC_PM_STATE_REARM = 0x1, 2260 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2261 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2262 }; 2263 2264 enum { 2265 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2266 }; 2267 2268 enum { 2269 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2270 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2271 }; 2272 2273 enum { 2274 MLX5_QPC_MTU_256_BYTES = 0x1, 2275 MLX5_QPC_MTU_512_BYTES = 0x2, 2276 MLX5_QPC_MTU_1K_BYTES = 0x3, 2277 MLX5_QPC_MTU_2K_BYTES = 0x4, 2278 MLX5_QPC_MTU_4K_BYTES = 0x5, 2279 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2280 }; 2281 2282 enum { 2283 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2284 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2285 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2286 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2287 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2288 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2289 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2290 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2291 }; 2292 2293 enum { 2294 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2295 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2296 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2297 }; 2298 2299 enum { 2300 MLX5_QPC_CS_RES_DISABLE = 0x0, 2301 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2302 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2303 }; 2304 2305 struct mlx5_ifc_qpc_bits { 2306 u8 state[0x4]; 2307 u8 lag_tx_port_affinity[0x4]; 2308 u8 st[0x8]; 2309 u8 reserved_at_10[0x3]; 2310 u8 pm_state[0x2]; 2311 u8 reserved_at_15[0x1]; 2312 u8 req_e2e_credit_mode[0x2]; 2313 u8 offload_type[0x4]; 2314 u8 end_padding_mode[0x2]; 2315 u8 reserved_at_1e[0x2]; 2316 2317 u8 wq_signature[0x1]; 2318 u8 block_lb_mc[0x1]; 2319 u8 atomic_like_write_en[0x1]; 2320 u8 latency_sensitive[0x1]; 2321 u8 reserved_at_24[0x1]; 2322 u8 drain_sigerr[0x1]; 2323 u8 reserved_at_26[0x2]; 2324 u8 pd[0x18]; 2325 2326 u8 mtu[0x3]; 2327 u8 log_msg_max[0x5]; 2328 u8 reserved_at_48[0x1]; 2329 u8 log_rq_size[0x4]; 2330 u8 log_rq_stride[0x3]; 2331 u8 no_sq[0x1]; 2332 u8 log_sq_size[0x4]; 2333 u8 reserved_at_55[0x6]; 2334 u8 rlky[0x1]; 2335 u8 ulp_stateless_offload_mode[0x4]; 2336 2337 u8 counter_set_id[0x8]; 2338 u8 uar_page[0x18]; 2339 2340 u8 reserved_at_80[0x8]; 2341 u8 user_index[0x18]; 2342 2343 u8 reserved_at_a0[0x3]; 2344 u8 log_page_size[0x5]; 2345 u8 remote_qpn[0x18]; 2346 2347 struct mlx5_ifc_ads_bits primary_address_path; 2348 2349 struct mlx5_ifc_ads_bits secondary_address_path; 2350 2351 u8 log_ack_req_freq[0x4]; 2352 u8 reserved_at_384[0x4]; 2353 u8 log_sra_max[0x3]; 2354 u8 reserved_at_38b[0x2]; 2355 u8 retry_count[0x3]; 2356 u8 rnr_retry[0x3]; 2357 u8 reserved_at_393[0x1]; 2358 u8 fre[0x1]; 2359 u8 cur_rnr_retry[0x3]; 2360 u8 cur_retry_count[0x3]; 2361 u8 reserved_at_39b[0x5]; 2362 2363 u8 reserved_at_3a0[0x20]; 2364 2365 u8 reserved_at_3c0[0x8]; 2366 u8 next_send_psn[0x18]; 2367 2368 u8 reserved_at_3e0[0x8]; 2369 u8 cqn_snd[0x18]; 2370 2371 u8 reserved_at_400[0x8]; 2372 u8 deth_sqpn[0x18]; 2373 2374 u8 reserved_at_420[0x20]; 2375 2376 u8 reserved_at_440[0x8]; 2377 u8 last_acked_psn[0x18]; 2378 2379 u8 reserved_at_460[0x8]; 2380 u8 ssn[0x18]; 2381 2382 u8 reserved_at_480[0x8]; 2383 u8 log_rra_max[0x3]; 2384 u8 reserved_at_48b[0x1]; 2385 u8 atomic_mode[0x4]; 2386 u8 rre[0x1]; 2387 u8 rwe[0x1]; 2388 u8 rae[0x1]; 2389 u8 reserved_at_493[0x1]; 2390 u8 page_offset[0x6]; 2391 u8 reserved_at_49a[0x3]; 2392 u8 cd_slave_receive[0x1]; 2393 u8 cd_slave_send[0x1]; 2394 u8 cd_master[0x1]; 2395 2396 u8 reserved_at_4a0[0x3]; 2397 u8 min_rnr_nak[0x5]; 2398 u8 next_rcv_psn[0x18]; 2399 2400 u8 reserved_at_4c0[0x8]; 2401 u8 xrcd[0x18]; 2402 2403 u8 reserved_at_4e0[0x8]; 2404 u8 cqn_rcv[0x18]; 2405 2406 u8 dbr_addr[0x40]; 2407 2408 u8 q_key[0x20]; 2409 2410 u8 reserved_at_560[0x5]; 2411 u8 rq_type[0x3]; 2412 u8 srqn_rmpn_xrqn[0x18]; 2413 2414 u8 reserved_at_580[0x8]; 2415 u8 rmsn[0x18]; 2416 2417 u8 hw_sq_wqebb_counter[0x10]; 2418 u8 sw_sq_wqebb_counter[0x10]; 2419 2420 u8 hw_rq_counter[0x20]; 2421 2422 u8 sw_rq_counter[0x20]; 2423 2424 u8 reserved_at_600[0x20]; 2425 2426 u8 reserved_at_620[0xf]; 2427 u8 cgs[0x1]; 2428 u8 cs_req[0x8]; 2429 u8 cs_res[0x8]; 2430 2431 u8 dc_access_key[0x40]; 2432 2433 u8 reserved_at_680[0x3]; 2434 u8 dbr_umem_valid[0x1]; 2435 2436 u8 reserved_at_684[0xbc]; 2437 }; 2438 2439 struct mlx5_ifc_roce_addr_layout_bits { 2440 u8 source_l3_address[16][0x8]; 2441 2442 u8 reserved_at_80[0x3]; 2443 u8 vlan_valid[0x1]; 2444 u8 vlan_id[0xc]; 2445 u8 source_mac_47_32[0x10]; 2446 2447 u8 source_mac_31_0[0x20]; 2448 2449 u8 reserved_at_c0[0x14]; 2450 u8 roce_l3_type[0x4]; 2451 u8 roce_version[0x8]; 2452 2453 u8 reserved_at_e0[0x20]; 2454 }; 2455 2456 union mlx5_ifc_hca_cap_union_bits { 2457 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2458 struct mlx5_ifc_odp_cap_bits odp_cap; 2459 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2460 struct mlx5_ifc_roce_cap_bits roce_cap; 2461 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2462 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2463 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2464 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2465 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2466 struct mlx5_ifc_qos_cap_bits qos_cap; 2467 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2468 u8 reserved_at_0[0x8000]; 2469 }; 2470 2471 enum { 2472 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2473 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2474 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2475 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2476 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2477 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2478 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2479 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2480 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2481 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2482 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2483 }; 2484 2485 struct mlx5_ifc_vlan_bits { 2486 u8 ethtype[0x10]; 2487 u8 prio[0x3]; 2488 u8 cfi[0x1]; 2489 u8 vid[0xc]; 2490 }; 2491 2492 struct mlx5_ifc_flow_context_bits { 2493 struct mlx5_ifc_vlan_bits push_vlan; 2494 2495 u8 group_id[0x20]; 2496 2497 u8 reserved_at_40[0x8]; 2498 u8 flow_tag[0x18]; 2499 2500 u8 reserved_at_60[0x10]; 2501 u8 action[0x10]; 2502 2503 u8 extended_destination[0x1]; 2504 u8 reserved_at_80[0x7]; 2505 u8 destination_list_size[0x18]; 2506 2507 u8 reserved_at_a0[0x8]; 2508 u8 flow_counter_list_size[0x18]; 2509 2510 u8 packet_reformat_id[0x20]; 2511 2512 u8 modify_header_id[0x20]; 2513 2514 struct mlx5_ifc_vlan_bits push_vlan_2; 2515 2516 u8 reserved_at_120[0xe0]; 2517 2518 struct mlx5_ifc_fte_match_param_bits match_value; 2519 2520 u8 reserved_at_1200[0x600]; 2521 2522 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2523 }; 2524 2525 enum { 2526 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2527 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2528 }; 2529 2530 struct mlx5_ifc_xrc_srqc_bits { 2531 u8 state[0x4]; 2532 u8 log_xrc_srq_size[0x4]; 2533 u8 reserved_at_8[0x18]; 2534 2535 u8 wq_signature[0x1]; 2536 u8 cont_srq[0x1]; 2537 u8 reserved_at_22[0x1]; 2538 u8 rlky[0x1]; 2539 u8 basic_cyclic_rcv_wqe[0x1]; 2540 u8 log_rq_stride[0x3]; 2541 u8 xrcd[0x18]; 2542 2543 u8 page_offset[0x6]; 2544 u8 reserved_at_46[0x1]; 2545 u8 dbr_umem_valid[0x1]; 2546 u8 cqn[0x18]; 2547 2548 u8 reserved_at_60[0x20]; 2549 2550 u8 user_index_equal_xrc_srqn[0x1]; 2551 u8 reserved_at_81[0x1]; 2552 u8 log_page_size[0x6]; 2553 u8 user_index[0x18]; 2554 2555 u8 reserved_at_a0[0x20]; 2556 2557 u8 reserved_at_c0[0x8]; 2558 u8 pd[0x18]; 2559 2560 u8 lwm[0x10]; 2561 u8 wqe_cnt[0x10]; 2562 2563 u8 reserved_at_100[0x40]; 2564 2565 u8 db_record_addr_h[0x20]; 2566 2567 u8 db_record_addr_l[0x1e]; 2568 u8 reserved_at_17e[0x2]; 2569 2570 u8 reserved_at_180[0x80]; 2571 }; 2572 2573 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2574 u8 counter_error_queues[0x20]; 2575 2576 u8 total_error_queues[0x20]; 2577 2578 u8 send_queue_priority_update_flow[0x20]; 2579 2580 u8 reserved_at_60[0x20]; 2581 2582 u8 nic_receive_steering_discard[0x40]; 2583 2584 u8 receive_discard_vport_down[0x40]; 2585 2586 u8 transmit_discard_vport_down[0x40]; 2587 2588 u8 reserved_at_140[0xec0]; 2589 }; 2590 2591 struct mlx5_ifc_traffic_counter_bits { 2592 u8 packets[0x40]; 2593 2594 u8 octets[0x40]; 2595 }; 2596 2597 struct mlx5_ifc_tisc_bits { 2598 u8 strict_lag_tx_port_affinity[0x1]; 2599 u8 reserved_at_1[0x3]; 2600 u8 lag_tx_port_affinity[0x04]; 2601 2602 u8 reserved_at_8[0x4]; 2603 u8 prio[0x4]; 2604 u8 reserved_at_10[0x10]; 2605 2606 u8 reserved_at_20[0x100]; 2607 2608 u8 reserved_at_120[0x8]; 2609 u8 transport_domain[0x18]; 2610 2611 u8 reserved_at_140[0x8]; 2612 u8 underlay_qpn[0x18]; 2613 u8 reserved_at_160[0x3a0]; 2614 }; 2615 2616 enum { 2617 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2618 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2619 }; 2620 2621 enum { 2622 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2623 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2624 }; 2625 2626 enum { 2627 MLX5_RX_HASH_FN_NONE = 0x0, 2628 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2629 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2630 }; 2631 2632 enum { 2633 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2634 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2635 }; 2636 2637 struct mlx5_ifc_tirc_bits { 2638 u8 reserved_at_0[0x20]; 2639 2640 u8 disp_type[0x4]; 2641 u8 reserved_at_24[0x1c]; 2642 2643 u8 reserved_at_40[0x40]; 2644 2645 u8 reserved_at_80[0x4]; 2646 u8 lro_timeout_period_usecs[0x10]; 2647 u8 lro_enable_mask[0x4]; 2648 u8 lro_max_ip_payload_size[0x8]; 2649 2650 u8 reserved_at_a0[0x40]; 2651 2652 u8 reserved_at_e0[0x8]; 2653 u8 inline_rqn[0x18]; 2654 2655 u8 rx_hash_symmetric[0x1]; 2656 u8 reserved_at_101[0x1]; 2657 u8 tunneled_offload_en[0x1]; 2658 u8 reserved_at_103[0x5]; 2659 u8 indirect_table[0x18]; 2660 2661 u8 rx_hash_fn[0x4]; 2662 u8 reserved_at_124[0x2]; 2663 u8 self_lb_block[0x2]; 2664 u8 transport_domain[0x18]; 2665 2666 u8 rx_hash_toeplitz_key[10][0x20]; 2667 2668 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2669 2670 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2671 2672 u8 reserved_at_2c0[0x4c0]; 2673 }; 2674 2675 enum { 2676 MLX5_SRQC_STATE_GOOD = 0x0, 2677 MLX5_SRQC_STATE_ERROR = 0x1, 2678 }; 2679 2680 struct mlx5_ifc_srqc_bits { 2681 u8 state[0x4]; 2682 u8 log_srq_size[0x4]; 2683 u8 reserved_at_8[0x18]; 2684 2685 u8 wq_signature[0x1]; 2686 u8 cont_srq[0x1]; 2687 u8 reserved_at_22[0x1]; 2688 u8 rlky[0x1]; 2689 u8 reserved_at_24[0x1]; 2690 u8 log_rq_stride[0x3]; 2691 u8 xrcd[0x18]; 2692 2693 u8 page_offset[0x6]; 2694 u8 reserved_at_46[0x2]; 2695 u8 cqn[0x18]; 2696 2697 u8 reserved_at_60[0x20]; 2698 2699 u8 reserved_at_80[0x2]; 2700 u8 log_page_size[0x6]; 2701 u8 reserved_at_88[0x18]; 2702 2703 u8 reserved_at_a0[0x20]; 2704 2705 u8 reserved_at_c0[0x8]; 2706 u8 pd[0x18]; 2707 2708 u8 lwm[0x10]; 2709 u8 wqe_cnt[0x10]; 2710 2711 u8 reserved_at_100[0x40]; 2712 2713 u8 dbr_addr[0x40]; 2714 2715 u8 reserved_at_180[0x80]; 2716 }; 2717 2718 enum { 2719 MLX5_SQC_STATE_RST = 0x0, 2720 MLX5_SQC_STATE_RDY = 0x1, 2721 MLX5_SQC_STATE_ERR = 0x3, 2722 }; 2723 2724 struct mlx5_ifc_sqc_bits { 2725 u8 rlky[0x1]; 2726 u8 cd_master[0x1]; 2727 u8 fre[0x1]; 2728 u8 flush_in_error_en[0x1]; 2729 u8 allow_multi_pkt_send_wqe[0x1]; 2730 u8 min_wqe_inline_mode[0x3]; 2731 u8 state[0x4]; 2732 u8 reg_umr[0x1]; 2733 u8 allow_swp[0x1]; 2734 u8 hairpin[0x1]; 2735 u8 reserved_at_f[0x11]; 2736 2737 u8 reserved_at_20[0x8]; 2738 u8 user_index[0x18]; 2739 2740 u8 reserved_at_40[0x8]; 2741 u8 cqn[0x18]; 2742 2743 u8 reserved_at_60[0x8]; 2744 u8 hairpin_peer_rq[0x18]; 2745 2746 u8 reserved_at_80[0x10]; 2747 u8 hairpin_peer_vhca[0x10]; 2748 2749 u8 reserved_at_a0[0x50]; 2750 2751 u8 packet_pacing_rate_limit_index[0x10]; 2752 u8 tis_lst_sz[0x10]; 2753 u8 reserved_at_110[0x10]; 2754 2755 u8 reserved_at_120[0x40]; 2756 2757 u8 reserved_at_160[0x8]; 2758 u8 tis_num_0[0x18]; 2759 2760 struct mlx5_ifc_wq_bits wq; 2761 }; 2762 2763 enum { 2764 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2765 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2766 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2767 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2768 }; 2769 2770 struct mlx5_ifc_scheduling_context_bits { 2771 u8 element_type[0x8]; 2772 u8 reserved_at_8[0x18]; 2773 2774 u8 element_attributes[0x20]; 2775 2776 u8 parent_element_id[0x20]; 2777 2778 u8 reserved_at_60[0x40]; 2779 2780 u8 bw_share[0x20]; 2781 2782 u8 max_average_bw[0x20]; 2783 2784 u8 reserved_at_e0[0x120]; 2785 }; 2786 2787 struct mlx5_ifc_rqtc_bits { 2788 u8 reserved_at_0[0xa0]; 2789 2790 u8 reserved_at_a0[0x10]; 2791 u8 rqt_max_size[0x10]; 2792 2793 u8 reserved_at_c0[0x10]; 2794 u8 rqt_actual_size[0x10]; 2795 2796 u8 reserved_at_e0[0x6a0]; 2797 2798 struct mlx5_ifc_rq_num_bits rq_num[0]; 2799 }; 2800 2801 enum { 2802 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2803 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2804 }; 2805 2806 enum { 2807 MLX5_RQC_STATE_RST = 0x0, 2808 MLX5_RQC_STATE_RDY = 0x1, 2809 MLX5_RQC_STATE_ERR = 0x3, 2810 }; 2811 2812 struct mlx5_ifc_rqc_bits { 2813 u8 rlky[0x1]; 2814 u8 delay_drop_en[0x1]; 2815 u8 scatter_fcs[0x1]; 2816 u8 vsd[0x1]; 2817 u8 mem_rq_type[0x4]; 2818 u8 state[0x4]; 2819 u8 reserved_at_c[0x1]; 2820 u8 flush_in_error_en[0x1]; 2821 u8 hairpin[0x1]; 2822 u8 reserved_at_f[0x11]; 2823 2824 u8 reserved_at_20[0x8]; 2825 u8 user_index[0x18]; 2826 2827 u8 reserved_at_40[0x8]; 2828 u8 cqn[0x18]; 2829 2830 u8 counter_set_id[0x8]; 2831 u8 reserved_at_68[0x18]; 2832 2833 u8 reserved_at_80[0x8]; 2834 u8 rmpn[0x18]; 2835 2836 u8 reserved_at_a0[0x8]; 2837 u8 hairpin_peer_sq[0x18]; 2838 2839 u8 reserved_at_c0[0x10]; 2840 u8 hairpin_peer_vhca[0x10]; 2841 2842 u8 reserved_at_e0[0xa0]; 2843 2844 struct mlx5_ifc_wq_bits wq; 2845 }; 2846 2847 enum { 2848 MLX5_RMPC_STATE_RDY = 0x1, 2849 MLX5_RMPC_STATE_ERR = 0x3, 2850 }; 2851 2852 struct mlx5_ifc_rmpc_bits { 2853 u8 reserved_at_0[0x8]; 2854 u8 state[0x4]; 2855 u8 reserved_at_c[0x14]; 2856 2857 u8 basic_cyclic_rcv_wqe[0x1]; 2858 u8 reserved_at_21[0x1f]; 2859 2860 u8 reserved_at_40[0x140]; 2861 2862 struct mlx5_ifc_wq_bits wq; 2863 }; 2864 2865 struct mlx5_ifc_nic_vport_context_bits { 2866 u8 reserved_at_0[0x5]; 2867 u8 min_wqe_inline_mode[0x3]; 2868 u8 reserved_at_8[0x15]; 2869 u8 disable_mc_local_lb[0x1]; 2870 u8 disable_uc_local_lb[0x1]; 2871 u8 roce_en[0x1]; 2872 2873 u8 arm_change_event[0x1]; 2874 u8 reserved_at_21[0x1a]; 2875 u8 event_on_mtu[0x1]; 2876 u8 event_on_promisc_change[0x1]; 2877 u8 event_on_vlan_change[0x1]; 2878 u8 event_on_mc_address_change[0x1]; 2879 u8 event_on_uc_address_change[0x1]; 2880 2881 u8 reserved_at_40[0xc]; 2882 2883 u8 affiliation_criteria[0x4]; 2884 u8 affiliated_vhca_id[0x10]; 2885 2886 u8 reserved_at_60[0xd0]; 2887 2888 u8 mtu[0x10]; 2889 2890 u8 system_image_guid[0x40]; 2891 u8 port_guid[0x40]; 2892 u8 node_guid[0x40]; 2893 2894 u8 reserved_at_200[0x140]; 2895 u8 qkey_violation_counter[0x10]; 2896 u8 reserved_at_350[0x430]; 2897 2898 u8 promisc_uc[0x1]; 2899 u8 promisc_mc[0x1]; 2900 u8 promisc_all[0x1]; 2901 u8 reserved_at_783[0x2]; 2902 u8 allowed_list_type[0x3]; 2903 u8 reserved_at_788[0xc]; 2904 u8 allowed_list_size[0xc]; 2905 2906 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2907 2908 u8 reserved_at_7e0[0x20]; 2909 2910 u8 current_uc_mac_address[0][0x40]; 2911 }; 2912 2913 enum { 2914 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2915 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2916 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2917 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2918 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2919 }; 2920 2921 struct mlx5_ifc_mkc_bits { 2922 u8 reserved_at_0[0x1]; 2923 u8 free[0x1]; 2924 u8 reserved_at_2[0x1]; 2925 u8 access_mode_4_2[0x3]; 2926 u8 reserved_at_6[0x7]; 2927 u8 relaxed_ordering_write[0x1]; 2928 u8 reserved_at_e[0x1]; 2929 u8 small_fence_on_rdma_read_response[0x1]; 2930 u8 umr_en[0x1]; 2931 u8 a[0x1]; 2932 u8 rw[0x1]; 2933 u8 rr[0x1]; 2934 u8 lw[0x1]; 2935 u8 lr[0x1]; 2936 u8 access_mode_1_0[0x2]; 2937 u8 reserved_at_18[0x8]; 2938 2939 u8 qpn[0x18]; 2940 u8 mkey_7_0[0x8]; 2941 2942 u8 reserved_at_40[0x20]; 2943 2944 u8 length64[0x1]; 2945 u8 bsf_en[0x1]; 2946 u8 sync_umr[0x1]; 2947 u8 reserved_at_63[0x2]; 2948 u8 expected_sigerr_count[0x1]; 2949 u8 reserved_at_66[0x1]; 2950 u8 en_rinval[0x1]; 2951 u8 pd[0x18]; 2952 2953 u8 start_addr[0x40]; 2954 2955 u8 len[0x40]; 2956 2957 u8 bsf_octword_size[0x20]; 2958 2959 u8 reserved_at_120[0x80]; 2960 2961 u8 translations_octword_size[0x20]; 2962 2963 u8 reserved_at_1c0[0x1b]; 2964 u8 log_page_size[0x5]; 2965 2966 u8 reserved_at_1e0[0x20]; 2967 }; 2968 2969 struct mlx5_ifc_pkey_bits { 2970 u8 reserved_at_0[0x10]; 2971 u8 pkey[0x10]; 2972 }; 2973 2974 struct mlx5_ifc_array128_auto_bits { 2975 u8 array128_auto[16][0x8]; 2976 }; 2977 2978 struct mlx5_ifc_hca_vport_context_bits { 2979 u8 field_select[0x20]; 2980 2981 u8 reserved_at_20[0xe0]; 2982 2983 u8 sm_virt_aware[0x1]; 2984 u8 has_smi[0x1]; 2985 u8 has_raw[0x1]; 2986 u8 grh_required[0x1]; 2987 u8 reserved_at_104[0xc]; 2988 u8 port_physical_state[0x4]; 2989 u8 vport_state_policy[0x4]; 2990 u8 port_state[0x4]; 2991 u8 vport_state[0x4]; 2992 2993 u8 reserved_at_120[0x20]; 2994 2995 u8 system_image_guid[0x40]; 2996 2997 u8 port_guid[0x40]; 2998 2999 u8 node_guid[0x40]; 3000 3001 u8 cap_mask1[0x20]; 3002 3003 u8 cap_mask1_field_select[0x20]; 3004 3005 u8 cap_mask2[0x20]; 3006 3007 u8 cap_mask2_field_select[0x20]; 3008 3009 u8 reserved_at_280[0x80]; 3010 3011 u8 lid[0x10]; 3012 u8 reserved_at_310[0x4]; 3013 u8 init_type_reply[0x4]; 3014 u8 lmc[0x3]; 3015 u8 subnet_timeout[0x5]; 3016 3017 u8 sm_lid[0x10]; 3018 u8 sm_sl[0x4]; 3019 u8 reserved_at_334[0xc]; 3020 3021 u8 qkey_violation_counter[0x10]; 3022 u8 pkey_violation_counter[0x10]; 3023 3024 u8 reserved_at_360[0xca0]; 3025 }; 3026 3027 struct mlx5_ifc_esw_vport_context_bits { 3028 u8 reserved_at_0[0x3]; 3029 u8 vport_svlan_strip[0x1]; 3030 u8 vport_cvlan_strip[0x1]; 3031 u8 vport_svlan_insert[0x1]; 3032 u8 vport_cvlan_insert[0x2]; 3033 u8 reserved_at_8[0x18]; 3034 3035 u8 reserved_at_20[0x20]; 3036 3037 u8 svlan_cfi[0x1]; 3038 u8 svlan_pcp[0x3]; 3039 u8 svlan_id[0xc]; 3040 u8 cvlan_cfi[0x1]; 3041 u8 cvlan_pcp[0x3]; 3042 u8 cvlan_id[0xc]; 3043 3044 u8 reserved_at_60[0x7a0]; 3045 }; 3046 3047 enum { 3048 MLX5_EQC_STATUS_OK = 0x0, 3049 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3050 }; 3051 3052 enum { 3053 MLX5_EQC_ST_ARMED = 0x9, 3054 MLX5_EQC_ST_FIRED = 0xa, 3055 }; 3056 3057 struct mlx5_ifc_eqc_bits { 3058 u8 status[0x4]; 3059 u8 reserved_at_4[0x9]; 3060 u8 ec[0x1]; 3061 u8 oi[0x1]; 3062 u8 reserved_at_f[0x5]; 3063 u8 st[0x4]; 3064 u8 reserved_at_18[0x8]; 3065 3066 u8 reserved_at_20[0x20]; 3067 3068 u8 reserved_at_40[0x14]; 3069 u8 page_offset[0x6]; 3070 u8 reserved_at_5a[0x6]; 3071 3072 u8 reserved_at_60[0x3]; 3073 u8 log_eq_size[0x5]; 3074 u8 uar_page[0x18]; 3075 3076 u8 reserved_at_80[0x20]; 3077 3078 u8 reserved_at_a0[0x18]; 3079 u8 intr[0x8]; 3080 3081 u8 reserved_at_c0[0x3]; 3082 u8 log_page_size[0x5]; 3083 u8 reserved_at_c8[0x18]; 3084 3085 u8 reserved_at_e0[0x60]; 3086 3087 u8 reserved_at_140[0x8]; 3088 u8 consumer_counter[0x18]; 3089 3090 u8 reserved_at_160[0x8]; 3091 u8 producer_counter[0x18]; 3092 3093 u8 reserved_at_180[0x80]; 3094 }; 3095 3096 enum { 3097 MLX5_DCTC_STATE_ACTIVE = 0x0, 3098 MLX5_DCTC_STATE_DRAINING = 0x1, 3099 MLX5_DCTC_STATE_DRAINED = 0x2, 3100 }; 3101 3102 enum { 3103 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3104 MLX5_DCTC_CS_RES_NA = 0x1, 3105 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3106 }; 3107 3108 enum { 3109 MLX5_DCTC_MTU_256_BYTES = 0x1, 3110 MLX5_DCTC_MTU_512_BYTES = 0x2, 3111 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3112 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3113 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3114 }; 3115 3116 struct mlx5_ifc_dctc_bits { 3117 u8 reserved_at_0[0x4]; 3118 u8 state[0x4]; 3119 u8 reserved_at_8[0x18]; 3120 3121 u8 reserved_at_20[0x8]; 3122 u8 user_index[0x18]; 3123 3124 u8 reserved_at_40[0x8]; 3125 u8 cqn[0x18]; 3126 3127 u8 counter_set_id[0x8]; 3128 u8 atomic_mode[0x4]; 3129 u8 rre[0x1]; 3130 u8 rwe[0x1]; 3131 u8 rae[0x1]; 3132 u8 atomic_like_write_en[0x1]; 3133 u8 latency_sensitive[0x1]; 3134 u8 rlky[0x1]; 3135 u8 free_ar[0x1]; 3136 u8 reserved_at_73[0xd]; 3137 3138 u8 reserved_at_80[0x8]; 3139 u8 cs_res[0x8]; 3140 u8 reserved_at_90[0x3]; 3141 u8 min_rnr_nak[0x5]; 3142 u8 reserved_at_98[0x8]; 3143 3144 u8 reserved_at_a0[0x8]; 3145 u8 srqn_xrqn[0x18]; 3146 3147 u8 reserved_at_c0[0x8]; 3148 u8 pd[0x18]; 3149 3150 u8 tclass[0x8]; 3151 u8 reserved_at_e8[0x4]; 3152 u8 flow_label[0x14]; 3153 3154 u8 dc_access_key[0x40]; 3155 3156 u8 reserved_at_140[0x5]; 3157 u8 mtu[0x3]; 3158 u8 port[0x8]; 3159 u8 pkey_index[0x10]; 3160 3161 u8 reserved_at_160[0x8]; 3162 u8 my_addr_index[0x8]; 3163 u8 reserved_at_170[0x8]; 3164 u8 hop_limit[0x8]; 3165 3166 u8 dc_access_key_violation_count[0x20]; 3167 3168 u8 reserved_at_1a0[0x14]; 3169 u8 dei_cfi[0x1]; 3170 u8 eth_prio[0x3]; 3171 u8 ecn[0x2]; 3172 u8 dscp[0x6]; 3173 3174 u8 reserved_at_1c0[0x40]; 3175 }; 3176 3177 enum { 3178 MLX5_CQC_STATUS_OK = 0x0, 3179 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3180 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3181 }; 3182 3183 enum { 3184 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3185 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3186 }; 3187 3188 enum { 3189 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3190 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3191 MLX5_CQC_ST_FIRED = 0xa, 3192 }; 3193 3194 enum { 3195 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3196 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3197 MLX5_CQ_PERIOD_NUM_MODES 3198 }; 3199 3200 struct mlx5_ifc_cqc_bits { 3201 u8 status[0x4]; 3202 u8 reserved_at_4[0x2]; 3203 u8 dbr_umem_valid[0x1]; 3204 u8 reserved_at_7[0x1]; 3205 u8 cqe_sz[0x3]; 3206 u8 cc[0x1]; 3207 u8 reserved_at_c[0x1]; 3208 u8 scqe_break_moderation_en[0x1]; 3209 u8 oi[0x1]; 3210 u8 cq_period_mode[0x2]; 3211 u8 cqe_comp_en[0x1]; 3212 u8 mini_cqe_res_format[0x2]; 3213 u8 st[0x4]; 3214 u8 reserved_at_18[0x8]; 3215 3216 u8 reserved_at_20[0x20]; 3217 3218 u8 reserved_at_40[0x14]; 3219 u8 page_offset[0x6]; 3220 u8 reserved_at_5a[0x6]; 3221 3222 u8 reserved_at_60[0x3]; 3223 u8 log_cq_size[0x5]; 3224 u8 uar_page[0x18]; 3225 3226 u8 reserved_at_80[0x4]; 3227 u8 cq_period[0xc]; 3228 u8 cq_max_count[0x10]; 3229 3230 u8 reserved_at_a0[0x18]; 3231 u8 c_eqn[0x8]; 3232 3233 u8 reserved_at_c0[0x3]; 3234 u8 log_page_size[0x5]; 3235 u8 reserved_at_c8[0x18]; 3236 3237 u8 reserved_at_e0[0x20]; 3238 3239 u8 reserved_at_100[0x8]; 3240 u8 last_notified_index[0x18]; 3241 3242 u8 reserved_at_120[0x8]; 3243 u8 last_solicit_index[0x18]; 3244 3245 u8 reserved_at_140[0x8]; 3246 u8 consumer_counter[0x18]; 3247 3248 u8 reserved_at_160[0x8]; 3249 u8 producer_counter[0x18]; 3250 3251 u8 reserved_at_180[0x40]; 3252 3253 u8 dbr_addr[0x40]; 3254 }; 3255 3256 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3257 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3258 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3259 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3260 u8 reserved_at_0[0x800]; 3261 }; 3262 3263 struct mlx5_ifc_query_adapter_param_block_bits { 3264 u8 reserved_at_0[0xc0]; 3265 3266 u8 reserved_at_c0[0x8]; 3267 u8 ieee_vendor_id[0x18]; 3268 3269 u8 reserved_at_e0[0x10]; 3270 u8 vsd_vendor_id[0x10]; 3271 3272 u8 vsd[208][0x8]; 3273 3274 u8 vsd_contd_psid[16][0x8]; 3275 }; 3276 3277 enum { 3278 MLX5_XRQC_STATE_GOOD = 0x0, 3279 MLX5_XRQC_STATE_ERROR = 0x1, 3280 }; 3281 3282 enum { 3283 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3284 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3285 }; 3286 3287 enum { 3288 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3289 }; 3290 3291 struct mlx5_ifc_tag_matching_topology_context_bits { 3292 u8 log_matching_list_sz[0x4]; 3293 u8 reserved_at_4[0xc]; 3294 u8 append_next_index[0x10]; 3295 3296 u8 sw_phase_cnt[0x10]; 3297 u8 hw_phase_cnt[0x10]; 3298 3299 u8 reserved_at_40[0x40]; 3300 }; 3301 3302 struct mlx5_ifc_xrqc_bits { 3303 u8 state[0x4]; 3304 u8 rlkey[0x1]; 3305 u8 reserved_at_5[0xf]; 3306 u8 topology[0x4]; 3307 u8 reserved_at_18[0x4]; 3308 u8 offload[0x4]; 3309 3310 u8 reserved_at_20[0x8]; 3311 u8 user_index[0x18]; 3312 3313 u8 reserved_at_40[0x8]; 3314 u8 cqn[0x18]; 3315 3316 u8 reserved_at_60[0xa0]; 3317 3318 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3319 3320 u8 reserved_at_180[0x280]; 3321 3322 struct mlx5_ifc_wq_bits wq; 3323 }; 3324 3325 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3326 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3327 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3328 u8 reserved_at_0[0x20]; 3329 }; 3330 3331 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3332 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3333 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3334 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3335 u8 reserved_at_0[0x20]; 3336 }; 3337 3338 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3339 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3340 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3341 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3342 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3343 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3344 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3345 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3346 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3347 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3348 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3349 u8 reserved_at_0[0x7c0]; 3350 }; 3351 3352 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3353 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3354 u8 reserved_at_0[0x7c0]; 3355 }; 3356 3357 union mlx5_ifc_event_auto_bits { 3358 struct mlx5_ifc_comp_event_bits comp_event; 3359 struct mlx5_ifc_dct_events_bits dct_events; 3360 struct mlx5_ifc_qp_events_bits qp_events; 3361 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3362 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3363 struct mlx5_ifc_cq_error_bits cq_error; 3364 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3365 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3366 struct mlx5_ifc_gpio_event_bits gpio_event; 3367 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3368 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3369 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3370 u8 reserved_at_0[0xe0]; 3371 }; 3372 3373 struct mlx5_ifc_health_buffer_bits { 3374 u8 reserved_at_0[0x100]; 3375 3376 u8 assert_existptr[0x20]; 3377 3378 u8 assert_callra[0x20]; 3379 3380 u8 reserved_at_140[0x40]; 3381 3382 u8 fw_version[0x20]; 3383 3384 u8 hw_id[0x20]; 3385 3386 u8 reserved_at_1c0[0x20]; 3387 3388 u8 irisc_index[0x8]; 3389 u8 synd[0x8]; 3390 u8 ext_synd[0x10]; 3391 }; 3392 3393 struct mlx5_ifc_register_loopback_control_bits { 3394 u8 no_lb[0x1]; 3395 u8 reserved_at_1[0x7]; 3396 u8 port[0x8]; 3397 u8 reserved_at_10[0x10]; 3398 3399 u8 reserved_at_20[0x60]; 3400 }; 3401 3402 struct mlx5_ifc_vport_tc_element_bits { 3403 u8 traffic_class[0x4]; 3404 u8 reserved_at_4[0xc]; 3405 u8 vport_number[0x10]; 3406 }; 3407 3408 struct mlx5_ifc_vport_element_bits { 3409 u8 reserved_at_0[0x10]; 3410 u8 vport_number[0x10]; 3411 }; 3412 3413 enum { 3414 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3415 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3416 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3417 }; 3418 3419 struct mlx5_ifc_tsar_element_bits { 3420 u8 reserved_at_0[0x8]; 3421 u8 tsar_type[0x8]; 3422 u8 reserved_at_10[0x10]; 3423 }; 3424 3425 enum { 3426 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3427 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3428 }; 3429 3430 struct mlx5_ifc_teardown_hca_out_bits { 3431 u8 status[0x8]; 3432 u8 reserved_at_8[0x18]; 3433 3434 u8 syndrome[0x20]; 3435 3436 u8 reserved_at_40[0x3f]; 3437 3438 u8 state[0x1]; 3439 }; 3440 3441 enum { 3442 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3443 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3444 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3445 }; 3446 3447 struct mlx5_ifc_teardown_hca_in_bits { 3448 u8 opcode[0x10]; 3449 u8 reserved_at_10[0x10]; 3450 3451 u8 reserved_at_20[0x10]; 3452 u8 op_mod[0x10]; 3453 3454 u8 reserved_at_40[0x10]; 3455 u8 profile[0x10]; 3456 3457 u8 reserved_at_60[0x20]; 3458 }; 3459 3460 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3461 u8 status[0x8]; 3462 u8 reserved_at_8[0x18]; 3463 3464 u8 syndrome[0x20]; 3465 3466 u8 reserved_at_40[0x40]; 3467 }; 3468 3469 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3470 u8 opcode[0x10]; 3471 u8 uid[0x10]; 3472 3473 u8 reserved_at_20[0x10]; 3474 u8 op_mod[0x10]; 3475 3476 u8 reserved_at_40[0x8]; 3477 u8 qpn[0x18]; 3478 3479 u8 reserved_at_60[0x20]; 3480 3481 u8 opt_param_mask[0x20]; 3482 3483 u8 reserved_at_a0[0x20]; 3484 3485 struct mlx5_ifc_qpc_bits qpc; 3486 3487 u8 reserved_at_800[0x80]; 3488 }; 3489 3490 struct mlx5_ifc_sqd2rts_qp_out_bits { 3491 u8 status[0x8]; 3492 u8 reserved_at_8[0x18]; 3493 3494 u8 syndrome[0x20]; 3495 3496 u8 reserved_at_40[0x40]; 3497 }; 3498 3499 struct mlx5_ifc_sqd2rts_qp_in_bits { 3500 u8 opcode[0x10]; 3501 u8 uid[0x10]; 3502 3503 u8 reserved_at_20[0x10]; 3504 u8 op_mod[0x10]; 3505 3506 u8 reserved_at_40[0x8]; 3507 u8 qpn[0x18]; 3508 3509 u8 reserved_at_60[0x20]; 3510 3511 u8 opt_param_mask[0x20]; 3512 3513 u8 reserved_at_a0[0x20]; 3514 3515 struct mlx5_ifc_qpc_bits qpc; 3516 3517 u8 reserved_at_800[0x80]; 3518 }; 3519 3520 struct mlx5_ifc_set_roce_address_out_bits { 3521 u8 status[0x8]; 3522 u8 reserved_at_8[0x18]; 3523 3524 u8 syndrome[0x20]; 3525 3526 u8 reserved_at_40[0x40]; 3527 }; 3528 3529 struct mlx5_ifc_set_roce_address_in_bits { 3530 u8 opcode[0x10]; 3531 u8 reserved_at_10[0x10]; 3532 3533 u8 reserved_at_20[0x10]; 3534 u8 op_mod[0x10]; 3535 3536 u8 roce_address_index[0x10]; 3537 u8 reserved_at_50[0xc]; 3538 u8 vhca_port_num[0x4]; 3539 3540 u8 reserved_at_60[0x20]; 3541 3542 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3543 }; 3544 3545 struct mlx5_ifc_set_mad_demux_out_bits { 3546 u8 status[0x8]; 3547 u8 reserved_at_8[0x18]; 3548 3549 u8 syndrome[0x20]; 3550 3551 u8 reserved_at_40[0x40]; 3552 }; 3553 3554 enum { 3555 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3556 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3557 }; 3558 3559 struct mlx5_ifc_set_mad_demux_in_bits { 3560 u8 opcode[0x10]; 3561 u8 reserved_at_10[0x10]; 3562 3563 u8 reserved_at_20[0x10]; 3564 u8 op_mod[0x10]; 3565 3566 u8 reserved_at_40[0x20]; 3567 3568 u8 reserved_at_60[0x6]; 3569 u8 demux_mode[0x2]; 3570 u8 reserved_at_68[0x18]; 3571 }; 3572 3573 struct mlx5_ifc_set_l2_table_entry_out_bits { 3574 u8 status[0x8]; 3575 u8 reserved_at_8[0x18]; 3576 3577 u8 syndrome[0x20]; 3578 3579 u8 reserved_at_40[0x40]; 3580 }; 3581 3582 struct mlx5_ifc_set_l2_table_entry_in_bits { 3583 u8 opcode[0x10]; 3584 u8 reserved_at_10[0x10]; 3585 3586 u8 reserved_at_20[0x10]; 3587 u8 op_mod[0x10]; 3588 3589 u8 reserved_at_40[0x60]; 3590 3591 u8 reserved_at_a0[0x8]; 3592 u8 table_index[0x18]; 3593 3594 u8 reserved_at_c0[0x20]; 3595 3596 u8 reserved_at_e0[0x13]; 3597 u8 vlan_valid[0x1]; 3598 u8 vlan[0xc]; 3599 3600 struct mlx5_ifc_mac_address_layout_bits mac_address; 3601 3602 u8 reserved_at_140[0xc0]; 3603 }; 3604 3605 struct mlx5_ifc_set_issi_out_bits { 3606 u8 status[0x8]; 3607 u8 reserved_at_8[0x18]; 3608 3609 u8 syndrome[0x20]; 3610 3611 u8 reserved_at_40[0x40]; 3612 }; 3613 3614 struct mlx5_ifc_set_issi_in_bits { 3615 u8 opcode[0x10]; 3616 u8 reserved_at_10[0x10]; 3617 3618 u8 reserved_at_20[0x10]; 3619 u8 op_mod[0x10]; 3620 3621 u8 reserved_at_40[0x10]; 3622 u8 current_issi[0x10]; 3623 3624 u8 reserved_at_60[0x20]; 3625 }; 3626 3627 struct mlx5_ifc_set_hca_cap_out_bits { 3628 u8 status[0x8]; 3629 u8 reserved_at_8[0x18]; 3630 3631 u8 syndrome[0x20]; 3632 3633 u8 reserved_at_40[0x40]; 3634 }; 3635 3636 struct mlx5_ifc_set_hca_cap_in_bits { 3637 u8 opcode[0x10]; 3638 u8 reserved_at_10[0x10]; 3639 3640 u8 reserved_at_20[0x10]; 3641 u8 op_mod[0x10]; 3642 3643 u8 reserved_at_40[0x40]; 3644 3645 union mlx5_ifc_hca_cap_union_bits capability; 3646 }; 3647 3648 enum { 3649 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3650 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3651 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3652 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3653 }; 3654 3655 struct mlx5_ifc_set_fte_out_bits { 3656 u8 status[0x8]; 3657 u8 reserved_at_8[0x18]; 3658 3659 u8 syndrome[0x20]; 3660 3661 u8 reserved_at_40[0x40]; 3662 }; 3663 3664 struct mlx5_ifc_set_fte_in_bits { 3665 u8 opcode[0x10]; 3666 u8 reserved_at_10[0x10]; 3667 3668 u8 reserved_at_20[0x10]; 3669 u8 op_mod[0x10]; 3670 3671 u8 other_vport[0x1]; 3672 u8 reserved_at_41[0xf]; 3673 u8 vport_number[0x10]; 3674 3675 u8 reserved_at_60[0x20]; 3676 3677 u8 table_type[0x8]; 3678 u8 reserved_at_88[0x18]; 3679 3680 u8 reserved_at_a0[0x8]; 3681 u8 table_id[0x18]; 3682 3683 u8 reserved_at_c0[0x18]; 3684 u8 modify_enable_mask[0x8]; 3685 3686 u8 reserved_at_e0[0x20]; 3687 3688 u8 flow_index[0x20]; 3689 3690 u8 reserved_at_120[0xe0]; 3691 3692 struct mlx5_ifc_flow_context_bits flow_context; 3693 }; 3694 3695 struct mlx5_ifc_rts2rts_qp_out_bits { 3696 u8 status[0x8]; 3697 u8 reserved_at_8[0x18]; 3698 3699 u8 syndrome[0x20]; 3700 3701 u8 reserved_at_40[0x40]; 3702 }; 3703 3704 struct mlx5_ifc_rts2rts_qp_in_bits { 3705 u8 opcode[0x10]; 3706 u8 uid[0x10]; 3707 3708 u8 reserved_at_20[0x10]; 3709 u8 op_mod[0x10]; 3710 3711 u8 reserved_at_40[0x8]; 3712 u8 qpn[0x18]; 3713 3714 u8 reserved_at_60[0x20]; 3715 3716 u8 opt_param_mask[0x20]; 3717 3718 u8 reserved_at_a0[0x20]; 3719 3720 struct mlx5_ifc_qpc_bits qpc; 3721 3722 u8 reserved_at_800[0x80]; 3723 }; 3724 3725 struct mlx5_ifc_rtr2rts_qp_out_bits { 3726 u8 status[0x8]; 3727 u8 reserved_at_8[0x18]; 3728 3729 u8 syndrome[0x20]; 3730 3731 u8 reserved_at_40[0x40]; 3732 }; 3733 3734 struct mlx5_ifc_rtr2rts_qp_in_bits { 3735 u8 opcode[0x10]; 3736 u8 uid[0x10]; 3737 3738 u8 reserved_at_20[0x10]; 3739 u8 op_mod[0x10]; 3740 3741 u8 reserved_at_40[0x8]; 3742 u8 qpn[0x18]; 3743 3744 u8 reserved_at_60[0x20]; 3745 3746 u8 opt_param_mask[0x20]; 3747 3748 u8 reserved_at_a0[0x20]; 3749 3750 struct mlx5_ifc_qpc_bits qpc; 3751 3752 u8 reserved_at_800[0x80]; 3753 }; 3754 3755 struct mlx5_ifc_rst2init_qp_out_bits { 3756 u8 status[0x8]; 3757 u8 reserved_at_8[0x18]; 3758 3759 u8 syndrome[0x20]; 3760 3761 u8 reserved_at_40[0x40]; 3762 }; 3763 3764 struct mlx5_ifc_rst2init_qp_in_bits { 3765 u8 opcode[0x10]; 3766 u8 uid[0x10]; 3767 3768 u8 reserved_at_20[0x10]; 3769 u8 op_mod[0x10]; 3770 3771 u8 reserved_at_40[0x8]; 3772 u8 qpn[0x18]; 3773 3774 u8 reserved_at_60[0x20]; 3775 3776 u8 opt_param_mask[0x20]; 3777 3778 u8 reserved_at_a0[0x20]; 3779 3780 struct mlx5_ifc_qpc_bits qpc; 3781 3782 u8 reserved_at_800[0x80]; 3783 }; 3784 3785 struct mlx5_ifc_query_xrq_out_bits { 3786 u8 status[0x8]; 3787 u8 reserved_at_8[0x18]; 3788 3789 u8 syndrome[0x20]; 3790 3791 u8 reserved_at_40[0x40]; 3792 3793 struct mlx5_ifc_xrqc_bits xrq_context; 3794 }; 3795 3796 struct mlx5_ifc_query_xrq_in_bits { 3797 u8 opcode[0x10]; 3798 u8 reserved_at_10[0x10]; 3799 3800 u8 reserved_at_20[0x10]; 3801 u8 op_mod[0x10]; 3802 3803 u8 reserved_at_40[0x8]; 3804 u8 xrqn[0x18]; 3805 3806 u8 reserved_at_60[0x20]; 3807 }; 3808 3809 struct mlx5_ifc_query_xrc_srq_out_bits { 3810 u8 status[0x8]; 3811 u8 reserved_at_8[0x18]; 3812 3813 u8 syndrome[0x20]; 3814 3815 u8 reserved_at_40[0x40]; 3816 3817 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3818 3819 u8 reserved_at_280[0x600]; 3820 3821 u8 pas[0][0x40]; 3822 }; 3823 3824 struct mlx5_ifc_query_xrc_srq_in_bits { 3825 u8 opcode[0x10]; 3826 u8 reserved_at_10[0x10]; 3827 3828 u8 reserved_at_20[0x10]; 3829 u8 op_mod[0x10]; 3830 3831 u8 reserved_at_40[0x8]; 3832 u8 xrc_srqn[0x18]; 3833 3834 u8 reserved_at_60[0x20]; 3835 }; 3836 3837 enum { 3838 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3839 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3840 }; 3841 3842 struct mlx5_ifc_query_vport_state_out_bits { 3843 u8 status[0x8]; 3844 u8 reserved_at_8[0x18]; 3845 3846 u8 syndrome[0x20]; 3847 3848 u8 reserved_at_40[0x20]; 3849 3850 u8 reserved_at_60[0x18]; 3851 u8 admin_state[0x4]; 3852 u8 state[0x4]; 3853 }; 3854 3855 enum { 3856 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3857 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3858 }; 3859 3860 struct mlx5_ifc_arm_monitor_counter_in_bits { 3861 u8 opcode[0x10]; 3862 u8 uid[0x10]; 3863 3864 u8 reserved_at_20[0x10]; 3865 u8 op_mod[0x10]; 3866 3867 u8 reserved_at_40[0x20]; 3868 3869 u8 reserved_at_60[0x20]; 3870 }; 3871 3872 struct mlx5_ifc_arm_monitor_counter_out_bits { 3873 u8 status[0x8]; 3874 u8 reserved_at_8[0x18]; 3875 3876 u8 syndrome[0x20]; 3877 3878 u8 reserved_at_40[0x40]; 3879 }; 3880 3881 enum { 3882 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3883 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3884 }; 3885 3886 enum mlx5_monitor_counter_ppcnt { 3887 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 3888 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 3889 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 3890 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 3891 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 3892 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 3893 }; 3894 3895 enum { 3896 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 3897 }; 3898 3899 struct mlx5_ifc_monitor_counter_output_bits { 3900 u8 reserved_at_0[0x4]; 3901 u8 type[0x4]; 3902 u8 reserved_at_8[0x8]; 3903 u8 counter[0x10]; 3904 3905 u8 counter_group_id[0x20]; 3906 }; 3907 3908 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 3909 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 3910 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 3911 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 3912 3913 struct mlx5_ifc_set_monitor_counter_in_bits { 3914 u8 opcode[0x10]; 3915 u8 uid[0x10]; 3916 3917 u8 reserved_at_20[0x10]; 3918 u8 op_mod[0x10]; 3919 3920 u8 reserved_at_40[0x10]; 3921 u8 num_of_counters[0x10]; 3922 3923 u8 reserved_at_60[0x20]; 3924 3925 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 3926 }; 3927 3928 struct mlx5_ifc_set_monitor_counter_out_bits { 3929 u8 status[0x8]; 3930 u8 reserved_at_8[0x18]; 3931 3932 u8 syndrome[0x20]; 3933 3934 u8 reserved_at_40[0x40]; 3935 }; 3936 3937 struct mlx5_ifc_query_vport_state_in_bits { 3938 u8 opcode[0x10]; 3939 u8 reserved_at_10[0x10]; 3940 3941 u8 reserved_at_20[0x10]; 3942 u8 op_mod[0x10]; 3943 3944 u8 other_vport[0x1]; 3945 u8 reserved_at_41[0xf]; 3946 u8 vport_number[0x10]; 3947 3948 u8 reserved_at_60[0x20]; 3949 }; 3950 3951 struct mlx5_ifc_query_vnic_env_out_bits { 3952 u8 status[0x8]; 3953 u8 reserved_at_8[0x18]; 3954 3955 u8 syndrome[0x20]; 3956 3957 u8 reserved_at_40[0x40]; 3958 3959 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3960 }; 3961 3962 enum { 3963 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3964 }; 3965 3966 struct mlx5_ifc_query_vnic_env_in_bits { 3967 u8 opcode[0x10]; 3968 u8 reserved_at_10[0x10]; 3969 3970 u8 reserved_at_20[0x10]; 3971 u8 op_mod[0x10]; 3972 3973 u8 other_vport[0x1]; 3974 u8 reserved_at_41[0xf]; 3975 u8 vport_number[0x10]; 3976 3977 u8 reserved_at_60[0x20]; 3978 }; 3979 3980 struct mlx5_ifc_query_vport_counter_out_bits { 3981 u8 status[0x8]; 3982 u8 reserved_at_8[0x18]; 3983 3984 u8 syndrome[0x20]; 3985 3986 u8 reserved_at_40[0x40]; 3987 3988 struct mlx5_ifc_traffic_counter_bits received_errors; 3989 3990 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3991 3992 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3993 3994 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3995 3996 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3997 3998 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3999 4000 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4001 4002 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4003 4004 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4005 4006 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4007 4008 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4009 4010 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4011 4012 u8 reserved_at_680[0xa00]; 4013 }; 4014 4015 enum { 4016 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4017 }; 4018 4019 struct mlx5_ifc_query_vport_counter_in_bits { 4020 u8 opcode[0x10]; 4021 u8 reserved_at_10[0x10]; 4022 4023 u8 reserved_at_20[0x10]; 4024 u8 op_mod[0x10]; 4025 4026 u8 other_vport[0x1]; 4027 u8 reserved_at_41[0xb]; 4028 u8 port_num[0x4]; 4029 u8 vport_number[0x10]; 4030 4031 u8 reserved_at_60[0x60]; 4032 4033 u8 clear[0x1]; 4034 u8 reserved_at_c1[0x1f]; 4035 4036 u8 reserved_at_e0[0x20]; 4037 }; 4038 4039 struct mlx5_ifc_query_tis_out_bits { 4040 u8 status[0x8]; 4041 u8 reserved_at_8[0x18]; 4042 4043 u8 syndrome[0x20]; 4044 4045 u8 reserved_at_40[0x40]; 4046 4047 struct mlx5_ifc_tisc_bits tis_context; 4048 }; 4049 4050 struct mlx5_ifc_query_tis_in_bits { 4051 u8 opcode[0x10]; 4052 u8 reserved_at_10[0x10]; 4053 4054 u8 reserved_at_20[0x10]; 4055 u8 op_mod[0x10]; 4056 4057 u8 reserved_at_40[0x8]; 4058 u8 tisn[0x18]; 4059 4060 u8 reserved_at_60[0x20]; 4061 }; 4062 4063 struct mlx5_ifc_query_tir_out_bits { 4064 u8 status[0x8]; 4065 u8 reserved_at_8[0x18]; 4066 4067 u8 syndrome[0x20]; 4068 4069 u8 reserved_at_40[0xc0]; 4070 4071 struct mlx5_ifc_tirc_bits tir_context; 4072 }; 4073 4074 struct mlx5_ifc_query_tir_in_bits { 4075 u8 opcode[0x10]; 4076 u8 reserved_at_10[0x10]; 4077 4078 u8 reserved_at_20[0x10]; 4079 u8 op_mod[0x10]; 4080 4081 u8 reserved_at_40[0x8]; 4082 u8 tirn[0x18]; 4083 4084 u8 reserved_at_60[0x20]; 4085 }; 4086 4087 struct mlx5_ifc_query_srq_out_bits { 4088 u8 status[0x8]; 4089 u8 reserved_at_8[0x18]; 4090 4091 u8 syndrome[0x20]; 4092 4093 u8 reserved_at_40[0x40]; 4094 4095 struct mlx5_ifc_srqc_bits srq_context_entry; 4096 4097 u8 reserved_at_280[0x600]; 4098 4099 u8 pas[0][0x40]; 4100 }; 4101 4102 struct mlx5_ifc_query_srq_in_bits { 4103 u8 opcode[0x10]; 4104 u8 reserved_at_10[0x10]; 4105 4106 u8 reserved_at_20[0x10]; 4107 u8 op_mod[0x10]; 4108 4109 u8 reserved_at_40[0x8]; 4110 u8 srqn[0x18]; 4111 4112 u8 reserved_at_60[0x20]; 4113 }; 4114 4115 struct mlx5_ifc_query_sq_out_bits { 4116 u8 status[0x8]; 4117 u8 reserved_at_8[0x18]; 4118 4119 u8 syndrome[0x20]; 4120 4121 u8 reserved_at_40[0xc0]; 4122 4123 struct mlx5_ifc_sqc_bits sq_context; 4124 }; 4125 4126 struct mlx5_ifc_query_sq_in_bits { 4127 u8 opcode[0x10]; 4128 u8 reserved_at_10[0x10]; 4129 4130 u8 reserved_at_20[0x10]; 4131 u8 op_mod[0x10]; 4132 4133 u8 reserved_at_40[0x8]; 4134 u8 sqn[0x18]; 4135 4136 u8 reserved_at_60[0x20]; 4137 }; 4138 4139 struct mlx5_ifc_query_special_contexts_out_bits { 4140 u8 status[0x8]; 4141 u8 reserved_at_8[0x18]; 4142 4143 u8 syndrome[0x20]; 4144 4145 u8 dump_fill_mkey[0x20]; 4146 4147 u8 resd_lkey[0x20]; 4148 4149 u8 null_mkey[0x20]; 4150 4151 u8 reserved_at_a0[0x60]; 4152 }; 4153 4154 struct mlx5_ifc_query_special_contexts_in_bits { 4155 u8 opcode[0x10]; 4156 u8 reserved_at_10[0x10]; 4157 4158 u8 reserved_at_20[0x10]; 4159 u8 op_mod[0x10]; 4160 4161 u8 reserved_at_40[0x40]; 4162 }; 4163 4164 struct mlx5_ifc_query_scheduling_element_out_bits { 4165 u8 opcode[0x10]; 4166 u8 reserved_at_10[0x10]; 4167 4168 u8 reserved_at_20[0x10]; 4169 u8 op_mod[0x10]; 4170 4171 u8 reserved_at_40[0xc0]; 4172 4173 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4174 4175 u8 reserved_at_300[0x100]; 4176 }; 4177 4178 enum { 4179 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4180 }; 4181 4182 struct mlx5_ifc_query_scheduling_element_in_bits { 4183 u8 opcode[0x10]; 4184 u8 reserved_at_10[0x10]; 4185 4186 u8 reserved_at_20[0x10]; 4187 u8 op_mod[0x10]; 4188 4189 u8 scheduling_hierarchy[0x8]; 4190 u8 reserved_at_48[0x18]; 4191 4192 u8 scheduling_element_id[0x20]; 4193 4194 u8 reserved_at_80[0x180]; 4195 }; 4196 4197 struct mlx5_ifc_query_rqt_out_bits { 4198 u8 status[0x8]; 4199 u8 reserved_at_8[0x18]; 4200 4201 u8 syndrome[0x20]; 4202 4203 u8 reserved_at_40[0xc0]; 4204 4205 struct mlx5_ifc_rqtc_bits rqt_context; 4206 }; 4207 4208 struct mlx5_ifc_query_rqt_in_bits { 4209 u8 opcode[0x10]; 4210 u8 reserved_at_10[0x10]; 4211 4212 u8 reserved_at_20[0x10]; 4213 u8 op_mod[0x10]; 4214 4215 u8 reserved_at_40[0x8]; 4216 u8 rqtn[0x18]; 4217 4218 u8 reserved_at_60[0x20]; 4219 }; 4220 4221 struct mlx5_ifc_query_rq_out_bits { 4222 u8 status[0x8]; 4223 u8 reserved_at_8[0x18]; 4224 4225 u8 syndrome[0x20]; 4226 4227 u8 reserved_at_40[0xc0]; 4228 4229 struct mlx5_ifc_rqc_bits rq_context; 4230 }; 4231 4232 struct mlx5_ifc_query_rq_in_bits { 4233 u8 opcode[0x10]; 4234 u8 reserved_at_10[0x10]; 4235 4236 u8 reserved_at_20[0x10]; 4237 u8 op_mod[0x10]; 4238 4239 u8 reserved_at_40[0x8]; 4240 u8 rqn[0x18]; 4241 4242 u8 reserved_at_60[0x20]; 4243 }; 4244 4245 struct mlx5_ifc_query_roce_address_out_bits { 4246 u8 status[0x8]; 4247 u8 reserved_at_8[0x18]; 4248 4249 u8 syndrome[0x20]; 4250 4251 u8 reserved_at_40[0x40]; 4252 4253 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4254 }; 4255 4256 struct mlx5_ifc_query_roce_address_in_bits { 4257 u8 opcode[0x10]; 4258 u8 reserved_at_10[0x10]; 4259 4260 u8 reserved_at_20[0x10]; 4261 u8 op_mod[0x10]; 4262 4263 u8 roce_address_index[0x10]; 4264 u8 reserved_at_50[0xc]; 4265 u8 vhca_port_num[0x4]; 4266 4267 u8 reserved_at_60[0x20]; 4268 }; 4269 4270 struct mlx5_ifc_query_rmp_out_bits { 4271 u8 status[0x8]; 4272 u8 reserved_at_8[0x18]; 4273 4274 u8 syndrome[0x20]; 4275 4276 u8 reserved_at_40[0xc0]; 4277 4278 struct mlx5_ifc_rmpc_bits rmp_context; 4279 }; 4280 4281 struct mlx5_ifc_query_rmp_in_bits { 4282 u8 opcode[0x10]; 4283 u8 reserved_at_10[0x10]; 4284 4285 u8 reserved_at_20[0x10]; 4286 u8 op_mod[0x10]; 4287 4288 u8 reserved_at_40[0x8]; 4289 u8 rmpn[0x18]; 4290 4291 u8 reserved_at_60[0x20]; 4292 }; 4293 4294 struct mlx5_ifc_query_qp_out_bits { 4295 u8 status[0x8]; 4296 u8 reserved_at_8[0x18]; 4297 4298 u8 syndrome[0x20]; 4299 4300 u8 reserved_at_40[0x40]; 4301 4302 u8 opt_param_mask[0x20]; 4303 4304 u8 reserved_at_a0[0x20]; 4305 4306 struct mlx5_ifc_qpc_bits qpc; 4307 4308 u8 reserved_at_800[0x80]; 4309 4310 u8 pas[0][0x40]; 4311 }; 4312 4313 struct mlx5_ifc_query_qp_in_bits { 4314 u8 opcode[0x10]; 4315 u8 reserved_at_10[0x10]; 4316 4317 u8 reserved_at_20[0x10]; 4318 u8 op_mod[0x10]; 4319 4320 u8 reserved_at_40[0x8]; 4321 u8 qpn[0x18]; 4322 4323 u8 reserved_at_60[0x20]; 4324 }; 4325 4326 struct mlx5_ifc_query_q_counter_out_bits { 4327 u8 status[0x8]; 4328 u8 reserved_at_8[0x18]; 4329 4330 u8 syndrome[0x20]; 4331 4332 u8 reserved_at_40[0x40]; 4333 4334 u8 rx_write_requests[0x20]; 4335 4336 u8 reserved_at_a0[0x20]; 4337 4338 u8 rx_read_requests[0x20]; 4339 4340 u8 reserved_at_e0[0x20]; 4341 4342 u8 rx_atomic_requests[0x20]; 4343 4344 u8 reserved_at_120[0x20]; 4345 4346 u8 rx_dct_connect[0x20]; 4347 4348 u8 reserved_at_160[0x20]; 4349 4350 u8 out_of_buffer[0x20]; 4351 4352 u8 reserved_at_1a0[0x20]; 4353 4354 u8 out_of_sequence[0x20]; 4355 4356 u8 reserved_at_1e0[0x20]; 4357 4358 u8 duplicate_request[0x20]; 4359 4360 u8 reserved_at_220[0x20]; 4361 4362 u8 rnr_nak_retry_err[0x20]; 4363 4364 u8 reserved_at_260[0x20]; 4365 4366 u8 packet_seq_err[0x20]; 4367 4368 u8 reserved_at_2a0[0x20]; 4369 4370 u8 implied_nak_seq_err[0x20]; 4371 4372 u8 reserved_at_2e0[0x20]; 4373 4374 u8 local_ack_timeout_err[0x20]; 4375 4376 u8 reserved_at_320[0xa0]; 4377 4378 u8 resp_local_length_error[0x20]; 4379 4380 u8 req_local_length_error[0x20]; 4381 4382 u8 resp_local_qp_error[0x20]; 4383 4384 u8 local_operation_error[0x20]; 4385 4386 u8 resp_local_protection[0x20]; 4387 4388 u8 req_local_protection[0x20]; 4389 4390 u8 resp_cqe_error[0x20]; 4391 4392 u8 req_cqe_error[0x20]; 4393 4394 u8 req_mw_binding[0x20]; 4395 4396 u8 req_bad_response[0x20]; 4397 4398 u8 req_remote_invalid_request[0x20]; 4399 4400 u8 resp_remote_invalid_request[0x20]; 4401 4402 u8 req_remote_access_errors[0x20]; 4403 4404 u8 resp_remote_access_errors[0x20]; 4405 4406 u8 req_remote_operation_errors[0x20]; 4407 4408 u8 req_transport_retries_exceeded[0x20]; 4409 4410 u8 cq_overflow[0x20]; 4411 4412 u8 resp_cqe_flush_error[0x20]; 4413 4414 u8 req_cqe_flush_error[0x20]; 4415 4416 u8 reserved_at_620[0x1e0]; 4417 }; 4418 4419 struct mlx5_ifc_query_q_counter_in_bits { 4420 u8 opcode[0x10]; 4421 u8 reserved_at_10[0x10]; 4422 4423 u8 reserved_at_20[0x10]; 4424 u8 op_mod[0x10]; 4425 4426 u8 reserved_at_40[0x80]; 4427 4428 u8 clear[0x1]; 4429 u8 reserved_at_c1[0x1f]; 4430 4431 u8 reserved_at_e0[0x18]; 4432 u8 counter_set_id[0x8]; 4433 }; 4434 4435 struct mlx5_ifc_query_pages_out_bits { 4436 u8 status[0x8]; 4437 u8 reserved_at_8[0x18]; 4438 4439 u8 syndrome[0x20]; 4440 4441 u8 reserved_at_40[0x10]; 4442 u8 function_id[0x10]; 4443 4444 u8 num_pages[0x20]; 4445 }; 4446 4447 enum { 4448 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4449 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4450 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4451 }; 4452 4453 struct mlx5_ifc_query_pages_in_bits { 4454 u8 opcode[0x10]; 4455 u8 reserved_at_10[0x10]; 4456 4457 u8 reserved_at_20[0x10]; 4458 u8 op_mod[0x10]; 4459 4460 u8 reserved_at_40[0x10]; 4461 u8 function_id[0x10]; 4462 4463 u8 reserved_at_60[0x20]; 4464 }; 4465 4466 struct mlx5_ifc_query_nic_vport_context_out_bits { 4467 u8 status[0x8]; 4468 u8 reserved_at_8[0x18]; 4469 4470 u8 syndrome[0x20]; 4471 4472 u8 reserved_at_40[0x40]; 4473 4474 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4475 }; 4476 4477 struct mlx5_ifc_query_nic_vport_context_in_bits { 4478 u8 opcode[0x10]; 4479 u8 reserved_at_10[0x10]; 4480 4481 u8 reserved_at_20[0x10]; 4482 u8 op_mod[0x10]; 4483 4484 u8 other_vport[0x1]; 4485 u8 reserved_at_41[0xf]; 4486 u8 vport_number[0x10]; 4487 4488 u8 reserved_at_60[0x5]; 4489 u8 allowed_list_type[0x3]; 4490 u8 reserved_at_68[0x18]; 4491 }; 4492 4493 struct mlx5_ifc_query_mkey_out_bits { 4494 u8 status[0x8]; 4495 u8 reserved_at_8[0x18]; 4496 4497 u8 syndrome[0x20]; 4498 4499 u8 reserved_at_40[0x40]; 4500 4501 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4502 4503 u8 reserved_at_280[0x600]; 4504 4505 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4506 4507 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4508 }; 4509 4510 struct mlx5_ifc_query_mkey_in_bits { 4511 u8 opcode[0x10]; 4512 u8 reserved_at_10[0x10]; 4513 4514 u8 reserved_at_20[0x10]; 4515 u8 op_mod[0x10]; 4516 4517 u8 reserved_at_40[0x8]; 4518 u8 mkey_index[0x18]; 4519 4520 u8 pg_access[0x1]; 4521 u8 reserved_at_61[0x1f]; 4522 }; 4523 4524 struct mlx5_ifc_query_mad_demux_out_bits { 4525 u8 status[0x8]; 4526 u8 reserved_at_8[0x18]; 4527 4528 u8 syndrome[0x20]; 4529 4530 u8 reserved_at_40[0x40]; 4531 4532 u8 mad_dumux_parameters_block[0x20]; 4533 }; 4534 4535 struct mlx5_ifc_query_mad_demux_in_bits { 4536 u8 opcode[0x10]; 4537 u8 reserved_at_10[0x10]; 4538 4539 u8 reserved_at_20[0x10]; 4540 u8 op_mod[0x10]; 4541 4542 u8 reserved_at_40[0x40]; 4543 }; 4544 4545 struct mlx5_ifc_query_l2_table_entry_out_bits { 4546 u8 status[0x8]; 4547 u8 reserved_at_8[0x18]; 4548 4549 u8 syndrome[0x20]; 4550 4551 u8 reserved_at_40[0xa0]; 4552 4553 u8 reserved_at_e0[0x13]; 4554 u8 vlan_valid[0x1]; 4555 u8 vlan[0xc]; 4556 4557 struct mlx5_ifc_mac_address_layout_bits mac_address; 4558 4559 u8 reserved_at_140[0xc0]; 4560 }; 4561 4562 struct mlx5_ifc_query_l2_table_entry_in_bits { 4563 u8 opcode[0x10]; 4564 u8 reserved_at_10[0x10]; 4565 4566 u8 reserved_at_20[0x10]; 4567 u8 op_mod[0x10]; 4568 4569 u8 reserved_at_40[0x60]; 4570 4571 u8 reserved_at_a0[0x8]; 4572 u8 table_index[0x18]; 4573 4574 u8 reserved_at_c0[0x140]; 4575 }; 4576 4577 struct mlx5_ifc_query_issi_out_bits { 4578 u8 status[0x8]; 4579 u8 reserved_at_8[0x18]; 4580 4581 u8 syndrome[0x20]; 4582 4583 u8 reserved_at_40[0x10]; 4584 u8 current_issi[0x10]; 4585 4586 u8 reserved_at_60[0xa0]; 4587 4588 u8 reserved_at_100[76][0x8]; 4589 u8 supported_issi_dw0[0x20]; 4590 }; 4591 4592 struct mlx5_ifc_query_issi_in_bits { 4593 u8 opcode[0x10]; 4594 u8 reserved_at_10[0x10]; 4595 4596 u8 reserved_at_20[0x10]; 4597 u8 op_mod[0x10]; 4598 4599 u8 reserved_at_40[0x40]; 4600 }; 4601 4602 struct mlx5_ifc_set_driver_version_out_bits { 4603 u8 status[0x8]; 4604 u8 reserved_0[0x18]; 4605 4606 u8 syndrome[0x20]; 4607 u8 reserved_1[0x40]; 4608 }; 4609 4610 struct mlx5_ifc_set_driver_version_in_bits { 4611 u8 opcode[0x10]; 4612 u8 reserved_0[0x10]; 4613 4614 u8 reserved_1[0x10]; 4615 u8 op_mod[0x10]; 4616 4617 u8 reserved_2[0x40]; 4618 u8 driver_version[64][0x8]; 4619 }; 4620 4621 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4622 u8 status[0x8]; 4623 u8 reserved_at_8[0x18]; 4624 4625 u8 syndrome[0x20]; 4626 4627 u8 reserved_at_40[0x40]; 4628 4629 struct mlx5_ifc_pkey_bits pkey[0]; 4630 }; 4631 4632 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4633 u8 opcode[0x10]; 4634 u8 reserved_at_10[0x10]; 4635 4636 u8 reserved_at_20[0x10]; 4637 u8 op_mod[0x10]; 4638 4639 u8 other_vport[0x1]; 4640 u8 reserved_at_41[0xb]; 4641 u8 port_num[0x4]; 4642 u8 vport_number[0x10]; 4643 4644 u8 reserved_at_60[0x10]; 4645 u8 pkey_index[0x10]; 4646 }; 4647 4648 enum { 4649 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4650 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4651 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4652 }; 4653 4654 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4655 u8 status[0x8]; 4656 u8 reserved_at_8[0x18]; 4657 4658 u8 syndrome[0x20]; 4659 4660 u8 reserved_at_40[0x20]; 4661 4662 u8 gids_num[0x10]; 4663 u8 reserved_at_70[0x10]; 4664 4665 struct mlx5_ifc_array128_auto_bits gid[0]; 4666 }; 4667 4668 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4669 u8 opcode[0x10]; 4670 u8 reserved_at_10[0x10]; 4671 4672 u8 reserved_at_20[0x10]; 4673 u8 op_mod[0x10]; 4674 4675 u8 other_vport[0x1]; 4676 u8 reserved_at_41[0xb]; 4677 u8 port_num[0x4]; 4678 u8 vport_number[0x10]; 4679 4680 u8 reserved_at_60[0x10]; 4681 u8 gid_index[0x10]; 4682 }; 4683 4684 struct mlx5_ifc_query_hca_vport_context_out_bits { 4685 u8 status[0x8]; 4686 u8 reserved_at_8[0x18]; 4687 4688 u8 syndrome[0x20]; 4689 4690 u8 reserved_at_40[0x40]; 4691 4692 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4693 }; 4694 4695 struct mlx5_ifc_query_hca_vport_context_in_bits { 4696 u8 opcode[0x10]; 4697 u8 reserved_at_10[0x10]; 4698 4699 u8 reserved_at_20[0x10]; 4700 u8 op_mod[0x10]; 4701 4702 u8 other_vport[0x1]; 4703 u8 reserved_at_41[0xb]; 4704 u8 port_num[0x4]; 4705 u8 vport_number[0x10]; 4706 4707 u8 reserved_at_60[0x20]; 4708 }; 4709 4710 struct mlx5_ifc_query_hca_cap_out_bits { 4711 u8 status[0x8]; 4712 u8 reserved_at_8[0x18]; 4713 4714 u8 syndrome[0x20]; 4715 4716 u8 reserved_at_40[0x40]; 4717 4718 union mlx5_ifc_hca_cap_union_bits capability; 4719 }; 4720 4721 struct mlx5_ifc_query_hca_cap_in_bits { 4722 u8 opcode[0x10]; 4723 u8 reserved_at_10[0x10]; 4724 4725 u8 reserved_at_20[0x10]; 4726 u8 op_mod[0x10]; 4727 4728 u8 reserved_at_40[0x40]; 4729 }; 4730 4731 struct mlx5_ifc_query_flow_table_out_bits { 4732 u8 status[0x8]; 4733 u8 reserved_at_8[0x18]; 4734 4735 u8 syndrome[0x20]; 4736 4737 u8 reserved_at_40[0x80]; 4738 4739 u8 reserved_at_c0[0x8]; 4740 u8 level[0x8]; 4741 u8 reserved_at_d0[0x8]; 4742 u8 log_size[0x8]; 4743 4744 u8 reserved_at_e0[0x120]; 4745 }; 4746 4747 struct mlx5_ifc_query_flow_table_in_bits { 4748 u8 opcode[0x10]; 4749 u8 reserved_at_10[0x10]; 4750 4751 u8 reserved_at_20[0x10]; 4752 u8 op_mod[0x10]; 4753 4754 u8 reserved_at_40[0x40]; 4755 4756 u8 table_type[0x8]; 4757 u8 reserved_at_88[0x18]; 4758 4759 u8 reserved_at_a0[0x8]; 4760 u8 table_id[0x18]; 4761 4762 u8 reserved_at_c0[0x140]; 4763 }; 4764 4765 struct mlx5_ifc_query_fte_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_at_8[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 reserved_at_40[0x1c0]; 4772 4773 struct mlx5_ifc_flow_context_bits flow_context; 4774 }; 4775 4776 struct mlx5_ifc_query_fte_in_bits { 4777 u8 opcode[0x10]; 4778 u8 reserved_at_10[0x10]; 4779 4780 u8 reserved_at_20[0x10]; 4781 u8 op_mod[0x10]; 4782 4783 u8 reserved_at_40[0x40]; 4784 4785 u8 table_type[0x8]; 4786 u8 reserved_at_88[0x18]; 4787 4788 u8 reserved_at_a0[0x8]; 4789 u8 table_id[0x18]; 4790 4791 u8 reserved_at_c0[0x40]; 4792 4793 u8 flow_index[0x20]; 4794 4795 u8 reserved_at_120[0xe0]; 4796 }; 4797 4798 enum { 4799 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4800 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4801 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4802 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 4803 }; 4804 4805 struct mlx5_ifc_query_flow_group_out_bits { 4806 u8 status[0x8]; 4807 u8 reserved_at_8[0x18]; 4808 4809 u8 syndrome[0x20]; 4810 4811 u8 reserved_at_40[0xa0]; 4812 4813 u8 start_flow_index[0x20]; 4814 4815 u8 reserved_at_100[0x20]; 4816 4817 u8 end_flow_index[0x20]; 4818 4819 u8 reserved_at_140[0xa0]; 4820 4821 u8 reserved_at_1e0[0x18]; 4822 u8 match_criteria_enable[0x8]; 4823 4824 struct mlx5_ifc_fte_match_param_bits match_criteria; 4825 4826 u8 reserved_at_1200[0xe00]; 4827 }; 4828 4829 struct mlx5_ifc_query_flow_group_in_bits { 4830 u8 opcode[0x10]; 4831 u8 reserved_at_10[0x10]; 4832 4833 u8 reserved_at_20[0x10]; 4834 u8 op_mod[0x10]; 4835 4836 u8 reserved_at_40[0x40]; 4837 4838 u8 table_type[0x8]; 4839 u8 reserved_at_88[0x18]; 4840 4841 u8 reserved_at_a0[0x8]; 4842 u8 table_id[0x18]; 4843 4844 u8 group_id[0x20]; 4845 4846 u8 reserved_at_e0[0x120]; 4847 }; 4848 4849 struct mlx5_ifc_query_flow_counter_out_bits { 4850 u8 status[0x8]; 4851 u8 reserved_at_8[0x18]; 4852 4853 u8 syndrome[0x20]; 4854 4855 u8 reserved_at_40[0x40]; 4856 4857 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4858 }; 4859 4860 struct mlx5_ifc_query_flow_counter_in_bits { 4861 u8 opcode[0x10]; 4862 u8 reserved_at_10[0x10]; 4863 4864 u8 reserved_at_20[0x10]; 4865 u8 op_mod[0x10]; 4866 4867 u8 reserved_at_40[0x80]; 4868 4869 u8 clear[0x1]; 4870 u8 reserved_at_c1[0xf]; 4871 u8 num_of_counters[0x10]; 4872 4873 u8 flow_counter_id[0x20]; 4874 }; 4875 4876 struct mlx5_ifc_query_esw_vport_context_out_bits { 4877 u8 status[0x8]; 4878 u8 reserved_at_8[0x18]; 4879 4880 u8 syndrome[0x20]; 4881 4882 u8 reserved_at_40[0x40]; 4883 4884 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4885 }; 4886 4887 struct mlx5_ifc_query_esw_vport_context_in_bits { 4888 u8 opcode[0x10]; 4889 u8 reserved_at_10[0x10]; 4890 4891 u8 reserved_at_20[0x10]; 4892 u8 op_mod[0x10]; 4893 4894 u8 other_vport[0x1]; 4895 u8 reserved_at_41[0xf]; 4896 u8 vport_number[0x10]; 4897 4898 u8 reserved_at_60[0x20]; 4899 }; 4900 4901 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4902 u8 status[0x8]; 4903 u8 reserved_at_8[0x18]; 4904 4905 u8 syndrome[0x20]; 4906 4907 u8 reserved_at_40[0x40]; 4908 }; 4909 4910 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4911 u8 reserved_at_0[0x1c]; 4912 u8 vport_cvlan_insert[0x1]; 4913 u8 vport_svlan_insert[0x1]; 4914 u8 vport_cvlan_strip[0x1]; 4915 u8 vport_svlan_strip[0x1]; 4916 }; 4917 4918 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4919 u8 opcode[0x10]; 4920 u8 reserved_at_10[0x10]; 4921 4922 u8 reserved_at_20[0x10]; 4923 u8 op_mod[0x10]; 4924 4925 u8 other_vport[0x1]; 4926 u8 reserved_at_41[0xf]; 4927 u8 vport_number[0x10]; 4928 4929 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4930 4931 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4932 }; 4933 4934 struct mlx5_ifc_query_eq_out_bits { 4935 u8 status[0x8]; 4936 u8 reserved_at_8[0x18]; 4937 4938 u8 syndrome[0x20]; 4939 4940 u8 reserved_at_40[0x40]; 4941 4942 struct mlx5_ifc_eqc_bits eq_context_entry; 4943 4944 u8 reserved_at_280[0x40]; 4945 4946 u8 event_bitmask[0x40]; 4947 4948 u8 reserved_at_300[0x580]; 4949 4950 u8 pas[0][0x40]; 4951 }; 4952 4953 struct mlx5_ifc_query_eq_in_bits { 4954 u8 opcode[0x10]; 4955 u8 reserved_at_10[0x10]; 4956 4957 u8 reserved_at_20[0x10]; 4958 u8 op_mod[0x10]; 4959 4960 u8 reserved_at_40[0x18]; 4961 u8 eq_number[0x8]; 4962 4963 u8 reserved_at_60[0x20]; 4964 }; 4965 4966 struct mlx5_ifc_packet_reformat_context_in_bits { 4967 u8 reserved_at_0[0x5]; 4968 u8 reformat_type[0x3]; 4969 u8 reserved_at_8[0xe]; 4970 u8 reformat_data_size[0xa]; 4971 4972 u8 reserved_at_20[0x10]; 4973 u8 reformat_data[2][0x8]; 4974 4975 u8 more_reformat_data[0][0x8]; 4976 }; 4977 4978 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4979 u8 status[0x8]; 4980 u8 reserved_at_8[0x18]; 4981 4982 u8 syndrome[0x20]; 4983 4984 u8 reserved_at_40[0xa0]; 4985 4986 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4987 }; 4988 4989 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4990 u8 opcode[0x10]; 4991 u8 reserved_at_10[0x10]; 4992 4993 u8 reserved_at_20[0x10]; 4994 u8 op_mod[0x10]; 4995 4996 u8 packet_reformat_id[0x20]; 4997 4998 u8 reserved_at_60[0xa0]; 4999 }; 5000 5001 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5002 u8 status[0x8]; 5003 u8 reserved_at_8[0x18]; 5004 5005 u8 syndrome[0x20]; 5006 5007 u8 packet_reformat_id[0x20]; 5008 5009 u8 reserved_at_60[0x20]; 5010 }; 5011 5012 enum { 5013 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5014 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5015 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5016 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5017 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5018 }; 5019 5020 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5021 u8 opcode[0x10]; 5022 u8 reserved_at_10[0x10]; 5023 5024 u8 reserved_at_20[0x10]; 5025 u8 op_mod[0x10]; 5026 5027 u8 reserved_at_40[0xa0]; 5028 5029 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5030 }; 5031 5032 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5033 u8 status[0x8]; 5034 u8 reserved_at_8[0x18]; 5035 5036 u8 syndrome[0x20]; 5037 5038 u8 reserved_at_40[0x40]; 5039 }; 5040 5041 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5042 u8 opcode[0x10]; 5043 u8 reserved_at_10[0x10]; 5044 5045 u8 reserved_20[0x10]; 5046 u8 op_mod[0x10]; 5047 5048 u8 packet_reformat_id[0x20]; 5049 5050 u8 reserved_60[0x20]; 5051 }; 5052 5053 struct mlx5_ifc_set_action_in_bits { 5054 u8 action_type[0x4]; 5055 u8 field[0xc]; 5056 u8 reserved_at_10[0x3]; 5057 u8 offset[0x5]; 5058 u8 reserved_at_18[0x3]; 5059 u8 length[0x5]; 5060 5061 u8 data[0x20]; 5062 }; 5063 5064 struct mlx5_ifc_add_action_in_bits { 5065 u8 action_type[0x4]; 5066 u8 field[0xc]; 5067 u8 reserved_at_10[0x10]; 5068 5069 u8 data[0x20]; 5070 }; 5071 5072 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5073 struct mlx5_ifc_set_action_in_bits set_action_in; 5074 struct mlx5_ifc_add_action_in_bits add_action_in; 5075 u8 reserved_at_0[0x40]; 5076 }; 5077 5078 enum { 5079 MLX5_ACTION_TYPE_SET = 0x1, 5080 MLX5_ACTION_TYPE_ADD = 0x2, 5081 }; 5082 5083 enum { 5084 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5085 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5086 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5087 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5088 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5089 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5090 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5091 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5092 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5093 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5094 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5095 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5096 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5097 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5098 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5099 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5100 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5101 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5102 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5103 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5104 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5105 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5106 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5107 }; 5108 5109 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5110 u8 status[0x8]; 5111 u8 reserved_at_8[0x18]; 5112 5113 u8 syndrome[0x20]; 5114 5115 u8 modify_header_id[0x20]; 5116 5117 u8 reserved_at_60[0x20]; 5118 }; 5119 5120 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5121 u8 opcode[0x10]; 5122 u8 reserved_at_10[0x10]; 5123 5124 u8 reserved_at_20[0x10]; 5125 u8 op_mod[0x10]; 5126 5127 u8 reserved_at_40[0x20]; 5128 5129 u8 table_type[0x8]; 5130 u8 reserved_at_68[0x10]; 5131 u8 num_of_actions[0x8]; 5132 5133 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5134 }; 5135 5136 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5137 u8 status[0x8]; 5138 u8 reserved_at_8[0x18]; 5139 5140 u8 syndrome[0x20]; 5141 5142 u8 reserved_at_40[0x40]; 5143 }; 5144 5145 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5146 u8 opcode[0x10]; 5147 u8 reserved_at_10[0x10]; 5148 5149 u8 reserved_at_20[0x10]; 5150 u8 op_mod[0x10]; 5151 5152 u8 modify_header_id[0x20]; 5153 5154 u8 reserved_at_60[0x20]; 5155 }; 5156 5157 struct mlx5_ifc_query_dct_out_bits { 5158 u8 status[0x8]; 5159 u8 reserved_at_8[0x18]; 5160 5161 u8 syndrome[0x20]; 5162 5163 u8 reserved_at_40[0x40]; 5164 5165 struct mlx5_ifc_dctc_bits dct_context_entry; 5166 5167 u8 reserved_at_280[0x180]; 5168 }; 5169 5170 struct mlx5_ifc_query_dct_in_bits { 5171 u8 opcode[0x10]; 5172 u8 reserved_at_10[0x10]; 5173 5174 u8 reserved_at_20[0x10]; 5175 u8 op_mod[0x10]; 5176 5177 u8 reserved_at_40[0x8]; 5178 u8 dctn[0x18]; 5179 5180 u8 reserved_at_60[0x20]; 5181 }; 5182 5183 struct mlx5_ifc_query_cq_out_bits { 5184 u8 status[0x8]; 5185 u8 reserved_at_8[0x18]; 5186 5187 u8 syndrome[0x20]; 5188 5189 u8 reserved_at_40[0x40]; 5190 5191 struct mlx5_ifc_cqc_bits cq_context; 5192 5193 u8 reserved_at_280[0x600]; 5194 5195 u8 pas[0][0x40]; 5196 }; 5197 5198 struct mlx5_ifc_query_cq_in_bits { 5199 u8 opcode[0x10]; 5200 u8 reserved_at_10[0x10]; 5201 5202 u8 reserved_at_20[0x10]; 5203 u8 op_mod[0x10]; 5204 5205 u8 reserved_at_40[0x8]; 5206 u8 cqn[0x18]; 5207 5208 u8 reserved_at_60[0x20]; 5209 }; 5210 5211 struct mlx5_ifc_query_cong_status_out_bits { 5212 u8 status[0x8]; 5213 u8 reserved_at_8[0x18]; 5214 5215 u8 syndrome[0x20]; 5216 5217 u8 reserved_at_40[0x20]; 5218 5219 u8 enable[0x1]; 5220 u8 tag_enable[0x1]; 5221 u8 reserved_at_62[0x1e]; 5222 }; 5223 5224 struct mlx5_ifc_query_cong_status_in_bits { 5225 u8 opcode[0x10]; 5226 u8 reserved_at_10[0x10]; 5227 5228 u8 reserved_at_20[0x10]; 5229 u8 op_mod[0x10]; 5230 5231 u8 reserved_at_40[0x18]; 5232 u8 priority[0x4]; 5233 u8 cong_protocol[0x4]; 5234 5235 u8 reserved_at_60[0x20]; 5236 }; 5237 5238 struct mlx5_ifc_query_cong_statistics_out_bits { 5239 u8 status[0x8]; 5240 u8 reserved_at_8[0x18]; 5241 5242 u8 syndrome[0x20]; 5243 5244 u8 reserved_at_40[0x40]; 5245 5246 u8 rp_cur_flows[0x20]; 5247 5248 u8 sum_flows[0x20]; 5249 5250 u8 rp_cnp_ignored_high[0x20]; 5251 5252 u8 rp_cnp_ignored_low[0x20]; 5253 5254 u8 rp_cnp_handled_high[0x20]; 5255 5256 u8 rp_cnp_handled_low[0x20]; 5257 5258 u8 reserved_at_140[0x100]; 5259 5260 u8 time_stamp_high[0x20]; 5261 5262 u8 time_stamp_low[0x20]; 5263 5264 u8 accumulators_period[0x20]; 5265 5266 u8 np_ecn_marked_roce_packets_high[0x20]; 5267 5268 u8 np_ecn_marked_roce_packets_low[0x20]; 5269 5270 u8 np_cnp_sent_high[0x20]; 5271 5272 u8 np_cnp_sent_low[0x20]; 5273 5274 u8 reserved_at_320[0x560]; 5275 }; 5276 5277 struct mlx5_ifc_query_cong_statistics_in_bits { 5278 u8 opcode[0x10]; 5279 u8 reserved_at_10[0x10]; 5280 5281 u8 reserved_at_20[0x10]; 5282 u8 op_mod[0x10]; 5283 5284 u8 clear[0x1]; 5285 u8 reserved_at_41[0x1f]; 5286 5287 u8 reserved_at_60[0x20]; 5288 }; 5289 5290 struct mlx5_ifc_query_cong_params_out_bits { 5291 u8 status[0x8]; 5292 u8 reserved_at_8[0x18]; 5293 5294 u8 syndrome[0x20]; 5295 5296 u8 reserved_at_40[0x40]; 5297 5298 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5299 }; 5300 5301 struct mlx5_ifc_query_cong_params_in_bits { 5302 u8 opcode[0x10]; 5303 u8 reserved_at_10[0x10]; 5304 5305 u8 reserved_at_20[0x10]; 5306 u8 op_mod[0x10]; 5307 5308 u8 reserved_at_40[0x1c]; 5309 u8 cong_protocol[0x4]; 5310 5311 u8 reserved_at_60[0x20]; 5312 }; 5313 5314 struct mlx5_ifc_query_adapter_out_bits { 5315 u8 status[0x8]; 5316 u8 reserved_at_8[0x18]; 5317 5318 u8 syndrome[0x20]; 5319 5320 u8 reserved_at_40[0x40]; 5321 5322 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5323 }; 5324 5325 struct mlx5_ifc_query_adapter_in_bits { 5326 u8 opcode[0x10]; 5327 u8 reserved_at_10[0x10]; 5328 5329 u8 reserved_at_20[0x10]; 5330 u8 op_mod[0x10]; 5331 5332 u8 reserved_at_40[0x40]; 5333 }; 5334 5335 struct mlx5_ifc_qp_2rst_out_bits { 5336 u8 status[0x8]; 5337 u8 reserved_at_8[0x18]; 5338 5339 u8 syndrome[0x20]; 5340 5341 u8 reserved_at_40[0x40]; 5342 }; 5343 5344 struct mlx5_ifc_qp_2rst_in_bits { 5345 u8 opcode[0x10]; 5346 u8 uid[0x10]; 5347 5348 u8 reserved_at_20[0x10]; 5349 u8 op_mod[0x10]; 5350 5351 u8 reserved_at_40[0x8]; 5352 u8 qpn[0x18]; 5353 5354 u8 reserved_at_60[0x20]; 5355 }; 5356 5357 struct mlx5_ifc_qp_2err_out_bits { 5358 u8 status[0x8]; 5359 u8 reserved_at_8[0x18]; 5360 5361 u8 syndrome[0x20]; 5362 5363 u8 reserved_at_40[0x40]; 5364 }; 5365 5366 struct mlx5_ifc_qp_2err_in_bits { 5367 u8 opcode[0x10]; 5368 u8 uid[0x10]; 5369 5370 u8 reserved_at_20[0x10]; 5371 u8 op_mod[0x10]; 5372 5373 u8 reserved_at_40[0x8]; 5374 u8 qpn[0x18]; 5375 5376 u8 reserved_at_60[0x20]; 5377 }; 5378 5379 struct mlx5_ifc_page_fault_resume_out_bits { 5380 u8 status[0x8]; 5381 u8 reserved_at_8[0x18]; 5382 5383 u8 syndrome[0x20]; 5384 5385 u8 reserved_at_40[0x40]; 5386 }; 5387 5388 struct mlx5_ifc_page_fault_resume_in_bits { 5389 u8 opcode[0x10]; 5390 u8 reserved_at_10[0x10]; 5391 5392 u8 reserved_at_20[0x10]; 5393 u8 op_mod[0x10]; 5394 5395 u8 error[0x1]; 5396 u8 reserved_at_41[0x4]; 5397 u8 page_fault_type[0x3]; 5398 u8 wq_number[0x18]; 5399 5400 u8 reserved_at_60[0x8]; 5401 u8 token[0x18]; 5402 }; 5403 5404 struct mlx5_ifc_nop_out_bits { 5405 u8 status[0x8]; 5406 u8 reserved_at_8[0x18]; 5407 5408 u8 syndrome[0x20]; 5409 5410 u8 reserved_at_40[0x40]; 5411 }; 5412 5413 struct mlx5_ifc_nop_in_bits { 5414 u8 opcode[0x10]; 5415 u8 reserved_at_10[0x10]; 5416 5417 u8 reserved_at_20[0x10]; 5418 u8 op_mod[0x10]; 5419 5420 u8 reserved_at_40[0x40]; 5421 }; 5422 5423 struct mlx5_ifc_modify_vport_state_out_bits { 5424 u8 status[0x8]; 5425 u8 reserved_at_8[0x18]; 5426 5427 u8 syndrome[0x20]; 5428 5429 u8 reserved_at_40[0x40]; 5430 }; 5431 5432 struct mlx5_ifc_modify_vport_state_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_at_10[0x10]; 5435 5436 u8 reserved_at_20[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 other_vport[0x1]; 5440 u8 reserved_at_41[0xf]; 5441 u8 vport_number[0x10]; 5442 5443 u8 reserved_at_60[0x18]; 5444 u8 admin_state[0x4]; 5445 u8 reserved_at_7c[0x4]; 5446 }; 5447 5448 struct mlx5_ifc_modify_tis_out_bits { 5449 u8 status[0x8]; 5450 u8 reserved_at_8[0x18]; 5451 5452 u8 syndrome[0x20]; 5453 5454 u8 reserved_at_40[0x40]; 5455 }; 5456 5457 struct mlx5_ifc_modify_tis_bitmask_bits { 5458 u8 reserved_at_0[0x20]; 5459 5460 u8 reserved_at_20[0x1d]; 5461 u8 lag_tx_port_affinity[0x1]; 5462 u8 strict_lag_tx_port_affinity[0x1]; 5463 u8 prio[0x1]; 5464 }; 5465 5466 struct mlx5_ifc_modify_tis_in_bits { 5467 u8 opcode[0x10]; 5468 u8 uid[0x10]; 5469 5470 u8 reserved_at_20[0x10]; 5471 u8 op_mod[0x10]; 5472 5473 u8 reserved_at_40[0x8]; 5474 u8 tisn[0x18]; 5475 5476 u8 reserved_at_60[0x20]; 5477 5478 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5479 5480 u8 reserved_at_c0[0x40]; 5481 5482 struct mlx5_ifc_tisc_bits ctx; 5483 }; 5484 5485 struct mlx5_ifc_modify_tir_bitmask_bits { 5486 u8 reserved_at_0[0x20]; 5487 5488 u8 reserved_at_20[0x1b]; 5489 u8 self_lb_en[0x1]; 5490 u8 reserved_at_3c[0x1]; 5491 u8 hash[0x1]; 5492 u8 reserved_at_3e[0x1]; 5493 u8 lro[0x1]; 5494 }; 5495 5496 struct mlx5_ifc_modify_tir_out_bits { 5497 u8 status[0x8]; 5498 u8 reserved_at_8[0x18]; 5499 5500 u8 syndrome[0x20]; 5501 5502 u8 reserved_at_40[0x40]; 5503 }; 5504 5505 struct mlx5_ifc_modify_tir_in_bits { 5506 u8 opcode[0x10]; 5507 u8 uid[0x10]; 5508 5509 u8 reserved_at_20[0x10]; 5510 u8 op_mod[0x10]; 5511 5512 u8 reserved_at_40[0x8]; 5513 u8 tirn[0x18]; 5514 5515 u8 reserved_at_60[0x20]; 5516 5517 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5518 5519 u8 reserved_at_c0[0x40]; 5520 5521 struct mlx5_ifc_tirc_bits ctx; 5522 }; 5523 5524 struct mlx5_ifc_modify_sq_out_bits { 5525 u8 status[0x8]; 5526 u8 reserved_at_8[0x18]; 5527 5528 u8 syndrome[0x20]; 5529 5530 u8 reserved_at_40[0x40]; 5531 }; 5532 5533 struct mlx5_ifc_modify_sq_in_bits { 5534 u8 opcode[0x10]; 5535 u8 uid[0x10]; 5536 5537 u8 reserved_at_20[0x10]; 5538 u8 op_mod[0x10]; 5539 5540 u8 sq_state[0x4]; 5541 u8 reserved_at_44[0x4]; 5542 u8 sqn[0x18]; 5543 5544 u8 reserved_at_60[0x20]; 5545 5546 u8 modify_bitmask[0x40]; 5547 5548 u8 reserved_at_c0[0x40]; 5549 5550 struct mlx5_ifc_sqc_bits ctx; 5551 }; 5552 5553 struct mlx5_ifc_modify_scheduling_element_out_bits { 5554 u8 status[0x8]; 5555 u8 reserved_at_8[0x18]; 5556 5557 u8 syndrome[0x20]; 5558 5559 u8 reserved_at_40[0x1c0]; 5560 }; 5561 5562 enum { 5563 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5564 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5565 }; 5566 5567 struct mlx5_ifc_modify_scheduling_element_in_bits { 5568 u8 opcode[0x10]; 5569 u8 reserved_at_10[0x10]; 5570 5571 u8 reserved_at_20[0x10]; 5572 u8 op_mod[0x10]; 5573 5574 u8 scheduling_hierarchy[0x8]; 5575 u8 reserved_at_48[0x18]; 5576 5577 u8 scheduling_element_id[0x20]; 5578 5579 u8 reserved_at_80[0x20]; 5580 5581 u8 modify_bitmask[0x20]; 5582 5583 u8 reserved_at_c0[0x40]; 5584 5585 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5586 5587 u8 reserved_at_300[0x100]; 5588 }; 5589 5590 struct mlx5_ifc_modify_rqt_out_bits { 5591 u8 status[0x8]; 5592 u8 reserved_at_8[0x18]; 5593 5594 u8 syndrome[0x20]; 5595 5596 u8 reserved_at_40[0x40]; 5597 }; 5598 5599 struct mlx5_ifc_rqt_bitmask_bits { 5600 u8 reserved_at_0[0x20]; 5601 5602 u8 reserved_at_20[0x1f]; 5603 u8 rqn_list[0x1]; 5604 }; 5605 5606 struct mlx5_ifc_modify_rqt_in_bits { 5607 u8 opcode[0x10]; 5608 u8 uid[0x10]; 5609 5610 u8 reserved_at_20[0x10]; 5611 u8 op_mod[0x10]; 5612 5613 u8 reserved_at_40[0x8]; 5614 u8 rqtn[0x18]; 5615 5616 u8 reserved_at_60[0x20]; 5617 5618 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5619 5620 u8 reserved_at_c0[0x40]; 5621 5622 struct mlx5_ifc_rqtc_bits ctx; 5623 }; 5624 5625 struct mlx5_ifc_modify_rq_out_bits { 5626 u8 status[0x8]; 5627 u8 reserved_at_8[0x18]; 5628 5629 u8 syndrome[0x20]; 5630 5631 u8 reserved_at_40[0x40]; 5632 }; 5633 5634 enum { 5635 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5636 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5637 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5638 }; 5639 5640 struct mlx5_ifc_modify_rq_in_bits { 5641 u8 opcode[0x10]; 5642 u8 uid[0x10]; 5643 5644 u8 reserved_at_20[0x10]; 5645 u8 op_mod[0x10]; 5646 5647 u8 rq_state[0x4]; 5648 u8 reserved_at_44[0x4]; 5649 u8 rqn[0x18]; 5650 5651 u8 reserved_at_60[0x20]; 5652 5653 u8 modify_bitmask[0x40]; 5654 5655 u8 reserved_at_c0[0x40]; 5656 5657 struct mlx5_ifc_rqc_bits ctx; 5658 }; 5659 5660 struct mlx5_ifc_modify_rmp_out_bits { 5661 u8 status[0x8]; 5662 u8 reserved_at_8[0x18]; 5663 5664 u8 syndrome[0x20]; 5665 5666 u8 reserved_at_40[0x40]; 5667 }; 5668 5669 struct mlx5_ifc_rmp_bitmask_bits { 5670 u8 reserved_at_0[0x20]; 5671 5672 u8 reserved_at_20[0x1f]; 5673 u8 lwm[0x1]; 5674 }; 5675 5676 struct mlx5_ifc_modify_rmp_in_bits { 5677 u8 opcode[0x10]; 5678 u8 uid[0x10]; 5679 5680 u8 reserved_at_20[0x10]; 5681 u8 op_mod[0x10]; 5682 5683 u8 rmp_state[0x4]; 5684 u8 reserved_at_44[0x4]; 5685 u8 rmpn[0x18]; 5686 5687 u8 reserved_at_60[0x20]; 5688 5689 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5690 5691 u8 reserved_at_c0[0x40]; 5692 5693 struct mlx5_ifc_rmpc_bits ctx; 5694 }; 5695 5696 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5697 u8 status[0x8]; 5698 u8 reserved_at_8[0x18]; 5699 5700 u8 syndrome[0x20]; 5701 5702 u8 reserved_at_40[0x40]; 5703 }; 5704 5705 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5706 u8 reserved_at_0[0x12]; 5707 u8 affiliation[0x1]; 5708 u8 reserved_at_13[0x1]; 5709 u8 disable_uc_local_lb[0x1]; 5710 u8 disable_mc_local_lb[0x1]; 5711 u8 node_guid[0x1]; 5712 u8 port_guid[0x1]; 5713 u8 min_inline[0x1]; 5714 u8 mtu[0x1]; 5715 u8 change_event[0x1]; 5716 u8 promisc[0x1]; 5717 u8 permanent_address[0x1]; 5718 u8 addresses_list[0x1]; 5719 u8 roce_en[0x1]; 5720 u8 reserved_at_1f[0x1]; 5721 }; 5722 5723 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5724 u8 opcode[0x10]; 5725 u8 reserved_at_10[0x10]; 5726 5727 u8 reserved_at_20[0x10]; 5728 u8 op_mod[0x10]; 5729 5730 u8 other_vport[0x1]; 5731 u8 reserved_at_41[0xf]; 5732 u8 vport_number[0x10]; 5733 5734 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5735 5736 u8 reserved_at_80[0x780]; 5737 5738 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5739 }; 5740 5741 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5742 u8 status[0x8]; 5743 u8 reserved_at_8[0x18]; 5744 5745 u8 syndrome[0x20]; 5746 5747 u8 reserved_at_40[0x40]; 5748 }; 5749 5750 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5751 u8 opcode[0x10]; 5752 u8 reserved_at_10[0x10]; 5753 5754 u8 reserved_at_20[0x10]; 5755 u8 op_mod[0x10]; 5756 5757 u8 other_vport[0x1]; 5758 u8 reserved_at_41[0xb]; 5759 u8 port_num[0x4]; 5760 u8 vport_number[0x10]; 5761 5762 u8 reserved_at_60[0x20]; 5763 5764 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5765 }; 5766 5767 struct mlx5_ifc_modify_cq_out_bits { 5768 u8 status[0x8]; 5769 u8 reserved_at_8[0x18]; 5770 5771 u8 syndrome[0x20]; 5772 5773 u8 reserved_at_40[0x40]; 5774 }; 5775 5776 enum { 5777 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5778 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5779 }; 5780 5781 struct mlx5_ifc_modify_cq_in_bits { 5782 u8 opcode[0x10]; 5783 u8 uid[0x10]; 5784 5785 u8 reserved_at_20[0x10]; 5786 u8 op_mod[0x10]; 5787 5788 u8 reserved_at_40[0x8]; 5789 u8 cqn[0x18]; 5790 5791 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5792 5793 struct mlx5_ifc_cqc_bits cq_context; 5794 5795 u8 reserved_at_280[0x40]; 5796 5797 u8 cq_umem_valid[0x1]; 5798 u8 reserved_at_2c1[0x5bf]; 5799 5800 u8 pas[0][0x40]; 5801 }; 5802 5803 struct mlx5_ifc_modify_cong_status_out_bits { 5804 u8 status[0x8]; 5805 u8 reserved_at_8[0x18]; 5806 5807 u8 syndrome[0x20]; 5808 5809 u8 reserved_at_40[0x40]; 5810 }; 5811 5812 struct mlx5_ifc_modify_cong_status_in_bits { 5813 u8 opcode[0x10]; 5814 u8 reserved_at_10[0x10]; 5815 5816 u8 reserved_at_20[0x10]; 5817 u8 op_mod[0x10]; 5818 5819 u8 reserved_at_40[0x18]; 5820 u8 priority[0x4]; 5821 u8 cong_protocol[0x4]; 5822 5823 u8 enable[0x1]; 5824 u8 tag_enable[0x1]; 5825 u8 reserved_at_62[0x1e]; 5826 }; 5827 5828 struct mlx5_ifc_modify_cong_params_out_bits { 5829 u8 status[0x8]; 5830 u8 reserved_at_8[0x18]; 5831 5832 u8 syndrome[0x20]; 5833 5834 u8 reserved_at_40[0x40]; 5835 }; 5836 5837 struct mlx5_ifc_modify_cong_params_in_bits { 5838 u8 opcode[0x10]; 5839 u8 reserved_at_10[0x10]; 5840 5841 u8 reserved_at_20[0x10]; 5842 u8 op_mod[0x10]; 5843 5844 u8 reserved_at_40[0x1c]; 5845 u8 cong_protocol[0x4]; 5846 5847 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5848 5849 u8 reserved_at_80[0x80]; 5850 5851 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5852 }; 5853 5854 struct mlx5_ifc_manage_pages_out_bits { 5855 u8 status[0x8]; 5856 u8 reserved_at_8[0x18]; 5857 5858 u8 syndrome[0x20]; 5859 5860 u8 output_num_entries[0x20]; 5861 5862 u8 reserved_at_60[0x20]; 5863 5864 u8 pas[0][0x40]; 5865 }; 5866 5867 enum { 5868 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5869 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5870 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5871 }; 5872 5873 struct mlx5_ifc_manage_pages_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_at_10[0x10]; 5876 5877 u8 reserved_at_20[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 reserved_at_40[0x10]; 5881 u8 function_id[0x10]; 5882 5883 u8 input_num_entries[0x20]; 5884 5885 u8 pas[0][0x40]; 5886 }; 5887 5888 struct mlx5_ifc_mad_ifc_out_bits { 5889 u8 status[0x8]; 5890 u8 reserved_at_8[0x18]; 5891 5892 u8 syndrome[0x20]; 5893 5894 u8 reserved_at_40[0x40]; 5895 5896 u8 response_mad_packet[256][0x8]; 5897 }; 5898 5899 struct mlx5_ifc_mad_ifc_in_bits { 5900 u8 opcode[0x10]; 5901 u8 reserved_at_10[0x10]; 5902 5903 u8 reserved_at_20[0x10]; 5904 u8 op_mod[0x10]; 5905 5906 u8 remote_lid[0x10]; 5907 u8 reserved_at_50[0x8]; 5908 u8 port[0x8]; 5909 5910 u8 reserved_at_60[0x20]; 5911 5912 u8 mad[256][0x8]; 5913 }; 5914 5915 struct mlx5_ifc_init_hca_out_bits { 5916 u8 status[0x8]; 5917 u8 reserved_at_8[0x18]; 5918 5919 u8 syndrome[0x20]; 5920 5921 u8 reserved_at_40[0x40]; 5922 }; 5923 5924 struct mlx5_ifc_init_hca_in_bits { 5925 u8 opcode[0x10]; 5926 u8 reserved_at_10[0x10]; 5927 5928 u8 reserved_at_20[0x10]; 5929 u8 op_mod[0x10]; 5930 5931 u8 reserved_at_40[0x40]; 5932 u8 sw_owner_id[4][0x20]; 5933 }; 5934 5935 struct mlx5_ifc_init2rtr_qp_out_bits { 5936 u8 status[0x8]; 5937 u8 reserved_at_8[0x18]; 5938 5939 u8 syndrome[0x20]; 5940 5941 u8 reserved_at_40[0x40]; 5942 }; 5943 5944 struct mlx5_ifc_init2rtr_qp_in_bits { 5945 u8 opcode[0x10]; 5946 u8 uid[0x10]; 5947 5948 u8 reserved_at_20[0x10]; 5949 u8 op_mod[0x10]; 5950 5951 u8 reserved_at_40[0x8]; 5952 u8 qpn[0x18]; 5953 5954 u8 reserved_at_60[0x20]; 5955 5956 u8 opt_param_mask[0x20]; 5957 5958 u8 reserved_at_a0[0x20]; 5959 5960 struct mlx5_ifc_qpc_bits qpc; 5961 5962 u8 reserved_at_800[0x80]; 5963 }; 5964 5965 struct mlx5_ifc_init2init_qp_out_bits { 5966 u8 status[0x8]; 5967 u8 reserved_at_8[0x18]; 5968 5969 u8 syndrome[0x20]; 5970 5971 u8 reserved_at_40[0x40]; 5972 }; 5973 5974 struct mlx5_ifc_init2init_qp_in_bits { 5975 u8 opcode[0x10]; 5976 u8 uid[0x10]; 5977 5978 u8 reserved_at_20[0x10]; 5979 u8 op_mod[0x10]; 5980 5981 u8 reserved_at_40[0x8]; 5982 u8 qpn[0x18]; 5983 5984 u8 reserved_at_60[0x20]; 5985 5986 u8 opt_param_mask[0x20]; 5987 5988 u8 reserved_at_a0[0x20]; 5989 5990 struct mlx5_ifc_qpc_bits qpc; 5991 5992 u8 reserved_at_800[0x80]; 5993 }; 5994 5995 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5996 u8 status[0x8]; 5997 u8 reserved_at_8[0x18]; 5998 5999 u8 syndrome[0x20]; 6000 6001 u8 reserved_at_40[0x40]; 6002 6003 u8 packet_headers_log[128][0x8]; 6004 6005 u8 packet_syndrome[64][0x8]; 6006 }; 6007 6008 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6009 u8 opcode[0x10]; 6010 u8 reserved_at_10[0x10]; 6011 6012 u8 reserved_at_20[0x10]; 6013 u8 op_mod[0x10]; 6014 6015 u8 reserved_at_40[0x40]; 6016 }; 6017 6018 struct mlx5_ifc_gen_eqe_in_bits { 6019 u8 opcode[0x10]; 6020 u8 reserved_at_10[0x10]; 6021 6022 u8 reserved_at_20[0x10]; 6023 u8 op_mod[0x10]; 6024 6025 u8 reserved_at_40[0x18]; 6026 u8 eq_number[0x8]; 6027 6028 u8 reserved_at_60[0x20]; 6029 6030 u8 eqe[64][0x8]; 6031 }; 6032 6033 struct mlx5_ifc_gen_eq_out_bits { 6034 u8 status[0x8]; 6035 u8 reserved_at_8[0x18]; 6036 6037 u8 syndrome[0x20]; 6038 6039 u8 reserved_at_40[0x40]; 6040 }; 6041 6042 struct mlx5_ifc_enable_hca_out_bits { 6043 u8 status[0x8]; 6044 u8 reserved_at_8[0x18]; 6045 6046 u8 syndrome[0x20]; 6047 6048 u8 reserved_at_40[0x20]; 6049 }; 6050 6051 struct mlx5_ifc_enable_hca_in_bits { 6052 u8 opcode[0x10]; 6053 u8 reserved_at_10[0x10]; 6054 6055 u8 reserved_at_20[0x10]; 6056 u8 op_mod[0x10]; 6057 6058 u8 reserved_at_40[0x10]; 6059 u8 function_id[0x10]; 6060 6061 u8 reserved_at_60[0x20]; 6062 }; 6063 6064 struct mlx5_ifc_drain_dct_out_bits { 6065 u8 status[0x8]; 6066 u8 reserved_at_8[0x18]; 6067 6068 u8 syndrome[0x20]; 6069 6070 u8 reserved_at_40[0x40]; 6071 }; 6072 6073 struct mlx5_ifc_drain_dct_in_bits { 6074 u8 opcode[0x10]; 6075 u8 uid[0x10]; 6076 6077 u8 reserved_at_20[0x10]; 6078 u8 op_mod[0x10]; 6079 6080 u8 reserved_at_40[0x8]; 6081 u8 dctn[0x18]; 6082 6083 u8 reserved_at_60[0x20]; 6084 }; 6085 6086 struct mlx5_ifc_disable_hca_out_bits { 6087 u8 status[0x8]; 6088 u8 reserved_at_8[0x18]; 6089 6090 u8 syndrome[0x20]; 6091 6092 u8 reserved_at_40[0x20]; 6093 }; 6094 6095 struct mlx5_ifc_disable_hca_in_bits { 6096 u8 opcode[0x10]; 6097 u8 reserved_at_10[0x10]; 6098 6099 u8 reserved_at_20[0x10]; 6100 u8 op_mod[0x10]; 6101 6102 u8 reserved_at_40[0x10]; 6103 u8 function_id[0x10]; 6104 6105 u8 reserved_at_60[0x20]; 6106 }; 6107 6108 struct mlx5_ifc_detach_from_mcg_out_bits { 6109 u8 status[0x8]; 6110 u8 reserved_at_8[0x18]; 6111 6112 u8 syndrome[0x20]; 6113 6114 u8 reserved_at_40[0x40]; 6115 }; 6116 6117 struct mlx5_ifc_detach_from_mcg_in_bits { 6118 u8 opcode[0x10]; 6119 u8 uid[0x10]; 6120 6121 u8 reserved_at_20[0x10]; 6122 u8 op_mod[0x10]; 6123 6124 u8 reserved_at_40[0x8]; 6125 u8 qpn[0x18]; 6126 6127 u8 reserved_at_60[0x20]; 6128 6129 u8 multicast_gid[16][0x8]; 6130 }; 6131 6132 struct mlx5_ifc_destroy_xrq_out_bits { 6133 u8 status[0x8]; 6134 u8 reserved_at_8[0x18]; 6135 6136 u8 syndrome[0x20]; 6137 6138 u8 reserved_at_40[0x40]; 6139 }; 6140 6141 struct mlx5_ifc_destroy_xrq_in_bits { 6142 u8 opcode[0x10]; 6143 u8 uid[0x10]; 6144 6145 u8 reserved_at_20[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 reserved_at_40[0x8]; 6149 u8 xrqn[0x18]; 6150 6151 u8 reserved_at_60[0x20]; 6152 }; 6153 6154 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6155 u8 status[0x8]; 6156 u8 reserved_at_8[0x18]; 6157 6158 u8 syndrome[0x20]; 6159 6160 u8 reserved_at_40[0x40]; 6161 }; 6162 6163 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6164 u8 opcode[0x10]; 6165 u8 uid[0x10]; 6166 6167 u8 reserved_at_20[0x10]; 6168 u8 op_mod[0x10]; 6169 6170 u8 reserved_at_40[0x8]; 6171 u8 xrc_srqn[0x18]; 6172 6173 u8 reserved_at_60[0x20]; 6174 }; 6175 6176 struct mlx5_ifc_destroy_tis_out_bits { 6177 u8 status[0x8]; 6178 u8 reserved_at_8[0x18]; 6179 6180 u8 syndrome[0x20]; 6181 6182 u8 reserved_at_40[0x40]; 6183 }; 6184 6185 struct mlx5_ifc_destroy_tis_in_bits { 6186 u8 opcode[0x10]; 6187 u8 uid[0x10]; 6188 6189 u8 reserved_at_20[0x10]; 6190 u8 op_mod[0x10]; 6191 6192 u8 reserved_at_40[0x8]; 6193 u8 tisn[0x18]; 6194 6195 u8 reserved_at_60[0x20]; 6196 }; 6197 6198 struct mlx5_ifc_destroy_tir_out_bits { 6199 u8 status[0x8]; 6200 u8 reserved_at_8[0x18]; 6201 6202 u8 syndrome[0x20]; 6203 6204 u8 reserved_at_40[0x40]; 6205 }; 6206 6207 struct mlx5_ifc_destroy_tir_in_bits { 6208 u8 opcode[0x10]; 6209 u8 uid[0x10]; 6210 6211 u8 reserved_at_20[0x10]; 6212 u8 op_mod[0x10]; 6213 6214 u8 reserved_at_40[0x8]; 6215 u8 tirn[0x18]; 6216 6217 u8 reserved_at_60[0x20]; 6218 }; 6219 6220 struct mlx5_ifc_destroy_srq_out_bits { 6221 u8 status[0x8]; 6222 u8 reserved_at_8[0x18]; 6223 6224 u8 syndrome[0x20]; 6225 6226 u8 reserved_at_40[0x40]; 6227 }; 6228 6229 struct mlx5_ifc_destroy_srq_in_bits { 6230 u8 opcode[0x10]; 6231 u8 uid[0x10]; 6232 6233 u8 reserved_at_20[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 reserved_at_40[0x8]; 6237 u8 srqn[0x18]; 6238 6239 u8 reserved_at_60[0x20]; 6240 }; 6241 6242 struct mlx5_ifc_destroy_sq_out_bits { 6243 u8 status[0x8]; 6244 u8 reserved_at_8[0x18]; 6245 6246 u8 syndrome[0x20]; 6247 6248 u8 reserved_at_40[0x40]; 6249 }; 6250 6251 struct mlx5_ifc_destroy_sq_in_bits { 6252 u8 opcode[0x10]; 6253 u8 uid[0x10]; 6254 6255 u8 reserved_at_20[0x10]; 6256 u8 op_mod[0x10]; 6257 6258 u8 reserved_at_40[0x8]; 6259 u8 sqn[0x18]; 6260 6261 u8 reserved_at_60[0x20]; 6262 }; 6263 6264 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6265 u8 status[0x8]; 6266 u8 reserved_at_8[0x18]; 6267 6268 u8 syndrome[0x20]; 6269 6270 u8 reserved_at_40[0x1c0]; 6271 }; 6272 6273 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6274 u8 opcode[0x10]; 6275 u8 reserved_at_10[0x10]; 6276 6277 u8 reserved_at_20[0x10]; 6278 u8 op_mod[0x10]; 6279 6280 u8 scheduling_hierarchy[0x8]; 6281 u8 reserved_at_48[0x18]; 6282 6283 u8 scheduling_element_id[0x20]; 6284 6285 u8 reserved_at_80[0x180]; 6286 }; 6287 6288 struct mlx5_ifc_destroy_rqt_out_bits { 6289 u8 status[0x8]; 6290 u8 reserved_at_8[0x18]; 6291 6292 u8 syndrome[0x20]; 6293 6294 u8 reserved_at_40[0x40]; 6295 }; 6296 6297 struct mlx5_ifc_destroy_rqt_in_bits { 6298 u8 opcode[0x10]; 6299 u8 uid[0x10]; 6300 6301 u8 reserved_at_20[0x10]; 6302 u8 op_mod[0x10]; 6303 6304 u8 reserved_at_40[0x8]; 6305 u8 rqtn[0x18]; 6306 6307 u8 reserved_at_60[0x20]; 6308 }; 6309 6310 struct mlx5_ifc_destroy_rq_out_bits { 6311 u8 status[0x8]; 6312 u8 reserved_at_8[0x18]; 6313 6314 u8 syndrome[0x20]; 6315 6316 u8 reserved_at_40[0x40]; 6317 }; 6318 6319 struct mlx5_ifc_destroy_rq_in_bits { 6320 u8 opcode[0x10]; 6321 u8 uid[0x10]; 6322 6323 u8 reserved_at_20[0x10]; 6324 u8 op_mod[0x10]; 6325 6326 u8 reserved_at_40[0x8]; 6327 u8 rqn[0x18]; 6328 6329 u8 reserved_at_60[0x20]; 6330 }; 6331 6332 struct mlx5_ifc_set_delay_drop_params_in_bits { 6333 u8 opcode[0x10]; 6334 u8 reserved_at_10[0x10]; 6335 6336 u8 reserved_at_20[0x10]; 6337 u8 op_mod[0x10]; 6338 6339 u8 reserved_at_40[0x20]; 6340 6341 u8 reserved_at_60[0x10]; 6342 u8 delay_drop_timeout[0x10]; 6343 }; 6344 6345 struct mlx5_ifc_set_delay_drop_params_out_bits { 6346 u8 status[0x8]; 6347 u8 reserved_at_8[0x18]; 6348 6349 u8 syndrome[0x20]; 6350 6351 u8 reserved_at_40[0x40]; 6352 }; 6353 6354 struct mlx5_ifc_destroy_rmp_out_bits { 6355 u8 status[0x8]; 6356 u8 reserved_at_8[0x18]; 6357 6358 u8 syndrome[0x20]; 6359 6360 u8 reserved_at_40[0x40]; 6361 }; 6362 6363 struct mlx5_ifc_destroy_rmp_in_bits { 6364 u8 opcode[0x10]; 6365 u8 uid[0x10]; 6366 6367 u8 reserved_at_20[0x10]; 6368 u8 op_mod[0x10]; 6369 6370 u8 reserved_at_40[0x8]; 6371 u8 rmpn[0x18]; 6372 6373 u8 reserved_at_60[0x20]; 6374 }; 6375 6376 struct mlx5_ifc_destroy_qp_out_bits { 6377 u8 status[0x8]; 6378 u8 reserved_at_8[0x18]; 6379 6380 u8 syndrome[0x20]; 6381 6382 u8 reserved_at_40[0x40]; 6383 }; 6384 6385 struct mlx5_ifc_destroy_qp_in_bits { 6386 u8 opcode[0x10]; 6387 u8 uid[0x10]; 6388 6389 u8 reserved_at_20[0x10]; 6390 u8 op_mod[0x10]; 6391 6392 u8 reserved_at_40[0x8]; 6393 u8 qpn[0x18]; 6394 6395 u8 reserved_at_60[0x20]; 6396 }; 6397 6398 struct mlx5_ifc_destroy_psv_out_bits { 6399 u8 status[0x8]; 6400 u8 reserved_at_8[0x18]; 6401 6402 u8 syndrome[0x20]; 6403 6404 u8 reserved_at_40[0x40]; 6405 }; 6406 6407 struct mlx5_ifc_destroy_psv_in_bits { 6408 u8 opcode[0x10]; 6409 u8 reserved_at_10[0x10]; 6410 6411 u8 reserved_at_20[0x10]; 6412 u8 op_mod[0x10]; 6413 6414 u8 reserved_at_40[0x8]; 6415 u8 psvn[0x18]; 6416 6417 u8 reserved_at_60[0x20]; 6418 }; 6419 6420 struct mlx5_ifc_destroy_mkey_out_bits { 6421 u8 status[0x8]; 6422 u8 reserved_at_8[0x18]; 6423 6424 u8 syndrome[0x20]; 6425 6426 u8 reserved_at_40[0x40]; 6427 }; 6428 6429 struct mlx5_ifc_destroy_mkey_in_bits { 6430 u8 opcode[0x10]; 6431 u8 reserved_at_10[0x10]; 6432 6433 u8 reserved_at_20[0x10]; 6434 u8 op_mod[0x10]; 6435 6436 u8 reserved_at_40[0x8]; 6437 u8 mkey_index[0x18]; 6438 6439 u8 reserved_at_60[0x20]; 6440 }; 6441 6442 struct mlx5_ifc_destroy_flow_table_out_bits { 6443 u8 status[0x8]; 6444 u8 reserved_at_8[0x18]; 6445 6446 u8 syndrome[0x20]; 6447 6448 u8 reserved_at_40[0x40]; 6449 }; 6450 6451 struct mlx5_ifc_destroy_flow_table_in_bits { 6452 u8 opcode[0x10]; 6453 u8 reserved_at_10[0x10]; 6454 6455 u8 reserved_at_20[0x10]; 6456 u8 op_mod[0x10]; 6457 6458 u8 other_vport[0x1]; 6459 u8 reserved_at_41[0xf]; 6460 u8 vport_number[0x10]; 6461 6462 u8 reserved_at_60[0x20]; 6463 6464 u8 table_type[0x8]; 6465 u8 reserved_at_88[0x18]; 6466 6467 u8 reserved_at_a0[0x8]; 6468 u8 table_id[0x18]; 6469 6470 u8 reserved_at_c0[0x140]; 6471 }; 6472 6473 struct mlx5_ifc_destroy_flow_group_out_bits { 6474 u8 status[0x8]; 6475 u8 reserved_at_8[0x18]; 6476 6477 u8 syndrome[0x20]; 6478 6479 u8 reserved_at_40[0x40]; 6480 }; 6481 6482 struct mlx5_ifc_destroy_flow_group_in_bits { 6483 u8 opcode[0x10]; 6484 u8 reserved_at_10[0x10]; 6485 6486 u8 reserved_at_20[0x10]; 6487 u8 op_mod[0x10]; 6488 6489 u8 other_vport[0x1]; 6490 u8 reserved_at_41[0xf]; 6491 u8 vport_number[0x10]; 6492 6493 u8 reserved_at_60[0x20]; 6494 6495 u8 table_type[0x8]; 6496 u8 reserved_at_88[0x18]; 6497 6498 u8 reserved_at_a0[0x8]; 6499 u8 table_id[0x18]; 6500 6501 u8 group_id[0x20]; 6502 6503 u8 reserved_at_e0[0x120]; 6504 }; 6505 6506 struct mlx5_ifc_destroy_eq_out_bits { 6507 u8 status[0x8]; 6508 u8 reserved_at_8[0x18]; 6509 6510 u8 syndrome[0x20]; 6511 6512 u8 reserved_at_40[0x40]; 6513 }; 6514 6515 struct mlx5_ifc_destroy_eq_in_bits { 6516 u8 opcode[0x10]; 6517 u8 reserved_at_10[0x10]; 6518 6519 u8 reserved_at_20[0x10]; 6520 u8 op_mod[0x10]; 6521 6522 u8 reserved_at_40[0x18]; 6523 u8 eq_number[0x8]; 6524 6525 u8 reserved_at_60[0x20]; 6526 }; 6527 6528 struct mlx5_ifc_destroy_dct_out_bits { 6529 u8 status[0x8]; 6530 u8 reserved_at_8[0x18]; 6531 6532 u8 syndrome[0x20]; 6533 6534 u8 reserved_at_40[0x40]; 6535 }; 6536 6537 struct mlx5_ifc_destroy_dct_in_bits { 6538 u8 opcode[0x10]; 6539 u8 uid[0x10]; 6540 6541 u8 reserved_at_20[0x10]; 6542 u8 op_mod[0x10]; 6543 6544 u8 reserved_at_40[0x8]; 6545 u8 dctn[0x18]; 6546 6547 u8 reserved_at_60[0x20]; 6548 }; 6549 6550 struct mlx5_ifc_destroy_cq_out_bits { 6551 u8 status[0x8]; 6552 u8 reserved_at_8[0x18]; 6553 6554 u8 syndrome[0x20]; 6555 6556 u8 reserved_at_40[0x40]; 6557 }; 6558 6559 struct mlx5_ifc_destroy_cq_in_bits { 6560 u8 opcode[0x10]; 6561 u8 uid[0x10]; 6562 6563 u8 reserved_at_20[0x10]; 6564 u8 op_mod[0x10]; 6565 6566 u8 reserved_at_40[0x8]; 6567 u8 cqn[0x18]; 6568 6569 u8 reserved_at_60[0x20]; 6570 }; 6571 6572 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6573 u8 status[0x8]; 6574 u8 reserved_at_8[0x18]; 6575 6576 u8 syndrome[0x20]; 6577 6578 u8 reserved_at_40[0x40]; 6579 }; 6580 6581 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6582 u8 opcode[0x10]; 6583 u8 reserved_at_10[0x10]; 6584 6585 u8 reserved_at_20[0x10]; 6586 u8 op_mod[0x10]; 6587 6588 u8 reserved_at_40[0x20]; 6589 6590 u8 reserved_at_60[0x10]; 6591 u8 vxlan_udp_port[0x10]; 6592 }; 6593 6594 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6595 u8 status[0x8]; 6596 u8 reserved_at_8[0x18]; 6597 6598 u8 syndrome[0x20]; 6599 6600 u8 reserved_at_40[0x40]; 6601 }; 6602 6603 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6604 u8 opcode[0x10]; 6605 u8 reserved_at_10[0x10]; 6606 6607 u8 reserved_at_20[0x10]; 6608 u8 op_mod[0x10]; 6609 6610 u8 reserved_at_40[0x60]; 6611 6612 u8 reserved_at_a0[0x8]; 6613 u8 table_index[0x18]; 6614 6615 u8 reserved_at_c0[0x140]; 6616 }; 6617 6618 struct mlx5_ifc_delete_fte_out_bits { 6619 u8 status[0x8]; 6620 u8 reserved_at_8[0x18]; 6621 6622 u8 syndrome[0x20]; 6623 6624 u8 reserved_at_40[0x40]; 6625 }; 6626 6627 struct mlx5_ifc_delete_fte_in_bits { 6628 u8 opcode[0x10]; 6629 u8 reserved_at_10[0x10]; 6630 6631 u8 reserved_at_20[0x10]; 6632 u8 op_mod[0x10]; 6633 6634 u8 other_vport[0x1]; 6635 u8 reserved_at_41[0xf]; 6636 u8 vport_number[0x10]; 6637 6638 u8 reserved_at_60[0x20]; 6639 6640 u8 table_type[0x8]; 6641 u8 reserved_at_88[0x18]; 6642 6643 u8 reserved_at_a0[0x8]; 6644 u8 table_id[0x18]; 6645 6646 u8 reserved_at_c0[0x40]; 6647 6648 u8 flow_index[0x20]; 6649 6650 u8 reserved_at_120[0xe0]; 6651 }; 6652 6653 struct mlx5_ifc_dealloc_xrcd_out_bits { 6654 u8 status[0x8]; 6655 u8 reserved_at_8[0x18]; 6656 6657 u8 syndrome[0x20]; 6658 6659 u8 reserved_at_40[0x40]; 6660 }; 6661 6662 struct mlx5_ifc_dealloc_xrcd_in_bits { 6663 u8 opcode[0x10]; 6664 u8 uid[0x10]; 6665 6666 u8 reserved_at_20[0x10]; 6667 u8 op_mod[0x10]; 6668 6669 u8 reserved_at_40[0x8]; 6670 u8 xrcd[0x18]; 6671 6672 u8 reserved_at_60[0x20]; 6673 }; 6674 6675 struct mlx5_ifc_dealloc_uar_out_bits { 6676 u8 status[0x8]; 6677 u8 reserved_at_8[0x18]; 6678 6679 u8 syndrome[0x20]; 6680 6681 u8 reserved_at_40[0x40]; 6682 }; 6683 6684 struct mlx5_ifc_dealloc_uar_in_bits { 6685 u8 opcode[0x10]; 6686 u8 reserved_at_10[0x10]; 6687 6688 u8 reserved_at_20[0x10]; 6689 u8 op_mod[0x10]; 6690 6691 u8 reserved_at_40[0x8]; 6692 u8 uar[0x18]; 6693 6694 u8 reserved_at_60[0x20]; 6695 }; 6696 6697 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6698 u8 status[0x8]; 6699 u8 reserved_at_8[0x18]; 6700 6701 u8 syndrome[0x20]; 6702 6703 u8 reserved_at_40[0x40]; 6704 }; 6705 6706 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6707 u8 opcode[0x10]; 6708 u8 uid[0x10]; 6709 6710 u8 reserved_at_20[0x10]; 6711 u8 op_mod[0x10]; 6712 6713 u8 reserved_at_40[0x8]; 6714 u8 transport_domain[0x18]; 6715 6716 u8 reserved_at_60[0x20]; 6717 }; 6718 6719 struct mlx5_ifc_dealloc_q_counter_out_bits { 6720 u8 status[0x8]; 6721 u8 reserved_at_8[0x18]; 6722 6723 u8 syndrome[0x20]; 6724 6725 u8 reserved_at_40[0x40]; 6726 }; 6727 6728 struct mlx5_ifc_dealloc_q_counter_in_bits { 6729 u8 opcode[0x10]; 6730 u8 reserved_at_10[0x10]; 6731 6732 u8 reserved_at_20[0x10]; 6733 u8 op_mod[0x10]; 6734 6735 u8 reserved_at_40[0x18]; 6736 u8 counter_set_id[0x8]; 6737 6738 u8 reserved_at_60[0x20]; 6739 }; 6740 6741 struct mlx5_ifc_dealloc_pd_out_bits { 6742 u8 status[0x8]; 6743 u8 reserved_at_8[0x18]; 6744 6745 u8 syndrome[0x20]; 6746 6747 u8 reserved_at_40[0x40]; 6748 }; 6749 6750 struct mlx5_ifc_dealloc_pd_in_bits { 6751 u8 opcode[0x10]; 6752 u8 uid[0x10]; 6753 6754 u8 reserved_at_20[0x10]; 6755 u8 op_mod[0x10]; 6756 6757 u8 reserved_at_40[0x8]; 6758 u8 pd[0x18]; 6759 6760 u8 reserved_at_60[0x20]; 6761 }; 6762 6763 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6764 u8 status[0x8]; 6765 u8 reserved_at_8[0x18]; 6766 6767 u8 syndrome[0x20]; 6768 6769 u8 reserved_at_40[0x40]; 6770 }; 6771 6772 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6773 u8 opcode[0x10]; 6774 u8 reserved_at_10[0x10]; 6775 6776 u8 reserved_at_20[0x10]; 6777 u8 op_mod[0x10]; 6778 6779 u8 flow_counter_id[0x20]; 6780 6781 u8 reserved_at_60[0x20]; 6782 }; 6783 6784 struct mlx5_ifc_create_xrq_out_bits { 6785 u8 status[0x8]; 6786 u8 reserved_at_8[0x18]; 6787 6788 u8 syndrome[0x20]; 6789 6790 u8 reserved_at_40[0x8]; 6791 u8 xrqn[0x18]; 6792 6793 u8 reserved_at_60[0x20]; 6794 }; 6795 6796 struct mlx5_ifc_create_xrq_in_bits { 6797 u8 opcode[0x10]; 6798 u8 uid[0x10]; 6799 6800 u8 reserved_at_20[0x10]; 6801 u8 op_mod[0x10]; 6802 6803 u8 reserved_at_40[0x40]; 6804 6805 struct mlx5_ifc_xrqc_bits xrq_context; 6806 }; 6807 6808 struct mlx5_ifc_create_xrc_srq_out_bits { 6809 u8 status[0x8]; 6810 u8 reserved_at_8[0x18]; 6811 6812 u8 syndrome[0x20]; 6813 6814 u8 reserved_at_40[0x8]; 6815 u8 xrc_srqn[0x18]; 6816 6817 u8 reserved_at_60[0x20]; 6818 }; 6819 6820 struct mlx5_ifc_create_xrc_srq_in_bits { 6821 u8 opcode[0x10]; 6822 u8 uid[0x10]; 6823 6824 u8 reserved_at_20[0x10]; 6825 u8 op_mod[0x10]; 6826 6827 u8 reserved_at_40[0x40]; 6828 6829 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6830 6831 u8 reserved_at_280[0x60]; 6832 6833 u8 xrc_srq_umem_valid[0x1]; 6834 u8 reserved_at_2e1[0x1f]; 6835 6836 u8 reserved_at_300[0x580]; 6837 6838 u8 pas[0][0x40]; 6839 }; 6840 6841 struct mlx5_ifc_create_tis_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_at_8[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_at_40[0x8]; 6848 u8 tisn[0x18]; 6849 6850 u8 reserved_at_60[0x20]; 6851 }; 6852 6853 struct mlx5_ifc_create_tis_in_bits { 6854 u8 opcode[0x10]; 6855 u8 uid[0x10]; 6856 6857 u8 reserved_at_20[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 reserved_at_40[0xc0]; 6861 6862 struct mlx5_ifc_tisc_bits ctx; 6863 }; 6864 6865 struct mlx5_ifc_create_tir_out_bits { 6866 u8 status[0x8]; 6867 u8 reserved_at_8[0x18]; 6868 6869 u8 syndrome[0x20]; 6870 6871 u8 reserved_at_40[0x8]; 6872 u8 tirn[0x18]; 6873 6874 u8 reserved_at_60[0x20]; 6875 }; 6876 6877 struct mlx5_ifc_create_tir_in_bits { 6878 u8 opcode[0x10]; 6879 u8 uid[0x10]; 6880 6881 u8 reserved_at_20[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 reserved_at_40[0xc0]; 6885 6886 struct mlx5_ifc_tirc_bits ctx; 6887 }; 6888 6889 struct mlx5_ifc_create_srq_out_bits { 6890 u8 status[0x8]; 6891 u8 reserved_at_8[0x18]; 6892 6893 u8 syndrome[0x20]; 6894 6895 u8 reserved_at_40[0x8]; 6896 u8 srqn[0x18]; 6897 6898 u8 reserved_at_60[0x20]; 6899 }; 6900 6901 struct mlx5_ifc_create_srq_in_bits { 6902 u8 opcode[0x10]; 6903 u8 uid[0x10]; 6904 6905 u8 reserved_at_20[0x10]; 6906 u8 op_mod[0x10]; 6907 6908 u8 reserved_at_40[0x40]; 6909 6910 struct mlx5_ifc_srqc_bits srq_context_entry; 6911 6912 u8 reserved_at_280[0x600]; 6913 6914 u8 pas[0][0x40]; 6915 }; 6916 6917 struct mlx5_ifc_create_sq_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_at_8[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_at_40[0x8]; 6924 u8 sqn[0x18]; 6925 6926 u8 reserved_at_60[0x20]; 6927 }; 6928 6929 struct mlx5_ifc_create_sq_in_bits { 6930 u8 opcode[0x10]; 6931 u8 uid[0x10]; 6932 6933 u8 reserved_at_20[0x10]; 6934 u8 op_mod[0x10]; 6935 6936 u8 reserved_at_40[0xc0]; 6937 6938 struct mlx5_ifc_sqc_bits ctx; 6939 }; 6940 6941 struct mlx5_ifc_create_scheduling_element_out_bits { 6942 u8 status[0x8]; 6943 u8 reserved_at_8[0x18]; 6944 6945 u8 syndrome[0x20]; 6946 6947 u8 reserved_at_40[0x40]; 6948 6949 u8 scheduling_element_id[0x20]; 6950 6951 u8 reserved_at_a0[0x160]; 6952 }; 6953 6954 struct mlx5_ifc_create_scheduling_element_in_bits { 6955 u8 opcode[0x10]; 6956 u8 reserved_at_10[0x10]; 6957 6958 u8 reserved_at_20[0x10]; 6959 u8 op_mod[0x10]; 6960 6961 u8 scheduling_hierarchy[0x8]; 6962 u8 reserved_at_48[0x18]; 6963 6964 u8 reserved_at_60[0xa0]; 6965 6966 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6967 6968 u8 reserved_at_300[0x100]; 6969 }; 6970 6971 struct mlx5_ifc_create_rqt_out_bits { 6972 u8 status[0x8]; 6973 u8 reserved_at_8[0x18]; 6974 6975 u8 syndrome[0x20]; 6976 6977 u8 reserved_at_40[0x8]; 6978 u8 rqtn[0x18]; 6979 6980 u8 reserved_at_60[0x20]; 6981 }; 6982 6983 struct mlx5_ifc_create_rqt_in_bits { 6984 u8 opcode[0x10]; 6985 u8 uid[0x10]; 6986 6987 u8 reserved_at_20[0x10]; 6988 u8 op_mod[0x10]; 6989 6990 u8 reserved_at_40[0xc0]; 6991 6992 struct mlx5_ifc_rqtc_bits rqt_context; 6993 }; 6994 6995 struct mlx5_ifc_create_rq_out_bits { 6996 u8 status[0x8]; 6997 u8 reserved_at_8[0x18]; 6998 6999 u8 syndrome[0x20]; 7000 7001 u8 reserved_at_40[0x8]; 7002 u8 rqn[0x18]; 7003 7004 u8 reserved_at_60[0x20]; 7005 }; 7006 7007 struct mlx5_ifc_create_rq_in_bits { 7008 u8 opcode[0x10]; 7009 u8 uid[0x10]; 7010 7011 u8 reserved_at_20[0x10]; 7012 u8 op_mod[0x10]; 7013 7014 u8 reserved_at_40[0xc0]; 7015 7016 struct mlx5_ifc_rqc_bits ctx; 7017 }; 7018 7019 struct mlx5_ifc_create_rmp_out_bits { 7020 u8 status[0x8]; 7021 u8 reserved_at_8[0x18]; 7022 7023 u8 syndrome[0x20]; 7024 7025 u8 reserved_at_40[0x8]; 7026 u8 rmpn[0x18]; 7027 7028 u8 reserved_at_60[0x20]; 7029 }; 7030 7031 struct mlx5_ifc_create_rmp_in_bits { 7032 u8 opcode[0x10]; 7033 u8 uid[0x10]; 7034 7035 u8 reserved_at_20[0x10]; 7036 u8 op_mod[0x10]; 7037 7038 u8 reserved_at_40[0xc0]; 7039 7040 struct mlx5_ifc_rmpc_bits ctx; 7041 }; 7042 7043 struct mlx5_ifc_create_qp_out_bits { 7044 u8 status[0x8]; 7045 u8 reserved_at_8[0x18]; 7046 7047 u8 syndrome[0x20]; 7048 7049 u8 reserved_at_40[0x8]; 7050 u8 qpn[0x18]; 7051 7052 u8 reserved_at_60[0x20]; 7053 }; 7054 7055 struct mlx5_ifc_create_qp_in_bits { 7056 u8 opcode[0x10]; 7057 u8 uid[0x10]; 7058 7059 u8 reserved_at_20[0x10]; 7060 u8 op_mod[0x10]; 7061 7062 u8 reserved_at_40[0x40]; 7063 7064 u8 opt_param_mask[0x20]; 7065 7066 u8 reserved_at_a0[0x20]; 7067 7068 struct mlx5_ifc_qpc_bits qpc; 7069 7070 u8 reserved_at_800[0x60]; 7071 7072 u8 wq_umem_valid[0x1]; 7073 u8 reserved_at_861[0x1f]; 7074 7075 u8 pas[0][0x40]; 7076 }; 7077 7078 struct mlx5_ifc_create_psv_out_bits { 7079 u8 status[0x8]; 7080 u8 reserved_at_8[0x18]; 7081 7082 u8 syndrome[0x20]; 7083 7084 u8 reserved_at_40[0x40]; 7085 7086 u8 reserved_at_80[0x8]; 7087 u8 psv0_index[0x18]; 7088 7089 u8 reserved_at_a0[0x8]; 7090 u8 psv1_index[0x18]; 7091 7092 u8 reserved_at_c0[0x8]; 7093 u8 psv2_index[0x18]; 7094 7095 u8 reserved_at_e0[0x8]; 7096 u8 psv3_index[0x18]; 7097 }; 7098 7099 struct mlx5_ifc_create_psv_in_bits { 7100 u8 opcode[0x10]; 7101 u8 reserved_at_10[0x10]; 7102 7103 u8 reserved_at_20[0x10]; 7104 u8 op_mod[0x10]; 7105 7106 u8 num_psv[0x4]; 7107 u8 reserved_at_44[0x4]; 7108 u8 pd[0x18]; 7109 7110 u8 reserved_at_60[0x20]; 7111 }; 7112 7113 struct mlx5_ifc_create_mkey_out_bits { 7114 u8 status[0x8]; 7115 u8 reserved_at_8[0x18]; 7116 7117 u8 syndrome[0x20]; 7118 7119 u8 reserved_at_40[0x8]; 7120 u8 mkey_index[0x18]; 7121 7122 u8 reserved_at_60[0x20]; 7123 }; 7124 7125 struct mlx5_ifc_create_mkey_in_bits { 7126 u8 opcode[0x10]; 7127 u8 reserved_at_10[0x10]; 7128 7129 u8 reserved_at_20[0x10]; 7130 u8 op_mod[0x10]; 7131 7132 u8 reserved_at_40[0x20]; 7133 7134 u8 pg_access[0x1]; 7135 u8 mkey_umem_valid[0x1]; 7136 u8 reserved_at_62[0x1e]; 7137 7138 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7139 7140 u8 reserved_at_280[0x80]; 7141 7142 u8 translations_octword_actual_size[0x20]; 7143 7144 u8 reserved_at_320[0x560]; 7145 7146 u8 klm_pas_mtt[0][0x20]; 7147 }; 7148 7149 struct mlx5_ifc_create_flow_table_out_bits { 7150 u8 status[0x8]; 7151 u8 reserved_at_8[0x18]; 7152 7153 u8 syndrome[0x20]; 7154 7155 u8 reserved_at_40[0x8]; 7156 u8 table_id[0x18]; 7157 7158 u8 reserved_at_60[0x20]; 7159 }; 7160 7161 struct mlx5_ifc_flow_table_context_bits { 7162 u8 reformat_en[0x1]; 7163 u8 decap_en[0x1]; 7164 u8 reserved_at_2[0x2]; 7165 u8 table_miss_action[0x4]; 7166 u8 level[0x8]; 7167 u8 reserved_at_10[0x8]; 7168 u8 log_size[0x8]; 7169 7170 u8 reserved_at_20[0x8]; 7171 u8 table_miss_id[0x18]; 7172 7173 u8 reserved_at_40[0x8]; 7174 u8 lag_master_next_table_id[0x18]; 7175 7176 u8 reserved_at_60[0xe0]; 7177 }; 7178 7179 struct mlx5_ifc_create_flow_table_in_bits { 7180 u8 opcode[0x10]; 7181 u8 reserved_at_10[0x10]; 7182 7183 u8 reserved_at_20[0x10]; 7184 u8 op_mod[0x10]; 7185 7186 u8 other_vport[0x1]; 7187 u8 reserved_at_41[0xf]; 7188 u8 vport_number[0x10]; 7189 7190 u8 reserved_at_60[0x20]; 7191 7192 u8 table_type[0x8]; 7193 u8 reserved_at_88[0x18]; 7194 7195 u8 reserved_at_a0[0x20]; 7196 7197 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7198 }; 7199 7200 struct mlx5_ifc_create_flow_group_out_bits { 7201 u8 status[0x8]; 7202 u8 reserved_at_8[0x18]; 7203 7204 u8 syndrome[0x20]; 7205 7206 u8 reserved_at_40[0x8]; 7207 u8 group_id[0x18]; 7208 7209 u8 reserved_at_60[0x20]; 7210 }; 7211 7212 enum { 7213 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7214 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7215 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7216 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7217 }; 7218 7219 struct mlx5_ifc_create_flow_group_in_bits { 7220 u8 opcode[0x10]; 7221 u8 reserved_at_10[0x10]; 7222 7223 u8 reserved_at_20[0x10]; 7224 u8 op_mod[0x10]; 7225 7226 u8 other_vport[0x1]; 7227 u8 reserved_at_41[0xf]; 7228 u8 vport_number[0x10]; 7229 7230 u8 reserved_at_60[0x20]; 7231 7232 u8 table_type[0x8]; 7233 u8 reserved_at_88[0x18]; 7234 7235 u8 reserved_at_a0[0x8]; 7236 u8 table_id[0x18]; 7237 7238 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7239 7240 u8 reserved_at_c1[0x1f]; 7241 7242 u8 start_flow_index[0x20]; 7243 7244 u8 reserved_at_100[0x20]; 7245 7246 u8 end_flow_index[0x20]; 7247 7248 u8 reserved_at_140[0xa0]; 7249 7250 u8 reserved_at_1e0[0x18]; 7251 u8 match_criteria_enable[0x8]; 7252 7253 struct mlx5_ifc_fte_match_param_bits match_criteria; 7254 7255 u8 reserved_at_1200[0xe00]; 7256 }; 7257 7258 struct mlx5_ifc_create_eq_out_bits { 7259 u8 status[0x8]; 7260 u8 reserved_at_8[0x18]; 7261 7262 u8 syndrome[0x20]; 7263 7264 u8 reserved_at_40[0x18]; 7265 u8 eq_number[0x8]; 7266 7267 u8 reserved_at_60[0x20]; 7268 }; 7269 7270 struct mlx5_ifc_create_eq_in_bits { 7271 u8 opcode[0x10]; 7272 u8 reserved_at_10[0x10]; 7273 7274 u8 reserved_at_20[0x10]; 7275 u8 op_mod[0x10]; 7276 7277 u8 reserved_at_40[0x40]; 7278 7279 struct mlx5_ifc_eqc_bits eq_context_entry; 7280 7281 u8 reserved_at_280[0x40]; 7282 7283 u8 event_bitmask[0x40]; 7284 7285 u8 reserved_at_300[0x580]; 7286 7287 u8 pas[0][0x40]; 7288 }; 7289 7290 struct mlx5_ifc_create_dct_out_bits { 7291 u8 status[0x8]; 7292 u8 reserved_at_8[0x18]; 7293 7294 u8 syndrome[0x20]; 7295 7296 u8 reserved_at_40[0x8]; 7297 u8 dctn[0x18]; 7298 7299 u8 reserved_at_60[0x20]; 7300 }; 7301 7302 struct mlx5_ifc_create_dct_in_bits { 7303 u8 opcode[0x10]; 7304 u8 uid[0x10]; 7305 7306 u8 reserved_at_20[0x10]; 7307 u8 op_mod[0x10]; 7308 7309 u8 reserved_at_40[0x40]; 7310 7311 struct mlx5_ifc_dctc_bits dct_context_entry; 7312 7313 u8 reserved_at_280[0x180]; 7314 }; 7315 7316 struct mlx5_ifc_create_cq_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x8]; 7323 u8 cqn[0x18]; 7324 7325 u8 reserved_at_60[0x20]; 7326 }; 7327 7328 struct mlx5_ifc_create_cq_in_bits { 7329 u8 opcode[0x10]; 7330 u8 uid[0x10]; 7331 7332 u8 reserved_at_20[0x10]; 7333 u8 op_mod[0x10]; 7334 7335 u8 reserved_at_40[0x40]; 7336 7337 struct mlx5_ifc_cqc_bits cq_context; 7338 7339 u8 reserved_at_280[0x60]; 7340 7341 u8 cq_umem_valid[0x1]; 7342 u8 reserved_at_2e1[0x59f]; 7343 7344 u8 pas[0][0x40]; 7345 }; 7346 7347 struct mlx5_ifc_config_int_moderation_out_bits { 7348 u8 status[0x8]; 7349 u8 reserved_at_8[0x18]; 7350 7351 u8 syndrome[0x20]; 7352 7353 u8 reserved_at_40[0x4]; 7354 u8 min_delay[0xc]; 7355 u8 int_vector[0x10]; 7356 7357 u8 reserved_at_60[0x20]; 7358 }; 7359 7360 enum { 7361 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7362 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7363 }; 7364 7365 struct mlx5_ifc_config_int_moderation_in_bits { 7366 u8 opcode[0x10]; 7367 u8 reserved_at_10[0x10]; 7368 7369 u8 reserved_at_20[0x10]; 7370 u8 op_mod[0x10]; 7371 7372 u8 reserved_at_40[0x4]; 7373 u8 min_delay[0xc]; 7374 u8 int_vector[0x10]; 7375 7376 u8 reserved_at_60[0x20]; 7377 }; 7378 7379 struct mlx5_ifc_attach_to_mcg_out_bits { 7380 u8 status[0x8]; 7381 u8 reserved_at_8[0x18]; 7382 7383 u8 syndrome[0x20]; 7384 7385 u8 reserved_at_40[0x40]; 7386 }; 7387 7388 struct mlx5_ifc_attach_to_mcg_in_bits { 7389 u8 opcode[0x10]; 7390 u8 uid[0x10]; 7391 7392 u8 reserved_at_20[0x10]; 7393 u8 op_mod[0x10]; 7394 7395 u8 reserved_at_40[0x8]; 7396 u8 qpn[0x18]; 7397 7398 u8 reserved_at_60[0x20]; 7399 7400 u8 multicast_gid[16][0x8]; 7401 }; 7402 7403 struct mlx5_ifc_arm_xrq_out_bits { 7404 u8 status[0x8]; 7405 u8 reserved_at_8[0x18]; 7406 7407 u8 syndrome[0x20]; 7408 7409 u8 reserved_at_40[0x40]; 7410 }; 7411 7412 struct mlx5_ifc_arm_xrq_in_bits { 7413 u8 opcode[0x10]; 7414 u8 reserved_at_10[0x10]; 7415 7416 u8 reserved_at_20[0x10]; 7417 u8 op_mod[0x10]; 7418 7419 u8 reserved_at_40[0x8]; 7420 u8 xrqn[0x18]; 7421 7422 u8 reserved_at_60[0x10]; 7423 u8 lwm[0x10]; 7424 }; 7425 7426 struct mlx5_ifc_arm_xrc_srq_out_bits { 7427 u8 status[0x8]; 7428 u8 reserved_at_8[0x18]; 7429 7430 u8 syndrome[0x20]; 7431 7432 u8 reserved_at_40[0x40]; 7433 }; 7434 7435 enum { 7436 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7437 }; 7438 7439 struct mlx5_ifc_arm_xrc_srq_in_bits { 7440 u8 opcode[0x10]; 7441 u8 uid[0x10]; 7442 7443 u8 reserved_at_20[0x10]; 7444 u8 op_mod[0x10]; 7445 7446 u8 reserved_at_40[0x8]; 7447 u8 xrc_srqn[0x18]; 7448 7449 u8 reserved_at_60[0x10]; 7450 u8 lwm[0x10]; 7451 }; 7452 7453 struct mlx5_ifc_arm_rq_out_bits { 7454 u8 status[0x8]; 7455 u8 reserved_at_8[0x18]; 7456 7457 u8 syndrome[0x20]; 7458 7459 u8 reserved_at_40[0x40]; 7460 }; 7461 7462 enum { 7463 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7464 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7465 }; 7466 7467 struct mlx5_ifc_arm_rq_in_bits { 7468 u8 opcode[0x10]; 7469 u8 uid[0x10]; 7470 7471 u8 reserved_at_20[0x10]; 7472 u8 op_mod[0x10]; 7473 7474 u8 reserved_at_40[0x8]; 7475 u8 srq_number[0x18]; 7476 7477 u8 reserved_at_60[0x10]; 7478 u8 lwm[0x10]; 7479 }; 7480 7481 struct mlx5_ifc_arm_dct_out_bits { 7482 u8 status[0x8]; 7483 u8 reserved_at_8[0x18]; 7484 7485 u8 syndrome[0x20]; 7486 7487 u8 reserved_at_40[0x40]; 7488 }; 7489 7490 struct mlx5_ifc_arm_dct_in_bits { 7491 u8 opcode[0x10]; 7492 u8 reserved_at_10[0x10]; 7493 7494 u8 reserved_at_20[0x10]; 7495 u8 op_mod[0x10]; 7496 7497 u8 reserved_at_40[0x8]; 7498 u8 dct_number[0x18]; 7499 7500 u8 reserved_at_60[0x20]; 7501 }; 7502 7503 struct mlx5_ifc_alloc_xrcd_out_bits { 7504 u8 status[0x8]; 7505 u8 reserved_at_8[0x18]; 7506 7507 u8 syndrome[0x20]; 7508 7509 u8 reserved_at_40[0x8]; 7510 u8 xrcd[0x18]; 7511 7512 u8 reserved_at_60[0x20]; 7513 }; 7514 7515 struct mlx5_ifc_alloc_xrcd_in_bits { 7516 u8 opcode[0x10]; 7517 u8 uid[0x10]; 7518 7519 u8 reserved_at_20[0x10]; 7520 u8 op_mod[0x10]; 7521 7522 u8 reserved_at_40[0x40]; 7523 }; 7524 7525 struct mlx5_ifc_alloc_uar_out_bits { 7526 u8 status[0x8]; 7527 u8 reserved_at_8[0x18]; 7528 7529 u8 syndrome[0x20]; 7530 7531 u8 reserved_at_40[0x8]; 7532 u8 uar[0x18]; 7533 7534 u8 reserved_at_60[0x20]; 7535 }; 7536 7537 struct mlx5_ifc_alloc_uar_in_bits { 7538 u8 opcode[0x10]; 7539 u8 reserved_at_10[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 reserved_at_40[0x40]; 7545 }; 7546 7547 struct mlx5_ifc_alloc_transport_domain_out_bits { 7548 u8 status[0x8]; 7549 u8 reserved_at_8[0x18]; 7550 7551 u8 syndrome[0x20]; 7552 7553 u8 reserved_at_40[0x8]; 7554 u8 transport_domain[0x18]; 7555 7556 u8 reserved_at_60[0x20]; 7557 }; 7558 7559 struct mlx5_ifc_alloc_transport_domain_in_bits { 7560 u8 opcode[0x10]; 7561 u8 uid[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 reserved_at_40[0x40]; 7567 }; 7568 7569 struct mlx5_ifc_alloc_q_counter_out_bits { 7570 u8 status[0x8]; 7571 u8 reserved_at_8[0x18]; 7572 7573 u8 syndrome[0x20]; 7574 7575 u8 reserved_at_40[0x18]; 7576 u8 counter_set_id[0x8]; 7577 7578 u8 reserved_at_60[0x20]; 7579 }; 7580 7581 struct mlx5_ifc_alloc_q_counter_in_bits { 7582 u8 opcode[0x10]; 7583 u8 uid[0x10]; 7584 7585 u8 reserved_at_20[0x10]; 7586 u8 op_mod[0x10]; 7587 7588 u8 reserved_at_40[0x40]; 7589 }; 7590 7591 struct mlx5_ifc_alloc_pd_out_bits { 7592 u8 status[0x8]; 7593 u8 reserved_at_8[0x18]; 7594 7595 u8 syndrome[0x20]; 7596 7597 u8 reserved_at_40[0x8]; 7598 u8 pd[0x18]; 7599 7600 u8 reserved_at_60[0x20]; 7601 }; 7602 7603 struct mlx5_ifc_alloc_pd_in_bits { 7604 u8 opcode[0x10]; 7605 u8 uid[0x10]; 7606 7607 u8 reserved_at_20[0x10]; 7608 u8 op_mod[0x10]; 7609 7610 u8 reserved_at_40[0x40]; 7611 }; 7612 7613 struct mlx5_ifc_alloc_flow_counter_out_bits { 7614 u8 status[0x8]; 7615 u8 reserved_at_8[0x18]; 7616 7617 u8 syndrome[0x20]; 7618 7619 u8 flow_counter_id[0x20]; 7620 7621 u8 reserved_at_60[0x20]; 7622 }; 7623 7624 struct mlx5_ifc_alloc_flow_counter_in_bits { 7625 u8 opcode[0x10]; 7626 u8 reserved_at_10[0x10]; 7627 7628 u8 reserved_at_20[0x10]; 7629 u8 op_mod[0x10]; 7630 7631 u8 reserved_at_40[0x40]; 7632 }; 7633 7634 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7635 u8 status[0x8]; 7636 u8 reserved_at_8[0x18]; 7637 7638 u8 syndrome[0x20]; 7639 7640 u8 reserved_at_40[0x40]; 7641 }; 7642 7643 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7644 u8 opcode[0x10]; 7645 u8 reserved_at_10[0x10]; 7646 7647 u8 reserved_at_20[0x10]; 7648 u8 op_mod[0x10]; 7649 7650 u8 reserved_at_40[0x20]; 7651 7652 u8 reserved_at_60[0x10]; 7653 u8 vxlan_udp_port[0x10]; 7654 }; 7655 7656 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7657 u8 status[0x8]; 7658 u8 reserved_at_8[0x18]; 7659 7660 u8 syndrome[0x20]; 7661 7662 u8 reserved_at_40[0x40]; 7663 }; 7664 7665 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7666 u8 opcode[0x10]; 7667 u8 reserved_at_10[0x10]; 7668 7669 u8 reserved_at_20[0x10]; 7670 u8 op_mod[0x10]; 7671 7672 u8 reserved_at_40[0x10]; 7673 u8 rate_limit_index[0x10]; 7674 7675 u8 reserved_at_60[0x20]; 7676 7677 u8 rate_limit[0x20]; 7678 7679 u8 burst_upper_bound[0x20]; 7680 7681 u8 reserved_at_c0[0x10]; 7682 u8 typical_packet_size[0x10]; 7683 7684 u8 reserved_at_e0[0x120]; 7685 }; 7686 7687 struct mlx5_ifc_access_register_out_bits { 7688 u8 status[0x8]; 7689 u8 reserved_at_8[0x18]; 7690 7691 u8 syndrome[0x20]; 7692 7693 u8 reserved_at_40[0x40]; 7694 7695 u8 register_data[0][0x20]; 7696 }; 7697 7698 enum { 7699 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7700 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7701 }; 7702 7703 struct mlx5_ifc_access_register_in_bits { 7704 u8 opcode[0x10]; 7705 u8 reserved_at_10[0x10]; 7706 7707 u8 reserved_at_20[0x10]; 7708 u8 op_mod[0x10]; 7709 7710 u8 reserved_at_40[0x10]; 7711 u8 register_id[0x10]; 7712 7713 u8 argument[0x20]; 7714 7715 u8 register_data[0][0x20]; 7716 }; 7717 7718 struct mlx5_ifc_sltp_reg_bits { 7719 u8 status[0x4]; 7720 u8 version[0x4]; 7721 u8 local_port[0x8]; 7722 u8 pnat[0x2]; 7723 u8 reserved_at_12[0x2]; 7724 u8 lane[0x4]; 7725 u8 reserved_at_18[0x8]; 7726 7727 u8 reserved_at_20[0x20]; 7728 7729 u8 reserved_at_40[0x7]; 7730 u8 polarity[0x1]; 7731 u8 ob_tap0[0x8]; 7732 u8 ob_tap1[0x8]; 7733 u8 ob_tap2[0x8]; 7734 7735 u8 reserved_at_60[0xc]; 7736 u8 ob_preemp_mode[0x4]; 7737 u8 ob_reg[0x8]; 7738 u8 ob_bias[0x8]; 7739 7740 u8 reserved_at_80[0x20]; 7741 }; 7742 7743 struct mlx5_ifc_slrg_reg_bits { 7744 u8 status[0x4]; 7745 u8 version[0x4]; 7746 u8 local_port[0x8]; 7747 u8 pnat[0x2]; 7748 u8 reserved_at_12[0x2]; 7749 u8 lane[0x4]; 7750 u8 reserved_at_18[0x8]; 7751 7752 u8 time_to_link_up[0x10]; 7753 u8 reserved_at_30[0xc]; 7754 u8 grade_lane_speed[0x4]; 7755 7756 u8 grade_version[0x8]; 7757 u8 grade[0x18]; 7758 7759 u8 reserved_at_60[0x4]; 7760 u8 height_grade_type[0x4]; 7761 u8 height_grade[0x18]; 7762 7763 u8 height_dz[0x10]; 7764 u8 height_dv[0x10]; 7765 7766 u8 reserved_at_a0[0x10]; 7767 u8 height_sigma[0x10]; 7768 7769 u8 reserved_at_c0[0x20]; 7770 7771 u8 reserved_at_e0[0x4]; 7772 u8 phase_grade_type[0x4]; 7773 u8 phase_grade[0x18]; 7774 7775 u8 reserved_at_100[0x8]; 7776 u8 phase_eo_pos[0x8]; 7777 u8 reserved_at_110[0x8]; 7778 u8 phase_eo_neg[0x8]; 7779 7780 u8 ffe_set_tested[0x10]; 7781 u8 test_errors_per_lane[0x10]; 7782 }; 7783 7784 struct mlx5_ifc_pvlc_reg_bits { 7785 u8 reserved_at_0[0x8]; 7786 u8 local_port[0x8]; 7787 u8 reserved_at_10[0x10]; 7788 7789 u8 reserved_at_20[0x1c]; 7790 u8 vl_hw_cap[0x4]; 7791 7792 u8 reserved_at_40[0x1c]; 7793 u8 vl_admin[0x4]; 7794 7795 u8 reserved_at_60[0x1c]; 7796 u8 vl_operational[0x4]; 7797 }; 7798 7799 struct mlx5_ifc_pude_reg_bits { 7800 u8 swid[0x8]; 7801 u8 local_port[0x8]; 7802 u8 reserved_at_10[0x4]; 7803 u8 admin_status[0x4]; 7804 u8 reserved_at_18[0x4]; 7805 u8 oper_status[0x4]; 7806 7807 u8 reserved_at_20[0x60]; 7808 }; 7809 7810 struct mlx5_ifc_ptys_reg_bits { 7811 u8 reserved_at_0[0x1]; 7812 u8 an_disable_admin[0x1]; 7813 u8 an_disable_cap[0x1]; 7814 u8 reserved_at_3[0x5]; 7815 u8 local_port[0x8]; 7816 u8 reserved_at_10[0xd]; 7817 u8 proto_mask[0x3]; 7818 7819 u8 an_status[0x4]; 7820 u8 reserved_at_24[0x3c]; 7821 7822 u8 eth_proto_capability[0x20]; 7823 7824 u8 ib_link_width_capability[0x10]; 7825 u8 ib_proto_capability[0x10]; 7826 7827 u8 reserved_at_a0[0x20]; 7828 7829 u8 eth_proto_admin[0x20]; 7830 7831 u8 ib_link_width_admin[0x10]; 7832 u8 ib_proto_admin[0x10]; 7833 7834 u8 reserved_at_100[0x20]; 7835 7836 u8 eth_proto_oper[0x20]; 7837 7838 u8 ib_link_width_oper[0x10]; 7839 u8 ib_proto_oper[0x10]; 7840 7841 u8 reserved_at_160[0x1c]; 7842 u8 connector_type[0x4]; 7843 7844 u8 eth_proto_lp_advertise[0x20]; 7845 7846 u8 reserved_at_1a0[0x60]; 7847 }; 7848 7849 struct mlx5_ifc_mlcr_reg_bits { 7850 u8 reserved_at_0[0x8]; 7851 u8 local_port[0x8]; 7852 u8 reserved_at_10[0x20]; 7853 7854 u8 beacon_duration[0x10]; 7855 u8 reserved_at_40[0x10]; 7856 7857 u8 beacon_remain[0x10]; 7858 }; 7859 7860 struct mlx5_ifc_ptas_reg_bits { 7861 u8 reserved_at_0[0x20]; 7862 7863 u8 algorithm_options[0x10]; 7864 u8 reserved_at_30[0x4]; 7865 u8 repetitions_mode[0x4]; 7866 u8 num_of_repetitions[0x8]; 7867 7868 u8 grade_version[0x8]; 7869 u8 height_grade_type[0x4]; 7870 u8 phase_grade_type[0x4]; 7871 u8 height_grade_weight[0x8]; 7872 u8 phase_grade_weight[0x8]; 7873 7874 u8 gisim_measure_bits[0x10]; 7875 u8 adaptive_tap_measure_bits[0x10]; 7876 7877 u8 ber_bath_high_error_threshold[0x10]; 7878 u8 ber_bath_mid_error_threshold[0x10]; 7879 7880 u8 ber_bath_low_error_threshold[0x10]; 7881 u8 one_ratio_high_threshold[0x10]; 7882 7883 u8 one_ratio_high_mid_threshold[0x10]; 7884 u8 one_ratio_low_mid_threshold[0x10]; 7885 7886 u8 one_ratio_low_threshold[0x10]; 7887 u8 ndeo_error_threshold[0x10]; 7888 7889 u8 mixer_offset_step_size[0x10]; 7890 u8 reserved_at_110[0x8]; 7891 u8 mix90_phase_for_voltage_bath[0x8]; 7892 7893 u8 mixer_offset_start[0x10]; 7894 u8 mixer_offset_end[0x10]; 7895 7896 u8 reserved_at_140[0x15]; 7897 u8 ber_test_time[0xb]; 7898 }; 7899 7900 struct mlx5_ifc_pspa_reg_bits { 7901 u8 swid[0x8]; 7902 u8 local_port[0x8]; 7903 u8 sub_port[0x8]; 7904 u8 reserved_at_18[0x8]; 7905 7906 u8 reserved_at_20[0x20]; 7907 }; 7908 7909 struct mlx5_ifc_pqdr_reg_bits { 7910 u8 reserved_at_0[0x8]; 7911 u8 local_port[0x8]; 7912 u8 reserved_at_10[0x5]; 7913 u8 prio[0x3]; 7914 u8 reserved_at_18[0x6]; 7915 u8 mode[0x2]; 7916 7917 u8 reserved_at_20[0x20]; 7918 7919 u8 reserved_at_40[0x10]; 7920 u8 min_threshold[0x10]; 7921 7922 u8 reserved_at_60[0x10]; 7923 u8 max_threshold[0x10]; 7924 7925 u8 reserved_at_80[0x10]; 7926 u8 mark_probability_denominator[0x10]; 7927 7928 u8 reserved_at_a0[0x60]; 7929 }; 7930 7931 struct mlx5_ifc_ppsc_reg_bits { 7932 u8 reserved_at_0[0x8]; 7933 u8 local_port[0x8]; 7934 u8 reserved_at_10[0x10]; 7935 7936 u8 reserved_at_20[0x60]; 7937 7938 u8 reserved_at_80[0x1c]; 7939 u8 wrps_admin[0x4]; 7940 7941 u8 reserved_at_a0[0x1c]; 7942 u8 wrps_status[0x4]; 7943 7944 u8 reserved_at_c0[0x8]; 7945 u8 up_threshold[0x8]; 7946 u8 reserved_at_d0[0x8]; 7947 u8 down_threshold[0x8]; 7948 7949 u8 reserved_at_e0[0x20]; 7950 7951 u8 reserved_at_100[0x1c]; 7952 u8 srps_admin[0x4]; 7953 7954 u8 reserved_at_120[0x1c]; 7955 u8 srps_status[0x4]; 7956 7957 u8 reserved_at_140[0x40]; 7958 }; 7959 7960 struct mlx5_ifc_pplr_reg_bits { 7961 u8 reserved_at_0[0x8]; 7962 u8 local_port[0x8]; 7963 u8 reserved_at_10[0x10]; 7964 7965 u8 reserved_at_20[0x8]; 7966 u8 lb_cap[0x8]; 7967 u8 reserved_at_30[0x8]; 7968 u8 lb_en[0x8]; 7969 }; 7970 7971 struct mlx5_ifc_pplm_reg_bits { 7972 u8 reserved_at_0[0x8]; 7973 u8 local_port[0x8]; 7974 u8 reserved_at_10[0x10]; 7975 7976 u8 reserved_at_20[0x20]; 7977 7978 u8 port_profile_mode[0x8]; 7979 u8 static_port_profile[0x8]; 7980 u8 active_port_profile[0x8]; 7981 u8 reserved_at_58[0x8]; 7982 7983 u8 retransmission_active[0x8]; 7984 u8 fec_mode_active[0x18]; 7985 7986 u8 rs_fec_correction_bypass_cap[0x4]; 7987 u8 reserved_at_84[0x8]; 7988 u8 fec_override_cap_56g[0x4]; 7989 u8 fec_override_cap_100g[0x4]; 7990 u8 fec_override_cap_50g[0x4]; 7991 u8 fec_override_cap_25g[0x4]; 7992 u8 fec_override_cap_10g_40g[0x4]; 7993 7994 u8 rs_fec_correction_bypass_admin[0x4]; 7995 u8 reserved_at_a4[0x8]; 7996 u8 fec_override_admin_56g[0x4]; 7997 u8 fec_override_admin_100g[0x4]; 7998 u8 fec_override_admin_50g[0x4]; 7999 u8 fec_override_admin_25g[0x4]; 8000 u8 fec_override_admin_10g_40g[0x4]; 8001 }; 8002 8003 struct mlx5_ifc_ppcnt_reg_bits { 8004 u8 swid[0x8]; 8005 u8 local_port[0x8]; 8006 u8 pnat[0x2]; 8007 u8 reserved_at_12[0x8]; 8008 u8 grp[0x6]; 8009 8010 u8 clr[0x1]; 8011 u8 reserved_at_21[0x1c]; 8012 u8 prio_tc[0x3]; 8013 8014 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8015 }; 8016 8017 struct mlx5_ifc_mpcnt_reg_bits { 8018 u8 reserved_at_0[0x8]; 8019 u8 pcie_index[0x8]; 8020 u8 reserved_at_10[0xa]; 8021 u8 grp[0x6]; 8022 8023 u8 clr[0x1]; 8024 u8 reserved_at_21[0x1f]; 8025 8026 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8027 }; 8028 8029 struct mlx5_ifc_ppad_reg_bits { 8030 u8 reserved_at_0[0x3]; 8031 u8 single_mac[0x1]; 8032 u8 reserved_at_4[0x4]; 8033 u8 local_port[0x8]; 8034 u8 mac_47_32[0x10]; 8035 8036 u8 mac_31_0[0x20]; 8037 8038 u8 reserved_at_40[0x40]; 8039 }; 8040 8041 struct mlx5_ifc_pmtu_reg_bits { 8042 u8 reserved_at_0[0x8]; 8043 u8 local_port[0x8]; 8044 u8 reserved_at_10[0x10]; 8045 8046 u8 max_mtu[0x10]; 8047 u8 reserved_at_30[0x10]; 8048 8049 u8 admin_mtu[0x10]; 8050 u8 reserved_at_50[0x10]; 8051 8052 u8 oper_mtu[0x10]; 8053 u8 reserved_at_70[0x10]; 8054 }; 8055 8056 struct mlx5_ifc_pmpr_reg_bits { 8057 u8 reserved_at_0[0x8]; 8058 u8 module[0x8]; 8059 u8 reserved_at_10[0x10]; 8060 8061 u8 reserved_at_20[0x18]; 8062 u8 attenuation_5g[0x8]; 8063 8064 u8 reserved_at_40[0x18]; 8065 u8 attenuation_7g[0x8]; 8066 8067 u8 reserved_at_60[0x18]; 8068 u8 attenuation_12g[0x8]; 8069 }; 8070 8071 struct mlx5_ifc_pmpe_reg_bits { 8072 u8 reserved_at_0[0x8]; 8073 u8 module[0x8]; 8074 u8 reserved_at_10[0xc]; 8075 u8 module_status[0x4]; 8076 8077 u8 reserved_at_20[0x60]; 8078 }; 8079 8080 struct mlx5_ifc_pmpc_reg_bits { 8081 u8 module_state_updated[32][0x8]; 8082 }; 8083 8084 struct mlx5_ifc_pmlpn_reg_bits { 8085 u8 reserved_at_0[0x4]; 8086 u8 mlpn_status[0x4]; 8087 u8 local_port[0x8]; 8088 u8 reserved_at_10[0x10]; 8089 8090 u8 e[0x1]; 8091 u8 reserved_at_21[0x1f]; 8092 }; 8093 8094 struct mlx5_ifc_pmlp_reg_bits { 8095 u8 rxtx[0x1]; 8096 u8 reserved_at_1[0x7]; 8097 u8 local_port[0x8]; 8098 u8 reserved_at_10[0x8]; 8099 u8 width[0x8]; 8100 8101 u8 lane0_module_mapping[0x20]; 8102 8103 u8 lane1_module_mapping[0x20]; 8104 8105 u8 lane2_module_mapping[0x20]; 8106 8107 u8 lane3_module_mapping[0x20]; 8108 8109 u8 reserved_at_a0[0x160]; 8110 }; 8111 8112 struct mlx5_ifc_pmaos_reg_bits { 8113 u8 reserved_at_0[0x8]; 8114 u8 module[0x8]; 8115 u8 reserved_at_10[0x4]; 8116 u8 admin_status[0x4]; 8117 u8 reserved_at_18[0x4]; 8118 u8 oper_status[0x4]; 8119 8120 u8 ase[0x1]; 8121 u8 ee[0x1]; 8122 u8 reserved_at_22[0x1c]; 8123 u8 e[0x2]; 8124 8125 u8 reserved_at_40[0x40]; 8126 }; 8127 8128 struct mlx5_ifc_plpc_reg_bits { 8129 u8 reserved_at_0[0x4]; 8130 u8 profile_id[0xc]; 8131 u8 reserved_at_10[0x4]; 8132 u8 proto_mask[0x4]; 8133 u8 reserved_at_18[0x8]; 8134 8135 u8 reserved_at_20[0x10]; 8136 u8 lane_speed[0x10]; 8137 8138 u8 reserved_at_40[0x17]; 8139 u8 lpbf[0x1]; 8140 u8 fec_mode_policy[0x8]; 8141 8142 u8 retransmission_capability[0x8]; 8143 u8 fec_mode_capability[0x18]; 8144 8145 u8 retransmission_support_admin[0x8]; 8146 u8 fec_mode_support_admin[0x18]; 8147 8148 u8 retransmission_request_admin[0x8]; 8149 u8 fec_mode_request_admin[0x18]; 8150 8151 u8 reserved_at_c0[0x80]; 8152 }; 8153 8154 struct mlx5_ifc_plib_reg_bits { 8155 u8 reserved_at_0[0x8]; 8156 u8 local_port[0x8]; 8157 u8 reserved_at_10[0x8]; 8158 u8 ib_port[0x8]; 8159 8160 u8 reserved_at_20[0x60]; 8161 }; 8162 8163 struct mlx5_ifc_plbf_reg_bits { 8164 u8 reserved_at_0[0x8]; 8165 u8 local_port[0x8]; 8166 u8 reserved_at_10[0xd]; 8167 u8 lbf_mode[0x3]; 8168 8169 u8 reserved_at_20[0x20]; 8170 }; 8171 8172 struct mlx5_ifc_pipg_reg_bits { 8173 u8 reserved_at_0[0x8]; 8174 u8 local_port[0x8]; 8175 u8 reserved_at_10[0x10]; 8176 8177 u8 dic[0x1]; 8178 u8 reserved_at_21[0x19]; 8179 u8 ipg[0x4]; 8180 u8 reserved_at_3e[0x2]; 8181 }; 8182 8183 struct mlx5_ifc_pifr_reg_bits { 8184 u8 reserved_at_0[0x8]; 8185 u8 local_port[0x8]; 8186 u8 reserved_at_10[0x10]; 8187 8188 u8 reserved_at_20[0xe0]; 8189 8190 u8 port_filter[8][0x20]; 8191 8192 u8 port_filter_update_en[8][0x20]; 8193 }; 8194 8195 struct mlx5_ifc_pfcc_reg_bits { 8196 u8 reserved_at_0[0x8]; 8197 u8 local_port[0x8]; 8198 u8 reserved_at_10[0xb]; 8199 u8 ppan_mask_n[0x1]; 8200 u8 minor_stall_mask[0x1]; 8201 u8 critical_stall_mask[0x1]; 8202 u8 reserved_at_1e[0x2]; 8203 8204 u8 ppan[0x4]; 8205 u8 reserved_at_24[0x4]; 8206 u8 prio_mask_tx[0x8]; 8207 u8 reserved_at_30[0x8]; 8208 u8 prio_mask_rx[0x8]; 8209 8210 u8 pptx[0x1]; 8211 u8 aptx[0x1]; 8212 u8 pptx_mask_n[0x1]; 8213 u8 reserved_at_43[0x5]; 8214 u8 pfctx[0x8]; 8215 u8 reserved_at_50[0x10]; 8216 8217 u8 pprx[0x1]; 8218 u8 aprx[0x1]; 8219 u8 pprx_mask_n[0x1]; 8220 u8 reserved_at_63[0x5]; 8221 u8 pfcrx[0x8]; 8222 u8 reserved_at_70[0x10]; 8223 8224 u8 device_stall_minor_watermark[0x10]; 8225 u8 device_stall_critical_watermark[0x10]; 8226 8227 u8 reserved_at_a0[0x60]; 8228 }; 8229 8230 struct mlx5_ifc_pelc_reg_bits { 8231 u8 op[0x4]; 8232 u8 reserved_at_4[0x4]; 8233 u8 local_port[0x8]; 8234 u8 reserved_at_10[0x10]; 8235 8236 u8 op_admin[0x8]; 8237 u8 op_capability[0x8]; 8238 u8 op_request[0x8]; 8239 u8 op_active[0x8]; 8240 8241 u8 admin[0x40]; 8242 8243 u8 capability[0x40]; 8244 8245 u8 request[0x40]; 8246 8247 u8 active[0x40]; 8248 8249 u8 reserved_at_140[0x80]; 8250 }; 8251 8252 struct mlx5_ifc_peir_reg_bits { 8253 u8 reserved_at_0[0x8]; 8254 u8 local_port[0x8]; 8255 u8 reserved_at_10[0x10]; 8256 8257 u8 reserved_at_20[0xc]; 8258 u8 error_count[0x4]; 8259 u8 reserved_at_30[0x10]; 8260 8261 u8 reserved_at_40[0xc]; 8262 u8 lane[0x4]; 8263 u8 reserved_at_50[0x8]; 8264 u8 error_type[0x8]; 8265 }; 8266 8267 struct mlx5_ifc_mpegc_reg_bits { 8268 u8 reserved_at_0[0x30]; 8269 u8 field_select[0x10]; 8270 8271 u8 tx_overflow_sense[0x1]; 8272 u8 mark_cqe[0x1]; 8273 u8 mark_cnp[0x1]; 8274 u8 reserved_at_43[0x1b]; 8275 u8 tx_lossy_overflow_oper[0x2]; 8276 8277 u8 reserved_at_60[0x100]; 8278 }; 8279 8280 struct mlx5_ifc_pcam_enhanced_features_bits { 8281 u8 reserved_at_0[0x6d]; 8282 u8 rx_icrc_encapsulated_counter[0x1]; 8283 u8 reserved_at_6e[0x8]; 8284 u8 pfcc_mask[0x1]; 8285 u8 reserved_at_77[0x3]; 8286 u8 per_lane_error_counters[0x1]; 8287 u8 rx_buffer_fullness_counters[0x1]; 8288 u8 ptys_connector_type[0x1]; 8289 u8 reserved_at_7d[0x1]; 8290 u8 ppcnt_discard_group[0x1]; 8291 u8 ppcnt_statistical_group[0x1]; 8292 }; 8293 8294 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8295 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8296 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8297 8298 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8299 u8 pplm[0x1]; 8300 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8301 8302 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8303 u8 pbmc[0x1]; 8304 u8 pptb[0x1]; 8305 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8306 u8 ppcnt[0x1]; 8307 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8308 }; 8309 8310 struct mlx5_ifc_pcam_reg_bits { 8311 u8 reserved_at_0[0x8]; 8312 u8 feature_group[0x8]; 8313 u8 reserved_at_10[0x8]; 8314 u8 access_reg_group[0x8]; 8315 8316 u8 reserved_at_20[0x20]; 8317 8318 union { 8319 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8320 u8 reserved_at_0[0x80]; 8321 } port_access_reg_cap_mask; 8322 8323 u8 reserved_at_c0[0x80]; 8324 8325 union { 8326 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8327 u8 reserved_at_0[0x80]; 8328 } feature_cap_mask; 8329 8330 u8 reserved_at_1c0[0xc0]; 8331 }; 8332 8333 struct mlx5_ifc_mcam_enhanced_features_bits { 8334 u8 reserved_at_0[0x74]; 8335 u8 mark_tx_action_cnp[0x1]; 8336 u8 mark_tx_action_cqe[0x1]; 8337 u8 dynamic_tx_overflow[0x1]; 8338 u8 reserved_at_77[0x4]; 8339 u8 pcie_outbound_stalled[0x1]; 8340 u8 tx_overflow_buffer_pkt[0x1]; 8341 u8 mtpps_enh_out_per_adj[0x1]; 8342 u8 mtpps_fs[0x1]; 8343 u8 pcie_performance_group[0x1]; 8344 }; 8345 8346 struct mlx5_ifc_mcam_access_reg_bits { 8347 u8 reserved_at_0[0x1c]; 8348 u8 mcda[0x1]; 8349 u8 mcc[0x1]; 8350 u8 mcqi[0x1]; 8351 u8 reserved_at_1f[0x1]; 8352 8353 u8 regs_95_to_87[0x9]; 8354 u8 mpegc[0x1]; 8355 u8 regs_85_to_68[0x12]; 8356 u8 tracer_registers[0x4]; 8357 8358 u8 regs_63_to_32[0x20]; 8359 u8 regs_31_to_0[0x20]; 8360 }; 8361 8362 struct mlx5_ifc_mcam_reg_bits { 8363 u8 reserved_at_0[0x8]; 8364 u8 feature_group[0x8]; 8365 u8 reserved_at_10[0x8]; 8366 u8 access_reg_group[0x8]; 8367 8368 u8 reserved_at_20[0x20]; 8369 8370 union { 8371 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8372 u8 reserved_at_0[0x80]; 8373 } mng_access_reg_cap_mask; 8374 8375 u8 reserved_at_c0[0x80]; 8376 8377 union { 8378 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8379 u8 reserved_at_0[0x80]; 8380 } mng_feature_cap_mask; 8381 8382 u8 reserved_at_1c0[0x80]; 8383 }; 8384 8385 struct mlx5_ifc_qcam_access_reg_cap_mask { 8386 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8387 u8 qpdpm[0x1]; 8388 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8389 u8 qdpm[0x1]; 8390 u8 qpts[0x1]; 8391 u8 qcap[0x1]; 8392 u8 qcam_access_reg_cap_mask_0[0x1]; 8393 }; 8394 8395 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8396 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8397 u8 qpts_trust_both[0x1]; 8398 }; 8399 8400 struct mlx5_ifc_qcam_reg_bits { 8401 u8 reserved_at_0[0x8]; 8402 u8 feature_group[0x8]; 8403 u8 reserved_at_10[0x8]; 8404 u8 access_reg_group[0x8]; 8405 u8 reserved_at_20[0x20]; 8406 8407 union { 8408 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8409 u8 reserved_at_0[0x80]; 8410 } qos_access_reg_cap_mask; 8411 8412 u8 reserved_at_c0[0x80]; 8413 8414 union { 8415 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8416 u8 reserved_at_0[0x80]; 8417 } qos_feature_cap_mask; 8418 8419 u8 reserved_at_1c0[0x80]; 8420 }; 8421 8422 struct mlx5_ifc_pcap_reg_bits { 8423 u8 reserved_at_0[0x8]; 8424 u8 local_port[0x8]; 8425 u8 reserved_at_10[0x10]; 8426 8427 u8 port_capability_mask[4][0x20]; 8428 }; 8429 8430 struct mlx5_ifc_paos_reg_bits { 8431 u8 swid[0x8]; 8432 u8 local_port[0x8]; 8433 u8 reserved_at_10[0x4]; 8434 u8 admin_status[0x4]; 8435 u8 reserved_at_18[0x4]; 8436 u8 oper_status[0x4]; 8437 8438 u8 ase[0x1]; 8439 u8 ee[0x1]; 8440 u8 reserved_at_22[0x1c]; 8441 u8 e[0x2]; 8442 8443 u8 reserved_at_40[0x40]; 8444 }; 8445 8446 struct mlx5_ifc_pamp_reg_bits { 8447 u8 reserved_at_0[0x8]; 8448 u8 opamp_group[0x8]; 8449 u8 reserved_at_10[0xc]; 8450 u8 opamp_group_type[0x4]; 8451 8452 u8 start_index[0x10]; 8453 u8 reserved_at_30[0x4]; 8454 u8 num_of_indices[0xc]; 8455 8456 u8 index_data[18][0x10]; 8457 }; 8458 8459 struct mlx5_ifc_pcmr_reg_bits { 8460 u8 reserved_at_0[0x8]; 8461 u8 local_port[0x8]; 8462 u8 reserved_at_10[0x2e]; 8463 u8 fcs_cap[0x1]; 8464 u8 reserved_at_3f[0x1f]; 8465 u8 fcs_chk[0x1]; 8466 u8 reserved_at_5f[0x1]; 8467 }; 8468 8469 struct mlx5_ifc_lane_2_module_mapping_bits { 8470 u8 reserved_at_0[0x6]; 8471 u8 rx_lane[0x2]; 8472 u8 reserved_at_8[0x6]; 8473 u8 tx_lane[0x2]; 8474 u8 reserved_at_10[0x8]; 8475 u8 module[0x8]; 8476 }; 8477 8478 struct mlx5_ifc_bufferx_reg_bits { 8479 u8 reserved_at_0[0x6]; 8480 u8 lossy[0x1]; 8481 u8 epsb[0x1]; 8482 u8 reserved_at_8[0xc]; 8483 u8 size[0xc]; 8484 8485 u8 xoff_threshold[0x10]; 8486 u8 xon_threshold[0x10]; 8487 }; 8488 8489 struct mlx5_ifc_set_node_in_bits { 8490 u8 node_description[64][0x8]; 8491 }; 8492 8493 struct mlx5_ifc_register_power_settings_bits { 8494 u8 reserved_at_0[0x18]; 8495 u8 power_settings_level[0x8]; 8496 8497 u8 reserved_at_20[0x60]; 8498 }; 8499 8500 struct mlx5_ifc_register_host_endianness_bits { 8501 u8 he[0x1]; 8502 u8 reserved_at_1[0x1f]; 8503 8504 u8 reserved_at_20[0x60]; 8505 }; 8506 8507 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8508 u8 reserved_at_0[0x20]; 8509 8510 u8 mkey[0x20]; 8511 8512 u8 addressh_63_32[0x20]; 8513 8514 u8 addressl_31_0[0x20]; 8515 }; 8516 8517 struct mlx5_ifc_ud_adrs_vector_bits { 8518 u8 dc_key[0x40]; 8519 8520 u8 ext[0x1]; 8521 u8 reserved_at_41[0x7]; 8522 u8 destination_qp_dct[0x18]; 8523 8524 u8 static_rate[0x4]; 8525 u8 sl_eth_prio[0x4]; 8526 u8 fl[0x1]; 8527 u8 mlid[0x7]; 8528 u8 rlid_udp_sport[0x10]; 8529 8530 u8 reserved_at_80[0x20]; 8531 8532 u8 rmac_47_16[0x20]; 8533 8534 u8 rmac_15_0[0x10]; 8535 u8 tclass[0x8]; 8536 u8 hop_limit[0x8]; 8537 8538 u8 reserved_at_e0[0x1]; 8539 u8 grh[0x1]; 8540 u8 reserved_at_e2[0x2]; 8541 u8 src_addr_index[0x8]; 8542 u8 flow_label[0x14]; 8543 8544 u8 rgid_rip[16][0x8]; 8545 }; 8546 8547 struct mlx5_ifc_pages_req_event_bits { 8548 u8 reserved_at_0[0x10]; 8549 u8 function_id[0x10]; 8550 8551 u8 num_pages[0x20]; 8552 8553 u8 reserved_at_40[0xa0]; 8554 }; 8555 8556 struct mlx5_ifc_eqe_bits { 8557 u8 reserved_at_0[0x8]; 8558 u8 event_type[0x8]; 8559 u8 reserved_at_10[0x8]; 8560 u8 event_sub_type[0x8]; 8561 8562 u8 reserved_at_20[0xe0]; 8563 8564 union mlx5_ifc_event_auto_bits event_data; 8565 8566 u8 reserved_at_1e0[0x10]; 8567 u8 signature[0x8]; 8568 u8 reserved_at_1f8[0x7]; 8569 u8 owner[0x1]; 8570 }; 8571 8572 enum { 8573 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8574 }; 8575 8576 struct mlx5_ifc_cmd_queue_entry_bits { 8577 u8 type[0x8]; 8578 u8 reserved_at_8[0x18]; 8579 8580 u8 input_length[0x20]; 8581 8582 u8 input_mailbox_pointer_63_32[0x20]; 8583 8584 u8 input_mailbox_pointer_31_9[0x17]; 8585 u8 reserved_at_77[0x9]; 8586 8587 u8 command_input_inline_data[16][0x8]; 8588 8589 u8 command_output_inline_data[16][0x8]; 8590 8591 u8 output_mailbox_pointer_63_32[0x20]; 8592 8593 u8 output_mailbox_pointer_31_9[0x17]; 8594 u8 reserved_at_1b7[0x9]; 8595 8596 u8 output_length[0x20]; 8597 8598 u8 token[0x8]; 8599 u8 signature[0x8]; 8600 u8 reserved_at_1f0[0x8]; 8601 u8 status[0x7]; 8602 u8 ownership[0x1]; 8603 }; 8604 8605 struct mlx5_ifc_cmd_out_bits { 8606 u8 status[0x8]; 8607 u8 reserved_at_8[0x18]; 8608 8609 u8 syndrome[0x20]; 8610 8611 u8 command_output[0x20]; 8612 }; 8613 8614 struct mlx5_ifc_cmd_in_bits { 8615 u8 opcode[0x10]; 8616 u8 reserved_at_10[0x10]; 8617 8618 u8 reserved_at_20[0x10]; 8619 u8 op_mod[0x10]; 8620 8621 u8 command[0][0x20]; 8622 }; 8623 8624 struct mlx5_ifc_cmd_if_box_bits { 8625 u8 mailbox_data[512][0x8]; 8626 8627 u8 reserved_at_1000[0x180]; 8628 8629 u8 next_pointer_63_32[0x20]; 8630 8631 u8 next_pointer_31_10[0x16]; 8632 u8 reserved_at_11b6[0xa]; 8633 8634 u8 block_number[0x20]; 8635 8636 u8 reserved_at_11e0[0x8]; 8637 u8 token[0x8]; 8638 u8 ctrl_signature[0x8]; 8639 u8 signature[0x8]; 8640 }; 8641 8642 struct mlx5_ifc_mtt_bits { 8643 u8 ptag_63_32[0x20]; 8644 8645 u8 ptag_31_8[0x18]; 8646 u8 reserved_at_38[0x6]; 8647 u8 wr_en[0x1]; 8648 u8 rd_en[0x1]; 8649 }; 8650 8651 struct mlx5_ifc_query_wol_rol_out_bits { 8652 u8 status[0x8]; 8653 u8 reserved_at_8[0x18]; 8654 8655 u8 syndrome[0x20]; 8656 8657 u8 reserved_at_40[0x10]; 8658 u8 rol_mode[0x8]; 8659 u8 wol_mode[0x8]; 8660 8661 u8 reserved_at_60[0x20]; 8662 }; 8663 8664 struct mlx5_ifc_query_wol_rol_in_bits { 8665 u8 opcode[0x10]; 8666 u8 reserved_at_10[0x10]; 8667 8668 u8 reserved_at_20[0x10]; 8669 u8 op_mod[0x10]; 8670 8671 u8 reserved_at_40[0x40]; 8672 }; 8673 8674 struct mlx5_ifc_set_wol_rol_out_bits { 8675 u8 status[0x8]; 8676 u8 reserved_at_8[0x18]; 8677 8678 u8 syndrome[0x20]; 8679 8680 u8 reserved_at_40[0x40]; 8681 }; 8682 8683 struct mlx5_ifc_set_wol_rol_in_bits { 8684 u8 opcode[0x10]; 8685 u8 reserved_at_10[0x10]; 8686 8687 u8 reserved_at_20[0x10]; 8688 u8 op_mod[0x10]; 8689 8690 u8 rol_mode_valid[0x1]; 8691 u8 wol_mode_valid[0x1]; 8692 u8 reserved_at_42[0xe]; 8693 u8 rol_mode[0x8]; 8694 u8 wol_mode[0x8]; 8695 8696 u8 reserved_at_60[0x20]; 8697 }; 8698 8699 enum { 8700 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8701 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8702 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8703 }; 8704 8705 enum { 8706 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8707 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8708 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8709 }; 8710 8711 enum { 8712 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8713 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8714 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8715 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8716 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8717 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8723 }; 8724 8725 struct mlx5_ifc_initial_seg_bits { 8726 u8 fw_rev_minor[0x10]; 8727 u8 fw_rev_major[0x10]; 8728 8729 u8 cmd_interface_rev[0x10]; 8730 u8 fw_rev_subminor[0x10]; 8731 8732 u8 reserved_at_40[0x40]; 8733 8734 u8 cmdq_phy_addr_63_32[0x20]; 8735 8736 u8 cmdq_phy_addr_31_12[0x14]; 8737 u8 reserved_at_b4[0x2]; 8738 u8 nic_interface[0x2]; 8739 u8 log_cmdq_size[0x4]; 8740 u8 log_cmdq_stride[0x4]; 8741 8742 u8 command_doorbell_vector[0x20]; 8743 8744 u8 reserved_at_e0[0xf00]; 8745 8746 u8 initializing[0x1]; 8747 u8 reserved_at_fe1[0x4]; 8748 u8 nic_interface_supported[0x3]; 8749 u8 reserved_at_fe8[0x18]; 8750 8751 struct mlx5_ifc_health_buffer_bits health_buffer; 8752 8753 u8 no_dram_nic_offset[0x20]; 8754 8755 u8 reserved_at_1220[0x6e40]; 8756 8757 u8 reserved_at_8060[0x1f]; 8758 u8 clear_int[0x1]; 8759 8760 u8 health_syndrome[0x8]; 8761 u8 health_counter[0x18]; 8762 8763 u8 reserved_at_80a0[0x17fc0]; 8764 }; 8765 8766 struct mlx5_ifc_mtpps_reg_bits { 8767 u8 reserved_at_0[0xc]; 8768 u8 cap_number_of_pps_pins[0x4]; 8769 u8 reserved_at_10[0x4]; 8770 u8 cap_max_num_of_pps_in_pins[0x4]; 8771 u8 reserved_at_18[0x4]; 8772 u8 cap_max_num_of_pps_out_pins[0x4]; 8773 8774 u8 reserved_at_20[0x24]; 8775 u8 cap_pin_3_mode[0x4]; 8776 u8 reserved_at_48[0x4]; 8777 u8 cap_pin_2_mode[0x4]; 8778 u8 reserved_at_50[0x4]; 8779 u8 cap_pin_1_mode[0x4]; 8780 u8 reserved_at_58[0x4]; 8781 u8 cap_pin_0_mode[0x4]; 8782 8783 u8 reserved_at_60[0x4]; 8784 u8 cap_pin_7_mode[0x4]; 8785 u8 reserved_at_68[0x4]; 8786 u8 cap_pin_6_mode[0x4]; 8787 u8 reserved_at_70[0x4]; 8788 u8 cap_pin_5_mode[0x4]; 8789 u8 reserved_at_78[0x4]; 8790 u8 cap_pin_4_mode[0x4]; 8791 8792 u8 field_select[0x20]; 8793 u8 reserved_at_a0[0x60]; 8794 8795 u8 enable[0x1]; 8796 u8 reserved_at_101[0xb]; 8797 u8 pattern[0x4]; 8798 u8 reserved_at_110[0x4]; 8799 u8 pin_mode[0x4]; 8800 u8 pin[0x8]; 8801 8802 u8 reserved_at_120[0x20]; 8803 8804 u8 time_stamp[0x40]; 8805 8806 u8 out_pulse_duration[0x10]; 8807 u8 out_periodic_adjustment[0x10]; 8808 u8 enhanced_out_periodic_adjustment[0x20]; 8809 8810 u8 reserved_at_1c0[0x20]; 8811 }; 8812 8813 struct mlx5_ifc_mtppse_reg_bits { 8814 u8 reserved_at_0[0x18]; 8815 u8 pin[0x8]; 8816 u8 event_arm[0x1]; 8817 u8 reserved_at_21[0x1b]; 8818 u8 event_generation_mode[0x4]; 8819 u8 reserved_at_40[0x40]; 8820 }; 8821 8822 struct mlx5_ifc_mcqi_cap_bits { 8823 u8 supported_info_bitmask[0x20]; 8824 8825 u8 component_size[0x20]; 8826 8827 u8 max_component_size[0x20]; 8828 8829 u8 log_mcda_word_size[0x4]; 8830 u8 reserved_at_64[0xc]; 8831 u8 mcda_max_write_size[0x10]; 8832 8833 u8 rd_en[0x1]; 8834 u8 reserved_at_81[0x1]; 8835 u8 match_chip_id[0x1]; 8836 u8 match_psid[0x1]; 8837 u8 check_user_timestamp[0x1]; 8838 u8 match_base_guid_mac[0x1]; 8839 u8 reserved_at_86[0x1a]; 8840 }; 8841 8842 struct mlx5_ifc_mcqi_reg_bits { 8843 u8 read_pending_component[0x1]; 8844 u8 reserved_at_1[0xf]; 8845 u8 component_index[0x10]; 8846 8847 u8 reserved_at_20[0x20]; 8848 8849 u8 reserved_at_40[0x1b]; 8850 u8 info_type[0x5]; 8851 8852 u8 info_size[0x20]; 8853 8854 u8 offset[0x20]; 8855 8856 u8 reserved_at_a0[0x10]; 8857 u8 data_size[0x10]; 8858 8859 u8 data[0][0x20]; 8860 }; 8861 8862 struct mlx5_ifc_mcc_reg_bits { 8863 u8 reserved_at_0[0x4]; 8864 u8 time_elapsed_since_last_cmd[0xc]; 8865 u8 reserved_at_10[0x8]; 8866 u8 instruction[0x8]; 8867 8868 u8 reserved_at_20[0x10]; 8869 u8 component_index[0x10]; 8870 8871 u8 reserved_at_40[0x8]; 8872 u8 update_handle[0x18]; 8873 8874 u8 handle_owner_type[0x4]; 8875 u8 handle_owner_host_id[0x4]; 8876 u8 reserved_at_68[0x1]; 8877 u8 control_progress[0x7]; 8878 u8 error_code[0x8]; 8879 u8 reserved_at_78[0x4]; 8880 u8 control_state[0x4]; 8881 8882 u8 component_size[0x20]; 8883 8884 u8 reserved_at_a0[0x60]; 8885 }; 8886 8887 struct mlx5_ifc_mcda_reg_bits { 8888 u8 reserved_at_0[0x8]; 8889 u8 update_handle[0x18]; 8890 8891 u8 offset[0x20]; 8892 8893 u8 reserved_at_40[0x10]; 8894 u8 size[0x10]; 8895 8896 u8 reserved_at_60[0x20]; 8897 8898 u8 data[0][0x20]; 8899 }; 8900 8901 union mlx5_ifc_ports_control_registers_document_bits { 8902 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8903 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8904 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8905 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8906 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8907 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8908 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8909 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8910 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8911 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8912 struct mlx5_ifc_paos_reg_bits paos_reg; 8913 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8914 struct mlx5_ifc_peir_reg_bits peir_reg; 8915 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8916 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8917 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8918 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8919 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8920 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8921 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8922 struct mlx5_ifc_plib_reg_bits plib_reg; 8923 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8924 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8925 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8926 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8927 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8928 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8929 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8930 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8931 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8932 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8933 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8934 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8935 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8936 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8937 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8938 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8939 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8940 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8941 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8942 struct mlx5_ifc_pude_reg_bits pude_reg; 8943 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8944 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8945 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8946 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8947 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8948 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8949 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8950 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8951 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8952 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8953 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8954 u8 reserved_at_0[0x60e0]; 8955 }; 8956 8957 union mlx5_ifc_debug_enhancements_document_bits { 8958 struct mlx5_ifc_health_buffer_bits health_buffer; 8959 u8 reserved_at_0[0x200]; 8960 }; 8961 8962 union mlx5_ifc_uplink_pci_interface_document_bits { 8963 struct mlx5_ifc_initial_seg_bits initial_seg; 8964 u8 reserved_at_0[0x20060]; 8965 }; 8966 8967 struct mlx5_ifc_set_flow_table_root_out_bits { 8968 u8 status[0x8]; 8969 u8 reserved_at_8[0x18]; 8970 8971 u8 syndrome[0x20]; 8972 8973 u8 reserved_at_40[0x40]; 8974 }; 8975 8976 struct mlx5_ifc_set_flow_table_root_in_bits { 8977 u8 opcode[0x10]; 8978 u8 reserved_at_10[0x10]; 8979 8980 u8 reserved_at_20[0x10]; 8981 u8 op_mod[0x10]; 8982 8983 u8 other_vport[0x1]; 8984 u8 reserved_at_41[0xf]; 8985 u8 vport_number[0x10]; 8986 8987 u8 reserved_at_60[0x20]; 8988 8989 u8 table_type[0x8]; 8990 u8 reserved_at_88[0x18]; 8991 8992 u8 reserved_at_a0[0x8]; 8993 u8 table_id[0x18]; 8994 8995 u8 reserved_at_c0[0x8]; 8996 u8 underlay_qpn[0x18]; 8997 u8 reserved_at_e0[0x120]; 8998 }; 8999 9000 enum { 9001 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9002 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9003 }; 9004 9005 struct mlx5_ifc_modify_flow_table_out_bits { 9006 u8 status[0x8]; 9007 u8 reserved_at_8[0x18]; 9008 9009 u8 syndrome[0x20]; 9010 9011 u8 reserved_at_40[0x40]; 9012 }; 9013 9014 struct mlx5_ifc_modify_flow_table_in_bits { 9015 u8 opcode[0x10]; 9016 u8 reserved_at_10[0x10]; 9017 9018 u8 reserved_at_20[0x10]; 9019 u8 op_mod[0x10]; 9020 9021 u8 other_vport[0x1]; 9022 u8 reserved_at_41[0xf]; 9023 u8 vport_number[0x10]; 9024 9025 u8 reserved_at_60[0x10]; 9026 u8 modify_field_select[0x10]; 9027 9028 u8 table_type[0x8]; 9029 u8 reserved_at_88[0x18]; 9030 9031 u8 reserved_at_a0[0x8]; 9032 u8 table_id[0x18]; 9033 9034 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9035 }; 9036 9037 struct mlx5_ifc_ets_tcn_config_reg_bits { 9038 u8 g[0x1]; 9039 u8 b[0x1]; 9040 u8 r[0x1]; 9041 u8 reserved_at_3[0x9]; 9042 u8 group[0x4]; 9043 u8 reserved_at_10[0x9]; 9044 u8 bw_allocation[0x7]; 9045 9046 u8 reserved_at_20[0xc]; 9047 u8 max_bw_units[0x4]; 9048 u8 reserved_at_30[0x8]; 9049 u8 max_bw_value[0x8]; 9050 }; 9051 9052 struct mlx5_ifc_ets_global_config_reg_bits { 9053 u8 reserved_at_0[0x2]; 9054 u8 r[0x1]; 9055 u8 reserved_at_3[0x1d]; 9056 9057 u8 reserved_at_20[0xc]; 9058 u8 max_bw_units[0x4]; 9059 u8 reserved_at_30[0x8]; 9060 u8 max_bw_value[0x8]; 9061 }; 9062 9063 struct mlx5_ifc_qetc_reg_bits { 9064 u8 reserved_at_0[0x8]; 9065 u8 port_number[0x8]; 9066 u8 reserved_at_10[0x30]; 9067 9068 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9069 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9070 }; 9071 9072 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9073 u8 e[0x1]; 9074 u8 reserved_at_01[0x0b]; 9075 u8 prio[0x04]; 9076 }; 9077 9078 struct mlx5_ifc_qpdpm_reg_bits { 9079 u8 reserved_at_0[0x8]; 9080 u8 local_port[0x8]; 9081 u8 reserved_at_10[0x10]; 9082 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9083 }; 9084 9085 struct mlx5_ifc_qpts_reg_bits { 9086 u8 reserved_at_0[0x8]; 9087 u8 local_port[0x8]; 9088 u8 reserved_at_10[0x2d]; 9089 u8 trust_state[0x3]; 9090 }; 9091 9092 struct mlx5_ifc_pptb_reg_bits { 9093 u8 reserved_at_0[0x2]; 9094 u8 mm[0x2]; 9095 u8 reserved_at_4[0x4]; 9096 u8 local_port[0x8]; 9097 u8 reserved_at_10[0x6]; 9098 u8 cm[0x1]; 9099 u8 um[0x1]; 9100 u8 pm[0x8]; 9101 9102 u8 prio_x_buff[0x20]; 9103 9104 u8 pm_msb[0x8]; 9105 u8 reserved_at_48[0x10]; 9106 u8 ctrl_buff[0x4]; 9107 u8 untagged_buff[0x4]; 9108 }; 9109 9110 struct mlx5_ifc_pbmc_reg_bits { 9111 u8 reserved_at_0[0x8]; 9112 u8 local_port[0x8]; 9113 u8 reserved_at_10[0x10]; 9114 9115 u8 xoff_timer_value[0x10]; 9116 u8 xoff_refresh[0x10]; 9117 9118 u8 reserved_at_40[0x9]; 9119 u8 fullness_threshold[0x7]; 9120 u8 port_buffer_size[0x10]; 9121 9122 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9123 9124 u8 reserved_at_2e0[0x40]; 9125 }; 9126 9127 struct mlx5_ifc_qtct_reg_bits { 9128 u8 reserved_at_0[0x8]; 9129 u8 port_number[0x8]; 9130 u8 reserved_at_10[0xd]; 9131 u8 prio[0x3]; 9132 9133 u8 reserved_at_20[0x1d]; 9134 u8 tclass[0x3]; 9135 }; 9136 9137 struct mlx5_ifc_mcia_reg_bits { 9138 u8 l[0x1]; 9139 u8 reserved_at_1[0x7]; 9140 u8 module[0x8]; 9141 u8 reserved_at_10[0x8]; 9142 u8 status[0x8]; 9143 9144 u8 i2c_device_address[0x8]; 9145 u8 page_number[0x8]; 9146 u8 device_address[0x10]; 9147 9148 u8 reserved_at_40[0x10]; 9149 u8 size[0x10]; 9150 9151 u8 reserved_at_60[0x20]; 9152 9153 u8 dword_0[0x20]; 9154 u8 dword_1[0x20]; 9155 u8 dword_2[0x20]; 9156 u8 dword_3[0x20]; 9157 u8 dword_4[0x20]; 9158 u8 dword_5[0x20]; 9159 u8 dword_6[0x20]; 9160 u8 dword_7[0x20]; 9161 u8 dword_8[0x20]; 9162 u8 dword_9[0x20]; 9163 u8 dword_10[0x20]; 9164 u8 dword_11[0x20]; 9165 }; 9166 9167 struct mlx5_ifc_dcbx_param_bits { 9168 u8 dcbx_cee_cap[0x1]; 9169 u8 dcbx_ieee_cap[0x1]; 9170 u8 dcbx_standby_cap[0x1]; 9171 u8 reserved_at_3[0x5]; 9172 u8 port_number[0x8]; 9173 u8 reserved_at_10[0xa]; 9174 u8 max_application_table_size[6]; 9175 u8 reserved_at_20[0x15]; 9176 u8 version_oper[0x3]; 9177 u8 reserved_at_38[5]; 9178 u8 version_admin[0x3]; 9179 u8 willing_admin[0x1]; 9180 u8 reserved_at_41[0x3]; 9181 u8 pfc_cap_oper[0x4]; 9182 u8 reserved_at_48[0x4]; 9183 u8 pfc_cap_admin[0x4]; 9184 u8 reserved_at_50[0x4]; 9185 u8 num_of_tc_oper[0x4]; 9186 u8 reserved_at_58[0x4]; 9187 u8 num_of_tc_admin[0x4]; 9188 u8 remote_willing[0x1]; 9189 u8 reserved_at_61[3]; 9190 u8 remote_pfc_cap[4]; 9191 u8 reserved_at_68[0x14]; 9192 u8 remote_num_of_tc[0x4]; 9193 u8 reserved_at_80[0x18]; 9194 u8 error[0x8]; 9195 u8 reserved_at_a0[0x160]; 9196 }; 9197 9198 struct mlx5_ifc_lagc_bits { 9199 u8 reserved_at_0[0x1d]; 9200 u8 lag_state[0x3]; 9201 9202 u8 reserved_at_20[0x14]; 9203 u8 tx_remap_affinity_2[0x4]; 9204 u8 reserved_at_38[0x4]; 9205 u8 tx_remap_affinity_1[0x4]; 9206 }; 9207 9208 struct mlx5_ifc_create_lag_out_bits { 9209 u8 status[0x8]; 9210 u8 reserved_at_8[0x18]; 9211 9212 u8 syndrome[0x20]; 9213 9214 u8 reserved_at_40[0x40]; 9215 }; 9216 9217 struct mlx5_ifc_create_lag_in_bits { 9218 u8 opcode[0x10]; 9219 u8 reserved_at_10[0x10]; 9220 9221 u8 reserved_at_20[0x10]; 9222 u8 op_mod[0x10]; 9223 9224 struct mlx5_ifc_lagc_bits ctx; 9225 }; 9226 9227 struct mlx5_ifc_modify_lag_out_bits { 9228 u8 status[0x8]; 9229 u8 reserved_at_8[0x18]; 9230 9231 u8 syndrome[0x20]; 9232 9233 u8 reserved_at_40[0x40]; 9234 }; 9235 9236 struct mlx5_ifc_modify_lag_in_bits { 9237 u8 opcode[0x10]; 9238 u8 reserved_at_10[0x10]; 9239 9240 u8 reserved_at_20[0x10]; 9241 u8 op_mod[0x10]; 9242 9243 u8 reserved_at_40[0x20]; 9244 u8 field_select[0x20]; 9245 9246 struct mlx5_ifc_lagc_bits ctx; 9247 }; 9248 9249 struct mlx5_ifc_query_lag_out_bits { 9250 u8 status[0x8]; 9251 u8 reserved_at_8[0x18]; 9252 9253 u8 syndrome[0x20]; 9254 9255 u8 reserved_at_40[0x40]; 9256 9257 struct mlx5_ifc_lagc_bits ctx; 9258 }; 9259 9260 struct mlx5_ifc_query_lag_in_bits { 9261 u8 opcode[0x10]; 9262 u8 reserved_at_10[0x10]; 9263 9264 u8 reserved_at_20[0x10]; 9265 u8 op_mod[0x10]; 9266 9267 u8 reserved_at_40[0x40]; 9268 }; 9269 9270 struct mlx5_ifc_destroy_lag_out_bits { 9271 u8 status[0x8]; 9272 u8 reserved_at_8[0x18]; 9273 9274 u8 syndrome[0x20]; 9275 9276 u8 reserved_at_40[0x40]; 9277 }; 9278 9279 struct mlx5_ifc_destroy_lag_in_bits { 9280 u8 opcode[0x10]; 9281 u8 reserved_at_10[0x10]; 9282 9283 u8 reserved_at_20[0x10]; 9284 u8 op_mod[0x10]; 9285 9286 u8 reserved_at_40[0x40]; 9287 }; 9288 9289 struct mlx5_ifc_create_vport_lag_out_bits { 9290 u8 status[0x8]; 9291 u8 reserved_at_8[0x18]; 9292 9293 u8 syndrome[0x20]; 9294 9295 u8 reserved_at_40[0x40]; 9296 }; 9297 9298 struct mlx5_ifc_create_vport_lag_in_bits { 9299 u8 opcode[0x10]; 9300 u8 reserved_at_10[0x10]; 9301 9302 u8 reserved_at_20[0x10]; 9303 u8 op_mod[0x10]; 9304 9305 u8 reserved_at_40[0x40]; 9306 }; 9307 9308 struct mlx5_ifc_destroy_vport_lag_out_bits { 9309 u8 status[0x8]; 9310 u8 reserved_at_8[0x18]; 9311 9312 u8 syndrome[0x20]; 9313 9314 u8 reserved_at_40[0x40]; 9315 }; 9316 9317 struct mlx5_ifc_destroy_vport_lag_in_bits { 9318 u8 opcode[0x10]; 9319 u8 reserved_at_10[0x10]; 9320 9321 u8 reserved_at_20[0x10]; 9322 u8 op_mod[0x10]; 9323 9324 u8 reserved_at_40[0x40]; 9325 }; 9326 9327 struct mlx5_ifc_alloc_memic_in_bits { 9328 u8 opcode[0x10]; 9329 u8 reserved_at_10[0x10]; 9330 9331 u8 reserved_at_20[0x10]; 9332 u8 op_mod[0x10]; 9333 9334 u8 reserved_at_30[0x20]; 9335 9336 u8 reserved_at_40[0x18]; 9337 u8 log_memic_addr_alignment[0x8]; 9338 9339 u8 range_start_addr[0x40]; 9340 9341 u8 range_size[0x20]; 9342 9343 u8 memic_size[0x20]; 9344 }; 9345 9346 struct mlx5_ifc_alloc_memic_out_bits { 9347 u8 status[0x8]; 9348 u8 reserved_at_8[0x18]; 9349 9350 u8 syndrome[0x20]; 9351 9352 u8 memic_start_addr[0x40]; 9353 }; 9354 9355 struct mlx5_ifc_dealloc_memic_in_bits { 9356 u8 opcode[0x10]; 9357 u8 reserved_at_10[0x10]; 9358 9359 u8 reserved_at_20[0x10]; 9360 u8 op_mod[0x10]; 9361 9362 u8 reserved_at_40[0x40]; 9363 9364 u8 memic_start_addr[0x40]; 9365 9366 u8 memic_size[0x20]; 9367 9368 u8 reserved_at_e0[0x20]; 9369 }; 9370 9371 struct mlx5_ifc_dealloc_memic_out_bits { 9372 u8 status[0x8]; 9373 u8 reserved_at_8[0x18]; 9374 9375 u8 syndrome[0x20]; 9376 9377 u8 reserved_at_40[0x40]; 9378 }; 9379 9380 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9381 u8 opcode[0x10]; 9382 u8 uid[0x10]; 9383 9384 u8 reserved_at_20[0x10]; 9385 u8 obj_type[0x10]; 9386 9387 u8 obj_id[0x20]; 9388 9389 u8 reserved_at_60[0x20]; 9390 }; 9391 9392 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9393 u8 status[0x8]; 9394 u8 reserved_at_8[0x18]; 9395 9396 u8 syndrome[0x20]; 9397 9398 u8 obj_id[0x20]; 9399 9400 u8 reserved_at_60[0x20]; 9401 }; 9402 9403 struct mlx5_ifc_umem_bits { 9404 u8 reserved_at_0[0x80]; 9405 9406 u8 reserved_at_80[0x1b]; 9407 u8 log_page_size[0x5]; 9408 9409 u8 page_offset[0x20]; 9410 9411 u8 num_of_mtt[0x40]; 9412 9413 struct mlx5_ifc_mtt_bits mtt[0]; 9414 }; 9415 9416 struct mlx5_ifc_uctx_bits { 9417 u8 cap[0x20]; 9418 9419 u8 reserved_at_20[0x160]; 9420 }; 9421 9422 struct mlx5_ifc_create_umem_in_bits { 9423 u8 opcode[0x10]; 9424 u8 uid[0x10]; 9425 9426 u8 reserved_at_20[0x10]; 9427 u8 op_mod[0x10]; 9428 9429 u8 reserved_at_40[0x40]; 9430 9431 struct mlx5_ifc_umem_bits umem; 9432 }; 9433 9434 struct mlx5_ifc_create_uctx_in_bits { 9435 u8 opcode[0x10]; 9436 u8 reserved_at_10[0x10]; 9437 9438 u8 reserved_at_20[0x10]; 9439 u8 op_mod[0x10]; 9440 9441 u8 reserved_at_40[0x40]; 9442 9443 struct mlx5_ifc_uctx_bits uctx; 9444 }; 9445 9446 struct mlx5_ifc_destroy_uctx_in_bits { 9447 u8 opcode[0x10]; 9448 u8 reserved_at_10[0x10]; 9449 9450 u8 reserved_at_20[0x10]; 9451 u8 op_mod[0x10]; 9452 9453 u8 reserved_at_40[0x10]; 9454 u8 uid[0x10]; 9455 9456 u8 reserved_at_60[0x20]; 9457 }; 9458 9459 struct mlx5_ifc_mtrc_string_db_param_bits { 9460 u8 string_db_base_address[0x20]; 9461 9462 u8 reserved_at_20[0x8]; 9463 u8 string_db_size[0x18]; 9464 }; 9465 9466 struct mlx5_ifc_mtrc_cap_bits { 9467 u8 trace_owner[0x1]; 9468 u8 trace_to_memory[0x1]; 9469 u8 reserved_at_2[0x4]; 9470 u8 trc_ver[0x2]; 9471 u8 reserved_at_8[0x14]; 9472 u8 num_string_db[0x4]; 9473 9474 u8 first_string_trace[0x8]; 9475 u8 num_string_trace[0x8]; 9476 u8 reserved_at_30[0x28]; 9477 9478 u8 log_max_trace_buffer_size[0x8]; 9479 9480 u8 reserved_at_60[0x20]; 9481 9482 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9483 9484 u8 reserved_at_280[0x180]; 9485 }; 9486 9487 struct mlx5_ifc_mtrc_conf_bits { 9488 u8 reserved_at_0[0x1c]; 9489 u8 trace_mode[0x4]; 9490 u8 reserved_at_20[0x18]; 9491 u8 log_trace_buffer_size[0x8]; 9492 u8 trace_mkey[0x20]; 9493 u8 reserved_at_60[0x3a0]; 9494 }; 9495 9496 struct mlx5_ifc_mtrc_stdb_bits { 9497 u8 string_db_index[0x4]; 9498 u8 reserved_at_4[0x4]; 9499 u8 read_size[0x18]; 9500 u8 start_offset[0x20]; 9501 u8 string_db_data[0]; 9502 }; 9503 9504 struct mlx5_ifc_mtrc_ctrl_bits { 9505 u8 trace_status[0x2]; 9506 u8 reserved_at_2[0x2]; 9507 u8 arm_event[0x1]; 9508 u8 reserved_at_5[0xb]; 9509 u8 modify_field_select[0x10]; 9510 u8 reserved_at_20[0x2b]; 9511 u8 current_timestamp52_32[0x15]; 9512 u8 current_timestamp31_0[0x20]; 9513 u8 reserved_at_80[0x180]; 9514 }; 9515 9516 #endif /* MLX5_IFC_H */ 9517