1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 82 }; 83 84 enum { 85 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 86 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 87 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 88 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 89 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 90 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 96 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 99 MLX5_OBJ_TYPE_MKEY = 0xff01, 100 MLX5_OBJ_TYPE_QP = 0xff02, 101 MLX5_OBJ_TYPE_PSV = 0xff03, 102 MLX5_OBJ_TYPE_RMP = 0xff04, 103 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 104 MLX5_OBJ_TYPE_RQ = 0xff06, 105 MLX5_OBJ_TYPE_SQ = 0xff07, 106 MLX5_OBJ_TYPE_TIR = 0xff08, 107 MLX5_OBJ_TYPE_TIS = 0xff09, 108 MLX5_OBJ_TYPE_DCT = 0xff0a, 109 MLX5_OBJ_TYPE_XRQ = 0xff0b, 110 MLX5_OBJ_TYPE_RQT = 0xff0e, 111 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 112 MLX5_OBJ_TYPE_CQ = 0xff10, 113 }; 114 115 enum { 116 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 117 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 118 MLX5_CMD_OP_INIT_HCA = 0x102, 119 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 120 MLX5_CMD_OP_ENABLE_HCA = 0x104, 121 MLX5_CMD_OP_DISABLE_HCA = 0x105, 122 MLX5_CMD_OP_QUERY_PAGES = 0x107, 123 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 124 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 125 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 126 MLX5_CMD_OP_SET_ISSI = 0x10b, 127 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 128 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 129 MLX5_CMD_OP_ALLOC_SF = 0x113, 130 MLX5_CMD_OP_DEALLOC_SF = 0x114, 131 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 132 MLX5_CMD_OP_RESUME_VHCA = 0x116, 133 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 134 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 135 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 136 MLX5_CMD_OP_CREATE_MKEY = 0x200, 137 MLX5_CMD_OP_QUERY_MKEY = 0x201, 138 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 139 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 140 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 141 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 142 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 143 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 144 MLX5_CMD_OP_CREATE_EQ = 0x301, 145 MLX5_CMD_OP_DESTROY_EQ = 0x302, 146 MLX5_CMD_OP_QUERY_EQ = 0x303, 147 MLX5_CMD_OP_GEN_EQE = 0x304, 148 MLX5_CMD_OP_CREATE_CQ = 0x400, 149 MLX5_CMD_OP_DESTROY_CQ = 0x401, 150 MLX5_CMD_OP_QUERY_CQ = 0x402, 151 MLX5_CMD_OP_MODIFY_CQ = 0x403, 152 MLX5_CMD_OP_CREATE_QP = 0x500, 153 MLX5_CMD_OP_DESTROY_QP = 0x501, 154 MLX5_CMD_OP_RST2INIT_QP = 0x502, 155 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 156 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 157 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 158 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 159 MLX5_CMD_OP_2ERR_QP = 0x507, 160 MLX5_CMD_OP_2RST_QP = 0x50a, 161 MLX5_CMD_OP_QUERY_QP = 0x50b, 162 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 163 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 164 MLX5_CMD_OP_CREATE_PSV = 0x600, 165 MLX5_CMD_OP_DESTROY_PSV = 0x601, 166 MLX5_CMD_OP_CREATE_SRQ = 0x700, 167 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 168 MLX5_CMD_OP_QUERY_SRQ = 0x702, 169 MLX5_CMD_OP_ARM_RQ = 0x703, 170 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 171 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 172 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 173 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 174 MLX5_CMD_OP_CREATE_DCT = 0x710, 175 MLX5_CMD_OP_DESTROY_DCT = 0x711, 176 MLX5_CMD_OP_DRAIN_DCT = 0x712, 177 MLX5_CMD_OP_QUERY_DCT = 0x713, 178 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 179 MLX5_CMD_OP_CREATE_XRQ = 0x717, 180 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 181 MLX5_CMD_OP_QUERY_XRQ = 0x719, 182 MLX5_CMD_OP_ARM_XRQ = 0x71a, 183 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 184 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 185 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 186 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 187 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 188 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 189 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 190 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 191 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 192 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 193 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 194 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 195 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 196 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 198 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 200 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 201 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 202 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 203 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 204 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 205 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 206 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 207 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 208 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 209 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 210 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 211 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 212 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 213 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 214 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 215 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 216 MLX5_CMD_OP_ALLOC_PD = 0x800, 217 MLX5_CMD_OP_DEALLOC_PD = 0x801, 218 MLX5_CMD_OP_ALLOC_UAR = 0x802, 219 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 220 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 221 MLX5_CMD_OP_ACCESS_REG = 0x805, 222 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 223 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 224 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 225 MLX5_CMD_OP_MAD_IFC = 0x50d, 226 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 227 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 228 MLX5_CMD_OP_NOP = 0x80d, 229 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 230 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 231 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 232 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 233 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 234 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 235 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 236 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 237 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 238 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 239 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 240 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 241 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 242 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 243 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 244 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 245 MLX5_CMD_OP_CREATE_LAG = 0x840, 246 MLX5_CMD_OP_MODIFY_LAG = 0x841, 247 MLX5_CMD_OP_QUERY_LAG = 0x842, 248 MLX5_CMD_OP_DESTROY_LAG = 0x843, 249 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 250 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 251 MLX5_CMD_OP_CREATE_TIR = 0x900, 252 MLX5_CMD_OP_MODIFY_TIR = 0x901, 253 MLX5_CMD_OP_DESTROY_TIR = 0x902, 254 MLX5_CMD_OP_QUERY_TIR = 0x903, 255 MLX5_CMD_OP_CREATE_SQ = 0x904, 256 MLX5_CMD_OP_MODIFY_SQ = 0x905, 257 MLX5_CMD_OP_DESTROY_SQ = 0x906, 258 MLX5_CMD_OP_QUERY_SQ = 0x907, 259 MLX5_CMD_OP_CREATE_RQ = 0x908, 260 MLX5_CMD_OP_MODIFY_RQ = 0x909, 261 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 262 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 263 MLX5_CMD_OP_QUERY_RQ = 0x90b, 264 MLX5_CMD_OP_CREATE_RMP = 0x90c, 265 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 266 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 267 MLX5_CMD_OP_QUERY_RMP = 0x90f, 268 MLX5_CMD_OP_CREATE_TIS = 0x912, 269 MLX5_CMD_OP_MODIFY_TIS = 0x913, 270 MLX5_CMD_OP_DESTROY_TIS = 0x914, 271 MLX5_CMD_OP_QUERY_TIS = 0x915, 272 MLX5_CMD_OP_CREATE_RQT = 0x916, 273 MLX5_CMD_OP_MODIFY_RQT = 0x917, 274 MLX5_CMD_OP_DESTROY_RQT = 0x918, 275 MLX5_CMD_OP_QUERY_RQT = 0x919, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 277 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 278 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 279 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 280 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 281 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 282 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 284 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 285 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 286 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 287 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 288 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 289 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 290 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 291 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 292 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 293 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 294 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 295 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 296 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 297 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 298 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 299 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 301 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 302 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 303 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 304 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 305 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 306 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 307 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 308 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 309 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 310 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 311 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 312 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 313 MLX5_CMD_OP_MAX 314 }; 315 316 /* Valid range for general commands that don't work over an object */ 317 enum { 318 MLX5_CMD_OP_GENERAL_START = 0xb00, 319 MLX5_CMD_OP_GENERAL_END = 0xd00, 320 }; 321 322 enum { 323 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 324 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 325 }; 326 327 enum { 328 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 329 }; 330 331 struct mlx5_ifc_flow_table_fields_supported_bits { 332 u8 outer_dmac[0x1]; 333 u8 outer_smac[0x1]; 334 u8 outer_ether_type[0x1]; 335 u8 outer_ip_version[0x1]; 336 u8 outer_first_prio[0x1]; 337 u8 outer_first_cfi[0x1]; 338 u8 outer_first_vid[0x1]; 339 u8 outer_ipv4_ttl[0x1]; 340 u8 outer_second_prio[0x1]; 341 u8 outer_second_cfi[0x1]; 342 u8 outer_second_vid[0x1]; 343 u8 reserved_at_b[0x1]; 344 u8 outer_sip[0x1]; 345 u8 outer_dip[0x1]; 346 u8 outer_frag[0x1]; 347 u8 outer_ip_protocol[0x1]; 348 u8 outer_ip_ecn[0x1]; 349 u8 outer_ip_dscp[0x1]; 350 u8 outer_udp_sport[0x1]; 351 u8 outer_udp_dport[0x1]; 352 u8 outer_tcp_sport[0x1]; 353 u8 outer_tcp_dport[0x1]; 354 u8 outer_tcp_flags[0x1]; 355 u8 outer_gre_protocol[0x1]; 356 u8 outer_gre_key[0x1]; 357 u8 outer_vxlan_vni[0x1]; 358 u8 outer_geneve_vni[0x1]; 359 u8 outer_geneve_oam[0x1]; 360 u8 outer_geneve_protocol_type[0x1]; 361 u8 outer_geneve_opt_len[0x1]; 362 u8 source_vhca_port[0x1]; 363 u8 source_eswitch_port[0x1]; 364 365 u8 inner_dmac[0x1]; 366 u8 inner_smac[0x1]; 367 u8 inner_ether_type[0x1]; 368 u8 inner_ip_version[0x1]; 369 u8 inner_first_prio[0x1]; 370 u8 inner_first_cfi[0x1]; 371 u8 inner_first_vid[0x1]; 372 u8 reserved_at_27[0x1]; 373 u8 inner_second_prio[0x1]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0x1]; 376 u8 reserved_at_2b[0x1]; 377 u8 inner_sip[0x1]; 378 u8 inner_dip[0x1]; 379 u8 inner_frag[0x1]; 380 u8 inner_ip_protocol[0x1]; 381 u8 inner_ip_ecn[0x1]; 382 u8 inner_ip_dscp[0x1]; 383 u8 inner_udp_sport[0x1]; 384 u8 inner_udp_dport[0x1]; 385 u8 inner_tcp_sport[0x1]; 386 u8 inner_tcp_dport[0x1]; 387 u8 inner_tcp_flags[0x1]; 388 u8 reserved_at_37[0x9]; 389 390 u8 geneve_tlv_option_0_data[0x1]; 391 u8 geneve_tlv_option_0_exist[0x1]; 392 u8 reserved_at_42[0x3]; 393 u8 outer_first_mpls_over_udp[0x4]; 394 u8 outer_first_mpls_over_gre[0x4]; 395 u8 inner_first_mpls[0x4]; 396 u8 outer_first_mpls[0x4]; 397 u8 reserved_at_55[0x2]; 398 u8 outer_esp_spi[0x1]; 399 u8 reserved_at_58[0x2]; 400 u8 bth_dst_qp[0x1]; 401 u8 reserved_at_5b[0x5]; 402 403 u8 reserved_at_60[0x18]; 404 u8 metadata_reg_c_7[0x1]; 405 u8 metadata_reg_c_6[0x1]; 406 u8 metadata_reg_c_5[0x1]; 407 u8 metadata_reg_c_4[0x1]; 408 u8 metadata_reg_c_3[0x1]; 409 u8 metadata_reg_c_2[0x1]; 410 u8 metadata_reg_c_1[0x1]; 411 u8 metadata_reg_c_0[0x1]; 412 }; 413 414 /* Table 2170 - Flow Table Fields Supported 2 Format */ 415 struct mlx5_ifc_flow_table_fields_supported_2_bits { 416 u8 reserved_at_0[0xe]; 417 u8 bth_opcode[0x1]; 418 u8 reserved_at_f[0x1]; 419 u8 tunnel_header_0_1[0x1]; 420 u8 reserved_at_11[0xf]; 421 422 u8 reserved_at_20[0x60]; 423 }; 424 425 struct mlx5_ifc_flow_table_prop_layout_bits { 426 u8 ft_support[0x1]; 427 u8 reserved_at_1[0x1]; 428 u8 flow_counter[0x1]; 429 u8 flow_modify_en[0x1]; 430 u8 modify_root[0x1]; 431 u8 identified_miss_table_mode[0x1]; 432 u8 flow_table_modify[0x1]; 433 u8 reformat[0x1]; 434 u8 decap[0x1]; 435 u8 reserved_at_9[0x1]; 436 u8 pop_vlan[0x1]; 437 u8 push_vlan[0x1]; 438 u8 reserved_at_c[0x1]; 439 u8 pop_vlan_2[0x1]; 440 u8 push_vlan_2[0x1]; 441 u8 reformat_and_vlan_action[0x1]; 442 u8 reserved_at_10[0x1]; 443 u8 sw_owner[0x1]; 444 u8 reformat_l3_tunnel_to_l2[0x1]; 445 u8 reformat_l2_to_l3_tunnel[0x1]; 446 u8 reformat_and_modify_action[0x1]; 447 u8 ignore_flow_level[0x1]; 448 u8 reserved_at_16[0x1]; 449 u8 table_miss_action_domain[0x1]; 450 u8 termination_table[0x1]; 451 u8 reformat_and_fwd_to_table[0x1]; 452 u8 reserved_at_1a[0x2]; 453 u8 ipsec_encrypt[0x1]; 454 u8 ipsec_decrypt[0x1]; 455 u8 sw_owner_v2[0x1]; 456 u8 reserved_at_1f[0x1]; 457 458 u8 termination_table_raw_traffic[0x1]; 459 u8 reserved_at_21[0x1]; 460 u8 log_max_ft_size[0x6]; 461 u8 log_max_modify_header_context[0x8]; 462 u8 max_modify_header_actions[0x8]; 463 u8 max_ft_level[0x8]; 464 465 u8 reformat_add_esp_trasport[0x1]; 466 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 467 u8 reformat_add_esp_transport_over_udp[0x1]; 468 u8 reformat_del_esp_trasport[0x1]; 469 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 470 u8 reformat_del_esp_transport_over_udp[0x1]; 471 u8 execute_aso[0x1]; 472 u8 reserved_at_47[0x19]; 473 474 u8 reserved_at_60[0x2]; 475 u8 reformat_insert[0x1]; 476 u8 reformat_remove[0x1]; 477 u8 macsec_encrypt[0x1]; 478 u8 macsec_decrypt[0x1]; 479 u8 reserved_at_66[0x2]; 480 u8 reformat_add_macsec[0x1]; 481 u8 reformat_remove_macsec[0x1]; 482 u8 reserved_at_6a[0xe]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_at_6[0x1a]; 507 }; 508 509 struct mlx5_ifc_ipv4_layout_bits { 510 u8 reserved_at_0[0x60]; 511 512 u8 ipv4[0x20]; 513 }; 514 515 struct mlx5_ifc_ipv6_layout_bits { 516 u8 ipv6[16][0x8]; 517 }; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 520 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 521 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 522 u8 reserved_at_0[0x80]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 526 u8 smac_47_16[0x20]; 527 528 u8 smac_15_0[0x10]; 529 u8 ethertype[0x10]; 530 531 u8 dmac_47_16[0x20]; 532 533 u8 dmac_15_0[0x10]; 534 u8 first_prio[0x3]; 535 u8 first_cfi[0x1]; 536 u8 first_vid[0xc]; 537 538 u8 ip_protocol[0x8]; 539 u8 ip_dscp[0x6]; 540 u8 ip_ecn[0x2]; 541 u8 cvlan_tag[0x1]; 542 u8 svlan_tag[0x1]; 543 u8 frag[0x1]; 544 u8 ip_version[0x4]; 545 u8 tcp_flags[0x9]; 546 547 u8 tcp_sport[0x10]; 548 u8 tcp_dport[0x10]; 549 550 u8 reserved_at_c0[0x10]; 551 u8 ipv4_ihl[0x4]; 552 u8 reserved_at_c4[0x4]; 553 554 u8 ttl_hoplimit[0x8]; 555 556 u8 udp_sport[0x10]; 557 u8 udp_dport[0x10]; 558 559 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 560 561 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 562 }; 563 564 struct mlx5_ifc_nvgre_key_bits { 565 u8 hi[0x18]; 566 u8 lo[0x8]; 567 }; 568 569 union mlx5_ifc_gre_key_bits { 570 struct mlx5_ifc_nvgre_key_bits nvgre; 571 u8 key[0x20]; 572 }; 573 574 struct mlx5_ifc_fte_match_set_misc_bits { 575 u8 gre_c_present[0x1]; 576 u8 reserved_at_1[0x1]; 577 u8 gre_k_present[0x1]; 578 u8 gre_s_present[0x1]; 579 u8 source_vhca_port[0x4]; 580 u8 source_sqn[0x18]; 581 582 u8 source_eswitch_owner_vhca_id[0x10]; 583 u8 source_port[0x10]; 584 585 u8 outer_second_prio[0x3]; 586 u8 outer_second_cfi[0x1]; 587 u8 outer_second_vid[0xc]; 588 u8 inner_second_prio[0x3]; 589 u8 inner_second_cfi[0x1]; 590 u8 inner_second_vid[0xc]; 591 592 u8 outer_second_cvlan_tag[0x1]; 593 u8 inner_second_cvlan_tag[0x1]; 594 u8 outer_second_svlan_tag[0x1]; 595 u8 inner_second_svlan_tag[0x1]; 596 u8 reserved_at_64[0xc]; 597 u8 gre_protocol[0x10]; 598 599 union mlx5_ifc_gre_key_bits gre_key; 600 601 u8 vxlan_vni[0x18]; 602 u8 bth_opcode[0x8]; 603 604 u8 geneve_vni[0x18]; 605 u8 reserved_at_d8[0x6]; 606 u8 geneve_tlv_option_0_exist[0x1]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_at_e0[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_at_100[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_120[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_at_140[0x8]; 620 u8 bth_dst_qp[0x18]; 621 u8 reserved_at_160[0x20]; 622 u8 outer_esp_spi[0x20]; 623 u8 reserved_at_1a0[0x60]; 624 }; 625 626 struct mlx5_ifc_fte_match_mpls_bits { 627 u8 mpls_label[0x14]; 628 u8 mpls_exp[0x3]; 629 u8 mpls_s_bos[0x1]; 630 u8 mpls_ttl[0x8]; 631 }; 632 633 struct mlx5_ifc_fte_match_set_misc2_bits { 634 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 635 636 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 637 638 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 639 640 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 641 642 u8 metadata_reg_c_7[0x20]; 643 644 u8 metadata_reg_c_6[0x20]; 645 646 u8 metadata_reg_c_5[0x20]; 647 648 u8 metadata_reg_c_4[0x20]; 649 650 u8 metadata_reg_c_3[0x20]; 651 652 u8 metadata_reg_c_2[0x20]; 653 654 u8 metadata_reg_c_1[0x20]; 655 656 u8 metadata_reg_c_0[0x20]; 657 658 u8 metadata_reg_a[0x20]; 659 660 u8 reserved_at_1a0[0x8]; 661 662 u8 macsec_syndrome[0x8]; 663 u8 ipsec_syndrome[0x8]; 664 u8 reserved_at_1b8[0x8]; 665 666 u8 reserved_at_1c0[0x40]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc3_bits { 670 u8 inner_tcp_seq_num[0x20]; 671 672 u8 outer_tcp_seq_num[0x20]; 673 674 u8 inner_tcp_ack_num[0x20]; 675 676 u8 outer_tcp_ack_num[0x20]; 677 678 u8 reserved_at_80[0x8]; 679 u8 outer_vxlan_gpe_vni[0x18]; 680 681 u8 outer_vxlan_gpe_next_protocol[0x8]; 682 u8 outer_vxlan_gpe_flags[0x8]; 683 u8 reserved_at_b0[0x10]; 684 685 u8 icmp_header_data[0x20]; 686 687 u8 icmpv6_header_data[0x20]; 688 689 u8 icmp_type[0x8]; 690 u8 icmp_code[0x8]; 691 u8 icmpv6_type[0x8]; 692 u8 icmpv6_code[0x8]; 693 694 u8 geneve_tlv_option_0_data[0x20]; 695 696 u8 gtpu_teid[0x20]; 697 698 u8 gtpu_msg_type[0x8]; 699 u8 gtpu_msg_flags[0x8]; 700 u8 reserved_at_170[0x10]; 701 702 u8 gtpu_dw_2[0x20]; 703 704 u8 gtpu_first_ext_dw_0[0x20]; 705 706 u8 gtpu_dw_0[0x20]; 707 708 u8 reserved_at_1e0[0x20]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc4_bits { 712 u8 prog_sample_field_value_0[0x20]; 713 714 u8 prog_sample_field_id_0[0x20]; 715 716 u8 prog_sample_field_value_1[0x20]; 717 718 u8 prog_sample_field_id_1[0x20]; 719 720 u8 prog_sample_field_value_2[0x20]; 721 722 u8 prog_sample_field_id_2[0x20]; 723 724 u8 prog_sample_field_value_3[0x20]; 725 726 u8 prog_sample_field_id_3[0x20]; 727 728 u8 reserved_at_100[0x100]; 729 }; 730 731 struct mlx5_ifc_fte_match_set_misc5_bits { 732 u8 macsec_tag_0[0x20]; 733 734 u8 macsec_tag_1[0x20]; 735 736 u8 macsec_tag_2[0x20]; 737 738 u8 macsec_tag_3[0x20]; 739 740 u8 tunnel_header_0[0x20]; 741 742 u8 tunnel_header_1[0x20]; 743 744 u8 tunnel_header_2[0x20]; 745 746 u8 tunnel_header_3[0x20]; 747 748 u8 reserved_at_100[0x100]; 749 }; 750 751 struct mlx5_ifc_cmd_pas_bits { 752 u8 pa_h[0x20]; 753 754 u8 pa_l[0x14]; 755 u8 reserved_at_34[0xc]; 756 }; 757 758 struct mlx5_ifc_uint64_bits { 759 u8 hi[0x20]; 760 761 u8 lo[0x20]; 762 }; 763 764 enum { 765 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 766 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 767 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 768 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 769 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 770 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 771 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 772 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 773 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 774 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 775 }; 776 777 struct mlx5_ifc_ads_bits { 778 u8 fl[0x1]; 779 u8 free_ar[0x1]; 780 u8 reserved_at_2[0xe]; 781 u8 pkey_index[0x10]; 782 783 u8 reserved_at_20[0x8]; 784 u8 grh[0x1]; 785 u8 mlid[0x7]; 786 u8 rlid[0x10]; 787 788 u8 ack_timeout[0x5]; 789 u8 reserved_at_45[0x3]; 790 u8 src_addr_index[0x8]; 791 u8 reserved_at_50[0x4]; 792 u8 stat_rate[0x4]; 793 u8 hop_limit[0x8]; 794 795 u8 reserved_at_60[0x4]; 796 u8 tclass[0x8]; 797 u8 flow_label[0x14]; 798 799 u8 rgid_rip[16][0x8]; 800 801 u8 reserved_at_100[0x4]; 802 u8 f_dscp[0x1]; 803 u8 f_ecn[0x1]; 804 u8 reserved_at_106[0x1]; 805 u8 f_eth_prio[0x1]; 806 u8 ecn[0x2]; 807 u8 dscp[0x6]; 808 u8 udp_sport[0x10]; 809 810 u8 dei_cfi[0x1]; 811 u8 eth_prio[0x3]; 812 u8 sl[0x4]; 813 u8 vhca_port_num[0x8]; 814 u8 rmac_47_32[0x10]; 815 816 u8 rmac_31_0[0x20]; 817 }; 818 819 struct mlx5_ifc_flow_table_nic_cap_bits { 820 u8 nic_rx_multi_path_tirs[0x1]; 821 u8 nic_rx_multi_path_tirs_fts[0x1]; 822 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 823 u8 reserved_at_3[0x4]; 824 u8 sw_owner_reformat_supported[0x1]; 825 u8 reserved_at_8[0x18]; 826 827 u8 encap_general_header[0x1]; 828 u8 reserved_at_21[0xa]; 829 u8 log_max_packet_reformat_context[0x5]; 830 u8 reserved_at_30[0x6]; 831 u8 max_encap_header_size[0xa]; 832 u8 reserved_at_40[0x1c0]; 833 834 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 835 836 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 837 838 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 839 840 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 841 842 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 843 844 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 845 846 u8 reserved_at_e00[0x700]; 847 848 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 849 850 u8 reserved_at_1580[0x280]; 851 852 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 853 854 u8 reserved_at_1880[0x780]; 855 856 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 857 858 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 859 860 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 861 862 u8 reserved_at_20c0[0x5f40]; 863 }; 864 865 struct mlx5_ifc_port_selection_cap_bits { 866 u8 reserved_at_0[0x10]; 867 u8 port_select_flow_table[0x1]; 868 u8 reserved_at_11[0x1]; 869 u8 port_select_flow_table_bypass[0x1]; 870 u8 reserved_at_13[0xd]; 871 872 u8 reserved_at_20[0x1e0]; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 875 876 u8 reserved_at_400[0x7c00]; 877 }; 878 879 enum { 880 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 881 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 882 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 883 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 884 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 885 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 886 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 887 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 888 }; 889 890 struct mlx5_ifc_flow_table_eswitch_cap_bits { 891 u8 fdb_to_vport_reg_c_id[0x8]; 892 u8 reserved_at_8[0x5]; 893 u8 fdb_uplink_hairpin[0x1]; 894 u8 fdb_multi_path_any_table_limit_regc[0x1]; 895 u8 reserved_at_f[0x3]; 896 u8 fdb_multi_path_any_table[0x1]; 897 u8 reserved_at_13[0x2]; 898 u8 fdb_modify_header_fwd_to_table[0x1]; 899 u8 fdb_ipv4_ttl_modify[0x1]; 900 u8 flow_source[0x1]; 901 u8 reserved_at_18[0x2]; 902 u8 multi_fdb_encap[0x1]; 903 u8 egress_acl_forward_to_vport[0x1]; 904 u8 fdb_multi_path_to_table[0x1]; 905 u8 reserved_at_1d[0x3]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 910 911 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 912 913 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 914 915 u8 reserved_at_800[0xC00]; 916 917 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 918 919 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 920 921 u8 reserved_at_1500[0x300]; 922 923 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 924 925 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 926 927 u8 sw_steering_uplink_icm_address_rx[0x40]; 928 929 u8 sw_steering_uplink_icm_address_tx[0x40]; 930 931 u8 reserved_at_1900[0x6700]; 932 }; 933 934 enum { 935 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 936 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 937 }; 938 939 struct mlx5_ifc_e_switch_cap_bits { 940 u8 vport_svlan_strip[0x1]; 941 u8 vport_cvlan_strip[0x1]; 942 u8 vport_svlan_insert[0x1]; 943 u8 vport_cvlan_insert_if_not_exist[0x1]; 944 u8 vport_cvlan_insert_overwrite[0x1]; 945 u8 reserved_at_5[0x1]; 946 u8 vport_cvlan_insert_always[0x1]; 947 u8 esw_shared_ingress_acl[0x1]; 948 u8 esw_uplink_ingress_acl[0x1]; 949 u8 root_ft_on_other_esw[0x1]; 950 u8 reserved_at_a[0xf]; 951 u8 esw_functions_changed[0x1]; 952 u8 reserved_at_1a[0x1]; 953 u8 ecpf_vport_exists[0x1]; 954 u8 counter_eswitch_affinity[0x1]; 955 u8 merged_eswitch[0x1]; 956 u8 nic_vport_node_guid_modify[0x1]; 957 u8 nic_vport_port_guid_modify[0x1]; 958 959 u8 vxlan_encap_decap[0x1]; 960 u8 nvgre_encap_decap[0x1]; 961 u8 reserved_at_22[0x1]; 962 u8 log_max_fdb_encap_uplink[0x5]; 963 u8 reserved_at_21[0x3]; 964 u8 log_max_packet_reformat_context[0x5]; 965 u8 reserved_2b[0x6]; 966 u8 max_encap_header_size[0xa]; 967 968 u8 reserved_at_40[0xb]; 969 u8 log_max_esw_sf[0x5]; 970 u8 esw_sf_base_id[0x10]; 971 972 u8 reserved_at_60[0x7a0]; 973 974 }; 975 976 struct mlx5_ifc_qos_cap_bits { 977 u8 packet_pacing[0x1]; 978 u8 esw_scheduling[0x1]; 979 u8 esw_bw_share[0x1]; 980 u8 esw_rate_limit[0x1]; 981 u8 reserved_at_4[0x1]; 982 u8 packet_pacing_burst_bound[0x1]; 983 u8 packet_pacing_typical_size[0x1]; 984 u8 reserved_at_7[0x1]; 985 u8 nic_sq_scheduling[0x1]; 986 u8 nic_bw_share[0x1]; 987 u8 nic_rate_limit[0x1]; 988 u8 packet_pacing_uid[0x1]; 989 u8 log_esw_max_sched_depth[0x4]; 990 u8 reserved_at_10[0x10]; 991 992 u8 reserved_at_20[0xb]; 993 u8 log_max_qos_nic_queue_group[0x5]; 994 u8 reserved_at_30[0x10]; 995 996 u8 packet_pacing_max_rate[0x20]; 997 998 u8 packet_pacing_min_rate[0x20]; 999 1000 u8 reserved_at_80[0x10]; 1001 u8 packet_pacing_rate_table_size[0x10]; 1002 1003 u8 esw_element_type[0x10]; 1004 u8 esw_tsar_type[0x10]; 1005 1006 u8 reserved_at_c0[0x10]; 1007 u8 max_qos_para_vport[0x10]; 1008 1009 u8 max_tsar_bw_share[0x20]; 1010 1011 u8 reserved_at_100[0x20]; 1012 1013 u8 reserved_at_120[0x3]; 1014 u8 log_meter_aso_granularity[0x5]; 1015 u8 reserved_at_128[0x3]; 1016 u8 log_meter_aso_max_alloc[0x5]; 1017 u8 reserved_at_130[0x3]; 1018 u8 log_max_num_meter_aso[0x5]; 1019 u8 reserved_at_138[0x8]; 1020 1021 u8 reserved_at_140[0x6c0]; 1022 }; 1023 1024 struct mlx5_ifc_debug_cap_bits { 1025 u8 core_dump_general[0x1]; 1026 u8 core_dump_qp[0x1]; 1027 u8 reserved_at_2[0x7]; 1028 u8 resource_dump[0x1]; 1029 u8 reserved_at_a[0x16]; 1030 1031 u8 reserved_at_20[0x2]; 1032 u8 stall_detect[0x1]; 1033 u8 reserved_at_23[0x1d]; 1034 1035 u8 reserved_at_40[0x7c0]; 1036 }; 1037 1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1039 u8 csum_cap[0x1]; 1040 u8 vlan_cap[0x1]; 1041 u8 lro_cap[0x1]; 1042 u8 lro_psh_flag[0x1]; 1043 u8 lro_time_stamp[0x1]; 1044 u8 reserved_at_5[0x2]; 1045 u8 wqe_vlan_insert[0x1]; 1046 u8 self_lb_en_modifiable[0x1]; 1047 u8 reserved_at_9[0x2]; 1048 u8 max_lso_cap[0x5]; 1049 u8 multi_pkt_send_wqe[0x2]; 1050 u8 wqe_inline_mode[0x2]; 1051 u8 rss_ind_tbl_cap[0x4]; 1052 u8 reg_umr_sq[0x1]; 1053 u8 scatter_fcs[0x1]; 1054 u8 enhanced_multi_pkt_send_wqe[0x1]; 1055 u8 tunnel_lso_const_out_ip_id[0x1]; 1056 u8 tunnel_lro_gre[0x1]; 1057 u8 tunnel_lro_vxlan[0x1]; 1058 u8 tunnel_stateless_gre[0x1]; 1059 u8 tunnel_stateless_vxlan[0x1]; 1060 1061 u8 swp[0x1]; 1062 u8 swp_csum[0x1]; 1063 u8 swp_lso[0x1]; 1064 u8 cqe_checksum_full[0x1]; 1065 u8 tunnel_stateless_geneve_tx[0x1]; 1066 u8 tunnel_stateless_mpls_over_udp[0x1]; 1067 u8 tunnel_stateless_mpls_over_gre[0x1]; 1068 u8 tunnel_stateless_vxlan_gpe[0x1]; 1069 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1070 u8 tunnel_stateless_ip_over_ip[0x1]; 1071 u8 insert_trailer[0x1]; 1072 u8 reserved_at_2b[0x1]; 1073 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1074 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1075 u8 reserved_at_2e[0x2]; 1076 u8 max_vxlan_udp_ports[0x8]; 1077 u8 reserved_at_38[0x6]; 1078 u8 max_geneve_opt_len[0x1]; 1079 u8 tunnel_stateless_geneve_rx[0x1]; 1080 1081 u8 reserved_at_40[0x10]; 1082 u8 lro_min_mss_size[0x10]; 1083 1084 u8 reserved_at_60[0x120]; 1085 1086 u8 lro_timer_supported_periods[4][0x20]; 1087 1088 u8 reserved_at_200[0x600]; 1089 }; 1090 1091 enum { 1092 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1093 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1094 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1095 }; 1096 1097 struct mlx5_ifc_roce_cap_bits { 1098 u8 roce_apm[0x1]; 1099 u8 reserved_at_1[0x3]; 1100 u8 sw_r_roce_src_udp_port[0x1]; 1101 u8 fl_rc_qp_when_roce_disabled[0x1]; 1102 u8 fl_rc_qp_when_roce_enabled[0x1]; 1103 u8 reserved_at_7[0x1]; 1104 u8 qp_ooo_transmit_default[0x1]; 1105 u8 reserved_at_9[0x15]; 1106 u8 qp_ts_format[0x2]; 1107 1108 u8 reserved_at_20[0x60]; 1109 1110 u8 reserved_at_80[0xc]; 1111 u8 l3_type[0x4]; 1112 u8 reserved_at_90[0x8]; 1113 u8 roce_version[0x8]; 1114 1115 u8 reserved_at_a0[0x10]; 1116 u8 r_roce_dest_udp_port[0x10]; 1117 1118 u8 r_roce_max_src_udp_port[0x10]; 1119 u8 r_roce_min_src_udp_port[0x10]; 1120 1121 u8 reserved_at_e0[0x10]; 1122 u8 roce_address_table_size[0x10]; 1123 1124 u8 reserved_at_100[0x700]; 1125 }; 1126 1127 struct mlx5_ifc_sync_steering_in_bits { 1128 u8 opcode[0x10]; 1129 u8 uid[0x10]; 1130 1131 u8 reserved_at_20[0x10]; 1132 u8 op_mod[0x10]; 1133 1134 u8 reserved_at_40[0xc0]; 1135 }; 1136 1137 struct mlx5_ifc_sync_steering_out_bits { 1138 u8 status[0x8]; 1139 u8 reserved_at_8[0x18]; 1140 1141 u8 syndrome[0x20]; 1142 1143 u8 reserved_at_40[0x40]; 1144 }; 1145 1146 struct mlx5_ifc_sync_crypto_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0x20]; 1154 1155 u8 reserved_at_60[0x10]; 1156 u8 crypto_type[0x10]; 1157 1158 u8 reserved_at_80[0x80]; 1159 }; 1160 1161 struct mlx5_ifc_sync_crypto_out_bits { 1162 u8 status[0x8]; 1163 u8 reserved_at_8[0x18]; 1164 1165 u8 syndrome[0x20]; 1166 1167 u8 reserved_at_40[0x40]; 1168 }; 1169 1170 struct mlx5_ifc_device_mem_cap_bits { 1171 u8 memic[0x1]; 1172 u8 reserved_at_1[0x1f]; 1173 1174 u8 reserved_at_20[0xb]; 1175 u8 log_min_memic_alloc_size[0x5]; 1176 u8 reserved_at_30[0x8]; 1177 u8 log_max_memic_addr_alignment[0x8]; 1178 1179 u8 memic_bar_start_addr[0x40]; 1180 1181 u8 memic_bar_size[0x20]; 1182 1183 u8 max_memic_size[0x20]; 1184 1185 u8 steering_sw_icm_start_address[0x40]; 1186 1187 u8 reserved_at_100[0x8]; 1188 u8 log_header_modify_sw_icm_size[0x8]; 1189 u8 reserved_at_110[0x2]; 1190 u8 log_sw_icm_alloc_granularity[0x6]; 1191 u8 log_steering_sw_icm_size[0x8]; 1192 1193 u8 reserved_at_120[0x18]; 1194 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1195 1196 u8 header_modify_sw_icm_start_address[0x40]; 1197 1198 u8 reserved_at_180[0x40]; 1199 1200 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1201 1202 u8 memic_operations[0x20]; 1203 1204 u8 reserved_at_220[0x5e0]; 1205 }; 1206 1207 struct mlx5_ifc_device_event_cap_bits { 1208 u8 user_affiliated_events[4][0x40]; 1209 1210 u8 user_unaffiliated_events[4][0x40]; 1211 }; 1212 1213 struct mlx5_ifc_virtio_emulation_cap_bits { 1214 u8 desc_tunnel_offload_type[0x1]; 1215 u8 eth_frame_offload_type[0x1]; 1216 u8 virtio_version_1_0[0x1]; 1217 u8 device_features_bits_mask[0xd]; 1218 u8 event_mode[0x8]; 1219 u8 virtio_queue_type[0x8]; 1220 1221 u8 max_tunnel_desc[0x10]; 1222 u8 reserved_at_30[0x3]; 1223 u8 log_doorbell_stride[0x5]; 1224 u8 reserved_at_38[0x3]; 1225 u8 log_doorbell_bar_size[0x5]; 1226 1227 u8 doorbell_bar_offset[0x40]; 1228 1229 u8 max_emulated_devices[0x8]; 1230 u8 max_num_virtio_queues[0x18]; 1231 1232 u8 reserved_at_a0[0x60]; 1233 1234 u8 umem_1_buffer_param_a[0x20]; 1235 1236 u8 umem_1_buffer_param_b[0x20]; 1237 1238 u8 umem_2_buffer_param_a[0x20]; 1239 1240 u8 umem_2_buffer_param_b[0x20]; 1241 1242 u8 umem_3_buffer_param_a[0x20]; 1243 1244 u8 umem_3_buffer_param_b[0x20]; 1245 1246 u8 reserved_at_1c0[0x640]; 1247 }; 1248 1249 enum { 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1257 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1258 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1259 }; 1260 1261 enum { 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1271 }; 1272 1273 struct mlx5_ifc_atomic_caps_bits { 1274 u8 reserved_at_0[0x40]; 1275 1276 u8 atomic_req_8B_endianness_mode[0x2]; 1277 u8 reserved_at_42[0x4]; 1278 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1279 1280 u8 reserved_at_47[0x19]; 1281 1282 u8 reserved_at_60[0x20]; 1283 1284 u8 reserved_at_80[0x10]; 1285 u8 atomic_operations[0x10]; 1286 1287 u8 reserved_at_a0[0x10]; 1288 u8 atomic_size_qp[0x10]; 1289 1290 u8 reserved_at_c0[0x10]; 1291 u8 atomic_size_dc[0x10]; 1292 1293 u8 reserved_at_e0[0x720]; 1294 }; 1295 1296 struct mlx5_ifc_odp_cap_bits { 1297 u8 reserved_at_0[0x40]; 1298 1299 u8 sig[0x1]; 1300 u8 reserved_at_41[0x1f]; 1301 1302 u8 reserved_at_60[0x20]; 1303 1304 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1305 1306 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1307 1308 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1309 1310 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1311 1312 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1313 1314 u8 reserved_at_120[0x6E0]; 1315 }; 1316 1317 struct mlx5_ifc_tls_cap_bits { 1318 u8 tls_1_2_aes_gcm_128[0x1]; 1319 u8 tls_1_3_aes_gcm_128[0x1]; 1320 u8 tls_1_2_aes_gcm_256[0x1]; 1321 u8 tls_1_3_aes_gcm_256[0x1]; 1322 u8 reserved_at_4[0x1c]; 1323 1324 u8 reserved_at_20[0x7e0]; 1325 }; 1326 1327 struct mlx5_ifc_ipsec_cap_bits { 1328 u8 ipsec_full_offload[0x1]; 1329 u8 ipsec_crypto_offload[0x1]; 1330 u8 ipsec_esn[0x1]; 1331 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1332 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1333 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1334 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1335 u8 reserved_at_7[0x4]; 1336 u8 log_max_ipsec_offload[0x5]; 1337 u8 reserved_at_10[0x10]; 1338 1339 u8 min_log_ipsec_full_replay_window[0x8]; 1340 u8 max_log_ipsec_full_replay_window[0x8]; 1341 u8 reserved_at_30[0x7d0]; 1342 }; 1343 1344 struct mlx5_ifc_macsec_cap_bits { 1345 u8 macsec_epn[0x1]; 1346 u8 reserved_at_1[0x2]; 1347 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1348 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1349 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1350 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1351 u8 reserved_at_7[0x4]; 1352 u8 log_max_macsec_offload[0x5]; 1353 u8 reserved_at_10[0x10]; 1354 1355 u8 min_log_macsec_full_replay_window[0x8]; 1356 u8 max_log_macsec_full_replay_window[0x8]; 1357 u8 reserved_at_30[0x10]; 1358 1359 u8 reserved_at_40[0x7c0]; 1360 }; 1361 1362 enum { 1363 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1364 MLX5_WQ_TYPE_CYCLIC = 0x1, 1365 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1366 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1367 }; 1368 1369 enum { 1370 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1371 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1372 }; 1373 1374 enum { 1375 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1376 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1377 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1378 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1379 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1380 }; 1381 1382 enum { 1383 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1384 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1385 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1386 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1387 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1388 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1389 }; 1390 1391 enum { 1392 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1393 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1394 }; 1395 1396 enum { 1397 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1398 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1399 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1400 }; 1401 1402 enum { 1403 MLX5_CAP_PORT_TYPE_IB = 0x0, 1404 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1405 }; 1406 1407 enum { 1408 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1409 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1410 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1411 }; 1412 1413 enum { 1414 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1415 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1416 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1417 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1418 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1419 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1420 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1421 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1422 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1423 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1424 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1425 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1426 }; 1427 1428 enum { 1429 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1430 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1431 }; 1432 1433 #define MLX5_FC_BULK_SIZE_FACTOR 128 1434 1435 enum mlx5_fc_bulk_alloc_bitmask { 1436 MLX5_FC_BULK_128 = (1 << 0), 1437 MLX5_FC_BULK_256 = (1 << 1), 1438 MLX5_FC_BULK_512 = (1 << 2), 1439 MLX5_FC_BULK_1024 = (1 << 3), 1440 MLX5_FC_BULK_2048 = (1 << 4), 1441 MLX5_FC_BULK_4096 = (1 << 5), 1442 MLX5_FC_BULK_8192 = (1 << 6), 1443 MLX5_FC_BULK_16384 = (1 << 7), 1444 }; 1445 1446 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1447 1448 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1449 1450 enum { 1451 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1452 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1453 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1454 }; 1455 1456 struct mlx5_ifc_cmd_hca_cap_bits { 1457 u8 reserved_at_0[0x10]; 1458 u8 shared_object_to_user_object_allowed[0x1]; 1459 u8 reserved_at_13[0xe]; 1460 u8 vhca_resource_manager[0x1]; 1461 1462 u8 hca_cap_2[0x1]; 1463 u8 create_lag_when_not_master_up[0x1]; 1464 u8 dtor[0x1]; 1465 u8 event_on_vhca_state_teardown_request[0x1]; 1466 u8 event_on_vhca_state_in_use[0x1]; 1467 u8 event_on_vhca_state_active[0x1]; 1468 u8 event_on_vhca_state_allocated[0x1]; 1469 u8 event_on_vhca_state_invalid[0x1]; 1470 u8 reserved_at_28[0x8]; 1471 u8 vhca_id[0x10]; 1472 1473 u8 reserved_at_40[0x40]; 1474 1475 u8 log_max_srq_sz[0x8]; 1476 u8 log_max_qp_sz[0x8]; 1477 u8 event_cap[0x1]; 1478 u8 reserved_at_91[0x2]; 1479 u8 isolate_vl_tc_new[0x1]; 1480 u8 reserved_at_94[0x4]; 1481 u8 prio_tag_required[0x1]; 1482 u8 reserved_at_99[0x2]; 1483 u8 log_max_qp[0x5]; 1484 1485 u8 reserved_at_a0[0x3]; 1486 u8 ece_support[0x1]; 1487 u8 reserved_at_a4[0x5]; 1488 u8 reg_c_preserve[0x1]; 1489 u8 reserved_at_aa[0x1]; 1490 u8 log_max_srq[0x5]; 1491 u8 reserved_at_b0[0x1]; 1492 u8 uplink_follow[0x1]; 1493 u8 ts_cqe_to_dest_cqn[0x1]; 1494 u8 reserved_at_b3[0x6]; 1495 u8 go_back_n[0x1]; 1496 u8 shampo[0x1]; 1497 u8 reserved_at_bb[0x5]; 1498 1499 u8 max_sgl_for_optimized_performance[0x8]; 1500 u8 log_max_cq_sz[0x8]; 1501 u8 relaxed_ordering_write_umr[0x1]; 1502 u8 relaxed_ordering_read_umr[0x1]; 1503 u8 reserved_at_d2[0x7]; 1504 u8 virtio_net_device_emualtion_manager[0x1]; 1505 u8 virtio_blk_device_emualtion_manager[0x1]; 1506 u8 log_max_cq[0x5]; 1507 1508 u8 log_max_eq_sz[0x8]; 1509 u8 relaxed_ordering_write[0x1]; 1510 u8 relaxed_ordering_read_pci_enabled[0x1]; 1511 u8 log_max_mkey[0x6]; 1512 u8 reserved_at_f0[0x6]; 1513 u8 terminate_scatter_list_mkey[0x1]; 1514 u8 repeated_mkey[0x1]; 1515 u8 dump_fill_mkey[0x1]; 1516 u8 reserved_at_f9[0x2]; 1517 u8 fast_teardown[0x1]; 1518 u8 log_max_eq[0x4]; 1519 1520 u8 max_indirection[0x8]; 1521 u8 fixed_buffer_size[0x1]; 1522 u8 log_max_mrw_sz[0x7]; 1523 u8 force_teardown[0x1]; 1524 u8 reserved_at_111[0x1]; 1525 u8 log_max_bsf_list_size[0x6]; 1526 u8 umr_extended_translation_offset[0x1]; 1527 u8 null_mkey[0x1]; 1528 u8 log_max_klm_list_size[0x6]; 1529 1530 u8 reserved_at_120[0x2]; 1531 u8 qpc_extension[0x1]; 1532 u8 reserved_at_123[0x7]; 1533 u8 log_max_ra_req_dc[0x6]; 1534 u8 reserved_at_130[0x2]; 1535 u8 eth_wqe_too_small[0x1]; 1536 u8 reserved_at_133[0x6]; 1537 u8 vnic_env_cq_overrun[0x1]; 1538 u8 log_max_ra_res_dc[0x6]; 1539 1540 u8 reserved_at_140[0x5]; 1541 u8 release_all_pages[0x1]; 1542 u8 must_not_use[0x1]; 1543 u8 reserved_at_147[0x2]; 1544 u8 roce_accl[0x1]; 1545 u8 log_max_ra_req_qp[0x6]; 1546 u8 reserved_at_150[0xa]; 1547 u8 log_max_ra_res_qp[0x6]; 1548 1549 u8 end_pad[0x1]; 1550 u8 cc_query_allowed[0x1]; 1551 u8 cc_modify_allowed[0x1]; 1552 u8 start_pad[0x1]; 1553 u8 cache_line_128byte[0x1]; 1554 u8 reserved_at_165[0x4]; 1555 u8 rts2rts_qp_counters_set_id[0x1]; 1556 u8 reserved_at_16a[0x2]; 1557 u8 vnic_env_int_rq_oob[0x1]; 1558 u8 sbcam_reg[0x1]; 1559 u8 reserved_at_16e[0x1]; 1560 u8 qcam_reg[0x1]; 1561 u8 gid_table_size[0x10]; 1562 1563 u8 out_of_seq_cnt[0x1]; 1564 u8 vport_counters[0x1]; 1565 u8 retransmission_q_counters[0x1]; 1566 u8 debug[0x1]; 1567 u8 modify_rq_counter_set_id[0x1]; 1568 u8 rq_delay_drop[0x1]; 1569 u8 max_qp_cnt[0xa]; 1570 u8 pkey_table_size[0x10]; 1571 1572 u8 vport_group_manager[0x1]; 1573 u8 vhca_group_manager[0x1]; 1574 u8 ib_virt[0x1]; 1575 u8 eth_virt[0x1]; 1576 u8 vnic_env_queue_counters[0x1]; 1577 u8 ets[0x1]; 1578 u8 nic_flow_table[0x1]; 1579 u8 eswitch_manager[0x1]; 1580 u8 device_memory[0x1]; 1581 u8 mcam_reg[0x1]; 1582 u8 pcam_reg[0x1]; 1583 u8 local_ca_ack_delay[0x5]; 1584 u8 port_module_event[0x1]; 1585 u8 enhanced_error_q_counters[0x1]; 1586 u8 ports_check[0x1]; 1587 u8 reserved_at_1b3[0x1]; 1588 u8 disable_link_up[0x1]; 1589 u8 beacon_led[0x1]; 1590 u8 port_type[0x2]; 1591 u8 num_ports[0x8]; 1592 1593 u8 reserved_at_1c0[0x1]; 1594 u8 pps[0x1]; 1595 u8 pps_modify[0x1]; 1596 u8 log_max_msg[0x5]; 1597 u8 reserved_at_1c8[0x4]; 1598 u8 max_tc[0x4]; 1599 u8 temp_warn_event[0x1]; 1600 u8 dcbx[0x1]; 1601 u8 general_notification_event[0x1]; 1602 u8 reserved_at_1d3[0x2]; 1603 u8 fpga[0x1]; 1604 u8 rol_s[0x1]; 1605 u8 rol_g[0x1]; 1606 u8 reserved_at_1d8[0x1]; 1607 u8 wol_s[0x1]; 1608 u8 wol_g[0x1]; 1609 u8 wol_a[0x1]; 1610 u8 wol_b[0x1]; 1611 u8 wol_m[0x1]; 1612 u8 wol_u[0x1]; 1613 u8 wol_p[0x1]; 1614 1615 u8 stat_rate_support[0x10]; 1616 u8 reserved_at_1f0[0x1]; 1617 u8 pci_sync_for_fw_update_event[0x1]; 1618 u8 reserved_at_1f2[0x6]; 1619 u8 init2_lag_tx_port_affinity[0x1]; 1620 u8 reserved_at_1fa[0x3]; 1621 u8 cqe_version[0x4]; 1622 1623 u8 compact_address_vector[0x1]; 1624 u8 striding_rq[0x1]; 1625 u8 reserved_at_202[0x1]; 1626 u8 ipoib_enhanced_offloads[0x1]; 1627 u8 ipoib_basic_offloads[0x1]; 1628 u8 reserved_at_205[0x1]; 1629 u8 repeated_block_disabled[0x1]; 1630 u8 umr_modify_entity_size_disabled[0x1]; 1631 u8 umr_modify_atomic_disabled[0x1]; 1632 u8 umr_indirect_mkey_disabled[0x1]; 1633 u8 umr_fence[0x2]; 1634 u8 dc_req_scat_data_cqe[0x1]; 1635 u8 reserved_at_20d[0x2]; 1636 u8 drain_sigerr[0x1]; 1637 u8 cmdif_checksum[0x2]; 1638 u8 sigerr_cqe[0x1]; 1639 u8 reserved_at_213[0x1]; 1640 u8 wq_signature[0x1]; 1641 u8 sctr_data_cqe[0x1]; 1642 u8 reserved_at_216[0x1]; 1643 u8 sho[0x1]; 1644 u8 tph[0x1]; 1645 u8 rf[0x1]; 1646 u8 dct[0x1]; 1647 u8 qos[0x1]; 1648 u8 eth_net_offloads[0x1]; 1649 u8 roce[0x1]; 1650 u8 atomic[0x1]; 1651 u8 reserved_at_21f[0x1]; 1652 1653 u8 cq_oi[0x1]; 1654 u8 cq_resize[0x1]; 1655 u8 cq_moderation[0x1]; 1656 u8 reserved_at_223[0x3]; 1657 u8 cq_eq_remap[0x1]; 1658 u8 pg[0x1]; 1659 u8 block_lb_mc[0x1]; 1660 u8 reserved_at_229[0x1]; 1661 u8 scqe_break_moderation[0x1]; 1662 u8 cq_period_start_from_cqe[0x1]; 1663 u8 cd[0x1]; 1664 u8 reserved_at_22d[0x1]; 1665 u8 apm[0x1]; 1666 u8 vector_calc[0x1]; 1667 u8 umr_ptr_rlky[0x1]; 1668 u8 imaicl[0x1]; 1669 u8 qp_packet_based[0x1]; 1670 u8 reserved_at_233[0x3]; 1671 u8 qkv[0x1]; 1672 u8 pkv[0x1]; 1673 u8 set_deth_sqpn[0x1]; 1674 u8 reserved_at_239[0x3]; 1675 u8 xrc[0x1]; 1676 u8 ud[0x1]; 1677 u8 uc[0x1]; 1678 u8 rc[0x1]; 1679 1680 u8 uar_4k[0x1]; 1681 u8 reserved_at_241[0x7]; 1682 u8 fl_rc_qp_when_roce_disabled[0x1]; 1683 u8 regexp_params[0x1]; 1684 u8 uar_sz[0x6]; 1685 u8 port_selection_cap[0x1]; 1686 u8 reserved_at_251[0x1]; 1687 u8 umem_uid_0[0x1]; 1688 u8 reserved_at_253[0x5]; 1689 u8 log_pg_sz[0x8]; 1690 1691 u8 bf[0x1]; 1692 u8 driver_version[0x1]; 1693 u8 pad_tx_eth_packet[0x1]; 1694 u8 reserved_at_263[0x3]; 1695 u8 mkey_by_name[0x1]; 1696 u8 reserved_at_267[0x4]; 1697 1698 u8 log_bf_reg_size[0x5]; 1699 1700 u8 reserved_at_270[0x3]; 1701 u8 qp_error_syndrome[0x1]; 1702 u8 reserved_at_274[0x2]; 1703 u8 lag_dct[0x2]; 1704 u8 lag_tx_port_affinity[0x1]; 1705 u8 lag_native_fdb_selection[0x1]; 1706 u8 reserved_at_27a[0x1]; 1707 u8 lag_master[0x1]; 1708 u8 num_lag_ports[0x4]; 1709 1710 u8 reserved_at_280[0x10]; 1711 u8 max_wqe_sz_sq[0x10]; 1712 1713 u8 reserved_at_2a0[0x10]; 1714 u8 max_wqe_sz_rq[0x10]; 1715 1716 u8 max_flow_counter_31_16[0x10]; 1717 u8 max_wqe_sz_sq_dc[0x10]; 1718 1719 u8 reserved_at_2e0[0x7]; 1720 u8 max_qp_mcg[0x19]; 1721 1722 u8 reserved_at_300[0x10]; 1723 u8 flow_counter_bulk_alloc[0x8]; 1724 u8 log_max_mcg[0x8]; 1725 1726 u8 reserved_at_320[0x3]; 1727 u8 log_max_transport_domain[0x5]; 1728 u8 reserved_at_328[0x2]; 1729 u8 relaxed_ordering_read[0x1]; 1730 u8 log_max_pd[0x5]; 1731 u8 reserved_at_330[0x6]; 1732 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1733 u8 vnic_env_cnt_steering_fail[0x1]; 1734 u8 vport_counter_local_loopback[0x1]; 1735 u8 q_counter_aggregation[0x1]; 1736 u8 q_counter_other_vport[0x1]; 1737 u8 log_max_xrcd[0x5]; 1738 1739 u8 nic_receive_steering_discard[0x1]; 1740 u8 receive_discard_vport_down[0x1]; 1741 u8 transmit_discard_vport_down[0x1]; 1742 u8 eq_overrun_count[0x1]; 1743 u8 reserved_at_344[0x1]; 1744 u8 invalid_command_count[0x1]; 1745 u8 quota_exceeded_count[0x1]; 1746 u8 reserved_at_347[0x1]; 1747 u8 log_max_flow_counter_bulk[0x8]; 1748 u8 max_flow_counter_15_0[0x10]; 1749 1750 1751 u8 reserved_at_360[0x3]; 1752 u8 log_max_rq[0x5]; 1753 u8 reserved_at_368[0x3]; 1754 u8 log_max_sq[0x5]; 1755 u8 reserved_at_370[0x3]; 1756 u8 log_max_tir[0x5]; 1757 u8 reserved_at_378[0x3]; 1758 u8 log_max_tis[0x5]; 1759 1760 u8 basic_cyclic_rcv_wqe[0x1]; 1761 u8 reserved_at_381[0x2]; 1762 u8 log_max_rmp[0x5]; 1763 u8 reserved_at_388[0x3]; 1764 u8 log_max_rqt[0x5]; 1765 u8 reserved_at_390[0x3]; 1766 u8 log_max_rqt_size[0x5]; 1767 u8 reserved_at_398[0x3]; 1768 u8 log_max_tis_per_sq[0x5]; 1769 1770 u8 ext_stride_num_range[0x1]; 1771 u8 roce_rw_supported[0x1]; 1772 u8 log_max_current_uc_list_wr_supported[0x1]; 1773 u8 log_max_stride_sz_rq[0x5]; 1774 u8 reserved_at_3a8[0x3]; 1775 u8 log_min_stride_sz_rq[0x5]; 1776 u8 reserved_at_3b0[0x3]; 1777 u8 log_max_stride_sz_sq[0x5]; 1778 u8 reserved_at_3b8[0x3]; 1779 u8 log_min_stride_sz_sq[0x5]; 1780 1781 u8 hairpin[0x1]; 1782 u8 reserved_at_3c1[0x2]; 1783 u8 log_max_hairpin_queues[0x5]; 1784 u8 reserved_at_3c8[0x3]; 1785 u8 log_max_hairpin_wq_data_sz[0x5]; 1786 u8 reserved_at_3d0[0x3]; 1787 u8 log_max_hairpin_num_packets[0x5]; 1788 u8 reserved_at_3d8[0x3]; 1789 u8 log_max_wq_sz[0x5]; 1790 1791 u8 nic_vport_change_event[0x1]; 1792 u8 disable_local_lb_uc[0x1]; 1793 u8 disable_local_lb_mc[0x1]; 1794 u8 log_min_hairpin_wq_data_sz[0x5]; 1795 u8 reserved_at_3e8[0x2]; 1796 u8 vhca_state[0x1]; 1797 u8 log_max_vlan_list[0x5]; 1798 u8 reserved_at_3f0[0x3]; 1799 u8 log_max_current_mc_list[0x5]; 1800 u8 reserved_at_3f8[0x3]; 1801 u8 log_max_current_uc_list[0x5]; 1802 1803 u8 general_obj_types[0x40]; 1804 1805 u8 sq_ts_format[0x2]; 1806 u8 rq_ts_format[0x2]; 1807 u8 steering_format_version[0x4]; 1808 u8 create_qp_start_hint[0x18]; 1809 1810 u8 reserved_at_460[0x1]; 1811 u8 ats[0x1]; 1812 u8 reserved_at_462[0x1]; 1813 u8 log_max_uctx[0x5]; 1814 u8 reserved_at_468[0x1]; 1815 u8 crypto[0x1]; 1816 u8 ipsec_offload[0x1]; 1817 u8 log_max_umem[0x5]; 1818 u8 max_num_eqs[0x10]; 1819 1820 u8 reserved_at_480[0x1]; 1821 u8 tls_tx[0x1]; 1822 u8 tls_rx[0x1]; 1823 u8 log_max_l2_table[0x5]; 1824 u8 reserved_at_488[0x8]; 1825 u8 log_uar_page_sz[0x10]; 1826 1827 u8 reserved_at_4a0[0x20]; 1828 u8 device_frequency_mhz[0x20]; 1829 u8 device_frequency_khz[0x20]; 1830 1831 u8 reserved_at_500[0x20]; 1832 u8 num_of_uars_per_page[0x20]; 1833 1834 u8 flex_parser_protocols[0x20]; 1835 1836 u8 max_geneve_tlv_options[0x8]; 1837 u8 reserved_at_568[0x3]; 1838 u8 max_geneve_tlv_option_data_len[0x5]; 1839 u8 reserved_at_570[0x9]; 1840 u8 adv_virtualization[0x1]; 1841 u8 reserved_at_57a[0x6]; 1842 1843 u8 reserved_at_580[0xb]; 1844 u8 log_max_dci_stream_channels[0x5]; 1845 u8 reserved_at_590[0x3]; 1846 u8 log_max_dci_errored_streams[0x5]; 1847 u8 reserved_at_598[0x8]; 1848 1849 u8 reserved_at_5a0[0x10]; 1850 u8 enhanced_cqe_compression[0x1]; 1851 u8 reserved_at_5b1[0x2]; 1852 u8 log_max_dek[0x5]; 1853 u8 reserved_at_5b8[0x4]; 1854 u8 mini_cqe_resp_stride_index[0x1]; 1855 u8 cqe_128_always[0x1]; 1856 u8 cqe_compression_128[0x1]; 1857 u8 cqe_compression[0x1]; 1858 1859 u8 cqe_compression_timeout[0x10]; 1860 u8 cqe_compression_max_num[0x10]; 1861 1862 u8 reserved_at_5e0[0x8]; 1863 u8 flex_parser_id_gtpu_dw_0[0x4]; 1864 u8 reserved_at_5ec[0x4]; 1865 u8 tag_matching[0x1]; 1866 u8 rndv_offload_rc[0x1]; 1867 u8 rndv_offload_dc[0x1]; 1868 u8 log_tag_matching_list_sz[0x5]; 1869 u8 reserved_at_5f8[0x3]; 1870 u8 log_max_xrq[0x5]; 1871 1872 u8 affiliate_nic_vport_criteria[0x8]; 1873 u8 native_port_num[0x8]; 1874 u8 num_vhca_ports[0x8]; 1875 u8 flex_parser_id_gtpu_teid[0x4]; 1876 u8 reserved_at_61c[0x2]; 1877 u8 sw_owner_id[0x1]; 1878 u8 reserved_at_61f[0x1]; 1879 1880 u8 max_num_of_monitor_counters[0x10]; 1881 u8 num_ppcnt_monitor_counters[0x10]; 1882 1883 u8 max_num_sf[0x10]; 1884 u8 num_q_monitor_counters[0x10]; 1885 1886 u8 reserved_at_660[0x20]; 1887 1888 u8 sf[0x1]; 1889 u8 sf_set_partition[0x1]; 1890 u8 reserved_at_682[0x1]; 1891 u8 log_max_sf[0x5]; 1892 u8 apu[0x1]; 1893 u8 reserved_at_689[0x4]; 1894 u8 migration[0x1]; 1895 u8 reserved_at_68e[0x2]; 1896 u8 log_min_sf_size[0x8]; 1897 u8 max_num_sf_partitions[0x8]; 1898 1899 u8 uctx_cap[0x20]; 1900 1901 u8 reserved_at_6c0[0x4]; 1902 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1903 u8 flex_parser_id_icmp_dw1[0x4]; 1904 u8 flex_parser_id_icmp_dw0[0x4]; 1905 u8 flex_parser_id_icmpv6_dw1[0x4]; 1906 u8 flex_parser_id_icmpv6_dw0[0x4]; 1907 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1908 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1909 1910 u8 max_num_match_definer[0x10]; 1911 u8 sf_base_id[0x10]; 1912 1913 u8 flex_parser_id_gtpu_dw_2[0x4]; 1914 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1915 u8 num_total_dynamic_vf_msix[0x18]; 1916 u8 reserved_at_720[0x14]; 1917 u8 dynamic_msix_table_size[0xc]; 1918 u8 reserved_at_740[0xc]; 1919 u8 min_dynamic_vf_msix_table_size[0x4]; 1920 u8 reserved_at_750[0x4]; 1921 u8 max_dynamic_vf_msix_table_size[0xc]; 1922 1923 u8 reserved_at_760[0x3]; 1924 u8 log_max_num_header_modify_argument[0x5]; 1925 u8 reserved_at_768[0x4]; 1926 u8 log_header_modify_argument_granularity[0x4]; 1927 u8 reserved_at_770[0x3]; 1928 u8 log_header_modify_argument_max_alloc[0x5]; 1929 u8 reserved_at_778[0x8]; 1930 1931 u8 vhca_tunnel_commands[0x40]; 1932 u8 match_definer_format_supported[0x40]; 1933 }; 1934 1935 struct mlx5_ifc_cmd_hca_cap_2_bits { 1936 u8 reserved_at_0[0x80]; 1937 1938 u8 migratable[0x1]; 1939 u8 reserved_at_81[0x1f]; 1940 1941 u8 max_reformat_insert_size[0x8]; 1942 u8 max_reformat_insert_offset[0x8]; 1943 u8 max_reformat_remove_size[0x8]; 1944 u8 max_reformat_remove_offset[0x8]; 1945 1946 u8 reserved_at_c0[0x8]; 1947 u8 migration_multi_load[0x1]; 1948 u8 migration_tracking_state[0x1]; 1949 u8 reserved_at_ca[0x16]; 1950 1951 u8 reserved_at_e0[0xc0]; 1952 1953 u8 flow_table_type_2_type[0x8]; 1954 u8 reserved_at_1a8[0x3]; 1955 u8 log_min_mkey_entity_size[0x5]; 1956 u8 reserved_at_1b0[0x10]; 1957 1958 u8 reserved_at_1c0[0x60]; 1959 1960 u8 reserved_at_220[0x1]; 1961 u8 sw_vhca_id_valid[0x1]; 1962 u8 sw_vhca_id[0xe]; 1963 u8 reserved_at_230[0x10]; 1964 1965 u8 reserved_at_240[0xb]; 1966 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1967 u8 reserved_at_250[0x10]; 1968 1969 u8 reserved_at_260[0x120]; 1970 u8 reserved_at_380[0x10]; 1971 u8 ec_vf_vport_base[0x10]; 1972 u8 reserved_at_3a0[0x460]; 1973 }; 1974 1975 enum mlx5_ifc_flow_destination_type { 1976 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1977 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1978 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1979 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1980 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1981 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1982 }; 1983 1984 enum mlx5_flow_table_miss_action { 1985 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1986 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1987 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1988 }; 1989 1990 struct mlx5_ifc_dest_format_struct_bits { 1991 u8 destination_type[0x8]; 1992 u8 destination_id[0x18]; 1993 1994 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1995 u8 packet_reformat[0x1]; 1996 u8 reserved_at_22[0x6]; 1997 u8 destination_table_type[0x8]; 1998 u8 destination_eswitch_owner_vhca_id[0x10]; 1999 }; 2000 2001 struct mlx5_ifc_flow_counter_list_bits { 2002 u8 flow_counter_id[0x20]; 2003 2004 u8 reserved_at_20[0x20]; 2005 }; 2006 2007 struct mlx5_ifc_extended_dest_format_bits { 2008 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2009 2010 u8 packet_reformat_id[0x20]; 2011 2012 u8 reserved_at_60[0x20]; 2013 }; 2014 2015 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2016 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2017 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2018 }; 2019 2020 struct mlx5_ifc_fte_match_param_bits { 2021 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2022 2023 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2024 2025 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2026 2027 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2028 2029 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2030 2031 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2032 2033 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2034 2035 u8 reserved_at_e00[0x200]; 2036 }; 2037 2038 enum { 2039 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2040 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2041 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2042 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2043 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2044 }; 2045 2046 struct mlx5_ifc_rx_hash_field_select_bits { 2047 u8 l3_prot_type[0x1]; 2048 u8 l4_prot_type[0x1]; 2049 u8 selected_fields[0x1e]; 2050 }; 2051 2052 enum { 2053 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2054 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2055 }; 2056 2057 enum { 2058 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2059 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2060 }; 2061 2062 struct mlx5_ifc_wq_bits { 2063 u8 wq_type[0x4]; 2064 u8 wq_signature[0x1]; 2065 u8 end_padding_mode[0x2]; 2066 u8 cd_slave[0x1]; 2067 u8 reserved_at_8[0x18]; 2068 2069 u8 hds_skip_first_sge[0x1]; 2070 u8 log2_hds_buf_size[0x3]; 2071 u8 reserved_at_24[0x7]; 2072 u8 page_offset[0x5]; 2073 u8 lwm[0x10]; 2074 2075 u8 reserved_at_40[0x8]; 2076 u8 pd[0x18]; 2077 2078 u8 reserved_at_60[0x8]; 2079 u8 uar_page[0x18]; 2080 2081 u8 dbr_addr[0x40]; 2082 2083 u8 hw_counter[0x20]; 2084 2085 u8 sw_counter[0x20]; 2086 2087 u8 reserved_at_100[0xc]; 2088 u8 log_wq_stride[0x4]; 2089 u8 reserved_at_110[0x3]; 2090 u8 log_wq_pg_sz[0x5]; 2091 u8 reserved_at_118[0x3]; 2092 u8 log_wq_sz[0x5]; 2093 2094 u8 dbr_umem_valid[0x1]; 2095 u8 wq_umem_valid[0x1]; 2096 u8 reserved_at_122[0x1]; 2097 u8 log_hairpin_num_packets[0x5]; 2098 u8 reserved_at_128[0x3]; 2099 u8 log_hairpin_data_sz[0x5]; 2100 2101 u8 reserved_at_130[0x4]; 2102 u8 log_wqe_num_of_strides[0x4]; 2103 u8 two_byte_shift_en[0x1]; 2104 u8 reserved_at_139[0x4]; 2105 u8 log_wqe_stride_size[0x3]; 2106 2107 u8 reserved_at_140[0x80]; 2108 2109 u8 headers_mkey[0x20]; 2110 2111 u8 shampo_enable[0x1]; 2112 u8 reserved_at_1e1[0x4]; 2113 u8 log_reservation_size[0x3]; 2114 u8 reserved_at_1e8[0x5]; 2115 u8 log_max_num_of_packets_per_reservation[0x3]; 2116 u8 reserved_at_1f0[0x6]; 2117 u8 log_headers_entry_size[0x2]; 2118 u8 reserved_at_1f8[0x4]; 2119 u8 log_headers_buffer_entry_num[0x4]; 2120 2121 u8 reserved_at_200[0x400]; 2122 2123 struct mlx5_ifc_cmd_pas_bits pas[]; 2124 }; 2125 2126 struct mlx5_ifc_rq_num_bits { 2127 u8 reserved_at_0[0x8]; 2128 u8 rq_num[0x18]; 2129 }; 2130 2131 struct mlx5_ifc_mac_address_layout_bits { 2132 u8 reserved_at_0[0x10]; 2133 u8 mac_addr_47_32[0x10]; 2134 2135 u8 mac_addr_31_0[0x20]; 2136 }; 2137 2138 struct mlx5_ifc_vlan_layout_bits { 2139 u8 reserved_at_0[0x14]; 2140 u8 vlan[0x0c]; 2141 2142 u8 reserved_at_20[0x20]; 2143 }; 2144 2145 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2146 u8 reserved_at_0[0xa0]; 2147 2148 u8 min_time_between_cnps[0x20]; 2149 2150 u8 reserved_at_c0[0x12]; 2151 u8 cnp_dscp[0x6]; 2152 u8 reserved_at_d8[0x4]; 2153 u8 cnp_prio_mode[0x1]; 2154 u8 cnp_802p_prio[0x3]; 2155 2156 u8 reserved_at_e0[0x720]; 2157 }; 2158 2159 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2160 u8 reserved_at_0[0x60]; 2161 2162 u8 reserved_at_60[0x4]; 2163 u8 clamp_tgt_rate[0x1]; 2164 u8 reserved_at_65[0x3]; 2165 u8 clamp_tgt_rate_after_time_inc[0x1]; 2166 u8 reserved_at_69[0x17]; 2167 2168 u8 reserved_at_80[0x20]; 2169 2170 u8 rpg_time_reset[0x20]; 2171 2172 u8 rpg_byte_reset[0x20]; 2173 2174 u8 rpg_threshold[0x20]; 2175 2176 u8 rpg_max_rate[0x20]; 2177 2178 u8 rpg_ai_rate[0x20]; 2179 2180 u8 rpg_hai_rate[0x20]; 2181 2182 u8 rpg_gd[0x20]; 2183 2184 u8 rpg_min_dec_fac[0x20]; 2185 2186 u8 rpg_min_rate[0x20]; 2187 2188 u8 reserved_at_1c0[0xe0]; 2189 2190 u8 rate_to_set_on_first_cnp[0x20]; 2191 2192 u8 dce_tcp_g[0x20]; 2193 2194 u8 dce_tcp_rtt[0x20]; 2195 2196 u8 rate_reduce_monitor_period[0x20]; 2197 2198 u8 reserved_at_320[0x20]; 2199 2200 u8 initial_alpha_value[0x20]; 2201 2202 u8 reserved_at_360[0x4a0]; 2203 }; 2204 2205 struct mlx5_ifc_cong_control_r_roce_general_bits { 2206 u8 reserved_at_0[0x80]; 2207 2208 u8 reserved_at_80[0x10]; 2209 u8 rtt_resp_dscp_valid[0x1]; 2210 u8 reserved_at_91[0x9]; 2211 u8 rtt_resp_dscp[0x6]; 2212 2213 u8 reserved_at_a0[0x760]; 2214 }; 2215 2216 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2217 u8 reserved_at_0[0x80]; 2218 2219 u8 rppp_max_rps[0x20]; 2220 2221 u8 rpg_time_reset[0x20]; 2222 2223 u8 rpg_byte_reset[0x20]; 2224 2225 u8 rpg_threshold[0x20]; 2226 2227 u8 rpg_max_rate[0x20]; 2228 2229 u8 rpg_ai_rate[0x20]; 2230 2231 u8 rpg_hai_rate[0x20]; 2232 2233 u8 rpg_gd[0x20]; 2234 2235 u8 rpg_min_dec_fac[0x20]; 2236 2237 u8 rpg_min_rate[0x20]; 2238 2239 u8 reserved_at_1c0[0x640]; 2240 }; 2241 2242 enum { 2243 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2244 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2245 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2246 }; 2247 2248 struct mlx5_ifc_resize_field_select_bits { 2249 u8 resize_field_select[0x20]; 2250 }; 2251 2252 struct mlx5_ifc_resource_dump_bits { 2253 u8 more_dump[0x1]; 2254 u8 inline_dump[0x1]; 2255 u8 reserved_at_2[0xa]; 2256 u8 seq_num[0x4]; 2257 u8 segment_type[0x10]; 2258 2259 u8 reserved_at_20[0x10]; 2260 u8 vhca_id[0x10]; 2261 2262 u8 index1[0x20]; 2263 2264 u8 index2[0x20]; 2265 2266 u8 num_of_obj1[0x10]; 2267 u8 num_of_obj2[0x10]; 2268 2269 u8 reserved_at_a0[0x20]; 2270 2271 u8 device_opaque[0x40]; 2272 2273 u8 mkey[0x20]; 2274 2275 u8 size[0x20]; 2276 2277 u8 address[0x40]; 2278 2279 u8 inline_data[52][0x20]; 2280 }; 2281 2282 struct mlx5_ifc_resource_dump_menu_record_bits { 2283 u8 reserved_at_0[0x4]; 2284 u8 num_of_obj2_supports_active[0x1]; 2285 u8 num_of_obj2_supports_all[0x1]; 2286 u8 must_have_num_of_obj2[0x1]; 2287 u8 support_num_of_obj2[0x1]; 2288 u8 num_of_obj1_supports_active[0x1]; 2289 u8 num_of_obj1_supports_all[0x1]; 2290 u8 must_have_num_of_obj1[0x1]; 2291 u8 support_num_of_obj1[0x1]; 2292 u8 must_have_index2[0x1]; 2293 u8 support_index2[0x1]; 2294 u8 must_have_index1[0x1]; 2295 u8 support_index1[0x1]; 2296 u8 segment_type[0x10]; 2297 2298 u8 segment_name[4][0x20]; 2299 2300 u8 index1_name[4][0x20]; 2301 2302 u8 index2_name[4][0x20]; 2303 }; 2304 2305 struct mlx5_ifc_resource_dump_segment_header_bits { 2306 u8 length_dw[0x10]; 2307 u8 segment_type[0x10]; 2308 }; 2309 2310 struct mlx5_ifc_resource_dump_command_segment_bits { 2311 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2312 2313 u8 segment_called[0x10]; 2314 u8 vhca_id[0x10]; 2315 2316 u8 index1[0x20]; 2317 2318 u8 index2[0x20]; 2319 2320 u8 num_of_obj1[0x10]; 2321 u8 num_of_obj2[0x10]; 2322 }; 2323 2324 struct mlx5_ifc_resource_dump_error_segment_bits { 2325 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2326 2327 u8 reserved_at_20[0x10]; 2328 u8 syndrome_id[0x10]; 2329 2330 u8 reserved_at_40[0x40]; 2331 2332 u8 error[8][0x20]; 2333 }; 2334 2335 struct mlx5_ifc_resource_dump_info_segment_bits { 2336 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2337 2338 u8 reserved_at_20[0x18]; 2339 u8 dump_version[0x8]; 2340 2341 u8 hw_version[0x20]; 2342 2343 u8 fw_version[0x20]; 2344 }; 2345 2346 struct mlx5_ifc_resource_dump_menu_segment_bits { 2347 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2348 2349 u8 reserved_at_20[0x10]; 2350 u8 num_of_records[0x10]; 2351 2352 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2353 }; 2354 2355 struct mlx5_ifc_resource_dump_resource_segment_bits { 2356 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2357 2358 u8 reserved_at_20[0x20]; 2359 2360 u8 index1[0x20]; 2361 2362 u8 index2[0x20]; 2363 2364 u8 payload[][0x20]; 2365 }; 2366 2367 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2368 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2369 }; 2370 2371 struct mlx5_ifc_menu_resource_dump_response_bits { 2372 struct mlx5_ifc_resource_dump_info_segment_bits info; 2373 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2374 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2375 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2376 }; 2377 2378 enum { 2379 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2380 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2381 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2382 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2383 }; 2384 2385 struct mlx5_ifc_modify_field_select_bits { 2386 u8 modify_field_select[0x20]; 2387 }; 2388 2389 struct mlx5_ifc_field_select_r_roce_np_bits { 2390 u8 field_select_r_roce_np[0x20]; 2391 }; 2392 2393 struct mlx5_ifc_field_select_r_roce_rp_bits { 2394 u8 field_select_r_roce_rp[0x20]; 2395 }; 2396 2397 enum { 2398 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2399 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2400 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2401 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2402 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2403 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2404 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2405 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2406 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2407 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2408 }; 2409 2410 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2411 u8 field_select_8021qaurp[0x20]; 2412 }; 2413 2414 struct mlx5_ifc_phys_layer_cntrs_bits { 2415 u8 time_since_last_clear_high[0x20]; 2416 2417 u8 time_since_last_clear_low[0x20]; 2418 2419 u8 symbol_errors_high[0x20]; 2420 2421 u8 symbol_errors_low[0x20]; 2422 2423 u8 sync_headers_errors_high[0x20]; 2424 2425 u8 sync_headers_errors_low[0x20]; 2426 2427 u8 edpl_bip_errors_lane0_high[0x20]; 2428 2429 u8 edpl_bip_errors_lane0_low[0x20]; 2430 2431 u8 edpl_bip_errors_lane1_high[0x20]; 2432 2433 u8 edpl_bip_errors_lane1_low[0x20]; 2434 2435 u8 edpl_bip_errors_lane2_high[0x20]; 2436 2437 u8 edpl_bip_errors_lane2_low[0x20]; 2438 2439 u8 edpl_bip_errors_lane3_high[0x20]; 2440 2441 u8 edpl_bip_errors_lane3_low[0x20]; 2442 2443 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2444 2445 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2446 2447 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2448 2449 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2450 2451 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2452 2453 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2454 2455 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2456 2457 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2458 2459 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2460 2461 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2462 2463 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2464 2465 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2466 2467 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2468 2469 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2470 2471 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2472 2473 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2474 2475 u8 rs_fec_corrected_blocks_high[0x20]; 2476 2477 u8 rs_fec_corrected_blocks_low[0x20]; 2478 2479 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2480 2481 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2482 2483 u8 rs_fec_no_errors_blocks_high[0x20]; 2484 2485 u8 rs_fec_no_errors_blocks_low[0x20]; 2486 2487 u8 rs_fec_single_error_blocks_high[0x20]; 2488 2489 u8 rs_fec_single_error_blocks_low[0x20]; 2490 2491 u8 rs_fec_corrected_symbols_total_high[0x20]; 2492 2493 u8 rs_fec_corrected_symbols_total_low[0x20]; 2494 2495 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2496 2497 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2498 2499 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2500 2501 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2502 2503 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2504 2505 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2506 2507 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2508 2509 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2510 2511 u8 link_down_events[0x20]; 2512 2513 u8 successful_recovery_events[0x20]; 2514 2515 u8 reserved_at_640[0x180]; 2516 }; 2517 2518 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2519 u8 time_since_last_clear_high[0x20]; 2520 2521 u8 time_since_last_clear_low[0x20]; 2522 2523 u8 phy_received_bits_high[0x20]; 2524 2525 u8 phy_received_bits_low[0x20]; 2526 2527 u8 phy_symbol_errors_high[0x20]; 2528 2529 u8 phy_symbol_errors_low[0x20]; 2530 2531 u8 phy_corrected_bits_high[0x20]; 2532 2533 u8 phy_corrected_bits_low[0x20]; 2534 2535 u8 phy_corrected_bits_lane0_high[0x20]; 2536 2537 u8 phy_corrected_bits_lane0_low[0x20]; 2538 2539 u8 phy_corrected_bits_lane1_high[0x20]; 2540 2541 u8 phy_corrected_bits_lane1_low[0x20]; 2542 2543 u8 phy_corrected_bits_lane2_high[0x20]; 2544 2545 u8 phy_corrected_bits_lane2_low[0x20]; 2546 2547 u8 phy_corrected_bits_lane3_high[0x20]; 2548 2549 u8 phy_corrected_bits_lane3_low[0x20]; 2550 2551 u8 reserved_at_200[0x5c0]; 2552 }; 2553 2554 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2555 u8 symbol_error_counter[0x10]; 2556 2557 u8 link_error_recovery_counter[0x8]; 2558 2559 u8 link_downed_counter[0x8]; 2560 2561 u8 port_rcv_errors[0x10]; 2562 2563 u8 port_rcv_remote_physical_errors[0x10]; 2564 2565 u8 port_rcv_switch_relay_errors[0x10]; 2566 2567 u8 port_xmit_discards[0x10]; 2568 2569 u8 port_xmit_constraint_errors[0x8]; 2570 2571 u8 port_rcv_constraint_errors[0x8]; 2572 2573 u8 reserved_at_70[0x8]; 2574 2575 u8 link_overrun_errors[0x8]; 2576 2577 u8 reserved_at_80[0x10]; 2578 2579 u8 vl_15_dropped[0x10]; 2580 2581 u8 reserved_at_a0[0x80]; 2582 2583 u8 port_xmit_wait[0x20]; 2584 }; 2585 2586 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2587 u8 transmit_queue_high[0x20]; 2588 2589 u8 transmit_queue_low[0x20]; 2590 2591 u8 no_buffer_discard_uc_high[0x20]; 2592 2593 u8 no_buffer_discard_uc_low[0x20]; 2594 2595 u8 reserved_at_80[0x740]; 2596 }; 2597 2598 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2599 u8 wred_discard_high[0x20]; 2600 2601 u8 wred_discard_low[0x20]; 2602 2603 u8 ecn_marked_tc_high[0x20]; 2604 2605 u8 ecn_marked_tc_low[0x20]; 2606 2607 u8 reserved_at_80[0x740]; 2608 }; 2609 2610 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2611 u8 rx_octets_high[0x20]; 2612 2613 u8 rx_octets_low[0x20]; 2614 2615 u8 reserved_at_40[0xc0]; 2616 2617 u8 rx_frames_high[0x20]; 2618 2619 u8 rx_frames_low[0x20]; 2620 2621 u8 tx_octets_high[0x20]; 2622 2623 u8 tx_octets_low[0x20]; 2624 2625 u8 reserved_at_180[0xc0]; 2626 2627 u8 tx_frames_high[0x20]; 2628 2629 u8 tx_frames_low[0x20]; 2630 2631 u8 rx_pause_high[0x20]; 2632 2633 u8 rx_pause_low[0x20]; 2634 2635 u8 rx_pause_duration_high[0x20]; 2636 2637 u8 rx_pause_duration_low[0x20]; 2638 2639 u8 tx_pause_high[0x20]; 2640 2641 u8 tx_pause_low[0x20]; 2642 2643 u8 tx_pause_duration_high[0x20]; 2644 2645 u8 tx_pause_duration_low[0x20]; 2646 2647 u8 rx_pause_transition_high[0x20]; 2648 2649 u8 rx_pause_transition_low[0x20]; 2650 2651 u8 rx_discards_high[0x20]; 2652 2653 u8 rx_discards_low[0x20]; 2654 2655 u8 device_stall_minor_watermark_cnt_high[0x20]; 2656 2657 u8 device_stall_minor_watermark_cnt_low[0x20]; 2658 2659 u8 device_stall_critical_watermark_cnt_high[0x20]; 2660 2661 u8 device_stall_critical_watermark_cnt_low[0x20]; 2662 2663 u8 reserved_at_480[0x340]; 2664 }; 2665 2666 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2667 u8 port_transmit_wait_high[0x20]; 2668 2669 u8 port_transmit_wait_low[0x20]; 2670 2671 u8 reserved_at_40[0x100]; 2672 2673 u8 rx_buffer_almost_full_high[0x20]; 2674 2675 u8 rx_buffer_almost_full_low[0x20]; 2676 2677 u8 rx_buffer_full_high[0x20]; 2678 2679 u8 rx_buffer_full_low[0x20]; 2680 2681 u8 rx_icrc_encapsulated_high[0x20]; 2682 2683 u8 rx_icrc_encapsulated_low[0x20]; 2684 2685 u8 reserved_at_200[0x5c0]; 2686 }; 2687 2688 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2689 u8 dot3stats_alignment_errors_high[0x20]; 2690 2691 u8 dot3stats_alignment_errors_low[0x20]; 2692 2693 u8 dot3stats_fcs_errors_high[0x20]; 2694 2695 u8 dot3stats_fcs_errors_low[0x20]; 2696 2697 u8 dot3stats_single_collision_frames_high[0x20]; 2698 2699 u8 dot3stats_single_collision_frames_low[0x20]; 2700 2701 u8 dot3stats_multiple_collision_frames_high[0x20]; 2702 2703 u8 dot3stats_multiple_collision_frames_low[0x20]; 2704 2705 u8 dot3stats_sqe_test_errors_high[0x20]; 2706 2707 u8 dot3stats_sqe_test_errors_low[0x20]; 2708 2709 u8 dot3stats_deferred_transmissions_high[0x20]; 2710 2711 u8 dot3stats_deferred_transmissions_low[0x20]; 2712 2713 u8 dot3stats_late_collisions_high[0x20]; 2714 2715 u8 dot3stats_late_collisions_low[0x20]; 2716 2717 u8 dot3stats_excessive_collisions_high[0x20]; 2718 2719 u8 dot3stats_excessive_collisions_low[0x20]; 2720 2721 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2722 2723 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2724 2725 u8 dot3stats_carrier_sense_errors_high[0x20]; 2726 2727 u8 dot3stats_carrier_sense_errors_low[0x20]; 2728 2729 u8 dot3stats_frame_too_longs_high[0x20]; 2730 2731 u8 dot3stats_frame_too_longs_low[0x20]; 2732 2733 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2734 2735 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2736 2737 u8 dot3stats_symbol_errors_high[0x20]; 2738 2739 u8 dot3stats_symbol_errors_low[0x20]; 2740 2741 u8 dot3control_in_unknown_opcodes_high[0x20]; 2742 2743 u8 dot3control_in_unknown_opcodes_low[0x20]; 2744 2745 u8 dot3in_pause_frames_high[0x20]; 2746 2747 u8 dot3in_pause_frames_low[0x20]; 2748 2749 u8 dot3out_pause_frames_high[0x20]; 2750 2751 u8 dot3out_pause_frames_low[0x20]; 2752 2753 u8 reserved_at_400[0x3c0]; 2754 }; 2755 2756 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2757 u8 ether_stats_drop_events_high[0x20]; 2758 2759 u8 ether_stats_drop_events_low[0x20]; 2760 2761 u8 ether_stats_octets_high[0x20]; 2762 2763 u8 ether_stats_octets_low[0x20]; 2764 2765 u8 ether_stats_pkts_high[0x20]; 2766 2767 u8 ether_stats_pkts_low[0x20]; 2768 2769 u8 ether_stats_broadcast_pkts_high[0x20]; 2770 2771 u8 ether_stats_broadcast_pkts_low[0x20]; 2772 2773 u8 ether_stats_multicast_pkts_high[0x20]; 2774 2775 u8 ether_stats_multicast_pkts_low[0x20]; 2776 2777 u8 ether_stats_crc_align_errors_high[0x20]; 2778 2779 u8 ether_stats_crc_align_errors_low[0x20]; 2780 2781 u8 ether_stats_undersize_pkts_high[0x20]; 2782 2783 u8 ether_stats_undersize_pkts_low[0x20]; 2784 2785 u8 ether_stats_oversize_pkts_high[0x20]; 2786 2787 u8 ether_stats_oversize_pkts_low[0x20]; 2788 2789 u8 ether_stats_fragments_high[0x20]; 2790 2791 u8 ether_stats_fragments_low[0x20]; 2792 2793 u8 ether_stats_jabbers_high[0x20]; 2794 2795 u8 ether_stats_jabbers_low[0x20]; 2796 2797 u8 ether_stats_collisions_high[0x20]; 2798 2799 u8 ether_stats_collisions_low[0x20]; 2800 2801 u8 ether_stats_pkts64octets_high[0x20]; 2802 2803 u8 ether_stats_pkts64octets_low[0x20]; 2804 2805 u8 ether_stats_pkts65to127octets_high[0x20]; 2806 2807 u8 ether_stats_pkts65to127octets_low[0x20]; 2808 2809 u8 ether_stats_pkts128to255octets_high[0x20]; 2810 2811 u8 ether_stats_pkts128to255octets_low[0x20]; 2812 2813 u8 ether_stats_pkts256to511octets_high[0x20]; 2814 2815 u8 ether_stats_pkts256to511octets_low[0x20]; 2816 2817 u8 ether_stats_pkts512to1023octets_high[0x20]; 2818 2819 u8 ether_stats_pkts512to1023octets_low[0x20]; 2820 2821 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2822 2823 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2824 2825 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2826 2827 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2828 2829 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2830 2831 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2832 2833 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2834 2835 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2836 2837 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2838 2839 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2840 2841 u8 reserved_at_540[0x280]; 2842 }; 2843 2844 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2845 u8 if_in_octets_high[0x20]; 2846 2847 u8 if_in_octets_low[0x20]; 2848 2849 u8 if_in_ucast_pkts_high[0x20]; 2850 2851 u8 if_in_ucast_pkts_low[0x20]; 2852 2853 u8 if_in_discards_high[0x20]; 2854 2855 u8 if_in_discards_low[0x20]; 2856 2857 u8 if_in_errors_high[0x20]; 2858 2859 u8 if_in_errors_low[0x20]; 2860 2861 u8 if_in_unknown_protos_high[0x20]; 2862 2863 u8 if_in_unknown_protos_low[0x20]; 2864 2865 u8 if_out_octets_high[0x20]; 2866 2867 u8 if_out_octets_low[0x20]; 2868 2869 u8 if_out_ucast_pkts_high[0x20]; 2870 2871 u8 if_out_ucast_pkts_low[0x20]; 2872 2873 u8 if_out_discards_high[0x20]; 2874 2875 u8 if_out_discards_low[0x20]; 2876 2877 u8 if_out_errors_high[0x20]; 2878 2879 u8 if_out_errors_low[0x20]; 2880 2881 u8 if_in_multicast_pkts_high[0x20]; 2882 2883 u8 if_in_multicast_pkts_low[0x20]; 2884 2885 u8 if_in_broadcast_pkts_high[0x20]; 2886 2887 u8 if_in_broadcast_pkts_low[0x20]; 2888 2889 u8 if_out_multicast_pkts_high[0x20]; 2890 2891 u8 if_out_multicast_pkts_low[0x20]; 2892 2893 u8 if_out_broadcast_pkts_high[0x20]; 2894 2895 u8 if_out_broadcast_pkts_low[0x20]; 2896 2897 u8 reserved_at_340[0x480]; 2898 }; 2899 2900 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2901 u8 a_frames_transmitted_ok_high[0x20]; 2902 2903 u8 a_frames_transmitted_ok_low[0x20]; 2904 2905 u8 a_frames_received_ok_high[0x20]; 2906 2907 u8 a_frames_received_ok_low[0x20]; 2908 2909 u8 a_frame_check_sequence_errors_high[0x20]; 2910 2911 u8 a_frame_check_sequence_errors_low[0x20]; 2912 2913 u8 a_alignment_errors_high[0x20]; 2914 2915 u8 a_alignment_errors_low[0x20]; 2916 2917 u8 a_octets_transmitted_ok_high[0x20]; 2918 2919 u8 a_octets_transmitted_ok_low[0x20]; 2920 2921 u8 a_octets_received_ok_high[0x20]; 2922 2923 u8 a_octets_received_ok_low[0x20]; 2924 2925 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2926 2927 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2928 2929 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2930 2931 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2932 2933 u8 a_multicast_frames_received_ok_high[0x20]; 2934 2935 u8 a_multicast_frames_received_ok_low[0x20]; 2936 2937 u8 a_broadcast_frames_received_ok_high[0x20]; 2938 2939 u8 a_broadcast_frames_received_ok_low[0x20]; 2940 2941 u8 a_in_range_length_errors_high[0x20]; 2942 2943 u8 a_in_range_length_errors_low[0x20]; 2944 2945 u8 a_out_of_range_length_field_high[0x20]; 2946 2947 u8 a_out_of_range_length_field_low[0x20]; 2948 2949 u8 a_frame_too_long_errors_high[0x20]; 2950 2951 u8 a_frame_too_long_errors_low[0x20]; 2952 2953 u8 a_symbol_error_during_carrier_high[0x20]; 2954 2955 u8 a_symbol_error_during_carrier_low[0x20]; 2956 2957 u8 a_mac_control_frames_transmitted_high[0x20]; 2958 2959 u8 a_mac_control_frames_transmitted_low[0x20]; 2960 2961 u8 a_mac_control_frames_received_high[0x20]; 2962 2963 u8 a_mac_control_frames_received_low[0x20]; 2964 2965 u8 a_unsupported_opcodes_received_high[0x20]; 2966 2967 u8 a_unsupported_opcodes_received_low[0x20]; 2968 2969 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2970 2971 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2972 2973 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2974 2975 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2976 2977 u8 reserved_at_4c0[0x300]; 2978 }; 2979 2980 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2981 u8 life_time_counter_high[0x20]; 2982 2983 u8 life_time_counter_low[0x20]; 2984 2985 u8 rx_errors[0x20]; 2986 2987 u8 tx_errors[0x20]; 2988 2989 u8 l0_to_recovery_eieos[0x20]; 2990 2991 u8 l0_to_recovery_ts[0x20]; 2992 2993 u8 l0_to_recovery_framing[0x20]; 2994 2995 u8 l0_to_recovery_retrain[0x20]; 2996 2997 u8 crc_error_dllp[0x20]; 2998 2999 u8 crc_error_tlp[0x20]; 3000 3001 u8 tx_overflow_buffer_pkt_high[0x20]; 3002 3003 u8 tx_overflow_buffer_pkt_low[0x20]; 3004 3005 u8 outbound_stalled_reads[0x20]; 3006 3007 u8 outbound_stalled_writes[0x20]; 3008 3009 u8 outbound_stalled_reads_events[0x20]; 3010 3011 u8 outbound_stalled_writes_events[0x20]; 3012 3013 u8 reserved_at_200[0x5c0]; 3014 }; 3015 3016 struct mlx5_ifc_cmd_inter_comp_event_bits { 3017 u8 command_completion_vector[0x20]; 3018 3019 u8 reserved_at_20[0xc0]; 3020 }; 3021 3022 struct mlx5_ifc_stall_vl_event_bits { 3023 u8 reserved_at_0[0x18]; 3024 u8 port_num[0x1]; 3025 u8 reserved_at_19[0x3]; 3026 u8 vl[0x4]; 3027 3028 u8 reserved_at_20[0xa0]; 3029 }; 3030 3031 struct mlx5_ifc_db_bf_congestion_event_bits { 3032 u8 event_subtype[0x8]; 3033 u8 reserved_at_8[0x8]; 3034 u8 congestion_level[0x8]; 3035 u8 reserved_at_18[0x8]; 3036 3037 u8 reserved_at_20[0xa0]; 3038 }; 3039 3040 struct mlx5_ifc_gpio_event_bits { 3041 u8 reserved_at_0[0x60]; 3042 3043 u8 gpio_event_hi[0x20]; 3044 3045 u8 gpio_event_lo[0x20]; 3046 3047 u8 reserved_at_a0[0x40]; 3048 }; 3049 3050 struct mlx5_ifc_port_state_change_event_bits { 3051 u8 reserved_at_0[0x40]; 3052 3053 u8 port_num[0x4]; 3054 u8 reserved_at_44[0x1c]; 3055 3056 u8 reserved_at_60[0x80]; 3057 }; 3058 3059 struct mlx5_ifc_dropped_packet_logged_bits { 3060 u8 reserved_at_0[0xe0]; 3061 }; 3062 3063 struct mlx5_ifc_default_timeout_bits { 3064 u8 to_multiplier[0x3]; 3065 u8 reserved_at_3[0x9]; 3066 u8 to_value[0x14]; 3067 }; 3068 3069 struct mlx5_ifc_dtor_reg_bits { 3070 u8 reserved_at_0[0x20]; 3071 3072 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3073 3074 u8 reserved_at_40[0x60]; 3075 3076 struct mlx5_ifc_default_timeout_bits health_poll_to; 3077 3078 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3079 3080 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3081 3082 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3083 3084 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3085 3086 struct mlx5_ifc_default_timeout_bits tear_down_to; 3087 3088 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3089 3090 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3091 3092 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3093 3094 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3095 3096 u8 reserved_at_1c0[0x20]; 3097 }; 3098 3099 enum { 3100 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3101 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3102 }; 3103 3104 struct mlx5_ifc_cq_error_bits { 3105 u8 reserved_at_0[0x8]; 3106 u8 cqn[0x18]; 3107 3108 u8 reserved_at_20[0x20]; 3109 3110 u8 reserved_at_40[0x18]; 3111 u8 syndrome[0x8]; 3112 3113 u8 reserved_at_60[0x80]; 3114 }; 3115 3116 struct mlx5_ifc_rdma_page_fault_event_bits { 3117 u8 bytes_committed[0x20]; 3118 3119 u8 r_key[0x20]; 3120 3121 u8 reserved_at_40[0x10]; 3122 u8 packet_len[0x10]; 3123 3124 u8 rdma_op_len[0x20]; 3125 3126 u8 rdma_va[0x40]; 3127 3128 u8 reserved_at_c0[0x5]; 3129 u8 rdma[0x1]; 3130 u8 write[0x1]; 3131 u8 requestor[0x1]; 3132 u8 qp_number[0x18]; 3133 }; 3134 3135 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3136 u8 bytes_committed[0x20]; 3137 3138 u8 reserved_at_20[0x10]; 3139 u8 wqe_index[0x10]; 3140 3141 u8 reserved_at_40[0x10]; 3142 u8 len[0x10]; 3143 3144 u8 reserved_at_60[0x60]; 3145 3146 u8 reserved_at_c0[0x5]; 3147 u8 rdma[0x1]; 3148 u8 write_read[0x1]; 3149 u8 requestor[0x1]; 3150 u8 qpn[0x18]; 3151 }; 3152 3153 struct mlx5_ifc_qp_events_bits { 3154 u8 reserved_at_0[0xa0]; 3155 3156 u8 type[0x8]; 3157 u8 reserved_at_a8[0x18]; 3158 3159 u8 reserved_at_c0[0x8]; 3160 u8 qpn_rqn_sqn[0x18]; 3161 }; 3162 3163 struct mlx5_ifc_dct_events_bits { 3164 u8 reserved_at_0[0xc0]; 3165 3166 u8 reserved_at_c0[0x8]; 3167 u8 dct_number[0x18]; 3168 }; 3169 3170 struct mlx5_ifc_comp_event_bits { 3171 u8 reserved_at_0[0xc0]; 3172 3173 u8 reserved_at_c0[0x8]; 3174 u8 cq_number[0x18]; 3175 }; 3176 3177 enum { 3178 MLX5_QPC_STATE_RST = 0x0, 3179 MLX5_QPC_STATE_INIT = 0x1, 3180 MLX5_QPC_STATE_RTR = 0x2, 3181 MLX5_QPC_STATE_RTS = 0x3, 3182 MLX5_QPC_STATE_SQER = 0x4, 3183 MLX5_QPC_STATE_ERR = 0x6, 3184 MLX5_QPC_STATE_SQD = 0x7, 3185 MLX5_QPC_STATE_SUSPENDED = 0x9, 3186 }; 3187 3188 enum { 3189 MLX5_QPC_ST_RC = 0x0, 3190 MLX5_QPC_ST_UC = 0x1, 3191 MLX5_QPC_ST_UD = 0x2, 3192 MLX5_QPC_ST_XRC = 0x3, 3193 MLX5_QPC_ST_DCI = 0x5, 3194 MLX5_QPC_ST_QP0 = 0x7, 3195 MLX5_QPC_ST_QP1 = 0x8, 3196 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3197 MLX5_QPC_ST_REG_UMR = 0xc, 3198 }; 3199 3200 enum { 3201 MLX5_QPC_PM_STATE_ARMED = 0x0, 3202 MLX5_QPC_PM_STATE_REARM = 0x1, 3203 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3204 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3205 }; 3206 3207 enum { 3208 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3209 }; 3210 3211 enum { 3212 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3213 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3214 }; 3215 3216 enum { 3217 MLX5_QPC_MTU_256_BYTES = 0x1, 3218 MLX5_QPC_MTU_512_BYTES = 0x2, 3219 MLX5_QPC_MTU_1K_BYTES = 0x3, 3220 MLX5_QPC_MTU_2K_BYTES = 0x4, 3221 MLX5_QPC_MTU_4K_BYTES = 0x5, 3222 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3223 }; 3224 3225 enum { 3226 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3227 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3228 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3229 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3230 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3231 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3232 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3233 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3234 }; 3235 3236 enum { 3237 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3238 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3239 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3240 }; 3241 3242 enum { 3243 MLX5_QPC_CS_RES_DISABLE = 0x0, 3244 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3245 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3246 }; 3247 3248 enum { 3249 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3250 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3251 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3252 }; 3253 3254 struct mlx5_ifc_qpc_bits { 3255 u8 state[0x4]; 3256 u8 lag_tx_port_affinity[0x4]; 3257 u8 st[0x8]; 3258 u8 reserved_at_10[0x2]; 3259 u8 isolate_vl_tc[0x1]; 3260 u8 pm_state[0x2]; 3261 u8 reserved_at_15[0x1]; 3262 u8 req_e2e_credit_mode[0x2]; 3263 u8 offload_type[0x4]; 3264 u8 end_padding_mode[0x2]; 3265 u8 reserved_at_1e[0x2]; 3266 3267 u8 wq_signature[0x1]; 3268 u8 block_lb_mc[0x1]; 3269 u8 atomic_like_write_en[0x1]; 3270 u8 latency_sensitive[0x1]; 3271 u8 reserved_at_24[0x1]; 3272 u8 drain_sigerr[0x1]; 3273 u8 reserved_at_26[0x2]; 3274 u8 pd[0x18]; 3275 3276 u8 mtu[0x3]; 3277 u8 log_msg_max[0x5]; 3278 u8 reserved_at_48[0x1]; 3279 u8 log_rq_size[0x4]; 3280 u8 log_rq_stride[0x3]; 3281 u8 no_sq[0x1]; 3282 u8 log_sq_size[0x4]; 3283 u8 reserved_at_55[0x1]; 3284 u8 retry_mode[0x2]; 3285 u8 ts_format[0x2]; 3286 u8 reserved_at_5a[0x1]; 3287 u8 rlky[0x1]; 3288 u8 ulp_stateless_offload_mode[0x4]; 3289 3290 u8 counter_set_id[0x8]; 3291 u8 uar_page[0x18]; 3292 3293 u8 reserved_at_80[0x8]; 3294 u8 user_index[0x18]; 3295 3296 u8 reserved_at_a0[0x3]; 3297 u8 log_page_size[0x5]; 3298 u8 remote_qpn[0x18]; 3299 3300 struct mlx5_ifc_ads_bits primary_address_path; 3301 3302 struct mlx5_ifc_ads_bits secondary_address_path; 3303 3304 u8 log_ack_req_freq[0x4]; 3305 u8 reserved_at_384[0x4]; 3306 u8 log_sra_max[0x3]; 3307 u8 reserved_at_38b[0x2]; 3308 u8 retry_count[0x3]; 3309 u8 rnr_retry[0x3]; 3310 u8 reserved_at_393[0x1]; 3311 u8 fre[0x1]; 3312 u8 cur_rnr_retry[0x3]; 3313 u8 cur_retry_count[0x3]; 3314 u8 reserved_at_39b[0x5]; 3315 3316 u8 reserved_at_3a0[0x20]; 3317 3318 u8 reserved_at_3c0[0x8]; 3319 u8 next_send_psn[0x18]; 3320 3321 u8 reserved_at_3e0[0x3]; 3322 u8 log_num_dci_stream_channels[0x5]; 3323 u8 cqn_snd[0x18]; 3324 3325 u8 reserved_at_400[0x3]; 3326 u8 log_num_dci_errored_streams[0x5]; 3327 u8 deth_sqpn[0x18]; 3328 3329 u8 reserved_at_420[0x20]; 3330 3331 u8 reserved_at_440[0x8]; 3332 u8 last_acked_psn[0x18]; 3333 3334 u8 reserved_at_460[0x8]; 3335 u8 ssn[0x18]; 3336 3337 u8 reserved_at_480[0x8]; 3338 u8 log_rra_max[0x3]; 3339 u8 reserved_at_48b[0x1]; 3340 u8 atomic_mode[0x4]; 3341 u8 rre[0x1]; 3342 u8 rwe[0x1]; 3343 u8 rae[0x1]; 3344 u8 reserved_at_493[0x1]; 3345 u8 page_offset[0x6]; 3346 u8 reserved_at_49a[0x3]; 3347 u8 cd_slave_receive[0x1]; 3348 u8 cd_slave_send[0x1]; 3349 u8 cd_master[0x1]; 3350 3351 u8 reserved_at_4a0[0x3]; 3352 u8 min_rnr_nak[0x5]; 3353 u8 next_rcv_psn[0x18]; 3354 3355 u8 reserved_at_4c0[0x8]; 3356 u8 xrcd[0x18]; 3357 3358 u8 reserved_at_4e0[0x8]; 3359 u8 cqn_rcv[0x18]; 3360 3361 u8 dbr_addr[0x40]; 3362 3363 u8 q_key[0x20]; 3364 3365 u8 reserved_at_560[0x5]; 3366 u8 rq_type[0x3]; 3367 u8 srqn_rmpn_xrqn[0x18]; 3368 3369 u8 reserved_at_580[0x8]; 3370 u8 rmsn[0x18]; 3371 3372 u8 hw_sq_wqebb_counter[0x10]; 3373 u8 sw_sq_wqebb_counter[0x10]; 3374 3375 u8 hw_rq_counter[0x20]; 3376 3377 u8 sw_rq_counter[0x20]; 3378 3379 u8 reserved_at_600[0x20]; 3380 3381 u8 reserved_at_620[0xf]; 3382 u8 cgs[0x1]; 3383 u8 cs_req[0x8]; 3384 u8 cs_res[0x8]; 3385 3386 u8 dc_access_key[0x40]; 3387 3388 u8 reserved_at_680[0x3]; 3389 u8 dbr_umem_valid[0x1]; 3390 3391 u8 reserved_at_684[0xbc]; 3392 }; 3393 3394 struct mlx5_ifc_roce_addr_layout_bits { 3395 u8 source_l3_address[16][0x8]; 3396 3397 u8 reserved_at_80[0x3]; 3398 u8 vlan_valid[0x1]; 3399 u8 vlan_id[0xc]; 3400 u8 source_mac_47_32[0x10]; 3401 3402 u8 source_mac_31_0[0x20]; 3403 3404 u8 reserved_at_c0[0x14]; 3405 u8 roce_l3_type[0x4]; 3406 u8 roce_version[0x8]; 3407 3408 u8 reserved_at_e0[0x20]; 3409 }; 3410 3411 struct mlx5_ifc_crypto_cap_bits { 3412 u8 reserved_at_0[0x3]; 3413 u8 synchronize_dek[0x1]; 3414 u8 int_kek_manual[0x1]; 3415 u8 int_kek_auto[0x1]; 3416 u8 reserved_at_6[0x1a]; 3417 3418 u8 reserved_at_20[0x3]; 3419 u8 log_dek_max_alloc[0x5]; 3420 u8 reserved_at_28[0x3]; 3421 u8 log_max_num_deks[0x5]; 3422 u8 reserved_at_30[0x10]; 3423 3424 u8 reserved_at_40[0x20]; 3425 3426 u8 reserved_at_60[0x3]; 3427 u8 log_dek_granularity[0x5]; 3428 u8 reserved_at_68[0x3]; 3429 u8 log_max_num_int_kek[0x5]; 3430 u8 sw_wrapped_dek[0x10]; 3431 3432 u8 reserved_at_80[0x780]; 3433 }; 3434 3435 union mlx5_ifc_hca_cap_union_bits { 3436 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3437 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3438 struct mlx5_ifc_odp_cap_bits odp_cap; 3439 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3440 struct mlx5_ifc_roce_cap_bits roce_cap; 3441 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3442 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3443 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3444 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3445 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3446 struct mlx5_ifc_qos_cap_bits qos_cap; 3447 struct mlx5_ifc_debug_cap_bits debug_cap; 3448 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3449 struct mlx5_ifc_tls_cap_bits tls_cap; 3450 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3451 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3452 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3453 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3454 u8 reserved_at_0[0x8000]; 3455 }; 3456 3457 enum { 3458 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3459 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3460 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3461 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3462 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3463 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3464 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3465 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3466 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3467 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3468 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3469 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3470 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3471 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3472 }; 3473 3474 enum { 3475 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3476 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3477 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3478 }; 3479 3480 enum { 3481 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3482 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3483 }; 3484 3485 struct mlx5_ifc_vlan_bits { 3486 u8 ethtype[0x10]; 3487 u8 prio[0x3]; 3488 u8 cfi[0x1]; 3489 u8 vid[0xc]; 3490 }; 3491 3492 enum { 3493 MLX5_FLOW_METER_COLOR_RED = 0x0, 3494 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3495 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3496 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3497 }; 3498 3499 enum { 3500 MLX5_EXE_ASO_FLOW_METER = 0x2, 3501 }; 3502 3503 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3504 u8 return_reg_id[0x4]; 3505 u8 aso_type[0x4]; 3506 u8 reserved_at_8[0x14]; 3507 u8 action[0x1]; 3508 u8 init_color[0x2]; 3509 u8 meter_id[0x1]; 3510 }; 3511 3512 union mlx5_ifc_exe_aso_ctrl { 3513 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3514 }; 3515 3516 struct mlx5_ifc_execute_aso_bits { 3517 u8 valid[0x1]; 3518 u8 reserved_at_1[0x7]; 3519 u8 aso_object_id[0x18]; 3520 3521 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3522 }; 3523 3524 struct mlx5_ifc_flow_context_bits { 3525 struct mlx5_ifc_vlan_bits push_vlan; 3526 3527 u8 group_id[0x20]; 3528 3529 u8 reserved_at_40[0x8]; 3530 u8 flow_tag[0x18]; 3531 3532 u8 reserved_at_60[0x10]; 3533 u8 action[0x10]; 3534 3535 u8 extended_destination[0x1]; 3536 u8 reserved_at_81[0x1]; 3537 u8 flow_source[0x2]; 3538 u8 encrypt_decrypt_type[0x4]; 3539 u8 destination_list_size[0x18]; 3540 3541 u8 reserved_at_a0[0x8]; 3542 u8 flow_counter_list_size[0x18]; 3543 3544 u8 packet_reformat_id[0x20]; 3545 3546 u8 modify_header_id[0x20]; 3547 3548 struct mlx5_ifc_vlan_bits push_vlan_2; 3549 3550 u8 encrypt_decrypt_obj_id[0x20]; 3551 u8 reserved_at_140[0xc0]; 3552 3553 struct mlx5_ifc_fte_match_param_bits match_value; 3554 3555 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3556 3557 u8 reserved_at_1300[0x500]; 3558 3559 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3560 }; 3561 3562 enum { 3563 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3564 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3565 }; 3566 3567 struct mlx5_ifc_xrc_srqc_bits { 3568 u8 state[0x4]; 3569 u8 log_xrc_srq_size[0x4]; 3570 u8 reserved_at_8[0x18]; 3571 3572 u8 wq_signature[0x1]; 3573 u8 cont_srq[0x1]; 3574 u8 reserved_at_22[0x1]; 3575 u8 rlky[0x1]; 3576 u8 basic_cyclic_rcv_wqe[0x1]; 3577 u8 log_rq_stride[0x3]; 3578 u8 xrcd[0x18]; 3579 3580 u8 page_offset[0x6]; 3581 u8 reserved_at_46[0x1]; 3582 u8 dbr_umem_valid[0x1]; 3583 u8 cqn[0x18]; 3584 3585 u8 reserved_at_60[0x20]; 3586 3587 u8 user_index_equal_xrc_srqn[0x1]; 3588 u8 reserved_at_81[0x1]; 3589 u8 log_page_size[0x6]; 3590 u8 user_index[0x18]; 3591 3592 u8 reserved_at_a0[0x20]; 3593 3594 u8 reserved_at_c0[0x8]; 3595 u8 pd[0x18]; 3596 3597 u8 lwm[0x10]; 3598 u8 wqe_cnt[0x10]; 3599 3600 u8 reserved_at_100[0x40]; 3601 3602 u8 db_record_addr_h[0x20]; 3603 3604 u8 db_record_addr_l[0x1e]; 3605 u8 reserved_at_17e[0x2]; 3606 3607 u8 reserved_at_180[0x80]; 3608 }; 3609 3610 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3611 u8 counter_error_queues[0x20]; 3612 3613 u8 total_error_queues[0x20]; 3614 3615 u8 send_queue_priority_update_flow[0x20]; 3616 3617 u8 reserved_at_60[0x20]; 3618 3619 u8 nic_receive_steering_discard[0x40]; 3620 3621 u8 receive_discard_vport_down[0x40]; 3622 3623 u8 transmit_discard_vport_down[0x40]; 3624 3625 u8 async_eq_overrun[0x20]; 3626 3627 u8 comp_eq_overrun[0x20]; 3628 3629 u8 reserved_at_180[0x20]; 3630 3631 u8 invalid_command[0x20]; 3632 3633 u8 quota_exceeded_command[0x20]; 3634 3635 u8 internal_rq_out_of_buffer[0x20]; 3636 3637 u8 cq_overrun[0x20]; 3638 3639 u8 eth_wqe_too_small[0x20]; 3640 3641 u8 reserved_at_220[0xc0]; 3642 3643 u8 generated_pkt_steering_fail[0x40]; 3644 3645 u8 handled_pkt_steering_fail[0x40]; 3646 3647 u8 reserved_at_360[0xc80]; 3648 }; 3649 3650 struct mlx5_ifc_traffic_counter_bits { 3651 u8 packets[0x40]; 3652 3653 u8 octets[0x40]; 3654 }; 3655 3656 struct mlx5_ifc_tisc_bits { 3657 u8 strict_lag_tx_port_affinity[0x1]; 3658 u8 tls_en[0x1]; 3659 u8 reserved_at_2[0x2]; 3660 u8 lag_tx_port_affinity[0x04]; 3661 3662 u8 reserved_at_8[0x4]; 3663 u8 prio[0x4]; 3664 u8 reserved_at_10[0x10]; 3665 3666 u8 reserved_at_20[0x100]; 3667 3668 u8 reserved_at_120[0x8]; 3669 u8 transport_domain[0x18]; 3670 3671 u8 reserved_at_140[0x8]; 3672 u8 underlay_qpn[0x18]; 3673 3674 u8 reserved_at_160[0x8]; 3675 u8 pd[0x18]; 3676 3677 u8 reserved_at_180[0x380]; 3678 }; 3679 3680 enum { 3681 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3682 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3683 }; 3684 3685 enum { 3686 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3687 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3688 }; 3689 3690 enum { 3691 MLX5_RX_HASH_FN_NONE = 0x0, 3692 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3693 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3694 }; 3695 3696 enum { 3697 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3698 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3699 }; 3700 3701 struct mlx5_ifc_tirc_bits { 3702 u8 reserved_at_0[0x20]; 3703 3704 u8 disp_type[0x4]; 3705 u8 tls_en[0x1]; 3706 u8 reserved_at_25[0x1b]; 3707 3708 u8 reserved_at_40[0x40]; 3709 3710 u8 reserved_at_80[0x4]; 3711 u8 lro_timeout_period_usecs[0x10]; 3712 u8 packet_merge_mask[0x4]; 3713 u8 lro_max_ip_payload_size[0x8]; 3714 3715 u8 reserved_at_a0[0x40]; 3716 3717 u8 reserved_at_e0[0x8]; 3718 u8 inline_rqn[0x18]; 3719 3720 u8 rx_hash_symmetric[0x1]; 3721 u8 reserved_at_101[0x1]; 3722 u8 tunneled_offload_en[0x1]; 3723 u8 reserved_at_103[0x5]; 3724 u8 indirect_table[0x18]; 3725 3726 u8 rx_hash_fn[0x4]; 3727 u8 reserved_at_124[0x2]; 3728 u8 self_lb_block[0x2]; 3729 u8 transport_domain[0x18]; 3730 3731 u8 rx_hash_toeplitz_key[10][0x20]; 3732 3733 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3734 3735 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3736 3737 u8 reserved_at_2c0[0x4c0]; 3738 }; 3739 3740 enum { 3741 MLX5_SRQC_STATE_GOOD = 0x0, 3742 MLX5_SRQC_STATE_ERROR = 0x1, 3743 }; 3744 3745 struct mlx5_ifc_srqc_bits { 3746 u8 state[0x4]; 3747 u8 log_srq_size[0x4]; 3748 u8 reserved_at_8[0x18]; 3749 3750 u8 wq_signature[0x1]; 3751 u8 cont_srq[0x1]; 3752 u8 reserved_at_22[0x1]; 3753 u8 rlky[0x1]; 3754 u8 reserved_at_24[0x1]; 3755 u8 log_rq_stride[0x3]; 3756 u8 xrcd[0x18]; 3757 3758 u8 page_offset[0x6]; 3759 u8 reserved_at_46[0x2]; 3760 u8 cqn[0x18]; 3761 3762 u8 reserved_at_60[0x20]; 3763 3764 u8 reserved_at_80[0x2]; 3765 u8 log_page_size[0x6]; 3766 u8 reserved_at_88[0x18]; 3767 3768 u8 reserved_at_a0[0x20]; 3769 3770 u8 reserved_at_c0[0x8]; 3771 u8 pd[0x18]; 3772 3773 u8 lwm[0x10]; 3774 u8 wqe_cnt[0x10]; 3775 3776 u8 reserved_at_100[0x40]; 3777 3778 u8 dbr_addr[0x40]; 3779 3780 u8 reserved_at_180[0x80]; 3781 }; 3782 3783 enum { 3784 MLX5_SQC_STATE_RST = 0x0, 3785 MLX5_SQC_STATE_RDY = 0x1, 3786 MLX5_SQC_STATE_ERR = 0x3, 3787 }; 3788 3789 struct mlx5_ifc_sqc_bits { 3790 u8 rlky[0x1]; 3791 u8 cd_master[0x1]; 3792 u8 fre[0x1]; 3793 u8 flush_in_error_en[0x1]; 3794 u8 allow_multi_pkt_send_wqe[0x1]; 3795 u8 min_wqe_inline_mode[0x3]; 3796 u8 state[0x4]; 3797 u8 reg_umr[0x1]; 3798 u8 allow_swp[0x1]; 3799 u8 hairpin[0x1]; 3800 u8 reserved_at_f[0xb]; 3801 u8 ts_format[0x2]; 3802 u8 reserved_at_1c[0x4]; 3803 3804 u8 reserved_at_20[0x8]; 3805 u8 user_index[0x18]; 3806 3807 u8 reserved_at_40[0x8]; 3808 u8 cqn[0x18]; 3809 3810 u8 reserved_at_60[0x8]; 3811 u8 hairpin_peer_rq[0x18]; 3812 3813 u8 reserved_at_80[0x10]; 3814 u8 hairpin_peer_vhca[0x10]; 3815 3816 u8 reserved_at_a0[0x20]; 3817 3818 u8 reserved_at_c0[0x8]; 3819 u8 ts_cqe_to_dest_cqn[0x18]; 3820 3821 u8 reserved_at_e0[0x10]; 3822 u8 packet_pacing_rate_limit_index[0x10]; 3823 u8 tis_lst_sz[0x10]; 3824 u8 qos_queue_group_id[0x10]; 3825 3826 u8 reserved_at_120[0x40]; 3827 3828 u8 reserved_at_160[0x8]; 3829 u8 tis_num_0[0x18]; 3830 3831 struct mlx5_ifc_wq_bits wq; 3832 }; 3833 3834 enum { 3835 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3836 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3837 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3838 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3839 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3840 }; 3841 3842 enum { 3843 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3844 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3845 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3846 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3847 }; 3848 3849 struct mlx5_ifc_scheduling_context_bits { 3850 u8 element_type[0x8]; 3851 u8 reserved_at_8[0x18]; 3852 3853 u8 element_attributes[0x20]; 3854 3855 u8 parent_element_id[0x20]; 3856 3857 u8 reserved_at_60[0x40]; 3858 3859 u8 bw_share[0x20]; 3860 3861 u8 max_average_bw[0x20]; 3862 3863 u8 reserved_at_e0[0x120]; 3864 }; 3865 3866 struct mlx5_ifc_rqtc_bits { 3867 u8 reserved_at_0[0xa0]; 3868 3869 u8 reserved_at_a0[0x5]; 3870 u8 list_q_type[0x3]; 3871 u8 reserved_at_a8[0x8]; 3872 u8 rqt_max_size[0x10]; 3873 3874 u8 rq_vhca_id_format[0x1]; 3875 u8 reserved_at_c1[0xf]; 3876 u8 rqt_actual_size[0x10]; 3877 3878 u8 reserved_at_e0[0x6a0]; 3879 3880 struct mlx5_ifc_rq_num_bits rq_num[]; 3881 }; 3882 3883 enum { 3884 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3885 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3886 }; 3887 3888 enum { 3889 MLX5_RQC_STATE_RST = 0x0, 3890 MLX5_RQC_STATE_RDY = 0x1, 3891 MLX5_RQC_STATE_ERR = 0x3, 3892 }; 3893 3894 enum { 3895 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3896 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3897 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3898 }; 3899 3900 enum { 3901 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3902 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3903 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3904 }; 3905 3906 struct mlx5_ifc_rqc_bits { 3907 u8 rlky[0x1]; 3908 u8 delay_drop_en[0x1]; 3909 u8 scatter_fcs[0x1]; 3910 u8 vsd[0x1]; 3911 u8 mem_rq_type[0x4]; 3912 u8 state[0x4]; 3913 u8 reserved_at_c[0x1]; 3914 u8 flush_in_error_en[0x1]; 3915 u8 hairpin[0x1]; 3916 u8 reserved_at_f[0xb]; 3917 u8 ts_format[0x2]; 3918 u8 reserved_at_1c[0x4]; 3919 3920 u8 reserved_at_20[0x8]; 3921 u8 user_index[0x18]; 3922 3923 u8 reserved_at_40[0x8]; 3924 u8 cqn[0x18]; 3925 3926 u8 counter_set_id[0x8]; 3927 u8 reserved_at_68[0x18]; 3928 3929 u8 reserved_at_80[0x8]; 3930 u8 rmpn[0x18]; 3931 3932 u8 reserved_at_a0[0x8]; 3933 u8 hairpin_peer_sq[0x18]; 3934 3935 u8 reserved_at_c0[0x10]; 3936 u8 hairpin_peer_vhca[0x10]; 3937 3938 u8 reserved_at_e0[0x46]; 3939 u8 shampo_no_match_alignment_granularity[0x2]; 3940 u8 reserved_at_128[0x6]; 3941 u8 shampo_match_criteria_type[0x2]; 3942 u8 reservation_timeout[0x10]; 3943 3944 u8 reserved_at_140[0x40]; 3945 3946 struct mlx5_ifc_wq_bits wq; 3947 }; 3948 3949 enum { 3950 MLX5_RMPC_STATE_RDY = 0x1, 3951 MLX5_RMPC_STATE_ERR = 0x3, 3952 }; 3953 3954 struct mlx5_ifc_rmpc_bits { 3955 u8 reserved_at_0[0x8]; 3956 u8 state[0x4]; 3957 u8 reserved_at_c[0x14]; 3958 3959 u8 basic_cyclic_rcv_wqe[0x1]; 3960 u8 reserved_at_21[0x1f]; 3961 3962 u8 reserved_at_40[0x140]; 3963 3964 struct mlx5_ifc_wq_bits wq; 3965 }; 3966 3967 enum { 3968 VHCA_ID_TYPE_HW = 0, 3969 VHCA_ID_TYPE_SW = 1, 3970 }; 3971 3972 struct mlx5_ifc_nic_vport_context_bits { 3973 u8 reserved_at_0[0x5]; 3974 u8 min_wqe_inline_mode[0x3]; 3975 u8 reserved_at_8[0x15]; 3976 u8 disable_mc_local_lb[0x1]; 3977 u8 disable_uc_local_lb[0x1]; 3978 u8 roce_en[0x1]; 3979 3980 u8 arm_change_event[0x1]; 3981 u8 reserved_at_21[0x1a]; 3982 u8 event_on_mtu[0x1]; 3983 u8 event_on_promisc_change[0x1]; 3984 u8 event_on_vlan_change[0x1]; 3985 u8 event_on_mc_address_change[0x1]; 3986 u8 event_on_uc_address_change[0x1]; 3987 3988 u8 vhca_id_type[0x1]; 3989 u8 reserved_at_41[0xb]; 3990 u8 affiliation_criteria[0x4]; 3991 u8 affiliated_vhca_id[0x10]; 3992 3993 u8 reserved_at_60[0xd0]; 3994 3995 u8 mtu[0x10]; 3996 3997 u8 system_image_guid[0x40]; 3998 u8 port_guid[0x40]; 3999 u8 node_guid[0x40]; 4000 4001 u8 reserved_at_200[0x140]; 4002 u8 qkey_violation_counter[0x10]; 4003 u8 reserved_at_350[0x430]; 4004 4005 u8 promisc_uc[0x1]; 4006 u8 promisc_mc[0x1]; 4007 u8 promisc_all[0x1]; 4008 u8 reserved_at_783[0x2]; 4009 u8 allowed_list_type[0x3]; 4010 u8 reserved_at_788[0xc]; 4011 u8 allowed_list_size[0xc]; 4012 4013 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4014 4015 u8 reserved_at_7e0[0x20]; 4016 4017 u8 current_uc_mac_address[][0x40]; 4018 }; 4019 4020 enum { 4021 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4022 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4023 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4024 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4025 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4026 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4027 }; 4028 4029 struct mlx5_ifc_mkc_bits { 4030 u8 reserved_at_0[0x1]; 4031 u8 free[0x1]; 4032 u8 reserved_at_2[0x1]; 4033 u8 access_mode_4_2[0x3]; 4034 u8 reserved_at_6[0x7]; 4035 u8 relaxed_ordering_write[0x1]; 4036 u8 reserved_at_e[0x1]; 4037 u8 small_fence_on_rdma_read_response[0x1]; 4038 u8 umr_en[0x1]; 4039 u8 a[0x1]; 4040 u8 rw[0x1]; 4041 u8 rr[0x1]; 4042 u8 lw[0x1]; 4043 u8 lr[0x1]; 4044 u8 access_mode_1_0[0x2]; 4045 u8 reserved_at_18[0x2]; 4046 u8 ma_translation_mode[0x2]; 4047 u8 reserved_at_1c[0x4]; 4048 4049 u8 qpn[0x18]; 4050 u8 mkey_7_0[0x8]; 4051 4052 u8 reserved_at_40[0x20]; 4053 4054 u8 length64[0x1]; 4055 u8 bsf_en[0x1]; 4056 u8 sync_umr[0x1]; 4057 u8 reserved_at_63[0x2]; 4058 u8 expected_sigerr_count[0x1]; 4059 u8 reserved_at_66[0x1]; 4060 u8 en_rinval[0x1]; 4061 u8 pd[0x18]; 4062 4063 u8 start_addr[0x40]; 4064 4065 u8 len[0x40]; 4066 4067 u8 bsf_octword_size[0x20]; 4068 4069 u8 reserved_at_120[0x80]; 4070 4071 u8 translations_octword_size[0x20]; 4072 4073 u8 reserved_at_1c0[0x19]; 4074 u8 relaxed_ordering_read[0x1]; 4075 u8 reserved_at_1d9[0x1]; 4076 u8 log_page_size[0x5]; 4077 4078 u8 reserved_at_1e0[0x20]; 4079 }; 4080 4081 struct mlx5_ifc_pkey_bits { 4082 u8 reserved_at_0[0x10]; 4083 u8 pkey[0x10]; 4084 }; 4085 4086 struct mlx5_ifc_array128_auto_bits { 4087 u8 array128_auto[16][0x8]; 4088 }; 4089 4090 struct mlx5_ifc_hca_vport_context_bits { 4091 u8 field_select[0x20]; 4092 4093 u8 reserved_at_20[0xe0]; 4094 4095 u8 sm_virt_aware[0x1]; 4096 u8 has_smi[0x1]; 4097 u8 has_raw[0x1]; 4098 u8 grh_required[0x1]; 4099 u8 reserved_at_104[0xc]; 4100 u8 port_physical_state[0x4]; 4101 u8 vport_state_policy[0x4]; 4102 u8 port_state[0x4]; 4103 u8 vport_state[0x4]; 4104 4105 u8 reserved_at_120[0x20]; 4106 4107 u8 system_image_guid[0x40]; 4108 4109 u8 port_guid[0x40]; 4110 4111 u8 node_guid[0x40]; 4112 4113 u8 cap_mask1[0x20]; 4114 4115 u8 cap_mask1_field_select[0x20]; 4116 4117 u8 cap_mask2[0x20]; 4118 4119 u8 cap_mask2_field_select[0x20]; 4120 4121 u8 reserved_at_280[0x80]; 4122 4123 u8 lid[0x10]; 4124 u8 reserved_at_310[0x4]; 4125 u8 init_type_reply[0x4]; 4126 u8 lmc[0x3]; 4127 u8 subnet_timeout[0x5]; 4128 4129 u8 sm_lid[0x10]; 4130 u8 sm_sl[0x4]; 4131 u8 reserved_at_334[0xc]; 4132 4133 u8 qkey_violation_counter[0x10]; 4134 u8 pkey_violation_counter[0x10]; 4135 4136 u8 reserved_at_360[0xca0]; 4137 }; 4138 4139 struct mlx5_ifc_esw_vport_context_bits { 4140 u8 fdb_to_vport_reg_c[0x1]; 4141 u8 reserved_at_1[0x2]; 4142 u8 vport_svlan_strip[0x1]; 4143 u8 vport_cvlan_strip[0x1]; 4144 u8 vport_svlan_insert[0x1]; 4145 u8 vport_cvlan_insert[0x2]; 4146 u8 fdb_to_vport_reg_c_id[0x8]; 4147 u8 reserved_at_10[0x10]; 4148 4149 u8 reserved_at_20[0x20]; 4150 4151 u8 svlan_cfi[0x1]; 4152 u8 svlan_pcp[0x3]; 4153 u8 svlan_id[0xc]; 4154 u8 cvlan_cfi[0x1]; 4155 u8 cvlan_pcp[0x3]; 4156 u8 cvlan_id[0xc]; 4157 4158 u8 reserved_at_60[0x720]; 4159 4160 u8 sw_steering_vport_icm_address_rx[0x40]; 4161 4162 u8 sw_steering_vport_icm_address_tx[0x40]; 4163 }; 4164 4165 enum { 4166 MLX5_EQC_STATUS_OK = 0x0, 4167 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4168 }; 4169 4170 enum { 4171 MLX5_EQC_ST_ARMED = 0x9, 4172 MLX5_EQC_ST_FIRED = 0xa, 4173 }; 4174 4175 struct mlx5_ifc_eqc_bits { 4176 u8 status[0x4]; 4177 u8 reserved_at_4[0x9]; 4178 u8 ec[0x1]; 4179 u8 oi[0x1]; 4180 u8 reserved_at_f[0x5]; 4181 u8 st[0x4]; 4182 u8 reserved_at_18[0x8]; 4183 4184 u8 reserved_at_20[0x20]; 4185 4186 u8 reserved_at_40[0x14]; 4187 u8 page_offset[0x6]; 4188 u8 reserved_at_5a[0x6]; 4189 4190 u8 reserved_at_60[0x3]; 4191 u8 log_eq_size[0x5]; 4192 u8 uar_page[0x18]; 4193 4194 u8 reserved_at_80[0x20]; 4195 4196 u8 reserved_at_a0[0x14]; 4197 u8 intr[0xc]; 4198 4199 u8 reserved_at_c0[0x3]; 4200 u8 log_page_size[0x5]; 4201 u8 reserved_at_c8[0x18]; 4202 4203 u8 reserved_at_e0[0x60]; 4204 4205 u8 reserved_at_140[0x8]; 4206 u8 consumer_counter[0x18]; 4207 4208 u8 reserved_at_160[0x8]; 4209 u8 producer_counter[0x18]; 4210 4211 u8 reserved_at_180[0x80]; 4212 }; 4213 4214 enum { 4215 MLX5_DCTC_STATE_ACTIVE = 0x0, 4216 MLX5_DCTC_STATE_DRAINING = 0x1, 4217 MLX5_DCTC_STATE_DRAINED = 0x2, 4218 }; 4219 4220 enum { 4221 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4222 MLX5_DCTC_CS_RES_NA = 0x1, 4223 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4224 }; 4225 4226 enum { 4227 MLX5_DCTC_MTU_256_BYTES = 0x1, 4228 MLX5_DCTC_MTU_512_BYTES = 0x2, 4229 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4230 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4231 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4232 }; 4233 4234 struct mlx5_ifc_dctc_bits { 4235 u8 reserved_at_0[0x4]; 4236 u8 state[0x4]; 4237 u8 reserved_at_8[0x18]; 4238 4239 u8 reserved_at_20[0x8]; 4240 u8 user_index[0x18]; 4241 4242 u8 reserved_at_40[0x8]; 4243 u8 cqn[0x18]; 4244 4245 u8 counter_set_id[0x8]; 4246 u8 atomic_mode[0x4]; 4247 u8 rre[0x1]; 4248 u8 rwe[0x1]; 4249 u8 rae[0x1]; 4250 u8 atomic_like_write_en[0x1]; 4251 u8 latency_sensitive[0x1]; 4252 u8 rlky[0x1]; 4253 u8 free_ar[0x1]; 4254 u8 reserved_at_73[0xd]; 4255 4256 u8 reserved_at_80[0x8]; 4257 u8 cs_res[0x8]; 4258 u8 reserved_at_90[0x3]; 4259 u8 min_rnr_nak[0x5]; 4260 u8 reserved_at_98[0x8]; 4261 4262 u8 reserved_at_a0[0x8]; 4263 u8 srqn_xrqn[0x18]; 4264 4265 u8 reserved_at_c0[0x8]; 4266 u8 pd[0x18]; 4267 4268 u8 tclass[0x8]; 4269 u8 reserved_at_e8[0x4]; 4270 u8 flow_label[0x14]; 4271 4272 u8 dc_access_key[0x40]; 4273 4274 u8 reserved_at_140[0x5]; 4275 u8 mtu[0x3]; 4276 u8 port[0x8]; 4277 u8 pkey_index[0x10]; 4278 4279 u8 reserved_at_160[0x8]; 4280 u8 my_addr_index[0x8]; 4281 u8 reserved_at_170[0x8]; 4282 u8 hop_limit[0x8]; 4283 4284 u8 dc_access_key_violation_count[0x20]; 4285 4286 u8 reserved_at_1a0[0x14]; 4287 u8 dei_cfi[0x1]; 4288 u8 eth_prio[0x3]; 4289 u8 ecn[0x2]; 4290 u8 dscp[0x6]; 4291 4292 u8 reserved_at_1c0[0x20]; 4293 u8 ece[0x20]; 4294 }; 4295 4296 enum { 4297 MLX5_CQC_STATUS_OK = 0x0, 4298 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4299 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4300 }; 4301 4302 enum { 4303 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4304 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4305 }; 4306 4307 enum { 4308 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4309 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4310 MLX5_CQC_ST_FIRED = 0xa, 4311 }; 4312 4313 enum { 4314 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4315 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4316 MLX5_CQ_PERIOD_NUM_MODES 4317 }; 4318 4319 struct mlx5_ifc_cqc_bits { 4320 u8 status[0x4]; 4321 u8 reserved_at_4[0x2]; 4322 u8 dbr_umem_valid[0x1]; 4323 u8 apu_cq[0x1]; 4324 u8 cqe_sz[0x3]; 4325 u8 cc[0x1]; 4326 u8 reserved_at_c[0x1]; 4327 u8 scqe_break_moderation_en[0x1]; 4328 u8 oi[0x1]; 4329 u8 cq_period_mode[0x2]; 4330 u8 cqe_comp_en[0x1]; 4331 u8 mini_cqe_res_format[0x2]; 4332 u8 st[0x4]; 4333 u8 reserved_at_18[0x6]; 4334 u8 cqe_compression_layout[0x2]; 4335 4336 u8 reserved_at_20[0x20]; 4337 4338 u8 reserved_at_40[0x14]; 4339 u8 page_offset[0x6]; 4340 u8 reserved_at_5a[0x6]; 4341 4342 u8 reserved_at_60[0x3]; 4343 u8 log_cq_size[0x5]; 4344 u8 uar_page[0x18]; 4345 4346 u8 reserved_at_80[0x4]; 4347 u8 cq_period[0xc]; 4348 u8 cq_max_count[0x10]; 4349 4350 u8 c_eqn_or_apu_element[0x20]; 4351 4352 u8 reserved_at_c0[0x3]; 4353 u8 log_page_size[0x5]; 4354 u8 reserved_at_c8[0x18]; 4355 4356 u8 reserved_at_e0[0x20]; 4357 4358 u8 reserved_at_100[0x8]; 4359 u8 last_notified_index[0x18]; 4360 4361 u8 reserved_at_120[0x8]; 4362 u8 last_solicit_index[0x18]; 4363 4364 u8 reserved_at_140[0x8]; 4365 u8 consumer_counter[0x18]; 4366 4367 u8 reserved_at_160[0x8]; 4368 u8 producer_counter[0x18]; 4369 4370 u8 reserved_at_180[0x40]; 4371 4372 u8 dbr_addr[0x40]; 4373 }; 4374 4375 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4376 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4377 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4378 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4379 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4380 u8 reserved_at_0[0x800]; 4381 }; 4382 4383 struct mlx5_ifc_query_adapter_param_block_bits { 4384 u8 reserved_at_0[0xc0]; 4385 4386 u8 reserved_at_c0[0x8]; 4387 u8 ieee_vendor_id[0x18]; 4388 4389 u8 reserved_at_e0[0x10]; 4390 u8 vsd_vendor_id[0x10]; 4391 4392 u8 vsd[208][0x8]; 4393 4394 u8 vsd_contd_psid[16][0x8]; 4395 }; 4396 4397 enum { 4398 MLX5_XRQC_STATE_GOOD = 0x0, 4399 MLX5_XRQC_STATE_ERROR = 0x1, 4400 }; 4401 4402 enum { 4403 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4404 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4405 }; 4406 4407 enum { 4408 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4409 }; 4410 4411 struct mlx5_ifc_tag_matching_topology_context_bits { 4412 u8 log_matching_list_sz[0x4]; 4413 u8 reserved_at_4[0xc]; 4414 u8 append_next_index[0x10]; 4415 4416 u8 sw_phase_cnt[0x10]; 4417 u8 hw_phase_cnt[0x10]; 4418 4419 u8 reserved_at_40[0x40]; 4420 }; 4421 4422 struct mlx5_ifc_xrqc_bits { 4423 u8 state[0x4]; 4424 u8 rlkey[0x1]; 4425 u8 reserved_at_5[0xf]; 4426 u8 topology[0x4]; 4427 u8 reserved_at_18[0x4]; 4428 u8 offload[0x4]; 4429 4430 u8 reserved_at_20[0x8]; 4431 u8 user_index[0x18]; 4432 4433 u8 reserved_at_40[0x8]; 4434 u8 cqn[0x18]; 4435 4436 u8 reserved_at_60[0xa0]; 4437 4438 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4439 4440 u8 reserved_at_180[0x280]; 4441 4442 struct mlx5_ifc_wq_bits wq; 4443 }; 4444 4445 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4446 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4447 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4448 u8 reserved_at_0[0x20]; 4449 }; 4450 4451 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4452 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4453 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4454 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4455 u8 reserved_at_0[0x20]; 4456 }; 4457 4458 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4459 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4460 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4461 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4462 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4463 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4464 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4465 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4466 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4467 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4468 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4469 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4470 u8 reserved_at_0[0x7c0]; 4471 }; 4472 4473 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4474 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4475 u8 reserved_at_0[0x7c0]; 4476 }; 4477 4478 union mlx5_ifc_event_auto_bits { 4479 struct mlx5_ifc_comp_event_bits comp_event; 4480 struct mlx5_ifc_dct_events_bits dct_events; 4481 struct mlx5_ifc_qp_events_bits qp_events; 4482 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4483 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4484 struct mlx5_ifc_cq_error_bits cq_error; 4485 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4486 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4487 struct mlx5_ifc_gpio_event_bits gpio_event; 4488 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4489 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4490 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4491 u8 reserved_at_0[0xe0]; 4492 }; 4493 4494 struct mlx5_ifc_health_buffer_bits { 4495 u8 reserved_at_0[0x100]; 4496 4497 u8 assert_existptr[0x20]; 4498 4499 u8 assert_callra[0x20]; 4500 4501 u8 reserved_at_140[0x20]; 4502 4503 u8 time[0x20]; 4504 4505 u8 fw_version[0x20]; 4506 4507 u8 hw_id[0x20]; 4508 4509 u8 rfr[0x1]; 4510 u8 reserved_at_1c1[0x3]; 4511 u8 valid[0x1]; 4512 u8 severity[0x3]; 4513 u8 reserved_at_1c8[0x18]; 4514 4515 u8 irisc_index[0x8]; 4516 u8 synd[0x8]; 4517 u8 ext_synd[0x10]; 4518 }; 4519 4520 struct mlx5_ifc_register_loopback_control_bits { 4521 u8 no_lb[0x1]; 4522 u8 reserved_at_1[0x7]; 4523 u8 port[0x8]; 4524 u8 reserved_at_10[0x10]; 4525 4526 u8 reserved_at_20[0x60]; 4527 }; 4528 4529 struct mlx5_ifc_vport_tc_element_bits { 4530 u8 traffic_class[0x4]; 4531 u8 reserved_at_4[0xc]; 4532 u8 vport_number[0x10]; 4533 }; 4534 4535 struct mlx5_ifc_vport_element_bits { 4536 u8 reserved_at_0[0x10]; 4537 u8 vport_number[0x10]; 4538 }; 4539 4540 enum { 4541 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4542 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4543 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4544 }; 4545 4546 struct mlx5_ifc_tsar_element_bits { 4547 u8 reserved_at_0[0x8]; 4548 u8 tsar_type[0x8]; 4549 u8 reserved_at_10[0x10]; 4550 }; 4551 4552 enum { 4553 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4554 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4555 }; 4556 4557 struct mlx5_ifc_teardown_hca_out_bits { 4558 u8 status[0x8]; 4559 u8 reserved_at_8[0x18]; 4560 4561 u8 syndrome[0x20]; 4562 4563 u8 reserved_at_40[0x3f]; 4564 4565 u8 state[0x1]; 4566 }; 4567 4568 enum { 4569 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4570 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4571 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4572 }; 4573 4574 struct mlx5_ifc_teardown_hca_in_bits { 4575 u8 opcode[0x10]; 4576 u8 reserved_at_10[0x10]; 4577 4578 u8 reserved_at_20[0x10]; 4579 u8 op_mod[0x10]; 4580 4581 u8 reserved_at_40[0x10]; 4582 u8 profile[0x10]; 4583 4584 u8 reserved_at_60[0x20]; 4585 }; 4586 4587 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4588 u8 status[0x8]; 4589 u8 reserved_at_8[0x18]; 4590 4591 u8 syndrome[0x20]; 4592 4593 u8 reserved_at_40[0x40]; 4594 }; 4595 4596 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4597 u8 opcode[0x10]; 4598 u8 uid[0x10]; 4599 4600 u8 reserved_at_20[0x10]; 4601 u8 op_mod[0x10]; 4602 4603 u8 reserved_at_40[0x8]; 4604 u8 qpn[0x18]; 4605 4606 u8 reserved_at_60[0x20]; 4607 4608 u8 opt_param_mask[0x20]; 4609 4610 u8 reserved_at_a0[0x20]; 4611 4612 struct mlx5_ifc_qpc_bits qpc; 4613 4614 u8 reserved_at_800[0x80]; 4615 }; 4616 4617 struct mlx5_ifc_sqd2rts_qp_out_bits { 4618 u8 status[0x8]; 4619 u8 reserved_at_8[0x18]; 4620 4621 u8 syndrome[0x20]; 4622 4623 u8 reserved_at_40[0x40]; 4624 }; 4625 4626 struct mlx5_ifc_sqd2rts_qp_in_bits { 4627 u8 opcode[0x10]; 4628 u8 uid[0x10]; 4629 4630 u8 reserved_at_20[0x10]; 4631 u8 op_mod[0x10]; 4632 4633 u8 reserved_at_40[0x8]; 4634 u8 qpn[0x18]; 4635 4636 u8 reserved_at_60[0x20]; 4637 4638 u8 opt_param_mask[0x20]; 4639 4640 u8 reserved_at_a0[0x20]; 4641 4642 struct mlx5_ifc_qpc_bits qpc; 4643 4644 u8 reserved_at_800[0x80]; 4645 }; 4646 4647 struct mlx5_ifc_set_roce_address_out_bits { 4648 u8 status[0x8]; 4649 u8 reserved_at_8[0x18]; 4650 4651 u8 syndrome[0x20]; 4652 4653 u8 reserved_at_40[0x40]; 4654 }; 4655 4656 struct mlx5_ifc_set_roce_address_in_bits { 4657 u8 opcode[0x10]; 4658 u8 reserved_at_10[0x10]; 4659 4660 u8 reserved_at_20[0x10]; 4661 u8 op_mod[0x10]; 4662 4663 u8 roce_address_index[0x10]; 4664 u8 reserved_at_50[0xc]; 4665 u8 vhca_port_num[0x4]; 4666 4667 u8 reserved_at_60[0x20]; 4668 4669 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4670 }; 4671 4672 struct mlx5_ifc_set_mad_demux_out_bits { 4673 u8 status[0x8]; 4674 u8 reserved_at_8[0x18]; 4675 4676 u8 syndrome[0x20]; 4677 4678 u8 reserved_at_40[0x40]; 4679 }; 4680 4681 enum { 4682 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4683 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4684 }; 4685 4686 struct mlx5_ifc_set_mad_demux_in_bits { 4687 u8 opcode[0x10]; 4688 u8 reserved_at_10[0x10]; 4689 4690 u8 reserved_at_20[0x10]; 4691 u8 op_mod[0x10]; 4692 4693 u8 reserved_at_40[0x20]; 4694 4695 u8 reserved_at_60[0x6]; 4696 u8 demux_mode[0x2]; 4697 u8 reserved_at_68[0x18]; 4698 }; 4699 4700 struct mlx5_ifc_set_l2_table_entry_out_bits { 4701 u8 status[0x8]; 4702 u8 reserved_at_8[0x18]; 4703 4704 u8 syndrome[0x20]; 4705 4706 u8 reserved_at_40[0x40]; 4707 }; 4708 4709 struct mlx5_ifc_set_l2_table_entry_in_bits { 4710 u8 opcode[0x10]; 4711 u8 reserved_at_10[0x10]; 4712 4713 u8 reserved_at_20[0x10]; 4714 u8 op_mod[0x10]; 4715 4716 u8 reserved_at_40[0x60]; 4717 4718 u8 reserved_at_a0[0x8]; 4719 u8 table_index[0x18]; 4720 4721 u8 reserved_at_c0[0x20]; 4722 4723 u8 reserved_at_e0[0x13]; 4724 u8 vlan_valid[0x1]; 4725 u8 vlan[0xc]; 4726 4727 struct mlx5_ifc_mac_address_layout_bits mac_address; 4728 4729 u8 reserved_at_140[0xc0]; 4730 }; 4731 4732 struct mlx5_ifc_set_issi_out_bits { 4733 u8 status[0x8]; 4734 u8 reserved_at_8[0x18]; 4735 4736 u8 syndrome[0x20]; 4737 4738 u8 reserved_at_40[0x40]; 4739 }; 4740 4741 struct mlx5_ifc_set_issi_in_bits { 4742 u8 opcode[0x10]; 4743 u8 reserved_at_10[0x10]; 4744 4745 u8 reserved_at_20[0x10]; 4746 u8 op_mod[0x10]; 4747 4748 u8 reserved_at_40[0x10]; 4749 u8 current_issi[0x10]; 4750 4751 u8 reserved_at_60[0x20]; 4752 }; 4753 4754 struct mlx5_ifc_set_hca_cap_out_bits { 4755 u8 status[0x8]; 4756 u8 reserved_at_8[0x18]; 4757 4758 u8 syndrome[0x20]; 4759 4760 u8 reserved_at_40[0x40]; 4761 }; 4762 4763 struct mlx5_ifc_set_hca_cap_in_bits { 4764 u8 opcode[0x10]; 4765 u8 reserved_at_10[0x10]; 4766 4767 u8 reserved_at_20[0x10]; 4768 u8 op_mod[0x10]; 4769 4770 u8 other_function[0x1]; 4771 u8 ec_vf_function[0x1]; 4772 u8 reserved_at_42[0xe]; 4773 u8 function_id[0x10]; 4774 4775 u8 reserved_at_60[0x20]; 4776 4777 union mlx5_ifc_hca_cap_union_bits capability; 4778 }; 4779 4780 enum { 4781 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4782 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4783 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4784 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4785 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4786 }; 4787 4788 struct mlx5_ifc_set_fte_out_bits { 4789 u8 status[0x8]; 4790 u8 reserved_at_8[0x18]; 4791 4792 u8 syndrome[0x20]; 4793 4794 u8 reserved_at_40[0x40]; 4795 }; 4796 4797 struct mlx5_ifc_set_fte_in_bits { 4798 u8 opcode[0x10]; 4799 u8 reserved_at_10[0x10]; 4800 4801 u8 reserved_at_20[0x10]; 4802 u8 op_mod[0x10]; 4803 4804 u8 other_vport[0x1]; 4805 u8 reserved_at_41[0xf]; 4806 u8 vport_number[0x10]; 4807 4808 u8 reserved_at_60[0x20]; 4809 4810 u8 table_type[0x8]; 4811 u8 reserved_at_88[0x18]; 4812 4813 u8 reserved_at_a0[0x8]; 4814 u8 table_id[0x18]; 4815 4816 u8 ignore_flow_level[0x1]; 4817 u8 reserved_at_c1[0x17]; 4818 u8 modify_enable_mask[0x8]; 4819 4820 u8 reserved_at_e0[0x20]; 4821 4822 u8 flow_index[0x20]; 4823 4824 u8 reserved_at_120[0xe0]; 4825 4826 struct mlx5_ifc_flow_context_bits flow_context; 4827 }; 4828 4829 struct mlx5_ifc_rts2rts_qp_out_bits { 4830 u8 status[0x8]; 4831 u8 reserved_at_8[0x18]; 4832 4833 u8 syndrome[0x20]; 4834 4835 u8 reserved_at_40[0x20]; 4836 u8 ece[0x20]; 4837 }; 4838 4839 struct mlx5_ifc_rts2rts_qp_in_bits { 4840 u8 opcode[0x10]; 4841 u8 uid[0x10]; 4842 4843 u8 reserved_at_20[0x10]; 4844 u8 op_mod[0x10]; 4845 4846 u8 reserved_at_40[0x8]; 4847 u8 qpn[0x18]; 4848 4849 u8 reserved_at_60[0x20]; 4850 4851 u8 opt_param_mask[0x20]; 4852 4853 u8 ece[0x20]; 4854 4855 struct mlx5_ifc_qpc_bits qpc; 4856 4857 u8 reserved_at_800[0x80]; 4858 }; 4859 4860 struct mlx5_ifc_rtr2rts_qp_out_bits { 4861 u8 status[0x8]; 4862 u8 reserved_at_8[0x18]; 4863 4864 u8 syndrome[0x20]; 4865 4866 u8 reserved_at_40[0x20]; 4867 u8 ece[0x20]; 4868 }; 4869 4870 struct mlx5_ifc_rtr2rts_qp_in_bits { 4871 u8 opcode[0x10]; 4872 u8 uid[0x10]; 4873 4874 u8 reserved_at_20[0x10]; 4875 u8 op_mod[0x10]; 4876 4877 u8 reserved_at_40[0x8]; 4878 u8 qpn[0x18]; 4879 4880 u8 reserved_at_60[0x20]; 4881 4882 u8 opt_param_mask[0x20]; 4883 4884 u8 ece[0x20]; 4885 4886 struct mlx5_ifc_qpc_bits qpc; 4887 4888 u8 reserved_at_800[0x80]; 4889 }; 4890 4891 struct mlx5_ifc_rst2init_qp_out_bits { 4892 u8 status[0x8]; 4893 u8 reserved_at_8[0x18]; 4894 4895 u8 syndrome[0x20]; 4896 4897 u8 reserved_at_40[0x20]; 4898 u8 ece[0x20]; 4899 }; 4900 4901 struct mlx5_ifc_rst2init_qp_in_bits { 4902 u8 opcode[0x10]; 4903 u8 uid[0x10]; 4904 4905 u8 reserved_at_20[0x10]; 4906 u8 op_mod[0x10]; 4907 4908 u8 reserved_at_40[0x8]; 4909 u8 qpn[0x18]; 4910 4911 u8 reserved_at_60[0x20]; 4912 4913 u8 opt_param_mask[0x20]; 4914 4915 u8 ece[0x20]; 4916 4917 struct mlx5_ifc_qpc_bits qpc; 4918 4919 u8 reserved_at_800[0x80]; 4920 }; 4921 4922 struct mlx5_ifc_query_xrq_out_bits { 4923 u8 status[0x8]; 4924 u8 reserved_at_8[0x18]; 4925 4926 u8 syndrome[0x20]; 4927 4928 u8 reserved_at_40[0x40]; 4929 4930 struct mlx5_ifc_xrqc_bits xrq_context; 4931 }; 4932 4933 struct mlx5_ifc_query_xrq_in_bits { 4934 u8 opcode[0x10]; 4935 u8 reserved_at_10[0x10]; 4936 4937 u8 reserved_at_20[0x10]; 4938 u8 op_mod[0x10]; 4939 4940 u8 reserved_at_40[0x8]; 4941 u8 xrqn[0x18]; 4942 4943 u8 reserved_at_60[0x20]; 4944 }; 4945 4946 struct mlx5_ifc_query_xrc_srq_out_bits { 4947 u8 status[0x8]; 4948 u8 reserved_at_8[0x18]; 4949 4950 u8 syndrome[0x20]; 4951 4952 u8 reserved_at_40[0x40]; 4953 4954 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4955 4956 u8 reserved_at_280[0x600]; 4957 4958 u8 pas[][0x40]; 4959 }; 4960 4961 struct mlx5_ifc_query_xrc_srq_in_bits { 4962 u8 opcode[0x10]; 4963 u8 reserved_at_10[0x10]; 4964 4965 u8 reserved_at_20[0x10]; 4966 u8 op_mod[0x10]; 4967 4968 u8 reserved_at_40[0x8]; 4969 u8 xrc_srqn[0x18]; 4970 4971 u8 reserved_at_60[0x20]; 4972 }; 4973 4974 enum { 4975 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4976 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4977 }; 4978 4979 struct mlx5_ifc_query_vport_state_out_bits { 4980 u8 status[0x8]; 4981 u8 reserved_at_8[0x18]; 4982 4983 u8 syndrome[0x20]; 4984 4985 u8 reserved_at_40[0x20]; 4986 4987 u8 reserved_at_60[0x18]; 4988 u8 admin_state[0x4]; 4989 u8 state[0x4]; 4990 }; 4991 4992 enum { 4993 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4994 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4995 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4996 }; 4997 4998 struct mlx5_ifc_arm_monitor_counter_in_bits { 4999 u8 opcode[0x10]; 5000 u8 uid[0x10]; 5001 5002 u8 reserved_at_20[0x10]; 5003 u8 op_mod[0x10]; 5004 5005 u8 reserved_at_40[0x20]; 5006 5007 u8 reserved_at_60[0x20]; 5008 }; 5009 5010 struct mlx5_ifc_arm_monitor_counter_out_bits { 5011 u8 status[0x8]; 5012 u8 reserved_at_8[0x18]; 5013 5014 u8 syndrome[0x20]; 5015 5016 u8 reserved_at_40[0x40]; 5017 }; 5018 5019 enum { 5020 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5021 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5022 }; 5023 5024 enum mlx5_monitor_counter_ppcnt { 5025 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5026 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5027 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5028 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5029 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5030 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5031 }; 5032 5033 enum { 5034 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5035 }; 5036 5037 struct mlx5_ifc_monitor_counter_output_bits { 5038 u8 reserved_at_0[0x4]; 5039 u8 type[0x4]; 5040 u8 reserved_at_8[0x8]; 5041 u8 counter[0x10]; 5042 5043 u8 counter_group_id[0x20]; 5044 }; 5045 5046 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5047 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5048 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5049 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5050 5051 struct mlx5_ifc_set_monitor_counter_in_bits { 5052 u8 opcode[0x10]; 5053 u8 uid[0x10]; 5054 5055 u8 reserved_at_20[0x10]; 5056 u8 op_mod[0x10]; 5057 5058 u8 reserved_at_40[0x10]; 5059 u8 num_of_counters[0x10]; 5060 5061 u8 reserved_at_60[0x20]; 5062 5063 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5064 }; 5065 5066 struct mlx5_ifc_set_monitor_counter_out_bits { 5067 u8 status[0x8]; 5068 u8 reserved_at_8[0x18]; 5069 5070 u8 syndrome[0x20]; 5071 5072 u8 reserved_at_40[0x40]; 5073 }; 5074 5075 struct mlx5_ifc_query_vport_state_in_bits { 5076 u8 opcode[0x10]; 5077 u8 reserved_at_10[0x10]; 5078 5079 u8 reserved_at_20[0x10]; 5080 u8 op_mod[0x10]; 5081 5082 u8 other_vport[0x1]; 5083 u8 reserved_at_41[0xf]; 5084 u8 vport_number[0x10]; 5085 5086 u8 reserved_at_60[0x20]; 5087 }; 5088 5089 struct mlx5_ifc_query_vnic_env_out_bits { 5090 u8 status[0x8]; 5091 u8 reserved_at_8[0x18]; 5092 5093 u8 syndrome[0x20]; 5094 5095 u8 reserved_at_40[0x40]; 5096 5097 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5098 }; 5099 5100 enum { 5101 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5102 }; 5103 5104 struct mlx5_ifc_query_vnic_env_in_bits { 5105 u8 opcode[0x10]; 5106 u8 reserved_at_10[0x10]; 5107 5108 u8 reserved_at_20[0x10]; 5109 u8 op_mod[0x10]; 5110 5111 u8 other_vport[0x1]; 5112 u8 reserved_at_41[0xf]; 5113 u8 vport_number[0x10]; 5114 5115 u8 reserved_at_60[0x20]; 5116 }; 5117 5118 struct mlx5_ifc_query_vport_counter_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x40]; 5125 5126 struct mlx5_ifc_traffic_counter_bits received_errors; 5127 5128 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5129 5130 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5131 5132 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5133 5134 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5135 5136 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5137 5138 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5139 5140 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5141 5142 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5143 5144 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5145 5146 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5147 5148 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5149 5150 struct mlx5_ifc_traffic_counter_bits local_loopback; 5151 5152 u8 reserved_at_700[0x980]; 5153 }; 5154 5155 enum { 5156 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5157 }; 5158 5159 struct mlx5_ifc_query_vport_counter_in_bits { 5160 u8 opcode[0x10]; 5161 u8 reserved_at_10[0x10]; 5162 5163 u8 reserved_at_20[0x10]; 5164 u8 op_mod[0x10]; 5165 5166 u8 other_vport[0x1]; 5167 u8 reserved_at_41[0xb]; 5168 u8 port_num[0x4]; 5169 u8 vport_number[0x10]; 5170 5171 u8 reserved_at_60[0x60]; 5172 5173 u8 clear[0x1]; 5174 u8 reserved_at_c1[0x1f]; 5175 5176 u8 reserved_at_e0[0x20]; 5177 }; 5178 5179 struct mlx5_ifc_query_tis_out_bits { 5180 u8 status[0x8]; 5181 u8 reserved_at_8[0x18]; 5182 5183 u8 syndrome[0x20]; 5184 5185 u8 reserved_at_40[0x40]; 5186 5187 struct mlx5_ifc_tisc_bits tis_context; 5188 }; 5189 5190 struct mlx5_ifc_query_tis_in_bits { 5191 u8 opcode[0x10]; 5192 u8 reserved_at_10[0x10]; 5193 5194 u8 reserved_at_20[0x10]; 5195 u8 op_mod[0x10]; 5196 5197 u8 reserved_at_40[0x8]; 5198 u8 tisn[0x18]; 5199 5200 u8 reserved_at_60[0x20]; 5201 }; 5202 5203 struct mlx5_ifc_query_tir_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_at_8[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_at_40[0xc0]; 5210 5211 struct mlx5_ifc_tirc_bits tir_context; 5212 }; 5213 5214 struct mlx5_ifc_query_tir_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_at_10[0x10]; 5217 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 reserved_at_40[0x8]; 5222 u8 tirn[0x18]; 5223 5224 u8 reserved_at_60[0x20]; 5225 }; 5226 5227 struct mlx5_ifc_query_srq_out_bits { 5228 u8 status[0x8]; 5229 u8 reserved_at_8[0x18]; 5230 5231 u8 syndrome[0x20]; 5232 5233 u8 reserved_at_40[0x40]; 5234 5235 struct mlx5_ifc_srqc_bits srq_context_entry; 5236 5237 u8 reserved_at_280[0x600]; 5238 5239 u8 pas[][0x40]; 5240 }; 5241 5242 struct mlx5_ifc_query_srq_in_bits { 5243 u8 opcode[0x10]; 5244 u8 reserved_at_10[0x10]; 5245 5246 u8 reserved_at_20[0x10]; 5247 u8 op_mod[0x10]; 5248 5249 u8 reserved_at_40[0x8]; 5250 u8 srqn[0x18]; 5251 5252 u8 reserved_at_60[0x20]; 5253 }; 5254 5255 struct mlx5_ifc_query_sq_out_bits { 5256 u8 status[0x8]; 5257 u8 reserved_at_8[0x18]; 5258 5259 u8 syndrome[0x20]; 5260 5261 u8 reserved_at_40[0xc0]; 5262 5263 struct mlx5_ifc_sqc_bits sq_context; 5264 }; 5265 5266 struct mlx5_ifc_query_sq_in_bits { 5267 u8 opcode[0x10]; 5268 u8 reserved_at_10[0x10]; 5269 5270 u8 reserved_at_20[0x10]; 5271 u8 op_mod[0x10]; 5272 5273 u8 reserved_at_40[0x8]; 5274 u8 sqn[0x18]; 5275 5276 u8 reserved_at_60[0x20]; 5277 }; 5278 5279 struct mlx5_ifc_query_special_contexts_out_bits { 5280 u8 status[0x8]; 5281 u8 reserved_at_8[0x18]; 5282 5283 u8 syndrome[0x20]; 5284 5285 u8 dump_fill_mkey[0x20]; 5286 5287 u8 resd_lkey[0x20]; 5288 5289 u8 null_mkey[0x20]; 5290 5291 u8 terminate_scatter_list_mkey[0x20]; 5292 5293 u8 repeated_mkey[0x20]; 5294 5295 u8 reserved_at_a0[0x20]; 5296 }; 5297 5298 struct mlx5_ifc_query_special_contexts_in_bits { 5299 u8 opcode[0x10]; 5300 u8 reserved_at_10[0x10]; 5301 5302 u8 reserved_at_20[0x10]; 5303 u8 op_mod[0x10]; 5304 5305 u8 reserved_at_40[0x40]; 5306 }; 5307 5308 struct mlx5_ifc_query_scheduling_element_out_bits { 5309 u8 opcode[0x10]; 5310 u8 reserved_at_10[0x10]; 5311 5312 u8 reserved_at_20[0x10]; 5313 u8 op_mod[0x10]; 5314 5315 u8 reserved_at_40[0xc0]; 5316 5317 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5318 5319 u8 reserved_at_300[0x100]; 5320 }; 5321 5322 enum { 5323 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5324 SCHEDULING_HIERARCHY_NIC = 0x3, 5325 }; 5326 5327 struct mlx5_ifc_query_scheduling_element_in_bits { 5328 u8 opcode[0x10]; 5329 u8 reserved_at_10[0x10]; 5330 5331 u8 reserved_at_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 scheduling_hierarchy[0x8]; 5335 u8 reserved_at_48[0x18]; 5336 5337 u8 scheduling_element_id[0x20]; 5338 5339 u8 reserved_at_80[0x180]; 5340 }; 5341 5342 struct mlx5_ifc_query_rqt_out_bits { 5343 u8 status[0x8]; 5344 u8 reserved_at_8[0x18]; 5345 5346 u8 syndrome[0x20]; 5347 5348 u8 reserved_at_40[0xc0]; 5349 5350 struct mlx5_ifc_rqtc_bits rqt_context; 5351 }; 5352 5353 struct mlx5_ifc_query_rqt_in_bits { 5354 u8 opcode[0x10]; 5355 u8 reserved_at_10[0x10]; 5356 5357 u8 reserved_at_20[0x10]; 5358 u8 op_mod[0x10]; 5359 5360 u8 reserved_at_40[0x8]; 5361 u8 rqtn[0x18]; 5362 5363 u8 reserved_at_60[0x20]; 5364 }; 5365 5366 struct mlx5_ifc_query_rq_out_bits { 5367 u8 status[0x8]; 5368 u8 reserved_at_8[0x18]; 5369 5370 u8 syndrome[0x20]; 5371 5372 u8 reserved_at_40[0xc0]; 5373 5374 struct mlx5_ifc_rqc_bits rq_context; 5375 }; 5376 5377 struct mlx5_ifc_query_rq_in_bits { 5378 u8 opcode[0x10]; 5379 u8 reserved_at_10[0x10]; 5380 5381 u8 reserved_at_20[0x10]; 5382 u8 op_mod[0x10]; 5383 5384 u8 reserved_at_40[0x8]; 5385 u8 rqn[0x18]; 5386 5387 u8 reserved_at_60[0x20]; 5388 }; 5389 5390 struct mlx5_ifc_query_roce_address_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_at_8[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_at_40[0x40]; 5397 5398 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5399 }; 5400 5401 struct mlx5_ifc_query_roce_address_in_bits { 5402 u8 opcode[0x10]; 5403 u8 reserved_at_10[0x10]; 5404 5405 u8 reserved_at_20[0x10]; 5406 u8 op_mod[0x10]; 5407 5408 u8 roce_address_index[0x10]; 5409 u8 reserved_at_50[0xc]; 5410 u8 vhca_port_num[0x4]; 5411 5412 u8 reserved_at_60[0x20]; 5413 }; 5414 5415 struct mlx5_ifc_query_rmp_out_bits { 5416 u8 status[0x8]; 5417 u8 reserved_at_8[0x18]; 5418 5419 u8 syndrome[0x20]; 5420 5421 u8 reserved_at_40[0xc0]; 5422 5423 struct mlx5_ifc_rmpc_bits rmp_context; 5424 }; 5425 5426 struct mlx5_ifc_query_rmp_in_bits { 5427 u8 opcode[0x10]; 5428 u8 reserved_at_10[0x10]; 5429 5430 u8 reserved_at_20[0x10]; 5431 u8 op_mod[0x10]; 5432 5433 u8 reserved_at_40[0x8]; 5434 u8 rmpn[0x18]; 5435 5436 u8 reserved_at_60[0x20]; 5437 }; 5438 5439 struct mlx5_ifc_cqe_error_syndrome_bits { 5440 u8 hw_error_syndrome[0x8]; 5441 u8 hw_syndrome_type[0x4]; 5442 u8 reserved_at_c[0x4]; 5443 u8 vendor_error_syndrome[0x8]; 5444 u8 syndrome[0x8]; 5445 }; 5446 5447 struct mlx5_ifc_qp_context_extension_bits { 5448 u8 reserved_at_0[0x60]; 5449 5450 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5451 5452 u8 reserved_at_80[0x580]; 5453 }; 5454 5455 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5456 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5457 5458 u8 pas[0][0x40]; 5459 }; 5460 5461 struct mlx5_ifc_qp_pas_list_in_bits { 5462 struct mlx5_ifc_cmd_pas_bits pas[0]; 5463 }; 5464 5465 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5466 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5467 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5468 }; 5469 5470 struct mlx5_ifc_query_qp_out_bits { 5471 u8 status[0x8]; 5472 u8 reserved_at_8[0x18]; 5473 5474 u8 syndrome[0x20]; 5475 5476 u8 reserved_at_40[0x40]; 5477 5478 u8 opt_param_mask[0x20]; 5479 5480 u8 ece[0x20]; 5481 5482 struct mlx5_ifc_qpc_bits qpc; 5483 5484 u8 reserved_at_800[0x80]; 5485 5486 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5487 }; 5488 5489 struct mlx5_ifc_query_qp_in_bits { 5490 u8 opcode[0x10]; 5491 u8 reserved_at_10[0x10]; 5492 5493 u8 reserved_at_20[0x10]; 5494 u8 op_mod[0x10]; 5495 5496 u8 qpc_ext[0x1]; 5497 u8 reserved_at_41[0x7]; 5498 u8 qpn[0x18]; 5499 5500 u8 reserved_at_60[0x20]; 5501 }; 5502 5503 struct mlx5_ifc_query_q_counter_out_bits { 5504 u8 status[0x8]; 5505 u8 reserved_at_8[0x18]; 5506 5507 u8 syndrome[0x20]; 5508 5509 u8 reserved_at_40[0x40]; 5510 5511 u8 rx_write_requests[0x20]; 5512 5513 u8 reserved_at_a0[0x20]; 5514 5515 u8 rx_read_requests[0x20]; 5516 5517 u8 reserved_at_e0[0x20]; 5518 5519 u8 rx_atomic_requests[0x20]; 5520 5521 u8 reserved_at_120[0x20]; 5522 5523 u8 rx_dct_connect[0x20]; 5524 5525 u8 reserved_at_160[0x20]; 5526 5527 u8 out_of_buffer[0x20]; 5528 5529 u8 reserved_at_1a0[0x20]; 5530 5531 u8 out_of_sequence[0x20]; 5532 5533 u8 reserved_at_1e0[0x20]; 5534 5535 u8 duplicate_request[0x20]; 5536 5537 u8 reserved_at_220[0x20]; 5538 5539 u8 rnr_nak_retry_err[0x20]; 5540 5541 u8 reserved_at_260[0x20]; 5542 5543 u8 packet_seq_err[0x20]; 5544 5545 u8 reserved_at_2a0[0x20]; 5546 5547 u8 implied_nak_seq_err[0x20]; 5548 5549 u8 reserved_at_2e0[0x20]; 5550 5551 u8 local_ack_timeout_err[0x20]; 5552 5553 u8 reserved_at_320[0xa0]; 5554 5555 u8 resp_local_length_error[0x20]; 5556 5557 u8 req_local_length_error[0x20]; 5558 5559 u8 resp_local_qp_error[0x20]; 5560 5561 u8 local_operation_error[0x20]; 5562 5563 u8 resp_local_protection[0x20]; 5564 5565 u8 req_local_protection[0x20]; 5566 5567 u8 resp_cqe_error[0x20]; 5568 5569 u8 req_cqe_error[0x20]; 5570 5571 u8 req_mw_binding[0x20]; 5572 5573 u8 req_bad_response[0x20]; 5574 5575 u8 req_remote_invalid_request[0x20]; 5576 5577 u8 resp_remote_invalid_request[0x20]; 5578 5579 u8 req_remote_access_errors[0x20]; 5580 5581 u8 resp_remote_access_errors[0x20]; 5582 5583 u8 req_remote_operation_errors[0x20]; 5584 5585 u8 req_transport_retries_exceeded[0x20]; 5586 5587 u8 cq_overflow[0x20]; 5588 5589 u8 resp_cqe_flush_error[0x20]; 5590 5591 u8 req_cqe_flush_error[0x20]; 5592 5593 u8 reserved_at_620[0x20]; 5594 5595 u8 roce_adp_retrans[0x20]; 5596 5597 u8 roce_adp_retrans_to[0x20]; 5598 5599 u8 roce_slow_restart[0x20]; 5600 5601 u8 roce_slow_restart_cnps[0x20]; 5602 5603 u8 roce_slow_restart_trans[0x20]; 5604 5605 u8 reserved_at_6e0[0x120]; 5606 }; 5607 5608 struct mlx5_ifc_query_q_counter_in_bits { 5609 u8 opcode[0x10]; 5610 u8 reserved_at_10[0x10]; 5611 5612 u8 reserved_at_20[0x10]; 5613 u8 op_mod[0x10]; 5614 5615 u8 other_vport[0x1]; 5616 u8 reserved_at_41[0xf]; 5617 u8 vport_number[0x10]; 5618 5619 u8 reserved_at_60[0x60]; 5620 5621 u8 clear[0x1]; 5622 u8 aggregate[0x1]; 5623 u8 reserved_at_c2[0x1e]; 5624 5625 u8 reserved_at_e0[0x18]; 5626 u8 counter_set_id[0x8]; 5627 }; 5628 5629 struct mlx5_ifc_query_pages_out_bits { 5630 u8 status[0x8]; 5631 u8 reserved_at_8[0x18]; 5632 5633 u8 syndrome[0x20]; 5634 5635 u8 embedded_cpu_function[0x1]; 5636 u8 reserved_at_41[0xf]; 5637 u8 function_id[0x10]; 5638 5639 u8 num_pages[0x20]; 5640 }; 5641 5642 enum { 5643 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5644 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5645 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5646 }; 5647 5648 struct mlx5_ifc_query_pages_in_bits { 5649 u8 opcode[0x10]; 5650 u8 reserved_at_10[0x10]; 5651 5652 u8 reserved_at_20[0x10]; 5653 u8 op_mod[0x10]; 5654 5655 u8 embedded_cpu_function[0x1]; 5656 u8 reserved_at_41[0xf]; 5657 u8 function_id[0x10]; 5658 5659 u8 reserved_at_60[0x20]; 5660 }; 5661 5662 struct mlx5_ifc_query_nic_vport_context_out_bits { 5663 u8 status[0x8]; 5664 u8 reserved_at_8[0x18]; 5665 5666 u8 syndrome[0x20]; 5667 5668 u8 reserved_at_40[0x40]; 5669 5670 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5671 }; 5672 5673 struct mlx5_ifc_query_nic_vport_context_in_bits { 5674 u8 opcode[0x10]; 5675 u8 reserved_at_10[0x10]; 5676 5677 u8 reserved_at_20[0x10]; 5678 u8 op_mod[0x10]; 5679 5680 u8 other_vport[0x1]; 5681 u8 reserved_at_41[0xf]; 5682 u8 vport_number[0x10]; 5683 5684 u8 reserved_at_60[0x5]; 5685 u8 allowed_list_type[0x3]; 5686 u8 reserved_at_68[0x18]; 5687 }; 5688 5689 struct mlx5_ifc_query_mkey_out_bits { 5690 u8 status[0x8]; 5691 u8 reserved_at_8[0x18]; 5692 5693 u8 syndrome[0x20]; 5694 5695 u8 reserved_at_40[0x40]; 5696 5697 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5698 5699 u8 reserved_at_280[0x600]; 5700 5701 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5702 5703 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5704 }; 5705 5706 struct mlx5_ifc_query_mkey_in_bits { 5707 u8 opcode[0x10]; 5708 u8 reserved_at_10[0x10]; 5709 5710 u8 reserved_at_20[0x10]; 5711 u8 op_mod[0x10]; 5712 5713 u8 reserved_at_40[0x8]; 5714 u8 mkey_index[0x18]; 5715 5716 u8 pg_access[0x1]; 5717 u8 reserved_at_61[0x1f]; 5718 }; 5719 5720 struct mlx5_ifc_query_mad_demux_out_bits { 5721 u8 status[0x8]; 5722 u8 reserved_at_8[0x18]; 5723 5724 u8 syndrome[0x20]; 5725 5726 u8 reserved_at_40[0x40]; 5727 5728 u8 mad_dumux_parameters_block[0x20]; 5729 }; 5730 5731 struct mlx5_ifc_query_mad_demux_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 reserved_at_40[0x40]; 5739 }; 5740 5741 struct mlx5_ifc_query_l2_table_entry_out_bits { 5742 u8 status[0x8]; 5743 u8 reserved_at_8[0x18]; 5744 5745 u8 syndrome[0x20]; 5746 5747 u8 reserved_at_40[0xa0]; 5748 5749 u8 reserved_at_e0[0x13]; 5750 u8 vlan_valid[0x1]; 5751 u8 vlan[0xc]; 5752 5753 struct mlx5_ifc_mac_address_layout_bits mac_address; 5754 5755 u8 reserved_at_140[0xc0]; 5756 }; 5757 5758 struct mlx5_ifc_query_l2_table_entry_in_bits { 5759 u8 opcode[0x10]; 5760 u8 reserved_at_10[0x10]; 5761 5762 u8 reserved_at_20[0x10]; 5763 u8 op_mod[0x10]; 5764 5765 u8 reserved_at_40[0x60]; 5766 5767 u8 reserved_at_a0[0x8]; 5768 u8 table_index[0x18]; 5769 5770 u8 reserved_at_c0[0x140]; 5771 }; 5772 5773 struct mlx5_ifc_query_issi_out_bits { 5774 u8 status[0x8]; 5775 u8 reserved_at_8[0x18]; 5776 5777 u8 syndrome[0x20]; 5778 5779 u8 reserved_at_40[0x10]; 5780 u8 current_issi[0x10]; 5781 5782 u8 reserved_at_60[0xa0]; 5783 5784 u8 reserved_at_100[76][0x8]; 5785 u8 supported_issi_dw0[0x20]; 5786 }; 5787 5788 struct mlx5_ifc_query_issi_in_bits { 5789 u8 opcode[0x10]; 5790 u8 reserved_at_10[0x10]; 5791 5792 u8 reserved_at_20[0x10]; 5793 u8 op_mod[0x10]; 5794 5795 u8 reserved_at_40[0x40]; 5796 }; 5797 5798 struct mlx5_ifc_set_driver_version_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_0[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 u8 reserved_1[0x40]; 5804 }; 5805 5806 struct mlx5_ifc_set_driver_version_in_bits { 5807 u8 opcode[0x10]; 5808 u8 reserved_0[0x10]; 5809 5810 u8 reserved_1[0x10]; 5811 u8 op_mod[0x10]; 5812 5813 u8 reserved_2[0x40]; 5814 u8 driver_version[64][0x8]; 5815 }; 5816 5817 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5818 u8 status[0x8]; 5819 u8 reserved_at_8[0x18]; 5820 5821 u8 syndrome[0x20]; 5822 5823 u8 reserved_at_40[0x40]; 5824 5825 struct mlx5_ifc_pkey_bits pkey[]; 5826 }; 5827 5828 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5829 u8 opcode[0x10]; 5830 u8 reserved_at_10[0x10]; 5831 5832 u8 reserved_at_20[0x10]; 5833 u8 op_mod[0x10]; 5834 5835 u8 other_vport[0x1]; 5836 u8 reserved_at_41[0xb]; 5837 u8 port_num[0x4]; 5838 u8 vport_number[0x10]; 5839 5840 u8 reserved_at_60[0x10]; 5841 u8 pkey_index[0x10]; 5842 }; 5843 5844 enum { 5845 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5846 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5847 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5848 }; 5849 5850 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5851 u8 status[0x8]; 5852 u8 reserved_at_8[0x18]; 5853 5854 u8 syndrome[0x20]; 5855 5856 u8 reserved_at_40[0x20]; 5857 5858 u8 gids_num[0x10]; 5859 u8 reserved_at_70[0x10]; 5860 5861 struct mlx5_ifc_array128_auto_bits gid[]; 5862 }; 5863 5864 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5865 u8 opcode[0x10]; 5866 u8 reserved_at_10[0x10]; 5867 5868 u8 reserved_at_20[0x10]; 5869 u8 op_mod[0x10]; 5870 5871 u8 other_vport[0x1]; 5872 u8 reserved_at_41[0xb]; 5873 u8 port_num[0x4]; 5874 u8 vport_number[0x10]; 5875 5876 u8 reserved_at_60[0x10]; 5877 u8 gid_index[0x10]; 5878 }; 5879 5880 struct mlx5_ifc_query_hca_vport_context_out_bits { 5881 u8 status[0x8]; 5882 u8 reserved_at_8[0x18]; 5883 5884 u8 syndrome[0x20]; 5885 5886 u8 reserved_at_40[0x40]; 5887 5888 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5889 }; 5890 5891 struct mlx5_ifc_query_hca_vport_context_in_bits { 5892 u8 opcode[0x10]; 5893 u8 reserved_at_10[0x10]; 5894 5895 u8 reserved_at_20[0x10]; 5896 u8 op_mod[0x10]; 5897 5898 u8 other_vport[0x1]; 5899 u8 reserved_at_41[0xb]; 5900 u8 port_num[0x4]; 5901 u8 vport_number[0x10]; 5902 5903 u8 reserved_at_60[0x20]; 5904 }; 5905 5906 struct mlx5_ifc_query_hca_cap_out_bits { 5907 u8 status[0x8]; 5908 u8 reserved_at_8[0x18]; 5909 5910 u8 syndrome[0x20]; 5911 5912 u8 reserved_at_40[0x40]; 5913 5914 union mlx5_ifc_hca_cap_union_bits capability; 5915 }; 5916 5917 struct mlx5_ifc_query_hca_cap_in_bits { 5918 u8 opcode[0x10]; 5919 u8 reserved_at_10[0x10]; 5920 5921 u8 reserved_at_20[0x10]; 5922 u8 op_mod[0x10]; 5923 5924 u8 other_function[0x1]; 5925 u8 ec_vf_function[0x1]; 5926 u8 reserved_at_42[0xe]; 5927 u8 function_id[0x10]; 5928 5929 u8 reserved_at_60[0x20]; 5930 }; 5931 5932 struct mlx5_ifc_other_hca_cap_bits { 5933 u8 roce[0x1]; 5934 u8 reserved_at_1[0x27f]; 5935 }; 5936 5937 struct mlx5_ifc_query_other_hca_cap_out_bits { 5938 u8 status[0x8]; 5939 u8 reserved_at_8[0x18]; 5940 5941 u8 syndrome[0x20]; 5942 5943 u8 reserved_at_40[0x40]; 5944 5945 struct mlx5_ifc_other_hca_cap_bits other_capability; 5946 }; 5947 5948 struct mlx5_ifc_query_other_hca_cap_in_bits { 5949 u8 opcode[0x10]; 5950 u8 reserved_at_10[0x10]; 5951 5952 u8 reserved_at_20[0x10]; 5953 u8 op_mod[0x10]; 5954 5955 u8 reserved_at_40[0x10]; 5956 u8 function_id[0x10]; 5957 5958 u8 reserved_at_60[0x20]; 5959 }; 5960 5961 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5962 u8 status[0x8]; 5963 u8 reserved_at_8[0x18]; 5964 5965 u8 syndrome[0x20]; 5966 5967 u8 reserved_at_40[0x40]; 5968 }; 5969 5970 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5971 u8 opcode[0x10]; 5972 u8 reserved_at_10[0x10]; 5973 5974 u8 reserved_at_20[0x10]; 5975 u8 op_mod[0x10]; 5976 5977 u8 reserved_at_40[0x10]; 5978 u8 function_id[0x10]; 5979 u8 field_select[0x20]; 5980 5981 struct mlx5_ifc_other_hca_cap_bits other_capability; 5982 }; 5983 5984 struct mlx5_ifc_flow_table_context_bits { 5985 u8 reformat_en[0x1]; 5986 u8 decap_en[0x1]; 5987 u8 sw_owner[0x1]; 5988 u8 termination_table[0x1]; 5989 u8 table_miss_action[0x4]; 5990 u8 level[0x8]; 5991 u8 reserved_at_10[0x8]; 5992 u8 log_size[0x8]; 5993 5994 u8 reserved_at_20[0x8]; 5995 u8 table_miss_id[0x18]; 5996 5997 u8 reserved_at_40[0x8]; 5998 u8 lag_master_next_table_id[0x18]; 5999 6000 u8 reserved_at_60[0x60]; 6001 6002 u8 sw_owner_icm_root_1[0x40]; 6003 6004 u8 sw_owner_icm_root_0[0x40]; 6005 6006 }; 6007 6008 struct mlx5_ifc_query_flow_table_out_bits { 6009 u8 status[0x8]; 6010 u8 reserved_at_8[0x18]; 6011 6012 u8 syndrome[0x20]; 6013 6014 u8 reserved_at_40[0x80]; 6015 6016 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6017 }; 6018 6019 struct mlx5_ifc_query_flow_table_in_bits { 6020 u8 opcode[0x10]; 6021 u8 reserved_at_10[0x10]; 6022 6023 u8 reserved_at_20[0x10]; 6024 u8 op_mod[0x10]; 6025 6026 u8 reserved_at_40[0x40]; 6027 6028 u8 table_type[0x8]; 6029 u8 reserved_at_88[0x18]; 6030 6031 u8 reserved_at_a0[0x8]; 6032 u8 table_id[0x18]; 6033 6034 u8 reserved_at_c0[0x140]; 6035 }; 6036 6037 struct mlx5_ifc_query_fte_out_bits { 6038 u8 status[0x8]; 6039 u8 reserved_at_8[0x18]; 6040 6041 u8 syndrome[0x20]; 6042 6043 u8 reserved_at_40[0x1c0]; 6044 6045 struct mlx5_ifc_flow_context_bits flow_context; 6046 }; 6047 6048 struct mlx5_ifc_query_fte_in_bits { 6049 u8 opcode[0x10]; 6050 u8 reserved_at_10[0x10]; 6051 6052 u8 reserved_at_20[0x10]; 6053 u8 op_mod[0x10]; 6054 6055 u8 reserved_at_40[0x40]; 6056 6057 u8 table_type[0x8]; 6058 u8 reserved_at_88[0x18]; 6059 6060 u8 reserved_at_a0[0x8]; 6061 u8 table_id[0x18]; 6062 6063 u8 reserved_at_c0[0x40]; 6064 6065 u8 flow_index[0x20]; 6066 6067 u8 reserved_at_120[0xe0]; 6068 }; 6069 6070 struct mlx5_ifc_match_definer_format_0_bits { 6071 u8 reserved_at_0[0x100]; 6072 6073 u8 metadata_reg_c_0[0x20]; 6074 6075 u8 metadata_reg_c_1[0x20]; 6076 6077 u8 outer_dmac_47_16[0x20]; 6078 6079 u8 outer_dmac_15_0[0x10]; 6080 u8 outer_ethertype[0x10]; 6081 6082 u8 reserved_at_180[0x1]; 6083 u8 sx_sniffer[0x1]; 6084 u8 functional_lb[0x1]; 6085 u8 outer_ip_frag[0x1]; 6086 u8 outer_qp_type[0x2]; 6087 u8 outer_encap_type[0x2]; 6088 u8 port_number[0x2]; 6089 u8 outer_l3_type[0x2]; 6090 u8 outer_l4_type[0x2]; 6091 u8 outer_first_vlan_type[0x2]; 6092 u8 outer_first_vlan_prio[0x3]; 6093 u8 outer_first_vlan_cfi[0x1]; 6094 u8 outer_first_vlan_vid[0xc]; 6095 6096 u8 outer_l4_type_ext[0x4]; 6097 u8 reserved_at_1a4[0x2]; 6098 u8 outer_ipsec_layer[0x2]; 6099 u8 outer_l2_type[0x2]; 6100 u8 force_lb[0x1]; 6101 u8 outer_l2_ok[0x1]; 6102 u8 outer_l3_ok[0x1]; 6103 u8 outer_l4_ok[0x1]; 6104 u8 outer_second_vlan_type[0x2]; 6105 u8 outer_second_vlan_prio[0x3]; 6106 u8 outer_second_vlan_cfi[0x1]; 6107 u8 outer_second_vlan_vid[0xc]; 6108 6109 u8 outer_smac_47_16[0x20]; 6110 6111 u8 outer_smac_15_0[0x10]; 6112 u8 inner_ipv4_checksum_ok[0x1]; 6113 u8 inner_l4_checksum_ok[0x1]; 6114 u8 outer_ipv4_checksum_ok[0x1]; 6115 u8 outer_l4_checksum_ok[0x1]; 6116 u8 inner_l3_ok[0x1]; 6117 u8 inner_l4_ok[0x1]; 6118 u8 outer_l3_ok_duplicate[0x1]; 6119 u8 outer_l4_ok_duplicate[0x1]; 6120 u8 outer_tcp_cwr[0x1]; 6121 u8 outer_tcp_ece[0x1]; 6122 u8 outer_tcp_urg[0x1]; 6123 u8 outer_tcp_ack[0x1]; 6124 u8 outer_tcp_psh[0x1]; 6125 u8 outer_tcp_rst[0x1]; 6126 u8 outer_tcp_syn[0x1]; 6127 u8 outer_tcp_fin[0x1]; 6128 }; 6129 6130 struct mlx5_ifc_match_definer_format_22_bits { 6131 u8 reserved_at_0[0x100]; 6132 6133 u8 outer_ip_src_addr[0x20]; 6134 6135 u8 outer_ip_dest_addr[0x20]; 6136 6137 u8 outer_l4_sport[0x10]; 6138 u8 outer_l4_dport[0x10]; 6139 6140 u8 reserved_at_160[0x1]; 6141 u8 sx_sniffer[0x1]; 6142 u8 functional_lb[0x1]; 6143 u8 outer_ip_frag[0x1]; 6144 u8 outer_qp_type[0x2]; 6145 u8 outer_encap_type[0x2]; 6146 u8 port_number[0x2]; 6147 u8 outer_l3_type[0x2]; 6148 u8 outer_l4_type[0x2]; 6149 u8 outer_first_vlan_type[0x2]; 6150 u8 outer_first_vlan_prio[0x3]; 6151 u8 outer_first_vlan_cfi[0x1]; 6152 u8 outer_first_vlan_vid[0xc]; 6153 6154 u8 metadata_reg_c_0[0x20]; 6155 6156 u8 outer_dmac_47_16[0x20]; 6157 6158 u8 outer_smac_47_16[0x20]; 6159 6160 u8 outer_smac_15_0[0x10]; 6161 u8 outer_dmac_15_0[0x10]; 6162 }; 6163 6164 struct mlx5_ifc_match_definer_format_23_bits { 6165 u8 reserved_at_0[0x100]; 6166 6167 u8 inner_ip_src_addr[0x20]; 6168 6169 u8 inner_ip_dest_addr[0x20]; 6170 6171 u8 inner_l4_sport[0x10]; 6172 u8 inner_l4_dport[0x10]; 6173 6174 u8 reserved_at_160[0x1]; 6175 u8 sx_sniffer[0x1]; 6176 u8 functional_lb[0x1]; 6177 u8 inner_ip_frag[0x1]; 6178 u8 inner_qp_type[0x2]; 6179 u8 inner_encap_type[0x2]; 6180 u8 port_number[0x2]; 6181 u8 inner_l3_type[0x2]; 6182 u8 inner_l4_type[0x2]; 6183 u8 inner_first_vlan_type[0x2]; 6184 u8 inner_first_vlan_prio[0x3]; 6185 u8 inner_first_vlan_cfi[0x1]; 6186 u8 inner_first_vlan_vid[0xc]; 6187 6188 u8 tunnel_header_0[0x20]; 6189 6190 u8 inner_dmac_47_16[0x20]; 6191 6192 u8 inner_smac_47_16[0x20]; 6193 6194 u8 inner_smac_15_0[0x10]; 6195 u8 inner_dmac_15_0[0x10]; 6196 }; 6197 6198 struct mlx5_ifc_match_definer_format_29_bits { 6199 u8 reserved_at_0[0xc0]; 6200 6201 u8 outer_ip_dest_addr[0x80]; 6202 6203 u8 outer_ip_src_addr[0x80]; 6204 6205 u8 outer_l4_sport[0x10]; 6206 u8 outer_l4_dport[0x10]; 6207 6208 u8 reserved_at_1e0[0x20]; 6209 }; 6210 6211 struct mlx5_ifc_match_definer_format_30_bits { 6212 u8 reserved_at_0[0xa0]; 6213 6214 u8 outer_ip_dest_addr[0x80]; 6215 6216 u8 outer_ip_src_addr[0x80]; 6217 6218 u8 outer_dmac_47_16[0x20]; 6219 6220 u8 outer_smac_47_16[0x20]; 6221 6222 u8 outer_smac_15_0[0x10]; 6223 u8 outer_dmac_15_0[0x10]; 6224 }; 6225 6226 struct mlx5_ifc_match_definer_format_31_bits { 6227 u8 reserved_at_0[0xc0]; 6228 6229 u8 inner_ip_dest_addr[0x80]; 6230 6231 u8 inner_ip_src_addr[0x80]; 6232 6233 u8 inner_l4_sport[0x10]; 6234 u8 inner_l4_dport[0x10]; 6235 6236 u8 reserved_at_1e0[0x20]; 6237 }; 6238 6239 struct mlx5_ifc_match_definer_format_32_bits { 6240 u8 reserved_at_0[0xa0]; 6241 6242 u8 inner_ip_dest_addr[0x80]; 6243 6244 u8 inner_ip_src_addr[0x80]; 6245 6246 u8 inner_dmac_47_16[0x20]; 6247 6248 u8 inner_smac_47_16[0x20]; 6249 6250 u8 inner_smac_15_0[0x10]; 6251 u8 inner_dmac_15_0[0x10]; 6252 }; 6253 6254 enum { 6255 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6256 }; 6257 6258 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6259 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6260 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6261 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6262 6263 struct mlx5_ifc_match_definer_match_mask_bits { 6264 u8 reserved_at_1c0[5][0x20]; 6265 u8 match_dw_8[0x20]; 6266 u8 match_dw_7[0x20]; 6267 u8 match_dw_6[0x20]; 6268 u8 match_dw_5[0x20]; 6269 u8 match_dw_4[0x20]; 6270 u8 match_dw_3[0x20]; 6271 u8 match_dw_2[0x20]; 6272 u8 match_dw_1[0x20]; 6273 u8 match_dw_0[0x20]; 6274 6275 u8 match_byte_7[0x8]; 6276 u8 match_byte_6[0x8]; 6277 u8 match_byte_5[0x8]; 6278 u8 match_byte_4[0x8]; 6279 6280 u8 match_byte_3[0x8]; 6281 u8 match_byte_2[0x8]; 6282 u8 match_byte_1[0x8]; 6283 u8 match_byte_0[0x8]; 6284 }; 6285 6286 struct mlx5_ifc_match_definer_bits { 6287 u8 modify_field_select[0x40]; 6288 6289 u8 reserved_at_40[0x40]; 6290 6291 u8 reserved_at_80[0x10]; 6292 u8 format_id[0x10]; 6293 6294 u8 reserved_at_a0[0x60]; 6295 6296 u8 format_select_dw3[0x8]; 6297 u8 format_select_dw2[0x8]; 6298 u8 format_select_dw1[0x8]; 6299 u8 format_select_dw0[0x8]; 6300 6301 u8 format_select_dw7[0x8]; 6302 u8 format_select_dw6[0x8]; 6303 u8 format_select_dw5[0x8]; 6304 u8 format_select_dw4[0x8]; 6305 6306 u8 reserved_at_100[0x18]; 6307 u8 format_select_dw8[0x8]; 6308 6309 u8 reserved_at_120[0x20]; 6310 6311 u8 format_select_byte3[0x8]; 6312 u8 format_select_byte2[0x8]; 6313 u8 format_select_byte1[0x8]; 6314 u8 format_select_byte0[0x8]; 6315 6316 u8 format_select_byte7[0x8]; 6317 u8 format_select_byte6[0x8]; 6318 u8 format_select_byte5[0x8]; 6319 u8 format_select_byte4[0x8]; 6320 6321 u8 reserved_at_180[0x40]; 6322 6323 union { 6324 struct { 6325 u8 match_mask[16][0x20]; 6326 }; 6327 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6328 }; 6329 }; 6330 6331 struct mlx5_ifc_general_obj_create_param_bits { 6332 u8 alias_object[0x1]; 6333 u8 reserved_at_1[0x2]; 6334 u8 log_obj_range[0x5]; 6335 u8 reserved_at_8[0x18]; 6336 }; 6337 6338 struct mlx5_ifc_general_obj_query_param_bits { 6339 u8 alias_object[0x1]; 6340 u8 obj_offset[0x1f]; 6341 }; 6342 6343 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6344 u8 opcode[0x10]; 6345 u8 uid[0x10]; 6346 6347 u8 vhca_tunnel_id[0x10]; 6348 u8 obj_type[0x10]; 6349 6350 u8 obj_id[0x20]; 6351 6352 union { 6353 struct mlx5_ifc_general_obj_create_param_bits create; 6354 struct mlx5_ifc_general_obj_query_param_bits query; 6355 } op_param; 6356 }; 6357 6358 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6359 u8 status[0x8]; 6360 u8 reserved_at_8[0x18]; 6361 6362 u8 syndrome[0x20]; 6363 6364 u8 obj_id[0x20]; 6365 6366 u8 reserved_at_60[0x20]; 6367 }; 6368 6369 struct mlx5_ifc_modify_header_arg_bits { 6370 u8 reserved_at_0[0x80]; 6371 6372 u8 reserved_at_80[0x8]; 6373 u8 access_pd[0x18]; 6374 }; 6375 6376 struct mlx5_ifc_create_modify_header_arg_in_bits { 6377 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6378 struct mlx5_ifc_modify_header_arg_bits arg; 6379 }; 6380 6381 struct mlx5_ifc_create_match_definer_in_bits { 6382 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6383 6384 struct mlx5_ifc_match_definer_bits obj_context; 6385 }; 6386 6387 struct mlx5_ifc_create_match_definer_out_bits { 6388 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6389 }; 6390 6391 enum { 6392 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6393 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6394 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6395 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6396 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6397 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6398 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6399 }; 6400 6401 struct mlx5_ifc_query_flow_group_out_bits { 6402 u8 status[0x8]; 6403 u8 reserved_at_8[0x18]; 6404 6405 u8 syndrome[0x20]; 6406 6407 u8 reserved_at_40[0xa0]; 6408 6409 u8 start_flow_index[0x20]; 6410 6411 u8 reserved_at_100[0x20]; 6412 6413 u8 end_flow_index[0x20]; 6414 6415 u8 reserved_at_140[0xa0]; 6416 6417 u8 reserved_at_1e0[0x18]; 6418 u8 match_criteria_enable[0x8]; 6419 6420 struct mlx5_ifc_fte_match_param_bits match_criteria; 6421 6422 u8 reserved_at_1200[0xe00]; 6423 }; 6424 6425 struct mlx5_ifc_query_flow_group_in_bits { 6426 u8 opcode[0x10]; 6427 u8 reserved_at_10[0x10]; 6428 6429 u8 reserved_at_20[0x10]; 6430 u8 op_mod[0x10]; 6431 6432 u8 reserved_at_40[0x40]; 6433 6434 u8 table_type[0x8]; 6435 u8 reserved_at_88[0x18]; 6436 6437 u8 reserved_at_a0[0x8]; 6438 u8 table_id[0x18]; 6439 6440 u8 group_id[0x20]; 6441 6442 u8 reserved_at_e0[0x120]; 6443 }; 6444 6445 struct mlx5_ifc_query_flow_counter_out_bits { 6446 u8 status[0x8]; 6447 u8 reserved_at_8[0x18]; 6448 6449 u8 syndrome[0x20]; 6450 6451 u8 reserved_at_40[0x40]; 6452 6453 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6454 }; 6455 6456 struct mlx5_ifc_query_flow_counter_in_bits { 6457 u8 opcode[0x10]; 6458 u8 reserved_at_10[0x10]; 6459 6460 u8 reserved_at_20[0x10]; 6461 u8 op_mod[0x10]; 6462 6463 u8 reserved_at_40[0x80]; 6464 6465 u8 clear[0x1]; 6466 u8 reserved_at_c1[0xf]; 6467 u8 num_of_counters[0x10]; 6468 6469 u8 flow_counter_id[0x20]; 6470 }; 6471 6472 struct mlx5_ifc_query_esw_vport_context_out_bits { 6473 u8 status[0x8]; 6474 u8 reserved_at_8[0x18]; 6475 6476 u8 syndrome[0x20]; 6477 6478 u8 reserved_at_40[0x40]; 6479 6480 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6481 }; 6482 6483 struct mlx5_ifc_query_esw_vport_context_in_bits { 6484 u8 opcode[0x10]; 6485 u8 reserved_at_10[0x10]; 6486 6487 u8 reserved_at_20[0x10]; 6488 u8 op_mod[0x10]; 6489 6490 u8 other_vport[0x1]; 6491 u8 reserved_at_41[0xf]; 6492 u8 vport_number[0x10]; 6493 6494 u8 reserved_at_60[0x20]; 6495 }; 6496 6497 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6498 u8 status[0x8]; 6499 u8 reserved_at_8[0x18]; 6500 6501 u8 syndrome[0x20]; 6502 6503 u8 reserved_at_40[0x40]; 6504 }; 6505 6506 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6507 u8 reserved_at_0[0x1b]; 6508 u8 fdb_to_vport_reg_c_id[0x1]; 6509 u8 vport_cvlan_insert[0x1]; 6510 u8 vport_svlan_insert[0x1]; 6511 u8 vport_cvlan_strip[0x1]; 6512 u8 vport_svlan_strip[0x1]; 6513 }; 6514 6515 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6516 u8 opcode[0x10]; 6517 u8 reserved_at_10[0x10]; 6518 6519 u8 reserved_at_20[0x10]; 6520 u8 op_mod[0x10]; 6521 6522 u8 other_vport[0x1]; 6523 u8 reserved_at_41[0xf]; 6524 u8 vport_number[0x10]; 6525 6526 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6527 6528 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6529 }; 6530 6531 struct mlx5_ifc_query_eq_out_bits { 6532 u8 status[0x8]; 6533 u8 reserved_at_8[0x18]; 6534 6535 u8 syndrome[0x20]; 6536 6537 u8 reserved_at_40[0x40]; 6538 6539 struct mlx5_ifc_eqc_bits eq_context_entry; 6540 6541 u8 reserved_at_280[0x40]; 6542 6543 u8 event_bitmask[0x40]; 6544 6545 u8 reserved_at_300[0x580]; 6546 6547 u8 pas[][0x40]; 6548 }; 6549 6550 struct mlx5_ifc_query_eq_in_bits { 6551 u8 opcode[0x10]; 6552 u8 reserved_at_10[0x10]; 6553 6554 u8 reserved_at_20[0x10]; 6555 u8 op_mod[0x10]; 6556 6557 u8 reserved_at_40[0x18]; 6558 u8 eq_number[0x8]; 6559 6560 u8 reserved_at_60[0x20]; 6561 }; 6562 6563 struct mlx5_ifc_packet_reformat_context_in_bits { 6564 u8 reformat_type[0x8]; 6565 u8 reserved_at_8[0x4]; 6566 u8 reformat_param_0[0x4]; 6567 u8 reserved_at_10[0x6]; 6568 u8 reformat_data_size[0xa]; 6569 6570 u8 reformat_param_1[0x8]; 6571 u8 reserved_at_28[0x8]; 6572 u8 reformat_data[2][0x8]; 6573 6574 u8 more_reformat_data[][0x8]; 6575 }; 6576 6577 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6578 u8 status[0x8]; 6579 u8 reserved_at_8[0x18]; 6580 6581 u8 syndrome[0x20]; 6582 6583 u8 reserved_at_40[0xa0]; 6584 6585 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6586 }; 6587 6588 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6589 u8 opcode[0x10]; 6590 u8 reserved_at_10[0x10]; 6591 6592 u8 reserved_at_20[0x10]; 6593 u8 op_mod[0x10]; 6594 6595 u8 packet_reformat_id[0x20]; 6596 6597 u8 reserved_at_60[0xa0]; 6598 }; 6599 6600 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6601 u8 status[0x8]; 6602 u8 reserved_at_8[0x18]; 6603 6604 u8 syndrome[0x20]; 6605 6606 u8 packet_reformat_id[0x20]; 6607 6608 u8 reserved_at_60[0x20]; 6609 }; 6610 6611 enum { 6612 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6613 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6614 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6615 }; 6616 6617 enum mlx5_reformat_ctx_type { 6618 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6619 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6620 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6621 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6622 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6623 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6624 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6625 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6626 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6627 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6628 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6629 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6630 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6631 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6632 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6633 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6634 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6635 }; 6636 6637 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6638 u8 opcode[0x10]; 6639 u8 reserved_at_10[0x10]; 6640 6641 u8 reserved_at_20[0x10]; 6642 u8 op_mod[0x10]; 6643 6644 u8 reserved_at_40[0xa0]; 6645 6646 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6647 }; 6648 6649 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6650 u8 status[0x8]; 6651 u8 reserved_at_8[0x18]; 6652 6653 u8 syndrome[0x20]; 6654 6655 u8 reserved_at_40[0x40]; 6656 }; 6657 6658 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6659 u8 opcode[0x10]; 6660 u8 reserved_at_10[0x10]; 6661 6662 u8 reserved_20[0x10]; 6663 u8 op_mod[0x10]; 6664 6665 u8 packet_reformat_id[0x20]; 6666 6667 u8 reserved_60[0x20]; 6668 }; 6669 6670 struct mlx5_ifc_set_action_in_bits { 6671 u8 action_type[0x4]; 6672 u8 field[0xc]; 6673 u8 reserved_at_10[0x3]; 6674 u8 offset[0x5]; 6675 u8 reserved_at_18[0x3]; 6676 u8 length[0x5]; 6677 6678 u8 data[0x20]; 6679 }; 6680 6681 struct mlx5_ifc_add_action_in_bits { 6682 u8 action_type[0x4]; 6683 u8 field[0xc]; 6684 u8 reserved_at_10[0x10]; 6685 6686 u8 data[0x20]; 6687 }; 6688 6689 struct mlx5_ifc_copy_action_in_bits { 6690 u8 action_type[0x4]; 6691 u8 src_field[0xc]; 6692 u8 reserved_at_10[0x3]; 6693 u8 src_offset[0x5]; 6694 u8 reserved_at_18[0x3]; 6695 u8 length[0x5]; 6696 6697 u8 reserved_at_20[0x4]; 6698 u8 dst_field[0xc]; 6699 u8 reserved_at_30[0x3]; 6700 u8 dst_offset[0x5]; 6701 u8 reserved_at_38[0x8]; 6702 }; 6703 6704 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6705 struct mlx5_ifc_set_action_in_bits set_action_in; 6706 struct mlx5_ifc_add_action_in_bits add_action_in; 6707 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6708 u8 reserved_at_0[0x40]; 6709 }; 6710 6711 enum { 6712 MLX5_ACTION_TYPE_SET = 0x1, 6713 MLX5_ACTION_TYPE_ADD = 0x2, 6714 MLX5_ACTION_TYPE_COPY = 0x3, 6715 }; 6716 6717 enum { 6718 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6719 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6720 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6721 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6722 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6723 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6724 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6725 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6726 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6727 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6728 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6729 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6730 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6731 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6732 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6733 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6734 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6735 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6736 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6737 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6738 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6739 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6740 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6741 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6742 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6743 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6744 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6745 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6746 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6747 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6748 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6749 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6750 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6751 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6752 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6753 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6754 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6755 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6756 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6757 }; 6758 6759 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6760 u8 status[0x8]; 6761 u8 reserved_at_8[0x18]; 6762 6763 u8 syndrome[0x20]; 6764 6765 u8 modify_header_id[0x20]; 6766 6767 u8 reserved_at_60[0x20]; 6768 }; 6769 6770 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6771 u8 opcode[0x10]; 6772 u8 reserved_at_10[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 reserved_at_40[0x20]; 6778 6779 u8 table_type[0x8]; 6780 u8 reserved_at_68[0x10]; 6781 u8 num_of_actions[0x8]; 6782 6783 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6784 }; 6785 6786 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6787 u8 status[0x8]; 6788 u8 reserved_at_8[0x18]; 6789 6790 u8 syndrome[0x20]; 6791 6792 u8 reserved_at_40[0x40]; 6793 }; 6794 6795 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6796 u8 opcode[0x10]; 6797 u8 reserved_at_10[0x10]; 6798 6799 u8 reserved_at_20[0x10]; 6800 u8 op_mod[0x10]; 6801 6802 u8 modify_header_id[0x20]; 6803 6804 u8 reserved_at_60[0x20]; 6805 }; 6806 6807 struct mlx5_ifc_query_modify_header_context_in_bits { 6808 u8 opcode[0x10]; 6809 u8 uid[0x10]; 6810 6811 u8 reserved_at_20[0x10]; 6812 u8 op_mod[0x10]; 6813 6814 u8 modify_header_id[0x20]; 6815 6816 u8 reserved_at_60[0xa0]; 6817 }; 6818 6819 struct mlx5_ifc_query_dct_out_bits { 6820 u8 status[0x8]; 6821 u8 reserved_at_8[0x18]; 6822 6823 u8 syndrome[0x20]; 6824 6825 u8 reserved_at_40[0x40]; 6826 6827 struct mlx5_ifc_dctc_bits dct_context_entry; 6828 6829 u8 reserved_at_280[0x180]; 6830 }; 6831 6832 struct mlx5_ifc_query_dct_in_bits { 6833 u8 opcode[0x10]; 6834 u8 reserved_at_10[0x10]; 6835 6836 u8 reserved_at_20[0x10]; 6837 u8 op_mod[0x10]; 6838 6839 u8 reserved_at_40[0x8]; 6840 u8 dctn[0x18]; 6841 6842 u8 reserved_at_60[0x20]; 6843 }; 6844 6845 struct mlx5_ifc_query_cq_out_bits { 6846 u8 status[0x8]; 6847 u8 reserved_at_8[0x18]; 6848 6849 u8 syndrome[0x20]; 6850 6851 u8 reserved_at_40[0x40]; 6852 6853 struct mlx5_ifc_cqc_bits cq_context; 6854 6855 u8 reserved_at_280[0x600]; 6856 6857 u8 pas[][0x40]; 6858 }; 6859 6860 struct mlx5_ifc_query_cq_in_bits { 6861 u8 opcode[0x10]; 6862 u8 reserved_at_10[0x10]; 6863 6864 u8 reserved_at_20[0x10]; 6865 u8 op_mod[0x10]; 6866 6867 u8 reserved_at_40[0x8]; 6868 u8 cqn[0x18]; 6869 6870 u8 reserved_at_60[0x20]; 6871 }; 6872 6873 struct mlx5_ifc_query_cong_status_out_bits { 6874 u8 status[0x8]; 6875 u8 reserved_at_8[0x18]; 6876 6877 u8 syndrome[0x20]; 6878 6879 u8 reserved_at_40[0x20]; 6880 6881 u8 enable[0x1]; 6882 u8 tag_enable[0x1]; 6883 u8 reserved_at_62[0x1e]; 6884 }; 6885 6886 struct mlx5_ifc_query_cong_status_in_bits { 6887 u8 opcode[0x10]; 6888 u8 reserved_at_10[0x10]; 6889 6890 u8 reserved_at_20[0x10]; 6891 u8 op_mod[0x10]; 6892 6893 u8 reserved_at_40[0x18]; 6894 u8 priority[0x4]; 6895 u8 cong_protocol[0x4]; 6896 6897 u8 reserved_at_60[0x20]; 6898 }; 6899 6900 struct mlx5_ifc_query_cong_statistics_out_bits { 6901 u8 status[0x8]; 6902 u8 reserved_at_8[0x18]; 6903 6904 u8 syndrome[0x20]; 6905 6906 u8 reserved_at_40[0x40]; 6907 6908 u8 rp_cur_flows[0x20]; 6909 6910 u8 sum_flows[0x20]; 6911 6912 u8 rp_cnp_ignored_high[0x20]; 6913 6914 u8 rp_cnp_ignored_low[0x20]; 6915 6916 u8 rp_cnp_handled_high[0x20]; 6917 6918 u8 rp_cnp_handled_low[0x20]; 6919 6920 u8 reserved_at_140[0x100]; 6921 6922 u8 time_stamp_high[0x20]; 6923 6924 u8 time_stamp_low[0x20]; 6925 6926 u8 accumulators_period[0x20]; 6927 6928 u8 np_ecn_marked_roce_packets_high[0x20]; 6929 6930 u8 np_ecn_marked_roce_packets_low[0x20]; 6931 6932 u8 np_cnp_sent_high[0x20]; 6933 6934 u8 np_cnp_sent_low[0x20]; 6935 6936 u8 reserved_at_320[0x560]; 6937 }; 6938 6939 struct mlx5_ifc_query_cong_statistics_in_bits { 6940 u8 opcode[0x10]; 6941 u8 reserved_at_10[0x10]; 6942 6943 u8 reserved_at_20[0x10]; 6944 u8 op_mod[0x10]; 6945 6946 u8 clear[0x1]; 6947 u8 reserved_at_41[0x1f]; 6948 6949 u8 reserved_at_60[0x20]; 6950 }; 6951 6952 struct mlx5_ifc_query_cong_params_out_bits { 6953 u8 status[0x8]; 6954 u8 reserved_at_8[0x18]; 6955 6956 u8 syndrome[0x20]; 6957 6958 u8 reserved_at_40[0x40]; 6959 6960 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6961 }; 6962 6963 struct mlx5_ifc_query_cong_params_in_bits { 6964 u8 opcode[0x10]; 6965 u8 reserved_at_10[0x10]; 6966 6967 u8 reserved_at_20[0x10]; 6968 u8 op_mod[0x10]; 6969 6970 u8 reserved_at_40[0x1c]; 6971 u8 cong_protocol[0x4]; 6972 6973 u8 reserved_at_60[0x20]; 6974 }; 6975 6976 struct mlx5_ifc_query_adapter_out_bits { 6977 u8 status[0x8]; 6978 u8 reserved_at_8[0x18]; 6979 6980 u8 syndrome[0x20]; 6981 6982 u8 reserved_at_40[0x40]; 6983 6984 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6985 }; 6986 6987 struct mlx5_ifc_query_adapter_in_bits { 6988 u8 opcode[0x10]; 6989 u8 reserved_at_10[0x10]; 6990 6991 u8 reserved_at_20[0x10]; 6992 u8 op_mod[0x10]; 6993 6994 u8 reserved_at_40[0x40]; 6995 }; 6996 6997 struct mlx5_ifc_qp_2rst_out_bits { 6998 u8 status[0x8]; 6999 u8 reserved_at_8[0x18]; 7000 7001 u8 syndrome[0x20]; 7002 7003 u8 reserved_at_40[0x40]; 7004 }; 7005 7006 struct mlx5_ifc_qp_2rst_in_bits { 7007 u8 opcode[0x10]; 7008 u8 uid[0x10]; 7009 7010 u8 reserved_at_20[0x10]; 7011 u8 op_mod[0x10]; 7012 7013 u8 reserved_at_40[0x8]; 7014 u8 qpn[0x18]; 7015 7016 u8 reserved_at_60[0x20]; 7017 }; 7018 7019 struct mlx5_ifc_qp_2err_out_bits { 7020 u8 status[0x8]; 7021 u8 reserved_at_8[0x18]; 7022 7023 u8 syndrome[0x20]; 7024 7025 u8 reserved_at_40[0x40]; 7026 }; 7027 7028 struct mlx5_ifc_qp_2err_in_bits { 7029 u8 opcode[0x10]; 7030 u8 uid[0x10]; 7031 7032 u8 reserved_at_20[0x10]; 7033 u8 op_mod[0x10]; 7034 7035 u8 reserved_at_40[0x8]; 7036 u8 qpn[0x18]; 7037 7038 u8 reserved_at_60[0x20]; 7039 }; 7040 7041 struct mlx5_ifc_page_fault_resume_out_bits { 7042 u8 status[0x8]; 7043 u8 reserved_at_8[0x18]; 7044 7045 u8 syndrome[0x20]; 7046 7047 u8 reserved_at_40[0x40]; 7048 }; 7049 7050 struct mlx5_ifc_page_fault_resume_in_bits { 7051 u8 opcode[0x10]; 7052 u8 reserved_at_10[0x10]; 7053 7054 u8 reserved_at_20[0x10]; 7055 u8 op_mod[0x10]; 7056 7057 u8 error[0x1]; 7058 u8 reserved_at_41[0x4]; 7059 u8 page_fault_type[0x3]; 7060 u8 wq_number[0x18]; 7061 7062 u8 reserved_at_60[0x8]; 7063 u8 token[0x18]; 7064 }; 7065 7066 struct mlx5_ifc_nop_out_bits { 7067 u8 status[0x8]; 7068 u8 reserved_at_8[0x18]; 7069 7070 u8 syndrome[0x20]; 7071 7072 u8 reserved_at_40[0x40]; 7073 }; 7074 7075 struct mlx5_ifc_nop_in_bits { 7076 u8 opcode[0x10]; 7077 u8 reserved_at_10[0x10]; 7078 7079 u8 reserved_at_20[0x10]; 7080 u8 op_mod[0x10]; 7081 7082 u8 reserved_at_40[0x40]; 7083 }; 7084 7085 struct mlx5_ifc_modify_vport_state_out_bits { 7086 u8 status[0x8]; 7087 u8 reserved_at_8[0x18]; 7088 7089 u8 syndrome[0x20]; 7090 7091 u8 reserved_at_40[0x40]; 7092 }; 7093 7094 struct mlx5_ifc_modify_vport_state_in_bits { 7095 u8 opcode[0x10]; 7096 u8 reserved_at_10[0x10]; 7097 7098 u8 reserved_at_20[0x10]; 7099 u8 op_mod[0x10]; 7100 7101 u8 other_vport[0x1]; 7102 u8 reserved_at_41[0xf]; 7103 u8 vport_number[0x10]; 7104 7105 u8 reserved_at_60[0x18]; 7106 u8 admin_state[0x4]; 7107 u8 reserved_at_7c[0x4]; 7108 }; 7109 7110 struct mlx5_ifc_modify_tis_out_bits { 7111 u8 status[0x8]; 7112 u8 reserved_at_8[0x18]; 7113 7114 u8 syndrome[0x20]; 7115 7116 u8 reserved_at_40[0x40]; 7117 }; 7118 7119 struct mlx5_ifc_modify_tis_bitmask_bits { 7120 u8 reserved_at_0[0x20]; 7121 7122 u8 reserved_at_20[0x1d]; 7123 u8 lag_tx_port_affinity[0x1]; 7124 u8 strict_lag_tx_port_affinity[0x1]; 7125 u8 prio[0x1]; 7126 }; 7127 7128 struct mlx5_ifc_modify_tis_in_bits { 7129 u8 opcode[0x10]; 7130 u8 uid[0x10]; 7131 7132 u8 reserved_at_20[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 reserved_at_40[0x8]; 7136 u8 tisn[0x18]; 7137 7138 u8 reserved_at_60[0x20]; 7139 7140 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7141 7142 u8 reserved_at_c0[0x40]; 7143 7144 struct mlx5_ifc_tisc_bits ctx; 7145 }; 7146 7147 struct mlx5_ifc_modify_tir_bitmask_bits { 7148 u8 reserved_at_0[0x20]; 7149 7150 u8 reserved_at_20[0x1b]; 7151 u8 self_lb_en[0x1]; 7152 u8 reserved_at_3c[0x1]; 7153 u8 hash[0x1]; 7154 u8 reserved_at_3e[0x1]; 7155 u8 packet_merge[0x1]; 7156 }; 7157 7158 struct mlx5_ifc_modify_tir_out_bits { 7159 u8 status[0x8]; 7160 u8 reserved_at_8[0x18]; 7161 7162 u8 syndrome[0x20]; 7163 7164 u8 reserved_at_40[0x40]; 7165 }; 7166 7167 struct mlx5_ifc_modify_tir_in_bits { 7168 u8 opcode[0x10]; 7169 u8 uid[0x10]; 7170 7171 u8 reserved_at_20[0x10]; 7172 u8 op_mod[0x10]; 7173 7174 u8 reserved_at_40[0x8]; 7175 u8 tirn[0x18]; 7176 7177 u8 reserved_at_60[0x20]; 7178 7179 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7180 7181 u8 reserved_at_c0[0x40]; 7182 7183 struct mlx5_ifc_tirc_bits ctx; 7184 }; 7185 7186 struct mlx5_ifc_modify_sq_out_bits { 7187 u8 status[0x8]; 7188 u8 reserved_at_8[0x18]; 7189 7190 u8 syndrome[0x20]; 7191 7192 u8 reserved_at_40[0x40]; 7193 }; 7194 7195 struct mlx5_ifc_modify_sq_in_bits { 7196 u8 opcode[0x10]; 7197 u8 uid[0x10]; 7198 7199 u8 reserved_at_20[0x10]; 7200 u8 op_mod[0x10]; 7201 7202 u8 sq_state[0x4]; 7203 u8 reserved_at_44[0x4]; 7204 u8 sqn[0x18]; 7205 7206 u8 reserved_at_60[0x20]; 7207 7208 u8 modify_bitmask[0x40]; 7209 7210 u8 reserved_at_c0[0x40]; 7211 7212 struct mlx5_ifc_sqc_bits ctx; 7213 }; 7214 7215 struct mlx5_ifc_modify_scheduling_element_out_bits { 7216 u8 status[0x8]; 7217 u8 reserved_at_8[0x18]; 7218 7219 u8 syndrome[0x20]; 7220 7221 u8 reserved_at_40[0x1c0]; 7222 }; 7223 7224 enum { 7225 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7226 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7227 }; 7228 7229 struct mlx5_ifc_modify_scheduling_element_in_bits { 7230 u8 opcode[0x10]; 7231 u8 reserved_at_10[0x10]; 7232 7233 u8 reserved_at_20[0x10]; 7234 u8 op_mod[0x10]; 7235 7236 u8 scheduling_hierarchy[0x8]; 7237 u8 reserved_at_48[0x18]; 7238 7239 u8 scheduling_element_id[0x20]; 7240 7241 u8 reserved_at_80[0x20]; 7242 7243 u8 modify_bitmask[0x20]; 7244 7245 u8 reserved_at_c0[0x40]; 7246 7247 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7248 7249 u8 reserved_at_300[0x100]; 7250 }; 7251 7252 struct mlx5_ifc_modify_rqt_out_bits { 7253 u8 status[0x8]; 7254 u8 reserved_at_8[0x18]; 7255 7256 u8 syndrome[0x20]; 7257 7258 u8 reserved_at_40[0x40]; 7259 }; 7260 7261 struct mlx5_ifc_rqt_bitmask_bits { 7262 u8 reserved_at_0[0x20]; 7263 7264 u8 reserved_at_20[0x1f]; 7265 u8 rqn_list[0x1]; 7266 }; 7267 7268 struct mlx5_ifc_modify_rqt_in_bits { 7269 u8 opcode[0x10]; 7270 u8 uid[0x10]; 7271 7272 u8 reserved_at_20[0x10]; 7273 u8 op_mod[0x10]; 7274 7275 u8 reserved_at_40[0x8]; 7276 u8 rqtn[0x18]; 7277 7278 u8 reserved_at_60[0x20]; 7279 7280 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7281 7282 u8 reserved_at_c0[0x40]; 7283 7284 struct mlx5_ifc_rqtc_bits ctx; 7285 }; 7286 7287 struct mlx5_ifc_modify_rq_out_bits { 7288 u8 status[0x8]; 7289 u8 reserved_at_8[0x18]; 7290 7291 u8 syndrome[0x20]; 7292 7293 u8 reserved_at_40[0x40]; 7294 }; 7295 7296 enum { 7297 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7298 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7299 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7300 }; 7301 7302 struct mlx5_ifc_modify_rq_in_bits { 7303 u8 opcode[0x10]; 7304 u8 uid[0x10]; 7305 7306 u8 reserved_at_20[0x10]; 7307 u8 op_mod[0x10]; 7308 7309 u8 rq_state[0x4]; 7310 u8 reserved_at_44[0x4]; 7311 u8 rqn[0x18]; 7312 7313 u8 reserved_at_60[0x20]; 7314 7315 u8 modify_bitmask[0x40]; 7316 7317 u8 reserved_at_c0[0x40]; 7318 7319 struct mlx5_ifc_rqc_bits ctx; 7320 }; 7321 7322 struct mlx5_ifc_modify_rmp_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_at_8[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_at_40[0x40]; 7329 }; 7330 7331 struct mlx5_ifc_rmp_bitmask_bits { 7332 u8 reserved_at_0[0x20]; 7333 7334 u8 reserved_at_20[0x1f]; 7335 u8 lwm[0x1]; 7336 }; 7337 7338 struct mlx5_ifc_modify_rmp_in_bits { 7339 u8 opcode[0x10]; 7340 u8 uid[0x10]; 7341 7342 u8 reserved_at_20[0x10]; 7343 u8 op_mod[0x10]; 7344 7345 u8 rmp_state[0x4]; 7346 u8 reserved_at_44[0x4]; 7347 u8 rmpn[0x18]; 7348 7349 u8 reserved_at_60[0x20]; 7350 7351 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7352 7353 u8 reserved_at_c0[0x40]; 7354 7355 struct mlx5_ifc_rmpc_bits ctx; 7356 }; 7357 7358 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7359 u8 status[0x8]; 7360 u8 reserved_at_8[0x18]; 7361 7362 u8 syndrome[0x20]; 7363 7364 u8 reserved_at_40[0x40]; 7365 }; 7366 7367 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7368 u8 reserved_at_0[0x12]; 7369 u8 affiliation[0x1]; 7370 u8 reserved_at_13[0x1]; 7371 u8 disable_uc_local_lb[0x1]; 7372 u8 disable_mc_local_lb[0x1]; 7373 u8 node_guid[0x1]; 7374 u8 port_guid[0x1]; 7375 u8 min_inline[0x1]; 7376 u8 mtu[0x1]; 7377 u8 change_event[0x1]; 7378 u8 promisc[0x1]; 7379 u8 permanent_address[0x1]; 7380 u8 addresses_list[0x1]; 7381 u8 roce_en[0x1]; 7382 u8 reserved_at_1f[0x1]; 7383 }; 7384 7385 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7386 u8 opcode[0x10]; 7387 u8 reserved_at_10[0x10]; 7388 7389 u8 reserved_at_20[0x10]; 7390 u8 op_mod[0x10]; 7391 7392 u8 other_vport[0x1]; 7393 u8 reserved_at_41[0xf]; 7394 u8 vport_number[0x10]; 7395 7396 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7397 7398 u8 reserved_at_80[0x780]; 7399 7400 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7401 }; 7402 7403 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7404 u8 status[0x8]; 7405 u8 reserved_at_8[0x18]; 7406 7407 u8 syndrome[0x20]; 7408 7409 u8 reserved_at_40[0x40]; 7410 }; 7411 7412 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7413 u8 opcode[0x10]; 7414 u8 reserved_at_10[0x10]; 7415 7416 u8 reserved_at_20[0x10]; 7417 u8 op_mod[0x10]; 7418 7419 u8 other_vport[0x1]; 7420 u8 reserved_at_41[0xb]; 7421 u8 port_num[0x4]; 7422 u8 vport_number[0x10]; 7423 7424 u8 reserved_at_60[0x20]; 7425 7426 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7427 }; 7428 7429 struct mlx5_ifc_modify_cq_out_bits { 7430 u8 status[0x8]; 7431 u8 reserved_at_8[0x18]; 7432 7433 u8 syndrome[0x20]; 7434 7435 u8 reserved_at_40[0x40]; 7436 }; 7437 7438 enum { 7439 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7440 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7441 }; 7442 7443 struct mlx5_ifc_modify_cq_in_bits { 7444 u8 opcode[0x10]; 7445 u8 uid[0x10]; 7446 7447 u8 reserved_at_20[0x10]; 7448 u8 op_mod[0x10]; 7449 7450 u8 reserved_at_40[0x8]; 7451 u8 cqn[0x18]; 7452 7453 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7454 7455 struct mlx5_ifc_cqc_bits cq_context; 7456 7457 u8 reserved_at_280[0x60]; 7458 7459 u8 cq_umem_valid[0x1]; 7460 u8 reserved_at_2e1[0x1f]; 7461 7462 u8 reserved_at_300[0x580]; 7463 7464 u8 pas[][0x40]; 7465 }; 7466 7467 struct mlx5_ifc_modify_cong_status_out_bits { 7468 u8 status[0x8]; 7469 u8 reserved_at_8[0x18]; 7470 7471 u8 syndrome[0x20]; 7472 7473 u8 reserved_at_40[0x40]; 7474 }; 7475 7476 struct mlx5_ifc_modify_cong_status_in_bits { 7477 u8 opcode[0x10]; 7478 u8 reserved_at_10[0x10]; 7479 7480 u8 reserved_at_20[0x10]; 7481 u8 op_mod[0x10]; 7482 7483 u8 reserved_at_40[0x18]; 7484 u8 priority[0x4]; 7485 u8 cong_protocol[0x4]; 7486 7487 u8 enable[0x1]; 7488 u8 tag_enable[0x1]; 7489 u8 reserved_at_62[0x1e]; 7490 }; 7491 7492 struct mlx5_ifc_modify_cong_params_out_bits { 7493 u8 status[0x8]; 7494 u8 reserved_at_8[0x18]; 7495 7496 u8 syndrome[0x20]; 7497 7498 u8 reserved_at_40[0x40]; 7499 }; 7500 7501 struct mlx5_ifc_modify_cong_params_in_bits { 7502 u8 opcode[0x10]; 7503 u8 reserved_at_10[0x10]; 7504 7505 u8 reserved_at_20[0x10]; 7506 u8 op_mod[0x10]; 7507 7508 u8 reserved_at_40[0x1c]; 7509 u8 cong_protocol[0x4]; 7510 7511 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7512 7513 u8 reserved_at_80[0x80]; 7514 7515 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7516 }; 7517 7518 struct mlx5_ifc_manage_pages_out_bits { 7519 u8 status[0x8]; 7520 u8 reserved_at_8[0x18]; 7521 7522 u8 syndrome[0x20]; 7523 7524 u8 output_num_entries[0x20]; 7525 7526 u8 reserved_at_60[0x20]; 7527 7528 u8 pas[][0x40]; 7529 }; 7530 7531 enum { 7532 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7533 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7534 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7535 }; 7536 7537 struct mlx5_ifc_manage_pages_in_bits { 7538 u8 opcode[0x10]; 7539 u8 reserved_at_10[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 embedded_cpu_function[0x1]; 7545 u8 reserved_at_41[0xf]; 7546 u8 function_id[0x10]; 7547 7548 u8 input_num_entries[0x20]; 7549 7550 u8 pas[][0x40]; 7551 }; 7552 7553 struct mlx5_ifc_mad_ifc_out_bits { 7554 u8 status[0x8]; 7555 u8 reserved_at_8[0x18]; 7556 7557 u8 syndrome[0x20]; 7558 7559 u8 reserved_at_40[0x40]; 7560 7561 u8 response_mad_packet[256][0x8]; 7562 }; 7563 7564 struct mlx5_ifc_mad_ifc_in_bits { 7565 u8 opcode[0x10]; 7566 u8 reserved_at_10[0x10]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 u8 remote_lid[0x10]; 7572 u8 reserved_at_50[0x8]; 7573 u8 port[0x8]; 7574 7575 u8 reserved_at_60[0x20]; 7576 7577 u8 mad[256][0x8]; 7578 }; 7579 7580 struct mlx5_ifc_init_hca_out_bits { 7581 u8 status[0x8]; 7582 u8 reserved_at_8[0x18]; 7583 7584 u8 syndrome[0x20]; 7585 7586 u8 reserved_at_40[0x40]; 7587 }; 7588 7589 struct mlx5_ifc_init_hca_in_bits { 7590 u8 opcode[0x10]; 7591 u8 reserved_at_10[0x10]; 7592 7593 u8 reserved_at_20[0x10]; 7594 u8 op_mod[0x10]; 7595 7596 u8 reserved_at_40[0x20]; 7597 7598 u8 reserved_at_60[0x2]; 7599 u8 sw_vhca_id[0xe]; 7600 u8 reserved_at_70[0x10]; 7601 7602 u8 sw_owner_id[4][0x20]; 7603 }; 7604 7605 struct mlx5_ifc_init2rtr_qp_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_at_8[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_at_40[0x20]; 7612 u8 ece[0x20]; 7613 }; 7614 7615 struct mlx5_ifc_init2rtr_qp_in_bits { 7616 u8 opcode[0x10]; 7617 u8 uid[0x10]; 7618 7619 u8 reserved_at_20[0x10]; 7620 u8 op_mod[0x10]; 7621 7622 u8 reserved_at_40[0x8]; 7623 u8 qpn[0x18]; 7624 7625 u8 reserved_at_60[0x20]; 7626 7627 u8 opt_param_mask[0x20]; 7628 7629 u8 ece[0x20]; 7630 7631 struct mlx5_ifc_qpc_bits qpc; 7632 7633 u8 reserved_at_800[0x80]; 7634 }; 7635 7636 struct mlx5_ifc_init2init_qp_out_bits { 7637 u8 status[0x8]; 7638 u8 reserved_at_8[0x18]; 7639 7640 u8 syndrome[0x20]; 7641 7642 u8 reserved_at_40[0x20]; 7643 u8 ece[0x20]; 7644 }; 7645 7646 struct mlx5_ifc_init2init_qp_in_bits { 7647 u8 opcode[0x10]; 7648 u8 uid[0x10]; 7649 7650 u8 reserved_at_20[0x10]; 7651 u8 op_mod[0x10]; 7652 7653 u8 reserved_at_40[0x8]; 7654 u8 qpn[0x18]; 7655 7656 u8 reserved_at_60[0x20]; 7657 7658 u8 opt_param_mask[0x20]; 7659 7660 u8 ece[0x20]; 7661 7662 struct mlx5_ifc_qpc_bits qpc; 7663 7664 u8 reserved_at_800[0x80]; 7665 }; 7666 7667 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7668 u8 status[0x8]; 7669 u8 reserved_at_8[0x18]; 7670 7671 u8 syndrome[0x20]; 7672 7673 u8 reserved_at_40[0x40]; 7674 7675 u8 packet_headers_log[128][0x8]; 7676 7677 u8 packet_syndrome[64][0x8]; 7678 }; 7679 7680 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7681 u8 opcode[0x10]; 7682 u8 reserved_at_10[0x10]; 7683 7684 u8 reserved_at_20[0x10]; 7685 u8 op_mod[0x10]; 7686 7687 u8 reserved_at_40[0x40]; 7688 }; 7689 7690 struct mlx5_ifc_gen_eqe_in_bits { 7691 u8 opcode[0x10]; 7692 u8 reserved_at_10[0x10]; 7693 7694 u8 reserved_at_20[0x10]; 7695 u8 op_mod[0x10]; 7696 7697 u8 reserved_at_40[0x18]; 7698 u8 eq_number[0x8]; 7699 7700 u8 reserved_at_60[0x20]; 7701 7702 u8 eqe[64][0x8]; 7703 }; 7704 7705 struct mlx5_ifc_gen_eq_out_bits { 7706 u8 status[0x8]; 7707 u8 reserved_at_8[0x18]; 7708 7709 u8 syndrome[0x20]; 7710 7711 u8 reserved_at_40[0x40]; 7712 }; 7713 7714 struct mlx5_ifc_enable_hca_out_bits { 7715 u8 status[0x8]; 7716 u8 reserved_at_8[0x18]; 7717 7718 u8 syndrome[0x20]; 7719 7720 u8 reserved_at_40[0x20]; 7721 }; 7722 7723 struct mlx5_ifc_enable_hca_in_bits { 7724 u8 opcode[0x10]; 7725 u8 reserved_at_10[0x10]; 7726 7727 u8 reserved_at_20[0x10]; 7728 u8 op_mod[0x10]; 7729 7730 u8 embedded_cpu_function[0x1]; 7731 u8 reserved_at_41[0xf]; 7732 u8 function_id[0x10]; 7733 7734 u8 reserved_at_60[0x20]; 7735 }; 7736 7737 struct mlx5_ifc_drain_dct_out_bits { 7738 u8 status[0x8]; 7739 u8 reserved_at_8[0x18]; 7740 7741 u8 syndrome[0x20]; 7742 7743 u8 reserved_at_40[0x40]; 7744 }; 7745 7746 struct mlx5_ifc_drain_dct_in_bits { 7747 u8 opcode[0x10]; 7748 u8 uid[0x10]; 7749 7750 u8 reserved_at_20[0x10]; 7751 u8 op_mod[0x10]; 7752 7753 u8 reserved_at_40[0x8]; 7754 u8 dctn[0x18]; 7755 7756 u8 reserved_at_60[0x20]; 7757 }; 7758 7759 struct mlx5_ifc_disable_hca_out_bits { 7760 u8 status[0x8]; 7761 u8 reserved_at_8[0x18]; 7762 7763 u8 syndrome[0x20]; 7764 7765 u8 reserved_at_40[0x20]; 7766 }; 7767 7768 struct mlx5_ifc_disable_hca_in_bits { 7769 u8 opcode[0x10]; 7770 u8 reserved_at_10[0x10]; 7771 7772 u8 reserved_at_20[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 embedded_cpu_function[0x1]; 7776 u8 reserved_at_41[0xf]; 7777 u8 function_id[0x10]; 7778 7779 u8 reserved_at_60[0x20]; 7780 }; 7781 7782 struct mlx5_ifc_detach_from_mcg_out_bits { 7783 u8 status[0x8]; 7784 u8 reserved_at_8[0x18]; 7785 7786 u8 syndrome[0x20]; 7787 7788 u8 reserved_at_40[0x40]; 7789 }; 7790 7791 struct mlx5_ifc_detach_from_mcg_in_bits { 7792 u8 opcode[0x10]; 7793 u8 uid[0x10]; 7794 7795 u8 reserved_at_20[0x10]; 7796 u8 op_mod[0x10]; 7797 7798 u8 reserved_at_40[0x8]; 7799 u8 qpn[0x18]; 7800 7801 u8 reserved_at_60[0x20]; 7802 7803 u8 multicast_gid[16][0x8]; 7804 }; 7805 7806 struct mlx5_ifc_destroy_xrq_out_bits { 7807 u8 status[0x8]; 7808 u8 reserved_at_8[0x18]; 7809 7810 u8 syndrome[0x20]; 7811 7812 u8 reserved_at_40[0x40]; 7813 }; 7814 7815 struct mlx5_ifc_destroy_xrq_in_bits { 7816 u8 opcode[0x10]; 7817 u8 uid[0x10]; 7818 7819 u8 reserved_at_20[0x10]; 7820 u8 op_mod[0x10]; 7821 7822 u8 reserved_at_40[0x8]; 7823 u8 xrqn[0x18]; 7824 7825 u8 reserved_at_60[0x20]; 7826 }; 7827 7828 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7829 u8 status[0x8]; 7830 u8 reserved_at_8[0x18]; 7831 7832 u8 syndrome[0x20]; 7833 7834 u8 reserved_at_40[0x40]; 7835 }; 7836 7837 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7838 u8 opcode[0x10]; 7839 u8 uid[0x10]; 7840 7841 u8 reserved_at_20[0x10]; 7842 u8 op_mod[0x10]; 7843 7844 u8 reserved_at_40[0x8]; 7845 u8 xrc_srqn[0x18]; 7846 7847 u8 reserved_at_60[0x20]; 7848 }; 7849 7850 struct mlx5_ifc_destroy_tis_out_bits { 7851 u8 status[0x8]; 7852 u8 reserved_at_8[0x18]; 7853 7854 u8 syndrome[0x20]; 7855 7856 u8 reserved_at_40[0x40]; 7857 }; 7858 7859 struct mlx5_ifc_destroy_tis_in_bits { 7860 u8 opcode[0x10]; 7861 u8 uid[0x10]; 7862 7863 u8 reserved_at_20[0x10]; 7864 u8 op_mod[0x10]; 7865 7866 u8 reserved_at_40[0x8]; 7867 u8 tisn[0x18]; 7868 7869 u8 reserved_at_60[0x20]; 7870 }; 7871 7872 struct mlx5_ifc_destroy_tir_out_bits { 7873 u8 status[0x8]; 7874 u8 reserved_at_8[0x18]; 7875 7876 u8 syndrome[0x20]; 7877 7878 u8 reserved_at_40[0x40]; 7879 }; 7880 7881 struct mlx5_ifc_destroy_tir_in_bits { 7882 u8 opcode[0x10]; 7883 u8 uid[0x10]; 7884 7885 u8 reserved_at_20[0x10]; 7886 u8 op_mod[0x10]; 7887 7888 u8 reserved_at_40[0x8]; 7889 u8 tirn[0x18]; 7890 7891 u8 reserved_at_60[0x20]; 7892 }; 7893 7894 struct mlx5_ifc_destroy_srq_out_bits { 7895 u8 status[0x8]; 7896 u8 reserved_at_8[0x18]; 7897 7898 u8 syndrome[0x20]; 7899 7900 u8 reserved_at_40[0x40]; 7901 }; 7902 7903 struct mlx5_ifc_destroy_srq_in_bits { 7904 u8 opcode[0x10]; 7905 u8 uid[0x10]; 7906 7907 u8 reserved_at_20[0x10]; 7908 u8 op_mod[0x10]; 7909 7910 u8 reserved_at_40[0x8]; 7911 u8 srqn[0x18]; 7912 7913 u8 reserved_at_60[0x20]; 7914 }; 7915 7916 struct mlx5_ifc_destroy_sq_out_bits { 7917 u8 status[0x8]; 7918 u8 reserved_at_8[0x18]; 7919 7920 u8 syndrome[0x20]; 7921 7922 u8 reserved_at_40[0x40]; 7923 }; 7924 7925 struct mlx5_ifc_destroy_sq_in_bits { 7926 u8 opcode[0x10]; 7927 u8 uid[0x10]; 7928 7929 u8 reserved_at_20[0x10]; 7930 u8 op_mod[0x10]; 7931 7932 u8 reserved_at_40[0x8]; 7933 u8 sqn[0x18]; 7934 7935 u8 reserved_at_60[0x20]; 7936 }; 7937 7938 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7939 u8 status[0x8]; 7940 u8 reserved_at_8[0x18]; 7941 7942 u8 syndrome[0x20]; 7943 7944 u8 reserved_at_40[0x1c0]; 7945 }; 7946 7947 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7948 u8 opcode[0x10]; 7949 u8 reserved_at_10[0x10]; 7950 7951 u8 reserved_at_20[0x10]; 7952 u8 op_mod[0x10]; 7953 7954 u8 scheduling_hierarchy[0x8]; 7955 u8 reserved_at_48[0x18]; 7956 7957 u8 scheduling_element_id[0x20]; 7958 7959 u8 reserved_at_80[0x180]; 7960 }; 7961 7962 struct mlx5_ifc_destroy_rqt_out_bits { 7963 u8 status[0x8]; 7964 u8 reserved_at_8[0x18]; 7965 7966 u8 syndrome[0x20]; 7967 7968 u8 reserved_at_40[0x40]; 7969 }; 7970 7971 struct mlx5_ifc_destroy_rqt_in_bits { 7972 u8 opcode[0x10]; 7973 u8 uid[0x10]; 7974 7975 u8 reserved_at_20[0x10]; 7976 u8 op_mod[0x10]; 7977 7978 u8 reserved_at_40[0x8]; 7979 u8 rqtn[0x18]; 7980 7981 u8 reserved_at_60[0x20]; 7982 }; 7983 7984 struct mlx5_ifc_destroy_rq_out_bits { 7985 u8 status[0x8]; 7986 u8 reserved_at_8[0x18]; 7987 7988 u8 syndrome[0x20]; 7989 7990 u8 reserved_at_40[0x40]; 7991 }; 7992 7993 struct mlx5_ifc_destroy_rq_in_bits { 7994 u8 opcode[0x10]; 7995 u8 uid[0x10]; 7996 7997 u8 reserved_at_20[0x10]; 7998 u8 op_mod[0x10]; 7999 8000 u8 reserved_at_40[0x8]; 8001 u8 rqn[0x18]; 8002 8003 u8 reserved_at_60[0x20]; 8004 }; 8005 8006 struct mlx5_ifc_set_delay_drop_params_in_bits { 8007 u8 opcode[0x10]; 8008 u8 reserved_at_10[0x10]; 8009 8010 u8 reserved_at_20[0x10]; 8011 u8 op_mod[0x10]; 8012 8013 u8 reserved_at_40[0x20]; 8014 8015 u8 reserved_at_60[0x10]; 8016 u8 delay_drop_timeout[0x10]; 8017 }; 8018 8019 struct mlx5_ifc_set_delay_drop_params_out_bits { 8020 u8 status[0x8]; 8021 u8 reserved_at_8[0x18]; 8022 8023 u8 syndrome[0x20]; 8024 8025 u8 reserved_at_40[0x40]; 8026 }; 8027 8028 struct mlx5_ifc_destroy_rmp_out_bits { 8029 u8 status[0x8]; 8030 u8 reserved_at_8[0x18]; 8031 8032 u8 syndrome[0x20]; 8033 8034 u8 reserved_at_40[0x40]; 8035 }; 8036 8037 struct mlx5_ifc_destroy_rmp_in_bits { 8038 u8 opcode[0x10]; 8039 u8 uid[0x10]; 8040 8041 u8 reserved_at_20[0x10]; 8042 u8 op_mod[0x10]; 8043 8044 u8 reserved_at_40[0x8]; 8045 u8 rmpn[0x18]; 8046 8047 u8 reserved_at_60[0x20]; 8048 }; 8049 8050 struct mlx5_ifc_destroy_qp_out_bits { 8051 u8 status[0x8]; 8052 u8 reserved_at_8[0x18]; 8053 8054 u8 syndrome[0x20]; 8055 8056 u8 reserved_at_40[0x40]; 8057 }; 8058 8059 struct mlx5_ifc_destroy_qp_in_bits { 8060 u8 opcode[0x10]; 8061 u8 uid[0x10]; 8062 8063 u8 reserved_at_20[0x10]; 8064 u8 op_mod[0x10]; 8065 8066 u8 reserved_at_40[0x8]; 8067 u8 qpn[0x18]; 8068 8069 u8 reserved_at_60[0x20]; 8070 }; 8071 8072 struct mlx5_ifc_destroy_psv_out_bits { 8073 u8 status[0x8]; 8074 u8 reserved_at_8[0x18]; 8075 8076 u8 syndrome[0x20]; 8077 8078 u8 reserved_at_40[0x40]; 8079 }; 8080 8081 struct mlx5_ifc_destroy_psv_in_bits { 8082 u8 opcode[0x10]; 8083 u8 reserved_at_10[0x10]; 8084 8085 u8 reserved_at_20[0x10]; 8086 u8 op_mod[0x10]; 8087 8088 u8 reserved_at_40[0x8]; 8089 u8 psvn[0x18]; 8090 8091 u8 reserved_at_60[0x20]; 8092 }; 8093 8094 struct mlx5_ifc_destroy_mkey_out_bits { 8095 u8 status[0x8]; 8096 u8 reserved_at_8[0x18]; 8097 8098 u8 syndrome[0x20]; 8099 8100 u8 reserved_at_40[0x40]; 8101 }; 8102 8103 struct mlx5_ifc_destroy_mkey_in_bits { 8104 u8 opcode[0x10]; 8105 u8 uid[0x10]; 8106 8107 u8 reserved_at_20[0x10]; 8108 u8 op_mod[0x10]; 8109 8110 u8 reserved_at_40[0x8]; 8111 u8 mkey_index[0x18]; 8112 8113 u8 reserved_at_60[0x20]; 8114 }; 8115 8116 struct mlx5_ifc_destroy_flow_table_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_at_8[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_at_40[0x40]; 8123 }; 8124 8125 struct mlx5_ifc_destroy_flow_table_in_bits { 8126 u8 opcode[0x10]; 8127 u8 reserved_at_10[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 other_vport[0x1]; 8133 u8 reserved_at_41[0xf]; 8134 u8 vport_number[0x10]; 8135 8136 u8 reserved_at_60[0x20]; 8137 8138 u8 table_type[0x8]; 8139 u8 reserved_at_88[0x18]; 8140 8141 u8 reserved_at_a0[0x8]; 8142 u8 table_id[0x18]; 8143 8144 u8 reserved_at_c0[0x140]; 8145 }; 8146 8147 struct mlx5_ifc_destroy_flow_group_out_bits { 8148 u8 status[0x8]; 8149 u8 reserved_at_8[0x18]; 8150 8151 u8 syndrome[0x20]; 8152 8153 u8 reserved_at_40[0x40]; 8154 }; 8155 8156 struct mlx5_ifc_destroy_flow_group_in_bits { 8157 u8 opcode[0x10]; 8158 u8 reserved_at_10[0x10]; 8159 8160 u8 reserved_at_20[0x10]; 8161 u8 op_mod[0x10]; 8162 8163 u8 other_vport[0x1]; 8164 u8 reserved_at_41[0xf]; 8165 u8 vport_number[0x10]; 8166 8167 u8 reserved_at_60[0x20]; 8168 8169 u8 table_type[0x8]; 8170 u8 reserved_at_88[0x18]; 8171 8172 u8 reserved_at_a0[0x8]; 8173 u8 table_id[0x18]; 8174 8175 u8 group_id[0x20]; 8176 8177 u8 reserved_at_e0[0x120]; 8178 }; 8179 8180 struct mlx5_ifc_destroy_eq_out_bits { 8181 u8 status[0x8]; 8182 u8 reserved_at_8[0x18]; 8183 8184 u8 syndrome[0x20]; 8185 8186 u8 reserved_at_40[0x40]; 8187 }; 8188 8189 struct mlx5_ifc_destroy_eq_in_bits { 8190 u8 opcode[0x10]; 8191 u8 reserved_at_10[0x10]; 8192 8193 u8 reserved_at_20[0x10]; 8194 u8 op_mod[0x10]; 8195 8196 u8 reserved_at_40[0x18]; 8197 u8 eq_number[0x8]; 8198 8199 u8 reserved_at_60[0x20]; 8200 }; 8201 8202 struct mlx5_ifc_destroy_dct_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 reserved_at_40[0x40]; 8209 }; 8210 8211 struct mlx5_ifc_destroy_dct_in_bits { 8212 u8 opcode[0x10]; 8213 u8 uid[0x10]; 8214 8215 u8 reserved_at_20[0x10]; 8216 u8 op_mod[0x10]; 8217 8218 u8 reserved_at_40[0x8]; 8219 u8 dctn[0x18]; 8220 8221 u8 reserved_at_60[0x20]; 8222 }; 8223 8224 struct mlx5_ifc_destroy_cq_out_bits { 8225 u8 status[0x8]; 8226 u8 reserved_at_8[0x18]; 8227 8228 u8 syndrome[0x20]; 8229 8230 u8 reserved_at_40[0x40]; 8231 }; 8232 8233 struct mlx5_ifc_destroy_cq_in_bits { 8234 u8 opcode[0x10]; 8235 u8 uid[0x10]; 8236 8237 u8 reserved_at_20[0x10]; 8238 u8 op_mod[0x10]; 8239 8240 u8 reserved_at_40[0x8]; 8241 u8 cqn[0x18]; 8242 8243 u8 reserved_at_60[0x20]; 8244 }; 8245 8246 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x40]; 8253 }; 8254 8255 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8256 u8 opcode[0x10]; 8257 u8 reserved_at_10[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 reserved_at_40[0x20]; 8263 8264 u8 reserved_at_60[0x10]; 8265 u8 vxlan_udp_port[0x10]; 8266 }; 8267 8268 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8269 u8 status[0x8]; 8270 u8 reserved_at_8[0x18]; 8271 8272 u8 syndrome[0x20]; 8273 8274 u8 reserved_at_40[0x40]; 8275 }; 8276 8277 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8278 u8 opcode[0x10]; 8279 u8 reserved_at_10[0x10]; 8280 8281 u8 reserved_at_20[0x10]; 8282 u8 op_mod[0x10]; 8283 8284 u8 reserved_at_40[0x60]; 8285 8286 u8 reserved_at_a0[0x8]; 8287 u8 table_index[0x18]; 8288 8289 u8 reserved_at_c0[0x140]; 8290 }; 8291 8292 struct mlx5_ifc_delete_fte_out_bits { 8293 u8 status[0x8]; 8294 u8 reserved_at_8[0x18]; 8295 8296 u8 syndrome[0x20]; 8297 8298 u8 reserved_at_40[0x40]; 8299 }; 8300 8301 struct mlx5_ifc_delete_fte_in_bits { 8302 u8 opcode[0x10]; 8303 u8 reserved_at_10[0x10]; 8304 8305 u8 reserved_at_20[0x10]; 8306 u8 op_mod[0x10]; 8307 8308 u8 other_vport[0x1]; 8309 u8 reserved_at_41[0xf]; 8310 u8 vport_number[0x10]; 8311 8312 u8 reserved_at_60[0x20]; 8313 8314 u8 table_type[0x8]; 8315 u8 reserved_at_88[0x18]; 8316 8317 u8 reserved_at_a0[0x8]; 8318 u8 table_id[0x18]; 8319 8320 u8 reserved_at_c0[0x40]; 8321 8322 u8 flow_index[0x20]; 8323 8324 u8 reserved_at_120[0xe0]; 8325 }; 8326 8327 struct mlx5_ifc_dealloc_xrcd_out_bits { 8328 u8 status[0x8]; 8329 u8 reserved_at_8[0x18]; 8330 8331 u8 syndrome[0x20]; 8332 8333 u8 reserved_at_40[0x40]; 8334 }; 8335 8336 struct mlx5_ifc_dealloc_xrcd_in_bits { 8337 u8 opcode[0x10]; 8338 u8 uid[0x10]; 8339 8340 u8 reserved_at_20[0x10]; 8341 u8 op_mod[0x10]; 8342 8343 u8 reserved_at_40[0x8]; 8344 u8 xrcd[0x18]; 8345 8346 u8 reserved_at_60[0x20]; 8347 }; 8348 8349 struct mlx5_ifc_dealloc_uar_out_bits { 8350 u8 status[0x8]; 8351 u8 reserved_at_8[0x18]; 8352 8353 u8 syndrome[0x20]; 8354 8355 u8 reserved_at_40[0x40]; 8356 }; 8357 8358 struct mlx5_ifc_dealloc_uar_in_bits { 8359 u8 opcode[0x10]; 8360 u8 uid[0x10]; 8361 8362 u8 reserved_at_20[0x10]; 8363 u8 op_mod[0x10]; 8364 8365 u8 reserved_at_40[0x8]; 8366 u8 uar[0x18]; 8367 8368 u8 reserved_at_60[0x20]; 8369 }; 8370 8371 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8372 u8 status[0x8]; 8373 u8 reserved_at_8[0x18]; 8374 8375 u8 syndrome[0x20]; 8376 8377 u8 reserved_at_40[0x40]; 8378 }; 8379 8380 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8381 u8 opcode[0x10]; 8382 u8 uid[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 reserved_at_40[0x8]; 8388 u8 transport_domain[0x18]; 8389 8390 u8 reserved_at_60[0x20]; 8391 }; 8392 8393 struct mlx5_ifc_dealloc_q_counter_out_bits { 8394 u8 status[0x8]; 8395 u8 reserved_at_8[0x18]; 8396 8397 u8 syndrome[0x20]; 8398 8399 u8 reserved_at_40[0x40]; 8400 }; 8401 8402 struct mlx5_ifc_dealloc_q_counter_in_bits { 8403 u8 opcode[0x10]; 8404 u8 reserved_at_10[0x10]; 8405 8406 u8 reserved_at_20[0x10]; 8407 u8 op_mod[0x10]; 8408 8409 u8 reserved_at_40[0x18]; 8410 u8 counter_set_id[0x8]; 8411 8412 u8 reserved_at_60[0x20]; 8413 }; 8414 8415 struct mlx5_ifc_dealloc_pd_out_bits { 8416 u8 status[0x8]; 8417 u8 reserved_at_8[0x18]; 8418 8419 u8 syndrome[0x20]; 8420 8421 u8 reserved_at_40[0x40]; 8422 }; 8423 8424 struct mlx5_ifc_dealloc_pd_in_bits { 8425 u8 opcode[0x10]; 8426 u8 uid[0x10]; 8427 8428 u8 reserved_at_20[0x10]; 8429 u8 op_mod[0x10]; 8430 8431 u8 reserved_at_40[0x8]; 8432 u8 pd[0x18]; 8433 8434 u8 reserved_at_60[0x20]; 8435 }; 8436 8437 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8438 u8 status[0x8]; 8439 u8 reserved_at_8[0x18]; 8440 8441 u8 syndrome[0x20]; 8442 8443 u8 reserved_at_40[0x40]; 8444 }; 8445 8446 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8447 u8 opcode[0x10]; 8448 u8 reserved_at_10[0x10]; 8449 8450 u8 reserved_at_20[0x10]; 8451 u8 op_mod[0x10]; 8452 8453 u8 flow_counter_id[0x20]; 8454 8455 u8 reserved_at_60[0x20]; 8456 }; 8457 8458 struct mlx5_ifc_create_xrq_out_bits { 8459 u8 status[0x8]; 8460 u8 reserved_at_8[0x18]; 8461 8462 u8 syndrome[0x20]; 8463 8464 u8 reserved_at_40[0x8]; 8465 u8 xrqn[0x18]; 8466 8467 u8 reserved_at_60[0x20]; 8468 }; 8469 8470 struct mlx5_ifc_create_xrq_in_bits { 8471 u8 opcode[0x10]; 8472 u8 uid[0x10]; 8473 8474 u8 reserved_at_20[0x10]; 8475 u8 op_mod[0x10]; 8476 8477 u8 reserved_at_40[0x40]; 8478 8479 struct mlx5_ifc_xrqc_bits xrq_context; 8480 }; 8481 8482 struct mlx5_ifc_create_xrc_srq_out_bits { 8483 u8 status[0x8]; 8484 u8 reserved_at_8[0x18]; 8485 8486 u8 syndrome[0x20]; 8487 8488 u8 reserved_at_40[0x8]; 8489 u8 xrc_srqn[0x18]; 8490 8491 u8 reserved_at_60[0x20]; 8492 }; 8493 8494 struct mlx5_ifc_create_xrc_srq_in_bits { 8495 u8 opcode[0x10]; 8496 u8 uid[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0x40]; 8502 8503 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8504 8505 u8 reserved_at_280[0x60]; 8506 8507 u8 xrc_srq_umem_valid[0x1]; 8508 u8 reserved_at_2e1[0x1f]; 8509 8510 u8 reserved_at_300[0x580]; 8511 8512 u8 pas[][0x40]; 8513 }; 8514 8515 struct mlx5_ifc_create_tis_out_bits { 8516 u8 status[0x8]; 8517 u8 reserved_at_8[0x18]; 8518 8519 u8 syndrome[0x20]; 8520 8521 u8 reserved_at_40[0x8]; 8522 u8 tisn[0x18]; 8523 8524 u8 reserved_at_60[0x20]; 8525 }; 8526 8527 struct mlx5_ifc_create_tis_in_bits { 8528 u8 opcode[0x10]; 8529 u8 uid[0x10]; 8530 8531 u8 reserved_at_20[0x10]; 8532 u8 op_mod[0x10]; 8533 8534 u8 reserved_at_40[0xc0]; 8535 8536 struct mlx5_ifc_tisc_bits ctx; 8537 }; 8538 8539 struct mlx5_ifc_create_tir_out_bits { 8540 u8 status[0x8]; 8541 u8 icm_address_63_40[0x18]; 8542 8543 u8 syndrome[0x20]; 8544 8545 u8 icm_address_39_32[0x8]; 8546 u8 tirn[0x18]; 8547 8548 u8 icm_address_31_0[0x20]; 8549 }; 8550 8551 struct mlx5_ifc_create_tir_in_bits { 8552 u8 opcode[0x10]; 8553 u8 uid[0x10]; 8554 8555 u8 reserved_at_20[0x10]; 8556 u8 op_mod[0x10]; 8557 8558 u8 reserved_at_40[0xc0]; 8559 8560 struct mlx5_ifc_tirc_bits ctx; 8561 }; 8562 8563 struct mlx5_ifc_create_srq_out_bits { 8564 u8 status[0x8]; 8565 u8 reserved_at_8[0x18]; 8566 8567 u8 syndrome[0x20]; 8568 8569 u8 reserved_at_40[0x8]; 8570 u8 srqn[0x18]; 8571 8572 u8 reserved_at_60[0x20]; 8573 }; 8574 8575 struct mlx5_ifc_create_srq_in_bits { 8576 u8 opcode[0x10]; 8577 u8 uid[0x10]; 8578 8579 u8 reserved_at_20[0x10]; 8580 u8 op_mod[0x10]; 8581 8582 u8 reserved_at_40[0x40]; 8583 8584 struct mlx5_ifc_srqc_bits srq_context_entry; 8585 8586 u8 reserved_at_280[0x600]; 8587 8588 u8 pas[][0x40]; 8589 }; 8590 8591 struct mlx5_ifc_create_sq_out_bits { 8592 u8 status[0x8]; 8593 u8 reserved_at_8[0x18]; 8594 8595 u8 syndrome[0x20]; 8596 8597 u8 reserved_at_40[0x8]; 8598 u8 sqn[0x18]; 8599 8600 u8 reserved_at_60[0x20]; 8601 }; 8602 8603 struct mlx5_ifc_create_sq_in_bits { 8604 u8 opcode[0x10]; 8605 u8 uid[0x10]; 8606 8607 u8 reserved_at_20[0x10]; 8608 u8 op_mod[0x10]; 8609 8610 u8 reserved_at_40[0xc0]; 8611 8612 struct mlx5_ifc_sqc_bits ctx; 8613 }; 8614 8615 struct mlx5_ifc_create_scheduling_element_out_bits { 8616 u8 status[0x8]; 8617 u8 reserved_at_8[0x18]; 8618 8619 u8 syndrome[0x20]; 8620 8621 u8 reserved_at_40[0x40]; 8622 8623 u8 scheduling_element_id[0x20]; 8624 8625 u8 reserved_at_a0[0x160]; 8626 }; 8627 8628 struct mlx5_ifc_create_scheduling_element_in_bits { 8629 u8 opcode[0x10]; 8630 u8 reserved_at_10[0x10]; 8631 8632 u8 reserved_at_20[0x10]; 8633 u8 op_mod[0x10]; 8634 8635 u8 scheduling_hierarchy[0x8]; 8636 u8 reserved_at_48[0x18]; 8637 8638 u8 reserved_at_60[0xa0]; 8639 8640 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8641 8642 u8 reserved_at_300[0x100]; 8643 }; 8644 8645 struct mlx5_ifc_create_rqt_out_bits { 8646 u8 status[0x8]; 8647 u8 reserved_at_8[0x18]; 8648 8649 u8 syndrome[0x20]; 8650 8651 u8 reserved_at_40[0x8]; 8652 u8 rqtn[0x18]; 8653 8654 u8 reserved_at_60[0x20]; 8655 }; 8656 8657 struct mlx5_ifc_create_rqt_in_bits { 8658 u8 opcode[0x10]; 8659 u8 uid[0x10]; 8660 8661 u8 reserved_at_20[0x10]; 8662 u8 op_mod[0x10]; 8663 8664 u8 reserved_at_40[0xc0]; 8665 8666 struct mlx5_ifc_rqtc_bits rqt_context; 8667 }; 8668 8669 struct mlx5_ifc_create_rq_out_bits { 8670 u8 status[0x8]; 8671 u8 reserved_at_8[0x18]; 8672 8673 u8 syndrome[0x20]; 8674 8675 u8 reserved_at_40[0x8]; 8676 u8 rqn[0x18]; 8677 8678 u8 reserved_at_60[0x20]; 8679 }; 8680 8681 struct mlx5_ifc_create_rq_in_bits { 8682 u8 opcode[0x10]; 8683 u8 uid[0x10]; 8684 8685 u8 reserved_at_20[0x10]; 8686 u8 op_mod[0x10]; 8687 8688 u8 reserved_at_40[0xc0]; 8689 8690 struct mlx5_ifc_rqc_bits ctx; 8691 }; 8692 8693 struct mlx5_ifc_create_rmp_out_bits { 8694 u8 status[0x8]; 8695 u8 reserved_at_8[0x18]; 8696 8697 u8 syndrome[0x20]; 8698 8699 u8 reserved_at_40[0x8]; 8700 u8 rmpn[0x18]; 8701 8702 u8 reserved_at_60[0x20]; 8703 }; 8704 8705 struct mlx5_ifc_create_rmp_in_bits { 8706 u8 opcode[0x10]; 8707 u8 uid[0x10]; 8708 8709 u8 reserved_at_20[0x10]; 8710 u8 op_mod[0x10]; 8711 8712 u8 reserved_at_40[0xc0]; 8713 8714 struct mlx5_ifc_rmpc_bits ctx; 8715 }; 8716 8717 struct mlx5_ifc_create_qp_out_bits { 8718 u8 status[0x8]; 8719 u8 reserved_at_8[0x18]; 8720 8721 u8 syndrome[0x20]; 8722 8723 u8 reserved_at_40[0x8]; 8724 u8 qpn[0x18]; 8725 8726 u8 ece[0x20]; 8727 }; 8728 8729 struct mlx5_ifc_create_qp_in_bits { 8730 u8 opcode[0x10]; 8731 u8 uid[0x10]; 8732 8733 u8 reserved_at_20[0x10]; 8734 u8 op_mod[0x10]; 8735 8736 u8 qpc_ext[0x1]; 8737 u8 reserved_at_41[0x7]; 8738 u8 input_qpn[0x18]; 8739 8740 u8 reserved_at_60[0x20]; 8741 u8 opt_param_mask[0x20]; 8742 8743 u8 ece[0x20]; 8744 8745 struct mlx5_ifc_qpc_bits qpc; 8746 8747 u8 reserved_at_800[0x60]; 8748 8749 u8 wq_umem_valid[0x1]; 8750 u8 reserved_at_861[0x1f]; 8751 8752 u8 pas[][0x40]; 8753 }; 8754 8755 struct mlx5_ifc_create_psv_out_bits { 8756 u8 status[0x8]; 8757 u8 reserved_at_8[0x18]; 8758 8759 u8 syndrome[0x20]; 8760 8761 u8 reserved_at_40[0x40]; 8762 8763 u8 reserved_at_80[0x8]; 8764 u8 psv0_index[0x18]; 8765 8766 u8 reserved_at_a0[0x8]; 8767 u8 psv1_index[0x18]; 8768 8769 u8 reserved_at_c0[0x8]; 8770 u8 psv2_index[0x18]; 8771 8772 u8 reserved_at_e0[0x8]; 8773 u8 psv3_index[0x18]; 8774 }; 8775 8776 struct mlx5_ifc_create_psv_in_bits { 8777 u8 opcode[0x10]; 8778 u8 reserved_at_10[0x10]; 8779 8780 u8 reserved_at_20[0x10]; 8781 u8 op_mod[0x10]; 8782 8783 u8 num_psv[0x4]; 8784 u8 reserved_at_44[0x4]; 8785 u8 pd[0x18]; 8786 8787 u8 reserved_at_60[0x20]; 8788 }; 8789 8790 struct mlx5_ifc_create_mkey_out_bits { 8791 u8 status[0x8]; 8792 u8 reserved_at_8[0x18]; 8793 8794 u8 syndrome[0x20]; 8795 8796 u8 reserved_at_40[0x8]; 8797 u8 mkey_index[0x18]; 8798 8799 u8 reserved_at_60[0x20]; 8800 }; 8801 8802 struct mlx5_ifc_create_mkey_in_bits { 8803 u8 opcode[0x10]; 8804 u8 uid[0x10]; 8805 8806 u8 reserved_at_20[0x10]; 8807 u8 op_mod[0x10]; 8808 8809 u8 reserved_at_40[0x20]; 8810 8811 u8 pg_access[0x1]; 8812 u8 mkey_umem_valid[0x1]; 8813 u8 reserved_at_62[0x1e]; 8814 8815 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8816 8817 u8 reserved_at_280[0x80]; 8818 8819 u8 translations_octword_actual_size[0x20]; 8820 8821 u8 reserved_at_320[0x560]; 8822 8823 u8 klm_pas_mtt[][0x20]; 8824 }; 8825 8826 enum { 8827 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8828 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8829 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8830 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8831 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8832 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8833 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8834 }; 8835 8836 struct mlx5_ifc_create_flow_table_out_bits { 8837 u8 status[0x8]; 8838 u8 icm_address_63_40[0x18]; 8839 8840 u8 syndrome[0x20]; 8841 8842 u8 icm_address_39_32[0x8]; 8843 u8 table_id[0x18]; 8844 8845 u8 icm_address_31_0[0x20]; 8846 }; 8847 8848 struct mlx5_ifc_create_flow_table_in_bits { 8849 u8 opcode[0x10]; 8850 u8 uid[0x10]; 8851 8852 u8 reserved_at_20[0x10]; 8853 u8 op_mod[0x10]; 8854 8855 u8 other_vport[0x1]; 8856 u8 reserved_at_41[0xf]; 8857 u8 vport_number[0x10]; 8858 8859 u8 reserved_at_60[0x20]; 8860 8861 u8 table_type[0x8]; 8862 u8 reserved_at_88[0x18]; 8863 8864 u8 reserved_at_a0[0x20]; 8865 8866 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8867 }; 8868 8869 struct mlx5_ifc_create_flow_group_out_bits { 8870 u8 status[0x8]; 8871 u8 reserved_at_8[0x18]; 8872 8873 u8 syndrome[0x20]; 8874 8875 u8 reserved_at_40[0x8]; 8876 u8 group_id[0x18]; 8877 8878 u8 reserved_at_60[0x20]; 8879 }; 8880 8881 enum { 8882 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8883 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8884 }; 8885 8886 enum { 8887 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8888 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8889 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8890 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8891 }; 8892 8893 struct mlx5_ifc_create_flow_group_in_bits { 8894 u8 opcode[0x10]; 8895 u8 reserved_at_10[0x10]; 8896 8897 u8 reserved_at_20[0x10]; 8898 u8 op_mod[0x10]; 8899 8900 u8 other_vport[0x1]; 8901 u8 reserved_at_41[0xf]; 8902 u8 vport_number[0x10]; 8903 8904 u8 reserved_at_60[0x20]; 8905 8906 u8 table_type[0x8]; 8907 u8 reserved_at_88[0x4]; 8908 u8 group_type[0x4]; 8909 u8 reserved_at_90[0x10]; 8910 8911 u8 reserved_at_a0[0x8]; 8912 u8 table_id[0x18]; 8913 8914 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8915 8916 u8 reserved_at_c1[0x1f]; 8917 8918 u8 start_flow_index[0x20]; 8919 8920 u8 reserved_at_100[0x20]; 8921 8922 u8 end_flow_index[0x20]; 8923 8924 u8 reserved_at_140[0x10]; 8925 u8 match_definer_id[0x10]; 8926 8927 u8 reserved_at_160[0x80]; 8928 8929 u8 reserved_at_1e0[0x18]; 8930 u8 match_criteria_enable[0x8]; 8931 8932 struct mlx5_ifc_fte_match_param_bits match_criteria; 8933 8934 u8 reserved_at_1200[0xe00]; 8935 }; 8936 8937 struct mlx5_ifc_create_eq_out_bits { 8938 u8 status[0x8]; 8939 u8 reserved_at_8[0x18]; 8940 8941 u8 syndrome[0x20]; 8942 8943 u8 reserved_at_40[0x18]; 8944 u8 eq_number[0x8]; 8945 8946 u8 reserved_at_60[0x20]; 8947 }; 8948 8949 struct mlx5_ifc_create_eq_in_bits { 8950 u8 opcode[0x10]; 8951 u8 uid[0x10]; 8952 8953 u8 reserved_at_20[0x10]; 8954 u8 op_mod[0x10]; 8955 8956 u8 reserved_at_40[0x40]; 8957 8958 struct mlx5_ifc_eqc_bits eq_context_entry; 8959 8960 u8 reserved_at_280[0x40]; 8961 8962 u8 event_bitmask[4][0x40]; 8963 8964 u8 reserved_at_3c0[0x4c0]; 8965 8966 u8 pas[][0x40]; 8967 }; 8968 8969 struct mlx5_ifc_create_dct_out_bits { 8970 u8 status[0x8]; 8971 u8 reserved_at_8[0x18]; 8972 8973 u8 syndrome[0x20]; 8974 8975 u8 reserved_at_40[0x8]; 8976 u8 dctn[0x18]; 8977 8978 u8 ece[0x20]; 8979 }; 8980 8981 struct mlx5_ifc_create_dct_in_bits { 8982 u8 opcode[0x10]; 8983 u8 uid[0x10]; 8984 8985 u8 reserved_at_20[0x10]; 8986 u8 op_mod[0x10]; 8987 8988 u8 reserved_at_40[0x40]; 8989 8990 struct mlx5_ifc_dctc_bits dct_context_entry; 8991 8992 u8 reserved_at_280[0x180]; 8993 }; 8994 8995 struct mlx5_ifc_create_cq_out_bits { 8996 u8 status[0x8]; 8997 u8 reserved_at_8[0x18]; 8998 8999 u8 syndrome[0x20]; 9000 9001 u8 reserved_at_40[0x8]; 9002 u8 cqn[0x18]; 9003 9004 u8 reserved_at_60[0x20]; 9005 }; 9006 9007 struct mlx5_ifc_create_cq_in_bits { 9008 u8 opcode[0x10]; 9009 u8 uid[0x10]; 9010 9011 u8 reserved_at_20[0x10]; 9012 u8 op_mod[0x10]; 9013 9014 u8 reserved_at_40[0x40]; 9015 9016 struct mlx5_ifc_cqc_bits cq_context; 9017 9018 u8 reserved_at_280[0x60]; 9019 9020 u8 cq_umem_valid[0x1]; 9021 u8 reserved_at_2e1[0x59f]; 9022 9023 u8 pas[][0x40]; 9024 }; 9025 9026 struct mlx5_ifc_config_int_moderation_out_bits { 9027 u8 status[0x8]; 9028 u8 reserved_at_8[0x18]; 9029 9030 u8 syndrome[0x20]; 9031 9032 u8 reserved_at_40[0x4]; 9033 u8 min_delay[0xc]; 9034 u8 int_vector[0x10]; 9035 9036 u8 reserved_at_60[0x20]; 9037 }; 9038 9039 enum { 9040 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9041 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9042 }; 9043 9044 struct mlx5_ifc_config_int_moderation_in_bits { 9045 u8 opcode[0x10]; 9046 u8 reserved_at_10[0x10]; 9047 9048 u8 reserved_at_20[0x10]; 9049 u8 op_mod[0x10]; 9050 9051 u8 reserved_at_40[0x4]; 9052 u8 min_delay[0xc]; 9053 u8 int_vector[0x10]; 9054 9055 u8 reserved_at_60[0x20]; 9056 }; 9057 9058 struct mlx5_ifc_attach_to_mcg_out_bits { 9059 u8 status[0x8]; 9060 u8 reserved_at_8[0x18]; 9061 9062 u8 syndrome[0x20]; 9063 9064 u8 reserved_at_40[0x40]; 9065 }; 9066 9067 struct mlx5_ifc_attach_to_mcg_in_bits { 9068 u8 opcode[0x10]; 9069 u8 uid[0x10]; 9070 9071 u8 reserved_at_20[0x10]; 9072 u8 op_mod[0x10]; 9073 9074 u8 reserved_at_40[0x8]; 9075 u8 qpn[0x18]; 9076 9077 u8 reserved_at_60[0x20]; 9078 9079 u8 multicast_gid[16][0x8]; 9080 }; 9081 9082 struct mlx5_ifc_arm_xrq_out_bits { 9083 u8 status[0x8]; 9084 u8 reserved_at_8[0x18]; 9085 9086 u8 syndrome[0x20]; 9087 9088 u8 reserved_at_40[0x40]; 9089 }; 9090 9091 struct mlx5_ifc_arm_xrq_in_bits { 9092 u8 opcode[0x10]; 9093 u8 reserved_at_10[0x10]; 9094 9095 u8 reserved_at_20[0x10]; 9096 u8 op_mod[0x10]; 9097 9098 u8 reserved_at_40[0x8]; 9099 u8 xrqn[0x18]; 9100 9101 u8 reserved_at_60[0x10]; 9102 u8 lwm[0x10]; 9103 }; 9104 9105 struct mlx5_ifc_arm_xrc_srq_out_bits { 9106 u8 status[0x8]; 9107 u8 reserved_at_8[0x18]; 9108 9109 u8 syndrome[0x20]; 9110 9111 u8 reserved_at_40[0x40]; 9112 }; 9113 9114 enum { 9115 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9116 }; 9117 9118 struct mlx5_ifc_arm_xrc_srq_in_bits { 9119 u8 opcode[0x10]; 9120 u8 uid[0x10]; 9121 9122 u8 reserved_at_20[0x10]; 9123 u8 op_mod[0x10]; 9124 9125 u8 reserved_at_40[0x8]; 9126 u8 xrc_srqn[0x18]; 9127 9128 u8 reserved_at_60[0x10]; 9129 u8 lwm[0x10]; 9130 }; 9131 9132 struct mlx5_ifc_arm_rq_out_bits { 9133 u8 status[0x8]; 9134 u8 reserved_at_8[0x18]; 9135 9136 u8 syndrome[0x20]; 9137 9138 u8 reserved_at_40[0x40]; 9139 }; 9140 9141 enum { 9142 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9143 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9144 }; 9145 9146 struct mlx5_ifc_arm_rq_in_bits { 9147 u8 opcode[0x10]; 9148 u8 uid[0x10]; 9149 9150 u8 reserved_at_20[0x10]; 9151 u8 op_mod[0x10]; 9152 9153 u8 reserved_at_40[0x8]; 9154 u8 srq_number[0x18]; 9155 9156 u8 reserved_at_60[0x10]; 9157 u8 lwm[0x10]; 9158 }; 9159 9160 struct mlx5_ifc_arm_dct_out_bits { 9161 u8 status[0x8]; 9162 u8 reserved_at_8[0x18]; 9163 9164 u8 syndrome[0x20]; 9165 9166 u8 reserved_at_40[0x40]; 9167 }; 9168 9169 struct mlx5_ifc_arm_dct_in_bits { 9170 u8 opcode[0x10]; 9171 u8 reserved_at_10[0x10]; 9172 9173 u8 reserved_at_20[0x10]; 9174 u8 op_mod[0x10]; 9175 9176 u8 reserved_at_40[0x8]; 9177 u8 dct_number[0x18]; 9178 9179 u8 reserved_at_60[0x20]; 9180 }; 9181 9182 struct mlx5_ifc_alloc_xrcd_out_bits { 9183 u8 status[0x8]; 9184 u8 reserved_at_8[0x18]; 9185 9186 u8 syndrome[0x20]; 9187 9188 u8 reserved_at_40[0x8]; 9189 u8 xrcd[0x18]; 9190 9191 u8 reserved_at_60[0x20]; 9192 }; 9193 9194 struct mlx5_ifc_alloc_xrcd_in_bits { 9195 u8 opcode[0x10]; 9196 u8 uid[0x10]; 9197 9198 u8 reserved_at_20[0x10]; 9199 u8 op_mod[0x10]; 9200 9201 u8 reserved_at_40[0x40]; 9202 }; 9203 9204 struct mlx5_ifc_alloc_uar_out_bits { 9205 u8 status[0x8]; 9206 u8 reserved_at_8[0x18]; 9207 9208 u8 syndrome[0x20]; 9209 9210 u8 reserved_at_40[0x8]; 9211 u8 uar[0x18]; 9212 9213 u8 reserved_at_60[0x20]; 9214 }; 9215 9216 struct mlx5_ifc_alloc_uar_in_bits { 9217 u8 opcode[0x10]; 9218 u8 uid[0x10]; 9219 9220 u8 reserved_at_20[0x10]; 9221 u8 op_mod[0x10]; 9222 9223 u8 reserved_at_40[0x40]; 9224 }; 9225 9226 struct mlx5_ifc_alloc_transport_domain_out_bits { 9227 u8 status[0x8]; 9228 u8 reserved_at_8[0x18]; 9229 9230 u8 syndrome[0x20]; 9231 9232 u8 reserved_at_40[0x8]; 9233 u8 transport_domain[0x18]; 9234 9235 u8 reserved_at_60[0x20]; 9236 }; 9237 9238 struct mlx5_ifc_alloc_transport_domain_in_bits { 9239 u8 opcode[0x10]; 9240 u8 uid[0x10]; 9241 9242 u8 reserved_at_20[0x10]; 9243 u8 op_mod[0x10]; 9244 9245 u8 reserved_at_40[0x40]; 9246 }; 9247 9248 struct mlx5_ifc_alloc_q_counter_out_bits { 9249 u8 status[0x8]; 9250 u8 reserved_at_8[0x18]; 9251 9252 u8 syndrome[0x20]; 9253 9254 u8 reserved_at_40[0x18]; 9255 u8 counter_set_id[0x8]; 9256 9257 u8 reserved_at_60[0x20]; 9258 }; 9259 9260 struct mlx5_ifc_alloc_q_counter_in_bits { 9261 u8 opcode[0x10]; 9262 u8 uid[0x10]; 9263 9264 u8 reserved_at_20[0x10]; 9265 u8 op_mod[0x10]; 9266 9267 u8 reserved_at_40[0x40]; 9268 }; 9269 9270 struct mlx5_ifc_alloc_pd_out_bits { 9271 u8 status[0x8]; 9272 u8 reserved_at_8[0x18]; 9273 9274 u8 syndrome[0x20]; 9275 9276 u8 reserved_at_40[0x8]; 9277 u8 pd[0x18]; 9278 9279 u8 reserved_at_60[0x20]; 9280 }; 9281 9282 struct mlx5_ifc_alloc_pd_in_bits { 9283 u8 opcode[0x10]; 9284 u8 uid[0x10]; 9285 9286 u8 reserved_at_20[0x10]; 9287 u8 op_mod[0x10]; 9288 9289 u8 reserved_at_40[0x40]; 9290 }; 9291 9292 struct mlx5_ifc_alloc_flow_counter_out_bits { 9293 u8 status[0x8]; 9294 u8 reserved_at_8[0x18]; 9295 9296 u8 syndrome[0x20]; 9297 9298 u8 flow_counter_id[0x20]; 9299 9300 u8 reserved_at_60[0x20]; 9301 }; 9302 9303 struct mlx5_ifc_alloc_flow_counter_in_bits { 9304 u8 opcode[0x10]; 9305 u8 reserved_at_10[0x10]; 9306 9307 u8 reserved_at_20[0x10]; 9308 u8 op_mod[0x10]; 9309 9310 u8 reserved_at_40[0x33]; 9311 u8 flow_counter_bulk_log_size[0x5]; 9312 u8 flow_counter_bulk[0x8]; 9313 }; 9314 9315 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9316 u8 status[0x8]; 9317 u8 reserved_at_8[0x18]; 9318 9319 u8 syndrome[0x20]; 9320 9321 u8 reserved_at_40[0x40]; 9322 }; 9323 9324 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9325 u8 opcode[0x10]; 9326 u8 reserved_at_10[0x10]; 9327 9328 u8 reserved_at_20[0x10]; 9329 u8 op_mod[0x10]; 9330 9331 u8 reserved_at_40[0x20]; 9332 9333 u8 reserved_at_60[0x10]; 9334 u8 vxlan_udp_port[0x10]; 9335 }; 9336 9337 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9338 u8 status[0x8]; 9339 u8 reserved_at_8[0x18]; 9340 9341 u8 syndrome[0x20]; 9342 9343 u8 reserved_at_40[0x40]; 9344 }; 9345 9346 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9347 u8 rate_limit[0x20]; 9348 9349 u8 burst_upper_bound[0x20]; 9350 9351 u8 reserved_at_40[0x10]; 9352 u8 typical_packet_size[0x10]; 9353 9354 u8 reserved_at_60[0x120]; 9355 }; 9356 9357 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9358 u8 opcode[0x10]; 9359 u8 uid[0x10]; 9360 9361 u8 reserved_at_20[0x10]; 9362 u8 op_mod[0x10]; 9363 9364 u8 reserved_at_40[0x10]; 9365 u8 rate_limit_index[0x10]; 9366 9367 u8 reserved_at_60[0x20]; 9368 9369 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9370 }; 9371 9372 struct mlx5_ifc_access_register_out_bits { 9373 u8 status[0x8]; 9374 u8 reserved_at_8[0x18]; 9375 9376 u8 syndrome[0x20]; 9377 9378 u8 reserved_at_40[0x40]; 9379 9380 u8 register_data[][0x20]; 9381 }; 9382 9383 enum { 9384 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9385 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9386 }; 9387 9388 struct mlx5_ifc_access_register_in_bits { 9389 u8 opcode[0x10]; 9390 u8 reserved_at_10[0x10]; 9391 9392 u8 reserved_at_20[0x10]; 9393 u8 op_mod[0x10]; 9394 9395 u8 reserved_at_40[0x10]; 9396 u8 register_id[0x10]; 9397 9398 u8 argument[0x20]; 9399 9400 u8 register_data[][0x20]; 9401 }; 9402 9403 struct mlx5_ifc_sltp_reg_bits { 9404 u8 status[0x4]; 9405 u8 version[0x4]; 9406 u8 local_port[0x8]; 9407 u8 pnat[0x2]; 9408 u8 reserved_at_12[0x2]; 9409 u8 lane[0x4]; 9410 u8 reserved_at_18[0x8]; 9411 9412 u8 reserved_at_20[0x20]; 9413 9414 u8 reserved_at_40[0x7]; 9415 u8 polarity[0x1]; 9416 u8 ob_tap0[0x8]; 9417 u8 ob_tap1[0x8]; 9418 u8 ob_tap2[0x8]; 9419 9420 u8 reserved_at_60[0xc]; 9421 u8 ob_preemp_mode[0x4]; 9422 u8 ob_reg[0x8]; 9423 u8 ob_bias[0x8]; 9424 9425 u8 reserved_at_80[0x20]; 9426 }; 9427 9428 struct mlx5_ifc_slrg_reg_bits { 9429 u8 status[0x4]; 9430 u8 version[0x4]; 9431 u8 local_port[0x8]; 9432 u8 pnat[0x2]; 9433 u8 reserved_at_12[0x2]; 9434 u8 lane[0x4]; 9435 u8 reserved_at_18[0x8]; 9436 9437 u8 time_to_link_up[0x10]; 9438 u8 reserved_at_30[0xc]; 9439 u8 grade_lane_speed[0x4]; 9440 9441 u8 grade_version[0x8]; 9442 u8 grade[0x18]; 9443 9444 u8 reserved_at_60[0x4]; 9445 u8 height_grade_type[0x4]; 9446 u8 height_grade[0x18]; 9447 9448 u8 height_dz[0x10]; 9449 u8 height_dv[0x10]; 9450 9451 u8 reserved_at_a0[0x10]; 9452 u8 height_sigma[0x10]; 9453 9454 u8 reserved_at_c0[0x20]; 9455 9456 u8 reserved_at_e0[0x4]; 9457 u8 phase_grade_type[0x4]; 9458 u8 phase_grade[0x18]; 9459 9460 u8 reserved_at_100[0x8]; 9461 u8 phase_eo_pos[0x8]; 9462 u8 reserved_at_110[0x8]; 9463 u8 phase_eo_neg[0x8]; 9464 9465 u8 ffe_set_tested[0x10]; 9466 u8 test_errors_per_lane[0x10]; 9467 }; 9468 9469 struct mlx5_ifc_pvlc_reg_bits { 9470 u8 reserved_at_0[0x8]; 9471 u8 local_port[0x8]; 9472 u8 reserved_at_10[0x10]; 9473 9474 u8 reserved_at_20[0x1c]; 9475 u8 vl_hw_cap[0x4]; 9476 9477 u8 reserved_at_40[0x1c]; 9478 u8 vl_admin[0x4]; 9479 9480 u8 reserved_at_60[0x1c]; 9481 u8 vl_operational[0x4]; 9482 }; 9483 9484 struct mlx5_ifc_pude_reg_bits { 9485 u8 swid[0x8]; 9486 u8 local_port[0x8]; 9487 u8 reserved_at_10[0x4]; 9488 u8 admin_status[0x4]; 9489 u8 reserved_at_18[0x4]; 9490 u8 oper_status[0x4]; 9491 9492 u8 reserved_at_20[0x60]; 9493 }; 9494 9495 struct mlx5_ifc_ptys_reg_bits { 9496 u8 reserved_at_0[0x1]; 9497 u8 an_disable_admin[0x1]; 9498 u8 an_disable_cap[0x1]; 9499 u8 reserved_at_3[0x5]; 9500 u8 local_port[0x8]; 9501 u8 reserved_at_10[0xd]; 9502 u8 proto_mask[0x3]; 9503 9504 u8 an_status[0x4]; 9505 u8 reserved_at_24[0xc]; 9506 u8 data_rate_oper[0x10]; 9507 9508 u8 ext_eth_proto_capability[0x20]; 9509 9510 u8 eth_proto_capability[0x20]; 9511 9512 u8 ib_link_width_capability[0x10]; 9513 u8 ib_proto_capability[0x10]; 9514 9515 u8 ext_eth_proto_admin[0x20]; 9516 9517 u8 eth_proto_admin[0x20]; 9518 9519 u8 ib_link_width_admin[0x10]; 9520 u8 ib_proto_admin[0x10]; 9521 9522 u8 ext_eth_proto_oper[0x20]; 9523 9524 u8 eth_proto_oper[0x20]; 9525 9526 u8 ib_link_width_oper[0x10]; 9527 u8 ib_proto_oper[0x10]; 9528 9529 u8 reserved_at_160[0x1c]; 9530 u8 connector_type[0x4]; 9531 9532 u8 eth_proto_lp_advertise[0x20]; 9533 9534 u8 reserved_at_1a0[0x60]; 9535 }; 9536 9537 struct mlx5_ifc_mlcr_reg_bits { 9538 u8 reserved_at_0[0x8]; 9539 u8 local_port[0x8]; 9540 u8 reserved_at_10[0x20]; 9541 9542 u8 beacon_duration[0x10]; 9543 u8 reserved_at_40[0x10]; 9544 9545 u8 beacon_remain[0x10]; 9546 }; 9547 9548 struct mlx5_ifc_ptas_reg_bits { 9549 u8 reserved_at_0[0x20]; 9550 9551 u8 algorithm_options[0x10]; 9552 u8 reserved_at_30[0x4]; 9553 u8 repetitions_mode[0x4]; 9554 u8 num_of_repetitions[0x8]; 9555 9556 u8 grade_version[0x8]; 9557 u8 height_grade_type[0x4]; 9558 u8 phase_grade_type[0x4]; 9559 u8 height_grade_weight[0x8]; 9560 u8 phase_grade_weight[0x8]; 9561 9562 u8 gisim_measure_bits[0x10]; 9563 u8 adaptive_tap_measure_bits[0x10]; 9564 9565 u8 ber_bath_high_error_threshold[0x10]; 9566 u8 ber_bath_mid_error_threshold[0x10]; 9567 9568 u8 ber_bath_low_error_threshold[0x10]; 9569 u8 one_ratio_high_threshold[0x10]; 9570 9571 u8 one_ratio_high_mid_threshold[0x10]; 9572 u8 one_ratio_low_mid_threshold[0x10]; 9573 9574 u8 one_ratio_low_threshold[0x10]; 9575 u8 ndeo_error_threshold[0x10]; 9576 9577 u8 mixer_offset_step_size[0x10]; 9578 u8 reserved_at_110[0x8]; 9579 u8 mix90_phase_for_voltage_bath[0x8]; 9580 9581 u8 mixer_offset_start[0x10]; 9582 u8 mixer_offset_end[0x10]; 9583 9584 u8 reserved_at_140[0x15]; 9585 u8 ber_test_time[0xb]; 9586 }; 9587 9588 struct mlx5_ifc_pspa_reg_bits { 9589 u8 swid[0x8]; 9590 u8 local_port[0x8]; 9591 u8 sub_port[0x8]; 9592 u8 reserved_at_18[0x8]; 9593 9594 u8 reserved_at_20[0x20]; 9595 }; 9596 9597 struct mlx5_ifc_pqdr_reg_bits { 9598 u8 reserved_at_0[0x8]; 9599 u8 local_port[0x8]; 9600 u8 reserved_at_10[0x5]; 9601 u8 prio[0x3]; 9602 u8 reserved_at_18[0x6]; 9603 u8 mode[0x2]; 9604 9605 u8 reserved_at_20[0x20]; 9606 9607 u8 reserved_at_40[0x10]; 9608 u8 min_threshold[0x10]; 9609 9610 u8 reserved_at_60[0x10]; 9611 u8 max_threshold[0x10]; 9612 9613 u8 reserved_at_80[0x10]; 9614 u8 mark_probability_denominator[0x10]; 9615 9616 u8 reserved_at_a0[0x60]; 9617 }; 9618 9619 struct mlx5_ifc_ppsc_reg_bits { 9620 u8 reserved_at_0[0x8]; 9621 u8 local_port[0x8]; 9622 u8 reserved_at_10[0x10]; 9623 9624 u8 reserved_at_20[0x60]; 9625 9626 u8 reserved_at_80[0x1c]; 9627 u8 wrps_admin[0x4]; 9628 9629 u8 reserved_at_a0[0x1c]; 9630 u8 wrps_status[0x4]; 9631 9632 u8 reserved_at_c0[0x8]; 9633 u8 up_threshold[0x8]; 9634 u8 reserved_at_d0[0x8]; 9635 u8 down_threshold[0x8]; 9636 9637 u8 reserved_at_e0[0x20]; 9638 9639 u8 reserved_at_100[0x1c]; 9640 u8 srps_admin[0x4]; 9641 9642 u8 reserved_at_120[0x1c]; 9643 u8 srps_status[0x4]; 9644 9645 u8 reserved_at_140[0x40]; 9646 }; 9647 9648 struct mlx5_ifc_pplr_reg_bits { 9649 u8 reserved_at_0[0x8]; 9650 u8 local_port[0x8]; 9651 u8 reserved_at_10[0x10]; 9652 9653 u8 reserved_at_20[0x8]; 9654 u8 lb_cap[0x8]; 9655 u8 reserved_at_30[0x8]; 9656 u8 lb_en[0x8]; 9657 }; 9658 9659 struct mlx5_ifc_pplm_reg_bits { 9660 u8 reserved_at_0[0x8]; 9661 u8 local_port[0x8]; 9662 u8 reserved_at_10[0x10]; 9663 9664 u8 reserved_at_20[0x20]; 9665 9666 u8 port_profile_mode[0x8]; 9667 u8 static_port_profile[0x8]; 9668 u8 active_port_profile[0x8]; 9669 u8 reserved_at_58[0x8]; 9670 9671 u8 retransmission_active[0x8]; 9672 u8 fec_mode_active[0x18]; 9673 9674 u8 rs_fec_correction_bypass_cap[0x4]; 9675 u8 reserved_at_84[0x8]; 9676 u8 fec_override_cap_56g[0x4]; 9677 u8 fec_override_cap_100g[0x4]; 9678 u8 fec_override_cap_50g[0x4]; 9679 u8 fec_override_cap_25g[0x4]; 9680 u8 fec_override_cap_10g_40g[0x4]; 9681 9682 u8 rs_fec_correction_bypass_admin[0x4]; 9683 u8 reserved_at_a4[0x8]; 9684 u8 fec_override_admin_56g[0x4]; 9685 u8 fec_override_admin_100g[0x4]; 9686 u8 fec_override_admin_50g[0x4]; 9687 u8 fec_override_admin_25g[0x4]; 9688 u8 fec_override_admin_10g_40g[0x4]; 9689 9690 u8 fec_override_cap_400g_8x[0x10]; 9691 u8 fec_override_cap_200g_4x[0x10]; 9692 9693 u8 fec_override_cap_100g_2x[0x10]; 9694 u8 fec_override_cap_50g_1x[0x10]; 9695 9696 u8 fec_override_admin_400g_8x[0x10]; 9697 u8 fec_override_admin_200g_4x[0x10]; 9698 9699 u8 fec_override_admin_100g_2x[0x10]; 9700 u8 fec_override_admin_50g_1x[0x10]; 9701 9702 u8 reserved_at_140[0x140]; 9703 }; 9704 9705 struct mlx5_ifc_ppcnt_reg_bits { 9706 u8 swid[0x8]; 9707 u8 local_port[0x8]; 9708 u8 pnat[0x2]; 9709 u8 reserved_at_12[0x8]; 9710 u8 grp[0x6]; 9711 9712 u8 clr[0x1]; 9713 u8 reserved_at_21[0x1c]; 9714 u8 prio_tc[0x3]; 9715 9716 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9717 }; 9718 9719 struct mlx5_ifc_mpein_reg_bits { 9720 u8 reserved_at_0[0x2]; 9721 u8 depth[0x6]; 9722 u8 pcie_index[0x8]; 9723 u8 node[0x8]; 9724 u8 reserved_at_18[0x8]; 9725 9726 u8 capability_mask[0x20]; 9727 9728 u8 reserved_at_40[0x8]; 9729 u8 link_width_enabled[0x8]; 9730 u8 link_speed_enabled[0x10]; 9731 9732 u8 lane0_physical_position[0x8]; 9733 u8 link_width_active[0x8]; 9734 u8 link_speed_active[0x10]; 9735 9736 u8 num_of_pfs[0x10]; 9737 u8 num_of_vfs[0x10]; 9738 9739 u8 bdf0[0x10]; 9740 u8 reserved_at_b0[0x10]; 9741 9742 u8 max_read_request_size[0x4]; 9743 u8 max_payload_size[0x4]; 9744 u8 reserved_at_c8[0x5]; 9745 u8 pwr_status[0x3]; 9746 u8 port_type[0x4]; 9747 u8 reserved_at_d4[0xb]; 9748 u8 lane_reversal[0x1]; 9749 9750 u8 reserved_at_e0[0x14]; 9751 u8 pci_power[0xc]; 9752 9753 u8 reserved_at_100[0x20]; 9754 9755 u8 device_status[0x10]; 9756 u8 port_state[0x8]; 9757 u8 reserved_at_138[0x8]; 9758 9759 u8 reserved_at_140[0x10]; 9760 u8 receiver_detect_result[0x10]; 9761 9762 u8 reserved_at_160[0x20]; 9763 }; 9764 9765 struct mlx5_ifc_mpcnt_reg_bits { 9766 u8 reserved_at_0[0x8]; 9767 u8 pcie_index[0x8]; 9768 u8 reserved_at_10[0xa]; 9769 u8 grp[0x6]; 9770 9771 u8 clr[0x1]; 9772 u8 reserved_at_21[0x1f]; 9773 9774 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9775 }; 9776 9777 struct mlx5_ifc_ppad_reg_bits { 9778 u8 reserved_at_0[0x3]; 9779 u8 single_mac[0x1]; 9780 u8 reserved_at_4[0x4]; 9781 u8 local_port[0x8]; 9782 u8 mac_47_32[0x10]; 9783 9784 u8 mac_31_0[0x20]; 9785 9786 u8 reserved_at_40[0x40]; 9787 }; 9788 9789 struct mlx5_ifc_pmtu_reg_bits { 9790 u8 reserved_at_0[0x8]; 9791 u8 local_port[0x8]; 9792 u8 reserved_at_10[0x10]; 9793 9794 u8 max_mtu[0x10]; 9795 u8 reserved_at_30[0x10]; 9796 9797 u8 admin_mtu[0x10]; 9798 u8 reserved_at_50[0x10]; 9799 9800 u8 oper_mtu[0x10]; 9801 u8 reserved_at_70[0x10]; 9802 }; 9803 9804 struct mlx5_ifc_pmpr_reg_bits { 9805 u8 reserved_at_0[0x8]; 9806 u8 module[0x8]; 9807 u8 reserved_at_10[0x10]; 9808 9809 u8 reserved_at_20[0x18]; 9810 u8 attenuation_5g[0x8]; 9811 9812 u8 reserved_at_40[0x18]; 9813 u8 attenuation_7g[0x8]; 9814 9815 u8 reserved_at_60[0x18]; 9816 u8 attenuation_12g[0x8]; 9817 }; 9818 9819 struct mlx5_ifc_pmpe_reg_bits { 9820 u8 reserved_at_0[0x8]; 9821 u8 module[0x8]; 9822 u8 reserved_at_10[0xc]; 9823 u8 module_status[0x4]; 9824 9825 u8 reserved_at_20[0x60]; 9826 }; 9827 9828 struct mlx5_ifc_pmpc_reg_bits { 9829 u8 module_state_updated[32][0x8]; 9830 }; 9831 9832 struct mlx5_ifc_pmlpn_reg_bits { 9833 u8 reserved_at_0[0x4]; 9834 u8 mlpn_status[0x4]; 9835 u8 local_port[0x8]; 9836 u8 reserved_at_10[0x10]; 9837 9838 u8 e[0x1]; 9839 u8 reserved_at_21[0x1f]; 9840 }; 9841 9842 struct mlx5_ifc_pmlp_reg_bits { 9843 u8 rxtx[0x1]; 9844 u8 reserved_at_1[0x7]; 9845 u8 local_port[0x8]; 9846 u8 reserved_at_10[0x8]; 9847 u8 width[0x8]; 9848 9849 u8 lane0_module_mapping[0x20]; 9850 9851 u8 lane1_module_mapping[0x20]; 9852 9853 u8 lane2_module_mapping[0x20]; 9854 9855 u8 lane3_module_mapping[0x20]; 9856 9857 u8 reserved_at_a0[0x160]; 9858 }; 9859 9860 struct mlx5_ifc_pmaos_reg_bits { 9861 u8 reserved_at_0[0x8]; 9862 u8 module[0x8]; 9863 u8 reserved_at_10[0x4]; 9864 u8 admin_status[0x4]; 9865 u8 reserved_at_18[0x4]; 9866 u8 oper_status[0x4]; 9867 9868 u8 ase[0x1]; 9869 u8 ee[0x1]; 9870 u8 reserved_at_22[0x1c]; 9871 u8 e[0x2]; 9872 9873 u8 reserved_at_40[0x40]; 9874 }; 9875 9876 struct mlx5_ifc_plpc_reg_bits { 9877 u8 reserved_at_0[0x4]; 9878 u8 profile_id[0xc]; 9879 u8 reserved_at_10[0x4]; 9880 u8 proto_mask[0x4]; 9881 u8 reserved_at_18[0x8]; 9882 9883 u8 reserved_at_20[0x10]; 9884 u8 lane_speed[0x10]; 9885 9886 u8 reserved_at_40[0x17]; 9887 u8 lpbf[0x1]; 9888 u8 fec_mode_policy[0x8]; 9889 9890 u8 retransmission_capability[0x8]; 9891 u8 fec_mode_capability[0x18]; 9892 9893 u8 retransmission_support_admin[0x8]; 9894 u8 fec_mode_support_admin[0x18]; 9895 9896 u8 retransmission_request_admin[0x8]; 9897 u8 fec_mode_request_admin[0x18]; 9898 9899 u8 reserved_at_c0[0x80]; 9900 }; 9901 9902 struct mlx5_ifc_plib_reg_bits { 9903 u8 reserved_at_0[0x8]; 9904 u8 local_port[0x8]; 9905 u8 reserved_at_10[0x8]; 9906 u8 ib_port[0x8]; 9907 9908 u8 reserved_at_20[0x60]; 9909 }; 9910 9911 struct mlx5_ifc_plbf_reg_bits { 9912 u8 reserved_at_0[0x8]; 9913 u8 local_port[0x8]; 9914 u8 reserved_at_10[0xd]; 9915 u8 lbf_mode[0x3]; 9916 9917 u8 reserved_at_20[0x20]; 9918 }; 9919 9920 struct mlx5_ifc_pipg_reg_bits { 9921 u8 reserved_at_0[0x8]; 9922 u8 local_port[0x8]; 9923 u8 reserved_at_10[0x10]; 9924 9925 u8 dic[0x1]; 9926 u8 reserved_at_21[0x19]; 9927 u8 ipg[0x4]; 9928 u8 reserved_at_3e[0x2]; 9929 }; 9930 9931 struct mlx5_ifc_pifr_reg_bits { 9932 u8 reserved_at_0[0x8]; 9933 u8 local_port[0x8]; 9934 u8 reserved_at_10[0x10]; 9935 9936 u8 reserved_at_20[0xe0]; 9937 9938 u8 port_filter[8][0x20]; 9939 9940 u8 port_filter_update_en[8][0x20]; 9941 }; 9942 9943 struct mlx5_ifc_pfcc_reg_bits { 9944 u8 reserved_at_0[0x8]; 9945 u8 local_port[0x8]; 9946 u8 reserved_at_10[0xb]; 9947 u8 ppan_mask_n[0x1]; 9948 u8 minor_stall_mask[0x1]; 9949 u8 critical_stall_mask[0x1]; 9950 u8 reserved_at_1e[0x2]; 9951 9952 u8 ppan[0x4]; 9953 u8 reserved_at_24[0x4]; 9954 u8 prio_mask_tx[0x8]; 9955 u8 reserved_at_30[0x8]; 9956 u8 prio_mask_rx[0x8]; 9957 9958 u8 pptx[0x1]; 9959 u8 aptx[0x1]; 9960 u8 pptx_mask_n[0x1]; 9961 u8 reserved_at_43[0x5]; 9962 u8 pfctx[0x8]; 9963 u8 reserved_at_50[0x10]; 9964 9965 u8 pprx[0x1]; 9966 u8 aprx[0x1]; 9967 u8 pprx_mask_n[0x1]; 9968 u8 reserved_at_63[0x5]; 9969 u8 pfcrx[0x8]; 9970 u8 reserved_at_70[0x10]; 9971 9972 u8 device_stall_minor_watermark[0x10]; 9973 u8 device_stall_critical_watermark[0x10]; 9974 9975 u8 reserved_at_a0[0x60]; 9976 }; 9977 9978 struct mlx5_ifc_pelc_reg_bits { 9979 u8 op[0x4]; 9980 u8 reserved_at_4[0x4]; 9981 u8 local_port[0x8]; 9982 u8 reserved_at_10[0x10]; 9983 9984 u8 op_admin[0x8]; 9985 u8 op_capability[0x8]; 9986 u8 op_request[0x8]; 9987 u8 op_active[0x8]; 9988 9989 u8 admin[0x40]; 9990 9991 u8 capability[0x40]; 9992 9993 u8 request[0x40]; 9994 9995 u8 active[0x40]; 9996 9997 u8 reserved_at_140[0x80]; 9998 }; 9999 10000 struct mlx5_ifc_peir_reg_bits { 10001 u8 reserved_at_0[0x8]; 10002 u8 local_port[0x8]; 10003 u8 reserved_at_10[0x10]; 10004 10005 u8 reserved_at_20[0xc]; 10006 u8 error_count[0x4]; 10007 u8 reserved_at_30[0x10]; 10008 10009 u8 reserved_at_40[0xc]; 10010 u8 lane[0x4]; 10011 u8 reserved_at_50[0x8]; 10012 u8 error_type[0x8]; 10013 }; 10014 10015 struct mlx5_ifc_mpegc_reg_bits { 10016 u8 reserved_at_0[0x30]; 10017 u8 field_select[0x10]; 10018 10019 u8 tx_overflow_sense[0x1]; 10020 u8 mark_cqe[0x1]; 10021 u8 mark_cnp[0x1]; 10022 u8 reserved_at_43[0x1b]; 10023 u8 tx_lossy_overflow_oper[0x2]; 10024 10025 u8 reserved_at_60[0x100]; 10026 }; 10027 10028 enum { 10029 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10030 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10031 }; 10032 10033 enum { 10034 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10035 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10036 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10037 }; 10038 10039 struct mlx5_ifc_mtutc_reg_bits { 10040 u8 reserved_at_0[0x5]; 10041 u8 freq_adj_units[0x3]; 10042 u8 reserved_at_8[0x14]; 10043 u8 operation[0x4]; 10044 10045 u8 freq_adjustment[0x20]; 10046 10047 u8 reserved_at_40[0x40]; 10048 10049 u8 utc_sec[0x20]; 10050 10051 u8 reserved_at_a0[0x2]; 10052 u8 utc_nsec[0x1e]; 10053 10054 u8 time_adjustment[0x20]; 10055 }; 10056 10057 struct mlx5_ifc_pcam_enhanced_features_bits { 10058 u8 reserved_at_0[0x68]; 10059 u8 fec_50G_per_lane_in_pplm[0x1]; 10060 u8 reserved_at_69[0x4]; 10061 u8 rx_icrc_encapsulated_counter[0x1]; 10062 u8 reserved_at_6e[0x4]; 10063 u8 ptys_extended_ethernet[0x1]; 10064 u8 reserved_at_73[0x3]; 10065 u8 pfcc_mask[0x1]; 10066 u8 reserved_at_77[0x3]; 10067 u8 per_lane_error_counters[0x1]; 10068 u8 rx_buffer_fullness_counters[0x1]; 10069 u8 ptys_connector_type[0x1]; 10070 u8 reserved_at_7d[0x1]; 10071 u8 ppcnt_discard_group[0x1]; 10072 u8 ppcnt_statistical_group[0x1]; 10073 }; 10074 10075 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10076 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10077 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10078 10079 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10080 u8 pplm[0x1]; 10081 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10082 10083 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10084 u8 pbmc[0x1]; 10085 u8 pptb[0x1]; 10086 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10087 u8 ppcnt[0x1]; 10088 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10089 }; 10090 10091 struct mlx5_ifc_pcam_reg_bits { 10092 u8 reserved_at_0[0x8]; 10093 u8 feature_group[0x8]; 10094 u8 reserved_at_10[0x8]; 10095 u8 access_reg_group[0x8]; 10096 10097 u8 reserved_at_20[0x20]; 10098 10099 union { 10100 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10101 u8 reserved_at_0[0x80]; 10102 } port_access_reg_cap_mask; 10103 10104 u8 reserved_at_c0[0x80]; 10105 10106 union { 10107 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10108 u8 reserved_at_0[0x80]; 10109 } feature_cap_mask; 10110 10111 u8 reserved_at_1c0[0xc0]; 10112 }; 10113 10114 struct mlx5_ifc_mcam_enhanced_features_bits { 10115 u8 reserved_at_0[0x50]; 10116 u8 mtutc_freq_adj_units[0x1]; 10117 u8 mtutc_time_adjustment_extended_range[0x1]; 10118 u8 reserved_at_52[0xb]; 10119 u8 mcia_32dwords[0x1]; 10120 u8 out_pulse_duration_ns[0x1]; 10121 u8 npps_period[0x1]; 10122 u8 reserved_at_60[0xa]; 10123 u8 reset_state[0x1]; 10124 u8 ptpcyc2realtime_modify[0x1]; 10125 u8 reserved_at_6c[0x2]; 10126 u8 pci_status_and_power[0x1]; 10127 u8 reserved_at_6f[0x5]; 10128 u8 mark_tx_action_cnp[0x1]; 10129 u8 mark_tx_action_cqe[0x1]; 10130 u8 dynamic_tx_overflow[0x1]; 10131 u8 reserved_at_77[0x4]; 10132 u8 pcie_outbound_stalled[0x1]; 10133 u8 tx_overflow_buffer_pkt[0x1]; 10134 u8 mtpps_enh_out_per_adj[0x1]; 10135 u8 mtpps_fs[0x1]; 10136 u8 pcie_performance_group[0x1]; 10137 }; 10138 10139 struct mlx5_ifc_mcam_access_reg_bits { 10140 u8 reserved_at_0[0x1c]; 10141 u8 mcda[0x1]; 10142 u8 mcc[0x1]; 10143 u8 mcqi[0x1]; 10144 u8 mcqs[0x1]; 10145 10146 u8 regs_95_to_87[0x9]; 10147 u8 mpegc[0x1]; 10148 u8 mtutc[0x1]; 10149 u8 regs_84_to_68[0x11]; 10150 u8 tracer_registers[0x4]; 10151 10152 u8 regs_63_to_46[0x12]; 10153 u8 mrtc[0x1]; 10154 u8 regs_44_to_32[0xd]; 10155 10156 u8 regs_31_to_10[0x16]; 10157 u8 mtmp[0x1]; 10158 u8 regs_8_to_0[0x9]; 10159 }; 10160 10161 struct mlx5_ifc_mcam_access_reg_bits1 { 10162 u8 regs_127_to_96[0x20]; 10163 10164 u8 regs_95_to_64[0x20]; 10165 10166 u8 regs_63_to_32[0x20]; 10167 10168 u8 regs_31_to_0[0x20]; 10169 }; 10170 10171 struct mlx5_ifc_mcam_access_reg_bits2 { 10172 u8 regs_127_to_99[0x1d]; 10173 u8 mirc[0x1]; 10174 u8 regs_97_to_96[0x2]; 10175 10176 u8 regs_95_to_64[0x20]; 10177 10178 u8 regs_63_to_32[0x20]; 10179 10180 u8 regs_31_to_0[0x20]; 10181 }; 10182 10183 struct mlx5_ifc_mcam_reg_bits { 10184 u8 reserved_at_0[0x8]; 10185 u8 feature_group[0x8]; 10186 u8 reserved_at_10[0x8]; 10187 u8 access_reg_group[0x8]; 10188 10189 u8 reserved_at_20[0x20]; 10190 10191 union { 10192 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10193 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10194 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10195 u8 reserved_at_0[0x80]; 10196 } mng_access_reg_cap_mask; 10197 10198 u8 reserved_at_c0[0x80]; 10199 10200 union { 10201 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10202 u8 reserved_at_0[0x80]; 10203 } mng_feature_cap_mask; 10204 10205 u8 reserved_at_1c0[0x80]; 10206 }; 10207 10208 struct mlx5_ifc_qcam_access_reg_cap_mask { 10209 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10210 u8 qpdpm[0x1]; 10211 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10212 u8 qdpm[0x1]; 10213 u8 qpts[0x1]; 10214 u8 qcap[0x1]; 10215 u8 qcam_access_reg_cap_mask_0[0x1]; 10216 }; 10217 10218 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10219 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10220 u8 qpts_trust_both[0x1]; 10221 }; 10222 10223 struct mlx5_ifc_qcam_reg_bits { 10224 u8 reserved_at_0[0x8]; 10225 u8 feature_group[0x8]; 10226 u8 reserved_at_10[0x8]; 10227 u8 access_reg_group[0x8]; 10228 u8 reserved_at_20[0x20]; 10229 10230 union { 10231 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10232 u8 reserved_at_0[0x80]; 10233 } qos_access_reg_cap_mask; 10234 10235 u8 reserved_at_c0[0x80]; 10236 10237 union { 10238 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10239 u8 reserved_at_0[0x80]; 10240 } qos_feature_cap_mask; 10241 10242 u8 reserved_at_1c0[0x80]; 10243 }; 10244 10245 struct mlx5_ifc_core_dump_reg_bits { 10246 u8 reserved_at_0[0x18]; 10247 u8 core_dump_type[0x8]; 10248 10249 u8 reserved_at_20[0x30]; 10250 u8 vhca_id[0x10]; 10251 10252 u8 reserved_at_60[0x8]; 10253 u8 qpn[0x18]; 10254 u8 reserved_at_80[0x180]; 10255 }; 10256 10257 struct mlx5_ifc_pcap_reg_bits { 10258 u8 reserved_at_0[0x8]; 10259 u8 local_port[0x8]; 10260 u8 reserved_at_10[0x10]; 10261 10262 u8 port_capability_mask[4][0x20]; 10263 }; 10264 10265 struct mlx5_ifc_paos_reg_bits { 10266 u8 swid[0x8]; 10267 u8 local_port[0x8]; 10268 u8 reserved_at_10[0x4]; 10269 u8 admin_status[0x4]; 10270 u8 reserved_at_18[0x4]; 10271 u8 oper_status[0x4]; 10272 10273 u8 ase[0x1]; 10274 u8 ee[0x1]; 10275 u8 reserved_at_22[0x1c]; 10276 u8 e[0x2]; 10277 10278 u8 reserved_at_40[0x40]; 10279 }; 10280 10281 struct mlx5_ifc_pamp_reg_bits { 10282 u8 reserved_at_0[0x8]; 10283 u8 opamp_group[0x8]; 10284 u8 reserved_at_10[0xc]; 10285 u8 opamp_group_type[0x4]; 10286 10287 u8 start_index[0x10]; 10288 u8 reserved_at_30[0x4]; 10289 u8 num_of_indices[0xc]; 10290 10291 u8 index_data[18][0x10]; 10292 }; 10293 10294 struct mlx5_ifc_pcmr_reg_bits { 10295 u8 reserved_at_0[0x8]; 10296 u8 local_port[0x8]; 10297 u8 reserved_at_10[0x10]; 10298 10299 u8 entropy_force_cap[0x1]; 10300 u8 entropy_calc_cap[0x1]; 10301 u8 entropy_gre_calc_cap[0x1]; 10302 u8 reserved_at_23[0xf]; 10303 u8 rx_ts_over_crc_cap[0x1]; 10304 u8 reserved_at_33[0xb]; 10305 u8 fcs_cap[0x1]; 10306 u8 reserved_at_3f[0x1]; 10307 10308 u8 entropy_force[0x1]; 10309 u8 entropy_calc[0x1]; 10310 u8 entropy_gre_calc[0x1]; 10311 u8 reserved_at_43[0xf]; 10312 u8 rx_ts_over_crc[0x1]; 10313 u8 reserved_at_53[0xb]; 10314 u8 fcs_chk[0x1]; 10315 u8 reserved_at_5f[0x1]; 10316 }; 10317 10318 struct mlx5_ifc_lane_2_module_mapping_bits { 10319 u8 reserved_at_0[0x4]; 10320 u8 rx_lane[0x4]; 10321 u8 reserved_at_8[0x4]; 10322 u8 tx_lane[0x4]; 10323 u8 reserved_at_10[0x8]; 10324 u8 module[0x8]; 10325 }; 10326 10327 struct mlx5_ifc_bufferx_reg_bits { 10328 u8 reserved_at_0[0x6]; 10329 u8 lossy[0x1]; 10330 u8 epsb[0x1]; 10331 u8 reserved_at_8[0x8]; 10332 u8 size[0x10]; 10333 10334 u8 xoff_threshold[0x10]; 10335 u8 xon_threshold[0x10]; 10336 }; 10337 10338 struct mlx5_ifc_set_node_in_bits { 10339 u8 node_description[64][0x8]; 10340 }; 10341 10342 struct mlx5_ifc_register_power_settings_bits { 10343 u8 reserved_at_0[0x18]; 10344 u8 power_settings_level[0x8]; 10345 10346 u8 reserved_at_20[0x60]; 10347 }; 10348 10349 struct mlx5_ifc_register_host_endianness_bits { 10350 u8 he[0x1]; 10351 u8 reserved_at_1[0x1f]; 10352 10353 u8 reserved_at_20[0x60]; 10354 }; 10355 10356 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10357 u8 reserved_at_0[0x20]; 10358 10359 u8 mkey[0x20]; 10360 10361 u8 addressh_63_32[0x20]; 10362 10363 u8 addressl_31_0[0x20]; 10364 }; 10365 10366 struct mlx5_ifc_ud_adrs_vector_bits { 10367 u8 dc_key[0x40]; 10368 10369 u8 ext[0x1]; 10370 u8 reserved_at_41[0x7]; 10371 u8 destination_qp_dct[0x18]; 10372 10373 u8 static_rate[0x4]; 10374 u8 sl_eth_prio[0x4]; 10375 u8 fl[0x1]; 10376 u8 mlid[0x7]; 10377 u8 rlid_udp_sport[0x10]; 10378 10379 u8 reserved_at_80[0x20]; 10380 10381 u8 rmac_47_16[0x20]; 10382 10383 u8 rmac_15_0[0x10]; 10384 u8 tclass[0x8]; 10385 u8 hop_limit[0x8]; 10386 10387 u8 reserved_at_e0[0x1]; 10388 u8 grh[0x1]; 10389 u8 reserved_at_e2[0x2]; 10390 u8 src_addr_index[0x8]; 10391 u8 flow_label[0x14]; 10392 10393 u8 rgid_rip[16][0x8]; 10394 }; 10395 10396 struct mlx5_ifc_pages_req_event_bits { 10397 u8 reserved_at_0[0x10]; 10398 u8 function_id[0x10]; 10399 10400 u8 num_pages[0x20]; 10401 10402 u8 reserved_at_40[0xa0]; 10403 }; 10404 10405 struct mlx5_ifc_eqe_bits { 10406 u8 reserved_at_0[0x8]; 10407 u8 event_type[0x8]; 10408 u8 reserved_at_10[0x8]; 10409 u8 event_sub_type[0x8]; 10410 10411 u8 reserved_at_20[0xe0]; 10412 10413 union mlx5_ifc_event_auto_bits event_data; 10414 10415 u8 reserved_at_1e0[0x10]; 10416 u8 signature[0x8]; 10417 u8 reserved_at_1f8[0x7]; 10418 u8 owner[0x1]; 10419 }; 10420 10421 enum { 10422 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10423 }; 10424 10425 struct mlx5_ifc_cmd_queue_entry_bits { 10426 u8 type[0x8]; 10427 u8 reserved_at_8[0x18]; 10428 10429 u8 input_length[0x20]; 10430 10431 u8 input_mailbox_pointer_63_32[0x20]; 10432 10433 u8 input_mailbox_pointer_31_9[0x17]; 10434 u8 reserved_at_77[0x9]; 10435 10436 u8 command_input_inline_data[16][0x8]; 10437 10438 u8 command_output_inline_data[16][0x8]; 10439 10440 u8 output_mailbox_pointer_63_32[0x20]; 10441 10442 u8 output_mailbox_pointer_31_9[0x17]; 10443 u8 reserved_at_1b7[0x9]; 10444 10445 u8 output_length[0x20]; 10446 10447 u8 token[0x8]; 10448 u8 signature[0x8]; 10449 u8 reserved_at_1f0[0x8]; 10450 u8 status[0x7]; 10451 u8 ownership[0x1]; 10452 }; 10453 10454 struct mlx5_ifc_cmd_out_bits { 10455 u8 status[0x8]; 10456 u8 reserved_at_8[0x18]; 10457 10458 u8 syndrome[0x20]; 10459 10460 u8 command_output[0x20]; 10461 }; 10462 10463 struct mlx5_ifc_cmd_in_bits { 10464 u8 opcode[0x10]; 10465 u8 reserved_at_10[0x10]; 10466 10467 u8 reserved_at_20[0x10]; 10468 u8 op_mod[0x10]; 10469 10470 u8 command[][0x20]; 10471 }; 10472 10473 struct mlx5_ifc_cmd_if_box_bits { 10474 u8 mailbox_data[512][0x8]; 10475 10476 u8 reserved_at_1000[0x180]; 10477 10478 u8 next_pointer_63_32[0x20]; 10479 10480 u8 next_pointer_31_10[0x16]; 10481 u8 reserved_at_11b6[0xa]; 10482 10483 u8 block_number[0x20]; 10484 10485 u8 reserved_at_11e0[0x8]; 10486 u8 token[0x8]; 10487 u8 ctrl_signature[0x8]; 10488 u8 signature[0x8]; 10489 }; 10490 10491 struct mlx5_ifc_mtt_bits { 10492 u8 ptag_63_32[0x20]; 10493 10494 u8 ptag_31_8[0x18]; 10495 u8 reserved_at_38[0x6]; 10496 u8 wr_en[0x1]; 10497 u8 rd_en[0x1]; 10498 }; 10499 10500 struct mlx5_ifc_query_wol_rol_out_bits { 10501 u8 status[0x8]; 10502 u8 reserved_at_8[0x18]; 10503 10504 u8 syndrome[0x20]; 10505 10506 u8 reserved_at_40[0x10]; 10507 u8 rol_mode[0x8]; 10508 u8 wol_mode[0x8]; 10509 10510 u8 reserved_at_60[0x20]; 10511 }; 10512 10513 struct mlx5_ifc_query_wol_rol_in_bits { 10514 u8 opcode[0x10]; 10515 u8 reserved_at_10[0x10]; 10516 10517 u8 reserved_at_20[0x10]; 10518 u8 op_mod[0x10]; 10519 10520 u8 reserved_at_40[0x40]; 10521 }; 10522 10523 struct mlx5_ifc_set_wol_rol_out_bits { 10524 u8 status[0x8]; 10525 u8 reserved_at_8[0x18]; 10526 10527 u8 syndrome[0x20]; 10528 10529 u8 reserved_at_40[0x40]; 10530 }; 10531 10532 struct mlx5_ifc_set_wol_rol_in_bits { 10533 u8 opcode[0x10]; 10534 u8 reserved_at_10[0x10]; 10535 10536 u8 reserved_at_20[0x10]; 10537 u8 op_mod[0x10]; 10538 10539 u8 rol_mode_valid[0x1]; 10540 u8 wol_mode_valid[0x1]; 10541 u8 reserved_at_42[0xe]; 10542 u8 rol_mode[0x8]; 10543 u8 wol_mode[0x8]; 10544 10545 u8 reserved_at_60[0x20]; 10546 }; 10547 10548 enum { 10549 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10550 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10551 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10552 }; 10553 10554 enum { 10555 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10556 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10557 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10558 }; 10559 10560 enum { 10561 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10562 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10563 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10564 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10565 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10566 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10567 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10568 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10569 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10570 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10571 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10572 }; 10573 10574 struct mlx5_ifc_initial_seg_bits { 10575 u8 fw_rev_minor[0x10]; 10576 u8 fw_rev_major[0x10]; 10577 10578 u8 cmd_interface_rev[0x10]; 10579 u8 fw_rev_subminor[0x10]; 10580 10581 u8 reserved_at_40[0x40]; 10582 10583 u8 cmdq_phy_addr_63_32[0x20]; 10584 10585 u8 cmdq_phy_addr_31_12[0x14]; 10586 u8 reserved_at_b4[0x2]; 10587 u8 nic_interface[0x2]; 10588 u8 log_cmdq_size[0x4]; 10589 u8 log_cmdq_stride[0x4]; 10590 10591 u8 command_doorbell_vector[0x20]; 10592 10593 u8 reserved_at_e0[0xf00]; 10594 10595 u8 initializing[0x1]; 10596 u8 reserved_at_fe1[0x4]; 10597 u8 nic_interface_supported[0x3]; 10598 u8 embedded_cpu[0x1]; 10599 u8 reserved_at_fe9[0x17]; 10600 10601 struct mlx5_ifc_health_buffer_bits health_buffer; 10602 10603 u8 no_dram_nic_offset[0x20]; 10604 10605 u8 reserved_at_1220[0x6e40]; 10606 10607 u8 reserved_at_8060[0x1f]; 10608 u8 clear_int[0x1]; 10609 10610 u8 health_syndrome[0x8]; 10611 u8 health_counter[0x18]; 10612 10613 u8 reserved_at_80a0[0x17fc0]; 10614 }; 10615 10616 struct mlx5_ifc_mtpps_reg_bits { 10617 u8 reserved_at_0[0xc]; 10618 u8 cap_number_of_pps_pins[0x4]; 10619 u8 reserved_at_10[0x4]; 10620 u8 cap_max_num_of_pps_in_pins[0x4]; 10621 u8 reserved_at_18[0x4]; 10622 u8 cap_max_num_of_pps_out_pins[0x4]; 10623 10624 u8 reserved_at_20[0x13]; 10625 u8 cap_log_min_npps_period[0x5]; 10626 u8 reserved_at_38[0x3]; 10627 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10628 10629 u8 reserved_at_40[0x4]; 10630 u8 cap_pin_3_mode[0x4]; 10631 u8 reserved_at_48[0x4]; 10632 u8 cap_pin_2_mode[0x4]; 10633 u8 reserved_at_50[0x4]; 10634 u8 cap_pin_1_mode[0x4]; 10635 u8 reserved_at_58[0x4]; 10636 u8 cap_pin_0_mode[0x4]; 10637 10638 u8 reserved_at_60[0x4]; 10639 u8 cap_pin_7_mode[0x4]; 10640 u8 reserved_at_68[0x4]; 10641 u8 cap_pin_6_mode[0x4]; 10642 u8 reserved_at_70[0x4]; 10643 u8 cap_pin_5_mode[0x4]; 10644 u8 reserved_at_78[0x4]; 10645 u8 cap_pin_4_mode[0x4]; 10646 10647 u8 field_select[0x20]; 10648 u8 reserved_at_a0[0x20]; 10649 10650 u8 npps_period[0x40]; 10651 10652 u8 enable[0x1]; 10653 u8 reserved_at_101[0xb]; 10654 u8 pattern[0x4]; 10655 u8 reserved_at_110[0x4]; 10656 u8 pin_mode[0x4]; 10657 u8 pin[0x8]; 10658 10659 u8 reserved_at_120[0x2]; 10660 u8 out_pulse_duration_ns[0x1e]; 10661 10662 u8 time_stamp[0x40]; 10663 10664 u8 out_pulse_duration[0x10]; 10665 u8 out_periodic_adjustment[0x10]; 10666 u8 enhanced_out_periodic_adjustment[0x20]; 10667 10668 u8 reserved_at_1c0[0x20]; 10669 }; 10670 10671 struct mlx5_ifc_mtppse_reg_bits { 10672 u8 reserved_at_0[0x18]; 10673 u8 pin[0x8]; 10674 u8 event_arm[0x1]; 10675 u8 reserved_at_21[0x1b]; 10676 u8 event_generation_mode[0x4]; 10677 u8 reserved_at_40[0x40]; 10678 }; 10679 10680 struct mlx5_ifc_mcqs_reg_bits { 10681 u8 last_index_flag[0x1]; 10682 u8 reserved_at_1[0x7]; 10683 u8 fw_device[0x8]; 10684 u8 component_index[0x10]; 10685 10686 u8 reserved_at_20[0x10]; 10687 u8 identifier[0x10]; 10688 10689 u8 reserved_at_40[0x17]; 10690 u8 component_status[0x5]; 10691 u8 component_update_state[0x4]; 10692 10693 u8 last_update_state_changer_type[0x4]; 10694 u8 last_update_state_changer_host_id[0x4]; 10695 u8 reserved_at_68[0x18]; 10696 }; 10697 10698 struct mlx5_ifc_mcqi_cap_bits { 10699 u8 supported_info_bitmask[0x20]; 10700 10701 u8 component_size[0x20]; 10702 10703 u8 max_component_size[0x20]; 10704 10705 u8 log_mcda_word_size[0x4]; 10706 u8 reserved_at_64[0xc]; 10707 u8 mcda_max_write_size[0x10]; 10708 10709 u8 rd_en[0x1]; 10710 u8 reserved_at_81[0x1]; 10711 u8 match_chip_id[0x1]; 10712 u8 match_psid[0x1]; 10713 u8 check_user_timestamp[0x1]; 10714 u8 match_base_guid_mac[0x1]; 10715 u8 reserved_at_86[0x1a]; 10716 }; 10717 10718 struct mlx5_ifc_mcqi_version_bits { 10719 u8 reserved_at_0[0x2]; 10720 u8 build_time_valid[0x1]; 10721 u8 user_defined_time_valid[0x1]; 10722 u8 reserved_at_4[0x14]; 10723 u8 version_string_length[0x8]; 10724 10725 u8 version[0x20]; 10726 10727 u8 build_time[0x40]; 10728 10729 u8 user_defined_time[0x40]; 10730 10731 u8 build_tool_version[0x20]; 10732 10733 u8 reserved_at_e0[0x20]; 10734 10735 u8 version_string[92][0x8]; 10736 }; 10737 10738 struct mlx5_ifc_mcqi_activation_method_bits { 10739 u8 pending_server_ac_power_cycle[0x1]; 10740 u8 pending_server_dc_power_cycle[0x1]; 10741 u8 pending_server_reboot[0x1]; 10742 u8 pending_fw_reset[0x1]; 10743 u8 auto_activate[0x1]; 10744 u8 all_hosts_sync[0x1]; 10745 u8 device_hw_reset[0x1]; 10746 u8 reserved_at_7[0x19]; 10747 }; 10748 10749 union mlx5_ifc_mcqi_reg_data_bits { 10750 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10751 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10752 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10753 }; 10754 10755 struct mlx5_ifc_mcqi_reg_bits { 10756 u8 read_pending_component[0x1]; 10757 u8 reserved_at_1[0xf]; 10758 u8 component_index[0x10]; 10759 10760 u8 reserved_at_20[0x20]; 10761 10762 u8 reserved_at_40[0x1b]; 10763 u8 info_type[0x5]; 10764 10765 u8 info_size[0x20]; 10766 10767 u8 offset[0x20]; 10768 10769 u8 reserved_at_a0[0x10]; 10770 u8 data_size[0x10]; 10771 10772 union mlx5_ifc_mcqi_reg_data_bits data[]; 10773 }; 10774 10775 struct mlx5_ifc_mcc_reg_bits { 10776 u8 reserved_at_0[0x4]; 10777 u8 time_elapsed_since_last_cmd[0xc]; 10778 u8 reserved_at_10[0x8]; 10779 u8 instruction[0x8]; 10780 10781 u8 reserved_at_20[0x10]; 10782 u8 component_index[0x10]; 10783 10784 u8 reserved_at_40[0x8]; 10785 u8 update_handle[0x18]; 10786 10787 u8 handle_owner_type[0x4]; 10788 u8 handle_owner_host_id[0x4]; 10789 u8 reserved_at_68[0x1]; 10790 u8 control_progress[0x7]; 10791 u8 error_code[0x8]; 10792 u8 reserved_at_78[0x4]; 10793 u8 control_state[0x4]; 10794 10795 u8 component_size[0x20]; 10796 10797 u8 reserved_at_a0[0x60]; 10798 }; 10799 10800 struct mlx5_ifc_mcda_reg_bits { 10801 u8 reserved_at_0[0x8]; 10802 u8 update_handle[0x18]; 10803 10804 u8 offset[0x20]; 10805 10806 u8 reserved_at_40[0x10]; 10807 u8 size[0x10]; 10808 10809 u8 reserved_at_60[0x20]; 10810 10811 u8 data[][0x20]; 10812 }; 10813 10814 enum { 10815 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10816 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10817 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10818 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10819 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10820 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10821 }; 10822 10823 enum { 10824 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10825 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10826 }; 10827 10828 enum { 10829 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10830 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10831 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10832 }; 10833 10834 struct mlx5_ifc_mfrl_reg_bits { 10835 u8 reserved_at_0[0x20]; 10836 10837 u8 reserved_at_20[0x2]; 10838 u8 pci_sync_for_fw_update_start[0x1]; 10839 u8 pci_sync_for_fw_update_resp[0x2]; 10840 u8 rst_type_sel[0x3]; 10841 u8 reserved_at_28[0x4]; 10842 u8 reset_state[0x4]; 10843 u8 reset_type[0x8]; 10844 u8 reset_level[0x8]; 10845 }; 10846 10847 struct mlx5_ifc_mirc_reg_bits { 10848 u8 reserved_at_0[0x18]; 10849 u8 status_code[0x8]; 10850 10851 u8 reserved_at_20[0x20]; 10852 }; 10853 10854 struct mlx5_ifc_pddr_monitor_opcode_bits { 10855 u8 reserved_at_0[0x10]; 10856 u8 monitor_opcode[0x10]; 10857 }; 10858 10859 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10860 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10861 u8 reserved_at_0[0x20]; 10862 }; 10863 10864 enum { 10865 /* Monitor opcodes */ 10866 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10867 }; 10868 10869 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10870 u8 reserved_at_0[0x10]; 10871 u8 group_opcode[0x10]; 10872 10873 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10874 10875 u8 reserved_at_40[0x20]; 10876 10877 u8 status_message[59][0x20]; 10878 }; 10879 10880 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10881 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10882 u8 reserved_at_0[0x7c0]; 10883 }; 10884 10885 enum { 10886 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10887 }; 10888 10889 struct mlx5_ifc_pddr_reg_bits { 10890 u8 reserved_at_0[0x8]; 10891 u8 local_port[0x8]; 10892 u8 pnat[0x2]; 10893 u8 reserved_at_12[0xe]; 10894 10895 u8 reserved_at_20[0x18]; 10896 u8 page_select[0x8]; 10897 10898 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10899 }; 10900 10901 struct mlx5_ifc_mrtc_reg_bits { 10902 u8 time_synced[0x1]; 10903 u8 reserved_at_1[0x1f]; 10904 10905 u8 reserved_at_20[0x20]; 10906 10907 u8 time_h[0x20]; 10908 10909 u8 time_l[0x20]; 10910 }; 10911 10912 struct mlx5_ifc_mtcap_reg_bits { 10913 u8 reserved_at_0[0x19]; 10914 u8 sensor_count[0x7]; 10915 10916 u8 reserved_at_20[0x20]; 10917 10918 u8 sensor_map[0x40]; 10919 }; 10920 10921 struct mlx5_ifc_mtmp_reg_bits { 10922 u8 reserved_at_0[0x14]; 10923 u8 sensor_index[0xc]; 10924 10925 u8 reserved_at_20[0x10]; 10926 u8 temperature[0x10]; 10927 10928 u8 mte[0x1]; 10929 u8 mtr[0x1]; 10930 u8 reserved_at_42[0xe]; 10931 u8 max_temperature[0x10]; 10932 10933 u8 tee[0x2]; 10934 u8 reserved_at_62[0xe]; 10935 u8 temp_threshold_hi[0x10]; 10936 10937 u8 reserved_at_80[0x10]; 10938 u8 temp_threshold_lo[0x10]; 10939 10940 u8 reserved_at_a0[0x20]; 10941 10942 u8 sensor_name_hi[0x20]; 10943 u8 sensor_name_lo[0x20]; 10944 }; 10945 10946 union mlx5_ifc_ports_control_registers_document_bits { 10947 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10948 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10949 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10950 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10951 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10952 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10953 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10954 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10955 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10956 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10957 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10958 struct mlx5_ifc_paos_reg_bits paos_reg; 10959 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10960 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10961 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10962 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10963 struct mlx5_ifc_peir_reg_bits peir_reg; 10964 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10965 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10966 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10967 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10968 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10969 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10970 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10971 struct mlx5_ifc_plib_reg_bits plib_reg; 10972 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10973 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10974 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10975 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10976 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10977 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10978 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10979 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10980 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10981 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10982 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10983 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10984 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10985 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10986 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10987 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10988 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10989 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10990 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10991 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10992 struct mlx5_ifc_pude_reg_bits pude_reg; 10993 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10994 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10995 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10996 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10997 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10998 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10999 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11000 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11001 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11002 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11003 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11004 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11005 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11006 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11007 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11008 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11009 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11010 u8 reserved_at_0[0x60e0]; 11011 }; 11012 11013 union mlx5_ifc_debug_enhancements_document_bits { 11014 struct mlx5_ifc_health_buffer_bits health_buffer; 11015 u8 reserved_at_0[0x200]; 11016 }; 11017 11018 union mlx5_ifc_uplink_pci_interface_document_bits { 11019 struct mlx5_ifc_initial_seg_bits initial_seg; 11020 u8 reserved_at_0[0x20060]; 11021 }; 11022 11023 struct mlx5_ifc_set_flow_table_root_out_bits { 11024 u8 status[0x8]; 11025 u8 reserved_at_8[0x18]; 11026 11027 u8 syndrome[0x20]; 11028 11029 u8 reserved_at_40[0x40]; 11030 }; 11031 11032 struct mlx5_ifc_set_flow_table_root_in_bits { 11033 u8 opcode[0x10]; 11034 u8 reserved_at_10[0x10]; 11035 11036 u8 reserved_at_20[0x10]; 11037 u8 op_mod[0x10]; 11038 11039 u8 other_vport[0x1]; 11040 u8 reserved_at_41[0xf]; 11041 u8 vport_number[0x10]; 11042 11043 u8 reserved_at_60[0x20]; 11044 11045 u8 table_type[0x8]; 11046 u8 reserved_at_88[0x7]; 11047 u8 table_of_other_vport[0x1]; 11048 u8 table_vport_number[0x10]; 11049 11050 u8 reserved_at_a0[0x8]; 11051 u8 table_id[0x18]; 11052 11053 u8 reserved_at_c0[0x8]; 11054 u8 underlay_qpn[0x18]; 11055 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11056 u8 reserved_at_e1[0xf]; 11057 u8 table_eswitch_owner_vhca_id[0x10]; 11058 u8 reserved_at_100[0x100]; 11059 }; 11060 11061 enum { 11062 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11063 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11064 }; 11065 11066 struct mlx5_ifc_modify_flow_table_out_bits { 11067 u8 status[0x8]; 11068 u8 reserved_at_8[0x18]; 11069 11070 u8 syndrome[0x20]; 11071 11072 u8 reserved_at_40[0x40]; 11073 }; 11074 11075 struct mlx5_ifc_modify_flow_table_in_bits { 11076 u8 opcode[0x10]; 11077 u8 reserved_at_10[0x10]; 11078 11079 u8 reserved_at_20[0x10]; 11080 u8 op_mod[0x10]; 11081 11082 u8 other_vport[0x1]; 11083 u8 reserved_at_41[0xf]; 11084 u8 vport_number[0x10]; 11085 11086 u8 reserved_at_60[0x10]; 11087 u8 modify_field_select[0x10]; 11088 11089 u8 table_type[0x8]; 11090 u8 reserved_at_88[0x18]; 11091 11092 u8 reserved_at_a0[0x8]; 11093 u8 table_id[0x18]; 11094 11095 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11096 }; 11097 11098 struct mlx5_ifc_ets_tcn_config_reg_bits { 11099 u8 g[0x1]; 11100 u8 b[0x1]; 11101 u8 r[0x1]; 11102 u8 reserved_at_3[0x9]; 11103 u8 group[0x4]; 11104 u8 reserved_at_10[0x9]; 11105 u8 bw_allocation[0x7]; 11106 11107 u8 reserved_at_20[0xc]; 11108 u8 max_bw_units[0x4]; 11109 u8 reserved_at_30[0x8]; 11110 u8 max_bw_value[0x8]; 11111 }; 11112 11113 struct mlx5_ifc_ets_global_config_reg_bits { 11114 u8 reserved_at_0[0x2]; 11115 u8 r[0x1]; 11116 u8 reserved_at_3[0x1d]; 11117 11118 u8 reserved_at_20[0xc]; 11119 u8 max_bw_units[0x4]; 11120 u8 reserved_at_30[0x8]; 11121 u8 max_bw_value[0x8]; 11122 }; 11123 11124 struct mlx5_ifc_qetc_reg_bits { 11125 u8 reserved_at_0[0x8]; 11126 u8 port_number[0x8]; 11127 u8 reserved_at_10[0x30]; 11128 11129 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11130 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11131 }; 11132 11133 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11134 u8 e[0x1]; 11135 u8 reserved_at_01[0x0b]; 11136 u8 prio[0x04]; 11137 }; 11138 11139 struct mlx5_ifc_qpdpm_reg_bits { 11140 u8 reserved_at_0[0x8]; 11141 u8 local_port[0x8]; 11142 u8 reserved_at_10[0x10]; 11143 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11144 }; 11145 11146 struct mlx5_ifc_qpts_reg_bits { 11147 u8 reserved_at_0[0x8]; 11148 u8 local_port[0x8]; 11149 u8 reserved_at_10[0x2d]; 11150 u8 trust_state[0x3]; 11151 }; 11152 11153 struct mlx5_ifc_pptb_reg_bits { 11154 u8 reserved_at_0[0x2]; 11155 u8 mm[0x2]; 11156 u8 reserved_at_4[0x4]; 11157 u8 local_port[0x8]; 11158 u8 reserved_at_10[0x6]; 11159 u8 cm[0x1]; 11160 u8 um[0x1]; 11161 u8 pm[0x8]; 11162 11163 u8 prio_x_buff[0x20]; 11164 11165 u8 pm_msb[0x8]; 11166 u8 reserved_at_48[0x10]; 11167 u8 ctrl_buff[0x4]; 11168 u8 untagged_buff[0x4]; 11169 }; 11170 11171 struct mlx5_ifc_sbcam_reg_bits { 11172 u8 reserved_at_0[0x8]; 11173 u8 feature_group[0x8]; 11174 u8 reserved_at_10[0x8]; 11175 u8 access_reg_group[0x8]; 11176 11177 u8 reserved_at_20[0x20]; 11178 11179 u8 sb_access_reg_cap_mask[4][0x20]; 11180 11181 u8 reserved_at_c0[0x80]; 11182 11183 u8 sb_feature_cap_mask[4][0x20]; 11184 11185 u8 reserved_at_1c0[0x40]; 11186 11187 u8 cap_total_buffer_size[0x20]; 11188 11189 u8 cap_cell_size[0x10]; 11190 u8 cap_max_pg_buffers[0x8]; 11191 u8 cap_num_pool_supported[0x8]; 11192 11193 u8 reserved_at_240[0x8]; 11194 u8 cap_sbsr_stat_size[0x8]; 11195 u8 cap_max_tclass_data[0x8]; 11196 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11197 }; 11198 11199 struct mlx5_ifc_pbmc_reg_bits { 11200 u8 reserved_at_0[0x8]; 11201 u8 local_port[0x8]; 11202 u8 reserved_at_10[0x10]; 11203 11204 u8 xoff_timer_value[0x10]; 11205 u8 xoff_refresh[0x10]; 11206 11207 u8 reserved_at_40[0x9]; 11208 u8 fullness_threshold[0x7]; 11209 u8 port_buffer_size[0x10]; 11210 11211 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11212 11213 u8 reserved_at_2e0[0x80]; 11214 }; 11215 11216 struct mlx5_ifc_sbpr_reg_bits { 11217 u8 desc[0x1]; 11218 u8 snap[0x1]; 11219 u8 reserved_at_2[0x4]; 11220 u8 dir[0x2]; 11221 u8 reserved_at_8[0x14]; 11222 u8 pool[0x4]; 11223 11224 u8 infi_size[0x1]; 11225 u8 reserved_at_21[0x7]; 11226 u8 size[0x18]; 11227 11228 u8 reserved_at_40[0x1c]; 11229 u8 mode[0x4]; 11230 11231 u8 reserved_at_60[0x8]; 11232 u8 buff_occupancy[0x18]; 11233 11234 u8 clr[0x1]; 11235 u8 reserved_at_81[0x7]; 11236 u8 max_buff_occupancy[0x18]; 11237 11238 u8 reserved_at_a0[0x8]; 11239 u8 ext_buff_occupancy[0x18]; 11240 }; 11241 11242 struct mlx5_ifc_sbcm_reg_bits { 11243 u8 desc[0x1]; 11244 u8 snap[0x1]; 11245 u8 reserved_at_2[0x6]; 11246 u8 local_port[0x8]; 11247 u8 pnat[0x2]; 11248 u8 pg_buff[0x6]; 11249 u8 reserved_at_18[0x6]; 11250 u8 dir[0x2]; 11251 11252 u8 reserved_at_20[0x1f]; 11253 u8 exc[0x1]; 11254 11255 u8 reserved_at_40[0x40]; 11256 11257 u8 reserved_at_80[0x8]; 11258 u8 buff_occupancy[0x18]; 11259 11260 u8 clr[0x1]; 11261 u8 reserved_at_a1[0x7]; 11262 u8 max_buff_occupancy[0x18]; 11263 11264 u8 reserved_at_c0[0x8]; 11265 u8 min_buff[0x18]; 11266 11267 u8 infi_max[0x1]; 11268 u8 reserved_at_e1[0x7]; 11269 u8 max_buff[0x18]; 11270 11271 u8 reserved_at_100[0x20]; 11272 11273 u8 reserved_at_120[0x1c]; 11274 u8 pool[0x4]; 11275 }; 11276 11277 struct mlx5_ifc_qtct_reg_bits { 11278 u8 reserved_at_0[0x8]; 11279 u8 port_number[0x8]; 11280 u8 reserved_at_10[0xd]; 11281 u8 prio[0x3]; 11282 11283 u8 reserved_at_20[0x1d]; 11284 u8 tclass[0x3]; 11285 }; 11286 11287 struct mlx5_ifc_mcia_reg_bits { 11288 u8 l[0x1]; 11289 u8 reserved_at_1[0x7]; 11290 u8 module[0x8]; 11291 u8 reserved_at_10[0x8]; 11292 u8 status[0x8]; 11293 11294 u8 i2c_device_address[0x8]; 11295 u8 page_number[0x8]; 11296 u8 device_address[0x10]; 11297 11298 u8 reserved_at_40[0x10]; 11299 u8 size[0x10]; 11300 11301 u8 reserved_at_60[0x20]; 11302 11303 u8 dword_0[0x20]; 11304 u8 dword_1[0x20]; 11305 u8 dword_2[0x20]; 11306 u8 dword_3[0x20]; 11307 u8 dword_4[0x20]; 11308 u8 dword_5[0x20]; 11309 u8 dword_6[0x20]; 11310 u8 dword_7[0x20]; 11311 u8 dword_8[0x20]; 11312 u8 dword_9[0x20]; 11313 u8 dword_10[0x20]; 11314 u8 dword_11[0x20]; 11315 }; 11316 11317 struct mlx5_ifc_dcbx_param_bits { 11318 u8 dcbx_cee_cap[0x1]; 11319 u8 dcbx_ieee_cap[0x1]; 11320 u8 dcbx_standby_cap[0x1]; 11321 u8 reserved_at_3[0x5]; 11322 u8 port_number[0x8]; 11323 u8 reserved_at_10[0xa]; 11324 u8 max_application_table_size[6]; 11325 u8 reserved_at_20[0x15]; 11326 u8 version_oper[0x3]; 11327 u8 reserved_at_38[5]; 11328 u8 version_admin[0x3]; 11329 u8 willing_admin[0x1]; 11330 u8 reserved_at_41[0x3]; 11331 u8 pfc_cap_oper[0x4]; 11332 u8 reserved_at_48[0x4]; 11333 u8 pfc_cap_admin[0x4]; 11334 u8 reserved_at_50[0x4]; 11335 u8 num_of_tc_oper[0x4]; 11336 u8 reserved_at_58[0x4]; 11337 u8 num_of_tc_admin[0x4]; 11338 u8 remote_willing[0x1]; 11339 u8 reserved_at_61[3]; 11340 u8 remote_pfc_cap[4]; 11341 u8 reserved_at_68[0x14]; 11342 u8 remote_num_of_tc[0x4]; 11343 u8 reserved_at_80[0x18]; 11344 u8 error[0x8]; 11345 u8 reserved_at_a0[0x160]; 11346 }; 11347 11348 enum { 11349 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11350 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11351 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11352 }; 11353 11354 struct mlx5_ifc_lagc_bits { 11355 u8 fdb_selection_mode[0x1]; 11356 u8 reserved_at_1[0x14]; 11357 u8 port_select_mode[0x3]; 11358 u8 reserved_at_18[0x5]; 11359 u8 lag_state[0x3]; 11360 11361 u8 reserved_at_20[0xc]; 11362 u8 active_port[0x4]; 11363 u8 reserved_at_30[0x4]; 11364 u8 tx_remap_affinity_2[0x4]; 11365 u8 reserved_at_38[0x4]; 11366 u8 tx_remap_affinity_1[0x4]; 11367 }; 11368 11369 struct mlx5_ifc_create_lag_out_bits { 11370 u8 status[0x8]; 11371 u8 reserved_at_8[0x18]; 11372 11373 u8 syndrome[0x20]; 11374 11375 u8 reserved_at_40[0x40]; 11376 }; 11377 11378 struct mlx5_ifc_create_lag_in_bits { 11379 u8 opcode[0x10]; 11380 u8 reserved_at_10[0x10]; 11381 11382 u8 reserved_at_20[0x10]; 11383 u8 op_mod[0x10]; 11384 11385 struct mlx5_ifc_lagc_bits ctx; 11386 }; 11387 11388 struct mlx5_ifc_modify_lag_out_bits { 11389 u8 status[0x8]; 11390 u8 reserved_at_8[0x18]; 11391 11392 u8 syndrome[0x20]; 11393 11394 u8 reserved_at_40[0x40]; 11395 }; 11396 11397 struct mlx5_ifc_modify_lag_in_bits { 11398 u8 opcode[0x10]; 11399 u8 reserved_at_10[0x10]; 11400 11401 u8 reserved_at_20[0x10]; 11402 u8 op_mod[0x10]; 11403 11404 u8 reserved_at_40[0x20]; 11405 u8 field_select[0x20]; 11406 11407 struct mlx5_ifc_lagc_bits ctx; 11408 }; 11409 11410 struct mlx5_ifc_query_lag_out_bits { 11411 u8 status[0x8]; 11412 u8 reserved_at_8[0x18]; 11413 11414 u8 syndrome[0x20]; 11415 11416 struct mlx5_ifc_lagc_bits ctx; 11417 }; 11418 11419 struct mlx5_ifc_query_lag_in_bits { 11420 u8 opcode[0x10]; 11421 u8 reserved_at_10[0x10]; 11422 11423 u8 reserved_at_20[0x10]; 11424 u8 op_mod[0x10]; 11425 11426 u8 reserved_at_40[0x40]; 11427 }; 11428 11429 struct mlx5_ifc_destroy_lag_out_bits { 11430 u8 status[0x8]; 11431 u8 reserved_at_8[0x18]; 11432 11433 u8 syndrome[0x20]; 11434 11435 u8 reserved_at_40[0x40]; 11436 }; 11437 11438 struct mlx5_ifc_destroy_lag_in_bits { 11439 u8 opcode[0x10]; 11440 u8 reserved_at_10[0x10]; 11441 11442 u8 reserved_at_20[0x10]; 11443 u8 op_mod[0x10]; 11444 11445 u8 reserved_at_40[0x40]; 11446 }; 11447 11448 struct mlx5_ifc_create_vport_lag_out_bits { 11449 u8 status[0x8]; 11450 u8 reserved_at_8[0x18]; 11451 11452 u8 syndrome[0x20]; 11453 11454 u8 reserved_at_40[0x40]; 11455 }; 11456 11457 struct mlx5_ifc_create_vport_lag_in_bits { 11458 u8 opcode[0x10]; 11459 u8 reserved_at_10[0x10]; 11460 11461 u8 reserved_at_20[0x10]; 11462 u8 op_mod[0x10]; 11463 11464 u8 reserved_at_40[0x40]; 11465 }; 11466 11467 struct mlx5_ifc_destroy_vport_lag_out_bits { 11468 u8 status[0x8]; 11469 u8 reserved_at_8[0x18]; 11470 11471 u8 syndrome[0x20]; 11472 11473 u8 reserved_at_40[0x40]; 11474 }; 11475 11476 struct mlx5_ifc_destroy_vport_lag_in_bits { 11477 u8 opcode[0x10]; 11478 u8 reserved_at_10[0x10]; 11479 11480 u8 reserved_at_20[0x10]; 11481 u8 op_mod[0x10]; 11482 11483 u8 reserved_at_40[0x40]; 11484 }; 11485 11486 enum { 11487 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11488 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11489 }; 11490 11491 struct mlx5_ifc_modify_memic_in_bits { 11492 u8 opcode[0x10]; 11493 u8 uid[0x10]; 11494 11495 u8 reserved_at_20[0x10]; 11496 u8 op_mod[0x10]; 11497 11498 u8 reserved_at_40[0x20]; 11499 11500 u8 reserved_at_60[0x18]; 11501 u8 memic_operation_type[0x8]; 11502 11503 u8 memic_start_addr[0x40]; 11504 11505 u8 reserved_at_c0[0x140]; 11506 }; 11507 11508 struct mlx5_ifc_modify_memic_out_bits { 11509 u8 status[0x8]; 11510 u8 reserved_at_8[0x18]; 11511 11512 u8 syndrome[0x20]; 11513 11514 u8 reserved_at_40[0x40]; 11515 11516 u8 memic_operation_addr[0x40]; 11517 11518 u8 reserved_at_c0[0x140]; 11519 }; 11520 11521 struct mlx5_ifc_alloc_memic_in_bits { 11522 u8 opcode[0x10]; 11523 u8 reserved_at_10[0x10]; 11524 11525 u8 reserved_at_20[0x10]; 11526 u8 op_mod[0x10]; 11527 11528 u8 reserved_at_30[0x20]; 11529 11530 u8 reserved_at_40[0x18]; 11531 u8 log_memic_addr_alignment[0x8]; 11532 11533 u8 range_start_addr[0x40]; 11534 11535 u8 range_size[0x20]; 11536 11537 u8 memic_size[0x20]; 11538 }; 11539 11540 struct mlx5_ifc_alloc_memic_out_bits { 11541 u8 status[0x8]; 11542 u8 reserved_at_8[0x18]; 11543 11544 u8 syndrome[0x20]; 11545 11546 u8 memic_start_addr[0x40]; 11547 }; 11548 11549 struct mlx5_ifc_dealloc_memic_in_bits { 11550 u8 opcode[0x10]; 11551 u8 reserved_at_10[0x10]; 11552 11553 u8 reserved_at_20[0x10]; 11554 u8 op_mod[0x10]; 11555 11556 u8 reserved_at_40[0x40]; 11557 11558 u8 memic_start_addr[0x40]; 11559 11560 u8 memic_size[0x20]; 11561 11562 u8 reserved_at_e0[0x20]; 11563 }; 11564 11565 struct mlx5_ifc_dealloc_memic_out_bits { 11566 u8 status[0x8]; 11567 u8 reserved_at_8[0x18]; 11568 11569 u8 syndrome[0x20]; 11570 11571 u8 reserved_at_40[0x40]; 11572 }; 11573 11574 struct mlx5_ifc_umem_bits { 11575 u8 reserved_at_0[0x80]; 11576 11577 u8 ats[0x1]; 11578 u8 reserved_at_81[0x1a]; 11579 u8 log_page_size[0x5]; 11580 11581 u8 page_offset[0x20]; 11582 11583 u8 num_of_mtt[0x40]; 11584 11585 struct mlx5_ifc_mtt_bits mtt[]; 11586 }; 11587 11588 struct mlx5_ifc_uctx_bits { 11589 u8 cap[0x20]; 11590 11591 u8 reserved_at_20[0x160]; 11592 }; 11593 11594 struct mlx5_ifc_sw_icm_bits { 11595 u8 modify_field_select[0x40]; 11596 11597 u8 reserved_at_40[0x18]; 11598 u8 log_sw_icm_size[0x8]; 11599 11600 u8 reserved_at_60[0x20]; 11601 11602 u8 sw_icm_start_addr[0x40]; 11603 11604 u8 reserved_at_c0[0x140]; 11605 }; 11606 11607 struct mlx5_ifc_geneve_tlv_option_bits { 11608 u8 modify_field_select[0x40]; 11609 11610 u8 reserved_at_40[0x18]; 11611 u8 geneve_option_fte_index[0x8]; 11612 11613 u8 option_class[0x10]; 11614 u8 option_type[0x8]; 11615 u8 reserved_at_78[0x3]; 11616 u8 option_data_length[0x5]; 11617 11618 u8 reserved_at_80[0x180]; 11619 }; 11620 11621 struct mlx5_ifc_create_umem_in_bits { 11622 u8 opcode[0x10]; 11623 u8 uid[0x10]; 11624 11625 u8 reserved_at_20[0x10]; 11626 u8 op_mod[0x10]; 11627 11628 u8 reserved_at_40[0x40]; 11629 11630 struct mlx5_ifc_umem_bits umem; 11631 }; 11632 11633 struct mlx5_ifc_create_umem_out_bits { 11634 u8 status[0x8]; 11635 u8 reserved_at_8[0x18]; 11636 11637 u8 syndrome[0x20]; 11638 11639 u8 reserved_at_40[0x8]; 11640 u8 umem_id[0x18]; 11641 11642 u8 reserved_at_60[0x20]; 11643 }; 11644 11645 struct mlx5_ifc_destroy_umem_in_bits { 11646 u8 opcode[0x10]; 11647 u8 uid[0x10]; 11648 11649 u8 reserved_at_20[0x10]; 11650 u8 op_mod[0x10]; 11651 11652 u8 reserved_at_40[0x8]; 11653 u8 umem_id[0x18]; 11654 11655 u8 reserved_at_60[0x20]; 11656 }; 11657 11658 struct mlx5_ifc_destroy_umem_out_bits { 11659 u8 status[0x8]; 11660 u8 reserved_at_8[0x18]; 11661 11662 u8 syndrome[0x20]; 11663 11664 u8 reserved_at_40[0x40]; 11665 }; 11666 11667 struct mlx5_ifc_create_uctx_in_bits { 11668 u8 opcode[0x10]; 11669 u8 reserved_at_10[0x10]; 11670 11671 u8 reserved_at_20[0x10]; 11672 u8 op_mod[0x10]; 11673 11674 u8 reserved_at_40[0x40]; 11675 11676 struct mlx5_ifc_uctx_bits uctx; 11677 }; 11678 11679 struct mlx5_ifc_create_uctx_out_bits { 11680 u8 status[0x8]; 11681 u8 reserved_at_8[0x18]; 11682 11683 u8 syndrome[0x20]; 11684 11685 u8 reserved_at_40[0x10]; 11686 u8 uid[0x10]; 11687 11688 u8 reserved_at_60[0x20]; 11689 }; 11690 11691 struct mlx5_ifc_destroy_uctx_in_bits { 11692 u8 opcode[0x10]; 11693 u8 reserved_at_10[0x10]; 11694 11695 u8 reserved_at_20[0x10]; 11696 u8 op_mod[0x10]; 11697 11698 u8 reserved_at_40[0x10]; 11699 u8 uid[0x10]; 11700 11701 u8 reserved_at_60[0x20]; 11702 }; 11703 11704 struct mlx5_ifc_destroy_uctx_out_bits { 11705 u8 status[0x8]; 11706 u8 reserved_at_8[0x18]; 11707 11708 u8 syndrome[0x20]; 11709 11710 u8 reserved_at_40[0x40]; 11711 }; 11712 11713 struct mlx5_ifc_create_sw_icm_in_bits { 11714 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11715 struct mlx5_ifc_sw_icm_bits sw_icm; 11716 }; 11717 11718 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11719 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11720 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11721 }; 11722 11723 struct mlx5_ifc_mtrc_string_db_param_bits { 11724 u8 string_db_base_address[0x20]; 11725 11726 u8 reserved_at_20[0x8]; 11727 u8 string_db_size[0x18]; 11728 }; 11729 11730 struct mlx5_ifc_mtrc_cap_bits { 11731 u8 trace_owner[0x1]; 11732 u8 trace_to_memory[0x1]; 11733 u8 reserved_at_2[0x4]; 11734 u8 trc_ver[0x2]; 11735 u8 reserved_at_8[0x14]; 11736 u8 num_string_db[0x4]; 11737 11738 u8 first_string_trace[0x8]; 11739 u8 num_string_trace[0x8]; 11740 u8 reserved_at_30[0x28]; 11741 11742 u8 log_max_trace_buffer_size[0x8]; 11743 11744 u8 reserved_at_60[0x20]; 11745 11746 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11747 11748 u8 reserved_at_280[0x180]; 11749 }; 11750 11751 struct mlx5_ifc_mtrc_conf_bits { 11752 u8 reserved_at_0[0x1c]; 11753 u8 trace_mode[0x4]; 11754 u8 reserved_at_20[0x18]; 11755 u8 log_trace_buffer_size[0x8]; 11756 u8 trace_mkey[0x20]; 11757 u8 reserved_at_60[0x3a0]; 11758 }; 11759 11760 struct mlx5_ifc_mtrc_stdb_bits { 11761 u8 string_db_index[0x4]; 11762 u8 reserved_at_4[0x4]; 11763 u8 read_size[0x18]; 11764 u8 start_offset[0x20]; 11765 u8 string_db_data[]; 11766 }; 11767 11768 struct mlx5_ifc_mtrc_ctrl_bits { 11769 u8 trace_status[0x2]; 11770 u8 reserved_at_2[0x2]; 11771 u8 arm_event[0x1]; 11772 u8 reserved_at_5[0xb]; 11773 u8 modify_field_select[0x10]; 11774 u8 reserved_at_20[0x2b]; 11775 u8 current_timestamp52_32[0x15]; 11776 u8 current_timestamp31_0[0x20]; 11777 u8 reserved_at_80[0x180]; 11778 }; 11779 11780 struct mlx5_ifc_host_params_context_bits { 11781 u8 host_number[0x8]; 11782 u8 reserved_at_8[0x7]; 11783 u8 host_pf_disabled[0x1]; 11784 u8 host_num_of_vfs[0x10]; 11785 11786 u8 host_total_vfs[0x10]; 11787 u8 host_pci_bus[0x10]; 11788 11789 u8 reserved_at_40[0x10]; 11790 u8 host_pci_device[0x10]; 11791 11792 u8 reserved_at_60[0x10]; 11793 u8 host_pci_function[0x10]; 11794 11795 u8 reserved_at_80[0x180]; 11796 }; 11797 11798 struct mlx5_ifc_query_esw_functions_in_bits { 11799 u8 opcode[0x10]; 11800 u8 reserved_at_10[0x10]; 11801 11802 u8 reserved_at_20[0x10]; 11803 u8 op_mod[0x10]; 11804 11805 u8 reserved_at_40[0x40]; 11806 }; 11807 11808 struct mlx5_ifc_query_esw_functions_out_bits { 11809 u8 status[0x8]; 11810 u8 reserved_at_8[0x18]; 11811 11812 u8 syndrome[0x20]; 11813 11814 u8 reserved_at_40[0x40]; 11815 11816 struct mlx5_ifc_host_params_context_bits host_params_context; 11817 11818 u8 reserved_at_280[0x180]; 11819 u8 host_sf_enable[][0x40]; 11820 }; 11821 11822 struct mlx5_ifc_sf_partition_bits { 11823 u8 reserved_at_0[0x10]; 11824 u8 log_num_sf[0x8]; 11825 u8 log_sf_bar_size[0x8]; 11826 }; 11827 11828 struct mlx5_ifc_query_sf_partitions_out_bits { 11829 u8 status[0x8]; 11830 u8 reserved_at_8[0x18]; 11831 11832 u8 syndrome[0x20]; 11833 11834 u8 reserved_at_40[0x18]; 11835 u8 num_sf_partitions[0x8]; 11836 11837 u8 reserved_at_60[0x20]; 11838 11839 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11840 }; 11841 11842 struct mlx5_ifc_query_sf_partitions_in_bits { 11843 u8 opcode[0x10]; 11844 u8 reserved_at_10[0x10]; 11845 11846 u8 reserved_at_20[0x10]; 11847 u8 op_mod[0x10]; 11848 11849 u8 reserved_at_40[0x40]; 11850 }; 11851 11852 struct mlx5_ifc_dealloc_sf_out_bits { 11853 u8 status[0x8]; 11854 u8 reserved_at_8[0x18]; 11855 11856 u8 syndrome[0x20]; 11857 11858 u8 reserved_at_40[0x40]; 11859 }; 11860 11861 struct mlx5_ifc_dealloc_sf_in_bits { 11862 u8 opcode[0x10]; 11863 u8 reserved_at_10[0x10]; 11864 11865 u8 reserved_at_20[0x10]; 11866 u8 op_mod[0x10]; 11867 11868 u8 reserved_at_40[0x10]; 11869 u8 function_id[0x10]; 11870 11871 u8 reserved_at_60[0x20]; 11872 }; 11873 11874 struct mlx5_ifc_alloc_sf_out_bits { 11875 u8 status[0x8]; 11876 u8 reserved_at_8[0x18]; 11877 11878 u8 syndrome[0x20]; 11879 11880 u8 reserved_at_40[0x40]; 11881 }; 11882 11883 struct mlx5_ifc_alloc_sf_in_bits { 11884 u8 opcode[0x10]; 11885 u8 reserved_at_10[0x10]; 11886 11887 u8 reserved_at_20[0x10]; 11888 u8 op_mod[0x10]; 11889 11890 u8 reserved_at_40[0x10]; 11891 u8 function_id[0x10]; 11892 11893 u8 reserved_at_60[0x20]; 11894 }; 11895 11896 struct mlx5_ifc_affiliated_event_header_bits { 11897 u8 reserved_at_0[0x10]; 11898 u8 obj_type[0x10]; 11899 11900 u8 obj_id[0x20]; 11901 }; 11902 11903 enum { 11904 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11905 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11906 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11907 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11908 }; 11909 11910 enum { 11911 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11912 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11913 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11914 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11915 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11916 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11917 }; 11918 11919 enum { 11920 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11921 }; 11922 11923 enum { 11924 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11925 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11926 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11927 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11928 }; 11929 11930 enum { 11931 MLX5_IPSEC_ASO_MODE = 0x0, 11932 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11933 MLX5_IPSEC_ASO_INC_SN = 0x2, 11934 }; 11935 11936 struct mlx5_ifc_ipsec_aso_bits { 11937 u8 valid[0x1]; 11938 u8 reserved_at_201[0x1]; 11939 u8 mode[0x2]; 11940 u8 window_sz[0x2]; 11941 u8 soft_lft_arm[0x1]; 11942 u8 hard_lft_arm[0x1]; 11943 u8 remove_flow_enable[0x1]; 11944 u8 esn_event_arm[0x1]; 11945 u8 reserved_at_20a[0x16]; 11946 11947 u8 remove_flow_pkt_cnt[0x20]; 11948 11949 u8 remove_flow_soft_lft[0x20]; 11950 11951 u8 reserved_at_260[0x80]; 11952 11953 u8 mode_parameter[0x20]; 11954 11955 u8 replay_protection_window[0x100]; 11956 }; 11957 11958 struct mlx5_ifc_ipsec_obj_bits { 11959 u8 modify_field_select[0x40]; 11960 u8 full_offload[0x1]; 11961 u8 reserved_at_41[0x1]; 11962 u8 esn_en[0x1]; 11963 u8 esn_overlap[0x1]; 11964 u8 reserved_at_44[0x2]; 11965 u8 icv_length[0x2]; 11966 u8 reserved_at_48[0x4]; 11967 u8 aso_return_reg[0x4]; 11968 u8 reserved_at_50[0x10]; 11969 11970 u8 esn_msb[0x20]; 11971 11972 u8 reserved_at_80[0x8]; 11973 u8 dekn[0x18]; 11974 11975 u8 salt[0x20]; 11976 11977 u8 implicit_iv[0x40]; 11978 11979 u8 reserved_at_100[0x8]; 11980 u8 ipsec_aso_access_pd[0x18]; 11981 u8 reserved_at_120[0xe0]; 11982 11983 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11984 }; 11985 11986 struct mlx5_ifc_create_ipsec_obj_in_bits { 11987 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11988 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11989 }; 11990 11991 enum { 11992 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11993 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11994 }; 11995 11996 struct mlx5_ifc_query_ipsec_obj_out_bits { 11997 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11998 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11999 }; 12000 12001 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12002 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12003 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12004 }; 12005 12006 enum { 12007 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12008 }; 12009 12010 enum { 12011 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12012 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12013 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12014 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12015 }; 12016 12017 #define MLX5_MACSEC_ASO_INC_SN 0x2 12018 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12019 12020 struct mlx5_ifc_macsec_aso_bits { 12021 u8 valid[0x1]; 12022 u8 reserved_at_1[0x1]; 12023 u8 mode[0x2]; 12024 u8 window_size[0x2]; 12025 u8 soft_lifetime_arm[0x1]; 12026 u8 hard_lifetime_arm[0x1]; 12027 u8 remove_flow_enable[0x1]; 12028 u8 epn_event_arm[0x1]; 12029 u8 reserved_at_a[0x16]; 12030 12031 u8 remove_flow_packet_count[0x20]; 12032 12033 u8 remove_flow_soft_lifetime[0x20]; 12034 12035 u8 reserved_at_60[0x80]; 12036 12037 u8 mode_parameter[0x20]; 12038 12039 u8 replay_protection_window[8][0x20]; 12040 }; 12041 12042 struct mlx5_ifc_macsec_offload_obj_bits { 12043 u8 modify_field_select[0x40]; 12044 12045 u8 confidentiality_en[0x1]; 12046 u8 reserved_at_41[0x1]; 12047 u8 epn_en[0x1]; 12048 u8 epn_overlap[0x1]; 12049 u8 reserved_at_44[0x2]; 12050 u8 confidentiality_offset[0x2]; 12051 u8 reserved_at_48[0x4]; 12052 u8 aso_return_reg[0x4]; 12053 u8 reserved_at_50[0x10]; 12054 12055 u8 epn_msb[0x20]; 12056 12057 u8 reserved_at_80[0x8]; 12058 u8 dekn[0x18]; 12059 12060 u8 reserved_at_a0[0x20]; 12061 12062 u8 sci[0x40]; 12063 12064 u8 reserved_at_100[0x8]; 12065 u8 macsec_aso_access_pd[0x18]; 12066 12067 u8 reserved_at_120[0x60]; 12068 12069 u8 salt[3][0x20]; 12070 12071 u8 reserved_at_1e0[0x20]; 12072 12073 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12074 }; 12075 12076 struct mlx5_ifc_create_macsec_obj_in_bits { 12077 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12078 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12079 }; 12080 12081 struct mlx5_ifc_modify_macsec_obj_in_bits { 12082 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12083 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12084 }; 12085 12086 enum { 12087 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12088 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12089 }; 12090 12091 struct mlx5_ifc_query_macsec_obj_out_bits { 12092 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12093 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12094 }; 12095 12096 struct mlx5_ifc_wrapped_dek_bits { 12097 u8 gcm_iv[0x60]; 12098 12099 u8 reserved_at_60[0x20]; 12100 12101 u8 const0[0x1]; 12102 u8 key_size[0x1]; 12103 u8 reserved_at_82[0x2]; 12104 u8 key2_invalid[0x1]; 12105 u8 reserved_at_85[0x3]; 12106 u8 pd[0x18]; 12107 12108 u8 key_purpose[0x5]; 12109 u8 reserved_at_a5[0x13]; 12110 u8 kek_id[0x8]; 12111 12112 u8 reserved_at_c0[0x40]; 12113 12114 u8 key1[0x8][0x20]; 12115 12116 u8 key2[0x8][0x20]; 12117 12118 u8 reserved_at_300[0x40]; 12119 12120 u8 const1[0x1]; 12121 u8 reserved_at_341[0x1f]; 12122 12123 u8 reserved_at_360[0x20]; 12124 12125 u8 auth_tag[0x80]; 12126 }; 12127 12128 struct mlx5_ifc_encryption_key_obj_bits { 12129 u8 modify_field_select[0x40]; 12130 12131 u8 state[0x8]; 12132 u8 sw_wrapped[0x1]; 12133 u8 reserved_at_49[0xb]; 12134 u8 key_size[0x4]; 12135 u8 reserved_at_58[0x4]; 12136 u8 key_purpose[0x4]; 12137 12138 u8 reserved_at_60[0x8]; 12139 u8 pd[0x18]; 12140 12141 u8 reserved_at_80[0x100]; 12142 12143 u8 opaque[0x40]; 12144 12145 u8 reserved_at_1c0[0x40]; 12146 12147 u8 key[8][0x80]; 12148 12149 u8 sw_wrapped_dek[8][0x80]; 12150 12151 u8 reserved_at_a00[0x600]; 12152 }; 12153 12154 struct mlx5_ifc_create_encryption_key_in_bits { 12155 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12156 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12157 }; 12158 12159 struct mlx5_ifc_modify_encryption_key_in_bits { 12160 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12161 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12162 }; 12163 12164 enum { 12165 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12166 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12167 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12168 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12169 }; 12170 12171 struct mlx5_ifc_flow_meter_parameters_bits { 12172 u8 valid[0x1]; 12173 u8 bucket_overflow[0x1]; 12174 u8 start_color[0x2]; 12175 u8 both_buckets_on_green[0x1]; 12176 u8 reserved_at_5[0x1]; 12177 u8 meter_mode[0x2]; 12178 u8 reserved_at_8[0x18]; 12179 12180 u8 reserved_at_20[0x20]; 12181 12182 u8 reserved_at_40[0x3]; 12183 u8 cbs_exponent[0x5]; 12184 u8 cbs_mantissa[0x8]; 12185 u8 reserved_at_50[0x3]; 12186 u8 cir_exponent[0x5]; 12187 u8 cir_mantissa[0x8]; 12188 12189 u8 reserved_at_60[0x20]; 12190 12191 u8 reserved_at_80[0x3]; 12192 u8 ebs_exponent[0x5]; 12193 u8 ebs_mantissa[0x8]; 12194 u8 reserved_at_90[0x3]; 12195 u8 eir_exponent[0x5]; 12196 u8 eir_mantissa[0x8]; 12197 12198 u8 reserved_at_a0[0x60]; 12199 }; 12200 12201 struct mlx5_ifc_flow_meter_aso_obj_bits { 12202 u8 modify_field_select[0x40]; 12203 12204 u8 reserved_at_40[0x40]; 12205 12206 u8 reserved_at_80[0x8]; 12207 u8 meter_aso_access_pd[0x18]; 12208 12209 u8 reserved_at_a0[0x160]; 12210 12211 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12212 }; 12213 12214 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12215 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12216 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12217 }; 12218 12219 struct mlx5_ifc_int_kek_obj_bits { 12220 u8 modify_field_select[0x40]; 12221 12222 u8 state[0x8]; 12223 u8 auto_gen[0x1]; 12224 u8 reserved_at_49[0xb]; 12225 u8 key_size[0x4]; 12226 u8 reserved_at_58[0x8]; 12227 12228 u8 reserved_at_60[0x8]; 12229 u8 pd[0x18]; 12230 12231 u8 reserved_at_80[0x180]; 12232 u8 key[8][0x80]; 12233 12234 u8 reserved_at_600[0x200]; 12235 }; 12236 12237 struct mlx5_ifc_create_int_kek_obj_in_bits { 12238 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12239 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12240 }; 12241 12242 struct mlx5_ifc_create_int_kek_obj_out_bits { 12243 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12244 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12245 }; 12246 12247 struct mlx5_ifc_sampler_obj_bits { 12248 u8 modify_field_select[0x40]; 12249 12250 u8 table_type[0x8]; 12251 u8 level[0x8]; 12252 u8 reserved_at_50[0xf]; 12253 u8 ignore_flow_level[0x1]; 12254 12255 u8 sample_ratio[0x20]; 12256 12257 u8 reserved_at_80[0x8]; 12258 u8 sample_table_id[0x18]; 12259 12260 u8 reserved_at_a0[0x8]; 12261 u8 default_table_id[0x18]; 12262 12263 u8 sw_steering_icm_address_rx[0x40]; 12264 u8 sw_steering_icm_address_tx[0x40]; 12265 12266 u8 reserved_at_140[0xa0]; 12267 }; 12268 12269 struct mlx5_ifc_create_sampler_obj_in_bits { 12270 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12271 struct mlx5_ifc_sampler_obj_bits sampler_object; 12272 }; 12273 12274 struct mlx5_ifc_query_sampler_obj_out_bits { 12275 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12276 struct mlx5_ifc_sampler_obj_bits sampler_object; 12277 }; 12278 12279 enum { 12280 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12281 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12282 }; 12283 12284 enum { 12285 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12286 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12287 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12288 }; 12289 12290 struct mlx5_ifc_tls_static_params_bits { 12291 u8 const_2[0x2]; 12292 u8 tls_version[0x4]; 12293 u8 const_1[0x2]; 12294 u8 reserved_at_8[0x14]; 12295 u8 encryption_standard[0x4]; 12296 12297 u8 reserved_at_20[0x20]; 12298 12299 u8 initial_record_number[0x40]; 12300 12301 u8 resync_tcp_sn[0x20]; 12302 12303 u8 gcm_iv[0x20]; 12304 12305 u8 implicit_iv[0x40]; 12306 12307 u8 reserved_at_100[0x8]; 12308 u8 dek_index[0x18]; 12309 12310 u8 reserved_at_120[0xe0]; 12311 }; 12312 12313 struct mlx5_ifc_tls_progress_params_bits { 12314 u8 next_record_tcp_sn[0x20]; 12315 12316 u8 hw_resync_tcp_sn[0x20]; 12317 12318 u8 record_tracker_state[0x2]; 12319 u8 auth_state[0x2]; 12320 u8 reserved_at_44[0x4]; 12321 u8 hw_offset_record_number[0x18]; 12322 }; 12323 12324 enum { 12325 MLX5_MTT_PERM_READ = 1 << 0, 12326 MLX5_MTT_PERM_WRITE = 1 << 1, 12327 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12328 }; 12329 12330 enum { 12331 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12332 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12333 }; 12334 12335 struct mlx5_ifc_suspend_vhca_in_bits { 12336 u8 opcode[0x10]; 12337 u8 uid[0x10]; 12338 12339 u8 reserved_at_20[0x10]; 12340 u8 op_mod[0x10]; 12341 12342 u8 reserved_at_40[0x10]; 12343 u8 vhca_id[0x10]; 12344 12345 u8 reserved_at_60[0x20]; 12346 }; 12347 12348 struct mlx5_ifc_suspend_vhca_out_bits { 12349 u8 status[0x8]; 12350 u8 reserved_at_8[0x18]; 12351 12352 u8 syndrome[0x20]; 12353 12354 u8 reserved_at_40[0x40]; 12355 }; 12356 12357 enum { 12358 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12359 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12360 }; 12361 12362 struct mlx5_ifc_resume_vhca_in_bits { 12363 u8 opcode[0x10]; 12364 u8 uid[0x10]; 12365 12366 u8 reserved_at_20[0x10]; 12367 u8 op_mod[0x10]; 12368 12369 u8 reserved_at_40[0x10]; 12370 u8 vhca_id[0x10]; 12371 12372 u8 reserved_at_60[0x20]; 12373 }; 12374 12375 struct mlx5_ifc_resume_vhca_out_bits { 12376 u8 status[0x8]; 12377 u8 reserved_at_8[0x18]; 12378 12379 u8 syndrome[0x20]; 12380 12381 u8 reserved_at_40[0x40]; 12382 }; 12383 12384 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12385 u8 opcode[0x10]; 12386 u8 uid[0x10]; 12387 12388 u8 reserved_at_20[0x10]; 12389 u8 op_mod[0x10]; 12390 12391 u8 incremental[0x1]; 12392 u8 reserved_at_41[0xf]; 12393 u8 vhca_id[0x10]; 12394 12395 u8 reserved_at_60[0x20]; 12396 }; 12397 12398 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12399 u8 status[0x8]; 12400 u8 reserved_at_8[0x18]; 12401 12402 u8 syndrome[0x20]; 12403 12404 u8 reserved_at_40[0x40]; 12405 12406 u8 required_umem_size[0x20]; 12407 12408 u8 reserved_at_a0[0x160]; 12409 }; 12410 12411 struct mlx5_ifc_save_vhca_state_in_bits { 12412 u8 opcode[0x10]; 12413 u8 uid[0x10]; 12414 12415 u8 reserved_at_20[0x10]; 12416 u8 op_mod[0x10]; 12417 12418 u8 incremental[0x1]; 12419 u8 set_track[0x1]; 12420 u8 reserved_at_42[0xe]; 12421 u8 vhca_id[0x10]; 12422 12423 u8 reserved_at_60[0x20]; 12424 12425 u8 va[0x40]; 12426 12427 u8 mkey[0x20]; 12428 12429 u8 size[0x20]; 12430 }; 12431 12432 struct mlx5_ifc_save_vhca_state_out_bits { 12433 u8 status[0x8]; 12434 u8 reserved_at_8[0x18]; 12435 12436 u8 syndrome[0x20]; 12437 12438 u8 actual_image_size[0x20]; 12439 12440 u8 reserved_at_60[0x20]; 12441 }; 12442 12443 struct mlx5_ifc_load_vhca_state_in_bits { 12444 u8 opcode[0x10]; 12445 u8 uid[0x10]; 12446 12447 u8 reserved_at_20[0x10]; 12448 u8 op_mod[0x10]; 12449 12450 u8 reserved_at_40[0x10]; 12451 u8 vhca_id[0x10]; 12452 12453 u8 reserved_at_60[0x20]; 12454 12455 u8 va[0x40]; 12456 12457 u8 mkey[0x20]; 12458 12459 u8 size[0x20]; 12460 }; 12461 12462 struct mlx5_ifc_load_vhca_state_out_bits { 12463 u8 status[0x8]; 12464 u8 reserved_at_8[0x18]; 12465 12466 u8 syndrome[0x20]; 12467 12468 u8 reserved_at_40[0x40]; 12469 }; 12470 12471 struct mlx5_ifc_adv_virtualization_cap_bits { 12472 u8 reserved_at_0[0x3]; 12473 u8 pg_track_log_max_num[0x5]; 12474 u8 pg_track_max_num_range[0x8]; 12475 u8 pg_track_log_min_addr_space[0x8]; 12476 u8 pg_track_log_max_addr_space[0x8]; 12477 12478 u8 reserved_at_20[0x3]; 12479 u8 pg_track_log_min_msg_size[0x5]; 12480 u8 reserved_at_28[0x3]; 12481 u8 pg_track_log_max_msg_size[0x5]; 12482 u8 reserved_at_30[0x3]; 12483 u8 pg_track_log_min_page_size[0x5]; 12484 u8 reserved_at_38[0x3]; 12485 u8 pg_track_log_max_page_size[0x5]; 12486 12487 u8 reserved_at_40[0x7c0]; 12488 }; 12489 12490 struct mlx5_ifc_page_track_report_entry_bits { 12491 u8 dirty_address_high[0x20]; 12492 12493 u8 dirty_address_low[0x20]; 12494 }; 12495 12496 enum { 12497 MLX5_PAGE_TRACK_STATE_TRACKING, 12498 MLX5_PAGE_TRACK_STATE_REPORTING, 12499 MLX5_PAGE_TRACK_STATE_ERROR, 12500 }; 12501 12502 struct mlx5_ifc_page_track_range_bits { 12503 u8 start_address[0x40]; 12504 12505 u8 length[0x40]; 12506 }; 12507 12508 struct mlx5_ifc_page_track_bits { 12509 u8 modify_field_select[0x40]; 12510 12511 u8 reserved_at_40[0x10]; 12512 u8 vhca_id[0x10]; 12513 12514 u8 reserved_at_60[0x20]; 12515 12516 u8 state[0x4]; 12517 u8 track_type[0x4]; 12518 u8 log_addr_space_size[0x8]; 12519 u8 reserved_at_90[0x3]; 12520 u8 log_page_size[0x5]; 12521 u8 reserved_at_98[0x3]; 12522 u8 log_msg_size[0x5]; 12523 12524 u8 reserved_at_a0[0x8]; 12525 u8 reporting_qpn[0x18]; 12526 12527 u8 reserved_at_c0[0x18]; 12528 u8 num_ranges[0x8]; 12529 12530 u8 reserved_at_e0[0x20]; 12531 12532 u8 range_start_address[0x40]; 12533 12534 u8 length[0x40]; 12535 12536 struct mlx5_ifc_page_track_range_bits track_range[0]; 12537 }; 12538 12539 struct mlx5_ifc_create_page_track_obj_in_bits { 12540 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12541 struct mlx5_ifc_page_track_bits obj_context; 12542 }; 12543 12544 struct mlx5_ifc_modify_page_track_obj_in_bits { 12545 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12546 struct mlx5_ifc_page_track_bits obj_context; 12547 }; 12548 12549 #endif /* MLX5_IFC_H */ 12550