1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 reserved_at_1e[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 reserved_at_41[0x4]; 375 u8 outer_first_mpls_over_udp[0x4]; 376 u8 outer_first_mpls_over_gre[0x4]; 377 u8 inner_first_mpls[0x4]; 378 u8 outer_first_mpls[0x4]; 379 u8 reserved_at_55[0x2]; 380 u8 outer_esp_spi[0x1]; 381 u8 reserved_at_58[0x2]; 382 u8 bth_dst_qp[0x1]; 383 u8 reserved_at_5b[0x5]; 384 385 u8 reserved_at_60[0x18]; 386 u8 metadata_reg_c_7[0x1]; 387 u8 metadata_reg_c_6[0x1]; 388 u8 metadata_reg_c_5[0x1]; 389 u8 metadata_reg_c_4[0x1]; 390 u8 metadata_reg_c_3[0x1]; 391 u8 metadata_reg_c_2[0x1]; 392 u8 metadata_reg_c_1[0x1]; 393 u8 metadata_reg_c_0[0x1]; 394 }; 395 396 struct mlx5_ifc_flow_table_prop_layout_bits { 397 u8 ft_support[0x1]; 398 u8 reserved_at_1[0x1]; 399 u8 flow_counter[0x1]; 400 u8 flow_modify_en[0x1]; 401 u8 modify_root[0x1]; 402 u8 identified_miss_table_mode[0x1]; 403 u8 flow_table_modify[0x1]; 404 u8 reformat[0x1]; 405 u8 decap[0x1]; 406 u8 reserved_at_9[0x1]; 407 u8 pop_vlan[0x1]; 408 u8 push_vlan[0x1]; 409 u8 reserved_at_c[0x1]; 410 u8 pop_vlan_2[0x1]; 411 u8 push_vlan_2[0x1]; 412 u8 reformat_and_vlan_action[0x1]; 413 u8 reserved_at_10[0x1]; 414 u8 sw_owner[0x1]; 415 u8 reformat_l3_tunnel_to_l2[0x1]; 416 u8 reformat_l2_to_l3_tunnel[0x1]; 417 u8 reformat_and_modify_action[0x1]; 418 u8 ignore_flow_level[0x1]; 419 u8 reserved_at_16[0x1]; 420 u8 table_miss_action_domain[0x1]; 421 u8 termination_table[0x1]; 422 u8 reformat_and_fwd_to_table[0x1]; 423 u8 reserved_at_1a[0x2]; 424 u8 ipsec_encrypt[0x1]; 425 u8 ipsec_decrypt[0x1]; 426 u8 sw_owner_v2[0x1]; 427 u8 reserved_at_1f[0x1]; 428 429 u8 termination_table_raw_traffic[0x1]; 430 u8 reserved_at_21[0x1]; 431 u8 log_max_ft_size[0x6]; 432 u8 log_max_modify_header_context[0x8]; 433 u8 max_modify_header_actions[0x8]; 434 u8 max_ft_level[0x8]; 435 436 u8 reserved_at_40[0x20]; 437 438 u8 reserved_at_60[0x18]; 439 u8 log_max_ft_num[0x8]; 440 441 u8 reserved_at_80[0x10]; 442 u8 log_max_flow_counter[0x8]; 443 u8 log_max_destination[0x8]; 444 445 u8 reserved_at_a0[0x18]; 446 u8 log_max_flow[0x8]; 447 448 u8 reserved_at_c0[0x40]; 449 450 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 451 452 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 453 }; 454 455 struct mlx5_ifc_odp_per_transport_service_cap_bits { 456 u8 send[0x1]; 457 u8 receive[0x1]; 458 u8 write[0x1]; 459 u8 read[0x1]; 460 u8 atomic[0x1]; 461 u8 srq_receive[0x1]; 462 u8 reserved_at_6[0x1a]; 463 }; 464 465 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 466 u8 smac_47_16[0x20]; 467 468 u8 smac_15_0[0x10]; 469 u8 ethertype[0x10]; 470 471 u8 dmac_47_16[0x20]; 472 473 u8 dmac_15_0[0x10]; 474 u8 first_prio[0x3]; 475 u8 first_cfi[0x1]; 476 u8 first_vid[0xc]; 477 478 u8 ip_protocol[0x8]; 479 u8 ip_dscp[0x6]; 480 u8 ip_ecn[0x2]; 481 u8 cvlan_tag[0x1]; 482 u8 svlan_tag[0x1]; 483 u8 frag[0x1]; 484 u8 ip_version[0x4]; 485 u8 tcp_flags[0x9]; 486 487 u8 tcp_sport[0x10]; 488 u8 tcp_dport[0x10]; 489 490 u8 reserved_at_c0[0x18]; 491 u8 ttl_hoplimit[0x8]; 492 493 u8 udp_sport[0x10]; 494 u8 udp_dport[0x10]; 495 496 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 497 498 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 499 }; 500 501 struct mlx5_ifc_nvgre_key_bits { 502 u8 hi[0x18]; 503 u8 lo[0x8]; 504 }; 505 506 union mlx5_ifc_gre_key_bits { 507 struct mlx5_ifc_nvgre_key_bits nvgre; 508 u8 key[0x20]; 509 }; 510 511 struct mlx5_ifc_fte_match_set_misc_bits { 512 u8 gre_c_present[0x1]; 513 u8 reserved_at_1[0x1]; 514 u8 gre_k_present[0x1]; 515 u8 gre_s_present[0x1]; 516 u8 source_vhca_port[0x4]; 517 u8 source_sqn[0x18]; 518 519 u8 source_eswitch_owner_vhca_id[0x10]; 520 u8 source_port[0x10]; 521 522 u8 outer_second_prio[0x3]; 523 u8 outer_second_cfi[0x1]; 524 u8 outer_second_vid[0xc]; 525 u8 inner_second_prio[0x3]; 526 u8 inner_second_cfi[0x1]; 527 u8 inner_second_vid[0xc]; 528 529 u8 outer_second_cvlan_tag[0x1]; 530 u8 inner_second_cvlan_tag[0x1]; 531 u8 outer_second_svlan_tag[0x1]; 532 u8 inner_second_svlan_tag[0x1]; 533 u8 reserved_at_64[0xc]; 534 u8 gre_protocol[0x10]; 535 536 union mlx5_ifc_gre_key_bits gre_key; 537 538 u8 vxlan_vni[0x18]; 539 u8 reserved_at_b8[0x8]; 540 541 u8 geneve_vni[0x18]; 542 u8 reserved_at_d8[0x7]; 543 u8 geneve_oam[0x1]; 544 545 u8 reserved_at_e0[0xc]; 546 u8 outer_ipv6_flow_label[0x14]; 547 548 u8 reserved_at_100[0xc]; 549 u8 inner_ipv6_flow_label[0x14]; 550 551 u8 reserved_at_120[0xa]; 552 u8 geneve_opt_len[0x6]; 553 u8 geneve_protocol_type[0x10]; 554 555 u8 reserved_at_140[0x8]; 556 u8 bth_dst_qp[0x18]; 557 u8 reserved_at_160[0x20]; 558 u8 outer_esp_spi[0x20]; 559 u8 reserved_at_1a0[0x60]; 560 }; 561 562 struct mlx5_ifc_fte_match_mpls_bits { 563 u8 mpls_label[0x14]; 564 u8 mpls_exp[0x3]; 565 u8 mpls_s_bos[0x1]; 566 u8 mpls_ttl[0x8]; 567 }; 568 569 struct mlx5_ifc_fte_match_set_misc2_bits { 570 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 571 572 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 573 574 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 575 576 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 577 578 u8 metadata_reg_c_7[0x20]; 579 580 u8 metadata_reg_c_6[0x20]; 581 582 u8 metadata_reg_c_5[0x20]; 583 584 u8 metadata_reg_c_4[0x20]; 585 586 u8 metadata_reg_c_3[0x20]; 587 588 u8 metadata_reg_c_2[0x20]; 589 590 u8 metadata_reg_c_1[0x20]; 591 592 u8 metadata_reg_c_0[0x20]; 593 594 u8 metadata_reg_a[0x20]; 595 596 u8 reserved_at_1a0[0x60]; 597 }; 598 599 struct mlx5_ifc_fte_match_set_misc3_bits { 600 u8 inner_tcp_seq_num[0x20]; 601 602 u8 outer_tcp_seq_num[0x20]; 603 604 u8 inner_tcp_ack_num[0x20]; 605 606 u8 outer_tcp_ack_num[0x20]; 607 608 u8 reserved_at_80[0x8]; 609 u8 outer_vxlan_gpe_vni[0x18]; 610 611 u8 outer_vxlan_gpe_next_protocol[0x8]; 612 u8 outer_vxlan_gpe_flags[0x8]; 613 u8 reserved_at_b0[0x10]; 614 615 u8 icmp_header_data[0x20]; 616 617 u8 icmpv6_header_data[0x20]; 618 619 u8 icmp_type[0x8]; 620 u8 icmp_code[0x8]; 621 u8 icmpv6_type[0x8]; 622 u8 icmpv6_code[0x8]; 623 624 u8 geneve_tlv_option_0_data[0x20]; 625 626 u8 gtpu_teid[0x20]; 627 628 u8 gtpu_msg_type[0x8]; 629 u8 gtpu_msg_flags[0x8]; 630 u8 reserved_at_170[0x10]; 631 632 u8 gtpu_dw_2[0x20]; 633 634 u8 gtpu_first_ext_dw_0[0x20]; 635 636 u8 gtpu_dw_0[0x20]; 637 638 u8 reserved_at_1e0[0x20]; 639 }; 640 641 struct mlx5_ifc_fte_match_set_misc4_bits { 642 u8 prog_sample_field_value_0[0x20]; 643 644 u8 prog_sample_field_id_0[0x20]; 645 646 u8 prog_sample_field_value_1[0x20]; 647 648 u8 prog_sample_field_id_1[0x20]; 649 650 u8 prog_sample_field_value_2[0x20]; 651 652 u8 prog_sample_field_id_2[0x20]; 653 654 u8 prog_sample_field_value_3[0x20]; 655 656 u8 prog_sample_field_id_3[0x20]; 657 658 u8 reserved_at_100[0x100]; 659 }; 660 661 struct mlx5_ifc_cmd_pas_bits { 662 u8 pa_h[0x20]; 663 664 u8 pa_l[0x14]; 665 u8 reserved_at_34[0xc]; 666 }; 667 668 struct mlx5_ifc_uint64_bits { 669 u8 hi[0x20]; 670 671 u8 lo[0x20]; 672 }; 673 674 enum { 675 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 676 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 677 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 678 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 679 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 680 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 681 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 682 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 683 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 684 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 685 }; 686 687 struct mlx5_ifc_ads_bits { 688 u8 fl[0x1]; 689 u8 free_ar[0x1]; 690 u8 reserved_at_2[0xe]; 691 u8 pkey_index[0x10]; 692 693 u8 reserved_at_20[0x8]; 694 u8 grh[0x1]; 695 u8 mlid[0x7]; 696 u8 rlid[0x10]; 697 698 u8 ack_timeout[0x5]; 699 u8 reserved_at_45[0x3]; 700 u8 src_addr_index[0x8]; 701 u8 reserved_at_50[0x4]; 702 u8 stat_rate[0x4]; 703 u8 hop_limit[0x8]; 704 705 u8 reserved_at_60[0x4]; 706 u8 tclass[0x8]; 707 u8 flow_label[0x14]; 708 709 u8 rgid_rip[16][0x8]; 710 711 u8 reserved_at_100[0x4]; 712 u8 f_dscp[0x1]; 713 u8 f_ecn[0x1]; 714 u8 reserved_at_106[0x1]; 715 u8 f_eth_prio[0x1]; 716 u8 ecn[0x2]; 717 u8 dscp[0x6]; 718 u8 udp_sport[0x10]; 719 720 u8 dei_cfi[0x1]; 721 u8 eth_prio[0x3]; 722 u8 sl[0x4]; 723 u8 vhca_port_num[0x8]; 724 u8 rmac_47_32[0x10]; 725 726 u8 rmac_31_0[0x20]; 727 }; 728 729 struct mlx5_ifc_flow_table_nic_cap_bits { 730 u8 nic_rx_multi_path_tirs[0x1]; 731 u8 nic_rx_multi_path_tirs_fts[0x1]; 732 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 733 u8 reserved_at_3[0x4]; 734 u8 sw_owner_reformat_supported[0x1]; 735 u8 reserved_at_8[0x18]; 736 737 u8 encap_general_header[0x1]; 738 u8 reserved_at_21[0xa]; 739 u8 log_max_packet_reformat_context[0x5]; 740 u8 reserved_at_30[0x6]; 741 u8 max_encap_header_size[0xa]; 742 u8 reserved_at_40[0x1c0]; 743 744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 745 746 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 747 748 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 749 750 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 751 752 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 753 754 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 755 756 u8 reserved_at_e00[0x1200]; 757 758 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 759 760 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 761 762 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 763 764 u8 reserved_at_20c0[0x5f40]; 765 }; 766 767 enum { 768 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 769 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 770 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 771 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 772 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 773 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 774 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 775 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 776 }; 777 778 struct mlx5_ifc_flow_table_eswitch_cap_bits { 779 u8 fdb_to_vport_reg_c_id[0x8]; 780 u8 reserved_at_8[0xd]; 781 u8 fdb_modify_header_fwd_to_table[0x1]; 782 u8 reserved_at_16[0x1]; 783 u8 flow_source[0x1]; 784 u8 reserved_at_18[0x2]; 785 u8 multi_fdb_encap[0x1]; 786 u8 egress_acl_forward_to_vport[0x1]; 787 u8 fdb_multi_path_to_table[0x1]; 788 u8 reserved_at_1d[0x3]; 789 790 u8 reserved_at_20[0x1e0]; 791 792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 793 794 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 795 796 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 797 798 u8 reserved_at_800[0x1000]; 799 800 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 801 802 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 803 804 u8 sw_steering_uplink_icm_address_rx[0x40]; 805 806 u8 sw_steering_uplink_icm_address_tx[0x40]; 807 808 u8 reserved_at_1900[0x6700]; 809 }; 810 811 enum { 812 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 813 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 814 }; 815 816 struct mlx5_ifc_e_switch_cap_bits { 817 u8 vport_svlan_strip[0x1]; 818 u8 vport_cvlan_strip[0x1]; 819 u8 vport_svlan_insert[0x1]; 820 u8 vport_cvlan_insert_if_not_exist[0x1]; 821 u8 vport_cvlan_insert_overwrite[0x1]; 822 u8 reserved_at_5[0x2]; 823 u8 esw_shared_ingress_acl[0x1]; 824 u8 esw_uplink_ingress_acl[0x1]; 825 u8 root_ft_on_other_esw[0x1]; 826 u8 reserved_at_a[0xf]; 827 u8 esw_functions_changed[0x1]; 828 u8 reserved_at_1a[0x1]; 829 u8 ecpf_vport_exists[0x1]; 830 u8 counter_eswitch_affinity[0x1]; 831 u8 merged_eswitch[0x1]; 832 u8 nic_vport_node_guid_modify[0x1]; 833 u8 nic_vport_port_guid_modify[0x1]; 834 835 u8 vxlan_encap_decap[0x1]; 836 u8 nvgre_encap_decap[0x1]; 837 u8 reserved_at_22[0x1]; 838 u8 log_max_fdb_encap_uplink[0x5]; 839 u8 reserved_at_21[0x3]; 840 u8 log_max_packet_reformat_context[0x5]; 841 u8 reserved_2b[0x6]; 842 u8 max_encap_header_size[0xa]; 843 844 u8 reserved_at_40[0xb]; 845 u8 log_max_esw_sf[0x5]; 846 u8 esw_sf_base_id[0x10]; 847 848 u8 reserved_at_60[0x7a0]; 849 850 }; 851 852 struct mlx5_ifc_qos_cap_bits { 853 u8 packet_pacing[0x1]; 854 u8 esw_scheduling[0x1]; 855 u8 esw_bw_share[0x1]; 856 u8 esw_rate_limit[0x1]; 857 u8 reserved_at_4[0x1]; 858 u8 packet_pacing_burst_bound[0x1]; 859 u8 packet_pacing_typical_size[0x1]; 860 u8 reserved_at_7[0x1]; 861 u8 nic_sq_scheduling[0x1]; 862 u8 nic_bw_share[0x1]; 863 u8 nic_rate_limit[0x1]; 864 u8 packet_pacing_uid[0x1]; 865 u8 reserved_at_c[0x14]; 866 867 u8 reserved_at_20[0xb]; 868 u8 log_max_qos_nic_queue_group[0x5]; 869 u8 reserved_at_30[0x10]; 870 871 u8 packet_pacing_max_rate[0x20]; 872 873 u8 packet_pacing_min_rate[0x20]; 874 875 u8 reserved_at_80[0x10]; 876 u8 packet_pacing_rate_table_size[0x10]; 877 878 u8 esw_element_type[0x10]; 879 u8 esw_tsar_type[0x10]; 880 881 u8 reserved_at_c0[0x10]; 882 u8 max_qos_para_vport[0x10]; 883 884 u8 max_tsar_bw_share[0x20]; 885 886 u8 reserved_at_100[0x700]; 887 }; 888 889 struct mlx5_ifc_debug_cap_bits { 890 u8 core_dump_general[0x1]; 891 u8 core_dump_qp[0x1]; 892 u8 reserved_at_2[0x7]; 893 u8 resource_dump[0x1]; 894 u8 reserved_at_a[0x16]; 895 896 u8 reserved_at_20[0x2]; 897 u8 stall_detect[0x1]; 898 u8 reserved_at_23[0x1d]; 899 900 u8 reserved_at_40[0x7c0]; 901 }; 902 903 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 904 u8 csum_cap[0x1]; 905 u8 vlan_cap[0x1]; 906 u8 lro_cap[0x1]; 907 u8 lro_psh_flag[0x1]; 908 u8 lro_time_stamp[0x1]; 909 u8 reserved_at_5[0x2]; 910 u8 wqe_vlan_insert[0x1]; 911 u8 self_lb_en_modifiable[0x1]; 912 u8 reserved_at_9[0x2]; 913 u8 max_lso_cap[0x5]; 914 u8 multi_pkt_send_wqe[0x2]; 915 u8 wqe_inline_mode[0x2]; 916 u8 rss_ind_tbl_cap[0x4]; 917 u8 reg_umr_sq[0x1]; 918 u8 scatter_fcs[0x1]; 919 u8 enhanced_multi_pkt_send_wqe[0x1]; 920 u8 tunnel_lso_const_out_ip_id[0x1]; 921 u8 reserved_at_1c[0x2]; 922 u8 tunnel_stateless_gre[0x1]; 923 u8 tunnel_stateless_vxlan[0x1]; 924 925 u8 swp[0x1]; 926 u8 swp_csum[0x1]; 927 u8 swp_lso[0x1]; 928 u8 cqe_checksum_full[0x1]; 929 u8 tunnel_stateless_geneve_tx[0x1]; 930 u8 tunnel_stateless_mpls_over_udp[0x1]; 931 u8 tunnel_stateless_mpls_over_gre[0x1]; 932 u8 tunnel_stateless_vxlan_gpe[0x1]; 933 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 934 u8 tunnel_stateless_ip_over_ip[0x1]; 935 u8 insert_trailer[0x1]; 936 u8 reserved_at_2b[0x1]; 937 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 938 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 939 u8 reserved_at_2e[0x2]; 940 u8 max_vxlan_udp_ports[0x8]; 941 u8 reserved_at_38[0x6]; 942 u8 max_geneve_opt_len[0x1]; 943 u8 tunnel_stateless_geneve_rx[0x1]; 944 945 u8 reserved_at_40[0x10]; 946 u8 lro_min_mss_size[0x10]; 947 948 u8 reserved_at_60[0x120]; 949 950 u8 lro_timer_supported_periods[4][0x20]; 951 952 u8 reserved_at_200[0x600]; 953 }; 954 955 enum { 956 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 957 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 958 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 959 }; 960 961 struct mlx5_ifc_roce_cap_bits { 962 u8 roce_apm[0x1]; 963 u8 reserved_at_1[0x3]; 964 u8 sw_r_roce_src_udp_port[0x1]; 965 u8 fl_rc_qp_when_roce_disabled[0x1]; 966 u8 fl_rc_qp_when_roce_enabled[0x1]; 967 u8 reserved_at_7[0x17]; 968 u8 qp_ts_format[0x2]; 969 970 u8 reserved_at_20[0x60]; 971 972 u8 reserved_at_80[0xc]; 973 u8 l3_type[0x4]; 974 u8 reserved_at_90[0x8]; 975 u8 roce_version[0x8]; 976 977 u8 reserved_at_a0[0x10]; 978 u8 r_roce_dest_udp_port[0x10]; 979 980 u8 r_roce_max_src_udp_port[0x10]; 981 u8 r_roce_min_src_udp_port[0x10]; 982 983 u8 reserved_at_e0[0x10]; 984 u8 roce_address_table_size[0x10]; 985 986 u8 reserved_at_100[0x700]; 987 }; 988 989 struct mlx5_ifc_sync_steering_in_bits { 990 u8 opcode[0x10]; 991 u8 uid[0x10]; 992 993 u8 reserved_at_20[0x10]; 994 u8 op_mod[0x10]; 995 996 u8 reserved_at_40[0xc0]; 997 }; 998 999 struct mlx5_ifc_sync_steering_out_bits { 1000 u8 status[0x8]; 1001 u8 reserved_at_8[0x18]; 1002 1003 u8 syndrome[0x20]; 1004 1005 u8 reserved_at_40[0x40]; 1006 }; 1007 1008 struct mlx5_ifc_device_mem_cap_bits { 1009 u8 memic[0x1]; 1010 u8 reserved_at_1[0x1f]; 1011 1012 u8 reserved_at_20[0xb]; 1013 u8 log_min_memic_alloc_size[0x5]; 1014 u8 reserved_at_30[0x8]; 1015 u8 log_max_memic_addr_alignment[0x8]; 1016 1017 u8 memic_bar_start_addr[0x40]; 1018 1019 u8 memic_bar_size[0x20]; 1020 1021 u8 max_memic_size[0x20]; 1022 1023 u8 steering_sw_icm_start_address[0x40]; 1024 1025 u8 reserved_at_100[0x8]; 1026 u8 log_header_modify_sw_icm_size[0x8]; 1027 u8 reserved_at_110[0x2]; 1028 u8 log_sw_icm_alloc_granularity[0x6]; 1029 u8 log_steering_sw_icm_size[0x8]; 1030 1031 u8 reserved_at_120[0x20]; 1032 1033 u8 header_modify_sw_icm_start_address[0x40]; 1034 1035 u8 reserved_at_180[0x80]; 1036 1037 u8 memic_operations[0x20]; 1038 1039 u8 reserved_at_220[0x5e0]; 1040 }; 1041 1042 struct mlx5_ifc_device_event_cap_bits { 1043 u8 user_affiliated_events[4][0x40]; 1044 1045 u8 user_unaffiliated_events[4][0x40]; 1046 }; 1047 1048 struct mlx5_ifc_virtio_emulation_cap_bits { 1049 u8 desc_tunnel_offload_type[0x1]; 1050 u8 eth_frame_offload_type[0x1]; 1051 u8 virtio_version_1_0[0x1]; 1052 u8 device_features_bits_mask[0xd]; 1053 u8 event_mode[0x8]; 1054 u8 virtio_queue_type[0x8]; 1055 1056 u8 max_tunnel_desc[0x10]; 1057 u8 reserved_at_30[0x3]; 1058 u8 log_doorbell_stride[0x5]; 1059 u8 reserved_at_38[0x3]; 1060 u8 log_doorbell_bar_size[0x5]; 1061 1062 u8 doorbell_bar_offset[0x40]; 1063 1064 u8 max_emulated_devices[0x8]; 1065 u8 max_num_virtio_queues[0x18]; 1066 1067 u8 reserved_at_a0[0x60]; 1068 1069 u8 umem_1_buffer_param_a[0x20]; 1070 1071 u8 umem_1_buffer_param_b[0x20]; 1072 1073 u8 umem_2_buffer_param_a[0x20]; 1074 1075 u8 umem_2_buffer_param_b[0x20]; 1076 1077 u8 umem_3_buffer_param_a[0x20]; 1078 1079 u8 umem_3_buffer_param_b[0x20]; 1080 1081 u8 reserved_at_1c0[0x640]; 1082 }; 1083 1084 enum { 1085 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1086 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1087 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1088 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1089 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1090 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1091 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1092 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1093 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1094 }; 1095 1096 enum { 1097 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1098 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1099 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1100 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1101 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1102 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1103 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1104 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1105 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1106 }; 1107 1108 struct mlx5_ifc_atomic_caps_bits { 1109 u8 reserved_at_0[0x40]; 1110 1111 u8 atomic_req_8B_endianness_mode[0x2]; 1112 u8 reserved_at_42[0x4]; 1113 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1114 1115 u8 reserved_at_47[0x19]; 1116 1117 u8 reserved_at_60[0x20]; 1118 1119 u8 reserved_at_80[0x10]; 1120 u8 atomic_operations[0x10]; 1121 1122 u8 reserved_at_a0[0x10]; 1123 u8 atomic_size_qp[0x10]; 1124 1125 u8 reserved_at_c0[0x10]; 1126 u8 atomic_size_dc[0x10]; 1127 1128 u8 reserved_at_e0[0x720]; 1129 }; 1130 1131 struct mlx5_ifc_odp_cap_bits { 1132 u8 reserved_at_0[0x40]; 1133 1134 u8 sig[0x1]; 1135 u8 reserved_at_41[0x1f]; 1136 1137 u8 reserved_at_60[0x20]; 1138 1139 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1140 1141 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1142 1143 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1144 1145 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1146 1147 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1148 1149 u8 reserved_at_120[0x6E0]; 1150 }; 1151 1152 struct mlx5_ifc_calc_op { 1153 u8 reserved_at_0[0x10]; 1154 u8 reserved_at_10[0x9]; 1155 u8 op_swap_endianness[0x1]; 1156 u8 op_min[0x1]; 1157 u8 op_xor[0x1]; 1158 u8 op_or[0x1]; 1159 u8 op_and[0x1]; 1160 u8 op_max[0x1]; 1161 u8 op_add[0x1]; 1162 }; 1163 1164 struct mlx5_ifc_vector_calc_cap_bits { 1165 u8 calc_matrix[0x1]; 1166 u8 reserved_at_1[0x1f]; 1167 u8 reserved_at_20[0x8]; 1168 u8 max_vec_count[0x8]; 1169 u8 reserved_at_30[0xd]; 1170 u8 max_chunk_size[0x3]; 1171 struct mlx5_ifc_calc_op calc0; 1172 struct mlx5_ifc_calc_op calc1; 1173 struct mlx5_ifc_calc_op calc2; 1174 struct mlx5_ifc_calc_op calc3; 1175 1176 u8 reserved_at_c0[0x720]; 1177 }; 1178 1179 struct mlx5_ifc_tls_cap_bits { 1180 u8 tls_1_2_aes_gcm_128[0x1]; 1181 u8 tls_1_3_aes_gcm_128[0x1]; 1182 u8 tls_1_2_aes_gcm_256[0x1]; 1183 u8 tls_1_3_aes_gcm_256[0x1]; 1184 u8 reserved_at_4[0x1c]; 1185 1186 u8 reserved_at_20[0x7e0]; 1187 }; 1188 1189 struct mlx5_ifc_ipsec_cap_bits { 1190 u8 ipsec_full_offload[0x1]; 1191 u8 ipsec_crypto_offload[0x1]; 1192 u8 ipsec_esn[0x1]; 1193 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1194 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1195 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1196 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1197 u8 reserved_at_7[0x4]; 1198 u8 log_max_ipsec_offload[0x5]; 1199 u8 reserved_at_10[0x10]; 1200 1201 u8 min_log_ipsec_full_replay_window[0x8]; 1202 u8 max_log_ipsec_full_replay_window[0x8]; 1203 u8 reserved_at_30[0x7d0]; 1204 }; 1205 1206 enum { 1207 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1208 MLX5_WQ_TYPE_CYCLIC = 0x1, 1209 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1210 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1211 }; 1212 1213 enum { 1214 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1215 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1216 }; 1217 1218 enum { 1219 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1220 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1221 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1222 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1223 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1224 }; 1225 1226 enum { 1227 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1228 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1229 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1230 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1231 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1232 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1233 }; 1234 1235 enum { 1236 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1237 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1238 }; 1239 1240 enum { 1241 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1242 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1243 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1244 }; 1245 1246 enum { 1247 MLX5_CAP_PORT_TYPE_IB = 0x0, 1248 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1249 }; 1250 1251 enum { 1252 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1253 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1254 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1255 }; 1256 1257 enum { 1258 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1259 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1260 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1261 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1262 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1263 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1264 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1265 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1266 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1267 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1268 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1269 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1270 }; 1271 1272 enum { 1273 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1274 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1275 }; 1276 1277 #define MLX5_FC_BULK_SIZE_FACTOR 128 1278 1279 enum mlx5_fc_bulk_alloc_bitmask { 1280 MLX5_FC_BULK_128 = (1 << 0), 1281 MLX5_FC_BULK_256 = (1 << 1), 1282 MLX5_FC_BULK_512 = (1 << 2), 1283 MLX5_FC_BULK_1024 = (1 << 3), 1284 MLX5_FC_BULK_2048 = (1 << 4), 1285 MLX5_FC_BULK_4096 = (1 << 5), 1286 MLX5_FC_BULK_8192 = (1 << 6), 1287 MLX5_FC_BULK_16384 = (1 << 7), 1288 }; 1289 1290 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1291 1292 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1293 1294 enum { 1295 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1296 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1297 }; 1298 1299 enum { 1300 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1301 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1302 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1303 }; 1304 1305 enum { 1306 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1307 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1308 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1309 }; 1310 1311 struct mlx5_ifc_cmd_hca_cap_bits { 1312 u8 reserved_at_0[0x1f]; 1313 u8 vhca_resource_manager[0x1]; 1314 1315 u8 reserved_at_20[0x3]; 1316 u8 event_on_vhca_state_teardown_request[0x1]; 1317 u8 event_on_vhca_state_in_use[0x1]; 1318 u8 event_on_vhca_state_active[0x1]; 1319 u8 event_on_vhca_state_allocated[0x1]; 1320 u8 event_on_vhca_state_invalid[0x1]; 1321 u8 reserved_at_28[0x8]; 1322 u8 vhca_id[0x10]; 1323 1324 u8 reserved_at_40[0x40]; 1325 1326 u8 log_max_srq_sz[0x8]; 1327 u8 log_max_qp_sz[0x8]; 1328 u8 event_cap[0x1]; 1329 u8 reserved_at_91[0x2]; 1330 u8 isolate_vl_tc_new[0x1]; 1331 u8 reserved_at_94[0x4]; 1332 u8 prio_tag_required[0x1]; 1333 u8 reserved_at_99[0x2]; 1334 u8 log_max_qp[0x5]; 1335 1336 u8 reserved_at_a0[0x3]; 1337 u8 ece_support[0x1]; 1338 u8 reserved_at_a4[0x5]; 1339 u8 reg_c_preserve[0x1]; 1340 u8 reserved_at_aa[0x1]; 1341 u8 log_max_srq[0x5]; 1342 u8 reserved_at_b0[0x1]; 1343 u8 uplink_follow[0x1]; 1344 u8 ts_cqe_to_dest_cqn[0x1]; 1345 u8 reserved_at_b3[0xd]; 1346 1347 u8 max_sgl_for_optimized_performance[0x8]; 1348 u8 log_max_cq_sz[0x8]; 1349 u8 relaxed_ordering_write_umr[0x1]; 1350 u8 relaxed_ordering_read_umr[0x1]; 1351 u8 reserved_at_d2[0x7]; 1352 u8 virtio_net_device_emualtion_manager[0x1]; 1353 u8 virtio_blk_device_emualtion_manager[0x1]; 1354 u8 log_max_cq[0x5]; 1355 1356 u8 log_max_eq_sz[0x8]; 1357 u8 relaxed_ordering_write[0x1]; 1358 u8 relaxed_ordering_read[0x1]; 1359 u8 log_max_mkey[0x6]; 1360 u8 reserved_at_f0[0x8]; 1361 u8 dump_fill_mkey[0x1]; 1362 u8 reserved_at_f9[0x2]; 1363 u8 fast_teardown[0x1]; 1364 u8 log_max_eq[0x4]; 1365 1366 u8 max_indirection[0x8]; 1367 u8 fixed_buffer_size[0x1]; 1368 u8 log_max_mrw_sz[0x7]; 1369 u8 force_teardown[0x1]; 1370 u8 reserved_at_111[0x1]; 1371 u8 log_max_bsf_list_size[0x6]; 1372 u8 umr_extended_translation_offset[0x1]; 1373 u8 null_mkey[0x1]; 1374 u8 log_max_klm_list_size[0x6]; 1375 1376 u8 reserved_at_120[0xa]; 1377 u8 log_max_ra_req_dc[0x6]; 1378 u8 reserved_at_130[0xa]; 1379 u8 log_max_ra_res_dc[0x6]; 1380 1381 u8 reserved_at_140[0x6]; 1382 u8 release_all_pages[0x1]; 1383 u8 reserved_at_147[0x2]; 1384 u8 roce_accl[0x1]; 1385 u8 log_max_ra_req_qp[0x6]; 1386 u8 reserved_at_150[0xa]; 1387 u8 log_max_ra_res_qp[0x6]; 1388 1389 u8 end_pad[0x1]; 1390 u8 cc_query_allowed[0x1]; 1391 u8 cc_modify_allowed[0x1]; 1392 u8 start_pad[0x1]; 1393 u8 cache_line_128byte[0x1]; 1394 u8 reserved_at_165[0x4]; 1395 u8 rts2rts_qp_counters_set_id[0x1]; 1396 u8 reserved_at_16a[0x2]; 1397 u8 vnic_env_int_rq_oob[0x1]; 1398 u8 sbcam_reg[0x1]; 1399 u8 reserved_at_16e[0x1]; 1400 u8 qcam_reg[0x1]; 1401 u8 gid_table_size[0x10]; 1402 1403 u8 out_of_seq_cnt[0x1]; 1404 u8 vport_counters[0x1]; 1405 u8 retransmission_q_counters[0x1]; 1406 u8 debug[0x1]; 1407 u8 modify_rq_counter_set_id[0x1]; 1408 u8 rq_delay_drop[0x1]; 1409 u8 max_qp_cnt[0xa]; 1410 u8 pkey_table_size[0x10]; 1411 1412 u8 vport_group_manager[0x1]; 1413 u8 vhca_group_manager[0x1]; 1414 u8 ib_virt[0x1]; 1415 u8 eth_virt[0x1]; 1416 u8 vnic_env_queue_counters[0x1]; 1417 u8 ets[0x1]; 1418 u8 nic_flow_table[0x1]; 1419 u8 eswitch_manager[0x1]; 1420 u8 device_memory[0x1]; 1421 u8 mcam_reg[0x1]; 1422 u8 pcam_reg[0x1]; 1423 u8 local_ca_ack_delay[0x5]; 1424 u8 port_module_event[0x1]; 1425 u8 enhanced_error_q_counters[0x1]; 1426 u8 ports_check[0x1]; 1427 u8 reserved_at_1b3[0x1]; 1428 u8 disable_link_up[0x1]; 1429 u8 beacon_led[0x1]; 1430 u8 port_type[0x2]; 1431 u8 num_ports[0x8]; 1432 1433 u8 reserved_at_1c0[0x1]; 1434 u8 pps[0x1]; 1435 u8 pps_modify[0x1]; 1436 u8 log_max_msg[0x5]; 1437 u8 reserved_at_1c8[0x4]; 1438 u8 max_tc[0x4]; 1439 u8 temp_warn_event[0x1]; 1440 u8 dcbx[0x1]; 1441 u8 general_notification_event[0x1]; 1442 u8 reserved_at_1d3[0x2]; 1443 u8 fpga[0x1]; 1444 u8 rol_s[0x1]; 1445 u8 rol_g[0x1]; 1446 u8 reserved_at_1d8[0x1]; 1447 u8 wol_s[0x1]; 1448 u8 wol_g[0x1]; 1449 u8 wol_a[0x1]; 1450 u8 wol_b[0x1]; 1451 u8 wol_m[0x1]; 1452 u8 wol_u[0x1]; 1453 u8 wol_p[0x1]; 1454 1455 u8 stat_rate_support[0x10]; 1456 u8 reserved_at_1f0[0x1]; 1457 u8 pci_sync_for_fw_update_event[0x1]; 1458 u8 reserved_at_1f2[0x6]; 1459 u8 init2_lag_tx_port_affinity[0x1]; 1460 u8 reserved_at_1fa[0x3]; 1461 u8 cqe_version[0x4]; 1462 1463 u8 compact_address_vector[0x1]; 1464 u8 striding_rq[0x1]; 1465 u8 reserved_at_202[0x1]; 1466 u8 ipoib_enhanced_offloads[0x1]; 1467 u8 ipoib_basic_offloads[0x1]; 1468 u8 reserved_at_205[0x1]; 1469 u8 repeated_block_disabled[0x1]; 1470 u8 umr_modify_entity_size_disabled[0x1]; 1471 u8 umr_modify_atomic_disabled[0x1]; 1472 u8 umr_indirect_mkey_disabled[0x1]; 1473 u8 umr_fence[0x2]; 1474 u8 dc_req_scat_data_cqe[0x1]; 1475 u8 reserved_at_20d[0x2]; 1476 u8 drain_sigerr[0x1]; 1477 u8 cmdif_checksum[0x2]; 1478 u8 sigerr_cqe[0x1]; 1479 u8 reserved_at_213[0x1]; 1480 u8 wq_signature[0x1]; 1481 u8 sctr_data_cqe[0x1]; 1482 u8 reserved_at_216[0x1]; 1483 u8 sho[0x1]; 1484 u8 tph[0x1]; 1485 u8 rf[0x1]; 1486 u8 dct[0x1]; 1487 u8 qos[0x1]; 1488 u8 eth_net_offloads[0x1]; 1489 u8 roce[0x1]; 1490 u8 atomic[0x1]; 1491 u8 reserved_at_21f[0x1]; 1492 1493 u8 cq_oi[0x1]; 1494 u8 cq_resize[0x1]; 1495 u8 cq_moderation[0x1]; 1496 u8 reserved_at_223[0x3]; 1497 u8 cq_eq_remap[0x1]; 1498 u8 pg[0x1]; 1499 u8 block_lb_mc[0x1]; 1500 u8 reserved_at_229[0x1]; 1501 u8 scqe_break_moderation[0x1]; 1502 u8 cq_period_start_from_cqe[0x1]; 1503 u8 cd[0x1]; 1504 u8 reserved_at_22d[0x1]; 1505 u8 apm[0x1]; 1506 u8 vector_calc[0x1]; 1507 u8 umr_ptr_rlky[0x1]; 1508 u8 imaicl[0x1]; 1509 u8 qp_packet_based[0x1]; 1510 u8 reserved_at_233[0x3]; 1511 u8 qkv[0x1]; 1512 u8 pkv[0x1]; 1513 u8 set_deth_sqpn[0x1]; 1514 u8 reserved_at_239[0x3]; 1515 u8 xrc[0x1]; 1516 u8 ud[0x1]; 1517 u8 uc[0x1]; 1518 u8 rc[0x1]; 1519 1520 u8 uar_4k[0x1]; 1521 u8 reserved_at_241[0x9]; 1522 u8 uar_sz[0x6]; 1523 u8 reserved_at_250[0x8]; 1524 u8 log_pg_sz[0x8]; 1525 1526 u8 bf[0x1]; 1527 u8 driver_version[0x1]; 1528 u8 pad_tx_eth_packet[0x1]; 1529 u8 reserved_at_263[0x3]; 1530 u8 mkey_by_name[0x1]; 1531 u8 reserved_at_267[0x4]; 1532 1533 u8 log_bf_reg_size[0x5]; 1534 1535 u8 reserved_at_270[0x6]; 1536 u8 lag_dct[0x2]; 1537 u8 lag_tx_port_affinity[0x1]; 1538 u8 lag_native_fdb_selection[0x1]; 1539 u8 reserved_at_27a[0x1]; 1540 u8 lag_master[0x1]; 1541 u8 num_lag_ports[0x4]; 1542 1543 u8 reserved_at_280[0x10]; 1544 u8 max_wqe_sz_sq[0x10]; 1545 1546 u8 reserved_at_2a0[0x10]; 1547 u8 max_wqe_sz_rq[0x10]; 1548 1549 u8 max_flow_counter_31_16[0x10]; 1550 u8 max_wqe_sz_sq_dc[0x10]; 1551 1552 u8 reserved_at_2e0[0x7]; 1553 u8 max_qp_mcg[0x19]; 1554 1555 u8 reserved_at_300[0x10]; 1556 u8 flow_counter_bulk_alloc[0x8]; 1557 u8 log_max_mcg[0x8]; 1558 1559 u8 reserved_at_320[0x3]; 1560 u8 log_max_transport_domain[0x5]; 1561 u8 reserved_at_328[0x3]; 1562 u8 log_max_pd[0x5]; 1563 u8 reserved_at_330[0xb]; 1564 u8 log_max_xrcd[0x5]; 1565 1566 u8 nic_receive_steering_discard[0x1]; 1567 u8 receive_discard_vport_down[0x1]; 1568 u8 transmit_discard_vport_down[0x1]; 1569 u8 reserved_at_343[0x5]; 1570 u8 log_max_flow_counter_bulk[0x8]; 1571 u8 max_flow_counter_15_0[0x10]; 1572 1573 1574 u8 reserved_at_360[0x3]; 1575 u8 log_max_rq[0x5]; 1576 u8 reserved_at_368[0x3]; 1577 u8 log_max_sq[0x5]; 1578 u8 reserved_at_370[0x3]; 1579 u8 log_max_tir[0x5]; 1580 u8 reserved_at_378[0x3]; 1581 u8 log_max_tis[0x5]; 1582 1583 u8 basic_cyclic_rcv_wqe[0x1]; 1584 u8 reserved_at_381[0x2]; 1585 u8 log_max_rmp[0x5]; 1586 u8 reserved_at_388[0x3]; 1587 u8 log_max_rqt[0x5]; 1588 u8 reserved_at_390[0x3]; 1589 u8 log_max_rqt_size[0x5]; 1590 u8 reserved_at_398[0x3]; 1591 u8 log_max_tis_per_sq[0x5]; 1592 1593 u8 ext_stride_num_range[0x1]; 1594 u8 reserved_at_3a1[0x2]; 1595 u8 log_max_stride_sz_rq[0x5]; 1596 u8 reserved_at_3a8[0x3]; 1597 u8 log_min_stride_sz_rq[0x5]; 1598 u8 reserved_at_3b0[0x3]; 1599 u8 log_max_stride_sz_sq[0x5]; 1600 u8 reserved_at_3b8[0x3]; 1601 u8 log_min_stride_sz_sq[0x5]; 1602 1603 u8 hairpin[0x1]; 1604 u8 reserved_at_3c1[0x2]; 1605 u8 log_max_hairpin_queues[0x5]; 1606 u8 reserved_at_3c8[0x3]; 1607 u8 log_max_hairpin_wq_data_sz[0x5]; 1608 u8 reserved_at_3d0[0x3]; 1609 u8 log_max_hairpin_num_packets[0x5]; 1610 u8 reserved_at_3d8[0x3]; 1611 u8 log_max_wq_sz[0x5]; 1612 1613 u8 nic_vport_change_event[0x1]; 1614 u8 disable_local_lb_uc[0x1]; 1615 u8 disable_local_lb_mc[0x1]; 1616 u8 log_min_hairpin_wq_data_sz[0x5]; 1617 u8 reserved_at_3e8[0x2]; 1618 u8 vhca_state[0x1]; 1619 u8 log_max_vlan_list[0x5]; 1620 u8 reserved_at_3f0[0x3]; 1621 u8 log_max_current_mc_list[0x5]; 1622 u8 reserved_at_3f8[0x3]; 1623 u8 log_max_current_uc_list[0x5]; 1624 1625 u8 general_obj_types[0x40]; 1626 1627 u8 sq_ts_format[0x2]; 1628 u8 rq_ts_format[0x2]; 1629 u8 steering_format_version[0x4]; 1630 u8 create_qp_start_hint[0x18]; 1631 1632 u8 reserved_at_460[0x3]; 1633 u8 log_max_uctx[0x5]; 1634 u8 reserved_at_468[0x2]; 1635 u8 ipsec_offload[0x1]; 1636 u8 log_max_umem[0x5]; 1637 u8 max_num_eqs[0x10]; 1638 1639 u8 reserved_at_480[0x1]; 1640 u8 tls_tx[0x1]; 1641 u8 tls_rx[0x1]; 1642 u8 log_max_l2_table[0x5]; 1643 u8 reserved_at_488[0x8]; 1644 u8 log_uar_page_sz[0x10]; 1645 1646 u8 reserved_at_4a0[0x20]; 1647 u8 device_frequency_mhz[0x20]; 1648 u8 device_frequency_khz[0x20]; 1649 1650 u8 reserved_at_500[0x20]; 1651 u8 num_of_uars_per_page[0x20]; 1652 1653 u8 flex_parser_protocols[0x20]; 1654 1655 u8 max_geneve_tlv_options[0x8]; 1656 u8 reserved_at_568[0x3]; 1657 u8 max_geneve_tlv_option_data_len[0x5]; 1658 u8 reserved_at_570[0x10]; 1659 1660 u8 reserved_at_580[0x33]; 1661 u8 log_max_dek[0x5]; 1662 u8 reserved_at_5b8[0x4]; 1663 u8 mini_cqe_resp_stride_index[0x1]; 1664 u8 cqe_128_always[0x1]; 1665 u8 cqe_compression_128[0x1]; 1666 u8 cqe_compression[0x1]; 1667 1668 u8 cqe_compression_timeout[0x10]; 1669 u8 cqe_compression_max_num[0x10]; 1670 1671 u8 reserved_at_5e0[0x8]; 1672 u8 flex_parser_id_gtpu_dw_0[0x4]; 1673 u8 reserved_at_5ec[0x4]; 1674 u8 tag_matching[0x1]; 1675 u8 rndv_offload_rc[0x1]; 1676 u8 rndv_offload_dc[0x1]; 1677 u8 log_tag_matching_list_sz[0x5]; 1678 u8 reserved_at_5f8[0x3]; 1679 u8 log_max_xrq[0x5]; 1680 1681 u8 affiliate_nic_vport_criteria[0x8]; 1682 u8 native_port_num[0x8]; 1683 u8 num_vhca_ports[0x8]; 1684 u8 flex_parser_id_gtpu_teid[0x4]; 1685 u8 reserved_at_61c[0x2]; 1686 u8 sw_owner_id[0x1]; 1687 u8 reserved_at_61f[0x1]; 1688 1689 u8 max_num_of_monitor_counters[0x10]; 1690 u8 num_ppcnt_monitor_counters[0x10]; 1691 1692 u8 max_num_sf[0x10]; 1693 u8 num_q_monitor_counters[0x10]; 1694 1695 u8 reserved_at_660[0x20]; 1696 1697 u8 sf[0x1]; 1698 u8 sf_set_partition[0x1]; 1699 u8 reserved_at_682[0x1]; 1700 u8 log_max_sf[0x5]; 1701 u8 apu[0x1]; 1702 u8 reserved_at_689[0x7]; 1703 u8 log_min_sf_size[0x8]; 1704 u8 max_num_sf_partitions[0x8]; 1705 1706 u8 uctx_cap[0x20]; 1707 1708 u8 reserved_at_6c0[0x4]; 1709 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1710 u8 flex_parser_id_icmp_dw1[0x4]; 1711 u8 flex_parser_id_icmp_dw0[0x4]; 1712 u8 flex_parser_id_icmpv6_dw1[0x4]; 1713 u8 flex_parser_id_icmpv6_dw0[0x4]; 1714 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1715 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1716 1717 u8 reserved_at_6e0[0x10]; 1718 u8 sf_base_id[0x10]; 1719 1720 u8 flex_parser_id_gtpu_dw_2[0x4]; 1721 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1722 u8 num_total_dynamic_vf_msix[0x18]; 1723 u8 reserved_at_720[0x14]; 1724 u8 dynamic_msix_table_size[0xc]; 1725 u8 reserved_at_740[0xc]; 1726 u8 min_dynamic_vf_msix_table_size[0x4]; 1727 u8 reserved_at_750[0x4]; 1728 u8 max_dynamic_vf_msix_table_size[0xc]; 1729 1730 u8 reserved_at_760[0x20]; 1731 u8 vhca_tunnel_commands[0x40]; 1732 u8 reserved_at_7c0[0x40]; 1733 }; 1734 1735 enum mlx5_flow_destination_type { 1736 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1737 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1738 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1739 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1740 1741 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1742 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1743 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1744 }; 1745 1746 enum mlx5_flow_table_miss_action { 1747 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1748 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1749 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1750 }; 1751 1752 struct mlx5_ifc_dest_format_struct_bits { 1753 u8 destination_type[0x8]; 1754 u8 destination_id[0x18]; 1755 1756 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1757 u8 packet_reformat[0x1]; 1758 u8 reserved_at_22[0xe]; 1759 u8 destination_eswitch_owner_vhca_id[0x10]; 1760 }; 1761 1762 struct mlx5_ifc_flow_counter_list_bits { 1763 u8 flow_counter_id[0x20]; 1764 1765 u8 reserved_at_20[0x20]; 1766 }; 1767 1768 struct mlx5_ifc_extended_dest_format_bits { 1769 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1770 1771 u8 packet_reformat_id[0x20]; 1772 1773 u8 reserved_at_60[0x20]; 1774 }; 1775 1776 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1777 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1778 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1779 }; 1780 1781 struct mlx5_ifc_fte_match_param_bits { 1782 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1783 1784 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1785 1786 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1787 1788 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1789 1790 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1791 1792 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1793 1794 u8 reserved_at_c00[0x400]; 1795 }; 1796 1797 enum { 1798 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1799 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1800 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1801 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1802 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1803 }; 1804 1805 struct mlx5_ifc_rx_hash_field_select_bits { 1806 u8 l3_prot_type[0x1]; 1807 u8 l4_prot_type[0x1]; 1808 u8 selected_fields[0x1e]; 1809 }; 1810 1811 enum { 1812 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1813 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1814 }; 1815 1816 enum { 1817 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1818 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1819 }; 1820 1821 struct mlx5_ifc_wq_bits { 1822 u8 wq_type[0x4]; 1823 u8 wq_signature[0x1]; 1824 u8 end_padding_mode[0x2]; 1825 u8 cd_slave[0x1]; 1826 u8 reserved_at_8[0x18]; 1827 1828 u8 hds_skip_first_sge[0x1]; 1829 u8 log2_hds_buf_size[0x3]; 1830 u8 reserved_at_24[0x7]; 1831 u8 page_offset[0x5]; 1832 u8 lwm[0x10]; 1833 1834 u8 reserved_at_40[0x8]; 1835 u8 pd[0x18]; 1836 1837 u8 reserved_at_60[0x8]; 1838 u8 uar_page[0x18]; 1839 1840 u8 dbr_addr[0x40]; 1841 1842 u8 hw_counter[0x20]; 1843 1844 u8 sw_counter[0x20]; 1845 1846 u8 reserved_at_100[0xc]; 1847 u8 log_wq_stride[0x4]; 1848 u8 reserved_at_110[0x3]; 1849 u8 log_wq_pg_sz[0x5]; 1850 u8 reserved_at_118[0x3]; 1851 u8 log_wq_sz[0x5]; 1852 1853 u8 dbr_umem_valid[0x1]; 1854 u8 wq_umem_valid[0x1]; 1855 u8 reserved_at_122[0x1]; 1856 u8 log_hairpin_num_packets[0x5]; 1857 u8 reserved_at_128[0x3]; 1858 u8 log_hairpin_data_sz[0x5]; 1859 1860 u8 reserved_at_130[0x4]; 1861 u8 log_wqe_num_of_strides[0x4]; 1862 u8 two_byte_shift_en[0x1]; 1863 u8 reserved_at_139[0x4]; 1864 u8 log_wqe_stride_size[0x3]; 1865 1866 u8 reserved_at_140[0x4c0]; 1867 1868 struct mlx5_ifc_cmd_pas_bits pas[]; 1869 }; 1870 1871 struct mlx5_ifc_rq_num_bits { 1872 u8 reserved_at_0[0x8]; 1873 u8 rq_num[0x18]; 1874 }; 1875 1876 struct mlx5_ifc_mac_address_layout_bits { 1877 u8 reserved_at_0[0x10]; 1878 u8 mac_addr_47_32[0x10]; 1879 1880 u8 mac_addr_31_0[0x20]; 1881 }; 1882 1883 struct mlx5_ifc_vlan_layout_bits { 1884 u8 reserved_at_0[0x14]; 1885 u8 vlan[0x0c]; 1886 1887 u8 reserved_at_20[0x20]; 1888 }; 1889 1890 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1891 u8 reserved_at_0[0xa0]; 1892 1893 u8 min_time_between_cnps[0x20]; 1894 1895 u8 reserved_at_c0[0x12]; 1896 u8 cnp_dscp[0x6]; 1897 u8 reserved_at_d8[0x4]; 1898 u8 cnp_prio_mode[0x1]; 1899 u8 cnp_802p_prio[0x3]; 1900 1901 u8 reserved_at_e0[0x720]; 1902 }; 1903 1904 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1905 u8 reserved_at_0[0x60]; 1906 1907 u8 reserved_at_60[0x4]; 1908 u8 clamp_tgt_rate[0x1]; 1909 u8 reserved_at_65[0x3]; 1910 u8 clamp_tgt_rate_after_time_inc[0x1]; 1911 u8 reserved_at_69[0x17]; 1912 1913 u8 reserved_at_80[0x20]; 1914 1915 u8 rpg_time_reset[0x20]; 1916 1917 u8 rpg_byte_reset[0x20]; 1918 1919 u8 rpg_threshold[0x20]; 1920 1921 u8 rpg_max_rate[0x20]; 1922 1923 u8 rpg_ai_rate[0x20]; 1924 1925 u8 rpg_hai_rate[0x20]; 1926 1927 u8 rpg_gd[0x20]; 1928 1929 u8 rpg_min_dec_fac[0x20]; 1930 1931 u8 rpg_min_rate[0x20]; 1932 1933 u8 reserved_at_1c0[0xe0]; 1934 1935 u8 rate_to_set_on_first_cnp[0x20]; 1936 1937 u8 dce_tcp_g[0x20]; 1938 1939 u8 dce_tcp_rtt[0x20]; 1940 1941 u8 rate_reduce_monitor_period[0x20]; 1942 1943 u8 reserved_at_320[0x20]; 1944 1945 u8 initial_alpha_value[0x20]; 1946 1947 u8 reserved_at_360[0x4a0]; 1948 }; 1949 1950 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1951 u8 reserved_at_0[0x80]; 1952 1953 u8 rppp_max_rps[0x20]; 1954 1955 u8 rpg_time_reset[0x20]; 1956 1957 u8 rpg_byte_reset[0x20]; 1958 1959 u8 rpg_threshold[0x20]; 1960 1961 u8 rpg_max_rate[0x20]; 1962 1963 u8 rpg_ai_rate[0x20]; 1964 1965 u8 rpg_hai_rate[0x20]; 1966 1967 u8 rpg_gd[0x20]; 1968 1969 u8 rpg_min_dec_fac[0x20]; 1970 1971 u8 rpg_min_rate[0x20]; 1972 1973 u8 reserved_at_1c0[0x640]; 1974 }; 1975 1976 enum { 1977 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1978 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1979 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1980 }; 1981 1982 struct mlx5_ifc_resize_field_select_bits { 1983 u8 resize_field_select[0x20]; 1984 }; 1985 1986 struct mlx5_ifc_resource_dump_bits { 1987 u8 more_dump[0x1]; 1988 u8 inline_dump[0x1]; 1989 u8 reserved_at_2[0xa]; 1990 u8 seq_num[0x4]; 1991 u8 segment_type[0x10]; 1992 1993 u8 reserved_at_20[0x10]; 1994 u8 vhca_id[0x10]; 1995 1996 u8 index1[0x20]; 1997 1998 u8 index2[0x20]; 1999 2000 u8 num_of_obj1[0x10]; 2001 u8 num_of_obj2[0x10]; 2002 2003 u8 reserved_at_a0[0x20]; 2004 2005 u8 device_opaque[0x40]; 2006 2007 u8 mkey[0x20]; 2008 2009 u8 size[0x20]; 2010 2011 u8 address[0x40]; 2012 2013 u8 inline_data[52][0x20]; 2014 }; 2015 2016 struct mlx5_ifc_resource_dump_menu_record_bits { 2017 u8 reserved_at_0[0x4]; 2018 u8 num_of_obj2_supports_active[0x1]; 2019 u8 num_of_obj2_supports_all[0x1]; 2020 u8 must_have_num_of_obj2[0x1]; 2021 u8 support_num_of_obj2[0x1]; 2022 u8 num_of_obj1_supports_active[0x1]; 2023 u8 num_of_obj1_supports_all[0x1]; 2024 u8 must_have_num_of_obj1[0x1]; 2025 u8 support_num_of_obj1[0x1]; 2026 u8 must_have_index2[0x1]; 2027 u8 support_index2[0x1]; 2028 u8 must_have_index1[0x1]; 2029 u8 support_index1[0x1]; 2030 u8 segment_type[0x10]; 2031 2032 u8 segment_name[4][0x20]; 2033 2034 u8 index1_name[4][0x20]; 2035 2036 u8 index2_name[4][0x20]; 2037 }; 2038 2039 struct mlx5_ifc_resource_dump_segment_header_bits { 2040 u8 length_dw[0x10]; 2041 u8 segment_type[0x10]; 2042 }; 2043 2044 struct mlx5_ifc_resource_dump_command_segment_bits { 2045 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2046 2047 u8 segment_called[0x10]; 2048 u8 vhca_id[0x10]; 2049 2050 u8 index1[0x20]; 2051 2052 u8 index2[0x20]; 2053 2054 u8 num_of_obj1[0x10]; 2055 u8 num_of_obj2[0x10]; 2056 }; 2057 2058 struct mlx5_ifc_resource_dump_error_segment_bits { 2059 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2060 2061 u8 reserved_at_20[0x10]; 2062 u8 syndrome_id[0x10]; 2063 2064 u8 reserved_at_40[0x40]; 2065 2066 u8 error[8][0x20]; 2067 }; 2068 2069 struct mlx5_ifc_resource_dump_info_segment_bits { 2070 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2071 2072 u8 reserved_at_20[0x18]; 2073 u8 dump_version[0x8]; 2074 2075 u8 hw_version[0x20]; 2076 2077 u8 fw_version[0x20]; 2078 }; 2079 2080 struct mlx5_ifc_resource_dump_menu_segment_bits { 2081 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2082 2083 u8 reserved_at_20[0x10]; 2084 u8 num_of_records[0x10]; 2085 2086 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2087 }; 2088 2089 struct mlx5_ifc_resource_dump_resource_segment_bits { 2090 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2091 2092 u8 reserved_at_20[0x20]; 2093 2094 u8 index1[0x20]; 2095 2096 u8 index2[0x20]; 2097 2098 u8 payload[][0x20]; 2099 }; 2100 2101 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2102 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2103 }; 2104 2105 struct mlx5_ifc_menu_resource_dump_response_bits { 2106 struct mlx5_ifc_resource_dump_info_segment_bits info; 2107 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2108 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2109 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2110 }; 2111 2112 enum { 2113 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2114 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2115 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2116 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2117 }; 2118 2119 struct mlx5_ifc_modify_field_select_bits { 2120 u8 modify_field_select[0x20]; 2121 }; 2122 2123 struct mlx5_ifc_field_select_r_roce_np_bits { 2124 u8 field_select_r_roce_np[0x20]; 2125 }; 2126 2127 struct mlx5_ifc_field_select_r_roce_rp_bits { 2128 u8 field_select_r_roce_rp[0x20]; 2129 }; 2130 2131 enum { 2132 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2133 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2134 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2135 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2136 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2137 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2138 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2139 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2140 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2141 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2142 }; 2143 2144 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2145 u8 field_select_8021qaurp[0x20]; 2146 }; 2147 2148 struct mlx5_ifc_phys_layer_cntrs_bits { 2149 u8 time_since_last_clear_high[0x20]; 2150 2151 u8 time_since_last_clear_low[0x20]; 2152 2153 u8 symbol_errors_high[0x20]; 2154 2155 u8 symbol_errors_low[0x20]; 2156 2157 u8 sync_headers_errors_high[0x20]; 2158 2159 u8 sync_headers_errors_low[0x20]; 2160 2161 u8 edpl_bip_errors_lane0_high[0x20]; 2162 2163 u8 edpl_bip_errors_lane0_low[0x20]; 2164 2165 u8 edpl_bip_errors_lane1_high[0x20]; 2166 2167 u8 edpl_bip_errors_lane1_low[0x20]; 2168 2169 u8 edpl_bip_errors_lane2_high[0x20]; 2170 2171 u8 edpl_bip_errors_lane2_low[0x20]; 2172 2173 u8 edpl_bip_errors_lane3_high[0x20]; 2174 2175 u8 edpl_bip_errors_lane3_low[0x20]; 2176 2177 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2178 2179 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2180 2181 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2182 2183 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2184 2185 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2186 2187 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2188 2189 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2190 2191 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2192 2193 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2194 2195 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2196 2197 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2198 2199 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2200 2201 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2202 2203 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2204 2205 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2206 2207 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2208 2209 u8 rs_fec_corrected_blocks_high[0x20]; 2210 2211 u8 rs_fec_corrected_blocks_low[0x20]; 2212 2213 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2214 2215 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2216 2217 u8 rs_fec_no_errors_blocks_high[0x20]; 2218 2219 u8 rs_fec_no_errors_blocks_low[0x20]; 2220 2221 u8 rs_fec_single_error_blocks_high[0x20]; 2222 2223 u8 rs_fec_single_error_blocks_low[0x20]; 2224 2225 u8 rs_fec_corrected_symbols_total_high[0x20]; 2226 2227 u8 rs_fec_corrected_symbols_total_low[0x20]; 2228 2229 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2230 2231 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2232 2233 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2234 2235 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2236 2237 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2238 2239 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2240 2241 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2242 2243 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2244 2245 u8 link_down_events[0x20]; 2246 2247 u8 successful_recovery_events[0x20]; 2248 2249 u8 reserved_at_640[0x180]; 2250 }; 2251 2252 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2253 u8 time_since_last_clear_high[0x20]; 2254 2255 u8 time_since_last_clear_low[0x20]; 2256 2257 u8 phy_received_bits_high[0x20]; 2258 2259 u8 phy_received_bits_low[0x20]; 2260 2261 u8 phy_symbol_errors_high[0x20]; 2262 2263 u8 phy_symbol_errors_low[0x20]; 2264 2265 u8 phy_corrected_bits_high[0x20]; 2266 2267 u8 phy_corrected_bits_low[0x20]; 2268 2269 u8 phy_corrected_bits_lane0_high[0x20]; 2270 2271 u8 phy_corrected_bits_lane0_low[0x20]; 2272 2273 u8 phy_corrected_bits_lane1_high[0x20]; 2274 2275 u8 phy_corrected_bits_lane1_low[0x20]; 2276 2277 u8 phy_corrected_bits_lane2_high[0x20]; 2278 2279 u8 phy_corrected_bits_lane2_low[0x20]; 2280 2281 u8 phy_corrected_bits_lane3_high[0x20]; 2282 2283 u8 phy_corrected_bits_lane3_low[0x20]; 2284 2285 u8 reserved_at_200[0x5c0]; 2286 }; 2287 2288 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2289 u8 symbol_error_counter[0x10]; 2290 2291 u8 link_error_recovery_counter[0x8]; 2292 2293 u8 link_downed_counter[0x8]; 2294 2295 u8 port_rcv_errors[0x10]; 2296 2297 u8 port_rcv_remote_physical_errors[0x10]; 2298 2299 u8 port_rcv_switch_relay_errors[0x10]; 2300 2301 u8 port_xmit_discards[0x10]; 2302 2303 u8 port_xmit_constraint_errors[0x8]; 2304 2305 u8 port_rcv_constraint_errors[0x8]; 2306 2307 u8 reserved_at_70[0x8]; 2308 2309 u8 link_overrun_errors[0x8]; 2310 2311 u8 reserved_at_80[0x10]; 2312 2313 u8 vl_15_dropped[0x10]; 2314 2315 u8 reserved_at_a0[0x80]; 2316 2317 u8 port_xmit_wait[0x20]; 2318 }; 2319 2320 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2321 u8 transmit_queue_high[0x20]; 2322 2323 u8 transmit_queue_low[0x20]; 2324 2325 u8 no_buffer_discard_uc_high[0x20]; 2326 2327 u8 no_buffer_discard_uc_low[0x20]; 2328 2329 u8 reserved_at_80[0x740]; 2330 }; 2331 2332 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2333 u8 wred_discard_high[0x20]; 2334 2335 u8 wred_discard_low[0x20]; 2336 2337 u8 ecn_marked_tc_high[0x20]; 2338 2339 u8 ecn_marked_tc_low[0x20]; 2340 2341 u8 reserved_at_80[0x740]; 2342 }; 2343 2344 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2345 u8 rx_octets_high[0x20]; 2346 2347 u8 rx_octets_low[0x20]; 2348 2349 u8 reserved_at_40[0xc0]; 2350 2351 u8 rx_frames_high[0x20]; 2352 2353 u8 rx_frames_low[0x20]; 2354 2355 u8 tx_octets_high[0x20]; 2356 2357 u8 tx_octets_low[0x20]; 2358 2359 u8 reserved_at_180[0xc0]; 2360 2361 u8 tx_frames_high[0x20]; 2362 2363 u8 tx_frames_low[0x20]; 2364 2365 u8 rx_pause_high[0x20]; 2366 2367 u8 rx_pause_low[0x20]; 2368 2369 u8 rx_pause_duration_high[0x20]; 2370 2371 u8 rx_pause_duration_low[0x20]; 2372 2373 u8 tx_pause_high[0x20]; 2374 2375 u8 tx_pause_low[0x20]; 2376 2377 u8 tx_pause_duration_high[0x20]; 2378 2379 u8 tx_pause_duration_low[0x20]; 2380 2381 u8 rx_pause_transition_high[0x20]; 2382 2383 u8 rx_pause_transition_low[0x20]; 2384 2385 u8 rx_discards_high[0x20]; 2386 2387 u8 rx_discards_low[0x20]; 2388 2389 u8 device_stall_minor_watermark_cnt_high[0x20]; 2390 2391 u8 device_stall_minor_watermark_cnt_low[0x20]; 2392 2393 u8 device_stall_critical_watermark_cnt_high[0x20]; 2394 2395 u8 device_stall_critical_watermark_cnt_low[0x20]; 2396 2397 u8 reserved_at_480[0x340]; 2398 }; 2399 2400 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2401 u8 port_transmit_wait_high[0x20]; 2402 2403 u8 port_transmit_wait_low[0x20]; 2404 2405 u8 reserved_at_40[0x100]; 2406 2407 u8 rx_buffer_almost_full_high[0x20]; 2408 2409 u8 rx_buffer_almost_full_low[0x20]; 2410 2411 u8 rx_buffer_full_high[0x20]; 2412 2413 u8 rx_buffer_full_low[0x20]; 2414 2415 u8 rx_icrc_encapsulated_high[0x20]; 2416 2417 u8 rx_icrc_encapsulated_low[0x20]; 2418 2419 u8 reserved_at_200[0x5c0]; 2420 }; 2421 2422 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2423 u8 dot3stats_alignment_errors_high[0x20]; 2424 2425 u8 dot3stats_alignment_errors_low[0x20]; 2426 2427 u8 dot3stats_fcs_errors_high[0x20]; 2428 2429 u8 dot3stats_fcs_errors_low[0x20]; 2430 2431 u8 dot3stats_single_collision_frames_high[0x20]; 2432 2433 u8 dot3stats_single_collision_frames_low[0x20]; 2434 2435 u8 dot3stats_multiple_collision_frames_high[0x20]; 2436 2437 u8 dot3stats_multiple_collision_frames_low[0x20]; 2438 2439 u8 dot3stats_sqe_test_errors_high[0x20]; 2440 2441 u8 dot3stats_sqe_test_errors_low[0x20]; 2442 2443 u8 dot3stats_deferred_transmissions_high[0x20]; 2444 2445 u8 dot3stats_deferred_transmissions_low[0x20]; 2446 2447 u8 dot3stats_late_collisions_high[0x20]; 2448 2449 u8 dot3stats_late_collisions_low[0x20]; 2450 2451 u8 dot3stats_excessive_collisions_high[0x20]; 2452 2453 u8 dot3stats_excessive_collisions_low[0x20]; 2454 2455 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2456 2457 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2458 2459 u8 dot3stats_carrier_sense_errors_high[0x20]; 2460 2461 u8 dot3stats_carrier_sense_errors_low[0x20]; 2462 2463 u8 dot3stats_frame_too_longs_high[0x20]; 2464 2465 u8 dot3stats_frame_too_longs_low[0x20]; 2466 2467 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2468 2469 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2470 2471 u8 dot3stats_symbol_errors_high[0x20]; 2472 2473 u8 dot3stats_symbol_errors_low[0x20]; 2474 2475 u8 dot3control_in_unknown_opcodes_high[0x20]; 2476 2477 u8 dot3control_in_unknown_opcodes_low[0x20]; 2478 2479 u8 dot3in_pause_frames_high[0x20]; 2480 2481 u8 dot3in_pause_frames_low[0x20]; 2482 2483 u8 dot3out_pause_frames_high[0x20]; 2484 2485 u8 dot3out_pause_frames_low[0x20]; 2486 2487 u8 reserved_at_400[0x3c0]; 2488 }; 2489 2490 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2491 u8 ether_stats_drop_events_high[0x20]; 2492 2493 u8 ether_stats_drop_events_low[0x20]; 2494 2495 u8 ether_stats_octets_high[0x20]; 2496 2497 u8 ether_stats_octets_low[0x20]; 2498 2499 u8 ether_stats_pkts_high[0x20]; 2500 2501 u8 ether_stats_pkts_low[0x20]; 2502 2503 u8 ether_stats_broadcast_pkts_high[0x20]; 2504 2505 u8 ether_stats_broadcast_pkts_low[0x20]; 2506 2507 u8 ether_stats_multicast_pkts_high[0x20]; 2508 2509 u8 ether_stats_multicast_pkts_low[0x20]; 2510 2511 u8 ether_stats_crc_align_errors_high[0x20]; 2512 2513 u8 ether_stats_crc_align_errors_low[0x20]; 2514 2515 u8 ether_stats_undersize_pkts_high[0x20]; 2516 2517 u8 ether_stats_undersize_pkts_low[0x20]; 2518 2519 u8 ether_stats_oversize_pkts_high[0x20]; 2520 2521 u8 ether_stats_oversize_pkts_low[0x20]; 2522 2523 u8 ether_stats_fragments_high[0x20]; 2524 2525 u8 ether_stats_fragments_low[0x20]; 2526 2527 u8 ether_stats_jabbers_high[0x20]; 2528 2529 u8 ether_stats_jabbers_low[0x20]; 2530 2531 u8 ether_stats_collisions_high[0x20]; 2532 2533 u8 ether_stats_collisions_low[0x20]; 2534 2535 u8 ether_stats_pkts64octets_high[0x20]; 2536 2537 u8 ether_stats_pkts64octets_low[0x20]; 2538 2539 u8 ether_stats_pkts65to127octets_high[0x20]; 2540 2541 u8 ether_stats_pkts65to127octets_low[0x20]; 2542 2543 u8 ether_stats_pkts128to255octets_high[0x20]; 2544 2545 u8 ether_stats_pkts128to255octets_low[0x20]; 2546 2547 u8 ether_stats_pkts256to511octets_high[0x20]; 2548 2549 u8 ether_stats_pkts256to511octets_low[0x20]; 2550 2551 u8 ether_stats_pkts512to1023octets_high[0x20]; 2552 2553 u8 ether_stats_pkts512to1023octets_low[0x20]; 2554 2555 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2556 2557 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2558 2559 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2560 2561 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2562 2563 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2564 2565 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2566 2567 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2568 2569 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2570 2571 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2572 2573 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2574 2575 u8 reserved_at_540[0x280]; 2576 }; 2577 2578 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2579 u8 if_in_octets_high[0x20]; 2580 2581 u8 if_in_octets_low[0x20]; 2582 2583 u8 if_in_ucast_pkts_high[0x20]; 2584 2585 u8 if_in_ucast_pkts_low[0x20]; 2586 2587 u8 if_in_discards_high[0x20]; 2588 2589 u8 if_in_discards_low[0x20]; 2590 2591 u8 if_in_errors_high[0x20]; 2592 2593 u8 if_in_errors_low[0x20]; 2594 2595 u8 if_in_unknown_protos_high[0x20]; 2596 2597 u8 if_in_unknown_protos_low[0x20]; 2598 2599 u8 if_out_octets_high[0x20]; 2600 2601 u8 if_out_octets_low[0x20]; 2602 2603 u8 if_out_ucast_pkts_high[0x20]; 2604 2605 u8 if_out_ucast_pkts_low[0x20]; 2606 2607 u8 if_out_discards_high[0x20]; 2608 2609 u8 if_out_discards_low[0x20]; 2610 2611 u8 if_out_errors_high[0x20]; 2612 2613 u8 if_out_errors_low[0x20]; 2614 2615 u8 if_in_multicast_pkts_high[0x20]; 2616 2617 u8 if_in_multicast_pkts_low[0x20]; 2618 2619 u8 if_in_broadcast_pkts_high[0x20]; 2620 2621 u8 if_in_broadcast_pkts_low[0x20]; 2622 2623 u8 if_out_multicast_pkts_high[0x20]; 2624 2625 u8 if_out_multicast_pkts_low[0x20]; 2626 2627 u8 if_out_broadcast_pkts_high[0x20]; 2628 2629 u8 if_out_broadcast_pkts_low[0x20]; 2630 2631 u8 reserved_at_340[0x480]; 2632 }; 2633 2634 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2635 u8 a_frames_transmitted_ok_high[0x20]; 2636 2637 u8 a_frames_transmitted_ok_low[0x20]; 2638 2639 u8 a_frames_received_ok_high[0x20]; 2640 2641 u8 a_frames_received_ok_low[0x20]; 2642 2643 u8 a_frame_check_sequence_errors_high[0x20]; 2644 2645 u8 a_frame_check_sequence_errors_low[0x20]; 2646 2647 u8 a_alignment_errors_high[0x20]; 2648 2649 u8 a_alignment_errors_low[0x20]; 2650 2651 u8 a_octets_transmitted_ok_high[0x20]; 2652 2653 u8 a_octets_transmitted_ok_low[0x20]; 2654 2655 u8 a_octets_received_ok_high[0x20]; 2656 2657 u8 a_octets_received_ok_low[0x20]; 2658 2659 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2660 2661 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2662 2663 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2664 2665 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2666 2667 u8 a_multicast_frames_received_ok_high[0x20]; 2668 2669 u8 a_multicast_frames_received_ok_low[0x20]; 2670 2671 u8 a_broadcast_frames_received_ok_high[0x20]; 2672 2673 u8 a_broadcast_frames_received_ok_low[0x20]; 2674 2675 u8 a_in_range_length_errors_high[0x20]; 2676 2677 u8 a_in_range_length_errors_low[0x20]; 2678 2679 u8 a_out_of_range_length_field_high[0x20]; 2680 2681 u8 a_out_of_range_length_field_low[0x20]; 2682 2683 u8 a_frame_too_long_errors_high[0x20]; 2684 2685 u8 a_frame_too_long_errors_low[0x20]; 2686 2687 u8 a_symbol_error_during_carrier_high[0x20]; 2688 2689 u8 a_symbol_error_during_carrier_low[0x20]; 2690 2691 u8 a_mac_control_frames_transmitted_high[0x20]; 2692 2693 u8 a_mac_control_frames_transmitted_low[0x20]; 2694 2695 u8 a_mac_control_frames_received_high[0x20]; 2696 2697 u8 a_mac_control_frames_received_low[0x20]; 2698 2699 u8 a_unsupported_opcodes_received_high[0x20]; 2700 2701 u8 a_unsupported_opcodes_received_low[0x20]; 2702 2703 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2704 2705 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2706 2707 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2708 2709 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2710 2711 u8 reserved_at_4c0[0x300]; 2712 }; 2713 2714 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2715 u8 life_time_counter_high[0x20]; 2716 2717 u8 life_time_counter_low[0x20]; 2718 2719 u8 rx_errors[0x20]; 2720 2721 u8 tx_errors[0x20]; 2722 2723 u8 l0_to_recovery_eieos[0x20]; 2724 2725 u8 l0_to_recovery_ts[0x20]; 2726 2727 u8 l0_to_recovery_framing[0x20]; 2728 2729 u8 l0_to_recovery_retrain[0x20]; 2730 2731 u8 crc_error_dllp[0x20]; 2732 2733 u8 crc_error_tlp[0x20]; 2734 2735 u8 tx_overflow_buffer_pkt_high[0x20]; 2736 2737 u8 tx_overflow_buffer_pkt_low[0x20]; 2738 2739 u8 outbound_stalled_reads[0x20]; 2740 2741 u8 outbound_stalled_writes[0x20]; 2742 2743 u8 outbound_stalled_reads_events[0x20]; 2744 2745 u8 outbound_stalled_writes_events[0x20]; 2746 2747 u8 reserved_at_200[0x5c0]; 2748 }; 2749 2750 struct mlx5_ifc_cmd_inter_comp_event_bits { 2751 u8 command_completion_vector[0x20]; 2752 2753 u8 reserved_at_20[0xc0]; 2754 }; 2755 2756 struct mlx5_ifc_stall_vl_event_bits { 2757 u8 reserved_at_0[0x18]; 2758 u8 port_num[0x1]; 2759 u8 reserved_at_19[0x3]; 2760 u8 vl[0x4]; 2761 2762 u8 reserved_at_20[0xa0]; 2763 }; 2764 2765 struct mlx5_ifc_db_bf_congestion_event_bits { 2766 u8 event_subtype[0x8]; 2767 u8 reserved_at_8[0x8]; 2768 u8 congestion_level[0x8]; 2769 u8 reserved_at_18[0x8]; 2770 2771 u8 reserved_at_20[0xa0]; 2772 }; 2773 2774 struct mlx5_ifc_gpio_event_bits { 2775 u8 reserved_at_0[0x60]; 2776 2777 u8 gpio_event_hi[0x20]; 2778 2779 u8 gpio_event_lo[0x20]; 2780 2781 u8 reserved_at_a0[0x40]; 2782 }; 2783 2784 struct mlx5_ifc_port_state_change_event_bits { 2785 u8 reserved_at_0[0x40]; 2786 2787 u8 port_num[0x4]; 2788 u8 reserved_at_44[0x1c]; 2789 2790 u8 reserved_at_60[0x80]; 2791 }; 2792 2793 struct mlx5_ifc_dropped_packet_logged_bits { 2794 u8 reserved_at_0[0xe0]; 2795 }; 2796 2797 enum { 2798 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2799 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2800 }; 2801 2802 struct mlx5_ifc_cq_error_bits { 2803 u8 reserved_at_0[0x8]; 2804 u8 cqn[0x18]; 2805 2806 u8 reserved_at_20[0x20]; 2807 2808 u8 reserved_at_40[0x18]; 2809 u8 syndrome[0x8]; 2810 2811 u8 reserved_at_60[0x80]; 2812 }; 2813 2814 struct mlx5_ifc_rdma_page_fault_event_bits { 2815 u8 bytes_committed[0x20]; 2816 2817 u8 r_key[0x20]; 2818 2819 u8 reserved_at_40[0x10]; 2820 u8 packet_len[0x10]; 2821 2822 u8 rdma_op_len[0x20]; 2823 2824 u8 rdma_va[0x40]; 2825 2826 u8 reserved_at_c0[0x5]; 2827 u8 rdma[0x1]; 2828 u8 write[0x1]; 2829 u8 requestor[0x1]; 2830 u8 qp_number[0x18]; 2831 }; 2832 2833 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2834 u8 bytes_committed[0x20]; 2835 2836 u8 reserved_at_20[0x10]; 2837 u8 wqe_index[0x10]; 2838 2839 u8 reserved_at_40[0x10]; 2840 u8 len[0x10]; 2841 2842 u8 reserved_at_60[0x60]; 2843 2844 u8 reserved_at_c0[0x5]; 2845 u8 rdma[0x1]; 2846 u8 write_read[0x1]; 2847 u8 requestor[0x1]; 2848 u8 qpn[0x18]; 2849 }; 2850 2851 struct mlx5_ifc_qp_events_bits { 2852 u8 reserved_at_0[0xa0]; 2853 2854 u8 type[0x8]; 2855 u8 reserved_at_a8[0x18]; 2856 2857 u8 reserved_at_c0[0x8]; 2858 u8 qpn_rqn_sqn[0x18]; 2859 }; 2860 2861 struct mlx5_ifc_dct_events_bits { 2862 u8 reserved_at_0[0xc0]; 2863 2864 u8 reserved_at_c0[0x8]; 2865 u8 dct_number[0x18]; 2866 }; 2867 2868 struct mlx5_ifc_comp_event_bits { 2869 u8 reserved_at_0[0xc0]; 2870 2871 u8 reserved_at_c0[0x8]; 2872 u8 cq_number[0x18]; 2873 }; 2874 2875 enum { 2876 MLX5_QPC_STATE_RST = 0x0, 2877 MLX5_QPC_STATE_INIT = 0x1, 2878 MLX5_QPC_STATE_RTR = 0x2, 2879 MLX5_QPC_STATE_RTS = 0x3, 2880 MLX5_QPC_STATE_SQER = 0x4, 2881 MLX5_QPC_STATE_ERR = 0x6, 2882 MLX5_QPC_STATE_SQD = 0x7, 2883 MLX5_QPC_STATE_SUSPENDED = 0x9, 2884 }; 2885 2886 enum { 2887 MLX5_QPC_ST_RC = 0x0, 2888 MLX5_QPC_ST_UC = 0x1, 2889 MLX5_QPC_ST_UD = 0x2, 2890 MLX5_QPC_ST_XRC = 0x3, 2891 MLX5_QPC_ST_DCI = 0x5, 2892 MLX5_QPC_ST_QP0 = 0x7, 2893 MLX5_QPC_ST_QP1 = 0x8, 2894 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2895 MLX5_QPC_ST_REG_UMR = 0xc, 2896 }; 2897 2898 enum { 2899 MLX5_QPC_PM_STATE_ARMED = 0x0, 2900 MLX5_QPC_PM_STATE_REARM = 0x1, 2901 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2902 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2903 }; 2904 2905 enum { 2906 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2907 }; 2908 2909 enum { 2910 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2911 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2912 }; 2913 2914 enum { 2915 MLX5_QPC_MTU_256_BYTES = 0x1, 2916 MLX5_QPC_MTU_512_BYTES = 0x2, 2917 MLX5_QPC_MTU_1K_BYTES = 0x3, 2918 MLX5_QPC_MTU_2K_BYTES = 0x4, 2919 MLX5_QPC_MTU_4K_BYTES = 0x5, 2920 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2921 }; 2922 2923 enum { 2924 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2925 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2926 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2927 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2928 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2929 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2930 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2931 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2932 }; 2933 2934 enum { 2935 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2936 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2937 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2938 }; 2939 2940 enum { 2941 MLX5_QPC_CS_RES_DISABLE = 0x0, 2942 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2943 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2944 }; 2945 2946 enum { 2947 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2948 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2949 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2950 }; 2951 2952 struct mlx5_ifc_qpc_bits { 2953 u8 state[0x4]; 2954 u8 lag_tx_port_affinity[0x4]; 2955 u8 st[0x8]; 2956 u8 reserved_at_10[0x2]; 2957 u8 isolate_vl_tc[0x1]; 2958 u8 pm_state[0x2]; 2959 u8 reserved_at_15[0x1]; 2960 u8 req_e2e_credit_mode[0x2]; 2961 u8 offload_type[0x4]; 2962 u8 end_padding_mode[0x2]; 2963 u8 reserved_at_1e[0x2]; 2964 2965 u8 wq_signature[0x1]; 2966 u8 block_lb_mc[0x1]; 2967 u8 atomic_like_write_en[0x1]; 2968 u8 latency_sensitive[0x1]; 2969 u8 reserved_at_24[0x1]; 2970 u8 drain_sigerr[0x1]; 2971 u8 reserved_at_26[0x2]; 2972 u8 pd[0x18]; 2973 2974 u8 mtu[0x3]; 2975 u8 log_msg_max[0x5]; 2976 u8 reserved_at_48[0x1]; 2977 u8 log_rq_size[0x4]; 2978 u8 log_rq_stride[0x3]; 2979 u8 no_sq[0x1]; 2980 u8 log_sq_size[0x4]; 2981 u8 reserved_at_55[0x3]; 2982 u8 ts_format[0x2]; 2983 u8 reserved_at_5a[0x1]; 2984 u8 rlky[0x1]; 2985 u8 ulp_stateless_offload_mode[0x4]; 2986 2987 u8 counter_set_id[0x8]; 2988 u8 uar_page[0x18]; 2989 2990 u8 reserved_at_80[0x8]; 2991 u8 user_index[0x18]; 2992 2993 u8 reserved_at_a0[0x3]; 2994 u8 log_page_size[0x5]; 2995 u8 remote_qpn[0x18]; 2996 2997 struct mlx5_ifc_ads_bits primary_address_path; 2998 2999 struct mlx5_ifc_ads_bits secondary_address_path; 3000 3001 u8 log_ack_req_freq[0x4]; 3002 u8 reserved_at_384[0x4]; 3003 u8 log_sra_max[0x3]; 3004 u8 reserved_at_38b[0x2]; 3005 u8 retry_count[0x3]; 3006 u8 rnr_retry[0x3]; 3007 u8 reserved_at_393[0x1]; 3008 u8 fre[0x1]; 3009 u8 cur_rnr_retry[0x3]; 3010 u8 cur_retry_count[0x3]; 3011 u8 reserved_at_39b[0x5]; 3012 3013 u8 reserved_at_3a0[0x20]; 3014 3015 u8 reserved_at_3c0[0x8]; 3016 u8 next_send_psn[0x18]; 3017 3018 u8 reserved_at_3e0[0x8]; 3019 u8 cqn_snd[0x18]; 3020 3021 u8 reserved_at_400[0x8]; 3022 u8 deth_sqpn[0x18]; 3023 3024 u8 reserved_at_420[0x20]; 3025 3026 u8 reserved_at_440[0x8]; 3027 u8 last_acked_psn[0x18]; 3028 3029 u8 reserved_at_460[0x8]; 3030 u8 ssn[0x18]; 3031 3032 u8 reserved_at_480[0x8]; 3033 u8 log_rra_max[0x3]; 3034 u8 reserved_at_48b[0x1]; 3035 u8 atomic_mode[0x4]; 3036 u8 rre[0x1]; 3037 u8 rwe[0x1]; 3038 u8 rae[0x1]; 3039 u8 reserved_at_493[0x1]; 3040 u8 page_offset[0x6]; 3041 u8 reserved_at_49a[0x3]; 3042 u8 cd_slave_receive[0x1]; 3043 u8 cd_slave_send[0x1]; 3044 u8 cd_master[0x1]; 3045 3046 u8 reserved_at_4a0[0x3]; 3047 u8 min_rnr_nak[0x5]; 3048 u8 next_rcv_psn[0x18]; 3049 3050 u8 reserved_at_4c0[0x8]; 3051 u8 xrcd[0x18]; 3052 3053 u8 reserved_at_4e0[0x8]; 3054 u8 cqn_rcv[0x18]; 3055 3056 u8 dbr_addr[0x40]; 3057 3058 u8 q_key[0x20]; 3059 3060 u8 reserved_at_560[0x5]; 3061 u8 rq_type[0x3]; 3062 u8 srqn_rmpn_xrqn[0x18]; 3063 3064 u8 reserved_at_580[0x8]; 3065 u8 rmsn[0x18]; 3066 3067 u8 hw_sq_wqebb_counter[0x10]; 3068 u8 sw_sq_wqebb_counter[0x10]; 3069 3070 u8 hw_rq_counter[0x20]; 3071 3072 u8 sw_rq_counter[0x20]; 3073 3074 u8 reserved_at_600[0x20]; 3075 3076 u8 reserved_at_620[0xf]; 3077 u8 cgs[0x1]; 3078 u8 cs_req[0x8]; 3079 u8 cs_res[0x8]; 3080 3081 u8 dc_access_key[0x40]; 3082 3083 u8 reserved_at_680[0x3]; 3084 u8 dbr_umem_valid[0x1]; 3085 3086 u8 reserved_at_684[0xbc]; 3087 }; 3088 3089 struct mlx5_ifc_roce_addr_layout_bits { 3090 u8 source_l3_address[16][0x8]; 3091 3092 u8 reserved_at_80[0x3]; 3093 u8 vlan_valid[0x1]; 3094 u8 vlan_id[0xc]; 3095 u8 source_mac_47_32[0x10]; 3096 3097 u8 source_mac_31_0[0x20]; 3098 3099 u8 reserved_at_c0[0x14]; 3100 u8 roce_l3_type[0x4]; 3101 u8 roce_version[0x8]; 3102 3103 u8 reserved_at_e0[0x20]; 3104 }; 3105 3106 union mlx5_ifc_hca_cap_union_bits { 3107 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3108 struct mlx5_ifc_odp_cap_bits odp_cap; 3109 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3110 struct mlx5_ifc_roce_cap_bits roce_cap; 3111 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3112 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3113 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3114 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3115 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3116 struct mlx5_ifc_qos_cap_bits qos_cap; 3117 struct mlx5_ifc_debug_cap_bits debug_cap; 3118 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3119 struct mlx5_ifc_tls_cap_bits tls_cap; 3120 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3121 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3122 u8 reserved_at_0[0x8000]; 3123 }; 3124 3125 enum { 3126 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3127 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3128 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3129 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3130 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3131 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3132 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3133 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3134 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3135 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3136 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3137 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3138 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3139 }; 3140 3141 enum { 3142 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3143 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3144 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3145 }; 3146 3147 struct mlx5_ifc_vlan_bits { 3148 u8 ethtype[0x10]; 3149 u8 prio[0x3]; 3150 u8 cfi[0x1]; 3151 u8 vid[0xc]; 3152 }; 3153 3154 struct mlx5_ifc_flow_context_bits { 3155 struct mlx5_ifc_vlan_bits push_vlan; 3156 3157 u8 group_id[0x20]; 3158 3159 u8 reserved_at_40[0x8]; 3160 u8 flow_tag[0x18]; 3161 3162 u8 reserved_at_60[0x10]; 3163 u8 action[0x10]; 3164 3165 u8 extended_destination[0x1]; 3166 u8 reserved_at_81[0x1]; 3167 u8 flow_source[0x2]; 3168 u8 reserved_at_84[0x4]; 3169 u8 destination_list_size[0x18]; 3170 3171 u8 reserved_at_a0[0x8]; 3172 u8 flow_counter_list_size[0x18]; 3173 3174 u8 packet_reformat_id[0x20]; 3175 3176 u8 modify_header_id[0x20]; 3177 3178 struct mlx5_ifc_vlan_bits push_vlan_2; 3179 3180 u8 ipsec_obj_id[0x20]; 3181 u8 reserved_at_140[0xc0]; 3182 3183 struct mlx5_ifc_fte_match_param_bits match_value; 3184 3185 u8 reserved_at_1200[0x600]; 3186 3187 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3188 }; 3189 3190 enum { 3191 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3192 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3193 }; 3194 3195 struct mlx5_ifc_xrc_srqc_bits { 3196 u8 state[0x4]; 3197 u8 log_xrc_srq_size[0x4]; 3198 u8 reserved_at_8[0x18]; 3199 3200 u8 wq_signature[0x1]; 3201 u8 cont_srq[0x1]; 3202 u8 reserved_at_22[0x1]; 3203 u8 rlky[0x1]; 3204 u8 basic_cyclic_rcv_wqe[0x1]; 3205 u8 log_rq_stride[0x3]; 3206 u8 xrcd[0x18]; 3207 3208 u8 page_offset[0x6]; 3209 u8 reserved_at_46[0x1]; 3210 u8 dbr_umem_valid[0x1]; 3211 u8 cqn[0x18]; 3212 3213 u8 reserved_at_60[0x20]; 3214 3215 u8 user_index_equal_xrc_srqn[0x1]; 3216 u8 reserved_at_81[0x1]; 3217 u8 log_page_size[0x6]; 3218 u8 user_index[0x18]; 3219 3220 u8 reserved_at_a0[0x20]; 3221 3222 u8 reserved_at_c0[0x8]; 3223 u8 pd[0x18]; 3224 3225 u8 lwm[0x10]; 3226 u8 wqe_cnt[0x10]; 3227 3228 u8 reserved_at_100[0x40]; 3229 3230 u8 db_record_addr_h[0x20]; 3231 3232 u8 db_record_addr_l[0x1e]; 3233 u8 reserved_at_17e[0x2]; 3234 3235 u8 reserved_at_180[0x80]; 3236 }; 3237 3238 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3239 u8 counter_error_queues[0x20]; 3240 3241 u8 total_error_queues[0x20]; 3242 3243 u8 send_queue_priority_update_flow[0x20]; 3244 3245 u8 reserved_at_60[0x20]; 3246 3247 u8 nic_receive_steering_discard[0x40]; 3248 3249 u8 receive_discard_vport_down[0x40]; 3250 3251 u8 transmit_discard_vport_down[0x40]; 3252 3253 u8 reserved_at_140[0xa0]; 3254 3255 u8 internal_rq_out_of_buffer[0x20]; 3256 3257 u8 reserved_at_200[0xe00]; 3258 }; 3259 3260 struct mlx5_ifc_traffic_counter_bits { 3261 u8 packets[0x40]; 3262 3263 u8 octets[0x40]; 3264 }; 3265 3266 struct mlx5_ifc_tisc_bits { 3267 u8 strict_lag_tx_port_affinity[0x1]; 3268 u8 tls_en[0x1]; 3269 u8 reserved_at_2[0x2]; 3270 u8 lag_tx_port_affinity[0x04]; 3271 3272 u8 reserved_at_8[0x4]; 3273 u8 prio[0x4]; 3274 u8 reserved_at_10[0x10]; 3275 3276 u8 reserved_at_20[0x100]; 3277 3278 u8 reserved_at_120[0x8]; 3279 u8 transport_domain[0x18]; 3280 3281 u8 reserved_at_140[0x8]; 3282 u8 underlay_qpn[0x18]; 3283 3284 u8 reserved_at_160[0x8]; 3285 u8 pd[0x18]; 3286 3287 u8 reserved_at_180[0x380]; 3288 }; 3289 3290 enum { 3291 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3292 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3293 }; 3294 3295 enum { 3296 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3297 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3298 }; 3299 3300 enum { 3301 MLX5_RX_HASH_FN_NONE = 0x0, 3302 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3303 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3304 }; 3305 3306 enum { 3307 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3308 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3309 }; 3310 3311 struct mlx5_ifc_tirc_bits { 3312 u8 reserved_at_0[0x20]; 3313 3314 u8 disp_type[0x4]; 3315 u8 tls_en[0x1]; 3316 u8 reserved_at_25[0x1b]; 3317 3318 u8 reserved_at_40[0x40]; 3319 3320 u8 reserved_at_80[0x4]; 3321 u8 lro_timeout_period_usecs[0x10]; 3322 u8 lro_enable_mask[0x4]; 3323 u8 lro_max_ip_payload_size[0x8]; 3324 3325 u8 reserved_at_a0[0x40]; 3326 3327 u8 reserved_at_e0[0x8]; 3328 u8 inline_rqn[0x18]; 3329 3330 u8 rx_hash_symmetric[0x1]; 3331 u8 reserved_at_101[0x1]; 3332 u8 tunneled_offload_en[0x1]; 3333 u8 reserved_at_103[0x5]; 3334 u8 indirect_table[0x18]; 3335 3336 u8 rx_hash_fn[0x4]; 3337 u8 reserved_at_124[0x2]; 3338 u8 self_lb_block[0x2]; 3339 u8 transport_domain[0x18]; 3340 3341 u8 rx_hash_toeplitz_key[10][0x20]; 3342 3343 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3344 3345 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3346 3347 u8 reserved_at_2c0[0x4c0]; 3348 }; 3349 3350 enum { 3351 MLX5_SRQC_STATE_GOOD = 0x0, 3352 MLX5_SRQC_STATE_ERROR = 0x1, 3353 }; 3354 3355 struct mlx5_ifc_srqc_bits { 3356 u8 state[0x4]; 3357 u8 log_srq_size[0x4]; 3358 u8 reserved_at_8[0x18]; 3359 3360 u8 wq_signature[0x1]; 3361 u8 cont_srq[0x1]; 3362 u8 reserved_at_22[0x1]; 3363 u8 rlky[0x1]; 3364 u8 reserved_at_24[0x1]; 3365 u8 log_rq_stride[0x3]; 3366 u8 xrcd[0x18]; 3367 3368 u8 page_offset[0x6]; 3369 u8 reserved_at_46[0x2]; 3370 u8 cqn[0x18]; 3371 3372 u8 reserved_at_60[0x20]; 3373 3374 u8 reserved_at_80[0x2]; 3375 u8 log_page_size[0x6]; 3376 u8 reserved_at_88[0x18]; 3377 3378 u8 reserved_at_a0[0x20]; 3379 3380 u8 reserved_at_c0[0x8]; 3381 u8 pd[0x18]; 3382 3383 u8 lwm[0x10]; 3384 u8 wqe_cnt[0x10]; 3385 3386 u8 reserved_at_100[0x40]; 3387 3388 u8 dbr_addr[0x40]; 3389 3390 u8 reserved_at_180[0x80]; 3391 }; 3392 3393 enum { 3394 MLX5_SQC_STATE_RST = 0x0, 3395 MLX5_SQC_STATE_RDY = 0x1, 3396 MLX5_SQC_STATE_ERR = 0x3, 3397 }; 3398 3399 enum { 3400 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3401 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3402 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3403 }; 3404 3405 struct mlx5_ifc_sqc_bits { 3406 u8 rlky[0x1]; 3407 u8 cd_master[0x1]; 3408 u8 fre[0x1]; 3409 u8 flush_in_error_en[0x1]; 3410 u8 allow_multi_pkt_send_wqe[0x1]; 3411 u8 min_wqe_inline_mode[0x3]; 3412 u8 state[0x4]; 3413 u8 reg_umr[0x1]; 3414 u8 allow_swp[0x1]; 3415 u8 hairpin[0x1]; 3416 u8 reserved_at_f[0xb]; 3417 u8 ts_format[0x2]; 3418 u8 reserved_at_1c[0x4]; 3419 3420 u8 reserved_at_20[0x8]; 3421 u8 user_index[0x18]; 3422 3423 u8 reserved_at_40[0x8]; 3424 u8 cqn[0x18]; 3425 3426 u8 reserved_at_60[0x8]; 3427 u8 hairpin_peer_rq[0x18]; 3428 3429 u8 reserved_at_80[0x10]; 3430 u8 hairpin_peer_vhca[0x10]; 3431 3432 u8 reserved_at_a0[0x20]; 3433 3434 u8 reserved_at_c0[0x8]; 3435 u8 ts_cqe_to_dest_cqn[0x18]; 3436 3437 u8 reserved_at_e0[0x10]; 3438 u8 packet_pacing_rate_limit_index[0x10]; 3439 u8 tis_lst_sz[0x10]; 3440 u8 qos_queue_group_id[0x10]; 3441 3442 u8 reserved_at_120[0x40]; 3443 3444 u8 reserved_at_160[0x8]; 3445 u8 tis_num_0[0x18]; 3446 3447 struct mlx5_ifc_wq_bits wq; 3448 }; 3449 3450 enum { 3451 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3452 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3453 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3454 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3455 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3456 }; 3457 3458 enum { 3459 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3460 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3461 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3462 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3463 }; 3464 3465 struct mlx5_ifc_scheduling_context_bits { 3466 u8 element_type[0x8]; 3467 u8 reserved_at_8[0x18]; 3468 3469 u8 element_attributes[0x20]; 3470 3471 u8 parent_element_id[0x20]; 3472 3473 u8 reserved_at_60[0x40]; 3474 3475 u8 bw_share[0x20]; 3476 3477 u8 max_average_bw[0x20]; 3478 3479 u8 reserved_at_e0[0x120]; 3480 }; 3481 3482 struct mlx5_ifc_rqtc_bits { 3483 u8 reserved_at_0[0xa0]; 3484 3485 u8 reserved_at_a0[0x5]; 3486 u8 list_q_type[0x3]; 3487 u8 reserved_at_a8[0x8]; 3488 u8 rqt_max_size[0x10]; 3489 3490 u8 rq_vhca_id_format[0x1]; 3491 u8 reserved_at_c1[0xf]; 3492 u8 rqt_actual_size[0x10]; 3493 3494 u8 reserved_at_e0[0x6a0]; 3495 3496 struct mlx5_ifc_rq_num_bits rq_num[]; 3497 }; 3498 3499 enum { 3500 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3501 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3502 }; 3503 3504 enum { 3505 MLX5_RQC_STATE_RST = 0x0, 3506 MLX5_RQC_STATE_RDY = 0x1, 3507 MLX5_RQC_STATE_ERR = 0x3, 3508 }; 3509 3510 enum { 3511 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3512 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3513 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3514 }; 3515 3516 struct mlx5_ifc_rqc_bits { 3517 u8 rlky[0x1]; 3518 u8 delay_drop_en[0x1]; 3519 u8 scatter_fcs[0x1]; 3520 u8 vsd[0x1]; 3521 u8 mem_rq_type[0x4]; 3522 u8 state[0x4]; 3523 u8 reserved_at_c[0x1]; 3524 u8 flush_in_error_en[0x1]; 3525 u8 hairpin[0x1]; 3526 u8 reserved_at_f[0xb]; 3527 u8 ts_format[0x2]; 3528 u8 reserved_at_1c[0x4]; 3529 3530 u8 reserved_at_20[0x8]; 3531 u8 user_index[0x18]; 3532 3533 u8 reserved_at_40[0x8]; 3534 u8 cqn[0x18]; 3535 3536 u8 counter_set_id[0x8]; 3537 u8 reserved_at_68[0x18]; 3538 3539 u8 reserved_at_80[0x8]; 3540 u8 rmpn[0x18]; 3541 3542 u8 reserved_at_a0[0x8]; 3543 u8 hairpin_peer_sq[0x18]; 3544 3545 u8 reserved_at_c0[0x10]; 3546 u8 hairpin_peer_vhca[0x10]; 3547 3548 u8 reserved_at_e0[0xa0]; 3549 3550 struct mlx5_ifc_wq_bits wq; 3551 }; 3552 3553 enum { 3554 MLX5_RMPC_STATE_RDY = 0x1, 3555 MLX5_RMPC_STATE_ERR = 0x3, 3556 }; 3557 3558 struct mlx5_ifc_rmpc_bits { 3559 u8 reserved_at_0[0x8]; 3560 u8 state[0x4]; 3561 u8 reserved_at_c[0x14]; 3562 3563 u8 basic_cyclic_rcv_wqe[0x1]; 3564 u8 reserved_at_21[0x1f]; 3565 3566 u8 reserved_at_40[0x140]; 3567 3568 struct mlx5_ifc_wq_bits wq; 3569 }; 3570 3571 struct mlx5_ifc_nic_vport_context_bits { 3572 u8 reserved_at_0[0x5]; 3573 u8 min_wqe_inline_mode[0x3]; 3574 u8 reserved_at_8[0x15]; 3575 u8 disable_mc_local_lb[0x1]; 3576 u8 disable_uc_local_lb[0x1]; 3577 u8 roce_en[0x1]; 3578 3579 u8 arm_change_event[0x1]; 3580 u8 reserved_at_21[0x1a]; 3581 u8 event_on_mtu[0x1]; 3582 u8 event_on_promisc_change[0x1]; 3583 u8 event_on_vlan_change[0x1]; 3584 u8 event_on_mc_address_change[0x1]; 3585 u8 event_on_uc_address_change[0x1]; 3586 3587 u8 reserved_at_40[0xc]; 3588 3589 u8 affiliation_criteria[0x4]; 3590 u8 affiliated_vhca_id[0x10]; 3591 3592 u8 reserved_at_60[0xd0]; 3593 3594 u8 mtu[0x10]; 3595 3596 u8 system_image_guid[0x40]; 3597 u8 port_guid[0x40]; 3598 u8 node_guid[0x40]; 3599 3600 u8 reserved_at_200[0x140]; 3601 u8 qkey_violation_counter[0x10]; 3602 u8 reserved_at_350[0x430]; 3603 3604 u8 promisc_uc[0x1]; 3605 u8 promisc_mc[0x1]; 3606 u8 promisc_all[0x1]; 3607 u8 reserved_at_783[0x2]; 3608 u8 allowed_list_type[0x3]; 3609 u8 reserved_at_788[0xc]; 3610 u8 allowed_list_size[0xc]; 3611 3612 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3613 3614 u8 reserved_at_7e0[0x20]; 3615 3616 u8 current_uc_mac_address[][0x40]; 3617 }; 3618 3619 enum { 3620 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3621 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3622 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3623 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3624 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3625 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3626 }; 3627 3628 struct mlx5_ifc_mkc_bits { 3629 u8 reserved_at_0[0x1]; 3630 u8 free[0x1]; 3631 u8 reserved_at_2[0x1]; 3632 u8 access_mode_4_2[0x3]; 3633 u8 reserved_at_6[0x7]; 3634 u8 relaxed_ordering_write[0x1]; 3635 u8 reserved_at_e[0x1]; 3636 u8 small_fence_on_rdma_read_response[0x1]; 3637 u8 umr_en[0x1]; 3638 u8 a[0x1]; 3639 u8 rw[0x1]; 3640 u8 rr[0x1]; 3641 u8 lw[0x1]; 3642 u8 lr[0x1]; 3643 u8 access_mode_1_0[0x2]; 3644 u8 reserved_at_18[0x8]; 3645 3646 u8 qpn[0x18]; 3647 u8 mkey_7_0[0x8]; 3648 3649 u8 reserved_at_40[0x20]; 3650 3651 u8 length64[0x1]; 3652 u8 bsf_en[0x1]; 3653 u8 sync_umr[0x1]; 3654 u8 reserved_at_63[0x2]; 3655 u8 expected_sigerr_count[0x1]; 3656 u8 reserved_at_66[0x1]; 3657 u8 en_rinval[0x1]; 3658 u8 pd[0x18]; 3659 3660 u8 start_addr[0x40]; 3661 3662 u8 len[0x40]; 3663 3664 u8 bsf_octword_size[0x20]; 3665 3666 u8 reserved_at_120[0x80]; 3667 3668 u8 translations_octword_size[0x20]; 3669 3670 u8 reserved_at_1c0[0x19]; 3671 u8 relaxed_ordering_read[0x1]; 3672 u8 reserved_at_1d9[0x1]; 3673 u8 log_page_size[0x5]; 3674 3675 u8 reserved_at_1e0[0x20]; 3676 }; 3677 3678 struct mlx5_ifc_pkey_bits { 3679 u8 reserved_at_0[0x10]; 3680 u8 pkey[0x10]; 3681 }; 3682 3683 struct mlx5_ifc_array128_auto_bits { 3684 u8 array128_auto[16][0x8]; 3685 }; 3686 3687 struct mlx5_ifc_hca_vport_context_bits { 3688 u8 field_select[0x20]; 3689 3690 u8 reserved_at_20[0xe0]; 3691 3692 u8 sm_virt_aware[0x1]; 3693 u8 has_smi[0x1]; 3694 u8 has_raw[0x1]; 3695 u8 grh_required[0x1]; 3696 u8 reserved_at_104[0xc]; 3697 u8 port_physical_state[0x4]; 3698 u8 vport_state_policy[0x4]; 3699 u8 port_state[0x4]; 3700 u8 vport_state[0x4]; 3701 3702 u8 reserved_at_120[0x20]; 3703 3704 u8 system_image_guid[0x40]; 3705 3706 u8 port_guid[0x40]; 3707 3708 u8 node_guid[0x40]; 3709 3710 u8 cap_mask1[0x20]; 3711 3712 u8 cap_mask1_field_select[0x20]; 3713 3714 u8 cap_mask2[0x20]; 3715 3716 u8 cap_mask2_field_select[0x20]; 3717 3718 u8 reserved_at_280[0x80]; 3719 3720 u8 lid[0x10]; 3721 u8 reserved_at_310[0x4]; 3722 u8 init_type_reply[0x4]; 3723 u8 lmc[0x3]; 3724 u8 subnet_timeout[0x5]; 3725 3726 u8 sm_lid[0x10]; 3727 u8 sm_sl[0x4]; 3728 u8 reserved_at_334[0xc]; 3729 3730 u8 qkey_violation_counter[0x10]; 3731 u8 pkey_violation_counter[0x10]; 3732 3733 u8 reserved_at_360[0xca0]; 3734 }; 3735 3736 struct mlx5_ifc_esw_vport_context_bits { 3737 u8 fdb_to_vport_reg_c[0x1]; 3738 u8 reserved_at_1[0x2]; 3739 u8 vport_svlan_strip[0x1]; 3740 u8 vport_cvlan_strip[0x1]; 3741 u8 vport_svlan_insert[0x1]; 3742 u8 vport_cvlan_insert[0x2]; 3743 u8 fdb_to_vport_reg_c_id[0x8]; 3744 u8 reserved_at_10[0x10]; 3745 3746 u8 reserved_at_20[0x20]; 3747 3748 u8 svlan_cfi[0x1]; 3749 u8 svlan_pcp[0x3]; 3750 u8 svlan_id[0xc]; 3751 u8 cvlan_cfi[0x1]; 3752 u8 cvlan_pcp[0x3]; 3753 u8 cvlan_id[0xc]; 3754 3755 u8 reserved_at_60[0x720]; 3756 3757 u8 sw_steering_vport_icm_address_rx[0x40]; 3758 3759 u8 sw_steering_vport_icm_address_tx[0x40]; 3760 }; 3761 3762 enum { 3763 MLX5_EQC_STATUS_OK = 0x0, 3764 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3765 }; 3766 3767 enum { 3768 MLX5_EQC_ST_ARMED = 0x9, 3769 MLX5_EQC_ST_FIRED = 0xa, 3770 }; 3771 3772 struct mlx5_ifc_eqc_bits { 3773 u8 status[0x4]; 3774 u8 reserved_at_4[0x9]; 3775 u8 ec[0x1]; 3776 u8 oi[0x1]; 3777 u8 reserved_at_f[0x5]; 3778 u8 st[0x4]; 3779 u8 reserved_at_18[0x8]; 3780 3781 u8 reserved_at_20[0x20]; 3782 3783 u8 reserved_at_40[0x14]; 3784 u8 page_offset[0x6]; 3785 u8 reserved_at_5a[0x6]; 3786 3787 u8 reserved_at_60[0x3]; 3788 u8 log_eq_size[0x5]; 3789 u8 uar_page[0x18]; 3790 3791 u8 reserved_at_80[0x20]; 3792 3793 u8 reserved_at_a0[0x18]; 3794 u8 intr[0x8]; 3795 3796 u8 reserved_at_c0[0x3]; 3797 u8 log_page_size[0x5]; 3798 u8 reserved_at_c8[0x18]; 3799 3800 u8 reserved_at_e0[0x60]; 3801 3802 u8 reserved_at_140[0x8]; 3803 u8 consumer_counter[0x18]; 3804 3805 u8 reserved_at_160[0x8]; 3806 u8 producer_counter[0x18]; 3807 3808 u8 reserved_at_180[0x80]; 3809 }; 3810 3811 enum { 3812 MLX5_DCTC_STATE_ACTIVE = 0x0, 3813 MLX5_DCTC_STATE_DRAINING = 0x1, 3814 MLX5_DCTC_STATE_DRAINED = 0x2, 3815 }; 3816 3817 enum { 3818 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3819 MLX5_DCTC_CS_RES_NA = 0x1, 3820 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3821 }; 3822 3823 enum { 3824 MLX5_DCTC_MTU_256_BYTES = 0x1, 3825 MLX5_DCTC_MTU_512_BYTES = 0x2, 3826 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3827 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3828 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3829 }; 3830 3831 struct mlx5_ifc_dctc_bits { 3832 u8 reserved_at_0[0x4]; 3833 u8 state[0x4]; 3834 u8 reserved_at_8[0x18]; 3835 3836 u8 reserved_at_20[0x8]; 3837 u8 user_index[0x18]; 3838 3839 u8 reserved_at_40[0x8]; 3840 u8 cqn[0x18]; 3841 3842 u8 counter_set_id[0x8]; 3843 u8 atomic_mode[0x4]; 3844 u8 rre[0x1]; 3845 u8 rwe[0x1]; 3846 u8 rae[0x1]; 3847 u8 atomic_like_write_en[0x1]; 3848 u8 latency_sensitive[0x1]; 3849 u8 rlky[0x1]; 3850 u8 free_ar[0x1]; 3851 u8 reserved_at_73[0xd]; 3852 3853 u8 reserved_at_80[0x8]; 3854 u8 cs_res[0x8]; 3855 u8 reserved_at_90[0x3]; 3856 u8 min_rnr_nak[0x5]; 3857 u8 reserved_at_98[0x8]; 3858 3859 u8 reserved_at_a0[0x8]; 3860 u8 srqn_xrqn[0x18]; 3861 3862 u8 reserved_at_c0[0x8]; 3863 u8 pd[0x18]; 3864 3865 u8 tclass[0x8]; 3866 u8 reserved_at_e8[0x4]; 3867 u8 flow_label[0x14]; 3868 3869 u8 dc_access_key[0x40]; 3870 3871 u8 reserved_at_140[0x5]; 3872 u8 mtu[0x3]; 3873 u8 port[0x8]; 3874 u8 pkey_index[0x10]; 3875 3876 u8 reserved_at_160[0x8]; 3877 u8 my_addr_index[0x8]; 3878 u8 reserved_at_170[0x8]; 3879 u8 hop_limit[0x8]; 3880 3881 u8 dc_access_key_violation_count[0x20]; 3882 3883 u8 reserved_at_1a0[0x14]; 3884 u8 dei_cfi[0x1]; 3885 u8 eth_prio[0x3]; 3886 u8 ecn[0x2]; 3887 u8 dscp[0x6]; 3888 3889 u8 reserved_at_1c0[0x20]; 3890 u8 ece[0x20]; 3891 }; 3892 3893 enum { 3894 MLX5_CQC_STATUS_OK = 0x0, 3895 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3896 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3897 }; 3898 3899 enum { 3900 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3901 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3902 }; 3903 3904 enum { 3905 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3906 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3907 MLX5_CQC_ST_FIRED = 0xa, 3908 }; 3909 3910 enum { 3911 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3912 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3913 MLX5_CQ_PERIOD_NUM_MODES 3914 }; 3915 3916 struct mlx5_ifc_cqc_bits { 3917 u8 status[0x4]; 3918 u8 reserved_at_4[0x2]; 3919 u8 dbr_umem_valid[0x1]; 3920 u8 apu_thread_cq[0x1]; 3921 u8 cqe_sz[0x3]; 3922 u8 cc[0x1]; 3923 u8 reserved_at_c[0x1]; 3924 u8 scqe_break_moderation_en[0x1]; 3925 u8 oi[0x1]; 3926 u8 cq_period_mode[0x2]; 3927 u8 cqe_comp_en[0x1]; 3928 u8 mini_cqe_res_format[0x2]; 3929 u8 st[0x4]; 3930 u8 reserved_at_18[0x8]; 3931 3932 u8 reserved_at_20[0x20]; 3933 3934 u8 reserved_at_40[0x14]; 3935 u8 page_offset[0x6]; 3936 u8 reserved_at_5a[0x6]; 3937 3938 u8 reserved_at_60[0x3]; 3939 u8 log_cq_size[0x5]; 3940 u8 uar_page[0x18]; 3941 3942 u8 reserved_at_80[0x4]; 3943 u8 cq_period[0xc]; 3944 u8 cq_max_count[0x10]; 3945 3946 u8 reserved_at_a0[0x18]; 3947 u8 c_eqn[0x8]; 3948 3949 u8 reserved_at_c0[0x3]; 3950 u8 log_page_size[0x5]; 3951 u8 reserved_at_c8[0x18]; 3952 3953 u8 reserved_at_e0[0x20]; 3954 3955 u8 reserved_at_100[0x8]; 3956 u8 last_notified_index[0x18]; 3957 3958 u8 reserved_at_120[0x8]; 3959 u8 last_solicit_index[0x18]; 3960 3961 u8 reserved_at_140[0x8]; 3962 u8 consumer_counter[0x18]; 3963 3964 u8 reserved_at_160[0x8]; 3965 u8 producer_counter[0x18]; 3966 3967 u8 reserved_at_180[0x40]; 3968 3969 u8 dbr_addr[0x40]; 3970 }; 3971 3972 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3973 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3974 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3975 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3976 u8 reserved_at_0[0x800]; 3977 }; 3978 3979 struct mlx5_ifc_query_adapter_param_block_bits { 3980 u8 reserved_at_0[0xc0]; 3981 3982 u8 reserved_at_c0[0x8]; 3983 u8 ieee_vendor_id[0x18]; 3984 3985 u8 reserved_at_e0[0x10]; 3986 u8 vsd_vendor_id[0x10]; 3987 3988 u8 vsd[208][0x8]; 3989 3990 u8 vsd_contd_psid[16][0x8]; 3991 }; 3992 3993 enum { 3994 MLX5_XRQC_STATE_GOOD = 0x0, 3995 MLX5_XRQC_STATE_ERROR = 0x1, 3996 }; 3997 3998 enum { 3999 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4000 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4001 }; 4002 4003 enum { 4004 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4005 }; 4006 4007 struct mlx5_ifc_tag_matching_topology_context_bits { 4008 u8 log_matching_list_sz[0x4]; 4009 u8 reserved_at_4[0xc]; 4010 u8 append_next_index[0x10]; 4011 4012 u8 sw_phase_cnt[0x10]; 4013 u8 hw_phase_cnt[0x10]; 4014 4015 u8 reserved_at_40[0x40]; 4016 }; 4017 4018 struct mlx5_ifc_xrqc_bits { 4019 u8 state[0x4]; 4020 u8 rlkey[0x1]; 4021 u8 reserved_at_5[0xf]; 4022 u8 topology[0x4]; 4023 u8 reserved_at_18[0x4]; 4024 u8 offload[0x4]; 4025 4026 u8 reserved_at_20[0x8]; 4027 u8 user_index[0x18]; 4028 4029 u8 reserved_at_40[0x8]; 4030 u8 cqn[0x18]; 4031 4032 u8 reserved_at_60[0xa0]; 4033 4034 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4035 4036 u8 reserved_at_180[0x280]; 4037 4038 struct mlx5_ifc_wq_bits wq; 4039 }; 4040 4041 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4042 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4043 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4044 u8 reserved_at_0[0x20]; 4045 }; 4046 4047 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4048 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4049 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4050 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4051 u8 reserved_at_0[0x20]; 4052 }; 4053 4054 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4055 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4056 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4057 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4058 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4059 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4060 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4061 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4062 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4063 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4064 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4065 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4066 u8 reserved_at_0[0x7c0]; 4067 }; 4068 4069 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4070 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4071 u8 reserved_at_0[0x7c0]; 4072 }; 4073 4074 union mlx5_ifc_event_auto_bits { 4075 struct mlx5_ifc_comp_event_bits comp_event; 4076 struct mlx5_ifc_dct_events_bits dct_events; 4077 struct mlx5_ifc_qp_events_bits qp_events; 4078 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4079 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4080 struct mlx5_ifc_cq_error_bits cq_error; 4081 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4082 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4083 struct mlx5_ifc_gpio_event_bits gpio_event; 4084 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4085 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4086 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4087 u8 reserved_at_0[0xe0]; 4088 }; 4089 4090 struct mlx5_ifc_health_buffer_bits { 4091 u8 reserved_at_0[0x100]; 4092 4093 u8 assert_existptr[0x20]; 4094 4095 u8 assert_callra[0x20]; 4096 4097 u8 reserved_at_140[0x40]; 4098 4099 u8 fw_version[0x20]; 4100 4101 u8 hw_id[0x20]; 4102 4103 u8 reserved_at_1c0[0x20]; 4104 4105 u8 irisc_index[0x8]; 4106 u8 synd[0x8]; 4107 u8 ext_synd[0x10]; 4108 }; 4109 4110 struct mlx5_ifc_register_loopback_control_bits { 4111 u8 no_lb[0x1]; 4112 u8 reserved_at_1[0x7]; 4113 u8 port[0x8]; 4114 u8 reserved_at_10[0x10]; 4115 4116 u8 reserved_at_20[0x60]; 4117 }; 4118 4119 struct mlx5_ifc_vport_tc_element_bits { 4120 u8 traffic_class[0x4]; 4121 u8 reserved_at_4[0xc]; 4122 u8 vport_number[0x10]; 4123 }; 4124 4125 struct mlx5_ifc_vport_element_bits { 4126 u8 reserved_at_0[0x10]; 4127 u8 vport_number[0x10]; 4128 }; 4129 4130 enum { 4131 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4132 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4133 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4134 }; 4135 4136 struct mlx5_ifc_tsar_element_bits { 4137 u8 reserved_at_0[0x8]; 4138 u8 tsar_type[0x8]; 4139 u8 reserved_at_10[0x10]; 4140 }; 4141 4142 enum { 4143 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4144 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4145 }; 4146 4147 struct mlx5_ifc_teardown_hca_out_bits { 4148 u8 status[0x8]; 4149 u8 reserved_at_8[0x18]; 4150 4151 u8 syndrome[0x20]; 4152 4153 u8 reserved_at_40[0x3f]; 4154 4155 u8 state[0x1]; 4156 }; 4157 4158 enum { 4159 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4160 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4161 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4162 }; 4163 4164 struct mlx5_ifc_teardown_hca_in_bits { 4165 u8 opcode[0x10]; 4166 u8 reserved_at_10[0x10]; 4167 4168 u8 reserved_at_20[0x10]; 4169 u8 op_mod[0x10]; 4170 4171 u8 reserved_at_40[0x10]; 4172 u8 profile[0x10]; 4173 4174 u8 reserved_at_60[0x20]; 4175 }; 4176 4177 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4178 u8 status[0x8]; 4179 u8 reserved_at_8[0x18]; 4180 4181 u8 syndrome[0x20]; 4182 4183 u8 reserved_at_40[0x40]; 4184 }; 4185 4186 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4187 u8 opcode[0x10]; 4188 u8 uid[0x10]; 4189 4190 u8 reserved_at_20[0x10]; 4191 u8 op_mod[0x10]; 4192 4193 u8 reserved_at_40[0x8]; 4194 u8 qpn[0x18]; 4195 4196 u8 reserved_at_60[0x20]; 4197 4198 u8 opt_param_mask[0x20]; 4199 4200 u8 reserved_at_a0[0x20]; 4201 4202 struct mlx5_ifc_qpc_bits qpc; 4203 4204 u8 reserved_at_800[0x80]; 4205 }; 4206 4207 struct mlx5_ifc_sqd2rts_qp_out_bits { 4208 u8 status[0x8]; 4209 u8 reserved_at_8[0x18]; 4210 4211 u8 syndrome[0x20]; 4212 4213 u8 reserved_at_40[0x40]; 4214 }; 4215 4216 struct mlx5_ifc_sqd2rts_qp_in_bits { 4217 u8 opcode[0x10]; 4218 u8 uid[0x10]; 4219 4220 u8 reserved_at_20[0x10]; 4221 u8 op_mod[0x10]; 4222 4223 u8 reserved_at_40[0x8]; 4224 u8 qpn[0x18]; 4225 4226 u8 reserved_at_60[0x20]; 4227 4228 u8 opt_param_mask[0x20]; 4229 4230 u8 reserved_at_a0[0x20]; 4231 4232 struct mlx5_ifc_qpc_bits qpc; 4233 4234 u8 reserved_at_800[0x80]; 4235 }; 4236 4237 struct mlx5_ifc_set_roce_address_out_bits { 4238 u8 status[0x8]; 4239 u8 reserved_at_8[0x18]; 4240 4241 u8 syndrome[0x20]; 4242 4243 u8 reserved_at_40[0x40]; 4244 }; 4245 4246 struct mlx5_ifc_set_roce_address_in_bits { 4247 u8 opcode[0x10]; 4248 u8 reserved_at_10[0x10]; 4249 4250 u8 reserved_at_20[0x10]; 4251 u8 op_mod[0x10]; 4252 4253 u8 roce_address_index[0x10]; 4254 u8 reserved_at_50[0xc]; 4255 u8 vhca_port_num[0x4]; 4256 4257 u8 reserved_at_60[0x20]; 4258 4259 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4260 }; 4261 4262 struct mlx5_ifc_set_mad_demux_out_bits { 4263 u8 status[0x8]; 4264 u8 reserved_at_8[0x18]; 4265 4266 u8 syndrome[0x20]; 4267 4268 u8 reserved_at_40[0x40]; 4269 }; 4270 4271 enum { 4272 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4273 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4274 }; 4275 4276 struct mlx5_ifc_set_mad_demux_in_bits { 4277 u8 opcode[0x10]; 4278 u8 reserved_at_10[0x10]; 4279 4280 u8 reserved_at_20[0x10]; 4281 u8 op_mod[0x10]; 4282 4283 u8 reserved_at_40[0x20]; 4284 4285 u8 reserved_at_60[0x6]; 4286 u8 demux_mode[0x2]; 4287 u8 reserved_at_68[0x18]; 4288 }; 4289 4290 struct mlx5_ifc_set_l2_table_entry_out_bits { 4291 u8 status[0x8]; 4292 u8 reserved_at_8[0x18]; 4293 4294 u8 syndrome[0x20]; 4295 4296 u8 reserved_at_40[0x40]; 4297 }; 4298 4299 struct mlx5_ifc_set_l2_table_entry_in_bits { 4300 u8 opcode[0x10]; 4301 u8 reserved_at_10[0x10]; 4302 4303 u8 reserved_at_20[0x10]; 4304 u8 op_mod[0x10]; 4305 4306 u8 reserved_at_40[0x60]; 4307 4308 u8 reserved_at_a0[0x8]; 4309 u8 table_index[0x18]; 4310 4311 u8 reserved_at_c0[0x20]; 4312 4313 u8 reserved_at_e0[0x13]; 4314 u8 vlan_valid[0x1]; 4315 u8 vlan[0xc]; 4316 4317 struct mlx5_ifc_mac_address_layout_bits mac_address; 4318 4319 u8 reserved_at_140[0xc0]; 4320 }; 4321 4322 struct mlx5_ifc_set_issi_out_bits { 4323 u8 status[0x8]; 4324 u8 reserved_at_8[0x18]; 4325 4326 u8 syndrome[0x20]; 4327 4328 u8 reserved_at_40[0x40]; 4329 }; 4330 4331 struct mlx5_ifc_set_issi_in_bits { 4332 u8 opcode[0x10]; 4333 u8 reserved_at_10[0x10]; 4334 4335 u8 reserved_at_20[0x10]; 4336 u8 op_mod[0x10]; 4337 4338 u8 reserved_at_40[0x10]; 4339 u8 current_issi[0x10]; 4340 4341 u8 reserved_at_60[0x20]; 4342 }; 4343 4344 struct mlx5_ifc_set_hca_cap_out_bits { 4345 u8 status[0x8]; 4346 u8 reserved_at_8[0x18]; 4347 4348 u8 syndrome[0x20]; 4349 4350 u8 reserved_at_40[0x40]; 4351 }; 4352 4353 struct mlx5_ifc_set_hca_cap_in_bits { 4354 u8 opcode[0x10]; 4355 u8 reserved_at_10[0x10]; 4356 4357 u8 reserved_at_20[0x10]; 4358 u8 op_mod[0x10]; 4359 4360 u8 other_function[0x1]; 4361 u8 reserved_at_41[0xf]; 4362 u8 function_id[0x10]; 4363 4364 u8 reserved_at_60[0x20]; 4365 4366 union mlx5_ifc_hca_cap_union_bits capability; 4367 }; 4368 4369 enum { 4370 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4371 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4372 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4373 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4374 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4375 }; 4376 4377 struct mlx5_ifc_set_fte_out_bits { 4378 u8 status[0x8]; 4379 u8 reserved_at_8[0x18]; 4380 4381 u8 syndrome[0x20]; 4382 4383 u8 reserved_at_40[0x40]; 4384 }; 4385 4386 struct mlx5_ifc_set_fte_in_bits { 4387 u8 opcode[0x10]; 4388 u8 reserved_at_10[0x10]; 4389 4390 u8 reserved_at_20[0x10]; 4391 u8 op_mod[0x10]; 4392 4393 u8 other_vport[0x1]; 4394 u8 reserved_at_41[0xf]; 4395 u8 vport_number[0x10]; 4396 4397 u8 reserved_at_60[0x20]; 4398 4399 u8 table_type[0x8]; 4400 u8 reserved_at_88[0x18]; 4401 4402 u8 reserved_at_a0[0x8]; 4403 u8 table_id[0x18]; 4404 4405 u8 ignore_flow_level[0x1]; 4406 u8 reserved_at_c1[0x17]; 4407 u8 modify_enable_mask[0x8]; 4408 4409 u8 reserved_at_e0[0x20]; 4410 4411 u8 flow_index[0x20]; 4412 4413 u8 reserved_at_120[0xe0]; 4414 4415 struct mlx5_ifc_flow_context_bits flow_context; 4416 }; 4417 4418 struct mlx5_ifc_rts2rts_qp_out_bits { 4419 u8 status[0x8]; 4420 u8 reserved_at_8[0x18]; 4421 4422 u8 syndrome[0x20]; 4423 4424 u8 reserved_at_40[0x20]; 4425 u8 ece[0x20]; 4426 }; 4427 4428 struct mlx5_ifc_rts2rts_qp_in_bits { 4429 u8 opcode[0x10]; 4430 u8 uid[0x10]; 4431 4432 u8 reserved_at_20[0x10]; 4433 u8 op_mod[0x10]; 4434 4435 u8 reserved_at_40[0x8]; 4436 u8 qpn[0x18]; 4437 4438 u8 reserved_at_60[0x20]; 4439 4440 u8 opt_param_mask[0x20]; 4441 4442 u8 ece[0x20]; 4443 4444 struct mlx5_ifc_qpc_bits qpc; 4445 4446 u8 reserved_at_800[0x80]; 4447 }; 4448 4449 struct mlx5_ifc_rtr2rts_qp_out_bits { 4450 u8 status[0x8]; 4451 u8 reserved_at_8[0x18]; 4452 4453 u8 syndrome[0x20]; 4454 4455 u8 reserved_at_40[0x20]; 4456 u8 ece[0x20]; 4457 }; 4458 4459 struct mlx5_ifc_rtr2rts_qp_in_bits { 4460 u8 opcode[0x10]; 4461 u8 uid[0x10]; 4462 4463 u8 reserved_at_20[0x10]; 4464 u8 op_mod[0x10]; 4465 4466 u8 reserved_at_40[0x8]; 4467 u8 qpn[0x18]; 4468 4469 u8 reserved_at_60[0x20]; 4470 4471 u8 opt_param_mask[0x20]; 4472 4473 u8 ece[0x20]; 4474 4475 struct mlx5_ifc_qpc_bits qpc; 4476 4477 u8 reserved_at_800[0x80]; 4478 }; 4479 4480 struct mlx5_ifc_rst2init_qp_out_bits { 4481 u8 status[0x8]; 4482 u8 reserved_at_8[0x18]; 4483 4484 u8 syndrome[0x20]; 4485 4486 u8 reserved_at_40[0x20]; 4487 u8 ece[0x20]; 4488 }; 4489 4490 struct mlx5_ifc_rst2init_qp_in_bits { 4491 u8 opcode[0x10]; 4492 u8 uid[0x10]; 4493 4494 u8 reserved_at_20[0x10]; 4495 u8 op_mod[0x10]; 4496 4497 u8 reserved_at_40[0x8]; 4498 u8 qpn[0x18]; 4499 4500 u8 reserved_at_60[0x20]; 4501 4502 u8 opt_param_mask[0x20]; 4503 4504 u8 ece[0x20]; 4505 4506 struct mlx5_ifc_qpc_bits qpc; 4507 4508 u8 reserved_at_800[0x80]; 4509 }; 4510 4511 struct mlx5_ifc_query_xrq_out_bits { 4512 u8 status[0x8]; 4513 u8 reserved_at_8[0x18]; 4514 4515 u8 syndrome[0x20]; 4516 4517 u8 reserved_at_40[0x40]; 4518 4519 struct mlx5_ifc_xrqc_bits xrq_context; 4520 }; 4521 4522 struct mlx5_ifc_query_xrq_in_bits { 4523 u8 opcode[0x10]; 4524 u8 reserved_at_10[0x10]; 4525 4526 u8 reserved_at_20[0x10]; 4527 u8 op_mod[0x10]; 4528 4529 u8 reserved_at_40[0x8]; 4530 u8 xrqn[0x18]; 4531 4532 u8 reserved_at_60[0x20]; 4533 }; 4534 4535 struct mlx5_ifc_query_xrc_srq_out_bits { 4536 u8 status[0x8]; 4537 u8 reserved_at_8[0x18]; 4538 4539 u8 syndrome[0x20]; 4540 4541 u8 reserved_at_40[0x40]; 4542 4543 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4544 4545 u8 reserved_at_280[0x600]; 4546 4547 u8 pas[][0x40]; 4548 }; 4549 4550 struct mlx5_ifc_query_xrc_srq_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_at_10[0x10]; 4553 4554 u8 reserved_at_20[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 reserved_at_40[0x8]; 4558 u8 xrc_srqn[0x18]; 4559 4560 u8 reserved_at_60[0x20]; 4561 }; 4562 4563 enum { 4564 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4565 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4566 }; 4567 4568 struct mlx5_ifc_query_vport_state_out_bits { 4569 u8 status[0x8]; 4570 u8 reserved_at_8[0x18]; 4571 4572 u8 syndrome[0x20]; 4573 4574 u8 reserved_at_40[0x20]; 4575 4576 u8 reserved_at_60[0x18]; 4577 u8 admin_state[0x4]; 4578 u8 state[0x4]; 4579 }; 4580 4581 enum { 4582 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4583 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4584 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4585 }; 4586 4587 struct mlx5_ifc_arm_monitor_counter_in_bits { 4588 u8 opcode[0x10]; 4589 u8 uid[0x10]; 4590 4591 u8 reserved_at_20[0x10]; 4592 u8 op_mod[0x10]; 4593 4594 u8 reserved_at_40[0x20]; 4595 4596 u8 reserved_at_60[0x20]; 4597 }; 4598 4599 struct mlx5_ifc_arm_monitor_counter_out_bits { 4600 u8 status[0x8]; 4601 u8 reserved_at_8[0x18]; 4602 4603 u8 syndrome[0x20]; 4604 4605 u8 reserved_at_40[0x40]; 4606 }; 4607 4608 enum { 4609 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4610 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4611 }; 4612 4613 enum mlx5_monitor_counter_ppcnt { 4614 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4615 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4616 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4617 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4618 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4619 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4620 }; 4621 4622 enum { 4623 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4624 }; 4625 4626 struct mlx5_ifc_monitor_counter_output_bits { 4627 u8 reserved_at_0[0x4]; 4628 u8 type[0x4]; 4629 u8 reserved_at_8[0x8]; 4630 u8 counter[0x10]; 4631 4632 u8 counter_group_id[0x20]; 4633 }; 4634 4635 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4636 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4637 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4638 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4639 4640 struct mlx5_ifc_set_monitor_counter_in_bits { 4641 u8 opcode[0x10]; 4642 u8 uid[0x10]; 4643 4644 u8 reserved_at_20[0x10]; 4645 u8 op_mod[0x10]; 4646 4647 u8 reserved_at_40[0x10]; 4648 u8 num_of_counters[0x10]; 4649 4650 u8 reserved_at_60[0x20]; 4651 4652 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4653 }; 4654 4655 struct mlx5_ifc_set_monitor_counter_out_bits { 4656 u8 status[0x8]; 4657 u8 reserved_at_8[0x18]; 4658 4659 u8 syndrome[0x20]; 4660 4661 u8 reserved_at_40[0x40]; 4662 }; 4663 4664 struct mlx5_ifc_query_vport_state_in_bits { 4665 u8 opcode[0x10]; 4666 u8 reserved_at_10[0x10]; 4667 4668 u8 reserved_at_20[0x10]; 4669 u8 op_mod[0x10]; 4670 4671 u8 other_vport[0x1]; 4672 u8 reserved_at_41[0xf]; 4673 u8 vport_number[0x10]; 4674 4675 u8 reserved_at_60[0x20]; 4676 }; 4677 4678 struct mlx5_ifc_query_vnic_env_out_bits { 4679 u8 status[0x8]; 4680 u8 reserved_at_8[0x18]; 4681 4682 u8 syndrome[0x20]; 4683 4684 u8 reserved_at_40[0x40]; 4685 4686 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4687 }; 4688 4689 enum { 4690 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4691 }; 4692 4693 struct mlx5_ifc_query_vnic_env_in_bits { 4694 u8 opcode[0x10]; 4695 u8 reserved_at_10[0x10]; 4696 4697 u8 reserved_at_20[0x10]; 4698 u8 op_mod[0x10]; 4699 4700 u8 other_vport[0x1]; 4701 u8 reserved_at_41[0xf]; 4702 u8 vport_number[0x10]; 4703 4704 u8 reserved_at_60[0x20]; 4705 }; 4706 4707 struct mlx5_ifc_query_vport_counter_out_bits { 4708 u8 status[0x8]; 4709 u8 reserved_at_8[0x18]; 4710 4711 u8 syndrome[0x20]; 4712 4713 u8 reserved_at_40[0x40]; 4714 4715 struct mlx5_ifc_traffic_counter_bits received_errors; 4716 4717 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4718 4719 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4720 4721 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4722 4723 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4724 4725 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4726 4727 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4728 4729 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4730 4731 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4732 4733 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4734 4735 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4736 4737 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4738 4739 u8 reserved_at_680[0xa00]; 4740 }; 4741 4742 enum { 4743 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4744 }; 4745 4746 struct mlx5_ifc_query_vport_counter_in_bits { 4747 u8 opcode[0x10]; 4748 u8 reserved_at_10[0x10]; 4749 4750 u8 reserved_at_20[0x10]; 4751 u8 op_mod[0x10]; 4752 4753 u8 other_vport[0x1]; 4754 u8 reserved_at_41[0xb]; 4755 u8 port_num[0x4]; 4756 u8 vport_number[0x10]; 4757 4758 u8 reserved_at_60[0x60]; 4759 4760 u8 clear[0x1]; 4761 u8 reserved_at_c1[0x1f]; 4762 4763 u8 reserved_at_e0[0x20]; 4764 }; 4765 4766 struct mlx5_ifc_query_tis_out_bits { 4767 u8 status[0x8]; 4768 u8 reserved_at_8[0x18]; 4769 4770 u8 syndrome[0x20]; 4771 4772 u8 reserved_at_40[0x40]; 4773 4774 struct mlx5_ifc_tisc_bits tis_context; 4775 }; 4776 4777 struct mlx5_ifc_query_tis_in_bits { 4778 u8 opcode[0x10]; 4779 u8 reserved_at_10[0x10]; 4780 4781 u8 reserved_at_20[0x10]; 4782 u8 op_mod[0x10]; 4783 4784 u8 reserved_at_40[0x8]; 4785 u8 tisn[0x18]; 4786 4787 u8 reserved_at_60[0x20]; 4788 }; 4789 4790 struct mlx5_ifc_query_tir_out_bits { 4791 u8 status[0x8]; 4792 u8 reserved_at_8[0x18]; 4793 4794 u8 syndrome[0x20]; 4795 4796 u8 reserved_at_40[0xc0]; 4797 4798 struct mlx5_ifc_tirc_bits tir_context; 4799 }; 4800 4801 struct mlx5_ifc_query_tir_in_bits { 4802 u8 opcode[0x10]; 4803 u8 reserved_at_10[0x10]; 4804 4805 u8 reserved_at_20[0x10]; 4806 u8 op_mod[0x10]; 4807 4808 u8 reserved_at_40[0x8]; 4809 u8 tirn[0x18]; 4810 4811 u8 reserved_at_60[0x20]; 4812 }; 4813 4814 struct mlx5_ifc_query_srq_out_bits { 4815 u8 status[0x8]; 4816 u8 reserved_at_8[0x18]; 4817 4818 u8 syndrome[0x20]; 4819 4820 u8 reserved_at_40[0x40]; 4821 4822 struct mlx5_ifc_srqc_bits srq_context_entry; 4823 4824 u8 reserved_at_280[0x600]; 4825 4826 u8 pas[][0x40]; 4827 }; 4828 4829 struct mlx5_ifc_query_srq_in_bits { 4830 u8 opcode[0x10]; 4831 u8 reserved_at_10[0x10]; 4832 4833 u8 reserved_at_20[0x10]; 4834 u8 op_mod[0x10]; 4835 4836 u8 reserved_at_40[0x8]; 4837 u8 srqn[0x18]; 4838 4839 u8 reserved_at_60[0x20]; 4840 }; 4841 4842 struct mlx5_ifc_query_sq_out_bits { 4843 u8 status[0x8]; 4844 u8 reserved_at_8[0x18]; 4845 4846 u8 syndrome[0x20]; 4847 4848 u8 reserved_at_40[0xc0]; 4849 4850 struct mlx5_ifc_sqc_bits sq_context; 4851 }; 4852 4853 struct mlx5_ifc_query_sq_in_bits { 4854 u8 opcode[0x10]; 4855 u8 reserved_at_10[0x10]; 4856 4857 u8 reserved_at_20[0x10]; 4858 u8 op_mod[0x10]; 4859 4860 u8 reserved_at_40[0x8]; 4861 u8 sqn[0x18]; 4862 4863 u8 reserved_at_60[0x20]; 4864 }; 4865 4866 struct mlx5_ifc_query_special_contexts_out_bits { 4867 u8 status[0x8]; 4868 u8 reserved_at_8[0x18]; 4869 4870 u8 syndrome[0x20]; 4871 4872 u8 dump_fill_mkey[0x20]; 4873 4874 u8 resd_lkey[0x20]; 4875 4876 u8 null_mkey[0x20]; 4877 4878 u8 reserved_at_a0[0x60]; 4879 }; 4880 4881 struct mlx5_ifc_query_special_contexts_in_bits { 4882 u8 opcode[0x10]; 4883 u8 reserved_at_10[0x10]; 4884 4885 u8 reserved_at_20[0x10]; 4886 u8 op_mod[0x10]; 4887 4888 u8 reserved_at_40[0x40]; 4889 }; 4890 4891 struct mlx5_ifc_query_scheduling_element_out_bits { 4892 u8 opcode[0x10]; 4893 u8 reserved_at_10[0x10]; 4894 4895 u8 reserved_at_20[0x10]; 4896 u8 op_mod[0x10]; 4897 4898 u8 reserved_at_40[0xc0]; 4899 4900 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4901 4902 u8 reserved_at_300[0x100]; 4903 }; 4904 4905 enum { 4906 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4907 SCHEDULING_HIERARCHY_NIC = 0x3, 4908 }; 4909 4910 struct mlx5_ifc_query_scheduling_element_in_bits { 4911 u8 opcode[0x10]; 4912 u8 reserved_at_10[0x10]; 4913 4914 u8 reserved_at_20[0x10]; 4915 u8 op_mod[0x10]; 4916 4917 u8 scheduling_hierarchy[0x8]; 4918 u8 reserved_at_48[0x18]; 4919 4920 u8 scheduling_element_id[0x20]; 4921 4922 u8 reserved_at_80[0x180]; 4923 }; 4924 4925 struct mlx5_ifc_query_rqt_out_bits { 4926 u8 status[0x8]; 4927 u8 reserved_at_8[0x18]; 4928 4929 u8 syndrome[0x20]; 4930 4931 u8 reserved_at_40[0xc0]; 4932 4933 struct mlx5_ifc_rqtc_bits rqt_context; 4934 }; 4935 4936 struct mlx5_ifc_query_rqt_in_bits { 4937 u8 opcode[0x10]; 4938 u8 reserved_at_10[0x10]; 4939 4940 u8 reserved_at_20[0x10]; 4941 u8 op_mod[0x10]; 4942 4943 u8 reserved_at_40[0x8]; 4944 u8 rqtn[0x18]; 4945 4946 u8 reserved_at_60[0x20]; 4947 }; 4948 4949 struct mlx5_ifc_query_rq_out_bits { 4950 u8 status[0x8]; 4951 u8 reserved_at_8[0x18]; 4952 4953 u8 syndrome[0x20]; 4954 4955 u8 reserved_at_40[0xc0]; 4956 4957 struct mlx5_ifc_rqc_bits rq_context; 4958 }; 4959 4960 struct mlx5_ifc_query_rq_in_bits { 4961 u8 opcode[0x10]; 4962 u8 reserved_at_10[0x10]; 4963 4964 u8 reserved_at_20[0x10]; 4965 u8 op_mod[0x10]; 4966 4967 u8 reserved_at_40[0x8]; 4968 u8 rqn[0x18]; 4969 4970 u8 reserved_at_60[0x20]; 4971 }; 4972 4973 struct mlx5_ifc_query_roce_address_out_bits { 4974 u8 status[0x8]; 4975 u8 reserved_at_8[0x18]; 4976 4977 u8 syndrome[0x20]; 4978 4979 u8 reserved_at_40[0x40]; 4980 4981 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4982 }; 4983 4984 struct mlx5_ifc_query_roce_address_in_bits { 4985 u8 opcode[0x10]; 4986 u8 reserved_at_10[0x10]; 4987 4988 u8 reserved_at_20[0x10]; 4989 u8 op_mod[0x10]; 4990 4991 u8 roce_address_index[0x10]; 4992 u8 reserved_at_50[0xc]; 4993 u8 vhca_port_num[0x4]; 4994 4995 u8 reserved_at_60[0x20]; 4996 }; 4997 4998 struct mlx5_ifc_query_rmp_out_bits { 4999 u8 status[0x8]; 5000 u8 reserved_at_8[0x18]; 5001 5002 u8 syndrome[0x20]; 5003 5004 u8 reserved_at_40[0xc0]; 5005 5006 struct mlx5_ifc_rmpc_bits rmp_context; 5007 }; 5008 5009 struct mlx5_ifc_query_rmp_in_bits { 5010 u8 opcode[0x10]; 5011 u8 reserved_at_10[0x10]; 5012 5013 u8 reserved_at_20[0x10]; 5014 u8 op_mod[0x10]; 5015 5016 u8 reserved_at_40[0x8]; 5017 u8 rmpn[0x18]; 5018 5019 u8 reserved_at_60[0x20]; 5020 }; 5021 5022 struct mlx5_ifc_query_qp_out_bits { 5023 u8 status[0x8]; 5024 u8 reserved_at_8[0x18]; 5025 5026 u8 syndrome[0x20]; 5027 5028 u8 reserved_at_40[0x20]; 5029 u8 ece[0x20]; 5030 5031 u8 opt_param_mask[0x20]; 5032 5033 u8 reserved_at_a0[0x20]; 5034 5035 struct mlx5_ifc_qpc_bits qpc; 5036 5037 u8 reserved_at_800[0x80]; 5038 5039 u8 pas[][0x40]; 5040 }; 5041 5042 struct mlx5_ifc_query_qp_in_bits { 5043 u8 opcode[0x10]; 5044 u8 reserved_at_10[0x10]; 5045 5046 u8 reserved_at_20[0x10]; 5047 u8 op_mod[0x10]; 5048 5049 u8 reserved_at_40[0x8]; 5050 u8 qpn[0x18]; 5051 5052 u8 reserved_at_60[0x20]; 5053 }; 5054 5055 struct mlx5_ifc_query_q_counter_out_bits { 5056 u8 status[0x8]; 5057 u8 reserved_at_8[0x18]; 5058 5059 u8 syndrome[0x20]; 5060 5061 u8 reserved_at_40[0x40]; 5062 5063 u8 rx_write_requests[0x20]; 5064 5065 u8 reserved_at_a0[0x20]; 5066 5067 u8 rx_read_requests[0x20]; 5068 5069 u8 reserved_at_e0[0x20]; 5070 5071 u8 rx_atomic_requests[0x20]; 5072 5073 u8 reserved_at_120[0x20]; 5074 5075 u8 rx_dct_connect[0x20]; 5076 5077 u8 reserved_at_160[0x20]; 5078 5079 u8 out_of_buffer[0x20]; 5080 5081 u8 reserved_at_1a0[0x20]; 5082 5083 u8 out_of_sequence[0x20]; 5084 5085 u8 reserved_at_1e0[0x20]; 5086 5087 u8 duplicate_request[0x20]; 5088 5089 u8 reserved_at_220[0x20]; 5090 5091 u8 rnr_nak_retry_err[0x20]; 5092 5093 u8 reserved_at_260[0x20]; 5094 5095 u8 packet_seq_err[0x20]; 5096 5097 u8 reserved_at_2a0[0x20]; 5098 5099 u8 implied_nak_seq_err[0x20]; 5100 5101 u8 reserved_at_2e0[0x20]; 5102 5103 u8 local_ack_timeout_err[0x20]; 5104 5105 u8 reserved_at_320[0xa0]; 5106 5107 u8 resp_local_length_error[0x20]; 5108 5109 u8 req_local_length_error[0x20]; 5110 5111 u8 resp_local_qp_error[0x20]; 5112 5113 u8 local_operation_error[0x20]; 5114 5115 u8 resp_local_protection[0x20]; 5116 5117 u8 req_local_protection[0x20]; 5118 5119 u8 resp_cqe_error[0x20]; 5120 5121 u8 req_cqe_error[0x20]; 5122 5123 u8 req_mw_binding[0x20]; 5124 5125 u8 req_bad_response[0x20]; 5126 5127 u8 req_remote_invalid_request[0x20]; 5128 5129 u8 resp_remote_invalid_request[0x20]; 5130 5131 u8 req_remote_access_errors[0x20]; 5132 5133 u8 resp_remote_access_errors[0x20]; 5134 5135 u8 req_remote_operation_errors[0x20]; 5136 5137 u8 req_transport_retries_exceeded[0x20]; 5138 5139 u8 cq_overflow[0x20]; 5140 5141 u8 resp_cqe_flush_error[0x20]; 5142 5143 u8 req_cqe_flush_error[0x20]; 5144 5145 u8 reserved_at_620[0x20]; 5146 5147 u8 roce_adp_retrans[0x20]; 5148 5149 u8 roce_adp_retrans_to[0x20]; 5150 5151 u8 roce_slow_restart[0x20]; 5152 5153 u8 roce_slow_restart_cnps[0x20]; 5154 5155 u8 roce_slow_restart_trans[0x20]; 5156 5157 u8 reserved_at_6e0[0x120]; 5158 }; 5159 5160 struct mlx5_ifc_query_q_counter_in_bits { 5161 u8 opcode[0x10]; 5162 u8 reserved_at_10[0x10]; 5163 5164 u8 reserved_at_20[0x10]; 5165 u8 op_mod[0x10]; 5166 5167 u8 reserved_at_40[0x80]; 5168 5169 u8 clear[0x1]; 5170 u8 reserved_at_c1[0x1f]; 5171 5172 u8 reserved_at_e0[0x18]; 5173 u8 counter_set_id[0x8]; 5174 }; 5175 5176 struct mlx5_ifc_query_pages_out_bits { 5177 u8 status[0x8]; 5178 u8 reserved_at_8[0x18]; 5179 5180 u8 syndrome[0x20]; 5181 5182 u8 embedded_cpu_function[0x1]; 5183 u8 reserved_at_41[0xf]; 5184 u8 function_id[0x10]; 5185 5186 u8 num_pages[0x20]; 5187 }; 5188 5189 enum { 5190 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5191 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5192 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5193 }; 5194 5195 struct mlx5_ifc_query_pages_in_bits { 5196 u8 opcode[0x10]; 5197 u8 reserved_at_10[0x10]; 5198 5199 u8 reserved_at_20[0x10]; 5200 u8 op_mod[0x10]; 5201 5202 u8 embedded_cpu_function[0x1]; 5203 u8 reserved_at_41[0xf]; 5204 u8 function_id[0x10]; 5205 5206 u8 reserved_at_60[0x20]; 5207 }; 5208 5209 struct mlx5_ifc_query_nic_vport_context_out_bits { 5210 u8 status[0x8]; 5211 u8 reserved_at_8[0x18]; 5212 5213 u8 syndrome[0x20]; 5214 5215 u8 reserved_at_40[0x40]; 5216 5217 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5218 }; 5219 5220 struct mlx5_ifc_query_nic_vport_context_in_bits { 5221 u8 opcode[0x10]; 5222 u8 reserved_at_10[0x10]; 5223 5224 u8 reserved_at_20[0x10]; 5225 u8 op_mod[0x10]; 5226 5227 u8 other_vport[0x1]; 5228 u8 reserved_at_41[0xf]; 5229 u8 vport_number[0x10]; 5230 5231 u8 reserved_at_60[0x5]; 5232 u8 allowed_list_type[0x3]; 5233 u8 reserved_at_68[0x18]; 5234 }; 5235 5236 struct mlx5_ifc_query_mkey_out_bits { 5237 u8 status[0x8]; 5238 u8 reserved_at_8[0x18]; 5239 5240 u8 syndrome[0x20]; 5241 5242 u8 reserved_at_40[0x40]; 5243 5244 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5245 5246 u8 reserved_at_280[0x600]; 5247 5248 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5249 5250 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5251 }; 5252 5253 struct mlx5_ifc_query_mkey_in_bits { 5254 u8 opcode[0x10]; 5255 u8 reserved_at_10[0x10]; 5256 5257 u8 reserved_at_20[0x10]; 5258 u8 op_mod[0x10]; 5259 5260 u8 reserved_at_40[0x8]; 5261 u8 mkey_index[0x18]; 5262 5263 u8 pg_access[0x1]; 5264 u8 reserved_at_61[0x1f]; 5265 }; 5266 5267 struct mlx5_ifc_query_mad_demux_out_bits { 5268 u8 status[0x8]; 5269 u8 reserved_at_8[0x18]; 5270 5271 u8 syndrome[0x20]; 5272 5273 u8 reserved_at_40[0x40]; 5274 5275 u8 mad_dumux_parameters_block[0x20]; 5276 }; 5277 5278 struct mlx5_ifc_query_mad_demux_in_bits { 5279 u8 opcode[0x10]; 5280 u8 reserved_at_10[0x10]; 5281 5282 u8 reserved_at_20[0x10]; 5283 u8 op_mod[0x10]; 5284 5285 u8 reserved_at_40[0x40]; 5286 }; 5287 5288 struct mlx5_ifc_query_l2_table_entry_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_at_8[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 reserved_at_40[0xa0]; 5295 5296 u8 reserved_at_e0[0x13]; 5297 u8 vlan_valid[0x1]; 5298 u8 vlan[0xc]; 5299 5300 struct mlx5_ifc_mac_address_layout_bits mac_address; 5301 5302 u8 reserved_at_140[0xc0]; 5303 }; 5304 5305 struct mlx5_ifc_query_l2_table_entry_in_bits { 5306 u8 opcode[0x10]; 5307 u8 reserved_at_10[0x10]; 5308 5309 u8 reserved_at_20[0x10]; 5310 u8 op_mod[0x10]; 5311 5312 u8 reserved_at_40[0x60]; 5313 5314 u8 reserved_at_a0[0x8]; 5315 u8 table_index[0x18]; 5316 5317 u8 reserved_at_c0[0x140]; 5318 }; 5319 5320 struct mlx5_ifc_query_issi_out_bits { 5321 u8 status[0x8]; 5322 u8 reserved_at_8[0x18]; 5323 5324 u8 syndrome[0x20]; 5325 5326 u8 reserved_at_40[0x10]; 5327 u8 current_issi[0x10]; 5328 5329 u8 reserved_at_60[0xa0]; 5330 5331 u8 reserved_at_100[76][0x8]; 5332 u8 supported_issi_dw0[0x20]; 5333 }; 5334 5335 struct mlx5_ifc_query_issi_in_bits { 5336 u8 opcode[0x10]; 5337 u8 reserved_at_10[0x10]; 5338 5339 u8 reserved_at_20[0x10]; 5340 u8 op_mod[0x10]; 5341 5342 u8 reserved_at_40[0x40]; 5343 }; 5344 5345 struct mlx5_ifc_set_driver_version_out_bits { 5346 u8 status[0x8]; 5347 u8 reserved_0[0x18]; 5348 5349 u8 syndrome[0x20]; 5350 u8 reserved_1[0x40]; 5351 }; 5352 5353 struct mlx5_ifc_set_driver_version_in_bits { 5354 u8 opcode[0x10]; 5355 u8 reserved_0[0x10]; 5356 5357 u8 reserved_1[0x10]; 5358 u8 op_mod[0x10]; 5359 5360 u8 reserved_2[0x40]; 5361 u8 driver_version[64][0x8]; 5362 }; 5363 5364 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5365 u8 status[0x8]; 5366 u8 reserved_at_8[0x18]; 5367 5368 u8 syndrome[0x20]; 5369 5370 u8 reserved_at_40[0x40]; 5371 5372 struct mlx5_ifc_pkey_bits pkey[]; 5373 }; 5374 5375 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5376 u8 opcode[0x10]; 5377 u8 reserved_at_10[0x10]; 5378 5379 u8 reserved_at_20[0x10]; 5380 u8 op_mod[0x10]; 5381 5382 u8 other_vport[0x1]; 5383 u8 reserved_at_41[0xb]; 5384 u8 port_num[0x4]; 5385 u8 vport_number[0x10]; 5386 5387 u8 reserved_at_60[0x10]; 5388 u8 pkey_index[0x10]; 5389 }; 5390 5391 enum { 5392 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5393 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5394 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5395 }; 5396 5397 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5398 u8 status[0x8]; 5399 u8 reserved_at_8[0x18]; 5400 5401 u8 syndrome[0x20]; 5402 5403 u8 reserved_at_40[0x20]; 5404 5405 u8 gids_num[0x10]; 5406 u8 reserved_at_70[0x10]; 5407 5408 struct mlx5_ifc_array128_auto_bits gid[]; 5409 }; 5410 5411 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5412 u8 opcode[0x10]; 5413 u8 reserved_at_10[0x10]; 5414 5415 u8 reserved_at_20[0x10]; 5416 u8 op_mod[0x10]; 5417 5418 u8 other_vport[0x1]; 5419 u8 reserved_at_41[0xb]; 5420 u8 port_num[0x4]; 5421 u8 vport_number[0x10]; 5422 5423 u8 reserved_at_60[0x10]; 5424 u8 gid_index[0x10]; 5425 }; 5426 5427 struct mlx5_ifc_query_hca_vport_context_out_bits { 5428 u8 status[0x8]; 5429 u8 reserved_at_8[0x18]; 5430 5431 u8 syndrome[0x20]; 5432 5433 u8 reserved_at_40[0x40]; 5434 5435 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5436 }; 5437 5438 struct mlx5_ifc_query_hca_vport_context_in_bits { 5439 u8 opcode[0x10]; 5440 u8 reserved_at_10[0x10]; 5441 5442 u8 reserved_at_20[0x10]; 5443 u8 op_mod[0x10]; 5444 5445 u8 other_vport[0x1]; 5446 u8 reserved_at_41[0xb]; 5447 u8 port_num[0x4]; 5448 u8 vport_number[0x10]; 5449 5450 u8 reserved_at_60[0x20]; 5451 }; 5452 5453 struct mlx5_ifc_query_hca_cap_out_bits { 5454 u8 status[0x8]; 5455 u8 reserved_at_8[0x18]; 5456 5457 u8 syndrome[0x20]; 5458 5459 u8 reserved_at_40[0x40]; 5460 5461 union mlx5_ifc_hca_cap_union_bits capability; 5462 }; 5463 5464 struct mlx5_ifc_query_hca_cap_in_bits { 5465 u8 opcode[0x10]; 5466 u8 reserved_at_10[0x10]; 5467 5468 u8 reserved_at_20[0x10]; 5469 u8 op_mod[0x10]; 5470 5471 u8 other_function[0x1]; 5472 u8 reserved_at_41[0xf]; 5473 u8 function_id[0x10]; 5474 5475 u8 reserved_at_60[0x20]; 5476 }; 5477 5478 struct mlx5_ifc_other_hca_cap_bits { 5479 u8 roce[0x1]; 5480 u8 reserved_at_1[0x27f]; 5481 }; 5482 5483 struct mlx5_ifc_query_other_hca_cap_out_bits { 5484 u8 status[0x8]; 5485 u8 reserved_at_8[0x18]; 5486 5487 u8 syndrome[0x20]; 5488 5489 u8 reserved_at_40[0x40]; 5490 5491 struct mlx5_ifc_other_hca_cap_bits other_capability; 5492 }; 5493 5494 struct mlx5_ifc_query_other_hca_cap_in_bits { 5495 u8 opcode[0x10]; 5496 u8 reserved_at_10[0x10]; 5497 5498 u8 reserved_at_20[0x10]; 5499 u8 op_mod[0x10]; 5500 5501 u8 reserved_at_40[0x10]; 5502 u8 function_id[0x10]; 5503 5504 u8 reserved_at_60[0x20]; 5505 }; 5506 5507 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5508 u8 status[0x8]; 5509 u8 reserved_at_8[0x18]; 5510 5511 u8 syndrome[0x20]; 5512 5513 u8 reserved_at_40[0x40]; 5514 }; 5515 5516 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5517 u8 opcode[0x10]; 5518 u8 reserved_at_10[0x10]; 5519 5520 u8 reserved_at_20[0x10]; 5521 u8 op_mod[0x10]; 5522 5523 u8 reserved_at_40[0x10]; 5524 u8 function_id[0x10]; 5525 u8 field_select[0x20]; 5526 5527 struct mlx5_ifc_other_hca_cap_bits other_capability; 5528 }; 5529 5530 struct mlx5_ifc_flow_table_context_bits { 5531 u8 reformat_en[0x1]; 5532 u8 decap_en[0x1]; 5533 u8 sw_owner[0x1]; 5534 u8 termination_table[0x1]; 5535 u8 table_miss_action[0x4]; 5536 u8 level[0x8]; 5537 u8 reserved_at_10[0x8]; 5538 u8 log_size[0x8]; 5539 5540 u8 reserved_at_20[0x8]; 5541 u8 table_miss_id[0x18]; 5542 5543 u8 reserved_at_40[0x8]; 5544 u8 lag_master_next_table_id[0x18]; 5545 5546 u8 reserved_at_60[0x60]; 5547 5548 u8 sw_owner_icm_root_1[0x40]; 5549 5550 u8 sw_owner_icm_root_0[0x40]; 5551 5552 }; 5553 5554 struct mlx5_ifc_query_flow_table_out_bits { 5555 u8 status[0x8]; 5556 u8 reserved_at_8[0x18]; 5557 5558 u8 syndrome[0x20]; 5559 5560 u8 reserved_at_40[0x80]; 5561 5562 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5563 }; 5564 5565 struct mlx5_ifc_query_flow_table_in_bits { 5566 u8 opcode[0x10]; 5567 u8 reserved_at_10[0x10]; 5568 5569 u8 reserved_at_20[0x10]; 5570 u8 op_mod[0x10]; 5571 5572 u8 reserved_at_40[0x40]; 5573 5574 u8 table_type[0x8]; 5575 u8 reserved_at_88[0x18]; 5576 5577 u8 reserved_at_a0[0x8]; 5578 u8 table_id[0x18]; 5579 5580 u8 reserved_at_c0[0x140]; 5581 }; 5582 5583 struct mlx5_ifc_query_fte_out_bits { 5584 u8 status[0x8]; 5585 u8 reserved_at_8[0x18]; 5586 5587 u8 syndrome[0x20]; 5588 5589 u8 reserved_at_40[0x1c0]; 5590 5591 struct mlx5_ifc_flow_context_bits flow_context; 5592 }; 5593 5594 struct mlx5_ifc_query_fte_in_bits { 5595 u8 opcode[0x10]; 5596 u8 reserved_at_10[0x10]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 op_mod[0x10]; 5600 5601 u8 reserved_at_40[0x40]; 5602 5603 u8 table_type[0x8]; 5604 u8 reserved_at_88[0x18]; 5605 5606 u8 reserved_at_a0[0x8]; 5607 u8 table_id[0x18]; 5608 5609 u8 reserved_at_c0[0x40]; 5610 5611 u8 flow_index[0x20]; 5612 5613 u8 reserved_at_120[0xe0]; 5614 }; 5615 5616 enum { 5617 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5618 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5619 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5620 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5621 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5622 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5623 }; 5624 5625 struct mlx5_ifc_query_flow_group_out_bits { 5626 u8 status[0x8]; 5627 u8 reserved_at_8[0x18]; 5628 5629 u8 syndrome[0x20]; 5630 5631 u8 reserved_at_40[0xa0]; 5632 5633 u8 start_flow_index[0x20]; 5634 5635 u8 reserved_at_100[0x20]; 5636 5637 u8 end_flow_index[0x20]; 5638 5639 u8 reserved_at_140[0xa0]; 5640 5641 u8 reserved_at_1e0[0x18]; 5642 u8 match_criteria_enable[0x8]; 5643 5644 struct mlx5_ifc_fte_match_param_bits match_criteria; 5645 5646 u8 reserved_at_1200[0xe00]; 5647 }; 5648 5649 struct mlx5_ifc_query_flow_group_in_bits { 5650 u8 opcode[0x10]; 5651 u8 reserved_at_10[0x10]; 5652 5653 u8 reserved_at_20[0x10]; 5654 u8 op_mod[0x10]; 5655 5656 u8 reserved_at_40[0x40]; 5657 5658 u8 table_type[0x8]; 5659 u8 reserved_at_88[0x18]; 5660 5661 u8 reserved_at_a0[0x8]; 5662 u8 table_id[0x18]; 5663 5664 u8 group_id[0x20]; 5665 5666 u8 reserved_at_e0[0x120]; 5667 }; 5668 5669 struct mlx5_ifc_query_flow_counter_out_bits { 5670 u8 status[0x8]; 5671 u8 reserved_at_8[0x18]; 5672 5673 u8 syndrome[0x20]; 5674 5675 u8 reserved_at_40[0x40]; 5676 5677 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5678 }; 5679 5680 struct mlx5_ifc_query_flow_counter_in_bits { 5681 u8 opcode[0x10]; 5682 u8 reserved_at_10[0x10]; 5683 5684 u8 reserved_at_20[0x10]; 5685 u8 op_mod[0x10]; 5686 5687 u8 reserved_at_40[0x80]; 5688 5689 u8 clear[0x1]; 5690 u8 reserved_at_c1[0xf]; 5691 u8 num_of_counters[0x10]; 5692 5693 u8 flow_counter_id[0x20]; 5694 }; 5695 5696 struct mlx5_ifc_query_esw_vport_context_out_bits { 5697 u8 status[0x8]; 5698 u8 reserved_at_8[0x18]; 5699 5700 u8 syndrome[0x20]; 5701 5702 u8 reserved_at_40[0x40]; 5703 5704 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5705 }; 5706 5707 struct mlx5_ifc_query_esw_vport_context_in_bits { 5708 u8 opcode[0x10]; 5709 u8 reserved_at_10[0x10]; 5710 5711 u8 reserved_at_20[0x10]; 5712 u8 op_mod[0x10]; 5713 5714 u8 other_vport[0x1]; 5715 u8 reserved_at_41[0xf]; 5716 u8 vport_number[0x10]; 5717 5718 u8 reserved_at_60[0x20]; 5719 }; 5720 5721 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5722 u8 status[0x8]; 5723 u8 reserved_at_8[0x18]; 5724 5725 u8 syndrome[0x20]; 5726 5727 u8 reserved_at_40[0x40]; 5728 }; 5729 5730 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5731 u8 reserved_at_0[0x1b]; 5732 u8 fdb_to_vport_reg_c_id[0x1]; 5733 u8 vport_cvlan_insert[0x1]; 5734 u8 vport_svlan_insert[0x1]; 5735 u8 vport_cvlan_strip[0x1]; 5736 u8 vport_svlan_strip[0x1]; 5737 }; 5738 5739 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5740 u8 opcode[0x10]; 5741 u8 reserved_at_10[0x10]; 5742 5743 u8 reserved_at_20[0x10]; 5744 u8 op_mod[0x10]; 5745 5746 u8 other_vport[0x1]; 5747 u8 reserved_at_41[0xf]; 5748 u8 vport_number[0x10]; 5749 5750 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5751 5752 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5753 }; 5754 5755 struct mlx5_ifc_query_eq_out_bits { 5756 u8 status[0x8]; 5757 u8 reserved_at_8[0x18]; 5758 5759 u8 syndrome[0x20]; 5760 5761 u8 reserved_at_40[0x40]; 5762 5763 struct mlx5_ifc_eqc_bits eq_context_entry; 5764 5765 u8 reserved_at_280[0x40]; 5766 5767 u8 event_bitmask[0x40]; 5768 5769 u8 reserved_at_300[0x580]; 5770 5771 u8 pas[][0x40]; 5772 }; 5773 5774 struct mlx5_ifc_query_eq_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 reserved_at_40[0x18]; 5782 u8 eq_number[0x8]; 5783 5784 u8 reserved_at_60[0x20]; 5785 }; 5786 5787 struct mlx5_ifc_packet_reformat_context_in_bits { 5788 u8 reserved_at_0[0x5]; 5789 u8 reformat_type[0x3]; 5790 u8 reserved_at_8[0xe]; 5791 u8 reformat_data_size[0xa]; 5792 5793 u8 reserved_at_20[0x10]; 5794 u8 reformat_data[2][0x8]; 5795 5796 u8 more_reformat_data[][0x8]; 5797 }; 5798 5799 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0xa0]; 5806 5807 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5808 }; 5809 5810 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5811 u8 opcode[0x10]; 5812 u8 reserved_at_10[0x10]; 5813 5814 u8 reserved_at_20[0x10]; 5815 u8 op_mod[0x10]; 5816 5817 u8 packet_reformat_id[0x20]; 5818 5819 u8 reserved_at_60[0xa0]; 5820 }; 5821 5822 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5823 u8 status[0x8]; 5824 u8 reserved_at_8[0x18]; 5825 5826 u8 syndrome[0x20]; 5827 5828 u8 packet_reformat_id[0x20]; 5829 5830 u8 reserved_at_60[0x20]; 5831 }; 5832 5833 enum mlx5_reformat_ctx_type { 5834 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5835 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5836 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5837 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5838 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5839 }; 5840 5841 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5842 u8 opcode[0x10]; 5843 u8 reserved_at_10[0x10]; 5844 5845 u8 reserved_at_20[0x10]; 5846 u8 op_mod[0x10]; 5847 5848 u8 reserved_at_40[0xa0]; 5849 5850 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5851 }; 5852 5853 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5854 u8 status[0x8]; 5855 u8 reserved_at_8[0x18]; 5856 5857 u8 syndrome[0x20]; 5858 5859 u8 reserved_at_40[0x40]; 5860 }; 5861 5862 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5863 u8 opcode[0x10]; 5864 u8 reserved_at_10[0x10]; 5865 5866 u8 reserved_20[0x10]; 5867 u8 op_mod[0x10]; 5868 5869 u8 packet_reformat_id[0x20]; 5870 5871 u8 reserved_60[0x20]; 5872 }; 5873 5874 struct mlx5_ifc_set_action_in_bits { 5875 u8 action_type[0x4]; 5876 u8 field[0xc]; 5877 u8 reserved_at_10[0x3]; 5878 u8 offset[0x5]; 5879 u8 reserved_at_18[0x3]; 5880 u8 length[0x5]; 5881 5882 u8 data[0x20]; 5883 }; 5884 5885 struct mlx5_ifc_add_action_in_bits { 5886 u8 action_type[0x4]; 5887 u8 field[0xc]; 5888 u8 reserved_at_10[0x10]; 5889 5890 u8 data[0x20]; 5891 }; 5892 5893 struct mlx5_ifc_copy_action_in_bits { 5894 u8 action_type[0x4]; 5895 u8 src_field[0xc]; 5896 u8 reserved_at_10[0x3]; 5897 u8 src_offset[0x5]; 5898 u8 reserved_at_18[0x3]; 5899 u8 length[0x5]; 5900 5901 u8 reserved_at_20[0x4]; 5902 u8 dst_field[0xc]; 5903 u8 reserved_at_30[0x3]; 5904 u8 dst_offset[0x5]; 5905 u8 reserved_at_38[0x8]; 5906 }; 5907 5908 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5909 struct mlx5_ifc_set_action_in_bits set_action_in; 5910 struct mlx5_ifc_add_action_in_bits add_action_in; 5911 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5912 u8 reserved_at_0[0x40]; 5913 }; 5914 5915 enum { 5916 MLX5_ACTION_TYPE_SET = 0x1, 5917 MLX5_ACTION_TYPE_ADD = 0x2, 5918 MLX5_ACTION_TYPE_COPY = 0x3, 5919 }; 5920 5921 enum { 5922 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5923 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5924 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5925 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5926 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5927 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5928 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5929 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5930 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5931 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5932 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5933 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5934 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5935 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5936 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5937 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5938 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5939 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5940 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5941 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5942 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5943 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5944 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5945 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5946 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5947 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5948 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5949 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5950 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5951 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5952 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5953 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5954 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5955 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5956 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5957 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5958 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5959 }; 5960 5961 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5962 u8 status[0x8]; 5963 u8 reserved_at_8[0x18]; 5964 5965 u8 syndrome[0x20]; 5966 5967 u8 modify_header_id[0x20]; 5968 5969 u8 reserved_at_60[0x20]; 5970 }; 5971 5972 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5973 u8 opcode[0x10]; 5974 u8 reserved_at_10[0x10]; 5975 5976 u8 reserved_at_20[0x10]; 5977 u8 op_mod[0x10]; 5978 5979 u8 reserved_at_40[0x20]; 5980 5981 u8 table_type[0x8]; 5982 u8 reserved_at_68[0x10]; 5983 u8 num_of_actions[0x8]; 5984 5985 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5986 }; 5987 5988 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5989 u8 status[0x8]; 5990 u8 reserved_at_8[0x18]; 5991 5992 u8 syndrome[0x20]; 5993 5994 u8 reserved_at_40[0x40]; 5995 }; 5996 5997 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5998 u8 opcode[0x10]; 5999 u8 reserved_at_10[0x10]; 6000 6001 u8 reserved_at_20[0x10]; 6002 u8 op_mod[0x10]; 6003 6004 u8 modify_header_id[0x20]; 6005 6006 u8 reserved_at_60[0x20]; 6007 }; 6008 6009 struct mlx5_ifc_query_modify_header_context_in_bits { 6010 u8 opcode[0x10]; 6011 u8 uid[0x10]; 6012 6013 u8 reserved_at_20[0x10]; 6014 u8 op_mod[0x10]; 6015 6016 u8 modify_header_id[0x20]; 6017 6018 u8 reserved_at_60[0xa0]; 6019 }; 6020 6021 struct mlx5_ifc_query_dct_out_bits { 6022 u8 status[0x8]; 6023 u8 reserved_at_8[0x18]; 6024 6025 u8 syndrome[0x20]; 6026 6027 u8 reserved_at_40[0x40]; 6028 6029 struct mlx5_ifc_dctc_bits dct_context_entry; 6030 6031 u8 reserved_at_280[0x180]; 6032 }; 6033 6034 struct mlx5_ifc_query_dct_in_bits { 6035 u8 opcode[0x10]; 6036 u8 reserved_at_10[0x10]; 6037 6038 u8 reserved_at_20[0x10]; 6039 u8 op_mod[0x10]; 6040 6041 u8 reserved_at_40[0x8]; 6042 u8 dctn[0x18]; 6043 6044 u8 reserved_at_60[0x20]; 6045 }; 6046 6047 struct mlx5_ifc_query_cq_out_bits { 6048 u8 status[0x8]; 6049 u8 reserved_at_8[0x18]; 6050 6051 u8 syndrome[0x20]; 6052 6053 u8 reserved_at_40[0x40]; 6054 6055 struct mlx5_ifc_cqc_bits cq_context; 6056 6057 u8 reserved_at_280[0x600]; 6058 6059 u8 pas[][0x40]; 6060 }; 6061 6062 struct mlx5_ifc_query_cq_in_bits { 6063 u8 opcode[0x10]; 6064 u8 reserved_at_10[0x10]; 6065 6066 u8 reserved_at_20[0x10]; 6067 u8 op_mod[0x10]; 6068 6069 u8 reserved_at_40[0x8]; 6070 u8 cqn[0x18]; 6071 6072 u8 reserved_at_60[0x20]; 6073 }; 6074 6075 struct mlx5_ifc_query_cong_status_out_bits { 6076 u8 status[0x8]; 6077 u8 reserved_at_8[0x18]; 6078 6079 u8 syndrome[0x20]; 6080 6081 u8 reserved_at_40[0x20]; 6082 6083 u8 enable[0x1]; 6084 u8 tag_enable[0x1]; 6085 u8 reserved_at_62[0x1e]; 6086 }; 6087 6088 struct mlx5_ifc_query_cong_status_in_bits { 6089 u8 opcode[0x10]; 6090 u8 reserved_at_10[0x10]; 6091 6092 u8 reserved_at_20[0x10]; 6093 u8 op_mod[0x10]; 6094 6095 u8 reserved_at_40[0x18]; 6096 u8 priority[0x4]; 6097 u8 cong_protocol[0x4]; 6098 6099 u8 reserved_at_60[0x20]; 6100 }; 6101 6102 struct mlx5_ifc_query_cong_statistics_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_at_8[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 reserved_at_40[0x40]; 6109 6110 u8 rp_cur_flows[0x20]; 6111 6112 u8 sum_flows[0x20]; 6113 6114 u8 rp_cnp_ignored_high[0x20]; 6115 6116 u8 rp_cnp_ignored_low[0x20]; 6117 6118 u8 rp_cnp_handled_high[0x20]; 6119 6120 u8 rp_cnp_handled_low[0x20]; 6121 6122 u8 reserved_at_140[0x100]; 6123 6124 u8 time_stamp_high[0x20]; 6125 6126 u8 time_stamp_low[0x20]; 6127 6128 u8 accumulators_period[0x20]; 6129 6130 u8 np_ecn_marked_roce_packets_high[0x20]; 6131 6132 u8 np_ecn_marked_roce_packets_low[0x20]; 6133 6134 u8 np_cnp_sent_high[0x20]; 6135 6136 u8 np_cnp_sent_low[0x20]; 6137 6138 u8 reserved_at_320[0x560]; 6139 }; 6140 6141 struct mlx5_ifc_query_cong_statistics_in_bits { 6142 u8 opcode[0x10]; 6143 u8 reserved_at_10[0x10]; 6144 6145 u8 reserved_at_20[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 clear[0x1]; 6149 u8 reserved_at_41[0x1f]; 6150 6151 u8 reserved_at_60[0x20]; 6152 }; 6153 6154 struct mlx5_ifc_query_cong_params_out_bits { 6155 u8 status[0x8]; 6156 u8 reserved_at_8[0x18]; 6157 6158 u8 syndrome[0x20]; 6159 6160 u8 reserved_at_40[0x40]; 6161 6162 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6163 }; 6164 6165 struct mlx5_ifc_query_cong_params_in_bits { 6166 u8 opcode[0x10]; 6167 u8 reserved_at_10[0x10]; 6168 6169 u8 reserved_at_20[0x10]; 6170 u8 op_mod[0x10]; 6171 6172 u8 reserved_at_40[0x1c]; 6173 u8 cong_protocol[0x4]; 6174 6175 u8 reserved_at_60[0x20]; 6176 }; 6177 6178 struct mlx5_ifc_query_adapter_out_bits { 6179 u8 status[0x8]; 6180 u8 reserved_at_8[0x18]; 6181 6182 u8 syndrome[0x20]; 6183 6184 u8 reserved_at_40[0x40]; 6185 6186 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6187 }; 6188 6189 struct mlx5_ifc_query_adapter_in_bits { 6190 u8 opcode[0x10]; 6191 u8 reserved_at_10[0x10]; 6192 6193 u8 reserved_at_20[0x10]; 6194 u8 op_mod[0x10]; 6195 6196 u8 reserved_at_40[0x40]; 6197 }; 6198 6199 struct mlx5_ifc_qp_2rst_out_bits { 6200 u8 status[0x8]; 6201 u8 reserved_at_8[0x18]; 6202 6203 u8 syndrome[0x20]; 6204 6205 u8 reserved_at_40[0x40]; 6206 }; 6207 6208 struct mlx5_ifc_qp_2rst_in_bits { 6209 u8 opcode[0x10]; 6210 u8 uid[0x10]; 6211 6212 u8 reserved_at_20[0x10]; 6213 u8 op_mod[0x10]; 6214 6215 u8 reserved_at_40[0x8]; 6216 u8 qpn[0x18]; 6217 6218 u8 reserved_at_60[0x20]; 6219 }; 6220 6221 struct mlx5_ifc_qp_2err_out_bits { 6222 u8 status[0x8]; 6223 u8 reserved_at_8[0x18]; 6224 6225 u8 syndrome[0x20]; 6226 6227 u8 reserved_at_40[0x40]; 6228 }; 6229 6230 struct mlx5_ifc_qp_2err_in_bits { 6231 u8 opcode[0x10]; 6232 u8 uid[0x10]; 6233 6234 u8 reserved_at_20[0x10]; 6235 u8 op_mod[0x10]; 6236 6237 u8 reserved_at_40[0x8]; 6238 u8 qpn[0x18]; 6239 6240 u8 reserved_at_60[0x20]; 6241 }; 6242 6243 struct mlx5_ifc_page_fault_resume_out_bits { 6244 u8 status[0x8]; 6245 u8 reserved_at_8[0x18]; 6246 6247 u8 syndrome[0x20]; 6248 6249 u8 reserved_at_40[0x40]; 6250 }; 6251 6252 struct mlx5_ifc_page_fault_resume_in_bits { 6253 u8 opcode[0x10]; 6254 u8 reserved_at_10[0x10]; 6255 6256 u8 reserved_at_20[0x10]; 6257 u8 op_mod[0x10]; 6258 6259 u8 error[0x1]; 6260 u8 reserved_at_41[0x4]; 6261 u8 page_fault_type[0x3]; 6262 u8 wq_number[0x18]; 6263 6264 u8 reserved_at_60[0x8]; 6265 u8 token[0x18]; 6266 }; 6267 6268 struct mlx5_ifc_nop_out_bits { 6269 u8 status[0x8]; 6270 u8 reserved_at_8[0x18]; 6271 6272 u8 syndrome[0x20]; 6273 6274 u8 reserved_at_40[0x40]; 6275 }; 6276 6277 struct mlx5_ifc_nop_in_bits { 6278 u8 opcode[0x10]; 6279 u8 reserved_at_10[0x10]; 6280 6281 u8 reserved_at_20[0x10]; 6282 u8 op_mod[0x10]; 6283 6284 u8 reserved_at_40[0x40]; 6285 }; 6286 6287 struct mlx5_ifc_modify_vport_state_out_bits { 6288 u8 status[0x8]; 6289 u8 reserved_at_8[0x18]; 6290 6291 u8 syndrome[0x20]; 6292 6293 u8 reserved_at_40[0x40]; 6294 }; 6295 6296 struct mlx5_ifc_modify_vport_state_in_bits { 6297 u8 opcode[0x10]; 6298 u8 reserved_at_10[0x10]; 6299 6300 u8 reserved_at_20[0x10]; 6301 u8 op_mod[0x10]; 6302 6303 u8 other_vport[0x1]; 6304 u8 reserved_at_41[0xf]; 6305 u8 vport_number[0x10]; 6306 6307 u8 reserved_at_60[0x18]; 6308 u8 admin_state[0x4]; 6309 u8 reserved_at_7c[0x4]; 6310 }; 6311 6312 struct mlx5_ifc_modify_tis_out_bits { 6313 u8 status[0x8]; 6314 u8 reserved_at_8[0x18]; 6315 6316 u8 syndrome[0x20]; 6317 6318 u8 reserved_at_40[0x40]; 6319 }; 6320 6321 struct mlx5_ifc_modify_tis_bitmask_bits { 6322 u8 reserved_at_0[0x20]; 6323 6324 u8 reserved_at_20[0x1d]; 6325 u8 lag_tx_port_affinity[0x1]; 6326 u8 strict_lag_tx_port_affinity[0x1]; 6327 u8 prio[0x1]; 6328 }; 6329 6330 struct mlx5_ifc_modify_tis_in_bits { 6331 u8 opcode[0x10]; 6332 u8 uid[0x10]; 6333 6334 u8 reserved_at_20[0x10]; 6335 u8 op_mod[0x10]; 6336 6337 u8 reserved_at_40[0x8]; 6338 u8 tisn[0x18]; 6339 6340 u8 reserved_at_60[0x20]; 6341 6342 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6343 6344 u8 reserved_at_c0[0x40]; 6345 6346 struct mlx5_ifc_tisc_bits ctx; 6347 }; 6348 6349 struct mlx5_ifc_modify_tir_bitmask_bits { 6350 u8 reserved_at_0[0x20]; 6351 6352 u8 reserved_at_20[0x1b]; 6353 u8 self_lb_en[0x1]; 6354 u8 reserved_at_3c[0x1]; 6355 u8 hash[0x1]; 6356 u8 reserved_at_3e[0x1]; 6357 u8 lro[0x1]; 6358 }; 6359 6360 struct mlx5_ifc_modify_tir_out_bits { 6361 u8 status[0x8]; 6362 u8 reserved_at_8[0x18]; 6363 6364 u8 syndrome[0x20]; 6365 6366 u8 reserved_at_40[0x40]; 6367 }; 6368 6369 struct mlx5_ifc_modify_tir_in_bits { 6370 u8 opcode[0x10]; 6371 u8 uid[0x10]; 6372 6373 u8 reserved_at_20[0x10]; 6374 u8 op_mod[0x10]; 6375 6376 u8 reserved_at_40[0x8]; 6377 u8 tirn[0x18]; 6378 6379 u8 reserved_at_60[0x20]; 6380 6381 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6382 6383 u8 reserved_at_c0[0x40]; 6384 6385 struct mlx5_ifc_tirc_bits ctx; 6386 }; 6387 6388 struct mlx5_ifc_modify_sq_out_bits { 6389 u8 status[0x8]; 6390 u8 reserved_at_8[0x18]; 6391 6392 u8 syndrome[0x20]; 6393 6394 u8 reserved_at_40[0x40]; 6395 }; 6396 6397 struct mlx5_ifc_modify_sq_in_bits { 6398 u8 opcode[0x10]; 6399 u8 uid[0x10]; 6400 6401 u8 reserved_at_20[0x10]; 6402 u8 op_mod[0x10]; 6403 6404 u8 sq_state[0x4]; 6405 u8 reserved_at_44[0x4]; 6406 u8 sqn[0x18]; 6407 6408 u8 reserved_at_60[0x20]; 6409 6410 u8 modify_bitmask[0x40]; 6411 6412 u8 reserved_at_c0[0x40]; 6413 6414 struct mlx5_ifc_sqc_bits ctx; 6415 }; 6416 6417 struct mlx5_ifc_modify_scheduling_element_out_bits { 6418 u8 status[0x8]; 6419 u8 reserved_at_8[0x18]; 6420 6421 u8 syndrome[0x20]; 6422 6423 u8 reserved_at_40[0x1c0]; 6424 }; 6425 6426 enum { 6427 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6428 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6429 }; 6430 6431 struct mlx5_ifc_modify_scheduling_element_in_bits { 6432 u8 opcode[0x10]; 6433 u8 reserved_at_10[0x10]; 6434 6435 u8 reserved_at_20[0x10]; 6436 u8 op_mod[0x10]; 6437 6438 u8 scheduling_hierarchy[0x8]; 6439 u8 reserved_at_48[0x18]; 6440 6441 u8 scheduling_element_id[0x20]; 6442 6443 u8 reserved_at_80[0x20]; 6444 6445 u8 modify_bitmask[0x20]; 6446 6447 u8 reserved_at_c0[0x40]; 6448 6449 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6450 6451 u8 reserved_at_300[0x100]; 6452 }; 6453 6454 struct mlx5_ifc_modify_rqt_out_bits { 6455 u8 status[0x8]; 6456 u8 reserved_at_8[0x18]; 6457 6458 u8 syndrome[0x20]; 6459 6460 u8 reserved_at_40[0x40]; 6461 }; 6462 6463 struct mlx5_ifc_rqt_bitmask_bits { 6464 u8 reserved_at_0[0x20]; 6465 6466 u8 reserved_at_20[0x1f]; 6467 u8 rqn_list[0x1]; 6468 }; 6469 6470 struct mlx5_ifc_modify_rqt_in_bits { 6471 u8 opcode[0x10]; 6472 u8 uid[0x10]; 6473 6474 u8 reserved_at_20[0x10]; 6475 u8 op_mod[0x10]; 6476 6477 u8 reserved_at_40[0x8]; 6478 u8 rqtn[0x18]; 6479 6480 u8 reserved_at_60[0x20]; 6481 6482 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6483 6484 u8 reserved_at_c0[0x40]; 6485 6486 struct mlx5_ifc_rqtc_bits ctx; 6487 }; 6488 6489 struct mlx5_ifc_modify_rq_out_bits { 6490 u8 status[0x8]; 6491 u8 reserved_at_8[0x18]; 6492 6493 u8 syndrome[0x20]; 6494 6495 u8 reserved_at_40[0x40]; 6496 }; 6497 6498 enum { 6499 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6500 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6501 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6502 }; 6503 6504 struct mlx5_ifc_modify_rq_in_bits { 6505 u8 opcode[0x10]; 6506 u8 uid[0x10]; 6507 6508 u8 reserved_at_20[0x10]; 6509 u8 op_mod[0x10]; 6510 6511 u8 rq_state[0x4]; 6512 u8 reserved_at_44[0x4]; 6513 u8 rqn[0x18]; 6514 6515 u8 reserved_at_60[0x20]; 6516 6517 u8 modify_bitmask[0x40]; 6518 6519 u8 reserved_at_c0[0x40]; 6520 6521 struct mlx5_ifc_rqc_bits ctx; 6522 }; 6523 6524 struct mlx5_ifc_modify_rmp_out_bits { 6525 u8 status[0x8]; 6526 u8 reserved_at_8[0x18]; 6527 6528 u8 syndrome[0x20]; 6529 6530 u8 reserved_at_40[0x40]; 6531 }; 6532 6533 struct mlx5_ifc_rmp_bitmask_bits { 6534 u8 reserved_at_0[0x20]; 6535 6536 u8 reserved_at_20[0x1f]; 6537 u8 lwm[0x1]; 6538 }; 6539 6540 struct mlx5_ifc_modify_rmp_in_bits { 6541 u8 opcode[0x10]; 6542 u8 uid[0x10]; 6543 6544 u8 reserved_at_20[0x10]; 6545 u8 op_mod[0x10]; 6546 6547 u8 rmp_state[0x4]; 6548 u8 reserved_at_44[0x4]; 6549 u8 rmpn[0x18]; 6550 6551 u8 reserved_at_60[0x20]; 6552 6553 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6554 6555 u8 reserved_at_c0[0x40]; 6556 6557 struct mlx5_ifc_rmpc_bits ctx; 6558 }; 6559 6560 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6561 u8 status[0x8]; 6562 u8 reserved_at_8[0x18]; 6563 6564 u8 syndrome[0x20]; 6565 6566 u8 reserved_at_40[0x40]; 6567 }; 6568 6569 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6570 u8 reserved_at_0[0x12]; 6571 u8 affiliation[0x1]; 6572 u8 reserved_at_13[0x1]; 6573 u8 disable_uc_local_lb[0x1]; 6574 u8 disable_mc_local_lb[0x1]; 6575 u8 node_guid[0x1]; 6576 u8 port_guid[0x1]; 6577 u8 min_inline[0x1]; 6578 u8 mtu[0x1]; 6579 u8 change_event[0x1]; 6580 u8 promisc[0x1]; 6581 u8 permanent_address[0x1]; 6582 u8 addresses_list[0x1]; 6583 u8 roce_en[0x1]; 6584 u8 reserved_at_1f[0x1]; 6585 }; 6586 6587 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6588 u8 opcode[0x10]; 6589 u8 reserved_at_10[0x10]; 6590 6591 u8 reserved_at_20[0x10]; 6592 u8 op_mod[0x10]; 6593 6594 u8 other_vport[0x1]; 6595 u8 reserved_at_41[0xf]; 6596 u8 vport_number[0x10]; 6597 6598 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6599 6600 u8 reserved_at_80[0x780]; 6601 6602 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6603 }; 6604 6605 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6606 u8 status[0x8]; 6607 u8 reserved_at_8[0x18]; 6608 6609 u8 syndrome[0x20]; 6610 6611 u8 reserved_at_40[0x40]; 6612 }; 6613 6614 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6615 u8 opcode[0x10]; 6616 u8 reserved_at_10[0x10]; 6617 6618 u8 reserved_at_20[0x10]; 6619 u8 op_mod[0x10]; 6620 6621 u8 other_vport[0x1]; 6622 u8 reserved_at_41[0xb]; 6623 u8 port_num[0x4]; 6624 u8 vport_number[0x10]; 6625 6626 u8 reserved_at_60[0x20]; 6627 6628 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6629 }; 6630 6631 struct mlx5_ifc_modify_cq_out_bits { 6632 u8 status[0x8]; 6633 u8 reserved_at_8[0x18]; 6634 6635 u8 syndrome[0x20]; 6636 6637 u8 reserved_at_40[0x40]; 6638 }; 6639 6640 enum { 6641 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6642 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6643 }; 6644 6645 struct mlx5_ifc_modify_cq_in_bits { 6646 u8 opcode[0x10]; 6647 u8 uid[0x10]; 6648 6649 u8 reserved_at_20[0x10]; 6650 u8 op_mod[0x10]; 6651 6652 u8 reserved_at_40[0x8]; 6653 u8 cqn[0x18]; 6654 6655 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6656 6657 struct mlx5_ifc_cqc_bits cq_context; 6658 6659 u8 reserved_at_280[0x60]; 6660 6661 u8 cq_umem_valid[0x1]; 6662 u8 reserved_at_2e1[0x1f]; 6663 6664 u8 reserved_at_300[0x580]; 6665 6666 u8 pas[][0x40]; 6667 }; 6668 6669 struct mlx5_ifc_modify_cong_status_out_bits { 6670 u8 status[0x8]; 6671 u8 reserved_at_8[0x18]; 6672 6673 u8 syndrome[0x20]; 6674 6675 u8 reserved_at_40[0x40]; 6676 }; 6677 6678 struct mlx5_ifc_modify_cong_status_in_bits { 6679 u8 opcode[0x10]; 6680 u8 reserved_at_10[0x10]; 6681 6682 u8 reserved_at_20[0x10]; 6683 u8 op_mod[0x10]; 6684 6685 u8 reserved_at_40[0x18]; 6686 u8 priority[0x4]; 6687 u8 cong_protocol[0x4]; 6688 6689 u8 enable[0x1]; 6690 u8 tag_enable[0x1]; 6691 u8 reserved_at_62[0x1e]; 6692 }; 6693 6694 struct mlx5_ifc_modify_cong_params_out_bits { 6695 u8 status[0x8]; 6696 u8 reserved_at_8[0x18]; 6697 6698 u8 syndrome[0x20]; 6699 6700 u8 reserved_at_40[0x40]; 6701 }; 6702 6703 struct mlx5_ifc_modify_cong_params_in_bits { 6704 u8 opcode[0x10]; 6705 u8 reserved_at_10[0x10]; 6706 6707 u8 reserved_at_20[0x10]; 6708 u8 op_mod[0x10]; 6709 6710 u8 reserved_at_40[0x1c]; 6711 u8 cong_protocol[0x4]; 6712 6713 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6714 6715 u8 reserved_at_80[0x80]; 6716 6717 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6718 }; 6719 6720 struct mlx5_ifc_manage_pages_out_bits { 6721 u8 status[0x8]; 6722 u8 reserved_at_8[0x18]; 6723 6724 u8 syndrome[0x20]; 6725 6726 u8 output_num_entries[0x20]; 6727 6728 u8 reserved_at_60[0x20]; 6729 6730 u8 pas[][0x40]; 6731 }; 6732 6733 enum { 6734 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6735 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6736 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6737 }; 6738 6739 struct mlx5_ifc_manage_pages_in_bits { 6740 u8 opcode[0x10]; 6741 u8 reserved_at_10[0x10]; 6742 6743 u8 reserved_at_20[0x10]; 6744 u8 op_mod[0x10]; 6745 6746 u8 embedded_cpu_function[0x1]; 6747 u8 reserved_at_41[0xf]; 6748 u8 function_id[0x10]; 6749 6750 u8 input_num_entries[0x20]; 6751 6752 u8 pas[][0x40]; 6753 }; 6754 6755 struct mlx5_ifc_mad_ifc_out_bits { 6756 u8 status[0x8]; 6757 u8 reserved_at_8[0x18]; 6758 6759 u8 syndrome[0x20]; 6760 6761 u8 reserved_at_40[0x40]; 6762 6763 u8 response_mad_packet[256][0x8]; 6764 }; 6765 6766 struct mlx5_ifc_mad_ifc_in_bits { 6767 u8 opcode[0x10]; 6768 u8 reserved_at_10[0x10]; 6769 6770 u8 reserved_at_20[0x10]; 6771 u8 op_mod[0x10]; 6772 6773 u8 remote_lid[0x10]; 6774 u8 reserved_at_50[0x8]; 6775 u8 port[0x8]; 6776 6777 u8 reserved_at_60[0x20]; 6778 6779 u8 mad[256][0x8]; 6780 }; 6781 6782 struct mlx5_ifc_init_hca_out_bits { 6783 u8 status[0x8]; 6784 u8 reserved_at_8[0x18]; 6785 6786 u8 syndrome[0x20]; 6787 6788 u8 reserved_at_40[0x40]; 6789 }; 6790 6791 struct mlx5_ifc_init_hca_in_bits { 6792 u8 opcode[0x10]; 6793 u8 reserved_at_10[0x10]; 6794 6795 u8 reserved_at_20[0x10]; 6796 u8 op_mod[0x10]; 6797 6798 u8 reserved_at_40[0x40]; 6799 u8 sw_owner_id[4][0x20]; 6800 }; 6801 6802 struct mlx5_ifc_init2rtr_qp_out_bits { 6803 u8 status[0x8]; 6804 u8 reserved_at_8[0x18]; 6805 6806 u8 syndrome[0x20]; 6807 6808 u8 reserved_at_40[0x20]; 6809 u8 ece[0x20]; 6810 }; 6811 6812 struct mlx5_ifc_init2rtr_qp_in_bits { 6813 u8 opcode[0x10]; 6814 u8 uid[0x10]; 6815 6816 u8 reserved_at_20[0x10]; 6817 u8 op_mod[0x10]; 6818 6819 u8 reserved_at_40[0x8]; 6820 u8 qpn[0x18]; 6821 6822 u8 reserved_at_60[0x20]; 6823 6824 u8 opt_param_mask[0x20]; 6825 6826 u8 ece[0x20]; 6827 6828 struct mlx5_ifc_qpc_bits qpc; 6829 6830 u8 reserved_at_800[0x80]; 6831 }; 6832 6833 struct mlx5_ifc_init2init_qp_out_bits { 6834 u8 status[0x8]; 6835 u8 reserved_at_8[0x18]; 6836 6837 u8 syndrome[0x20]; 6838 6839 u8 reserved_at_40[0x20]; 6840 u8 ece[0x20]; 6841 }; 6842 6843 struct mlx5_ifc_init2init_qp_in_bits { 6844 u8 opcode[0x10]; 6845 u8 uid[0x10]; 6846 6847 u8 reserved_at_20[0x10]; 6848 u8 op_mod[0x10]; 6849 6850 u8 reserved_at_40[0x8]; 6851 u8 qpn[0x18]; 6852 6853 u8 reserved_at_60[0x20]; 6854 6855 u8 opt_param_mask[0x20]; 6856 6857 u8 ece[0x20]; 6858 6859 struct mlx5_ifc_qpc_bits qpc; 6860 6861 u8 reserved_at_800[0x80]; 6862 }; 6863 6864 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6865 u8 status[0x8]; 6866 u8 reserved_at_8[0x18]; 6867 6868 u8 syndrome[0x20]; 6869 6870 u8 reserved_at_40[0x40]; 6871 6872 u8 packet_headers_log[128][0x8]; 6873 6874 u8 packet_syndrome[64][0x8]; 6875 }; 6876 6877 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6878 u8 opcode[0x10]; 6879 u8 reserved_at_10[0x10]; 6880 6881 u8 reserved_at_20[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 reserved_at_40[0x40]; 6885 }; 6886 6887 struct mlx5_ifc_gen_eqe_in_bits { 6888 u8 opcode[0x10]; 6889 u8 reserved_at_10[0x10]; 6890 6891 u8 reserved_at_20[0x10]; 6892 u8 op_mod[0x10]; 6893 6894 u8 reserved_at_40[0x18]; 6895 u8 eq_number[0x8]; 6896 6897 u8 reserved_at_60[0x20]; 6898 6899 u8 eqe[64][0x8]; 6900 }; 6901 6902 struct mlx5_ifc_gen_eq_out_bits { 6903 u8 status[0x8]; 6904 u8 reserved_at_8[0x18]; 6905 6906 u8 syndrome[0x20]; 6907 6908 u8 reserved_at_40[0x40]; 6909 }; 6910 6911 struct mlx5_ifc_enable_hca_out_bits { 6912 u8 status[0x8]; 6913 u8 reserved_at_8[0x18]; 6914 6915 u8 syndrome[0x20]; 6916 6917 u8 reserved_at_40[0x20]; 6918 }; 6919 6920 struct mlx5_ifc_enable_hca_in_bits { 6921 u8 opcode[0x10]; 6922 u8 reserved_at_10[0x10]; 6923 6924 u8 reserved_at_20[0x10]; 6925 u8 op_mod[0x10]; 6926 6927 u8 embedded_cpu_function[0x1]; 6928 u8 reserved_at_41[0xf]; 6929 u8 function_id[0x10]; 6930 6931 u8 reserved_at_60[0x20]; 6932 }; 6933 6934 struct mlx5_ifc_drain_dct_out_bits { 6935 u8 status[0x8]; 6936 u8 reserved_at_8[0x18]; 6937 6938 u8 syndrome[0x20]; 6939 6940 u8 reserved_at_40[0x40]; 6941 }; 6942 6943 struct mlx5_ifc_drain_dct_in_bits { 6944 u8 opcode[0x10]; 6945 u8 uid[0x10]; 6946 6947 u8 reserved_at_20[0x10]; 6948 u8 op_mod[0x10]; 6949 6950 u8 reserved_at_40[0x8]; 6951 u8 dctn[0x18]; 6952 6953 u8 reserved_at_60[0x20]; 6954 }; 6955 6956 struct mlx5_ifc_disable_hca_out_bits { 6957 u8 status[0x8]; 6958 u8 reserved_at_8[0x18]; 6959 6960 u8 syndrome[0x20]; 6961 6962 u8 reserved_at_40[0x20]; 6963 }; 6964 6965 struct mlx5_ifc_disable_hca_in_bits { 6966 u8 opcode[0x10]; 6967 u8 reserved_at_10[0x10]; 6968 6969 u8 reserved_at_20[0x10]; 6970 u8 op_mod[0x10]; 6971 6972 u8 embedded_cpu_function[0x1]; 6973 u8 reserved_at_41[0xf]; 6974 u8 function_id[0x10]; 6975 6976 u8 reserved_at_60[0x20]; 6977 }; 6978 6979 struct mlx5_ifc_detach_from_mcg_out_bits { 6980 u8 status[0x8]; 6981 u8 reserved_at_8[0x18]; 6982 6983 u8 syndrome[0x20]; 6984 6985 u8 reserved_at_40[0x40]; 6986 }; 6987 6988 struct mlx5_ifc_detach_from_mcg_in_bits { 6989 u8 opcode[0x10]; 6990 u8 uid[0x10]; 6991 6992 u8 reserved_at_20[0x10]; 6993 u8 op_mod[0x10]; 6994 6995 u8 reserved_at_40[0x8]; 6996 u8 qpn[0x18]; 6997 6998 u8 reserved_at_60[0x20]; 6999 7000 u8 multicast_gid[16][0x8]; 7001 }; 7002 7003 struct mlx5_ifc_destroy_xrq_out_bits { 7004 u8 status[0x8]; 7005 u8 reserved_at_8[0x18]; 7006 7007 u8 syndrome[0x20]; 7008 7009 u8 reserved_at_40[0x40]; 7010 }; 7011 7012 struct mlx5_ifc_destroy_xrq_in_bits { 7013 u8 opcode[0x10]; 7014 u8 uid[0x10]; 7015 7016 u8 reserved_at_20[0x10]; 7017 u8 op_mod[0x10]; 7018 7019 u8 reserved_at_40[0x8]; 7020 u8 xrqn[0x18]; 7021 7022 u8 reserved_at_60[0x20]; 7023 }; 7024 7025 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7026 u8 status[0x8]; 7027 u8 reserved_at_8[0x18]; 7028 7029 u8 syndrome[0x20]; 7030 7031 u8 reserved_at_40[0x40]; 7032 }; 7033 7034 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7035 u8 opcode[0x10]; 7036 u8 uid[0x10]; 7037 7038 u8 reserved_at_20[0x10]; 7039 u8 op_mod[0x10]; 7040 7041 u8 reserved_at_40[0x8]; 7042 u8 xrc_srqn[0x18]; 7043 7044 u8 reserved_at_60[0x20]; 7045 }; 7046 7047 struct mlx5_ifc_destroy_tis_out_bits { 7048 u8 status[0x8]; 7049 u8 reserved_at_8[0x18]; 7050 7051 u8 syndrome[0x20]; 7052 7053 u8 reserved_at_40[0x40]; 7054 }; 7055 7056 struct mlx5_ifc_destroy_tis_in_bits { 7057 u8 opcode[0x10]; 7058 u8 uid[0x10]; 7059 7060 u8 reserved_at_20[0x10]; 7061 u8 op_mod[0x10]; 7062 7063 u8 reserved_at_40[0x8]; 7064 u8 tisn[0x18]; 7065 7066 u8 reserved_at_60[0x20]; 7067 }; 7068 7069 struct mlx5_ifc_destroy_tir_out_bits { 7070 u8 status[0x8]; 7071 u8 reserved_at_8[0x18]; 7072 7073 u8 syndrome[0x20]; 7074 7075 u8 reserved_at_40[0x40]; 7076 }; 7077 7078 struct mlx5_ifc_destroy_tir_in_bits { 7079 u8 opcode[0x10]; 7080 u8 uid[0x10]; 7081 7082 u8 reserved_at_20[0x10]; 7083 u8 op_mod[0x10]; 7084 7085 u8 reserved_at_40[0x8]; 7086 u8 tirn[0x18]; 7087 7088 u8 reserved_at_60[0x20]; 7089 }; 7090 7091 struct mlx5_ifc_destroy_srq_out_bits { 7092 u8 status[0x8]; 7093 u8 reserved_at_8[0x18]; 7094 7095 u8 syndrome[0x20]; 7096 7097 u8 reserved_at_40[0x40]; 7098 }; 7099 7100 struct mlx5_ifc_destroy_srq_in_bits { 7101 u8 opcode[0x10]; 7102 u8 uid[0x10]; 7103 7104 u8 reserved_at_20[0x10]; 7105 u8 op_mod[0x10]; 7106 7107 u8 reserved_at_40[0x8]; 7108 u8 srqn[0x18]; 7109 7110 u8 reserved_at_60[0x20]; 7111 }; 7112 7113 struct mlx5_ifc_destroy_sq_out_bits { 7114 u8 status[0x8]; 7115 u8 reserved_at_8[0x18]; 7116 7117 u8 syndrome[0x20]; 7118 7119 u8 reserved_at_40[0x40]; 7120 }; 7121 7122 struct mlx5_ifc_destroy_sq_in_bits { 7123 u8 opcode[0x10]; 7124 u8 uid[0x10]; 7125 7126 u8 reserved_at_20[0x10]; 7127 u8 op_mod[0x10]; 7128 7129 u8 reserved_at_40[0x8]; 7130 u8 sqn[0x18]; 7131 7132 u8 reserved_at_60[0x20]; 7133 }; 7134 7135 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7136 u8 status[0x8]; 7137 u8 reserved_at_8[0x18]; 7138 7139 u8 syndrome[0x20]; 7140 7141 u8 reserved_at_40[0x1c0]; 7142 }; 7143 7144 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7145 u8 opcode[0x10]; 7146 u8 reserved_at_10[0x10]; 7147 7148 u8 reserved_at_20[0x10]; 7149 u8 op_mod[0x10]; 7150 7151 u8 scheduling_hierarchy[0x8]; 7152 u8 reserved_at_48[0x18]; 7153 7154 u8 scheduling_element_id[0x20]; 7155 7156 u8 reserved_at_80[0x180]; 7157 }; 7158 7159 struct mlx5_ifc_destroy_rqt_out_bits { 7160 u8 status[0x8]; 7161 u8 reserved_at_8[0x18]; 7162 7163 u8 syndrome[0x20]; 7164 7165 u8 reserved_at_40[0x40]; 7166 }; 7167 7168 struct mlx5_ifc_destroy_rqt_in_bits { 7169 u8 opcode[0x10]; 7170 u8 uid[0x10]; 7171 7172 u8 reserved_at_20[0x10]; 7173 u8 op_mod[0x10]; 7174 7175 u8 reserved_at_40[0x8]; 7176 u8 rqtn[0x18]; 7177 7178 u8 reserved_at_60[0x20]; 7179 }; 7180 7181 struct mlx5_ifc_destroy_rq_out_bits { 7182 u8 status[0x8]; 7183 u8 reserved_at_8[0x18]; 7184 7185 u8 syndrome[0x20]; 7186 7187 u8 reserved_at_40[0x40]; 7188 }; 7189 7190 struct mlx5_ifc_destroy_rq_in_bits { 7191 u8 opcode[0x10]; 7192 u8 uid[0x10]; 7193 7194 u8 reserved_at_20[0x10]; 7195 u8 op_mod[0x10]; 7196 7197 u8 reserved_at_40[0x8]; 7198 u8 rqn[0x18]; 7199 7200 u8 reserved_at_60[0x20]; 7201 }; 7202 7203 struct mlx5_ifc_set_delay_drop_params_in_bits { 7204 u8 opcode[0x10]; 7205 u8 reserved_at_10[0x10]; 7206 7207 u8 reserved_at_20[0x10]; 7208 u8 op_mod[0x10]; 7209 7210 u8 reserved_at_40[0x20]; 7211 7212 u8 reserved_at_60[0x10]; 7213 u8 delay_drop_timeout[0x10]; 7214 }; 7215 7216 struct mlx5_ifc_set_delay_drop_params_out_bits { 7217 u8 status[0x8]; 7218 u8 reserved_at_8[0x18]; 7219 7220 u8 syndrome[0x20]; 7221 7222 u8 reserved_at_40[0x40]; 7223 }; 7224 7225 struct mlx5_ifc_destroy_rmp_out_bits { 7226 u8 status[0x8]; 7227 u8 reserved_at_8[0x18]; 7228 7229 u8 syndrome[0x20]; 7230 7231 u8 reserved_at_40[0x40]; 7232 }; 7233 7234 struct mlx5_ifc_destroy_rmp_in_bits { 7235 u8 opcode[0x10]; 7236 u8 uid[0x10]; 7237 7238 u8 reserved_at_20[0x10]; 7239 u8 op_mod[0x10]; 7240 7241 u8 reserved_at_40[0x8]; 7242 u8 rmpn[0x18]; 7243 7244 u8 reserved_at_60[0x20]; 7245 }; 7246 7247 struct mlx5_ifc_destroy_qp_out_bits { 7248 u8 status[0x8]; 7249 u8 reserved_at_8[0x18]; 7250 7251 u8 syndrome[0x20]; 7252 7253 u8 reserved_at_40[0x40]; 7254 }; 7255 7256 struct mlx5_ifc_destroy_qp_in_bits { 7257 u8 opcode[0x10]; 7258 u8 uid[0x10]; 7259 7260 u8 reserved_at_20[0x10]; 7261 u8 op_mod[0x10]; 7262 7263 u8 reserved_at_40[0x8]; 7264 u8 qpn[0x18]; 7265 7266 u8 reserved_at_60[0x20]; 7267 }; 7268 7269 struct mlx5_ifc_destroy_psv_out_bits { 7270 u8 status[0x8]; 7271 u8 reserved_at_8[0x18]; 7272 7273 u8 syndrome[0x20]; 7274 7275 u8 reserved_at_40[0x40]; 7276 }; 7277 7278 struct mlx5_ifc_destroy_psv_in_bits { 7279 u8 opcode[0x10]; 7280 u8 reserved_at_10[0x10]; 7281 7282 u8 reserved_at_20[0x10]; 7283 u8 op_mod[0x10]; 7284 7285 u8 reserved_at_40[0x8]; 7286 u8 psvn[0x18]; 7287 7288 u8 reserved_at_60[0x20]; 7289 }; 7290 7291 struct mlx5_ifc_destroy_mkey_out_bits { 7292 u8 status[0x8]; 7293 u8 reserved_at_8[0x18]; 7294 7295 u8 syndrome[0x20]; 7296 7297 u8 reserved_at_40[0x40]; 7298 }; 7299 7300 struct mlx5_ifc_destroy_mkey_in_bits { 7301 u8 opcode[0x10]; 7302 u8 uid[0x10]; 7303 7304 u8 reserved_at_20[0x10]; 7305 u8 op_mod[0x10]; 7306 7307 u8 reserved_at_40[0x8]; 7308 u8 mkey_index[0x18]; 7309 7310 u8 reserved_at_60[0x20]; 7311 }; 7312 7313 struct mlx5_ifc_destroy_flow_table_out_bits { 7314 u8 status[0x8]; 7315 u8 reserved_at_8[0x18]; 7316 7317 u8 syndrome[0x20]; 7318 7319 u8 reserved_at_40[0x40]; 7320 }; 7321 7322 struct mlx5_ifc_destroy_flow_table_in_bits { 7323 u8 opcode[0x10]; 7324 u8 reserved_at_10[0x10]; 7325 7326 u8 reserved_at_20[0x10]; 7327 u8 op_mod[0x10]; 7328 7329 u8 other_vport[0x1]; 7330 u8 reserved_at_41[0xf]; 7331 u8 vport_number[0x10]; 7332 7333 u8 reserved_at_60[0x20]; 7334 7335 u8 table_type[0x8]; 7336 u8 reserved_at_88[0x18]; 7337 7338 u8 reserved_at_a0[0x8]; 7339 u8 table_id[0x18]; 7340 7341 u8 reserved_at_c0[0x140]; 7342 }; 7343 7344 struct mlx5_ifc_destroy_flow_group_out_bits { 7345 u8 status[0x8]; 7346 u8 reserved_at_8[0x18]; 7347 7348 u8 syndrome[0x20]; 7349 7350 u8 reserved_at_40[0x40]; 7351 }; 7352 7353 struct mlx5_ifc_destroy_flow_group_in_bits { 7354 u8 opcode[0x10]; 7355 u8 reserved_at_10[0x10]; 7356 7357 u8 reserved_at_20[0x10]; 7358 u8 op_mod[0x10]; 7359 7360 u8 other_vport[0x1]; 7361 u8 reserved_at_41[0xf]; 7362 u8 vport_number[0x10]; 7363 7364 u8 reserved_at_60[0x20]; 7365 7366 u8 table_type[0x8]; 7367 u8 reserved_at_88[0x18]; 7368 7369 u8 reserved_at_a0[0x8]; 7370 u8 table_id[0x18]; 7371 7372 u8 group_id[0x20]; 7373 7374 u8 reserved_at_e0[0x120]; 7375 }; 7376 7377 struct mlx5_ifc_destroy_eq_out_bits { 7378 u8 status[0x8]; 7379 u8 reserved_at_8[0x18]; 7380 7381 u8 syndrome[0x20]; 7382 7383 u8 reserved_at_40[0x40]; 7384 }; 7385 7386 struct mlx5_ifc_destroy_eq_in_bits { 7387 u8 opcode[0x10]; 7388 u8 reserved_at_10[0x10]; 7389 7390 u8 reserved_at_20[0x10]; 7391 u8 op_mod[0x10]; 7392 7393 u8 reserved_at_40[0x18]; 7394 u8 eq_number[0x8]; 7395 7396 u8 reserved_at_60[0x20]; 7397 }; 7398 7399 struct mlx5_ifc_destroy_dct_out_bits { 7400 u8 status[0x8]; 7401 u8 reserved_at_8[0x18]; 7402 7403 u8 syndrome[0x20]; 7404 7405 u8 reserved_at_40[0x40]; 7406 }; 7407 7408 struct mlx5_ifc_destroy_dct_in_bits { 7409 u8 opcode[0x10]; 7410 u8 uid[0x10]; 7411 7412 u8 reserved_at_20[0x10]; 7413 u8 op_mod[0x10]; 7414 7415 u8 reserved_at_40[0x8]; 7416 u8 dctn[0x18]; 7417 7418 u8 reserved_at_60[0x20]; 7419 }; 7420 7421 struct mlx5_ifc_destroy_cq_out_bits { 7422 u8 status[0x8]; 7423 u8 reserved_at_8[0x18]; 7424 7425 u8 syndrome[0x20]; 7426 7427 u8 reserved_at_40[0x40]; 7428 }; 7429 7430 struct mlx5_ifc_destroy_cq_in_bits { 7431 u8 opcode[0x10]; 7432 u8 uid[0x10]; 7433 7434 u8 reserved_at_20[0x10]; 7435 u8 op_mod[0x10]; 7436 7437 u8 reserved_at_40[0x8]; 7438 u8 cqn[0x18]; 7439 7440 u8 reserved_at_60[0x20]; 7441 }; 7442 7443 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7444 u8 status[0x8]; 7445 u8 reserved_at_8[0x18]; 7446 7447 u8 syndrome[0x20]; 7448 7449 u8 reserved_at_40[0x40]; 7450 }; 7451 7452 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7453 u8 opcode[0x10]; 7454 u8 reserved_at_10[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_at_40[0x20]; 7460 7461 u8 reserved_at_60[0x10]; 7462 u8 vxlan_udp_port[0x10]; 7463 }; 7464 7465 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7466 u8 status[0x8]; 7467 u8 reserved_at_8[0x18]; 7468 7469 u8 syndrome[0x20]; 7470 7471 u8 reserved_at_40[0x40]; 7472 }; 7473 7474 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7475 u8 opcode[0x10]; 7476 u8 reserved_at_10[0x10]; 7477 7478 u8 reserved_at_20[0x10]; 7479 u8 op_mod[0x10]; 7480 7481 u8 reserved_at_40[0x60]; 7482 7483 u8 reserved_at_a0[0x8]; 7484 u8 table_index[0x18]; 7485 7486 u8 reserved_at_c0[0x140]; 7487 }; 7488 7489 struct mlx5_ifc_delete_fte_out_bits { 7490 u8 status[0x8]; 7491 u8 reserved_at_8[0x18]; 7492 7493 u8 syndrome[0x20]; 7494 7495 u8 reserved_at_40[0x40]; 7496 }; 7497 7498 struct mlx5_ifc_delete_fte_in_bits { 7499 u8 opcode[0x10]; 7500 u8 reserved_at_10[0x10]; 7501 7502 u8 reserved_at_20[0x10]; 7503 u8 op_mod[0x10]; 7504 7505 u8 other_vport[0x1]; 7506 u8 reserved_at_41[0xf]; 7507 u8 vport_number[0x10]; 7508 7509 u8 reserved_at_60[0x20]; 7510 7511 u8 table_type[0x8]; 7512 u8 reserved_at_88[0x18]; 7513 7514 u8 reserved_at_a0[0x8]; 7515 u8 table_id[0x18]; 7516 7517 u8 reserved_at_c0[0x40]; 7518 7519 u8 flow_index[0x20]; 7520 7521 u8 reserved_at_120[0xe0]; 7522 }; 7523 7524 struct mlx5_ifc_dealloc_xrcd_out_bits { 7525 u8 status[0x8]; 7526 u8 reserved_at_8[0x18]; 7527 7528 u8 syndrome[0x20]; 7529 7530 u8 reserved_at_40[0x40]; 7531 }; 7532 7533 struct mlx5_ifc_dealloc_xrcd_in_bits { 7534 u8 opcode[0x10]; 7535 u8 uid[0x10]; 7536 7537 u8 reserved_at_20[0x10]; 7538 u8 op_mod[0x10]; 7539 7540 u8 reserved_at_40[0x8]; 7541 u8 xrcd[0x18]; 7542 7543 u8 reserved_at_60[0x20]; 7544 }; 7545 7546 struct mlx5_ifc_dealloc_uar_out_bits { 7547 u8 status[0x8]; 7548 u8 reserved_at_8[0x18]; 7549 7550 u8 syndrome[0x20]; 7551 7552 u8 reserved_at_40[0x40]; 7553 }; 7554 7555 struct mlx5_ifc_dealloc_uar_in_bits { 7556 u8 opcode[0x10]; 7557 u8 reserved_at_10[0x10]; 7558 7559 u8 reserved_at_20[0x10]; 7560 u8 op_mod[0x10]; 7561 7562 u8 reserved_at_40[0x8]; 7563 u8 uar[0x18]; 7564 7565 u8 reserved_at_60[0x20]; 7566 }; 7567 7568 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7569 u8 status[0x8]; 7570 u8 reserved_at_8[0x18]; 7571 7572 u8 syndrome[0x20]; 7573 7574 u8 reserved_at_40[0x40]; 7575 }; 7576 7577 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7578 u8 opcode[0x10]; 7579 u8 uid[0x10]; 7580 7581 u8 reserved_at_20[0x10]; 7582 u8 op_mod[0x10]; 7583 7584 u8 reserved_at_40[0x8]; 7585 u8 transport_domain[0x18]; 7586 7587 u8 reserved_at_60[0x20]; 7588 }; 7589 7590 struct mlx5_ifc_dealloc_q_counter_out_bits { 7591 u8 status[0x8]; 7592 u8 reserved_at_8[0x18]; 7593 7594 u8 syndrome[0x20]; 7595 7596 u8 reserved_at_40[0x40]; 7597 }; 7598 7599 struct mlx5_ifc_dealloc_q_counter_in_bits { 7600 u8 opcode[0x10]; 7601 u8 reserved_at_10[0x10]; 7602 7603 u8 reserved_at_20[0x10]; 7604 u8 op_mod[0x10]; 7605 7606 u8 reserved_at_40[0x18]; 7607 u8 counter_set_id[0x8]; 7608 7609 u8 reserved_at_60[0x20]; 7610 }; 7611 7612 struct mlx5_ifc_dealloc_pd_out_bits { 7613 u8 status[0x8]; 7614 u8 reserved_at_8[0x18]; 7615 7616 u8 syndrome[0x20]; 7617 7618 u8 reserved_at_40[0x40]; 7619 }; 7620 7621 struct mlx5_ifc_dealloc_pd_in_bits { 7622 u8 opcode[0x10]; 7623 u8 uid[0x10]; 7624 7625 u8 reserved_at_20[0x10]; 7626 u8 op_mod[0x10]; 7627 7628 u8 reserved_at_40[0x8]; 7629 u8 pd[0x18]; 7630 7631 u8 reserved_at_60[0x20]; 7632 }; 7633 7634 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7635 u8 status[0x8]; 7636 u8 reserved_at_8[0x18]; 7637 7638 u8 syndrome[0x20]; 7639 7640 u8 reserved_at_40[0x40]; 7641 }; 7642 7643 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7644 u8 opcode[0x10]; 7645 u8 reserved_at_10[0x10]; 7646 7647 u8 reserved_at_20[0x10]; 7648 u8 op_mod[0x10]; 7649 7650 u8 flow_counter_id[0x20]; 7651 7652 u8 reserved_at_60[0x20]; 7653 }; 7654 7655 struct mlx5_ifc_create_xrq_out_bits { 7656 u8 status[0x8]; 7657 u8 reserved_at_8[0x18]; 7658 7659 u8 syndrome[0x20]; 7660 7661 u8 reserved_at_40[0x8]; 7662 u8 xrqn[0x18]; 7663 7664 u8 reserved_at_60[0x20]; 7665 }; 7666 7667 struct mlx5_ifc_create_xrq_in_bits { 7668 u8 opcode[0x10]; 7669 u8 uid[0x10]; 7670 7671 u8 reserved_at_20[0x10]; 7672 u8 op_mod[0x10]; 7673 7674 u8 reserved_at_40[0x40]; 7675 7676 struct mlx5_ifc_xrqc_bits xrq_context; 7677 }; 7678 7679 struct mlx5_ifc_create_xrc_srq_out_bits { 7680 u8 status[0x8]; 7681 u8 reserved_at_8[0x18]; 7682 7683 u8 syndrome[0x20]; 7684 7685 u8 reserved_at_40[0x8]; 7686 u8 xrc_srqn[0x18]; 7687 7688 u8 reserved_at_60[0x20]; 7689 }; 7690 7691 struct mlx5_ifc_create_xrc_srq_in_bits { 7692 u8 opcode[0x10]; 7693 u8 uid[0x10]; 7694 7695 u8 reserved_at_20[0x10]; 7696 u8 op_mod[0x10]; 7697 7698 u8 reserved_at_40[0x40]; 7699 7700 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7701 7702 u8 reserved_at_280[0x60]; 7703 7704 u8 xrc_srq_umem_valid[0x1]; 7705 u8 reserved_at_2e1[0x1f]; 7706 7707 u8 reserved_at_300[0x580]; 7708 7709 u8 pas[][0x40]; 7710 }; 7711 7712 struct mlx5_ifc_create_tis_out_bits { 7713 u8 status[0x8]; 7714 u8 reserved_at_8[0x18]; 7715 7716 u8 syndrome[0x20]; 7717 7718 u8 reserved_at_40[0x8]; 7719 u8 tisn[0x18]; 7720 7721 u8 reserved_at_60[0x20]; 7722 }; 7723 7724 struct mlx5_ifc_create_tis_in_bits { 7725 u8 opcode[0x10]; 7726 u8 uid[0x10]; 7727 7728 u8 reserved_at_20[0x10]; 7729 u8 op_mod[0x10]; 7730 7731 u8 reserved_at_40[0xc0]; 7732 7733 struct mlx5_ifc_tisc_bits ctx; 7734 }; 7735 7736 struct mlx5_ifc_create_tir_out_bits { 7737 u8 status[0x8]; 7738 u8 icm_address_63_40[0x18]; 7739 7740 u8 syndrome[0x20]; 7741 7742 u8 icm_address_39_32[0x8]; 7743 u8 tirn[0x18]; 7744 7745 u8 icm_address_31_0[0x20]; 7746 }; 7747 7748 struct mlx5_ifc_create_tir_in_bits { 7749 u8 opcode[0x10]; 7750 u8 uid[0x10]; 7751 7752 u8 reserved_at_20[0x10]; 7753 u8 op_mod[0x10]; 7754 7755 u8 reserved_at_40[0xc0]; 7756 7757 struct mlx5_ifc_tirc_bits ctx; 7758 }; 7759 7760 struct mlx5_ifc_create_srq_out_bits { 7761 u8 status[0x8]; 7762 u8 reserved_at_8[0x18]; 7763 7764 u8 syndrome[0x20]; 7765 7766 u8 reserved_at_40[0x8]; 7767 u8 srqn[0x18]; 7768 7769 u8 reserved_at_60[0x20]; 7770 }; 7771 7772 struct mlx5_ifc_create_srq_in_bits { 7773 u8 opcode[0x10]; 7774 u8 uid[0x10]; 7775 7776 u8 reserved_at_20[0x10]; 7777 u8 op_mod[0x10]; 7778 7779 u8 reserved_at_40[0x40]; 7780 7781 struct mlx5_ifc_srqc_bits srq_context_entry; 7782 7783 u8 reserved_at_280[0x600]; 7784 7785 u8 pas[][0x40]; 7786 }; 7787 7788 struct mlx5_ifc_create_sq_out_bits { 7789 u8 status[0x8]; 7790 u8 reserved_at_8[0x18]; 7791 7792 u8 syndrome[0x20]; 7793 7794 u8 reserved_at_40[0x8]; 7795 u8 sqn[0x18]; 7796 7797 u8 reserved_at_60[0x20]; 7798 }; 7799 7800 struct mlx5_ifc_create_sq_in_bits { 7801 u8 opcode[0x10]; 7802 u8 uid[0x10]; 7803 7804 u8 reserved_at_20[0x10]; 7805 u8 op_mod[0x10]; 7806 7807 u8 reserved_at_40[0xc0]; 7808 7809 struct mlx5_ifc_sqc_bits ctx; 7810 }; 7811 7812 struct mlx5_ifc_create_scheduling_element_out_bits { 7813 u8 status[0x8]; 7814 u8 reserved_at_8[0x18]; 7815 7816 u8 syndrome[0x20]; 7817 7818 u8 reserved_at_40[0x40]; 7819 7820 u8 scheduling_element_id[0x20]; 7821 7822 u8 reserved_at_a0[0x160]; 7823 }; 7824 7825 struct mlx5_ifc_create_scheduling_element_in_bits { 7826 u8 opcode[0x10]; 7827 u8 reserved_at_10[0x10]; 7828 7829 u8 reserved_at_20[0x10]; 7830 u8 op_mod[0x10]; 7831 7832 u8 scheduling_hierarchy[0x8]; 7833 u8 reserved_at_48[0x18]; 7834 7835 u8 reserved_at_60[0xa0]; 7836 7837 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7838 7839 u8 reserved_at_300[0x100]; 7840 }; 7841 7842 struct mlx5_ifc_create_rqt_out_bits { 7843 u8 status[0x8]; 7844 u8 reserved_at_8[0x18]; 7845 7846 u8 syndrome[0x20]; 7847 7848 u8 reserved_at_40[0x8]; 7849 u8 rqtn[0x18]; 7850 7851 u8 reserved_at_60[0x20]; 7852 }; 7853 7854 struct mlx5_ifc_create_rqt_in_bits { 7855 u8 opcode[0x10]; 7856 u8 uid[0x10]; 7857 7858 u8 reserved_at_20[0x10]; 7859 u8 op_mod[0x10]; 7860 7861 u8 reserved_at_40[0xc0]; 7862 7863 struct mlx5_ifc_rqtc_bits rqt_context; 7864 }; 7865 7866 struct mlx5_ifc_create_rq_out_bits { 7867 u8 status[0x8]; 7868 u8 reserved_at_8[0x18]; 7869 7870 u8 syndrome[0x20]; 7871 7872 u8 reserved_at_40[0x8]; 7873 u8 rqn[0x18]; 7874 7875 u8 reserved_at_60[0x20]; 7876 }; 7877 7878 struct mlx5_ifc_create_rq_in_bits { 7879 u8 opcode[0x10]; 7880 u8 uid[0x10]; 7881 7882 u8 reserved_at_20[0x10]; 7883 u8 op_mod[0x10]; 7884 7885 u8 reserved_at_40[0xc0]; 7886 7887 struct mlx5_ifc_rqc_bits ctx; 7888 }; 7889 7890 struct mlx5_ifc_create_rmp_out_bits { 7891 u8 status[0x8]; 7892 u8 reserved_at_8[0x18]; 7893 7894 u8 syndrome[0x20]; 7895 7896 u8 reserved_at_40[0x8]; 7897 u8 rmpn[0x18]; 7898 7899 u8 reserved_at_60[0x20]; 7900 }; 7901 7902 struct mlx5_ifc_create_rmp_in_bits { 7903 u8 opcode[0x10]; 7904 u8 uid[0x10]; 7905 7906 u8 reserved_at_20[0x10]; 7907 u8 op_mod[0x10]; 7908 7909 u8 reserved_at_40[0xc0]; 7910 7911 struct mlx5_ifc_rmpc_bits ctx; 7912 }; 7913 7914 struct mlx5_ifc_create_qp_out_bits { 7915 u8 status[0x8]; 7916 u8 reserved_at_8[0x18]; 7917 7918 u8 syndrome[0x20]; 7919 7920 u8 reserved_at_40[0x8]; 7921 u8 qpn[0x18]; 7922 7923 u8 ece[0x20]; 7924 }; 7925 7926 struct mlx5_ifc_create_qp_in_bits { 7927 u8 opcode[0x10]; 7928 u8 uid[0x10]; 7929 7930 u8 reserved_at_20[0x10]; 7931 u8 op_mod[0x10]; 7932 7933 u8 reserved_at_40[0x8]; 7934 u8 input_qpn[0x18]; 7935 7936 u8 reserved_at_60[0x20]; 7937 u8 opt_param_mask[0x20]; 7938 7939 u8 ece[0x20]; 7940 7941 struct mlx5_ifc_qpc_bits qpc; 7942 7943 u8 reserved_at_800[0x60]; 7944 7945 u8 wq_umem_valid[0x1]; 7946 u8 reserved_at_861[0x1f]; 7947 7948 u8 pas[][0x40]; 7949 }; 7950 7951 struct mlx5_ifc_create_psv_out_bits { 7952 u8 status[0x8]; 7953 u8 reserved_at_8[0x18]; 7954 7955 u8 syndrome[0x20]; 7956 7957 u8 reserved_at_40[0x40]; 7958 7959 u8 reserved_at_80[0x8]; 7960 u8 psv0_index[0x18]; 7961 7962 u8 reserved_at_a0[0x8]; 7963 u8 psv1_index[0x18]; 7964 7965 u8 reserved_at_c0[0x8]; 7966 u8 psv2_index[0x18]; 7967 7968 u8 reserved_at_e0[0x8]; 7969 u8 psv3_index[0x18]; 7970 }; 7971 7972 struct mlx5_ifc_create_psv_in_bits { 7973 u8 opcode[0x10]; 7974 u8 reserved_at_10[0x10]; 7975 7976 u8 reserved_at_20[0x10]; 7977 u8 op_mod[0x10]; 7978 7979 u8 num_psv[0x4]; 7980 u8 reserved_at_44[0x4]; 7981 u8 pd[0x18]; 7982 7983 u8 reserved_at_60[0x20]; 7984 }; 7985 7986 struct mlx5_ifc_create_mkey_out_bits { 7987 u8 status[0x8]; 7988 u8 reserved_at_8[0x18]; 7989 7990 u8 syndrome[0x20]; 7991 7992 u8 reserved_at_40[0x8]; 7993 u8 mkey_index[0x18]; 7994 7995 u8 reserved_at_60[0x20]; 7996 }; 7997 7998 struct mlx5_ifc_create_mkey_in_bits { 7999 u8 opcode[0x10]; 8000 u8 uid[0x10]; 8001 8002 u8 reserved_at_20[0x10]; 8003 u8 op_mod[0x10]; 8004 8005 u8 reserved_at_40[0x20]; 8006 8007 u8 pg_access[0x1]; 8008 u8 mkey_umem_valid[0x1]; 8009 u8 reserved_at_62[0x1e]; 8010 8011 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8012 8013 u8 reserved_at_280[0x80]; 8014 8015 u8 translations_octword_actual_size[0x20]; 8016 8017 u8 reserved_at_320[0x560]; 8018 8019 u8 klm_pas_mtt[][0x20]; 8020 }; 8021 8022 enum { 8023 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8024 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8025 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8026 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8027 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8028 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8029 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8030 }; 8031 8032 struct mlx5_ifc_create_flow_table_out_bits { 8033 u8 status[0x8]; 8034 u8 icm_address_63_40[0x18]; 8035 8036 u8 syndrome[0x20]; 8037 8038 u8 icm_address_39_32[0x8]; 8039 u8 table_id[0x18]; 8040 8041 u8 icm_address_31_0[0x20]; 8042 }; 8043 8044 struct mlx5_ifc_create_flow_table_in_bits { 8045 u8 opcode[0x10]; 8046 u8 reserved_at_10[0x10]; 8047 8048 u8 reserved_at_20[0x10]; 8049 u8 op_mod[0x10]; 8050 8051 u8 other_vport[0x1]; 8052 u8 reserved_at_41[0xf]; 8053 u8 vport_number[0x10]; 8054 8055 u8 reserved_at_60[0x20]; 8056 8057 u8 table_type[0x8]; 8058 u8 reserved_at_88[0x18]; 8059 8060 u8 reserved_at_a0[0x20]; 8061 8062 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8063 }; 8064 8065 struct mlx5_ifc_create_flow_group_out_bits { 8066 u8 status[0x8]; 8067 u8 reserved_at_8[0x18]; 8068 8069 u8 syndrome[0x20]; 8070 8071 u8 reserved_at_40[0x8]; 8072 u8 group_id[0x18]; 8073 8074 u8 reserved_at_60[0x20]; 8075 }; 8076 8077 enum { 8078 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8079 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8080 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8081 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8082 }; 8083 8084 struct mlx5_ifc_create_flow_group_in_bits { 8085 u8 opcode[0x10]; 8086 u8 reserved_at_10[0x10]; 8087 8088 u8 reserved_at_20[0x10]; 8089 u8 op_mod[0x10]; 8090 8091 u8 other_vport[0x1]; 8092 u8 reserved_at_41[0xf]; 8093 u8 vport_number[0x10]; 8094 8095 u8 reserved_at_60[0x20]; 8096 8097 u8 table_type[0x8]; 8098 u8 reserved_at_88[0x18]; 8099 8100 u8 reserved_at_a0[0x8]; 8101 u8 table_id[0x18]; 8102 8103 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8104 8105 u8 reserved_at_c1[0x1f]; 8106 8107 u8 start_flow_index[0x20]; 8108 8109 u8 reserved_at_100[0x20]; 8110 8111 u8 end_flow_index[0x20]; 8112 8113 u8 reserved_at_140[0xa0]; 8114 8115 u8 reserved_at_1e0[0x18]; 8116 u8 match_criteria_enable[0x8]; 8117 8118 struct mlx5_ifc_fte_match_param_bits match_criteria; 8119 8120 u8 reserved_at_1200[0xe00]; 8121 }; 8122 8123 struct mlx5_ifc_create_eq_out_bits { 8124 u8 status[0x8]; 8125 u8 reserved_at_8[0x18]; 8126 8127 u8 syndrome[0x20]; 8128 8129 u8 reserved_at_40[0x18]; 8130 u8 eq_number[0x8]; 8131 8132 u8 reserved_at_60[0x20]; 8133 }; 8134 8135 struct mlx5_ifc_create_eq_in_bits { 8136 u8 opcode[0x10]; 8137 u8 uid[0x10]; 8138 8139 u8 reserved_at_20[0x10]; 8140 u8 op_mod[0x10]; 8141 8142 u8 reserved_at_40[0x40]; 8143 8144 struct mlx5_ifc_eqc_bits eq_context_entry; 8145 8146 u8 reserved_at_280[0x40]; 8147 8148 u8 event_bitmask[4][0x40]; 8149 8150 u8 reserved_at_3c0[0x4c0]; 8151 8152 u8 pas[][0x40]; 8153 }; 8154 8155 struct mlx5_ifc_create_dct_out_bits { 8156 u8 status[0x8]; 8157 u8 reserved_at_8[0x18]; 8158 8159 u8 syndrome[0x20]; 8160 8161 u8 reserved_at_40[0x8]; 8162 u8 dctn[0x18]; 8163 8164 u8 ece[0x20]; 8165 }; 8166 8167 struct mlx5_ifc_create_dct_in_bits { 8168 u8 opcode[0x10]; 8169 u8 uid[0x10]; 8170 8171 u8 reserved_at_20[0x10]; 8172 u8 op_mod[0x10]; 8173 8174 u8 reserved_at_40[0x40]; 8175 8176 struct mlx5_ifc_dctc_bits dct_context_entry; 8177 8178 u8 reserved_at_280[0x180]; 8179 }; 8180 8181 struct mlx5_ifc_create_cq_out_bits { 8182 u8 status[0x8]; 8183 u8 reserved_at_8[0x18]; 8184 8185 u8 syndrome[0x20]; 8186 8187 u8 reserved_at_40[0x8]; 8188 u8 cqn[0x18]; 8189 8190 u8 reserved_at_60[0x20]; 8191 }; 8192 8193 struct mlx5_ifc_create_cq_in_bits { 8194 u8 opcode[0x10]; 8195 u8 uid[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0x40]; 8201 8202 struct mlx5_ifc_cqc_bits cq_context; 8203 8204 u8 reserved_at_280[0x60]; 8205 8206 u8 cq_umem_valid[0x1]; 8207 u8 reserved_at_2e1[0x59f]; 8208 8209 u8 pas[][0x40]; 8210 }; 8211 8212 struct mlx5_ifc_config_int_moderation_out_bits { 8213 u8 status[0x8]; 8214 u8 reserved_at_8[0x18]; 8215 8216 u8 syndrome[0x20]; 8217 8218 u8 reserved_at_40[0x4]; 8219 u8 min_delay[0xc]; 8220 u8 int_vector[0x10]; 8221 8222 u8 reserved_at_60[0x20]; 8223 }; 8224 8225 enum { 8226 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8227 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8228 }; 8229 8230 struct mlx5_ifc_config_int_moderation_in_bits { 8231 u8 opcode[0x10]; 8232 u8 reserved_at_10[0x10]; 8233 8234 u8 reserved_at_20[0x10]; 8235 u8 op_mod[0x10]; 8236 8237 u8 reserved_at_40[0x4]; 8238 u8 min_delay[0xc]; 8239 u8 int_vector[0x10]; 8240 8241 u8 reserved_at_60[0x20]; 8242 }; 8243 8244 struct mlx5_ifc_attach_to_mcg_out_bits { 8245 u8 status[0x8]; 8246 u8 reserved_at_8[0x18]; 8247 8248 u8 syndrome[0x20]; 8249 8250 u8 reserved_at_40[0x40]; 8251 }; 8252 8253 struct mlx5_ifc_attach_to_mcg_in_bits { 8254 u8 opcode[0x10]; 8255 u8 uid[0x10]; 8256 8257 u8 reserved_at_20[0x10]; 8258 u8 op_mod[0x10]; 8259 8260 u8 reserved_at_40[0x8]; 8261 u8 qpn[0x18]; 8262 8263 u8 reserved_at_60[0x20]; 8264 8265 u8 multicast_gid[16][0x8]; 8266 }; 8267 8268 struct mlx5_ifc_arm_xrq_out_bits { 8269 u8 status[0x8]; 8270 u8 reserved_at_8[0x18]; 8271 8272 u8 syndrome[0x20]; 8273 8274 u8 reserved_at_40[0x40]; 8275 }; 8276 8277 struct mlx5_ifc_arm_xrq_in_bits { 8278 u8 opcode[0x10]; 8279 u8 reserved_at_10[0x10]; 8280 8281 u8 reserved_at_20[0x10]; 8282 u8 op_mod[0x10]; 8283 8284 u8 reserved_at_40[0x8]; 8285 u8 xrqn[0x18]; 8286 8287 u8 reserved_at_60[0x10]; 8288 u8 lwm[0x10]; 8289 }; 8290 8291 struct mlx5_ifc_arm_xrc_srq_out_bits { 8292 u8 status[0x8]; 8293 u8 reserved_at_8[0x18]; 8294 8295 u8 syndrome[0x20]; 8296 8297 u8 reserved_at_40[0x40]; 8298 }; 8299 8300 enum { 8301 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8302 }; 8303 8304 struct mlx5_ifc_arm_xrc_srq_in_bits { 8305 u8 opcode[0x10]; 8306 u8 uid[0x10]; 8307 8308 u8 reserved_at_20[0x10]; 8309 u8 op_mod[0x10]; 8310 8311 u8 reserved_at_40[0x8]; 8312 u8 xrc_srqn[0x18]; 8313 8314 u8 reserved_at_60[0x10]; 8315 u8 lwm[0x10]; 8316 }; 8317 8318 struct mlx5_ifc_arm_rq_out_bits { 8319 u8 status[0x8]; 8320 u8 reserved_at_8[0x18]; 8321 8322 u8 syndrome[0x20]; 8323 8324 u8 reserved_at_40[0x40]; 8325 }; 8326 8327 enum { 8328 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8329 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8330 }; 8331 8332 struct mlx5_ifc_arm_rq_in_bits { 8333 u8 opcode[0x10]; 8334 u8 uid[0x10]; 8335 8336 u8 reserved_at_20[0x10]; 8337 u8 op_mod[0x10]; 8338 8339 u8 reserved_at_40[0x8]; 8340 u8 srq_number[0x18]; 8341 8342 u8 reserved_at_60[0x10]; 8343 u8 lwm[0x10]; 8344 }; 8345 8346 struct mlx5_ifc_arm_dct_out_bits { 8347 u8 status[0x8]; 8348 u8 reserved_at_8[0x18]; 8349 8350 u8 syndrome[0x20]; 8351 8352 u8 reserved_at_40[0x40]; 8353 }; 8354 8355 struct mlx5_ifc_arm_dct_in_bits { 8356 u8 opcode[0x10]; 8357 u8 reserved_at_10[0x10]; 8358 8359 u8 reserved_at_20[0x10]; 8360 u8 op_mod[0x10]; 8361 8362 u8 reserved_at_40[0x8]; 8363 u8 dct_number[0x18]; 8364 8365 u8 reserved_at_60[0x20]; 8366 }; 8367 8368 struct mlx5_ifc_alloc_xrcd_out_bits { 8369 u8 status[0x8]; 8370 u8 reserved_at_8[0x18]; 8371 8372 u8 syndrome[0x20]; 8373 8374 u8 reserved_at_40[0x8]; 8375 u8 xrcd[0x18]; 8376 8377 u8 reserved_at_60[0x20]; 8378 }; 8379 8380 struct mlx5_ifc_alloc_xrcd_in_bits { 8381 u8 opcode[0x10]; 8382 u8 uid[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 reserved_at_40[0x40]; 8388 }; 8389 8390 struct mlx5_ifc_alloc_uar_out_bits { 8391 u8 status[0x8]; 8392 u8 reserved_at_8[0x18]; 8393 8394 u8 syndrome[0x20]; 8395 8396 u8 reserved_at_40[0x8]; 8397 u8 uar[0x18]; 8398 8399 u8 reserved_at_60[0x20]; 8400 }; 8401 8402 struct mlx5_ifc_alloc_uar_in_bits { 8403 u8 opcode[0x10]; 8404 u8 reserved_at_10[0x10]; 8405 8406 u8 reserved_at_20[0x10]; 8407 u8 op_mod[0x10]; 8408 8409 u8 reserved_at_40[0x40]; 8410 }; 8411 8412 struct mlx5_ifc_alloc_transport_domain_out_bits { 8413 u8 status[0x8]; 8414 u8 reserved_at_8[0x18]; 8415 8416 u8 syndrome[0x20]; 8417 8418 u8 reserved_at_40[0x8]; 8419 u8 transport_domain[0x18]; 8420 8421 u8 reserved_at_60[0x20]; 8422 }; 8423 8424 struct mlx5_ifc_alloc_transport_domain_in_bits { 8425 u8 opcode[0x10]; 8426 u8 uid[0x10]; 8427 8428 u8 reserved_at_20[0x10]; 8429 u8 op_mod[0x10]; 8430 8431 u8 reserved_at_40[0x40]; 8432 }; 8433 8434 struct mlx5_ifc_alloc_q_counter_out_bits { 8435 u8 status[0x8]; 8436 u8 reserved_at_8[0x18]; 8437 8438 u8 syndrome[0x20]; 8439 8440 u8 reserved_at_40[0x18]; 8441 u8 counter_set_id[0x8]; 8442 8443 u8 reserved_at_60[0x20]; 8444 }; 8445 8446 struct mlx5_ifc_alloc_q_counter_in_bits { 8447 u8 opcode[0x10]; 8448 u8 uid[0x10]; 8449 8450 u8 reserved_at_20[0x10]; 8451 u8 op_mod[0x10]; 8452 8453 u8 reserved_at_40[0x40]; 8454 }; 8455 8456 struct mlx5_ifc_alloc_pd_out_bits { 8457 u8 status[0x8]; 8458 u8 reserved_at_8[0x18]; 8459 8460 u8 syndrome[0x20]; 8461 8462 u8 reserved_at_40[0x8]; 8463 u8 pd[0x18]; 8464 8465 u8 reserved_at_60[0x20]; 8466 }; 8467 8468 struct mlx5_ifc_alloc_pd_in_bits { 8469 u8 opcode[0x10]; 8470 u8 uid[0x10]; 8471 8472 u8 reserved_at_20[0x10]; 8473 u8 op_mod[0x10]; 8474 8475 u8 reserved_at_40[0x40]; 8476 }; 8477 8478 struct mlx5_ifc_alloc_flow_counter_out_bits { 8479 u8 status[0x8]; 8480 u8 reserved_at_8[0x18]; 8481 8482 u8 syndrome[0x20]; 8483 8484 u8 flow_counter_id[0x20]; 8485 8486 u8 reserved_at_60[0x20]; 8487 }; 8488 8489 struct mlx5_ifc_alloc_flow_counter_in_bits { 8490 u8 opcode[0x10]; 8491 u8 reserved_at_10[0x10]; 8492 8493 u8 reserved_at_20[0x10]; 8494 u8 op_mod[0x10]; 8495 8496 u8 reserved_at_40[0x38]; 8497 u8 flow_counter_bulk[0x8]; 8498 }; 8499 8500 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8501 u8 status[0x8]; 8502 u8 reserved_at_8[0x18]; 8503 8504 u8 syndrome[0x20]; 8505 8506 u8 reserved_at_40[0x40]; 8507 }; 8508 8509 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8510 u8 opcode[0x10]; 8511 u8 reserved_at_10[0x10]; 8512 8513 u8 reserved_at_20[0x10]; 8514 u8 op_mod[0x10]; 8515 8516 u8 reserved_at_40[0x20]; 8517 8518 u8 reserved_at_60[0x10]; 8519 u8 vxlan_udp_port[0x10]; 8520 }; 8521 8522 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8523 u8 status[0x8]; 8524 u8 reserved_at_8[0x18]; 8525 8526 u8 syndrome[0x20]; 8527 8528 u8 reserved_at_40[0x40]; 8529 }; 8530 8531 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8532 u8 rate_limit[0x20]; 8533 8534 u8 burst_upper_bound[0x20]; 8535 8536 u8 reserved_at_40[0x10]; 8537 u8 typical_packet_size[0x10]; 8538 8539 u8 reserved_at_60[0x120]; 8540 }; 8541 8542 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8543 u8 opcode[0x10]; 8544 u8 uid[0x10]; 8545 8546 u8 reserved_at_20[0x10]; 8547 u8 op_mod[0x10]; 8548 8549 u8 reserved_at_40[0x10]; 8550 u8 rate_limit_index[0x10]; 8551 8552 u8 reserved_at_60[0x20]; 8553 8554 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8555 }; 8556 8557 struct mlx5_ifc_access_register_out_bits { 8558 u8 status[0x8]; 8559 u8 reserved_at_8[0x18]; 8560 8561 u8 syndrome[0x20]; 8562 8563 u8 reserved_at_40[0x40]; 8564 8565 u8 register_data[][0x20]; 8566 }; 8567 8568 enum { 8569 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8570 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8571 }; 8572 8573 struct mlx5_ifc_access_register_in_bits { 8574 u8 opcode[0x10]; 8575 u8 reserved_at_10[0x10]; 8576 8577 u8 reserved_at_20[0x10]; 8578 u8 op_mod[0x10]; 8579 8580 u8 reserved_at_40[0x10]; 8581 u8 register_id[0x10]; 8582 8583 u8 argument[0x20]; 8584 8585 u8 register_data[][0x20]; 8586 }; 8587 8588 struct mlx5_ifc_sltp_reg_bits { 8589 u8 status[0x4]; 8590 u8 version[0x4]; 8591 u8 local_port[0x8]; 8592 u8 pnat[0x2]; 8593 u8 reserved_at_12[0x2]; 8594 u8 lane[0x4]; 8595 u8 reserved_at_18[0x8]; 8596 8597 u8 reserved_at_20[0x20]; 8598 8599 u8 reserved_at_40[0x7]; 8600 u8 polarity[0x1]; 8601 u8 ob_tap0[0x8]; 8602 u8 ob_tap1[0x8]; 8603 u8 ob_tap2[0x8]; 8604 8605 u8 reserved_at_60[0xc]; 8606 u8 ob_preemp_mode[0x4]; 8607 u8 ob_reg[0x8]; 8608 u8 ob_bias[0x8]; 8609 8610 u8 reserved_at_80[0x20]; 8611 }; 8612 8613 struct mlx5_ifc_slrg_reg_bits { 8614 u8 status[0x4]; 8615 u8 version[0x4]; 8616 u8 local_port[0x8]; 8617 u8 pnat[0x2]; 8618 u8 reserved_at_12[0x2]; 8619 u8 lane[0x4]; 8620 u8 reserved_at_18[0x8]; 8621 8622 u8 time_to_link_up[0x10]; 8623 u8 reserved_at_30[0xc]; 8624 u8 grade_lane_speed[0x4]; 8625 8626 u8 grade_version[0x8]; 8627 u8 grade[0x18]; 8628 8629 u8 reserved_at_60[0x4]; 8630 u8 height_grade_type[0x4]; 8631 u8 height_grade[0x18]; 8632 8633 u8 height_dz[0x10]; 8634 u8 height_dv[0x10]; 8635 8636 u8 reserved_at_a0[0x10]; 8637 u8 height_sigma[0x10]; 8638 8639 u8 reserved_at_c0[0x20]; 8640 8641 u8 reserved_at_e0[0x4]; 8642 u8 phase_grade_type[0x4]; 8643 u8 phase_grade[0x18]; 8644 8645 u8 reserved_at_100[0x8]; 8646 u8 phase_eo_pos[0x8]; 8647 u8 reserved_at_110[0x8]; 8648 u8 phase_eo_neg[0x8]; 8649 8650 u8 ffe_set_tested[0x10]; 8651 u8 test_errors_per_lane[0x10]; 8652 }; 8653 8654 struct mlx5_ifc_pvlc_reg_bits { 8655 u8 reserved_at_0[0x8]; 8656 u8 local_port[0x8]; 8657 u8 reserved_at_10[0x10]; 8658 8659 u8 reserved_at_20[0x1c]; 8660 u8 vl_hw_cap[0x4]; 8661 8662 u8 reserved_at_40[0x1c]; 8663 u8 vl_admin[0x4]; 8664 8665 u8 reserved_at_60[0x1c]; 8666 u8 vl_operational[0x4]; 8667 }; 8668 8669 struct mlx5_ifc_pude_reg_bits { 8670 u8 swid[0x8]; 8671 u8 local_port[0x8]; 8672 u8 reserved_at_10[0x4]; 8673 u8 admin_status[0x4]; 8674 u8 reserved_at_18[0x4]; 8675 u8 oper_status[0x4]; 8676 8677 u8 reserved_at_20[0x60]; 8678 }; 8679 8680 struct mlx5_ifc_ptys_reg_bits { 8681 u8 reserved_at_0[0x1]; 8682 u8 an_disable_admin[0x1]; 8683 u8 an_disable_cap[0x1]; 8684 u8 reserved_at_3[0x5]; 8685 u8 local_port[0x8]; 8686 u8 reserved_at_10[0xd]; 8687 u8 proto_mask[0x3]; 8688 8689 u8 an_status[0x4]; 8690 u8 reserved_at_24[0xc]; 8691 u8 data_rate_oper[0x10]; 8692 8693 u8 ext_eth_proto_capability[0x20]; 8694 8695 u8 eth_proto_capability[0x20]; 8696 8697 u8 ib_link_width_capability[0x10]; 8698 u8 ib_proto_capability[0x10]; 8699 8700 u8 ext_eth_proto_admin[0x20]; 8701 8702 u8 eth_proto_admin[0x20]; 8703 8704 u8 ib_link_width_admin[0x10]; 8705 u8 ib_proto_admin[0x10]; 8706 8707 u8 ext_eth_proto_oper[0x20]; 8708 8709 u8 eth_proto_oper[0x20]; 8710 8711 u8 ib_link_width_oper[0x10]; 8712 u8 ib_proto_oper[0x10]; 8713 8714 u8 reserved_at_160[0x1c]; 8715 u8 connector_type[0x4]; 8716 8717 u8 eth_proto_lp_advertise[0x20]; 8718 8719 u8 reserved_at_1a0[0x60]; 8720 }; 8721 8722 struct mlx5_ifc_mlcr_reg_bits { 8723 u8 reserved_at_0[0x8]; 8724 u8 local_port[0x8]; 8725 u8 reserved_at_10[0x20]; 8726 8727 u8 beacon_duration[0x10]; 8728 u8 reserved_at_40[0x10]; 8729 8730 u8 beacon_remain[0x10]; 8731 }; 8732 8733 struct mlx5_ifc_ptas_reg_bits { 8734 u8 reserved_at_0[0x20]; 8735 8736 u8 algorithm_options[0x10]; 8737 u8 reserved_at_30[0x4]; 8738 u8 repetitions_mode[0x4]; 8739 u8 num_of_repetitions[0x8]; 8740 8741 u8 grade_version[0x8]; 8742 u8 height_grade_type[0x4]; 8743 u8 phase_grade_type[0x4]; 8744 u8 height_grade_weight[0x8]; 8745 u8 phase_grade_weight[0x8]; 8746 8747 u8 gisim_measure_bits[0x10]; 8748 u8 adaptive_tap_measure_bits[0x10]; 8749 8750 u8 ber_bath_high_error_threshold[0x10]; 8751 u8 ber_bath_mid_error_threshold[0x10]; 8752 8753 u8 ber_bath_low_error_threshold[0x10]; 8754 u8 one_ratio_high_threshold[0x10]; 8755 8756 u8 one_ratio_high_mid_threshold[0x10]; 8757 u8 one_ratio_low_mid_threshold[0x10]; 8758 8759 u8 one_ratio_low_threshold[0x10]; 8760 u8 ndeo_error_threshold[0x10]; 8761 8762 u8 mixer_offset_step_size[0x10]; 8763 u8 reserved_at_110[0x8]; 8764 u8 mix90_phase_for_voltage_bath[0x8]; 8765 8766 u8 mixer_offset_start[0x10]; 8767 u8 mixer_offset_end[0x10]; 8768 8769 u8 reserved_at_140[0x15]; 8770 u8 ber_test_time[0xb]; 8771 }; 8772 8773 struct mlx5_ifc_pspa_reg_bits { 8774 u8 swid[0x8]; 8775 u8 local_port[0x8]; 8776 u8 sub_port[0x8]; 8777 u8 reserved_at_18[0x8]; 8778 8779 u8 reserved_at_20[0x20]; 8780 }; 8781 8782 struct mlx5_ifc_pqdr_reg_bits { 8783 u8 reserved_at_0[0x8]; 8784 u8 local_port[0x8]; 8785 u8 reserved_at_10[0x5]; 8786 u8 prio[0x3]; 8787 u8 reserved_at_18[0x6]; 8788 u8 mode[0x2]; 8789 8790 u8 reserved_at_20[0x20]; 8791 8792 u8 reserved_at_40[0x10]; 8793 u8 min_threshold[0x10]; 8794 8795 u8 reserved_at_60[0x10]; 8796 u8 max_threshold[0x10]; 8797 8798 u8 reserved_at_80[0x10]; 8799 u8 mark_probability_denominator[0x10]; 8800 8801 u8 reserved_at_a0[0x60]; 8802 }; 8803 8804 struct mlx5_ifc_ppsc_reg_bits { 8805 u8 reserved_at_0[0x8]; 8806 u8 local_port[0x8]; 8807 u8 reserved_at_10[0x10]; 8808 8809 u8 reserved_at_20[0x60]; 8810 8811 u8 reserved_at_80[0x1c]; 8812 u8 wrps_admin[0x4]; 8813 8814 u8 reserved_at_a0[0x1c]; 8815 u8 wrps_status[0x4]; 8816 8817 u8 reserved_at_c0[0x8]; 8818 u8 up_threshold[0x8]; 8819 u8 reserved_at_d0[0x8]; 8820 u8 down_threshold[0x8]; 8821 8822 u8 reserved_at_e0[0x20]; 8823 8824 u8 reserved_at_100[0x1c]; 8825 u8 srps_admin[0x4]; 8826 8827 u8 reserved_at_120[0x1c]; 8828 u8 srps_status[0x4]; 8829 8830 u8 reserved_at_140[0x40]; 8831 }; 8832 8833 struct mlx5_ifc_pplr_reg_bits { 8834 u8 reserved_at_0[0x8]; 8835 u8 local_port[0x8]; 8836 u8 reserved_at_10[0x10]; 8837 8838 u8 reserved_at_20[0x8]; 8839 u8 lb_cap[0x8]; 8840 u8 reserved_at_30[0x8]; 8841 u8 lb_en[0x8]; 8842 }; 8843 8844 struct mlx5_ifc_pplm_reg_bits { 8845 u8 reserved_at_0[0x8]; 8846 u8 local_port[0x8]; 8847 u8 reserved_at_10[0x10]; 8848 8849 u8 reserved_at_20[0x20]; 8850 8851 u8 port_profile_mode[0x8]; 8852 u8 static_port_profile[0x8]; 8853 u8 active_port_profile[0x8]; 8854 u8 reserved_at_58[0x8]; 8855 8856 u8 retransmission_active[0x8]; 8857 u8 fec_mode_active[0x18]; 8858 8859 u8 rs_fec_correction_bypass_cap[0x4]; 8860 u8 reserved_at_84[0x8]; 8861 u8 fec_override_cap_56g[0x4]; 8862 u8 fec_override_cap_100g[0x4]; 8863 u8 fec_override_cap_50g[0x4]; 8864 u8 fec_override_cap_25g[0x4]; 8865 u8 fec_override_cap_10g_40g[0x4]; 8866 8867 u8 rs_fec_correction_bypass_admin[0x4]; 8868 u8 reserved_at_a4[0x8]; 8869 u8 fec_override_admin_56g[0x4]; 8870 u8 fec_override_admin_100g[0x4]; 8871 u8 fec_override_admin_50g[0x4]; 8872 u8 fec_override_admin_25g[0x4]; 8873 u8 fec_override_admin_10g_40g[0x4]; 8874 8875 u8 fec_override_cap_400g_8x[0x10]; 8876 u8 fec_override_cap_200g_4x[0x10]; 8877 8878 u8 fec_override_cap_100g_2x[0x10]; 8879 u8 fec_override_cap_50g_1x[0x10]; 8880 8881 u8 fec_override_admin_400g_8x[0x10]; 8882 u8 fec_override_admin_200g_4x[0x10]; 8883 8884 u8 fec_override_admin_100g_2x[0x10]; 8885 u8 fec_override_admin_50g_1x[0x10]; 8886 8887 u8 reserved_at_140[0x140]; 8888 }; 8889 8890 struct mlx5_ifc_ppcnt_reg_bits { 8891 u8 swid[0x8]; 8892 u8 local_port[0x8]; 8893 u8 pnat[0x2]; 8894 u8 reserved_at_12[0x8]; 8895 u8 grp[0x6]; 8896 8897 u8 clr[0x1]; 8898 u8 reserved_at_21[0x1c]; 8899 u8 prio_tc[0x3]; 8900 8901 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8902 }; 8903 8904 struct mlx5_ifc_mpein_reg_bits { 8905 u8 reserved_at_0[0x2]; 8906 u8 depth[0x6]; 8907 u8 pcie_index[0x8]; 8908 u8 node[0x8]; 8909 u8 reserved_at_18[0x8]; 8910 8911 u8 capability_mask[0x20]; 8912 8913 u8 reserved_at_40[0x8]; 8914 u8 link_width_enabled[0x8]; 8915 u8 link_speed_enabled[0x10]; 8916 8917 u8 lane0_physical_position[0x8]; 8918 u8 link_width_active[0x8]; 8919 u8 link_speed_active[0x10]; 8920 8921 u8 num_of_pfs[0x10]; 8922 u8 num_of_vfs[0x10]; 8923 8924 u8 bdf0[0x10]; 8925 u8 reserved_at_b0[0x10]; 8926 8927 u8 max_read_request_size[0x4]; 8928 u8 max_payload_size[0x4]; 8929 u8 reserved_at_c8[0x5]; 8930 u8 pwr_status[0x3]; 8931 u8 port_type[0x4]; 8932 u8 reserved_at_d4[0xb]; 8933 u8 lane_reversal[0x1]; 8934 8935 u8 reserved_at_e0[0x14]; 8936 u8 pci_power[0xc]; 8937 8938 u8 reserved_at_100[0x20]; 8939 8940 u8 device_status[0x10]; 8941 u8 port_state[0x8]; 8942 u8 reserved_at_138[0x8]; 8943 8944 u8 reserved_at_140[0x10]; 8945 u8 receiver_detect_result[0x10]; 8946 8947 u8 reserved_at_160[0x20]; 8948 }; 8949 8950 struct mlx5_ifc_mpcnt_reg_bits { 8951 u8 reserved_at_0[0x8]; 8952 u8 pcie_index[0x8]; 8953 u8 reserved_at_10[0xa]; 8954 u8 grp[0x6]; 8955 8956 u8 clr[0x1]; 8957 u8 reserved_at_21[0x1f]; 8958 8959 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8960 }; 8961 8962 struct mlx5_ifc_ppad_reg_bits { 8963 u8 reserved_at_0[0x3]; 8964 u8 single_mac[0x1]; 8965 u8 reserved_at_4[0x4]; 8966 u8 local_port[0x8]; 8967 u8 mac_47_32[0x10]; 8968 8969 u8 mac_31_0[0x20]; 8970 8971 u8 reserved_at_40[0x40]; 8972 }; 8973 8974 struct mlx5_ifc_pmtu_reg_bits { 8975 u8 reserved_at_0[0x8]; 8976 u8 local_port[0x8]; 8977 u8 reserved_at_10[0x10]; 8978 8979 u8 max_mtu[0x10]; 8980 u8 reserved_at_30[0x10]; 8981 8982 u8 admin_mtu[0x10]; 8983 u8 reserved_at_50[0x10]; 8984 8985 u8 oper_mtu[0x10]; 8986 u8 reserved_at_70[0x10]; 8987 }; 8988 8989 struct mlx5_ifc_pmpr_reg_bits { 8990 u8 reserved_at_0[0x8]; 8991 u8 module[0x8]; 8992 u8 reserved_at_10[0x10]; 8993 8994 u8 reserved_at_20[0x18]; 8995 u8 attenuation_5g[0x8]; 8996 8997 u8 reserved_at_40[0x18]; 8998 u8 attenuation_7g[0x8]; 8999 9000 u8 reserved_at_60[0x18]; 9001 u8 attenuation_12g[0x8]; 9002 }; 9003 9004 struct mlx5_ifc_pmpe_reg_bits { 9005 u8 reserved_at_0[0x8]; 9006 u8 module[0x8]; 9007 u8 reserved_at_10[0xc]; 9008 u8 module_status[0x4]; 9009 9010 u8 reserved_at_20[0x60]; 9011 }; 9012 9013 struct mlx5_ifc_pmpc_reg_bits { 9014 u8 module_state_updated[32][0x8]; 9015 }; 9016 9017 struct mlx5_ifc_pmlpn_reg_bits { 9018 u8 reserved_at_0[0x4]; 9019 u8 mlpn_status[0x4]; 9020 u8 local_port[0x8]; 9021 u8 reserved_at_10[0x10]; 9022 9023 u8 e[0x1]; 9024 u8 reserved_at_21[0x1f]; 9025 }; 9026 9027 struct mlx5_ifc_pmlp_reg_bits { 9028 u8 rxtx[0x1]; 9029 u8 reserved_at_1[0x7]; 9030 u8 local_port[0x8]; 9031 u8 reserved_at_10[0x8]; 9032 u8 width[0x8]; 9033 9034 u8 lane0_module_mapping[0x20]; 9035 9036 u8 lane1_module_mapping[0x20]; 9037 9038 u8 lane2_module_mapping[0x20]; 9039 9040 u8 lane3_module_mapping[0x20]; 9041 9042 u8 reserved_at_a0[0x160]; 9043 }; 9044 9045 struct mlx5_ifc_pmaos_reg_bits { 9046 u8 reserved_at_0[0x8]; 9047 u8 module[0x8]; 9048 u8 reserved_at_10[0x4]; 9049 u8 admin_status[0x4]; 9050 u8 reserved_at_18[0x4]; 9051 u8 oper_status[0x4]; 9052 9053 u8 ase[0x1]; 9054 u8 ee[0x1]; 9055 u8 reserved_at_22[0x1c]; 9056 u8 e[0x2]; 9057 9058 u8 reserved_at_40[0x40]; 9059 }; 9060 9061 struct mlx5_ifc_plpc_reg_bits { 9062 u8 reserved_at_0[0x4]; 9063 u8 profile_id[0xc]; 9064 u8 reserved_at_10[0x4]; 9065 u8 proto_mask[0x4]; 9066 u8 reserved_at_18[0x8]; 9067 9068 u8 reserved_at_20[0x10]; 9069 u8 lane_speed[0x10]; 9070 9071 u8 reserved_at_40[0x17]; 9072 u8 lpbf[0x1]; 9073 u8 fec_mode_policy[0x8]; 9074 9075 u8 retransmission_capability[0x8]; 9076 u8 fec_mode_capability[0x18]; 9077 9078 u8 retransmission_support_admin[0x8]; 9079 u8 fec_mode_support_admin[0x18]; 9080 9081 u8 retransmission_request_admin[0x8]; 9082 u8 fec_mode_request_admin[0x18]; 9083 9084 u8 reserved_at_c0[0x80]; 9085 }; 9086 9087 struct mlx5_ifc_plib_reg_bits { 9088 u8 reserved_at_0[0x8]; 9089 u8 local_port[0x8]; 9090 u8 reserved_at_10[0x8]; 9091 u8 ib_port[0x8]; 9092 9093 u8 reserved_at_20[0x60]; 9094 }; 9095 9096 struct mlx5_ifc_plbf_reg_bits { 9097 u8 reserved_at_0[0x8]; 9098 u8 local_port[0x8]; 9099 u8 reserved_at_10[0xd]; 9100 u8 lbf_mode[0x3]; 9101 9102 u8 reserved_at_20[0x20]; 9103 }; 9104 9105 struct mlx5_ifc_pipg_reg_bits { 9106 u8 reserved_at_0[0x8]; 9107 u8 local_port[0x8]; 9108 u8 reserved_at_10[0x10]; 9109 9110 u8 dic[0x1]; 9111 u8 reserved_at_21[0x19]; 9112 u8 ipg[0x4]; 9113 u8 reserved_at_3e[0x2]; 9114 }; 9115 9116 struct mlx5_ifc_pifr_reg_bits { 9117 u8 reserved_at_0[0x8]; 9118 u8 local_port[0x8]; 9119 u8 reserved_at_10[0x10]; 9120 9121 u8 reserved_at_20[0xe0]; 9122 9123 u8 port_filter[8][0x20]; 9124 9125 u8 port_filter_update_en[8][0x20]; 9126 }; 9127 9128 struct mlx5_ifc_pfcc_reg_bits { 9129 u8 reserved_at_0[0x8]; 9130 u8 local_port[0x8]; 9131 u8 reserved_at_10[0xb]; 9132 u8 ppan_mask_n[0x1]; 9133 u8 minor_stall_mask[0x1]; 9134 u8 critical_stall_mask[0x1]; 9135 u8 reserved_at_1e[0x2]; 9136 9137 u8 ppan[0x4]; 9138 u8 reserved_at_24[0x4]; 9139 u8 prio_mask_tx[0x8]; 9140 u8 reserved_at_30[0x8]; 9141 u8 prio_mask_rx[0x8]; 9142 9143 u8 pptx[0x1]; 9144 u8 aptx[0x1]; 9145 u8 pptx_mask_n[0x1]; 9146 u8 reserved_at_43[0x5]; 9147 u8 pfctx[0x8]; 9148 u8 reserved_at_50[0x10]; 9149 9150 u8 pprx[0x1]; 9151 u8 aprx[0x1]; 9152 u8 pprx_mask_n[0x1]; 9153 u8 reserved_at_63[0x5]; 9154 u8 pfcrx[0x8]; 9155 u8 reserved_at_70[0x10]; 9156 9157 u8 device_stall_minor_watermark[0x10]; 9158 u8 device_stall_critical_watermark[0x10]; 9159 9160 u8 reserved_at_a0[0x60]; 9161 }; 9162 9163 struct mlx5_ifc_pelc_reg_bits { 9164 u8 op[0x4]; 9165 u8 reserved_at_4[0x4]; 9166 u8 local_port[0x8]; 9167 u8 reserved_at_10[0x10]; 9168 9169 u8 op_admin[0x8]; 9170 u8 op_capability[0x8]; 9171 u8 op_request[0x8]; 9172 u8 op_active[0x8]; 9173 9174 u8 admin[0x40]; 9175 9176 u8 capability[0x40]; 9177 9178 u8 request[0x40]; 9179 9180 u8 active[0x40]; 9181 9182 u8 reserved_at_140[0x80]; 9183 }; 9184 9185 struct mlx5_ifc_peir_reg_bits { 9186 u8 reserved_at_0[0x8]; 9187 u8 local_port[0x8]; 9188 u8 reserved_at_10[0x10]; 9189 9190 u8 reserved_at_20[0xc]; 9191 u8 error_count[0x4]; 9192 u8 reserved_at_30[0x10]; 9193 9194 u8 reserved_at_40[0xc]; 9195 u8 lane[0x4]; 9196 u8 reserved_at_50[0x8]; 9197 u8 error_type[0x8]; 9198 }; 9199 9200 struct mlx5_ifc_mpegc_reg_bits { 9201 u8 reserved_at_0[0x30]; 9202 u8 field_select[0x10]; 9203 9204 u8 tx_overflow_sense[0x1]; 9205 u8 mark_cqe[0x1]; 9206 u8 mark_cnp[0x1]; 9207 u8 reserved_at_43[0x1b]; 9208 u8 tx_lossy_overflow_oper[0x2]; 9209 9210 u8 reserved_at_60[0x100]; 9211 }; 9212 9213 enum { 9214 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9215 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9216 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9217 }; 9218 9219 struct mlx5_ifc_mtutc_reg_bits { 9220 u8 reserved_at_0[0x1c]; 9221 u8 operation[0x4]; 9222 9223 u8 freq_adjustment[0x20]; 9224 9225 u8 reserved_at_40[0x40]; 9226 9227 u8 utc_sec[0x20]; 9228 9229 u8 reserved_at_a0[0x2]; 9230 u8 utc_nsec[0x1e]; 9231 9232 u8 time_adjustment[0x20]; 9233 }; 9234 9235 struct mlx5_ifc_pcam_enhanced_features_bits { 9236 u8 reserved_at_0[0x68]; 9237 u8 fec_50G_per_lane_in_pplm[0x1]; 9238 u8 reserved_at_69[0x4]; 9239 u8 rx_icrc_encapsulated_counter[0x1]; 9240 u8 reserved_at_6e[0x4]; 9241 u8 ptys_extended_ethernet[0x1]; 9242 u8 reserved_at_73[0x3]; 9243 u8 pfcc_mask[0x1]; 9244 u8 reserved_at_77[0x3]; 9245 u8 per_lane_error_counters[0x1]; 9246 u8 rx_buffer_fullness_counters[0x1]; 9247 u8 ptys_connector_type[0x1]; 9248 u8 reserved_at_7d[0x1]; 9249 u8 ppcnt_discard_group[0x1]; 9250 u8 ppcnt_statistical_group[0x1]; 9251 }; 9252 9253 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9254 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9255 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9256 9257 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9258 u8 pplm[0x1]; 9259 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9260 9261 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9262 u8 pbmc[0x1]; 9263 u8 pptb[0x1]; 9264 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9265 u8 ppcnt[0x1]; 9266 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9267 }; 9268 9269 struct mlx5_ifc_pcam_reg_bits { 9270 u8 reserved_at_0[0x8]; 9271 u8 feature_group[0x8]; 9272 u8 reserved_at_10[0x8]; 9273 u8 access_reg_group[0x8]; 9274 9275 u8 reserved_at_20[0x20]; 9276 9277 union { 9278 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9279 u8 reserved_at_0[0x80]; 9280 } port_access_reg_cap_mask; 9281 9282 u8 reserved_at_c0[0x80]; 9283 9284 union { 9285 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9286 u8 reserved_at_0[0x80]; 9287 } feature_cap_mask; 9288 9289 u8 reserved_at_1c0[0xc0]; 9290 }; 9291 9292 struct mlx5_ifc_mcam_enhanced_features_bits { 9293 u8 reserved_at_0[0x6b]; 9294 u8 ptpcyc2realtime_modify[0x1]; 9295 u8 reserved_at_6c[0x2]; 9296 u8 pci_status_and_power[0x1]; 9297 u8 reserved_at_6f[0x5]; 9298 u8 mark_tx_action_cnp[0x1]; 9299 u8 mark_tx_action_cqe[0x1]; 9300 u8 dynamic_tx_overflow[0x1]; 9301 u8 reserved_at_77[0x4]; 9302 u8 pcie_outbound_stalled[0x1]; 9303 u8 tx_overflow_buffer_pkt[0x1]; 9304 u8 mtpps_enh_out_per_adj[0x1]; 9305 u8 mtpps_fs[0x1]; 9306 u8 pcie_performance_group[0x1]; 9307 }; 9308 9309 struct mlx5_ifc_mcam_access_reg_bits { 9310 u8 reserved_at_0[0x1c]; 9311 u8 mcda[0x1]; 9312 u8 mcc[0x1]; 9313 u8 mcqi[0x1]; 9314 u8 mcqs[0x1]; 9315 9316 u8 regs_95_to_87[0x9]; 9317 u8 mpegc[0x1]; 9318 u8 mtutc[0x1]; 9319 u8 regs_84_to_68[0x11]; 9320 u8 tracer_registers[0x4]; 9321 9322 u8 regs_63_to_32[0x20]; 9323 u8 regs_31_to_0[0x20]; 9324 }; 9325 9326 struct mlx5_ifc_mcam_access_reg_bits1 { 9327 u8 regs_127_to_96[0x20]; 9328 9329 u8 regs_95_to_64[0x20]; 9330 9331 u8 regs_63_to_32[0x20]; 9332 9333 u8 regs_31_to_0[0x20]; 9334 }; 9335 9336 struct mlx5_ifc_mcam_access_reg_bits2 { 9337 u8 regs_127_to_99[0x1d]; 9338 u8 mirc[0x1]; 9339 u8 regs_97_to_96[0x2]; 9340 9341 u8 regs_95_to_64[0x20]; 9342 9343 u8 regs_63_to_32[0x20]; 9344 9345 u8 regs_31_to_0[0x20]; 9346 }; 9347 9348 struct mlx5_ifc_mcam_reg_bits { 9349 u8 reserved_at_0[0x8]; 9350 u8 feature_group[0x8]; 9351 u8 reserved_at_10[0x8]; 9352 u8 access_reg_group[0x8]; 9353 9354 u8 reserved_at_20[0x20]; 9355 9356 union { 9357 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9358 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9359 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9360 u8 reserved_at_0[0x80]; 9361 } mng_access_reg_cap_mask; 9362 9363 u8 reserved_at_c0[0x80]; 9364 9365 union { 9366 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9367 u8 reserved_at_0[0x80]; 9368 } mng_feature_cap_mask; 9369 9370 u8 reserved_at_1c0[0x80]; 9371 }; 9372 9373 struct mlx5_ifc_qcam_access_reg_cap_mask { 9374 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9375 u8 qpdpm[0x1]; 9376 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9377 u8 qdpm[0x1]; 9378 u8 qpts[0x1]; 9379 u8 qcap[0x1]; 9380 u8 qcam_access_reg_cap_mask_0[0x1]; 9381 }; 9382 9383 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9384 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9385 u8 qpts_trust_both[0x1]; 9386 }; 9387 9388 struct mlx5_ifc_qcam_reg_bits { 9389 u8 reserved_at_0[0x8]; 9390 u8 feature_group[0x8]; 9391 u8 reserved_at_10[0x8]; 9392 u8 access_reg_group[0x8]; 9393 u8 reserved_at_20[0x20]; 9394 9395 union { 9396 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9397 u8 reserved_at_0[0x80]; 9398 } qos_access_reg_cap_mask; 9399 9400 u8 reserved_at_c0[0x80]; 9401 9402 union { 9403 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9404 u8 reserved_at_0[0x80]; 9405 } qos_feature_cap_mask; 9406 9407 u8 reserved_at_1c0[0x80]; 9408 }; 9409 9410 struct mlx5_ifc_core_dump_reg_bits { 9411 u8 reserved_at_0[0x18]; 9412 u8 core_dump_type[0x8]; 9413 9414 u8 reserved_at_20[0x30]; 9415 u8 vhca_id[0x10]; 9416 9417 u8 reserved_at_60[0x8]; 9418 u8 qpn[0x18]; 9419 u8 reserved_at_80[0x180]; 9420 }; 9421 9422 struct mlx5_ifc_pcap_reg_bits { 9423 u8 reserved_at_0[0x8]; 9424 u8 local_port[0x8]; 9425 u8 reserved_at_10[0x10]; 9426 9427 u8 port_capability_mask[4][0x20]; 9428 }; 9429 9430 struct mlx5_ifc_paos_reg_bits { 9431 u8 swid[0x8]; 9432 u8 local_port[0x8]; 9433 u8 reserved_at_10[0x4]; 9434 u8 admin_status[0x4]; 9435 u8 reserved_at_18[0x4]; 9436 u8 oper_status[0x4]; 9437 9438 u8 ase[0x1]; 9439 u8 ee[0x1]; 9440 u8 reserved_at_22[0x1c]; 9441 u8 e[0x2]; 9442 9443 u8 reserved_at_40[0x40]; 9444 }; 9445 9446 struct mlx5_ifc_pamp_reg_bits { 9447 u8 reserved_at_0[0x8]; 9448 u8 opamp_group[0x8]; 9449 u8 reserved_at_10[0xc]; 9450 u8 opamp_group_type[0x4]; 9451 9452 u8 start_index[0x10]; 9453 u8 reserved_at_30[0x4]; 9454 u8 num_of_indices[0xc]; 9455 9456 u8 index_data[18][0x10]; 9457 }; 9458 9459 struct mlx5_ifc_pcmr_reg_bits { 9460 u8 reserved_at_0[0x8]; 9461 u8 local_port[0x8]; 9462 u8 reserved_at_10[0x10]; 9463 u8 entropy_force_cap[0x1]; 9464 u8 entropy_calc_cap[0x1]; 9465 u8 entropy_gre_calc_cap[0x1]; 9466 u8 reserved_at_23[0x1b]; 9467 u8 fcs_cap[0x1]; 9468 u8 reserved_at_3f[0x1]; 9469 u8 entropy_force[0x1]; 9470 u8 entropy_calc[0x1]; 9471 u8 entropy_gre_calc[0x1]; 9472 u8 reserved_at_43[0x1b]; 9473 u8 fcs_chk[0x1]; 9474 u8 reserved_at_5f[0x1]; 9475 }; 9476 9477 struct mlx5_ifc_lane_2_module_mapping_bits { 9478 u8 reserved_at_0[0x6]; 9479 u8 rx_lane[0x2]; 9480 u8 reserved_at_8[0x6]; 9481 u8 tx_lane[0x2]; 9482 u8 reserved_at_10[0x8]; 9483 u8 module[0x8]; 9484 }; 9485 9486 struct mlx5_ifc_bufferx_reg_bits { 9487 u8 reserved_at_0[0x6]; 9488 u8 lossy[0x1]; 9489 u8 epsb[0x1]; 9490 u8 reserved_at_8[0xc]; 9491 u8 size[0xc]; 9492 9493 u8 xoff_threshold[0x10]; 9494 u8 xon_threshold[0x10]; 9495 }; 9496 9497 struct mlx5_ifc_set_node_in_bits { 9498 u8 node_description[64][0x8]; 9499 }; 9500 9501 struct mlx5_ifc_register_power_settings_bits { 9502 u8 reserved_at_0[0x18]; 9503 u8 power_settings_level[0x8]; 9504 9505 u8 reserved_at_20[0x60]; 9506 }; 9507 9508 struct mlx5_ifc_register_host_endianness_bits { 9509 u8 he[0x1]; 9510 u8 reserved_at_1[0x1f]; 9511 9512 u8 reserved_at_20[0x60]; 9513 }; 9514 9515 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9516 u8 reserved_at_0[0x20]; 9517 9518 u8 mkey[0x20]; 9519 9520 u8 addressh_63_32[0x20]; 9521 9522 u8 addressl_31_0[0x20]; 9523 }; 9524 9525 struct mlx5_ifc_ud_adrs_vector_bits { 9526 u8 dc_key[0x40]; 9527 9528 u8 ext[0x1]; 9529 u8 reserved_at_41[0x7]; 9530 u8 destination_qp_dct[0x18]; 9531 9532 u8 static_rate[0x4]; 9533 u8 sl_eth_prio[0x4]; 9534 u8 fl[0x1]; 9535 u8 mlid[0x7]; 9536 u8 rlid_udp_sport[0x10]; 9537 9538 u8 reserved_at_80[0x20]; 9539 9540 u8 rmac_47_16[0x20]; 9541 9542 u8 rmac_15_0[0x10]; 9543 u8 tclass[0x8]; 9544 u8 hop_limit[0x8]; 9545 9546 u8 reserved_at_e0[0x1]; 9547 u8 grh[0x1]; 9548 u8 reserved_at_e2[0x2]; 9549 u8 src_addr_index[0x8]; 9550 u8 flow_label[0x14]; 9551 9552 u8 rgid_rip[16][0x8]; 9553 }; 9554 9555 struct mlx5_ifc_pages_req_event_bits { 9556 u8 reserved_at_0[0x10]; 9557 u8 function_id[0x10]; 9558 9559 u8 num_pages[0x20]; 9560 9561 u8 reserved_at_40[0xa0]; 9562 }; 9563 9564 struct mlx5_ifc_eqe_bits { 9565 u8 reserved_at_0[0x8]; 9566 u8 event_type[0x8]; 9567 u8 reserved_at_10[0x8]; 9568 u8 event_sub_type[0x8]; 9569 9570 u8 reserved_at_20[0xe0]; 9571 9572 union mlx5_ifc_event_auto_bits event_data; 9573 9574 u8 reserved_at_1e0[0x10]; 9575 u8 signature[0x8]; 9576 u8 reserved_at_1f8[0x7]; 9577 u8 owner[0x1]; 9578 }; 9579 9580 enum { 9581 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9582 }; 9583 9584 struct mlx5_ifc_cmd_queue_entry_bits { 9585 u8 type[0x8]; 9586 u8 reserved_at_8[0x18]; 9587 9588 u8 input_length[0x20]; 9589 9590 u8 input_mailbox_pointer_63_32[0x20]; 9591 9592 u8 input_mailbox_pointer_31_9[0x17]; 9593 u8 reserved_at_77[0x9]; 9594 9595 u8 command_input_inline_data[16][0x8]; 9596 9597 u8 command_output_inline_data[16][0x8]; 9598 9599 u8 output_mailbox_pointer_63_32[0x20]; 9600 9601 u8 output_mailbox_pointer_31_9[0x17]; 9602 u8 reserved_at_1b7[0x9]; 9603 9604 u8 output_length[0x20]; 9605 9606 u8 token[0x8]; 9607 u8 signature[0x8]; 9608 u8 reserved_at_1f0[0x8]; 9609 u8 status[0x7]; 9610 u8 ownership[0x1]; 9611 }; 9612 9613 struct mlx5_ifc_cmd_out_bits { 9614 u8 status[0x8]; 9615 u8 reserved_at_8[0x18]; 9616 9617 u8 syndrome[0x20]; 9618 9619 u8 command_output[0x20]; 9620 }; 9621 9622 struct mlx5_ifc_cmd_in_bits { 9623 u8 opcode[0x10]; 9624 u8 reserved_at_10[0x10]; 9625 9626 u8 reserved_at_20[0x10]; 9627 u8 op_mod[0x10]; 9628 9629 u8 command[][0x20]; 9630 }; 9631 9632 struct mlx5_ifc_cmd_if_box_bits { 9633 u8 mailbox_data[512][0x8]; 9634 9635 u8 reserved_at_1000[0x180]; 9636 9637 u8 next_pointer_63_32[0x20]; 9638 9639 u8 next_pointer_31_10[0x16]; 9640 u8 reserved_at_11b6[0xa]; 9641 9642 u8 block_number[0x20]; 9643 9644 u8 reserved_at_11e0[0x8]; 9645 u8 token[0x8]; 9646 u8 ctrl_signature[0x8]; 9647 u8 signature[0x8]; 9648 }; 9649 9650 struct mlx5_ifc_mtt_bits { 9651 u8 ptag_63_32[0x20]; 9652 9653 u8 ptag_31_8[0x18]; 9654 u8 reserved_at_38[0x6]; 9655 u8 wr_en[0x1]; 9656 u8 rd_en[0x1]; 9657 }; 9658 9659 struct mlx5_ifc_query_wol_rol_out_bits { 9660 u8 status[0x8]; 9661 u8 reserved_at_8[0x18]; 9662 9663 u8 syndrome[0x20]; 9664 9665 u8 reserved_at_40[0x10]; 9666 u8 rol_mode[0x8]; 9667 u8 wol_mode[0x8]; 9668 9669 u8 reserved_at_60[0x20]; 9670 }; 9671 9672 struct mlx5_ifc_query_wol_rol_in_bits { 9673 u8 opcode[0x10]; 9674 u8 reserved_at_10[0x10]; 9675 9676 u8 reserved_at_20[0x10]; 9677 u8 op_mod[0x10]; 9678 9679 u8 reserved_at_40[0x40]; 9680 }; 9681 9682 struct mlx5_ifc_set_wol_rol_out_bits { 9683 u8 status[0x8]; 9684 u8 reserved_at_8[0x18]; 9685 9686 u8 syndrome[0x20]; 9687 9688 u8 reserved_at_40[0x40]; 9689 }; 9690 9691 struct mlx5_ifc_set_wol_rol_in_bits { 9692 u8 opcode[0x10]; 9693 u8 reserved_at_10[0x10]; 9694 9695 u8 reserved_at_20[0x10]; 9696 u8 op_mod[0x10]; 9697 9698 u8 rol_mode_valid[0x1]; 9699 u8 wol_mode_valid[0x1]; 9700 u8 reserved_at_42[0xe]; 9701 u8 rol_mode[0x8]; 9702 u8 wol_mode[0x8]; 9703 9704 u8 reserved_at_60[0x20]; 9705 }; 9706 9707 enum { 9708 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9709 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9710 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9711 }; 9712 9713 enum { 9714 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9715 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9716 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9717 }; 9718 9719 enum { 9720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9731 }; 9732 9733 struct mlx5_ifc_initial_seg_bits { 9734 u8 fw_rev_minor[0x10]; 9735 u8 fw_rev_major[0x10]; 9736 9737 u8 cmd_interface_rev[0x10]; 9738 u8 fw_rev_subminor[0x10]; 9739 9740 u8 reserved_at_40[0x40]; 9741 9742 u8 cmdq_phy_addr_63_32[0x20]; 9743 9744 u8 cmdq_phy_addr_31_12[0x14]; 9745 u8 reserved_at_b4[0x2]; 9746 u8 nic_interface[0x2]; 9747 u8 log_cmdq_size[0x4]; 9748 u8 log_cmdq_stride[0x4]; 9749 9750 u8 command_doorbell_vector[0x20]; 9751 9752 u8 reserved_at_e0[0xf00]; 9753 9754 u8 initializing[0x1]; 9755 u8 reserved_at_fe1[0x4]; 9756 u8 nic_interface_supported[0x3]; 9757 u8 embedded_cpu[0x1]; 9758 u8 reserved_at_fe9[0x17]; 9759 9760 struct mlx5_ifc_health_buffer_bits health_buffer; 9761 9762 u8 no_dram_nic_offset[0x20]; 9763 9764 u8 reserved_at_1220[0x6e40]; 9765 9766 u8 reserved_at_8060[0x1f]; 9767 u8 clear_int[0x1]; 9768 9769 u8 health_syndrome[0x8]; 9770 u8 health_counter[0x18]; 9771 9772 u8 reserved_at_80a0[0x17fc0]; 9773 }; 9774 9775 struct mlx5_ifc_mtpps_reg_bits { 9776 u8 reserved_at_0[0xc]; 9777 u8 cap_number_of_pps_pins[0x4]; 9778 u8 reserved_at_10[0x4]; 9779 u8 cap_max_num_of_pps_in_pins[0x4]; 9780 u8 reserved_at_18[0x4]; 9781 u8 cap_max_num_of_pps_out_pins[0x4]; 9782 9783 u8 reserved_at_20[0x24]; 9784 u8 cap_pin_3_mode[0x4]; 9785 u8 reserved_at_48[0x4]; 9786 u8 cap_pin_2_mode[0x4]; 9787 u8 reserved_at_50[0x4]; 9788 u8 cap_pin_1_mode[0x4]; 9789 u8 reserved_at_58[0x4]; 9790 u8 cap_pin_0_mode[0x4]; 9791 9792 u8 reserved_at_60[0x4]; 9793 u8 cap_pin_7_mode[0x4]; 9794 u8 reserved_at_68[0x4]; 9795 u8 cap_pin_6_mode[0x4]; 9796 u8 reserved_at_70[0x4]; 9797 u8 cap_pin_5_mode[0x4]; 9798 u8 reserved_at_78[0x4]; 9799 u8 cap_pin_4_mode[0x4]; 9800 9801 u8 field_select[0x20]; 9802 u8 reserved_at_a0[0x60]; 9803 9804 u8 enable[0x1]; 9805 u8 reserved_at_101[0xb]; 9806 u8 pattern[0x4]; 9807 u8 reserved_at_110[0x4]; 9808 u8 pin_mode[0x4]; 9809 u8 pin[0x8]; 9810 9811 u8 reserved_at_120[0x20]; 9812 9813 u8 time_stamp[0x40]; 9814 9815 u8 out_pulse_duration[0x10]; 9816 u8 out_periodic_adjustment[0x10]; 9817 u8 enhanced_out_periodic_adjustment[0x20]; 9818 9819 u8 reserved_at_1c0[0x20]; 9820 }; 9821 9822 struct mlx5_ifc_mtppse_reg_bits { 9823 u8 reserved_at_0[0x18]; 9824 u8 pin[0x8]; 9825 u8 event_arm[0x1]; 9826 u8 reserved_at_21[0x1b]; 9827 u8 event_generation_mode[0x4]; 9828 u8 reserved_at_40[0x40]; 9829 }; 9830 9831 struct mlx5_ifc_mcqs_reg_bits { 9832 u8 last_index_flag[0x1]; 9833 u8 reserved_at_1[0x7]; 9834 u8 fw_device[0x8]; 9835 u8 component_index[0x10]; 9836 9837 u8 reserved_at_20[0x10]; 9838 u8 identifier[0x10]; 9839 9840 u8 reserved_at_40[0x17]; 9841 u8 component_status[0x5]; 9842 u8 component_update_state[0x4]; 9843 9844 u8 last_update_state_changer_type[0x4]; 9845 u8 last_update_state_changer_host_id[0x4]; 9846 u8 reserved_at_68[0x18]; 9847 }; 9848 9849 struct mlx5_ifc_mcqi_cap_bits { 9850 u8 supported_info_bitmask[0x20]; 9851 9852 u8 component_size[0x20]; 9853 9854 u8 max_component_size[0x20]; 9855 9856 u8 log_mcda_word_size[0x4]; 9857 u8 reserved_at_64[0xc]; 9858 u8 mcda_max_write_size[0x10]; 9859 9860 u8 rd_en[0x1]; 9861 u8 reserved_at_81[0x1]; 9862 u8 match_chip_id[0x1]; 9863 u8 match_psid[0x1]; 9864 u8 check_user_timestamp[0x1]; 9865 u8 match_base_guid_mac[0x1]; 9866 u8 reserved_at_86[0x1a]; 9867 }; 9868 9869 struct mlx5_ifc_mcqi_version_bits { 9870 u8 reserved_at_0[0x2]; 9871 u8 build_time_valid[0x1]; 9872 u8 user_defined_time_valid[0x1]; 9873 u8 reserved_at_4[0x14]; 9874 u8 version_string_length[0x8]; 9875 9876 u8 version[0x20]; 9877 9878 u8 build_time[0x40]; 9879 9880 u8 user_defined_time[0x40]; 9881 9882 u8 build_tool_version[0x20]; 9883 9884 u8 reserved_at_e0[0x20]; 9885 9886 u8 version_string[92][0x8]; 9887 }; 9888 9889 struct mlx5_ifc_mcqi_activation_method_bits { 9890 u8 pending_server_ac_power_cycle[0x1]; 9891 u8 pending_server_dc_power_cycle[0x1]; 9892 u8 pending_server_reboot[0x1]; 9893 u8 pending_fw_reset[0x1]; 9894 u8 auto_activate[0x1]; 9895 u8 all_hosts_sync[0x1]; 9896 u8 device_hw_reset[0x1]; 9897 u8 reserved_at_7[0x19]; 9898 }; 9899 9900 union mlx5_ifc_mcqi_reg_data_bits { 9901 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9902 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9903 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9904 }; 9905 9906 struct mlx5_ifc_mcqi_reg_bits { 9907 u8 read_pending_component[0x1]; 9908 u8 reserved_at_1[0xf]; 9909 u8 component_index[0x10]; 9910 9911 u8 reserved_at_20[0x20]; 9912 9913 u8 reserved_at_40[0x1b]; 9914 u8 info_type[0x5]; 9915 9916 u8 info_size[0x20]; 9917 9918 u8 offset[0x20]; 9919 9920 u8 reserved_at_a0[0x10]; 9921 u8 data_size[0x10]; 9922 9923 union mlx5_ifc_mcqi_reg_data_bits data[]; 9924 }; 9925 9926 struct mlx5_ifc_mcc_reg_bits { 9927 u8 reserved_at_0[0x4]; 9928 u8 time_elapsed_since_last_cmd[0xc]; 9929 u8 reserved_at_10[0x8]; 9930 u8 instruction[0x8]; 9931 9932 u8 reserved_at_20[0x10]; 9933 u8 component_index[0x10]; 9934 9935 u8 reserved_at_40[0x8]; 9936 u8 update_handle[0x18]; 9937 9938 u8 handle_owner_type[0x4]; 9939 u8 handle_owner_host_id[0x4]; 9940 u8 reserved_at_68[0x1]; 9941 u8 control_progress[0x7]; 9942 u8 error_code[0x8]; 9943 u8 reserved_at_78[0x4]; 9944 u8 control_state[0x4]; 9945 9946 u8 component_size[0x20]; 9947 9948 u8 reserved_at_a0[0x60]; 9949 }; 9950 9951 struct mlx5_ifc_mcda_reg_bits { 9952 u8 reserved_at_0[0x8]; 9953 u8 update_handle[0x18]; 9954 9955 u8 offset[0x20]; 9956 9957 u8 reserved_at_40[0x10]; 9958 u8 size[0x10]; 9959 9960 u8 reserved_at_60[0x20]; 9961 9962 u8 data[][0x20]; 9963 }; 9964 9965 enum { 9966 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9967 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9968 }; 9969 9970 enum { 9971 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9972 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9973 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9974 }; 9975 9976 struct mlx5_ifc_mfrl_reg_bits { 9977 u8 reserved_at_0[0x20]; 9978 9979 u8 reserved_at_20[0x2]; 9980 u8 pci_sync_for_fw_update_start[0x1]; 9981 u8 pci_sync_for_fw_update_resp[0x2]; 9982 u8 rst_type_sel[0x3]; 9983 u8 reserved_at_28[0x8]; 9984 u8 reset_type[0x8]; 9985 u8 reset_level[0x8]; 9986 }; 9987 9988 struct mlx5_ifc_mirc_reg_bits { 9989 u8 reserved_at_0[0x18]; 9990 u8 status_code[0x8]; 9991 9992 u8 reserved_at_20[0x20]; 9993 }; 9994 9995 struct mlx5_ifc_pddr_monitor_opcode_bits { 9996 u8 reserved_at_0[0x10]; 9997 u8 monitor_opcode[0x10]; 9998 }; 9999 10000 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10001 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10002 u8 reserved_at_0[0x20]; 10003 }; 10004 10005 enum { 10006 /* Monitor opcodes */ 10007 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10008 }; 10009 10010 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10011 u8 reserved_at_0[0x10]; 10012 u8 group_opcode[0x10]; 10013 10014 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10015 10016 u8 reserved_at_40[0x20]; 10017 10018 u8 status_message[59][0x20]; 10019 }; 10020 10021 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10022 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10023 u8 reserved_at_0[0x7c0]; 10024 }; 10025 10026 enum { 10027 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10028 }; 10029 10030 struct mlx5_ifc_pddr_reg_bits { 10031 u8 reserved_at_0[0x8]; 10032 u8 local_port[0x8]; 10033 u8 pnat[0x2]; 10034 u8 reserved_at_12[0xe]; 10035 10036 u8 reserved_at_20[0x18]; 10037 u8 page_select[0x8]; 10038 10039 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10040 }; 10041 10042 union mlx5_ifc_ports_control_registers_document_bits { 10043 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10044 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10045 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10046 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10047 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10048 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10049 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10050 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10051 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10052 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10053 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10054 struct mlx5_ifc_paos_reg_bits paos_reg; 10055 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10056 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10057 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10058 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10059 struct mlx5_ifc_peir_reg_bits peir_reg; 10060 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10061 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10062 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10063 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10064 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10065 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10066 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10067 struct mlx5_ifc_plib_reg_bits plib_reg; 10068 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10069 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10070 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10071 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10072 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10073 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10074 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10075 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10076 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10077 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10078 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10079 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10080 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10081 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10082 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10083 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10084 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10085 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10086 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10087 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10088 struct mlx5_ifc_pude_reg_bits pude_reg; 10089 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10090 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10091 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10092 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10093 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10094 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10095 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10096 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10097 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10098 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10099 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10100 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10101 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10102 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10103 u8 reserved_at_0[0x60e0]; 10104 }; 10105 10106 union mlx5_ifc_debug_enhancements_document_bits { 10107 struct mlx5_ifc_health_buffer_bits health_buffer; 10108 u8 reserved_at_0[0x200]; 10109 }; 10110 10111 union mlx5_ifc_uplink_pci_interface_document_bits { 10112 struct mlx5_ifc_initial_seg_bits initial_seg; 10113 u8 reserved_at_0[0x20060]; 10114 }; 10115 10116 struct mlx5_ifc_set_flow_table_root_out_bits { 10117 u8 status[0x8]; 10118 u8 reserved_at_8[0x18]; 10119 10120 u8 syndrome[0x20]; 10121 10122 u8 reserved_at_40[0x40]; 10123 }; 10124 10125 struct mlx5_ifc_set_flow_table_root_in_bits { 10126 u8 opcode[0x10]; 10127 u8 reserved_at_10[0x10]; 10128 10129 u8 reserved_at_20[0x10]; 10130 u8 op_mod[0x10]; 10131 10132 u8 other_vport[0x1]; 10133 u8 reserved_at_41[0xf]; 10134 u8 vport_number[0x10]; 10135 10136 u8 reserved_at_60[0x20]; 10137 10138 u8 table_type[0x8]; 10139 u8 reserved_at_88[0x7]; 10140 u8 table_of_other_vport[0x1]; 10141 u8 table_vport_number[0x10]; 10142 10143 u8 reserved_at_a0[0x8]; 10144 u8 table_id[0x18]; 10145 10146 u8 reserved_at_c0[0x8]; 10147 u8 underlay_qpn[0x18]; 10148 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10149 u8 reserved_at_e1[0xf]; 10150 u8 table_eswitch_owner_vhca_id[0x10]; 10151 u8 reserved_at_100[0x100]; 10152 }; 10153 10154 enum { 10155 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10156 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10157 }; 10158 10159 struct mlx5_ifc_modify_flow_table_out_bits { 10160 u8 status[0x8]; 10161 u8 reserved_at_8[0x18]; 10162 10163 u8 syndrome[0x20]; 10164 10165 u8 reserved_at_40[0x40]; 10166 }; 10167 10168 struct mlx5_ifc_modify_flow_table_in_bits { 10169 u8 opcode[0x10]; 10170 u8 reserved_at_10[0x10]; 10171 10172 u8 reserved_at_20[0x10]; 10173 u8 op_mod[0x10]; 10174 10175 u8 other_vport[0x1]; 10176 u8 reserved_at_41[0xf]; 10177 u8 vport_number[0x10]; 10178 10179 u8 reserved_at_60[0x10]; 10180 u8 modify_field_select[0x10]; 10181 10182 u8 table_type[0x8]; 10183 u8 reserved_at_88[0x18]; 10184 10185 u8 reserved_at_a0[0x8]; 10186 u8 table_id[0x18]; 10187 10188 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10189 }; 10190 10191 struct mlx5_ifc_ets_tcn_config_reg_bits { 10192 u8 g[0x1]; 10193 u8 b[0x1]; 10194 u8 r[0x1]; 10195 u8 reserved_at_3[0x9]; 10196 u8 group[0x4]; 10197 u8 reserved_at_10[0x9]; 10198 u8 bw_allocation[0x7]; 10199 10200 u8 reserved_at_20[0xc]; 10201 u8 max_bw_units[0x4]; 10202 u8 reserved_at_30[0x8]; 10203 u8 max_bw_value[0x8]; 10204 }; 10205 10206 struct mlx5_ifc_ets_global_config_reg_bits { 10207 u8 reserved_at_0[0x2]; 10208 u8 r[0x1]; 10209 u8 reserved_at_3[0x1d]; 10210 10211 u8 reserved_at_20[0xc]; 10212 u8 max_bw_units[0x4]; 10213 u8 reserved_at_30[0x8]; 10214 u8 max_bw_value[0x8]; 10215 }; 10216 10217 struct mlx5_ifc_qetc_reg_bits { 10218 u8 reserved_at_0[0x8]; 10219 u8 port_number[0x8]; 10220 u8 reserved_at_10[0x30]; 10221 10222 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10223 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10224 }; 10225 10226 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10227 u8 e[0x1]; 10228 u8 reserved_at_01[0x0b]; 10229 u8 prio[0x04]; 10230 }; 10231 10232 struct mlx5_ifc_qpdpm_reg_bits { 10233 u8 reserved_at_0[0x8]; 10234 u8 local_port[0x8]; 10235 u8 reserved_at_10[0x10]; 10236 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10237 }; 10238 10239 struct mlx5_ifc_qpts_reg_bits { 10240 u8 reserved_at_0[0x8]; 10241 u8 local_port[0x8]; 10242 u8 reserved_at_10[0x2d]; 10243 u8 trust_state[0x3]; 10244 }; 10245 10246 struct mlx5_ifc_pptb_reg_bits { 10247 u8 reserved_at_0[0x2]; 10248 u8 mm[0x2]; 10249 u8 reserved_at_4[0x4]; 10250 u8 local_port[0x8]; 10251 u8 reserved_at_10[0x6]; 10252 u8 cm[0x1]; 10253 u8 um[0x1]; 10254 u8 pm[0x8]; 10255 10256 u8 prio_x_buff[0x20]; 10257 10258 u8 pm_msb[0x8]; 10259 u8 reserved_at_48[0x10]; 10260 u8 ctrl_buff[0x4]; 10261 u8 untagged_buff[0x4]; 10262 }; 10263 10264 struct mlx5_ifc_sbcam_reg_bits { 10265 u8 reserved_at_0[0x8]; 10266 u8 feature_group[0x8]; 10267 u8 reserved_at_10[0x8]; 10268 u8 access_reg_group[0x8]; 10269 10270 u8 reserved_at_20[0x20]; 10271 10272 u8 sb_access_reg_cap_mask[4][0x20]; 10273 10274 u8 reserved_at_c0[0x80]; 10275 10276 u8 sb_feature_cap_mask[4][0x20]; 10277 10278 u8 reserved_at_1c0[0x40]; 10279 10280 u8 cap_total_buffer_size[0x20]; 10281 10282 u8 cap_cell_size[0x10]; 10283 u8 cap_max_pg_buffers[0x8]; 10284 u8 cap_num_pool_supported[0x8]; 10285 10286 u8 reserved_at_240[0x8]; 10287 u8 cap_sbsr_stat_size[0x8]; 10288 u8 cap_max_tclass_data[0x8]; 10289 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10290 }; 10291 10292 struct mlx5_ifc_pbmc_reg_bits { 10293 u8 reserved_at_0[0x8]; 10294 u8 local_port[0x8]; 10295 u8 reserved_at_10[0x10]; 10296 10297 u8 xoff_timer_value[0x10]; 10298 u8 xoff_refresh[0x10]; 10299 10300 u8 reserved_at_40[0x9]; 10301 u8 fullness_threshold[0x7]; 10302 u8 port_buffer_size[0x10]; 10303 10304 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10305 10306 u8 reserved_at_2e0[0x80]; 10307 }; 10308 10309 struct mlx5_ifc_qtct_reg_bits { 10310 u8 reserved_at_0[0x8]; 10311 u8 port_number[0x8]; 10312 u8 reserved_at_10[0xd]; 10313 u8 prio[0x3]; 10314 10315 u8 reserved_at_20[0x1d]; 10316 u8 tclass[0x3]; 10317 }; 10318 10319 struct mlx5_ifc_mcia_reg_bits { 10320 u8 l[0x1]; 10321 u8 reserved_at_1[0x7]; 10322 u8 module[0x8]; 10323 u8 reserved_at_10[0x8]; 10324 u8 status[0x8]; 10325 10326 u8 i2c_device_address[0x8]; 10327 u8 page_number[0x8]; 10328 u8 device_address[0x10]; 10329 10330 u8 reserved_at_40[0x10]; 10331 u8 size[0x10]; 10332 10333 u8 reserved_at_60[0x20]; 10334 10335 u8 dword_0[0x20]; 10336 u8 dword_1[0x20]; 10337 u8 dword_2[0x20]; 10338 u8 dword_3[0x20]; 10339 u8 dword_4[0x20]; 10340 u8 dword_5[0x20]; 10341 u8 dword_6[0x20]; 10342 u8 dword_7[0x20]; 10343 u8 dword_8[0x20]; 10344 u8 dword_9[0x20]; 10345 u8 dword_10[0x20]; 10346 u8 dword_11[0x20]; 10347 }; 10348 10349 struct mlx5_ifc_dcbx_param_bits { 10350 u8 dcbx_cee_cap[0x1]; 10351 u8 dcbx_ieee_cap[0x1]; 10352 u8 dcbx_standby_cap[0x1]; 10353 u8 reserved_at_3[0x5]; 10354 u8 port_number[0x8]; 10355 u8 reserved_at_10[0xa]; 10356 u8 max_application_table_size[6]; 10357 u8 reserved_at_20[0x15]; 10358 u8 version_oper[0x3]; 10359 u8 reserved_at_38[5]; 10360 u8 version_admin[0x3]; 10361 u8 willing_admin[0x1]; 10362 u8 reserved_at_41[0x3]; 10363 u8 pfc_cap_oper[0x4]; 10364 u8 reserved_at_48[0x4]; 10365 u8 pfc_cap_admin[0x4]; 10366 u8 reserved_at_50[0x4]; 10367 u8 num_of_tc_oper[0x4]; 10368 u8 reserved_at_58[0x4]; 10369 u8 num_of_tc_admin[0x4]; 10370 u8 remote_willing[0x1]; 10371 u8 reserved_at_61[3]; 10372 u8 remote_pfc_cap[4]; 10373 u8 reserved_at_68[0x14]; 10374 u8 remote_num_of_tc[0x4]; 10375 u8 reserved_at_80[0x18]; 10376 u8 error[0x8]; 10377 u8 reserved_at_a0[0x160]; 10378 }; 10379 10380 struct mlx5_ifc_lagc_bits { 10381 u8 fdb_selection_mode[0x1]; 10382 u8 reserved_at_1[0x1c]; 10383 u8 lag_state[0x3]; 10384 10385 u8 reserved_at_20[0x14]; 10386 u8 tx_remap_affinity_2[0x4]; 10387 u8 reserved_at_38[0x4]; 10388 u8 tx_remap_affinity_1[0x4]; 10389 }; 10390 10391 struct mlx5_ifc_create_lag_out_bits { 10392 u8 status[0x8]; 10393 u8 reserved_at_8[0x18]; 10394 10395 u8 syndrome[0x20]; 10396 10397 u8 reserved_at_40[0x40]; 10398 }; 10399 10400 struct mlx5_ifc_create_lag_in_bits { 10401 u8 opcode[0x10]; 10402 u8 reserved_at_10[0x10]; 10403 10404 u8 reserved_at_20[0x10]; 10405 u8 op_mod[0x10]; 10406 10407 struct mlx5_ifc_lagc_bits ctx; 10408 }; 10409 10410 struct mlx5_ifc_modify_lag_out_bits { 10411 u8 status[0x8]; 10412 u8 reserved_at_8[0x18]; 10413 10414 u8 syndrome[0x20]; 10415 10416 u8 reserved_at_40[0x40]; 10417 }; 10418 10419 struct mlx5_ifc_modify_lag_in_bits { 10420 u8 opcode[0x10]; 10421 u8 reserved_at_10[0x10]; 10422 10423 u8 reserved_at_20[0x10]; 10424 u8 op_mod[0x10]; 10425 10426 u8 reserved_at_40[0x20]; 10427 u8 field_select[0x20]; 10428 10429 struct mlx5_ifc_lagc_bits ctx; 10430 }; 10431 10432 struct mlx5_ifc_query_lag_out_bits { 10433 u8 status[0x8]; 10434 u8 reserved_at_8[0x18]; 10435 10436 u8 syndrome[0x20]; 10437 10438 struct mlx5_ifc_lagc_bits ctx; 10439 }; 10440 10441 struct mlx5_ifc_query_lag_in_bits { 10442 u8 opcode[0x10]; 10443 u8 reserved_at_10[0x10]; 10444 10445 u8 reserved_at_20[0x10]; 10446 u8 op_mod[0x10]; 10447 10448 u8 reserved_at_40[0x40]; 10449 }; 10450 10451 struct mlx5_ifc_destroy_lag_out_bits { 10452 u8 status[0x8]; 10453 u8 reserved_at_8[0x18]; 10454 10455 u8 syndrome[0x20]; 10456 10457 u8 reserved_at_40[0x40]; 10458 }; 10459 10460 struct mlx5_ifc_destroy_lag_in_bits { 10461 u8 opcode[0x10]; 10462 u8 reserved_at_10[0x10]; 10463 10464 u8 reserved_at_20[0x10]; 10465 u8 op_mod[0x10]; 10466 10467 u8 reserved_at_40[0x40]; 10468 }; 10469 10470 struct mlx5_ifc_create_vport_lag_out_bits { 10471 u8 status[0x8]; 10472 u8 reserved_at_8[0x18]; 10473 10474 u8 syndrome[0x20]; 10475 10476 u8 reserved_at_40[0x40]; 10477 }; 10478 10479 struct mlx5_ifc_create_vport_lag_in_bits { 10480 u8 opcode[0x10]; 10481 u8 reserved_at_10[0x10]; 10482 10483 u8 reserved_at_20[0x10]; 10484 u8 op_mod[0x10]; 10485 10486 u8 reserved_at_40[0x40]; 10487 }; 10488 10489 struct mlx5_ifc_destroy_vport_lag_out_bits { 10490 u8 status[0x8]; 10491 u8 reserved_at_8[0x18]; 10492 10493 u8 syndrome[0x20]; 10494 10495 u8 reserved_at_40[0x40]; 10496 }; 10497 10498 struct mlx5_ifc_destroy_vport_lag_in_bits { 10499 u8 opcode[0x10]; 10500 u8 reserved_at_10[0x10]; 10501 10502 u8 reserved_at_20[0x10]; 10503 u8 op_mod[0x10]; 10504 10505 u8 reserved_at_40[0x40]; 10506 }; 10507 10508 enum { 10509 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10510 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10511 }; 10512 10513 struct mlx5_ifc_modify_memic_in_bits { 10514 u8 opcode[0x10]; 10515 u8 uid[0x10]; 10516 10517 u8 reserved_at_20[0x10]; 10518 u8 op_mod[0x10]; 10519 10520 u8 reserved_at_40[0x20]; 10521 10522 u8 reserved_at_60[0x18]; 10523 u8 memic_operation_type[0x8]; 10524 10525 u8 memic_start_addr[0x40]; 10526 10527 u8 reserved_at_c0[0x140]; 10528 }; 10529 10530 struct mlx5_ifc_modify_memic_out_bits { 10531 u8 status[0x8]; 10532 u8 reserved_at_8[0x18]; 10533 10534 u8 syndrome[0x20]; 10535 10536 u8 reserved_at_40[0x40]; 10537 10538 u8 memic_operation_addr[0x40]; 10539 10540 u8 reserved_at_c0[0x140]; 10541 }; 10542 10543 struct mlx5_ifc_alloc_memic_in_bits { 10544 u8 opcode[0x10]; 10545 u8 reserved_at_10[0x10]; 10546 10547 u8 reserved_at_20[0x10]; 10548 u8 op_mod[0x10]; 10549 10550 u8 reserved_at_30[0x20]; 10551 10552 u8 reserved_at_40[0x18]; 10553 u8 log_memic_addr_alignment[0x8]; 10554 10555 u8 range_start_addr[0x40]; 10556 10557 u8 range_size[0x20]; 10558 10559 u8 memic_size[0x20]; 10560 }; 10561 10562 struct mlx5_ifc_alloc_memic_out_bits { 10563 u8 status[0x8]; 10564 u8 reserved_at_8[0x18]; 10565 10566 u8 syndrome[0x20]; 10567 10568 u8 memic_start_addr[0x40]; 10569 }; 10570 10571 struct mlx5_ifc_dealloc_memic_in_bits { 10572 u8 opcode[0x10]; 10573 u8 reserved_at_10[0x10]; 10574 10575 u8 reserved_at_20[0x10]; 10576 u8 op_mod[0x10]; 10577 10578 u8 reserved_at_40[0x40]; 10579 10580 u8 memic_start_addr[0x40]; 10581 10582 u8 memic_size[0x20]; 10583 10584 u8 reserved_at_e0[0x20]; 10585 }; 10586 10587 struct mlx5_ifc_dealloc_memic_out_bits { 10588 u8 status[0x8]; 10589 u8 reserved_at_8[0x18]; 10590 10591 u8 syndrome[0x20]; 10592 10593 u8 reserved_at_40[0x40]; 10594 }; 10595 10596 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10597 u8 opcode[0x10]; 10598 u8 uid[0x10]; 10599 10600 u8 vhca_tunnel_id[0x10]; 10601 u8 obj_type[0x10]; 10602 10603 u8 obj_id[0x20]; 10604 10605 u8 reserved_at_60[0x20]; 10606 }; 10607 10608 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10609 u8 status[0x8]; 10610 u8 reserved_at_8[0x18]; 10611 10612 u8 syndrome[0x20]; 10613 10614 u8 obj_id[0x20]; 10615 10616 u8 reserved_at_60[0x20]; 10617 }; 10618 10619 struct mlx5_ifc_umem_bits { 10620 u8 reserved_at_0[0x80]; 10621 10622 u8 reserved_at_80[0x1b]; 10623 u8 log_page_size[0x5]; 10624 10625 u8 page_offset[0x20]; 10626 10627 u8 num_of_mtt[0x40]; 10628 10629 struct mlx5_ifc_mtt_bits mtt[]; 10630 }; 10631 10632 struct mlx5_ifc_uctx_bits { 10633 u8 cap[0x20]; 10634 10635 u8 reserved_at_20[0x160]; 10636 }; 10637 10638 struct mlx5_ifc_sw_icm_bits { 10639 u8 modify_field_select[0x40]; 10640 10641 u8 reserved_at_40[0x18]; 10642 u8 log_sw_icm_size[0x8]; 10643 10644 u8 reserved_at_60[0x20]; 10645 10646 u8 sw_icm_start_addr[0x40]; 10647 10648 u8 reserved_at_c0[0x140]; 10649 }; 10650 10651 struct mlx5_ifc_geneve_tlv_option_bits { 10652 u8 modify_field_select[0x40]; 10653 10654 u8 reserved_at_40[0x18]; 10655 u8 geneve_option_fte_index[0x8]; 10656 10657 u8 option_class[0x10]; 10658 u8 option_type[0x8]; 10659 u8 reserved_at_78[0x3]; 10660 u8 option_data_length[0x5]; 10661 10662 u8 reserved_at_80[0x180]; 10663 }; 10664 10665 struct mlx5_ifc_create_umem_in_bits { 10666 u8 opcode[0x10]; 10667 u8 uid[0x10]; 10668 10669 u8 reserved_at_20[0x10]; 10670 u8 op_mod[0x10]; 10671 10672 u8 reserved_at_40[0x40]; 10673 10674 struct mlx5_ifc_umem_bits umem; 10675 }; 10676 10677 struct mlx5_ifc_create_umem_out_bits { 10678 u8 status[0x8]; 10679 u8 reserved_at_8[0x18]; 10680 10681 u8 syndrome[0x20]; 10682 10683 u8 reserved_at_40[0x8]; 10684 u8 umem_id[0x18]; 10685 10686 u8 reserved_at_60[0x20]; 10687 }; 10688 10689 struct mlx5_ifc_destroy_umem_in_bits { 10690 u8 opcode[0x10]; 10691 u8 uid[0x10]; 10692 10693 u8 reserved_at_20[0x10]; 10694 u8 op_mod[0x10]; 10695 10696 u8 reserved_at_40[0x8]; 10697 u8 umem_id[0x18]; 10698 10699 u8 reserved_at_60[0x20]; 10700 }; 10701 10702 struct mlx5_ifc_destroy_umem_out_bits { 10703 u8 status[0x8]; 10704 u8 reserved_at_8[0x18]; 10705 10706 u8 syndrome[0x20]; 10707 10708 u8 reserved_at_40[0x40]; 10709 }; 10710 10711 struct mlx5_ifc_create_uctx_in_bits { 10712 u8 opcode[0x10]; 10713 u8 reserved_at_10[0x10]; 10714 10715 u8 reserved_at_20[0x10]; 10716 u8 op_mod[0x10]; 10717 10718 u8 reserved_at_40[0x40]; 10719 10720 struct mlx5_ifc_uctx_bits uctx; 10721 }; 10722 10723 struct mlx5_ifc_create_uctx_out_bits { 10724 u8 status[0x8]; 10725 u8 reserved_at_8[0x18]; 10726 10727 u8 syndrome[0x20]; 10728 10729 u8 reserved_at_40[0x10]; 10730 u8 uid[0x10]; 10731 10732 u8 reserved_at_60[0x20]; 10733 }; 10734 10735 struct mlx5_ifc_destroy_uctx_in_bits { 10736 u8 opcode[0x10]; 10737 u8 reserved_at_10[0x10]; 10738 10739 u8 reserved_at_20[0x10]; 10740 u8 op_mod[0x10]; 10741 10742 u8 reserved_at_40[0x10]; 10743 u8 uid[0x10]; 10744 10745 u8 reserved_at_60[0x20]; 10746 }; 10747 10748 struct mlx5_ifc_destroy_uctx_out_bits { 10749 u8 status[0x8]; 10750 u8 reserved_at_8[0x18]; 10751 10752 u8 syndrome[0x20]; 10753 10754 u8 reserved_at_40[0x40]; 10755 }; 10756 10757 struct mlx5_ifc_create_sw_icm_in_bits { 10758 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10759 struct mlx5_ifc_sw_icm_bits sw_icm; 10760 }; 10761 10762 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10763 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10764 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10765 }; 10766 10767 struct mlx5_ifc_mtrc_string_db_param_bits { 10768 u8 string_db_base_address[0x20]; 10769 10770 u8 reserved_at_20[0x8]; 10771 u8 string_db_size[0x18]; 10772 }; 10773 10774 struct mlx5_ifc_mtrc_cap_bits { 10775 u8 trace_owner[0x1]; 10776 u8 trace_to_memory[0x1]; 10777 u8 reserved_at_2[0x4]; 10778 u8 trc_ver[0x2]; 10779 u8 reserved_at_8[0x14]; 10780 u8 num_string_db[0x4]; 10781 10782 u8 first_string_trace[0x8]; 10783 u8 num_string_trace[0x8]; 10784 u8 reserved_at_30[0x28]; 10785 10786 u8 log_max_trace_buffer_size[0x8]; 10787 10788 u8 reserved_at_60[0x20]; 10789 10790 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10791 10792 u8 reserved_at_280[0x180]; 10793 }; 10794 10795 struct mlx5_ifc_mtrc_conf_bits { 10796 u8 reserved_at_0[0x1c]; 10797 u8 trace_mode[0x4]; 10798 u8 reserved_at_20[0x18]; 10799 u8 log_trace_buffer_size[0x8]; 10800 u8 trace_mkey[0x20]; 10801 u8 reserved_at_60[0x3a0]; 10802 }; 10803 10804 struct mlx5_ifc_mtrc_stdb_bits { 10805 u8 string_db_index[0x4]; 10806 u8 reserved_at_4[0x4]; 10807 u8 read_size[0x18]; 10808 u8 start_offset[0x20]; 10809 u8 string_db_data[]; 10810 }; 10811 10812 struct mlx5_ifc_mtrc_ctrl_bits { 10813 u8 trace_status[0x2]; 10814 u8 reserved_at_2[0x2]; 10815 u8 arm_event[0x1]; 10816 u8 reserved_at_5[0xb]; 10817 u8 modify_field_select[0x10]; 10818 u8 reserved_at_20[0x2b]; 10819 u8 current_timestamp52_32[0x15]; 10820 u8 current_timestamp31_0[0x20]; 10821 u8 reserved_at_80[0x180]; 10822 }; 10823 10824 struct mlx5_ifc_host_params_context_bits { 10825 u8 host_number[0x8]; 10826 u8 reserved_at_8[0x7]; 10827 u8 host_pf_disabled[0x1]; 10828 u8 host_num_of_vfs[0x10]; 10829 10830 u8 host_total_vfs[0x10]; 10831 u8 host_pci_bus[0x10]; 10832 10833 u8 reserved_at_40[0x10]; 10834 u8 host_pci_device[0x10]; 10835 10836 u8 reserved_at_60[0x10]; 10837 u8 host_pci_function[0x10]; 10838 10839 u8 reserved_at_80[0x180]; 10840 }; 10841 10842 struct mlx5_ifc_query_esw_functions_in_bits { 10843 u8 opcode[0x10]; 10844 u8 reserved_at_10[0x10]; 10845 10846 u8 reserved_at_20[0x10]; 10847 u8 op_mod[0x10]; 10848 10849 u8 reserved_at_40[0x40]; 10850 }; 10851 10852 struct mlx5_ifc_query_esw_functions_out_bits { 10853 u8 status[0x8]; 10854 u8 reserved_at_8[0x18]; 10855 10856 u8 syndrome[0x20]; 10857 10858 u8 reserved_at_40[0x40]; 10859 10860 struct mlx5_ifc_host_params_context_bits host_params_context; 10861 10862 u8 reserved_at_280[0x180]; 10863 u8 host_sf_enable[][0x40]; 10864 }; 10865 10866 struct mlx5_ifc_sf_partition_bits { 10867 u8 reserved_at_0[0x10]; 10868 u8 log_num_sf[0x8]; 10869 u8 log_sf_bar_size[0x8]; 10870 }; 10871 10872 struct mlx5_ifc_query_sf_partitions_out_bits { 10873 u8 status[0x8]; 10874 u8 reserved_at_8[0x18]; 10875 10876 u8 syndrome[0x20]; 10877 10878 u8 reserved_at_40[0x18]; 10879 u8 num_sf_partitions[0x8]; 10880 10881 u8 reserved_at_60[0x20]; 10882 10883 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10884 }; 10885 10886 struct mlx5_ifc_query_sf_partitions_in_bits { 10887 u8 opcode[0x10]; 10888 u8 reserved_at_10[0x10]; 10889 10890 u8 reserved_at_20[0x10]; 10891 u8 op_mod[0x10]; 10892 10893 u8 reserved_at_40[0x40]; 10894 }; 10895 10896 struct mlx5_ifc_dealloc_sf_out_bits { 10897 u8 status[0x8]; 10898 u8 reserved_at_8[0x18]; 10899 10900 u8 syndrome[0x20]; 10901 10902 u8 reserved_at_40[0x40]; 10903 }; 10904 10905 struct mlx5_ifc_dealloc_sf_in_bits { 10906 u8 opcode[0x10]; 10907 u8 reserved_at_10[0x10]; 10908 10909 u8 reserved_at_20[0x10]; 10910 u8 op_mod[0x10]; 10911 10912 u8 reserved_at_40[0x10]; 10913 u8 function_id[0x10]; 10914 10915 u8 reserved_at_60[0x20]; 10916 }; 10917 10918 struct mlx5_ifc_alloc_sf_out_bits { 10919 u8 status[0x8]; 10920 u8 reserved_at_8[0x18]; 10921 10922 u8 syndrome[0x20]; 10923 10924 u8 reserved_at_40[0x40]; 10925 }; 10926 10927 struct mlx5_ifc_alloc_sf_in_bits { 10928 u8 opcode[0x10]; 10929 u8 reserved_at_10[0x10]; 10930 10931 u8 reserved_at_20[0x10]; 10932 u8 op_mod[0x10]; 10933 10934 u8 reserved_at_40[0x10]; 10935 u8 function_id[0x10]; 10936 10937 u8 reserved_at_60[0x20]; 10938 }; 10939 10940 struct mlx5_ifc_affiliated_event_header_bits { 10941 u8 reserved_at_0[0x10]; 10942 u8 obj_type[0x10]; 10943 10944 u8 obj_id[0x20]; 10945 }; 10946 10947 enum { 10948 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10949 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10950 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10951 }; 10952 10953 enum { 10954 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10955 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10956 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10957 }; 10958 10959 enum { 10960 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10961 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10962 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10963 }; 10964 10965 struct mlx5_ifc_ipsec_obj_bits { 10966 u8 modify_field_select[0x40]; 10967 u8 full_offload[0x1]; 10968 u8 reserved_at_41[0x1]; 10969 u8 esn_en[0x1]; 10970 u8 esn_overlap[0x1]; 10971 u8 reserved_at_44[0x2]; 10972 u8 icv_length[0x2]; 10973 u8 reserved_at_48[0x4]; 10974 u8 aso_return_reg[0x4]; 10975 u8 reserved_at_50[0x10]; 10976 10977 u8 esn_msb[0x20]; 10978 10979 u8 reserved_at_80[0x8]; 10980 u8 dekn[0x18]; 10981 10982 u8 salt[0x20]; 10983 10984 u8 implicit_iv[0x40]; 10985 10986 u8 reserved_at_100[0x700]; 10987 }; 10988 10989 struct mlx5_ifc_create_ipsec_obj_in_bits { 10990 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10991 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10992 }; 10993 10994 enum { 10995 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10996 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10997 }; 10998 10999 struct mlx5_ifc_query_ipsec_obj_out_bits { 11000 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11001 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11002 }; 11003 11004 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11005 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11006 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11007 }; 11008 11009 struct mlx5_ifc_encryption_key_obj_bits { 11010 u8 modify_field_select[0x40]; 11011 11012 u8 reserved_at_40[0x14]; 11013 u8 key_size[0x4]; 11014 u8 reserved_at_58[0x4]; 11015 u8 key_type[0x4]; 11016 11017 u8 reserved_at_60[0x8]; 11018 u8 pd[0x18]; 11019 11020 u8 reserved_at_80[0x180]; 11021 u8 key[8][0x20]; 11022 11023 u8 reserved_at_300[0x500]; 11024 }; 11025 11026 struct mlx5_ifc_create_encryption_key_in_bits { 11027 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11028 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11029 }; 11030 11031 struct mlx5_ifc_sampler_obj_bits { 11032 u8 modify_field_select[0x40]; 11033 11034 u8 table_type[0x8]; 11035 u8 level[0x8]; 11036 u8 reserved_at_50[0xf]; 11037 u8 ignore_flow_level[0x1]; 11038 11039 u8 sample_ratio[0x20]; 11040 11041 u8 reserved_at_80[0x8]; 11042 u8 sample_table_id[0x18]; 11043 11044 u8 reserved_at_a0[0x8]; 11045 u8 default_table_id[0x18]; 11046 11047 u8 sw_steering_icm_address_rx[0x40]; 11048 u8 sw_steering_icm_address_tx[0x40]; 11049 11050 u8 reserved_at_140[0xa0]; 11051 }; 11052 11053 struct mlx5_ifc_create_sampler_obj_in_bits { 11054 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11055 struct mlx5_ifc_sampler_obj_bits sampler_object; 11056 }; 11057 11058 enum { 11059 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11060 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11061 }; 11062 11063 enum { 11064 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11065 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11066 }; 11067 11068 struct mlx5_ifc_tls_static_params_bits { 11069 u8 const_2[0x2]; 11070 u8 tls_version[0x4]; 11071 u8 const_1[0x2]; 11072 u8 reserved_at_8[0x14]; 11073 u8 encryption_standard[0x4]; 11074 11075 u8 reserved_at_20[0x20]; 11076 11077 u8 initial_record_number[0x40]; 11078 11079 u8 resync_tcp_sn[0x20]; 11080 11081 u8 gcm_iv[0x20]; 11082 11083 u8 implicit_iv[0x40]; 11084 11085 u8 reserved_at_100[0x8]; 11086 u8 dek_index[0x18]; 11087 11088 u8 reserved_at_120[0xe0]; 11089 }; 11090 11091 struct mlx5_ifc_tls_progress_params_bits { 11092 u8 next_record_tcp_sn[0x20]; 11093 11094 u8 hw_resync_tcp_sn[0x20]; 11095 11096 u8 record_tracker_state[0x2]; 11097 u8 auth_state[0x2]; 11098 u8 reserved_at_44[0x4]; 11099 u8 hw_offset_record_number[0x18]; 11100 }; 11101 11102 enum { 11103 MLX5_MTT_PERM_READ = 1 << 0, 11104 MLX5_MTT_PERM_WRITE = 1 << 1, 11105 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11106 }; 11107 11108 #endif /* MLX5_IFC_H */ 11109