1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_CREATE_MKEY = 0x200, 129 MLX5_CMD_OP_QUERY_MKEY = 0x201, 130 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 131 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 132 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 133 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 134 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 135 MLX5_CMD_OP_CREATE_EQ = 0x301, 136 MLX5_CMD_OP_DESTROY_EQ = 0x302, 137 MLX5_CMD_OP_QUERY_EQ = 0x303, 138 MLX5_CMD_OP_GEN_EQE = 0x304, 139 MLX5_CMD_OP_CREATE_CQ = 0x400, 140 MLX5_CMD_OP_DESTROY_CQ = 0x401, 141 MLX5_CMD_OP_QUERY_CQ = 0x402, 142 MLX5_CMD_OP_MODIFY_CQ = 0x403, 143 MLX5_CMD_OP_CREATE_QP = 0x500, 144 MLX5_CMD_OP_DESTROY_QP = 0x501, 145 MLX5_CMD_OP_RST2INIT_QP = 0x502, 146 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 147 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 148 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 149 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 150 MLX5_CMD_OP_2ERR_QP = 0x507, 151 MLX5_CMD_OP_2RST_QP = 0x50a, 152 MLX5_CMD_OP_QUERY_QP = 0x50b, 153 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 154 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 155 MLX5_CMD_OP_CREATE_PSV = 0x600, 156 MLX5_CMD_OP_DESTROY_PSV = 0x601, 157 MLX5_CMD_OP_CREATE_SRQ = 0x700, 158 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 159 MLX5_CMD_OP_QUERY_SRQ = 0x702, 160 MLX5_CMD_OP_ARM_RQ = 0x703, 161 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 162 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 163 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 164 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 165 MLX5_CMD_OP_CREATE_DCT = 0x710, 166 MLX5_CMD_OP_DESTROY_DCT = 0x711, 167 MLX5_CMD_OP_DRAIN_DCT = 0x712, 168 MLX5_CMD_OP_QUERY_DCT = 0x713, 169 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 170 MLX5_CMD_OP_CREATE_XRQ = 0x717, 171 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 172 MLX5_CMD_OP_QUERY_XRQ = 0x719, 173 MLX5_CMD_OP_ARM_XRQ = 0x71a, 174 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 175 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 176 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 177 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 178 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 179 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 180 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 181 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 182 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 183 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 184 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 185 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 186 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 187 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 188 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 189 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 192 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 193 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 194 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 195 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 196 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 197 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 198 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 199 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 200 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 201 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 202 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 203 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 204 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 205 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 206 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 207 MLX5_CMD_OP_ALLOC_PD = 0x800, 208 MLX5_CMD_OP_DEALLOC_PD = 0x801, 209 MLX5_CMD_OP_ALLOC_UAR = 0x802, 210 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 211 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 212 MLX5_CMD_OP_ACCESS_REG = 0x805, 213 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 214 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 215 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 216 MLX5_CMD_OP_MAD_IFC = 0x50d, 217 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 218 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 219 MLX5_CMD_OP_NOP = 0x80d, 220 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 221 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 222 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 223 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 224 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 225 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 226 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 227 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 228 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 229 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 230 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 231 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 232 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 233 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 234 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 235 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 236 MLX5_CMD_OP_CREATE_LAG = 0x840, 237 MLX5_CMD_OP_MODIFY_LAG = 0x841, 238 MLX5_CMD_OP_QUERY_LAG = 0x842, 239 MLX5_CMD_OP_DESTROY_LAG = 0x843, 240 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 241 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 242 MLX5_CMD_OP_CREATE_TIR = 0x900, 243 MLX5_CMD_OP_MODIFY_TIR = 0x901, 244 MLX5_CMD_OP_DESTROY_TIR = 0x902, 245 MLX5_CMD_OP_QUERY_TIR = 0x903, 246 MLX5_CMD_OP_CREATE_SQ = 0x904, 247 MLX5_CMD_OP_MODIFY_SQ = 0x905, 248 MLX5_CMD_OP_DESTROY_SQ = 0x906, 249 MLX5_CMD_OP_QUERY_SQ = 0x907, 250 MLX5_CMD_OP_CREATE_RQ = 0x908, 251 MLX5_CMD_OP_MODIFY_RQ = 0x909, 252 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 253 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 254 MLX5_CMD_OP_QUERY_RQ = 0x90b, 255 MLX5_CMD_OP_CREATE_RMP = 0x90c, 256 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 257 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 258 MLX5_CMD_OP_QUERY_RMP = 0x90f, 259 MLX5_CMD_OP_CREATE_TIS = 0x912, 260 MLX5_CMD_OP_MODIFY_TIS = 0x913, 261 MLX5_CMD_OP_DESTROY_TIS = 0x914, 262 MLX5_CMD_OP_QUERY_TIS = 0x915, 263 MLX5_CMD_OP_CREATE_RQT = 0x916, 264 MLX5_CMD_OP_MODIFY_RQT = 0x917, 265 MLX5_CMD_OP_DESTROY_RQT = 0x918, 266 MLX5_CMD_OP_QUERY_RQT = 0x919, 267 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 268 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 269 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 270 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 271 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 272 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 273 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 274 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 276 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 277 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 278 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 279 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 280 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 281 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 282 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 283 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 284 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 285 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 286 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 287 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 288 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 289 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 290 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 291 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 292 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 293 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 294 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 295 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 296 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 297 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 298 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 299 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 300 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 301 MLX5_CMD_OP_MAX 302 }; 303 304 /* Valid range for general commands that don't work over an object */ 305 enum { 306 MLX5_CMD_OP_GENERAL_START = 0xb00, 307 MLX5_CMD_OP_GENERAL_END = 0xd00, 308 }; 309 310 struct mlx5_ifc_flow_table_fields_supported_bits { 311 u8 outer_dmac[0x1]; 312 u8 outer_smac[0x1]; 313 u8 outer_ether_type[0x1]; 314 u8 outer_ip_version[0x1]; 315 u8 outer_first_prio[0x1]; 316 u8 outer_first_cfi[0x1]; 317 u8 outer_first_vid[0x1]; 318 u8 outer_ipv4_ttl[0x1]; 319 u8 outer_second_prio[0x1]; 320 u8 outer_second_cfi[0x1]; 321 u8 outer_second_vid[0x1]; 322 u8 reserved_at_b[0x1]; 323 u8 outer_sip[0x1]; 324 u8 outer_dip[0x1]; 325 u8 outer_frag[0x1]; 326 u8 outer_ip_protocol[0x1]; 327 u8 outer_ip_ecn[0x1]; 328 u8 outer_ip_dscp[0x1]; 329 u8 outer_udp_sport[0x1]; 330 u8 outer_udp_dport[0x1]; 331 u8 outer_tcp_sport[0x1]; 332 u8 outer_tcp_dport[0x1]; 333 u8 outer_tcp_flags[0x1]; 334 u8 outer_gre_protocol[0x1]; 335 u8 outer_gre_key[0x1]; 336 u8 outer_vxlan_vni[0x1]; 337 u8 outer_geneve_vni[0x1]; 338 u8 outer_geneve_oam[0x1]; 339 u8 outer_geneve_protocol_type[0x1]; 340 u8 outer_geneve_opt_len[0x1]; 341 u8 reserved_at_1e[0x1]; 342 u8 source_eswitch_port[0x1]; 343 344 u8 inner_dmac[0x1]; 345 u8 inner_smac[0x1]; 346 u8 inner_ether_type[0x1]; 347 u8 inner_ip_version[0x1]; 348 u8 inner_first_prio[0x1]; 349 u8 inner_first_cfi[0x1]; 350 u8 inner_first_vid[0x1]; 351 u8 reserved_at_27[0x1]; 352 u8 inner_second_prio[0x1]; 353 u8 inner_second_cfi[0x1]; 354 u8 inner_second_vid[0x1]; 355 u8 reserved_at_2b[0x1]; 356 u8 inner_sip[0x1]; 357 u8 inner_dip[0x1]; 358 u8 inner_frag[0x1]; 359 u8 inner_ip_protocol[0x1]; 360 u8 inner_ip_ecn[0x1]; 361 u8 inner_ip_dscp[0x1]; 362 u8 inner_udp_sport[0x1]; 363 u8 inner_udp_dport[0x1]; 364 u8 inner_tcp_sport[0x1]; 365 u8 inner_tcp_dport[0x1]; 366 u8 inner_tcp_flags[0x1]; 367 u8 reserved_at_37[0x9]; 368 369 u8 geneve_tlv_option_0_data[0x1]; 370 u8 reserved_at_41[0x4]; 371 u8 outer_first_mpls_over_udp[0x4]; 372 u8 outer_first_mpls_over_gre[0x4]; 373 u8 inner_first_mpls[0x4]; 374 u8 outer_first_mpls[0x4]; 375 u8 reserved_at_55[0x2]; 376 u8 outer_esp_spi[0x1]; 377 u8 reserved_at_58[0x2]; 378 u8 bth_dst_qp[0x1]; 379 u8 reserved_at_5b[0x5]; 380 381 u8 reserved_at_60[0x18]; 382 u8 metadata_reg_c_7[0x1]; 383 u8 metadata_reg_c_6[0x1]; 384 u8 metadata_reg_c_5[0x1]; 385 u8 metadata_reg_c_4[0x1]; 386 u8 metadata_reg_c_3[0x1]; 387 u8 metadata_reg_c_2[0x1]; 388 u8 metadata_reg_c_1[0x1]; 389 u8 metadata_reg_c_0[0x1]; 390 }; 391 392 struct mlx5_ifc_flow_table_prop_layout_bits { 393 u8 ft_support[0x1]; 394 u8 reserved_at_1[0x1]; 395 u8 flow_counter[0x1]; 396 u8 flow_modify_en[0x1]; 397 u8 modify_root[0x1]; 398 u8 identified_miss_table_mode[0x1]; 399 u8 flow_table_modify[0x1]; 400 u8 reformat[0x1]; 401 u8 decap[0x1]; 402 u8 reserved_at_9[0x1]; 403 u8 pop_vlan[0x1]; 404 u8 push_vlan[0x1]; 405 u8 reserved_at_c[0x1]; 406 u8 pop_vlan_2[0x1]; 407 u8 push_vlan_2[0x1]; 408 u8 reformat_and_vlan_action[0x1]; 409 u8 reserved_at_10[0x1]; 410 u8 sw_owner[0x1]; 411 u8 reformat_l3_tunnel_to_l2[0x1]; 412 u8 reformat_l2_to_l3_tunnel[0x1]; 413 u8 reformat_and_modify_action[0x1]; 414 u8 ignore_flow_level[0x1]; 415 u8 reserved_at_16[0x1]; 416 u8 table_miss_action_domain[0x1]; 417 u8 termination_table[0x1]; 418 u8 reformat_and_fwd_to_table[0x1]; 419 u8 reserved_at_1a[0x2]; 420 u8 ipsec_encrypt[0x1]; 421 u8 ipsec_decrypt[0x1]; 422 u8 reserved_at_1e[0x2]; 423 424 u8 termination_table_raw_traffic[0x1]; 425 u8 reserved_at_21[0x1]; 426 u8 log_max_ft_size[0x6]; 427 u8 log_max_modify_header_context[0x8]; 428 u8 max_modify_header_actions[0x8]; 429 u8 max_ft_level[0x8]; 430 431 u8 reserved_at_40[0x20]; 432 433 u8 reserved_at_60[0x18]; 434 u8 log_max_ft_num[0x8]; 435 436 u8 reserved_at_80[0x18]; 437 u8 log_max_destination[0x8]; 438 439 u8 log_max_flow_counter[0x8]; 440 u8 reserved_at_a8[0x10]; 441 u8 log_max_flow[0x8]; 442 443 u8 reserved_at_c0[0x40]; 444 445 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 446 447 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 448 }; 449 450 struct mlx5_ifc_odp_per_transport_service_cap_bits { 451 u8 send[0x1]; 452 u8 receive[0x1]; 453 u8 write[0x1]; 454 u8 read[0x1]; 455 u8 atomic[0x1]; 456 u8 srq_receive[0x1]; 457 u8 reserved_at_6[0x1a]; 458 }; 459 460 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 461 u8 smac_47_16[0x20]; 462 463 u8 smac_15_0[0x10]; 464 u8 ethertype[0x10]; 465 466 u8 dmac_47_16[0x20]; 467 468 u8 dmac_15_0[0x10]; 469 u8 first_prio[0x3]; 470 u8 first_cfi[0x1]; 471 u8 first_vid[0xc]; 472 473 u8 ip_protocol[0x8]; 474 u8 ip_dscp[0x6]; 475 u8 ip_ecn[0x2]; 476 u8 cvlan_tag[0x1]; 477 u8 svlan_tag[0x1]; 478 u8 frag[0x1]; 479 u8 ip_version[0x4]; 480 u8 tcp_flags[0x9]; 481 482 u8 tcp_sport[0x10]; 483 u8 tcp_dport[0x10]; 484 485 u8 reserved_at_c0[0x18]; 486 u8 ttl_hoplimit[0x8]; 487 488 u8 udp_sport[0x10]; 489 u8 udp_dport[0x10]; 490 491 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 492 493 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 494 }; 495 496 struct mlx5_ifc_nvgre_key_bits { 497 u8 hi[0x18]; 498 u8 lo[0x8]; 499 }; 500 501 union mlx5_ifc_gre_key_bits { 502 struct mlx5_ifc_nvgre_key_bits nvgre; 503 u8 key[0x20]; 504 }; 505 506 struct mlx5_ifc_fte_match_set_misc_bits { 507 u8 gre_c_present[0x1]; 508 u8 reserved_at_1[0x1]; 509 u8 gre_k_present[0x1]; 510 u8 gre_s_present[0x1]; 511 u8 source_vhca_port[0x4]; 512 u8 source_sqn[0x18]; 513 514 u8 source_eswitch_owner_vhca_id[0x10]; 515 u8 source_port[0x10]; 516 517 u8 outer_second_prio[0x3]; 518 u8 outer_second_cfi[0x1]; 519 u8 outer_second_vid[0xc]; 520 u8 inner_second_prio[0x3]; 521 u8 inner_second_cfi[0x1]; 522 u8 inner_second_vid[0xc]; 523 524 u8 outer_second_cvlan_tag[0x1]; 525 u8 inner_second_cvlan_tag[0x1]; 526 u8 outer_second_svlan_tag[0x1]; 527 u8 inner_second_svlan_tag[0x1]; 528 u8 reserved_at_64[0xc]; 529 u8 gre_protocol[0x10]; 530 531 union mlx5_ifc_gre_key_bits gre_key; 532 533 u8 vxlan_vni[0x18]; 534 u8 reserved_at_b8[0x8]; 535 536 u8 geneve_vni[0x18]; 537 u8 reserved_at_d8[0x7]; 538 u8 geneve_oam[0x1]; 539 540 u8 reserved_at_e0[0xc]; 541 u8 outer_ipv6_flow_label[0x14]; 542 543 u8 reserved_at_100[0xc]; 544 u8 inner_ipv6_flow_label[0x14]; 545 546 u8 reserved_at_120[0xa]; 547 u8 geneve_opt_len[0x6]; 548 u8 geneve_protocol_type[0x10]; 549 550 u8 reserved_at_140[0x8]; 551 u8 bth_dst_qp[0x18]; 552 u8 reserved_at_160[0x20]; 553 u8 outer_esp_spi[0x20]; 554 u8 reserved_at_1a0[0x60]; 555 }; 556 557 struct mlx5_ifc_fte_match_mpls_bits { 558 u8 mpls_label[0x14]; 559 u8 mpls_exp[0x3]; 560 u8 mpls_s_bos[0x1]; 561 u8 mpls_ttl[0x8]; 562 }; 563 564 struct mlx5_ifc_fte_match_set_misc2_bits { 565 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 566 567 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 568 569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 570 571 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 572 573 u8 metadata_reg_c_7[0x20]; 574 575 u8 metadata_reg_c_6[0x20]; 576 577 u8 metadata_reg_c_5[0x20]; 578 579 u8 metadata_reg_c_4[0x20]; 580 581 u8 metadata_reg_c_3[0x20]; 582 583 u8 metadata_reg_c_2[0x20]; 584 585 u8 metadata_reg_c_1[0x20]; 586 587 u8 metadata_reg_c_0[0x20]; 588 589 u8 metadata_reg_a[0x20]; 590 591 u8 reserved_at_1a0[0x60]; 592 }; 593 594 struct mlx5_ifc_fte_match_set_misc3_bits { 595 u8 inner_tcp_seq_num[0x20]; 596 597 u8 outer_tcp_seq_num[0x20]; 598 599 u8 inner_tcp_ack_num[0x20]; 600 601 u8 outer_tcp_ack_num[0x20]; 602 603 u8 reserved_at_80[0x8]; 604 u8 outer_vxlan_gpe_vni[0x18]; 605 606 u8 outer_vxlan_gpe_next_protocol[0x8]; 607 u8 outer_vxlan_gpe_flags[0x8]; 608 u8 reserved_at_b0[0x10]; 609 610 u8 icmp_header_data[0x20]; 611 612 u8 icmpv6_header_data[0x20]; 613 614 u8 icmp_type[0x8]; 615 u8 icmp_code[0x8]; 616 u8 icmpv6_type[0x8]; 617 u8 icmpv6_code[0x8]; 618 619 u8 geneve_tlv_option_0_data[0x20]; 620 621 u8 reserved_at_140[0xc0]; 622 }; 623 624 struct mlx5_ifc_cmd_pas_bits { 625 u8 pa_h[0x20]; 626 627 u8 pa_l[0x14]; 628 u8 reserved_at_34[0xc]; 629 }; 630 631 struct mlx5_ifc_uint64_bits { 632 u8 hi[0x20]; 633 634 u8 lo[0x20]; 635 }; 636 637 enum { 638 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 639 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 640 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 641 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 642 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 643 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 644 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 645 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 646 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 647 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 648 }; 649 650 struct mlx5_ifc_ads_bits { 651 u8 fl[0x1]; 652 u8 free_ar[0x1]; 653 u8 reserved_at_2[0xe]; 654 u8 pkey_index[0x10]; 655 656 u8 reserved_at_20[0x8]; 657 u8 grh[0x1]; 658 u8 mlid[0x7]; 659 u8 rlid[0x10]; 660 661 u8 ack_timeout[0x5]; 662 u8 reserved_at_45[0x3]; 663 u8 src_addr_index[0x8]; 664 u8 reserved_at_50[0x4]; 665 u8 stat_rate[0x4]; 666 u8 hop_limit[0x8]; 667 668 u8 reserved_at_60[0x4]; 669 u8 tclass[0x8]; 670 u8 flow_label[0x14]; 671 672 u8 rgid_rip[16][0x8]; 673 674 u8 reserved_at_100[0x4]; 675 u8 f_dscp[0x1]; 676 u8 f_ecn[0x1]; 677 u8 reserved_at_106[0x1]; 678 u8 f_eth_prio[0x1]; 679 u8 ecn[0x2]; 680 u8 dscp[0x6]; 681 u8 udp_sport[0x10]; 682 683 u8 dei_cfi[0x1]; 684 u8 eth_prio[0x3]; 685 u8 sl[0x4]; 686 u8 vhca_port_num[0x8]; 687 u8 rmac_47_32[0x10]; 688 689 u8 rmac_31_0[0x20]; 690 }; 691 692 struct mlx5_ifc_flow_table_nic_cap_bits { 693 u8 nic_rx_multi_path_tirs[0x1]; 694 u8 nic_rx_multi_path_tirs_fts[0x1]; 695 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 696 u8 reserved_at_3[0x4]; 697 u8 sw_owner_reformat_supported[0x1]; 698 u8 reserved_at_8[0x18]; 699 700 u8 encap_general_header[0x1]; 701 u8 reserved_at_21[0xa]; 702 u8 log_max_packet_reformat_context[0x5]; 703 u8 reserved_at_30[0x6]; 704 u8 max_encap_header_size[0xa]; 705 u8 reserved_at_40[0x1c0]; 706 707 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 708 709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 710 711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 712 713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 714 715 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 716 717 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 718 719 u8 reserved_at_e00[0x1200]; 720 721 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 722 723 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 724 725 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 726 727 u8 reserved_at_20c0[0x5f40]; 728 }; 729 730 enum { 731 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 732 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 733 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 734 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 735 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 736 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 737 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 738 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 739 }; 740 741 struct mlx5_ifc_flow_table_eswitch_cap_bits { 742 u8 fdb_to_vport_reg_c_id[0x8]; 743 u8 reserved_at_8[0xd]; 744 u8 fdb_modify_header_fwd_to_table[0x1]; 745 u8 reserved_at_16[0x1]; 746 u8 flow_source[0x1]; 747 u8 reserved_at_18[0x2]; 748 u8 multi_fdb_encap[0x1]; 749 u8 egress_acl_forward_to_vport[0x1]; 750 u8 fdb_multi_path_to_table[0x1]; 751 u8 reserved_at_1d[0x3]; 752 753 u8 reserved_at_20[0x1e0]; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 758 759 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 760 761 u8 reserved_at_800[0x1000]; 762 763 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 764 765 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 766 767 u8 sw_steering_uplink_icm_address_rx[0x40]; 768 769 u8 sw_steering_uplink_icm_address_tx[0x40]; 770 771 u8 reserved_at_1900[0x6700]; 772 }; 773 774 enum { 775 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 776 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 777 }; 778 779 struct mlx5_ifc_e_switch_cap_bits { 780 u8 vport_svlan_strip[0x1]; 781 u8 vport_cvlan_strip[0x1]; 782 u8 vport_svlan_insert[0x1]; 783 u8 vport_cvlan_insert_if_not_exist[0x1]; 784 u8 vport_cvlan_insert_overwrite[0x1]; 785 u8 reserved_at_5[0x3]; 786 u8 esw_uplink_ingress_acl[0x1]; 787 u8 reserved_at_9[0x10]; 788 u8 esw_functions_changed[0x1]; 789 u8 reserved_at_1a[0x1]; 790 u8 ecpf_vport_exists[0x1]; 791 u8 counter_eswitch_affinity[0x1]; 792 u8 merged_eswitch[0x1]; 793 u8 nic_vport_node_guid_modify[0x1]; 794 u8 nic_vport_port_guid_modify[0x1]; 795 796 u8 vxlan_encap_decap[0x1]; 797 u8 nvgre_encap_decap[0x1]; 798 u8 reserved_at_22[0x1]; 799 u8 log_max_fdb_encap_uplink[0x5]; 800 u8 reserved_at_21[0x3]; 801 u8 log_max_packet_reformat_context[0x5]; 802 u8 reserved_2b[0x6]; 803 u8 max_encap_header_size[0xa]; 804 805 u8 reserved_at_40[0xb]; 806 u8 log_max_esw_sf[0x5]; 807 u8 esw_sf_base_id[0x10]; 808 809 u8 reserved_at_60[0x7a0]; 810 811 }; 812 813 struct mlx5_ifc_qos_cap_bits { 814 u8 packet_pacing[0x1]; 815 u8 esw_scheduling[0x1]; 816 u8 esw_bw_share[0x1]; 817 u8 esw_rate_limit[0x1]; 818 u8 reserved_at_4[0x1]; 819 u8 packet_pacing_burst_bound[0x1]; 820 u8 packet_pacing_typical_size[0x1]; 821 u8 reserved_at_7[0x4]; 822 u8 packet_pacing_uid[0x1]; 823 u8 reserved_at_c[0x14]; 824 825 u8 reserved_at_20[0x20]; 826 827 u8 packet_pacing_max_rate[0x20]; 828 829 u8 packet_pacing_min_rate[0x20]; 830 831 u8 reserved_at_80[0x10]; 832 u8 packet_pacing_rate_table_size[0x10]; 833 834 u8 esw_element_type[0x10]; 835 u8 esw_tsar_type[0x10]; 836 837 u8 reserved_at_c0[0x10]; 838 u8 max_qos_para_vport[0x10]; 839 840 u8 max_tsar_bw_share[0x20]; 841 842 u8 reserved_at_100[0x700]; 843 }; 844 845 struct mlx5_ifc_debug_cap_bits { 846 u8 core_dump_general[0x1]; 847 u8 core_dump_qp[0x1]; 848 u8 reserved_at_2[0x7]; 849 u8 resource_dump[0x1]; 850 u8 reserved_at_a[0x16]; 851 852 u8 reserved_at_20[0x2]; 853 u8 stall_detect[0x1]; 854 u8 reserved_at_23[0x1d]; 855 856 u8 reserved_at_40[0x7c0]; 857 }; 858 859 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 860 u8 csum_cap[0x1]; 861 u8 vlan_cap[0x1]; 862 u8 lro_cap[0x1]; 863 u8 lro_psh_flag[0x1]; 864 u8 lro_time_stamp[0x1]; 865 u8 reserved_at_5[0x2]; 866 u8 wqe_vlan_insert[0x1]; 867 u8 self_lb_en_modifiable[0x1]; 868 u8 reserved_at_9[0x2]; 869 u8 max_lso_cap[0x5]; 870 u8 multi_pkt_send_wqe[0x2]; 871 u8 wqe_inline_mode[0x2]; 872 u8 rss_ind_tbl_cap[0x4]; 873 u8 reg_umr_sq[0x1]; 874 u8 scatter_fcs[0x1]; 875 u8 enhanced_multi_pkt_send_wqe[0x1]; 876 u8 tunnel_lso_const_out_ip_id[0x1]; 877 u8 reserved_at_1c[0x2]; 878 u8 tunnel_stateless_gre[0x1]; 879 u8 tunnel_stateless_vxlan[0x1]; 880 881 u8 swp[0x1]; 882 u8 swp_csum[0x1]; 883 u8 swp_lso[0x1]; 884 u8 cqe_checksum_full[0x1]; 885 u8 tunnel_stateless_geneve_tx[0x1]; 886 u8 tunnel_stateless_mpls_over_udp[0x1]; 887 u8 tunnel_stateless_mpls_over_gre[0x1]; 888 u8 tunnel_stateless_vxlan_gpe[0x1]; 889 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 890 u8 tunnel_stateless_ip_over_ip[0x1]; 891 u8 insert_trailer[0x1]; 892 u8 reserved_at_2b[0x5]; 893 u8 max_vxlan_udp_ports[0x8]; 894 u8 reserved_at_38[0x6]; 895 u8 max_geneve_opt_len[0x1]; 896 u8 tunnel_stateless_geneve_rx[0x1]; 897 898 u8 reserved_at_40[0x10]; 899 u8 lro_min_mss_size[0x10]; 900 901 u8 reserved_at_60[0x120]; 902 903 u8 lro_timer_supported_periods[4][0x20]; 904 905 u8 reserved_at_200[0x600]; 906 }; 907 908 struct mlx5_ifc_roce_cap_bits { 909 u8 roce_apm[0x1]; 910 u8 reserved_at_1[0x3]; 911 u8 sw_r_roce_src_udp_port[0x1]; 912 u8 reserved_at_5[0x1b]; 913 914 u8 reserved_at_20[0x60]; 915 916 u8 reserved_at_80[0xc]; 917 u8 l3_type[0x4]; 918 u8 reserved_at_90[0x8]; 919 u8 roce_version[0x8]; 920 921 u8 reserved_at_a0[0x10]; 922 u8 r_roce_dest_udp_port[0x10]; 923 924 u8 r_roce_max_src_udp_port[0x10]; 925 u8 r_roce_min_src_udp_port[0x10]; 926 927 u8 reserved_at_e0[0x10]; 928 u8 roce_address_table_size[0x10]; 929 930 u8 reserved_at_100[0x700]; 931 }; 932 933 struct mlx5_ifc_sync_steering_in_bits { 934 u8 opcode[0x10]; 935 u8 uid[0x10]; 936 937 u8 reserved_at_20[0x10]; 938 u8 op_mod[0x10]; 939 940 u8 reserved_at_40[0xc0]; 941 }; 942 943 struct mlx5_ifc_sync_steering_out_bits { 944 u8 status[0x8]; 945 u8 reserved_at_8[0x18]; 946 947 u8 syndrome[0x20]; 948 949 u8 reserved_at_40[0x40]; 950 }; 951 952 struct mlx5_ifc_device_mem_cap_bits { 953 u8 memic[0x1]; 954 u8 reserved_at_1[0x1f]; 955 956 u8 reserved_at_20[0xb]; 957 u8 log_min_memic_alloc_size[0x5]; 958 u8 reserved_at_30[0x8]; 959 u8 log_max_memic_addr_alignment[0x8]; 960 961 u8 memic_bar_start_addr[0x40]; 962 963 u8 memic_bar_size[0x20]; 964 965 u8 max_memic_size[0x20]; 966 967 u8 steering_sw_icm_start_address[0x40]; 968 969 u8 reserved_at_100[0x8]; 970 u8 log_header_modify_sw_icm_size[0x8]; 971 u8 reserved_at_110[0x2]; 972 u8 log_sw_icm_alloc_granularity[0x6]; 973 u8 log_steering_sw_icm_size[0x8]; 974 975 u8 reserved_at_120[0x20]; 976 977 u8 header_modify_sw_icm_start_address[0x40]; 978 979 u8 reserved_at_180[0x680]; 980 }; 981 982 struct mlx5_ifc_device_event_cap_bits { 983 u8 user_affiliated_events[4][0x40]; 984 985 u8 user_unaffiliated_events[4][0x40]; 986 }; 987 988 struct mlx5_ifc_device_virtio_emulation_cap_bits { 989 u8 reserved_at_0[0x20]; 990 991 u8 reserved_at_20[0x13]; 992 u8 log_doorbell_stride[0x5]; 993 u8 reserved_at_38[0x3]; 994 u8 log_doorbell_bar_size[0x5]; 995 996 u8 doorbell_bar_offset[0x40]; 997 998 u8 reserved_at_80[0x780]; 999 }; 1000 1001 enum { 1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1009 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1010 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1011 }; 1012 1013 enum { 1014 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1015 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1016 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1017 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1018 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1019 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1020 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1021 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1022 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1023 }; 1024 1025 struct mlx5_ifc_atomic_caps_bits { 1026 u8 reserved_at_0[0x40]; 1027 1028 u8 atomic_req_8B_endianness_mode[0x2]; 1029 u8 reserved_at_42[0x4]; 1030 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1031 1032 u8 reserved_at_47[0x19]; 1033 1034 u8 reserved_at_60[0x20]; 1035 1036 u8 reserved_at_80[0x10]; 1037 u8 atomic_operations[0x10]; 1038 1039 u8 reserved_at_a0[0x10]; 1040 u8 atomic_size_qp[0x10]; 1041 1042 u8 reserved_at_c0[0x10]; 1043 u8 atomic_size_dc[0x10]; 1044 1045 u8 reserved_at_e0[0x720]; 1046 }; 1047 1048 struct mlx5_ifc_odp_cap_bits { 1049 u8 reserved_at_0[0x40]; 1050 1051 u8 sig[0x1]; 1052 u8 reserved_at_41[0x1f]; 1053 1054 u8 reserved_at_60[0x20]; 1055 1056 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1057 1058 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1059 1060 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1061 1062 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1063 1064 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1065 1066 u8 reserved_at_120[0x6E0]; 1067 }; 1068 1069 struct mlx5_ifc_calc_op { 1070 u8 reserved_at_0[0x10]; 1071 u8 reserved_at_10[0x9]; 1072 u8 op_swap_endianness[0x1]; 1073 u8 op_min[0x1]; 1074 u8 op_xor[0x1]; 1075 u8 op_or[0x1]; 1076 u8 op_and[0x1]; 1077 u8 op_max[0x1]; 1078 u8 op_add[0x1]; 1079 }; 1080 1081 struct mlx5_ifc_vector_calc_cap_bits { 1082 u8 calc_matrix[0x1]; 1083 u8 reserved_at_1[0x1f]; 1084 u8 reserved_at_20[0x8]; 1085 u8 max_vec_count[0x8]; 1086 u8 reserved_at_30[0xd]; 1087 u8 max_chunk_size[0x3]; 1088 struct mlx5_ifc_calc_op calc0; 1089 struct mlx5_ifc_calc_op calc1; 1090 struct mlx5_ifc_calc_op calc2; 1091 struct mlx5_ifc_calc_op calc3; 1092 1093 u8 reserved_at_c0[0x720]; 1094 }; 1095 1096 struct mlx5_ifc_tls_cap_bits { 1097 u8 tls_1_2_aes_gcm_128[0x1]; 1098 u8 tls_1_3_aes_gcm_128[0x1]; 1099 u8 tls_1_2_aes_gcm_256[0x1]; 1100 u8 tls_1_3_aes_gcm_256[0x1]; 1101 u8 reserved_at_4[0x1c]; 1102 1103 u8 reserved_at_20[0x7e0]; 1104 }; 1105 1106 struct mlx5_ifc_ipsec_cap_bits { 1107 u8 ipsec_full_offload[0x1]; 1108 u8 ipsec_crypto_offload[0x1]; 1109 u8 ipsec_esn[0x1]; 1110 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1111 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1112 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1113 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1114 u8 reserved_at_7[0x4]; 1115 u8 log_max_ipsec_offload[0x5]; 1116 u8 reserved_at_10[0x10]; 1117 1118 u8 min_log_ipsec_full_replay_window[0x8]; 1119 u8 max_log_ipsec_full_replay_window[0x8]; 1120 u8 reserved_at_30[0x7d0]; 1121 }; 1122 1123 enum { 1124 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1125 MLX5_WQ_TYPE_CYCLIC = 0x1, 1126 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1127 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1128 }; 1129 1130 enum { 1131 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1132 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1133 }; 1134 1135 enum { 1136 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1137 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1138 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1139 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1140 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1141 }; 1142 1143 enum { 1144 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1145 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1146 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1147 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1148 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1149 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1150 }; 1151 1152 enum { 1153 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1154 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1155 }; 1156 1157 enum { 1158 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1159 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1160 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1161 }; 1162 1163 enum { 1164 MLX5_CAP_PORT_TYPE_IB = 0x0, 1165 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1166 }; 1167 1168 enum { 1169 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1170 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1171 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1172 }; 1173 1174 enum { 1175 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1176 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1177 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1178 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1179 }; 1180 1181 enum { 1182 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1183 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1184 }; 1185 1186 #define MLX5_FC_BULK_SIZE_FACTOR 128 1187 1188 enum mlx5_fc_bulk_alloc_bitmask { 1189 MLX5_FC_BULK_128 = (1 << 0), 1190 MLX5_FC_BULK_256 = (1 << 1), 1191 MLX5_FC_BULK_512 = (1 << 2), 1192 MLX5_FC_BULK_1024 = (1 << 3), 1193 MLX5_FC_BULK_2048 = (1 << 4), 1194 MLX5_FC_BULK_4096 = (1 << 5), 1195 MLX5_FC_BULK_8192 = (1 << 6), 1196 MLX5_FC_BULK_16384 = (1 << 7), 1197 }; 1198 1199 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1200 1201 struct mlx5_ifc_cmd_hca_cap_bits { 1202 u8 reserved_at_0[0x30]; 1203 u8 vhca_id[0x10]; 1204 1205 u8 reserved_at_40[0x40]; 1206 1207 u8 log_max_srq_sz[0x8]; 1208 u8 log_max_qp_sz[0x8]; 1209 u8 event_cap[0x1]; 1210 u8 reserved_at_91[0x7]; 1211 u8 prio_tag_required[0x1]; 1212 u8 reserved_at_99[0x2]; 1213 u8 log_max_qp[0x5]; 1214 1215 u8 reserved_at_a0[0x3]; 1216 u8 ece_support[0x1]; 1217 u8 reserved_at_a4[0x7]; 1218 u8 log_max_srq[0x5]; 1219 u8 reserved_at_b0[0x10]; 1220 1221 u8 max_sgl_for_optimized_performance[0x8]; 1222 u8 log_max_cq_sz[0x8]; 1223 u8 reserved_at_d0[0xb]; 1224 u8 log_max_cq[0x5]; 1225 1226 u8 log_max_eq_sz[0x8]; 1227 u8 relaxed_ordering_write[0x1]; 1228 u8 relaxed_ordering_read[0x1]; 1229 u8 log_max_mkey[0x6]; 1230 u8 reserved_at_f0[0x8]; 1231 u8 dump_fill_mkey[0x1]; 1232 u8 reserved_at_f9[0x2]; 1233 u8 fast_teardown[0x1]; 1234 u8 log_max_eq[0x4]; 1235 1236 u8 max_indirection[0x8]; 1237 u8 fixed_buffer_size[0x1]; 1238 u8 log_max_mrw_sz[0x7]; 1239 u8 force_teardown[0x1]; 1240 u8 reserved_at_111[0x1]; 1241 u8 log_max_bsf_list_size[0x6]; 1242 u8 umr_extended_translation_offset[0x1]; 1243 u8 null_mkey[0x1]; 1244 u8 log_max_klm_list_size[0x6]; 1245 1246 u8 reserved_at_120[0xa]; 1247 u8 log_max_ra_req_dc[0x6]; 1248 u8 reserved_at_130[0xa]; 1249 u8 log_max_ra_res_dc[0x6]; 1250 1251 u8 reserved_at_140[0x6]; 1252 u8 release_all_pages[0x1]; 1253 u8 reserved_at_147[0x2]; 1254 u8 roce_accl[0x1]; 1255 u8 log_max_ra_req_qp[0x6]; 1256 u8 reserved_at_150[0xa]; 1257 u8 log_max_ra_res_qp[0x6]; 1258 1259 u8 end_pad[0x1]; 1260 u8 cc_query_allowed[0x1]; 1261 u8 cc_modify_allowed[0x1]; 1262 u8 start_pad[0x1]; 1263 u8 cache_line_128byte[0x1]; 1264 u8 reserved_at_165[0x4]; 1265 u8 rts2rts_qp_counters_set_id[0x1]; 1266 u8 reserved_at_16a[0x2]; 1267 u8 vnic_env_int_rq_oob[0x1]; 1268 u8 sbcam_reg[0x1]; 1269 u8 reserved_at_16e[0x1]; 1270 u8 qcam_reg[0x1]; 1271 u8 gid_table_size[0x10]; 1272 1273 u8 out_of_seq_cnt[0x1]; 1274 u8 vport_counters[0x1]; 1275 u8 retransmission_q_counters[0x1]; 1276 u8 debug[0x1]; 1277 u8 modify_rq_counter_set_id[0x1]; 1278 u8 rq_delay_drop[0x1]; 1279 u8 max_qp_cnt[0xa]; 1280 u8 pkey_table_size[0x10]; 1281 1282 u8 vport_group_manager[0x1]; 1283 u8 vhca_group_manager[0x1]; 1284 u8 ib_virt[0x1]; 1285 u8 eth_virt[0x1]; 1286 u8 vnic_env_queue_counters[0x1]; 1287 u8 ets[0x1]; 1288 u8 nic_flow_table[0x1]; 1289 u8 eswitch_manager[0x1]; 1290 u8 device_memory[0x1]; 1291 u8 mcam_reg[0x1]; 1292 u8 pcam_reg[0x1]; 1293 u8 local_ca_ack_delay[0x5]; 1294 u8 port_module_event[0x1]; 1295 u8 enhanced_error_q_counters[0x1]; 1296 u8 ports_check[0x1]; 1297 u8 reserved_at_1b3[0x1]; 1298 u8 disable_link_up[0x1]; 1299 u8 beacon_led[0x1]; 1300 u8 port_type[0x2]; 1301 u8 num_ports[0x8]; 1302 1303 u8 reserved_at_1c0[0x1]; 1304 u8 pps[0x1]; 1305 u8 pps_modify[0x1]; 1306 u8 log_max_msg[0x5]; 1307 u8 reserved_at_1c8[0x4]; 1308 u8 max_tc[0x4]; 1309 u8 temp_warn_event[0x1]; 1310 u8 dcbx[0x1]; 1311 u8 general_notification_event[0x1]; 1312 u8 reserved_at_1d3[0x2]; 1313 u8 fpga[0x1]; 1314 u8 rol_s[0x1]; 1315 u8 rol_g[0x1]; 1316 u8 reserved_at_1d8[0x1]; 1317 u8 wol_s[0x1]; 1318 u8 wol_g[0x1]; 1319 u8 wol_a[0x1]; 1320 u8 wol_b[0x1]; 1321 u8 wol_m[0x1]; 1322 u8 wol_u[0x1]; 1323 u8 wol_p[0x1]; 1324 1325 u8 stat_rate_support[0x10]; 1326 u8 reserved_at_1f0[0x1]; 1327 u8 pci_sync_for_fw_update_event[0x1]; 1328 u8 reserved_at_1f2[0x6]; 1329 u8 init2_lag_tx_port_affinity[0x1]; 1330 u8 reserved_at_1fa[0x3]; 1331 u8 cqe_version[0x4]; 1332 1333 u8 compact_address_vector[0x1]; 1334 u8 striding_rq[0x1]; 1335 u8 reserved_at_202[0x1]; 1336 u8 ipoib_enhanced_offloads[0x1]; 1337 u8 ipoib_basic_offloads[0x1]; 1338 u8 reserved_at_205[0x1]; 1339 u8 repeated_block_disabled[0x1]; 1340 u8 umr_modify_entity_size_disabled[0x1]; 1341 u8 umr_modify_atomic_disabled[0x1]; 1342 u8 umr_indirect_mkey_disabled[0x1]; 1343 u8 umr_fence[0x2]; 1344 u8 dc_req_scat_data_cqe[0x1]; 1345 u8 reserved_at_20d[0x2]; 1346 u8 drain_sigerr[0x1]; 1347 u8 cmdif_checksum[0x2]; 1348 u8 sigerr_cqe[0x1]; 1349 u8 reserved_at_213[0x1]; 1350 u8 wq_signature[0x1]; 1351 u8 sctr_data_cqe[0x1]; 1352 u8 reserved_at_216[0x1]; 1353 u8 sho[0x1]; 1354 u8 tph[0x1]; 1355 u8 rf[0x1]; 1356 u8 dct[0x1]; 1357 u8 qos[0x1]; 1358 u8 eth_net_offloads[0x1]; 1359 u8 roce[0x1]; 1360 u8 atomic[0x1]; 1361 u8 reserved_at_21f[0x1]; 1362 1363 u8 cq_oi[0x1]; 1364 u8 cq_resize[0x1]; 1365 u8 cq_moderation[0x1]; 1366 u8 reserved_at_223[0x3]; 1367 u8 cq_eq_remap[0x1]; 1368 u8 pg[0x1]; 1369 u8 block_lb_mc[0x1]; 1370 u8 reserved_at_229[0x1]; 1371 u8 scqe_break_moderation[0x1]; 1372 u8 cq_period_start_from_cqe[0x1]; 1373 u8 cd[0x1]; 1374 u8 reserved_at_22d[0x1]; 1375 u8 apm[0x1]; 1376 u8 vector_calc[0x1]; 1377 u8 umr_ptr_rlky[0x1]; 1378 u8 imaicl[0x1]; 1379 u8 qp_packet_based[0x1]; 1380 u8 reserved_at_233[0x3]; 1381 u8 qkv[0x1]; 1382 u8 pkv[0x1]; 1383 u8 set_deth_sqpn[0x1]; 1384 u8 reserved_at_239[0x3]; 1385 u8 xrc[0x1]; 1386 u8 ud[0x1]; 1387 u8 uc[0x1]; 1388 u8 rc[0x1]; 1389 1390 u8 uar_4k[0x1]; 1391 u8 reserved_at_241[0x9]; 1392 u8 uar_sz[0x6]; 1393 u8 reserved_at_250[0x8]; 1394 u8 log_pg_sz[0x8]; 1395 1396 u8 bf[0x1]; 1397 u8 driver_version[0x1]; 1398 u8 pad_tx_eth_packet[0x1]; 1399 u8 reserved_at_263[0x8]; 1400 u8 log_bf_reg_size[0x5]; 1401 1402 u8 reserved_at_270[0x8]; 1403 u8 lag_tx_port_affinity[0x1]; 1404 u8 reserved_at_279[0x2]; 1405 u8 lag_master[0x1]; 1406 u8 num_lag_ports[0x4]; 1407 1408 u8 reserved_at_280[0x10]; 1409 u8 max_wqe_sz_sq[0x10]; 1410 1411 u8 reserved_at_2a0[0x10]; 1412 u8 max_wqe_sz_rq[0x10]; 1413 1414 u8 max_flow_counter_31_16[0x10]; 1415 u8 max_wqe_sz_sq_dc[0x10]; 1416 1417 u8 reserved_at_2e0[0x7]; 1418 u8 max_qp_mcg[0x19]; 1419 1420 u8 reserved_at_300[0x10]; 1421 u8 flow_counter_bulk_alloc[0x8]; 1422 u8 log_max_mcg[0x8]; 1423 1424 u8 reserved_at_320[0x3]; 1425 u8 log_max_transport_domain[0x5]; 1426 u8 reserved_at_328[0x3]; 1427 u8 log_max_pd[0x5]; 1428 u8 reserved_at_330[0xb]; 1429 u8 log_max_xrcd[0x5]; 1430 1431 u8 nic_receive_steering_discard[0x1]; 1432 u8 receive_discard_vport_down[0x1]; 1433 u8 transmit_discard_vport_down[0x1]; 1434 u8 reserved_at_343[0x5]; 1435 u8 log_max_flow_counter_bulk[0x8]; 1436 u8 max_flow_counter_15_0[0x10]; 1437 1438 1439 u8 reserved_at_360[0x3]; 1440 u8 log_max_rq[0x5]; 1441 u8 reserved_at_368[0x3]; 1442 u8 log_max_sq[0x5]; 1443 u8 reserved_at_370[0x3]; 1444 u8 log_max_tir[0x5]; 1445 u8 reserved_at_378[0x3]; 1446 u8 log_max_tis[0x5]; 1447 1448 u8 basic_cyclic_rcv_wqe[0x1]; 1449 u8 reserved_at_381[0x2]; 1450 u8 log_max_rmp[0x5]; 1451 u8 reserved_at_388[0x3]; 1452 u8 log_max_rqt[0x5]; 1453 u8 reserved_at_390[0x3]; 1454 u8 log_max_rqt_size[0x5]; 1455 u8 reserved_at_398[0x3]; 1456 u8 log_max_tis_per_sq[0x5]; 1457 1458 u8 ext_stride_num_range[0x1]; 1459 u8 reserved_at_3a1[0x2]; 1460 u8 log_max_stride_sz_rq[0x5]; 1461 u8 reserved_at_3a8[0x3]; 1462 u8 log_min_stride_sz_rq[0x5]; 1463 u8 reserved_at_3b0[0x3]; 1464 u8 log_max_stride_sz_sq[0x5]; 1465 u8 reserved_at_3b8[0x3]; 1466 u8 log_min_stride_sz_sq[0x5]; 1467 1468 u8 hairpin[0x1]; 1469 u8 reserved_at_3c1[0x2]; 1470 u8 log_max_hairpin_queues[0x5]; 1471 u8 reserved_at_3c8[0x3]; 1472 u8 log_max_hairpin_wq_data_sz[0x5]; 1473 u8 reserved_at_3d0[0x3]; 1474 u8 log_max_hairpin_num_packets[0x5]; 1475 u8 reserved_at_3d8[0x3]; 1476 u8 log_max_wq_sz[0x5]; 1477 1478 u8 nic_vport_change_event[0x1]; 1479 u8 disable_local_lb_uc[0x1]; 1480 u8 disable_local_lb_mc[0x1]; 1481 u8 log_min_hairpin_wq_data_sz[0x5]; 1482 u8 reserved_at_3e8[0x3]; 1483 u8 log_max_vlan_list[0x5]; 1484 u8 reserved_at_3f0[0x3]; 1485 u8 log_max_current_mc_list[0x5]; 1486 u8 reserved_at_3f8[0x3]; 1487 u8 log_max_current_uc_list[0x5]; 1488 1489 u8 general_obj_types[0x40]; 1490 1491 u8 reserved_at_440[0x20]; 1492 1493 u8 reserved_at_460[0x3]; 1494 u8 log_max_uctx[0x5]; 1495 u8 reserved_at_468[0x2]; 1496 u8 ipsec_offload[0x1]; 1497 u8 log_max_umem[0x5]; 1498 u8 max_num_eqs[0x10]; 1499 1500 u8 reserved_at_480[0x1]; 1501 u8 tls_tx[0x1]; 1502 u8 tls_rx[0x1]; 1503 u8 log_max_l2_table[0x5]; 1504 u8 reserved_at_488[0x8]; 1505 u8 log_uar_page_sz[0x10]; 1506 1507 u8 reserved_at_4a0[0x20]; 1508 u8 device_frequency_mhz[0x20]; 1509 u8 device_frequency_khz[0x20]; 1510 1511 u8 reserved_at_500[0x20]; 1512 u8 num_of_uars_per_page[0x20]; 1513 1514 u8 flex_parser_protocols[0x20]; 1515 1516 u8 max_geneve_tlv_options[0x8]; 1517 u8 reserved_at_568[0x3]; 1518 u8 max_geneve_tlv_option_data_len[0x5]; 1519 u8 reserved_at_570[0x10]; 1520 1521 u8 reserved_at_580[0x33]; 1522 u8 log_max_dek[0x5]; 1523 u8 reserved_at_5b8[0x4]; 1524 u8 mini_cqe_resp_stride_index[0x1]; 1525 u8 cqe_128_always[0x1]; 1526 u8 cqe_compression_128[0x1]; 1527 u8 cqe_compression[0x1]; 1528 1529 u8 cqe_compression_timeout[0x10]; 1530 u8 cqe_compression_max_num[0x10]; 1531 1532 u8 reserved_at_5e0[0x10]; 1533 u8 tag_matching[0x1]; 1534 u8 rndv_offload_rc[0x1]; 1535 u8 rndv_offload_dc[0x1]; 1536 u8 log_tag_matching_list_sz[0x5]; 1537 u8 reserved_at_5f8[0x3]; 1538 u8 log_max_xrq[0x5]; 1539 1540 u8 affiliate_nic_vport_criteria[0x8]; 1541 u8 native_port_num[0x8]; 1542 u8 num_vhca_ports[0x8]; 1543 u8 reserved_at_618[0x6]; 1544 u8 sw_owner_id[0x1]; 1545 u8 reserved_at_61f[0x1]; 1546 1547 u8 max_num_of_monitor_counters[0x10]; 1548 u8 num_ppcnt_monitor_counters[0x10]; 1549 1550 u8 reserved_at_640[0x10]; 1551 u8 num_q_monitor_counters[0x10]; 1552 1553 u8 reserved_at_660[0x20]; 1554 1555 u8 sf[0x1]; 1556 u8 sf_set_partition[0x1]; 1557 u8 reserved_at_682[0x1]; 1558 u8 log_max_sf[0x5]; 1559 u8 reserved_at_688[0x8]; 1560 u8 log_min_sf_size[0x8]; 1561 u8 max_num_sf_partitions[0x8]; 1562 1563 u8 uctx_cap[0x20]; 1564 1565 u8 reserved_at_6c0[0x4]; 1566 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1567 u8 flex_parser_id_icmp_dw1[0x4]; 1568 u8 flex_parser_id_icmp_dw0[0x4]; 1569 u8 flex_parser_id_icmpv6_dw1[0x4]; 1570 u8 flex_parser_id_icmpv6_dw0[0x4]; 1571 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1572 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1573 1574 u8 reserved_at_6e0[0x10]; 1575 u8 sf_base_id[0x10]; 1576 1577 u8 reserved_at_700[0x80]; 1578 u8 vhca_tunnel_commands[0x40]; 1579 u8 reserved_at_7c0[0x40]; 1580 }; 1581 1582 enum mlx5_flow_destination_type { 1583 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1584 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1585 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1586 1587 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1588 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1589 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1590 }; 1591 1592 enum mlx5_flow_table_miss_action { 1593 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1594 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1595 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1596 }; 1597 1598 struct mlx5_ifc_dest_format_struct_bits { 1599 u8 destination_type[0x8]; 1600 u8 destination_id[0x18]; 1601 1602 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1603 u8 packet_reformat[0x1]; 1604 u8 reserved_at_22[0xe]; 1605 u8 destination_eswitch_owner_vhca_id[0x10]; 1606 }; 1607 1608 struct mlx5_ifc_flow_counter_list_bits { 1609 u8 flow_counter_id[0x20]; 1610 1611 u8 reserved_at_20[0x20]; 1612 }; 1613 1614 struct mlx5_ifc_extended_dest_format_bits { 1615 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1616 1617 u8 packet_reformat_id[0x20]; 1618 1619 u8 reserved_at_60[0x20]; 1620 }; 1621 1622 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1623 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1624 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1625 }; 1626 1627 struct mlx5_ifc_fte_match_param_bits { 1628 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1629 1630 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1631 1632 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1633 1634 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1635 1636 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1637 1638 u8 reserved_at_a00[0x600]; 1639 }; 1640 1641 enum { 1642 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1643 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1644 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1645 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1646 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1647 }; 1648 1649 struct mlx5_ifc_rx_hash_field_select_bits { 1650 u8 l3_prot_type[0x1]; 1651 u8 l4_prot_type[0x1]; 1652 u8 selected_fields[0x1e]; 1653 }; 1654 1655 enum { 1656 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1657 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1658 }; 1659 1660 enum { 1661 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1662 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1663 }; 1664 1665 struct mlx5_ifc_wq_bits { 1666 u8 wq_type[0x4]; 1667 u8 wq_signature[0x1]; 1668 u8 end_padding_mode[0x2]; 1669 u8 cd_slave[0x1]; 1670 u8 reserved_at_8[0x18]; 1671 1672 u8 hds_skip_first_sge[0x1]; 1673 u8 log2_hds_buf_size[0x3]; 1674 u8 reserved_at_24[0x7]; 1675 u8 page_offset[0x5]; 1676 u8 lwm[0x10]; 1677 1678 u8 reserved_at_40[0x8]; 1679 u8 pd[0x18]; 1680 1681 u8 reserved_at_60[0x8]; 1682 u8 uar_page[0x18]; 1683 1684 u8 dbr_addr[0x40]; 1685 1686 u8 hw_counter[0x20]; 1687 1688 u8 sw_counter[0x20]; 1689 1690 u8 reserved_at_100[0xc]; 1691 u8 log_wq_stride[0x4]; 1692 u8 reserved_at_110[0x3]; 1693 u8 log_wq_pg_sz[0x5]; 1694 u8 reserved_at_118[0x3]; 1695 u8 log_wq_sz[0x5]; 1696 1697 u8 dbr_umem_valid[0x1]; 1698 u8 wq_umem_valid[0x1]; 1699 u8 reserved_at_122[0x1]; 1700 u8 log_hairpin_num_packets[0x5]; 1701 u8 reserved_at_128[0x3]; 1702 u8 log_hairpin_data_sz[0x5]; 1703 1704 u8 reserved_at_130[0x4]; 1705 u8 log_wqe_num_of_strides[0x4]; 1706 u8 two_byte_shift_en[0x1]; 1707 u8 reserved_at_139[0x4]; 1708 u8 log_wqe_stride_size[0x3]; 1709 1710 u8 reserved_at_140[0x4c0]; 1711 1712 struct mlx5_ifc_cmd_pas_bits pas[]; 1713 }; 1714 1715 struct mlx5_ifc_rq_num_bits { 1716 u8 reserved_at_0[0x8]; 1717 u8 rq_num[0x18]; 1718 }; 1719 1720 struct mlx5_ifc_mac_address_layout_bits { 1721 u8 reserved_at_0[0x10]; 1722 u8 mac_addr_47_32[0x10]; 1723 1724 u8 mac_addr_31_0[0x20]; 1725 }; 1726 1727 struct mlx5_ifc_vlan_layout_bits { 1728 u8 reserved_at_0[0x14]; 1729 u8 vlan[0x0c]; 1730 1731 u8 reserved_at_20[0x20]; 1732 }; 1733 1734 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1735 u8 reserved_at_0[0xa0]; 1736 1737 u8 min_time_between_cnps[0x20]; 1738 1739 u8 reserved_at_c0[0x12]; 1740 u8 cnp_dscp[0x6]; 1741 u8 reserved_at_d8[0x4]; 1742 u8 cnp_prio_mode[0x1]; 1743 u8 cnp_802p_prio[0x3]; 1744 1745 u8 reserved_at_e0[0x720]; 1746 }; 1747 1748 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1749 u8 reserved_at_0[0x60]; 1750 1751 u8 reserved_at_60[0x4]; 1752 u8 clamp_tgt_rate[0x1]; 1753 u8 reserved_at_65[0x3]; 1754 u8 clamp_tgt_rate_after_time_inc[0x1]; 1755 u8 reserved_at_69[0x17]; 1756 1757 u8 reserved_at_80[0x20]; 1758 1759 u8 rpg_time_reset[0x20]; 1760 1761 u8 rpg_byte_reset[0x20]; 1762 1763 u8 rpg_threshold[0x20]; 1764 1765 u8 rpg_max_rate[0x20]; 1766 1767 u8 rpg_ai_rate[0x20]; 1768 1769 u8 rpg_hai_rate[0x20]; 1770 1771 u8 rpg_gd[0x20]; 1772 1773 u8 rpg_min_dec_fac[0x20]; 1774 1775 u8 rpg_min_rate[0x20]; 1776 1777 u8 reserved_at_1c0[0xe0]; 1778 1779 u8 rate_to_set_on_first_cnp[0x20]; 1780 1781 u8 dce_tcp_g[0x20]; 1782 1783 u8 dce_tcp_rtt[0x20]; 1784 1785 u8 rate_reduce_monitor_period[0x20]; 1786 1787 u8 reserved_at_320[0x20]; 1788 1789 u8 initial_alpha_value[0x20]; 1790 1791 u8 reserved_at_360[0x4a0]; 1792 }; 1793 1794 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1795 u8 reserved_at_0[0x80]; 1796 1797 u8 rppp_max_rps[0x20]; 1798 1799 u8 rpg_time_reset[0x20]; 1800 1801 u8 rpg_byte_reset[0x20]; 1802 1803 u8 rpg_threshold[0x20]; 1804 1805 u8 rpg_max_rate[0x20]; 1806 1807 u8 rpg_ai_rate[0x20]; 1808 1809 u8 rpg_hai_rate[0x20]; 1810 1811 u8 rpg_gd[0x20]; 1812 1813 u8 rpg_min_dec_fac[0x20]; 1814 1815 u8 rpg_min_rate[0x20]; 1816 1817 u8 reserved_at_1c0[0x640]; 1818 }; 1819 1820 enum { 1821 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1822 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1823 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1824 }; 1825 1826 struct mlx5_ifc_resize_field_select_bits { 1827 u8 resize_field_select[0x20]; 1828 }; 1829 1830 struct mlx5_ifc_resource_dump_bits { 1831 u8 more_dump[0x1]; 1832 u8 inline_dump[0x1]; 1833 u8 reserved_at_2[0xa]; 1834 u8 seq_num[0x4]; 1835 u8 segment_type[0x10]; 1836 1837 u8 reserved_at_20[0x10]; 1838 u8 vhca_id[0x10]; 1839 1840 u8 index1[0x20]; 1841 1842 u8 index2[0x20]; 1843 1844 u8 num_of_obj1[0x10]; 1845 u8 num_of_obj2[0x10]; 1846 1847 u8 reserved_at_a0[0x20]; 1848 1849 u8 device_opaque[0x40]; 1850 1851 u8 mkey[0x20]; 1852 1853 u8 size[0x20]; 1854 1855 u8 address[0x40]; 1856 1857 u8 inline_data[52][0x20]; 1858 }; 1859 1860 struct mlx5_ifc_resource_dump_menu_record_bits { 1861 u8 reserved_at_0[0x4]; 1862 u8 num_of_obj2_supports_active[0x1]; 1863 u8 num_of_obj2_supports_all[0x1]; 1864 u8 must_have_num_of_obj2[0x1]; 1865 u8 support_num_of_obj2[0x1]; 1866 u8 num_of_obj1_supports_active[0x1]; 1867 u8 num_of_obj1_supports_all[0x1]; 1868 u8 must_have_num_of_obj1[0x1]; 1869 u8 support_num_of_obj1[0x1]; 1870 u8 must_have_index2[0x1]; 1871 u8 support_index2[0x1]; 1872 u8 must_have_index1[0x1]; 1873 u8 support_index1[0x1]; 1874 u8 segment_type[0x10]; 1875 1876 u8 segment_name[4][0x20]; 1877 1878 u8 index1_name[4][0x20]; 1879 1880 u8 index2_name[4][0x20]; 1881 }; 1882 1883 struct mlx5_ifc_resource_dump_segment_header_bits { 1884 u8 length_dw[0x10]; 1885 u8 segment_type[0x10]; 1886 }; 1887 1888 struct mlx5_ifc_resource_dump_command_segment_bits { 1889 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1890 1891 u8 segment_called[0x10]; 1892 u8 vhca_id[0x10]; 1893 1894 u8 index1[0x20]; 1895 1896 u8 index2[0x20]; 1897 1898 u8 num_of_obj1[0x10]; 1899 u8 num_of_obj2[0x10]; 1900 }; 1901 1902 struct mlx5_ifc_resource_dump_error_segment_bits { 1903 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1904 1905 u8 reserved_at_20[0x10]; 1906 u8 syndrome_id[0x10]; 1907 1908 u8 reserved_at_40[0x40]; 1909 1910 u8 error[8][0x20]; 1911 }; 1912 1913 struct mlx5_ifc_resource_dump_info_segment_bits { 1914 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1915 1916 u8 reserved_at_20[0x18]; 1917 u8 dump_version[0x8]; 1918 1919 u8 hw_version[0x20]; 1920 1921 u8 fw_version[0x20]; 1922 }; 1923 1924 struct mlx5_ifc_resource_dump_menu_segment_bits { 1925 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1926 1927 u8 reserved_at_20[0x10]; 1928 u8 num_of_records[0x10]; 1929 1930 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 1931 }; 1932 1933 struct mlx5_ifc_resource_dump_resource_segment_bits { 1934 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1935 1936 u8 reserved_at_20[0x20]; 1937 1938 u8 index1[0x20]; 1939 1940 u8 index2[0x20]; 1941 1942 u8 payload[][0x20]; 1943 }; 1944 1945 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1946 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1947 }; 1948 1949 struct mlx5_ifc_menu_resource_dump_response_bits { 1950 struct mlx5_ifc_resource_dump_info_segment_bits info; 1951 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1952 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1953 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1954 }; 1955 1956 enum { 1957 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1958 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1959 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1960 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1961 }; 1962 1963 struct mlx5_ifc_modify_field_select_bits { 1964 u8 modify_field_select[0x20]; 1965 }; 1966 1967 struct mlx5_ifc_field_select_r_roce_np_bits { 1968 u8 field_select_r_roce_np[0x20]; 1969 }; 1970 1971 struct mlx5_ifc_field_select_r_roce_rp_bits { 1972 u8 field_select_r_roce_rp[0x20]; 1973 }; 1974 1975 enum { 1976 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1977 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1978 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1979 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1980 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1981 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1982 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1983 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1984 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1985 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1986 }; 1987 1988 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1989 u8 field_select_8021qaurp[0x20]; 1990 }; 1991 1992 struct mlx5_ifc_phys_layer_cntrs_bits { 1993 u8 time_since_last_clear_high[0x20]; 1994 1995 u8 time_since_last_clear_low[0x20]; 1996 1997 u8 symbol_errors_high[0x20]; 1998 1999 u8 symbol_errors_low[0x20]; 2000 2001 u8 sync_headers_errors_high[0x20]; 2002 2003 u8 sync_headers_errors_low[0x20]; 2004 2005 u8 edpl_bip_errors_lane0_high[0x20]; 2006 2007 u8 edpl_bip_errors_lane0_low[0x20]; 2008 2009 u8 edpl_bip_errors_lane1_high[0x20]; 2010 2011 u8 edpl_bip_errors_lane1_low[0x20]; 2012 2013 u8 edpl_bip_errors_lane2_high[0x20]; 2014 2015 u8 edpl_bip_errors_lane2_low[0x20]; 2016 2017 u8 edpl_bip_errors_lane3_high[0x20]; 2018 2019 u8 edpl_bip_errors_lane3_low[0x20]; 2020 2021 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2022 2023 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2024 2025 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2026 2027 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2028 2029 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2030 2031 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2032 2033 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2034 2035 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2036 2037 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2038 2039 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2040 2041 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2042 2043 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2044 2045 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2046 2047 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2048 2049 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2050 2051 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2052 2053 u8 rs_fec_corrected_blocks_high[0x20]; 2054 2055 u8 rs_fec_corrected_blocks_low[0x20]; 2056 2057 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2058 2059 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2060 2061 u8 rs_fec_no_errors_blocks_high[0x20]; 2062 2063 u8 rs_fec_no_errors_blocks_low[0x20]; 2064 2065 u8 rs_fec_single_error_blocks_high[0x20]; 2066 2067 u8 rs_fec_single_error_blocks_low[0x20]; 2068 2069 u8 rs_fec_corrected_symbols_total_high[0x20]; 2070 2071 u8 rs_fec_corrected_symbols_total_low[0x20]; 2072 2073 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2074 2075 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2076 2077 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2078 2079 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2080 2081 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2082 2083 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2084 2085 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2086 2087 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2088 2089 u8 link_down_events[0x20]; 2090 2091 u8 successful_recovery_events[0x20]; 2092 2093 u8 reserved_at_640[0x180]; 2094 }; 2095 2096 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2097 u8 time_since_last_clear_high[0x20]; 2098 2099 u8 time_since_last_clear_low[0x20]; 2100 2101 u8 phy_received_bits_high[0x20]; 2102 2103 u8 phy_received_bits_low[0x20]; 2104 2105 u8 phy_symbol_errors_high[0x20]; 2106 2107 u8 phy_symbol_errors_low[0x20]; 2108 2109 u8 phy_corrected_bits_high[0x20]; 2110 2111 u8 phy_corrected_bits_low[0x20]; 2112 2113 u8 phy_corrected_bits_lane0_high[0x20]; 2114 2115 u8 phy_corrected_bits_lane0_low[0x20]; 2116 2117 u8 phy_corrected_bits_lane1_high[0x20]; 2118 2119 u8 phy_corrected_bits_lane1_low[0x20]; 2120 2121 u8 phy_corrected_bits_lane2_high[0x20]; 2122 2123 u8 phy_corrected_bits_lane2_low[0x20]; 2124 2125 u8 phy_corrected_bits_lane3_high[0x20]; 2126 2127 u8 phy_corrected_bits_lane3_low[0x20]; 2128 2129 u8 reserved_at_200[0x5c0]; 2130 }; 2131 2132 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2133 u8 symbol_error_counter[0x10]; 2134 2135 u8 link_error_recovery_counter[0x8]; 2136 2137 u8 link_downed_counter[0x8]; 2138 2139 u8 port_rcv_errors[0x10]; 2140 2141 u8 port_rcv_remote_physical_errors[0x10]; 2142 2143 u8 port_rcv_switch_relay_errors[0x10]; 2144 2145 u8 port_xmit_discards[0x10]; 2146 2147 u8 port_xmit_constraint_errors[0x8]; 2148 2149 u8 port_rcv_constraint_errors[0x8]; 2150 2151 u8 reserved_at_70[0x8]; 2152 2153 u8 link_overrun_errors[0x8]; 2154 2155 u8 reserved_at_80[0x10]; 2156 2157 u8 vl_15_dropped[0x10]; 2158 2159 u8 reserved_at_a0[0x80]; 2160 2161 u8 port_xmit_wait[0x20]; 2162 }; 2163 2164 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2165 u8 transmit_queue_high[0x20]; 2166 2167 u8 transmit_queue_low[0x20]; 2168 2169 u8 no_buffer_discard_uc_high[0x20]; 2170 2171 u8 no_buffer_discard_uc_low[0x20]; 2172 2173 u8 reserved_at_80[0x740]; 2174 }; 2175 2176 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2177 u8 wred_discard_high[0x20]; 2178 2179 u8 wred_discard_low[0x20]; 2180 2181 u8 ecn_marked_tc_high[0x20]; 2182 2183 u8 ecn_marked_tc_low[0x20]; 2184 2185 u8 reserved_at_80[0x740]; 2186 }; 2187 2188 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2189 u8 rx_octets_high[0x20]; 2190 2191 u8 rx_octets_low[0x20]; 2192 2193 u8 reserved_at_40[0xc0]; 2194 2195 u8 rx_frames_high[0x20]; 2196 2197 u8 rx_frames_low[0x20]; 2198 2199 u8 tx_octets_high[0x20]; 2200 2201 u8 tx_octets_low[0x20]; 2202 2203 u8 reserved_at_180[0xc0]; 2204 2205 u8 tx_frames_high[0x20]; 2206 2207 u8 tx_frames_low[0x20]; 2208 2209 u8 rx_pause_high[0x20]; 2210 2211 u8 rx_pause_low[0x20]; 2212 2213 u8 rx_pause_duration_high[0x20]; 2214 2215 u8 rx_pause_duration_low[0x20]; 2216 2217 u8 tx_pause_high[0x20]; 2218 2219 u8 tx_pause_low[0x20]; 2220 2221 u8 tx_pause_duration_high[0x20]; 2222 2223 u8 tx_pause_duration_low[0x20]; 2224 2225 u8 rx_pause_transition_high[0x20]; 2226 2227 u8 rx_pause_transition_low[0x20]; 2228 2229 u8 rx_discards_high[0x20]; 2230 2231 u8 rx_discards_low[0x20]; 2232 2233 u8 device_stall_minor_watermark_cnt_high[0x20]; 2234 2235 u8 device_stall_minor_watermark_cnt_low[0x20]; 2236 2237 u8 device_stall_critical_watermark_cnt_high[0x20]; 2238 2239 u8 device_stall_critical_watermark_cnt_low[0x20]; 2240 2241 u8 reserved_at_480[0x340]; 2242 }; 2243 2244 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2245 u8 port_transmit_wait_high[0x20]; 2246 2247 u8 port_transmit_wait_low[0x20]; 2248 2249 u8 reserved_at_40[0x100]; 2250 2251 u8 rx_buffer_almost_full_high[0x20]; 2252 2253 u8 rx_buffer_almost_full_low[0x20]; 2254 2255 u8 rx_buffer_full_high[0x20]; 2256 2257 u8 rx_buffer_full_low[0x20]; 2258 2259 u8 rx_icrc_encapsulated_high[0x20]; 2260 2261 u8 rx_icrc_encapsulated_low[0x20]; 2262 2263 u8 reserved_at_200[0x5c0]; 2264 }; 2265 2266 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2267 u8 dot3stats_alignment_errors_high[0x20]; 2268 2269 u8 dot3stats_alignment_errors_low[0x20]; 2270 2271 u8 dot3stats_fcs_errors_high[0x20]; 2272 2273 u8 dot3stats_fcs_errors_low[0x20]; 2274 2275 u8 dot3stats_single_collision_frames_high[0x20]; 2276 2277 u8 dot3stats_single_collision_frames_low[0x20]; 2278 2279 u8 dot3stats_multiple_collision_frames_high[0x20]; 2280 2281 u8 dot3stats_multiple_collision_frames_low[0x20]; 2282 2283 u8 dot3stats_sqe_test_errors_high[0x20]; 2284 2285 u8 dot3stats_sqe_test_errors_low[0x20]; 2286 2287 u8 dot3stats_deferred_transmissions_high[0x20]; 2288 2289 u8 dot3stats_deferred_transmissions_low[0x20]; 2290 2291 u8 dot3stats_late_collisions_high[0x20]; 2292 2293 u8 dot3stats_late_collisions_low[0x20]; 2294 2295 u8 dot3stats_excessive_collisions_high[0x20]; 2296 2297 u8 dot3stats_excessive_collisions_low[0x20]; 2298 2299 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2300 2301 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2302 2303 u8 dot3stats_carrier_sense_errors_high[0x20]; 2304 2305 u8 dot3stats_carrier_sense_errors_low[0x20]; 2306 2307 u8 dot3stats_frame_too_longs_high[0x20]; 2308 2309 u8 dot3stats_frame_too_longs_low[0x20]; 2310 2311 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2312 2313 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2314 2315 u8 dot3stats_symbol_errors_high[0x20]; 2316 2317 u8 dot3stats_symbol_errors_low[0x20]; 2318 2319 u8 dot3control_in_unknown_opcodes_high[0x20]; 2320 2321 u8 dot3control_in_unknown_opcodes_low[0x20]; 2322 2323 u8 dot3in_pause_frames_high[0x20]; 2324 2325 u8 dot3in_pause_frames_low[0x20]; 2326 2327 u8 dot3out_pause_frames_high[0x20]; 2328 2329 u8 dot3out_pause_frames_low[0x20]; 2330 2331 u8 reserved_at_400[0x3c0]; 2332 }; 2333 2334 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2335 u8 ether_stats_drop_events_high[0x20]; 2336 2337 u8 ether_stats_drop_events_low[0x20]; 2338 2339 u8 ether_stats_octets_high[0x20]; 2340 2341 u8 ether_stats_octets_low[0x20]; 2342 2343 u8 ether_stats_pkts_high[0x20]; 2344 2345 u8 ether_stats_pkts_low[0x20]; 2346 2347 u8 ether_stats_broadcast_pkts_high[0x20]; 2348 2349 u8 ether_stats_broadcast_pkts_low[0x20]; 2350 2351 u8 ether_stats_multicast_pkts_high[0x20]; 2352 2353 u8 ether_stats_multicast_pkts_low[0x20]; 2354 2355 u8 ether_stats_crc_align_errors_high[0x20]; 2356 2357 u8 ether_stats_crc_align_errors_low[0x20]; 2358 2359 u8 ether_stats_undersize_pkts_high[0x20]; 2360 2361 u8 ether_stats_undersize_pkts_low[0x20]; 2362 2363 u8 ether_stats_oversize_pkts_high[0x20]; 2364 2365 u8 ether_stats_oversize_pkts_low[0x20]; 2366 2367 u8 ether_stats_fragments_high[0x20]; 2368 2369 u8 ether_stats_fragments_low[0x20]; 2370 2371 u8 ether_stats_jabbers_high[0x20]; 2372 2373 u8 ether_stats_jabbers_low[0x20]; 2374 2375 u8 ether_stats_collisions_high[0x20]; 2376 2377 u8 ether_stats_collisions_low[0x20]; 2378 2379 u8 ether_stats_pkts64octets_high[0x20]; 2380 2381 u8 ether_stats_pkts64octets_low[0x20]; 2382 2383 u8 ether_stats_pkts65to127octets_high[0x20]; 2384 2385 u8 ether_stats_pkts65to127octets_low[0x20]; 2386 2387 u8 ether_stats_pkts128to255octets_high[0x20]; 2388 2389 u8 ether_stats_pkts128to255octets_low[0x20]; 2390 2391 u8 ether_stats_pkts256to511octets_high[0x20]; 2392 2393 u8 ether_stats_pkts256to511octets_low[0x20]; 2394 2395 u8 ether_stats_pkts512to1023octets_high[0x20]; 2396 2397 u8 ether_stats_pkts512to1023octets_low[0x20]; 2398 2399 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2400 2401 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2402 2403 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2404 2405 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2406 2407 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2408 2409 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2410 2411 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2412 2413 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2414 2415 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2416 2417 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2418 2419 u8 reserved_at_540[0x280]; 2420 }; 2421 2422 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2423 u8 if_in_octets_high[0x20]; 2424 2425 u8 if_in_octets_low[0x20]; 2426 2427 u8 if_in_ucast_pkts_high[0x20]; 2428 2429 u8 if_in_ucast_pkts_low[0x20]; 2430 2431 u8 if_in_discards_high[0x20]; 2432 2433 u8 if_in_discards_low[0x20]; 2434 2435 u8 if_in_errors_high[0x20]; 2436 2437 u8 if_in_errors_low[0x20]; 2438 2439 u8 if_in_unknown_protos_high[0x20]; 2440 2441 u8 if_in_unknown_protos_low[0x20]; 2442 2443 u8 if_out_octets_high[0x20]; 2444 2445 u8 if_out_octets_low[0x20]; 2446 2447 u8 if_out_ucast_pkts_high[0x20]; 2448 2449 u8 if_out_ucast_pkts_low[0x20]; 2450 2451 u8 if_out_discards_high[0x20]; 2452 2453 u8 if_out_discards_low[0x20]; 2454 2455 u8 if_out_errors_high[0x20]; 2456 2457 u8 if_out_errors_low[0x20]; 2458 2459 u8 if_in_multicast_pkts_high[0x20]; 2460 2461 u8 if_in_multicast_pkts_low[0x20]; 2462 2463 u8 if_in_broadcast_pkts_high[0x20]; 2464 2465 u8 if_in_broadcast_pkts_low[0x20]; 2466 2467 u8 if_out_multicast_pkts_high[0x20]; 2468 2469 u8 if_out_multicast_pkts_low[0x20]; 2470 2471 u8 if_out_broadcast_pkts_high[0x20]; 2472 2473 u8 if_out_broadcast_pkts_low[0x20]; 2474 2475 u8 reserved_at_340[0x480]; 2476 }; 2477 2478 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2479 u8 a_frames_transmitted_ok_high[0x20]; 2480 2481 u8 a_frames_transmitted_ok_low[0x20]; 2482 2483 u8 a_frames_received_ok_high[0x20]; 2484 2485 u8 a_frames_received_ok_low[0x20]; 2486 2487 u8 a_frame_check_sequence_errors_high[0x20]; 2488 2489 u8 a_frame_check_sequence_errors_low[0x20]; 2490 2491 u8 a_alignment_errors_high[0x20]; 2492 2493 u8 a_alignment_errors_low[0x20]; 2494 2495 u8 a_octets_transmitted_ok_high[0x20]; 2496 2497 u8 a_octets_transmitted_ok_low[0x20]; 2498 2499 u8 a_octets_received_ok_high[0x20]; 2500 2501 u8 a_octets_received_ok_low[0x20]; 2502 2503 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2504 2505 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2506 2507 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2508 2509 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2510 2511 u8 a_multicast_frames_received_ok_high[0x20]; 2512 2513 u8 a_multicast_frames_received_ok_low[0x20]; 2514 2515 u8 a_broadcast_frames_received_ok_high[0x20]; 2516 2517 u8 a_broadcast_frames_received_ok_low[0x20]; 2518 2519 u8 a_in_range_length_errors_high[0x20]; 2520 2521 u8 a_in_range_length_errors_low[0x20]; 2522 2523 u8 a_out_of_range_length_field_high[0x20]; 2524 2525 u8 a_out_of_range_length_field_low[0x20]; 2526 2527 u8 a_frame_too_long_errors_high[0x20]; 2528 2529 u8 a_frame_too_long_errors_low[0x20]; 2530 2531 u8 a_symbol_error_during_carrier_high[0x20]; 2532 2533 u8 a_symbol_error_during_carrier_low[0x20]; 2534 2535 u8 a_mac_control_frames_transmitted_high[0x20]; 2536 2537 u8 a_mac_control_frames_transmitted_low[0x20]; 2538 2539 u8 a_mac_control_frames_received_high[0x20]; 2540 2541 u8 a_mac_control_frames_received_low[0x20]; 2542 2543 u8 a_unsupported_opcodes_received_high[0x20]; 2544 2545 u8 a_unsupported_opcodes_received_low[0x20]; 2546 2547 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2548 2549 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2550 2551 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2552 2553 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2554 2555 u8 reserved_at_4c0[0x300]; 2556 }; 2557 2558 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2559 u8 life_time_counter_high[0x20]; 2560 2561 u8 life_time_counter_low[0x20]; 2562 2563 u8 rx_errors[0x20]; 2564 2565 u8 tx_errors[0x20]; 2566 2567 u8 l0_to_recovery_eieos[0x20]; 2568 2569 u8 l0_to_recovery_ts[0x20]; 2570 2571 u8 l0_to_recovery_framing[0x20]; 2572 2573 u8 l0_to_recovery_retrain[0x20]; 2574 2575 u8 crc_error_dllp[0x20]; 2576 2577 u8 crc_error_tlp[0x20]; 2578 2579 u8 tx_overflow_buffer_pkt_high[0x20]; 2580 2581 u8 tx_overflow_buffer_pkt_low[0x20]; 2582 2583 u8 outbound_stalled_reads[0x20]; 2584 2585 u8 outbound_stalled_writes[0x20]; 2586 2587 u8 outbound_stalled_reads_events[0x20]; 2588 2589 u8 outbound_stalled_writes_events[0x20]; 2590 2591 u8 reserved_at_200[0x5c0]; 2592 }; 2593 2594 struct mlx5_ifc_cmd_inter_comp_event_bits { 2595 u8 command_completion_vector[0x20]; 2596 2597 u8 reserved_at_20[0xc0]; 2598 }; 2599 2600 struct mlx5_ifc_stall_vl_event_bits { 2601 u8 reserved_at_0[0x18]; 2602 u8 port_num[0x1]; 2603 u8 reserved_at_19[0x3]; 2604 u8 vl[0x4]; 2605 2606 u8 reserved_at_20[0xa0]; 2607 }; 2608 2609 struct mlx5_ifc_db_bf_congestion_event_bits { 2610 u8 event_subtype[0x8]; 2611 u8 reserved_at_8[0x8]; 2612 u8 congestion_level[0x8]; 2613 u8 reserved_at_18[0x8]; 2614 2615 u8 reserved_at_20[0xa0]; 2616 }; 2617 2618 struct mlx5_ifc_gpio_event_bits { 2619 u8 reserved_at_0[0x60]; 2620 2621 u8 gpio_event_hi[0x20]; 2622 2623 u8 gpio_event_lo[0x20]; 2624 2625 u8 reserved_at_a0[0x40]; 2626 }; 2627 2628 struct mlx5_ifc_port_state_change_event_bits { 2629 u8 reserved_at_0[0x40]; 2630 2631 u8 port_num[0x4]; 2632 u8 reserved_at_44[0x1c]; 2633 2634 u8 reserved_at_60[0x80]; 2635 }; 2636 2637 struct mlx5_ifc_dropped_packet_logged_bits { 2638 u8 reserved_at_0[0xe0]; 2639 }; 2640 2641 enum { 2642 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2643 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2644 }; 2645 2646 struct mlx5_ifc_cq_error_bits { 2647 u8 reserved_at_0[0x8]; 2648 u8 cqn[0x18]; 2649 2650 u8 reserved_at_20[0x20]; 2651 2652 u8 reserved_at_40[0x18]; 2653 u8 syndrome[0x8]; 2654 2655 u8 reserved_at_60[0x80]; 2656 }; 2657 2658 struct mlx5_ifc_rdma_page_fault_event_bits { 2659 u8 bytes_committed[0x20]; 2660 2661 u8 r_key[0x20]; 2662 2663 u8 reserved_at_40[0x10]; 2664 u8 packet_len[0x10]; 2665 2666 u8 rdma_op_len[0x20]; 2667 2668 u8 rdma_va[0x40]; 2669 2670 u8 reserved_at_c0[0x5]; 2671 u8 rdma[0x1]; 2672 u8 write[0x1]; 2673 u8 requestor[0x1]; 2674 u8 qp_number[0x18]; 2675 }; 2676 2677 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2678 u8 bytes_committed[0x20]; 2679 2680 u8 reserved_at_20[0x10]; 2681 u8 wqe_index[0x10]; 2682 2683 u8 reserved_at_40[0x10]; 2684 u8 len[0x10]; 2685 2686 u8 reserved_at_60[0x60]; 2687 2688 u8 reserved_at_c0[0x5]; 2689 u8 rdma[0x1]; 2690 u8 write_read[0x1]; 2691 u8 requestor[0x1]; 2692 u8 qpn[0x18]; 2693 }; 2694 2695 struct mlx5_ifc_qp_events_bits { 2696 u8 reserved_at_0[0xa0]; 2697 2698 u8 type[0x8]; 2699 u8 reserved_at_a8[0x18]; 2700 2701 u8 reserved_at_c0[0x8]; 2702 u8 qpn_rqn_sqn[0x18]; 2703 }; 2704 2705 struct mlx5_ifc_dct_events_bits { 2706 u8 reserved_at_0[0xc0]; 2707 2708 u8 reserved_at_c0[0x8]; 2709 u8 dct_number[0x18]; 2710 }; 2711 2712 struct mlx5_ifc_comp_event_bits { 2713 u8 reserved_at_0[0xc0]; 2714 2715 u8 reserved_at_c0[0x8]; 2716 u8 cq_number[0x18]; 2717 }; 2718 2719 enum { 2720 MLX5_QPC_STATE_RST = 0x0, 2721 MLX5_QPC_STATE_INIT = 0x1, 2722 MLX5_QPC_STATE_RTR = 0x2, 2723 MLX5_QPC_STATE_RTS = 0x3, 2724 MLX5_QPC_STATE_SQER = 0x4, 2725 MLX5_QPC_STATE_ERR = 0x6, 2726 MLX5_QPC_STATE_SQD = 0x7, 2727 MLX5_QPC_STATE_SUSPENDED = 0x9, 2728 }; 2729 2730 enum { 2731 MLX5_QPC_ST_RC = 0x0, 2732 MLX5_QPC_ST_UC = 0x1, 2733 MLX5_QPC_ST_UD = 0x2, 2734 MLX5_QPC_ST_XRC = 0x3, 2735 MLX5_QPC_ST_DCI = 0x5, 2736 MLX5_QPC_ST_QP0 = 0x7, 2737 MLX5_QPC_ST_QP1 = 0x8, 2738 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2739 MLX5_QPC_ST_REG_UMR = 0xc, 2740 }; 2741 2742 enum { 2743 MLX5_QPC_PM_STATE_ARMED = 0x0, 2744 MLX5_QPC_PM_STATE_REARM = 0x1, 2745 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2746 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2747 }; 2748 2749 enum { 2750 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2751 }; 2752 2753 enum { 2754 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2755 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2756 }; 2757 2758 enum { 2759 MLX5_QPC_MTU_256_BYTES = 0x1, 2760 MLX5_QPC_MTU_512_BYTES = 0x2, 2761 MLX5_QPC_MTU_1K_BYTES = 0x3, 2762 MLX5_QPC_MTU_2K_BYTES = 0x4, 2763 MLX5_QPC_MTU_4K_BYTES = 0x5, 2764 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2765 }; 2766 2767 enum { 2768 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2769 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2770 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2771 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2772 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2773 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2774 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2775 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2776 }; 2777 2778 enum { 2779 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2780 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2781 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2782 }; 2783 2784 enum { 2785 MLX5_QPC_CS_RES_DISABLE = 0x0, 2786 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2787 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2788 }; 2789 2790 struct mlx5_ifc_qpc_bits { 2791 u8 state[0x4]; 2792 u8 lag_tx_port_affinity[0x4]; 2793 u8 st[0x8]; 2794 u8 reserved_at_10[0x3]; 2795 u8 pm_state[0x2]; 2796 u8 reserved_at_15[0x1]; 2797 u8 req_e2e_credit_mode[0x2]; 2798 u8 offload_type[0x4]; 2799 u8 end_padding_mode[0x2]; 2800 u8 reserved_at_1e[0x2]; 2801 2802 u8 wq_signature[0x1]; 2803 u8 block_lb_mc[0x1]; 2804 u8 atomic_like_write_en[0x1]; 2805 u8 latency_sensitive[0x1]; 2806 u8 reserved_at_24[0x1]; 2807 u8 drain_sigerr[0x1]; 2808 u8 reserved_at_26[0x2]; 2809 u8 pd[0x18]; 2810 2811 u8 mtu[0x3]; 2812 u8 log_msg_max[0x5]; 2813 u8 reserved_at_48[0x1]; 2814 u8 log_rq_size[0x4]; 2815 u8 log_rq_stride[0x3]; 2816 u8 no_sq[0x1]; 2817 u8 log_sq_size[0x4]; 2818 u8 reserved_at_55[0x6]; 2819 u8 rlky[0x1]; 2820 u8 ulp_stateless_offload_mode[0x4]; 2821 2822 u8 counter_set_id[0x8]; 2823 u8 uar_page[0x18]; 2824 2825 u8 reserved_at_80[0x8]; 2826 u8 user_index[0x18]; 2827 2828 u8 reserved_at_a0[0x3]; 2829 u8 log_page_size[0x5]; 2830 u8 remote_qpn[0x18]; 2831 2832 struct mlx5_ifc_ads_bits primary_address_path; 2833 2834 struct mlx5_ifc_ads_bits secondary_address_path; 2835 2836 u8 log_ack_req_freq[0x4]; 2837 u8 reserved_at_384[0x4]; 2838 u8 log_sra_max[0x3]; 2839 u8 reserved_at_38b[0x2]; 2840 u8 retry_count[0x3]; 2841 u8 rnr_retry[0x3]; 2842 u8 reserved_at_393[0x1]; 2843 u8 fre[0x1]; 2844 u8 cur_rnr_retry[0x3]; 2845 u8 cur_retry_count[0x3]; 2846 u8 reserved_at_39b[0x5]; 2847 2848 u8 reserved_at_3a0[0x20]; 2849 2850 u8 reserved_at_3c0[0x8]; 2851 u8 next_send_psn[0x18]; 2852 2853 u8 reserved_at_3e0[0x8]; 2854 u8 cqn_snd[0x18]; 2855 2856 u8 reserved_at_400[0x8]; 2857 u8 deth_sqpn[0x18]; 2858 2859 u8 reserved_at_420[0x20]; 2860 2861 u8 reserved_at_440[0x8]; 2862 u8 last_acked_psn[0x18]; 2863 2864 u8 reserved_at_460[0x8]; 2865 u8 ssn[0x18]; 2866 2867 u8 reserved_at_480[0x8]; 2868 u8 log_rra_max[0x3]; 2869 u8 reserved_at_48b[0x1]; 2870 u8 atomic_mode[0x4]; 2871 u8 rre[0x1]; 2872 u8 rwe[0x1]; 2873 u8 rae[0x1]; 2874 u8 reserved_at_493[0x1]; 2875 u8 page_offset[0x6]; 2876 u8 reserved_at_49a[0x3]; 2877 u8 cd_slave_receive[0x1]; 2878 u8 cd_slave_send[0x1]; 2879 u8 cd_master[0x1]; 2880 2881 u8 reserved_at_4a0[0x3]; 2882 u8 min_rnr_nak[0x5]; 2883 u8 next_rcv_psn[0x18]; 2884 2885 u8 reserved_at_4c0[0x8]; 2886 u8 xrcd[0x18]; 2887 2888 u8 reserved_at_4e0[0x8]; 2889 u8 cqn_rcv[0x18]; 2890 2891 u8 dbr_addr[0x40]; 2892 2893 u8 q_key[0x20]; 2894 2895 u8 reserved_at_560[0x5]; 2896 u8 rq_type[0x3]; 2897 u8 srqn_rmpn_xrqn[0x18]; 2898 2899 u8 reserved_at_580[0x8]; 2900 u8 rmsn[0x18]; 2901 2902 u8 hw_sq_wqebb_counter[0x10]; 2903 u8 sw_sq_wqebb_counter[0x10]; 2904 2905 u8 hw_rq_counter[0x20]; 2906 2907 u8 sw_rq_counter[0x20]; 2908 2909 u8 reserved_at_600[0x20]; 2910 2911 u8 reserved_at_620[0xf]; 2912 u8 cgs[0x1]; 2913 u8 cs_req[0x8]; 2914 u8 cs_res[0x8]; 2915 2916 u8 dc_access_key[0x40]; 2917 2918 u8 reserved_at_680[0x3]; 2919 u8 dbr_umem_valid[0x1]; 2920 2921 u8 reserved_at_684[0xbc]; 2922 }; 2923 2924 struct mlx5_ifc_roce_addr_layout_bits { 2925 u8 source_l3_address[16][0x8]; 2926 2927 u8 reserved_at_80[0x3]; 2928 u8 vlan_valid[0x1]; 2929 u8 vlan_id[0xc]; 2930 u8 source_mac_47_32[0x10]; 2931 2932 u8 source_mac_31_0[0x20]; 2933 2934 u8 reserved_at_c0[0x14]; 2935 u8 roce_l3_type[0x4]; 2936 u8 roce_version[0x8]; 2937 2938 u8 reserved_at_e0[0x20]; 2939 }; 2940 2941 union mlx5_ifc_hca_cap_union_bits { 2942 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2943 struct mlx5_ifc_odp_cap_bits odp_cap; 2944 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2945 struct mlx5_ifc_roce_cap_bits roce_cap; 2946 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2947 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2948 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2949 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2950 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2951 struct mlx5_ifc_qos_cap_bits qos_cap; 2952 struct mlx5_ifc_debug_cap_bits debug_cap; 2953 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2954 struct mlx5_ifc_tls_cap_bits tls_cap; 2955 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2956 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap; 2957 u8 reserved_at_0[0x8000]; 2958 }; 2959 2960 enum { 2961 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2962 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2963 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2964 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2965 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2966 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2967 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2968 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2969 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2970 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2971 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2972 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 2973 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 2974 }; 2975 2976 enum { 2977 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2978 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2979 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2980 }; 2981 2982 struct mlx5_ifc_vlan_bits { 2983 u8 ethtype[0x10]; 2984 u8 prio[0x3]; 2985 u8 cfi[0x1]; 2986 u8 vid[0xc]; 2987 }; 2988 2989 struct mlx5_ifc_flow_context_bits { 2990 struct mlx5_ifc_vlan_bits push_vlan; 2991 2992 u8 group_id[0x20]; 2993 2994 u8 reserved_at_40[0x8]; 2995 u8 flow_tag[0x18]; 2996 2997 u8 reserved_at_60[0x10]; 2998 u8 action[0x10]; 2999 3000 u8 extended_destination[0x1]; 3001 u8 reserved_at_81[0x1]; 3002 u8 flow_source[0x2]; 3003 u8 reserved_at_84[0x4]; 3004 u8 destination_list_size[0x18]; 3005 3006 u8 reserved_at_a0[0x8]; 3007 u8 flow_counter_list_size[0x18]; 3008 3009 u8 packet_reformat_id[0x20]; 3010 3011 u8 modify_header_id[0x20]; 3012 3013 struct mlx5_ifc_vlan_bits push_vlan_2; 3014 3015 u8 ipsec_obj_id[0x20]; 3016 u8 reserved_at_140[0xc0]; 3017 3018 struct mlx5_ifc_fte_match_param_bits match_value; 3019 3020 u8 reserved_at_1200[0x600]; 3021 3022 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3023 }; 3024 3025 enum { 3026 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3027 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3028 }; 3029 3030 struct mlx5_ifc_xrc_srqc_bits { 3031 u8 state[0x4]; 3032 u8 log_xrc_srq_size[0x4]; 3033 u8 reserved_at_8[0x18]; 3034 3035 u8 wq_signature[0x1]; 3036 u8 cont_srq[0x1]; 3037 u8 reserved_at_22[0x1]; 3038 u8 rlky[0x1]; 3039 u8 basic_cyclic_rcv_wqe[0x1]; 3040 u8 log_rq_stride[0x3]; 3041 u8 xrcd[0x18]; 3042 3043 u8 page_offset[0x6]; 3044 u8 reserved_at_46[0x1]; 3045 u8 dbr_umem_valid[0x1]; 3046 u8 cqn[0x18]; 3047 3048 u8 reserved_at_60[0x20]; 3049 3050 u8 user_index_equal_xrc_srqn[0x1]; 3051 u8 reserved_at_81[0x1]; 3052 u8 log_page_size[0x6]; 3053 u8 user_index[0x18]; 3054 3055 u8 reserved_at_a0[0x20]; 3056 3057 u8 reserved_at_c0[0x8]; 3058 u8 pd[0x18]; 3059 3060 u8 lwm[0x10]; 3061 u8 wqe_cnt[0x10]; 3062 3063 u8 reserved_at_100[0x40]; 3064 3065 u8 db_record_addr_h[0x20]; 3066 3067 u8 db_record_addr_l[0x1e]; 3068 u8 reserved_at_17e[0x2]; 3069 3070 u8 reserved_at_180[0x80]; 3071 }; 3072 3073 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3074 u8 counter_error_queues[0x20]; 3075 3076 u8 total_error_queues[0x20]; 3077 3078 u8 send_queue_priority_update_flow[0x20]; 3079 3080 u8 reserved_at_60[0x20]; 3081 3082 u8 nic_receive_steering_discard[0x40]; 3083 3084 u8 receive_discard_vport_down[0x40]; 3085 3086 u8 transmit_discard_vport_down[0x40]; 3087 3088 u8 reserved_at_140[0xa0]; 3089 3090 u8 internal_rq_out_of_buffer[0x20]; 3091 3092 u8 reserved_at_200[0xe00]; 3093 }; 3094 3095 struct mlx5_ifc_traffic_counter_bits { 3096 u8 packets[0x40]; 3097 3098 u8 octets[0x40]; 3099 }; 3100 3101 struct mlx5_ifc_tisc_bits { 3102 u8 strict_lag_tx_port_affinity[0x1]; 3103 u8 tls_en[0x1]; 3104 u8 reserved_at_2[0x2]; 3105 u8 lag_tx_port_affinity[0x04]; 3106 3107 u8 reserved_at_8[0x4]; 3108 u8 prio[0x4]; 3109 u8 reserved_at_10[0x10]; 3110 3111 u8 reserved_at_20[0x100]; 3112 3113 u8 reserved_at_120[0x8]; 3114 u8 transport_domain[0x18]; 3115 3116 u8 reserved_at_140[0x8]; 3117 u8 underlay_qpn[0x18]; 3118 3119 u8 reserved_at_160[0x8]; 3120 u8 pd[0x18]; 3121 3122 u8 reserved_at_180[0x380]; 3123 }; 3124 3125 enum { 3126 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3127 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3128 }; 3129 3130 enum { 3131 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3132 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3133 }; 3134 3135 enum { 3136 MLX5_RX_HASH_FN_NONE = 0x0, 3137 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3138 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3139 }; 3140 3141 enum { 3142 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3143 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3144 }; 3145 3146 struct mlx5_ifc_tirc_bits { 3147 u8 reserved_at_0[0x20]; 3148 3149 u8 disp_type[0x4]; 3150 u8 tls_en[0x1]; 3151 u8 reserved_at_25[0x1b]; 3152 3153 u8 reserved_at_40[0x40]; 3154 3155 u8 reserved_at_80[0x4]; 3156 u8 lro_timeout_period_usecs[0x10]; 3157 u8 lro_enable_mask[0x4]; 3158 u8 lro_max_ip_payload_size[0x8]; 3159 3160 u8 reserved_at_a0[0x40]; 3161 3162 u8 reserved_at_e0[0x8]; 3163 u8 inline_rqn[0x18]; 3164 3165 u8 rx_hash_symmetric[0x1]; 3166 u8 reserved_at_101[0x1]; 3167 u8 tunneled_offload_en[0x1]; 3168 u8 reserved_at_103[0x5]; 3169 u8 indirect_table[0x18]; 3170 3171 u8 rx_hash_fn[0x4]; 3172 u8 reserved_at_124[0x2]; 3173 u8 self_lb_block[0x2]; 3174 u8 transport_domain[0x18]; 3175 3176 u8 rx_hash_toeplitz_key[10][0x20]; 3177 3178 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3179 3180 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3181 3182 u8 reserved_at_2c0[0x4c0]; 3183 }; 3184 3185 enum { 3186 MLX5_SRQC_STATE_GOOD = 0x0, 3187 MLX5_SRQC_STATE_ERROR = 0x1, 3188 }; 3189 3190 struct mlx5_ifc_srqc_bits { 3191 u8 state[0x4]; 3192 u8 log_srq_size[0x4]; 3193 u8 reserved_at_8[0x18]; 3194 3195 u8 wq_signature[0x1]; 3196 u8 cont_srq[0x1]; 3197 u8 reserved_at_22[0x1]; 3198 u8 rlky[0x1]; 3199 u8 reserved_at_24[0x1]; 3200 u8 log_rq_stride[0x3]; 3201 u8 xrcd[0x18]; 3202 3203 u8 page_offset[0x6]; 3204 u8 reserved_at_46[0x2]; 3205 u8 cqn[0x18]; 3206 3207 u8 reserved_at_60[0x20]; 3208 3209 u8 reserved_at_80[0x2]; 3210 u8 log_page_size[0x6]; 3211 u8 reserved_at_88[0x18]; 3212 3213 u8 reserved_at_a0[0x20]; 3214 3215 u8 reserved_at_c0[0x8]; 3216 u8 pd[0x18]; 3217 3218 u8 lwm[0x10]; 3219 u8 wqe_cnt[0x10]; 3220 3221 u8 reserved_at_100[0x40]; 3222 3223 u8 dbr_addr[0x40]; 3224 3225 u8 reserved_at_180[0x80]; 3226 }; 3227 3228 enum { 3229 MLX5_SQC_STATE_RST = 0x0, 3230 MLX5_SQC_STATE_RDY = 0x1, 3231 MLX5_SQC_STATE_ERR = 0x3, 3232 }; 3233 3234 struct mlx5_ifc_sqc_bits { 3235 u8 rlky[0x1]; 3236 u8 cd_master[0x1]; 3237 u8 fre[0x1]; 3238 u8 flush_in_error_en[0x1]; 3239 u8 allow_multi_pkt_send_wqe[0x1]; 3240 u8 min_wqe_inline_mode[0x3]; 3241 u8 state[0x4]; 3242 u8 reg_umr[0x1]; 3243 u8 allow_swp[0x1]; 3244 u8 hairpin[0x1]; 3245 u8 reserved_at_f[0x11]; 3246 3247 u8 reserved_at_20[0x8]; 3248 u8 user_index[0x18]; 3249 3250 u8 reserved_at_40[0x8]; 3251 u8 cqn[0x18]; 3252 3253 u8 reserved_at_60[0x8]; 3254 u8 hairpin_peer_rq[0x18]; 3255 3256 u8 reserved_at_80[0x10]; 3257 u8 hairpin_peer_vhca[0x10]; 3258 3259 u8 reserved_at_a0[0x50]; 3260 3261 u8 packet_pacing_rate_limit_index[0x10]; 3262 u8 tis_lst_sz[0x10]; 3263 u8 reserved_at_110[0x10]; 3264 3265 u8 reserved_at_120[0x40]; 3266 3267 u8 reserved_at_160[0x8]; 3268 u8 tis_num_0[0x18]; 3269 3270 struct mlx5_ifc_wq_bits wq; 3271 }; 3272 3273 enum { 3274 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3275 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3276 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3277 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3278 }; 3279 3280 enum { 3281 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3282 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3283 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3284 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3285 }; 3286 3287 struct mlx5_ifc_scheduling_context_bits { 3288 u8 element_type[0x8]; 3289 u8 reserved_at_8[0x18]; 3290 3291 u8 element_attributes[0x20]; 3292 3293 u8 parent_element_id[0x20]; 3294 3295 u8 reserved_at_60[0x40]; 3296 3297 u8 bw_share[0x20]; 3298 3299 u8 max_average_bw[0x20]; 3300 3301 u8 reserved_at_e0[0x120]; 3302 }; 3303 3304 struct mlx5_ifc_rqtc_bits { 3305 u8 reserved_at_0[0xa0]; 3306 3307 u8 reserved_at_a0[0x10]; 3308 u8 rqt_max_size[0x10]; 3309 3310 u8 reserved_at_c0[0x10]; 3311 u8 rqt_actual_size[0x10]; 3312 3313 u8 reserved_at_e0[0x6a0]; 3314 3315 struct mlx5_ifc_rq_num_bits rq_num[]; 3316 }; 3317 3318 enum { 3319 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3320 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3321 }; 3322 3323 enum { 3324 MLX5_RQC_STATE_RST = 0x0, 3325 MLX5_RQC_STATE_RDY = 0x1, 3326 MLX5_RQC_STATE_ERR = 0x3, 3327 }; 3328 3329 struct mlx5_ifc_rqc_bits { 3330 u8 rlky[0x1]; 3331 u8 delay_drop_en[0x1]; 3332 u8 scatter_fcs[0x1]; 3333 u8 vsd[0x1]; 3334 u8 mem_rq_type[0x4]; 3335 u8 state[0x4]; 3336 u8 reserved_at_c[0x1]; 3337 u8 flush_in_error_en[0x1]; 3338 u8 hairpin[0x1]; 3339 u8 reserved_at_f[0x11]; 3340 3341 u8 reserved_at_20[0x8]; 3342 u8 user_index[0x18]; 3343 3344 u8 reserved_at_40[0x8]; 3345 u8 cqn[0x18]; 3346 3347 u8 counter_set_id[0x8]; 3348 u8 reserved_at_68[0x18]; 3349 3350 u8 reserved_at_80[0x8]; 3351 u8 rmpn[0x18]; 3352 3353 u8 reserved_at_a0[0x8]; 3354 u8 hairpin_peer_sq[0x18]; 3355 3356 u8 reserved_at_c0[0x10]; 3357 u8 hairpin_peer_vhca[0x10]; 3358 3359 u8 reserved_at_e0[0xa0]; 3360 3361 struct mlx5_ifc_wq_bits wq; 3362 }; 3363 3364 enum { 3365 MLX5_RMPC_STATE_RDY = 0x1, 3366 MLX5_RMPC_STATE_ERR = 0x3, 3367 }; 3368 3369 struct mlx5_ifc_rmpc_bits { 3370 u8 reserved_at_0[0x8]; 3371 u8 state[0x4]; 3372 u8 reserved_at_c[0x14]; 3373 3374 u8 basic_cyclic_rcv_wqe[0x1]; 3375 u8 reserved_at_21[0x1f]; 3376 3377 u8 reserved_at_40[0x140]; 3378 3379 struct mlx5_ifc_wq_bits wq; 3380 }; 3381 3382 struct mlx5_ifc_nic_vport_context_bits { 3383 u8 reserved_at_0[0x5]; 3384 u8 min_wqe_inline_mode[0x3]; 3385 u8 reserved_at_8[0x15]; 3386 u8 disable_mc_local_lb[0x1]; 3387 u8 disable_uc_local_lb[0x1]; 3388 u8 roce_en[0x1]; 3389 3390 u8 arm_change_event[0x1]; 3391 u8 reserved_at_21[0x1a]; 3392 u8 event_on_mtu[0x1]; 3393 u8 event_on_promisc_change[0x1]; 3394 u8 event_on_vlan_change[0x1]; 3395 u8 event_on_mc_address_change[0x1]; 3396 u8 event_on_uc_address_change[0x1]; 3397 3398 u8 reserved_at_40[0xc]; 3399 3400 u8 affiliation_criteria[0x4]; 3401 u8 affiliated_vhca_id[0x10]; 3402 3403 u8 reserved_at_60[0xd0]; 3404 3405 u8 mtu[0x10]; 3406 3407 u8 system_image_guid[0x40]; 3408 u8 port_guid[0x40]; 3409 u8 node_guid[0x40]; 3410 3411 u8 reserved_at_200[0x140]; 3412 u8 qkey_violation_counter[0x10]; 3413 u8 reserved_at_350[0x430]; 3414 3415 u8 promisc_uc[0x1]; 3416 u8 promisc_mc[0x1]; 3417 u8 promisc_all[0x1]; 3418 u8 reserved_at_783[0x2]; 3419 u8 allowed_list_type[0x3]; 3420 u8 reserved_at_788[0xc]; 3421 u8 allowed_list_size[0xc]; 3422 3423 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3424 3425 u8 reserved_at_7e0[0x20]; 3426 3427 u8 current_uc_mac_address[][0x40]; 3428 }; 3429 3430 enum { 3431 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3432 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3433 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3434 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3435 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3436 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3437 }; 3438 3439 struct mlx5_ifc_mkc_bits { 3440 u8 reserved_at_0[0x1]; 3441 u8 free[0x1]; 3442 u8 reserved_at_2[0x1]; 3443 u8 access_mode_4_2[0x3]; 3444 u8 reserved_at_6[0x7]; 3445 u8 relaxed_ordering_write[0x1]; 3446 u8 reserved_at_e[0x1]; 3447 u8 small_fence_on_rdma_read_response[0x1]; 3448 u8 umr_en[0x1]; 3449 u8 a[0x1]; 3450 u8 rw[0x1]; 3451 u8 rr[0x1]; 3452 u8 lw[0x1]; 3453 u8 lr[0x1]; 3454 u8 access_mode_1_0[0x2]; 3455 u8 reserved_at_18[0x8]; 3456 3457 u8 qpn[0x18]; 3458 u8 mkey_7_0[0x8]; 3459 3460 u8 reserved_at_40[0x20]; 3461 3462 u8 length64[0x1]; 3463 u8 bsf_en[0x1]; 3464 u8 sync_umr[0x1]; 3465 u8 reserved_at_63[0x2]; 3466 u8 expected_sigerr_count[0x1]; 3467 u8 reserved_at_66[0x1]; 3468 u8 en_rinval[0x1]; 3469 u8 pd[0x18]; 3470 3471 u8 start_addr[0x40]; 3472 3473 u8 len[0x40]; 3474 3475 u8 bsf_octword_size[0x20]; 3476 3477 u8 reserved_at_120[0x80]; 3478 3479 u8 translations_octword_size[0x20]; 3480 3481 u8 reserved_at_1c0[0x19]; 3482 u8 relaxed_ordering_read[0x1]; 3483 u8 reserved_at_1d9[0x1]; 3484 u8 log_page_size[0x5]; 3485 3486 u8 reserved_at_1e0[0x20]; 3487 }; 3488 3489 struct mlx5_ifc_pkey_bits { 3490 u8 reserved_at_0[0x10]; 3491 u8 pkey[0x10]; 3492 }; 3493 3494 struct mlx5_ifc_array128_auto_bits { 3495 u8 array128_auto[16][0x8]; 3496 }; 3497 3498 struct mlx5_ifc_hca_vport_context_bits { 3499 u8 field_select[0x20]; 3500 3501 u8 reserved_at_20[0xe0]; 3502 3503 u8 sm_virt_aware[0x1]; 3504 u8 has_smi[0x1]; 3505 u8 has_raw[0x1]; 3506 u8 grh_required[0x1]; 3507 u8 reserved_at_104[0xc]; 3508 u8 port_physical_state[0x4]; 3509 u8 vport_state_policy[0x4]; 3510 u8 port_state[0x4]; 3511 u8 vport_state[0x4]; 3512 3513 u8 reserved_at_120[0x20]; 3514 3515 u8 system_image_guid[0x40]; 3516 3517 u8 port_guid[0x40]; 3518 3519 u8 node_guid[0x40]; 3520 3521 u8 cap_mask1[0x20]; 3522 3523 u8 cap_mask1_field_select[0x20]; 3524 3525 u8 cap_mask2[0x20]; 3526 3527 u8 cap_mask2_field_select[0x20]; 3528 3529 u8 reserved_at_280[0x80]; 3530 3531 u8 lid[0x10]; 3532 u8 reserved_at_310[0x4]; 3533 u8 init_type_reply[0x4]; 3534 u8 lmc[0x3]; 3535 u8 subnet_timeout[0x5]; 3536 3537 u8 sm_lid[0x10]; 3538 u8 sm_sl[0x4]; 3539 u8 reserved_at_334[0xc]; 3540 3541 u8 qkey_violation_counter[0x10]; 3542 u8 pkey_violation_counter[0x10]; 3543 3544 u8 reserved_at_360[0xca0]; 3545 }; 3546 3547 struct mlx5_ifc_esw_vport_context_bits { 3548 u8 fdb_to_vport_reg_c[0x1]; 3549 u8 reserved_at_1[0x2]; 3550 u8 vport_svlan_strip[0x1]; 3551 u8 vport_cvlan_strip[0x1]; 3552 u8 vport_svlan_insert[0x1]; 3553 u8 vport_cvlan_insert[0x2]; 3554 u8 fdb_to_vport_reg_c_id[0x8]; 3555 u8 reserved_at_10[0x10]; 3556 3557 u8 reserved_at_20[0x20]; 3558 3559 u8 svlan_cfi[0x1]; 3560 u8 svlan_pcp[0x3]; 3561 u8 svlan_id[0xc]; 3562 u8 cvlan_cfi[0x1]; 3563 u8 cvlan_pcp[0x3]; 3564 u8 cvlan_id[0xc]; 3565 3566 u8 reserved_at_60[0x720]; 3567 3568 u8 sw_steering_vport_icm_address_rx[0x40]; 3569 3570 u8 sw_steering_vport_icm_address_tx[0x40]; 3571 }; 3572 3573 enum { 3574 MLX5_EQC_STATUS_OK = 0x0, 3575 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3576 }; 3577 3578 enum { 3579 MLX5_EQC_ST_ARMED = 0x9, 3580 MLX5_EQC_ST_FIRED = 0xa, 3581 }; 3582 3583 struct mlx5_ifc_eqc_bits { 3584 u8 status[0x4]; 3585 u8 reserved_at_4[0x9]; 3586 u8 ec[0x1]; 3587 u8 oi[0x1]; 3588 u8 reserved_at_f[0x5]; 3589 u8 st[0x4]; 3590 u8 reserved_at_18[0x8]; 3591 3592 u8 reserved_at_20[0x20]; 3593 3594 u8 reserved_at_40[0x14]; 3595 u8 page_offset[0x6]; 3596 u8 reserved_at_5a[0x6]; 3597 3598 u8 reserved_at_60[0x3]; 3599 u8 log_eq_size[0x5]; 3600 u8 uar_page[0x18]; 3601 3602 u8 reserved_at_80[0x20]; 3603 3604 u8 reserved_at_a0[0x18]; 3605 u8 intr[0x8]; 3606 3607 u8 reserved_at_c0[0x3]; 3608 u8 log_page_size[0x5]; 3609 u8 reserved_at_c8[0x18]; 3610 3611 u8 reserved_at_e0[0x60]; 3612 3613 u8 reserved_at_140[0x8]; 3614 u8 consumer_counter[0x18]; 3615 3616 u8 reserved_at_160[0x8]; 3617 u8 producer_counter[0x18]; 3618 3619 u8 reserved_at_180[0x80]; 3620 }; 3621 3622 enum { 3623 MLX5_DCTC_STATE_ACTIVE = 0x0, 3624 MLX5_DCTC_STATE_DRAINING = 0x1, 3625 MLX5_DCTC_STATE_DRAINED = 0x2, 3626 }; 3627 3628 enum { 3629 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3630 MLX5_DCTC_CS_RES_NA = 0x1, 3631 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3632 }; 3633 3634 enum { 3635 MLX5_DCTC_MTU_256_BYTES = 0x1, 3636 MLX5_DCTC_MTU_512_BYTES = 0x2, 3637 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3638 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3639 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3640 }; 3641 3642 struct mlx5_ifc_dctc_bits { 3643 u8 reserved_at_0[0x4]; 3644 u8 state[0x4]; 3645 u8 reserved_at_8[0x18]; 3646 3647 u8 reserved_at_20[0x8]; 3648 u8 user_index[0x18]; 3649 3650 u8 reserved_at_40[0x8]; 3651 u8 cqn[0x18]; 3652 3653 u8 counter_set_id[0x8]; 3654 u8 atomic_mode[0x4]; 3655 u8 rre[0x1]; 3656 u8 rwe[0x1]; 3657 u8 rae[0x1]; 3658 u8 atomic_like_write_en[0x1]; 3659 u8 latency_sensitive[0x1]; 3660 u8 rlky[0x1]; 3661 u8 free_ar[0x1]; 3662 u8 reserved_at_73[0xd]; 3663 3664 u8 reserved_at_80[0x8]; 3665 u8 cs_res[0x8]; 3666 u8 reserved_at_90[0x3]; 3667 u8 min_rnr_nak[0x5]; 3668 u8 reserved_at_98[0x8]; 3669 3670 u8 reserved_at_a0[0x8]; 3671 u8 srqn_xrqn[0x18]; 3672 3673 u8 reserved_at_c0[0x8]; 3674 u8 pd[0x18]; 3675 3676 u8 tclass[0x8]; 3677 u8 reserved_at_e8[0x4]; 3678 u8 flow_label[0x14]; 3679 3680 u8 dc_access_key[0x40]; 3681 3682 u8 reserved_at_140[0x5]; 3683 u8 mtu[0x3]; 3684 u8 port[0x8]; 3685 u8 pkey_index[0x10]; 3686 3687 u8 reserved_at_160[0x8]; 3688 u8 my_addr_index[0x8]; 3689 u8 reserved_at_170[0x8]; 3690 u8 hop_limit[0x8]; 3691 3692 u8 dc_access_key_violation_count[0x20]; 3693 3694 u8 reserved_at_1a0[0x14]; 3695 u8 dei_cfi[0x1]; 3696 u8 eth_prio[0x3]; 3697 u8 ecn[0x2]; 3698 u8 dscp[0x6]; 3699 3700 u8 reserved_at_1c0[0x20]; 3701 u8 ece[0x20]; 3702 }; 3703 3704 enum { 3705 MLX5_CQC_STATUS_OK = 0x0, 3706 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3707 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3708 }; 3709 3710 enum { 3711 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3712 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3713 }; 3714 3715 enum { 3716 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3717 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3718 MLX5_CQC_ST_FIRED = 0xa, 3719 }; 3720 3721 enum { 3722 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3723 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3724 MLX5_CQ_PERIOD_NUM_MODES 3725 }; 3726 3727 struct mlx5_ifc_cqc_bits { 3728 u8 status[0x4]; 3729 u8 reserved_at_4[0x2]; 3730 u8 dbr_umem_valid[0x1]; 3731 u8 reserved_at_7[0x1]; 3732 u8 cqe_sz[0x3]; 3733 u8 cc[0x1]; 3734 u8 reserved_at_c[0x1]; 3735 u8 scqe_break_moderation_en[0x1]; 3736 u8 oi[0x1]; 3737 u8 cq_period_mode[0x2]; 3738 u8 cqe_comp_en[0x1]; 3739 u8 mini_cqe_res_format[0x2]; 3740 u8 st[0x4]; 3741 u8 reserved_at_18[0x8]; 3742 3743 u8 reserved_at_20[0x20]; 3744 3745 u8 reserved_at_40[0x14]; 3746 u8 page_offset[0x6]; 3747 u8 reserved_at_5a[0x6]; 3748 3749 u8 reserved_at_60[0x3]; 3750 u8 log_cq_size[0x5]; 3751 u8 uar_page[0x18]; 3752 3753 u8 reserved_at_80[0x4]; 3754 u8 cq_period[0xc]; 3755 u8 cq_max_count[0x10]; 3756 3757 u8 reserved_at_a0[0x18]; 3758 u8 c_eqn[0x8]; 3759 3760 u8 reserved_at_c0[0x3]; 3761 u8 log_page_size[0x5]; 3762 u8 reserved_at_c8[0x18]; 3763 3764 u8 reserved_at_e0[0x20]; 3765 3766 u8 reserved_at_100[0x8]; 3767 u8 last_notified_index[0x18]; 3768 3769 u8 reserved_at_120[0x8]; 3770 u8 last_solicit_index[0x18]; 3771 3772 u8 reserved_at_140[0x8]; 3773 u8 consumer_counter[0x18]; 3774 3775 u8 reserved_at_160[0x8]; 3776 u8 producer_counter[0x18]; 3777 3778 u8 reserved_at_180[0x40]; 3779 3780 u8 dbr_addr[0x40]; 3781 }; 3782 3783 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3784 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3785 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3786 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3787 u8 reserved_at_0[0x800]; 3788 }; 3789 3790 struct mlx5_ifc_query_adapter_param_block_bits { 3791 u8 reserved_at_0[0xc0]; 3792 3793 u8 reserved_at_c0[0x8]; 3794 u8 ieee_vendor_id[0x18]; 3795 3796 u8 reserved_at_e0[0x10]; 3797 u8 vsd_vendor_id[0x10]; 3798 3799 u8 vsd[208][0x8]; 3800 3801 u8 vsd_contd_psid[16][0x8]; 3802 }; 3803 3804 enum { 3805 MLX5_XRQC_STATE_GOOD = 0x0, 3806 MLX5_XRQC_STATE_ERROR = 0x1, 3807 }; 3808 3809 enum { 3810 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3811 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3812 }; 3813 3814 enum { 3815 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3816 }; 3817 3818 struct mlx5_ifc_tag_matching_topology_context_bits { 3819 u8 log_matching_list_sz[0x4]; 3820 u8 reserved_at_4[0xc]; 3821 u8 append_next_index[0x10]; 3822 3823 u8 sw_phase_cnt[0x10]; 3824 u8 hw_phase_cnt[0x10]; 3825 3826 u8 reserved_at_40[0x40]; 3827 }; 3828 3829 struct mlx5_ifc_xrqc_bits { 3830 u8 state[0x4]; 3831 u8 rlkey[0x1]; 3832 u8 reserved_at_5[0xf]; 3833 u8 topology[0x4]; 3834 u8 reserved_at_18[0x4]; 3835 u8 offload[0x4]; 3836 3837 u8 reserved_at_20[0x8]; 3838 u8 user_index[0x18]; 3839 3840 u8 reserved_at_40[0x8]; 3841 u8 cqn[0x18]; 3842 3843 u8 reserved_at_60[0xa0]; 3844 3845 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3846 3847 u8 reserved_at_180[0x280]; 3848 3849 struct mlx5_ifc_wq_bits wq; 3850 }; 3851 3852 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3853 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3854 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3855 u8 reserved_at_0[0x20]; 3856 }; 3857 3858 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3859 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3860 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3861 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3862 u8 reserved_at_0[0x20]; 3863 }; 3864 3865 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3866 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3867 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3868 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3869 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3870 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3871 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3872 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3873 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3874 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3875 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3876 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3877 u8 reserved_at_0[0x7c0]; 3878 }; 3879 3880 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3881 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3882 u8 reserved_at_0[0x7c0]; 3883 }; 3884 3885 union mlx5_ifc_event_auto_bits { 3886 struct mlx5_ifc_comp_event_bits comp_event; 3887 struct mlx5_ifc_dct_events_bits dct_events; 3888 struct mlx5_ifc_qp_events_bits qp_events; 3889 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3890 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3891 struct mlx5_ifc_cq_error_bits cq_error; 3892 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3893 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3894 struct mlx5_ifc_gpio_event_bits gpio_event; 3895 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3896 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3897 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3898 u8 reserved_at_0[0xe0]; 3899 }; 3900 3901 struct mlx5_ifc_health_buffer_bits { 3902 u8 reserved_at_0[0x100]; 3903 3904 u8 assert_existptr[0x20]; 3905 3906 u8 assert_callra[0x20]; 3907 3908 u8 reserved_at_140[0x40]; 3909 3910 u8 fw_version[0x20]; 3911 3912 u8 hw_id[0x20]; 3913 3914 u8 reserved_at_1c0[0x20]; 3915 3916 u8 irisc_index[0x8]; 3917 u8 synd[0x8]; 3918 u8 ext_synd[0x10]; 3919 }; 3920 3921 struct mlx5_ifc_register_loopback_control_bits { 3922 u8 no_lb[0x1]; 3923 u8 reserved_at_1[0x7]; 3924 u8 port[0x8]; 3925 u8 reserved_at_10[0x10]; 3926 3927 u8 reserved_at_20[0x60]; 3928 }; 3929 3930 struct mlx5_ifc_vport_tc_element_bits { 3931 u8 traffic_class[0x4]; 3932 u8 reserved_at_4[0xc]; 3933 u8 vport_number[0x10]; 3934 }; 3935 3936 struct mlx5_ifc_vport_element_bits { 3937 u8 reserved_at_0[0x10]; 3938 u8 vport_number[0x10]; 3939 }; 3940 3941 enum { 3942 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3943 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3944 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3945 }; 3946 3947 struct mlx5_ifc_tsar_element_bits { 3948 u8 reserved_at_0[0x8]; 3949 u8 tsar_type[0x8]; 3950 u8 reserved_at_10[0x10]; 3951 }; 3952 3953 enum { 3954 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3955 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3956 }; 3957 3958 struct mlx5_ifc_teardown_hca_out_bits { 3959 u8 status[0x8]; 3960 u8 reserved_at_8[0x18]; 3961 3962 u8 syndrome[0x20]; 3963 3964 u8 reserved_at_40[0x3f]; 3965 3966 u8 state[0x1]; 3967 }; 3968 3969 enum { 3970 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3971 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3972 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3973 }; 3974 3975 struct mlx5_ifc_teardown_hca_in_bits { 3976 u8 opcode[0x10]; 3977 u8 reserved_at_10[0x10]; 3978 3979 u8 reserved_at_20[0x10]; 3980 u8 op_mod[0x10]; 3981 3982 u8 reserved_at_40[0x10]; 3983 u8 profile[0x10]; 3984 3985 u8 reserved_at_60[0x20]; 3986 }; 3987 3988 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3989 u8 status[0x8]; 3990 u8 reserved_at_8[0x18]; 3991 3992 u8 syndrome[0x20]; 3993 3994 u8 reserved_at_40[0x40]; 3995 }; 3996 3997 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3998 u8 opcode[0x10]; 3999 u8 uid[0x10]; 4000 4001 u8 reserved_at_20[0x10]; 4002 u8 op_mod[0x10]; 4003 4004 u8 reserved_at_40[0x8]; 4005 u8 qpn[0x18]; 4006 4007 u8 reserved_at_60[0x20]; 4008 4009 u8 opt_param_mask[0x20]; 4010 4011 u8 reserved_at_a0[0x20]; 4012 4013 struct mlx5_ifc_qpc_bits qpc; 4014 4015 u8 reserved_at_800[0x80]; 4016 }; 4017 4018 struct mlx5_ifc_sqd2rts_qp_out_bits { 4019 u8 status[0x8]; 4020 u8 reserved_at_8[0x18]; 4021 4022 u8 syndrome[0x20]; 4023 4024 u8 reserved_at_40[0x40]; 4025 }; 4026 4027 struct mlx5_ifc_sqd2rts_qp_in_bits { 4028 u8 opcode[0x10]; 4029 u8 uid[0x10]; 4030 4031 u8 reserved_at_20[0x10]; 4032 u8 op_mod[0x10]; 4033 4034 u8 reserved_at_40[0x8]; 4035 u8 qpn[0x18]; 4036 4037 u8 reserved_at_60[0x20]; 4038 4039 u8 opt_param_mask[0x20]; 4040 4041 u8 reserved_at_a0[0x20]; 4042 4043 struct mlx5_ifc_qpc_bits qpc; 4044 4045 u8 reserved_at_800[0x80]; 4046 }; 4047 4048 struct mlx5_ifc_set_roce_address_out_bits { 4049 u8 status[0x8]; 4050 u8 reserved_at_8[0x18]; 4051 4052 u8 syndrome[0x20]; 4053 4054 u8 reserved_at_40[0x40]; 4055 }; 4056 4057 struct mlx5_ifc_set_roce_address_in_bits { 4058 u8 opcode[0x10]; 4059 u8 reserved_at_10[0x10]; 4060 4061 u8 reserved_at_20[0x10]; 4062 u8 op_mod[0x10]; 4063 4064 u8 roce_address_index[0x10]; 4065 u8 reserved_at_50[0xc]; 4066 u8 vhca_port_num[0x4]; 4067 4068 u8 reserved_at_60[0x20]; 4069 4070 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4071 }; 4072 4073 struct mlx5_ifc_set_mad_demux_out_bits { 4074 u8 status[0x8]; 4075 u8 reserved_at_8[0x18]; 4076 4077 u8 syndrome[0x20]; 4078 4079 u8 reserved_at_40[0x40]; 4080 }; 4081 4082 enum { 4083 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4084 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4085 }; 4086 4087 struct mlx5_ifc_set_mad_demux_in_bits { 4088 u8 opcode[0x10]; 4089 u8 reserved_at_10[0x10]; 4090 4091 u8 reserved_at_20[0x10]; 4092 u8 op_mod[0x10]; 4093 4094 u8 reserved_at_40[0x20]; 4095 4096 u8 reserved_at_60[0x6]; 4097 u8 demux_mode[0x2]; 4098 u8 reserved_at_68[0x18]; 4099 }; 4100 4101 struct mlx5_ifc_set_l2_table_entry_out_bits { 4102 u8 status[0x8]; 4103 u8 reserved_at_8[0x18]; 4104 4105 u8 syndrome[0x20]; 4106 4107 u8 reserved_at_40[0x40]; 4108 }; 4109 4110 struct mlx5_ifc_set_l2_table_entry_in_bits { 4111 u8 opcode[0x10]; 4112 u8 reserved_at_10[0x10]; 4113 4114 u8 reserved_at_20[0x10]; 4115 u8 op_mod[0x10]; 4116 4117 u8 reserved_at_40[0x60]; 4118 4119 u8 reserved_at_a0[0x8]; 4120 u8 table_index[0x18]; 4121 4122 u8 reserved_at_c0[0x20]; 4123 4124 u8 reserved_at_e0[0x13]; 4125 u8 vlan_valid[0x1]; 4126 u8 vlan[0xc]; 4127 4128 struct mlx5_ifc_mac_address_layout_bits mac_address; 4129 4130 u8 reserved_at_140[0xc0]; 4131 }; 4132 4133 struct mlx5_ifc_set_issi_out_bits { 4134 u8 status[0x8]; 4135 u8 reserved_at_8[0x18]; 4136 4137 u8 syndrome[0x20]; 4138 4139 u8 reserved_at_40[0x40]; 4140 }; 4141 4142 struct mlx5_ifc_set_issi_in_bits { 4143 u8 opcode[0x10]; 4144 u8 reserved_at_10[0x10]; 4145 4146 u8 reserved_at_20[0x10]; 4147 u8 op_mod[0x10]; 4148 4149 u8 reserved_at_40[0x10]; 4150 u8 current_issi[0x10]; 4151 4152 u8 reserved_at_60[0x20]; 4153 }; 4154 4155 struct mlx5_ifc_set_hca_cap_out_bits { 4156 u8 status[0x8]; 4157 u8 reserved_at_8[0x18]; 4158 4159 u8 syndrome[0x20]; 4160 4161 u8 reserved_at_40[0x40]; 4162 }; 4163 4164 struct mlx5_ifc_set_hca_cap_in_bits { 4165 u8 opcode[0x10]; 4166 u8 reserved_at_10[0x10]; 4167 4168 u8 reserved_at_20[0x10]; 4169 u8 op_mod[0x10]; 4170 4171 u8 reserved_at_40[0x40]; 4172 4173 union mlx5_ifc_hca_cap_union_bits capability; 4174 }; 4175 4176 enum { 4177 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4178 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4179 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4180 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4181 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4182 }; 4183 4184 struct mlx5_ifc_set_fte_out_bits { 4185 u8 status[0x8]; 4186 u8 reserved_at_8[0x18]; 4187 4188 u8 syndrome[0x20]; 4189 4190 u8 reserved_at_40[0x40]; 4191 }; 4192 4193 struct mlx5_ifc_set_fte_in_bits { 4194 u8 opcode[0x10]; 4195 u8 reserved_at_10[0x10]; 4196 4197 u8 reserved_at_20[0x10]; 4198 u8 op_mod[0x10]; 4199 4200 u8 other_vport[0x1]; 4201 u8 reserved_at_41[0xf]; 4202 u8 vport_number[0x10]; 4203 4204 u8 reserved_at_60[0x20]; 4205 4206 u8 table_type[0x8]; 4207 u8 reserved_at_88[0x18]; 4208 4209 u8 reserved_at_a0[0x8]; 4210 u8 table_id[0x18]; 4211 4212 u8 ignore_flow_level[0x1]; 4213 u8 reserved_at_c1[0x17]; 4214 u8 modify_enable_mask[0x8]; 4215 4216 u8 reserved_at_e0[0x20]; 4217 4218 u8 flow_index[0x20]; 4219 4220 u8 reserved_at_120[0xe0]; 4221 4222 struct mlx5_ifc_flow_context_bits flow_context; 4223 }; 4224 4225 struct mlx5_ifc_rts2rts_qp_out_bits { 4226 u8 status[0x8]; 4227 u8 reserved_at_8[0x18]; 4228 4229 u8 syndrome[0x20]; 4230 4231 u8 reserved_at_40[0x20]; 4232 u8 ece[0x20]; 4233 }; 4234 4235 struct mlx5_ifc_rts2rts_qp_in_bits { 4236 u8 opcode[0x10]; 4237 u8 uid[0x10]; 4238 4239 u8 reserved_at_20[0x10]; 4240 u8 op_mod[0x10]; 4241 4242 u8 reserved_at_40[0x8]; 4243 u8 qpn[0x18]; 4244 4245 u8 reserved_at_60[0x20]; 4246 4247 u8 opt_param_mask[0x20]; 4248 4249 u8 ece[0x20]; 4250 4251 struct mlx5_ifc_qpc_bits qpc; 4252 4253 u8 reserved_at_800[0x80]; 4254 }; 4255 4256 struct mlx5_ifc_rtr2rts_qp_out_bits { 4257 u8 status[0x8]; 4258 u8 reserved_at_8[0x18]; 4259 4260 u8 syndrome[0x20]; 4261 4262 u8 reserved_at_40[0x20]; 4263 u8 ece[0x20]; 4264 }; 4265 4266 struct mlx5_ifc_rtr2rts_qp_in_bits { 4267 u8 opcode[0x10]; 4268 u8 uid[0x10]; 4269 4270 u8 reserved_at_20[0x10]; 4271 u8 op_mod[0x10]; 4272 4273 u8 reserved_at_40[0x8]; 4274 u8 qpn[0x18]; 4275 4276 u8 reserved_at_60[0x20]; 4277 4278 u8 opt_param_mask[0x20]; 4279 4280 u8 ece[0x20]; 4281 4282 struct mlx5_ifc_qpc_bits qpc; 4283 4284 u8 reserved_at_800[0x80]; 4285 }; 4286 4287 struct mlx5_ifc_rst2init_qp_out_bits { 4288 u8 status[0x8]; 4289 u8 reserved_at_8[0x18]; 4290 4291 u8 syndrome[0x20]; 4292 4293 u8 reserved_at_40[0x20]; 4294 u8 ece[0x20]; 4295 }; 4296 4297 struct mlx5_ifc_rst2init_qp_in_bits { 4298 u8 opcode[0x10]; 4299 u8 uid[0x10]; 4300 4301 u8 reserved_at_20[0x10]; 4302 u8 op_mod[0x10]; 4303 4304 u8 reserved_at_40[0x8]; 4305 u8 qpn[0x18]; 4306 4307 u8 reserved_at_60[0x20]; 4308 4309 u8 opt_param_mask[0x20]; 4310 4311 u8 ece[0x20]; 4312 4313 struct mlx5_ifc_qpc_bits qpc; 4314 4315 u8 reserved_at_800[0x80]; 4316 }; 4317 4318 struct mlx5_ifc_query_xrq_out_bits { 4319 u8 status[0x8]; 4320 u8 reserved_at_8[0x18]; 4321 4322 u8 syndrome[0x20]; 4323 4324 u8 reserved_at_40[0x40]; 4325 4326 struct mlx5_ifc_xrqc_bits xrq_context; 4327 }; 4328 4329 struct mlx5_ifc_query_xrq_in_bits { 4330 u8 opcode[0x10]; 4331 u8 reserved_at_10[0x10]; 4332 4333 u8 reserved_at_20[0x10]; 4334 u8 op_mod[0x10]; 4335 4336 u8 reserved_at_40[0x8]; 4337 u8 xrqn[0x18]; 4338 4339 u8 reserved_at_60[0x20]; 4340 }; 4341 4342 struct mlx5_ifc_query_xrc_srq_out_bits { 4343 u8 status[0x8]; 4344 u8 reserved_at_8[0x18]; 4345 4346 u8 syndrome[0x20]; 4347 4348 u8 reserved_at_40[0x40]; 4349 4350 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4351 4352 u8 reserved_at_280[0x600]; 4353 4354 u8 pas[][0x40]; 4355 }; 4356 4357 struct mlx5_ifc_query_xrc_srq_in_bits { 4358 u8 opcode[0x10]; 4359 u8 reserved_at_10[0x10]; 4360 4361 u8 reserved_at_20[0x10]; 4362 u8 op_mod[0x10]; 4363 4364 u8 reserved_at_40[0x8]; 4365 u8 xrc_srqn[0x18]; 4366 4367 u8 reserved_at_60[0x20]; 4368 }; 4369 4370 enum { 4371 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4372 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4373 }; 4374 4375 struct mlx5_ifc_query_vport_state_out_bits { 4376 u8 status[0x8]; 4377 u8 reserved_at_8[0x18]; 4378 4379 u8 syndrome[0x20]; 4380 4381 u8 reserved_at_40[0x20]; 4382 4383 u8 reserved_at_60[0x18]; 4384 u8 admin_state[0x4]; 4385 u8 state[0x4]; 4386 }; 4387 4388 enum { 4389 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4390 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4391 }; 4392 4393 struct mlx5_ifc_arm_monitor_counter_in_bits { 4394 u8 opcode[0x10]; 4395 u8 uid[0x10]; 4396 4397 u8 reserved_at_20[0x10]; 4398 u8 op_mod[0x10]; 4399 4400 u8 reserved_at_40[0x20]; 4401 4402 u8 reserved_at_60[0x20]; 4403 }; 4404 4405 struct mlx5_ifc_arm_monitor_counter_out_bits { 4406 u8 status[0x8]; 4407 u8 reserved_at_8[0x18]; 4408 4409 u8 syndrome[0x20]; 4410 4411 u8 reserved_at_40[0x40]; 4412 }; 4413 4414 enum { 4415 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4416 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4417 }; 4418 4419 enum mlx5_monitor_counter_ppcnt { 4420 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4421 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4422 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4423 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4424 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4425 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4426 }; 4427 4428 enum { 4429 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4430 }; 4431 4432 struct mlx5_ifc_monitor_counter_output_bits { 4433 u8 reserved_at_0[0x4]; 4434 u8 type[0x4]; 4435 u8 reserved_at_8[0x8]; 4436 u8 counter[0x10]; 4437 4438 u8 counter_group_id[0x20]; 4439 }; 4440 4441 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4442 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4443 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4444 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4445 4446 struct mlx5_ifc_set_monitor_counter_in_bits { 4447 u8 opcode[0x10]; 4448 u8 uid[0x10]; 4449 4450 u8 reserved_at_20[0x10]; 4451 u8 op_mod[0x10]; 4452 4453 u8 reserved_at_40[0x10]; 4454 u8 num_of_counters[0x10]; 4455 4456 u8 reserved_at_60[0x20]; 4457 4458 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4459 }; 4460 4461 struct mlx5_ifc_set_monitor_counter_out_bits { 4462 u8 status[0x8]; 4463 u8 reserved_at_8[0x18]; 4464 4465 u8 syndrome[0x20]; 4466 4467 u8 reserved_at_40[0x40]; 4468 }; 4469 4470 struct mlx5_ifc_query_vport_state_in_bits { 4471 u8 opcode[0x10]; 4472 u8 reserved_at_10[0x10]; 4473 4474 u8 reserved_at_20[0x10]; 4475 u8 op_mod[0x10]; 4476 4477 u8 other_vport[0x1]; 4478 u8 reserved_at_41[0xf]; 4479 u8 vport_number[0x10]; 4480 4481 u8 reserved_at_60[0x20]; 4482 }; 4483 4484 struct mlx5_ifc_query_vnic_env_out_bits { 4485 u8 status[0x8]; 4486 u8 reserved_at_8[0x18]; 4487 4488 u8 syndrome[0x20]; 4489 4490 u8 reserved_at_40[0x40]; 4491 4492 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4493 }; 4494 4495 enum { 4496 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4497 }; 4498 4499 struct mlx5_ifc_query_vnic_env_in_bits { 4500 u8 opcode[0x10]; 4501 u8 reserved_at_10[0x10]; 4502 4503 u8 reserved_at_20[0x10]; 4504 u8 op_mod[0x10]; 4505 4506 u8 other_vport[0x1]; 4507 u8 reserved_at_41[0xf]; 4508 u8 vport_number[0x10]; 4509 4510 u8 reserved_at_60[0x20]; 4511 }; 4512 4513 struct mlx5_ifc_query_vport_counter_out_bits { 4514 u8 status[0x8]; 4515 u8 reserved_at_8[0x18]; 4516 4517 u8 syndrome[0x20]; 4518 4519 u8 reserved_at_40[0x40]; 4520 4521 struct mlx5_ifc_traffic_counter_bits received_errors; 4522 4523 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4524 4525 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4526 4527 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4528 4529 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4530 4531 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4532 4533 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4534 4535 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4536 4537 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4538 4539 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4540 4541 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4542 4543 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4544 4545 u8 reserved_at_680[0xa00]; 4546 }; 4547 4548 enum { 4549 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4550 }; 4551 4552 struct mlx5_ifc_query_vport_counter_in_bits { 4553 u8 opcode[0x10]; 4554 u8 reserved_at_10[0x10]; 4555 4556 u8 reserved_at_20[0x10]; 4557 u8 op_mod[0x10]; 4558 4559 u8 other_vport[0x1]; 4560 u8 reserved_at_41[0xb]; 4561 u8 port_num[0x4]; 4562 u8 vport_number[0x10]; 4563 4564 u8 reserved_at_60[0x60]; 4565 4566 u8 clear[0x1]; 4567 u8 reserved_at_c1[0x1f]; 4568 4569 u8 reserved_at_e0[0x20]; 4570 }; 4571 4572 struct mlx5_ifc_query_tis_out_bits { 4573 u8 status[0x8]; 4574 u8 reserved_at_8[0x18]; 4575 4576 u8 syndrome[0x20]; 4577 4578 u8 reserved_at_40[0x40]; 4579 4580 struct mlx5_ifc_tisc_bits tis_context; 4581 }; 4582 4583 struct mlx5_ifc_query_tis_in_bits { 4584 u8 opcode[0x10]; 4585 u8 reserved_at_10[0x10]; 4586 4587 u8 reserved_at_20[0x10]; 4588 u8 op_mod[0x10]; 4589 4590 u8 reserved_at_40[0x8]; 4591 u8 tisn[0x18]; 4592 4593 u8 reserved_at_60[0x20]; 4594 }; 4595 4596 struct mlx5_ifc_query_tir_out_bits { 4597 u8 status[0x8]; 4598 u8 reserved_at_8[0x18]; 4599 4600 u8 syndrome[0x20]; 4601 4602 u8 reserved_at_40[0xc0]; 4603 4604 struct mlx5_ifc_tirc_bits tir_context; 4605 }; 4606 4607 struct mlx5_ifc_query_tir_in_bits { 4608 u8 opcode[0x10]; 4609 u8 reserved_at_10[0x10]; 4610 4611 u8 reserved_at_20[0x10]; 4612 u8 op_mod[0x10]; 4613 4614 u8 reserved_at_40[0x8]; 4615 u8 tirn[0x18]; 4616 4617 u8 reserved_at_60[0x20]; 4618 }; 4619 4620 struct mlx5_ifc_query_srq_out_bits { 4621 u8 status[0x8]; 4622 u8 reserved_at_8[0x18]; 4623 4624 u8 syndrome[0x20]; 4625 4626 u8 reserved_at_40[0x40]; 4627 4628 struct mlx5_ifc_srqc_bits srq_context_entry; 4629 4630 u8 reserved_at_280[0x600]; 4631 4632 u8 pas[][0x40]; 4633 }; 4634 4635 struct mlx5_ifc_query_srq_in_bits { 4636 u8 opcode[0x10]; 4637 u8 reserved_at_10[0x10]; 4638 4639 u8 reserved_at_20[0x10]; 4640 u8 op_mod[0x10]; 4641 4642 u8 reserved_at_40[0x8]; 4643 u8 srqn[0x18]; 4644 4645 u8 reserved_at_60[0x20]; 4646 }; 4647 4648 struct mlx5_ifc_query_sq_out_bits { 4649 u8 status[0x8]; 4650 u8 reserved_at_8[0x18]; 4651 4652 u8 syndrome[0x20]; 4653 4654 u8 reserved_at_40[0xc0]; 4655 4656 struct mlx5_ifc_sqc_bits sq_context; 4657 }; 4658 4659 struct mlx5_ifc_query_sq_in_bits { 4660 u8 opcode[0x10]; 4661 u8 reserved_at_10[0x10]; 4662 4663 u8 reserved_at_20[0x10]; 4664 u8 op_mod[0x10]; 4665 4666 u8 reserved_at_40[0x8]; 4667 u8 sqn[0x18]; 4668 4669 u8 reserved_at_60[0x20]; 4670 }; 4671 4672 struct mlx5_ifc_query_special_contexts_out_bits { 4673 u8 status[0x8]; 4674 u8 reserved_at_8[0x18]; 4675 4676 u8 syndrome[0x20]; 4677 4678 u8 dump_fill_mkey[0x20]; 4679 4680 u8 resd_lkey[0x20]; 4681 4682 u8 null_mkey[0x20]; 4683 4684 u8 reserved_at_a0[0x60]; 4685 }; 4686 4687 struct mlx5_ifc_query_special_contexts_in_bits { 4688 u8 opcode[0x10]; 4689 u8 reserved_at_10[0x10]; 4690 4691 u8 reserved_at_20[0x10]; 4692 u8 op_mod[0x10]; 4693 4694 u8 reserved_at_40[0x40]; 4695 }; 4696 4697 struct mlx5_ifc_query_scheduling_element_out_bits { 4698 u8 opcode[0x10]; 4699 u8 reserved_at_10[0x10]; 4700 4701 u8 reserved_at_20[0x10]; 4702 u8 op_mod[0x10]; 4703 4704 u8 reserved_at_40[0xc0]; 4705 4706 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4707 4708 u8 reserved_at_300[0x100]; 4709 }; 4710 4711 enum { 4712 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4713 }; 4714 4715 struct mlx5_ifc_query_scheduling_element_in_bits { 4716 u8 opcode[0x10]; 4717 u8 reserved_at_10[0x10]; 4718 4719 u8 reserved_at_20[0x10]; 4720 u8 op_mod[0x10]; 4721 4722 u8 scheduling_hierarchy[0x8]; 4723 u8 reserved_at_48[0x18]; 4724 4725 u8 scheduling_element_id[0x20]; 4726 4727 u8 reserved_at_80[0x180]; 4728 }; 4729 4730 struct mlx5_ifc_query_rqt_out_bits { 4731 u8 status[0x8]; 4732 u8 reserved_at_8[0x18]; 4733 4734 u8 syndrome[0x20]; 4735 4736 u8 reserved_at_40[0xc0]; 4737 4738 struct mlx5_ifc_rqtc_bits rqt_context; 4739 }; 4740 4741 struct mlx5_ifc_query_rqt_in_bits { 4742 u8 opcode[0x10]; 4743 u8 reserved_at_10[0x10]; 4744 4745 u8 reserved_at_20[0x10]; 4746 u8 op_mod[0x10]; 4747 4748 u8 reserved_at_40[0x8]; 4749 u8 rqtn[0x18]; 4750 4751 u8 reserved_at_60[0x20]; 4752 }; 4753 4754 struct mlx5_ifc_query_rq_out_bits { 4755 u8 status[0x8]; 4756 u8 reserved_at_8[0x18]; 4757 4758 u8 syndrome[0x20]; 4759 4760 u8 reserved_at_40[0xc0]; 4761 4762 struct mlx5_ifc_rqc_bits rq_context; 4763 }; 4764 4765 struct mlx5_ifc_query_rq_in_bits { 4766 u8 opcode[0x10]; 4767 u8 reserved_at_10[0x10]; 4768 4769 u8 reserved_at_20[0x10]; 4770 u8 op_mod[0x10]; 4771 4772 u8 reserved_at_40[0x8]; 4773 u8 rqn[0x18]; 4774 4775 u8 reserved_at_60[0x20]; 4776 }; 4777 4778 struct mlx5_ifc_query_roce_address_out_bits { 4779 u8 status[0x8]; 4780 u8 reserved_at_8[0x18]; 4781 4782 u8 syndrome[0x20]; 4783 4784 u8 reserved_at_40[0x40]; 4785 4786 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4787 }; 4788 4789 struct mlx5_ifc_query_roce_address_in_bits { 4790 u8 opcode[0x10]; 4791 u8 reserved_at_10[0x10]; 4792 4793 u8 reserved_at_20[0x10]; 4794 u8 op_mod[0x10]; 4795 4796 u8 roce_address_index[0x10]; 4797 u8 reserved_at_50[0xc]; 4798 u8 vhca_port_num[0x4]; 4799 4800 u8 reserved_at_60[0x20]; 4801 }; 4802 4803 struct mlx5_ifc_query_rmp_out_bits { 4804 u8 status[0x8]; 4805 u8 reserved_at_8[0x18]; 4806 4807 u8 syndrome[0x20]; 4808 4809 u8 reserved_at_40[0xc0]; 4810 4811 struct mlx5_ifc_rmpc_bits rmp_context; 4812 }; 4813 4814 struct mlx5_ifc_query_rmp_in_bits { 4815 u8 opcode[0x10]; 4816 u8 reserved_at_10[0x10]; 4817 4818 u8 reserved_at_20[0x10]; 4819 u8 op_mod[0x10]; 4820 4821 u8 reserved_at_40[0x8]; 4822 u8 rmpn[0x18]; 4823 4824 u8 reserved_at_60[0x20]; 4825 }; 4826 4827 struct mlx5_ifc_query_qp_out_bits { 4828 u8 status[0x8]; 4829 u8 reserved_at_8[0x18]; 4830 4831 u8 syndrome[0x20]; 4832 4833 u8 reserved_at_40[0x20]; 4834 u8 ece[0x20]; 4835 4836 u8 opt_param_mask[0x20]; 4837 4838 u8 reserved_at_a0[0x20]; 4839 4840 struct mlx5_ifc_qpc_bits qpc; 4841 4842 u8 reserved_at_800[0x80]; 4843 4844 u8 pas[][0x40]; 4845 }; 4846 4847 struct mlx5_ifc_query_qp_in_bits { 4848 u8 opcode[0x10]; 4849 u8 reserved_at_10[0x10]; 4850 4851 u8 reserved_at_20[0x10]; 4852 u8 op_mod[0x10]; 4853 4854 u8 reserved_at_40[0x8]; 4855 u8 qpn[0x18]; 4856 4857 u8 reserved_at_60[0x20]; 4858 }; 4859 4860 struct mlx5_ifc_query_q_counter_out_bits { 4861 u8 status[0x8]; 4862 u8 reserved_at_8[0x18]; 4863 4864 u8 syndrome[0x20]; 4865 4866 u8 reserved_at_40[0x40]; 4867 4868 u8 rx_write_requests[0x20]; 4869 4870 u8 reserved_at_a0[0x20]; 4871 4872 u8 rx_read_requests[0x20]; 4873 4874 u8 reserved_at_e0[0x20]; 4875 4876 u8 rx_atomic_requests[0x20]; 4877 4878 u8 reserved_at_120[0x20]; 4879 4880 u8 rx_dct_connect[0x20]; 4881 4882 u8 reserved_at_160[0x20]; 4883 4884 u8 out_of_buffer[0x20]; 4885 4886 u8 reserved_at_1a0[0x20]; 4887 4888 u8 out_of_sequence[0x20]; 4889 4890 u8 reserved_at_1e0[0x20]; 4891 4892 u8 duplicate_request[0x20]; 4893 4894 u8 reserved_at_220[0x20]; 4895 4896 u8 rnr_nak_retry_err[0x20]; 4897 4898 u8 reserved_at_260[0x20]; 4899 4900 u8 packet_seq_err[0x20]; 4901 4902 u8 reserved_at_2a0[0x20]; 4903 4904 u8 implied_nak_seq_err[0x20]; 4905 4906 u8 reserved_at_2e0[0x20]; 4907 4908 u8 local_ack_timeout_err[0x20]; 4909 4910 u8 reserved_at_320[0xa0]; 4911 4912 u8 resp_local_length_error[0x20]; 4913 4914 u8 req_local_length_error[0x20]; 4915 4916 u8 resp_local_qp_error[0x20]; 4917 4918 u8 local_operation_error[0x20]; 4919 4920 u8 resp_local_protection[0x20]; 4921 4922 u8 req_local_protection[0x20]; 4923 4924 u8 resp_cqe_error[0x20]; 4925 4926 u8 req_cqe_error[0x20]; 4927 4928 u8 req_mw_binding[0x20]; 4929 4930 u8 req_bad_response[0x20]; 4931 4932 u8 req_remote_invalid_request[0x20]; 4933 4934 u8 resp_remote_invalid_request[0x20]; 4935 4936 u8 req_remote_access_errors[0x20]; 4937 4938 u8 resp_remote_access_errors[0x20]; 4939 4940 u8 req_remote_operation_errors[0x20]; 4941 4942 u8 req_transport_retries_exceeded[0x20]; 4943 4944 u8 cq_overflow[0x20]; 4945 4946 u8 resp_cqe_flush_error[0x20]; 4947 4948 u8 req_cqe_flush_error[0x20]; 4949 4950 u8 reserved_at_620[0x20]; 4951 4952 u8 roce_adp_retrans[0x20]; 4953 4954 u8 roce_adp_retrans_to[0x20]; 4955 4956 u8 roce_slow_restart[0x20]; 4957 4958 u8 roce_slow_restart_cnps[0x20]; 4959 4960 u8 roce_slow_restart_trans[0x20]; 4961 4962 u8 reserved_at_6e0[0x120]; 4963 }; 4964 4965 struct mlx5_ifc_query_q_counter_in_bits { 4966 u8 opcode[0x10]; 4967 u8 reserved_at_10[0x10]; 4968 4969 u8 reserved_at_20[0x10]; 4970 u8 op_mod[0x10]; 4971 4972 u8 reserved_at_40[0x80]; 4973 4974 u8 clear[0x1]; 4975 u8 reserved_at_c1[0x1f]; 4976 4977 u8 reserved_at_e0[0x18]; 4978 u8 counter_set_id[0x8]; 4979 }; 4980 4981 struct mlx5_ifc_query_pages_out_bits { 4982 u8 status[0x8]; 4983 u8 reserved_at_8[0x18]; 4984 4985 u8 syndrome[0x20]; 4986 4987 u8 embedded_cpu_function[0x1]; 4988 u8 reserved_at_41[0xf]; 4989 u8 function_id[0x10]; 4990 4991 u8 num_pages[0x20]; 4992 }; 4993 4994 enum { 4995 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4996 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4997 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4998 }; 4999 5000 struct mlx5_ifc_query_pages_in_bits { 5001 u8 opcode[0x10]; 5002 u8 reserved_at_10[0x10]; 5003 5004 u8 reserved_at_20[0x10]; 5005 u8 op_mod[0x10]; 5006 5007 u8 embedded_cpu_function[0x1]; 5008 u8 reserved_at_41[0xf]; 5009 u8 function_id[0x10]; 5010 5011 u8 reserved_at_60[0x20]; 5012 }; 5013 5014 struct mlx5_ifc_query_nic_vport_context_out_bits { 5015 u8 status[0x8]; 5016 u8 reserved_at_8[0x18]; 5017 5018 u8 syndrome[0x20]; 5019 5020 u8 reserved_at_40[0x40]; 5021 5022 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5023 }; 5024 5025 struct mlx5_ifc_query_nic_vport_context_in_bits { 5026 u8 opcode[0x10]; 5027 u8 reserved_at_10[0x10]; 5028 5029 u8 reserved_at_20[0x10]; 5030 u8 op_mod[0x10]; 5031 5032 u8 other_vport[0x1]; 5033 u8 reserved_at_41[0xf]; 5034 u8 vport_number[0x10]; 5035 5036 u8 reserved_at_60[0x5]; 5037 u8 allowed_list_type[0x3]; 5038 u8 reserved_at_68[0x18]; 5039 }; 5040 5041 struct mlx5_ifc_query_mkey_out_bits { 5042 u8 status[0x8]; 5043 u8 reserved_at_8[0x18]; 5044 5045 u8 syndrome[0x20]; 5046 5047 u8 reserved_at_40[0x40]; 5048 5049 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5050 5051 u8 reserved_at_280[0x600]; 5052 5053 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5054 5055 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5056 }; 5057 5058 struct mlx5_ifc_query_mkey_in_bits { 5059 u8 opcode[0x10]; 5060 u8 reserved_at_10[0x10]; 5061 5062 u8 reserved_at_20[0x10]; 5063 u8 op_mod[0x10]; 5064 5065 u8 reserved_at_40[0x8]; 5066 u8 mkey_index[0x18]; 5067 5068 u8 pg_access[0x1]; 5069 u8 reserved_at_61[0x1f]; 5070 }; 5071 5072 struct mlx5_ifc_query_mad_demux_out_bits { 5073 u8 status[0x8]; 5074 u8 reserved_at_8[0x18]; 5075 5076 u8 syndrome[0x20]; 5077 5078 u8 reserved_at_40[0x40]; 5079 5080 u8 mad_dumux_parameters_block[0x20]; 5081 }; 5082 5083 struct mlx5_ifc_query_mad_demux_in_bits { 5084 u8 opcode[0x10]; 5085 u8 reserved_at_10[0x10]; 5086 5087 u8 reserved_at_20[0x10]; 5088 u8 op_mod[0x10]; 5089 5090 u8 reserved_at_40[0x40]; 5091 }; 5092 5093 struct mlx5_ifc_query_l2_table_entry_out_bits { 5094 u8 status[0x8]; 5095 u8 reserved_at_8[0x18]; 5096 5097 u8 syndrome[0x20]; 5098 5099 u8 reserved_at_40[0xa0]; 5100 5101 u8 reserved_at_e0[0x13]; 5102 u8 vlan_valid[0x1]; 5103 u8 vlan[0xc]; 5104 5105 struct mlx5_ifc_mac_address_layout_bits mac_address; 5106 5107 u8 reserved_at_140[0xc0]; 5108 }; 5109 5110 struct mlx5_ifc_query_l2_table_entry_in_bits { 5111 u8 opcode[0x10]; 5112 u8 reserved_at_10[0x10]; 5113 5114 u8 reserved_at_20[0x10]; 5115 u8 op_mod[0x10]; 5116 5117 u8 reserved_at_40[0x60]; 5118 5119 u8 reserved_at_a0[0x8]; 5120 u8 table_index[0x18]; 5121 5122 u8 reserved_at_c0[0x140]; 5123 }; 5124 5125 struct mlx5_ifc_query_issi_out_bits { 5126 u8 status[0x8]; 5127 u8 reserved_at_8[0x18]; 5128 5129 u8 syndrome[0x20]; 5130 5131 u8 reserved_at_40[0x10]; 5132 u8 current_issi[0x10]; 5133 5134 u8 reserved_at_60[0xa0]; 5135 5136 u8 reserved_at_100[76][0x8]; 5137 u8 supported_issi_dw0[0x20]; 5138 }; 5139 5140 struct mlx5_ifc_query_issi_in_bits { 5141 u8 opcode[0x10]; 5142 u8 reserved_at_10[0x10]; 5143 5144 u8 reserved_at_20[0x10]; 5145 u8 op_mod[0x10]; 5146 5147 u8 reserved_at_40[0x40]; 5148 }; 5149 5150 struct mlx5_ifc_set_driver_version_out_bits { 5151 u8 status[0x8]; 5152 u8 reserved_0[0x18]; 5153 5154 u8 syndrome[0x20]; 5155 u8 reserved_1[0x40]; 5156 }; 5157 5158 struct mlx5_ifc_set_driver_version_in_bits { 5159 u8 opcode[0x10]; 5160 u8 reserved_0[0x10]; 5161 5162 u8 reserved_1[0x10]; 5163 u8 op_mod[0x10]; 5164 5165 u8 reserved_2[0x40]; 5166 u8 driver_version[64][0x8]; 5167 }; 5168 5169 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5170 u8 status[0x8]; 5171 u8 reserved_at_8[0x18]; 5172 5173 u8 syndrome[0x20]; 5174 5175 u8 reserved_at_40[0x40]; 5176 5177 struct mlx5_ifc_pkey_bits pkey[]; 5178 }; 5179 5180 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5181 u8 opcode[0x10]; 5182 u8 reserved_at_10[0x10]; 5183 5184 u8 reserved_at_20[0x10]; 5185 u8 op_mod[0x10]; 5186 5187 u8 other_vport[0x1]; 5188 u8 reserved_at_41[0xb]; 5189 u8 port_num[0x4]; 5190 u8 vport_number[0x10]; 5191 5192 u8 reserved_at_60[0x10]; 5193 u8 pkey_index[0x10]; 5194 }; 5195 5196 enum { 5197 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5198 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5199 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5200 }; 5201 5202 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5203 u8 status[0x8]; 5204 u8 reserved_at_8[0x18]; 5205 5206 u8 syndrome[0x20]; 5207 5208 u8 reserved_at_40[0x20]; 5209 5210 u8 gids_num[0x10]; 5211 u8 reserved_at_70[0x10]; 5212 5213 struct mlx5_ifc_array128_auto_bits gid[]; 5214 }; 5215 5216 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_at_10[0x10]; 5219 5220 u8 reserved_at_20[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 other_vport[0x1]; 5224 u8 reserved_at_41[0xb]; 5225 u8 port_num[0x4]; 5226 u8 vport_number[0x10]; 5227 5228 u8 reserved_at_60[0x10]; 5229 u8 gid_index[0x10]; 5230 }; 5231 5232 struct mlx5_ifc_query_hca_vport_context_out_bits { 5233 u8 status[0x8]; 5234 u8 reserved_at_8[0x18]; 5235 5236 u8 syndrome[0x20]; 5237 5238 u8 reserved_at_40[0x40]; 5239 5240 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5241 }; 5242 5243 struct mlx5_ifc_query_hca_vport_context_in_bits { 5244 u8 opcode[0x10]; 5245 u8 reserved_at_10[0x10]; 5246 5247 u8 reserved_at_20[0x10]; 5248 u8 op_mod[0x10]; 5249 5250 u8 other_vport[0x1]; 5251 u8 reserved_at_41[0xb]; 5252 u8 port_num[0x4]; 5253 u8 vport_number[0x10]; 5254 5255 u8 reserved_at_60[0x20]; 5256 }; 5257 5258 struct mlx5_ifc_query_hca_cap_out_bits { 5259 u8 status[0x8]; 5260 u8 reserved_at_8[0x18]; 5261 5262 u8 syndrome[0x20]; 5263 5264 u8 reserved_at_40[0x40]; 5265 5266 union mlx5_ifc_hca_cap_union_bits capability; 5267 }; 5268 5269 struct mlx5_ifc_query_hca_cap_in_bits { 5270 u8 opcode[0x10]; 5271 u8 reserved_at_10[0x10]; 5272 5273 u8 reserved_at_20[0x10]; 5274 u8 op_mod[0x10]; 5275 5276 u8 other_function[0x1]; 5277 u8 reserved_at_41[0xf]; 5278 u8 function_id[0x10]; 5279 5280 u8 reserved_at_60[0x20]; 5281 }; 5282 5283 struct mlx5_ifc_other_hca_cap_bits { 5284 u8 roce[0x1]; 5285 u8 reserved_at_1[0x27f]; 5286 }; 5287 5288 struct mlx5_ifc_query_other_hca_cap_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_at_8[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 reserved_at_40[0x40]; 5295 5296 struct mlx5_ifc_other_hca_cap_bits other_capability; 5297 }; 5298 5299 struct mlx5_ifc_query_other_hca_cap_in_bits { 5300 u8 opcode[0x10]; 5301 u8 reserved_at_10[0x10]; 5302 5303 u8 reserved_at_20[0x10]; 5304 u8 op_mod[0x10]; 5305 5306 u8 reserved_at_40[0x10]; 5307 u8 function_id[0x10]; 5308 5309 u8 reserved_at_60[0x20]; 5310 }; 5311 5312 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5313 u8 status[0x8]; 5314 u8 reserved_at_8[0x18]; 5315 5316 u8 syndrome[0x20]; 5317 5318 u8 reserved_at_40[0x40]; 5319 }; 5320 5321 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5322 u8 opcode[0x10]; 5323 u8 reserved_at_10[0x10]; 5324 5325 u8 reserved_at_20[0x10]; 5326 u8 op_mod[0x10]; 5327 5328 u8 reserved_at_40[0x10]; 5329 u8 function_id[0x10]; 5330 u8 field_select[0x20]; 5331 5332 struct mlx5_ifc_other_hca_cap_bits other_capability; 5333 }; 5334 5335 struct mlx5_ifc_flow_table_context_bits { 5336 u8 reformat_en[0x1]; 5337 u8 decap_en[0x1]; 5338 u8 sw_owner[0x1]; 5339 u8 termination_table[0x1]; 5340 u8 table_miss_action[0x4]; 5341 u8 level[0x8]; 5342 u8 reserved_at_10[0x8]; 5343 u8 log_size[0x8]; 5344 5345 u8 reserved_at_20[0x8]; 5346 u8 table_miss_id[0x18]; 5347 5348 u8 reserved_at_40[0x8]; 5349 u8 lag_master_next_table_id[0x18]; 5350 5351 u8 reserved_at_60[0x60]; 5352 5353 u8 sw_owner_icm_root_1[0x40]; 5354 5355 u8 sw_owner_icm_root_0[0x40]; 5356 5357 }; 5358 5359 struct mlx5_ifc_query_flow_table_out_bits { 5360 u8 status[0x8]; 5361 u8 reserved_at_8[0x18]; 5362 5363 u8 syndrome[0x20]; 5364 5365 u8 reserved_at_40[0x80]; 5366 5367 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5368 }; 5369 5370 struct mlx5_ifc_query_flow_table_in_bits { 5371 u8 opcode[0x10]; 5372 u8 reserved_at_10[0x10]; 5373 5374 u8 reserved_at_20[0x10]; 5375 u8 op_mod[0x10]; 5376 5377 u8 reserved_at_40[0x40]; 5378 5379 u8 table_type[0x8]; 5380 u8 reserved_at_88[0x18]; 5381 5382 u8 reserved_at_a0[0x8]; 5383 u8 table_id[0x18]; 5384 5385 u8 reserved_at_c0[0x140]; 5386 }; 5387 5388 struct mlx5_ifc_query_fte_out_bits { 5389 u8 status[0x8]; 5390 u8 reserved_at_8[0x18]; 5391 5392 u8 syndrome[0x20]; 5393 5394 u8 reserved_at_40[0x1c0]; 5395 5396 struct mlx5_ifc_flow_context_bits flow_context; 5397 }; 5398 5399 struct mlx5_ifc_query_fte_in_bits { 5400 u8 opcode[0x10]; 5401 u8 reserved_at_10[0x10]; 5402 5403 u8 reserved_at_20[0x10]; 5404 u8 op_mod[0x10]; 5405 5406 u8 reserved_at_40[0x40]; 5407 5408 u8 table_type[0x8]; 5409 u8 reserved_at_88[0x18]; 5410 5411 u8 reserved_at_a0[0x8]; 5412 u8 table_id[0x18]; 5413 5414 u8 reserved_at_c0[0x40]; 5415 5416 u8 flow_index[0x20]; 5417 5418 u8 reserved_at_120[0xe0]; 5419 }; 5420 5421 enum { 5422 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5423 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5424 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5425 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5426 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5427 }; 5428 5429 struct mlx5_ifc_query_flow_group_out_bits { 5430 u8 status[0x8]; 5431 u8 reserved_at_8[0x18]; 5432 5433 u8 syndrome[0x20]; 5434 5435 u8 reserved_at_40[0xa0]; 5436 5437 u8 start_flow_index[0x20]; 5438 5439 u8 reserved_at_100[0x20]; 5440 5441 u8 end_flow_index[0x20]; 5442 5443 u8 reserved_at_140[0xa0]; 5444 5445 u8 reserved_at_1e0[0x18]; 5446 u8 match_criteria_enable[0x8]; 5447 5448 struct mlx5_ifc_fte_match_param_bits match_criteria; 5449 5450 u8 reserved_at_1200[0xe00]; 5451 }; 5452 5453 struct mlx5_ifc_query_flow_group_in_bits { 5454 u8 opcode[0x10]; 5455 u8 reserved_at_10[0x10]; 5456 5457 u8 reserved_at_20[0x10]; 5458 u8 op_mod[0x10]; 5459 5460 u8 reserved_at_40[0x40]; 5461 5462 u8 table_type[0x8]; 5463 u8 reserved_at_88[0x18]; 5464 5465 u8 reserved_at_a0[0x8]; 5466 u8 table_id[0x18]; 5467 5468 u8 group_id[0x20]; 5469 5470 u8 reserved_at_e0[0x120]; 5471 }; 5472 5473 struct mlx5_ifc_query_flow_counter_out_bits { 5474 u8 status[0x8]; 5475 u8 reserved_at_8[0x18]; 5476 5477 u8 syndrome[0x20]; 5478 5479 u8 reserved_at_40[0x40]; 5480 5481 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5482 }; 5483 5484 struct mlx5_ifc_query_flow_counter_in_bits { 5485 u8 opcode[0x10]; 5486 u8 reserved_at_10[0x10]; 5487 5488 u8 reserved_at_20[0x10]; 5489 u8 op_mod[0x10]; 5490 5491 u8 reserved_at_40[0x80]; 5492 5493 u8 clear[0x1]; 5494 u8 reserved_at_c1[0xf]; 5495 u8 num_of_counters[0x10]; 5496 5497 u8 flow_counter_id[0x20]; 5498 }; 5499 5500 struct mlx5_ifc_query_esw_vport_context_out_bits { 5501 u8 status[0x8]; 5502 u8 reserved_at_8[0x18]; 5503 5504 u8 syndrome[0x20]; 5505 5506 u8 reserved_at_40[0x40]; 5507 5508 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5509 }; 5510 5511 struct mlx5_ifc_query_esw_vport_context_in_bits { 5512 u8 opcode[0x10]; 5513 u8 reserved_at_10[0x10]; 5514 5515 u8 reserved_at_20[0x10]; 5516 u8 op_mod[0x10]; 5517 5518 u8 other_vport[0x1]; 5519 u8 reserved_at_41[0xf]; 5520 u8 vport_number[0x10]; 5521 5522 u8 reserved_at_60[0x20]; 5523 }; 5524 5525 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5526 u8 status[0x8]; 5527 u8 reserved_at_8[0x18]; 5528 5529 u8 syndrome[0x20]; 5530 5531 u8 reserved_at_40[0x40]; 5532 }; 5533 5534 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5535 u8 reserved_at_0[0x1b]; 5536 u8 fdb_to_vport_reg_c_id[0x1]; 5537 u8 vport_cvlan_insert[0x1]; 5538 u8 vport_svlan_insert[0x1]; 5539 u8 vport_cvlan_strip[0x1]; 5540 u8 vport_svlan_strip[0x1]; 5541 }; 5542 5543 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5544 u8 opcode[0x10]; 5545 u8 reserved_at_10[0x10]; 5546 5547 u8 reserved_at_20[0x10]; 5548 u8 op_mod[0x10]; 5549 5550 u8 other_vport[0x1]; 5551 u8 reserved_at_41[0xf]; 5552 u8 vport_number[0x10]; 5553 5554 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5555 5556 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5557 }; 5558 5559 struct mlx5_ifc_query_eq_out_bits { 5560 u8 status[0x8]; 5561 u8 reserved_at_8[0x18]; 5562 5563 u8 syndrome[0x20]; 5564 5565 u8 reserved_at_40[0x40]; 5566 5567 struct mlx5_ifc_eqc_bits eq_context_entry; 5568 5569 u8 reserved_at_280[0x40]; 5570 5571 u8 event_bitmask[0x40]; 5572 5573 u8 reserved_at_300[0x580]; 5574 5575 u8 pas[][0x40]; 5576 }; 5577 5578 struct mlx5_ifc_query_eq_in_bits { 5579 u8 opcode[0x10]; 5580 u8 reserved_at_10[0x10]; 5581 5582 u8 reserved_at_20[0x10]; 5583 u8 op_mod[0x10]; 5584 5585 u8 reserved_at_40[0x18]; 5586 u8 eq_number[0x8]; 5587 5588 u8 reserved_at_60[0x20]; 5589 }; 5590 5591 struct mlx5_ifc_packet_reformat_context_in_bits { 5592 u8 reserved_at_0[0x5]; 5593 u8 reformat_type[0x3]; 5594 u8 reserved_at_8[0xe]; 5595 u8 reformat_data_size[0xa]; 5596 5597 u8 reserved_at_20[0x10]; 5598 u8 reformat_data[2][0x8]; 5599 5600 u8 more_reformat_data[][0x8]; 5601 }; 5602 5603 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5604 u8 status[0x8]; 5605 u8 reserved_at_8[0x18]; 5606 5607 u8 syndrome[0x20]; 5608 5609 u8 reserved_at_40[0xa0]; 5610 5611 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5612 }; 5613 5614 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5615 u8 opcode[0x10]; 5616 u8 reserved_at_10[0x10]; 5617 5618 u8 reserved_at_20[0x10]; 5619 u8 op_mod[0x10]; 5620 5621 u8 packet_reformat_id[0x20]; 5622 5623 u8 reserved_at_60[0xa0]; 5624 }; 5625 5626 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5627 u8 status[0x8]; 5628 u8 reserved_at_8[0x18]; 5629 5630 u8 syndrome[0x20]; 5631 5632 u8 packet_reformat_id[0x20]; 5633 5634 u8 reserved_at_60[0x20]; 5635 }; 5636 5637 enum mlx5_reformat_ctx_type { 5638 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5639 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5640 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5641 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5642 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5643 }; 5644 5645 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5646 u8 opcode[0x10]; 5647 u8 reserved_at_10[0x10]; 5648 5649 u8 reserved_at_20[0x10]; 5650 u8 op_mod[0x10]; 5651 5652 u8 reserved_at_40[0xa0]; 5653 5654 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5655 }; 5656 5657 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5658 u8 status[0x8]; 5659 u8 reserved_at_8[0x18]; 5660 5661 u8 syndrome[0x20]; 5662 5663 u8 reserved_at_40[0x40]; 5664 }; 5665 5666 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5667 u8 opcode[0x10]; 5668 u8 reserved_at_10[0x10]; 5669 5670 u8 reserved_20[0x10]; 5671 u8 op_mod[0x10]; 5672 5673 u8 packet_reformat_id[0x20]; 5674 5675 u8 reserved_60[0x20]; 5676 }; 5677 5678 struct mlx5_ifc_set_action_in_bits { 5679 u8 action_type[0x4]; 5680 u8 field[0xc]; 5681 u8 reserved_at_10[0x3]; 5682 u8 offset[0x5]; 5683 u8 reserved_at_18[0x3]; 5684 u8 length[0x5]; 5685 5686 u8 data[0x20]; 5687 }; 5688 5689 struct mlx5_ifc_add_action_in_bits { 5690 u8 action_type[0x4]; 5691 u8 field[0xc]; 5692 u8 reserved_at_10[0x10]; 5693 5694 u8 data[0x20]; 5695 }; 5696 5697 struct mlx5_ifc_copy_action_in_bits { 5698 u8 action_type[0x4]; 5699 u8 src_field[0xc]; 5700 u8 reserved_at_10[0x3]; 5701 u8 src_offset[0x5]; 5702 u8 reserved_at_18[0x3]; 5703 u8 length[0x5]; 5704 5705 u8 reserved_at_20[0x4]; 5706 u8 dst_field[0xc]; 5707 u8 reserved_at_30[0x3]; 5708 u8 dst_offset[0x5]; 5709 u8 reserved_at_38[0x8]; 5710 }; 5711 5712 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5713 struct mlx5_ifc_set_action_in_bits set_action_in; 5714 struct mlx5_ifc_add_action_in_bits add_action_in; 5715 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5716 u8 reserved_at_0[0x40]; 5717 }; 5718 5719 enum { 5720 MLX5_ACTION_TYPE_SET = 0x1, 5721 MLX5_ACTION_TYPE_ADD = 0x2, 5722 MLX5_ACTION_TYPE_COPY = 0x3, 5723 }; 5724 5725 enum { 5726 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5727 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5728 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5729 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5730 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5731 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5732 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5733 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5734 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5735 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5736 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5737 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5738 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5739 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5740 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5741 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5742 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5743 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5744 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5745 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5746 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5747 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5748 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5749 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5750 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5751 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5752 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5753 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5754 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5755 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5756 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5757 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5758 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5759 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5760 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5761 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5762 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5763 }; 5764 5765 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5766 u8 status[0x8]; 5767 u8 reserved_at_8[0x18]; 5768 5769 u8 syndrome[0x20]; 5770 5771 u8 modify_header_id[0x20]; 5772 5773 u8 reserved_at_60[0x20]; 5774 }; 5775 5776 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5777 u8 opcode[0x10]; 5778 u8 reserved_at_10[0x10]; 5779 5780 u8 reserved_at_20[0x10]; 5781 u8 op_mod[0x10]; 5782 5783 u8 reserved_at_40[0x20]; 5784 5785 u8 table_type[0x8]; 5786 u8 reserved_at_68[0x10]; 5787 u8 num_of_actions[0x8]; 5788 5789 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0]; 5790 }; 5791 5792 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5793 u8 status[0x8]; 5794 u8 reserved_at_8[0x18]; 5795 5796 u8 syndrome[0x20]; 5797 5798 u8 reserved_at_40[0x40]; 5799 }; 5800 5801 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5802 u8 opcode[0x10]; 5803 u8 reserved_at_10[0x10]; 5804 5805 u8 reserved_at_20[0x10]; 5806 u8 op_mod[0x10]; 5807 5808 u8 modify_header_id[0x20]; 5809 5810 u8 reserved_at_60[0x20]; 5811 }; 5812 5813 struct mlx5_ifc_query_dct_out_bits { 5814 u8 status[0x8]; 5815 u8 reserved_at_8[0x18]; 5816 5817 u8 syndrome[0x20]; 5818 5819 u8 reserved_at_40[0x40]; 5820 5821 struct mlx5_ifc_dctc_bits dct_context_entry; 5822 5823 u8 reserved_at_280[0x180]; 5824 }; 5825 5826 struct mlx5_ifc_query_dct_in_bits { 5827 u8 opcode[0x10]; 5828 u8 reserved_at_10[0x10]; 5829 5830 u8 reserved_at_20[0x10]; 5831 u8 op_mod[0x10]; 5832 5833 u8 reserved_at_40[0x8]; 5834 u8 dctn[0x18]; 5835 5836 u8 reserved_at_60[0x20]; 5837 }; 5838 5839 struct mlx5_ifc_query_cq_out_bits { 5840 u8 status[0x8]; 5841 u8 reserved_at_8[0x18]; 5842 5843 u8 syndrome[0x20]; 5844 5845 u8 reserved_at_40[0x40]; 5846 5847 struct mlx5_ifc_cqc_bits cq_context; 5848 5849 u8 reserved_at_280[0x600]; 5850 5851 u8 pas[][0x40]; 5852 }; 5853 5854 struct mlx5_ifc_query_cq_in_bits { 5855 u8 opcode[0x10]; 5856 u8 reserved_at_10[0x10]; 5857 5858 u8 reserved_at_20[0x10]; 5859 u8 op_mod[0x10]; 5860 5861 u8 reserved_at_40[0x8]; 5862 u8 cqn[0x18]; 5863 5864 u8 reserved_at_60[0x20]; 5865 }; 5866 5867 struct mlx5_ifc_query_cong_status_out_bits { 5868 u8 status[0x8]; 5869 u8 reserved_at_8[0x18]; 5870 5871 u8 syndrome[0x20]; 5872 5873 u8 reserved_at_40[0x20]; 5874 5875 u8 enable[0x1]; 5876 u8 tag_enable[0x1]; 5877 u8 reserved_at_62[0x1e]; 5878 }; 5879 5880 struct mlx5_ifc_query_cong_status_in_bits { 5881 u8 opcode[0x10]; 5882 u8 reserved_at_10[0x10]; 5883 5884 u8 reserved_at_20[0x10]; 5885 u8 op_mod[0x10]; 5886 5887 u8 reserved_at_40[0x18]; 5888 u8 priority[0x4]; 5889 u8 cong_protocol[0x4]; 5890 5891 u8 reserved_at_60[0x20]; 5892 }; 5893 5894 struct mlx5_ifc_query_cong_statistics_out_bits { 5895 u8 status[0x8]; 5896 u8 reserved_at_8[0x18]; 5897 5898 u8 syndrome[0x20]; 5899 5900 u8 reserved_at_40[0x40]; 5901 5902 u8 rp_cur_flows[0x20]; 5903 5904 u8 sum_flows[0x20]; 5905 5906 u8 rp_cnp_ignored_high[0x20]; 5907 5908 u8 rp_cnp_ignored_low[0x20]; 5909 5910 u8 rp_cnp_handled_high[0x20]; 5911 5912 u8 rp_cnp_handled_low[0x20]; 5913 5914 u8 reserved_at_140[0x100]; 5915 5916 u8 time_stamp_high[0x20]; 5917 5918 u8 time_stamp_low[0x20]; 5919 5920 u8 accumulators_period[0x20]; 5921 5922 u8 np_ecn_marked_roce_packets_high[0x20]; 5923 5924 u8 np_ecn_marked_roce_packets_low[0x20]; 5925 5926 u8 np_cnp_sent_high[0x20]; 5927 5928 u8 np_cnp_sent_low[0x20]; 5929 5930 u8 reserved_at_320[0x560]; 5931 }; 5932 5933 struct mlx5_ifc_query_cong_statistics_in_bits { 5934 u8 opcode[0x10]; 5935 u8 reserved_at_10[0x10]; 5936 5937 u8 reserved_at_20[0x10]; 5938 u8 op_mod[0x10]; 5939 5940 u8 clear[0x1]; 5941 u8 reserved_at_41[0x1f]; 5942 5943 u8 reserved_at_60[0x20]; 5944 }; 5945 5946 struct mlx5_ifc_query_cong_params_out_bits { 5947 u8 status[0x8]; 5948 u8 reserved_at_8[0x18]; 5949 5950 u8 syndrome[0x20]; 5951 5952 u8 reserved_at_40[0x40]; 5953 5954 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5955 }; 5956 5957 struct mlx5_ifc_query_cong_params_in_bits { 5958 u8 opcode[0x10]; 5959 u8 reserved_at_10[0x10]; 5960 5961 u8 reserved_at_20[0x10]; 5962 u8 op_mod[0x10]; 5963 5964 u8 reserved_at_40[0x1c]; 5965 u8 cong_protocol[0x4]; 5966 5967 u8 reserved_at_60[0x20]; 5968 }; 5969 5970 struct mlx5_ifc_query_adapter_out_bits { 5971 u8 status[0x8]; 5972 u8 reserved_at_8[0x18]; 5973 5974 u8 syndrome[0x20]; 5975 5976 u8 reserved_at_40[0x40]; 5977 5978 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5979 }; 5980 5981 struct mlx5_ifc_query_adapter_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_at_10[0x10]; 5984 5985 u8 reserved_at_20[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_at_40[0x40]; 5989 }; 5990 5991 struct mlx5_ifc_qp_2rst_out_bits { 5992 u8 status[0x8]; 5993 u8 reserved_at_8[0x18]; 5994 5995 u8 syndrome[0x20]; 5996 5997 u8 reserved_at_40[0x40]; 5998 }; 5999 6000 struct mlx5_ifc_qp_2rst_in_bits { 6001 u8 opcode[0x10]; 6002 u8 uid[0x10]; 6003 6004 u8 reserved_at_20[0x10]; 6005 u8 op_mod[0x10]; 6006 6007 u8 reserved_at_40[0x8]; 6008 u8 qpn[0x18]; 6009 6010 u8 reserved_at_60[0x20]; 6011 }; 6012 6013 struct mlx5_ifc_qp_2err_out_bits { 6014 u8 status[0x8]; 6015 u8 reserved_at_8[0x18]; 6016 6017 u8 syndrome[0x20]; 6018 6019 u8 reserved_at_40[0x40]; 6020 }; 6021 6022 struct mlx5_ifc_qp_2err_in_bits { 6023 u8 opcode[0x10]; 6024 u8 uid[0x10]; 6025 6026 u8 reserved_at_20[0x10]; 6027 u8 op_mod[0x10]; 6028 6029 u8 reserved_at_40[0x8]; 6030 u8 qpn[0x18]; 6031 6032 u8 reserved_at_60[0x20]; 6033 }; 6034 6035 struct mlx5_ifc_page_fault_resume_out_bits { 6036 u8 status[0x8]; 6037 u8 reserved_at_8[0x18]; 6038 6039 u8 syndrome[0x20]; 6040 6041 u8 reserved_at_40[0x40]; 6042 }; 6043 6044 struct mlx5_ifc_page_fault_resume_in_bits { 6045 u8 opcode[0x10]; 6046 u8 reserved_at_10[0x10]; 6047 6048 u8 reserved_at_20[0x10]; 6049 u8 op_mod[0x10]; 6050 6051 u8 error[0x1]; 6052 u8 reserved_at_41[0x4]; 6053 u8 page_fault_type[0x3]; 6054 u8 wq_number[0x18]; 6055 6056 u8 reserved_at_60[0x8]; 6057 u8 token[0x18]; 6058 }; 6059 6060 struct mlx5_ifc_nop_out_bits { 6061 u8 status[0x8]; 6062 u8 reserved_at_8[0x18]; 6063 6064 u8 syndrome[0x20]; 6065 6066 u8 reserved_at_40[0x40]; 6067 }; 6068 6069 struct mlx5_ifc_nop_in_bits { 6070 u8 opcode[0x10]; 6071 u8 reserved_at_10[0x10]; 6072 6073 u8 reserved_at_20[0x10]; 6074 u8 op_mod[0x10]; 6075 6076 u8 reserved_at_40[0x40]; 6077 }; 6078 6079 struct mlx5_ifc_modify_vport_state_out_bits { 6080 u8 status[0x8]; 6081 u8 reserved_at_8[0x18]; 6082 6083 u8 syndrome[0x20]; 6084 6085 u8 reserved_at_40[0x40]; 6086 }; 6087 6088 struct mlx5_ifc_modify_vport_state_in_bits { 6089 u8 opcode[0x10]; 6090 u8 reserved_at_10[0x10]; 6091 6092 u8 reserved_at_20[0x10]; 6093 u8 op_mod[0x10]; 6094 6095 u8 other_vport[0x1]; 6096 u8 reserved_at_41[0xf]; 6097 u8 vport_number[0x10]; 6098 6099 u8 reserved_at_60[0x18]; 6100 u8 admin_state[0x4]; 6101 u8 reserved_at_7c[0x4]; 6102 }; 6103 6104 struct mlx5_ifc_modify_tis_out_bits { 6105 u8 status[0x8]; 6106 u8 reserved_at_8[0x18]; 6107 6108 u8 syndrome[0x20]; 6109 6110 u8 reserved_at_40[0x40]; 6111 }; 6112 6113 struct mlx5_ifc_modify_tis_bitmask_bits { 6114 u8 reserved_at_0[0x20]; 6115 6116 u8 reserved_at_20[0x1d]; 6117 u8 lag_tx_port_affinity[0x1]; 6118 u8 strict_lag_tx_port_affinity[0x1]; 6119 u8 prio[0x1]; 6120 }; 6121 6122 struct mlx5_ifc_modify_tis_in_bits { 6123 u8 opcode[0x10]; 6124 u8 uid[0x10]; 6125 6126 u8 reserved_at_20[0x10]; 6127 u8 op_mod[0x10]; 6128 6129 u8 reserved_at_40[0x8]; 6130 u8 tisn[0x18]; 6131 6132 u8 reserved_at_60[0x20]; 6133 6134 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6135 6136 u8 reserved_at_c0[0x40]; 6137 6138 struct mlx5_ifc_tisc_bits ctx; 6139 }; 6140 6141 struct mlx5_ifc_modify_tir_bitmask_bits { 6142 u8 reserved_at_0[0x20]; 6143 6144 u8 reserved_at_20[0x1b]; 6145 u8 self_lb_en[0x1]; 6146 u8 reserved_at_3c[0x1]; 6147 u8 hash[0x1]; 6148 u8 reserved_at_3e[0x1]; 6149 u8 lro[0x1]; 6150 }; 6151 6152 struct mlx5_ifc_modify_tir_out_bits { 6153 u8 status[0x8]; 6154 u8 reserved_at_8[0x18]; 6155 6156 u8 syndrome[0x20]; 6157 6158 u8 reserved_at_40[0x40]; 6159 }; 6160 6161 struct mlx5_ifc_modify_tir_in_bits { 6162 u8 opcode[0x10]; 6163 u8 uid[0x10]; 6164 6165 u8 reserved_at_20[0x10]; 6166 u8 op_mod[0x10]; 6167 6168 u8 reserved_at_40[0x8]; 6169 u8 tirn[0x18]; 6170 6171 u8 reserved_at_60[0x20]; 6172 6173 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6174 6175 u8 reserved_at_c0[0x40]; 6176 6177 struct mlx5_ifc_tirc_bits ctx; 6178 }; 6179 6180 struct mlx5_ifc_modify_sq_out_bits { 6181 u8 status[0x8]; 6182 u8 reserved_at_8[0x18]; 6183 6184 u8 syndrome[0x20]; 6185 6186 u8 reserved_at_40[0x40]; 6187 }; 6188 6189 struct mlx5_ifc_modify_sq_in_bits { 6190 u8 opcode[0x10]; 6191 u8 uid[0x10]; 6192 6193 u8 reserved_at_20[0x10]; 6194 u8 op_mod[0x10]; 6195 6196 u8 sq_state[0x4]; 6197 u8 reserved_at_44[0x4]; 6198 u8 sqn[0x18]; 6199 6200 u8 reserved_at_60[0x20]; 6201 6202 u8 modify_bitmask[0x40]; 6203 6204 u8 reserved_at_c0[0x40]; 6205 6206 struct mlx5_ifc_sqc_bits ctx; 6207 }; 6208 6209 struct mlx5_ifc_modify_scheduling_element_out_bits { 6210 u8 status[0x8]; 6211 u8 reserved_at_8[0x18]; 6212 6213 u8 syndrome[0x20]; 6214 6215 u8 reserved_at_40[0x1c0]; 6216 }; 6217 6218 enum { 6219 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6220 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6221 }; 6222 6223 struct mlx5_ifc_modify_scheduling_element_in_bits { 6224 u8 opcode[0x10]; 6225 u8 reserved_at_10[0x10]; 6226 6227 u8 reserved_at_20[0x10]; 6228 u8 op_mod[0x10]; 6229 6230 u8 scheduling_hierarchy[0x8]; 6231 u8 reserved_at_48[0x18]; 6232 6233 u8 scheduling_element_id[0x20]; 6234 6235 u8 reserved_at_80[0x20]; 6236 6237 u8 modify_bitmask[0x20]; 6238 6239 u8 reserved_at_c0[0x40]; 6240 6241 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6242 6243 u8 reserved_at_300[0x100]; 6244 }; 6245 6246 struct mlx5_ifc_modify_rqt_out_bits { 6247 u8 status[0x8]; 6248 u8 reserved_at_8[0x18]; 6249 6250 u8 syndrome[0x20]; 6251 6252 u8 reserved_at_40[0x40]; 6253 }; 6254 6255 struct mlx5_ifc_rqt_bitmask_bits { 6256 u8 reserved_at_0[0x20]; 6257 6258 u8 reserved_at_20[0x1f]; 6259 u8 rqn_list[0x1]; 6260 }; 6261 6262 struct mlx5_ifc_modify_rqt_in_bits { 6263 u8 opcode[0x10]; 6264 u8 uid[0x10]; 6265 6266 u8 reserved_at_20[0x10]; 6267 u8 op_mod[0x10]; 6268 6269 u8 reserved_at_40[0x8]; 6270 u8 rqtn[0x18]; 6271 6272 u8 reserved_at_60[0x20]; 6273 6274 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6275 6276 u8 reserved_at_c0[0x40]; 6277 6278 struct mlx5_ifc_rqtc_bits ctx; 6279 }; 6280 6281 struct mlx5_ifc_modify_rq_out_bits { 6282 u8 status[0x8]; 6283 u8 reserved_at_8[0x18]; 6284 6285 u8 syndrome[0x20]; 6286 6287 u8 reserved_at_40[0x40]; 6288 }; 6289 6290 enum { 6291 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6292 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6293 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6294 }; 6295 6296 struct mlx5_ifc_modify_rq_in_bits { 6297 u8 opcode[0x10]; 6298 u8 uid[0x10]; 6299 6300 u8 reserved_at_20[0x10]; 6301 u8 op_mod[0x10]; 6302 6303 u8 rq_state[0x4]; 6304 u8 reserved_at_44[0x4]; 6305 u8 rqn[0x18]; 6306 6307 u8 reserved_at_60[0x20]; 6308 6309 u8 modify_bitmask[0x40]; 6310 6311 u8 reserved_at_c0[0x40]; 6312 6313 struct mlx5_ifc_rqc_bits ctx; 6314 }; 6315 6316 struct mlx5_ifc_modify_rmp_out_bits { 6317 u8 status[0x8]; 6318 u8 reserved_at_8[0x18]; 6319 6320 u8 syndrome[0x20]; 6321 6322 u8 reserved_at_40[0x40]; 6323 }; 6324 6325 struct mlx5_ifc_rmp_bitmask_bits { 6326 u8 reserved_at_0[0x20]; 6327 6328 u8 reserved_at_20[0x1f]; 6329 u8 lwm[0x1]; 6330 }; 6331 6332 struct mlx5_ifc_modify_rmp_in_bits { 6333 u8 opcode[0x10]; 6334 u8 uid[0x10]; 6335 6336 u8 reserved_at_20[0x10]; 6337 u8 op_mod[0x10]; 6338 6339 u8 rmp_state[0x4]; 6340 u8 reserved_at_44[0x4]; 6341 u8 rmpn[0x18]; 6342 6343 u8 reserved_at_60[0x20]; 6344 6345 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6346 6347 u8 reserved_at_c0[0x40]; 6348 6349 struct mlx5_ifc_rmpc_bits ctx; 6350 }; 6351 6352 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6353 u8 status[0x8]; 6354 u8 reserved_at_8[0x18]; 6355 6356 u8 syndrome[0x20]; 6357 6358 u8 reserved_at_40[0x40]; 6359 }; 6360 6361 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6362 u8 reserved_at_0[0x12]; 6363 u8 affiliation[0x1]; 6364 u8 reserved_at_13[0x1]; 6365 u8 disable_uc_local_lb[0x1]; 6366 u8 disable_mc_local_lb[0x1]; 6367 u8 node_guid[0x1]; 6368 u8 port_guid[0x1]; 6369 u8 min_inline[0x1]; 6370 u8 mtu[0x1]; 6371 u8 change_event[0x1]; 6372 u8 promisc[0x1]; 6373 u8 permanent_address[0x1]; 6374 u8 addresses_list[0x1]; 6375 u8 roce_en[0x1]; 6376 u8 reserved_at_1f[0x1]; 6377 }; 6378 6379 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6380 u8 opcode[0x10]; 6381 u8 reserved_at_10[0x10]; 6382 6383 u8 reserved_at_20[0x10]; 6384 u8 op_mod[0x10]; 6385 6386 u8 other_vport[0x1]; 6387 u8 reserved_at_41[0xf]; 6388 u8 vport_number[0x10]; 6389 6390 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6391 6392 u8 reserved_at_80[0x780]; 6393 6394 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6395 }; 6396 6397 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6398 u8 status[0x8]; 6399 u8 reserved_at_8[0x18]; 6400 6401 u8 syndrome[0x20]; 6402 6403 u8 reserved_at_40[0x40]; 6404 }; 6405 6406 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6407 u8 opcode[0x10]; 6408 u8 reserved_at_10[0x10]; 6409 6410 u8 reserved_at_20[0x10]; 6411 u8 op_mod[0x10]; 6412 6413 u8 other_vport[0x1]; 6414 u8 reserved_at_41[0xb]; 6415 u8 port_num[0x4]; 6416 u8 vport_number[0x10]; 6417 6418 u8 reserved_at_60[0x20]; 6419 6420 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6421 }; 6422 6423 struct mlx5_ifc_modify_cq_out_bits { 6424 u8 status[0x8]; 6425 u8 reserved_at_8[0x18]; 6426 6427 u8 syndrome[0x20]; 6428 6429 u8 reserved_at_40[0x40]; 6430 }; 6431 6432 enum { 6433 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6434 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6435 }; 6436 6437 struct mlx5_ifc_modify_cq_in_bits { 6438 u8 opcode[0x10]; 6439 u8 uid[0x10]; 6440 6441 u8 reserved_at_20[0x10]; 6442 u8 op_mod[0x10]; 6443 6444 u8 reserved_at_40[0x8]; 6445 u8 cqn[0x18]; 6446 6447 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6448 6449 struct mlx5_ifc_cqc_bits cq_context; 6450 6451 u8 reserved_at_280[0x60]; 6452 6453 u8 cq_umem_valid[0x1]; 6454 u8 reserved_at_2e1[0x1f]; 6455 6456 u8 reserved_at_300[0x580]; 6457 6458 u8 pas[][0x40]; 6459 }; 6460 6461 struct mlx5_ifc_modify_cong_status_out_bits { 6462 u8 status[0x8]; 6463 u8 reserved_at_8[0x18]; 6464 6465 u8 syndrome[0x20]; 6466 6467 u8 reserved_at_40[0x40]; 6468 }; 6469 6470 struct mlx5_ifc_modify_cong_status_in_bits { 6471 u8 opcode[0x10]; 6472 u8 reserved_at_10[0x10]; 6473 6474 u8 reserved_at_20[0x10]; 6475 u8 op_mod[0x10]; 6476 6477 u8 reserved_at_40[0x18]; 6478 u8 priority[0x4]; 6479 u8 cong_protocol[0x4]; 6480 6481 u8 enable[0x1]; 6482 u8 tag_enable[0x1]; 6483 u8 reserved_at_62[0x1e]; 6484 }; 6485 6486 struct mlx5_ifc_modify_cong_params_out_bits { 6487 u8 status[0x8]; 6488 u8 reserved_at_8[0x18]; 6489 6490 u8 syndrome[0x20]; 6491 6492 u8 reserved_at_40[0x40]; 6493 }; 6494 6495 struct mlx5_ifc_modify_cong_params_in_bits { 6496 u8 opcode[0x10]; 6497 u8 reserved_at_10[0x10]; 6498 6499 u8 reserved_at_20[0x10]; 6500 u8 op_mod[0x10]; 6501 6502 u8 reserved_at_40[0x1c]; 6503 u8 cong_protocol[0x4]; 6504 6505 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6506 6507 u8 reserved_at_80[0x80]; 6508 6509 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6510 }; 6511 6512 struct mlx5_ifc_manage_pages_out_bits { 6513 u8 status[0x8]; 6514 u8 reserved_at_8[0x18]; 6515 6516 u8 syndrome[0x20]; 6517 6518 u8 output_num_entries[0x20]; 6519 6520 u8 reserved_at_60[0x20]; 6521 6522 u8 pas[][0x40]; 6523 }; 6524 6525 enum { 6526 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6527 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6528 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6529 }; 6530 6531 struct mlx5_ifc_manage_pages_in_bits { 6532 u8 opcode[0x10]; 6533 u8 reserved_at_10[0x10]; 6534 6535 u8 reserved_at_20[0x10]; 6536 u8 op_mod[0x10]; 6537 6538 u8 embedded_cpu_function[0x1]; 6539 u8 reserved_at_41[0xf]; 6540 u8 function_id[0x10]; 6541 6542 u8 input_num_entries[0x20]; 6543 6544 u8 pas[][0x40]; 6545 }; 6546 6547 struct mlx5_ifc_mad_ifc_out_bits { 6548 u8 status[0x8]; 6549 u8 reserved_at_8[0x18]; 6550 6551 u8 syndrome[0x20]; 6552 6553 u8 reserved_at_40[0x40]; 6554 6555 u8 response_mad_packet[256][0x8]; 6556 }; 6557 6558 struct mlx5_ifc_mad_ifc_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_at_10[0x10]; 6561 6562 u8 reserved_at_20[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 remote_lid[0x10]; 6566 u8 reserved_at_50[0x8]; 6567 u8 port[0x8]; 6568 6569 u8 reserved_at_60[0x20]; 6570 6571 u8 mad[256][0x8]; 6572 }; 6573 6574 struct mlx5_ifc_init_hca_out_bits { 6575 u8 status[0x8]; 6576 u8 reserved_at_8[0x18]; 6577 6578 u8 syndrome[0x20]; 6579 6580 u8 reserved_at_40[0x40]; 6581 }; 6582 6583 struct mlx5_ifc_init_hca_in_bits { 6584 u8 opcode[0x10]; 6585 u8 reserved_at_10[0x10]; 6586 6587 u8 reserved_at_20[0x10]; 6588 u8 op_mod[0x10]; 6589 6590 u8 reserved_at_40[0x40]; 6591 u8 sw_owner_id[4][0x20]; 6592 }; 6593 6594 struct mlx5_ifc_init2rtr_qp_out_bits { 6595 u8 status[0x8]; 6596 u8 reserved_at_8[0x18]; 6597 6598 u8 syndrome[0x20]; 6599 6600 u8 reserved_at_40[0x20]; 6601 u8 ece[0x20]; 6602 }; 6603 6604 struct mlx5_ifc_init2rtr_qp_in_bits { 6605 u8 opcode[0x10]; 6606 u8 uid[0x10]; 6607 6608 u8 reserved_at_20[0x10]; 6609 u8 op_mod[0x10]; 6610 6611 u8 reserved_at_40[0x8]; 6612 u8 qpn[0x18]; 6613 6614 u8 reserved_at_60[0x20]; 6615 6616 u8 opt_param_mask[0x20]; 6617 6618 u8 ece[0x20]; 6619 6620 struct mlx5_ifc_qpc_bits qpc; 6621 6622 u8 reserved_at_800[0x80]; 6623 }; 6624 6625 struct mlx5_ifc_init2init_qp_out_bits { 6626 u8 status[0x8]; 6627 u8 reserved_at_8[0x18]; 6628 6629 u8 syndrome[0x20]; 6630 6631 u8 reserved_at_40[0x20]; 6632 u8 ece[0x20]; 6633 }; 6634 6635 struct mlx5_ifc_init2init_qp_in_bits { 6636 u8 opcode[0x10]; 6637 u8 uid[0x10]; 6638 6639 u8 reserved_at_20[0x10]; 6640 u8 op_mod[0x10]; 6641 6642 u8 reserved_at_40[0x8]; 6643 u8 qpn[0x18]; 6644 6645 u8 reserved_at_60[0x20]; 6646 6647 u8 opt_param_mask[0x20]; 6648 6649 u8 ece[0x20]; 6650 6651 struct mlx5_ifc_qpc_bits qpc; 6652 6653 u8 reserved_at_800[0x80]; 6654 }; 6655 6656 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6657 u8 status[0x8]; 6658 u8 reserved_at_8[0x18]; 6659 6660 u8 syndrome[0x20]; 6661 6662 u8 reserved_at_40[0x40]; 6663 6664 u8 packet_headers_log[128][0x8]; 6665 6666 u8 packet_syndrome[64][0x8]; 6667 }; 6668 6669 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6670 u8 opcode[0x10]; 6671 u8 reserved_at_10[0x10]; 6672 6673 u8 reserved_at_20[0x10]; 6674 u8 op_mod[0x10]; 6675 6676 u8 reserved_at_40[0x40]; 6677 }; 6678 6679 struct mlx5_ifc_gen_eqe_in_bits { 6680 u8 opcode[0x10]; 6681 u8 reserved_at_10[0x10]; 6682 6683 u8 reserved_at_20[0x10]; 6684 u8 op_mod[0x10]; 6685 6686 u8 reserved_at_40[0x18]; 6687 u8 eq_number[0x8]; 6688 6689 u8 reserved_at_60[0x20]; 6690 6691 u8 eqe[64][0x8]; 6692 }; 6693 6694 struct mlx5_ifc_gen_eq_out_bits { 6695 u8 status[0x8]; 6696 u8 reserved_at_8[0x18]; 6697 6698 u8 syndrome[0x20]; 6699 6700 u8 reserved_at_40[0x40]; 6701 }; 6702 6703 struct mlx5_ifc_enable_hca_out_bits { 6704 u8 status[0x8]; 6705 u8 reserved_at_8[0x18]; 6706 6707 u8 syndrome[0x20]; 6708 6709 u8 reserved_at_40[0x20]; 6710 }; 6711 6712 struct mlx5_ifc_enable_hca_in_bits { 6713 u8 opcode[0x10]; 6714 u8 reserved_at_10[0x10]; 6715 6716 u8 reserved_at_20[0x10]; 6717 u8 op_mod[0x10]; 6718 6719 u8 embedded_cpu_function[0x1]; 6720 u8 reserved_at_41[0xf]; 6721 u8 function_id[0x10]; 6722 6723 u8 reserved_at_60[0x20]; 6724 }; 6725 6726 struct mlx5_ifc_drain_dct_out_bits { 6727 u8 status[0x8]; 6728 u8 reserved_at_8[0x18]; 6729 6730 u8 syndrome[0x20]; 6731 6732 u8 reserved_at_40[0x40]; 6733 }; 6734 6735 struct mlx5_ifc_drain_dct_in_bits { 6736 u8 opcode[0x10]; 6737 u8 uid[0x10]; 6738 6739 u8 reserved_at_20[0x10]; 6740 u8 op_mod[0x10]; 6741 6742 u8 reserved_at_40[0x8]; 6743 u8 dctn[0x18]; 6744 6745 u8 reserved_at_60[0x20]; 6746 }; 6747 6748 struct mlx5_ifc_disable_hca_out_bits { 6749 u8 status[0x8]; 6750 u8 reserved_at_8[0x18]; 6751 6752 u8 syndrome[0x20]; 6753 6754 u8 reserved_at_40[0x20]; 6755 }; 6756 6757 struct mlx5_ifc_disable_hca_in_bits { 6758 u8 opcode[0x10]; 6759 u8 reserved_at_10[0x10]; 6760 6761 u8 reserved_at_20[0x10]; 6762 u8 op_mod[0x10]; 6763 6764 u8 embedded_cpu_function[0x1]; 6765 u8 reserved_at_41[0xf]; 6766 u8 function_id[0x10]; 6767 6768 u8 reserved_at_60[0x20]; 6769 }; 6770 6771 struct mlx5_ifc_detach_from_mcg_out_bits { 6772 u8 status[0x8]; 6773 u8 reserved_at_8[0x18]; 6774 6775 u8 syndrome[0x20]; 6776 6777 u8 reserved_at_40[0x40]; 6778 }; 6779 6780 struct mlx5_ifc_detach_from_mcg_in_bits { 6781 u8 opcode[0x10]; 6782 u8 uid[0x10]; 6783 6784 u8 reserved_at_20[0x10]; 6785 u8 op_mod[0x10]; 6786 6787 u8 reserved_at_40[0x8]; 6788 u8 qpn[0x18]; 6789 6790 u8 reserved_at_60[0x20]; 6791 6792 u8 multicast_gid[16][0x8]; 6793 }; 6794 6795 struct mlx5_ifc_destroy_xrq_out_bits { 6796 u8 status[0x8]; 6797 u8 reserved_at_8[0x18]; 6798 6799 u8 syndrome[0x20]; 6800 6801 u8 reserved_at_40[0x40]; 6802 }; 6803 6804 struct mlx5_ifc_destroy_xrq_in_bits { 6805 u8 opcode[0x10]; 6806 u8 uid[0x10]; 6807 6808 u8 reserved_at_20[0x10]; 6809 u8 op_mod[0x10]; 6810 6811 u8 reserved_at_40[0x8]; 6812 u8 xrqn[0x18]; 6813 6814 u8 reserved_at_60[0x20]; 6815 }; 6816 6817 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6818 u8 status[0x8]; 6819 u8 reserved_at_8[0x18]; 6820 6821 u8 syndrome[0x20]; 6822 6823 u8 reserved_at_40[0x40]; 6824 }; 6825 6826 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6827 u8 opcode[0x10]; 6828 u8 uid[0x10]; 6829 6830 u8 reserved_at_20[0x10]; 6831 u8 op_mod[0x10]; 6832 6833 u8 reserved_at_40[0x8]; 6834 u8 xrc_srqn[0x18]; 6835 6836 u8 reserved_at_60[0x20]; 6837 }; 6838 6839 struct mlx5_ifc_destroy_tis_out_bits { 6840 u8 status[0x8]; 6841 u8 reserved_at_8[0x18]; 6842 6843 u8 syndrome[0x20]; 6844 6845 u8 reserved_at_40[0x40]; 6846 }; 6847 6848 struct mlx5_ifc_destroy_tis_in_bits { 6849 u8 opcode[0x10]; 6850 u8 uid[0x10]; 6851 6852 u8 reserved_at_20[0x10]; 6853 u8 op_mod[0x10]; 6854 6855 u8 reserved_at_40[0x8]; 6856 u8 tisn[0x18]; 6857 6858 u8 reserved_at_60[0x20]; 6859 }; 6860 6861 struct mlx5_ifc_destroy_tir_out_bits { 6862 u8 status[0x8]; 6863 u8 reserved_at_8[0x18]; 6864 6865 u8 syndrome[0x20]; 6866 6867 u8 reserved_at_40[0x40]; 6868 }; 6869 6870 struct mlx5_ifc_destroy_tir_in_bits { 6871 u8 opcode[0x10]; 6872 u8 uid[0x10]; 6873 6874 u8 reserved_at_20[0x10]; 6875 u8 op_mod[0x10]; 6876 6877 u8 reserved_at_40[0x8]; 6878 u8 tirn[0x18]; 6879 6880 u8 reserved_at_60[0x20]; 6881 }; 6882 6883 struct mlx5_ifc_destroy_srq_out_bits { 6884 u8 status[0x8]; 6885 u8 reserved_at_8[0x18]; 6886 6887 u8 syndrome[0x20]; 6888 6889 u8 reserved_at_40[0x40]; 6890 }; 6891 6892 struct mlx5_ifc_destroy_srq_in_bits { 6893 u8 opcode[0x10]; 6894 u8 uid[0x10]; 6895 6896 u8 reserved_at_20[0x10]; 6897 u8 op_mod[0x10]; 6898 6899 u8 reserved_at_40[0x8]; 6900 u8 srqn[0x18]; 6901 6902 u8 reserved_at_60[0x20]; 6903 }; 6904 6905 struct mlx5_ifc_destroy_sq_out_bits { 6906 u8 status[0x8]; 6907 u8 reserved_at_8[0x18]; 6908 6909 u8 syndrome[0x20]; 6910 6911 u8 reserved_at_40[0x40]; 6912 }; 6913 6914 struct mlx5_ifc_destroy_sq_in_bits { 6915 u8 opcode[0x10]; 6916 u8 uid[0x10]; 6917 6918 u8 reserved_at_20[0x10]; 6919 u8 op_mod[0x10]; 6920 6921 u8 reserved_at_40[0x8]; 6922 u8 sqn[0x18]; 6923 6924 u8 reserved_at_60[0x20]; 6925 }; 6926 6927 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6928 u8 status[0x8]; 6929 u8 reserved_at_8[0x18]; 6930 6931 u8 syndrome[0x20]; 6932 6933 u8 reserved_at_40[0x1c0]; 6934 }; 6935 6936 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6937 u8 opcode[0x10]; 6938 u8 reserved_at_10[0x10]; 6939 6940 u8 reserved_at_20[0x10]; 6941 u8 op_mod[0x10]; 6942 6943 u8 scheduling_hierarchy[0x8]; 6944 u8 reserved_at_48[0x18]; 6945 6946 u8 scheduling_element_id[0x20]; 6947 6948 u8 reserved_at_80[0x180]; 6949 }; 6950 6951 struct mlx5_ifc_destroy_rqt_out_bits { 6952 u8 status[0x8]; 6953 u8 reserved_at_8[0x18]; 6954 6955 u8 syndrome[0x20]; 6956 6957 u8 reserved_at_40[0x40]; 6958 }; 6959 6960 struct mlx5_ifc_destroy_rqt_in_bits { 6961 u8 opcode[0x10]; 6962 u8 uid[0x10]; 6963 6964 u8 reserved_at_20[0x10]; 6965 u8 op_mod[0x10]; 6966 6967 u8 reserved_at_40[0x8]; 6968 u8 rqtn[0x18]; 6969 6970 u8 reserved_at_60[0x20]; 6971 }; 6972 6973 struct mlx5_ifc_destroy_rq_out_bits { 6974 u8 status[0x8]; 6975 u8 reserved_at_8[0x18]; 6976 6977 u8 syndrome[0x20]; 6978 6979 u8 reserved_at_40[0x40]; 6980 }; 6981 6982 struct mlx5_ifc_destroy_rq_in_bits { 6983 u8 opcode[0x10]; 6984 u8 uid[0x10]; 6985 6986 u8 reserved_at_20[0x10]; 6987 u8 op_mod[0x10]; 6988 6989 u8 reserved_at_40[0x8]; 6990 u8 rqn[0x18]; 6991 6992 u8 reserved_at_60[0x20]; 6993 }; 6994 6995 struct mlx5_ifc_set_delay_drop_params_in_bits { 6996 u8 opcode[0x10]; 6997 u8 reserved_at_10[0x10]; 6998 6999 u8 reserved_at_20[0x10]; 7000 u8 op_mod[0x10]; 7001 7002 u8 reserved_at_40[0x20]; 7003 7004 u8 reserved_at_60[0x10]; 7005 u8 delay_drop_timeout[0x10]; 7006 }; 7007 7008 struct mlx5_ifc_set_delay_drop_params_out_bits { 7009 u8 status[0x8]; 7010 u8 reserved_at_8[0x18]; 7011 7012 u8 syndrome[0x20]; 7013 7014 u8 reserved_at_40[0x40]; 7015 }; 7016 7017 struct mlx5_ifc_destroy_rmp_out_bits { 7018 u8 status[0x8]; 7019 u8 reserved_at_8[0x18]; 7020 7021 u8 syndrome[0x20]; 7022 7023 u8 reserved_at_40[0x40]; 7024 }; 7025 7026 struct mlx5_ifc_destroy_rmp_in_bits { 7027 u8 opcode[0x10]; 7028 u8 uid[0x10]; 7029 7030 u8 reserved_at_20[0x10]; 7031 u8 op_mod[0x10]; 7032 7033 u8 reserved_at_40[0x8]; 7034 u8 rmpn[0x18]; 7035 7036 u8 reserved_at_60[0x20]; 7037 }; 7038 7039 struct mlx5_ifc_destroy_qp_out_bits { 7040 u8 status[0x8]; 7041 u8 reserved_at_8[0x18]; 7042 7043 u8 syndrome[0x20]; 7044 7045 u8 reserved_at_40[0x40]; 7046 }; 7047 7048 struct mlx5_ifc_destroy_qp_in_bits { 7049 u8 opcode[0x10]; 7050 u8 uid[0x10]; 7051 7052 u8 reserved_at_20[0x10]; 7053 u8 op_mod[0x10]; 7054 7055 u8 reserved_at_40[0x8]; 7056 u8 qpn[0x18]; 7057 7058 u8 reserved_at_60[0x20]; 7059 }; 7060 7061 struct mlx5_ifc_destroy_psv_out_bits { 7062 u8 status[0x8]; 7063 u8 reserved_at_8[0x18]; 7064 7065 u8 syndrome[0x20]; 7066 7067 u8 reserved_at_40[0x40]; 7068 }; 7069 7070 struct mlx5_ifc_destroy_psv_in_bits { 7071 u8 opcode[0x10]; 7072 u8 reserved_at_10[0x10]; 7073 7074 u8 reserved_at_20[0x10]; 7075 u8 op_mod[0x10]; 7076 7077 u8 reserved_at_40[0x8]; 7078 u8 psvn[0x18]; 7079 7080 u8 reserved_at_60[0x20]; 7081 }; 7082 7083 struct mlx5_ifc_destroy_mkey_out_bits { 7084 u8 status[0x8]; 7085 u8 reserved_at_8[0x18]; 7086 7087 u8 syndrome[0x20]; 7088 7089 u8 reserved_at_40[0x40]; 7090 }; 7091 7092 struct mlx5_ifc_destroy_mkey_in_bits { 7093 u8 opcode[0x10]; 7094 u8 reserved_at_10[0x10]; 7095 7096 u8 reserved_at_20[0x10]; 7097 u8 op_mod[0x10]; 7098 7099 u8 reserved_at_40[0x8]; 7100 u8 mkey_index[0x18]; 7101 7102 u8 reserved_at_60[0x20]; 7103 }; 7104 7105 struct mlx5_ifc_destroy_flow_table_out_bits { 7106 u8 status[0x8]; 7107 u8 reserved_at_8[0x18]; 7108 7109 u8 syndrome[0x20]; 7110 7111 u8 reserved_at_40[0x40]; 7112 }; 7113 7114 struct mlx5_ifc_destroy_flow_table_in_bits { 7115 u8 opcode[0x10]; 7116 u8 reserved_at_10[0x10]; 7117 7118 u8 reserved_at_20[0x10]; 7119 u8 op_mod[0x10]; 7120 7121 u8 other_vport[0x1]; 7122 u8 reserved_at_41[0xf]; 7123 u8 vport_number[0x10]; 7124 7125 u8 reserved_at_60[0x20]; 7126 7127 u8 table_type[0x8]; 7128 u8 reserved_at_88[0x18]; 7129 7130 u8 reserved_at_a0[0x8]; 7131 u8 table_id[0x18]; 7132 7133 u8 reserved_at_c0[0x140]; 7134 }; 7135 7136 struct mlx5_ifc_destroy_flow_group_out_bits { 7137 u8 status[0x8]; 7138 u8 reserved_at_8[0x18]; 7139 7140 u8 syndrome[0x20]; 7141 7142 u8 reserved_at_40[0x40]; 7143 }; 7144 7145 struct mlx5_ifc_destroy_flow_group_in_bits { 7146 u8 opcode[0x10]; 7147 u8 reserved_at_10[0x10]; 7148 7149 u8 reserved_at_20[0x10]; 7150 u8 op_mod[0x10]; 7151 7152 u8 other_vport[0x1]; 7153 u8 reserved_at_41[0xf]; 7154 u8 vport_number[0x10]; 7155 7156 u8 reserved_at_60[0x20]; 7157 7158 u8 table_type[0x8]; 7159 u8 reserved_at_88[0x18]; 7160 7161 u8 reserved_at_a0[0x8]; 7162 u8 table_id[0x18]; 7163 7164 u8 group_id[0x20]; 7165 7166 u8 reserved_at_e0[0x120]; 7167 }; 7168 7169 struct mlx5_ifc_destroy_eq_out_bits { 7170 u8 status[0x8]; 7171 u8 reserved_at_8[0x18]; 7172 7173 u8 syndrome[0x20]; 7174 7175 u8 reserved_at_40[0x40]; 7176 }; 7177 7178 struct mlx5_ifc_destroy_eq_in_bits { 7179 u8 opcode[0x10]; 7180 u8 reserved_at_10[0x10]; 7181 7182 u8 reserved_at_20[0x10]; 7183 u8 op_mod[0x10]; 7184 7185 u8 reserved_at_40[0x18]; 7186 u8 eq_number[0x8]; 7187 7188 u8 reserved_at_60[0x20]; 7189 }; 7190 7191 struct mlx5_ifc_destroy_dct_out_bits { 7192 u8 status[0x8]; 7193 u8 reserved_at_8[0x18]; 7194 7195 u8 syndrome[0x20]; 7196 7197 u8 reserved_at_40[0x40]; 7198 }; 7199 7200 struct mlx5_ifc_destroy_dct_in_bits { 7201 u8 opcode[0x10]; 7202 u8 uid[0x10]; 7203 7204 u8 reserved_at_20[0x10]; 7205 u8 op_mod[0x10]; 7206 7207 u8 reserved_at_40[0x8]; 7208 u8 dctn[0x18]; 7209 7210 u8 reserved_at_60[0x20]; 7211 }; 7212 7213 struct mlx5_ifc_destroy_cq_out_bits { 7214 u8 status[0x8]; 7215 u8 reserved_at_8[0x18]; 7216 7217 u8 syndrome[0x20]; 7218 7219 u8 reserved_at_40[0x40]; 7220 }; 7221 7222 struct mlx5_ifc_destroy_cq_in_bits { 7223 u8 opcode[0x10]; 7224 u8 uid[0x10]; 7225 7226 u8 reserved_at_20[0x10]; 7227 u8 op_mod[0x10]; 7228 7229 u8 reserved_at_40[0x8]; 7230 u8 cqn[0x18]; 7231 7232 u8 reserved_at_60[0x20]; 7233 }; 7234 7235 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7236 u8 status[0x8]; 7237 u8 reserved_at_8[0x18]; 7238 7239 u8 syndrome[0x20]; 7240 7241 u8 reserved_at_40[0x40]; 7242 }; 7243 7244 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7245 u8 opcode[0x10]; 7246 u8 reserved_at_10[0x10]; 7247 7248 u8 reserved_at_20[0x10]; 7249 u8 op_mod[0x10]; 7250 7251 u8 reserved_at_40[0x20]; 7252 7253 u8 reserved_at_60[0x10]; 7254 u8 vxlan_udp_port[0x10]; 7255 }; 7256 7257 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7258 u8 status[0x8]; 7259 u8 reserved_at_8[0x18]; 7260 7261 u8 syndrome[0x20]; 7262 7263 u8 reserved_at_40[0x40]; 7264 }; 7265 7266 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7267 u8 opcode[0x10]; 7268 u8 reserved_at_10[0x10]; 7269 7270 u8 reserved_at_20[0x10]; 7271 u8 op_mod[0x10]; 7272 7273 u8 reserved_at_40[0x60]; 7274 7275 u8 reserved_at_a0[0x8]; 7276 u8 table_index[0x18]; 7277 7278 u8 reserved_at_c0[0x140]; 7279 }; 7280 7281 struct mlx5_ifc_delete_fte_out_bits { 7282 u8 status[0x8]; 7283 u8 reserved_at_8[0x18]; 7284 7285 u8 syndrome[0x20]; 7286 7287 u8 reserved_at_40[0x40]; 7288 }; 7289 7290 struct mlx5_ifc_delete_fte_in_bits { 7291 u8 opcode[0x10]; 7292 u8 reserved_at_10[0x10]; 7293 7294 u8 reserved_at_20[0x10]; 7295 u8 op_mod[0x10]; 7296 7297 u8 other_vport[0x1]; 7298 u8 reserved_at_41[0xf]; 7299 u8 vport_number[0x10]; 7300 7301 u8 reserved_at_60[0x20]; 7302 7303 u8 table_type[0x8]; 7304 u8 reserved_at_88[0x18]; 7305 7306 u8 reserved_at_a0[0x8]; 7307 u8 table_id[0x18]; 7308 7309 u8 reserved_at_c0[0x40]; 7310 7311 u8 flow_index[0x20]; 7312 7313 u8 reserved_at_120[0xe0]; 7314 }; 7315 7316 struct mlx5_ifc_dealloc_xrcd_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x40]; 7323 }; 7324 7325 struct mlx5_ifc_dealloc_xrcd_in_bits { 7326 u8 opcode[0x10]; 7327 u8 uid[0x10]; 7328 7329 u8 reserved_at_20[0x10]; 7330 u8 op_mod[0x10]; 7331 7332 u8 reserved_at_40[0x8]; 7333 u8 xrcd[0x18]; 7334 7335 u8 reserved_at_60[0x20]; 7336 }; 7337 7338 struct mlx5_ifc_dealloc_uar_out_bits { 7339 u8 status[0x8]; 7340 u8 reserved_at_8[0x18]; 7341 7342 u8 syndrome[0x20]; 7343 7344 u8 reserved_at_40[0x40]; 7345 }; 7346 7347 struct mlx5_ifc_dealloc_uar_in_bits { 7348 u8 opcode[0x10]; 7349 u8 reserved_at_10[0x10]; 7350 7351 u8 reserved_at_20[0x10]; 7352 u8 op_mod[0x10]; 7353 7354 u8 reserved_at_40[0x8]; 7355 u8 uar[0x18]; 7356 7357 u8 reserved_at_60[0x20]; 7358 }; 7359 7360 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7361 u8 status[0x8]; 7362 u8 reserved_at_8[0x18]; 7363 7364 u8 syndrome[0x20]; 7365 7366 u8 reserved_at_40[0x40]; 7367 }; 7368 7369 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7370 u8 opcode[0x10]; 7371 u8 uid[0x10]; 7372 7373 u8 reserved_at_20[0x10]; 7374 u8 op_mod[0x10]; 7375 7376 u8 reserved_at_40[0x8]; 7377 u8 transport_domain[0x18]; 7378 7379 u8 reserved_at_60[0x20]; 7380 }; 7381 7382 struct mlx5_ifc_dealloc_q_counter_out_bits { 7383 u8 status[0x8]; 7384 u8 reserved_at_8[0x18]; 7385 7386 u8 syndrome[0x20]; 7387 7388 u8 reserved_at_40[0x40]; 7389 }; 7390 7391 struct mlx5_ifc_dealloc_q_counter_in_bits { 7392 u8 opcode[0x10]; 7393 u8 reserved_at_10[0x10]; 7394 7395 u8 reserved_at_20[0x10]; 7396 u8 op_mod[0x10]; 7397 7398 u8 reserved_at_40[0x18]; 7399 u8 counter_set_id[0x8]; 7400 7401 u8 reserved_at_60[0x20]; 7402 }; 7403 7404 struct mlx5_ifc_dealloc_pd_out_bits { 7405 u8 status[0x8]; 7406 u8 reserved_at_8[0x18]; 7407 7408 u8 syndrome[0x20]; 7409 7410 u8 reserved_at_40[0x40]; 7411 }; 7412 7413 struct mlx5_ifc_dealloc_pd_in_bits { 7414 u8 opcode[0x10]; 7415 u8 uid[0x10]; 7416 7417 u8 reserved_at_20[0x10]; 7418 u8 op_mod[0x10]; 7419 7420 u8 reserved_at_40[0x8]; 7421 u8 pd[0x18]; 7422 7423 u8 reserved_at_60[0x20]; 7424 }; 7425 7426 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7427 u8 status[0x8]; 7428 u8 reserved_at_8[0x18]; 7429 7430 u8 syndrome[0x20]; 7431 7432 u8 reserved_at_40[0x40]; 7433 }; 7434 7435 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7436 u8 opcode[0x10]; 7437 u8 reserved_at_10[0x10]; 7438 7439 u8 reserved_at_20[0x10]; 7440 u8 op_mod[0x10]; 7441 7442 u8 flow_counter_id[0x20]; 7443 7444 u8 reserved_at_60[0x20]; 7445 }; 7446 7447 struct mlx5_ifc_create_xrq_out_bits { 7448 u8 status[0x8]; 7449 u8 reserved_at_8[0x18]; 7450 7451 u8 syndrome[0x20]; 7452 7453 u8 reserved_at_40[0x8]; 7454 u8 xrqn[0x18]; 7455 7456 u8 reserved_at_60[0x20]; 7457 }; 7458 7459 struct mlx5_ifc_create_xrq_in_bits { 7460 u8 opcode[0x10]; 7461 u8 uid[0x10]; 7462 7463 u8 reserved_at_20[0x10]; 7464 u8 op_mod[0x10]; 7465 7466 u8 reserved_at_40[0x40]; 7467 7468 struct mlx5_ifc_xrqc_bits xrq_context; 7469 }; 7470 7471 struct mlx5_ifc_create_xrc_srq_out_bits { 7472 u8 status[0x8]; 7473 u8 reserved_at_8[0x18]; 7474 7475 u8 syndrome[0x20]; 7476 7477 u8 reserved_at_40[0x8]; 7478 u8 xrc_srqn[0x18]; 7479 7480 u8 reserved_at_60[0x20]; 7481 }; 7482 7483 struct mlx5_ifc_create_xrc_srq_in_bits { 7484 u8 opcode[0x10]; 7485 u8 uid[0x10]; 7486 7487 u8 reserved_at_20[0x10]; 7488 u8 op_mod[0x10]; 7489 7490 u8 reserved_at_40[0x40]; 7491 7492 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7493 7494 u8 reserved_at_280[0x60]; 7495 7496 u8 xrc_srq_umem_valid[0x1]; 7497 u8 reserved_at_2e1[0x1f]; 7498 7499 u8 reserved_at_300[0x580]; 7500 7501 u8 pas[][0x40]; 7502 }; 7503 7504 struct mlx5_ifc_create_tis_out_bits { 7505 u8 status[0x8]; 7506 u8 reserved_at_8[0x18]; 7507 7508 u8 syndrome[0x20]; 7509 7510 u8 reserved_at_40[0x8]; 7511 u8 tisn[0x18]; 7512 7513 u8 reserved_at_60[0x20]; 7514 }; 7515 7516 struct mlx5_ifc_create_tis_in_bits { 7517 u8 opcode[0x10]; 7518 u8 uid[0x10]; 7519 7520 u8 reserved_at_20[0x10]; 7521 u8 op_mod[0x10]; 7522 7523 u8 reserved_at_40[0xc0]; 7524 7525 struct mlx5_ifc_tisc_bits ctx; 7526 }; 7527 7528 struct mlx5_ifc_create_tir_out_bits { 7529 u8 status[0x8]; 7530 u8 icm_address_63_40[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 icm_address_39_32[0x8]; 7535 u8 tirn[0x18]; 7536 7537 u8 icm_address_31_0[0x20]; 7538 }; 7539 7540 struct mlx5_ifc_create_tir_in_bits { 7541 u8 opcode[0x10]; 7542 u8 uid[0x10]; 7543 7544 u8 reserved_at_20[0x10]; 7545 u8 op_mod[0x10]; 7546 7547 u8 reserved_at_40[0xc0]; 7548 7549 struct mlx5_ifc_tirc_bits ctx; 7550 }; 7551 7552 struct mlx5_ifc_create_srq_out_bits { 7553 u8 status[0x8]; 7554 u8 reserved_at_8[0x18]; 7555 7556 u8 syndrome[0x20]; 7557 7558 u8 reserved_at_40[0x8]; 7559 u8 srqn[0x18]; 7560 7561 u8 reserved_at_60[0x20]; 7562 }; 7563 7564 struct mlx5_ifc_create_srq_in_bits { 7565 u8 opcode[0x10]; 7566 u8 uid[0x10]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 u8 reserved_at_40[0x40]; 7572 7573 struct mlx5_ifc_srqc_bits srq_context_entry; 7574 7575 u8 reserved_at_280[0x600]; 7576 7577 u8 pas[][0x40]; 7578 }; 7579 7580 struct mlx5_ifc_create_sq_out_bits { 7581 u8 status[0x8]; 7582 u8 reserved_at_8[0x18]; 7583 7584 u8 syndrome[0x20]; 7585 7586 u8 reserved_at_40[0x8]; 7587 u8 sqn[0x18]; 7588 7589 u8 reserved_at_60[0x20]; 7590 }; 7591 7592 struct mlx5_ifc_create_sq_in_bits { 7593 u8 opcode[0x10]; 7594 u8 uid[0x10]; 7595 7596 u8 reserved_at_20[0x10]; 7597 u8 op_mod[0x10]; 7598 7599 u8 reserved_at_40[0xc0]; 7600 7601 struct mlx5_ifc_sqc_bits ctx; 7602 }; 7603 7604 struct mlx5_ifc_create_scheduling_element_out_bits { 7605 u8 status[0x8]; 7606 u8 reserved_at_8[0x18]; 7607 7608 u8 syndrome[0x20]; 7609 7610 u8 reserved_at_40[0x40]; 7611 7612 u8 scheduling_element_id[0x20]; 7613 7614 u8 reserved_at_a0[0x160]; 7615 }; 7616 7617 struct mlx5_ifc_create_scheduling_element_in_bits { 7618 u8 opcode[0x10]; 7619 u8 reserved_at_10[0x10]; 7620 7621 u8 reserved_at_20[0x10]; 7622 u8 op_mod[0x10]; 7623 7624 u8 scheduling_hierarchy[0x8]; 7625 u8 reserved_at_48[0x18]; 7626 7627 u8 reserved_at_60[0xa0]; 7628 7629 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7630 7631 u8 reserved_at_300[0x100]; 7632 }; 7633 7634 struct mlx5_ifc_create_rqt_out_bits { 7635 u8 status[0x8]; 7636 u8 reserved_at_8[0x18]; 7637 7638 u8 syndrome[0x20]; 7639 7640 u8 reserved_at_40[0x8]; 7641 u8 rqtn[0x18]; 7642 7643 u8 reserved_at_60[0x20]; 7644 }; 7645 7646 struct mlx5_ifc_create_rqt_in_bits { 7647 u8 opcode[0x10]; 7648 u8 uid[0x10]; 7649 7650 u8 reserved_at_20[0x10]; 7651 u8 op_mod[0x10]; 7652 7653 u8 reserved_at_40[0xc0]; 7654 7655 struct mlx5_ifc_rqtc_bits rqt_context; 7656 }; 7657 7658 struct mlx5_ifc_create_rq_out_bits { 7659 u8 status[0x8]; 7660 u8 reserved_at_8[0x18]; 7661 7662 u8 syndrome[0x20]; 7663 7664 u8 reserved_at_40[0x8]; 7665 u8 rqn[0x18]; 7666 7667 u8 reserved_at_60[0x20]; 7668 }; 7669 7670 struct mlx5_ifc_create_rq_in_bits { 7671 u8 opcode[0x10]; 7672 u8 uid[0x10]; 7673 7674 u8 reserved_at_20[0x10]; 7675 u8 op_mod[0x10]; 7676 7677 u8 reserved_at_40[0xc0]; 7678 7679 struct mlx5_ifc_rqc_bits ctx; 7680 }; 7681 7682 struct mlx5_ifc_create_rmp_out_bits { 7683 u8 status[0x8]; 7684 u8 reserved_at_8[0x18]; 7685 7686 u8 syndrome[0x20]; 7687 7688 u8 reserved_at_40[0x8]; 7689 u8 rmpn[0x18]; 7690 7691 u8 reserved_at_60[0x20]; 7692 }; 7693 7694 struct mlx5_ifc_create_rmp_in_bits { 7695 u8 opcode[0x10]; 7696 u8 uid[0x10]; 7697 7698 u8 reserved_at_20[0x10]; 7699 u8 op_mod[0x10]; 7700 7701 u8 reserved_at_40[0xc0]; 7702 7703 struct mlx5_ifc_rmpc_bits ctx; 7704 }; 7705 7706 struct mlx5_ifc_create_qp_out_bits { 7707 u8 status[0x8]; 7708 u8 reserved_at_8[0x18]; 7709 7710 u8 syndrome[0x20]; 7711 7712 u8 reserved_at_40[0x8]; 7713 u8 qpn[0x18]; 7714 7715 u8 ece[0x20]; 7716 }; 7717 7718 struct mlx5_ifc_create_qp_in_bits { 7719 u8 opcode[0x10]; 7720 u8 uid[0x10]; 7721 7722 u8 reserved_at_20[0x10]; 7723 u8 op_mod[0x10]; 7724 7725 u8 reserved_at_40[0x40]; 7726 7727 u8 opt_param_mask[0x20]; 7728 7729 u8 ece[0x20]; 7730 7731 struct mlx5_ifc_qpc_bits qpc; 7732 7733 u8 reserved_at_800[0x60]; 7734 7735 u8 wq_umem_valid[0x1]; 7736 u8 reserved_at_861[0x1f]; 7737 7738 u8 pas[][0x40]; 7739 }; 7740 7741 struct mlx5_ifc_create_psv_out_bits { 7742 u8 status[0x8]; 7743 u8 reserved_at_8[0x18]; 7744 7745 u8 syndrome[0x20]; 7746 7747 u8 reserved_at_40[0x40]; 7748 7749 u8 reserved_at_80[0x8]; 7750 u8 psv0_index[0x18]; 7751 7752 u8 reserved_at_a0[0x8]; 7753 u8 psv1_index[0x18]; 7754 7755 u8 reserved_at_c0[0x8]; 7756 u8 psv2_index[0x18]; 7757 7758 u8 reserved_at_e0[0x8]; 7759 u8 psv3_index[0x18]; 7760 }; 7761 7762 struct mlx5_ifc_create_psv_in_bits { 7763 u8 opcode[0x10]; 7764 u8 reserved_at_10[0x10]; 7765 7766 u8 reserved_at_20[0x10]; 7767 u8 op_mod[0x10]; 7768 7769 u8 num_psv[0x4]; 7770 u8 reserved_at_44[0x4]; 7771 u8 pd[0x18]; 7772 7773 u8 reserved_at_60[0x20]; 7774 }; 7775 7776 struct mlx5_ifc_create_mkey_out_bits { 7777 u8 status[0x8]; 7778 u8 reserved_at_8[0x18]; 7779 7780 u8 syndrome[0x20]; 7781 7782 u8 reserved_at_40[0x8]; 7783 u8 mkey_index[0x18]; 7784 7785 u8 reserved_at_60[0x20]; 7786 }; 7787 7788 struct mlx5_ifc_create_mkey_in_bits { 7789 u8 opcode[0x10]; 7790 u8 reserved_at_10[0x10]; 7791 7792 u8 reserved_at_20[0x10]; 7793 u8 op_mod[0x10]; 7794 7795 u8 reserved_at_40[0x20]; 7796 7797 u8 pg_access[0x1]; 7798 u8 mkey_umem_valid[0x1]; 7799 u8 reserved_at_62[0x1e]; 7800 7801 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7802 7803 u8 reserved_at_280[0x80]; 7804 7805 u8 translations_octword_actual_size[0x20]; 7806 7807 u8 reserved_at_320[0x560]; 7808 7809 u8 klm_pas_mtt[][0x20]; 7810 }; 7811 7812 enum { 7813 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7814 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7815 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7816 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7817 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7818 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7819 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7820 }; 7821 7822 struct mlx5_ifc_create_flow_table_out_bits { 7823 u8 status[0x8]; 7824 u8 icm_address_63_40[0x18]; 7825 7826 u8 syndrome[0x20]; 7827 7828 u8 icm_address_39_32[0x8]; 7829 u8 table_id[0x18]; 7830 7831 u8 icm_address_31_0[0x20]; 7832 }; 7833 7834 struct mlx5_ifc_create_flow_table_in_bits { 7835 u8 opcode[0x10]; 7836 u8 reserved_at_10[0x10]; 7837 7838 u8 reserved_at_20[0x10]; 7839 u8 op_mod[0x10]; 7840 7841 u8 other_vport[0x1]; 7842 u8 reserved_at_41[0xf]; 7843 u8 vport_number[0x10]; 7844 7845 u8 reserved_at_60[0x20]; 7846 7847 u8 table_type[0x8]; 7848 u8 reserved_at_88[0x18]; 7849 7850 u8 reserved_at_a0[0x20]; 7851 7852 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7853 }; 7854 7855 struct mlx5_ifc_create_flow_group_out_bits { 7856 u8 status[0x8]; 7857 u8 reserved_at_8[0x18]; 7858 7859 u8 syndrome[0x20]; 7860 7861 u8 reserved_at_40[0x8]; 7862 u8 group_id[0x18]; 7863 7864 u8 reserved_at_60[0x20]; 7865 }; 7866 7867 enum { 7868 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7869 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7870 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7871 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7872 }; 7873 7874 struct mlx5_ifc_create_flow_group_in_bits { 7875 u8 opcode[0x10]; 7876 u8 reserved_at_10[0x10]; 7877 7878 u8 reserved_at_20[0x10]; 7879 u8 op_mod[0x10]; 7880 7881 u8 other_vport[0x1]; 7882 u8 reserved_at_41[0xf]; 7883 u8 vport_number[0x10]; 7884 7885 u8 reserved_at_60[0x20]; 7886 7887 u8 table_type[0x8]; 7888 u8 reserved_at_88[0x18]; 7889 7890 u8 reserved_at_a0[0x8]; 7891 u8 table_id[0x18]; 7892 7893 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7894 7895 u8 reserved_at_c1[0x1f]; 7896 7897 u8 start_flow_index[0x20]; 7898 7899 u8 reserved_at_100[0x20]; 7900 7901 u8 end_flow_index[0x20]; 7902 7903 u8 reserved_at_140[0xa0]; 7904 7905 u8 reserved_at_1e0[0x18]; 7906 u8 match_criteria_enable[0x8]; 7907 7908 struct mlx5_ifc_fte_match_param_bits match_criteria; 7909 7910 u8 reserved_at_1200[0xe00]; 7911 }; 7912 7913 struct mlx5_ifc_create_eq_out_bits { 7914 u8 status[0x8]; 7915 u8 reserved_at_8[0x18]; 7916 7917 u8 syndrome[0x20]; 7918 7919 u8 reserved_at_40[0x18]; 7920 u8 eq_number[0x8]; 7921 7922 u8 reserved_at_60[0x20]; 7923 }; 7924 7925 struct mlx5_ifc_create_eq_in_bits { 7926 u8 opcode[0x10]; 7927 u8 uid[0x10]; 7928 7929 u8 reserved_at_20[0x10]; 7930 u8 op_mod[0x10]; 7931 7932 u8 reserved_at_40[0x40]; 7933 7934 struct mlx5_ifc_eqc_bits eq_context_entry; 7935 7936 u8 reserved_at_280[0x40]; 7937 7938 u8 event_bitmask[4][0x40]; 7939 7940 u8 reserved_at_3c0[0x4c0]; 7941 7942 u8 pas[][0x40]; 7943 }; 7944 7945 struct mlx5_ifc_create_dct_out_bits { 7946 u8 status[0x8]; 7947 u8 reserved_at_8[0x18]; 7948 7949 u8 syndrome[0x20]; 7950 7951 u8 reserved_at_40[0x8]; 7952 u8 dctn[0x18]; 7953 7954 u8 ece[0x20]; 7955 }; 7956 7957 struct mlx5_ifc_create_dct_in_bits { 7958 u8 opcode[0x10]; 7959 u8 uid[0x10]; 7960 7961 u8 reserved_at_20[0x10]; 7962 u8 op_mod[0x10]; 7963 7964 u8 reserved_at_40[0x40]; 7965 7966 struct mlx5_ifc_dctc_bits dct_context_entry; 7967 7968 u8 reserved_at_280[0x180]; 7969 }; 7970 7971 struct mlx5_ifc_create_cq_out_bits { 7972 u8 status[0x8]; 7973 u8 reserved_at_8[0x18]; 7974 7975 u8 syndrome[0x20]; 7976 7977 u8 reserved_at_40[0x8]; 7978 u8 cqn[0x18]; 7979 7980 u8 reserved_at_60[0x20]; 7981 }; 7982 7983 struct mlx5_ifc_create_cq_in_bits { 7984 u8 opcode[0x10]; 7985 u8 uid[0x10]; 7986 7987 u8 reserved_at_20[0x10]; 7988 u8 op_mod[0x10]; 7989 7990 u8 reserved_at_40[0x40]; 7991 7992 struct mlx5_ifc_cqc_bits cq_context; 7993 7994 u8 reserved_at_280[0x60]; 7995 7996 u8 cq_umem_valid[0x1]; 7997 u8 reserved_at_2e1[0x59f]; 7998 7999 u8 pas[][0x40]; 8000 }; 8001 8002 struct mlx5_ifc_config_int_moderation_out_bits { 8003 u8 status[0x8]; 8004 u8 reserved_at_8[0x18]; 8005 8006 u8 syndrome[0x20]; 8007 8008 u8 reserved_at_40[0x4]; 8009 u8 min_delay[0xc]; 8010 u8 int_vector[0x10]; 8011 8012 u8 reserved_at_60[0x20]; 8013 }; 8014 8015 enum { 8016 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8017 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8018 }; 8019 8020 struct mlx5_ifc_config_int_moderation_in_bits { 8021 u8 opcode[0x10]; 8022 u8 reserved_at_10[0x10]; 8023 8024 u8 reserved_at_20[0x10]; 8025 u8 op_mod[0x10]; 8026 8027 u8 reserved_at_40[0x4]; 8028 u8 min_delay[0xc]; 8029 u8 int_vector[0x10]; 8030 8031 u8 reserved_at_60[0x20]; 8032 }; 8033 8034 struct mlx5_ifc_attach_to_mcg_out_bits { 8035 u8 status[0x8]; 8036 u8 reserved_at_8[0x18]; 8037 8038 u8 syndrome[0x20]; 8039 8040 u8 reserved_at_40[0x40]; 8041 }; 8042 8043 struct mlx5_ifc_attach_to_mcg_in_bits { 8044 u8 opcode[0x10]; 8045 u8 uid[0x10]; 8046 8047 u8 reserved_at_20[0x10]; 8048 u8 op_mod[0x10]; 8049 8050 u8 reserved_at_40[0x8]; 8051 u8 qpn[0x18]; 8052 8053 u8 reserved_at_60[0x20]; 8054 8055 u8 multicast_gid[16][0x8]; 8056 }; 8057 8058 struct mlx5_ifc_arm_xrq_out_bits { 8059 u8 status[0x8]; 8060 u8 reserved_at_8[0x18]; 8061 8062 u8 syndrome[0x20]; 8063 8064 u8 reserved_at_40[0x40]; 8065 }; 8066 8067 struct mlx5_ifc_arm_xrq_in_bits { 8068 u8 opcode[0x10]; 8069 u8 reserved_at_10[0x10]; 8070 8071 u8 reserved_at_20[0x10]; 8072 u8 op_mod[0x10]; 8073 8074 u8 reserved_at_40[0x8]; 8075 u8 xrqn[0x18]; 8076 8077 u8 reserved_at_60[0x10]; 8078 u8 lwm[0x10]; 8079 }; 8080 8081 struct mlx5_ifc_arm_xrc_srq_out_bits { 8082 u8 status[0x8]; 8083 u8 reserved_at_8[0x18]; 8084 8085 u8 syndrome[0x20]; 8086 8087 u8 reserved_at_40[0x40]; 8088 }; 8089 8090 enum { 8091 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8092 }; 8093 8094 struct mlx5_ifc_arm_xrc_srq_in_bits { 8095 u8 opcode[0x10]; 8096 u8 uid[0x10]; 8097 8098 u8 reserved_at_20[0x10]; 8099 u8 op_mod[0x10]; 8100 8101 u8 reserved_at_40[0x8]; 8102 u8 xrc_srqn[0x18]; 8103 8104 u8 reserved_at_60[0x10]; 8105 u8 lwm[0x10]; 8106 }; 8107 8108 struct mlx5_ifc_arm_rq_out_bits { 8109 u8 status[0x8]; 8110 u8 reserved_at_8[0x18]; 8111 8112 u8 syndrome[0x20]; 8113 8114 u8 reserved_at_40[0x40]; 8115 }; 8116 8117 enum { 8118 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8119 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8120 }; 8121 8122 struct mlx5_ifc_arm_rq_in_bits { 8123 u8 opcode[0x10]; 8124 u8 uid[0x10]; 8125 8126 u8 reserved_at_20[0x10]; 8127 u8 op_mod[0x10]; 8128 8129 u8 reserved_at_40[0x8]; 8130 u8 srq_number[0x18]; 8131 8132 u8 reserved_at_60[0x10]; 8133 u8 lwm[0x10]; 8134 }; 8135 8136 struct mlx5_ifc_arm_dct_out_bits { 8137 u8 status[0x8]; 8138 u8 reserved_at_8[0x18]; 8139 8140 u8 syndrome[0x20]; 8141 8142 u8 reserved_at_40[0x40]; 8143 }; 8144 8145 struct mlx5_ifc_arm_dct_in_bits { 8146 u8 opcode[0x10]; 8147 u8 reserved_at_10[0x10]; 8148 8149 u8 reserved_at_20[0x10]; 8150 u8 op_mod[0x10]; 8151 8152 u8 reserved_at_40[0x8]; 8153 u8 dct_number[0x18]; 8154 8155 u8 reserved_at_60[0x20]; 8156 }; 8157 8158 struct mlx5_ifc_alloc_xrcd_out_bits { 8159 u8 status[0x8]; 8160 u8 reserved_at_8[0x18]; 8161 8162 u8 syndrome[0x20]; 8163 8164 u8 reserved_at_40[0x8]; 8165 u8 xrcd[0x18]; 8166 8167 u8 reserved_at_60[0x20]; 8168 }; 8169 8170 struct mlx5_ifc_alloc_xrcd_in_bits { 8171 u8 opcode[0x10]; 8172 u8 uid[0x10]; 8173 8174 u8 reserved_at_20[0x10]; 8175 u8 op_mod[0x10]; 8176 8177 u8 reserved_at_40[0x40]; 8178 }; 8179 8180 struct mlx5_ifc_alloc_uar_out_bits { 8181 u8 status[0x8]; 8182 u8 reserved_at_8[0x18]; 8183 8184 u8 syndrome[0x20]; 8185 8186 u8 reserved_at_40[0x8]; 8187 u8 uar[0x18]; 8188 8189 u8 reserved_at_60[0x20]; 8190 }; 8191 8192 struct mlx5_ifc_alloc_uar_in_bits { 8193 u8 opcode[0x10]; 8194 u8 reserved_at_10[0x10]; 8195 8196 u8 reserved_at_20[0x10]; 8197 u8 op_mod[0x10]; 8198 8199 u8 reserved_at_40[0x40]; 8200 }; 8201 8202 struct mlx5_ifc_alloc_transport_domain_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 reserved_at_40[0x8]; 8209 u8 transport_domain[0x18]; 8210 8211 u8 reserved_at_60[0x20]; 8212 }; 8213 8214 struct mlx5_ifc_alloc_transport_domain_in_bits { 8215 u8 opcode[0x10]; 8216 u8 uid[0x10]; 8217 8218 u8 reserved_at_20[0x10]; 8219 u8 op_mod[0x10]; 8220 8221 u8 reserved_at_40[0x40]; 8222 }; 8223 8224 struct mlx5_ifc_alloc_q_counter_out_bits { 8225 u8 status[0x8]; 8226 u8 reserved_at_8[0x18]; 8227 8228 u8 syndrome[0x20]; 8229 8230 u8 reserved_at_40[0x18]; 8231 u8 counter_set_id[0x8]; 8232 8233 u8 reserved_at_60[0x20]; 8234 }; 8235 8236 struct mlx5_ifc_alloc_q_counter_in_bits { 8237 u8 opcode[0x10]; 8238 u8 uid[0x10]; 8239 8240 u8 reserved_at_20[0x10]; 8241 u8 op_mod[0x10]; 8242 8243 u8 reserved_at_40[0x40]; 8244 }; 8245 8246 struct mlx5_ifc_alloc_pd_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x8]; 8253 u8 pd[0x18]; 8254 8255 u8 reserved_at_60[0x20]; 8256 }; 8257 8258 struct mlx5_ifc_alloc_pd_in_bits { 8259 u8 opcode[0x10]; 8260 u8 uid[0x10]; 8261 8262 u8 reserved_at_20[0x10]; 8263 u8 op_mod[0x10]; 8264 8265 u8 reserved_at_40[0x40]; 8266 }; 8267 8268 struct mlx5_ifc_alloc_flow_counter_out_bits { 8269 u8 status[0x8]; 8270 u8 reserved_at_8[0x18]; 8271 8272 u8 syndrome[0x20]; 8273 8274 u8 flow_counter_id[0x20]; 8275 8276 u8 reserved_at_60[0x20]; 8277 }; 8278 8279 struct mlx5_ifc_alloc_flow_counter_in_bits { 8280 u8 opcode[0x10]; 8281 u8 reserved_at_10[0x10]; 8282 8283 u8 reserved_at_20[0x10]; 8284 u8 op_mod[0x10]; 8285 8286 u8 reserved_at_40[0x38]; 8287 u8 flow_counter_bulk[0x8]; 8288 }; 8289 8290 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8291 u8 status[0x8]; 8292 u8 reserved_at_8[0x18]; 8293 8294 u8 syndrome[0x20]; 8295 8296 u8 reserved_at_40[0x40]; 8297 }; 8298 8299 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8300 u8 opcode[0x10]; 8301 u8 reserved_at_10[0x10]; 8302 8303 u8 reserved_at_20[0x10]; 8304 u8 op_mod[0x10]; 8305 8306 u8 reserved_at_40[0x20]; 8307 8308 u8 reserved_at_60[0x10]; 8309 u8 vxlan_udp_port[0x10]; 8310 }; 8311 8312 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8313 u8 status[0x8]; 8314 u8 reserved_at_8[0x18]; 8315 8316 u8 syndrome[0x20]; 8317 8318 u8 reserved_at_40[0x40]; 8319 }; 8320 8321 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8322 u8 rate_limit[0x20]; 8323 8324 u8 burst_upper_bound[0x20]; 8325 8326 u8 reserved_at_40[0x10]; 8327 u8 typical_packet_size[0x10]; 8328 8329 u8 reserved_at_60[0x120]; 8330 }; 8331 8332 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8333 u8 opcode[0x10]; 8334 u8 uid[0x10]; 8335 8336 u8 reserved_at_20[0x10]; 8337 u8 op_mod[0x10]; 8338 8339 u8 reserved_at_40[0x10]; 8340 u8 rate_limit_index[0x10]; 8341 8342 u8 reserved_at_60[0x20]; 8343 8344 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8345 }; 8346 8347 struct mlx5_ifc_access_register_out_bits { 8348 u8 status[0x8]; 8349 u8 reserved_at_8[0x18]; 8350 8351 u8 syndrome[0x20]; 8352 8353 u8 reserved_at_40[0x40]; 8354 8355 u8 register_data[][0x20]; 8356 }; 8357 8358 enum { 8359 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8360 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8361 }; 8362 8363 struct mlx5_ifc_access_register_in_bits { 8364 u8 opcode[0x10]; 8365 u8 reserved_at_10[0x10]; 8366 8367 u8 reserved_at_20[0x10]; 8368 u8 op_mod[0x10]; 8369 8370 u8 reserved_at_40[0x10]; 8371 u8 register_id[0x10]; 8372 8373 u8 argument[0x20]; 8374 8375 u8 register_data[][0x20]; 8376 }; 8377 8378 struct mlx5_ifc_sltp_reg_bits { 8379 u8 status[0x4]; 8380 u8 version[0x4]; 8381 u8 local_port[0x8]; 8382 u8 pnat[0x2]; 8383 u8 reserved_at_12[0x2]; 8384 u8 lane[0x4]; 8385 u8 reserved_at_18[0x8]; 8386 8387 u8 reserved_at_20[0x20]; 8388 8389 u8 reserved_at_40[0x7]; 8390 u8 polarity[0x1]; 8391 u8 ob_tap0[0x8]; 8392 u8 ob_tap1[0x8]; 8393 u8 ob_tap2[0x8]; 8394 8395 u8 reserved_at_60[0xc]; 8396 u8 ob_preemp_mode[0x4]; 8397 u8 ob_reg[0x8]; 8398 u8 ob_bias[0x8]; 8399 8400 u8 reserved_at_80[0x20]; 8401 }; 8402 8403 struct mlx5_ifc_slrg_reg_bits { 8404 u8 status[0x4]; 8405 u8 version[0x4]; 8406 u8 local_port[0x8]; 8407 u8 pnat[0x2]; 8408 u8 reserved_at_12[0x2]; 8409 u8 lane[0x4]; 8410 u8 reserved_at_18[0x8]; 8411 8412 u8 time_to_link_up[0x10]; 8413 u8 reserved_at_30[0xc]; 8414 u8 grade_lane_speed[0x4]; 8415 8416 u8 grade_version[0x8]; 8417 u8 grade[0x18]; 8418 8419 u8 reserved_at_60[0x4]; 8420 u8 height_grade_type[0x4]; 8421 u8 height_grade[0x18]; 8422 8423 u8 height_dz[0x10]; 8424 u8 height_dv[0x10]; 8425 8426 u8 reserved_at_a0[0x10]; 8427 u8 height_sigma[0x10]; 8428 8429 u8 reserved_at_c0[0x20]; 8430 8431 u8 reserved_at_e0[0x4]; 8432 u8 phase_grade_type[0x4]; 8433 u8 phase_grade[0x18]; 8434 8435 u8 reserved_at_100[0x8]; 8436 u8 phase_eo_pos[0x8]; 8437 u8 reserved_at_110[0x8]; 8438 u8 phase_eo_neg[0x8]; 8439 8440 u8 ffe_set_tested[0x10]; 8441 u8 test_errors_per_lane[0x10]; 8442 }; 8443 8444 struct mlx5_ifc_pvlc_reg_bits { 8445 u8 reserved_at_0[0x8]; 8446 u8 local_port[0x8]; 8447 u8 reserved_at_10[0x10]; 8448 8449 u8 reserved_at_20[0x1c]; 8450 u8 vl_hw_cap[0x4]; 8451 8452 u8 reserved_at_40[0x1c]; 8453 u8 vl_admin[0x4]; 8454 8455 u8 reserved_at_60[0x1c]; 8456 u8 vl_operational[0x4]; 8457 }; 8458 8459 struct mlx5_ifc_pude_reg_bits { 8460 u8 swid[0x8]; 8461 u8 local_port[0x8]; 8462 u8 reserved_at_10[0x4]; 8463 u8 admin_status[0x4]; 8464 u8 reserved_at_18[0x4]; 8465 u8 oper_status[0x4]; 8466 8467 u8 reserved_at_20[0x60]; 8468 }; 8469 8470 struct mlx5_ifc_ptys_reg_bits { 8471 u8 reserved_at_0[0x1]; 8472 u8 an_disable_admin[0x1]; 8473 u8 an_disable_cap[0x1]; 8474 u8 reserved_at_3[0x5]; 8475 u8 local_port[0x8]; 8476 u8 reserved_at_10[0xd]; 8477 u8 proto_mask[0x3]; 8478 8479 u8 an_status[0x4]; 8480 u8 reserved_at_24[0xc]; 8481 u8 data_rate_oper[0x10]; 8482 8483 u8 ext_eth_proto_capability[0x20]; 8484 8485 u8 eth_proto_capability[0x20]; 8486 8487 u8 ib_link_width_capability[0x10]; 8488 u8 ib_proto_capability[0x10]; 8489 8490 u8 ext_eth_proto_admin[0x20]; 8491 8492 u8 eth_proto_admin[0x20]; 8493 8494 u8 ib_link_width_admin[0x10]; 8495 u8 ib_proto_admin[0x10]; 8496 8497 u8 ext_eth_proto_oper[0x20]; 8498 8499 u8 eth_proto_oper[0x20]; 8500 8501 u8 ib_link_width_oper[0x10]; 8502 u8 ib_proto_oper[0x10]; 8503 8504 u8 reserved_at_160[0x1c]; 8505 u8 connector_type[0x4]; 8506 8507 u8 eth_proto_lp_advertise[0x20]; 8508 8509 u8 reserved_at_1a0[0x60]; 8510 }; 8511 8512 struct mlx5_ifc_mlcr_reg_bits { 8513 u8 reserved_at_0[0x8]; 8514 u8 local_port[0x8]; 8515 u8 reserved_at_10[0x20]; 8516 8517 u8 beacon_duration[0x10]; 8518 u8 reserved_at_40[0x10]; 8519 8520 u8 beacon_remain[0x10]; 8521 }; 8522 8523 struct mlx5_ifc_ptas_reg_bits { 8524 u8 reserved_at_0[0x20]; 8525 8526 u8 algorithm_options[0x10]; 8527 u8 reserved_at_30[0x4]; 8528 u8 repetitions_mode[0x4]; 8529 u8 num_of_repetitions[0x8]; 8530 8531 u8 grade_version[0x8]; 8532 u8 height_grade_type[0x4]; 8533 u8 phase_grade_type[0x4]; 8534 u8 height_grade_weight[0x8]; 8535 u8 phase_grade_weight[0x8]; 8536 8537 u8 gisim_measure_bits[0x10]; 8538 u8 adaptive_tap_measure_bits[0x10]; 8539 8540 u8 ber_bath_high_error_threshold[0x10]; 8541 u8 ber_bath_mid_error_threshold[0x10]; 8542 8543 u8 ber_bath_low_error_threshold[0x10]; 8544 u8 one_ratio_high_threshold[0x10]; 8545 8546 u8 one_ratio_high_mid_threshold[0x10]; 8547 u8 one_ratio_low_mid_threshold[0x10]; 8548 8549 u8 one_ratio_low_threshold[0x10]; 8550 u8 ndeo_error_threshold[0x10]; 8551 8552 u8 mixer_offset_step_size[0x10]; 8553 u8 reserved_at_110[0x8]; 8554 u8 mix90_phase_for_voltage_bath[0x8]; 8555 8556 u8 mixer_offset_start[0x10]; 8557 u8 mixer_offset_end[0x10]; 8558 8559 u8 reserved_at_140[0x15]; 8560 u8 ber_test_time[0xb]; 8561 }; 8562 8563 struct mlx5_ifc_pspa_reg_bits { 8564 u8 swid[0x8]; 8565 u8 local_port[0x8]; 8566 u8 sub_port[0x8]; 8567 u8 reserved_at_18[0x8]; 8568 8569 u8 reserved_at_20[0x20]; 8570 }; 8571 8572 struct mlx5_ifc_pqdr_reg_bits { 8573 u8 reserved_at_0[0x8]; 8574 u8 local_port[0x8]; 8575 u8 reserved_at_10[0x5]; 8576 u8 prio[0x3]; 8577 u8 reserved_at_18[0x6]; 8578 u8 mode[0x2]; 8579 8580 u8 reserved_at_20[0x20]; 8581 8582 u8 reserved_at_40[0x10]; 8583 u8 min_threshold[0x10]; 8584 8585 u8 reserved_at_60[0x10]; 8586 u8 max_threshold[0x10]; 8587 8588 u8 reserved_at_80[0x10]; 8589 u8 mark_probability_denominator[0x10]; 8590 8591 u8 reserved_at_a0[0x60]; 8592 }; 8593 8594 struct mlx5_ifc_ppsc_reg_bits { 8595 u8 reserved_at_0[0x8]; 8596 u8 local_port[0x8]; 8597 u8 reserved_at_10[0x10]; 8598 8599 u8 reserved_at_20[0x60]; 8600 8601 u8 reserved_at_80[0x1c]; 8602 u8 wrps_admin[0x4]; 8603 8604 u8 reserved_at_a0[0x1c]; 8605 u8 wrps_status[0x4]; 8606 8607 u8 reserved_at_c0[0x8]; 8608 u8 up_threshold[0x8]; 8609 u8 reserved_at_d0[0x8]; 8610 u8 down_threshold[0x8]; 8611 8612 u8 reserved_at_e0[0x20]; 8613 8614 u8 reserved_at_100[0x1c]; 8615 u8 srps_admin[0x4]; 8616 8617 u8 reserved_at_120[0x1c]; 8618 u8 srps_status[0x4]; 8619 8620 u8 reserved_at_140[0x40]; 8621 }; 8622 8623 struct mlx5_ifc_pplr_reg_bits { 8624 u8 reserved_at_0[0x8]; 8625 u8 local_port[0x8]; 8626 u8 reserved_at_10[0x10]; 8627 8628 u8 reserved_at_20[0x8]; 8629 u8 lb_cap[0x8]; 8630 u8 reserved_at_30[0x8]; 8631 u8 lb_en[0x8]; 8632 }; 8633 8634 struct mlx5_ifc_pplm_reg_bits { 8635 u8 reserved_at_0[0x8]; 8636 u8 local_port[0x8]; 8637 u8 reserved_at_10[0x10]; 8638 8639 u8 reserved_at_20[0x20]; 8640 8641 u8 port_profile_mode[0x8]; 8642 u8 static_port_profile[0x8]; 8643 u8 active_port_profile[0x8]; 8644 u8 reserved_at_58[0x8]; 8645 8646 u8 retransmission_active[0x8]; 8647 u8 fec_mode_active[0x18]; 8648 8649 u8 rs_fec_correction_bypass_cap[0x4]; 8650 u8 reserved_at_84[0x8]; 8651 u8 fec_override_cap_56g[0x4]; 8652 u8 fec_override_cap_100g[0x4]; 8653 u8 fec_override_cap_50g[0x4]; 8654 u8 fec_override_cap_25g[0x4]; 8655 u8 fec_override_cap_10g_40g[0x4]; 8656 8657 u8 rs_fec_correction_bypass_admin[0x4]; 8658 u8 reserved_at_a4[0x8]; 8659 u8 fec_override_admin_56g[0x4]; 8660 u8 fec_override_admin_100g[0x4]; 8661 u8 fec_override_admin_50g[0x4]; 8662 u8 fec_override_admin_25g[0x4]; 8663 u8 fec_override_admin_10g_40g[0x4]; 8664 8665 u8 fec_override_cap_400g_8x[0x10]; 8666 u8 fec_override_cap_200g_4x[0x10]; 8667 8668 u8 fec_override_cap_100g_2x[0x10]; 8669 u8 fec_override_cap_50g_1x[0x10]; 8670 8671 u8 fec_override_admin_400g_8x[0x10]; 8672 u8 fec_override_admin_200g_4x[0x10]; 8673 8674 u8 fec_override_admin_100g_2x[0x10]; 8675 u8 fec_override_admin_50g_1x[0x10]; 8676 }; 8677 8678 struct mlx5_ifc_ppcnt_reg_bits { 8679 u8 swid[0x8]; 8680 u8 local_port[0x8]; 8681 u8 pnat[0x2]; 8682 u8 reserved_at_12[0x8]; 8683 u8 grp[0x6]; 8684 8685 u8 clr[0x1]; 8686 u8 reserved_at_21[0x1c]; 8687 u8 prio_tc[0x3]; 8688 8689 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8690 }; 8691 8692 struct mlx5_ifc_mpein_reg_bits { 8693 u8 reserved_at_0[0x2]; 8694 u8 depth[0x6]; 8695 u8 pcie_index[0x8]; 8696 u8 node[0x8]; 8697 u8 reserved_at_18[0x8]; 8698 8699 u8 capability_mask[0x20]; 8700 8701 u8 reserved_at_40[0x8]; 8702 u8 link_width_enabled[0x8]; 8703 u8 link_speed_enabled[0x10]; 8704 8705 u8 lane0_physical_position[0x8]; 8706 u8 link_width_active[0x8]; 8707 u8 link_speed_active[0x10]; 8708 8709 u8 num_of_pfs[0x10]; 8710 u8 num_of_vfs[0x10]; 8711 8712 u8 bdf0[0x10]; 8713 u8 reserved_at_b0[0x10]; 8714 8715 u8 max_read_request_size[0x4]; 8716 u8 max_payload_size[0x4]; 8717 u8 reserved_at_c8[0x5]; 8718 u8 pwr_status[0x3]; 8719 u8 port_type[0x4]; 8720 u8 reserved_at_d4[0xb]; 8721 u8 lane_reversal[0x1]; 8722 8723 u8 reserved_at_e0[0x14]; 8724 u8 pci_power[0xc]; 8725 8726 u8 reserved_at_100[0x20]; 8727 8728 u8 device_status[0x10]; 8729 u8 port_state[0x8]; 8730 u8 reserved_at_138[0x8]; 8731 8732 u8 reserved_at_140[0x10]; 8733 u8 receiver_detect_result[0x10]; 8734 8735 u8 reserved_at_160[0x20]; 8736 }; 8737 8738 struct mlx5_ifc_mpcnt_reg_bits { 8739 u8 reserved_at_0[0x8]; 8740 u8 pcie_index[0x8]; 8741 u8 reserved_at_10[0xa]; 8742 u8 grp[0x6]; 8743 8744 u8 clr[0x1]; 8745 u8 reserved_at_21[0x1f]; 8746 8747 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8748 }; 8749 8750 struct mlx5_ifc_ppad_reg_bits { 8751 u8 reserved_at_0[0x3]; 8752 u8 single_mac[0x1]; 8753 u8 reserved_at_4[0x4]; 8754 u8 local_port[0x8]; 8755 u8 mac_47_32[0x10]; 8756 8757 u8 mac_31_0[0x20]; 8758 8759 u8 reserved_at_40[0x40]; 8760 }; 8761 8762 struct mlx5_ifc_pmtu_reg_bits { 8763 u8 reserved_at_0[0x8]; 8764 u8 local_port[0x8]; 8765 u8 reserved_at_10[0x10]; 8766 8767 u8 max_mtu[0x10]; 8768 u8 reserved_at_30[0x10]; 8769 8770 u8 admin_mtu[0x10]; 8771 u8 reserved_at_50[0x10]; 8772 8773 u8 oper_mtu[0x10]; 8774 u8 reserved_at_70[0x10]; 8775 }; 8776 8777 struct mlx5_ifc_pmpr_reg_bits { 8778 u8 reserved_at_0[0x8]; 8779 u8 module[0x8]; 8780 u8 reserved_at_10[0x10]; 8781 8782 u8 reserved_at_20[0x18]; 8783 u8 attenuation_5g[0x8]; 8784 8785 u8 reserved_at_40[0x18]; 8786 u8 attenuation_7g[0x8]; 8787 8788 u8 reserved_at_60[0x18]; 8789 u8 attenuation_12g[0x8]; 8790 }; 8791 8792 struct mlx5_ifc_pmpe_reg_bits { 8793 u8 reserved_at_0[0x8]; 8794 u8 module[0x8]; 8795 u8 reserved_at_10[0xc]; 8796 u8 module_status[0x4]; 8797 8798 u8 reserved_at_20[0x60]; 8799 }; 8800 8801 struct mlx5_ifc_pmpc_reg_bits { 8802 u8 module_state_updated[32][0x8]; 8803 }; 8804 8805 struct mlx5_ifc_pmlpn_reg_bits { 8806 u8 reserved_at_0[0x4]; 8807 u8 mlpn_status[0x4]; 8808 u8 local_port[0x8]; 8809 u8 reserved_at_10[0x10]; 8810 8811 u8 e[0x1]; 8812 u8 reserved_at_21[0x1f]; 8813 }; 8814 8815 struct mlx5_ifc_pmlp_reg_bits { 8816 u8 rxtx[0x1]; 8817 u8 reserved_at_1[0x7]; 8818 u8 local_port[0x8]; 8819 u8 reserved_at_10[0x8]; 8820 u8 width[0x8]; 8821 8822 u8 lane0_module_mapping[0x20]; 8823 8824 u8 lane1_module_mapping[0x20]; 8825 8826 u8 lane2_module_mapping[0x20]; 8827 8828 u8 lane3_module_mapping[0x20]; 8829 8830 u8 reserved_at_a0[0x160]; 8831 }; 8832 8833 struct mlx5_ifc_pmaos_reg_bits { 8834 u8 reserved_at_0[0x8]; 8835 u8 module[0x8]; 8836 u8 reserved_at_10[0x4]; 8837 u8 admin_status[0x4]; 8838 u8 reserved_at_18[0x4]; 8839 u8 oper_status[0x4]; 8840 8841 u8 ase[0x1]; 8842 u8 ee[0x1]; 8843 u8 reserved_at_22[0x1c]; 8844 u8 e[0x2]; 8845 8846 u8 reserved_at_40[0x40]; 8847 }; 8848 8849 struct mlx5_ifc_plpc_reg_bits { 8850 u8 reserved_at_0[0x4]; 8851 u8 profile_id[0xc]; 8852 u8 reserved_at_10[0x4]; 8853 u8 proto_mask[0x4]; 8854 u8 reserved_at_18[0x8]; 8855 8856 u8 reserved_at_20[0x10]; 8857 u8 lane_speed[0x10]; 8858 8859 u8 reserved_at_40[0x17]; 8860 u8 lpbf[0x1]; 8861 u8 fec_mode_policy[0x8]; 8862 8863 u8 retransmission_capability[0x8]; 8864 u8 fec_mode_capability[0x18]; 8865 8866 u8 retransmission_support_admin[0x8]; 8867 u8 fec_mode_support_admin[0x18]; 8868 8869 u8 retransmission_request_admin[0x8]; 8870 u8 fec_mode_request_admin[0x18]; 8871 8872 u8 reserved_at_c0[0x80]; 8873 }; 8874 8875 struct mlx5_ifc_plib_reg_bits { 8876 u8 reserved_at_0[0x8]; 8877 u8 local_port[0x8]; 8878 u8 reserved_at_10[0x8]; 8879 u8 ib_port[0x8]; 8880 8881 u8 reserved_at_20[0x60]; 8882 }; 8883 8884 struct mlx5_ifc_plbf_reg_bits { 8885 u8 reserved_at_0[0x8]; 8886 u8 local_port[0x8]; 8887 u8 reserved_at_10[0xd]; 8888 u8 lbf_mode[0x3]; 8889 8890 u8 reserved_at_20[0x20]; 8891 }; 8892 8893 struct mlx5_ifc_pipg_reg_bits { 8894 u8 reserved_at_0[0x8]; 8895 u8 local_port[0x8]; 8896 u8 reserved_at_10[0x10]; 8897 8898 u8 dic[0x1]; 8899 u8 reserved_at_21[0x19]; 8900 u8 ipg[0x4]; 8901 u8 reserved_at_3e[0x2]; 8902 }; 8903 8904 struct mlx5_ifc_pifr_reg_bits { 8905 u8 reserved_at_0[0x8]; 8906 u8 local_port[0x8]; 8907 u8 reserved_at_10[0x10]; 8908 8909 u8 reserved_at_20[0xe0]; 8910 8911 u8 port_filter[8][0x20]; 8912 8913 u8 port_filter_update_en[8][0x20]; 8914 }; 8915 8916 struct mlx5_ifc_pfcc_reg_bits { 8917 u8 reserved_at_0[0x8]; 8918 u8 local_port[0x8]; 8919 u8 reserved_at_10[0xb]; 8920 u8 ppan_mask_n[0x1]; 8921 u8 minor_stall_mask[0x1]; 8922 u8 critical_stall_mask[0x1]; 8923 u8 reserved_at_1e[0x2]; 8924 8925 u8 ppan[0x4]; 8926 u8 reserved_at_24[0x4]; 8927 u8 prio_mask_tx[0x8]; 8928 u8 reserved_at_30[0x8]; 8929 u8 prio_mask_rx[0x8]; 8930 8931 u8 pptx[0x1]; 8932 u8 aptx[0x1]; 8933 u8 pptx_mask_n[0x1]; 8934 u8 reserved_at_43[0x5]; 8935 u8 pfctx[0x8]; 8936 u8 reserved_at_50[0x10]; 8937 8938 u8 pprx[0x1]; 8939 u8 aprx[0x1]; 8940 u8 pprx_mask_n[0x1]; 8941 u8 reserved_at_63[0x5]; 8942 u8 pfcrx[0x8]; 8943 u8 reserved_at_70[0x10]; 8944 8945 u8 device_stall_minor_watermark[0x10]; 8946 u8 device_stall_critical_watermark[0x10]; 8947 8948 u8 reserved_at_a0[0x60]; 8949 }; 8950 8951 struct mlx5_ifc_pelc_reg_bits { 8952 u8 op[0x4]; 8953 u8 reserved_at_4[0x4]; 8954 u8 local_port[0x8]; 8955 u8 reserved_at_10[0x10]; 8956 8957 u8 op_admin[0x8]; 8958 u8 op_capability[0x8]; 8959 u8 op_request[0x8]; 8960 u8 op_active[0x8]; 8961 8962 u8 admin[0x40]; 8963 8964 u8 capability[0x40]; 8965 8966 u8 request[0x40]; 8967 8968 u8 active[0x40]; 8969 8970 u8 reserved_at_140[0x80]; 8971 }; 8972 8973 struct mlx5_ifc_peir_reg_bits { 8974 u8 reserved_at_0[0x8]; 8975 u8 local_port[0x8]; 8976 u8 reserved_at_10[0x10]; 8977 8978 u8 reserved_at_20[0xc]; 8979 u8 error_count[0x4]; 8980 u8 reserved_at_30[0x10]; 8981 8982 u8 reserved_at_40[0xc]; 8983 u8 lane[0x4]; 8984 u8 reserved_at_50[0x8]; 8985 u8 error_type[0x8]; 8986 }; 8987 8988 struct mlx5_ifc_mpegc_reg_bits { 8989 u8 reserved_at_0[0x30]; 8990 u8 field_select[0x10]; 8991 8992 u8 tx_overflow_sense[0x1]; 8993 u8 mark_cqe[0x1]; 8994 u8 mark_cnp[0x1]; 8995 u8 reserved_at_43[0x1b]; 8996 u8 tx_lossy_overflow_oper[0x2]; 8997 8998 u8 reserved_at_60[0x100]; 8999 }; 9000 9001 struct mlx5_ifc_pcam_enhanced_features_bits { 9002 u8 reserved_at_0[0x68]; 9003 u8 fec_50G_per_lane_in_pplm[0x1]; 9004 u8 reserved_at_69[0x4]; 9005 u8 rx_icrc_encapsulated_counter[0x1]; 9006 u8 reserved_at_6e[0x4]; 9007 u8 ptys_extended_ethernet[0x1]; 9008 u8 reserved_at_73[0x3]; 9009 u8 pfcc_mask[0x1]; 9010 u8 reserved_at_77[0x3]; 9011 u8 per_lane_error_counters[0x1]; 9012 u8 rx_buffer_fullness_counters[0x1]; 9013 u8 ptys_connector_type[0x1]; 9014 u8 reserved_at_7d[0x1]; 9015 u8 ppcnt_discard_group[0x1]; 9016 u8 ppcnt_statistical_group[0x1]; 9017 }; 9018 9019 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9020 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9021 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9022 9023 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9024 u8 pplm[0x1]; 9025 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9026 9027 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9028 u8 pbmc[0x1]; 9029 u8 pptb[0x1]; 9030 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9031 u8 ppcnt[0x1]; 9032 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9033 }; 9034 9035 struct mlx5_ifc_pcam_reg_bits { 9036 u8 reserved_at_0[0x8]; 9037 u8 feature_group[0x8]; 9038 u8 reserved_at_10[0x8]; 9039 u8 access_reg_group[0x8]; 9040 9041 u8 reserved_at_20[0x20]; 9042 9043 union { 9044 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9045 u8 reserved_at_0[0x80]; 9046 } port_access_reg_cap_mask; 9047 9048 u8 reserved_at_c0[0x80]; 9049 9050 union { 9051 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9052 u8 reserved_at_0[0x80]; 9053 } feature_cap_mask; 9054 9055 u8 reserved_at_1c0[0xc0]; 9056 }; 9057 9058 struct mlx5_ifc_mcam_enhanced_features_bits { 9059 u8 reserved_at_0[0x6e]; 9060 u8 pci_status_and_power[0x1]; 9061 u8 reserved_at_6f[0x5]; 9062 u8 mark_tx_action_cnp[0x1]; 9063 u8 mark_tx_action_cqe[0x1]; 9064 u8 dynamic_tx_overflow[0x1]; 9065 u8 reserved_at_77[0x4]; 9066 u8 pcie_outbound_stalled[0x1]; 9067 u8 tx_overflow_buffer_pkt[0x1]; 9068 u8 mtpps_enh_out_per_adj[0x1]; 9069 u8 mtpps_fs[0x1]; 9070 u8 pcie_performance_group[0x1]; 9071 }; 9072 9073 struct mlx5_ifc_mcam_access_reg_bits { 9074 u8 reserved_at_0[0x1c]; 9075 u8 mcda[0x1]; 9076 u8 mcc[0x1]; 9077 u8 mcqi[0x1]; 9078 u8 mcqs[0x1]; 9079 9080 u8 regs_95_to_87[0x9]; 9081 u8 mpegc[0x1]; 9082 u8 regs_85_to_68[0x12]; 9083 u8 tracer_registers[0x4]; 9084 9085 u8 regs_63_to_32[0x20]; 9086 u8 regs_31_to_0[0x20]; 9087 }; 9088 9089 struct mlx5_ifc_mcam_access_reg_bits1 { 9090 u8 regs_127_to_96[0x20]; 9091 9092 u8 regs_95_to_64[0x20]; 9093 9094 u8 regs_63_to_32[0x20]; 9095 9096 u8 regs_31_to_0[0x20]; 9097 }; 9098 9099 struct mlx5_ifc_mcam_access_reg_bits2 { 9100 u8 regs_127_to_99[0x1d]; 9101 u8 mirc[0x1]; 9102 u8 regs_97_to_96[0x2]; 9103 9104 u8 regs_95_to_64[0x20]; 9105 9106 u8 regs_63_to_32[0x20]; 9107 9108 u8 regs_31_to_0[0x20]; 9109 }; 9110 9111 struct mlx5_ifc_mcam_reg_bits { 9112 u8 reserved_at_0[0x8]; 9113 u8 feature_group[0x8]; 9114 u8 reserved_at_10[0x8]; 9115 u8 access_reg_group[0x8]; 9116 9117 u8 reserved_at_20[0x20]; 9118 9119 union { 9120 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9121 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9122 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9123 u8 reserved_at_0[0x80]; 9124 } mng_access_reg_cap_mask; 9125 9126 u8 reserved_at_c0[0x80]; 9127 9128 union { 9129 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9130 u8 reserved_at_0[0x80]; 9131 } mng_feature_cap_mask; 9132 9133 u8 reserved_at_1c0[0x80]; 9134 }; 9135 9136 struct mlx5_ifc_qcam_access_reg_cap_mask { 9137 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9138 u8 qpdpm[0x1]; 9139 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9140 u8 qdpm[0x1]; 9141 u8 qpts[0x1]; 9142 u8 qcap[0x1]; 9143 u8 qcam_access_reg_cap_mask_0[0x1]; 9144 }; 9145 9146 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9147 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9148 u8 qpts_trust_both[0x1]; 9149 }; 9150 9151 struct mlx5_ifc_qcam_reg_bits { 9152 u8 reserved_at_0[0x8]; 9153 u8 feature_group[0x8]; 9154 u8 reserved_at_10[0x8]; 9155 u8 access_reg_group[0x8]; 9156 u8 reserved_at_20[0x20]; 9157 9158 union { 9159 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9160 u8 reserved_at_0[0x80]; 9161 } qos_access_reg_cap_mask; 9162 9163 u8 reserved_at_c0[0x80]; 9164 9165 union { 9166 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9167 u8 reserved_at_0[0x80]; 9168 } qos_feature_cap_mask; 9169 9170 u8 reserved_at_1c0[0x80]; 9171 }; 9172 9173 struct mlx5_ifc_core_dump_reg_bits { 9174 u8 reserved_at_0[0x18]; 9175 u8 core_dump_type[0x8]; 9176 9177 u8 reserved_at_20[0x30]; 9178 u8 vhca_id[0x10]; 9179 9180 u8 reserved_at_60[0x8]; 9181 u8 qpn[0x18]; 9182 u8 reserved_at_80[0x180]; 9183 }; 9184 9185 struct mlx5_ifc_pcap_reg_bits { 9186 u8 reserved_at_0[0x8]; 9187 u8 local_port[0x8]; 9188 u8 reserved_at_10[0x10]; 9189 9190 u8 port_capability_mask[4][0x20]; 9191 }; 9192 9193 struct mlx5_ifc_paos_reg_bits { 9194 u8 swid[0x8]; 9195 u8 local_port[0x8]; 9196 u8 reserved_at_10[0x4]; 9197 u8 admin_status[0x4]; 9198 u8 reserved_at_18[0x4]; 9199 u8 oper_status[0x4]; 9200 9201 u8 ase[0x1]; 9202 u8 ee[0x1]; 9203 u8 reserved_at_22[0x1c]; 9204 u8 e[0x2]; 9205 9206 u8 reserved_at_40[0x40]; 9207 }; 9208 9209 struct mlx5_ifc_pamp_reg_bits { 9210 u8 reserved_at_0[0x8]; 9211 u8 opamp_group[0x8]; 9212 u8 reserved_at_10[0xc]; 9213 u8 opamp_group_type[0x4]; 9214 9215 u8 start_index[0x10]; 9216 u8 reserved_at_30[0x4]; 9217 u8 num_of_indices[0xc]; 9218 9219 u8 index_data[18][0x10]; 9220 }; 9221 9222 struct mlx5_ifc_pcmr_reg_bits { 9223 u8 reserved_at_0[0x8]; 9224 u8 local_port[0x8]; 9225 u8 reserved_at_10[0x10]; 9226 u8 entropy_force_cap[0x1]; 9227 u8 entropy_calc_cap[0x1]; 9228 u8 entropy_gre_calc_cap[0x1]; 9229 u8 reserved_at_23[0x1b]; 9230 u8 fcs_cap[0x1]; 9231 u8 reserved_at_3f[0x1]; 9232 u8 entropy_force[0x1]; 9233 u8 entropy_calc[0x1]; 9234 u8 entropy_gre_calc[0x1]; 9235 u8 reserved_at_43[0x1b]; 9236 u8 fcs_chk[0x1]; 9237 u8 reserved_at_5f[0x1]; 9238 }; 9239 9240 struct mlx5_ifc_lane_2_module_mapping_bits { 9241 u8 reserved_at_0[0x6]; 9242 u8 rx_lane[0x2]; 9243 u8 reserved_at_8[0x6]; 9244 u8 tx_lane[0x2]; 9245 u8 reserved_at_10[0x8]; 9246 u8 module[0x8]; 9247 }; 9248 9249 struct mlx5_ifc_bufferx_reg_bits { 9250 u8 reserved_at_0[0x6]; 9251 u8 lossy[0x1]; 9252 u8 epsb[0x1]; 9253 u8 reserved_at_8[0xc]; 9254 u8 size[0xc]; 9255 9256 u8 xoff_threshold[0x10]; 9257 u8 xon_threshold[0x10]; 9258 }; 9259 9260 struct mlx5_ifc_set_node_in_bits { 9261 u8 node_description[64][0x8]; 9262 }; 9263 9264 struct mlx5_ifc_register_power_settings_bits { 9265 u8 reserved_at_0[0x18]; 9266 u8 power_settings_level[0x8]; 9267 9268 u8 reserved_at_20[0x60]; 9269 }; 9270 9271 struct mlx5_ifc_register_host_endianness_bits { 9272 u8 he[0x1]; 9273 u8 reserved_at_1[0x1f]; 9274 9275 u8 reserved_at_20[0x60]; 9276 }; 9277 9278 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9279 u8 reserved_at_0[0x20]; 9280 9281 u8 mkey[0x20]; 9282 9283 u8 addressh_63_32[0x20]; 9284 9285 u8 addressl_31_0[0x20]; 9286 }; 9287 9288 struct mlx5_ifc_ud_adrs_vector_bits { 9289 u8 dc_key[0x40]; 9290 9291 u8 ext[0x1]; 9292 u8 reserved_at_41[0x7]; 9293 u8 destination_qp_dct[0x18]; 9294 9295 u8 static_rate[0x4]; 9296 u8 sl_eth_prio[0x4]; 9297 u8 fl[0x1]; 9298 u8 mlid[0x7]; 9299 u8 rlid_udp_sport[0x10]; 9300 9301 u8 reserved_at_80[0x20]; 9302 9303 u8 rmac_47_16[0x20]; 9304 9305 u8 rmac_15_0[0x10]; 9306 u8 tclass[0x8]; 9307 u8 hop_limit[0x8]; 9308 9309 u8 reserved_at_e0[0x1]; 9310 u8 grh[0x1]; 9311 u8 reserved_at_e2[0x2]; 9312 u8 src_addr_index[0x8]; 9313 u8 flow_label[0x14]; 9314 9315 u8 rgid_rip[16][0x8]; 9316 }; 9317 9318 struct mlx5_ifc_pages_req_event_bits { 9319 u8 reserved_at_0[0x10]; 9320 u8 function_id[0x10]; 9321 9322 u8 num_pages[0x20]; 9323 9324 u8 reserved_at_40[0xa0]; 9325 }; 9326 9327 struct mlx5_ifc_eqe_bits { 9328 u8 reserved_at_0[0x8]; 9329 u8 event_type[0x8]; 9330 u8 reserved_at_10[0x8]; 9331 u8 event_sub_type[0x8]; 9332 9333 u8 reserved_at_20[0xe0]; 9334 9335 union mlx5_ifc_event_auto_bits event_data; 9336 9337 u8 reserved_at_1e0[0x10]; 9338 u8 signature[0x8]; 9339 u8 reserved_at_1f8[0x7]; 9340 u8 owner[0x1]; 9341 }; 9342 9343 enum { 9344 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9345 }; 9346 9347 struct mlx5_ifc_cmd_queue_entry_bits { 9348 u8 type[0x8]; 9349 u8 reserved_at_8[0x18]; 9350 9351 u8 input_length[0x20]; 9352 9353 u8 input_mailbox_pointer_63_32[0x20]; 9354 9355 u8 input_mailbox_pointer_31_9[0x17]; 9356 u8 reserved_at_77[0x9]; 9357 9358 u8 command_input_inline_data[16][0x8]; 9359 9360 u8 command_output_inline_data[16][0x8]; 9361 9362 u8 output_mailbox_pointer_63_32[0x20]; 9363 9364 u8 output_mailbox_pointer_31_9[0x17]; 9365 u8 reserved_at_1b7[0x9]; 9366 9367 u8 output_length[0x20]; 9368 9369 u8 token[0x8]; 9370 u8 signature[0x8]; 9371 u8 reserved_at_1f0[0x8]; 9372 u8 status[0x7]; 9373 u8 ownership[0x1]; 9374 }; 9375 9376 struct mlx5_ifc_cmd_out_bits { 9377 u8 status[0x8]; 9378 u8 reserved_at_8[0x18]; 9379 9380 u8 syndrome[0x20]; 9381 9382 u8 command_output[0x20]; 9383 }; 9384 9385 struct mlx5_ifc_cmd_in_bits { 9386 u8 opcode[0x10]; 9387 u8 reserved_at_10[0x10]; 9388 9389 u8 reserved_at_20[0x10]; 9390 u8 op_mod[0x10]; 9391 9392 u8 command[][0x20]; 9393 }; 9394 9395 struct mlx5_ifc_cmd_if_box_bits { 9396 u8 mailbox_data[512][0x8]; 9397 9398 u8 reserved_at_1000[0x180]; 9399 9400 u8 next_pointer_63_32[0x20]; 9401 9402 u8 next_pointer_31_10[0x16]; 9403 u8 reserved_at_11b6[0xa]; 9404 9405 u8 block_number[0x20]; 9406 9407 u8 reserved_at_11e0[0x8]; 9408 u8 token[0x8]; 9409 u8 ctrl_signature[0x8]; 9410 u8 signature[0x8]; 9411 }; 9412 9413 struct mlx5_ifc_mtt_bits { 9414 u8 ptag_63_32[0x20]; 9415 9416 u8 ptag_31_8[0x18]; 9417 u8 reserved_at_38[0x6]; 9418 u8 wr_en[0x1]; 9419 u8 rd_en[0x1]; 9420 }; 9421 9422 struct mlx5_ifc_query_wol_rol_out_bits { 9423 u8 status[0x8]; 9424 u8 reserved_at_8[0x18]; 9425 9426 u8 syndrome[0x20]; 9427 9428 u8 reserved_at_40[0x10]; 9429 u8 rol_mode[0x8]; 9430 u8 wol_mode[0x8]; 9431 9432 u8 reserved_at_60[0x20]; 9433 }; 9434 9435 struct mlx5_ifc_query_wol_rol_in_bits { 9436 u8 opcode[0x10]; 9437 u8 reserved_at_10[0x10]; 9438 9439 u8 reserved_at_20[0x10]; 9440 u8 op_mod[0x10]; 9441 9442 u8 reserved_at_40[0x40]; 9443 }; 9444 9445 struct mlx5_ifc_set_wol_rol_out_bits { 9446 u8 status[0x8]; 9447 u8 reserved_at_8[0x18]; 9448 9449 u8 syndrome[0x20]; 9450 9451 u8 reserved_at_40[0x40]; 9452 }; 9453 9454 struct mlx5_ifc_set_wol_rol_in_bits { 9455 u8 opcode[0x10]; 9456 u8 reserved_at_10[0x10]; 9457 9458 u8 reserved_at_20[0x10]; 9459 u8 op_mod[0x10]; 9460 9461 u8 rol_mode_valid[0x1]; 9462 u8 wol_mode_valid[0x1]; 9463 u8 reserved_at_42[0xe]; 9464 u8 rol_mode[0x8]; 9465 u8 wol_mode[0x8]; 9466 9467 u8 reserved_at_60[0x20]; 9468 }; 9469 9470 enum { 9471 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9472 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9473 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9474 }; 9475 9476 enum { 9477 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9478 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9479 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9480 }; 9481 9482 enum { 9483 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9484 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9485 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9486 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9487 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9488 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9489 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9490 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9491 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9492 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9493 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9494 }; 9495 9496 struct mlx5_ifc_initial_seg_bits { 9497 u8 fw_rev_minor[0x10]; 9498 u8 fw_rev_major[0x10]; 9499 9500 u8 cmd_interface_rev[0x10]; 9501 u8 fw_rev_subminor[0x10]; 9502 9503 u8 reserved_at_40[0x40]; 9504 9505 u8 cmdq_phy_addr_63_32[0x20]; 9506 9507 u8 cmdq_phy_addr_31_12[0x14]; 9508 u8 reserved_at_b4[0x2]; 9509 u8 nic_interface[0x2]; 9510 u8 log_cmdq_size[0x4]; 9511 u8 log_cmdq_stride[0x4]; 9512 9513 u8 command_doorbell_vector[0x20]; 9514 9515 u8 reserved_at_e0[0xf00]; 9516 9517 u8 initializing[0x1]; 9518 u8 reserved_at_fe1[0x4]; 9519 u8 nic_interface_supported[0x3]; 9520 u8 embedded_cpu[0x1]; 9521 u8 reserved_at_fe9[0x17]; 9522 9523 struct mlx5_ifc_health_buffer_bits health_buffer; 9524 9525 u8 no_dram_nic_offset[0x20]; 9526 9527 u8 reserved_at_1220[0x6e40]; 9528 9529 u8 reserved_at_8060[0x1f]; 9530 u8 clear_int[0x1]; 9531 9532 u8 health_syndrome[0x8]; 9533 u8 health_counter[0x18]; 9534 9535 u8 reserved_at_80a0[0x17fc0]; 9536 }; 9537 9538 struct mlx5_ifc_mtpps_reg_bits { 9539 u8 reserved_at_0[0xc]; 9540 u8 cap_number_of_pps_pins[0x4]; 9541 u8 reserved_at_10[0x4]; 9542 u8 cap_max_num_of_pps_in_pins[0x4]; 9543 u8 reserved_at_18[0x4]; 9544 u8 cap_max_num_of_pps_out_pins[0x4]; 9545 9546 u8 reserved_at_20[0x24]; 9547 u8 cap_pin_3_mode[0x4]; 9548 u8 reserved_at_48[0x4]; 9549 u8 cap_pin_2_mode[0x4]; 9550 u8 reserved_at_50[0x4]; 9551 u8 cap_pin_1_mode[0x4]; 9552 u8 reserved_at_58[0x4]; 9553 u8 cap_pin_0_mode[0x4]; 9554 9555 u8 reserved_at_60[0x4]; 9556 u8 cap_pin_7_mode[0x4]; 9557 u8 reserved_at_68[0x4]; 9558 u8 cap_pin_6_mode[0x4]; 9559 u8 reserved_at_70[0x4]; 9560 u8 cap_pin_5_mode[0x4]; 9561 u8 reserved_at_78[0x4]; 9562 u8 cap_pin_4_mode[0x4]; 9563 9564 u8 field_select[0x20]; 9565 u8 reserved_at_a0[0x60]; 9566 9567 u8 enable[0x1]; 9568 u8 reserved_at_101[0xb]; 9569 u8 pattern[0x4]; 9570 u8 reserved_at_110[0x4]; 9571 u8 pin_mode[0x4]; 9572 u8 pin[0x8]; 9573 9574 u8 reserved_at_120[0x20]; 9575 9576 u8 time_stamp[0x40]; 9577 9578 u8 out_pulse_duration[0x10]; 9579 u8 out_periodic_adjustment[0x10]; 9580 u8 enhanced_out_periodic_adjustment[0x20]; 9581 9582 u8 reserved_at_1c0[0x20]; 9583 }; 9584 9585 struct mlx5_ifc_mtppse_reg_bits { 9586 u8 reserved_at_0[0x18]; 9587 u8 pin[0x8]; 9588 u8 event_arm[0x1]; 9589 u8 reserved_at_21[0x1b]; 9590 u8 event_generation_mode[0x4]; 9591 u8 reserved_at_40[0x40]; 9592 }; 9593 9594 struct mlx5_ifc_mcqs_reg_bits { 9595 u8 last_index_flag[0x1]; 9596 u8 reserved_at_1[0x7]; 9597 u8 fw_device[0x8]; 9598 u8 component_index[0x10]; 9599 9600 u8 reserved_at_20[0x10]; 9601 u8 identifier[0x10]; 9602 9603 u8 reserved_at_40[0x17]; 9604 u8 component_status[0x5]; 9605 u8 component_update_state[0x4]; 9606 9607 u8 last_update_state_changer_type[0x4]; 9608 u8 last_update_state_changer_host_id[0x4]; 9609 u8 reserved_at_68[0x18]; 9610 }; 9611 9612 struct mlx5_ifc_mcqi_cap_bits { 9613 u8 supported_info_bitmask[0x20]; 9614 9615 u8 component_size[0x20]; 9616 9617 u8 max_component_size[0x20]; 9618 9619 u8 log_mcda_word_size[0x4]; 9620 u8 reserved_at_64[0xc]; 9621 u8 mcda_max_write_size[0x10]; 9622 9623 u8 rd_en[0x1]; 9624 u8 reserved_at_81[0x1]; 9625 u8 match_chip_id[0x1]; 9626 u8 match_psid[0x1]; 9627 u8 check_user_timestamp[0x1]; 9628 u8 match_base_guid_mac[0x1]; 9629 u8 reserved_at_86[0x1a]; 9630 }; 9631 9632 struct mlx5_ifc_mcqi_version_bits { 9633 u8 reserved_at_0[0x2]; 9634 u8 build_time_valid[0x1]; 9635 u8 user_defined_time_valid[0x1]; 9636 u8 reserved_at_4[0x14]; 9637 u8 version_string_length[0x8]; 9638 9639 u8 version[0x20]; 9640 9641 u8 build_time[0x40]; 9642 9643 u8 user_defined_time[0x40]; 9644 9645 u8 build_tool_version[0x20]; 9646 9647 u8 reserved_at_e0[0x20]; 9648 9649 u8 version_string[92][0x8]; 9650 }; 9651 9652 struct mlx5_ifc_mcqi_activation_method_bits { 9653 u8 pending_server_ac_power_cycle[0x1]; 9654 u8 pending_server_dc_power_cycle[0x1]; 9655 u8 pending_server_reboot[0x1]; 9656 u8 pending_fw_reset[0x1]; 9657 u8 auto_activate[0x1]; 9658 u8 all_hosts_sync[0x1]; 9659 u8 device_hw_reset[0x1]; 9660 u8 reserved_at_7[0x19]; 9661 }; 9662 9663 union mlx5_ifc_mcqi_reg_data_bits { 9664 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9665 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9666 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9667 }; 9668 9669 struct mlx5_ifc_mcqi_reg_bits { 9670 u8 read_pending_component[0x1]; 9671 u8 reserved_at_1[0xf]; 9672 u8 component_index[0x10]; 9673 9674 u8 reserved_at_20[0x20]; 9675 9676 u8 reserved_at_40[0x1b]; 9677 u8 info_type[0x5]; 9678 9679 u8 info_size[0x20]; 9680 9681 u8 offset[0x20]; 9682 9683 u8 reserved_at_a0[0x10]; 9684 u8 data_size[0x10]; 9685 9686 union mlx5_ifc_mcqi_reg_data_bits data[]; 9687 }; 9688 9689 struct mlx5_ifc_mcc_reg_bits { 9690 u8 reserved_at_0[0x4]; 9691 u8 time_elapsed_since_last_cmd[0xc]; 9692 u8 reserved_at_10[0x8]; 9693 u8 instruction[0x8]; 9694 9695 u8 reserved_at_20[0x10]; 9696 u8 component_index[0x10]; 9697 9698 u8 reserved_at_40[0x8]; 9699 u8 update_handle[0x18]; 9700 9701 u8 handle_owner_type[0x4]; 9702 u8 handle_owner_host_id[0x4]; 9703 u8 reserved_at_68[0x1]; 9704 u8 control_progress[0x7]; 9705 u8 error_code[0x8]; 9706 u8 reserved_at_78[0x4]; 9707 u8 control_state[0x4]; 9708 9709 u8 component_size[0x20]; 9710 9711 u8 reserved_at_a0[0x60]; 9712 }; 9713 9714 struct mlx5_ifc_mcda_reg_bits { 9715 u8 reserved_at_0[0x8]; 9716 u8 update_handle[0x18]; 9717 9718 u8 offset[0x20]; 9719 9720 u8 reserved_at_40[0x10]; 9721 u8 size[0x10]; 9722 9723 u8 reserved_at_60[0x20]; 9724 9725 u8 data[0][0x20]; 9726 }; 9727 9728 enum { 9729 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9730 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9731 }; 9732 9733 enum { 9734 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9735 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9736 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9737 }; 9738 9739 struct mlx5_ifc_mfrl_reg_bits { 9740 u8 reserved_at_0[0x20]; 9741 9742 u8 reserved_at_20[0x2]; 9743 u8 pci_sync_for_fw_update_start[0x1]; 9744 u8 pci_sync_for_fw_update_resp[0x2]; 9745 u8 rst_type_sel[0x3]; 9746 u8 reserved_at_28[0x8]; 9747 u8 reset_type[0x8]; 9748 u8 reset_level[0x8]; 9749 }; 9750 9751 struct mlx5_ifc_mirc_reg_bits { 9752 u8 reserved_at_0[0x18]; 9753 u8 status_code[0x8]; 9754 9755 u8 reserved_at_20[0x20]; 9756 }; 9757 9758 union mlx5_ifc_ports_control_registers_document_bits { 9759 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9760 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9761 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9762 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9763 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9764 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9765 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9766 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9767 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9768 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9769 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9770 struct mlx5_ifc_paos_reg_bits paos_reg; 9771 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9772 struct mlx5_ifc_peir_reg_bits peir_reg; 9773 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9774 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9775 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9776 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9777 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9778 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9779 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9780 struct mlx5_ifc_plib_reg_bits plib_reg; 9781 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9782 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9783 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9784 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9785 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9786 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9787 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9788 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9789 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9790 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9791 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9792 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9793 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9794 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9795 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9796 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9797 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9798 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9799 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9800 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9801 struct mlx5_ifc_pude_reg_bits pude_reg; 9802 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9803 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9804 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9805 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9806 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9807 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9808 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9809 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9810 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9811 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9812 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9813 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9814 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9815 u8 reserved_at_0[0x60e0]; 9816 }; 9817 9818 union mlx5_ifc_debug_enhancements_document_bits { 9819 struct mlx5_ifc_health_buffer_bits health_buffer; 9820 u8 reserved_at_0[0x200]; 9821 }; 9822 9823 union mlx5_ifc_uplink_pci_interface_document_bits { 9824 struct mlx5_ifc_initial_seg_bits initial_seg; 9825 u8 reserved_at_0[0x20060]; 9826 }; 9827 9828 struct mlx5_ifc_set_flow_table_root_out_bits { 9829 u8 status[0x8]; 9830 u8 reserved_at_8[0x18]; 9831 9832 u8 syndrome[0x20]; 9833 9834 u8 reserved_at_40[0x40]; 9835 }; 9836 9837 struct mlx5_ifc_set_flow_table_root_in_bits { 9838 u8 opcode[0x10]; 9839 u8 reserved_at_10[0x10]; 9840 9841 u8 reserved_at_20[0x10]; 9842 u8 op_mod[0x10]; 9843 9844 u8 other_vport[0x1]; 9845 u8 reserved_at_41[0xf]; 9846 u8 vport_number[0x10]; 9847 9848 u8 reserved_at_60[0x20]; 9849 9850 u8 table_type[0x8]; 9851 u8 reserved_at_88[0x18]; 9852 9853 u8 reserved_at_a0[0x8]; 9854 u8 table_id[0x18]; 9855 9856 u8 reserved_at_c0[0x8]; 9857 u8 underlay_qpn[0x18]; 9858 u8 reserved_at_e0[0x120]; 9859 }; 9860 9861 enum { 9862 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9863 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9864 }; 9865 9866 struct mlx5_ifc_modify_flow_table_out_bits { 9867 u8 status[0x8]; 9868 u8 reserved_at_8[0x18]; 9869 9870 u8 syndrome[0x20]; 9871 9872 u8 reserved_at_40[0x40]; 9873 }; 9874 9875 struct mlx5_ifc_modify_flow_table_in_bits { 9876 u8 opcode[0x10]; 9877 u8 reserved_at_10[0x10]; 9878 9879 u8 reserved_at_20[0x10]; 9880 u8 op_mod[0x10]; 9881 9882 u8 other_vport[0x1]; 9883 u8 reserved_at_41[0xf]; 9884 u8 vport_number[0x10]; 9885 9886 u8 reserved_at_60[0x10]; 9887 u8 modify_field_select[0x10]; 9888 9889 u8 table_type[0x8]; 9890 u8 reserved_at_88[0x18]; 9891 9892 u8 reserved_at_a0[0x8]; 9893 u8 table_id[0x18]; 9894 9895 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9896 }; 9897 9898 struct mlx5_ifc_ets_tcn_config_reg_bits { 9899 u8 g[0x1]; 9900 u8 b[0x1]; 9901 u8 r[0x1]; 9902 u8 reserved_at_3[0x9]; 9903 u8 group[0x4]; 9904 u8 reserved_at_10[0x9]; 9905 u8 bw_allocation[0x7]; 9906 9907 u8 reserved_at_20[0xc]; 9908 u8 max_bw_units[0x4]; 9909 u8 reserved_at_30[0x8]; 9910 u8 max_bw_value[0x8]; 9911 }; 9912 9913 struct mlx5_ifc_ets_global_config_reg_bits { 9914 u8 reserved_at_0[0x2]; 9915 u8 r[0x1]; 9916 u8 reserved_at_3[0x1d]; 9917 9918 u8 reserved_at_20[0xc]; 9919 u8 max_bw_units[0x4]; 9920 u8 reserved_at_30[0x8]; 9921 u8 max_bw_value[0x8]; 9922 }; 9923 9924 struct mlx5_ifc_qetc_reg_bits { 9925 u8 reserved_at_0[0x8]; 9926 u8 port_number[0x8]; 9927 u8 reserved_at_10[0x30]; 9928 9929 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9930 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9931 }; 9932 9933 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9934 u8 e[0x1]; 9935 u8 reserved_at_01[0x0b]; 9936 u8 prio[0x04]; 9937 }; 9938 9939 struct mlx5_ifc_qpdpm_reg_bits { 9940 u8 reserved_at_0[0x8]; 9941 u8 local_port[0x8]; 9942 u8 reserved_at_10[0x10]; 9943 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9944 }; 9945 9946 struct mlx5_ifc_qpts_reg_bits { 9947 u8 reserved_at_0[0x8]; 9948 u8 local_port[0x8]; 9949 u8 reserved_at_10[0x2d]; 9950 u8 trust_state[0x3]; 9951 }; 9952 9953 struct mlx5_ifc_pptb_reg_bits { 9954 u8 reserved_at_0[0x2]; 9955 u8 mm[0x2]; 9956 u8 reserved_at_4[0x4]; 9957 u8 local_port[0x8]; 9958 u8 reserved_at_10[0x6]; 9959 u8 cm[0x1]; 9960 u8 um[0x1]; 9961 u8 pm[0x8]; 9962 9963 u8 prio_x_buff[0x20]; 9964 9965 u8 pm_msb[0x8]; 9966 u8 reserved_at_48[0x10]; 9967 u8 ctrl_buff[0x4]; 9968 u8 untagged_buff[0x4]; 9969 }; 9970 9971 struct mlx5_ifc_sbcam_reg_bits { 9972 u8 reserved_at_0[0x8]; 9973 u8 feature_group[0x8]; 9974 u8 reserved_at_10[0x8]; 9975 u8 access_reg_group[0x8]; 9976 9977 u8 reserved_at_20[0x20]; 9978 9979 u8 sb_access_reg_cap_mask[4][0x20]; 9980 9981 u8 reserved_at_c0[0x80]; 9982 9983 u8 sb_feature_cap_mask[4][0x20]; 9984 9985 u8 reserved_at_1c0[0x40]; 9986 9987 u8 cap_total_buffer_size[0x20]; 9988 9989 u8 cap_cell_size[0x10]; 9990 u8 cap_max_pg_buffers[0x8]; 9991 u8 cap_num_pool_supported[0x8]; 9992 9993 u8 reserved_at_240[0x8]; 9994 u8 cap_sbsr_stat_size[0x8]; 9995 u8 cap_max_tclass_data[0x8]; 9996 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 9997 }; 9998 9999 struct mlx5_ifc_pbmc_reg_bits { 10000 u8 reserved_at_0[0x8]; 10001 u8 local_port[0x8]; 10002 u8 reserved_at_10[0x10]; 10003 10004 u8 xoff_timer_value[0x10]; 10005 u8 xoff_refresh[0x10]; 10006 10007 u8 reserved_at_40[0x9]; 10008 u8 fullness_threshold[0x7]; 10009 u8 port_buffer_size[0x10]; 10010 10011 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10012 10013 u8 reserved_at_2e0[0x40]; 10014 }; 10015 10016 struct mlx5_ifc_qtct_reg_bits { 10017 u8 reserved_at_0[0x8]; 10018 u8 port_number[0x8]; 10019 u8 reserved_at_10[0xd]; 10020 u8 prio[0x3]; 10021 10022 u8 reserved_at_20[0x1d]; 10023 u8 tclass[0x3]; 10024 }; 10025 10026 struct mlx5_ifc_mcia_reg_bits { 10027 u8 l[0x1]; 10028 u8 reserved_at_1[0x7]; 10029 u8 module[0x8]; 10030 u8 reserved_at_10[0x8]; 10031 u8 status[0x8]; 10032 10033 u8 i2c_device_address[0x8]; 10034 u8 page_number[0x8]; 10035 u8 device_address[0x10]; 10036 10037 u8 reserved_at_40[0x10]; 10038 u8 size[0x10]; 10039 10040 u8 reserved_at_60[0x20]; 10041 10042 u8 dword_0[0x20]; 10043 u8 dword_1[0x20]; 10044 u8 dword_2[0x20]; 10045 u8 dword_3[0x20]; 10046 u8 dword_4[0x20]; 10047 u8 dword_5[0x20]; 10048 u8 dword_6[0x20]; 10049 u8 dword_7[0x20]; 10050 u8 dword_8[0x20]; 10051 u8 dword_9[0x20]; 10052 u8 dword_10[0x20]; 10053 u8 dword_11[0x20]; 10054 }; 10055 10056 struct mlx5_ifc_dcbx_param_bits { 10057 u8 dcbx_cee_cap[0x1]; 10058 u8 dcbx_ieee_cap[0x1]; 10059 u8 dcbx_standby_cap[0x1]; 10060 u8 reserved_at_3[0x5]; 10061 u8 port_number[0x8]; 10062 u8 reserved_at_10[0xa]; 10063 u8 max_application_table_size[6]; 10064 u8 reserved_at_20[0x15]; 10065 u8 version_oper[0x3]; 10066 u8 reserved_at_38[5]; 10067 u8 version_admin[0x3]; 10068 u8 willing_admin[0x1]; 10069 u8 reserved_at_41[0x3]; 10070 u8 pfc_cap_oper[0x4]; 10071 u8 reserved_at_48[0x4]; 10072 u8 pfc_cap_admin[0x4]; 10073 u8 reserved_at_50[0x4]; 10074 u8 num_of_tc_oper[0x4]; 10075 u8 reserved_at_58[0x4]; 10076 u8 num_of_tc_admin[0x4]; 10077 u8 remote_willing[0x1]; 10078 u8 reserved_at_61[3]; 10079 u8 remote_pfc_cap[4]; 10080 u8 reserved_at_68[0x14]; 10081 u8 remote_num_of_tc[0x4]; 10082 u8 reserved_at_80[0x18]; 10083 u8 error[0x8]; 10084 u8 reserved_at_a0[0x160]; 10085 }; 10086 10087 struct mlx5_ifc_lagc_bits { 10088 u8 reserved_at_0[0x1d]; 10089 u8 lag_state[0x3]; 10090 10091 u8 reserved_at_20[0x14]; 10092 u8 tx_remap_affinity_2[0x4]; 10093 u8 reserved_at_38[0x4]; 10094 u8 tx_remap_affinity_1[0x4]; 10095 }; 10096 10097 struct mlx5_ifc_create_lag_out_bits { 10098 u8 status[0x8]; 10099 u8 reserved_at_8[0x18]; 10100 10101 u8 syndrome[0x20]; 10102 10103 u8 reserved_at_40[0x40]; 10104 }; 10105 10106 struct mlx5_ifc_create_lag_in_bits { 10107 u8 opcode[0x10]; 10108 u8 reserved_at_10[0x10]; 10109 10110 u8 reserved_at_20[0x10]; 10111 u8 op_mod[0x10]; 10112 10113 struct mlx5_ifc_lagc_bits ctx; 10114 }; 10115 10116 struct mlx5_ifc_modify_lag_out_bits { 10117 u8 status[0x8]; 10118 u8 reserved_at_8[0x18]; 10119 10120 u8 syndrome[0x20]; 10121 10122 u8 reserved_at_40[0x40]; 10123 }; 10124 10125 struct mlx5_ifc_modify_lag_in_bits { 10126 u8 opcode[0x10]; 10127 u8 reserved_at_10[0x10]; 10128 10129 u8 reserved_at_20[0x10]; 10130 u8 op_mod[0x10]; 10131 10132 u8 reserved_at_40[0x20]; 10133 u8 field_select[0x20]; 10134 10135 struct mlx5_ifc_lagc_bits ctx; 10136 }; 10137 10138 struct mlx5_ifc_query_lag_out_bits { 10139 u8 status[0x8]; 10140 u8 reserved_at_8[0x18]; 10141 10142 u8 syndrome[0x20]; 10143 10144 struct mlx5_ifc_lagc_bits ctx; 10145 }; 10146 10147 struct mlx5_ifc_query_lag_in_bits { 10148 u8 opcode[0x10]; 10149 u8 reserved_at_10[0x10]; 10150 10151 u8 reserved_at_20[0x10]; 10152 u8 op_mod[0x10]; 10153 10154 u8 reserved_at_40[0x40]; 10155 }; 10156 10157 struct mlx5_ifc_destroy_lag_out_bits { 10158 u8 status[0x8]; 10159 u8 reserved_at_8[0x18]; 10160 10161 u8 syndrome[0x20]; 10162 10163 u8 reserved_at_40[0x40]; 10164 }; 10165 10166 struct mlx5_ifc_destroy_lag_in_bits { 10167 u8 opcode[0x10]; 10168 u8 reserved_at_10[0x10]; 10169 10170 u8 reserved_at_20[0x10]; 10171 u8 op_mod[0x10]; 10172 10173 u8 reserved_at_40[0x40]; 10174 }; 10175 10176 struct mlx5_ifc_create_vport_lag_out_bits { 10177 u8 status[0x8]; 10178 u8 reserved_at_8[0x18]; 10179 10180 u8 syndrome[0x20]; 10181 10182 u8 reserved_at_40[0x40]; 10183 }; 10184 10185 struct mlx5_ifc_create_vport_lag_in_bits { 10186 u8 opcode[0x10]; 10187 u8 reserved_at_10[0x10]; 10188 10189 u8 reserved_at_20[0x10]; 10190 u8 op_mod[0x10]; 10191 10192 u8 reserved_at_40[0x40]; 10193 }; 10194 10195 struct mlx5_ifc_destroy_vport_lag_out_bits { 10196 u8 status[0x8]; 10197 u8 reserved_at_8[0x18]; 10198 10199 u8 syndrome[0x20]; 10200 10201 u8 reserved_at_40[0x40]; 10202 }; 10203 10204 struct mlx5_ifc_destroy_vport_lag_in_bits { 10205 u8 opcode[0x10]; 10206 u8 reserved_at_10[0x10]; 10207 10208 u8 reserved_at_20[0x10]; 10209 u8 op_mod[0x10]; 10210 10211 u8 reserved_at_40[0x40]; 10212 }; 10213 10214 struct mlx5_ifc_alloc_memic_in_bits { 10215 u8 opcode[0x10]; 10216 u8 reserved_at_10[0x10]; 10217 10218 u8 reserved_at_20[0x10]; 10219 u8 op_mod[0x10]; 10220 10221 u8 reserved_at_30[0x20]; 10222 10223 u8 reserved_at_40[0x18]; 10224 u8 log_memic_addr_alignment[0x8]; 10225 10226 u8 range_start_addr[0x40]; 10227 10228 u8 range_size[0x20]; 10229 10230 u8 memic_size[0x20]; 10231 }; 10232 10233 struct mlx5_ifc_alloc_memic_out_bits { 10234 u8 status[0x8]; 10235 u8 reserved_at_8[0x18]; 10236 10237 u8 syndrome[0x20]; 10238 10239 u8 memic_start_addr[0x40]; 10240 }; 10241 10242 struct mlx5_ifc_dealloc_memic_in_bits { 10243 u8 opcode[0x10]; 10244 u8 reserved_at_10[0x10]; 10245 10246 u8 reserved_at_20[0x10]; 10247 u8 op_mod[0x10]; 10248 10249 u8 reserved_at_40[0x40]; 10250 10251 u8 memic_start_addr[0x40]; 10252 10253 u8 memic_size[0x20]; 10254 10255 u8 reserved_at_e0[0x20]; 10256 }; 10257 10258 struct mlx5_ifc_dealloc_memic_out_bits { 10259 u8 status[0x8]; 10260 u8 reserved_at_8[0x18]; 10261 10262 u8 syndrome[0x20]; 10263 10264 u8 reserved_at_40[0x40]; 10265 }; 10266 10267 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10268 u8 opcode[0x10]; 10269 u8 uid[0x10]; 10270 10271 u8 vhca_tunnel_id[0x10]; 10272 u8 obj_type[0x10]; 10273 10274 u8 obj_id[0x20]; 10275 10276 u8 reserved_at_60[0x20]; 10277 }; 10278 10279 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10280 u8 status[0x8]; 10281 u8 reserved_at_8[0x18]; 10282 10283 u8 syndrome[0x20]; 10284 10285 u8 obj_id[0x20]; 10286 10287 u8 reserved_at_60[0x20]; 10288 }; 10289 10290 struct mlx5_ifc_umem_bits { 10291 u8 reserved_at_0[0x80]; 10292 10293 u8 reserved_at_80[0x1b]; 10294 u8 log_page_size[0x5]; 10295 10296 u8 page_offset[0x20]; 10297 10298 u8 num_of_mtt[0x40]; 10299 10300 struct mlx5_ifc_mtt_bits mtt[]; 10301 }; 10302 10303 struct mlx5_ifc_uctx_bits { 10304 u8 cap[0x20]; 10305 10306 u8 reserved_at_20[0x160]; 10307 }; 10308 10309 struct mlx5_ifc_sw_icm_bits { 10310 u8 modify_field_select[0x40]; 10311 10312 u8 reserved_at_40[0x18]; 10313 u8 log_sw_icm_size[0x8]; 10314 10315 u8 reserved_at_60[0x20]; 10316 10317 u8 sw_icm_start_addr[0x40]; 10318 10319 u8 reserved_at_c0[0x140]; 10320 }; 10321 10322 struct mlx5_ifc_geneve_tlv_option_bits { 10323 u8 modify_field_select[0x40]; 10324 10325 u8 reserved_at_40[0x18]; 10326 u8 geneve_option_fte_index[0x8]; 10327 10328 u8 option_class[0x10]; 10329 u8 option_type[0x8]; 10330 u8 reserved_at_78[0x3]; 10331 u8 option_data_length[0x5]; 10332 10333 u8 reserved_at_80[0x180]; 10334 }; 10335 10336 struct mlx5_ifc_create_umem_in_bits { 10337 u8 opcode[0x10]; 10338 u8 uid[0x10]; 10339 10340 u8 reserved_at_20[0x10]; 10341 u8 op_mod[0x10]; 10342 10343 u8 reserved_at_40[0x40]; 10344 10345 struct mlx5_ifc_umem_bits umem; 10346 }; 10347 10348 struct mlx5_ifc_create_uctx_in_bits { 10349 u8 opcode[0x10]; 10350 u8 reserved_at_10[0x10]; 10351 10352 u8 reserved_at_20[0x10]; 10353 u8 op_mod[0x10]; 10354 10355 u8 reserved_at_40[0x40]; 10356 10357 struct mlx5_ifc_uctx_bits uctx; 10358 }; 10359 10360 struct mlx5_ifc_destroy_uctx_in_bits { 10361 u8 opcode[0x10]; 10362 u8 reserved_at_10[0x10]; 10363 10364 u8 reserved_at_20[0x10]; 10365 u8 op_mod[0x10]; 10366 10367 u8 reserved_at_40[0x10]; 10368 u8 uid[0x10]; 10369 10370 u8 reserved_at_60[0x20]; 10371 }; 10372 10373 struct mlx5_ifc_create_sw_icm_in_bits { 10374 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10375 struct mlx5_ifc_sw_icm_bits sw_icm; 10376 }; 10377 10378 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10379 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10380 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10381 }; 10382 10383 struct mlx5_ifc_mtrc_string_db_param_bits { 10384 u8 string_db_base_address[0x20]; 10385 10386 u8 reserved_at_20[0x8]; 10387 u8 string_db_size[0x18]; 10388 }; 10389 10390 struct mlx5_ifc_mtrc_cap_bits { 10391 u8 trace_owner[0x1]; 10392 u8 trace_to_memory[0x1]; 10393 u8 reserved_at_2[0x4]; 10394 u8 trc_ver[0x2]; 10395 u8 reserved_at_8[0x14]; 10396 u8 num_string_db[0x4]; 10397 10398 u8 first_string_trace[0x8]; 10399 u8 num_string_trace[0x8]; 10400 u8 reserved_at_30[0x28]; 10401 10402 u8 log_max_trace_buffer_size[0x8]; 10403 10404 u8 reserved_at_60[0x20]; 10405 10406 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10407 10408 u8 reserved_at_280[0x180]; 10409 }; 10410 10411 struct mlx5_ifc_mtrc_conf_bits { 10412 u8 reserved_at_0[0x1c]; 10413 u8 trace_mode[0x4]; 10414 u8 reserved_at_20[0x18]; 10415 u8 log_trace_buffer_size[0x8]; 10416 u8 trace_mkey[0x20]; 10417 u8 reserved_at_60[0x3a0]; 10418 }; 10419 10420 struct mlx5_ifc_mtrc_stdb_bits { 10421 u8 string_db_index[0x4]; 10422 u8 reserved_at_4[0x4]; 10423 u8 read_size[0x18]; 10424 u8 start_offset[0x20]; 10425 u8 string_db_data[]; 10426 }; 10427 10428 struct mlx5_ifc_mtrc_ctrl_bits { 10429 u8 trace_status[0x2]; 10430 u8 reserved_at_2[0x2]; 10431 u8 arm_event[0x1]; 10432 u8 reserved_at_5[0xb]; 10433 u8 modify_field_select[0x10]; 10434 u8 reserved_at_20[0x2b]; 10435 u8 current_timestamp52_32[0x15]; 10436 u8 current_timestamp31_0[0x20]; 10437 u8 reserved_at_80[0x180]; 10438 }; 10439 10440 struct mlx5_ifc_host_params_context_bits { 10441 u8 host_number[0x8]; 10442 u8 reserved_at_8[0x7]; 10443 u8 host_pf_disabled[0x1]; 10444 u8 host_num_of_vfs[0x10]; 10445 10446 u8 host_total_vfs[0x10]; 10447 u8 host_pci_bus[0x10]; 10448 10449 u8 reserved_at_40[0x10]; 10450 u8 host_pci_device[0x10]; 10451 10452 u8 reserved_at_60[0x10]; 10453 u8 host_pci_function[0x10]; 10454 10455 u8 reserved_at_80[0x180]; 10456 }; 10457 10458 struct mlx5_ifc_query_esw_functions_in_bits { 10459 u8 opcode[0x10]; 10460 u8 reserved_at_10[0x10]; 10461 10462 u8 reserved_at_20[0x10]; 10463 u8 op_mod[0x10]; 10464 10465 u8 reserved_at_40[0x40]; 10466 }; 10467 10468 struct mlx5_ifc_query_esw_functions_out_bits { 10469 u8 status[0x8]; 10470 u8 reserved_at_8[0x18]; 10471 10472 u8 syndrome[0x20]; 10473 10474 u8 reserved_at_40[0x40]; 10475 10476 struct mlx5_ifc_host_params_context_bits host_params_context; 10477 10478 u8 reserved_at_280[0x180]; 10479 u8 host_sf_enable[][0x40]; 10480 }; 10481 10482 struct mlx5_ifc_sf_partition_bits { 10483 u8 reserved_at_0[0x10]; 10484 u8 log_num_sf[0x8]; 10485 u8 log_sf_bar_size[0x8]; 10486 }; 10487 10488 struct mlx5_ifc_query_sf_partitions_out_bits { 10489 u8 status[0x8]; 10490 u8 reserved_at_8[0x18]; 10491 10492 u8 syndrome[0x20]; 10493 10494 u8 reserved_at_40[0x18]; 10495 u8 num_sf_partitions[0x8]; 10496 10497 u8 reserved_at_60[0x20]; 10498 10499 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10500 }; 10501 10502 struct mlx5_ifc_query_sf_partitions_in_bits { 10503 u8 opcode[0x10]; 10504 u8 reserved_at_10[0x10]; 10505 10506 u8 reserved_at_20[0x10]; 10507 u8 op_mod[0x10]; 10508 10509 u8 reserved_at_40[0x40]; 10510 }; 10511 10512 struct mlx5_ifc_dealloc_sf_out_bits { 10513 u8 status[0x8]; 10514 u8 reserved_at_8[0x18]; 10515 10516 u8 syndrome[0x20]; 10517 10518 u8 reserved_at_40[0x40]; 10519 }; 10520 10521 struct mlx5_ifc_dealloc_sf_in_bits { 10522 u8 opcode[0x10]; 10523 u8 reserved_at_10[0x10]; 10524 10525 u8 reserved_at_20[0x10]; 10526 u8 op_mod[0x10]; 10527 10528 u8 reserved_at_40[0x10]; 10529 u8 function_id[0x10]; 10530 10531 u8 reserved_at_60[0x20]; 10532 }; 10533 10534 struct mlx5_ifc_alloc_sf_out_bits { 10535 u8 status[0x8]; 10536 u8 reserved_at_8[0x18]; 10537 10538 u8 syndrome[0x20]; 10539 10540 u8 reserved_at_40[0x40]; 10541 }; 10542 10543 struct mlx5_ifc_alloc_sf_in_bits { 10544 u8 opcode[0x10]; 10545 u8 reserved_at_10[0x10]; 10546 10547 u8 reserved_at_20[0x10]; 10548 u8 op_mod[0x10]; 10549 10550 u8 reserved_at_40[0x10]; 10551 u8 function_id[0x10]; 10552 10553 u8 reserved_at_60[0x20]; 10554 }; 10555 10556 struct mlx5_ifc_affiliated_event_header_bits { 10557 u8 reserved_at_0[0x10]; 10558 u8 obj_type[0x10]; 10559 10560 u8 obj_id[0x20]; 10561 }; 10562 10563 enum { 10564 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10565 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13), 10566 }; 10567 10568 enum { 10569 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10570 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10571 }; 10572 10573 enum { 10574 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10575 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10576 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10577 }; 10578 10579 struct mlx5_ifc_ipsec_obj_bits { 10580 u8 modify_field_select[0x40]; 10581 u8 full_offload[0x1]; 10582 u8 reserved_at_41[0x1]; 10583 u8 esn_en[0x1]; 10584 u8 esn_overlap[0x1]; 10585 u8 reserved_at_44[0x2]; 10586 u8 icv_length[0x2]; 10587 u8 reserved_at_48[0x4]; 10588 u8 aso_return_reg[0x4]; 10589 u8 reserved_at_50[0x10]; 10590 10591 u8 esn_msb[0x20]; 10592 10593 u8 reserved_at_80[0x8]; 10594 u8 dekn[0x18]; 10595 10596 u8 salt[0x20]; 10597 10598 u8 implicit_iv[0x40]; 10599 10600 u8 reserved_at_100[0x700]; 10601 }; 10602 10603 struct mlx5_ifc_create_ipsec_obj_in_bits { 10604 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10605 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10606 }; 10607 10608 enum { 10609 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10610 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10611 }; 10612 10613 struct mlx5_ifc_query_ipsec_obj_out_bits { 10614 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10615 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10616 }; 10617 10618 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10619 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10620 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10621 }; 10622 10623 struct mlx5_ifc_encryption_key_obj_bits { 10624 u8 modify_field_select[0x40]; 10625 10626 u8 reserved_at_40[0x14]; 10627 u8 key_size[0x4]; 10628 u8 reserved_at_58[0x4]; 10629 u8 key_type[0x4]; 10630 10631 u8 reserved_at_60[0x8]; 10632 u8 pd[0x18]; 10633 10634 u8 reserved_at_80[0x180]; 10635 u8 key[8][0x20]; 10636 10637 u8 reserved_at_300[0x500]; 10638 }; 10639 10640 struct mlx5_ifc_create_encryption_key_in_bits { 10641 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10642 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10643 }; 10644 10645 enum { 10646 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10647 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10648 }; 10649 10650 enum { 10651 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10652 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10653 }; 10654 10655 struct mlx5_ifc_tls_static_params_bits { 10656 u8 const_2[0x2]; 10657 u8 tls_version[0x4]; 10658 u8 const_1[0x2]; 10659 u8 reserved_at_8[0x14]; 10660 u8 encryption_standard[0x4]; 10661 10662 u8 reserved_at_20[0x20]; 10663 10664 u8 initial_record_number[0x40]; 10665 10666 u8 resync_tcp_sn[0x20]; 10667 10668 u8 gcm_iv[0x20]; 10669 10670 u8 implicit_iv[0x40]; 10671 10672 u8 reserved_at_100[0x8]; 10673 u8 dek_index[0x18]; 10674 10675 u8 reserved_at_120[0xe0]; 10676 }; 10677 10678 struct mlx5_ifc_tls_progress_params_bits { 10679 u8 next_record_tcp_sn[0x20]; 10680 10681 u8 hw_resync_tcp_sn[0x20]; 10682 10683 u8 record_tracker_state[0x2]; 10684 u8 auth_state[0x2]; 10685 u8 reserved_at_44[0x4]; 10686 u8 hw_offset_record_number[0x18]; 10687 }; 10688 10689 #endif /* MLX5_IFC_H */ 10690