1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 72 }; 73 74 enum { 75 MLX5_SHARED_RESOURCE_UID = 0xffff, 76 }; 77 78 enum { 79 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 80 }; 81 82 enum { 83 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 84 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 85 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 86 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 87 }; 88 89 enum { 90 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 91 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 92 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 93 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 94 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 95 MLX5_OBJ_TYPE_MKEY = 0xff01, 96 MLX5_OBJ_TYPE_QP = 0xff02, 97 MLX5_OBJ_TYPE_PSV = 0xff03, 98 MLX5_OBJ_TYPE_RMP = 0xff04, 99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 100 MLX5_OBJ_TYPE_RQ = 0xff06, 101 MLX5_OBJ_TYPE_SQ = 0xff07, 102 MLX5_OBJ_TYPE_TIR = 0xff08, 103 MLX5_OBJ_TYPE_TIS = 0xff09, 104 MLX5_OBJ_TYPE_DCT = 0xff0a, 105 MLX5_OBJ_TYPE_XRQ = 0xff0b, 106 MLX5_OBJ_TYPE_RQT = 0xff0e, 107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 108 MLX5_OBJ_TYPE_CQ = 0xff10, 109 }; 110 111 enum { 112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 114 MLX5_CMD_OP_INIT_HCA = 0x102, 115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 116 MLX5_CMD_OP_ENABLE_HCA = 0x104, 117 MLX5_CMD_OP_DISABLE_HCA = 0x105, 118 MLX5_CMD_OP_QUERY_PAGES = 0x107, 119 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 120 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 121 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 122 MLX5_CMD_OP_SET_ISSI = 0x10b, 123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 125 MLX5_CMD_OP_ALLOC_SF = 0x113, 126 MLX5_CMD_OP_DEALLOC_SF = 0x114, 127 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 128 MLX5_CMD_OP_RESUME_VHCA = 0x116, 129 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 130 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 131 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 132 MLX5_CMD_OP_CREATE_MKEY = 0x200, 133 MLX5_CMD_OP_QUERY_MKEY = 0x201, 134 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 135 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 136 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 137 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 138 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 139 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 140 MLX5_CMD_OP_CREATE_EQ = 0x301, 141 MLX5_CMD_OP_DESTROY_EQ = 0x302, 142 MLX5_CMD_OP_QUERY_EQ = 0x303, 143 MLX5_CMD_OP_GEN_EQE = 0x304, 144 MLX5_CMD_OP_CREATE_CQ = 0x400, 145 MLX5_CMD_OP_DESTROY_CQ = 0x401, 146 MLX5_CMD_OP_QUERY_CQ = 0x402, 147 MLX5_CMD_OP_MODIFY_CQ = 0x403, 148 MLX5_CMD_OP_CREATE_QP = 0x500, 149 MLX5_CMD_OP_DESTROY_QP = 0x501, 150 MLX5_CMD_OP_RST2INIT_QP = 0x502, 151 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 152 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 153 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 154 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 155 MLX5_CMD_OP_2ERR_QP = 0x507, 156 MLX5_CMD_OP_2RST_QP = 0x50a, 157 MLX5_CMD_OP_QUERY_QP = 0x50b, 158 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 159 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 160 MLX5_CMD_OP_CREATE_PSV = 0x600, 161 MLX5_CMD_OP_DESTROY_PSV = 0x601, 162 MLX5_CMD_OP_CREATE_SRQ = 0x700, 163 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 164 MLX5_CMD_OP_QUERY_SRQ = 0x702, 165 MLX5_CMD_OP_ARM_RQ = 0x703, 166 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 167 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 168 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 169 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 170 MLX5_CMD_OP_CREATE_DCT = 0x710, 171 MLX5_CMD_OP_DESTROY_DCT = 0x711, 172 MLX5_CMD_OP_DRAIN_DCT = 0x712, 173 MLX5_CMD_OP_QUERY_DCT = 0x713, 174 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 175 MLX5_CMD_OP_CREATE_XRQ = 0x717, 176 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 177 MLX5_CMD_OP_QUERY_XRQ = 0x719, 178 MLX5_CMD_OP_ARM_XRQ = 0x71a, 179 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 180 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 181 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 182 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 183 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 184 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 185 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 186 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 187 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 188 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 189 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 190 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 191 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 192 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 194 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 195 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 197 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 198 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 199 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 200 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 201 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 202 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 203 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 204 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 205 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 206 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 207 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 208 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 209 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 210 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 211 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 212 MLX5_CMD_OP_ALLOC_PD = 0x800, 213 MLX5_CMD_OP_DEALLOC_PD = 0x801, 214 MLX5_CMD_OP_ALLOC_UAR = 0x802, 215 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 216 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 217 MLX5_CMD_OP_ACCESS_REG = 0x805, 218 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 219 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 220 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 221 MLX5_CMD_OP_MAD_IFC = 0x50d, 222 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 223 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 224 MLX5_CMD_OP_NOP = 0x80d, 225 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 226 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 227 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 228 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 229 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 230 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 231 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 232 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 233 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 234 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 235 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 236 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 237 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 238 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 239 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 240 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 241 MLX5_CMD_OP_CREATE_LAG = 0x840, 242 MLX5_CMD_OP_MODIFY_LAG = 0x841, 243 MLX5_CMD_OP_QUERY_LAG = 0x842, 244 MLX5_CMD_OP_DESTROY_LAG = 0x843, 245 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 246 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 247 MLX5_CMD_OP_CREATE_TIR = 0x900, 248 MLX5_CMD_OP_MODIFY_TIR = 0x901, 249 MLX5_CMD_OP_DESTROY_TIR = 0x902, 250 MLX5_CMD_OP_QUERY_TIR = 0x903, 251 MLX5_CMD_OP_CREATE_SQ = 0x904, 252 MLX5_CMD_OP_MODIFY_SQ = 0x905, 253 MLX5_CMD_OP_DESTROY_SQ = 0x906, 254 MLX5_CMD_OP_QUERY_SQ = 0x907, 255 MLX5_CMD_OP_CREATE_RQ = 0x908, 256 MLX5_CMD_OP_MODIFY_RQ = 0x909, 257 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 258 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 259 MLX5_CMD_OP_QUERY_RQ = 0x90b, 260 MLX5_CMD_OP_CREATE_RMP = 0x90c, 261 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 262 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 263 MLX5_CMD_OP_QUERY_RMP = 0x90f, 264 MLX5_CMD_OP_CREATE_TIS = 0x912, 265 MLX5_CMD_OP_MODIFY_TIS = 0x913, 266 MLX5_CMD_OP_DESTROY_TIS = 0x914, 267 MLX5_CMD_OP_QUERY_TIS = 0x915, 268 MLX5_CMD_OP_CREATE_RQT = 0x916, 269 MLX5_CMD_OP_MODIFY_RQT = 0x917, 270 MLX5_CMD_OP_DESTROY_RQT = 0x918, 271 MLX5_CMD_OP_QUERY_RQT = 0x919, 272 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 273 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 274 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 276 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 277 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 278 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 279 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 280 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 281 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 282 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 283 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 284 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 285 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 286 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 287 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 288 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 289 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 290 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 291 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 292 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 293 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 294 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 295 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 296 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 297 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 298 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 299 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 300 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 301 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 302 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 303 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 304 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 305 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 306 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 307 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 308 MLX5_CMD_OP_MAX 309 }; 310 311 /* Valid range for general commands that don't work over an object */ 312 enum { 313 MLX5_CMD_OP_GENERAL_START = 0xb00, 314 MLX5_CMD_OP_GENERAL_END = 0xd00, 315 }; 316 317 struct mlx5_ifc_flow_table_fields_supported_bits { 318 u8 outer_dmac[0x1]; 319 u8 outer_smac[0x1]; 320 u8 outer_ether_type[0x1]; 321 u8 outer_ip_version[0x1]; 322 u8 outer_first_prio[0x1]; 323 u8 outer_first_cfi[0x1]; 324 u8 outer_first_vid[0x1]; 325 u8 outer_ipv4_ttl[0x1]; 326 u8 outer_second_prio[0x1]; 327 u8 outer_second_cfi[0x1]; 328 u8 outer_second_vid[0x1]; 329 u8 reserved_at_b[0x1]; 330 u8 outer_sip[0x1]; 331 u8 outer_dip[0x1]; 332 u8 outer_frag[0x1]; 333 u8 outer_ip_protocol[0x1]; 334 u8 outer_ip_ecn[0x1]; 335 u8 outer_ip_dscp[0x1]; 336 u8 outer_udp_sport[0x1]; 337 u8 outer_udp_dport[0x1]; 338 u8 outer_tcp_sport[0x1]; 339 u8 outer_tcp_dport[0x1]; 340 u8 outer_tcp_flags[0x1]; 341 u8 outer_gre_protocol[0x1]; 342 u8 outer_gre_key[0x1]; 343 u8 outer_vxlan_vni[0x1]; 344 u8 outer_geneve_vni[0x1]; 345 u8 outer_geneve_oam[0x1]; 346 u8 outer_geneve_protocol_type[0x1]; 347 u8 outer_geneve_opt_len[0x1]; 348 u8 source_vhca_port[0x1]; 349 u8 source_eswitch_port[0x1]; 350 351 u8 inner_dmac[0x1]; 352 u8 inner_smac[0x1]; 353 u8 inner_ether_type[0x1]; 354 u8 inner_ip_version[0x1]; 355 u8 inner_first_prio[0x1]; 356 u8 inner_first_cfi[0x1]; 357 u8 inner_first_vid[0x1]; 358 u8 reserved_at_27[0x1]; 359 u8 inner_second_prio[0x1]; 360 u8 inner_second_cfi[0x1]; 361 u8 inner_second_vid[0x1]; 362 u8 reserved_at_2b[0x1]; 363 u8 inner_sip[0x1]; 364 u8 inner_dip[0x1]; 365 u8 inner_frag[0x1]; 366 u8 inner_ip_protocol[0x1]; 367 u8 inner_ip_ecn[0x1]; 368 u8 inner_ip_dscp[0x1]; 369 u8 inner_udp_sport[0x1]; 370 u8 inner_udp_dport[0x1]; 371 u8 inner_tcp_sport[0x1]; 372 u8 inner_tcp_dport[0x1]; 373 u8 inner_tcp_flags[0x1]; 374 u8 reserved_at_37[0x9]; 375 376 u8 geneve_tlv_option_0_data[0x1]; 377 u8 geneve_tlv_option_0_exist[0x1]; 378 u8 reserved_at_42[0x3]; 379 u8 outer_first_mpls_over_udp[0x4]; 380 u8 outer_first_mpls_over_gre[0x4]; 381 u8 inner_first_mpls[0x4]; 382 u8 outer_first_mpls[0x4]; 383 u8 reserved_at_55[0x2]; 384 u8 outer_esp_spi[0x1]; 385 u8 reserved_at_58[0x2]; 386 u8 bth_dst_qp[0x1]; 387 u8 reserved_at_5b[0x5]; 388 389 u8 reserved_at_60[0x18]; 390 u8 metadata_reg_c_7[0x1]; 391 u8 metadata_reg_c_6[0x1]; 392 u8 metadata_reg_c_5[0x1]; 393 u8 metadata_reg_c_4[0x1]; 394 u8 metadata_reg_c_3[0x1]; 395 u8 metadata_reg_c_2[0x1]; 396 u8 metadata_reg_c_1[0x1]; 397 u8 metadata_reg_c_0[0x1]; 398 }; 399 400 struct mlx5_ifc_flow_table_fields_supported_2_bits { 401 u8 reserved_at_0[0xe]; 402 u8 bth_opcode[0x1]; 403 u8 reserved_at_f[0x11]; 404 405 u8 reserved_at_20[0x60]; 406 }; 407 408 struct mlx5_ifc_flow_table_prop_layout_bits { 409 u8 ft_support[0x1]; 410 u8 reserved_at_1[0x1]; 411 u8 flow_counter[0x1]; 412 u8 flow_modify_en[0x1]; 413 u8 modify_root[0x1]; 414 u8 identified_miss_table_mode[0x1]; 415 u8 flow_table_modify[0x1]; 416 u8 reformat[0x1]; 417 u8 decap[0x1]; 418 u8 reserved_at_9[0x1]; 419 u8 pop_vlan[0x1]; 420 u8 push_vlan[0x1]; 421 u8 reserved_at_c[0x1]; 422 u8 pop_vlan_2[0x1]; 423 u8 push_vlan_2[0x1]; 424 u8 reformat_and_vlan_action[0x1]; 425 u8 reserved_at_10[0x1]; 426 u8 sw_owner[0x1]; 427 u8 reformat_l3_tunnel_to_l2[0x1]; 428 u8 reformat_l2_to_l3_tunnel[0x1]; 429 u8 reformat_and_modify_action[0x1]; 430 u8 ignore_flow_level[0x1]; 431 u8 reserved_at_16[0x1]; 432 u8 table_miss_action_domain[0x1]; 433 u8 termination_table[0x1]; 434 u8 reformat_and_fwd_to_table[0x1]; 435 u8 reserved_at_1a[0x2]; 436 u8 ipsec_encrypt[0x1]; 437 u8 ipsec_decrypt[0x1]; 438 u8 sw_owner_v2[0x1]; 439 u8 reserved_at_1f[0x1]; 440 441 u8 termination_table_raw_traffic[0x1]; 442 u8 reserved_at_21[0x1]; 443 u8 log_max_ft_size[0x6]; 444 u8 log_max_modify_header_context[0x8]; 445 u8 max_modify_header_actions[0x8]; 446 u8 max_ft_level[0x8]; 447 448 u8 reserved_at_40[0x6]; 449 u8 execute_aso[0x1]; 450 u8 reserved_at_47[0x19]; 451 452 u8 reserved_at_60[0x2]; 453 u8 reformat_insert[0x1]; 454 u8 reformat_remove[0x1]; 455 u8 macsec_encrypt[0x1]; 456 u8 macsec_decrypt[0x1]; 457 u8 reserved_at_66[0x2]; 458 u8 reformat_add_macsec[0x1]; 459 u8 reformat_remove_macsec[0x1]; 460 u8 reserved_at_6a[0xe]; 461 u8 log_max_ft_num[0x8]; 462 463 u8 reserved_at_80[0x10]; 464 u8 log_max_flow_counter[0x8]; 465 u8 log_max_destination[0x8]; 466 467 u8 reserved_at_a0[0x18]; 468 u8 log_max_flow[0x8]; 469 470 u8 reserved_at_c0[0x40]; 471 472 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 473 474 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 475 }; 476 477 struct mlx5_ifc_odp_per_transport_service_cap_bits { 478 u8 send[0x1]; 479 u8 receive[0x1]; 480 u8 write[0x1]; 481 u8 read[0x1]; 482 u8 atomic[0x1]; 483 u8 srq_receive[0x1]; 484 u8 reserved_at_6[0x1a]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 ip_version[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_at_c0[0x10]; 529 u8 ipv4_ihl[0x4]; 530 u8 reserved_at_c4[0x4]; 531 532 u8 ttl_hoplimit[0x8]; 533 534 u8 udp_sport[0x10]; 535 u8 udp_dport[0x10]; 536 537 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 538 539 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 540 }; 541 542 struct mlx5_ifc_nvgre_key_bits { 543 u8 hi[0x18]; 544 u8 lo[0x8]; 545 }; 546 547 union mlx5_ifc_gre_key_bits { 548 struct mlx5_ifc_nvgre_key_bits nvgre; 549 u8 key[0x20]; 550 }; 551 552 struct mlx5_ifc_fte_match_set_misc_bits { 553 u8 gre_c_present[0x1]; 554 u8 reserved_at_1[0x1]; 555 u8 gre_k_present[0x1]; 556 u8 gre_s_present[0x1]; 557 u8 source_vhca_port[0x4]; 558 u8 source_sqn[0x18]; 559 560 u8 source_eswitch_owner_vhca_id[0x10]; 561 u8 source_port[0x10]; 562 563 u8 outer_second_prio[0x3]; 564 u8 outer_second_cfi[0x1]; 565 u8 outer_second_vid[0xc]; 566 u8 inner_second_prio[0x3]; 567 u8 inner_second_cfi[0x1]; 568 u8 inner_second_vid[0xc]; 569 570 u8 outer_second_cvlan_tag[0x1]; 571 u8 inner_second_cvlan_tag[0x1]; 572 u8 outer_second_svlan_tag[0x1]; 573 u8 inner_second_svlan_tag[0x1]; 574 u8 reserved_at_64[0xc]; 575 u8 gre_protocol[0x10]; 576 577 union mlx5_ifc_gre_key_bits gre_key; 578 579 u8 vxlan_vni[0x18]; 580 u8 bth_opcode[0x8]; 581 582 u8 geneve_vni[0x18]; 583 u8 reserved_at_d8[0x6]; 584 u8 geneve_tlv_option_0_exist[0x1]; 585 u8 geneve_oam[0x1]; 586 587 u8 reserved_at_e0[0xc]; 588 u8 outer_ipv6_flow_label[0x14]; 589 590 u8 reserved_at_100[0xc]; 591 u8 inner_ipv6_flow_label[0x14]; 592 593 u8 reserved_at_120[0xa]; 594 u8 geneve_opt_len[0x6]; 595 u8 geneve_protocol_type[0x10]; 596 597 u8 reserved_at_140[0x8]; 598 u8 bth_dst_qp[0x18]; 599 u8 reserved_at_160[0x20]; 600 u8 outer_esp_spi[0x20]; 601 u8 reserved_at_1a0[0x60]; 602 }; 603 604 struct mlx5_ifc_fte_match_mpls_bits { 605 u8 mpls_label[0x14]; 606 u8 mpls_exp[0x3]; 607 u8 mpls_s_bos[0x1]; 608 u8 mpls_ttl[0x8]; 609 }; 610 611 struct mlx5_ifc_fte_match_set_misc2_bits { 612 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 613 614 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 615 616 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 617 618 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 619 620 u8 metadata_reg_c_7[0x20]; 621 622 u8 metadata_reg_c_6[0x20]; 623 624 u8 metadata_reg_c_5[0x20]; 625 626 u8 metadata_reg_c_4[0x20]; 627 628 u8 metadata_reg_c_3[0x20]; 629 630 u8 metadata_reg_c_2[0x20]; 631 632 u8 metadata_reg_c_1[0x20]; 633 634 u8 metadata_reg_c_0[0x20]; 635 636 u8 metadata_reg_a[0x20]; 637 638 u8 reserved_at_1a0[0x8]; 639 640 u8 macsec_syndrome[0x8]; 641 642 u8 reserved_at_1b0[0x50]; 643 }; 644 645 struct mlx5_ifc_fte_match_set_misc3_bits { 646 u8 inner_tcp_seq_num[0x20]; 647 648 u8 outer_tcp_seq_num[0x20]; 649 650 u8 inner_tcp_ack_num[0x20]; 651 652 u8 outer_tcp_ack_num[0x20]; 653 654 u8 reserved_at_80[0x8]; 655 u8 outer_vxlan_gpe_vni[0x18]; 656 657 u8 outer_vxlan_gpe_next_protocol[0x8]; 658 u8 outer_vxlan_gpe_flags[0x8]; 659 u8 reserved_at_b0[0x10]; 660 661 u8 icmp_header_data[0x20]; 662 663 u8 icmpv6_header_data[0x20]; 664 665 u8 icmp_type[0x8]; 666 u8 icmp_code[0x8]; 667 u8 icmpv6_type[0x8]; 668 u8 icmpv6_code[0x8]; 669 670 u8 geneve_tlv_option_0_data[0x20]; 671 672 u8 gtpu_teid[0x20]; 673 674 u8 gtpu_msg_type[0x8]; 675 u8 gtpu_msg_flags[0x8]; 676 u8 reserved_at_170[0x10]; 677 678 u8 gtpu_dw_2[0x20]; 679 680 u8 gtpu_first_ext_dw_0[0x20]; 681 682 u8 gtpu_dw_0[0x20]; 683 684 u8 reserved_at_1e0[0x20]; 685 }; 686 687 struct mlx5_ifc_fte_match_set_misc4_bits { 688 u8 prog_sample_field_value_0[0x20]; 689 690 u8 prog_sample_field_id_0[0x20]; 691 692 u8 prog_sample_field_value_1[0x20]; 693 694 u8 prog_sample_field_id_1[0x20]; 695 696 u8 prog_sample_field_value_2[0x20]; 697 698 u8 prog_sample_field_id_2[0x20]; 699 700 u8 prog_sample_field_value_3[0x20]; 701 702 u8 prog_sample_field_id_3[0x20]; 703 704 u8 reserved_at_100[0x100]; 705 }; 706 707 struct mlx5_ifc_fte_match_set_misc5_bits { 708 u8 macsec_tag_0[0x20]; 709 710 u8 macsec_tag_1[0x20]; 711 712 u8 macsec_tag_2[0x20]; 713 714 u8 macsec_tag_3[0x20]; 715 716 u8 tunnel_header_0[0x20]; 717 718 u8 tunnel_header_1[0x20]; 719 720 u8 tunnel_header_2[0x20]; 721 722 u8 tunnel_header_3[0x20]; 723 724 u8 reserved_at_100[0x100]; 725 }; 726 727 struct mlx5_ifc_cmd_pas_bits { 728 u8 pa_h[0x20]; 729 730 u8 pa_l[0x14]; 731 u8 reserved_at_34[0xc]; 732 }; 733 734 struct mlx5_ifc_uint64_bits { 735 u8 hi[0x20]; 736 737 u8 lo[0x20]; 738 }; 739 740 enum { 741 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 742 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 743 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 744 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 745 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 746 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 747 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 748 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 749 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 750 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 751 }; 752 753 struct mlx5_ifc_ads_bits { 754 u8 fl[0x1]; 755 u8 free_ar[0x1]; 756 u8 reserved_at_2[0xe]; 757 u8 pkey_index[0x10]; 758 759 u8 reserved_at_20[0x8]; 760 u8 grh[0x1]; 761 u8 mlid[0x7]; 762 u8 rlid[0x10]; 763 764 u8 ack_timeout[0x5]; 765 u8 reserved_at_45[0x3]; 766 u8 src_addr_index[0x8]; 767 u8 reserved_at_50[0x4]; 768 u8 stat_rate[0x4]; 769 u8 hop_limit[0x8]; 770 771 u8 reserved_at_60[0x4]; 772 u8 tclass[0x8]; 773 u8 flow_label[0x14]; 774 775 u8 rgid_rip[16][0x8]; 776 777 u8 reserved_at_100[0x4]; 778 u8 f_dscp[0x1]; 779 u8 f_ecn[0x1]; 780 u8 reserved_at_106[0x1]; 781 u8 f_eth_prio[0x1]; 782 u8 ecn[0x2]; 783 u8 dscp[0x6]; 784 u8 udp_sport[0x10]; 785 786 u8 dei_cfi[0x1]; 787 u8 eth_prio[0x3]; 788 u8 sl[0x4]; 789 u8 vhca_port_num[0x8]; 790 u8 rmac_47_32[0x10]; 791 792 u8 rmac_31_0[0x20]; 793 }; 794 795 struct mlx5_ifc_flow_table_nic_cap_bits { 796 u8 nic_rx_multi_path_tirs[0x1]; 797 u8 nic_rx_multi_path_tirs_fts[0x1]; 798 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 799 u8 reserved_at_3[0x4]; 800 u8 sw_owner_reformat_supported[0x1]; 801 u8 reserved_at_8[0x18]; 802 803 u8 encap_general_header[0x1]; 804 u8 reserved_at_21[0xa]; 805 u8 log_max_packet_reformat_context[0x5]; 806 u8 reserved_at_30[0x6]; 807 u8 max_encap_header_size[0xa]; 808 u8 reserved_at_40[0x1c0]; 809 810 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 811 812 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 813 814 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 815 816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 821 822 u8 reserved_at_e00[0x700]; 823 824 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 825 826 u8 reserved_at_1580[0x280]; 827 828 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 829 830 u8 reserved_at_1880[0x780]; 831 832 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 833 834 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 835 836 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 837 838 u8 reserved_at_20c0[0x5f40]; 839 }; 840 841 struct mlx5_ifc_port_selection_cap_bits { 842 u8 reserved_at_0[0x10]; 843 u8 port_select_flow_table[0x1]; 844 u8 reserved_at_11[0x1]; 845 u8 port_select_flow_table_bypass[0x1]; 846 u8 reserved_at_13[0xd]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 851 852 u8 reserved_at_400[0x7c00]; 853 }; 854 855 enum { 856 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 857 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 858 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 859 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 860 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 861 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 862 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 863 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 864 }; 865 866 struct mlx5_ifc_flow_table_eswitch_cap_bits { 867 u8 fdb_to_vport_reg_c_id[0x8]; 868 u8 reserved_at_8[0xd]; 869 u8 fdb_modify_header_fwd_to_table[0x1]; 870 u8 fdb_ipv4_ttl_modify[0x1]; 871 u8 flow_source[0x1]; 872 u8 reserved_at_18[0x2]; 873 u8 multi_fdb_encap[0x1]; 874 u8 egress_acl_forward_to_vport[0x1]; 875 u8 fdb_multi_path_to_table[0x1]; 876 u8 reserved_at_1d[0x3]; 877 878 u8 reserved_at_20[0x1e0]; 879 880 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 881 882 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 883 884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 885 886 u8 reserved_at_800[0x1000]; 887 888 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 889 890 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 891 892 u8 sw_steering_uplink_icm_address_rx[0x40]; 893 894 u8 sw_steering_uplink_icm_address_tx[0x40]; 895 896 u8 reserved_at_1900[0x6700]; 897 }; 898 899 enum { 900 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 901 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 902 }; 903 904 struct mlx5_ifc_e_switch_cap_bits { 905 u8 vport_svlan_strip[0x1]; 906 u8 vport_cvlan_strip[0x1]; 907 u8 vport_svlan_insert[0x1]; 908 u8 vport_cvlan_insert_if_not_exist[0x1]; 909 u8 vport_cvlan_insert_overwrite[0x1]; 910 u8 reserved_at_5[0x2]; 911 u8 esw_shared_ingress_acl[0x1]; 912 u8 esw_uplink_ingress_acl[0x1]; 913 u8 root_ft_on_other_esw[0x1]; 914 u8 reserved_at_a[0xf]; 915 u8 esw_functions_changed[0x1]; 916 u8 reserved_at_1a[0x1]; 917 u8 ecpf_vport_exists[0x1]; 918 u8 counter_eswitch_affinity[0x1]; 919 u8 merged_eswitch[0x1]; 920 u8 nic_vport_node_guid_modify[0x1]; 921 u8 nic_vport_port_guid_modify[0x1]; 922 923 u8 vxlan_encap_decap[0x1]; 924 u8 nvgre_encap_decap[0x1]; 925 u8 reserved_at_22[0x1]; 926 u8 log_max_fdb_encap_uplink[0x5]; 927 u8 reserved_at_21[0x3]; 928 u8 log_max_packet_reformat_context[0x5]; 929 u8 reserved_2b[0x6]; 930 u8 max_encap_header_size[0xa]; 931 932 u8 reserved_at_40[0xb]; 933 u8 log_max_esw_sf[0x5]; 934 u8 esw_sf_base_id[0x10]; 935 936 u8 reserved_at_60[0x7a0]; 937 938 }; 939 940 struct mlx5_ifc_qos_cap_bits { 941 u8 packet_pacing[0x1]; 942 u8 esw_scheduling[0x1]; 943 u8 esw_bw_share[0x1]; 944 u8 esw_rate_limit[0x1]; 945 u8 reserved_at_4[0x1]; 946 u8 packet_pacing_burst_bound[0x1]; 947 u8 packet_pacing_typical_size[0x1]; 948 u8 reserved_at_7[0x1]; 949 u8 nic_sq_scheduling[0x1]; 950 u8 nic_bw_share[0x1]; 951 u8 nic_rate_limit[0x1]; 952 u8 packet_pacing_uid[0x1]; 953 u8 log_esw_max_sched_depth[0x4]; 954 u8 reserved_at_10[0x10]; 955 956 u8 reserved_at_20[0xb]; 957 u8 log_max_qos_nic_queue_group[0x5]; 958 u8 reserved_at_30[0x10]; 959 960 u8 packet_pacing_max_rate[0x20]; 961 962 u8 packet_pacing_min_rate[0x20]; 963 964 u8 reserved_at_80[0x10]; 965 u8 packet_pacing_rate_table_size[0x10]; 966 967 u8 esw_element_type[0x10]; 968 u8 esw_tsar_type[0x10]; 969 970 u8 reserved_at_c0[0x10]; 971 u8 max_qos_para_vport[0x10]; 972 973 u8 max_tsar_bw_share[0x20]; 974 975 u8 reserved_at_100[0x20]; 976 977 u8 reserved_at_120[0x3]; 978 u8 log_meter_aso_granularity[0x5]; 979 u8 reserved_at_128[0x3]; 980 u8 log_meter_aso_max_alloc[0x5]; 981 u8 reserved_at_130[0x3]; 982 u8 log_max_num_meter_aso[0x5]; 983 u8 reserved_at_138[0x8]; 984 985 u8 reserved_at_140[0x6c0]; 986 }; 987 988 struct mlx5_ifc_debug_cap_bits { 989 u8 core_dump_general[0x1]; 990 u8 core_dump_qp[0x1]; 991 u8 reserved_at_2[0x7]; 992 u8 resource_dump[0x1]; 993 u8 reserved_at_a[0x16]; 994 995 u8 reserved_at_20[0x2]; 996 u8 stall_detect[0x1]; 997 u8 reserved_at_23[0x1d]; 998 999 u8 reserved_at_40[0x7c0]; 1000 }; 1001 1002 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1003 u8 csum_cap[0x1]; 1004 u8 vlan_cap[0x1]; 1005 u8 lro_cap[0x1]; 1006 u8 lro_psh_flag[0x1]; 1007 u8 lro_time_stamp[0x1]; 1008 u8 reserved_at_5[0x2]; 1009 u8 wqe_vlan_insert[0x1]; 1010 u8 self_lb_en_modifiable[0x1]; 1011 u8 reserved_at_9[0x2]; 1012 u8 max_lso_cap[0x5]; 1013 u8 multi_pkt_send_wqe[0x2]; 1014 u8 wqe_inline_mode[0x2]; 1015 u8 rss_ind_tbl_cap[0x4]; 1016 u8 reg_umr_sq[0x1]; 1017 u8 scatter_fcs[0x1]; 1018 u8 enhanced_multi_pkt_send_wqe[0x1]; 1019 u8 tunnel_lso_const_out_ip_id[0x1]; 1020 u8 tunnel_lro_gre[0x1]; 1021 u8 tunnel_lro_vxlan[0x1]; 1022 u8 tunnel_stateless_gre[0x1]; 1023 u8 tunnel_stateless_vxlan[0x1]; 1024 1025 u8 swp[0x1]; 1026 u8 swp_csum[0x1]; 1027 u8 swp_lso[0x1]; 1028 u8 cqe_checksum_full[0x1]; 1029 u8 tunnel_stateless_geneve_tx[0x1]; 1030 u8 tunnel_stateless_mpls_over_udp[0x1]; 1031 u8 tunnel_stateless_mpls_over_gre[0x1]; 1032 u8 tunnel_stateless_vxlan_gpe[0x1]; 1033 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1034 u8 tunnel_stateless_ip_over_ip[0x1]; 1035 u8 insert_trailer[0x1]; 1036 u8 reserved_at_2b[0x1]; 1037 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1038 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1039 u8 reserved_at_2e[0x2]; 1040 u8 max_vxlan_udp_ports[0x8]; 1041 u8 reserved_at_38[0x6]; 1042 u8 max_geneve_opt_len[0x1]; 1043 u8 tunnel_stateless_geneve_rx[0x1]; 1044 1045 u8 reserved_at_40[0x10]; 1046 u8 lro_min_mss_size[0x10]; 1047 1048 u8 reserved_at_60[0x120]; 1049 1050 u8 lro_timer_supported_periods[4][0x20]; 1051 1052 u8 reserved_at_200[0x600]; 1053 }; 1054 1055 enum { 1056 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1057 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1058 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1059 }; 1060 1061 struct mlx5_ifc_roce_cap_bits { 1062 u8 roce_apm[0x1]; 1063 u8 reserved_at_1[0x3]; 1064 u8 sw_r_roce_src_udp_port[0x1]; 1065 u8 fl_rc_qp_when_roce_disabled[0x1]; 1066 u8 fl_rc_qp_when_roce_enabled[0x1]; 1067 u8 reserved_at_7[0x17]; 1068 u8 qp_ts_format[0x2]; 1069 1070 u8 reserved_at_20[0x60]; 1071 1072 u8 reserved_at_80[0xc]; 1073 u8 l3_type[0x4]; 1074 u8 reserved_at_90[0x8]; 1075 u8 roce_version[0x8]; 1076 1077 u8 reserved_at_a0[0x10]; 1078 u8 r_roce_dest_udp_port[0x10]; 1079 1080 u8 r_roce_max_src_udp_port[0x10]; 1081 u8 r_roce_min_src_udp_port[0x10]; 1082 1083 u8 reserved_at_e0[0x10]; 1084 u8 roce_address_table_size[0x10]; 1085 1086 u8 reserved_at_100[0x700]; 1087 }; 1088 1089 struct mlx5_ifc_sync_steering_in_bits { 1090 u8 opcode[0x10]; 1091 u8 uid[0x10]; 1092 1093 u8 reserved_at_20[0x10]; 1094 u8 op_mod[0x10]; 1095 1096 u8 reserved_at_40[0xc0]; 1097 }; 1098 1099 struct mlx5_ifc_sync_steering_out_bits { 1100 u8 status[0x8]; 1101 u8 reserved_at_8[0x18]; 1102 1103 u8 syndrome[0x20]; 1104 1105 u8 reserved_at_40[0x40]; 1106 }; 1107 1108 struct mlx5_ifc_device_mem_cap_bits { 1109 u8 memic[0x1]; 1110 u8 reserved_at_1[0x1f]; 1111 1112 u8 reserved_at_20[0xb]; 1113 u8 log_min_memic_alloc_size[0x5]; 1114 u8 reserved_at_30[0x8]; 1115 u8 log_max_memic_addr_alignment[0x8]; 1116 1117 u8 memic_bar_start_addr[0x40]; 1118 1119 u8 memic_bar_size[0x20]; 1120 1121 u8 max_memic_size[0x20]; 1122 1123 u8 steering_sw_icm_start_address[0x40]; 1124 1125 u8 reserved_at_100[0x8]; 1126 u8 log_header_modify_sw_icm_size[0x8]; 1127 u8 reserved_at_110[0x2]; 1128 u8 log_sw_icm_alloc_granularity[0x6]; 1129 u8 log_steering_sw_icm_size[0x8]; 1130 1131 u8 reserved_at_120[0x18]; 1132 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1133 1134 u8 header_modify_sw_icm_start_address[0x40]; 1135 1136 u8 reserved_at_180[0x40]; 1137 1138 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1139 1140 u8 memic_operations[0x20]; 1141 1142 u8 reserved_at_220[0x5e0]; 1143 }; 1144 1145 struct mlx5_ifc_device_event_cap_bits { 1146 u8 user_affiliated_events[4][0x40]; 1147 1148 u8 user_unaffiliated_events[4][0x40]; 1149 }; 1150 1151 struct mlx5_ifc_virtio_emulation_cap_bits { 1152 u8 desc_tunnel_offload_type[0x1]; 1153 u8 eth_frame_offload_type[0x1]; 1154 u8 virtio_version_1_0[0x1]; 1155 u8 device_features_bits_mask[0xd]; 1156 u8 event_mode[0x8]; 1157 u8 virtio_queue_type[0x8]; 1158 1159 u8 max_tunnel_desc[0x10]; 1160 u8 reserved_at_30[0x3]; 1161 u8 log_doorbell_stride[0x5]; 1162 u8 reserved_at_38[0x3]; 1163 u8 log_doorbell_bar_size[0x5]; 1164 1165 u8 doorbell_bar_offset[0x40]; 1166 1167 u8 max_emulated_devices[0x8]; 1168 u8 max_num_virtio_queues[0x18]; 1169 1170 u8 reserved_at_a0[0x60]; 1171 1172 u8 umem_1_buffer_param_a[0x20]; 1173 1174 u8 umem_1_buffer_param_b[0x20]; 1175 1176 u8 umem_2_buffer_param_a[0x20]; 1177 1178 u8 umem_2_buffer_param_b[0x20]; 1179 1180 u8 umem_3_buffer_param_a[0x20]; 1181 1182 u8 umem_3_buffer_param_b[0x20]; 1183 1184 u8 reserved_at_1c0[0x640]; 1185 }; 1186 1187 enum { 1188 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1189 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1190 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1191 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1192 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1193 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1197 }; 1198 1199 enum { 1200 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1203 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1204 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1205 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1209 }; 1210 1211 struct mlx5_ifc_atomic_caps_bits { 1212 u8 reserved_at_0[0x40]; 1213 1214 u8 atomic_req_8B_endianness_mode[0x2]; 1215 u8 reserved_at_42[0x4]; 1216 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1217 1218 u8 reserved_at_47[0x19]; 1219 1220 u8 reserved_at_60[0x20]; 1221 1222 u8 reserved_at_80[0x10]; 1223 u8 atomic_operations[0x10]; 1224 1225 u8 reserved_at_a0[0x10]; 1226 u8 atomic_size_qp[0x10]; 1227 1228 u8 reserved_at_c0[0x10]; 1229 u8 atomic_size_dc[0x10]; 1230 1231 u8 reserved_at_e0[0x720]; 1232 }; 1233 1234 struct mlx5_ifc_odp_cap_bits { 1235 u8 reserved_at_0[0x40]; 1236 1237 u8 sig[0x1]; 1238 u8 reserved_at_41[0x1f]; 1239 1240 u8 reserved_at_60[0x20]; 1241 1242 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1243 1244 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1245 1246 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1247 1248 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1249 1250 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1251 1252 u8 reserved_at_120[0x6E0]; 1253 }; 1254 1255 struct mlx5_ifc_calc_op { 1256 u8 reserved_at_0[0x10]; 1257 u8 reserved_at_10[0x9]; 1258 u8 op_swap_endianness[0x1]; 1259 u8 op_min[0x1]; 1260 u8 op_xor[0x1]; 1261 u8 op_or[0x1]; 1262 u8 op_and[0x1]; 1263 u8 op_max[0x1]; 1264 u8 op_add[0x1]; 1265 }; 1266 1267 struct mlx5_ifc_vector_calc_cap_bits { 1268 u8 calc_matrix[0x1]; 1269 u8 reserved_at_1[0x1f]; 1270 u8 reserved_at_20[0x8]; 1271 u8 max_vec_count[0x8]; 1272 u8 reserved_at_30[0xd]; 1273 u8 max_chunk_size[0x3]; 1274 struct mlx5_ifc_calc_op calc0; 1275 struct mlx5_ifc_calc_op calc1; 1276 struct mlx5_ifc_calc_op calc2; 1277 struct mlx5_ifc_calc_op calc3; 1278 1279 u8 reserved_at_c0[0x720]; 1280 }; 1281 1282 struct mlx5_ifc_tls_cap_bits { 1283 u8 tls_1_2_aes_gcm_128[0x1]; 1284 u8 tls_1_3_aes_gcm_128[0x1]; 1285 u8 tls_1_2_aes_gcm_256[0x1]; 1286 u8 tls_1_3_aes_gcm_256[0x1]; 1287 u8 reserved_at_4[0x1c]; 1288 1289 u8 reserved_at_20[0x7e0]; 1290 }; 1291 1292 struct mlx5_ifc_ipsec_cap_bits { 1293 u8 ipsec_full_offload[0x1]; 1294 u8 ipsec_crypto_offload[0x1]; 1295 u8 ipsec_esn[0x1]; 1296 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1297 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1298 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1299 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1300 u8 reserved_at_7[0x4]; 1301 u8 log_max_ipsec_offload[0x5]; 1302 u8 reserved_at_10[0x10]; 1303 1304 u8 min_log_ipsec_full_replay_window[0x8]; 1305 u8 max_log_ipsec_full_replay_window[0x8]; 1306 u8 reserved_at_30[0x7d0]; 1307 }; 1308 1309 struct mlx5_ifc_macsec_cap_bits { 1310 u8 macsec_epn[0x1]; 1311 u8 reserved_at_1[0x2]; 1312 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1313 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1314 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1315 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1316 u8 reserved_at_7[0x4]; 1317 u8 log_max_macsec_offload[0x5]; 1318 u8 reserved_at_10[0x10]; 1319 1320 u8 min_log_macsec_full_replay_window[0x8]; 1321 u8 max_log_macsec_full_replay_window[0x8]; 1322 u8 reserved_at_30[0x10]; 1323 1324 u8 reserved_at_40[0x7c0]; 1325 }; 1326 1327 enum { 1328 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1329 MLX5_WQ_TYPE_CYCLIC = 0x1, 1330 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1331 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1332 }; 1333 1334 enum { 1335 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1336 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1337 }; 1338 1339 enum { 1340 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1341 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1342 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1343 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1344 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1345 }; 1346 1347 enum { 1348 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1349 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1350 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1351 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1352 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1353 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1354 }; 1355 1356 enum { 1357 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1358 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1359 }; 1360 1361 enum { 1362 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1363 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1364 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1365 }; 1366 1367 enum { 1368 MLX5_CAP_PORT_TYPE_IB = 0x0, 1369 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1370 }; 1371 1372 enum { 1373 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1374 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1375 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1376 }; 1377 1378 enum { 1379 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1380 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1381 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1382 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1383 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1384 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1385 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1386 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1387 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1388 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1389 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1390 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1391 }; 1392 1393 enum { 1394 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1395 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1396 }; 1397 1398 #define MLX5_FC_BULK_SIZE_FACTOR 128 1399 1400 enum mlx5_fc_bulk_alloc_bitmask { 1401 MLX5_FC_BULK_128 = (1 << 0), 1402 MLX5_FC_BULK_256 = (1 << 1), 1403 MLX5_FC_BULK_512 = (1 << 2), 1404 MLX5_FC_BULK_1024 = (1 << 3), 1405 MLX5_FC_BULK_2048 = (1 << 4), 1406 MLX5_FC_BULK_4096 = (1 << 5), 1407 MLX5_FC_BULK_8192 = (1 << 6), 1408 MLX5_FC_BULK_16384 = (1 << 7), 1409 }; 1410 1411 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1412 1413 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1414 1415 enum { 1416 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1417 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1418 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1419 }; 1420 1421 struct mlx5_ifc_cmd_hca_cap_bits { 1422 u8 reserved_at_0[0x10]; 1423 u8 shared_object_to_user_object_allowed[0x1]; 1424 u8 reserved_at_13[0xe]; 1425 u8 vhca_resource_manager[0x1]; 1426 1427 u8 hca_cap_2[0x1]; 1428 u8 create_lag_when_not_master_up[0x1]; 1429 u8 dtor[0x1]; 1430 u8 event_on_vhca_state_teardown_request[0x1]; 1431 u8 event_on_vhca_state_in_use[0x1]; 1432 u8 event_on_vhca_state_active[0x1]; 1433 u8 event_on_vhca_state_allocated[0x1]; 1434 u8 event_on_vhca_state_invalid[0x1]; 1435 u8 reserved_at_28[0x8]; 1436 u8 vhca_id[0x10]; 1437 1438 u8 reserved_at_40[0x40]; 1439 1440 u8 log_max_srq_sz[0x8]; 1441 u8 log_max_qp_sz[0x8]; 1442 u8 event_cap[0x1]; 1443 u8 reserved_at_91[0x2]; 1444 u8 isolate_vl_tc_new[0x1]; 1445 u8 reserved_at_94[0x4]; 1446 u8 prio_tag_required[0x1]; 1447 u8 reserved_at_99[0x2]; 1448 u8 log_max_qp[0x5]; 1449 1450 u8 reserved_at_a0[0x3]; 1451 u8 ece_support[0x1]; 1452 u8 reserved_at_a4[0x5]; 1453 u8 reg_c_preserve[0x1]; 1454 u8 reserved_at_aa[0x1]; 1455 u8 log_max_srq[0x5]; 1456 u8 reserved_at_b0[0x1]; 1457 u8 uplink_follow[0x1]; 1458 u8 ts_cqe_to_dest_cqn[0x1]; 1459 u8 reserved_at_b3[0x7]; 1460 u8 shampo[0x1]; 1461 u8 reserved_at_bb[0x5]; 1462 1463 u8 max_sgl_for_optimized_performance[0x8]; 1464 u8 log_max_cq_sz[0x8]; 1465 u8 relaxed_ordering_write_umr[0x1]; 1466 u8 relaxed_ordering_read_umr[0x1]; 1467 u8 reserved_at_d2[0x7]; 1468 u8 virtio_net_device_emualtion_manager[0x1]; 1469 u8 virtio_blk_device_emualtion_manager[0x1]; 1470 u8 log_max_cq[0x5]; 1471 1472 u8 log_max_eq_sz[0x8]; 1473 u8 relaxed_ordering_write[0x1]; 1474 u8 relaxed_ordering_read[0x1]; 1475 u8 log_max_mkey[0x6]; 1476 u8 reserved_at_f0[0x8]; 1477 u8 dump_fill_mkey[0x1]; 1478 u8 reserved_at_f9[0x2]; 1479 u8 fast_teardown[0x1]; 1480 u8 log_max_eq[0x4]; 1481 1482 u8 max_indirection[0x8]; 1483 u8 fixed_buffer_size[0x1]; 1484 u8 log_max_mrw_sz[0x7]; 1485 u8 force_teardown[0x1]; 1486 u8 reserved_at_111[0x1]; 1487 u8 log_max_bsf_list_size[0x6]; 1488 u8 umr_extended_translation_offset[0x1]; 1489 u8 null_mkey[0x1]; 1490 u8 log_max_klm_list_size[0x6]; 1491 1492 u8 reserved_at_120[0xa]; 1493 u8 log_max_ra_req_dc[0x6]; 1494 u8 reserved_at_130[0x9]; 1495 u8 vnic_env_cq_overrun[0x1]; 1496 u8 log_max_ra_res_dc[0x6]; 1497 1498 u8 reserved_at_140[0x5]; 1499 u8 release_all_pages[0x1]; 1500 u8 must_not_use[0x1]; 1501 u8 reserved_at_147[0x2]; 1502 u8 roce_accl[0x1]; 1503 u8 log_max_ra_req_qp[0x6]; 1504 u8 reserved_at_150[0xa]; 1505 u8 log_max_ra_res_qp[0x6]; 1506 1507 u8 end_pad[0x1]; 1508 u8 cc_query_allowed[0x1]; 1509 u8 cc_modify_allowed[0x1]; 1510 u8 start_pad[0x1]; 1511 u8 cache_line_128byte[0x1]; 1512 u8 reserved_at_165[0x4]; 1513 u8 rts2rts_qp_counters_set_id[0x1]; 1514 u8 reserved_at_16a[0x2]; 1515 u8 vnic_env_int_rq_oob[0x1]; 1516 u8 sbcam_reg[0x1]; 1517 u8 reserved_at_16e[0x1]; 1518 u8 qcam_reg[0x1]; 1519 u8 gid_table_size[0x10]; 1520 1521 u8 out_of_seq_cnt[0x1]; 1522 u8 vport_counters[0x1]; 1523 u8 retransmission_q_counters[0x1]; 1524 u8 debug[0x1]; 1525 u8 modify_rq_counter_set_id[0x1]; 1526 u8 rq_delay_drop[0x1]; 1527 u8 max_qp_cnt[0xa]; 1528 u8 pkey_table_size[0x10]; 1529 1530 u8 vport_group_manager[0x1]; 1531 u8 vhca_group_manager[0x1]; 1532 u8 ib_virt[0x1]; 1533 u8 eth_virt[0x1]; 1534 u8 vnic_env_queue_counters[0x1]; 1535 u8 ets[0x1]; 1536 u8 nic_flow_table[0x1]; 1537 u8 eswitch_manager[0x1]; 1538 u8 device_memory[0x1]; 1539 u8 mcam_reg[0x1]; 1540 u8 pcam_reg[0x1]; 1541 u8 local_ca_ack_delay[0x5]; 1542 u8 port_module_event[0x1]; 1543 u8 enhanced_error_q_counters[0x1]; 1544 u8 ports_check[0x1]; 1545 u8 reserved_at_1b3[0x1]; 1546 u8 disable_link_up[0x1]; 1547 u8 beacon_led[0x1]; 1548 u8 port_type[0x2]; 1549 u8 num_ports[0x8]; 1550 1551 u8 reserved_at_1c0[0x1]; 1552 u8 pps[0x1]; 1553 u8 pps_modify[0x1]; 1554 u8 log_max_msg[0x5]; 1555 u8 reserved_at_1c8[0x4]; 1556 u8 max_tc[0x4]; 1557 u8 temp_warn_event[0x1]; 1558 u8 dcbx[0x1]; 1559 u8 general_notification_event[0x1]; 1560 u8 reserved_at_1d3[0x2]; 1561 u8 fpga[0x1]; 1562 u8 rol_s[0x1]; 1563 u8 rol_g[0x1]; 1564 u8 reserved_at_1d8[0x1]; 1565 u8 wol_s[0x1]; 1566 u8 wol_g[0x1]; 1567 u8 wol_a[0x1]; 1568 u8 wol_b[0x1]; 1569 u8 wol_m[0x1]; 1570 u8 wol_u[0x1]; 1571 u8 wol_p[0x1]; 1572 1573 u8 stat_rate_support[0x10]; 1574 u8 reserved_at_1f0[0x1]; 1575 u8 pci_sync_for_fw_update_event[0x1]; 1576 u8 reserved_at_1f2[0x6]; 1577 u8 init2_lag_tx_port_affinity[0x1]; 1578 u8 reserved_at_1fa[0x3]; 1579 u8 cqe_version[0x4]; 1580 1581 u8 compact_address_vector[0x1]; 1582 u8 striding_rq[0x1]; 1583 u8 reserved_at_202[0x1]; 1584 u8 ipoib_enhanced_offloads[0x1]; 1585 u8 ipoib_basic_offloads[0x1]; 1586 u8 reserved_at_205[0x1]; 1587 u8 repeated_block_disabled[0x1]; 1588 u8 umr_modify_entity_size_disabled[0x1]; 1589 u8 umr_modify_atomic_disabled[0x1]; 1590 u8 umr_indirect_mkey_disabled[0x1]; 1591 u8 umr_fence[0x2]; 1592 u8 dc_req_scat_data_cqe[0x1]; 1593 u8 reserved_at_20d[0x2]; 1594 u8 drain_sigerr[0x1]; 1595 u8 cmdif_checksum[0x2]; 1596 u8 sigerr_cqe[0x1]; 1597 u8 reserved_at_213[0x1]; 1598 u8 wq_signature[0x1]; 1599 u8 sctr_data_cqe[0x1]; 1600 u8 reserved_at_216[0x1]; 1601 u8 sho[0x1]; 1602 u8 tph[0x1]; 1603 u8 rf[0x1]; 1604 u8 dct[0x1]; 1605 u8 qos[0x1]; 1606 u8 eth_net_offloads[0x1]; 1607 u8 roce[0x1]; 1608 u8 atomic[0x1]; 1609 u8 reserved_at_21f[0x1]; 1610 1611 u8 cq_oi[0x1]; 1612 u8 cq_resize[0x1]; 1613 u8 cq_moderation[0x1]; 1614 u8 reserved_at_223[0x3]; 1615 u8 cq_eq_remap[0x1]; 1616 u8 pg[0x1]; 1617 u8 block_lb_mc[0x1]; 1618 u8 reserved_at_229[0x1]; 1619 u8 scqe_break_moderation[0x1]; 1620 u8 cq_period_start_from_cqe[0x1]; 1621 u8 cd[0x1]; 1622 u8 reserved_at_22d[0x1]; 1623 u8 apm[0x1]; 1624 u8 vector_calc[0x1]; 1625 u8 umr_ptr_rlky[0x1]; 1626 u8 imaicl[0x1]; 1627 u8 qp_packet_based[0x1]; 1628 u8 reserved_at_233[0x3]; 1629 u8 qkv[0x1]; 1630 u8 pkv[0x1]; 1631 u8 set_deth_sqpn[0x1]; 1632 u8 reserved_at_239[0x3]; 1633 u8 xrc[0x1]; 1634 u8 ud[0x1]; 1635 u8 uc[0x1]; 1636 u8 rc[0x1]; 1637 1638 u8 uar_4k[0x1]; 1639 u8 reserved_at_241[0x9]; 1640 u8 uar_sz[0x6]; 1641 u8 port_selection_cap[0x1]; 1642 u8 reserved_at_248[0x1]; 1643 u8 umem_uid_0[0x1]; 1644 u8 reserved_at_250[0x5]; 1645 u8 log_pg_sz[0x8]; 1646 1647 u8 bf[0x1]; 1648 u8 driver_version[0x1]; 1649 u8 pad_tx_eth_packet[0x1]; 1650 u8 reserved_at_263[0x3]; 1651 u8 mkey_by_name[0x1]; 1652 u8 reserved_at_267[0x4]; 1653 1654 u8 log_bf_reg_size[0x5]; 1655 1656 u8 reserved_at_270[0x6]; 1657 u8 lag_dct[0x2]; 1658 u8 lag_tx_port_affinity[0x1]; 1659 u8 lag_native_fdb_selection[0x1]; 1660 u8 reserved_at_27a[0x1]; 1661 u8 lag_master[0x1]; 1662 u8 num_lag_ports[0x4]; 1663 1664 u8 reserved_at_280[0x10]; 1665 u8 max_wqe_sz_sq[0x10]; 1666 1667 u8 reserved_at_2a0[0x10]; 1668 u8 max_wqe_sz_rq[0x10]; 1669 1670 u8 max_flow_counter_31_16[0x10]; 1671 u8 max_wqe_sz_sq_dc[0x10]; 1672 1673 u8 reserved_at_2e0[0x7]; 1674 u8 max_qp_mcg[0x19]; 1675 1676 u8 reserved_at_300[0x10]; 1677 u8 flow_counter_bulk_alloc[0x8]; 1678 u8 log_max_mcg[0x8]; 1679 1680 u8 reserved_at_320[0x3]; 1681 u8 log_max_transport_domain[0x5]; 1682 u8 reserved_at_328[0x3]; 1683 u8 log_max_pd[0x5]; 1684 u8 reserved_at_330[0xb]; 1685 u8 log_max_xrcd[0x5]; 1686 1687 u8 nic_receive_steering_discard[0x1]; 1688 u8 receive_discard_vport_down[0x1]; 1689 u8 transmit_discard_vport_down[0x1]; 1690 u8 eq_overrun_count[0x1]; 1691 u8 reserved_at_344[0x1]; 1692 u8 invalid_command_count[0x1]; 1693 u8 quota_exceeded_count[0x1]; 1694 u8 reserved_at_347[0x1]; 1695 u8 log_max_flow_counter_bulk[0x8]; 1696 u8 max_flow_counter_15_0[0x10]; 1697 1698 1699 u8 reserved_at_360[0x3]; 1700 u8 log_max_rq[0x5]; 1701 u8 reserved_at_368[0x3]; 1702 u8 log_max_sq[0x5]; 1703 u8 reserved_at_370[0x3]; 1704 u8 log_max_tir[0x5]; 1705 u8 reserved_at_378[0x3]; 1706 u8 log_max_tis[0x5]; 1707 1708 u8 basic_cyclic_rcv_wqe[0x1]; 1709 u8 reserved_at_381[0x2]; 1710 u8 log_max_rmp[0x5]; 1711 u8 reserved_at_388[0x3]; 1712 u8 log_max_rqt[0x5]; 1713 u8 reserved_at_390[0x3]; 1714 u8 log_max_rqt_size[0x5]; 1715 u8 reserved_at_398[0x3]; 1716 u8 log_max_tis_per_sq[0x5]; 1717 1718 u8 ext_stride_num_range[0x1]; 1719 u8 roce_rw_supported[0x1]; 1720 u8 log_max_current_uc_list_wr_supported[0x1]; 1721 u8 log_max_stride_sz_rq[0x5]; 1722 u8 reserved_at_3a8[0x3]; 1723 u8 log_min_stride_sz_rq[0x5]; 1724 u8 reserved_at_3b0[0x3]; 1725 u8 log_max_stride_sz_sq[0x5]; 1726 u8 reserved_at_3b8[0x3]; 1727 u8 log_min_stride_sz_sq[0x5]; 1728 1729 u8 hairpin[0x1]; 1730 u8 reserved_at_3c1[0x2]; 1731 u8 log_max_hairpin_queues[0x5]; 1732 u8 reserved_at_3c8[0x3]; 1733 u8 log_max_hairpin_wq_data_sz[0x5]; 1734 u8 reserved_at_3d0[0x3]; 1735 u8 log_max_hairpin_num_packets[0x5]; 1736 u8 reserved_at_3d8[0x3]; 1737 u8 log_max_wq_sz[0x5]; 1738 1739 u8 nic_vport_change_event[0x1]; 1740 u8 disable_local_lb_uc[0x1]; 1741 u8 disable_local_lb_mc[0x1]; 1742 u8 log_min_hairpin_wq_data_sz[0x5]; 1743 u8 reserved_at_3e8[0x2]; 1744 u8 vhca_state[0x1]; 1745 u8 log_max_vlan_list[0x5]; 1746 u8 reserved_at_3f0[0x3]; 1747 u8 log_max_current_mc_list[0x5]; 1748 u8 reserved_at_3f8[0x3]; 1749 u8 log_max_current_uc_list[0x5]; 1750 1751 u8 general_obj_types[0x40]; 1752 1753 u8 sq_ts_format[0x2]; 1754 u8 rq_ts_format[0x2]; 1755 u8 steering_format_version[0x4]; 1756 u8 create_qp_start_hint[0x18]; 1757 1758 u8 reserved_at_460[0x3]; 1759 u8 log_max_uctx[0x5]; 1760 u8 reserved_at_468[0x2]; 1761 u8 ipsec_offload[0x1]; 1762 u8 log_max_umem[0x5]; 1763 u8 max_num_eqs[0x10]; 1764 1765 u8 reserved_at_480[0x1]; 1766 u8 tls_tx[0x1]; 1767 u8 tls_rx[0x1]; 1768 u8 log_max_l2_table[0x5]; 1769 u8 reserved_at_488[0x8]; 1770 u8 log_uar_page_sz[0x10]; 1771 1772 u8 reserved_at_4a0[0x20]; 1773 u8 device_frequency_mhz[0x20]; 1774 u8 device_frequency_khz[0x20]; 1775 1776 u8 reserved_at_500[0x20]; 1777 u8 num_of_uars_per_page[0x20]; 1778 1779 u8 flex_parser_protocols[0x20]; 1780 1781 u8 max_geneve_tlv_options[0x8]; 1782 u8 reserved_at_568[0x3]; 1783 u8 max_geneve_tlv_option_data_len[0x5]; 1784 u8 reserved_at_570[0x9]; 1785 u8 adv_virtualization[0x1]; 1786 u8 reserved_at_57a[0x6]; 1787 1788 u8 reserved_at_580[0xb]; 1789 u8 log_max_dci_stream_channels[0x5]; 1790 u8 reserved_at_590[0x3]; 1791 u8 log_max_dci_errored_streams[0x5]; 1792 u8 reserved_at_598[0x8]; 1793 1794 u8 reserved_at_5a0[0x10]; 1795 u8 enhanced_cqe_compression[0x1]; 1796 u8 reserved_at_5b1[0x2]; 1797 u8 log_max_dek[0x5]; 1798 u8 reserved_at_5b8[0x4]; 1799 u8 mini_cqe_resp_stride_index[0x1]; 1800 u8 cqe_128_always[0x1]; 1801 u8 cqe_compression_128[0x1]; 1802 u8 cqe_compression[0x1]; 1803 1804 u8 cqe_compression_timeout[0x10]; 1805 u8 cqe_compression_max_num[0x10]; 1806 1807 u8 reserved_at_5e0[0x8]; 1808 u8 flex_parser_id_gtpu_dw_0[0x4]; 1809 u8 reserved_at_5ec[0x4]; 1810 u8 tag_matching[0x1]; 1811 u8 rndv_offload_rc[0x1]; 1812 u8 rndv_offload_dc[0x1]; 1813 u8 log_tag_matching_list_sz[0x5]; 1814 u8 reserved_at_5f8[0x3]; 1815 u8 log_max_xrq[0x5]; 1816 1817 u8 affiliate_nic_vport_criteria[0x8]; 1818 u8 native_port_num[0x8]; 1819 u8 num_vhca_ports[0x8]; 1820 u8 flex_parser_id_gtpu_teid[0x4]; 1821 u8 reserved_at_61c[0x2]; 1822 u8 sw_owner_id[0x1]; 1823 u8 reserved_at_61f[0x1]; 1824 1825 u8 max_num_of_monitor_counters[0x10]; 1826 u8 num_ppcnt_monitor_counters[0x10]; 1827 1828 u8 max_num_sf[0x10]; 1829 u8 num_q_monitor_counters[0x10]; 1830 1831 u8 reserved_at_660[0x20]; 1832 1833 u8 sf[0x1]; 1834 u8 sf_set_partition[0x1]; 1835 u8 reserved_at_682[0x1]; 1836 u8 log_max_sf[0x5]; 1837 u8 apu[0x1]; 1838 u8 reserved_at_689[0x4]; 1839 u8 migration[0x1]; 1840 u8 reserved_at_68e[0x2]; 1841 u8 log_min_sf_size[0x8]; 1842 u8 max_num_sf_partitions[0x8]; 1843 1844 u8 uctx_cap[0x20]; 1845 1846 u8 reserved_at_6c0[0x4]; 1847 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1848 u8 flex_parser_id_icmp_dw1[0x4]; 1849 u8 flex_parser_id_icmp_dw0[0x4]; 1850 u8 flex_parser_id_icmpv6_dw1[0x4]; 1851 u8 flex_parser_id_icmpv6_dw0[0x4]; 1852 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1853 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1854 1855 u8 max_num_match_definer[0x10]; 1856 u8 sf_base_id[0x10]; 1857 1858 u8 flex_parser_id_gtpu_dw_2[0x4]; 1859 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1860 u8 num_total_dynamic_vf_msix[0x18]; 1861 u8 reserved_at_720[0x14]; 1862 u8 dynamic_msix_table_size[0xc]; 1863 u8 reserved_at_740[0xc]; 1864 u8 min_dynamic_vf_msix_table_size[0x4]; 1865 u8 reserved_at_750[0x4]; 1866 u8 max_dynamic_vf_msix_table_size[0xc]; 1867 1868 u8 reserved_at_760[0x20]; 1869 u8 vhca_tunnel_commands[0x40]; 1870 u8 match_definer_format_supported[0x40]; 1871 }; 1872 1873 struct mlx5_ifc_cmd_hca_cap_2_bits { 1874 u8 reserved_at_0[0xa0]; 1875 1876 u8 max_reformat_insert_size[0x8]; 1877 u8 max_reformat_insert_offset[0x8]; 1878 u8 max_reformat_remove_size[0x8]; 1879 u8 max_reformat_remove_offset[0x8]; 1880 1881 u8 reserved_at_c0[0xe0]; 1882 1883 u8 reserved_at_1a0[0xb]; 1884 u8 log_min_mkey_entity_size[0x5]; 1885 u8 reserved_at_1b0[0x10]; 1886 1887 u8 reserved_at_1c0[0x60]; 1888 1889 u8 reserved_at_220[0x1]; 1890 u8 sw_vhca_id_valid[0x1]; 1891 u8 sw_vhca_id[0xe]; 1892 u8 reserved_at_230[0x10]; 1893 1894 u8 reserved_at_240[0xb]; 1895 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1896 u8 reserved_at_250[0x10]; 1897 1898 u8 reserved_at_260[0x5a0]; 1899 }; 1900 1901 enum mlx5_ifc_flow_destination_type { 1902 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1903 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1904 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1905 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1906 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1907 }; 1908 1909 enum mlx5_flow_table_miss_action { 1910 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1911 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1912 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1913 }; 1914 1915 struct mlx5_ifc_dest_format_struct_bits { 1916 u8 destination_type[0x8]; 1917 u8 destination_id[0x18]; 1918 1919 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1920 u8 packet_reformat[0x1]; 1921 u8 reserved_at_22[0xe]; 1922 u8 destination_eswitch_owner_vhca_id[0x10]; 1923 }; 1924 1925 struct mlx5_ifc_flow_counter_list_bits { 1926 u8 flow_counter_id[0x20]; 1927 1928 u8 reserved_at_20[0x20]; 1929 }; 1930 1931 struct mlx5_ifc_extended_dest_format_bits { 1932 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1933 1934 u8 packet_reformat_id[0x20]; 1935 1936 u8 reserved_at_60[0x20]; 1937 }; 1938 1939 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1940 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1941 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1942 }; 1943 1944 struct mlx5_ifc_fte_match_param_bits { 1945 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1946 1947 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1948 1949 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1950 1951 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1952 1953 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1954 1955 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1956 1957 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1958 1959 u8 reserved_at_e00[0x200]; 1960 }; 1961 1962 enum { 1963 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1964 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1965 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1966 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1967 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1968 }; 1969 1970 struct mlx5_ifc_rx_hash_field_select_bits { 1971 u8 l3_prot_type[0x1]; 1972 u8 l4_prot_type[0x1]; 1973 u8 selected_fields[0x1e]; 1974 }; 1975 1976 enum { 1977 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1978 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1979 }; 1980 1981 enum { 1982 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1983 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1984 }; 1985 1986 struct mlx5_ifc_wq_bits { 1987 u8 wq_type[0x4]; 1988 u8 wq_signature[0x1]; 1989 u8 end_padding_mode[0x2]; 1990 u8 cd_slave[0x1]; 1991 u8 reserved_at_8[0x18]; 1992 1993 u8 hds_skip_first_sge[0x1]; 1994 u8 log2_hds_buf_size[0x3]; 1995 u8 reserved_at_24[0x7]; 1996 u8 page_offset[0x5]; 1997 u8 lwm[0x10]; 1998 1999 u8 reserved_at_40[0x8]; 2000 u8 pd[0x18]; 2001 2002 u8 reserved_at_60[0x8]; 2003 u8 uar_page[0x18]; 2004 2005 u8 dbr_addr[0x40]; 2006 2007 u8 hw_counter[0x20]; 2008 2009 u8 sw_counter[0x20]; 2010 2011 u8 reserved_at_100[0xc]; 2012 u8 log_wq_stride[0x4]; 2013 u8 reserved_at_110[0x3]; 2014 u8 log_wq_pg_sz[0x5]; 2015 u8 reserved_at_118[0x3]; 2016 u8 log_wq_sz[0x5]; 2017 2018 u8 dbr_umem_valid[0x1]; 2019 u8 wq_umem_valid[0x1]; 2020 u8 reserved_at_122[0x1]; 2021 u8 log_hairpin_num_packets[0x5]; 2022 u8 reserved_at_128[0x3]; 2023 u8 log_hairpin_data_sz[0x5]; 2024 2025 u8 reserved_at_130[0x4]; 2026 u8 log_wqe_num_of_strides[0x4]; 2027 u8 two_byte_shift_en[0x1]; 2028 u8 reserved_at_139[0x4]; 2029 u8 log_wqe_stride_size[0x3]; 2030 2031 u8 reserved_at_140[0x80]; 2032 2033 u8 headers_mkey[0x20]; 2034 2035 u8 shampo_enable[0x1]; 2036 u8 reserved_at_1e1[0x4]; 2037 u8 log_reservation_size[0x3]; 2038 u8 reserved_at_1e8[0x5]; 2039 u8 log_max_num_of_packets_per_reservation[0x3]; 2040 u8 reserved_at_1f0[0x6]; 2041 u8 log_headers_entry_size[0x2]; 2042 u8 reserved_at_1f8[0x4]; 2043 u8 log_headers_buffer_entry_num[0x4]; 2044 2045 u8 reserved_at_200[0x400]; 2046 2047 struct mlx5_ifc_cmd_pas_bits pas[]; 2048 }; 2049 2050 struct mlx5_ifc_rq_num_bits { 2051 u8 reserved_at_0[0x8]; 2052 u8 rq_num[0x18]; 2053 }; 2054 2055 struct mlx5_ifc_mac_address_layout_bits { 2056 u8 reserved_at_0[0x10]; 2057 u8 mac_addr_47_32[0x10]; 2058 2059 u8 mac_addr_31_0[0x20]; 2060 }; 2061 2062 struct mlx5_ifc_vlan_layout_bits { 2063 u8 reserved_at_0[0x14]; 2064 u8 vlan[0x0c]; 2065 2066 u8 reserved_at_20[0x20]; 2067 }; 2068 2069 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2070 u8 reserved_at_0[0xa0]; 2071 2072 u8 min_time_between_cnps[0x20]; 2073 2074 u8 reserved_at_c0[0x12]; 2075 u8 cnp_dscp[0x6]; 2076 u8 reserved_at_d8[0x4]; 2077 u8 cnp_prio_mode[0x1]; 2078 u8 cnp_802p_prio[0x3]; 2079 2080 u8 reserved_at_e0[0x720]; 2081 }; 2082 2083 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2084 u8 reserved_at_0[0x60]; 2085 2086 u8 reserved_at_60[0x4]; 2087 u8 clamp_tgt_rate[0x1]; 2088 u8 reserved_at_65[0x3]; 2089 u8 clamp_tgt_rate_after_time_inc[0x1]; 2090 u8 reserved_at_69[0x17]; 2091 2092 u8 reserved_at_80[0x20]; 2093 2094 u8 rpg_time_reset[0x20]; 2095 2096 u8 rpg_byte_reset[0x20]; 2097 2098 u8 rpg_threshold[0x20]; 2099 2100 u8 rpg_max_rate[0x20]; 2101 2102 u8 rpg_ai_rate[0x20]; 2103 2104 u8 rpg_hai_rate[0x20]; 2105 2106 u8 rpg_gd[0x20]; 2107 2108 u8 rpg_min_dec_fac[0x20]; 2109 2110 u8 rpg_min_rate[0x20]; 2111 2112 u8 reserved_at_1c0[0xe0]; 2113 2114 u8 rate_to_set_on_first_cnp[0x20]; 2115 2116 u8 dce_tcp_g[0x20]; 2117 2118 u8 dce_tcp_rtt[0x20]; 2119 2120 u8 rate_reduce_monitor_period[0x20]; 2121 2122 u8 reserved_at_320[0x20]; 2123 2124 u8 initial_alpha_value[0x20]; 2125 2126 u8 reserved_at_360[0x4a0]; 2127 }; 2128 2129 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2130 u8 reserved_at_0[0x80]; 2131 2132 u8 rppp_max_rps[0x20]; 2133 2134 u8 rpg_time_reset[0x20]; 2135 2136 u8 rpg_byte_reset[0x20]; 2137 2138 u8 rpg_threshold[0x20]; 2139 2140 u8 rpg_max_rate[0x20]; 2141 2142 u8 rpg_ai_rate[0x20]; 2143 2144 u8 rpg_hai_rate[0x20]; 2145 2146 u8 rpg_gd[0x20]; 2147 2148 u8 rpg_min_dec_fac[0x20]; 2149 2150 u8 rpg_min_rate[0x20]; 2151 2152 u8 reserved_at_1c0[0x640]; 2153 }; 2154 2155 enum { 2156 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2157 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2158 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2159 }; 2160 2161 struct mlx5_ifc_resize_field_select_bits { 2162 u8 resize_field_select[0x20]; 2163 }; 2164 2165 struct mlx5_ifc_resource_dump_bits { 2166 u8 more_dump[0x1]; 2167 u8 inline_dump[0x1]; 2168 u8 reserved_at_2[0xa]; 2169 u8 seq_num[0x4]; 2170 u8 segment_type[0x10]; 2171 2172 u8 reserved_at_20[0x10]; 2173 u8 vhca_id[0x10]; 2174 2175 u8 index1[0x20]; 2176 2177 u8 index2[0x20]; 2178 2179 u8 num_of_obj1[0x10]; 2180 u8 num_of_obj2[0x10]; 2181 2182 u8 reserved_at_a0[0x20]; 2183 2184 u8 device_opaque[0x40]; 2185 2186 u8 mkey[0x20]; 2187 2188 u8 size[0x20]; 2189 2190 u8 address[0x40]; 2191 2192 u8 inline_data[52][0x20]; 2193 }; 2194 2195 struct mlx5_ifc_resource_dump_menu_record_bits { 2196 u8 reserved_at_0[0x4]; 2197 u8 num_of_obj2_supports_active[0x1]; 2198 u8 num_of_obj2_supports_all[0x1]; 2199 u8 must_have_num_of_obj2[0x1]; 2200 u8 support_num_of_obj2[0x1]; 2201 u8 num_of_obj1_supports_active[0x1]; 2202 u8 num_of_obj1_supports_all[0x1]; 2203 u8 must_have_num_of_obj1[0x1]; 2204 u8 support_num_of_obj1[0x1]; 2205 u8 must_have_index2[0x1]; 2206 u8 support_index2[0x1]; 2207 u8 must_have_index1[0x1]; 2208 u8 support_index1[0x1]; 2209 u8 segment_type[0x10]; 2210 2211 u8 segment_name[4][0x20]; 2212 2213 u8 index1_name[4][0x20]; 2214 2215 u8 index2_name[4][0x20]; 2216 }; 2217 2218 struct mlx5_ifc_resource_dump_segment_header_bits { 2219 u8 length_dw[0x10]; 2220 u8 segment_type[0x10]; 2221 }; 2222 2223 struct mlx5_ifc_resource_dump_command_segment_bits { 2224 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2225 2226 u8 segment_called[0x10]; 2227 u8 vhca_id[0x10]; 2228 2229 u8 index1[0x20]; 2230 2231 u8 index2[0x20]; 2232 2233 u8 num_of_obj1[0x10]; 2234 u8 num_of_obj2[0x10]; 2235 }; 2236 2237 struct mlx5_ifc_resource_dump_error_segment_bits { 2238 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2239 2240 u8 reserved_at_20[0x10]; 2241 u8 syndrome_id[0x10]; 2242 2243 u8 reserved_at_40[0x40]; 2244 2245 u8 error[8][0x20]; 2246 }; 2247 2248 struct mlx5_ifc_resource_dump_info_segment_bits { 2249 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2250 2251 u8 reserved_at_20[0x18]; 2252 u8 dump_version[0x8]; 2253 2254 u8 hw_version[0x20]; 2255 2256 u8 fw_version[0x20]; 2257 }; 2258 2259 struct mlx5_ifc_resource_dump_menu_segment_bits { 2260 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2261 2262 u8 reserved_at_20[0x10]; 2263 u8 num_of_records[0x10]; 2264 2265 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2266 }; 2267 2268 struct mlx5_ifc_resource_dump_resource_segment_bits { 2269 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2270 2271 u8 reserved_at_20[0x20]; 2272 2273 u8 index1[0x20]; 2274 2275 u8 index2[0x20]; 2276 2277 u8 payload[][0x20]; 2278 }; 2279 2280 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2281 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2282 }; 2283 2284 struct mlx5_ifc_menu_resource_dump_response_bits { 2285 struct mlx5_ifc_resource_dump_info_segment_bits info; 2286 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2287 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2288 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2289 }; 2290 2291 enum { 2292 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2293 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2294 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2295 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2296 }; 2297 2298 struct mlx5_ifc_modify_field_select_bits { 2299 u8 modify_field_select[0x20]; 2300 }; 2301 2302 struct mlx5_ifc_field_select_r_roce_np_bits { 2303 u8 field_select_r_roce_np[0x20]; 2304 }; 2305 2306 struct mlx5_ifc_field_select_r_roce_rp_bits { 2307 u8 field_select_r_roce_rp[0x20]; 2308 }; 2309 2310 enum { 2311 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2312 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2321 }; 2322 2323 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2324 u8 field_select_8021qaurp[0x20]; 2325 }; 2326 2327 struct mlx5_ifc_phys_layer_cntrs_bits { 2328 u8 time_since_last_clear_high[0x20]; 2329 2330 u8 time_since_last_clear_low[0x20]; 2331 2332 u8 symbol_errors_high[0x20]; 2333 2334 u8 symbol_errors_low[0x20]; 2335 2336 u8 sync_headers_errors_high[0x20]; 2337 2338 u8 sync_headers_errors_low[0x20]; 2339 2340 u8 edpl_bip_errors_lane0_high[0x20]; 2341 2342 u8 edpl_bip_errors_lane0_low[0x20]; 2343 2344 u8 edpl_bip_errors_lane1_high[0x20]; 2345 2346 u8 edpl_bip_errors_lane1_low[0x20]; 2347 2348 u8 edpl_bip_errors_lane2_high[0x20]; 2349 2350 u8 edpl_bip_errors_lane2_low[0x20]; 2351 2352 u8 edpl_bip_errors_lane3_high[0x20]; 2353 2354 u8 edpl_bip_errors_lane3_low[0x20]; 2355 2356 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2357 2358 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2359 2360 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2361 2362 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2363 2364 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2365 2366 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2367 2368 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2369 2370 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2371 2372 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2373 2374 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2375 2376 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2377 2378 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2379 2380 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2381 2382 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2383 2384 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2385 2386 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2387 2388 u8 rs_fec_corrected_blocks_high[0x20]; 2389 2390 u8 rs_fec_corrected_blocks_low[0x20]; 2391 2392 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2393 2394 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2395 2396 u8 rs_fec_no_errors_blocks_high[0x20]; 2397 2398 u8 rs_fec_no_errors_blocks_low[0x20]; 2399 2400 u8 rs_fec_single_error_blocks_high[0x20]; 2401 2402 u8 rs_fec_single_error_blocks_low[0x20]; 2403 2404 u8 rs_fec_corrected_symbols_total_high[0x20]; 2405 2406 u8 rs_fec_corrected_symbols_total_low[0x20]; 2407 2408 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2409 2410 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2411 2412 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2413 2414 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2415 2416 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2417 2418 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2419 2420 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2421 2422 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2423 2424 u8 link_down_events[0x20]; 2425 2426 u8 successful_recovery_events[0x20]; 2427 2428 u8 reserved_at_640[0x180]; 2429 }; 2430 2431 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2432 u8 time_since_last_clear_high[0x20]; 2433 2434 u8 time_since_last_clear_low[0x20]; 2435 2436 u8 phy_received_bits_high[0x20]; 2437 2438 u8 phy_received_bits_low[0x20]; 2439 2440 u8 phy_symbol_errors_high[0x20]; 2441 2442 u8 phy_symbol_errors_low[0x20]; 2443 2444 u8 phy_corrected_bits_high[0x20]; 2445 2446 u8 phy_corrected_bits_low[0x20]; 2447 2448 u8 phy_corrected_bits_lane0_high[0x20]; 2449 2450 u8 phy_corrected_bits_lane0_low[0x20]; 2451 2452 u8 phy_corrected_bits_lane1_high[0x20]; 2453 2454 u8 phy_corrected_bits_lane1_low[0x20]; 2455 2456 u8 phy_corrected_bits_lane2_high[0x20]; 2457 2458 u8 phy_corrected_bits_lane2_low[0x20]; 2459 2460 u8 phy_corrected_bits_lane3_high[0x20]; 2461 2462 u8 phy_corrected_bits_lane3_low[0x20]; 2463 2464 u8 reserved_at_200[0x5c0]; 2465 }; 2466 2467 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2468 u8 symbol_error_counter[0x10]; 2469 2470 u8 link_error_recovery_counter[0x8]; 2471 2472 u8 link_downed_counter[0x8]; 2473 2474 u8 port_rcv_errors[0x10]; 2475 2476 u8 port_rcv_remote_physical_errors[0x10]; 2477 2478 u8 port_rcv_switch_relay_errors[0x10]; 2479 2480 u8 port_xmit_discards[0x10]; 2481 2482 u8 port_xmit_constraint_errors[0x8]; 2483 2484 u8 port_rcv_constraint_errors[0x8]; 2485 2486 u8 reserved_at_70[0x8]; 2487 2488 u8 link_overrun_errors[0x8]; 2489 2490 u8 reserved_at_80[0x10]; 2491 2492 u8 vl_15_dropped[0x10]; 2493 2494 u8 reserved_at_a0[0x80]; 2495 2496 u8 port_xmit_wait[0x20]; 2497 }; 2498 2499 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2500 u8 transmit_queue_high[0x20]; 2501 2502 u8 transmit_queue_low[0x20]; 2503 2504 u8 no_buffer_discard_uc_high[0x20]; 2505 2506 u8 no_buffer_discard_uc_low[0x20]; 2507 2508 u8 reserved_at_80[0x740]; 2509 }; 2510 2511 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2512 u8 wred_discard_high[0x20]; 2513 2514 u8 wred_discard_low[0x20]; 2515 2516 u8 ecn_marked_tc_high[0x20]; 2517 2518 u8 ecn_marked_tc_low[0x20]; 2519 2520 u8 reserved_at_80[0x740]; 2521 }; 2522 2523 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2524 u8 rx_octets_high[0x20]; 2525 2526 u8 rx_octets_low[0x20]; 2527 2528 u8 reserved_at_40[0xc0]; 2529 2530 u8 rx_frames_high[0x20]; 2531 2532 u8 rx_frames_low[0x20]; 2533 2534 u8 tx_octets_high[0x20]; 2535 2536 u8 tx_octets_low[0x20]; 2537 2538 u8 reserved_at_180[0xc0]; 2539 2540 u8 tx_frames_high[0x20]; 2541 2542 u8 tx_frames_low[0x20]; 2543 2544 u8 rx_pause_high[0x20]; 2545 2546 u8 rx_pause_low[0x20]; 2547 2548 u8 rx_pause_duration_high[0x20]; 2549 2550 u8 rx_pause_duration_low[0x20]; 2551 2552 u8 tx_pause_high[0x20]; 2553 2554 u8 tx_pause_low[0x20]; 2555 2556 u8 tx_pause_duration_high[0x20]; 2557 2558 u8 tx_pause_duration_low[0x20]; 2559 2560 u8 rx_pause_transition_high[0x20]; 2561 2562 u8 rx_pause_transition_low[0x20]; 2563 2564 u8 rx_discards_high[0x20]; 2565 2566 u8 rx_discards_low[0x20]; 2567 2568 u8 device_stall_minor_watermark_cnt_high[0x20]; 2569 2570 u8 device_stall_minor_watermark_cnt_low[0x20]; 2571 2572 u8 device_stall_critical_watermark_cnt_high[0x20]; 2573 2574 u8 device_stall_critical_watermark_cnt_low[0x20]; 2575 2576 u8 reserved_at_480[0x340]; 2577 }; 2578 2579 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2580 u8 port_transmit_wait_high[0x20]; 2581 2582 u8 port_transmit_wait_low[0x20]; 2583 2584 u8 reserved_at_40[0x100]; 2585 2586 u8 rx_buffer_almost_full_high[0x20]; 2587 2588 u8 rx_buffer_almost_full_low[0x20]; 2589 2590 u8 rx_buffer_full_high[0x20]; 2591 2592 u8 rx_buffer_full_low[0x20]; 2593 2594 u8 rx_icrc_encapsulated_high[0x20]; 2595 2596 u8 rx_icrc_encapsulated_low[0x20]; 2597 2598 u8 reserved_at_200[0x5c0]; 2599 }; 2600 2601 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2602 u8 dot3stats_alignment_errors_high[0x20]; 2603 2604 u8 dot3stats_alignment_errors_low[0x20]; 2605 2606 u8 dot3stats_fcs_errors_high[0x20]; 2607 2608 u8 dot3stats_fcs_errors_low[0x20]; 2609 2610 u8 dot3stats_single_collision_frames_high[0x20]; 2611 2612 u8 dot3stats_single_collision_frames_low[0x20]; 2613 2614 u8 dot3stats_multiple_collision_frames_high[0x20]; 2615 2616 u8 dot3stats_multiple_collision_frames_low[0x20]; 2617 2618 u8 dot3stats_sqe_test_errors_high[0x20]; 2619 2620 u8 dot3stats_sqe_test_errors_low[0x20]; 2621 2622 u8 dot3stats_deferred_transmissions_high[0x20]; 2623 2624 u8 dot3stats_deferred_transmissions_low[0x20]; 2625 2626 u8 dot3stats_late_collisions_high[0x20]; 2627 2628 u8 dot3stats_late_collisions_low[0x20]; 2629 2630 u8 dot3stats_excessive_collisions_high[0x20]; 2631 2632 u8 dot3stats_excessive_collisions_low[0x20]; 2633 2634 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2635 2636 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2637 2638 u8 dot3stats_carrier_sense_errors_high[0x20]; 2639 2640 u8 dot3stats_carrier_sense_errors_low[0x20]; 2641 2642 u8 dot3stats_frame_too_longs_high[0x20]; 2643 2644 u8 dot3stats_frame_too_longs_low[0x20]; 2645 2646 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2647 2648 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2649 2650 u8 dot3stats_symbol_errors_high[0x20]; 2651 2652 u8 dot3stats_symbol_errors_low[0x20]; 2653 2654 u8 dot3control_in_unknown_opcodes_high[0x20]; 2655 2656 u8 dot3control_in_unknown_opcodes_low[0x20]; 2657 2658 u8 dot3in_pause_frames_high[0x20]; 2659 2660 u8 dot3in_pause_frames_low[0x20]; 2661 2662 u8 dot3out_pause_frames_high[0x20]; 2663 2664 u8 dot3out_pause_frames_low[0x20]; 2665 2666 u8 reserved_at_400[0x3c0]; 2667 }; 2668 2669 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2670 u8 ether_stats_drop_events_high[0x20]; 2671 2672 u8 ether_stats_drop_events_low[0x20]; 2673 2674 u8 ether_stats_octets_high[0x20]; 2675 2676 u8 ether_stats_octets_low[0x20]; 2677 2678 u8 ether_stats_pkts_high[0x20]; 2679 2680 u8 ether_stats_pkts_low[0x20]; 2681 2682 u8 ether_stats_broadcast_pkts_high[0x20]; 2683 2684 u8 ether_stats_broadcast_pkts_low[0x20]; 2685 2686 u8 ether_stats_multicast_pkts_high[0x20]; 2687 2688 u8 ether_stats_multicast_pkts_low[0x20]; 2689 2690 u8 ether_stats_crc_align_errors_high[0x20]; 2691 2692 u8 ether_stats_crc_align_errors_low[0x20]; 2693 2694 u8 ether_stats_undersize_pkts_high[0x20]; 2695 2696 u8 ether_stats_undersize_pkts_low[0x20]; 2697 2698 u8 ether_stats_oversize_pkts_high[0x20]; 2699 2700 u8 ether_stats_oversize_pkts_low[0x20]; 2701 2702 u8 ether_stats_fragments_high[0x20]; 2703 2704 u8 ether_stats_fragments_low[0x20]; 2705 2706 u8 ether_stats_jabbers_high[0x20]; 2707 2708 u8 ether_stats_jabbers_low[0x20]; 2709 2710 u8 ether_stats_collisions_high[0x20]; 2711 2712 u8 ether_stats_collisions_low[0x20]; 2713 2714 u8 ether_stats_pkts64octets_high[0x20]; 2715 2716 u8 ether_stats_pkts64octets_low[0x20]; 2717 2718 u8 ether_stats_pkts65to127octets_high[0x20]; 2719 2720 u8 ether_stats_pkts65to127octets_low[0x20]; 2721 2722 u8 ether_stats_pkts128to255octets_high[0x20]; 2723 2724 u8 ether_stats_pkts128to255octets_low[0x20]; 2725 2726 u8 ether_stats_pkts256to511octets_high[0x20]; 2727 2728 u8 ether_stats_pkts256to511octets_low[0x20]; 2729 2730 u8 ether_stats_pkts512to1023octets_high[0x20]; 2731 2732 u8 ether_stats_pkts512to1023octets_low[0x20]; 2733 2734 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2735 2736 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2737 2738 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2739 2740 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2741 2742 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2743 2744 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2745 2746 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2747 2748 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2749 2750 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2751 2752 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2753 2754 u8 reserved_at_540[0x280]; 2755 }; 2756 2757 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2758 u8 if_in_octets_high[0x20]; 2759 2760 u8 if_in_octets_low[0x20]; 2761 2762 u8 if_in_ucast_pkts_high[0x20]; 2763 2764 u8 if_in_ucast_pkts_low[0x20]; 2765 2766 u8 if_in_discards_high[0x20]; 2767 2768 u8 if_in_discards_low[0x20]; 2769 2770 u8 if_in_errors_high[0x20]; 2771 2772 u8 if_in_errors_low[0x20]; 2773 2774 u8 if_in_unknown_protos_high[0x20]; 2775 2776 u8 if_in_unknown_protos_low[0x20]; 2777 2778 u8 if_out_octets_high[0x20]; 2779 2780 u8 if_out_octets_low[0x20]; 2781 2782 u8 if_out_ucast_pkts_high[0x20]; 2783 2784 u8 if_out_ucast_pkts_low[0x20]; 2785 2786 u8 if_out_discards_high[0x20]; 2787 2788 u8 if_out_discards_low[0x20]; 2789 2790 u8 if_out_errors_high[0x20]; 2791 2792 u8 if_out_errors_low[0x20]; 2793 2794 u8 if_in_multicast_pkts_high[0x20]; 2795 2796 u8 if_in_multicast_pkts_low[0x20]; 2797 2798 u8 if_in_broadcast_pkts_high[0x20]; 2799 2800 u8 if_in_broadcast_pkts_low[0x20]; 2801 2802 u8 if_out_multicast_pkts_high[0x20]; 2803 2804 u8 if_out_multicast_pkts_low[0x20]; 2805 2806 u8 if_out_broadcast_pkts_high[0x20]; 2807 2808 u8 if_out_broadcast_pkts_low[0x20]; 2809 2810 u8 reserved_at_340[0x480]; 2811 }; 2812 2813 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2814 u8 a_frames_transmitted_ok_high[0x20]; 2815 2816 u8 a_frames_transmitted_ok_low[0x20]; 2817 2818 u8 a_frames_received_ok_high[0x20]; 2819 2820 u8 a_frames_received_ok_low[0x20]; 2821 2822 u8 a_frame_check_sequence_errors_high[0x20]; 2823 2824 u8 a_frame_check_sequence_errors_low[0x20]; 2825 2826 u8 a_alignment_errors_high[0x20]; 2827 2828 u8 a_alignment_errors_low[0x20]; 2829 2830 u8 a_octets_transmitted_ok_high[0x20]; 2831 2832 u8 a_octets_transmitted_ok_low[0x20]; 2833 2834 u8 a_octets_received_ok_high[0x20]; 2835 2836 u8 a_octets_received_ok_low[0x20]; 2837 2838 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2839 2840 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2841 2842 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2843 2844 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2845 2846 u8 a_multicast_frames_received_ok_high[0x20]; 2847 2848 u8 a_multicast_frames_received_ok_low[0x20]; 2849 2850 u8 a_broadcast_frames_received_ok_high[0x20]; 2851 2852 u8 a_broadcast_frames_received_ok_low[0x20]; 2853 2854 u8 a_in_range_length_errors_high[0x20]; 2855 2856 u8 a_in_range_length_errors_low[0x20]; 2857 2858 u8 a_out_of_range_length_field_high[0x20]; 2859 2860 u8 a_out_of_range_length_field_low[0x20]; 2861 2862 u8 a_frame_too_long_errors_high[0x20]; 2863 2864 u8 a_frame_too_long_errors_low[0x20]; 2865 2866 u8 a_symbol_error_during_carrier_high[0x20]; 2867 2868 u8 a_symbol_error_during_carrier_low[0x20]; 2869 2870 u8 a_mac_control_frames_transmitted_high[0x20]; 2871 2872 u8 a_mac_control_frames_transmitted_low[0x20]; 2873 2874 u8 a_mac_control_frames_received_high[0x20]; 2875 2876 u8 a_mac_control_frames_received_low[0x20]; 2877 2878 u8 a_unsupported_opcodes_received_high[0x20]; 2879 2880 u8 a_unsupported_opcodes_received_low[0x20]; 2881 2882 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2883 2884 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2885 2886 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2887 2888 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2889 2890 u8 reserved_at_4c0[0x300]; 2891 }; 2892 2893 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2894 u8 life_time_counter_high[0x20]; 2895 2896 u8 life_time_counter_low[0x20]; 2897 2898 u8 rx_errors[0x20]; 2899 2900 u8 tx_errors[0x20]; 2901 2902 u8 l0_to_recovery_eieos[0x20]; 2903 2904 u8 l0_to_recovery_ts[0x20]; 2905 2906 u8 l0_to_recovery_framing[0x20]; 2907 2908 u8 l0_to_recovery_retrain[0x20]; 2909 2910 u8 crc_error_dllp[0x20]; 2911 2912 u8 crc_error_tlp[0x20]; 2913 2914 u8 tx_overflow_buffer_pkt_high[0x20]; 2915 2916 u8 tx_overflow_buffer_pkt_low[0x20]; 2917 2918 u8 outbound_stalled_reads[0x20]; 2919 2920 u8 outbound_stalled_writes[0x20]; 2921 2922 u8 outbound_stalled_reads_events[0x20]; 2923 2924 u8 outbound_stalled_writes_events[0x20]; 2925 2926 u8 reserved_at_200[0x5c0]; 2927 }; 2928 2929 struct mlx5_ifc_cmd_inter_comp_event_bits { 2930 u8 command_completion_vector[0x20]; 2931 2932 u8 reserved_at_20[0xc0]; 2933 }; 2934 2935 struct mlx5_ifc_stall_vl_event_bits { 2936 u8 reserved_at_0[0x18]; 2937 u8 port_num[0x1]; 2938 u8 reserved_at_19[0x3]; 2939 u8 vl[0x4]; 2940 2941 u8 reserved_at_20[0xa0]; 2942 }; 2943 2944 struct mlx5_ifc_db_bf_congestion_event_bits { 2945 u8 event_subtype[0x8]; 2946 u8 reserved_at_8[0x8]; 2947 u8 congestion_level[0x8]; 2948 u8 reserved_at_18[0x8]; 2949 2950 u8 reserved_at_20[0xa0]; 2951 }; 2952 2953 struct mlx5_ifc_gpio_event_bits { 2954 u8 reserved_at_0[0x60]; 2955 2956 u8 gpio_event_hi[0x20]; 2957 2958 u8 gpio_event_lo[0x20]; 2959 2960 u8 reserved_at_a0[0x40]; 2961 }; 2962 2963 struct mlx5_ifc_port_state_change_event_bits { 2964 u8 reserved_at_0[0x40]; 2965 2966 u8 port_num[0x4]; 2967 u8 reserved_at_44[0x1c]; 2968 2969 u8 reserved_at_60[0x80]; 2970 }; 2971 2972 struct mlx5_ifc_dropped_packet_logged_bits { 2973 u8 reserved_at_0[0xe0]; 2974 }; 2975 2976 struct mlx5_ifc_default_timeout_bits { 2977 u8 to_multiplier[0x3]; 2978 u8 reserved_at_3[0x9]; 2979 u8 to_value[0x14]; 2980 }; 2981 2982 struct mlx5_ifc_dtor_reg_bits { 2983 u8 reserved_at_0[0x20]; 2984 2985 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2986 2987 u8 reserved_at_40[0x60]; 2988 2989 struct mlx5_ifc_default_timeout_bits health_poll_to; 2990 2991 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2992 2993 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2994 2995 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2996 2997 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2998 2999 struct mlx5_ifc_default_timeout_bits tear_down_to; 3000 3001 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3002 3003 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3004 3005 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3006 3007 u8 reserved_at_1c0[0x40]; 3008 }; 3009 3010 enum { 3011 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3012 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3013 }; 3014 3015 struct mlx5_ifc_cq_error_bits { 3016 u8 reserved_at_0[0x8]; 3017 u8 cqn[0x18]; 3018 3019 u8 reserved_at_20[0x20]; 3020 3021 u8 reserved_at_40[0x18]; 3022 u8 syndrome[0x8]; 3023 3024 u8 reserved_at_60[0x80]; 3025 }; 3026 3027 struct mlx5_ifc_rdma_page_fault_event_bits { 3028 u8 bytes_committed[0x20]; 3029 3030 u8 r_key[0x20]; 3031 3032 u8 reserved_at_40[0x10]; 3033 u8 packet_len[0x10]; 3034 3035 u8 rdma_op_len[0x20]; 3036 3037 u8 rdma_va[0x40]; 3038 3039 u8 reserved_at_c0[0x5]; 3040 u8 rdma[0x1]; 3041 u8 write[0x1]; 3042 u8 requestor[0x1]; 3043 u8 qp_number[0x18]; 3044 }; 3045 3046 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3047 u8 bytes_committed[0x20]; 3048 3049 u8 reserved_at_20[0x10]; 3050 u8 wqe_index[0x10]; 3051 3052 u8 reserved_at_40[0x10]; 3053 u8 len[0x10]; 3054 3055 u8 reserved_at_60[0x60]; 3056 3057 u8 reserved_at_c0[0x5]; 3058 u8 rdma[0x1]; 3059 u8 write_read[0x1]; 3060 u8 requestor[0x1]; 3061 u8 qpn[0x18]; 3062 }; 3063 3064 struct mlx5_ifc_qp_events_bits { 3065 u8 reserved_at_0[0xa0]; 3066 3067 u8 type[0x8]; 3068 u8 reserved_at_a8[0x18]; 3069 3070 u8 reserved_at_c0[0x8]; 3071 u8 qpn_rqn_sqn[0x18]; 3072 }; 3073 3074 struct mlx5_ifc_dct_events_bits { 3075 u8 reserved_at_0[0xc0]; 3076 3077 u8 reserved_at_c0[0x8]; 3078 u8 dct_number[0x18]; 3079 }; 3080 3081 struct mlx5_ifc_comp_event_bits { 3082 u8 reserved_at_0[0xc0]; 3083 3084 u8 reserved_at_c0[0x8]; 3085 u8 cq_number[0x18]; 3086 }; 3087 3088 enum { 3089 MLX5_QPC_STATE_RST = 0x0, 3090 MLX5_QPC_STATE_INIT = 0x1, 3091 MLX5_QPC_STATE_RTR = 0x2, 3092 MLX5_QPC_STATE_RTS = 0x3, 3093 MLX5_QPC_STATE_SQER = 0x4, 3094 MLX5_QPC_STATE_ERR = 0x6, 3095 MLX5_QPC_STATE_SQD = 0x7, 3096 MLX5_QPC_STATE_SUSPENDED = 0x9, 3097 }; 3098 3099 enum { 3100 MLX5_QPC_ST_RC = 0x0, 3101 MLX5_QPC_ST_UC = 0x1, 3102 MLX5_QPC_ST_UD = 0x2, 3103 MLX5_QPC_ST_XRC = 0x3, 3104 MLX5_QPC_ST_DCI = 0x5, 3105 MLX5_QPC_ST_QP0 = 0x7, 3106 MLX5_QPC_ST_QP1 = 0x8, 3107 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3108 MLX5_QPC_ST_REG_UMR = 0xc, 3109 }; 3110 3111 enum { 3112 MLX5_QPC_PM_STATE_ARMED = 0x0, 3113 MLX5_QPC_PM_STATE_REARM = 0x1, 3114 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3115 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3116 }; 3117 3118 enum { 3119 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3120 }; 3121 3122 enum { 3123 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3124 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3125 }; 3126 3127 enum { 3128 MLX5_QPC_MTU_256_BYTES = 0x1, 3129 MLX5_QPC_MTU_512_BYTES = 0x2, 3130 MLX5_QPC_MTU_1K_BYTES = 0x3, 3131 MLX5_QPC_MTU_2K_BYTES = 0x4, 3132 MLX5_QPC_MTU_4K_BYTES = 0x5, 3133 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3134 }; 3135 3136 enum { 3137 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3138 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3139 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3140 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3141 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3142 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3143 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3144 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3145 }; 3146 3147 enum { 3148 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3149 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3150 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3151 }; 3152 3153 enum { 3154 MLX5_QPC_CS_RES_DISABLE = 0x0, 3155 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3156 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3157 }; 3158 3159 enum { 3160 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3161 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3162 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3163 }; 3164 3165 struct mlx5_ifc_qpc_bits { 3166 u8 state[0x4]; 3167 u8 lag_tx_port_affinity[0x4]; 3168 u8 st[0x8]; 3169 u8 reserved_at_10[0x2]; 3170 u8 isolate_vl_tc[0x1]; 3171 u8 pm_state[0x2]; 3172 u8 reserved_at_15[0x1]; 3173 u8 req_e2e_credit_mode[0x2]; 3174 u8 offload_type[0x4]; 3175 u8 end_padding_mode[0x2]; 3176 u8 reserved_at_1e[0x2]; 3177 3178 u8 wq_signature[0x1]; 3179 u8 block_lb_mc[0x1]; 3180 u8 atomic_like_write_en[0x1]; 3181 u8 latency_sensitive[0x1]; 3182 u8 reserved_at_24[0x1]; 3183 u8 drain_sigerr[0x1]; 3184 u8 reserved_at_26[0x2]; 3185 u8 pd[0x18]; 3186 3187 u8 mtu[0x3]; 3188 u8 log_msg_max[0x5]; 3189 u8 reserved_at_48[0x1]; 3190 u8 log_rq_size[0x4]; 3191 u8 log_rq_stride[0x3]; 3192 u8 no_sq[0x1]; 3193 u8 log_sq_size[0x4]; 3194 u8 reserved_at_55[0x3]; 3195 u8 ts_format[0x2]; 3196 u8 reserved_at_5a[0x1]; 3197 u8 rlky[0x1]; 3198 u8 ulp_stateless_offload_mode[0x4]; 3199 3200 u8 counter_set_id[0x8]; 3201 u8 uar_page[0x18]; 3202 3203 u8 reserved_at_80[0x8]; 3204 u8 user_index[0x18]; 3205 3206 u8 reserved_at_a0[0x3]; 3207 u8 log_page_size[0x5]; 3208 u8 remote_qpn[0x18]; 3209 3210 struct mlx5_ifc_ads_bits primary_address_path; 3211 3212 struct mlx5_ifc_ads_bits secondary_address_path; 3213 3214 u8 log_ack_req_freq[0x4]; 3215 u8 reserved_at_384[0x4]; 3216 u8 log_sra_max[0x3]; 3217 u8 reserved_at_38b[0x2]; 3218 u8 retry_count[0x3]; 3219 u8 rnr_retry[0x3]; 3220 u8 reserved_at_393[0x1]; 3221 u8 fre[0x1]; 3222 u8 cur_rnr_retry[0x3]; 3223 u8 cur_retry_count[0x3]; 3224 u8 reserved_at_39b[0x5]; 3225 3226 u8 reserved_at_3a0[0x20]; 3227 3228 u8 reserved_at_3c0[0x8]; 3229 u8 next_send_psn[0x18]; 3230 3231 u8 reserved_at_3e0[0x3]; 3232 u8 log_num_dci_stream_channels[0x5]; 3233 u8 cqn_snd[0x18]; 3234 3235 u8 reserved_at_400[0x3]; 3236 u8 log_num_dci_errored_streams[0x5]; 3237 u8 deth_sqpn[0x18]; 3238 3239 u8 reserved_at_420[0x20]; 3240 3241 u8 reserved_at_440[0x8]; 3242 u8 last_acked_psn[0x18]; 3243 3244 u8 reserved_at_460[0x8]; 3245 u8 ssn[0x18]; 3246 3247 u8 reserved_at_480[0x8]; 3248 u8 log_rra_max[0x3]; 3249 u8 reserved_at_48b[0x1]; 3250 u8 atomic_mode[0x4]; 3251 u8 rre[0x1]; 3252 u8 rwe[0x1]; 3253 u8 rae[0x1]; 3254 u8 reserved_at_493[0x1]; 3255 u8 page_offset[0x6]; 3256 u8 reserved_at_49a[0x3]; 3257 u8 cd_slave_receive[0x1]; 3258 u8 cd_slave_send[0x1]; 3259 u8 cd_master[0x1]; 3260 3261 u8 reserved_at_4a0[0x3]; 3262 u8 min_rnr_nak[0x5]; 3263 u8 next_rcv_psn[0x18]; 3264 3265 u8 reserved_at_4c0[0x8]; 3266 u8 xrcd[0x18]; 3267 3268 u8 reserved_at_4e0[0x8]; 3269 u8 cqn_rcv[0x18]; 3270 3271 u8 dbr_addr[0x40]; 3272 3273 u8 q_key[0x20]; 3274 3275 u8 reserved_at_560[0x5]; 3276 u8 rq_type[0x3]; 3277 u8 srqn_rmpn_xrqn[0x18]; 3278 3279 u8 reserved_at_580[0x8]; 3280 u8 rmsn[0x18]; 3281 3282 u8 hw_sq_wqebb_counter[0x10]; 3283 u8 sw_sq_wqebb_counter[0x10]; 3284 3285 u8 hw_rq_counter[0x20]; 3286 3287 u8 sw_rq_counter[0x20]; 3288 3289 u8 reserved_at_600[0x20]; 3290 3291 u8 reserved_at_620[0xf]; 3292 u8 cgs[0x1]; 3293 u8 cs_req[0x8]; 3294 u8 cs_res[0x8]; 3295 3296 u8 dc_access_key[0x40]; 3297 3298 u8 reserved_at_680[0x3]; 3299 u8 dbr_umem_valid[0x1]; 3300 3301 u8 reserved_at_684[0xbc]; 3302 }; 3303 3304 struct mlx5_ifc_roce_addr_layout_bits { 3305 u8 source_l3_address[16][0x8]; 3306 3307 u8 reserved_at_80[0x3]; 3308 u8 vlan_valid[0x1]; 3309 u8 vlan_id[0xc]; 3310 u8 source_mac_47_32[0x10]; 3311 3312 u8 source_mac_31_0[0x20]; 3313 3314 u8 reserved_at_c0[0x14]; 3315 u8 roce_l3_type[0x4]; 3316 u8 roce_version[0x8]; 3317 3318 u8 reserved_at_e0[0x20]; 3319 }; 3320 3321 struct mlx5_ifc_shampo_cap_bits { 3322 u8 reserved_at_0[0x3]; 3323 u8 shampo_log_max_reservation_size[0x5]; 3324 u8 reserved_at_8[0x3]; 3325 u8 shampo_log_min_reservation_size[0x5]; 3326 u8 shampo_min_mss_size[0x10]; 3327 3328 u8 reserved_at_20[0x3]; 3329 u8 shampo_max_log_headers_entry_size[0x5]; 3330 u8 reserved_at_28[0x18]; 3331 3332 u8 reserved_at_40[0x7c0]; 3333 }; 3334 3335 union mlx5_ifc_hca_cap_union_bits { 3336 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3337 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3338 struct mlx5_ifc_odp_cap_bits odp_cap; 3339 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3340 struct mlx5_ifc_roce_cap_bits roce_cap; 3341 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3342 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3343 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3344 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3345 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3346 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3347 struct mlx5_ifc_qos_cap_bits qos_cap; 3348 struct mlx5_ifc_debug_cap_bits debug_cap; 3349 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3350 struct mlx5_ifc_tls_cap_bits tls_cap; 3351 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3352 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3353 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3354 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3355 u8 reserved_at_0[0x8000]; 3356 }; 3357 3358 enum { 3359 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3360 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3361 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3362 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3363 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3364 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3365 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3366 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3367 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3368 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3369 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3370 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3371 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3372 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3373 }; 3374 3375 enum { 3376 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3377 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3378 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3379 }; 3380 3381 enum { 3382 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3383 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3384 }; 3385 3386 struct mlx5_ifc_vlan_bits { 3387 u8 ethtype[0x10]; 3388 u8 prio[0x3]; 3389 u8 cfi[0x1]; 3390 u8 vid[0xc]; 3391 }; 3392 3393 enum { 3394 MLX5_FLOW_METER_COLOR_RED = 0x0, 3395 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3396 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3397 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3398 }; 3399 3400 enum { 3401 MLX5_EXE_ASO_FLOW_METER = 0x2, 3402 }; 3403 3404 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3405 u8 return_reg_id[0x4]; 3406 u8 aso_type[0x4]; 3407 u8 reserved_at_8[0x14]; 3408 u8 action[0x1]; 3409 u8 init_color[0x2]; 3410 u8 meter_id[0x1]; 3411 }; 3412 3413 union mlx5_ifc_exe_aso_ctrl { 3414 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3415 }; 3416 3417 struct mlx5_ifc_execute_aso_bits { 3418 u8 valid[0x1]; 3419 u8 reserved_at_1[0x7]; 3420 u8 aso_object_id[0x18]; 3421 3422 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3423 }; 3424 3425 struct mlx5_ifc_flow_context_bits { 3426 struct mlx5_ifc_vlan_bits push_vlan; 3427 3428 u8 group_id[0x20]; 3429 3430 u8 reserved_at_40[0x8]; 3431 u8 flow_tag[0x18]; 3432 3433 u8 reserved_at_60[0x10]; 3434 u8 action[0x10]; 3435 3436 u8 extended_destination[0x1]; 3437 u8 reserved_at_81[0x1]; 3438 u8 flow_source[0x2]; 3439 u8 encrypt_decrypt_type[0x4]; 3440 u8 destination_list_size[0x18]; 3441 3442 u8 reserved_at_a0[0x8]; 3443 u8 flow_counter_list_size[0x18]; 3444 3445 u8 packet_reformat_id[0x20]; 3446 3447 u8 modify_header_id[0x20]; 3448 3449 struct mlx5_ifc_vlan_bits push_vlan_2; 3450 3451 u8 encrypt_decrypt_obj_id[0x20]; 3452 u8 reserved_at_140[0xc0]; 3453 3454 struct mlx5_ifc_fte_match_param_bits match_value; 3455 3456 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3457 3458 u8 reserved_at_1300[0x500]; 3459 3460 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3461 }; 3462 3463 enum { 3464 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3465 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3466 }; 3467 3468 struct mlx5_ifc_xrc_srqc_bits { 3469 u8 state[0x4]; 3470 u8 log_xrc_srq_size[0x4]; 3471 u8 reserved_at_8[0x18]; 3472 3473 u8 wq_signature[0x1]; 3474 u8 cont_srq[0x1]; 3475 u8 reserved_at_22[0x1]; 3476 u8 rlky[0x1]; 3477 u8 basic_cyclic_rcv_wqe[0x1]; 3478 u8 log_rq_stride[0x3]; 3479 u8 xrcd[0x18]; 3480 3481 u8 page_offset[0x6]; 3482 u8 reserved_at_46[0x1]; 3483 u8 dbr_umem_valid[0x1]; 3484 u8 cqn[0x18]; 3485 3486 u8 reserved_at_60[0x20]; 3487 3488 u8 user_index_equal_xrc_srqn[0x1]; 3489 u8 reserved_at_81[0x1]; 3490 u8 log_page_size[0x6]; 3491 u8 user_index[0x18]; 3492 3493 u8 reserved_at_a0[0x20]; 3494 3495 u8 reserved_at_c0[0x8]; 3496 u8 pd[0x18]; 3497 3498 u8 lwm[0x10]; 3499 u8 wqe_cnt[0x10]; 3500 3501 u8 reserved_at_100[0x40]; 3502 3503 u8 db_record_addr_h[0x20]; 3504 3505 u8 db_record_addr_l[0x1e]; 3506 u8 reserved_at_17e[0x2]; 3507 3508 u8 reserved_at_180[0x80]; 3509 }; 3510 3511 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3512 u8 counter_error_queues[0x20]; 3513 3514 u8 total_error_queues[0x20]; 3515 3516 u8 send_queue_priority_update_flow[0x20]; 3517 3518 u8 reserved_at_60[0x20]; 3519 3520 u8 nic_receive_steering_discard[0x40]; 3521 3522 u8 receive_discard_vport_down[0x40]; 3523 3524 u8 transmit_discard_vport_down[0x40]; 3525 3526 u8 async_eq_overrun[0x20]; 3527 3528 u8 comp_eq_overrun[0x20]; 3529 3530 u8 reserved_at_180[0x20]; 3531 3532 u8 invalid_command[0x20]; 3533 3534 u8 quota_exceeded_command[0x20]; 3535 3536 u8 internal_rq_out_of_buffer[0x20]; 3537 3538 u8 cq_overrun[0x20]; 3539 3540 u8 reserved_at_220[0xde0]; 3541 }; 3542 3543 struct mlx5_ifc_traffic_counter_bits { 3544 u8 packets[0x40]; 3545 3546 u8 octets[0x40]; 3547 }; 3548 3549 struct mlx5_ifc_tisc_bits { 3550 u8 strict_lag_tx_port_affinity[0x1]; 3551 u8 tls_en[0x1]; 3552 u8 reserved_at_2[0x2]; 3553 u8 lag_tx_port_affinity[0x04]; 3554 3555 u8 reserved_at_8[0x4]; 3556 u8 prio[0x4]; 3557 u8 reserved_at_10[0x10]; 3558 3559 u8 reserved_at_20[0x100]; 3560 3561 u8 reserved_at_120[0x8]; 3562 u8 transport_domain[0x18]; 3563 3564 u8 reserved_at_140[0x8]; 3565 u8 underlay_qpn[0x18]; 3566 3567 u8 reserved_at_160[0x8]; 3568 u8 pd[0x18]; 3569 3570 u8 reserved_at_180[0x380]; 3571 }; 3572 3573 enum { 3574 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3575 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3576 }; 3577 3578 enum { 3579 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3580 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3581 }; 3582 3583 enum { 3584 MLX5_RX_HASH_FN_NONE = 0x0, 3585 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3586 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3587 }; 3588 3589 enum { 3590 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3591 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3592 }; 3593 3594 struct mlx5_ifc_tirc_bits { 3595 u8 reserved_at_0[0x20]; 3596 3597 u8 disp_type[0x4]; 3598 u8 tls_en[0x1]; 3599 u8 reserved_at_25[0x1b]; 3600 3601 u8 reserved_at_40[0x40]; 3602 3603 u8 reserved_at_80[0x4]; 3604 u8 lro_timeout_period_usecs[0x10]; 3605 u8 packet_merge_mask[0x4]; 3606 u8 lro_max_ip_payload_size[0x8]; 3607 3608 u8 reserved_at_a0[0x40]; 3609 3610 u8 reserved_at_e0[0x8]; 3611 u8 inline_rqn[0x18]; 3612 3613 u8 rx_hash_symmetric[0x1]; 3614 u8 reserved_at_101[0x1]; 3615 u8 tunneled_offload_en[0x1]; 3616 u8 reserved_at_103[0x5]; 3617 u8 indirect_table[0x18]; 3618 3619 u8 rx_hash_fn[0x4]; 3620 u8 reserved_at_124[0x2]; 3621 u8 self_lb_block[0x2]; 3622 u8 transport_domain[0x18]; 3623 3624 u8 rx_hash_toeplitz_key[10][0x20]; 3625 3626 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3627 3628 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3629 3630 u8 reserved_at_2c0[0x4c0]; 3631 }; 3632 3633 enum { 3634 MLX5_SRQC_STATE_GOOD = 0x0, 3635 MLX5_SRQC_STATE_ERROR = 0x1, 3636 }; 3637 3638 struct mlx5_ifc_srqc_bits { 3639 u8 state[0x4]; 3640 u8 log_srq_size[0x4]; 3641 u8 reserved_at_8[0x18]; 3642 3643 u8 wq_signature[0x1]; 3644 u8 cont_srq[0x1]; 3645 u8 reserved_at_22[0x1]; 3646 u8 rlky[0x1]; 3647 u8 reserved_at_24[0x1]; 3648 u8 log_rq_stride[0x3]; 3649 u8 xrcd[0x18]; 3650 3651 u8 page_offset[0x6]; 3652 u8 reserved_at_46[0x2]; 3653 u8 cqn[0x18]; 3654 3655 u8 reserved_at_60[0x20]; 3656 3657 u8 reserved_at_80[0x2]; 3658 u8 log_page_size[0x6]; 3659 u8 reserved_at_88[0x18]; 3660 3661 u8 reserved_at_a0[0x20]; 3662 3663 u8 reserved_at_c0[0x8]; 3664 u8 pd[0x18]; 3665 3666 u8 lwm[0x10]; 3667 u8 wqe_cnt[0x10]; 3668 3669 u8 reserved_at_100[0x40]; 3670 3671 u8 dbr_addr[0x40]; 3672 3673 u8 reserved_at_180[0x80]; 3674 }; 3675 3676 enum { 3677 MLX5_SQC_STATE_RST = 0x0, 3678 MLX5_SQC_STATE_RDY = 0x1, 3679 MLX5_SQC_STATE_ERR = 0x3, 3680 }; 3681 3682 struct mlx5_ifc_sqc_bits { 3683 u8 rlky[0x1]; 3684 u8 cd_master[0x1]; 3685 u8 fre[0x1]; 3686 u8 flush_in_error_en[0x1]; 3687 u8 allow_multi_pkt_send_wqe[0x1]; 3688 u8 min_wqe_inline_mode[0x3]; 3689 u8 state[0x4]; 3690 u8 reg_umr[0x1]; 3691 u8 allow_swp[0x1]; 3692 u8 hairpin[0x1]; 3693 u8 reserved_at_f[0xb]; 3694 u8 ts_format[0x2]; 3695 u8 reserved_at_1c[0x4]; 3696 3697 u8 reserved_at_20[0x8]; 3698 u8 user_index[0x18]; 3699 3700 u8 reserved_at_40[0x8]; 3701 u8 cqn[0x18]; 3702 3703 u8 reserved_at_60[0x8]; 3704 u8 hairpin_peer_rq[0x18]; 3705 3706 u8 reserved_at_80[0x10]; 3707 u8 hairpin_peer_vhca[0x10]; 3708 3709 u8 reserved_at_a0[0x20]; 3710 3711 u8 reserved_at_c0[0x8]; 3712 u8 ts_cqe_to_dest_cqn[0x18]; 3713 3714 u8 reserved_at_e0[0x10]; 3715 u8 packet_pacing_rate_limit_index[0x10]; 3716 u8 tis_lst_sz[0x10]; 3717 u8 qos_queue_group_id[0x10]; 3718 3719 u8 reserved_at_120[0x40]; 3720 3721 u8 reserved_at_160[0x8]; 3722 u8 tis_num_0[0x18]; 3723 3724 struct mlx5_ifc_wq_bits wq; 3725 }; 3726 3727 enum { 3728 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3729 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3730 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3731 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3732 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3733 }; 3734 3735 enum { 3736 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3737 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3738 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3739 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3740 }; 3741 3742 struct mlx5_ifc_scheduling_context_bits { 3743 u8 element_type[0x8]; 3744 u8 reserved_at_8[0x18]; 3745 3746 u8 element_attributes[0x20]; 3747 3748 u8 parent_element_id[0x20]; 3749 3750 u8 reserved_at_60[0x40]; 3751 3752 u8 bw_share[0x20]; 3753 3754 u8 max_average_bw[0x20]; 3755 3756 u8 reserved_at_e0[0x120]; 3757 }; 3758 3759 struct mlx5_ifc_rqtc_bits { 3760 u8 reserved_at_0[0xa0]; 3761 3762 u8 reserved_at_a0[0x5]; 3763 u8 list_q_type[0x3]; 3764 u8 reserved_at_a8[0x8]; 3765 u8 rqt_max_size[0x10]; 3766 3767 u8 rq_vhca_id_format[0x1]; 3768 u8 reserved_at_c1[0xf]; 3769 u8 rqt_actual_size[0x10]; 3770 3771 u8 reserved_at_e0[0x6a0]; 3772 3773 struct mlx5_ifc_rq_num_bits rq_num[]; 3774 }; 3775 3776 enum { 3777 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3778 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3779 }; 3780 3781 enum { 3782 MLX5_RQC_STATE_RST = 0x0, 3783 MLX5_RQC_STATE_RDY = 0x1, 3784 MLX5_RQC_STATE_ERR = 0x3, 3785 }; 3786 3787 enum { 3788 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3789 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3790 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3791 }; 3792 3793 enum { 3794 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3795 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3796 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3797 }; 3798 3799 struct mlx5_ifc_rqc_bits { 3800 u8 rlky[0x1]; 3801 u8 delay_drop_en[0x1]; 3802 u8 scatter_fcs[0x1]; 3803 u8 vsd[0x1]; 3804 u8 mem_rq_type[0x4]; 3805 u8 state[0x4]; 3806 u8 reserved_at_c[0x1]; 3807 u8 flush_in_error_en[0x1]; 3808 u8 hairpin[0x1]; 3809 u8 reserved_at_f[0xb]; 3810 u8 ts_format[0x2]; 3811 u8 reserved_at_1c[0x4]; 3812 3813 u8 reserved_at_20[0x8]; 3814 u8 user_index[0x18]; 3815 3816 u8 reserved_at_40[0x8]; 3817 u8 cqn[0x18]; 3818 3819 u8 counter_set_id[0x8]; 3820 u8 reserved_at_68[0x18]; 3821 3822 u8 reserved_at_80[0x8]; 3823 u8 rmpn[0x18]; 3824 3825 u8 reserved_at_a0[0x8]; 3826 u8 hairpin_peer_sq[0x18]; 3827 3828 u8 reserved_at_c0[0x10]; 3829 u8 hairpin_peer_vhca[0x10]; 3830 3831 u8 reserved_at_e0[0x46]; 3832 u8 shampo_no_match_alignment_granularity[0x2]; 3833 u8 reserved_at_128[0x6]; 3834 u8 shampo_match_criteria_type[0x2]; 3835 u8 reservation_timeout[0x10]; 3836 3837 u8 reserved_at_140[0x40]; 3838 3839 struct mlx5_ifc_wq_bits wq; 3840 }; 3841 3842 enum { 3843 MLX5_RMPC_STATE_RDY = 0x1, 3844 MLX5_RMPC_STATE_ERR = 0x3, 3845 }; 3846 3847 struct mlx5_ifc_rmpc_bits { 3848 u8 reserved_at_0[0x8]; 3849 u8 state[0x4]; 3850 u8 reserved_at_c[0x14]; 3851 3852 u8 basic_cyclic_rcv_wqe[0x1]; 3853 u8 reserved_at_21[0x1f]; 3854 3855 u8 reserved_at_40[0x140]; 3856 3857 struct mlx5_ifc_wq_bits wq; 3858 }; 3859 3860 enum { 3861 VHCA_ID_TYPE_HW = 0, 3862 VHCA_ID_TYPE_SW = 1, 3863 }; 3864 3865 struct mlx5_ifc_nic_vport_context_bits { 3866 u8 reserved_at_0[0x5]; 3867 u8 min_wqe_inline_mode[0x3]; 3868 u8 reserved_at_8[0x15]; 3869 u8 disable_mc_local_lb[0x1]; 3870 u8 disable_uc_local_lb[0x1]; 3871 u8 roce_en[0x1]; 3872 3873 u8 arm_change_event[0x1]; 3874 u8 reserved_at_21[0x1a]; 3875 u8 event_on_mtu[0x1]; 3876 u8 event_on_promisc_change[0x1]; 3877 u8 event_on_vlan_change[0x1]; 3878 u8 event_on_mc_address_change[0x1]; 3879 u8 event_on_uc_address_change[0x1]; 3880 3881 u8 vhca_id_type[0x1]; 3882 u8 reserved_at_41[0xb]; 3883 u8 affiliation_criteria[0x4]; 3884 u8 affiliated_vhca_id[0x10]; 3885 3886 u8 reserved_at_60[0xd0]; 3887 3888 u8 mtu[0x10]; 3889 3890 u8 system_image_guid[0x40]; 3891 u8 port_guid[0x40]; 3892 u8 node_guid[0x40]; 3893 3894 u8 reserved_at_200[0x140]; 3895 u8 qkey_violation_counter[0x10]; 3896 u8 reserved_at_350[0x430]; 3897 3898 u8 promisc_uc[0x1]; 3899 u8 promisc_mc[0x1]; 3900 u8 promisc_all[0x1]; 3901 u8 reserved_at_783[0x2]; 3902 u8 allowed_list_type[0x3]; 3903 u8 reserved_at_788[0xc]; 3904 u8 allowed_list_size[0xc]; 3905 3906 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3907 3908 u8 reserved_at_7e0[0x20]; 3909 3910 u8 current_uc_mac_address[][0x40]; 3911 }; 3912 3913 enum { 3914 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3915 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3916 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3917 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3918 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3919 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3920 }; 3921 3922 struct mlx5_ifc_mkc_bits { 3923 u8 reserved_at_0[0x1]; 3924 u8 free[0x1]; 3925 u8 reserved_at_2[0x1]; 3926 u8 access_mode_4_2[0x3]; 3927 u8 reserved_at_6[0x7]; 3928 u8 relaxed_ordering_write[0x1]; 3929 u8 reserved_at_e[0x1]; 3930 u8 small_fence_on_rdma_read_response[0x1]; 3931 u8 umr_en[0x1]; 3932 u8 a[0x1]; 3933 u8 rw[0x1]; 3934 u8 rr[0x1]; 3935 u8 lw[0x1]; 3936 u8 lr[0x1]; 3937 u8 access_mode_1_0[0x2]; 3938 u8 reserved_at_18[0x8]; 3939 3940 u8 qpn[0x18]; 3941 u8 mkey_7_0[0x8]; 3942 3943 u8 reserved_at_40[0x20]; 3944 3945 u8 length64[0x1]; 3946 u8 bsf_en[0x1]; 3947 u8 sync_umr[0x1]; 3948 u8 reserved_at_63[0x2]; 3949 u8 expected_sigerr_count[0x1]; 3950 u8 reserved_at_66[0x1]; 3951 u8 en_rinval[0x1]; 3952 u8 pd[0x18]; 3953 3954 u8 start_addr[0x40]; 3955 3956 u8 len[0x40]; 3957 3958 u8 bsf_octword_size[0x20]; 3959 3960 u8 reserved_at_120[0x80]; 3961 3962 u8 translations_octword_size[0x20]; 3963 3964 u8 reserved_at_1c0[0x19]; 3965 u8 relaxed_ordering_read[0x1]; 3966 u8 reserved_at_1d9[0x1]; 3967 u8 log_page_size[0x5]; 3968 3969 u8 reserved_at_1e0[0x20]; 3970 }; 3971 3972 struct mlx5_ifc_pkey_bits { 3973 u8 reserved_at_0[0x10]; 3974 u8 pkey[0x10]; 3975 }; 3976 3977 struct mlx5_ifc_array128_auto_bits { 3978 u8 array128_auto[16][0x8]; 3979 }; 3980 3981 struct mlx5_ifc_hca_vport_context_bits { 3982 u8 field_select[0x20]; 3983 3984 u8 reserved_at_20[0xe0]; 3985 3986 u8 sm_virt_aware[0x1]; 3987 u8 has_smi[0x1]; 3988 u8 has_raw[0x1]; 3989 u8 grh_required[0x1]; 3990 u8 reserved_at_104[0xc]; 3991 u8 port_physical_state[0x4]; 3992 u8 vport_state_policy[0x4]; 3993 u8 port_state[0x4]; 3994 u8 vport_state[0x4]; 3995 3996 u8 reserved_at_120[0x20]; 3997 3998 u8 system_image_guid[0x40]; 3999 4000 u8 port_guid[0x40]; 4001 4002 u8 node_guid[0x40]; 4003 4004 u8 cap_mask1[0x20]; 4005 4006 u8 cap_mask1_field_select[0x20]; 4007 4008 u8 cap_mask2[0x20]; 4009 4010 u8 cap_mask2_field_select[0x20]; 4011 4012 u8 reserved_at_280[0x80]; 4013 4014 u8 lid[0x10]; 4015 u8 reserved_at_310[0x4]; 4016 u8 init_type_reply[0x4]; 4017 u8 lmc[0x3]; 4018 u8 subnet_timeout[0x5]; 4019 4020 u8 sm_lid[0x10]; 4021 u8 sm_sl[0x4]; 4022 u8 reserved_at_334[0xc]; 4023 4024 u8 qkey_violation_counter[0x10]; 4025 u8 pkey_violation_counter[0x10]; 4026 4027 u8 reserved_at_360[0xca0]; 4028 }; 4029 4030 struct mlx5_ifc_esw_vport_context_bits { 4031 u8 fdb_to_vport_reg_c[0x1]; 4032 u8 reserved_at_1[0x2]; 4033 u8 vport_svlan_strip[0x1]; 4034 u8 vport_cvlan_strip[0x1]; 4035 u8 vport_svlan_insert[0x1]; 4036 u8 vport_cvlan_insert[0x2]; 4037 u8 fdb_to_vport_reg_c_id[0x8]; 4038 u8 reserved_at_10[0x10]; 4039 4040 u8 reserved_at_20[0x20]; 4041 4042 u8 svlan_cfi[0x1]; 4043 u8 svlan_pcp[0x3]; 4044 u8 svlan_id[0xc]; 4045 u8 cvlan_cfi[0x1]; 4046 u8 cvlan_pcp[0x3]; 4047 u8 cvlan_id[0xc]; 4048 4049 u8 reserved_at_60[0x720]; 4050 4051 u8 sw_steering_vport_icm_address_rx[0x40]; 4052 4053 u8 sw_steering_vport_icm_address_tx[0x40]; 4054 }; 4055 4056 enum { 4057 MLX5_EQC_STATUS_OK = 0x0, 4058 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4059 }; 4060 4061 enum { 4062 MLX5_EQC_ST_ARMED = 0x9, 4063 MLX5_EQC_ST_FIRED = 0xa, 4064 }; 4065 4066 struct mlx5_ifc_eqc_bits { 4067 u8 status[0x4]; 4068 u8 reserved_at_4[0x9]; 4069 u8 ec[0x1]; 4070 u8 oi[0x1]; 4071 u8 reserved_at_f[0x5]; 4072 u8 st[0x4]; 4073 u8 reserved_at_18[0x8]; 4074 4075 u8 reserved_at_20[0x20]; 4076 4077 u8 reserved_at_40[0x14]; 4078 u8 page_offset[0x6]; 4079 u8 reserved_at_5a[0x6]; 4080 4081 u8 reserved_at_60[0x3]; 4082 u8 log_eq_size[0x5]; 4083 u8 uar_page[0x18]; 4084 4085 u8 reserved_at_80[0x20]; 4086 4087 u8 reserved_at_a0[0x14]; 4088 u8 intr[0xc]; 4089 4090 u8 reserved_at_c0[0x3]; 4091 u8 log_page_size[0x5]; 4092 u8 reserved_at_c8[0x18]; 4093 4094 u8 reserved_at_e0[0x60]; 4095 4096 u8 reserved_at_140[0x8]; 4097 u8 consumer_counter[0x18]; 4098 4099 u8 reserved_at_160[0x8]; 4100 u8 producer_counter[0x18]; 4101 4102 u8 reserved_at_180[0x80]; 4103 }; 4104 4105 enum { 4106 MLX5_DCTC_STATE_ACTIVE = 0x0, 4107 MLX5_DCTC_STATE_DRAINING = 0x1, 4108 MLX5_DCTC_STATE_DRAINED = 0x2, 4109 }; 4110 4111 enum { 4112 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4113 MLX5_DCTC_CS_RES_NA = 0x1, 4114 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4115 }; 4116 4117 enum { 4118 MLX5_DCTC_MTU_256_BYTES = 0x1, 4119 MLX5_DCTC_MTU_512_BYTES = 0x2, 4120 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4121 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4122 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4123 }; 4124 4125 struct mlx5_ifc_dctc_bits { 4126 u8 reserved_at_0[0x4]; 4127 u8 state[0x4]; 4128 u8 reserved_at_8[0x18]; 4129 4130 u8 reserved_at_20[0x8]; 4131 u8 user_index[0x18]; 4132 4133 u8 reserved_at_40[0x8]; 4134 u8 cqn[0x18]; 4135 4136 u8 counter_set_id[0x8]; 4137 u8 atomic_mode[0x4]; 4138 u8 rre[0x1]; 4139 u8 rwe[0x1]; 4140 u8 rae[0x1]; 4141 u8 atomic_like_write_en[0x1]; 4142 u8 latency_sensitive[0x1]; 4143 u8 rlky[0x1]; 4144 u8 free_ar[0x1]; 4145 u8 reserved_at_73[0xd]; 4146 4147 u8 reserved_at_80[0x8]; 4148 u8 cs_res[0x8]; 4149 u8 reserved_at_90[0x3]; 4150 u8 min_rnr_nak[0x5]; 4151 u8 reserved_at_98[0x8]; 4152 4153 u8 reserved_at_a0[0x8]; 4154 u8 srqn_xrqn[0x18]; 4155 4156 u8 reserved_at_c0[0x8]; 4157 u8 pd[0x18]; 4158 4159 u8 tclass[0x8]; 4160 u8 reserved_at_e8[0x4]; 4161 u8 flow_label[0x14]; 4162 4163 u8 dc_access_key[0x40]; 4164 4165 u8 reserved_at_140[0x5]; 4166 u8 mtu[0x3]; 4167 u8 port[0x8]; 4168 u8 pkey_index[0x10]; 4169 4170 u8 reserved_at_160[0x8]; 4171 u8 my_addr_index[0x8]; 4172 u8 reserved_at_170[0x8]; 4173 u8 hop_limit[0x8]; 4174 4175 u8 dc_access_key_violation_count[0x20]; 4176 4177 u8 reserved_at_1a0[0x14]; 4178 u8 dei_cfi[0x1]; 4179 u8 eth_prio[0x3]; 4180 u8 ecn[0x2]; 4181 u8 dscp[0x6]; 4182 4183 u8 reserved_at_1c0[0x20]; 4184 u8 ece[0x20]; 4185 }; 4186 4187 enum { 4188 MLX5_CQC_STATUS_OK = 0x0, 4189 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4190 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4191 }; 4192 4193 enum { 4194 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4195 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4196 }; 4197 4198 enum { 4199 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4200 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4201 MLX5_CQC_ST_FIRED = 0xa, 4202 }; 4203 4204 enum { 4205 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4206 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4207 MLX5_CQ_PERIOD_NUM_MODES 4208 }; 4209 4210 struct mlx5_ifc_cqc_bits { 4211 u8 status[0x4]; 4212 u8 reserved_at_4[0x2]; 4213 u8 dbr_umem_valid[0x1]; 4214 u8 apu_cq[0x1]; 4215 u8 cqe_sz[0x3]; 4216 u8 cc[0x1]; 4217 u8 reserved_at_c[0x1]; 4218 u8 scqe_break_moderation_en[0x1]; 4219 u8 oi[0x1]; 4220 u8 cq_period_mode[0x2]; 4221 u8 cqe_comp_en[0x1]; 4222 u8 mini_cqe_res_format[0x2]; 4223 u8 st[0x4]; 4224 u8 reserved_at_18[0x6]; 4225 u8 cqe_compression_layout[0x2]; 4226 4227 u8 reserved_at_20[0x20]; 4228 4229 u8 reserved_at_40[0x14]; 4230 u8 page_offset[0x6]; 4231 u8 reserved_at_5a[0x6]; 4232 4233 u8 reserved_at_60[0x3]; 4234 u8 log_cq_size[0x5]; 4235 u8 uar_page[0x18]; 4236 4237 u8 reserved_at_80[0x4]; 4238 u8 cq_period[0xc]; 4239 u8 cq_max_count[0x10]; 4240 4241 u8 c_eqn_or_apu_element[0x20]; 4242 4243 u8 reserved_at_c0[0x3]; 4244 u8 log_page_size[0x5]; 4245 u8 reserved_at_c8[0x18]; 4246 4247 u8 reserved_at_e0[0x20]; 4248 4249 u8 reserved_at_100[0x8]; 4250 u8 last_notified_index[0x18]; 4251 4252 u8 reserved_at_120[0x8]; 4253 u8 last_solicit_index[0x18]; 4254 4255 u8 reserved_at_140[0x8]; 4256 u8 consumer_counter[0x18]; 4257 4258 u8 reserved_at_160[0x8]; 4259 u8 producer_counter[0x18]; 4260 4261 u8 reserved_at_180[0x40]; 4262 4263 u8 dbr_addr[0x40]; 4264 }; 4265 4266 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4267 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4268 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4269 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4270 u8 reserved_at_0[0x800]; 4271 }; 4272 4273 struct mlx5_ifc_query_adapter_param_block_bits { 4274 u8 reserved_at_0[0xc0]; 4275 4276 u8 reserved_at_c0[0x8]; 4277 u8 ieee_vendor_id[0x18]; 4278 4279 u8 reserved_at_e0[0x10]; 4280 u8 vsd_vendor_id[0x10]; 4281 4282 u8 vsd[208][0x8]; 4283 4284 u8 vsd_contd_psid[16][0x8]; 4285 }; 4286 4287 enum { 4288 MLX5_XRQC_STATE_GOOD = 0x0, 4289 MLX5_XRQC_STATE_ERROR = 0x1, 4290 }; 4291 4292 enum { 4293 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4294 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4295 }; 4296 4297 enum { 4298 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4299 }; 4300 4301 struct mlx5_ifc_tag_matching_topology_context_bits { 4302 u8 log_matching_list_sz[0x4]; 4303 u8 reserved_at_4[0xc]; 4304 u8 append_next_index[0x10]; 4305 4306 u8 sw_phase_cnt[0x10]; 4307 u8 hw_phase_cnt[0x10]; 4308 4309 u8 reserved_at_40[0x40]; 4310 }; 4311 4312 struct mlx5_ifc_xrqc_bits { 4313 u8 state[0x4]; 4314 u8 rlkey[0x1]; 4315 u8 reserved_at_5[0xf]; 4316 u8 topology[0x4]; 4317 u8 reserved_at_18[0x4]; 4318 u8 offload[0x4]; 4319 4320 u8 reserved_at_20[0x8]; 4321 u8 user_index[0x18]; 4322 4323 u8 reserved_at_40[0x8]; 4324 u8 cqn[0x18]; 4325 4326 u8 reserved_at_60[0xa0]; 4327 4328 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4329 4330 u8 reserved_at_180[0x280]; 4331 4332 struct mlx5_ifc_wq_bits wq; 4333 }; 4334 4335 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4336 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4337 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4338 u8 reserved_at_0[0x20]; 4339 }; 4340 4341 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4342 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4343 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4344 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4345 u8 reserved_at_0[0x20]; 4346 }; 4347 4348 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4349 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4350 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4351 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4352 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4353 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4354 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4355 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4356 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4357 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4358 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4359 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4360 u8 reserved_at_0[0x7c0]; 4361 }; 4362 4363 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4364 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4365 u8 reserved_at_0[0x7c0]; 4366 }; 4367 4368 union mlx5_ifc_event_auto_bits { 4369 struct mlx5_ifc_comp_event_bits comp_event; 4370 struct mlx5_ifc_dct_events_bits dct_events; 4371 struct mlx5_ifc_qp_events_bits qp_events; 4372 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4373 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4374 struct mlx5_ifc_cq_error_bits cq_error; 4375 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4376 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4377 struct mlx5_ifc_gpio_event_bits gpio_event; 4378 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4379 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4380 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4381 u8 reserved_at_0[0xe0]; 4382 }; 4383 4384 struct mlx5_ifc_health_buffer_bits { 4385 u8 reserved_at_0[0x100]; 4386 4387 u8 assert_existptr[0x20]; 4388 4389 u8 assert_callra[0x20]; 4390 4391 u8 reserved_at_140[0x20]; 4392 4393 u8 time[0x20]; 4394 4395 u8 fw_version[0x20]; 4396 4397 u8 hw_id[0x20]; 4398 4399 u8 rfr[0x1]; 4400 u8 reserved_at_1c1[0x3]; 4401 u8 valid[0x1]; 4402 u8 severity[0x3]; 4403 u8 reserved_at_1c8[0x18]; 4404 4405 u8 irisc_index[0x8]; 4406 u8 synd[0x8]; 4407 u8 ext_synd[0x10]; 4408 }; 4409 4410 struct mlx5_ifc_register_loopback_control_bits { 4411 u8 no_lb[0x1]; 4412 u8 reserved_at_1[0x7]; 4413 u8 port[0x8]; 4414 u8 reserved_at_10[0x10]; 4415 4416 u8 reserved_at_20[0x60]; 4417 }; 4418 4419 struct mlx5_ifc_vport_tc_element_bits { 4420 u8 traffic_class[0x4]; 4421 u8 reserved_at_4[0xc]; 4422 u8 vport_number[0x10]; 4423 }; 4424 4425 struct mlx5_ifc_vport_element_bits { 4426 u8 reserved_at_0[0x10]; 4427 u8 vport_number[0x10]; 4428 }; 4429 4430 enum { 4431 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4432 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4433 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4434 }; 4435 4436 struct mlx5_ifc_tsar_element_bits { 4437 u8 reserved_at_0[0x8]; 4438 u8 tsar_type[0x8]; 4439 u8 reserved_at_10[0x10]; 4440 }; 4441 4442 enum { 4443 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4444 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4445 }; 4446 4447 struct mlx5_ifc_teardown_hca_out_bits { 4448 u8 status[0x8]; 4449 u8 reserved_at_8[0x18]; 4450 4451 u8 syndrome[0x20]; 4452 4453 u8 reserved_at_40[0x3f]; 4454 4455 u8 state[0x1]; 4456 }; 4457 4458 enum { 4459 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4460 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4461 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4462 }; 4463 4464 struct mlx5_ifc_teardown_hca_in_bits { 4465 u8 opcode[0x10]; 4466 u8 reserved_at_10[0x10]; 4467 4468 u8 reserved_at_20[0x10]; 4469 u8 op_mod[0x10]; 4470 4471 u8 reserved_at_40[0x10]; 4472 u8 profile[0x10]; 4473 4474 u8 reserved_at_60[0x20]; 4475 }; 4476 4477 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4478 u8 status[0x8]; 4479 u8 reserved_at_8[0x18]; 4480 4481 u8 syndrome[0x20]; 4482 4483 u8 reserved_at_40[0x40]; 4484 }; 4485 4486 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4487 u8 opcode[0x10]; 4488 u8 uid[0x10]; 4489 4490 u8 reserved_at_20[0x10]; 4491 u8 op_mod[0x10]; 4492 4493 u8 reserved_at_40[0x8]; 4494 u8 qpn[0x18]; 4495 4496 u8 reserved_at_60[0x20]; 4497 4498 u8 opt_param_mask[0x20]; 4499 4500 u8 reserved_at_a0[0x20]; 4501 4502 struct mlx5_ifc_qpc_bits qpc; 4503 4504 u8 reserved_at_800[0x80]; 4505 }; 4506 4507 struct mlx5_ifc_sqd2rts_qp_out_bits { 4508 u8 status[0x8]; 4509 u8 reserved_at_8[0x18]; 4510 4511 u8 syndrome[0x20]; 4512 4513 u8 reserved_at_40[0x40]; 4514 }; 4515 4516 struct mlx5_ifc_sqd2rts_qp_in_bits { 4517 u8 opcode[0x10]; 4518 u8 uid[0x10]; 4519 4520 u8 reserved_at_20[0x10]; 4521 u8 op_mod[0x10]; 4522 4523 u8 reserved_at_40[0x8]; 4524 u8 qpn[0x18]; 4525 4526 u8 reserved_at_60[0x20]; 4527 4528 u8 opt_param_mask[0x20]; 4529 4530 u8 reserved_at_a0[0x20]; 4531 4532 struct mlx5_ifc_qpc_bits qpc; 4533 4534 u8 reserved_at_800[0x80]; 4535 }; 4536 4537 struct mlx5_ifc_set_roce_address_out_bits { 4538 u8 status[0x8]; 4539 u8 reserved_at_8[0x18]; 4540 4541 u8 syndrome[0x20]; 4542 4543 u8 reserved_at_40[0x40]; 4544 }; 4545 4546 struct mlx5_ifc_set_roce_address_in_bits { 4547 u8 opcode[0x10]; 4548 u8 reserved_at_10[0x10]; 4549 4550 u8 reserved_at_20[0x10]; 4551 u8 op_mod[0x10]; 4552 4553 u8 roce_address_index[0x10]; 4554 u8 reserved_at_50[0xc]; 4555 u8 vhca_port_num[0x4]; 4556 4557 u8 reserved_at_60[0x20]; 4558 4559 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4560 }; 4561 4562 struct mlx5_ifc_set_mad_demux_out_bits { 4563 u8 status[0x8]; 4564 u8 reserved_at_8[0x18]; 4565 4566 u8 syndrome[0x20]; 4567 4568 u8 reserved_at_40[0x40]; 4569 }; 4570 4571 enum { 4572 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4573 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4574 }; 4575 4576 struct mlx5_ifc_set_mad_demux_in_bits { 4577 u8 opcode[0x10]; 4578 u8 reserved_at_10[0x10]; 4579 4580 u8 reserved_at_20[0x10]; 4581 u8 op_mod[0x10]; 4582 4583 u8 reserved_at_40[0x20]; 4584 4585 u8 reserved_at_60[0x6]; 4586 u8 demux_mode[0x2]; 4587 u8 reserved_at_68[0x18]; 4588 }; 4589 4590 struct mlx5_ifc_set_l2_table_entry_out_bits { 4591 u8 status[0x8]; 4592 u8 reserved_at_8[0x18]; 4593 4594 u8 syndrome[0x20]; 4595 4596 u8 reserved_at_40[0x40]; 4597 }; 4598 4599 struct mlx5_ifc_set_l2_table_entry_in_bits { 4600 u8 opcode[0x10]; 4601 u8 reserved_at_10[0x10]; 4602 4603 u8 reserved_at_20[0x10]; 4604 u8 op_mod[0x10]; 4605 4606 u8 reserved_at_40[0x60]; 4607 4608 u8 reserved_at_a0[0x8]; 4609 u8 table_index[0x18]; 4610 4611 u8 reserved_at_c0[0x20]; 4612 4613 u8 reserved_at_e0[0x13]; 4614 u8 vlan_valid[0x1]; 4615 u8 vlan[0xc]; 4616 4617 struct mlx5_ifc_mac_address_layout_bits mac_address; 4618 4619 u8 reserved_at_140[0xc0]; 4620 }; 4621 4622 struct mlx5_ifc_set_issi_out_bits { 4623 u8 status[0x8]; 4624 u8 reserved_at_8[0x18]; 4625 4626 u8 syndrome[0x20]; 4627 4628 u8 reserved_at_40[0x40]; 4629 }; 4630 4631 struct mlx5_ifc_set_issi_in_bits { 4632 u8 opcode[0x10]; 4633 u8 reserved_at_10[0x10]; 4634 4635 u8 reserved_at_20[0x10]; 4636 u8 op_mod[0x10]; 4637 4638 u8 reserved_at_40[0x10]; 4639 u8 current_issi[0x10]; 4640 4641 u8 reserved_at_60[0x20]; 4642 }; 4643 4644 struct mlx5_ifc_set_hca_cap_out_bits { 4645 u8 status[0x8]; 4646 u8 reserved_at_8[0x18]; 4647 4648 u8 syndrome[0x20]; 4649 4650 u8 reserved_at_40[0x40]; 4651 }; 4652 4653 struct mlx5_ifc_set_hca_cap_in_bits { 4654 u8 opcode[0x10]; 4655 u8 reserved_at_10[0x10]; 4656 4657 u8 reserved_at_20[0x10]; 4658 u8 op_mod[0x10]; 4659 4660 u8 other_function[0x1]; 4661 u8 reserved_at_41[0xf]; 4662 u8 function_id[0x10]; 4663 4664 u8 reserved_at_60[0x20]; 4665 4666 union mlx5_ifc_hca_cap_union_bits capability; 4667 }; 4668 4669 enum { 4670 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4671 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4672 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4673 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4674 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4675 }; 4676 4677 struct mlx5_ifc_set_fte_out_bits { 4678 u8 status[0x8]; 4679 u8 reserved_at_8[0x18]; 4680 4681 u8 syndrome[0x20]; 4682 4683 u8 reserved_at_40[0x40]; 4684 }; 4685 4686 struct mlx5_ifc_set_fte_in_bits { 4687 u8 opcode[0x10]; 4688 u8 reserved_at_10[0x10]; 4689 4690 u8 reserved_at_20[0x10]; 4691 u8 op_mod[0x10]; 4692 4693 u8 other_vport[0x1]; 4694 u8 reserved_at_41[0xf]; 4695 u8 vport_number[0x10]; 4696 4697 u8 reserved_at_60[0x20]; 4698 4699 u8 table_type[0x8]; 4700 u8 reserved_at_88[0x18]; 4701 4702 u8 reserved_at_a0[0x8]; 4703 u8 table_id[0x18]; 4704 4705 u8 ignore_flow_level[0x1]; 4706 u8 reserved_at_c1[0x17]; 4707 u8 modify_enable_mask[0x8]; 4708 4709 u8 reserved_at_e0[0x20]; 4710 4711 u8 flow_index[0x20]; 4712 4713 u8 reserved_at_120[0xe0]; 4714 4715 struct mlx5_ifc_flow_context_bits flow_context; 4716 }; 4717 4718 struct mlx5_ifc_rts2rts_qp_out_bits { 4719 u8 status[0x8]; 4720 u8 reserved_at_8[0x18]; 4721 4722 u8 syndrome[0x20]; 4723 4724 u8 reserved_at_40[0x20]; 4725 u8 ece[0x20]; 4726 }; 4727 4728 struct mlx5_ifc_rts2rts_qp_in_bits { 4729 u8 opcode[0x10]; 4730 u8 uid[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x8]; 4736 u8 qpn[0x18]; 4737 4738 u8 reserved_at_60[0x20]; 4739 4740 u8 opt_param_mask[0x20]; 4741 4742 u8 ece[0x20]; 4743 4744 struct mlx5_ifc_qpc_bits qpc; 4745 4746 u8 reserved_at_800[0x80]; 4747 }; 4748 4749 struct mlx5_ifc_rtr2rts_qp_out_bits { 4750 u8 status[0x8]; 4751 u8 reserved_at_8[0x18]; 4752 4753 u8 syndrome[0x20]; 4754 4755 u8 reserved_at_40[0x20]; 4756 u8 ece[0x20]; 4757 }; 4758 4759 struct mlx5_ifc_rtr2rts_qp_in_bits { 4760 u8 opcode[0x10]; 4761 u8 uid[0x10]; 4762 4763 u8 reserved_at_20[0x10]; 4764 u8 op_mod[0x10]; 4765 4766 u8 reserved_at_40[0x8]; 4767 u8 qpn[0x18]; 4768 4769 u8 reserved_at_60[0x20]; 4770 4771 u8 opt_param_mask[0x20]; 4772 4773 u8 ece[0x20]; 4774 4775 struct mlx5_ifc_qpc_bits qpc; 4776 4777 u8 reserved_at_800[0x80]; 4778 }; 4779 4780 struct mlx5_ifc_rst2init_qp_out_bits { 4781 u8 status[0x8]; 4782 u8 reserved_at_8[0x18]; 4783 4784 u8 syndrome[0x20]; 4785 4786 u8 reserved_at_40[0x20]; 4787 u8 ece[0x20]; 4788 }; 4789 4790 struct mlx5_ifc_rst2init_qp_in_bits { 4791 u8 opcode[0x10]; 4792 u8 uid[0x10]; 4793 4794 u8 reserved_at_20[0x10]; 4795 u8 op_mod[0x10]; 4796 4797 u8 reserved_at_40[0x8]; 4798 u8 qpn[0x18]; 4799 4800 u8 reserved_at_60[0x20]; 4801 4802 u8 opt_param_mask[0x20]; 4803 4804 u8 ece[0x20]; 4805 4806 struct mlx5_ifc_qpc_bits qpc; 4807 4808 u8 reserved_at_800[0x80]; 4809 }; 4810 4811 struct mlx5_ifc_query_xrq_out_bits { 4812 u8 status[0x8]; 4813 u8 reserved_at_8[0x18]; 4814 4815 u8 syndrome[0x20]; 4816 4817 u8 reserved_at_40[0x40]; 4818 4819 struct mlx5_ifc_xrqc_bits xrq_context; 4820 }; 4821 4822 struct mlx5_ifc_query_xrq_in_bits { 4823 u8 opcode[0x10]; 4824 u8 reserved_at_10[0x10]; 4825 4826 u8 reserved_at_20[0x10]; 4827 u8 op_mod[0x10]; 4828 4829 u8 reserved_at_40[0x8]; 4830 u8 xrqn[0x18]; 4831 4832 u8 reserved_at_60[0x20]; 4833 }; 4834 4835 struct mlx5_ifc_query_xrc_srq_out_bits { 4836 u8 status[0x8]; 4837 u8 reserved_at_8[0x18]; 4838 4839 u8 syndrome[0x20]; 4840 4841 u8 reserved_at_40[0x40]; 4842 4843 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4844 4845 u8 reserved_at_280[0x600]; 4846 4847 u8 pas[][0x40]; 4848 }; 4849 4850 struct mlx5_ifc_query_xrc_srq_in_bits { 4851 u8 opcode[0x10]; 4852 u8 reserved_at_10[0x10]; 4853 4854 u8 reserved_at_20[0x10]; 4855 u8 op_mod[0x10]; 4856 4857 u8 reserved_at_40[0x8]; 4858 u8 xrc_srqn[0x18]; 4859 4860 u8 reserved_at_60[0x20]; 4861 }; 4862 4863 enum { 4864 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4865 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4866 }; 4867 4868 struct mlx5_ifc_query_vport_state_out_bits { 4869 u8 status[0x8]; 4870 u8 reserved_at_8[0x18]; 4871 4872 u8 syndrome[0x20]; 4873 4874 u8 reserved_at_40[0x20]; 4875 4876 u8 reserved_at_60[0x18]; 4877 u8 admin_state[0x4]; 4878 u8 state[0x4]; 4879 }; 4880 4881 enum { 4882 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4883 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4884 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4885 }; 4886 4887 struct mlx5_ifc_arm_monitor_counter_in_bits { 4888 u8 opcode[0x10]; 4889 u8 uid[0x10]; 4890 4891 u8 reserved_at_20[0x10]; 4892 u8 op_mod[0x10]; 4893 4894 u8 reserved_at_40[0x20]; 4895 4896 u8 reserved_at_60[0x20]; 4897 }; 4898 4899 struct mlx5_ifc_arm_monitor_counter_out_bits { 4900 u8 status[0x8]; 4901 u8 reserved_at_8[0x18]; 4902 4903 u8 syndrome[0x20]; 4904 4905 u8 reserved_at_40[0x40]; 4906 }; 4907 4908 enum { 4909 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4910 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4911 }; 4912 4913 enum mlx5_monitor_counter_ppcnt { 4914 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4915 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4916 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4917 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4918 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4919 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4920 }; 4921 4922 enum { 4923 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4924 }; 4925 4926 struct mlx5_ifc_monitor_counter_output_bits { 4927 u8 reserved_at_0[0x4]; 4928 u8 type[0x4]; 4929 u8 reserved_at_8[0x8]; 4930 u8 counter[0x10]; 4931 4932 u8 counter_group_id[0x20]; 4933 }; 4934 4935 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4936 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4937 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4938 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4939 4940 struct mlx5_ifc_set_monitor_counter_in_bits { 4941 u8 opcode[0x10]; 4942 u8 uid[0x10]; 4943 4944 u8 reserved_at_20[0x10]; 4945 u8 op_mod[0x10]; 4946 4947 u8 reserved_at_40[0x10]; 4948 u8 num_of_counters[0x10]; 4949 4950 u8 reserved_at_60[0x20]; 4951 4952 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4953 }; 4954 4955 struct mlx5_ifc_set_monitor_counter_out_bits { 4956 u8 status[0x8]; 4957 u8 reserved_at_8[0x18]; 4958 4959 u8 syndrome[0x20]; 4960 4961 u8 reserved_at_40[0x40]; 4962 }; 4963 4964 struct mlx5_ifc_query_vport_state_in_bits { 4965 u8 opcode[0x10]; 4966 u8 reserved_at_10[0x10]; 4967 4968 u8 reserved_at_20[0x10]; 4969 u8 op_mod[0x10]; 4970 4971 u8 other_vport[0x1]; 4972 u8 reserved_at_41[0xf]; 4973 u8 vport_number[0x10]; 4974 4975 u8 reserved_at_60[0x20]; 4976 }; 4977 4978 struct mlx5_ifc_query_vnic_env_out_bits { 4979 u8 status[0x8]; 4980 u8 reserved_at_8[0x18]; 4981 4982 u8 syndrome[0x20]; 4983 4984 u8 reserved_at_40[0x40]; 4985 4986 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4987 }; 4988 4989 enum { 4990 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4991 }; 4992 4993 struct mlx5_ifc_query_vnic_env_in_bits { 4994 u8 opcode[0x10]; 4995 u8 reserved_at_10[0x10]; 4996 4997 u8 reserved_at_20[0x10]; 4998 u8 op_mod[0x10]; 4999 5000 u8 other_vport[0x1]; 5001 u8 reserved_at_41[0xf]; 5002 u8 vport_number[0x10]; 5003 5004 u8 reserved_at_60[0x20]; 5005 }; 5006 5007 struct mlx5_ifc_query_vport_counter_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_at_8[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_at_40[0x40]; 5014 5015 struct mlx5_ifc_traffic_counter_bits received_errors; 5016 5017 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5018 5019 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5020 5021 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5022 5023 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5024 5025 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5026 5027 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5028 5029 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5030 5031 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5032 5033 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5034 5035 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5036 5037 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5038 5039 u8 reserved_at_680[0xa00]; 5040 }; 5041 5042 enum { 5043 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5044 }; 5045 5046 struct mlx5_ifc_query_vport_counter_in_bits { 5047 u8 opcode[0x10]; 5048 u8 reserved_at_10[0x10]; 5049 5050 u8 reserved_at_20[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 other_vport[0x1]; 5054 u8 reserved_at_41[0xb]; 5055 u8 port_num[0x4]; 5056 u8 vport_number[0x10]; 5057 5058 u8 reserved_at_60[0x60]; 5059 5060 u8 clear[0x1]; 5061 u8 reserved_at_c1[0x1f]; 5062 5063 u8 reserved_at_e0[0x20]; 5064 }; 5065 5066 struct mlx5_ifc_query_tis_out_bits { 5067 u8 status[0x8]; 5068 u8 reserved_at_8[0x18]; 5069 5070 u8 syndrome[0x20]; 5071 5072 u8 reserved_at_40[0x40]; 5073 5074 struct mlx5_ifc_tisc_bits tis_context; 5075 }; 5076 5077 struct mlx5_ifc_query_tis_in_bits { 5078 u8 opcode[0x10]; 5079 u8 reserved_at_10[0x10]; 5080 5081 u8 reserved_at_20[0x10]; 5082 u8 op_mod[0x10]; 5083 5084 u8 reserved_at_40[0x8]; 5085 u8 tisn[0x18]; 5086 5087 u8 reserved_at_60[0x20]; 5088 }; 5089 5090 struct mlx5_ifc_query_tir_out_bits { 5091 u8 status[0x8]; 5092 u8 reserved_at_8[0x18]; 5093 5094 u8 syndrome[0x20]; 5095 5096 u8 reserved_at_40[0xc0]; 5097 5098 struct mlx5_ifc_tirc_bits tir_context; 5099 }; 5100 5101 struct mlx5_ifc_query_tir_in_bits { 5102 u8 opcode[0x10]; 5103 u8 reserved_at_10[0x10]; 5104 5105 u8 reserved_at_20[0x10]; 5106 u8 op_mod[0x10]; 5107 5108 u8 reserved_at_40[0x8]; 5109 u8 tirn[0x18]; 5110 5111 u8 reserved_at_60[0x20]; 5112 }; 5113 5114 struct mlx5_ifc_query_srq_out_bits { 5115 u8 status[0x8]; 5116 u8 reserved_at_8[0x18]; 5117 5118 u8 syndrome[0x20]; 5119 5120 u8 reserved_at_40[0x40]; 5121 5122 struct mlx5_ifc_srqc_bits srq_context_entry; 5123 5124 u8 reserved_at_280[0x600]; 5125 5126 u8 pas[][0x40]; 5127 }; 5128 5129 struct mlx5_ifc_query_srq_in_bits { 5130 u8 opcode[0x10]; 5131 u8 reserved_at_10[0x10]; 5132 5133 u8 reserved_at_20[0x10]; 5134 u8 op_mod[0x10]; 5135 5136 u8 reserved_at_40[0x8]; 5137 u8 srqn[0x18]; 5138 5139 u8 reserved_at_60[0x20]; 5140 }; 5141 5142 struct mlx5_ifc_query_sq_out_bits { 5143 u8 status[0x8]; 5144 u8 reserved_at_8[0x18]; 5145 5146 u8 syndrome[0x20]; 5147 5148 u8 reserved_at_40[0xc0]; 5149 5150 struct mlx5_ifc_sqc_bits sq_context; 5151 }; 5152 5153 struct mlx5_ifc_query_sq_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 reserved_at_40[0x8]; 5161 u8 sqn[0x18]; 5162 5163 u8 reserved_at_60[0x20]; 5164 }; 5165 5166 struct mlx5_ifc_query_special_contexts_out_bits { 5167 u8 status[0x8]; 5168 u8 reserved_at_8[0x18]; 5169 5170 u8 syndrome[0x20]; 5171 5172 u8 dump_fill_mkey[0x20]; 5173 5174 u8 resd_lkey[0x20]; 5175 5176 u8 null_mkey[0x20]; 5177 5178 u8 reserved_at_a0[0x60]; 5179 }; 5180 5181 struct mlx5_ifc_query_special_contexts_in_bits { 5182 u8 opcode[0x10]; 5183 u8 reserved_at_10[0x10]; 5184 5185 u8 reserved_at_20[0x10]; 5186 u8 op_mod[0x10]; 5187 5188 u8 reserved_at_40[0x40]; 5189 }; 5190 5191 struct mlx5_ifc_query_scheduling_element_out_bits { 5192 u8 opcode[0x10]; 5193 u8 reserved_at_10[0x10]; 5194 5195 u8 reserved_at_20[0x10]; 5196 u8 op_mod[0x10]; 5197 5198 u8 reserved_at_40[0xc0]; 5199 5200 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5201 5202 u8 reserved_at_300[0x100]; 5203 }; 5204 5205 enum { 5206 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5207 SCHEDULING_HIERARCHY_NIC = 0x3, 5208 }; 5209 5210 struct mlx5_ifc_query_scheduling_element_in_bits { 5211 u8 opcode[0x10]; 5212 u8 reserved_at_10[0x10]; 5213 5214 u8 reserved_at_20[0x10]; 5215 u8 op_mod[0x10]; 5216 5217 u8 scheduling_hierarchy[0x8]; 5218 u8 reserved_at_48[0x18]; 5219 5220 u8 scheduling_element_id[0x20]; 5221 5222 u8 reserved_at_80[0x180]; 5223 }; 5224 5225 struct mlx5_ifc_query_rqt_out_bits { 5226 u8 status[0x8]; 5227 u8 reserved_at_8[0x18]; 5228 5229 u8 syndrome[0x20]; 5230 5231 u8 reserved_at_40[0xc0]; 5232 5233 struct mlx5_ifc_rqtc_bits rqt_context; 5234 }; 5235 5236 struct mlx5_ifc_query_rqt_in_bits { 5237 u8 opcode[0x10]; 5238 u8 reserved_at_10[0x10]; 5239 5240 u8 reserved_at_20[0x10]; 5241 u8 op_mod[0x10]; 5242 5243 u8 reserved_at_40[0x8]; 5244 u8 rqtn[0x18]; 5245 5246 u8 reserved_at_60[0x20]; 5247 }; 5248 5249 struct mlx5_ifc_query_rq_out_bits { 5250 u8 status[0x8]; 5251 u8 reserved_at_8[0x18]; 5252 5253 u8 syndrome[0x20]; 5254 5255 u8 reserved_at_40[0xc0]; 5256 5257 struct mlx5_ifc_rqc_bits rq_context; 5258 }; 5259 5260 struct mlx5_ifc_query_rq_in_bits { 5261 u8 opcode[0x10]; 5262 u8 reserved_at_10[0x10]; 5263 5264 u8 reserved_at_20[0x10]; 5265 u8 op_mod[0x10]; 5266 5267 u8 reserved_at_40[0x8]; 5268 u8 rqn[0x18]; 5269 5270 u8 reserved_at_60[0x20]; 5271 }; 5272 5273 struct mlx5_ifc_query_roce_address_out_bits { 5274 u8 status[0x8]; 5275 u8 reserved_at_8[0x18]; 5276 5277 u8 syndrome[0x20]; 5278 5279 u8 reserved_at_40[0x40]; 5280 5281 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5282 }; 5283 5284 struct mlx5_ifc_query_roce_address_in_bits { 5285 u8 opcode[0x10]; 5286 u8 reserved_at_10[0x10]; 5287 5288 u8 reserved_at_20[0x10]; 5289 u8 op_mod[0x10]; 5290 5291 u8 roce_address_index[0x10]; 5292 u8 reserved_at_50[0xc]; 5293 u8 vhca_port_num[0x4]; 5294 5295 u8 reserved_at_60[0x20]; 5296 }; 5297 5298 struct mlx5_ifc_query_rmp_out_bits { 5299 u8 status[0x8]; 5300 u8 reserved_at_8[0x18]; 5301 5302 u8 syndrome[0x20]; 5303 5304 u8 reserved_at_40[0xc0]; 5305 5306 struct mlx5_ifc_rmpc_bits rmp_context; 5307 }; 5308 5309 struct mlx5_ifc_query_rmp_in_bits { 5310 u8 opcode[0x10]; 5311 u8 reserved_at_10[0x10]; 5312 5313 u8 reserved_at_20[0x10]; 5314 u8 op_mod[0x10]; 5315 5316 u8 reserved_at_40[0x8]; 5317 u8 rmpn[0x18]; 5318 5319 u8 reserved_at_60[0x20]; 5320 }; 5321 5322 struct mlx5_ifc_query_qp_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_at_40[0x40]; 5329 5330 u8 opt_param_mask[0x20]; 5331 5332 u8 ece[0x20]; 5333 5334 struct mlx5_ifc_qpc_bits qpc; 5335 5336 u8 reserved_at_800[0x80]; 5337 5338 u8 pas[][0x40]; 5339 }; 5340 5341 struct mlx5_ifc_query_qp_in_bits { 5342 u8 opcode[0x10]; 5343 u8 reserved_at_10[0x10]; 5344 5345 u8 reserved_at_20[0x10]; 5346 u8 op_mod[0x10]; 5347 5348 u8 reserved_at_40[0x8]; 5349 u8 qpn[0x18]; 5350 5351 u8 reserved_at_60[0x20]; 5352 }; 5353 5354 struct mlx5_ifc_query_q_counter_out_bits { 5355 u8 status[0x8]; 5356 u8 reserved_at_8[0x18]; 5357 5358 u8 syndrome[0x20]; 5359 5360 u8 reserved_at_40[0x40]; 5361 5362 u8 rx_write_requests[0x20]; 5363 5364 u8 reserved_at_a0[0x20]; 5365 5366 u8 rx_read_requests[0x20]; 5367 5368 u8 reserved_at_e0[0x20]; 5369 5370 u8 rx_atomic_requests[0x20]; 5371 5372 u8 reserved_at_120[0x20]; 5373 5374 u8 rx_dct_connect[0x20]; 5375 5376 u8 reserved_at_160[0x20]; 5377 5378 u8 out_of_buffer[0x20]; 5379 5380 u8 reserved_at_1a0[0x20]; 5381 5382 u8 out_of_sequence[0x20]; 5383 5384 u8 reserved_at_1e0[0x20]; 5385 5386 u8 duplicate_request[0x20]; 5387 5388 u8 reserved_at_220[0x20]; 5389 5390 u8 rnr_nak_retry_err[0x20]; 5391 5392 u8 reserved_at_260[0x20]; 5393 5394 u8 packet_seq_err[0x20]; 5395 5396 u8 reserved_at_2a0[0x20]; 5397 5398 u8 implied_nak_seq_err[0x20]; 5399 5400 u8 reserved_at_2e0[0x20]; 5401 5402 u8 local_ack_timeout_err[0x20]; 5403 5404 u8 reserved_at_320[0xa0]; 5405 5406 u8 resp_local_length_error[0x20]; 5407 5408 u8 req_local_length_error[0x20]; 5409 5410 u8 resp_local_qp_error[0x20]; 5411 5412 u8 local_operation_error[0x20]; 5413 5414 u8 resp_local_protection[0x20]; 5415 5416 u8 req_local_protection[0x20]; 5417 5418 u8 resp_cqe_error[0x20]; 5419 5420 u8 req_cqe_error[0x20]; 5421 5422 u8 req_mw_binding[0x20]; 5423 5424 u8 req_bad_response[0x20]; 5425 5426 u8 req_remote_invalid_request[0x20]; 5427 5428 u8 resp_remote_invalid_request[0x20]; 5429 5430 u8 req_remote_access_errors[0x20]; 5431 5432 u8 resp_remote_access_errors[0x20]; 5433 5434 u8 req_remote_operation_errors[0x20]; 5435 5436 u8 req_transport_retries_exceeded[0x20]; 5437 5438 u8 cq_overflow[0x20]; 5439 5440 u8 resp_cqe_flush_error[0x20]; 5441 5442 u8 req_cqe_flush_error[0x20]; 5443 5444 u8 reserved_at_620[0x20]; 5445 5446 u8 roce_adp_retrans[0x20]; 5447 5448 u8 roce_adp_retrans_to[0x20]; 5449 5450 u8 roce_slow_restart[0x20]; 5451 5452 u8 roce_slow_restart_cnps[0x20]; 5453 5454 u8 roce_slow_restart_trans[0x20]; 5455 5456 u8 reserved_at_6e0[0x120]; 5457 }; 5458 5459 struct mlx5_ifc_query_q_counter_in_bits { 5460 u8 opcode[0x10]; 5461 u8 reserved_at_10[0x10]; 5462 5463 u8 reserved_at_20[0x10]; 5464 u8 op_mod[0x10]; 5465 5466 u8 reserved_at_40[0x80]; 5467 5468 u8 clear[0x1]; 5469 u8 reserved_at_c1[0x1f]; 5470 5471 u8 reserved_at_e0[0x18]; 5472 u8 counter_set_id[0x8]; 5473 }; 5474 5475 struct mlx5_ifc_query_pages_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_at_8[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 embedded_cpu_function[0x1]; 5482 u8 reserved_at_41[0xf]; 5483 u8 function_id[0x10]; 5484 5485 u8 num_pages[0x20]; 5486 }; 5487 5488 enum { 5489 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5490 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5491 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5492 }; 5493 5494 struct mlx5_ifc_query_pages_in_bits { 5495 u8 opcode[0x10]; 5496 u8 reserved_at_10[0x10]; 5497 5498 u8 reserved_at_20[0x10]; 5499 u8 op_mod[0x10]; 5500 5501 u8 embedded_cpu_function[0x1]; 5502 u8 reserved_at_41[0xf]; 5503 u8 function_id[0x10]; 5504 5505 u8 reserved_at_60[0x20]; 5506 }; 5507 5508 struct mlx5_ifc_query_nic_vport_context_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_at_8[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 5514 u8 reserved_at_40[0x40]; 5515 5516 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5517 }; 5518 5519 struct mlx5_ifc_query_nic_vport_context_in_bits { 5520 u8 opcode[0x10]; 5521 u8 reserved_at_10[0x10]; 5522 5523 u8 reserved_at_20[0x10]; 5524 u8 op_mod[0x10]; 5525 5526 u8 other_vport[0x1]; 5527 u8 reserved_at_41[0xf]; 5528 u8 vport_number[0x10]; 5529 5530 u8 reserved_at_60[0x5]; 5531 u8 allowed_list_type[0x3]; 5532 u8 reserved_at_68[0x18]; 5533 }; 5534 5535 struct mlx5_ifc_query_mkey_out_bits { 5536 u8 status[0x8]; 5537 u8 reserved_at_8[0x18]; 5538 5539 u8 syndrome[0x20]; 5540 5541 u8 reserved_at_40[0x40]; 5542 5543 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5544 5545 u8 reserved_at_280[0x600]; 5546 5547 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5548 5549 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5550 }; 5551 5552 struct mlx5_ifc_query_mkey_in_bits { 5553 u8 opcode[0x10]; 5554 u8 reserved_at_10[0x10]; 5555 5556 u8 reserved_at_20[0x10]; 5557 u8 op_mod[0x10]; 5558 5559 u8 reserved_at_40[0x8]; 5560 u8 mkey_index[0x18]; 5561 5562 u8 pg_access[0x1]; 5563 u8 reserved_at_61[0x1f]; 5564 }; 5565 5566 struct mlx5_ifc_query_mad_demux_out_bits { 5567 u8 status[0x8]; 5568 u8 reserved_at_8[0x18]; 5569 5570 u8 syndrome[0x20]; 5571 5572 u8 reserved_at_40[0x40]; 5573 5574 u8 mad_dumux_parameters_block[0x20]; 5575 }; 5576 5577 struct mlx5_ifc_query_mad_demux_in_bits { 5578 u8 opcode[0x10]; 5579 u8 reserved_at_10[0x10]; 5580 5581 u8 reserved_at_20[0x10]; 5582 u8 op_mod[0x10]; 5583 5584 u8 reserved_at_40[0x40]; 5585 }; 5586 5587 struct mlx5_ifc_query_l2_table_entry_out_bits { 5588 u8 status[0x8]; 5589 u8 reserved_at_8[0x18]; 5590 5591 u8 syndrome[0x20]; 5592 5593 u8 reserved_at_40[0xa0]; 5594 5595 u8 reserved_at_e0[0x13]; 5596 u8 vlan_valid[0x1]; 5597 u8 vlan[0xc]; 5598 5599 struct mlx5_ifc_mac_address_layout_bits mac_address; 5600 5601 u8 reserved_at_140[0xc0]; 5602 }; 5603 5604 struct mlx5_ifc_query_l2_table_entry_in_bits { 5605 u8 opcode[0x10]; 5606 u8 reserved_at_10[0x10]; 5607 5608 u8 reserved_at_20[0x10]; 5609 u8 op_mod[0x10]; 5610 5611 u8 reserved_at_40[0x60]; 5612 5613 u8 reserved_at_a0[0x8]; 5614 u8 table_index[0x18]; 5615 5616 u8 reserved_at_c0[0x140]; 5617 }; 5618 5619 struct mlx5_ifc_query_issi_out_bits { 5620 u8 status[0x8]; 5621 u8 reserved_at_8[0x18]; 5622 5623 u8 syndrome[0x20]; 5624 5625 u8 reserved_at_40[0x10]; 5626 u8 current_issi[0x10]; 5627 5628 u8 reserved_at_60[0xa0]; 5629 5630 u8 reserved_at_100[76][0x8]; 5631 u8 supported_issi_dw0[0x20]; 5632 }; 5633 5634 struct mlx5_ifc_query_issi_in_bits { 5635 u8 opcode[0x10]; 5636 u8 reserved_at_10[0x10]; 5637 5638 u8 reserved_at_20[0x10]; 5639 u8 op_mod[0x10]; 5640 5641 u8 reserved_at_40[0x40]; 5642 }; 5643 5644 struct mlx5_ifc_set_driver_version_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_0[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 u8 reserved_1[0x40]; 5650 }; 5651 5652 struct mlx5_ifc_set_driver_version_in_bits { 5653 u8 opcode[0x10]; 5654 u8 reserved_0[0x10]; 5655 5656 u8 reserved_1[0x10]; 5657 u8 op_mod[0x10]; 5658 5659 u8 reserved_2[0x40]; 5660 u8 driver_version[64][0x8]; 5661 }; 5662 5663 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5664 u8 status[0x8]; 5665 u8 reserved_at_8[0x18]; 5666 5667 u8 syndrome[0x20]; 5668 5669 u8 reserved_at_40[0x40]; 5670 5671 struct mlx5_ifc_pkey_bits pkey[]; 5672 }; 5673 5674 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5675 u8 opcode[0x10]; 5676 u8 reserved_at_10[0x10]; 5677 5678 u8 reserved_at_20[0x10]; 5679 u8 op_mod[0x10]; 5680 5681 u8 other_vport[0x1]; 5682 u8 reserved_at_41[0xb]; 5683 u8 port_num[0x4]; 5684 u8 vport_number[0x10]; 5685 5686 u8 reserved_at_60[0x10]; 5687 u8 pkey_index[0x10]; 5688 }; 5689 5690 enum { 5691 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5692 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5693 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5694 }; 5695 5696 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5697 u8 status[0x8]; 5698 u8 reserved_at_8[0x18]; 5699 5700 u8 syndrome[0x20]; 5701 5702 u8 reserved_at_40[0x20]; 5703 5704 u8 gids_num[0x10]; 5705 u8 reserved_at_70[0x10]; 5706 5707 struct mlx5_ifc_array128_auto_bits gid[]; 5708 }; 5709 5710 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5711 u8 opcode[0x10]; 5712 u8 reserved_at_10[0x10]; 5713 5714 u8 reserved_at_20[0x10]; 5715 u8 op_mod[0x10]; 5716 5717 u8 other_vport[0x1]; 5718 u8 reserved_at_41[0xb]; 5719 u8 port_num[0x4]; 5720 u8 vport_number[0x10]; 5721 5722 u8 reserved_at_60[0x10]; 5723 u8 gid_index[0x10]; 5724 }; 5725 5726 struct mlx5_ifc_query_hca_vport_context_out_bits { 5727 u8 status[0x8]; 5728 u8 reserved_at_8[0x18]; 5729 5730 u8 syndrome[0x20]; 5731 5732 u8 reserved_at_40[0x40]; 5733 5734 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5735 }; 5736 5737 struct mlx5_ifc_query_hca_vport_context_in_bits { 5738 u8 opcode[0x10]; 5739 u8 reserved_at_10[0x10]; 5740 5741 u8 reserved_at_20[0x10]; 5742 u8 op_mod[0x10]; 5743 5744 u8 other_vport[0x1]; 5745 u8 reserved_at_41[0xb]; 5746 u8 port_num[0x4]; 5747 u8 vport_number[0x10]; 5748 5749 u8 reserved_at_60[0x20]; 5750 }; 5751 5752 struct mlx5_ifc_query_hca_cap_out_bits { 5753 u8 status[0x8]; 5754 u8 reserved_at_8[0x18]; 5755 5756 u8 syndrome[0x20]; 5757 5758 u8 reserved_at_40[0x40]; 5759 5760 union mlx5_ifc_hca_cap_union_bits capability; 5761 }; 5762 5763 struct mlx5_ifc_query_hca_cap_in_bits { 5764 u8 opcode[0x10]; 5765 u8 reserved_at_10[0x10]; 5766 5767 u8 reserved_at_20[0x10]; 5768 u8 op_mod[0x10]; 5769 5770 u8 other_function[0x1]; 5771 u8 reserved_at_41[0xf]; 5772 u8 function_id[0x10]; 5773 5774 u8 reserved_at_60[0x20]; 5775 }; 5776 5777 struct mlx5_ifc_other_hca_cap_bits { 5778 u8 roce[0x1]; 5779 u8 reserved_at_1[0x27f]; 5780 }; 5781 5782 struct mlx5_ifc_query_other_hca_cap_out_bits { 5783 u8 status[0x8]; 5784 u8 reserved_at_8[0x18]; 5785 5786 u8 syndrome[0x20]; 5787 5788 u8 reserved_at_40[0x40]; 5789 5790 struct mlx5_ifc_other_hca_cap_bits other_capability; 5791 }; 5792 5793 struct mlx5_ifc_query_other_hca_cap_in_bits { 5794 u8 opcode[0x10]; 5795 u8 reserved_at_10[0x10]; 5796 5797 u8 reserved_at_20[0x10]; 5798 u8 op_mod[0x10]; 5799 5800 u8 reserved_at_40[0x10]; 5801 u8 function_id[0x10]; 5802 5803 u8 reserved_at_60[0x20]; 5804 }; 5805 5806 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5807 u8 status[0x8]; 5808 u8 reserved_at_8[0x18]; 5809 5810 u8 syndrome[0x20]; 5811 5812 u8 reserved_at_40[0x40]; 5813 }; 5814 5815 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5816 u8 opcode[0x10]; 5817 u8 reserved_at_10[0x10]; 5818 5819 u8 reserved_at_20[0x10]; 5820 u8 op_mod[0x10]; 5821 5822 u8 reserved_at_40[0x10]; 5823 u8 function_id[0x10]; 5824 u8 field_select[0x20]; 5825 5826 struct mlx5_ifc_other_hca_cap_bits other_capability; 5827 }; 5828 5829 struct mlx5_ifc_flow_table_context_bits { 5830 u8 reformat_en[0x1]; 5831 u8 decap_en[0x1]; 5832 u8 sw_owner[0x1]; 5833 u8 termination_table[0x1]; 5834 u8 table_miss_action[0x4]; 5835 u8 level[0x8]; 5836 u8 reserved_at_10[0x8]; 5837 u8 log_size[0x8]; 5838 5839 u8 reserved_at_20[0x8]; 5840 u8 table_miss_id[0x18]; 5841 5842 u8 reserved_at_40[0x8]; 5843 u8 lag_master_next_table_id[0x18]; 5844 5845 u8 reserved_at_60[0x60]; 5846 5847 u8 sw_owner_icm_root_1[0x40]; 5848 5849 u8 sw_owner_icm_root_0[0x40]; 5850 5851 }; 5852 5853 struct mlx5_ifc_query_flow_table_out_bits { 5854 u8 status[0x8]; 5855 u8 reserved_at_8[0x18]; 5856 5857 u8 syndrome[0x20]; 5858 5859 u8 reserved_at_40[0x80]; 5860 5861 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5862 }; 5863 5864 struct mlx5_ifc_query_flow_table_in_bits { 5865 u8 opcode[0x10]; 5866 u8 reserved_at_10[0x10]; 5867 5868 u8 reserved_at_20[0x10]; 5869 u8 op_mod[0x10]; 5870 5871 u8 reserved_at_40[0x40]; 5872 5873 u8 table_type[0x8]; 5874 u8 reserved_at_88[0x18]; 5875 5876 u8 reserved_at_a0[0x8]; 5877 u8 table_id[0x18]; 5878 5879 u8 reserved_at_c0[0x140]; 5880 }; 5881 5882 struct mlx5_ifc_query_fte_out_bits { 5883 u8 status[0x8]; 5884 u8 reserved_at_8[0x18]; 5885 5886 u8 syndrome[0x20]; 5887 5888 u8 reserved_at_40[0x1c0]; 5889 5890 struct mlx5_ifc_flow_context_bits flow_context; 5891 }; 5892 5893 struct mlx5_ifc_query_fte_in_bits { 5894 u8 opcode[0x10]; 5895 u8 reserved_at_10[0x10]; 5896 5897 u8 reserved_at_20[0x10]; 5898 u8 op_mod[0x10]; 5899 5900 u8 reserved_at_40[0x40]; 5901 5902 u8 table_type[0x8]; 5903 u8 reserved_at_88[0x18]; 5904 5905 u8 reserved_at_a0[0x8]; 5906 u8 table_id[0x18]; 5907 5908 u8 reserved_at_c0[0x40]; 5909 5910 u8 flow_index[0x20]; 5911 5912 u8 reserved_at_120[0xe0]; 5913 }; 5914 5915 struct mlx5_ifc_match_definer_format_0_bits { 5916 u8 reserved_at_0[0x100]; 5917 5918 u8 metadata_reg_c_0[0x20]; 5919 5920 u8 metadata_reg_c_1[0x20]; 5921 5922 u8 outer_dmac_47_16[0x20]; 5923 5924 u8 outer_dmac_15_0[0x10]; 5925 u8 outer_ethertype[0x10]; 5926 5927 u8 reserved_at_180[0x1]; 5928 u8 sx_sniffer[0x1]; 5929 u8 functional_lb[0x1]; 5930 u8 outer_ip_frag[0x1]; 5931 u8 outer_qp_type[0x2]; 5932 u8 outer_encap_type[0x2]; 5933 u8 port_number[0x2]; 5934 u8 outer_l3_type[0x2]; 5935 u8 outer_l4_type[0x2]; 5936 u8 outer_first_vlan_type[0x2]; 5937 u8 outer_first_vlan_prio[0x3]; 5938 u8 outer_first_vlan_cfi[0x1]; 5939 u8 outer_first_vlan_vid[0xc]; 5940 5941 u8 outer_l4_type_ext[0x4]; 5942 u8 reserved_at_1a4[0x2]; 5943 u8 outer_ipsec_layer[0x2]; 5944 u8 outer_l2_type[0x2]; 5945 u8 force_lb[0x1]; 5946 u8 outer_l2_ok[0x1]; 5947 u8 outer_l3_ok[0x1]; 5948 u8 outer_l4_ok[0x1]; 5949 u8 outer_second_vlan_type[0x2]; 5950 u8 outer_second_vlan_prio[0x3]; 5951 u8 outer_second_vlan_cfi[0x1]; 5952 u8 outer_second_vlan_vid[0xc]; 5953 5954 u8 outer_smac_47_16[0x20]; 5955 5956 u8 outer_smac_15_0[0x10]; 5957 u8 inner_ipv4_checksum_ok[0x1]; 5958 u8 inner_l4_checksum_ok[0x1]; 5959 u8 outer_ipv4_checksum_ok[0x1]; 5960 u8 outer_l4_checksum_ok[0x1]; 5961 u8 inner_l3_ok[0x1]; 5962 u8 inner_l4_ok[0x1]; 5963 u8 outer_l3_ok_duplicate[0x1]; 5964 u8 outer_l4_ok_duplicate[0x1]; 5965 u8 outer_tcp_cwr[0x1]; 5966 u8 outer_tcp_ece[0x1]; 5967 u8 outer_tcp_urg[0x1]; 5968 u8 outer_tcp_ack[0x1]; 5969 u8 outer_tcp_psh[0x1]; 5970 u8 outer_tcp_rst[0x1]; 5971 u8 outer_tcp_syn[0x1]; 5972 u8 outer_tcp_fin[0x1]; 5973 }; 5974 5975 struct mlx5_ifc_match_definer_format_22_bits { 5976 u8 reserved_at_0[0x100]; 5977 5978 u8 outer_ip_src_addr[0x20]; 5979 5980 u8 outer_ip_dest_addr[0x20]; 5981 5982 u8 outer_l4_sport[0x10]; 5983 u8 outer_l4_dport[0x10]; 5984 5985 u8 reserved_at_160[0x1]; 5986 u8 sx_sniffer[0x1]; 5987 u8 functional_lb[0x1]; 5988 u8 outer_ip_frag[0x1]; 5989 u8 outer_qp_type[0x2]; 5990 u8 outer_encap_type[0x2]; 5991 u8 port_number[0x2]; 5992 u8 outer_l3_type[0x2]; 5993 u8 outer_l4_type[0x2]; 5994 u8 outer_first_vlan_type[0x2]; 5995 u8 outer_first_vlan_prio[0x3]; 5996 u8 outer_first_vlan_cfi[0x1]; 5997 u8 outer_first_vlan_vid[0xc]; 5998 5999 u8 metadata_reg_c_0[0x20]; 6000 6001 u8 outer_dmac_47_16[0x20]; 6002 6003 u8 outer_smac_47_16[0x20]; 6004 6005 u8 outer_smac_15_0[0x10]; 6006 u8 outer_dmac_15_0[0x10]; 6007 }; 6008 6009 struct mlx5_ifc_match_definer_format_23_bits { 6010 u8 reserved_at_0[0x100]; 6011 6012 u8 inner_ip_src_addr[0x20]; 6013 6014 u8 inner_ip_dest_addr[0x20]; 6015 6016 u8 inner_l4_sport[0x10]; 6017 u8 inner_l4_dport[0x10]; 6018 6019 u8 reserved_at_160[0x1]; 6020 u8 sx_sniffer[0x1]; 6021 u8 functional_lb[0x1]; 6022 u8 inner_ip_frag[0x1]; 6023 u8 inner_qp_type[0x2]; 6024 u8 inner_encap_type[0x2]; 6025 u8 port_number[0x2]; 6026 u8 inner_l3_type[0x2]; 6027 u8 inner_l4_type[0x2]; 6028 u8 inner_first_vlan_type[0x2]; 6029 u8 inner_first_vlan_prio[0x3]; 6030 u8 inner_first_vlan_cfi[0x1]; 6031 u8 inner_first_vlan_vid[0xc]; 6032 6033 u8 tunnel_header_0[0x20]; 6034 6035 u8 inner_dmac_47_16[0x20]; 6036 6037 u8 inner_smac_47_16[0x20]; 6038 6039 u8 inner_smac_15_0[0x10]; 6040 u8 inner_dmac_15_0[0x10]; 6041 }; 6042 6043 struct mlx5_ifc_match_definer_format_29_bits { 6044 u8 reserved_at_0[0xc0]; 6045 6046 u8 outer_ip_dest_addr[0x80]; 6047 6048 u8 outer_ip_src_addr[0x80]; 6049 6050 u8 outer_l4_sport[0x10]; 6051 u8 outer_l4_dport[0x10]; 6052 6053 u8 reserved_at_1e0[0x20]; 6054 }; 6055 6056 struct mlx5_ifc_match_definer_format_30_bits { 6057 u8 reserved_at_0[0xa0]; 6058 6059 u8 outer_ip_dest_addr[0x80]; 6060 6061 u8 outer_ip_src_addr[0x80]; 6062 6063 u8 outer_dmac_47_16[0x20]; 6064 6065 u8 outer_smac_47_16[0x20]; 6066 6067 u8 outer_smac_15_0[0x10]; 6068 u8 outer_dmac_15_0[0x10]; 6069 }; 6070 6071 struct mlx5_ifc_match_definer_format_31_bits { 6072 u8 reserved_at_0[0xc0]; 6073 6074 u8 inner_ip_dest_addr[0x80]; 6075 6076 u8 inner_ip_src_addr[0x80]; 6077 6078 u8 inner_l4_sport[0x10]; 6079 u8 inner_l4_dport[0x10]; 6080 6081 u8 reserved_at_1e0[0x20]; 6082 }; 6083 6084 struct mlx5_ifc_match_definer_format_32_bits { 6085 u8 reserved_at_0[0xa0]; 6086 6087 u8 inner_ip_dest_addr[0x80]; 6088 6089 u8 inner_ip_src_addr[0x80]; 6090 6091 u8 inner_dmac_47_16[0x20]; 6092 6093 u8 inner_smac_47_16[0x20]; 6094 6095 u8 inner_smac_15_0[0x10]; 6096 u8 inner_dmac_15_0[0x10]; 6097 }; 6098 6099 struct mlx5_ifc_match_definer_bits { 6100 u8 modify_field_select[0x40]; 6101 6102 u8 reserved_at_40[0x40]; 6103 6104 u8 reserved_at_80[0x10]; 6105 u8 format_id[0x10]; 6106 6107 u8 reserved_at_a0[0x160]; 6108 6109 u8 match_mask[16][0x20]; 6110 }; 6111 6112 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6113 u8 opcode[0x10]; 6114 u8 uid[0x10]; 6115 6116 u8 vhca_tunnel_id[0x10]; 6117 u8 obj_type[0x10]; 6118 6119 u8 obj_id[0x20]; 6120 6121 u8 reserved_at_60[0x3]; 6122 u8 log_obj_range[0x5]; 6123 u8 reserved_at_68[0x18]; 6124 }; 6125 6126 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6127 u8 status[0x8]; 6128 u8 reserved_at_8[0x18]; 6129 6130 u8 syndrome[0x20]; 6131 6132 u8 obj_id[0x20]; 6133 6134 u8 reserved_at_60[0x20]; 6135 }; 6136 6137 struct mlx5_ifc_create_match_definer_in_bits { 6138 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6139 6140 struct mlx5_ifc_match_definer_bits obj_context; 6141 }; 6142 6143 struct mlx5_ifc_create_match_definer_out_bits { 6144 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6145 }; 6146 6147 enum { 6148 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6149 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6150 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6151 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6152 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6153 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6154 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6155 }; 6156 6157 struct mlx5_ifc_query_flow_group_out_bits { 6158 u8 status[0x8]; 6159 u8 reserved_at_8[0x18]; 6160 6161 u8 syndrome[0x20]; 6162 6163 u8 reserved_at_40[0xa0]; 6164 6165 u8 start_flow_index[0x20]; 6166 6167 u8 reserved_at_100[0x20]; 6168 6169 u8 end_flow_index[0x20]; 6170 6171 u8 reserved_at_140[0xa0]; 6172 6173 u8 reserved_at_1e0[0x18]; 6174 u8 match_criteria_enable[0x8]; 6175 6176 struct mlx5_ifc_fte_match_param_bits match_criteria; 6177 6178 u8 reserved_at_1200[0xe00]; 6179 }; 6180 6181 struct mlx5_ifc_query_flow_group_in_bits { 6182 u8 opcode[0x10]; 6183 u8 reserved_at_10[0x10]; 6184 6185 u8 reserved_at_20[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 reserved_at_40[0x40]; 6189 6190 u8 table_type[0x8]; 6191 u8 reserved_at_88[0x18]; 6192 6193 u8 reserved_at_a0[0x8]; 6194 u8 table_id[0x18]; 6195 6196 u8 group_id[0x20]; 6197 6198 u8 reserved_at_e0[0x120]; 6199 }; 6200 6201 struct mlx5_ifc_query_flow_counter_out_bits { 6202 u8 status[0x8]; 6203 u8 reserved_at_8[0x18]; 6204 6205 u8 syndrome[0x20]; 6206 6207 u8 reserved_at_40[0x40]; 6208 6209 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6210 }; 6211 6212 struct mlx5_ifc_query_flow_counter_in_bits { 6213 u8 opcode[0x10]; 6214 u8 reserved_at_10[0x10]; 6215 6216 u8 reserved_at_20[0x10]; 6217 u8 op_mod[0x10]; 6218 6219 u8 reserved_at_40[0x80]; 6220 6221 u8 clear[0x1]; 6222 u8 reserved_at_c1[0xf]; 6223 u8 num_of_counters[0x10]; 6224 6225 u8 flow_counter_id[0x20]; 6226 }; 6227 6228 struct mlx5_ifc_query_esw_vport_context_out_bits { 6229 u8 status[0x8]; 6230 u8 reserved_at_8[0x18]; 6231 6232 u8 syndrome[0x20]; 6233 6234 u8 reserved_at_40[0x40]; 6235 6236 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6237 }; 6238 6239 struct mlx5_ifc_query_esw_vport_context_in_bits { 6240 u8 opcode[0x10]; 6241 u8 reserved_at_10[0x10]; 6242 6243 u8 reserved_at_20[0x10]; 6244 u8 op_mod[0x10]; 6245 6246 u8 other_vport[0x1]; 6247 u8 reserved_at_41[0xf]; 6248 u8 vport_number[0x10]; 6249 6250 u8 reserved_at_60[0x20]; 6251 }; 6252 6253 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6254 u8 status[0x8]; 6255 u8 reserved_at_8[0x18]; 6256 6257 u8 syndrome[0x20]; 6258 6259 u8 reserved_at_40[0x40]; 6260 }; 6261 6262 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6263 u8 reserved_at_0[0x1b]; 6264 u8 fdb_to_vport_reg_c_id[0x1]; 6265 u8 vport_cvlan_insert[0x1]; 6266 u8 vport_svlan_insert[0x1]; 6267 u8 vport_cvlan_strip[0x1]; 6268 u8 vport_svlan_strip[0x1]; 6269 }; 6270 6271 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6272 u8 opcode[0x10]; 6273 u8 reserved_at_10[0x10]; 6274 6275 u8 reserved_at_20[0x10]; 6276 u8 op_mod[0x10]; 6277 6278 u8 other_vport[0x1]; 6279 u8 reserved_at_41[0xf]; 6280 u8 vport_number[0x10]; 6281 6282 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6283 6284 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6285 }; 6286 6287 struct mlx5_ifc_query_eq_out_bits { 6288 u8 status[0x8]; 6289 u8 reserved_at_8[0x18]; 6290 6291 u8 syndrome[0x20]; 6292 6293 u8 reserved_at_40[0x40]; 6294 6295 struct mlx5_ifc_eqc_bits eq_context_entry; 6296 6297 u8 reserved_at_280[0x40]; 6298 6299 u8 event_bitmask[0x40]; 6300 6301 u8 reserved_at_300[0x580]; 6302 6303 u8 pas[][0x40]; 6304 }; 6305 6306 struct mlx5_ifc_query_eq_in_bits { 6307 u8 opcode[0x10]; 6308 u8 reserved_at_10[0x10]; 6309 6310 u8 reserved_at_20[0x10]; 6311 u8 op_mod[0x10]; 6312 6313 u8 reserved_at_40[0x18]; 6314 u8 eq_number[0x8]; 6315 6316 u8 reserved_at_60[0x20]; 6317 }; 6318 6319 struct mlx5_ifc_packet_reformat_context_in_bits { 6320 u8 reformat_type[0x8]; 6321 u8 reserved_at_8[0x4]; 6322 u8 reformat_param_0[0x4]; 6323 u8 reserved_at_10[0x6]; 6324 u8 reformat_data_size[0xa]; 6325 6326 u8 reformat_param_1[0x8]; 6327 u8 reserved_at_28[0x8]; 6328 u8 reformat_data[2][0x8]; 6329 6330 u8 more_reformat_data[][0x8]; 6331 }; 6332 6333 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6334 u8 status[0x8]; 6335 u8 reserved_at_8[0x18]; 6336 6337 u8 syndrome[0x20]; 6338 6339 u8 reserved_at_40[0xa0]; 6340 6341 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6342 }; 6343 6344 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6345 u8 opcode[0x10]; 6346 u8 reserved_at_10[0x10]; 6347 6348 u8 reserved_at_20[0x10]; 6349 u8 op_mod[0x10]; 6350 6351 u8 packet_reformat_id[0x20]; 6352 6353 u8 reserved_at_60[0xa0]; 6354 }; 6355 6356 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6357 u8 status[0x8]; 6358 u8 reserved_at_8[0x18]; 6359 6360 u8 syndrome[0x20]; 6361 6362 u8 packet_reformat_id[0x20]; 6363 6364 u8 reserved_at_60[0x20]; 6365 }; 6366 6367 enum { 6368 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6369 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6370 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6371 }; 6372 6373 enum mlx5_reformat_ctx_type { 6374 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6375 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6376 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6377 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6378 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6379 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6380 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6381 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6382 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6383 }; 6384 6385 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6386 u8 opcode[0x10]; 6387 u8 reserved_at_10[0x10]; 6388 6389 u8 reserved_at_20[0x10]; 6390 u8 op_mod[0x10]; 6391 6392 u8 reserved_at_40[0xa0]; 6393 6394 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6395 }; 6396 6397 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6398 u8 status[0x8]; 6399 u8 reserved_at_8[0x18]; 6400 6401 u8 syndrome[0x20]; 6402 6403 u8 reserved_at_40[0x40]; 6404 }; 6405 6406 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6407 u8 opcode[0x10]; 6408 u8 reserved_at_10[0x10]; 6409 6410 u8 reserved_20[0x10]; 6411 u8 op_mod[0x10]; 6412 6413 u8 packet_reformat_id[0x20]; 6414 6415 u8 reserved_60[0x20]; 6416 }; 6417 6418 struct mlx5_ifc_set_action_in_bits { 6419 u8 action_type[0x4]; 6420 u8 field[0xc]; 6421 u8 reserved_at_10[0x3]; 6422 u8 offset[0x5]; 6423 u8 reserved_at_18[0x3]; 6424 u8 length[0x5]; 6425 6426 u8 data[0x20]; 6427 }; 6428 6429 struct mlx5_ifc_add_action_in_bits { 6430 u8 action_type[0x4]; 6431 u8 field[0xc]; 6432 u8 reserved_at_10[0x10]; 6433 6434 u8 data[0x20]; 6435 }; 6436 6437 struct mlx5_ifc_copy_action_in_bits { 6438 u8 action_type[0x4]; 6439 u8 src_field[0xc]; 6440 u8 reserved_at_10[0x3]; 6441 u8 src_offset[0x5]; 6442 u8 reserved_at_18[0x3]; 6443 u8 length[0x5]; 6444 6445 u8 reserved_at_20[0x4]; 6446 u8 dst_field[0xc]; 6447 u8 reserved_at_30[0x3]; 6448 u8 dst_offset[0x5]; 6449 u8 reserved_at_38[0x8]; 6450 }; 6451 6452 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6453 struct mlx5_ifc_set_action_in_bits set_action_in; 6454 struct mlx5_ifc_add_action_in_bits add_action_in; 6455 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6456 u8 reserved_at_0[0x40]; 6457 }; 6458 6459 enum { 6460 MLX5_ACTION_TYPE_SET = 0x1, 6461 MLX5_ACTION_TYPE_ADD = 0x2, 6462 MLX5_ACTION_TYPE_COPY = 0x3, 6463 }; 6464 6465 enum { 6466 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6467 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6468 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6469 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6470 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6471 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6472 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6473 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6474 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6475 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6476 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6477 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6478 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6479 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6480 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6481 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6482 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6483 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6484 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6485 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6486 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6487 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6488 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6489 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6490 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6491 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6492 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6493 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6494 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6495 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6496 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6497 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6498 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6499 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6500 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6501 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6502 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6503 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6504 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6505 }; 6506 6507 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6508 u8 status[0x8]; 6509 u8 reserved_at_8[0x18]; 6510 6511 u8 syndrome[0x20]; 6512 6513 u8 modify_header_id[0x20]; 6514 6515 u8 reserved_at_60[0x20]; 6516 }; 6517 6518 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6519 u8 opcode[0x10]; 6520 u8 reserved_at_10[0x10]; 6521 6522 u8 reserved_at_20[0x10]; 6523 u8 op_mod[0x10]; 6524 6525 u8 reserved_at_40[0x20]; 6526 6527 u8 table_type[0x8]; 6528 u8 reserved_at_68[0x10]; 6529 u8 num_of_actions[0x8]; 6530 6531 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6532 }; 6533 6534 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6535 u8 status[0x8]; 6536 u8 reserved_at_8[0x18]; 6537 6538 u8 syndrome[0x20]; 6539 6540 u8 reserved_at_40[0x40]; 6541 }; 6542 6543 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6544 u8 opcode[0x10]; 6545 u8 reserved_at_10[0x10]; 6546 6547 u8 reserved_at_20[0x10]; 6548 u8 op_mod[0x10]; 6549 6550 u8 modify_header_id[0x20]; 6551 6552 u8 reserved_at_60[0x20]; 6553 }; 6554 6555 struct mlx5_ifc_query_modify_header_context_in_bits { 6556 u8 opcode[0x10]; 6557 u8 uid[0x10]; 6558 6559 u8 reserved_at_20[0x10]; 6560 u8 op_mod[0x10]; 6561 6562 u8 modify_header_id[0x20]; 6563 6564 u8 reserved_at_60[0xa0]; 6565 }; 6566 6567 struct mlx5_ifc_query_dct_out_bits { 6568 u8 status[0x8]; 6569 u8 reserved_at_8[0x18]; 6570 6571 u8 syndrome[0x20]; 6572 6573 u8 reserved_at_40[0x40]; 6574 6575 struct mlx5_ifc_dctc_bits dct_context_entry; 6576 6577 u8 reserved_at_280[0x180]; 6578 }; 6579 6580 struct mlx5_ifc_query_dct_in_bits { 6581 u8 opcode[0x10]; 6582 u8 reserved_at_10[0x10]; 6583 6584 u8 reserved_at_20[0x10]; 6585 u8 op_mod[0x10]; 6586 6587 u8 reserved_at_40[0x8]; 6588 u8 dctn[0x18]; 6589 6590 u8 reserved_at_60[0x20]; 6591 }; 6592 6593 struct mlx5_ifc_query_cq_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_at_8[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_at_40[0x40]; 6600 6601 struct mlx5_ifc_cqc_bits cq_context; 6602 6603 u8 reserved_at_280[0x600]; 6604 6605 u8 pas[][0x40]; 6606 }; 6607 6608 struct mlx5_ifc_query_cq_in_bits { 6609 u8 opcode[0x10]; 6610 u8 reserved_at_10[0x10]; 6611 6612 u8 reserved_at_20[0x10]; 6613 u8 op_mod[0x10]; 6614 6615 u8 reserved_at_40[0x8]; 6616 u8 cqn[0x18]; 6617 6618 u8 reserved_at_60[0x20]; 6619 }; 6620 6621 struct mlx5_ifc_query_cong_status_out_bits { 6622 u8 status[0x8]; 6623 u8 reserved_at_8[0x18]; 6624 6625 u8 syndrome[0x20]; 6626 6627 u8 reserved_at_40[0x20]; 6628 6629 u8 enable[0x1]; 6630 u8 tag_enable[0x1]; 6631 u8 reserved_at_62[0x1e]; 6632 }; 6633 6634 struct mlx5_ifc_query_cong_status_in_bits { 6635 u8 opcode[0x10]; 6636 u8 reserved_at_10[0x10]; 6637 6638 u8 reserved_at_20[0x10]; 6639 u8 op_mod[0x10]; 6640 6641 u8 reserved_at_40[0x18]; 6642 u8 priority[0x4]; 6643 u8 cong_protocol[0x4]; 6644 6645 u8 reserved_at_60[0x20]; 6646 }; 6647 6648 struct mlx5_ifc_query_cong_statistics_out_bits { 6649 u8 status[0x8]; 6650 u8 reserved_at_8[0x18]; 6651 6652 u8 syndrome[0x20]; 6653 6654 u8 reserved_at_40[0x40]; 6655 6656 u8 rp_cur_flows[0x20]; 6657 6658 u8 sum_flows[0x20]; 6659 6660 u8 rp_cnp_ignored_high[0x20]; 6661 6662 u8 rp_cnp_ignored_low[0x20]; 6663 6664 u8 rp_cnp_handled_high[0x20]; 6665 6666 u8 rp_cnp_handled_low[0x20]; 6667 6668 u8 reserved_at_140[0x100]; 6669 6670 u8 time_stamp_high[0x20]; 6671 6672 u8 time_stamp_low[0x20]; 6673 6674 u8 accumulators_period[0x20]; 6675 6676 u8 np_ecn_marked_roce_packets_high[0x20]; 6677 6678 u8 np_ecn_marked_roce_packets_low[0x20]; 6679 6680 u8 np_cnp_sent_high[0x20]; 6681 6682 u8 np_cnp_sent_low[0x20]; 6683 6684 u8 reserved_at_320[0x560]; 6685 }; 6686 6687 struct mlx5_ifc_query_cong_statistics_in_bits { 6688 u8 opcode[0x10]; 6689 u8 reserved_at_10[0x10]; 6690 6691 u8 reserved_at_20[0x10]; 6692 u8 op_mod[0x10]; 6693 6694 u8 clear[0x1]; 6695 u8 reserved_at_41[0x1f]; 6696 6697 u8 reserved_at_60[0x20]; 6698 }; 6699 6700 struct mlx5_ifc_query_cong_params_out_bits { 6701 u8 status[0x8]; 6702 u8 reserved_at_8[0x18]; 6703 6704 u8 syndrome[0x20]; 6705 6706 u8 reserved_at_40[0x40]; 6707 6708 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6709 }; 6710 6711 struct mlx5_ifc_query_cong_params_in_bits { 6712 u8 opcode[0x10]; 6713 u8 reserved_at_10[0x10]; 6714 6715 u8 reserved_at_20[0x10]; 6716 u8 op_mod[0x10]; 6717 6718 u8 reserved_at_40[0x1c]; 6719 u8 cong_protocol[0x4]; 6720 6721 u8 reserved_at_60[0x20]; 6722 }; 6723 6724 struct mlx5_ifc_query_adapter_out_bits { 6725 u8 status[0x8]; 6726 u8 reserved_at_8[0x18]; 6727 6728 u8 syndrome[0x20]; 6729 6730 u8 reserved_at_40[0x40]; 6731 6732 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6733 }; 6734 6735 struct mlx5_ifc_query_adapter_in_bits { 6736 u8 opcode[0x10]; 6737 u8 reserved_at_10[0x10]; 6738 6739 u8 reserved_at_20[0x10]; 6740 u8 op_mod[0x10]; 6741 6742 u8 reserved_at_40[0x40]; 6743 }; 6744 6745 struct mlx5_ifc_qp_2rst_out_bits { 6746 u8 status[0x8]; 6747 u8 reserved_at_8[0x18]; 6748 6749 u8 syndrome[0x20]; 6750 6751 u8 reserved_at_40[0x40]; 6752 }; 6753 6754 struct mlx5_ifc_qp_2rst_in_bits { 6755 u8 opcode[0x10]; 6756 u8 uid[0x10]; 6757 6758 u8 reserved_at_20[0x10]; 6759 u8 op_mod[0x10]; 6760 6761 u8 reserved_at_40[0x8]; 6762 u8 qpn[0x18]; 6763 6764 u8 reserved_at_60[0x20]; 6765 }; 6766 6767 struct mlx5_ifc_qp_2err_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_at_8[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 reserved_at_40[0x40]; 6774 }; 6775 6776 struct mlx5_ifc_qp_2err_in_bits { 6777 u8 opcode[0x10]; 6778 u8 uid[0x10]; 6779 6780 u8 reserved_at_20[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 reserved_at_40[0x8]; 6784 u8 qpn[0x18]; 6785 6786 u8 reserved_at_60[0x20]; 6787 }; 6788 6789 struct mlx5_ifc_page_fault_resume_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_at_8[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 reserved_at_40[0x40]; 6796 }; 6797 6798 struct mlx5_ifc_page_fault_resume_in_bits { 6799 u8 opcode[0x10]; 6800 u8 reserved_at_10[0x10]; 6801 6802 u8 reserved_at_20[0x10]; 6803 u8 op_mod[0x10]; 6804 6805 u8 error[0x1]; 6806 u8 reserved_at_41[0x4]; 6807 u8 page_fault_type[0x3]; 6808 u8 wq_number[0x18]; 6809 6810 u8 reserved_at_60[0x8]; 6811 u8 token[0x18]; 6812 }; 6813 6814 struct mlx5_ifc_nop_out_bits { 6815 u8 status[0x8]; 6816 u8 reserved_at_8[0x18]; 6817 6818 u8 syndrome[0x20]; 6819 6820 u8 reserved_at_40[0x40]; 6821 }; 6822 6823 struct mlx5_ifc_nop_in_bits { 6824 u8 opcode[0x10]; 6825 u8 reserved_at_10[0x10]; 6826 6827 u8 reserved_at_20[0x10]; 6828 u8 op_mod[0x10]; 6829 6830 u8 reserved_at_40[0x40]; 6831 }; 6832 6833 struct mlx5_ifc_modify_vport_state_out_bits { 6834 u8 status[0x8]; 6835 u8 reserved_at_8[0x18]; 6836 6837 u8 syndrome[0x20]; 6838 6839 u8 reserved_at_40[0x40]; 6840 }; 6841 6842 struct mlx5_ifc_modify_vport_state_in_bits { 6843 u8 opcode[0x10]; 6844 u8 reserved_at_10[0x10]; 6845 6846 u8 reserved_at_20[0x10]; 6847 u8 op_mod[0x10]; 6848 6849 u8 other_vport[0x1]; 6850 u8 reserved_at_41[0xf]; 6851 u8 vport_number[0x10]; 6852 6853 u8 reserved_at_60[0x18]; 6854 u8 admin_state[0x4]; 6855 u8 reserved_at_7c[0x4]; 6856 }; 6857 6858 struct mlx5_ifc_modify_tis_out_bits { 6859 u8 status[0x8]; 6860 u8 reserved_at_8[0x18]; 6861 6862 u8 syndrome[0x20]; 6863 6864 u8 reserved_at_40[0x40]; 6865 }; 6866 6867 struct mlx5_ifc_modify_tis_bitmask_bits { 6868 u8 reserved_at_0[0x20]; 6869 6870 u8 reserved_at_20[0x1d]; 6871 u8 lag_tx_port_affinity[0x1]; 6872 u8 strict_lag_tx_port_affinity[0x1]; 6873 u8 prio[0x1]; 6874 }; 6875 6876 struct mlx5_ifc_modify_tis_in_bits { 6877 u8 opcode[0x10]; 6878 u8 uid[0x10]; 6879 6880 u8 reserved_at_20[0x10]; 6881 u8 op_mod[0x10]; 6882 6883 u8 reserved_at_40[0x8]; 6884 u8 tisn[0x18]; 6885 6886 u8 reserved_at_60[0x20]; 6887 6888 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6889 6890 u8 reserved_at_c0[0x40]; 6891 6892 struct mlx5_ifc_tisc_bits ctx; 6893 }; 6894 6895 struct mlx5_ifc_modify_tir_bitmask_bits { 6896 u8 reserved_at_0[0x20]; 6897 6898 u8 reserved_at_20[0x1b]; 6899 u8 self_lb_en[0x1]; 6900 u8 reserved_at_3c[0x1]; 6901 u8 hash[0x1]; 6902 u8 reserved_at_3e[0x1]; 6903 u8 packet_merge[0x1]; 6904 }; 6905 6906 struct mlx5_ifc_modify_tir_out_bits { 6907 u8 status[0x8]; 6908 u8 reserved_at_8[0x18]; 6909 6910 u8 syndrome[0x20]; 6911 6912 u8 reserved_at_40[0x40]; 6913 }; 6914 6915 struct mlx5_ifc_modify_tir_in_bits { 6916 u8 opcode[0x10]; 6917 u8 uid[0x10]; 6918 6919 u8 reserved_at_20[0x10]; 6920 u8 op_mod[0x10]; 6921 6922 u8 reserved_at_40[0x8]; 6923 u8 tirn[0x18]; 6924 6925 u8 reserved_at_60[0x20]; 6926 6927 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6928 6929 u8 reserved_at_c0[0x40]; 6930 6931 struct mlx5_ifc_tirc_bits ctx; 6932 }; 6933 6934 struct mlx5_ifc_modify_sq_out_bits { 6935 u8 status[0x8]; 6936 u8 reserved_at_8[0x18]; 6937 6938 u8 syndrome[0x20]; 6939 6940 u8 reserved_at_40[0x40]; 6941 }; 6942 6943 struct mlx5_ifc_modify_sq_in_bits { 6944 u8 opcode[0x10]; 6945 u8 uid[0x10]; 6946 6947 u8 reserved_at_20[0x10]; 6948 u8 op_mod[0x10]; 6949 6950 u8 sq_state[0x4]; 6951 u8 reserved_at_44[0x4]; 6952 u8 sqn[0x18]; 6953 6954 u8 reserved_at_60[0x20]; 6955 6956 u8 modify_bitmask[0x40]; 6957 6958 u8 reserved_at_c0[0x40]; 6959 6960 struct mlx5_ifc_sqc_bits ctx; 6961 }; 6962 6963 struct mlx5_ifc_modify_scheduling_element_out_bits { 6964 u8 status[0x8]; 6965 u8 reserved_at_8[0x18]; 6966 6967 u8 syndrome[0x20]; 6968 6969 u8 reserved_at_40[0x1c0]; 6970 }; 6971 6972 enum { 6973 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6974 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6975 }; 6976 6977 struct mlx5_ifc_modify_scheduling_element_in_bits { 6978 u8 opcode[0x10]; 6979 u8 reserved_at_10[0x10]; 6980 6981 u8 reserved_at_20[0x10]; 6982 u8 op_mod[0x10]; 6983 6984 u8 scheduling_hierarchy[0x8]; 6985 u8 reserved_at_48[0x18]; 6986 6987 u8 scheduling_element_id[0x20]; 6988 6989 u8 reserved_at_80[0x20]; 6990 6991 u8 modify_bitmask[0x20]; 6992 6993 u8 reserved_at_c0[0x40]; 6994 6995 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6996 6997 u8 reserved_at_300[0x100]; 6998 }; 6999 7000 struct mlx5_ifc_modify_rqt_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_at_8[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_at_40[0x40]; 7007 }; 7008 7009 struct mlx5_ifc_rqt_bitmask_bits { 7010 u8 reserved_at_0[0x20]; 7011 7012 u8 reserved_at_20[0x1f]; 7013 u8 rqn_list[0x1]; 7014 }; 7015 7016 struct mlx5_ifc_modify_rqt_in_bits { 7017 u8 opcode[0x10]; 7018 u8 uid[0x10]; 7019 7020 u8 reserved_at_20[0x10]; 7021 u8 op_mod[0x10]; 7022 7023 u8 reserved_at_40[0x8]; 7024 u8 rqtn[0x18]; 7025 7026 u8 reserved_at_60[0x20]; 7027 7028 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7029 7030 u8 reserved_at_c0[0x40]; 7031 7032 struct mlx5_ifc_rqtc_bits ctx; 7033 }; 7034 7035 struct mlx5_ifc_modify_rq_out_bits { 7036 u8 status[0x8]; 7037 u8 reserved_at_8[0x18]; 7038 7039 u8 syndrome[0x20]; 7040 7041 u8 reserved_at_40[0x40]; 7042 }; 7043 7044 enum { 7045 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7046 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7047 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7048 }; 7049 7050 struct mlx5_ifc_modify_rq_in_bits { 7051 u8 opcode[0x10]; 7052 u8 uid[0x10]; 7053 7054 u8 reserved_at_20[0x10]; 7055 u8 op_mod[0x10]; 7056 7057 u8 rq_state[0x4]; 7058 u8 reserved_at_44[0x4]; 7059 u8 rqn[0x18]; 7060 7061 u8 reserved_at_60[0x20]; 7062 7063 u8 modify_bitmask[0x40]; 7064 7065 u8 reserved_at_c0[0x40]; 7066 7067 struct mlx5_ifc_rqc_bits ctx; 7068 }; 7069 7070 struct mlx5_ifc_modify_rmp_out_bits { 7071 u8 status[0x8]; 7072 u8 reserved_at_8[0x18]; 7073 7074 u8 syndrome[0x20]; 7075 7076 u8 reserved_at_40[0x40]; 7077 }; 7078 7079 struct mlx5_ifc_rmp_bitmask_bits { 7080 u8 reserved_at_0[0x20]; 7081 7082 u8 reserved_at_20[0x1f]; 7083 u8 lwm[0x1]; 7084 }; 7085 7086 struct mlx5_ifc_modify_rmp_in_bits { 7087 u8 opcode[0x10]; 7088 u8 uid[0x10]; 7089 7090 u8 reserved_at_20[0x10]; 7091 u8 op_mod[0x10]; 7092 7093 u8 rmp_state[0x4]; 7094 u8 reserved_at_44[0x4]; 7095 u8 rmpn[0x18]; 7096 7097 u8 reserved_at_60[0x20]; 7098 7099 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7100 7101 u8 reserved_at_c0[0x40]; 7102 7103 struct mlx5_ifc_rmpc_bits ctx; 7104 }; 7105 7106 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7107 u8 status[0x8]; 7108 u8 reserved_at_8[0x18]; 7109 7110 u8 syndrome[0x20]; 7111 7112 u8 reserved_at_40[0x40]; 7113 }; 7114 7115 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7116 u8 reserved_at_0[0x12]; 7117 u8 affiliation[0x1]; 7118 u8 reserved_at_13[0x1]; 7119 u8 disable_uc_local_lb[0x1]; 7120 u8 disable_mc_local_lb[0x1]; 7121 u8 node_guid[0x1]; 7122 u8 port_guid[0x1]; 7123 u8 min_inline[0x1]; 7124 u8 mtu[0x1]; 7125 u8 change_event[0x1]; 7126 u8 promisc[0x1]; 7127 u8 permanent_address[0x1]; 7128 u8 addresses_list[0x1]; 7129 u8 roce_en[0x1]; 7130 u8 reserved_at_1f[0x1]; 7131 }; 7132 7133 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7134 u8 opcode[0x10]; 7135 u8 reserved_at_10[0x10]; 7136 7137 u8 reserved_at_20[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 other_vport[0x1]; 7141 u8 reserved_at_41[0xf]; 7142 u8 vport_number[0x10]; 7143 7144 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7145 7146 u8 reserved_at_80[0x780]; 7147 7148 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7149 }; 7150 7151 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7152 u8 status[0x8]; 7153 u8 reserved_at_8[0x18]; 7154 7155 u8 syndrome[0x20]; 7156 7157 u8 reserved_at_40[0x40]; 7158 }; 7159 7160 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7161 u8 opcode[0x10]; 7162 u8 reserved_at_10[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 other_vport[0x1]; 7168 u8 reserved_at_41[0xb]; 7169 u8 port_num[0x4]; 7170 u8 vport_number[0x10]; 7171 7172 u8 reserved_at_60[0x20]; 7173 7174 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7175 }; 7176 7177 struct mlx5_ifc_modify_cq_out_bits { 7178 u8 status[0x8]; 7179 u8 reserved_at_8[0x18]; 7180 7181 u8 syndrome[0x20]; 7182 7183 u8 reserved_at_40[0x40]; 7184 }; 7185 7186 enum { 7187 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7188 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7189 }; 7190 7191 struct mlx5_ifc_modify_cq_in_bits { 7192 u8 opcode[0x10]; 7193 u8 uid[0x10]; 7194 7195 u8 reserved_at_20[0x10]; 7196 u8 op_mod[0x10]; 7197 7198 u8 reserved_at_40[0x8]; 7199 u8 cqn[0x18]; 7200 7201 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7202 7203 struct mlx5_ifc_cqc_bits cq_context; 7204 7205 u8 reserved_at_280[0x60]; 7206 7207 u8 cq_umem_valid[0x1]; 7208 u8 reserved_at_2e1[0x1f]; 7209 7210 u8 reserved_at_300[0x580]; 7211 7212 u8 pas[][0x40]; 7213 }; 7214 7215 struct mlx5_ifc_modify_cong_status_out_bits { 7216 u8 status[0x8]; 7217 u8 reserved_at_8[0x18]; 7218 7219 u8 syndrome[0x20]; 7220 7221 u8 reserved_at_40[0x40]; 7222 }; 7223 7224 struct mlx5_ifc_modify_cong_status_in_bits { 7225 u8 opcode[0x10]; 7226 u8 reserved_at_10[0x10]; 7227 7228 u8 reserved_at_20[0x10]; 7229 u8 op_mod[0x10]; 7230 7231 u8 reserved_at_40[0x18]; 7232 u8 priority[0x4]; 7233 u8 cong_protocol[0x4]; 7234 7235 u8 enable[0x1]; 7236 u8 tag_enable[0x1]; 7237 u8 reserved_at_62[0x1e]; 7238 }; 7239 7240 struct mlx5_ifc_modify_cong_params_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_at_8[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_at_40[0x40]; 7247 }; 7248 7249 struct mlx5_ifc_modify_cong_params_in_bits { 7250 u8 opcode[0x10]; 7251 u8 reserved_at_10[0x10]; 7252 7253 u8 reserved_at_20[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 reserved_at_40[0x1c]; 7257 u8 cong_protocol[0x4]; 7258 7259 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7260 7261 u8 reserved_at_80[0x80]; 7262 7263 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7264 }; 7265 7266 struct mlx5_ifc_manage_pages_out_bits { 7267 u8 status[0x8]; 7268 u8 reserved_at_8[0x18]; 7269 7270 u8 syndrome[0x20]; 7271 7272 u8 output_num_entries[0x20]; 7273 7274 u8 reserved_at_60[0x20]; 7275 7276 u8 pas[][0x40]; 7277 }; 7278 7279 enum { 7280 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7281 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7282 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7283 }; 7284 7285 struct mlx5_ifc_manage_pages_in_bits { 7286 u8 opcode[0x10]; 7287 u8 reserved_at_10[0x10]; 7288 7289 u8 reserved_at_20[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 embedded_cpu_function[0x1]; 7293 u8 reserved_at_41[0xf]; 7294 u8 function_id[0x10]; 7295 7296 u8 input_num_entries[0x20]; 7297 7298 u8 pas[][0x40]; 7299 }; 7300 7301 struct mlx5_ifc_mad_ifc_out_bits { 7302 u8 status[0x8]; 7303 u8 reserved_at_8[0x18]; 7304 7305 u8 syndrome[0x20]; 7306 7307 u8 reserved_at_40[0x40]; 7308 7309 u8 response_mad_packet[256][0x8]; 7310 }; 7311 7312 struct mlx5_ifc_mad_ifc_in_bits { 7313 u8 opcode[0x10]; 7314 u8 reserved_at_10[0x10]; 7315 7316 u8 reserved_at_20[0x10]; 7317 u8 op_mod[0x10]; 7318 7319 u8 remote_lid[0x10]; 7320 u8 reserved_at_50[0x8]; 7321 u8 port[0x8]; 7322 7323 u8 reserved_at_60[0x20]; 7324 7325 u8 mad[256][0x8]; 7326 }; 7327 7328 struct mlx5_ifc_init_hca_out_bits { 7329 u8 status[0x8]; 7330 u8 reserved_at_8[0x18]; 7331 7332 u8 syndrome[0x20]; 7333 7334 u8 reserved_at_40[0x40]; 7335 }; 7336 7337 struct mlx5_ifc_init_hca_in_bits { 7338 u8 opcode[0x10]; 7339 u8 reserved_at_10[0x10]; 7340 7341 u8 reserved_at_20[0x10]; 7342 u8 op_mod[0x10]; 7343 7344 u8 reserved_at_40[0x20]; 7345 7346 u8 reserved_at_60[0x2]; 7347 u8 sw_vhca_id[0xe]; 7348 u8 reserved_at_70[0x10]; 7349 7350 u8 sw_owner_id[4][0x20]; 7351 }; 7352 7353 struct mlx5_ifc_init2rtr_qp_out_bits { 7354 u8 status[0x8]; 7355 u8 reserved_at_8[0x18]; 7356 7357 u8 syndrome[0x20]; 7358 7359 u8 reserved_at_40[0x20]; 7360 u8 ece[0x20]; 7361 }; 7362 7363 struct mlx5_ifc_init2rtr_qp_in_bits { 7364 u8 opcode[0x10]; 7365 u8 uid[0x10]; 7366 7367 u8 reserved_at_20[0x10]; 7368 u8 op_mod[0x10]; 7369 7370 u8 reserved_at_40[0x8]; 7371 u8 qpn[0x18]; 7372 7373 u8 reserved_at_60[0x20]; 7374 7375 u8 opt_param_mask[0x20]; 7376 7377 u8 ece[0x20]; 7378 7379 struct mlx5_ifc_qpc_bits qpc; 7380 7381 u8 reserved_at_800[0x80]; 7382 }; 7383 7384 struct mlx5_ifc_init2init_qp_out_bits { 7385 u8 status[0x8]; 7386 u8 reserved_at_8[0x18]; 7387 7388 u8 syndrome[0x20]; 7389 7390 u8 reserved_at_40[0x20]; 7391 u8 ece[0x20]; 7392 }; 7393 7394 struct mlx5_ifc_init2init_qp_in_bits { 7395 u8 opcode[0x10]; 7396 u8 uid[0x10]; 7397 7398 u8 reserved_at_20[0x10]; 7399 u8 op_mod[0x10]; 7400 7401 u8 reserved_at_40[0x8]; 7402 u8 qpn[0x18]; 7403 7404 u8 reserved_at_60[0x20]; 7405 7406 u8 opt_param_mask[0x20]; 7407 7408 u8 ece[0x20]; 7409 7410 struct mlx5_ifc_qpc_bits qpc; 7411 7412 u8 reserved_at_800[0x80]; 7413 }; 7414 7415 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7416 u8 status[0x8]; 7417 u8 reserved_at_8[0x18]; 7418 7419 u8 syndrome[0x20]; 7420 7421 u8 reserved_at_40[0x40]; 7422 7423 u8 packet_headers_log[128][0x8]; 7424 7425 u8 packet_syndrome[64][0x8]; 7426 }; 7427 7428 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7429 u8 opcode[0x10]; 7430 u8 reserved_at_10[0x10]; 7431 7432 u8 reserved_at_20[0x10]; 7433 u8 op_mod[0x10]; 7434 7435 u8 reserved_at_40[0x40]; 7436 }; 7437 7438 struct mlx5_ifc_gen_eqe_in_bits { 7439 u8 opcode[0x10]; 7440 u8 reserved_at_10[0x10]; 7441 7442 u8 reserved_at_20[0x10]; 7443 u8 op_mod[0x10]; 7444 7445 u8 reserved_at_40[0x18]; 7446 u8 eq_number[0x8]; 7447 7448 u8 reserved_at_60[0x20]; 7449 7450 u8 eqe[64][0x8]; 7451 }; 7452 7453 struct mlx5_ifc_gen_eq_out_bits { 7454 u8 status[0x8]; 7455 u8 reserved_at_8[0x18]; 7456 7457 u8 syndrome[0x20]; 7458 7459 u8 reserved_at_40[0x40]; 7460 }; 7461 7462 struct mlx5_ifc_enable_hca_out_bits { 7463 u8 status[0x8]; 7464 u8 reserved_at_8[0x18]; 7465 7466 u8 syndrome[0x20]; 7467 7468 u8 reserved_at_40[0x20]; 7469 }; 7470 7471 struct mlx5_ifc_enable_hca_in_bits { 7472 u8 opcode[0x10]; 7473 u8 reserved_at_10[0x10]; 7474 7475 u8 reserved_at_20[0x10]; 7476 u8 op_mod[0x10]; 7477 7478 u8 embedded_cpu_function[0x1]; 7479 u8 reserved_at_41[0xf]; 7480 u8 function_id[0x10]; 7481 7482 u8 reserved_at_60[0x20]; 7483 }; 7484 7485 struct mlx5_ifc_drain_dct_out_bits { 7486 u8 status[0x8]; 7487 u8 reserved_at_8[0x18]; 7488 7489 u8 syndrome[0x20]; 7490 7491 u8 reserved_at_40[0x40]; 7492 }; 7493 7494 struct mlx5_ifc_drain_dct_in_bits { 7495 u8 opcode[0x10]; 7496 u8 uid[0x10]; 7497 7498 u8 reserved_at_20[0x10]; 7499 u8 op_mod[0x10]; 7500 7501 u8 reserved_at_40[0x8]; 7502 u8 dctn[0x18]; 7503 7504 u8 reserved_at_60[0x20]; 7505 }; 7506 7507 struct mlx5_ifc_disable_hca_out_bits { 7508 u8 status[0x8]; 7509 u8 reserved_at_8[0x18]; 7510 7511 u8 syndrome[0x20]; 7512 7513 u8 reserved_at_40[0x20]; 7514 }; 7515 7516 struct mlx5_ifc_disable_hca_in_bits { 7517 u8 opcode[0x10]; 7518 u8 reserved_at_10[0x10]; 7519 7520 u8 reserved_at_20[0x10]; 7521 u8 op_mod[0x10]; 7522 7523 u8 embedded_cpu_function[0x1]; 7524 u8 reserved_at_41[0xf]; 7525 u8 function_id[0x10]; 7526 7527 u8 reserved_at_60[0x20]; 7528 }; 7529 7530 struct mlx5_ifc_detach_from_mcg_out_bits { 7531 u8 status[0x8]; 7532 u8 reserved_at_8[0x18]; 7533 7534 u8 syndrome[0x20]; 7535 7536 u8 reserved_at_40[0x40]; 7537 }; 7538 7539 struct mlx5_ifc_detach_from_mcg_in_bits { 7540 u8 opcode[0x10]; 7541 u8 uid[0x10]; 7542 7543 u8 reserved_at_20[0x10]; 7544 u8 op_mod[0x10]; 7545 7546 u8 reserved_at_40[0x8]; 7547 u8 qpn[0x18]; 7548 7549 u8 reserved_at_60[0x20]; 7550 7551 u8 multicast_gid[16][0x8]; 7552 }; 7553 7554 struct mlx5_ifc_destroy_xrq_out_bits { 7555 u8 status[0x8]; 7556 u8 reserved_at_8[0x18]; 7557 7558 u8 syndrome[0x20]; 7559 7560 u8 reserved_at_40[0x40]; 7561 }; 7562 7563 struct mlx5_ifc_destroy_xrq_in_bits { 7564 u8 opcode[0x10]; 7565 u8 uid[0x10]; 7566 7567 u8 reserved_at_20[0x10]; 7568 u8 op_mod[0x10]; 7569 7570 u8 reserved_at_40[0x8]; 7571 u8 xrqn[0x18]; 7572 7573 u8 reserved_at_60[0x20]; 7574 }; 7575 7576 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7577 u8 status[0x8]; 7578 u8 reserved_at_8[0x18]; 7579 7580 u8 syndrome[0x20]; 7581 7582 u8 reserved_at_40[0x40]; 7583 }; 7584 7585 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7586 u8 opcode[0x10]; 7587 u8 uid[0x10]; 7588 7589 u8 reserved_at_20[0x10]; 7590 u8 op_mod[0x10]; 7591 7592 u8 reserved_at_40[0x8]; 7593 u8 xrc_srqn[0x18]; 7594 7595 u8 reserved_at_60[0x20]; 7596 }; 7597 7598 struct mlx5_ifc_destroy_tis_out_bits { 7599 u8 status[0x8]; 7600 u8 reserved_at_8[0x18]; 7601 7602 u8 syndrome[0x20]; 7603 7604 u8 reserved_at_40[0x40]; 7605 }; 7606 7607 struct mlx5_ifc_destroy_tis_in_bits { 7608 u8 opcode[0x10]; 7609 u8 uid[0x10]; 7610 7611 u8 reserved_at_20[0x10]; 7612 u8 op_mod[0x10]; 7613 7614 u8 reserved_at_40[0x8]; 7615 u8 tisn[0x18]; 7616 7617 u8 reserved_at_60[0x20]; 7618 }; 7619 7620 struct mlx5_ifc_destroy_tir_out_bits { 7621 u8 status[0x8]; 7622 u8 reserved_at_8[0x18]; 7623 7624 u8 syndrome[0x20]; 7625 7626 u8 reserved_at_40[0x40]; 7627 }; 7628 7629 struct mlx5_ifc_destroy_tir_in_bits { 7630 u8 opcode[0x10]; 7631 u8 uid[0x10]; 7632 7633 u8 reserved_at_20[0x10]; 7634 u8 op_mod[0x10]; 7635 7636 u8 reserved_at_40[0x8]; 7637 u8 tirn[0x18]; 7638 7639 u8 reserved_at_60[0x20]; 7640 }; 7641 7642 struct mlx5_ifc_destroy_srq_out_bits { 7643 u8 status[0x8]; 7644 u8 reserved_at_8[0x18]; 7645 7646 u8 syndrome[0x20]; 7647 7648 u8 reserved_at_40[0x40]; 7649 }; 7650 7651 struct mlx5_ifc_destroy_srq_in_bits { 7652 u8 opcode[0x10]; 7653 u8 uid[0x10]; 7654 7655 u8 reserved_at_20[0x10]; 7656 u8 op_mod[0x10]; 7657 7658 u8 reserved_at_40[0x8]; 7659 u8 srqn[0x18]; 7660 7661 u8 reserved_at_60[0x20]; 7662 }; 7663 7664 struct mlx5_ifc_destroy_sq_out_bits { 7665 u8 status[0x8]; 7666 u8 reserved_at_8[0x18]; 7667 7668 u8 syndrome[0x20]; 7669 7670 u8 reserved_at_40[0x40]; 7671 }; 7672 7673 struct mlx5_ifc_destroy_sq_in_bits { 7674 u8 opcode[0x10]; 7675 u8 uid[0x10]; 7676 7677 u8 reserved_at_20[0x10]; 7678 u8 op_mod[0x10]; 7679 7680 u8 reserved_at_40[0x8]; 7681 u8 sqn[0x18]; 7682 7683 u8 reserved_at_60[0x20]; 7684 }; 7685 7686 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7687 u8 status[0x8]; 7688 u8 reserved_at_8[0x18]; 7689 7690 u8 syndrome[0x20]; 7691 7692 u8 reserved_at_40[0x1c0]; 7693 }; 7694 7695 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7696 u8 opcode[0x10]; 7697 u8 reserved_at_10[0x10]; 7698 7699 u8 reserved_at_20[0x10]; 7700 u8 op_mod[0x10]; 7701 7702 u8 scheduling_hierarchy[0x8]; 7703 u8 reserved_at_48[0x18]; 7704 7705 u8 scheduling_element_id[0x20]; 7706 7707 u8 reserved_at_80[0x180]; 7708 }; 7709 7710 struct mlx5_ifc_destroy_rqt_out_bits { 7711 u8 status[0x8]; 7712 u8 reserved_at_8[0x18]; 7713 7714 u8 syndrome[0x20]; 7715 7716 u8 reserved_at_40[0x40]; 7717 }; 7718 7719 struct mlx5_ifc_destroy_rqt_in_bits { 7720 u8 opcode[0x10]; 7721 u8 uid[0x10]; 7722 7723 u8 reserved_at_20[0x10]; 7724 u8 op_mod[0x10]; 7725 7726 u8 reserved_at_40[0x8]; 7727 u8 rqtn[0x18]; 7728 7729 u8 reserved_at_60[0x20]; 7730 }; 7731 7732 struct mlx5_ifc_destroy_rq_out_bits { 7733 u8 status[0x8]; 7734 u8 reserved_at_8[0x18]; 7735 7736 u8 syndrome[0x20]; 7737 7738 u8 reserved_at_40[0x40]; 7739 }; 7740 7741 struct mlx5_ifc_destroy_rq_in_bits { 7742 u8 opcode[0x10]; 7743 u8 uid[0x10]; 7744 7745 u8 reserved_at_20[0x10]; 7746 u8 op_mod[0x10]; 7747 7748 u8 reserved_at_40[0x8]; 7749 u8 rqn[0x18]; 7750 7751 u8 reserved_at_60[0x20]; 7752 }; 7753 7754 struct mlx5_ifc_set_delay_drop_params_in_bits { 7755 u8 opcode[0x10]; 7756 u8 reserved_at_10[0x10]; 7757 7758 u8 reserved_at_20[0x10]; 7759 u8 op_mod[0x10]; 7760 7761 u8 reserved_at_40[0x20]; 7762 7763 u8 reserved_at_60[0x10]; 7764 u8 delay_drop_timeout[0x10]; 7765 }; 7766 7767 struct mlx5_ifc_set_delay_drop_params_out_bits { 7768 u8 status[0x8]; 7769 u8 reserved_at_8[0x18]; 7770 7771 u8 syndrome[0x20]; 7772 7773 u8 reserved_at_40[0x40]; 7774 }; 7775 7776 struct mlx5_ifc_destroy_rmp_out_bits { 7777 u8 status[0x8]; 7778 u8 reserved_at_8[0x18]; 7779 7780 u8 syndrome[0x20]; 7781 7782 u8 reserved_at_40[0x40]; 7783 }; 7784 7785 struct mlx5_ifc_destroy_rmp_in_bits { 7786 u8 opcode[0x10]; 7787 u8 uid[0x10]; 7788 7789 u8 reserved_at_20[0x10]; 7790 u8 op_mod[0x10]; 7791 7792 u8 reserved_at_40[0x8]; 7793 u8 rmpn[0x18]; 7794 7795 u8 reserved_at_60[0x20]; 7796 }; 7797 7798 struct mlx5_ifc_destroy_qp_out_bits { 7799 u8 status[0x8]; 7800 u8 reserved_at_8[0x18]; 7801 7802 u8 syndrome[0x20]; 7803 7804 u8 reserved_at_40[0x40]; 7805 }; 7806 7807 struct mlx5_ifc_destroy_qp_in_bits { 7808 u8 opcode[0x10]; 7809 u8 uid[0x10]; 7810 7811 u8 reserved_at_20[0x10]; 7812 u8 op_mod[0x10]; 7813 7814 u8 reserved_at_40[0x8]; 7815 u8 qpn[0x18]; 7816 7817 u8 reserved_at_60[0x20]; 7818 }; 7819 7820 struct mlx5_ifc_destroy_psv_out_bits { 7821 u8 status[0x8]; 7822 u8 reserved_at_8[0x18]; 7823 7824 u8 syndrome[0x20]; 7825 7826 u8 reserved_at_40[0x40]; 7827 }; 7828 7829 struct mlx5_ifc_destroy_psv_in_bits { 7830 u8 opcode[0x10]; 7831 u8 reserved_at_10[0x10]; 7832 7833 u8 reserved_at_20[0x10]; 7834 u8 op_mod[0x10]; 7835 7836 u8 reserved_at_40[0x8]; 7837 u8 psvn[0x18]; 7838 7839 u8 reserved_at_60[0x20]; 7840 }; 7841 7842 struct mlx5_ifc_destroy_mkey_out_bits { 7843 u8 status[0x8]; 7844 u8 reserved_at_8[0x18]; 7845 7846 u8 syndrome[0x20]; 7847 7848 u8 reserved_at_40[0x40]; 7849 }; 7850 7851 struct mlx5_ifc_destroy_mkey_in_bits { 7852 u8 opcode[0x10]; 7853 u8 uid[0x10]; 7854 7855 u8 reserved_at_20[0x10]; 7856 u8 op_mod[0x10]; 7857 7858 u8 reserved_at_40[0x8]; 7859 u8 mkey_index[0x18]; 7860 7861 u8 reserved_at_60[0x20]; 7862 }; 7863 7864 struct mlx5_ifc_destroy_flow_table_out_bits { 7865 u8 status[0x8]; 7866 u8 reserved_at_8[0x18]; 7867 7868 u8 syndrome[0x20]; 7869 7870 u8 reserved_at_40[0x40]; 7871 }; 7872 7873 struct mlx5_ifc_destroy_flow_table_in_bits { 7874 u8 opcode[0x10]; 7875 u8 reserved_at_10[0x10]; 7876 7877 u8 reserved_at_20[0x10]; 7878 u8 op_mod[0x10]; 7879 7880 u8 other_vport[0x1]; 7881 u8 reserved_at_41[0xf]; 7882 u8 vport_number[0x10]; 7883 7884 u8 reserved_at_60[0x20]; 7885 7886 u8 table_type[0x8]; 7887 u8 reserved_at_88[0x18]; 7888 7889 u8 reserved_at_a0[0x8]; 7890 u8 table_id[0x18]; 7891 7892 u8 reserved_at_c0[0x140]; 7893 }; 7894 7895 struct mlx5_ifc_destroy_flow_group_out_bits { 7896 u8 status[0x8]; 7897 u8 reserved_at_8[0x18]; 7898 7899 u8 syndrome[0x20]; 7900 7901 u8 reserved_at_40[0x40]; 7902 }; 7903 7904 struct mlx5_ifc_destroy_flow_group_in_bits { 7905 u8 opcode[0x10]; 7906 u8 reserved_at_10[0x10]; 7907 7908 u8 reserved_at_20[0x10]; 7909 u8 op_mod[0x10]; 7910 7911 u8 other_vport[0x1]; 7912 u8 reserved_at_41[0xf]; 7913 u8 vport_number[0x10]; 7914 7915 u8 reserved_at_60[0x20]; 7916 7917 u8 table_type[0x8]; 7918 u8 reserved_at_88[0x18]; 7919 7920 u8 reserved_at_a0[0x8]; 7921 u8 table_id[0x18]; 7922 7923 u8 group_id[0x20]; 7924 7925 u8 reserved_at_e0[0x120]; 7926 }; 7927 7928 struct mlx5_ifc_destroy_eq_out_bits { 7929 u8 status[0x8]; 7930 u8 reserved_at_8[0x18]; 7931 7932 u8 syndrome[0x20]; 7933 7934 u8 reserved_at_40[0x40]; 7935 }; 7936 7937 struct mlx5_ifc_destroy_eq_in_bits { 7938 u8 opcode[0x10]; 7939 u8 reserved_at_10[0x10]; 7940 7941 u8 reserved_at_20[0x10]; 7942 u8 op_mod[0x10]; 7943 7944 u8 reserved_at_40[0x18]; 7945 u8 eq_number[0x8]; 7946 7947 u8 reserved_at_60[0x20]; 7948 }; 7949 7950 struct mlx5_ifc_destroy_dct_out_bits { 7951 u8 status[0x8]; 7952 u8 reserved_at_8[0x18]; 7953 7954 u8 syndrome[0x20]; 7955 7956 u8 reserved_at_40[0x40]; 7957 }; 7958 7959 struct mlx5_ifc_destroy_dct_in_bits { 7960 u8 opcode[0x10]; 7961 u8 uid[0x10]; 7962 7963 u8 reserved_at_20[0x10]; 7964 u8 op_mod[0x10]; 7965 7966 u8 reserved_at_40[0x8]; 7967 u8 dctn[0x18]; 7968 7969 u8 reserved_at_60[0x20]; 7970 }; 7971 7972 struct mlx5_ifc_destroy_cq_out_bits { 7973 u8 status[0x8]; 7974 u8 reserved_at_8[0x18]; 7975 7976 u8 syndrome[0x20]; 7977 7978 u8 reserved_at_40[0x40]; 7979 }; 7980 7981 struct mlx5_ifc_destroy_cq_in_bits { 7982 u8 opcode[0x10]; 7983 u8 uid[0x10]; 7984 7985 u8 reserved_at_20[0x10]; 7986 u8 op_mod[0x10]; 7987 7988 u8 reserved_at_40[0x8]; 7989 u8 cqn[0x18]; 7990 7991 u8 reserved_at_60[0x20]; 7992 }; 7993 7994 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7995 u8 status[0x8]; 7996 u8 reserved_at_8[0x18]; 7997 7998 u8 syndrome[0x20]; 7999 8000 u8 reserved_at_40[0x40]; 8001 }; 8002 8003 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8004 u8 opcode[0x10]; 8005 u8 reserved_at_10[0x10]; 8006 8007 u8 reserved_at_20[0x10]; 8008 u8 op_mod[0x10]; 8009 8010 u8 reserved_at_40[0x20]; 8011 8012 u8 reserved_at_60[0x10]; 8013 u8 vxlan_udp_port[0x10]; 8014 }; 8015 8016 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8017 u8 status[0x8]; 8018 u8 reserved_at_8[0x18]; 8019 8020 u8 syndrome[0x20]; 8021 8022 u8 reserved_at_40[0x40]; 8023 }; 8024 8025 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8026 u8 opcode[0x10]; 8027 u8 reserved_at_10[0x10]; 8028 8029 u8 reserved_at_20[0x10]; 8030 u8 op_mod[0x10]; 8031 8032 u8 reserved_at_40[0x60]; 8033 8034 u8 reserved_at_a0[0x8]; 8035 u8 table_index[0x18]; 8036 8037 u8 reserved_at_c0[0x140]; 8038 }; 8039 8040 struct mlx5_ifc_delete_fte_out_bits { 8041 u8 status[0x8]; 8042 u8 reserved_at_8[0x18]; 8043 8044 u8 syndrome[0x20]; 8045 8046 u8 reserved_at_40[0x40]; 8047 }; 8048 8049 struct mlx5_ifc_delete_fte_in_bits { 8050 u8 opcode[0x10]; 8051 u8 reserved_at_10[0x10]; 8052 8053 u8 reserved_at_20[0x10]; 8054 u8 op_mod[0x10]; 8055 8056 u8 other_vport[0x1]; 8057 u8 reserved_at_41[0xf]; 8058 u8 vport_number[0x10]; 8059 8060 u8 reserved_at_60[0x20]; 8061 8062 u8 table_type[0x8]; 8063 u8 reserved_at_88[0x18]; 8064 8065 u8 reserved_at_a0[0x8]; 8066 u8 table_id[0x18]; 8067 8068 u8 reserved_at_c0[0x40]; 8069 8070 u8 flow_index[0x20]; 8071 8072 u8 reserved_at_120[0xe0]; 8073 }; 8074 8075 struct mlx5_ifc_dealloc_xrcd_out_bits { 8076 u8 status[0x8]; 8077 u8 reserved_at_8[0x18]; 8078 8079 u8 syndrome[0x20]; 8080 8081 u8 reserved_at_40[0x40]; 8082 }; 8083 8084 struct mlx5_ifc_dealloc_xrcd_in_bits { 8085 u8 opcode[0x10]; 8086 u8 uid[0x10]; 8087 8088 u8 reserved_at_20[0x10]; 8089 u8 op_mod[0x10]; 8090 8091 u8 reserved_at_40[0x8]; 8092 u8 xrcd[0x18]; 8093 8094 u8 reserved_at_60[0x20]; 8095 }; 8096 8097 struct mlx5_ifc_dealloc_uar_out_bits { 8098 u8 status[0x8]; 8099 u8 reserved_at_8[0x18]; 8100 8101 u8 syndrome[0x20]; 8102 8103 u8 reserved_at_40[0x40]; 8104 }; 8105 8106 struct mlx5_ifc_dealloc_uar_in_bits { 8107 u8 opcode[0x10]; 8108 u8 uid[0x10]; 8109 8110 u8 reserved_at_20[0x10]; 8111 u8 op_mod[0x10]; 8112 8113 u8 reserved_at_40[0x8]; 8114 u8 uar[0x18]; 8115 8116 u8 reserved_at_60[0x20]; 8117 }; 8118 8119 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8120 u8 status[0x8]; 8121 u8 reserved_at_8[0x18]; 8122 8123 u8 syndrome[0x20]; 8124 8125 u8 reserved_at_40[0x40]; 8126 }; 8127 8128 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8129 u8 opcode[0x10]; 8130 u8 uid[0x10]; 8131 8132 u8 reserved_at_20[0x10]; 8133 u8 op_mod[0x10]; 8134 8135 u8 reserved_at_40[0x8]; 8136 u8 transport_domain[0x18]; 8137 8138 u8 reserved_at_60[0x20]; 8139 }; 8140 8141 struct mlx5_ifc_dealloc_q_counter_out_bits { 8142 u8 status[0x8]; 8143 u8 reserved_at_8[0x18]; 8144 8145 u8 syndrome[0x20]; 8146 8147 u8 reserved_at_40[0x40]; 8148 }; 8149 8150 struct mlx5_ifc_dealloc_q_counter_in_bits { 8151 u8 opcode[0x10]; 8152 u8 reserved_at_10[0x10]; 8153 8154 u8 reserved_at_20[0x10]; 8155 u8 op_mod[0x10]; 8156 8157 u8 reserved_at_40[0x18]; 8158 u8 counter_set_id[0x8]; 8159 8160 u8 reserved_at_60[0x20]; 8161 }; 8162 8163 struct mlx5_ifc_dealloc_pd_out_bits { 8164 u8 status[0x8]; 8165 u8 reserved_at_8[0x18]; 8166 8167 u8 syndrome[0x20]; 8168 8169 u8 reserved_at_40[0x40]; 8170 }; 8171 8172 struct mlx5_ifc_dealloc_pd_in_bits { 8173 u8 opcode[0x10]; 8174 u8 uid[0x10]; 8175 8176 u8 reserved_at_20[0x10]; 8177 u8 op_mod[0x10]; 8178 8179 u8 reserved_at_40[0x8]; 8180 u8 pd[0x18]; 8181 8182 u8 reserved_at_60[0x20]; 8183 }; 8184 8185 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8186 u8 status[0x8]; 8187 u8 reserved_at_8[0x18]; 8188 8189 u8 syndrome[0x20]; 8190 8191 u8 reserved_at_40[0x40]; 8192 }; 8193 8194 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8195 u8 opcode[0x10]; 8196 u8 reserved_at_10[0x10]; 8197 8198 u8 reserved_at_20[0x10]; 8199 u8 op_mod[0x10]; 8200 8201 u8 flow_counter_id[0x20]; 8202 8203 u8 reserved_at_60[0x20]; 8204 }; 8205 8206 struct mlx5_ifc_create_xrq_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_at_8[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_at_40[0x8]; 8213 u8 xrqn[0x18]; 8214 8215 u8 reserved_at_60[0x20]; 8216 }; 8217 8218 struct mlx5_ifc_create_xrq_in_bits { 8219 u8 opcode[0x10]; 8220 u8 uid[0x10]; 8221 8222 u8 reserved_at_20[0x10]; 8223 u8 op_mod[0x10]; 8224 8225 u8 reserved_at_40[0x40]; 8226 8227 struct mlx5_ifc_xrqc_bits xrq_context; 8228 }; 8229 8230 struct mlx5_ifc_create_xrc_srq_out_bits { 8231 u8 status[0x8]; 8232 u8 reserved_at_8[0x18]; 8233 8234 u8 syndrome[0x20]; 8235 8236 u8 reserved_at_40[0x8]; 8237 u8 xrc_srqn[0x18]; 8238 8239 u8 reserved_at_60[0x20]; 8240 }; 8241 8242 struct mlx5_ifc_create_xrc_srq_in_bits { 8243 u8 opcode[0x10]; 8244 u8 uid[0x10]; 8245 8246 u8 reserved_at_20[0x10]; 8247 u8 op_mod[0x10]; 8248 8249 u8 reserved_at_40[0x40]; 8250 8251 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8252 8253 u8 reserved_at_280[0x60]; 8254 8255 u8 xrc_srq_umem_valid[0x1]; 8256 u8 reserved_at_2e1[0x1f]; 8257 8258 u8 reserved_at_300[0x580]; 8259 8260 u8 pas[][0x40]; 8261 }; 8262 8263 struct mlx5_ifc_create_tis_out_bits { 8264 u8 status[0x8]; 8265 u8 reserved_at_8[0x18]; 8266 8267 u8 syndrome[0x20]; 8268 8269 u8 reserved_at_40[0x8]; 8270 u8 tisn[0x18]; 8271 8272 u8 reserved_at_60[0x20]; 8273 }; 8274 8275 struct mlx5_ifc_create_tis_in_bits { 8276 u8 opcode[0x10]; 8277 u8 uid[0x10]; 8278 8279 u8 reserved_at_20[0x10]; 8280 u8 op_mod[0x10]; 8281 8282 u8 reserved_at_40[0xc0]; 8283 8284 struct mlx5_ifc_tisc_bits ctx; 8285 }; 8286 8287 struct mlx5_ifc_create_tir_out_bits { 8288 u8 status[0x8]; 8289 u8 icm_address_63_40[0x18]; 8290 8291 u8 syndrome[0x20]; 8292 8293 u8 icm_address_39_32[0x8]; 8294 u8 tirn[0x18]; 8295 8296 u8 icm_address_31_0[0x20]; 8297 }; 8298 8299 struct mlx5_ifc_create_tir_in_bits { 8300 u8 opcode[0x10]; 8301 u8 uid[0x10]; 8302 8303 u8 reserved_at_20[0x10]; 8304 u8 op_mod[0x10]; 8305 8306 u8 reserved_at_40[0xc0]; 8307 8308 struct mlx5_ifc_tirc_bits ctx; 8309 }; 8310 8311 struct mlx5_ifc_create_srq_out_bits { 8312 u8 status[0x8]; 8313 u8 reserved_at_8[0x18]; 8314 8315 u8 syndrome[0x20]; 8316 8317 u8 reserved_at_40[0x8]; 8318 u8 srqn[0x18]; 8319 8320 u8 reserved_at_60[0x20]; 8321 }; 8322 8323 struct mlx5_ifc_create_srq_in_bits { 8324 u8 opcode[0x10]; 8325 u8 uid[0x10]; 8326 8327 u8 reserved_at_20[0x10]; 8328 u8 op_mod[0x10]; 8329 8330 u8 reserved_at_40[0x40]; 8331 8332 struct mlx5_ifc_srqc_bits srq_context_entry; 8333 8334 u8 reserved_at_280[0x600]; 8335 8336 u8 pas[][0x40]; 8337 }; 8338 8339 struct mlx5_ifc_create_sq_out_bits { 8340 u8 status[0x8]; 8341 u8 reserved_at_8[0x18]; 8342 8343 u8 syndrome[0x20]; 8344 8345 u8 reserved_at_40[0x8]; 8346 u8 sqn[0x18]; 8347 8348 u8 reserved_at_60[0x20]; 8349 }; 8350 8351 struct mlx5_ifc_create_sq_in_bits { 8352 u8 opcode[0x10]; 8353 u8 uid[0x10]; 8354 8355 u8 reserved_at_20[0x10]; 8356 u8 op_mod[0x10]; 8357 8358 u8 reserved_at_40[0xc0]; 8359 8360 struct mlx5_ifc_sqc_bits ctx; 8361 }; 8362 8363 struct mlx5_ifc_create_scheduling_element_out_bits { 8364 u8 status[0x8]; 8365 u8 reserved_at_8[0x18]; 8366 8367 u8 syndrome[0x20]; 8368 8369 u8 reserved_at_40[0x40]; 8370 8371 u8 scheduling_element_id[0x20]; 8372 8373 u8 reserved_at_a0[0x160]; 8374 }; 8375 8376 struct mlx5_ifc_create_scheduling_element_in_bits { 8377 u8 opcode[0x10]; 8378 u8 reserved_at_10[0x10]; 8379 8380 u8 reserved_at_20[0x10]; 8381 u8 op_mod[0x10]; 8382 8383 u8 scheduling_hierarchy[0x8]; 8384 u8 reserved_at_48[0x18]; 8385 8386 u8 reserved_at_60[0xa0]; 8387 8388 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8389 8390 u8 reserved_at_300[0x100]; 8391 }; 8392 8393 struct mlx5_ifc_create_rqt_out_bits { 8394 u8 status[0x8]; 8395 u8 reserved_at_8[0x18]; 8396 8397 u8 syndrome[0x20]; 8398 8399 u8 reserved_at_40[0x8]; 8400 u8 rqtn[0x18]; 8401 8402 u8 reserved_at_60[0x20]; 8403 }; 8404 8405 struct mlx5_ifc_create_rqt_in_bits { 8406 u8 opcode[0x10]; 8407 u8 uid[0x10]; 8408 8409 u8 reserved_at_20[0x10]; 8410 u8 op_mod[0x10]; 8411 8412 u8 reserved_at_40[0xc0]; 8413 8414 struct mlx5_ifc_rqtc_bits rqt_context; 8415 }; 8416 8417 struct mlx5_ifc_create_rq_out_bits { 8418 u8 status[0x8]; 8419 u8 reserved_at_8[0x18]; 8420 8421 u8 syndrome[0x20]; 8422 8423 u8 reserved_at_40[0x8]; 8424 u8 rqn[0x18]; 8425 8426 u8 reserved_at_60[0x20]; 8427 }; 8428 8429 struct mlx5_ifc_create_rq_in_bits { 8430 u8 opcode[0x10]; 8431 u8 uid[0x10]; 8432 8433 u8 reserved_at_20[0x10]; 8434 u8 op_mod[0x10]; 8435 8436 u8 reserved_at_40[0xc0]; 8437 8438 struct mlx5_ifc_rqc_bits ctx; 8439 }; 8440 8441 struct mlx5_ifc_create_rmp_out_bits { 8442 u8 status[0x8]; 8443 u8 reserved_at_8[0x18]; 8444 8445 u8 syndrome[0x20]; 8446 8447 u8 reserved_at_40[0x8]; 8448 u8 rmpn[0x18]; 8449 8450 u8 reserved_at_60[0x20]; 8451 }; 8452 8453 struct mlx5_ifc_create_rmp_in_bits { 8454 u8 opcode[0x10]; 8455 u8 uid[0x10]; 8456 8457 u8 reserved_at_20[0x10]; 8458 u8 op_mod[0x10]; 8459 8460 u8 reserved_at_40[0xc0]; 8461 8462 struct mlx5_ifc_rmpc_bits ctx; 8463 }; 8464 8465 struct mlx5_ifc_create_qp_out_bits { 8466 u8 status[0x8]; 8467 u8 reserved_at_8[0x18]; 8468 8469 u8 syndrome[0x20]; 8470 8471 u8 reserved_at_40[0x8]; 8472 u8 qpn[0x18]; 8473 8474 u8 ece[0x20]; 8475 }; 8476 8477 struct mlx5_ifc_create_qp_in_bits { 8478 u8 opcode[0x10]; 8479 u8 uid[0x10]; 8480 8481 u8 reserved_at_20[0x10]; 8482 u8 op_mod[0x10]; 8483 8484 u8 reserved_at_40[0x8]; 8485 u8 input_qpn[0x18]; 8486 8487 u8 reserved_at_60[0x20]; 8488 u8 opt_param_mask[0x20]; 8489 8490 u8 ece[0x20]; 8491 8492 struct mlx5_ifc_qpc_bits qpc; 8493 8494 u8 reserved_at_800[0x60]; 8495 8496 u8 wq_umem_valid[0x1]; 8497 u8 reserved_at_861[0x1f]; 8498 8499 u8 pas[][0x40]; 8500 }; 8501 8502 struct mlx5_ifc_create_psv_out_bits { 8503 u8 status[0x8]; 8504 u8 reserved_at_8[0x18]; 8505 8506 u8 syndrome[0x20]; 8507 8508 u8 reserved_at_40[0x40]; 8509 8510 u8 reserved_at_80[0x8]; 8511 u8 psv0_index[0x18]; 8512 8513 u8 reserved_at_a0[0x8]; 8514 u8 psv1_index[0x18]; 8515 8516 u8 reserved_at_c0[0x8]; 8517 u8 psv2_index[0x18]; 8518 8519 u8 reserved_at_e0[0x8]; 8520 u8 psv3_index[0x18]; 8521 }; 8522 8523 struct mlx5_ifc_create_psv_in_bits { 8524 u8 opcode[0x10]; 8525 u8 reserved_at_10[0x10]; 8526 8527 u8 reserved_at_20[0x10]; 8528 u8 op_mod[0x10]; 8529 8530 u8 num_psv[0x4]; 8531 u8 reserved_at_44[0x4]; 8532 u8 pd[0x18]; 8533 8534 u8 reserved_at_60[0x20]; 8535 }; 8536 8537 struct mlx5_ifc_create_mkey_out_bits { 8538 u8 status[0x8]; 8539 u8 reserved_at_8[0x18]; 8540 8541 u8 syndrome[0x20]; 8542 8543 u8 reserved_at_40[0x8]; 8544 u8 mkey_index[0x18]; 8545 8546 u8 reserved_at_60[0x20]; 8547 }; 8548 8549 struct mlx5_ifc_create_mkey_in_bits { 8550 u8 opcode[0x10]; 8551 u8 uid[0x10]; 8552 8553 u8 reserved_at_20[0x10]; 8554 u8 op_mod[0x10]; 8555 8556 u8 reserved_at_40[0x20]; 8557 8558 u8 pg_access[0x1]; 8559 u8 mkey_umem_valid[0x1]; 8560 u8 reserved_at_62[0x1e]; 8561 8562 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8563 8564 u8 reserved_at_280[0x80]; 8565 8566 u8 translations_octword_actual_size[0x20]; 8567 8568 u8 reserved_at_320[0x560]; 8569 8570 u8 klm_pas_mtt[][0x20]; 8571 }; 8572 8573 enum { 8574 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8575 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8576 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8577 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8578 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8579 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8580 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8581 }; 8582 8583 struct mlx5_ifc_create_flow_table_out_bits { 8584 u8 status[0x8]; 8585 u8 icm_address_63_40[0x18]; 8586 8587 u8 syndrome[0x20]; 8588 8589 u8 icm_address_39_32[0x8]; 8590 u8 table_id[0x18]; 8591 8592 u8 icm_address_31_0[0x20]; 8593 }; 8594 8595 struct mlx5_ifc_create_flow_table_in_bits { 8596 u8 opcode[0x10]; 8597 u8 uid[0x10]; 8598 8599 u8 reserved_at_20[0x10]; 8600 u8 op_mod[0x10]; 8601 8602 u8 other_vport[0x1]; 8603 u8 reserved_at_41[0xf]; 8604 u8 vport_number[0x10]; 8605 8606 u8 reserved_at_60[0x20]; 8607 8608 u8 table_type[0x8]; 8609 u8 reserved_at_88[0x18]; 8610 8611 u8 reserved_at_a0[0x20]; 8612 8613 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8614 }; 8615 8616 struct mlx5_ifc_create_flow_group_out_bits { 8617 u8 status[0x8]; 8618 u8 reserved_at_8[0x18]; 8619 8620 u8 syndrome[0x20]; 8621 8622 u8 reserved_at_40[0x8]; 8623 u8 group_id[0x18]; 8624 8625 u8 reserved_at_60[0x20]; 8626 }; 8627 8628 enum { 8629 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8630 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8631 }; 8632 8633 enum { 8634 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8635 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8636 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8637 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8638 }; 8639 8640 struct mlx5_ifc_create_flow_group_in_bits { 8641 u8 opcode[0x10]; 8642 u8 reserved_at_10[0x10]; 8643 8644 u8 reserved_at_20[0x10]; 8645 u8 op_mod[0x10]; 8646 8647 u8 other_vport[0x1]; 8648 u8 reserved_at_41[0xf]; 8649 u8 vport_number[0x10]; 8650 8651 u8 reserved_at_60[0x20]; 8652 8653 u8 table_type[0x8]; 8654 u8 reserved_at_88[0x4]; 8655 u8 group_type[0x4]; 8656 u8 reserved_at_90[0x10]; 8657 8658 u8 reserved_at_a0[0x8]; 8659 u8 table_id[0x18]; 8660 8661 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8662 8663 u8 reserved_at_c1[0x1f]; 8664 8665 u8 start_flow_index[0x20]; 8666 8667 u8 reserved_at_100[0x20]; 8668 8669 u8 end_flow_index[0x20]; 8670 8671 u8 reserved_at_140[0x10]; 8672 u8 match_definer_id[0x10]; 8673 8674 u8 reserved_at_160[0x80]; 8675 8676 u8 reserved_at_1e0[0x18]; 8677 u8 match_criteria_enable[0x8]; 8678 8679 struct mlx5_ifc_fte_match_param_bits match_criteria; 8680 8681 u8 reserved_at_1200[0xe00]; 8682 }; 8683 8684 struct mlx5_ifc_create_eq_out_bits { 8685 u8 status[0x8]; 8686 u8 reserved_at_8[0x18]; 8687 8688 u8 syndrome[0x20]; 8689 8690 u8 reserved_at_40[0x18]; 8691 u8 eq_number[0x8]; 8692 8693 u8 reserved_at_60[0x20]; 8694 }; 8695 8696 struct mlx5_ifc_create_eq_in_bits { 8697 u8 opcode[0x10]; 8698 u8 uid[0x10]; 8699 8700 u8 reserved_at_20[0x10]; 8701 u8 op_mod[0x10]; 8702 8703 u8 reserved_at_40[0x40]; 8704 8705 struct mlx5_ifc_eqc_bits eq_context_entry; 8706 8707 u8 reserved_at_280[0x40]; 8708 8709 u8 event_bitmask[4][0x40]; 8710 8711 u8 reserved_at_3c0[0x4c0]; 8712 8713 u8 pas[][0x40]; 8714 }; 8715 8716 struct mlx5_ifc_create_dct_out_bits { 8717 u8 status[0x8]; 8718 u8 reserved_at_8[0x18]; 8719 8720 u8 syndrome[0x20]; 8721 8722 u8 reserved_at_40[0x8]; 8723 u8 dctn[0x18]; 8724 8725 u8 ece[0x20]; 8726 }; 8727 8728 struct mlx5_ifc_create_dct_in_bits { 8729 u8 opcode[0x10]; 8730 u8 uid[0x10]; 8731 8732 u8 reserved_at_20[0x10]; 8733 u8 op_mod[0x10]; 8734 8735 u8 reserved_at_40[0x40]; 8736 8737 struct mlx5_ifc_dctc_bits dct_context_entry; 8738 8739 u8 reserved_at_280[0x180]; 8740 }; 8741 8742 struct mlx5_ifc_create_cq_out_bits { 8743 u8 status[0x8]; 8744 u8 reserved_at_8[0x18]; 8745 8746 u8 syndrome[0x20]; 8747 8748 u8 reserved_at_40[0x8]; 8749 u8 cqn[0x18]; 8750 8751 u8 reserved_at_60[0x20]; 8752 }; 8753 8754 struct mlx5_ifc_create_cq_in_bits { 8755 u8 opcode[0x10]; 8756 u8 uid[0x10]; 8757 8758 u8 reserved_at_20[0x10]; 8759 u8 op_mod[0x10]; 8760 8761 u8 reserved_at_40[0x40]; 8762 8763 struct mlx5_ifc_cqc_bits cq_context; 8764 8765 u8 reserved_at_280[0x60]; 8766 8767 u8 cq_umem_valid[0x1]; 8768 u8 reserved_at_2e1[0x59f]; 8769 8770 u8 pas[][0x40]; 8771 }; 8772 8773 struct mlx5_ifc_config_int_moderation_out_bits { 8774 u8 status[0x8]; 8775 u8 reserved_at_8[0x18]; 8776 8777 u8 syndrome[0x20]; 8778 8779 u8 reserved_at_40[0x4]; 8780 u8 min_delay[0xc]; 8781 u8 int_vector[0x10]; 8782 8783 u8 reserved_at_60[0x20]; 8784 }; 8785 8786 enum { 8787 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8788 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8789 }; 8790 8791 struct mlx5_ifc_config_int_moderation_in_bits { 8792 u8 opcode[0x10]; 8793 u8 reserved_at_10[0x10]; 8794 8795 u8 reserved_at_20[0x10]; 8796 u8 op_mod[0x10]; 8797 8798 u8 reserved_at_40[0x4]; 8799 u8 min_delay[0xc]; 8800 u8 int_vector[0x10]; 8801 8802 u8 reserved_at_60[0x20]; 8803 }; 8804 8805 struct mlx5_ifc_attach_to_mcg_out_bits { 8806 u8 status[0x8]; 8807 u8 reserved_at_8[0x18]; 8808 8809 u8 syndrome[0x20]; 8810 8811 u8 reserved_at_40[0x40]; 8812 }; 8813 8814 struct mlx5_ifc_attach_to_mcg_in_bits { 8815 u8 opcode[0x10]; 8816 u8 uid[0x10]; 8817 8818 u8 reserved_at_20[0x10]; 8819 u8 op_mod[0x10]; 8820 8821 u8 reserved_at_40[0x8]; 8822 u8 qpn[0x18]; 8823 8824 u8 reserved_at_60[0x20]; 8825 8826 u8 multicast_gid[16][0x8]; 8827 }; 8828 8829 struct mlx5_ifc_arm_xrq_out_bits { 8830 u8 status[0x8]; 8831 u8 reserved_at_8[0x18]; 8832 8833 u8 syndrome[0x20]; 8834 8835 u8 reserved_at_40[0x40]; 8836 }; 8837 8838 struct mlx5_ifc_arm_xrq_in_bits { 8839 u8 opcode[0x10]; 8840 u8 reserved_at_10[0x10]; 8841 8842 u8 reserved_at_20[0x10]; 8843 u8 op_mod[0x10]; 8844 8845 u8 reserved_at_40[0x8]; 8846 u8 xrqn[0x18]; 8847 8848 u8 reserved_at_60[0x10]; 8849 u8 lwm[0x10]; 8850 }; 8851 8852 struct mlx5_ifc_arm_xrc_srq_out_bits { 8853 u8 status[0x8]; 8854 u8 reserved_at_8[0x18]; 8855 8856 u8 syndrome[0x20]; 8857 8858 u8 reserved_at_40[0x40]; 8859 }; 8860 8861 enum { 8862 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8863 }; 8864 8865 struct mlx5_ifc_arm_xrc_srq_in_bits { 8866 u8 opcode[0x10]; 8867 u8 uid[0x10]; 8868 8869 u8 reserved_at_20[0x10]; 8870 u8 op_mod[0x10]; 8871 8872 u8 reserved_at_40[0x8]; 8873 u8 xrc_srqn[0x18]; 8874 8875 u8 reserved_at_60[0x10]; 8876 u8 lwm[0x10]; 8877 }; 8878 8879 struct mlx5_ifc_arm_rq_out_bits { 8880 u8 status[0x8]; 8881 u8 reserved_at_8[0x18]; 8882 8883 u8 syndrome[0x20]; 8884 8885 u8 reserved_at_40[0x40]; 8886 }; 8887 8888 enum { 8889 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8890 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8891 }; 8892 8893 struct mlx5_ifc_arm_rq_in_bits { 8894 u8 opcode[0x10]; 8895 u8 uid[0x10]; 8896 8897 u8 reserved_at_20[0x10]; 8898 u8 op_mod[0x10]; 8899 8900 u8 reserved_at_40[0x8]; 8901 u8 srq_number[0x18]; 8902 8903 u8 reserved_at_60[0x10]; 8904 u8 lwm[0x10]; 8905 }; 8906 8907 struct mlx5_ifc_arm_dct_out_bits { 8908 u8 status[0x8]; 8909 u8 reserved_at_8[0x18]; 8910 8911 u8 syndrome[0x20]; 8912 8913 u8 reserved_at_40[0x40]; 8914 }; 8915 8916 struct mlx5_ifc_arm_dct_in_bits { 8917 u8 opcode[0x10]; 8918 u8 reserved_at_10[0x10]; 8919 8920 u8 reserved_at_20[0x10]; 8921 u8 op_mod[0x10]; 8922 8923 u8 reserved_at_40[0x8]; 8924 u8 dct_number[0x18]; 8925 8926 u8 reserved_at_60[0x20]; 8927 }; 8928 8929 struct mlx5_ifc_alloc_xrcd_out_bits { 8930 u8 status[0x8]; 8931 u8 reserved_at_8[0x18]; 8932 8933 u8 syndrome[0x20]; 8934 8935 u8 reserved_at_40[0x8]; 8936 u8 xrcd[0x18]; 8937 8938 u8 reserved_at_60[0x20]; 8939 }; 8940 8941 struct mlx5_ifc_alloc_xrcd_in_bits { 8942 u8 opcode[0x10]; 8943 u8 uid[0x10]; 8944 8945 u8 reserved_at_20[0x10]; 8946 u8 op_mod[0x10]; 8947 8948 u8 reserved_at_40[0x40]; 8949 }; 8950 8951 struct mlx5_ifc_alloc_uar_out_bits { 8952 u8 status[0x8]; 8953 u8 reserved_at_8[0x18]; 8954 8955 u8 syndrome[0x20]; 8956 8957 u8 reserved_at_40[0x8]; 8958 u8 uar[0x18]; 8959 8960 u8 reserved_at_60[0x20]; 8961 }; 8962 8963 struct mlx5_ifc_alloc_uar_in_bits { 8964 u8 opcode[0x10]; 8965 u8 uid[0x10]; 8966 8967 u8 reserved_at_20[0x10]; 8968 u8 op_mod[0x10]; 8969 8970 u8 reserved_at_40[0x40]; 8971 }; 8972 8973 struct mlx5_ifc_alloc_transport_domain_out_bits { 8974 u8 status[0x8]; 8975 u8 reserved_at_8[0x18]; 8976 8977 u8 syndrome[0x20]; 8978 8979 u8 reserved_at_40[0x8]; 8980 u8 transport_domain[0x18]; 8981 8982 u8 reserved_at_60[0x20]; 8983 }; 8984 8985 struct mlx5_ifc_alloc_transport_domain_in_bits { 8986 u8 opcode[0x10]; 8987 u8 uid[0x10]; 8988 8989 u8 reserved_at_20[0x10]; 8990 u8 op_mod[0x10]; 8991 8992 u8 reserved_at_40[0x40]; 8993 }; 8994 8995 struct mlx5_ifc_alloc_q_counter_out_bits { 8996 u8 status[0x8]; 8997 u8 reserved_at_8[0x18]; 8998 8999 u8 syndrome[0x20]; 9000 9001 u8 reserved_at_40[0x18]; 9002 u8 counter_set_id[0x8]; 9003 9004 u8 reserved_at_60[0x20]; 9005 }; 9006 9007 struct mlx5_ifc_alloc_q_counter_in_bits { 9008 u8 opcode[0x10]; 9009 u8 uid[0x10]; 9010 9011 u8 reserved_at_20[0x10]; 9012 u8 op_mod[0x10]; 9013 9014 u8 reserved_at_40[0x40]; 9015 }; 9016 9017 struct mlx5_ifc_alloc_pd_out_bits { 9018 u8 status[0x8]; 9019 u8 reserved_at_8[0x18]; 9020 9021 u8 syndrome[0x20]; 9022 9023 u8 reserved_at_40[0x8]; 9024 u8 pd[0x18]; 9025 9026 u8 reserved_at_60[0x20]; 9027 }; 9028 9029 struct mlx5_ifc_alloc_pd_in_bits { 9030 u8 opcode[0x10]; 9031 u8 uid[0x10]; 9032 9033 u8 reserved_at_20[0x10]; 9034 u8 op_mod[0x10]; 9035 9036 u8 reserved_at_40[0x40]; 9037 }; 9038 9039 struct mlx5_ifc_alloc_flow_counter_out_bits { 9040 u8 status[0x8]; 9041 u8 reserved_at_8[0x18]; 9042 9043 u8 syndrome[0x20]; 9044 9045 u8 flow_counter_id[0x20]; 9046 9047 u8 reserved_at_60[0x20]; 9048 }; 9049 9050 struct mlx5_ifc_alloc_flow_counter_in_bits { 9051 u8 opcode[0x10]; 9052 u8 reserved_at_10[0x10]; 9053 9054 u8 reserved_at_20[0x10]; 9055 u8 op_mod[0x10]; 9056 9057 u8 reserved_at_40[0x38]; 9058 u8 flow_counter_bulk[0x8]; 9059 }; 9060 9061 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9062 u8 status[0x8]; 9063 u8 reserved_at_8[0x18]; 9064 9065 u8 syndrome[0x20]; 9066 9067 u8 reserved_at_40[0x40]; 9068 }; 9069 9070 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9071 u8 opcode[0x10]; 9072 u8 reserved_at_10[0x10]; 9073 9074 u8 reserved_at_20[0x10]; 9075 u8 op_mod[0x10]; 9076 9077 u8 reserved_at_40[0x20]; 9078 9079 u8 reserved_at_60[0x10]; 9080 u8 vxlan_udp_port[0x10]; 9081 }; 9082 9083 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9084 u8 status[0x8]; 9085 u8 reserved_at_8[0x18]; 9086 9087 u8 syndrome[0x20]; 9088 9089 u8 reserved_at_40[0x40]; 9090 }; 9091 9092 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9093 u8 rate_limit[0x20]; 9094 9095 u8 burst_upper_bound[0x20]; 9096 9097 u8 reserved_at_40[0x10]; 9098 u8 typical_packet_size[0x10]; 9099 9100 u8 reserved_at_60[0x120]; 9101 }; 9102 9103 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9104 u8 opcode[0x10]; 9105 u8 uid[0x10]; 9106 9107 u8 reserved_at_20[0x10]; 9108 u8 op_mod[0x10]; 9109 9110 u8 reserved_at_40[0x10]; 9111 u8 rate_limit_index[0x10]; 9112 9113 u8 reserved_at_60[0x20]; 9114 9115 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9116 }; 9117 9118 struct mlx5_ifc_access_register_out_bits { 9119 u8 status[0x8]; 9120 u8 reserved_at_8[0x18]; 9121 9122 u8 syndrome[0x20]; 9123 9124 u8 reserved_at_40[0x40]; 9125 9126 u8 register_data[][0x20]; 9127 }; 9128 9129 enum { 9130 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9131 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9132 }; 9133 9134 struct mlx5_ifc_access_register_in_bits { 9135 u8 opcode[0x10]; 9136 u8 reserved_at_10[0x10]; 9137 9138 u8 reserved_at_20[0x10]; 9139 u8 op_mod[0x10]; 9140 9141 u8 reserved_at_40[0x10]; 9142 u8 register_id[0x10]; 9143 9144 u8 argument[0x20]; 9145 9146 u8 register_data[][0x20]; 9147 }; 9148 9149 struct mlx5_ifc_sltp_reg_bits { 9150 u8 status[0x4]; 9151 u8 version[0x4]; 9152 u8 local_port[0x8]; 9153 u8 pnat[0x2]; 9154 u8 reserved_at_12[0x2]; 9155 u8 lane[0x4]; 9156 u8 reserved_at_18[0x8]; 9157 9158 u8 reserved_at_20[0x20]; 9159 9160 u8 reserved_at_40[0x7]; 9161 u8 polarity[0x1]; 9162 u8 ob_tap0[0x8]; 9163 u8 ob_tap1[0x8]; 9164 u8 ob_tap2[0x8]; 9165 9166 u8 reserved_at_60[0xc]; 9167 u8 ob_preemp_mode[0x4]; 9168 u8 ob_reg[0x8]; 9169 u8 ob_bias[0x8]; 9170 9171 u8 reserved_at_80[0x20]; 9172 }; 9173 9174 struct mlx5_ifc_slrg_reg_bits { 9175 u8 status[0x4]; 9176 u8 version[0x4]; 9177 u8 local_port[0x8]; 9178 u8 pnat[0x2]; 9179 u8 reserved_at_12[0x2]; 9180 u8 lane[0x4]; 9181 u8 reserved_at_18[0x8]; 9182 9183 u8 time_to_link_up[0x10]; 9184 u8 reserved_at_30[0xc]; 9185 u8 grade_lane_speed[0x4]; 9186 9187 u8 grade_version[0x8]; 9188 u8 grade[0x18]; 9189 9190 u8 reserved_at_60[0x4]; 9191 u8 height_grade_type[0x4]; 9192 u8 height_grade[0x18]; 9193 9194 u8 height_dz[0x10]; 9195 u8 height_dv[0x10]; 9196 9197 u8 reserved_at_a0[0x10]; 9198 u8 height_sigma[0x10]; 9199 9200 u8 reserved_at_c0[0x20]; 9201 9202 u8 reserved_at_e0[0x4]; 9203 u8 phase_grade_type[0x4]; 9204 u8 phase_grade[0x18]; 9205 9206 u8 reserved_at_100[0x8]; 9207 u8 phase_eo_pos[0x8]; 9208 u8 reserved_at_110[0x8]; 9209 u8 phase_eo_neg[0x8]; 9210 9211 u8 ffe_set_tested[0x10]; 9212 u8 test_errors_per_lane[0x10]; 9213 }; 9214 9215 struct mlx5_ifc_pvlc_reg_bits { 9216 u8 reserved_at_0[0x8]; 9217 u8 local_port[0x8]; 9218 u8 reserved_at_10[0x10]; 9219 9220 u8 reserved_at_20[0x1c]; 9221 u8 vl_hw_cap[0x4]; 9222 9223 u8 reserved_at_40[0x1c]; 9224 u8 vl_admin[0x4]; 9225 9226 u8 reserved_at_60[0x1c]; 9227 u8 vl_operational[0x4]; 9228 }; 9229 9230 struct mlx5_ifc_pude_reg_bits { 9231 u8 swid[0x8]; 9232 u8 local_port[0x8]; 9233 u8 reserved_at_10[0x4]; 9234 u8 admin_status[0x4]; 9235 u8 reserved_at_18[0x4]; 9236 u8 oper_status[0x4]; 9237 9238 u8 reserved_at_20[0x60]; 9239 }; 9240 9241 struct mlx5_ifc_ptys_reg_bits { 9242 u8 reserved_at_0[0x1]; 9243 u8 an_disable_admin[0x1]; 9244 u8 an_disable_cap[0x1]; 9245 u8 reserved_at_3[0x5]; 9246 u8 local_port[0x8]; 9247 u8 reserved_at_10[0xd]; 9248 u8 proto_mask[0x3]; 9249 9250 u8 an_status[0x4]; 9251 u8 reserved_at_24[0xc]; 9252 u8 data_rate_oper[0x10]; 9253 9254 u8 ext_eth_proto_capability[0x20]; 9255 9256 u8 eth_proto_capability[0x20]; 9257 9258 u8 ib_link_width_capability[0x10]; 9259 u8 ib_proto_capability[0x10]; 9260 9261 u8 ext_eth_proto_admin[0x20]; 9262 9263 u8 eth_proto_admin[0x20]; 9264 9265 u8 ib_link_width_admin[0x10]; 9266 u8 ib_proto_admin[0x10]; 9267 9268 u8 ext_eth_proto_oper[0x20]; 9269 9270 u8 eth_proto_oper[0x20]; 9271 9272 u8 ib_link_width_oper[0x10]; 9273 u8 ib_proto_oper[0x10]; 9274 9275 u8 reserved_at_160[0x1c]; 9276 u8 connector_type[0x4]; 9277 9278 u8 eth_proto_lp_advertise[0x20]; 9279 9280 u8 reserved_at_1a0[0x60]; 9281 }; 9282 9283 struct mlx5_ifc_mlcr_reg_bits { 9284 u8 reserved_at_0[0x8]; 9285 u8 local_port[0x8]; 9286 u8 reserved_at_10[0x20]; 9287 9288 u8 beacon_duration[0x10]; 9289 u8 reserved_at_40[0x10]; 9290 9291 u8 beacon_remain[0x10]; 9292 }; 9293 9294 struct mlx5_ifc_ptas_reg_bits { 9295 u8 reserved_at_0[0x20]; 9296 9297 u8 algorithm_options[0x10]; 9298 u8 reserved_at_30[0x4]; 9299 u8 repetitions_mode[0x4]; 9300 u8 num_of_repetitions[0x8]; 9301 9302 u8 grade_version[0x8]; 9303 u8 height_grade_type[0x4]; 9304 u8 phase_grade_type[0x4]; 9305 u8 height_grade_weight[0x8]; 9306 u8 phase_grade_weight[0x8]; 9307 9308 u8 gisim_measure_bits[0x10]; 9309 u8 adaptive_tap_measure_bits[0x10]; 9310 9311 u8 ber_bath_high_error_threshold[0x10]; 9312 u8 ber_bath_mid_error_threshold[0x10]; 9313 9314 u8 ber_bath_low_error_threshold[0x10]; 9315 u8 one_ratio_high_threshold[0x10]; 9316 9317 u8 one_ratio_high_mid_threshold[0x10]; 9318 u8 one_ratio_low_mid_threshold[0x10]; 9319 9320 u8 one_ratio_low_threshold[0x10]; 9321 u8 ndeo_error_threshold[0x10]; 9322 9323 u8 mixer_offset_step_size[0x10]; 9324 u8 reserved_at_110[0x8]; 9325 u8 mix90_phase_for_voltage_bath[0x8]; 9326 9327 u8 mixer_offset_start[0x10]; 9328 u8 mixer_offset_end[0x10]; 9329 9330 u8 reserved_at_140[0x15]; 9331 u8 ber_test_time[0xb]; 9332 }; 9333 9334 struct mlx5_ifc_pspa_reg_bits { 9335 u8 swid[0x8]; 9336 u8 local_port[0x8]; 9337 u8 sub_port[0x8]; 9338 u8 reserved_at_18[0x8]; 9339 9340 u8 reserved_at_20[0x20]; 9341 }; 9342 9343 struct mlx5_ifc_pqdr_reg_bits { 9344 u8 reserved_at_0[0x8]; 9345 u8 local_port[0x8]; 9346 u8 reserved_at_10[0x5]; 9347 u8 prio[0x3]; 9348 u8 reserved_at_18[0x6]; 9349 u8 mode[0x2]; 9350 9351 u8 reserved_at_20[0x20]; 9352 9353 u8 reserved_at_40[0x10]; 9354 u8 min_threshold[0x10]; 9355 9356 u8 reserved_at_60[0x10]; 9357 u8 max_threshold[0x10]; 9358 9359 u8 reserved_at_80[0x10]; 9360 u8 mark_probability_denominator[0x10]; 9361 9362 u8 reserved_at_a0[0x60]; 9363 }; 9364 9365 struct mlx5_ifc_ppsc_reg_bits { 9366 u8 reserved_at_0[0x8]; 9367 u8 local_port[0x8]; 9368 u8 reserved_at_10[0x10]; 9369 9370 u8 reserved_at_20[0x60]; 9371 9372 u8 reserved_at_80[0x1c]; 9373 u8 wrps_admin[0x4]; 9374 9375 u8 reserved_at_a0[0x1c]; 9376 u8 wrps_status[0x4]; 9377 9378 u8 reserved_at_c0[0x8]; 9379 u8 up_threshold[0x8]; 9380 u8 reserved_at_d0[0x8]; 9381 u8 down_threshold[0x8]; 9382 9383 u8 reserved_at_e0[0x20]; 9384 9385 u8 reserved_at_100[0x1c]; 9386 u8 srps_admin[0x4]; 9387 9388 u8 reserved_at_120[0x1c]; 9389 u8 srps_status[0x4]; 9390 9391 u8 reserved_at_140[0x40]; 9392 }; 9393 9394 struct mlx5_ifc_pplr_reg_bits { 9395 u8 reserved_at_0[0x8]; 9396 u8 local_port[0x8]; 9397 u8 reserved_at_10[0x10]; 9398 9399 u8 reserved_at_20[0x8]; 9400 u8 lb_cap[0x8]; 9401 u8 reserved_at_30[0x8]; 9402 u8 lb_en[0x8]; 9403 }; 9404 9405 struct mlx5_ifc_pplm_reg_bits { 9406 u8 reserved_at_0[0x8]; 9407 u8 local_port[0x8]; 9408 u8 reserved_at_10[0x10]; 9409 9410 u8 reserved_at_20[0x20]; 9411 9412 u8 port_profile_mode[0x8]; 9413 u8 static_port_profile[0x8]; 9414 u8 active_port_profile[0x8]; 9415 u8 reserved_at_58[0x8]; 9416 9417 u8 retransmission_active[0x8]; 9418 u8 fec_mode_active[0x18]; 9419 9420 u8 rs_fec_correction_bypass_cap[0x4]; 9421 u8 reserved_at_84[0x8]; 9422 u8 fec_override_cap_56g[0x4]; 9423 u8 fec_override_cap_100g[0x4]; 9424 u8 fec_override_cap_50g[0x4]; 9425 u8 fec_override_cap_25g[0x4]; 9426 u8 fec_override_cap_10g_40g[0x4]; 9427 9428 u8 rs_fec_correction_bypass_admin[0x4]; 9429 u8 reserved_at_a4[0x8]; 9430 u8 fec_override_admin_56g[0x4]; 9431 u8 fec_override_admin_100g[0x4]; 9432 u8 fec_override_admin_50g[0x4]; 9433 u8 fec_override_admin_25g[0x4]; 9434 u8 fec_override_admin_10g_40g[0x4]; 9435 9436 u8 fec_override_cap_400g_8x[0x10]; 9437 u8 fec_override_cap_200g_4x[0x10]; 9438 9439 u8 fec_override_cap_100g_2x[0x10]; 9440 u8 fec_override_cap_50g_1x[0x10]; 9441 9442 u8 fec_override_admin_400g_8x[0x10]; 9443 u8 fec_override_admin_200g_4x[0x10]; 9444 9445 u8 fec_override_admin_100g_2x[0x10]; 9446 u8 fec_override_admin_50g_1x[0x10]; 9447 9448 u8 reserved_at_140[0x140]; 9449 }; 9450 9451 struct mlx5_ifc_ppcnt_reg_bits { 9452 u8 swid[0x8]; 9453 u8 local_port[0x8]; 9454 u8 pnat[0x2]; 9455 u8 reserved_at_12[0x8]; 9456 u8 grp[0x6]; 9457 9458 u8 clr[0x1]; 9459 u8 reserved_at_21[0x1c]; 9460 u8 prio_tc[0x3]; 9461 9462 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9463 }; 9464 9465 struct mlx5_ifc_mpein_reg_bits { 9466 u8 reserved_at_0[0x2]; 9467 u8 depth[0x6]; 9468 u8 pcie_index[0x8]; 9469 u8 node[0x8]; 9470 u8 reserved_at_18[0x8]; 9471 9472 u8 capability_mask[0x20]; 9473 9474 u8 reserved_at_40[0x8]; 9475 u8 link_width_enabled[0x8]; 9476 u8 link_speed_enabled[0x10]; 9477 9478 u8 lane0_physical_position[0x8]; 9479 u8 link_width_active[0x8]; 9480 u8 link_speed_active[0x10]; 9481 9482 u8 num_of_pfs[0x10]; 9483 u8 num_of_vfs[0x10]; 9484 9485 u8 bdf0[0x10]; 9486 u8 reserved_at_b0[0x10]; 9487 9488 u8 max_read_request_size[0x4]; 9489 u8 max_payload_size[0x4]; 9490 u8 reserved_at_c8[0x5]; 9491 u8 pwr_status[0x3]; 9492 u8 port_type[0x4]; 9493 u8 reserved_at_d4[0xb]; 9494 u8 lane_reversal[0x1]; 9495 9496 u8 reserved_at_e0[0x14]; 9497 u8 pci_power[0xc]; 9498 9499 u8 reserved_at_100[0x20]; 9500 9501 u8 device_status[0x10]; 9502 u8 port_state[0x8]; 9503 u8 reserved_at_138[0x8]; 9504 9505 u8 reserved_at_140[0x10]; 9506 u8 receiver_detect_result[0x10]; 9507 9508 u8 reserved_at_160[0x20]; 9509 }; 9510 9511 struct mlx5_ifc_mpcnt_reg_bits { 9512 u8 reserved_at_0[0x8]; 9513 u8 pcie_index[0x8]; 9514 u8 reserved_at_10[0xa]; 9515 u8 grp[0x6]; 9516 9517 u8 clr[0x1]; 9518 u8 reserved_at_21[0x1f]; 9519 9520 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9521 }; 9522 9523 struct mlx5_ifc_ppad_reg_bits { 9524 u8 reserved_at_0[0x3]; 9525 u8 single_mac[0x1]; 9526 u8 reserved_at_4[0x4]; 9527 u8 local_port[0x8]; 9528 u8 mac_47_32[0x10]; 9529 9530 u8 mac_31_0[0x20]; 9531 9532 u8 reserved_at_40[0x40]; 9533 }; 9534 9535 struct mlx5_ifc_pmtu_reg_bits { 9536 u8 reserved_at_0[0x8]; 9537 u8 local_port[0x8]; 9538 u8 reserved_at_10[0x10]; 9539 9540 u8 max_mtu[0x10]; 9541 u8 reserved_at_30[0x10]; 9542 9543 u8 admin_mtu[0x10]; 9544 u8 reserved_at_50[0x10]; 9545 9546 u8 oper_mtu[0x10]; 9547 u8 reserved_at_70[0x10]; 9548 }; 9549 9550 struct mlx5_ifc_pmpr_reg_bits { 9551 u8 reserved_at_0[0x8]; 9552 u8 module[0x8]; 9553 u8 reserved_at_10[0x10]; 9554 9555 u8 reserved_at_20[0x18]; 9556 u8 attenuation_5g[0x8]; 9557 9558 u8 reserved_at_40[0x18]; 9559 u8 attenuation_7g[0x8]; 9560 9561 u8 reserved_at_60[0x18]; 9562 u8 attenuation_12g[0x8]; 9563 }; 9564 9565 struct mlx5_ifc_pmpe_reg_bits { 9566 u8 reserved_at_0[0x8]; 9567 u8 module[0x8]; 9568 u8 reserved_at_10[0xc]; 9569 u8 module_status[0x4]; 9570 9571 u8 reserved_at_20[0x60]; 9572 }; 9573 9574 struct mlx5_ifc_pmpc_reg_bits { 9575 u8 module_state_updated[32][0x8]; 9576 }; 9577 9578 struct mlx5_ifc_pmlpn_reg_bits { 9579 u8 reserved_at_0[0x4]; 9580 u8 mlpn_status[0x4]; 9581 u8 local_port[0x8]; 9582 u8 reserved_at_10[0x10]; 9583 9584 u8 e[0x1]; 9585 u8 reserved_at_21[0x1f]; 9586 }; 9587 9588 struct mlx5_ifc_pmlp_reg_bits { 9589 u8 rxtx[0x1]; 9590 u8 reserved_at_1[0x7]; 9591 u8 local_port[0x8]; 9592 u8 reserved_at_10[0x8]; 9593 u8 width[0x8]; 9594 9595 u8 lane0_module_mapping[0x20]; 9596 9597 u8 lane1_module_mapping[0x20]; 9598 9599 u8 lane2_module_mapping[0x20]; 9600 9601 u8 lane3_module_mapping[0x20]; 9602 9603 u8 reserved_at_a0[0x160]; 9604 }; 9605 9606 struct mlx5_ifc_pmaos_reg_bits { 9607 u8 reserved_at_0[0x8]; 9608 u8 module[0x8]; 9609 u8 reserved_at_10[0x4]; 9610 u8 admin_status[0x4]; 9611 u8 reserved_at_18[0x4]; 9612 u8 oper_status[0x4]; 9613 9614 u8 ase[0x1]; 9615 u8 ee[0x1]; 9616 u8 reserved_at_22[0x1c]; 9617 u8 e[0x2]; 9618 9619 u8 reserved_at_40[0x40]; 9620 }; 9621 9622 struct mlx5_ifc_plpc_reg_bits { 9623 u8 reserved_at_0[0x4]; 9624 u8 profile_id[0xc]; 9625 u8 reserved_at_10[0x4]; 9626 u8 proto_mask[0x4]; 9627 u8 reserved_at_18[0x8]; 9628 9629 u8 reserved_at_20[0x10]; 9630 u8 lane_speed[0x10]; 9631 9632 u8 reserved_at_40[0x17]; 9633 u8 lpbf[0x1]; 9634 u8 fec_mode_policy[0x8]; 9635 9636 u8 retransmission_capability[0x8]; 9637 u8 fec_mode_capability[0x18]; 9638 9639 u8 retransmission_support_admin[0x8]; 9640 u8 fec_mode_support_admin[0x18]; 9641 9642 u8 retransmission_request_admin[0x8]; 9643 u8 fec_mode_request_admin[0x18]; 9644 9645 u8 reserved_at_c0[0x80]; 9646 }; 9647 9648 struct mlx5_ifc_plib_reg_bits { 9649 u8 reserved_at_0[0x8]; 9650 u8 local_port[0x8]; 9651 u8 reserved_at_10[0x8]; 9652 u8 ib_port[0x8]; 9653 9654 u8 reserved_at_20[0x60]; 9655 }; 9656 9657 struct mlx5_ifc_plbf_reg_bits { 9658 u8 reserved_at_0[0x8]; 9659 u8 local_port[0x8]; 9660 u8 reserved_at_10[0xd]; 9661 u8 lbf_mode[0x3]; 9662 9663 u8 reserved_at_20[0x20]; 9664 }; 9665 9666 struct mlx5_ifc_pipg_reg_bits { 9667 u8 reserved_at_0[0x8]; 9668 u8 local_port[0x8]; 9669 u8 reserved_at_10[0x10]; 9670 9671 u8 dic[0x1]; 9672 u8 reserved_at_21[0x19]; 9673 u8 ipg[0x4]; 9674 u8 reserved_at_3e[0x2]; 9675 }; 9676 9677 struct mlx5_ifc_pifr_reg_bits { 9678 u8 reserved_at_0[0x8]; 9679 u8 local_port[0x8]; 9680 u8 reserved_at_10[0x10]; 9681 9682 u8 reserved_at_20[0xe0]; 9683 9684 u8 port_filter[8][0x20]; 9685 9686 u8 port_filter_update_en[8][0x20]; 9687 }; 9688 9689 struct mlx5_ifc_pfcc_reg_bits { 9690 u8 reserved_at_0[0x8]; 9691 u8 local_port[0x8]; 9692 u8 reserved_at_10[0xb]; 9693 u8 ppan_mask_n[0x1]; 9694 u8 minor_stall_mask[0x1]; 9695 u8 critical_stall_mask[0x1]; 9696 u8 reserved_at_1e[0x2]; 9697 9698 u8 ppan[0x4]; 9699 u8 reserved_at_24[0x4]; 9700 u8 prio_mask_tx[0x8]; 9701 u8 reserved_at_30[0x8]; 9702 u8 prio_mask_rx[0x8]; 9703 9704 u8 pptx[0x1]; 9705 u8 aptx[0x1]; 9706 u8 pptx_mask_n[0x1]; 9707 u8 reserved_at_43[0x5]; 9708 u8 pfctx[0x8]; 9709 u8 reserved_at_50[0x10]; 9710 9711 u8 pprx[0x1]; 9712 u8 aprx[0x1]; 9713 u8 pprx_mask_n[0x1]; 9714 u8 reserved_at_63[0x5]; 9715 u8 pfcrx[0x8]; 9716 u8 reserved_at_70[0x10]; 9717 9718 u8 device_stall_minor_watermark[0x10]; 9719 u8 device_stall_critical_watermark[0x10]; 9720 9721 u8 reserved_at_a0[0x60]; 9722 }; 9723 9724 struct mlx5_ifc_pelc_reg_bits { 9725 u8 op[0x4]; 9726 u8 reserved_at_4[0x4]; 9727 u8 local_port[0x8]; 9728 u8 reserved_at_10[0x10]; 9729 9730 u8 op_admin[0x8]; 9731 u8 op_capability[0x8]; 9732 u8 op_request[0x8]; 9733 u8 op_active[0x8]; 9734 9735 u8 admin[0x40]; 9736 9737 u8 capability[0x40]; 9738 9739 u8 request[0x40]; 9740 9741 u8 active[0x40]; 9742 9743 u8 reserved_at_140[0x80]; 9744 }; 9745 9746 struct mlx5_ifc_peir_reg_bits { 9747 u8 reserved_at_0[0x8]; 9748 u8 local_port[0x8]; 9749 u8 reserved_at_10[0x10]; 9750 9751 u8 reserved_at_20[0xc]; 9752 u8 error_count[0x4]; 9753 u8 reserved_at_30[0x10]; 9754 9755 u8 reserved_at_40[0xc]; 9756 u8 lane[0x4]; 9757 u8 reserved_at_50[0x8]; 9758 u8 error_type[0x8]; 9759 }; 9760 9761 struct mlx5_ifc_mpegc_reg_bits { 9762 u8 reserved_at_0[0x30]; 9763 u8 field_select[0x10]; 9764 9765 u8 tx_overflow_sense[0x1]; 9766 u8 mark_cqe[0x1]; 9767 u8 mark_cnp[0x1]; 9768 u8 reserved_at_43[0x1b]; 9769 u8 tx_lossy_overflow_oper[0x2]; 9770 9771 u8 reserved_at_60[0x100]; 9772 }; 9773 9774 enum { 9775 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9776 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9777 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9778 }; 9779 9780 struct mlx5_ifc_mtutc_reg_bits { 9781 u8 reserved_at_0[0x1c]; 9782 u8 operation[0x4]; 9783 9784 u8 freq_adjustment[0x20]; 9785 9786 u8 reserved_at_40[0x40]; 9787 9788 u8 utc_sec[0x20]; 9789 9790 u8 reserved_at_a0[0x2]; 9791 u8 utc_nsec[0x1e]; 9792 9793 u8 time_adjustment[0x20]; 9794 }; 9795 9796 struct mlx5_ifc_pcam_enhanced_features_bits { 9797 u8 reserved_at_0[0x68]; 9798 u8 fec_50G_per_lane_in_pplm[0x1]; 9799 u8 reserved_at_69[0x4]; 9800 u8 rx_icrc_encapsulated_counter[0x1]; 9801 u8 reserved_at_6e[0x4]; 9802 u8 ptys_extended_ethernet[0x1]; 9803 u8 reserved_at_73[0x3]; 9804 u8 pfcc_mask[0x1]; 9805 u8 reserved_at_77[0x3]; 9806 u8 per_lane_error_counters[0x1]; 9807 u8 rx_buffer_fullness_counters[0x1]; 9808 u8 ptys_connector_type[0x1]; 9809 u8 reserved_at_7d[0x1]; 9810 u8 ppcnt_discard_group[0x1]; 9811 u8 ppcnt_statistical_group[0x1]; 9812 }; 9813 9814 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9815 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9816 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9817 9818 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9819 u8 pplm[0x1]; 9820 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9821 9822 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9823 u8 pbmc[0x1]; 9824 u8 pptb[0x1]; 9825 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9826 u8 ppcnt[0x1]; 9827 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9828 }; 9829 9830 struct mlx5_ifc_pcam_reg_bits { 9831 u8 reserved_at_0[0x8]; 9832 u8 feature_group[0x8]; 9833 u8 reserved_at_10[0x8]; 9834 u8 access_reg_group[0x8]; 9835 9836 u8 reserved_at_20[0x20]; 9837 9838 union { 9839 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9840 u8 reserved_at_0[0x80]; 9841 } port_access_reg_cap_mask; 9842 9843 u8 reserved_at_c0[0x80]; 9844 9845 union { 9846 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9847 u8 reserved_at_0[0x80]; 9848 } feature_cap_mask; 9849 9850 u8 reserved_at_1c0[0xc0]; 9851 }; 9852 9853 struct mlx5_ifc_mcam_enhanced_features_bits { 9854 u8 reserved_at_0[0x5d]; 9855 u8 mcia_32dwords[0x1]; 9856 u8 out_pulse_duration_ns[0x1]; 9857 u8 npps_period[0x1]; 9858 u8 reserved_at_60[0xa]; 9859 u8 reset_state[0x1]; 9860 u8 ptpcyc2realtime_modify[0x1]; 9861 u8 reserved_at_6c[0x2]; 9862 u8 pci_status_and_power[0x1]; 9863 u8 reserved_at_6f[0x5]; 9864 u8 mark_tx_action_cnp[0x1]; 9865 u8 mark_tx_action_cqe[0x1]; 9866 u8 dynamic_tx_overflow[0x1]; 9867 u8 reserved_at_77[0x4]; 9868 u8 pcie_outbound_stalled[0x1]; 9869 u8 tx_overflow_buffer_pkt[0x1]; 9870 u8 mtpps_enh_out_per_adj[0x1]; 9871 u8 mtpps_fs[0x1]; 9872 u8 pcie_performance_group[0x1]; 9873 }; 9874 9875 struct mlx5_ifc_mcam_access_reg_bits { 9876 u8 reserved_at_0[0x1c]; 9877 u8 mcda[0x1]; 9878 u8 mcc[0x1]; 9879 u8 mcqi[0x1]; 9880 u8 mcqs[0x1]; 9881 9882 u8 regs_95_to_87[0x9]; 9883 u8 mpegc[0x1]; 9884 u8 mtutc[0x1]; 9885 u8 regs_84_to_68[0x11]; 9886 u8 tracer_registers[0x4]; 9887 9888 u8 regs_63_to_46[0x12]; 9889 u8 mrtc[0x1]; 9890 u8 regs_44_to_32[0xd]; 9891 9892 u8 regs_31_to_0[0x20]; 9893 }; 9894 9895 struct mlx5_ifc_mcam_access_reg_bits1 { 9896 u8 regs_127_to_96[0x20]; 9897 9898 u8 regs_95_to_64[0x20]; 9899 9900 u8 regs_63_to_32[0x20]; 9901 9902 u8 regs_31_to_0[0x20]; 9903 }; 9904 9905 struct mlx5_ifc_mcam_access_reg_bits2 { 9906 u8 regs_127_to_99[0x1d]; 9907 u8 mirc[0x1]; 9908 u8 regs_97_to_96[0x2]; 9909 9910 u8 regs_95_to_64[0x20]; 9911 9912 u8 regs_63_to_32[0x20]; 9913 9914 u8 regs_31_to_0[0x20]; 9915 }; 9916 9917 struct mlx5_ifc_mcam_reg_bits { 9918 u8 reserved_at_0[0x8]; 9919 u8 feature_group[0x8]; 9920 u8 reserved_at_10[0x8]; 9921 u8 access_reg_group[0x8]; 9922 9923 u8 reserved_at_20[0x20]; 9924 9925 union { 9926 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9927 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9928 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9929 u8 reserved_at_0[0x80]; 9930 } mng_access_reg_cap_mask; 9931 9932 u8 reserved_at_c0[0x80]; 9933 9934 union { 9935 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9936 u8 reserved_at_0[0x80]; 9937 } mng_feature_cap_mask; 9938 9939 u8 reserved_at_1c0[0x80]; 9940 }; 9941 9942 struct mlx5_ifc_qcam_access_reg_cap_mask { 9943 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9944 u8 qpdpm[0x1]; 9945 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9946 u8 qdpm[0x1]; 9947 u8 qpts[0x1]; 9948 u8 qcap[0x1]; 9949 u8 qcam_access_reg_cap_mask_0[0x1]; 9950 }; 9951 9952 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9953 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9954 u8 qpts_trust_both[0x1]; 9955 }; 9956 9957 struct mlx5_ifc_qcam_reg_bits { 9958 u8 reserved_at_0[0x8]; 9959 u8 feature_group[0x8]; 9960 u8 reserved_at_10[0x8]; 9961 u8 access_reg_group[0x8]; 9962 u8 reserved_at_20[0x20]; 9963 9964 union { 9965 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9966 u8 reserved_at_0[0x80]; 9967 } qos_access_reg_cap_mask; 9968 9969 u8 reserved_at_c0[0x80]; 9970 9971 union { 9972 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9973 u8 reserved_at_0[0x80]; 9974 } qos_feature_cap_mask; 9975 9976 u8 reserved_at_1c0[0x80]; 9977 }; 9978 9979 struct mlx5_ifc_core_dump_reg_bits { 9980 u8 reserved_at_0[0x18]; 9981 u8 core_dump_type[0x8]; 9982 9983 u8 reserved_at_20[0x30]; 9984 u8 vhca_id[0x10]; 9985 9986 u8 reserved_at_60[0x8]; 9987 u8 qpn[0x18]; 9988 u8 reserved_at_80[0x180]; 9989 }; 9990 9991 struct mlx5_ifc_pcap_reg_bits { 9992 u8 reserved_at_0[0x8]; 9993 u8 local_port[0x8]; 9994 u8 reserved_at_10[0x10]; 9995 9996 u8 port_capability_mask[4][0x20]; 9997 }; 9998 9999 struct mlx5_ifc_paos_reg_bits { 10000 u8 swid[0x8]; 10001 u8 local_port[0x8]; 10002 u8 reserved_at_10[0x4]; 10003 u8 admin_status[0x4]; 10004 u8 reserved_at_18[0x4]; 10005 u8 oper_status[0x4]; 10006 10007 u8 ase[0x1]; 10008 u8 ee[0x1]; 10009 u8 reserved_at_22[0x1c]; 10010 u8 e[0x2]; 10011 10012 u8 reserved_at_40[0x40]; 10013 }; 10014 10015 struct mlx5_ifc_pamp_reg_bits { 10016 u8 reserved_at_0[0x8]; 10017 u8 opamp_group[0x8]; 10018 u8 reserved_at_10[0xc]; 10019 u8 opamp_group_type[0x4]; 10020 10021 u8 start_index[0x10]; 10022 u8 reserved_at_30[0x4]; 10023 u8 num_of_indices[0xc]; 10024 10025 u8 index_data[18][0x10]; 10026 }; 10027 10028 struct mlx5_ifc_pcmr_reg_bits { 10029 u8 reserved_at_0[0x8]; 10030 u8 local_port[0x8]; 10031 u8 reserved_at_10[0x10]; 10032 10033 u8 entropy_force_cap[0x1]; 10034 u8 entropy_calc_cap[0x1]; 10035 u8 entropy_gre_calc_cap[0x1]; 10036 u8 reserved_at_23[0xf]; 10037 u8 rx_ts_over_crc_cap[0x1]; 10038 u8 reserved_at_33[0xb]; 10039 u8 fcs_cap[0x1]; 10040 u8 reserved_at_3f[0x1]; 10041 10042 u8 entropy_force[0x1]; 10043 u8 entropy_calc[0x1]; 10044 u8 entropy_gre_calc[0x1]; 10045 u8 reserved_at_43[0xf]; 10046 u8 rx_ts_over_crc[0x1]; 10047 u8 reserved_at_53[0xb]; 10048 u8 fcs_chk[0x1]; 10049 u8 reserved_at_5f[0x1]; 10050 }; 10051 10052 struct mlx5_ifc_lane_2_module_mapping_bits { 10053 u8 reserved_at_0[0x4]; 10054 u8 rx_lane[0x4]; 10055 u8 reserved_at_8[0x4]; 10056 u8 tx_lane[0x4]; 10057 u8 reserved_at_10[0x8]; 10058 u8 module[0x8]; 10059 }; 10060 10061 struct mlx5_ifc_bufferx_reg_bits { 10062 u8 reserved_at_0[0x6]; 10063 u8 lossy[0x1]; 10064 u8 epsb[0x1]; 10065 u8 reserved_at_8[0x8]; 10066 u8 size[0x10]; 10067 10068 u8 xoff_threshold[0x10]; 10069 u8 xon_threshold[0x10]; 10070 }; 10071 10072 struct mlx5_ifc_set_node_in_bits { 10073 u8 node_description[64][0x8]; 10074 }; 10075 10076 struct mlx5_ifc_register_power_settings_bits { 10077 u8 reserved_at_0[0x18]; 10078 u8 power_settings_level[0x8]; 10079 10080 u8 reserved_at_20[0x60]; 10081 }; 10082 10083 struct mlx5_ifc_register_host_endianness_bits { 10084 u8 he[0x1]; 10085 u8 reserved_at_1[0x1f]; 10086 10087 u8 reserved_at_20[0x60]; 10088 }; 10089 10090 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10091 u8 reserved_at_0[0x20]; 10092 10093 u8 mkey[0x20]; 10094 10095 u8 addressh_63_32[0x20]; 10096 10097 u8 addressl_31_0[0x20]; 10098 }; 10099 10100 struct mlx5_ifc_ud_adrs_vector_bits { 10101 u8 dc_key[0x40]; 10102 10103 u8 ext[0x1]; 10104 u8 reserved_at_41[0x7]; 10105 u8 destination_qp_dct[0x18]; 10106 10107 u8 static_rate[0x4]; 10108 u8 sl_eth_prio[0x4]; 10109 u8 fl[0x1]; 10110 u8 mlid[0x7]; 10111 u8 rlid_udp_sport[0x10]; 10112 10113 u8 reserved_at_80[0x20]; 10114 10115 u8 rmac_47_16[0x20]; 10116 10117 u8 rmac_15_0[0x10]; 10118 u8 tclass[0x8]; 10119 u8 hop_limit[0x8]; 10120 10121 u8 reserved_at_e0[0x1]; 10122 u8 grh[0x1]; 10123 u8 reserved_at_e2[0x2]; 10124 u8 src_addr_index[0x8]; 10125 u8 flow_label[0x14]; 10126 10127 u8 rgid_rip[16][0x8]; 10128 }; 10129 10130 struct mlx5_ifc_pages_req_event_bits { 10131 u8 reserved_at_0[0x10]; 10132 u8 function_id[0x10]; 10133 10134 u8 num_pages[0x20]; 10135 10136 u8 reserved_at_40[0xa0]; 10137 }; 10138 10139 struct mlx5_ifc_eqe_bits { 10140 u8 reserved_at_0[0x8]; 10141 u8 event_type[0x8]; 10142 u8 reserved_at_10[0x8]; 10143 u8 event_sub_type[0x8]; 10144 10145 u8 reserved_at_20[0xe0]; 10146 10147 union mlx5_ifc_event_auto_bits event_data; 10148 10149 u8 reserved_at_1e0[0x10]; 10150 u8 signature[0x8]; 10151 u8 reserved_at_1f8[0x7]; 10152 u8 owner[0x1]; 10153 }; 10154 10155 enum { 10156 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10157 }; 10158 10159 struct mlx5_ifc_cmd_queue_entry_bits { 10160 u8 type[0x8]; 10161 u8 reserved_at_8[0x18]; 10162 10163 u8 input_length[0x20]; 10164 10165 u8 input_mailbox_pointer_63_32[0x20]; 10166 10167 u8 input_mailbox_pointer_31_9[0x17]; 10168 u8 reserved_at_77[0x9]; 10169 10170 u8 command_input_inline_data[16][0x8]; 10171 10172 u8 command_output_inline_data[16][0x8]; 10173 10174 u8 output_mailbox_pointer_63_32[0x20]; 10175 10176 u8 output_mailbox_pointer_31_9[0x17]; 10177 u8 reserved_at_1b7[0x9]; 10178 10179 u8 output_length[0x20]; 10180 10181 u8 token[0x8]; 10182 u8 signature[0x8]; 10183 u8 reserved_at_1f0[0x8]; 10184 u8 status[0x7]; 10185 u8 ownership[0x1]; 10186 }; 10187 10188 struct mlx5_ifc_cmd_out_bits { 10189 u8 status[0x8]; 10190 u8 reserved_at_8[0x18]; 10191 10192 u8 syndrome[0x20]; 10193 10194 u8 command_output[0x20]; 10195 }; 10196 10197 struct mlx5_ifc_cmd_in_bits { 10198 u8 opcode[0x10]; 10199 u8 reserved_at_10[0x10]; 10200 10201 u8 reserved_at_20[0x10]; 10202 u8 op_mod[0x10]; 10203 10204 u8 command[][0x20]; 10205 }; 10206 10207 struct mlx5_ifc_cmd_if_box_bits { 10208 u8 mailbox_data[512][0x8]; 10209 10210 u8 reserved_at_1000[0x180]; 10211 10212 u8 next_pointer_63_32[0x20]; 10213 10214 u8 next_pointer_31_10[0x16]; 10215 u8 reserved_at_11b6[0xa]; 10216 10217 u8 block_number[0x20]; 10218 10219 u8 reserved_at_11e0[0x8]; 10220 u8 token[0x8]; 10221 u8 ctrl_signature[0x8]; 10222 u8 signature[0x8]; 10223 }; 10224 10225 struct mlx5_ifc_mtt_bits { 10226 u8 ptag_63_32[0x20]; 10227 10228 u8 ptag_31_8[0x18]; 10229 u8 reserved_at_38[0x6]; 10230 u8 wr_en[0x1]; 10231 u8 rd_en[0x1]; 10232 }; 10233 10234 struct mlx5_ifc_query_wol_rol_out_bits { 10235 u8 status[0x8]; 10236 u8 reserved_at_8[0x18]; 10237 10238 u8 syndrome[0x20]; 10239 10240 u8 reserved_at_40[0x10]; 10241 u8 rol_mode[0x8]; 10242 u8 wol_mode[0x8]; 10243 10244 u8 reserved_at_60[0x20]; 10245 }; 10246 10247 struct mlx5_ifc_query_wol_rol_in_bits { 10248 u8 opcode[0x10]; 10249 u8 reserved_at_10[0x10]; 10250 10251 u8 reserved_at_20[0x10]; 10252 u8 op_mod[0x10]; 10253 10254 u8 reserved_at_40[0x40]; 10255 }; 10256 10257 struct mlx5_ifc_set_wol_rol_out_bits { 10258 u8 status[0x8]; 10259 u8 reserved_at_8[0x18]; 10260 10261 u8 syndrome[0x20]; 10262 10263 u8 reserved_at_40[0x40]; 10264 }; 10265 10266 struct mlx5_ifc_set_wol_rol_in_bits { 10267 u8 opcode[0x10]; 10268 u8 reserved_at_10[0x10]; 10269 10270 u8 reserved_at_20[0x10]; 10271 u8 op_mod[0x10]; 10272 10273 u8 rol_mode_valid[0x1]; 10274 u8 wol_mode_valid[0x1]; 10275 u8 reserved_at_42[0xe]; 10276 u8 rol_mode[0x8]; 10277 u8 wol_mode[0x8]; 10278 10279 u8 reserved_at_60[0x20]; 10280 }; 10281 10282 enum { 10283 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10284 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10285 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10286 }; 10287 10288 enum { 10289 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10290 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10291 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10292 }; 10293 10294 enum { 10295 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10296 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10297 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10298 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10299 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10300 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10301 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10302 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10303 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10304 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10305 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10306 }; 10307 10308 struct mlx5_ifc_initial_seg_bits { 10309 u8 fw_rev_minor[0x10]; 10310 u8 fw_rev_major[0x10]; 10311 10312 u8 cmd_interface_rev[0x10]; 10313 u8 fw_rev_subminor[0x10]; 10314 10315 u8 reserved_at_40[0x40]; 10316 10317 u8 cmdq_phy_addr_63_32[0x20]; 10318 10319 u8 cmdq_phy_addr_31_12[0x14]; 10320 u8 reserved_at_b4[0x2]; 10321 u8 nic_interface[0x2]; 10322 u8 log_cmdq_size[0x4]; 10323 u8 log_cmdq_stride[0x4]; 10324 10325 u8 command_doorbell_vector[0x20]; 10326 10327 u8 reserved_at_e0[0xf00]; 10328 10329 u8 initializing[0x1]; 10330 u8 reserved_at_fe1[0x4]; 10331 u8 nic_interface_supported[0x3]; 10332 u8 embedded_cpu[0x1]; 10333 u8 reserved_at_fe9[0x17]; 10334 10335 struct mlx5_ifc_health_buffer_bits health_buffer; 10336 10337 u8 no_dram_nic_offset[0x20]; 10338 10339 u8 reserved_at_1220[0x6e40]; 10340 10341 u8 reserved_at_8060[0x1f]; 10342 u8 clear_int[0x1]; 10343 10344 u8 health_syndrome[0x8]; 10345 u8 health_counter[0x18]; 10346 10347 u8 reserved_at_80a0[0x17fc0]; 10348 }; 10349 10350 struct mlx5_ifc_mtpps_reg_bits { 10351 u8 reserved_at_0[0xc]; 10352 u8 cap_number_of_pps_pins[0x4]; 10353 u8 reserved_at_10[0x4]; 10354 u8 cap_max_num_of_pps_in_pins[0x4]; 10355 u8 reserved_at_18[0x4]; 10356 u8 cap_max_num_of_pps_out_pins[0x4]; 10357 10358 u8 reserved_at_20[0x13]; 10359 u8 cap_log_min_npps_period[0x5]; 10360 u8 reserved_at_38[0x3]; 10361 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10362 10363 u8 reserved_at_40[0x4]; 10364 u8 cap_pin_3_mode[0x4]; 10365 u8 reserved_at_48[0x4]; 10366 u8 cap_pin_2_mode[0x4]; 10367 u8 reserved_at_50[0x4]; 10368 u8 cap_pin_1_mode[0x4]; 10369 u8 reserved_at_58[0x4]; 10370 u8 cap_pin_0_mode[0x4]; 10371 10372 u8 reserved_at_60[0x4]; 10373 u8 cap_pin_7_mode[0x4]; 10374 u8 reserved_at_68[0x4]; 10375 u8 cap_pin_6_mode[0x4]; 10376 u8 reserved_at_70[0x4]; 10377 u8 cap_pin_5_mode[0x4]; 10378 u8 reserved_at_78[0x4]; 10379 u8 cap_pin_4_mode[0x4]; 10380 10381 u8 field_select[0x20]; 10382 u8 reserved_at_a0[0x20]; 10383 10384 u8 npps_period[0x40]; 10385 10386 u8 enable[0x1]; 10387 u8 reserved_at_101[0xb]; 10388 u8 pattern[0x4]; 10389 u8 reserved_at_110[0x4]; 10390 u8 pin_mode[0x4]; 10391 u8 pin[0x8]; 10392 10393 u8 reserved_at_120[0x2]; 10394 u8 out_pulse_duration_ns[0x1e]; 10395 10396 u8 time_stamp[0x40]; 10397 10398 u8 out_pulse_duration[0x10]; 10399 u8 out_periodic_adjustment[0x10]; 10400 u8 enhanced_out_periodic_adjustment[0x20]; 10401 10402 u8 reserved_at_1c0[0x20]; 10403 }; 10404 10405 struct mlx5_ifc_mtppse_reg_bits { 10406 u8 reserved_at_0[0x18]; 10407 u8 pin[0x8]; 10408 u8 event_arm[0x1]; 10409 u8 reserved_at_21[0x1b]; 10410 u8 event_generation_mode[0x4]; 10411 u8 reserved_at_40[0x40]; 10412 }; 10413 10414 struct mlx5_ifc_mcqs_reg_bits { 10415 u8 last_index_flag[0x1]; 10416 u8 reserved_at_1[0x7]; 10417 u8 fw_device[0x8]; 10418 u8 component_index[0x10]; 10419 10420 u8 reserved_at_20[0x10]; 10421 u8 identifier[0x10]; 10422 10423 u8 reserved_at_40[0x17]; 10424 u8 component_status[0x5]; 10425 u8 component_update_state[0x4]; 10426 10427 u8 last_update_state_changer_type[0x4]; 10428 u8 last_update_state_changer_host_id[0x4]; 10429 u8 reserved_at_68[0x18]; 10430 }; 10431 10432 struct mlx5_ifc_mcqi_cap_bits { 10433 u8 supported_info_bitmask[0x20]; 10434 10435 u8 component_size[0x20]; 10436 10437 u8 max_component_size[0x20]; 10438 10439 u8 log_mcda_word_size[0x4]; 10440 u8 reserved_at_64[0xc]; 10441 u8 mcda_max_write_size[0x10]; 10442 10443 u8 rd_en[0x1]; 10444 u8 reserved_at_81[0x1]; 10445 u8 match_chip_id[0x1]; 10446 u8 match_psid[0x1]; 10447 u8 check_user_timestamp[0x1]; 10448 u8 match_base_guid_mac[0x1]; 10449 u8 reserved_at_86[0x1a]; 10450 }; 10451 10452 struct mlx5_ifc_mcqi_version_bits { 10453 u8 reserved_at_0[0x2]; 10454 u8 build_time_valid[0x1]; 10455 u8 user_defined_time_valid[0x1]; 10456 u8 reserved_at_4[0x14]; 10457 u8 version_string_length[0x8]; 10458 10459 u8 version[0x20]; 10460 10461 u8 build_time[0x40]; 10462 10463 u8 user_defined_time[0x40]; 10464 10465 u8 build_tool_version[0x20]; 10466 10467 u8 reserved_at_e0[0x20]; 10468 10469 u8 version_string[92][0x8]; 10470 }; 10471 10472 struct mlx5_ifc_mcqi_activation_method_bits { 10473 u8 pending_server_ac_power_cycle[0x1]; 10474 u8 pending_server_dc_power_cycle[0x1]; 10475 u8 pending_server_reboot[0x1]; 10476 u8 pending_fw_reset[0x1]; 10477 u8 auto_activate[0x1]; 10478 u8 all_hosts_sync[0x1]; 10479 u8 device_hw_reset[0x1]; 10480 u8 reserved_at_7[0x19]; 10481 }; 10482 10483 union mlx5_ifc_mcqi_reg_data_bits { 10484 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10485 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10486 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10487 }; 10488 10489 struct mlx5_ifc_mcqi_reg_bits { 10490 u8 read_pending_component[0x1]; 10491 u8 reserved_at_1[0xf]; 10492 u8 component_index[0x10]; 10493 10494 u8 reserved_at_20[0x20]; 10495 10496 u8 reserved_at_40[0x1b]; 10497 u8 info_type[0x5]; 10498 10499 u8 info_size[0x20]; 10500 10501 u8 offset[0x20]; 10502 10503 u8 reserved_at_a0[0x10]; 10504 u8 data_size[0x10]; 10505 10506 union mlx5_ifc_mcqi_reg_data_bits data[]; 10507 }; 10508 10509 struct mlx5_ifc_mcc_reg_bits { 10510 u8 reserved_at_0[0x4]; 10511 u8 time_elapsed_since_last_cmd[0xc]; 10512 u8 reserved_at_10[0x8]; 10513 u8 instruction[0x8]; 10514 10515 u8 reserved_at_20[0x10]; 10516 u8 component_index[0x10]; 10517 10518 u8 reserved_at_40[0x8]; 10519 u8 update_handle[0x18]; 10520 10521 u8 handle_owner_type[0x4]; 10522 u8 handle_owner_host_id[0x4]; 10523 u8 reserved_at_68[0x1]; 10524 u8 control_progress[0x7]; 10525 u8 error_code[0x8]; 10526 u8 reserved_at_78[0x4]; 10527 u8 control_state[0x4]; 10528 10529 u8 component_size[0x20]; 10530 10531 u8 reserved_at_a0[0x60]; 10532 }; 10533 10534 struct mlx5_ifc_mcda_reg_bits { 10535 u8 reserved_at_0[0x8]; 10536 u8 update_handle[0x18]; 10537 10538 u8 offset[0x20]; 10539 10540 u8 reserved_at_40[0x10]; 10541 u8 size[0x10]; 10542 10543 u8 reserved_at_60[0x20]; 10544 10545 u8 data[][0x20]; 10546 }; 10547 10548 enum { 10549 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10550 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10551 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10552 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10553 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10554 }; 10555 10556 enum { 10557 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10558 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10559 }; 10560 10561 enum { 10562 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10563 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10564 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10565 }; 10566 10567 struct mlx5_ifc_mfrl_reg_bits { 10568 u8 reserved_at_0[0x20]; 10569 10570 u8 reserved_at_20[0x2]; 10571 u8 pci_sync_for_fw_update_start[0x1]; 10572 u8 pci_sync_for_fw_update_resp[0x2]; 10573 u8 rst_type_sel[0x3]; 10574 u8 reserved_at_28[0x4]; 10575 u8 reset_state[0x4]; 10576 u8 reset_type[0x8]; 10577 u8 reset_level[0x8]; 10578 }; 10579 10580 struct mlx5_ifc_mirc_reg_bits { 10581 u8 reserved_at_0[0x18]; 10582 u8 status_code[0x8]; 10583 10584 u8 reserved_at_20[0x20]; 10585 }; 10586 10587 struct mlx5_ifc_pddr_monitor_opcode_bits { 10588 u8 reserved_at_0[0x10]; 10589 u8 monitor_opcode[0x10]; 10590 }; 10591 10592 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10593 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10594 u8 reserved_at_0[0x20]; 10595 }; 10596 10597 enum { 10598 /* Monitor opcodes */ 10599 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10600 }; 10601 10602 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10603 u8 reserved_at_0[0x10]; 10604 u8 group_opcode[0x10]; 10605 10606 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10607 10608 u8 reserved_at_40[0x20]; 10609 10610 u8 status_message[59][0x20]; 10611 }; 10612 10613 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10614 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10615 u8 reserved_at_0[0x7c0]; 10616 }; 10617 10618 enum { 10619 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10620 }; 10621 10622 struct mlx5_ifc_pddr_reg_bits { 10623 u8 reserved_at_0[0x8]; 10624 u8 local_port[0x8]; 10625 u8 pnat[0x2]; 10626 u8 reserved_at_12[0xe]; 10627 10628 u8 reserved_at_20[0x18]; 10629 u8 page_select[0x8]; 10630 10631 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10632 }; 10633 10634 struct mlx5_ifc_mrtc_reg_bits { 10635 u8 time_synced[0x1]; 10636 u8 reserved_at_1[0x1f]; 10637 10638 u8 reserved_at_20[0x20]; 10639 10640 u8 time_h[0x20]; 10641 10642 u8 time_l[0x20]; 10643 }; 10644 10645 union mlx5_ifc_ports_control_registers_document_bits { 10646 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10647 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10648 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10649 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10650 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10651 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10652 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10653 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10654 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10655 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10656 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10657 struct mlx5_ifc_paos_reg_bits paos_reg; 10658 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10659 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10660 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10661 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10662 struct mlx5_ifc_peir_reg_bits peir_reg; 10663 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10664 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10665 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10666 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10667 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10668 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10669 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10670 struct mlx5_ifc_plib_reg_bits plib_reg; 10671 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10672 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10673 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10674 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10675 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10676 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10677 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10678 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10679 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10680 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10681 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10682 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10683 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10684 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10685 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10686 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10687 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10688 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10689 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10690 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10691 struct mlx5_ifc_pude_reg_bits pude_reg; 10692 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10693 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10694 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10695 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10696 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10697 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10698 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10699 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10700 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10701 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10702 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10703 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10704 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10705 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10706 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10707 u8 reserved_at_0[0x60e0]; 10708 }; 10709 10710 union mlx5_ifc_debug_enhancements_document_bits { 10711 struct mlx5_ifc_health_buffer_bits health_buffer; 10712 u8 reserved_at_0[0x200]; 10713 }; 10714 10715 union mlx5_ifc_uplink_pci_interface_document_bits { 10716 struct mlx5_ifc_initial_seg_bits initial_seg; 10717 u8 reserved_at_0[0x20060]; 10718 }; 10719 10720 struct mlx5_ifc_set_flow_table_root_out_bits { 10721 u8 status[0x8]; 10722 u8 reserved_at_8[0x18]; 10723 10724 u8 syndrome[0x20]; 10725 10726 u8 reserved_at_40[0x40]; 10727 }; 10728 10729 struct mlx5_ifc_set_flow_table_root_in_bits { 10730 u8 opcode[0x10]; 10731 u8 reserved_at_10[0x10]; 10732 10733 u8 reserved_at_20[0x10]; 10734 u8 op_mod[0x10]; 10735 10736 u8 other_vport[0x1]; 10737 u8 reserved_at_41[0xf]; 10738 u8 vport_number[0x10]; 10739 10740 u8 reserved_at_60[0x20]; 10741 10742 u8 table_type[0x8]; 10743 u8 reserved_at_88[0x7]; 10744 u8 table_of_other_vport[0x1]; 10745 u8 table_vport_number[0x10]; 10746 10747 u8 reserved_at_a0[0x8]; 10748 u8 table_id[0x18]; 10749 10750 u8 reserved_at_c0[0x8]; 10751 u8 underlay_qpn[0x18]; 10752 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10753 u8 reserved_at_e1[0xf]; 10754 u8 table_eswitch_owner_vhca_id[0x10]; 10755 u8 reserved_at_100[0x100]; 10756 }; 10757 10758 enum { 10759 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10760 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10761 }; 10762 10763 struct mlx5_ifc_modify_flow_table_out_bits { 10764 u8 status[0x8]; 10765 u8 reserved_at_8[0x18]; 10766 10767 u8 syndrome[0x20]; 10768 10769 u8 reserved_at_40[0x40]; 10770 }; 10771 10772 struct mlx5_ifc_modify_flow_table_in_bits { 10773 u8 opcode[0x10]; 10774 u8 reserved_at_10[0x10]; 10775 10776 u8 reserved_at_20[0x10]; 10777 u8 op_mod[0x10]; 10778 10779 u8 other_vport[0x1]; 10780 u8 reserved_at_41[0xf]; 10781 u8 vport_number[0x10]; 10782 10783 u8 reserved_at_60[0x10]; 10784 u8 modify_field_select[0x10]; 10785 10786 u8 table_type[0x8]; 10787 u8 reserved_at_88[0x18]; 10788 10789 u8 reserved_at_a0[0x8]; 10790 u8 table_id[0x18]; 10791 10792 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10793 }; 10794 10795 struct mlx5_ifc_ets_tcn_config_reg_bits { 10796 u8 g[0x1]; 10797 u8 b[0x1]; 10798 u8 r[0x1]; 10799 u8 reserved_at_3[0x9]; 10800 u8 group[0x4]; 10801 u8 reserved_at_10[0x9]; 10802 u8 bw_allocation[0x7]; 10803 10804 u8 reserved_at_20[0xc]; 10805 u8 max_bw_units[0x4]; 10806 u8 reserved_at_30[0x8]; 10807 u8 max_bw_value[0x8]; 10808 }; 10809 10810 struct mlx5_ifc_ets_global_config_reg_bits { 10811 u8 reserved_at_0[0x2]; 10812 u8 r[0x1]; 10813 u8 reserved_at_3[0x1d]; 10814 10815 u8 reserved_at_20[0xc]; 10816 u8 max_bw_units[0x4]; 10817 u8 reserved_at_30[0x8]; 10818 u8 max_bw_value[0x8]; 10819 }; 10820 10821 struct mlx5_ifc_qetc_reg_bits { 10822 u8 reserved_at_0[0x8]; 10823 u8 port_number[0x8]; 10824 u8 reserved_at_10[0x30]; 10825 10826 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10827 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10828 }; 10829 10830 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10831 u8 e[0x1]; 10832 u8 reserved_at_01[0x0b]; 10833 u8 prio[0x04]; 10834 }; 10835 10836 struct mlx5_ifc_qpdpm_reg_bits { 10837 u8 reserved_at_0[0x8]; 10838 u8 local_port[0x8]; 10839 u8 reserved_at_10[0x10]; 10840 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10841 }; 10842 10843 struct mlx5_ifc_qpts_reg_bits { 10844 u8 reserved_at_0[0x8]; 10845 u8 local_port[0x8]; 10846 u8 reserved_at_10[0x2d]; 10847 u8 trust_state[0x3]; 10848 }; 10849 10850 struct mlx5_ifc_pptb_reg_bits { 10851 u8 reserved_at_0[0x2]; 10852 u8 mm[0x2]; 10853 u8 reserved_at_4[0x4]; 10854 u8 local_port[0x8]; 10855 u8 reserved_at_10[0x6]; 10856 u8 cm[0x1]; 10857 u8 um[0x1]; 10858 u8 pm[0x8]; 10859 10860 u8 prio_x_buff[0x20]; 10861 10862 u8 pm_msb[0x8]; 10863 u8 reserved_at_48[0x10]; 10864 u8 ctrl_buff[0x4]; 10865 u8 untagged_buff[0x4]; 10866 }; 10867 10868 struct mlx5_ifc_sbcam_reg_bits { 10869 u8 reserved_at_0[0x8]; 10870 u8 feature_group[0x8]; 10871 u8 reserved_at_10[0x8]; 10872 u8 access_reg_group[0x8]; 10873 10874 u8 reserved_at_20[0x20]; 10875 10876 u8 sb_access_reg_cap_mask[4][0x20]; 10877 10878 u8 reserved_at_c0[0x80]; 10879 10880 u8 sb_feature_cap_mask[4][0x20]; 10881 10882 u8 reserved_at_1c0[0x40]; 10883 10884 u8 cap_total_buffer_size[0x20]; 10885 10886 u8 cap_cell_size[0x10]; 10887 u8 cap_max_pg_buffers[0x8]; 10888 u8 cap_num_pool_supported[0x8]; 10889 10890 u8 reserved_at_240[0x8]; 10891 u8 cap_sbsr_stat_size[0x8]; 10892 u8 cap_max_tclass_data[0x8]; 10893 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10894 }; 10895 10896 struct mlx5_ifc_pbmc_reg_bits { 10897 u8 reserved_at_0[0x8]; 10898 u8 local_port[0x8]; 10899 u8 reserved_at_10[0x10]; 10900 10901 u8 xoff_timer_value[0x10]; 10902 u8 xoff_refresh[0x10]; 10903 10904 u8 reserved_at_40[0x9]; 10905 u8 fullness_threshold[0x7]; 10906 u8 port_buffer_size[0x10]; 10907 10908 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10909 10910 u8 reserved_at_2e0[0x80]; 10911 }; 10912 10913 struct mlx5_ifc_qtct_reg_bits { 10914 u8 reserved_at_0[0x8]; 10915 u8 port_number[0x8]; 10916 u8 reserved_at_10[0xd]; 10917 u8 prio[0x3]; 10918 10919 u8 reserved_at_20[0x1d]; 10920 u8 tclass[0x3]; 10921 }; 10922 10923 struct mlx5_ifc_mcia_reg_bits { 10924 u8 l[0x1]; 10925 u8 reserved_at_1[0x7]; 10926 u8 module[0x8]; 10927 u8 reserved_at_10[0x8]; 10928 u8 status[0x8]; 10929 10930 u8 i2c_device_address[0x8]; 10931 u8 page_number[0x8]; 10932 u8 device_address[0x10]; 10933 10934 u8 reserved_at_40[0x10]; 10935 u8 size[0x10]; 10936 10937 u8 reserved_at_60[0x20]; 10938 10939 u8 dword_0[0x20]; 10940 u8 dword_1[0x20]; 10941 u8 dword_2[0x20]; 10942 u8 dword_3[0x20]; 10943 u8 dword_4[0x20]; 10944 u8 dword_5[0x20]; 10945 u8 dword_6[0x20]; 10946 u8 dword_7[0x20]; 10947 u8 dword_8[0x20]; 10948 u8 dword_9[0x20]; 10949 u8 dword_10[0x20]; 10950 u8 dword_11[0x20]; 10951 }; 10952 10953 struct mlx5_ifc_dcbx_param_bits { 10954 u8 dcbx_cee_cap[0x1]; 10955 u8 dcbx_ieee_cap[0x1]; 10956 u8 dcbx_standby_cap[0x1]; 10957 u8 reserved_at_3[0x5]; 10958 u8 port_number[0x8]; 10959 u8 reserved_at_10[0xa]; 10960 u8 max_application_table_size[6]; 10961 u8 reserved_at_20[0x15]; 10962 u8 version_oper[0x3]; 10963 u8 reserved_at_38[5]; 10964 u8 version_admin[0x3]; 10965 u8 willing_admin[0x1]; 10966 u8 reserved_at_41[0x3]; 10967 u8 pfc_cap_oper[0x4]; 10968 u8 reserved_at_48[0x4]; 10969 u8 pfc_cap_admin[0x4]; 10970 u8 reserved_at_50[0x4]; 10971 u8 num_of_tc_oper[0x4]; 10972 u8 reserved_at_58[0x4]; 10973 u8 num_of_tc_admin[0x4]; 10974 u8 remote_willing[0x1]; 10975 u8 reserved_at_61[3]; 10976 u8 remote_pfc_cap[4]; 10977 u8 reserved_at_68[0x14]; 10978 u8 remote_num_of_tc[0x4]; 10979 u8 reserved_at_80[0x18]; 10980 u8 error[0x8]; 10981 u8 reserved_at_a0[0x160]; 10982 }; 10983 10984 enum { 10985 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10986 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10987 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10988 }; 10989 10990 struct mlx5_ifc_lagc_bits { 10991 u8 fdb_selection_mode[0x1]; 10992 u8 reserved_at_1[0x14]; 10993 u8 port_select_mode[0x3]; 10994 u8 reserved_at_18[0x5]; 10995 u8 lag_state[0x3]; 10996 10997 u8 reserved_at_20[0xc]; 10998 u8 active_port[0x4]; 10999 u8 reserved_at_30[0x4]; 11000 u8 tx_remap_affinity_2[0x4]; 11001 u8 reserved_at_38[0x4]; 11002 u8 tx_remap_affinity_1[0x4]; 11003 }; 11004 11005 struct mlx5_ifc_create_lag_out_bits { 11006 u8 status[0x8]; 11007 u8 reserved_at_8[0x18]; 11008 11009 u8 syndrome[0x20]; 11010 11011 u8 reserved_at_40[0x40]; 11012 }; 11013 11014 struct mlx5_ifc_create_lag_in_bits { 11015 u8 opcode[0x10]; 11016 u8 reserved_at_10[0x10]; 11017 11018 u8 reserved_at_20[0x10]; 11019 u8 op_mod[0x10]; 11020 11021 struct mlx5_ifc_lagc_bits ctx; 11022 }; 11023 11024 struct mlx5_ifc_modify_lag_out_bits { 11025 u8 status[0x8]; 11026 u8 reserved_at_8[0x18]; 11027 11028 u8 syndrome[0x20]; 11029 11030 u8 reserved_at_40[0x40]; 11031 }; 11032 11033 struct mlx5_ifc_modify_lag_in_bits { 11034 u8 opcode[0x10]; 11035 u8 reserved_at_10[0x10]; 11036 11037 u8 reserved_at_20[0x10]; 11038 u8 op_mod[0x10]; 11039 11040 u8 reserved_at_40[0x20]; 11041 u8 field_select[0x20]; 11042 11043 struct mlx5_ifc_lagc_bits ctx; 11044 }; 11045 11046 struct mlx5_ifc_query_lag_out_bits { 11047 u8 status[0x8]; 11048 u8 reserved_at_8[0x18]; 11049 11050 u8 syndrome[0x20]; 11051 11052 struct mlx5_ifc_lagc_bits ctx; 11053 }; 11054 11055 struct mlx5_ifc_query_lag_in_bits { 11056 u8 opcode[0x10]; 11057 u8 reserved_at_10[0x10]; 11058 11059 u8 reserved_at_20[0x10]; 11060 u8 op_mod[0x10]; 11061 11062 u8 reserved_at_40[0x40]; 11063 }; 11064 11065 struct mlx5_ifc_destroy_lag_out_bits { 11066 u8 status[0x8]; 11067 u8 reserved_at_8[0x18]; 11068 11069 u8 syndrome[0x20]; 11070 11071 u8 reserved_at_40[0x40]; 11072 }; 11073 11074 struct mlx5_ifc_destroy_lag_in_bits { 11075 u8 opcode[0x10]; 11076 u8 reserved_at_10[0x10]; 11077 11078 u8 reserved_at_20[0x10]; 11079 u8 op_mod[0x10]; 11080 11081 u8 reserved_at_40[0x40]; 11082 }; 11083 11084 struct mlx5_ifc_create_vport_lag_out_bits { 11085 u8 status[0x8]; 11086 u8 reserved_at_8[0x18]; 11087 11088 u8 syndrome[0x20]; 11089 11090 u8 reserved_at_40[0x40]; 11091 }; 11092 11093 struct mlx5_ifc_create_vport_lag_in_bits { 11094 u8 opcode[0x10]; 11095 u8 reserved_at_10[0x10]; 11096 11097 u8 reserved_at_20[0x10]; 11098 u8 op_mod[0x10]; 11099 11100 u8 reserved_at_40[0x40]; 11101 }; 11102 11103 struct mlx5_ifc_destroy_vport_lag_out_bits { 11104 u8 status[0x8]; 11105 u8 reserved_at_8[0x18]; 11106 11107 u8 syndrome[0x20]; 11108 11109 u8 reserved_at_40[0x40]; 11110 }; 11111 11112 struct mlx5_ifc_destroy_vport_lag_in_bits { 11113 u8 opcode[0x10]; 11114 u8 reserved_at_10[0x10]; 11115 11116 u8 reserved_at_20[0x10]; 11117 u8 op_mod[0x10]; 11118 11119 u8 reserved_at_40[0x40]; 11120 }; 11121 11122 enum { 11123 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11124 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11125 }; 11126 11127 struct mlx5_ifc_modify_memic_in_bits { 11128 u8 opcode[0x10]; 11129 u8 uid[0x10]; 11130 11131 u8 reserved_at_20[0x10]; 11132 u8 op_mod[0x10]; 11133 11134 u8 reserved_at_40[0x20]; 11135 11136 u8 reserved_at_60[0x18]; 11137 u8 memic_operation_type[0x8]; 11138 11139 u8 memic_start_addr[0x40]; 11140 11141 u8 reserved_at_c0[0x140]; 11142 }; 11143 11144 struct mlx5_ifc_modify_memic_out_bits { 11145 u8 status[0x8]; 11146 u8 reserved_at_8[0x18]; 11147 11148 u8 syndrome[0x20]; 11149 11150 u8 reserved_at_40[0x40]; 11151 11152 u8 memic_operation_addr[0x40]; 11153 11154 u8 reserved_at_c0[0x140]; 11155 }; 11156 11157 struct mlx5_ifc_alloc_memic_in_bits { 11158 u8 opcode[0x10]; 11159 u8 reserved_at_10[0x10]; 11160 11161 u8 reserved_at_20[0x10]; 11162 u8 op_mod[0x10]; 11163 11164 u8 reserved_at_30[0x20]; 11165 11166 u8 reserved_at_40[0x18]; 11167 u8 log_memic_addr_alignment[0x8]; 11168 11169 u8 range_start_addr[0x40]; 11170 11171 u8 range_size[0x20]; 11172 11173 u8 memic_size[0x20]; 11174 }; 11175 11176 struct mlx5_ifc_alloc_memic_out_bits { 11177 u8 status[0x8]; 11178 u8 reserved_at_8[0x18]; 11179 11180 u8 syndrome[0x20]; 11181 11182 u8 memic_start_addr[0x40]; 11183 }; 11184 11185 struct mlx5_ifc_dealloc_memic_in_bits { 11186 u8 opcode[0x10]; 11187 u8 reserved_at_10[0x10]; 11188 11189 u8 reserved_at_20[0x10]; 11190 u8 op_mod[0x10]; 11191 11192 u8 reserved_at_40[0x40]; 11193 11194 u8 memic_start_addr[0x40]; 11195 11196 u8 memic_size[0x20]; 11197 11198 u8 reserved_at_e0[0x20]; 11199 }; 11200 11201 struct mlx5_ifc_dealloc_memic_out_bits { 11202 u8 status[0x8]; 11203 u8 reserved_at_8[0x18]; 11204 11205 u8 syndrome[0x20]; 11206 11207 u8 reserved_at_40[0x40]; 11208 }; 11209 11210 struct mlx5_ifc_umem_bits { 11211 u8 reserved_at_0[0x80]; 11212 11213 u8 reserved_at_80[0x1b]; 11214 u8 log_page_size[0x5]; 11215 11216 u8 page_offset[0x20]; 11217 11218 u8 num_of_mtt[0x40]; 11219 11220 struct mlx5_ifc_mtt_bits mtt[]; 11221 }; 11222 11223 struct mlx5_ifc_uctx_bits { 11224 u8 cap[0x20]; 11225 11226 u8 reserved_at_20[0x160]; 11227 }; 11228 11229 struct mlx5_ifc_sw_icm_bits { 11230 u8 modify_field_select[0x40]; 11231 11232 u8 reserved_at_40[0x18]; 11233 u8 log_sw_icm_size[0x8]; 11234 11235 u8 reserved_at_60[0x20]; 11236 11237 u8 sw_icm_start_addr[0x40]; 11238 11239 u8 reserved_at_c0[0x140]; 11240 }; 11241 11242 struct mlx5_ifc_geneve_tlv_option_bits { 11243 u8 modify_field_select[0x40]; 11244 11245 u8 reserved_at_40[0x18]; 11246 u8 geneve_option_fte_index[0x8]; 11247 11248 u8 option_class[0x10]; 11249 u8 option_type[0x8]; 11250 u8 reserved_at_78[0x3]; 11251 u8 option_data_length[0x5]; 11252 11253 u8 reserved_at_80[0x180]; 11254 }; 11255 11256 struct mlx5_ifc_create_umem_in_bits { 11257 u8 opcode[0x10]; 11258 u8 uid[0x10]; 11259 11260 u8 reserved_at_20[0x10]; 11261 u8 op_mod[0x10]; 11262 11263 u8 reserved_at_40[0x40]; 11264 11265 struct mlx5_ifc_umem_bits umem; 11266 }; 11267 11268 struct mlx5_ifc_create_umem_out_bits { 11269 u8 status[0x8]; 11270 u8 reserved_at_8[0x18]; 11271 11272 u8 syndrome[0x20]; 11273 11274 u8 reserved_at_40[0x8]; 11275 u8 umem_id[0x18]; 11276 11277 u8 reserved_at_60[0x20]; 11278 }; 11279 11280 struct mlx5_ifc_destroy_umem_in_bits { 11281 u8 opcode[0x10]; 11282 u8 uid[0x10]; 11283 11284 u8 reserved_at_20[0x10]; 11285 u8 op_mod[0x10]; 11286 11287 u8 reserved_at_40[0x8]; 11288 u8 umem_id[0x18]; 11289 11290 u8 reserved_at_60[0x20]; 11291 }; 11292 11293 struct mlx5_ifc_destroy_umem_out_bits { 11294 u8 status[0x8]; 11295 u8 reserved_at_8[0x18]; 11296 11297 u8 syndrome[0x20]; 11298 11299 u8 reserved_at_40[0x40]; 11300 }; 11301 11302 struct mlx5_ifc_create_uctx_in_bits { 11303 u8 opcode[0x10]; 11304 u8 reserved_at_10[0x10]; 11305 11306 u8 reserved_at_20[0x10]; 11307 u8 op_mod[0x10]; 11308 11309 u8 reserved_at_40[0x40]; 11310 11311 struct mlx5_ifc_uctx_bits uctx; 11312 }; 11313 11314 struct mlx5_ifc_create_uctx_out_bits { 11315 u8 status[0x8]; 11316 u8 reserved_at_8[0x18]; 11317 11318 u8 syndrome[0x20]; 11319 11320 u8 reserved_at_40[0x10]; 11321 u8 uid[0x10]; 11322 11323 u8 reserved_at_60[0x20]; 11324 }; 11325 11326 struct mlx5_ifc_destroy_uctx_in_bits { 11327 u8 opcode[0x10]; 11328 u8 reserved_at_10[0x10]; 11329 11330 u8 reserved_at_20[0x10]; 11331 u8 op_mod[0x10]; 11332 11333 u8 reserved_at_40[0x10]; 11334 u8 uid[0x10]; 11335 11336 u8 reserved_at_60[0x20]; 11337 }; 11338 11339 struct mlx5_ifc_destroy_uctx_out_bits { 11340 u8 status[0x8]; 11341 u8 reserved_at_8[0x18]; 11342 11343 u8 syndrome[0x20]; 11344 11345 u8 reserved_at_40[0x40]; 11346 }; 11347 11348 struct mlx5_ifc_create_sw_icm_in_bits { 11349 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11350 struct mlx5_ifc_sw_icm_bits sw_icm; 11351 }; 11352 11353 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11354 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11355 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11356 }; 11357 11358 struct mlx5_ifc_mtrc_string_db_param_bits { 11359 u8 string_db_base_address[0x20]; 11360 11361 u8 reserved_at_20[0x8]; 11362 u8 string_db_size[0x18]; 11363 }; 11364 11365 struct mlx5_ifc_mtrc_cap_bits { 11366 u8 trace_owner[0x1]; 11367 u8 trace_to_memory[0x1]; 11368 u8 reserved_at_2[0x4]; 11369 u8 trc_ver[0x2]; 11370 u8 reserved_at_8[0x14]; 11371 u8 num_string_db[0x4]; 11372 11373 u8 first_string_trace[0x8]; 11374 u8 num_string_trace[0x8]; 11375 u8 reserved_at_30[0x28]; 11376 11377 u8 log_max_trace_buffer_size[0x8]; 11378 11379 u8 reserved_at_60[0x20]; 11380 11381 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11382 11383 u8 reserved_at_280[0x180]; 11384 }; 11385 11386 struct mlx5_ifc_mtrc_conf_bits { 11387 u8 reserved_at_0[0x1c]; 11388 u8 trace_mode[0x4]; 11389 u8 reserved_at_20[0x18]; 11390 u8 log_trace_buffer_size[0x8]; 11391 u8 trace_mkey[0x20]; 11392 u8 reserved_at_60[0x3a0]; 11393 }; 11394 11395 struct mlx5_ifc_mtrc_stdb_bits { 11396 u8 string_db_index[0x4]; 11397 u8 reserved_at_4[0x4]; 11398 u8 read_size[0x18]; 11399 u8 start_offset[0x20]; 11400 u8 string_db_data[]; 11401 }; 11402 11403 struct mlx5_ifc_mtrc_ctrl_bits { 11404 u8 trace_status[0x2]; 11405 u8 reserved_at_2[0x2]; 11406 u8 arm_event[0x1]; 11407 u8 reserved_at_5[0xb]; 11408 u8 modify_field_select[0x10]; 11409 u8 reserved_at_20[0x2b]; 11410 u8 current_timestamp52_32[0x15]; 11411 u8 current_timestamp31_0[0x20]; 11412 u8 reserved_at_80[0x180]; 11413 }; 11414 11415 struct mlx5_ifc_host_params_context_bits { 11416 u8 host_number[0x8]; 11417 u8 reserved_at_8[0x7]; 11418 u8 host_pf_disabled[0x1]; 11419 u8 host_num_of_vfs[0x10]; 11420 11421 u8 host_total_vfs[0x10]; 11422 u8 host_pci_bus[0x10]; 11423 11424 u8 reserved_at_40[0x10]; 11425 u8 host_pci_device[0x10]; 11426 11427 u8 reserved_at_60[0x10]; 11428 u8 host_pci_function[0x10]; 11429 11430 u8 reserved_at_80[0x180]; 11431 }; 11432 11433 struct mlx5_ifc_query_esw_functions_in_bits { 11434 u8 opcode[0x10]; 11435 u8 reserved_at_10[0x10]; 11436 11437 u8 reserved_at_20[0x10]; 11438 u8 op_mod[0x10]; 11439 11440 u8 reserved_at_40[0x40]; 11441 }; 11442 11443 struct mlx5_ifc_query_esw_functions_out_bits { 11444 u8 status[0x8]; 11445 u8 reserved_at_8[0x18]; 11446 11447 u8 syndrome[0x20]; 11448 11449 u8 reserved_at_40[0x40]; 11450 11451 struct mlx5_ifc_host_params_context_bits host_params_context; 11452 11453 u8 reserved_at_280[0x180]; 11454 u8 host_sf_enable[][0x40]; 11455 }; 11456 11457 struct mlx5_ifc_sf_partition_bits { 11458 u8 reserved_at_0[0x10]; 11459 u8 log_num_sf[0x8]; 11460 u8 log_sf_bar_size[0x8]; 11461 }; 11462 11463 struct mlx5_ifc_query_sf_partitions_out_bits { 11464 u8 status[0x8]; 11465 u8 reserved_at_8[0x18]; 11466 11467 u8 syndrome[0x20]; 11468 11469 u8 reserved_at_40[0x18]; 11470 u8 num_sf_partitions[0x8]; 11471 11472 u8 reserved_at_60[0x20]; 11473 11474 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11475 }; 11476 11477 struct mlx5_ifc_query_sf_partitions_in_bits { 11478 u8 opcode[0x10]; 11479 u8 reserved_at_10[0x10]; 11480 11481 u8 reserved_at_20[0x10]; 11482 u8 op_mod[0x10]; 11483 11484 u8 reserved_at_40[0x40]; 11485 }; 11486 11487 struct mlx5_ifc_dealloc_sf_out_bits { 11488 u8 status[0x8]; 11489 u8 reserved_at_8[0x18]; 11490 11491 u8 syndrome[0x20]; 11492 11493 u8 reserved_at_40[0x40]; 11494 }; 11495 11496 struct mlx5_ifc_dealloc_sf_in_bits { 11497 u8 opcode[0x10]; 11498 u8 reserved_at_10[0x10]; 11499 11500 u8 reserved_at_20[0x10]; 11501 u8 op_mod[0x10]; 11502 11503 u8 reserved_at_40[0x10]; 11504 u8 function_id[0x10]; 11505 11506 u8 reserved_at_60[0x20]; 11507 }; 11508 11509 struct mlx5_ifc_alloc_sf_out_bits { 11510 u8 status[0x8]; 11511 u8 reserved_at_8[0x18]; 11512 11513 u8 syndrome[0x20]; 11514 11515 u8 reserved_at_40[0x40]; 11516 }; 11517 11518 struct mlx5_ifc_alloc_sf_in_bits { 11519 u8 opcode[0x10]; 11520 u8 reserved_at_10[0x10]; 11521 11522 u8 reserved_at_20[0x10]; 11523 u8 op_mod[0x10]; 11524 11525 u8 reserved_at_40[0x10]; 11526 u8 function_id[0x10]; 11527 11528 u8 reserved_at_60[0x20]; 11529 }; 11530 11531 struct mlx5_ifc_affiliated_event_header_bits { 11532 u8 reserved_at_0[0x10]; 11533 u8 obj_type[0x10]; 11534 11535 u8 obj_id[0x20]; 11536 }; 11537 11538 enum { 11539 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11540 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11541 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11542 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11543 }; 11544 11545 enum { 11546 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11547 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11548 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11549 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11550 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11551 }; 11552 11553 enum { 11554 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11555 }; 11556 11557 struct mlx5_ifc_ipsec_obj_bits { 11558 u8 modify_field_select[0x40]; 11559 u8 full_offload[0x1]; 11560 u8 reserved_at_41[0x1]; 11561 u8 esn_en[0x1]; 11562 u8 esn_overlap[0x1]; 11563 u8 reserved_at_44[0x2]; 11564 u8 icv_length[0x2]; 11565 u8 reserved_at_48[0x4]; 11566 u8 aso_return_reg[0x4]; 11567 u8 reserved_at_50[0x10]; 11568 11569 u8 esn_msb[0x20]; 11570 11571 u8 reserved_at_80[0x8]; 11572 u8 dekn[0x18]; 11573 11574 u8 salt[0x20]; 11575 11576 u8 implicit_iv[0x40]; 11577 11578 u8 reserved_at_100[0x700]; 11579 }; 11580 11581 struct mlx5_ifc_create_ipsec_obj_in_bits { 11582 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11583 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11584 }; 11585 11586 enum { 11587 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11588 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11589 }; 11590 11591 struct mlx5_ifc_query_ipsec_obj_out_bits { 11592 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11593 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11594 }; 11595 11596 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11597 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11598 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11599 }; 11600 11601 enum { 11602 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11603 }; 11604 11605 enum { 11606 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11607 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11608 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11609 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11610 }; 11611 11612 #define MLX5_MACSEC_ASO_INC_SN 0x2 11613 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11614 11615 struct mlx5_ifc_macsec_aso_bits { 11616 u8 valid[0x1]; 11617 u8 reserved_at_1[0x1]; 11618 u8 mode[0x2]; 11619 u8 window_size[0x2]; 11620 u8 soft_lifetime_arm[0x1]; 11621 u8 hard_lifetime_arm[0x1]; 11622 u8 remove_flow_enable[0x1]; 11623 u8 epn_event_arm[0x1]; 11624 u8 reserved_at_a[0x16]; 11625 11626 u8 remove_flow_packet_count[0x20]; 11627 11628 u8 remove_flow_soft_lifetime[0x20]; 11629 11630 u8 reserved_at_60[0x80]; 11631 11632 u8 mode_parameter[0x20]; 11633 11634 u8 replay_protection_window[8][0x20]; 11635 }; 11636 11637 struct mlx5_ifc_macsec_offload_obj_bits { 11638 u8 modify_field_select[0x40]; 11639 11640 u8 confidentiality_en[0x1]; 11641 u8 reserved_at_41[0x1]; 11642 u8 epn_en[0x1]; 11643 u8 epn_overlap[0x1]; 11644 u8 reserved_at_44[0x2]; 11645 u8 confidentiality_offset[0x2]; 11646 u8 reserved_at_48[0x4]; 11647 u8 aso_return_reg[0x4]; 11648 u8 reserved_at_50[0x10]; 11649 11650 u8 epn_msb[0x20]; 11651 11652 u8 reserved_at_80[0x8]; 11653 u8 dekn[0x18]; 11654 11655 u8 reserved_at_a0[0x20]; 11656 11657 u8 sci[0x40]; 11658 11659 u8 reserved_at_100[0x8]; 11660 u8 macsec_aso_access_pd[0x18]; 11661 11662 u8 reserved_at_120[0x60]; 11663 11664 u8 salt[3][0x20]; 11665 11666 u8 reserved_at_1e0[0x20]; 11667 11668 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11669 }; 11670 11671 struct mlx5_ifc_create_macsec_obj_in_bits { 11672 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11673 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11674 }; 11675 11676 struct mlx5_ifc_modify_macsec_obj_in_bits { 11677 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11678 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11679 }; 11680 11681 enum { 11682 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11683 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11684 }; 11685 11686 struct mlx5_ifc_query_macsec_obj_out_bits { 11687 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11688 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11689 }; 11690 11691 struct mlx5_ifc_encryption_key_obj_bits { 11692 u8 modify_field_select[0x40]; 11693 11694 u8 reserved_at_40[0x14]; 11695 u8 key_size[0x4]; 11696 u8 reserved_at_58[0x4]; 11697 u8 key_type[0x4]; 11698 11699 u8 reserved_at_60[0x8]; 11700 u8 pd[0x18]; 11701 11702 u8 reserved_at_80[0x180]; 11703 u8 key[8][0x20]; 11704 11705 u8 reserved_at_300[0x500]; 11706 }; 11707 11708 struct mlx5_ifc_create_encryption_key_in_bits { 11709 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11710 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11711 }; 11712 11713 enum { 11714 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11715 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11716 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11717 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11718 }; 11719 11720 struct mlx5_ifc_flow_meter_parameters_bits { 11721 u8 valid[0x1]; 11722 u8 bucket_overflow[0x1]; 11723 u8 start_color[0x2]; 11724 u8 both_buckets_on_green[0x1]; 11725 u8 reserved_at_5[0x1]; 11726 u8 meter_mode[0x2]; 11727 u8 reserved_at_8[0x18]; 11728 11729 u8 reserved_at_20[0x20]; 11730 11731 u8 reserved_at_40[0x3]; 11732 u8 cbs_exponent[0x5]; 11733 u8 cbs_mantissa[0x8]; 11734 u8 reserved_at_50[0x3]; 11735 u8 cir_exponent[0x5]; 11736 u8 cir_mantissa[0x8]; 11737 11738 u8 reserved_at_60[0x20]; 11739 11740 u8 reserved_at_80[0x3]; 11741 u8 ebs_exponent[0x5]; 11742 u8 ebs_mantissa[0x8]; 11743 u8 reserved_at_90[0x3]; 11744 u8 eir_exponent[0x5]; 11745 u8 eir_mantissa[0x8]; 11746 11747 u8 reserved_at_a0[0x60]; 11748 }; 11749 11750 struct mlx5_ifc_flow_meter_aso_obj_bits { 11751 u8 modify_field_select[0x40]; 11752 11753 u8 reserved_at_40[0x40]; 11754 11755 u8 reserved_at_80[0x8]; 11756 u8 meter_aso_access_pd[0x18]; 11757 11758 u8 reserved_at_a0[0x160]; 11759 11760 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11761 }; 11762 11763 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11764 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11765 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11766 }; 11767 11768 struct mlx5_ifc_sampler_obj_bits { 11769 u8 modify_field_select[0x40]; 11770 11771 u8 table_type[0x8]; 11772 u8 level[0x8]; 11773 u8 reserved_at_50[0xf]; 11774 u8 ignore_flow_level[0x1]; 11775 11776 u8 sample_ratio[0x20]; 11777 11778 u8 reserved_at_80[0x8]; 11779 u8 sample_table_id[0x18]; 11780 11781 u8 reserved_at_a0[0x8]; 11782 u8 default_table_id[0x18]; 11783 11784 u8 sw_steering_icm_address_rx[0x40]; 11785 u8 sw_steering_icm_address_tx[0x40]; 11786 11787 u8 reserved_at_140[0xa0]; 11788 }; 11789 11790 struct mlx5_ifc_create_sampler_obj_in_bits { 11791 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11792 struct mlx5_ifc_sampler_obj_bits sampler_object; 11793 }; 11794 11795 struct mlx5_ifc_query_sampler_obj_out_bits { 11796 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11797 struct mlx5_ifc_sampler_obj_bits sampler_object; 11798 }; 11799 11800 enum { 11801 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11802 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11803 }; 11804 11805 enum { 11806 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11807 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11808 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4, 11809 }; 11810 11811 struct mlx5_ifc_tls_static_params_bits { 11812 u8 const_2[0x2]; 11813 u8 tls_version[0x4]; 11814 u8 const_1[0x2]; 11815 u8 reserved_at_8[0x14]; 11816 u8 encryption_standard[0x4]; 11817 11818 u8 reserved_at_20[0x20]; 11819 11820 u8 initial_record_number[0x40]; 11821 11822 u8 resync_tcp_sn[0x20]; 11823 11824 u8 gcm_iv[0x20]; 11825 11826 u8 implicit_iv[0x40]; 11827 11828 u8 reserved_at_100[0x8]; 11829 u8 dek_index[0x18]; 11830 11831 u8 reserved_at_120[0xe0]; 11832 }; 11833 11834 struct mlx5_ifc_tls_progress_params_bits { 11835 u8 next_record_tcp_sn[0x20]; 11836 11837 u8 hw_resync_tcp_sn[0x20]; 11838 11839 u8 record_tracker_state[0x2]; 11840 u8 auth_state[0x2]; 11841 u8 reserved_at_44[0x4]; 11842 u8 hw_offset_record_number[0x18]; 11843 }; 11844 11845 enum { 11846 MLX5_MTT_PERM_READ = 1 << 0, 11847 MLX5_MTT_PERM_WRITE = 1 << 1, 11848 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11849 }; 11850 11851 enum { 11852 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11853 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11854 }; 11855 11856 struct mlx5_ifc_suspend_vhca_in_bits { 11857 u8 opcode[0x10]; 11858 u8 uid[0x10]; 11859 11860 u8 reserved_at_20[0x10]; 11861 u8 op_mod[0x10]; 11862 11863 u8 reserved_at_40[0x10]; 11864 u8 vhca_id[0x10]; 11865 11866 u8 reserved_at_60[0x20]; 11867 }; 11868 11869 struct mlx5_ifc_suspend_vhca_out_bits { 11870 u8 status[0x8]; 11871 u8 reserved_at_8[0x18]; 11872 11873 u8 syndrome[0x20]; 11874 11875 u8 reserved_at_40[0x40]; 11876 }; 11877 11878 enum { 11879 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11880 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11881 }; 11882 11883 struct mlx5_ifc_resume_vhca_in_bits { 11884 u8 opcode[0x10]; 11885 u8 uid[0x10]; 11886 11887 u8 reserved_at_20[0x10]; 11888 u8 op_mod[0x10]; 11889 11890 u8 reserved_at_40[0x10]; 11891 u8 vhca_id[0x10]; 11892 11893 u8 reserved_at_60[0x20]; 11894 }; 11895 11896 struct mlx5_ifc_resume_vhca_out_bits { 11897 u8 status[0x8]; 11898 u8 reserved_at_8[0x18]; 11899 11900 u8 syndrome[0x20]; 11901 11902 u8 reserved_at_40[0x40]; 11903 }; 11904 11905 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11906 u8 opcode[0x10]; 11907 u8 uid[0x10]; 11908 11909 u8 reserved_at_20[0x10]; 11910 u8 op_mod[0x10]; 11911 11912 u8 reserved_at_40[0x10]; 11913 u8 vhca_id[0x10]; 11914 11915 u8 reserved_at_60[0x20]; 11916 }; 11917 11918 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11919 u8 status[0x8]; 11920 u8 reserved_at_8[0x18]; 11921 11922 u8 syndrome[0x20]; 11923 11924 u8 reserved_at_40[0x40]; 11925 11926 u8 required_umem_size[0x20]; 11927 11928 u8 reserved_at_a0[0x160]; 11929 }; 11930 11931 struct mlx5_ifc_save_vhca_state_in_bits { 11932 u8 opcode[0x10]; 11933 u8 uid[0x10]; 11934 11935 u8 reserved_at_20[0x10]; 11936 u8 op_mod[0x10]; 11937 11938 u8 reserved_at_40[0x10]; 11939 u8 vhca_id[0x10]; 11940 11941 u8 reserved_at_60[0x20]; 11942 11943 u8 va[0x40]; 11944 11945 u8 mkey[0x20]; 11946 11947 u8 size[0x20]; 11948 }; 11949 11950 struct mlx5_ifc_save_vhca_state_out_bits { 11951 u8 status[0x8]; 11952 u8 reserved_at_8[0x18]; 11953 11954 u8 syndrome[0x20]; 11955 11956 u8 actual_image_size[0x20]; 11957 11958 u8 reserved_at_60[0x20]; 11959 }; 11960 11961 struct mlx5_ifc_load_vhca_state_in_bits { 11962 u8 opcode[0x10]; 11963 u8 uid[0x10]; 11964 11965 u8 reserved_at_20[0x10]; 11966 u8 op_mod[0x10]; 11967 11968 u8 reserved_at_40[0x10]; 11969 u8 vhca_id[0x10]; 11970 11971 u8 reserved_at_60[0x20]; 11972 11973 u8 va[0x40]; 11974 11975 u8 mkey[0x20]; 11976 11977 u8 size[0x20]; 11978 }; 11979 11980 struct mlx5_ifc_load_vhca_state_out_bits { 11981 u8 status[0x8]; 11982 u8 reserved_at_8[0x18]; 11983 11984 u8 syndrome[0x20]; 11985 11986 u8 reserved_at_40[0x40]; 11987 }; 11988 11989 struct mlx5_ifc_adv_virtualization_cap_bits { 11990 u8 reserved_at_0[0x3]; 11991 u8 pg_track_log_max_num[0x5]; 11992 u8 pg_track_max_num_range[0x8]; 11993 u8 pg_track_log_min_addr_space[0x8]; 11994 u8 pg_track_log_max_addr_space[0x8]; 11995 11996 u8 reserved_at_20[0x3]; 11997 u8 pg_track_log_min_msg_size[0x5]; 11998 u8 reserved_at_28[0x3]; 11999 u8 pg_track_log_max_msg_size[0x5]; 12000 u8 reserved_at_30[0x3]; 12001 u8 pg_track_log_min_page_size[0x5]; 12002 u8 reserved_at_38[0x3]; 12003 u8 pg_track_log_max_page_size[0x5]; 12004 12005 u8 reserved_at_40[0x7c0]; 12006 }; 12007 12008 struct mlx5_ifc_page_track_report_entry_bits { 12009 u8 dirty_address_high[0x20]; 12010 12011 u8 dirty_address_low[0x20]; 12012 }; 12013 12014 enum { 12015 MLX5_PAGE_TRACK_STATE_TRACKING, 12016 MLX5_PAGE_TRACK_STATE_REPORTING, 12017 MLX5_PAGE_TRACK_STATE_ERROR, 12018 }; 12019 12020 struct mlx5_ifc_page_track_range_bits { 12021 u8 start_address[0x40]; 12022 12023 u8 length[0x40]; 12024 }; 12025 12026 struct mlx5_ifc_page_track_bits { 12027 u8 modify_field_select[0x40]; 12028 12029 u8 reserved_at_40[0x10]; 12030 u8 vhca_id[0x10]; 12031 12032 u8 reserved_at_60[0x20]; 12033 12034 u8 state[0x4]; 12035 u8 track_type[0x4]; 12036 u8 log_addr_space_size[0x8]; 12037 u8 reserved_at_90[0x3]; 12038 u8 log_page_size[0x5]; 12039 u8 reserved_at_98[0x3]; 12040 u8 log_msg_size[0x5]; 12041 12042 u8 reserved_at_a0[0x8]; 12043 u8 reporting_qpn[0x18]; 12044 12045 u8 reserved_at_c0[0x18]; 12046 u8 num_ranges[0x8]; 12047 12048 u8 reserved_at_e0[0x20]; 12049 12050 u8 range_start_address[0x40]; 12051 12052 u8 length[0x40]; 12053 12054 struct mlx5_ifc_page_track_range_bits track_range[0]; 12055 }; 12056 12057 struct mlx5_ifc_create_page_track_obj_in_bits { 12058 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12059 struct mlx5_ifc_page_track_bits obj_context; 12060 }; 12061 12062 struct mlx5_ifc_modify_page_track_obj_in_bits { 12063 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12064 struct mlx5_ifc_page_track_bits obj_context; 12065 }; 12066 12067 #endif /* MLX5_IFC_H */ 12068