1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 }; 82 83 enum { 84 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 85 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 86 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 87 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 88 }; 89 90 enum { 91 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 92 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 93 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 94 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 95 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 129 MLX5_CMD_OP_RESUME_VHCA = 0x116, 130 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 131 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 132 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 133 MLX5_CMD_OP_CREATE_MKEY = 0x200, 134 MLX5_CMD_OP_QUERY_MKEY = 0x201, 135 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 136 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 137 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 138 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 139 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 140 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 141 MLX5_CMD_OP_CREATE_EQ = 0x301, 142 MLX5_CMD_OP_DESTROY_EQ = 0x302, 143 MLX5_CMD_OP_QUERY_EQ = 0x303, 144 MLX5_CMD_OP_GEN_EQE = 0x304, 145 MLX5_CMD_OP_CREATE_CQ = 0x400, 146 MLX5_CMD_OP_DESTROY_CQ = 0x401, 147 MLX5_CMD_OP_QUERY_CQ = 0x402, 148 MLX5_CMD_OP_MODIFY_CQ = 0x403, 149 MLX5_CMD_OP_CREATE_QP = 0x500, 150 MLX5_CMD_OP_DESTROY_QP = 0x501, 151 MLX5_CMD_OP_RST2INIT_QP = 0x502, 152 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 153 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 154 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 155 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 156 MLX5_CMD_OP_2ERR_QP = 0x507, 157 MLX5_CMD_OP_2RST_QP = 0x50a, 158 MLX5_CMD_OP_QUERY_QP = 0x50b, 159 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 160 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 161 MLX5_CMD_OP_CREATE_PSV = 0x600, 162 MLX5_CMD_OP_DESTROY_PSV = 0x601, 163 MLX5_CMD_OP_CREATE_SRQ = 0x700, 164 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 165 MLX5_CMD_OP_QUERY_SRQ = 0x702, 166 MLX5_CMD_OP_ARM_RQ = 0x703, 167 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 168 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 169 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 170 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 171 MLX5_CMD_OP_CREATE_DCT = 0x710, 172 MLX5_CMD_OP_DESTROY_DCT = 0x711, 173 MLX5_CMD_OP_DRAIN_DCT = 0x712, 174 MLX5_CMD_OP_QUERY_DCT = 0x713, 175 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 176 MLX5_CMD_OP_CREATE_XRQ = 0x717, 177 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 178 MLX5_CMD_OP_QUERY_XRQ = 0x719, 179 MLX5_CMD_OP_ARM_XRQ = 0x71a, 180 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 181 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 182 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 183 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 184 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 185 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 186 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 187 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 188 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 189 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 190 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 191 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 192 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 193 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 195 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 198 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 199 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 200 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 201 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 202 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 203 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 204 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 205 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 206 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 207 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 208 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 209 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 210 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 211 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 212 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 213 MLX5_CMD_OP_ALLOC_PD = 0x800, 214 MLX5_CMD_OP_DEALLOC_PD = 0x801, 215 MLX5_CMD_OP_ALLOC_UAR = 0x802, 216 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 217 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 218 MLX5_CMD_OP_ACCESS_REG = 0x805, 219 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 220 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 221 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 222 MLX5_CMD_OP_MAD_IFC = 0x50d, 223 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 224 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 225 MLX5_CMD_OP_NOP = 0x80d, 226 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 227 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 229 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 230 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 231 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 232 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 233 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 234 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 235 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 236 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 237 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 238 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 239 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 240 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 241 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 242 MLX5_CMD_OP_CREATE_LAG = 0x840, 243 MLX5_CMD_OP_MODIFY_LAG = 0x841, 244 MLX5_CMD_OP_QUERY_LAG = 0x842, 245 MLX5_CMD_OP_DESTROY_LAG = 0x843, 246 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 247 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 248 MLX5_CMD_OP_CREATE_TIR = 0x900, 249 MLX5_CMD_OP_MODIFY_TIR = 0x901, 250 MLX5_CMD_OP_DESTROY_TIR = 0x902, 251 MLX5_CMD_OP_QUERY_TIR = 0x903, 252 MLX5_CMD_OP_CREATE_SQ = 0x904, 253 MLX5_CMD_OP_MODIFY_SQ = 0x905, 254 MLX5_CMD_OP_DESTROY_SQ = 0x906, 255 MLX5_CMD_OP_QUERY_SQ = 0x907, 256 MLX5_CMD_OP_CREATE_RQ = 0x908, 257 MLX5_CMD_OP_MODIFY_RQ = 0x909, 258 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 259 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 260 MLX5_CMD_OP_QUERY_RQ = 0x90b, 261 MLX5_CMD_OP_CREATE_RMP = 0x90c, 262 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 263 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 264 MLX5_CMD_OP_QUERY_RMP = 0x90f, 265 MLX5_CMD_OP_CREATE_TIS = 0x912, 266 MLX5_CMD_OP_MODIFY_TIS = 0x913, 267 MLX5_CMD_OP_DESTROY_TIS = 0x914, 268 MLX5_CMD_OP_QUERY_TIS = 0x915, 269 MLX5_CMD_OP_CREATE_RQT = 0x916, 270 MLX5_CMD_OP_MODIFY_RQT = 0x917, 271 MLX5_CMD_OP_DESTROY_RQT = 0x918, 272 MLX5_CMD_OP_QUERY_RQT = 0x919, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 274 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 275 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 277 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 278 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 279 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 282 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 283 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 284 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 285 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 286 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 287 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 288 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 289 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 290 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 291 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 292 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 293 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 294 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 295 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 296 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 297 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 298 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 299 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 300 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 301 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 302 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 303 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 304 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 305 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 306 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 307 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 308 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 309 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 310 MLX5_CMD_OP_MAX 311 }; 312 313 /* Valid range for general commands that don't work over an object */ 314 enum { 315 MLX5_CMD_OP_GENERAL_START = 0xb00, 316 MLX5_CMD_OP_GENERAL_END = 0xd00, 317 }; 318 319 struct mlx5_ifc_flow_table_fields_supported_bits { 320 u8 outer_dmac[0x1]; 321 u8 outer_smac[0x1]; 322 u8 outer_ether_type[0x1]; 323 u8 outer_ip_version[0x1]; 324 u8 outer_first_prio[0x1]; 325 u8 outer_first_cfi[0x1]; 326 u8 outer_first_vid[0x1]; 327 u8 outer_ipv4_ttl[0x1]; 328 u8 outer_second_prio[0x1]; 329 u8 outer_second_cfi[0x1]; 330 u8 outer_second_vid[0x1]; 331 u8 reserved_at_b[0x1]; 332 u8 outer_sip[0x1]; 333 u8 outer_dip[0x1]; 334 u8 outer_frag[0x1]; 335 u8 outer_ip_protocol[0x1]; 336 u8 outer_ip_ecn[0x1]; 337 u8 outer_ip_dscp[0x1]; 338 u8 outer_udp_sport[0x1]; 339 u8 outer_udp_dport[0x1]; 340 u8 outer_tcp_sport[0x1]; 341 u8 outer_tcp_dport[0x1]; 342 u8 outer_tcp_flags[0x1]; 343 u8 outer_gre_protocol[0x1]; 344 u8 outer_gre_key[0x1]; 345 u8 outer_vxlan_vni[0x1]; 346 u8 outer_geneve_vni[0x1]; 347 u8 outer_geneve_oam[0x1]; 348 u8 outer_geneve_protocol_type[0x1]; 349 u8 outer_geneve_opt_len[0x1]; 350 u8 source_vhca_port[0x1]; 351 u8 source_eswitch_port[0x1]; 352 353 u8 inner_dmac[0x1]; 354 u8 inner_smac[0x1]; 355 u8 inner_ether_type[0x1]; 356 u8 inner_ip_version[0x1]; 357 u8 inner_first_prio[0x1]; 358 u8 inner_first_cfi[0x1]; 359 u8 inner_first_vid[0x1]; 360 u8 reserved_at_27[0x1]; 361 u8 inner_second_prio[0x1]; 362 u8 inner_second_cfi[0x1]; 363 u8 inner_second_vid[0x1]; 364 u8 reserved_at_2b[0x1]; 365 u8 inner_sip[0x1]; 366 u8 inner_dip[0x1]; 367 u8 inner_frag[0x1]; 368 u8 inner_ip_protocol[0x1]; 369 u8 inner_ip_ecn[0x1]; 370 u8 inner_ip_dscp[0x1]; 371 u8 inner_udp_sport[0x1]; 372 u8 inner_udp_dport[0x1]; 373 u8 inner_tcp_sport[0x1]; 374 u8 inner_tcp_dport[0x1]; 375 u8 inner_tcp_flags[0x1]; 376 u8 reserved_at_37[0x9]; 377 378 u8 geneve_tlv_option_0_data[0x1]; 379 u8 geneve_tlv_option_0_exist[0x1]; 380 u8 reserved_at_42[0x3]; 381 u8 outer_first_mpls_over_udp[0x4]; 382 u8 outer_first_mpls_over_gre[0x4]; 383 u8 inner_first_mpls[0x4]; 384 u8 outer_first_mpls[0x4]; 385 u8 reserved_at_55[0x2]; 386 u8 outer_esp_spi[0x1]; 387 u8 reserved_at_58[0x2]; 388 u8 bth_dst_qp[0x1]; 389 u8 reserved_at_5b[0x5]; 390 391 u8 reserved_at_60[0x18]; 392 u8 metadata_reg_c_7[0x1]; 393 u8 metadata_reg_c_6[0x1]; 394 u8 metadata_reg_c_5[0x1]; 395 u8 metadata_reg_c_4[0x1]; 396 u8 metadata_reg_c_3[0x1]; 397 u8 metadata_reg_c_2[0x1]; 398 u8 metadata_reg_c_1[0x1]; 399 u8 metadata_reg_c_0[0x1]; 400 }; 401 402 struct mlx5_ifc_flow_table_fields_supported_2_bits { 403 u8 reserved_at_0[0xe]; 404 u8 bth_opcode[0x1]; 405 u8 reserved_at_f[0x11]; 406 407 u8 reserved_at_20[0x60]; 408 }; 409 410 struct mlx5_ifc_flow_table_prop_layout_bits { 411 u8 ft_support[0x1]; 412 u8 reserved_at_1[0x1]; 413 u8 flow_counter[0x1]; 414 u8 flow_modify_en[0x1]; 415 u8 modify_root[0x1]; 416 u8 identified_miss_table_mode[0x1]; 417 u8 flow_table_modify[0x1]; 418 u8 reformat[0x1]; 419 u8 decap[0x1]; 420 u8 reserved_at_9[0x1]; 421 u8 pop_vlan[0x1]; 422 u8 push_vlan[0x1]; 423 u8 reserved_at_c[0x1]; 424 u8 pop_vlan_2[0x1]; 425 u8 push_vlan_2[0x1]; 426 u8 reformat_and_vlan_action[0x1]; 427 u8 reserved_at_10[0x1]; 428 u8 sw_owner[0x1]; 429 u8 reformat_l3_tunnel_to_l2[0x1]; 430 u8 reformat_l2_to_l3_tunnel[0x1]; 431 u8 reformat_and_modify_action[0x1]; 432 u8 ignore_flow_level[0x1]; 433 u8 reserved_at_16[0x1]; 434 u8 table_miss_action_domain[0x1]; 435 u8 termination_table[0x1]; 436 u8 reformat_and_fwd_to_table[0x1]; 437 u8 reserved_at_1a[0x2]; 438 u8 ipsec_encrypt[0x1]; 439 u8 ipsec_decrypt[0x1]; 440 u8 sw_owner_v2[0x1]; 441 u8 reserved_at_1f[0x1]; 442 443 u8 termination_table_raw_traffic[0x1]; 444 u8 reserved_at_21[0x1]; 445 u8 log_max_ft_size[0x6]; 446 u8 log_max_modify_header_context[0x8]; 447 u8 max_modify_header_actions[0x8]; 448 u8 max_ft_level[0x8]; 449 450 u8 reformat_add_esp_trasport[0x1]; 451 u8 reserved_at_41[0x2]; 452 u8 reformat_del_esp_trasport[0x1]; 453 u8 reserved_at_44[0x2]; 454 u8 execute_aso[0x1]; 455 u8 reserved_at_47[0x19]; 456 457 u8 reserved_at_60[0x2]; 458 u8 reformat_insert[0x1]; 459 u8 reformat_remove[0x1]; 460 u8 macsec_encrypt[0x1]; 461 u8 macsec_decrypt[0x1]; 462 u8 reserved_at_66[0x2]; 463 u8 reformat_add_macsec[0x1]; 464 u8 reformat_remove_macsec[0x1]; 465 u8 reserved_at_6a[0xe]; 466 u8 log_max_ft_num[0x8]; 467 468 u8 reserved_at_80[0x10]; 469 u8 log_max_flow_counter[0x8]; 470 u8 log_max_destination[0x8]; 471 472 u8 reserved_at_a0[0x18]; 473 u8 log_max_flow[0x8]; 474 475 u8 reserved_at_c0[0x40]; 476 477 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 478 479 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 480 }; 481 482 struct mlx5_ifc_odp_per_transport_service_cap_bits { 483 u8 send[0x1]; 484 u8 receive[0x1]; 485 u8 write[0x1]; 486 u8 read[0x1]; 487 u8 atomic[0x1]; 488 u8 srq_receive[0x1]; 489 u8 reserved_at_6[0x1a]; 490 }; 491 492 struct mlx5_ifc_ipv4_layout_bits { 493 u8 reserved_at_0[0x60]; 494 495 u8 ipv4[0x20]; 496 }; 497 498 struct mlx5_ifc_ipv6_layout_bits { 499 u8 ipv6[16][0x8]; 500 }; 501 502 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 503 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 504 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 505 u8 reserved_at_0[0x80]; 506 }; 507 508 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 509 u8 smac_47_16[0x20]; 510 511 u8 smac_15_0[0x10]; 512 u8 ethertype[0x10]; 513 514 u8 dmac_47_16[0x20]; 515 516 u8 dmac_15_0[0x10]; 517 u8 first_prio[0x3]; 518 u8 first_cfi[0x1]; 519 u8 first_vid[0xc]; 520 521 u8 ip_protocol[0x8]; 522 u8 ip_dscp[0x6]; 523 u8 ip_ecn[0x2]; 524 u8 cvlan_tag[0x1]; 525 u8 svlan_tag[0x1]; 526 u8 frag[0x1]; 527 u8 ip_version[0x4]; 528 u8 tcp_flags[0x9]; 529 530 u8 tcp_sport[0x10]; 531 u8 tcp_dport[0x10]; 532 533 u8 reserved_at_c0[0x10]; 534 u8 ipv4_ihl[0x4]; 535 u8 reserved_at_c4[0x4]; 536 537 u8 ttl_hoplimit[0x8]; 538 539 u8 udp_sport[0x10]; 540 u8 udp_dport[0x10]; 541 542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 543 544 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 545 }; 546 547 struct mlx5_ifc_nvgre_key_bits { 548 u8 hi[0x18]; 549 u8 lo[0x8]; 550 }; 551 552 union mlx5_ifc_gre_key_bits { 553 struct mlx5_ifc_nvgre_key_bits nvgre; 554 u8 key[0x20]; 555 }; 556 557 struct mlx5_ifc_fte_match_set_misc_bits { 558 u8 gre_c_present[0x1]; 559 u8 reserved_at_1[0x1]; 560 u8 gre_k_present[0x1]; 561 u8 gre_s_present[0x1]; 562 u8 source_vhca_port[0x4]; 563 u8 source_sqn[0x18]; 564 565 u8 source_eswitch_owner_vhca_id[0x10]; 566 u8 source_port[0x10]; 567 568 u8 outer_second_prio[0x3]; 569 u8 outer_second_cfi[0x1]; 570 u8 outer_second_vid[0xc]; 571 u8 inner_second_prio[0x3]; 572 u8 inner_second_cfi[0x1]; 573 u8 inner_second_vid[0xc]; 574 575 u8 outer_second_cvlan_tag[0x1]; 576 u8 inner_second_cvlan_tag[0x1]; 577 u8 outer_second_svlan_tag[0x1]; 578 u8 inner_second_svlan_tag[0x1]; 579 u8 reserved_at_64[0xc]; 580 u8 gre_protocol[0x10]; 581 582 union mlx5_ifc_gre_key_bits gre_key; 583 584 u8 vxlan_vni[0x18]; 585 u8 bth_opcode[0x8]; 586 587 u8 geneve_vni[0x18]; 588 u8 reserved_at_d8[0x6]; 589 u8 geneve_tlv_option_0_exist[0x1]; 590 u8 geneve_oam[0x1]; 591 592 u8 reserved_at_e0[0xc]; 593 u8 outer_ipv6_flow_label[0x14]; 594 595 u8 reserved_at_100[0xc]; 596 u8 inner_ipv6_flow_label[0x14]; 597 598 u8 reserved_at_120[0xa]; 599 u8 geneve_opt_len[0x6]; 600 u8 geneve_protocol_type[0x10]; 601 602 u8 reserved_at_140[0x8]; 603 u8 bth_dst_qp[0x18]; 604 u8 reserved_at_160[0x20]; 605 u8 outer_esp_spi[0x20]; 606 u8 reserved_at_1a0[0x60]; 607 }; 608 609 struct mlx5_ifc_fte_match_mpls_bits { 610 u8 mpls_label[0x14]; 611 u8 mpls_exp[0x3]; 612 u8 mpls_s_bos[0x1]; 613 u8 mpls_ttl[0x8]; 614 }; 615 616 struct mlx5_ifc_fte_match_set_misc2_bits { 617 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 618 619 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 620 621 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 622 623 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 624 625 u8 metadata_reg_c_7[0x20]; 626 627 u8 metadata_reg_c_6[0x20]; 628 629 u8 metadata_reg_c_5[0x20]; 630 631 u8 metadata_reg_c_4[0x20]; 632 633 u8 metadata_reg_c_3[0x20]; 634 635 u8 metadata_reg_c_2[0x20]; 636 637 u8 metadata_reg_c_1[0x20]; 638 639 u8 metadata_reg_c_0[0x20]; 640 641 u8 metadata_reg_a[0x20]; 642 643 u8 reserved_at_1a0[0x8]; 644 645 u8 macsec_syndrome[0x8]; 646 u8 ipsec_syndrome[0x8]; 647 u8 reserved_at_1b8[0x8]; 648 649 u8 reserved_at_1c0[0x40]; 650 }; 651 652 struct mlx5_ifc_fte_match_set_misc3_bits { 653 u8 inner_tcp_seq_num[0x20]; 654 655 u8 outer_tcp_seq_num[0x20]; 656 657 u8 inner_tcp_ack_num[0x20]; 658 659 u8 outer_tcp_ack_num[0x20]; 660 661 u8 reserved_at_80[0x8]; 662 u8 outer_vxlan_gpe_vni[0x18]; 663 664 u8 outer_vxlan_gpe_next_protocol[0x8]; 665 u8 outer_vxlan_gpe_flags[0x8]; 666 u8 reserved_at_b0[0x10]; 667 668 u8 icmp_header_data[0x20]; 669 670 u8 icmpv6_header_data[0x20]; 671 672 u8 icmp_type[0x8]; 673 u8 icmp_code[0x8]; 674 u8 icmpv6_type[0x8]; 675 u8 icmpv6_code[0x8]; 676 677 u8 geneve_tlv_option_0_data[0x20]; 678 679 u8 gtpu_teid[0x20]; 680 681 u8 gtpu_msg_type[0x8]; 682 u8 gtpu_msg_flags[0x8]; 683 u8 reserved_at_170[0x10]; 684 685 u8 gtpu_dw_2[0x20]; 686 687 u8 gtpu_first_ext_dw_0[0x20]; 688 689 u8 gtpu_dw_0[0x20]; 690 691 u8 reserved_at_1e0[0x20]; 692 }; 693 694 struct mlx5_ifc_fte_match_set_misc4_bits { 695 u8 prog_sample_field_value_0[0x20]; 696 697 u8 prog_sample_field_id_0[0x20]; 698 699 u8 prog_sample_field_value_1[0x20]; 700 701 u8 prog_sample_field_id_1[0x20]; 702 703 u8 prog_sample_field_value_2[0x20]; 704 705 u8 prog_sample_field_id_2[0x20]; 706 707 u8 prog_sample_field_value_3[0x20]; 708 709 u8 prog_sample_field_id_3[0x20]; 710 711 u8 reserved_at_100[0x100]; 712 }; 713 714 struct mlx5_ifc_fte_match_set_misc5_bits { 715 u8 macsec_tag_0[0x20]; 716 717 u8 macsec_tag_1[0x20]; 718 719 u8 macsec_tag_2[0x20]; 720 721 u8 macsec_tag_3[0x20]; 722 723 u8 tunnel_header_0[0x20]; 724 725 u8 tunnel_header_1[0x20]; 726 727 u8 tunnel_header_2[0x20]; 728 729 u8 tunnel_header_3[0x20]; 730 731 u8 reserved_at_100[0x100]; 732 }; 733 734 struct mlx5_ifc_cmd_pas_bits { 735 u8 pa_h[0x20]; 736 737 u8 pa_l[0x14]; 738 u8 reserved_at_34[0xc]; 739 }; 740 741 struct mlx5_ifc_uint64_bits { 742 u8 hi[0x20]; 743 744 u8 lo[0x20]; 745 }; 746 747 enum { 748 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 749 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 750 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 751 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 752 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 753 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 754 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 755 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 756 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 757 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 758 }; 759 760 struct mlx5_ifc_ads_bits { 761 u8 fl[0x1]; 762 u8 free_ar[0x1]; 763 u8 reserved_at_2[0xe]; 764 u8 pkey_index[0x10]; 765 766 u8 reserved_at_20[0x8]; 767 u8 grh[0x1]; 768 u8 mlid[0x7]; 769 u8 rlid[0x10]; 770 771 u8 ack_timeout[0x5]; 772 u8 reserved_at_45[0x3]; 773 u8 src_addr_index[0x8]; 774 u8 reserved_at_50[0x4]; 775 u8 stat_rate[0x4]; 776 u8 hop_limit[0x8]; 777 778 u8 reserved_at_60[0x4]; 779 u8 tclass[0x8]; 780 u8 flow_label[0x14]; 781 782 u8 rgid_rip[16][0x8]; 783 784 u8 reserved_at_100[0x4]; 785 u8 f_dscp[0x1]; 786 u8 f_ecn[0x1]; 787 u8 reserved_at_106[0x1]; 788 u8 f_eth_prio[0x1]; 789 u8 ecn[0x2]; 790 u8 dscp[0x6]; 791 u8 udp_sport[0x10]; 792 793 u8 dei_cfi[0x1]; 794 u8 eth_prio[0x3]; 795 u8 sl[0x4]; 796 u8 vhca_port_num[0x8]; 797 u8 rmac_47_32[0x10]; 798 799 u8 rmac_31_0[0x20]; 800 }; 801 802 struct mlx5_ifc_flow_table_nic_cap_bits { 803 u8 nic_rx_multi_path_tirs[0x1]; 804 u8 nic_rx_multi_path_tirs_fts[0x1]; 805 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 806 u8 reserved_at_3[0x4]; 807 u8 sw_owner_reformat_supported[0x1]; 808 u8 reserved_at_8[0x18]; 809 810 u8 encap_general_header[0x1]; 811 u8 reserved_at_21[0xa]; 812 u8 log_max_packet_reformat_context[0x5]; 813 u8 reserved_at_30[0x6]; 814 u8 max_encap_header_size[0xa]; 815 u8 reserved_at_40[0x1c0]; 816 817 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 818 819 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 820 821 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 822 823 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 824 825 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 826 827 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 828 829 u8 reserved_at_e00[0x700]; 830 831 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 832 833 u8 reserved_at_1580[0x280]; 834 835 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 836 837 u8 reserved_at_1880[0x780]; 838 839 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 840 841 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 842 843 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 844 845 u8 reserved_at_20c0[0x5f40]; 846 }; 847 848 struct mlx5_ifc_port_selection_cap_bits { 849 u8 reserved_at_0[0x10]; 850 u8 port_select_flow_table[0x1]; 851 u8 reserved_at_11[0x1]; 852 u8 port_select_flow_table_bypass[0x1]; 853 u8 reserved_at_13[0xd]; 854 855 u8 reserved_at_20[0x1e0]; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 858 859 u8 reserved_at_400[0x7c00]; 860 }; 861 862 enum { 863 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 864 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 865 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 866 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 867 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 868 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 869 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 870 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 871 }; 872 873 struct mlx5_ifc_flow_table_eswitch_cap_bits { 874 u8 fdb_to_vport_reg_c_id[0x8]; 875 u8 reserved_at_8[0xd]; 876 u8 fdb_modify_header_fwd_to_table[0x1]; 877 u8 fdb_ipv4_ttl_modify[0x1]; 878 u8 flow_source[0x1]; 879 u8 reserved_at_18[0x2]; 880 u8 multi_fdb_encap[0x1]; 881 u8 egress_acl_forward_to_vport[0x1]; 882 u8 fdb_multi_path_to_table[0x1]; 883 u8 reserved_at_1d[0x3]; 884 885 u8 reserved_at_20[0x1e0]; 886 887 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 888 889 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 892 893 u8 reserved_at_800[0x1000]; 894 895 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 896 897 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 898 899 u8 sw_steering_uplink_icm_address_rx[0x40]; 900 901 u8 sw_steering_uplink_icm_address_tx[0x40]; 902 903 u8 reserved_at_1900[0x6700]; 904 }; 905 906 enum { 907 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 908 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 909 }; 910 911 struct mlx5_ifc_e_switch_cap_bits { 912 u8 vport_svlan_strip[0x1]; 913 u8 vport_cvlan_strip[0x1]; 914 u8 vport_svlan_insert[0x1]; 915 u8 vport_cvlan_insert_if_not_exist[0x1]; 916 u8 vport_cvlan_insert_overwrite[0x1]; 917 u8 reserved_at_5[0x1]; 918 u8 vport_cvlan_insert_always[0x1]; 919 u8 esw_shared_ingress_acl[0x1]; 920 u8 esw_uplink_ingress_acl[0x1]; 921 u8 root_ft_on_other_esw[0x1]; 922 u8 reserved_at_a[0xf]; 923 u8 esw_functions_changed[0x1]; 924 u8 reserved_at_1a[0x1]; 925 u8 ecpf_vport_exists[0x1]; 926 u8 counter_eswitch_affinity[0x1]; 927 u8 merged_eswitch[0x1]; 928 u8 nic_vport_node_guid_modify[0x1]; 929 u8 nic_vport_port_guid_modify[0x1]; 930 931 u8 vxlan_encap_decap[0x1]; 932 u8 nvgre_encap_decap[0x1]; 933 u8 reserved_at_22[0x1]; 934 u8 log_max_fdb_encap_uplink[0x5]; 935 u8 reserved_at_21[0x3]; 936 u8 log_max_packet_reformat_context[0x5]; 937 u8 reserved_2b[0x6]; 938 u8 max_encap_header_size[0xa]; 939 940 u8 reserved_at_40[0xb]; 941 u8 log_max_esw_sf[0x5]; 942 u8 esw_sf_base_id[0x10]; 943 944 u8 reserved_at_60[0x7a0]; 945 946 }; 947 948 struct mlx5_ifc_qos_cap_bits { 949 u8 packet_pacing[0x1]; 950 u8 esw_scheduling[0x1]; 951 u8 esw_bw_share[0x1]; 952 u8 esw_rate_limit[0x1]; 953 u8 reserved_at_4[0x1]; 954 u8 packet_pacing_burst_bound[0x1]; 955 u8 packet_pacing_typical_size[0x1]; 956 u8 reserved_at_7[0x1]; 957 u8 nic_sq_scheduling[0x1]; 958 u8 nic_bw_share[0x1]; 959 u8 nic_rate_limit[0x1]; 960 u8 packet_pacing_uid[0x1]; 961 u8 log_esw_max_sched_depth[0x4]; 962 u8 reserved_at_10[0x10]; 963 964 u8 reserved_at_20[0xb]; 965 u8 log_max_qos_nic_queue_group[0x5]; 966 u8 reserved_at_30[0x10]; 967 968 u8 packet_pacing_max_rate[0x20]; 969 970 u8 packet_pacing_min_rate[0x20]; 971 972 u8 reserved_at_80[0x10]; 973 u8 packet_pacing_rate_table_size[0x10]; 974 975 u8 esw_element_type[0x10]; 976 u8 esw_tsar_type[0x10]; 977 978 u8 reserved_at_c0[0x10]; 979 u8 max_qos_para_vport[0x10]; 980 981 u8 max_tsar_bw_share[0x20]; 982 983 u8 reserved_at_100[0x20]; 984 985 u8 reserved_at_120[0x3]; 986 u8 log_meter_aso_granularity[0x5]; 987 u8 reserved_at_128[0x3]; 988 u8 log_meter_aso_max_alloc[0x5]; 989 u8 reserved_at_130[0x3]; 990 u8 log_max_num_meter_aso[0x5]; 991 u8 reserved_at_138[0x8]; 992 993 u8 reserved_at_140[0x6c0]; 994 }; 995 996 struct mlx5_ifc_debug_cap_bits { 997 u8 core_dump_general[0x1]; 998 u8 core_dump_qp[0x1]; 999 u8 reserved_at_2[0x7]; 1000 u8 resource_dump[0x1]; 1001 u8 reserved_at_a[0x16]; 1002 1003 u8 reserved_at_20[0x2]; 1004 u8 stall_detect[0x1]; 1005 u8 reserved_at_23[0x1d]; 1006 1007 u8 reserved_at_40[0x7c0]; 1008 }; 1009 1010 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1011 u8 csum_cap[0x1]; 1012 u8 vlan_cap[0x1]; 1013 u8 lro_cap[0x1]; 1014 u8 lro_psh_flag[0x1]; 1015 u8 lro_time_stamp[0x1]; 1016 u8 reserved_at_5[0x2]; 1017 u8 wqe_vlan_insert[0x1]; 1018 u8 self_lb_en_modifiable[0x1]; 1019 u8 reserved_at_9[0x2]; 1020 u8 max_lso_cap[0x5]; 1021 u8 multi_pkt_send_wqe[0x2]; 1022 u8 wqe_inline_mode[0x2]; 1023 u8 rss_ind_tbl_cap[0x4]; 1024 u8 reg_umr_sq[0x1]; 1025 u8 scatter_fcs[0x1]; 1026 u8 enhanced_multi_pkt_send_wqe[0x1]; 1027 u8 tunnel_lso_const_out_ip_id[0x1]; 1028 u8 tunnel_lro_gre[0x1]; 1029 u8 tunnel_lro_vxlan[0x1]; 1030 u8 tunnel_stateless_gre[0x1]; 1031 u8 tunnel_stateless_vxlan[0x1]; 1032 1033 u8 swp[0x1]; 1034 u8 swp_csum[0x1]; 1035 u8 swp_lso[0x1]; 1036 u8 cqe_checksum_full[0x1]; 1037 u8 tunnel_stateless_geneve_tx[0x1]; 1038 u8 tunnel_stateless_mpls_over_udp[0x1]; 1039 u8 tunnel_stateless_mpls_over_gre[0x1]; 1040 u8 tunnel_stateless_vxlan_gpe[0x1]; 1041 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1042 u8 tunnel_stateless_ip_over_ip[0x1]; 1043 u8 insert_trailer[0x1]; 1044 u8 reserved_at_2b[0x1]; 1045 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1046 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1047 u8 reserved_at_2e[0x2]; 1048 u8 max_vxlan_udp_ports[0x8]; 1049 u8 reserved_at_38[0x6]; 1050 u8 max_geneve_opt_len[0x1]; 1051 u8 tunnel_stateless_geneve_rx[0x1]; 1052 1053 u8 reserved_at_40[0x10]; 1054 u8 lro_min_mss_size[0x10]; 1055 1056 u8 reserved_at_60[0x120]; 1057 1058 u8 lro_timer_supported_periods[4][0x20]; 1059 1060 u8 reserved_at_200[0x600]; 1061 }; 1062 1063 enum { 1064 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1065 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1066 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1067 }; 1068 1069 struct mlx5_ifc_roce_cap_bits { 1070 u8 roce_apm[0x1]; 1071 u8 reserved_at_1[0x3]; 1072 u8 sw_r_roce_src_udp_port[0x1]; 1073 u8 fl_rc_qp_when_roce_disabled[0x1]; 1074 u8 fl_rc_qp_when_roce_enabled[0x1]; 1075 u8 reserved_at_7[0x17]; 1076 u8 qp_ts_format[0x2]; 1077 1078 u8 reserved_at_20[0x60]; 1079 1080 u8 reserved_at_80[0xc]; 1081 u8 l3_type[0x4]; 1082 u8 reserved_at_90[0x8]; 1083 u8 roce_version[0x8]; 1084 1085 u8 reserved_at_a0[0x10]; 1086 u8 r_roce_dest_udp_port[0x10]; 1087 1088 u8 r_roce_max_src_udp_port[0x10]; 1089 u8 r_roce_min_src_udp_port[0x10]; 1090 1091 u8 reserved_at_e0[0x10]; 1092 u8 roce_address_table_size[0x10]; 1093 1094 u8 reserved_at_100[0x700]; 1095 }; 1096 1097 struct mlx5_ifc_sync_steering_in_bits { 1098 u8 opcode[0x10]; 1099 u8 uid[0x10]; 1100 1101 u8 reserved_at_20[0x10]; 1102 u8 op_mod[0x10]; 1103 1104 u8 reserved_at_40[0xc0]; 1105 }; 1106 1107 struct mlx5_ifc_sync_steering_out_bits { 1108 u8 status[0x8]; 1109 u8 reserved_at_8[0x18]; 1110 1111 u8 syndrome[0x20]; 1112 1113 u8 reserved_at_40[0x40]; 1114 }; 1115 1116 struct mlx5_ifc_sync_crypto_in_bits { 1117 u8 opcode[0x10]; 1118 u8 uid[0x10]; 1119 1120 u8 reserved_at_20[0x10]; 1121 u8 op_mod[0x10]; 1122 1123 u8 reserved_at_40[0x20]; 1124 1125 u8 reserved_at_60[0x10]; 1126 u8 crypto_type[0x10]; 1127 1128 u8 reserved_at_80[0x80]; 1129 }; 1130 1131 struct mlx5_ifc_sync_crypto_out_bits { 1132 u8 status[0x8]; 1133 u8 reserved_at_8[0x18]; 1134 1135 u8 syndrome[0x20]; 1136 1137 u8 reserved_at_40[0x40]; 1138 }; 1139 1140 struct mlx5_ifc_device_mem_cap_bits { 1141 u8 memic[0x1]; 1142 u8 reserved_at_1[0x1f]; 1143 1144 u8 reserved_at_20[0xb]; 1145 u8 log_min_memic_alloc_size[0x5]; 1146 u8 reserved_at_30[0x8]; 1147 u8 log_max_memic_addr_alignment[0x8]; 1148 1149 u8 memic_bar_start_addr[0x40]; 1150 1151 u8 memic_bar_size[0x20]; 1152 1153 u8 max_memic_size[0x20]; 1154 1155 u8 steering_sw_icm_start_address[0x40]; 1156 1157 u8 reserved_at_100[0x8]; 1158 u8 log_header_modify_sw_icm_size[0x8]; 1159 u8 reserved_at_110[0x2]; 1160 u8 log_sw_icm_alloc_granularity[0x6]; 1161 u8 log_steering_sw_icm_size[0x8]; 1162 1163 u8 reserved_at_120[0x18]; 1164 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1165 1166 u8 header_modify_sw_icm_start_address[0x40]; 1167 1168 u8 reserved_at_180[0x40]; 1169 1170 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1171 1172 u8 memic_operations[0x20]; 1173 1174 u8 reserved_at_220[0x5e0]; 1175 }; 1176 1177 struct mlx5_ifc_device_event_cap_bits { 1178 u8 user_affiliated_events[4][0x40]; 1179 1180 u8 user_unaffiliated_events[4][0x40]; 1181 }; 1182 1183 struct mlx5_ifc_virtio_emulation_cap_bits { 1184 u8 desc_tunnel_offload_type[0x1]; 1185 u8 eth_frame_offload_type[0x1]; 1186 u8 virtio_version_1_0[0x1]; 1187 u8 device_features_bits_mask[0xd]; 1188 u8 event_mode[0x8]; 1189 u8 virtio_queue_type[0x8]; 1190 1191 u8 max_tunnel_desc[0x10]; 1192 u8 reserved_at_30[0x3]; 1193 u8 log_doorbell_stride[0x5]; 1194 u8 reserved_at_38[0x3]; 1195 u8 log_doorbell_bar_size[0x5]; 1196 1197 u8 doorbell_bar_offset[0x40]; 1198 1199 u8 max_emulated_devices[0x8]; 1200 u8 max_num_virtio_queues[0x18]; 1201 1202 u8 reserved_at_a0[0x60]; 1203 1204 u8 umem_1_buffer_param_a[0x20]; 1205 1206 u8 umem_1_buffer_param_b[0x20]; 1207 1208 u8 umem_2_buffer_param_a[0x20]; 1209 1210 u8 umem_2_buffer_param_b[0x20]; 1211 1212 u8 umem_3_buffer_param_a[0x20]; 1213 1214 u8 umem_3_buffer_param_b[0x20]; 1215 1216 u8 reserved_at_1c0[0x640]; 1217 }; 1218 1219 enum { 1220 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1221 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1222 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1223 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1224 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1225 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1226 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1227 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1228 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1229 }; 1230 1231 enum { 1232 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1233 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1234 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1235 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1236 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1237 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1238 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1239 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1240 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1241 }; 1242 1243 struct mlx5_ifc_atomic_caps_bits { 1244 u8 reserved_at_0[0x40]; 1245 1246 u8 atomic_req_8B_endianness_mode[0x2]; 1247 u8 reserved_at_42[0x4]; 1248 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1249 1250 u8 reserved_at_47[0x19]; 1251 1252 u8 reserved_at_60[0x20]; 1253 1254 u8 reserved_at_80[0x10]; 1255 u8 atomic_operations[0x10]; 1256 1257 u8 reserved_at_a0[0x10]; 1258 u8 atomic_size_qp[0x10]; 1259 1260 u8 reserved_at_c0[0x10]; 1261 u8 atomic_size_dc[0x10]; 1262 1263 u8 reserved_at_e0[0x720]; 1264 }; 1265 1266 struct mlx5_ifc_odp_cap_bits { 1267 u8 reserved_at_0[0x40]; 1268 1269 u8 sig[0x1]; 1270 u8 reserved_at_41[0x1f]; 1271 1272 u8 reserved_at_60[0x20]; 1273 1274 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1275 1276 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1277 1278 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1279 1280 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1281 1282 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1283 1284 u8 reserved_at_120[0x6E0]; 1285 }; 1286 1287 struct mlx5_ifc_calc_op { 1288 u8 reserved_at_0[0x10]; 1289 u8 reserved_at_10[0x9]; 1290 u8 op_swap_endianness[0x1]; 1291 u8 op_min[0x1]; 1292 u8 op_xor[0x1]; 1293 u8 op_or[0x1]; 1294 u8 op_and[0x1]; 1295 u8 op_max[0x1]; 1296 u8 op_add[0x1]; 1297 }; 1298 1299 struct mlx5_ifc_vector_calc_cap_bits { 1300 u8 calc_matrix[0x1]; 1301 u8 reserved_at_1[0x1f]; 1302 u8 reserved_at_20[0x8]; 1303 u8 max_vec_count[0x8]; 1304 u8 reserved_at_30[0xd]; 1305 u8 max_chunk_size[0x3]; 1306 struct mlx5_ifc_calc_op calc0; 1307 struct mlx5_ifc_calc_op calc1; 1308 struct mlx5_ifc_calc_op calc2; 1309 struct mlx5_ifc_calc_op calc3; 1310 1311 u8 reserved_at_c0[0x720]; 1312 }; 1313 1314 struct mlx5_ifc_tls_cap_bits { 1315 u8 tls_1_2_aes_gcm_128[0x1]; 1316 u8 tls_1_3_aes_gcm_128[0x1]; 1317 u8 tls_1_2_aes_gcm_256[0x1]; 1318 u8 tls_1_3_aes_gcm_256[0x1]; 1319 u8 reserved_at_4[0x1c]; 1320 1321 u8 reserved_at_20[0x7e0]; 1322 }; 1323 1324 struct mlx5_ifc_ipsec_cap_bits { 1325 u8 ipsec_full_offload[0x1]; 1326 u8 ipsec_crypto_offload[0x1]; 1327 u8 ipsec_esn[0x1]; 1328 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1329 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1330 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1331 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1332 u8 reserved_at_7[0x4]; 1333 u8 log_max_ipsec_offload[0x5]; 1334 u8 reserved_at_10[0x10]; 1335 1336 u8 min_log_ipsec_full_replay_window[0x8]; 1337 u8 max_log_ipsec_full_replay_window[0x8]; 1338 u8 reserved_at_30[0x7d0]; 1339 }; 1340 1341 struct mlx5_ifc_macsec_cap_bits { 1342 u8 macsec_epn[0x1]; 1343 u8 reserved_at_1[0x2]; 1344 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1345 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1346 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1347 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1348 u8 reserved_at_7[0x4]; 1349 u8 log_max_macsec_offload[0x5]; 1350 u8 reserved_at_10[0x10]; 1351 1352 u8 min_log_macsec_full_replay_window[0x8]; 1353 u8 max_log_macsec_full_replay_window[0x8]; 1354 u8 reserved_at_30[0x10]; 1355 1356 u8 reserved_at_40[0x7c0]; 1357 }; 1358 1359 enum { 1360 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1361 MLX5_WQ_TYPE_CYCLIC = 0x1, 1362 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1363 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1364 }; 1365 1366 enum { 1367 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1368 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1369 }; 1370 1371 enum { 1372 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1373 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1374 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1375 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1376 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1377 }; 1378 1379 enum { 1380 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1381 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1382 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1383 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1384 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1385 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1386 }; 1387 1388 enum { 1389 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1390 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1391 }; 1392 1393 enum { 1394 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1395 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1396 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1397 }; 1398 1399 enum { 1400 MLX5_CAP_PORT_TYPE_IB = 0x0, 1401 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1402 }; 1403 1404 enum { 1405 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1406 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1407 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1408 }; 1409 1410 enum { 1411 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1412 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1413 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1414 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1415 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1416 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1417 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1418 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1419 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1420 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1421 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1422 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1423 }; 1424 1425 enum { 1426 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1427 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1428 }; 1429 1430 #define MLX5_FC_BULK_SIZE_FACTOR 128 1431 1432 enum mlx5_fc_bulk_alloc_bitmask { 1433 MLX5_FC_BULK_128 = (1 << 0), 1434 MLX5_FC_BULK_256 = (1 << 1), 1435 MLX5_FC_BULK_512 = (1 << 2), 1436 MLX5_FC_BULK_1024 = (1 << 3), 1437 MLX5_FC_BULK_2048 = (1 << 4), 1438 MLX5_FC_BULK_4096 = (1 << 5), 1439 MLX5_FC_BULK_8192 = (1 << 6), 1440 MLX5_FC_BULK_16384 = (1 << 7), 1441 }; 1442 1443 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1444 1445 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1446 1447 enum { 1448 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1449 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1450 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1451 }; 1452 1453 struct mlx5_ifc_cmd_hca_cap_bits { 1454 u8 reserved_at_0[0x10]; 1455 u8 shared_object_to_user_object_allowed[0x1]; 1456 u8 reserved_at_13[0xe]; 1457 u8 vhca_resource_manager[0x1]; 1458 1459 u8 hca_cap_2[0x1]; 1460 u8 create_lag_when_not_master_up[0x1]; 1461 u8 dtor[0x1]; 1462 u8 event_on_vhca_state_teardown_request[0x1]; 1463 u8 event_on_vhca_state_in_use[0x1]; 1464 u8 event_on_vhca_state_active[0x1]; 1465 u8 event_on_vhca_state_allocated[0x1]; 1466 u8 event_on_vhca_state_invalid[0x1]; 1467 u8 reserved_at_28[0x8]; 1468 u8 vhca_id[0x10]; 1469 1470 u8 reserved_at_40[0x40]; 1471 1472 u8 log_max_srq_sz[0x8]; 1473 u8 log_max_qp_sz[0x8]; 1474 u8 event_cap[0x1]; 1475 u8 reserved_at_91[0x2]; 1476 u8 isolate_vl_tc_new[0x1]; 1477 u8 reserved_at_94[0x4]; 1478 u8 prio_tag_required[0x1]; 1479 u8 reserved_at_99[0x2]; 1480 u8 log_max_qp[0x5]; 1481 1482 u8 reserved_at_a0[0x3]; 1483 u8 ece_support[0x1]; 1484 u8 reserved_at_a4[0x5]; 1485 u8 reg_c_preserve[0x1]; 1486 u8 reserved_at_aa[0x1]; 1487 u8 log_max_srq[0x5]; 1488 u8 reserved_at_b0[0x1]; 1489 u8 uplink_follow[0x1]; 1490 u8 ts_cqe_to_dest_cqn[0x1]; 1491 u8 reserved_at_b3[0x7]; 1492 u8 shampo[0x1]; 1493 u8 reserved_at_bb[0x5]; 1494 1495 u8 max_sgl_for_optimized_performance[0x8]; 1496 u8 log_max_cq_sz[0x8]; 1497 u8 relaxed_ordering_write_umr[0x1]; 1498 u8 relaxed_ordering_read_umr[0x1]; 1499 u8 reserved_at_d2[0x7]; 1500 u8 virtio_net_device_emualtion_manager[0x1]; 1501 u8 virtio_blk_device_emualtion_manager[0x1]; 1502 u8 log_max_cq[0x5]; 1503 1504 u8 log_max_eq_sz[0x8]; 1505 u8 relaxed_ordering_write[0x1]; 1506 u8 relaxed_ordering_read[0x1]; 1507 u8 log_max_mkey[0x6]; 1508 u8 reserved_at_f0[0x8]; 1509 u8 dump_fill_mkey[0x1]; 1510 u8 reserved_at_f9[0x2]; 1511 u8 fast_teardown[0x1]; 1512 u8 log_max_eq[0x4]; 1513 1514 u8 max_indirection[0x8]; 1515 u8 fixed_buffer_size[0x1]; 1516 u8 log_max_mrw_sz[0x7]; 1517 u8 force_teardown[0x1]; 1518 u8 reserved_at_111[0x1]; 1519 u8 log_max_bsf_list_size[0x6]; 1520 u8 umr_extended_translation_offset[0x1]; 1521 u8 null_mkey[0x1]; 1522 u8 log_max_klm_list_size[0x6]; 1523 1524 u8 reserved_at_120[0x2]; 1525 u8 qpc_extension[0x1]; 1526 u8 reserved_at_123[0x7]; 1527 u8 log_max_ra_req_dc[0x6]; 1528 u8 reserved_at_130[0x2]; 1529 u8 eth_wqe_too_small[0x1]; 1530 u8 reserved_at_133[0x6]; 1531 u8 vnic_env_cq_overrun[0x1]; 1532 u8 log_max_ra_res_dc[0x6]; 1533 1534 u8 reserved_at_140[0x5]; 1535 u8 release_all_pages[0x1]; 1536 u8 must_not_use[0x1]; 1537 u8 reserved_at_147[0x2]; 1538 u8 roce_accl[0x1]; 1539 u8 log_max_ra_req_qp[0x6]; 1540 u8 reserved_at_150[0xa]; 1541 u8 log_max_ra_res_qp[0x6]; 1542 1543 u8 end_pad[0x1]; 1544 u8 cc_query_allowed[0x1]; 1545 u8 cc_modify_allowed[0x1]; 1546 u8 start_pad[0x1]; 1547 u8 cache_line_128byte[0x1]; 1548 u8 reserved_at_165[0x4]; 1549 u8 rts2rts_qp_counters_set_id[0x1]; 1550 u8 reserved_at_16a[0x2]; 1551 u8 vnic_env_int_rq_oob[0x1]; 1552 u8 sbcam_reg[0x1]; 1553 u8 reserved_at_16e[0x1]; 1554 u8 qcam_reg[0x1]; 1555 u8 gid_table_size[0x10]; 1556 1557 u8 out_of_seq_cnt[0x1]; 1558 u8 vport_counters[0x1]; 1559 u8 retransmission_q_counters[0x1]; 1560 u8 debug[0x1]; 1561 u8 modify_rq_counter_set_id[0x1]; 1562 u8 rq_delay_drop[0x1]; 1563 u8 max_qp_cnt[0xa]; 1564 u8 pkey_table_size[0x10]; 1565 1566 u8 vport_group_manager[0x1]; 1567 u8 vhca_group_manager[0x1]; 1568 u8 ib_virt[0x1]; 1569 u8 eth_virt[0x1]; 1570 u8 vnic_env_queue_counters[0x1]; 1571 u8 ets[0x1]; 1572 u8 nic_flow_table[0x1]; 1573 u8 eswitch_manager[0x1]; 1574 u8 device_memory[0x1]; 1575 u8 mcam_reg[0x1]; 1576 u8 pcam_reg[0x1]; 1577 u8 local_ca_ack_delay[0x5]; 1578 u8 port_module_event[0x1]; 1579 u8 enhanced_error_q_counters[0x1]; 1580 u8 ports_check[0x1]; 1581 u8 reserved_at_1b3[0x1]; 1582 u8 disable_link_up[0x1]; 1583 u8 beacon_led[0x1]; 1584 u8 port_type[0x2]; 1585 u8 num_ports[0x8]; 1586 1587 u8 reserved_at_1c0[0x1]; 1588 u8 pps[0x1]; 1589 u8 pps_modify[0x1]; 1590 u8 log_max_msg[0x5]; 1591 u8 reserved_at_1c8[0x4]; 1592 u8 max_tc[0x4]; 1593 u8 temp_warn_event[0x1]; 1594 u8 dcbx[0x1]; 1595 u8 general_notification_event[0x1]; 1596 u8 reserved_at_1d3[0x2]; 1597 u8 fpga[0x1]; 1598 u8 rol_s[0x1]; 1599 u8 rol_g[0x1]; 1600 u8 reserved_at_1d8[0x1]; 1601 u8 wol_s[0x1]; 1602 u8 wol_g[0x1]; 1603 u8 wol_a[0x1]; 1604 u8 wol_b[0x1]; 1605 u8 wol_m[0x1]; 1606 u8 wol_u[0x1]; 1607 u8 wol_p[0x1]; 1608 1609 u8 stat_rate_support[0x10]; 1610 u8 reserved_at_1f0[0x1]; 1611 u8 pci_sync_for_fw_update_event[0x1]; 1612 u8 reserved_at_1f2[0x6]; 1613 u8 init2_lag_tx_port_affinity[0x1]; 1614 u8 reserved_at_1fa[0x3]; 1615 u8 cqe_version[0x4]; 1616 1617 u8 compact_address_vector[0x1]; 1618 u8 striding_rq[0x1]; 1619 u8 reserved_at_202[0x1]; 1620 u8 ipoib_enhanced_offloads[0x1]; 1621 u8 ipoib_basic_offloads[0x1]; 1622 u8 reserved_at_205[0x1]; 1623 u8 repeated_block_disabled[0x1]; 1624 u8 umr_modify_entity_size_disabled[0x1]; 1625 u8 umr_modify_atomic_disabled[0x1]; 1626 u8 umr_indirect_mkey_disabled[0x1]; 1627 u8 umr_fence[0x2]; 1628 u8 dc_req_scat_data_cqe[0x1]; 1629 u8 reserved_at_20d[0x2]; 1630 u8 drain_sigerr[0x1]; 1631 u8 cmdif_checksum[0x2]; 1632 u8 sigerr_cqe[0x1]; 1633 u8 reserved_at_213[0x1]; 1634 u8 wq_signature[0x1]; 1635 u8 sctr_data_cqe[0x1]; 1636 u8 reserved_at_216[0x1]; 1637 u8 sho[0x1]; 1638 u8 tph[0x1]; 1639 u8 rf[0x1]; 1640 u8 dct[0x1]; 1641 u8 qos[0x1]; 1642 u8 eth_net_offloads[0x1]; 1643 u8 roce[0x1]; 1644 u8 atomic[0x1]; 1645 u8 reserved_at_21f[0x1]; 1646 1647 u8 cq_oi[0x1]; 1648 u8 cq_resize[0x1]; 1649 u8 cq_moderation[0x1]; 1650 u8 reserved_at_223[0x3]; 1651 u8 cq_eq_remap[0x1]; 1652 u8 pg[0x1]; 1653 u8 block_lb_mc[0x1]; 1654 u8 reserved_at_229[0x1]; 1655 u8 scqe_break_moderation[0x1]; 1656 u8 cq_period_start_from_cqe[0x1]; 1657 u8 cd[0x1]; 1658 u8 reserved_at_22d[0x1]; 1659 u8 apm[0x1]; 1660 u8 vector_calc[0x1]; 1661 u8 umr_ptr_rlky[0x1]; 1662 u8 imaicl[0x1]; 1663 u8 qp_packet_based[0x1]; 1664 u8 reserved_at_233[0x3]; 1665 u8 qkv[0x1]; 1666 u8 pkv[0x1]; 1667 u8 set_deth_sqpn[0x1]; 1668 u8 reserved_at_239[0x3]; 1669 u8 xrc[0x1]; 1670 u8 ud[0x1]; 1671 u8 uc[0x1]; 1672 u8 rc[0x1]; 1673 1674 u8 uar_4k[0x1]; 1675 u8 reserved_at_241[0x9]; 1676 u8 uar_sz[0x6]; 1677 u8 port_selection_cap[0x1]; 1678 u8 reserved_at_248[0x1]; 1679 u8 umem_uid_0[0x1]; 1680 u8 reserved_at_250[0x5]; 1681 u8 log_pg_sz[0x8]; 1682 1683 u8 bf[0x1]; 1684 u8 driver_version[0x1]; 1685 u8 pad_tx_eth_packet[0x1]; 1686 u8 reserved_at_263[0x3]; 1687 u8 mkey_by_name[0x1]; 1688 u8 reserved_at_267[0x4]; 1689 1690 u8 log_bf_reg_size[0x5]; 1691 1692 u8 reserved_at_270[0x3]; 1693 u8 qp_error_syndrome[0x1]; 1694 u8 reserved_at_274[0x2]; 1695 u8 lag_dct[0x2]; 1696 u8 lag_tx_port_affinity[0x1]; 1697 u8 lag_native_fdb_selection[0x1]; 1698 u8 reserved_at_27a[0x1]; 1699 u8 lag_master[0x1]; 1700 u8 num_lag_ports[0x4]; 1701 1702 u8 reserved_at_280[0x10]; 1703 u8 max_wqe_sz_sq[0x10]; 1704 1705 u8 reserved_at_2a0[0x10]; 1706 u8 max_wqe_sz_rq[0x10]; 1707 1708 u8 max_flow_counter_31_16[0x10]; 1709 u8 max_wqe_sz_sq_dc[0x10]; 1710 1711 u8 reserved_at_2e0[0x7]; 1712 u8 max_qp_mcg[0x19]; 1713 1714 u8 reserved_at_300[0x10]; 1715 u8 flow_counter_bulk_alloc[0x8]; 1716 u8 log_max_mcg[0x8]; 1717 1718 u8 reserved_at_320[0x3]; 1719 u8 log_max_transport_domain[0x5]; 1720 u8 reserved_at_328[0x3]; 1721 u8 log_max_pd[0x5]; 1722 u8 reserved_at_330[0xb]; 1723 u8 log_max_xrcd[0x5]; 1724 1725 u8 nic_receive_steering_discard[0x1]; 1726 u8 receive_discard_vport_down[0x1]; 1727 u8 transmit_discard_vport_down[0x1]; 1728 u8 eq_overrun_count[0x1]; 1729 u8 reserved_at_344[0x1]; 1730 u8 invalid_command_count[0x1]; 1731 u8 quota_exceeded_count[0x1]; 1732 u8 reserved_at_347[0x1]; 1733 u8 log_max_flow_counter_bulk[0x8]; 1734 u8 max_flow_counter_15_0[0x10]; 1735 1736 1737 u8 reserved_at_360[0x3]; 1738 u8 log_max_rq[0x5]; 1739 u8 reserved_at_368[0x3]; 1740 u8 log_max_sq[0x5]; 1741 u8 reserved_at_370[0x3]; 1742 u8 log_max_tir[0x5]; 1743 u8 reserved_at_378[0x3]; 1744 u8 log_max_tis[0x5]; 1745 1746 u8 basic_cyclic_rcv_wqe[0x1]; 1747 u8 reserved_at_381[0x2]; 1748 u8 log_max_rmp[0x5]; 1749 u8 reserved_at_388[0x3]; 1750 u8 log_max_rqt[0x5]; 1751 u8 reserved_at_390[0x3]; 1752 u8 log_max_rqt_size[0x5]; 1753 u8 reserved_at_398[0x3]; 1754 u8 log_max_tis_per_sq[0x5]; 1755 1756 u8 ext_stride_num_range[0x1]; 1757 u8 roce_rw_supported[0x1]; 1758 u8 log_max_current_uc_list_wr_supported[0x1]; 1759 u8 log_max_stride_sz_rq[0x5]; 1760 u8 reserved_at_3a8[0x3]; 1761 u8 log_min_stride_sz_rq[0x5]; 1762 u8 reserved_at_3b0[0x3]; 1763 u8 log_max_stride_sz_sq[0x5]; 1764 u8 reserved_at_3b8[0x3]; 1765 u8 log_min_stride_sz_sq[0x5]; 1766 1767 u8 hairpin[0x1]; 1768 u8 reserved_at_3c1[0x2]; 1769 u8 log_max_hairpin_queues[0x5]; 1770 u8 reserved_at_3c8[0x3]; 1771 u8 log_max_hairpin_wq_data_sz[0x5]; 1772 u8 reserved_at_3d0[0x3]; 1773 u8 log_max_hairpin_num_packets[0x5]; 1774 u8 reserved_at_3d8[0x3]; 1775 u8 log_max_wq_sz[0x5]; 1776 1777 u8 nic_vport_change_event[0x1]; 1778 u8 disable_local_lb_uc[0x1]; 1779 u8 disable_local_lb_mc[0x1]; 1780 u8 log_min_hairpin_wq_data_sz[0x5]; 1781 u8 reserved_at_3e8[0x2]; 1782 u8 vhca_state[0x1]; 1783 u8 log_max_vlan_list[0x5]; 1784 u8 reserved_at_3f0[0x3]; 1785 u8 log_max_current_mc_list[0x5]; 1786 u8 reserved_at_3f8[0x3]; 1787 u8 log_max_current_uc_list[0x5]; 1788 1789 u8 general_obj_types[0x40]; 1790 1791 u8 sq_ts_format[0x2]; 1792 u8 rq_ts_format[0x2]; 1793 u8 steering_format_version[0x4]; 1794 u8 create_qp_start_hint[0x18]; 1795 1796 u8 reserved_at_460[0x1]; 1797 u8 ats[0x1]; 1798 u8 reserved_at_462[0x1]; 1799 u8 log_max_uctx[0x5]; 1800 u8 reserved_at_468[0x1]; 1801 u8 crypto[0x1]; 1802 u8 ipsec_offload[0x1]; 1803 u8 log_max_umem[0x5]; 1804 u8 max_num_eqs[0x10]; 1805 1806 u8 reserved_at_480[0x1]; 1807 u8 tls_tx[0x1]; 1808 u8 tls_rx[0x1]; 1809 u8 log_max_l2_table[0x5]; 1810 u8 reserved_at_488[0x8]; 1811 u8 log_uar_page_sz[0x10]; 1812 1813 u8 reserved_at_4a0[0x20]; 1814 u8 device_frequency_mhz[0x20]; 1815 u8 device_frequency_khz[0x20]; 1816 1817 u8 reserved_at_500[0x20]; 1818 u8 num_of_uars_per_page[0x20]; 1819 1820 u8 flex_parser_protocols[0x20]; 1821 1822 u8 max_geneve_tlv_options[0x8]; 1823 u8 reserved_at_568[0x3]; 1824 u8 max_geneve_tlv_option_data_len[0x5]; 1825 u8 reserved_at_570[0x9]; 1826 u8 adv_virtualization[0x1]; 1827 u8 reserved_at_57a[0x6]; 1828 1829 u8 reserved_at_580[0xb]; 1830 u8 log_max_dci_stream_channels[0x5]; 1831 u8 reserved_at_590[0x3]; 1832 u8 log_max_dci_errored_streams[0x5]; 1833 u8 reserved_at_598[0x8]; 1834 1835 u8 reserved_at_5a0[0x10]; 1836 u8 enhanced_cqe_compression[0x1]; 1837 u8 reserved_at_5b1[0x2]; 1838 u8 log_max_dek[0x5]; 1839 u8 reserved_at_5b8[0x4]; 1840 u8 mini_cqe_resp_stride_index[0x1]; 1841 u8 cqe_128_always[0x1]; 1842 u8 cqe_compression_128[0x1]; 1843 u8 cqe_compression[0x1]; 1844 1845 u8 cqe_compression_timeout[0x10]; 1846 u8 cqe_compression_max_num[0x10]; 1847 1848 u8 reserved_at_5e0[0x8]; 1849 u8 flex_parser_id_gtpu_dw_0[0x4]; 1850 u8 reserved_at_5ec[0x4]; 1851 u8 tag_matching[0x1]; 1852 u8 rndv_offload_rc[0x1]; 1853 u8 rndv_offload_dc[0x1]; 1854 u8 log_tag_matching_list_sz[0x5]; 1855 u8 reserved_at_5f8[0x3]; 1856 u8 log_max_xrq[0x5]; 1857 1858 u8 affiliate_nic_vport_criteria[0x8]; 1859 u8 native_port_num[0x8]; 1860 u8 num_vhca_ports[0x8]; 1861 u8 flex_parser_id_gtpu_teid[0x4]; 1862 u8 reserved_at_61c[0x2]; 1863 u8 sw_owner_id[0x1]; 1864 u8 reserved_at_61f[0x1]; 1865 1866 u8 max_num_of_monitor_counters[0x10]; 1867 u8 num_ppcnt_monitor_counters[0x10]; 1868 1869 u8 max_num_sf[0x10]; 1870 u8 num_q_monitor_counters[0x10]; 1871 1872 u8 reserved_at_660[0x20]; 1873 1874 u8 sf[0x1]; 1875 u8 sf_set_partition[0x1]; 1876 u8 reserved_at_682[0x1]; 1877 u8 log_max_sf[0x5]; 1878 u8 apu[0x1]; 1879 u8 reserved_at_689[0x4]; 1880 u8 migration[0x1]; 1881 u8 reserved_at_68e[0x2]; 1882 u8 log_min_sf_size[0x8]; 1883 u8 max_num_sf_partitions[0x8]; 1884 1885 u8 uctx_cap[0x20]; 1886 1887 u8 reserved_at_6c0[0x4]; 1888 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1889 u8 flex_parser_id_icmp_dw1[0x4]; 1890 u8 flex_parser_id_icmp_dw0[0x4]; 1891 u8 flex_parser_id_icmpv6_dw1[0x4]; 1892 u8 flex_parser_id_icmpv6_dw0[0x4]; 1893 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1894 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1895 1896 u8 max_num_match_definer[0x10]; 1897 u8 sf_base_id[0x10]; 1898 1899 u8 flex_parser_id_gtpu_dw_2[0x4]; 1900 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1901 u8 num_total_dynamic_vf_msix[0x18]; 1902 u8 reserved_at_720[0x14]; 1903 u8 dynamic_msix_table_size[0xc]; 1904 u8 reserved_at_740[0xc]; 1905 u8 min_dynamic_vf_msix_table_size[0x4]; 1906 u8 reserved_at_750[0x4]; 1907 u8 max_dynamic_vf_msix_table_size[0xc]; 1908 1909 u8 reserved_at_760[0x20]; 1910 u8 vhca_tunnel_commands[0x40]; 1911 u8 match_definer_format_supported[0x40]; 1912 }; 1913 1914 struct mlx5_ifc_cmd_hca_cap_2_bits { 1915 u8 reserved_at_0[0x80]; 1916 1917 u8 migratable[0x1]; 1918 u8 reserved_at_81[0x1f]; 1919 1920 u8 max_reformat_insert_size[0x8]; 1921 u8 max_reformat_insert_offset[0x8]; 1922 u8 max_reformat_remove_size[0x8]; 1923 u8 max_reformat_remove_offset[0x8]; 1924 1925 u8 reserved_at_c0[0x8]; 1926 u8 migration_multi_load[0x1]; 1927 u8 migration_tracking_state[0x1]; 1928 u8 reserved_at_ca[0x16]; 1929 1930 u8 reserved_at_e0[0xc0]; 1931 1932 u8 reserved_at_1a0[0xb]; 1933 u8 log_min_mkey_entity_size[0x5]; 1934 u8 reserved_at_1b0[0x10]; 1935 1936 u8 reserved_at_1c0[0x60]; 1937 1938 u8 reserved_at_220[0x1]; 1939 u8 sw_vhca_id_valid[0x1]; 1940 u8 sw_vhca_id[0xe]; 1941 u8 reserved_at_230[0x10]; 1942 1943 u8 reserved_at_240[0xb]; 1944 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1945 u8 reserved_at_250[0x10]; 1946 1947 u8 reserved_at_260[0x5a0]; 1948 }; 1949 1950 enum mlx5_ifc_flow_destination_type { 1951 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1952 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1953 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1954 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1955 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1956 }; 1957 1958 enum mlx5_flow_table_miss_action { 1959 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1960 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1961 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1962 }; 1963 1964 struct mlx5_ifc_dest_format_struct_bits { 1965 u8 destination_type[0x8]; 1966 u8 destination_id[0x18]; 1967 1968 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1969 u8 packet_reformat[0x1]; 1970 u8 reserved_at_22[0xe]; 1971 u8 destination_eswitch_owner_vhca_id[0x10]; 1972 }; 1973 1974 struct mlx5_ifc_flow_counter_list_bits { 1975 u8 flow_counter_id[0x20]; 1976 1977 u8 reserved_at_20[0x20]; 1978 }; 1979 1980 struct mlx5_ifc_extended_dest_format_bits { 1981 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1982 1983 u8 packet_reformat_id[0x20]; 1984 1985 u8 reserved_at_60[0x20]; 1986 }; 1987 1988 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1989 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1990 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1991 }; 1992 1993 struct mlx5_ifc_fte_match_param_bits { 1994 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1995 1996 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1997 1998 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1999 2000 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2001 2002 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2003 2004 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2005 2006 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2007 2008 u8 reserved_at_e00[0x200]; 2009 }; 2010 2011 enum { 2012 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2013 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2014 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2015 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2016 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2017 }; 2018 2019 struct mlx5_ifc_rx_hash_field_select_bits { 2020 u8 l3_prot_type[0x1]; 2021 u8 l4_prot_type[0x1]; 2022 u8 selected_fields[0x1e]; 2023 }; 2024 2025 enum { 2026 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2027 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2028 }; 2029 2030 enum { 2031 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2032 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2033 }; 2034 2035 struct mlx5_ifc_wq_bits { 2036 u8 wq_type[0x4]; 2037 u8 wq_signature[0x1]; 2038 u8 end_padding_mode[0x2]; 2039 u8 cd_slave[0x1]; 2040 u8 reserved_at_8[0x18]; 2041 2042 u8 hds_skip_first_sge[0x1]; 2043 u8 log2_hds_buf_size[0x3]; 2044 u8 reserved_at_24[0x7]; 2045 u8 page_offset[0x5]; 2046 u8 lwm[0x10]; 2047 2048 u8 reserved_at_40[0x8]; 2049 u8 pd[0x18]; 2050 2051 u8 reserved_at_60[0x8]; 2052 u8 uar_page[0x18]; 2053 2054 u8 dbr_addr[0x40]; 2055 2056 u8 hw_counter[0x20]; 2057 2058 u8 sw_counter[0x20]; 2059 2060 u8 reserved_at_100[0xc]; 2061 u8 log_wq_stride[0x4]; 2062 u8 reserved_at_110[0x3]; 2063 u8 log_wq_pg_sz[0x5]; 2064 u8 reserved_at_118[0x3]; 2065 u8 log_wq_sz[0x5]; 2066 2067 u8 dbr_umem_valid[0x1]; 2068 u8 wq_umem_valid[0x1]; 2069 u8 reserved_at_122[0x1]; 2070 u8 log_hairpin_num_packets[0x5]; 2071 u8 reserved_at_128[0x3]; 2072 u8 log_hairpin_data_sz[0x5]; 2073 2074 u8 reserved_at_130[0x4]; 2075 u8 log_wqe_num_of_strides[0x4]; 2076 u8 two_byte_shift_en[0x1]; 2077 u8 reserved_at_139[0x4]; 2078 u8 log_wqe_stride_size[0x3]; 2079 2080 u8 reserved_at_140[0x80]; 2081 2082 u8 headers_mkey[0x20]; 2083 2084 u8 shampo_enable[0x1]; 2085 u8 reserved_at_1e1[0x4]; 2086 u8 log_reservation_size[0x3]; 2087 u8 reserved_at_1e8[0x5]; 2088 u8 log_max_num_of_packets_per_reservation[0x3]; 2089 u8 reserved_at_1f0[0x6]; 2090 u8 log_headers_entry_size[0x2]; 2091 u8 reserved_at_1f8[0x4]; 2092 u8 log_headers_buffer_entry_num[0x4]; 2093 2094 u8 reserved_at_200[0x400]; 2095 2096 struct mlx5_ifc_cmd_pas_bits pas[]; 2097 }; 2098 2099 struct mlx5_ifc_rq_num_bits { 2100 u8 reserved_at_0[0x8]; 2101 u8 rq_num[0x18]; 2102 }; 2103 2104 struct mlx5_ifc_mac_address_layout_bits { 2105 u8 reserved_at_0[0x10]; 2106 u8 mac_addr_47_32[0x10]; 2107 2108 u8 mac_addr_31_0[0x20]; 2109 }; 2110 2111 struct mlx5_ifc_vlan_layout_bits { 2112 u8 reserved_at_0[0x14]; 2113 u8 vlan[0x0c]; 2114 2115 u8 reserved_at_20[0x20]; 2116 }; 2117 2118 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2119 u8 reserved_at_0[0xa0]; 2120 2121 u8 min_time_between_cnps[0x20]; 2122 2123 u8 reserved_at_c0[0x12]; 2124 u8 cnp_dscp[0x6]; 2125 u8 reserved_at_d8[0x4]; 2126 u8 cnp_prio_mode[0x1]; 2127 u8 cnp_802p_prio[0x3]; 2128 2129 u8 reserved_at_e0[0x720]; 2130 }; 2131 2132 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2133 u8 reserved_at_0[0x60]; 2134 2135 u8 reserved_at_60[0x4]; 2136 u8 clamp_tgt_rate[0x1]; 2137 u8 reserved_at_65[0x3]; 2138 u8 clamp_tgt_rate_after_time_inc[0x1]; 2139 u8 reserved_at_69[0x17]; 2140 2141 u8 reserved_at_80[0x20]; 2142 2143 u8 rpg_time_reset[0x20]; 2144 2145 u8 rpg_byte_reset[0x20]; 2146 2147 u8 rpg_threshold[0x20]; 2148 2149 u8 rpg_max_rate[0x20]; 2150 2151 u8 rpg_ai_rate[0x20]; 2152 2153 u8 rpg_hai_rate[0x20]; 2154 2155 u8 rpg_gd[0x20]; 2156 2157 u8 rpg_min_dec_fac[0x20]; 2158 2159 u8 rpg_min_rate[0x20]; 2160 2161 u8 reserved_at_1c0[0xe0]; 2162 2163 u8 rate_to_set_on_first_cnp[0x20]; 2164 2165 u8 dce_tcp_g[0x20]; 2166 2167 u8 dce_tcp_rtt[0x20]; 2168 2169 u8 rate_reduce_monitor_period[0x20]; 2170 2171 u8 reserved_at_320[0x20]; 2172 2173 u8 initial_alpha_value[0x20]; 2174 2175 u8 reserved_at_360[0x4a0]; 2176 }; 2177 2178 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2179 u8 reserved_at_0[0x80]; 2180 2181 u8 rppp_max_rps[0x20]; 2182 2183 u8 rpg_time_reset[0x20]; 2184 2185 u8 rpg_byte_reset[0x20]; 2186 2187 u8 rpg_threshold[0x20]; 2188 2189 u8 rpg_max_rate[0x20]; 2190 2191 u8 rpg_ai_rate[0x20]; 2192 2193 u8 rpg_hai_rate[0x20]; 2194 2195 u8 rpg_gd[0x20]; 2196 2197 u8 rpg_min_dec_fac[0x20]; 2198 2199 u8 rpg_min_rate[0x20]; 2200 2201 u8 reserved_at_1c0[0x640]; 2202 }; 2203 2204 enum { 2205 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2206 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2207 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2208 }; 2209 2210 struct mlx5_ifc_resize_field_select_bits { 2211 u8 resize_field_select[0x20]; 2212 }; 2213 2214 struct mlx5_ifc_resource_dump_bits { 2215 u8 more_dump[0x1]; 2216 u8 inline_dump[0x1]; 2217 u8 reserved_at_2[0xa]; 2218 u8 seq_num[0x4]; 2219 u8 segment_type[0x10]; 2220 2221 u8 reserved_at_20[0x10]; 2222 u8 vhca_id[0x10]; 2223 2224 u8 index1[0x20]; 2225 2226 u8 index2[0x20]; 2227 2228 u8 num_of_obj1[0x10]; 2229 u8 num_of_obj2[0x10]; 2230 2231 u8 reserved_at_a0[0x20]; 2232 2233 u8 device_opaque[0x40]; 2234 2235 u8 mkey[0x20]; 2236 2237 u8 size[0x20]; 2238 2239 u8 address[0x40]; 2240 2241 u8 inline_data[52][0x20]; 2242 }; 2243 2244 struct mlx5_ifc_resource_dump_menu_record_bits { 2245 u8 reserved_at_0[0x4]; 2246 u8 num_of_obj2_supports_active[0x1]; 2247 u8 num_of_obj2_supports_all[0x1]; 2248 u8 must_have_num_of_obj2[0x1]; 2249 u8 support_num_of_obj2[0x1]; 2250 u8 num_of_obj1_supports_active[0x1]; 2251 u8 num_of_obj1_supports_all[0x1]; 2252 u8 must_have_num_of_obj1[0x1]; 2253 u8 support_num_of_obj1[0x1]; 2254 u8 must_have_index2[0x1]; 2255 u8 support_index2[0x1]; 2256 u8 must_have_index1[0x1]; 2257 u8 support_index1[0x1]; 2258 u8 segment_type[0x10]; 2259 2260 u8 segment_name[4][0x20]; 2261 2262 u8 index1_name[4][0x20]; 2263 2264 u8 index2_name[4][0x20]; 2265 }; 2266 2267 struct mlx5_ifc_resource_dump_segment_header_bits { 2268 u8 length_dw[0x10]; 2269 u8 segment_type[0x10]; 2270 }; 2271 2272 struct mlx5_ifc_resource_dump_command_segment_bits { 2273 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2274 2275 u8 segment_called[0x10]; 2276 u8 vhca_id[0x10]; 2277 2278 u8 index1[0x20]; 2279 2280 u8 index2[0x20]; 2281 2282 u8 num_of_obj1[0x10]; 2283 u8 num_of_obj2[0x10]; 2284 }; 2285 2286 struct mlx5_ifc_resource_dump_error_segment_bits { 2287 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2288 2289 u8 reserved_at_20[0x10]; 2290 u8 syndrome_id[0x10]; 2291 2292 u8 reserved_at_40[0x40]; 2293 2294 u8 error[8][0x20]; 2295 }; 2296 2297 struct mlx5_ifc_resource_dump_info_segment_bits { 2298 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2299 2300 u8 reserved_at_20[0x18]; 2301 u8 dump_version[0x8]; 2302 2303 u8 hw_version[0x20]; 2304 2305 u8 fw_version[0x20]; 2306 }; 2307 2308 struct mlx5_ifc_resource_dump_menu_segment_bits { 2309 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2310 2311 u8 reserved_at_20[0x10]; 2312 u8 num_of_records[0x10]; 2313 2314 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2315 }; 2316 2317 struct mlx5_ifc_resource_dump_resource_segment_bits { 2318 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2319 2320 u8 reserved_at_20[0x20]; 2321 2322 u8 index1[0x20]; 2323 2324 u8 index2[0x20]; 2325 2326 u8 payload[][0x20]; 2327 }; 2328 2329 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2330 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2331 }; 2332 2333 struct mlx5_ifc_menu_resource_dump_response_bits { 2334 struct mlx5_ifc_resource_dump_info_segment_bits info; 2335 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2336 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2337 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2338 }; 2339 2340 enum { 2341 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2342 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2343 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2344 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2345 }; 2346 2347 struct mlx5_ifc_modify_field_select_bits { 2348 u8 modify_field_select[0x20]; 2349 }; 2350 2351 struct mlx5_ifc_field_select_r_roce_np_bits { 2352 u8 field_select_r_roce_np[0x20]; 2353 }; 2354 2355 struct mlx5_ifc_field_select_r_roce_rp_bits { 2356 u8 field_select_r_roce_rp[0x20]; 2357 }; 2358 2359 enum { 2360 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2361 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2362 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2363 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2364 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2365 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2366 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2367 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2368 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2369 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2370 }; 2371 2372 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2373 u8 field_select_8021qaurp[0x20]; 2374 }; 2375 2376 struct mlx5_ifc_phys_layer_cntrs_bits { 2377 u8 time_since_last_clear_high[0x20]; 2378 2379 u8 time_since_last_clear_low[0x20]; 2380 2381 u8 symbol_errors_high[0x20]; 2382 2383 u8 symbol_errors_low[0x20]; 2384 2385 u8 sync_headers_errors_high[0x20]; 2386 2387 u8 sync_headers_errors_low[0x20]; 2388 2389 u8 edpl_bip_errors_lane0_high[0x20]; 2390 2391 u8 edpl_bip_errors_lane0_low[0x20]; 2392 2393 u8 edpl_bip_errors_lane1_high[0x20]; 2394 2395 u8 edpl_bip_errors_lane1_low[0x20]; 2396 2397 u8 edpl_bip_errors_lane2_high[0x20]; 2398 2399 u8 edpl_bip_errors_lane2_low[0x20]; 2400 2401 u8 edpl_bip_errors_lane3_high[0x20]; 2402 2403 u8 edpl_bip_errors_lane3_low[0x20]; 2404 2405 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2406 2407 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2408 2409 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2410 2411 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2412 2413 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2414 2415 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2416 2417 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2418 2419 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2420 2421 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2422 2423 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2424 2425 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2426 2427 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2428 2429 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2430 2431 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2432 2433 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2434 2435 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2436 2437 u8 rs_fec_corrected_blocks_high[0x20]; 2438 2439 u8 rs_fec_corrected_blocks_low[0x20]; 2440 2441 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2442 2443 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2444 2445 u8 rs_fec_no_errors_blocks_high[0x20]; 2446 2447 u8 rs_fec_no_errors_blocks_low[0x20]; 2448 2449 u8 rs_fec_single_error_blocks_high[0x20]; 2450 2451 u8 rs_fec_single_error_blocks_low[0x20]; 2452 2453 u8 rs_fec_corrected_symbols_total_high[0x20]; 2454 2455 u8 rs_fec_corrected_symbols_total_low[0x20]; 2456 2457 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2458 2459 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2460 2461 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2462 2463 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2464 2465 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2466 2467 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2468 2469 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2470 2471 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2472 2473 u8 link_down_events[0x20]; 2474 2475 u8 successful_recovery_events[0x20]; 2476 2477 u8 reserved_at_640[0x180]; 2478 }; 2479 2480 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2481 u8 time_since_last_clear_high[0x20]; 2482 2483 u8 time_since_last_clear_low[0x20]; 2484 2485 u8 phy_received_bits_high[0x20]; 2486 2487 u8 phy_received_bits_low[0x20]; 2488 2489 u8 phy_symbol_errors_high[0x20]; 2490 2491 u8 phy_symbol_errors_low[0x20]; 2492 2493 u8 phy_corrected_bits_high[0x20]; 2494 2495 u8 phy_corrected_bits_low[0x20]; 2496 2497 u8 phy_corrected_bits_lane0_high[0x20]; 2498 2499 u8 phy_corrected_bits_lane0_low[0x20]; 2500 2501 u8 phy_corrected_bits_lane1_high[0x20]; 2502 2503 u8 phy_corrected_bits_lane1_low[0x20]; 2504 2505 u8 phy_corrected_bits_lane2_high[0x20]; 2506 2507 u8 phy_corrected_bits_lane2_low[0x20]; 2508 2509 u8 phy_corrected_bits_lane3_high[0x20]; 2510 2511 u8 phy_corrected_bits_lane3_low[0x20]; 2512 2513 u8 reserved_at_200[0x5c0]; 2514 }; 2515 2516 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2517 u8 symbol_error_counter[0x10]; 2518 2519 u8 link_error_recovery_counter[0x8]; 2520 2521 u8 link_downed_counter[0x8]; 2522 2523 u8 port_rcv_errors[0x10]; 2524 2525 u8 port_rcv_remote_physical_errors[0x10]; 2526 2527 u8 port_rcv_switch_relay_errors[0x10]; 2528 2529 u8 port_xmit_discards[0x10]; 2530 2531 u8 port_xmit_constraint_errors[0x8]; 2532 2533 u8 port_rcv_constraint_errors[0x8]; 2534 2535 u8 reserved_at_70[0x8]; 2536 2537 u8 link_overrun_errors[0x8]; 2538 2539 u8 reserved_at_80[0x10]; 2540 2541 u8 vl_15_dropped[0x10]; 2542 2543 u8 reserved_at_a0[0x80]; 2544 2545 u8 port_xmit_wait[0x20]; 2546 }; 2547 2548 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2549 u8 transmit_queue_high[0x20]; 2550 2551 u8 transmit_queue_low[0x20]; 2552 2553 u8 no_buffer_discard_uc_high[0x20]; 2554 2555 u8 no_buffer_discard_uc_low[0x20]; 2556 2557 u8 reserved_at_80[0x740]; 2558 }; 2559 2560 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2561 u8 wred_discard_high[0x20]; 2562 2563 u8 wred_discard_low[0x20]; 2564 2565 u8 ecn_marked_tc_high[0x20]; 2566 2567 u8 ecn_marked_tc_low[0x20]; 2568 2569 u8 reserved_at_80[0x740]; 2570 }; 2571 2572 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2573 u8 rx_octets_high[0x20]; 2574 2575 u8 rx_octets_low[0x20]; 2576 2577 u8 reserved_at_40[0xc0]; 2578 2579 u8 rx_frames_high[0x20]; 2580 2581 u8 rx_frames_low[0x20]; 2582 2583 u8 tx_octets_high[0x20]; 2584 2585 u8 tx_octets_low[0x20]; 2586 2587 u8 reserved_at_180[0xc0]; 2588 2589 u8 tx_frames_high[0x20]; 2590 2591 u8 tx_frames_low[0x20]; 2592 2593 u8 rx_pause_high[0x20]; 2594 2595 u8 rx_pause_low[0x20]; 2596 2597 u8 rx_pause_duration_high[0x20]; 2598 2599 u8 rx_pause_duration_low[0x20]; 2600 2601 u8 tx_pause_high[0x20]; 2602 2603 u8 tx_pause_low[0x20]; 2604 2605 u8 tx_pause_duration_high[0x20]; 2606 2607 u8 tx_pause_duration_low[0x20]; 2608 2609 u8 rx_pause_transition_high[0x20]; 2610 2611 u8 rx_pause_transition_low[0x20]; 2612 2613 u8 rx_discards_high[0x20]; 2614 2615 u8 rx_discards_low[0x20]; 2616 2617 u8 device_stall_minor_watermark_cnt_high[0x20]; 2618 2619 u8 device_stall_minor_watermark_cnt_low[0x20]; 2620 2621 u8 device_stall_critical_watermark_cnt_high[0x20]; 2622 2623 u8 device_stall_critical_watermark_cnt_low[0x20]; 2624 2625 u8 reserved_at_480[0x340]; 2626 }; 2627 2628 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2629 u8 port_transmit_wait_high[0x20]; 2630 2631 u8 port_transmit_wait_low[0x20]; 2632 2633 u8 reserved_at_40[0x100]; 2634 2635 u8 rx_buffer_almost_full_high[0x20]; 2636 2637 u8 rx_buffer_almost_full_low[0x20]; 2638 2639 u8 rx_buffer_full_high[0x20]; 2640 2641 u8 rx_buffer_full_low[0x20]; 2642 2643 u8 rx_icrc_encapsulated_high[0x20]; 2644 2645 u8 rx_icrc_encapsulated_low[0x20]; 2646 2647 u8 reserved_at_200[0x5c0]; 2648 }; 2649 2650 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2651 u8 dot3stats_alignment_errors_high[0x20]; 2652 2653 u8 dot3stats_alignment_errors_low[0x20]; 2654 2655 u8 dot3stats_fcs_errors_high[0x20]; 2656 2657 u8 dot3stats_fcs_errors_low[0x20]; 2658 2659 u8 dot3stats_single_collision_frames_high[0x20]; 2660 2661 u8 dot3stats_single_collision_frames_low[0x20]; 2662 2663 u8 dot3stats_multiple_collision_frames_high[0x20]; 2664 2665 u8 dot3stats_multiple_collision_frames_low[0x20]; 2666 2667 u8 dot3stats_sqe_test_errors_high[0x20]; 2668 2669 u8 dot3stats_sqe_test_errors_low[0x20]; 2670 2671 u8 dot3stats_deferred_transmissions_high[0x20]; 2672 2673 u8 dot3stats_deferred_transmissions_low[0x20]; 2674 2675 u8 dot3stats_late_collisions_high[0x20]; 2676 2677 u8 dot3stats_late_collisions_low[0x20]; 2678 2679 u8 dot3stats_excessive_collisions_high[0x20]; 2680 2681 u8 dot3stats_excessive_collisions_low[0x20]; 2682 2683 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2684 2685 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2686 2687 u8 dot3stats_carrier_sense_errors_high[0x20]; 2688 2689 u8 dot3stats_carrier_sense_errors_low[0x20]; 2690 2691 u8 dot3stats_frame_too_longs_high[0x20]; 2692 2693 u8 dot3stats_frame_too_longs_low[0x20]; 2694 2695 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2696 2697 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2698 2699 u8 dot3stats_symbol_errors_high[0x20]; 2700 2701 u8 dot3stats_symbol_errors_low[0x20]; 2702 2703 u8 dot3control_in_unknown_opcodes_high[0x20]; 2704 2705 u8 dot3control_in_unknown_opcodes_low[0x20]; 2706 2707 u8 dot3in_pause_frames_high[0x20]; 2708 2709 u8 dot3in_pause_frames_low[0x20]; 2710 2711 u8 dot3out_pause_frames_high[0x20]; 2712 2713 u8 dot3out_pause_frames_low[0x20]; 2714 2715 u8 reserved_at_400[0x3c0]; 2716 }; 2717 2718 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2719 u8 ether_stats_drop_events_high[0x20]; 2720 2721 u8 ether_stats_drop_events_low[0x20]; 2722 2723 u8 ether_stats_octets_high[0x20]; 2724 2725 u8 ether_stats_octets_low[0x20]; 2726 2727 u8 ether_stats_pkts_high[0x20]; 2728 2729 u8 ether_stats_pkts_low[0x20]; 2730 2731 u8 ether_stats_broadcast_pkts_high[0x20]; 2732 2733 u8 ether_stats_broadcast_pkts_low[0x20]; 2734 2735 u8 ether_stats_multicast_pkts_high[0x20]; 2736 2737 u8 ether_stats_multicast_pkts_low[0x20]; 2738 2739 u8 ether_stats_crc_align_errors_high[0x20]; 2740 2741 u8 ether_stats_crc_align_errors_low[0x20]; 2742 2743 u8 ether_stats_undersize_pkts_high[0x20]; 2744 2745 u8 ether_stats_undersize_pkts_low[0x20]; 2746 2747 u8 ether_stats_oversize_pkts_high[0x20]; 2748 2749 u8 ether_stats_oversize_pkts_low[0x20]; 2750 2751 u8 ether_stats_fragments_high[0x20]; 2752 2753 u8 ether_stats_fragments_low[0x20]; 2754 2755 u8 ether_stats_jabbers_high[0x20]; 2756 2757 u8 ether_stats_jabbers_low[0x20]; 2758 2759 u8 ether_stats_collisions_high[0x20]; 2760 2761 u8 ether_stats_collisions_low[0x20]; 2762 2763 u8 ether_stats_pkts64octets_high[0x20]; 2764 2765 u8 ether_stats_pkts64octets_low[0x20]; 2766 2767 u8 ether_stats_pkts65to127octets_high[0x20]; 2768 2769 u8 ether_stats_pkts65to127octets_low[0x20]; 2770 2771 u8 ether_stats_pkts128to255octets_high[0x20]; 2772 2773 u8 ether_stats_pkts128to255octets_low[0x20]; 2774 2775 u8 ether_stats_pkts256to511octets_high[0x20]; 2776 2777 u8 ether_stats_pkts256to511octets_low[0x20]; 2778 2779 u8 ether_stats_pkts512to1023octets_high[0x20]; 2780 2781 u8 ether_stats_pkts512to1023octets_low[0x20]; 2782 2783 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2784 2785 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2786 2787 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2788 2789 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2790 2791 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2792 2793 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2794 2795 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2796 2797 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2798 2799 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2800 2801 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2802 2803 u8 reserved_at_540[0x280]; 2804 }; 2805 2806 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2807 u8 if_in_octets_high[0x20]; 2808 2809 u8 if_in_octets_low[0x20]; 2810 2811 u8 if_in_ucast_pkts_high[0x20]; 2812 2813 u8 if_in_ucast_pkts_low[0x20]; 2814 2815 u8 if_in_discards_high[0x20]; 2816 2817 u8 if_in_discards_low[0x20]; 2818 2819 u8 if_in_errors_high[0x20]; 2820 2821 u8 if_in_errors_low[0x20]; 2822 2823 u8 if_in_unknown_protos_high[0x20]; 2824 2825 u8 if_in_unknown_protos_low[0x20]; 2826 2827 u8 if_out_octets_high[0x20]; 2828 2829 u8 if_out_octets_low[0x20]; 2830 2831 u8 if_out_ucast_pkts_high[0x20]; 2832 2833 u8 if_out_ucast_pkts_low[0x20]; 2834 2835 u8 if_out_discards_high[0x20]; 2836 2837 u8 if_out_discards_low[0x20]; 2838 2839 u8 if_out_errors_high[0x20]; 2840 2841 u8 if_out_errors_low[0x20]; 2842 2843 u8 if_in_multicast_pkts_high[0x20]; 2844 2845 u8 if_in_multicast_pkts_low[0x20]; 2846 2847 u8 if_in_broadcast_pkts_high[0x20]; 2848 2849 u8 if_in_broadcast_pkts_low[0x20]; 2850 2851 u8 if_out_multicast_pkts_high[0x20]; 2852 2853 u8 if_out_multicast_pkts_low[0x20]; 2854 2855 u8 if_out_broadcast_pkts_high[0x20]; 2856 2857 u8 if_out_broadcast_pkts_low[0x20]; 2858 2859 u8 reserved_at_340[0x480]; 2860 }; 2861 2862 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2863 u8 a_frames_transmitted_ok_high[0x20]; 2864 2865 u8 a_frames_transmitted_ok_low[0x20]; 2866 2867 u8 a_frames_received_ok_high[0x20]; 2868 2869 u8 a_frames_received_ok_low[0x20]; 2870 2871 u8 a_frame_check_sequence_errors_high[0x20]; 2872 2873 u8 a_frame_check_sequence_errors_low[0x20]; 2874 2875 u8 a_alignment_errors_high[0x20]; 2876 2877 u8 a_alignment_errors_low[0x20]; 2878 2879 u8 a_octets_transmitted_ok_high[0x20]; 2880 2881 u8 a_octets_transmitted_ok_low[0x20]; 2882 2883 u8 a_octets_received_ok_high[0x20]; 2884 2885 u8 a_octets_received_ok_low[0x20]; 2886 2887 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2888 2889 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2890 2891 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2892 2893 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2894 2895 u8 a_multicast_frames_received_ok_high[0x20]; 2896 2897 u8 a_multicast_frames_received_ok_low[0x20]; 2898 2899 u8 a_broadcast_frames_received_ok_high[0x20]; 2900 2901 u8 a_broadcast_frames_received_ok_low[0x20]; 2902 2903 u8 a_in_range_length_errors_high[0x20]; 2904 2905 u8 a_in_range_length_errors_low[0x20]; 2906 2907 u8 a_out_of_range_length_field_high[0x20]; 2908 2909 u8 a_out_of_range_length_field_low[0x20]; 2910 2911 u8 a_frame_too_long_errors_high[0x20]; 2912 2913 u8 a_frame_too_long_errors_low[0x20]; 2914 2915 u8 a_symbol_error_during_carrier_high[0x20]; 2916 2917 u8 a_symbol_error_during_carrier_low[0x20]; 2918 2919 u8 a_mac_control_frames_transmitted_high[0x20]; 2920 2921 u8 a_mac_control_frames_transmitted_low[0x20]; 2922 2923 u8 a_mac_control_frames_received_high[0x20]; 2924 2925 u8 a_mac_control_frames_received_low[0x20]; 2926 2927 u8 a_unsupported_opcodes_received_high[0x20]; 2928 2929 u8 a_unsupported_opcodes_received_low[0x20]; 2930 2931 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2932 2933 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2934 2935 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2936 2937 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2938 2939 u8 reserved_at_4c0[0x300]; 2940 }; 2941 2942 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2943 u8 life_time_counter_high[0x20]; 2944 2945 u8 life_time_counter_low[0x20]; 2946 2947 u8 rx_errors[0x20]; 2948 2949 u8 tx_errors[0x20]; 2950 2951 u8 l0_to_recovery_eieos[0x20]; 2952 2953 u8 l0_to_recovery_ts[0x20]; 2954 2955 u8 l0_to_recovery_framing[0x20]; 2956 2957 u8 l0_to_recovery_retrain[0x20]; 2958 2959 u8 crc_error_dllp[0x20]; 2960 2961 u8 crc_error_tlp[0x20]; 2962 2963 u8 tx_overflow_buffer_pkt_high[0x20]; 2964 2965 u8 tx_overflow_buffer_pkt_low[0x20]; 2966 2967 u8 outbound_stalled_reads[0x20]; 2968 2969 u8 outbound_stalled_writes[0x20]; 2970 2971 u8 outbound_stalled_reads_events[0x20]; 2972 2973 u8 outbound_stalled_writes_events[0x20]; 2974 2975 u8 reserved_at_200[0x5c0]; 2976 }; 2977 2978 struct mlx5_ifc_cmd_inter_comp_event_bits { 2979 u8 command_completion_vector[0x20]; 2980 2981 u8 reserved_at_20[0xc0]; 2982 }; 2983 2984 struct mlx5_ifc_stall_vl_event_bits { 2985 u8 reserved_at_0[0x18]; 2986 u8 port_num[0x1]; 2987 u8 reserved_at_19[0x3]; 2988 u8 vl[0x4]; 2989 2990 u8 reserved_at_20[0xa0]; 2991 }; 2992 2993 struct mlx5_ifc_db_bf_congestion_event_bits { 2994 u8 event_subtype[0x8]; 2995 u8 reserved_at_8[0x8]; 2996 u8 congestion_level[0x8]; 2997 u8 reserved_at_18[0x8]; 2998 2999 u8 reserved_at_20[0xa0]; 3000 }; 3001 3002 struct mlx5_ifc_gpio_event_bits { 3003 u8 reserved_at_0[0x60]; 3004 3005 u8 gpio_event_hi[0x20]; 3006 3007 u8 gpio_event_lo[0x20]; 3008 3009 u8 reserved_at_a0[0x40]; 3010 }; 3011 3012 struct mlx5_ifc_port_state_change_event_bits { 3013 u8 reserved_at_0[0x40]; 3014 3015 u8 port_num[0x4]; 3016 u8 reserved_at_44[0x1c]; 3017 3018 u8 reserved_at_60[0x80]; 3019 }; 3020 3021 struct mlx5_ifc_dropped_packet_logged_bits { 3022 u8 reserved_at_0[0xe0]; 3023 }; 3024 3025 struct mlx5_ifc_default_timeout_bits { 3026 u8 to_multiplier[0x3]; 3027 u8 reserved_at_3[0x9]; 3028 u8 to_value[0x14]; 3029 }; 3030 3031 struct mlx5_ifc_dtor_reg_bits { 3032 u8 reserved_at_0[0x20]; 3033 3034 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3035 3036 u8 reserved_at_40[0x60]; 3037 3038 struct mlx5_ifc_default_timeout_bits health_poll_to; 3039 3040 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3041 3042 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3043 3044 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3045 3046 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3047 3048 struct mlx5_ifc_default_timeout_bits tear_down_to; 3049 3050 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3051 3052 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3053 3054 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3055 3056 u8 reserved_at_1c0[0x40]; 3057 }; 3058 3059 enum { 3060 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3061 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3062 }; 3063 3064 struct mlx5_ifc_cq_error_bits { 3065 u8 reserved_at_0[0x8]; 3066 u8 cqn[0x18]; 3067 3068 u8 reserved_at_20[0x20]; 3069 3070 u8 reserved_at_40[0x18]; 3071 u8 syndrome[0x8]; 3072 3073 u8 reserved_at_60[0x80]; 3074 }; 3075 3076 struct mlx5_ifc_rdma_page_fault_event_bits { 3077 u8 bytes_committed[0x20]; 3078 3079 u8 r_key[0x20]; 3080 3081 u8 reserved_at_40[0x10]; 3082 u8 packet_len[0x10]; 3083 3084 u8 rdma_op_len[0x20]; 3085 3086 u8 rdma_va[0x40]; 3087 3088 u8 reserved_at_c0[0x5]; 3089 u8 rdma[0x1]; 3090 u8 write[0x1]; 3091 u8 requestor[0x1]; 3092 u8 qp_number[0x18]; 3093 }; 3094 3095 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3096 u8 bytes_committed[0x20]; 3097 3098 u8 reserved_at_20[0x10]; 3099 u8 wqe_index[0x10]; 3100 3101 u8 reserved_at_40[0x10]; 3102 u8 len[0x10]; 3103 3104 u8 reserved_at_60[0x60]; 3105 3106 u8 reserved_at_c0[0x5]; 3107 u8 rdma[0x1]; 3108 u8 write_read[0x1]; 3109 u8 requestor[0x1]; 3110 u8 qpn[0x18]; 3111 }; 3112 3113 struct mlx5_ifc_qp_events_bits { 3114 u8 reserved_at_0[0xa0]; 3115 3116 u8 type[0x8]; 3117 u8 reserved_at_a8[0x18]; 3118 3119 u8 reserved_at_c0[0x8]; 3120 u8 qpn_rqn_sqn[0x18]; 3121 }; 3122 3123 struct mlx5_ifc_dct_events_bits { 3124 u8 reserved_at_0[0xc0]; 3125 3126 u8 reserved_at_c0[0x8]; 3127 u8 dct_number[0x18]; 3128 }; 3129 3130 struct mlx5_ifc_comp_event_bits { 3131 u8 reserved_at_0[0xc0]; 3132 3133 u8 reserved_at_c0[0x8]; 3134 u8 cq_number[0x18]; 3135 }; 3136 3137 enum { 3138 MLX5_QPC_STATE_RST = 0x0, 3139 MLX5_QPC_STATE_INIT = 0x1, 3140 MLX5_QPC_STATE_RTR = 0x2, 3141 MLX5_QPC_STATE_RTS = 0x3, 3142 MLX5_QPC_STATE_SQER = 0x4, 3143 MLX5_QPC_STATE_ERR = 0x6, 3144 MLX5_QPC_STATE_SQD = 0x7, 3145 MLX5_QPC_STATE_SUSPENDED = 0x9, 3146 }; 3147 3148 enum { 3149 MLX5_QPC_ST_RC = 0x0, 3150 MLX5_QPC_ST_UC = 0x1, 3151 MLX5_QPC_ST_UD = 0x2, 3152 MLX5_QPC_ST_XRC = 0x3, 3153 MLX5_QPC_ST_DCI = 0x5, 3154 MLX5_QPC_ST_QP0 = 0x7, 3155 MLX5_QPC_ST_QP1 = 0x8, 3156 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3157 MLX5_QPC_ST_REG_UMR = 0xc, 3158 }; 3159 3160 enum { 3161 MLX5_QPC_PM_STATE_ARMED = 0x0, 3162 MLX5_QPC_PM_STATE_REARM = 0x1, 3163 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3164 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3165 }; 3166 3167 enum { 3168 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3169 }; 3170 3171 enum { 3172 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3173 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3174 }; 3175 3176 enum { 3177 MLX5_QPC_MTU_256_BYTES = 0x1, 3178 MLX5_QPC_MTU_512_BYTES = 0x2, 3179 MLX5_QPC_MTU_1K_BYTES = 0x3, 3180 MLX5_QPC_MTU_2K_BYTES = 0x4, 3181 MLX5_QPC_MTU_4K_BYTES = 0x5, 3182 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3183 }; 3184 3185 enum { 3186 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3187 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3188 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3189 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3190 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3191 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3192 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3193 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3194 }; 3195 3196 enum { 3197 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3198 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3199 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3200 }; 3201 3202 enum { 3203 MLX5_QPC_CS_RES_DISABLE = 0x0, 3204 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3205 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3206 }; 3207 3208 enum { 3209 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3210 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3211 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3212 }; 3213 3214 struct mlx5_ifc_qpc_bits { 3215 u8 state[0x4]; 3216 u8 lag_tx_port_affinity[0x4]; 3217 u8 st[0x8]; 3218 u8 reserved_at_10[0x2]; 3219 u8 isolate_vl_tc[0x1]; 3220 u8 pm_state[0x2]; 3221 u8 reserved_at_15[0x1]; 3222 u8 req_e2e_credit_mode[0x2]; 3223 u8 offload_type[0x4]; 3224 u8 end_padding_mode[0x2]; 3225 u8 reserved_at_1e[0x2]; 3226 3227 u8 wq_signature[0x1]; 3228 u8 block_lb_mc[0x1]; 3229 u8 atomic_like_write_en[0x1]; 3230 u8 latency_sensitive[0x1]; 3231 u8 reserved_at_24[0x1]; 3232 u8 drain_sigerr[0x1]; 3233 u8 reserved_at_26[0x2]; 3234 u8 pd[0x18]; 3235 3236 u8 mtu[0x3]; 3237 u8 log_msg_max[0x5]; 3238 u8 reserved_at_48[0x1]; 3239 u8 log_rq_size[0x4]; 3240 u8 log_rq_stride[0x3]; 3241 u8 no_sq[0x1]; 3242 u8 log_sq_size[0x4]; 3243 u8 reserved_at_55[0x3]; 3244 u8 ts_format[0x2]; 3245 u8 reserved_at_5a[0x1]; 3246 u8 rlky[0x1]; 3247 u8 ulp_stateless_offload_mode[0x4]; 3248 3249 u8 counter_set_id[0x8]; 3250 u8 uar_page[0x18]; 3251 3252 u8 reserved_at_80[0x8]; 3253 u8 user_index[0x18]; 3254 3255 u8 reserved_at_a0[0x3]; 3256 u8 log_page_size[0x5]; 3257 u8 remote_qpn[0x18]; 3258 3259 struct mlx5_ifc_ads_bits primary_address_path; 3260 3261 struct mlx5_ifc_ads_bits secondary_address_path; 3262 3263 u8 log_ack_req_freq[0x4]; 3264 u8 reserved_at_384[0x4]; 3265 u8 log_sra_max[0x3]; 3266 u8 reserved_at_38b[0x2]; 3267 u8 retry_count[0x3]; 3268 u8 rnr_retry[0x3]; 3269 u8 reserved_at_393[0x1]; 3270 u8 fre[0x1]; 3271 u8 cur_rnr_retry[0x3]; 3272 u8 cur_retry_count[0x3]; 3273 u8 reserved_at_39b[0x5]; 3274 3275 u8 reserved_at_3a0[0x20]; 3276 3277 u8 reserved_at_3c0[0x8]; 3278 u8 next_send_psn[0x18]; 3279 3280 u8 reserved_at_3e0[0x3]; 3281 u8 log_num_dci_stream_channels[0x5]; 3282 u8 cqn_snd[0x18]; 3283 3284 u8 reserved_at_400[0x3]; 3285 u8 log_num_dci_errored_streams[0x5]; 3286 u8 deth_sqpn[0x18]; 3287 3288 u8 reserved_at_420[0x20]; 3289 3290 u8 reserved_at_440[0x8]; 3291 u8 last_acked_psn[0x18]; 3292 3293 u8 reserved_at_460[0x8]; 3294 u8 ssn[0x18]; 3295 3296 u8 reserved_at_480[0x8]; 3297 u8 log_rra_max[0x3]; 3298 u8 reserved_at_48b[0x1]; 3299 u8 atomic_mode[0x4]; 3300 u8 rre[0x1]; 3301 u8 rwe[0x1]; 3302 u8 rae[0x1]; 3303 u8 reserved_at_493[0x1]; 3304 u8 page_offset[0x6]; 3305 u8 reserved_at_49a[0x3]; 3306 u8 cd_slave_receive[0x1]; 3307 u8 cd_slave_send[0x1]; 3308 u8 cd_master[0x1]; 3309 3310 u8 reserved_at_4a0[0x3]; 3311 u8 min_rnr_nak[0x5]; 3312 u8 next_rcv_psn[0x18]; 3313 3314 u8 reserved_at_4c0[0x8]; 3315 u8 xrcd[0x18]; 3316 3317 u8 reserved_at_4e0[0x8]; 3318 u8 cqn_rcv[0x18]; 3319 3320 u8 dbr_addr[0x40]; 3321 3322 u8 q_key[0x20]; 3323 3324 u8 reserved_at_560[0x5]; 3325 u8 rq_type[0x3]; 3326 u8 srqn_rmpn_xrqn[0x18]; 3327 3328 u8 reserved_at_580[0x8]; 3329 u8 rmsn[0x18]; 3330 3331 u8 hw_sq_wqebb_counter[0x10]; 3332 u8 sw_sq_wqebb_counter[0x10]; 3333 3334 u8 hw_rq_counter[0x20]; 3335 3336 u8 sw_rq_counter[0x20]; 3337 3338 u8 reserved_at_600[0x20]; 3339 3340 u8 reserved_at_620[0xf]; 3341 u8 cgs[0x1]; 3342 u8 cs_req[0x8]; 3343 u8 cs_res[0x8]; 3344 3345 u8 dc_access_key[0x40]; 3346 3347 u8 reserved_at_680[0x3]; 3348 u8 dbr_umem_valid[0x1]; 3349 3350 u8 reserved_at_684[0xbc]; 3351 }; 3352 3353 struct mlx5_ifc_roce_addr_layout_bits { 3354 u8 source_l3_address[16][0x8]; 3355 3356 u8 reserved_at_80[0x3]; 3357 u8 vlan_valid[0x1]; 3358 u8 vlan_id[0xc]; 3359 u8 source_mac_47_32[0x10]; 3360 3361 u8 source_mac_31_0[0x20]; 3362 3363 u8 reserved_at_c0[0x14]; 3364 u8 roce_l3_type[0x4]; 3365 u8 roce_version[0x8]; 3366 3367 u8 reserved_at_e0[0x20]; 3368 }; 3369 3370 struct mlx5_ifc_shampo_cap_bits { 3371 u8 reserved_at_0[0x3]; 3372 u8 shampo_log_max_reservation_size[0x5]; 3373 u8 reserved_at_8[0x3]; 3374 u8 shampo_log_min_reservation_size[0x5]; 3375 u8 shampo_min_mss_size[0x10]; 3376 3377 u8 reserved_at_20[0x3]; 3378 u8 shampo_max_log_headers_entry_size[0x5]; 3379 u8 reserved_at_28[0x18]; 3380 3381 u8 reserved_at_40[0x7c0]; 3382 }; 3383 3384 struct mlx5_ifc_crypto_cap_bits { 3385 u8 reserved_at_0[0x3]; 3386 u8 synchronize_dek[0x1]; 3387 u8 int_kek_manual[0x1]; 3388 u8 int_kek_auto[0x1]; 3389 u8 reserved_at_6[0x1a]; 3390 3391 u8 reserved_at_20[0x3]; 3392 u8 log_dek_max_alloc[0x5]; 3393 u8 reserved_at_28[0x3]; 3394 u8 log_max_num_deks[0x5]; 3395 u8 reserved_at_30[0x10]; 3396 3397 u8 reserved_at_40[0x20]; 3398 3399 u8 reserved_at_60[0x3]; 3400 u8 log_dek_granularity[0x5]; 3401 u8 reserved_at_68[0x3]; 3402 u8 log_max_num_int_kek[0x5]; 3403 u8 sw_wrapped_dek[0x10]; 3404 3405 u8 reserved_at_80[0x780]; 3406 }; 3407 3408 union mlx5_ifc_hca_cap_union_bits { 3409 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3410 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3411 struct mlx5_ifc_odp_cap_bits odp_cap; 3412 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3413 struct mlx5_ifc_roce_cap_bits roce_cap; 3414 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3415 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3416 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3417 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3418 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3419 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3420 struct mlx5_ifc_qos_cap_bits qos_cap; 3421 struct mlx5_ifc_debug_cap_bits debug_cap; 3422 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3423 struct mlx5_ifc_tls_cap_bits tls_cap; 3424 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3425 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3426 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3427 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3428 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3429 u8 reserved_at_0[0x8000]; 3430 }; 3431 3432 enum { 3433 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3434 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3435 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3436 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3437 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3438 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3439 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3440 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3441 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3442 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3443 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3444 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3445 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3446 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3447 }; 3448 3449 enum { 3450 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3451 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3452 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3453 }; 3454 3455 enum { 3456 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3457 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3458 }; 3459 3460 struct mlx5_ifc_vlan_bits { 3461 u8 ethtype[0x10]; 3462 u8 prio[0x3]; 3463 u8 cfi[0x1]; 3464 u8 vid[0xc]; 3465 }; 3466 3467 enum { 3468 MLX5_FLOW_METER_COLOR_RED = 0x0, 3469 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3470 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3471 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3472 }; 3473 3474 enum { 3475 MLX5_EXE_ASO_FLOW_METER = 0x2, 3476 }; 3477 3478 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3479 u8 return_reg_id[0x4]; 3480 u8 aso_type[0x4]; 3481 u8 reserved_at_8[0x14]; 3482 u8 action[0x1]; 3483 u8 init_color[0x2]; 3484 u8 meter_id[0x1]; 3485 }; 3486 3487 union mlx5_ifc_exe_aso_ctrl { 3488 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3489 }; 3490 3491 struct mlx5_ifc_execute_aso_bits { 3492 u8 valid[0x1]; 3493 u8 reserved_at_1[0x7]; 3494 u8 aso_object_id[0x18]; 3495 3496 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3497 }; 3498 3499 struct mlx5_ifc_flow_context_bits { 3500 struct mlx5_ifc_vlan_bits push_vlan; 3501 3502 u8 group_id[0x20]; 3503 3504 u8 reserved_at_40[0x8]; 3505 u8 flow_tag[0x18]; 3506 3507 u8 reserved_at_60[0x10]; 3508 u8 action[0x10]; 3509 3510 u8 extended_destination[0x1]; 3511 u8 reserved_at_81[0x1]; 3512 u8 flow_source[0x2]; 3513 u8 encrypt_decrypt_type[0x4]; 3514 u8 destination_list_size[0x18]; 3515 3516 u8 reserved_at_a0[0x8]; 3517 u8 flow_counter_list_size[0x18]; 3518 3519 u8 packet_reformat_id[0x20]; 3520 3521 u8 modify_header_id[0x20]; 3522 3523 struct mlx5_ifc_vlan_bits push_vlan_2; 3524 3525 u8 encrypt_decrypt_obj_id[0x20]; 3526 u8 reserved_at_140[0xc0]; 3527 3528 struct mlx5_ifc_fte_match_param_bits match_value; 3529 3530 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3531 3532 u8 reserved_at_1300[0x500]; 3533 3534 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3535 }; 3536 3537 enum { 3538 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3539 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3540 }; 3541 3542 struct mlx5_ifc_xrc_srqc_bits { 3543 u8 state[0x4]; 3544 u8 log_xrc_srq_size[0x4]; 3545 u8 reserved_at_8[0x18]; 3546 3547 u8 wq_signature[0x1]; 3548 u8 cont_srq[0x1]; 3549 u8 reserved_at_22[0x1]; 3550 u8 rlky[0x1]; 3551 u8 basic_cyclic_rcv_wqe[0x1]; 3552 u8 log_rq_stride[0x3]; 3553 u8 xrcd[0x18]; 3554 3555 u8 page_offset[0x6]; 3556 u8 reserved_at_46[0x1]; 3557 u8 dbr_umem_valid[0x1]; 3558 u8 cqn[0x18]; 3559 3560 u8 reserved_at_60[0x20]; 3561 3562 u8 user_index_equal_xrc_srqn[0x1]; 3563 u8 reserved_at_81[0x1]; 3564 u8 log_page_size[0x6]; 3565 u8 user_index[0x18]; 3566 3567 u8 reserved_at_a0[0x20]; 3568 3569 u8 reserved_at_c0[0x8]; 3570 u8 pd[0x18]; 3571 3572 u8 lwm[0x10]; 3573 u8 wqe_cnt[0x10]; 3574 3575 u8 reserved_at_100[0x40]; 3576 3577 u8 db_record_addr_h[0x20]; 3578 3579 u8 db_record_addr_l[0x1e]; 3580 u8 reserved_at_17e[0x2]; 3581 3582 u8 reserved_at_180[0x80]; 3583 }; 3584 3585 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3586 u8 counter_error_queues[0x20]; 3587 3588 u8 total_error_queues[0x20]; 3589 3590 u8 send_queue_priority_update_flow[0x20]; 3591 3592 u8 reserved_at_60[0x20]; 3593 3594 u8 nic_receive_steering_discard[0x40]; 3595 3596 u8 receive_discard_vport_down[0x40]; 3597 3598 u8 transmit_discard_vport_down[0x40]; 3599 3600 u8 async_eq_overrun[0x20]; 3601 3602 u8 comp_eq_overrun[0x20]; 3603 3604 u8 reserved_at_180[0x20]; 3605 3606 u8 invalid_command[0x20]; 3607 3608 u8 quota_exceeded_command[0x20]; 3609 3610 u8 internal_rq_out_of_buffer[0x20]; 3611 3612 u8 cq_overrun[0x20]; 3613 3614 u8 eth_wqe_too_small[0x20]; 3615 3616 u8 reserved_at_220[0xdc0]; 3617 }; 3618 3619 struct mlx5_ifc_traffic_counter_bits { 3620 u8 packets[0x40]; 3621 3622 u8 octets[0x40]; 3623 }; 3624 3625 struct mlx5_ifc_tisc_bits { 3626 u8 strict_lag_tx_port_affinity[0x1]; 3627 u8 tls_en[0x1]; 3628 u8 reserved_at_2[0x2]; 3629 u8 lag_tx_port_affinity[0x04]; 3630 3631 u8 reserved_at_8[0x4]; 3632 u8 prio[0x4]; 3633 u8 reserved_at_10[0x10]; 3634 3635 u8 reserved_at_20[0x100]; 3636 3637 u8 reserved_at_120[0x8]; 3638 u8 transport_domain[0x18]; 3639 3640 u8 reserved_at_140[0x8]; 3641 u8 underlay_qpn[0x18]; 3642 3643 u8 reserved_at_160[0x8]; 3644 u8 pd[0x18]; 3645 3646 u8 reserved_at_180[0x380]; 3647 }; 3648 3649 enum { 3650 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3651 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3652 }; 3653 3654 enum { 3655 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3656 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3657 }; 3658 3659 enum { 3660 MLX5_RX_HASH_FN_NONE = 0x0, 3661 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3662 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3663 }; 3664 3665 enum { 3666 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3667 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3668 }; 3669 3670 struct mlx5_ifc_tirc_bits { 3671 u8 reserved_at_0[0x20]; 3672 3673 u8 disp_type[0x4]; 3674 u8 tls_en[0x1]; 3675 u8 reserved_at_25[0x1b]; 3676 3677 u8 reserved_at_40[0x40]; 3678 3679 u8 reserved_at_80[0x4]; 3680 u8 lro_timeout_period_usecs[0x10]; 3681 u8 packet_merge_mask[0x4]; 3682 u8 lro_max_ip_payload_size[0x8]; 3683 3684 u8 reserved_at_a0[0x40]; 3685 3686 u8 reserved_at_e0[0x8]; 3687 u8 inline_rqn[0x18]; 3688 3689 u8 rx_hash_symmetric[0x1]; 3690 u8 reserved_at_101[0x1]; 3691 u8 tunneled_offload_en[0x1]; 3692 u8 reserved_at_103[0x5]; 3693 u8 indirect_table[0x18]; 3694 3695 u8 rx_hash_fn[0x4]; 3696 u8 reserved_at_124[0x2]; 3697 u8 self_lb_block[0x2]; 3698 u8 transport_domain[0x18]; 3699 3700 u8 rx_hash_toeplitz_key[10][0x20]; 3701 3702 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3703 3704 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3705 3706 u8 reserved_at_2c0[0x4c0]; 3707 }; 3708 3709 enum { 3710 MLX5_SRQC_STATE_GOOD = 0x0, 3711 MLX5_SRQC_STATE_ERROR = 0x1, 3712 }; 3713 3714 struct mlx5_ifc_srqc_bits { 3715 u8 state[0x4]; 3716 u8 log_srq_size[0x4]; 3717 u8 reserved_at_8[0x18]; 3718 3719 u8 wq_signature[0x1]; 3720 u8 cont_srq[0x1]; 3721 u8 reserved_at_22[0x1]; 3722 u8 rlky[0x1]; 3723 u8 reserved_at_24[0x1]; 3724 u8 log_rq_stride[0x3]; 3725 u8 xrcd[0x18]; 3726 3727 u8 page_offset[0x6]; 3728 u8 reserved_at_46[0x2]; 3729 u8 cqn[0x18]; 3730 3731 u8 reserved_at_60[0x20]; 3732 3733 u8 reserved_at_80[0x2]; 3734 u8 log_page_size[0x6]; 3735 u8 reserved_at_88[0x18]; 3736 3737 u8 reserved_at_a0[0x20]; 3738 3739 u8 reserved_at_c0[0x8]; 3740 u8 pd[0x18]; 3741 3742 u8 lwm[0x10]; 3743 u8 wqe_cnt[0x10]; 3744 3745 u8 reserved_at_100[0x40]; 3746 3747 u8 dbr_addr[0x40]; 3748 3749 u8 reserved_at_180[0x80]; 3750 }; 3751 3752 enum { 3753 MLX5_SQC_STATE_RST = 0x0, 3754 MLX5_SQC_STATE_RDY = 0x1, 3755 MLX5_SQC_STATE_ERR = 0x3, 3756 }; 3757 3758 struct mlx5_ifc_sqc_bits { 3759 u8 rlky[0x1]; 3760 u8 cd_master[0x1]; 3761 u8 fre[0x1]; 3762 u8 flush_in_error_en[0x1]; 3763 u8 allow_multi_pkt_send_wqe[0x1]; 3764 u8 min_wqe_inline_mode[0x3]; 3765 u8 state[0x4]; 3766 u8 reg_umr[0x1]; 3767 u8 allow_swp[0x1]; 3768 u8 hairpin[0x1]; 3769 u8 reserved_at_f[0xb]; 3770 u8 ts_format[0x2]; 3771 u8 reserved_at_1c[0x4]; 3772 3773 u8 reserved_at_20[0x8]; 3774 u8 user_index[0x18]; 3775 3776 u8 reserved_at_40[0x8]; 3777 u8 cqn[0x18]; 3778 3779 u8 reserved_at_60[0x8]; 3780 u8 hairpin_peer_rq[0x18]; 3781 3782 u8 reserved_at_80[0x10]; 3783 u8 hairpin_peer_vhca[0x10]; 3784 3785 u8 reserved_at_a0[0x20]; 3786 3787 u8 reserved_at_c0[0x8]; 3788 u8 ts_cqe_to_dest_cqn[0x18]; 3789 3790 u8 reserved_at_e0[0x10]; 3791 u8 packet_pacing_rate_limit_index[0x10]; 3792 u8 tis_lst_sz[0x10]; 3793 u8 qos_queue_group_id[0x10]; 3794 3795 u8 reserved_at_120[0x40]; 3796 3797 u8 reserved_at_160[0x8]; 3798 u8 tis_num_0[0x18]; 3799 3800 struct mlx5_ifc_wq_bits wq; 3801 }; 3802 3803 enum { 3804 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3805 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3806 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3807 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3808 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3809 }; 3810 3811 enum { 3812 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3813 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3814 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3815 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3816 }; 3817 3818 struct mlx5_ifc_scheduling_context_bits { 3819 u8 element_type[0x8]; 3820 u8 reserved_at_8[0x18]; 3821 3822 u8 element_attributes[0x20]; 3823 3824 u8 parent_element_id[0x20]; 3825 3826 u8 reserved_at_60[0x40]; 3827 3828 u8 bw_share[0x20]; 3829 3830 u8 max_average_bw[0x20]; 3831 3832 u8 reserved_at_e0[0x120]; 3833 }; 3834 3835 struct mlx5_ifc_rqtc_bits { 3836 u8 reserved_at_0[0xa0]; 3837 3838 u8 reserved_at_a0[0x5]; 3839 u8 list_q_type[0x3]; 3840 u8 reserved_at_a8[0x8]; 3841 u8 rqt_max_size[0x10]; 3842 3843 u8 rq_vhca_id_format[0x1]; 3844 u8 reserved_at_c1[0xf]; 3845 u8 rqt_actual_size[0x10]; 3846 3847 u8 reserved_at_e0[0x6a0]; 3848 3849 struct mlx5_ifc_rq_num_bits rq_num[]; 3850 }; 3851 3852 enum { 3853 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3854 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3855 }; 3856 3857 enum { 3858 MLX5_RQC_STATE_RST = 0x0, 3859 MLX5_RQC_STATE_RDY = 0x1, 3860 MLX5_RQC_STATE_ERR = 0x3, 3861 }; 3862 3863 enum { 3864 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3865 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3866 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3867 }; 3868 3869 enum { 3870 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3871 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3872 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3873 }; 3874 3875 struct mlx5_ifc_rqc_bits { 3876 u8 rlky[0x1]; 3877 u8 delay_drop_en[0x1]; 3878 u8 scatter_fcs[0x1]; 3879 u8 vsd[0x1]; 3880 u8 mem_rq_type[0x4]; 3881 u8 state[0x4]; 3882 u8 reserved_at_c[0x1]; 3883 u8 flush_in_error_en[0x1]; 3884 u8 hairpin[0x1]; 3885 u8 reserved_at_f[0xb]; 3886 u8 ts_format[0x2]; 3887 u8 reserved_at_1c[0x4]; 3888 3889 u8 reserved_at_20[0x8]; 3890 u8 user_index[0x18]; 3891 3892 u8 reserved_at_40[0x8]; 3893 u8 cqn[0x18]; 3894 3895 u8 counter_set_id[0x8]; 3896 u8 reserved_at_68[0x18]; 3897 3898 u8 reserved_at_80[0x8]; 3899 u8 rmpn[0x18]; 3900 3901 u8 reserved_at_a0[0x8]; 3902 u8 hairpin_peer_sq[0x18]; 3903 3904 u8 reserved_at_c0[0x10]; 3905 u8 hairpin_peer_vhca[0x10]; 3906 3907 u8 reserved_at_e0[0x46]; 3908 u8 shampo_no_match_alignment_granularity[0x2]; 3909 u8 reserved_at_128[0x6]; 3910 u8 shampo_match_criteria_type[0x2]; 3911 u8 reservation_timeout[0x10]; 3912 3913 u8 reserved_at_140[0x40]; 3914 3915 struct mlx5_ifc_wq_bits wq; 3916 }; 3917 3918 enum { 3919 MLX5_RMPC_STATE_RDY = 0x1, 3920 MLX5_RMPC_STATE_ERR = 0x3, 3921 }; 3922 3923 struct mlx5_ifc_rmpc_bits { 3924 u8 reserved_at_0[0x8]; 3925 u8 state[0x4]; 3926 u8 reserved_at_c[0x14]; 3927 3928 u8 basic_cyclic_rcv_wqe[0x1]; 3929 u8 reserved_at_21[0x1f]; 3930 3931 u8 reserved_at_40[0x140]; 3932 3933 struct mlx5_ifc_wq_bits wq; 3934 }; 3935 3936 enum { 3937 VHCA_ID_TYPE_HW = 0, 3938 VHCA_ID_TYPE_SW = 1, 3939 }; 3940 3941 struct mlx5_ifc_nic_vport_context_bits { 3942 u8 reserved_at_0[0x5]; 3943 u8 min_wqe_inline_mode[0x3]; 3944 u8 reserved_at_8[0x15]; 3945 u8 disable_mc_local_lb[0x1]; 3946 u8 disable_uc_local_lb[0x1]; 3947 u8 roce_en[0x1]; 3948 3949 u8 arm_change_event[0x1]; 3950 u8 reserved_at_21[0x1a]; 3951 u8 event_on_mtu[0x1]; 3952 u8 event_on_promisc_change[0x1]; 3953 u8 event_on_vlan_change[0x1]; 3954 u8 event_on_mc_address_change[0x1]; 3955 u8 event_on_uc_address_change[0x1]; 3956 3957 u8 vhca_id_type[0x1]; 3958 u8 reserved_at_41[0xb]; 3959 u8 affiliation_criteria[0x4]; 3960 u8 affiliated_vhca_id[0x10]; 3961 3962 u8 reserved_at_60[0xd0]; 3963 3964 u8 mtu[0x10]; 3965 3966 u8 system_image_guid[0x40]; 3967 u8 port_guid[0x40]; 3968 u8 node_guid[0x40]; 3969 3970 u8 reserved_at_200[0x140]; 3971 u8 qkey_violation_counter[0x10]; 3972 u8 reserved_at_350[0x430]; 3973 3974 u8 promisc_uc[0x1]; 3975 u8 promisc_mc[0x1]; 3976 u8 promisc_all[0x1]; 3977 u8 reserved_at_783[0x2]; 3978 u8 allowed_list_type[0x3]; 3979 u8 reserved_at_788[0xc]; 3980 u8 allowed_list_size[0xc]; 3981 3982 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3983 3984 u8 reserved_at_7e0[0x20]; 3985 3986 u8 current_uc_mac_address[][0x40]; 3987 }; 3988 3989 enum { 3990 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3991 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3992 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3993 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3994 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3995 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3996 }; 3997 3998 struct mlx5_ifc_mkc_bits { 3999 u8 reserved_at_0[0x1]; 4000 u8 free[0x1]; 4001 u8 reserved_at_2[0x1]; 4002 u8 access_mode_4_2[0x3]; 4003 u8 reserved_at_6[0x7]; 4004 u8 relaxed_ordering_write[0x1]; 4005 u8 reserved_at_e[0x1]; 4006 u8 small_fence_on_rdma_read_response[0x1]; 4007 u8 umr_en[0x1]; 4008 u8 a[0x1]; 4009 u8 rw[0x1]; 4010 u8 rr[0x1]; 4011 u8 lw[0x1]; 4012 u8 lr[0x1]; 4013 u8 access_mode_1_0[0x2]; 4014 u8 reserved_at_18[0x2]; 4015 u8 ma_translation_mode[0x2]; 4016 u8 reserved_at_1c[0x4]; 4017 4018 u8 qpn[0x18]; 4019 u8 mkey_7_0[0x8]; 4020 4021 u8 reserved_at_40[0x20]; 4022 4023 u8 length64[0x1]; 4024 u8 bsf_en[0x1]; 4025 u8 sync_umr[0x1]; 4026 u8 reserved_at_63[0x2]; 4027 u8 expected_sigerr_count[0x1]; 4028 u8 reserved_at_66[0x1]; 4029 u8 en_rinval[0x1]; 4030 u8 pd[0x18]; 4031 4032 u8 start_addr[0x40]; 4033 4034 u8 len[0x40]; 4035 4036 u8 bsf_octword_size[0x20]; 4037 4038 u8 reserved_at_120[0x80]; 4039 4040 u8 translations_octword_size[0x20]; 4041 4042 u8 reserved_at_1c0[0x19]; 4043 u8 relaxed_ordering_read[0x1]; 4044 u8 reserved_at_1d9[0x1]; 4045 u8 log_page_size[0x5]; 4046 4047 u8 reserved_at_1e0[0x20]; 4048 }; 4049 4050 struct mlx5_ifc_pkey_bits { 4051 u8 reserved_at_0[0x10]; 4052 u8 pkey[0x10]; 4053 }; 4054 4055 struct mlx5_ifc_array128_auto_bits { 4056 u8 array128_auto[16][0x8]; 4057 }; 4058 4059 struct mlx5_ifc_hca_vport_context_bits { 4060 u8 field_select[0x20]; 4061 4062 u8 reserved_at_20[0xe0]; 4063 4064 u8 sm_virt_aware[0x1]; 4065 u8 has_smi[0x1]; 4066 u8 has_raw[0x1]; 4067 u8 grh_required[0x1]; 4068 u8 reserved_at_104[0xc]; 4069 u8 port_physical_state[0x4]; 4070 u8 vport_state_policy[0x4]; 4071 u8 port_state[0x4]; 4072 u8 vport_state[0x4]; 4073 4074 u8 reserved_at_120[0x20]; 4075 4076 u8 system_image_guid[0x40]; 4077 4078 u8 port_guid[0x40]; 4079 4080 u8 node_guid[0x40]; 4081 4082 u8 cap_mask1[0x20]; 4083 4084 u8 cap_mask1_field_select[0x20]; 4085 4086 u8 cap_mask2[0x20]; 4087 4088 u8 cap_mask2_field_select[0x20]; 4089 4090 u8 reserved_at_280[0x80]; 4091 4092 u8 lid[0x10]; 4093 u8 reserved_at_310[0x4]; 4094 u8 init_type_reply[0x4]; 4095 u8 lmc[0x3]; 4096 u8 subnet_timeout[0x5]; 4097 4098 u8 sm_lid[0x10]; 4099 u8 sm_sl[0x4]; 4100 u8 reserved_at_334[0xc]; 4101 4102 u8 qkey_violation_counter[0x10]; 4103 u8 pkey_violation_counter[0x10]; 4104 4105 u8 reserved_at_360[0xca0]; 4106 }; 4107 4108 struct mlx5_ifc_esw_vport_context_bits { 4109 u8 fdb_to_vport_reg_c[0x1]; 4110 u8 reserved_at_1[0x2]; 4111 u8 vport_svlan_strip[0x1]; 4112 u8 vport_cvlan_strip[0x1]; 4113 u8 vport_svlan_insert[0x1]; 4114 u8 vport_cvlan_insert[0x2]; 4115 u8 fdb_to_vport_reg_c_id[0x8]; 4116 u8 reserved_at_10[0x10]; 4117 4118 u8 reserved_at_20[0x20]; 4119 4120 u8 svlan_cfi[0x1]; 4121 u8 svlan_pcp[0x3]; 4122 u8 svlan_id[0xc]; 4123 u8 cvlan_cfi[0x1]; 4124 u8 cvlan_pcp[0x3]; 4125 u8 cvlan_id[0xc]; 4126 4127 u8 reserved_at_60[0x720]; 4128 4129 u8 sw_steering_vport_icm_address_rx[0x40]; 4130 4131 u8 sw_steering_vport_icm_address_tx[0x40]; 4132 }; 4133 4134 enum { 4135 MLX5_EQC_STATUS_OK = 0x0, 4136 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4137 }; 4138 4139 enum { 4140 MLX5_EQC_ST_ARMED = 0x9, 4141 MLX5_EQC_ST_FIRED = 0xa, 4142 }; 4143 4144 struct mlx5_ifc_eqc_bits { 4145 u8 status[0x4]; 4146 u8 reserved_at_4[0x9]; 4147 u8 ec[0x1]; 4148 u8 oi[0x1]; 4149 u8 reserved_at_f[0x5]; 4150 u8 st[0x4]; 4151 u8 reserved_at_18[0x8]; 4152 4153 u8 reserved_at_20[0x20]; 4154 4155 u8 reserved_at_40[0x14]; 4156 u8 page_offset[0x6]; 4157 u8 reserved_at_5a[0x6]; 4158 4159 u8 reserved_at_60[0x3]; 4160 u8 log_eq_size[0x5]; 4161 u8 uar_page[0x18]; 4162 4163 u8 reserved_at_80[0x20]; 4164 4165 u8 reserved_at_a0[0x14]; 4166 u8 intr[0xc]; 4167 4168 u8 reserved_at_c0[0x3]; 4169 u8 log_page_size[0x5]; 4170 u8 reserved_at_c8[0x18]; 4171 4172 u8 reserved_at_e0[0x60]; 4173 4174 u8 reserved_at_140[0x8]; 4175 u8 consumer_counter[0x18]; 4176 4177 u8 reserved_at_160[0x8]; 4178 u8 producer_counter[0x18]; 4179 4180 u8 reserved_at_180[0x80]; 4181 }; 4182 4183 enum { 4184 MLX5_DCTC_STATE_ACTIVE = 0x0, 4185 MLX5_DCTC_STATE_DRAINING = 0x1, 4186 MLX5_DCTC_STATE_DRAINED = 0x2, 4187 }; 4188 4189 enum { 4190 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4191 MLX5_DCTC_CS_RES_NA = 0x1, 4192 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4193 }; 4194 4195 enum { 4196 MLX5_DCTC_MTU_256_BYTES = 0x1, 4197 MLX5_DCTC_MTU_512_BYTES = 0x2, 4198 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4199 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4200 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4201 }; 4202 4203 struct mlx5_ifc_dctc_bits { 4204 u8 reserved_at_0[0x4]; 4205 u8 state[0x4]; 4206 u8 reserved_at_8[0x18]; 4207 4208 u8 reserved_at_20[0x8]; 4209 u8 user_index[0x18]; 4210 4211 u8 reserved_at_40[0x8]; 4212 u8 cqn[0x18]; 4213 4214 u8 counter_set_id[0x8]; 4215 u8 atomic_mode[0x4]; 4216 u8 rre[0x1]; 4217 u8 rwe[0x1]; 4218 u8 rae[0x1]; 4219 u8 atomic_like_write_en[0x1]; 4220 u8 latency_sensitive[0x1]; 4221 u8 rlky[0x1]; 4222 u8 free_ar[0x1]; 4223 u8 reserved_at_73[0xd]; 4224 4225 u8 reserved_at_80[0x8]; 4226 u8 cs_res[0x8]; 4227 u8 reserved_at_90[0x3]; 4228 u8 min_rnr_nak[0x5]; 4229 u8 reserved_at_98[0x8]; 4230 4231 u8 reserved_at_a0[0x8]; 4232 u8 srqn_xrqn[0x18]; 4233 4234 u8 reserved_at_c0[0x8]; 4235 u8 pd[0x18]; 4236 4237 u8 tclass[0x8]; 4238 u8 reserved_at_e8[0x4]; 4239 u8 flow_label[0x14]; 4240 4241 u8 dc_access_key[0x40]; 4242 4243 u8 reserved_at_140[0x5]; 4244 u8 mtu[0x3]; 4245 u8 port[0x8]; 4246 u8 pkey_index[0x10]; 4247 4248 u8 reserved_at_160[0x8]; 4249 u8 my_addr_index[0x8]; 4250 u8 reserved_at_170[0x8]; 4251 u8 hop_limit[0x8]; 4252 4253 u8 dc_access_key_violation_count[0x20]; 4254 4255 u8 reserved_at_1a0[0x14]; 4256 u8 dei_cfi[0x1]; 4257 u8 eth_prio[0x3]; 4258 u8 ecn[0x2]; 4259 u8 dscp[0x6]; 4260 4261 u8 reserved_at_1c0[0x20]; 4262 u8 ece[0x20]; 4263 }; 4264 4265 enum { 4266 MLX5_CQC_STATUS_OK = 0x0, 4267 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4268 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4269 }; 4270 4271 enum { 4272 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4273 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4274 }; 4275 4276 enum { 4277 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4278 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4279 MLX5_CQC_ST_FIRED = 0xa, 4280 }; 4281 4282 enum { 4283 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4284 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4285 MLX5_CQ_PERIOD_NUM_MODES 4286 }; 4287 4288 struct mlx5_ifc_cqc_bits { 4289 u8 status[0x4]; 4290 u8 reserved_at_4[0x2]; 4291 u8 dbr_umem_valid[0x1]; 4292 u8 apu_cq[0x1]; 4293 u8 cqe_sz[0x3]; 4294 u8 cc[0x1]; 4295 u8 reserved_at_c[0x1]; 4296 u8 scqe_break_moderation_en[0x1]; 4297 u8 oi[0x1]; 4298 u8 cq_period_mode[0x2]; 4299 u8 cqe_comp_en[0x1]; 4300 u8 mini_cqe_res_format[0x2]; 4301 u8 st[0x4]; 4302 u8 reserved_at_18[0x6]; 4303 u8 cqe_compression_layout[0x2]; 4304 4305 u8 reserved_at_20[0x20]; 4306 4307 u8 reserved_at_40[0x14]; 4308 u8 page_offset[0x6]; 4309 u8 reserved_at_5a[0x6]; 4310 4311 u8 reserved_at_60[0x3]; 4312 u8 log_cq_size[0x5]; 4313 u8 uar_page[0x18]; 4314 4315 u8 reserved_at_80[0x4]; 4316 u8 cq_period[0xc]; 4317 u8 cq_max_count[0x10]; 4318 4319 u8 c_eqn_or_apu_element[0x20]; 4320 4321 u8 reserved_at_c0[0x3]; 4322 u8 log_page_size[0x5]; 4323 u8 reserved_at_c8[0x18]; 4324 4325 u8 reserved_at_e0[0x20]; 4326 4327 u8 reserved_at_100[0x8]; 4328 u8 last_notified_index[0x18]; 4329 4330 u8 reserved_at_120[0x8]; 4331 u8 last_solicit_index[0x18]; 4332 4333 u8 reserved_at_140[0x8]; 4334 u8 consumer_counter[0x18]; 4335 4336 u8 reserved_at_160[0x8]; 4337 u8 producer_counter[0x18]; 4338 4339 u8 reserved_at_180[0x40]; 4340 4341 u8 dbr_addr[0x40]; 4342 }; 4343 4344 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4345 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4346 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4347 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4348 u8 reserved_at_0[0x800]; 4349 }; 4350 4351 struct mlx5_ifc_query_adapter_param_block_bits { 4352 u8 reserved_at_0[0xc0]; 4353 4354 u8 reserved_at_c0[0x8]; 4355 u8 ieee_vendor_id[0x18]; 4356 4357 u8 reserved_at_e0[0x10]; 4358 u8 vsd_vendor_id[0x10]; 4359 4360 u8 vsd[208][0x8]; 4361 4362 u8 vsd_contd_psid[16][0x8]; 4363 }; 4364 4365 enum { 4366 MLX5_XRQC_STATE_GOOD = 0x0, 4367 MLX5_XRQC_STATE_ERROR = 0x1, 4368 }; 4369 4370 enum { 4371 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4372 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4373 }; 4374 4375 enum { 4376 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4377 }; 4378 4379 struct mlx5_ifc_tag_matching_topology_context_bits { 4380 u8 log_matching_list_sz[0x4]; 4381 u8 reserved_at_4[0xc]; 4382 u8 append_next_index[0x10]; 4383 4384 u8 sw_phase_cnt[0x10]; 4385 u8 hw_phase_cnt[0x10]; 4386 4387 u8 reserved_at_40[0x40]; 4388 }; 4389 4390 struct mlx5_ifc_xrqc_bits { 4391 u8 state[0x4]; 4392 u8 rlkey[0x1]; 4393 u8 reserved_at_5[0xf]; 4394 u8 topology[0x4]; 4395 u8 reserved_at_18[0x4]; 4396 u8 offload[0x4]; 4397 4398 u8 reserved_at_20[0x8]; 4399 u8 user_index[0x18]; 4400 4401 u8 reserved_at_40[0x8]; 4402 u8 cqn[0x18]; 4403 4404 u8 reserved_at_60[0xa0]; 4405 4406 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4407 4408 u8 reserved_at_180[0x280]; 4409 4410 struct mlx5_ifc_wq_bits wq; 4411 }; 4412 4413 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4414 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4415 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4416 u8 reserved_at_0[0x20]; 4417 }; 4418 4419 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4420 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4421 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4422 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4423 u8 reserved_at_0[0x20]; 4424 }; 4425 4426 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4427 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4428 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4429 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4430 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4431 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4432 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4433 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4434 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4435 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4436 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4437 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4438 u8 reserved_at_0[0x7c0]; 4439 }; 4440 4441 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4442 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4443 u8 reserved_at_0[0x7c0]; 4444 }; 4445 4446 union mlx5_ifc_event_auto_bits { 4447 struct mlx5_ifc_comp_event_bits comp_event; 4448 struct mlx5_ifc_dct_events_bits dct_events; 4449 struct mlx5_ifc_qp_events_bits qp_events; 4450 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4451 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4452 struct mlx5_ifc_cq_error_bits cq_error; 4453 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4454 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4455 struct mlx5_ifc_gpio_event_bits gpio_event; 4456 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4457 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4458 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4459 u8 reserved_at_0[0xe0]; 4460 }; 4461 4462 struct mlx5_ifc_health_buffer_bits { 4463 u8 reserved_at_0[0x100]; 4464 4465 u8 assert_existptr[0x20]; 4466 4467 u8 assert_callra[0x20]; 4468 4469 u8 reserved_at_140[0x20]; 4470 4471 u8 time[0x20]; 4472 4473 u8 fw_version[0x20]; 4474 4475 u8 hw_id[0x20]; 4476 4477 u8 rfr[0x1]; 4478 u8 reserved_at_1c1[0x3]; 4479 u8 valid[0x1]; 4480 u8 severity[0x3]; 4481 u8 reserved_at_1c8[0x18]; 4482 4483 u8 irisc_index[0x8]; 4484 u8 synd[0x8]; 4485 u8 ext_synd[0x10]; 4486 }; 4487 4488 struct mlx5_ifc_register_loopback_control_bits { 4489 u8 no_lb[0x1]; 4490 u8 reserved_at_1[0x7]; 4491 u8 port[0x8]; 4492 u8 reserved_at_10[0x10]; 4493 4494 u8 reserved_at_20[0x60]; 4495 }; 4496 4497 struct mlx5_ifc_vport_tc_element_bits { 4498 u8 traffic_class[0x4]; 4499 u8 reserved_at_4[0xc]; 4500 u8 vport_number[0x10]; 4501 }; 4502 4503 struct mlx5_ifc_vport_element_bits { 4504 u8 reserved_at_0[0x10]; 4505 u8 vport_number[0x10]; 4506 }; 4507 4508 enum { 4509 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4510 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4511 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4512 }; 4513 4514 struct mlx5_ifc_tsar_element_bits { 4515 u8 reserved_at_0[0x8]; 4516 u8 tsar_type[0x8]; 4517 u8 reserved_at_10[0x10]; 4518 }; 4519 4520 enum { 4521 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4522 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4523 }; 4524 4525 struct mlx5_ifc_teardown_hca_out_bits { 4526 u8 status[0x8]; 4527 u8 reserved_at_8[0x18]; 4528 4529 u8 syndrome[0x20]; 4530 4531 u8 reserved_at_40[0x3f]; 4532 4533 u8 state[0x1]; 4534 }; 4535 4536 enum { 4537 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4538 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4539 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4540 }; 4541 4542 struct mlx5_ifc_teardown_hca_in_bits { 4543 u8 opcode[0x10]; 4544 u8 reserved_at_10[0x10]; 4545 4546 u8 reserved_at_20[0x10]; 4547 u8 op_mod[0x10]; 4548 4549 u8 reserved_at_40[0x10]; 4550 u8 profile[0x10]; 4551 4552 u8 reserved_at_60[0x20]; 4553 }; 4554 4555 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4556 u8 status[0x8]; 4557 u8 reserved_at_8[0x18]; 4558 4559 u8 syndrome[0x20]; 4560 4561 u8 reserved_at_40[0x40]; 4562 }; 4563 4564 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4565 u8 opcode[0x10]; 4566 u8 uid[0x10]; 4567 4568 u8 reserved_at_20[0x10]; 4569 u8 op_mod[0x10]; 4570 4571 u8 reserved_at_40[0x8]; 4572 u8 qpn[0x18]; 4573 4574 u8 reserved_at_60[0x20]; 4575 4576 u8 opt_param_mask[0x20]; 4577 4578 u8 reserved_at_a0[0x20]; 4579 4580 struct mlx5_ifc_qpc_bits qpc; 4581 4582 u8 reserved_at_800[0x80]; 4583 }; 4584 4585 struct mlx5_ifc_sqd2rts_qp_out_bits { 4586 u8 status[0x8]; 4587 u8 reserved_at_8[0x18]; 4588 4589 u8 syndrome[0x20]; 4590 4591 u8 reserved_at_40[0x40]; 4592 }; 4593 4594 struct mlx5_ifc_sqd2rts_qp_in_bits { 4595 u8 opcode[0x10]; 4596 u8 uid[0x10]; 4597 4598 u8 reserved_at_20[0x10]; 4599 u8 op_mod[0x10]; 4600 4601 u8 reserved_at_40[0x8]; 4602 u8 qpn[0x18]; 4603 4604 u8 reserved_at_60[0x20]; 4605 4606 u8 opt_param_mask[0x20]; 4607 4608 u8 reserved_at_a0[0x20]; 4609 4610 struct mlx5_ifc_qpc_bits qpc; 4611 4612 u8 reserved_at_800[0x80]; 4613 }; 4614 4615 struct mlx5_ifc_set_roce_address_out_bits { 4616 u8 status[0x8]; 4617 u8 reserved_at_8[0x18]; 4618 4619 u8 syndrome[0x20]; 4620 4621 u8 reserved_at_40[0x40]; 4622 }; 4623 4624 struct mlx5_ifc_set_roce_address_in_bits { 4625 u8 opcode[0x10]; 4626 u8 reserved_at_10[0x10]; 4627 4628 u8 reserved_at_20[0x10]; 4629 u8 op_mod[0x10]; 4630 4631 u8 roce_address_index[0x10]; 4632 u8 reserved_at_50[0xc]; 4633 u8 vhca_port_num[0x4]; 4634 4635 u8 reserved_at_60[0x20]; 4636 4637 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4638 }; 4639 4640 struct mlx5_ifc_set_mad_demux_out_bits { 4641 u8 status[0x8]; 4642 u8 reserved_at_8[0x18]; 4643 4644 u8 syndrome[0x20]; 4645 4646 u8 reserved_at_40[0x40]; 4647 }; 4648 4649 enum { 4650 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4651 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4652 }; 4653 4654 struct mlx5_ifc_set_mad_demux_in_bits { 4655 u8 opcode[0x10]; 4656 u8 reserved_at_10[0x10]; 4657 4658 u8 reserved_at_20[0x10]; 4659 u8 op_mod[0x10]; 4660 4661 u8 reserved_at_40[0x20]; 4662 4663 u8 reserved_at_60[0x6]; 4664 u8 demux_mode[0x2]; 4665 u8 reserved_at_68[0x18]; 4666 }; 4667 4668 struct mlx5_ifc_set_l2_table_entry_out_bits { 4669 u8 status[0x8]; 4670 u8 reserved_at_8[0x18]; 4671 4672 u8 syndrome[0x20]; 4673 4674 u8 reserved_at_40[0x40]; 4675 }; 4676 4677 struct mlx5_ifc_set_l2_table_entry_in_bits { 4678 u8 opcode[0x10]; 4679 u8 reserved_at_10[0x10]; 4680 4681 u8 reserved_at_20[0x10]; 4682 u8 op_mod[0x10]; 4683 4684 u8 reserved_at_40[0x60]; 4685 4686 u8 reserved_at_a0[0x8]; 4687 u8 table_index[0x18]; 4688 4689 u8 reserved_at_c0[0x20]; 4690 4691 u8 reserved_at_e0[0x13]; 4692 u8 vlan_valid[0x1]; 4693 u8 vlan[0xc]; 4694 4695 struct mlx5_ifc_mac_address_layout_bits mac_address; 4696 4697 u8 reserved_at_140[0xc0]; 4698 }; 4699 4700 struct mlx5_ifc_set_issi_out_bits { 4701 u8 status[0x8]; 4702 u8 reserved_at_8[0x18]; 4703 4704 u8 syndrome[0x20]; 4705 4706 u8 reserved_at_40[0x40]; 4707 }; 4708 4709 struct mlx5_ifc_set_issi_in_bits { 4710 u8 opcode[0x10]; 4711 u8 reserved_at_10[0x10]; 4712 4713 u8 reserved_at_20[0x10]; 4714 u8 op_mod[0x10]; 4715 4716 u8 reserved_at_40[0x10]; 4717 u8 current_issi[0x10]; 4718 4719 u8 reserved_at_60[0x20]; 4720 }; 4721 4722 struct mlx5_ifc_set_hca_cap_out_bits { 4723 u8 status[0x8]; 4724 u8 reserved_at_8[0x18]; 4725 4726 u8 syndrome[0x20]; 4727 4728 u8 reserved_at_40[0x40]; 4729 }; 4730 4731 struct mlx5_ifc_set_hca_cap_in_bits { 4732 u8 opcode[0x10]; 4733 u8 reserved_at_10[0x10]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 op_mod[0x10]; 4737 4738 u8 other_function[0x1]; 4739 u8 reserved_at_41[0xf]; 4740 u8 function_id[0x10]; 4741 4742 u8 reserved_at_60[0x20]; 4743 4744 union mlx5_ifc_hca_cap_union_bits capability; 4745 }; 4746 4747 enum { 4748 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4749 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4750 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4751 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4752 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4753 }; 4754 4755 struct mlx5_ifc_set_fte_out_bits { 4756 u8 status[0x8]; 4757 u8 reserved_at_8[0x18]; 4758 4759 u8 syndrome[0x20]; 4760 4761 u8 reserved_at_40[0x40]; 4762 }; 4763 4764 struct mlx5_ifc_set_fte_in_bits { 4765 u8 opcode[0x10]; 4766 u8 reserved_at_10[0x10]; 4767 4768 u8 reserved_at_20[0x10]; 4769 u8 op_mod[0x10]; 4770 4771 u8 other_vport[0x1]; 4772 u8 reserved_at_41[0xf]; 4773 u8 vport_number[0x10]; 4774 4775 u8 reserved_at_60[0x20]; 4776 4777 u8 table_type[0x8]; 4778 u8 reserved_at_88[0x18]; 4779 4780 u8 reserved_at_a0[0x8]; 4781 u8 table_id[0x18]; 4782 4783 u8 ignore_flow_level[0x1]; 4784 u8 reserved_at_c1[0x17]; 4785 u8 modify_enable_mask[0x8]; 4786 4787 u8 reserved_at_e0[0x20]; 4788 4789 u8 flow_index[0x20]; 4790 4791 u8 reserved_at_120[0xe0]; 4792 4793 struct mlx5_ifc_flow_context_bits flow_context; 4794 }; 4795 4796 struct mlx5_ifc_rts2rts_qp_out_bits { 4797 u8 status[0x8]; 4798 u8 reserved_at_8[0x18]; 4799 4800 u8 syndrome[0x20]; 4801 4802 u8 reserved_at_40[0x20]; 4803 u8 ece[0x20]; 4804 }; 4805 4806 struct mlx5_ifc_rts2rts_qp_in_bits { 4807 u8 opcode[0x10]; 4808 u8 uid[0x10]; 4809 4810 u8 reserved_at_20[0x10]; 4811 u8 op_mod[0x10]; 4812 4813 u8 reserved_at_40[0x8]; 4814 u8 qpn[0x18]; 4815 4816 u8 reserved_at_60[0x20]; 4817 4818 u8 opt_param_mask[0x20]; 4819 4820 u8 ece[0x20]; 4821 4822 struct mlx5_ifc_qpc_bits qpc; 4823 4824 u8 reserved_at_800[0x80]; 4825 }; 4826 4827 struct mlx5_ifc_rtr2rts_qp_out_bits { 4828 u8 status[0x8]; 4829 u8 reserved_at_8[0x18]; 4830 4831 u8 syndrome[0x20]; 4832 4833 u8 reserved_at_40[0x20]; 4834 u8 ece[0x20]; 4835 }; 4836 4837 struct mlx5_ifc_rtr2rts_qp_in_bits { 4838 u8 opcode[0x10]; 4839 u8 uid[0x10]; 4840 4841 u8 reserved_at_20[0x10]; 4842 u8 op_mod[0x10]; 4843 4844 u8 reserved_at_40[0x8]; 4845 u8 qpn[0x18]; 4846 4847 u8 reserved_at_60[0x20]; 4848 4849 u8 opt_param_mask[0x20]; 4850 4851 u8 ece[0x20]; 4852 4853 struct mlx5_ifc_qpc_bits qpc; 4854 4855 u8 reserved_at_800[0x80]; 4856 }; 4857 4858 struct mlx5_ifc_rst2init_qp_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_at_8[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 reserved_at_40[0x20]; 4865 u8 ece[0x20]; 4866 }; 4867 4868 struct mlx5_ifc_rst2init_qp_in_bits { 4869 u8 opcode[0x10]; 4870 u8 uid[0x10]; 4871 4872 u8 reserved_at_20[0x10]; 4873 u8 op_mod[0x10]; 4874 4875 u8 reserved_at_40[0x8]; 4876 u8 qpn[0x18]; 4877 4878 u8 reserved_at_60[0x20]; 4879 4880 u8 opt_param_mask[0x20]; 4881 4882 u8 ece[0x20]; 4883 4884 struct mlx5_ifc_qpc_bits qpc; 4885 4886 u8 reserved_at_800[0x80]; 4887 }; 4888 4889 struct mlx5_ifc_query_xrq_out_bits { 4890 u8 status[0x8]; 4891 u8 reserved_at_8[0x18]; 4892 4893 u8 syndrome[0x20]; 4894 4895 u8 reserved_at_40[0x40]; 4896 4897 struct mlx5_ifc_xrqc_bits xrq_context; 4898 }; 4899 4900 struct mlx5_ifc_query_xrq_in_bits { 4901 u8 opcode[0x10]; 4902 u8 reserved_at_10[0x10]; 4903 4904 u8 reserved_at_20[0x10]; 4905 u8 op_mod[0x10]; 4906 4907 u8 reserved_at_40[0x8]; 4908 u8 xrqn[0x18]; 4909 4910 u8 reserved_at_60[0x20]; 4911 }; 4912 4913 struct mlx5_ifc_query_xrc_srq_out_bits { 4914 u8 status[0x8]; 4915 u8 reserved_at_8[0x18]; 4916 4917 u8 syndrome[0x20]; 4918 4919 u8 reserved_at_40[0x40]; 4920 4921 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4922 4923 u8 reserved_at_280[0x600]; 4924 4925 u8 pas[][0x40]; 4926 }; 4927 4928 struct mlx5_ifc_query_xrc_srq_in_bits { 4929 u8 opcode[0x10]; 4930 u8 reserved_at_10[0x10]; 4931 4932 u8 reserved_at_20[0x10]; 4933 u8 op_mod[0x10]; 4934 4935 u8 reserved_at_40[0x8]; 4936 u8 xrc_srqn[0x18]; 4937 4938 u8 reserved_at_60[0x20]; 4939 }; 4940 4941 enum { 4942 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4943 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4944 }; 4945 4946 struct mlx5_ifc_query_vport_state_out_bits { 4947 u8 status[0x8]; 4948 u8 reserved_at_8[0x18]; 4949 4950 u8 syndrome[0x20]; 4951 4952 u8 reserved_at_40[0x20]; 4953 4954 u8 reserved_at_60[0x18]; 4955 u8 admin_state[0x4]; 4956 u8 state[0x4]; 4957 }; 4958 4959 enum { 4960 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4961 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4962 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4963 }; 4964 4965 struct mlx5_ifc_arm_monitor_counter_in_bits { 4966 u8 opcode[0x10]; 4967 u8 uid[0x10]; 4968 4969 u8 reserved_at_20[0x10]; 4970 u8 op_mod[0x10]; 4971 4972 u8 reserved_at_40[0x20]; 4973 4974 u8 reserved_at_60[0x20]; 4975 }; 4976 4977 struct mlx5_ifc_arm_monitor_counter_out_bits { 4978 u8 status[0x8]; 4979 u8 reserved_at_8[0x18]; 4980 4981 u8 syndrome[0x20]; 4982 4983 u8 reserved_at_40[0x40]; 4984 }; 4985 4986 enum { 4987 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4988 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4989 }; 4990 4991 enum mlx5_monitor_counter_ppcnt { 4992 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4993 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4994 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4995 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4996 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4997 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4998 }; 4999 5000 enum { 5001 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5002 }; 5003 5004 struct mlx5_ifc_monitor_counter_output_bits { 5005 u8 reserved_at_0[0x4]; 5006 u8 type[0x4]; 5007 u8 reserved_at_8[0x8]; 5008 u8 counter[0x10]; 5009 5010 u8 counter_group_id[0x20]; 5011 }; 5012 5013 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5014 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5015 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5016 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5017 5018 struct mlx5_ifc_set_monitor_counter_in_bits { 5019 u8 opcode[0x10]; 5020 u8 uid[0x10]; 5021 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 reserved_at_40[0x10]; 5026 u8 num_of_counters[0x10]; 5027 5028 u8 reserved_at_60[0x20]; 5029 5030 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5031 }; 5032 5033 struct mlx5_ifc_set_monitor_counter_out_bits { 5034 u8 status[0x8]; 5035 u8 reserved_at_8[0x18]; 5036 5037 u8 syndrome[0x20]; 5038 5039 u8 reserved_at_40[0x40]; 5040 }; 5041 5042 struct mlx5_ifc_query_vport_state_in_bits { 5043 u8 opcode[0x10]; 5044 u8 reserved_at_10[0x10]; 5045 5046 u8 reserved_at_20[0x10]; 5047 u8 op_mod[0x10]; 5048 5049 u8 other_vport[0x1]; 5050 u8 reserved_at_41[0xf]; 5051 u8 vport_number[0x10]; 5052 5053 u8 reserved_at_60[0x20]; 5054 }; 5055 5056 struct mlx5_ifc_query_vnic_env_out_bits { 5057 u8 status[0x8]; 5058 u8 reserved_at_8[0x18]; 5059 5060 u8 syndrome[0x20]; 5061 5062 u8 reserved_at_40[0x40]; 5063 5064 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5065 }; 5066 5067 enum { 5068 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5069 }; 5070 5071 struct mlx5_ifc_query_vnic_env_in_bits { 5072 u8 opcode[0x10]; 5073 u8 reserved_at_10[0x10]; 5074 5075 u8 reserved_at_20[0x10]; 5076 u8 op_mod[0x10]; 5077 5078 u8 other_vport[0x1]; 5079 u8 reserved_at_41[0xf]; 5080 u8 vport_number[0x10]; 5081 5082 u8 reserved_at_60[0x20]; 5083 }; 5084 5085 struct mlx5_ifc_query_vport_counter_out_bits { 5086 u8 status[0x8]; 5087 u8 reserved_at_8[0x18]; 5088 5089 u8 syndrome[0x20]; 5090 5091 u8 reserved_at_40[0x40]; 5092 5093 struct mlx5_ifc_traffic_counter_bits received_errors; 5094 5095 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5096 5097 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5098 5099 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5100 5101 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5102 5103 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5104 5105 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5106 5107 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5108 5109 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5110 5111 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5112 5113 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5114 5115 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5116 5117 u8 reserved_at_680[0xa00]; 5118 }; 5119 5120 enum { 5121 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5122 }; 5123 5124 struct mlx5_ifc_query_vport_counter_in_bits { 5125 u8 opcode[0x10]; 5126 u8 reserved_at_10[0x10]; 5127 5128 u8 reserved_at_20[0x10]; 5129 u8 op_mod[0x10]; 5130 5131 u8 other_vport[0x1]; 5132 u8 reserved_at_41[0xb]; 5133 u8 port_num[0x4]; 5134 u8 vport_number[0x10]; 5135 5136 u8 reserved_at_60[0x60]; 5137 5138 u8 clear[0x1]; 5139 u8 reserved_at_c1[0x1f]; 5140 5141 u8 reserved_at_e0[0x20]; 5142 }; 5143 5144 struct mlx5_ifc_query_tis_out_bits { 5145 u8 status[0x8]; 5146 u8 reserved_at_8[0x18]; 5147 5148 u8 syndrome[0x20]; 5149 5150 u8 reserved_at_40[0x40]; 5151 5152 struct mlx5_ifc_tisc_bits tis_context; 5153 }; 5154 5155 struct mlx5_ifc_query_tis_in_bits { 5156 u8 opcode[0x10]; 5157 u8 reserved_at_10[0x10]; 5158 5159 u8 reserved_at_20[0x10]; 5160 u8 op_mod[0x10]; 5161 5162 u8 reserved_at_40[0x8]; 5163 u8 tisn[0x18]; 5164 5165 u8 reserved_at_60[0x20]; 5166 }; 5167 5168 struct mlx5_ifc_query_tir_out_bits { 5169 u8 status[0x8]; 5170 u8 reserved_at_8[0x18]; 5171 5172 u8 syndrome[0x20]; 5173 5174 u8 reserved_at_40[0xc0]; 5175 5176 struct mlx5_ifc_tirc_bits tir_context; 5177 }; 5178 5179 struct mlx5_ifc_query_tir_in_bits { 5180 u8 opcode[0x10]; 5181 u8 reserved_at_10[0x10]; 5182 5183 u8 reserved_at_20[0x10]; 5184 u8 op_mod[0x10]; 5185 5186 u8 reserved_at_40[0x8]; 5187 u8 tirn[0x18]; 5188 5189 u8 reserved_at_60[0x20]; 5190 }; 5191 5192 struct mlx5_ifc_query_srq_out_bits { 5193 u8 status[0x8]; 5194 u8 reserved_at_8[0x18]; 5195 5196 u8 syndrome[0x20]; 5197 5198 u8 reserved_at_40[0x40]; 5199 5200 struct mlx5_ifc_srqc_bits srq_context_entry; 5201 5202 u8 reserved_at_280[0x600]; 5203 5204 u8 pas[][0x40]; 5205 }; 5206 5207 struct mlx5_ifc_query_srq_in_bits { 5208 u8 opcode[0x10]; 5209 u8 reserved_at_10[0x10]; 5210 5211 u8 reserved_at_20[0x10]; 5212 u8 op_mod[0x10]; 5213 5214 u8 reserved_at_40[0x8]; 5215 u8 srqn[0x18]; 5216 5217 u8 reserved_at_60[0x20]; 5218 }; 5219 5220 struct mlx5_ifc_query_sq_out_bits { 5221 u8 status[0x8]; 5222 u8 reserved_at_8[0x18]; 5223 5224 u8 syndrome[0x20]; 5225 5226 u8 reserved_at_40[0xc0]; 5227 5228 struct mlx5_ifc_sqc_bits sq_context; 5229 }; 5230 5231 struct mlx5_ifc_query_sq_in_bits { 5232 u8 opcode[0x10]; 5233 u8 reserved_at_10[0x10]; 5234 5235 u8 reserved_at_20[0x10]; 5236 u8 op_mod[0x10]; 5237 5238 u8 reserved_at_40[0x8]; 5239 u8 sqn[0x18]; 5240 5241 u8 reserved_at_60[0x20]; 5242 }; 5243 5244 struct mlx5_ifc_query_special_contexts_out_bits { 5245 u8 status[0x8]; 5246 u8 reserved_at_8[0x18]; 5247 5248 u8 syndrome[0x20]; 5249 5250 u8 dump_fill_mkey[0x20]; 5251 5252 u8 resd_lkey[0x20]; 5253 5254 u8 null_mkey[0x20]; 5255 5256 u8 reserved_at_a0[0x60]; 5257 }; 5258 5259 struct mlx5_ifc_query_special_contexts_in_bits { 5260 u8 opcode[0x10]; 5261 u8 reserved_at_10[0x10]; 5262 5263 u8 reserved_at_20[0x10]; 5264 u8 op_mod[0x10]; 5265 5266 u8 reserved_at_40[0x40]; 5267 }; 5268 5269 struct mlx5_ifc_query_scheduling_element_out_bits { 5270 u8 opcode[0x10]; 5271 u8 reserved_at_10[0x10]; 5272 5273 u8 reserved_at_20[0x10]; 5274 u8 op_mod[0x10]; 5275 5276 u8 reserved_at_40[0xc0]; 5277 5278 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5279 5280 u8 reserved_at_300[0x100]; 5281 }; 5282 5283 enum { 5284 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5285 SCHEDULING_HIERARCHY_NIC = 0x3, 5286 }; 5287 5288 struct mlx5_ifc_query_scheduling_element_in_bits { 5289 u8 opcode[0x10]; 5290 u8 reserved_at_10[0x10]; 5291 5292 u8 reserved_at_20[0x10]; 5293 u8 op_mod[0x10]; 5294 5295 u8 scheduling_hierarchy[0x8]; 5296 u8 reserved_at_48[0x18]; 5297 5298 u8 scheduling_element_id[0x20]; 5299 5300 u8 reserved_at_80[0x180]; 5301 }; 5302 5303 struct mlx5_ifc_query_rqt_out_bits { 5304 u8 status[0x8]; 5305 u8 reserved_at_8[0x18]; 5306 5307 u8 syndrome[0x20]; 5308 5309 u8 reserved_at_40[0xc0]; 5310 5311 struct mlx5_ifc_rqtc_bits rqt_context; 5312 }; 5313 5314 struct mlx5_ifc_query_rqt_in_bits { 5315 u8 opcode[0x10]; 5316 u8 reserved_at_10[0x10]; 5317 5318 u8 reserved_at_20[0x10]; 5319 u8 op_mod[0x10]; 5320 5321 u8 reserved_at_40[0x8]; 5322 u8 rqtn[0x18]; 5323 5324 u8 reserved_at_60[0x20]; 5325 }; 5326 5327 struct mlx5_ifc_query_rq_out_bits { 5328 u8 status[0x8]; 5329 u8 reserved_at_8[0x18]; 5330 5331 u8 syndrome[0x20]; 5332 5333 u8 reserved_at_40[0xc0]; 5334 5335 struct mlx5_ifc_rqc_bits rq_context; 5336 }; 5337 5338 struct mlx5_ifc_query_rq_in_bits { 5339 u8 opcode[0x10]; 5340 u8 reserved_at_10[0x10]; 5341 5342 u8 reserved_at_20[0x10]; 5343 u8 op_mod[0x10]; 5344 5345 u8 reserved_at_40[0x8]; 5346 u8 rqn[0x18]; 5347 5348 u8 reserved_at_60[0x20]; 5349 }; 5350 5351 struct mlx5_ifc_query_roce_address_out_bits { 5352 u8 status[0x8]; 5353 u8 reserved_at_8[0x18]; 5354 5355 u8 syndrome[0x20]; 5356 5357 u8 reserved_at_40[0x40]; 5358 5359 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5360 }; 5361 5362 struct mlx5_ifc_query_roce_address_in_bits { 5363 u8 opcode[0x10]; 5364 u8 reserved_at_10[0x10]; 5365 5366 u8 reserved_at_20[0x10]; 5367 u8 op_mod[0x10]; 5368 5369 u8 roce_address_index[0x10]; 5370 u8 reserved_at_50[0xc]; 5371 u8 vhca_port_num[0x4]; 5372 5373 u8 reserved_at_60[0x20]; 5374 }; 5375 5376 struct mlx5_ifc_query_rmp_out_bits { 5377 u8 status[0x8]; 5378 u8 reserved_at_8[0x18]; 5379 5380 u8 syndrome[0x20]; 5381 5382 u8 reserved_at_40[0xc0]; 5383 5384 struct mlx5_ifc_rmpc_bits rmp_context; 5385 }; 5386 5387 struct mlx5_ifc_query_rmp_in_bits { 5388 u8 opcode[0x10]; 5389 u8 reserved_at_10[0x10]; 5390 5391 u8 reserved_at_20[0x10]; 5392 u8 op_mod[0x10]; 5393 5394 u8 reserved_at_40[0x8]; 5395 u8 rmpn[0x18]; 5396 5397 u8 reserved_at_60[0x20]; 5398 }; 5399 5400 struct mlx5_ifc_cqe_error_syndrome_bits { 5401 u8 hw_error_syndrome[0x8]; 5402 u8 hw_syndrome_type[0x4]; 5403 u8 reserved_at_c[0x4]; 5404 u8 vendor_error_syndrome[0x8]; 5405 u8 syndrome[0x8]; 5406 }; 5407 5408 struct mlx5_ifc_qp_context_extension_bits { 5409 u8 reserved_at_0[0x60]; 5410 5411 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5412 5413 u8 reserved_at_80[0x580]; 5414 }; 5415 5416 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5417 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5418 5419 u8 pas[0][0x40]; 5420 }; 5421 5422 struct mlx5_ifc_qp_pas_list_in_bits { 5423 struct mlx5_ifc_cmd_pas_bits pas[0]; 5424 }; 5425 5426 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5427 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5428 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5429 }; 5430 5431 struct mlx5_ifc_query_qp_out_bits { 5432 u8 status[0x8]; 5433 u8 reserved_at_8[0x18]; 5434 5435 u8 syndrome[0x20]; 5436 5437 u8 reserved_at_40[0x40]; 5438 5439 u8 opt_param_mask[0x20]; 5440 5441 u8 ece[0x20]; 5442 5443 struct mlx5_ifc_qpc_bits qpc; 5444 5445 u8 reserved_at_800[0x80]; 5446 5447 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5448 }; 5449 5450 struct mlx5_ifc_query_qp_in_bits { 5451 u8 opcode[0x10]; 5452 u8 reserved_at_10[0x10]; 5453 5454 u8 reserved_at_20[0x10]; 5455 u8 op_mod[0x10]; 5456 5457 u8 qpc_ext[0x1]; 5458 u8 reserved_at_41[0x7]; 5459 u8 qpn[0x18]; 5460 5461 u8 reserved_at_60[0x20]; 5462 }; 5463 5464 struct mlx5_ifc_query_q_counter_out_bits { 5465 u8 status[0x8]; 5466 u8 reserved_at_8[0x18]; 5467 5468 u8 syndrome[0x20]; 5469 5470 u8 reserved_at_40[0x40]; 5471 5472 u8 rx_write_requests[0x20]; 5473 5474 u8 reserved_at_a0[0x20]; 5475 5476 u8 rx_read_requests[0x20]; 5477 5478 u8 reserved_at_e0[0x20]; 5479 5480 u8 rx_atomic_requests[0x20]; 5481 5482 u8 reserved_at_120[0x20]; 5483 5484 u8 rx_dct_connect[0x20]; 5485 5486 u8 reserved_at_160[0x20]; 5487 5488 u8 out_of_buffer[0x20]; 5489 5490 u8 reserved_at_1a0[0x20]; 5491 5492 u8 out_of_sequence[0x20]; 5493 5494 u8 reserved_at_1e0[0x20]; 5495 5496 u8 duplicate_request[0x20]; 5497 5498 u8 reserved_at_220[0x20]; 5499 5500 u8 rnr_nak_retry_err[0x20]; 5501 5502 u8 reserved_at_260[0x20]; 5503 5504 u8 packet_seq_err[0x20]; 5505 5506 u8 reserved_at_2a0[0x20]; 5507 5508 u8 implied_nak_seq_err[0x20]; 5509 5510 u8 reserved_at_2e0[0x20]; 5511 5512 u8 local_ack_timeout_err[0x20]; 5513 5514 u8 reserved_at_320[0xa0]; 5515 5516 u8 resp_local_length_error[0x20]; 5517 5518 u8 req_local_length_error[0x20]; 5519 5520 u8 resp_local_qp_error[0x20]; 5521 5522 u8 local_operation_error[0x20]; 5523 5524 u8 resp_local_protection[0x20]; 5525 5526 u8 req_local_protection[0x20]; 5527 5528 u8 resp_cqe_error[0x20]; 5529 5530 u8 req_cqe_error[0x20]; 5531 5532 u8 req_mw_binding[0x20]; 5533 5534 u8 req_bad_response[0x20]; 5535 5536 u8 req_remote_invalid_request[0x20]; 5537 5538 u8 resp_remote_invalid_request[0x20]; 5539 5540 u8 req_remote_access_errors[0x20]; 5541 5542 u8 resp_remote_access_errors[0x20]; 5543 5544 u8 req_remote_operation_errors[0x20]; 5545 5546 u8 req_transport_retries_exceeded[0x20]; 5547 5548 u8 cq_overflow[0x20]; 5549 5550 u8 resp_cqe_flush_error[0x20]; 5551 5552 u8 req_cqe_flush_error[0x20]; 5553 5554 u8 reserved_at_620[0x20]; 5555 5556 u8 roce_adp_retrans[0x20]; 5557 5558 u8 roce_adp_retrans_to[0x20]; 5559 5560 u8 roce_slow_restart[0x20]; 5561 5562 u8 roce_slow_restart_cnps[0x20]; 5563 5564 u8 roce_slow_restart_trans[0x20]; 5565 5566 u8 reserved_at_6e0[0x120]; 5567 }; 5568 5569 struct mlx5_ifc_query_q_counter_in_bits { 5570 u8 opcode[0x10]; 5571 u8 reserved_at_10[0x10]; 5572 5573 u8 reserved_at_20[0x10]; 5574 u8 op_mod[0x10]; 5575 5576 u8 reserved_at_40[0x80]; 5577 5578 u8 clear[0x1]; 5579 u8 reserved_at_c1[0x1f]; 5580 5581 u8 reserved_at_e0[0x18]; 5582 u8 counter_set_id[0x8]; 5583 }; 5584 5585 struct mlx5_ifc_query_pages_out_bits { 5586 u8 status[0x8]; 5587 u8 reserved_at_8[0x18]; 5588 5589 u8 syndrome[0x20]; 5590 5591 u8 embedded_cpu_function[0x1]; 5592 u8 reserved_at_41[0xf]; 5593 u8 function_id[0x10]; 5594 5595 u8 num_pages[0x20]; 5596 }; 5597 5598 enum { 5599 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5600 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5601 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5602 }; 5603 5604 struct mlx5_ifc_query_pages_in_bits { 5605 u8 opcode[0x10]; 5606 u8 reserved_at_10[0x10]; 5607 5608 u8 reserved_at_20[0x10]; 5609 u8 op_mod[0x10]; 5610 5611 u8 embedded_cpu_function[0x1]; 5612 u8 reserved_at_41[0xf]; 5613 u8 function_id[0x10]; 5614 5615 u8 reserved_at_60[0x20]; 5616 }; 5617 5618 struct mlx5_ifc_query_nic_vport_context_out_bits { 5619 u8 status[0x8]; 5620 u8 reserved_at_8[0x18]; 5621 5622 u8 syndrome[0x20]; 5623 5624 u8 reserved_at_40[0x40]; 5625 5626 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5627 }; 5628 5629 struct mlx5_ifc_query_nic_vport_context_in_bits { 5630 u8 opcode[0x10]; 5631 u8 reserved_at_10[0x10]; 5632 5633 u8 reserved_at_20[0x10]; 5634 u8 op_mod[0x10]; 5635 5636 u8 other_vport[0x1]; 5637 u8 reserved_at_41[0xf]; 5638 u8 vport_number[0x10]; 5639 5640 u8 reserved_at_60[0x5]; 5641 u8 allowed_list_type[0x3]; 5642 u8 reserved_at_68[0x18]; 5643 }; 5644 5645 struct mlx5_ifc_query_mkey_out_bits { 5646 u8 status[0x8]; 5647 u8 reserved_at_8[0x18]; 5648 5649 u8 syndrome[0x20]; 5650 5651 u8 reserved_at_40[0x40]; 5652 5653 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5654 5655 u8 reserved_at_280[0x600]; 5656 5657 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5658 5659 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5660 }; 5661 5662 struct mlx5_ifc_query_mkey_in_bits { 5663 u8 opcode[0x10]; 5664 u8 reserved_at_10[0x10]; 5665 5666 u8 reserved_at_20[0x10]; 5667 u8 op_mod[0x10]; 5668 5669 u8 reserved_at_40[0x8]; 5670 u8 mkey_index[0x18]; 5671 5672 u8 pg_access[0x1]; 5673 u8 reserved_at_61[0x1f]; 5674 }; 5675 5676 struct mlx5_ifc_query_mad_demux_out_bits { 5677 u8 status[0x8]; 5678 u8 reserved_at_8[0x18]; 5679 5680 u8 syndrome[0x20]; 5681 5682 u8 reserved_at_40[0x40]; 5683 5684 u8 mad_dumux_parameters_block[0x20]; 5685 }; 5686 5687 struct mlx5_ifc_query_mad_demux_in_bits { 5688 u8 opcode[0x10]; 5689 u8 reserved_at_10[0x10]; 5690 5691 u8 reserved_at_20[0x10]; 5692 u8 op_mod[0x10]; 5693 5694 u8 reserved_at_40[0x40]; 5695 }; 5696 5697 struct mlx5_ifc_query_l2_table_entry_out_bits { 5698 u8 status[0x8]; 5699 u8 reserved_at_8[0x18]; 5700 5701 u8 syndrome[0x20]; 5702 5703 u8 reserved_at_40[0xa0]; 5704 5705 u8 reserved_at_e0[0x13]; 5706 u8 vlan_valid[0x1]; 5707 u8 vlan[0xc]; 5708 5709 struct mlx5_ifc_mac_address_layout_bits mac_address; 5710 5711 u8 reserved_at_140[0xc0]; 5712 }; 5713 5714 struct mlx5_ifc_query_l2_table_entry_in_bits { 5715 u8 opcode[0x10]; 5716 u8 reserved_at_10[0x10]; 5717 5718 u8 reserved_at_20[0x10]; 5719 u8 op_mod[0x10]; 5720 5721 u8 reserved_at_40[0x60]; 5722 5723 u8 reserved_at_a0[0x8]; 5724 u8 table_index[0x18]; 5725 5726 u8 reserved_at_c0[0x140]; 5727 }; 5728 5729 struct mlx5_ifc_query_issi_out_bits { 5730 u8 status[0x8]; 5731 u8 reserved_at_8[0x18]; 5732 5733 u8 syndrome[0x20]; 5734 5735 u8 reserved_at_40[0x10]; 5736 u8 current_issi[0x10]; 5737 5738 u8 reserved_at_60[0xa0]; 5739 5740 u8 reserved_at_100[76][0x8]; 5741 u8 supported_issi_dw0[0x20]; 5742 }; 5743 5744 struct mlx5_ifc_query_issi_in_bits { 5745 u8 opcode[0x10]; 5746 u8 reserved_at_10[0x10]; 5747 5748 u8 reserved_at_20[0x10]; 5749 u8 op_mod[0x10]; 5750 5751 u8 reserved_at_40[0x40]; 5752 }; 5753 5754 struct mlx5_ifc_set_driver_version_out_bits { 5755 u8 status[0x8]; 5756 u8 reserved_0[0x18]; 5757 5758 u8 syndrome[0x20]; 5759 u8 reserved_1[0x40]; 5760 }; 5761 5762 struct mlx5_ifc_set_driver_version_in_bits { 5763 u8 opcode[0x10]; 5764 u8 reserved_0[0x10]; 5765 5766 u8 reserved_1[0x10]; 5767 u8 op_mod[0x10]; 5768 5769 u8 reserved_2[0x40]; 5770 u8 driver_version[64][0x8]; 5771 }; 5772 5773 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5774 u8 status[0x8]; 5775 u8 reserved_at_8[0x18]; 5776 5777 u8 syndrome[0x20]; 5778 5779 u8 reserved_at_40[0x40]; 5780 5781 struct mlx5_ifc_pkey_bits pkey[]; 5782 }; 5783 5784 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5785 u8 opcode[0x10]; 5786 u8 reserved_at_10[0x10]; 5787 5788 u8 reserved_at_20[0x10]; 5789 u8 op_mod[0x10]; 5790 5791 u8 other_vport[0x1]; 5792 u8 reserved_at_41[0xb]; 5793 u8 port_num[0x4]; 5794 u8 vport_number[0x10]; 5795 5796 u8 reserved_at_60[0x10]; 5797 u8 pkey_index[0x10]; 5798 }; 5799 5800 enum { 5801 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5802 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5803 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5804 }; 5805 5806 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5807 u8 status[0x8]; 5808 u8 reserved_at_8[0x18]; 5809 5810 u8 syndrome[0x20]; 5811 5812 u8 reserved_at_40[0x20]; 5813 5814 u8 gids_num[0x10]; 5815 u8 reserved_at_70[0x10]; 5816 5817 struct mlx5_ifc_array128_auto_bits gid[]; 5818 }; 5819 5820 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5821 u8 opcode[0x10]; 5822 u8 reserved_at_10[0x10]; 5823 5824 u8 reserved_at_20[0x10]; 5825 u8 op_mod[0x10]; 5826 5827 u8 other_vport[0x1]; 5828 u8 reserved_at_41[0xb]; 5829 u8 port_num[0x4]; 5830 u8 vport_number[0x10]; 5831 5832 u8 reserved_at_60[0x10]; 5833 u8 gid_index[0x10]; 5834 }; 5835 5836 struct mlx5_ifc_query_hca_vport_context_out_bits { 5837 u8 status[0x8]; 5838 u8 reserved_at_8[0x18]; 5839 5840 u8 syndrome[0x20]; 5841 5842 u8 reserved_at_40[0x40]; 5843 5844 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5845 }; 5846 5847 struct mlx5_ifc_query_hca_vport_context_in_bits { 5848 u8 opcode[0x10]; 5849 u8 reserved_at_10[0x10]; 5850 5851 u8 reserved_at_20[0x10]; 5852 u8 op_mod[0x10]; 5853 5854 u8 other_vport[0x1]; 5855 u8 reserved_at_41[0xb]; 5856 u8 port_num[0x4]; 5857 u8 vport_number[0x10]; 5858 5859 u8 reserved_at_60[0x20]; 5860 }; 5861 5862 struct mlx5_ifc_query_hca_cap_out_bits { 5863 u8 status[0x8]; 5864 u8 reserved_at_8[0x18]; 5865 5866 u8 syndrome[0x20]; 5867 5868 u8 reserved_at_40[0x40]; 5869 5870 union mlx5_ifc_hca_cap_union_bits capability; 5871 }; 5872 5873 struct mlx5_ifc_query_hca_cap_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_at_10[0x10]; 5876 5877 u8 reserved_at_20[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 other_function[0x1]; 5881 u8 reserved_at_41[0xf]; 5882 u8 function_id[0x10]; 5883 5884 u8 reserved_at_60[0x20]; 5885 }; 5886 5887 struct mlx5_ifc_other_hca_cap_bits { 5888 u8 roce[0x1]; 5889 u8 reserved_at_1[0x27f]; 5890 }; 5891 5892 struct mlx5_ifc_query_other_hca_cap_out_bits { 5893 u8 status[0x8]; 5894 u8 reserved_at_8[0x18]; 5895 5896 u8 syndrome[0x20]; 5897 5898 u8 reserved_at_40[0x40]; 5899 5900 struct mlx5_ifc_other_hca_cap_bits other_capability; 5901 }; 5902 5903 struct mlx5_ifc_query_other_hca_cap_in_bits { 5904 u8 opcode[0x10]; 5905 u8 reserved_at_10[0x10]; 5906 5907 u8 reserved_at_20[0x10]; 5908 u8 op_mod[0x10]; 5909 5910 u8 reserved_at_40[0x10]; 5911 u8 function_id[0x10]; 5912 5913 u8 reserved_at_60[0x20]; 5914 }; 5915 5916 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5917 u8 status[0x8]; 5918 u8 reserved_at_8[0x18]; 5919 5920 u8 syndrome[0x20]; 5921 5922 u8 reserved_at_40[0x40]; 5923 }; 5924 5925 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5926 u8 opcode[0x10]; 5927 u8 reserved_at_10[0x10]; 5928 5929 u8 reserved_at_20[0x10]; 5930 u8 op_mod[0x10]; 5931 5932 u8 reserved_at_40[0x10]; 5933 u8 function_id[0x10]; 5934 u8 field_select[0x20]; 5935 5936 struct mlx5_ifc_other_hca_cap_bits other_capability; 5937 }; 5938 5939 struct mlx5_ifc_flow_table_context_bits { 5940 u8 reformat_en[0x1]; 5941 u8 decap_en[0x1]; 5942 u8 sw_owner[0x1]; 5943 u8 termination_table[0x1]; 5944 u8 table_miss_action[0x4]; 5945 u8 level[0x8]; 5946 u8 reserved_at_10[0x8]; 5947 u8 log_size[0x8]; 5948 5949 u8 reserved_at_20[0x8]; 5950 u8 table_miss_id[0x18]; 5951 5952 u8 reserved_at_40[0x8]; 5953 u8 lag_master_next_table_id[0x18]; 5954 5955 u8 reserved_at_60[0x60]; 5956 5957 u8 sw_owner_icm_root_1[0x40]; 5958 5959 u8 sw_owner_icm_root_0[0x40]; 5960 5961 }; 5962 5963 struct mlx5_ifc_query_flow_table_out_bits { 5964 u8 status[0x8]; 5965 u8 reserved_at_8[0x18]; 5966 5967 u8 syndrome[0x20]; 5968 5969 u8 reserved_at_40[0x80]; 5970 5971 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5972 }; 5973 5974 struct mlx5_ifc_query_flow_table_in_bits { 5975 u8 opcode[0x10]; 5976 u8 reserved_at_10[0x10]; 5977 5978 u8 reserved_at_20[0x10]; 5979 u8 op_mod[0x10]; 5980 5981 u8 reserved_at_40[0x40]; 5982 5983 u8 table_type[0x8]; 5984 u8 reserved_at_88[0x18]; 5985 5986 u8 reserved_at_a0[0x8]; 5987 u8 table_id[0x18]; 5988 5989 u8 reserved_at_c0[0x140]; 5990 }; 5991 5992 struct mlx5_ifc_query_fte_out_bits { 5993 u8 status[0x8]; 5994 u8 reserved_at_8[0x18]; 5995 5996 u8 syndrome[0x20]; 5997 5998 u8 reserved_at_40[0x1c0]; 5999 6000 struct mlx5_ifc_flow_context_bits flow_context; 6001 }; 6002 6003 struct mlx5_ifc_query_fte_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x40]; 6011 6012 u8 table_type[0x8]; 6013 u8 reserved_at_88[0x18]; 6014 6015 u8 reserved_at_a0[0x8]; 6016 u8 table_id[0x18]; 6017 6018 u8 reserved_at_c0[0x40]; 6019 6020 u8 flow_index[0x20]; 6021 6022 u8 reserved_at_120[0xe0]; 6023 }; 6024 6025 struct mlx5_ifc_match_definer_format_0_bits { 6026 u8 reserved_at_0[0x100]; 6027 6028 u8 metadata_reg_c_0[0x20]; 6029 6030 u8 metadata_reg_c_1[0x20]; 6031 6032 u8 outer_dmac_47_16[0x20]; 6033 6034 u8 outer_dmac_15_0[0x10]; 6035 u8 outer_ethertype[0x10]; 6036 6037 u8 reserved_at_180[0x1]; 6038 u8 sx_sniffer[0x1]; 6039 u8 functional_lb[0x1]; 6040 u8 outer_ip_frag[0x1]; 6041 u8 outer_qp_type[0x2]; 6042 u8 outer_encap_type[0x2]; 6043 u8 port_number[0x2]; 6044 u8 outer_l3_type[0x2]; 6045 u8 outer_l4_type[0x2]; 6046 u8 outer_first_vlan_type[0x2]; 6047 u8 outer_first_vlan_prio[0x3]; 6048 u8 outer_first_vlan_cfi[0x1]; 6049 u8 outer_first_vlan_vid[0xc]; 6050 6051 u8 outer_l4_type_ext[0x4]; 6052 u8 reserved_at_1a4[0x2]; 6053 u8 outer_ipsec_layer[0x2]; 6054 u8 outer_l2_type[0x2]; 6055 u8 force_lb[0x1]; 6056 u8 outer_l2_ok[0x1]; 6057 u8 outer_l3_ok[0x1]; 6058 u8 outer_l4_ok[0x1]; 6059 u8 outer_second_vlan_type[0x2]; 6060 u8 outer_second_vlan_prio[0x3]; 6061 u8 outer_second_vlan_cfi[0x1]; 6062 u8 outer_second_vlan_vid[0xc]; 6063 6064 u8 outer_smac_47_16[0x20]; 6065 6066 u8 outer_smac_15_0[0x10]; 6067 u8 inner_ipv4_checksum_ok[0x1]; 6068 u8 inner_l4_checksum_ok[0x1]; 6069 u8 outer_ipv4_checksum_ok[0x1]; 6070 u8 outer_l4_checksum_ok[0x1]; 6071 u8 inner_l3_ok[0x1]; 6072 u8 inner_l4_ok[0x1]; 6073 u8 outer_l3_ok_duplicate[0x1]; 6074 u8 outer_l4_ok_duplicate[0x1]; 6075 u8 outer_tcp_cwr[0x1]; 6076 u8 outer_tcp_ece[0x1]; 6077 u8 outer_tcp_urg[0x1]; 6078 u8 outer_tcp_ack[0x1]; 6079 u8 outer_tcp_psh[0x1]; 6080 u8 outer_tcp_rst[0x1]; 6081 u8 outer_tcp_syn[0x1]; 6082 u8 outer_tcp_fin[0x1]; 6083 }; 6084 6085 struct mlx5_ifc_match_definer_format_22_bits { 6086 u8 reserved_at_0[0x100]; 6087 6088 u8 outer_ip_src_addr[0x20]; 6089 6090 u8 outer_ip_dest_addr[0x20]; 6091 6092 u8 outer_l4_sport[0x10]; 6093 u8 outer_l4_dport[0x10]; 6094 6095 u8 reserved_at_160[0x1]; 6096 u8 sx_sniffer[0x1]; 6097 u8 functional_lb[0x1]; 6098 u8 outer_ip_frag[0x1]; 6099 u8 outer_qp_type[0x2]; 6100 u8 outer_encap_type[0x2]; 6101 u8 port_number[0x2]; 6102 u8 outer_l3_type[0x2]; 6103 u8 outer_l4_type[0x2]; 6104 u8 outer_first_vlan_type[0x2]; 6105 u8 outer_first_vlan_prio[0x3]; 6106 u8 outer_first_vlan_cfi[0x1]; 6107 u8 outer_first_vlan_vid[0xc]; 6108 6109 u8 metadata_reg_c_0[0x20]; 6110 6111 u8 outer_dmac_47_16[0x20]; 6112 6113 u8 outer_smac_47_16[0x20]; 6114 6115 u8 outer_smac_15_0[0x10]; 6116 u8 outer_dmac_15_0[0x10]; 6117 }; 6118 6119 struct mlx5_ifc_match_definer_format_23_bits { 6120 u8 reserved_at_0[0x100]; 6121 6122 u8 inner_ip_src_addr[0x20]; 6123 6124 u8 inner_ip_dest_addr[0x20]; 6125 6126 u8 inner_l4_sport[0x10]; 6127 u8 inner_l4_dport[0x10]; 6128 6129 u8 reserved_at_160[0x1]; 6130 u8 sx_sniffer[0x1]; 6131 u8 functional_lb[0x1]; 6132 u8 inner_ip_frag[0x1]; 6133 u8 inner_qp_type[0x2]; 6134 u8 inner_encap_type[0x2]; 6135 u8 port_number[0x2]; 6136 u8 inner_l3_type[0x2]; 6137 u8 inner_l4_type[0x2]; 6138 u8 inner_first_vlan_type[0x2]; 6139 u8 inner_first_vlan_prio[0x3]; 6140 u8 inner_first_vlan_cfi[0x1]; 6141 u8 inner_first_vlan_vid[0xc]; 6142 6143 u8 tunnel_header_0[0x20]; 6144 6145 u8 inner_dmac_47_16[0x20]; 6146 6147 u8 inner_smac_47_16[0x20]; 6148 6149 u8 inner_smac_15_0[0x10]; 6150 u8 inner_dmac_15_0[0x10]; 6151 }; 6152 6153 struct mlx5_ifc_match_definer_format_29_bits { 6154 u8 reserved_at_0[0xc0]; 6155 6156 u8 outer_ip_dest_addr[0x80]; 6157 6158 u8 outer_ip_src_addr[0x80]; 6159 6160 u8 outer_l4_sport[0x10]; 6161 u8 outer_l4_dport[0x10]; 6162 6163 u8 reserved_at_1e0[0x20]; 6164 }; 6165 6166 struct mlx5_ifc_match_definer_format_30_bits { 6167 u8 reserved_at_0[0xa0]; 6168 6169 u8 outer_ip_dest_addr[0x80]; 6170 6171 u8 outer_ip_src_addr[0x80]; 6172 6173 u8 outer_dmac_47_16[0x20]; 6174 6175 u8 outer_smac_47_16[0x20]; 6176 6177 u8 outer_smac_15_0[0x10]; 6178 u8 outer_dmac_15_0[0x10]; 6179 }; 6180 6181 struct mlx5_ifc_match_definer_format_31_bits { 6182 u8 reserved_at_0[0xc0]; 6183 6184 u8 inner_ip_dest_addr[0x80]; 6185 6186 u8 inner_ip_src_addr[0x80]; 6187 6188 u8 inner_l4_sport[0x10]; 6189 u8 inner_l4_dport[0x10]; 6190 6191 u8 reserved_at_1e0[0x20]; 6192 }; 6193 6194 struct mlx5_ifc_match_definer_format_32_bits { 6195 u8 reserved_at_0[0xa0]; 6196 6197 u8 inner_ip_dest_addr[0x80]; 6198 6199 u8 inner_ip_src_addr[0x80]; 6200 6201 u8 inner_dmac_47_16[0x20]; 6202 6203 u8 inner_smac_47_16[0x20]; 6204 6205 u8 inner_smac_15_0[0x10]; 6206 u8 inner_dmac_15_0[0x10]; 6207 }; 6208 6209 enum { 6210 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6211 }; 6212 6213 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6214 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6215 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6216 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6217 6218 struct mlx5_ifc_match_definer_match_mask_bits { 6219 u8 reserved_at_1c0[5][0x20]; 6220 u8 match_dw_8[0x20]; 6221 u8 match_dw_7[0x20]; 6222 u8 match_dw_6[0x20]; 6223 u8 match_dw_5[0x20]; 6224 u8 match_dw_4[0x20]; 6225 u8 match_dw_3[0x20]; 6226 u8 match_dw_2[0x20]; 6227 u8 match_dw_1[0x20]; 6228 u8 match_dw_0[0x20]; 6229 6230 u8 match_byte_7[0x8]; 6231 u8 match_byte_6[0x8]; 6232 u8 match_byte_5[0x8]; 6233 u8 match_byte_4[0x8]; 6234 6235 u8 match_byte_3[0x8]; 6236 u8 match_byte_2[0x8]; 6237 u8 match_byte_1[0x8]; 6238 u8 match_byte_0[0x8]; 6239 }; 6240 6241 struct mlx5_ifc_match_definer_bits { 6242 u8 modify_field_select[0x40]; 6243 6244 u8 reserved_at_40[0x40]; 6245 6246 u8 reserved_at_80[0x10]; 6247 u8 format_id[0x10]; 6248 6249 u8 reserved_at_a0[0x60]; 6250 6251 u8 format_select_dw3[0x8]; 6252 u8 format_select_dw2[0x8]; 6253 u8 format_select_dw1[0x8]; 6254 u8 format_select_dw0[0x8]; 6255 6256 u8 format_select_dw7[0x8]; 6257 u8 format_select_dw6[0x8]; 6258 u8 format_select_dw5[0x8]; 6259 u8 format_select_dw4[0x8]; 6260 6261 u8 reserved_at_100[0x18]; 6262 u8 format_select_dw8[0x8]; 6263 6264 u8 reserved_at_120[0x20]; 6265 6266 u8 format_select_byte3[0x8]; 6267 u8 format_select_byte2[0x8]; 6268 u8 format_select_byte1[0x8]; 6269 u8 format_select_byte0[0x8]; 6270 6271 u8 format_select_byte7[0x8]; 6272 u8 format_select_byte6[0x8]; 6273 u8 format_select_byte5[0x8]; 6274 u8 format_select_byte4[0x8]; 6275 6276 u8 reserved_at_180[0x40]; 6277 6278 union { 6279 struct { 6280 u8 match_mask[16][0x20]; 6281 }; 6282 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6283 }; 6284 }; 6285 6286 struct mlx5_ifc_general_obj_create_param_bits { 6287 u8 alias_object[0x1]; 6288 u8 reserved_at_1[0x2]; 6289 u8 log_obj_range[0x5]; 6290 u8 reserved_at_8[0x18]; 6291 }; 6292 6293 struct mlx5_ifc_general_obj_query_param_bits { 6294 u8 alias_object[0x1]; 6295 u8 obj_offset[0x1f]; 6296 }; 6297 6298 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6299 u8 opcode[0x10]; 6300 u8 uid[0x10]; 6301 6302 u8 vhca_tunnel_id[0x10]; 6303 u8 obj_type[0x10]; 6304 6305 u8 obj_id[0x20]; 6306 6307 union { 6308 struct mlx5_ifc_general_obj_create_param_bits create; 6309 struct mlx5_ifc_general_obj_query_param_bits query; 6310 } op_param; 6311 }; 6312 6313 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6314 u8 status[0x8]; 6315 u8 reserved_at_8[0x18]; 6316 6317 u8 syndrome[0x20]; 6318 6319 u8 obj_id[0x20]; 6320 6321 u8 reserved_at_60[0x20]; 6322 }; 6323 6324 struct mlx5_ifc_create_match_definer_in_bits { 6325 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6326 6327 struct mlx5_ifc_match_definer_bits obj_context; 6328 }; 6329 6330 struct mlx5_ifc_create_match_definer_out_bits { 6331 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6332 }; 6333 6334 enum { 6335 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6336 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6337 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6338 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6339 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6340 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6341 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6342 }; 6343 6344 struct mlx5_ifc_query_flow_group_out_bits { 6345 u8 status[0x8]; 6346 u8 reserved_at_8[0x18]; 6347 6348 u8 syndrome[0x20]; 6349 6350 u8 reserved_at_40[0xa0]; 6351 6352 u8 start_flow_index[0x20]; 6353 6354 u8 reserved_at_100[0x20]; 6355 6356 u8 end_flow_index[0x20]; 6357 6358 u8 reserved_at_140[0xa0]; 6359 6360 u8 reserved_at_1e0[0x18]; 6361 u8 match_criteria_enable[0x8]; 6362 6363 struct mlx5_ifc_fte_match_param_bits match_criteria; 6364 6365 u8 reserved_at_1200[0xe00]; 6366 }; 6367 6368 struct mlx5_ifc_query_flow_group_in_bits { 6369 u8 opcode[0x10]; 6370 u8 reserved_at_10[0x10]; 6371 6372 u8 reserved_at_20[0x10]; 6373 u8 op_mod[0x10]; 6374 6375 u8 reserved_at_40[0x40]; 6376 6377 u8 table_type[0x8]; 6378 u8 reserved_at_88[0x18]; 6379 6380 u8 reserved_at_a0[0x8]; 6381 u8 table_id[0x18]; 6382 6383 u8 group_id[0x20]; 6384 6385 u8 reserved_at_e0[0x120]; 6386 }; 6387 6388 struct mlx5_ifc_query_flow_counter_out_bits { 6389 u8 status[0x8]; 6390 u8 reserved_at_8[0x18]; 6391 6392 u8 syndrome[0x20]; 6393 6394 u8 reserved_at_40[0x40]; 6395 6396 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6397 }; 6398 6399 struct mlx5_ifc_query_flow_counter_in_bits { 6400 u8 opcode[0x10]; 6401 u8 reserved_at_10[0x10]; 6402 6403 u8 reserved_at_20[0x10]; 6404 u8 op_mod[0x10]; 6405 6406 u8 reserved_at_40[0x80]; 6407 6408 u8 clear[0x1]; 6409 u8 reserved_at_c1[0xf]; 6410 u8 num_of_counters[0x10]; 6411 6412 u8 flow_counter_id[0x20]; 6413 }; 6414 6415 struct mlx5_ifc_query_esw_vport_context_out_bits { 6416 u8 status[0x8]; 6417 u8 reserved_at_8[0x18]; 6418 6419 u8 syndrome[0x20]; 6420 6421 u8 reserved_at_40[0x40]; 6422 6423 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6424 }; 6425 6426 struct mlx5_ifc_query_esw_vport_context_in_bits { 6427 u8 opcode[0x10]; 6428 u8 reserved_at_10[0x10]; 6429 6430 u8 reserved_at_20[0x10]; 6431 u8 op_mod[0x10]; 6432 6433 u8 other_vport[0x1]; 6434 u8 reserved_at_41[0xf]; 6435 u8 vport_number[0x10]; 6436 6437 u8 reserved_at_60[0x20]; 6438 }; 6439 6440 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6441 u8 status[0x8]; 6442 u8 reserved_at_8[0x18]; 6443 6444 u8 syndrome[0x20]; 6445 6446 u8 reserved_at_40[0x40]; 6447 }; 6448 6449 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6450 u8 reserved_at_0[0x1b]; 6451 u8 fdb_to_vport_reg_c_id[0x1]; 6452 u8 vport_cvlan_insert[0x1]; 6453 u8 vport_svlan_insert[0x1]; 6454 u8 vport_cvlan_strip[0x1]; 6455 u8 vport_svlan_strip[0x1]; 6456 }; 6457 6458 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6459 u8 opcode[0x10]; 6460 u8 reserved_at_10[0x10]; 6461 6462 u8 reserved_at_20[0x10]; 6463 u8 op_mod[0x10]; 6464 6465 u8 other_vport[0x1]; 6466 u8 reserved_at_41[0xf]; 6467 u8 vport_number[0x10]; 6468 6469 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6470 6471 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6472 }; 6473 6474 struct mlx5_ifc_query_eq_out_bits { 6475 u8 status[0x8]; 6476 u8 reserved_at_8[0x18]; 6477 6478 u8 syndrome[0x20]; 6479 6480 u8 reserved_at_40[0x40]; 6481 6482 struct mlx5_ifc_eqc_bits eq_context_entry; 6483 6484 u8 reserved_at_280[0x40]; 6485 6486 u8 event_bitmask[0x40]; 6487 6488 u8 reserved_at_300[0x580]; 6489 6490 u8 pas[][0x40]; 6491 }; 6492 6493 struct mlx5_ifc_query_eq_in_bits { 6494 u8 opcode[0x10]; 6495 u8 reserved_at_10[0x10]; 6496 6497 u8 reserved_at_20[0x10]; 6498 u8 op_mod[0x10]; 6499 6500 u8 reserved_at_40[0x18]; 6501 u8 eq_number[0x8]; 6502 6503 u8 reserved_at_60[0x20]; 6504 }; 6505 6506 struct mlx5_ifc_packet_reformat_context_in_bits { 6507 u8 reformat_type[0x8]; 6508 u8 reserved_at_8[0x4]; 6509 u8 reformat_param_0[0x4]; 6510 u8 reserved_at_10[0x6]; 6511 u8 reformat_data_size[0xa]; 6512 6513 u8 reformat_param_1[0x8]; 6514 u8 reserved_at_28[0x8]; 6515 u8 reformat_data[2][0x8]; 6516 6517 u8 more_reformat_data[][0x8]; 6518 }; 6519 6520 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6521 u8 status[0x8]; 6522 u8 reserved_at_8[0x18]; 6523 6524 u8 syndrome[0x20]; 6525 6526 u8 reserved_at_40[0xa0]; 6527 6528 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6529 }; 6530 6531 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6532 u8 opcode[0x10]; 6533 u8 reserved_at_10[0x10]; 6534 6535 u8 reserved_at_20[0x10]; 6536 u8 op_mod[0x10]; 6537 6538 u8 packet_reformat_id[0x20]; 6539 6540 u8 reserved_at_60[0xa0]; 6541 }; 6542 6543 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6544 u8 status[0x8]; 6545 u8 reserved_at_8[0x18]; 6546 6547 u8 syndrome[0x20]; 6548 6549 u8 packet_reformat_id[0x20]; 6550 6551 u8 reserved_at_60[0x20]; 6552 }; 6553 6554 enum { 6555 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6556 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6557 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6558 }; 6559 6560 enum mlx5_reformat_ctx_type { 6561 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6562 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6563 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6564 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6565 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6566 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6567 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6568 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6569 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6570 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6571 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6572 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6573 }; 6574 6575 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6576 u8 opcode[0x10]; 6577 u8 reserved_at_10[0x10]; 6578 6579 u8 reserved_at_20[0x10]; 6580 u8 op_mod[0x10]; 6581 6582 u8 reserved_at_40[0xa0]; 6583 6584 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6585 }; 6586 6587 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6588 u8 status[0x8]; 6589 u8 reserved_at_8[0x18]; 6590 6591 u8 syndrome[0x20]; 6592 6593 u8 reserved_at_40[0x40]; 6594 }; 6595 6596 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6597 u8 opcode[0x10]; 6598 u8 reserved_at_10[0x10]; 6599 6600 u8 reserved_20[0x10]; 6601 u8 op_mod[0x10]; 6602 6603 u8 packet_reformat_id[0x20]; 6604 6605 u8 reserved_60[0x20]; 6606 }; 6607 6608 struct mlx5_ifc_set_action_in_bits { 6609 u8 action_type[0x4]; 6610 u8 field[0xc]; 6611 u8 reserved_at_10[0x3]; 6612 u8 offset[0x5]; 6613 u8 reserved_at_18[0x3]; 6614 u8 length[0x5]; 6615 6616 u8 data[0x20]; 6617 }; 6618 6619 struct mlx5_ifc_add_action_in_bits { 6620 u8 action_type[0x4]; 6621 u8 field[0xc]; 6622 u8 reserved_at_10[0x10]; 6623 6624 u8 data[0x20]; 6625 }; 6626 6627 struct mlx5_ifc_copy_action_in_bits { 6628 u8 action_type[0x4]; 6629 u8 src_field[0xc]; 6630 u8 reserved_at_10[0x3]; 6631 u8 src_offset[0x5]; 6632 u8 reserved_at_18[0x3]; 6633 u8 length[0x5]; 6634 6635 u8 reserved_at_20[0x4]; 6636 u8 dst_field[0xc]; 6637 u8 reserved_at_30[0x3]; 6638 u8 dst_offset[0x5]; 6639 u8 reserved_at_38[0x8]; 6640 }; 6641 6642 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6643 struct mlx5_ifc_set_action_in_bits set_action_in; 6644 struct mlx5_ifc_add_action_in_bits add_action_in; 6645 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6646 u8 reserved_at_0[0x40]; 6647 }; 6648 6649 enum { 6650 MLX5_ACTION_TYPE_SET = 0x1, 6651 MLX5_ACTION_TYPE_ADD = 0x2, 6652 MLX5_ACTION_TYPE_COPY = 0x3, 6653 }; 6654 6655 enum { 6656 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6657 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6658 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6659 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6660 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6661 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6662 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6663 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6664 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6665 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6666 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6667 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6668 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6669 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6670 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6671 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6672 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6673 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6674 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6675 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6676 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6677 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6678 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6679 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6680 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6681 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6682 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6683 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6684 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6685 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6686 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6687 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6688 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6689 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6690 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6691 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6692 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6693 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6694 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6695 }; 6696 6697 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6698 u8 status[0x8]; 6699 u8 reserved_at_8[0x18]; 6700 6701 u8 syndrome[0x20]; 6702 6703 u8 modify_header_id[0x20]; 6704 6705 u8 reserved_at_60[0x20]; 6706 }; 6707 6708 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6709 u8 opcode[0x10]; 6710 u8 reserved_at_10[0x10]; 6711 6712 u8 reserved_at_20[0x10]; 6713 u8 op_mod[0x10]; 6714 6715 u8 reserved_at_40[0x20]; 6716 6717 u8 table_type[0x8]; 6718 u8 reserved_at_68[0x10]; 6719 u8 num_of_actions[0x8]; 6720 6721 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6722 }; 6723 6724 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6725 u8 status[0x8]; 6726 u8 reserved_at_8[0x18]; 6727 6728 u8 syndrome[0x20]; 6729 6730 u8 reserved_at_40[0x40]; 6731 }; 6732 6733 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6734 u8 opcode[0x10]; 6735 u8 reserved_at_10[0x10]; 6736 6737 u8 reserved_at_20[0x10]; 6738 u8 op_mod[0x10]; 6739 6740 u8 modify_header_id[0x20]; 6741 6742 u8 reserved_at_60[0x20]; 6743 }; 6744 6745 struct mlx5_ifc_query_modify_header_context_in_bits { 6746 u8 opcode[0x10]; 6747 u8 uid[0x10]; 6748 6749 u8 reserved_at_20[0x10]; 6750 u8 op_mod[0x10]; 6751 6752 u8 modify_header_id[0x20]; 6753 6754 u8 reserved_at_60[0xa0]; 6755 }; 6756 6757 struct mlx5_ifc_query_dct_out_bits { 6758 u8 status[0x8]; 6759 u8 reserved_at_8[0x18]; 6760 6761 u8 syndrome[0x20]; 6762 6763 u8 reserved_at_40[0x40]; 6764 6765 struct mlx5_ifc_dctc_bits dct_context_entry; 6766 6767 u8 reserved_at_280[0x180]; 6768 }; 6769 6770 struct mlx5_ifc_query_dct_in_bits { 6771 u8 opcode[0x10]; 6772 u8 reserved_at_10[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 reserved_at_40[0x8]; 6778 u8 dctn[0x18]; 6779 6780 u8 reserved_at_60[0x20]; 6781 }; 6782 6783 struct mlx5_ifc_query_cq_out_bits { 6784 u8 status[0x8]; 6785 u8 reserved_at_8[0x18]; 6786 6787 u8 syndrome[0x20]; 6788 6789 u8 reserved_at_40[0x40]; 6790 6791 struct mlx5_ifc_cqc_bits cq_context; 6792 6793 u8 reserved_at_280[0x600]; 6794 6795 u8 pas[][0x40]; 6796 }; 6797 6798 struct mlx5_ifc_query_cq_in_bits { 6799 u8 opcode[0x10]; 6800 u8 reserved_at_10[0x10]; 6801 6802 u8 reserved_at_20[0x10]; 6803 u8 op_mod[0x10]; 6804 6805 u8 reserved_at_40[0x8]; 6806 u8 cqn[0x18]; 6807 6808 u8 reserved_at_60[0x20]; 6809 }; 6810 6811 struct mlx5_ifc_query_cong_status_out_bits { 6812 u8 status[0x8]; 6813 u8 reserved_at_8[0x18]; 6814 6815 u8 syndrome[0x20]; 6816 6817 u8 reserved_at_40[0x20]; 6818 6819 u8 enable[0x1]; 6820 u8 tag_enable[0x1]; 6821 u8 reserved_at_62[0x1e]; 6822 }; 6823 6824 struct mlx5_ifc_query_cong_status_in_bits { 6825 u8 opcode[0x10]; 6826 u8 reserved_at_10[0x10]; 6827 6828 u8 reserved_at_20[0x10]; 6829 u8 op_mod[0x10]; 6830 6831 u8 reserved_at_40[0x18]; 6832 u8 priority[0x4]; 6833 u8 cong_protocol[0x4]; 6834 6835 u8 reserved_at_60[0x20]; 6836 }; 6837 6838 struct mlx5_ifc_query_cong_statistics_out_bits { 6839 u8 status[0x8]; 6840 u8 reserved_at_8[0x18]; 6841 6842 u8 syndrome[0x20]; 6843 6844 u8 reserved_at_40[0x40]; 6845 6846 u8 rp_cur_flows[0x20]; 6847 6848 u8 sum_flows[0x20]; 6849 6850 u8 rp_cnp_ignored_high[0x20]; 6851 6852 u8 rp_cnp_ignored_low[0x20]; 6853 6854 u8 rp_cnp_handled_high[0x20]; 6855 6856 u8 rp_cnp_handled_low[0x20]; 6857 6858 u8 reserved_at_140[0x100]; 6859 6860 u8 time_stamp_high[0x20]; 6861 6862 u8 time_stamp_low[0x20]; 6863 6864 u8 accumulators_period[0x20]; 6865 6866 u8 np_ecn_marked_roce_packets_high[0x20]; 6867 6868 u8 np_ecn_marked_roce_packets_low[0x20]; 6869 6870 u8 np_cnp_sent_high[0x20]; 6871 6872 u8 np_cnp_sent_low[0x20]; 6873 6874 u8 reserved_at_320[0x560]; 6875 }; 6876 6877 struct mlx5_ifc_query_cong_statistics_in_bits { 6878 u8 opcode[0x10]; 6879 u8 reserved_at_10[0x10]; 6880 6881 u8 reserved_at_20[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 clear[0x1]; 6885 u8 reserved_at_41[0x1f]; 6886 6887 u8 reserved_at_60[0x20]; 6888 }; 6889 6890 struct mlx5_ifc_query_cong_params_out_bits { 6891 u8 status[0x8]; 6892 u8 reserved_at_8[0x18]; 6893 6894 u8 syndrome[0x20]; 6895 6896 u8 reserved_at_40[0x40]; 6897 6898 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6899 }; 6900 6901 struct mlx5_ifc_query_cong_params_in_bits { 6902 u8 opcode[0x10]; 6903 u8 reserved_at_10[0x10]; 6904 6905 u8 reserved_at_20[0x10]; 6906 u8 op_mod[0x10]; 6907 6908 u8 reserved_at_40[0x1c]; 6909 u8 cong_protocol[0x4]; 6910 6911 u8 reserved_at_60[0x20]; 6912 }; 6913 6914 struct mlx5_ifc_query_adapter_out_bits { 6915 u8 status[0x8]; 6916 u8 reserved_at_8[0x18]; 6917 6918 u8 syndrome[0x20]; 6919 6920 u8 reserved_at_40[0x40]; 6921 6922 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6923 }; 6924 6925 struct mlx5_ifc_query_adapter_in_bits { 6926 u8 opcode[0x10]; 6927 u8 reserved_at_10[0x10]; 6928 6929 u8 reserved_at_20[0x10]; 6930 u8 op_mod[0x10]; 6931 6932 u8 reserved_at_40[0x40]; 6933 }; 6934 6935 struct mlx5_ifc_qp_2rst_out_bits { 6936 u8 status[0x8]; 6937 u8 reserved_at_8[0x18]; 6938 6939 u8 syndrome[0x20]; 6940 6941 u8 reserved_at_40[0x40]; 6942 }; 6943 6944 struct mlx5_ifc_qp_2rst_in_bits { 6945 u8 opcode[0x10]; 6946 u8 uid[0x10]; 6947 6948 u8 reserved_at_20[0x10]; 6949 u8 op_mod[0x10]; 6950 6951 u8 reserved_at_40[0x8]; 6952 u8 qpn[0x18]; 6953 6954 u8 reserved_at_60[0x20]; 6955 }; 6956 6957 struct mlx5_ifc_qp_2err_out_bits { 6958 u8 status[0x8]; 6959 u8 reserved_at_8[0x18]; 6960 6961 u8 syndrome[0x20]; 6962 6963 u8 reserved_at_40[0x40]; 6964 }; 6965 6966 struct mlx5_ifc_qp_2err_in_bits { 6967 u8 opcode[0x10]; 6968 u8 uid[0x10]; 6969 6970 u8 reserved_at_20[0x10]; 6971 u8 op_mod[0x10]; 6972 6973 u8 reserved_at_40[0x8]; 6974 u8 qpn[0x18]; 6975 6976 u8 reserved_at_60[0x20]; 6977 }; 6978 6979 struct mlx5_ifc_page_fault_resume_out_bits { 6980 u8 status[0x8]; 6981 u8 reserved_at_8[0x18]; 6982 6983 u8 syndrome[0x20]; 6984 6985 u8 reserved_at_40[0x40]; 6986 }; 6987 6988 struct mlx5_ifc_page_fault_resume_in_bits { 6989 u8 opcode[0x10]; 6990 u8 reserved_at_10[0x10]; 6991 6992 u8 reserved_at_20[0x10]; 6993 u8 op_mod[0x10]; 6994 6995 u8 error[0x1]; 6996 u8 reserved_at_41[0x4]; 6997 u8 page_fault_type[0x3]; 6998 u8 wq_number[0x18]; 6999 7000 u8 reserved_at_60[0x8]; 7001 u8 token[0x18]; 7002 }; 7003 7004 struct mlx5_ifc_nop_out_bits { 7005 u8 status[0x8]; 7006 u8 reserved_at_8[0x18]; 7007 7008 u8 syndrome[0x20]; 7009 7010 u8 reserved_at_40[0x40]; 7011 }; 7012 7013 struct mlx5_ifc_nop_in_bits { 7014 u8 opcode[0x10]; 7015 u8 reserved_at_10[0x10]; 7016 7017 u8 reserved_at_20[0x10]; 7018 u8 op_mod[0x10]; 7019 7020 u8 reserved_at_40[0x40]; 7021 }; 7022 7023 struct mlx5_ifc_modify_vport_state_out_bits { 7024 u8 status[0x8]; 7025 u8 reserved_at_8[0x18]; 7026 7027 u8 syndrome[0x20]; 7028 7029 u8 reserved_at_40[0x40]; 7030 }; 7031 7032 struct mlx5_ifc_modify_vport_state_in_bits { 7033 u8 opcode[0x10]; 7034 u8 reserved_at_10[0x10]; 7035 7036 u8 reserved_at_20[0x10]; 7037 u8 op_mod[0x10]; 7038 7039 u8 other_vport[0x1]; 7040 u8 reserved_at_41[0xf]; 7041 u8 vport_number[0x10]; 7042 7043 u8 reserved_at_60[0x18]; 7044 u8 admin_state[0x4]; 7045 u8 reserved_at_7c[0x4]; 7046 }; 7047 7048 struct mlx5_ifc_modify_tis_out_bits { 7049 u8 status[0x8]; 7050 u8 reserved_at_8[0x18]; 7051 7052 u8 syndrome[0x20]; 7053 7054 u8 reserved_at_40[0x40]; 7055 }; 7056 7057 struct mlx5_ifc_modify_tis_bitmask_bits { 7058 u8 reserved_at_0[0x20]; 7059 7060 u8 reserved_at_20[0x1d]; 7061 u8 lag_tx_port_affinity[0x1]; 7062 u8 strict_lag_tx_port_affinity[0x1]; 7063 u8 prio[0x1]; 7064 }; 7065 7066 struct mlx5_ifc_modify_tis_in_bits { 7067 u8 opcode[0x10]; 7068 u8 uid[0x10]; 7069 7070 u8 reserved_at_20[0x10]; 7071 u8 op_mod[0x10]; 7072 7073 u8 reserved_at_40[0x8]; 7074 u8 tisn[0x18]; 7075 7076 u8 reserved_at_60[0x20]; 7077 7078 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7079 7080 u8 reserved_at_c0[0x40]; 7081 7082 struct mlx5_ifc_tisc_bits ctx; 7083 }; 7084 7085 struct mlx5_ifc_modify_tir_bitmask_bits { 7086 u8 reserved_at_0[0x20]; 7087 7088 u8 reserved_at_20[0x1b]; 7089 u8 self_lb_en[0x1]; 7090 u8 reserved_at_3c[0x1]; 7091 u8 hash[0x1]; 7092 u8 reserved_at_3e[0x1]; 7093 u8 packet_merge[0x1]; 7094 }; 7095 7096 struct mlx5_ifc_modify_tir_out_bits { 7097 u8 status[0x8]; 7098 u8 reserved_at_8[0x18]; 7099 7100 u8 syndrome[0x20]; 7101 7102 u8 reserved_at_40[0x40]; 7103 }; 7104 7105 struct mlx5_ifc_modify_tir_in_bits { 7106 u8 opcode[0x10]; 7107 u8 uid[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 reserved_at_40[0x8]; 7113 u8 tirn[0x18]; 7114 7115 u8 reserved_at_60[0x20]; 7116 7117 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7118 7119 u8 reserved_at_c0[0x40]; 7120 7121 struct mlx5_ifc_tirc_bits ctx; 7122 }; 7123 7124 struct mlx5_ifc_modify_sq_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x40]; 7131 }; 7132 7133 struct mlx5_ifc_modify_sq_in_bits { 7134 u8 opcode[0x10]; 7135 u8 uid[0x10]; 7136 7137 u8 reserved_at_20[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 sq_state[0x4]; 7141 u8 reserved_at_44[0x4]; 7142 u8 sqn[0x18]; 7143 7144 u8 reserved_at_60[0x20]; 7145 7146 u8 modify_bitmask[0x40]; 7147 7148 u8 reserved_at_c0[0x40]; 7149 7150 struct mlx5_ifc_sqc_bits ctx; 7151 }; 7152 7153 struct mlx5_ifc_modify_scheduling_element_out_bits { 7154 u8 status[0x8]; 7155 u8 reserved_at_8[0x18]; 7156 7157 u8 syndrome[0x20]; 7158 7159 u8 reserved_at_40[0x1c0]; 7160 }; 7161 7162 enum { 7163 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7164 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7165 }; 7166 7167 struct mlx5_ifc_modify_scheduling_element_in_bits { 7168 u8 opcode[0x10]; 7169 u8 reserved_at_10[0x10]; 7170 7171 u8 reserved_at_20[0x10]; 7172 u8 op_mod[0x10]; 7173 7174 u8 scheduling_hierarchy[0x8]; 7175 u8 reserved_at_48[0x18]; 7176 7177 u8 scheduling_element_id[0x20]; 7178 7179 u8 reserved_at_80[0x20]; 7180 7181 u8 modify_bitmask[0x20]; 7182 7183 u8 reserved_at_c0[0x40]; 7184 7185 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7186 7187 u8 reserved_at_300[0x100]; 7188 }; 7189 7190 struct mlx5_ifc_modify_rqt_out_bits { 7191 u8 status[0x8]; 7192 u8 reserved_at_8[0x18]; 7193 7194 u8 syndrome[0x20]; 7195 7196 u8 reserved_at_40[0x40]; 7197 }; 7198 7199 struct mlx5_ifc_rqt_bitmask_bits { 7200 u8 reserved_at_0[0x20]; 7201 7202 u8 reserved_at_20[0x1f]; 7203 u8 rqn_list[0x1]; 7204 }; 7205 7206 struct mlx5_ifc_modify_rqt_in_bits { 7207 u8 opcode[0x10]; 7208 u8 uid[0x10]; 7209 7210 u8 reserved_at_20[0x10]; 7211 u8 op_mod[0x10]; 7212 7213 u8 reserved_at_40[0x8]; 7214 u8 rqtn[0x18]; 7215 7216 u8 reserved_at_60[0x20]; 7217 7218 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7219 7220 u8 reserved_at_c0[0x40]; 7221 7222 struct mlx5_ifc_rqtc_bits ctx; 7223 }; 7224 7225 struct mlx5_ifc_modify_rq_out_bits { 7226 u8 status[0x8]; 7227 u8 reserved_at_8[0x18]; 7228 7229 u8 syndrome[0x20]; 7230 7231 u8 reserved_at_40[0x40]; 7232 }; 7233 7234 enum { 7235 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7236 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7237 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7238 }; 7239 7240 struct mlx5_ifc_modify_rq_in_bits { 7241 u8 opcode[0x10]; 7242 u8 uid[0x10]; 7243 7244 u8 reserved_at_20[0x10]; 7245 u8 op_mod[0x10]; 7246 7247 u8 rq_state[0x4]; 7248 u8 reserved_at_44[0x4]; 7249 u8 rqn[0x18]; 7250 7251 u8 reserved_at_60[0x20]; 7252 7253 u8 modify_bitmask[0x40]; 7254 7255 u8 reserved_at_c0[0x40]; 7256 7257 struct mlx5_ifc_rqc_bits ctx; 7258 }; 7259 7260 struct mlx5_ifc_modify_rmp_out_bits { 7261 u8 status[0x8]; 7262 u8 reserved_at_8[0x18]; 7263 7264 u8 syndrome[0x20]; 7265 7266 u8 reserved_at_40[0x40]; 7267 }; 7268 7269 struct mlx5_ifc_rmp_bitmask_bits { 7270 u8 reserved_at_0[0x20]; 7271 7272 u8 reserved_at_20[0x1f]; 7273 u8 lwm[0x1]; 7274 }; 7275 7276 struct mlx5_ifc_modify_rmp_in_bits { 7277 u8 opcode[0x10]; 7278 u8 uid[0x10]; 7279 7280 u8 reserved_at_20[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 rmp_state[0x4]; 7284 u8 reserved_at_44[0x4]; 7285 u8 rmpn[0x18]; 7286 7287 u8 reserved_at_60[0x20]; 7288 7289 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7290 7291 u8 reserved_at_c0[0x40]; 7292 7293 struct mlx5_ifc_rmpc_bits ctx; 7294 }; 7295 7296 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7297 u8 status[0x8]; 7298 u8 reserved_at_8[0x18]; 7299 7300 u8 syndrome[0x20]; 7301 7302 u8 reserved_at_40[0x40]; 7303 }; 7304 7305 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7306 u8 reserved_at_0[0x12]; 7307 u8 affiliation[0x1]; 7308 u8 reserved_at_13[0x1]; 7309 u8 disable_uc_local_lb[0x1]; 7310 u8 disable_mc_local_lb[0x1]; 7311 u8 node_guid[0x1]; 7312 u8 port_guid[0x1]; 7313 u8 min_inline[0x1]; 7314 u8 mtu[0x1]; 7315 u8 change_event[0x1]; 7316 u8 promisc[0x1]; 7317 u8 permanent_address[0x1]; 7318 u8 addresses_list[0x1]; 7319 u8 roce_en[0x1]; 7320 u8 reserved_at_1f[0x1]; 7321 }; 7322 7323 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7324 u8 opcode[0x10]; 7325 u8 reserved_at_10[0x10]; 7326 7327 u8 reserved_at_20[0x10]; 7328 u8 op_mod[0x10]; 7329 7330 u8 other_vport[0x1]; 7331 u8 reserved_at_41[0xf]; 7332 u8 vport_number[0x10]; 7333 7334 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7335 7336 u8 reserved_at_80[0x780]; 7337 7338 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7339 }; 7340 7341 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7342 u8 status[0x8]; 7343 u8 reserved_at_8[0x18]; 7344 7345 u8 syndrome[0x20]; 7346 7347 u8 reserved_at_40[0x40]; 7348 }; 7349 7350 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7351 u8 opcode[0x10]; 7352 u8 reserved_at_10[0x10]; 7353 7354 u8 reserved_at_20[0x10]; 7355 u8 op_mod[0x10]; 7356 7357 u8 other_vport[0x1]; 7358 u8 reserved_at_41[0xb]; 7359 u8 port_num[0x4]; 7360 u8 vport_number[0x10]; 7361 7362 u8 reserved_at_60[0x20]; 7363 7364 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7365 }; 7366 7367 struct mlx5_ifc_modify_cq_out_bits { 7368 u8 status[0x8]; 7369 u8 reserved_at_8[0x18]; 7370 7371 u8 syndrome[0x20]; 7372 7373 u8 reserved_at_40[0x40]; 7374 }; 7375 7376 enum { 7377 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7378 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7379 }; 7380 7381 struct mlx5_ifc_modify_cq_in_bits { 7382 u8 opcode[0x10]; 7383 u8 uid[0x10]; 7384 7385 u8 reserved_at_20[0x10]; 7386 u8 op_mod[0x10]; 7387 7388 u8 reserved_at_40[0x8]; 7389 u8 cqn[0x18]; 7390 7391 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7392 7393 struct mlx5_ifc_cqc_bits cq_context; 7394 7395 u8 reserved_at_280[0x60]; 7396 7397 u8 cq_umem_valid[0x1]; 7398 u8 reserved_at_2e1[0x1f]; 7399 7400 u8 reserved_at_300[0x580]; 7401 7402 u8 pas[][0x40]; 7403 }; 7404 7405 struct mlx5_ifc_modify_cong_status_out_bits { 7406 u8 status[0x8]; 7407 u8 reserved_at_8[0x18]; 7408 7409 u8 syndrome[0x20]; 7410 7411 u8 reserved_at_40[0x40]; 7412 }; 7413 7414 struct mlx5_ifc_modify_cong_status_in_bits { 7415 u8 opcode[0x10]; 7416 u8 reserved_at_10[0x10]; 7417 7418 u8 reserved_at_20[0x10]; 7419 u8 op_mod[0x10]; 7420 7421 u8 reserved_at_40[0x18]; 7422 u8 priority[0x4]; 7423 u8 cong_protocol[0x4]; 7424 7425 u8 enable[0x1]; 7426 u8 tag_enable[0x1]; 7427 u8 reserved_at_62[0x1e]; 7428 }; 7429 7430 struct mlx5_ifc_modify_cong_params_out_bits { 7431 u8 status[0x8]; 7432 u8 reserved_at_8[0x18]; 7433 7434 u8 syndrome[0x20]; 7435 7436 u8 reserved_at_40[0x40]; 7437 }; 7438 7439 struct mlx5_ifc_modify_cong_params_in_bits { 7440 u8 opcode[0x10]; 7441 u8 reserved_at_10[0x10]; 7442 7443 u8 reserved_at_20[0x10]; 7444 u8 op_mod[0x10]; 7445 7446 u8 reserved_at_40[0x1c]; 7447 u8 cong_protocol[0x4]; 7448 7449 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7450 7451 u8 reserved_at_80[0x80]; 7452 7453 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7454 }; 7455 7456 struct mlx5_ifc_manage_pages_out_bits { 7457 u8 status[0x8]; 7458 u8 reserved_at_8[0x18]; 7459 7460 u8 syndrome[0x20]; 7461 7462 u8 output_num_entries[0x20]; 7463 7464 u8 reserved_at_60[0x20]; 7465 7466 u8 pas[][0x40]; 7467 }; 7468 7469 enum { 7470 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7471 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7472 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7473 }; 7474 7475 struct mlx5_ifc_manage_pages_in_bits { 7476 u8 opcode[0x10]; 7477 u8 reserved_at_10[0x10]; 7478 7479 u8 reserved_at_20[0x10]; 7480 u8 op_mod[0x10]; 7481 7482 u8 embedded_cpu_function[0x1]; 7483 u8 reserved_at_41[0xf]; 7484 u8 function_id[0x10]; 7485 7486 u8 input_num_entries[0x20]; 7487 7488 u8 pas[][0x40]; 7489 }; 7490 7491 struct mlx5_ifc_mad_ifc_out_bits { 7492 u8 status[0x8]; 7493 u8 reserved_at_8[0x18]; 7494 7495 u8 syndrome[0x20]; 7496 7497 u8 reserved_at_40[0x40]; 7498 7499 u8 response_mad_packet[256][0x8]; 7500 }; 7501 7502 struct mlx5_ifc_mad_ifc_in_bits { 7503 u8 opcode[0x10]; 7504 u8 reserved_at_10[0x10]; 7505 7506 u8 reserved_at_20[0x10]; 7507 u8 op_mod[0x10]; 7508 7509 u8 remote_lid[0x10]; 7510 u8 reserved_at_50[0x8]; 7511 u8 port[0x8]; 7512 7513 u8 reserved_at_60[0x20]; 7514 7515 u8 mad[256][0x8]; 7516 }; 7517 7518 struct mlx5_ifc_init_hca_out_bits { 7519 u8 status[0x8]; 7520 u8 reserved_at_8[0x18]; 7521 7522 u8 syndrome[0x20]; 7523 7524 u8 reserved_at_40[0x40]; 7525 }; 7526 7527 struct mlx5_ifc_init_hca_in_bits { 7528 u8 opcode[0x10]; 7529 u8 reserved_at_10[0x10]; 7530 7531 u8 reserved_at_20[0x10]; 7532 u8 op_mod[0x10]; 7533 7534 u8 reserved_at_40[0x20]; 7535 7536 u8 reserved_at_60[0x2]; 7537 u8 sw_vhca_id[0xe]; 7538 u8 reserved_at_70[0x10]; 7539 7540 u8 sw_owner_id[4][0x20]; 7541 }; 7542 7543 struct mlx5_ifc_init2rtr_qp_out_bits { 7544 u8 status[0x8]; 7545 u8 reserved_at_8[0x18]; 7546 7547 u8 syndrome[0x20]; 7548 7549 u8 reserved_at_40[0x20]; 7550 u8 ece[0x20]; 7551 }; 7552 7553 struct mlx5_ifc_init2rtr_qp_in_bits { 7554 u8 opcode[0x10]; 7555 u8 uid[0x10]; 7556 7557 u8 reserved_at_20[0x10]; 7558 u8 op_mod[0x10]; 7559 7560 u8 reserved_at_40[0x8]; 7561 u8 qpn[0x18]; 7562 7563 u8 reserved_at_60[0x20]; 7564 7565 u8 opt_param_mask[0x20]; 7566 7567 u8 ece[0x20]; 7568 7569 struct mlx5_ifc_qpc_bits qpc; 7570 7571 u8 reserved_at_800[0x80]; 7572 }; 7573 7574 struct mlx5_ifc_init2init_qp_out_bits { 7575 u8 status[0x8]; 7576 u8 reserved_at_8[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 reserved_at_40[0x20]; 7581 u8 ece[0x20]; 7582 }; 7583 7584 struct mlx5_ifc_init2init_qp_in_bits { 7585 u8 opcode[0x10]; 7586 u8 uid[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 reserved_at_40[0x8]; 7592 u8 qpn[0x18]; 7593 7594 u8 reserved_at_60[0x20]; 7595 7596 u8 opt_param_mask[0x20]; 7597 7598 u8 ece[0x20]; 7599 7600 struct mlx5_ifc_qpc_bits qpc; 7601 7602 u8 reserved_at_800[0x80]; 7603 }; 7604 7605 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_at_8[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_at_40[0x40]; 7612 7613 u8 packet_headers_log[128][0x8]; 7614 7615 u8 packet_syndrome[64][0x8]; 7616 }; 7617 7618 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7619 u8 opcode[0x10]; 7620 u8 reserved_at_10[0x10]; 7621 7622 u8 reserved_at_20[0x10]; 7623 u8 op_mod[0x10]; 7624 7625 u8 reserved_at_40[0x40]; 7626 }; 7627 7628 struct mlx5_ifc_gen_eqe_in_bits { 7629 u8 opcode[0x10]; 7630 u8 reserved_at_10[0x10]; 7631 7632 u8 reserved_at_20[0x10]; 7633 u8 op_mod[0x10]; 7634 7635 u8 reserved_at_40[0x18]; 7636 u8 eq_number[0x8]; 7637 7638 u8 reserved_at_60[0x20]; 7639 7640 u8 eqe[64][0x8]; 7641 }; 7642 7643 struct mlx5_ifc_gen_eq_out_bits { 7644 u8 status[0x8]; 7645 u8 reserved_at_8[0x18]; 7646 7647 u8 syndrome[0x20]; 7648 7649 u8 reserved_at_40[0x40]; 7650 }; 7651 7652 struct mlx5_ifc_enable_hca_out_bits { 7653 u8 status[0x8]; 7654 u8 reserved_at_8[0x18]; 7655 7656 u8 syndrome[0x20]; 7657 7658 u8 reserved_at_40[0x20]; 7659 }; 7660 7661 struct mlx5_ifc_enable_hca_in_bits { 7662 u8 opcode[0x10]; 7663 u8 reserved_at_10[0x10]; 7664 7665 u8 reserved_at_20[0x10]; 7666 u8 op_mod[0x10]; 7667 7668 u8 embedded_cpu_function[0x1]; 7669 u8 reserved_at_41[0xf]; 7670 u8 function_id[0x10]; 7671 7672 u8 reserved_at_60[0x20]; 7673 }; 7674 7675 struct mlx5_ifc_drain_dct_out_bits { 7676 u8 status[0x8]; 7677 u8 reserved_at_8[0x18]; 7678 7679 u8 syndrome[0x20]; 7680 7681 u8 reserved_at_40[0x40]; 7682 }; 7683 7684 struct mlx5_ifc_drain_dct_in_bits { 7685 u8 opcode[0x10]; 7686 u8 uid[0x10]; 7687 7688 u8 reserved_at_20[0x10]; 7689 u8 op_mod[0x10]; 7690 7691 u8 reserved_at_40[0x8]; 7692 u8 dctn[0x18]; 7693 7694 u8 reserved_at_60[0x20]; 7695 }; 7696 7697 struct mlx5_ifc_disable_hca_out_bits { 7698 u8 status[0x8]; 7699 u8 reserved_at_8[0x18]; 7700 7701 u8 syndrome[0x20]; 7702 7703 u8 reserved_at_40[0x20]; 7704 }; 7705 7706 struct mlx5_ifc_disable_hca_in_bits { 7707 u8 opcode[0x10]; 7708 u8 reserved_at_10[0x10]; 7709 7710 u8 reserved_at_20[0x10]; 7711 u8 op_mod[0x10]; 7712 7713 u8 embedded_cpu_function[0x1]; 7714 u8 reserved_at_41[0xf]; 7715 u8 function_id[0x10]; 7716 7717 u8 reserved_at_60[0x20]; 7718 }; 7719 7720 struct mlx5_ifc_detach_from_mcg_out_bits { 7721 u8 status[0x8]; 7722 u8 reserved_at_8[0x18]; 7723 7724 u8 syndrome[0x20]; 7725 7726 u8 reserved_at_40[0x40]; 7727 }; 7728 7729 struct mlx5_ifc_detach_from_mcg_in_bits { 7730 u8 opcode[0x10]; 7731 u8 uid[0x10]; 7732 7733 u8 reserved_at_20[0x10]; 7734 u8 op_mod[0x10]; 7735 7736 u8 reserved_at_40[0x8]; 7737 u8 qpn[0x18]; 7738 7739 u8 reserved_at_60[0x20]; 7740 7741 u8 multicast_gid[16][0x8]; 7742 }; 7743 7744 struct mlx5_ifc_destroy_xrq_out_bits { 7745 u8 status[0x8]; 7746 u8 reserved_at_8[0x18]; 7747 7748 u8 syndrome[0x20]; 7749 7750 u8 reserved_at_40[0x40]; 7751 }; 7752 7753 struct mlx5_ifc_destroy_xrq_in_bits { 7754 u8 opcode[0x10]; 7755 u8 uid[0x10]; 7756 7757 u8 reserved_at_20[0x10]; 7758 u8 op_mod[0x10]; 7759 7760 u8 reserved_at_40[0x8]; 7761 u8 xrqn[0x18]; 7762 7763 u8 reserved_at_60[0x20]; 7764 }; 7765 7766 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7767 u8 status[0x8]; 7768 u8 reserved_at_8[0x18]; 7769 7770 u8 syndrome[0x20]; 7771 7772 u8 reserved_at_40[0x40]; 7773 }; 7774 7775 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7776 u8 opcode[0x10]; 7777 u8 uid[0x10]; 7778 7779 u8 reserved_at_20[0x10]; 7780 u8 op_mod[0x10]; 7781 7782 u8 reserved_at_40[0x8]; 7783 u8 xrc_srqn[0x18]; 7784 7785 u8 reserved_at_60[0x20]; 7786 }; 7787 7788 struct mlx5_ifc_destroy_tis_out_bits { 7789 u8 status[0x8]; 7790 u8 reserved_at_8[0x18]; 7791 7792 u8 syndrome[0x20]; 7793 7794 u8 reserved_at_40[0x40]; 7795 }; 7796 7797 struct mlx5_ifc_destroy_tis_in_bits { 7798 u8 opcode[0x10]; 7799 u8 uid[0x10]; 7800 7801 u8 reserved_at_20[0x10]; 7802 u8 op_mod[0x10]; 7803 7804 u8 reserved_at_40[0x8]; 7805 u8 tisn[0x18]; 7806 7807 u8 reserved_at_60[0x20]; 7808 }; 7809 7810 struct mlx5_ifc_destroy_tir_out_bits { 7811 u8 status[0x8]; 7812 u8 reserved_at_8[0x18]; 7813 7814 u8 syndrome[0x20]; 7815 7816 u8 reserved_at_40[0x40]; 7817 }; 7818 7819 struct mlx5_ifc_destroy_tir_in_bits { 7820 u8 opcode[0x10]; 7821 u8 uid[0x10]; 7822 7823 u8 reserved_at_20[0x10]; 7824 u8 op_mod[0x10]; 7825 7826 u8 reserved_at_40[0x8]; 7827 u8 tirn[0x18]; 7828 7829 u8 reserved_at_60[0x20]; 7830 }; 7831 7832 struct mlx5_ifc_destroy_srq_out_bits { 7833 u8 status[0x8]; 7834 u8 reserved_at_8[0x18]; 7835 7836 u8 syndrome[0x20]; 7837 7838 u8 reserved_at_40[0x40]; 7839 }; 7840 7841 struct mlx5_ifc_destroy_srq_in_bits { 7842 u8 opcode[0x10]; 7843 u8 uid[0x10]; 7844 7845 u8 reserved_at_20[0x10]; 7846 u8 op_mod[0x10]; 7847 7848 u8 reserved_at_40[0x8]; 7849 u8 srqn[0x18]; 7850 7851 u8 reserved_at_60[0x20]; 7852 }; 7853 7854 struct mlx5_ifc_destroy_sq_out_bits { 7855 u8 status[0x8]; 7856 u8 reserved_at_8[0x18]; 7857 7858 u8 syndrome[0x20]; 7859 7860 u8 reserved_at_40[0x40]; 7861 }; 7862 7863 struct mlx5_ifc_destroy_sq_in_bits { 7864 u8 opcode[0x10]; 7865 u8 uid[0x10]; 7866 7867 u8 reserved_at_20[0x10]; 7868 u8 op_mod[0x10]; 7869 7870 u8 reserved_at_40[0x8]; 7871 u8 sqn[0x18]; 7872 7873 u8 reserved_at_60[0x20]; 7874 }; 7875 7876 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7877 u8 status[0x8]; 7878 u8 reserved_at_8[0x18]; 7879 7880 u8 syndrome[0x20]; 7881 7882 u8 reserved_at_40[0x1c0]; 7883 }; 7884 7885 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7886 u8 opcode[0x10]; 7887 u8 reserved_at_10[0x10]; 7888 7889 u8 reserved_at_20[0x10]; 7890 u8 op_mod[0x10]; 7891 7892 u8 scheduling_hierarchy[0x8]; 7893 u8 reserved_at_48[0x18]; 7894 7895 u8 scheduling_element_id[0x20]; 7896 7897 u8 reserved_at_80[0x180]; 7898 }; 7899 7900 struct mlx5_ifc_destroy_rqt_out_bits { 7901 u8 status[0x8]; 7902 u8 reserved_at_8[0x18]; 7903 7904 u8 syndrome[0x20]; 7905 7906 u8 reserved_at_40[0x40]; 7907 }; 7908 7909 struct mlx5_ifc_destroy_rqt_in_bits { 7910 u8 opcode[0x10]; 7911 u8 uid[0x10]; 7912 7913 u8 reserved_at_20[0x10]; 7914 u8 op_mod[0x10]; 7915 7916 u8 reserved_at_40[0x8]; 7917 u8 rqtn[0x18]; 7918 7919 u8 reserved_at_60[0x20]; 7920 }; 7921 7922 struct mlx5_ifc_destroy_rq_out_bits { 7923 u8 status[0x8]; 7924 u8 reserved_at_8[0x18]; 7925 7926 u8 syndrome[0x20]; 7927 7928 u8 reserved_at_40[0x40]; 7929 }; 7930 7931 struct mlx5_ifc_destroy_rq_in_bits { 7932 u8 opcode[0x10]; 7933 u8 uid[0x10]; 7934 7935 u8 reserved_at_20[0x10]; 7936 u8 op_mod[0x10]; 7937 7938 u8 reserved_at_40[0x8]; 7939 u8 rqn[0x18]; 7940 7941 u8 reserved_at_60[0x20]; 7942 }; 7943 7944 struct mlx5_ifc_set_delay_drop_params_in_bits { 7945 u8 opcode[0x10]; 7946 u8 reserved_at_10[0x10]; 7947 7948 u8 reserved_at_20[0x10]; 7949 u8 op_mod[0x10]; 7950 7951 u8 reserved_at_40[0x20]; 7952 7953 u8 reserved_at_60[0x10]; 7954 u8 delay_drop_timeout[0x10]; 7955 }; 7956 7957 struct mlx5_ifc_set_delay_drop_params_out_bits { 7958 u8 status[0x8]; 7959 u8 reserved_at_8[0x18]; 7960 7961 u8 syndrome[0x20]; 7962 7963 u8 reserved_at_40[0x40]; 7964 }; 7965 7966 struct mlx5_ifc_destroy_rmp_out_bits { 7967 u8 status[0x8]; 7968 u8 reserved_at_8[0x18]; 7969 7970 u8 syndrome[0x20]; 7971 7972 u8 reserved_at_40[0x40]; 7973 }; 7974 7975 struct mlx5_ifc_destroy_rmp_in_bits { 7976 u8 opcode[0x10]; 7977 u8 uid[0x10]; 7978 7979 u8 reserved_at_20[0x10]; 7980 u8 op_mod[0x10]; 7981 7982 u8 reserved_at_40[0x8]; 7983 u8 rmpn[0x18]; 7984 7985 u8 reserved_at_60[0x20]; 7986 }; 7987 7988 struct mlx5_ifc_destroy_qp_out_bits { 7989 u8 status[0x8]; 7990 u8 reserved_at_8[0x18]; 7991 7992 u8 syndrome[0x20]; 7993 7994 u8 reserved_at_40[0x40]; 7995 }; 7996 7997 struct mlx5_ifc_destroy_qp_in_bits { 7998 u8 opcode[0x10]; 7999 u8 uid[0x10]; 8000 8001 u8 reserved_at_20[0x10]; 8002 u8 op_mod[0x10]; 8003 8004 u8 reserved_at_40[0x8]; 8005 u8 qpn[0x18]; 8006 8007 u8 reserved_at_60[0x20]; 8008 }; 8009 8010 struct mlx5_ifc_destroy_psv_out_bits { 8011 u8 status[0x8]; 8012 u8 reserved_at_8[0x18]; 8013 8014 u8 syndrome[0x20]; 8015 8016 u8 reserved_at_40[0x40]; 8017 }; 8018 8019 struct mlx5_ifc_destroy_psv_in_bits { 8020 u8 opcode[0x10]; 8021 u8 reserved_at_10[0x10]; 8022 8023 u8 reserved_at_20[0x10]; 8024 u8 op_mod[0x10]; 8025 8026 u8 reserved_at_40[0x8]; 8027 u8 psvn[0x18]; 8028 8029 u8 reserved_at_60[0x20]; 8030 }; 8031 8032 struct mlx5_ifc_destroy_mkey_out_bits { 8033 u8 status[0x8]; 8034 u8 reserved_at_8[0x18]; 8035 8036 u8 syndrome[0x20]; 8037 8038 u8 reserved_at_40[0x40]; 8039 }; 8040 8041 struct mlx5_ifc_destroy_mkey_in_bits { 8042 u8 opcode[0x10]; 8043 u8 uid[0x10]; 8044 8045 u8 reserved_at_20[0x10]; 8046 u8 op_mod[0x10]; 8047 8048 u8 reserved_at_40[0x8]; 8049 u8 mkey_index[0x18]; 8050 8051 u8 reserved_at_60[0x20]; 8052 }; 8053 8054 struct mlx5_ifc_destroy_flow_table_out_bits { 8055 u8 status[0x8]; 8056 u8 reserved_at_8[0x18]; 8057 8058 u8 syndrome[0x20]; 8059 8060 u8 reserved_at_40[0x40]; 8061 }; 8062 8063 struct mlx5_ifc_destroy_flow_table_in_bits { 8064 u8 opcode[0x10]; 8065 u8 reserved_at_10[0x10]; 8066 8067 u8 reserved_at_20[0x10]; 8068 u8 op_mod[0x10]; 8069 8070 u8 other_vport[0x1]; 8071 u8 reserved_at_41[0xf]; 8072 u8 vport_number[0x10]; 8073 8074 u8 reserved_at_60[0x20]; 8075 8076 u8 table_type[0x8]; 8077 u8 reserved_at_88[0x18]; 8078 8079 u8 reserved_at_a0[0x8]; 8080 u8 table_id[0x18]; 8081 8082 u8 reserved_at_c0[0x140]; 8083 }; 8084 8085 struct mlx5_ifc_destroy_flow_group_out_bits { 8086 u8 status[0x8]; 8087 u8 reserved_at_8[0x18]; 8088 8089 u8 syndrome[0x20]; 8090 8091 u8 reserved_at_40[0x40]; 8092 }; 8093 8094 struct mlx5_ifc_destroy_flow_group_in_bits { 8095 u8 opcode[0x10]; 8096 u8 reserved_at_10[0x10]; 8097 8098 u8 reserved_at_20[0x10]; 8099 u8 op_mod[0x10]; 8100 8101 u8 other_vport[0x1]; 8102 u8 reserved_at_41[0xf]; 8103 u8 vport_number[0x10]; 8104 8105 u8 reserved_at_60[0x20]; 8106 8107 u8 table_type[0x8]; 8108 u8 reserved_at_88[0x18]; 8109 8110 u8 reserved_at_a0[0x8]; 8111 u8 table_id[0x18]; 8112 8113 u8 group_id[0x20]; 8114 8115 u8 reserved_at_e0[0x120]; 8116 }; 8117 8118 struct mlx5_ifc_destroy_eq_out_bits { 8119 u8 status[0x8]; 8120 u8 reserved_at_8[0x18]; 8121 8122 u8 syndrome[0x20]; 8123 8124 u8 reserved_at_40[0x40]; 8125 }; 8126 8127 struct mlx5_ifc_destroy_eq_in_bits { 8128 u8 opcode[0x10]; 8129 u8 reserved_at_10[0x10]; 8130 8131 u8 reserved_at_20[0x10]; 8132 u8 op_mod[0x10]; 8133 8134 u8 reserved_at_40[0x18]; 8135 u8 eq_number[0x8]; 8136 8137 u8 reserved_at_60[0x20]; 8138 }; 8139 8140 struct mlx5_ifc_destroy_dct_out_bits { 8141 u8 status[0x8]; 8142 u8 reserved_at_8[0x18]; 8143 8144 u8 syndrome[0x20]; 8145 8146 u8 reserved_at_40[0x40]; 8147 }; 8148 8149 struct mlx5_ifc_destroy_dct_in_bits { 8150 u8 opcode[0x10]; 8151 u8 uid[0x10]; 8152 8153 u8 reserved_at_20[0x10]; 8154 u8 op_mod[0x10]; 8155 8156 u8 reserved_at_40[0x8]; 8157 u8 dctn[0x18]; 8158 8159 u8 reserved_at_60[0x20]; 8160 }; 8161 8162 struct mlx5_ifc_destroy_cq_out_bits { 8163 u8 status[0x8]; 8164 u8 reserved_at_8[0x18]; 8165 8166 u8 syndrome[0x20]; 8167 8168 u8 reserved_at_40[0x40]; 8169 }; 8170 8171 struct mlx5_ifc_destroy_cq_in_bits { 8172 u8 opcode[0x10]; 8173 u8 uid[0x10]; 8174 8175 u8 reserved_at_20[0x10]; 8176 u8 op_mod[0x10]; 8177 8178 u8 reserved_at_40[0x8]; 8179 u8 cqn[0x18]; 8180 8181 u8 reserved_at_60[0x20]; 8182 }; 8183 8184 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8185 u8 status[0x8]; 8186 u8 reserved_at_8[0x18]; 8187 8188 u8 syndrome[0x20]; 8189 8190 u8 reserved_at_40[0x40]; 8191 }; 8192 8193 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8194 u8 opcode[0x10]; 8195 u8 reserved_at_10[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0x20]; 8201 8202 u8 reserved_at_60[0x10]; 8203 u8 vxlan_udp_port[0x10]; 8204 }; 8205 8206 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_at_8[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_at_40[0x40]; 8213 }; 8214 8215 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8216 u8 opcode[0x10]; 8217 u8 reserved_at_10[0x10]; 8218 8219 u8 reserved_at_20[0x10]; 8220 u8 op_mod[0x10]; 8221 8222 u8 reserved_at_40[0x60]; 8223 8224 u8 reserved_at_a0[0x8]; 8225 u8 table_index[0x18]; 8226 8227 u8 reserved_at_c0[0x140]; 8228 }; 8229 8230 struct mlx5_ifc_delete_fte_out_bits { 8231 u8 status[0x8]; 8232 u8 reserved_at_8[0x18]; 8233 8234 u8 syndrome[0x20]; 8235 8236 u8 reserved_at_40[0x40]; 8237 }; 8238 8239 struct mlx5_ifc_delete_fte_in_bits { 8240 u8 opcode[0x10]; 8241 u8 reserved_at_10[0x10]; 8242 8243 u8 reserved_at_20[0x10]; 8244 u8 op_mod[0x10]; 8245 8246 u8 other_vport[0x1]; 8247 u8 reserved_at_41[0xf]; 8248 u8 vport_number[0x10]; 8249 8250 u8 reserved_at_60[0x20]; 8251 8252 u8 table_type[0x8]; 8253 u8 reserved_at_88[0x18]; 8254 8255 u8 reserved_at_a0[0x8]; 8256 u8 table_id[0x18]; 8257 8258 u8 reserved_at_c0[0x40]; 8259 8260 u8 flow_index[0x20]; 8261 8262 u8 reserved_at_120[0xe0]; 8263 }; 8264 8265 struct mlx5_ifc_dealloc_xrcd_out_bits { 8266 u8 status[0x8]; 8267 u8 reserved_at_8[0x18]; 8268 8269 u8 syndrome[0x20]; 8270 8271 u8 reserved_at_40[0x40]; 8272 }; 8273 8274 struct mlx5_ifc_dealloc_xrcd_in_bits { 8275 u8 opcode[0x10]; 8276 u8 uid[0x10]; 8277 8278 u8 reserved_at_20[0x10]; 8279 u8 op_mod[0x10]; 8280 8281 u8 reserved_at_40[0x8]; 8282 u8 xrcd[0x18]; 8283 8284 u8 reserved_at_60[0x20]; 8285 }; 8286 8287 struct mlx5_ifc_dealloc_uar_out_bits { 8288 u8 status[0x8]; 8289 u8 reserved_at_8[0x18]; 8290 8291 u8 syndrome[0x20]; 8292 8293 u8 reserved_at_40[0x40]; 8294 }; 8295 8296 struct mlx5_ifc_dealloc_uar_in_bits { 8297 u8 opcode[0x10]; 8298 u8 uid[0x10]; 8299 8300 u8 reserved_at_20[0x10]; 8301 u8 op_mod[0x10]; 8302 8303 u8 reserved_at_40[0x8]; 8304 u8 uar[0x18]; 8305 8306 u8 reserved_at_60[0x20]; 8307 }; 8308 8309 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8310 u8 status[0x8]; 8311 u8 reserved_at_8[0x18]; 8312 8313 u8 syndrome[0x20]; 8314 8315 u8 reserved_at_40[0x40]; 8316 }; 8317 8318 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8319 u8 opcode[0x10]; 8320 u8 uid[0x10]; 8321 8322 u8 reserved_at_20[0x10]; 8323 u8 op_mod[0x10]; 8324 8325 u8 reserved_at_40[0x8]; 8326 u8 transport_domain[0x18]; 8327 8328 u8 reserved_at_60[0x20]; 8329 }; 8330 8331 struct mlx5_ifc_dealloc_q_counter_out_bits { 8332 u8 status[0x8]; 8333 u8 reserved_at_8[0x18]; 8334 8335 u8 syndrome[0x20]; 8336 8337 u8 reserved_at_40[0x40]; 8338 }; 8339 8340 struct mlx5_ifc_dealloc_q_counter_in_bits { 8341 u8 opcode[0x10]; 8342 u8 reserved_at_10[0x10]; 8343 8344 u8 reserved_at_20[0x10]; 8345 u8 op_mod[0x10]; 8346 8347 u8 reserved_at_40[0x18]; 8348 u8 counter_set_id[0x8]; 8349 8350 u8 reserved_at_60[0x20]; 8351 }; 8352 8353 struct mlx5_ifc_dealloc_pd_out_bits { 8354 u8 status[0x8]; 8355 u8 reserved_at_8[0x18]; 8356 8357 u8 syndrome[0x20]; 8358 8359 u8 reserved_at_40[0x40]; 8360 }; 8361 8362 struct mlx5_ifc_dealloc_pd_in_bits { 8363 u8 opcode[0x10]; 8364 u8 uid[0x10]; 8365 8366 u8 reserved_at_20[0x10]; 8367 u8 op_mod[0x10]; 8368 8369 u8 reserved_at_40[0x8]; 8370 u8 pd[0x18]; 8371 8372 u8 reserved_at_60[0x20]; 8373 }; 8374 8375 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8376 u8 status[0x8]; 8377 u8 reserved_at_8[0x18]; 8378 8379 u8 syndrome[0x20]; 8380 8381 u8 reserved_at_40[0x40]; 8382 }; 8383 8384 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8385 u8 opcode[0x10]; 8386 u8 reserved_at_10[0x10]; 8387 8388 u8 reserved_at_20[0x10]; 8389 u8 op_mod[0x10]; 8390 8391 u8 flow_counter_id[0x20]; 8392 8393 u8 reserved_at_60[0x20]; 8394 }; 8395 8396 struct mlx5_ifc_create_xrq_out_bits { 8397 u8 status[0x8]; 8398 u8 reserved_at_8[0x18]; 8399 8400 u8 syndrome[0x20]; 8401 8402 u8 reserved_at_40[0x8]; 8403 u8 xrqn[0x18]; 8404 8405 u8 reserved_at_60[0x20]; 8406 }; 8407 8408 struct mlx5_ifc_create_xrq_in_bits { 8409 u8 opcode[0x10]; 8410 u8 uid[0x10]; 8411 8412 u8 reserved_at_20[0x10]; 8413 u8 op_mod[0x10]; 8414 8415 u8 reserved_at_40[0x40]; 8416 8417 struct mlx5_ifc_xrqc_bits xrq_context; 8418 }; 8419 8420 struct mlx5_ifc_create_xrc_srq_out_bits { 8421 u8 status[0x8]; 8422 u8 reserved_at_8[0x18]; 8423 8424 u8 syndrome[0x20]; 8425 8426 u8 reserved_at_40[0x8]; 8427 u8 xrc_srqn[0x18]; 8428 8429 u8 reserved_at_60[0x20]; 8430 }; 8431 8432 struct mlx5_ifc_create_xrc_srq_in_bits { 8433 u8 opcode[0x10]; 8434 u8 uid[0x10]; 8435 8436 u8 reserved_at_20[0x10]; 8437 u8 op_mod[0x10]; 8438 8439 u8 reserved_at_40[0x40]; 8440 8441 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8442 8443 u8 reserved_at_280[0x60]; 8444 8445 u8 xrc_srq_umem_valid[0x1]; 8446 u8 reserved_at_2e1[0x1f]; 8447 8448 u8 reserved_at_300[0x580]; 8449 8450 u8 pas[][0x40]; 8451 }; 8452 8453 struct mlx5_ifc_create_tis_out_bits { 8454 u8 status[0x8]; 8455 u8 reserved_at_8[0x18]; 8456 8457 u8 syndrome[0x20]; 8458 8459 u8 reserved_at_40[0x8]; 8460 u8 tisn[0x18]; 8461 8462 u8 reserved_at_60[0x20]; 8463 }; 8464 8465 struct mlx5_ifc_create_tis_in_bits { 8466 u8 opcode[0x10]; 8467 u8 uid[0x10]; 8468 8469 u8 reserved_at_20[0x10]; 8470 u8 op_mod[0x10]; 8471 8472 u8 reserved_at_40[0xc0]; 8473 8474 struct mlx5_ifc_tisc_bits ctx; 8475 }; 8476 8477 struct mlx5_ifc_create_tir_out_bits { 8478 u8 status[0x8]; 8479 u8 icm_address_63_40[0x18]; 8480 8481 u8 syndrome[0x20]; 8482 8483 u8 icm_address_39_32[0x8]; 8484 u8 tirn[0x18]; 8485 8486 u8 icm_address_31_0[0x20]; 8487 }; 8488 8489 struct mlx5_ifc_create_tir_in_bits { 8490 u8 opcode[0x10]; 8491 u8 uid[0x10]; 8492 8493 u8 reserved_at_20[0x10]; 8494 u8 op_mod[0x10]; 8495 8496 u8 reserved_at_40[0xc0]; 8497 8498 struct mlx5_ifc_tirc_bits ctx; 8499 }; 8500 8501 struct mlx5_ifc_create_srq_out_bits { 8502 u8 status[0x8]; 8503 u8 reserved_at_8[0x18]; 8504 8505 u8 syndrome[0x20]; 8506 8507 u8 reserved_at_40[0x8]; 8508 u8 srqn[0x18]; 8509 8510 u8 reserved_at_60[0x20]; 8511 }; 8512 8513 struct mlx5_ifc_create_srq_in_bits { 8514 u8 opcode[0x10]; 8515 u8 uid[0x10]; 8516 8517 u8 reserved_at_20[0x10]; 8518 u8 op_mod[0x10]; 8519 8520 u8 reserved_at_40[0x40]; 8521 8522 struct mlx5_ifc_srqc_bits srq_context_entry; 8523 8524 u8 reserved_at_280[0x600]; 8525 8526 u8 pas[][0x40]; 8527 }; 8528 8529 struct mlx5_ifc_create_sq_out_bits { 8530 u8 status[0x8]; 8531 u8 reserved_at_8[0x18]; 8532 8533 u8 syndrome[0x20]; 8534 8535 u8 reserved_at_40[0x8]; 8536 u8 sqn[0x18]; 8537 8538 u8 reserved_at_60[0x20]; 8539 }; 8540 8541 struct mlx5_ifc_create_sq_in_bits { 8542 u8 opcode[0x10]; 8543 u8 uid[0x10]; 8544 8545 u8 reserved_at_20[0x10]; 8546 u8 op_mod[0x10]; 8547 8548 u8 reserved_at_40[0xc0]; 8549 8550 struct mlx5_ifc_sqc_bits ctx; 8551 }; 8552 8553 struct mlx5_ifc_create_scheduling_element_out_bits { 8554 u8 status[0x8]; 8555 u8 reserved_at_8[0x18]; 8556 8557 u8 syndrome[0x20]; 8558 8559 u8 reserved_at_40[0x40]; 8560 8561 u8 scheduling_element_id[0x20]; 8562 8563 u8 reserved_at_a0[0x160]; 8564 }; 8565 8566 struct mlx5_ifc_create_scheduling_element_in_bits { 8567 u8 opcode[0x10]; 8568 u8 reserved_at_10[0x10]; 8569 8570 u8 reserved_at_20[0x10]; 8571 u8 op_mod[0x10]; 8572 8573 u8 scheduling_hierarchy[0x8]; 8574 u8 reserved_at_48[0x18]; 8575 8576 u8 reserved_at_60[0xa0]; 8577 8578 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8579 8580 u8 reserved_at_300[0x100]; 8581 }; 8582 8583 struct mlx5_ifc_create_rqt_out_bits { 8584 u8 status[0x8]; 8585 u8 reserved_at_8[0x18]; 8586 8587 u8 syndrome[0x20]; 8588 8589 u8 reserved_at_40[0x8]; 8590 u8 rqtn[0x18]; 8591 8592 u8 reserved_at_60[0x20]; 8593 }; 8594 8595 struct mlx5_ifc_create_rqt_in_bits { 8596 u8 opcode[0x10]; 8597 u8 uid[0x10]; 8598 8599 u8 reserved_at_20[0x10]; 8600 u8 op_mod[0x10]; 8601 8602 u8 reserved_at_40[0xc0]; 8603 8604 struct mlx5_ifc_rqtc_bits rqt_context; 8605 }; 8606 8607 struct mlx5_ifc_create_rq_out_bits { 8608 u8 status[0x8]; 8609 u8 reserved_at_8[0x18]; 8610 8611 u8 syndrome[0x20]; 8612 8613 u8 reserved_at_40[0x8]; 8614 u8 rqn[0x18]; 8615 8616 u8 reserved_at_60[0x20]; 8617 }; 8618 8619 struct mlx5_ifc_create_rq_in_bits { 8620 u8 opcode[0x10]; 8621 u8 uid[0x10]; 8622 8623 u8 reserved_at_20[0x10]; 8624 u8 op_mod[0x10]; 8625 8626 u8 reserved_at_40[0xc0]; 8627 8628 struct mlx5_ifc_rqc_bits ctx; 8629 }; 8630 8631 struct mlx5_ifc_create_rmp_out_bits { 8632 u8 status[0x8]; 8633 u8 reserved_at_8[0x18]; 8634 8635 u8 syndrome[0x20]; 8636 8637 u8 reserved_at_40[0x8]; 8638 u8 rmpn[0x18]; 8639 8640 u8 reserved_at_60[0x20]; 8641 }; 8642 8643 struct mlx5_ifc_create_rmp_in_bits { 8644 u8 opcode[0x10]; 8645 u8 uid[0x10]; 8646 8647 u8 reserved_at_20[0x10]; 8648 u8 op_mod[0x10]; 8649 8650 u8 reserved_at_40[0xc0]; 8651 8652 struct mlx5_ifc_rmpc_bits ctx; 8653 }; 8654 8655 struct mlx5_ifc_create_qp_out_bits { 8656 u8 status[0x8]; 8657 u8 reserved_at_8[0x18]; 8658 8659 u8 syndrome[0x20]; 8660 8661 u8 reserved_at_40[0x8]; 8662 u8 qpn[0x18]; 8663 8664 u8 ece[0x20]; 8665 }; 8666 8667 struct mlx5_ifc_create_qp_in_bits { 8668 u8 opcode[0x10]; 8669 u8 uid[0x10]; 8670 8671 u8 reserved_at_20[0x10]; 8672 u8 op_mod[0x10]; 8673 8674 u8 qpc_ext[0x1]; 8675 u8 reserved_at_41[0x7]; 8676 u8 input_qpn[0x18]; 8677 8678 u8 reserved_at_60[0x20]; 8679 u8 opt_param_mask[0x20]; 8680 8681 u8 ece[0x20]; 8682 8683 struct mlx5_ifc_qpc_bits qpc; 8684 8685 u8 reserved_at_800[0x60]; 8686 8687 u8 wq_umem_valid[0x1]; 8688 u8 reserved_at_861[0x1f]; 8689 8690 u8 pas[][0x40]; 8691 }; 8692 8693 struct mlx5_ifc_create_psv_out_bits { 8694 u8 status[0x8]; 8695 u8 reserved_at_8[0x18]; 8696 8697 u8 syndrome[0x20]; 8698 8699 u8 reserved_at_40[0x40]; 8700 8701 u8 reserved_at_80[0x8]; 8702 u8 psv0_index[0x18]; 8703 8704 u8 reserved_at_a0[0x8]; 8705 u8 psv1_index[0x18]; 8706 8707 u8 reserved_at_c0[0x8]; 8708 u8 psv2_index[0x18]; 8709 8710 u8 reserved_at_e0[0x8]; 8711 u8 psv3_index[0x18]; 8712 }; 8713 8714 struct mlx5_ifc_create_psv_in_bits { 8715 u8 opcode[0x10]; 8716 u8 reserved_at_10[0x10]; 8717 8718 u8 reserved_at_20[0x10]; 8719 u8 op_mod[0x10]; 8720 8721 u8 num_psv[0x4]; 8722 u8 reserved_at_44[0x4]; 8723 u8 pd[0x18]; 8724 8725 u8 reserved_at_60[0x20]; 8726 }; 8727 8728 struct mlx5_ifc_create_mkey_out_bits { 8729 u8 status[0x8]; 8730 u8 reserved_at_8[0x18]; 8731 8732 u8 syndrome[0x20]; 8733 8734 u8 reserved_at_40[0x8]; 8735 u8 mkey_index[0x18]; 8736 8737 u8 reserved_at_60[0x20]; 8738 }; 8739 8740 struct mlx5_ifc_create_mkey_in_bits { 8741 u8 opcode[0x10]; 8742 u8 uid[0x10]; 8743 8744 u8 reserved_at_20[0x10]; 8745 u8 op_mod[0x10]; 8746 8747 u8 reserved_at_40[0x20]; 8748 8749 u8 pg_access[0x1]; 8750 u8 mkey_umem_valid[0x1]; 8751 u8 reserved_at_62[0x1e]; 8752 8753 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8754 8755 u8 reserved_at_280[0x80]; 8756 8757 u8 translations_octword_actual_size[0x20]; 8758 8759 u8 reserved_at_320[0x560]; 8760 8761 u8 klm_pas_mtt[][0x20]; 8762 }; 8763 8764 enum { 8765 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8766 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8767 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8768 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8769 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8770 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8771 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8772 }; 8773 8774 struct mlx5_ifc_create_flow_table_out_bits { 8775 u8 status[0x8]; 8776 u8 icm_address_63_40[0x18]; 8777 8778 u8 syndrome[0x20]; 8779 8780 u8 icm_address_39_32[0x8]; 8781 u8 table_id[0x18]; 8782 8783 u8 icm_address_31_0[0x20]; 8784 }; 8785 8786 struct mlx5_ifc_create_flow_table_in_bits { 8787 u8 opcode[0x10]; 8788 u8 uid[0x10]; 8789 8790 u8 reserved_at_20[0x10]; 8791 u8 op_mod[0x10]; 8792 8793 u8 other_vport[0x1]; 8794 u8 reserved_at_41[0xf]; 8795 u8 vport_number[0x10]; 8796 8797 u8 reserved_at_60[0x20]; 8798 8799 u8 table_type[0x8]; 8800 u8 reserved_at_88[0x18]; 8801 8802 u8 reserved_at_a0[0x20]; 8803 8804 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8805 }; 8806 8807 struct mlx5_ifc_create_flow_group_out_bits { 8808 u8 status[0x8]; 8809 u8 reserved_at_8[0x18]; 8810 8811 u8 syndrome[0x20]; 8812 8813 u8 reserved_at_40[0x8]; 8814 u8 group_id[0x18]; 8815 8816 u8 reserved_at_60[0x20]; 8817 }; 8818 8819 enum { 8820 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8821 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8822 }; 8823 8824 enum { 8825 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8826 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8827 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8828 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8829 }; 8830 8831 struct mlx5_ifc_create_flow_group_in_bits { 8832 u8 opcode[0x10]; 8833 u8 reserved_at_10[0x10]; 8834 8835 u8 reserved_at_20[0x10]; 8836 u8 op_mod[0x10]; 8837 8838 u8 other_vport[0x1]; 8839 u8 reserved_at_41[0xf]; 8840 u8 vport_number[0x10]; 8841 8842 u8 reserved_at_60[0x20]; 8843 8844 u8 table_type[0x8]; 8845 u8 reserved_at_88[0x4]; 8846 u8 group_type[0x4]; 8847 u8 reserved_at_90[0x10]; 8848 8849 u8 reserved_at_a0[0x8]; 8850 u8 table_id[0x18]; 8851 8852 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8853 8854 u8 reserved_at_c1[0x1f]; 8855 8856 u8 start_flow_index[0x20]; 8857 8858 u8 reserved_at_100[0x20]; 8859 8860 u8 end_flow_index[0x20]; 8861 8862 u8 reserved_at_140[0x10]; 8863 u8 match_definer_id[0x10]; 8864 8865 u8 reserved_at_160[0x80]; 8866 8867 u8 reserved_at_1e0[0x18]; 8868 u8 match_criteria_enable[0x8]; 8869 8870 struct mlx5_ifc_fte_match_param_bits match_criteria; 8871 8872 u8 reserved_at_1200[0xe00]; 8873 }; 8874 8875 struct mlx5_ifc_create_eq_out_bits { 8876 u8 status[0x8]; 8877 u8 reserved_at_8[0x18]; 8878 8879 u8 syndrome[0x20]; 8880 8881 u8 reserved_at_40[0x18]; 8882 u8 eq_number[0x8]; 8883 8884 u8 reserved_at_60[0x20]; 8885 }; 8886 8887 struct mlx5_ifc_create_eq_in_bits { 8888 u8 opcode[0x10]; 8889 u8 uid[0x10]; 8890 8891 u8 reserved_at_20[0x10]; 8892 u8 op_mod[0x10]; 8893 8894 u8 reserved_at_40[0x40]; 8895 8896 struct mlx5_ifc_eqc_bits eq_context_entry; 8897 8898 u8 reserved_at_280[0x40]; 8899 8900 u8 event_bitmask[4][0x40]; 8901 8902 u8 reserved_at_3c0[0x4c0]; 8903 8904 u8 pas[][0x40]; 8905 }; 8906 8907 struct mlx5_ifc_create_dct_out_bits { 8908 u8 status[0x8]; 8909 u8 reserved_at_8[0x18]; 8910 8911 u8 syndrome[0x20]; 8912 8913 u8 reserved_at_40[0x8]; 8914 u8 dctn[0x18]; 8915 8916 u8 ece[0x20]; 8917 }; 8918 8919 struct mlx5_ifc_create_dct_in_bits { 8920 u8 opcode[0x10]; 8921 u8 uid[0x10]; 8922 8923 u8 reserved_at_20[0x10]; 8924 u8 op_mod[0x10]; 8925 8926 u8 reserved_at_40[0x40]; 8927 8928 struct mlx5_ifc_dctc_bits dct_context_entry; 8929 8930 u8 reserved_at_280[0x180]; 8931 }; 8932 8933 struct mlx5_ifc_create_cq_out_bits { 8934 u8 status[0x8]; 8935 u8 reserved_at_8[0x18]; 8936 8937 u8 syndrome[0x20]; 8938 8939 u8 reserved_at_40[0x8]; 8940 u8 cqn[0x18]; 8941 8942 u8 reserved_at_60[0x20]; 8943 }; 8944 8945 struct mlx5_ifc_create_cq_in_bits { 8946 u8 opcode[0x10]; 8947 u8 uid[0x10]; 8948 8949 u8 reserved_at_20[0x10]; 8950 u8 op_mod[0x10]; 8951 8952 u8 reserved_at_40[0x40]; 8953 8954 struct mlx5_ifc_cqc_bits cq_context; 8955 8956 u8 reserved_at_280[0x60]; 8957 8958 u8 cq_umem_valid[0x1]; 8959 u8 reserved_at_2e1[0x59f]; 8960 8961 u8 pas[][0x40]; 8962 }; 8963 8964 struct mlx5_ifc_config_int_moderation_out_bits { 8965 u8 status[0x8]; 8966 u8 reserved_at_8[0x18]; 8967 8968 u8 syndrome[0x20]; 8969 8970 u8 reserved_at_40[0x4]; 8971 u8 min_delay[0xc]; 8972 u8 int_vector[0x10]; 8973 8974 u8 reserved_at_60[0x20]; 8975 }; 8976 8977 enum { 8978 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8979 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8980 }; 8981 8982 struct mlx5_ifc_config_int_moderation_in_bits { 8983 u8 opcode[0x10]; 8984 u8 reserved_at_10[0x10]; 8985 8986 u8 reserved_at_20[0x10]; 8987 u8 op_mod[0x10]; 8988 8989 u8 reserved_at_40[0x4]; 8990 u8 min_delay[0xc]; 8991 u8 int_vector[0x10]; 8992 8993 u8 reserved_at_60[0x20]; 8994 }; 8995 8996 struct mlx5_ifc_attach_to_mcg_out_bits { 8997 u8 status[0x8]; 8998 u8 reserved_at_8[0x18]; 8999 9000 u8 syndrome[0x20]; 9001 9002 u8 reserved_at_40[0x40]; 9003 }; 9004 9005 struct mlx5_ifc_attach_to_mcg_in_bits { 9006 u8 opcode[0x10]; 9007 u8 uid[0x10]; 9008 9009 u8 reserved_at_20[0x10]; 9010 u8 op_mod[0x10]; 9011 9012 u8 reserved_at_40[0x8]; 9013 u8 qpn[0x18]; 9014 9015 u8 reserved_at_60[0x20]; 9016 9017 u8 multicast_gid[16][0x8]; 9018 }; 9019 9020 struct mlx5_ifc_arm_xrq_out_bits { 9021 u8 status[0x8]; 9022 u8 reserved_at_8[0x18]; 9023 9024 u8 syndrome[0x20]; 9025 9026 u8 reserved_at_40[0x40]; 9027 }; 9028 9029 struct mlx5_ifc_arm_xrq_in_bits { 9030 u8 opcode[0x10]; 9031 u8 reserved_at_10[0x10]; 9032 9033 u8 reserved_at_20[0x10]; 9034 u8 op_mod[0x10]; 9035 9036 u8 reserved_at_40[0x8]; 9037 u8 xrqn[0x18]; 9038 9039 u8 reserved_at_60[0x10]; 9040 u8 lwm[0x10]; 9041 }; 9042 9043 struct mlx5_ifc_arm_xrc_srq_out_bits { 9044 u8 status[0x8]; 9045 u8 reserved_at_8[0x18]; 9046 9047 u8 syndrome[0x20]; 9048 9049 u8 reserved_at_40[0x40]; 9050 }; 9051 9052 enum { 9053 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9054 }; 9055 9056 struct mlx5_ifc_arm_xrc_srq_in_bits { 9057 u8 opcode[0x10]; 9058 u8 uid[0x10]; 9059 9060 u8 reserved_at_20[0x10]; 9061 u8 op_mod[0x10]; 9062 9063 u8 reserved_at_40[0x8]; 9064 u8 xrc_srqn[0x18]; 9065 9066 u8 reserved_at_60[0x10]; 9067 u8 lwm[0x10]; 9068 }; 9069 9070 struct mlx5_ifc_arm_rq_out_bits { 9071 u8 status[0x8]; 9072 u8 reserved_at_8[0x18]; 9073 9074 u8 syndrome[0x20]; 9075 9076 u8 reserved_at_40[0x40]; 9077 }; 9078 9079 enum { 9080 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9081 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9082 }; 9083 9084 struct mlx5_ifc_arm_rq_in_bits { 9085 u8 opcode[0x10]; 9086 u8 uid[0x10]; 9087 9088 u8 reserved_at_20[0x10]; 9089 u8 op_mod[0x10]; 9090 9091 u8 reserved_at_40[0x8]; 9092 u8 srq_number[0x18]; 9093 9094 u8 reserved_at_60[0x10]; 9095 u8 lwm[0x10]; 9096 }; 9097 9098 struct mlx5_ifc_arm_dct_out_bits { 9099 u8 status[0x8]; 9100 u8 reserved_at_8[0x18]; 9101 9102 u8 syndrome[0x20]; 9103 9104 u8 reserved_at_40[0x40]; 9105 }; 9106 9107 struct mlx5_ifc_arm_dct_in_bits { 9108 u8 opcode[0x10]; 9109 u8 reserved_at_10[0x10]; 9110 9111 u8 reserved_at_20[0x10]; 9112 u8 op_mod[0x10]; 9113 9114 u8 reserved_at_40[0x8]; 9115 u8 dct_number[0x18]; 9116 9117 u8 reserved_at_60[0x20]; 9118 }; 9119 9120 struct mlx5_ifc_alloc_xrcd_out_bits { 9121 u8 status[0x8]; 9122 u8 reserved_at_8[0x18]; 9123 9124 u8 syndrome[0x20]; 9125 9126 u8 reserved_at_40[0x8]; 9127 u8 xrcd[0x18]; 9128 9129 u8 reserved_at_60[0x20]; 9130 }; 9131 9132 struct mlx5_ifc_alloc_xrcd_in_bits { 9133 u8 opcode[0x10]; 9134 u8 uid[0x10]; 9135 9136 u8 reserved_at_20[0x10]; 9137 u8 op_mod[0x10]; 9138 9139 u8 reserved_at_40[0x40]; 9140 }; 9141 9142 struct mlx5_ifc_alloc_uar_out_bits { 9143 u8 status[0x8]; 9144 u8 reserved_at_8[0x18]; 9145 9146 u8 syndrome[0x20]; 9147 9148 u8 reserved_at_40[0x8]; 9149 u8 uar[0x18]; 9150 9151 u8 reserved_at_60[0x20]; 9152 }; 9153 9154 struct mlx5_ifc_alloc_uar_in_bits { 9155 u8 opcode[0x10]; 9156 u8 uid[0x10]; 9157 9158 u8 reserved_at_20[0x10]; 9159 u8 op_mod[0x10]; 9160 9161 u8 reserved_at_40[0x40]; 9162 }; 9163 9164 struct mlx5_ifc_alloc_transport_domain_out_bits { 9165 u8 status[0x8]; 9166 u8 reserved_at_8[0x18]; 9167 9168 u8 syndrome[0x20]; 9169 9170 u8 reserved_at_40[0x8]; 9171 u8 transport_domain[0x18]; 9172 9173 u8 reserved_at_60[0x20]; 9174 }; 9175 9176 struct mlx5_ifc_alloc_transport_domain_in_bits { 9177 u8 opcode[0x10]; 9178 u8 uid[0x10]; 9179 9180 u8 reserved_at_20[0x10]; 9181 u8 op_mod[0x10]; 9182 9183 u8 reserved_at_40[0x40]; 9184 }; 9185 9186 struct mlx5_ifc_alloc_q_counter_out_bits { 9187 u8 status[0x8]; 9188 u8 reserved_at_8[0x18]; 9189 9190 u8 syndrome[0x20]; 9191 9192 u8 reserved_at_40[0x18]; 9193 u8 counter_set_id[0x8]; 9194 9195 u8 reserved_at_60[0x20]; 9196 }; 9197 9198 struct mlx5_ifc_alloc_q_counter_in_bits { 9199 u8 opcode[0x10]; 9200 u8 uid[0x10]; 9201 9202 u8 reserved_at_20[0x10]; 9203 u8 op_mod[0x10]; 9204 9205 u8 reserved_at_40[0x40]; 9206 }; 9207 9208 struct mlx5_ifc_alloc_pd_out_bits { 9209 u8 status[0x8]; 9210 u8 reserved_at_8[0x18]; 9211 9212 u8 syndrome[0x20]; 9213 9214 u8 reserved_at_40[0x8]; 9215 u8 pd[0x18]; 9216 9217 u8 reserved_at_60[0x20]; 9218 }; 9219 9220 struct mlx5_ifc_alloc_pd_in_bits { 9221 u8 opcode[0x10]; 9222 u8 uid[0x10]; 9223 9224 u8 reserved_at_20[0x10]; 9225 u8 op_mod[0x10]; 9226 9227 u8 reserved_at_40[0x40]; 9228 }; 9229 9230 struct mlx5_ifc_alloc_flow_counter_out_bits { 9231 u8 status[0x8]; 9232 u8 reserved_at_8[0x18]; 9233 9234 u8 syndrome[0x20]; 9235 9236 u8 flow_counter_id[0x20]; 9237 9238 u8 reserved_at_60[0x20]; 9239 }; 9240 9241 struct mlx5_ifc_alloc_flow_counter_in_bits { 9242 u8 opcode[0x10]; 9243 u8 reserved_at_10[0x10]; 9244 9245 u8 reserved_at_20[0x10]; 9246 u8 op_mod[0x10]; 9247 9248 u8 reserved_at_40[0x38]; 9249 u8 flow_counter_bulk[0x8]; 9250 }; 9251 9252 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9253 u8 status[0x8]; 9254 u8 reserved_at_8[0x18]; 9255 9256 u8 syndrome[0x20]; 9257 9258 u8 reserved_at_40[0x40]; 9259 }; 9260 9261 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9262 u8 opcode[0x10]; 9263 u8 reserved_at_10[0x10]; 9264 9265 u8 reserved_at_20[0x10]; 9266 u8 op_mod[0x10]; 9267 9268 u8 reserved_at_40[0x20]; 9269 9270 u8 reserved_at_60[0x10]; 9271 u8 vxlan_udp_port[0x10]; 9272 }; 9273 9274 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9275 u8 status[0x8]; 9276 u8 reserved_at_8[0x18]; 9277 9278 u8 syndrome[0x20]; 9279 9280 u8 reserved_at_40[0x40]; 9281 }; 9282 9283 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9284 u8 rate_limit[0x20]; 9285 9286 u8 burst_upper_bound[0x20]; 9287 9288 u8 reserved_at_40[0x10]; 9289 u8 typical_packet_size[0x10]; 9290 9291 u8 reserved_at_60[0x120]; 9292 }; 9293 9294 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9295 u8 opcode[0x10]; 9296 u8 uid[0x10]; 9297 9298 u8 reserved_at_20[0x10]; 9299 u8 op_mod[0x10]; 9300 9301 u8 reserved_at_40[0x10]; 9302 u8 rate_limit_index[0x10]; 9303 9304 u8 reserved_at_60[0x20]; 9305 9306 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9307 }; 9308 9309 struct mlx5_ifc_access_register_out_bits { 9310 u8 status[0x8]; 9311 u8 reserved_at_8[0x18]; 9312 9313 u8 syndrome[0x20]; 9314 9315 u8 reserved_at_40[0x40]; 9316 9317 u8 register_data[][0x20]; 9318 }; 9319 9320 enum { 9321 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9322 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9323 }; 9324 9325 struct mlx5_ifc_access_register_in_bits { 9326 u8 opcode[0x10]; 9327 u8 reserved_at_10[0x10]; 9328 9329 u8 reserved_at_20[0x10]; 9330 u8 op_mod[0x10]; 9331 9332 u8 reserved_at_40[0x10]; 9333 u8 register_id[0x10]; 9334 9335 u8 argument[0x20]; 9336 9337 u8 register_data[][0x20]; 9338 }; 9339 9340 struct mlx5_ifc_sltp_reg_bits { 9341 u8 status[0x4]; 9342 u8 version[0x4]; 9343 u8 local_port[0x8]; 9344 u8 pnat[0x2]; 9345 u8 reserved_at_12[0x2]; 9346 u8 lane[0x4]; 9347 u8 reserved_at_18[0x8]; 9348 9349 u8 reserved_at_20[0x20]; 9350 9351 u8 reserved_at_40[0x7]; 9352 u8 polarity[0x1]; 9353 u8 ob_tap0[0x8]; 9354 u8 ob_tap1[0x8]; 9355 u8 ob_tap2[0x8]; 9356 9357 u8 reserved_at_60[0xc]; 9358 u8 ob_preemp_mode[0x4]; 9359 u8 ob_reg[0x8]; 9360 u8 ob_bias[0x8]; 9361 9362 u8 reserved_at_80[0x20]; 9363 }; 9364 9365 struct mlx5_ifc_slrg_reg_bits { 9366 u8 status[0x4]; 9367 u8 version[0x4]; 9368 u8 local_port[0x8]; 9369 u8 pnat[0x2]; 9370 u8 reserved_at_12[0x2]; 9371 u8 lane[0x4]; 9372 u8 reserved_at_18[0x8]; 9373 9374 u8 time_to_link_up[0x10]; 9375 u8 reserved_at_30[0xc]; 9376 u8 grade_lane_speed[0x4]; 9377 9378 u8 grade_version[0x8]; 9379 u8 grade[0x18]; 9380 9381 u8 reserved_at_60[0x4]; 9382 u8 height_grade_type[0x4]; 9383 u8 height_grade[0x18]; 9384 9385 u8 height_dz[0x10]; 9386 u8 height_dv[0x10]; 9387 9388 u8 reserved_at_a0[0x10]; 9389 u8 height_sigma[0x10]; 9390 9391 u8 reserved_at_c0[0x20]; 9392 9393 u8 reserved_at_e0[0x4]; 9394 u8 phase_grade_type[0x4]; 9395 u8 phase_grade[0x18]; 9396 9397 u8 reserved_at_100[0x8]; 9398 u8 phase_eo_pos[0x8]; 9399 u8 reserved_at_110[0x8]; 9400 u8 phase_eo_neg[0x8]; 9401 9402 u8 ffe_set_tested[0x10]; 9403 u8 test_errors_per_lane[0x10]; 9404 }; 9405 9406 struct mlx5_ifc_pvlc_reg_bits { 9407 u8 reserved_at_0[0x8]; 9408 u8 local_port[0x8]; 9409 u8 reserved_at_10[0x10]; 9410 9411 u8 reserved_at_20[0x1c]; 9412 u8 vl_hw_cap[0x4]; 9413 9414 u8 reserved_at_40[0x1c]; 9415 u8 vl_admin[0x4]; 9416 9417 u8 reserved_at_60[0x1c]; 9418 u8 vl_operational[0x4]; 9419 }; 9420 9421 struct mlx5_ifc_pude_reg_bits { 9422 u8 swid[0x8]; 9423 u8 local_port[0x8]; 9424 u8 reserved_at_10[0x4]; 9425 u8 admin_status[0x4]; 9426 u8 reserved_at_18[0x4]; 9427 u8 oper_status[0x4]; 9428 9429 u8 reserved_at_20[0x60]; 9430 }; 9431 9432 struct mlx5_ifc_ptys_reg_bits { 9433 u8 reserved_at_0[0x1]; 9434 u8 an_disable_admin[0x1]; 9435 u8 an_disable_cap[0x1]; 9436 u8 reserved_at_3[0x5]; 9437 u8 local_port[0x8]; 9438 u8 reserved_at_10[0xd]; 9439 u8 proto_mask[0x3]; 9440 9441 u8 an_status[0x4]; 9442 u8 reserved_at_24[0xc]; 9443 u8 data_rate_oper[0x10]; 9444 9445 u8 ext_eth_proto_capability[0x20]; 9446 9447 u8 eth_proto_capability[0x20]; 9448 9449 u8 ib_link_width_capability[0x10]; 9450 u8 ib_proto_capability[0x10]; 9451 9452 u8 ext_eth_proto_admin[0x20]; 9453 9454 u8 eth_proto_admin[0x20]; 9455 9456 u8 ib_link_width_admin[0x10]; 9457 u8 ib_proto_admin[0x10]; 9458 9459 u8 ext_eth_proto_oper[0x20]; 9460 9461 u8 eth_proto_oper[0x20]; 9462 9463 u8 ib_link_width_oper[0x10]; 9464 u8 ib_proto_oper[0x10]; 9465 9466 u8 reserved_at_160[0x1c]; 9467 u8 connector_type[0x4]; 9468 9469 u8 eth_proto_lp_advertise[0x20]; 9470 9471 u8 reserved_at_1a0[0x60]; 9472 }; 9473 9474 struct mlx5_ifc_mlcr_reg_bits { 9475 u8 reserved_at_0[0x8]; 9476 u8 local_port[0x8]; 9477 u8 reserved_at_10[0x20]; 9478 9479 u8 beacon_duration[0x10]; 9480 u8 reserved_at_40[0x10]; 9481 9482 u8 beacon_remain[0x10]; 9483 }; 9484 9485 struct mlx5_ifc_ptas_reg_bits { 9486 u8 reserved_at_0[0x20]; 9487 9488 u8 algorithm_options[0x10]; 9489 u8 reserved_at_30[0x4]; 9490 u8 repetitions_mode[0x4]; 9491 u8 num_of_repetitions[0x8]; 9492 9493 u8 grade_version[0x8]; 9494 u8 height_grade_type[0x4]; 9495 u8 phase_grade_type[0x4]; 9496 u8 height_grade_weight[0x8]; 9497 u8 phase_grade_weight[0x8]; 9498 9499 u8 gisim_measure_bits[0x10]; 9500 u8 adaptive_tap_measure_bits[0x10]; 9501 9502 u8 ber_bath_high_error_threshold[0x10]; 9503 u8 ber_bath_mid_error_threshold[0x10]; 9504 9505 u8 ber_bath_low_error_threshold[0x10]; 9506 u8 one_ratio_high_threshold[0x10]; 9507 9508 u8 one_ratio_high_mid_threshold[0x10]; 9509 u8 one_ratio_low_mid_threshold[0x10]; 9510 9511 u8 one_ratio_low_threshold[0x10]; 9512 u8 ndeo_error_threshold[0x10]; 9513 9514 u8 mixer_offset_step_size[0x10]; 9515 u8 reserved_at_110[0x8]; 9516 u8 mix90_phase_for_voltage_bath[0x8]; 9517 9518 u8 mixer_offset_start[0x10]; 9519 u8 mixer_offset_end[0x10]; 9520 9521 u8 reserved_at_140[0x15]; 9522 u8 ber_test_time[0xb]; 9523 }; 9524 9525 struct mlx5_ifc_pspa_reg_bits { 9526 u8 swid[0x8]; 9527 u8 local_port[0x8]; 9528 u8 sub_port[0x8]; 9529 u8 reserved_at_18[0x8]; 9530 9531 u8 reserved_at_20[0x20]; 9532 }; 9533 9534 struct mlx5_ifc_pqdr_reg_bits { 9535 u8 reserved_at_0[0x8]; 9536 u8 local_port[0x8]; 9537 u8 reserved_at_10[0x5]; 9538 u8 prio[0x3]; 9539 u8 reserved_at_18[0x6]; 9540 u8 mode[0x2]; 9541 9542 u8 reserved_at_20[0x20]; 9543 9544 u8 reserved_at_40[0x10]; 9545 u8 min_threshold[0x10]; 9546 9547 u8 reserved_at_60[0x10]; 9548 u8 max_threshold[0x10]; 9549 9550 u8 reserved_at_80[0x10]; 9551 u8 mark_probability_denominator[0x10]; 9552 9553 u8 reserved_at_a0[0x60]; 9554 }; 9555 9556 struct mlx5_ifc_ppsc_reg_bits { 9557 u8 reserved_at_0[0x8]; 9558 u8 local_port[0x8]; 9559 u8 reserved_at_10[0x10]; 9560 9561 u8 reserved_at_20[0x60]; 9562 9563 u8 reserved_at_80[0x1c]; 9564 u8 wrps_admin[0x4]; 9565 9566 u8 reserved_at_a0[0x1c]; 9567 u8 wrps_status[0x4]; 9568 9569 u8 reserved_at_c0[0x8]; 9570 u8 up_threshold[0x8]; 9571 u8 reserved_at_d0[0x8]; 9572 u8 down_threshold[0x8]; 9573 9574 u8 reserved_at_e0[0x20]; 9575 9576 u8 reserved_at_100[0x1c]; 9577 u8 srps_admin[0x4]; 9578 9579 u8 reserved_at_120[0x1c]; 9580 u8 srps_status[0x4]; 9581 9582 u8 reserved_at_140[0x40]; 9583 }; 9584 9585 struct mlx5_ifc_pplr_reg_bits { 9586 u8 reserved_at_0[0x8]; 9587 u8 local_port[0x8]; 9588 u8 reserved_at_10[0x10]; 9589 9590 u8 reserved_at_20[0x8]; 9591 u8 lb_cap[0x8]; 9592 u8 reserved_at_30[0x8]; 9593 u8 lb_en[0x8]; 9594 }; 9595 9596 struct mlx5_ifc_pplm_reg_bits { 9597 u8 reserved_at_0[0x8]; 9598 u8 local_port[0x8]; 9599 u8 reserved_at_10[0x10]; 9600 9601 u8 reserved_at_20[0x20]; 9602 9603 u8 port_profile_mode[0x8]; 9604 u8 static_port_profile[0x8]; 9605 u8 active_port_profile[0x8]; 9606 u8 reserved_at_58[0x8]; 9607 9608 u8 retransmission_active[0x8]; 9609 u8 fec_mode_active[0x18]; 9610 9611 u8 rs_fec_correction_bypass_cap[0x4]; 9612 u8 reserved_at_84[0x8]; 9613 u8 fec_override_cap_56g[0x4]; 9614 u8 fec_override_cap_100g[0x4]; 9615 u8 fec_override_cap_50g[0x4]; 9616 u8 fec_override_cap_25g[0x4]; 9617 u8 fec_override_cap_10g_40g[0x4]; 9618 9619 u8 rs_fec_correction_bypass_admin[0x4]; 9620 u8 reserved_at_a4[0x8]; 9621 u8 fec_override_admin_56g[0x4]; 9622 u8 fec_override_admin_100g[0x4]; 9623 u8 fec_override_admin_50g[0x4]; 9624 u8 fec_override_admin_25g[0x4]; 9625 u8 fec_override_admin_10g_40g[0x4]; 9626 9627 u8 fec_override_cap_400g_8x[0x10]; 9628 u8 fec_override_cap_200g_4x[0x10]; 9629 9630 u8 fec_override_cap_100g_2x[0x10]; 9631 u8 fec_override_cap_50g_1x[0x10]; 9632 9633 u8 fec_override_admin_400g_8x[0x10]; 9634 u8 fec_override_admin_200g_4x[0x10]; 9635 9636 u8 fec_override_admin_100g_2x[0x10]; 9637 u8 fec_override_admin_50g_1x[0x10]; 9638 9639 u8 reserved_at_140[0x140]; 9640 }; 9641 9642 struct mlx5_ifc_ppcnt_reg_bits { 9643 u8 swid[0x8]; 9644 u8 local_port[0x8]; 9645 u8 pnat[0x2]; 9646 u8 reserved_at_12[0x8]; 9647 u8 grp[0x6]; 9648 9649 u8 clr[0x1]; 9650 u8 reserved_at_21[0x1c]; 9651 u8 prio_tc[0x3]; 9652 9653 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9654 }; 9655 9656 struct mlx5_ifc_mpein_reg_bits { 9657 u8 reserved_at_0[0x2]; 9658 u8 depth[0x6]; 9659 u8 pcie_index[0x8]; 9660 u8 node[0x8]; 9661 u8 reserved_at_18[0x8]; 9662 9663 u8 capability_mask[0x20]; 9664 9665 u8 reserved_at_40[0x8]; 9666 u8 link_width_enabled[0x8]; 9667 u8 link_speed_enabled[0x10]; 9668 9669 u8 lane0_physical_position[0x8]; 9670 u8 link_width_active[0x8]; 9671 u8 link_speed_active[0x10]; 9672 9673 u8 num_of_pfs[0x10]; 9674 u8 num_of_vfs[0x10]; 9675 9676 u8 bdf0[0x10]; 9677 u8 reserved_at_b0[0x10]; 9678 9679 u8 max_read_request_size[0x4]; 9680 u8 max_payload_size[0x4]; 9681 u8 reserved_at_c8[0x5]; 9682 u8 pwr_status[0x3]; 9683 u8 port_type[0x4]; 9684 u8 reserved_at_d4[0xb]; 9685 u8 lane_reversal[0x1]; 9686 9687 u8 reserved_at_e0[0x14]; 9688 u8 pci_power[0xc]; 9689 9690 u8 reserved_at_100[0x20]; 9691 9692 u8 device_status[0x10]; 9693 u8 port_state[0x8]; 9694 u8 reserved_at_138[0x8]; 9695 9696 u8 reserved_at_140[0x10]; 9697 u8 receiver_detect_result[0x10]; 9698 9699 u8 reserved_at_160[0x20]; 9700 }; 9701 9702 struct mlx5_ifc_mpcnt_reg_bits { 9703 u8 reserved_at_0[0x8]; 9704 u8 pcie_index[0x8]; 9705 u8 reserved_at_10[0xa]; 9706 u8 grp[0x6]; 9707 9708 u8 clr[0x1]; 9709 u8 reserved_at_21[0x1f]; 9710 9711 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9712 }; 9713 9714 struct mlx5_ifc_ppad_reg_bits { 9715 u8 reserved_at_0[0x3]; 9716 u8 single_mac[0x1]; 9717 u8 reserved_at_4[0x4]; 9718 u8 local_port[0x8]; 9719 u8 mac_47_32[0x10]; 9720 9721 u8 mac_31_0[0x20]; 9722 9723 u8 reserved_at_40[0x40]; 9724 }; 9725 9726 struct mlx5_ifc_pmtu_reg_bits { 9727 u8 reserved_at_0[0x8]; 9728 u8 local_port[0x8]; 9729 u8 reserved_at_10[0x10]; 9730 9731 u8 max_mtu[0x10]; 9732 u8 reserved_at_30[0x10]; 9733 9734 u8 admin_mtu[0x10]; 9735 u8 reserved_at_50[0x10]; 9736 9737 u8 oper_mtu[0x10]; 9738 u8 reserved_at_70[0x10]; 9739 }; 9740 9741 struct mlx5_ifc_pmpr_reg_bits { 9742 u8 reserved_at_0[0x8]; 9743 u8 module[0x8]; 9744 u8 reserved_at_10[0x10]; 9745 9746 u8 reserved_at_20[0x18]; 9747 u8 attenuation_5g[0x8]; 9748 9749 u8 reserved_at_40[0x18]; 9750 u8 attenuation_7g[0x8]; 9751 9752 u8 reserved_at_60[0x18]; 9753 u8 attenuation_12g[0x8]; 9754 }; 9755 9756 struct mlx5_ifc_pmpe_reg_bits { 9757 u8 reserved_at_0[0x8]; 9758 u8 module[0x8]; 9759 u8 reserved_at_10[0xc]; 9760 u8 module_status[0x4]; 9761 9762 u8 reserved_at_20[0x60]; 9763 }; 9764 9765 struct mlx5_ifc_pmpc_reg_bits { 9766 u8 module_state_updated[32][0x8]; 9767 }; 9768 9769 struct mlx5_ifc_pmlpn_reg_bits { 9770 u8 reserved_at_0[0x4]; 9771 u8 mlpn_status[0x4]; 9772 u8 local_port[0x8]; 9773 u8 reserved_at_10[0x10]; 9774 9775 u8 e[0x1]; 9776 u8 reserved_at_21[0x1f]; 9777 }; 9778 9779 struct mlx5_ifc_pmlp_reg_bits { 9780 u8 rxtx[0x1]; 9781 u8 reserved_at_1[0x7]; 9782 u8 local_port[0x8]; 9783 u8 reserved_at_10[0x8]; 9784 u8 width[0x8]; 9785 9786 u8 lane0_module_mapping[0x20]; 9787 9788 u8 lane1_module_mapping[0x20]; 9789 9790 u8 lane2_module_mapping[0x20]; 9791 9792 u8 lane3_module_mapping[0x20]; 9793 9794 u8 reserved_at_a0[0x160]; 9795 }; 9796 9797 struct mlx5_ifc_pmaos_reg_bits { 9798 u8 reserved_at_0[0x8]; 9799 u8 module[0x8]; 9800 u8 reserved_at_10[0x4]; 9801 u8 admin_status[0x4]; 9802 u8 reserved_at_18[0x4]; 9803 u8 oper_status[0x4]; 9804 9805 u8 ase[0x1]; 9806 u8 ee[0x1]; 9807 u8 reserved_at_22[0x1c]; 9808 u8 e[0x2]; 9809 9810 u8 reserved_at_40[0x40]; 9811 }; 9812 9813 struct mlx5_ifc_plpc_reg_bits { 9814 u8 reserved_at_0[0x4]; 9815 u8 profile_id[0xc]; 9816 u8 reserved_at_10[0x4]; 9817 u8 proto_mask[0x4]; 9818 u8 reserved_at_18[0x8]; 9819 9820 u8 reserved_at_20[0x10]; 9821 u8 lane_speed[0x10]; 9822 9823 u8 reserved_at_40[0x17]; 9824 u8 lpbf[0x1]; 9825 u8 fec_mode_policy[0x8]; 9826 9827 u8 retransmission_capability[0x8]; 9828 u8 fec_mode_capability[0x18]; 9829 9830 u8 retransmission_support_admin[0x8]; 9831 u8 fec_mode_support_admin[0x18]; 9832 9833 u8 retransmission_request_admin[0x8]; 9834 u8 fec_mode_request_admin[0x18]; 9835 9836 u8 reserved_at_c0[0x80]; 9837 }; 9838 9839 struct mlx5_ifc_plib_reg_bits { 9840 u8 reserved_at_0[0x8]; 9841 u8 local_port[0x8]; 9842 u8 reserved_at_10[0x8]; 9843 u8 ib_port[0x8]; 9844 9845 u8 reserved_at_20[0x60]; 9846 }; 9847 9848 struct mlx5_ifc_plbf_reg_bits { 9849 u8 reserved_at_0[0x8]; 9850 u8 local_port[0x8]; 9851 u8 reserved_at_10[0xd]; 9852 u8 lbf_mode[0x3]; 9853 9854 u8 reserved_at_20[0x20]; 9855 }; 9856 9857 struct mlx5_ifc_pipg_reg_bits { 9858 u8 reserved_at_0[0x8]; 9859 u8 local_port[0x8]; 9860 u8 reserved_at_10[0x10]; 9861 9862 u8 dic[0x1]; 9863 u8 reserved_at_21[0x19]; 9864 u8 ipg[0x4]; 9865 u8 reserved_at_3e[0x2]; 9866 }; 9867 9868 struct mlx5_ifc_pifr_reg_bits { 9869 u8 reserved_at_0[0x8]; 9870 u8 local_port[0x8]; 9871 u8 reserved_at_10[0x10]; 9872 9873 u8 reserved_at_20[0xe0]; 9874 9875 u8 port_filter[8][0x20]; 9876 9877 u8 port_filter_update_en[8][0x20]; 9878 }; 9879 9880 struct mlx5_ifc_pfcc_reg_bits { 9881 u8 reserved_at_0[0x8]; 9882 u8 local_port[0x8]; 9883 u8 reserved_at_10[0xb]; 9884 u8 ppan_mask_n[0x1]; 9885 u8 minor_stall_mask[0x1]; 9886 u8 critical_stall_mask[0x1]; 9887 u8 reserved_at_1e[0x2]; 9888 9889 u8 ppan[0x4]; 9890 u8 reserved_at_24[0x4]; 9891 u8 prio_mask_tx[0x8]; 9892 u8 reserved_at_30[0x8]; 9893 u8 prio_mask_rx[0x8]; 9894 9895 u8 pptx[0x1]; 9896 u8 aptx[0x1]; 9897 u8 pptx_mask_n[0x1]; 9898 u8 reserved_at_43[0x5]; 9899 u8 pfctx[0x8]; 9900 u8 reserved_at_50[0x10]; 9901 9902 u8 pprx[0x1]; 9903 u8 aprx[0x1]; 9904 u8 pprx_mask_n[0x1]; 9905 u8 reserved_at_63[0x5]; 9906 u8 pfcrx[0x8]; 9907 u8 reserved_at_70[0x10]; 9908 9909 u8 device_stall_minor_watermark[0x10]; 9910 u8 device_stall_critical_watermark[0x10]; 9911 9912 u8 reserved_at_a0[0x60]; 9913 }; 9914 9915 struct mlx5_ifc_pelc_reg_bits { 9916 u8 op[0x4]; 9917 u8 reserved_at_4[0x4]; 9918 u8 local_port[0x8]; 9919 u8 reserved_at_10[0x10]; 9920 9921 u8 op_admin[0x8]; 9922 u8 op_capability[0x8]; 9923 u8 op_request[0x8]; 9924 u8 op_active[0x8]; 9925 9926 u8 admin[0x40]; 9927 9928 u8 capability[0x40]; 9929 9930 u8 request[0x40]; 9931 9932 u8 active[0x40]; 9933 9934 u8 reserved_at_140[0x80]; 9935 }; 9936 9937 struct mlx5_ifc_peir_reg_bits { 9938 u8 reserved_at_0[0x8]; 9939 u8 local_port[0x8]; 9940 u8 reserved_at_10[0x10]; 9941 9942 u8 reserved_at_20[0xc]; 9943 u8 error_count[0x4]; 9944 u8 reserved_at_30[0x10]; 9945 9946 u8 reserved_at_40[0xc]; 9947 u8 lane[0x4]; 9948 u8 reserved_at_50[0x8]; 9949 u8 error_type[0x8]; 9950 }; 9951 9952 struct mlx5_ifc_mpegc_reg_bits { 9953 u8 reserved_at_0[0x30]; 9954 u8 field_select[0x10]; 9955 9956 u8 tx_overflow_sense[0x1]; 9957 u8 mark_cqe[0x1]; 9958 u8 mark_cnp[0x1]; 9959 u8 reserved_at_43[0x1b]; 9960 u8 tx_lossy_overflow_oper[0x2]; 9961 9962 u8 reserved_at_60[0x100]; 9963 }; 9964 9965 enum { 9966 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 9967 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 9968 }; 9969 9970 enum { 9971 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9972 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9973 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9974 }; 9975 9976 struct mlx5_ifc_mtutc_reg_bits { 9977 u8 reserved_at_0[0x5]; 9978 u8 freq_adj_units[0x3]; 9979 u8 reserved_at_8[0x14]; 9980 u8 operation[0x4]; 9981 9982 u8 freq_adjustment[0x20]; 9983 9984 u8 reserved_at_40[0x40]; 9985 9986 u8 utc_sec[0x20]; 9987 9988 u8 reserved_at_a0[0x2]; 9989 u8 utc_nsec[0x1e]; 9990 9991 u8 time_adjustment[0x20]; 9992 }; 9993 9994 struct mlx5_ifc_pcam_enhanced_features_bits { 9995 u8 reserved_at_0[0x68]; 9996 u8 fec_50G_per_lane_in_pplm[0x1]; 9997 u8 reserved_at_69[0x4]; 9998 u8 rx_icrc_encapsulated_counter[0x1]; 9999 u8 reserved_at_6e[0x4]; 10000 u8 ptys_extended_ethernet[0x1]; 10001 u8 reserved_at_73[0x3]; 10002 u8 pfcc_mask[0x1]; 10003 u8 reserved_at_77[0x3]; 10004 u8 per_lane_error_counters[0x1]; 10005 u8 rx_buffer_fullness_counters[0x1]; 10006 u8 ptys_connector_type[0x1]; 10007 u8 reserved_at_7d[0x1]; 10008 u8 ppcnt_discard_group[0x1]; 10009 u8 ppcnt_statistical_group[0x1]; 10010 }; 10011 10012 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10013 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10014 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10015 10016 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10017 u8 pplm[0x1]; 10018 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10019 10020 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10021 u8 pbmc[0x1]; 10022 u8 pptb[0x1]; 10023 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10024 u8 ppcnt[0x1]; 10025 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10026 }; 10027 10028 struct mlx5_ifc_pcam_reg_bits { 10029 u8 reserved_at_0[0x8]; 10030 u8 feature_group[0x8]; 10031 u8 reserved_at_10[0x8]; 10032 u8 access_reg_group[0x8]; 10033 10034 u8 reserved_at_20[0x20]; 10035 10036 union { 10037 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10038 u8 reserved_at_0[0x80]; 10039 } port_access_reg_cap_mask; 10040 10041 u8 reserved_at_c0[0x80]; 10042 10043 union { 10044 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10045 u8 reserved_at_0[0x80]; 10046 } feature_cap_mask; 10047 10048 u8 reserved_at_1c0[0xc0]; 10049 }; 10050 10051 struct mlx5_ifc_mcam_enhanced_features_bits { 10052 u8 reserved_at_0[0x50]; 10053 u8 mtutc_freq_adj_units[0x1]; 10054 u8 mtutc_time_adjustment_extended_range[0x1]; 10055 u8 reserved_at_52[0xb]; 10056 u8 mcia_32dwords[0x1]; 10057 u8 out_pulse_duration_ns[0x1]; 10058 u8 npps_period[0x1]; 10059 u8 reserved_at_60[0xa]; 10060 u8 reset_state[0x1]; 10061 u8 ptpcyc2realtime_modify[0x1]; 10062 u8 reserved_at_6c[0x2]; 10063 u8 pci_status_and_power[0x1]; 10064 u8 reserved_at_6f[0x5]; 10065 u8 mark_tx_action_cnp[0x1]; 10066 u8 mark_tx_action_cqe[0x1]; 10067 u8 dynamic_tx_overflow[0x1]; 10068 u8 reserved_at_77[0x4]; 10069 u8 pcie_outbound_stalled[0x1]; 10070 u8 tx_overflow_buffer_pkt[0x1]; 10071 u8 mtpps_enh_out_per_adj[0x1]; 10072 u8 mtpps_fs[0x1]; 10073 u8 pcie_performance_group[0x1]; 10074 }; 10075 10076 struct mlx5_ifc_mcam_access_reg_bits { 10077 u8 reserved_at_0[0x1c]; 10078 u8 mcda[0x1]; 10079 u8 mcc[0x1]; 10080 u8 mcqi[0x1]; 10081 u8 mcqs[0x1]; 10082 10083 u8 regs_95_to_87[0x9]; 10084 u8 mpegc[0x1]; 10085 u8 mtutc[0x1]; 10086 u8 regs_84_to_68[0x11]; 10087 u8 tracer_registers[0x4]; 10088 10089 u8 regs_63_to_46[0x12]; 10090 u8 mrtc[0x1]; 10091 u8 regs_44_to_32[0xd]; 10092 10093 u8 regs_31_to_0[0x20]; 10094 }; 10095 10096 struct mlx5_ifc_mcam_access_reg_bits1 { 10097 u8 regs_127_to_96[0x20]; 10098 10099 u8 regs_95_to_64[0x20]; 10100 10101 u8 regs_63_to_32[0x20]; 10102 10103 u8 regs_31_to_0[0x20]; 10104 }; 10105 10106 struct mlx5_ifc_mcam_access_reg_bits2 { 10107 u8 regs_127_to_99[0x1d]; 10108 u8 mirc[0x1]; 10109 u8 regs_97_to_96[0x2]; 10110 10111 u8 regs_95_to_64[0x20]; 10112 10113 u8 regs_63_to_32[0x20]; 10114 10115 u8 regs_31_to_0[0x20]; 10116 }; 10117 10118 struct mlx5_ifc_mcam_reg_bits { 10119 u8 reserved_at_0[0x8]; 10120 u8 feature_group[0x8]; 10121 u8 reserved_at_10[0x8]; 10122 u8 access_reg_group[0x8]; 10123 10124 u8 reserved_at_20[0x20]; 10125 10126 union { 10127 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10128 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10129 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10130 u8 reserved_at_0[0x80]; 10131 } mng_access_reg_cap_mask; 10132 10133 u8 reserved_at_c0[0x80]; 10134 10135 union { 10136 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10137 u8 reserved_at_0[0x80]; 10138 } mng_feature_cap_mask; 10139 10140 u8 reserved_at_1c0[0x80]; 10141 }; 10142 10143 struct mlx5_ifc_qcam_access_reg_cap_mask { 10144 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10145 u8 qpdpm[0x1]; 10146 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10147 u8 qdpm[0x1]; 10148 u8 qpts[0x1]; 10149 u8 qcap[0x1]; 10150 u8 qcam_access_reg_cap_mask_0[0x1]; 10151 }; 10152 10153 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10154 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10155 u8 qpts_trust_both[0x1]; 10156 }; 10157 10158 struct mlx5_ifc_qcam_reg_bits { 10159 u8 reserved_at_0[0x8]; 10160 u8 feature_group[0x8]; 10161 u8 reserved_at_10[0x8]; 10162 u8 access_reg_group[0x8]; 10163 u8 reserved_at_20[0x20]; 10164 10165 union { 10166 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10167 u8 reserved_at_0[0x80]; 10168 } qos_access_reg_cap_mask; 10169 10170 u8 reserved_at_c0[0x80]; 10171 10172 union { 10173 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10174 u8 reserved_at_0[0x80]; 10175 } qos_feature_cap_mask; 10176 10177 u8 reserved_at_1c0[0x80]; 10178 }; 10179 10180 struct mlx5_ifc_core_dump_reg_bits { 10181 u8 reserved_at_0[0x18]; 10182 u8 core_dump_type[0x8]; 10183 10184 u8 reserved_at_20[0x30]; 10185 u8 vhca_id[0x10]; 10186 10187 u8 reserved_at_60[0x8]; 10188 u8 qpn[0x18]; 10189 u8 reserved_at_80[0x180]; 10190 }; 10191 10192 struct mlx5_ifc_pcap_reg_bits { 10193 u8 reserved_at_0[0x8]; 10194 u8 local_port[0x8]; 10195 u8 reserved_at_10[0x10]; 10196 10197 u8 port_capability_mask[4][0x20]; 10198 }; 10199 10200 struct mlx5_ifc_paos_reg_bits { 10201 u8 swid[0x8]; 10202 u8 local_port[0x8]; 10203 u8 reserved_at_10[0x4]; 10204 u8 admin_status[0x4]; 10205 u8 reserved_at_18[0x4]; 10206 u8 oper_status[0x4]; 10207 10208 u8 ase[0x1]; 10209 u8 ee[0x1]; 10210 u8 reserved_at_22[0x1c]; 10211 u8 e[0x2]; 10212 10213 u8 reserved_at_40[0x40]; 10214 }; 10215 10216 struct mlx5_ifc_pamp_reg_bits { 10217 u8 reserved_at_0[0x8]; 10218 u8 opamp_group[0x8]; 10219 u8 reserved_at_10[0xc]; 10220 u8 opamp_group_type[0x4]; 10221 10222 u8 start_index[0x10]; 10223 u8 reserved_at_30[0x4]; 10224 u8 num_of_indices[0xc]; 10225 10226 u8 index_data[18][0x10]; 10227 }; 10228 10229 struct mlx5_ifc_pcmr_reg_bits { 10230 u8 reserved_at_0[0x8]; 10231 u8 local_port[0x8]; 10232 u8 reserved_at_10[0x10]; 10233 10234 u8 entropy_force_cap[0x1]; 10235 u8 entropy_calc_cap[0x1]; 10236 u8 entropy_gre_calc_cap[0x1]; 10237 u8 reserved_at_23[0xf]; 10238 u8 rx_ts_over_crc_cap[0x1]; 10239 u8 reserved_at_33[0xb]; 10240 u8 fcs_cap[0x1]; 10241 u8 reserved_at_3f[0x1]; 10242 10243 u8 entropy_force[0x1]; 10244 u8 entropy_calc[0x1]; 10245 u8 entropy_gre_calc[0x1]; 10246 u8 reserved_at_43[0xf]; 10247 u8 rx_ts_over_crc[0x1]; 10248 u8 reserved_at_53[0xb]; 10249 u8 fcs_chk[0x1]; 10250 u8 reserved_at_5f[0x1]; 10251 }; 10252 10253 struct mlx5_ifc_lane_2_module_mapping_bits { 10254 u8 reserved_at_0[0x4]; 10255 u8 rx_lane[0x4]; 10256 u8 reserved_at_8[0x4]; 10257 u8 tx_lane[0x4]; 10258 u8 reserved_at_10[0x8]; 10259 u8 module[0x8]; 10260 }; 10261 10262 struct mlx5_ifc_bufferx_reg_bits { 10263 u8 reserved_at_0[0x6]; 10264 u8 lossy[0x1]; 10265 u8 epsb[0x1]; 10266 u8 reserved_at_8[0x8]; 10267 u8 size[0x10]; 10268 10269 u8 xoff_threshold[0x10]; 10270 u8 xon_threshold[0x10]; 10271 }; 10272 10273 struct mlx5_ifc_set_node_in_bits { 10274 u8 node_description[64][0x8]; 10275 }; 10276 10277 struct mlx5_ifc_register_power_settings_bits { 10278 u8 reserved_at_0[0x18]; 10279 u8 power_settings_level[0x8]; 10280 10281 u8 reserved_at_20[0x60]; 10282 }; 10283 10284 struct mlx5_ifc_register_host_endianness_bits { 10285 u8 he[0x1]; 10286 u8 reserved_at_1[0x1f]; 10287 10288 u8 reserved_at_20[0x60]; 10289 }; 10290 10291 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10292 u8 reserved_at_0[0x20]; 10293 10294 u8 mkey[0x20]; 10295 10296 u8 addressh_63_32[0x20]; 10297 10298 u8 addressl_31_0[0x20]; 10299 }; 10300 10301 struct mlx5_ifc_ud_adrs_vector_bits { 10302 u8 dc_key[0x40]; 10303 10304 u8 ext[0x1]; 10305 u8 reserved_at_41[0x7]; 10306 u8 destination_qp_dct[0x18]; 10307 10308 u8 static_rate[0x4]; 10309 u8 sl_eth_prio[0x4]; 10310 u8 fl[0x1]; 10311 u8 mlid[0x7]; 10312 u8 rlid_udp_sport[0x10]; 10313 10314 u8 reserved_at_80[0x20]; 10315 10316 u8 rmac_47_16[0x20]; 10317 10318 u8 rmac_15_0[0x10]; 10319 u8 tclass[0x8]; 10320 u8 hop_limit[0x8]; 10321 10322 u8 reserved_at_e0[0x1]; 10323 u8 grh[0x1]; 10324 u8 reserved_at_e2[0x2]; 10325 u8 src_addr_index[0x8]; 10326 u8 flow_label[0x14]; 10327 10328 u8 rgid_rip[16][0x8]; 10329 }; 10330 10331 struct mlx5_ifc_pages_req_event_bits { 10332 u8 reserved_at_0[0x10]; 10333 u8 function_id[0x10]; 10334 10335 u8 num_pages[0x20]; 10336 10337 u8 reserved_at_40[0xa0]; 10338 }; 10339 10340 struct mlx5_ifc_eqe_bits { 10341 u8 reserved_at_0[0x8]; 10342 u8 event_type[0x8]; 10343 u8 reserved_at_10[0x8]; 10344 u8 event_sub_type[0x8]; 10345 10346 u8 reserved_at_20[0xe0]; 10347 10348 union mlx5_ifc_event_auto_bits event_data; 10349 10350 u8 reserved_at_1e0[0x10]; 10351 u8 signature[0x8]; 10352 u8 reserved_at_1f8[0x7]; 10353 u8 owner[0x1]; 10354 }; 10355 10356 enum { 10357 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10358 }; 10359 10360 struct mlx5_ifc_cmd_queue_entry_bits { 10361 u8 type[0x8]; 10362 u8 reserved_at_8[0x18]; 10363 10364 u8 input_length[0x20]; 10365 10366 u8 input_mailbox_pointer_63_32[0x20]; 10367 10368 u8 input_mailbox_pointer_31_9[0x17]; 10369 u8 reserved_at_77[0x9]; 10370 10371 u8 command_input_inline_data[16][0x8]; 10372 10373 u8 command_output_inline_data[16][0x8]; 10374 10375 u8 output_mailbox_pointer_63_32[0x20]; 10376 10377 u8 output_mailbox_pointer_31_9[0x17]; 10378 u8 reserved_at_1b7[0x9]; 10379 10380 u8 output_length[0x20]; 10381 10382 u8 token[0x8]; 10383 u8 signature[0x8]; 10384 u8 reserved_at_1f0[0x8]; 10385 u8 status[0x7]; 10386 u8 ownership[0x1]; 10387 }; 10388 10389 struct mlx5_ifc_cmd_out_bits { 10390 u8 status[0x8]; 10391 u8 reserved_at_8[0x18]; 10392 10393 u8 syndrome[0x20]; 10394 10395 u8 command_output[0x20]; 10396 }; 10397 10398 struct mlx5_ifc_cmd_in_bits { 10399 u8 opcode[0x10]; 10400 u8 reserved_at_10[0x10]; 10401 10402 u8 reserved_at_20[0x10]; 10403 u8 op_mod[0x10]; 10404 10405 u8 command[][0x20]; 10406 }; 10407 10408 struct mlx5_ifc_cmd_if_box_bits { 10409 u8 mailbox_data[512][0x8]; 10410 10411 u8 reserved_at_1000[0x180]; 10412 10413 u8 next_pointer_63_32[0x20]; 10414 10415 u8 next_pointer_31_10[0x16]; 10416 u8 reserved_at_11b6[0xa]; 10417 10418 u8 block_number[0x20]; 10419 10420 u8 reserved_at_11e0[0x8]; 10421 u8 token[0x8]; 10422 u8 ctrl_signature[0x8]; 10423 u8 signature[0x8]; 10424 }; 10425 10426 struct mlx5_ifc_mtt_bits { 10427 u8 ptag_63_32[0x20]; 10428 10429 u8 ptag_31_8[0x18]; 10430 u8 reserved_at_38[0x6]; 10431 u8 wr_en[0x1]; 10432 u8 rd_en[0x1]; 10433 }; 10434 10435 struct mlx5_ifc_query_wol_rol_out_bits { 10436 u8 status[0x8]; 10437 u8 reserved_at_8[0x18]; 10438 10439 u8 syndrome[0x20]; 10440 10441 u8 reserved_at_40[0x10]; 10442 u8 rol_mode[0x8]; 10443 u8 wol_mode[0x8]; 10444 10445 u8 reserved_at_60[0x20]; 10446 }; 10447 10448 struct mlx5_ifc_query_wol_rol_in_bits { 10449 u8 opcode[0x10]; 10450 u8 reserved_at_10[0x10]; 10451 10452 u8 reserved_at_20[0x10]; 10453 u8 op_mod[0x10]; 10454 10455 u8 reserved_at_40[0x40]; 10456 }; 10457 10458 struct mlx5_ifc_set_wol_rol_out_bits { 10459 u8 status[0x8]; 10460 u8 reserved_at_8[0x18]; 10461 10462 u8 syndrome[0x20]; 10463 10464 u8 reserved_at_40[0x40]; 10465 }; 10466 10467 struct mlx5_ifc_set_wol_rol_in_bits { 10468 u8 opcode[0x10]; 10469 u8 reserved_at_10[0x10]; 10470 10471 u8 reserved_at_20[0x10]; 10472 u8 op_mod[0x10]; 10473 10474 u8 rol_mode_valid[0x1]; 10475 u8 wol_mode_valid[0x1]; 10476 u8 reserved_at_42[0xe]; 10477 u8 rol_mode[0x8]; 10478 u8 wol_mode[0x8]; 10479 10480 u8 reserved_at_60[0x20]; 10481 }; 10482 10483 enum { 10484 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10485 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10486 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10487 }; 10488 10489 enum { 10490 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10491 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10492 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10493 }; 10494 10495 enum { 10496 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10497 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10498 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10499 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10500 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10501 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10502 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10503 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10504 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10505 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10506 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10507 }; 10508 10509 struct mlx5_ifc_initial_seg_bits { 10510 u8 fw_rev_minor[0x10]; 10511 u8 fw_rev_major[0x10]; 10512 10513 u8 cmd_interface_rev[0x10]; 10514 u8 fw_rev_subminor[0x10]; 10515 10516 u8 reserved_at_40[0x40]; 10517 10518 u8 cmdq_phy_addr_63_32[0x20]; 10519 10520 u8 cmdq_phy_addr_31_12[0x14]; 10521 u8 reserved_at_b4[0x2]; 10522 u8 nic_interface[0x2]; 10523 u8 log_cmdq_size[0x4]; 10524 u8 log_cmdq_stride[0x4]; 10525 10526 u8 command_doorbell_vector[0x20]; 10527 10528 u8 reserved_at_e0[0xf00]; 10529 10530 u8 initializing[0x1]; 10531 u8 reserved_at_fe1[0x4]; 10532 u8 nic_interface_supported[0x3]; 10533 u8 embedded_cpu[0x1]; 10534 u8 reserved_at_fe9[0x17]; 10535 10536 struct mlx5_ifc_health_buffer_bits health_buffer; 10537 10538 u8 no_dram_nic_offset[0x20]; 10539 10540 u8 reserved_at_1220[0x6e40]; 10541 10542 u8 reserved_at_8060[0x1f]; 10543 u8 clear_int[0x1]; 10544 10545 u8 health_syndrome[0x8]; 10546 u8 health_counter[0x18]; 10547 10548 u8 reserved_at_80a0[0x17fc0]; 10549 }; 10550 10551 struct mlx5_ifc_mtpps_reg_bits { 10552 u8 reserved_at_0[0xc]; 10553 u8 cap_number_of_pps_pins[0x4]; 10554 u8 reserved_at_10[0x4]; 10555 u8 cap_max_num_of_pps_in_pins[0x4]; 10556 u8 reserved_at_18[0x4]; 10557 u8 cap_max_num_of_pps_out_pins[0x4]; 10558 10559 u8 reserved_at_20[0x13]; 10560 u8 cap_log_min_npps_period[0x5]; 10561 u8 reserved_at_38[0x3]; 10562 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10563 10564 u8 reserved_at_40[0x4]; 10565 u8 cap_pin_3_mode[0x4]; 10566 u8 reserved_at_48[0x4]; 10567 u8 cap_pin_2_mode[0x4]; 10568 u8 reserved_at_50[0x4]; 10569 u8 cap_pin_1_mode[0x4]; 10570 u8 reserved_at_58[0x4]; 10571 u8 cap_pin_0_mode[0x4]; 10572 10573 u8 reserved_at_60[0x4]; 10574 u8 cap_pin_7_mode[0x4]; 10575 u8 reserved_at_68[0x4]; 10576 u8 cap_pin_6_mode[0x4]; 10577 u8 reserved_at_70[0x4]; 10578 u8 cap_pin_5_mode[0x4]; 10579 u8 reserved_at_78[0x4]; 10580 u8 cap_pin_4_mode[0x4]; 10581 10582 u8 field_select[0x20]; 10583 u8 reserved_at_a0[0x20]; 10584 10585 u8 npps_period[0x40]; 10586 10587 u8 enable[0x1]; 10588 u8 reserved_at_101[0xb]; 10589 u8 pattern[0x4]; 10590 u8 reserved_at_110[0x4]; 10591 u8 pin_mode[0x4]; 10592 u8 pin[0x8]; 10593 10594 u8 reserved_at_120[0x2]; 10595 u8 out_pulse_duration_ns[0x1e]; 10596 10597 u8 time_stamp[0x40]; 10598 10599 u8 out_pulse_duration[0x10]; 10600 u8 out_periodic_adjustment[0x10]; 10601 u8 enhanced_out_periodic_adjustment[0x20]; 10602 10603 u8 reserved_at_1c0[0x20]; 10604 }; 10605 10606 struct mlx5_ifc_mtppse_reg_bits { 10607 u8 reserved_at_0[0x18]; 10608 u8 pin[0x8]; 10609 u8 event_arm[0x1]; 10610 u8 reserved_at_21[0x1b]; 10611 u8 event_generation_mode[0x4]; 10612 u8 reserved_at_40[0x40]; 10613 }; 10614 10615 struct mlx5_ifc_mcqs_reg_bits { 10616 u8 last_index_flag[0x1]; 10617 u8 reserved_at_1[0x7]; 10618 u8 fw_device[0x8]; 10619 u8 component_index[0x10]; 10620 10621 u8 reserved_at_20[0x10]; 10622 u8 identifier[0x10]; 10623 10624 u8 reserved_at_40[0x17]; 10625 u8 component_status[0x5]; 10626 u8 component_update_state[0x4]; 10627 10628 u8 last_update_state_changer_type[0x4]; 10629 u8 last_update_state_changer_host_id[0x4]; 10630 u8 reserved_at_68[0x18]; 10631 }; 10632 10633 struct mlx5_ifc_mcqi_cap_bits { 10634 u8 supported_info_bitmask[0x20]; 10635 10636 u8 component_size[0x20]; 10637 10638 u8 max_component_size[0x20]; 10639 10640 u8 log_mcda_word_size[0x4]; 10641 u8 reserved_at_64[0xc]; 10642 u8 mcda_max_write_size[0x10]; 10643 10644 u8 rd_en[0x1]; 10645 u8 reserved_at_81[0x1]; 10646 u8 match_chip_id[0x1]; 10647 u8 match_psid[0x1]; 10648 u8 check_user_timestamp[0x1]; 10649 u8 match_base_guid_mac[0x1]; 10650 u8 reserved_at_86[0x1a]; 10651 }; 10652 10653 struct mlx5_ifc_mcqi_version_bits { 10654 u8 reserved_at_0[0x2]; 10655 u8 build_time_valid[0x1]; 10656 u8 user_defined_time_valid[0x1]; 10657 u8 reserved_at_4[0x14]; 10658 u8 version_string_length[0x8]; 10659 10660 u8 version[0x20]; 10661 10662 u8 build_time[0x40]; 10663 10664 u8 user_defined_time[0x40]; 10665 10666 u8 build_tool_version[0x20]; 10667 10668 u8 reserved_at_e0[0x20]; 10669 10670 u8 version_string[92][0x8]; 10671 }; 10672 10673 struct mlx5_ifc_mcqi_activation_method_bits { 10674 u8 pending_server_ac_power_cycle[0x1]; 10675 u8 pending_server_dc_power_cycle[0x1]; 10676 u8 pending_server_reboot[0x1]; 10677 u8 pending_fw_reset[0x1]; 10678 u8 auto_activate[0x1]; 10679 u8 all_hosts_sync[0x1]; 10680 u8 device_hw_reset[0x1]; 10681 u8 reserved_at_7[0x19]; 10682 }; 10683 10684 union mlx5_ifc_mcqi_reg_data_bits { 10685 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10686 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10687 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10688 }; 10689 10690 struct mlx5_ifc_mcqi_reg_bits { 10691 u8 read_pending_component[0x1]; 10692 u8 reserved_at_1[0xf]; 10693 u8 component_index[0x10]; 10694 10695 u8 reserved_at_20[0x20]; 10696 10697 u8 reserved_at_40[0x1b]; 10698 u8 info_type[0x5]; 10699 10700 u8 info_size[0x20]; 10701 10702 u8 offset[0x20]; 10703 10704 u8 reserved_at_a0[0x10]; 10705 u8 data_size[0x10]; 10706 10707 union mlx5_ifc_mcqi_reg_data_bits data[]; 10708 }; 10709 10710 struct mlx5_ifc_mcc_reg_bits { 10711 u8 reserved_at_0[0x4]; 10712 u8 time_elapsed_since_last_cmd[0xc]; 10713 u8 reserved_at_10[0x8]; 10714 u8 instruction[0x8]; 10715 10716 u8 reserved_at_20[0x10]; 10717 u8 component_index[0x10]; 10718 10719 u8 reserved_at_40[0x8]; 10720 u8 update_handle[0x18]; 10721 10722 u8 handle_owner_type[0x4]; 10723 u8 handle_owner_host_id[0x4]; 10724 u8 reserved_at_68[0x1]; 10725 u8 control_progress[0x7]; 10726 u8 error_code[0x8]; 10727 u8 reserved_at_78[0x4]; 10728 u8 control_state[0x4]; 10729 10730 u8 component_size[0x20]; 10731 10732 u8 reserved_at_a0[0x60]; 10733 }; 10734 10735 struct mlx5_ifc_mcda_reg_bits { 10736 u8 reserved_at_0[0x8]; 10737 u8 update_handle[0x18]; 10738 10739 u8 offset[0x20]; 10740 10741 u8 reserved_at_40[0x10]; 10742 u8 size[0x10]; 10743 10744 u8 reserved_at_60[0x20]; 10745 10746 u8 data[][0x20]; 10747 }; 10748 10749 enum { 10750 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10751 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10752 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10753 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10754 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10755 }; 10756 10757 enum { 10758 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10759 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10760 }; 10761 10762 enum { 10763 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10764 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10765 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10766 }; 10767 10768 struct mlx5_ifc_mfrl_reg_bits { 10769 u8 reserved_at_0[0x20]; 10770 10771 u8 reserved_at_20[0x2]; 10772 u8 pci_sync_for_fw_update_start[0x1]; 10773 u8 pci_sync_for_fw_update_resp[0x2]; 10774 u8 rst_type_sel[0x3]; 10775 u8 reserved_at_28[0x4]; 10776 u8 reset_state[0x4]; 10777 u8 reset_type[0x8]; 10778 u8 reset_level[0x8]; 10779 }; 10780 10781 struct mlx5_ifc_mirc_reg_bits { 10782 u8 reserved_at_0[0x18]; 10783 u8 status_code[0x8]; 10784 10785 u8 reserved_at_20[0x20]; 10786 }; 10787 10788 struct mlx5_ifc_pddr_monitor_opcode_bits { 10789 u8 reserved_at_0[0x10]; 10790 u8 monitor_opcode[0x10]; 10791 }; 10792 10793 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10794 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10795 u8 reserved_at_0[0x20]; 10796 }; 10797 10798 enum { 10799 /* Monitor opcodes */ 10800 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10801 }; 10802 10803 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10804 u8 reserved_at_0[0x10]; 10805 u8 group_opcode[0x10]; 10806 10807 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10808 10809 u8 reserved_at_40[0x20]; 10810 10811 u8 status_message[59][0x20]; 10812 }; 10813 10814 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10815 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10816 u8 reserved_at_0[0x7c0]; 10817 }; 10818 10819 enum { 10820 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10821 }; 10822 10823 struct mlx5_ifc_pddr_reg_bits { 10824 u8 reserved_at_0[0x8]; 10825 u8 local_port[0x8]; 10826 u8 pnat[0x2]; 10827 u8 reserved_at_12[0xe]; 10828 10829 u8 reserved_at_20[0x18]; 10830 u8 page_select[0x8]; 10831 10832 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10833 }; 10834 10835 struct mlx5_ifc_mrtc_reg_bits { 10836 u8 time_synced[0x1]; 10837 u8 reserved_at_1[0x1f]; 10838 10839 u8 reserved_at_20[0x20]; 10840 10841 u8 time_h[0x20]; 10842 10843 u8 time_l[0x20]; 10844 }; 10845 10846 union mlx5_ifc_ports_control_registers_document_bits { 10847 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10848 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10849 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10850 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10851 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10852 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10853 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10854 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10855 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10856 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10857 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10858 struct mlx5_ifc_paos_reg_bits paos_reg; 10859 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10860 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10861 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10862 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10863 struct mlx5_ifc_peir_reg_bits peir_reg; 10864 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10865 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10866 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10867 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10868 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10869 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10870 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10871 struct mlx5_ifc_plib_reg_bits plib_reg; 10872 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10873 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10874 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10875 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10876 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10877 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10878 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10879 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10880 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10881 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10882 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10883 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10884 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10885 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10886 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10887 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10888 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10889 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10890 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10891 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10892 struct mlx5_ifc_pude_reg_bits pude_reg; 10893 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10894 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10895 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10896 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10897 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10898 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10899 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10900 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10901 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10902 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10903 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10904 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10905 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10906 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10907 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10908 u8 reserved_at_0[0x60e0]; 10909 }; 10910 10911 union mlx5_ifc_debug_enhancements_document_bits { 10912 struct mlx5_ifc_health_buffer_bits health_buffer; 10913 u8 reserved_at_0[0x200]; 10914 }; 10915 10916 union mlx5_ifc_uplink_pci_interface_document_bits { 10917 struct mlx5_ifc_initial_seg_bits initial_seg; 10918 u8 reserved_at_0[0x20060]; 10919 }; 10920 10921 struct mlx5_ifc_set_flow_table_root_out_bits { 10922 u8 status[0x8]; 10923 u8 reserved_at_8[0x18]; 10924 10925 u8 syndrome[0x20]; 10926 10927 u8 reserved_at_40[0x40]; 10928 }; 10929 10930 struct mlx5_ifc_set_flow_table_root_in_bits { 10931 u8 opcode[0x10]; 10932 u8 reserved_at_10[0x10]; 10933 10934 u8 reserved_at_20[0x10]; 10935 u8 op_mod[0x10]; 10936 10937 u8 other_vport[0x1]; 10938 u8 reserved_at_41[0xf]; 10939 u8 vport_number[0x10]; 10940 10941 u8 reserved_at_60[0x20]; 10942 10943 u8 table_type[0x8]; 10944 u8 reserved_at_88[0x7]; 10945 u8 table_of_other_vport[0x1]; 10946 u8 table_vport_number[0x10]; 10947 10948 u8 reserved_at_a0[0x8]; 10949 u8 table_id[0x18]; 10950 10951 u8 reserved_at_c0[0x8]; 10952 u8 underlay_qpn[0x18]; 10953 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10954 u8 reserved_at_e1[0xf]; 10955 u8 table_eswitch_owner_vhca_id[0x10]; 10956 u8 reserved_at_100[0x100]; 10957 }; 10958 10959 enum { 10960 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10961 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10962 }; 10963 10964 struct mlx5_ifc_modify_flow_table_out_bits { 10965 u8 status[0x8]; 10966 u8 reserved_at_8[0x18]; 10967 10968 u8 syndrome[0x20]; 10969 10970 u8 reserved_at_40[0x40]; 10971 }; 10972 10973 struct mlx5_ifc_modify_flow_table_in_bits { 10974 u8 opcode[0x10]; 10975 u8 reserved_at_10[0x10]; 10976 10977 u8 reserved_at_20[0x10]; 10978 u8 op_mod[0x10]; 10979 10980 u8 other_vport[0x1]; 10981 u8 reserved_at_41[0xf]; 10982 u8 vport_number[0x10]; 10983 10984 u8 reserved_at_60[0x10]; 10985 u8 modify_field_select[0x10]; 10986 10987 u8 table_type[0x8]; 10988 u8 reserved_at_88[0x18]; 10989 10990 u8 reserved_at_a0[0x8]; 10991 u8 table_id[0x18]; 10992 10993 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10994 }; 10995 10996 struct mlx5_ifc_ets_tcn_config_reg_bits { 10997 u8 g[0x1]; 10998 u8 b[0x1]; 10999 u8 r[0x1]; 11000 u8 reserved_at_3[0x9]; 11001 u8 group[0x4]; 11002 u8 reserved_at_10[0x9]; 11003 u8 bw_allocation[0x7]; 11004 11005 u8 reserved_at_20[0xc]; 11006 u8 max_bw_units[0x4]; 11007 u8 reserved_at_30[0x8]; 11008 u8 max_bw_value[0x8]; 11009 }; 11010 11011 struct mlx5_ifc_ets_global_config_reg_bits { 11012 u8 reserved_at_0[0x2]; 11013 u8 r[0x1]; 11014 u8 reserved_at_3[0x1d]; 11015 11016 u8 reserved_at_20[0xc]; 11017 u8 max_bw_units[0x4]; 11018 u8 reserved_at_30[0x8]; 11019 u8 max_bw_value[0x8]; 11020 }; 11021 11022 struct mlx5_ifc_qetc_reg_bits { 11023 u8 reserved_at_0[0x8]; 11024 u8 port_number[0x8]; 11025 u8 reserved_at_10[0x30]; 11026 11027 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11028 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11029 }; 11030 11031 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11032 u8 e[0x1]; 11033 u8 reserved_at_01[0x0b]; 11034 u8 prio[0x04]; 11035 }; 11036 11037 struct mlx5_ifc_qpdpm_reg_bits { 11038 u8 reserved_at_0[0x8]; 11039 u8 local_port[0x8]; 11040 u8 reserved_at_10[0x10]; 11041 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11042 }; 11043 11044 struct mlx5_ifc_qpts_reg_bits { 11045 u8 reserved_at_0[0x8]; 11046 u8 local_port[0x8]; 11047 u8 reserved_at_10[0x2d]; 11048 u8 trust_state[0x3]; 11049 }; 11050 11051 struct mlx5_ifc_pptb_reg_bits { 11052 u8 reserved_at_0[0x2]; 11053 u8 mm[0x2]; 11054 u8 reserved_at_4[0x4]; 11055 u8 local_port[0x8]; 11056 u8 reserved_at_10[0x6]; 11057 u8 cm[0x1]; 11058 u8 um[0x1]; 11059 u8 pm[0x8]; 11060 11061 u8 prio_x_buff[0x20]; 11062 11063 u8 pm_msb[0x8]; 11064 u8 reserved_at_48[0x10]; 11065 u8 ctrl_buff[0x4]; 11066 u8 untagged_buff[0x4]; 11067 }; 11068 11069 struct mlx5_ifc_sbcam_reg_bits { 11070 u8 reserved_at_0[0x8]; 11071 u8 feature_group[0x8]; 11072 u8 reserved_at_10[0x8]; 11073 u8 access_reg_group[0x8]; 11074 11075 u8 reserved_at_20[0x20]; 11076 11077 u8 sb_access_reg_cap_mask[4][0x20]; 11078 11079 u8 reserved_at_c0[0x80]; 11080 11081 u8 sb_feature_cap_mask[4][0x20]; 11082 11083 u8 reserved_at_1c0[0x40]; 11084 11085 u8 cap_total_buffer_size[0x20]; 11086 11087 u8 cap_cell_size[0x10]; 11088 u8 cap_max_pg_buffers[0x8]; 11089 u8 cap_num_pool_supported[0x8]; 11090 11091 u8 reserved_at_240[0x8]; 11092 u8 cap_sbsr_stat_size[0x8]; 11093 u8 cap_max_tclass_data[0x8]; 11094 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11095 }; 11096 11097 struct mlx5_ifc_pbmc_reg_bits { 11098 u8 reserved_at_0[0x8]; 11099 u8 local_port[0x8]; 11100 u8 reserved_at_10[0x10]; 11101 11102 u8 xoff_timer_value[0x10]; 11103 u8 xoff_refresh[0x10]; 11104 11105 u8 reserved_at_40[0x9]; 11106 u8 fullness_threshold[0x7]; 11107 u8 port_buffer_size[0x10]; 11108 11109 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11110 11111 u8 reserved_at_2e0[0x80]; 11112 }; 11113 11114 struct mlx5_ifc_sbpr_reg_bits { 11115 u8 desc[0x1]; 11116 u8 snap[0x1]; 11117 u8 reserved_at_2[0x4]; 11118 u8 dir[0x2]; 11119 u8 reserved_at_8[0x14]; 11120 u8 pool[0x4]; 11121 11122 u8 infi_size[0x1]; 11123 u8 reserved_at_21[0x7]; 11124 u8 size[0x18]; 11125 11126 u8 reserved_at_40[0x1c]; 11127 u8 mode[0x4]; 11128 11129 u8 reserved_at_60[0x8]; 11130 u8 buff_occupancy[0x18]; 11131 11132 u8 clr[0x1]; 11133 u8 reserved_at_81[0x7]; 11134 u8 max_buff_occupancy[0x18]; 11135 11136 u8 reserved_at_a0[0x8]; 11137 u8 ext_buff_occupancy[0x18]; 11138 }; 11139 11140 struct mlx5_ifc_sbcm_reg_bits { 11141 u8 desc[0x1]; 11142 u8 snap[0x1]; 11143 u8 reserved_at_2[0x6]; 11144 u8 local_port[0x8]; 11145 u8 pnat[0x2]; 11146 u8 pg_buff[0x6]; 11147 u8 reserved_at_18[0x6]; 11148 u8 dir[0x2]; 11149 11150 u8 reserved_at_20[0x1f]; 11151 u8 exc[0x1]; 11152 11153 u8 reserved_at_40[0x40]; 11154 11155 u8 reserved_at_80[0x8]; 11156 u8 buff_occupancy[0x18]; 11157 11158 u8 clr[0x1]; 11159 u8 reserved_at_a1[0x7]; 11160 u8 max_buff_occupancy[0x18]; 11161 11162 u8 reserved_at_c0[0x8]; 11163 u8 min_buff[0x18]; 11164 11165 u8 infi_max[0x1]; 11166 u8 reserved_at_e1[0x7]; 11167 u8 max_buff[0x18]; 11168 11169 u8 reserved_at_100[0x20]; 11170 11171 u8 reserved_at_120[0x1c]; 11172 u8 pool[0x4]; 11173 }; 11174 11175 struct mlx5_ifc_qtct_reg_bits { 11176 u8 reserved_at_0[0x8]; 11177 u8 port_number[0x8]; 11178 u8 reserved_at_10[0xd]; 11179 u8 prio[0x3]; 11180 11181 u8 reserved_at_20[0x1d]; 11182 u8 tclass[0x3]; 11183 }; 11184 11185 struct mlx5_ifc_mcia_reg_bits { 11186 u8 l[0x1]; 11187 u8 reserved_at_1[0x7]; 11188 u8 module[0x8]; 11189 u8 reserved_at_10[0x8]; 11190 u8 status[0x8]; 11191 11192 u8 i2c_device_address[0x8]; 11193 u8 page_number[0x8]; 11194 u8 device_address[0x10]; 11195 11196 u8 reserved_at_40[0x10]; 11197 u8 size[0x10]; 11198 11199 u8 reserved_at_60[0x20]; 11200 11201 u8 dword_0[0x20]; 11202 u8 dword_1[0x20]; 11203 u8 dword_2[0x20]; 11204 u8 dword_3[0x20]; 11205 u8 dword_4[0x20]; 11206 u8 dword_5[0x20]; 11207 u8 dword_6[0x20]; 11208 u8 dword_7[0x20]; 11209 u8 dword_8[0x20]; 11210 u8 dword_9[0x20]; 11211 u8 dword_10[0x20]; 11212 u8 dword_11[0x20]; 11213 }; 11214 11215 struct mlx5_ifc_dcbx_param_bits { 11216 u8 dcbx_cee_cap[0x1]; 11217 u8 dcbx_ieee_cap[0x1]; 11218 u8 dcbx_standby_cap[0x1]; 11219 u8 reserved_at_3[0x5]; 11220 u8 port_number[0x8]; 11221 u8 reserved_at_10[0xa]; 11222 u8 max_application_table_size[6]; 11223 u8 reserved_at_20[0x15]; 11224 u8 version_oper[0x3]; 11225 u8 reserved_at_38[5]; 11226 u8 version_admin[0x3]; 11227 u8 willing_admin[0x1]; 11228 u8 reserved_at_41[0x3]; 11229 u8 pfc_cap_oper[0x4]; 11230 u8 reserved_at_48[0x4]; 11231 u8 pfc_cap_admin[0x4]; 11232 u8 reserved_at_50[0x4]; 11233 u8 num_of_tc_oper[0x4]; 11234 u8 reserved_at_58[0x4]; 11235 u8 num_of_tc_admin[0x4]; 11236 u8 remote_willing[0x1]; 11237 u8 reserved_at_61[3]; 11238 u8 remote_pfc_cap[4]; 11239 u8 reserved_at_68[0x14]; 11240 u8 remote_num_of_tc[0x4]; 11241 u8 reserved_at_80[0x18]; 11242 u8 error[0x8]; 11243 u8 reserved_at_a0[0x160]; 11244 }; 11245 11246 enum { 11247 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11248 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11249 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11250 }; 11251 11252 struct mlx5_ifc_lagc_bits { 11253 u8 fdb_selection_mode[0x1]; 11254 u8 reserved_at_1[0x14]; 11255 u8 port_select_mode[0x3]; 11256 u8 reserved_at_18[0x5]; 11257 u8 lag_state[0x3]; 11258 11259 u8 reserved_at_20[0xc]; 11260 u8 active_port[0x4]; 11261 u8 reserved_at_30[0x4]; 11262 u8 tx_remap_affinity_2[0x4]; 11263 u8 reserved_at_38[0x4]; 11264 u8 tx_remap_affinity_1[0x4]; 11265 }; 11266 11267 struct mlx5_ifc_create_lag_out_bits { 11268 u8 status[0x8]; 11269 u8 reserved_at_8[0x18]; 11270 11271 u8 syndrome[0x20]; 11272 11273 u8 reserved_at_40[0x40]; 11274 }; 11275 11276 struct mlx5_ifc_create_lag_in_bits { 11277 u8 opcode[0x10]; 11278 u8 reserved_at_10[0x10]; 11279 11280 u8 reserved_at_20[0x10]; 11281 u8 op_mod[0x10]; 11282 11283 struct mlx5_ifc_lagc_bits ctx; 11284 }; 11285 11286 struct mlx5_ifc_modify_lag_out_bits { 11287 u8 status[0x8]; 11288 u8 reserved_at_8[0x18]; 11289 11290 u8 syndrome[0x20]; 11291 11292 u8 reserved_at_40[0x40]; 11293 }; 11294 11295 struct mlx5_ifc_modify_lag_in_bits { 11296 u8 opcode[0x10]; 11297 u8 reserved_at_10[0x10]; 11298 11299 u8 reserved_at_20[0x10]; 11300 u8 op_mod[0x10]; 11301 11302 u8 reserved_at_40[0x20]; 11303 u8 field_select[0x20]; 11304 11305 struct mlx5_ifc_lagc_bits ctx; 11306 }; 11307 11308 struct mlx5_ifc_query_lag_out_bits { 11309 u8 status[0x8]; 11310 u8 reserved_at_8[0x18]; 11311 11312 u8 syndrome[0x20]; 11313 11314 struct mlx5_ifc_lagc_bits ctx; 11315 }; 11316 11317 struct mlx5_ifc_query_lag_in_bits { 11318 u8 opcode[0x10]; 11319 u8 reserved_at_10[0x10]; 11320 11321 u8 reserved_at_20[0x10]; 11322 u8 op_mod[0x10]; 11323 11324 u8 reserved_at_40[0x40]; 11325 }; 11326 11327 struct mlx5_ifc_destroy_lag_out_bits { 11328 u8 status[0x8]; 11329 u8 reserved_at_8[0x18]; 11330 11331 u8 syndrome[0x20]; 11332 11333 u8 reserved_at_40[0x40]; 11334 }; 11335 11336 struct mlx5_ifc_destroy_lag_in_bits { 11337 u8 opcode[0x10]; 11338 u8 reserved_at_10[0x10]; 11339 11340 u8 reserved_at_20[0x10]; 11341 u8 op_mod[0x10]; 11342 11343 u8 reserved_at_40[0x40]; 11344 }; 11345 11346 struct mlx5_ifc_create_vport_lag_out_bits { 11347 u8 status[0x8]; 11348 u8 reserved_at_8[0x18]; 11349 11350 u8 syndrome[0x20]; 11351 11352 u8 reserved_at_40[0x40]; 11353 }; 11354 11355 struct mlx5_ifc_create_vport_lag_in_bits { 11356 u8 opcode[0x10]; 11357 u8 reserved_at_10[0x10]; 11358 11359 u8 reserved_at_20[0x10]; 11360 u8 op_mod[0x10]; 11361 11362 u8 reserved_at_40[0x40]; 11363 }; 11364 11365 struct mlx5_ifc_destroy_vport_lag_out_bits { 11366 u8 status[0x8]; 11367 u8 reserved_at_8[0x18]; 11368 11369 u8 syndrome[0x20]; 11370 11371 u8 reserved_at_40[0x40]; 11372 }; 11373 11374 struct mlx5_ifc_destroy_vport_lag_in_bits { 11375 u8 opcode[0x10]; 11376 u8 reserved_at_10[0x10]; 11377 11378 u8 reserved_at_20[0x10]; 11379 u8 op_mod[0x10]; 11380 11381 u8 reserved_at_40[0x40]; 11382 }; 11383 11384 enum { 11385 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11386 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11387 }; 11388 11389 struct mlx5_ifc_modify_memic_in_bits { 11390 u8 opcode[0x10]; 11391 u8 uid[0x10]; 11392 11393 u8 reserved_at_20[0x10]; 11394 u8 op_mod[0x10]; 11395 11396 u8 reserved_at_40[0x20]; 11397 11398 u8 reserved_at_60[0x18]; 11399 u8 memic_operation_type[0x8]; 11400 11401 u8 memic_start_addr[0x40]; 11402 11403 u8 reserved_at_c0[0x140]; 11404 }; 11405 11406 struct mlx5_ifc_modify_memic_out_bits { 11407 u8 status[0x8]; 11408 u8 reserved_at_8[0x18]; 11409 11410 u8 syndrome[0x20]; 11411 11412 u8 reserved_at_40[0x40]; 11413 11414 u8 memic_operation_addr[0x40]; 11415 11416 u8 reserved_at_c0[0x140]; 11417 }; 11418 11419 struct mlx5_ifc_alloc_memic_in_bits { 11420 u8 opcode[0x10]; 11421 u8 reserved_at_10[0x10]; 11422 11423 u8 reserved_at_20[0x10]; 11424 u8 op_mod[0x10]; 11425 11426 u8 reserved_at_30[0x20]; 11427 11428 u8 reserved_at_40[0x18]; 11429 u8 log_memic_addr_alignment[0x8]; 11430 11431 u8 range_start_addr[0x40]; 11432 11433 u8 range_size[0x20]; 11434 11435 u8 memic_size[0x20]; 11436 }; 11437 11438 struct mlx5_ifc_alloc_memic_out_bits { 11439 u8 status[0x8]; 11440 u8 reserved_at_8[0x18]; 11441 11442 u8 syndrome[0x20]; 11443 11444 u8 memic_start_addr[0x40]; 11445 }; 11446 11447 struct mlx5_ifc_dealloc_memic_in_bits { 11448 u8 opcode[0x10]; 11449 u8 reserved_at_10[0x10]; 11450 11451 u8 reserved_at_20[0x10]; 11452 u8 op_mod[0x10]; 11453 11454 u8 reserved_at_40[0x40]; 11455 11456 u8 memic_start_addr[0x40]; 11457 11458 u8 memic_size[0x20]; 11459 11460 u8 reserved_at_e0[0x20]; 11461 }; 11462 11463 struct mlx5_ifc_dealloc_memic_out_bits { 11464 u8 status[0x8]; 11465 u8 reserved_at_8[0x18]; 11466 11467 u8 syndrome[0x20]; 11468 11469 u8 reserved_at_40[0x40]; 11470 }; 11471 11472 struct mlx5_ifc_umem_bits { 11473 u8 reserved_at_0[0x80]; 11474 11475 u8 ats[0x1]; 11476 u8 reserved_at_81[0x1a]; 11477 u8 log_page_size[0x5]; 11478 11479 u8 page_offset[0x20]; 11480 11481 u8 num_of_mtt[0x40]; 11482 11483 struct mlx5_ifc_mtt_bits mtt[]; 11484 }; 11485 11486 struct mlx5_ifc_uctx_bits { 11487 u8 cap[0x20]; 11488 11489 u8 reserved_at_20[0x160]; 11490 }; 11491 11492 struct mlx5_ifc_sw_icm_bits { 11493 u8 modify_field_select[0x40]; 11494 11495 u8 reserved_at_40[0x18]; 11496 u8 log_sw_icm_size[0x8]; 11497 11498 u8 reserved_at_60[0x20]; 11499 11500 u8 sw_icm_start_addr[0x40]; 11501 11502 u8 reserved_at_c0[0x140]; 11503 }; 11504 11505 struct mlx5_ifc_geneve_tlv_option_bits { 11506 u8 modify_field_select[0x40]; 11507 11508 u8 reserved_at_40[0x18]; 11509 u8 geneve_option_fte_index[0x8]; 11510 11511 u8 option_class[0x10]; 11512 u8 option_type[0x8]; 11513 u8 reserved_at_78[0x3]; 11514 u8 option_data_length[0x5]; 11515 11516 u8 reserved_at_80[0x180]; 11517 }; 11518 11519 struct mlx5_ifc_create_umem_in_bits { 11520 u8 opcode[0x10]; 11521 u8 uid[0x10]; 11522 11523 u8 reserved_at_20[0x10]; 11524 u8 op_mod[0x10]; 11525 11526 u8 reserved_at_40[0x40]; 11527 11528 struct mlx5_ifc_umem_bits umem; 11529 }; 11530 11531 struct mlx5_ifc_create_umem_out_bits { 11532 u8 status[0x8]; 11533 u8 reserved_at_8[0x18]; 11534 11535 u8 syndrome[0x20]; 11536 11537 u8 reserved_at_40[0x8]; 11538 u8 umem_id[0x18]; 11539 11540 u8 reserved_at_60[0x20]; 11541 }; 11542 11543 struct mlx5_ifc_destroy_umem_in_bits { 11544 u8 opcode[0x10]; 11545 u8 uid[0x10]; 11546 11547 u8 reserved_at_20[0x10]; 11548 u8 op_mod[0x10]; 11549 11550 u8 reserved_at_40[0x8]; 11551 u8 umem_id[0x18]; 11552 11553 u8 reserved_at_60[0x20]; 11554 }; 11555 11556 struct mlx5_ifc_destroy_umem_out_bits { 11557 u8 status[0x8]; 11558 u8 reserved_at_8[0x18]; 11559 11560 u8 syndrome[0x20]; 11561 11562 u8 reserved_at_40[0x40]; 11563 }; 11564 11565 struct mlx5_ifc_create_uctx_in_bits { 11566 u8 opcode[0x10]; 11567 u8 reserved_at_10[0x10]; 11568 11569 u8 reserved_at_20[0x10]; 11570 u8 op_mod[0x10]; 11571 11572 u8 reserved_at_40[0x40]; 11573 11574 struct mlx5_ifc_uctx_bits uctx; 11575 }; 11576 11577 struct mlx5_ifc_create_uctx_out_bits { 11578 u8 status[0x8]; 11579 u8 reserved_at_8[0x18]; 11580 11581 u8 syndrome[0x20]; 11582 11583 u8 reserved_at_40[0x10]; 11584 u8 uid[0x10]; 11585 11586 u8 reserved_at_60[0x20]; 11587 }; 11588 11589 struct mlx5_ifc_destroy_uctx_in_bits { 11590 u8 opcode[0x10]; 11591 u8 reserved_at_10[0x10]; 11592 11593 u8 reserved_at_20[0x10]; 11594 u8 op_mod[0x10]; 11595 11596 u8 reserved_at_40[0x10]; 11597 u8 uid[0x10]; 11598 11599 u8 reserved_at_60[0x20]; 11600 }; 11601 11602 struct mlx5_ifc_destroy_uctx_out_bits { 11603 u8 status[0x8]; 11604 u8 reserved_at_8[0x18]; 11605 11606 u8 syndrome[0x20]; 11607 11608 u8 reserved_at_40[0x40]; 11609 }; 11610 11611 struct mlx5_ifc_create_sw_icm_in_bits { 11612 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11613 struct mlx5_ifc_sw_icm_bits sw_icm; 11614 }; 11615 11616 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11617 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11618 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11619 }; 11620 11621 struct mlx5_ifc_mtrc_string_db_param_bits { 11622 u8 string_db_base_address[0x20]; 11623 11624 u8 reserved_at_20[0x8]; 11625 u8 string_db_size[0x18]; 11626 }; 11627 11628 struct mlx5_ifc_mtrc_cap_bits { 11629 u8 trace_owner[0x1]; 11630 u8 trace_to_memory[0x1]; 11631 u8 reserved_at_2[0x4]; 11632 u8 trc_ver[0x2]; 11633 u8 reserved_at_8[0x14]; 11634 u8 num_string_db[0x4]; 11635 11636 u8 first_string_trace[0x8]; 11637 u8 num_string_trace[0x8]; 11638 u8 reserved_at_30[0x28]; 11639 11640 u8 log_max_trace_buffer_size[0x8]; 11641 11642 u8 reserved_at_60[0x20]; 11643 11644 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11645 11646 u8 reserved_at_280[0x180]; 11647 }; 11648 11649 struct mlx5_ifc_mtrc_conf_bits { 11650 u8 reserved_at_0[0x1c]; 11651 u8 trace_mode[0x4]; 11652 u8 reserved_at_20[0x18]; 11653 u8 log_trace_buffer_size[0x8]; 11654 u8 trace_mkey[0x20]; 11655 u8 reserved_at_60[0x3a0]; 11656 }; 11657 11658 struct mlx5_ifc_mtrc_stdb_bits { 11659 u8 string_db_index[0x4]; 11660 u8 reserved_at_4[0x4]; 11661 u8 read_size[0x18]; 11662 u8 start_offset[0x20]; 11663 u8 string_db_data[]; 11664 }; 11665 11666 struct mlx5_ifc_mtrc_ctrl_bits { 11667 u8 trace_status[0x2]; 11668 u8 reserved_at_2[0x2]; 11669 u8 arm_event[0x1]; 11670 u8 reserved_at_5[0xb]; 11671 u8 modify_field_select[0x10]; 11672 u8 reserved_at_20[0x2b]; 11673 u8 current_timestamp52_32[0x15]; 11674 u8 current_timestamp31_0[0x20]; 11675 u8 reserved_at_80[0x180]; 11676 }; 11677 11678 struct mlx5_ifc_host_params_context_bits { 11679 u8 host_number[0x8]; 11680 u8 reserved_at_8[0x7]; 11681 u8 host_pf_disabled[0x1]; 11682 u8 host_num_of_vfs[0x10]; 11683 11684 u8 host_total_vfs[0x10]; 11685 u8 host_pci_bus[0x10]; 11686 11687 u8 reserved_at_40[0x10]; 11688 u8 host_pci_device[0x10]; 11689 11690 u8 reserved_at_60[0x10]; 11691 u8 host_pci_function[0x10]; 11692 11693 u8 reserved_at_80[0x180]; 11694 }; 11695 11696 struct mlx5_ifc_query_esw_functions_in_bits { 11697 u8 opcode[0x10]; 11698 u8 reserved_at_10[0x10]; 11699 11700 u8 reserved_at_20[0x10]; 11701 u8 op_mod[0x10]; 11702 11703 u8 reserved_at_40[0x40]; 11704 }; 11705 11706 struct mlx5_ifc_query_esw_functions_out_bits { 11707 u8 status[0x8]; 11708 u8 reserved_at_8[0x18]; 11709 11710 u8 syndrome[0x20]; 11711 11712 u8 reserved_at_40[0x40]; 11713 11714 struct mlx5_ifc_host_params_context_bits host_params_context; 11715 11716 u8 reserved_at_280[0x180]; 11717 u8 host_sf_enable[][0x40]; 11718 }; 11719 11720 struct mlx5_ifc_sf_partition_bits { 11721 u8 reserved_at_0[0x10]; 11722 u8 log_num_sf[0x8]; 11723 u8 log_sf_bar_size[0x8]; 11724 }; 11725 11726 struct mlx5_ifc_query_sf_partitions_out_bits { 11727 u8 status[0x8]; 11728 u8 reserved_at_8[0x18]; 11729 11730 u8 syndrome[0x20]; 11731 11732 u8 reserved_at_40[0x18]; 11733 u8 num_sf_partitions[0x8]; 11734 11735 u8 reserved_at_60[0x20]; 11736 11737 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11738 }; 11739 11740 struct mlx5_ifc_query_sf_partitions_in_bits { 11741 u8 opcode[0x10]; 11742 u8 reserved_at_10[0x10]; 11743 11744 u8 reserved_at_20[0x10]; 11745 u8 op_mod[0x10]; 11746 11747 u8 reserved_at_40[0x40]; 11748 }; 11749 11750 struct mlx5_ifc_dealloc_sf_out_bits { 11751 u8 status[0x8]; 11752 u8 reserved_at_8[0x18]; 11753 11754 u8 syndrome[0x20]; 11755 11756 u8 reserved_at_40[0x40]; 11757 }; 11758 11759 struct mlx5_ifc_dealloc_sf_in_bits { 11760 u8 opcode[0x10]; 11761 u8 reserved_at_10[0x10]; 11762 11763 u8 reserved_at_20[0x10]; 11764 u8 op_mod[0x10]; 11765 11766 u8 reserved_at_40[0x10]; 11767 u8 function_id[0x10]; 11768 11769 u8 reserved_at_60[0x20]; 11770 }; 11771 11772 struct mlx5_ifc_alloc_sf_out_bits { 11773 u8 status[0x8]; 11774 u8 reserved_at_8[0x18]; 11775 11776 u8 syndrome[0x20]; 11777 11778 u8 reserved_at_40[0x40]; 11779 }; 11780 11781 struct mlx5_ifc_alloc_sf_in_bits { 11782 u8 opcode[0x10]; 11783 u8 reserved_at_10[0x10]; 11784 11785 u8 reserved_at_20[0x10]; 11786 u8 op_mod[0x10]; 11787 11788 u8 reserved_at_40[0x10]; 11789 u8 function_id[0x10]; 11790 11791 u8 reserved_at_60[0x20]; 11792 }; 11793 11794 struct mlx5_ifc_affiliated_event_header_bits { 11795 u8 reserved_at_0[0x10]; 11796 u8 obj_type[0x10]; 11797 11798 u8 obj_id[0x20]; 11799 }; 11800 11801 enum { 11802 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11803 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11804 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11805 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11806 }; 11807 11808 enum { 11809 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11810 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11811 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11812 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11813 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11814 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11815 }; 11816 11817 enum { 11818 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11819 }; 11820 11821 enum { 11822 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11823 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11824 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11825 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11826 }; 11827 11828 enum { 11829 MLX5_IPSEC_ASO_MODE = 0x0, 11830 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11831 MLX5_IPSEC_ASO_INC_SN = 0x2, 11832 }; 11833 11834 struct mlx5_ifc_ipsec_aso_bits { 11835 u8 valid[0x1]; 11836 u8 reserved_at_201[0x1]; 11837 u8 mode[0x2]; 11838 u8 window_sz[0x2]; 11839 u8 soft_lft_arm[0x1]; 11840 u8 hard_lft_arm[0x1]; 11841 u8 remove_flow_enable[0x1]; 11842 u8 esn_event_arm[0x1]; 11843 u8 reserved_at_20a[0x16]; 11844 11845 u8 remove_flow_pkt_cnt[0x20]; 11846 11847 u8 remove_flow_soft_lft[0x20]; 11848 11849 u8 reserved_at_260[0x80]; 11850 11851 u8 mode_parameter[0x20]; 11852 11853 u8 replay_protection_window[0x100]; 11854 }; 11855 11856 struct mlx5_ifc_ipsec_obj_bits { 11857 u8 modify_field_select[0x40]; 11858 u8 full_offload[0x1]; 11859 u8 reserved_at_41[0x1]; 11860 u8 esn_en[0x1]; 11861 u8 esn_overlap[0x1]; 11862 u8 reserved_at_44[0x2]; 11863 u8 icv_length[0x2]; 11864 u8 reserved_at_48[0x4]; 11865 u8 aso_return_reg[0x4]; 11866 u8 reserved_at_50[0x10]; 11867 11868 u8 esn_msb[0x20]; 11869 11870 u8 reserved_at_80[0x8]; 11871 u8 dekn[0x18]; 11872 11873 u8 salt[0x20]; 11874 11875 u8 implicit_iv[0x40]; 11876 11877 u8 reserved_at_100[0x8]; 11878 u8 ipsec_aso_access_pd[0x18]; 11879 u8 reserved_at_120[0xe0]; 11880 11881 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11882 }; 11883 11884 struct mlx5_ifc_create_ipsec_obj_in_bits { 11885 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11886 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11887 }; 11888 11889 enum { 11890 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11891 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11892 }; 11893 11894 struct mlx5_ifc_query_ipsec_obj_out_bits { 11895 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11896 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11897 }; 11898 11899 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11900 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11901 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11902 }; 11903 11904 enum { 11905 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11906 }; 11907 11908 enum { 11909 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11910 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11911 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11912 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11913 }; 11914 11915 #define MLX5_MACSEC_ASO_INC_SN 0x2 11916 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11917 11918 struct mlx5_ifc_macsec_aso_bits { 11919 u8 valid[0x1]; 11920 u8 reserved_at_1[0x1]; 11921 u8 mode[0x2]; 11922 u8 window_size[0x2]; 11923 u8 soft_lifetime_arm[0x1]; 11924 u8 hard_lifetime_arm[0x1]; 11925 u8 remove_flow_enable[0x1]; 11926 u8 epn_event_arm[0x1]; 11927 u8 reserved_at_a[0x16]; 11928 11929 u8 remove_flow_packet_count[0x20]; 11930 11931 u8 remove_flow_soft_lifetime[0x20]; 11932 11933 u8 reserved_at_60[0x80]; 11934 11935 u8 mode_parameter[0x20]; 11936 11937 u8 replay_protection_window[8][0x20]; 11938 }; 11939 11940 struct mlx5_ifc_macsec_offload_obj_bits { 11941 u8 modify_field_select[0x40]; 11942 11943 u8 confidentiality_en[0x1]; 11944 u8 reserved_at_41[0x1]; 11945 u8 epn_en[0x1]; 11946 u8 epn_overlap[0x1]; 11947 u8 reserved_at_44[0x2]; 11948 u8 confidentiality_offset[0x2]; 11949 u8 reserved_at_48[0x4]; 11950 u8 aso_return_reg[0x4]; 11951 u8 reserved_at_50[0x10]; 11952 11953 u8 epn_msb[0x20]; 11954 11955 u8 reserved_at_80[0x8]; 11956 u8 dekn[0x18]; 11957 11958 u8 reserved_at_a0[0x20]; 11959 11960 u8 sci[0x40]; 11961 11962 u8 reserved_at_100[0x8]; 11963 u8 macsec_aso_access_pd[0x18]; 11964 11965 u8 reserved_at_120[0x60]; 11966 11967 u8 salt[3][0x20]; 11968 11969 u8 reserved_at_1e0[0x20]; 11970 11971 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11972 }; 11973 11974 struct mlx5_ifc_create_macsec_obj_in_bits { 11975 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11976 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11977 }; 11978 11979 struct mlx5_ifc_modify_macsec_obj_in_bits { 11980 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11981 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11982 }; 11983 11984 enum { 11985 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11986 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11987 }; 11988 11989 struct mlx5_ifc_query_macsec_obj_out_bits { 11990 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11991 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11992 }; 11993 11994 struct mlx5_ifc_wrapped_dek_bits { 11995 u8 gcm_iv[0x60]; 11996 11997 u8 reserved_at_60[0x20]; 11998 11999 u8 const0[0x1]; 12000 u8 key_size[0x1]; 12001 u8 reserved_at_82[0x2]; 12002 u8 key2_invalid[0x1]; 12003 u8 reserved_at_85[0x3]; 12004 u8 pd[0x18]; 12005 12006 u8 key_purpose[0x5]; 12007 u8 reserved_at_a5[0x13]; 12008 u8 kek_id[0x8]; 12009 12010 u8 reserved_at_c0[0x40]; 12011 12012 u8 key1[0x8][0x20]; 12013 12014 u8 key2[0x8][0x20]; 12015 12016 u8 reserved_at_300[0x40]; 12017 12018 u8 const1[0x1]; 12019 u8 reserved_at_341[0x1f]; 12020 12021 u8 reserved_at_360[0x20]; 12022 12023 u8 auth_tag[0x80]; 12024 }; 12025 12026 struct mlx5_ifc_encryption_key_obj_bits { 12027 u8 modify_field_select[0x40]; 12028 12029 u8 state[0x8]; 12030 u8 sw_wrapped[0x1]; 12031 u8 reserved_at_49[0xb]; 12032 u8 key_size[0x4]; 12033 u8 reserved_at_58[0x4]; 12034 u8 key_purpose[0x4]; 12035 12036 u8 reserved_at_60[0x8]; 12037 u8 pd[0x18]; 12038 12039 u8 reserved_at_80[0x100]; 12040 12041 u8 opaque[0x40]; 12042 12043 u8 reserved_at_1c0[0x40]; 12044 12045 u8 key[8][0x80]; 12046 12047 u8 sw_wrapped_dek[8][0x80]; 12048 12049 u8 reserved_at_a00[0x600]; 12050 }; 12051 12052 struct mlx5_ifc_create_encryption_key_in_bits { 12053 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12054 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12055 }; 12056 12057 struct mlx5_ifc_modify_encryption_key_in_bits { 12058 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12059 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12060 }; 12061 12062 enum { 12063 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12064 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12065 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12066 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12067 }; 12068 12069 struct mlx5_ifc_flow_meter_parameters_bits { 12070 u8 valid[0x1]; 12071 u8 bucket_overflow[0x1]; 12072 u8 start_color[0x2]; 12073 u8 both_buckets_on_green[0x1]; 12074 u8 reserved_at_5[0x1]; 12075 u8 meter_mode[0x2]; 12076 u8 reserved_at_8[0x18]; 12077 12078 u8 reserved_at_20[0x20]; 12079 12080 u8 reserved_at_40[0x3]; 12081 u8 cbs_exponent[0x5]; 12082 u8 cbs_mantissa[0x8]; 12083 u8 reserved_at_50[0x3]; 12084 u8 cir_exponent[0x5]; 12085 u8 cir_mantissa[0x8]; 12086 12087 u8 reserved_at_60[0x20]; 12088 12089 u8 reserved_at_80[0x3]; 12090 u8 ebs_exponent[0x5]; 12091 u8 ebs_mantissa[0x8]; 12092 u8 reserved_at_90[0x3]; 12093 u8 eir_exponent[0x5]; 12094 u8 eir_mantissa[0x8]; 12095 12096 u8 reserved_at_a0[0x60]; 12097 }; 12098 12099 struct mlx5_ifc_flow_meter_aso_obj_bits { 12100 u8 modify_field_select[0x40]; 12101 12102 u8 reserved_at_40[0x40]; 12103 12104 u8 reserved_at_80[0x8]; 12105 u8 meter_aso_access_pd[0x18]; 12106 12107 u8 reserved_at_a0[0x160]; 12108 12109 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12110 }; 12111 12112 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12113 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12114 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12115 }; 12116 12117 struct mlx5_ifc_int_kek_obj_bits { 12118 u8 modify_field_select[0x40]; 12119 12120 u8 state[0x8]; 12121 u8 auto_gen[0x1]; 12122 u8 reserved_at_49[0xb]; 12123 u8 key_size[0x4]; 12124 u8 reserved_at_58[0x8]; 12125 12126 u8 reserved_at_60[0x8]; 12127 u8 pd[0x18]; 12128 12129 u8 reserved_at_80[0x180]; 12130 u8 key[8][0x80]; 12131 12132 u8 reserved_at_600[0x200]; 12133 }; 12134 12135 struct mlx5_ifc_create_int_kek_obj_in_bits { 12136 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12137 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12138 }; 12139 12140 struct mlx5_ifc_create_int_kek_obj_out_bits { 12141 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12142 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12143 }; 12144 12145 struct mlx5_ifc_sampler_obj_bits { 12146 u8 modify_field_select[0x40]; 12147 12148 u8 table_type[0x8]; 12149 u8 level[0x8]; 12150 u8 reserved_at_50[0xf]; 12151 u8 ignore_flow_level[0x1]; 12152 12153 u8 sample_ratio[0x20]; 12154 12155 u8 reserved_at_80[0x8]; 12156 u8 sample_table_id[0x18]; 12157 12158 u8 reserved_at_a0[0x8]; 12159 u8 default_table_id[0x18]; 12160 12161 u8 sw_steering_icm_address_rx[0x40]; 12162 u8 sw_steering_icm_address_tx[0x40]; 12163 12164 u8 reserved_at_140[0xa0]; 12165 }; 12166 12167 struct mlx5_ifc_create_sampler_obj_in_bits { 12168 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12169 struct mlx5_ifc_sampler_obj_bits sampler_object; 12170 }; 12171 12172 struct mlx5_ifc_query_sampler_obj_out_bits { 12173 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12174 struct mlx5_ifc_sampler_obj_bits sampler_object; 12175 }; 12176 12177 enum { 12178 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12179 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12180 }; 12181 12182 enum { 12183 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12184 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12185 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12186 }; 12187 12188 struct mlx5_ifc_tls_static_params_bits { 12189 u8 const_2[0x2]; 12190 u8 tls_version[0x4]; 12191 u8 const_1[0x2]; 12192 u8 reserved_at_8[0x14]; 12193 u8 encryption_standard[0x4]; 12194 12195 u8 reserved_at_20[0x20]; 12196 12197 u8 initial_record_number[0x40]; 12198 12199 u8 resync_tcp_sn[0x20]; 12200 12201 u8 gcm_iv[0x20]; 12202 12203 u8 implicit_iv[0x40]; 12204 12205 u8 reserved_at_100[0x8]; 12206 u8 dek_index[0x18]; 12207 12208 u8 reserved_at_120[0xe0]; 12209 }; 12210 12211 struct mlx5_ifc_tls_progress_params_bits { 12212 u8 next_record_tcp_sn[0x20]; 12213 12214 u8 hw_resync_tcp_sn[0x20]; 12215 12216 u8 record_tracker_state[0x2]; 12217 u8 auth_state[0x2]; 12218 u8 reserved_at_44[0x4]; 12219 u8 hw_offset_record_number[0x18]; 12220 }; 12221 12222 enum { 12223 MLX5_MTT_PERM_READ = 1 << 0, 12224 MLX5_MTT_PERM_WRITE = 1 << 1, 12225 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12226 }; 12227 12228 enum { 12229 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12230 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12231 }; 12232 12233 struct mlx5_ifc_suspend_vhca_in_bits { 12234 u8 opcode[0x10]; 12235 u8 uid[0x10]; 12236 12237 u8 reserved_at_20[0x10]; 12238 u8 op_mod[0x10]; 12239 12240 u8 reserved_at_40[0x10]; 12241 u8 vhca_id[0x10]; 12242 12243 u8 reserved_at_60[0x20]; 12244 }; 12245 12246 struct mlx5_ifc_suspend_vhca_out_bits { 12247 u8 status[0x8]; 12248 u8 reserved_at_8[0x18]; 12249 12250 u8 syndrome[0x20]; 12251 12252 u8 reserved_at_40[0x40]; 12253 }; 12254 12255 enum { 12256 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12257 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12258 }; 12259 12260 struct mlx5_ifc_resume_vhca_in_bits { 12261 u8 opcode[0x10]; 12262 u8 uid[0x10]; 12263 12264 u8 reserved_at_20[0x10]; 12265 u8 op_mod[0x10]; 12266 12267 u8 reserved_at_40[0x10]; 12268 u8 vhca_id[0x10]; 12269 12270 u8 reserved_at_60[0x20]; 12271 }; 12272 12273 struct mlx5_ifc_resume_vhca_out_bits { 12274 u8 status[0x8]; 12275 u8 reserved_at_8[0x18]; 12276 12277 u8 syndrome[0x20]; 12278 12279 u8 reserved_at_40[0x40]; 12280 }; 12281 12282 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12283 u8 opcode[0x10]; 12284 u8 uid[0x10]; 12285 12286 u8 reserved_at_20[0x10]; 12287 u8 op_mod[0x10]; 12288 12289 u8 incremental[0x1]; 12290 u8 reserved_at_41[0xf]; 12291 u8 vhca_id[0x10]; 12292 12293 u8 reserved_at_60[0x20]; 12294 }; 12295 12296 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12297 u8 status[0x8]; 12298 u8 reserved_at_8[0x18]; 12299 12300 u8 syndrome[0x20]; 12301 12302 u8 reserved_at_40[0x40]; 12303 12304 u8 required_umem_size[0x20]; 12305 12306 u8 reserved_at_a0[0x160]; 12307 }; 12308 12309 struct mlx5_ifc_save_vhca_state_in_bits { 12310 u8 opcode[0x10]; 12311 u8 uid[0x10]; 12312 12313 u8 reserved_at_20[0x10]; 12314 u8 op_mod[0x10]; 12315 12316 u8 incremental[0x1]; 12317 u8 set_track[0x1]; 12318 u8 reserved_at_42[0xe]; 12319 u8 vhca_id[0x10]; 12320 12321 u8 reserved_at_60[0x20]; 12322 12323 u8 va[0x40]; 12324 12325 u8 mkey[0x20]; 12326 12327 u8 size[0x20]; 12328 }; 12329 12330 struct mlx5_ifc_save_vhca_state_out_bits { 12331 u8 status[0x8]; 12332 u8 reserved_at_8[0x18]; 12333 12334 u8 syndrome[0x20]; 12335 12336 u8 actual_image_size[0x20]; 12337 12338 u8 reserved_at_60[0x20]; 12339 }; 12340 12341 struct mlx5_ifc_load_vhca_state_in_bits { 12342 u8 opcode[0x10]; 12343 u8 uid[0x10]; 12344 12345 u8 reserved_at_20[0x10]; 12346 u8 op_mod[0x10]; 12347 12348 u8 reserved_at_40[0x10]; 12349 u8 vhca_id[0x10]; 12350 12351 u8 reserved_at_60[0x20]; 12352 12353 u8 va[0x40]; 12354 12355 u8 mkey[0x20]; 12356 12357 u8 size[0x20]; 12358 }; 12359 12360 struct mlx5_ifc_load_vhca_state_out_bits { 12361 u8 status[0x8]; 12362 u8 reserved_at_8[0x18]; 12363 12364 u8 syndrome[0x20]; 12365 12366 u8 reserved_at_40[0x40]; 12367 }; 12368 12369 struct mlx5_ifc_adv_virtualization_cap_bits { 12370 u8 reserved_at_0[0x3]; 12371 u8 pg_track_log_max_num[0x5]; 12372 u8 pg_track_max_num_range[0x8]; 12373 u8 pg_track_log_min_addr_space[0x8]; 12374 u8 pg_track_log_max_addr_space[0x8]; 12375 12376 u8 reserved_at_20[0x3]; 12377 u8 pg_track_log_min_msg_size[0x5]; 12378 u8 reserved_at_28[0x3]; 12379 u8 pg_track_log_max_msg_size[0x5]; 12380 u8 reserved_at_30[0x3]; 12381 u8 pg_track_log_min_page_size[0x5]; 12382 u8 reserved_at_38[0x3]; 12383 u8 pg_track_log_max_page_size[0x5]; 12384 12385 u8 reserved_at_40[0x7c0]; 12386 }; 12387 12388 struct mlx5_ifc_page_track_report_entry_bits { 12389 u8 dirty_address_high[0x20]; 12390 12391 u8 dirty_address_low[0x20]; 12392 }; 12393 12394 enum { 12395 MLX5_PAGE_TRACK_STATE_TRACKING, 12396 MLX5_PAGE_TRACK_STATE_REPORTING, 12397 MLX5_PAGE_TRACK_STATE_ERROR, 12398 }; 12399 12400 struct mlx5_ifc_page_track_range_bits { 12401 u8 start_address[0x40]; 12402 12403 u8 length[0x40]; 12404 }; 12405 12406 struct mlx5_ifc_page_track_bits { 12407 u8 modify_field_select[0x40]; 12408 12409 u8 reserved_at_40[0x10]; 12410 u8 vhca_id[0x10]; 12411 12412 u8 reserved_at_60[0x20]; 12413 12414 u8 state[0x4]; 12415 u8 track_type[0x4]; 12416 u8 log_addr_space_size[0x8]; 12417 u8 reserved_at_90[0x3]; 12418 u8 log_page_size[0x5]; 12419 u8 reserved_at_98[0x3]; 12420 u8 log_msg_size[0x5]; 12421 12422 u8 reserved_at_a0[0x8]; 12423 u8 reporting_qpn[0x18]; 12424 12425 u8 reserved_at_c0[0x18]; 12426 u8 num_ranges[0x8]; 12427 12428 u8 reserved_at_e0[0x20]; 12429 12430 u8 range_start_address[0x40]; 12431 12432 u8 length[0x40]; 12433 12434 struct mlx5_ifc_page_track_range_bits track_range[0]; 12435 }; 12436 12437 struct mlx5_ifc_create_page_track_obj_in_bits { 12438 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12439 struct mlx5_ifc_page_track_bits obj_context; 12440 }; 12441 12442 struct mlx5_ifc_modify_page_track_obj_in_bits { 12443 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12444 struct mlx5_ifc_page_track_bits obj_context; 12445 }; 12446 12447 #endif /* MLX5_IFC_H */ 12448