1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 85 }; 86 87 enum { 88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 90 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_MKEY = 0xff01, 96 MLX5_OBJ_TYPE_QP = 0xff02, 97 MLX5_OBJ_TYPE_PSV = 0xff03, 98 MLX5_OBJ_TYPE_RMP = 0xff04, 99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 100 MLX5_OBJ_TYPE_RQ = 0xff06, 101 MLX5_OBJ_TYPE_SQ = 0xff07, 102 MLX5_OBJ_TYPE_TIR = 0xff08, 103 MLX5_OBJ_TYPE_TIS = 0xff09, 104 MLX5_OBJ_TYPE_DCT = 0xff0a, 105 MLX5_OBJ_TYPE_XRQ = 0xff0b, 106 MLX5_OBJ_TYPE_RQT = 0xff0e, 107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 108 MLX5_OBJ_TYPE_CQ = 0xff10, 109 }; 110 111 enum { 112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 114 MLX5_CMD_OP_INIT_HCA = 0x102, 115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 116 MLX5_CMD_OP_ENABLE_HCA = 0x104, 117 MLX5_CMD_OP_DISABLE_HCA = 0x105, 118 MLX5_CMD_OP_QUERY_PAGES = 0x107, 119 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 120 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 121 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 122 MLX5_CMD_OP_SET_ISSI = 0x10b, 123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 125 MLX5_CMD_OP_ALLOC_SF = 0x113, 126 MLX5_CMD_OP_DEALLOC_SF = 0x114, 127 MLX5_CMD_OP_CREATE_MKEY = 0x200, 128 MLX5_CMD_OP_QUERY_MKEY = 0x201, 129 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 130 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 131 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 132 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 133 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 134 MLX5_CMD_OP_CREATE_EQ = 0x301, 135 MLX5_CMD_OP_DESTROY_EQ = 0x302, 136 MLX5_CMD_OP_QUERY_EQ = 0x303, 137 MLX5_CMD_OP_GEN_EQE = 0x304, 138 MLX5_CMD_OP_CREATE_CQ = 0x400, 139 MLX5_CMD_OP_DESTROY_CQ = 0x401, 140 MLX5_CMD_OP_QUERY_CQ = 0x402, 141 MLX5_CMD_OP_MODIFY_CQ = 0x403, 142 MLX5_CMD_OP_CREATE_QP = 0x500, 143 MLX5_CMD_OP_DESTROY_QP = 0x501, 144 MLX5_CMD_OP_RST2INIT_QP = 0x502, 145 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 146 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 147 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 148 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 149 MLX5_CMD_OP_2ERR_QP = 0x507, 150 MLX5_CMD_OP_2RST_QP = 0x50a, 151 MLX5_CMD_OP_QUERY_QP = 0x50b, 152 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 153 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 154 MLX5_CMD_OP_CREATE_PSV = 0x600, 155 MLX5_CMD_OP_DESTROY_PSV = 0x601, 156 MLX5_CMD_OP_CREATE_SRQ = 0x700, 157 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 158 MLX5_CMD_OP_QUERY_SRQ = 0x702, 159 MLX5_CMD_OP_ARM_RQ = 0x703, 160 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 161 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 162 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 163 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 164 MLX5_CMD_OP_CREATE_DCT = 0x710, 165 MLX5_CMD_OP_DESTROY_DCT = 0x711, 166 MLX5_CMD_OP_DRAIN_DCT = 0x712, 167 MLX5_CMD_OP_QUERY_DCT = 0x713, 168 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 169 MLX5_CMD_OP_CREATE_XRQ = 0x717, 170 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 171 MLX5_CMD_OP_QUERY_XRQ = 0x719, 172 MLX5_CMD_OP_ARM_XRQ = 0x71a, 173 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 174 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 175 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 176 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 177 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 178 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 179 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 180 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 181 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 182 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 183 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 184 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 185 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 186 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 187 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 188 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 191 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 192 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 193 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 194 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 195 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 196 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 197 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 198 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 199 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 200 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 201 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 202 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 203 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 204 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 205 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 206 MLX5_CMD_OP_ALLOC_PD = 0x800, 207 MLX5_CMD_OP_DEALLOC_PD = 0x801, 208 MLX5_CMD_OP_ALLOC_UAR = 0x802, 209 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 210 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 211 MLX5_CMD_OP_ACCESS_REG = 0x805, 212 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 213 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 214 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 215 MLX5_CMD_OP_MAD_IFC = 0x50d, 216 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 217 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 218 MLX5_CMD_OP_NOP = 0x80d, 219 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 220 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 221 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 222 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 223 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 224 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 225 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 226 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 227 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 228 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 229 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 230 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 231 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 232 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 233 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 234 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 235 MLX5_CMD_OP_CREATE_LAG = 0x840, 236 MLX5_CMD_OP_MODIFY_LAG = 0x841, 237 MLX5_CMD_OP_QUERY_LAG = 0x842, 238 MLX5_CMD_OP_DESTROY_LAG = 0x843, 239 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 240 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 241 MLX5_CMD_OP_CREATE_TIR = 0x900, 242 MLX5_CMD_OP_MODIFY_TIR = 0x901, 243 MLX5_CMD_OP_DESTROY_TIR = 0x902, 244 MLX5_CMD_OP_QUERY_TIR = 0x903, 245 MLX5_CMD_OP_CREATE_SQ = 0x904, 246 MLX5_CMD_OP_MODIFY_SQ = 0x905, 247 MLX5_CMD_OP_DESTROY_SQ = 0x906, 248 MLX5_CMD_OP_QUERY_SQ = 0x907, 249 MLX5_CMD_OP_CREATE_RQ = 0x908, 250 MLX5_CMD_OP_MODIFY_RQ = 0x909, 251 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 252 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 253 MLX5_CMD_OP_QUERY_RQ = 0x90b, 254 MLX5_CMD_OP_CREATE_RMP = 0x90c, 255 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 256 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 257 MLX5_CMD_OP_QUERY_RMP = 0x90f, 258 MLX5_CMD_OP_CREATE_TIS = 0x912, 259 MLX5_CMD_OP_MODIFY_TIS = 0x913, 260 MLX5_CMD_OP_DESTROY_TIS = 0x914, 261 MLX5_CMD_OP_QUERY_TIS = 0x915, 262 MLX5_CMD_OP_CREATE_RQT = 0x916, 263 MLX5_CMD_OP_MODIFY_RQT = 0x917, 264 MLX5_CMD_OP_DESTROY_RQT = 0x918, 265 MLX5_CMD_OP_QUERY_RQT = 0x919, 266 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 267 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 268 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 269 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 270 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 271 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 272 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 274 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 275 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 276 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 277 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 278 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 279 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 280 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 281 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 282 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 283 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 284 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 285 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 286 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 287 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 288 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 289 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 290 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 291 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 292 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 293 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 294 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 295 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 296 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 297 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 298 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 299 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 300 MLX5_CMD_OP_MAX 301 }; 302 303 /* Valid range for general commands that don't work over an object */ 304 enum { 305 MLX5_CMD_OP_GENERAL_START = 0xb00, 306 MLX5_CMD_OP_GENERAL_END = 0xd00, 307 }; 308 309 struct mlx5_ifc_flow_table_fields_supported_bits { 310 u8 outer_dmac[0x1]; 311 u8 outer_smac[0x1]; 312 u8 outer_ether_type[0x1]; 313 u8 outer_ip_version[0x1]; 314 u8 outer_first_prio[0x1]; 315 u8 outer_first_cfi[0x1]; 316 u8 outer_first_vid[0x1]; 317 u8 outer_ipv4_ttl[0x1]; 318 u8 outer_second_prio[0x1]; 319 u8 outer_second_cfi[0x1]; 320 u8 outer_second_vid[0x1]; 321 u8 reserved_at_b[0x1]; 322 u8 outer_sip[0x1]; 323 u8 outer_dip[0x1]; 324 u8 outer_frag[0x1]; 325 u8 outer_ip_protocol[0x1]; 326 u8 outer_ip_ecn[0x1]; 327 u8 outer_ip_dscp[0x1]; 328 u8 outer_udp_sport[0x1]; 329 u8 outer_udp_dport[0x1]; 330 u8 outer_tcp_sport[0x1]; 331 u8 outer_tcp_dport[0x1]; 332 u8 outer_tcp_flags[0x1]; 333 u8 outer_gre_protocol[0x1]; 334 u8 outer_gre_key[0x1]; 335 u8 outer_vxlan_vni[0x1]; 336 u8 outer_geneve_vni[0x1]; 337 u8 outer_geneve_oam[0x1]; 338 u8 outer_geneve_protocol_type[0x1]; 339 u8 outer_geneve_opt_len[0x1]; 340 u8 reserved_at_1e[0x1]; 341 u8 source_eswitch_port[0x1]; 342 343 u8 inner_dmac[0x1]; 344 u8 inner_smac[0x1]; 345 u8 inner_ether_type[0x1]; 346 u8 inner_ip_version[0x1]; 347 u8 inner_first_prio[0x1]; 348 u8 inner_first_cfi[0x1]; 349 u8 inner_first_vid[0x1]; 350 u8 reserved_at_27[0x1]; 351 u8 inner_second_prio[0x1]; 352 u8 inner_second_cfi[0x1]; 353 u8 inner_second_vid[0x1]; 354 u8 reserved_at_2b[0x1]; 355 u8 inner_sip[0x1]; 356 u8 inner_dip[0x1]; 357 u8 inner_frag[0x1]; 358 u8 inner_ip_protocol[0x1]; 359 u8 inner_ip_ecn[0x1]; 360 u8 inner_ip_dscp[0x1]; 361 u8 inner_udp_sport[0x1]; 362 u8 inner_udp_dport[0x1]; 363 u8 inner_tcp_sport[0x1]; 364 u8 inner_tcp_dport[0x1]; 365 u8 inner_tcp_flags[0x1]; 366 u8 reserved_at_37[0x9]; 367 368 u8 geneve_tlv_option_0_data[0x1]; 369 u8 reserved_at_41[0x4]; 370 u8 outer_first_mpls_over_udp[0x4]; 371 u8 outer_first_mpls_over_gre[0x4]; 372 u8 inner_first_mpls[0x4]; 373 u8 outer_first_mpls[0x4]; 374 u8 reserved_at_55[0x2]; 375 u8 outer_esp_spi[0x1]; 376 u8 reserved_at_58[0x2]; 377 u8 bth_dst_qp[0x1]; 378 u8 reserved_at_5b[0x5]; 379 380 u8 reserved_at_60[0x18]; 381 u8 metadata_reg_c_7[0x1]; 382 u8 metadata_reg_c_6[0x1]; 383 u8 metadata_reg_c_5[0x1]; 384 u8 metadata_reg_c_4[0x1]; 385 u8 metadata_reg_c_3[0x1]; 386 u8 metadata_reg_c_2[0x1]; 387 u8 metadata_reg_c_1[0x1]; 388 u8 metadata_reg_c_0[0x1]; 389 }; 390 391 struct mlx5_ifc_flow_table_prop_layout_bits { 392 u8 ft_support[0x1]; 393 u8 reserved_at_1[0x1]; 394 u8 flow_counter[0x1]; 395 u8 flow_modify_en[0x1]; 396 u8 modify_root[0x1]; 397 u8 identified_miss_table_mode[0x1]; 398 u8 flow_table_modify[0x1]; 399 u8 reformat[0x1]; 400 u8 decap[0x1]; 401 u8 reserved_at_9[0x1]; 402 u8 pop_vlan[0x1]; 403 u8 push_vlan[0x1]; 404 u8 reserved_at_c[0x1]; 405 u8 pop_vlan_2[0x1]; 406 u8 push_vlan_2[0x1]; 407 u8 reformat_and_vlan_action[0x1]; 408 u8 reserved_at_10[0x1]; 409 u8 sw_owner[0x1]; 410 u8 reformat_l3_tunnel_to_l2[0x1]; 411 u8 reformat_l2_to_l3_tunnel[0x1]; 412 u8 reformat_and_modify_action[0x1]; 413 u8 ignore_flow_level[0x1]; 414 u8 reserved_at_16[0x1]; 415 u8 table_miss_action_domain[0x1]; 416 u8 termination_table[0x1]; 417 u8 reserved_at_19[0x7]; 418 u8 reserved_at_20[0x2]; 419 u8 log_max_ft_size[0x6]; 420 u8 log_max_modify_header_context[0x8]; 421 u8 max_modify_header_actions[0x8]; 422 u8 max_ft_level[0x8]; 423 424 u8 reserved_at_40[0x20]; 425 426 u8 reserved_at_60[0x18]; 427 u8 log_max_ft_num[0x8]; 428 429 u8 reserved_at_80[0x18]; 430 u8 log_max_destination[0x8]; 431 432 u8 log_max_flow_counter[0x8]; 433 u8 reserved_at_a8[0x10]; 434 u8 log_max_flow[0x8]; 435 436 u8 reserved_at_c0[0x40]; 437 438 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 439 440 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 441 }; 442 443 struct mlx5_ifc_odp_per_transport_service_cap_bits { 444 u8 send[0x1]; 445 u8 receive[0x1]; 446 u8 write[0x1]; 447 u8 read[0x1]; 448 u8 atomic[0x1]; 449 u8 srq_receive[0x1]; 450 u8 reserved_at_6[0x1a]; 451 }; 452 453 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 454 u8 smac_47_16[0x20]; 455 456 u8 smac_15_0[0x10]; 457 u8 ethertype[0x10]; 458 459 u8 dmac_47_16[0x20]; 460 461 u8 dmac_15_0[0x10]; 462 u8 first_prio[0x3]; 463 u8 first_cfi[0x1]; 464 u8 first_vid[0xc]; 465 466 u8 ip_protocol[0x8]; 467 u8 ip_dscp[0x6]; 468 u8 ip_ecn[0x2]; 469 u8 cvlan_tag[0x1]; 470 u8 svlan_tag[0x1]; 471 u8 frag[0x1]; 472 u8 ip_version[0x4]; 473 u8 tcp_flags[0x9]; 474 475 u8 tcp_sport[0x10]; 476 u8 tcp_dport[0x10]; 477 478 u8 reserved_at_c0[0x18]; 479 u8 ttl_hoplimit[0x8]; 480 481 u8 udp_sport[0x10]; 482 u8 udp_dport[0x10]; 483 484 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 485 486 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 487 }; 488 489 struct mlx5_ifc_nvgre_key_bits { 490 u8 hi[0x18]; 491 u8 lo[0x8]; 492 }; 493 494 union mlx5_ifc_gre_key_bits { 495 struct mlx5_ifc_nvgre_key_bits nvgre; 496 u8 key[0x20]; 497 }; 498 499 struct mlx5_ifc_fte_match_set_misc_bits { 500 u8 gre_c_present[0x1]; 501 u8 reserved_at_1[0x1]; 502 u8 gre_k_present[0x1]; 503 u8 gre_s_present[0x1]; 504 u8 source_vhca_port[0x4]; 505 u8 source_sqn[0x18]; 506 507 u8 source_eswitch_owner_vhca_id[0x10]; 508 u8 source_port[0x10]; 509 510 u8 outer_second_prio[0x3]; 511 u8 outer_second_cfi[0x1]; 512 u8 outer_second_vid[0xc]; 513 u8 inner_second_prio[0x3]; 514 u8 inner_second_cfi[0x1]; 515 u8 inner_second_vid[0xc]; 516 517 u8 outer_second_cvlan_tag[0x1]; 518 u8 inner_second_cvlan_tag[0x1]; 519 u8 outer_second_svlan_tag[0x1]; 520 u8 inner_second_svlan_tag[0x1]; 521 u8 reserved_at_64[0xc]; 522 u8 gre_protocol[0x10]; 523 524 union mlx5_ifc_gre_key_bits gre_key; 525 526 u8 vxlan_vni[0x18]; 527 u8 reserved_at_b8[0x8]; 528 529 u8 geneve_vni[0x18]; 530 u8 reserved_at_d8[0x7]; 531 u8 geneve_oam[0x1]; 532 533 u8 reserved_at_e0[0xc]; 534 u8 outer_ipv6_flow_label[0x14]; 535 536 u8 reserved_at_100[0xc]; 537 u8 inner_ipv6_flow_label[0x14]; 538 539 u8 reserved_at_120[0xa]; 540 u8 geneve_opt_len[0x6]; 541 u8 geneve_protocol_type[0x10]; 542 543 u8 reserved_at_140[0x8]; 544 u8 bth_dst_qp[0x18]; 545 u8 reserved_at_160[0x20]; 546 u8 outer_esp_spi[0x20]; 547 u8 reserved_at_1a0[0x60]; 548 }; 549 550 struct mlx5_ifc_fte_match_mpls_bits { 551 u8 mpls_label[0x14]; 552 u8 mpls_exp[0x3]; 553 u8 mpls_s_bos[0x1]; 554 u8 mpls_ttl[0x8]; 555 }; 556 557 struct mlx5_ifc_fte_match_set_misc2_bits { 558 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 559 560 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 561 562 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 563 564 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 565 566 u8 metadata_reg_c_7[0x20]; 567 568 u8 metadata_reg_c_6[0x20]; 569 570 u8 metadata_reg_c_5[0x20]; 571 572 u8 metadata_reg_c_4[0x20]; 573 574 u8 metadata_reg_c_3[0x20]; 575 576 u8 metadata_reg_c_2[0x20]; 577 578 u8 metadata_reg_c_1[0x20]; 579 580 u8 metadata_reg_c_0[0x20]; 581 582 u8 metadata_reg_a[0x20]; 583 584 u8 metadata_reg_b[0x20]; 585 586 u8 reserved_at_1c0[0x40]; 587 }; 588 589 struct mlx5_ifc_fte_match_set_misc3_bits { 590 u8 inner_tcp_seq_num[0x20]; 591 592 u8 outer_tcp_seq_num[0x20]; 593 594 u8 inner_tcp_ack_num[0x20]; 595 596 u8 outer_tcp_ack_num[0x20]; 597 598 u8 reserved_at_80[0x8]; 599 u8 outer_vxlan_gpe_vni[0x18]; 600 601 u8 outer_vxlan_gpe_next_protocol[0x8]; 602 u8 outer_vxlan_gpe_flags[0x8]; 603 u8 reserved_at_b0[0x10]; 604 605 u8 icmp_header_data[0x20]; 606 607 u8 icmpv6_header_data[0x20]; 608 609 u8 icmp_type[0x8]; 610 u8 icmp_code[0x8]; 611 u8 icmpv6_type[0x8]; 612 u8 icmpv6_code[0x8]; 613 614 u8 geneve_tlv_option_0_data[0x20]; 615 616 u8 reserved_at_140[0xc0]; 617 }; 618 619 struct mlx5_ifc_cmd_pas_bits { 620 u8 pa_h[0x20]; 621 622 u8 pa_l[0x14]; 623 u8 reserved_at_34[0xc]; 624 }; 625 626 struct mlx5_ifc_uint64_bits { 627 u8 hi[0x20]; 628 629 u8 lo[0x20]; 630 }; 631 632 enum { 633 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 634 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 635 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 636 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 637 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 638 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 639 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 640 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 641 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 642 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 643 }; 644 645 struct mlx5_ifc_ads_bits { 646 u8 fl[0x1]; 647 u8 free_ar[0x1]; 648 u8 reserved_at_2[0xe]; 649 u8 pkey_index[0x10]; 650 651 u8 reserved_at_20[0x8]; 652 u8 grh[0x1]; 653 u8 mlid[0x7]; 654 u8 rlid[0x10]; 655 656 u8 ack_timeout[0x5]; 657 u8 reserved_at_45[0x3]; 658 u8 src_addr_index[0x8]; 659 u8 reserved_at_50[0x4]; 660 u8 stat_rate[0x4]; 661 u8 hop_limit[0x8]; 662 663 u8 reserved_at_60[0x4]; 664 u8 tclass[0x8]; 665 u8 flow_label[0x14]; 666 667 u8 rgid_rip[16][0x8]; 668 669 u8 reserved_at_100[0x4]; 670 u8 f_dscp[0x1]; 671 u8 f_ecn[0x1]; 672 u8 reserved_at_106[0x1]; 673 u8 f_eth_prio[0x1]; 674 u8 ecn[0x2]; 675 u8 dscp[0x6]; 676 u8 udp_sport[0x10]; 677 678 u8 dei_cfi[0x1]; 679 u8 eth_prio[0x3]; 680 u8 sl[0x4]; 681 u8 vhca_port_num[0x8]; 682 u8 rmac_47_32[0x10]; 683 684 u8 rmac_31_0[0x20]; 685 }; 686 687 struct mlx5_ifc_flow_table_nic_cap_bits { 688 u8 nic_rx_multi_path_tirs[0x1]; 689 u8 nic_rx_multi_path_tirs_fts[0x1]; 690 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 691 u8 reserved_at_3[0x1d]; 692 u8 encap_general_header[0x1]; 693 u8 reserved_at_21[0xa]; 694 u8 log_max_packet_reformat_context[0x5]; 695 u8 reserved_at_30[0x6]; 696 u8 max_encap_header_size[0xa]; 697 u8 reserved_at_40[0x1c0]; 698 699 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 700 701 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 702 703 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 704 705 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 706 707 u8 reserved_at_a00[0x200]; 708 709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 710 711 u8 reserved_at_e00[0x1200]; 712 713 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 714 715 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 716 717 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 718 719 u8 reserved_at_20c0[0x5f40]; 720 }; 721 722 enum { 723 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 724 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 725 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 726 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 727 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 728 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 729 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 730 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 731 }; 732 733 struct mlx5_ifc_flow_table_eswitch_cap_bits { 734 u8 fdb_to_vport_reg_c_id[0x8]; 735 u8 reserved_at_8[0xd]; 736 u8 fdb_modify_header_fwd_to_table[0x1]; 737 u8 reserved_at_16[0x1]; 738 u8 flow_source[0x1]; 739 u8 reserved_at_18[0x2]; 740 u8 multi_fdb_encap[0x1]; 741 u8 reserved_at_1b[0x1]; 742 u8 fdb_multi_path_to_table[0x1]; 743 u8 reserved_at_1d[0x3]; 744 745 u8 reserved_at_20[0x1e0]; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 752 753 u8 reserved_at_800[0x1000]; 754 755 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 756 757 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 758 759 u8 sw_steering_uplink_icm_address_rx[0x40]; 760 761 u8 sw_steering_uplink_icm_address_tx[0x40]; 762 763 u8 reserved_at_1900[0x6700]; 764 }; 765 766 enum { 767 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 768 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 769 }; 770 771 struct mlx5_ifc_e_switch_cap_bits { 772 u8 vport_svlan_strip[0x1]; 773 u8 vport_cvlan_strip[0x1]; 774 u8 vport_svlan_insert[0x1]; 775 u8 vport_cvlan_insert_if_not_exist[0x1]; 776 u8 vport_cvlan_insert_overwrite[0x1]; 777 u8 reserved_at_5[0x3]; 778 u8 esw_uplink_ingress_acl[0x1]; 779 u8 reserved_at_9[0x10]; 780 u8 esw_functions_changed[0x1]; 781 u8 reserved_at_1a[0x1]; 782 u8 ecpf_vport_exists[0x1]; 783 u8 counter_eswitch_affinity[0x1]; 784 u8 merged_eswitch[0x1]; 785 u8 nic_vport_node_guid_modify[0x1]; 786 u8 nic_vport_port_guid_modify[0x1]; 787 788 u8 vxlan_encap_decap[0x1]; 789 u8 nvgre_encap_decap[0x1]; 790 u8 reserved_at_22[0x1]; 791 u8 log_max_fdb_encap_uplink[0x5]; 792 u8 reserved_at_21[0x3]; 793 u8 log_max_packet_reformat_context[0x5]; 794 u8 reserved_2b[0x6]; 795 u8 max_encap_header_size[0xa]; 796 797 u8 reserved_at_40[0xb]; 798 u8 log_max_esw_sf[0x5]; 799 u8 esw_sf_base_id[0x10]; 800 801 u8 reserved_at_60[0x7a0]; 802 803 }; 804 805 struct mlx5_ifc_qos_cap_bits { 806 u8 packet_pacing[0x1]; 807 u8 esw_scheduling[0x1]; 808 u8 esw_bw_share[0x1]; 809 u8 esw_rate_limit[0x1]; 810 u8 reserved_at_4[0x1]; 811 u8 packet_pacing_burst_bound[0x1]; 812 u8 packet_pacing_typical_size[0x1]; 813 u8 reserved_at_7[0x19]; 814 815 u8 reserved_at_20[0x20]; 816 817 u8 packet_pacing_max_rate[0x20]; 818 819 u8 packet_pacing_min_rate[0x20]; 820 821 u8 reserved_at_80[0x10]; 822 u8 packet_pacing_rate_table_size[0x10]; 823 824 u8 esw_element_type[0x10]; 825 u8 esw_tsar_type[0x10]; 826 827 u8 reserved_at_c0[0x10]; 828 u8 max_qos_para_vport[0x10]; 829 830 u8 max_tsar_bw_share[0x20]; 831 832 u8 reserved_at_100[0x700]; 833 }; 834 835 struct mlx5_ifc_debug_cap_bits { 836 u8 core_dump_general[0x1]; 837 u8 core_dump_qp[0x1]; 838 u8 reserved_at_2[0x7]; 839 u8 resource_dump[0x1]; 840 u8 reserved_at_a[0x16]; 841 842 u8 reserved_at_20[0x2]; 843 u8 stall_detect[0x1]; 844 u8 reserved_at_23[0x1d]; 845 846 u8 reserved_at_40[0x7c0]; 847 }; 848 849 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 850 u8 csum_cap[0x1]; 851 u8 vlan_cap[0x1]; 852 u8 lro_cap[0x1]; 853 u8 lro_psh_flag[0x1]; 854 u8 lro_time_stamp[0x1]; 855 u8 reserved_at_5[0x2]; 856 u8 wqe_vlan_insert[0x1]; 857 u8 self_lb_en_modifiable[0x1]; 858 u8 reserved_at_9[0x2]; 859 u8 max_lso_cap[0x5]; 860 u8 multi_pkt_send_wqe[0x2]; 861 u8 wqe_inline_mode[0x2]; 862 u8 rss_ind_tbl_cap[0x4]; 863 u8 reg_umr_sq[0x1]; 864 u8 scatter_fcs[0x1]; 865 u8 enhanced_multi_pkt_send_wqe[0x1]; 866 u8 tunnel_lso_const_out_ip_id[0x1]; 867 u8 reserved_at_1c[0x2]; 868 u8 tunnel_stateless_gre[0x1]; 869 u8 tunnel_stateless_vxlan[0x1]; 870 871 u8 swp[0x1]; 872 u8 swp_csum[0x1]; 873 u8 swp_lso[0x1]; 874 u8 cqe_checksum_full[0x1]; 875 u8 reserved_at_24[0x5]; 876 u8 tunnel_stateless_ip_over_ip[0x1]; 877 u8 reserved_at_2a[0x6]; 878 u8 max_vxlan_udp_ports[0x8]; 879 u8 reserved_at_38[0x6]; 880 u8 max_geneve_opt_len[0x1]; 881 u8 tunnel_stateless_geneve_rx[0x1]; 882 883 u8 reserved_at_40[0x10]; 884 u8 lro_min_mss_size[0x10]; 885 886 u8 reserved_at_60[0x120]; 887 888 u8 lro_timer_supported_periods[4][0x20]; 889 890 u8 reserved_at_200[0x600]; 891 }; 892 893 struct mlx5_ifc_roce_cap_bits { 894 u8 roce_apm[0x1]; 895 u8 reserved_at_1[0x1f]; 896 897 u8 reserved_at_20[0x60]; 898 899 u8 reserved_at_80[0xc]; 900 u8 l3_type[0x4]; 901 u8 reserved_at_90[0x8]; 902 u8 roce_version[0x8]; 903 904 u8 reserved_at_a0[0x10]; 905 u8 r_roce_dest_udp_port[0x10]; 906 907 u8 r_roce_max_src_udp_port[0x10]; 908 u8 r_roce_min_src_udp_port[0x10]; 909 910 u8 reserved_at_e0[0x10]; 911 u8 roce_address_table_size[0x10]; 912 913 u8 reserved_at_100[0x700]; 914 }; 915 916 struct mlx5_ifc_sync_steering_in_bits { 917 u8 opcode[0x10]; 918 u8 uid[0x10]; 919 920 u8 reserved_at_20[0x10]; 921 u8 op_mod[0x10]; 922 923 u8 reserved_at_40[0xc0]; 924 }; 925 926 struct mlx5_ifc_sync_steering_out_bits { 927 u8 status[0x8]; 928 u8 reserved_at_8[0x18]; 929 930 u8 syndrome[0x20]; 931 932 u8 reserved_at_40[0x40]; 933 }; 934 935 struct mlx5_ifc_device_mem_cap_bits { 936 u8 memic[0x1]; 937 u8 reserved_at_1[0x1f]; 938 939 u8 reserved_at_20[0xb]; 940 u8 log_min_memic_alloc_size[0x5]; 941 u8 reserved_at_30[0x8]; 942 u8 log_max_memic_addr_alignment[0x8]; 943 944 u8 memic_bar_start_addr[0x40]; 945 946 u8 memic_bar_size[0x20]; 947 948 u8 max_memic_size[0x20]; 949 950 u8 steering_sw_icm_start_address[0x40]; 951 952 u8 reserved_at_100[0x8]; 953 u8 log_header_modify_sw_icm_size[0x8]; 954 u8 reserved_at_110[0x2]; 955 u8 log_sw_icm_alloc_granularity[0x6]; 956 u8 log_steering_sw_icm_size[0x8]; 957 958 u8 reserved_at_120[0x20]; 959 960 u8 header_modify_sw_icm_start_address[0x40]; 961 962 u8 reserved_at_180[0x680]; 963 }; 964 965 struct mlx5_ifc_device_event_cap_bits { 966 u8 user_affiliated_events[4][0x40]; 967 968 u8 user_unaffiliated_events[4][0x40]; 969 }; 970 971 struct mlx5_ifc_device_virtio_emulation_cap_bits { 972 u8 reserved_at_0[0x20]; 973 974 u8 reserved_at_20[0x13]; 975 u8 log_doorbell_stride[0x5]; 976 u8 reserved_at_38[0x3]; 977 u8 log_doorbell_bar_size[0x5]; 978 979 u8 doorbell_bar_offset[0x40]; 980 981 u8 reserved_at_80[0x780]; 982 }; 983 984 enum { 985 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 986 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 987 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 988 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 989 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 990 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 991 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 992 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 993 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 994 }; 995 996 enum { 997 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 998 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 999 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1000 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1001 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1006 }; 1007 1008 struct mlx5_ifc_atomic_caps_bits { 1009 u8 reserved_at_0[0x40]; 1010 1011 u8 atomic_req_8B_endianness_mode[0x2]; 1012 u8 reserved_at_42[0x4]; 1013 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1014 1015 u8 reserved_at_47[0x19]; 1016 1017 u8 reserved_at_60[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 atomic_operations[0x10]; 1021 1022 u8 reserved_at_a0[0x10]; 1023 u8 atomic_size_qp[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 atomic_size_dc[0x10]; 1027 1028 u8 reserved_at_e0[0x720]; 1029 }; 1030 1031 struct mlx5_ifc_odp_cap_bits { 1032 u8 reserved_at_0[0x40]; 1033 1034 u8 sig[0x1]; 1035 u8 reserved_at_41[0x1f]; 1036 1037 u8 reserved_at_60[0x20]; 1038 1039 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1040 1041 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1042 1043 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1044 1045 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1046 1047 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1048 1049 u8 reserved_at_120[0x6E0]; 1050 }; 1051 1052 struct mlx5_ifc_calc_op { 1053 u8 reserved_at_0[0x10]; 1054 u8 reserved_at_10[0x9]; 1055 u8 op_swap_endianness[0x1]; 1056 u8 op_min[0x1]; 1057 u8 op_xor[0x1]; 1058 u8 op_or[0x1]; 1059 u8 op_and[0x1]; 1060 u8 op_max[0x1]; 1061 u8 op_add[0x1]; 1062 }; 1063 1064 struct mlx5_ifc_vector_calc_cap_bits { 1065 u8 calc_matrix[0x1]; 1066 u8 reserved_at_1[0x1f]; 1067 u8 reserved_at_20[0x8]; 1068 u8 max_vec_count[0x8]; 1069 u8 reserved_at_30[0xd]; 1070 u8 max_chunk_size[0x3]; 1071 struct mlx5_ifc_calc_op calc0; 1072 struct mlx5_ifc_calc_op calc1; 1073 struct mlx5_ifc_calc_op calc2; 1074 struct mlx5_ifc_calc_op calc3; 1075 1076 u8 reserved_at_c0[0x720]; 1077 }; 1078 1079 struct mlx5_ifc_tls_cap_bits { 1080 u8 tls_1_2_aes_gcm_128[0x1]; 1081 u8 tls_1_3_aes_gcm_128[0x1]; 1082 u8 tls_1_2_aes_gcm_256[0x1]; 1083 u8 tls_1_3_aes_gcm_256[0x1]; 1084 u8 reserved_at_4[0x1c]; 1085 1086 u8 reserved_at_20[0x7e0]; 1087 }; 1088 1089 enum { 1090 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1091 MLX5_WQ_TYPE_CYCLIC = 0x1, 1092 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1093 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1094 }; 1095 1096 enum { 1097 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1098 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1099 }; 1100 1101 enum { 1102 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1103 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1104 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1105 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1106 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1107 }; 1108 1109 enum { 1110 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1111 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1112 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1113 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1114 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1115 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1116 }; 1117 1118 enum { 1119 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1120 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1121 }; 1122 1123 enum { 1124 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1125 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1126 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1127 }; 1128 1129 enum { 1130 MLX5_CAP_PORT_TYPE_IB = 0x0, 1131 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1132 }; 1133 1134 enum { 1135 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1136 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1137 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1138 }; 1139 1140 enum { 1141 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1142 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1143 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1144 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1145 }; 1146 1147 enum { 1148 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1149 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1150 }; 1151 1152 #define MLX5_FC_BULK_SIZE_FACTOR 128 1153 1154 enum mlx5_fc_bulk_alloc_bitmask { 1155 MLX5_FC_BULK_128 = (1 << 0), 1156 MLX5_FC_BULK_256 = (1 << 1), 1157 MLX5_FC_BULK_512 = (1 << 2), 1158 MLX5_FC_BULK_1024 = (1 << 3), 1159 MLX5_FC_BULK_2048 = (1 << 4), 1160 MLX5_FC_BULK_4096 = (1 << 5), 1161 MLX5_FC_BULK_8192 = (1 << 6), 1162 MLX5_FC_BULK_16384 = (1 << 7), 1163 }; 1164 1165 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1166 1167 struct mlx5_ifc_cmd_hca_cap_bits { 1168 u8 reserved_at_0[0x30]; 1169 u8 vhca_id[0x10]; 1170 1171 u8 reserved_at_40[0x40]; 1172 1173 u8 log_max_srq_sz[0x8]; 1174 u8 log_max_qp_sz[0x8]; 1175 u8 event_cap[0x1]; 1176 u8 reserved_at_91[0x7]; 1177 u8 prio_tag_required[0x1]; 1178 u8 reserved_at_99[0x2]; 1179 u8 log_max_qp[0x5]; 1180 1181 u8 reserved_at_a0[0xb]; 1182 u8 log_max_srq[0x5]; 1183 u8 reserved_at_b0[0x10]; 1184 1185 u8 max_sgl_for_optimized_performance[0x8]; 1186 u8 log_max_cq_sz[0x8]; 1187 u8 reserved_at_d0[0xb]; 1188 u8 log_max_cq[0x5]; 1189 1190 u8 log_max_eq_sz[0x8]; 1191 u8 relaxed_ordering_write[0x1]; 1192 u8 relaxed_ordering_read[0x1]; 1193 u8 log_max_mkey[0x6]; 1194 u8 reserved_at_f0[0x8]; 1195 u8 dump_fill_mkey[0x1]; 1196 u8 reserved_at_f9[0x2]; 1197 u8 fast_teardown[0x1]; 1198 u8 log_max_eq[0x4]; 1199 1200 u8 max_indirection[0x8]; 1201 u8 fixed_buffer_size[0x1]; 1202 u8 log_max_mrw_sz[0x7]; 1203 u8 force_teardown[0x1]; 1204 u8 reserved_at_111[0x1]; 1205 u8 log_max_bsf_list_size[0x6]; 1206 u8 umr_extended_translation_offset[0x1]; 1207 u8 null_mkey[0x1]; 1208 u8 log_max_klm_list_size[0x6]; 1209 1210 u8 reserved_at_120[0xa]; 1211 u8 log_max_ra_req_dc[0x6]; 1212 u8 reserved_at_130[0xa]; 1213 u8 log_max_ra_res_dc[0x6]; 1214 1215 u8 reserved_at_140[0x9]; 1216 u8 roce_accl[0x1]; 1217 u8 log_max_ra_req_qp[0x6]; 1218 u8 reserved_at_150[0xa]; 1219 u8 log_max_ra_res_qp[0x6]; 1220 1221 u8 end_pad[0x1]; 1222 u8 cc_query_allowed[0x1]; 1223 u8 cc_modify_allowed[0x1]; 1224 u8 start_pad[0x1]; 1225 u8 cache_line_128byte[0x1]; 1226 u8 reserved_at_165[0x4]; 1227 u8 rts2rts_qp_counters_set_id[0x1]; 1228 u8 reserved_at_16a[0x2]; 1229 u8 vnic_env_int_rq_oob[0x1]; 1230 u8 sbcam_reg[0x1]; 1231 u8 reserved_at_16e[0x1]; 1232 u8 qcam_reg[0x1]; 1233 u8 gid_table_size[0x10]; 1234 1235 u8 out_of_seq_cnt[0x1]; 1236 u8 vport_counters[0x1]; 1237 u8 retransmission_q_counters[0x1]; 1238 u8 debug[0x1]; 1239 u8 modify_rq_counter_set_id[0x1]; 1240 u8 rq_delay_drop[0x1]; 1241 u8 max_qp_cnt[0xa]; 1242 u8 pkey_table_size[0x10]; 1243 1244 u8 vport_group_manager[0x1]; 1245 u8 vhca_group_manager[0x1]; 1246 u8 ib_virt[0x1]; 1247 u8 eth_virt[0x1]; 1248 u8 vnic_env_queue_counters[0x1]; 1249 u8 ets[0x1]; 1250 u8 nic_flow_table[0x1]; 1251 u8 eswitch_manager[0x1]; 1252 u8 device_memory[0x1]; 1253 u8 mcam_reg[0x1]; 1254 u8 pcam_reg[0x1]; 1255 u8 local_ca_ack_delay[0x5]; 1256 u8 port_module_event[0x1]; 1257 u8 enhanced_error_q_counters[0x1]; 1258 u8 ports_check[0x1]; 1259 u8 reserved_at_1b3[0x1]; 1260 u8 disable_link_up[0x1]; 1261 u8 beacon_led[0x1]; 1262 u8 port_type[0x2]; 1263 u8 num_ports[0x8]; 1264 1265 u8 reserved_at_1c0[0x1]; 1266 u8 pps[0x1]; 1267 u8 pps_modify[0x1]; 1268 u8 log_max_msg[0x5]; 1269 u8 reserved_at_1c8[0x4]; 1270 u8 max_tc[0x4]; 1271 u8 temp_warn_event[0x1]; 1272 u8 dcbx[0x1]; 1273 u8 general_notification_event[0x1]; 1274 u8 reserved_at_1d3[0x2]; 1275 u8 fpga[0x1]; 1276 u8 rol_s[0x1]; 1277 u8 rol_g[0x1]; 1278 u8 reserved_at_1d8[0x1]; 1279 u8 wol_s[0x1]; 1280 u8 wol_g[0x1]; 1281 u8 wol_a[0x1]; 1282 u8 wol_b[0x1]; 1283 u8 wol_m[0x1]; 1284 u8 wol_u[0x1]; 1285 u8 wol_p[0x1]; 1286 1287 u8 stat_rate_support[0x10]; 1288 u8 reserved_at_1f0[0xc]; 1289 u8 cqe_version[0x4]; 1290 1291 u8 compact_address_vector[0x1]; 1292 u8 striding_rq[0x1]; 1293 u8 reserved_at_202[0x1]; 1294 u8 ipoib_enhanced_offloads[0x1]; 1295 u8 ipoib_basic_offloads[0x1]; 1296 u8 reserved_at_205[0x1]; 1297 u8 repeated_block_disabled[0x1]; 1298 u8 umr_modify_entity_size_disabled[0x1]; 1299 u8 umr_modify_atomic_disabled[0x1]; 1300 u8 umr_indirect_mkey_disabled[0x1]; 1301 u8 umr_fence[0x2]; 1302 u8 dc_req_scat_data_cqe[0x1]; 1303 u8 reserved_at_20d[0x2]; 1304 u8 drain_sigerr[0x1]; 1305 u8 cmdif_checksum[0x2]; 1306 u8 sigerr_cqe[0x1]; 1307 u8 reserved_at_213[0x1]; 1308 u8 wq_signature[0x1]; 1309 u8 sctr_data_cqe[0x1]; 1310 u8 reserved_at_216[0x1]; 1311 u8 sho[0x1]; 1312 u8 tph[0x1]; 1313 u8 rf[0x1]; 1314 u8 dct[0x1]; 1315 u8 qos[0x1]; 1316 u8 eth_net_offloads[0x1]; 1317 u8 roce[0x1]; 1318 u8 atomic[0x1]; 1319 u8 reserved_at_21f[0x1]; 1320 1321 u8 cq_oi[0x1]; 1322 u8 cq_resize[0x1]; 1323 u8 cq_moderation[0x1]; 1324 u8 reserved_at_223[0x3]; 1325 u8 cq_eq_remap[0x1]; 1326 u8 pg[0x1]; 1327 u8 block_lb_mc[0x1]; 1328 u8 reserved_at_229[0x1]; 1329 u8 scqe_break_moderation[0x1]; 1330 u8 cq_period_start_from_cqe[0x1]; 1331 u8 cd[0x1]; 1332 u8 reserved_at_22d[0x1]; 1333 u8 apm[0x1]; 1334 u8 vector_calc[0x1]; 1335 u8 umr_ptr_rlky[0x1]; 1336 u8 imaicl[0x1]; 1337 u8 qp_packet_based[0x1]; 1338 u8 reserved_at_233[0x3]; 1339 u8 qkv[0x1]; 1340 u8 pkv[0x1]; 1341 u8 set_deth_sqpn[0x1]; 1342 u8 reserved_at_239[0x3]; 1343 u8 xrc[0x1]; 1344 u8 ud[0x1]; 1345 u8 uc[0x1]; 1346 u8 rc[0x1]; 1347 1348 u8 uar_4k[0x1]; 1349 u8 reserved_at_241[0x9]; 1350 u8 uar_sz[0x6]; 1351 u8 reserved_at_250[0x8]; 1352 u8 log_pg_sz[0x8]; 1353 1354 u8 bf[0x1]; 1355 u8 driver_version[0x1]; 1356 u8 pad_tx_eth_packet[0x1]; 1357 u8 reserved_at_263[0x8]; 1358 u8 log_bf_reg_size[0x5]; 1359 1360 u8 reserved_at_270[0x8]; 1361 u8 lag_tx_port_affinity[0x1]; 1362 u8 reserved_at_279[0x2]; 1363 u8 lag_master[0x1]; 1364 u8 num_lag_ports[0x4]; 1365 1366 u8 reserved_at_280[0x10]; 1367 u8 max_wqe_sz_sq[0x10]; 1368 1369 u8 reserved_at_2a0[0x10]; 1370 u8 max_wqe_sz_rq[0x10]; 1371 1372 u8 max_flow_counter_31_16[0x10]; 1373 u8 max_wqe_sz_sq_dc[0x10]; 1374 1375 u8 reserved_at_2e0[0x7]; 1376 u8 max_qp_mcg[0x19]; 1377 1378 u8 reserved_at_300[0x10]; 1379 u8 flow_counter_bulk_alloc[0x8]; 1380 u8 log_max_mcg[0x8]; 1381 1382 u8 reserved_at_320[0x3]; 1383 u8 log_max_transport_domain[0x5]; 1384 u8 reserved_at_328[0x3]; 1385 u8 log_max_pd[0x5]; 1386 u8 reserved_at_330[0xb]; 1387 u8 log_max_xrcd[0x5]; 1388 1389 u8 nic_receive_steering_discard[0x1]; 1390 u8 receive_discard_vport_down[0x1]; 1391 u8 transmit_discard_vport_down[0x1]; 1392 u8 reserved_at_343[0x5]; 1393 u8 log_max_flow_counter_bulk[0x8]; 1394 u8 max_flow_counter_15_0[0x10]; 1395 1396 1397 u8 reserved_at_360[0x3]; 1398 u8 log_max_rq[0x5]; 1399 u8 reserved_at_368[0x3]; 1400 u8 log_max_sq[0x5]; 1401 u8 reserved_at_370[0x3]; 1402 u8 log_max_tir[0x5]; 1403 u8 reserved_at_378[0x3]; 1404 u8 log_max_tis[0x5]; 1405 1406 u8 basic_cyclic_rcv_wqe[0x1]; 1407 u8 reserved_at_381[0x2]; 1408 u8 log_max_rmp[0x5]; 1409 u8 reserved_at_388[0x3]; 1410 u8 log_max_rqt[0x5]; 1411 u8 reserved_at_390[0x3]; 1412 u8 log_max_rqt_size[0x5]; 1413 u8 reserved_at_398[0x3]; 1414 u8 log_max_tis_per_sq[0x5]; 1415 1416 u8 ext_stride_num_range[0x1]; 1417 u8 reserved_at_3a1[0x2]; 1418 u8 log_max_stride_sz_rq[0x5]; 1419 u8 reserved_at_3a8[0x3]; 1420 u8 log_min_stride_sz_rq[0x5]; 1421 u8 reserved_at_3b0[0x3]; 1422 u8 log_max_stride_sz_sq[0x5]; 1423 u8 reserved_at_3b8[0x3]; 1424 u8 log_min_stride_sz_sq[0x5]; 1425 1426 u8 hairpin[0x1]; 1427 u8 reserved_at_3c1[0x2]; 1428 u8 log_max_hairpin_queues[0x5]; 1429 u8 reserved_at_3c8[0x3]; 1430 u8 log_max_hairpin_wq_data_sz[0x5]; 1431 u8 reserved_at_3d0[0x3]; 1432 u8 log_max_hairpin_num_packets[0x5]; 1433 u8 reserved_at_3d8[0x3]; 1434 u8 log_max_wq_sz[0x5]; 1435 1436 u8 nic_vport_change_event[0x1]; 1437 u8 disable_local_lb_uc[0x1]; 1438 u8 disable_local_lb_mc[0x1]; 1439 u8 log_min_hairpin_wq_data_sz[0x5]; 1440 u8 reserved_at_3e8[0x3]; 1441 u8 log_max_vlan_list[0x5]; 1442 u8 reserved_at_3f0[0x3]; 1443 u8 log_max_current_mc_list[0x5]; 1444 u8 reserved_at_3f8[0x3]; 1445 u8 log_max_current_uc_list[0x5]; 1446 1447 u8 general_obj_types[0x40]; 1448 1449 u8 reserved_at_440[0x20]; 1450 1451 u8 reserved_at_460[0x3]; 1452 u8 log_max_uctx[0x5]; 1453 u8 reserved_at_468[0x3]; 1454 u8 log_max_umem[0x5]; 1455 u8 max_num_eqs[0x10]; 1456 1457 u8 reserved_at_480[0x1]; 1458 u8 tls_tx[0x1]; 1459 u8 reserved_at_482[0x1]; 1460 u8 log_max_l2_table[0x5]; 1461 u8 reserved_at_488[0x8]; 1462 u8 log_uar_page_sz[0x10]; 1463 1464 u8 reserved_at_4a0[0x20]; 1465 u8 device_frequency_mhz[0x20]; 1466 u8 device_frequency_khz[0x20]; 1467 1468 u8 reserved_at_500[0x20]; 1469 u8 num_of_uars_per_page[0x20]; 1470 1471 u8 flex_parser_protocols[0x20]; 1472 1473 u8 max_geneve_tlv_options[0x8]; 1474 u8 reserved_at_568[0x3]; 1475 u8 max_geneve_tlv_option_data_len[0x5]; 1476 u8 reserved_at_570[0x10]; 1477 1478 u8 reserved_at_580[0x33]; 1479 u8 log_max_dek[0x5]; 1480 u8 reserved_at_5b8[0x4]; 1481 u8 mini_cqe_resp_stride_index[0x1]; 1482 u8 cqe_128_always[0x1]; 1483 u8 cqe_compression_128[0x1]; 1484 u8 cqe_compression[0x1]; 1485 1486 u8 cqe_compression_timeout[0x10]; 1487 u8 cqe_compression_max_num[0x10]; 1488 1489 u8 reserved_at_5e0[0x10]; 1490 u8 tag_matching[0x1]; 1491 u8 rndv_offload_rc[0x1]; 1492 u8 rndv_offload_dc[0x1]; 1493 u8 log_tag_matching_list_sz[0x5]; 1494 u8 reserved_at_5f8[0x3]; 1495 u8 log_max_xrq[0x5]; 1496 1497 u8 affiliate_nic_vport_criteria[0x8]; 1498 u8 native_port_num[0x8]; 1499 u8 num_vhca_ports[0x8]; 1500 u8 reserved_at_618[0x6]; 1501 u8 sw_owner_id[0x1]; 1502 u8 reserved_at_61f[0x1]; 1503 1504 u8 max_num_of_monitor_counters[0x10]; 1505 u8 num_ppcnt_monitor_counters[0x10]; 1506 1507 u8 reserved_at_640[0x10]; 1508 u8 num_q_monitor_counters[0x10]; 1509 1510 u8 reserved_at_660[0x20]; 1511 1512 u8 sf[0x1]; 1513 u8 sf_set_partition[0x1]; 1514 u8 reserved_at_682[0x1]; 1515 u8 log_max_sf[0x5]; 1516 u8 reserved_at_688[0x8]; 1517 u8 log_min_sf_size[0x8]; 1518 u8 max_num_sf_partitions[0x8]; 1519 1520 u8 uctx_cap[0x20]; 1521 1522 u8 reserved_at_6c0[0x4]; 1523 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1524 u8 flex_parser_id_icmp_dw1[0x4]; 1525 u8 flex_parser_id_icmp_dw0[0x4]; 1526 u8 flex_parser_id_icmpv6_dw1[0x4]; 1527 u8 flex_parser_id_icmpv6_dw0[0x4]; 1528 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1529 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1530 1531 u8 reserved_at_6e0[0x10]; 1532 u8 sf_base_id[0x10]; 1533 1534 u8 reserved_at_700[0x80]; 1535 u8 vhca_tunnel_commands[0x40]; 1536 u8 reserved_at_7c0[0x40]; 1537 }; 1538 1539 enum mlx5_flow_destination_type { 1540 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1541 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1542 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1543 1544 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1545 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1546 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1547 }; 1548 1549 enum mlx5_flow_table_miss_action { 1550 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1551 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1552 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1553 }; 1554 1555 struct mlx5_ifc_dest_format_struct_bits { 1556 u8 destination_type[0x8]; 1557 u8 destination_id[0x18]; 1558 1559 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1560 u8 packet_reformat[0x1]; 1561 u8 reserved_at_22[0xe]; 1562 u8 destination_eswitch_owner_vhca_id[0x10]; 1563 }; 1564 1565 struct mlx5_ifc_flow_counter_list_bits { 1566 u8 flow_counter_id[0x20]; 1567 1568 u8 reserved_at_20[0x20]; 1569 }; 1570 1571 struct mlx5_ifc_extended_dest_format_bits { 1572 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1573 1574 u8 packet_reformat_id[0x20]; 1575 1576 u8 reserved_at_60[0x20]; 1577 }; 1578 1579 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1580 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1581 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1582 }; 1583 1584 struct mlx5_ifc_fte_match_param_bits { 1585 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1586 1587 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1588 1589 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1590 1591 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1592 1593 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1594 1595 u8 reserved_at_a00[0x600]; 1596 }; 1597 1598 enum { 1599 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1600 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1601 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1602 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1603 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1604 }; 1605 1606 struct mlx5_ifc_rx_hash_field_select_bits { 1607 u8 l3_prot_type[0x1]; 1608 u8 l4_prot_type[0x1]; 1609 u8 selected_fields[0x1e]; 1610 }; 1611 1612 enum { 1613 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1614 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1615 }; 1616 1617 enum { 1618 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1619 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1620 }; 1621 1622 struct mlx5_ifc_wq_bits { 1623 u8 wq_type[0x4]; 1624 u8 wq_signature[0x1]; 1625 u8 end_padding_mode[0x2]; 1626 u8 cd_slave[0x1]; 1627 u8 reserved_at_8[0x18]; 1628 1629 u8 hds_skip_first_sge[0x1]; 1630 u8 log2_hds_buf_size[0x3]; 1631 u8 reserved_at_24[0x7]; 1632 u8 page_offset[0x5]; 1633 u8 lwm[0x10]; 1634 1635 u8 reserved_at_40[0x8]; 1636 u8 pd[0x18]; 1637 1638 u8 reserved_at_60[0x8]; 1639 u8 uar_page[0x18]; 1640 1641 u8 dbr_addr[0x40]; 1642 1643 u8 hw_counter[0x20]; 1644 1645 u8 sw_counter[0x20]; 1646 1647 u8 reserved_at_100[0xc]; 1648 u8 log_wq_stride[0x4]; 1649 u8 reserved_at_110[0x3]; 1650 u8 log_wq_pg_sz[0x5]; 1651 u8 reserved_at_118[0x3]; 1652 u8 log_wq_sz[0x5]; 1653 1654 u8 dbr_umem_valid[0x1]; 1655 u8 wq_umem_valid[0x1]; 1656 u8 reserved_at_122[0x1]; 1657 u8 log_hairpin_num_packets[0x5]; 1658 u8 reserved_at_128[0x3]; 1659 u8 log_hairpin_data_sz[0x5]; 1660 1661 u8 reserved_at_130[0x4]; 1662 u8 log_wqe_num_of_strides[0x4]; 1663 u8 two_byte_shift_en[0x1]; 1664 u8 reserved_at_139[0x4]; 1665 u8 log_wqe_stride_size[0x3]; 1666 1667 u8 reserved_at_140[0x4c0]; 1668 1669 struct mlx5_ifc_cmd_pas_bits pas[0]; 1670 }; 1671 1672 struct mlx5_ifc_rq_num_bits { 1673 u8 reserved_at_0[0x8]; 1674 u8 rq_num[0x18]; 1675 }; 1676 1677 struct mlx5_ifc_mac_address_layout_bits { 1678 u8 reserved_at_0[0x10]; 1679 u8 mac_addr_47_32[0x10]; 1680 1681 u8 mac_addr_31_0[0x20]; 1682 }; 1683 1684 struct mlx5_ifc_vlan_layout_bits { 1685 u8 reserved_at_0[0x14]; 1686 u8 vlan[0x0c]; 1687 1688 u8 reserved_at_20[0x20]; 1689 }; 1690 1691 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1692 u8 reserved_at_0[0xa0]; 1693 1694 u8 min_time_between_cnps[0x20]; 1695 1696 u8 reserved_at_c0[0x12]; 1697 u8 cnp_dscp[0x6]; 1698 u8 reserved_at_d8[0x4]; 1699 u8 cnp_prio_mode[0x1]; 1700 u8 cnp_802p_prio[0x3]; 1701 1702 u8 reserved_at_e0[0x720]; 1703 }; 1704 1705 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1706 u8 reserved_at_0[0x60]; 1707 1708 u8 reserved_at_60[0x4]; 1709 u8 clamp_tgt_rate[0x1]; 1710 u8 reserved_at_65[0x3]; 1711 u8 clamp_tgt_rate_after_time_inc[0x1]; 1712 u8 reserved_at_69[0x17]; 1713 1714 u8 reserved_at_80[0x20]; 1715 1716 u8 rpg_time_reset[0x20]; 1717 1718 u8 rpg_byte_reset[0x20]; 1719 1720 u8 rpg_threshold[0x20]; 1721 1722 u8 rpg_max_rate[0x20]; 1723 1724 u8 rpg_ai_rate[0x20]; 1725 1726 u8 rpg_hai_rate[0x20]; 1727 1728 u8 rpg_gd[0x20]; 1729 1730 u8 rpg_min_dec_fac[0x20]; 1731 1732 u8 rpg_min_rate[0x20]; 1733 1734 u8 reserved_at_1c0[0xe0]; 1735 1736 u8 rate_to_set_on_first_cnp[0x20]; 1737 1738 u8 dce_tcp_g[0x20]; 1739 1740 u8 dce_tcp_rtt[0x20]; 1741 1742 u8 rate_reduce_monitor_period[0x20]; 1743 1744 u8 reserved_at_320[0x20]; 1745 1746 u8 initial_alpha_value[0x20]; 1747 1748 u8 reserved_at_360[0x4a0]; 1749 }; 1750 1751 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1752 u8 reserved_at_0[0x80]; 1753 1754 u8 rppp_max_rps[0x20]; 1755 1756 u8 rpg_time_reset[0x20]; 1757 1758 u8 rpg_byte_reset[0x20]; 1759 1760 u8 rpg_threshold[0x20]; 1761 1762 u8 rpg_max_rate[0x20]; 1763 1764 u8 rpg_ai_rate[0x20]; 1765 1766 u8 rpg_hai_rate[0x20]; 1767 1768 u8 rpg_gd[0x20]; 1769 1770 u8 rpg_min_dec_fac[0x20]; 1771 1772 u8 rpg_min_rate[0x20]; 1773 1774 u8 reserved_at_1c0[0x640]; 1775 }; 1776 1777 enum { 1778 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1779 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1780 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1781 }; 1782 1783 struct mlx5_ifc_resize_field_select_bits { 1784 u8 resize_field_select[0x20]; 1785 }; 1786 1787 struct mlx5_ifc_resource_dump_bits { 1788 u8 more_dump[0x1]; 1789 u8 inline_dump[0x1]; 1790 u8 reserved_at_2[0xa]; 1791 u8 seq_num[0x4]; 1792 u8 segment_type[0x10]; 1793 1794 u8 reserved_at_20[0x10]; 1795 u8 vhca_id[0x10]; 1796 1797 u8 index1[0x20]; 1798 1799 u8 index2[0x20]; 1800 1801 u8 num_of_obj1[0x10]; 1802 u8 num_of_obj2[0x10]; 1803 1804 u8 reserved_at_a0[0x20]; 1805 1806 u8 device_opaque[0x40]; 1807 1808 u8 mkey[0x20]; 1809 1810 u8 size[0x20]; 1811 1812 u8 address[0x40]; 1813 1814 u8 inline_data[52][0x20]; 1815 }; 1816 1817 struct mlx5_ifc_resource_dump_menu_record_bits { 1818 u8 reserved_at_0[0x4]; 1819 u8 num_of_obj2_supports_active[0x1]; 1820 u8 num_of_obj2_supports_all[0x1]; 1821 u8 must_have_num_of_obj2[0x1]; 1822 u8 support_num_of_obj2[0x1]; 1823 u8 num_of_obj1_supports_active[0x1]; 1824 u8 num_of_obj1_supports_all[0x1]; 1825 u8 must_have_num_of_obj1[0x1]; 1826 u8 support_num_of_obj1[0x1]; 1827 u8 must_have_index2[0x1]; 1828 u8 support_index2[0x1]; 1829 u8 must_have_index1[0x1]; 1830 u8 support_index1[0x1]; 1831 u8 segment_type[0x10]; 1832 1833 u8 segment_name[4][0x20]; 1834 1835 u8 index1_name[4][0x20]; 1836 1837 u8 index2_name[4][0x20]; 1838 }; 1839 1840 struct mlx5_ifc_resource_dump_segment_header_bits { 1841 u8 length_dw[0x10]; 1842 u8 segment_type[0x10]; 1843 }; 1844 1845 struct mlx5_ifc_resource_dump_command_segment_bits { 1846 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1847 1848 u8 segment_called[0x10]; 1849 u8 vhca_id[0x10]; 1850 1851 u8 index1[0x20]; 1852 1853 u8 index2[0x20]; 1854 1855 u8 num_of_obj1[0x10]; 1856 u8 num_of_obj2[0x10]; 1857 }; 1858 1859 struct mlx5_ifc_resource_dump_error_segment_bits { 1860 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1861 1862 u8 reserved_at_20[0x10]; 1863 u8 syndrome_id[0x10]; 1864 1865 u8 reserved_at_40[0x40]; 1866 1867 u8 error[8][0x20]; 1868 }; 1869 1870 struct mlx5_ifc_resource_dump_info_segment_bits { 1871 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1872 1873 u8 reserved_at_20[0x18]; 1874 u8 dump_version[0x8]; 1875 1876 u8 hw_version[0x20]; 1877 1878 u8 fw_version[0x20]; 1879 }; 1880 1881 struct mlx5_ifc_resource_dump_menu_segment_bits { 1882 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1883 1884 u8 reserved_at_20[0x10]; 1885 u8 num_of_records[0x10]; 1886 1887 struct mlx5_ifc_resource_dump_menu_record_bits record[0]; 1888 }; 1889 1890 struct mlx5_ifc_resource_dump_resource_segment_bits { 1891 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1892 1893 u8 reserved_at_20[0x20]; 1894 1895 u8 index1[0x20]; 1896 1897 u8 index2[0x20]; 1898 1899 u8 payload[0][0x20]; 1900 }; 1901 1902 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1903 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1904 }; 1905 1906 struct mlx5_ifc_menu_resource_dump_response_bits { 1907 struct mlx5_ifc_resource_dump_info_segment_bits info; 1908 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1909 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1910 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1911 }; 1912 1913 enum { 1914 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1915 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1916 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1917 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1918 }; 1919 1920 struct mlx5_ifc_modify_field_select_bits { 1921 u8 modify_field_select[0x20]; 1922 }; 1923 1924 struct mlx5_ifc_field_select_r_roce_np_bits { 1925 u8 field_select_r_roce_np[0x20]; 1926 }; 1927 1928 struct mlx5_ifc_field_select_r_roce_rp_bits { 1929 u8 field_select_r_roce_rp[0x20]; 1930 }; 1931 1932 enum { 1933 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1934 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1935 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1936 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1937 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1938 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1939 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1940 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1941 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1942 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1943 }; 1944 1945 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1946 u8 field_select_8021qaurp[0x20]; 1947 }; 1948 1949 struct mlx5_ifc_phys_layer_cntrs_bits { 1950 u8 time_since_last_clear_high[0x20]; 1951 1952 u8 time_since_last_clear_low[0x20]; 1953 1954 u8 symbol_errors_high[0x20]; 1955 1956 u8 symbol_errors_low[0x20]; 1957 1958 u8 sync_headers_errors_high[0x20]; 1959 1960 u8 sync_headers_errors_low[0x20]; 1961 1962 u8 edpl_bip_errors_lane0_high[0x20]; 1963 1964 u8 edpl_bip_errors_lane0_low[0x20]; 1965 1966 u8 edpl_bip_errors_lane1_high[0x20]; 1967 1968 u8 edpl_bip_errors_lane1_low[0x20]; 1969 1970 u8 edpl_bip_errors_lane2_high[0x20]; 1971 1972 u8 edpl_bip_errors_lane2_low[0x20]; 1973 1974 u8 edpl_bip_errors_lane3_high[0x20]; 1975 1976 u8 edpl_bip_errors_lane3_low[0x20]; 1977 1978 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1979 1980 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1981 1982 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1983 1984 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1985 1986 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1987 1988 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1989 1990 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1991 1992 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1993 1994 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1995 1996 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1997 1998 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1999 2000 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2001 2002 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2003 2004 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2005 2006 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2007 2008 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2009 2010 u8 rs_fec_corrected_blocks_high[0x20]; 2011 2012 u8 rs_fec_corrected_blocks_low[0x20]; 2013 2014 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2015 2016 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2017 2018 u8 rs_fec_no_errors_blocks_high[0x20]; 2019 2020 u8 rs_fec_no_errors_blocks_low[0x20]; 2021 2022 u8 rs_fec_single_error_blocks_high[0x20]; 2023 2024 u8 rs_fec_single_error_blocks_low[0x20]; 2025 2026 u8 rs_fec_corrected_symbols_total_high[0x20]; 2027 2028 u8 rs_fec_corrected_symbols_total_low[0x20]; 2029 2030 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2031 2032 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2033 2034 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2035 2036 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2037 2038 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2039 2040 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2041 2042 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2043 2044 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2045 2046 u8 link_down_events[0x20]; 2047 2048 u8 successful_recovery_events[0x20]; 2049 2050 u8 reserved_at_640[0x180]; 2051 }; 2052 2053 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2054 u8 time_since_last_clear_high[0x20]; 2055 2056 u8 time_since_last_clear_low[0x20]; 2057 2058 u8 phy_received_bits_high[0x20]; 2059 2060 u8 phy_received_bits_low[0x20]; 2061 2062 u8 phy_symbol_errors_high[0x20]; 2063 2064 u8 phy_symbol_errors_low[0x20]; 2065 2066 u8 phy_corrected_bits_high[0x20]; 2067 2068 u8 phy_corrected_bits_low[0x20]; 2069 2070 u8 phy_corrected_bits_lane0_high[0x20]; 2071 2072 u8 phy_corrected_bits_lane0_low[0x20]; 2073 2074 u8 phy_corrected_bits_lane1_high[0x20]; 2075 2076 u8 phy_corrected_bits_lane1_low[0x20]; 2077 2078 u8 phy_corrected_bits_lane2_high[0x20]; 2079 2080 u8 phy_corrected_bits_lane2_low[0x20]; 2081 2082 u8 phy_corrected_bits_lane3_high[0x20]; 2083 2084 u8 phy_corrected_bits_lane3_low[0x20]; 2085 2086 u8 reserved_at_200[0x5c0]; 2087 }; 2088 2089 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2090 u8 symbol_error_counter[0x10]; 2091 2092 u8 link_error_recovery_counter[0x8]; 2093 2094 u8 link_downed_counter[0x8]; 2095 2096 u8 port_rcv_errors[0x10]; 2097 2098 u8 port_rcv_remote_physical_errors[0x10]; 2099 2100 u8 port_rcv_switch_relay_errors[0x10]; 2101 2102 u8 port_xmit_discards[0x10]; 2103 2104 u8 port_xmit_constraint_errors[0x8]; 2105 2106 u8 port_rcv_constraint_errors[0x8]; 2107 2108 u8 reserved_at_70[0x8]; 2109 2110 u8 link_overrun_errors[0x8]; 2111 2112 u8 reserved_at_80[0x10]; 2113 2114 u8 vl_15_dropped[0x10]; 2115 2116 u8 reserved_at_a0[0x80]; 2117 2118 u8 port_xmit_wait[0x20]; 2119 }; 2120 2121 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2122 u8 transmit_queue_high[0x20]; 2123 2124 u8 transmit_queue_low[0x20]; 2125 2126 u8 no_buffer_discard_uc_high[0x20]; 2127 2128 u8 no_buffer_discard_uc_low[0x20]; 2129 2130 u8 reserved_at_80[0x740]; 2131 }; 2132 2133 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2134 u8 wred_discard_high[0x20]; 2135 2136 u8 wred_discard_low[0x20]; 2137 2138 u8 ecn_marked_tc_high[0x20]; 2139 2140 u8 ecn_marked_tc_low[0x20]; 2141 2142 u8 reserved_at_80[0x740]; 2143 }; 2144 2145 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2146 u8 rx_octets_high[0x20]; 2147 2148 u8 rx_octets_low[0x20]; 2149 2150 u8 reserved_at_40[0xc0]; 2151 2152 u8 rx_frames_high[0x20]; 2153 2154 u8 rx_frames_low[0x20]; 2155 2156 u8 tx_octets_high[0x20]; 2157 2158 u8 tx_octets_low[0x20]; 2159 2160 u8 reserved_at_180[0xc0]; 2161 2162 u8 tx_frames_high[0x20]; 2163 2164 u8 tx_frames_low[0x20]; 2165 2166 u8 rx_pause_high[0x20]; 2167 2168 u8 rx_pause_low[0x20]; 2169 2170 u8 rx_pause_duration_high[0x20]; 2171 2172 u8 rx_pause_duration_low[0x20]; 2173 2174 u8 tx_pause_high[0x20]; 2175 2176 u8 tx_pause_low[0x20]; 2177 2178 u8 tx_pause_duration_high[0x20]; 2179 2180 u8 tx_pause_duration_low[0x20]; 2181 2182 u8 rx_pause_transition_high[0x20]; 2183 2184 u8 rx_pause_transition_low[0x20]; 2185 2186 u8 rx_discards_high[0x20]; 2187 2188 u8 rx_discards_low[0x20]; 2189 2190 u8 device_stall_minor_watermark_cnt_high[0x20]; 2191 2192 u8 device_stall_minor_watermark_cnt_low[0x20]; 2193 2194 u8 device_stall_critical_watermark_cnt_high[0x20]; 2195 2196 u8 device_stall_critical_watermark_cnt_low[0x20]; 2197 2198 u8 reserved_at_480[0x340]; 2199 }; 2200 2201 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2202 u8 port_transmit_wait_high[0x20]; 2203 2204 u8 port_transmit_wait_low[0x20]; 2205 2206 u8 reserved_at_40[0x100]; 2207 2208 u8 rx_buffer_almost_full_high[0x20]; 2209 2210 u8 rx_buffer_almost_full_low[0x20]; 2211 2212 u8 rx_buffer_full_high[0x20]; 2213 2214 u8 rx_buffer_full_low[0x20]; 2215 2216 u8 rx_icrc_encapsulated_high[0x20]; 2217 2218 u8 rx_icrc_encapsulated_low[0x20]; 2219 2220 u8 reserved_at_200[0x5c0]; 2221 }; 2222 2223 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2224 u8 dot3stats_alignment_errors_high[0x20]; 2225 2226 u8 dot3stats_alignment_errors_low[0x20]; 2227 2228 u8 dot3stats_fcs_errors_high[0x20]; 2229 2230 u8 dot3stats_fcs_errors_low[0x20]; 2231 2232 u8 dot3stats_single_collision_frames_high[0x20]; 2233 2234 u8 dot3stats_single_collision_frames_low[0x20]; 2235 2236 u8 dot3stats_multiple_collision_frames_high[0x20]; 2237 2238 u8 dot3stats_multiple_collision_frames_low[0x20]; 2239 2240 u8 dot3stats_sqe_test_errors_high[0x20]; 2241 2242 u8 dot3stats_sqe_test_errors_low[0x20]; 2243 2244 u8 dot3stats_deferred_transmissions_high[0x20]; 2245 2246 u8 dot3stats_deferred_transmissions_low[0x20]; 2247 2248 u8 dot3stats_late_collisions_high[0x20]; 2249 2250 u8 dot3stats_late_collisions_low[0x20]; 2251 2252 u8 dot3stats_excessive_collisions_high[0x20]; 2253 2254 u8 dot3stats_excessive_collisions_low[0x20]; 2255 2256 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2257 2258 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2259 2260 u8 dot3stats_carrier_sense_errors_high[0x20]; 2261 2262 u8 dot3stats_carrier_sense_errors_low[0x20]; 2263 2264 u8 dot3stats_frame_too_longs_high[0x20]; 2265 2266 u8 dot3stats_frame_too_longs_low[0x20]; 2267 2268 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2269 2270 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2271 2272 u8 dot3stats_symbol_errors_high[0x20]; 2273 2274 u8 dot3stats_symbol_errors_low[0x20]; 2275 2276 u8 dot3control_in_unknown_opcodes_high[0x20]; 2277 2278 u8 dot3control_in_unknown_opcodes_low[0x20]; 2279 2280 u8 dot3in_pause_frames_high[0x20]; 2281 2282 u8 dot3in_pause_frames_low[0x20]; 2283 2284 u8 dot3out_pause_frames_high[0x20]; 2285 2286 u8 dot3out_pause_frames_low[0x20]; 2287 2288 u8 reserved_at_400[0x3c0]; 2289 }; 2290 2291 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2292 u8 ether_stats_drop_events_high[0x20]; 2293 2294 u8 ether_stats_drop_events_low[0x20]; 2295 2296 u8 ether_stats_octets_high[0x20]; 2297 2298 u8 ether_stats_octets_low[0x20]; 2299 2300 u8 ether_stats_pkts_high[0x20]; 2301 2302 u8 ether_stats_pkts_low[0x20]; 2303 2304 u8 ether_stats_broadcast_pkts_high[0x20]; 2305 2306 u8 ether_stats_broadcast_pkts_low[0x20]; 2307 2308 u8 ether_stats_multicast_pkts_high[0x20]; 2309 2310 u8 ether_stats_multicast_pkts_low[0x20]; 2311 2312 u8 ether_stats_crc_align_errors_high[0x20]; 2313 2314 u8 ether_stats_crc_align_errors_low[0x20]; 2315 2316 u8 ether_stats_undersize_pkts_high[0x20]; 2317 2318 u8 ether_stats_undersize_pkts_low[0x20]; 2319 2320 u8 ether_stats_oversize_pkts_high[0x20]; 2321 2322 u8 ether_stats_oversize_pkts_low[0x20]; 2323 2324 u8 ether_stats_fragments_high[0x20]; 2325 2326 u8 ether_stats_fragments_low[0x20]; 2327 2328 u8 ether_stats_jabbers_high[0x20]; 2329 2330 u8 ether_stats_jabbers_low[0x20]; 2331 2332 u8 ether_stats_collisions_high[0x20]; 2333 2334 u8 ether_stats_collisions_low[0x20]; 2335 2336 u8 ether_stats_pkts64octets_high[0x20]; 2337 2338 u8 ether_stats_pkts64octets_low[0x20]; 2339 2340 u8 ether_stats_pkts65to127octets_high[0x20]; 2341 2342 u8 ether_stats_pkts65to127octets_low[0x20]; 2343 2344 u8 ether_stats_pkts128to255octets_high[0x20]; 2345 2346 u8 ether_stats_pkts128to255octets_low[0x20]; 2347 2348 u8 ether_stats_pkts256to511octets_high[0x20]; 2349 2350 u8 ether_stats_pkts256to511octets_low[0x20]; 2351 2352 u8 ether_stats_pkts512to1023octets_high[0x20]; 2353 2354 u8 ether_stats_pkts512to1023octets_low[0x20]; 2355 2356 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2357 2358 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2359 2360 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2361 2362 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2363 2364 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2365 2366 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2367 2368 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2369 2370 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2371 2372 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2373 2374 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2375 2376 u8 reserved_at_540[0x280]; 2377 }; 2378 2379 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2380 u8 if_in_octets_high[0x20]; 2381 2382 u8 if_in_octets_low[0x20]; 2383 2384 u8 if_in_ucast_pkts_high[0x20]; 2385 2386 u8 if_in_ucast_pkts_low[0x20]; 2387 2388 u8 if_in_discards_high[0x20]; 2389 2390 u8 if_in_discards_low[0x20]; 2391 2392 u8 if_in_errors_high[0x20]; 2393 2394 u8 if_in_errors_low[0x20]; 2395 2396 u8 if_in_unknown_protos_high[0x20]; 2397 2398 u8 if_in_unknown_protos_low[0x20]; 2399 2400 u8 if_out_octets_high[0x20]; 2401 2402 u8 if_out_octets_low[0x20]; 2403 2404 u8 if_out_ucast_pkts_high[0x20]; 2405 2406 u8 if_out_ucast_pkts_low[0x20]; 2407 2408 u8 if_out_discards_high[0x20]; 2409 2410 u8 if_out_discards_low[0x20]; 2411 2412 u8 if_out_errors_high[0x20]; 2413 2414 u8 if_out_errors_low[0x20]; 2415 2416 u8 if_in_multicast_pkts_high[0x20]; 2417 2418 u8 if_in_multicast_pkts_low[0x20]; 2419 2420 u8 if_in_broadcast_pkts_high[0x20]; 2421 2422 u8 if_in_broadcast_pkts_low[0x20]; 2423 2424 u8 if_out_multicast_pkts_high[0x20]; 2425 2426 u8 if_out_multicast_pkts_low[0x20]; 2427 2428 u8 if_out_broadcast_pkts_high[0x20]; 2429 2430 u8 if_out_broadcast_pkts_low[0x20]; 2431 2432 u8 reserved_at_340[0x480]; 2433 }; 2434 2435 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2436 u8 a_frames_transmitted_ok_high[0x20]; 2437 2438 u8 a_frames_transmitted_ok_low[0x20]; 2439 2440 u8 a_frames_received_ok_high[0x20]; 2441 2442 u8 a_frames_received_ok_low[0x20]; 2443 2444 u8 a_frame_check_sequence_errors_high[0x20]; 2445 2446 u8 a_frame_check_sequence_errors_low[0x20]; 2447 2448 u8 a_alignment_errors_high[0x20]; 2449 2450 u8 a_alignment_errors_low[0x20]; 2451 2452 u8 a_octets_transmitted_ok_high[0x20]; 2453 2454 u8 a_octets_transmitted_ok_low[0x20]; 2455 2456 u8 a_octets_received_ok_high[0x20]; 2457 2458 u8 a_octets_received_ok_low[0x20]; 2459 2460 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2461 2462 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2463 2464 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2465 2466 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2467 2468 u8 a_multicast_frames_received_ok_high[0x20]; 2469 2470 u8 a_multicast_frames_received_ok_low[0x20]; 2471 2472 u8 a_broadcast_frames_received_ok_high[0x20]; 2473 2474 u8 a_broadcast_frames_received_ok_low[0x20]; 2475 2476 u8 a_in_range_length_errors_high[0x20]; 2477 2478 u8 a_in_range_length_errors_low[0x20]; 2479 2480 u8 a_out_of_range_length_field_high[0x20]; 2481 2482 u8 a_out_of_range_length_field_low[0x20]; 2483 2484 u8 a_frame_too_long_errors_high[0x20]; 2485 2486 u8 a_frame_too_long_errors_low[0x20]; 2487 2488 u8 a_symbol_error_during_carrier_high[0x20]; 2489 2490 u8 a_symbol_error_during_carrier_low[0x20]; 2491 2492 u8 a_mac_control_frames_transmitted_high[0x20]; 2493 2494 u8 a_mac_control_frames_transmitted_low[0x20]; 2495 2496 u8 a_mac_control_frames_received_high[0x20]; 2497 2498 u8 a_mac_control_frames_received_low[0x20]; 2499 2500 u8 a_unsupported_opcodes_received_high[0x20]; 2501 2502 u8 a_unsupported_opcodes_received_low[0x20]; 2503 2504 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2505 2506 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2507 2508 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2509 2510 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2511 2512 u8 reserved_at_4c0[0x300]; 2513 }; 2514 2515 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2516 u8 life_time_counter_high[0x20]; 2517 2518 u8 life_time_counter_low[0x20]; 2519 2520 u8 rx_errors[0x20]; 2521 2522 u8 tx_errors[0x20]; 2523 2524 u8 l0_to_recovery_eieos[0x20]; 2525 2526 u8 l0_to_recovery_ts[0x20]; 2527 2528 u8 l0_to_recovery_framing[0x20]; 2529 2530 u8 l0_to_recovery_retrain[0x20]; 2531 2532 u8 crc_error_dllp[0x20]; 2533 2534 u8 crc_error_tlp[0x20]; 2535 2536 u8 tx_overflow_buffer_pkt_high[0x20]; 2537 2538 u8 tx_overflow_buffer_pkt_low[0x20]; 2539 2540 u8 outbound_stalled_reads[0x20]; 2541 2542 u8 outbound_stalled_writes[0x20]; 2543 2544 u8 outbound_stalled_reads_events[0x20]; 2545 2546 u8 outbound_stalled_writes_events[0x20]; 2547 2548 u8 reserved_at_200[0x5c0]; 2549 }; 2550 2551 struct mlx5_ifc_cmd_inter_comp_event_bits { 2552 u8 command_completion_vector[0x20]; 2553 2554 u8 reserved_at_20[0xc0]; 2555 }; 2556 2557 struct mlx5_ifc_stall_vl_event_bits { 2558 u8 reserved_at_0[0x18]; 2559 u8 port_num[0x1]; 2560 u8 reserved_at_19[0x3]; 2561 u8 vl[0x4]; 2562 2563 u8 reserved_at_20[0xa0]; 2564 }; 2565 2566 struct mlx5_ifc_db_bf_congestion_event_bits { 2567 u8 event_subtype[0x8]; 2568 u8 reserved_at_8[0x8]; 2569 u8 congestion_level[0x8]; 2570 u8 reserved_at_18[0x8]; 2571 2572 u8 reserved_at_20[0xa0]; 2573 }; 2574 2575 struct mlx5_ifc_gpio_event_bits { 2576 u8 reserved_at_0[0x60]; 2577 2578 u8 gpio_event_hi[0x20]; 2579 2580 u8 gpio_event_lo[0x20]; 2581 2582 u8 reserved_at_a0[0x40]; 2583 }; 2584 2585 struct mlx5_ifc_port_state_change_event_bits { 2586 u8 reserved_at_0[0x40]; 2587 2588 u8 port_num[0x4]; 2589 u8 reserved_at_44[0x1c]; 2590 2591 u8 reserved_at_60[0x80]; 2592 }; 2593 2594 struct mlx5_ifc_dropped_packet_logged_bits { 2595 u8 reserved_at_0[0xe0]; 2596 }; 2597 2598 enum { 2599 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2600 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2601 }; 2602 2603 struct mlx5_ifc_cq_error_bits { 2604 u8 reserved_at_0[0x8]; 2605 u8 cqn[0x18]; 2606 2607 u8 reserved_at_20[0x20]; 2608 2609 u8 reserved_at_40[0x18]; 2610 u8 syndrome[0x8]; 2611 2612 u8 reserved_at_60[0x80]; 2613 }; 2614 2615 struct mlx5_ifc_rdma_page_fault_event_bits { 2616 u8 bytes_committed[0x20]; 2617 2618 u8 r_key[0x20]; 2619 2620 u8 reserved_at_40[0x10]; 2621 u8 packet_len[0x10]; 2622 2623 u8 rdma_op_len[0x20]; 2624 2625 u8 rdma_va[0x40]; 2626 2627 u8 reserved_at_c0[0x5]; 2628 u8 rdma[0x1]; 2629 u8 write[0x1]; 2630 u8 requestor[0x1]; 2631 u8 qp_number[0x18]; 2632 }; 2633 2634 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2635 u8 bytes_committed[0x20]; 2636 2637 u8 reserved_at_20[0x10]; 2638 u8 wqe_index[0x10]; 2639 2640 u8 reserved_at_40[0x10]; 2641 u8 len[0x10]; 2642 2643 u8 reserved_at_60[0x60]; 2644 2645 u8 reserved_at_c0[0x5]; 2646 u8 rdma[0x1]; 2647 u8 write_read[0x1]; 2648 u8 requestor[0x1]; 2649 u8 qpn[0x18]; 2650 }; 2651 2652 struct mlx5_ifc_qp_events_bits { 2653 u8 reserved_at_0[0xa0]; 2654 2655 u8 type[0x8]; 2656 u8 reserved_at_a8[0x18]; 2657 2658 u8 reserved_at_c0[0x8]; 2659 u8 qpn_rqn_sqn[0x18]; 2660 }; 2661 2662 struct mlx5_ifc_dct_events_bits { 2663 u8 reserved_at_0[0xc0]; 2664 2665 u8 reserved_at_c0[0x8]; 2666 u8 dct_number[0x18]; 2667 }; 2668 2669 struct mlx5_ifc_comp_event_bits { 2670 u8 reserved_at_0[0xc0]; 2671 2672 u8 reserved_at_c0[0x8]; 2673 u8 cq_number[0x18]; 2674 }; 2675 2676 enum { 2677 MLX5_QPC_STATE_RST = 0x0, 2678 MLX5_QPC_STATE_INIT = 0x1, 2679 MLX5_QPC_STATE_RTR = 0x2, 2680 MLX5_QPC_STATE_RTS = 0x3, 2681 MLX5_QPC_STATE_SQER = 0x4, 2682 MLX5_QPC_STATE_ERR = 0x6, 2683 MLX5_QPC_STATE_SQD = 0x7, 2684 MLX5_QPC_STATE_SUSPENDED = 0x9, 2685 }; 2686 2687 enum { 2688 MLX5_QPC_ST_RC = 0x0, 2689 MLX5_QPC_ST_UC = 0x1, 2690 MLX5_QPC_ST_UD = 0x2, 2691 MLX5_QPC_ST_XRC = 0x3, 2692 MLX5_QPC_ST_DCI = 0x5, 2693 MLX5_QPC_ST_QP0 = 0x7, 2694 MLX5_QPC_ST_QP1 = 0x8, 2695 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2696 MLX5_QPC_ST_REG_UMR = 0xc, 2697 }; 2698 2699 enum { 2700 MLX5_QPC_PM_STATE_ARMED = 0x0, 2701 MLX5_QPC_PM_STATE_REARM = 0x1, 2702 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2703 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2704 }; 2705 2706 enum { 2707 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2708 }; 2709 2710 enum { 2711 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2712 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2713 }; 2714 2715 enum { 2716 MLX5_QPC_MTU_256_BYTES = 0x1, 2717 MLX5_QPC_MTU_512_BYTES = 0x2, 2718 MLX5_QPC_MTU_1K_BYTES = 0x3, 2719 MLX5_QPC_MTU_2K_BYTES = 0x4, 2720 MLX5_QPC_MTU_4K_BYTES = 0x5, 2721 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2722 }; 2723 2724 enum { 2725 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2726 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2727 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2728 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2729 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2730 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2731 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2732 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2733 }; 2734 2735 enum { 2736 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2737 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2738 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2739 }; 2740 2741 enum { 2742 MLX5_QPC_CS_RES_DISABLE = 0x0, 2743 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2744 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2745 }; 2746 2747 struct mlx5_ifc_qpc_bits { 2748 u8 state[0x4]; 2749 u8 lag_tx_port_affinity[0x4]; 2750 u8 st[0x8]; 2751 u8 reserved_at_10[0x3]; 2752 u8 pm_state[0x2]; 2753 u8 reserved_at_15[0x1]; 2754 u8 req_e2e_credit_mode[0x2]; 2755 u8 offload_type[0x4]; 2756 u8 end_padding_mode[0x2]; 2757 u8 reserved_at_1e[0x2]; 2758 2759 u8 wq_signature[0x1]; 2760 u8 block_lb_mc[0x1]; 2761 u8 atomic_like_write_en[0x1]; 2762 u8 latency_sensitive[0x1]; 2763 u8 reserved_at_24[0x1]; 2764 u8 drain_sigerr[0x1]; 2765 u8 reserved_at_26[0x2]; 2766 u8 pd[0x18]; 2767 2768 u8 mtu[0x3]; 2769 u8 log_msg_max[0x5]; 2770 u8 reserved_at_48[0x1]; 2771 u8 log_rq_size[0x4]; 2772 u8 log_rq_stride[0x3]; 2773 u8 no_sq[0x1]; 2774 u8 log_sq_size[0x4]; 2775 u8 reserved_at_55[0x6]; 2776 u8 rlky[0x1]; 2777 u8 ulp_stateless_offload_mode[0x4]; 2778 2779 u8 counter_set_id[0x8]; 2780 u8 uar_page[0x18]; 2781 2782 u8 reserved_at_80[0x8]; 2783 u8 user_index[0x18]; 2784 2785 u8 reserved_at_a0[0x3]; 2786 u8 log_page_size[0x5]; 2787 u8 remote_qpn[0x18]; 2788 2789 struct mlx5_ifc_ads_bits primary_address_path; 2790 2791 struct mlx5_ifc_ads_bits secondary_address_path; 2792 2793 u8 log_ack_req_freq[0x4]; 2794 u8 reserved_at_384[0x4]; 2795 u8 log_sra_max[0x3]; 2796 u8 reserved_at_38b[0x2]; 2797 u8 retry_count[0x3]; 2798 u8 rnr_retry[0x3]; 2799 u8 reserved_at_393[0x1]; 2800 u8 fre[0x1]; 2801 u8 cur_rnr_retry[0x3]; 2802 u8 cur_retry_count[0x3]; 2803 u8 reserved_at_39b[0x5]; 2804 2805 u8 reserved_at_3a0[0x20]; 2806 2807 u8 reserved_at_3c0[0x8]; 2808 u8 next_send_psn[0x18]; 2809 2810 u8 reserved_at_3e0[0x8]; 2811 u8 cqn_snd[0x18]; 2812 2813 u8 reserved_at_400[0x8]; 2814 u8 deth_sqpn[0x18]; 2815 2816 u8 reserved_at_420[0x20]; 2817 2818 u8 reserved_at_440[0x8]; 2819 u8 last_acked_psn[0x18]; 2820 2821 u8 reserved_at_460[0x8]; 2822 u8 ssn[0x18]; 2823 2824 u8 reserved_at_480[0x8]; 2825 u8 log_rra_max[0x3]; 2826 u8 reserved_at_48b[0x1]; 2827 u8 atomic_mode[0x4]; 2828 u8 rre[0x1]; 2829 u8 rwe[0x1]; 2830 u8 rae[0x1]; 2831 u8 reserved_at_493[0x1]; 2832 u8 page_offset[0x6]; 2833 u8 reserved_at_49a[0x3]; 2834 u8 cd_slave_receive[0x1]; 2835 u8 cd_slave_send[0x1]; 2836 u8 cd_master[0x1]; 2837 2838 u8 reserved_at_4a0[0x3]; 2839 u8 min_rnr_nak[0x5]; 2840 u8 next_rcv_psn[0x18]; 2841 2842 u8 reserved_at_4c0[0x8]; 2843 u8 xrcd[0x18]; 2844 2845 u8 reserved_at_4e0[0x8]; 2846 u8 cqn_rcv[0x18]; 2847 2848 u8 dbr_addr[0x40]; 2849 2850 u8 q_key[0x20]; 2851 2852 u8 reserved_at_560[0x5]; 2853 u8 rq_type[0x3]; 2854 u8 srqn_rmpn_xrqn[0x18]; 2855 2856 u8 reserved_at_580[0x8]; 2857 u8 rmsn[0x18]; 2858 2859 u8 hw_sq_wqebb_counter[0x10]; 2860 u8 sw_sq_wqebb_counter[0x10]; 2861 2862 u8 hw_rq_counter[0x20]; 2863 2864 u8 sw_rq_counter[0x20]; 2865 2866 u8 reserved_at_600[0x20]; 2867 2868 u8 reserved_at_620[0xf]; 2869 u8 cgs[0x1]; 2870 u8 cs_req[0x8]; 2871 u8 cs_res[0x8]; 2872 2873 u8 dc_access_key[0x40]; 2874 2875 u8 reserved_at_680[0x3]; 2876 u8 dbr_umem_valid[0x1]; 2877 2878 u8 reserved_at_684[0xbc]; 2879 }; 2880 2881 struct mlx5_ifc_roce_addr_layout_bits { 2882 u8 source_l3_address[16][0x8]; 2883 2884 u8 reserved_at_80[0x3]; 2885 u8 vlan_valid[0x1]; 2886 u8 vlan_id[0xc]; 2887 u8 source_mac_47_32[0x10]; 2888 2889 u8 source_mac_31_0[0x20]; 2890 2891 u8 reserved_at_c0[0x14]; 2892 u8 roce_l3_type[0x4]; 2893 u8 roce_version[0x8]; 2894 2895 u8 reserved_at_e0[0x20]; 2896 }; 2897 2898 union mlx5_ifc_hca_cap_union_bits { 2899 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2900 struct mlx5_ifc_odp_cap_bits odp_cap; 2901 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2902 struct mlx5_ifc_roce_cap_bits roce_cap; 2903 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2904 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2905 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2906 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2907 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2908 struct mlx5_ifc_qos_cap_bits qos_cap; 2909 struct mlx5_ifc_debug_cap_bits debug_cap; 2910 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2911 struct mlx5_ifc_tls_cap_bits tls_cap; 2912 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2913 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap; 2914 u8 reserved_at_0[0x8000]; 2915 }; 2916 2917 enum { 2918 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2919 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2920 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2921 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2922 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2923 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2924 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2925 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2926 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2927 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2928 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2929 }; 2930 2931 enum { 2932 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2933 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2934 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2935 }; 2936 2937 struct mlx5_ifc_vlan_bits { 2938 u8 ethtype[0x10]; 2939 u8 prio[0x3]; 2940 u8 cfi[0x1]; 2941 u8 vid[0xc]; 2942 }; 2943 2944 struct mlx5_ifc_flow_context_bits { 2945 struct mlx5_ifc_vlan_bits push_vlan; 2946 2947 u8 group_id[0x20]; 2948 2949 u8 reserved_at_40[0x8]; 2950 u8 flow_tag[0x18]; 2951 2952 u8 reserved_at_60[0x10]; 2953 u8 action[0x10]; 2954 2955 u8 extended_destination[0x1]; 2956 u8 reserved_at_81[0x1]; 2957 u8 flow_source[0x2]; 2958 u8 reserved_at_84[0x4]; 2959 u8 destination_list_size[0x18]; 2960 2961 u8 reserved_at_a0[0x8]; 2962 u8 flow_counter_list_size[0x18]; 2963 2964 u8 packet_reformat_id[0x20]; 2965 2966 u8 modify_header_id[0x20]; 2967 2968 struct mlx5_ifc_vlan_bits push_vlan_2; 2969 2970 u8 reserved_at_120[0xe0]; 2971 2972 struct mlx5_ifc_fte_match_param_bits match_value; 2973 2974 u8 reserved_at_1200[0x600]; 2975 2976 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2977 }; 2978 2979 enum { 2980 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2981 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2982 }; 2983 2984 struct mlx5_ifc_xrc_srqc_bits { 2985 u8 state[0x4]; 2986 u8 log_xrc_srq_size[0x4]; 2987 u8 reserved_at_8[0x18]; 2988 2989 u8 wq_signature[0x1]; 2990 u8 cont_srq[0x1]; 2991 u8 reserved_at_22[0x1]; 2992 u8 rlky[0x1]; 2993 u8 basic_cyclic_rcv_wqe[0x1]; 2994 u8 log_rq_stride[0x3]; 2995 u8 xrcd[0x18]; 2996 2997 u8 page_offset[0x6]; 2998 u8 reserved_at_46[0x1]; 2999 u8 dbr_umem_valid[0x1]; 3000 u8 cqn[0x18]; 3001 3002 u8 reserved_at_60[0x20]; 3003 3004 u8 user_index_equal_xrc_srqn[0x1]; 3005 u8 reserved_at_81[0x1]; 3006 u8 log_page_size[0x6]; 3007 u8 user_index[0x18]; 3008 3009 u8 reserved_at_a0[0x20]; 3010 3011 u8 reserved_at_c0[0x8]; 3012 u8 pd[0x18]; 3013 3014 u8 lwm[0x10]; 3015 u8 wqe_cnt[0x10]; 3016 3017 u8 reserved_at_100[0x40]; 3018 3019 u8 db_record_addr_h[0x20]; 3020 3021 u8 db_record_addr_l[0x1e]; 3022 u8 reserved_at_17e[0x2]; 3023 3024 u8 reserved_at_180[0x80]; 3025 }; 3026 3027 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3028 u8 counter_error_queues[0x20]; 3029 3030 u8 total_error_queues[0x20]; 3031 3032 u8 send_queue_priority_update_flow[0x20]; 3033 3034 u8 reserved_at_60[0x20]; 3035 3036 u8 nic_receive_steering_discard[0x40]; 3037 3038 u8 receive_discard_vport_down[0x40]; 3039 3040 u8 transmit_discard_vport_down[0x40]; 3041 3042 u8 reserved_at_140[0xa0]; 3043 3044 u8 internal_rq_out_of_buffer[0x20]; 3045 3046 u8 reserved_at_200[0xe00]; 3047 }; 3048 3049 struct mlx5_ifc_traffic_counter_bits { 3050 u8 packets[0x40]; 3051 3052 u8 octets[0x40]; 3053 }; 3054 3055 struct mlx5_ifc_tisc_bits { 3056 u8 strict_lag_tx_port_affinity[0x1]; 3057 u8 tls_en[0x1]; 3058 u8 reserved_at_2[0x2]; 3059 u8 lag_tx_port_affinity[0x04]; 3060 3061 u8 reserved_at_8[0x4]; 3062 u8 prio[0x4]; 3063 u8 reserved_at_10[0x10]; 3064 3065 u8 reserved_at_20[0x100]; 3066 3067 u8 reserved_at_120[0x8]; 3068 u8 transport_domain[0x18]; 3069 3070 u8 reserved_at_140[0x8]; 3071 u8 underlay_qpn[0x18]; 3072 3073 u8 reserved_at_160[0x8]; 3074 u8 pd[0x18]; 3075 3076 u8 reserved_at_180[0x380]; 3077 }; 3078 3079 enum { 3080 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3081 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3082 }; 3083 3084 enum { 3085 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3086 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3087 }; 3088 3089 enum { 3090 MLX5_RX_HASH_FN_NONE = 0x0, 3091 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3092 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3093 }; 3094 3095 enum { 3096 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3097 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3098 }; 3099 3100 struct mlx5_ifc_tirc_bits { 3101 u8 reserved_at_0[0x20]; 3102 3103 u8 disp_type[0x4]; 3104 u8 reserved_at_24[0x1c]; 3105 3106 u8 reserved_at_40[0x40]; 3107 3108 u8 reserved_at_80[0x4]; 3109 u8 lro_timeout_period_usecs[0x10]; 3110 u8 lro_enable_mask[0x4]; 3111 u8 lro_max_ip_payload_size[0x8]; 3112 3113 u8 reserved_at_a0[0x40]; 3114 3115 u8 reserved_at_e0[0x8]; 3116 u8 inline_rqn[0x18]; 3117 3118 u8 rx_hash_symmetric[0x1]; 3119 u8 reserved_at_101[0x1]; 3120 u8 tunneled_offload_en[0x1]; 3121 u8 reserved_at_103[0x5]; 3122 u8 indirect_table[0x18]; 3123 3124 u8 rx_hash_fn[0x4]; 3125 u8 reserved_at_124[0x2]; 3126 u8 self_lb_block[0x2]; 3127 u8 transport_domain[0x18]; 3128 3129 u8 rx_hash_toeplitz_key[10][0x20]; 3130 3131 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3132 3133 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3134 3135 u8 reserved_at_2c0[0x4c0]; 3136 }; 3137 3138 enum { 3139 MLX5_SRQC_STATE_GOOD = 0x0, 3140 MLX5_SRQC_STATE_ERROR = 0x1, 3141 }; 3142 3143 struct mlx5_ifc_srqc_bits { 3144 u8 state[0x4]; 3145 u8 log_srq_size[0x4]; 3146 u8 reserved_at_8[0x18]; 3147 3148 u8 wq_signature[0x1]; 3149 u8 cont_srq[0x1]; 3150 u8 reserved_at_22[0x1]; 3151 u8 rlky[0x1]; 3152 u8 reserved_at_24[0x1]; 3153 u8 log_rq_stride[0x3]; 3154 u8 xrcd[0x18]; 3155 3156 u8 page_offset[0x6]; 3157 u8 reserved_at_46[0x2]; 3158 u8 cqn[0x18]; 3159 3160 u8 reserved_at_60[0x20]; 3161 3162 u8 reserved_at_80[0x2]; 3163 u8 log_page_size[0x6]; 3164 u8 reserved_at_88[0x18]; 3165 3166 u8 reserved_at_a0[0x20]; 3167 3168 u8 reserved_at_c0[0x8]; 3169 u8 pd[0x18]; 3170 3171 u8 lwm[0x10]; 3172 u8 wqe_cnt[0x10]; 3173 3174 u8 reserved_at_100[0x40]; 3175 3176 u8 dbr_addr[0x40]; 3177 3178 u8 reserved_at_180[0x80]; 3179 }; 3180 3181 enum { 3182 MLX5_SQC_STATE_RST = 0x0, 3183 MLX5_SQC_STATE_RDY = 0x1, 3184 MLX5_SQC_STATE_ERR = 0x3, 3185 }; 3186 3187 struct mlx5_ifc_sqc_bits { 3188 u8 rlky[0x1]; 3189 u8 cd_master[0x1]; 3190 u8 fre[0x1]; 3191 u8 flush_in_error_en[0x1]; 3192 u8 allow_multi_pkt_send_wqe[0x1]; 3193 u8 min_wqe_inline_mode[0x3]; 3194 u8 state[0x4]; 3195 u8 reg_umr[0x1]; 3196 u8 allow_swp[0x1]; 3197 u8 hairpin[0x1]; 3198 u8 reserved_at_f[0x11]; 3199 3200 u8 reserved_at_20[0x8]; 3201 u8 user_index[0x18]; 3202 3203 u8 reserved_at_40[0x8]; 3204 u8 cqn[0x18]; 3205 3206 u8 reserved_at_60[0x8]; 3207 u8 hairpin_peer_rq[0x18]; 3208 3209 u8 reserved_at_80[0x10]; 3210 u8 hairpin_peer_vhca[0x10]; 3211 3212 u8 reserved_at_a0[0x50]; 3213 3214 u8 packet_pacing_rate_limit_index[0x10]; 3215 u8 tis_lst_sz[0x10]; 3216 u8 reserved_at_110[0x10]; 3217 3218 u8 reserved_at_120[0x40]; 3219 3220 u8 reserved_at_160[0x8]; 3221 u8 tis_num_0[0x18]; 3222 3223 struct mlx5_ifc_wq_bits wq; 3224 }; 3225 3226 enum { 3227 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3228 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3229 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3230 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3231 }; 3232 3233 enum { 3234 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3235 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3236 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3237 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3238 }; 3239 3240 struct mlx5_ifc_scheduling_context_bits { 3241 u8 element_type[0x8]; 3242 u8 reserved_at_8[0x18]; 3243 3244 u8 element_attributes[0x20]; 3245 3246 u8 parent_element_id[0x20]; 3247 3248 u8 reserved_at_60[0x40]; 3249 3250 u8 bw_share[0x20]; 3251 3252 u8 max_average_bw[0x20]; 3253 3254 u8 reserved_at_e0[0x120]; 3255 }; 3256 3257 struct mlx5_ifc_rqtc_bits { 3258 u8 reserved_at_0[0xa0]; 3259 3260 u8 reserved_at_a0[0x10]; 3261 u8 rqt_max_size[0x10]; 3262 3263 u8 reserved_at_c0[0x10]; 3264 u8 rqt_actual_size[0x10]; 3265 3266 u8 reserved_at_e0[0x6a0]; 3267 3268 struct mlx5_ifc_rq_num_bits rq_num[0]; 3269 }; 3270 3271 enum { 3272 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3273 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3274 }; 3275 3276 enum { 3277 MLX5_RQC_STATE_RST = 0x0, 3278 MLX5_RQC_STATE_RDY = 0x1, 3279 MLX5_RQC_STATE_ERR = 0x3, 3280 }; 3281 3282 struct mlx5_ifc_rqc_bits { 3283 u8 rlky[0x1]; 3284 u8 delay_drop_en[0x1]; 3285 u8 scatter_fcs[0x1]; 3286 u8 vsd[0x1]; 3287 u8 mem_rq_type[0x4]; 3288 u8 state[0x4]; 3289 u8 reserved_at_c[0x1]; 3290 u8 flush_in_error_en[0x1]; 3291 u8 hairpin[0x1]; 3292 u8 reserved_at_f[0x11]; 3293 3294 u8 reserved_at_20[0x8]; 3295 u8 user_index[0x18]; 3296 3297 u8 reserved_at_40[0x8]; 3298 u8 cqn[0x18]; 3299 3300 u8 counter_set_id[0x8]; 3301 u8 reserved_at_68[0x18]; 3302 3303 u8 reserved_at_80[0x8]; 3304 u8 rmpn[0x18]; 3305 3306 u8 reserved_at_a0[0x8]; 3307 u8 hairpin_peer_sq[0x18]; 3308 3309 u8 reserved_at_c0[0x10]; 3310 u8 hairpin_peer_vhca[0x10]; 3311 3312 u8 reserved_at_e0[0xa0]; 3313 3314 struct mlx5_ifc_wq_bits wq; 3315 }; 3316 3317 enum { 3318 MLX5_RMPC_STATE_RDY = 0x1, 3319 MLX5_RMPC_STATE_ERR = 0x3, 3320 }; 3321 3322 struct mlx5_ifc_rmpc_bits { 3323 u8 reserved_at_0[0x8]; 3324 u8 state[0x4]; 3325 u8 reserved_at_c[0x14]; 3326 3327 u8 basic_cyclic_rcv_wqe[0x1]; 3328 u8 reserved_at_21[0x1f]; 3329 3330 u8 reserved_at_40[0x140]; 3331 3332 struct mlx5_ifc_wq_bits wq; 3333 }; 3334 3335 struct mlx5_ifc_nic_vport_context_bits { 3336 u8 reserved_at_0[0x5]; 3337 u8 min_wqe_inline_mode[0x3]; 3338 u8 reserved_at_8[0x15]; 3339 u8 disable_mc_local_lb[0x1]; 3340 u8 disable_uc_local_lb[0x1]; 3341 u8 roce_en[0x1]; 3342 3343 u8 arm_change_event[0x1]; 3344 u8 reserved_at_21[0x1a]; 3345 u8 event_on_mtu[0x1]; 3346 u8 event_on_promisc_change[0x1]; 3347 u8 event_on_vlan_change[0x1]; 3348 u8 event_on_mc_address_change[0x1]; 3349 u8 event_on_uc_address_change[0x1]; 3350 3351 u8 reserved_at_40[0xc]; 3352 3353 u8 affiliation_criteria[0x4]; 3354 u8 affiliated_vhca_id[0x10]; 3355 3356 u8 reserved_at_60[0xd0]; 3357 3358 u8 mtu[0x10]; 3359 3360 u8 system_image_guid[0x40]; 3361 u8 port_guid[0x40]; 3362 u8 node_guid[0x40]; 3363 3364 u8 reserved_at_200[0x140]; 3365 u8 qkey_violation_counter[0x10]; 3366 u8 reserved_at_350[0x430]; 3367 3368 u8 promisc_uc[0x1]; 3369 u8 promisc_mc[0x1]; 3370 u8 promisc_all[0x1]; 3371 u8 reserved_at_783[0x2]; 3372 u8 allowed_list_type[0x3]; 3373 u8 reserved_at_788[0xc]; 3374 u8 allowed_list_size[0xc]; 3375 3376 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3377 3378 u8 reserved_at_7e0[0x20]; 3379 3380 u8 current_uc_mac_address[0][0x40]; 3381 }; 3382 3383 enum { 3384 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3385 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3386 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3387 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3388 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3389 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3390 }; 3391 3392 struct mlx5_ifc_mkc_bits { 3393 u8 reserved_at_0[0x1]; 3394 u8 free[0x1]; 3395 u8 reserved_at_2[0x1]; 3396 u8 access_mode_4_2[0x3]; 3397 u8 reserved_at_6[0x7]; 3398 u8 relaxed_ordering_write[0x1]; 3399 u8 reserved_at_e[0x1]; 3400 u8 small_fence_on_rdma_read_response[0x1]; 3401 u8 umr_en[0x1]; 3402 u8 a[0x1]; 3403 u8 rw[0x1]; 3404 u8 rr[0x1]; 3405 u8 lw[0x1]; 3406 u8 lr[0x1]; 3407 u8 access_mode_1_0[0x2]; 3408 u8 reserved_at_18[0x8]; 3409 3410 u8 qpn[0x18]; 3411 u8 mkey_7_0[0x8]; 3412 3413 u8 reserved_at_40[0x20]; 3414 3415 u8 length64[0x1]; 3416 u8 bsf_en[0x1]; 3417 u8 sync_umr[0x1]; 3418 u8 reserved_at_63[0x2]; 3419 u8 expected_sigerr_count[0x1]; 3420 u8 reserved_at_66[0x1]; 3421 u8 en_rinval[0x1]; 3422 u8 pd[0x18]; 3423 3424 u8 start_addr[0x40]; 3425 3426 u8 len[0x40]; 3427 3428 u8 bsf_octword_size[0x20]; 3429 3430 u8 reserved_at_120[0x80]; 3431 3432 u8 translations_octword_size[0x20]; 3433 3434 u8 reserved_at_1c0[0x19]; 3435 u8 relaxed_ordering_read[0x1]; 3436 u8 reserved_at_1d9[0x1]; 3437 u8 log_page_size[0x5]; 3438 3439 u8 reserved_at_1e0[0x20]; 3440 }; 3441 3442 struct mlx5_ifc_pkey_bits { 3443 u8 reserved_at_0[0x10]; 3444 u8 pkey[0x10]; 3445 }; 3446 3447 struct mlx5_ifc_array128_auto_bits { 3448 u8 array128_auto[16][0x8]; 3449 }; 3450 3451 struct mlx5_ifc_hca_vport_context_bits { 3452 u8 field_select[0x20]; 3453 3454 u8 reserved_at_20[0xe0]; 3455 3456 u8 sm_virt_aware[0x1]; 3457 u8 has_smi[0x1]; 3458 u8 has_raw[0x1]; 3459 u8 grh_required[0x1]; 3460 u8 reserved_at_104[0xc]; 3461 u8 port_physical_state[0x4]; 3462 u8 vport_state_policy[0x4]; 3463 u8 port_state[0x4]; 3464 u8 vport_state[0x4]; 3465 3466 u8 reserved_at_120[0x20]; 3467 3468 u8 system_image_guid[0x40]; 3469 3470 u8 port_guid[0x40]; 3471 3472 u8 node_guid[0x40]; 3473 3474 u8 cap_mask1[0x20]; 3475 3476 u8 cap_mask1_field_select[0x20]; 3477 3478 u8 cap_mask2[0x20]; 3479 3480 u8 cap_mask2_field_select[0x20]; 3481 3482 u8 reserved_at_280[0x80]; 3483 3484 u8 lid[0x10]; 3485 u8 reserved_at_310[0x4]; 3486 u8 init_type_reply[0x4]; 3487 u8 lmc[0x3]; 3488 u8 subnet_timeout[0x5]; 3489 3490 u8 sm_lid[0x10]; 3491 u8 sm_sl[0x4]; 3492 u8 reserved_at_334[0xc]; 3493 3494 u8 qkey_violation_counter[0x10]; 3495 u8 pkey_violation_counter[0x10]; 3496 3497 u8 reserved_at_360[0xca0]; 3498 }; 3499 3500 struct mlx5_ifc_esw_vport_context_bits { 3501 u8 fdb_to_vport_reg_c[0x1]; 3502 u8 reserved_at_1[0x2]; 3503 u8 vport_svlan_strip[0x1]; 3504 u8 vport_cvlan_strip[0x1]; 3505 u8 vport_svlan_insert[0x1]; 3506 u8 vport_cvlan_insert[0x2]; 3507 u8 fdb_to_vport_reg_c_id[0x8]; 3508 u8 reserved_at_10[0x10]; 3509 3510 u8 reserved_at_20[0x20]; 3511 3512 u8 svlan_cfi[0x1]; 3513 u8 svlan_pcp[0x3]; 3514 u8 svlan_id[0xc]; 3515 u8 cvlan_cfi[0x1]; 3516 u8 cvlan_pcp[0x3]; 3517 u8 cvlan_id[0xc]; 3518 3519 u8 reserved_at_60[0x720]; 3520 3521 u8 sw_steering_vport_icm_address_rx[0x40]; 3522 3523 u8 sw_steering_vport_icm_address_tx[0x40]; 3524 }; 3525 3526 enum { 3527 MLX5_EQC_STATUS_OK = 0x0, 3528 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3529 }; 3530 3531 enum { 3532 MLX5_EQC_ST_ARMED = 0x9, 3533 MLX5_EQC_ST_FIRED = 0xa, 3534 }; 3535 3536 struct mlx5_ifc_eqc_bits { 3537 u8 status[0x4]; 3538 u8 reserved_at_4[0x9]; 3539 u8 ec[0x1]; 3540 u8 oi[0x1]; 3541 u8 reserved_at_f[0x5]; 3542 u8 st[0x4]; 3543 u8 reserved_at_18[0x8]; 3544 3545 u8 reserved_at_20[0x20]; 3546 3547 u8 reserved_at_40[0x14]; 3548 u8 page_offset[0x6]; 3549 u8 reserved_at_5a[0x6]; 3550 3551 u8 reserved_at_60[0x3]; 3552 u8 log_eq_size[0x5]; 3553 u8 uar_page[0x18]; 3554 3555 u8 reserved_at_80[0x20]; 3556 3557 u8 reserved_at_a0[0x18]; 3558 u8 intr[0x8]; 3559 3560 u8 reserved_at_c0[0x3]; 3561 u8 log_page_size[0x5]; 3562 u8 reserved_at_c8[0x18]; 3563 3564 u8 reserved_at_e0[0x60]; 3565 3566 u8 reserved_at_140[0x8]; 3567 u8 consumer_counter[0x18]; 3568 3569 u8 reserved_at_160[0x8]; 3570 u8 producer_counter[0x18]; 3571 3572 u8 reserved_at_180[0x80]; 3573 }; 3574 3575 enum { 3576 MLX5_DCTC_STATE_ACTIVE = 0x0, 3577 MLX5_DCTC_STATE_DRAINING = 0x1, 3578 MLX5_DCTC_STATE_DRAINED = 0x2, 3579 }; 3580 3581 enum { 3582 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3583 MLX5_DCTC_CS_RES_NA = 0x1, 3584 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3585 }; 3586 3587 enum { 3588 MLX5_DCTC_MTU_256_BYTES = 0x1, 3589 MLX5_DCTC_MTU_512_BYTES = 0x2, 3590 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3591 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3592 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3593 }; 3594 3595 struct mlx5_ifc_dctc_bits { 3596 u8 reserved_at_0[0x4]; 3597 u8 state[0x4]; 3598 u8 reserved_at_8[0x18]; 3599 3600 u8 reserved_at_20[0x8]; 3601 u8 user_index[0x18]; 3602 3603 u8 reserved_at_40[0x8]; 3604 u8 cqn[0x18]; 3605 3606 u8 counter_set_id[0x8]; 3607 u8 atomic_mode[0x4]; 3608 u8 rre[0x1]; 3609 u8 rwe[0x1]; 3610 u8 rae[0x1]; 3611 u8 atomic_like_write_en[0x1]; 3612 u8 latency_sensitive[0x1]; 3613 u8 rlky[0x1]; 3614 u8 free_ar[0x1]; 3615 u8 reserved_at_73[0xd]; 3616 3617 u8 reserved_at_80[0x8]; 3618 u8 cs_res[0x8]; 3619 u8 reserved_at_90[0x3]; 3620 u8 min_rnr_nak[0x5]; 3621 u8 reserved_at_98[0x8]; 3622 3623 u8 reserved_at_a0[0x8]; 3624 u8 srqn_xrqn[0x18]; 3625 3626 u8 reserved_at_c0[0x8]; 3627 u8 pd[0x18]; 3628 3629 u8 tclass[0x8]; 3630 u8 reserved_at_e8[0x4]; 3631 u8 flow_label[0x14]; 3632 3633 u8 dc_access_key[0x40]; 3634 3635 u8 reserved_at_140[0x5]; 3636 u8 mtu[0x3]; 3637 u8 port[0x8]; 3638 u8 pkey_index[0x10]; 3639 3640 u8 reserved_at_160[0x8]; 3641 u8 my_addr_index[0x8]; 3642 u8 reserved_at_170[0x8]; 3643 u8 hop_limit[0x8]; 3644 3645 u8 dc_access_key_violation_count[0x20]; 3646 3647 u8 reserved_at_1a0[0x14]; 3648 u8 dei_cfi[0x1]; 3649 u8 eth_prio[0x3]; 3650 u8 ecn[0x2]; 3651 u8 dscp[0x6]; 3652 3653 u8 reserved_at_1c0[0x40]; 3654 }; 3655 3656 enum { 3657 MLX5_CQC_STATUS_OK = 0x0, 3658 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3659 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3660 }; 3661 3662 enum { 3663 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3664 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3665 }; 3666 3667 enum { 3668 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3669 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3670 MLX5_CQC_ST_FIRED = 0xa, 3671 }; 3672 3673 enum { 3674 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3675 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3676 MLX5_CQ_PERIOD_NUM_MODES 3677 }; 3678 3679 struct mlx5_ifc_cqc_bits { 3680 u8 status[0x4]; 3681 u8 reserved_at_4[0x2]; 3682 u8 dbr_umem_valid[0x1]; 3683 u8 reserved_at_7[0x1]; 3684 u8 cqe_sz[0x3]; 3685 u8 cc[0x1]; 3686 u8 reserved_at_c[0x1]; 3687 u8 scqe_break_moderation_en[0x1]; 3688 u8 oi[0x1]; 3689 u8 cq_period_mode[0x2]; 3690 u8 cqe_comp_en[0x1]; 3691 u8 mini_cqe_res_format[0x2]; 3692 u8 st[0x4]; 3693 u8 reserved_at_18[0x8]; 3694 3695 u8 reserved_at_20[0x20]; 3696 3697 u8 reserved_at_40[0x14]; 3698 u8 page_offset[0x6]; 3699 u8 reserved_at_5a[0x6]; 3700 3701 u8 reserved_at_60[0x3]; 3702 u8 log_cq_size[0x5]; 3703 u8 uar_page[0x18]; 3704 3705 u8 reserved_at_80[0x4]; 3706 u8 cq_period[0xc]; 3707 u8 cq_max_count[0x10]; 3708 3709 u8 reserved_at_a0[0x18]; 3710 u8 c_eqn[0x8]; 3711 3712 u8 reserved_at_c0[0x3]; 3713 u8 log_page_size[0x5]; 3714 u8 reserved_at_c8[0x18]; 3715 3716 u8 reserved_at_e0[0x20]; 3717 3718 u8 reserved_at_100[0x8]; 3719 u8 last_notified_index[0x18]; 3720 3721 u8 reserved_at_120[0x8]; 3722 u8 last_solicit_index[0x18]; 3723 3724 u8 reserved_at_140[0x8]; 3725 u8 consumer_counter[0x18]; 3726 3727 u8 reserved_at_160[0x8]; 3728 u8 producer_counter[0x18]; 3729 3730 u8 reserved_at_180[0x40]; 3731 3732 u8 dbr_addr[0x40]; 3733 }; 3734 3735 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3736 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3737 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3738 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3739 u8 reserved_at_0[0x800]; 3740 }; 3741 3742 struct mlx5_ifc_query_adapter_param_block_bits { 3743 u8 reserved_at_0[0xc0]; 3744 3745 u8 reserved_at_c0[0x8]; 3746 u8 ieee_vendor_id[0x18]; 3747 3748 u8 reserved_at_e0[0x10]; 3749 u8 vsd_vendor_id[0x10]; 3750 3751 u8 vsd[208][0x8]; 3752 3753 u8 vsd_contd_psid[16][0x8]; 3754 }; 3755 3756 enum { 3757 MLX5_XRQC_STATE_GOOD = 0x0, 3758 MLX5_XRQC_STATE_ERROR = 0x1, 3759 }; 3760 3761 enum { 3762 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3763 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3764 }; 3765 3766 enum { 3767 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3768 }; 3769 3770 struct mlx5_ifc_tag_matching_topology_context_bits { 3771 u8 log_matching_list_sz[0x4]; 3772 u8 reserved_at_4[0xc]; 3773 u8 append_next_index[0x10]; 3774 3775 u8 sw_phase_cnt[0x10]; 3776 u8 hw_phase_cnt[0x10]; 3777 3778 u8 reserved_at_40[0x40]; 3779 }; 3780 3781 struct mlx5_ifc_xrqc_bits { 3782 u8 state[0x4]; 3783 u8 rlkey[0x1]; 3784 u8 reserved_at_5[0xf]; 3785 u8 topology[0x4]; 3786 u8 reserved_at_18[0x4]; 3787 u8 offload[0x4]; 3788 3789 u8 reserved_at_20[0x8]; 3790 u8 user_index[0x18]; 3791 3792 u8 reserved_at_40[0x8]; 3793 u8 cqn[0x18]; 3794 3795 u8 reserved_at_60[0xa0]; 3796 3797 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3798 3799 u8 reserved_at_180[0x280]; 3800 3801 struct mlx5_ifc_wq_bits wq; 3802 }; 3803 3804 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3805 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3806 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3807 u8 reserved_at_0[0x20]; 3808 }; 3809 3810 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3811 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3812 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3813 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3814 u8 reserved_at_0[0x20]; 3815 }; 3816 3817 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3818 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3819 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3820 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3821 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3822 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3823 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3824 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3825 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3826 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3827 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3828 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3829 u8 reserved_at_0[0x7c0]; 3830 }; 3831 3832 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3833 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3834 u8 reserved_at_0[0x7c0]; 3835 }; 3836 3837 union mlx5_ifc_event_auto_bits { 3838 struct mlx5_ifc_comp_event_bits comp_event; 3839 struct mlx5_ifc_dct_events_bits dct_events; 3840 struct mlx5_ifc_qp_events_bits qp_events; 3841 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3842 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3843 struct mlx5_ifc_cq_error_bits cq_error; 3844 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3845 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3846 struct mlx5_ifc_gpio_event_bits gpio_event; 3847 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3848 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3849 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3850 u8 reserved_at_0[0xe0]; 3851 }; 3852 3853 struct mlx5_ifc_health_buffer_bits { 3854 u8 reserved_at_0[0x100]; 3855 3856 u8 assert_existptr[0x20]; 3857 3858 u8 assert_callra[0x20]; 3859 3860 u8 reserved_at_140[0x40]; 3861 3862 u8 fw_version[0x20]; 3863 3864 u8 hw_id[0x20]; 3865 3866 u8 reserved_at_1c0[0x20]; 3867 3868 u8 irisc_index[0x8]; 3869 u8 synd[0x8]; 3870 u8 ext_synd[0x10]; 3871 }; 3872 3873 struct mlx5_ifc_register_loopback_control_bits { 3874 u8 no_lb[0x1]; 3875 u8 reserved_at_1[0x7]; 3876 u8 port[0x8]; 3877 u8 reserved_at_10[0x10]; 3878 3879 u8 reserved_at_20[0x60]; 3880 }; 3881 3882 struct mlx5_ifc_vport_tc_element_bits { 3883 u8 traffic_class[0x4]; 3884 u8 reserved_at_4[0xc]; 3885 u8 vport_number[0x10]; 3886 }; 3887 3888 struct mlx5_ifc_vport_element_bits { 3889 u8 reserved_at_0[0x10]; 3890 u8 vport_number[0x10]; 3891 }; 3892 3893 enum { 3894 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3895 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3896 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3897 }; 3898 3899 struct mlx5_ifc_tsar_element_bits { 3900 u8 reserved_at_0[0x8]; 3901 u8 tsar_type[0x8]; 3902 u8 reserved_at_10[0x10]; 3903 }; 3904 3905 enum { 3906 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3907 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3908 }; 3909 3910 struct mlx5_ifc_teardown_hca_out_bits { 3911 u8 status[0x8]; 3912 u8 reserved_at_8[0x18]; 3913 3914 u8 syndrome[0x20]; 3915 3916 u8 reserved_at_40[0x3f]; 3917 3918 u8 state[0x1]; 3919 }; 3920 3921 enum { 3922 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3923 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3924 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3925 }; 3926 3927 struct mlx5_ifc_teardown_hca_in_bits { 3928 u8 opcode[0x10]; 3929 u8 reserved_at_10[0x10]; 3930 3931 u8 reserved_at_20[0x10]; 3932 u8 op_mod[0x10]; 3933 3934 u8 reserved_at_40[0x10]; 3935 u8 profile[0x10]; 3936 3937 u8 reserved_at_60[0x20]; 3938 }; 3939 3940 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3941 u8 status[0x8]; 3942 u8 reserved_at_8[0x18]; 3943 3944 u8 syndrome[0x20]; 3945 3946 u8 reserved_at_40[0x40]; 3947 }; 3948 3949 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3950 u8 opcode[0x10]; 3951 u8 uid[0x10]; 3952 3953 u8 reserved_at_20[0x10]; 3954 u8 op_mod[0x10]; 3955 3956 u8 reserved_at_40[0x8]; 3957 u8 qpn[0x18]; 3958 3959 u8 reserved_at_60[0x20]; 3960 3961 u8 opt_param_mask[0x20]; 3962 3963 u8 reserved_at_a0[0x20]; 3964 3965 struct mlx5_ifc_qpc_bits qpc; 3966 3967 u8 reserved_at_800[0x80]; 3968 }; 3969 3970 struct mlx5_ifc_sqd2rts_qp_out_bits { 3971 u8 status[0x8]; 3972 u8 reserved_at_8[0x18]; 3973 3974 u8 syndrome[0x20]; 3975 3976 u8 reserved_at_40[0x40]; 3977 }; 3978 3979 struct mlx5_ifc_sqd2rts_qp_in_bits { 3980 u8 opcode[0x10]; 3981 u8 uid[0x10]; 3982 3983 u8 reserved_at_20[0x10]; 3984 u8 op_mod[0x10]; 3985 3986 u8 reserved_at_40[0x8]; 3987 u8 qpn[0x18]; 3988 3989 u8 reserved_at_60[0x20]; 3990 3991 u8 opt_param_mask[0x20]; 3992 3993 u8 reserved_at_a0[0x20]; 3994 3995 struct mlx5_ifc_qpc_bits qpc; 3996 3997 u8 reserved_at_800[0x80]; 3998 }; 3999 4000 struct mlx5_ifc_set_roce_address_out_bits { 4001 u8 status[0x8]; 4002 u8 reserved_at_8[0x18]; 4003 4004 u8 syndrome[0x20]; 4005 4006 u8 reserved_at_40[0x40]; 4007 }; 4008 4009 struct mlx5_ifc_set_roce_address_in_bits { 4010 u8 opcode[0x10]; 4011 u8 reserved_at_10[0x10]; 4012 4013 u8 reserved_at_20[0x10]; 4014 u8 op_mod[0x10]; 4015 4016 u8 roce_address_index[0x10]; 4017 u8 reserved_at_50[0xc]; 4018 u8 vhca_port_num[0x4]; 4019 4020 u8 reserved_at_60[0x20]; 4021 4022 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4023 }; 4024 4025 struct mlx5_ifc_set_mad_demux_out_bits { 4026 u8 status[0x8]; 4027 u8 reserved_at_8[0x18]; 4028 4029 u8 syndrome[0x20]; 4030 4031 u8 reserved_at_40[0x40]; 4032 }; 4033 4034 enum { 4035 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4036 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4037 }; 4038 4039 struct mlx5_ifc_set_mad_demux_in_bits { 4040 u8 opcode[0x10]; 4041 u8 reserved_at_10[0x10]; 4042 4043 u8 reserved_at_20[0x10]; 4044 u8 op_mod[0x10]; 4045 4046 u8 reserved_at_40[0x20]; 4047 4048 u8 reserved_at_60[0x6]; 4049 u8 demux_mode[0x2]; 4050 u8 reserved_at_68[0x18]; 4051 }; 4052 4053 struct mlx5_ifc_set_l2_table_entry_out_bits { 4054 u8 status[0x8]; 4055 u8 reserved_at_8[0x18]; 4056 4057 u8 syndrome[0x20]; 4058 4059 u8 reserved_at_40[0x40]; 4060 }; 4061 4062 struct mlx5_ifc_set_l2_table_entry_in_bits { 4063 u8 opcode[0x10]; 4064 u8 reserved_at_10[0x10]; 4065 4066 u8 reserved_at_20[0x10]; 4067 u8 op_mod[0x10]; 4068 4069 u8 reserved_at_40[0x60]; 4070 4071 u8 reserved_at_a0[0x8]; 4072 u8 table_index[0x18]; 4073 4074 u8 reserved_at_c0[0x20]; 4075 4076 u8 reserved_at_e0[0x13]; 4077 u8 vlan_valid[0x1]; 4078 u8 vlan[0xc]; 4079 4080 struct mlx5_ifc_mac_address_layout_bits mac_address; 4081 4082 u8 reserved_at_140[0xc0]; 4083 }; 4084 4085 struct mlx5_ifc_set_issi_out_bits { 4086 u8 status[0x8]; 4087 u8 reserved_at_8[0x18]; 4088 4089 u8 syndrome[0x20]; 4090 4091 u8 reserved_at_40[0x40]; 4092 }; 4093 4094 struct mlx5_ifc_set_issi_in_bits { 4095 u8 opcode[0x10]; 4096 u8 reserved_at_10[0x10]; 4097 4098 u8 reserved_at_20[0x10]; 4099 u8 op_mod[0x10]; 4100 4101 u8 reserved_at_40[0x10]; 4102 u8 current_issi[0x10]; 4103 4104 u8 reserved_at_60[0x20]; 4105 }; 4106 4107 struct mlx5_ifc_set_hca_cap_out_bits { 4108 u8 status[0x8]; 4109 u8 reserved_at_8[0x18]; 4110 4111 u8 syndrome[0x20]; 4112 4113 u8 reserved_at_40[0x40]; 4114 }; 4115 4116 struct mlx5_ifc_set_hca_cap_in_bits { 4117 u8 opcode[0x10]; 4118 u8 reserved_at_10[0x10]; 4119 4120 u8 reserved_at_20[0x10]; 4121 u8 op_mod[0x10]; 4122 4123 u8 reserved_at_40[0x40]; 4124 4125 union mlx5_ifc_hca_cap_union_bits capability; 4126 }; 4127 4128 enum { 4129 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4130 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4131 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4132 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 4133 }; 4134 4135 struct mlx5_ifc_set_fte_out_bits { 4136 u8 status[0x8]; 4137 u8 reserved_at_8[0x18]; 4138 4139 u8 syndrome[0x20]; 4140 4141 u8 reserved_at_40[0x40]; 4142 }; 4143 4144 struct mlx5_ifc_set_fte_in_bits { 4145 u8 opcode[0x10]; 4146 u8 reserved_at_10[0x10]; 4147 4148 u8 reserved_at_20[0x10]; 4149 u8 op_mod[0x10]; 4150 4151 u8 other_vport[0x1]; 4152 u8 reserved_at_41[0xf]; 4153 u8 vport_number[0x10]; 4154 4155 u8 reserved_at_60[0x20]; 4156 4157 u8 table_type[0x8]; 4158 u8 reserved_at_88[0x18]; 4159 4160 u8 reserved_at_a0[0x8]; 4161 u8 table_id[0x18]; 4162 4163 u8 ignore_flow_level[0x1]; 4164 u8 reserved_at_c1[0x17]; 4165 u8 modify_enable_mask[0x8]; 4166 4167 u8 reserved_at_e0[0x20]; 4168 4169 u8 flow_index[0x20]; 4170 4171 u8 reserved_at_120[0xe0]; 4172 4173 struct mlx5_ifc_flow_context_bits flow_context; 4174 }; 4175 4176 struct mlx5_ifc_rts2rts_qp_out_bits { 4177 u8 status[0x8]; 4178 u8 reserved_at_8[0x18]; 4179 4180 u8 syndrome[0x20]; 4181 4182 u8 reserved_at_40[0x40]; 4183 }; 4184 4185 struct mlx5_ifc_rts2rts_qp_in_bits { 4186 u8 opcode[0x10]; 4187 u8 uid[0x10]; 4188 4189 u8 reserved_at_20[0x10]; 4190 u8 op_mod[0x10]; 4191 4192 u8 reserved_at_40[0x8]; 4193 u8 qpn[0x18]; 4194 4195 u8 reserved_at_60[0x20]; 4196 4197 u8 opt_param_mask[0x20]; 4198 4199 u8 reserved_at_a0[0x20]; 4200 4201 struct mlx5_ifc_qpc_bits qpc; 4202 4203 u8 reserved_at_800[0x80]; 4204 }; 4205 4206 struct mlx5_ifc_rtr2rts_qp_out_bits { 4207 u8 status[0x8]; 4208 u8 reserved_at_8[0x18]; 4209 4210 u8 syndrome[0x20]; 4211 4212 u8 reserved_at_40[0x40]; 4213 }; 4214 4215 struct mlx5_ifc_rtr2rts_qp_in_bits { 4216 u8 opcode[0x10]; 4217 u8 uid[0x10]; 4218 4219 u8 reserved_at_20[0x10]; 4220 u8 op_mod[0x10]; 4221 4222 u8 reserved_at_40[0x8]; 4223 u8 qpn[0x18]; 4224 4225 u8 reserved_at_60[0x20]; 4226 4227 u8 opt_param_mask[0x20]; 4228 4229 u8 reserved_at_a0[0x20]; 4230 4231 struct mlx5_ifc_qpc_bits qpc; 4232 4233 u8 reserved_at_800[0x80]; 4234 }; 4235 4236 struct mlx5_ifc_rst2init_qp_out_bits { 4237 u8 status[0x8]; 4238 u8 reserved_at_8[0x18]; 4239 4240 u8 syndrome[0x20]; 4241 4242 u8 reserved_at_40[0x40]; 4243 }; 4244 4245 struct mlx5_ifc_rst2init_qp_in_bits { 4246 u8 opcode[0x10]; 4247 u8 uid[0x10]; 4248 4249 u8 reserved_at_20[0x10]; 4250 u8 op_mod[0x10]; 4251 4252 u8 reserved_at_40[0x8]; 4253 u8 qpn[0x18]; 4254 4255 u8 reserved_at_60[0x20]; 4256 4257 u8 opt_param_mask[0x20]; 4258 4259 u8 reserved_at_a0[0x20]; 4260 4261 struct mlx5_ifc_qpc_bits qpc; 4262 4263 u8 reserved_at_800[0x80]; 4264 }; 4265 4266 struct mlx5_ifc_query_xrq_out_bits { 4267 u8 status[0x8]; 4268 u8 reserved_at_8[0x18]; 4269 4270 u8 syndrome[0x20]; 4271 4272 u8 reserved_at_40[0x40]; 4273 4274 struct mlx5_ifc_xrqc_bits xrq_context; 4275 }; 4276 4277 struct mlx5_ifc_query_xrq_in_bits { 4278 u8 opcode[0x10]; 4279 u8 reserved_at_10[0x10]; 4280 4281 u8 reserved_at_20[0x10]; 4282 u8 op_mod[0x10]; 4283 4284 u8 reserved_at_40[0x8]; 4285 u8 xrqn[0x18]; 4286 4287 u8 reserved_at_60[0x20]; 4288 }; 4289 4290 struct mlx5_ifc_query_xrc_srq_out_bits { 4291 u8 status[0x8]; 4292 u8 reserved_at_8[0x18]; 4293 4294 u8 syndrome[0x20]; 4295 4296 u8 reserved_at_40[0x40]; 4297 4298 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4299 4300 u8 reserved_at_280[0x600]; 4301 4302 u8 pas[0][0x40]; 4303 }; 4304 4305 struct mlx5_ifc_query_xrc_srq_in_bits { 4306 u8 opcode[0x10]; 4307 u8 reserved_at_10[0x10]; 4308 4309 u8 reserved_at_20[0x10]; 4310 u8 op_mod[0x10]; 4311 4312 u8 reserved_at_40[0x8]; 4313 u8 xrc_srqn[0x18]; 4314 4315 u8 reserved_at_60[0x20]; 4316 }; 4317 4318 enum { 4319 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4320 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4321 }; 4322 4323 struct mlx5_ifc_query_vport_state_out_bits { 4324 u8 status[0x8]; 4325 u8 reserved_at_8[0x18]; 4326 4327 u8 syndrome[0x20]; 4328 4329 u8 reserved_at_40[0x20]; 4330 4331 u8 reserved_at_60[0x18]; 4332 u8 admin_state[0x4]; 4333 u8 state[0x4]; 4334 }; 4335 4336 enum { 4337 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4338 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4339 }; 4340 4341 struct mlx5_ifc_arm_monitor_counter_in_bits { 4342 u8 opcode[0x10]; 4343 u8 uid[0x10]; 4344 4345 u8 reserved_at_20[0x10]; 4346 u8 op_mod[0x10]; 4347 4348 u8 reserved_at_40[0x20]; 4349 4350 u8 reserved_at_60[0x20]; 4351 }; 4352 4353 struct mlx5_ifc_arm_monitor_counter_out_bits { 4354 u8 status[0x8]; 4355 u8 reserved_at_8[0x18]; 4356 4357 u8 syndrome[0x20]; 4358 4359 u8 reserved_at_40[0x40]; 4360 }; 4361 4362 enum { 4363 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4364 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4365 }; 4366 4367 enum mlx5_monitor_counter_ppcnt { 4368 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4369 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4370 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4371 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4372 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4373 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4374 }; 4375 4376 enum { 4377 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4378 }; 4379 4380 struct mlx5_ifc_monitor_counter_output_bits { 4381 u8 reserved_at_0[0x4]; 4382 u8 type[0x4]; 4383 u8 reserved_at_8[0x8]; 4384 u8 counter[0x10]; 4385 4386 u8 counter_group_id[0x20]; 4387 }; 4388 4389 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4390 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4391 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4392 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4393 4394 struct mlx5_ifc_set_monitor_counter_in_bits { 4395 u8 opcode[0x10]; 4396 u8 uid[0x10]; 4397 4398 u8 reserved_at_20[0x10]; 4399 u8 op_mod[0x10]; 4400 4401 u8 reserved_at_40[0x10]; 4402 u8 num_of_counters[0x10]; 4403 4404 u8 reserved_at_60[0x20]; 4405 4406 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4407 }; 4408 4409 struct mlx5_ifc_set_monitor_counter_out_bits { 4410 u8 status[0x8]; 4411 u8 reserved_at_8[0x18]; 4412 4413 u8 syndrome[0x20]; 4414 4415 u8 reserved_at_40[0x40]; 4416 }; 4417 4418 struct mlx5_ifc_query_vport_state_in_bits { 4419 u8 opcode[0x10]; 4420 u8 reserved_at_10[0x10]; 4421 4422 u8 reserved_at_20[0x10]; 4423 u8 op_mod[0x10]; 4424 4425 u8 other_vport[0x1]; 4426 u8 reserved_at_41[0xf]; 4427 u8 vport_number[0x10]; 4428 4429 u8 reserved_at_60[0x20]; 4430 }; 4431 4432 struct mlx5_ifc_query_vnic_env_out_bits { 4433 u8 status[0x8]; 4434 u8 reserved_at_8[0x18]; 4435 4436 u8 syndrome[0x20]; 4437 4438 u8 reserved_at_40[0x40]; 4439 4440 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4441 }; 4442 4443 enum { 4444 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4445 }; 4446 4447 struct mlx5_ifc_query_vnic_env_in_bits { 4448 u8 opcode[0x10]; 4449 u8 reserved_at_10[0x10]; 4450 4451 u8 reserved_at_20[0x10]; 4452 u8 op_mod[0x10]; 4453 4454 u8 other_vport[0x1]; 4455 u8 reserved_at_41[0xf]; 4456 u8 vport_number[0x10]; 4457 4458 u8 reserved_at_60[0x20]; 4459 }; 4460 4461 struct mlx5_ifc_query_vport_counter_out_bits { 4462 u8 status[0x8]; 4463 u8 reserved_at_8[0x18]; 4464 4465 u8 syndrome[0x20]; 4466 4467 u8 reserved_at_40[0x40]; 4468 4469 struct mlx5_ifc_traffic_counter_bits received_errors; 4470 4471 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4472 4473 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4474 4475 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4476 4477 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4478 4479 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4480 4481 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4482 4483 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4484 4485 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4486 4487 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4488 4489 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4490 4491 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4492 4493 u8 reserved_at_680[0xa00]; 4494 }; 4495 4496 enum { 4497 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4498 }; 4499 4500 struct mlx5_ifc_query_vport_counter_in_bits { 4501 u8 opcode[0x10]; 4502 u8 reserved_at_10[0x10]; 4503 4504 u8 reserved_at_20[0x10]; 4505 u8 op_mod[0x10]; 4506 4507 u8 other_vport[0x1]; 4508 u8 reserved_at_41[0xb]; 4509 u8 port_num[0x4]; 4510 u8 vport_number[0x10]; 4511 4512 u8 reserved_at_60[0x60]; 4513 4514 u8 clear[0x1]; 4515 u8 reserved_at_c1[0x1f]; 4516 4517 u8 reserved_at_e0[0x20]; 4518 }; 4519 4520 struct mlx5_ifc_query_tis_out_bits { 4521 u8 status[0x8]; 4522 u8 reserved_at_8[0x18]; 4523 4524 u8 syndrome[0x20]; 4525 4526 u8 reserved_at_40[0x40]; 4527 4528 struct mlx5_ifc_tisc_bits tis_context; 4529 }; 4530 4531 struct mlx5_ifc_query_tis_in_bits { 4532 u8 opcode[0x10]; 4533 u8 reserved_at_10[0x10]; 4534 4535 u8 reserved_at_20[0x10]; 4536 u8 op_mod[0x10]; 4537 4538 u8 reserved_at_40[0x8]; 4539 u8 tisn[0x18]; 4540 4541 u8 reserved_at_60[0x20]; 4542 }; 4543 4544 struct mlx5_ifc_query_tir_out_bits { 4545 u8 status[0x8]; 4546 u8 reserved_at_8[0x18]; 4547 4548 u8 syndrome[0x20]; 4549 4550 u8 reserved_at_40[0xc0]; 4551 4552 struct mlx5_ifc_tirc_bits tir_context; 4553 }; 4554 4555 struct mlx5_ifc_query_tir_in_bits { 4556 u8 opcode[0x10]; 4557 u8 reserved_at_10[0x10]; 4558 4559 u8 reserved_at_20[0x10]; 4560 u8 op_mod[0x10]; 4561 4562 u8 reserved_at_40[0x8]; 4563 u8 tirn[0x18]; 4564 4565 u8 reserved_at_60[0x20]; 4566 }; 4567 4568 struct mlx5_ifc_query_srq_out_bits { 4569 u8 status[0x8]; 4570 u8 reserved_at_8[0x18]; 4571 4572 u8 syndrome[0x20]; 4573 4574 u8 reserved_at_40[0x40]; 4575 4576 struct mlx5_ifc_srqc_bits srq_context_entry; 4577 4578 u8 reserved_at_280[0x600]; 4579 4580 u8 pas[0][0x40]; 4581 }; 4582 4583 struct mlx5_ifc_query_srq_in_bits { 4584 u8 opcode[0x10]; 4585 u8 reserved_at_10[0x10]; 4586 4587 u8 reserved_at_20[0x10]; 4588 u8 op_mod[0x10]; 4589 4590 u8 reserved_at_40[0x8]; 4591 u8 srqn[0x18]; 4592 4593 u8 reserved_at_60[0x20]; 4594 }; 4595 4596 struct mlx5_ifc_query_sq_out_bits { 4597 u8 status[0x8]; 4598 u8 reserved_at_8[0x18]; 4599 4600 u8 syndrome[0x20]; 4601 4602 u8 reserved_at_40[0xc0]; 4603 4604 struct mlx5_ifc_sqc_bits sq_context; 4605 }; 4606 4607 struct mlx5_ifc_query_sq_in_bits { 4608 u8 opcode[0x10]; 4609 u8 reserved_at_10[0x10]; 4610 4611 u8 reserved_at_20[0x10]; 4612 u8 op_mod[0x10]; 4613 4614 u8 reserved_at_40[0x8]; 4615 u8 sqn[0x18]; 4616 4617 u8 reserved_at_60[0x20]; 4618 }; 4619 4620 struct mlx5_ifc_query_special_contexts_out_bits { 4621 u8 status[0x8]; 4622 u8 reserved_at_8[0x18]; 4623 4624 u8 syndrome[0x20]; 4625 4626 u8 dump_fill_mkey[0x20]; 4627 4628 u8 resd_lkey[0x20]; 4629 4630 u8 null_mkey[0x20]; 4631 4632 u8 reserved_at_a0[0x60]; 4633 }; 4634 4635 struct mlx5_ifc_query_special_contexts_in_bits { 4636 u8 opcode[0x10]; 4637 u8 reserved_at_10[0x10]; 4638 4639 u8 reserved_at_20[0x10]; 4640 u8 op_mod[0x10]; 4641 4642 u8 reserved_at_40[0x40]; 4643 }; 4644 4645 struct mlx5_ifc_query_scheduling_element_out_bits { 4646 u8 opcode[0x10]; 4647 u8 reserved_at_10[0x10]; 4648 4649 u8 reserved_at_20[0x10]; 4650 u8 op_mod[0x10]; 4651 4652 u8 reserved_at_40[0xc0]; 4653 4654 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4655 4656 u8 reserved_at_300[0x100]; 4657 }; 4658 4659 enum { 4660 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4661 }; 4662 4663 struct mlx5_ifc_query_scheduling_element_in_bits { 4664 u8 opcode[0x10]; 4665 u8 reserved_at_10[0x10]; 4666 4667 u8 reserved_at_20[0x10]; 4668 u8 op_mod[0x10]; 4669 4670 u8 scheduling_hierarchy[0x8]; 4671 u8 reserved_at_48[0x18]; 4672 4673 u8 scheduling_element_id[0x20]; 4674 4675 u8 reserved_at_80[0x180]; 4676 }; 4677 4678 struct mlx5_ifc_query_rqt_out_bits { 4679 u8 status[0x8]; 4680 u8 reserved_at_8[0x18]; 4681 4682 u8 syndrome[0x20]; 4683 4684 u8 reserved_at_40[0xc0]; 4685 4686 struct mlx5_ifc_rqtc_bits rqt_context; 4687 }; 4688 4689 struct mlx5_ifc_query_rqt_in_bits { 4690 u8 opcode[0x10]; 4691 u8 reserved_at_10[0x10]; 4692 4693 u8 reserved_at_20[0x10]; 4694 u8 op_mod[0x10]; 4695 4696 u8 reserved_at_40[0x8]; 4697 u8 rqtn[0x18]; 4698 4699 u8 reserved_at_60[0x20]; 4700 }; 4701 4702 struct mlx5_ifc_query_rq_out_bits { 4703 u8 status[0x8]; 4704 u8 reserved_at_8[0x18]; 4705 4706 u8 syndrome[0x20]; 4707 4708 u8 reserved_at_40[0xc0]; 4709 4710 struct mlx5_ifc_rqc_bits rq_context; 4711 }; 4712 4713 struct mlx5_ifc_query_rq_in_bits { 4714 u8 opcode[0x10]; 4715 u8 reserved_at_10[0x10]; 4716 4717 u8 reserved_at_20[0x10]; 4718 u8 op_mod[0x10]; 4719 4720 u8 reserved_at_40[0x8]; 4721 u8 rqn[0x18]; 4722 4723 u8 reserved_at_60[0x20]; 4724 }; 4725 4726 struct mlx5_ifc_query_roce_address_out_bits { 4727 u8 status[0x8]; 4728 u8 reserved_at_8[0x18]; 4729 4730 u8 syndrome[0x20]; 4731 4732 u8 reserved_at_40[0x40]; 4733 4734 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4735 }; 4736 4737 struct mlx5_ifc_query_roce_address_in_bits { 4738 u8 opcode[0x10]; 4739 u8 reserved_at_10[0x10]; 4740 4741 u8 reserved_at_20[0x10]; 4742 u8 op_mod[0x10]; 4743 4744 u8 roce_address_index[0x10]; 4745 u8 reserved_at_50[0xc]; 4746 u8 vhca_port_num[0x4]; 4747 4748 u8 reserved_at_60[0x20]; 4749 }; 4750 4751 struct mlx5_ifc_query_rmp_out_bits { 4752 u8 status[0x8]; 4753 u8 reserved_at_8[0x18]; 4754 4755 u8 syndrome[0x20]; 4756 4757 u8 reserved_at_40[0xc0]; 4758 4759 struct mlx5_ifc_rmpc_bits rmp_context; 4760 }; 4761 4762 struct mlx5_ifc_query_rmp_in_bits { 4763 u8 opcode[0x10]; 4764 u8 reserved_at_10[0x10]; 4765 4766 u8 reserved_at_20[0x10]; 4767 u8 op_mod[0x10]; 4768 4769 u8 reserved_at_40[0x8]; 4770 u8 rmpn[0x18]; 4771 4772 u8 reserved_at_60[0x20]; 4773 }; 4774 4775 struct mlx5_ifc_query_qp_out_bits { 4776 u8 status[0x8]; 4777 u8 reserved_at_8[0x18]; 4778 4779 u8 syndrome[0x20]; 4780 4781 u8 reserved_at_40[0x40]; 4782 4783 u8 opt_param_mask[0x20]; 4784 4785 u8 reserved_at_a0[0x20]; 4786 4787 struct mlx5_ifc_qpc_bits qpc; 4788 4789 u8 reserved_at_800[0x80]; 4790 4791 u8 pas[0][0x40]; 4792 }; 4793 4794 struct mlx5_ifc_query_qp_in_bits { 4795 u8 opcode[0x10]; 4796 u8 reserved_at_10[0x10]; 4797 4798 u8 reserved_at_20[0x10]; 4799 u8 op_mod[0x10]; 4800 4801 u8 reserved_at_40[0x8]; 4802 u8 qpn[0x18]; 4803 4804 u8 reserved_at_60[0x20]; 4805 }; 4806 4807 struct mlx5_ifc_query_q_counter_out_bits { 4808 u8 status[0x8]; 4809 u8 reserved_at_8[0x18]; 4810 4811 u8 syndrome[0x20]; 4812 4813 u8 reserved_at_40[0x40]; 4814 4815 u8 rx_write_requests[0x20]; 4816 4817 u8 reserved_at_a0[0x20]; 4818 4819 u8 rx_read_requests[0x20]; 4820 4821 u8 reserved_at_e0[0x20]; 4822 4823 u8 rx_atomic_requests[0x20]; 4824 4825 u8 reserved_at_120[0x20]; 4826 4827 u8 rx_dct_connect[0x20]; 4828 4829 u8 reserved_at_160[0x20]; 4830 4831 u8 out_of_buffer[0x20]; 4832 4833 u8 reserved_at_1a0[0x20]; 4834 4835 u8 out_of_sequence[0x20]; 4836 4837 u8 reserved_at_1e0[0x20]; 4838 4839 u8 duplicate_request[0x20]; 4840 4841 u8 reserved_at_220[0x20]; 4842 4843 u8 rnr_nak_retry_err[0x20]; 4844 4845 u8 reserved_at_260[0x20]; 4846 4847 u8 packet_seq_err[0x20]; 4848 4849 u8 reserved_at_2a0[0x20]; 4850 4851 u8 implied_nak_seq_err[0x20]; 4852 4853 u8 reserved_at_2e0[0x20]; 4854 4855 u8 local_ack_timeout_err[0x20]; 4856 4857 u8 reserved_at_320[0xa0]; 4858 4859 u8 resp_local_length_error[0x20]; 4860 4861 u8 req_local_length_error[0x20]; 4862 4863 u8 resp_local_qp_error[0x20]; 4864 4865 u8 local_operation_error[0x20]; 4866 4867 u8 resp_local_protection[0x20]; 4868 4869 u8 req_local_protection[0x20]; 4870 4871 u8 resp_cqe_error[0x20]; 4872 4873 u8 req_cqe_error[0x20]; 4874 4875 u8 req_mw_binding[0x20]; 4876 4877 u8 req_bad_response[0x20]; 4878 4879 u8 req_remote_invalid_request[0x20]; 4880 4881 u8 resp_remote_invalid_request[0x20]; 4882 4883 u8 req_remote_access_errors[0x20]; 4884 4885 u8 resp_remote_access_errors[0x20]; 4886 4887 u8 req_remote_operation_errors[0x20]; 4888 4889 u8 req_transport_retries_exceeded[0x20]; 4890 4891 u8 cq_overflow[0x20]; 4892 4893 u8 resp_cqe_flush_error[0x20]; 4894 4895 u8 req_cqe_flush_error[0x20]; 4896 4897 u8 reserved_at_620[0x20]; 4898 4899 u8 roce_adp_retrans[0x20]; 4900 4901 u8 roce_adp_retrans_to[0x20]; 4902 4903 u8 roce_slow_restart[0x20]; 4904 4905 u8 roce_slow_restart_cnps[0x20]; 4906 4907 u8 roce_slow_restart_trans[0x20]; 4908 4909 u8 reserved_at_6e0[0x120]; 4910 }; 4911 4912 struct mlx5_ifc_query_q_counter_in_bits { 4913 u8 opcode[0x10]; 4914 u8 reserved_at_10[0x10]; 4915 4916 u8 reserved_at_20[0x10]; 4917 u8 op_mod[0x10]; 4918 4919 u8 reserved_at_40[0x80]; 4920 4921 u8 clear[0x1]; 4922 u8 reserved_at_c1[0x1f]; 4923 4924 u8 reserved_at_e0[0x18]; 4925 u8 counter_set_id[0x8]; 4926 }; 4927 4928 struct mlx5_ifc_query_pages_out_bits { 4929 u8 status[0x8]; 4930 u8 reserved_at_8[0x18]; 4931 4932 u8 syndrome[0x20]; 4933 4934 u8 embedded_cpu_function[0x1]; 4935 u8 reserved_at_41[0xf]; 4936 u8 function_id[0x10]; 4937 4938 u8 num_pages[0x20]; 4939 }; 4940 4941 enum { 4942 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4943 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4944 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4945 }; 4946 4947 struct mlx5_ifc_query_pages_in_bits { 4948 u8 opcode[0x10]; 4949 u8 reserved_at_10[0x10]; 4950 4951 u8 reserved_at_20[0x10]; 4952 u8 op_mod[0x10]; 4953 4954 u8 embedded_cpu_function[0x1]; 4955 u8 reserved_at_41[0xf]; 4956 u8 function_id[0x10]; 4957 4958 u8 reserved_at_60[0x20]; 4959 }; 4960 4961 struct mlx5_ifc_query_nic_vport_context_out_bits { 4962 u8 status[0x8]; 4963 u8 reserved_at_8[0x18]; 4964 4965 u8 syndrome[0x20]; 4966 4967 u8 reserved_at_40[0x40]; 4968 4969 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4970 }; 4971 4972 struct mlx5_ifc_query_nic_vport_context_in_bits { 4973 u8 opcode[0x10]; 4974 u8 reserved_at_10[0x10]; 4975 4976 u8 reserved_at_20[0x10]; 4977 u8 op_mod[0x10]; 4978 4979 u8 other_vport[0x1]; 4980 u8 reserved_at_41[0xf]; 4981 u8 vport_number[0x10]; 4982 4983 u8 reserved_at_60[0x5]; 4984 u8 allowed_list_type[0x3]; 4985 u8 reserved_at_68[0x18]; 4986 }; 4987 4988 struct mlx5_ifc_query_mkey_out_bits { 4989 u8 status[0x8]; 4990 u8 reserved_at_8[0x18]; 4991 4992 u8 syndrome[0x20]; 4993 4994 u8 reserved_at_40[0x40]; 4995 4996 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4997 4998 u8 reserved_at_280[0x600]; 4999 5000 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5001 5002 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5003 }; 5004 5005 struct mlx5_ifc_query_mkey_in_bits { 5006 u8 opcode[0x10]; 5007 u8 reserved_at_10[0x10]; 5008 5009 u8 reserved_at_20[0x10]; 5010 u8 op_mod[0x10]; 5011 5012 u8 reserved_at_40[0x8]; 5013 u8 mkey_index[0x18]; 5014 5015 u8 pg_access[0x1]; 5016 u8 reserved_at_61[0x1f]; 5017 }; 5018 5019 struct mlx5_ifc_query_mad_demux_out_bits { 5020 u8 status[0x8]; 5021 u8 reserved_at_8[0x18]; 5022 5023 u8 syndrome[0x20]; 5024 5025 u8 reserved_at_40[0x40]; 5026 5027 u8 mad_dumux_parameters_block[0x20]; 5028 }; 5029 5030 struct mlx5_ifc_query_mad_demux_in_bits { 5031 u8 opcode[0x10]; 5032 u8 reserved_at_10[0x10]; 5033 5034 u8 reserved_at_20[0x10]; 5035 u8 op_mod[0x10]; 5036 5037 u8 reserved_at_40[0x40]; 5038 }; 5039 5040 struct mlx5_ifc_query_l2_table_entry_out_bits { 5041 u8 status[0x8]; 5042 u8 reserved_at_8[0x18]; 5043 5044 u8 syndrome[0x20]; 5045 5046 u8 reserved_at_40[0xa0]; 5047 5048 u8 reserved_at_e0[0x13]; 5049 u8 vlan_valid[0x1]; 5050 u8 vlan[0xc]; 5051 5052 struct mlx5_ifc_mac_address_layout_bits mac_address; 5053 5054 u8 reserved_at_140[0xc0]; 5055 }; 5056 5057 struct mlx5_ifc_query_l2_table_entry_in_bits { 5058 u8 opcode[0x10]; 5059 u8 reserved_at_10[0x10]; 5060 5061 u8 reserved_at_20[0x10]; 5062 u8 op_mod[0x10]; 5063 5064 u8 reserved_at_40[0x60]; 5065 5066 u8 reserved_at_a0[0x8]; 5067 u8 table_index[0x18]; 5068 5069 u8 reserved_at_c0[0x140]; 5070 }; 5071 5072 struct mlx5_ifc_query_issi_out_bits { 5073 u8 status[0x8]; 5074 u8 reserved_at_8[0x18]; 5075 5076 u8 syndrome[0x20]; 5077 5078 u8 reserved_at_40[0x10]; 5079 u8 current_issi[0x10]; 5080 5081 u8 reserved_at_60[0xa0]; 5082 5083 u8 reserved_at_100[76][0x8]; 5084 u8 supported_issi_dw0[0x20]; 5085 }; 5086 5087 struct mlx5_ifc_query_issi_in_bits { 5088 u8 opcode[0x10]; 5089 u8 reserved_at_10[0x10]; 5090 5091 u8 reserved_at_20[0x10]; 5092 u8 op_mod[0x10]; 5093 5094 u8 reserved_at_40[0x40]; 5095 }; 5096 5097 struct mlx5_ifc_set_driver_version_out_bits { 5098 u8 status[0x8]; 5099 u8 reserved_0[0x18]; 5100 5101 u8 syndrome[0x20]; 5102 u8 reserved_1[0x40]; 5103 }; 5104 5105 struct mlx5_ifc_set_driver_version_in_bits { 5106 u8 opcode[0x10]; 5107 u8 reserved_0[0x10]; 5108 5109 u8 reserved_1[0x10]; 5110 u8 op_mod[0x10]; 5111 5112 u8 reserved_2[0x40]; 5113 u8 driver_version[64][0x8]; 5114 }; 5115 5116 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5117 u8 status[0x8]; 5118 u8 reserved_at_8[0x18]; 5119 5120 u8 syndrome[0x20]; 5121 5122 u8 reserved_at_40[0x40]; 5123 5124 struct mlx5_ifc_pkey_bits pkey[0]; 5125 }; 5126 5127 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5128 u8 opcode[0x10]; 5129 u8 reserved_at_10[0x10]; 5130 5131 u8 reserved_at_20[0x10]; 5132 u8 op_mod[0x10]; 5133 5134 u8 other_vport[0x1]; 5135 u8 reserved_at_41[0xb]; 5136 u8 port_num[0x4]; 5137 u8 vport_number[0x10]; 5138 5139 u8 reserved_at_60[0x10]; 5140 u8 pkey_index[0x10]; 5141 }; 5142 5143 enum { 5144 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5145 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5146 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5147 }; 5148 5149 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5150 u8 status[0x8]; 5151 u8 reserved_at_8[0x18]; 5152 5153 u8 syndrome[0x20]; 5154 5155 u8 reserved_at_40[0x20]; 5156 5157 u8 gids_num[0x10]; 5158 u8 reserved_at_70[0x10]; 5159 5160 struct mlx5_ifc_array128_auto_bits gid[0]; 5161 }; 5162 5163 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5164 u8 opcode[0x10]; 5165 u8 reserved_at_10[0x10]; 5166 5167 u8 reserved_at_20[0x10]; 5168 u8 op_mod[0x10]; 5169 5170 u8 other_vport[0x1]; 5171 u8 reserved_at_41[0xb]; 5172 u8 port_num[0x4]; 5173 u8 vport_number[0x10]; 5174 5175 u8 reserved_at_60[0x10]; 5176 u8 gid_index[0x10]; 5177 }; 5178 5179 struct mlx5_ifc_query_hca_vport_context_out_bits { 5180 u8 status[0x8]; 5181 u8 reserved_at_8[0x18]; 5182 5183 u8 syndrome[0x20]; 5184 5185 u8 reserved_at_40[0x40]; 5186 5187 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5188 }; 5189 5190 struct mlx5_ifc_query_hca_vport_context_in_bits { 5191 u8 opcode[0x10]; 5192 u8 reserved_at_10[0x10]; 5193 5194 u8 reserved_at_20[0x10]; 5195 u8 op_mod[0x10]; 5196 5197 u8 other_vport[0x1]; 5198 u8 reserved_at_41[0xb]; 5199 u8 port_num[0x4]; 5200 u8 vport_number[0x10]; 5201 5202 u8 reserved_at_60[0x20]; 5203 }; 5204 5205 struct mlx5_ifc_query_hca_cap_out_bits { 5206 u8 status[0x8]; 5207 u8 reserved_at_8[0x18]; 5208 5209 u8 syndrome[0x20]; 5210 5211 u8 reserved_at_40[0x40]; 5212 5213 union mlx5_ifc_hca_cap_union_bits capability; 5214 }; 5215 5216 struct mlx5_ifc_query_hca_cap_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_at_10[0x10]; 5219 5220 u8 reserved_at_20[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 other_function[0x1]; 5224 u8 reserved_at_41[0xf]; 5225 u8 function_id[0x10]; 5226 5227 u8 reserved_at_60[0x20]; 5228 }; 5229 5230 struct mlx5_ifc_other_hca_cap_bits { 5231 u8 roce[0x1]; 5232 u8 reserved_at_1[0x27f]; 5233 }; 5234 5235 struct mlx5_ifc_query_other_hca_cap_out_bits { 5236 u8 status[0x8]; 5237 u8 reserved_at_8[0x18]; 5238 5239 u8 syndrome[0x20]; 5240 5241 u8 reserved_at_40[0x40]; 5242 5243 struct mlx5_ifc_other_hca_cap_bits other_capability; 5244 }; 5245 5246 struct mlx5_ifc_query_other_hca_cap_in_bits { 5247 u8 opcode[0x10]; 5248 u8 reserved_at_10[0x10]; 5249 5250 u8 reserved_at_20[0x10]; 5251 u8 op_mod[0x10]; 5252 5253 u8 reserved_at_40[0x10]; 5254 u8 function_id[0x10]; 5255 5256 u8 reserved_at_60[0x20]; 5257 }; 5258 5259 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5260 u8 status[0x8]; 5261 u8 reserved_at_8[0x18]; 5262 5263 u8 syndrome[0x20]; 5264 5265 u8 reserved_at_40[0x40]; 5266 }; 5267 5268 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5269 u8 opcode[0x10]; 5270 u8 reserved_at_10[0x10]; 5271 5272 u8 reserved_at_20[0x10]; 5273 u8 op_mod[0x10]; 5274 5275 u8 reserved_at_40[0x10]; 5276 u8 function_id[0x10]; 5277 u8 field_select[0x20]; 5278 5279 struct mlx5_ifc_other_hca_cap_bits other_capability; 5280 }; 5281 5282 struct mlx5_ifc_flow_table_context_bits { 5283 u8 reformat_en[0x1]; 5284 u8 decap_en[0x1]; 5285 u8 sw_owner[0x1]; 5286 u8 termination_table[0x1]; 5287 u8 table_miss_action[0x4]; 5288 u8 level[0x8]; 5289 u8 reserved_at_10[0x8]; 5290 u8 log_size[0x8]; 5291 5292 u8 reserved_at_20[0x8]; 5293 u8 table_miss_id[0x18]; 5294 5295 u8 reserved_at_40[0x8]; 5296 u8 lag_master_next_table_id[0x18]; 5297 5298 u8 reserved_at_60[0x60]; 5299 5300 u8 sw_owner_icm_root_1[0x40]; 5301 5302 u8 sw_owner_icm_root_0[0x40]; 5303 5304 }; 5305 5306 struct mlx5_ifc_query_flow_table_out_bits { 5307 u8 status[0x8]; 5308 u8 reserved_at_8[0x18]; 5309 5310 u8 syndrome[0x20]; 5311 5312 u8 reserved_at_40[0x80]; 5313 5314 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5315 }; 5316 5317 struct mlx5_ifc_query_flow_table_in_bits { 5318 u8 opcode[0x10]; 5319 u8 reserved_at_10[0x10]; 5320 5321 u8 reserved_at_20[0x10]; 5322 u8 op_mod[0x10]; 5323 5324 u8 reserved_at_40[0x40]; 5325 5326 u8 table_type[0x8]; 5327 u8 reserved_at_88[0x18]; 5328 5329 u8 reserved_at_a0[0x8]; 5330 u8 table_id[0x18]; 5331 5332 u8 reserved_at_c0[0x140]; 5333 }; 5334 5335 struct mlx5_ifc_query_fte_out_bits { 5336 u8 status[0x8]; 5337 u8 reserved_at_8[0x18]; 5338 5339 u8 syndrome[0x20]; 5340 5341 u8 reserved_at_40[0x1c0]; 5342 5343 struct mlx5_ifc_flow_context_bits flow_context; 5344 }; 5345 5346 struct mlx5_ifc_query_fte_in_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_at_10[0x10]; 5349 5350 u8 reserved_at_20[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 reserved_at_40[0x40]; 5354 5355 u8 table_type[0x8]; 5356 u8 reserved_at_88[0x18]; 5357 5358 u8 reserved_at_a0[0x8]; 5359 u8 table_id[0x18]; 5360 5361 u8 reserved_at_c0[0x40]; 5362 5363 u8 flow_index[0x20]; 5364 5365 u8 reserved_at_120[0xe0]; 5366 }; 5367 5368 enum { 5369 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5370 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5371 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5372 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5373 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5374 }; 5375 5376 struct mlx5_ifc_query_flow_group_out_bits { 5377 u8 status[0x8]; 5378 u8 reserved_at_8[0x18]; 5379 5380 u8 syndrome[0x20]; 5381 5382 u8 reserved_at_40[0xa0]; 5383 5384 u8 start_flow_index[0x20]; 5385 5386 u8 reserved_at_100[0x20]; 5387 5388 u8 end_flow_index[0x20]; 5389 5390 u8 reserved_at_140[0xa0]; 5391 5392 u8 reserved_at_1e0[0x18]; 5393 u8 match_criteria_enable[0x8]; 5394 5395 struct mlx5_ifc_fte_match_param_bits match_criteria; 5396 5397 u8 reserved_at_1200[0xe00]; 5398 }; 5399 5400 struct mlx5_ifc_query_flow_group_in_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_at_10[0x10]; 5403 5404 u8 reserved_at_20[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 reserved_at_40[0x40]; 5408 5409 u8 table_type[0x8]; 5410 u8 reserved_at_88[0x18]; 5411 5412 u8 reserved_at_a0[0x8]; 5413 u8 table_id[0x18]; 5414 5415 u8 group_id[0x20]; 5416 5417 u8 reserved_at_e0[0x120]; 5418 }; 5419 5420 struct mlx5_ifc_query_flow_counter_out_bits { 5421 u8 status[0x8]; 5422 u8 reserved_at_8[0x18]; 5423 5424 u8 syndrome[0x20]; 5425 5426 u8 reserved_at_40[0x40]; 5427 5428 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5429 }; 5430 5431 struct mlx5_ifc_query_flow_counter_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_at_10[0x10]; 5434 5435 u8 reserved_at_20[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 reserved_at_40[0x80]; 5439 5440 u8 clear[0x1]; 5441 u8 reserved_at_c1[0xf]; 5442 u8 num_of_counters[0x10]; 5443 5444 u8 flow_counter_id[0x20]; 5445 }; 5446 5447 struct mlx5_ifc_query_esw_vport_context_out_bits { 5448 u8 status[0x8]; 5449 u8 reserved_at_8[0x18]; 5450 5451 u8 syndrome[0x20]; 5452 5453 u8 reserved_at_40[0x40]; 5454 5455 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5456 }; 5457 5458 struct mlx5_ifc_query_esw_vport_context_in_bits { 5459 u8 opcode[0x10]; 5460 u8 reserved_at_10[0x10]; 5461 5462 u8 reserved_at_20[0x10]; 5463 u8 op_mod[0x10]; 5464 5465 u8 other_vport[0x1]; 5466 u8 reserved_at_41[0xf]; 5467 u8 vport_number[0x10]; 5468 5469 u8 reserved_at_60[0x20]; 5470 }; 5471 5472 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5473 u8 status[0x8]; 5474 u8 reserved_at_8[0x18]; 5475 5476 u8 syndrome[0x20]; 5477 5478 u8 reserved_at_40[0x40]; 5479 }; 5480 5481 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5482 u8 reserved_at_0[0x1b]; 5483 u8 fdb_to_vport_reg_c_id[0x1]; 5484 u8 vport_cvlan_insert[0x1]; 5485 u8 vport_svlan_insert[0x1]; 5486 u8 vport_cvlan_strip[0x1]; 5487 u8 vport_svlan_strip[0x1]; 5488 }; 5489 5490 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5491 u8 opcode[0x10]; 5492 u8 reserved_at_10[0x10]; 5493 5494 u8 reserved_at_20[0x10]; 5495 u8 op_mod[0x10]; 5496 5497 u8 other_vport[0x1]; 5498 u8 reserved_at_41[0xf]; 5499 u8 vport_number[0x10]; 5500 5501 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5502 5503 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5504 }; 5505 5506 struct mlx5_ifc_query_eq_out_bits { 5507 u8 status[0x8]; 5508 u8 reserved_at_8[0x18]; 5509 5510 u8 syndrome[0x20]; 5511 5512 u8 reserved_at_40[0x40]; 5513 5514 struct mlx5_ifc_eqc_bits eq_context_entry; 5515 5516 u8 reserved_at_280[0x40]; 5517 5518 u8 event_bitmask[0x40]; 5519 5520 u8 reserved_at_300[0x580]; 5521 5522 u8 pas[0][0x40]; 5523 }; 5524 5525 struct mlx5_ifc_query_eq_in_bits { 5526 u8 opcode[0x10]; 5527 u8 reserved_at_10[0x10]; 5528 5529 u8 reserved_at_20[0x10]; 5530 u8 op_mod[0x10]; 5531 5532 u8 reserved_at_40[0x18]; 5533 u8 eq_number[0x8]; 5534 5535 u8 reserved_at_60[0x20]; 5536 }; 5537 5538 struct mlx5_ifc_packet_reformat_context_in_bits { 5539 u8 reserved_at_0[0x5]; 5540 u8 reformat_type[0x3]; 5541 u8 reserved_at_8[0xe]; 5542 u8 reformat_data_size[0xa]; 5543 5544 u8 reserved_at_20[0x10]; 5545 u8 reformat_data[2][0x8]; 5546 5547 u8 more_reformat_data[0][0x8]; 5548 }; 5549 5550 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5551 u8 status[0x8]; 5552 u8 reserved_at_8[0x18]; 5553 5554 u8 syndrome[0x20]; 5555 5556 u8 reserved_at_40[0xa0]; 5557 5558 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5559 }; 5560 5561 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5562 u8 opcode[0x10]; 5563 u8 reserved_at_10[0x10]; 5564 5565 u8 reserved_at_20[0x10]; 5566 u8 op_mod[0x10]; 5567 5568 u8 packet_reformat_id[0x20]; 5569 5570 u8 reserved_at_60[0xa0]; 5571 }; 5572 5573 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5574 u8 status[0x8]; 5575 u8 reserved_at_8[0x18]; 5576 5577 u8 syndrome[0x20]; 5578 5579 u8 packet_reformat_id[0x20]; 5580 5581 u8 reserved_at_60[0x20]; 5582 }; 5583 5584 enum mlx5_reformat_ctx_type { 5585 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5586 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5587 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5588 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5589 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5590 }; 5591 5592 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5593 u8 opcode[0x10]; 5594 u8 reserved_at_10[0x10]; 5595 5596 u8 reserved_at_20[0x10]; 5597 u8 op_mod[0x10]; 5598 5599 u8 reserved_at_40[0xa0]; 5600 5601 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5602 }; 5603 5604 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5605 u8 status[0x8]; 5606 u8 reserved_at_8[0x18]; 5607 5608 u8 syndrome[0x20]; 5609 5610 u8 reserved_at_40[0x40]; 5611 }; 5612 5613 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5614 u8 opcode[0x10]; 5615 u8 reserved_at_10[0x10]; 5616 5617 u8 reserved_20[0x10]; 5618 u8 op_mod[0x10]; 5619 5620 u8 packet_reformat_id[0x20]; 5621 5622 u8 reserved_60[0x20]; 5623 }; 5624 5625 struct mlx5_ifc_set_action_in_bits { 5626 u8 action_type[0x4]; 5627 u8 field[0xc]; 5628 u8 reserved_at_10[0x3]; 5629 u8 offset[0x5]; 5630 u8 reserved_at_18[0x3]; 5631 u8 length[0x5]; 5632 5633 u8 data[0x20]; 5634 }; 5635 5636 struct mlx5_ifc_add_action_in_bits { 5637 u8 action_type[0x4]; 5638 u8 field[0xc]; 5639 u8 reserved_at_10[0x10]; 5640 5641 u8 data[0x20]; 5642 }; 5643 5644 struct mlx5_ifc_copy_action_in_bits { 5645 u8 action_type[0x4]; 5646 u8 src_field[0xc]; 5647 u8 reserved_at_10[0x3]; 5648 u8 src_offset[0x5]; 5649 u8 reserved_at_18[0x3]; 5650 u8 length[0x5]; 5651 5652 u8 reserved_at_20[0x4]; 5653 u8 dst_field[0xc]; 5654 u8 reserved_at_30[0x3]; 5655 u8 dst_offset[0x5]; 5656 u8 reserved_at_38[0x8]; 5657 }; 5658 5659 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5660 struct mlx5_ifc_set_action_in_bits set_action_in; 5661 struct mlx5_ifc_add_action_in_bits add_action_in; 5662 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5663 u8 reserved_at_0[0x40]; 5664 }; 5665 5666 enum { 5667 MLX5_ACTION_TYPE_SET = 0x1, 5668 MLX5_ACTION_TYPE_ADD = 0x2, 5669 MLX5_ACTION_TYPE_COPY = 0x3, 5670 }; 5671 5672 enum { 5673 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5674 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5675 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5676 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5677 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5678 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5679 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5680 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5681 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5682 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5683 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5684 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5685 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5686 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5687 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5688 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5689 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5690 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5691 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5692 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5693 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5694 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5695 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5696 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5697 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5698 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5699 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5700 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5701 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5702 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5703 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5704 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5705 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5706 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5707 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5708 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5709 }; 5710 5711 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5712 u8 status[0x8]; 5713 u8 reserved_at_8[0x18]; 5714 5715 u8 syndrome[0x20]; 5716 5717 u8 modify_header_id[0x20]; 5718 5719 u8 reserved_at_60[0x20]; 5720 }; 5721 5722 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5723 u8 opcode[0x10]; 5724 u8 reserved_at_10[0x10]; 5725 5726 u8 reserved_at_20[0x10]; 5727 u8 op_mod[0x10]; 5728 5729 u8 reserved_at_40[0x20]; 5730 5731 u8 table_type[0x8]; 5732 u8 reserved_at_68[0x10]; 5733 u8 num_of_actions[0x8]; 5734 5735 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5736 }; 5737 5738 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5739 u8 status[0x8]; 5740 u8 reserved_at_8[0x18]; 5741 5742 u8 syndrome[0x20]; 5743 5744 u8 reserved_at_40[0x40]; 5745 }; 5746 5747 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5748 u8 opcode[0x10]; 5749 u8 reserved_at_10[0x10]; 5750 5751 u8 reserved_at_20[0x10]; 5752 u8 op_mod[0x10]; 5753 5754 u8 modify_header_id[0x20]; 5755 5756 u8 reserved_at_60[0x20]; 5757 }; 5758 5759 struct mlx5_ifc_query_dct_out_bits { 5760 u8 status[0x8]; 5761 u8 reserved_at_8[0x18]; 5762 5763 u8 syndrome[0x20]; 5764 5765 u8 reserved_at_40[0x40]; 5766 5767 struct mlx5_ifc_dctc_bits dct_context_entry; 5768 5769 u8 reserved_at_280[0x180]; 5770 }; 5771 5772 struct mlx5_ifc_query_dct_in_bits { 5773 u8 opcode[0x10]; 5774 u8 reserved_at_10[0x10]; 5775 5776 u8 reserved_at_20[0x10]; 5777 u8 op_mod[0x10]; 5778 5779 u8 reserved_at_40[0x8]; 5780 u8 dctn[0x18]; 5781 5782 u8 reserved_at_60[0x20]; 5783 }; 5784 5785 struct mlx5_ifc_query_cq_out_bits { 5786 u8 status[0x8]; 5787 u8 reserved_at_8[0x18]; 5788 5789 u8 syndrome[0x20]; 5790 5791 u8 reserved_at_40[0x40]; 5792 5793 struct mlx5_ifc_cqc_bits cq_context; 5794 5795 u8 reserved_at_280[0x600]; 5796 5797 u8 pas[0][0x40]; 5798 }; 5799 5800 struct mlx5_ifc_query_cq_in_bits { 5801 u8 opcode[0x10]; 5802 u8 reserved_at_10[0x10]; 5803 5804 u8 reserved_at_20[0x10]; 5805 u8 op_mod[0x10]; 5806 5807 u8 reserved_at_40[0x8]; 5808 u8 cqn[0x18]; 5809 5810 u8 reserved_at_60[0x20]; 5811 }; 5812 5813 struct mlx5_ifc_query_cong_status_out_bits { 5814 u8 status[0x8]; 5815 u8 reserved_at_8[0x18]; 5816 5817 u8 syndrome[0x20]; 5818 5819 u8 reserved_at_40[0x20]; 5820 5821 u8 enable[0x1]; 5822 u8 tag_enable[0x1]; 5823 u8 reserved_at_62[0x1e]; 5824 }; 5825 5826 struct mlx5_ifc_query_cong_status_in_bits { 5827 u8 opcode[0x10]; 5828 u8 reserved_at_10[0x10]; 5829 5830 u8 reserved_at_20[0x10]; 5831 u8 op_mod[0x10]; 5832 5833 u8 reserved_at_40[0x18]; 5834 u8 priority[0x4]; 5835 u8 cong_protocol[0x4]; 5836 5837 u8 reserved_at_60[0x20]; 5838 }; 5839 5840 struct mlx5_ifc_query_cong_statistics_out_bits { 5841 u8 status[0x8]; 5842 u8 reserved_at_8[0x18]; 5843 5844 u8 syndrome[0x20]; 5845 5846 u8 reserved_at_40[0x40]; 5847 5848 u8 rp_cur_flows[0x20]; 5849 5850 u8 sum_flows[0x20]; 5851 5852 u8 rp_cnp_ignored_high[0x20]; 5853 5854 u8 rp_cnp_ignored_low[0x20]; 5855 5856 u8 rp_cnp_handled_high[0x20]; 5857 5858 u8 rp_cnp_handled_low[0x20]; 5859 5860 u8 reserved_at_140[0x100]; 5861 5862 u8 time_stamp_high[0x20]; 5863 5864 u8 time_stamp_low[0x20]; 5865 5866 u8 accumulators_period[0x20]; 5867 5868 u8 np_ecn_marked_roce_packets_high[0x20]; 5869 5870 u8 np_ecn_marked_roce_packets_low[0x20]; 5871 5872 u8 np_cnp_sent_high[0x20]; 5873 5874 u8 np_cnp_sent_low[0x20]; 5875 5876 u8 reserved_at_320[0x560]; 5877 }; 5878 5879 struct mlx5_ifc_query_cong_statistics_in_bits { 5880 u8 opcode[0x10]; 5881 u8 reserved_at_10[0x10]; 5882 5883 u8 reserved_at_20[0x10]; 5884 u8 op_mod[0x10]; 5885 5886 u8 clear[0x1]; 5887 u8 reserved_at_41[0x1f]; 5888 5889 u8 reserved_at_60[0x20]; 5890 }; 5891 5892 struct mlx5_ifc_query_cong_params_out_bits { 5893 u8 status[0x8]; 5894 u8 reserved_at_8[0x18]; 5895 5896 u8 syndrome[0x20]; 5897 5898 u8 reserved_at_40[0x40]; 5899 5900 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5901 }; 5902 5903 struct mlx5_ifc_query_cong_params_in_bits { 5904 u8 opcode[0x10]; 5905 u8 reserved_at_10[0x10]; 5906 5907 u8 reserved_at_20[0x10]; 5908 u8 op_mod[0x10]; 5909 5910 u8 reserved_at_40[0x1c]; 5911 u8 cong_protocol[0x4]; 5912 5913 u8 reserved_at_60[0x20]; 5914 }; 5915 5916 struct mlx5_ifc_query_adapter_out_bits { 5917 u8 status[0x8]; 5918 u8 reserved_at_8[0x18]; 5919 5920 u8 syndrome[0x20]; 5921 5922 u8 reserved_at_40[0x40]; 5923 5924 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5925 }; 5926 5927 struct mlx5_ifc_query_adapter_in_bits { 5928 u8 opcode[0x10]; 5929 u8 reserved_at_10[0x10]; 5930 5931 u8 reserved_at_20[0x10]; 5932 u8 op_mod[0x10]; 5933 5934 u8 reserved_at_40[0x40]; 5935 }; 5936 5937 struct mlx5_ifc_qp_2rst_out_bits { 5938 u8 status[0x8]; 5939 u8 reserved_at_8[0x18]; 5940 5941 u8 syndrome[0x20]; 5942 5943 u8 reserved_at_40[0x40]; 5944 }; 5945 5946 struct mlx5_ifc_qp_2rst_in_bits { 5947 u8 opcode[0x10]; 5948 u8 uid[0x10]; 5949 5950 u8 reserved_at_20[0x10]; 5951 u8 op_mod[0x10]; 5952 5953 u8 reserved_at_40[0x8]; 5954 u8 qpn[0x18]; 5955 5956 u8 reserved_at_60[0x20]; 5957 }; 5958 5959 struct mlx5_ifc_qp_2err_out_bits { 5960 u8 status[0x8]; 5961 u8 reserved_at_8[0x18]; 5962 5963 u8 syndrome[0x20]; 5964 5965 u8 reserved_at_40[0x40]; 5966 }; 5967 5968 struct mlx5_ifc_qp_2err_in_bits { 5969 u8 opcode[0x10]; 5970 u8 uid[0x10]; 5971 5972 u8 reserved_at_20[0x10]; 5973 u8 op_mod[0x10]; 5974 5975 u8 reserved_at_40[0x8]; 5976 u8 qpn[0x18]; 5977 5978 u8 reserved_at_60[0x20]; 5979 }; 5980 5981 struct mlx5_ifc_page_fault_resume_out_bits { 5982 u8 status[0x8]; 5983 u8 reserved_at_8[0x18]; 5984 5985 u8 syndrome[0x20]; 5986 5987 u8 reserved_at_40[0x40]; 5988 }; 5989 5990 struct mlx5_ifc_page_fault_resume_in_bits { 5991 u8 opcode[0x10]; 5992 u8 reserved_at_10[0x10]; 5993 5994 u8 reserved_at_20[0x10]; 5995 u8 op_mod[0x10]; 5996 5997 u8 error[0x1]; 5998 u8 reserved_at_41[0x4]; 5999 u8 page_fault_type[0x3]; 6000 u8 wq_number[0x18]; 6001 6002 u8 reserved_at_60[0x8]; 6003 u8 token[0x18]; 6004 }; 6005 6006 struct mlx5_ifc_nop_out_bits { 6007 u8 status[0x8]; 6008 u8 reserved_at_8[0x18]; 6009 6010 u8 syndrome[0x20]; 6011 6012 u8 reserved_at_40[0x40]; 6013 }; 6014 6015 struct mlx5_ifc_nop_in_bits { 6016 u8 opcode[0x10]; 6017 u8 reserved_at_10[0x10]; 6018 6019 u8 reserved_at_20[0x10]; 6020 u8 op_mod[0x10]; 6021 6022 u8 reserved_at_40[0x40]; 6023 }; 6024 6025 struct mlx5_ifc_modify_vport_state_out_bits { 6026 u8 status[0x8]; 6027 u8 reserved_at_8[0x18]; 6028 6029 u8 syndrome[0x20]; 6030 6031 u8 reserved_at_40[0x40]; 6032 }; 6033 6034 struct mlx5_ifc_modify_vport_state_in_bits { 6035 u8 opcode[0x10]; 6036 u8 reserved_at_10[0x10]; 6037 6038 u8 reserved_at_20[0x10]; 6039 u8 op_mod[0x10]; 6040 6041 u8 other_vport[0x1]; 6042 u8 reserved_at_41[0xf]; 6043 u8 vport_number[0x10]; 6044 6045 u8 reserved_at_60[0x18]; 6046 u8 admin_state[0x4]; 6047 u8 reserved_at_7c[0x4]; 6048 }; 6049 6050 struct mlx5_ifc_modify_tis_out_bits { 6051 u8 status[0x8]; 6052 u8 reserved_at_8[0x18]; 6053 6054 u8 syndrome[0x20]; 6055 6056 u8 reserved_at_40[0x40]; 6057 }; 6058 6059 struct mlx5_ifc_modify_tis_bitmask_bits { 6060 u8 reserved_at_0[0x20]; 6061 6062 u8 reserved_at_20[0x1d]; 6063 u8 lag_tx_port_affinity[0x1]; 6064 u8 strict_lag_tx_port_affinity[0x1]; 6065 u8 prio[0x1]; 6066 }; 6067 6068 struct mlx5_ifc_modify_tis_in_bits { 6069 u8 opcode[0x10]; 6070 u8 uid[0x10]; 6071 6072 u8 reserved_at_20[0x10]; 6073 u8 op_mod[0x10]; 6074 6075 u8 reserved_at_40[0x8]; 6076 u8 tisn[0x18]; 6077 6078 u8 reserved_at_60[0x20]; 6079 6080 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6081 6082 u8 reserved_at_c0[0x40]; 6083 6084 struct mlx5_ifc_tisc_bits ctx; 6085 }; 6086 6087 struct mlx5_ifc_modify_tir_bitmask_bits { 6088 u8 reserved_at_0[0x20]; 6089 6090 u8 reserved_at_20[0x1b]; 6091 u8 self_lb_en[0x1]; 6092 u8 reserved_at_3c[0x1]; 6093 u8 hash[0x1]; 6094 u8 reserved_at_3e[0x1]; 6095 u8 lro[0x1]; 6096 }; 6097 6098 struct mlx5_ifc_modify_tir_out_bits { 6099 u8 status[0x8]; 6100 u8 reserved_at_8[0x18]; 6101 6102 u8 syndrome[0x20]; 6103 6104 u8 reserved_at_40[0x40]; 6105 }; 6106 6107 struct mlx5_ifc_modify_tir_in_bits { 6108 u8 opcode[0x10]; 6109 u8 uid[0x10]; 6110 6111 u8 reserved_at_20[0x10]; 6112 u8 op_mod[0x10]; 6113 6114 u8 reserved_at_40[0x8]; 6115 u8 tirn[0x18]; 6116 6117 u8 reserved_at_60[0x20]; 6118 6119 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6120 6121 u8 reserved_at_c0[0x40]; 6122 6123 struct mlx5_ifc_tirc_bits ctx; 6124 }; 6125 6126 struct mlx5_ifc_modify_sq_out_bits { 6127 u8 status[0x8]; 6128 u8 reserved_at_8[0x18]; 6129 6130 u8 syndrome[0x20]; 6131 6132 u8 reserved_at_40[0x40]; 6133 }; 6134 6135 struct mlx5_ifc_modify_sq_in_bits { 6136 u8 opcode[0x10]; 6137 u8 uid[0x10]; 6138 6139 u8 reserved_at_20[0x10]; 6140 u8 op_mod[0x10]; 6141 6142 u8 sq_state[0x4]; 6143 u8 reserved_at_44[0x4]; 6144 u8 sqn[0x18]; 6145 6146 u8 reserved_at_60[0x20]; 6147 6148 u8 modify_bitmask[0x40]; 6149 6150 u8 reserved_at_c0[0x40]; 6151 6152 struct mlx5_ifc_sqc_bits ctx; 6153 }; 6154 6155 struct mlx5_ifc_modify_scheduling_element_out_bits { 6156 u8 status[0x8]; 6157 u8 reserved_at_8[0x18]; 6158 6159 u8 syndrome[0x20]; 6160 6161 u8 reserved_at_40[0x1c0]; 6162 }; 6163 6164 enum { 6165 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6166 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6167 }; 6168 6169 struct mlx5_ifc_modify_scheduling_element_in_bits { 6170 u8 opcode[0x10]; 6171 u8 reserved_at_10[0x10]; 6172 6173 u8 reserved_at_20[0x10]; 6174 u8 op_mod[0x10]; 6175 6176 u8 scheduling_hierarchy[0x8]; 6177 u8 reserved_at_48[0x18]; 6178 6179 u8 scheduling_element_id[0x20]; 6180 6181 u8 reserved_at_80[0x20]; 6182 6183 u8 modify_bitmask[0x20]; 6184 6185 u8 reserved_at_c0[0x40]; 6186 6187 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6188 6189 u8 reserved_at_300[0x100]; 6190 }; 6191 6192 struct mlx5_ifc_modify_rqt_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_at_8[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_at_40[0x40]; 6199 }; 6200 6201 struct mlx5_ifc_rqt_bitmask_bits { 6202 u8 reserved_at_0[0x20]; 6203 6204 u8 reserved_at_20[0x1f]; 6205 u8 rqn_list[0x1]; 6206 }; 6207 6208 struct mlx5_ifc_modify_rqt_in_bits { 6209 u8 opcode[0x10]; 6210 u8 uid[0x10]; 6211 6212 u8 reserved_at_20[0x10]; 6213 u8 op_mod[0x10]; 6214 6215 u8 reserved_at_40[0x8]; 6216 u8 rqtn[0x18]; 6217 6218 u8 reserved_at_60[0x20]; 6219 6220 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6221 6222 u8 reserved_at_c0[0x40]; 6223 6224 struct mlx5_ifc_rqtc_bits ctx; 6225 }; 6226 6227 struct mlx5_ifc_modify_rq_out_bits { 6228 u8 status[0x8]; 6229 u8 reserved_at_8[0x18]; 6230 6231 u8 syndrome[0x20]; 6232 6233 u8 reserved_at_40[0x40]; 6234 }; 6235 6236 enum { 6237 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6238 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6239 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6240 }; 6241 6242 struct mlx5_ifc_modify_rq_in_bits { 6243 u8 opcode[0x10]; 6244 u8 uid[0x10]; 6245 6246 u8 reserved_at_20[0x10]; 6247 u8 op_mod[0x10]; 6248 6249 u8 rq_state[0x4]; 6250 u8 reserved_at_44[0x4]; 6251 u8 rqn[0x18]; 6252 6253 u8 reserved_at_60[0x20]; 6254 6255 u8 modify_bitmask[0x40]; 6256 6257 u8 reserved_at_c0[0x40]; 6258 6259 struct mlx5_ifc_rqc_bits ctx; 6260 }; 6261 6262 struct mlx5_ifc_modify_rmp_out_bits { 6263 u8 status[0x8]; 6264 u8 reserved_at_8[0x18]; 6265 6266 u8 syndrome[0x20]; 6267 6268 u8 reserved_at_40[0x40]; 6269 }; 6270 6271 struct mlx5_ifc_rmp_bitmask_bits { 6272 u8 reserved_at_0[0x20]; 6273 6274 u8 reserved_at_20[0x1f]; 6275 u8 lwm[0x1]; 6276 }; 6277 6278 struct mlx5_ifc_modify_rmp_in_bits { 6279 u8 opcode[0x10]; 6280 u8 uid[0x10]; 6281 6282 u8 reserved_at_20[0x10]; 6283 u8 op_mod[0x10]; 6284 6285 u8 rmp_state[0x4]; 6286 u8 reserved_at_44[0x4]; 6287 u8 rmpn[0x18]; 6288 6289 u8 reserved_at_60[0x20]; 6290 6291 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6292 6293 u8 reserved_at_c0[0x40]; 6294 6295 struct mlx5_ifc_rmpc_bits ctx; 6296 }; 6297 6298 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6299 u8 status[0x8]; 6300 u8 reserved_at_8[0x18]; 6301 6302 u8 syndrome[0x20]; 6303 6304 u8 reserved_at_40[0x40]; 6305 }; 6306 6307 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6308 u8 reserved_at_0[0x12]; 6309 u8 affiliation[0x1]; 6310 u8 reserved_at_13[0x1]; 6311 u8 disable_uc_local_lb[0x1]; 6312 u8 disable_mc_local_lb[0x1]; 6313 u8 node_guid[0x1]; 6314 u8 port_guid[0x1]; 6315 u8 min_inline[0x1]; 6316 u8 mtu[0x1]; 6317 u8 change_event[0x1]; 6318 u8 promisc[0x1]; 6319 u8 permanent_address[0x1]; 6320 u8 addresses_list[0x1]; 6321 u8 roce_en[0x1]; 6322 u8 reserved_at_1f[0x1]; 6323 }; 6324 6325 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6326 u8 opcode[0x10]; 6327 u8 reserved_at_10[0x10]; 6328 6329 u8 reserved_at_20[0x10]; 6330 u8 op_mod[0x10]; 6331 6332 u8 other_vport[0x1]; 6333 u8 reserved_at_41[0xf]; 6334 u8 vport_number[0x10]; 6335 6336 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6337 6338 u8 reserved_at_80[0x780]; 6339 6340 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6341 }; 6342 6343 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6344 u8 status[0x8]; 6345 u8 reserved_at_8[0x18]; 6346 6347 u8 syndrome[0x20]; 6348 6349 u8 reserved_at_40[0x40]; 6350 }; 6351 6352 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6353 u8 opcode[0x10]; 6354 u8 reserved_at_10[0x10]; 6355 6356 u8 reserved_at_20[0x10]; 6357 u8 op_mod[0x10]; 6358 6359 u8 other_vport[0x1]; 6360 u8 reserved_at_41[0xb]; 6361 u8 port_num[0x4]; 6362 u8 vport_number[0x10]; 6363 6364 u8 reserved_at_60[0x20]; 6365 6366 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6367 }; 6368 6369 struct mlx5_ifc_modify_cq_out_bits { 6370 u8 status[0x8]; 6371 u8 reserved_at_8[0x18]; 6372 6373 u8 syndrome[0x20]; 6374 6375 u8 reserved_at_40[0x40]; 6376 }; 6377 6378 enum { 6379 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6380 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6381 }; 6382 6383 struct mlx5_ifc_modify_cq_in_bits { 6384 u8 opcode[0x10]; 6385 u8 uid[0x10]; 6386 6387 u8 reserved_at_20[0x10]; 6388 u8 op_mod[0x10]; 6389 6390 u8 reserved_at_40[0x8]; 6391 u8 cqn[0x18]; 6392 6393 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6394 6395 struct mlx5_ifc_cqc_bits cq_context; 6396 6397 u8 reserved_at_280[0x60]; 6398 6399 u8 cq_umem_valid[0x1]; 6400 u8 reserved_at_2e1[0x1f]; 6401 6402 u8 reserved_at_300[0x580]; 6403 6404 u8 pas[0][0x40]; 6405 }; 6406 6407 struct mlx5_ifc_modify_cong_status_out_bits { 6408 u8 status[0x8]; 6409 u8 reserved_at_8[0x18]; 6410 6411 u8 syndrome[0x20]; 6412 6413 u8 reserved_at_40[0x40]; 6414 }; 6415 6416 struct mlx5_ifc_modify_cong_status_in_bits { 6417 u8 opcode[0x10]; 6418 u8 reserved_at_10[0x10]; 6419 6420 u8 reserved_at_20[0x10]; 6421 u8 op_mod[0x10]; 6422 6423 u8 reserved_at_40[0x18]; 6424 u8 priority[0x4]; 6425 u8 cong_protocol[0x4]; 6426 6427 u8 enable[0x1]; 6428 u8 tag_enable[0x1]; 6429 u8 reserved_at_62[0x1e]; 6430 }; 6431 6432 struct mlx5_ifc_modify_cong_params_out_bits { 6433 u8 status[0x8]; 6434 u8 reserved_at_8[0x18]; 6435 6436 u8 syndrome[0x20]; 6437 6438 u8 reserved_at_40[0x40]; 6439 }; 6440 6441 struct mlx5_ifc_modify_cong_params_in_bits { 6442 u8 opcode[0x10]; 6443 u8 reserved_at_10[0x10]; 6444 6445 u8 reserved_at_20[0x10]; 6446 u8 op_mod[0x10]; 6447 6448 u8 reserved_at_40[0x1c]; 6449 u8 cong_protocol[0x4]; 6450 6451 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6452 6453 u8 reserved_at_80[0x80]; 6454 6455 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6456 }; 6457 6458 struct mlx5_ifc_manage_pages_out_bits { 6459 u8 status[0x8]; 6460 u8 reserved_at_8[0x18]; 6461 6462 u8 syndrome[0x20]; 6463 6464 u8 output_num_entries[0x20]; 6465 6466 u8 reserved_at_60[0x20]; 6467 6468 u8 pas[0][0x40]; 6469 }; 6470 6471 enum { 6472 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6473 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6474 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6475 }; 6476 6477 struct mlx5_ifc_manage_pages_in_bits { 6478 u8 opcode[0x10]; 6479 u8 reserved_at_10[0x10]; 6480 6481 u8 reserved_at_20[0x10]; 6482 u8 op_mod[0x10]; 6483 6484 u8 embedded_cpu_function[0x1]; 6485 u8 reserved_at_41[0xf]; 6486 u8 function_id[0x10]; 6487 6488 u8 input_num_entries[0x20]; 6489 6490 u8 pas[0][0x40]; 6491 }; 6492 6493 struct mlx5_ifc_mad_ifc_out_bits { 6494 u8 status[0x8]; 6495 u8 reserved_at_8[0x18]; 6496 6497 u8 syndrome[0x20]; 6498 6499 u8 reserved_at_40[0x40]; 6500 6501 u8 response_mad_packet[256][0x8]; 6502 }; 6503 6504 struct mlx5_ifc_mad_ifc_in_bits { 6505 u8 opcode[0x10]; 6506 u8 reserved_at_10[0x10]; 6507 6508 u8 reserved_at_20[0x10]; 6509 u8 op_mod[0x10]; 6510 6511 u8 remote_lid[0x10]; 6512 u8 reserved_at_50[0x8]; 6513 u8 port[0x8]; 6514 6515 u8 reserved_at_60[0x20]; 6516 6517 u8 mad[256][0x8]; 6518 }; 6519 6520 struct mlx5_ifc_init_hca_out_bits { 6521 u8 status[0x8]; 6522 u8 reserved_at_8[0x18]; 6523 6524 u8 syndrome[0x20]; 6525 6526 u8 reserved_at_40[0x40]; 6527 }; 6528 6529 struct mlx5_ifc_init_hca_in_bits { 6530 u8 opcode[0x10]; 6531 u8 reserved_at_10[0x10]; 6532 6533 u8 reserved_at_20[0x10]; 6534 u8 op_mod[0x10]; 6535 6536 u8 reserved_at_40[0x40]; 6537 u8 sw_owner_id[4][0x20]; 6538 }; 6539 6540 struct mlx5_ifc_init2rtr_qp_out_bits { 6541 u8 status[0x8]; 6542 u8 reserved_at_8[0x18]; 6543 6544 u8 syndrome[0x20]; 6545 6546 u8 reserved_at_40[0x40]; 6547 }; 6548 6549 struct mlx5_ifc_init2rtr_qp_in_bits { 6550 u8 opcode[0x10]; 6551 u8 uid[0x10]; 6552 6553 u8 reserved_at_20[0x10]; 6554 u8 op_mod[0x10]; 6555 6556 u8 reserved_at_40[0x8]; 6557 u8 qpn[0x18]; 6558 6559 u8 reserved_at_60[0x20]; 6560 6561 u8 opt_param_mask[0x20]; 6562 6563 u8 reserved_at_a0[0x20]; 6564 6565 struct mlx5_ifc_qpc_bits qpc; 6566 6567 u8 reserved_at_800[0x80]; 6568 }; 6569 6570 struct mlx5_ifc_init2init_qp_out_bits { 6571 u8 status[0x8]; 6572 u8 reserved_at_8[0x18]; 6573 6574 u8 syndrome[0x20]; 6575 6576 u8 reserved_at_40[0x40]; 6577 }; 6578 6579 struct mlx5_ifc_init2init_qp_in_bits { 6580 u8 opcode[0x10]; 6581 u8 uid[0x10]; 6582 6583 u8 reserved_at_20[0x10]; 6584 u8 op_mod[0x10]; 6585 6586 u8 reserved_at_40[0x8]; 6587 u8 qpn[0x18]; 6588 6589 u8 reserved_at_60[0x20]; 6590 6591 u8 opt_param_mask[0x20]; 6592 6593 u8 reserved_at_a0[0x20]; 6594 6595 struct mlx5_ifc_qpc_bits qpc; 6596 6597 u8 reserved_at_800[0x80]; 6598 }; 6599 6600 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6601 u8 status[0x8]; 6602 u8 reserved_at_8[0x18]; 6603 6604 u8 syndrome[0x20]; 6605 6606 u8 reserved_at_40[0x40]; 6607 6608 u8 packet_headers_log[128][0x8]; 6609 6610 u8 packet_syndrome[64][0x8]; 6611 }; 6612 6613 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6614 u8 opcode[0x10]; 6615 u8 reserved_at_10[0x10]; 6616 6617 u8 reserved_at_20[0x10]; 6618 u8 op_mod[0x10]; 6619 6620 u8 reserved_at_40[0x40]; 6621 }; 6622 6623 struct mlx5_ifc_gen_eqe_in_bits { 6624 u8 opcode[0x10]; 6625 u8 reserved_at_10[0x10]; 6626 6627 u8 reserved_at_20[0x10]; 6628 u8 op_mod[0x10]; 6629 6630 u8 reserved_at_40[0x18]; 6631 u8 eq_number[0x8]; 6632 6633 u8 reserved_at_60[0x20]; 6634 6635 u8 eqe[64][0x8]; 6636 }; 6637 6638 struct mlx5_ifc_gen_eq_out_bits { 6639 u8 status[0x8]; 6640 u8 reserved_at_8[0x18]; 6641 6642 u8 syndrome[0x20]; 6643 6644 u8 reserved_at_40[0x40]; 6645 }; 6646 6647 struct mlx5_ifc_enable_hca_out_bits { 6648 u8 status[0x8]; 6649 u8 reserved_at_8[0x18]; 6650 6651 u8 syndrome[0x20]; 6652 6653 u8 reserved_at_40[0x20]; 6654 }; 6655 6656 struct mlx5_ifc_enable_hca_in_bits { 6657 u8 opcode[0x10]; 6658 u8 reserved_at_10[0x10]; 6659 6660 u8 reserved_at_20[0x10]; 6661 u8 op_mod[0x10]; 6662 6663 u8 embedded_cpu_function[0x1]; 6664 u8 reserved_at_41[0xf]; 6665 u8 function_id[0x10]; 6666 6667 u8 reserved_at_60[0x20]; 6668 }; 6669 6670 struct mlx5_ifc_drain_dct_out_bits { 6671 u8 status[0x8]; 6672 u8 reserved_at_8[0x18]; 6673 6674 u8 syndrome[0x20]; 6675 6676 u8 reserved_at_40[0x40]; 6677 }; 6678 6679 struct mlx5_ifc_drain_dct_in_bits { 6680 u8 opcode[0x10]; 6681 u8 uid[0x10]; 6682 6683 u8 reserved_at_20[0x10]; 6684 u8 op_mod[0x10]; 6685 6686 u8 reserved_at_40[0x8]; 6687 u8 dctn[0x18]; 6688 6689 u8 reserved_at_60[0x20]; 6690 }; 6691 6692 struct mlx5_ifc_disable_hca_out_bits { 6693 u8 status[0x8]; 6694 u8 reserved_at_8[0x18]; 6695 6696 u8 syndrome[0x20]; 6697 6698 u8 reserved_at_40[0x20]; 6699 }; 6700 6701 struct mlx5_ifc_disable_hca_in_bits { 6702 u8 opcode[0x10]; 6703 u8 reserved_at_10[0x10]; 6704 6705 u8 reserved_at_20[0x10]; 6706 u8 op_mod[0x10]; 6707 6708 u8 embedded_cpu_function[0x1]; 6709 u8 reserved_at_41[0xf]; 6710 u8 function_id[0x10]; 6711 6712 u8 reserved_at_60[0x20]; 6713 }; 6714 6715 struct mlx5_ifc_detach_from_mcg_out_bits { 6716 u8 status[0x8]; 6717 u8 reserved_at_8[0x18]; 6718 6719 u8 syndrome[0x20]; 6720 6721 u8 reserved_at_40[0x40]; 6722 }; 6723 6724 struct mlx5_ifc_detach_from_mcg_in_bits { 6725 u8 opcode[0x10]; 6726 u8 uid[0x10]; 6727 6728 u8 reserved_at_20[0x10]; 6729 u8 op_mod[0x10]; 6730 6731 u8 reserved_at_40[0x8]; 6732 u8 qpn[0x18]; 6733 6734 u8 reserved_at_60[0x20]; 6735 6736 u8 multicast_gid[16][0x8]; 6737 }; 6738 6739 struct mlx5_ifc_destroy_xrq_out_bits { 6740 u8 status[0x8]; 6741 u8 reserved_at_8[0x18]; 6742 6743 u8 syndrome[0x20]; 6744 6745 u8 reserved_at_40[0x40]; 6746 }; 6747 6748 struct mlx5_ifc_destroy_xrq_in_bits { 6749 u8 opcode[0x10]; 6750 u8 uid[0x10]; 6751 6752 u8 reserved_at_20[0x10]; 6753 u8 op_mod[0x10]; 6754 6755 u8 reserved_at_40[0x8]; 6756 u8 xrqn[0x18]; 6757 6758 u8 reserved_at_60[0x20]; 6759 }; 6760 6761 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6762 u8 status[0x8]; 6763 u8 reserved_at_8[0x18]; 6764 6765 u8 syndrome[0x20]; 6766 6767 u8 reserved_at_40[0x40]; 6768 }; 6769 6770 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6771 u8 opcode[0x10]; 6772 u8 uid[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 reserved_at_40[0x8]; 6778 u8 xrc_srqn[0x18]; 6779 6780 u8 reserved_at_60[0x20]; 6781 }; 6782 6783 struct mlx5_ifc_destroy_tis_out_bits { 6784 u8 status[0x8]; 6785 u8 reserved_at_8[0x18]; 6786 6787 u8 syndrome[0x20]; 6788 6789 u8 reserved_at_40[0x40]; 6790 }; 6791 6792 struct mlx5_ifc_destroy_tis_in_bits { 6793 u8 opcode[0x10]; 6794 u8 uid[0x10]; 6795 6796 u8 reserved_at_20[0x10]; 6797 u8 op_mod[0x10]; 6798 6799 u8 reserved_at_40[0x8]; 6800 u8 tisn[0x18]; 6801 6802 u8 reserved_at_60[0x20]; 6803 }; 6804 6805 struct mlx5_ifc_destroy_tir_out_bits { 6806 u8 status[0x8]; 6807 u8 reserved_at_8[0x18]; 6808 6809 u8 syndrome[0x20]; 6810 6811 u8 reserved_at_40[0x40]; 6812 }; 6813 6814 struct mlx5_ifc_destroy_tir_in_bits { 6815 u8 opcode[0x10]; 6816 u8 uid[0x10]; 6817 6818 u8 reserved_at_20[0x10]; 6819 u8 op_mod[0x10]; 6820 6821 u8 reserved_at_40[0x8]; 6822 u8 tirn[0x18]; 6823 6824 u8 reserved_at_60[0x20]; 6825 }; 6826 6827 struct mlx5_ifc_destroy_srq_out_bits { 6828 u8 status[0x8]; 6829 u8 reserved_at_8[0x18]; 6830 6831 u8 syndrome[0x20]; 6832 6833 u8 reserved_at_40[0x40]; 6834 }; 6835 6836 struct mlx5_ifc_destroy_srq_in_bits { 6837 u8 opcode[0x10]; 6838 u8 uid[0x10]; 6839 6840 u8 reserved_at_20[0x10]; 6841 u8 op_mod[0x10]; 6842 6843 u8 reserved_at_40[0x8]; 6844 u8 srqn[0x18]; 6845 6846 u8 reserved_at_60[0x20]; 6847 }; 6848 6849 struct mlx5_ifc_destroy_sq_out_bits { 6850 u8 status[0x8]; 6851 u8 reserved_at_8[0x18]; 6852 6853 u8 syndrome[0x20]; 6854 6855 u8 reserved_at_40[0x40]; 6856 }; 6857 6858 struct mlx5_ifc_destroy_sq_in_bits { 6859 u8 opcode[0x10]; 6860 u8 uid[0x10]; 6861 6862 u8 reserved_at_20[0x10]; 6863 u8 op_mod[0x10]; 6864 6865 u8 reserved_at_40[0x8]; 6866 u8 sqn[0x18]; 6867 6868 u8 reserved_at_60[0x20]; 6869 }; 6870 6871 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6872 u8 status[0x8]; 6873 u8 reserved_at_8[0x18]; 6874 6875 u8 syndrome[0x20]; 6876 6877 u8 reserved_at_40[0x1c0]; 6878 }; 6879 6880 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6881 u8 opcode[0x10]; 6882 u8 reserved_at_10[0x10]; 6883 6884 u8 reserved_at_20[0x10]; 6885 u8 op_mod[0x10]; 6886 6887 u8 scheduling_hierarchy[0x8]; 6888 u8 reserved_at_48[0x18]; 6889 6890 u8 scheduling_element_id[0x20]; 6891 6892 u8 reserved_at_80[0x180]; 6893 }; 6894 6895 struct mlx5_ifc_destroy_rqt_out_bits { 6896 u8 status[0x8]; 6897 u8 reserved_at_8[0x18]; 6898 6899 u8 syndrome[0x20]; 6900 6901 u8 reserved_at_40[0x40]; 6902 }; 6903 6904 struct mlx5_ifc_destroy_rqt_in_bits { 6905 u8 opcode[0x10]; 6906 u8 uid[0x10]; 6907 6908 u8 reserved_at_20[0x10]; 6909 u8 op_mod[0x10]; 6910 6911 u8 reserved_at_40[0x8]; 6912 u8 rqtn[0x18]; 6913 6914 u8 reserved_at_60[0x20]; 6915 }; 6916 6917 struct mlx5_ifc_destroy_rq_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_at_8[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_at_40[0x40]; 6924 }; 6925 6926 struct mlx5_ifc_destroy_rq_in_bits { 6927 u8 opcode[0x10]; 6928 u8 uid[0x10]; 6929 6930 u8 reserved_at_20[0x10]; 6931 u8 op_mod[0x10]; 6932 6933 u8 reserved_at_40[0x8]; 6934 u8 rqn[0x18]; 6935 6936 u8 reserved_at_60[0x20]; 6937 }; 6938 6939 struct mlx5_ifc_set_delay_drop_params_in_bits { 6940 u8 opcode[0x10]; 6941 u8 reserved_at_10[0x10]; 6942 6943 u8 reserved_at_20[0x10]; 6944 u8 op_mod[0x10]; 6945 6946 u8 reserved_at_40[0x20]; 6947 6948 u8 reserved_at_60[0x10]; 6949 u8 delay_drop_timeout[0x10]; 6950 }; 6951 6952 struct mlx5_ifc_set_delay_drop_params_out_bits { 6953 u8 status[0x8]; 6954 u8 reserved_at_8[0x18]; 6955 6956 u8 syndrome[0x20]; 6957 6958 u8 reserved_at_40[0x40]; 6959 }; 6960 6961 struct mlx5_ifc_destroy_rmp_out_bits { 6962 u8 status[0x8]; 6963 u8 reserved_at_8[0x18]; 6964 6965 u8 syndrome[0x20]; 6966 6967 u8 reserved_at_40[0x40]; 6968 }; 6969 6970 struct mlx5_ifc_destroy_rmp_in_bits { 6971 u8 opcode[0x10]; 6972 u8 uid[0x10]; 6973 6974 u8 reserved_at_20[0x10]; 6975 u8 op_mod[0x10]; 6976 6977 u8 reserved_at_40[0x8]; 6978 u8 rmpn[0x18]; 6979 6980 u8 reserved_at_60[0x20]; 6981 }; 6982 6983 struct mlx5_ifc_destroy_qp_out_bits { 6984 u8 status[0x8]; 6985 u8 reserved_at_8[0x18]; 6986 6987 u8 syndrome[0x20]; 6988 6989 u8 reserved_at_40[0x40]; 6990 }; 6991 6992 struct mlx5_ifc_destroy_qp_in_bits { 6993 u8 opcode[0x10]; 6994 u8 uid[0x10]; 6995 6996 u8 reserved_at_20[0x10]; 6997 u8 op_mod[0x10]; 6998 6999 u8 reserved_at_40[0x8]; 7000 u8 qpn[0x18]; 7001 7002 u8 reserved_at_60[0x20]; 7003 }; 7004 7005 struct mlx5_ifc_destroy_psv_out_bits { 7006 u8 status[0x8]; 7007 u8 reserved_at_8[0x18]; 7008 7009 u8 syndrome[0x20]; 7010 7011 u8 reserved_at_40[0x40]; 7012 }; 7013 7014 struct mlx5_ifc_destroy_psv_in_bits { 7015 u8 opcode[0x10]; 7016 u8 reserved_at_10[0x10]; 7017 7018 u8 reserved_at_20[0x10]; 7019 u8 op_mod[0x10]; 7020 7021 u8 reserved_at_40[0x8]; 7022 u8 psvn[0x18]; 7023 7024 u8 reserved_at_60[0x20]; 7025 }; 7026 7027 struct mlx5_ifc_destroy_mkey_out_bits { 7028 u8 status[0x8]; 7029 u8 reserved_at_8[0x18]; 7030 7031 u8 syndrome[0x20]; 7032 7033 u8 reserved_at_40[0x40]; 7034 }; 7035 7036 struct mlx5_ifc_destroy_mkey_in_bits { 7037 u8 opcode[0x10]; 7038 u8 reserved_at_10[0x10]; 7039 7040 u8 reserved_at_20[0x10]; 7041 u8 op_mod[0x10]; 7042 7043 u8 reserved_at_40[0x8]; 7044 u8 mkey_index[0x18]; 7045 7046 u8 reserved_at_60[0x20]; 7047 }; 7048 7049 struct mlx5_ifc_destroy_flow_table_out_bits { 7050 u8 status[0x8]; 7051 u8 reserved_at_8[0x18]; 7052 7053 u8 syndrome[0x20]; 7054 7055 u8 reserved_at_40[0x40]; 7056 }; 7057 7058 struct mlx5_ifc_destroy_flow_table_in_bits { 7059 u8 opcode[0x10]; 7060 u8 reserved_at_10[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 other_vport[0x1]; 7066 u8 reserved_at_41[0xf]; 7067 u8 vport_number[0x10]; 7068 7069 u8 reserved_at_60[0x20]; 7070 7071 u8 table_type[0x8]; 7072 u8 reserved_at_88[0x18]; 7073 7074 u8 reserved_at_a0[0x8]; 7075 u8 table_id[0x18]; 7076 7077 u8 reserved_at_c0[0x140]; 7078 }; 7079 7080 struct mlx5_ifc_destroy_flow_group_out_bits { 7081 u8 status[0x8]; 7082 u8 reserved_at_8[0x18]; 7083 7084 u8 syndrome[0x20]; 7085 7086 u8 reserved_at_40[0x40]; 7087 }; 7088 7089 struct mlx5_ifc_destroy_flow_group_in_bits { 7090 u8 opcode[0x10]; 7091 u8 reserved_at_10[0x10]; 7092 7093 u8 reserved_at_20[0x10]; 7094 u8 op_mod[0x10]; 7095 7096 u8 other_vport[0x1]; 7097 u8 reserved_at_41[0xf]; 7098 u8 vport_number[0x10]; 7099 7100 u8 reserved_at_60[0x20]; 7101 7102 u8 table_type[0x8]; 7103 u8 reserved_at_88[0x18]; 7104 7105 u8 reserved_at_a0[0x8]; 7106 u8 table_id[0x18]; 7107 7108 u8 group_id[0x20]; 7109 7110 u8 reserved_at_e0[0x120]; 7111 }; 7112 7113 struct mlx5_ifc_destroy_eq_out_bits { 7114 u8 status[0x8]; 7115 u8 reserved_at_8[0x18]; 7116 7117 u8 syndrome[0x20]; 7118 7119 u8 reserved_at_40[0x40]; 7120 }; 7121 7122 struct mlx5_ifc_destroy_eq_in_bits { 7123 u8 opcode[0x10]; 7124 u8 reserved_at_10[0x10]; 7125 7126 u8 reserved_at_20[0x10]; 7127 u8 op_mod[0x10]; 7128 7129 u8 reserved_at_40[0x18]; 7130 u8 eq_number[0x8]; 7131 7132 u8 reserved_at_60[0x20]; 7133 }; 7134 7135 struct mlx5_ifc_destroy_dct_out_bits { 7136 u8 status[0x8]; 7137 u8 reserved_at_8[0x18]; 7138 7139 u8 syndrome[0x20]; 7140 7141 u8 reserved_at_40[0x40]; 7142 }; 7143 7144 struct mlx5_ifc_destroy_dct_in_bits { 7145 u8 opcode[0x10]; 7146 u8 uid[0x10]; 7147 7148 u8 reserved_at_20[0x10]; 7149 u8 op_mod[0x10]; 7150 7151 u8 reserved_at_40[0x8]; 7152 u8 dctn[0x18]; 7153 7154 u8 reserved_at_60[0x20]; 7155 }; 7156 7157 struct mlx5_ifc_destroy_cq_out_bits { 7158 u8 status[0x8]; 7159 u8 reserved_at_8[0x18]; 7160 7161 u8 syndrome[0x20]; 7162 7163 u8 reserved_at_40[0x40]; 7164 }; 7165 7166 struct mlx5_ifc_destroy_cq_in_bits { 7167 u8 opcode[0x10]; 7168 u8 uid[0x10]; 7169 7170 u8 reserved_at_20[0x10]; 7171 u8 op_mod[0x10]; 7172 7173 u8 reserved_at_40[0x8]; 7174 u8 cqn[0x18]; 7175 7176 u8 reserved_at_60[0x20]; 7177 }; 7178 7179 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7180 u8 status[0x8]; 7181 u8 reserved_at_8[0x18]; 7182 7183 u8 syndrome[0x20]; 7184 7185 u8 reserved_at_40[0x40]; 7186 }; 7187 7188 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7189 u8 opcode[0x10]; 7190 u8 reserved_at_10[0x10]; 7191 7192 u8 reserved_at_20[0x10]; 7193 u8 op_mod[0x10]; 7194 7195 u8 reserved_at_40[0x20]; 7196 7197 u8 reserved_at_60[0x10]; 7198 u8 vxlan_udp_port[0x10]; 7199 }; 7200 7201 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7202 u8 status[0x8]; 7203 u8 reserved_at_8[0x18]; 7204 7205 u8 syndrome[0x20]; 7206 7207 u8 reserved_at_40[0x40]; 7208 }; 7209 7210 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7211 u8 opcode[0x10]; 7212 u8 reserved_at_10[0x10]; 7213 7214 u8 reserved_at_20[0x10]; 7215 u8 op_mod[0x10]; 7216 7217 u8 reserved_at_40[0x60]; 7218 7219 u8 reserved_at_a0[0x8]; 7220 u8 table_index[0x18]; 7221 7222 u8 reserved_at_c0[0x140]; 7223 }; 7224 7225 struct mlx5_ifc_delete_fte_out_bits { 7226 u8 status[0x8]; 7227 u8 reserved_at_8[0x18]; 7228 7229 u8 syndrome[0x20]; 7230 7231 u8 reserved_at_40[0x40]; 7232 }; 7233 7234 struct mlx5_ifc_delete_fte_in_bits { 7235 u8 opcode[0x10]; 7236 u8 reserved_at_10[0x10]; 7237 7238 u8 reserved_at_20[0x10]; 7239 u8 op_mod[0x10]; 7240 7241 u8 other_vport[0x1]; 7242 u8 reserved_at_41[0xf]; 7243 u8 vport_number[0x10]; 7244 7245 u8 reserved_at_60[0x20]; 7246 7247 u8 table_type[0x8]; 7248 u8 reserved_at_88[0x18]; 7249 7250 u8 reserved_at_a0[0x8]; 7251 u8 table_id[0x18]; 7252 7253 u8 reserved_at_c0[0x40]; 7254 7255 u8 flow_index[0x20]; 7256 7257 u8 reserved_at_120[0xe0]; 7258 }; 7259 7260 struct mlx5_ifc_dealloc_xrcd_out_bits { 7261 u8 status[0x8]; 7262 u8 reserved_at_8[0x18]; 7263 7264 u8 syndrome[0x20]; 7265 7266 u8 reserved_at_40[0x40]; 7267 }; 7268 7269 struct mlx5_ifc_dealloc_xrcd_in_bits { 7270 u8 opcode[0x10]; 7271 u8 uid[0x10]; 7272 7273 u8 reserved_at_20[0x10]; 7274 u8 op_mod[0x10]; 7275 7276 u8 reserved_at_40[0x8]; 7277 u8 xrcd[0x18]; 7278 7279 u8 reserved_at_60[0x20]; 7280 }; 7281 7282 struct mlx5_ifc_dealloc_uar_out_bits { 7283 u8 status[0x8]; 7284 u8 reserved_at_8[0x18]; 7285 7286 u8 syndrome[0x20]; 7287 7288 u8 reserved_at_40[0x40]; 7289 }; 7290 7291 struct mlx5_ifc_dealloc_uar_in_bits { 7292 u8 opcode[0x10]; 7293 u8 reserved_at_10[0x10]; 7294 7295 u8 reserved_at_20[0x10]; 7296 u8 op_mod[0x10]; 7297 7298 u8 reserved_at_40[0x8]; 7299 u8 uar[0x18]; 7300 7301 u8 reserved_at_60[0x20]; 7302 }; 7303 7304 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7305 u8 status[0x8]; 7306 u8 reserved_at_8[0x18]; 7307 7308 u8 syndrome[0x20]; 7309 7310 u8 reserved_at_40[0x40]; 7311 }; 7312 7313 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7314 u8 opcode[0x10]; 7315 u8 uid[0x10]; 7316 7317 u8 reserved_at_20[0x10]; 7318 u8 op_mod[0x10]; 7319 7320 u8 reserved_at_40[0x8]; 7321 u8 transport_domain[0x18]; 7322 7323 u8 reserved_at_60[0x20]; 7324 }; 7325 7326 struct mlx5_ifc_dealloc_q_counter_out_bits { 7327 u8 status[0x8]; 7328 u8 reserved_at_8[0x18]; 7329 7330 u8 syndrome[0x20]; 7331 7332 u8 reserved_at_40[0x40]; 7333 }; 7334 7335 struct mlx5_ifc_dealloc_q_counter_in_bits { 7336 u8 opcode[0x10]; 7337 u8 reserved_at_10[0x10]; 7338 7339 u8 reserved_at_20[0x10]; 7340 u8 op_mod[0x10]; 7341 7342 u8 reserved_at_40[0x18]; 7343 u8 counter_set_id[0x8]; 7344 7345 u8 reserved_at_60[0x20]; 7346 }; 7347 7348 struct mlx5_ifc_dealloc_pd_out_bits { 7349 u8 status[0x8]; 7350 u8 reserved_at_8[0x18]; 7351 7352 u8 syndrome[0x20]; 7353 7354 u8 reserved_at_40[0x40]; 7355 }; 7356 7357 struct mlx5_ifc_dealloc_pd_in_bits { 7358 u8 opcode[0x10]; 7359 u8 uid[0x10]; 7360 7361 u8 reserved_at_20[0x10]; 7362 u8 op_mod[0x10]; 7363 7364 u8 reserved_at_40[0x8]; 7365 u8 pd[0x18]; 7366 7367 u8 reserved_at_60[0x20]; 7368 }; 7369 7370 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7371 u8 status[0x8]; 7372 u8 reserved_at_8[0x18]; 7373 7374 u8 syndrome[0x20]; 7375 7376 u8 reserved_at_40[0x40]; 7377 }; 7378 7379 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7380 u8 opcode[0x10]; 7381 u8 reserved_at_10[0x10]; 7382 7383 u8 reserved_at_20[0x10]; 7384 u8 op_mod[0x10]; 7385 7386 u8 flow_counter_id[0x20]; 7387 7388 u8 reserved_at_60[0x20]; 7389 }; 7390 7391 struct mlx5_ifc_create_xrq_out_bits { 7392 u8 status[0x8]; 7393 u8 reserved_at_8[0x18]; 7394 7395 u8 syndrome[0x20]; 7396 7397 u8 reserved_at_40[0x8]; 7398 u8 xrqn[0x18]; 7399 7400 u8 reserved_at_60[0x20]; 7401 }; 7402 7403 struct mlx5_ifc_create_xrq_in_bits { 7404 u8 opcode[0x10]; 7405 u8 uid[0x10]; 7406 7407 u8 reserved_at_20[0x10]; 7408 u8 op_mod[0x10]; 7409 7410 u8 reserved_at_40[0x40]; 7411 7412 struct mlx5_ifc_xrqc_bits xrq_context; 7413 }; 7414 7415 struct mlx5_ifc_create_xrc_srq_out_bits { 7416 u8 status[0x8]; 7417 u8 reserved_at_8[0x18]; 7418 7419 u8 syndrome[0x20]; 7420 7421 u8 reserved_at_40[0x8]; 7422 u8 xrc_srqn[0x18]; 7423 7424 u8 reserved_at_60[0x20]; 7425 }; 7426 7427 struct mlx5_ifc_create_xrc_srq_in_bits { 7428 u8 opcode[0x10]; 7429 u8 uid[0x10]; 7430 7431 u8 reserved_at_20[0x10]; 7432 u8 op_mod[0x10]; 7433 7434 u8 reserved_at_40[0x40]; 7435 7436 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7437 7438 u8 reserved_at_280[0x60]; 7439 7440 u8 xrc_srq_umem_valid[0x1]; 7441 u8 reserved_at_2e1[0x1f]; 7442 7443 u8 reserved_at_300[0x580]; 7444 7445 u8 pas[0][0x40]; 7446 }; 7447 7448 struct mlx5_ifc_create_tis_out_bits { 7449 u8 status[0x8]; 7450 u8 reserved_at_8[0x18]; 7451 7452 u8 syndrome[0x20]; 7453 7454 u8 reserved_at_40[0x8]; 7455 u8 tisn[0x18]; 7456 7457 u8 reserved_at_60[0x20]; 7458 }; 7459 7460 struct mlx5_ifc_create_tis_in_bits { 7461 u8 opcode[0x10]; 7462 u8 uid[0x10]; 7463 7464 u8 reserved_at_20[0x10]; 7465 u8 op_mod[0x10]; 7466 7467 u8 reserved_at_40[0xc0]; 7468 7469 struct mlx5_ifc_tisc_bits ctx; 7470 }; 7471 7472 struct mlx5_ifc_create_tir_out_bits { 7473 u8 status[0x8]; 7474 u8 icm_address_63_40[0x18]; 7475 7476 u8 syndrome[0x20]; 7477 7478 u8 icm_address_39_32[0x8]; 7479 u8 tirn[0x18]; 7480 7481 u8 icm_address_31_0[0x20]; 7482 }; 7483 7484 struct mlx5_ifc_create_tir_in_bits { 7485 u8 opcode[0x10]; 7486 u8 uid[0x10]; 7487 7488 u8 reserved_at_20[0x10]; 7489 u8 op_mod[0x10]; 7490 7491 u8 reserved_at_40[0xc0]; 7492 7493 struct mlx5_ifc_tirc_bits ctx; 7494 }; 7495 7496 struct mlx5_ifc_create_srq_out_bits { 7497 u8 status[0x8]; 7498 u8 reserved_at_8[0x18]; 7499 7500 u8 syndrome[0x20]; 7501 7502 u8 reserved_at_40[0x8]; 7503 u8 srqn[0x18]; 7504 7505 u8 reserved_at_60[0x20]; 7506 }; 7507 7508 struct mlx5_ifc_create_srq_in_bits { 7509 u8 opcode[0x10]; 7510 u8 uid[0x10]; 7511 7512 u8 reserved_at_20[0x10]; 7513 u8 op_mod[0x10]; 7514 7515 u8 reserved_at_40[0x40]; 7516 7517 struct mlx5_ifc_srqc_bits srq_context_entry; 7518 7519 u8 reserved_at_280[0x600]; 7520 7521 u8 pas[0][0x40]; 7522 }; 7523 7524 struct mlx5_ifc_create_sq_out_bits { 7525 u8 status[0x8]; 7526 u8 reserved_at_8[0x18]; 7527 7528 u8 syndrome[0x20]; 7529 7530 u8 reserved_at_40[0x8]; 7531 u8 sqn[0x18]; 7532 7533 u8 reserved_at_60[0x20]; 7534 }; 7535 7536 struct mlx5_ifc_create_sq_in_bits { 7537 u8 opcode[0x10]; 7538 u8 uid[0x10]; 7539 7540 u8 reserved_at_20[0x10]; 7541 u8 op_mod[0x10]; 7542 7543 u8 reserved_at_40[0xc0]; 7544 7545 struct mlx5_ifc_sqc_bits ctx; 7546 }; 7547 7548 struct mlx5_ifc_create_scheduling_element_out_bits { 7549 u8 status[0x8]; 7550 u8 reserved_at_8[0x18]; 7551 7552 u8 syndrome[0x20]; 7553 7554 u8 reserved_at_40[0x40]; 7555 7556 u8 scheduling_element_id[0x20]; 7557 7558 u8 reserved_at_a0[0x160]; 7559 }; 7560 7561 struct mlx5_ifc_create_scheduling_element_in_bits { 7562 u8 opcode[0x10]; 7563 u8 reserved_at_10[0x10]; 7564 7565 u8 reserved_at_20[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 scheduling_hierarchy[0x8]; 7569 u8 reserved_at_48[0x18]; 7570 7571 u8 reserved_at_60[0xa0]; 7572 7573 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7574 7575 u8 reserved_at_300[0x100]; 7576 }; 7577 7578 struct mlx5_ifc_create_rqt_out_bits { 7579 u8 status[0x8]; 7580 u8 reserved_at_8[0x18]; 7581 7582 u8 syndrome[0x20]; 7583 7584 u8 reserved_at_40[0x8]; 7585 u8 rqtn[0x18]; 7586 7587 u8 reserved_at_60[0x20]; 7588 }; 7589 7590 struct mlx5_ifc_create_rqt_in_bits { 7591 u8 opcode[0x10]; 7592 u8 uid[0x10]; 7593 7594 u8 reserved_at_20[0x10]; 7595 u8 op_mod[0x10]; 7596 7597 u8 reserved_at_40[0xc0]; 7598 7599 struct mlx5_ifc_rqtc_bits rqt_context; 7600 }; 7601 7602 struct mlx5_ifc_create_rq_out_bits { 7603 u8 status[0x8]; 7604 u8 reserved_at_8[0x18]; 7605 7606 u8 syndrome[0x20]; 7607 7608 u8 reserved_at_40[0x8]; 7609 u8 rqn[0x18]; 7610 7611 u8 reserved_at_60[0x20]; 7612 }; 7613 7614 struct mlx5_ifc_create_rq_in_bits { 7615 u8 opcode[0x10]; 7616 u8 uid[0x10]; 7617 7618 u8 reserved_at_20[0x10]; 7619 u8 op_mod[0x10]; 7620 7621 u8 reserved_at_40[0xc0]; 7622 7623 struct mlx5_ifc_rqc_bits ctx; 7624 }; 7625 7626 struct mlx5_ifc_create_rmp_out_bits { 7627 u8 status[0x8]; 7628 u8 reserved_at_8[0x18]; 7629 7630 u8 syndrome[0x20]; 7631 7632 u8 reserved_at_40[0x8]; 7633 u8 rmpn[0x18]; 7634 7635 u8 reserved_at_60[0x20]; 7636 }; 7637 7638 struct mlx5_ifc_create_rmp_in_bits { 7639 u8 opcode[0x10]; 7640 u8 uid[0x10]; 7641 7642 u8 reserved_at_20[0x10]; 7643 u8 op_mod[0x10]; 7644 7645 u8 reserved_at_40[0xc0]; 7646 7647 struct mlx5_ifc_rmpc_bits ctx; 7648 }; 7649 7650 struct mlx5_ifc_create_qp_out_bits { 7651 u8 status[0x8]; 7652 u8 reserved_at_8[0x18]; 7653 7654 u8 syndrome[0x20]; 7655 7656 u8 reserved_at_40[0x8]; 7657 u8 qpn[0x18]; 7658 7659 u8 reserved_at_60[0x20]; 7660 }; 7661 7662 struct mlx5_ifc_create_qp_in_bits { 7663 u8 opcode[0x10]; 7664 u8 uid[0x10]; 7665 7666 u8 reserved_at_20[0x10]; 7667 u8 op_mod[0x10]; 7668 7669 u8 reserved_at_40[0x40]; 7670 7671 u8 opt_param_mask[0x20]; 7672 7673 u8 reserved_at_a0[0x20]; 7674 7675 struct mlx5_ifc_qpc_bits qpc; 7676 7677 u8 reserved_at_800[0x60]; 7678 7679 u8 wq_umem_valid[0x1]; 7680 u8 reserved_at_861[0x1f]; 7681 7682 u8 pas[0][0x40]; 7683 }; 7684 7685 struct mlx5_ifc_create_psv_out_bits { 7686 u8 status[0x8]; 7687 u8 reserved_at_8[0x18]; 7688 7689 u8 syndrome[0x20]; 7690 7691 u8 reserved_at_40[0x40]; 7692 7693 u8 reserved_at_80[0x8]; 7694 u8 psv0_index[0x18]; 7695 7696 u8 reserved_at_a0[0x8]; 7697 u8 psv1_index[0x18]; 7698 7699 u8 reserved_at_c0[0x8]; 7700 u8 psv2_index[0x18]; 7701 7702 u8 reserved_at_e0[0x8]; 7703 u8 psv3_index[0x18]; 7704 }; 7705 7706 struct mlx5_ifc_create_psv_in_bits { 7707 u8 opcode[0x10]; 7708 u8 reserved_at_10[0x10]; 7709 7710 u8 reserved_at_20[0x10]; 7711 u8 op_mod[0x10]; 7712 7713 u8 num_psv[0x4]; 7714 u8 reserved_at_44[0x4]; 7715 u8 pd[0x18]; 7716 7717 u8 reserved_at_60[0x20]; 7718 }; 7719 7720 struct mlx5_ifc_create_mkey_out_bits { 7721 u8 status[0x8]; 7722 u8 reserved_at_8[0x18]; 7723 7724 u8 syndrome[0x20]; 7725 7726 u8 reserved_at_40[0x8]; 7727 u8 mkey_index[0x18]; 7728 7729 u8 reserved_at_60[0x20]; 7730 }; 7731 7732 struct mlx5_ifc_create_mkey_in_bits { 7733 u8 opcode[0x10]; 7734 u8 reserved_at_10[0x10]; 7735 7736 u8 reserved_at_20[0x10]; 7737 u8 op_mod[0x10]; 7738 7739 u8 reserved_at_40[0x20]; 7740 7741 u8 pg_access[0x1]; 7742 u8 mkey_umem_valid[0x1]; 7743 u8 reserved_at_62[0x1e]; 7744 7745 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7746 7747 u8 reserved_at_280[0x80]; 7748 7749 u8 translations_octword_actual_size[0x20]; 7750 7751 u8 reserved_at_320[0x560]; 7752 7753 u8 klm_pas_mtt[0][0x20]; 7754 }; 7755 7756 enum { 7757 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7758 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7759 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7760 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7761 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7762 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7763 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7764 }; 7765 7766 struct mlx5_ifc_create_flow_table_out_bits { 7767 u8 status[0x8]; 7768 u8 icm_address_63_40[0x18]; 7769 7770 u8 syndrome[0x20]; 7771 7772 u8 icm_address_39_32[0x8]; 7773 u8 table_id[0x18]; 7774 7775 u8 icm_address_31_0[0x20]; 7776 }; 7777 7778 struct mlx5_ifc_create_flow_table_in_bits { 7779 u8 opcode[0x10]; 7780 u8 reserved_at_10[0x10]; 7781 7782 u8 reserved_at_20[0x10]; 7783 u8 op_mod[0x10]; 7784 7785 u8 other_vport[0x1]; 7786 u8 reserved_at_41[0xf]; 7787 u8 vport_number[0x10]; 7788 7789 u8 reserved_at_60[0x20]; 7790 7791 u8 table_type[0x8]; 7792 u8 reserved_at_88[0x18]; 7793 7794 u8 reserved_at_a0[0x20]; 7795 7796 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7797 }; 7798 7799 struct mlx5_ifc_create_flow_group_out_bits { 7800 u8 status[0x8]; 7801 u8 reserved_at_8[0x18]; 7802 7803 u8 syndrome[0x20]; 7804 7805 u8 reserved_at_40[0x8]; 7806 u8 group_id[0x18]; 7807 7808 u8 reserved_at_60[0x20]; 7809 }; 7810 7811 enum { 7812 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7813 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7814 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7815 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7816 }; 7817 7818 struct mlx5_ifc_create_flow_group_in_bits { 7819 u8 opcode[0x10]; 7820 u8 reserved_at_10[0x10]; 7821 7822 u8 reserved_at_20[0x10]; 7823 u8 op_mod[0x10]; 7824 7825 u8 other_vport[0x1]; 7826 u8 reserved_at_41[0xf]; 7827 u8 vport_number[0x10]; 7828 7829 u8 reserved_at_60[0x20]; 7830 7831 u8 table_type[0x8]; 7832 u8 reserved_at_88[0x18]; 7833 7834 u8 reserved_at_a0[0x8]; 7835 u8 table_id[0x18]; 7836 7837 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7838 7839 u8 reserved_at_c1[0x1f]; 7840 7841 u8 start_flow_index[0x20]; 7842 7843 u8 reserved_at_100[0x20]; 7844 7845 u8 end_flow_index[0x20]; 7846 7847 u8 reserved_at_140[0xa0]; 7848 7849 u8 reserved_at_1e0[0x18]; 7850 u8 match_criteria_enable[0x8]; 7851 7852 struct mlx5_ifc_fte_match_param_bits match_criteria; 7853 7854 u8 reserved_at_1200[0xe00]; 7855 }; 7856 7857 struct mlx5_ifc_create_eq_out_bits { 7858 u8 status[0x8]; 7859 u8 reserved_at_8[0x18]; 7860 7861 u8 syndrome[0x20]; 7862 7863 u8 reserved_at_40[0x18]; 7864 u8 eq_number[0x8]; 7865 7866 u8 reserved_at_60[0x20]; 7867 }; 7868 7869 struct mlx5_ifc_create_eq_in_bits { 7870 u8 opcode[0x10]; 7871 u8 uid[0x10]; 7872 7873 u8 reserved_at_20[0x10]; 7874 u8 op_mod[0x10]; 7875 7876 u8 reserved_at_40[0x40]; 7877 7878 struct mlx5_ifc_eqc_bits eq_context_entry; 7879 7880 u8 reserved_at_280[0x40]; 7881 7882 u8 event_bitmask[4][0x40]; 7883 7884 u8 reserved_at_3c0[0x4c0]; 7885 7886 u8 pas[0][0x40]; 7887 }; 7888 7889 struct mlx5_ifc_create_dct_out_bits { 7890 u8 status[0x8]; 7891 u8 reserved_at_8[0x18]; 7892 7893 u8 syndrome[0x20]; 7894 7895 u8 reserved_at_40[0x8]; 7896 u8 dctn[0x18]; 7897 7898 u8 reserved_at_60[0x20]; 7899 }; 7900 7901 struct mlx5_ifc_create_dct_in_bits { 7902 u8 opcode[0x10]; 7903 u8 uid[0x10]; 7904 7905 u8 reserved_at_20[0x10]; 7906 u8 op_mod[0x10]; 7907 7908 u8 reserved_at_40[0x40]; 7909 7910 struct mlx5_ifc_dctc_bits dct_context_entry; 7911 7912 u8 reserved_at_280[0x180]; 7913 }; 7914 7915 struct mlx5_ifc_create_cq_out_bits { 7916 u8 status[0x8]; 7917 u8 reserved_at_8[0x18]; 7918 7919 u8 syndrome[0x20]; 7920 7921 u8 reserved_at_40[0x8]; 7922 u8 cqn[0x18]; 7923 7924 u8 reserved_at_60[0x20]; 7925 }; 7926 7927 struct mlx5_ifc_create_cq_in_bits { 7928 u8 opcode[0x10]; 7929 u8 uid[0x10]; 7930 7931 u8 reserved_at_20[0x10]; 7932 u8 op_mod[0x10]; 7933 7934 u8 reserved_at_40[0x40]; 7935 7936 struct mlx5_ifc_cqc_bits cq_context; 7937 7938 u8 reserved_at_280[0x60]; 7939 7940 u8 cq_umem_valid[0x1]; 7941 u8 reserved_at_2e1[0x59f]; 7942 7943 u8 pas[0][0x40]; 7944 }; 7945 7946 struct mlx5_ifc_config_int_moderation_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x4]; 7953 u8 min_delay[0xc]; 7954 u8 int_vector[0x10]; 7955 7956 u8 reserved_at_60[0x20]; 7957 }; 7958 7959 enum { 7960 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7961 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7962 }; 7963 7964 struct mlx5_ifc_config_int_moderation_in_bits { 7965 u8 opcode[0x10]; 7966 u8 reserved_at_10[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x4]; 7972 u8 min_delay[0xc]; 7973 u8 int_vector[0x10]; 7974 7975 u8 reserved_at_60[0x20]; 7976 }; 7977 7978 struct mlx5_ifc_attach_to_mcg_out_bits { 7979 u8 status[0x8]; 7980 u8 reserved_at_8[0x18]; 7981 7982 u8 syndrome[0x20]; 7983 7984 u8 reserved_at_40[0x40]; 7985 }; 7986 7987 struct mlx5_ifc_attach_to_mcg_in_bits { 7988 u8 opcode[0x10]; 7989 u8 uid[0x10]; 7990 7991 u8 reserved_at_20[0x10]; 7992 u8 op_mod[0x10]; 7993 7994 u8 reserved_at_40[0x8]; 7995 u8 qpn[0x18]; 7996 7997 u8 reserved_at_60[0x20]; 7998 7999 u8 multicast_gid[16][0x8]; 8000 }; 8001 8002 struct mlx5_ifc_arm_xrq_out_bits { 8003 u8 status[0x8]; 8004 u8 reserved_at_8[0x18]; 8005 8006 u8 syndrome[0x20]; 8007 8008 u8 reserved_at_40[0x40]; 8009 }; 8010 8011 struct mlx5_ifc_arm_xrq_in_bits { 8012 u8 opcode[0x10]; 8013 u8 reserved_at_10[0x10]; 8014 8015 u8 reserved_at_20[0x10]; 8016 u8 op_mod[0x10]; 8017 8018 u8 reserved_at_40[0x8]; 8019 u8 xrqn[0x18]; 8020 8021 u8 reserved_at_60[0x10]; 8022 u8 lwm[0x10]; 8023 }; 8024 8025 struct mlx5_ifc_arm_xrc_srq_out_bits { 8026 u8 status[0x8]; 8027 u8 reserved_at_8[0x18]; 8028 8029 u8 syndrome[0x20]; 8030 8031 u8 reserved_at_40[0x40]; 8032 }; 8033 8034 enum { 8035 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8036 }; 8037 8038 struct mlx5_ifc_arm_xrc_srq_in_bits { 8039 u8 opcode[0x10]; 8040 u8 uid[0x10]; 8041 8042 u8 reserved_at_20[0x10]; 8043 u8 op_mod[0x10]; 8044 8045 u8 reserved_at_40[0x8]; 8046 u8 xrc_srqn[0x18]; 8047 8048 u8 reserved_at_60[0x10]; 8049 u8 lwm[0x10]; 8050 }; 8051 8052 struct mlx5_ifc_arm_rq_out_bits { 8053 u8 status[0x8]; 8054 u8 reserved_at_8[0x18]; 8055 8056 u8 syndrome[0x20]; 8057 8058 u8 reserved_at_40[0x40]; 8059 }; 8060 8061 enum { 8062 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8063 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8064 }; 8065 8066 struct mlx5_ifc_arm_rq_in_bits { 8067 u8 opcode[0x10]; 8068 u8 uid[0x10]; 8069 8070 u8 reserved_at_20[0x10]; 8071 u8 op_mod[0x10]; 8072 8073 u8 reserved_at_40[0x8]; 8074 u8 srq_number[0x18]; 8075 8076 u8 reserved_at_60[0x10]; 8077 u8 lwm[0x10]; 8078 }; 8079 8080 struct mlx5_ifc_arm_dct_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x40]; 8087 }; 8088 8089 struct mlx5_ifc_arm_dct_in_bits { 8090 u8 opcode[0x10]; 8091 u8 reserved_at_10[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 reserved_at_40[0x8]; 8097 u8 dct_number[0x18]; 8098 8099 u8 reserved_at_60[0x20]; 8100 }; 8101 8102 struct mlx5_ifc_alloc_xrcd_out_bits { 8103 u8 status[0x8]; 8104 u8 reserved_at_8[0x18]; 8105 8106 u8 syndrome[0x20]; 8107 8108 u8 reserved_at_40[0x8]; 8109 u8 xrcd[0x18]; 8110 8111 u8 reserved_at_60[0x20]; 8112 }; 8113 8114 struct mlx5_ifc_alloc_xrcd_in_bits { 8115 u8 opcode[0x10]; 8116 u8 uid[0x10]; 8117 8118 u8 reserved_at_20[0x10]; 8119 u8 op_mod[0x10]; 8120 8121 u8 reserved_at_40[0x40]; 8122 }; 8123 8124 struct mlx5_ifc_alloc_uar_out_bits { 8125 u8 status[0x8]; 8126 u8 reserved_at_8[0x18]; 8127 8128 u8 syndrome[0x20]; 8129 8130 u8 reserved_at_40[0x8]; 8131 u8 uar[0x18]; 8132 8133 u8 reserved_at_60[0x20]; 8134 }; 8135 8136 struct mlx5_ifc_alloc_uar_in_bits { 8137 u8 opcode[0x10]; 8138 u8 reserved_at_10[0x10]; 8139 8140 u8 reserved_at_20[0x10]; 8141 u8 op_mod[0x10]; 8142 8143 u8 reserved_at_40[0x40]; 8144 }; 8145 8146 struct mlx5_ifc_alloc_transport_domain_out_bits { 8147 u8 status[0x8]; 8148 u8 reserved_at_8[0x18]; 8149 8150 u8 syndrome[0x20]; 8151 8152 u8 reserved_at_40[0x8]; 8153 u8 transport_domain[0x18]; 8154 8155 u8 reserved_at_60[0x20]; 8156 }; 8157 8158 struct mlx5_ifc_alloc_transport_domain_in_bits { 8159 u8 opcode[0x10]; 8160 u8 uid[0x10]; 8161 8162 u8 reserved_at_20[0x10]; 8163 u8 op_mod[0x10]; 8164 8165 u8 reserved_at_40[0x40]; 8166 }; 8167 8168 struct mlx5_ifc_alloc_q_counter_out_bits { 8169 u8 status[0x8]; 8170 u8 reserved_at_8[0x18]; 8171 8172 u8 syndrome[0x20]; 8173 8174 u8 reserved_at_40[0x18]; 8175 u8 counter_set_id[0x8]; 8176 8177 u8 reserved_at_60[0x20]; 8178 }; 8179 8180 struct mlx5_ifc_alloc_q_counter_in_bits { 8181 u8 opcode[0x10]; 8182 u8 uid[0x10]; 8183 8184 u8 reserved_at_20[0x10]; 8185 u8 op_mod[0x10]; 8186 8187 u8 reserved_at_40[0x40]; 8188 }; 8189 8190 struct mlx5_ifc_alloc_pd_out_bits { 8191 u8 status[0x8]; 8192 u8 reserved_at_8[0x18]; 8193 8194 u8 syndrome[0x20]; 8195 8196 u8 reserved_at_40[0x8]; 8197 u8 pd[0x18]; 8198 8199 u8 reserved_at_60[0x20]; 8200 }; 8201 8202 struct mlx5_ifc_alloc_pd_in_bits { 8203 u8 opcode[0x10]; 8204 u8 uid[0x10]; 8205 8206 u8 reserved_at_20[0x10]; 8207 u8 op_mod[0x10]; 8208 8209 u8 reserved_at_40[0x40]; 8210 }; 8211 8212 struct mlx5_ifc_alloc_flow_counter_out_bits { 8213 u8 status[0x8]; 8214 u8 reserved_at_8[0x18]; 8215 8216 u8 syndrome[0x20]; 8217 8218 u8 flow_counter_id[0x20]; 8219 8220 u8 reserved_at_60[0x20]; 8221 }; 8222 8223 struct mlx5_ifc_alloc_flow_counter_in_bits { 8224 u8 opcode[0x10]; 8225 u8 reserved_at_10[0x10]; 8226 8227 u8 reserved_at_20[0x10]; 8228 u8 op_mod[0x10]; 8229 8230 u8 reserved_at_40[0x38]; 8231 u8 flow_counter_bulk[0x8]; 8232 }; 8233 8234 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8235 u8 status[0x8]; 8236 u8 reserved_at_8[0x18]; 8237 8238 u8 syndrome[0x20]; 8239 8240 u8 reserved_at_40[0x40]; 8241 }; 8242 8243 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8244 u8 opcode[0x10]; 8245 u8 reserved_at_10[0x10]; 8246 8247 u8 reserved_at_20[0x10]; 8248 u8 op_mod[0x10]; 8249 8250 u8 reserved_at_40[0x20]; 8251 8252 u8 reserved_at_60[0x10]; 8253 u8 vxlan_udp_port[0x10]; 8254 }; 8255 8256 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8257 u8 status[0x8]; 8258 u8 reserved_at_8[0x18]; 8259 8260 u8 syndrome[0x20]; 8261 8262 u8 reserved_at_40[0x40]; 8263 }; 8264 8265 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8266 u8 opcode[0x10]; 8267 u8 reserved_at_10[0x10]; 8268 8269 u8 reserved_at_20[0x10]; 8270 u8 op_mod[0x10]; 8271 8272 u8 reserved_at_40[0x10]; 8273 u8 rate_limit_index[0x10]; 8274 8275 u8 reserved_at_60[0x20]; 8276 8277 u8 rate_limit[0x20]; 8278 8279 u8 burst_upper_bound[0x20]; 8280 8281 u8 reserved_at_c0[0x10]; 8282 u8 typical_packet_size[0x10]; 8283 8284 u8 reserved_at_e0[0x120]; 8285 }; 8286 8287 struct mlx5_ifc_access_register_out_bits { 8288 u8 status[0x8]; 8289 u8 reserved_at_8[0x18]; 8290 8291 u8 syndrome[0x20]; 8292 8293 u8 reserved_at_40[0x40]; 8294 8295 u8 register_data[0][0x20]; 8296 }; 8297 8298 enum { 8299 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8300 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8301 }; 8302 8303 struct mlx5_ifc_access_register_in_bits { 8304 u8 opcode[0x10]; 8305 u8 reserved_at_10[0x10]; 8306 8307 u8 reserved_at_20[0x10]; 8308 u8 op_mod[0x10]; 8309 8310 u8 reserved_at_40[0x10]; 8311 u8 register_id[0x10]; 8312 8313 u8 argument[0x20]; 8314 8315 u8 register_data[0][0x20]; 8316 }; 8317 8318 struct mlx5_ifc_sltp_reg_bits { 8319 u8 status[0x4]; 8320 u8 version[0x4]; 8321 u8 local_port[0x8]; 8322 u8 pnat[0x2]; 8323 u8 reserved_at_12[0x2]; 8324 u8 lane[0x4]; 8325 u8 reserved_at_18[0x8]; 8326 8327 u8 reserved_at_20[0x20]; 8328 8329 u8 reserved_at_40[0x7]; 8330 u8 polarity[0x1]; 8331 u8 ob_tap0[0x8]; 8332 u8 ob_tap1[0x8]; 8333 u8 ob_tap2[0x8]; 8334 8335 u8 reserved_at_60[0xc]; 8336 u8 ob_preemp_mode[0x4]; 8337 u8 ob_reg[0x8]; 8338 u8 ob_bias[0x8]; 8339 8340 u8 reserved_at_80[0x20]; 8341 }; 8342 8343 struct mlx5_ifc_slrg_reg_bits { 8344 u8 status[0x4]; 8345 u8 version[0x4]; 8346 u8 local_port[0x8]; 8347 u8 pnat[0x2]; 8348 u8 reserved_at_12[0x2]; 8349 u8 lane[0x4]; 8350 u8 reserved_at_18[0x8]; 8351 8352 u8 time_to_link_up[0x10]; 8353 u8 reserved_at_30[0xc]; 8354 u8 grade_lane_speed[0x4]; 8355 8356 u8 grade_version[0x8]; 8357 u8 grade[0x18]; 8358 8359 u8 reserved_at_60[0x4]; 8360 u8 height_grade_type[0x4]; 8361 u8 height_grade[0x18]; 8362 8363 u8 height_dz[0x10]; 8364 u8 height_dv[0x10]; 8365 8366 u8 reserved_at_a0[0x10]; 8367 u8 height_sigma[0x10]; 8368 8369 u8 reserved_at_c0[0x20]; 8370 8371 u8 reserved_at_e0[0x4]; 8372 u8 phase_grade_type[0x4]; 8373 u8 phase_grade[0x18]; 8374 8375 u8 reserved_at_100[0x8]; 8376 u8 phase_eo_pos[0x8]; 8377 u8 reserved_at_110[0x8]; 8378 u8 phase_eo_neg[0x8]; 8379 8380 u8 ffe_set_tested[0x10]; 8381 u8 test_errors_per_lane[0x10]; 8382 }; 8383 8384 struct mlx5_ifc_pvlc_reg_bits { 8385 u8 reserved_at_0[0x8]; 8386 u8 local_port[0x8]; 8387 u8 reserved_at_10[0x10]; 8388 8389 u8 reserved_at_20[0x1c]; 8390 u8 vl_hw_cap[0x4]; 8391 8392 u8 reserved_at_40[0x1c]; 8393 u8 vl_admin[0x4]; 8394 8395 u8 reserved_at_60[0x1c]; 8396 u8 vl_operational[0x4]; 8397 }; 8398 8399 struct mlx5_ifc_pude_reg_bits { 8400 u8 swid[0x8]; 8401 u8 local_port[0x8]; 8402 u8 reserved_at_10[0x4]; 8403 u8 admin_status[0x4]; 8404 u8 reserved_at_18[0x4]; 8405 u8 oper_status[0x4]; 8406 8407 u8 reserved_at_20[0x60]; 8408 }; 8409 8410 struct mlx5_ifc_ptys_reg_bits { 8411 u8 reserved_at_0[0x1]; 8412 u8 an_disable_admin[0x1]; 8413 u8 an_disable_cap[0x1]; 8414 u8 reserved_at_3[0x5]; 8415 u8 local_port[0x8]; 8416 u8 reserved_at_10[0xd]; 8417 u8 proto_mask[0x3]; 8418 8419 u8 an_status[0x4]; 8420 u8 reserved_at_24[0x1c]; 8421 8422 u8 ext_eth_proto_capability[0x20]; 8423 8424 u8 eth_proto_capability[0x20]; 8425 8426 u8 ib_link_width_capability[0x10]; 8427 u8 ib_proto_capability[0x10]; 8428 8429 u8 ext_eth_proto_admin[0x20]; 8430 8431 u8 eth_proto_admin[0x20]; 8432 8433 u8 ib_link_width_admin[0x10]; 8434 u8 ib_proto_admin[0x10]; 8435 8436 u8 ext_eth_proto_oper[0x20]; 8437 8438 u8 eth_proto_oper[0x20]; 8439 8440 u8 ib_link_width_oper[0x10]; 8441 u8 ib_proto_oper[0x10]; 8442 8443 u8 reserved_at_160[0x1c]; 8444 u8 connector_type[0x4]; 8445 8446 u8 eth_proto_lp_advertise[0x20]; 8447 8448 u8 reserved_at_1a0[0x60]; 8449 }; 8450 8451 struct mlx5_ifc_mlcr_reg_bits { 8452 u8 reserved_at_0[0x8]; 8453 u8 local_port[0x8]; 8454 u8 reserved_at_10[0x20]; 8455 8456 u8 beacon_duration[0x10]; 8457 u8 reserved_at_40[0x10]; 8458 8459 u8 beacon_remain[0x10]; 8460 }; 8461 8462 struct mlx5_ifc_ptas_reg_bits { 8463 u8 reserved_at_0[0x20]; 8464 8465 u8 algorithm_options[0x10]; 8466 u8 reserved_at_30[0x4]; 8467 u8 repetitions_mode[0x4]; 8468 u8 num_of_repetitions[0x8]; 8469 8470 u8 grade_version[0x8]; 8471 u8 height_grade_type[0x4]; 8472 u8 phase_grade_type[0x4]; 8473 u8 height_grade_weight[0x8]; 8474 u8 phase_grade_weight[0x8]; 8475 8476 u8 gisim_measure_bits[0x10]; 8477 u8 adaptive_tap_measure_bits[0x10]; 8478 8479 u8 ber_bath_high_error_threshold[0x10]; 8480 u8 ber_bath_mid_error_threshold[0x10]; 8481 8482 u8 ber_bath_low_error_threshold[0x10]; 8483 u8 one_ratio_high_threshold[0x10]; 8484 8485 u8 one_ratio_high_mid_threshold[0x10]; 8486 u8 one_ratio_low_mid_threshold[0x10]; 8487 8488 u8 one_ratio_low_threshold[0x10]; 8489 u8 ndeo_error_threshold[0x10]; 8490 8491 u8 mixer_offset_step_size[0x10]; 8492 u8 reserved_at_110[0x8]; 8493 u8 mix90_phase_for_voltage_bath[0x8]; 8494 8495 u8 mixer_offset_start[0x10]; 8496 u8 mixer_offset_end[0x10]; 8497 8498 u8 reserved_at_140[0x15]; 8499 u8 ber_test_time[0xb]; 8500 }; 8501 8502 struct mlx5_ifc_pspa_reg_bits { 8503 u8 swid[0x8]; 8504 u8 local_port[0x8]; 8505 u8 sub_port[0x8]; 8506 u8 reserved_at_18[0x8]; 8507 8508 u8 reserved_at_20[0x20]; 8509 }; 8510 8511 struct mlx5_ifc_pqdr_reg_bits { 8512 u8 reserved_at_0[0x8]; 8513 u8 local_port[0x8]; 8514 u8 reserved_at_10[0x5]; 8515 u8 prio[0x3]; 8516 u8 reserved_at_18[0x6]; 8517 u8 mode[0x2]; 8518 8519 u8 reserved_at_20[0x20]; 8520 8521 u8 reserved_at_40[0x10]; 8522 u8 min_threshold[0x10]; 8523 8524 u8 reserved_at_60[0x10]; 8525 u8 max_threshold[0x10]; 8526 8527 u8 reserved_at_80[0x10]; 8528 u8 mark_probability_denominator[0x10]; 8529 8530 u8 reserved_at_a0[0x60]; 8531 }; 8532 8533 struct mlx5_ifc_ppsc_reg_bits { 8534 u8 reserved_at_0[0x8]; 8535 u8 local_port[0x8]; 8536 u8 reserved_at_10[0x10]; 8537 8538 u8 reserved_at_20[0x60]; 8539 8540 u8 reserved_at_80[0x1c]; 8541 u8 wrps_admin[0x4]; 8542 8543 u8 reserved_at_a0[0x1c]; 8544 u8 wrps_status[0x4]; 8545 8546 u8 reserved_at_c0[0x8]; 8547 u8 up_threshold[0x8]; 8548 u8 reserved_at_d0[0x8]; 8549 u8 down_threshold[0x8]; 8550 8551 u8 reserved_at_e0[0x20]; 8552 8553 u8 reserved_at_100[0x1c]; 8554 u8 srps_admin[0x4]; 8555 8556 u8 reserved_at_120[0x1c]; 8557 u8 srps_status[0x4]; 8558 8559 u8 reserved_at_140[0x40]; 8560 }; 8561 8562 struct mlx5_ifc_pplr_reg_bits { 8563 u8 reserved_at_0[0x8]; 8564 u8 local_port[0x8]; 8565 u8 reserved_at_10[0x10]; 8566 8567 u8 reserved_at_20[0x8]; 8568 u8 lb_cap[0x8]; 8569 u8 reserved_at_30[0x8]; 8570 u8 lb_en[0x8]; 8571 }; 8572 8573 struct mlx5_ifc_pplm_reg_bits { 8574 u8 reserved_at_0[0x8]; 8575 u8 local_port[0x8]; 8576 u8 reserved_at_10[0x10]; 8577 8578 u8 reserved_at_20[0x20]; 8579 8580 u8 port_profile_mode[0x8]; 8581 u8 static_port_profile[0x8]; 8582 u8 active_port_profile[0x8]; 8583 u8 reserved_at_58[0x8]; 8584 8585 u8 retransmission_active[0x8]; 8586 u8 fec_mode_active[0x18]; 8587 8588 u8 rs_fec_correction_bypass_cap[0x4]; 8589 u8 reserved_at_84[0x8]; 8590 u8 fec_override_cap_56g[0x4]; 8591 u8 fec_override_cap_100g[0x4]; 8592 u8 fec_override_cap_50g[0x4]; 8593 u8 fec_override_cap_25g[0x4]; 8594 u8 fec_override_cap_10g_40g[0x4]; 8595 8596 u8 rs_fec_correction_bypass_admin[0x4]; 8597 u8 reserved_at_a4[0x8]; 8598 u8 fec_override_admin_56g[0x4]; 8599 u8 fec_override_admin_100g[0x4]; 8600 u8 fec_override_admin_50g[0x4]; 8601 u8 fec_override_admin_25g[0x4]; 8602 u8 fec_override_admin_10g_40g[0x4]; 8603 8604 u8 fec_override_cap_400g_8x[0x10]; 8605 u8 fec_override_cap_200g_4x[0x10]; 8606 8607 u8 fec_override_cap_100g_2x[0x10]; 8608 u8 fec_override_cap_50g_1x[0x10]; 8609 8610 u8 fec_override_admin_400g_8x[0x10]; 8611 u8 fec_override_admin_200g_4x[0x10]; 8612 8613 u8 fec_override_admin_100g_2x[0x10]; 8614 u8 fec_override_admin_50g_1x[0x10]; 8615 }; 8616 8617 struct mlx5_ifc_ppcnt_reg_bits { 8618 u8 swid[0x8]; 8619 u8 local_port[0x8]; 8620 u8 pnat[0x2]; 8621 u8 reserved_at_12[0x8]; 8622 u8 grp[0x6]; 8623 8624 u8 clr[0x1]; 8625 u8 reserved_at_21[0x1c]; 8626 u8 prio_tc[0x3]; 8627 8628 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8629 }; 8630 8631 struct mlx5_ifc_mpein_reg_bits { 8632 u8 reserved_at_0[0x2]; 8633 u8 depth[0x6]; 8634 u8 pcie_index[0x8]; 8635 u8 node[0x8]; 8636 u8 reserved_at_18[0x8]; 8637 8638 u8 capability_mask[0x20]; 8639 8640 u8 reserved_at_40[0x8]; 8641 u8 link_width_enabled[0x8]; 8642 u8 link_speed_enabled[0x10]; 8643 8644 u8 lane0_physical_position[0x8]; 8645 u8 link_width_active[0x8]; 8646 u8 link_speed_active[0x10]; 8647 8648 u8 num_of_pfs[0x10]; 8649 u8 num_of_vfs[0x10]; 8650 8651 u8 bdf0[0x10]; 8652 u8 reserved_at_b0[0x10]; 8653 8654 u8 max_read_request_size[0x4]; 8655 u8 max_payload_size[0x4]; 8656 u8 reserved_at_c8[0x5]; 8657 u8 pwr_status[0x3]; 8658 u8 port_type[0x4]; 8659 u8 reserved_at_d4[0xb]; 8660 u8 lane_reversal[0x1]; 8661 8662 u8 reserved_at_e0[0x14]; 8663 u8 pci_power[0xc]; 8664 8665 u8 reserved_at_100[0x20]; 8666 8667 u8 device_status[0x10]; 8668 u8 port_state[0x8]; 8669 u8 reserved_at_138[0x8]; 8670 8671 u8 reserved_at_140[0x10]; 8672 u8 receiver_detect_result[0x10]; 8673 8674 u8 reserved_at_160[0x20]; 8675 }; 8676 8677 struct mlx5_ifc_mpcnt_reg_bits { 8678 u8 reserved_at_0[0x8]; 8679 u8 pcie_index[0x8]; 8680 u8 reserved_at_10[0xa]; 8681 u8 grp[0x6]; 8682 8683 u8 clr[0x1]; 8684 u8 reserved_at_21[0x1f]; 8685 8686 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8687 }; 8688 8689 struct mlx5_ifc_ppad_reg_bits { 8690 u8 reserved_at_0[0x3]; 8691 u8 single_mac[0x1]; 8692 u8 reserved_at_4[0x4]; 8693 u8 local_port[0x8]; 8694 u8 mac_47_32[0x10]; 8695 8696 u8 mac_31_0[0x20]; 8697 8698 u8 reserved_at_40[0x40]; 8699 }; 8700 8701 struct mlx5_ifc_pmtu_reg_bits { 8702 u8 reserved_at_0[0x8]; 8703 u8 local_port[0x8]; 8704 u8 reserved_at_10[0x10]; 8705 8706 u8 max_mtu[0x10]; 8707 u8 reserved_at_30[0x10]; 8708 8709 u8 admin_mtu[0x10]; 8710 u8 reserved_at_50[0x10]; 8711 8712 u8 oper_mtu[0x10]; 8713 u8 reserved_at_70[0x10]; 8714 }; 8715 8716 struct mlx5_ifc_pmpr_reg_bits { 8717 u8 reserved_at_0[0x8]; 8718 u8 module[0x8]; 8719 u8 reserved_at_10[0x10]; 8720 8721 u8 reserved_at_20[0x18]; 8722 u8 attenuation_5g[0x8]; 8723 8724 u8 reserved_at_40[0x18]; 8725 u8 attenuation_7g[0x8]; 8726 8727 u8 reserved_at_60[0x18]; 8728 u8 attenuation_12g[0x8]; 8729 }; 8730 8731 struct mlx5_ifc_pmpe_reg_bits { 8732 u8 reserved_at_0[0x8]; 8733 u8 module[0x8]; 8734 u8 reserved_at_10[0xc]; 8735 u8 module_status[0x4]; 8736 8737 u8 reserved_at_20[0x60]; 8738 }; 8739 8740 struct mlx5_ifc_pmpc_reg_bits { 8741 u8 module_state_updated[32][0x8]; 8742 }; 8743 8744 struct mlx5_ifc_pmlpn_reg_bits { 8745 u8 reserved_at_0[0x4]; 8746 u8 mlpn_status[0x4]; 8747 u8 local_port[0x8]; 8748 u8 reserved_at_10[0x10]; 8749 8750 u8 e[0x1]; 8751 u8 reserved_at_21[0x1f]; 8752 }; 8753 8754 struct mlx5_ifc_pmlp_reg_bits { 8755 u8 rxtx[0x1]; 8756 u8 reserved_at_1[0x7]; 8757 u8 local_port[0x8]; 8758 u8 reserved_at_10[0x8]; 8759 u8 width[0x8]; 8760 8761 u8 lane0_module_mapping[0x20]; 8762 8763 u8 lane1_module_mapping[0x20]; 8764 8765 u8 lane2_module_mapping[0x20]; 8766 8767 u8 lane3_module_mapping[0x20]; 8768 8769 u8 reserved_at_a0[0x160]; 8770 }; 8771 8772 struct mlx5_ifc_pmaos_reg_bits { 8773 u8 reserved_at_0[0x8]; 8774 u8 module[0x8]; 8775 u8 reserved_at_10[0x4]; 8776 u8 admin_status[0x4]; 8777 u8 reserved_at_18[0x4]; 8778 u8 oper_status[0x4]; 8779 8780 u8 ase[0x1]; 8781 u8 ee[0x1]; 8782 u8 reserved_at_22[0x1c]; 8783 u8 e[0x2]; 8784 8785 u8 reserved_at_40[0x40]; 8786 }; 8787 8788 struct mlx5_ifc_plpc_reg_bits { 8789 u8 reserved_at_0[0x4]; 8790 u8 profile_id[0xc]; 8791 u8 reserved_at_10[0x4]; 8792 u8 proto_mask[0x4]; 8793 u8 reserved_at_18[0x8]; 8794 8795 u8 reserved_at_20[0x10]; 8796 u8 lane_speed[0x10]; 8797 8798 u8 reserved_at_40[0x17]; 8799 u8 lpbf[0x1]; 8800 u8 fec_mode_policy[0x8]; 8801 8802 u8 retransmission_capability[0x8]; 8803 u8 fec_mode_capability[0x18]; 8804 8805 u8 retransmission_support_admin[0x8]; 8806 u8 fec_mode_support_admin[0x18]; 8807 8808 u8 retransmission_request_admin[0x8]; 8809 u8 fec_mode_request_admin[0x18]; 8810 8811 u8 reserved_at_c0[0x80]; 8812 }; 8813 8814 struct mlx5_ifc_plib_reg_bits { 8815 u8 reserved_at_0[0x8]; 8816 u8 local_port[0x8]; 8817 u8 reserved_at_10[0x8]; 8818 u8 ib_port[0x8]; 8819 8820 u8 reserved_at_20[0x60]; 8821 }; 8822 8823 struct mlx5_ifc_plbf_reg_bits { 8824 u8 reserved_at_0[0x8]; 8825 u8 local_port[0x8]; 8826 u8 reserved_at_10[0xd]; 8827 u8 lbf_mode[0x3]; 8828 8829 u8 reserved_at_20[0x20]; 8830 }; 8831 8832 struct mlx5_ifc_pipg_reg_bits { 8833 u8 reserved_at_0[0x8]; 8834 u8 local_port[0x8]; 8835 u8 reserved_at_10[0x10]; 8836 8837 u8 dic[0x1]; 8838 u8 reserved_at_21[0x19]; 8839 u8 ipg[0x4]; 8840 u8 reserved_at_3e[0x2]; 8841 }; 8842 8843 struct mlx5_ifc_pifr_reg_bits { 8844 u8 reserved_at_0[0x8]; 8845 u8 local_port[0x8]; 8846 u8 reserved_at_10[0x10]; 8847 8848 u8 reserved_at_20[0xe0]; 8849 8850 u8 port_filter[8][0x20]; 8851 8852 u8 port_filter_update_en[8][0x20]; 8853 }; 8854 8855 struct mlx5_ifc_pfcc_reg_bits { 8856 u8 reserved_at_0[0x8]; 8857 u8 local_port[0x8]; 8858 u8 reserved_at_10[0xb]; 8859 u8 ppan_mask_n[0x1]; 8860 u8 minor_stall_mask[0x1]; 8861 u8 critical_stall_mask[0x1]; 8862 u8 reserved_at_1e[0x2]; 8863 8864 u8 ppan[0x4]; 8865 u8 reserved_at_24[0x4]; 8866 u8 prio_mask_tx[0x8]; 8867 u8 reserved_at_30[0x8]; 8868 u8 prio_mask_rx[0x8]; 8869 8870 u8 pptx[0x1]; 8871 u8 aptx[0x1]; 8872 u8 pptx_mask_n[0x1]; 8873 u8 reserved_at_43[0x5]; 8874 u8 pfctx[0x8]; 8875 u8 reserved_at_50[0x10]; 8876 8877 u8 pprx[0x1]; 8878 u8 aprx[0x1]; 8879 u8 pprx_mask_n[0x1]; 8880 u8 reserved_at_63[0x5]; 8881 u8 pfcrx[0x8]; 8882 u8 reserved_at_70[0x10]; 8883 8884 u8 device_stall_minor_watermark[0x10]; 8885 u8 device_stall_critical_watermark[0x10]; 8886 8887 u8 reserved_at_a0[0x60]; 8888 }; 8889 8890 struct mlx5_ifc_pelc_reg_bits { 8891 u8 op[0x4]; 8892 u8 reserved_at_4[0x4]; 8893 u8 local_port[0x8]; 8894 u8 reserved_at_10[0x10]; 8895 8896 u8 op_admin[0x8]; 8897 u8 op_capability[0x8]; 8898 u8 op_request[0x8]; 8899 u8 op_active[0x8]; 8900 8901 u8 admin[0x40]; 8902 8903 u8 capability[0x40]; 8904 8905 u8 request[0x40]; 8906 8907 u8 active[0x40]; 8908 8909 u8 reserved_at_140[0x80]; 8910 }; 8911 8912 struct mlx5_ifc_peir_reg_bits { 8913 u8 reserved_at_0[0x8]; 8914 u8 local_port[0x8]; 8915 u8 reserved_at_10[0x10]; 8916 8917 u8 reserved_at_20[0xc]; 8918 u8 error_count[0x4]; 8919 u8 reserved_at_30[0x10]; 8920 8921 u8 reserved_at_40[0xc]; 8922 u8 lane[0x4]; 8923 u8 reserved_at_50[0x8]; 8924 u8 error_type[0x8]; 8925 }; 8926 8927 struct mlx5_ifc_mpegc_reg_bits { 8928 u8 reserved_at_0[0x30]; 8929 u8 field_select[0x10]; 8930 8931 u8 tx_overflow_sense[0x1]; 8932 u8 mark_cqe[0x1]; 8933 u8 mark_cnp[0x1]; 8934 u8 reserved_at_43[0x1b]; 8935 u8 tx_lossy_overflow_oper[0x2]; 8936 8937 u8 reserved_at_60[0x100]; 8938 }; 8939 8940 struct mlx5_ifc_pcam_enhanced_features_bits { 8941 u8 reserved_at_0[0x68]; 8942 u8 fec_50G_per_lane_in_pplm[0x1]; 8943 u8 reserved_at_69[0x4]; 8944 u8 rx_icrc_encapsulated_counter[0x1]; 8945 u8 reserved_at_6e[0x4]; 8946 u8 ptys_extended_ethernet[0x1]; 8947 u8 reserved_at_73[0x3]; 8948 u8 pfcc_mask[0x1]; 8949 u8 reserved_at_77[0x3]; 8950 u8 per_lane_error_counters[0x1]; 8951 u8 rx_buffer_fullness_counters[0x1]; 8952 u8 ptys_connector_type[0x1]; 8953 u8 reserved_at_7d[0x1]; 8954 u8 ppcnt_discard_group[0x1]; 8955 u8 ppcnt_statistical_group[0x1]; 8956 }; 8957 8958 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8959 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8960 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8961 8962 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8963 u8 pplm[0x1]; 8964 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8965 8966 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8967 u8 pbmc[0x1]; 8968 u8 pptb[0x1]; 8969 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8970 u8 ppcnt[0x1]; 8971 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8972 }; 8973 8974 struct mlx5_ifc_pcam_reg_bits { 8975 u8 reserved_at_0[0x8]; 8976 u8 feature_group[0x8]; 8977 u8 reserved_at_10[0x8]; 8978 u8 access_reg_group[0x8]; 8979 8980 u8 reserved_at_20[0x20]; 8981 8982 union { 8983 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8984 u8 reserved_at_0[0x80]; 8985 } port_access_reg_cap_mask; 8986 8987 u8 reserved_at_c0[0x80]; 8988 8989 union { 8990 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8991 u8 reserved_at_0[0x80]; 8992 } feature_cap_mask; 8993 8994 u8 reserved_at_1c0[0xc0]; 8995 }; 8996 8997 struct mlx5_ifc_mcam_enhanced_features_bits { 8998 u8 reserved_at_0[0x6e]; 8999 u8 pci_status_and_power[0x1]; 9000 u8 reserved_at_6f[0x5]; 9001 u8 mark_tx_action_cnp[0x1]; 9002 u8 mark_tx_action_cqe[0x1]; 9003 u8 dynamic_tx_overflow[0x1]; 9004 u8 reserved_at_77[0x4]; 9005 u8 pcie_outbound_stalled[0x1]; 9006 u8 tx_overflow_buffer_pkt[0x1]; 9007 u8 mtpps_enh_out_per_adj[0x1]; 9008 u8 mtpps_fs[0x1]; 9009 u8 pcie_performance_group[0x1]; 9010 }; 9011 9012 struct mlx5_ifc_mcam_access_reg_bits { 9013 u8 reserved_at_0[0x1c]; 9014 u8 mcda[0x1]; 9015 u8 mcc[0x1]; 9016 u8 mcqi[0x1]; 9017 u8 mcqs[0x1]; 9018 9019 u8 regs_95_to_87[0x9]; 9020 u8 mpegc[0x1]; 9021 u8 regs_85_to_68[0x12]; 9022 u8 tracer_registers[0x4]; 9023 9024 u8 regs_63_to_32[0x20]; 9025 u8 regs_31_to_0[0x20]; 9026 }; 9027 9028 struct mlx5_ifc_mcam_access_reg_bits1 { 9029 u8 regs_127_to_96[0x20]; 9030 9031 u8 regs_95_to_64[0x20]; 9032 9033 u8 regs_63_to_32[0x20]; 9034 9035 u8 regs_31_to_0[0x20]; 9036 }; 9037 9038 struct mlx5_ifc_mcam_access_reg_bits2 { 9039 u8 regs_127_to_99[0x1d]; 9040 u8 mirc[0x1]; 9041 u8 regs_97_to_96[0x2]; 9042 9043 u8 regs_95_to_64[0x20]; 9044 9045 u8 regs_63_to_32[0x20]; 9046 9047 u8 regs_31_to_0[0x20]; 9048 }; 9049 9050 struct mlx5_ifc_mcam_reg_bits { 9051 u8 reserved_at_0[0x8]; 9052 u8 feature_group[0x8]; 9053 u8 reserved_at_10[0x8]; 9054 u8 access_reg_group[0x8]; 9055 9056 u8 reserved_at_20[0x20]; 9057 9058 union { 9059 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9060 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9061 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9062 u8 reserved_at_0[0x80]; 9063 } mng_access_reg_cap_mask; 9064 9065 u8 reserved_at_c0[0x80]; 9066 9067 union { 9068 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9069 u8 reserved_at_0[0x80]; 9070 } mng_feature_cap_mask; 9071 9072 u8 reserved_at_1c0[0x80]; 9073 }; 9074 9075 struct mlx5_ifc_qcam_access_reg_cap_mask { 9076 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9077 u8 qpdpm[0x1]; 9078 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9079 u8 qdpm[0x1]; 9080 u8 qpts[0x1]; 9081 u8 qcap[0x1]; 9082 u8 qcam_access_reg_cap_mask_0[0x1]; 9083 }; 9084 9085 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9086 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9087 u8 qpts_trust_both[0x1]; 9088 }; 9089 9090 struct mlx5_ifc_qcam_reg_bits { 9091 u8 reserved_at_0[0x8]; 9092 u8 feature_group[0x8]; 9093 u8 reserved_at_10[0x8]; 9094 u8 access_reg_group[0x8]; 9095 u8 reserved_at_20[0x20]; 9096 9097 union { 9098 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9099 u8 reserved_at_0[0x80]; 9100 } qos_access_reg_cap_mask; 9101 9102 u8 reserved_at_c0[0x80]; 9103 9104 union { 9105 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9106 u8 reserved_at_0[0x80]; 9107 } qos_feature_cap_mask; 9108 9109 u8 reserved_at_1c0[0x80]; 9110 }; 9111 9112 struct mlx5_ifc_core_dump_reg_bits { 9113 u8 reserved_at_0[0x18]; 9114 u8 core_dump_type[0x8]; 9115 9116 u8 reserved_at_20[0x30]; 9117 u8 vhca_id[0x10]; 9118 9119 u8 reserved_at_60[0x8]; 9120 u8 qpn[0x18]; 9121 u8 reserved_at_80[0x180]; 9122 }; 9123 9124 struct mlx5_ifc_pcap_reg_bits { 9125 u8 reserved_at_0[0x8]; 9126 u8 local_port[0x8]; 9127 u8 reserved_at_10[0x10]; 9128 9129 u8 port_capability_mask[4][0x20]; 9130 }; 9131 9132 struct mlx5_ifc_paos_reg_bits { 9133 u8 swid[0x8]; 9134 u8 local_port[0x8]; 9135 u8 reserved_at_10[0x4]; 9136 u8 admin_status[0x4]; 9137 u8 reserved_at_18[0x4]; 9138 u8 oper_status[0x4]; 9139 9140 u8 ase[0x1]; 9141 u8 ee[0x1]; 9142 u8 reserved_at_22[0x1c]; 9143 u8 e[0x2]; 9144 9145 u8 reserved_at_40[0x40]; 9146 }; 9147 9148 struct mlx5_ifc_pamp_reg_bits { 9149 u8 reserved_at_0[0x8]; 9150 u8 opamp_group[0x8]; 9151 u8 reserved_at_10[0xc]; 9152 u8 opamp_group_type[0x4]; 9153 9154 u8 start_index[0x10]; 9155 u8 reserved_at_30[0x4]; 9156 u8 num_of_indices[0xc]; 9157 9158 u8 index_data[18][0x10]; 9159 }; 9160 9161 struct mlx5_ifc_pcmr_reg_bits { 9162 u8 reserved_at_0[0x8]; 9163 u8 local_port[0x8]; 9164 u8 reserved_at_10[0x10]; 9165 u8 entropy_force_cap[0x1]; 9166 u8 entropy_calc_cap[0x1]; 9167 u8 entropy_gre_calc_cap[0x1]; 9168 u8 reserved_at_23[0x1b]; 9169 u8 fcs_cap[0x1]; 9170 u8 reserved_at_3f[0x1]; 9171 u8 entropy_force[0x1]; 9172 u8 entropy_calc[0x1]; 9173 u8 entropy_gre_calc[0x1]; 9174 u8 reserved_at_43[0x1b]; 9175 u8 fcs_chk[0x1]; 9176 u8 reserved_at_5f[0x1]; 9177 }; 9178 9179 struct mlx5_ifc_lane_2_module_mapping_bits { 9180 u8 reserved_at_0[0x6]; 9181 u8 rx_lane[0x2]; 9182 u8 reserved_at_8[0x6]; 9183 u8 tx_lane[0x2]; 9184 u8 reserved_at_10[0x8]; 9185 u8 module[0x8]; 9186 }; 9187 9188 struct mlx5_ifc_bufferx_reg_bits { 9189 u8 reserved_at_0[0x6]; 9190 u8 lossy[0x1]; 9191 u8 epsb[0x1]; 9192 u8 reserved_at_8[0xc]; 9193 u8 size[0xc]; 9194 9195 u8 xoff_threshold[0x10]; 9196 u8 xon_threshold[0x10]; 9197 }; 9198 9199 struct mlx5_ifc_set_node_in_bits { 9200 u8 node_description[64][0x8]; 9201 }; 9202 9203 struct mlx5_ifc_register_power_settings_bits { 9204 u8 reserved_at_0[0x18]; 9205 u8 power_settings_level[0x8]; 9206 9207 u8 reserved_at_20[0x60]; 9208 }; 9209 9210 struct mlx5_ifc_register_host_endianness_bits { 9211 u8 he[0x1]; 9212 u8 reserved_at_1[0x1f]; 9213 9214 u8 reserved_at_20[0x60]; 9215 }; 9216 9217 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9218 u8 reserved_at_0[0x20]; 9219 9220 u8 mkey[0x20]; 9221 9222 u8 addressh_63_32[0x20]; 9223 9224 u8 addressl_31_0[0x20]; 9225 }; 9226 9227 struct mlx5_ifc_ud_adrs_vector_bits { 9228 u8 dc_key[0x40]; 9229 9230 u8 ext[0x1]; 9231 u8 reserved_at_41[0x7]; 9232 u8 destination_qp_dct[0x18]; 9233 9234 u8 static_rate[0x4]; 9235 u8 sl_eth_prio[0x4]; 9236 u8 fl[0x1]; 9237 u8 mlid[0x7]; 9238 u8 rlid_udp_sport[0x10]; 9239 9240 u8 reserved_at_80[0x20]; 9241 9242 u8 rmac_47_16[0x20]; 9243 9244 u8 rmac_15_0[0x10]; 9245 u8 tclass[0x8]; 9246 u8 hop_limit[0x8]; 9247 9248 u8 reserved_at_e0[0x1]; 9249 u8 grh[0x1]; 9250 u8 reserved_at_e2[0x2]; 9251 u8 src_addr_index[0x8]; 9252 u8 flow_label[0x14]; 9253 9254 u8 rgid_rip[16][0x8]; 9255 }; 9256 9257 struct mlx5_ifc_pages_req_event_bits { 9258 u8 reserved_at_0[0x10]; 9259 u8 function_id[0x10]; 9260 9261 u8 num_pages[0x20]; 9262 9263 u8 reserved_at_40[0xa0]; 9264 }; 9265 9266 struct mlx5_ifc_eqe_bits { 9267 u8 reserved_at_0[0x8]; 9268 u8 event_type[0x8]; 9269 u8 reserved_at_10[0x8]; 9270 u8 event_sub_type[0x8]; 9271 9272 u8 reserved_at_20[0xe0]; 9273 9274 union mlx5_ifc_event_auto_bits event_data; 9275 9276 u8 reserved_at_1e0[0x10]; 9277 u8 signature[0x8]; 9278 u8 reserved_at_1f8[0x7]; 9279 u8 owner[0x1]; 9280 }; 9281 9282 enum { 9283 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9284 }; 9285 9286 struct mlx5_ifc_cmd_queue_entry_bits { 9287 u8 type[0x8]; 9288 u8 reserved_at_8[0x18]; 9289 9290 u8 input_length[0x20]; 9291 9292 u8 input_mailbox_pointer_63_32[0x20]; 9293 9294 u8 input_mailbox_pointer_31_9[0x17]; 9295 u8 reserved_at_77[0x9]; 9296 9297 u8 command_input_inline_data[16][0x8]; 9298 9299 u8 command_output_inline_data[16][0x8]; 9300 9301 u8 output_mailbox_pointer_63_32[0x20]; 9302 9303 u8 output_mailbox_pointer_31_9[0x17]; 9304 u8 reserved_at_1b7[0x9]; 9305 9306 u8 output_length[0x20]; 9307 9308 u8 token[0x8]; 9309 u8 signature[0x8]; 9310 u8 reserved_at_1f0[0x8]; 9311 u8 status[0x7]; 9312 u8 ownership[0x1]; 9313 }; 9314 9315 struct mlx5_ifc_cmd_out_bits { 9316 u8 status[0x8]; 9317 u8 reserved_at_8[0x18]; 9318 9319 u8 syndrome[0x20]; 9320 9321 u8 command_output[0x20]; 9322 }; 9323 9324 struct mlx5_ifc_cmd_in_bits { 9325 u8 opcode[0x10]; 9326 u8 reserved_at_10[0x10]; 9327 9328 u8 reserved_at_20[0x10]; 9329 u8 op_mod[0x10]; 9330 9331 u8 command[0][0x20]; 9332 }; 9333 9334 struct mlx5_ifc_cmd_if_box_bits { 9335 u8 mailbox_data[512][0x8]; 9336 9337 u8 reserved_at_1000[0x180]; 9338 9339 u8 next_pointer_63_32[0x20]; 9340 9341 u8 next_pointer_31_10[0x16]; 9342 u8 reserved_at_11b6[0xa]; 9343 9344 u8 block_number[0x20]; 9345 9346 u8 reserved_at_11e0[0x8]; 9347 u8 token[0x8]; 9348 u8 ctrl_signature[0x8]; 9349 u8 signature[0x8]; 9350 }; 9351 9352 struct mlx5_ifc_mtt_bits { 9353 u8 ptag_63_32[0x20]; 9354 9355 u8 ptag_31_8[0x18]; 9356 u8 reserved_at_38[0x6]; 9357 u8 wr_en[0x1]; 9358 u8 rd_en[0x1]; 9359 }; 9360 9361 struct mlx5_ifc_query_wol_rol_out_bits { 9362 u8 status[0x8]; 9363 u8 reserved_at_8[0x18]; 9364 9365 u8 syndrome[0x20]; 9366 9367 u8 reserved_at_40[0x10]; 9368 u8 rol_mode[0x8]; 9369 u8 wol_mode[0x8]; 9370 9371 u8 reserved_at_60[0x20]; 9372 }; 9373 9374 struct mlx5_ifc_query_wol_rol_in_bits { 9375 u8 opcode[0x10]; 9376 u8 reserved_at_10[0x10]; 9377 9378 u8 reserved_at_20[0x10]; 9379 u8 op_mod[0x10]; 9380 9381 u8 reserved_at_40[0x40]; 9382 }; 9383 9384 struct mlx5_ifc_set_wol_rol_out_bits { 9385 u8 status[0x8]; 9386 u8 reserved_at_8[0x18]; 9387 9388 u8 syndrome[0x20]; 9389 9390 u8 reserved_at_40[0x40]; 9391 }; 9392 9393 struct mlx5_ifc_set_wol_rol_in_bits { 9394 u8 opcode[0x10]; 9395 u8 reserved_at_10[0x10]; 9396 9397 u8 reserved_at_20[0x10]; 9398 u8 op_mod[0x10]; 9399 9400 u8 rol_mode_valid[0x1]; 9401 u8 wol_mode_valid[0x1]; 9402 u8 reserved_at_42[0xe]; 9403 u8 rol_mode[0x8]; 9404 u8 wol_mode[0x8]; 9405 9406 u8 reserved_at_60[0x20]; 9407 }; 9408 9409 enum { 9410 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9411 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9412 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9413 }; 9414 9415 enum { 9416 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9417 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9418 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9419 }; 9420 9421 enum { 9422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9426 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9427 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9428 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9429 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9430 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9431 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9432 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9433 }; 9434 9435 struct mlx5_ifc_initial_seg_bits { 9436 u8 fw_rev_minor[0x10]; 9437 u8 fw_rev_major[0x10]; 9438 9439 u8 cmd_interface_rev[0x10]; 9440 u8 fw_rev_subminor[0x10]; 9441 9442 u8 reserved_at_40[0x40]; 9443 9444 u8 cmdq_phy_addr_63_32[0x20]; 9445 9446 u8 cmdq_phy_addr_31_12[0x14]; 9447 u8 reserved_at_b4[0x2]; 9448 u8 nic_interface[0x2]; 9449 u8 log_cmdq_size[0x4]; 9450 u8 log_cmdq_stride[0x4]; 9451 9452 u8 command_doorbell_vector[0x20]; 9453 9454 u8 reserved_at_e0[0xf00]; 9455 9456 u8 initializing[0x1]; 9457 u8 reserved_at_fe1[0x4]; 9458 u8 nic_interface_supported[0x3]; 9459 u8 embedded_cpu[0x1]; 9460 u8 reserved_at_fe9[0x17]; 9461 9462 struct mlx5_ifc_health_buffer_bits health_buffer; 9463 9464 u8 no_dram_nic_offset[0x20]; 9465 9466 u8 reserved_at_1220[0x6e40]; 9467 9468 u8 reserved_at_8060[0x1f]; 9469 u8 clear_int[0x1]; 9470 9471 u8 health_syndrome[0x8]; 9472 u8 health_counter[0x18]; 9473 9474 u8 reserved_at_80a0[0x17fc0]; 9475 }; 9476 9477 struct mlx5_ifc_mtpps_reg_bits { 9478 u8 reserved_at_0[0xc]; 9479 u8 cap_number_of_pps_pins[0x4]; 9480 u8 reserved_at_10[0x4]; 9481 u8 cap_max_num_of_pps_in_pins[0x4]; 9482 u8 reserved_at_18[0x4]; 9483 u8 cap_max_num_of_pps_out_pins[0x4]; 9484 9485 u8 reserved_at_20[0x24]; 9486 u8 cap_pin_3_mode[0x4]; 9487 u8 reserved_at_48[0x4]; 9488 u8 cap_pin_2_mode[0x4]; 9489 u8 reserved_at_50[0x4]; 9490 u8 cap_pin_1_mode[0x4]; 9491 u8 reserved_at_58[0x4]; 9492 u8 cap_pin_0_mode[0x4]; 9493 9494 u8 reserved_at_60[0x4]; 9495 u8 cap_pin_7_mode[0x4]; 9496 u8 reserved_at_68[0x4]; 9497 u8 cap_pin_6_mode[0x4]; 9498 u8 reserved_at_70[0x4]; 9499 u8 cap_pin_5_mode[0x4]; 9500 u8 reserved_at_78[0x4]; 9501 u8 cap_pin_4_mode[0x4]; 9502 9503 u8 field_select[0x20]; 9504 u8 reserved_at_a0[0x60]; 9505 9506 u8 enable[0x1]; 9507 u8 reserved_at_101[0xb]; 9508 u8 pattern[0x4]; 9509 u8 reserved_at_110[0x4]; 9510 u8 pin_mode[0x4]; 9511 u8 pin[0x8]; 9512 9513 u8 reserved_at_120[0x20]; 9514 9515 u8 time_stamp[0x40]; 9516 9517 u8 out_pulse_duration[0x10]; 9518 u8 out_periodic_adjustment[0x10]; 9519 u8 enhanced_out_periodic_adjustment[0x20]; 9520 9521 u8 reserved_at_1c0[0x20]; 9522 }; 9523 9524 struct mlx5_ifc_mtppse_reg_bits { 9525 u8 reserved_at_0[0x18]; 9526 u8 pin[0x8]; 9527 u8 event_arm[0x1]; 9528 u8 reserved_at_21[0x1b]; 9529 u8 event_generation_mode[0x4]; 9530 u8 reserved_at_40[0x40]; 9531 }; 9532 9533 struct mlx5_ifc_mcqs_reg_bits { 9534 u8 last_index_flag[0x1]; 9535 u8 reserved_at_1[0x7]; 9536 u8 fw_device[0x8]; 9537 u8 component_index[0x10]; 9538 9539 u8 reserved_at_20[0x10]; 9540 u8 identifier[0x10]; 9541 9542 u8 reserved_at_40[0x17]; 9543 u8 component_status[0x5]; 9544 u8 component_update_state[0x4]; 9545 9546 u8 last_update_state_changer_type[0x4]; 9547 u8 last_update_state_changer_host_id[0x4]; 9548 u8 reserved_at_68[0x18]; 9549 }; 9550 9551 struct mlx5_ifc_mcqi_cap_bits { 9552 u8 supported_info_bitmask[0x20]; 9553 9554 u8 component_size[0x20]; 9555 9556 u8 max_component_size[0x20]; 9557 9558 u8 log_mcda_word_size[0x4]; 9559 u8 reserved_at_64[0xc]; 9560 u8 mcda_max_write_size[0x10]; 9561 9562 u8 rd_en[0x1]; 9563 u8 reserved_at_81[0x1]; 9564 u8 match_chip_id[0x1]; 9565 u8 match_psid[0x1]; 9566 u8 check_user_timestamp[0x1]; 9567 u8 match_base_guid_mac[0x1]; 9568 u8 reserved_at_86[0x1a]; 9569 }; 9570 9571 struct mlx5_ifc_mcqi_version_bits { 9572 u8 reserved_at_0[0x2]; 9573 u8 build_time_valid[0x1]; 9574 u8 user_defined_time_valid[0x1]; 9575 u8 reserved_at_4[0x14]; 9576 u8 version_string_length[0x8]; 9577 9578 u8 version[0x20]; 9579 9580 u8 build_time[0x40]; 9581 9582 u8 user_defined_time[0x40]; 9583 9584 u8 build_tool_version[0x20]; 9585 9586 u8 reserved_at_e0[0x20]; 9587 9588 u8 version_string[92][0x8]; 9589 }; 9590 9591 struct mlx5_ifc_mcqi_activation_method_bits { 9592 u8 pending_server_ac_power_cycle[0x1]; 9593 u8 pending_server_dc_power_cycle[0x1]; 9594 u8 pending_server_reboot[0x1]; 9595 u8 pending_fw_reset[0x1]; 9596 u8 auto_activate[0x1]; 9597 u8 all_hosts_sync[0x1]; 9598 u8 device_hw_reset[0x1]; 9599 u8 reserved_at_7[0x19]; 9600 }; 9601 9602 union mlx5_ifc_mcqi_reg_data_bits { 9603 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9604 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9605 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9606 }; 9607 9608 struct mlx5_ifc_mcqi_reg_bits { 9609 u8 read_pending_component[0x1]; 9610 u8 reserved_at_1[0xf]; 9611 u8 component_index[0x10]; 9612 9613 u8 reserved_at_20[0x20]; 9614 9615 u8 reserved_at_40[0x1b]; 9616 u8 info_type[0x5]; 9617 9618 u8 info_size[0x20]; 9619 9620 u8 offset[0x20]; 9621 9622 u8 reserved_at_a0[0x10]; 9623 u8 data_size[0x10]; 9624 9625 union mlx5_ifc_mcqi_reg_data_bits data[0]; 9626 }; 9627 9628 struct mlx5_ifc_mcc_reg_bits { 9629 u8 reserved_at_0[0x4]; 9630 u8 time_elapsed_since_last_cmd[0xc]; 9631 u8 reserved_at_10[0x8]; 9632 u8 instruction[0x8]; 9633 9634 u8 reserved_at_20[0x10]; 9635 u8 component_index[0x10]; 9636 9637 u8 reserved_at_40[0x8]; 9638 u8 update_handle[0x18]; 9639 9640 u8 handle_owner_type[0x4]; 9641 u8 handle_owner_host_id[0x4]; 9642 u8 reserved_at_68[0x1]; 9643 u8 control_progress[0x7]; 9644 u8 error_code[0x8]; 9645 u8 reserved_at_78[0x4]; 9646 u8 control_state[0x4]; 9647 9648 u8 component_size[0x20]; 9649 9650 u8 reserved_at_a0[0x60]; 9651 }; 9652 9653 struct mlx5_ifc_mcda_reg_bits { 9654 u8 reserved_at_0[0x8]; 9655 u8 update_handle[0x18]; 9656 9657 u8 offset[0x20]; 9658 9659 u8 reserved_at_40[0x10]; 9660 u8 size[0x10]; 9661 9662 u8 reserved_at_60[0x20]; 9663 9664 u8 data[0][0x20]; 9665 }; 9666 9667 struct mlx5_ifc_mirc_reg_bits { 9668 u8 reserved_at_0[0x18]; 9669 u8 status_code[0x8]; 9670 9671 u8 reserved_at_20[0x20]; 9672 }; 9673 9674 union mlx5_ifc_ports_control_registers_document_bits { 9675 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9676 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9677 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9678 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9679 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9680 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9681 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9682 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9683 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9684 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9685 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9686 struct mlx5_ifc_paos_reg_bits paos_reg; 9687 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9688 struct mlx5_ifc_peir_reg_bits peir_reg; 9689 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9690 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9691 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9692 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9693 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9694 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9695 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9696 struct mlx5_ifc_plib_reg_bits plib_reg; 9697 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9698 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9699 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9700 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9701 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9702 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9703 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9704 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9705 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9706 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9707 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9708 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9709 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9710 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9711 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9712 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9713 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9714 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9715 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9716 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9717 struct mlx5_ifc_pude_reg_bits pude_reg; 9718 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9719 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9720 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9721 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9722 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9723 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9724 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9725 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9726 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9727 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9728 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9729 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9730 u8 reserved_at_0[0x60e0]; 9731 }; 9732 9733 union mlx5_ifc_debug_enhancements_document_bits { 9734 struct mlx5_ifc_health_buffer_bits health_buffer; 9735 u8 reserved_at_0[0x200]; 9736 }; 9737 9738 union mlx5_ifc_uplink_pci_interface_document_bits { 9739 struct mlx5_ifc_initial_seg_bits initial_seg; 9740 u8 reserved_at_0[0x20060]; 9741 }; 9742 9743 struct mlx5_ifc_set_flow_table_root_out_bits { 9744 u8 status[0x8]; 9745 u8 reserved_at_8[0x18]; 9746 9747 u8 syndrome[0x20]; 9748 9749 u8 reserved_at_40[0x40]; 9750 }; 9751 9752 struct mlx5_ifc_set_flow_table_root_in_bits { 9753 u8 opcode[0x10]; 9754 u8 reserved_at_10[0x10]; 9755 9756 u8 reserved_at_20[0x10]; 9757 u8 op_mod[0x10]; 9758 9759 u8 other_vport[0x1]; 9760 u8 reserved_at_41[0xf]; 9761 u8 vport_number[0x10]; 9762 9763 u8 reserved_at_60[0x20]; 9764 9765 u8 table_type[0x8]; 9766 u8 reserved_at_88[0x18]; 9767 9768 u8 reserved_at_a0[0x8]; 9769 u8 table_id[0x18]; 9770 9771 u8 reserved_at_c0[0x8]; 9772 u8 underlay_qpn[0x18]; 9773 u8 reserved_at_e0[0x120]; 9774 }; 9775 9776 enum { 9777 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9778 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9779 }; 9780 9781 struct mlx5_ifc_modify_flow_table_out_bits { 9782 u8 status[0x8]; 9783 u8 reserved_at_8[0x18]; 9784 9785 u8 syndrome[0x20]; 9786 9787 u8 reserved_at_40[0x40]; 9788 }; 9789 9790 struct mlx5_ifc_modify_flow_table_in_bits { 9791 u8 opcode[0x10]; 9792 u8 reserved_at_10[0x10]; 9793 9794 u8 reserved_at_20[0x10]; 9795 u8 op_mod[0x10]; 9796 9797 u8 other_vport[0x1]; 9798 u8 reserved_at_41[0xf]; 9799 u8 vport_number[0x10]; 9800 9801 u8 reserved_at_60[0x10]; 9802 u8 modify_field_select[0x10]; 9803 9804 u8 table_type[0x8]; 9805 u8 reserved_at_88[0x18]; 9806 9807 u8 reserved_at_a0[0x8]; 9808 u8 table_id[0x18]; 9809 9810 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9811 }; 9812 9813 struct mlx5_ifc_ets_tcn_config_reg_bits { 9814 u8 g[0x1]; 9815 u8 b[0x1]; 9816 u8 r[0x1]; 9817 u8 reserved_at_3[0x9]; 9818 u8 group[0x4]; 9819 u8 reserved_at_10[0x9]; 9820 u8 bw_allocation[0x7]; 9821 9822 u8 reserved_at_20[0xc]; 9823 u8 max_bw_units[0x4]; 9824 u8 reserved_at_30[0x8]; 9825 u8 max_bw_value[0x8]; 9826 }; 9827 9828 struct mlx5_ifc_ets_global_config_reg_bits { 9829 u8 reserved_at_0[0x2]; 9830 u8 r[0x1]; 9831 u8 reserved_at_3[0x1d]; 9832 9833 u8 reserved_at_20[0xc]; 9834 u8 max_bw_units[0x4]; 9835 u8 reserved_at_30[0x8]; 9836 u8 max_bw_value[0x8]; 9837 }; 9838 9839 struct mlx5_ifc_qetc_reg_bits { 9840 u8 reserved_at_0[0x8]; 9841 u8 port_number[0x8]; 9842 u8 reserved_at_10[0x30]; 9843 9844 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9845 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9846 }; 9847 9848 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9849 u8 e[0x1]; 9850 u8 reserved_at_01[0x0b]; 9851 u8 prio[0x04]; 9852 }; 9853 9854 struct mlx5_ifc_qpdpm_reg_bits { 9855 u8 reserved_at_0[0x8]; 9856 u8 local_port[0x8]; 9857 u8 reserved_at_10[0x10]; 9858 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9859 }; 9860 9861 struct mlx5_ifc_qpts_reg_bits { 9862 u8 reserved_at_0[0x8]; 9863 u8 local_port[0x8]; 9864 u8 reserved_at_10[0x2d]; 9865 u8 trust_state[0x3]; 9866 }; 9867 9868 struct mlx5_ifc_pptb_reg_bits { 9869 u8 reserved_at_0[0x2]; 9870 u8 mm[0x2]; 9871 u8 reserved_at_4[0x4]; 9872 u8 local_port[0x8]; 9873 u8 reserved_at_10[0x6]; 9874 u8 cm[0x1]; 9875 u8 um[0x1]; 9876 u8 pm[0x8]; 9877 9878 u8 prio_x_buff[0x20]; 9879 9880 u8 pm_msb[0x8]; 9881 u8 reserved_at_48[0x10]; 9882 u8 ctrl_buff[0x4]; 9883 u8 untagged_buff[0x4]; 9884 }; 9885 9886 struct mlx5_ifc_pbmc_reg_bits { 9887 u8 reserved_at_0[0x8]; 9888 u8 local_port[0x8]; 9889 u8 reserved_at_10[0x10]; 9890 9891 u8 xoff_timer_value[0x10]; 9892 u8 xoff_refresh[0x10]; 9893 9894 u8 reserved_at_40[0x9]; 9895 u8 fullness_threshold[0x7]; 9896 u8 port_buffer_size[0x10]; 9897 9898 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9899 9900 u8 reserved_at_2e0[0x40]; 9901 }; 9902 9903 struct mlx5_ifc_qtct_reg_bits { 9904 u8 reserved_at_0[0x8]; 9905 u8 port_number[0x8]; 9906 u8 reserved_at_10[0xd]; 9907 u8 prio[0x3]; 9908 9909 u8 reserved_at_20[0x1d]; 9910 u8 tclass[0x3]; 9911 }; 9912 9913 struct mlx5_ifc_mcia_reg_bits { 9914 u8 l[0x1]; 9915 u8 reserved_at_1[0x7]; 9916 u8 module[0x8]; 9917 u8 reserved_at_10[0x8]; 9918 u8 status[0x8]; 9919 9920 u8 i2c_device_address[0x8]; 9921 u8 page_number[0x8]; 9922 u8 device_address[0x10]; 9923 9924 u8 reserved_at_40[0x10]; 9925 u8 size[0x10]; 9926 9927 u8 reserved_at_60[0x20]; 9928 9929 u8 dword_0[0x20]; 9930 u8 dword_1[0x20]; 9931 u8 dword_2[0x20]; 9932 u8 dword_3[0x20]; 9933 u8 dword_4[0x20]; 9934 u8 dword_5[0x20]; 9935 u8 dword_6[0x20]; 9936 u8 dword_7[0x20]; 9937 u8 dword_8[0x20]; 9938 u8 dword_9[0x20]; 9939 u8 dword_10[0x20]; 9940 u8 dword_11[0x20]; 9941 }; 9942 9943 struct mlx5_ifc_dcbx_param_bits { 9944 u8 dcbx_cee_cap[0x1]; 9945 u8 dcbx_ieee_cap[0x1]; 9946 u8 dcbx_standby_cap[0x1]; 9947 u8 reserved_at_3[0x5]; 9948 u8 port_number[0x8]; 9949 u8 reserved_at_10[0xa]; 9950 u8 max_application_table_size[6]; 9951 u8 reserved_at_20[0x15]; 9952 u8 version_oper[0x3]; 9953 u8 reserved_at_38[5]; 9954 u8 version_admin[0x3]; 9955 u8 willing_admin[0x1]; 9956 u8 reserved_at_41[0x3]; 9957 u8 pfc_cap_oper[0x4]; 9958 u8 reserved_at_48[0x4]; 9959 u8 pfc_cap_admin[0x4]; 9960 u8 reserved_at_50[0x4]; 9961 u8 num_of_tc_oper[0x4]; 9962 u8 reserved_at_58[0x4]; 9963 u8 num_of_tc_admin[0x4]; 9964 u8 remote_willing[0x1]; 9965 u8 reserved_at_61[3]; 9966 u8 remote_pfc_cap[4]; 9967 u8 reserved_at_68[0x14]; 9968 u8 remote_num_of_tc[0x4]; 9969 u8 reserved_at_80[0x18]; 9970 u8 error[0x8]; 9971 u8 reserved_at_a0[0x160]; 9972 }; 9973 9974 struct mlx5_ifc_lagc_bits { 9975 u8 reserved_at_0[0x1d]; 9976 u8 lag_state[0x3]; 9977 9978 u8 reserved_at_20[0x14]; 9979 u8 tx_remap_affinity_2[0x4]; 9980 u8 reserved_at_38[0x4]; 9981 u8 tx_remap_affinity_1[0x4]; 9982 }; 9983 9984 struct mlx5_ifc_create_lag_out_bits { 9985 u8 status[0x8]; 9986 u8 reserved_at_8[0x18]; 9987 9988 u8 syndrome[0x20]; 9989 9990 u8 reserved_at_40[0x40]; 9991 }; 9992 9993 struct mlx5_ifc_create_lag_in_bits { 9994 u8 opcode[0x10]; 9995 u8 reserved_at_10[0x10]; 9996 9997 u8 reserved_at_20[0x10]; 9998 u8 op_mod[0x10]; 9999 10000 struct mlx5_ifc_lagc_bits ctx; 10001 }; 10002 10003 struct mlx5_ifc_modify_lag_out_bits { 10004 u8 status[0x8]; 10005 u8 reserved_at_8[0x18]; 10006 10007 u8 syndrome[0x20]; 10008 10009 u8 reserved_at_40[0x40]; 10010 }; 10011 10012 struct mlx5_ifc_modify_lag_in_bits { 10013 u8 opcode[0x10]; 10014 u8 reserved_at_10[0x10]; 10015 10016 u8 reserved_at_20[0x10]; 10017 u8 op_mod[0x10]; 10018 10019 u8 reserved_at_40[0x20]; 10020 u8 field_select[0x20]; 10021 10022 struct mlx5_ifc_lagc_bits ctx; 10023 }; 10024 10025 struct mlx5_ifc_query_lag_out_bits { 10026 u8 status[0x8]; 10027 u8 reserved_at_8[0x18]; 10028 10029 u8 syndrome[0x20]; 10030 10031 struct mlx5_ifc_lagc_bits ctx; 10032 }; 10033 10034 struct mlx5_ifc_query_lag_in_bits { 10035 u8 opcode[0x10]; 10036 u8 reserved_at_10[0x10]; 10037 10038 u8 reserved_at_20[0x10]; 10039 u8 op_mod[0x10]; 10040 10041 u8 reserved_at_40[0x40]; 10042 }; 10043 10044 struct mlx5_ifc_destroy_lag_out_bits { 10045 u8 status[0x8]; 10046 u8 reserved_at_8[0x18]; 10047 10048 u8 syndrome[0x20]; 10049 10050 u8 reserved_at_40[0x40]; 10051 }; 10052 10053 struct mlx5_ifc_destroy_lag_in_bits { 10054 u8 opcode[0x10]; 10055 u8 reserved_at_10[0x10]; 10056 10057 u8 reserved_at_20[0x10]; 10058 u8 op_mod[0x10]; 10059 10060 u8 reserved_at_40[0x40]; 10061 }; 10062 10063 struct mlx5_ifc_create_vport_lag_out_bits { 10064 u8 status[0x8]; 10065 u8 reserved_at_8[0x18]; 10066 10067 u8 syndrome[0x20]; 10068 10069 u8 reserved_at_40[0x40]; 10070 }; 10071 10072 struct mlx5_ifc_create_vport_lag_in_bits { 10073 u8 opcode[0x10]; 10074 u8 reserved_at_10[0x10]; 10075 10076 u8 reserved_at_20[0x10]; 10077 u8 op_mod[0x10]; 10078 10079 u8 reserved_at_40[0x40]; 10080 }; 10081 10082 struct mlx5_ifc_destroy_vport_lag_out_bits { 10083 u8 status[0x8]; 10084 u8 reserved_at_8[0x18]; 10085 10086 u8 syndrome[0x20]; 10087 10088 u8 reserved_at_40[0x40]; 10089 }; 10090 10091 struct mlx5_ifc_destroy_vport_lag_in_bits { 10092 u8 opcode[0x10]; 10093 u8 reserved_at_10[0x10]; 10094 10095 u8 reserved_at_20[0x10]; 10096 u8 op_mod[0x10]; 10097 10098 u8 reserved_at_40[0x40]; 10099 }; 10100 10101 struct mlx5_ifc_alloc_memic_in_bits { 10102 u8 opcode[0x10]; 10103 u8 reserved_at_10[0x10]; 10104 10105 u8 reserved_at_20[0x10]; 10106 u8 op_mod[0x10]; 10107 10108 u8 reserved_at_30[0x20]; 10109 10110 u8 reserved_at_40[0x18]; 10111 u8 log_memic_addr_alignment[0x8]; 10112 10113 u8 range_start_addr[0x40]; 10114 10115 u8 range_size[0x20]; 10116 10117 u8 memic_size[0x20]; 10118 }; 10119 10120 struct mlx5_ifc_alloc_memic_out_bits { 10121 u8 status[0x8]; 10122 u8 reserved_at_8[0x18]; 10123 10124 u8 syndrome[0x20]; 10125 10126 u8 memic_start_addr[0x40]; 10127 }; 10128 10129 struct mlx5_ifc_dealloc_memic_in_bits { 10130 u8 opcode[0x10]; 10131 u8 reserved_at_10[0x10]; 10132 10133 u8 reserved_at_20[0x10]; 10134 u8 op_mod[0x10]; 10135 10136 u8 reserved_at_40[0x40]; 10137 10138 u8 memic_start_addr[0x40]; 10139 10140 u8 memic_size[0x20]; 10141 10142 u8 reserved_at_e0[0x20]; 10143 }; 10144 10145 struct mlx5_ifc_dealloc_memic_out_bits { 10146 u8 status[0x8]; 10147 u8 reserved_at_8[0x18]; 10148 10149 u8 syndrome[0x20]; 10150 10151 u8 reserved_at_40[0x40]; 10152 }; 10153 10154 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10155 u8 opcode[0x10]; 10156 u8 uid[0x10]; 10157 10158 u8 vhca_tunnel_id[0x10]; 10159 u8 obj_type[0x10]; 10160 10161 u8 obj_id[0x20]; 10162 10163 u8 reserved_at_60[0x20]; 10164 }; 10165 10166 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10167 u8 status[0x8]; 10168 u8 reserved_at_8[0x18]; 10169 10170 u8 syndrome[0x20]; 10171 10172 u8 obj_id[0x20]; 10173 10174 u8 reserved_at_60[0x20]; 10175 }; 10176 10177 struct mlx5_ifc_umem_bits { 10178 u8 reserved_at_0[0x80]; 10179 10180 u8 reserved_at_80[0x1b]; 10181 u8 log_page_size[0x5]; 10182 10183 u8 page_offset[0x20]; 10184 10185 u8 num_of_mtt[0x40]; 10186 10187 struct mlx5_ifc_mtt_bits mtt[0]; 10188 }; 10189 10190 struct mlx5_ifc_uctx_bits { 10191 u8 cap[0x20]; 10192 10193 u8 reserved_at_20[0x160]; 10194 }; 10195 10196 struct mlx5_ifc_sw_icm_bits { 10197 u8 modify_field_select[0x40]; 10198 10199 u8 reserved_at_40[0x18]; 10200 u8 log_sw_icm_size[0x8]; 10201 10202 u8 reserved_at_60[0x20]; 10203 10204 u8 sw_icm_start_addr[0x40]; 10205 10206 u8 reserved_at_c0[0x140]; 10207 }; 10208 10209 struct mlx5_ifc_geneve_tlv_option_bits { 10210 u8 modify_field_select[0x40]; 10211 10212 u8 reserved_at_40[0x18]; 10213 u8 geneve_option_fte_index[0x8]; 10214 10215 u8 option_class[0x10]; 10216 u8 option_type[0x8]; 10217 u8 reserved_at_78[0x3]; 10218 u8 option_data_length[0x5]; 10219 10220 u8 reserved_at_80[0x180]; 10221 }; 10222 10223 struct mlx5_ifc_create_umem_in_bits { 10224 u8 opcode[0x10]; 10225 u8 uid[0x10]; 10226 10227 u8 reserved_at_20[0x10]; 10228 u8 op_mod[0x10]; 10229 10230 u8 reserved_at_40[0x40]; 10231 10232 struct mlx5_ifc_umem_bits umem; 10233 }; 10234 10235 struct mlx5_ifc_create_uctx_in_bits { 10236 u8 opcode[0x10]; 10237 u8 reserved_at_10[0x10]; 10238 10239 u8 reserved_at_20[0x10]; 10240 u8 op_mod[0x10]; 10241 10242 u8 reserved_at_40[0x40]; 10243 10244 struct mlx5_ifc_uctx_bits uctx; 10245 }; 10246 10247 struct mlx5_ifc_destroy_uctx_in_bits { 10248 u8 opcode[0x10]; 10249 u8 reserved_at_10[0x10]; 10250 10251 u8 reserved_at_20[0x10]; 10252 u8 op_mod[0x10]; 10253 10254 u8 reserved_at_40[0x10]; 10255 u8 uid[0x10]; 10256 10257 u8 reserved_at_60[0x20]; 10258 }; 10259 10260 struct mlx5_ifc_create_sw_icm_in_bits { 10261 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10262 struct mlx5_ifc_sw_icm_bits sw_icm; 10263 }; 10264 10265 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10266 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10267 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10268 }; 10269 10270 struct mlx5_ifc_mtrc_string_db_param_bits { 10271 u8 string_db_base_address[0x20]; 10272 10273 u8 reserved_at_20[0x8]; 10274 u8 string_db_size[0x18]; 10275 }; 10276 10277 struct mlx5_ifc_mtrc_cap_bits { 10278 u8 trace_owner[0x1]; 10279 u8 trace_to_memory[0x1]; 10280 u8 reserved_at_2[0x4]; 10281 u8 trc_ver[0x2]; 10282 u8 reserved_at_8[0x14]; 10283 u8 num_string_db[0x4]; 10284 10285 u8 first_string_trace[0x8]; 10286 u8 num_string_trace[0x8]; 10287 u8 reserved_at_30[0x28]; 10288 10289 u8 log_max_trace_buffer_size[0x8]; 10290 10291 u8 reserved_at_60[0x20]; 10292 10293 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10294 10295 u8 reserved_at_280[0x180]; 10296 }; 10297 10298 struct mlx5_ifc_mtrc_conf_bits { 10299 u8 reserved_at_0[0x1c]; 10300 u8 trace_mode[0x4]; 10301 u8 reserved_at_20[0x18]; 10302 u8 log_trace_buffer_size[0x8]; 10303 u8 trace_mkey[0x20]; 10304 u8 reserved_at_60[0x3a0]; 10305 }; 10306 10307 struct mlx5_ifc_mtrc_stdb_bits { 10308 u8 string_db_index[0x4]; 10309 u8 reserved_at_4[0x4]; 10310 u8 read_size[0x18]; 10311 u8 start_offset[0x20]; 10312 u8 string_db_data[0]; 10313 }; 10314 10315 struct mlx5_ifc_mtrc_ctrl_bits { 10316 u8 trace_status[0x2]; 10317 u8 reserved_at_2[0x2]; 10318 u8 arm_event[0x1]; 10319 u8 reserved_at_5[0xb]; 10320 u8 modify_field_select[0x10]; 10321 u8 reserved_at_20[0x2b]; 10322 u8 current_timestamp52_32[0x15]; 10323 u8 current_timestamp31_0[0x20]; 10324 u8 reserved_at_80[0x180]; 10325 }; 10326 10327 struct mlx5_ifc_host_params_context_bits { 10328 u8 host_number[0x8]; 10329 u8 reserved_at_8[0x7]; 10330 u8 host_pf_disabled[0x1]; 10331 u8 host_num_of_vfs[0x10]; 10332 10333 u8 host_total_vfs[0x10]; 10334 u8 host_pci_bus[0x10]; 10335 10336 u8 reserved_at_40[0x10]; 10337 u8 host_pci_device[0x10]; 10338 10339 u8 reserved_at_60[0x10]; 10340 u8 host_pci_function[0x10]; 10341 10342 u8 reserved_at_80[0x180]; 10343 }; 10344 10345 struct mlx5_ifc_query_esw_functions_in_bits { 10346 u8 opcode[0x10]; 10347 u8 reserved_at_10[0x10]; 10348 10349 u8 reserved_at_20[0x10]; 10350 u8 op_mod[0x10]; 10351 10352 u8 reserved_at_40[0x40]; 10353 }; 10354 10355 struct mlx5_ifc_query_esw_functions_out_bits { 10356 u8 status[0x8]; 10357 u8 reserved_at_8[0x18]; 10358 10359 u8 syndrome[0x20]; 10360 10361 u8 reserved_at_40[0x40]; 10362 10363 struct mlx5_ifc_host_params_context_bits host_params_context; 10364 10365 u8 reserved_at_280[0x180]; 10366 u8 host_sf_enable[0][0x40]; 10367 }; 10368 10369 struct mlx5_ifc_sf_partition_bits { 10370 u8 reserved_at_0[0x10]; 10371 u8 log_num_sf[0x8]; 10372 u8 log_sf_bar_size[0x8]; 10373 }; 10374 10375 struct mlx5_ifc_query_sf_partitions_out_bits { 10376 u8 status[0x8]; 10377 u8 reserved_at_8[0x18]; 10378 10379 u8 syndrome[0x20]; 10380 10381 u8 reserved_at_40[0x18]; 10382 u8 num_sf_partitions[0x8]; 10383 10384 u8 reserved_at_60[0x20]; 10385 10386 struct mlx5_ifc_sf_partition_bits sf_partition[0]; 10387 }; 10388 10389 struct mlx5_ifc_query_sf_partitions_in_bits { 10390 u8 opcode[0x10]; 10391 u8 reserved_at_10[0x10]; 10392 10393 u8 reserved_at_20[0x10]; 10394 u8 op_mod[0x10]; 10395 10396 u8 reserved_at_40[0x40]; 10397 }; 10398 10399 struct mlx5_ifc_dealloc_sf_out_bits { 10400 u8 status[0x8]; 10401 u8 reserved_at_8[0x18]; 10402 10403 u8 syndrome[0x20]; 10404 10405 u8 reserved_at_40[0x40]; 10406 }; 10407 10408 struct mlx5_ifc_dealloc_sf_in_bits { 10409 u8 opcode[0x10]; 10410 u8 reserved_at_10[0x10]; 10411 10412 u8 reserved_at_20[0x10]; 10413 u8 op_mod[0x10]; 10414 10415 u8 reserved_at_40[0x10]; 10416 u8 function_id[0x10]; 10417 10418 u8 reserved_at_60[0x20]; 10419 }; 10420 10421 struct mlx5_ifc_alloc_sf_out_bits { 10422 u8 status[0x8]; 10423 u8 reserved_at_8[0x18]; 10424 10425 u8 syndrome[0x20]; 10426 10427 u8 reserved_at_40[0x40]; 10428 }; 10429 10430 struct mlx5_ifc_alloc_sf_in_bits { 10431 u8 opcode[0x10]; 10432 u8 reserved_at_10[0x10]; 10433 10434 u8 reserved_at_20[0x10]; 10435 u8 op_mod[0x10]; 10436 10437 u8 reserved_at_40[0x10]; 10438 u8 function_id[0x10]; 10439 10440 u8 reserved_at_60[0x20]; 10441 }; 10442 10443 struct mlx5_ifc_affiliated_event_header_bits { 10444 u8 reserved_at_0[0x10]; 10445 u8 obj_type[0x10]; 10446 10447 u8 obj_id[0x20]; 10448 }; 10449 10450 enum { 10451 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10452 }; 10453 10454 enum { 10455 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10456 }; 10457 10458 struct mlx5_ifc_encryption_key_obj_bits { 10459 u8 modify_field_select[0x40]; 10460 10461 u8 reserved_at_40[0x14]; 10462 u8 key_size[0x4]; 10463 u8 reserved_at_58[0x4]; 10464 u8 key_type[0x4]; 10465 10466 u8 reserved_at_60[0x8]; 10467 u8 pd[0x18]; 10468 10469 u8 reserved_at_80[0x180]; 10470 u8 key[8][0x20]; 10471 10472 u8 reserved_at_300[0x500]; 10473 }; 10474 10475 struct mlx5_ifc_create_encryption_key_in_bits { 10476 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10477 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10478 }; 10479 10480 enum { 10481 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10482 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10483 }; 10484 10485 enum { 10486 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 10487 }; 10488 10489 struct mlx5_ifc_tls_static_params_bits { 10490 u8 const_2[0x2]; 10491 u8 tls_version[0x4]; 10492 u8 const_1[0x2]; 10493 u8 reserved_at_8[0x14]; 10494 u8 encryption_standard[0x4]; 10495 10496 u8 reserved_at_20[0x20]; 10497 10498 u8 initial_record_number[0x40]; 10499 10500 u8 resync_tcp_sn[0x20]; 10501 10502 u8 gcm_iv[0x20]; 10503 10504 u8 implicit_iv[0x40]; 10505 10506 u8 reserved_at_100[0x8]; 10507 u8 dek_index[0x18]; 10508 10509 u8 reserved_at_120[0xe0]; 10510 }; 10511 10512 struct mlx5_ifc_tls_progress_params_bits { 10513 u8 reserved_at_0[0x8]; 10514 u8 tisn[0x18]; 10515 10516 u8 next_record_tcp_sn[0x20]; 10517 10518 u8 hw_resync_tcp_sn[0x20]; 10519 10520 u8 record_tracker_state[0x2]; 10521 u8 auth_state[0x2]; 10522 u8 reserved_at_64[0x4]; 10523 u8 hw_offset_record_number[0x18]; 10524 }; 10525 10526 #endif /* MLX5_IFC_H */ 10527