1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 82 }; 83 84 enum { 85 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 86 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 87 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 88 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 89 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 90 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 96 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 99 MLX5_OBJ_TYPE_MKEY = 0xff01, 100 MLX5_OBJ_TYPE_QP = 0xff02, 101 MLX5_OBJ_TYPE_PSV = 0xff03, 102 MLX5_OBJ_TYPE_RMP = 0xff04, 103 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 104 MLX5_OBJ_TYPE_RQ = 0xff06, 105 MLX5_OBJ_TYPE_SQ = 0xff07, 106 MLX5_OBJ_TYPE_TIR = 0xff08, 107 MLX5_OBJ_TYPE_TIS = 0xff09, 108 MLX5_OBJ_TYPE_DCT = 0xff0a, 109 MLX5_OBJ_TYPE_XRQ = 0xff0b, 110 MLX5_OBJ_TYPE_RQT = 0xff0e, 111 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 112 MLX5_OBJ_TYPE_CQ = 0xff10, 113 }; 114 115 enum { 116 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 117 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 118 MLX5_CMD_OP_INIT_HCA = 0x102, 119 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 120 MLX5_CMD_OP_ENABLE_HCA = 0x104, 121 MLX5_CMD_OP_DISABLE_HCA = 0x105, 122 MLX5_CMD_OP_QUERY_PAGES = 0x107, 123 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 124 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 125 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 126 MLX5_CMD_OP_SET_ISSI = 0x10b, 127 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 128 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 129 MLX5_CMD_OP_ALLOC_SF = 0x113, 130 MLX5_CMD_OP_DEALLOC_SF = 0x114, 131 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 132 MLX5_CMD_OP_RESUME_VHCA = 0x116, 133 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 134 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 135 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 136 MLX5_CMD_OP_CREATE_MKEY = 0x200, 137 MLX5_CMD_OP_QUERY_MKEY = 0x201, 138 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 139 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 140 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 141 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 142 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 143 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 144 MLX5_CMD_OP_CREATE_EQ = 0x301, 145 MLX5_CMD_OP_DESTROY_EQ = 0x302, 146 MLX5_CMD_OP_QUERY_EQ = 0x303, 147 MLX5_CMD_OP_GEN_EQE = 0x304, 148 MLX5_CMD_OP_CREATE_CQ = 0x400, 149 MLX5_CMD_OP_DESTROY_CQ = 0x401, 150 MLX5_CMD_OP_QUERY_CQ = 0x402, 151 MLX5_CMD_OP_MODIFY_CQ = 0x403, 152 MLX5_CMD_OP_CREATE_QP = 0x500, 153 MLX5_CMD_OP_DESTROY_QP = 0x501, 154 MLX5_CMD_OP_RST2INIT_QP = 0x502, 155 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 156 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 157 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 158 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 159 MLX5_CMD_OP_2ERR_QP = 0x507, 160 MLX5_CMD_OP_2RST_QP = 0x50a, 161 MLX5_CMD_OP_QUERY_QP = 0x50b, 162 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 163 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 164 MLX5_CMD_OP_CREATE_PSV = 0x600, 165 MLX5_CMD_OP_DESTROY_PSV = 0x601, 166 MLX5_CMD_OP_CREATE_SRQ = 0x700, 167 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 168 MLX5_CMD_OP_QUERY_SRQ = 0x702, 169 MLX5_CMD_OP_ARM_RQ = 0x703, 170 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 171 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 172 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 173 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 174 MLX5_CMD_OP_CREATE_DCT = 0x710, 175 MLX5_CMD_OP_DESTROY_DCT = 0x711, 176 MLX5_CMD_OP_DRAIN_DCT = 0x712, 177 MLX5_CMD_OP_QUERY_DCT = 0x713, 178 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 179 MLX5_CMD_OP_CREATE_XRQ = 0x717, 180 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 181 MLX5_CMD_OP_QUERY_XRQ = 0x719, 182 MLX5_CMD_OP_ARM_XRQ = 0x71a, 183 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 184 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 185 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 186 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 187 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 188 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 189 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 190 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 191 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 192 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 193 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 194 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 195 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 196 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 198 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 200 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 201 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 202 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 203 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 204 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 205 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 206 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 207 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 208 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 209 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 210 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 211 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 212 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 213 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 214 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 215 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 216 MLX5_CMD_OP_ALLOC_PD = 0x800, 217 MLX5_CMD_OP_DEALLOC_PD = 0x801, 218 MLX5_CMD_OP_ALLOC_UAR = 0x802, 219 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 220 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 221 MLX5_CMD_OP_ACCESS_REG = 0x805, 222 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 223 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 224 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 225 MLX5_CMD_OP_MAD_IFC = 0x50d, 226 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 227 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 228 MLX5_CMD_OP_NOP = 0x80d, 229 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 230 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 231 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 232 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 233 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 234 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 235 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 236 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 237 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 238 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 239 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 240 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 241 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 242 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 243 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 244 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 245 MLX5_CMD_OP_CREATE_LAG = 0x840, 246 MLX5_CMD_OP_MODIFY_LAG = 0x841, 247 MLX5_CMD_OP_QUERY_LAG = 0x842, 248 MLX5_CMD_OP_DESTROY_LAG = 0x843, 249 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 250 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 251 MLX5_CMD_OP_CREATE_TIR = 0x900, 252 MLX5_CMD_OP_MODIFY_TIR = 0x901, 253 MLX5_CMD_OP_DESTROY_TIR = 0x902, 254 MLX5_CMD_OP_QUERY_TIR = 0x903, 255 MLX5_CMD_OP_CREATE_SQ = 0x904, 256 MLX5_CMD_OP_MODIFY_SQ = 0x905, 257 MLX5_CMD_OP_DESTROY_SQ = 0x906, 258 MLX5_CMD_OP_QUERY_SQ = 0x907, 259 MLX5_CMD_OP_CREATE_RQ = 0x908, 260 MLX5_CMD_OP_MODIFY_RQ = 0x909, 261 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 262 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 263 MLX5_CMD_OP_QUERY_RQ = 0x90b, 264 MLX5_CMD_OP_CREATE_RMP = 0x90c, 265 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 266 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 267 MLX5_CMD_OP_QUERY_RMP = 0x90f, 268 MLX5_CMD_OP_CREATE_TIS = 0x912, 269 MLX5_CMD_OP_MODIFY_TIS = 0x913, 270 MLX5_CMD_OP_DESTROY_TIS = 0x914, 271 MLX5_CMD_OP_QUERY_TIS = 0x915, 272 MLX5_CMD_OP_CREATE_RQT = 0x916, 273 MLX5_CMD_OP_MODIFY_RQT = 0x917, 274 MLX5_CMD_OP_DESTROY_RQT = 0x918, 275 MLX5_CMD_OP_QUERY_RQT = 0x919, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 277 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 278 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 279 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 280 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 281 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 282 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 284 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 285 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 286 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 287 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 288 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 289 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 290 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 291 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 292 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 293 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 294 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 295 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 296 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 297 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 298 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 299 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 301 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 302 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 303 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 304 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 305 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 306 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 307 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 308 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 309 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 310 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 311 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 312 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 313 MLX5_CMD_OP_MAX 314 }; 315 316 /* Valid range for general commands that don't work over an object */ 317 enum { 318 MLX5_CMD_OP_GENERAL_START = 0xb00, 319 MLX5_CMD_OP_GENERAL_END = 0xd00, 320 }; 321 322 enum { 323 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 324 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 325 }; 326 327 enum { 328 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 329 }; 330 331 struct mlx5_ifc_flow_table_fields_supported_bits { 332 u8 outer_dmac[0x1]; 333 u8 outer_smac[0x1]; 334 u8 outer_ether_type[0x1]; 335 u8 outer_ip_version[0x1]; 336 u8 outer_first_prio[0x1]; 337 u8 outer_first_cfi[0x1]; 338 u8 outer_first_vid[0x1]; 339 u8 outer_ipv4_ttl[0x1]; 340 u8 outer_second_prio[0x1]; 341 u8 outer_second_cfi[0x1]; 342 u8 outer_second_vid[0x1]; 343 u8 reserved_at_b[0x1]; 344 u8 outer_sip[0x1]; 345 u8 outer_dip[0x1]; 346 u8 outer_frag[0x1]; 347 u8 outer_ip_protocol[0x1]; 348 u8 outer_ip_ecn[0x1]; 349 u8 outer_ip_dscp[0x1]; 350 u8 outer_udp_sport[0x1]; 351 u8 outer_udp_dport[0x1]; 352 u8 outer_tcp_sport[0x1]; 353 u8 outer_tcp_dport[0x1]; 354 u8 outer_tcp_flags[0x1]; 355 u8 outer_gre_protocol[0x1]; 356 u8 outer_gre_key[0x1]; 357 u8 outer_vxlan_vni[0x1]; 358 u8 outer_geneve_vni[0x1]; 359 u8 outer_geneve_oam[0x1]; 360 u8 outer_geneve_protocol_type[0x1]; 361 u8 outer_geneve_opt_len[0x1]; 362 u8 source_vhca_port[0x1]; 363 u8 source_eswitch_port[0x1]; 364 365 u8 inner_dmac[0x1]; 366 u8 inner_smac[0x1]; 367 u8 inner_ether_type[0x1]; 368 u8 inner_ip_version[0x1]; 369 u8 inner_first_prio[0x1]; 370 u8 inner_first_cfi[0x1]; 371 u8 inner_first_vid[0x1]; 372 u8 reserved_at_27[0x1]; 373 u8 inner_second_prio[0x1]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0x1]; 376 u8 reserved_at_2b[0x1]; 377 u8 inner_sip[0x1]; 378 u8 inner_dip[0x1]; 379 u8 inner_frag[0x1]; 380 u8 inner_ip_protocol[0x1]; 381 u8 inner_ip_ecn[0x1]; 382 u8 inner_ip_dscp[0x1]; 383 u8 inner_udp_sport[0x1]; 384 u8 inner_udp_dport[0x1]; 385 u8 inner_tcp_sport[0x1]; 386 u8 inner_tcp_dport[0x1]; 387 u8 inner_tcp_flags[0x1]; 388 u8 reserved_at_37[0x9]; 389 390 u8 geneve_tlv_option_0_data[0x1]; 391 u8 geneve_tlv_option_0_exist[0x1]; 392 u8 reserved_at_42[0x3]; 393 u8 outer_first_mpls_over_udp[0x4]; 394 u8 outer_first_mpls_over_gre[0x4]; 395 u8 inner_first_mpls[0x4]; 396 u8 outer_first_mpls[0x4]; 397 u8 reserved_at_55[0x2]; 398 u8 outer_esp_spi[0x1]; 399 u8 reserved_at_58[0x2]; 400 u8 bth_dst_qp[0x1]; 401 u8 reserved_at_5b[0x5]; 402 403 u8 reserved_at_60[0x18]; 404 u8 metadata_reg_c_7[0x1]; 405 u8 metadata_reg_c_6[0x1]; 406 u8 metadata_reg_c_5[0x1]; 407 u8 metadata_reg_c_4[0x1]; 408 u8 metadata_reg_c_3[0x1]; 409 u8 metadata_reg_c_2[0x1]; 410 u8 metadata_reg_c_1[0x1]; 411 u8 metadata_reg_c_0[0x1]; 412 }; 413 414 /* Table 2170 - Flow Table Fields Supported 2 Format */ 415 struct mlx5_ifc_flow_table_fields_supported_2_bits { 416 u8 reserved_at_0[0xe]; 417 u8 bth_opcode[0x1]; 418 u8 reserved_at_f[0x1]; 419 u8 tunnel_header_0_1[0x1]; 420 u8 reserved_at_11[0xf]; 421 422 u8 reserved_at_20[0x60]; 423 }; 424 425 struct mlx5_ifc_flow_table_prop_layout_bits { 426 u8 ft_support[0x1]; 427 u8 reserved_at_1[0x1]; 428 u8 flow_counter[0x1]; 429 u8 flow_modify_en[0x1]; 430 u8 modify_root[0x1]; 431 u8 identified_miss_table_mode[0x1]; 432 u8 flow_table_modify[0x1]; 433 u8 reformat[0x1]; 434 u8 decap[0x1]; 435 u8 reserved_at_9[0x1]; 436 u8 pop_vlan[0x1]; 437 u8 push_vlan[0x1]; 438 u8 reserved_at_c[0x1]; 439 u8 pop_vlan_2[0x1]; 440 u8 push_vlan_2[0x1]; 441 u8 reformat_and_vlan_action[0x1]; 442 u8 reserved_at_10[0x1]; 443 u8 sw_owner[0x1]; 444 u8 reformat_l3_tunnel_to_l2[0x1]; 445 u8 reformat_l2_to_l3_tunnel[0x1]; 446 u8 reformat_and_modify_action[0x1]; 447 u8 ignore_flow_level[0x1]; 448 u8 reserved_at_16[0x1]; 449 u8 table_miss_action_domain[0x1]; 450 u8 termination_table[0x1]; 451 u8 reformat_and_fwd_to_table[0x1]; 452 u8 reserved_at_1a[0x2]; 453 u8 ipsec_encrypt[0x1]; 454 u8 ipsec_decrypt[0x1]; 455 u8 sw_owner_v2[0x1]; 456 u8 reserved_at_1f[0x1]; 457 458 u8 termination_table_raw_traffic[0x1]; 459 u8 reserved_at_21[0x1]; 460 u8 log_max_ft_size[0x6]; 461 u8 log_max_modify_header_context[0x8]; 462 u8 max_modify_header_actions[0x8]; 463 u8 max_ft_level[0x8]; 464 465 u8 reformat_add_esp_trasport[0x1]; 466 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 467 u8 reserved_at_42[0x1]; 468 u8 reformat_del_esp_trasport[0x1]; 469 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 470 u8 reserved_at_45[0x1]; 471 u8 execute_aso[0x1]; 472 u8 reserved_at_47[0x19]; 473 474 u8 reserved_at_60[0x2]; 475 u8 reformat_insert[0x1]; 476 u8 reformat_remove[0x1]; 477 u8 macsec_encrypt[0x1]; 478 u8 macsec_decrypt[0x1]; 479 u8 reserved_at_66[0x2]; 480 u8 reformat_add_macsec[0x1]; 481 u8 reformat_remove_macsec[0x1]; 482 u8 reserved_at_6a[0xe]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_at_6[0x1a]; 507 }; 508 509 struct mlx5_ifc_ipv4_layout_bits { 510 u8 reserved_at_0[0x60]; 511 512 u8 ipv4[0x20]; 513 }; 514 515 struct mlx5_ifc_ipv6_layout_bits { 516 u8 ipv6[16][0x8]; 517 }; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 520 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 521 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 522 u8 reserved_at_0[0x80]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 526 u8 smac_47_16[0x20]; 527 528 u8 smac_15_0[0x10]; 529 u8 ethertype[0x10]; 530 531 u8 dmac_47_16[0x20]; 532 533 u8 dmac_15_0[0x10]; 534 u8 first_prio[0x3]; 535 u8 first_cfi[0x1]; 536 u8 first_vid[0xc]; 537 538 u8 ip_protocol[0x8]; 539 u8 ip_dscp[0x6]; 540 u8 ip_ecn[0x2]; 541 u8 cvlan_tag[0x1]; 542 u8 svlan_tag[0x1]; 543 u8 frag[0x1]; 544 u8 ip_version[0x4]; 545 u8 tcp_flags[0x9]; 546 547 u8 tcp_sport[0x10]; 548 u8 tcp_dport[0x10]; 549 550 u8 reserved_at_c0[0x10]; 551 u8 ipv4_ihl[0x4]; 552 u8 reserved_at_c4[0x4]; 553 554 u8 ttl_hoplimit[0x8]; 555 556 u8 udp_sport[0x10]; 557 u8 udp_dport[0x10]; 558 559 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 560 561 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 562 }; 563 564 struct mlx5_ifc_nvgre_key_bits { 565 u8 hi[0x18]; 566 u8 lo[0x8]; 567 }; 568 569 union mlx5_ifc_gre_key_bits { 570 struct mlx5_ifc_nvgre_key_bits nvgre; 571 u8 key[0x20]; 572 }; 573 574 struct mlx5_ifc_fte_match_set_misc_bits { 575 u8 gre_c_present[0x1]; 576 u8 reserved_at_1[0x1]; 577 u8 gre_k_present[0x1]; 578 u8 gre_s_present[0x1]; 579 u8 source_vhca_port[0x4]; 580 u8 source_sqn[0x18]; 581 582 u8 source_eswitch_owner_vhca_id[0x10]; 583 u8 source_port[0x10]; 584 585 u8 outer_second_prio[0x3]; 586 u8 outer_second_cfi[0x1]; 587 u8 outer_second_vid[0xc]; 588 u8 inner_second_prio[0x3]; 589 u8 inner_second_cfi[0x1]; 590 u8 inner_second_vid[0xc]; 591 592 u8 outer_second_cvlan_tag[0x1]; 593 u8 inner_second_cvlan_tag[0x1]; 594 u8 outer_second_svlan_tag[0x1]; 595 u8 inner_second_svlan_tag[0x1]; 596 u8 reserved_at_64[0xc]; 597 u8 gre_protocol[0x10]; 598 599 union mlx5_ifc_gre_key_bits gre_key; 600 601 u8 vxlan_vni[0x18]; 602 u8 bth_opcode[0x8]; 603 604 u8 geneve_vni[0x18]; 605 u8 reserved_at_d8[0x6]; 606 u8 geneve_tlv_option_0_exist[0x1]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_at_e0[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_at_100[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_120[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_at_140[0x8]; 620 u8 bth_dst_qp[0x18]; 621 u8 reserved_at_160[0x20]; 622 u8 outer_esp_spi[0x20]; 623 u8 reserved_at_1a0[0x60]; 624 }; 625 626 struct mlx5_ifc_fte_match_mpls_bits { 627 u8 mpls_label[0x14]; 628 u8 mpls_exp[0x3]; 629 u8 mpls_s_bos[0x1]; 630 u8 mpls_ttl[0x8]; 631 }; 632 633 struct mlx5_ifc_fte_match_set_misc2_bits { 634 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 635 636 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 637 638 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 639 640 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 641 642 u8 metadata_reg_c_7[0x20]; 643 644 u8 metadata_reg_c_6[0x20]; 645 646 u8 metadata_reg_c_5[0x20]; 647 648 u8 metadata_reg_c_4[0x20]; 649 650 u8 metadata_reg_c_3[0x20]; 651 652 u8 metadata_reg_c_2[0x20]; 653 654 u8 metadata_reg_c_1[0x20]; 655 656 u8 metadata_reg_c_0[0x20]; 657 658 u8 metadata_reg_a[0x20]; 659 660 u8 reserved_at_1a0[0x8]; 661 662 u8 macsec_syndrome[0x8]; 663 u8 ipsec_syndrome[0x8]; 664 u8 reserved_at_1b8[0x8]; 665 666 u8 reserved_at_1c0[0x40]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc3_bits { 670 u8 inner_tcp_seq_num[0x20]; 671 672 u8 outer_tcp_seq_num[0x20]; 673 674 u8 inner_tcp_ack_num[0x20]; 675 676 u8 outer_tcp_ack_num[0x20]; 677 678 u8 reserved_at_80[0x8]; 679 u8 outer_vxlan_gpe_vni[0x18]; 680 681 u8 outer_vxlan_gpe_next_protocol[0x8]; 682 u8 outer_vxlan_gpe_flags[0x8]; 683 u8 reserved_at_b0[0x10]; 684 685 u8 icmp_header_data[0x20]; 686 687 u8 icmpv6_header_data[0x20]; 688 689 u8 icmp_type[0x8]; 690 u8 icmp_code[0x8]; 691 u8 icmpv6_type[0x8]; 692 u8 icmpv6_code[0x8]; 693 694 u8 geneve_tlv_option_0_data[0x20]; 695 696 u8 gtpu_teid[0x20]; 697 698 u8 gtpu_msg_type[0x8]; 699 u8 gtpu_msg_flags[0x8]; 700 u8 reserved_at_170[0x10]; 701 702 u8 gtpu_dw_2[0x20]; 703 704 u8 gtpu_first_ext_dw_0[0x20]; 705 706 u8 gtpu_dw_0[0x20]; 707 708 u8 reserved_at_1e0[0x20]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc4_bits { 712 u8 prog_sample_field_value_0[0x20]; 713 714 u8 prog_sample_field_id_0[0x20]; 715 716 u8 prog_sample_field_value_1[0x20]; 717 718 u8 prog_sample_field_id_1[0x20]; 719 720 u8 prog_sample_field_value_2[0x20]; 721 722 u8 prog_sample_field_id_2[0x20]; 723 724 u8 prog_sample_field_value_3[0x20]; 725 726 u8 prog_sample_field_id_3[0x20]; 727 728 u8 reserved_at_100[0x100]; 729 }; 730 731 struct mlx5_ifc_fte_match_set_misc5_bits { 732 u8 macsec_tag_0[0x20]; 733 734 u8 macsec_tag_1[0x20]; 735 736 u8 macsec_tag_2[0x20]; 737 738 u8 macsec_tag_3[0x20]; 739 740 u8 tunnel_header_0[0x20]; 741 742 u8 tunnel_header_1[0x20]; 743 744 u8 tunnel_header_2[0x20]; 745 746 u8 tunnel_header_3[0x20]; 747 748 u8 reserved_at_100[0x100]; 749 }; 750 751 struct mlx5_ifc_cmd_pas_bits { 752 u8 pa_h[0x20]; 753 754 u8 pa_l[0x14]; 755 u8 reserved_at_34[0xc]; 756 }; 757 758 struct mlx5_ifc_uint64_bits { 759 u8 hi[0x20]; 760 761 u8 lo[0x20]; 762 }; 763 764 enum { 765 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 766 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 767 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 768 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 769 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 770 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 771 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 772 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 773 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 774 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 775 }; 776 777 struct mlx5_ifc_ads_bits { 778 u8 fl[0x1]; 779 u8 free_ar[0x1]; 780 u8 reserved_at_2[0xe]; 781 u8 pkey_index[0x10]; 782 783 u8 reserved_at_20[0x8]; 784 u8 grh[0x1]; 785 u8 mlid[0x7]; 786 u8 rlid[0x10]; 787 788 u8 ack_timeout[0x5]; 789 u8 reserved_at_45[0x3]; 790 u8 src_addr_index[0x8]; 791 u8 reserved_at_50[0x4]; 792 u8 stat_rate[0x4]; 793 u8 hop_limit[0x8]; 794 795 u8 reserved_at_60[0x4]; 796 u8 tclass[0x8]; 797 u8 flow_label[0x14]; 798 799 u8 rgid_rip[16][0x8]; 800 801 u8 reserved_at_100[0x4]; 802 u8 f_dscp[0x1]; 803 u8 f_ecn[0x1]; 804 u8 reserved_at_106[0x1]; 805 u8 f_eth_prio[0x1]; 806 u8 ecn[0x2]; 807 u8 dscp[0x6]; 808 u8 udp_sport[0x10]; 809 810 u8 dei_cfi[0x1]; 811 u8 eth_prio[0x3]; 812 u8 sl[0x4]; 813 u8 vhca_port_num[0x8]; 814 u8 rmac_47_32[0x10]; 815 816 u8 rmac_31_0[0x20]; 817 }; 818 819 struct mlx5_ifc_flow_table_nic_cap_bits { 820 u8 nic_rx_multi_path_tirs[0x1]; 821 u8 nic_rx_multi_path_tirs_fts[0x1]; 822 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 823 u8 reserved_at_3[0x4]; 824 u8 sw_owner_reformat_supported[0x1]; 825 u8 reserved_at_8[0x18]; 826 827 u8 encap_general_header[0x1]; 828 u8 reserved_at_21[0xa]; 829 u8 log_max_packet_reformat_context[0x5]; 830 u8 reserved_at_30[0x6]; 831 u8 max_encap_header_size[0xa]; 832 u8 reserved_at_40[0x1c0]; 833 834 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 835 836 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 837 838 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 839 840 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 841 842 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 843 844 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 845 846 u8 reserved_at_e00[0x700]; 847 848 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 849 850 u8 reserved_at_1580[0x280]; 851 852 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 853 854 u8 reserved_at_1880[0x780]; 855 856 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 857 858 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 859 860 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 861 862 u8 reserved_at_20c0[0x5f40]; 863 }; 864 865 struct mlx5_ifc_port_selection_cap_bits { 866 u8 reserved_at_0[0x10]; 867 u8 port_select_flow_table[0x1]; 868 u8 reserved_at_11[0x1]; 869 u8 port_select_flow_table_bypass[0x1]; 870 u8 reserved_at_13[0xd]; 871 872 u8 reserved_at_20[0x1e0]; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 875 876 u8 reserved_at_400[0x7c00]; 877 }; 878 879 enum { 880 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 881 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 882 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 883 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 884 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 885 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 886 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 887 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 888 }; 889 890 struct mlx5_ifc_flow_table_eswitch_cap_bits { 891 u8 fdb_to_vport_reg_c_id[0x8]; 892 u8 reserved_at_8[0x5]; 893 u8 fdb_uplink_hairpin[0x1]; 894 u8 fdb_multi_path_any_table_limit_regc[0x1]; 895 u8 reserved_at_f[0x3]; 896 u8 fdb_multi_path_any_table[0x1]; 897 u8 reserved_at_13[0x2]; 898 u8 fdb_modify_header_fwd_to_table[0x1]; 899 u8 fdb_ipv4_ttl_modify[0x1]; 900 u8 flow_source[0x1]; 901 u8 reserved_at_18[0x2]; 902 u8 multi_fdb_encap[0x1]; 903 u8 egress_acl_forward_to_vport[0x1]; 904 u8 fdb_multi_path_to_table[0x1]; 905 u8 reserved_at_1d[0x3]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 910 911 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 912 913 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 914 915 u8 reserved_at_800[0xC00]; 916 917 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 918 919 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 920 921 u8 reserved_at_1500[0x300]; 922 923 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 924 925 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 926 927 u8 sw_steering_uplink_icm_address_rx[0x40]; 928 929 u8 sw_steering_uplink_icm_address_tx[0x40]; 930 931 u8 reserved_at_1900[0x6700]; 932 }; 933 934 enum { 935 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 936 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 937 }; 938 939 struct mlx5_ifc_e_switch_cap_bits { 940 u8 vport_svlan_strip[0x1]; 941 u8 vport_cvlan_strip[0x1]; 942 u8 vport_svlan_insert[0x1]; 943 u8 vport_cvlan_insert_if_not_exist[0x1]; 944 u8 vport_cvlan_insert_overwrite[0x1]; 945 u8 reserved_at_5[0x1]; 946 u8 vport_cvlan_insert_always[0x1]; 947 u8 esw_shared_ingress_acl[0x1]; 948 u8 esw_uplink_ingress_acl[0x1]; 949 u8 root_ft_on_other_esw[0x1]; 950 u8 reserved_at_a[0xf]; 951 u8 esw_functions_changed[0x1]; 952 u8 reserved_at_1a[0x1]; 953 u8 ecpf_vport_exists[0x1]; 954 u8 counter_eswitch_affinity[0x1]; 955 u8 merged_eswitch[0x1]; 956 u8 nic_vport_node_guid_modify[0x1]; 957 u8 nic_vport_port_guid_modify[0x1]; 958 959 u8 vxlan_encap_decap[0x1]; 960 u8 nvgre_encap_decap[0x1]; 961 u8 reserved_at_22[0x1]; 962 u8 log_max_fdb_encap_uplink[0x5]; 963 u8 reserved_at_21[0x3]; 964 u8 log_max_packet_reformat_context[0x5]; 965 u8 reserved_2b[0x6]; 966 u8 max_encap_header_size[0xa]; 967 968 u8 reserved_at_40[0xb]; 969 u8 log_max_esw_sf[0x5]; 970 u8 esw_sf_base_id[0x10]; 971 972 u8 reserved_at_60[0x7a0]; 973 974 }; 975 976 struct mlx5_ifc_qos_cap_bits { 977 u8 packet_pacing[0x1]; 978 u8 esw_scheduling[0x1]; 979 u8 esw_bw_share[0x1]; 980 u8 esw_rate_limit[0x1]; 981 u8 reserved_at_4[0x1]; 982 u8 packet_pacing_burst_bound[0x1]; 983 u8 packet_pacing_typical_size[0x1]; 984 u8 reserved_at_7[0x1]; 985 u8 nic_sq_scheduling[0x1]; 986 u8 nic_bw_share[0x1]; 987 u8 nic_rate_limit[0x1]; 988 u8 packet_pacing_uid[0x1]; 989 u8 log_esw_max_sched_depth[0x4]; 990 u8 reserved_at_10[0x10]; 991 992 u8 reserved_at_20[0xb]; 993 u8 log_max_qos_nic_queue_group[0x5]; 994 u8 reserved_at_30[0x10]; 995 996 u8 packet_pacing_max_rate[0x20]; 997 998 u8 packet_pacing_min_rate[0x20]; 999 1000 u8 reserved_at_80[0x10]; 1001 u8 packet_pacing_rate_table_size[0x10]; 1002 1003 u8 esw_element_type[0x10]; 1004 u8 esw_tsar_type[0x10]; 1005 1006 u8 reserved_at_c0[0x10]; 1007 u8 max_qos_para_vport[0x10]; 1008 1009 u8 max_tsar_bw_share[0x20]; 1010 1011 u8 reserved_at_100[0x20]; 1012 1013 u8 reserved_at_120[0x3]; 1014 u8 log_meter_aso_granularity[0x5]; 1015 u8 reserved_at_128[0x3]; 1016 u8 log_meter_aso_max_alloc[0x5]; 1017 u8 reserved_at_130[0x3]; 1018 u8 log_max_num_meter_aso[0x5]; 1019 u8 reserved_at_138[0x8]; 1020 1021 u8 reserved_at_140[0x6c0]; 1022 }; 1023 1024 struct mlx5_ifc_debug_cap_bits { 1025 u8 core_dump_general[0x1]; 1026 u8 core_dump_qp[0x1]; 1027 u8 reserved_at_2[0x7]; 1028 u8 resource_dump[0x1]; 1029 u8 reserved_at_a[0x16]; 1030 1031 u8 reserved_at_20[0x2]; 1032 u8 stall_detect[0x1]; 1033 u8 reserved_at_23[0x1d]; 1034 1035 u8 reserved_at_40[0x7c0]; 1036 }; 1037 1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1039 u8 csum_cap[0x1]; 1040 u8 vlan_cap[0x1]; 1041 u8 lro_cap[0x1]; 1042 u8 lro_psh_flag[0x1]; 1043 u8 lro_time_stamp[0x1]; 1044 u8 reserved_at_5[0x2]; 1045 u8 wqe_vlan_insert[0x1]; 1046 u8 self_lb_en_modifiable[0x1]; 1047 u8 reserved_at_9[0x2]; 1048 u8 max_lso_cap[0x5]; 1049 u8 multi_pkt_send_wqe[0x2]; 1050 u8 wqe_inline_mode[0x2]; 1051 u8 rss_ind_tbl_cap[0x4]; 1052 u8 reg_umr_sq[0x1]; 1053 u8 scatter_fcs[0x1]; 1054 u8 enhanced_multi_pkt_send_wqe[0x1]; 1055 u8 tunnel_lso_const_out_ip_id[0x1]; 1056 u8 tunnel_lro_gre[0x1]; 1057 u8 tunnel_lro_vxlan[0x1]; 1058 u8 tunnel_stateless_gre[0x1]; 1059 u8 tunnel_stateless_vxlan[0x1]; 1060 1061 u8 swp[0x1]; 1062 u8 swp_csum[0x1]; 1063 u8 swp_lso[0x1]; 1064 u8 cqe_checksum_full[0x1]; 1065 u8 tunnel_stateless_geneve_tx[0x1]; 1066 u8 tunnel_stateless_mpls_over_udp[0x1]; 1067 u8 tunnel_stateless_mpls_over_gre[0x1]; 1068 u8 tunnel_stateless_vxlan_gpe[0x1]; 1069 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1070 u8 tunnel_stateless_ip_over_ip[0x1]; 1071 u8 insert_trailer[0x1]; 1072 u8 reserved_at_2b[0x1]; 1073 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1074 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1075 u8 reserved_at_2e[0x2]; 1076 u8 max_vxlan_udp_ports[0x8]; 1077 u8 reserved_at_38[0x6]; 1078 u8 max_geneve_opt_len[0x1]; 1079 u8 tunnel_stateless_geneve_rx[0x1]; 1080 1081 u8 reserved_at_40[0x10]; 1082 u8 lro_min_mss_size[0x10]; 1083 1084 u8 reserved_at_60[0x120]; 1085 1086 u8 lro_timer_supported_periods[4][0x20]; 1087 1088 u8 reserved_at_200[0x600]; 1089 }; 1090 1091 enum { 1092 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1093 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1094 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1095 }; 1096 1097 struct mlx5_ifc_roce_cap_bits { 1098 u8 roce_apm[0x1]; 1099 u8 reserved_at_1[0x3]; 1100 u8 sw_r_roce_src_udp_port[0x1]; 1101 u8 fl_rc_qp_when_roce_disabled[0x1]; 1102 u8 fl_rc_qp_when_roce_enabled[0x1]; 1103 u8 reserved_at_7[0x1]; 1104 u8 qp_ooo_transmit_default[0x1]; 1105 u8 reserved_at_9[0x15]; 1106 u8 qp_ts_format[0x2]; 1107 1108 u8 reserved_at_20[0x60]; 1109 1110 u8 reserved_at_80[0xc]; 1111 u8 l3_type[0x4]; 1112 u8 reserved_at_90[0x8]; 1113 u8 roce_version[0x8]; 1114 1115 u8 reserved_at_a0[0x10]; 1116 u8 r_roce_dest_udp_port[0x10]; 1117 1118 u8 r_roce_max_src_udp_port[0x10]; 1119 u8 r_roce_min_src_udp_port[0x10]; 1120 1121 u8 reserved_at_e0[0x10]; 1122 u8 roce_address_table_size[0x10]; 1123 1124 u8 reserved_at_100[0x700]; 1125 }; 1126 1127 struct mlx5_ifc_sync_steering_in_bits { 1128 u8 opcode[0x10]; 1129 u8 uid[0x10]; 1130 1131 u8 reserved_at_20[0x10]; 1132 u8 op_mod[0x10]; 1133 1134 u8 reserved_at_40[0xc0]; 1135 }; 1136 1137 struct mlx5_ifc_sync_steering_out_bits { 1138 u8 status[0x8]; 1139 u8 reserved_at_8[0x18]; 1140 1141 u8 syndrome[0x20]; 1142 1143 u8 reserved_at_40[0x40]; 1144 }; 1145 1146 struct mlx5_ifc_sync_crypto_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0x20]; 1154 1155 u8 reserved_at_60[0x10]; 1156 u8 crypto_type[0x10]; 1157 1158 u8 reserved_at_80[0x80]; 1159 }; 1160 1161 struct mlx5_ifc_sync_crypto_out_bits { 1162 u8 status[0x8]; 1163 u8 reserved_at_8[0x18]; 1164 1165 u8 syndrome[0x20]; 1166 1167 u8 reserved_at_40[0x40]; 1168 }; 1169 1170 struct mlx5_ifc_device_mem_cap_bits { 1171 u8 memic[0x1]; 1172 u8 reserved_at_1[0x1f]; 1173 1174 u8 reserved_at_20[0xb]; 1175 u8 log_min_memic_alloc_size[0x5]; 1176 u8 reserved_at_30[0x8]; 1177 u8 log_max_memic_addr_alignment[0x8]; 1178 1179 u8 memic_bar_start_addr[0x40]; 1180 1181 u8 memic_bar_size[0x20]; 1182 1183 u8 max_memic_size[0x20]; 1184 1185 u8 steering_sw_icm_start_address[0x40]; 1186 1187 u8 reserved_at_100[0x8]; 1188 u8 log_header_modify_sw_icm_size[0x8]; 1189 u8 reserved_at_110[0x2]; 1190 u8 log_sw_icm_alloc_granularity[0x6]; 1191 u8 log_steering_sw_icm_size[0x8]; 1192 1193 u8 reserved_at_120[0x18]; 1194 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1195 1196 u8 header_modify_sw_icm_start_address[0x40]; 1197 1198 u8 reserved_at_180[0x40]; 1199 1200 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1201 1202 u8 memic_operations[0x20]; 1203 1204 u8 reserved_at_220[0x5e0]; 1205 }; 1206 1207 struct mlx5_ifc_device_event_cap_bits { 1208 u8 user_affiliated_events[4][0x40]; 1209 1210 u8 user_unaffiliated_events[4][0x40]; 1211 }; 1212 1213 struct mlx5_ifc_virtio_emulation_cap_bits { 1214 u8 desc_tunnel_offload_type[0x1]; 1215 u8 eth_frame_offload_type[0x1]; 1216 u8 virtio_version_1_0[0x1]; 1217 u8 device_features_bits_mask[0xd]; 1218 u8 event_mode[0x8]; 1219 u8 virtio_queue_type[0x8]; 1220 1221 u8 max_tunnel_desc[0x10]; 1222 u8 reserved_at_30[0x3]; 1223 u8 log_doorbell_stride[0x5]; 1224 u8 reserved_at_38[0x3]; 1225 u8 log_doorbell_bar_size[0x5]; 1226 1227 u8 doorbell_bar_offset[0x40]; 1228 1229 u8 max_emulated_devices[0x8]; 1230 u8 max_num_virtio_queues[0x18]; 1231 1232 u8 reserved_at_a0[0x60]; 1233 1234 u8 umem_1_buffer_param_a[0x20]; 1235 1236 u8 umem_1_buffer_param_b[0x20]; 1237 1238 u8 umem_2_buffer_param_a[0x20]; 1239 1240 u8 umem_2_buffer_param_b[0x20]; 1241 1242 u8 umem_3_buffer_param_a[0x20]; 1243 1244 u8 umem_3_buffer_param_b[0x20]; 1245 1246 u8 reserved_at_1c0[0x640]; 1247 }; 1248 1249 enum { 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1257 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1258 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1259 }; 1260 1261 enum { 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1271 }; 1272 1273 struct mlx5_ifc_atomic_caps_bits { 1274 u8 reserved_at_0[0x40]; 1275 1276 u8 atomic_req_8B_endianness_mode[0x2]; 1277 u8 reserved_at_42[0x4]; 1278 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1279 1280 u8 reserved_at_47[0x19]; 1281 1282 u8 reserved_at_60[0x20]; 1283 1284 u8 reserved_at_80[0x10]; 1285 u8 atomic_operations[0x10]; 1286 1287 u8 reserved_at_a0[0x10]; 1288 u8 atomic_size_qp[0x10]; 1289 1290 u8 reserved_at_c0[0x10]; 1291 u8 atomic_size_dc[0x10]; 1292 1293 u8 reserved_at_e0[0x720]; 1294 }; 1295 1296 struct mlx5_ifc_odp_cap_bits { 1297 u8 reserved_at_0[0x40]; 1298 1299 u8 sig[0x1]; 1300 u8 reserved_at_41[0x1f]; 1301 1302 u8 reserved_at_60[0x20]; 1303 1304 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1305 1306 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1307 1308 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1309 1310 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1311 1312 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1313 1314 u8 reserved_at_120[0x6E0]; 1315 }; 1316 1317 struct mlx5_ifc_calc_op { 1318 u8 reserved_at_0[0x10]; 1319 u8 reserved_at_10[0x9]; 1320 u8 op_swap_endianness[0x1]; 1321 u8 op_min[0x1]; 1322 u8 op_xor[0x1]; 1323 u8 op_or[0x1]; 1324 u8 op_and[0x1]; 1325 u8 op_max[0x1]; 1326 u8 op_add[0x1]; 1327 }; 1328 1329 struct mlx5_ifc_vector_calc_cap_bits { 1330 u8 calc_matrix[0x1]; 1331 u8 reserved_at_1[0x1f]; 1332 u8 reserved_at_20[0x8]; 1333 u8 max_vec_count[0x8]; 1334 u8 reserved_at_30[0xd]; 1335 u8 max_chunk_size[0x3]; 1336 struct mlx5_ifc_calc_op calc0; 1337 struct mlx5_ifc_calc_op calc1; 1338 struct mlx5_ifc_calc_op calc2; 1339 struct mlx5_ifc_calc_op calc3; 1340 1341 u8 reserved_at_c0[0x720]; 1342 }; 1343 1344 struct mlx5_ifc_tls_cap_bits { 1345 u8 tls_1_2_aes_gcm_128[0x1]; 1346 u8 tls_1_3_aes_gcm_128[0x1]; 1347 u8 tls_1_2_aes_gcm_256[0x1]; 1348 u8 tls_1_3_aes_gcm_256[0x1]; 1349 u8 reserved_at_4[0x1c]; 1350 1351 u8 reserved_at_20[0x7e0]; 1352 }; 1353 1354 struct mlx5_ifc_ipsec_cap_bits { 1355 u8 ipsec_full_offload[0x1]; 1356 u8 ipsec_crypto_offload[0x1]; 1357 u8 ipsec_esn[0x1]; 1358 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1359 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1360 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1361 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1362 u8 reserved_at_7[0x4]; 1363 u8 log_max_ipsec_offload[0x5]; 1364 u8 reserved_at_10[0x10]; 1365 1366 u8 min_log_ipsec_full_replay_window[0x8]; 1367 u8 max_log_ipsec_full_replay_window[0x8]; 1368 u8 reserved_at_30[0x7d0]; 1369 }; 1370 1371 struct mlx5_ifc_macsec_cap_bits { 1372 u8 macsec_epn[0x1]; 1373 u8 reserved_at_1[0x2]; 1374 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1375 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1376 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1377 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1378 u8 reserved_at_7[0x4]; 1379 u8 log_max_macsec_offload[0x5]; 1380 u8 reserved_at_10[0x10]; 1381 1382 u8 min_log_macsec_full_replay_window[0x8]; 1383 u8 max_log_macsec_full_replay_window[0x8]; 1384 u8 reserved_at_30[0x10]; 1385 1386 u8 reserved_at_40[0x7c0]; 1387 }; 1388 1389 enum { 1390 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1391 MLX5_WQ_TYPE_CYCLIC = 0x1, 1392 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1393 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1394 }; 1395 1396 enum { 1397 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1398 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1399 }; 1400 1401 enum { 1402 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1403 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1404 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1405 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1407 }; 1408 1409 enum { 1410 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1411 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1412 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1413 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1416 }; 1417 1418 enum { 1419 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1420 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1425 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1426 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1427 }; 1428 1429 enum { 1430 MLX5_CAP_PORT_TYPE_IB = 0x0, 1431 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1436 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1437 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1438 }; 1439 1440 enum { 1441 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1442 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1443 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1444 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1445 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1446 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1447 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1448 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1449 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1450 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1451 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1452 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1453 }; 1454 1455 enum { 1456 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1457 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1458 }; 1459 1460 #define MLX5_FC_BULK_SIZE_FACTOR 128 1461 1462 enum mlx5_fc_bulk_alloc_bitmask { 1463 MLX5_FC_BULK_128 = (1 << 0), 1464 MLX5_FC_BULK_256 = (1 << 1), 1465 MLX5_FC_BULK_512 = (1 << 2), 1466 MLX5_FC_BULK_1024 = (1 << 3), 1467 MLX5_FC_BULK_2048 = (1 << 4), 1468 MLX5_FC_BULK_4096 = (1 << 5), 1469 MLX5_FC_BULK_8192 = (1 << 6), 1470 MLX5_FC_BULK_16384 = (1 << 7), 1471 }; 1472 1473 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1474 1475 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1476 1477 enum { 1478 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1479 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1480 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1481 }; 1482 1483 struct mlx5_ifc_cmd_hca_cap_bits { 1484 u8 reserved_at_0[0x10]; 1485 u8 shared_object_to_user_object_allowed[0x1]; 1486 u8 reserved_at_13[0xe]; 1487 u8 vhca_resource_manager[0x1]; 1488 1489 u8 hca_cap_2[0x1]; 1490 u8 create_lag_when_not_master_up[0x1]; 1491 u8 dtor[0x1]; 1492 u8 event_on_vhca_state_teardown_request[0x1]; 1493 u8 event_on_vhca_state_in_use[0x1]; 1494 u8 event_on_vhca_state_active[0x1]; 1495 u8 event_on_vhca_state_allocated[0x1]; 1496 u8 event_on_vhca_state_invalid[0x1]; 1497 u8 reserved_at_28[0x8]; 1498 u8 vhca_id[0x10]; 1499 1500 u8 reserved_at_40[0x40]; 1501 1502 u8 log_max_srq_sz[0x8]; 1503 u8 log_max_qp_sz[0x8]; 1504 u8 event_cap[0x1]; 1505 u8 reserved_at_91[0x2]; 1506 u8 isolate_vl_tc_new[0x1]; 1507 u8 reserved_at_94[0x4]; 1508 u8 prio_tag_required[0x1]; 1509 u8 reserved_at_99[0x2]; 1510 u8 log_max_qp[0x5]; 1511 1512 u8 reserved_at_a0[0x3]; 1513 u8 ece_support[0x1]; 1514 u8 reserved_at_a4[0x5]; 1515 u8 reg_c_preserve[0x1]; 1516 u8 reserved_at_aa[0x1]; 1517 u8 log_max_srq[0x5]; 1518 u8 reserved_at_b0[0x1]; 1519 u8 uplink_follow[0x1]; 1520 u8 ts_cqe_to_dest_cqn[0x1]; 1521 u8 reserved_at_b3[0x6]; 1522 u8 go_back_n[0x1]; 1523 u8 shampo[0x1]; 1524 u8 reserved_at_bb[0x5]; 1525 1526 u8 max_sgl_for_optimized_performance[0x8]; 1527 u8 log_max_cq_sz[0x8]; 1528 u8 relaxed_ordering_write_umr[0x1]; 1529 u8 relaxed_ordering_read_umr[0x1]; 1530 u8 reserved_at_d2[0x7]; 1531 u8 virtio_net_device_emualtion_manager[0x1]; 1532 u8 virtio_blk_device_emualtion_manager[0x1]; 1533 u8 log_max_cq[0x5]; 1534 1535 u8 log_max_eq_sz[0x8]; 1536 u8 relaxed_ordering_write[0x1]; 1537 u8 relaxed_ordering_read_pci_enabled[0x1]; 1538 u8 log_max_mkey[0x6]; 1539 u8 reserved_at_f0[0x6]; 1540 u8 terminate_scatter_list_mkey[0x1]; 1541 u8 repeated_mkey[0x1]; 1542 u8 dump_fill_mkey[0x1]; 1543 u8 reserved_at_f9[0x2]; 1544 u8 fast_teardown[0x1]; 1545 u8 log_max_eq[0x4]; 1546 1547 u8 max_indirection[0x8]; 1548 u8 fixed_buffer_size[0x1]; 1549 u8 log_max_mrw_sz[0x7]; 1550 u8 force_teardown[0x1]; 1551 u8 reserved_at_111[0x1]; 1552 u8 log_max_bsf_list_size[0x6]; 1553 u8 umr_extended_translation_offset[0x1]; 1554 u8 null_mkey[0x1]; 1555 u8 log_max_klm_list_size[0x6]; 1556 1557 u8 reserved_at_120[0x2]; 1558 u8 qpc_extension[0x1]; 1559 u8 reserved_at_123[0x7]; 1560 u8 log_max_ra_req_dc[0x6]; 1561 u8 reserved_at_130[0x2]; 1562 u8 eth_wqe_too_small[0x1]; 1563 u8 reserved_at_133[0x6]; 1564 u8 vnic_env_cq_overrun[0x1]; 1565 u8 log_max_ra_res_dc[0x6]; 1566 1567 u8 reserved_at_140[0x5]; 1568 u8 release_all_pages[0x1]; 1569 u8 must_not_use[0x1]; 1570 u8 reserved_at_147[0x2]; 1571 u8 roce_accl[0x1]; 1572 u8 log_max_ra_req_qp[0x6]; 1573 u8 reserved_at_150[0xa]; 1574 u8 log_max_ra_res_qp[0x6]; 1575 1576 u8 end_pad[0x1]; 1577 u8 cc_query_allowed[0x1]; 1578 u8 cc_modify_allowed[0x1]; 1579 u8 start_pad[0x1]; 1580 u8 cache_line_128byte[0x1]; 1581 u8 reserved_at_165[0x4]; 1582 u8 rts2rts_qp_counters_set_id[0x1]; 1583 u8 reserved_at_16a[0x2]; 1584 u8 vnic_env_int_rq_oob[0x1]; 1585 u8 sbcam_reg[0x1]; 1586 u8 reserved_at_16e[0x1]; 1587 u8 qcam_reg[0x1]; 1588 u8 gid_table_size[0x10]; 1589 1590 u8 out_of_seq_cnt[0x1]; 1591 u8 vport_counters[0x1]; 1592 u8 retransmission_q_counters[0x1]; 1593 u8 debug[0x1]; 1594 u8 modify_rq_counter_set_id[0x1]; 1595 u8 rq_delay_drop[0x1]; 1596 u8 max_qp_cnt[0xa]; 1597 u8 pkey_table_size[0x10]; 1598 1599 u8 vport_group_manager[0x1]; 1600 u8 vhca_group_manager[0x1]; 1601 u8 ib_virt[0x1]; 1602 u8 eth_virt[0x1]; 1603 u8 vnic_env_queue_counters[0x1]; 1604 u8 ets[0x1]; 1605 u8 nic_flow_table[0x1]; 1606 u8 eswitch_manager[0x1]; 1607 u8 device_memory[0x1]; 1608 u8 mcam_reg[0x1]; 1609 u8 pcam_reg[0x1]; 1610 u8 local_ca_ack_delay[0x5]; 1611 u8 port_module_event[0x1]; 1612 u8 enhanced_error_q_counters[0x1]; 1613 u8 ports_check[0x1]; 1614 u8 reserved_at_1b3[0x1]; 1615 u8 disable_link_up[0x1]; 1616 u8 beacon_led[0x1]; 1617 u8 port_type[0x2]; 1618 u8 num_ports[0x8]; 1619 1620 u8 reserved_at_1c0[0x1]; 1621 u8 pps[0x1]; 1622 u8 pps_modify[0x1]; 1623 u8 log_max_msg[0x5]; 1624 u8 reserved_at_1c8[0x4]; 1625 u8 max_tc[0x4]; 1626 u8 temp_warn_event[0x1]; 1627 u8 dcbx[0x1]; 1628 u8 general_notification_event[0x1]; 1629 u8 reserved_at_1d3[0x2]; 1630 u8 fpga[0x1]; 1631 u8 rol_s[0x1]; 1632 u8 rol_g[0x1]; 1633 u8 reserved_at_1d8[0x1]; 1634 u8 wol_s[0x1]; 1635 u8 wol_g[0x1]; 1636 u8 wol_a[0x1]; 1637 u8 wol_b[0x1]; 1638 u8 wol_m[0x1]; 1639 u8 wol_u[0x1]; 1640 u8 wol_p[0x1]; 1641 1642 u8 stat_rate_support[0x10]; 1643 u8 reserved_at_1f0[0x1]; 1644 u8 pci_sync_for_fw_update_event[0x1]; 1645 u8 reserved_at_1f2[0x6]; 1646 u8 init2_lag_tx_port_affinity[0x1]; 1647 u8 reserved_at_1fa[0x3]; 1648 u8 cqe_version[0x4]; 1649 1650 u8 compact_address_vector[0x1]; 1651 u8 striding_rq[0x1]; 1652 u8 reserved_at_202[0x1]; 1653 u8 ipoib_enhanced_offloads[0x1]; 1654 u8 ipoib_basic_offloads[0x1]; 1655 u8 reserved_at_205[0x1]; 1656 u8 repeated_block_disabled[0x1]; 1657 u8 umr_modify_entity_size_disabled[0x1]; 1658 u8 umr_modify_atomic_disabled[0x1]; 1659 u8 umr_indirect_mkey_disabled[0x1]; 1660 u8 umr_fence[0x2]; 1661 u8 dc_req_scat_data_cqe[0x1]; 1662 u8 reserved_at_20d[0x2]; 1663 u8 drain_sigerr[0x1]; 1664 u8 cmdif_checksum[0x2]; 1665 u8 sigerr_cqe[0x1]; 1666 u8 reserved_at_213[0x1]; 1667 u8 wq_signature[0x1]; 1668 u8 sctr_data_cqe[0x1]; 1669 u8 reserved_at_216[0x1]; 1670 u8 sho[0x1]; 1671 u8 tph[0x1]; 1672 u8 rf[0x1]; 1673 u8 dct[0x1]; 1674 u8 qos[0x1]; 1675 u8 eth_net_offloads[0x1]; 1676 u8 roce[0x1]; 1677 u8 atomic[0x1]; 1678 u8 reserved_at_21f[0x1]; 1679 1680 u8 cq_oi[0x1]; 1681 u8 cq_resize[0x1]; 1682 u8 cq_moderation[0x1]; 1683 u8 reserved_at_223[0x3]; 1684 u8 cq_eq_remap[0x1]; 1685 u8 pg[0x1]; 1686 u8 block_lb_mc[0x1]; 1687 u8 reserved_at_229[0x1]; 1688 u8 scqe_break_moderation[0x1]; 1689 u8 cq_period_start_from_cqe[0x1]; 1690 u8 cd[0x1]; 1691 u8 reserved_at_22d[0x1]; 1692 u8 apm[0x1]; 1693 u8 vector_calc[0x1]; 1694 u8 umr_ptr_rlky[0x1]; 1695 u8 imaicl[0x1]; 1696 u8 qp_packet_based[0x1]; 1697 u8 reserved_at_233[0x3]; 1698 u8 qkv[0x1]; 1699 u8 pkv[0x1]; 1700 u8 set_deth_sqpn[0x1]; 1701 u8 reserved_at_239[0x3]; 1702 u8 xrc[0x1]; 1703 u8 ud[0x1]; 1704 u8 uc[0x1]; 1705 u8 rc[0x1]; 1706 1707 u8 uar_4k[0x1]; 1708 u8 reserved_at_241[0x7]; 1709 u8 fl_rc_qp_when_roce_disabled[0x1]; 1710 u8 regexp_params[0x1]; 1711 u8 uar_sz[0x6]; 1712 u8 port_selection_cap[0x1]; 1713 u8 reserved_at_251[0x1]; 1714 u8 umem_uid_0[0x1]; 1715 u8 reserved_at_253[0x5]; 1716 u8 log_pg_sz[0x8]; 1717 1718 u8 bf[0x1]; 1719 u8 driver_version[0x1]; 1720 u8 pad_tx_eth_packet[0x1]; 1721 u8 reserved_at_263[0x3]; 1722 u8 mkey_by_name[0x1]; 1723 u8 reserved_at_267[0x4]; 1724 1725 u8 log_bf_reg_size[0x5]; 1726 1727 u8 reserved_at_270[0x3]; 1728 u8 qp_error_syndrome[0x1]; 1729 u8 reserved_at_274[0x2]; 1730 u8 lag_dct[0x2]; 1731 u8 lag_tx_port_affinity[0x1]; 1732 u8 lag_native_fdb_selection[0x1]; 1733 u8 reserved_at_27a[0x1]; 1734 u8 lag_master[0x1]; 1735 u8 num_lag_ports[0x4]; 1736 1737 u8 reserved_at_280[0x10]; 1738 u8 max_wqe_sz_sq[0x10]; 1739 1740 u8 reserved_at_2a0[0x10]; 1741 u8 max_wqe_sz_rq[0x10]; 1742 1743 u8 max_flow_counter_31_16[0x10]; 1744 u8 max_wqe_sz_sq_dc[0x10]; 1745 1746 u8 reserved_at_2e0[0x7]; 1747 u8 max_qp_mcg[0x19]; 1748 1749 u8 reserved_at_300[0x10]; 1750 u8 flow_counter_bulk_alloc[0x8]; 1751 u8 log_max_mcg[0x8]; 1752 1753 u8 reserved_at_320[0x3]; 1754 u8 log_max_transport_domain[0x5]; 1755 u8 reserved_at_328[0x2]; 1756 u8 relaxed_ordering_read[0x1]; 1757 u8 log_max_pd[0x5]; 1758 u8 reserved_at_330[0x6]; 1759 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1760 u8 vnic_env_cnt_steering_fail[0x1]; 1761 u8 vport_counter_local_loopback[0x1]; 1762 u8 q_counter_aggregation[0x1]; 1763 u8 q_counter_other_vport[0x1]; 1764 u8 log_max_xrcd[0x5]; 1765 1766 u8 nic_receive_steering_discard[0x1]; 1767 u8 receive_discard_vport_down[0x1]; 1768 u8 transmit_discard_vport_down[0x1]; 1769 u8 eq_overrun_count[0x1]; 1770 u8 reserved_at_344[0x1]; 1771 u8 invalid_command_count[0x1]; 1772 u8 quota_exceeded_count[0x1]; 1773 u8 reserved_at_347[0x1]; 1774 u8 log_max_flow_counter_bulk[0x8]; 1775 u8 max_flow_counter_15_0[0x10]; 1776 1777 1778 u8 reserved_at_360[0x3]; 1779 u8 log_max_rq[0x5]; 1780 u8 reserved_at_368[0x3]; 1781 u8 log_max_sq[0x5]; 1782 u8 reserved_at_370[0x3]; 1783 u8 log_max_tir[0x5]; 1784 u8 reserved_at_378[0x3]; 1785 u8 log_max_tis[0x5]; 1786 1787 u8 basic_cyclic_rcv_wqe[0x1]; 1788 u8 reserved_at_381[0x2]; 1789 u8 log_max_rmp[0x5]; 1790 u8 reserved_at_388[0x3]; 1791 u8 log_max_rqt[0x5]; 1792 u8 reserved_at_390[0x3]; 1793 u8 log_max_rqt_size[0x5]; 1794 u8 reserved_at_398[0x3]; 1795 u8 log_max_tis_per_sq[0x5]; 1796 1797 u8 ext_stride_num_range[0x1]; 1798 u8 roce_rw_supported[0x1]; 1799 u8 log_max_current_uc_list_wr_supported[0x1]; 1800 u8 log_max_stride_sz_rq[0x5]; 1801 u8 reserved_at_3a8[0x3]; 1802 u8 log_min_stride_sz_rq[0x5]; 1803 u8 reserved_at_3b0[0x3]; 1804 u8 log_max_stride_sz_sq[0x5]; 1805 u8 reserved_at_3b8[0x3]; 1806 u8 log_min_stride_sz_sq[0x5]; 1807 1808 u8 hairpin[0x1]; 1809 u8 reserved_at_3c1[0x2]; 1810 u8 log_max_hairpin_queues[0x5]; 1811 u8 reserved_at_3c8[0x3]; 1812 u8 log_max_hairpin_wq_data_sz[0x5]; 1813 u8 reserved_at_3d0[0x3]; 1814 u8 log_max_hairpin_num_packets[0x5]; 1815 u8 reserved_at_3d8[0x3]; 1816 u8 log_max_wq_sz[0x5]; 1817 1818 u8 nic_vport_change_event[0x1]; 1819 u8 disable_local_lb_uc[0x1]; 1820 u8 disable_local_lb_mc[0x1]; 1821 u8 log_min_hairpin_wq_data_sz[0x5]; 1822 u8 reserved_at_3e8[0x2]; 1823 u8 vhca_state[0x1]; 1824 u8 log_max_vlan_list[0x5]; 1825 u8 reserved_at_3f0[0x3]; 1826 u8 log_max_current_mc_list[0x5]; 1827 u8 reserved_at_3f8[0x3]; 1828 u8 log_max_current_uc_list[0x5]; 1829 1830 u8 general_obj_types[0x40]; 1831 1832 u8 sq_ts_format[0x2]; 1833 u8 rq_ts_format[0x2]; 1834 u8 steering_format_version[0x4]; 1835 u8 create_qp_start_hint[0x18]; 1836 1837 u8 reserved_at_460[0x1]; 1838 u8 ats[0x1]; 1839 u8 reserved_at_462[0x1]; 1840 u8 log_max_uctx[0x5]; 1841 u8 reserved_at_468[0x1]; 1842 u8 crypto[0x1]; 1843 u8 ipsec_offload[0x1]; 1844 u8 log_max_umem[0x5]; 1845 u8 max_num_eqs[0x10]; 1846 1847 u8 reserved_at_480[0x1]; 1848 u8 tls_tx[0x1]; 1849 u8 tls_rx[0x1]; 1850 u8 log_max_l2_table[0x5]; 1851 u8 reserved_at_488[0x8]; 1852 u8 log_uar_page_sz[0x10]; 1853 1854 u8 reserved_at_4a0[0x20]; 1855 u8 device_frequency_mhz[0x20]; 1856 u8 device_frequency_khz[0x20]; 1857 1858 u8 reserved_at_500[0x20]; 1859 u8 num_of_uars_per_page[0x20]; 1860 1861 u8 flex_parser_protocols[0x20]; 1862 1863 u8 max_geneve_tlv_options[0x8]; 1864 u8 reserved_at_568[0x3]; 1865 u8 max_geneve_tlv_option_data_len[0x5]; 1866 u8 reserved_at_570[0x9]; 1867 u8 adv_virtualization[0x1]; 1868 u8 reserved_at_57a[0x6]; 1869 1870 u8 reserved_at_580[0xb]; 1871 u8 log_max_dci_stream_channels[0x5]; 1872 u8 reserved_at_590[0x3]; 1873 u8 log_max_dci_errored_streams[0x5]; 1874 u8 reserved_at_598[0x8]; 1875 1876 u8 reserved_at_5a0[0x10]; 1877 u8 enhanced_cqe_compression[0x1]; 1878 u8 reserved_at_5b1[0x2]; 1879 u8 log_max_dek[0x5]; 1880 u8 reserved_at_5b8[0x4]; 1881 u8 mini_cqe_resp_stride_index[0x1]; 1882 u8 cqe_128_always[0x1]; 1883 u8 cqe_compression_128[0x1]; 1884 u8 cqe_compression[0x1]; 1885 1886 u8 cqe_compression_timeout[0x10]; 1887 u8 cqe_compression_max_num[0x10]; 1888 1889 u8 reserved_at_5e0[0x8]; 1890 u8 flex_parser_id_gtpu_dw_0[0x4]; 1891 u8 reserved_at_5ec[0x4]; 1892 u8 tag_matching[0x1]; 1893 u8 rndv_offload_rc[0x1]; 1894 u8 rndv_offload_dc[0x1]; 1895 u8 log_tag_matching_list_sz[0x5]; 1896 u8 reserved_at_5f8[0x3]; 1897 u8 log_max_xrq[0x5]; 1898 1899 u8 affiliate_nic_vport_criteria[0x8]; 1900 u8 native_port_num[0x8]; 1901 u8 num_vhca_ports[0x8]; 1902 u8 flex_parser_id_gtpu_teid[0x4]; 1903 u8 reserved_at_61c[0x2]; 1904 u8 sw_owner_id[0x1]; 1905 u8 reserved_at_61f[0x1]; 1906 1907 u8 max_num_of_monitor_counters[0x10]; 1908 u8 num_ppcnt_monitor_counters[0x10]; 1909 1910 u8 max_num_sf[0x10]; 1911 u8 num_q_monitor_counters[0x10]; 1912 1913 u8 reserved_at_660[0x20]; 1914 1915 u8 sf[0x1]; 1916 u8 sf_set_partition[0x1]; 1917 u8 reserved_at_682[0x1]; 1918 u8 log_max_sf[0x5]; 1919 u8 apu[0x1]; 1920 u8 reserved_at_689[0x4]; 1921 u8 migration[0x1]; 1922 u8 reserved_at_68e[0x2]; 1923 u8 log_min_sf_size[0x8]; 1924 u8 max_num_sf_partitions[0x8]; 1925 1926 u8 uctx_cap[0x20]; 1927 1928 u8 reserved_at_6c0[0x4]; 1929 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1930 u8 flex_parser_id_icmp_dw1[0x4]; 1931 u8 flex_parser_id_icmp_dw0[0x4]; 1932 u8 flex_parser_id_icmpv6_dw1[0x4]; 1933 u8 flex_parser_id_icmpv6_dw0[0x4]; 1934 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1935 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1936 1937 u8 max_num_match_definer[0x10]; 1938 u8 sf_base_id[0x10]; 1939 1940 u8 flex_parser_id_gtpu_dw_2[0x4]; 1941 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1942 u8 num_total_dynamic_vf_msix[0x18]; 1943 u8 reserved_at_720[0x14]; 1944 u8 dynamic_msix_table_size[0xc]; 1945 u8 reserved_at_740[0xc]; 1946 u8 min_dynamic_vf_msix_table_size[0x4]; 1947 u8 reserved_at_750[0x4]; 1948 u8 max_dynamic_vf_msix_table_size[0xc]; 1949 1950 u8 reserved_at_760[0x3]; 1951 u8 log_max_num_header_modify_argument[0x5]; 1952 u8 reserved_at_768[0x4]; 1953 u8 log_header_modify_argument_granularity[0x4]; 1954 u8 reserved_at_770[0x3]; 1955 u8 log_header_modify_argument_max_alloc[0x5]; 1956 u8 reserved_at_778[0x8]; 1957 1958 u8 vhca_tunnel_commands[0x40]; 1959 u8 match_definer_format_supported[0x40]; 1960 }; 1961 1962 struct mlx5_ifc_cmd_hca_cap_2_bits { 1963 u8 reserved_at_0[0x80]; 1964 1965 u8 migratable[0x1]; 1966 u8 reserved_at_81[0x1f]; 1967 1968 u8 max_reformat_insert_size[0x8]; 1969 u8 max_reformat_insert_offset[0x8]; 1970 u8 max_reformat_remove_size[0x8]; 1971 u8 max_reformat_remove_offset[0x8]; 1972 1973 u8 reserved_at_c0[0x8]; 1974 u8 migration_multi_load[0x1]; 1975 u8 migration_tracking_state[0x1]; 1976 u8 reserved_at_ca[0x16]; 1977 1978 u8 reserved_at_e0[0xc0]; 1979 1980 u8 flow_table_type_2_type[0x8]; 1981 u8 reserved_at_1a8[0x3]; 1982 u8 log_min_mkey_entity_size[0x5]; 1983 u8 reserved_at_1b0[0x10]; 1984 1985 u8 reserved_at_1c0[0x60]; 1986 1987 u8 reserved_at_220[0x1]; 1988 u8 sw_vhca_id_valid[0x1]; 1989 u8 sw_vhca_id[0xe]; 1990 u8 reserved_at_230[0x10]; 1991 1992 u8 reserved_at_240[0xb]; 1993 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1994 u8 reserved_at_250[0x10]; 1995 1996 u8 reserved_at_260[0x120]; 1997 u8 reserved_at_380[0x10]; 1998 u8 ec_vf_vport_base[0x10]; 1999 u8 reserved_at_3a0[0x460]; 2000 }; 2001 2002 enum mlx5_ifc_flow_destination_type { 2003 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2004 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2005 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2006 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2007 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2008 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2009 }; 2010 2011 enum mlx5_flow_table_miss_action { 2012 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2013 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2014 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2015 }; 2016 2017 struct mlx5_ifc_dest_format_struct_bits { 2018 u8 destination_type[0x8]; 2019 u8 destination_id[0x18]; 2020 2021 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2022 u8 packet_reformat[0x1]; 2023 u8 reserved_at_22[0x6]; 2024 u8 destination_table_type[0x8]; 2025 u8 destination_eswitch_owner_vhca_id[0x10]; 2026 }; 2027 2028 struct mlx5_ifc_flow_counter_list_bits { 2029 u8 flow_counter_id[0x20]; 2030 2031 u8 reserved_at_20[0x20]; 2032 }; 2033 2034 struct mlx5_ifc_extended_dest_format_bits { 2035 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2036 2037 u8 packet_reformat_id[0x20]; 2038 2039 u8 reserved_at_60[0x20]; 2040 }; 2041 2042 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2043 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2044 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2045 }; 2046 2047 struct mlx5_ifc_fte_match_param_bits { 2048 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2049 2050 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2051 2052 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2053 2054 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2055 2056 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2057 2058 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2059 2060 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2061 2062 u8 reserved_at_e00[0x200]; 2063 }; 2064 2065 enum { 2066 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2067 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2068 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2069 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2070 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2071 }; 2072 2073 struct mlx5_ifc_rx_hash_field_select_bits { 2074 u8 l3_prot_type[0x1]; 2075 u8 l4_prot_type[0x1]; 2076 u8 selected_fields[0x1e]; 2077 }; 2078 2079 enum { 2080 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2081 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2082 }; 2083 2084 enum { 2085 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2086 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2087 }; 2088 2089 struct mlx5_ifc_wq_bits { 2090 u8 wq_type[0x4]; 2091 u8 wq_signature[0x1]; 2092 u8 end_padding_mode[0x2]; 2093 u8 cd_slave[0x1]; 2094 u8 reserved_at_8[0x18]; 2095 2096 u8 hds_skip_first_sge[0x1]; 2097 u8 log2_hds_buf_size[0x3]; 2098 u8 reserved_at_24[0x7]; 2099 u8 page_offset[0x5]; 2100 u8 lwm[0x10]; 2101 2102 u8 reserved_at_40[0x8]; 2103 u8 pd[0x18]; 2104 2105 u8 reserved_at_60[0x8]; 2106 u8 uar_page[0x18]; 2107 2108 u8 dbr_addr[0x40]; 2109 2110 u8 hw_counter[0x20]; 2111 2112 u8 sw_counter[0x20]; 2113 2114 u8 reserved_at_100[0xc]; 2115 u8 log_wq_stride[0x4]; 2116 u8 reserved_at_110[0x3]; 2117 u8 log_wq_pg_sz[0x5]; 2118 u8 reserved_at_118[0x3]; 2119 u8 log_wq_sz[0x5]; 2120 2121 u8 dbr_umem_valid[0x1]; 2122 u8 wq_umem_valid[0x1]; 2123 u8 reserved_at_122[0x1]; 2124 u8 log_hairpin_num_packets[0x5]; 2125 u8 reserved_at_128[0x3]; 2126 u8 log_hairpin_data_sz[0x5]; 2127 2128 u8 reserved_at_130[0x4]; 2129 u8 log_wqe_num_of_strides[0x4]; 2130 u8 two_byte_shift_en[0x1]; 2131 u8 reserved_at_139[0x4]; 2132 u8 log_wqe_stride_size[0x3]; 2133 2134 u8 reserved_at_140[0x80]; 2135 2136 u8 headers_mkey[0x20]; 2137 2138 u8 shampo_enable[0x1]; 2139 u8 reserved_at_1e1[0x4]; 2140 u8 log_reservation_size[0x3]; 2141 u8 reserved_at_1e8[0x5]; 2142 u8 log_max_num_of_packets_per_reservation[0x3]; 2143 u8 reserved_at_1f0[0x6]; 2144 u8 log_headers_entry_size[0x2]; 2145 u8 reserved_at_1f8[0x4]; 2146 u8 log_headers_buffer_entry_num[0x4]; 2147 2148 u8 reserved_at_200[0x400]; 2149 2150 struct mlx5_ifc_cmd_pas_bits pas[]; 2151 }; 2152 2153 struct mlx5_ifc_rq_num_bits { 2154 u8 reserved_at_0[0x8]; 2155 u8 rq_num[0x18]; 2156 }; 2157 2158 struct mlx5_ifc_mac_address_layout_bits { 2159 u8 reserved_at_0[0x10]; 2160 u8 mac_addr_47_32[0x10]; 2161 2162 u8 mac_addr_31_0[0x20]; 2163 }; 2164 2165 struct mlx5_ifc_vlan_layout_bits { 2166 u8 reserved_at_0[0x14]; 2167 u8 vlan[0x0c]; 2168 2169 u8 reserved_at_20[0x20]; 2170 }; 2171 2172 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2173 u8 reserved_at_0[0xa0]; 2174 2175 u8 min_time_between_cnps[0x20]; 2176 2177 u8 reserved_at_c0[0x12]; 2178 u8 cnp_dscp[0x6]; 2179 u8 reserved_at_d8[0x4]; 2180 u8 cnp_prio_mode[0x1]; 2181 u8 cnp_802p_prio[0x3]; 2182 2183 u8 reserved_at_e0[0x720]; 2184 }; 2185 2186 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2187 u8 reserved_at_0[0x60]; 2188 2189 u8 reserved_at_60[0x4]; 2190 u8 clamp_tgt_rate[0x1]; 2191 u8 reserved_at_65[0x3]; 2192 u8 clamp_tgt_rate_after_time_inc[0x1]; 2193 u8 reserved_at_69[0x17]; 2194 2195 u8 reserved_at_80[0x20]; 2196 2197 u8 rpg_time_reset[0x20]; 2198 2199 u8 rpg_byte_reset[0x20]; 2200 2201 u8 rpg_threshold[0x20]; 2202 2203 u8 rpg_max_rate[0x20]; 2204 2205 u8 rpg_ai_rate[0x20]; 2206 2207 u8 rpg_hai_rate[0x20]; 2208 2209 u8 rpg_gd[0x20]; 2210 2211 u8 rpg_min_dec_fac[0x20]; 2212 2213 u8 rpg_min_rate[0x20]; 2214 2215 u8 reserved_at_1c0[0xe0]; 2216 2217 u8 rate_to_set_on_first_cnp[0x20]; 2218 2219 u8 dce_tcp_g[0x20]; 2220 2221 u8 dce_tcp_rtt[0x20]; 2222 2223 u8 rate_reduce_monitor_period[0x20]; 2224 2225 u8 reserved_at_320[0x20]; 2226 2227 u8 initial_alpha_value[0x20]; 2228 2229 u8 reserved_at_360[0x4a0]; 2230 }; 2231 2232 struct mlx5_ifc_cong_control_r_roce_general_bits { 2233 u8 reserved_at_0[0x80]; 2234 2235 u8 reserved_at_80[0x10]; 2236 u8 rtt_resp_dscp_valid[0x1]; 2237 u8 reserved_at_91[0x9]; 2238 u8 rtt_resp_dscp[0x6]; 2239 2240 u8 reserved_at_a0[0x760]; 2241 }; 2242 2243 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2244 u8 reserved_at_0[0x80]; 2245 2246 u8 rppp_max_rps[0x20]; 2247 2248 u8 rpg_time_reset[0x20]; 2249 2250 u8 rpg_byte_reset[0x20]; 2251 2252 u8 rpg_threshold[0x20]; 2253 2254 u8 rpg_max_rate[0x20]; 2255 2256 u8 rpg_ai_rate[0x20]; 2257 2258 u8 rpg_hai_rate[0x20]; 2259 2260 u8 rpg_gd[0x20]; 2261 2262 u8 rpg_min_dec_fac[0x20]; 2263 2264 u8 rpg_min_rate[0x20]; 2265 2266 u8 reserved_at_1c0[0x640]; 2267 }; 2268 2269 enum { 2270 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2271 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2272 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2273 }; 2274 2275 struct mlx5_ifc_resize_field_select_bits { 2276 u8 resize_field_select[0x20]; 2277 }; 2278 2279 struct mlx5_ifc_resource_dump_bits { 2280 u8 more_dump[0x1]; 2281 u8 inline_dump[0x1]; 2282 u8 reserved_at_2[0xa]; 2283 u8 seq_num[0x4]; 2284 u8 segment_type[0x10]; 2285 2286 u8 reserved_at_20[0x10]; 2287 u8 vhca_id[0x10]; 2288 2289 u8 index1[0x20]; 2290 2291 u8 index2[0x20]; 2292 2293 u8 num_of_obj1[0x10]; 2294 u8 num_of_obj2[0x10]; 2295 2296 u8 reserved_at_a0[0x20]; 2297 2298 u8 device_opaque[0x40]; 2299 2300 u8 mkey[0x20]; 2301 2302 u8 size[0x20]; 2303 2304 u8 address[0x40]; 2305 2306 u8 inline_data[52][0x20]; 2307 }; 2308 2309 struct mlx5_ifc_resource_dump_menu_record_bits { 2310 u8 reserved_at_0[0x4]; 2311 u8 num_of_obj2_supports_active[0x1]; 2312 u8 num_of_obj2_supports_all[0x1]; 2313 u8 must_have_num_of_obj2[0x1]; 2314 u8 support_num_of_obj2[0x1]; 2315 u8 num_of_obj1_supports_active[0x1]; 2316 u8 num_of_obj1_supports_all[0x1]; 2317 u8 must_have_num_of_obj1[0x1]; 2318 u8 support_num_of_obj1[0x1]; 2319 u8 must_have_index2[0x1]; 2320 u8 support_index2[0x1]; 2321 u8 must_have_index1[0x1]; 2322 u8 support_index1[0x1]; 2323 u8 segment_type[0x10]; 2324 2325 u8 segment_name[4][0x20]; 2326 2327 u8 index1_name[4][0x20]; 2328 2329 u8 index2_name[4][0x20]; 2330 }; 2331 2332 struct mlx5_ifc_resource_dump_segment_header_bits { 2333 u8 length_dw[0x10]; 2334 u8 segment_type[0x10]; 2335 }; 2336 2337 struct mlx5_ifc_resource_dump_command_segment_bits { 2338 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2339 2340 u8 segment_called[0x10]; 2341 u8 vhca_id[0x10]; 2342 2343 u8 index1[0x20]; 2344 2345 u8 index2[0x20]; 2346 2347 u8 num_of_obj1[0x10]; 2348 u8 num_of_obj2[0x10]; 2349 }; 2350 2351 struct mlx5_ifc_resource_dump_error_segment_bits { 2352 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2353 2354 u8 reserved_at_20[0x10]; 2355 u8 syndrome_id[0x10]; 2356 2357 u8 reserved_at_40[0x40]; 2358 2359 u8 error[8][0x20]; 2360 }; 2361 2362 struct mlx5_ifc_resource_dump_info_segment_bits { 2363 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2364 2365 u8 reserved_at_20[0x18]; 2366 u8 dump_version[0x8]; 2367 2368 u8 hw_version[0x20]; 2369 2370 u8 fw_version[0x20]; 2371 }; 2372 2373 struct mlx5_ifc_resource_dump_menu_segment_bits { 2374 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2375 2376 u8 reserved_at_20[0x10]; 2377 u8 num_of_records[0x10]; 2378 2379 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2380 }; 2381 2382 struct mlx5_ifc_resource_dump_resource_segment_bits { 2383 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2384 2385 u8 reserved_at_20[0x20]; 2386 2387 u8 index1[0x20]; 2388 2389 u8 index2[0x20]; 2390 2391 u8 payload[][0x20]; 2392 }; 2393 2394 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2395 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2396 }; 2397 2398 struct mlx5_ifc_menu_resource_dump_response_bits { 2399 struct mlx5_ifc_resource_dump_info_segment_bits info; 2400 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2401 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2402 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2403 }; 2404 2405 enum { 2406 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2407 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2408 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2409 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2410 }; 2411 2412 struct mlx5_ifc_modify_field_select_bits { 2413 u8 modify_field_select[0x20]; 2414 }; 2415 2416 struct mlx5_ifc_field_select_r_roce_np_bits { 2417 u8 field_select_r_roce_np[0x20]; 2418 }; 2419 2420 struct mlx5_ifc_field_select_r_roce_rp_bits { 2421 u8 field_select_r_roce_rp[0x20]; 2422 }; 2423 2424 enum { 2425 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2426 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2427 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2428 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2429 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2430 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2431 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2432 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2433 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2434 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2435 }; 2436 2437 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2438 u8 field_select_8021qaurp[0x20]; 2439 }; 2440 2441 struct mlx5_ifc_phys_layer_cntrs_bits { 2442 u8 time_since_last_clear_high[0x20]; 2443 2444 u8 time_since_last_clear_low[0x20]; 2445 2446 u8 symbol_errors_high[0x20]; 2447 2448 u8 symbol_errors_low[0x20]; 2449 2450 u8 sync_headers_errors_high[0x20]; 2451 2452 u8 sync_headers_errors_low[0x20]; 2453 2454 u8 edpl_bip_errors_lane0_high[0x20]; 2455 2456 u8 edpl_bip_errors_lane0_low[0x20]; 2457 2458 u8 edpl_bip_errors_lane1_high[0x20]; 2459 2460 u8 edpl_bip_errors_lane1_low[0x20]; 2461 2462 u8 edpl_bip_errors_lane2_high[0x20]; 2463 2464 u8 edpl_bip_errors_lane2_low[0x20]; 2465 2466 u8 edpl_bip_errors_lane3_high[0x20]; 2467 2468 u8 edpl_bip_errors_lane3_low[0x20]; 2469 2470 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2471 2472 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2473 2474 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2475 2476 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2477 2478 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2479 2480 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2481 2482 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2483 2484 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2485 2486 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2487 2488 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2489 2490 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2491 2492 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2493 2494 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2495 2496 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2497 2498 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2499 2500 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2501 2502 u8 rs_fec_corrected_blocks_high[0x20]; 2503 2504 u8 rs_fec_corrected_blocks_low[0x20]; 2505 2506 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2507 2508 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2509 2510 u8 rs_fec_no_errors_blocks_high[0x20]; 2511 2512 u8 rs_fec_no_errors_blocks_low[0x20]; 2513 2514 u8 rs_fec_single_error_blocks_high[0x20]; 2515 2516 u8 rs_fec_single_error_blocks_low[0x20]; 2517 2518 u8 rs_fec_corrected_symbols_total_high[0x20]; 2519 2520 u8 rs_fec_corrected_symbols_total_low[0x20]; 2521 2522 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2523 2524 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2525 2526 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2527 2528 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2529 2530 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2531 2532 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2533 2534 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2535 2536 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2537 2538 u8 link_down_events[0x20]; 2539 2540 u8 successful_recovery_events[0x20]; 2541 2542 u8 reserved_at_640[0x180]; 2543 }; 2544 2545 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2546 u8 time_since_last_clear_high[0x20]; 2547 2548 u8 time_since_last_clear_low[0x20]; 2549 2550 u8 phy_received_bits_high[0x20]; 2551 2552 u8 phy_received_bits_low[0x20]; 2553 2554 u8 phy_symbol_errors_high[0x20]; 2555 2556 u8 phy_symbol_errors_low[0x20]; 2557 2558 u8 phy_corrected_bits_high[0x20]; 2559 2560 u8 phy_corrected_bits_low[0x20]; 2561 2562 u8 phy_corrected_bits_lane0_high[0x20]; 2563 2564 u8 phy_corrected_bits_lane0_low[0x20]; 2565 2566 u8 phy_corrected_bits_lane1_high[0x20]; 2567 2568 u8 phy_corrected_bits_lane1_low[0x20]; 2569 2570 u8 phy_corrected_bits_lane2_high[0x20]; 2571 2572 u8 phy_corrected_bits_lane2_low[0x20]; 2573 2574 u8 phy_corrected_bits_lane3_high[0x20]; 2575 2576 u8 phy_corrected_bits_lane3_low[0x20]; 2577 2578 u8 reserved_at_200[0x5c0]; 2579 }; 2580 2581 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2582 u8 symbol_error_counter[0x10]; 2583 2584 u8 link_error_recovery_counter[0x8]; 2585 2586 u8 link_downed_counter[0x8]; 2587 2588 u8 port_rcv_errors[0x10]; 2589 2590 u8 port_rcv_remote_physical_errors[0x10]; 2591 2592 u8 port_rcv_switch_relay_errors[0x10]; 2593 2594 u8 port_xmit_discards[0x10]; 2595 2596 u8 port_xmit_constraint_errors[0x8]; 2597 2598 u8 port_rcv_constraint_errors[0x8]; 2599 2600 u8 reserved_at_70[0x8]; 2601 2602 u8 link_overrun_errors[0x8]; 2603 2604 u8 reserved_at_80[0x10]; 2605 2606 u8 vl_15_dropped[0x10]; 2607 2608 u8 reserved_at_a0[0x80]; 2609 2610 u8 port_xmit_wait[0x20]; 2611 }; 2612 2613 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2614 u8 transmit_queue_high[0x20]; 2615 2616 u8 transmit_queue_low[0x20]; 2617 2618 u8 no_buffer_discard_uc_high[0x20]; 2619 2620 u8 no_buffer_discard_uc_low[0x20]; 2621 2622 u8 reserved_at_80[0x740]; 2623 }; 2624 2625 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2626 u8 wred_discard_high[0x20]; 2627 2628 u8 wred_discard_low[0x20]; 2629 2630 u8 ecn_marked_tc_high[0x20]; 2631 2632 u8 ecn_marked_tc_low[0x20]; 2633 2634 u8 reserved_at_80[0x740]; 2635 }; 2636 2637 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2638 u8 rx_octets_high[0x20]; 2639 2640 u8 rx_octets_low[0x20]; 2641 2642 u8 reserved_at_40[0xc0]; 2643 2644 u8 rx_frames_high[0x20]; 2645 2646 u8 rx_frames_low[0x20]; 2647 2648 u8 tx_octets_high[0x20]; 2649 2650 u8 tx_octets_low[0x20]; 2651 2652 u8 reserved_at_180[0xc0]; 2653 2654 u8 tx_frames_high[0x20]; 2655 2656 u8 tx_frames_low[0x20]; 2657 2658 u8 rx_pause_high[0x20]; 2659 2660 u8 rx_pause_low[0x20]; 2661 2662 u8 rx_pause_duration_high[0x20]; 2663 2664 u8 rx_pause_duration_low[0x20]; 2665 2666 u8 tx_pause_high[0x20]; 2667 2668 u8 tx_pause_low[0x20]; 2669 2670 u8 tx_pause_duration_high[0x20]; 2671 2672 u8 tx_pause_duration_low[0x20]; 2673 2674 u8 rx_pause_transition_high[0x20]; 2675 2676 u8 rx_pause_transition_low[0x20]; 2677 2678 u8 rx_discards_high[0x20]; 2679 2680 u8 rx_discards_low[0x20]; 2681 2682 u8 device_stall_minor_watermark_cnt_high[0x20]; 2683 2684 u8 device_stall_minor_watermark_cnt_low[0x20]; 2685 2686 u8 device_stall_critical_watermark_cnt_high[0x20]; 2687 2688 u8 device_stall_critical_watermark_cnt_low[0x20]; 2689 2690 u8 reserved_at_480[0x340]; 2691 }; 2692 2693 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2694 u8 port_transmit_wait_high[0x20]; 2695 2696 u8 port_transmit_wait_low[0x20]; 2697 2698 u8 reserved_at_40[0x100]; 2699 2700 u8 rx_buffer_almost_full_high[0x20]; 2701 2702 u8 rx_buffer_almost_full_low[0x20]; 2703 2704 u8 rx_buffer_full_high[0x20]; 2705 2706 u8 rx_buffer_full_low[0x20]; 2707 2708 u8 rx_icrc_encapsulated_high[0x20]; 2709 2710 u8 rx_icrc_encapsulated_low[0x20]; 2711 2712 u8 reserved_at_200[0x5c0]; 2713 }; 2714 2715 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2716 u8 dot3stats_alignment_errors_high[0x20]; 2717 2718 u8 dot3stats_alignment_errors_low[0x20]; 2719 2720 u8 dot3stats_fcs_errors_high[0x20]; 2721 2722 u8 dot3stats_fcs_errors_low[0x20]; 2723 2724 u8 dot3stats_single_collision_frames_high[0x20]; 2725 2726 u8 dot3stats_single_collision_frames_low[0x20]; 2727 2728 u8 dot3stats_multiple_collision_frames_high[0x20]; 2729 2730 u8 dot3stats_multiple_collision_frames_low[0x20]; 2731 2732 u8 dot3stats_sqe_test_errors_high[0x20]; 2733 2734 u8 dot3stats_sqe_test_errors_low[0x20]; 2735 2736 u8 dot3stats_deferred_transmissions_high[0x20]; 2737 2738 u8 dot3stats_deferred_transmissions_low[0x20]; 2739 2740 u8 dot3stats_late_collisions_high[0x20]; 2741 2742 u8 dot3stats_late_collisions_low[0x20]; 2743 2744 u8 dot3stats_excessive_collisions_high[0x20]; 2745 2746 u8 dot3stats_excessive_collisions_low[0x20]; 2747 2748 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2749 2750 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2751 2752 u8 dot3stats_carrier_sense_errors_high[0x20]; 2753 2754 u8 dot3stats_carrier_sense_errors_low[0x20]; 2755 2756 u8 dot3stats_frame_too_longs_high[0x20]; 2757 2758 u8 dot3stats_frame_too_longs_low[0x20]; 2759 2760 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2761 2762 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2763 2764 u8 dot3stats_symbol_errors_high[0x20]; 2765 2766 u8 dot3stats_symbol_errors_low[0x20]; 2767 2768 u8 dot3control_in_unknown_opcodes_high[0x20]; 2769 2770 u8 dot3control_in_unknown_opcodes_low[0x20]; 2771 2772 u8 dot3in_pause_frames_high[0x20]; 2773 2774 u8 dot3in_pause_frames_low[0x20]; 2775 2776 u8 dot3out_pause_frames_high[0x20]; 2777 2778 u8 dot3out_pause_frames_low[0x20]; 2779 2780 u8 reserved_at_400[0x3c0]; 2781 }; 2782 2783 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2784 u8 ether_stats_drop_events_high[0x20]; 2785 2786 u8 ether_stats_drop_events_low[0x20]; 2787 2788 u8 ether_stats_octets_high[0x20]; 2789 2790 u8 ether_stats_octets_low[0x20]; 2791 2792 u8 ether_stats_pkts_high[0x20]; 2793 2794 u8 ether_stats_pkts_low[0x20]; 2795 2796 u8 ether_stats_broadcast_pkts_high[0x20]; 2797 2798 u8 ether_stats_broadcast_pkts_low[0x20]; 2799 2800 u8 ether_stats_multicast_pkts_high[0x20]; 2801 2802 u8 ether_stats_multicast_pkts_low[0x20]; 2803 2804 u8 ether_stats_crc_align_errors_high[0x20]; 2805 2806 u8 ether_stats_crc_align_errors_low[0x20]; 2807 2808 u8 ether_stats_undersize_pkts_high[0x20]; 2809 2810 u8 ether_stats_undersize_pkts_low[0x20]; 2811 2812 u8 ether_stats_oversize_pkts_high[0x20]; 2813 2814 u8 ether_stats_oversize_pkts_low[0x20]; 2815 2816 u8 ether_stats_fragments_high[0x20]; 2817 2818 u8 ether_stats_fragments_low[0x20]; 2819 2820 u8 ether_stats_jabbers_high[0x20]; 2821 2822 u8 ether_stats_jabbers_low[0x20]; 2823 2824 u8 ether_stats_collisions_high[0x20]; 2825 2826 u8 ether_stats_collisions_low[0x20]; 2827 2828 u8 ether_stats_pkts64octets_high[0x20]; 2829 2830 u8 ether_stats_pkts64octets_low[0x20]; 2831 2832 u8 ether_stats_pkts65to127octets_high[0x20]; 2833 2834 u8 ether_stats_pkts65to127octets_low[0x20]; 2835 2836 u8 ether_stats_pkts128to255octets_high[0x20]; 2837 2838 u8 ether_stats_pkts128to255octets_low[0x20]; 2839 2840 u8 ether_stats_pkts256to511octets_high[0x20]; 2841 2842 u8 ether_stats_pkts256to511octets_low[0x20]; 2843 2844 u8 ether_stats_pkts512to1023octets_high[0x20]; 2845 2846 u8 ether_stats_pkts512to1023octets_low[0x20]; 2847 2848 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2849 2850 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2851 2852 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2853 2854 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2855 2856 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2857 2858 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2859 2860 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2861 2862 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2863 2864 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2865 2866 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2867 2868 u8 reserved_at_540[0x280]; 2869 }; 2870 2871 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2872 u8 if_in_octets_high[0x20]; 2873 2874 u8 if_in_octets_low[0x20]; 2875 2876 u8 if_in_ucast_pkts_high[0x20]; 2877 2878 u8 if_in_ucast_pkts_low[0x20]; 2879 2880 u8 if_in_discards_high[0x20]; 2881 2882 u8 if_in_discards_low[0x20]; 2883 2884 u8 if_in_errors_high[0x20]; 2885 2886 u8 if_in_errors_low[0x20]; 2887 2888 u8 if_in_unknown_protos_high[0x20]; 2889 2890 u8 if_in_unknown_protos_low[0x20]; 2891 2892 u8 if_out_octets_high[0x20]; 2893 2894 u8 if_out_octets_low[0x20]; 2895 2896 u8 if_out_ucast_pkts_high[0x20]; 2897 2898 u8 if_out_ucast_pkts_low[0x20]; 2899 2900 u8 if_out_discards_high[0x20]; 2901 2902 u8 if_out_discards_low[0x20]; 2903 2904 u8 if_out_errors_high[0x20]; 2905 2906 u8 if_out_errors_low[0x20]; 2907 2908 u8 if_in_multicast_pkts_high[0x20]; 2909 2910 u8 if_in_multicast_pkts_low[0x20]; 2911 2912 u8 if_in_broadcast_pkts_high[0x20]; 2913 2914 u8 if_in_broadcast_pkts_low[0x20]; 2915 2916 u8 if_out_multicast_pkts_high[0x20]; 2917 2918 u8 if_out_multicast_pkts_low[0x20]; 2919 2920 u8 if_out_broadcast_pkts_high[0x20]; 2921 2922 u8 if_out_broadcast_pkts_low[0x20]; 2923 2924 u8 reserved_at_340[0x480]; 2925 }; 2926 2927 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2928 u8 a_frames_transmitted_ok_high[0x20]; 2929 2930 u8 a_frames_transmitted_ok_low[0x20]; 2931 2932 u8 a_frames_received_ok_high[0x20]; 2933 2934 u8 a_frames_received_ok_low[0x20]; 2935 2936 u8 a_frame_check_sequence_errors_high[0x20]; 2937 2938 u8 a_frame_check_sequence_errors_low[0x20]; 2939 2940 u8 a_alignment_errors_high[0x20]; 2941 2942 u8 a_alignment_errors_low[0x20]; 2943 2944 u8 a_octets_transmitted_ok_high[0x20]; 2945 2946 u8 a_octets_transmitted_ok_low[0x20]; 2947 2948 u8 a_octets_received_ok_high[0x20]; 2949 2950 u8 a_octets_received_ok_low[0x20]; 2951 2952 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2953 2954 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2955 2956 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2957 2958 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2959 2960 u8 a_multicast_frames_received_ok_high[0x20]; 2961 2962 u8 a_multicast_frames_received_ok_low[0x20]; 2963 2964 u8 a_broadcast_frames_received_ok_high[0x20]; 2965 2966 u8 a_broadcast_frames_received_ok_low[0x20]; 2967 2968 u8 a_in_range_length_errors_high[0x20]; 2969 2970 u8 a_in_range_length_errors_low[0x20]; 2971 2972 u8 a_out_of_range_length_field_high[0x20]; 2973 2974 u8 a_out_of_range_length_field_low[0x20]; 2975 2976 u8 a_frame_too_long_errors_high[0x20]; 2977 2978 u8 a_frame_too_long_errors_low[0x20]; 2979 2980 u8 a_symbol_error_during_carrier_high[0x20]; 2981 2982 u8 a_symbol_error_during_carrier_low[0x20]; 2983 2984 u8 a_mac_control_frames_transmitted_high[0x20]; 2985 2986 u8 a_mac_control_frames_transmitted_low[0x20]; 2987 2988 u8 a_mac_control_frames_received_high[0x20]; 2989 2990 u8 a_mac_control_frames_received_low[0x20]; 2991 2992 u8 a_unsupported_opcodes_received_high[0x20]; 2993 2994 u8 a_unsupported_opcodes_received_low[0x20]; 2995 2996 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2997 2998 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2999 3000 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3001 3002 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3003 3004 u8 reserved_at_4c0[0x300]; 3005 }; 3006 3007 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3008 u8 life_time_counter_high[0x20]; 3009 3010 u8 life_time_counter_low[0x20]; 3011 3012 u8 rx_errors[0x20]; 3013 3014 u8 tx_errors[0x20]; 3015 3016 u8 l0_to_recovery_eieos[0x20]; 3017 3018 u8 l0_to_recovery_ts[0x20]; 3019 3020 u8 l0_to_recovery_framing[0x20]; 3021 3022 u8 l0_to_recovery_retrain[0x20]; 3023 3024 u8 crc_error_dllp[0x20]; 3025 3026 u8 crc_error_tlp[0x20]; 3027 3028 u8 tx_overflow_buffer_pkt_high[0x20]; 3029 3030 u8 tx_overflow_buffer_pkt_low[0x20]; 3031 3032 u8 outbound_stalled_reads[0x20]; 3033 3034 u8 outbound_stalled_writes[0x20]; 3035 3036 u8 outbound_stalled_reads_events[0x20]; 3037 3038 u8 outbound_stalled_writes_events[0x20]; 3039 3040 u8 reserved_at_200[0x5c0]; 3041 }; 3042 3043 struct mlx5_ifc_cmd_inter_comp_event_bits { 3044 u8 command_completion_vector[0x20]; 3045 3046 u8 reserved_at_20[0xc0]; 3047 }; 3048 3049 struct mlx5_ifc_stall_vl_event_bits { 3050 u8 reserved_at_0[0x18]; 3051 u8 port_num[0x1]; 3052 u8 reserved_at_19[0x3]; 3053 u8 vl[0x4]; 3054 3055 u8 reserved_at_20[0xa0]; 3056 }; 3057 3058 struct mlx5_ifc_db_bf_congestion_event_bits { 3059 u8 event_subtype[0x8]; 3060 u8 reserved_at_8[0x8]; 3061 u8 congestion_level[0x8]; 3062 u8 reserved_at_18[0x8]; 3063 3064 u8 reserved_at_20[0xa0]; 3065 }; 3066 3067 struct mlx5_ifc_gpio_event_bits { 3068 u8 reserved_at_0[0x60]; 3069 3070 u8 gpio_event_hi[0x20]; 3071 3072 u8 gpio_event_lo[0x20]; 3073 3074 u8 reserved_at_a0[0x40]; 3075 }; 3076 3077 struct mlx5_ifc_port_state_change_event_bits { 3078 u8 reserved_at_0[0x40]; 3079 3080 u8 port_num[0x4]; 3081 u8 reserved_at_44[0x1c]; 3082 3083 u8 reserved_at_60[0x80]; 3084 }; 3085 3086 struct mlx5_ifc_dropped_packet_logged_bits { 3087 u8 reserved_at_0[0xe0]; 3088 }; 3089 3090 struct mlx5_ifc_default_timeout_bits { 3091 u8 to_multiplier[0x3]; 3092 u8 reserved_at_3[0x9]; 3093 u8 to_value[0x14]; 3094 }; 3095 3096 struct mlx5_ifc_dtor_reg_bits { 3097 u8 reserved_at_0[0x20]; 3098 3099 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3100 3101 u8 reserved_at_40[0x60]; 3102 3103 struct mlx5_ifc_default_timeout_bits health_poll_to; 3104 3105 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3106 3107 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3108 3109 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3110 3111 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3112 3113 struct mlx5_ifc_default_timeout_bits tear_down_to; 3114 3115 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3116 3117 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3118 3119 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3120 3121 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3122 3123 u8 reserved_at_1c0[0x20]; 3124 }; 3125 3126 enum { 3127 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3128 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3129 }; 3130 3131 struct mlx5_ifc_cq_error_bits { 3132 u8 reserved_at_0[0x8]; 3133 u8 cqn[0x18]; 3134 3135 u8 reserved_at_20[0x20]; 3136 3137 u8 reserved_at_40[0x18]; 3138 u8 syndrome[0x8]; 3139 3140 u8 reserved_at_60[0x80]; 3141 }; 3142 3143 struct mlx5_ifc_rdma_page_fault_event_bits { 3144 u8 bytes_committed[0x20]; 3145 3146 u8 r_key[0x20]; 3147 3148 u8 reserved_at_40[0x10]; 3149 u8 packet_len[0x10]; 3150 3151 u8 rdma_op_len[0x20]; 3152 3153 u8 rdma_va[0x40]; 3154 3155 u8 reserved_at_c0[0x5]; 3156 u8 rdma[0x1]; 3157 u8 write[0x1]; 3158 u8 requestor[0x1]; 3159 u8 qp_number[0x18]; 3160 }; 3161 3162 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3163 u8 bytes_committed[0x20]; 3164 3165 u8 reserved_at_20[0x10]; 3166 u8 wqe_index[0x10]; 3167 3168 u8 reserved_at_40[0x10]; 3169 u8 len[0x10]; 3170 3171 u8 reserved_at_60[0x60]; 3172 3173 u8 reserved_at_c0[0x5]; 3174 u8 rdma[0x1]; 3175 u8 write_read[0x1]; 3176 u8 requestor[0x1]; 3177 u8 qpn[0x18]; 3178 }; 3179 3180 struct mlx5_ifc_qp_events_bits { 3181 u8 reserved_at_0[0xa0]; 3182 3183 u8 type[0x8]; 3184 u8 reserved_at_a8[0x18]; 3185 3186 u8 reserved_at_c0[0x8]; 3187 u8 qpn_rqn_sqn[0x18]; 3188 }; 3189 3190 struct mlx5_ifc_dct_events_bits { 3191 u8 reserved_at_0[0xc0]; 3192 3193 u8 reserved_at_c0[0x8]; 3194 u8 dct_number[0x18]; 3195 }; 3196 3197 struct mlx5_ifc_comp_event_bits { 3198 u8 reserved_at_0[0xc0]; 3199 3200 u8 reserved_at_c0[0x8]; 3201 u8 cq_number[0x18]; 3202 }; 3203 3204 enum { 3205 MLX5_QPC_STATE_RST = 0x0, 3206 MLX5_QPC_STATE_INIT = 0x1, 3207 MLX5_QPC_STATE_RTR = 0x2, 3208 MLX5_QPC_STATE_RTS = 0x3, 3209 MLX5_QPC_STATE_SQER = 0x4, 3210 MLX5_QPC_STATE_ERR = 0x6, 3211 MLX5_QPC_STATE_SQD = 0x7, 3212 MLX5_QPC_STATE_SUSPENDED = 0x9, 3213 }; 3214 3215 enum { 3216 MLX5_QPC_ST_RC = 0x0, 3217 MLX5_QPC_ST_UC = 0x1, 3218 MLX5_QPC_ST_UD = 0x2, 3219 MLX5_QPC_ST_XRC = 0x3, 3220 MLX5_QPC_ST_DCI = 0x5, 3221 MLX5_QPC_ST_QP0 = 0x7, 3222 MLX5_QPC_ST_QP1 = 0x8, 3223 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3224 MLX5_QPC_ST_REG_UMR = 0xc, 3225 }; 3226 3227 enum { 3228 MLX5_QPC_PM_STATE_ARMED = 0x0, 3229 MLX5_QPC_PM_STATE_REARM = 0x1, 3230 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3231 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3232 }; 3233 3234 enum { 3235 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3236 }; 3237 3238 enum { 3239 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3240 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3241 }; 3242 3243 enum { 3244 MLX5_QPC_MTU_256_BYTES = 0x1, 3245 MLX5_QPC_MTU_512_BYTES = 0x2, 3246 MLX5_QPC_MTU_1K_BYTES = 0x3, 3247 MLX5_QPC_MTU_2K_BYTES = 0x4, 3248 MLX5_QPC_MTU_4K_BYTES = 0x5, 3249 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3250 }; 3251 3252 enum { 3253 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3254 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3255 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3256 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3257 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3258 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3259 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3260 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3261 }; 3262 3263 enum { 3264 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3265 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3266 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3267 }; 3268 3269 enum { 3270 MLX5_QPC_CS_RES_DISABLE = 0x0, 3271 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3272 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3273 }; 3274 3275 enum { 3276 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3277 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3278 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3279 }; 3280 3281 struct mlx5_ifc_qpc_bits { 3282 u8 state[0x4]; 3283 u8 lag_tx_port_affinity[0x4]; 3284 u8 st[0x8]; 3285 u8 reserved_at_10[0x2]; 3286 u8 isolate_vl_tc[0x1]; 3287 u8 pm_state[0x2]; 3288 u8 reserved_at_15[0x1]; 3289 u8 req_e2e_credit_mode[0x2]; 3290 u8 offload_type[0x4]; 3291 u8 end_padding_mode[0x2]; 3292 u8 reserved_at_1e[0x2]; 3293 3294 u8 wq_signature[0x1]; 3295 u8 block_lb_mc[0x1]; 3296 u8 atomic_like_write_en[0x1]; 3297 u8 latency_sensitive[0x1]; 3298 u8 reserved_at_24[0x1]; 3299 u8 drain_sigerr[0x1]; 3300 u8 reserved_at_26[0x2]; 3301 u8 pd[0x18]; 3302 3303 u8 mtu[0x3]; 3304 u8 log_msg_max[0x5]; 3305 u8 reserved_at_48[0x1]; 3306 u8 log_rq_size[0x4]; 3307 u8 log_rq_stride[0x3]; 3308 u8 no_sq[0x1]; 3309 u8 log_sq_size[0x4]; 3310 u8 reserved_at_55[0x1]; 3311 u8 retry_mode[0x2]; 3312 u8 ts_format[0x2]; 3313 u8 reserved_at_5a[0x1]; 3314 u8 rlky[0x1]; 3315 u8 ulp_stateless_offload_mode[0x4]; 3316 3317 u8 counter_set_id[0x8]; 3318 u8 uar_page[0x18]; 3319 3320 u8 reserved_at_80[0x8]; 3321 u8 user_index[0x18]; 3322 3323 u8 reserved_at_a0[0x3]; 3324 u8 log_page_size[0x5]; 3325 u8 remote_qpn[0x18]; 3326 3327 struct mlx5_ifc_ads_bits primary_address_path; 3328 3329 struct mlx5_ifc_ads_bits secondary_address_path; 3330 3331 u8 log_ack_req_freq[0x4]; 3332 u8 reserved_at_384[0x4]; 3333 u8 log_sra_max[0x3]; 3334 u8 reserved_at_38b[0x2]; 3335 u8 retry_count[0x3]; 3336 u8 rnr_retry[0x3]; 3337 u8 reserved_at_393[0x1]; 3338 u8 fre[0x1]; 3339 u8 cur_rnr_retry[0x3]; 3340 u8 cur_retry_count[0x3]; 3341 u8 reserved_at_39b[0x5]; 3342 3343 u8 reserved_at_3a0[0x20]; 3344 3345 u8 reserved_at_3c0[0x8]; 3346 u8 next_send_psn[0x18]; 3347 3348 u8 reserved_at_3e0[0x3]; 3349 u8 log_num_dci_stream_channels[0x5]; 3350 u8 cqn_snd[0x18]; 3351 3352 u8 reserved_at_400[0x3]; 3353 u8 log_num_dci_errored_streams[0x5]; 3354 u8 deth_sqpn[0x18]; 3355 3356 u8 reserved_at_420[0x20]; 3357 3358 u8 reserved_at_440[0x8]; 3359 u8 last_acked_psn[0x18]; 3360 3361 u8 reserved_at_460[0x8]; 3362 u8 ssn[0x18]; 3363 3364 u8 reserved_at_480[0x8]; 3365 u8 log_rra_max[0x3]; 3366 u8 reserved_at_48b[0x1]; 3367 u8 atomic_mode[0x4]; 3368 u8 rre[0x1]; 3369 u8 rwe[0x1]; 3370 u8 rae[0x1]; 3371 u8 reserved_at_493[0x1]; 3372 u8 page_offset[0x6]; 3373 u8 reserved_at_49a[0x3]; 3374 u8 cd_slave_receive[0x1]; 3375 u8 cd_slave_send[0x1]; 3376 u8 cd_master[0x1]; 3377 3378 u8 reserved_at_4a0[0x3]; 3379 u8 min_rnr_nak[0x5]; 3380 u8 next_rcv_psn[0x18]; 3381 3382 u8 reserved_at_4c0[0x8]; 3383 u8 xrcd[0x18]; 3384 3385 u8 reserved_at_4e0[0x8]; 3386 u8 cqn_rcv[0x18]; 3387 3388 u8 dbr_addr[0x40]; 3389 3390 u8 q_key[0x20]; 3391 3392 u8 reserved_at_560[0x5]; 3393 u8 rq_type[0x3]; 3394 u8 srqn_rmpn_xrqn[0x18]; 3395 3396 u8 reserved_at_580[0x8]; 3397 u8 rmsn[0x18]; 3398 3399 u8 hw_sq_wqebb_counter[0x10]; 3400 u8 sw_sq_wqebb_counter[0x10]; 3401 3402 u8 hw_rq_counter[0x20]; 3403 3404 u8 sw_rq_counter[0x20]; 3405 3406 u8 reserved_at_600[0x20]; 3407 3408 u8 reserved_at_620[0xf]; 3409 u8 cgs[0x1]; 3410 u8 cs_req[0x8]; 3411 u8 cs_res[0x8]; 3412 3413 u8 dc_access_key[0x40]; 3414 3415 u8 reserved_at_680[0x3]; 3416 u8 dbr_umem_valid[0x1]; 3417 3418 u8 reserved_at_684[0xbc]; 3419 }; 3420 3421 struct mlx5_ifc_roce_addr_layout_bits { 3422 u8 source_l3_address[16][0x8]; 3423 3424 u8 reserved_at_80[0x3]; 3425 u8 vlan_valid[0x1]; 3426 u8 vlan_id[0xc]; 3427 u8 source_mac_47_32[0x10]; 3428 3429 u8 source_mac_31_0[0x20]; 3430 3431 u8 reserved_at_c0[0x14]; 3432 u8 roce_l3_type[0x4]; 3433 u8 roce_version[0x8]; 3434 3435 u8 reserved_at_e0[0x20]; 3436 }; 3437 3438 struct mlx5_ifc_shampo_cap_bits { 3439 u8 reserved_at_0[0x3]; 3440 u8 shampo_log_max_reservation_size[0x5]; 3441 u8 reserved_at_8[0x3]; 3442 u8 shampo_log_min_reservation_size[0x5]; 3443 u8 shampo_min_mss_size[0x10]; 3444 3445 u8 reserved_at_20[0x3]; 3446 u8 shampo_max_log_headers_entry_size[0x5]; 3447 u8 reserved_at_28[0x18]; 3448 3449 u8 reserved_at_40[0x7c0]; 3450 }; 3451 3452 struct mlx5_ifc_crypto_cap_bits { 3453 u8 reserved_at_0[0x3]; 3454 u8 synchronize_dek[0x1]; 3455 u8 int_kek_manual[0x1]; 3456 u8 int_kek_auto[0x1]; 3457 u8 reserved_at_6[0x1a]; 3458 3459 u8 reserved_at_20[0x3]; 3460 u8 log_dek_max_alloc[0x5]; 3461 u8 reserved_at_28[0x3]; 3462 u8 log_max_num_deks[0x5]; 3463 u8 reserved_at_30[0x10]; 3464 3465 u8 reserved_at_40[0x20]; 3466 3467 u8 reserved_at_60[0x3]; 3468 u8 log_dek_granularity[0x5]; 3469 u8 reserved_at_68[0x3]; 3470 u8 log_max_num_int_kek[0x5]; 3471 u8 sw_wrapped_dek[0x10]; 3472 3473 u8 reserved_at_80[0x780]; 3474 }; 3475 3476 union mlx5_ifc_hca_cap_union_bits { 3477 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3478 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3479 struct mlx5_ifc_odp_cap_bits odp_cap; 3480 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3481 struct mlx5_ifc_roce_cap_bits roce_cap; 3482 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3483 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3484 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3485 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3486 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3487 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3488 struct mlx5_ifc_qos_cap_bits qos_cap; 3489 struct mlx5_ifc_debug_cap_bits debug_cap; 3490 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3491 struct mlx5_ifc_tls_cap_bits tls_cap; 3492 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3493 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3494 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3495 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3496 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3497 u8 reserved_at_0[0x8000]; 3498 }; 3499 3500 enum { 3501 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3502 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3503 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3504 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3505 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3506 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3507 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3508 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3509 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3510 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3511 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3512 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3513 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3514 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3515 }; 3516 3517 enum { 3518 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3519 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3520 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3521 }; 3522 3523 enum { 3524 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3525 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3526 }; 3527 3528 struct mlx5_ifc_vlan_bits { 3529 u8 ethtype[0x10]; 3530 u8 prio[0x3]; 3531 u8 cfi[0x1]; 3532 u8 vid[0xc]; 3533 }; 3534 3535 enum { 3536 MLX5_FLOW_METER_COLOR_RED = 0x0, 3537 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3538 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3539 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3540 }; 3541 3542 enum { 3543 MLX5_EXE_ASO_FLOW_METER = 0x2, 3544 }; 3545 3546 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3547 u8 return_reg_id[0x4]; 3548 u8 aso_type[0x4]; 3549 u8 reserved_at_8[0x14]; 3550 u8 action[0x1]; 3551 u8 init_color[0x2]; 3552 u8 meter_id[0x1]; 3553 }; 3554 3555 union mlx5_ifc_exe_aso_ctrl { 3556 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3557 }; 3558 3559 struct mlx5_ifc_execute_aso_bits { 3560 u8 valid[0x1]; 3561 u8 reserved_at_1[0x7]; 3562 u8 aso_object_id[0x18]; 3563 3564 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3565 }; 3566 3567 struct mlx5_ifc_flow_context_bits { 3568 struct mlx5_ifc_vlan_bits push_vlan; 3569 3570 u8 group_id[0x20]; 3571 3572 u8 reserved_at_40[0x8]; 3573 u8 flow_tag[0x18]; 3574 3575 u8 reserved_at_60[0x10]; 3576 u8 action[0x10]; 3577 3578 u8 extended_destination[0x1]; 3579 u8 reserved_at_81[0x1]; 3580 u8 flow_source[0x2]; 3581 u8 encrypt_decrypt_type[0x4]; 3582 u8 destination_list_size[0x18]; 3583 3584 u8 reserved_at_a0[0x8]; 3585 u8 flow_counter_list_size[0x18]; 3586 3587 u8 packet_reformat_id[0x20]; 3588 3589 u8 modify_header_id[0x20]; 3590 3591 struct mlx5_ifc_vlan_bits push_vlan_2; 3592 3593 u8 encrypt_decrypt_obj_id[0x20]; 3594 u8 reserved_at_140[0xc0]; 3595 3596 struct mlx5_ifc_fte_match_param_bits match_value; 3597 3598 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3599 3600 u8 reserved_at_1300[0x500]; 3601 3602 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3603 }; 3604 3605 enum { 3606 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3607 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3608 }; 3609 3610 struct mlx5_ifc_xrc_srqc_bits { 3611 u8 state[0x4]; 3612 u8 log_xrc_srq_size[0x4]; 3613 u8 reserved_at_8[0x18]; 3614 3615 u8 wq_signature[0x1]; 3616 u8 cont_srq[0x1]; 3617 u8 reserved_at_22[0x1]; 3618 u8 rlky[0x1]; 3619 u8 basic_cyclic_rcv_wqe[0x1]; 3620 u8 log_rq_stride[0x3]; 3621 u8 xrcd[0x18]; 3622 3623 u8 page_offset[0x6]; 3624 u8 reserved_at_46[0x1]; 3625 u8 dbr_umem_valid[0x1]; 3626 u8 cqn[0x18]; 3627 3628 u8 reserved_at_60[0x20]; 3629 3630 u8 user_index_equal_xrc_srqn[0x1]; 3631 u8 reserved_at_81[0x1]; 3632 u8 log_page_size[0x6]; 3633 u8 user_index[0x18]; 3634 3635 u8 reserved_at_a0[0x20]; 3636 3637 u8 reserved_at_c0[0x8]; 3638 u8 pd[0x18]; 3639 3640 u8 lwm[0x10]; 3641 u8 wqe_cnt[0x10]; 3642 3643 u8 reserved_at_100[0x40]; 3644 3645 u8 db_record_addr_h[0x20]; 3646 3647 u8 db_record_addr_l[0x1e]; 3648 u8 reserved_at_17e[0x2]; 3649 3650 u8 reserved_at_180[0x80]; 3651 }; 3652 3653 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3654 u8 counter_error_queues[0x20]; 3655 3656 u8 total_error_queues[0x20]; 3657 3658 u8 send_queue_priority_update_flow[0x20]; 3659 3660 u8 reserved_at_60[0x20]; 3661 3662 u8 nic_receive_steering_discard[0x40]; 3663 3664 u8 receive_discard_vport_down[0x40]; 3665 3666 u8 transmit_discard_vport_down[0x40]; 3667 3668 u8 async_eq_overrun[0x20]; 3669 3670 u8 comp_eq_overrun[0x20]; 3671 3672 u8 reserved_at_180[0x20]; 3673 3674 u8 invalid_command[0x20]; 3675 3676 u8 quota_exceeded_command[0x20]; 3677 3678 u8 internal_rq_out_of_buffer[0x20]; 3679 3680 u8 cq_overrun[0x20]; 3681 3682 u8 eth_wqe_too_small[0x20]; 3683 3684 u8 reserved_at_220[0xc0]; 3685 3686 u8 generated_pkt_steering_fail[0x40]; 3687 3688 u8 handled_pkt_steering_fail[0x40]; 3689 3690 u8 reserved_at_360[0xc80]; 3691 }; 3692 3693 struct mlx5_ifc_traffic_counter_bits { 3694 u8 packets[0x40]; 3695 3696 u8 octets[0x40]; 3697 }; 3698 3699 struct mlx5_ifc_tisc_bits { 3700 u8 strict_lag_tx_port_affinity[0x1]; 3701 u8 tls_en[0x1]; 3702 u8 reserved_at_2[0x2]; 3703 u8 lag_tx_port_affinity[0x04]; 3704 3705 u8 reserved_at_8[0x4]; 3706 u8 prio[0x4]; 3707 u8 reserved_at_10[0x10]; 3708 3709 u8 reserved_at_20[0x100]; 3710 3711 u8 reserved_at_120[0x8]; 3712 u8 transport_domain[0x18]; 3713 3714 u8 reserved_at_140[0x8]; 3715 u8 underlay_qpn[0x18]; 3716 3717 u8 reserved_at_160[0x8]; 3718 u8 pd[0x18]; 3719 3720 u8 reserved_at_180[0x380]; 3721 }; 3722 3723 enum { 3724 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3725 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3726 }; 3727 3728 enum { 3729 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3730 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3731 }; 3732 3733 enum { 3734 MLX5_RX_HASH_FN_NONE = 0x0, 3735 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3736 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3737 }; 3738 3739 enum { 3740 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3741 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3742 }; 3743 3744 struct mlx5_ifc_tirc_bits { 3745 u8 reserved_at_0[0x20]; 3746 3747 u8 disp_type[0x4]; 3748 u8 tls_en[0x1]; 3749 u8 reserved_at_25[0x1b]; 3750 3751 u8 reserved_at_40[0x40]; 3752 3753 u8 reserved_at_80[0x4]; 3754 u8 lro_timeout_period_usecs[0x10]; 3755 u8 packet_merge_mask[0x4]; 3756 u8 lro_max_ip_payload_size[0x8]; 3757 3758 u8 reserved_at_a0[0x40]; 3759 3760 u8 reserved_at_e0[0x8]; 3761 u8 inline_rqn[0x18]; 3762 3763 u8 rx_hash_symmetric[0x1]; 3764 u8 reserved_at_101[0x1]; 3765 u8 tunneled_offload_en[0x1]; 3766 u8 reserved_at_103[0x5]; 3767 u8 indirect_table[0x18]; 3768 3769 u8 rx_hash_fn[0x4]; 3770 u8 reserved_at_124[0x2]; 3771 u8 self_lb_block[0x2]; 3772 u8 transport_domain[0x18]; 3773 3774 u8 rx_hash_toeplitz_key[10][0x20]; 3775 3776 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3777 3778 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3779 3780 u8 reserved_at_2c0[0x4c0]; 3781 }; 3782 3783 enum { 3784 MLX5_SRQC_STATE_GOOD = 0x0, 3785 MLX5_SRQC_STATE_ERROR = 0x1, 3786 }; 3787 3788 struct mlx5_ifc_srqc_bits { 3789 u8 state[0x4]; 3790 u8 log_srq_size[0x4]; 3791 u8 reserved_at_8[0x18]; 3792 3793 u8 wq_signature[0x1]; 3794 u8 cont_srq[0x1]; 3795 u8 reserved_at_22[0x1]; 3796 u8 rlky[0x1]; 3797 u8 reserved_at_24[0x1]; 3798 u8 log_rq_stride[0x3]; 3799 u8 xrcd[0x18]; 3800 3801 u8 page_offset[0x6]; 3802 u8 reserved_at_46[0x2]; 3803 u8 cqn[0x18]; 3804 3805 u8 reserved_at_60[0x20]; 3806 3807 u8 reserved_at_80[0x2]; 3808 u8 log_page_size[0x6]; 3809 u8 reserved_at_88[0x18]; 3810 3811 u8 reserved_at_a0[0x20]; 3812 3813 u8 reserved_at_c0[0x8]; 3814 u8 pd[0x18]; 3815 3816 u8 lwm[0x10]; 3817 u8 wqe_cnt[0x10]; 3818 3819 u8 reserved_at_100[0x40]; 3820 3821 u8 dbr_addr[0x40]; 3822 3823 u8 reserved_at_180[0x80]; 3824 }; 3825 3826 enum { 3827 MLX5_SQC_STATE_RST = 0x0, 3828 MLX5_SQC_STATE_RDY = 0x1, 3829 MLX5_SQC_STATE_ERR = 0x3, 3830 }; 3831 3832 struct mlx5_ifc_sqc_bits { 3833 u8 rlky[0x1]; 3834 u8 cd_master[0x1]; 3835 u8 fre[0x1]; 3836 u8 flush_in_error_en[0x1]; 3837 u8 allow_multi_pkt_send_wqe[0x1]; 3838 u8 min_wqe_inline_mode[0x3]; 3839 u8 state[0x4]; 3840 u8 reg_umr[0x1]; 3841 u8 allow_swp[0x1]; 3842 u8 hairpin[0x1]; 3843 u8 reserved_at_f[0xb]; 3844 u8 ts_format[0x2]; 3845 u8 reserved_at_1c[0x4]; 3846 3847 u8 reserved_at_20[0x8]; 3848 u8 user_index[0x18]; 3849 3850 u8 reserved_at_40[0x8]; 3851 u8 cqn[0x18]; 3852 3853 u8 reserved_at_60[0x8]; 3854 u8 hairpin_peer_rq[0x18]; 3855 3856 u8 reserved_at_80[0x10]; 3857 u8 hairpin_peer_vhca[0x10]; 3858 3859 u8 reserved_at_a0[0x20]; 3860 3861 u8 reserved_at_c0[0x8]; 3862 u8 ts_cqe_to_dest_cqn[0x18]; 3863 3864 u8 reserved_at_e0[0x10]; 3865 u8 packet_pacing_rate_limit_index[0x10]; 3866 u8 tis_lst_sz[0x10]; 3867 u8 qos_queue_group_id[0x10]; 3868 3869 u8 reserved_at_120[0x40]; 3870 3871 u8 reserved_at_160[0x8]; 3872 u8 tis_num_0[0x18]; 3873 3874 struct mlx5_ifc_wq_bits wq; 3875 }; 3876 3877 enum { 3878 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3879 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3880 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3881 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3882 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3883 }; 3884 3885 enum { 3886 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3887 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3888 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3889 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3890 }; 3891 3892 struct mlx5_ifc_scheduling_context_bits { 3893 u8 element_type[0x8]; 3894 u8 reserved_at_8[0x18]; 3895 3896 u8 element_attributes[0x20]; 3897 3898 u8 parent_element_id[0x20]; 3899 3900 u8 reserved_at_60[0x40]; 3901 3902 u8 bw_share[0x20]; 3903 3904 u8 max_average_bw[0x20]; 3905 3906 u8 reserved_at_e0[0x120]; 3907 }; 3908 3909 struct mlx5_ifc_rqtc_bits { 3910 u8 reserved_at_0[0xa0]; 3911 3912 u8 reserved_at_a0[0x5]; 3913 u8 list_q_type[0x3]; 3914 u8 reserved_at_a8[0x8]; 3915 u8 rqt_max_size[0x10]; 3916 3917 u8 rq_vhca_id_format[0x1]; 3918 u8 reserved_at_c1[0xf]; 3919 u8 rqt_actual_size[0x10]; 3920 3921 u8 reserved_at_e0[0x6a0]; 3922 3923 struct mlx5_ifc_rq_num_bits rq_num[]; 3924 }; 3925 3926 enum { 3927 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3928 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3929 }; 3930 3931 enum { 3932 MLX5_RQC_STATE_RST = 0x0, 3933 MLX5_RQC_STATE_RDY = 0x1, 3934 MLX5_RQC_STATE_ERR = 0x3, 3935 }; 3936 3937 enum { 3938 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3939 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3940 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3941 }; 3942 3943 enum { 3944 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3945 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3946 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3947 }; 3948 3949 struct mlx5_ifc_rqc_bits { 3950 u8 rlky[0x1]; 3951 u8 delay_drop_en[0x1]; 3952 u8 scatter_fcs[0x1]; 3953 u8 vsd[0x1]; 3954 u8 mem_rq_type[0x4]; 3955 u8 state[0x4]; 3956 u8 reserved_at_c[0x1]; 3957 u8 flush_in_error_en[0x1]; 3958 u8 hairpin[0x1]; 3959 u8 reserved_at_f[0xb]; 3960 u8 ts_format[0x2]; 3961 u8 reserved_at_1c[0x4]; 3962 3963 u8 reserved_at_20[0x8]; 3964 u8 user_index[0x18]; 3965 3966 u8 reserved_at_40[0x8]; 3967 u8 cqn[0x18]; 3968 3969 u8 counter_set_id[0x8]; 3970 u8 reserved_at_68[0x18]; 3971 3972 u8 reserved_at_80[0x8]; 3973 u8 rmpn[0x18]; 3974 3975 u8 reserved_at_a0[0x8]; 3976 u8 hairpin_peer_sq[0x18]; 3977 3978 u8 reserved_at_c0[0x10]; 3979 u8 hairpin_peer_vhca[0x10]; 3980 3981 u8 reserved_at_e0[0x46]; 3982 u8 shampo_no_match_alignment_granularity[0x2]; 3983 u8 reserved_at_128[0x6]; 3984 u8 shampo_match_criteria_type[0x2]; 3985 u8 reservation_timeout[0x10]; 3986 3987 u8 reserved_at_140[0x40]; 3988 3989 struct mlx5_ifc_wq_bits wq; 3990 }; 3991 3992 enum { 3993 MLX5_RMPC_STATE_RDY = 0x1, 3994 MLX5_RMPC_STATE_ERR = 0x3, 3995 }; 3996 3997 struct mlx5_ifc_rmpc_bits { 3998 u8 reserved_at_0[0x8]; 3999 u8 state[0x4]; 4000 u8 reserved_at_c[0x14]; 4001 4002 u8 basic_cyclic_rcv_wqe[0x1]; 4003 u8 reserved_at_21[0x1f]; 4004 4005 u8 reserved_at_40[0x140]; 4006 4007 struct mlx5_ifc_wq_bits wq; 4008 }; 4009 4010 enum { 4011 VHCA_ID_TYPE_HW = 0, 4012 VHCA_ID_TYPE_SW = 1, 4013 }; 4014 4015 struct mlx5_ifc_nic_vport_context_bits { 4016 u8 reserved_at_0[0x5]; 4017 u8 min_wqe_inline_mode[0x3]; 4018 u8 reserved_at_8[0x15]; 4019 u8 disable_mc_local_lb[0x1]; 4020 u8 disable_uc_local_lb[0x1]; 4021 u8 roce_en[0x1]; 4022 4023 u8 arm_change_event[0x1]; 4024 u8 reserved_at_21[0x1a]; 4025 u8 event_on_mtu[0x1]; 4026 u8 event_on_promisc_change[0x1]; 4027 u8 event_on_vlan_change[0x1]; 4028 u8 event_on_mc_address_change[0x1]; 4029 u8 event_on_uc_address_change[0x1]; 4030 4031 u8 vhca_id_type[0x1]; 4032 u8 reserved_at_41[0xb]; 4033 u8 affiliation_criteria[0x4]; 4034 u8 affiliated_vhca_id[0x10]; 4035 4036 u8 reserved_at_60[0xd0]; 4037 4038 u8 mtu[0x10]; 4039 4040 u8 system_image_guid[0x40]; 4041 u8 port_guid[0x40]; 4042 u8 node_guid[0x40]; 4043 4044 u8 reserved_at_200[0x140]; 4045 u8 qkey_violation_counter[0x10]; 4046 u8 reserved_at_350[0x430]; 4047 4048 u8 promisc_uc[0x1]; 4049 u8 promisc_mc[0x1]; 4050 u8 promisc_all[0x1]; 4051 u8 reserved_at_783[0x2]; 4052 u8 allowed_list_type[0x3]; 4053 u8 reserved_at_788[0xc]; 4054 u8 allowed_list_size[0xc]; 4055 4056 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4057 4058 u8 reserved_at_7e0[0x20]; 4059 4060 u8 current_uc_mac_address[][0x40]; 4061 }; 4062 4063 enum { 4064 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4065 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4066 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4067 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4068 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4069 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4070 }; 4071 4072 struct mlx5_ifc_mkc_bits { 4073 u8 reserved_at_0[0x1]; 4074 u8 free[0x1]; 4075 u8 reserved_at_2[0x1]; 4076 u8 access_mode_4_2[0x3]; 4077 u8 reserved_at_6[0x7]; 4078 u8 relaxed_ordering_write[0x1]; 4079 u8 reserved_at_e[0x1]; 4080 u8 small_fence_on_rdma_read_response[0x1]; 4081 u8 umr_en[0x1]; 4082 u8 a[0x1]; 4083 u8 rw[0x1]; 4084 u8 rr[0x1]; 4085 u8 lw[0x1]; 4086 u8 lr[0x1]; 4087 u8 access_mode_1_0[0x2]; 4088 u8 reserved_at_18[0x2]; 4089 u8 ma_translation_mode[0x2]; 4090 u8 reserved_at_1c[0x4]; 4091 4092 u8 qpn[0x18]; 4093 u8 mkey_7_0[0x8]; 4094 4095 u8 reserved_at_40[0x20]; 4096 4097 u8 length64[0x1]; 4098 u8 bsf_en[0x1]; 4099 u8 sync_umr[0x1]; 4100 u8 reserved_at_63[0x2]; 4101 u8 expected_sigerr_count[0x1]; 4102 u8 reserved_at_66[0x1]; 4103 u8 en_rinval[0x1]; 4104 u8 pd[0x18]; 4105 4106 u8 start_addr[0x40]; 4107 4108 u8 len[0x40]; 4109 4110 u8 bsf_octword_size[0x20]; 4111 4112 u8 reserved_at_120[0x80]; 4113 4114 u8 translations_octword_size[0x20]; 4115 4116 u8 reserved_at_1c0[0x19]; 4117 u8 relaxed_ordering_read[0x1]; 4118 u8 reserved_at_1d9[0x1]; 4119 u8 log_page_size[0x5]; 4120 4121 u8 reserved_at_1e0[0x20]; 4122 }; 4123 4124 struct mlx5_ifc_pkey_bits { 4125 u8 reserved_at_0[0x10]; 4126 u8 pkey[0x10]; 4127 }; 4128 4129 struct mlx5_ifc_array128_auto_bits { 4130 u8 array128_auto[16][0x8]; 4131 }; 4132 4133 struct mlx5_ifc_hca_vport_context_bits { 4134 u8 field_select[0x20]; 4135 4136 u8 reserved_at_20[0xe0]; 4137 4138 u8 sm_virt_aware[0x1]; 4139 u8 has_smi[0x1]; 4140 u8 has_raw[0x1]; 4141 u8 grh_required[0x1]; 4142 u8 reserved_at_104[0xc]; 4143 u8 port_physical_state[0x4]; 4144 u8 vport_state_policy[0x4]; 4145 u8 port_state[0x4]; 4146 u8 vport_state[0x4]; 4147 4148 u8 reserved_at_120[0x20]; 4149 4150 u8 system_image_guid[0x40]; 4151 4152 u8 port_guid[0x40]; 4153 4154 u8 node_guid[0x40]; 4155 4156 u8 cap_mask1[0x20]; 4157 4158 u8 cap_mask1_field_select[0x20]; 4159 4160 u8 cap_mask2[0x20]; 4161 4162 u8 cap_mask2_field_select[0x20]; 4163 4164 u8 reserved_at_280[0x80]; 4165 4166 u8 lid[0x10]; 4167 u8 reserved_at_310[0x4]; 4168 u8 init_type_reply[0x4]; 4169 u8 lmc[0x3]; 4170 u8 subnet_timeout[0x5]; 4171 4172 u8 sm_lid[0x10]; 4173 u8 sm_sl[0x4]; 4174 u8 reserved_at_334[0xc]; 4175 4176 u8 qkey_violation_counter[0x10]; 4177 u8 pkey_violation_counter[0x10]; 4178 4179 u8 reserved_at_360[0xca0]; 4180 }; 4181 4182 struct mlx5_ifc_esw_vport_context_bits { 4183 u8 fdb_to_vport_reg_c[0x1]; 4184 u8 reserved_at_1[0x2]; 4185 u8 vport_svlan_strip[0x1]; 4186 u8 vport_cvlan_strip[0x1]; 4187 u8 vport_svlan_insert[0x1]; 4188 u8 vport_cvlan_insert[0x2]; 4189 u8 fdb_to_vport_reg_c_id[0x8]; 4190 u8 reserved_at_10[0x10]; 4191 4192 u8 reserved_at_20[0x20]; 4193 4194 u8 svlan_cfi[0x1]; 4195 u8 svlan_pcp[0x3]; 4196 u8 svlan_id[0xc]; 4197 u8 cvlan_cfi[0x1]; 4198 u8 cvlan_pcp[0x3]; 4199 u8 cvlan_id[0xc]; 4200 4201 u8 reserved_at_60[0x720]; 4202 4203 u8 sw_steering_vport_icm_address_rx[0x40]; 4204 4205 u8 sw_steering_vport_icm_address_tx[0x40]; 4206 }; 4207 4208 enum { 4209 MLX5_EQC_STATUS_OK = 0x0, 4210 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4211 }; 4212 4213 enum { 4214 MLX5_EQC_ST_ARMED = 0x9, 4215 MLX5_EQC_ST_FIRED = 0xa, 4216 }; 4217 4218 struct mlx5_ifc_eqc_bits { 4219 u8 status[0x4]; 4220 u8 reserved_at_4[0x9]; 4221 u8 ec[0x1]; 4222 u8 oi[0x1]; 4223 u8 reserved_at_f[0x5]; 4224 u8 st[0x4]; 4225 u8 reserved_at_18[0x8]; 4226 4227 u8 reserved_at_20[0x20]; 4228 4229 u8 reserved_at_40[0x14]; 4230 u8 page_offset[0x6]; 4231 u8 reserved_at_5a[0x6]; 4232 4233 u8 reserved_at_60[0x3]; 4234 u8 log_eq_size[0x5]; 4235 u8 uar_page[0x18]; 4236 4237 u8 reserved_at_80[0x20]; 4238 4239 u8 reserved_at_a0[0x14]; 4240 u8 intr[0xc]; 4241 4242 u8 reserved_at_c0[0x3]; 4243 u8 log_page_size[0x5]; 4244 u8 reserved_at_c8[0x18]; 4245 4246 u8 reserved_at_e0[0x60]; 4247 4248 u8 reserved_at_140[0x8]; 4249 u8 consumer_counter[0x18]; 4250 4251 u8 reserved_at_160[0x8]; 4252 u8 producer_counter[0x18]; 4253 4254 u8 reserved_at_180[0x80]; 4255 }; 4256 4257 enum { 4258 MLX5_DCTC_STATE_ACTIVE = 0x0, 4259 MLX5_DCTC_STATE_DRAINING = 0x1, 4260 MLX5_DCTC_STATE_DRAINED = 0x2, 4261 }; 4262 4263 enum { 4264 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4265 MLX5_DCTC_CS_RES_NA = 0x1, 4266 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4267 }; 4268 4269 enum { 4270 MLX5_DCTC_MTU_256_BYTES = 0x1, 4271 MLX5_DCTC_MTU_512_BYTES = 0x2, 4272 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4273 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4274 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4275 }; 4276 4277 struct mlx5_ifc_dctc_bits { 4278 u8 reserved_at_0[0x4]; 4279 u8 state[0x4]; 4280 u8 reserved_at_8[0x18]; 4281 4282 u8 reserved_at_20[0x8]; 4283 u8 user_index[0x18]; 4284 4285 u8 reserved_at_40[0x8]; 4286 u8 cqn[0x18]; 4287 4288 u8 counter_set_id[0x8]; 4289 u8 atomic_mode[0x4]; 4290 u8 rre[0x1]; 4291 u8 rwe[0x1]; 4292 u8 rae[0x1]; 4293 u8 atomic_like_write_en[0x1]; 4294 u8 latency_sensitive[0x1]; 4295 u8 rlky[0x1]; 4296 u8 free_ar[0x1]; 4297 u8 reserved_at_73[0xd]; 4298 4299 u8 reserved_at_80[0x8]; 4300 u8 cs_res[0x8]; 4301 u8 reserved_at_90[0x3]; 4302 u8 min_rnr_nak[0x5]; 4303 u8 reserved_at_98[0x8]; 4304 4305 u8 reserved_at_a0[0x8]; 4306 u8 srqn_xrqn[0x18]; 4307 4308 u8 reserved_at_c0[0x8]; 4309 u8 pd[0x18]; 4310 4311 u8 tclass[0x8]; 4312 u8 reserved_at_e8[0x4]; 4313 u8 flow_label[0x14]; 4314 4315 u8 dc_access_key[0x40]; 4316 4317 u8 reserved_at_140[0x5]; 4318 u8 mtu[0x3]; 4319 u8 port[0x8]; 4320 u8 pkey_index[0x10]; 4321 4322 u8 reserved_at_160[0x8]; 4323 u8 my_addr_index[0x8]; 4324 u8 reserved_at_170[0x8]; 4325 u8 hop_limit[0x8]; 4326 4327 u8 dc_access_key_violation_count[0x20]; 4328 4329 u8 reserved_at_1a0[0x14]; 4330 u8 dei_cfi[0x1]; 4331 u8 eth_prio[0x3]; 4332 u8 ecn[0x2]; 4333 u8 dscp[0x6]; 4334 4335 u8 reserved_at_1c0[0x20]; 4336 u8 ece[0x20]; 4337 }; 4338 4339 enum { 4340 MLX5_CQC_STATUS_OK = 0x0, 4341 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4342 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4343 }; 4344 4345 enum { 4346 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4347 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4348 }; 4349 4350 enum { 4351 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4352 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4353 MLX5_CQC_ST_FIRED = 0xa, 4354 }; 4355 4356 enum { 4357 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4358 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4359 MLX5_CQ_PERIOD_NUM_MODES 4360 }; 4361 4362 struct mlx5_ifc_cqc_bits { 4363 u8 status[0x4]; 4364 u8 reserved_at_4[0x2]; 4365 u8 dbr_umem_valid[0x1]; 4366 u8 apu_cq[0x1]; 4367 u8 cqe_sz[0x3]; 4368 u8 cc[0x1]; 4369 u8 reserved_at_c[0x1]; 4370 u8 scqe_break_moderation_en[0x1]; 4371 u8 oi[0x1]; 4372 u8 cq_period_mode[0x2]; 4373 u8 cqe_comp_en[0x1]; 4374 u8 mini_cqe_res_format[0x2]; 4375 u8 st[0x4]; 4376 u8 reserved_at_18[0x6]; 4377 u8 cqe_compression_layout[0x2]; 4378 4379 u8 reserved_at_20[0x20]; 4380 4381 u8 reserved_at_40[0x14]; 4382 u8 page_offset[0x6]; 4383 u8 reserved_at_5a[0x6]; 4384 4385 u8 reserved_at_60[0x3]; 4386 u8 log_cq_size[0x5]; 4387 u8 uar_page[0x18]; 4388 4389 u8 reserved_at_80[0x4]; 4390 u8 cq_period[0xc]; 4391 u8 cq_max_count[0x10]; 4392 4393 u8 c_eqn_or_apu_element[0x20]; 4394 4395 u8 reserved_at_c0[0x3]; 4396 u8 log_page_size[0x5]; 4397 u8 reserved_at_c8[0x18]; 4398 4399 u8 reserved_at_e0[0x20]; 4400 4401 u8 reserved_at_100[0x8]; 4402 u8 last_notified_index[0x18]; 4403 4404 u8 reserved_at_120[0x8]; 4405 u8 last_solicit_index[0x18]; 4406 4407 u8 reserved_at_140[0x8]; 4408 u8 consumer_counter[0x18]; 4409 4410 u8 reserved_at_160[0x8]; 4411 u8 producer_counter[0x18]; 4412 4413 u8 reserved_at_180[0x40]; 4414 4415 u8 dbr_addr[0x40]; 4416 }; 4417 4418 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4419 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4420 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4421 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4422 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4423 u8 reserved_at_0[0x800]; 4424 }; 4425 4426 struct mlx5_ifc_query_adapter_param_block_bits { 4427 u8 reserved_at_0[0xc0]; 4428 4429 u8 reserved_at_c0[0x8]; 4430 u8 ieee_vendor_id[0x18]; 4431 4432 u8 reserved_at_e0[0x10]; 4433 u8 vsd_vendor_id[0x10]; 4434 4435 u8 vsd[208][0x8]; 4436 4437 u8 vsd_contd_psid[16][0x8]; 4438 }; 4439 4440 enum { 4441 MLX5_XRQC_STATE_GOOD = 0x0, 4442 MLX5_XRQC_STATE_ERROR = 0x1, 4443 }; 4444 4445 enum { 4446 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4447 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4448 }; 4449 4450 enum { 4451 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4452 }; 4453 4454 struct mlx5_ifc_tag_matching_topology_context_bits { 4455 u8 log_matching_list_sz[0x4]; 4456 u8 reserved_at_4[0xc]; 4457 u8 append_next_index[0x10]; 4458 4459 u8 sw_phase_cnt[0x10]; 4460 u8 hw_phase_cnt[0x10]; 4461 4462 u8 reserved_at_40[0x40]; 4463 }; 4464 4465 struct mlx5_ifc_xrqc_bits { 4466 u8 state[0x4]; 4467 u8 rlkey[0x1]; 4468 u8 reserved_at_5[0xf]; 4469 u8 topology[0x4]; 4470 u8 reserved_at_18[0x4]; 4471 u8 offload[0x4]; 4472 4473 u8 reserved_at_20[0x8]; 4474 u8 user_index[0x18]; 4475 4476 u8 reserved_at_40[0x8]; 4477 u8 cqn[0x18]; 4478 4479 u8 reserved_at_60[0xa0]; 4480 4481 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4482 4483 u8 reserved_at_180[0x280]; 4484 4485 struct mlx5_ifc_wq_bits wq; 4486 }; 4487 4488 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4489 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4490 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4491 u8 reserved_at_0[0x20]; 4492 }; 4493 4494 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4495 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4496 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4497 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4498 u8 reserved_at_0[0x20]; 4499 }; 4500 4501 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4502 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4503 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4504 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4505 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4506 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4507 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4508 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4509 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4510 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4511 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4512 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4513 u8 reserved_at_0[0x7c0]; 4514 }; 4515 4516 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4517 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4518 u8 reserved_at_0[0x7c0]; 4519 }; 4520 4521 union mlx5_ifc_event_auto_bits { 4522 struct mlx5_ifc_comp_event_bits comp_event; 4523 struct mlx5_ifc_dct_events_bits dct_events; 4524 struct mlx5_ifc_qp_events_bits qp_events; 4525 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4526 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4527 struct mlx5_ifc_cq_error_bits cq_error; 4528 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4529 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4530 struct mlx5_ifc_gpio_event_bits gpio_event; 4531 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4532 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4533 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4534 u8 reserved_at_0[0xe0]; 4535 }; 4536 4537 struct mlx5_ifc_health_buffer_bits { 4538 u8 reserved_at_0[0x100]; 4539 4540 u8 assert_existptr[0x20]; 4541 4542 u8 assert_callra[0x20]; 4543 4544 u8 reserved_at_140[0x20]; 4545 4546 u8 time[0x20]; 4547 4548 u8 fw_version[0x20]; 4549 4550 u8 hw_id[0x20]; 4551 4552 u8 rfr[0x1]; 4553 u8 reserved_at_1c1[0x3]; 4554 u8 valid[0x1]; 4555 u8 severity[0x3]; 4556 u8 reserved_at_1c8[0x18]; 4557 4558 u8 irisc_index[0x8]; 4559 u8 synd[0x8]; 4560 u8 ext_synd[0x10]; 4561 }; 4562 4563 struct mlx5_ifc_register_loopback_control_bits { 4564 u8 no_lb[0x1]; 4565 u8 reserved_at_1[0x7]; 4566 u8 port[0x8]; 4567 u8 reserved_at_10[0x10]; 4568 4569 u8 reserved_at_20[0x60]; 4570 }; 4571 4572 struct mlx5_ifc_vport_tc_element_bits { 4573 u8 traffic_class[0x4]; 4574 u8 reserved_at_4[0xc]; 4575 u8 vport_number[0x10]; 4576 }; 4577 4578 struct mlx5_ifc_vport_element_bits { 4579 u8 reserved_at_0[0x10]; 4580 u8 vport_number[0x10]; 4581 }; 4582 4583 enum { 4584 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4585 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4586 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4587 }; 4588 4589 struct mlx5_ifc_tsar_element_bits { 4590 u8 reserved_at_0[0x8]; 4591 u8 tsar_type[0x8]; 4592 u8 reserved_at_10[0x10]; 4593 }; 4594 4595 enum { 4596 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4597 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4598 }; 4599 4600 struct mlx5_ifc_teardown_hca_out_bits { 4601 u8 status[0x8]; 4602 u8 reserved_at_8[0x18]; 4603 4604 u8 syndrome[0x20]; 4605 4606 u8 reserved_at_40[0x3f]; 4607 4608 u8 state[0x1]; 4609 }; 4610 4611 enum { 4612 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4613 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4614 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4615 }; 4616 4617 struct mlx5_ifc_teardown_hca_in_bits { 4618 u8 opcode[0x10]; 4619 u8 reserved_at_10[0x10]; 4620 4621 u8 reserved_at_20[0x10]; 4622 u8 op_mod[0x10]; 4623 4624 u8 reserved_at_40[0x10]; 4625 u8 profile[0x10]; 4626 4627 u8 reserved_at_60[0x20]; 4628 }; 4629 4630 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4631 u8 status[0x8]; 4632 u8 reserved_at_8[0x18]; 4633 4634 u8 syndrome[0x20]; 4635 4636 u8 reserved_at_40[0x40]; 4637 }; 4638 4639 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4640 u8 opcode[0x10]; 4641 u8 uid[0x10]; 4642 4643 u8 reserved_at_20[0x10]; 4644 u8 op_mod[0x10]; 4645 4646 u8 reserved_at_40[0x8]; 4647 u8 qpn[0x18]; 4648 4649 u8 reserved_at_60[0x20]; 4650 4651 u8 opt_param_mask[0x20]; 4652 4653 u8 reserved_at_a0[0x20]; 4654 4655 struct mlx5_ifc_qpc_bits qpc; 4656 4657 u8 reserved_at_800[0x80]; 4658 }; 4659 4660 struct mlx5_ifc_sqd2rts_qp_out_bits { 4661 u8 status[0x8]; 4662 u8 reserved_at_8[0x18]; 4663 4664 u8 syndrome[0x20]; 4665 4666 u8 reserved_at_40[0x40]; 4667 }; 4668 4669 struct mlx5_ifc_sqd2rts_qp_in_bits { 4670 u8 opcode[0x10]; 4671 u8 uid[0x10]; 4672 4673 u8 reserved_at_20[0x10]; 4674 u8 op_mod[0x10]; 4675 4676 u8 reserved_at_40[0x8]; 4677 u8 qpn[0x18]; 4678 4679 u8 reserved_at_60[0x20]; 4680 4681 u8 opt_param_mask[0x20]; 4682 4683 u8 reserved_at_a0[0x20]; 4684 4685 struct mlx5_ifc_qpc_bits qpc; 4686 4687 u8 reserved_at_800[0x80]; 4688 }; 4689 4690 struct mlx5_ifc_set_roce_address_out_bits { 4691 u8 status[0x8]; 4692 u8 reserved_at_8[0x18]; 4693 4694 u8 syndrome[0x20]; 4695 4696 u8 reserved_at_40[0x40]; 4697 }; 4698 4699 struct mlx5_ifc_set_roce_address_in_bits { 4700 u8 opcode[0x10]; 4701 u8 reserved_at_10[0x10]; 4702 4703 u8 reserved_at_20[0x10]; 4704 u8 op_mod[0x10]; 4705 4706 u8 roce_address_index[0x10]; 4707 u8 reserved_at_50[0xc]; 4708 u8 vhca_port_num[0x4]; 4709 4710 u8 reserved_at_60[0x20]; 4711 4712 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4713 }; 4714 4715 struct mlx5_ifc_set_mad_demux_out_bits { 4716 u8 status[0x8]; 4717 u8 reserved_at_8[0x18]; 4718 4719 u8 syndrome[0x20]; 4720 4721 u8 reserved_at_40[0x40]; 4722 }; 4723 4724 enum { 4725 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4726 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4727 }; 4728 4729 struct mlx5_ifc_set_mad_demux_in_bits { 4730 u8 opcode[0x10]; 4731 u8 reserved_at_10[0x10]; 4732 4733 u8 reserved_at_20[0x10]; 4734 u8 op_mod[0x10]; 4735 4736 u8 reserved_at_40[0x20]; 4737 4738 u8 reserved_at_60[0x6]; 4739 u8 demux_mode[0x2]; 4740 u8 reserved_at_68[0x18]; 4741 }; 4742 4743 struct mlx5_ifc_set_l2_table_entry_out_bits { 4744 u8 status[0x8]; 4745 u8 reserved_at_8[0x18]; 4746 4747 u8 syndrome[0x20]; 4748 4749 u8 reserved_at_40[0x40]; 4750 }; 4751 4752 struct mlx5_ifc_set_l2_table_entry_in_bits { 4753 u8 opcode[0x10]; 4754 u8 reserved_at_10[0x10]; 4755 4756 u8 reserved_at_20[0x10]; 4757 u8 op_mod[0x10]; 4758 4759 u8 reserved_at_40[0x60]; 4760 4761 u8 reserved_at_a0[0x8]; 4762 u8 table_index[0x18]; 4763 4764 u8 reserved_at_c0[0x20]; 4765 4766 u8 reserved_at_e0[0x13]; 4767 u8 vlan_valid[0x1]; 4768 u8 vlan[0xc]; 4769 4770 struct mlx5_ifc_mac_address_layout_bits mac_address; 4771 4772 u8 reserved_at_140[0xc0]; 4773 }; 4774 4775 struct mlx5_ifc_set_issi_out_bits { 4776 u8 status[0x8]; 4777 u8 reserved_at_8[0x18]; 4778 4779 u8 syndrome[0x20]; 4780 4781 u8 reserved_at_40[0x40]; 4782 }; 4783 4784 struct mlx5_ifc_set_issi_in_bits { 4785 u8 opcode[0x10]; 4786 u8 reserved_at_10[0x10]; 4787 4788 u8 reserved_at_20[0x10]; 4789 u8 op_mod[0x10]; 4790 4791 u8 reserved_at_40[0x10]; 4792 u8 current_issi[0x10]; 4793 4794 u8 reserved_at_60[0x20]; 4795 }; 4796 4797 struct mlx5_ifc_set_hca_cap_out_bits { 4798 u8 status[0x8]; 4799 u8 reserved_at_8[0x18]; 4800 4801 u8 syndrome[0x20]; 4802 4803 u8 reserved_at_40[0x40]; 4804 }; 4805 4806 struct mlx5_ifc_set_hca_cap_in_bits { 4807 u8 opcode[0x10]; 4808 u8 reserved_at_10[0x10]; 4809 4810 u8 reserved_at_20[0x10]; 4811 u8 op_mod[0x10]; 4812 4813 u8 other_function[0x1]; 4814 u8 ec_vf_function[0x1]; 4815 u8 reserved_at_42[0xe]; 4816 u8 function_id[0x10]; 4817 4818 u8 reserved_at_60[0x20]; 4819 4820 union mlx5_ifc_hca_cap_union_bits capability; 4821 }; 4822 4823 enum { 4824 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4825 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4826 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4827 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4828 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4829 }; 4830 4831 struct mlx5_ifc_set_fte_out_bits { 4832 u8 status[0x8]; 4833 u8 reserved_at_8[0x18]; 4834 4835 u8 syndrome[0x20]; 4836 4837 u8 reserved_at_40[0x40]; 4838 }; 4839 4840 struct mlx5_ifc_set_fte_in_bits { 4841 u8 opcode[0x10]; 4842 u8 reserved_at_10[0x10]; 4843 4844 u8 reserved_at_20[0x10]; 4845 u8 op_mod[0x10]; 4846 4847 u8 other_vport[0x1]; 4848 u8 reserved_at_41[0xf]; 4849 u8 vport_number[0x10]; 4850 4851 u8 reserved_at_60[0x20]; 4852 4853 u8 table_type[0x8]; 4854 u8 reserved_at_88[0x18]; 4855 4856 u8 reserved_at_a0[0x8]; 4857 u8 table_id[0x18]; 4858 4859 u8 ignore_flow_level[0x1]; 4860 u8 reserved_at_c1[0x17]; 4861 u8 modify_enable_mask[0x8]; 4862 4863 u8 reserved_at_e0[0x20]; 4864 4865 u8 flow_index[0x20]; 4866 4867 u8 reserved_at_120[0xe0]; 4868 4869 struct mlx5_ifc_flow_context_bits flow_context; 4870 }; 4871 4872 struct mlx5_ifc_rts2rts_qp_out_bits { 4873 u8 status[0x8]; 4874 u8 reserved_at_8[0x18]; 4875 4876 u8 syndrome[0x20]; 4877 4878 u8 reserved_at_40[0x20]; 4879 u8 ece[0x20]; 4880 }; 4881 4882 struct mlx5_ifc_rts2rts_qp_in_bits { 4883 u8 opcode[0x10]; 4884 u8 uid[0x10]; 4885 4886 u8 reserved_at_20[0x10]; 4887 u8 op_mod[0x10]; 4888 4889 u8 reserved_at_40[0x8]; 4890 u8 qpn[0x18]; 4891 4892 u8 reserved_at_60[0x20]; 4893 4894 u8 opt_param_mask[0x20]; 4895 4896 u8 ece[0x20]; 4897 4898 struct mlx5_ifc_qpc_bits qpc; 4899 4900 u8 reserved_at_800[0x80]; 4901 }; 4902 4903 struct mlx5_ifc_rtr2rts_qp_out_bits { 4904 u8 status[0x8]; 4905 u8 reserved_at_8[0x18]; 4906 4907 u8 syndrome[0x20]; 4908 4909 u8 reserved_at_40[0x20]; 4910 u8 ece[0x20]; 4911 }; 4912 4913 struct mlx5_ifc_rtr2rts_qp_in_bits { 4914 u8 opcode[0x10]; 4915 u8 uid[0x10]; 4916 4917 u8 reserved_at_20[0x10]; 4918 u8 op_mod[0x10]; 4919 4920 u8 reserved_at_40[0x8]; 4921 u8 qpn[0x18]; 4922 4923 u8 reserved_at_60[0x20]; 4924 4925 u8 opt_param_mask[0x20]; 4926 4927 u8 ece[0x20]; 4928 4929 struct mlx5_ifc_qpc_bits qpc; 4930 4931 u8 reserved_at_800[0x80]; 4932 }; 4933 4934 struct mlx5_ifc_rst2init_qp_out_bits { 4935 u8 status[0x8]; 4936 u8 reserved_at_8[0x18]; 4937 4938 u8 syndrome[0x20]; 4939 4940 u8 reserved_at_40[0x20]; 4941 u8 ece[0x20]; 4942 }; 4943 4944 struct mlx5_ifc_rst2init_qp_in_bits { 4945 u8 opcode[0x10]; 4946 u8 uid[0x10]; 4947 4948 u8 reserved_at_20[0x10]; 4949 u8 op_mod[0x10]; 4950 4951 u8 reserved_at_40[0x8]; 4952 u8 qpn[0x18]; 4953 4954 u8 reserved_at_60[0x20]; 4955 4956 u8 opt_param_mask[0x20]; 4957 4958 u8 ece[0x20]; 4959 4960 struct mlx5_ifc_qpc_bits qpc; 4961 4962 u8 reserved_at_800[0x80]; 4963 }; 4964 4965 struct mlx5_ifc_query_xrq_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0x40]; 4972 4973 struct mlx5_ifc_xrqc_bits xrq_context; 4974 }; 4975 4976 struct mlx5_ifc_query_xrq_in_bits { 4977 u8 opcode[0x10]; 4978 u8 reserved_at_10[0x10]; 4979 4980 u8 reserved_at_20[0x10]; 4981 u8 op_mod[0x10]; 4982 4983 u8 reserved_at_40[0x8]; 4984 u8 xrqn[0x18]; 4985 4986 u8 reserved_at_60[0x20]; 4987 }; 4988 4989 struct mlx5_ifc_query_xrc_srq_out_bits { 4990 u8 status[0x8]; 4991 u8 reserved_at_8[0x18]; 4992 4993 u8 syndrome[0x20]; 4994 4995 u8 reserved_at_40[0x40]; 4996 4997 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4998 4999 u8 reserved_at_280[0x600]; 5000 5001 u8 pas[][0x40]; 5002 }; 5003 5004 struct mlx5_ifc_query_xrc_srq_in_bits { 5005 u8 opcode[0x10]; 5006 u8 reserved_at_10[0x10]; 5007 5008 u8 reserved_at_20[0x10]; 5009 u8 op_mod[0x10]; 5010 5011 u8 reserved_at_40[0x8]; 5012 u8 xrc_srqn[0x18]; 5013 5014 u8 reserved_at_60[0x20]; 5015 }; 5016 5017 enum { 5018 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5019 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5020 }; 5021 5022 struct mlx5_ifc_query_vport_state_out_bits { 5023 u8 status[0x8]; 5024 u8 reserved_at_8[0x18]; 5025 5026 u8 syndrome[0x20]; 5027 5028 u8 reserved_at_40[0x20]; 5029 5030 u8 reserved_at_60[0x18]; 5031 u8 admin_state[0x4]; 5032 u8 state[0x4]; 5033 }; 5034 5035 enum { 5036 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5037 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5038 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5039 }; 5040 5041 struct mlx5_ifc_arm_monitor_counter_in_bits { 5042 u8 opcode[0x10]; 5043 u8 uid[0x10]; 5044 5045 u8 reserved_at_20[0x10]; 5046 u8 op_mod[0x10]; 5047 5048 u8 reserved_at_40[0x20]; 5049 5050 u8 reserved_at_60[0x20]; 5051 }; 5052 5053 struct mlx5_ifc_arm_monitor_counter_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_at_8[0x18]; 5056 5057 u8 syndrome[0x20]; 5058 5059 u8 reserved_at_40[0x40]; 5060 }; 5061 5062 enum { 5063 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5064 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5065 }; 5066 5067 enum mlx5_monitor_counter_ppcnt { 5068 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5069 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5070 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5071 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5072 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5073 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5074 }; 5075 5076 enum { 5077 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5078 }; 5079 5080 struct mlx5_ifc_monitor_counter_output_bits { 5081 u8 reserved_at_0[0x4]; 5082 u8 type[0x4]; 5083 u8 reserved_at_8[0x8]; 5084 u8 counter[0x10]; 5085 5086 u8 counter_group_id[0x20]; 5087 }; 5088 5089 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5090 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5091 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5092 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5093 5094 struct mlx5_ifc_set_monitor_counter_in_bits { 5095 u8 opcode[0x10]; 5096 u8 uid[0x10]; 5097 5098 u8 reserved_at_20[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 reserved_at_40[0x10]; 5102 u8 num_of_counters[0x10]; 5103 5104 u8 reserved_at_60[0x20]; 5105 5106 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5107 }; 5108 5109 struct mlx5_ifc_set_monitor_counter_out_bits { 5110 u8 status[0x8]; 5111 u8 reserved_at_8[0x18]; 5112 5113 u8 syndrome[0x20]; 5114 5115 u8 reserved_at_40[0x40]; 5116 }; 5117 5118 struct mlx5_ifc_query_vport_state_in_bits { 5119 u8 opcode[0x10]; 5120 u8 reserved_at_10[0x10]; 5121 5122 u8 reserved_at_20[0x10]; 5123 u8 op_mod[0x10]; 5124 5125 u8 other_vport[0x1]; 5126 u8 reserved_at_41[0xf]; 5127 u8 vport_number[0x10]; 5128 5129 u8 reserved_at_60[0x20]; 5130 }; 5131 5132 struct mlx5_ifc_query_vnic_env_out_bits { 5133 u8 status[0x8]; 5134 u8 reserved_at_8[0x18]; 5135 5136 u8 syndrome[0x20]; 5137 5138 u8 reserved_at_40[0x40]; 5139 5140 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5141 }; 5142 5143 enum { 5144 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5145 }; 5146 5147 struct mlx5_ifc_query_vnic_env_in_bits { 5148 u8 opcode[0x10]; 5149 u8 reserved_at_10[0x10]; 5150 5151 u8 reserved_at_20[0x10]; 5152 u8 op_mod[0x10]; 5153 5154 u8 other_vport[0x1]; 5155 u8 reserved_at_41[0xf]; 5156 u8 vport_number[0x10]; 5157 5158 u8 reserved_at_60[0x20]; 5159 }; 5160 5161 struct mlx5_ifc_query_vport_counter_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_at_8[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_at_40[0x40]; 5168 5169 struct mlx5_ifc_traffic_counter_bits received_errors; 5170 5171 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5172 5173 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5174 5175 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5176 5177 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5178 5179 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5180 5181 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5182 5183 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5184 5185 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5186 5187 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5188 5189 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5190 5191 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5192 5193 struct mlx5_ifc_traffic_counter_bits local_loopback; 5194 5195 u8 reserved_at_700[0x980]; 5196 }; 5197 5198 enum { 5199 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5200 }; 5201 5202 struct mlx5_ifc_query_vport_counter_in_bits { 5203 u8 opcode[0x10]; 5204 u8 reserved_at_10[0x10]; 5205 5206 u8 reserved_at_20[0x10]; 5207 u8 op_mod[0x10]; 5208 5209 u8 other_vport[0x1]; 5210 u8 reserved_at_41[0xb]; 5211 u8 port_num[0x4]; 5212 u8 vport_number[0x10]; 5213 5214 u8 reserved_at_60[0x60]; 5215 5216 u8 clear[0x1]; 5217 u8 reserved_at_c1[0x1f]; 5218 5219 u8 reserved_at_e0[0x20]; 5220 }; 5221 5222 struct mlx5_ifc_query_tis_out_bits { 5223 u8 status[0x8]; 5224 u8 reserved_at_8[0x18]; 5225 5226 u8 syndrome[0x20]; 5227 5228 u8 reserved_at_40[0x40]; 5229 5230 struct mlx5_ifc_tisc_bits tis_context; 5231 }; 5232 5233 struct mlx5_ifc_query_tis_in_bits { 5234 u8 opcode[0x10]; 5235 u8 reserved_at_10[0x10]; 5236 5237 u8 reserved_at_20[0x10]; 5238 u8 op_mod[0x10]; 5239 5240 u8 reserved_at_40[0x8]; 5241 u8 tisn[0x18]; 5242 5243 u8 reserved_at_60[0x20]; 5244 }; 5245 5246 struct mlx5_ifc_query_tir_out_bits { 5247 u8 status[0x8]; 5248 u8 reserved_at_8[0x18]; 5249 5250 u8 syndrome[0x20]; 5251 5252 u8 reserved_at_40[0xc0]; 5253 5254 struct mlx5_ifc_tirc_bits tir_context; 5255 }; 5256 5257 struct mlx5_ifc_query_tir_in_bits { 5258 u8 opcode[0x10]; 5259 u8 reserved_at_10[0x10]; 5260 5261 u8 reserved_at_20[0x10]; 5262 u8 op_mod[0x10]; 5263 5264 u8 reserved_at_40[0x8]; 5265 u8 tirn[0x18]; 5266 5267 u8 reserved_at_60[0x20]; 5268 }; 5269 5270 struct mlx5_ifc_query_srq_out_bits { 5271 u8 status[0x8]; 5272 u8 reserved_at_8[0x18]; 5273 5274 u8 syndrome[0x20]; 5275 5276 u8 reserved_at_40[0x40]; 5277 5278 struct mlx5_ifc_srqc_bits srq_context_entry; 5279 5280 u8 reserved_at_280[0x600]; 5281 5282 u8 pas[][0x40]; 5283 }; 5284 5285 struct mlx5_ifc_query_srq_in_bits { 5286 u8 opcode[0x10]; 5287 u8 reserved_at_10[0x10]; 5288 5289 u8 reserved_at_20[0x10]; 5290 u8 op_mod[0x10]; 5291 5292 u8 reserved_at_40[0x8]; 5293 u8 srqn[0x18]; 5294 5295 u8 reserved_at_60[0x20]; 5296 }; 5297 5298 struct mlx5_ifc_query_sq_out_bits { 5299 u8 status[0x8]; 5300 u8 reserved_at_8[0x18]; 5301 5302 u8 syndrome[0x20]; 5303 5304 u8 reserved_at_40[0xc0]; 5305 5306 struct mlx5_ifc_sqc_bits sq_context; 5307 }; 5308 5309 struct mlx5_ifc_query_sq_in_bits { 5310 u8 opcode[0x10]; 5311 u8 reserved_at_10[0x10]; 5312 5313 u8 reserved_at_20[0x10]; 5314 u8 op_mod[0x10]; 5315 5316 u8 reserved_at_40[0x8]; 5317 u8 sqn[0x18]; 5318 5319 u8 reserved_at_60[0x20]; 5320 }; 5321 5322 struct mlx5_ifc_query_special_contexts_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 dump_fill_mkey[0x20]; 5329 5330 u8 resd_lkey[0x20]; 5331 5332 u8 null_mkey[0x20]; 5333 5334 u8 terminate_scatter_list_mkey[0x20]; 5335 5336 u8 repeated_mkey[0x20]; 5337 5338 u8 reserved_at_a0[0x20]; 5339 }; 5340 5341 struct mlx5_ifc_query_special_contexts_in_bits { 5342 u8 opcode[0x10]; 5343 u8 reserved_at_10[0x10]; 5344 5345 u8 reserved_at_20[0x10]; 5346 u8 op_mod[0x10]; 5347 5348 u8 reserved_at_40[0x40]; 5349 }; 5350 5351 struct mlx5_ifc_query_scheduling_element_out_bits { 5352 u8 opcode[0x10]; 5353 u8 reserved_at_10[0x10]; 5354 5355 u8 reserved_at_20[0x10]; 5356 u8 op_mod[0x10]; 5357 5358 u8 reserved_at_40[0xc0]; 5359 5360 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5361 5362 u8 reserved_at_300[0x100]; 5363 }; 5364 5365 enum { 5366 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5367 SCHEDULING_HIERARCHY_NIC = 0x3, 5368 }; 5369 5370 struct mlx5_ifc_query_scheduling_element_in_bits { 5371 u8 opcode[0x10]; 5372 u8 reserved_at_10[0x10]; 5373 5374 u8 reserved_at_20[0x10]; 5375 u8 op_mod[0x10]; 5376 5377 u8 scheduling_hierarchy[0x8]; 5378 u8 reserved_at_48[0x18]; 5379 5380 u8 scheduling_element_id[0x20]; 5381 5382 u8 reserved_at_80[0x180]; 5383 }; 5384 5385 struct mlx5_ifc_query_rqt_out_bits { 5386 u8 status[0x8]; 5387 u8 reserved_at_8[0x18]; 5388 5389 u8 syndrome[0x20]; 5390 5391 u8 reserved_at_40[0xc0]; 5392 5393 struct mlx5_ifc_rqtc_bits rqt_context; 5394 }; 5395 5396 struct mlx5_ifc_query_rqt_in_bits { 5397 u8 opcode[0x10]; 5398 u8 reserved_at_10[0x10]; 5399 5400 u8 reserved_at_20[0x10]; 5401 u8 op_mod[0x10]; 5402 5403 u8 reserved_at_40[0x8]; 5404 u8 rqtn[0x18]; 5405 5406 u8 reserved_at_60[0x20]; 5407 }; 5408 5409 struct mlx5_ifc_query_rq_out_bits { 5410 u8 status[0x8]; 5411 u8 reserved_at_8[0x18]; 5412 5413 u8 syndrome[0x20]; 5414 5415 u8 reserved_at_40[0xc0]; 5416 5417 struct mlx5_ifc_rqc_bits rq_context; 5418 }; 5419 5420 struct mlx5_ifc_query_rq_in_bits { 5421 u8 opcode[0x10]; 5422 u8 reserved_at_10[0x10]; 5423 5424 u8 reserved_at_20[0x10]; 5425 u8 op_mod[0x10]; 5426 5427 u8 reserved_at_40[0x8]; 5428 u8 rqn[0x18]; 5429 5430 u8 reserved_at_60[0x20]; 5431 }; 5432 5433 struct mlx5_ifc_query_roce_address_out_bits { 5434 u8 status[0x8]; 5435 u8 reserved_at_8[0x18]; 5436 5437 u8 syndrome[0x20]; 5438 5439 u8 reserved_at_40[0x40]; 5440 5441 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5442 }; 5443 5444 struct mlx5_ifc_query_roce_address_in_bits { 5445 u8 opcode[0x10]; 5446 u8 reserved_at_10[0x10]; 5447 5448 u8 reserved_at_20[0x10]; 5449 u8 op_mod[0x10]; 5450 5451 u8 roce_address_index[0x10]; 5452 u8 reserved_at_50[0xc]; 5453 u8 vhca_port_num[0x4]; 5454 5455 u8 reserved_at_60[0x20]; 5456 }; 5457 5458 struct mlx5_ifc_query_rmp_out_bits { 5459 u8 status[0x8]; 5460 u8 reserved_at_8[0x18]; 5461 5462 u8 syndrome[0x20]; 5463 5464 u8 reserved_at_40[0xc0]; 5465 5466 struct mlx5_ifc_rmpc_bits rmp_context; 5467 }; 5468 5469 struct mlx5_ifc_query_rmp_in_bits { 5470 u8 opcode[0x10]; 5471 u8 reserved_at_10[0x10]; 5472 5473 u8 reserved_at_20[0x10]; 5474 u8 op_mod[0x10]; 5475 5476 u8 reserved_at_40[0x8]; 5477 u8 rmpn[0x18]; 5478 5479 u8 reserved_at_60[0x20]; 5480 }; 5481 5482 struct mlx5_ifc_cqe_error_syndrome_bits { 5483 u8 hw_error_syndrome[0x8]; 5484 u8 hw_syndrome_type[0x4]; 5485 u8 reserved_at_c[0x4]; 5486 u8 vendor_error_syndrome[0x8]; 5487 u8 syndrome[0x8]; 5488 }; 5489 5490 struct mlx5_ifc_qp_context_extension_bits { 5491 u8 reserved_at_0[0x60]; 5492 5493 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5494 5495 u8 reserved_at_80[0x580]; 5496 }; 5497 5498 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5499 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5500 5501 u8 pas[0][0x40]; 5502 }; 5503 5504 struct mlx5_ifc_qp_pas_list_in_bits { 5505 struct mlx5_ifc_cmd_pas_bits pas[0]; 5506 }; 5507 5508 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5509 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5510 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5511 }; 5512 5513 struct mlx5_ifc_query_qp_out_bits { 5514 u8 status[0x8]; 5515 u8 reserved_at_8[0x18]; 5516 5517 u8 syndrome[0x20]; 5518 5519 u8 reserved_at_40[0x40]; 5520 5521 u8 opt_param_mask[0x20]; 5522 5523 u8 ece[0x20]; 5524 5525 struct mlx5_ifc_qpc_bits qpc; 5526 5527 u8 reserved_at_800[0x80]; 5528 5529 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5530 }; 5531 5532 struct mlx5_ifc_query_qp_in_bits { 5533 u8 opcode[0x10]; 5534 u8 reserved_at_10[0x10]; 5535 5536 u8 reserved_at_20[0x10]; 5537 u8 op_mod[0x10]; 5538 5539 u8 qpc_ext[0x1]; 5540 u8 reserved_at_41[0x7]; 5541 u8 qpn[0x18]; 5542 5543 u8 reserved_at_60[0x20]; 5544 }; 5545 5546 struct mlx5_ifc_query_q_counter_out_bits { 5547 u8 status[0x8]; 5548 u8 reserved_at_8[0x18]; 5549 5550 u8 syndrome[0x20]; 5551 5552 u8 reserved_at_40[0x40]; 5553 5554 u8 rx_write_requests[0x20]; 5555 5556 u8 reserved_at_a0[0x20]; 5557 5558 u8 rx_read_requests[0x20]; 5559 5560 u8 reserved_at_e0[0x20]; 5561 5562 u8 rx_atomic_requests[0x20]; 5563 5564 u8 reserved_at_120[0x20]; 5565 5566 u8 rx_dct_connect[0x20]; 5567 5568 u8 reserved_at_160[0x20]; 5569 5570 u8 out_of_buffer[0x20]; 5571 5572 u8 reserved_at_1a0[0x20]; 5573 5574 u8 out_of_sequence[0x20]; 5575 5576 u8 reserved_at_1e0[0x20]; 5577 5578 u8 duplicate_request[0x20]; 5579 5580 u8 reserved_at_220[0x20]; 5581 5582 u8 rnr_nak_retry_err[0x20]; 5583 5584 u8 reserved_at_260[0x20]; 5585 5586 u8 packet_seq_err[0x20]; 5587 5588 u8 reserved_at_2a0[0x20]; 5589 5590 u8 implied_nak_seq_err[0x20]; 5591 5592 u8 reserved_at_2e0[0x20]; 5593 5594 u8 local_ack_timeout_err[0x20]; 5595 5596 u8 reserved_at_320[0xa0]; 5597 5598 u8 resp_local_length_error[0x20]; 5599 5600 u8 req_local_length_error[0x20]; 5601 5602 u8 resp_local_qp_error[0x20]; 5603 5604 u8 local_operation_error[0x20]; 5605 5606 u8 resp_local_protection[0x20]; 5607 5608 u8 req_local_protection[0x20]; 5609 5610 u8 resp_cqe_error[0x20]; 5611 5612 u8 req_cqe_error[0x20]; 5613 5614 u8 req_mw_binding[0x20]; 5615 5616 u8 req_bad_response[0x20]; 5617 5618 u8 req_remote_invalid_request[0x20]; 5619 5620 u8 resp_remote_invalid_request[0x20]; 5621 5622 u8 req_remote_access_errors[0x20]; 5623 5624 u8 resp_remote_access_errors[0x20]; 5625 5626 u8 req_remote_operation_errors[0x20]; 5627 5628 u8 req_transport_retries_exceeded[0x20]; 5629 5630 u8 cq_overflow[0x20]; 5631 5632 u8 resp_cqe_flush_error[0x20]; 5633 5634 u8 req_cqe_flush_error[0x20]; 5635 5636 u8 reserved_at_620[0x20]; 5637 5638 u8 roce_adp_retrans[0x20]; 5639 5640 u8 roce_adp_retrans_to[0x20]; 5641 5642 u8 roce_slow_restart[0x20]; 5643 5644 u8 roce_slow_restart_cnps[0x20]; 5645 5646 u8 roce_slow_restart_trans[0x20]; 5647 5648 u8 reserved_at_6e0[0x120]; 5649 }; 5650 5651 struct mlx5_ifc_query_q_counter_in_bits { 5652 u8 opcode[0x10]; 5653 u8 reserved_at_10[0x10]; 5654 5655 u8 reserved_at_20[0x10]; 5656 u8 op_mod[0x10]; 5657 5658 u8 other_vport[0x1]; 5659 u8 reserved_at_41[0xf]; 5660 u8 vport_number[0x10]; 5661 5662 u8 reserved_at_60[0x60]; 5663 5664 u8 clear[0x1]; 5665 u8 aggregate[0x1]; 5666 u8 reserved_at_c2[0x1e]; 5667 5668 u8 reserved_at_e0[0x18]; 5669 u8 counter_set_id[0x8]; 5670 }; 5671 5672 struct mlx5_ifc_query_pages_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 embedded_cpu_function[0x1]; 5679 u8 reserved_at_41[0xf]; 5680 u8 function_id[0x10]; 5681 5682 u8 num_pages[0x20]; 5683 }; 5684 5685 enum { 5686 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5687 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5688 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5689 }; 5690 5691 struct mlx5_ifc_query_pages_in_bits { 5692 u8 opcode[0x10]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 reserved_at_20[0x10]; 5696 u8 op_mod[0x10]; 5697 5698 u8 embedded_cpu_function[0x1]; 5699 u8 reserved_at_41[0xf]; 5700 u8 function_id[0x10]; 5701 5702 u8 reserved_at_60[0x20]; 5703 }; 5704 5705 struct mlx5_ifc_query_nic_vport_context_out_bits { 5706 u8 status[0x8]; 5707 u8 reserved_at_8[0x18]; 5708 5709 u8 syndrome[0x20]; 5710 5711 u8 reserved_at_40[0x40]; 5712 5713 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5714 }; 5715 5716 struct mlx5_ifc_query_nic_vport_context_in_bits { 5717 u8 opcode[0x10]; 5718 u8 reserved_at_10[0x10]; 5719 5720 u8 reserved_at_20[0x10]; 5721 u8 op_mod[0x10]; 5722 5723 u8 other_vport[0x1]; 5724 u8 reserved_at_41[0xf]; 5725 u8 vport_number[0x10]; 5726 5727 u8 reserved_at_60[0x5]; 5728 u8 allowed_list_type[0x3]; 5729 u8 reserved_at_68[0x18]; 5730 }; 5731 5732 struct mlx5_ifc_query_mkey_out_bits { 5733 u8 status[0x8]; 5734 u8 reserved_at_8[0x18]; 5735 5736 u8 syndrome[0x20]; 5737 5738 u8 reserved_at_40[0x40]; 5739 5740 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5741 5742 u8 reserved_at_280[0x600]; 5743 5744 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5745 5746 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5747 }; 5748 5749 struct mlx5_ifc_query_mkey_in_bits { 5750 u8 opcode[0x10]; 5751 u8 reserved_at_10[0x10]; 5752 5753 u8 reserved_at_20[0x10]; 5754 u8 op_mod[0x10]; 5755 5756 u8 reserved_at_40[0x8]; 5757 u8 mkey_index[0x18]; 5758 5759 u8 pg_access[0x1]; 5760 u8 reserved_at_61[0x1f]; 5761 }; 5762 5763 struct mlx5_ifc_query_mad_demux_out_bits { 5764 u8 status[0x8]; 5765 u8 reserved_at_8[0x18]; 5766 5767 u8 syndrome[0x20]; 5768 5769 u8 reserved_at_40[0x40]; 5770 5771 u8 mad_dumux_parameters_block[0x20]; 5772 }; 5773 5774 struct mlx5_ifc_query_mad_demux_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 reserved_at_40[0x40]; 5782 }; 5783 5784 struct mlx5_ifc_query_l2_table_entry_out_bits { 5785 u8 status[0x8]; 5786 u8 reserved_at_8[0x18]; 5787 5788 u8 syndrome[0x20]; 5789 5790 u8 reserved_at_40[0xa0]; 5791 5792 u8 reserved_at_e0[0x13]; 5793 u8 vlan_valid[0x1]; 5794 u8 vlan[0xc]; 5795 5796 struct mlx5_ifc_mac_address_layout_bits mac_address; 5797 5798 u8 reserved_at_140[0xc0]; 5799 }; 5800 5801 struct mlx5_ifc_query_l2_table_entry_in_bits { 5802 u8 opcode[0x10]; 5803 u8 reserved_at_10[0x10]; 5804 5805 u8 reserved_at_20[0x10]; 5806 u8 op_mod[0x10]; 5807 5808 u8 reserved_at_40[0x60]; 5809 5810 u8 reserved_at_a0[0x8]; 5811 u8 table_index[0x18]; 5812 5813 u8 reserved_at_c0[0x140]; 5814 }; 5815 5816 struct mlx5_ifc_query_issi_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_at_8[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 5822 u8 reserved_at_40[0x10]; 5823 u8 current_issi[0x10]; 5824 5825 u8 reserved_at_60[0xa0]; 5826 5827 u8 reserved_at_100[76][0x8]; 5828 u8 supported_issi_dw0[0x20]; 5829 }; 5830 5831 struct mlx5_ifc_query_issi_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_at_10[0x10]; 5834 5835 u8 reserved_at_20[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 reserved_at_40[0x40]; 5839 }; 5840 5841 struct mlx5_ifc_set_driver_version_out_bits { 5842 u8 status[0x8]; 5843 u8 reserved_0[0x18]; 5844 5845 u8 syndrome[0x20]; 5846 u8 reserved_1[0x40]; 5847 }; 5848 5849 struct mlx5_ifc_set_driver_version_in_bits { 5850 u8 opcode[0x10]; 5851 u8 reserved_0[0x10]; 5852 5853 u8 reserved_1[0x10]; 5854 u8 op_mod[0x10]; 5855 5856 u8 reserved_2[0x40]; 5857 u8 driver_version[64][0x8]; 5858 }; 5859 5860 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5861 u8 status[0x8]; 5862 u8 reserved_at_8[0x18]; 5863 5864 u8 syndrome[0x20]; 5865 5866 u8 reserved_at_40[0x40]; 5867 5868 struct mlx5_ifc_pkey_bits pkey[]; 5869 }; 5870 5871 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5872 u8 opcode[0x10]; 5873 u8 reserved_at_10[0x10]; 5874 5875 u8 reserved_at_20[0x10]; 5876 u8 op_mod[0x10]; 5877 5878 u8 other_vport[0x1]; 5879 u8 reserved_at_41[0xb]; 5880 u8 port_num[0x4]; 5881 u8 vport_number[0x10]; 5882 5883 u8 reserved_at_60[0x10]; 5884 u8 pkey_index[0x10]; 5885 }; 5886 5887 enum { 5888 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5889 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5890 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5891 }; 5892 5893 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5894 u8 status[0x8]; 5895 u8 reserved_at_8[0x18]; 5896 5897 u8 syndrome[0x20]; 5898 5899 u8 reserved_at_40[0x20]; 5900 5901 u8 gids_num[0x10]; 5902 u8 reserved_at_70[0x10]; 5903 5904 struct mlx5_ifc_array128_auto_bits gid[]; 5905 }; 5906 5907 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5908 u8 opcode[0x10]; 5909 u8 reserved_at_10[0x10]; 5910 5911 u8 reserved_at_20[0x10]; 5912 u8 op_mod[0x10]; 5913 5914 u8 other_vport[0x1]; 5915 u8 reserved_at_41[0xb]; 5916 u8 port_num[0x4]; 5917 u8 vport_number[0x10]; 5918 5919 u8 reserved_at_60[0x10]; 5920 u8 gid_index[0x10]; 5921 }; 5922 5923 struct mlx5_ifc_query_hca_vport_context_out_bits { 5924 u8 status[0x8]; 5925 u8 reserved_at_8[0x18]; 5926 5927 u8 syndrome[0x20]; 5928 5929 u8 reserved_at_40[0x40]; 5930 5931 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5932 }; 5933 5934 struct mlx5_ifc_query_hca_vport_context_in_bits { 5935 u8 opcode[0x10]; 5936 u8 reserved_at_10[0x10]; 5937 5938 u8 reserved_at_20[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 other_vport[0x1]; 5942 u8 reserved_at_41[0xb]; 5943 u8 port_num[0x4]; 5944 u8 vport_number[0x10]; 5945 5946 u8 reserved_at_60[0x20]; 5947 }; 5948 5949 struct mlx5_ifc_query_hca_cap_out_bits { 5950 u8 status[0x8]; 5951 u8 reserved_at_8[0x18]; 5952 5953 u8 syndrome[0x20]; 5954 5955 u8 reserved_at_40[0x40]; 5956 5957 union mlx5_ifc_hca_cap_union_bits capability; 5958 }; 5959 5960 struct mlx5_ifc_query_hca_cap_in_bits { 5961 u8 opcode[0x10]; 5962 u8 reserved_at_10[0x10]; 5963 5964 u8 reserved_at_20[0x10]; 5965 u8 op_mod[0x10]; 5966 5967 u8 other_function[0x1]; 5968 u8 ec_vf_function[0x1]; 5969 u8 reserved_at_42[0xe]; 5970 u8 function_id[0x10]; 5971 5972 u8 reserved_at_60[0x20]; 5973 }; 5974 5975 struct mlx5_ifc_other_hca_cap_bits { 5976 u8 roce[0x1]; 5977 u8 reserved_at_1[0x27f]; 5978 }; 5979 5980 struct mlx5_ifc_query_other_hca_cap_out_bits { 5981 u8 status[0x8]; 5982 u8 reserved_at_8[0x18]; 5983 5984 u8 syndrome[0x20]; 5985 5986 u8 reserved_at_40[0x40]; 5987 5988 struct mlx5_ifc_other_hca_cap_bits other_capability; 5989 }; 5990 5991 struct mlx5_ifc_query_other_hca_cap_in_bits { 5992 u8 opcode[0x10]; 5993 u8 reserved_at_10[0x10]; 5994 5995 u8 reserved_at_20[0x10]; 5996 u8 op_mod[0x10]; 5997 5998 u8 reserved_at_40[0x10]; 5999 u8 function_id[0x10]; 6000 6001 u8 reserved_at_60[0x20]; 6002 }; 6003 6004 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6005 u8 status[0x8]; 6006 u8 reserved_at_8[0x18]; 6007 6008 u8 syndrome[0x20]; 6009 6010 u8 reserved_at_40[0x40]; 6011 }; 6012 6013 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6014 u8 opcode[0x10]; 6015 u8 reserved_at_10[0x10]; 6016 6017 u8 reserved_at_20[0x10]; 6018 u8 op_mod[0x10]; 6019 6020 u8 reserved_at_40[0x10]; 6021 u8 function_id[0x10]; 6022 u8 field_select[0x20]; 6023 6024 struct mlx5_ifc_other_hca_cap_bits other_capability; 6025 }; 6026 6027 struct mlx5_ifc_flow_table_context_bits { 6028 u8 reformat_en[0x1]; 6029 u8 decap_en[0x1]; 6030 u8 sw_owner[0x1]; 6031 u8 termination_table[0x1]; 6032 u8 table_miss_action[0x4]; 6033 u8 level[0x8]; 6034 u8 reserved_at_10[0x8]; 6035 u8 log_size[0x8]; 6036 6037 u8 reserved_at_20[0x8]; 6038 u8 table_miss_id[0x18]; 6039 6040 u8 reserved_at_40[0x8]; 6041 u8 lag_master_next_table_id[0x18]; 6042 6043 u8 reserved_at_60[0x60]; 6044 6045 u8 sw_owner_icm_root_1[0x40]; 6046 6047 u8 sw_owner_icm_root_0[0x40]; 6048 6049 }; 6050 6051 struct mlx5_ifc_query_flow_table_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_at_8[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_at_40[0x80]; 6058 6059 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6060 }; 6061 6062 struct mlx5_ifc_query_flow_table_in_bits { 6063 u8 opcode[0x10]; 6064 u8 reserved_at_10[0x10]; 6065 6066 u8 reserved_at_20[0x10]; 6067 u8 op_mod[0x10]; 6068 6069 u8 reserved_at_40[0x40]; 6070 6071 u8 table_type[0x8]; 6072 u8 reserved_at_88[0x18]; 6073 6074 u8 reserved_at_a0[0x8]; 6075 u8 table_id[0x18]; 6076 6077 u8 reserved_at_c0[0x140]; 6078 }; 6079 6080 struct mlx5_ifc_query_fte_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_at_8[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 reserved_at_40[0x1c0]; 6087 6088 struct mlx5_ifc_flow_context_bits flow_context; 6089 }; 6090 6091 struct mlx5_ifc_query_fte_in_bits { 6092 u8 opcode[0x10]; 6093 u8 reserved_at_10[0x10]; 6094 6095 u8 reserved_at_20[0x10]; 6096 u8 op_mod[0x10]; 6097 6098 u8 reserved_at_40[0x40]; 6099 6100 u8 table_type[0x8]; 6101 u8 reserved_at_88[0x18]; 6102 6103 u8 reserved_at_a0[0x8]; 6104 u8 table_id[0x18]; 6105 6106 u8 reserved_at_c0[0x40]; 6107 6108 u8 flow_index[0x20]; 6109 6110 u8 reserved_at_120[0xe0]; 6111 }; 6112 6113 struct mlx5_ifc_match_definer_format_0_bits { 6114 u8 reserved_at_0[0x100]; 6115 6116 u8 metadata_reg_c_0[0x20]; 6117 6118 u8 metadata_reg_c_1[0x20]; 6119 6120 u8 outer_dmac_47_16[0x20]; 6121 6122 u8 outer_dmac_15_0[0x10]; 6123 u8 outer_ethertype[0x10]; 6124 6125 u8 reserved_at_180[0x1]; 6126 u8 sx_sniffer[0x1]; 6127 u8 functional_lb[0x1]; 6128 u8 outer_ip_frag[0x1]; 6129 u8 outer_qp_type[0x2]; 6130 u8 outer_encap_type[0x2]; 6131 u8 port_number[0x2]; 6132 u8 outer_l3_type[0x2]; 6133 u8 outer_l4_type[0x2]; 6134 u8 outer_first_vlan_type[0x2]; 6135 u8 outer_first_vlan_prio[0x3]; 6136 u8 outer_first_vlan_cfi[0x1]; 6137 u8 outer_first_vlan_vid[0xc]; 6138 6139 u8 outer_l4_type_ext[0x4]; 6140 u8 reserved_at_1a4[0x2]; 6141 u8 outer_ipsec_layer[0x2]; 6142 u8 outer_l2_type[0x2]; 6143 u8 force_lb[0x1]; 6144 u8 outer_l2_ok[0x1]; 6145 u8 outer_l3_ok[0x1]; 6146 u8 outer_l4_ok[0x1]; 6147 u8 outer_second_vlan_type[0x2]; 6148 u8 outer_second_vlan_prio[0x3]; 6149 u8 outer_second_vlan_cfi[0x1]; 6150 u8 outer_second_vlan_vid[0xc]; 6151 6152 u8 outer_smac_47_16[0x20]; 6153 6154 u8 outer_smac_15_0[0x10]; 6155 u8 inner_ipv4_checksum_ok[0x1]; 6156 u8 inner_l4_checksum_ok[0x1]; 6157 u8 outer_ipv4_checksum_ok[0x1]; 6158 u8 outer_l4_checksum_ok[0x1]; 6159 u8 inner_l3_ok[0x1]; 6160 u8 inner_l4_ok[0x1]; 6161 u8 outer_l3_ok_duplicate[0x1]; 6162 u8 outer_l4_ok_duplicate[0x1]; 6163 u8 outer_tcp_cwr[0x1]; 6164 u8 outer_tcp_ece[0x1]; 6165 u8 outer_tcp_urg[0x1]; 6166 u8 outer_tcp_ack[0x1]; 6167 u8 outer_tcp_psh[0x1]; 6168 u8 outer_tcp_rst[0x1]; 6169 u8 outer_tcp_syn[0x1]; 6170 u8 outer_tcp_fin[0x1]; 6171 }; 6172 6173 struct mlx5_ifc_match_definer_format_22_bits { 6174 u8 reserved_at_0[0x100]; 6175 6176 u8 outer_ip_src_addr[0x20]; 6177 6178 u8 outer_ip_dest_addr[0x20]; 6179 6180 u8 outer_l4_sport[0x10]; 6181 u8 outer_l4_dport[0x10]; 6182 6183 u8 reserved_at_160[0x1]; 6184 u8 sx_sniffer[0x1]; 6185 u8 functional_lb[0x1]; 6186 u8 outer_ip_frag[0x1]; 6187 u8 outer_qp_type[0x2]; 6188 u8 outer_encap_type[0x2]; 6189 u8 port_number[0x2]; 6190 u8 outer_l3_type[0x2]; 6191 u8 outer_l4_type[0x2]; 6192 u8 outer_first_vlan_type[0x2]; 6193 u8 outer_first_vlan_prio[0x3]; 6194 u8 outer_first_vlan_cfi[0x1]; 6195 u8 outer_first_vlan_vid[0xc]; 6196 6197 u8 metadata_reg_c_0[0x20]; 6198 6199 u8 outer_dmac_47_16[0x20]; 6200 6201 u8 outer_smac_47_16[0x20]; 6202 6203 u8 outer_smac_15_0[0x10]; 6204 u8 outer_dmac_15_0[0x10]; 6205 }; 6206 6207 struct mlx5_ifc_match_definer_format_23_bits { 6208 u8 reserved_at_0[0x100]; 6209 6210 u8 inner_ip_src_addr[0x20]; 6211 6212 u8 inner_ip_dest_addr[0x20]; 6213 6214 u8 inner_l4_sport[0x10]; 6215 u8 inner_l4_dport[0x10]; 6216 6217 u8 reserved_at_160[0x1]; 6218 u8 sx_sniffer[0x1]; 6219 u8 functional_lb[0x1]; 6220 u8 inner_ip_frag[0x1]; 6221 u8 inner_qp_type[0x2]; 6222 u8 inner_encap_type[0x2]; 6223 u8 port_number[0x2]; 6224 u8 inner_l3_type[0x2]; 6225 u8 inner_l4_type[0x2]; 6226 u8 inner_first_vlan_type[0x2]; 6227 u8 inner_first_vlan_prio[0x3]; 6228 u8 inner_first_vlan_cfi[0x1]; 6229 u8 inner_first_vlan_vid[0xc]; 6230 6231 u8 tunnel_header_0[0x20]; 6232 6233 u8 inner_dmac_47_16[0x20]; 6234 6235 u8 inner_smac_47_16[0x20]; 6236 6237 u8 inner_smac_15_0[0x10]; 6238 u8 inner_dmac_15_0[0x10]; 6239 }; 6240 6241 struct mlx5_ifc_match_definer_format_29_bits { 6242 u8 reserved_at_0[0xc0]; 6243 6244 u8 outer_ip_dest_addr[0x80]; 6245 6246 u8 outer_ip_src_addr[0x80]; 6247 6248 u8 outer_l4_sport[0x10]; 6249 u8 outer_l4_dport[0x10]; 6250 6251 u8 reserved_at_1e0[0x20]; 6252 }; 6253 6254 struct mlx5_ifc_match_definer_format_30_bits { 6255 u8 reserved_at_0[0xa0]; 6256 6257 u8 outer_ip_dest_addr[0x80]; 6258 6259 u8 outer_ip_src_addr[0x80]; 6260 6261 u8 outer_dmac_47_16[0x20]; 6262 6263 u8 outer_smac_47_16[0x20]; 6264 6265 u8 outer_smac_15_0[0x10]; 6266 u8 outer_dmac_15_0[0x10]; 6267 }; 6268 6269 struct mlx5_ifc_match_definer_format_31_bits { 6270 u8 reserved_at_0[0xc0]; 6271 6272 u8 inner_ip_dest_addr[0x80]; 6273 6274 u8 inner_ip_src_addr[0x80]; 6275 6276 u8 inner_l4_sport[0x10]; 6277 u8 inner_l4_dport[0x10]; 6278 6279 u8 reserved_at_1e0[0x20]; 6280 }; 6281 6282 struct mlx5_ifc_match_definer_format_32_bits { 6283 u8 reserved_at_0[0xa0]; 6284 6285 u8 inner_ip_dest_addr[0x80]; 6286 6287 u8 inner_ip_src_addr[0x80]; 6288 6289 u8 inner_dmac_47_16[0x20]; 6290 6291 u8 inner_smac_47_16[0x20]; 6292 6293 u8 inner_smac_15_0[0x10]; 6294 u8 inner_dmac_15_0[0x10]; 6295 }; 6296 6297 enum { 6298 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6299 }; 6300 6301 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6302 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6303 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6304 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6305 6306 struct mlx5_ifc_match_definer_match_mask_bits { 6307 u8 reserved_at_1c0[5][0x20]; 6308 u8 match_dw_8[0x20]; 6309 u8 match_dw_7[0x20]; 6310 u8 match_dw_6[0x20]; 6311 u8 match_dw_5[0x20]; 6312 u8 match_dw_4[0x20]; 6313 u8 match_dw_3[0x20]; 6314 u8 match_dw_2[0x20]; 6315 u8 match_dw_1[0x20]; 6316 u8 match_dw_0[0x20]; 6317 6318 u8 match_byte_7[0x8]; 6319 u8 match_byte_6[0x8]; 6320 u8 match_byte_5[0x8]; 6321 u8 match_byte_4[0x8]; 6322 6323 u8 match_byte_3[0x8]; 6324 u8 match_byte_2[0x8]; 6325 u8 match_byte_1[0x8]; 6326 u8 match_byte_0[0x8]; 6327 }; 6328 6329 struct mlx5_ifc_match_definer_bits { 6330 u8 modify_field_select[0x40]; 6331 6332 u8 reserved_at_40[0x40]; 6333 6334 u8 reserved_at_80[0x10]; 6335 u8 format_id[0x10]; 6336 6337 u8 reserved_at_a0[0x60]; 6338 6339 u8 format_select_dw3[0x8]; 6340 u8 format_select_dw2[0x8]; 6341 u8 format_select_dw1[0x8]; 6342 u8 format_select_dw0[0x8]; 6343 6344 u8 format_select_dw7[0x8]; 6345 u8 format_select_dw6[0x8]; 6346 u8 format_select_dw5[0x8]; 6347 u8 format_select_dw4[0x8]; 6348 6349 u8 reserved_at_100[0x18]; 6350 u8 format_select_dw8[0x8]; 6351 6352 u8 reserved_at_120[0x20]; 6353 6354 u8 format_select_byte3[0x8]; 6355 u8 format_select_byte2[0x8]; 6356 u8 format_select_byte1[0x8]; 6357 u8 format_select_byte0[0x8]; 6358 6359 u8 format_select_byte7[0x8]; 6360 u8 format_select_byte6[0x8]; 6361 u8 format_select_byte5[0x8]; 6362 u8 format_select_byte4[0x8]; 6363 6364 u8 reserved_at_180[0x40]; 6365 6366 union { 6367 struct { 6368 u8 match_mask[16][0x20]; 6369 }; 6370 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6371 }; 6372 }; 6373 6374 struct mlx5_ifc_general_obj_create_param_bits { 6375 u8 alias_object[0x1]; 6376 u8 reserved_at_1[0x2]; 6377 u8 log_obj_range[0x5]; 6378 u8 reserved_at_8[0x18]; 6379 }; 6380 6381 struct mlx5_ifc_general_obj_query_param_bits { 6382 u8 alias_object[0x1]; 6383 u8 obj_offset[0x1f]; 6384 }; 6385 6386 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6387 u8 opcode[0x10]; 6388 u8 uid[0x10]; 6389 6390 u8 vhca_tunnel_id[0x10]; 6391 u8 obj_type[0x10]; 6392 6393 u8 obj_id[0x20]; 6394 6395 union { 6396 struct mlx5_ifc_general_obj_create_param_bits create; 6397 struct mlx5_ifc_general_obj_query_param_bits query; 6398 } op_param; 6399 }; 6400 6401 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6402 u8 status[0x8]; 6403 u8 reserved_at_8[0x18]; 6404 6405 u8 syndrome[0x20]; 6406 6407 u8 obj_id[0x20]; 6408 6409 u8 reserved_at_60[0x20]; 6410 }; 6411 6412 struct mlx5_ifc_modify_header_arg_bits { 6413 u8 reserved_at_0[0x80]; 6414 6415 u8 reserved_at_80[0x8]; 6416 u8 access_pd[0x18]; 6417 }; 6418 6419 struct mlx5_ifc_create_modify_header_arg_in_bits { 6420 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6421 struct mlx5_ifc_modify_header_arg_bits arg; 6422 }; 6423 6424 struct mlx5_ifc_create_match_definer_in_bits { 6425 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6426 6427 struct mlx5_ifc_match_definer_bits obj_context; 6428 }; 6429 6430 struct mlx5_ifc_create_match_definer_out_bits { 6431 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6432 }; 6433 6434 enum { 6435 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6436 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6437 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6438 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6439 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6440 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6441 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6442 }; 6443 6444 struct mlx5_ifc_query_flow_group_out_bits { 6445 u8 status[0x8]; 6446 u8 reserved_at_8[0x18]; 6447 6448 u8 syndrome[0x20]; 6449 6450 u8 reserved_at_40[0xa0]; 6451 6452 u8 start_flow_index[0x20]; 6453 6454 u8 reserved_at_100[0x20]; 6455 6456 u8 end_flow_index[0x20]; 6457 6458 u8 reserved_at_140[0xa0]; 6459 6460 u8 reserved_at_1e0[0x18]; 6461 u8 match_criteria_enable[0x8]; 6462 6463 struct mlx5_ifc_fte_match_param_bits match_criteria; 6464 6465 u8 reserved_at_1200[0xe00]; 6466 }; 6467 6468 struct mlx5_ifc_query_flow_group_in_bits { 6469 u8 opcode[0x10]; 6470 u8 reserved_at_10[0x10]; 6471 6472 u8 reserved_at_20[0x10]; 6473 u8 op_mod[0x10]; 6474 6475 u8 reserved_at_40[0x40]; 6476 6477 u8 table_type[0x8]; 6478 u8 reserved_at_88[0x18]; 6479 6480 u8 reserved_at_a0[0x8]; 6481 u8 table_id[0x18]; 6482 6483 u8 group_id[0x20]; 6484 6485 u8 reserved_at_e0[0x120]; 6486 }; 6487 6488 struct mlx5_ifc_query_flow_counter_out_bits { 6489 u8 status[0x8]; 6490 u8 reserved_at_8[0x18]; 6491 6492 u8 syndrome[0x20]; 6493 6494 u8 reserved_at_40[0x40]; 6495 6496 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6497 }; 6498 6499 struct mlx5_ifc_query_flow_counter_in_bits { 6500 u8 opcode[0x10]; 6501 u8 reserved_at_10[0x10]; 6502 6503 u8 reserved_at_20[0x10]; 6504 u8 op_mod[0x10]; 6505 6506 u8 reserved_at_40[0x80]; 6507 6508 u8 clear[0x1]; 6509 u8 reserved_at_c1[0xf]; 6510 u8 num_of_counters[0x10]; 6511 6512 u8 flow_counter_id[0x20]; 6513 }; 6514 6515 struct mlx5_ifc_query_esw_vport_context_out_bits { 6516 u8 status[0x8]; 6517 u8 reserved_at_8[0x18]; 6518 6519 u8 syndrome[0x20]; 6520 6521 u8 reserved_at_40[0x40]; 6522 6523 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6524 }; 6525 6526 struct mlx5_ifc_query_esw_vport_context_in_bits { 6527 u8 opcode[0x10]; 6528 u8 reserved_at_10[0x10]; 6529 6530 u8 reserved_at_20[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 other_vport[0x1]; 6534 u8 reserved_at_41[0xf]; 6535 u8 vport_number[0x10]; 6536 6537 u8 reserved_at_60[0x20]; 6538 }; 6539 6540 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6541 u8 status[0x8]; 6542 u8 reserved_at_8[0x18]; 6543 6544 u8 syndrome[0x20]; 6545 6546 u8 reserved_at_40[0x40]; 6547 }; 6548 6549 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6550 u8 reserved_at_0[0x1b]; 6551 u8 fdb_to_vport_reg_c_id[0x1]; 6552 u8 vport_cvlan_insert[0x1]; 6553 u8 vport_svlan_insert[0x1]; 6554 u8 vport_cvlan_strip[0x1]; 6555 u8 vport_svlan_strip[0x1]; 6556 }; 6557 6558 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_at_10[0x10]; 6561 6562 u8 reserved_at_20[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 other_vport[0x1]; 6566 u8 reserved_at_41[0xf]; 6567 u8 vport_number[0x10]; 6568 6569 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6570 6571 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6572 }; 6573 6574 struct mlx5_ifc_query_eq_out_bits { 6575 u8 status[0x8]; 6576 u8 reserved_at_8[0x18]; 6577 6578 u8 syndrome[0x20]; 6579 6580 u8 reserved_at_40[0x40]; 6581 6582 struct mlx5_ifc_eqc_bits eq_context_entry; 6583 6584 u8 reserved_at_280[0x40]; 6585 6586 u8 event_bitmask[0x40]; 6587 6588 u8 reserved_at_300[0x580]; 6589 6590 u8 pas[][0x40]; 6591 }; 6592 6593 struct mlx5_ifc_query_eq_in_bits { 6594 u8 opcode[0x10]; 6595 u8 reserved_at_10[0x10]; 6596 6597 u8 reserved_at_20[0x10]; 6598 u8 op_mod[0x10]; 6599 6600 u8 reserved_at_40[0x18]; 6601 u8 eq_number[0x8]; 6602 6603 u8 reserved_at_60[0x20]; 6604 }; 6605 6606 struct mlx5_ifc_packet_reformat_context_in_bits { 6607 u8 reformat_type[0x8]; 6608 u8 reserved_at_8[0x4]; 6609 u8 reformat_param_0[0x4]; 6610 u8 reserved_at_10[0x6]; 6611 u8 reformat_data_size[0xa]; 6612 6613 u8 reformat_param_1[0x8]; 6614 u8 reserved_at_28[0x8]; 6615 u8 reformat_data[2][0x8]; 6616 6617 u8 more_reformat_data[][0x8]; 6618 }; 6619 6620 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6621 u8 status[0x8]; 6622 u8 reserved_at_8[0x18]; 6623 6624 u8 syndrome[0x20]; 6625 6626 u8 reserved_at_40[0xa0]; 6627 6628 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6629 }; 6630 6631 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6632 u8 opcode[0x10]; 6633 u8 reserved_at_10[0x10]; 6634 6635 u8 reserved_at_20[0x10]; 6636 u8 op_mod[0x10]; 6637 6638 u8 packet_reformat_id[0x20]; 6639 6640 u8 reserved_at_60[0xa0]; 6641 }; 6642 6643 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6644 u8 status[0x8]; 6645 u8 reserved_at_8[0x18]; 6646 6647 u8 syndrome[0x20]; 6648 6649 u8 packet_reformat_id[0x20]; 6650 6651 u8 reserved_at_60[0x20]; 6652 }; 6653 6654 enum { 6655 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6656 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6657 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6658 }; 6659 6660 enum mlx5_reformat_ctx_type { 6661 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6662 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6663 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6664 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6665 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6666 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6667 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6668 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6669 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6670 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6671 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6672 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6673 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6674 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6675 }; 6676 6677 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6678 u8 opcode[0x10]; 6679 u8 reserved_at_10[0x10]; 6680 6681 u8 reserved_at_20[0x10]; 6682 u8 op_mod[0x10]; 6683 6684 u8 reserved_at_40[0xa0]; 6685 6686 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6687 }; 6688 6689 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6690 u8 status[0x8]; 6691 u8 reserved_at_8[0x18]; 6692 6693 u8 syndrome[0x20]; 6694 6695 u8 reserved_at_40[0x40]; 6696 }; 6697 6698 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6699 u8 opcode[0x10]; 6700 u8 reserved_at_10[0x10]; 6701 6702 u8 reserved_20[0x10]; 6703 u8 op_mod[0x10]; 6704 6705 u8 packet_reformat_id[0x20]; 6706 6707 u8 reserved_60[0x20]; 6708 }; 6709 6710 struct mlx5_ifc_set_action_in_bits { 6711 u8 action_type[0x4]; 6712 u8 field[0xc]; 6713 u8 reserved_at_10[0x3]; 6714 u8 offset[0x5]; 6715 u8 reserved_at_18[0x3]; 6716 u8 length[0x5]; 6717 6718 u8 data[0x20]; 6719 }; 6720 6721 struct mlx5_ifc_add_action_in_bits { 6722 u8 action_type[0x4]; 6723 u8 field[0xc]; 6724 u8 reserved_at_10[0x10]; 6725 6726 u8 data[0x20]; 6727 }; 6728 6729 struct mlx5_ifc_copy_action_in_bits { 6730 u8 action_type[0x4]; 6731 u8 src_field[0xc]; 6732 u8 reserved_at_10[0x3]; 6733 u8 src_offset[0x5]; 6734 u8 reserved_at_18[0x3]; 6735 u8 length[0x5]; 6736 6737 u8 reserved_at_20[0x4]; 6738 u8 dst_field[0xc]; 6739 u8 reserved_at_30[0x3]; 6740 u8 dst_offset[0x5]; 6741 u8 reserved_at_38[0x8]; 6742 }; 6743 6744 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6745 struct mlx5_ifc_set_action_in_bits set_action_in; 6746 struct mlx5_ifc_add_action_in_bits add_action_in; 6747 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6748 u8 reserved_at_0[0x40]; 6749 }; 6750 6751 enum { 6752 MLX5_ACTION_TYPE_SET = 0x1, 6753 MLX5_ACTION_TYPE_ADD = 0x2, 6754 MLX5_ACTION_TYPE_COPY = 0x3, 6755 }; 6756 6757 enum { 6758 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6759 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6760 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6761 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6762 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6763 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6764 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6765 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6766 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6767 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6768 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6769 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6770 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6771 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6772 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6773 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6774 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6775 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6776 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6777 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6778 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6779 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6780 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6781 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6782 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6783 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6784 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6785 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6786 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6787 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6788 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6789 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6790 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6791 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6792 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6793 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6794 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6795 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6796 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6797 }; 6798 6799 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6800 u8 status[0x8]; 6801 u8 reserved_at_8[0x18]; 6802 6803 u8 syndrome[0x20]; 6804 6805 u8 modify_header_id[0x20]; 6806 6807 u8 reserved_at_60[0x20]; 6808 }; 6809 6810 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6811 u8 opcode[0x10]; 6812 u8 reserved_at_10[0x10]; 6813 6814 u8 reserved_at_20[0x10]; 6815 u8 op_mod[0x10]; 6816 6817 u8 reserved_at_40[0x20]; 6818 6819 u8 table_type[0x8]; 6820 u8 reserved_at_68[0x10]; 6821 u8 num_of_actions[0x8]; 6822 6823 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6824 }; 6825 6826 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6827 u8 status[0x8]; 6828 u8 reserved_at_8[0x18]; 6829 6830 u8 syndrome[0x20]; 6831 6832 u8 reserved_at_40[0x40]; 6833 }; 6834 6835 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6836 u8 opcode[0x10]; 6837 u8 reserved_at_10[0x10]; 6838 6839 u8 reserved_at_20[0x10]; 6840 u8 op_mod[0x10]; 6841 6842 u8 modify_header_id[0x20]; 6843 6844 u8 reserved_at_60[0x20]; 6845 }; 6846 6847 struct mlx5_ifc_query_modify_header_context_in_bits { 6848 u8 opcode[0x10]; 6849 u8 uid[0x10]; 6850 6851 u8 reserved_at_20[0x10]; 6852 u8 op_mod[0x10]; 6853 6854 u8 modify_header_id[0x20]; 6855 6856 u8 reserved_at_60[0xa0]; 6857 }; 6858 6859 struct mlx5_ifc_query_dct_out_bits { 6860 u8 status[0x8]; 6861 u8 reserved_at_8[0x18]; 6862 6863 u8 syndrome[0x20]; 6864 6865 u8 reserved_at_40[0x40]; 6866 6867 struct mlx5_ifc_dctc_bits dct_context_entry; 6868 6869 u8 reserved_at_280[0x180]; 6870 }; 6871 6872 struct mlx5_ifc_query_dct_in_bits { 6873 u8 opcode[0x10]; 6874 u8 reserved_at_10[0x10]; 6875 6876 u8 reserved_at_20[0x10]; 6877 u8 op_mod[0x10]; 6878 6879 u8 reserved_at_40[0x8]; 6880 u8 dctn[0x18]; 6881 6882 u8 reserved_at_60[0x20]; 6883 }; 6884 6885 struct mlx5_ifc_query_cq_out_bits { 6886 u8 status[0x8]; 6887 u8 reserved_at_8[0x18]; 6888 6889 u8 syndrome[0x20]; 6890 6891 u8 reserved_at_40[0x40]; 6892 6893 struct mlx5_ifc_cqc_bits cq_context; 6894 6895 u8 reserved_at_280[0x600]; 6896 6897 u8 pas[][0x40]; 6898 }; 6899 6900 struct mlx5_ifc_query_cq_in_bits { 6901 u8 opcode[0x10]; 6902 u8 reserved_at_10[0x10]; 6903 6904 u8 reserved_at_20[0x10]; 6905 u8 op_mod[0x10]; 6906 6907 u8 reserved_at_40[0x8]; 6908 u8 cqn[0x18]; 6909 6910 u8 reserved_at_60[0x20]; 6911 }; 6912 6913 struct mlx5_ifc_query_cong_status_out_bits { 6914 u8 status[0x8]; 6915 u8 reserved_at_8[0x18]; 6916 6917 u8 syndrome[0x20]; 6918 6919 u8 reserved_at_40[0x20]; 6920 6921 u8 enable[0x1]; 6922 u8 tag_enable[0x1]; 6923 u8 reserved_at_62[0x1e]; 6924 }; 6925 6926 struct mlx5_ifc_query_cong_status_in_bits { 6927 u8 opcode[0x10]; 6928 u8 reserved_at_10[0x10]; 6929 6930 u8 reserved_at_20[0x10]; 6931 u8 op_mod[0x10]; 6932 6933 u8 reserved_at_40[0x18]; 6934 u8 priority[0x4]; 6935 u8 cong_protocol[0x4]; 6936 6937 u8 reserved_at_60[0x20]; 6938 }; 6939 6940 struct mlx5_ifc_query_cong_statistics_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_at_8[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_at_40[0x40]; 6947 6948 u8 rp_cur_flows[0x20]; 6949 6950 u8 sum_flows[0x20]; 6951 6952 u8 rp_cnp_ignored_high[0x20]; 6953 6954 u8 rp_cnp_ignored_low[0x20]; 6955 6956 u8 rp_cnp_handled_high[0x20]; 6957 6958 u8 rp_cnp_handled_low[0x20]; 6959 6960 u8 reserved_at_140[0x100]; 6961 6962 u8 time_stamp_high[0x20]; 6963 6964 u8 time_stamp_low[0x20]; 6965 6966 u8 accumulators_period[0x20]; 6967 6968 u8 np_ecn_marked_roce_packets_high[0x20]; 6969 6970 u8 np_ecn_marked_roce_packets_low[0x20]; 6971 6972 u8 np_cnp_sent_high[0x20]; 6973 6974 u8 np_cnp_sent_low[0x20]; 6975 6976 u8 reserved_at_320[0x560]; 6977 }; 6978 6979 struct mlx5_ifc_query_cong_statistics_in_bits { 6980 u8 opcode[0x10]; 6981 u8 reserved_at_10[0x10]; 6982 6983 u8 reserved_at_20[0x10]; 6984 u8 op_mod[0x10]; 6985 6986 u8 clear[0x1]; 6987 u8 reserved_at_41[0x1f]; 6988 6989 u8 reserved_at_60[0x20]; 6990 }; 6991 6992 struct mlx5_ifc_query_cong_params_out_bits { 6993 u8 status[0x8]; 6994 u8 reserved_at_8[0x18]; 6995 6996 u8 syndrome[0x20]; 6997 6998 u8 reserved_at_40[0x40]; 6999 7000 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7001 }; 7002 7003 struct mlx5_ifc_query_cong_params_in_bits { 7004 u8 opcode[0x10]; 7005 u8 reserved_at_10[0x10]; 7006 7007 u8 reserved_at_20[0x10]; 7008 u8 op_mod[0x10]; 7009 7010 u8 reserved_at_40[0x1c]; 7011 u8 cong_protocol[0x4]; 7012 7013 u8 reserved_at_60[0x20]; 7014 }; 7015 7016 struct mlx5_ifc_query_adapter_out_bits { 7017 u8 status[0x8]; 7018 u8 reserved_at_8[0x18]; 7019 7020 u8 syndrome[0x20]; 7021 7022 u8 reserved_at_40[0x40]; 7023 7024 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7025 }; 7026 7027 struct mlx5_ifc_query_adapter_in_bits { 7028 u8 opcode[0x10]; 7029 u8 reserved_at_10[0x10]; 7030 7031 u8 reserved_at_20[0x10]; 7032 u8 op_mod[0x10]; 7033 7034 u8 reserved_at_40[0x40]; 7035 }; 7036 7037 struct mlx5_ifc_qp_2rst_out_bits { 7038 u8 status[0x8]; 7039 u8 reserved_at_8[0x18]; 7040 7041 u8 syndrome[0x20]; 7042 7043 u8 reserved_at_40[0x40]; 7044 }; 7045 7046 struct mlx5_ifc_qp_2rst_in_bits { 7047 u8 opcode[0x10]; 7048 u8 uid[0x10]; 7049 7050 u8 reserved_at_20[0x10]; 7051 u8 op_mod[0x10]; 7052 7053 u8 reserved_at_40[0x8]; 7054 u8 qpn[0x18]; 7055 7056 u8 reserved_at_60[0x20]; 7057 }; 7058 7059 struct mlx5_ifc_qp_2err_out_bits { 7060 u8 status[0x8]; 7061 u8 reserved_at_8[0x18]; 7062 7063 u8 syndrome[0x20]; 7064 7065 u8 reserved_at_40[0x40]; 7066 }; 7067 7068 struct mlx5_ifc_qp_2err_in_bits { 7069 u8 opcode[0x10]; 7070 u8 uid[0x10]; 7071 7072 u8 reserved_at_20[0x10]; 7073 u8 op_mod[0x10]; 7074 7075 u8 reserved_at_40[0x8]; 7076 u8 qpn[0x18]; 7077 7078 u8 reserved_at_60[0x20]; 7079 }; 7080 7081 struct mlx5_ifc_page_fault_resume_out_bits { 7082 u8 status[0x8]; 7083 u8 reserved_at_8[0x18]; 7084 7085 u8 syndrome[0x20]; 7086 7087 u8 reserved_at_40[0x40]; 7088 }; 7089 7090 struct mlx5_ifc_page_fault_resume_in_bits { 7091 u8 opcode[0x10]; 7092 u8 reserved_at_10[0x10]; 7093 7094 u8 reserved_at_20[0x10]; 7095 u8 op_mod[0x10]; 7096 7097 u8 error[0x1]; 7098 u8 reserved_at_41[0x4]; 7099 u8 page_fault_type[0x3]; 7100 u8 wq_number[0x18]; 7101 7102 u8 reserved_at_60[0x8]; 7103 u8 token[0x18]; 7104 }; 7105 7106 struct mlx5_ifc_nop_out_bits { 7107 u8 status[0x8]; 7108 u8 reserved_at_8[0x18]; 7109 7110 u8 syndrome[0x20]; 7111 7112 u8 reserved_at_40[0x40]; 7113 }; 7114 7115 struct mlx5_ifc_nop_in_bits { 7116 u8 opcode[0x10]; 7117 u8 reserved_at_10[0x10]; 7118 7119 u8 reserved_at_20[0x10]; 7120 u8 op_mod[0x10]; 7121 7122 u8 reserved_at_40[0x40]; 7123 }; 7124 7125 struct mlx5_ifc_modify_vport_state_out_bits { 7126 u8 status[0x8]; 7127 u8 reserved_at_8[0x18]; 7128 7129 u8 syndrome[0x20]; 7130 7131 u8 reserved_at_40[0x40]; 7132 }; 7133 7134 struct mlx5_ifc_modify_vport_state_in_bits { 7135 u8 opcode[0x10]; 7136 u8 reserved_at_10[0x10]; 7137 7138 u8 reserved_at_20[0x10]; 7139 u8 op_mod[0x10]; 7140 7141 u8 other_vport[0x1]; 7142 u8 reserved_at_41[0xf]; 7143 u8 vport_number[0x10]; 7144 7145 u8 reserved_at_60[0x18]; 7146 u8 admin_state[0x4]; 7147 u8 reserved_at_7c[0x4]; 7148 }; 7149 7150 struct mlx5_ifc_modify_tis_out_bits { 7151 u8 status[0x8]; 7152 u8 reserved_at_8[0x18]; 7153 7154 u8 syndrome[0x20]; 7155 7156 u8 reserved_at_40[0x40]; 7157 }; 7158 7159 struct mlx5_ifc_modify_tis_bitmask_bits { 7160 u8 reserved_at_0[0x20]; 7161 7162 u8 reserved_at_20[0x1d]; 7163 u8 lag_tx_port_affinity[0x1]; 7164 u8 strict_lag_tx_port_affinity[0x1]; 7165 u8 prio[0x1]; 7166 }; 7167 7168 struct mlx5_ifc_modify_tis_in_bits { 7169 u8 opcode[0x10]; 7170 u8 uid[0x10]; 7171 7172 u8 reserved_at_20[0x10]; 7173 u8 op_mod[0x10]; 7174 7175 u8 reserved_at_40[0x8]; 7176 u8 tisn[0x18]; 7177 7178 u8 reserved_at_60[0x20]; 7179 7180 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7181 7182 u8 reserved_at_c0[0x40]; 7183 7184 struct mlx5_ifc_tisc_bits ctx; 7185 }; 7186 7187 struct mlx5_ifc_modify_tir_bitmask_bits { 7188 u8 reserved_at_0[0x20]; 7189 7190 u8 reserved_at_20[0x1b]; 7191 u8 self_lb_en[0x1]; 7192 u8 reserved_at_3c[0x1]; 7193 u8 hash[0x1]; 7194 u8 reserved_at_3e[0x1]; 7195 u8 packet_merge[0x1]; 7196 }; 7197 7198 struct mlx5_ifc_modify_tir_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_at_8[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_at_40[0x40]; 7205 }; 7206 7207 struct mlx5_ifc_modify_tir_in_bits { 7208 u8 opcode[0x10]; 7209 u8 uid[0x10]; 7210 7211 u8 reserved_at_20[0x10]; 7212 u8 op_mod[0x10]; 7213 7214 u8 reserved_at_40[0x8]; 7215 u8 tirn[0x18]; 7216 7217 u8 reserved_at_60[0x20]; 7218 7219 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7220 7221 u8 reserved_at_c0[0x40]; 7222 7223 struct mlx5_ifc_tirc_bits ctx; 7224 }; 7225 7226 struct mlx5_ifc_modify_sq_out_bits { 7227 u8 status[0x8]; 7228 u8 reserved_at_8[0x18]; 7229 7230 u8 syndrome[0x20]; 7231 7232 u8 reserved_at_40[0x40]; 7233 }; 7234 7235 struct mlx5_ifc_modify_sq_in_bits { 7236 u8 opcode[0x10]; 7237 u8 uid[0x10]; 7238 7239 u8 reserved_at_20[0x10]; 7240 u8 op_mod[0x10]; 7241 7242 u8 sq_state[0x4]; 7243 u8 reserved_at_44[0x4]; 7244 u8 sqn[0x18]; 7245 7246 u8 reserved_at_60[0x20]; 7247 7248 u8 modify_bitmask[0x40]; 7249 7250 u8 reserved_at_c0[0x40]; 7251 7252 struct mlx5_ifc_sqc_bits ctx; 7253 }; 7254 7255 struct mlx5_ifc_modify_scheduling_element_out_bits { 7256 u8 status[0x8]; 7257 u8 reserved_at_8[0x18]; 7258 7259 u8 syndrome[0x20]; 7260 7261 u8 reserved_at_40[0x1c0]; 7262 }; 7263 7264 enum { 7265 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7266 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7267 }; 7268 7269 struct mlx5_ifc_modify_scheduling_element_in_bits { 7270 u8 opcode[0x10]; 7271 u8 reserved_at_10[0x10]; 7272 7273 u8 reserved_at_20[0x10]; 7274 u8 op_mod[0x10]; 7275 7276 u8 scheduling_hierarchy[0x8]; 7277 u8 reserved_at_48[0x18]; 7278 7279 u8 scheduling_element_id[0x20]; 7280 7281 u8 reserved_at_80[0x20]; 7282 7283 u8 modify_bitmask[0x20]; 7284 7285 u8 reserved_at_c0[0x40]; 7286 7287 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7288 7289 u8 reserved_at_300[0x100]; 7290 }; 7291 7292 struct mlx5_ifc_modify_rqt_out_bits { 7293 u8 status[0x8]; 7294 u8 reserved_at_8[0x18]; 7295 7296 u8 syndrome[0x20]; 7297 7298 u8 reserved_at_40[0x40]; 7299 }; 7300 7301 struct mlx5_ifc_rqt_bitmask_bits { 7302 u8 reserved_at_0[0x20]; 7303 7304 u8 reserved_at_20[0x1f]; 7305 u8 rqn_list[0x1]; 7306 }; 7307 7308 struct mlx5_ifc_modify_rqt_in_bits { 7309 u8 opcode[0x10]; 7310 u8 uid[0x10]; 7311 7312 u8 reserved_at_20[0x10]; 7313 u8 op_mod[0x10]; 7314 7315 u8 reserved_at_40[0x8]; 7316 u8 rqtn[0x18]; 7317 7318 u8 reserved_at_60[0x20]; 7319 7320 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7321 7322 u8 reserved_at_c0[0x40]; 7323 7324 struct mlx5_ifc_rqtc_bits ctx; 7325 }; 7326 7327 struct mlx5_ifc_modify_rq_out_bits { 7328 u8 status[0x8]; 7329 u8 reserved_at_8[0x18]; 7330 7331 u8 syndrome[0x20]; 7332 7333 u8 reserved_at_40[0x40]; 7334 }; 7335 7336 enum { 7337 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7338 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7339 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7340 }; 7341 7342 struct mlx5_ifc_modify_rq_in_bits { 7343 u8 opcode[0x10]; 7344 u8 uid[0x10]; 7345 7346 u8 reserved_at_20[0x10]; 7347 u8 op_mod[0x10]; 7348 7349 u8 rq_state[0x4]; 7350 u8 reserved_at_44[0x4]; 7351 u8 rqn[0x18]; 7352 7353 u8 reserved_at_60[0x20]; 7354 7355 u8 modify_bitmask[0x40]; 7356 7357 u8 reserved_at_c0[0x40]; 7358 7359 struct mlx5_ifc_rqc_bits ctx; 7360 }; 7361 7362 struct mlx5_ifc_modify_rmp_out_bits { 7363 u8 status[0x8]; 7364 u8 reserved_at_8[0x18]; 7365 7366 u8 syndrome[0x20]; 7367 7368 u8 reserved_at_40[0x40]; 7369 }; 7370 7371 struct mlx5_ifc_rmp_bitmask_bits { 7372 u8 reserved_at_0[0x20]; 7373 7374 u8 reserved_at_20[0x1f]; 7375 u8 lwm[0x1]; 7376 }; 7377 7378 struct mlx5_ifc_modify_rmp_in_bits { 7379 u8 opcode[0x10]; 7380 u8 uid[0x10]; 7381 7382 u8 reserved_at_20[0x10]; 7383 u8 op_mod[0x10]; 7384 7385 u8 rmp_state[0x4]; 7386 u8 reserved_at_44[0x4]; 7387 u8 rmpn[0x18]; 7388 7389 u8 reserved_at_60[0x20]; 7390 7391 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7392 7393 u8 reserved_at_c0[0x40]; 7394 7395 struct mlx5_ifc_rmpc_bits ctx; 7396 }; 7397 7398 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7399 u8 status[0x8]; 7400 u8 reserved_at_8[0x18]; 7401 7402 u8 syndrome[0x20]; 7403 7404 u8 reserved_at_40[0x40]; 7405 }; 7406 7407 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7408 u8 reserved_at_0[0x12]; 7409 u8 affiliation[0x1]; 7410 u8 reserved_at_13[0x1]; 7411 u8 disable_uc_local_lb[0x1]; 7412 u8 disable_mc_local_lb[0x1]; 7413 u8 node_guid[0x1]; 7414 u8 port_guid[0x1]; 7415 u8 min_inline[0x1]; 7416 u8 mtu[0x1]; 7417 u8 change_event[0x1]; 7418 u8 promisc[0x1]; 7419 u8 permanent_address[0x1]; 7420 u8 addresses_list[0x1]; 7421 u8 roce_en[0x1]; 7422 u8 reserved_at_1f[0x1]; 7423 }; 7424 7425 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7426 u8 opcode[0x10]; 7427 u8 reserved_at_10[0x10]; 7428 7429 u8 reserved_at_20[0x10]; 7430 u8 op_mod[0x10]; 7431 7432 u8 other_vport[0x1]; 7433 u8 reserved_at_41[0xf]; 7434 u8 vport_number[0x10]; 7435 7436 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7437 7438 u8 reserved_at_80[0x780]; 7439 7440 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7441 }; 7442 7443 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7444 u8 status[0x8]; 7445 u8 reserved_at_8[0x18]; 7446 7447 u8 syndrome[0x20]; 7448 7449 u8 reserved_at_40[0x40]; 7450 }; 7451 7452 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7453 u8 opcode[0x10]; 7454 u8 reserved_at_10[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 other_vport[0x1]; 7460 u8 reserved_at_41[0xb]; 7461 u8 port_num[0x4]; 7462 u8 vport_number[0x10]; 7463 7464 u8 reserved_at_60[0x20]; 7465 7466 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7467 }; 7468 7469 struct mlx5_ifc_modify_cq_out_bits { 7470 u8 status[0x8]; 7471 u8 reserved_at_8[0x18]; 7472 7473 u8 syndrome[0x20]; 7474 7475 u8 reserved_at_40[0x40]; 7476 }; 7477 7478 enum { 7479 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7480 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7481 }; 7482 7483 struct mlx5_ifc_modify_cq_in_bits { 7484 u8 opcode[0x10]; 7485 u8 uid[0x10]; 7486 7487 u8 reserved_at_20[0x10]; 7488 u8 op_mod[0x10]; 7489 7490 u8 reserved_at_40[0x8]; 7491 u8 cqn[0x18]; 7492 7493 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7494 7495 struct mlx5_ifc_cqc_bits cq_context; 7496 7497 u8 reserved_at_280[0x60]; 7498 7499 u8 cq_umem_valid[0x1]; 7500 u8 reserved_at_2e1[0x1f]; 7501 7502 u8 reserved_at_300[0x580]; 7503 7504 u8 pas[][0x40]; 7505 }; 7506 7507 struct mlx5_ifc_modify_cong_status_out_bits { 7508 u8 status[0x8]; 7509 u8 reserved_at_8[0x18]; 7510 7511 u8 syndrome[0x20]; 7512 7513 u8 reserved_at_40[0x40]; 7514 }; 7515 7516 struct mlx5_ifc_modify_cong_status_in_bits { 7517 u8 opcode[0x10]; 7518 u8 reserved_at_10[0x10]; 7519 7520 u8 reserved_at_20[0x10]; 7521 u8 op_mod[0x10]; 7522 7523 u8 reserved_at_40[0x18]; 7524 u8 priority[0x4]; 7525 u8 cong_protocol[0x4]; 7526 7527 u8 enable[0x1]; 7528 u8 tag_enable[0x1]; 7529 u8 reserved_at_62[0x1e]; 7530 }; 7531 7532 struct mlx5_ifc_modify_cong_params_out_bits { 7533 u8 status[0x8]; 7534 u8 reserved_at_8[0x18]; 7535 7536 u8 syndrome[0x20]; 7537 7538 u8 reserved_at_40[0x40]; 7539 }; 7540 7541 struct mlx5_ifc_modify_cong_params_in_bits { 7542 u8 opcode[0x10]; 7543 u8 reserved_at_10[0x10]; 7544 7545 u8 reserved_at_20[0x10]; 7546 u8 op_mod[0x10]; 7547 7548 u8 reserved_at_40[0x1c]; 7549 u8 cong_protocol[0x4]; 7550 7551 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7552 7553 u8 reserved_at_80[0x80]; 7554 7555 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7556 }; 7557 7558 struct mlx5_ifc_manage_pages_out_bits { 7559 u8 status[0x8]; 7560 u8 reserved_at_8[0x18]; 7561 7562 u8 syndrome[0x20]; 7563 7564 u8 output_num_entries[0x20]; 7565 7566 u8 reserved_at_60[0x20]; 7567 7568 u8 pas[][0x40]; 7569 }; 7570 7571 enum { 7572 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7573 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7574 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7575 }; 7576 7577 struct mlx5_ifc_manage_pages_in_bits { 7578 u8 opcode[0x10]; 7579 u8 reserved_at_10[0x10]; 7580 7581 u8 reserved_at_20[0x10]; 7582 u8 op_mod[0x10]; 7583 7584 u8 embedded_cpu_function[0x1]; 7585 u8 reserved_at_41[0xf]; 7586 u8 function_id[0x10]; 7587 7588 u8 input_num_entries[0x20]; 7589 7590 u8 pas[][0x40]; 7591 }; 7592 7593 struct mlx5_ifc_mad_ifc_out_bits { 7594 u8 status[0x8]; 7595 u8 reserved_at_8[0x18]; 7596 7597 u8 syndrome[0x20]; 7598 7599 u8 reserved_at_40[0x40]; 7600 7601 u8 response_mad_packet[256][0x8]; 7602 }; 7603 7604 struct mlx5_ifc_mad_ifc_in_bits { 7605 u8 opcode[0x10]; 7606 u8 reserved_at_10[0x10]; 7607 7608 u8 reserved_at_20[0x10]; 7609 u8 op_mod[0x10]; 7610 7611 u8 remote_lid[0x10]; 7612 u8 reserved_at_50[0x8]; 7613 u8 port[0x8]; 7614 7615 u8 reserved_at_60[0x20]; 7616 7617 u8 mad[256][0x8]; 7618 }; 7619 7620 struct mlx5_ifc_init_hca_out_bits { 7621 u8 status[0x8]; 7622 u8 reserved_at_8[0x18]; 7623 7624 u8 syndrome[0x20]; 7625 7626 u8 reserved_at_40[0x40]; 7627 }; 7628 7629 struct mlx5_ifc_init_hca_in_bits { 7630 u8 opcode[0x10]; 7631 u8 reserved_at_10[0x10]; 7632 7633 u8 reserved_at_20[0x10]; 7634 u8 op_mod[0x10]; 7635 7636 u8 reserved_at_40[0x20]; 7637 7638 u8 reserved_at_60[0x2]; 7639 u8 sw_vhca_id[0xe]; 7640 u8 reserved_at_70[0x10]; 7641 7642 u8 sw_owner_id[4][0x20]; 7643 }; 7644 7645 struct mlx5_ifc_init2rtr_qp_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_at_8[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_at_40[0x20]; 7652 u8 ece[0x20]; 7653 }; 7654 7655 struct mlx5_ifc_init2rtr_qp_in_bits { 7656 u8 opcode[0x10]; 7657 u8 uid[0x10]; 7658 7659 u8 reserved_at_20[0x10]; 7660 u8 op_mod[0x10]; 7661 7662 u8 reserved_at_40[0x8]; 7663 u8 qpn[0x18]; 7664 7665 u8 reserved_at_60[0x20]; 7666 7667 u8 opt_param_mask[0x20]; 7668 7669 u8 ece[0x20]; 7670 7671 struct mlx5_ifc_qpc_bits qpc; 7672 7673 u8 reserved_at_800[0x80]; 7674 }; 7675 7676 struct mlx5_ifc_init2init_qp_out_bits { 7677 u8 status[0x8]; 7678 u8 reserved_at_8[0x18]; 7679 7680 u8 syndrome[0x20]; 7681 7682 u8 reserved_at_40[0x20]; 7683 u8 ece[0x20]; 7684 }; 7685 7686 struct mlx5_ifc_init2init_qp_in_bits { 7687 u8 opcode[0x10]; 7688 u8 uid[0x10]; 7689 7690 u8 reserved_at_20[0x10]; 7691 u8 op_mod[0x10]; 7692 7693 u8 reserved_at_40[0x8]; 7694 u8 qpn[0x18]; 7695 7696 u8 reserved_at_60[0x20]; 7697 7698 u8 opt_param_mask[0x20]; 7699 7700 u8 ece[0x20]; 7701 7702 struct mlx5_ifc_qpc_bits qpc; 7703 7704 u8 reserved_at_800[0x80]; 7705 }; 7706 7707 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7708 u8 status[0x8]; 7709 u8 reserved_at_8[0x18]; 7710 7711 u8 syndrome[0x20]; 7712 7713 u8 reserved_at_40[0x40]; 7714 7715 u8 packet_headers_log[128][0x8]; 7716 7717 u8 packet_syndrome[64][0x8]; 7718 }; 7719 7720 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7721 u8 opcode[0x10]; 7722 u8 reserved_at_10[0x10]; 7723 7724 u8 reserved_at_20[0x10]; 7725 u8 op_mod[0x10]; 7726 7727 u8 reserved_at_40[0x40]; 7728 }; 7729 7730 struct mlx5_ifc_gen_eqe_in_bits { 7731 u8 opcode[0x10]; 7732 u8 reserved_at_10[0x10]; 7733 7734 u8 reserved_at_20[0x10]; 7735 u8 op_mod[0x10]; 7736 7737 u8 reserved_at_40[0x18]; 7738 u8 eq_number[0x8]; 7739 7740 u8 reserved_at_60[0x20]; 7741 7742 u8 eqe[64][0x8]; 7743 }; 7744 7745 struct mlx5_ifc_gen_eq_out_bits { 7746 u8 status[0x8]; 7747 u8 reserved_at_8[0x18]; 7748 7749 u8 syndrome[0x20]; 7750 7751 u8 reserved_at_40[0x40]; 7752 }; 7753 7754 struct mlx5_ifc_enable_hca_out_bits { 7755 u8 status[0x8]; 7756 u8 reserved_at_8[0x18]; 7757 7758 u8 syndrome[0x20]; 7759 7760 u8 reserved_at_40[0x20]; 7761 }; 7762 7763 struct mlx5_ifc_enable_hca_in_bits { 7764 u8 opcode[0x10]; 7765 u8 reserved_at_10[0x10]; 7766 7767 u8 reserved_at_20[0x10]; 7768 u8 op_mod[0x10]; 7769 7770 u8 embedded_cpu_function[0x1]; 7771 u8 reserved_at_41[0xf]; 7772 u8 function_id[0x10]; 7773 7774 u8 reserved_at_60[0x20]; 7775 }; 7776 7777 struct mlx5_ifc_drain_dct_out_bits { 7778 u8 status[0x8]; 7779 u8 reserved_at_8[0x18]; 7780 7781 u8 syndrome[0x20]; 7782 7783 u8 reserved_at_40[0x40]; 7784 }; 7785 7786 struct mlx5_ifc_drain_dct_in_bits { 7787 u8 opcode[0x10]; 7788 u8 uid[0x10]; 7789 7790 u8 reserved_at_20[0x10]; 7791 u8 op_mod[0x10]; 7792 7793 u8 reserved_at_40[0x8]; 7794 u8 dctn[0x18]; 7795 7796 u8 reserved_at_60[0x20]; 7797 }; 7798 7799 struct mlx5_ifc_disable_hca_out_bits { 7800 u8 status[0x8]; 7801 u8 reserved_at_8[0x18]; 7802 7803 u8 syndrome[0x20]; 7804 7805 u8 reserved_at_40[0x20]; 7806 }; 7807 7808 struct mlx5_ifc_disable_hca_in_bits { 7809 u8 opcode[0x10]; 7810 u8 reserved_at_10[0x10]; 7811 7812 u8 reserved_at_20[0x10]; 7813 u8 op_mod[0x10]; 7814 7815 u8 embedded_cpu_function[0x1]; 7816 u8 reserved_at_41[0xf]; 7817 u8 function_id[0x10]; 7818 7819 u8 reserved_at_60[0x20]; 7820 }; 7821 7822 struct mlx5_ifc_detach_from_mcg_out_bits { 7823 u8 status[0x8]; 7824 u8 reserved_at_8[0x18]; 7825 7826 u8 syndrome[0x20]; 7827 7828 u8 reserved_at_40[0x40]; 7829 }; 7830 7831 struct mlx5_ifc_detach_from_mcg_in_bits { 7832 u8 opcode[0x10]; 7833 u8 uid[0x10]; 7834 7835 u8 reserved_at_20[0x10]; 7836 u8 op_mod[0x10]; 7837 7838 u8 reserved_at_40[0x8]; 7839 u8 qpn[0x18]; 7840 7841 u8 reserved_at_60[0x20]; 7842 7843 u8 multicast_gid[16][0x8]; 7844 }; 7845 7846 struct mlx5_ifc_destroy_xrq_out_bits { 7847 u8 status[0x8]; 7848 u8 reserved_at_8[0x18]; 7849 7850 u8 syndrome[0x20]; 7851 7852 u8 reserved_at_40[0x40]; 7853 }; 7854 7855 struct mlx5_ifc_destroy_xrq_in_bits { 7856 u8 opcode[0x10]; 7857 u8 uid[0x10]; 7858 7859 u8 reserved_at_20[0x10]; 7860 u8 op_mod[0x10]; 7861 7862 u8 reserved_at_40[0x8]; 7863 u8 xrqn[0x18]; 7864 7865 u8 reserved_at_60[0x20]; 7866 }; 7867 7868 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7869 u8 status[0x8]; 7870 u8 reserved_at_8[0x18]; 7871 7872 u8 syndrome[0x20]; 7873 7874 u8 reserved_at_40[0x40]; 7875 }; 7876 7877 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7878 u8 opcode[0x10]; 7879 u8 uid[0x10]; 7880 7881 u8 reserved_at_20[0x10]; 7882 u8 op_mod[0x10]; 7883 7884 u8 reserved_at_40[0x8]; 7885 u8 xrc_srqn[0x18]; 7886 7887 u8 reserved_at_60[0x20]; 7888 }; 7889 7890 struct mlx5_ifc_destroy_tis_out_bits { 7891 u8 status[0x8]; 7892 u8 reserved_at_8[0x18]; 7893 7894 u8 syndrome[0x20]; 7895 7896 u8 reserved_at_40[0x40]; 7897 }; 7898 7899 struct mlx5_ifc_destroy_tis_in_bits { 7900 u8 opcode[0x10]; 7901 u8 uid[0x10]; 7902 7903 u8 reserved_at_20[0x10]; 7904 u8 op_mod[0x10]; 7905 7906 u8 reserved_at_40[0x8]; 7907 u8 tisn[0x18]; 7908 7909 u8 reserved_at_60[0x20]; 7910 }; 7911 7912 struct mlx5_ifc_destroy_tir_out_bits { 7913 u8 status[0x8]; 7914 u8 reserved_at_8[0x18]; 7915 7916 u8 syndrome[0x20]; 7917 7918 u8 reserved_at_40[0x40]; 7919 }; 7920 7921 struct mlx5_ifc_destroy_tir_in_bits { 7922 u8 opcode[0x10]; 7923 u8 uid[0x10]; 7924 7925 u8 reserved_at_20[0x10]; 7926 u8 op_mod[0x10]; 7927 7928 u8 reserved_at_40[0x8]; 7929 u8 tirn[0x18]; 7930 7931 u8 reserved_at_60[0x20]; 7932 }; 7933 7934 struct mlx5_ifc_destroy_srq_out_bits { 7935 u8 status[0x8]; 7936 u8 reserved_at_8[0x18]; 7937 7938 u8 syndrome[0x20]; 7939 7940 u8 reserved_at_40[0x40]; 7941 }; 7942 7943 struct mlx5_ifc_destroy_srq_in_bits { 7944 u8 opcode[0x10]; 7945 u8 uid[0x10]; 7946 7947 u8 reserved_at_20[0x10]; 7948 u8 op_mod[0x10]; 7949 7950 u8 reserved_at_40[0x8]; 7951 u8 srqn[0x18]; 7952 7953 u8 reserved_at_60[0x20]; 7954 }; 7955 7956 struct mlx5_ifc_destroy_sq_out_bits { 7957 u8 status[0x8]; 7958 u8 reserved_at_8[0x18]; 7959 7960 u8 syndrome[0x20]; 7961 7962 u8 reserved_at_40[0x40]; 7963 }; 7964 7965 struct mlx5_ifc_destroy_sq_in_bits { 7966 u8 opcode[0x10]; 7967 u8 uid[0x10]; 7968 7969 u8 reserved_at_20[0x10]; 7970 u8 op_mod[0x10]; 7971 7972 u8 reserved_at_40[0x8]; 7973 u8 sqn[0x18]; 7974 7975 u8 reserved_at_60[0x20]; 7976 }; 7977 7978 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7979 u8 status[0x8]; 7980 u8 reserved_at_8[0x18]; 7981 7982 u8 syndrome[0x20]; 7983 7984 u8 reserved_at_40[0x1c0]; 7985 }; 7986 7987 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7988 u8 opcode[0x10]; 7989 u8 reserved_at_10[0x10]; 7990 7991 u8 reserved_at_20[0x10]; 7992 u8 op_mod[0x10]; 7993 7994 u8 scheduling_hierarchy[0x8]; 7995 u8 reserved_at_48[0x18]; 7996 7997 u8 scheduling_element_id[0x20]; 7998 7999 u8 reserved_at_80[0x180]; 8000 }; 8001 8002 struct mlx5_ifc_destroy_rqt_out_bits { 8003 u8 status[0x8]; 8004 u8 reserved_at_8[0x18]; 8005 8006 u8 syndrome[0x20]; 8007 8008 u8 reserved_at_40[0x40]; 8009 }; 8010 8011 struct mlx5_ifc_destroy_rqt_in_bits { 8012 u8 opcode[0x10]; 8013 u8 uid[0x10]; 8014 8015 u8 reserved_at_20[0x10]; 8016 u8 op_mod[0x10]; 8017 8018 u8 reserved_at_40[0x8]; 8019 u8 rqtn[0x18]; 8020 8021 u8 reserved_at_60[0x20]; 8022 }; 8023 8024 struct mlx5_ifc_destroy_rq_out_bits { 8025 u8 status[0x8]; 8026 u8 reserved_at_8[0x18]; 8027 8028 u8 syndrome[0x20]; 8029 8030 u8 reserved_at_40[0x40]; 8031 }; 8032 8033 struct mlx5_ifc_destroy_rq_in_bits { 8034 u8 opcode[0x10]; 8035 u8 uid[0x10]; 8036 8037 u8 reserved_at_20[0x10]; 8038 u8 op_mod[0x10]; 8039 8040 u8 reserved_at_40[0x8]; 8041 u8 rqn[0x18]; 8042 8043 u8 reserved_at_60[0x20]; 8044 }; 8045 8046 struct mlx5_ifc_set_delay_drop_params_in_bits { 8047 u8 opcode[0x10]; 8048 u8 reserved_at_10[0x10]; 8049 8050 u8 reserved_at_20[0x10]; 8051 u8 op_mod[0x10]; 8052 8053 u8 reserved_at_40[0x20]; 8054 8055 u8 reserved_at_60[0x10]; 8056 u8 delay_drop_timeout[0x10]; 8057 }; 8058 8059 struct mlx5_ifc_set_delay_drop_params_out_bits { 8060 u8 status[0x8]; 8061 u8 reserved_at_8[0x18]; 8062 8063 u8 syndrome[0x20]; 8064 8065 u8 reserved_at_40[0x40]; 8066 }; 8067 8068 struct mlx5_ifc_destroy_rmp_out_bits { 8069 u8 status[0x8]; 8070 u8 reserved_at_8[0x18]; 8071 8072 u8 syndrome[0x20]; 8073 8074 u8 reserved_at_40[0x40]; 8075 }; 8076 8077 struct mlx5_ifc_destroy_rmp_in_bits { 8078 u8 opcode[0x10]; 8079 u8 uid[0x10]; 8080 8081 u8 reserved_at_20[0x10]; 8082 u8 op_mod[0x10]; 8083 8084 u8 reserved_at_40[0x8]; 8085 u8 rmpn[0x18]; 8086 8087 u8 reserved_at_60[0x20]; 8088 }; 8089 8090 struct mlx5_ifc_destroy_qp_out_bits { 8091 u8 status[0x8]; 8092 u8 reserved_at_8[0x18]; 8093 8094 u8 syndrome[0x20]; 8095 8096 u8 reserved_at_40[0x40]; 8097 }; 8098 8099 struct mlx5_ifc_destroy_qp_in_bits { 8100 u8 opcode[0x10]; 8101 u8 uid[0x10]; 8102 8103 u8 reserved_at_20[0x10]; 8104 u8 op_mod[0x10]; 8105 8106 u8 reserved_at_40[0x8]; 8107 u8 qpn[0x18]; 8108 8109 u8 reserved_at_60[0x20]; 8110 }; 8111 8112 struct mlx5_ifc_destroy_psv_out_bits { 8113 u8 status[0x8]; 8114 u8 reserved_at_8[0x18]; 8115 8116 u8 syndrome[0x20]; 8117 8118 u8 reserved_at_40[0x40]; 8119 }; 8120 8121 struct mlx5_ifc_destroy_psv_in_bits { 8122 u8 opcode[0x10]; 8123 u8 reserved_at_10[0x10]; 8124 8125 u8 reserved_at_20[0x10]; 8126 u8 op_mod[0x10]; 8127 8128 u8 reserved_at_40[0x8]; 8129 u8 psvn[0x18]; 8130 8131 u8 reserved_at_60[0x20]; 8132 }; 8133 8134 struct mlx5_ifc_destroy_mkey_out_bits { 8135 u8 status[0x8]; 8136 u8 reserved_at_8[0x18]; 8137 8138 u8 syndrome[0x20]; 8139 8140 u8 reserved_at_40[0x40]; 8141 }; 8142 8143 struct mlx5_ifc_destroy_mkey_in_bits { 8144 u8 opcode[0x10]; 8145 u8 uid[0x10]; 8146 8147 u8 reserved_at_20[0x10]; 8148 u8 op_mod[0x10]; 8149 8150 u8 reserved_at_40[0x8]; 8151 u8 mkey_index[0x18]; 8152 8153 u8 reserved_at_60[0x20]; 8154 }; 8155 8156 struct mlx5_ifc_destroy_flow_table_out_bits { 8157 u8 status[0x8]; 8158 u8 reserved_at_8[0x18]; 8159 8160 u8 syndrome[0x20]; 8161 8162 u8 reserved_at_40[0x40]; 8163 }; 8164 8165 struct mlx5_ifc_destroy_flow_table_in_bits { 8166 u8 opcode[0x10]; 8167 u8 reserved_at_10[0x10]; 8168 8169 u8 reserved_at_20[0x10]; 8170 u8 op_mod[0x10]; 8171 8172 u8 other_vport[0x1]; 8173 u8 reserved_at_41[0xf]; 8174 u8 vport_number[0x10]; 8175 8176 u8 reserved_at_60[0x20]; 8177 8178 u8 table_type[0x8]; 8179 u8 reserved_at_88[0x18]; 8180 8181 u8 reserved_at_a0[0x8]; 8182 u8 table_id[0x18]; 8183 8184 u8 reserved_at_c0[0x140]; 8185 }; 8186 8187 struct mlx5_ifc_destroy_flow_group_out_bits { 8188 u8 status[0x8]; 8189 u8 reserved_at_8[0x18]; 8190 8191 u8 syndrome[0x20]; 8192 8193 u8 reserved_at_40[0x40]; 8194 }; 8195 8196 struct mlx5_ifc_destroy_flow_group_in_bits { 8197 u8 opcode[0x10]; 8198 u8 reserved_at_10[0x10]; 8199 8200 u8 reserved_at_20[0x10]; 8201 u8 op_mod[0x10]; 8202 8203 u8 other_vport[0x1]; 8204 u8 reserved_at_41[0xf]; 8205 u8 vport_number[0x10]; 8206 8207 u8 reserved_at_60[0x20]; 8208 8209 u8 table_type[0x8]; 8210 u8 reserved_at_88[0x18]; 8211 8212 u8 reserved_at_a0[0x8]; 8213 u8 table_id[0x18]; 8214 8215 u8 group_id[0x20]; 8216 8217 u8 reserved_at_e0[0x120]; 8218 }; 8219 8220 struct mlx5_ifc_destroy_eq_out_bits { 8221 u8 status[0x8]; 8222 u8 reserved_at_8[0x18]; 8223 8224 u8 syndrome[0x20]; 8225 8226 u8 reserved_at_40[0x40]; 8227 }; 8228 8229 struct mlx5_ifc_destroy_eq_in_bits { 8230 u8 opcode[0x10]; 8231 u8 reserved_at_10[0x10]; 8232 8233 u8 reserved_at_20[0x10]; 8234 u8 op_mod[0x10]; 8235 8236 u8 reserved_at_40[0x18]; 8237 u8 eq_number[0x8]; 8238 8239 u8 reserved_at_60[0x20]; 8240 }; 8241 8242 struct mlx5_ifc_destroy_dct_out_bits { 8243 u8 status[0x8]; 8244 u8 reserved_at_8[0x18]; 8245 8246 u8 syndrome[0x20]; 8247 8248 u8 reserved_at_40[0x40]; 8249 }; 8250 8251 struct mlx5_ifc_destroy_dct_in_bits { 8252 u8 opcode[0x10]; 8253 u8 uid[0x10]; 8254 8255 u8 reserved_at_20[0x10]; 8256 u8 op_mod[0x10]; 8257 8258 u8 reserved_at_40[0x8]; 8259 u8 dctn[0x18]; 8260 8261 u8 reserved_at_60[0x20]; 8262 }; 8263 8264 struct mlx5_ifc_destroy_cq_out_bits { 8265 u8 status[0x8]; 8266 u8 reserved_at_8[0x18]; 8267 8268 u8 syndrome[0x20]; 8269 8270 u8 reserved_at_40[0x40]; 8271 }; 8272 8273 struct mlx5_ifc_destroy_cq_in_bits { 8274 u8 opcode[0x10]; 8275 u8 uid[0x10]; 8276 8277 u8 reserved_at_20[0x10]; 8278 u8 op_mod[0x10]; 8279 8280 u8 reserved_at_40[0x8]; 8281 u8 cqn[0x18]; 8282 8283 u8 reserved_at_60[0x20]; 8284 }; 8285 8286 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8287 u8 status[0x8]; 8288 u8 reserved_at_8[0x18]; 8289 8290 u8 syndrome[0x20]; 8291 8292 u8 reserved_at_40[0x40]; 8293 }; 8294 8295 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8296 u8 opcode[0x10]; 8297 u8 reserved_at_10[0x10]; 8298 8299 u8 reserved_at_20[0x10]; 8300 u8 op_mod[0x10]; 8301 8302 u8 reserved_at_40[0x20]; 8303 8304 u8 reserved_at_60[0x10]; 8305 u8 vxlan_udp_port[0x10]; 8306 }; 8307 8308 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8309 u8 status[0x8]; 8310 u8 reserved_at_8[0x18]; 8311 8312 u8 syndrome[0x20]; 8313 8314 u8 reserved_at_40[0x40]; 8315 }; 8316 8317 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8318 u8 opcode[0x10]; 8319 u8 reserved_at_10[0x10]; 8320 8321 u8 reserved_at_20[0x10]; 8322 u8 op_mod[0x10]; 8323 8324 u8 reserved_at_40[0x60]; 8325 8326 u8 reserved_at_a0[0x8]; 8327 u8 table_index[0x18]; 8328 8329 u8 reserved_at_c0[0x140]; 8330 }; 8331 8332 struct mlx5_ifc_delete_fte_out_bits { 8333 u8 status[0x8]; 8334 u8 reserved_at_8[0x18]; 8335 8336 u8 syndrome[0x20]; 8337 8338 u8 reserved_at_40[0x40]; 8339 }; 8340 8341 struct mlx5_ifc_delete_fte_in_bits { 8342 u8 opcode[0x10]; 8343 u8 reserved_at_10[0x10]; 8344 8345 u8 reserved_at_20[0x10]; 8346 u8 op_mod[0x10]; 8347 8348 u8 other_vport[0x1]; 8349 u8 reserved_at_41[0xf]; 8350 u8 vport_number[0x10]; 8351 8352 u8 reserved_at_60[0x20]; 8353 8354 u8 table_type[0x8]; 8355 u8 reserved_at_88[0x18]; 8356 8357 u8 reserved_at_a0[0x8]; 8358 u8 table_id[0x18]; 8359 8360 u8 reserved_at_c0[0x40]; 8361 8362 u8 flow_index[0x20]; 8363 8364 u8 reserved_at_120[0xe0]; 8365 }; 8366 8367 struct mlx5_ifc_dealloc_xrcd_out_bits { 8368 u8 status[0x8]; 8369 u8 reserved_at_8[0x18]; 8370 8371 u8 syndrome[0x20]; 8372 8373 u8 reserved_at_40[0x40]; 8374 }; 8375 8376 struct mlx5_ifc_dealloc_xrcd_in_bits { 8377 u8 opcode[0x10]; 8378 u8 uid[0x10]; 8379 8380 u8 reserved_at_20[0x10]; 8381 u8 op_mod[0x10]; 8382 8383 u8 reserved_at_40[0x8]; 8384 u8 xrcd[0x18]; 8385 8386 u8 reserved_at_60[0x20]; 8387 }; 8388 8389 struct mlx5_ifc_dealloc_uar_out_bits { 8390 u8 status[0x8]; 8391 u8 reserved_at_8[0x18]; 8392 8393 u8 syndrome[0x20]; 8394 8395 u8 reserved_at_40[0x40]; 8396 }; 8397 8398 struct mlx5_ifc_dealloc_uar_in_bits { 8399 u8 opcode[0x10]; 8400 u8 uid[0x10]; 8401 8402 u8 reserved_at_20[0x10]; 8403 u8 op_mod[0x10]; 8404 8405 u8 reserved_at_40[0x8]; 8406 u8 uar[0x18]; 8407 8408 u8 reserved_at_60[0x20]; 8409 }; 8410 8411 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8412 u8 status[0x8]; 8413 u8 reserved_at_8[0x18]; 8414 8415 u8 syndrome[0x20]; 8416 8417 u8 reserved_at_40[0x40]; 8418 }; 8419 8420 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8421 u8 opcode[0x10]; 8422 u8 uid[0x10]; 8423 8424 u8 reserved_at_20[0x10]; 8425 u8 op_mod[0x10]; 8426 8427 u8 reserved_at_40[0x8]; 8428 u8 transport_domain[0x18]; 8429 8430 u8 reserved_at_60[0x20]; 8431 }; 8432 8433 struct mlx5_ifc_dealloc_q_counter_out_bits { 8434 u8 status[0x8]; 8435 u8 reserved_at_8[0x18]; 8436 8437 u8 syndrome[0x20]; 8438 8439 u8 reserved_at_40[0x40]; 8440 }; 8441 8442 struct mlx5_ifc_dealloc_q_counter_in_bits { 8443 u8 opcode[0x10]; 8444 u8 reserved_at_10[0x10]; 8445 8446 u8 reserved_at_20[0x10]; 8447 u8 op_mod[0x10]; 8448 8449 u8 reserved_at_40[0x18]; 8450 u8 counter_set_id[0x8]; 8451 8452 u8 reserved_at_60[0x20]; 8453 }; 8454 8455 struct mlx5_ifc_dealloc_pd_out_bits { 8456 u8 status[0x8]; 8457 u8 reserved_at_8[0x18]; 8458 8459 u8 syndrome[0x20]; 8460 8461 u8 reserved_at_40[0x40]; 8462 }; 8463 8464 struct mlx5_ifc_dealloc_pd_in_bits { 8465 u8 opcode[0x10]; 8466 u8 uid[0x10]; 8467 8468 u8 reserved_at_20[0x10]; 8469 u8 op_mod[0x10]; 8470 8471 u8 reserved_at_40[0x8]; 8472 u8 pd[0x18]; 8473 8474 u8 reserved_at_60[0x20]; 8475 }; 8476 8477 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8478 u8 status[0x8]; 8479 u8 reserved_at_8[0x18]; 8480 8481 u8 syndrome[0x20]; 8482 8483 u8 reserved_at_40[0x40]; 8484 }; 8485 8486 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8487 u8 opcode[0x10]; 8488 u8 reserved_at_10[0x10]; 8489 8490 u8 reserved_at_20[0x10]; 8491 u8 op_mod[0x10]; 8492 8493 u8 flow_counter_id[0x20]; 8494 8495 u8 reserved_at_60[0x20]; 8496 }; 8497 8498 struct mlx5_ifc_create_xrq_out_bits { 8499 u8 status[0x8]; 8500 u8 reserved_at_8[0x18]; 8501 8502 u8 syndrome[0x20]; 8503 8504 u8 reserved_at_40[0x8]; 8505 u8 xrqn[0x18]; 8506 8507 u8 reserved_at_60[0x20]; 8508 }; 8509 8510 struct mlx5_ifc_create_xrq_in_bits { 8511 u8 opcode[0x10]; 8512 u8 uid[0x10]; 8513 8514 u8 reserved_at_20[0x10]; 8515 u8 op_mod[0x10]; 8516 8517 u8 reserved_at_40[0x40]; 8518 8519 struct mlx5_ifc_xrqc_bits xrq_context; 8520 }; 8521 8522 struct mlx5_ifc_create_xrc_srq_out_bits { 8523 u8 status[0x8]; 8524 u8 reserved_at_8[0x18]; 8525 8526 u8 syndrome[0x20]; 8527 8528 u8 reserved_at_40[0x8]; 8529 u8 xrc_srqn[0x18]; 8530 8531 u8 reserved_at_60[0x20]; 8532 }; 8533 8534 struct mlx5_ifc_create_xrc_srq_in_bits { 8535 u8 opcode[0x10]; 8536 u8 uid[0x10]; 8537 8538 u8 reserved_at_20[0x10]; 8539 u8 op_mod[0x10]; 8540 8541 u8 reserved_at_40[0x40]; 8542 8543 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8544 8545 u8 reserved_at_280[0x60]; 8546 8547 u8 xrc_srq_umem_valid[0x1]; 8548 u8 reserved_at_2e1[0x1f]; 8549 8550 u8 reserved_at_300[0x580]; 8551 8552 u8 pas[][0x40]; 8553 }; 8554 8555 struct mlx5_ifc_create_tis_out_bits { 8556 u8 status[0x8]; 8557 u8 reserved_at_8[0x18]; 8558 8559 u8 syndrome[0x20]; 8560 8561 u8 reserved_at_40[0x8]; 8562 u8 tisn[0x18]; 8563 8564 u8 reserved_at_60[0x20]; 8565 }; 8566 8567 struct mlx5_ifc_create_tis_in_bits { 8568 u8 opcode[0x10]; 8569 u8 uid[0x10]; 8570 8571 u8 reserved_at_20[0x10]; 8572 u8 op_mod[0x10]; 8573 8574 u8 reserved_at_40[0xc0]; 8575 8576 struct mlx5_ifc_tisc_bits ctx; 8577 }; 8578 8579 struct mlx5_ifc_create_tir_out_bits { 8580 u8 status[0x8]; 8581 u8 icm_address_63_40[0x18]; 8582 8583 u8 syndrome[0x20]; 8584 8585 u8 icm_address_39_32[0x8]; 8586 u8 tirn[0x18]; 8587 8588 u8 icm_address_31_0[0x20]; 8589 }; 8590 8591 struct mlx5_ifc_create_tir_in_bits { 8592 u8 opcode[0x10]; 8593 u8 uid[0x10]; 8594 8595 u8 reserved_at_20[0x10]; 8596 u8 op_mod[0x10]; 8597 8598 u8 reserved_at_40[0xc0]; 8599 8600 struct mlx5_ifc_tirc_bits ctx; 8601 }; 8602 8603 struct mlx5_ifc_create_srq_out_bits { 8604 u8 status[0x8]; 8605 u8 reserved_at_8[0x18]; 8606 8607 u8 syndrome[0x20]; 8608 8609 u8 reserved_at_40[0x8]; 8610 u8 srqn[0x18]; 8611 8612 u8 reserved_at_60[0x20]; 8613 }; 8614 8615 struct mlx5_ifc_create_srq_in_bits { 8616 u8 opcode[0x10]; 8617 u8 uid[0x10]; 8618 8619 u8 reserved_at_20[0x10]; 8620 u8 op_mod[0x10]; 8621 8622 u8 reserved_at_40[0x40]; 8623 8624 struct mlx5_ifc_srqc_bits srq_context_entry; 8625 8626 u8 reserved_at_280[0x600]; 8627 8628 u8 pas[][0x40]; 8629 }; 8630 8631 struct mlx5_ifc_create_sq_out_bits { 8632 u8 status[0x8]; 8633 u8 reserved_at_8[0x18]; 8634 8635 u8 syndrome[0x20]; 8636 8637 u8 reserved_at_40[0x8]; 8638 u8 sqn[0x18]; 8639 8640 u8 reserved_at_60[0x20]; 8641 }; 8642 8643 struct mlx5_ifc_create_sq_in_bits { 8644 u8 opcode[0x10]; 8645 u8 uid[0x10]; 8646 8647 u8 reserved_at_20[0x10]; 8648 u8 op_mod[0x10]; 8649 8650 u8 reserved_at_40[0xc0]; 8651 8652 struct mlx5_ifc_sqc_bits ctx; 8653 }; 8654 8655 struct mlx5_ifc_create_scheduling_element_out_bits { 8656 u8 status[0x8]; 8657 u8 reserved_at_8[0x18]; 8658 8659 u8 syndrome[0x20]; 8660 8661 u8 reserved_at_40[0x40]; 8662 8663 u8 scheduling_element_id[0x20]; 8664 8665 u8 reserved_at_a0[0x160]; 8666 }; 8667 8668 struct mlx5_ifc_create_scheduling_element_in_bits { 8669 u8 opcode[0x10]; 8670 u8 reserved_at_10[0x10]; 8671 8672 u8 reserved_at_20[0x10]; 8673 u8 op_mod[0x10]; 8674 8675 u8 scheduling_hierarchy[0x8]; 8676 u8 reserved_at_48[0x18]; 8677 8678 u8 reserved_at_60[0xa0]; 8679 8680 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8681 8682 u8 reserved_at_300[0x100]; 8683 }; 8684 8685 struct mlx5_ifc_create_rqt_out_bits { 8686 u8 status[0x8]; 8687 u8 reserved_at_8[0x18]; 8688 8689 u8 syndrome[0x20]; 8690 8691 u8 reserved_at_40[0x8]; 8692 u8 rqtn[0x18]; 8693 8694 u8 reserved_at_60[0x20]; 8695 }; 8696 8697 struct mlx5_ifc_create_rqt_in_bits { 8698 u8 opcode[0x10]; 8699 u8 uid[0x10]; 8700 8701 u8 reserved_at_20[0x10]; 8702 u8 op_mod[0x10]; 8703 8704 u8 reserved_at_40[0xc0]; 8705 8706 struct mlx5_ifc_rqtc_bits rqt_context; 8707 }; 8708 8709 struct mlx5_ifc_create_rq_out_bits { 8710 u8 status[0x8]; 8711 u8 reserved_at_8[0x18]; 8712 8713 u8 syndrome[0x20]; 8714 8715 u8 reserved_at_40[0x8]; 8716 u8 rqn[0x18]; 8717 8718 u8 reserved_at_60[0x20]; 8719 }; 8720 8721 struct mlx5_ifc_create_rq_in_bits { 8722 u8 opcode[0x10]; 8723 u8 uid[0x10]; 8724 8725 u8 reserved_at_20[0x10]; 8726 u8 op_mod[0x10]; 8727 8728 u8 reserved_at_40[0xc0]; 8729 8730 struct mlx5_ifc_rqc_bits ctx; 8731 }; 8732 8733 struct mlx5_ifc_create_rmp_out_bits { 8734 u8 status[0x8]; 8735 u8 reserved_at_8[0x18]; 8736 8737 u8 syndrome[0x20]; 8738 8739 u8 reserved_at_40[0x8]; 8740 u8 rmpn[0x18]; 8741 8742 u8 reserved_at_60[0x20]; 8743 }; 8744 8745 struct mlx5_ifc_create_rmp_in_bits { 8746 u8 opcode[0x10]; 8747 u8 uid[0x10]; 8748 8749 u8 reserved_at_20[0x10]; 8750 u8 op_mod[0x10]; 8751 8752 u8 reserved_at_40[0xc0]; 8753 8754 struct mlx5_ifc_rmpc_bits ctx; 8755 }; 8756 8757 struct mlx5_ifc_create_qp_out_bits { 8758 u8 status[0x8]; 8759 u8 reserved_at_8[0x18]; 8760 8761 u8 syndrome[0x20]; 8762 8763 u8 reserved_at_40[0x8]; 8764 u8 qpn[0x18]; 8765 8766 u8 ece[0x20]; 8767 }; 8768 8769 struct mlx5_ifc_create_qp_in_bits { 8770 u8 opcode[0x10]; 8771 u8 uid[0x10]; 8772 8773 u8 reserved_at_20[0x10]; 8774 u8 op_mod[0x10]; 8775 8776 u8 qpc_ext[0x1]; 8777 u8 reserved_at_41[0x7]; 8778 u8 input_qpn[0x18]; 8779 8780 u8 reserved_at_60[0x20]; 8781 u8 opt_param_mask[0x20]; 8782 8783 u8 ece[0x20]; 8784 8785 struct mlx5_ifc_qpc_bits qpc; 8786 8787 u8 reserved_at_800[0x60]; 8788 8789 u8 wq_umem_valid[0x1]; 8790 u8 reserved_at_861[0x1f]; 8791 8792 u8 pas[][0x40]; 8793 }; 8794 8795 struct mlx5_ifc_create_psv_out_bits { 8796 u8 status[0x8]; 8797 u8 reserved_at_8[0x18]; 8798 8799 u8 syndrome[0x20]; 8800 8801 u8 reserved_at_40[0x40]; 8802 8803 u8 reserved_at_80[0x8]; 8804 u8 psv0_index[0x18]; 8805 8806 u8 reserved_at_a0[0x8]; 8807 u8 psv1_index[0x18]; 8808 8809 u8 reserved_at_c0[0x8]; 8810 u8 psv2_index[0x18]; 8811 8812 u8 reserved_at_e0[0x8]; 8813 u8 psv3_index[0x18]; 8814 }; 8815 8816 struct mlx5_ifc_create_psv_in_bits { 8817 u8 opcode[0x10]; 8818 u8 reserved_at_10[0x10]; 8819 8820 u8 reserved_at_20[0x10]; 8821 u8 op_mod[0x10]; 8822 8823 u8 num_psv[0x4]; 8824 u8 reserved_at_44[0x4]; 8825 u8 pd[0x18]; 8826 8827 u8 reserved_at_60[0x20]; 8828 }; 8829 8830 struct mlx5_ifc_create_mkey_out_bits { 8831 u8 status[0x8]; 8832 u8 reserved_at_8[0x18]; 8833 8834 u8 syndrome[0x20]; 8835 8836 u8 reserved_at_40[0x8]; 8837 u8 mkey_index[0x18]; 8838 8839 u8 reserved_at_60[0x20]; 8840 }; 8841 8842 struct mlx5_ifc_create_mkey_in_bits { 8843 u8 opcode[0x10]; 8844 u8 uid[0x10]; 8845 8846 u8 reserved_at_20[0x10]; 8847 u8 op_mod[0x10]; 8848 8849 u8 reserved_at_40[0x20]; 8850 8851 u8 pg_access[0x1]; 8852 u8 mkey_umem_valid[0x1]; 8853 u8 reserved_at_62[0x1e]; 8854 8855 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8856 8857 u8 reserved_at_280[0x80]; 8858 8859 u8 translations_octword_actual_size[0x20]; 8860 8861 u8 reserved_at_320[0x560]; 8862 8863 u8 klm_pas_mtt[][0x20]; 8864 }; 8865 8866 enum { 8867 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8868 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8869 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8870 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8871 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8872 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8873 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8874 }; 8875 8876 struct mlx5_ifc_create_flow_table_out_bits { 8877 u8 status[0x8]; 8878 u8 icm_address_63_40[0x18]; 8879 8880 u8 syndrome[0x20]; 8881 8882 u8 icm_address_39_32[0x8]; 8883 u8 table_id[0x18]; 8884 8885 u8 icm_address_31_0[0x20]; 8886 }; 8887 8888 struct mlx5_ifc_create_flow_table_in_bits { 8889 u8 opcode[0x10]; 8890 u8 uid[0x10]; 8891 8892 u8 reserved_at_20[0x10]; 8893 u8 op_mod[0x10]; 8894 8895 u8 other_vport[0x1]; 8896 u8 reserved_at_41[0xf]; 8897 u8 vport_number[0x10]; 8898 8899 u8 reserved_at_60[0x20]; 8900 8901 u8 table_type[0x8]; 8902 u8 reserved_at_88[0x18]; 8903 8904 u8 reserved_at_a0[0x20]; 8905 8906 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8907 }; 8908 8909 struct mlx5_ifc_create_flow_group_out_bits { 8910 u8 status[0x8]; 8911 u8 reserved_at_8[0x18]; 8912 8913 u8 syndrome[0x20]; 8914 8915 u8 reserved_at_40[0x8]; 8916 u8 group_id[0x18]; 8917 8918 u8 reserved_at_60[0x20]; 8919 }; 8920 8921 enum { 8922 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8923 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8924 }; 8925 8926 enum { 8927 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8928 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8929 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8930 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8931 }; 8932 8933 struct mlx5_ifc_create_flow_group_in_bits { 8934 u8 opcode[0x10]; 8935 u8 reserved_at_10[0x10]; 8936 8937 u8 reserved_at_20[0x10]; 8938 u8 op_mod[0x10]; 8939 8940 u8 other_vport[0x1]; 8941 u8 reserved_at_41[0xf]; 8942 u8 vport_number[0x10]; 8943 8944 u8 reserved_at_60[0x20]; 8945 8946 u8 table_type[0x8]; 8947 u8 reserved_at_88[0x4]; 8948 u8 group_type[0x4]; 8949 u8 reserved_at_90[0x10]; 8950 8951 u8 reserved_at_a0[0x8]; 8952 u8 table_id[0x18]; 8953 8954 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8955 8956 u8 reserved_at_c1[0x1f]; 8957 8958 u8 start_flow_index[0x20]; 8959 8960 u8 reserved_at_100[0x20]; 8961 8962 u8 end_flow_index[0x20]; 8963 8964 u8 reserved_at_140[0x10]; 8965 u8 match_definer_id[0x10]; 8966 8967 u8 reserved_at_160[0x80]; 8968 8969 u8 reserved_at_1e0[0x18]; 8970 u8 match_criteria_enable[0x8]; 8971 8972 struct mlx5_ifc_fte_match_param_bits match_criteria; 8973 8974 u8 reserved_at_1200[0xe00]; 8975 }; 8976 8977 struct mlx5_ifc_create_eq_out_bits { 8978 u8 status[0x8]; 8979 u8 reserved_at_8[0x18]; 8980 8981 u8 syndrome[0x20]; 8982 8983 u8 reserved_at_40[0x18]; 8984 u8 eq_number[0x8]; 8985 8986 u8 reserved_at_60[0x20]; 8987 }; 8988 8989 struct mlx5_ifc_create_eq_in_bits { 8990 u8 opcode[0x10]; 8991 u8 uid[0x10]; 8992 8993 u8 reserved_at_20[0x10]; 8994 u8 op_mod[0x10]; 8995 8996 u8 reserved_at_40[0x40]; 8997 8998 struct mlx5_ifc_eqc_bits eq_context_entry; 8999 9000 u8 reserved_at_280[0x40]; 9001 9002 u8 event_bitmask[4][0x40]; 9003 9004 u8 reserved_at_3c0[0x4c0]; 9005 9006 u8 pas[][0x40]; 9007 }; 9008 9009 struct mlx5_ifc_create_dct_out_bits { 9010 u8 status[0x8]; 9011 u8 reserved_at_8[0x18]; 9012 9013 u8 syndrome[0x20]; 9014 9015 u8 reserved_at_40[0x8]; 9016 u8 dctn[0x18]; 9017 9018 u8 ece[0x20]; 9019 }; 9020 9021 struct mlx5_ifc_create_dct_in_bits { 9022 u8 opcode[0x10]; 9023 u8 uid[0x10]; 9024 9025 u8 reserved_at_20[0x10]; 9026 u8 op_mod[0x10]; 9027 9028 u8 reserved_at_40[0x40]; 9029 9030 struct mlx5_ifc_dctc_bits dct_context_entry; 9031 9032 u8 reserved_at_280[0x180]; 9033 }; 9034 9035 struct mlx5_ifc_create_cq_out_bits { 9036 u8 status[0x8]; 9037 u8 reserved_at_8[0x18]; 9038 9039 u8 syndrome[0x20]; 9040 9041 u8 reserved_at_40[0x8]; 9042 u8 cqn[0x18]; 9043 9044 u8 reserved_at_60[0x20]; 9045 }; 9046 9047 struct mlx5_ifc_create_cq_in_bits { 9048 u8 opcode[0x10]; 9049 u8 uid[0x10]; 9050 9051 u8 reserved_at_20[0x10]; 9052 u8 op_mod[0x10]; 9053 9054 u8 reserved_at_40[0x40]; 9055 9056 struct mlx5_ifc_cqc_bits cq_context; 9057 9058 u8 reserved_at_280[0x60]; 9059 9060 u8 cq_umem_valid[0x1]; 9061 u8 reserved_at_2e1[0x59f]; 9062 9063 u8 pas[][0x40]; 9064 }; 9065 9066 struct mlx5_ifc_config_int_moderation_out_bits { 9067 u8 status[0x8]; 9068 u8 reserved_at_8[0x18]; 9069 9070 u8 syndrome[0x20]; 9071 9072 u8 reserved_at_40[0x4]; 9073 u8 min_delay[0xc]; 9074 u8 int_vector[0x10]; 9075 9076 u8 reserved_at_60[0x20]; 9077 }; 9078 9079 enum { 9080 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9081 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9082 }; 9083 9084 struct mlx5_ifc_config_int_moderation_in_bits { 9085 u8 opcode[0x10]; 9086 u8 reserved_at_10[0x10]; 9087 9088 u8 reserved_at_20[0x10]; 9089 u8 op_mod[0x10]; 9090 9091 u8 reserved_at_40[0x4]; 9092 u8 min_delay[0xc]; 9093 u8 int_vector[0x10]; 9094 9095 u8 reserved_at_60[0x20]; 9096 }; 9097 9098 struct mlx5_ifc_attach_to_mcg_out_bits { 9099 u8 status[0x8]; 9100 u8 reserved_at_8[0x18]; 9101 9102 u8 syndrome[0x20]; 9103 9104 u8 reserved_at_40[0x40]; 9105 }; 9106 9107 struct mlx5_ifc_attach_to_mcg_in_bits { 9108 u8 opcode[0x10]; 9109 u8 uid[0x10]; 9110 9111 u8 reserved_at_20[0x10]; 9112 u8 op_mod[0x10]; 9113 9114 u8 reserved_at_40[0x8]; 9115 u8 qpn[0x18]; 9116 9117 u8 reserved_at_60[0x20]; 9118 9119 u8 multicast_gid[16][0x8]; 9120 }; 9121 9122 struct mlx5_ifc_arm_xrq_out_bits { 9123 u8 status[0x8]; 9124 u8 reserved_at_8[0x18]; 9125 9126 u8 syndrome[0x20]; 9127 9128 u8 reserved_at_40[0x40]; 9129 }; 9130 9131 struct mlx5_ifc_arm_xrq_in_bits { 9132 u8 opcode[0x10]; 9133 u8 reserved_at_10[0x10]; 9134 9135 u8 reserved_at_20[0x10]; 9136 u8 op_mod[0x10]; 9137 9138 u8 reserved_at_40[0x8]; 9139 u8 xrqn[0x18]; 9140 9141 u8 reserved_at_60[0x10]; 9142 u8 lwm[0x10]; 9143 }; 9144 9145 struct mlx5_ifc_arm_xrc_srq_out_bits { 9146 u8 status[0x8]; 9147 u8 reserved_at_8[0x18]; 9148 9149 u8 syndrome[0x20]; 9150 9151 u8 reserved_at_40[0x40]; 9152 }; 9153 9154 enum { 9155 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9156 }; 9157 9158 struct mlx5_ifc_arm_xrc_srq_in_bits { 9159 u8 opcode[0x10]; 9160 u8 uid[0x10]; 9161 9162 u8 reserved_at_20[0x10]; 9163 u8 op_mod[0x10]; 9164 9165 u8 reserved_at_40[0x8]; 9166 u8 xrc_srqn[0x18]; 9167 9168 u8 reserved_at_60[0x10]; 9169 u8 lwm[0x10]; 9170 }; 9171 9172 struct mlx5_ifc_arm_rq_out_bits { 9173 u8 status[0x8]; 9174 u8 reserved_at_8[0x18]; 9175 9176 u8 syndrome[0x20]; 9177 9178 u8 reserved_at_40[0x40]; 9179 }; 9180 9181 enum { 9182 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9183 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9184 }; 9185 9186 struct mlx5_ifc_arm_rq_in_bits { 9187 u8 opcode[0x10]; 9188 u8 uid[0x10]; 9189 9190 u8 reserved_at_20[0x10]; 9191 u8 op_mod[0x10]; 9192 9193 u8 reserved_at_40[0x8]; 9194 u8 srq_number[0x18]; 9195 9196 u8 reserved_at_60[0x10]; 9197 u8 lwm[0x10]; 9198 }; 9199 9200 struct mlx5_ifc_arm_dct_out_bits { 9201 u8 status[0x8]; 9202 u8 reserved_at_8[0x18]; 9203 9204 u8 syndrome[0x20]; 9205 9206 u8 reserved_at_40[0x40]; 9207 }; 9208 9209 struct mlx5_ifc_arm_dct_in_bits { 9210 u8 opcode[0x10]; 9211 u8 reserved_at_10[0x10]; 9212 9213 u8 reserved_at_20[0x10]; 9214 u8 op_mod[0x10]; 9215 9216 u8 reserved_at_40[0x8]; 9217 u8 dct_number[0x18]; 9218 9219 u8 reserved_at_60[0x20]; 9220 }; 9221 9222 struct mlx5_ifc_alloc_xrcd_out_bits { 9223 u8 status[0x8]; 9224 u8 reserved_at_8[0x18]; 9225 9226 u8 syndrome[0x20]; 9227 9228 u8 reserved_at_40[0x8]; 9229 u8 xrcd[0x18]; 9230 9231 u8 reserved_at_60[0x20]; 9232 }; 9233 9234 struct mlx5_ifc_alloc_xrcd_in_bits { 9235 u8 opcode[0x10]; 9236 u8 uid[0x10]; 9237 9238 u8 reserved_at_20[0x10]; 9239 u8 op_mod[0x10]; 9240 9241 u8 reserved_at_40[0x40]; 9242 }; 9243 9244 struct mlx5_ifc_alloc_uar_out_bits { 9245 u8 status[0x8]; 9246 u8 reserved_at_8[0x18]; 9247 9248 u8 syndrome[0x20]; 9249 9250 u8 reserved_at_40[0x8]; 9251 u8 uar[0x18]; 9252 9253 u8 reserved_at_60[0x20]; 9254 }; 9255 9256 struct mlx5_ifc_alloc_uar_in_bits { 9257 u8 opcode[0x10]; 9258 u8 uid[0x10]; 9259 9260 u8 reserved_at_20[0x10]; 9261 u8 op_mod[0x10]; 9262 9263 u8 reserved_at_40[0x40]; 9264 }; 9265 9266 struct mlx5_ifc_alloc_transport_domain_out_bits { 9267 u8 status[0x8]; 9268 u8 reserved_at_8[0x18]; 9269 9270 u8 syndrome[0x20]; 9271 9272 u8 reserved_at_40[0x8]; 9273 u8 transport_domain[0x18]; 9274 9275 u8 reserved_at_60[0x20]; 9276 }; 9277 9278 struct mlx5_ifc_alloc_transport_domain_in_bits { 9279 u8 opcode[0x10]; 9280 u8 uid[0x10]; 9281 9282 u8 reserved_at_20[0x10]; 9283 u8 op_mod[0x10]; 9284 9285 u8 reserved_at_40[0x40]; 9286 }; 9287 9288 struct mlx5_ifc_alloc_q_counter_out_bits { 9289 u8 status[0x8]; 9290 u8 reserved_at_8[0x18]; 9291 9292 u8 syndrome[0x20]; 9293 9294 u8 reserved_at_40[0x18]; 9295 u8 counter_set_id[0x8]; 9296 9297 u8 reserved_at_60[0x20]; 9298 }; 9299 9300 struct mlx5_ifc_alloc_q_counter_in_bits { 9301 u8 opcode[0x10]; 9302 u8 uid[0x10]; 9303 9304 u8 reserved_at_20[0x10]; 9305 u8 op_mod[0x10]; 9306 9307 u8 reserved_at_40[0x40]; 9308 }; 9309 9310 struct mlx5_ifc_alloc_pd_out_bits { 9311 u8 status[0x8]; 9312 u8 reserved_at_8[0x18]; 9313 9314 u8 syndrome[0x20]; 9315 9316 u8 reserved_at_40[0x8]; 9317 u8 pd[0x18]; 9318 9319 u8 reserved_at_60[0x20]; 9320 }; 9321 9322 struct mlx5_ifc_alloc_pd_in_bits { 9323 u8 opcode[0x10]; 9324 u8 uid[0x10]; 9325 9326 u8 reserved_at_20[0x10]; 9327 u8 op_mod[0x10]; 9328 9329 u8 reserved_at_40[0x40]; 9330 }; 9331 9332 struct mlx5_ifc_alloc_flow_counter_out_bits { 9333 u8 status[0x8]; 9334 u8 reserved_at_8[0x18]; 9335 9336 u8 syndrome[0x20]; 9337 9338 u8 flow_counter_id[0x20]; 9339 9340 u8 reserved_at_60[0x20]; 9341 }; 9342 9343 struct mlx5_ifc_alloc_flow_counter_in_bits { 9344 u8 opcode[0x10]; 9345 u8 reserved_at_10[0x10]; 9346 9347 u8 reserved_at_20[0x10]; 9348 u8 op_mod[0x10]; 9349 9350 u8 reserved_at_40[0x33]; 9351 u8 flow_counter_bulk_log_size[0x5]; 9352 u8 flow_counter_bulk[0x8]; 9353 }; 9354 9355 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9356 u8 status[0x8]; 9357 u8 reserved_at_8[0x18]; 9358 9359 u8 syndrome[0x20]; 9360 9361 u8 reserved_at_40[0x40]; 9362 }; 9363 9364 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9365 u8 opcode[0x10]; 9366 u8 reserved_at_10[0x10]; 9367 9368 u8 reserved_at_20[0x10]; 9369 u8 op_mod[0x10]; 9370 9371 u8 reserved_at_40[0x20]; 9372 9373 u8 reserved_at_60[0x10]; 9374 u8 vxlan_udp_port[0x10]; 9375 }; 9376 9377 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9378 u8 status[0x8]; 9379 u8 reserved_at_8[0x18]; 9380 9381 u8 syndrome[0x20]; 9382 9383 u8 reserved_at_40[0x40]; 9384 }; 9385 9386 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9387 u8 rate_limit[0x20]; 9388 9389 u8 burst_upper_bound[0x20]; 9390 9391 u8 reserved_at_40[0x10]; 9392 u8 typical_packet_size[0x10]; 9393 9394 u8 reserved_at_60[0x120]; 9395 }; 9396 9397 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9398 u8 opcode[0x10]; 9399 u8 uid[0x10]; 9400 9401 u8 reserved_at_20[0x10]; 9402 u8 op_mod[0x10]; 9403 9404 u8 reserved_at_40[0x10]; 9405 u8 rate_limit_index[0x10]; 9406 9407 u8 reserved_at_60[0x20]; 9408 9409 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9410 }; 9411 9412 struct mlx5_ifc_access_register_out_bits { 9413 u8 status[0x8]; 9414 u8 reserved_at_8[0x18]; 9415 9416 u8 syndrome[0x20]; 9417 9418 u8 reserved_at_40[0x40]; 9419 9420 u8 register_data[][0x20]; 9421 }; 9422 9423 enum { 9424 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9425 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9426 }; 9427 9428 struct mlx5_ifc_access_register_in_bits { 9429 u8 opcode[0x10]; 9430 u8 reserved_at_10[0x10]; 9431 9432 u8 reserved_at_20[0x10]; 9433 u8 op_mod[0x10]; 9434 9435 u8 reserved_at_40[0x10]; 9436 u8 register_id[0x10]; 9437 9438 u8 argument[0x20]; 9439 9440 u8 register_data[][0x20]; 9441 }; 9442 9443 struct mlx5_ifc_sltp_reg_bits { 9444 u8 status[0x4]; 9445 u8 version[0x4]; 9446 u8 local_port[0x8]; 9447 u8 pnat[0x2]; 9448 u8 reserved_at_12[0x2]; 9449 u8 lane[0x4]; 9450 u8 reserved_at_18[0x8]; 9451 9452 u8 reserved_at_20[0x20]; 9453 9454 u8 reserved_at_40[0x7]; 9455 u8 polarity[0x1]; 9456 u8 ob_tap0[0x8]; 9457 u8 ob_tap1[0x8]; 9458 u8 ob_tap2[0x8]; 9459 9460 u8 reserved_at_60[0xc]; 9461 u8 ob_preemp_mode[0x4]; 9462 u8 ob_reg[0x8]; 9463 u8 ob_bias[0x8]; 9464 9465 u8 reserved_at_80[0x20]; 9466 }; 9467 9468 struct mlx5_ifc_slrg_reg_bits { 9469 u8 status[0x4]; 9470 u8 version[0x4]; 9471 u8 local_port[0x8]; 9472 u8 pnat[0x2]; 9473 u8 reserved_at_12[0x2]; 9474 u8 lane[0x4]; 9475 u8 reserved_at_18[0x8]; 9476 9477 u8 time_to_link_up[0x10]; 9478 u8 reserved_at_30[0xc]; 9479 u8 grade_lane_speed[0x4]; 9480 9481 u8 grade_version[0x8]; 9482 u8 grade[0x18]; 9483 9484 u8 reserved_at_60[0x4]; 9485 u8 height_grade_type[0x4]; 9486 u8 height_grade[0x18]; 9487 9488 u8 height_dz[0x10]; 9489 u8 height_dv[0x10]; 9490 9491 u8 reserved_at_a0[0x10]; 9492 u8 height_sigma[0x10]; 9493 9494 u8 reserved_at_c0[0x20]; 9495 9496 u8 reserved_at_e0[0x4]; 9497 u8 phase_grade_type[0x4]; 9498 u8 phase_grade[0x18]; 9499 9500 u8 reserved_at_100[0x8]; 9501 u8 phase_eo_pos[0x8]; 9502 u8 reserved_at_110[0x8]; 9503 u8 phase_eo_neg[0x8]; 9504 9505 u8 ffe_set_tested[0x10]; 9506 u8 test_errors_per_lane[0x10]; 9507 }; 9508 9509 struct mlx5_ifc_pvlc_reg_bits { 9510 u8 reserved_at_0[0x8]; 9511 u8 local_port[0x8]; 9512 u8 reserved_at_10[0x10]; 9513 9514 u8 reserved_at_20[0x1c]; 9515 u8 vl_hw_cap[0x4]; 9516 9517 u8 reserved_at_40[0x1c]; 9518 u8 vl_admin[0x4]; 9519 9520 u8 reserved_at_60[0x1c]; 9521 u8 vl_operational[0x4]; 9522 }; 9523 9524 struct mlx5_ifc_pude_reg_bits { 9525 u8 swid[0x8]; 9526 u8 local_port[0x8]; 9527 u8 reserved_at_10[0x4]; 9528 u8 admin_status[0x4]; 9529 u8 reserved_at_18[0x4]; 9530 u8 oper_status[0x4]; 9531 9532 u8 reserved_at_20[0x60]; 9533 }; 9534 9535 struct mlx5_ifc_ptys_reg_bits { 9536 u8 reserved_at_0[0x1]; 9537 u8 an_disable_admin[0x1]; 9538 u8 an_disable_cap[0x1]; 9539 u8 reserved_at_3[0x5]; 9540 u8 local_port[0x8]; 9541 u8 reserved_at_10[0xd]; 9542 u8 proto_mask[0x3]; 9543 9544 u8 an_status[0x4]; 9545 u8 reserved_at_24[0xc]; 9546 u8 data_rate_oper[0x10]; 9547 9548 u8 ext_eth_proto_capability[0x20]; 9549 9550 u8 eth_proto_capability[0x20]; 9551 9552 u8 ib_link_width_capability[0x10]; 9553 u8 ib_proto_capability[0x10]; 9554 9555 u8 ext_eth_proto_admin[0x20]; 9556 9557 u8 eth_proto_admin[0x20]; 9558 9559 u8 ib_link_width_admin[0x10]; 9560 u8 ib_proto_admin[0x10]; 9561 9562 u8 ext_eth_proto_oper[0x20]; 9563 9564 u8 eth_proto_oper[0x20]; 9565 9566 u8 ib_link_width_oper[0x10]; 9567 u8 ib_proto_oper[0x10]; 9568 9569 u8 reserved_at_160[0x1c]; 9570 u8 connector_type[0x4]; 9571 9572 u8 eth_proto_lp_advertise[0x20]; 9573 9574 u8 reserved_at_1a0[0x60]; 9575 }; 9576 9577 struct mlx5_ifc_mlcr_reg_bits { 9578 u8 reserved_at_0[0x8]; 9579 u8 local_port[0x8]; 9580 u8 reserved_at_10[0x20]; 9581 9582 u8 beacon_duration[0x10]; 9583 u8 reserved_at_40[0x10]; 9584 9585 u8 beacon_remain[0x10]; 9586 }; 9587 9588 struct mlx5_ifc_ptas_reg_bits { 9589 u8 reserved_at_0[0x20]; 9590 9591 u8 algorithm_options[0x10]; 9592 u8 reserved_at_30[0x4]; 9593 u8 repetitions_mode[0x4]; 9594 u8 num_of_repetitions[0x8]; 9595 9596 u8 grade_version[0x8]; 9597 u8 height_grade_type[0x4]; 9598 u8 phase_grade_type[0x4]; 9599 u8 height_grade_weight[0x8]; 9600 u8 phase_grade_weight[0x8]; 9601 9602 u8 gisim_measure_bits[0x10]; 9603 u8 adaptive_tap_measure_bits[0x10]; 9604 9605 u8 ber_bath_high_error_threshold[0x10]; 9606 u8 ber_bath_mid_error_threshold[0x10]; 9607 9608 u8 ber_bath_low_error_threshold[0x10]; 9609 u8 one_ratio_high_threshold[0x10]; 9610 9611 u8 one_ratio_high_mid_threshold[0x10]; 9612 u8 one_ratio_low_mid_threshold[0x10]; 9613 9614 u8 one_ratio_low_threshold[0x10]; 9615 u8 ndeo_error_threshold[0x10]; 9616 9617 u8 mixer_offset_step_size[0x10]; 9618 u8 reserved_at_110[0x8]; 9619 u8 mix90_phase_for_voltage_bath[0x8]; 9620 9621 u8 mixer_offset_start[0x10]; 9622 u8 mixer_offset_end[0x10]; 9623 9624 u8 reserved_at_140[0x15]; 9625 u8 ber_test_time[0xb]; 9626 }; 9627 9628 struct mlx5_ifc_pspa_reg_bits { 9629 u8 swid[0x8]; 9630 u8 local_port[0x8]; 9631 u8 sub_port[0x8]; 9632 u8 reserved_at_18[0x8]; 9633 9634 u8 reserved_at_20[0x20]; 9635 }; 9636 9637 struct mlx5_ifc_pqdr_reg_bits { 9638 u8 reserved_at_0[0x8]; 9639 u8 local_port[0x8]; 9640 u8 reserved_at_10[0x5]; 9641 u8 prio[0x3]; 9642 u8 reserved_at_18[0x6]; 9643 u8 mode[0x2]; 9644 9645 u8 reserved_at_20[0x20]; 9646 9647 u8 reserved_at_40[0x10]; 9648 u8 min_threshold[0x10]; 9649 9650 u8 reserved_at_60[0x10]; 9651 u8 max_threshold[0x10]; 9652 9653 u8 reserved_at_80[0x10]; 9654 u8 mark_probability_denominator[0x10]; 9655 9656 u8 reserved_at_a0[0x60]; 9657 }; 9658 9659 struct mlx5_ifc_ppsc_reg_bits { 9660 u8 reserved_at_0[0x8]; 9661 u8 local_port[0x8]; 9662 u8 reserved_at_10[0x10]; 9663 9664 u8 reserved_at_20[0x60]; 9665 9666 u8 reserved_at_80[0x1c]; 9667 u8 wrps_admin[0x4]; 9668 9669 u8 reserved_at_a0[0x1c]; 9670 u8 wrps_status[0x4]; 9671 9672 u8 reserved_at_c0[0x8]; 9673 u8 up_threshold[0x8]; 9674 u8 reserved_at_d0[0x8]; 9675 u8 down_threshold[0x8]; 9676 9677 u8 reserved_at_e0[0x20]; 9678 9679 u8 reserved_at_100[0x1c]; 9680 u8 srps_admin[0x4]; 9681 9682 u8 reserved_at_120[0x1c]; 9683 u8 srps_status[0x4]; 9684 9685 u8 reserved_at_140[0x40]; 9686 }; 9687 9688 struct mlx5_ifc_pplr_reg_bits { 9689 u8 reserved_at_0[0x8]; 9690 u8 local_port[0x8]; 9691 u8 reserved_at_10[0x10]; 9692 9693 u8 reserved_at_20[0x8]; 9694 u8 lb_cap[0x8]; 9695 u8 reserved_at_30[0x8]; 9696 u8 lb_en[0x8]; 9697 }; 9698 9699 struct mlx5_ifc_pplm_reg_bits { 9700 u8 reserved_at_0[0x8]; 9701 u8 local_port[0x8]; 9702 u8 reserved_at_10[0x10]; 9703 9704 u8 reserved_at_20[0x20]; 9705 9706 u8 port_profile_mode[0x8]; 9707 u8 static_port_profile[0x8]; 9708 u8 active_port_profile[0x8]; 9709 u8 reserved_at_58[0x8]; 9710 9711 u8 retransmission_active[0x8]; 9712 u8 fec_mode_active[0x18]; 9713 9714 u8 rs_fec_correction_bypass_cap[0x4]; 9715 u8 reserved_at_84[0x8]; 9716 u8 fec_override_cap_56g[0x4]; 9717 u8 fec_override_cap_100g[0x4]; 9718 u8 fec_override_cap_50g[0x4]; 9719 u8 fec_override_cap_25g[0x4]; 9720 u8 fec_override_cap_10g_40g[0x4]; 9721 9722 u8 rs_fec_correction_bypass_admin[0x4]; 9723 u8 reserved_at_a4[0x8]; 9724 u8 fec_override_admin_56g[0x4]; 9725 u8 fec_override_admin_100g[0x4]; 9726 u8 fec_override_admin_50g[0x4]; 9727 u8 fec_override_admin_25g[0x4]; 9728 u8 fec_override_admin_10g_40g[0x4]; 9729 9730 u8 fec_override_cap_400g_8x[0x10]; 9731 u8 fec_override_cap_200g_4x[0x10]; 9732 9733 u8 fec_override_cap_100g_2x[0x10]; 9734 u8 fec_override_cap_50g_1x[0x10]; 9735 9736 u8 fec_override_admin_400g_8x[0x10]; 9737 u8 fec_override_admin_200g_4x[0x10]; 9738 9739 u8 fec_override_admin_100g_2x[0x10]; 9740 u8 fec_override_admin_50g_1x[0x10]; 9741 9742 u8 reserved_at_140[0x140]; 9743 }; 9744 9745 struct mlx5_ifc_ppcnt_reg_bits { 9746 u8 swid[0x8]; 9747 u8 local_port[0x8]; 9748 u8 pnat[0x2]; 9749 u8 reserved_at_12[0x8]; 9750 u8 grp[0x6]; 9751 9752 u8 clr[0x1]; 9753 u8 reserved_at_21[0x1c]; 9754 u8 prio_tc[0x3]; 9755 9756 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9757 }; 9758 9759 struct mlx5_ifc_mpein_reg_bits { 9760 u8 reserved_at_0[0x2]; 9761 u8 depth[0x6]; 9762 u8 pcie_index[0x8]; 9763 u8 node[0x8]; 9764 u8 reserved_at_18[0x8]; 9765 9766 u8 capability_mask[0x20]; 9767 9768 u8 reserved_at_40[0x8]; 9769 u8 link_width_enabled[0x8]; 9770 u8 link_speed_enabled[0x10]; 9771 9772 u8 lane0_physical_position[0x8]; 9773 u8 link_width_active[0x8]; 9774 u8 link_speed_active[0x10]; 9775 9776 u8 num_of_pfs[0x10]; 9777 u8 num_of_vfs[0x10]; 9778 9779 u8 bdf0[0x10]; 9780 u8 reserved_at_b0[0x10]; 9781 9782 u8 max_read_request_size[0x4]; 9783 u8 max_payload_size[0x4]; 9784 u8 reserved_at_c8[0x5]; 9785 u8 pwr_status[0x3]; 9786 u8 port_type[0x4]; 9787 u8 reserved_at_d4[0xb]; 9788 u8 lane_reversal[0x1]; 9789 9790 u8 reserved_at_e0[0x14]; 9791 u8 pci_power[0xc]; 9792 9793 u8 reserved_at_100[0x20]; 9794 9795 u8 device_status[0x10]; 9796 u8 port_state[0x8]; 9797 u8 reserved_at_138[0x8]; 9798 9799 u8 reserved_at_140[0x10]; 9800 u8 receiver_detect_result[0x10]; 9801 9802 u8 reserved_at_160[0x20]; 9803 }; 9804 9805 struct mlx5_ifc_mpcnt_reg_bits { 9806 u8 reserved_at_0[0x8]; 9807 u8 pcie_index[0x8]; 9808 u8 reserved_at_10[0xa]; 9809 u8 grp[0x6]; 9810 9811 u8 clr[0x1]; 9812 u8 reserved_at_21[0x1f]; 9813 9814 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9815 }; 9816 9817 struct mlx5_ifc_ppad_reg_bits { 9818 u8 reserved_at_0[0x3]; 9819 u8 single_mac[0x1]; 9820 u8 reserved_at_4[0x4]; 9821 u8 local_port[0x8]; 9822 u8 mac_47_32[0x10]; 9823 9824 u8 mac_31_0[0x20]; 9825 9826 u8 reserved_at_40[0x40]; 9827 }; 9828 9829 struct mlx5_ifc_pmtu_reg_bits { 9830 u8 reserved_at_0[0x8]; 9831 u8 local_port[0x8]; 9832 u8 reserved_at_10[0x10]; 9833 9834 u8 max_mtu[0x10]; 9835 u8 reserved_at_30[0x10]; 9836 9837 u8 admin_mtu[0x10]; 9838 u8 reserved_at_50[0x10]; 9839 9840 u8 oper_mtu[0x10]; 9841 u8 reserved_at_70[0x10]; 9842 }; 9843 9844 struct mlx5_ifc_pmpr_reg_bits { 9845 u8 reserved_at_0[0x8]; 9846 u8 module[0x8]; 9847 u8 reserved_at_10[0x10]; 9848 9849 u8 reserved_at_20[0x18]; 9850 u8 attenuation_5g[0x8]; 9851 9852 u8 reserved_at_40[0x18]; 9853 u8 attenuation_7g[0x8]; 9854 9855 u8 reserved_at_60[0x18]; 9856 u8 attenuation_12g[0x8]; 9857 }; 9858 9859 struct mlx5_ifc_pmpe_reg_bits { 9860 u8 reserved_at_0[0x8]; 9861 u8 module[0x8]; 9862 u8 reserved_at_10[0xc]; 9863 u8 module_status[0x4]; 9864 9865 u8 reserved_at_20[0x60]; 9866 }; 9867 9868 struct mlx5_ifc_pmpc_reg_bits { 9869 u8 module_state_updated[32][0x8]; 9870 }; 9871 9872 struct mlx5_ifc_pmlpn_reg_bits { 9873 u8 reserved_at_0[0x4]; 9874 u8 mlpn_status[0x4]; 9875 u8 local_port[0x8]; 9876 u8 reserved_at_10[0x10]; 9877 9878 u8 e[0x1]; 9879 u8 reserved_at_21[0x1f]; 9880 }; 9881 9882 struct mlx5_ifc_pmlp_reg_bits { 9883 u8 rxtx[0x1]; 9884 u8 reserved_at_1[0x7]; 9885 u8 local_port[0x8]; 9886 u8 reserved_at_10[0x8]; 9887 u8 width[0x8]; 9888 9889 u8 lane0_module_mapping[0x20]; 9890 9891 u8 lane1_module_mapping[0x20]; 9892 9893 u8 lane2_module_mapping[0x20]; 9894 9895 u8 lane3_module_mapping[0x20]; 9896 9897 u8 reserved_at_a0[0x160]; 9898 }; 9899 9900 struct mlx5_ifc_pmaos_reg_bits { 9901 u8 reserved_at_0[0x8]; 9902 u8 module[0x8]; 9903 u8 reserved_at_10[0x4]; 9904 u8 admin_status[0x4]; 9905 u8 reserved_at_18[0x4]; 9906 u8 oper_status[0x4]; 9907 9908 u8 ase[0x1]; 9909 u8 ee[0x1]; 9910 u8 reserved_at_22[0x1c]; 9911 u8 e[0x2]; 9912 9913 u8 reserved_at_40[0x40]; 9914 }; 9915 9916 struct mlx5_ifc_plpc_reg_bits { 9917 u8 reserved_at_0[0x4]; 9918 u8 profile_id[0xc]; 9919 u8 reserved_at_10[0x4]; 9920 u8 proto_mask[0x4]; 9921 u8 reserved_at_18[0x8]; 9922 9923 u8 reserved_at_20[0x10]; 9924 u8 lane_speed[0x10]; 9925 9926 u8 reserved_at_40[0x17]; 9927 u8 lpbf[0x1]; 9928 u8 fec_mode_policy[0x8]; 9929 9930 u8 retransmission_capability[0x8]; 9931 u8 fec_mode_capability[0x18]; 9932 9933 u8 retransmission_support_admin[0x8]; 9934 u8 fec_mode_support_admin[0x18]; 9935 9936 u8 retransmission_request_admin[0x8]; 9937 u8 fec_mode_request_admin[0x18]; 9938 9939 u8 reserved_at_c0[0x80]; 9940 }; 9941 9942 struct mlx5_ifc_plib_reg_bits { 9943 u8 reserved_at_0[0x8]; 9944 u8 local_port[0x8]; 9945 u8 reserved_at_10[0x8]; 9946 u8 ib_port[0x8]; 9947 9948 u8 reserved_at_20[0x60]; 9949 }; 9950 9951 struct mlx5_ifc_plbf_reg_bits { 9952 u8 reserved_at_0[0x8]; 9953 u8 local_port[0x8]; 9954 u8 reserved_at_10[0xd]; 9955 u8 lbf_mode[0x3]; 9956 9957 u8 reserved_at_20[0x20]; 9958 }; 9959 9960 struct mlx5_ifc_pipg_reg_bits { 9961 u8 reserved_at_0[0x8]; 9962 u8 local_port[0x8]; 9963 u8 reserved_at_10[0x10]; 9964 9965 u8 dic[0x1]; 9966 u8 reserved_at_21[0x19]; 9967 u8 ipg[0x4]; 9968 u8 reserved_at_3e[0x2]; 9969 }; 9970 9971 struct mlx5_ifc_pifr_reg_bits { 9972 u8 reserved_at_0[0x8]; 9973 u8 local_port[0x8]; 9974 u8 reserved_at_10[0x10]; 9975 9976 u8 reserved_at_20[0xe0]; 9977 9978 u8 port_filter[8][0x20]; 9979 9980 u8 port_filter_update_en[8][0x20]; 9981 }; 9982 9983 struct mlx5_ifc_pfcc_reg_bits { 9984 u8 reserved_at_0[0x8]; 9985 u8 local_port[0x8]; 9986 u8 reserved_at_10[0xb]; 9987 u8 ppan_mask_n[0x1]; 9988 u8 minor_stall_mask[0x1]; 9989 u8 critical_stall_mask[0x1]; 9990 u8 reserved_at_1e[0x2]; 9991 9992 u8 ppan[0x4]; 9993 u8 reserved_at_24[0x4]; 9994 u8 prio_mask_tx[0x8]; 9995 u8 reserved_at_30[0x8]; 9996 u8 prio_mask_rx[0x8]; 9997 9998 u8 pptx[0x1]; 9999 u8 aptx[0x1]; 10000 u8 pptx_mask_n[0x1]; 10001 u8 reserved_at_43[0x5]; 10002 u8 pfctx[0x8]; 10003 u8 reserved_at_50[0x10]; 10004 10005 u8 pprx[0x1]; 10006 u8 aprx[0x1]; 10007 u8 pprx_mask_n[0x1]; 10008 u8 reserved_at_63[0x5]; 10009 u8 pfcrx[0x8]; 10010 u8 reserved_at_70[0x10]; 10011 10012 u8 device_stall_minor_watermark[0x10]; 10013 u8 device_stall_critical_watermark[0x10]; 10014 10015 u8 reserved_at_a0[0x60]; 10016 }; 10017 10018 struct mlx5_ifc_pelc_reg_bits { 10019 u8 op[0x4]; 10020 u8 reserved_at_4[0x4]; 10021 u8 local_port[0x8]; 10022 u8 reserved_at_10[0x10]; 10023 10024 u8 op_admin[0x8]; 10025 u8 op_capability[0x8]; 10026 u8 op_request[0x8]; 10027 u8 op_active[0x8]; 10028 10029 u8 admin[0x40]; 10030 10031 u8 capability[0x40]; 10032 10033 u8 request[0x40]; 10034 10035 u8 active[0x40]; 10036 10037 u8 reserved_at_140[0x80]; 10038 }; 10039 10040 struct mlx5_ifc_peir_reg_bits { 10041 u8 reserved_at_0[0x8]; 10042 u8 local_port[0x8]; 10043 u8 reserved_at_10[0x10]; 10044 10045 u8 reserved_at_20[0xc]; 10046 u8 error_count[0x4]; 10047 u8 reserved_at_30[0x10]; 10048 10049 u8 reserved_at_40[0xc]; 10050 u8 lane[0x4]; 10051 u8 reserved_at_50[0x8]; 10052 u8 error_type[0x8]; 10053 }; 10054 10055 struct mlx5_ifc_mpegc_reg_bits { 10056 u8 reserved_at_0[0x30]; 10057 u8 field_select[0x10]; 10058 10059 u8 tx_overflow_sense[0x1]; 10060 u8 mark_cqe[0x1]; 10061 u8 mark_cnp[0x1]; 10062 u8 reserved_at_43[0x1b]; 10063 u8 tx_lossy_overflow_oper[0x2]; 10064 10065 u8 reserved_at_60[0x100]; 10066 }; 10067 10068 enum { 10069 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10070 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10071 }; 10072 10073 enum { 10074 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10075 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10076 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10077 }; 10078 10079 struct mlx5_ifc_mtutc_reg_bits { 10080 u8 reserved_at_0[0x5]; 10081 u8 freq_adj_units[0x3]; 10082 u8 reserved_at_8[0x14]; 10083 u8 operation[0x4]; 10084 10085 u8 freq_adjustment[0x20]; 10086 10087 u8 reserved_at_40[0x40]; 10088 10089 u8 utc_sec[0x20]; 10090 10091 u8 reserved_at_a0[0x2]; 10092 u8 utc_nsec[0x1e]; 10093 10094 u8 time_adjustment[0x20]; 10095 }; 10096 10097 struct mlx5_ifc_pcam_enhanced_features_bits { 10098 u8 reserved_at_0[0x68]; 10099 u8 fec_50G_per_lane_in_pplm[0x1]; 10100 u8 reserved_at_69[0x4]; 10101 u8 rx_icrc_encapsulated_counter[0x1]; 10102 u8 reserved_at_6e[0x4]; 10103 u8 ptys_extended_ethernet[0x1]; 10104 u8 reserved_at_73[0x3]; 10105 u8 pfcc_mask[0x1]; 10106 u8 reserved_at_77[0x3]; 10107 u8 per_lane_error_counters[0x1]; 10108 u8 rx_buffer_fullness_counters[0x1]; 10109 u8 ptys_connector_type[0x1]; 10110 u8 reserved_at_7d[0x1]; 10111 u8 ppcnt_discard_group[0x1]; 10112 u8 ppcnt_statistical_group[0x1]; 10113 }; 10114 10115 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10116 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10117 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10118 10119 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10120 u8 pplm[0x1]; 10121 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10122 10123 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10124 u8 pbmc[0x1]; 10125 u8 pptb[0x1]; 10126 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10127 u8 ppcnt[0x1]; 10128 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10129 }; 10130 10131 struct mlx5_ifc_pcam_reg_bits { 10132 u8 reserved_at_0[0x8]; 10133 u8 feature_group[0x8]; 10134 u8 reserved_at_10[0x8]; 10135 u8 access_reg_group[0x8]; 10136 10137 u8 reserved_at_20[0x20]; 10138 10139 union { 10140 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10141 u8 reserved_at_0[0x80]; 10142 } port_access_reg_cap_mask; 10143 10144 u8 reserved_at_c0[0x80]; 10145 10146 union { 10147 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10148 u8 reserved_at_0[0x80]; 10149 } feature_cap_mask; 10150 10151 u8 reserved_at_1c0[0xc0]; 10152 }; 10153 10154 struct mlx5_ifc_mcam_enhanced_features_bits { 10155 u8 reserved_at_0[0x50]; 10156 u8 mtutc_freq_adj_units[0x1]; 10157 u8 mtutc_time_adjustment_extended_range[0x1]; 10158 u8 reserved_at_52[0xb]; 10159 u8 mcia_32dwords[0x1]; 10160 u8 out_pulse_duration_ns[0x1]; 10161 u8 npps_period[0x1]; 10162 u8 reserved_at_60[0xa]; 10163 u8 reset_state[0x1]; 10164 u8 ptpcyc2realtime_modify[0x1]; 10165 u8 reserved_at_6c[0x2]; 10166 u8 pci_status_and_power[0x1]; 10167 u8 reserved_at_6f[0x5]; 10168 u8 mark_tx_action_cnp[0x1]; 10169 u8 mark_tx_action_cqe[0x1]; 10170 u8 dynamic_tx_overflow[0x1]; 10171 u8 reserved_at_77[0x4]; 10172 u8 pcie_outbound_stalled[0x1]; 10173 u8 tx_overflow_buffer_pkt[0x1]; 10174 u8 mtpps_enh_out_per_adj[0x1]; 10175 u8 mtpps_fs[0x1]; 10176 u8 pcie_performance_group[0x1]; 10177 }; 10178 10179 struct mlx5_ifc_mcam_access_reg_bits { 10180 u8 reserved_at_0[0x1c]; 10181 u8 mcda[0x1]; 10182 u8 mcc[0x1]; 10183 u8 mcqi[0x1]; 10184 u8 mcqs[0x1]; 10185 10186 u8 regs_95_to_87[0x9]; 10187 u8 mpegc[0x1]; 10188 u8 mtutc[0x1]; 10189 u8 regs_84_to_68[0x11]; 10190 u8 tracer_registers[0x4]; 10191 10192 u8 regs_63_to_46[0x12]; 10193 u8 mrtc[0x1]; 10194 u8 regs_44_to_32[0xd]; 10195 10196 u8 regs_31_to_0[0x20]; 10197 }; 10198 10199 struct mlx5_ifc_mcam_access_reg_bits1 { 10200 u8 regs_127_to_96[0x20]; 10201 10202 u8 regs_95_to_64[0x20]; 10203 10204 u8 regs_63_to_32[0x20]; 10205 10206 u8 regs_31_to_0[0x20]; 10207 }; 10208 10209 struct mlx5_ifc_mcam_access_reg_bits2 { 10210 u8 regs_127_to_99[0x1d]; 10211 u8 mirc[0x1]; 10212 u8 regs_97_to_96[0x2]; 10213 10214 u8 regs_95_to_64[0x20]; 10215 10216 u8 regs_63_to_32[0x20]; 10217 10218 u8 regs_31_to_0[0x20]; 10219 }; 10220 10221 struct mlx5_ifc_mcam_reg_bits { 10222 u8 reserved_at_0[0x8]; 10223 u8 feature_group[0x8]; 10224 u8 reserved_at_10[0x8]; 10225 u8 access_reg_group[0x8]; 10226 10227 u8 reserved_at_20[0x20]; 10228 10229 union { 10230 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10231 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10232 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10233 u8 reserved_at_0[0x80]; 10234 } mng_access_reg_cap_mask; 10235 10236 u8 reserved_at_c0[0x80]; 10237 10238 union { 10239 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10240 u8 reserved_at_0[0x80]; 10241 } mng_feature_cap_mask; 10242 10243 u8 reserved_at_1c0[0x80]; 10244 }; 10245 10246 struct mlx5_ifc_qcam_access_reg_cap_mask { 10247 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10248 u8 qpdpm[0x1]; 10249 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10250 u8 qdpm[0x1]; 10251 u8 qpts[0x1]; 10252 u8 qcap[0x1]; 10253 u8 qcam_access_reg_cap_mask_0[0x1]; 10254 }; 10255 10256 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10257 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10258 u8 qpts_trust_both[0x1]; 10259 }; 10260 10261 struct mlx5_ifc_qcam_reg_bits { 10262 u8 reserved_at_0[0x8]; 10263 u8 feature_group[0x8]; 10264 u8 reserved_at_10[0x8]; 10265 u8 access_reg_group[0x8]; 10266 u8 reserved_at_20[0x20]; 10267 10268 union { 10269 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10270 u8 reserved_at_0[0x80]; 10271 } qos_access_reg_cap_mask; 10272 10273 u8 reserved_at_c0[0x80]; 10274 10275 union { 10276 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10277 u8 reserved_at_0[0x80]; 10278 } qos_feature_cap_mask; 10279 10280 u8 reserved_at_1c0[0x80]; 10281 }; 10282 10283 struct mlx5_ifc_core_dump_reg_bits { 10284 u8 reserved_at_0[0x18]; 10285 u8 core_dump_type[0x8]; 10286 10287 u8 reserved_at_20[0x30]; 10288 u8 vhca_id[0x10]; 10289 10290 u8 reserved_at_60[0x8]; 10291 u8 qpn[0x18]; 10292 u8 reserved_at_80[0x180]; 10293 }; 10294 10295 struct mlx5_ifc_pcap_reg_bits { 10296 u8 reserved_at_0[0x8]; 10297 u8 local_port[0x8]; 10298 u8 reserved_at_10[0x10]; 10299 10300 u8 port_capability_mask[4][0x20]; 10301 }; 10302 10303 struct mlx5_ifc_paos_reg_bits { 10304 u8 swid[0x8]; 10305 u8 local_port[0x8]; 10306 u8 reserved_at_10[0x4]; 10307 u8 admin_status[0x4]; 10308 u8 reserved_at_18[0x4]; 10309 u8 oper_status[0x4]; 10310 10311 u8 ase[0x1]; 10312 u8 ee[0x1]; 10313 u8 reserved_at_22[0x1c]; 10314 u8 e[0x2]; 10315 10316 u8 reserved_at_40[0x40]; 10317 }; 10318 10319 struct mlx5_ifc_pamp_reg_bits { 10320 u8 reserved_at_0[0x8]; 10321 u8 opamp_group[0x8]; 10322 u8 reserved_at_10[0xc]; 10323 u8 opamp_group_type[0x4]; 10324 10325 u8 start_index[0x10]; 10326 u8 reserved_at_30[0x4]; 10327 u8 num_of_indices[0xc]; 10328 10329 u8 index_data[18][0x10]; 10330 }; 10331 10332 struct mlx5_ifc_pcmr_reg_bits { 10333 u8 reserved_at_0[0x8]; 10334 u8 local_port[0x8]; 10335 u8 reserved_at_10[0x10]; 10336 10337 u8 entropy_force_cap[0x1]; 10338 u8 entropy_calc_cap[0x1]; 10339 u8 entropy_gre_calc_cap[0x1]; 10340 u8 reserved_at_23[0xf]; 10341 u8 rx_ts_over_crc_cap[0x1]; 10342 u8 reserved_at_33[0xb]; 10343 u8 fcs_cap[0x1]; 10344 u8 reserved_at_3f[0x1]; 10345 10346 u8 entropy_force[0x1]; 10347 u8 entropy_calc[0x1]; 10348 u8 entropy_gre_calc[0x1]; 10349 u8 reserved_at_43[0xf]; 10350 u8 rx_ts_over_crc[0x1]; 10351 u8 reserved_at_53[0xb]; 10352 u8 fcs_chk[0x1]; 10353 u8 reserved_at_5f[0x1]; 10354 }; 10355 10356 struct mlx5_ifc_lane_2_module_mapping_bits { 10357 u8 reserved_at_0[0x4]; 10358 u8 rx_lane[0x4]; 10359 u8 reserved_at_8[0x4]; 10360 u8 tx_lane[0x4]; 10361 u8 reserved_at_10[0x8]; 10362 u8 module[0x8]; 10363 }; 10364 10365 struct mlx5_ifc_bufferx_reg_bits { 10366 u8 reserved_at_0[0x6]; 10367 u8 lossy[0x1]; 10368 u8 epsb[0x1]; 10369 u8 reserved_at_8[0x8]; 10370 u8 size[0x10]; 10371 10372 u8 xoff_threshold[0x10]; 10373 u8 xon_threshold[0x10]; 10374 }; 10375 10376 struct mlx5_ifc_set_node_in_bits { 10377 u8 node_description[64][0x8]; 10378 }; 10379 10380 struct mlx5_ifc_register_power_settings_bits { 10381 u8 reserved_at_0[0x18]; 10382 u8 power_settings_level[0x8]; 10383 10384 u8 reserved_at_20[0x60]; 10385 }; 10386 10387 struct mlx5_ifc_register_host_endianness_bits { 10388 u8 he[0x1]; 10389 u8 reserved_at_1[0x1f]; 10390 10391 u8 reserved_at_20[0x60]; 10392 }; 10393 10394 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10395 u8 reserved_at_0[0x20]; 10396 10397 u8 mkey[0x20]; 10398 10399 u8 addressh_63_32[0x20]; 10400 10401 u8 addressl_31_0[0x20]; 10402 }; 10403 10404 struct mlx5_ifc_ud_adrs_vector_bits { 10405 u8 dc_key[0x40]; 10406 10407 u8 ext[0x1]; 10408 u8 reserved_at_41[0x7]; 10409 u8 destination_qp_dct[0x18]; 10410 10411 u8 static_rate[0x4]; 10412 u8 sl_eth_prio[0x4]; 10413 u8 fl[0x1]; 10414 u8 mlid[0x7]; 10415 u8 rlid_udp_sport[0x10]; 10416 10417 u8 reserved_at_80[0x20]; 10418 10419 u8 rmac_47_16[0x20]; 10420 10421 u8 rmac_15_0[0x10]; 10422 u8 tclass[0x8]; 10423 u8 hop_limit[0x8]; 10424 10425 u8 reserved_at_e0[0x1]; 10426 u8 grh[0x1]; 10427 u8 reserved_at_e2[0x2]; 10428 u8 src_addr_index[0x8]; 10429 u8 flow_label[0x14]; 10430 10431 u8 rgid_rip[16][0x8]; 10432 }; 10433 10434 struct mlx5_ifc_pages_req_event_bits { 10435 u8 reserved_at_0[0x10]; 10436 u8 function_id[0x10]; 10437 10438 u8 num_pages[0x20]; 10439 10440 u8 reserved_at_40[0xa0]; 10441 }; 10442 10443 struct mlx5_ifc_eqe_bits { 10444 u8 reserved_at_0[0x8]; 10445 u8 event_type[0x8]; 10446 u8 reserved_at_10[0x8]; 10447 u8 event_sub_type[0x8]; 10448 10449 u8 reserved_at_20[0xe0]; 10450 10451 union mlx5_ifc_event_auto_bits event_data; 10452 10453 u8 reserved_at_1e0[0x10]; 10454 u8 signature[0x8]; 10455 u8 reserved_at_1f8[0x7]; 10456 u8 owner[0x1]; 10457 }; 10458 10459 enum { 10460 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10461 }; 10462 10463 struct mlx5_ifc_cmd_queue_entry_bits { 10464 u8 type[0x8]; 10465 u8 reserved_at_8[0x18]; 10466 10467 u8 input_length[0x20]; 10468 10469 u8 input_mailbox_pointer_63_32[0x20]; 10470 10471 u8 input_mailbox_pointer_31_9[0x17]; 10472 u8 reserved_at_77[0x9]; 10473 10474 u8 command_input_inline_data[16][0x8]; 10475 10476 u8 command_output_inline_data[16][0x8]; 10477 10478 u8 output_mailbox_pointer_63_32[0x20]; 10479 10480 u8 output_mailbox_pointer_31_9[0x17]; 10481 u8 reserved_at_1b7[0x9]; 10482 10483 u8 output_length[0x20]; 10484 10485 u8 token[0x8]; 10486 u8 signature[0x8]; 10487 u8 reserved_at_1f0[0x8]; 10488 u8 status[0x7]; 10489 u8 ownership[0x1]; 10490 }; 10491 10492 struct mlx5_ifc_cmd_out_bits { 10493 u8 status[0x8]; 10494 u8 reserved_at_8[0x18]; 10495 10496 u8 syndrome[0x20]; 10497 10498 u8 command_output[0x20]; 10499 }; 10500 10501 struct mlx5_ifc_cmd_in_bits { 10502 u8 opcode[0x10]; 10503 u8 reserved_at_10[0x10]; 10504 10505 u8 reserved_at_20[0x10]; 10506 u8 op_mod[0x10]; 10507 10508 u8 command[][0x20]; 10509 }; 10510 10511 struct mlx5_ifc_cmd_if_box_bits { 10512 u8 mailbox_data[512][0x8]; 10513 10514 u8 reserved_at_1000[0x180]; 10515 10516 u8 next_pointer_63_32[0x20]; 10517 10518 u8 next_pointer_31_10[0x16]; 10519 u8 reserved_at_11b6[0xa]; 10520 10521 u8 block_number[0x20]; 10522 10523 u8 reserved_at_11e0[0x8]; 10524 u8 token[0x8]; 10525 u8 ctrl_signature[0x8]; 10526 u8 signature[0x8]; 10527 }; 10528 10529 struct mlx5_ifc_mtt_bits { 10530 u8 ptag_63_32[0x20]; 10531 10532 u8 ptag_31_8[0x18]; 10533 u8 reserved_at_38[0x6]; 10534 u8 wr_en[0x1]; 10535 u8 rd_en[0x1]; 10536 }; 10537 10538 struct mlx5_ifc_query_wol_rol_out_bits { 10539 u8 status[0x8]; 10540 u8 reserved_at_8[0x18]; 10541 10542 u8 syndrome[0x20]; 10543 10544 u8 reserved_at_40[0x10]; 10545 u8 rol_mode[0x8]; 10546 u8 wol_mode[0x8]; 10547 10548 u8 reserved_at_60[0x20]; 10549 }; 10550 10551 struct mlx5_ifc_query_wol_rol_in_bits { 10552 u8 opcode[0x10]; 10553 u8 reserved_at_10[0x10]; 10554 10555 u8 reserved_at_20[0x10]; 10556 u8 op_mod[0x10]; 10557 10558 u8 reserved_at_40[0x40]; 10559 }; 10560 10561 struct mlx5_ifc_set_wol_rol_out_bits { 10562 u8 status[0x8]; 10563 u8 reserved_at_8[0x18]; 10564 10565 u8 syndrome[0x20]; 10566 10567 u8 reserved_at_40[0x40]; 10568 }; 10569 10570 struct mlx5_ifc_set_wol_rol_in_bits { 10571 u8 opcode[0x10]; 10572 u8 reserved_at_10[0x10]; 10573 10574 u8 reserved_at_20[0x10]; 10575 u8 op_mod[0x10]; 10576 10577 u8 rol_mode_valid[0x1]; 10578 u8 wol_mode_valid[0x1]; 10579 u8 reserved_at_42[0xe]; 10580 u8 rol_mode[0x8]; 10581 u8 wol_mode[0x8]; 10582 10583 u8 reserved_at_60[0x20]; 10584 }; 10585 10586 enum { 10587 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10588 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10589 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10590 }; 10591 10592 enum { 10593 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10594 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10595 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10596 }; 10597 10598 enum { 10599 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10600 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10601 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10602 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10603 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10604 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10605 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10606 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10607 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10608 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10609 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10610 }; 10611 10612 struct mlx5_ifc_initial_seg_bits { 10613 u8 fw_rev_minor[0x10]; 10614 u8 fw_rev_major[0x10]; 10615 10616 u8 cmd_interface_rev[0x10]; 10617 u8 fw_rev_subminor[0x10]; 10618 10619 u8 reserved_at_40[0x40]; 10620 10621 u8 cmdq_phy_addr_63_32[0x20]; 10622 10623 u8 cmdq_phy_addr_31_12[0x14]; 10624 u8 reserved_at_b4[0x2]; 10625 u8 nic_interface[0x2]; 10626 u8 log_cmdq_size[0x4]; 10627 u8 log_cmdq_stride[0x4]; 10628 10629 u8 command_doorbell_vector[0x20]; 10630 10631 u8 reserved_at_e0[0xf00]; 10632 10633 u8 initializing[0x1]; 10634 u8 reserved_at_fe1[0x4]; 10635 u8 nic_interface_supported[0x3]; 10636 u8 embedded_cpu[0x1]; 10637 u8 reserved_at_fe9[0x17]; 10638 10639 struct mlx5_ifc_health_buffer_bits health_buffer; 10640 10641 u8 no_dram_nic_offset[0x20]; 10642 10643 u8 reserved_at_1220[0x6e40]; 10644 10645 u8 reserved_at_8060[0x1f]; 10646 u8 clear_int[0x1]; 10647 10648 u8 health_syndrome[0x8]; 10649 u8 health_counter[0x18]; 10650 10651 u8 reserved_at_80a0[0x17fc0]; 10652 }; 10653 10654 struct mlx5_ifc_mtpps_reg_bits { 10655 u8 reserved_at_0[0xc]; 10656 u8 cap_number_of_pps_pins[0x4]; 10657 u8 reserved_at_10[0x4]; 10658 u8 cap_max_num_of_pps_in_pins[0x4]; 10659 u8 reserved_at_18[0x4]; 10660 u8 cap_max_num_of_pps_out_pins[0x4]; 10661 10662 u8 reserved_at_20[0x13]; 10663 u8 cap_log_min_npps_period[0x5]; 10664 u8 reserved_at_38[0x3]; 10665 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10666 10667 u8 reserved_at_40[0x4]; 10668 u8 cap_pin_3_mode[0x4]; 10669 u8 reserved_at_48[0x4]; 10670 u8 cap_pin_2_mode[0x4]; 10671 u8 reserved_at_50[0x4]; 10672 u8 cap_pin_1_mode[0x4]; 10673 u8 reserved_at_58[0x4]; 10674 u8 cap_pin_0_mode[0x4]; 10675 10676 u8 reserved_at_60[0x4]; 10677 u8 cap_pin_7_mode[0x4]; 10678 u8 reserved_at_68[0x4]; 10679 u8 cap_pin_6_mode[0x4]; 10680 u8 reserved_at_70[0x4]; 10681 u8 cap_pin_5_mode[0x4]; 10682 u8 reserved_at_78[0x4]; 10683 u8 cap_pin_4_mode[0x4]; 10684 10685 u8 field_select[0x20]; 10686 u8 reserved_at_a0[0x20]; 10687 10688 u8 npps_period[0x40]; 10689 10690 u8 enable[0x1]; 10691 u8 reserved_at_101[0xb]; 10692 u8 pattern[0x4]; 10693 u8 reserved_at_110[0x4]; 10694 u8 pin_mode[0x4]; 10695 u8 pin[0x8]; 10696 10697 u8 reserved_at_120[0x2]; 10698 u8 out_pulse_duration_ns[0x1e]; 10699 10700 u8 time_stamp[0x40]; 10701 10702 u8 out_pulse_duration[0x10]; 10703 u8 out_periodic_adjustment[0x10]; 10704 u8 enhanced_out_periodic_adjustment[0x20]; 10705 10706 u8 reserved_at_1c0[0x20]; 10707 }; 10708 10709 struct mlx5_ifc_mtppse_reg_bits { 10710 u8 reserved_at_0[0x18]; 10711 u8 pin[0x8]; 10712 u8 event_arm[0x1]; 10713 u8 reserved_at_21[0x1b]; 10714 u8 event_generation_mode[0x4]; 10715 u8 reserved_at_40[0x40]; 10716 }; 10717 10718 struct mlx5_ifc_mcqs_reg_bits { 10719 u8 last_index_flag[0x1]; 10720 u8 reserved_at_1[0x7]; 10721 u8 fw_device[0x8]; 10722 u8 component_index[0x10]; 10723 10724 u8 reserved_at_20[0x10]; 10725 u8 identifier[0x10]; 10726 10727 u8 reserved_at_40[0x17]; 10728 u8 component_status[0x5]; 10729 u8 component_update_state[0x4]; 10730 10731 u8 last_update_state_changer_type[0x4]; 10732 u8 last_update_state_changer_host_id[0x4]; 10733 u8 reserved_at_68[0x18]; 10734 }; 10735 10736 struct mlx5_ifc_mcqi_cap_bits { 10737 u8 supported_info_bitmask[0x20]; 10738 10739 u8 component_size[0x20]; 10740 10741 u8 max_component_size[0x20]; 10742 10743 u8 log_mcda_word_size[0x4]; 10744 u8 reserved_at_64[0xc]; 10745 u8 mcda_max_write_size[0x10]; 10746 10747 u8 rd_en[0x1]; 10748 u8 reserved_at_81[0x1]; 10749 u8 match_chip_id[0x1]; 10750 u8 match_psid[0x1]; 10751 u8 check_user_timestamp[0x1]; 10752 u8 match_base_guid_mac[0x1]; 10753 u8 reserved_at_86[0x1a]; 10754 }; 10755 10756 struct mlx5_ifc_mcqi_version_bits { 10757 u8 reserved_at_0[0x2]; 10758 u8 build_time_valid[0x1]; 10759 u8 user_defined_time_valid[0x1]; 10760 u8 reserved_at_4[0x14]; 10761 u8 version_string_length[0x8]; 10762 10763 u8 version[0x20]; 10764 10765 u8 build_time[0x40]; 10766 10767 u8 user_defined_time[0x40]; 10768 10769 u8 build_tool_version[0x20]; 10770 10771 u8 reserved_at_e0[0x20]; 10772 10773 u8 version_string[92][0x8]; 10774 }; 10775 10776 struct mlx5_ifc_mcqi_activation_method_bits { 10777 u8 pending_server_ac_power_cycle[0x1]; 10778 u8 pending_server_dc_power_cycle[0x1]; 10779 u8 pending_server_reboot[0x1]; 10780 u8 pending_fw_reset[0x1]; 10781 u8 auto_activate[0x1]; 10782 u8 all_hosts_sync[0x1]; 10783 u8 device_hw_reset[0x1]; 10784 u8 reserved_at_7[0x19]; 10785 }; 10786 10787 union mlx5_ifc_mcqi_reg_data_bits { 10788 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10789 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10790 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10791 }; 10792 10793 struct mlx5_ifc_mcqi_reg_bits { 10794 u8 read_pending_component[0x1]; 10795 u8 reserved_at_1[0xf]; 10796 u8 component_index[0x10]; 10797 10798 u8 reserved_at_20[0x20]; 10799 10800 u8 reserved_at_40[0x1b]; 10801 u8 info_type[0x5]; 10802 10803 u8 info_size[0x20]; 10804 10805 u8 offset[0x20]; 10806 10807 u8 reserved_at_a0[0x10]; 10808 u8 data_size[0x10]; 10809 10810 union mlx5_ifc_mcqi_reg_data_bits data[]; 10811 }; 10812 10813 struct mlx5_ifc_mcc_reg_bits { 10814 u8 reserved_at_0[0x4]; 10815 u8 time_elapsed_since_last_cmd[0xc]; 10816 u8 reserved_at_10[0x8]; 10817 u8 instruction[0x8]; 10818 10819 u8 reserved_at_20[0x10]; 10820 u8 component_index[0x10]; 10821 10822 u8 reserved_at_40[0x8]; 10823 u8 update_handle[0x18]; 10824 10825 u8 handle_owner_type[0x4]; 10826 u8 handle_owner_host_id[0x4]; 10827 u8 reserved_at_68[0x1]; 10828 u8 control_progress[0x7]; 10829 u8 error_code[0x8]; 10830 u8 reserved_at_78[0x4]; 10831 u8 control_state[0x4]; 10832 10833 u8 component_size[0x20]; 10834 10835 u8 reserved_at_a0[0x60]; 10836 }; 10837 10838 struct mlx5_ifc_mcda_reg_bits { 10839 u8 reserved_at_0[0x8]; 10840 u8 update_handle[0x18]; 10841 10842 u8 offset[0x20]; 10843 10844 u8 reserved_at_40[0x10]; 10845 u8 size[0x10]; 10846 10847 u8 reserved_at_60[0x20]; 10848 10849 u8 data[][0x20]; 10850 }; 10851 10852 enum { 10853 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10854 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10855 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10856 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10857 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10858 }; 10859 10860 enum { 10861 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10862 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10863 }; 10864 10865 enum { 10866 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10867 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10868 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10869 }; 10870 10871 struct mlx5_ifc_mfrl_reg_bits { 10872 u8 reserved_at_0[0x20]; 10873 10874 u8 reserved_at_20[0x2]; 10875 u8 pci_sync_for_fw_update_start[0x1]; 10876 u8 pci_sync_for_fw_update_resp[0x2]; 10877 u8 rst_type_sel[0x3]; 10878 u8 reserved_at_28[0x4]; 10879 u8 reset_state[0x4]; 10880 u8 reset_type[0x8]; 10881 u8 reset_level[0x8]; 10882 }; 10883 10884 struct mlx5_ifc_mirc_reg_bits { 10885 u8 reserved_at_0[0x18]; 10886 u8 status_code[0x8]; 10887 10888 u8 reserved_at_20[0x20]; 10889 }; 10890 10891 struct mlx5_ifc_pddr_monitor_opcode_bits { 10892 u8 reserved_at_0[0x10]; 10893 u8 monitor_opcode[0x10]; 10894 }; 10895 10896 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10897 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10898 u8 reserved_at_0[0x20]; 10899 }; 10900 10901 enum { 10902 /* Monitor opcodes */ 10903 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10904 }; 10905 10906 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10907 u8 reserved_at_0[0x10]; 10908 u8 group_opcode[0x10]; 10909 10910 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10911 10912 u8 reserved_at_40[0x20]; 10913 10914 u8 status_message[59][0x20]; 10915 }; 10916 10917 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10918 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10919 u8 reserved_at_0[0x7c0]; 10920 }; 10921 10922 enum { 10923 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10924 }; 10925 10926 struct mlx5_ifc_pddr_reg_bits { 10927 u8 reserved_at_0[0x8]; 10928 u8 local_port[0x8]; 10929 u8 pnat[0x2]; 10930 u8 reserved_at_12[0xe]; 10931 10932 u8 reserved_at_20[0x18]; 10933 u8 page_select[0x8]; 10934 10935 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10936 }; 10937 10938 struct mlx5_ifc_mrtc_reg_bits { 10939 u8 time_synced[0x1]; 10940 u8 reserved_at_1[0x1f]; 10941 10942 u8 reserved_at_20[0x20]; 10943 10944 u8 time_h[0x20]; 10945 10946 u8 time_l[0x20]; 10947 }; 10948 10949 struct mlx5_ifc_mtmp_reg_bits { 10950 u8 reserved_at_0[0x14]; 10951 u8 sensor_index[0xc]; 10952 10953 u8 reserved_at_20[0x10]; 10954 u8 temperature[0x10]; 10955 10956 u8 mte[0x1]; 10957 u8 mtr[0x1]; 10958 u8 reserved_at_42[0xe]; 10959 u8 max_temperature[0x10]; 10960 10961 u8 tee[0x2]; 10962 u8 reserved_at_62[0xe]; 10963 u8 temp_threshold_hi[0x10]; 10964 10965 u8 reserved_at_80[0x10]; 10966 u8 temp_threshold_lo[0x10]; 10967 10968 u8 reserved_at_a0[0x20]; 10969 10970 u8 sensor_name_hi[0x20]; 10971 u8 sensor_name_lo[0x20]; 10972 }; 10973 10974 union mlx5_ifc_ports_control_registers_document_bits { 10975 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10976 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10977 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10978 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10979 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10980 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10981 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10982 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10983 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10984 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10985 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10986 struct mlx5_ifc_paos_reg_bits paos_reg; 10987 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10988 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10989 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10990 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10991 struct mlx5_ifc_peir_reg_bits peir_reg; 10992 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10993 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10994 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10995 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10996 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10997 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10998 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10999 struct mlx5_ifc_plib_reg_bits plib_reg; 11000 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11001 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11002 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11003 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11004 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11005 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11006 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11007 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11008 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11009 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11010 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11011 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11012 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11013 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11014 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11015 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11016 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11017 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11018 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11019 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11020 struct mlx5_ifc_pude_reg_bits pude_reg; 11021 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11022 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11023 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11024 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11025 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11026 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11027 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11028 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11029 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11030 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11031 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11032 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11033 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11034 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11035 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11036 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11037 u8 reserved_at_0[0x60e0]; 11038 }; 11039 11040 union mlx5_ifc_debug_enhancements_document_bits { 11041 struct mlx5_ifc_health_buffer_bits health_buffer; 11042 u8 reserved_at_0[0x200]; 11043 }; 11044 11045 union mlx5_ifc_uplink_pci_interface_document_bits { 11046 struct mlx5_ifc_initial_seg_bits initial_seg; 11047 u8 reserved_at_0[0x20060]; 11048 }; 11049 11050 struct mlx5_ifc_set_flow_table_root_out_bits { 11051 u8 status[0x8]; 11052 u8 reserved_at_8[0x18]; 11053 11054 u8 syndrome[0x20]; 11055 11056 u8 reserved_at_40[0x40]; 11057 }; 11058 11059 struct mlx5_ifc_set_flow_table_root_in_bits { 11060 u8 opcode[0x10]; 11061 u8 reserved_at_10[0x10]; 11062 11063 u8 reserved_at_20[0x10]; 11064 u8 op_mod[0x10]; 11065 11066 u8 other_vport[0x1]; 11067 u8 reserved_at_41[0xf]; 11068 u8 vport_number[0x10]; 11069 11070 u8 reserved_at_60[0x20]; 11071 11072 u8 table_type[0x8]; 11073 u8 reserved_at_88[0x7]; 11074 u8 table_of_other_vport[0x1]; 11075 u8 table_vport_number[0x10]; 11076 11077 u8 reserved_at_a0[0x8]; 11078 u8 table_id[0x18]; 11079 11080 u8 reserved_at_c0[0x8]; 11081 u8 underlay_qpn[0x18]; 11082 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11083 u8 reserved_at_e1[0xf]; 11084 u8 table_eswitch_owner_vhca_id[0x10]; 11085 u8 reserved_at_100[0x100]; 11086 }; 11087 11088 enum { 11089 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11090 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11091 }; 11092 11093 struct mlx5_ifc_modify_flow_table_out_bits { 11094 u8 status[0x8]; 11095 u8 reserved_at_8[0x18]; 11096 11097 u8 syndrome[0x20]; 11098 11099 u8 reserved_at_40[0x40]; 11100 }; 11101 11102 struct mlx5_ifc_modify_flow_table_in_bits { 11103 u8 opcode[0x10]; 11104 u8 reserved_at_10[0x10]; 11105 11106 u8 reserved_at_20[0x10]; 11107 u8 op_mod[0x10]; 11108 11109 u8 other_vport[0x1]; 11110 u8 reserved_at_41[0xf]; 11111 u8 vport_number[0x10]; 11112 11113 u8 reserved_at_60[0x10]; 11114 u8 modify_field_select[0x10]; 11115 11116 u8 table_type[0x8]; 11117 u8 reserved_at_88[0x18]; 11118 11119 u8 reserved_at_a0[0x8]; 11120 u8 table_id[0x18]; 11121 11122 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11123 }; 11124 11125 struct mlx5_ifc_ets_tcn_config_reg_bits { 11126 u8 g[0x1]; 11127 u8 b[0x1]; 11128 u8 r[0x1]; 11129 u8 reserved_at_3[0x9]; 11130 u8 group[0x4]; 11131 u8 reserved_at_10[0x9]; 11132 u8 bw_allocation[0x7]; 11133 11134 u8 reserved_at_20[0xc]; 11135 u8 max_bw_units[0x4]; 11136 u8 reserved_at_30[0x8]; 11137 u8 max_bw_value[0x8]; 11138 }; 11139 11140 struct mlx5_ifc_ets_global_config_reg_bits { 11141 u8 reserved_at_0[0x2]; 11142 u8 r[0x1]; 11143 u8 reserved_at_3[0x1d]; 11144 11145 u8 reserved_at_20[0xc]; 11146 u8 max_bw_units[0x4]; 11147 u8 reserved_at_30[0x8]; 11148 u8 max_bw_value[0x8]; 11149 }; 11150 11151 struct mlx5_ifc_qetc_reg_bits { 11152 u8 reserved_at_0[0x8]; 11153 u8 port_number[0x8]; 11154 u8 reserved_at_10[0x30]; 11155 11156 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11157 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11158 }; 11159 11160 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11161 u8 e[0x1]; 11162 u8 reserved_at_01[0x0b]; 11163 u8 prio[0x04]; 11164 }; 11165 11166 struct mlx5_ifc_qpdpm_reg_bits { 11167 u8 reserved_at_0[0x8]; 11168 u8 local_port[0x8]; 11169 u8 reserved_at_10[0x10]; 11170 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11171 }; 11172 11173 struct mlx5_ifc_qpts_reg_bits { 11174 u8 reserved_at_0[0x8]; 11175 u8 local_port[0x8]; 11176 u8 reserved_at_10[0x2d]; 11177 u8 trust_state[0x3]; 11178 }; 11179 11180 struct mlx5_ifc_pptb_reg_bits { 11181 u8 reserved_at_0[0x2]; 11182 u8 mm[0x2]; 11183 u8 reserved_at_4[0x4]; 11184 u8 local_port[0x8]; 11185 u8 reserved_at_10[0x6]; 11186 u8 cm[0x1]; 11187 u8 um[0x1]; 11188 u8 pm[0x8]; 11189 11190 u8 prio_x_buff[0x20]; 11191 11192 u8 pm_msb[0x8]; 11193 u8 reserved_at_48[0x10]; 11194 u8 ctrl_buff[0x4]; 11195 u8 untagged_buff[0x4]; 11196 }; 11197 11198 struct mlx5_ifc_sbcam_reg_bits { 11199 u8 reserved_at_0[0x8]; 11200 u8 feature_group[0x8]; 11201 u8 reserved_at_10[0x8]; 11202 u8 access_reg_group[0x8]; 11203 11204 u8 reserved_at_20[0x20]; 11205 11206 u8 sb_access_reg_cap_mask[4][0x20]; 11207 11208 u8 reserved_at_c0[0x80]; 11209 11210 u8 sb_feature_cap_mask[4][0x20]; 11211 11212 u8 reserved_at_1c0[0x40]; 11213 11214 u8 cap_total_buffer_size[0x20]; 11215 11216 u8 cap_cell_size[0x10]; 11217 u8 cap_max_pg_buffers[0x8]; 11218 u8 cap_num_pool_supported[0x8]; 11219 11220 u8 reserved_at_240[0x8]; 11221 u8 cap_sbsr_stat_size[0x8]; 11222 u8 cap_max_tclass_data[0x8]; 11223 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11224 }; 11225 11226 struct mlx5_ifc_pbmc_reg_bits { 11227 u8 reserved_at_0[0x8]; 11228 u8 local_port[0x8]; 11229 u8 reserved_at_10[0x10]; 11230 11231 u8 xoff_timer_value[0x10]; 11232 u8 xoff_refresh[0x10]; 11233 11234 u8 reserved_at_40[0x9]; 11235 u8 fullness_threshold[0x7]; 11236 u8 port_buffer_size[0x10]; 11237 11238 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11239 11240 u8 reserved_at_2e0[0x80]; 11241 }; 11242 11243 struct mlx5_ifc_sbpr_reg_bits { 11244 u8 desc[0x1]; 11245 u8 snap[0x1]; 11246 u8 reserved_at_2[0x4]; 11247 u8 dir[0x2]; 11248 u8 reserved_at_8[0x14]; 11249 u8 pool[0x4]; 11250 11251 u8 infi_size[0x1]; 11252 u8 reserved_at_21[0x7]; 11253 u8 size[0x18]; 11254 11255 u8 reserved_at_40[0x1c]; 11256 u8 mode[0x4]; 11257 11258 u8 reserved_at_60[0x8]; 11259 u8 buff_occupancy[0x18]; 11260 11261 u8 clr[0x1]; 11262 u8 reserved_at_81[0x7]; 11263 u8 max_buff_occupancy[0x18]; 11264 11265 u8 reserved_at_a0[0x8]; 11266 u8 ext_buff_occupancy[0x18]; 11267 }; 11268 11269 struct mlx5_ifc_sbcm_reg_bits { 11270 u8 desc[0x1]; 11271 u8 snap[0x1]; 11272 u8 reserved_at_2[0x6]; 11273 u8 local_port[0x8]; 11274 u8 pnat[0x2]; 11275 u8 pg_buff[0x6]; 11276 u8 reserved_at_18[0x6]; 11277 u8 dir[0x2]; 11278 11279 u8 reserved_at_20[0x1f]; 11280 u8 exc[0x1]; 11281 11282 u8 reserved_at_40[0x40]; 11283 11284 u8 reserved_at_80[0x8]; 11285 u8 buff_occupancy[0x18]; 11286 11287 u8 clr[0x1]; 11288 u8 reserved_at_a1[0x7]; 11289 u8 max_buff_occupancy[0x18]; 11290 11291 u8 reserved_at_c0[0x8]; 11292 u8 min_buff[0x18]; 11293 11294 u8 infi_max[0x1]; 11295 u8 reserved_at_e1[0x7]; 11296 u8 max_buff[0x18]; 11297 11298 u8 reserved_at_100[0x20]; 11299 11300 u8 reserved_at_120[0x1c]; 11301 u8 pool[0x4]; 11302 }; 11303 11304 struct mlx5_ifc_qtct_reg_bits { 11305 u8 reserved_at_0[0x8]; 11306 u8 port_number[0x8]; 11307 u8 reserved_at_10[0xd]; 11308 u8 prio[0x3]; 11309 11310 u8 reserved_at_20[0x1d]; 11311 u8 tclass[0x3]; 11312 }; 11313 11314 struct mlx5_ifc_mcia_reg_bits { 11315 u8 l[0x1]; 11316 u8 reserved_at_1[0x7]; 11317 u8 module[0x8]; 11318 u8 reserved_at_10[0x8]; 11319 u8 status[0x8]; 11320 11321 u8 i2c_device_address[0x8]; 11322 u8 page_number[0x8]; 11323 u8 device_address[0x10]; 11324 11325 u8 reserved_at_40[0x10]; 11326 u8 size[0x10]; 11327 11328 u8 reserved_at_60[0x20]; 11329 11330 u8 dword_0[0x20]; 11331 u8 dword_1[0x20]; 11332 u8 dword_2[0x20]; 11333 u8 dword_3[0x20]; 11334 u8 dword_4[0x20]; 11335 u8 dword_5[0x20]; 11336 u8 dword_6[0x20]; 11337 u8 dword_7[0x20]; 11338 u8 dword_8[0x20]; 11339 u8 dword_9[0x20]; 11340 u8 dword_10[0x20]; 11341 u8 dword_11[0x20]; 11342 }; 11343 11344 struct mlx5_ifc_dcbx_param_bits { 11345 u8 dcbx_cee_cap[0x1]; 11346 u8 dcbx_ieee_cap[0x1]; 11347 u8 dcbx_standby_cap[0x1]; 11348 u8 reserved_at_3[0x5]; 11349 u8 port_number[0x8]; 11350 u8 reserved_at_10[0xa]; 11351 u8 max_application_table_size[6]; 11352 u8 reserved_at_20[0x15]; 11353 u8 version_oper[0x3]; 11354 u8 reserved_at_38[5]; 11355 u8 version_admin[0x3]; 11356 u8 willing_admin[0x1]; 11357 u8 reserved_at_41[0x3]; 11358 u8 pfc_cap_oper[0x4]; 11359 u8 reserved_at_48[0x4]; 11360 u8 pfc_cap_admin[0x4]; 11361 u8 reserved_at_50[0x4]; 11362 u8 num_of_tc_oper[0x4]; 11363 u8 reserved_at_58[0x4]; 11364 u8 num_of_tc_admin[0x4]; 11365 u8 remote_willing[0x1]; 11366 u8 reserved_at_61[3]; 11367 u8 remote_pfc_cap[4]; 11368 u8 reserved_at_68[0x14]; 11369 u8 remote_num_of_tc[0x4]; 11370 u8 reserved_at_80[0x18]; 11371 u8 error[0x8]; 11372 u8 reserved_at_a0[0x160]; 11373 }; 11374 11375 enum { 11376 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11377 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11378 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11379 }; 11380 11381 struct mlx5_ifc_lagc_bits { 11382 u8 fdb_selection_mode[0x1]; 11383 u8 reserved_at_1[0x14]; 11384 u8 port_select_mode[0x3]; 11385 u8 reserved_at_18[0x5]; 11386 u8 lag_state[0x3]; 11387 11388 u8 reserved_at_20[0xc]; 11389 u8 active_port[0x4]; 11390 u8 reserved_at_30[0x4]; 11391 u8 tx_remap_affinity_2[0x4]; 11392 u8 reserved_at_38[0x4]; 11393 u8 tx_remap_affinity_1[0x4]; 11394 }; 11395 11396 struct mlx5_ifc_create_lag_out_bits { 11397 u8 status[0x8]; 11398 u8 reserved_at_8[0x18]; 11399 11400 u8 syndrome[0x20]; 11401 11402 u8 reserved_at_40[0x40]; 11403 }; 11404 11405 struct mlx5_ifc_create_lag_in_bits { 11406 u8 opcode[0x10]; 11407 u8 reserved_at_10[0x10]; 11408 11409 u8 reserved_at_20[0x10]; 11410 u8 op_mod[0x10]; 11411 11412 struct mlx5_ifc_lagc_bits ctx; 11413 }; 11414 11415 struct mlx5_ifc_modify_lag_out_bits { 11416 u8 status[0x8]; 11417 u8 reserved_at_8[0x18]; 11418 11419 u8 syndrome[0x20]; 11420 11421 u8 reserved_at_40[0x40]; 11422 }; 11423 11424 struct mlx5_ifc_modify_lag_in_bits { 11425 u8 opcode[0x10]; 11426 u8 reserved_at_10[0x10]; 11427 11428 u8 reserved_at_20[0x10]; 11429 u8 op_mod[0x10]; 11430 11431 u8 reserved_at_40[0x20]; 11432 u8 field_select[0x20]; 11433 11434 struct mlx5_ifc_lagc_bits ctx; 11435 }; 11436 11437 struct mlx5_ifc_query_lag_out_bits { 11438 u8 status[0x8]; 11439 u8 reserved_at_8[0x18]; 11440 11441 u8 syndrome[0x20]; 11442 11443 struct mlx5_ifc_lagc_bits ctx; 11444 }; 11445 11446 struct mlx5_ifc_query_lag_in_bits { 11447 u8 opcode[0x10]; 11448 u8 reserved_at_10[0x10]; 11449 11450 u8 reserved_at_20[0x10]; 11451 u8 op_mod[0x10]; 11452 11453 u8 reserved_at_40[0x40]; 11454 }; 11455 11456 struct mlx5_ifc_destroy_lag_out_bits { 11457 u8 status[0x8]; 11458 u8 reserved_at_8[0x18]; 11459 11460 u8 syndrome[0x20]; 11461 11462 u8 reserved_at_40[0x40]; 11463 }; 11464 11465 struct mlx5_ifc_destroy_lag_in_bits { 11466 u8 opcode[0x10]; 11467 u8 reserved_at_10[0x10]; 11468 11469 u8 reserved_at_20[0x10]; 11470 u8 op_mod[0x10]; 11471 11472 u8 reserved_at_40[0x40]; 11473 }; 11474 11475 struct mlx5_ifc_create_vport_lag_out_bits { 11476 u8 status[0x8]; 11477 u8 reserved_at_8[0x18]; 11478 11479 u8 syndrome[0x20]; 11480 11481 u8 reserved_at_40[0x40]; 11482 }; 11483 11484 struct mlx5_ifc_create_vport_lag_in_bits { 11485 u8 opcode[0x10]; 11486 u8 reserved_at_10[0x10]; 11487 11488 u8 reserved_at_20[0x10]; 11489 u8 op_mod[0x10]; 11490 11491 u8 reserved_at_40[0x40]; 11492 }; 11493 11494 struct mlx5_ifc_destroy_vport_lag_out_bits { 11495 u8 status[0x8]; 11496 u8 reserved_at_8[0x18]; 11497 11498 u8 syndrome[0x20]; 11499 11500 u8 reserved_at_40[0x40]; 11501 }; 11502 11503 struct mlx5_ifc_destroy_vport_lag_in_bits { 11504 u8 opcode[0x10]; 11505 u8 reserved_at_10[0x10]; 11506 11507 u8 reserved_at_20[0x10]; 11508 u8 op_mod[0x10]; 11509 11510 u8 reserved_at_40[0x40]; 11511 }; 11512 11513 enum { 11514 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11515 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11516 }; 11517 11518 struct mlx5_ifc_modify_memic_in_bits { 11519 u8 opcode[0x10]; 11520 u8 uid[0x10]; 11521 11522 u8 reserved_at_20[0x10]; 11523 u8 op_mod[0x10]; 11524 11525 u8 reserved_at_40[0x20]; 11526 11527 u8 reserved_at_60[0x18]; 11528 u8 memic_operation_type[0x8]; 11529 11530 u8 memic_start_addr[0x40]; 11531 11532 u8 reserved_at_c0[0x140]; 11533 }; 11534 11535 struct mlx5_ifc_modify_memic_out_bits { 11536 u8 status[0x8]; 11537 u8 reserved_at_8[0x18]; 11538 11539 u8 syndrome[0x20]; 11540 11541 u8 reserved_at_40[0x40]; 11542 11543 u8 memic_operation_addr[0x40]; 11544 11545 u8 reserved_at_c0[0x140]; 11546 }; 11547 11548 struct mlx5_ifc_alloc_memic_in_bits { 11549 u8 opcode[0x10]; 11550 u8 reserved_at_10[0x10]; 11551 11552 u8 reserved_at_20[0x10]; 11553 u8 op_mod[0x10]; 11554 11555 u8 reserved_at_30[0x20]; 11556 11557 u8 reserved_at_40[0x18]; 11558 u8 log_memic_addr_alignment[0x8]; 11559 11560 u8 range_start_addr[0x40]; 11561 11562 u8 range_size[0x20]; 11563 11564 u8 memic_size[0x20]; 11565 }; 11566 11567 struct mlx5_ifc_alloc_memic_out_bits { 11568 u8 status[0x8]; 11569 u8 reserved_at_8[0x18]; 11570 11571 u8 syndrome[0x20]; 11572 11573 u8 memic_start_addr[0x40]; 11574 }; 11575 11576 struct mlx5_ifc_dealloc_memic_in_bits { 11577 u8 opcode[0x10]; 11578 u8 reserved_at_10[0x10]; 11579 11580 u8 reserved_at_20[0x10]; 11581 u8 op_mod[0x10]; 11582 11583 u8 reserved_at_40[0x40]; 11584 11585 u8 memic_start_addr[0x40]; 11586 11587 u8 memic_size[0x20]; 11588 11589 u8 reserved_at_e0[0x20]; 11590 }; 11591 11592 struct mlx5_ifc_dealloc_memic_out_bits { 11593 u8 status[0x8]; 11594 u8 reserved_at_8[0x18]; 11595 11596 u8 syndrome[0x20]; 11597 11598 u8 reserved_at_40[0x40]; 11599 }; 11600 11601 struct mlx5_ifc_umem_bits { 11602 u8 reserved_at_0[0x80]; 11603 11604 u8 ats[0x1]; 11605 u8 reserved_at_81[0x1a]; 11606 u8 log_page_size[0x5]; 11607 11608 u8 page_offset[0x20]; 11609 11610 u8 num_of_mtt[0x40]; 11611 11612 struct mlx5_ifc_mtt_bits mtt[]; 11613 }; 11614 11615 struct mlx5_ifc_uctx_bits { 11616 u8 cap[0x20]; 11617 11618 u8 reserved_at_20[0x160]; 11619 }; 11620 11621 struct mlx5_ifc_sw_icm_bits { 11622 u8 modify_field_select[0x40]; 11623 11624 u8 reserved_at_40[0x18]; 11625 u8 log_sw_icm_size[0x8]; 11626 11627 u8 reserved_at_60[0x20]; 11628 11629 u8 sw_icm_start_addr[0x40]; 11630 11631 u8 reserved_at_c0[0x140]; 11632 }; 11633 11634 struct mlx5_ifc_geneve_tlv_option_bits { 11635 u8 modify_field_select[0x40]; 11636 11637 u8 reserved_at_40[0x18]; 11638 u8 geneve_option_fte_index[0x8]; 11639 11640 u8 option_class[0x10]; 11641 u8 option_type[0x8]; 11642 u8 reserved_at_78[0x3]; 11643 u8 option_data_length[0x5]; 11644 11645 u8 reserved_at_80[0x180]; 11646 }; 11647 11648 struct mlx5_ifc_create_umem_in_bits { 11649 u8 opcode[0x10]; 11650 u8 uid[0x10]; 11651 11652 u8 reserved_at_20[0x10]; 11653 u8 op_mod[0x10]; 11654 11655 u8 reserved_at_40[0x40]; 11656 11657 struct mlx5_ifc_umem_bits umem; 11658 }; 11659 11660 struct mlx5_ifc_create_umem_out_bits { 11661 u8 status[0x8]; 11662 u8 reserved_at_8[0x18]; 11663 11664 u8 syndrome[0x20]; 11665 11666 u8 reserved_at_40[0x8]; 11667 u8 umem_id[0x18]; 11668 11669 u8 reserved_at_60[0x20]; 11670 }; 11671 11672 struct mlx5_ifc_destroy_umem_in_bits { 11673 u8 opcode[0x10]; 11674 u8 uid[0x10]; 11675 11676 u8 reserved_at_20[0x10]; 11677 u8 op_mod[0x10]; 11678 11679 u8 reserved_at_40[0x8]; 11680 u8 umem_id[0x18]; 11681 11682 u8 reserved_at_60[0x20]; 11683 }; 11684 11685 struct mlx5_ifc_destroy_umem_out_bits { 11686 u8 status[0x8]; 11687 u8 reserved_at_8[0x18]; 11688 11689 u8 syndrome[0x20]; 11690 11691 u8 reserved_at_40[0x40]; 11692 }; 11693 11694 struct mlx5_ifc_create_uctx_in_bits { 11695 u8 opcode[0x10]; 11696 u8 reserved_at_10[0x10]; 11697 11698 u8 reserved_at_20[0x10]; 11699 u8 op_mod[0x10]; 11700 11701 u8 reserved_at_40[0x40]; 11702 11703 struct mlx5_ifc_uctx_bits uctx; 11704 }; 11705 11706 struct mlx5_ifc_create_uctx_out_bits { 11707 u8 status[0x8]; 11708 u8 reserved_at_8[0x18]; 11709 11710 u8 syndrome[0x20]; 11711 11712 u8 reserved_at_40[0x10]; 11713 u8 uid[0x10]; 11714 11715 u8 reserved_at_60[0x20]; 11716 }; 11717 11718 struct mlx5_ifc_destroy_uctx_in_bits { 11719 u8 opcode[0x10]; 11720 u8 reserved_at_10[0x10]; 11721 11722 u8 reserved_at_20[0x10]; 11723 u8 op_mod[0x10]; 11724 11725 u8 reserved_at_40[0x10]; 11726 u8 uid[0x10]; 11727 11728 u8 reserved_at_60[0x20]; 11729 }; 11730 11731 struct mlx5_ifc_destroy_uctx_out_bits { 11732 u8 status[0x8]; 11733 u8 reserved_at_8[0x18]; 11734 11735 u8 syndrome[0x20]; 11736 11737 u8 reserved_at_40[0x40]; 11738 }; 11739 11740 struct mlx5_ifc_create_sw_icm_in_bits { 11741 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11742 struct mlx5_ifc_sw_icm_bits sw_icm; 11743 }; 11744 11745 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11746 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11747 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11748 }; 11749 11750 struct mlx5_ifc_mtrc_string_db_param_bits { 11751 u8 string_db_base_address[0x20]; 11752 11753 u8 reserved_at_20[0x8]; 11754 u8 string_db_size[0x18]; 11755 }; 11756 11757 struct mlx5_ifc_mtrc_cap_bits { 11758 u8 trace_owner[0x1]; 11759 u8 trace_to_memory[0x1]; 11760 u8 reserved_at_2[0x4]; 11761 u8 trc_ver[0x2]; 11762 u8 reserved_at_8[0x14]; 11763 u8 num_string_db[0x4]; 11764 11765 u8 first_string_trace[0x8]; 11766 u8 num_string_trace[0x8]; 11767 u8 reserved_at_30[0x28]; 11768 11769 u8 log_max_trace_buffer_size[0x8]; 11770 11771 u8 reserved_at_60[0x20]; 11772 11773 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11774 11775 u8 reserved_at_280[0x180]; 11776 }; 11777 11778 struct mlx5_ifc_mtrc_conf_bits { 11779 u8 reserved_at_0[0x1c]; 11780 u8 trace_mode[0x4]; 11781 u8 reserved_at_20[0x18]; 11782 u8 log_trace_buffer_size[0x8]; 11783 u8 trace_mkey[0x20]; 11784 u8 reserved_at_60[0x3a0]; 11785 }; 11786 11787 struct mlx5_ifc_mtrc_stdb_bits { 11788 u8 string_db_index[0x4]; 11789 u8 reserved_at_4[0x4]; 11790 u8 read_size[0x18]; 11791 u8 start_offset[0x20]; 11792 u8 string_db_data[]; 11793 }; 11794 11795 struct mlx5_ifc_mtrc_ctrl_bits { 11796 u8 trace_status[0x2]; 11797 u8 reserved_at_2[0x2]; 11798 u8 arm_event[0x1]; 11799 u8 reserved_at_5[0xb]; 11800 u8 modify_field_select[0x10]; 11801 u8 reserved_at_20[0x2b]; 11802 u8 current_timestamp52_32[0x15]; 11803 u8 current_timestamp31_0[0x20]; 11804 u8 reserved_at_80[0x180]; 11805 }; 11806 11807 struct mlx5_ifc_host_params_context_bits { 11808 u8 host_number[0x8]; 11809 u8 reserved_at_8[0x7]; 11810 u8 host_pf_disabled[0x1]; 11811 u8 host_num_of_vfs[0x10]; 11812 11813 u8 host_total_vfs[0x10]; 11814 u8 host_pci_bus[0x10]; 11815 11816 u8 reserved_at_40[0x10]; 11817 u8 host_pci_device[0x10]; 11818 11819 u8 reserved_at_60[0x10]; 11820 u8 host_pci_function[0x10]; 11821 11822 u8 reserved_at_80[0x180]; 11823 }; 11824 11825 struct mlx5_ifc_query_esw_functions_in_bits { 11826 u8 opcode[0x10]; 11827 u8 reserved_at_10[0x10]; 11828 11829 u8 reserved_at_20[0x10]; 11830 u8 op_mod[0x10]; 11831 11832 u8 reserved_at_40[0x40]; 11833 }; 11834 11835 struct mlx5_ifc_query_esw_functions_out_bits { 11836 u8 status[0x8]; 11837 u8 reserved_at_8[0x18]; 11838 11839 u8 syndrome[0x20]; 11840 11841 u8 reserved_at_40[0x40]; 11842 11843 struct mlx5_ifc_host_params_context_bits host_params_context; 11844 11845 u8 reserved_at_280[0x180]; 11846 u8 host_sf_enable[][0x40]; 11847 }; 11848 11849 struct mlx5_ifc_sf_partition_bits { 11850 u8 reserved_at_0[0x10]; 11851 u8 log_num_sf[0x8]; 11852 u8 log_sf_bar_size[0x8]; 11853 }; 11854 11855 struct mlx5_ifc_query_sf_partitions_out_bits { 11856 u8 status[0x8]; 11857 u8 reserved_at_8[0x18]; 11858 11859 u8 syndrome[0x20]; 11860 11861 u8 reserved_at_40[0x18]; 11862 u8 num_sf_partitions[0x8]; 11863 11864 u8 reserved_at_60[0x20]; 11865 11866 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11867 }; 11868 11869 struct mlx5_ifc_query_sf_partitions_in_bits { 11870 u8 opcode[0x10]; 11871 u8 reserved_at_10[0x10]; 11872 11873 u8 reserved_at_20[0x10]; 11874 u8 op_mod[0x10]; 11875 11876 u8 reserved_at_40[0x40]; 11877 }; 11878 11879 struct mlx5_ifc_dealloc_sf_out_bits { 11880 u8 status[0x8]; 11881 u8 reserved_at_8[0x18]; 11882 11883 u8 syndrome[0x20]; 11884 11885 u8 reserved_at_40[0x40]; 11886 }; 11887 11888 struct mlx5_ifc_dealloc_sf_in_bits { 11889 u8 opcode[0x10]; 11890 u8 reserved_at_10[0x10]; 11891 11892 u8 reserved_at_20[0x10]; 11893 u8 op_mod[0x10]; 11894 11895 u8 reserved_at_40[0x10]; 11896 u8 function_id[0x10]; 11897 11898 u8 reserved_at_60[0x20]; 11899 }; 11900 11901 struct mlx5_ifc_alloc_sf_out_bits { 11902 u8 status[0x8]; 11903 u8 reserved_at_8[0x18]; 11904 11905 u8 syndrome[0x20]; 11906 11907 u8 reserved_at_40[0x40]; 11908 }; 11909 11910 struct mlx5_ifc_alloc_sf_in_bits { 11911 u8 opcode[0x10]; 11912 u8 reserved_at_10[0x10]; 11913 11914 u8 reserved_at_20[0x10]; 11915 u8 op_mod[0x10]; 11916 11917 u8 reserved_at_40[0x10]; 11918 u8 function_id[0x10]; 11919 11920 u8 reserved_at_60[0x20]; 11921 }; 11922 11923 struct mlx5_ifc_affiliated_event_header_bits { 11924 u8 reserved_at_0[0x10]; 11925 u8 obj_type[0x10]; 11926 11927 u8 obj_id[0x20]; 11928 }; 11929 11930 enum { 11931 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11932 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11933 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11934 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11935 }; 11936 11937 enum { 11938 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11939 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11940 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11941 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11942 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11943 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11944 }; 11945 11946 enum { 11947 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11948 }; 11949 11950 enum { 11951 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11952 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11953 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11954 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11955 }; 11956 11957 enum { 11958 MLX5_IPSEC_ASO_MODE = 0x0, 11959 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11960 MLX5_IPSEC_ASO_INC_SN = 0x2, 11961 }; 11962 11963 struct mlx5_ifc_ipsec_aso_bits { 11964 u8 valid[0x1]; 11965 u8 reserved_at_201[0x1]; 11966 u8 mode[0x2]; 11967 u8 window_sz[0x2]; 11968 u8 soft_lft_arm[0x1]; 11969 u8 hard_lft_arm[0x1]; 11970 u8 remove_flow_enable[0x1]; 11971 u8 esn_event_arm[0x1]; 11972 u8 reserved_at_20a[0x16]; 11973 11974 u8 remove_flow_pkt_cnt[0x20]; 11975 11976 u8 remove_flow_soft_lft[0x20]; 11977 11978 u8 reserved_at_260[0x80]; 11979 11980 u8 mode_parameter[0x20]; 11981 11982 u8 replay_protection_window[0x100]; 11983 }; 11984 11985 struct mlx5_ifc_ipsec_obj_bits { 11986 u8 modify_field_select[0x40]; 11987 u8 full_offload[0x1]; 11988 u8 reserved_at_41[0x1]; 11989 u8 esn_en[0x1]; 11990 u8 esn_overlap[0x1]; 11991 u8 reserved_at_44[0x2]; 11992 u8 icv_length[0x2]; 11993 u8 reserved_at_48[0x4]; 11994 u8 aso_return_reg[0x4]; 11995 u8 reserved_at_50[0x10]; 11996 11997 u8 esn_msb[0x20]; 11998 11999 u8 reserved_at_80[0x8]; 12000 u8 dekn[0x18]; 12001 12002 u8 salt[0x20]; 12003 12004 u8 implicit_iv[0x40]; 12005 12006 u8 reserved_at_100[0x8]; 12007 u8 ipsec_aso_access_pd[0x18]; 12008 u8 reserved_at_120[0xe0]; 12009 12010 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12011 }; 12012 12013 struct mlx5_ifc_create_ipsec_obj_in_bits { 12014 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12015 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12016 }; 12017 12018 enum { 12019 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12020 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12021 }; 12022 12023 struct mlx5_ifc_query_ipsec_obj_out_bits { 12024 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12025 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12026 }; 12027 12028 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12029 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12030 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12031 }; 12032 12033 enum { 12034 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12035 }; 12036 12037 enum { 12038 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12039 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12040 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12041 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12042 }; 12043 12044 #define MLX5_MACSEC_ASO_INC_SN 0x2 12045 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12046 12047 struct mlx5_ifc_macsec_aso_bits { 12048 u8 valid[0x1]; 12049 u8 reserved_at_1[0x1]; 12050 u8 mode[0x2]; 12051 u8 window_size[0x2]; 12052 u8 soft_lifetime_arm[0x1]; 12053 u8 hard_lifetime_arm[0x1]; 12054 u8 remove_flow_enable[0x1]; 12055 u8 epn_event_arm[0x1]; 12056 u8 reserved_at_a[0x16]; 12057 12058 u8 remove_flow_packet_count[0x20]; 12059 12060 u8 remove_flow_soft_lifetime[0x20]; 12061 12062 u8 reserved_at_60[0x80]; 12063 12064 u8 mode_parameter[0x20]; 12065 12066 u8 replay_protection_window[8][0x20]; 12067 }; 12068 12069 struct mlx5_ifc_macsec_offload_obj_bits { 12070 u8 modify_field_select[0x40]; 12071 12072 u8 confidentiality_en[0x1]; 12073 u8 reserved_at_41[0x1]; 12074 u8 epn_en[0x1]; 12075 u8 epn_overlap[0x1]; 12076 u8 reserved_at_44[0x2]; 12077 u8 confidentiality_offset[0x2]; 12078 u8 reserved_at_48[0x4]; 12079 u8 aso_return_reg[0x4]; 12080 u8 reserved_at_50[0x10]; 12081 12082 u8 epn_msb[0x20]; 12083 12084 u8 reserved_at_80[0x8]; 12085 u8 dekn[0x18]; 12086 12087 u8 reserved_at_a0[0x20]; 12088 12089 u8 sci[0x40]; 12090 12091 u8 reserved_at_100[0x8]; 12092 u8 macsec_aso_access_pd[0x18]; 12093 12094 u8 reserved_at_120[0x60]; 12095 12096 u8 salt[3][0x20]; 12097 12098 u8 reserved_at_1e0[0x20]; 12099 12100 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12101 }; 12102 12103 struct mlx5_ifc_create_macsec_obj_in_bits { 12104 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12105 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12106 }; 12107 12108 struct mlx5_ifc_modify_macsec_obj_in_bits { 12109 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12110 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12111 }; 12112 12113 enum { 12114 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12115 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12116 }; 12117 12118 struct mlx5_ifc_query_macsec_obj_out_bits { 12119 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12120 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12121 }; 12122 12123 struct mlx5_ifc_wrapped_dek_bits { 12124 u8 gcm_iv[0x60]; 12125 12126 u8 reserved_at_60[0x20]; 12127 12128 u8 const0[0x1]; 12129 u8 key_size[0x1]; 12130 u8 reserved_at_82[0x2]; 12131 u8 key2_invalid[0x1]; 12132 u8 reserved_at_85[0x3]; 12133 u8 pd[0x18]; 12134 12135 u8 key_purpose[0x5]; 12136 u8 reserved_at_a5[0x13]; 12137 u8 kek_id[0x8]; 12138 12139 u8 reserved_at_c0[0x40]; 12140 12141 u8 key1[0x8][0x20]; 12142 12143 u8 key2[0x8][0x20]; 12144 12145 u8 reserved_at_300[0x40]; 12146 12147 u8 const1[0x1]; 12148 u8 reserved_at_341[0x1f]; 12149 12150 u8 reserved_at_360[0x20]; 12151 12152 u8 auth_tag[0x80]; 12153 }; 12154 12155 struct mlx5_ifc_encryption_key_obj_bits { 12156 u8 modify_field_select[0x40]; 12157 12158 u8 state[0x8]; 12159 u8 sw_wrapped[0x1]; 12160 u8 reserved_at_49[0xb]; 12161 u8 key_size[0x4]; 12162 u8 reserved_at_58[0x4]; 12163 u8 key_purpose[0x4]; 12164 12165 u8 reserved_at_60[0x8]; 12166 u8 pd[0x18]; 12167 12168 u8 reserved_at_80[0x100]; 12169 12170 u8 opaque[0x40]; 12171 12172 u8 reserved_at_1c0[0x40]; 12173 12174 u8 key[8][0x80]; 12175 12176 u8 sw_wrapped_dek[8][0x80]; 12177 12178 u8 reserved_at_a00[0x600]; 12179 }; 12180 12181 struct mlx5_ifc_create_encryption_key_in_bits { 12182 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12183 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12184 }; 12185 12186 struct mlx5_ifc_modify_encryption_key_in_bits { 12187 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12188 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12189 }; 12190 12191 enum { 12192 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12193 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12194 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12195 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12196 }; 12197 12198 struct mlx5_ifc_flow_meter_parameters_bits { 12199 u8 valid[0x1]; 12200 u8 bucket_overflow[0x1]; 12201 u8 start_color[0x2]; 12202 u8 both_buckets_on_green[0x1]; 12203 u8 reserved_at_5[0x1]; 12204 u8 meter_mode[0x2]; 12205 u8 reserved_at_8[0x18]; 12206 12207 u8 reserved_at_20[0x20]; 12208 12209 u8 reserved_at_40[0x3]; 12210 u8 cbs_exponent[0x5]; 12211 u8 cbs_mantissa[0x8]; 12212 u8 reserved_at_50[0x3]; 12213 u8 cir_exponent[0x5]; 12214 u8 cir_mantissa[0x8]; 12215 12216 u8 reserved_at_60[0x20]; 12217 12218 u8 reserved_at_80[0x3]; 12219 u8 ebs_exponent[0x5]; 12220 u8 ebs_mantissa[0x8]; 12221 u8 reserved_at_90[0x3]; 12222 u8 eir_exponent[0x5]; 12223 u8 eir_mantissa[0x8]; 12224 12225 u8 reserved_at_a0[0x60]; 12226 }; 12227 12228 struct mlx5_ifc_flow_meter_aso_obj_bits { 12229 u8 modify_field_select[0x40]; 12230 12231 u8 reserved_at_40[0x40]; 12232 12233 u8 reserved_at_80[0x8]; 12234 u8 meter_aso_access_pd[0x18]; 12235 12236 u8 reserved_at_a0[0x160]; 12237 12238 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12239 }; 12240 12241 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12242 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12243 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12244 }; 12245 12246 struct mlx5_ifc_int_kek_obj_bits { 12247 u8 modify_field_select[0x40]; 12248 12249 u8 state[0x8]; 12250 u8 auto_gen[0x1]; 12251 u8 reserved_at_49[0xb]; 12252 u8 key_size[0x4]; 12253 u8 reserved_at_58[0x8]; 12254 12255 u8 reserved_at_60[0x8]; 12256 u8 pd[0x18]; 12257 12258 u8 reserved_at_80[0x180]; 12259 u8 key[8][0x80]; 12260 12261 u8 reserved_at_600[0x200]; 12262 }; 12263 12264 struct mlx5_ifc_create_int_kek_obj_in_bits { 12265 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12266 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12267 }; 12268 12269 struct mlx5_ifc_create_int_kek_obj_out_bits { 12270 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12271 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12272 }; 12273 12274 struct mlx5_ifc_sampler_obj_bits { 12275 u8 modify_field_select[0x40]; 12276 12277 u8 table_type[0x8]; 12278 u8 level[0x8]; 12279 u8 reserved_at_50[0xf]; 12280 u8 ignore_flow_level[0x1]; 12281 12282 u8 sample_ratio[0x20]; 12283 12284 u8 reserved_at_80[0x8]; 12285 u8 sample_table_id[0x18]; 12286 12287 u8 reserved_at_a0[0x8]; 12288 u8 default_table_id[0x18]; 12289 12290 u8 sw_steering_icm_address_rx[0x40]; 12291 u8 sw_steering_icm_address_tx[0x40]; 12292 12293 u8 reserved_at_140[0xa0]; 12294 }; 12295 12296 struct mlx5_ifc_create_sampler_obj_in_bits { 12297 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12298 struct mlx5_ifc_sampler_obj_bits sampler_object; 12299 }; 12300 12301 struct mlx5_ifc_query_sampler_obj_out_bits { 12302 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12303 struct mlx5_ifc_sampler_obj_bits sampler_object; 12304 }; 12305 12306 enum { 12307 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12308 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12309 }; 12310 12311 enum { 12312 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12313 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12314 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12315 }; 12316 12317 struct mlx5_ifc_tls_static_params_bits { 12318 u8 const_2[0x2]; 12319 u8 tls_version[0x4]; 12320 u8 const_1[0x2]; 12321 u8 reserved_at_8[0x14]; 12322 u8 encryption_standard[0x4]; 12323 12324 u8 reserved_at_20[0x20]; 12325 12326 u8 initial_record_number[0x40]; 12327 12328 u8 resync_tcp_sn[0x20]; 12329 12330 u8 gcm_iv[0x20]; 12331 12332 u8 implicit_iv[0x40]; 12333 12334 u8 reserved_at_100[0x8]; 12335 u8 dek_index[0x18]; 12336 12337 u8 reserved_at_120[0xe0]; 12338 }; 12339 12340 struct mlx5_ifc_tls_progress_params_bits { 12341 u8 next_record_tcp_sn[0x20]; 12342 12343 u8 hw_resync_tcp_sn[0x20]; 12344 12345 u8 record_tracker_state[0x2]; 12346 u8 auth_state[0x2]; 12347 u8 reserved_at_44[0x4]; 12348 u8 hw_offset_record_number[0x18]; 12349 }; 12350 12351 enum { 12352 MLX5_MTT_PERM_READ = 1 << 0, 12353 MLX5_MTT_PERM_WRITE = 1 << 1, 12354 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12355 }; 12356 12357 enum { 12358 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12359 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12360 }; 12361 12362 struct mlx5_ifc_suspend_vhca_in_bits { 12363 u8 opcode[0x10]; 12364 u8 uid[0x10]; 12365 12366 u8 reserved_at_20[0x10]; 12367 u8 op_mod[0x10]; 12368 12369 u8 reserved_at_40[0x10]; 12370 u8 vhca_id[0x10]; 12371 12372 u8 reserved_at_60[0x20]; 12373 }; 12374 12375 struct mlx5_ifc_suspend_vhca_out_bits { 12376 u8 status[0x8]; 12377 u8 reserved_at_8[0x18]; 12378 12379 u8 syndrome[0x20]; 12380 12381 u8 reserved_at_40[0x40]; 12382 }; 12383 12384 enum { 12385 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12386 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12387 }; 12388 12389 struct mlx5_ifc_resume_vhca_in_bits { 12390 u8 opcode[0x10]; 12391 u8 uid[0x10]; 12392 12393 u8 reserved_at_20[0x10]; 12394 u8 op_mod[0x10]; 12395 12396 u8 reserved_at_40[0x10]; 12397 u8 vhca_id[0x10]; 12398 12399 u8 reserved_at_60[0x20]; 12400 }; 12401 12402 struct mlx5_ifc_resume_vhca_out_bits { 12403 u8 status[0x8]; 12404 u8 reserved_at_8[0x18]; 12405 12406 u8 syndrome[0x20]; 12407 12408 u8 reserved_at_40[0x40]; 12409 }; 12410 12411 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12412 u8 opcode[0x10]; 12413 u8 uid[0x10]; 12414 12415 u8 reserved_at_20[0x10]; 12416 u8 op_mod[0x10]; 12417 12418 u8 incremental[0x1]; 12419 u8 reserved_at_41[0xf]; 12420 u8 vhca_id[0x10]; 12421 12422 u8 reserved_at_60[0x20]; 12423 }; 12424 12425 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12426 u8 status[0x8]; 12427 u8 reserved_at_8[0x18]; 12428 12429 u8 syndrome[0x20]; 12430 12431 u8 reserved_at_40[0x40]; 12432 12433 u8 required_umem_size[0x20]; 12434 12435 u8 reserved_at_a0[0x160]; 12436 }; 12437 12438 struct mlx5_ifc_save_vhca_state_in_bits { 12439 u8 opcode[0x10]; 12440 u8 uid[0x10]; 12441 12442 u8 reserved_at_20[0x10]; 12443 u8 op_mod[0x10]; 12444 12445 u8 incremental[0x1]; 12446 u8 set_track[0x1]; 12447 u8 reserved_at_42[0xe]; 12448 u8 vhca_id[0x10]; 12449 12450 u8 reserved_at_60[0x20]; 12451 12452 u8 va[0x40]; 12453 12454 u8 mkey[0x20]; 12455 12456 u8 size[0x20]; 12457 }; 12458 12459 struct mlx5_ifc_save_vhca_state_out_bits { 12460 u8 status[0x8]; 12461 u8 reserved_at_8[0x18]; 12462 12463 u8 syndrome[0x20]; 12464 12465 u8 actual_image_size[0x20]; 12466 12467 u8 reserved_at_60[0x20]; 12468 }; 12469 12470 struct mlx5_ifc_load_vhca_state_in_bits { 12471 u8 opcode[0x10]; 12472 u8 uid[0x10]; 12473 12474 u8 reserved_at_20[0x10]; 12475 u8 op_mod[0x10]; 12476 12477 u8 reserved_at_40[0x10]; 12478 u8 vhca_id[0x10]; 12479 12480 u8 reserved_at_60[0x20]; 12481 12482 u8 va[0x40]; 12483 12484 u8 mkey[0x20]; 12485 12486 u8 size[0x20]; 12487 }; 12488 12489 struct mlx5_ifc_load_vhca_state_out_bits { 12490 u8 status[0x8]; 12491 u8 reserved_at_8[0x18]; 12492 12493 u8 syndrome[0x20]; 12494 12495 u8 reserved_at_40[0x40]; 12496 }; 12497 12498 struct mlx5_ifc_adv_virtualization_cap_bits { 12499 u8 reserved_at_0[0x3]; 12500 u8 pg_track_log_max_num[0x5]; 12501 u8 pg_track_max_num_range[0x8]; 12502 u8 pg_track_log_min_addr_space[0x8]; 12503 u8 pg_track_log_max_addr_space[0x8]; 12504 12505 u8 reserved_at_20[0x3]; 12506 u8 pg_track_log_min_msg_size[0x5]; 12507 u8 reserved_at_28[0x3]; 12508 u8 pg_track_log_max_msg_size[0x5]; 12509 u8 reserved_at_30[0x3]; 12510 u8 pg_track_log_min_page_size[0x5]; 12511 u8 reserved_at_38[0x3]; 12512 u8 pg_track_log_max_page_size[0x5]; 12513 12514 u8 reserved_at_40[0x7c0]; 12515 }; 12516 12517 struct mlx5_ifc_page_track_report_entry_bits { 12518 u8 dirty_address_high[0x20]; 12519 12520 u8 dirty_address_low[0x20]; 12521 }; 12522 12523 enum { 12524 MLX5_PAGE_TRACK_STATE_TRACKING, 12525 MLX5_PAGE_TRACK_STATE_REPORTING, 12526 MLX5_PAGE_TRACK_STATE_ERROR, 12527 }; 12528 12529 struct mlx5_ifc_page_track_range_bits { 12530 u8 start_address[0x40]; 12531 12532 u8 length[0x40]; 12533 }; 12534 12535 struct mlx5_ifc_page_track_bits { 12536 u8 modify_field_select[0x40]; 12537 12538 u8 reserved_at_40[0x10]; 12539 u8 vhca_id[0x10]; 12540 12541 u8 reserved_at_60[0x20]; 12542 12543 u8 state[0x4]; 12544 u8 track_type[0x4]; 12545 u8 log_addr_space_size[0x8]; 12546 u8 reserved_at_90[0x3]; 12547 u8 log_page_size[0x5]; 12548 u8 reserved_at_98[0x3]; 12549 u8 log_msg_size[0x5]; 12550 12551 u8 reserved_at_a0[0x8]; 12552 u8 reporting_qpn[0x18]; 12553 12554 u8 reserved_at_c0[0x18]; 12555 u8 num_ranges[0x8]; 12556 12557 u8 reserved_at_e0[0x20]; 12558 12559 u8 range_start_address[0x40]; 12560 12561 u8 length[0x40]; 12562 12563 struct mlx5_ifc_page_track_range_bits track_range[0]; 12564 }; 12565 12566 struct mlx5_ifc_create_page_track_obj_in_bits { 12567 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12568 struct mlx5_ifc_page_track_bits obj_context; 12569 }; 12570 12571 struct mlx5_ifc_modify_page_track_obj_in_bits { 12572 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12573 struct mlx5_ifc_page_track_bits obj_context; 12574 }; 12575 12576 #endif /* MLX5_IFC_H */ 12577