1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 85 }; 86 87 enum { 88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 90 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_MKEY = 0xff01, 96 MLX5_OBJ_TYPE_QP = 0xff02, 97 MLX5_OBJ_TYPE_PSV = 0xff03, 98 MLX5_OBJ_TYPE_RMP = 0xff04, 99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 100 MLX5_OBJ_TYPE_RQ = 0xff06, 101 MLX5_OBJ_TYPE_SQ = 0xff07, 102 MLX5_OBJ_TYPE_TIR = 0xff08, 103 MLX5_OBJ_TYPE_TIS = 0xff09, 104 MLX5_OBJ_TYPE_DCT = 0xff0a, 105 MLX5_OBJ_TYPE_XRQ = 0xff0b, 106 MLX5_OBJ_TYPE_RQT = 0xff0e, 107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 108 MLX5_OBJ_TYPE_CQ = 0xff10, 109 }; 110 111 enum { 112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 114 MLX5_CMD_OP_INIT_HCA = 0x102, 115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 116 MLX5_CMD_OP_ENABLE_HCA = 0x104, 117 MLX5_CMD_OP_DISABLE_HCA = 0x105, 118 MLX5_CMD_OP_QUERY_PAGES = 0x107, 119 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 120 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 121 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 122 MLX5_CMD_OP_SET_ISSI = 0x10b, 123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 125 MLX5_CMD_OP_ALLOC_SF = 0x113, 126 MLX5_CMD_OP_DEALLOC_SF = 0x114, 127 MLX5_CMD_OP_CREATE_MKEY = 0x200, 128 MLX5_CMD_OP_QUERY_MKEY = 0x201, 129 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 130 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 131 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 132 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 133 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 134 MLX5_CMD_OP_CREATE_EQ = 0x301, 135 MLX5_CMD_OP_DESTROY_EQ = 0x302, 136 MLX5_CMD_OP_QUERY_EQ = 0x303, 137 MLX5_CMD_OP_GEN_EQE = 0x304, 138 MLX5_CMD_OP_CREATE_CQ = 0x400, 139 MLX5_CMD_OP_DESTROY_CQ = 0x401, 140 MLX5_CMD_OP_QUERY_CQ = 0x402, 141 MLX5_CMD_OP_MODIFY_CQ = 0x403, 142 MLX5_CMD_OP_CREATE_QP = 0x500, 143 MLX5_CMD_OP_DESTROY_QP = 0x501, 144 MLX5_CMD_OP_RST2INIT_QP = 0x502, 145 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 146 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 147 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 148 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 149 MLX5_CMD_OP_2ERR_QP = 0x507, 150 MLX5_CMD_OP_2RST_QP = 0x50a, 151 MLX5_CMD_OP_QUERY_QP = 0x50b, 152 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 153 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 154 MLX5_CMD_OP_CREATE_PSV = 0x600, 155 MLX5_CMD_OP_DESTROY_PSV = 0x601, 156 MLX5_CMD_OP_CREATE_SRQ = 0x700, 157 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 158 MLX5_CMD_OP_QUERY_SRQ = 0x702, 159 MLX5_CMD_OP_ARM_RQ = 0x703, 160 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 161 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 162 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 163 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 164 MLX5_CMD_OP_CREATE_DCT = 0x710, 165 MLX5_CMD_OP_DESTROY_DCT = 0x711, 166 MLX5_CMD_OP_DRAIN_DCT = 0x712, 167 MLX5_CMD_OP_QUERY_DCT = 0x713, 168 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 169 MLX5_CMD_OP_CREATE_XRQ = 0x717, 170 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 171 MLX5_CMD_OP_QUERY_XRQ = 0x719, 172 MLX5_CMD_OP_ARM_XRQ = 0x71a, 173 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 174 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 175 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 176 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 177 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 178 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 179 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 180 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 181 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 182 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 183 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 184 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 185 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 186 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 187 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 188 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 191 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 192 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 193 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 194 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 195 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 196 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 197 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 198 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 199 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 200 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 201 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 202 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 203 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 204 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 205 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 206 MLX5_CMD_OP_ALLOC_PD = 0x800, 207 MLX5_CMD_OP_DEALLOC_PD = 0x801, 208 MLX5_CMD_OP_ALLOC_UAR = 0x802, 209 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 210 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 211 MLX5_CMD_OP_ACCESS_REG = 0x805, 212 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 213 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 214 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 215 MLX5_CMD_OP_MAD_IFC = 0x50d, 216 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 217 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 218 MLX5_CMD_OP_NOP = 0x80d, 219 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 220 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 221 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 222 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 223 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 224 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 225 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 226 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 227 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 228 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 229 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 230 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 231 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 232 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 233 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 234 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 235 MLX5_CMD_OP_CREATE_LAG = 0x840, 236 MLX5_CMD_OP_MODIFY_LAG = 0x841, 237 MLX5_CMD_OP_QUERY_LAG = 0x842, 238 MLX5_CMD_OP_DESTROY_LAG = 0x843, 239 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 240 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 241 MLX5_CMD_OP_CREATE_TIR = 0x900, 242 MLX5_CMD_OP_MODIFY_TIR = 0x901, 243 MLX5_CMD_OP_DESTROY_TIR = 0x902, 244 MLX5_CMD_OP_QUERY_TIR = 0x903, 245 MLX5_CMD_OP_CREATE_SQ = 0x904, 246 MLX5_CMD_OP_MODIFY_SQ = 0x905, 247 MLX5_CMD_OP_DESTROY_SQ = 0x906, 248 MLX5_CMD_OP_QUERY_SQ = 0x907, 249 MLX5_CMD_OP_CREATE_RQ = 0x908, 250 MLX5_CMD_OP_MODIFY_RQ = 0x909, 251 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 252 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 253 MLX5_CMD_OP_QUERY_RQ = 0x90b, 254 MLX5_CMD_OP_CREATE_RMP = 0x90c, 255 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 256 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 257 MLX5_CMD_OP_QUERY_RMP = 0x90f, 258 MLX5_CMD_OP_CREATE_TIS = 0x912, 259 MLX5_CMD_OP_MODIFY_TIS = 0x913, 260 MLX5_CMD_OP_DESTROY_TIS = 0x914, 261 MLX5_CMD_OP_QUERY_TIS = 0x915, 262 MLX5_CMD_OP_CREATE_RQT = 0x916, 263 MLX5_CMD_OP_MODIFY_RQT = 0x917, 264 MLX5_CMD_OP_DESTROY_RQT = 0x918, 265 MLX5_CMD_OP_QUERY_RQT = 0x919, 266 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 267 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 268 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 269 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 270 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 271 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 272 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 274 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 275 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 276 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 277 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 278 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 279 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 280 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 281 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 282 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 283 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 284 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 285 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 286 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 287 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 288 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 289 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 290 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 291 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 292 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 293 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 294 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 295 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 296 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 297 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 298 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 299 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 300 MLX5_CMD_OP_MAX 301 }; 302 303 /* Valid range for general commands that don't work over an object */ 304 enum { 305 MLX5_CMD_OP_GENERAL_START = 0xb00, 306 MLX5_CMD_OP_GENERAL_END = 0xd00, 307 }; 308 309 struct mlx5_ifc_flow_table_fields_supported_bits { 310 u8 outer_dmac[0x1]; 311 u8 outer_smac[0x1]; 312 u8 outer_ether_type[0x1]; 313 u8 outer_ip_version[0x1]; 314 u8 outer_first_prio[0x1]; 315 u8 outer_first_cfi[0x1]; 316 u8 outer_first_vid[0x1]; 317 u8 outer_ipv4_ttl[0x1]; 318 u8 outer_second_prio[0x1]; 319 u8 outer_second_cfi[0x1]; 320 u8 outer_second_vid[0x1]; 321 u8 reserved_at_b[0x1]; 322 u8 outer_sip[0x1]; 323 u8 outer_dip[0x1]; 324 u8 outer_frag[0x1]; 325 u8 outer_ip_protocol[0x1]; 326 u8 outer_ip_ecn[0x1]; 327 u8 outer_ip_dscp[0x1]; 328 u8 outer_udp_sport[0x1]; 329 u8 outer_udp_dport[0x1]; 330 u8 outer_tcp_sport[0x1]; 331 u8 outer_tcp_dport[0x1]; 332 u8 outer_tcp_flags[0x1]; 333 u8 outer_gre_protocol[0x1]; 334 u8 outer_gre_key[0x1]; 335 u8 outer_vxlan_vni[0x1]; 336 u8 outer_geneve_vni[0x1]; 337 u8 outer_geneve_oam[0x1]; 338 u8 outer_geneve_protocol_type[0x1]; 339 u8 outer_geneve_opt_len[0x1]; 340 u8 reserved_at_1e[0x1]; 341 u8 source_eswitch_port[0x1]; 342 343 u8 inner_dmac[0x1]; 344 u8 inner_smac[0x1]; 345 u8 inner_ether_type[0x1]; 346 u8 inner_ip_version[0x1]; 347 u8 inner_first_prio[0x1]; 348 u8 inner_first_cfi[0x1]; 349 u8 inner_first_vid[0x1]; 350 u8 reserved_at_27[0x1]; 351 u8 inner_second_prio[0x1]; 352 u8 inner_second_cfi[0x1]; 353 u8 inner_second_vid[0x1]; 354 u8 reserved_at_2b[0x1]; 355 u8 inner_sip[0x1]; 356 u8 inner_dip[0x1]; 357 u8 inner_frag[0x1]; 358 u8 inner_ip_protocol[0x1]; 359 u8 inner_ip_ecn[0x1]; 360 u8 inner_ip_dscp[0x1]; 361 u8 inner_udp_sport[0x1]; 362 u8 inner_udp_dport[0x1]; 363 u8 inner_tcp_sport[0x1]; 364 u8 inner_tcp_dport[0x1]; 365 u8 inner_tcp_flags[0x1]; 366 u8 reserved_at_37[0x9]; 367 368 u8 geneve_tlv_option_0_data[0x1]; 369 u8 reserved_at_41[0x4]; 370 u8 outer_first_mpls_over_udp[0x4]; 371 u8 outer_first_mpls_over_gre[0x4]; 372 u8 inner_first_mpls[0x4]; 373 u8 outer_first_mpls[0x4]; 374 u8 reserved_at_55[0x2]; 375 u8 outer_esp_spi[0x1]; 376 u8 reserved_at_58[0x2]; 377 u8 bth_dst_qp[0x1]; 378 u8 reserved_at_5b[0x5]; 379 380 u8 reserved_at_60[0x18]; 381 u8 metadata_reg_c_7[0x1]; 382 u8 metadata_reg_c_6[0x1]; 383 u8 metadata_reg_c_5[0x1]; 384 u8 metadata_reg_c_4[0x1]; 385 u8 metadata_reg_c_3[0x1]; 386 u8 metadata_reg_c_2[0x1]; 387 u8 metadata_reg_c_1[0x1]; 388 u8 metadata_reg_c_0[0x1]; 389 }; 390 391 struct mlx5_ifc_flow_table_prop_layout_bits { 392 u8 ft_support[0x1]; 393 u8 reserved_at_1[0x1]; 394 u8 flow_counter[0x1]; 395 u8 flow_modify_en[0x1]; 396 u8 modify_root[0x1]; 397 u8 identified_miss_table_mode[0x1]; 398 u8 flow_table_modify[0x1]; 399 u8 reformat[0x1]; 400 u8 decap[0x1]; 401 u8 reserved_at_9[0x1]; 402 u8 pop_vlan[0x1]; 403 u8 push_vlan[0x1]; 404 u8 reserved_at_c[0x1]; 405 u8 pop_vlan_2[0x1]; 406 u8 push_vlan_2[0x1]; 407 u8 reformat_and_vlan_action[0x1]; 408 u8 reserved_at_10[0x1]; 409 u8 sw_owner[0x1]; 410 u8 reformat_l3_tunnel_to_l2[0x1]; 411 u8 reformat_l2_to_l3_tunnel[0x1]; 412 u8 reformat_and_modify_action[0x1]; 413 u8 ignore_flow_level[0x1]; 414 u8 reserved_at_16[0x1]; 415 u8 table_miss_action_domain[0x1]; 416 u8 termination_table[0x1]; 417 u8 reformat_and_fwd_to_table[0x1]; 418 u8 reserved_at_1a[0x6]; 419 u8 reserved_at_20[0x2]; 420 u8 log_max_ft_size[0x6]; 421 u8 log_max_modify_header_context[0x8]; 422 u8 max_modify_header_actions[0x8]; 423 u8 max_ft_level[0x8]; 424 425 u8 reserved_at_40[0x20]; 426 427 u8 reserved_at_60[0x18]; 428 u8 log_max_ft_num[0x8]; 429 430 u8 reserved_at_80[0x18]; 431 u8 log_max_destination[0x8]; 432 433 u8 log_max_flow_counter[0x8]; 434 u8 reserved_at_a8[0x10]; 435 u8 log_max_flow[0x8]; 436 437 u8 reserved_at_c0[0x40]; 438 439 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 440 441 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 442 }; 443 444 struct mlx5_ifc_odp_per_transport_service_cap_bits { 445 u8 send[0x1]; 446 u8 receive[0x1]; 447 u8 write[0x1]; 448 u8 read[0x1]; 449 u8 atomic[0x1]; 450 u8 srq_receive[0x1]; 451 u8 reserved_at_6[0x1a]; 452 }; 453 454 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 455 u8 smac_47_16[0x20]; 456 457 u8 smac_15_0[0x10]; 458 u8 ethertype[0x10]; 459 460 u8 dmac_47_16[0x20]; 461 462 u8 dmac_15_0[0x10]; 463 u8 first_prio[0x3]; 464 u8 first_cfi[0x1]; 465 u8 first_vid[0xc]; 466 467 u8 ip_protocol[0x8]; 468 u8 ip_dscp[0x6]; 469 u8 ip_ecn[0x2]; 470 u8 cvlan_tag[0x1]; 471 u8 svlan_tag[0x1]; 472 u8 frag[0x1]; 473 u8 ip_version[0x4]; 474 u8 tcp_flags[0x9]; 475 476 u8 tcp_sport[0x10]; 477 u8 tcp_dport[0x10]; 478 479 u8 reserved_at_c0[0x18]; 480 u8 ttl_hoplimit[0x8]; 481 482 u8 udp_sport[0x10]; 483 u8 udp_dport[0x10]; 484 485 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 486 487 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 488 }; 489 490 struct mlx5_ifc_nvgre_key_bits { 491 u8 hi[0x18]; 492 u8 lo[0x8]; 493 }; 494 495 union mlx5_ifc_gre_key_bits { 496 struct mlx5_ifc_nvgre_key_bits nvgre; 497 u8 key[0x20]; 498 }; 499 500 struct mlx5_ifc_fte_match_set_misc_bits { 501 u8 gre_c_present[0x1]; 502 u8 reserved_at_1[0x1]; 503 u8 gre_k_present[0x1]; 504 u8 gre_s_present[0x1]; 505 u8 source_vhca_port[0x4]; 506 u8 source_sqn[0x18]; 507 508 u8 source_eswitch_owner_vhca_id[0x10]; 509 u8 source_port[0x10]; 510 511 u8 outer_second_prio[0x3]; 512 u8 outer_second_cfi[0x1]; 513 u8 outer_second_vid[0xc]; 514 u8 inner_second_prio[0x3]; 515 u8 inner_second_cfi[0x1]; 516 u8 inner_second_vid[0xc]; 517 518 u8 outer_second_cvlan_tag[0x1]; 519 u8 inner_second_cvlan_tag[0x1]; 520 u8 outer_second_svlan_tag[0x1]; 521 u8 inner_second_svlan_tag[0x1]; 522 u8 reserved_at_64[0xc]; 523 u8 gre_protocol[0x10]; 524 525 union mlx5_ifc_gre_key_bits gre_key; 526 527 u8 vxlan_vni[0x18]; 528 u8 reserved_at_b8[0x8]; 529 530 u8 geneve_vni[0x18]; 531 u8 reserved_at_d8[0x7]; 532 u8 geneve_oam[0x1]; 533 534 u8 reserved_at_e0[0xc]; 535 u8 outer_ipv6_flow_label[0x14]; 536 537 u8 reserved_at_100[0xc]; 538 u8 inner_ipv6_flow_label[0x14]; 539 540 u8 reserved_at_120[0xa]; 541 u8 geneve_opt_len[0x6]; 542 u8 geneve_protocol_type[0x10]; 543 544 u8 reserved_at_140[0x8]; 545 u8 bth_dst_qp[0x18]; 546 u8 reserved_at_160[0x20]; 547 u8 outer_esp_spi[0x20]; 548 u8 reserved_at_1a0[0x60]; 549 }; 550 551 struct mlx5_ifc_fte_match_mpls_bits { 552 u8 mpls_label[0x14]; 553 u8 mpls_exp[0x3]; 554 u8 mpls_s_bos[0x1]; 555 u8 mpls_ttl[0x8]; 556 }; 557 558 struct mlx5_ifc_fte_match_set_misc2_bits { 559 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 560 561 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 562 563 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 564 565 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 566 567 u8 metadata_reg_c_7[0x20]; 568 569 u8 metadata_reg_c_6[0x20]; 570 571 u8 metadata_reg_c_5[0x20]; 572 573 u8 metadata_reg_c_4[0x20]; 574 575 u8 metadata_reg_c_3[0x20]; 576 577 u8 metadata_reg_c_2[0x20]; 578 579 u8 metadata_reg_c_1[0x20]; 580 581 u8 metadata_reg_c_0[0x20]; 582 583 u8 metadata_reg_a[0x20]; 584 585 u8 metadata_reg_b[0x20]; 586 587 u8 reserved_at_1c0[0x40]; 588 }; 589 590 struct mlx5_ifc_fte_match_set_misc3_bits { 591 u8 inner_tcp_seq_num[0x20]; 592 593 u8 outer_tcp_seq_num[0x20]; 594 595 u8 inner_tcp_ack_num[0x20]; 596 597 u8 outer_tcp_ack_num[0x20]; 598 599 u8 reserved_at_80[0x8]; 600 u8 outer_vxlan_gpe_vni[0x18]; 601 602 u8 outer_vxlan_gpe_next_protocol[0x8]; 603 u8 outer_vxlan_gpe_flags[0x8]; 604 u8 reserved_at_b0[0x10]; 605 606 u8 icmp_header_data[0x20]; 607 608 u8 icmpv6_header_data[0x20]; 609 610 u8 icmp_type[0x8]; 611 u8 icmp_code[0x8]; 612 u8 icmpv6_type[0x8]; 613 u8 icmpv6_code[0x8]; 614 615 u8 geneve_tlv_option_0_data[0x20]; 616 617 u8 reserved_at_140[0xc0]; 618 }; 619 620 struct mlx5_ifc_cmd_pas_bits { 621 u8 pa_h[0x20]; 622 623 u8 pa_l[0x14]; 624 u8 reserved_at_34[0xc]; 625 }; 626 627 struct mlx5_ifc_uint64_bits { 628 u8 hi[0x20]; 629 630 u8 lo[0x20]; 631 }; 632 633 enum { 634 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 635 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 636 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 637 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 638 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 639 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 640 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 641 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 642 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 643 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 644 }; 645 646 struct mlx5_ifc_ads_bits { 647 u8 fl[0x1]; 648 u8 free_ar[0x1]; 649 u8 reserved_at_2[0xe]; 650 u8 pkey_index[0x10]; 651 652 u8 reserved_at_20[0x8]; 653 u8 grh[0x1]; 654 u8 mlid[0x7]; 655 u8 rlid[0x10]; 656 657 u8 ack_timeout[0x5]; 658 u8 reserved_at_45[0x3]; 659 u8 src_addr_index[0x8]; 660 u8 reserved_at_50[0x4]; 661 u8 stat_rate[0x4]; 662 u8 hop_limit[0x8]; 663 664 u8 reserved_at_60[0x4]; 665 u8 tclass[0x8]; 666 u8 flow_label[0x14]; 667 668 u8 rgid_rip[16][0x8]; 669 670 u8 reserved_at_100[0x4]; 671 u8 f_dscp[0x1]; 672 u8 f_ecn[0x1]; 673 u8 reserved_at_106[0x1]; 674 u8 f_eth_prio[0x1]; 675 u8 ecn[0x2]; 676 u8 dscp[0x6]; 677 u8 udp_sport[0x10]; 678 679 u8 dei_cfi[0x1]; 680 u8 eth_prio[0x3]; 681 u8 sl[0x4]; 682 u8 vhca_port_num[0x8]; 683 u8 rmac_47_32[0x10]; 684 685 u8 rmac_31_0[0x20]; 686 }; 687 688 struct mlx5_ifc_flow_table_nic_cap_bits { 689 u8 nic_rx_multi_path_tirs[0x1]; 690 u8 nic_rx_multi_path_tirs_fts[0x1]; 691 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 692 u8 reserved_at_3[0x4]; 693 u8 sw_owner_reformat_supported[0x1]; 694 u8 reserved_at_8[0x18]; 695 696 u8 encap_general_header[0x1]; 697 u8 reserved_at_21[0xa]; 698 u8 log_max_packet_reformat_context[0x5]; 699 u8 reserved_at_30[0x6]; 700 u8 max_encap_header_size[0xa]; 701 u8 reserved_at_40[0x1c0]; 702 703 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 704 705 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 706 707 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 708 709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 710 711 u8 reserved_at_a00[0x200]; 712 713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 714 715 u8 reserved_at_e00[0x1200]; 716 717 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 718 719 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 720 721 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 722 723 u8 reserved_at_20c0[0x5f40]; 724 }; 725 726 enum { 727 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 728 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 729 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 730 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 731 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 732 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 733 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 734 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 735 }; 736 737 struct mlx5_ifc_flow_table_eswitch_cap_bits { 738 u8 fdb_to_vport_reg_c_id[0x8]; 739 u8 reserved_at_8[0xd]; 740 u8 fdb_modify_header_fwd_to_table[0x1]; 741 u8 reserved_at_16[0x1]; 742 u8 flow_source[0x1]; 743 u8 reserved_at_18[0x2]; 744 u8 multi_fdb_encap[0x1]; 745 u8 egress_acl_forward_to_vport[0x1]; 746 u8 fdb_multi_path_to_table[0x1]; 747 u8 reserved_at_1d[0x3]; 748 749 u8 reserved_at_20[0x1e0]; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 756 757 u8 reserved_at_800[0x1000]; 758 759 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 760 761 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 762 763 u8 sw_steering_uplink_icm_address_rx[0x40]; 764 765 u8 sw_steering_uplink_icm_address_tx[0x40]; 766 767 u8 reserved_at_1900[0x6700]; 768 }; 769 770 enum { 771 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 772 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 773 }; 774 775 struct mlx5_ifc_e_switch_cap_bits { 776 u8 vport_svlan_strip[0x1]; 777 u8 vport_cvlan_strip[0x1]; 778 u8 vport_svlan_insert[0x1]; 779 u8 vport_cvlan_insert_if_not_exist[0x1]; 780 u8 vport_cvlan_insert_overwrite[0x1]; 781 u8 reserved_at_5[0x3]; 782 u8 esw_uplink_ingress_acl[0x1]; 783 u8 reserved_at_9[0x10]; 784 u8 esw_functions_changed[0x1]; 785 u8 reserved_at_1a[0x1]; 786 u8 ecpf_vport_exists[0x1]; 787 u8 counter_eswitch_affinity[0x1]; 788 u8 merged_eswitch[0x1]; 789 u8 nic_vport_node_guid_modify[0x1]; 790 u8 nic_vport_port_guid_modify[0x1]; 791 792 u8 vxlan_encap_decap[0x1]; 793 u8 nvgre_encap_decap[0x1]; 794 u8 reserved_at_22[0x1]; 795 u8 log_max_fdb_encap_uplink[0x5]; 796 u8 reserved_at_21[0x3]; 797 u8 log_max_packet_reformat_context[0x5]; 798 u8 reserved_2b[0x6]; 799 u8 max_encap_header_size[0xa]; 800 801 u8 reserved_at_40[0xb]; 802 u8 log_max_esw_sf[0x5]; 803 u8 esw_sf_base_id[0x10]; 804 805 u8 reserved_at_60[0x7a0]; 806 807 }; 808 809 struct mlx5_ifc_qos_cap_bits { 810 u8 packet_pacing[0x1]; 811 u8 esw_scheduling[0x1]; 812 u8 esw_bw_share[0x1]; 813 u8 esw_rate_limit[0x1]; 814 u8 reserved_at_4[0x1]; 815 u8 packet_pacing_burst_bound[0x1]; 816 u8 packet_pacing_typical_size[0x1]; 817 u8 reserved_at_7[0x4]; 818 u8 packet_pacing_uid[0x1]; 819 u8 reserved_at_c[0x14]; 820 821 u8 reserved_at_20[0x20]; 822 823 u8 packet_pacing_max_rate[0x20]; 824 825 u8 packet_pacing_min_rate[0x20]; 826 827 u8 reserved_at_80[0x10]; 828 u8 packet_pacing_rate_table_size[0x10]; 829 830 u8 esw_element_type[0x10]; 831 u8 esw_tsar_type[0x10]; 832 833 u8 reserved_at_c0[0x10]; 834 u8 max_qos_para_vport[0x10]; 835 836 u8 max_tsar_bw_share[0x20]; 837 838 u8 reserved_at_100[0x700]; 839 }; 840 841 struct mlx5_ifc_debug_cap_bits { 842 u8 core_dump_general[0x1]; 843 u8 core_dump_qp[0x1]; 844 u8 reserved_at_2[0x7]; 845 u8 resource_dump[0x1]; 846 u8 reserved_at_a[0x16]; 847 848 u8 reserved_at_20[0x2]; 849 u8 stall_detect[0x1]; 850 u8 reserved_at_23[0x1d]; 851 852 u8 reserved_at_40[0x7c0]; 853 }; 854 855 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 856 u8 csum_cap[0x1]; 857 u8 vlan_cap[0x1]; 858 u8 lro_cap[0x1]; 859 u8 lro_psh_flag[0x1]; 860 u8 lro_time_stamp[0x1]; 861 u8 reserved_at_5[0x2]; 862 u8 wqe_vlan_insert[0x1]; 863 u8 self_lb_en_modifiable[0x1]; 864 u8 reserved_at_9[0x2]; 865 u8 max_lso_cap[0x5]; 866 u8 multi_pkt_send_wqe[0x2]; 867 u8 wqe_inline_mode[0x2]; 868 u8 rss_ind_tbl_cap[0x4]; 869 u8 reg_umr_sq[0x1]; 870 u8 scatter_fcs[0x1]; 871 u8 enhanced_multi_pkt_send_wqe[0x1]; 872 u8 tunnel_lso_const_out_ip_id[0x1]; 873 u8 reserved_at_1c[0x2]; 874 u8 tunnel_stateless_gre[0x1]; 875 u8 tunnel_stateless_vxlan[0x1]; 876 877 u8 swp[0x1]; 878 u8 swp_csum[0x1]; 879 u8 swp_lso[0x1]; 880 u8 cqe_checksum_full[0x1]; 881 u8 reserved_at_24[0x5]; 882 u8 tunnel_stateless_ip_over_ip[0x1]; 883 u8 reserved_at_2a[0x6]; 884 u8 max_vxlan_udp_ports[0x8]; 885 u8 reserved_at_38[0x6]; 886 u8 max_geneve_opt_len[0x1]; 887 u8 tunnel_stateless_geneve_rx[0x1]; 888 889 u8 reserved_at_40[0x10]; 890 u8 lro_min_mss_size[0x10]; 891 892 u8 reserved_at_60[0x120]; 893 894 u8 lro_timer_supported_periods[4][0x20]; 895 896 u8 reserved_at_200[0x600]; 897 }; 898 899 struct mlx5_ifc_roce_cap_bits { 900 u8 roce_apm[0x1]; 901 u8 reserved_at_1[0x1f]; 902 903 u8 reserved_at_20[0x60]; 904 905 u8 reserved_at_80[0xc]; 906 u8 l3_type[0x4]; 907 u8 reserved_at_90[0x8]; 908 u8 roce_version[0x8]; 909 910 u8 reserved_at_a0[0x10]; 911 u8 r_roce_dest_udp_port[0x10]; 912 913 u8 r_roce_max_src_udp_port[0x10]; 914 u8 r_roce_min_src_udp_port[0x10]; 915 916 u8 reserved_at_e0[0x10]; 917 u8 roce_address_table_size[0x10]; 918 919 u8 reserved_at_100[0x700]; 920 }; 921 922 struct mlx5_ifc_sync_steering_in_bits { 923 u8 opcode[0x10]; 924 u8 uid[0x10]; 925 926 u8 reserved_at_20[0x10]; 927 u8 op_mod[0x10]; 928 929 u8 reserved_at_40[0xc0]; 930 }; 931 932 struct mlx5_ifc_sync_steering_out_bits { 933 u8 status[0x8]; 934 u8 reserved_at_8[0x18]; 935 936 u8 syndrome[0x20]; 937 938 u8 reserved_at_40[0x40]; 939 }; 940 941 struct mlx5_ifc_device_mem_cap_bits { 942 u8 memic[0x1]; 943 u8 reserved_at_1[0x1f]; 944 945 u8 reserved_at_20[0xb]; 946 u8 log_min_memic_alloc_size[0x5]; 947 u8 reserved_at_30[0x8]; 948 u8 log_max_memic_addr_alignment[0x8]; 949 950 u8 memic_bar_start_addr[0x40]; 951 952 u8 memic_bar_size[0x20]; 953 954 u8 max_memic_size[0x20]; 955 956 u8 steering_sw_icm_start_address[0x40]; 957 958 u8 reserved_at_100[0x8]; 959 u8 log_header_modify_sw_icm_size[0x8]; 960 u8 reserved_at_110[0x2]; 961 u8 log_sw_icm_alloc_granularity[0x6]; 962 u8 log_steering_sw_icm_size[0x8]; 963 964 u8 reserved_at_120[0x20]; 965 966 u8 header_modify_sw_icm_start_address[0x40]; 967 968 u8 reserved_at_180[0x680]; 969 }; 970 971 struct mlx5_ifc_device_event_cap_bits { 972 u8 user_affiliated_events[4][0x40]; 973 974 u8 user_unaffiliated_events[4][0x40]; 975 }; 976 977 struct mlx5_ifc_device_virtio_emulation_cap_bits { 978 u8 reserved_at_0[0x20]; 979 980 u8 reserved_at_20[0x13]; 981 u8 log_doorbell_stride[0x5]; 982 u8 reserved_at_38[0x3]; 983 u8 log_doorbell_bar_size[0x5]; 984 985 u8 doorbell_bar_offset[0x40]; 986 987 u8 reserved_at_80[0x780]; 988 }; 989 990 enum { 991 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 992 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 993 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 994 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 995 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 996 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 997 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 998 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 999 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1000 }; 1001 1002 enum { 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1009 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1010 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1011 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1012 }; 1013 1014 struct mlx5_ifc_atomic_caps_bits { 1015 u8 reserved_at_0[0x40]; 1016 1017 u8 atomic_req_8B_endianness_mode[0x2]; 1018 u8 reserved_at_42[0x4]; 1019 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1020 1021 u8 reserved_at_47[0x19]; 1022 1023 u8 reserved_at_60[0x20]; 1024 1025 u8 reserved_at_80[0x10]; 1026 u8 atomic_operations[0x10]; 1027 1028 u8 reserved_at_a0[0x10]; 1029 u8 atomic_size_qp[0x10]; 1030 1031 u8 reserved_at_c0[0x10]; 1032 u8 atomic_size_dc[0x10]; 1033 1034 u8 reserved_at_e0[0x720]; 1035 }; 1036 1037 struct mlx5_ifc_odp_cap_bits { 1038 u8 reserved_at_0[0x40]; 1039 1040 u8 sig[0x1]; 1041 u8 reserved_at_41[0x1f]; 1042 1043 u8 reserved_at_60[0x20]; 1044 1045 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1046 1047 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1048 1049 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1050 1051 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1052 1053 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1054 1055 u8 reserved_at_120[0x6E0]; 1056 }; 1057 1058 struct mlx5_ifc_calc_op { 1059 u8 reserved_at_0[0x10]; 1060 u8 reserved_at_10[0x9]; 1061 u8 op_swap_endianness[0x1]; 1062 u8 op_min[0x1]; 1063 u8 op_xor[0x1]; 1064 u8 op_or[0x1]; 1065 u8 op_and[0x1]; 1066 u8 op_max[0x1]; 1067 u8 op_add[0x1]; 1068 }; 1069 1070 struct mlx5_ifc_vector_calc_cap_bits { 1071 u8 calc_matrix[0x1]; 1072 u8 reserved_at_1[0x1f]; 1073 u8 reserved_at_20[0x8]; 1074 u8 max_vec_count[0x8]; 1075 u8 reserved_at_30[0xd]; 1076 u8 max_chunk_size[0x3]; 1077 struct mlx5_ifc_calc_op calc0; 1078 struct mlx5_ifc_calc_op calc1; 1079 struct mlx5_ifc_calc_op calc2; 1080 struct mlx5_ifc_calc_op calc3; 1081 1082 u8 reserved_at_c0[0x720]; 1083 }; 1084 1085 struct mlx5_ifc_tls_cap_bits { 1086 u8 tls_1_2_aes_gcm_128[0x1]; 1087 u8 tls_1_3_aes_gcm_128[0x1]; 1088 u8 tls_1_2_aes_gcm_256[0x1]; 1089 u8 tls_1_3_aes_gcm_256[0x1]; 1090 u8 reserved_at_4[0x1c]; 1091 1092 u8 reserved_at_20[0x7e0]; 1093 }; 1094 1095 enum { 1096 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1097 MLX5_WQ_TYPE_CYCLIC = 0x1, 1098 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1099 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1100 }; 1101 1102 enum { 1103 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1104 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1105 }; 1106 1107 enum { 1108 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1109 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1110 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1111 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1112 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1113 }; 1114 1115 enum { 1116 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1117 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1118 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1119 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1120 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1121 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1122 }; 1123 1124 enum { 1125 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1126 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1127 }; 1128 1129 enum { 1130 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1131 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1132 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1133 }; 1134 1135 enum { 1136 MLX5_CAP_PORT_TYPE_IB = 0x0, 1137 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1138 }; 1139 1140 enum { 1141 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1142 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1143 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1144 }; 1145 1146 enum { 1147 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1148 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1149 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1150 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1151 }; 1152 1153 enum { 1154 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1155 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1156 }; 1157 1158 #define MLX5_FC_BULK_SIZE_FACTOR 128 1159 1160 enum mlx5_fc_bulk_alloc_bitmask { 1161 MLX5_FC_BULK_128 = (1 << 0), 1162 MLX5_FC_BULK_256 = (1 << 1), 1163 MLX5_FC_BULK_512 = (1 << 2), 1164 MLX5_FC_BULK_1024 = (1 << 3), 1165 MLX5_FC_BULK_2048 = (1 << 4), 1166 MLX5_FC_BULK_4096 = (1 << 5), 1167 MLX5_FC_BULK_8192 = (1 << 6), 1168 MLX5_FC_BULK_16384 = (1 << 7), 1169 }; 1170 1171 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1172 1173 struct mlx5_ifc_cmd_hca_cap_bits { 1174 u8 reserved_at_0[0x30]; 1175 u8 vhca_id[0x10]; 1176 1177 u8 reserved_at_40[0x40]; 1178 1179 u8 log_max_srq_sz[0x8]; 1180 u8 log_max_qp_sz[0x8]; 1181 u8 event_cap[0x1]; 1182 u8 reserved_at_91[0x7]; 1183 u8 prio_tag_required[0x1]; 1184 u8 reserved_at_99[0x2]; 1185 u8 log_max_qp[0x5]; 1186 1187 u8 reserved_at_a0[0xb]; 1188 u8 log_max_srq[0x5]; 1189 u8 reserved_at_b0[0x10]; 1190 1191 u8 max_sgl_for_optimized_performance[0x8]; 1192 u8 log_max_cq_sz[0x8]; 1193 u8 reserved_at_d0[0xb]; 1194 u8 log_max_cq[0x5]; 1195 1196 u8 log_max_eq_sz[0x8]; 1197 u8 relaxed_ordering_write[0x1]; 1198 u8 relaxed_ordering_read[0x1]; 1199 u8 log_max_mkey[0x6]; 1200 u8 reserved_at_f0[0x8]; 1201 u8 dump_fill_mkey[0x1]; 1202 u8 reserved_at_f9[0x2]; 1203 u8 fast_teardown[0x1]; 1204 u8 log_max_eq[0x4]; 1205 1206 u8 max_indirection[0x8]; 1207 u8 fixed_buffer_size[0x1]; 1208 u8 log_max_mrw_sz[0x7]; 1209 u8 force_teardown[0x1]; 1210 u8 reserved_at_111[0x1]; 1211 u8 log_max_bsf_list_size[0x6]; 1212 u8 umr_extended_translation_offset[0x1]; 1213 u8 null_mkey[0x1]; 1214 u8 log_max_klm_list_size[0x6]; 1215 1216 u8 reserved_at_120[0xa]; 1217 u8 log_max_ra_req_dc[0x6]; 1218 u8 reserved_at_130[0xa]; 1219 u8 log_max_ra_res_dc[0x6]; 1220 1221 u8 reserved_at_140[0x9]; 1222 u8 roce_accl[0x1]; 1223 u8 log_max_ra_req_qp[0x6]; 1224 u8 reserved_at_150[0xa]; 1225 u8 log_max_ra_res_qp[0x6]; 1226 1227 u8 end_pad[0x1]; 1228 u8 cc_query_allowed[0x1]; 1229 u8 cc_modify_allowed[0x1]; 1230 u8 start_pad[0x1]; 1231 u8 cache_line_128byte[0x1]; 1232 u8 reserved_at_165[0x4]; 1233 u8 rts2rts_qp_counters_set_id[0x1]; 1234 u8 reserved_at_16a[0x2]; 1235 u8 vnic_env_int_rq_oob[0x1]; 1236 u8 sbcam_reg[0x1]; 1237 u8 reserved_at_16e[0x1]; 1238 u8 qcam_reg[0x1]; 1239 u8 gid_table_size[0x10]; 1240 1241 u8 out_of_seq_cnt[0x1]; 1242 u8 vport_counters[0x1]; 1243 u8 retransmission_q_counters[0x1]; 1244 u8 debug[0x1]; 1245 u8 modify_rq_counter_set_id[0x1]; 1246 u8 rq_delay_drop[0x1]; 1247 u8 max_qp_cnt[0xa]; 1248 u8 pkey_table_size[0x10]; 1249 1250 u8 vport_group_manager[0x1]; 1251 u8 vhca_group_manager[0x1]; 1252 u8 ib_virt[0x1]; 1253 u8 eth_virt[0x1]; 1254 u8 vnic_env_queue_counters[0x1]; 1255 u8 ets[0x1]; 1256 u8 nic_flow_table[0x1]; 1257 u8 eswitch_manager[0x1]; 1258 u8 device_memory[0x1]; 1259 u8 mcam_reg[0x1]; 1260 u8 pcam_reg[0x1]; 1261 u8 local_ca_ack_delay[0x5]; 1262 u8 port_module_event[0x1]; 1263 u8 enhanced_error_q_counters[0x1]; 1264 u8 ports_check[0x1]; 1265 u8 reserved_at_1b3[0x1]; 1266 u8 disable_link_up[0x1]; 1267 u8 beacon_led[0x1]; 1268 u8 port_type[0x2]; 1269 u8 num_ports[0x8]; 1270 1271 u8 reserved_at_1c0[0x1]; 1272 u8 pps[0x1]; 1273 u8 pps_modify[0x1]; 1274 u8 log_max_msg[0x5]; 1275 u8 reserved_at_1c8[0x4]; 1276 u8 max_tc[0x4]; 1277 u8 temp_warn_event[0x1]; 1278 u8 dcbx[0x1]; 1279 u8 general_notification_event[0x1]; 1280 u8 reserved_at_1d3[0x2]; 1281 u8 fpga[0x1]; 1282 u8 rol_s[0x1]; 1283 u8 rol_g[0x1]; 1284 u8 reserved_at_1d8[0x1]; 1285 u8 wol_s[0x1]; 1286 u8 wol_g[0x1]; 1287 u8 wol_a[0x1]; 1288 u8 wol_b[0x1]; 1289 u8 wol_m[0x1]; 1290 u8 wol_u[0x1]; 1291 u8 wol_p[0x1]; 1292 1293 u8 stat_rate_support[0x10]; 1294 u8 reserved_at_1f0[0xc]; 1295 u8 cqe_version[0x4]; 1296 1297 u8 compact_address_vector[0x1]; 1298 u8 striding_rq[0x1]; 1299 u8 reserved_at_202[0x1]; 1300 u8 ipoib_enhanced_offloads[0x1]; 1301 u8 ipoib_basic_offloads[0x1]; 1302 u8 reserved_at_205[0x1]; 1303 u8 repeated_block_disabled[0x1]; 1304 u8 umr_modify_entity_size_disabled[0x1]; 1305 u8 umr_modify_atomic_disabled[0x1]; 1306 u8 umr_indirect_mkey_disabled[0x1]; 1307 u8 umr_fence[0x2]; 1308 u8 dc_req_scat_data_cqe[0x1]; 1309 u8 reserved_at_20d[0x2]; 1310 u8 drain_sigerr[0x1]; 1311 u8 cmdif_checksum[0x2]; 1312 u8 sigerr_cqe[0x1]; 1313 u8 reserved_at_213[0x1]; 1314 u8 wq_signature[0x1]; 1315 u8 sctr_data_cqe[0x1]; 1316 u8 reserved_at_216[0x1]; 1317 u8 sho[0x1]; 1318 u8 tph[0x1]; 1319 u8 rf[0x1]; 1320 u8 dct[0x1]; 1321 u8 qos[0x1]; 1322 u8 eth_net_offloads[0x1]; 1323 u8 roce[0x1]; 1324 u8 atomic[0x1]; 1325 u8 reserved_at_21f[0x1]; 1326 1327 u8 cq_oi[0x1]; 1328 u8 cq_resize[0x1]; 1329 u8 cq_moderation[0x1]; 1330 u8 reserved_at_223[0x3]; 1331 u8 cq_eq_remap[0x1]; 1332 u8 pg[0x1]; 1333 u8 block_lb_mc[0x1]; 1334 u8 reserved_at_229[0x1]; 1335 u8 scqe_break_moderation[0x1]; 1336 u8 cq_period_start_from_cqe[0x1]; 1337 u8 cd[0x1]; 1338 u8 reserved_at_22d[0x1]; 1339 u8 apm[0x1]; 1340 u8 vector_calc[0x1]; 1341 u8 umr_ptr_rlky[0x1]; 1342 u8 imaicl[0x1]; 1343 u8 qp_packet_based[0x1]; 1344 u8 reserved_at_233[0x3]; 1345 u8 qkv[0x1]; 1346 u8 pkv[0x1]; 1347 u8 set_deth_sqpn[0x1]; 1348 u8 reserved_at_239[0x3]; 1349 u8 xrc[0x1]; 1350 u8 ud[0x1]; 1351 u8 uc[0x1]; 1352 u8 rc[0x1]; 1353 1354 u8 uar_4k[0x1]; 1355 u8 reserved_at_241[0x9]; 1356 u8 uar_sz[0x6]; 1357 u8 reserved_at_250[0x8]; 1358 u8 log_pg_sz[0x8]; 1359 1360 u8 bf[0x1]; 1361 u8 driver_version[0x1]; 1362 u8 pad_tx_eth_packet[0x1]; 1363 u8 reserved_at_263[0x8]; 1364 u8 log_bf_reg_size[0x5]; 1365 1366 u8 reserved_at_270[0x8]; 1367 u8 lag_tx_port_affinity[0x1]; 1368 u8 reserved_at_279[0x2]; 1369 u8 lag_master[0x1]; 1370 u8 num_lag_ports[0x4]; 1371 1372 u8 reserved_at_280[0x10]; 1373 u8 max_wqe_sz_sq[0x10]; 1374 1375 u8 reserved_at_2a0[0x10]; 1376 u8 max_wqe_sz_rq[0x10]; 1377 1378 u8 max_flow_counter_31_16[0x10]; 1379 u8 max_wqe_sz_sq_dc[0x10]; 1380 1381 u8 reserved_at_2e0[0x7]; 1382 u8 max_qp_mcg[0x19]; 1383 1384 u8 reserved_at_300[0x10]; 1385 u8 flow_counter_bulk_alloc[0x8]; 1386 u8 log_max_mcg[0x8]; 1387 1388 u8 reserved_at_320[0x3]; 1389 u8 log_max_transport_domain[0x5]; 1390 u8 reserved_at_328[0x3]; 1391 u8 log_max_pd[0x5]; 1392 u8 reserved_at_330[0xb]; 1393 u8 log_max_xrcd[0x5]; 1394 1395 u8 nic_receive_steering_discard[0x1]; 1396 u8 receive_discard_vport_down[0x1]; 1397 u8 transmit_discard_vport_down[0x1]; 1398 u8 reserved_at_343[0x5]; 1399 u8 log_max_flow_counter_bulk[0x8]; 1400 u8 max_flow_counter_15_0[0x10]; 1401 1402 1403 u8 reserved_at_360[0x3]; 1404 u8 log_max_rq[0x5]; 1405 u8 reserved_at_368[0x3]; 1406 u8 log_max_sq[0x5]; 1407 u8 reserved_at_370[0x3]; 1408 u8 log_max_tir[0x5]; 1409 u8 reserved_at_378[0x3]; 1410 u8 log_max_tis[0x5]; 1411 1412 u8 basic_cyclic_rcv_wqe[0x1]; 1413 u8 reserved_at_381[0x2]; 1414 u8 log_max_rmp[0x5]; 1415 u8 reserved_at_388[0x3]; 1416 u8 log_max_rqt[0x5]; 1417 u8 reserved_at_390[0x3]; 1418 u8 log_max_rqt_size[0x5]; 1419 u8 reserved_at_398[0x3]; 1420 u8 log_max_tis_per_sq[0x5]; 1421 1422 u8 ext_stride_num_range[0x1]; 1423 u8 reserved_at_3a1[0x2]; 1424 u8 log_max_stride_sz_rq[0x5]; 1425 u8 reserved_at_3a8[0x3]; 1426 u8 log_min_stride_sz_rq[0x5]; 1427 u8 reserved_at_3b0[0x3]; 1428 u8 log_max_stride_sz_sq[0x5]; 1429 u8 reserved_at_3b8[0x3]; 1430 u8 log_min_stride_sz_sq[0x5]; 1431 1432 u8 hairpin[0x1]; 1433 u8 reserved_at_3c1[0x2]; 1434 u8 log_max_hairpin_queues[0x5]; 1435 u8 reserved_at_3c8[0x3]; 1436 u8 log_max_hairpin_wq_data_sz[0x5]; 1437 u8 reserved_at_3d0[0x3]; 1438 u8 log_max_hairpin_num_packets[0x5]; 1439 u8 reserved_at_3d8[0x3]; 1440 u8 log_max_wq_sz[0x5]; 1441 1442 u8 nic_vport_change_event[0x1]; 1443 u8 disable_local_lb_uc[0x1]; 1444 u8 disable_local_lb_mc[0x1]; 1445 u8 log_min_hairpin_wq_data_sz[0x5]; 1446 u8 reserved_at_3e8[0x3]; 1447 u8 log_max_vlan_list[0x5]; 1448 u8 reserved_at_3f0[0x3]; 1449 u8 log_max_current_mc_list[0x5]; 1450 u8 reserved_at_3f8[0x3]; 1451 u8 log_max_current_uc_list[0x5]; 1452 1453 u8 general_obj_types[0x40]; 1454 1455 u8 reserved_at_440[0x20]; 1456 1457 u8 reserved_at_460[0x3]; 1458 u8 log_max_uctx[0x5]; 1459 u8 reserved_at_468[0x3]; 1460 u8 log_max_umem[0x5]; 1461 u8 max_num_eqs[0x10]; 1462 1463 u8 reserved_at_480[0x1]; 1464 u8 tls_tx[0x1]; 1465 u8 reserved_at_482[0x1]; 1466 u8 log_max_l2_table[0x5]; 1467 u8 reserved_at_488[0x8]; 1468 u8 log_uar_page_sz[0x10]; 1469 1470 u8 reserved_at_4a0[0x20]; 1471 u8 device_frequency_mhz[0x20]; 1472 u8 device_frequency_khz[0x20]; 1473 1474 u8 reserved_at_500[0x20]; 1475 u8 num_of_uars_per_page[0x20]; 1476 1477 u8 flex_parser_protocols[0x20]; 1478 1479 u8 max_geneve_tlv_options[0x8]; 1480 u8 reserved_at_568[0x3]; 1481 u8 max_geneve_tlv_option_data_len[0x5]; 1482 u8 reserved_at_570[0x10]; 1483 1484 u8 reserved_at_580[0x33]; 1485 u8 log_max_dek[0x5]; 1486 u8 reserved_at_5b8[0x4]; 1487 u8 mini_cqe_resp_stride_index[0x1]; 1488 u8 cqe_128_always[0x1]; 1489 u8 cqe_compression_128[0x1]; 1490 u8 cqe_compression[0x1]; 1491 1492 u8 cqe_compression_timeout[0x10]; 1493 u8 cqe_compression_max_num[0x10]; 1494 1495 u8 reserved_at_5e0[0x10]; 1496 u8 tag_matching[0x1]; 1497 u8 rndv_offload_rc[0x1]; 1498 u8 rndv_offload_dc[0x1]; 1499 u8 log_tag_matching_list_sz[0x5]; 1500 u8 reserved_at_5f8[0x3]; 1501 u8 log_max_xrq[0x5]; 1502 1503 u8 affiliate_nic_vport_criteria[0x8]; 1504 u8 native_port_num[0x8]; 1505 u8 num_vhca_ports[0x8]; 1506 u8 reserved_at_618[0x6]; 1507 u8 sw_owner_id[0x1]; 1508 u8 reserved_at_61f[0x1]; 1509 1510 u8 max_num_of_monitor_counters[0x10]; 1511 u8 num_ppcnt_monitor_counters[0x10]; 1512 1513 u8 reserved_at_640[0x10]; 1514 u8 num_q_monitor_counters[0x10]; 1515 1516 u8 reserved_at_660[0x20]; 1517 1518 u8 sf[0x1]; 1519 u8 sf_set_partition[0x1]; 1520 u8 reserved_at_682[0x1]; 1521 u8 log_max_sf[0x5]; 1522 u8 reserved_at_688[0x8]; 1523 u8 log_min_sf_size[0x8]; 1524 u8 max_num_sf_partitions[0x8]; 1525 1526 u8 uctx_cap[0x20]; 1527 1528 u8 reserved_at_6c0[0x4]; 1529 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1530 u8 flex_parser_id_icmp_dw1[0x4]; 1531 u8 flex_parser_id_icmp_dw0[0x4]; 1532 u8 flex_parser_id_icmpv6_dw1[0x4]; 1533 u8 flex_parser_id_icmpv6_dw0[0x4]; 1534 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1535 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1536 1537 u8 reserved_at_6e0[0x10]; 1538 u8 sf_base_id[0x10]; 1539 1540 u8 reserved_at_700[0x80]; 1541 u8 vhca_tunnel_commands[0x40]; 1542 u8 reserved_at_7c0[0x40]; 1543 }; 1544 1545 enum mlx5_flow_destination_type { 1546 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1547 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1548 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1549 1550 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1551 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1552 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1553 }; 1554 1555 enum mlx5_flow_table_miss_action { 1556 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1557 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1558 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1559 }; 1560 1561 struct mlx5_ifc_dest_format_struct_bits { 1562 u8 destination_type[0x8]; 1563 u8 destination_id[0x18]; 1564 1565 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1566 u8 packet_reformat[0x1]; 1567 u8 reserved_at_22[0xe]; 1568 u8 destination_eswitch_owner_vhca_id[0x10]; 1569 }; 1570 1571 struct mlx5_ifc_flow_counter_list_bits { 1572 u8 flow_counter_id[0x20]; 1573 1574 u8 reserved_at_20[0x20]; 1575 }; 1576 1577 struct mlx5_ifc_extended_dest_format_bits { 1578 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1579 1580 u8 packet_reformat_id[0x20]; 1581 1582 u8 reserved_at_60[0x20]; 1583 }; 1584 1585 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1586 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1587 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1588 }; 1589 1590 struct mlx5_ifc_fte_match_param_bits { 1591 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1592 1593 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1594 1595 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1596 1597 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1598 1599 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1600 1601 u8 reserved_at_a00[0x600]; 1602 }; 1603 1604 enum { 1605 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1606 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1607 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1608 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1609 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1610 }; 1611 1612 struct mlx5_ifc_rx_hash_field_select_bits { 1613 u8 l3_prot_type[0x1]; 1614 u8 l4_prot_type[0x1]; 1615 u8 selected_fields[0x1e]; 1616 }; 1617 1618 enum { 1619 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1620 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1621 }; 1622 1623 enum { 1624 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1625 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1626 }; 1627 1628 struct mlx5_ifc_wq_bits { 1629 u8 wq_type[0x4]; 1630 u8 wq_signature[0x1]; 1631 u8 end_padding_mode[0x2]; 1632 u8 cd_slave[0x1]; 1633 u8 reserved_at_8[0x18]; 1634 1635 u8 hds_skip_first_sge[0x1]; 1636 u8 log2_hds_buf_size[0x3]; 1637 u8 reserved_at_24[0x7]; 1638 u8 page_offset[0x5]; 1639 u8 lwm[0x10]; 1640 1641 u8 reserved_at_40[0x8]; 1642 u8 pd[0x18]; 1643 1644 u8 reserved_at_60[0x8]; 1645 u8 uar_page[0x18]; 1646 1647 u8 dbr_addr[0x40]; 1648 1649 u8 hw_counter[0x20]; 1650 1651 u8 sw_counter[0x20]; 1652 1653 u8 reserved_at_100[0xc]; 1654 u8 log_wq_stride[0x4]; 1655 u8 reserved_at_110[0x3]; 1656 u8 log_wq_pg_sz[0x5]; 1657 u8 reserved_at_118[0x3]; 1658 u8 log_wq_sz[0x5]; 1659 1660 u8 dbr_umem_valid[0x1]; 1661 u8 wq_umem_valid[0x1]; 1662 u8 reserved_at_122[0x1]; 1663 u8 log_hairpin_num_packets[0x5]; 1664 u8 reserved_at_128[0x3]; 1665 u8 log_hairpin_data_sz[0x5]; 1666 1667 u8 reserved_at_130[0x4]; 1668 u8 log_wqe_num_of_strides[0x4]; 1669 u8 two_byte_shift_en[0x1]; 1670 u8 reserved_at_139[0x4]; 1671 u8 log_wqe_stride_size[0x3]; 1672 1673 u8 reserved_at_140[0x4c0]; 1674 1675 struct mlx5_ifc_cmd_pas_bits pas[0]; 1676 }; 1677 1678 struct mlx5_ifc_rq_num_bits { 1679 u8 reserved_at_0[0x8]; 1680 u8 rq_num[0x18]; 1681 }; 1682 1683 struct mlx5_ifc_mac_address_layout_bits { 1684 u8 reserved_at_0[0x10]; 1685 u8 mac_addr_47_32[0x10]; 1686 1687 u8 mac_addr_31_0[0x20]; 1688 }; 1689 1690 struct mlx5_ifc_vlan_layout_bits { 1691 u8 reserved_at_0[0x14]; 1692 u8 vlan[0x0c]; 1693 1694 u8 reserved_at_20[0x20]; 1695 }; 1696 1697 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1698 u8 reserved_at_0[0xa0]; 1699 1700 u8 min_time_between_cnps[0x20]; 1701 1702 u8 reserved_at_c0[0x12]; 1703 u8 cnp_dscp[0x6]; 1704 u8 reserved_at_d8[0x4]; 1705 u8 cnp_prio_mode[0x1]; 1706 u8 cnp_802p_prio[0x3]; 1707 1708 u8 reserved_at_e0[0x720]; 1709 }; 1710 1711 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1712 u8 reserved_at_0[0x60]; 1713 1714 u8 reserved_at_60[0x4]; 1715 u8 clamp_tgt_rate[0x1]; 1716 u8 reserved_at_65[0x3]; 1717 u8 clamp_tgt_rate_after_time_inc[0x1]; 1718 u8 reserved_at_69[0x17]; 1719 1720 u8 reserved_at_80[0x20]; 1721 1722 u8 rpg_time_reset[0x20]; 1723 1724 u8 rpg_byte_reset[0x20]; 1725 1726 u8 rpg_threshold[0x20]; 1727 1728 u8 rpg_max_rate[0x20]; 1729 1730 u8 rpg_ai_rate[0x20]; 1731 1732 u8 rpg_hai_rate[0x20]; 1733 1734 u8 rpg_gd[0x20]; 1735 1736 u8 rpg_min_dec_fac[0x20]; 1737 1738 u8 rpg_min_rate[0x20]; 1739 1740 u8 reserved_at_1c0[0xe0]; 1741 1742 u8 rate_to_set_on_first_cnp[0x20]; 1743 1744 u8 dce_tcp_g[0x20]; 1745 1746 u8 dce_tcp_rtt[0x20]; 1747 1748 u8 rate_reduce_monitor_period[0x20]; 1749 1750 u8 reserved_at_320[0x20]; 1751 1752 u8 initial_alpha_value[0x20]; 1753 1754 u8 reserved_at_360[0x4a0]; 1755 }; 1756 1757 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1758 u8 reserved_at_0[0x80]; 1759 1760 u8 rppp_max_rps[0x20]; 1761 1762 u8 rpg_time_reset[0x20]; 1763 1764 u8 rpg_byte_reset[0x20]; 1765 1766 u8 rpg_threshold[0x20]; 1767 1768 u8 rpg_max_rate[0x20]; 1769 1770 u8 rpg_ai_rate[0x20]; 1771 1772 u8 rpg_hai_rate[0x20]; 1773 1774 u8 rpg_gd[0x20]; 1775 1776 u8 rpg_min_dec_fac[0x20]; 1777 1778 u8 rpg_min_rate[0x20]; 1779 1780 u8 reserved_at_1c0[0x640]; 1781 }; 1782 1783 enum { 1784 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1785 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1786 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1787 }; 1788 1789 struct mlx5_ifc_resize_field_select_bits { 1790 u8 resize_field_select[0x20]; 1791 }; 1792 1793 struct mlx5_ifc_resource_dump_bits { 1794 u8 more_dump[0x1]; 1795 u8 inline_dump[0x1]; 1796 u8 reserved_at_2[0xa]; 1797 u8 seq_num[0x4]; 1798 u8 segment_type[0x10]; 1799 1800 u8 reserved_at_20[0x10]; 1801 u8 vhca_id[0x10]; 1802 1803 u8 index1[0x20]; 1804 1805 u8 index2[0x20]; 1806 1807 u8 num_of_obj1[0x10]; 1808 u8 num_of_obj2[0x10]; 1809 1810 u8 reserved_at_a0[0x20]; 1811 1812 u8 device_opaque[0x40]; 1813 1814 u8 mkey[0x20]; 1815 1816 u8 size[0x20]; 1817 1818 u8 address[0x40]; 1819 1820 u8 inline_data[52][0x20]; 1821 }; 1822 1823 struct mlx5_ifc_resource_dump_menu_record_bits { 1824 u8 reserved_at_0[0x4]; 1825 u8 num_of_obj2_supports_active[0x1]; 1826 u8 num_of_obj2_supports_all[0x1]; 1827 u8 must_have_num_of_obj2[0x1]; 1828 u8 support_num_of_obj2[0x1]; 1829 u8 num_of_obj1_supports_active[0x1]; 1830 u8 num_of_obj1_supports_all[0x1]; 1831 u8 must_have_num_of_obj1[0x1]; 1832 u8 support_num_of_obj1[0x1]; 1833 u8 must_have_index2[0x1]; 1834 u8 support_index2[0x1]; 1835 u8 must_have_index1[0x1]; 1836 u8 support_index1[0x1]; 1837 u8 segment_type[0x10]; 1838 1839 u8 segment_name[4][0x20]; 1840 1841 u8 index1_name[4][0x20]; 1842 1843 u8 index2_name[4][0x20]; 1844 }; 1845 1846 struct mlx5_ifc_resource_dump_segment_header_bits { 1847 u8 length_dw[0x10]; 1848 u8 segment_type[0x10]; 1849 }; 1850 1851 struct mlx5_ifc_resource_dump_command_segment_bits { 1852 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1853 1854 u8 segment_called[0x10]; 1855 u8 vhca_id[0x10]; 1856 1857 u8 index1[0x20]; 1858 1859 u8 index2[0x20]; 1860 1861 u8 num_of_obj1[0x10]; 1862 u8 num_of_obj2[0x10]; 1863 }; 1864 1865 struct mlx5_ifc_resource_dump_error_segment_bits { 1866 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1867 1868 u8 reserved_at_20[0x10]; 1869 u8 syndrome_id[0x10]; 1870 1871 u8 reserved_at_40[0x40]; 1872 1873 u8 error[8][0x20]; 1874 }; 1875 1876 struct mlx5_ifc_resource_dump_info_segment_bits { 1877 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1878 1879 u8 reserved_at_20[0x18]; 1880 u8 dump_version[0x8]; 1881 1882 u8 hw_version[0x20]; 1883 1884 u8 fw_version[0x20]; 1885 }; 1886 1887 struct mlx5_ifc_resource_dump_menu_segment_bits { 1888 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1889 1890 u8 reserved_at_20[0x10]; 1891 u8 num_of_records[0x10]; 1892 1893 struct mlx5_ifc_resource_dump_menu_record_bits record[0]; 1894 }; 1895 1896 struct mlx5_ifc_resource_dump_resource_segment_bits { 1897 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1898 1899 u8 reserved_at_20[0x20]; 1900 1901 u8 index1[0x20]; 1902 1903 u8 index2[0x20]; 1904 1905 u8 payload[0][0x20]; 1906 }; 1907 1908 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1909 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1910 }; 1911 1912 struct mlx5_ifc_menu_resource_dump_response_bits { 1913 struct mlx5_ifc_resource_dump_info_segment_bits info; 1914 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1915 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1916 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1917 }; 1918 1919 enum { 1920 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1921 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1922 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1923 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1924 }; 1925 1926 struct mlx5_ifc_modify_field_select_bits { 1927 u8 modify_field_select[0x20]; 1928 }; 1929 1930 struct mlx5_ifc_field_select_r_roce_np_bits { 1931 u8 field_select_r_roce_np[0x20]; 1932 }; 1933 1934 struct mlx5_ifc_field_select_r_roce_rp_bits { 1935 u8 field_select_r_roce_rp[0x20]; 1936 }; 1937 1938 enum { 1939 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1940 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1941 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1942 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1943 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1944 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1945 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1946 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1947 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1948 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1949 }; 1950 1951 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1952 u8 field_select_8021qaurp[0x20]; 1953 }; 1954 1955 struct mlx5_ifc_phys_layer_cntrs_bits { 1956 u8 time_since_last_clear_high[0x20]; 1957 1958 u8 time_since_last_clear_low[0x20]; 1959 1960 u8 symbol_errors_high[0x20]; 1961 1962 u8 symbol_errors_low[0x20]; 1963 1964 u8 sync_headers_errors_high[0x20]; 1965 1966 u8 sync_headers_errors_low[0x20]; 1967 1968 u8 edpl_bip_errors_lane0_high[0x20]; 1969 1970 u8 edpl_bip_errors_lane0_low[0x20]; 1971 1972 u8 edpl_bip_errors_lane1_high[0x20]; 1973 1974 u8 edpl_bip_errors_lane1_low[0x20]; 1975 1976 u8 edpl_bip_errors_lane2_high[0x20]; 1977 1978 u8 edpl_bip_errors_lane2_low[0x20]; 1979 1980 u8 edpl_bip_errors_lane3_high[0x20]; 1981 1982 u8 edpl_bip_errors_lane3_low[0x20]; 1983 1984 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1985 1986 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1987 1988 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1989 1990 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1991 1992 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1993 1994 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1995 1996 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1997 1998 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1999 2000 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2001 2002 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2003 2004 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2005 2006 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2007 2008 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2009 2010 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2011 2012 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2013 2014 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2015 2016 u8 rs_fec_corrected_blocks_high[0x20]; 2017 2018 u8 rs_fec_corrected_blocks_low[0x20]; 2019 2020 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2021 2022 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2023 2024 u8 rs_fec_no_errors_blocks_high[0x20]; 2025 2026 u8 rs_fec_no_errors_blocks_low[0x20]; 2027 2028 u8 rs_fec_single_error_blocks_high[0x20]; 2029 2030 u8 rs_fec_single_error_blocks_low[0x20]; 2031 2032 u8 rs_fec_corrected_symbols_total_high[0x20]; 2033 2034 u8 rs_fec_corrected_symbols_total_low[0x20]; 2035 2036 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2037 2038 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2039 2040 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2041 2042 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2043 2044 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2045 2046 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2047 2048 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2049 2050 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2051 2052 u8 link_down_events[0x20]; 2053 2054 u8 successful_recovery_events[0x20]; 2055 2056 u8 reserved_at_640[0x180]; 2057 }; 2058 2059 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2060 u8 time_since_last_clear_high[0x20]; 2061 2062 u8 time_since_last_clear_low[0x20]; 2063 2064 u8 phy_received_bits_high[0x20]; 2065 2066 u8 phy_received_bits_low[0x20]; 2067 2068 u8 phy_symbol_errors_high[0x20]; 2069 2070 u8 phy_symbol_errors_low[0x20]; 2071 2072 u8 phy_corrected_bits_high[0x20]; 2073 2074 u8 phy_corrected_bits_low[0x20]; 2075 2076 u8 phy_corrected_bits_lane0_high[0x20]; 2077 2078 u8 phy_corrected_bits_lane0_low[0x20]; 2079 2080 u8 phy_corrected_bits_lane1_high[0x20]; 2081 2082 u8 phy_corrected_bits_lane1_low[0x20]; 2083 2084 u8 phy_corrected_bits_lane2_high[0x20]; 2085 2086 u8 phy_corrected_bits_lane2_low[0x20]; 2087 2088 u8 phy_corrected_bits_lane3_high[0x20]; 2089 2090 u8 phy_corrected_bits_lane3_low[0x20]; 2091 2092 u8 reserved_at_200[0x5c0]; 2093 }; 2094 2095 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2096 u8 symbol_error_counter[0x10]; 2097 2098 u8 link_error_recovery_counter[0x8]; 2099 2100 u8 link_downed_counter[0x8]; 2101 2102 u8 port_rcv_errors[0x10]; 2103 2104 u8 port_rcv_remote_physical_errors[0x10]; 2105 2106 u8 port_rcv_switch_relay_errors[0x10]; 2107 2108 u8 port_xmit_discards[0x10]; 2109 2110 u8 port_xmit_constraint_errors[0x8]; 2111 2112 u8 port_rcv_constraint_errors[0x8]; 2113 2114 u8 reserved_at_70[0x8]; 2115 2116 u8 link_overrun_errors[0x8]; 2117 2118 u8 reserved_at_80[0x10]; 2119 2120 u8 vl_15_dropped[0x10]; 2121 2122 u8 reserved_at_a0[0x80]; 2123 2124 u8 port_xmit_wait[0x20]; 2125 }; 2126 2127 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2128 u8 transmit_queue_high[0x20]; 2129 2130 u8 transmit_queue_low[0x20]; 2131 2132 u8 no_buffer_discard_uc_high[0x20]; 2133 2134 u8 no_buffer_discard_uc_low[0x20]; 2135 2136 u8 reserved_at_80[0x740]; 2137 }; 2138 2139 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2140 u8 wred_discard_high[0x20]; 2141 2142 u8 wred_discard_low[0x20]; 2143 2144 u8 ecn_marked_tc_high[0x20]; 2145 2146 u8 ecn_marked_tc_low[0x20]; 2147 2148 u8 reserved_at_80[0x740]; 2149 }; 2150 2151 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2152 u8 rx_octets_high[0x20]; 2153 2154 u8 rx_octets_low[0x20]; 2155 2156 u8 reserved_at_40[0xc0]; 2157 2158 u8 rx_frames_high[0x20]; 2159 2160 u8 rx_frames_low[0x20]; 2161 2162 u8 tx_octets_high[0x20]; 2163 2164 u8 tx_octets_low[0x20]; 2165 2166 u8 reserved_at_180[0xc0]; 2167 2168 u8 tx_frames_high[0x20]; 2169 2170 u8 tx_frames_low[0x20]; 2171 2172 u8 rx_pause_high[0x20]; 2173 2174 u8 rx_pause_low[0x20]; 2175 2176 u8 rx_pause_duration_high[0x20]; 2177 2178 u8 rx_pause_duration_low[0x20]; 2179 2180 u8 tx_pause_high[0x20]; 2181 2182 u8 tx_pause_low[0x20]; 2183 2184 u8 tx_pause_duration_high[0x20]; 2185 2186 u8 tx_pause_duration_low[0x20]; 2187 2188 u8 rx_pause_transition_high[0x20]; 2189 2190 u8 rx_pause_transition_low[0x20]; 2191 2192 u8 rx_discards_high[0x20]; 2193 2194 u8 rx_discards_low[0x20]; 2195 2196 u8 device_stall_minor_watermark_cnt_high[0x20]; 2197 2198 u8 device_stall_minor_watermark_cnt_low[0x20]; 2199 2200 u8 device_stall_critical_watermark_cnt_high[0x20]; 2201 2202 u8 device_stall_critical_watermark_cnt_low[0x20]; 2203 2204 u8 reserved_at_480[0x340]; 2205 }; 2206 2207 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2208 u8 port_transmit_wait_high[0x20]; 2209 2210 u8 port_transmit_wait_low[0x20]; 2211 2212 u8 reserved_at_40[0x100]; 2213 2214 u8 rx_buffer_almost_full_high[0x20]; 2215 2216 u8 rx_buffer_almost_full_low[0x20]; 2217 2218 u8 rx_buffer_full_high[0x20]; 2219 2220 u8 rx_buffer_full_low[0x20]; 2221 2222 u8 rx_icrc_encapsulated_high[0x20]; 2223 2224 u8 rx_icrc_encapsulated_low[0x20]; 2225 2226 u8 reserved_at_200[0x5c0]; 2227 }; 2228 2229 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2230 u8 dot3stats_alignment_errors_high[0x20]; 2231 2232 u8 dot3stats_alignment_errors_low[0x20]; 2233 2234 u8 dot3stats_fcs_errors_high[0x20]; 2235 2236 u8 dot3stats_fcs_errors_low[0x20]; 2237 2238 u8 dot3stats_single_collision_frames_high[0x20]; 2239 2240 u8 dot3stats_single_collision_frames_low[0x20]; 2241 2242 u8 dot3stats_multiple_collision_frames_high[0x20]; 2243 2244 u8 dot3stats_multiple_collision_frames_low[0x20]; 2245 2246 u8 dot3stats_sqe_test_errors_high[0x20]; 2247 2248 u8 dot3stats_sqe_test_errors_low[0x20]; 2249 2250 u8 dot3stats_deferred_transmissions_high[0x20]; 2251 2252 u8 dot3stats_deferred_transmissions_low[0x20]; 2253 2254 u8 dot3stats_late_collisions_high[0x20]; 2255 2256 u8 dot3stats_late_collisions_low[0x20]; 2257 2258 u8 dot3stats_excessive_collisions_high[0x20]; 2259 2260 u8 dot3stats_excessive_collisions_low[0x20]; 2261 2262 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2263 2264 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2265 2266 u8 dot3stats_carrier_sense_errors_high[0x20]; 2267 2268 u8 dot3stats_carrier_sense_errors_low[0x20]; 2269 2270 u8 dot3stats_frame_too_longs_high[0x20]; 2271 2272 u8 dot3stats_frame_too_longs_low[0x20]; 2273 2274 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2275 2276 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2277 2278 u8 dot3stats_symbol_errors_high[0x20]; 2279 2280 u8 dot3stats_symbol_errors_low[0x20]; 2281 2282 u8 dot3control_in_unknown_opcodes_high[0x20]; 2283 2284 u8 dot3control_in_unknown_opcodes_low[0x20]; 2285 2286 u8 dot3in_pause_frames_high[0x20]; 2287 2288 u8 dot3in_pause_frames_low[0x20]; 2289 2290 u8 dot3out_pause_frames_high[0x20]; 2291 2292 u8 dot3out_pause_frames_low[0x20]; 2293 2294 u8 reserved_at_400[0x3c0]; 2295 }; 2296 2297 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2298 u8 ether_stats_drop_events_high[0x20]; 2299 2300 u8 ether_stats_drop_events_low[0x20]; 2301 2302 u8 ether_stats_octets_high[0x20]; 2303 2304 u8 ether_stats_octets_low[0x20]; 2305 2306 u8 ether_stats_pkts_high[0x20]; 2307 2308 u8 ether_stats_pkts_low[0x20]; 2309 2310 u8 ether_stats_broadcast_pkts_high[0x20]; 2311 2312 u8 ether_stats_broadcast_pkts_low[0x20]; 2313 2314 u8 ether_stats_multicast_pkts_high[0x20]; 2315 2316 u8 ether_stats_multicast_pkts_low[0x20]; 2317 2318 u8 ether_stats_crc_align_errors_high[0x20]; 2319 2320 u8 ether_stats_crc_align_errors_low[0x20]; 2321 2322 u8 ether_stats_undersize_pkts_high[0x20]; 2323 2324 u8 ether_stats_undersize_pkts_low[0x20]; 2325 2326 u8 ether_stats_oversize_pkts_high[0x20]; 2327 2328 u8 ether_stats_oversize_pkts_low[0x20]; 2329 2330 u8 ether_stats_fragments_high[0x20]; 2331 2332 u8 ether_stats_fragments_low[0x20]; 2333 2334 u8 ether_stats_jabbers_high[0x20]; 2335 2336 u8 ether_stats_jabbers_low[0x20]; 2337 2338 u8 ether_stats_collisions_high[0x20]; 2339 2340 u8 ether_stats_collisions_low[0x20]; 2341 2342 u8 ether_stats_pkts64octets_high[0x20]; 2343 2344 u8 ether_stats_pkts64octets_low[0x20]; 2345 2346 u8 ether_stats_pkts65to127octets_high[0x20]; 2347 2348 u8 ether_stats_pkts65to127octets_low[0x20]; 2349 2350 u8 ether_stats_pkts128to255octets_high[0x20]; 2351 2352 u8 ether_stats_pkts128to255octets_low[0x20]; 2353 2354 u8 ether_stats_pkts256to511octets_high[0x20]; 2355 2356 u8 ether_stats_pkts256to511octets_low[0x20]; 2357 2358 u8 ether_stats_pkts512to1023octets_high[0x20]; 2359 2360 u8 ether_stats_pkts512to1023octets_low[0x20]; 2361 2362 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2363 2364 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2365 2366 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2367 2368 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2369 2370 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2371 2372 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2373 2374 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2375 2376 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2377 2378 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2379 2380 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2381 2382 u8 reserved_at_540[0x280]; 2383 }; 2384 2385 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2386 u8 if_in_octets_high[0x20]; 2387 2388 u8 if_in_octets_low[0x20]; 2389 2390 u8 if_in_ucast_pkts_high[0x20]; 2391 2392 u8 if_in_ucast_pkts_low[0x20]; 2393 2394 u8 if_in_discards_high[0x20]; 2395 2396 u8 if_in_discards_low[0x20]; 2397 2398 u8 if_in_errors_high[0x20]; 2399 2400 u8 if_in_errors_low[0x20]; 2401 2402 u8 if_in_unknown_protos_high[0x20]; 2403 2404 u8 if_in_unknown_protos_low[0x20]; 2405 2406 u8 if_out_octets_high[0x20]; 2407 2408 u8 if_out_octets_low[0x20]; 2409 2410 u8 if_out_ucast_pkts_high[0x20]; 2411 2412 u8 if_out_ucast_pkts_low[0x20]; 2413 2414 u8 if_out_discards_high[0x20]; 2415 2416 u8 if_out_discards_low[0x20]; 2417 2418 u8 if_out_errors_high[0x20]; 2419 2420 u8 if_out_errors_low[0x20]; 2421 2422 u8 if_in_multicast_pkts_high[0x20]; 2423 2424 u8 if_in_multicast_pkts_low[0x20]; 2425 2426 u8 if_in_broadcast_pkts_high[0x20]; 2427 2428 u8 if_in_broadcast_pkts_low[0x20]; 2429 2430 u8 if_out_multicast_pkts_high[0x20]; 2431 2432 u8 if_out_multicast_pkts_low[0x20]; 2433 2434 u8 if_out_broadcast_pkts_high[0x20]; 2435 2436 u8 if_out_broadcast_pkts_low[0x20]; 2437 2438 u8 reserved_at_340[0x480]; 2439 }; 2440 2441 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2442 u8 a_frames_transmitted_ok_high[0x20]; 2443 2444 u8 a_frames_transmitted_ok_low[0x20]; 2445 2446 u8 a_frames_received_ok_high[0x20]; 2447 2448 u8 a_frames_received_ok_low[0x20]; 2449 2450 u8 a_frame_check_sequence_errors_high[0x20]; 2451 2452 u8 a_frame_check_sequence_errors_low[0x20]; 2453 2454 u8 a_alignment_errors_high[0x20]; 2455 2456 u8 a_alignment_errors_low[0x20]; 2457 2458 u8 a_octets_transmitted_ok_high[0x20]; 2459 2460 u8 a_octets_transmitted_ok_low[0x20]; 2461 2462 u8 a_octets_received_ok_high[0x20]; 2463 2464 u8 a_octets_received_ok_low[0x20]; 2465 2466 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2467 2468 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2469 2470 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2471 2472 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2473 2474 u8 a_multicast_frames_received_ok_high[0x20]; 2475 2476 u8 a_multicast_frames_received_ok_low[0x20]; 2477 2478 u8 a_broadcast_frames_received_ok_high[0x20]; 2479 2480 u8 a_broadcast_frames_received_ok_low[0x20]; 2481 2482 u8 a_in_range_length_errors_high[0x20]; 2483 2484 u8 a_in_range_length_errors_low[0x20]; 2485 2486 u8 a_out_of_range_length_field_high[0x20]; 2487 2488 u8 a_out_of_range_length_field_low[0x20]; 2489 2490 u8 a_frame_too_long_errors_high[0x20]; 2491 2492 u8 a_frame_too_long_errors_low[0x20]; 2493 2494 u8 a_symbol_error_during_carrier_high[0x20]; 2495 2496 u8 a_symbol_error_during_carrier_low[0x20]; 2497 2498 u8 a_mac_control_frames_transmitted_high[0x20]; 2499 2500 u8 a_mac_control_frames_transmitted_low[0x20]; 2501 2502 u8 a_mac_control_frames_received_high[0x20]; 2503 2504 u8 a_mac_control_frames_received_low[0x20]; 2505 2506 u8 a_unsupported_opcodes_received_high[0x20]; 2507 2508 u8 a_unsupported_opcodes_received_low[0x20]; 2509 2510 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2511 2512 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2513 2514 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2515 2516 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2517 2518 u8 reserved_at_4c0[0x300]; 2519 }; 2520 2521 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2522 u8 life_time_counter_high[0x20]; 2523 2524 u8 life_time_counter_low[0x20]; 2525 2526 u8 rx_errors[0x20]; 2527 2528 u8 tx_errors[0x20]; 2529 2530 u8 l0_to_recovery_eieos[0x20]; 2531 2532 u8 l0_to_recovery_ts[0x20]; 2533 2534 u8 l0_to_recovery_framing[0x20]; 2535 2536 u8 l0_to_recovery_retrain[0x20]; 2537 2538 u8 crc_error_dllp[0x20]; 2539 2540 u8 crc_error_tlp[0x20]; 2541 2542 u8 tx_overflow_buffer_pkt_high[0x20]; 2543 2544 u8 tx_overflow_buffer_pkt_low[0x20]; 2545 2546 u8 outbound_stalled_reads[0x20]; 2547 2548 u8 outbound_stalled_writes[0x20]; 2549 2550 u8 outbound_stalled_reads_events[0x20]; 2551 2552 u8 outbound_stalled_writes_events[0x20]; 2553 2554 u8 reserved_at_200[0x5c0]; 2555 }; 2556 2557 struct mlx5_ifc_cmd_inter_comp_event_bits { 2558 u8 command_completion_vector[0x20]; 2559 2560 u8 reserved_at_20[0xc0]; 2561 }; 2562 2563 struct mlx5_ifc_stall_vl_event_bits { 2564 u8 reserved_at_0[0x18]; 2565 u8 port_num[0x1]; 2566 u8 reserved_at_19[0x3]; 2567 u8 vl[0x4]; 2568 2569 u8 reserved_at_20[0xa0]; 2570 }; 2571 2572 struct mlx5_ifc_db_bf_congestion_event_bits { 2573 u8 event_subtype[0x8]; 2574 u8 reserved_at_8[0x8]; 2575 u8 congestion_level[0x8]; 2576 u8 reserved_at_18[0x8]; 2577 2578 u8 reserved_at_20[0xa0]; 2579 }; 2580 2581 struct mlx5_ifc_gpio_event_bits { 2582 u8 reserved_at_0[0x60]; 2583 2584 u8 gpio_event_hi[0x20]; 2585 2586 u8 gpio_event_lo[0x20]; 2587 2588 u8 reserved_at_a0[0x40]; 2589 }; 2590 2591 struct mlx5_ifc_port_state_change_event_bits { 2592 u8 reserved_at_0[0x40]; 2593 2594 u8 port_num[0x4]; 2595 u8 reserved_at_44[0x1c]; 2596 2597 u8 reserved_at_60[0x80]; 2598 }; 2599 2600 struct mlx5_ifc_dropped_packet_logged_bits { 2601 u8 reserved_at_0[0xe0]; 2602 }; 2603 2604 enum { 2605 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2606 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2607 }; 2608 2609 struct mlx5_ifc_cq_error_bits { 2610 u8 reserved_at_0[0x8]; 2611 u8 cqn[0x18]; 2612 2613 u8 reserved_at_20[0x20]; 2614 2615 u8 reserved_at_40[0x18]; 2616 u8 syndrome[0x8]; 2617 2618 u8 reserved_at_60[0x80]; 2619 }; 2620 2621 struct mlx5_ifc_rdma_page_fault_event_bits { 2622 u8 bytes_committed[0x20]; 2623 2624 u8 r_key[0x20]; 2625 2626 u8 reserved_at_40[0x10]; 2627 u8 packet_len[0x10]; 2628 2629 u8 rdma_op_len[0x20]; 2630 2631 u8 rdma_va[0x40]; 2632 2633 u8 reserved_at_c0[0x5]; 2634 u8 rdma[0x1]; 2635 u8 write[0x1]; 2636 u8 requestor[0x1]; 2637 u8 qp_number[0x18]; 2638 }; 2639 2640 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2641 u8 bytes_committed[0x20]; 2642 2643 u8 reserved_at_20[0x10]; 2644 u8 wqe_index[0x10]; 2645 2646 u8 reserved_at_40[0x10]; 2647 u8 len[0x10]; 2648 2649 u8 reserved_at_60[0x60]; 2650 2651 u8 reserved_at_c0[0x5]; 2652 u8 rdma[0x1]; 2653 u8 write_read[0x1]; 2654 u8 requestor[0x1]; 2655 u8 qpn[0x18]; 2656 }; 2657 2658 struct mlx5_ifc_qp_events_bits { 2659 u8 reserved_at_0[0xa0]; 2660 2661 u8 type[0x8]; 2662 u8 reserved_at_a8[0x18]; 2663 2664 u8 reserved_at_c0[0x8]; 2665 u8 qpn_rqn_sqn[0x18]; 2666 }; 2667 2668 struct mlx5_ifc_dct_events_bits { 2669 u8 reserved_at_0[0xc0]; 2670 2671 u8 reserved_at_c0[0x8]; 2672 u8 dct_number[0x18]; 2673 }; 2674 2675 struct mlx5_ifc_comp_event_bits { 2676 u8 reserved_at_0[0xc0]; 2677 2678 u8 reserved_at_c0[0x8]; 2679 u8 cq_number[0x18]; 2680 }; 2681 2682 enum { 2683 MLX5_QPC_STATE_RST = 0x0, 2684 MLX5_QPC_STATE_INIT = 0x1, 2685 MLX5_QPC_STATE_RTR = 0x2, 2686 MLX5_QPC_STATE_RTS = 0x3, 2687 MLX5_QPC_STATE_SQER = 0x4, 2688 MLX5_QPC_STATE_ERR = 0x6, 2689 MLX5_QPC_STATE_SQD = 0x7, 2690 MLX5_QPC_STATE_SUSPENDED = 0x9, 2691 }; 2692 2693 enum { 2694 MLX5_QPC_ST_RC = 0x0, 2695 MLX5_QPC_ST_UC = 0x1, 2696 MLX5_QPC_ST_UD = 0x2, 2697 MLX5_QPC_ST_XRC = 0x3, 2698 MLX5_QPC_ST_DCI = 0x5, 2699 MLX5_QPC_ST_QP0 = 0x7, 2700 MLX5_QPC_ST_QP1 = 0x8, 2701 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2702 MLX5_QPC_ST_REG_UMR = 0xc, 2703 }; 2704 2705 enum { 2706 MLX5_QPC_PM_STATE_ARMED = 0x0, 2707 MLX5_QPC_PM_STATE_REARM = 0x1, 2708 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2709 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2710 }; 2711 2712 enum { 2713 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2714 }; 2715 2716 enum { 2717 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2718 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2719 }; 2720 2721 enum { 2722 MLX5_QPC_MTU_256_BYTES = 0x1, 2723 MLX5_QPC_MTU_512_BYTES = 0x2, 2724 MLX5_QPC_MTU_1K_BYTES = 0x3, 2725 MLX5_QPC_MTU_2K_BYTES = 0x4, 2726 MLX5_QPC_MTU_4K_BYTES = 0x5, 2727 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2728 }; 2729 2730 enum { 2731 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2732 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2733 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2734 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2735 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2736 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2737 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2738 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2739 }; 2740 2741 enum { 2742 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2743 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2744 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2745 }; 2746 2747 enum { 2748 MLX5_QPC_CS_RES_DISABLE = 0x0, 2749 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2750 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2751 }; 2752 2753 struct mlx5_ifc_qpc_bits { 2754 u8 state[0x4]; 2755 u8 lag_tx_port_affinity[0x4]; 2756 u8 st[0x8]; 2757 u8 reserved_at_10[0x3]; 2758 u8 pm_state[0x2]; 2759 u8 reserved_at_15[0x1]; 2760 u8 req_e2e_credit_mode[0x2]; 2761 u8 offload_type[0x4]; 2762 u8 end_padding_mode[0x2]; 2763 u8 reserved_at_1e[0x2]; 2764 2765 u8 wq_signature[0x1]; 2766 u8 block_lb_mc[0x1]; 2767 u8 atomic_like_write_en[0x1]; 2768 u8 latency_sensitive[0x1]; 2769 u8 reserved_at_24[0x1]; 2770 u8 drain_sigerr[0x1]; 2771 u8 reserved_at_26[0x2]; 2772 u8 pd[0x18]; 2773 2774 u8 mtu[0x3]; 2775 u8 log_msg_max[0x5]; 2776 u8 reserved_at_48[0x1]; 2777 u8 log_rq_size[0x4]; 2778 u8 log_rq_stride[0x3]; 2779 u8 no_sq[0x1]; 2780 u8 log_sq_size[0x4]; 2781 u8 reserved_at_55[0x6]; 2782 u8 rlky[0x1]; 2783 u8 ulp_stateless_offload_mode[0x4]; 2784 2785 u8 counter_set_id[0x8]; 2786 u8 uar_page[0x18]; 2787 2788 u8 reserved_at_80[0x8]; 2789 u8 user_index[0x18]; 2790 2791 u8 reserved_at_a0[0x3]; 2792 u8 log_page_size[0x5]; 2793 u8 remote_qpn[0x18]; 2794 2795 struct mlx5_ifc_ads_bits primary_address_path; 2796 2797 struct mlx5_ifc_ads_bits secondary_address_path; 2798 2799 u8 log_ack_req_freq[0x4]; 2800 u8 reserved_at_384[0x4]; 2801 u8 log_sra_max[0x3]; 2802 u8 reserved_at_38b[0x2]; 2803 u8 retry_count[0x3]; 2804 u8 rnr_retry[0x3]; 2805 u8 reserved_at_393[0x1]; 2806 u8 fre[0x1]; 2807 u8 cur_rnr_retry[0x3]; 2808 u8 cur_retry_count[0x3]; 2809 u8 reserved_at_39b[0x5]; 2810 2811 u8 reserved_at_3a0[0x20]; 2812 2813 u8 reserved_at_3c0[0x8]; 2814 u8 next_send_psn[0x18]; 2815 2816 u8 reserved_at_3e0[0x8]; 2817 u8 cqn_snd[0x18]; 2818 2819 u8 reserved_at_400[0x8]; 2820 u8 deth_sqpn[0x18]; 2821 2822 u8 reserved_at_420[0x20]; 2823 2824 u8 reserved_at_440[0x8]; 2825 u8 last_acked_psn[0x18]; 2826 2827 u8 reserved_at_460[0x8]; 2828 u8 ssn[0x18]; 2829 2830 u8 reserved_at_480[0x8]; 2831 u8 log_rra_max[0x3]; 2832 u8 reserved_at_48b[0x1]; 2833 u8 atomic_mode[0x4]; 2834 u8 rre[0x1]; 2835 u8 rwe[0x1]; 2836 u8 rae[0x1]; 2837 u8 reserved_at_493[0x1]; 2838 u8 page_offset[0x6]; 2839 u8 reserved_at_49a[0x3]; 2840 u8 cd_slave_receive[0x1]; 2841 u8 cd_slave_send[0x1]; 2842 u8 cd_master[0x1]; 2843 2844 u8 reserved_at_4a0[0x3]; 2845 u8 min_rnr_nak[0x5]; 2846 u8 next_rcv_psn[0x18]; 2847 2848 u8 reserved_at_4c0[0x8]; 2849 u8 xrcd[0x18]; 2850 2851 u8 reserved_at_4e0[0x8]; 2852 u8 cqn_rcv[0x18]; 2853 2854 u8 dbr_addr[0x40]; 2855 2856 u8 q_key[0x20]; 2857 2858 u8 reserved_at_560[0x5]; 2859 u8 rq_type[0x3]; 2860 u8 srqn_rmpn_xrqn[0x18]; 2861 2862 u8 reserved_at_580[0x8]; 2863 u8 rmsn[0x18]; 2864 2865 u8 hw_sq_wqebb_counter[0x10]; 2866 u8 sw_sq_wqebb_counter[0x10]; 2867 2868 u8 hw_rq_counter[0x20]; 2869 2870 u8 sw_rq_counter[0x20]; 2871 2872 u8 reserved_at_600[0x20]; 2873 2874 u8 reserved_at_620[0xf]; 2875 u8 cgs[0x1]; 2876 u8 cs_req[0x8]; 2877 u8 cs_res[0x8]; 2878 2879 u8 dc_access_key[0x40]; 2880 2881 u8 reserved_at_680[0x3]; 2882 u8 dbr_umem_valid[0x1]; 2883 2884 u8 reserved_at_684[0xbc]; 2885 }; 2886 2887 struct mlx5_ifc_roce_addr_layout_bits { 2888 u8 source_l3_address[16][0x8]; 2889 2890 u8 reserved_at_80[0x3]; 2891 u8 vlan_valid[0x1]; 2892 u8 vlan_id[0xc]; 2893 u8 source_mac_47_32[0x10]; 2894 2895 u8 source_mac_31_0[0x20]; 2896 2897 u8 reserved_at_c0[0x14]; 2898 u8 roce_l3_type[0x4]; 2899 u8 roce_version[0x8]; 2900 2901 u8 reserved_at_e0[0x20]; 2902 }; 2903 2904 union mlx5_ifc_hca_cap_union_bits { 2905 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2906 struct mlx5_ifc_odp_cap_bits odp_cap; 2907 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2908 struct mlx5_ifc_roce_cap_bits roce_cap; 2909 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2910 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2911 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2912 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2913 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2914 struct mlx5_ifc_qos_cap_bits qos_cap; 2915 struct mlx5_ifc_debug_cap_bits debug_cap; 2916 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2917 struct mlx5_ifc_tls_cap_bits tls_cap; 2918 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2919 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap; 2920 u8 reserved_at_0[0x8000]; 2921 }; 2922 2923 enum { 2924 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2925 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2926 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2927 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2928 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2929 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2930 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2931 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2932 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2933 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2934 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2935 }; 2936 2937 enum { 2938 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2939 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2940 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2941 }; 2942 2943 struct mlx5_ifc_vlan_bits { 2944 u8 ethtype[0x10]; 2945 u8 prio[0x3]; 2946 u8 cfi[0x1]; 2947 u8 vid[0xc]; 2948 }; 2949 2950 struct mlx5_ifc_flow_context_bits { 2951 struct mlx5_ifc_vlan_bits push_vlan; 2952 2953 u8 group_id[0x20]; 2954 2955 u8 reserved_at_40[0x8]; 2956 u8 flow_tag[0x18]; 2957 2958 u8 reserved_at_60[0x10]; 2959 u8 action[0x10]; 2960 2961 u8 extended_destination[0x1]; 2962 u8 reserved_at_81[0x1]; 2963 u8 flow_source[0x2]; 2964 u8 reserved_at_84[0x4]; 2965 u8 destination_list_size[0x18]; 2966 2967 u8 reserved_at_a0[0x8]; 2968 u8 flow_counter_list_size[0x18]; 2969 2970 u8 packet_reformat_id[0x20]; 2971 2972 u8 modify_header_id[0x20]; 2973 2974 struct mlx5_ifc_vlan_bits push_vlan_2; 2975 2976 u8 reserved_at_120[0xe0]; 2977 2978 struct mlx5_ifc_fte_match_param_bits match_value; 2979 2980 u8 reserved_at_1200[0x600]; 2981 2982 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2983 }; 2984 2985 enum { 2986 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2987 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2988 }; 2989 2990 struct mlx5_ifc_xrc_srqc_bits { 2991 u8 state[0x4]; 2992 u8 log_xrc_srq_size[0x4]; 2993 u8 reserved_at_8[0x18]; 2994 2995 u8 wq_signature[0x1]; 2996 u8 cont_srq[0x1]; 2997 u8 reserved_at_22[0x1]; 2998 u8 rlky[0x1]; 2999 u8 basic_cyclic_rcv_wqe[0x1]; 3000 u8 log_rq_stride[0x3]; 3001 u8 xrcd[0x18]; 3002 3003 u8 page_offset[0x6]; 3004 u8 reserved_at_46[0x1]; 3005 u8 dbr_umem_valid[0x1]; 3006 u8 cqn[0x18]; 3007 3008 u8 reserved_at_60[0x20]; 3009 3010 u8 user_index_equal_xrc_srqn[0x1]; 3011 u8 reserved_at_81[0x1]; 3012 u8 log_page_size[0x6]; 3013 u8 user_index[0x18]; 3014 3015 u8 reserved_at_a0[0x20]; 3016 3017 u8 reserved_at_c0[0x8]; 3018 u8 pd[0x18]; 3019 3020 u8 lwm[0x10]; 3021 u8 wqe_cnt[0x10]; 3022 3023 u8 reserved_at_100[0x40]; 3024 3025 u8 db_record_addr_h[0x20]; 3026 3027 u8 db_record_addr_l[0x1e]; 3028 u8 reserved_at_17e[0x2]; 3029 3030 u8 reserved_at_180[0x80]; 3031 }; 3032 3033 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3034 u8 counter_error_queues[0x20]; 3035 3036 u8 total_error_queues[0x20]; 3037 3038 u8 send_queue_priority_update_flow[0x20]; 3039 3040 u8 reserved_at_60[0x20]; 3041 3042 u8 nic_receive_steering_discard[0x40]; 3043 3044 u8 receive_discard_vport_down[0x40]; 3045 3046 u8 transmit_discard_vport_down[0x40]; 3047 3048 u8 reserved_at_140[0xa0]; 3049 3050 u8 internal_rq_out_of_buffer[0x20]; 3051 3052 u8 reserved_at_200[0xe00]; 3053 }; 3054 3055 struct mlx5_ifc_traffic_counter_bits { 3056 u8 packets[0x40]; 3057 3058 u8 octets[0x40]; 3059 }; 3060 3061 struct mlx5_ifc_tisc_bits { 3062 u8 strict_lag_tx_port_affinity[0x1]; 3063 u8 tls_en[0x1]; 3064 u8 reserved_at_2[0x2]; 3065 u8 lag_tx_port_affinity[0x04]; 3066 3067 u8 reserved_at_8[0x4]; 3068 u8 prio[0x4]; 3069 u8 reserved_at_10[0x10]; 3070 3071 u8 reserved_at_20[0x100]; 3072 3073 u8 reserved_at_120[0x8]; 3074 u8 transport_domain[0x18]; 3075 3076 u8 reserved_at_140[0x8]; 3077 u8 underlay_qpn[0x18]; 3078 3079 u8 reserved_at_160[0x8]; 3080 u8 pd[0x18]; 3081 3082 u8 reserved_at_180[0x380]; 3083 }; 3084 3085 enum { 3086 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3087 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3088 }; 3089 3090 enum { 3091 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3092 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3093 }; 3094 3095 enum { 3096 MLX5_RX_HASH_FN_NONE = 0x0, 3097 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3098 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3099 }; 3100 3101 enum { 3102 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3103 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3104 }; 3105 3106 struct mlx5_ifc_tirc_bits { 3107 u8 reserved_at_0[0x20]; 3108 3109 u8 disp_type[0x4]; 3110 u8 reserved_at_24[0x1c]; 3111 3112 u8 reserved_at_40[0x40]; 3113 3114 u8 reserved_at_80[0x4]; 3115 u8 lro_timeout_period_usecs[0x10]; 3116 u8 lro_enable_mask[0x4]; 3117 u8 lro_max_ip_payload_size[0x8]; 3118 3119 u8 reserved_at_a0[0x40]; 3120 3121 u8 reserved_at_e0[0x8]; 3122 u8 inline_rqn[0x18]; 3123 3124 u8 rx_hash_symmetric[0x1]; 3125 u8 reserved_at_101[0x1]; 3126 u8 tunneled_offload_en[0x1]; 3127 u8 reserved_at_103[0x5]; 3128 u8 indirect_table[0x18]; 3129 3130 u8 rx_hash_fn[0x4]; 3131 u8 reserved_at_124[0x2]; 3132 u8 self_lb_block[0x2]; 3133 u8 transport_domain[0x18]; 3134 3135 u8 rx_hash_toeplitz_key[10][0x20]; 3136 3137 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3138 3139 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3140 3141 u8 reserved_at_2c0[0x4c0]; 3142 }; 3143 3144 enum { 3145 MLX5_SRQC_STATE_GOOD = 0x0, 3146 MLX5_SRQC_STATE_ERROR = 0x1, 3147 }; 3148 3149 struct mlx5_ifc_srqc_bits { 3150 u8 state[0x4]; 3151 u8 log_srq_size[0x4]; 3152 u8 reserved_at_8[0x18]; 3153 3154 u8 wq_signature[0x1]; 3155 u8 cont_srq[0x1]; 3156 u8 reserved_at_22[0x1]; 3157 u8 rlky[0x1]; 3158 u8 reserved_at_24[0x1]; 3159 u8 log_rq_stride[0x3]; 3160 u8 xrcd[0x18]; 3161 3162 u8 page_offset[0x6]; 3163 u8 reserved_at_46[0x2]; 3164 u8 cqn[0x18]; 3165 3166 u8 reserved_at_60[0x20]; 3167 3168 u8 reserved_at_80[0x2]; 3169 u8 log_page_size[0x6]; 3170 u8 reserved_at_88[0x18]; 3171 3172 u8 reserved_at_a0[0x20]; 3173 3174 u8 reserved_at_c0[0x8]; 3175 u8 pd[0x18]; 3176 3177 u8 lwm[0x10]; 3178 u8 wqe_cnt[0x10]; 3179 3180 u8 reserved_at_100[0x40]; 3181 3182 u8 dbr_addr[0x40]; 3183 3184 u8 reserved_at_180[0x80]; 3185 }; 3186 3187 enum { 3188 MLX5_SQC_STATE_RST = 0x0, 3189 MLX5_SQC_STATE_RDY = 0x1, 3190 MLX5_SQC_STATE_ERR = 0x3, 3191 }; 3192 3193 struct mlx5_ifc_sqc_bits { 3194 u8 rlky[0x1]; 3195 u8 cd_master[0x1]; 3196 u8 fre[0x1]; 3197 u8 flush_in_error_en[0x1]; 3198 u8 allow_multi_pkt_send_wqe[0x1]; 3199 u8 min_wqe_inline_mode[0x3]; 3200 u8 state[0x4]; 3201 u8 reg_umr[0x1]; 3202 u8 allow_swp[0x1]; 3203 u8 hairpin[0x1]; 3204 u8 reserved_at_f[0x11]; 3205 3206 u8 reserved_at_20[0x8]; 3207 u8 user_index[0x18]; 3208 3209 u8 reserved_at_40[0x8]; 3210 u8 cqn[0x18]; 3211 3212 u8 reserved_at_60[0x8]; 3213 u8 hairpin_peer_rq[0x18]; 3214 3215 u8 reserved_at_80[0x10]; 3216 u8 hairpin_peer_vhca[0x10]; 3217 3218 u8 reserved_at_a0[0x50]; 3219 3220 u8 packet_pacing_rate_limit_index[0x10]; 3221 u8 tis_lst_sz[0x10]; 3222 u8 reserved_at_110[0x10]; 3223 3224 u8 reserved_at_120[0x40]; 3225 3226 u8 reserved_at_160[0x8]; 3227 u8 tis_num_0[0x18]; 3228 3229 struct mlx5_ifc_wq_bits wq; 3230 }; 3231 3232 enum { 3233 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3234 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3235 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3236 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3237 }; 3238 3239 enum { 3240 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3241 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3242 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3243 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3244 }; 3245 3246 struct mlx5_ifc_scheduling_context_bits { 3247 u8 element_type[0x8]; 3248 u8 reserved_at_8[0x18]; 3249 3250 u8 element_attributes[0x20]; 3251 3252 u8 parent_element_id[0x20]; 3253 3254 u8 reserved_at_60[0x40]; 3255 3256 u8 bw_share[0x20]; 3257 3258 u8 max_average_bw[0x20]; 3259 3260 u8 reserved_at_e0[0x120]; 3261 }; 3262 3263 struct mlx5_ifc_rqtc_bits { 3264 u8 reserved_at_0[0xa0]; 3265 3266 u8 reserved_at_a0[0x10]; 3267 u8 rqt_max_size[0x10]; 3268 3269 u8 reserved_at_c0[0x10]; 3270 u8 rqt_actual_size[0x10]; 3271 3272 u8 reserved_at_e0[0x6a0]; 3273 3274 struct mlx5_ifc_rq_num_bits rq_num[0]; 3275 }; 3276 3277 enum { 3278 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3279 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3280 }; 3281 3282 enum { 3283 MLX5_RQC_STATE_RST = 0x0, 3284 MLX5_RQC_STATE_RDY = 0x1, 3285 MLX5_RQC_STATE_ERR = 0x3, 3286 }; 3287 3288 struct mlx5_ifc_rqc_bits { 3289 u8 rlky[0x1]; 3290 u8 delay_drop_en[0x1]; 3291 u8 scatter_fcs[0x1]; 3292 u8 vsd[0x1]; 3293 u8 mem_rq_type[0x4]; 3294 u8 state[0x4]; 3295 u8 reserved_at_c[0x1]; 3296 u8 flush_in_error_en[0x1]; 3297 u8 hairpin[0x1]; 3298 u8 reserved_at_f[0x11]; 3299 3300 u8 reserved_at_20[0x8]; 3301 u8 user_index[0x18]; 3302 3303 u8 reserved_at_40[0x8]; 3304 u8 cqn[0x18]; 3305 3306 u8 counter_set_id[0x8]; 3307 u8 reserved_at_68[0x18]; 3308 3309 u8 reserved_at_80[0x8]; 3310 u8 rmpn[0x18]; 3311 3312 u8 reserved_at_a0[0x8]; 3313 u8 hairpin_peer_sq[0x18]; 3314 3315 u8 reserved_at_c0[0x10]; 3316 u8 hairpin_peer_vhca[0x10]; 3317 3318 u8 reserved_at_e0[0xa0]; 3319 3320 struct mlx5_ifc_wq_bits wq; 3321 }; 3322 3323 enum { 3324 MLX5_RMPC_STATE_RDY = 0x1, 3325 MLX5_RMPC_STATE_ERR = 0x3, 3326 }; 3327 3328 struct mlx5_ifc_rmpc_bits { 3329 u8 reserved_at_0[0x8]; 3330 u8 state[0x4]; 3331 u8 reserved_at_c[0x14]; 3332 3333 u8 basic_cyclic_rcv_wqe[0x1]; 3334 u8 reserved_at_21[0x1f]; 3335 3336 u8 reserved_at_40[0x140]; 3337 3338 struct mlx5_ifc_wq_bits wq; 3339 }; 3340 3341 struct mlx5_ifc_nic_vport_context_bits { 3342 u8 reserved_at_0[0x5]; 3343 u8 min_wqe_inline_mode[0x3]; 3344 u8 reserved_at_8[0x15]; 3345 u8 disable_mc_local_lb[0x1]; 3346 u8 disable_uc_local_lb[0x1]; 3347 u8 roce_en[0x1]; 3348 3349 u8 arm_change_event[0x1]; 3350 u8 reserved_at_21[0x1a]; 3351 u8 event_on_mtu[0x1]; 3352 u8 event_on_promisc_change[0x1]; 3353 u8 event_on_vlan_change[0x1]; 3354 u8 event_on_mc_address_change[0x1]; 3355 u8 event_on_uc_address_change[0x1]; 3356 3357 u8 reserved_at_40[0xc]; 3358 3359 u8 affiliation_criteria[0x4]; 3360 u8 affiliated_vhca_id[0x10]; 3361 3362 u8 reserved_at_60[0xd0]; 3363 3364 u8 mtu[0x10]; 3365 3366 u8 system_image_guid[0x40]; 3367 u8 port_guid[0x40]; 3368 u8 node_guid[0x40]; 3369 3370 u8 reserved_at_200[0x140]; 3371 u8 qkey_violation_counter[0x10]; 3372 u8 reserved_at_350[0x430]; 3373 3374 u8 promisc_uc[0x1]; 3375 u8 promisc_mc[0x1]; 3376 u8 promisc_all[0x1]; 3377 u8 reserved_at_783[0x2]; 3378 u8 allowed_list_type[0x3]; 3379 u8 reserved_at_788[0xc]; 3380 u8 allowed_list_size[0xc]; 3381 3382 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3383 3384 u8 reserved_at_7e0[0x20]; 3385 3386 u8 current_uc_mac_address[0][0x40]; 3387 }; 3388 3389 enum { 3390 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3391 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3392 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3393 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3394 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3395 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3396 }; 3397 3398 struct mlx5_ifc_mkc_bits { 3399 u8 reserved_at_0[0x1]; 3400 u8 free[0x1]; 3401 u8 reserved_at_2[0x1]; 3402 u8 access_mode_4_2[0x3]; 3403 u8 reserved_at_6[0x7]; 3404 u8 relaxed_ordering_write[0x1]; 3405 u8 reserved_at_e[0x1]; 3406 u8 small_fence_on_rdma_read_response[0x1]; 3407 u8 umr_en[0x1]; 3408 u8 a[0x1]; 3409 u8 rw[0x1]; 3410 u8 rr[0x1]; 3411 u8 lw[0x1]; 3412 u8 lr[0x1]; 3413 u8 access_mode_1_0[0x2]; 3414 u8 reserved_at_18[0x8]; 3415 3416 u8 qpn[0x18]; 3417 u8 mkey_7_0[0x8]; 3418 3419 u8 reserved_at_40[0x20]; 3420 3421 u8 length64[0x1]; 3422 u8 bsf_en[0x1]; 3423 u8 sync_umr[0x1]; 3424 u8 reserved_at_63[0x2]; 3425 u8 expected_sigerr_count[0x1]; 3426 u8 reserved_at_66[0x1]; 3427 u8 en_rinval[0x1]; 3428 u8 pd[0x18]; 3429 3430 u8 start_addr[0x40]; 3431 3432 u8 len[0x40]; 3433 3434 u8 bsf_octword_size[0x20]; 3435 3436 u8 reserved_at_120[0x80]; 3437 3438 u8 translations_octword_size[0x20]; 3439 3440 u8 reserved_at_1c0[0x19]; 3441 u8 relaxed_ordering_read[0x1]; 3442 u8 reserved_at_1d9[0x1]; 3443 u8 log_page_size[0x5]; 3444 3445 u8 reserved_at_1e0[0x20]; 3446 }; 3447 3448 struct mlx5_ifc_pkey_bits { 3449 u8 reserved_at_0[0x10]; 3450 u8 pkey[0x10]; 3451 }; 3452 3453 struct mlx5_ifc_array128_auto_bits { 3454 u8 array128_auto[16][0x8]; 3455 }; 3456 3457 struct mlx5_ifc_hca_vport_context_bits { 3458 u8 field_select[0x20]; 3459 3460 u8 reserved_at_20[0xe0]; 3461 3462 u8 sm_virt_aware[0x1]; 3463 u8 has_smi[0x1]; 3464 u8 has_raw[0x1]; 3465 u8 grh_required[0x1]; 3466 u8 reserved_at_104[0xc]; 3467 u8 port_physical_state[0x4]; 3468 u8 vport_state_policy[0x4]; 3469 u8 port_state[0x4]; 3470 u8 vport_state[0x4]; 3471 3472 u8 reserved_at_120[0x20]; 3473 3474 u8 system_image_guid[0x40]; 3475 3476 u8 port_guid[0x40]; 3477 3478 u8 node_guid[0x40]; 3479 3480 u8 cap_mask1[0x20]; 3481 3482 u8 cap_mask1_field_select[0x20]; 3483 3484 u8 cap_mask2[0x20]; 3485 3486 u8 cap_mask2_field_select[0x20]; 3487 3488 u8 reserved_at_280[0x80]; 3489 3490 u8 lid[0x10]; 3491 u8 reserved_at_310[0x4]; 3492 u8 init_type_reply[0x4]; 3493 u8 lmc[0x3]; 3494 u8 subnet_timeout[0x5]; 3495 3496 u8 sm_lid[0x10]; 3497 u8 sm_sl[0x4]; 3498 u8 reserved_at_334[0xc]; 3499 3500 u8 qkey_violation_counter[0x10]; 3501 u8 pkey_violation_counter[0x10]; 3502 3503 u8 reserved_at_360[0xca0]; 3504 }; 3505 3506 struct mlx5_ifc_esw_vport_context_bits { 3507 u8 fdb_to_vport_reg_c[0x1]; 3508 u8 reserved_at_1[0x2]; 3509 u8 vport_svlan_strip[0x1]; 3510 u8 vport_cvlan_strip[0x1]; 3511 u8 vport_svlan_insert[0x1]; 3512 u8 vport_cvlan_insert[0x2]; 3513 u8 fdb_to_vport_reg_c_id[0x8]; 3514 u8 reserved_at_10[0x10]; 3515 3516 u8 reserved_at_20[0x20]; 3517 3518 u8 svlan_cfi[0x1]; 3519 u8 svlan_pcp[0x3]; 3520 u8 svlan_id[0xc]; 3521 u8 cvlan_cfi[0x1]; 3522 u8 cvlan_pcp[0x3]; 3523 u8 cvlan_id[0xc]; 3524 3525 u8 reserved_at_60[0x720]; 3526 3527 u8 sw_steering_vport_icm_address_rx[0x40]; 3528 3529 u8 sw_steering_vport_icm_address_tx[0x40]; 3530 }; 3531 3532 enum { 3533 MLX5_EQC_STATUS_OK = 0x0, 3534 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3535 }; 3536 3537 enum { 3538 MLX5_EQC_ST_ARMED = 0x9, 3539 MLX5_EQC_ST_FIRED = 0xa, 3540 }; 3541 3542 struct mlx5_ifc_eqc_bits { 3543 u8 status[0x4]; 3544 u8 reserved_at_4[0x9]; 3545 u8 ec[0x1]; 3546 u8 oi[0x1]; 3547 u8 reserved_at_f[0x5]; 3548 u8 st[0x4]; 3549 u8 reserved_at_18[0x8]; 3550 3551 u8 reserved_at_20[0x20]; 3552 3553 u8 reserved_at_40[0x14]; 3554 u8 page_offset[0x6]; 3555 u8 reserved_at_5a[0x6]; 3556 3557 u8 reserved_at_60[0x3]; 3558 u8 log_eq_size[0x5]; 3559 u8 uar_page[0x18]; 3560 3561 u8 reserved_at_80[0x20]; 3562 3563 u8 reserved_at_a0[0x18]; 3564 u8 intr[0x8]; 3565 3566 u8 reserved_at_c0[0x3]; 3567 u8 log_page_size[0x5]; 3568 u8 reserved_at_c8[0x18]; 3569 3570 u8 reserved_at_e0[0x60]; 3571 3572 u8 reserved_at_140[0x8]; 3573 u8 consumer_counter[0x18]; 3574 3575 u8 reserved_at_160[0x8]; 3576 u8 producer_counter[0x18]; 3577 3578 u8 reserved_at_180[0x80]; 3579 }; 3580 3581 enum { 3582 MLX5_DCTC_STATE_ACTIVE = 0x0, 3583 MLX5_DCTC_STATE_DRAINING = 0x1, 3584 MLX5_DCTC_STATE_DRAINED = 0x2, 3585 }; 3586 3587 enum { 3588 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3589 MLX5_DCTC_CS_RES_NA = 0x1, 3590 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3591 }; 3592 3593 enum { 3594 MLX5_DCTC_MTU_256_BYTES = 0x1, 3595 MLX5_DCTC_MTU_512_BYTES = 0x2, 3596 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3597 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3598 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3599 }; 3600 3601 struct mlx5_ifc_dctc_bits { 3602 u8 reserved_at_0[0x4]; 3603 u8 state[0x4]; 3604 u8 reserved_at_8[0x18]; 3605 3606 u8 reserved_at_20[0x8]; 3607 u8 user_index[0x18]; 3608 3609 u8 reserved_at_40[0x8]; 3610 u8 cqn[0x18]; 3611 3612 u8 counter_set_id[0x8]; 3613 u8 atomic_mode[0x4]; 3614 u8 rre[0x1]; 3615 u8 rwe[0x1]; 3616 u8 rae[0x1]; 3617 u8 atomic_like_write_en[0x1]; 3618 u8 latency_sensitive[0x1]; 3619 u8 rlky[0x1]; 3620 u8 free_ar[0x1]; 3621 u8 reserved_at_73[0xd]; 3622 3623 u8 reserved_at_80[0x8]; 3624 u8 cs_res[0x8]; 3625 u8 reserved_at_90[0x3]; 3626 u8 min_rnr_nak[0x5]; 3627 u8 reserved_at_98[0x8]; 3628 3629 u8 reserved_at_a0[0x8]; 3630 u8 srqn_xrqn[0x18]; 3631 3632 u8 reserved_at_c0[0x8]; 3633 u8 pd[0x18]; 3634 3635 u8 tclass[0x8]; 3636 u8 reserved_at_e8[0x4]; 3637 u8 flow_label[0x14]; 3638 3639 u8 dc_access_key[0x40]; 3640 3641 u8 reserved_at_140[0x5]; 3642 u8 mtu[0x3]; 3643 u8 port[0x8]; 3644 u8 pkey_index[0x10]; 3645 3646 u8 reserved_at_160[0x8]; 3647 u8 my_addr_index[0x8]; 3648 u8 reserved_at_170[0x8]; 3649 u8 hop_limit[0x8]; 3650 3651 u8 dc_access_key_violation_count[0x20]; 3652 3653 u8 reserved_at_1a0[0x14]; 3654 u8 dei_cfi[0x1]; 3655 u8 eth_prio[0x3]; 3656 u8 ecn[0x2]; 3657 u8 dscp[0x6]; 3658 3659 u8 reserved_at_1c0[0x40]; 3660 }; 3661 3662 enum { 3663 MLX5_CQC_STATUS_OK = 0x0, 3664 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3665 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3666 }; 3667 3668 enum { 3669 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3670 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3671 }; 3672 3673 enum { 3674 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3675 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3676 MLX5_CQC_ST_FIRED = 0xa, 3677 }; 3678 3679 enum { 3680 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3681 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3682 MLX5_CQ_PERIOD_NUM_MODES 3683 }; 3684 3685 struct mlx5_ifc_cqc_bits { 3686 u8 status[0x4]; 3687 u8 reserved_at_4[0x2]; 3688 u8 dbr_umem_valid[0x1]; 3689 u8 reserved_at_7[0x1]; 3690 u8 cqe_sz[0x3]; 3691 u8 cc[0x1]; 3692 u8 reserved_at_c[0x1]; 3693 u8 scqe_break_moderation_en[0x1]; 3694 u8 oi[0x1]; 3695 u8 cq_period_mode[0x2]; 3696 u8 cqe_comp_en[0x1]; 3697 u8 mini_cqe_res_format[0x2]; 3698 u8 st[0x4]; 3699 u8 reserved_at_18[0x8]; 3700 3701 u8 reserved_at_20[0x20]; 3702 3703 u8 reserved_at_40[0x14]; 3704 u8 page_offset[0x6]; 3705 u8 reserved_at_5a[0x6]; 3706 3707 u8 reserved_at_60[0x3]; 3708 u8 log_cq_size[0x5]; 3709 u8 uar_page[0x18]; 3710 3711 u8 reserved_at_80[0x4]; 3712 u8 cq_period[0xc]; 3713 u8 cq_max_count[0x10]; 3714 3715 u8 reserved_at_a0[0x18]; 3716 u8 c_eqn[0x8]; 3717 3718 u8 reserved_at_c0[0x3]; 3719 u8 log_page_size[0x5]; 3720 u8 reserved_at_c8[0x18]; 3721 3722 u8 reserved_at_e0[0x20]; 3723 3724 u8 reserved_at_100[0x8]; 3725 u8 last_notified_index[0x18]; 3726 3727 u8 reserved_at_120[0x8]; 3728 u8 last_solicit_index[0x18]; 3729 3730 u8 reserved_at_140[0x8]; 3731 u8 consumer_counter[0x18]; 3732 3733 u8 reserved_at_160[0x8]; 3734 u8 producer_counter[0x18]; 3735 3736 u8 reserved_at_180[0x40]; 3737 3738 u8 dbr_addr[0x40]; 3739 }; 3740 3741 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3742 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3743 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3744 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3745 u8 reserved_at_0[0x800]; 3746 }; 3747 3748 struct mlx5_ifc_query_adapter_param_block_bits { 3749 u8 reserved_at_0[0xc0]; 3750 3751 u8 reserved_at_c0[0x8]; 3752 u8 ieee_vendor_id[0x18]; 3753 3754 u8 reserved_at_e0[0x10]; 3755 u8 vsd_vendor_id[0x10]; 3756 3757 u8 vsd[208][0x8]; 3758 3759 u8 vsd_contd_psid[16][0x8]; 3760 }; 3761 3762 enum { 3763 MLX5_XRQC_STATE_GOOD = 0x0, 3764 MLX5_XRQC_STATE_ERROR = 0x1, 3765 }; 3766 3767 enum { 3768 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3769 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3770 }; 3771 3772 enum { 3773 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3774 }; 3775 3776 struct mlx5_ifc_tag_matching_topology_context_bits { 3777 u8 log_matching_list_sz[0x4]; 3778 u8 reserved_at_4[0xc]; 3779 u8 append_next_index[0x10]; 3780 3781 u8 sw_phase_cnt[0x10]; 3782 u8 hw_phase_cnt[0x10]; 3783 3784 u8 reserved_at_40[0x40]; 3785 }; 3786 3787 struct mlx5_ifc_xrqc_bits { 3788 u8 state[0x4]; 3789 u8 rlkey[0x1]; 3790 u8 reserved_at_5[0xf]; 3791 u8 topology[0x4]; 3792 u8 reserved_at_18[0x4]; 3793 u8 offload[0x4]; 3794 3795 u8 reserved_at_20[0x8]; 3796 u8 user_index[0x18]; 3797 3798 u8 reserved_at_40[0x8]; 3799 u8 cqn[0x18]; 3800 3801 u8 reserved_at_60[0xa0]; 3802 3803 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3804 3805 u8 reserved_at_180[0x280]; 3806 3807 struct mlx5_ifc_wq_bits wq; 3808 }; 3809 3810 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3811 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3812 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3813 u8 reserved_at_0[0x20]; 3814 }; 3815 3816 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3817 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3818 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3819 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3820 u8 reserved_at_0[0x20]; 3821 }; 3822 3823 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3824 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3825 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3826 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3827 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3828 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3829 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3830 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3831 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3832 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3833 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3834 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3835 u8 reserved_at_0[0x7c0]; 3836 }; 3837 3838 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3839 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3840 u8 reserved_at_0[0x7c0]; 3841 }; 3842 3843 union mlx5_ifc_event_auto_bits { 3844 struct mlx5_ifc_comp_event_bits comp_event; 3845 struct mlx5_ifc_dct_events_bits dct_events; 3846 struct mlx5_ifc_qp_events_bits qp_events; 3847 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3848 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3849 struct mlx5_ifc_cq_error_bits cq_error; 3850 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3851 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3852 struct mlx5_ifc_gpio_event_bits gpio_event; 3853 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3854 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3855 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3856 u8 reserved_at_0[0xe0]; 3857 }; 3858 3859 struct mlx5_ifc_health_buffer_bits { 3860 u8 reserved_at_0[0x100]; 3861 3862 u8 assert_existptr[0x20]; 3863 3864 u8 assert_callra[0x20]; 3865 3866 u8 reserved_at_140[0x40]; 3867 3868 u8 fw_version[0x20]; 3869 3870 u8 hw_id[0x20]; 3871 3872 u8 reserved_at_1c0[0x20]; 3873 3874 u8 irisc_index[0x8]; 3875 u8 synd[0x8]; 3876 u8 ext_synd[0x10]; 3877 }; 3878 3879 struct mlx5_ifc_register_loopback_control_bits { 3880 u8 no_lb[0x1]; 3881 u8 reserved_at_1[0x7]; 3882 u8 port[0x8]; 3883 u8 reserved_at_10[0x10]; 3884 3885 u8 reserved_at_20[0x60]; 3886 }; 3887 3888 struct mlx5_ifc_vport_tc_element_bits { 3889 u8 traffic_class[0x4]; 3890 u8 reserved_at_4[0xc]; 3891 u8 vport_number[0x10]; 3892 }; 3893 3894 struct mlx5_ifc_vport_element_bits { 3895 u8 reserved_at_0[0x10]; 3896 u8 vport_number[0x10]; 3897 }; 3898 3899 enum { 3900 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3901 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3902 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3903 }; 3904 3905 struct mlx5_ifc_tsar_element_bits { 3906 u8 reserved_at_0[0x8]; 3907 u8 tsar_type[0x8]; 3908 u8 reserved_at_10[0x10]; 3909 }; 3910 3911 enum { 3912 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3913 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3914 }; 3915 3916 struct mlx5_ifc_teardown_hca_out_bits { 3917 u8 status[0x8]; 3918 u8 reserved_at_8[0x18]; 3919 3920 u8 syndrome[0x20]; 3921 3922 u8 reserved_at_40[0x3f]; 3923 3924 u8 state[0x1]; 3925 }; 3926 3927 enum { 3928 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3929 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3930 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3931 }; 3932 3933 struct mlx5_ifc_teardown_hca_in_bits { 3934 u8 opcode[0x10]; 3935 u8 reserved_at_10[0x10]; 3936 3937 u8 reserved_at_20[0x10]; 3938 u8 op_mod[0x10]; 3939 3940 u8 reserved_at_40[0x10]; 3941 u8 profile[0x10]; 3942 3943 u8 reserved_at_60[0x20]; 3944 }; 3945 3946 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3947 u8 status[0x8]; 3948 u8 reserved_at_8[0x18]; 3949 3950 u8 syndrome[0x20]; 3951 3952 u8 reserved_at_40[0x40]; 3953 }; 3954 3955 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3956 u8 opcode[0x10]; 3957 u8 uid[0x10]; 3958 3959 u8 reserved_at_20[0x10]; 3960 u8 op_mod[0x10]; 3961 3962 u8 reserved_at_40[0x8]; 3963 u8 qpn[0x18]; 3964 3965 u8 reserved_at_60[0x20]; 3966 3967 u8 opt_param_mask[0x20]; 3968 3969 u8 reserved_at_a0[0x20]; 3970 3971 struct mlx5_ifc_qpc_bits qpc; 3972 3973 u8 reserved_at_800[0x80]; 3974 }; 3975 3976 struct mlx5_ifc_sqd2rts_qp_out_bits { 3977 u8 status[0x8]; 3978 u8 reserved_at_8[0x18]; 3979 3980 u8 syndrome[0x20]; 3981 3982 u8 reserved_at_40[0x40]; 3983 }; 3984 3985 struct mlx5_ifc_sqd2rts_qp_in_bits { 3986 u8 opcode[0x10]; 3987 u8 uid[0x10]; 3988 3989 u8 reserved_at_20[0x10]; 3990 u8 op_mod[0x10]; 3991 3992 u8 reserved_at_40[0x8]; 3993 u8 qpn[0x18]; 3994 3995 u8 reserved_at_60[0x20]; 3996 3997 u8 opt_param_mask[0x20]; 3998 3999 u8 reserved_at_a0[0x20]; 4000 4001 struct mlx5_ifc_qpc_bits qpc; 4002 4003 u8 reserved_at_800[0x80]; 4004 }; 4005 4006 struct mlx5_ifc_set_roce_address_out_bits { 4007 u8 status[0x8]; 4008 u8 reserved_at_8[0x18]; 4009 4010 u8 syndrome[0x20]; 4011 4012 u8 reserved_at_40[0x40]; 4013 }; 4014 4015 struct mlx5_ifc_set_roce_address_in_bits { 4016 u8 opcode[0x10]; 4017 u8 reserved_at_10[0x10]; 4018 4019 u8 reserved_at_20[0x10]; 4020 u8 op_mod[0x10]; 4021 4022 u8 roce_address_index[0x10]; 4023 u8 reserved_at_50[0xc]; 4024 u8 vhca_port_num[0x4]; 4025 4026 u8 reserved_at_60[0x20]; 4027 4028 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4029 }; 4030 4031 struct mlx5_ifc_set_mad_demux_out_bits { 4032 u8 status[0x8]; 4033 u8 reserved_at_8[0x18]; 4034 4035 u8 syndrome[0x20]; 4036 4037 u8 reserved_at_40[0x40]; 4038 }; 4039 4040 enum { 4041 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4042 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4043 }; 4044 4045 struct mlx5_ifc_set_mad_demux_in_bits { 4046 u8 opcode[0x10]; 4047 u8 reserved_at_10[0x10]; 4048 4049 u8 reserved_at_20[0x10]; 4050 u8 op_mod[0x10]; 4051 4052 u8 reserved_at_40[0x20]; 4053 4054 u8 reserved_at_60[0x6]; 4055 u8 demux_mode[0x2]; 4056 u8 reserved_at_68[0x18]; 4057 }; 4058 4059 struct mlx5_ifc_set_l2_table_entry_out_bits { 4060 u8 status[0x8]; 4061 u8 reserved_at_8[0x18]; 4062 4063 u8 syndrome[0x20]; 4064 4065 u8 reserved_at_40[0x40]; 4066 }; 4067 4068 struct mlx5_ifc_set_l2_table_entry_in_bits { 4069 u8 opcode[0x10]; 4070 u8 reserved_at_10[0x10]; 4071 4072 u8 reserved_at_20[0x10]; 4073 u8 op_mod[0x10]; 4074 4075 u8 reserved_at_40[0x60]; 4076 4077 u8 reserved_at_a0[0x8]; 4078 u8 table_index[0x18]; 4079 4080 u8 reserved_at_c0[0x20]; 4081 4082 u8 reserved_at_e0[0x13]; 4083 u8 vlan_valid[0x1]; 4084 u8 vlan[0xc]; 4085 4086 struct mlx5_ifc_mac_address_layout_bits mac_address; 4087 4088 u8 reserved_at_140[0xc0]; 4089 }; 4090 4091 struct mlx5_ifc_set_issi_out_bits { 4092 u8 status[0x8]; 4093 u8 reserved_at_8[0x18]; 4094 4095 u8 syndrome[0x20]; 4096 4097 u8 reserved_at_40[0x40]; 4098 }; 4099 4100 struct mlx5_ifc_set_issi_in_bits { 4101 u8 opcode[0x10]; 4102 u8 reserved_at_10[0x10]; 4103 4104 u8 reserved_at_20[0x10]; 4105 u8 op_mod[0x10]; 4106 4107 u8 reserved_at_40[0x10]; 4108 u8 current_issi[0x10]; 4109 4110 u8 reserved_at_60[0x20]; 4111 }; 4112 4113 struct mlx5_ifc_set_hca_cap_out_bits { 4114 u8 status[0x8]; 4115 u8 reserved_at_8[0x18]; 4116 4117 u8 syndrome[0x20]; 4118 4119 u8 reserved_at_40[0x40]; 4120 }; 4121 4122 struct mlx5_ifc_set_hca_cap_in_bits { 4123 u8 opcode[0x10]; 4124 u8 reserved_at_10[0x10]; 4125 4126 u8 reserved_at_20[0x10]; 4127 u8 op_mod[0x10]; 4128 4129 u8 reserved_at_40[0x40]; 4130 4131 union mlx5_ifc_hca_cap_union_bits capability; 4132 }; 4133 4134 enum { 4135 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4136 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4137 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4138 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 4139 }; 4140 4141 struct mlx5_ifc_set_fte_out_bits { 4142 u8 status[0x8]; 4143 u8 reserved_at_8[0x18]; 4144 4145 u8 syndrome[0x20]; 4146 4147 u8 reserved_at_40[0x40]; 4148 }; 4149 4150 struct mlx5_ifc_set_fte_in_bits { 4151 u8 opcode[0x10]; 4152 u8 reserved_at_10[0x10]; 4153 4154 u8 reserved_at_20[0x10]; 4155 u8 op_mod[0x10]; 4156 4157 u8 other_vport[0x1]; 4158 u8 reserved_at_41[0xf]; 4159 u8 vport_number[0x10]; 4160 4161 u8 reserved_at_60[0x20]; 4162 4163 u8 table_type[0x8]; 4164 u8 reserved_at_88[0x18]; 4165 4166 u8 reserved_at_a0[0x8]; 4167 u8 table_id[0x18]; 4168 4169 u8 ignore_flow_level[0x1]; 4170 u8 reserved_at_c1[0x17]; 4171 u8 modify_enable_mask[0x8]; 4172 4173 u8 reserved_at_e0[0x20]; 4174 4175 u8 flow_index[0x20]; 4176 4177 u8 reserved_at_120[0xe0]; 4178 4179 struct mlx5_ifc_flow_context_bits flow_context; 4180 }; 4181 4182 struct mlx5_ifc_rts2rts_qp_out_bits { 4183 u8 status[0x8]; 4184 u8 reserved_at_8[0x18]; 4185 4186 u8 syndrome[0x20]; 4187 4188 u8 reserved_at_40[0x40]; 4189 }; 4190 4191 struct mlx5_ifc_rts2rts_qp_in_bits { 4192 u8 opcode[0x10]; 4193 u8 uid[0x10]; 4194 4195 u8 reserved_at_20[0x10]; 4196 u8 op_mod[0x10]; 4197 4198 u8 reserved_at_40[0x8]; 4199 u8 qpn[0x18]; 4200 4201 u8 reserved_at_60[0x20]; 4202 4203 u8 opt_param_mask[0x20]; 4204 4205 u8 reserved_at_a0[0x20]; 4206 4207 struct mlx5_ifc_qpc_bits qpc; 4208 4209 u8 reserved_at_800[0x80]; 4210 }; 4211 4212 struct mlx5_ifc_rtr2rts_qp_out_bits { 4213 u8 status[0x8]; 4214 u8 reserved_at_8[0x18]; 4215 4216 u8 syndrome[0x20]; 4217 4218 u8 reserved_at_40[0x40]; 4219 }; 4220 4221 struct mlx5_ifc_rtr2rts_qp_in_bits { 4222 u8 opcode[0x10]; 4223 u8 uid[0x10]; 4224 4225 u8 reserved_at_20[0x10]; 4226 u8 op_mod[0x10]; 4227 4228 u8 reserved_at_40[0x8]; 4229 u8 qpn[0x18]; 4230 4231 u8 reserved_at_60[0x20]; 4232 4233 u8 opt_param_mask[0x20]; 4234 4235 u8 reserved_at_a0[0x20]; 4236 4237 struct mlx5_ifc_qpc_bits qpc; 4238 4239 u8 reserved_at_800[0x80]; 4240 }; 4241 4242 struct mlx5_ifc_rst2init_qp_out_bits { 4243 u8 status[0x8]; 4244 u8 reserved_at_8[0x18]; 4245 4246 u8 syndrome[0x20]; 4247 4248 u8 reserved_at_40[0x40]; 4249 }; 4250 4251 struct mlx5_ifc_rst2init_qp_in_bits { 4252 u8 opcode[0x10]; 4253 u8 uid[0x10]; 4254 4255 u8 reserved_at_20[0x10]; 4256 u8 op_mod[0x10]; 4257 4258 u8 reserved_at_40[0x8]; 4259 u8 qpn[0x18]; 4260 4261 u8 reserved_at_60[0x20]; 4262 4263 u8 opt_param_mask[0x20]; 4264 4265 u8 reserved_at_a0[0x20]; 4266 4267 struct mlx5_ifc_qpc_bits qpc; 4268 4269 u8 reserved_at_800[0x80]; 4270 }; 4271 4272 struct mlx5_ifc_query_xrq_out_bits { 4273 u8 status[0x8]; 4274 u8 reserved_at_8[0x18]; 4275 4276 u8 syndrome[0x20]; 4277 4278 u8 reserved_at_40[0x40]; 4279 4280 struct mlx5_ifc_xrqc_bits xrq_context; 4281 }; 4282 4283 struct mlx5_ifc_query_xrq_in_bits { 4284 u8 opcode[0x10]; 4285 u8 reserved_at_10[0x10]; 4286 4287 u8 reserved_at_20[0x10]; 4288 u8 op_mod[0x10]; 4289 4290 u8 reserved_at_40[0x8]; 4291 u8 xrqn[0x18]; 4292 4293 u8 reserved_at_60[0x20]; 4294 }; 4295 4296 struct mlx5_ifc_query_xrc_srq_out_bits { 4297 u8 status[0x8]; 4298 u8 reserved_at_8[0x18]; 4299 4300 u8 syndrome[0x20]; 4301 4302 u8 reserved_at_40[0x40]; 4303 4304 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4305 4306 u8 reserved_at_280[0x600]; 4307 4308 u8 pas[0][0x40]; 4309 }; 4310 4311 struct mlx5_ifc_query_xrc_srq_in_bits { 4312 u8 opcode[0x10]; 4313 u8 reserved_at_10[0x10]; 4314 4315 u8 reserved_at_20[0x10]; 4316 u8 op_mod[0x10]; 4317 4318 u8 reserved_at_40[0x8]; 4319 u8 xrc_srqn[0x18]; 4320 4321 u8 reserved_at_60[0x20]; 4322 }; 4323 4324 enum { 4325 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4326 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4327 }; 4328 4329 struct mlx5_ifc_query_vport_state_out_bits { 4330 u8 status[0x8]; 4331 u8 reserved_at_8[0x18]; 4332 4333 u8 syndrome[0x20]; 4334 4335 u8 reserved_at_40[0x20]; 4336 4337 u8 reserved_at_60[0x18]; 4338 u8 admin_state[0x4]; 4339 u8 state[0x4]; 4340 }; 4341 4342 enum { 4343 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4344 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4345 }; 4346 4347 struct mlx5_ifc_arm_monitor_counter_in_bits { 4348 u8 opcode[0x10]; 4349 u8 uid[0x10]; 4350 4351 u8 reserved_at_20[0x10]; 4352 u8 op_mod[0x10]; 4353 4354 u8 reserved_at_40[0x20]; 4355 4356 u8 reserved_at_60[0x20]; 4357 }; 4358 4359 struct mlx5_ifc_arm_monitor_counter_out_bits { 4360 u8 status[0x8]; 4361 u8 reserved_at_8[0x18]; 4362 4363 u8 syndrome[0x20]; 4364 4365 u8 reserved_at_40[0x40]; 4366 }; 4367 4368 enum { 4369 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4370 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4371 }; 4372 4373 enum mlx5_monitor_counter_ppcnt { 4374 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4375 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4376 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4377 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4378 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4379 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4380 }; 4381 4382 enum { 4383 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4384 }; 4385 4386 struct mlx5_ifc_monitor_counter_output_bits { 4387 u8 reserved_at_0[0x4]; 4388 u8 type[0x4]; 4389 u8 reserved_at_8[0x8]; 4390 u8 counter[0x10]; 4391 4392 u8 counter_group_id[0x20]; 4393 }; 4394 4395 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4396 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4397 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4398 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4399 4400 struct mlx5_ifc_set_monitor_counter_in_bits { 4401 u8 opcode[0x10]; 4402 u8 uid[0x10]; 4403 4404 u8 reserved_at_20[0x10]; 4405 u8 op_mod[0x10]; 4406 4407 u8 reserved_at_40[0x10]; 4408 u8 num_of_counters[0x10]; 4409 4410 u8 reserved_at_60[0x20]; 4411 4412 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4413 }; 4414 4415 struct mlx5_ifc_set_monitor_counter_out_bits { 4416 u8 status[0x8]; 4417 u8 reserved_at_8[0x18]; 4418 4419 u8 syndrome[0x20]; 4420 4421 u8 reserved_at_40[0x40]; 4422 }; 4423 4424 struct mlx5_ifc_query_vport_state_in_bits { 4425 u8 opcode[0x10]; 4426 u8 reserved_at_10[0x10]; 4427 4428 u8 reserved_at_20[0x10]; 4429 u8 op_mod[0x10]; 4430 4431 u8 other_vport[0x1]; 4432 u8 reserved_at_41[0xf]; 4433 u8 vport_number[0x10]; 4434 4435 u8 reserved_at_60[0x20]; 4436 }; 4437 4438 struct mlx5_ifc_query_vnic_env_out_bits { 4439 u8 status[0x8]; 4440 u8 reserved_at_8[0x18]; 4441 4442 u8 syndrome[0x20]; 4443 4444 u8 reserved_at_40[0x40]; 4445 4446 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4447 }; 4448 4449 enum { 4450 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4451 }; 4452 4453 struct mlx5_ifc_query_vnic_env_in_bits { 4454 u8 opcode[0x10]; 4455 u8 reserved_at_10[0x10]; 4456 4457 u8 reserved_at_20[0x10]; 4458 u8 op_mod[0x10]; 4459 4460 u8 other_vport[0x1]; 4461 u8 reserved_at_41[0xf]; 4462 u8 vport_number[0x10]; 4463 4464 u8 reserved_at_60[0x20]; 4465 }; 4466 4467 struct mlx5_ifc_query_vport_counter_out_bits { 4468 u8 status[0x8]; 4469 u8 reserved_at_8[0x18]; 4470 4471 u8 syndrome[0x20]; 4472 4473 u8 reserved_at_40[0x40]; 4474 4475 struct mlx5_ifc_traffic_counter_bits received_errors; 4476 4477 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4478 4479 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4480 4481 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4482 4483 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4484 4485 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4486 4487 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4488 4489 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4490 4491 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4492 4493 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4494 4495 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4496 4497 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4498 4499 u8 reserved_at_680[0xa00]; 4500 }; 4501 4502 enum { 4503 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4504 }; 4505 4506 struct mlx5_ifc_query_vport_counter_in_bits { 4507 u8 opcode[0x10]; 4508 u8 reserved_at_10[0x10]; 4509 4510 u8 reserved_at_20[0x10]; 4511 u8 op_mod[0x10]; 4512 4513 u8 other_vport[0x1]; 4514 u8 reserved_at_41[0xb]; 4515 u8 port_num[0x4]; 4516 u8 vport_number[0x10]; 4517 4518 u8 reserved_at_60[0x60]; 4519 4520 u8 clear[0x1]; 4521 u8 reserved_at_c1[0x1f]; 4522 4523 u8 reserved_at_e0[0x20]; 4524 }; 4525 4526 struct mlx5_ifc_query_tis_out_bits { 4527 u8 status[0x8]; 4528 u8 reserved_at_8[0x18]; 4529 4530 u8 syndrome[0x20]; 4531 4532 u8 reserved_at_40[0x40]; 4533 4534 struct mlx5_ifc_tisc_bits tis_context; 4535 }; 4536 4537 struct mlx5_ifc_query_tis_in_bits { 4538 u8 opcode[0x10]; 4539 u8 reserved_at_10[0x10]; 4540 4541 u8 reserved_at_20[0x10]; 4542 u8 op_mod[0x10]; 4543 4544 u8 reserved_at_40[0x8]; 4545 u8 tisn[0x18]; 4546 4547 u8 reserved_at_60[0x20]; 4548 }; 4549 4550 struct mlx5_ifc_query_tir_out_bits { 4551 u8 status[0x8]; 4552 u8 reserved_at_8[0x18]; 4553 4554 u8 syndrome[0x20]; 4555 4556 u8 reserved_at_40[0xc0]; 4557 4558 struct mlx5_ifc_tirc_bits tir_context; 4559 }; 4560 4561 struct mlx5_ifc_query_tir_in_bits { 4562 u8 opcode[0x10]; 4563 u8 reserved_at_10[0x10]; 4564 4565 u8 reserved_at_20[0x10]; 4566 u8 op_mod[0x10]; 4567 4568 u8 reserved_at_40[0x8]; 4569 u8 tirn[0x18]; 4570 4571 u8 reserved_at_60[0x20]; 4572 }; 4573 4574 struct mlx5_ifc_query_srq_out_bits { 4575 u8 status[0x8]; 4576 u8 reserved_at_8[0x18]; 4577 4578 u8 syndrome[0x20]; 4579 4580 u8 reserved_at_40[0x40]; 4581 4582 struct mlx5_ifc_srqc_bits srq_context_entry; 4583 4584 u8 reserved_at_280[0x600]; 4585 4586 u8 pas[0][0x40]; 4587 }; 4588 4589 struct mlx5_ifc_query_srq_in_bits { 4590 u8 opcode[0x10]; 4591 u8 reserved_at_10[0x10]; 4592 4593 u8 reserved_at_20[0x10]; 4594 u8 op_mod[0x10]; 4595 4596 u8 reserved_at_40[0x8]; 4597 u8 srqn[0x18]; 4598 4599 u8 reserved_at_60[0x20]; 4600 }; 4601 4602 struct mlx5_ifc_query_sq_out_bits { 4603 u8 status[0x8]; 4604 u8 reserved_at_8[0x18]; 4605 4606 u8 syndrome[0x20]; 4607 4608 u8 reserved_at_40[0xc0]; 4609 4610 struct mlx5_ifc_sqc_bits sq_context; 4611 }; 4612 4613 struct mlx5_ifc_query_sq_in_bits { 4614 u8 opcode[0x10]; 4615 u8 reserved_at_10[0x10]; 4616 4617 u8 reserved_at_20[0x10]; 4618 u8 op_mod[0x10]; 4619 4620 u8 reserved_at_40[0x8]; 4621 u8 sqn[0x18]; 4622 4623 u8 reserved_at_60[0x20]; 4624 }; 4625 4626 struct mlx5_ifc_query_special_contexts_out_bits { 4627 u8 status[0x8]; 4628 u8 reserved_at_8[0x18]; 4629 4630 u8 syndrome[0x20]; 4631 4632 u8 dump_fill_mkey[0x20]; 4633 4634 u8 resd_lkey[0x20]; 4635 4636 u8 null_mkey[0x20]; 4637 4638 u8 reserved_at_a0[0x60]; 4639 }; 4640 4641 struct mlx5_ifc_query_special_contexts_in_bits { 4642 u8 opcode[0x10]; 4643 u8 reserved_at_10[0x10]; 4644 4645 u8 reserved_at_20[0x10]; 4646 u8 op_mod[0x10]; 4647 4648 u8 reserved_at_40[0x40]; 4649 }; 4650 4651 struct mlx5_ifc_query_scheduling_element_out_bits { 4652 u8 opcode[0x10]; 4653 u8 reserved_at_10[0x10]; 4654 4655 u8 reserved_at_20[0x10]; 4656 u8 op_mod[0x10]; 4657 4658 u8 reserved_at_40[0xc0]; 4659 4660 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4661 4662 u8 reserved_at_300[0x100]; 4663 }; 4664 4665 enum { 4666 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4667 }; 4668 4669 struct mlx5_ifc_query_scheduling_element_in_bits { 4670 u8 opcode[0x10]; 4671 u8 reserved_at_10[0x10]; 4672 4673 u8 reserved_at_20[0x10]; 4674 u8 op_mod[0x10]; 4675 4676 u8 scheduling_hierarchy[0x8]; 4677 u8 reserved_at_48[0x18]; 4678 4679 u8 scheduling_element_id[0x20]; 4680 4681 u8 reserved_at_80[0x180]; 4682 }; 4683 4684 struct mlx5_ifc_query_rqt_out_bits { 4685 u8 status[0x8]; 4686 u8 reserved_at_8[0x18]; 4687 4688 u8 syndrome[0x20]; 4689 4690 u8 reserved_at_40[0xc0]; 4691 4692 struct mlx5_ifc_rqtc_bits rqt_context; 4693 }; 4694 4695 struct mlx5_ifc_query_rqt_in_bits { 4696 u8 opcode[0x10]; 4697 u8 reserved_at_10[0x10]; 4698 4699 u8 reserved_at_20[0x10]; 4700 u8 op_mod[0x10]; 4701 4702 u8 reserved_at_40[0x8]; 4703 u8 rqtn[0x18]; 4704 4705 u8 reserved_at_60[0x20]; 4706 }; 4707 4708 struct mlx5_ifc_query_rq_out_bits { 4709 u8 status[0x8]; 4710 u8 reserved_at_8[0x18]; 4711 4712 u8 syndrome[0x20]; 4713 4714 u8 reserved_at_40[0xc0]; 4715 4716 struct mlx5_ifc_rqc_bits rq_context; 4717 }; 4718 4719 struct mlx5_ifc_query_rq_in_bits { 4720 u8 opcode[0x10]; 4721 u8 reserved_at_10[0x10]; 4722 4723 u8 reserved_at_20[0x10]; 4724 u8 op_mod[0x10]; 4725 4726 u8 reserved_at_40[0x8]; 4727 u8 rqn[0x18]; 4728 4729 u8 reserved_at_60[0x20]; 4730 }; 4731 4732 struct mlx5_ifc_query_roce_address_out_bits { 4733 u8 status[0x8]; 4734 u8 reserved_at_8[0x18]; 4735 4736 u8 syndrome[0x20]; 4737 4738 u8 reserved_at_40[0x40]; 4739 4740 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4741 }; 4742 4743 struct mlx5_ifc_query_roce_address_in_bits { 4744 u8 opcode[0x10]; 4745 u8 reserved_at_10[0x10]; 4746 4747 u8 reserved_at_20[0x10]; 4748 u8 op_mod[0x10]; 4749 4750 u8 roce_address_index[0x10]; 4751 u8 reserved_at_50[0xc]; 4752 u8 vhca_port_num[0x4]; 4753 4754 u8 reserved_at_60[0x20]; 4755 }; 4756 4757 struct mlx5_ifc_query_rmp_out_bits { 4758 u8 status[0x8]; 4759 u8 reserved_at_8[0x18]; 4760 4761 u8 syndrome[0x20]; 4762 4763 u8 reserved_at_40[0xc0]; 4764 4765 struct mlx5_ifc_rmpc_bits rmp_context; 4766 }; 4767 4768 struct mlx5_ifc_query_rmp_in_bits { 4769 u8 opcode[0x10]; 4770 u8 reserved_at_10[0x10]; 4771 4772 u8 reserved_at_20[0x10]; 4773 u8 op_mod[0x10]; 4774 4775 u8 reserved_at_40[0x8]; 4776 u8 rmpn[0x18]; 4777 4778 u8 reserved_at_60[0x20]; 4779 }; 4780 4781 struct mlx5_ifc_query_qp_out_bits { 4782 u8 status[0x8]; 4783 u8 reserved_at_8[0x18]; 4784 4785 u8 syndrome[0x20]; 4786 4787 u8 reserved_at_40[0x40]; 4788 4789 u8 opt_param_mask[0x20]; 4790 4791 u8 reserved_at_a0[0x20]; 4792 4793 struct mlx5_ifc_qpc_bits qpc; 4794 4795 u8 reserved_at_800[0x80]; 4796 4797 u8 pas[0][0x40]; 4798 }; 4799 4800 struct mlx5_ifc_query_qp_in_bits { 4801 u8 opcode[0x10]; 4802 u8 reserved_at_10[0x10]; 4803 4804 u8 reserved_at_20[0x10]; 4805 u8 op_mod[0x10]; 4806 4807 u8 reserved_at_40[0x8]; 4808 u8 qpn[0x18]; 4809 4810 u8 reserved_at_60[0x20]; 4811 }; 4812 4813 struct mlx5_ifc_query_q_counter_out_bits { 4814 u8 status[0x8]; 4815 u8 reserved_at_8[0x18]; 4816 4817 u8 syndrome[0x20]; 4818 4819 u8 reserved_at_40[0x40]; 4820 4821 u8 rx_write_requests[0x20]; 4822 4823 u8 reserved_at_a0[0x20]; 4824 4825 u8 rx_read_requests[0x20]; 4826 4827 u8 reserved_at_e0[0x20]; 4828 4829 u8 rx_atomic_requests[0x20]; 4830 4831 u8 reserved_at_120[0x20]; 4832 4833 u8 rx_dct_connect[0x20]; 4834 4835 u8 reserved_at_160[0x20]; 4836 4837 u8 out_of_buffer[0x20]; 4838 4839 u8 reserved_at_1a0[0x20]; 4840 4841 u8 out_of_sequence[0x20]; 4842 4843 u8 reserved_at_1e0[0x20]; 4844 4845 u8 duplicate_request[0x20]; 4846 4847 u8 reserved_at_220[0x20]; 4848 4849 u8 rnr_nak_retry_err[0x20]; 4850 4851 u8 reserved_at_260[0x20]; 4852 4853 u8 packet_seq_err[0x20]; 4854 4855 u8 reserved_at_2a0[0x20]; 4856 4857 u8 implied_nak_seq_err[0x20]; 4858 4859 u8 reserved_at_2e0[0x20]; 4860 4861 u8 local_ack_timeout_err[0x20]; 4862 4863 u8 reserved_at_320[0xa0]; 4864 4865 u8 resp_local_length_error[0x20]; 4866 4867 u8 req_local_length_error[0x20]; 4868 4869 u8 resp_local_qp_error[0x20]; 4870 4871 u8 local_operation_error[0x20]; 4872 4873 u8 resp_local_protection[0x20]; 4874 4875 u8 req_local_protection[0x20]; 4876 4877 u8 resp_cqe_error[0x20]; 4878 4879 u8 req_cqe_error[0x20]; 4880 4881 u8 req_mw_binding[0x20]; 4882 4883 u8 req_bad_response[0x20]; 4884 4885 u8 req_remote_invalid_request[0x20]; 4886 4887 u8 resp_remote_invalid_request[0x20]; 4888 4889 u8 req_remote_access_errors[0x20]; 4890 4891 u8 resp_remote_access_errors[0x20]; 4892 4893 u8 req_remote_operation_errors[0x20]; 4894 4895 u8 req_transport_retries_exceeded[0x20]; 4896 4897 u8 cq_overflow[0x20]; 4898 4899 u8 resp_cqe_flush_error[0x20]; 4900 4901 u8 req_cqe_flush_error[0x20]; 4902 4903 u8 reserved_at_620[0x20]; 4904 4905 u8 roce_adp_retrans[0x20]; 4906 4907 u8 roce_adp_retrans_to[0x20]; 4908 4909 u8 roce_slow_restart[0x20]; 4910 4911 u8 roce_slow_restart_cnps[0x20]; 4912 4913 u8 roce_slow_restart_trans[0x20]; 4914 4915 u8 reserved_at_6e0[0x120]; 4916 }; 4917 4918 struct mlx5_ifc_query_q_counter_in_bits { 4919 u8 opcode[0x10]; 4920 u8 reserved_at_10[0x10]; 4921 4922 u8 reserved_at_20[0x10]; 4923 u8 op_mod[0x10]; 4924 4925 u8 reserved_at_40[0x80]; 4926 4927 u8 clear[0x1]; 4928 u8 reserved_at_c1[0x1f]; 4929 4930 u8 reserved_at_e0[0x18]; 4931 u8 counter_set_id[0x8]; 4932 }; 4933 4934 struct mlx5_ifc_query_pages_out_bits { 4935 u8 status[0x8]; 4936 u8 reserved_at_8[0x18]; 4937 4938 u8 syndrome[0x20]; 4939 4940 u8 embedded_cpu_function[0x1]; 4941 u8 reserved_at_41[0xf]; 4942 u8 function_id[0x10]; 4943 4944 u8 num_pages[0x20]; 4945 }; 4946 4947 enum { 4948 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4949 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4950 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4951 }; 4952 4953 struct mlx5_ifc_query_pages_in_bits { 4954 u8 opcode[0x10]; 4955 u8 reserved_at_10[0x10]; 4956 4957 u8 reserved_at_20[0x10]; 4958 u8 op_mod[0x10]; 4959 4960 u8 embedded_cpu_function[0x1]; 4961 u8 reserved_at_41[0xf]; 4962 u8 function_id[0x10]; 4963 4964 u8 reserved_at_60[0x20]; 4965 }; 4966 4967 struct mlx5_ifc_query_nic_vport_context_out_bits { 4968 u8 status[0x8]; 4969 u8 reserved_at_8[0x18]; 4970 4971 u8 syndrome[0x20]; 4972 4973 u8 reserved_at_40[0x40]; 4974 4975 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4976 }; 4977 4978 struct mlx5_ifc_query_nic_vport_context_in_bits { 4979 u8 opcode[0x10]; 4980 u8 reserved_at_10[0x10]; 4981 4982 u8 reserved_at_20[0x10]; 4983 u8 op_mod[0x10]; 4984 4985 u8 other_vport[0x1]; 4986 u8 reserved_at_41[0xf]; 4987 u8 vport_number[0x10]; 4988 4989 u8 reserved_at_60[0x5]; 4990 u8 allowed_list_type[0x3]; 4991 u8 reserved_at_68[0x18]; 4992 }; 4993 4994 struct mlx5_ifc_query_mkey_out_bits { 4995 u8 status[0x8]; 4996 u8 reserved_at_8[0x18]; 4997 4998 u8 syndrome[0x20]; 4999 5000 u8 reserved_at_40[0x40]; 5001 5002 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5003 5004 u8 reserved_at_280[0x600]; 5005 5006 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5007 5008 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5009 }; 5010 5011 struct mlx5_ifc_query_mkey_in_bits { 5012 u8 opcode[0x10]; 5013 u8 reserved_at_10[0x10]; 5014 5015 u8 reserved_at_20[0x10]; 5016 u8 op_mod[0x10]; 5017 5018 u8 reserved_at_40[0x8]; 5019 u8 mkey_index[0x18]; 5020 5021 u8 pg_access[0x1]; 5022 u8 reserved_at_61[0x1f]; 5023 }; 5024 5025 struct mlx5_ifc_query_mad_demux_out_bits { 5026 u8 status[0x8]; 5027 u8 reserved_at_8[0x18]; 5028 5029 u8 syndrome[0x20]; 5030 5031 u8 reserved_at_40[0x40]; 5032 5033 u8 mad_dumux_parameters_block[0x20]; 5034 }; 5035 5036 struct mlx5_ifc_query_mad_demux_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_at_10[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 reserved_at_40[0x40]; 5044 }; 5045 5046 struct mlx5_ifc_query_l2_table_entry_out_bits { 5047 u8 status[0x8]; 5048 u8 reserved_at_8[0x18]; 5049 5050 u8 syndrome[0x20]; 5051 5052 u8 reserved_at_40[0xa0]; 5053 5054 u8 reserved_at_e0[0x13]; 5055 u8 vlan_valid[0x1]; 5056 u8 vlan[0xc]; 5057 5058 struct mlx5_ifc_mac_address_layout_bits mac_address; 5059 5060 u8 reserved_at_140[0xc0]; 5061 }; 5062 5063 struct mlx5_ifc_query_l2_table_entry_in_bits { 5064 u8 opcode[0x10]; 5065 u8 reserved_at_10[0x10]; 5066 5067 u8 reserved_at_20[0x10]; 5068 u8 op_mod[0x10]; 5069 5070 u8 reserved_at_40[0x60]; 5071 5072 u8 reserved_at_a0[0x8]; 5073 u8 table_index[0x18]; 5074 5075 u8 reserved_at_c0[0x140]; 5076 }; 5077 5078 struct mlx5_ifc_query_issi_out_bits { 5079 u8 status[0x8]; 5080 u8 reserved_at_8[0x18]; 5081 5082 u8 syndrome[0x20]; 5083 5084 u8 reserved_at_40[0x10]; 5085 u8 current_issi[0x10]; 5086 5087 u8 reserved_at_60[0xa0]; 5088 5089 u8 reserved_at_100[76][0x8]; 5090 u8 supported_issi_dw0[0x20]; 5091 }; 5092 5093 struct mlx5_ifc_query_issi_in_bits { 5094 u8 opcode[0x10]; 5095 u8 reserved_at_10[0x10]; 5096 5097 u8 reserved_at_20[0x10]; 5098 u8 op_mod[0x10]; 5099 5100 u8 reserved_at_40[0x40]; 5101 }; 5102 5103 struct mlx5_ifc_set_driver_version_out_bits { 5104 u8 status[0x8]; 5105 u8 reserved_0[0x18]; 5106 5107 u8 syndrome[0x20]; 5108 u8 reserved_1[0x40]; 5109 }; 5110 5111 struct mlx5_ifc_set_driver_version_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_0[0x10]; 5114 5115 u8 reserved_1[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_2[0x40]; 5119 u8 driver_version[64][0x8]; 5120 }; 5121 5122 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5123 u8 status[0x8]; 5124 u8 reserved_at_8[0x18]; 5125 5126 u8 syndrome[0x20]; 5127 5128 u8 reserved_at_40[0x40]; 5129 5130 struct mlx5_ifc_pkey_bits pkey[0]; 5131 }; 5132 5133 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5134 u8 opcode[0x10]; 5135 u8 reserved_at_10[0x10]; 5136 5137 u8 reserved_at_20[0x10]; 5138 u8 op_mod[0x10]; 5139 5140 u8 other_vport[0x1]; 5141 u8 reserved_at_41[0xb]; 5142 u8 port_num[0x4]; 5143 u8 vport_number[0x10]; 5144 5145 u8 reserved_at_60[0x10]; 5146 u8 pkey_index[0x10]; 5147 }; 5148 5149 enum { 5150 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5151 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5152 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5153 }; 5154 5155 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5156 u8 status[0x8]; 5157 u8 reserved_at_8[0x18]; 5158 5159 u8 syndrome[0x20]; 5160 5161 u8 reserved_at_40[0x20]; 5162 5163 u8 gids_num[0x10]; 5164 u8 reserved_at_70[0x10]; 5165 5166 struct mlx5_ifc_array128_auto_bits gid[0]; 5167 }; 5168 5169 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5170 u8 opcode[0x10]; 5171 u8 reserved_at_10[0x10]; 5172 5173 u8 reserved_at_20[0x10]; 5174 u8 op_mod[0x10]; 5175 5176 u8 other_vport[0x1]; 5177 u8 reserved_at_41[0xb]; 5178 u8 port_num[0x4]; 5179 u8 vport_number[0x10]; 5180 5181 u8 reserved_at_60[0x10]; 5182 u8 gid_index[0x10]; 5183 }; 5184 5185 struct mlx5_ifc_query_hca_vport_context_out_bits { 5186 u8 status[0x8]; 5187 u8 reserved_at_8[0x18]; 5188 5189 u8 syndrome[0x20]; 5190 5191 u8 reserved_at_40[0x40]; 5192 5193 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5194 }; 5195 5196 struct mlx5_ifc_query_hca_vport_context_in_bits { 5197 u8 opcode[0x10]; 5198 u8 reserved_at_10[0x10]; 5199 5200 u8 reserved_at_20[0x10]; 5201 u8 op_mod[0x10]; 5202 5203 u8 other_vport[0x1]; 5204 u8 reserved_at_41[0xb]; 5205 u8 port_num[0x4]; 5206 u8 vport_number[0x10]; 5207 5208 u8 reserved_at_60[0x20]; 5209 }; 5210 5211 struct mlx5_ifc_query_hca_cap_out_bits { 5212 u8 status[0x8]; 5213 u8 reserved_at_8[0x18]; 5214 5215 u8 syndrome[0x20]; 5216 5217 u8 reserved_at_40[0x40]; 5218 5219 union mlx5_ifc_hca_cap_union_bits capability; 5220 }; 5221 5222 struct mlx5_ifc_query_hca_cap_in_bits { 5223 u8 opcode[0x10]; 5224 u8 reserved_at_10[0x10]; 5225 5226 u8 reserved_at_20[0x10]; 5227 u8 op_mod[0x10]; 5228 5229 u8 other_function[0x1]; 5230 u8 reserved_at_41[0xf]; 5231 u8 function_id[0x10]; 5232 5233 u8 reserved_at_60[0x20]; 5234 }; 5235 5236 struct mlx5_ifc_other_hca_cap_bits { 5237 u8 roce[0x1]; 5238 u8 reserved_at_1[0x27f]; 5239 }; 5240 5241 struct mlx5_ifc_query_other_hca_cap_out_bits { 5242 u8 status[0x8]; 5243 u8 reserved_at_8[0x18]; 5244 5245 u8 syndrome[0x20]; 5246 5247 u8 reserved_at_40[0x40]; 5248 5249 struct mlx5_ifc_other_hca_cap_bits other_capability; 5250 }; 5251 5252 struct mlx5_ifc_query_other_hca_cap_in_bits { 5253 u8 opcode[0x10]; 5254 u8 reserved_at_10[0x10]; 5255 5256 u8 reserved_at_20[0x10]; 5257 u8 op_mod[0x10]; 5258 5259 u8 reserved_at_40[0x10]; 5260 u8 function_id[0x10]; 5261 5262 u8 reserved_at_60[0x20]; 5263 }; 5264 5265 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5266 u8 status[0x8]; 5267 u8 reserved_at_8[0x18]; 5268 5269 u8 syndrome[0x20]; 5270 5271 u8 reserved_at_40[0x40]; 5272 }; 5273 5274 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5275 u8 opcode[0x10]; 5276 u8 reserved_at_10[0x10]; 5277 5278 u8 reserved_at_20[0x10]; 5279 u8 op_mod[0x10]; 5280 5281 u8 reserved_at_40[0x10]; 5282 u8 function_id[0x10]; 5283 u8 field_select[0x20]; 5284 5285 struct mlx5_ifc_other_hca_cap_bits other_capability; 5286 }; 5287 5288 struct mlx5_ifc_flow_table_context_bits { 5289 u8 reformat_en[0x1]; 5290 u8 decap_en[0x1]; 5291 u8 sw_owner[0x1]; 5292 u8 termination_table[0x1]; 5293 u8 table_miss_action[0x4]; 5294 u8 level[0x8]; 5295 u8 reserved_at_10[0x8]; 5296 u8 log_size[0x8]; 5297 5298 u8 reserved_at_20[0x8]; 5299 u8 table_miss_id[0x18]; 5300 5301 u8 reserved_at_40[0x8]; 5302 u8 lag_master_next_table_id[0x18]; 5303 5304 u8 reserved_at_60[0x60]; 5305 5306 u8 sw_owner_icm_root_1[0x40]; 5307 5308 u8 sw_owner_icm_root_0[0x40]; 5309 5310 }; 5311 5312 struct mlx5_ifc_query_flow_table_out_bits { 5313 u8 status[0x8]; 5314 u8 reserved_at_8[0x18]; 5315 5316 u8 syndrome[0x20]; 5317 5318 u8 reserved_at_40[0x80]; 5319 5320 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5321 }; 5322 5323 struct mlx5_ifc_query_flow_table_in_bits { 5324 u8 opcode[0x10]; 5325 u8 reserved_at_10[0x10]; 5326 5327 u8 reserved_at_20[0x10]; 5328 u8 op_mod[0x10]; 5329 5330 u8 reserved_at_40[0x40]; 5331 5332 u8 table_type[0x8]; 5333 u8 reserved_at_88[0x18]; 5334 5335 u8 reserved_at_a0[0x8]; 5336 u8 table_id[0x18]; 5337 5338 u8 reserved_at_c0[0x140]; 5339 }; 5340 5341 struct mlx5_ifc_query_fte_out_bits { 5342 u8 status[0x8]; 5343 u8 reserved_at_8[0x18]; 5344 5345 u8 syndrome[0x20]; 5346 5347 u8 reserved_at_40[0x1c0]; 5348 5349 struct mlx5_ifc_flow_context_bits flow_context; 5350 }; 5351 5352 struct mlx5_ifc_query_fte_in_bits { 5353 u8 opcode[0x10]; 5354 u8 reserved_at_10[0x10]; 5355 5356 u8 reserved_at_20[0x10]; 5357 u8 op_mod[0x10]; 5358 5359 u8 reserved_at_40[0x40]; 5360 5361 u8 table_type[0x8]; 5362 u8 reserved_at_88[0x18]; 5363 5364 u8 reserved_at_a0[0x8]; 5365 u8 table_id[0x18]; 5366 5367 u8 reserved_at_c0[0x40]; 5368 5369 u8 flow_index[0x20]; 5370 5371 u8 reserved_at_120[0xe0]; 5372 }; 5373 5374 enum { 5375 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5376 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5377 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5378 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5379 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5380 }; 5381 5382 struct mlx5_ifc_query_flow_group_out_bits { 5383 u8 status[0x8]; 5384 u8 reserved_at_8[0x18]; 5385 5386 u8 syndrome[0x20]; 5387 5388 u8 reserved_at_40[0xa0]; 5389 5390 u8 start_flow_index[0x20]; 5391 5392 u8 reserved_at_100[0x20]; 5393 5394 u8 end_flow_index[0x20]; 5395 5396 u8 reserved_at_140[0xa0]; 5397 5398 u8 reserved_at_1e0[0x18]; 5399 u8 match_criteria_enable[0x8]; 5400 5401 struct mlx5_ifc_fte_match_param_bits match_criteria; 5402 5403 u8 reserved_at_1200[0xe00]; 5404 }; 5405 5406 struct mlx5_ifc_query_flow_group_in_bits { 5407 u8 opcode[0x10]; 5408 u8 reserved_at_10[0x10]; 5409 5410 u8 reserved_at_20[0x10]; 5411 u8 op_mod[0x10]; 5412 5413 u8 reserved_at_40[0x40]; 5414 5415 u8 table_type[0x8]; 5416 u8 reserved_at_88[0x18]; 5417 5418 u8 reserved_at_a0[0x8]; 5419 u8 table_id[0x18]; 5420 5421 u8 group_id[0x20]; 5422 5423 u8 reserved_at_e0[0x120]; 5424 }; 5425 5426 struct mlx5_ifc_query_flow_counter_out_bits { 5427 u8 status[0x8]; 5428 u8 reserved_at_8[0x18]; 5429 5430 u8 syndrome[0x20]; 5431 5432 u8 reserved_at_40[0x40]; 5433 5434 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5435 }; 5436 5437 struct mlx5_ifc_query_flow_counter_in_bits { 5438 u8 opcode[0x10]; 5439 u8 reserved_at_10[0x10]; 5440 5441 u8 reserved_at_20[0x10]; 5442 u8 op_mod[0x10]; 5443 5444 u8 reserved_at_40[0x80]; 5445 5446 u8 clear[0x1]; 5447 u8 reserved_at_c1[0xf]; 5448 u8 num_of_counters[0x10]; 5449 5450 u8 flow_counter_id[0x20]; 5451 }; 5452 5453 struct mlx5_ifc_query_esw_vport_context_out_bits { 5454 u8 status[0x8]; 5455 u8 reserved_at_8[0x18]; 5456 5457 u8 syndrome[0x20]; 5458 5459 u8 reserved_at_40[0x40]; 5460 5461 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5462 }; 5463 5464 struct mlx5_ifc_query_esw_vport_context_in_bits { 5465 u8 opcode[0x10]; 5466 u8 reserved_at_10[0x10]; 5467 5468 u8 reserved_at_20[0x10]; 5469 u8 op_mod[0x10]; 5470 5471 u8 other_vport[0x1]; 5472 u8 reserved_at_41[0xf]; 5473 u8 vport_number[0x10]; 5474 5475 u8 reserved_at_60[0x20]; 5476 }; 5477 5478 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5479 u8 status[0x8]; 5480 u8 reserved_at_8[0x18]; 5481 5482 u8 syndrome[0x20]; 5483 5484 u8 reserved_at_40[0x40]; 5485 }; 5486 5487 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5488 u8 reserved_at_0[0x1b]; 5489 u8 fdb_to_vport_reg_c_id[0x1]; 5490 u8 vport_cvlan_insert[0x1]; 5491 u8 vport_svlan_insert[0x1]; 5492 u8 vport_cvlan_strip[0x1]; 5493 u8 vport_svlan_strip[0x1]; 5494 }; 5495 5496 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5497 u8 opcode[0x10]; 5498 u8 reserved_at_10[0x10]; 5499 5500 u8 reserved_at_20[0x10]; 5501 u8 op_mod[0x10]; 5502 5503 u8 other_vport[0x1]; 5504 u8 reserved_at_41[0xf]; 5505 u8 vport_number[0x10]; 5506 5507 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5508 5509 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5510 }; 5511 5512 struct mlx5_ifc_query_eq_out_bits { 5513 u8 status[0x8]; 5514 u8 reserved_at_8[0x18]; 5515 5516 u8 syndrome[0x20]; 5517 5518 u8 reserved_at_40[0x40]; 5519 5520 struct mlx5_ifc_eqc_bits eq_context_entry; 5521 5522 u8 reserved_at_280[0x40]; 5523 5524 u8 event_bitmask[0x40]; 5525 5526 u8 reserved_at_300[0x580]; 5527 5528 u8 pas[0][0x40]; 5529 }; 5530 5531 struct mlx5_ifc_query_eq_in_bits { 5532 u8 opcode[0x10]; 5533 u8 reserved_at_10[0x10]; 5534 5535 u8 reserved_at_20[0x10]; 5536 u8 op_mod[0x10]; 5537 5538 u8 reserved_at_40[0x18]; 5539 u8 eq_number[0x8]; 5540 5541 u8 reserved_at_60[0x20]; 5542 }; 5543 5544 struct mlx5_ifc_packet_reformat_context_in_bits { 5545 u8 reserved_at_0[0x5]; 5546 u8 reformat_type[0x3]; 5547 u8 reserved_at_8[0xe]; 5548 u8 reformat_data_size[0xa]; 5549 5550 u8 reserved_at_20[0x10]; 5551 u8 reformat_data[2][0x8]; 5552 5553 u8 more_reformat_data[0][0x8]; 5554 }; 5555 5556 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5557 u8 status[0x8]; 5558 u8 reserved_at_8[0x18]; 5559 5560 u8 syndrome[0x20]; 5561 5562 u8 reserved_at_40[0xa0]; 5563 5564 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5565 }; 5566 5567 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5568 u8 opcode[0x10]; 5569 u8 reserved_at_10[0x10]; 5570 5571 u8 reserved_at_20[0x10]; 5572 u8 op_mod[0x10]; 5573 5574 u8 packet_reformat_id[0x20]; 5575 5576 u8 reserved_at_60[0xa0]; 5577 }; 5578 5579 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5580 u8 status[0x8]; 5581 u8 reserved_at_8[0x18]; 5582 5583 u8 syndrome[0x20]; 5584 5585 u8 packet_reformat_id[0x20]; 5586 5587 u8 reserved_at_60[0x20]; 5588 }; 5589 5590 enum mlx5_reformat_ctx_type { 5591 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5592 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5593 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5594 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5595 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5596 }; 5597 5598 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5599 u8 opcode[0x10]; 5600 u8 reserved_at_10[0x10]; 5601 5602 u8 reserved_at_20[0x10]; 5603 u8 op_mod[0x10]; 5604 5605 u8 reserved_at_40[0xa0]; 5606 5607 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5608 }; 5609 5610 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5611 u8 status[0x8]; 5612 u8 reserved_at_8[0x18]; 5613 5614 u8 syndrome[0x20]; 5615 5616 u8 reserved_at_40[0x40]; 5617 }; 5618 5619 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5620 u8 opcode[0x10]; 5621 u8 reserved_at_10[0x10]; 5622 5623 u8 reserved_20[0x10]; 5624 u8 op_mod[0x10]; 5625 5626 u8 packet_reformat_id[0x20]; 5627 5628 u8 reserved_60[0x20]; 5629 }; 5630 5631 struct mlx5_ifc_set_action_in_bits { 5632 u8 action_type[0x4]; 5633 u8 field[0xc]; 5634 u8 reserved_at_10[0x3]; 5635 u8 offset[0x5]; 5636 u8 reserved_at_18[0x3]; 5637 u8 length[0x5]; 5638 5639 u8 data[0x20]; 5640 }; 5641 5642 struct mlx5_ifc_add_action_in_bits { 5643 u8 action_type[0x4]; 5644 u8 field[0xc]; 5645 u8 reserved_at_10[0x10]; 5646 5647 u8 data[0x20]; 5648 }; 5649 5650 struct mlx5_ifc_copy_action_in_bits { 5651 u8 action_type[0x4]; 5652 u8 src_field[0xc]; 5653 u8 reserved_at_10[0x3]; 5654 u8 src_offset[0x5]; 5655 u8 reserved_at_18[0x3]; 5656 u8 length[0x5]; 5657 5658 u8 reserved_at_20[0x4]; 5659 u8 dst_field[0xc]; 5660 u8 reserved_at_30[0x3]; 5661 u8 dst_offset[0x5]; 5662 u8 reserved_at_38[0x8]; 5663 }; 5664 5665 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5666 struct mlx5_ifc_set_action_in_bits set_action_in; 5667 struct mlx5_ifc_add_action_in_bits add_action_in; 5668 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5669 u8 reserved_at_0[0x40]; 5670 }; 5671 5672 enum { 5673 MLX5_ACTION_TYPE_SET = 0x1, 5674 MLX5_ACTION_TYPE_ADD = 0x2, 5675 MLX5_ACTION_TYPE_COPY = 0x3, 5676 }; 5677 5678 enum { 5679 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5680 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5681 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5682 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5683 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5684 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5685 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5686 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5687 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5688 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5689 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5690 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5691 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5692 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5693 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5694 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5695 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5696 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5697 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5698 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5699 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5700 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5701 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5702 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5703 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5704 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5705 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5706 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5707 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5708 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5709 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5710 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5711 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5712 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5713 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5714 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5715 }; 5716 5717 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5718 u8 status[0x8]; 5719 u8 reserved_at_8[0x18]; 5720 5721 u8 syndrome[0x20]; 5722 5723 u8 modify_header_id[0x20]; 5724 5725 u8 reserved_at_60[0x20]; 5726 }; 5727 5728 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5729 u8 opcode[0x10]; 5730 u8 reserved_at_10[0x10]; 5731 5732 u8 reserved_at_20[0x10]; 5733 u8 op_mod[0x10]; 5734 5735 u8 reserved_at_40[0x20]; 5736 5737 u8 table_type[0x8]; 5738 u8 reserved_at_68[0x10]; 5739 u8 num_of_actions[0x8]; 5740 5741 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5742 }; 5743 5744 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_at_8[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_at_40[0x40]; 5751 }; 5752 5753 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5754 u8 opcode[0x10]; 5755 u8 reserved_at_10[0x10]; 5756 5757 u8 reserved_at_20[0x10]; 5758 u8 op_mod[0x10]; 5759 5760 u8 modify_header_id[0x20]; 5761 5762 u8 reserved_at_60[0x20]; 5763 }; 5764 5765 struct mlx5_ifc_query_dct_out_bits { 5766 u8 status[0x8]; 5767 u8 reserved_at_8[0x18]; 5768 5769 u8 syndrome[0x20]; 5770 5771 u8 reserved_at_40[0x40]; 5772 5773 struct mlx5_ifc_dctc_bits dct_context_entry; 5774 5775 u8 reserved_at_280[0x180]; 5776 }; 5777 5778 struct mlx5_ifc_query_dct_in_bits { 5779 u8 opcode[0x10]; 5780 u8 reserved_at_10[0x10]; 5781 5782 u8 reserved_at_20[0x10]; 5783 u8 op_mod[0x10]; 5784 5785 u8 reserved_at_40[0x8]; 5786 u8 dctn[0x18]; 5787 5788 u8 reserved_at_60[0x20]; 5789 }; 5790 5791 struct mlx5_ifc_query_cq_out_bits { 5792 u8 status[0x8]; 5793 u8 reserved_at_8[0x18]; 5794 5795 u8 syndrome[0x20]; 5796 5797 u8 reserved_at_40[0x40]; 5798 5799 struct mlx5_ifc_cqc_bits cq_context; 5800 5801 u8 reserved_at_280[0x600]; 5802 5803 u8 pas[0][0x40]; 5804 }; 5805 5806 struct mlx5_ifc_query_cq_in_bits { 5807 u8 opcode[0x10]; 5808 u8 reserved_at_10[0x10]; 5809 5810 u8 reserved_at_20[0x10]; 5811 u8 op_mod[0x10]; 5812 5813 u8 reserved_at_40[0x8]; 5814 u8 cqn[0x18]; 5815 5816 u8 reserved_at_60[0x20]; 5817 }; 5818 5819 struct mlx5_ifc_query_cong_status_out_bits { 5820 u8 status[0x8]; 5821 u8 reserved_at_8[0x18]; 5822 5823 u8 syndrome[0x20]; 5824 5825 u8 reserved_at_40[0x20]; 5826 5827 u8 enable[0x1]; 5828 u8 tag_enable[0x1]; 5829 u8 reserved_at_62[0x1e]; 5830 }; 5831 5832 struct mlx5_ifc_query_cong_status_in_bits { 5833 u8 opcode[0x10]; 5834 u8 reserved_at_10[0x10]; 5835 5836 u8 reserved_at_20[0x10]; 5837 u8 op_mod[0x10]; 5838 5839 u8 reserved_at_40[0x18]; 5840 u8 priority[0x4]; 5841 u8 cong_protocol[0x4]; 5842 5843 u8 reserved_at_60[0x20]; 5844 }; 5845 5846 struct mlx5_ifc_query_cong_statistics_out_bits { 5847 u8 status[0x8]; 5848 u8 reserved_at_8[0x18]; 5849 5850 u8 syndrome[0x20]; 5851 5852 u8 reserved_at_40[0x40]; 5853 5854 u8 rp_cur_flows[0x20]; 5855 5856 u8 sum_flows[0x20]; 5857 5858 u8 rp_cnp_ignored_high[0x20]; 5859 5860 u8 rp_cnp_ignored_low[0x20]; 5861 5862 u8 rp_cnp_handled_high[0x20]; 5863 5864 u8 rp_cnp_handled_low[0x20]; 5865 5866 u8 reserved_at_140[0x100]; 5867 5868 u8 time_stamp_high[0x20]; 5869 5870 u8 time_stamp_low[0x20]; 5871 5872 u8 accumulators_period[0x20]; 5873 5874 u8 np_ecn_marked_roce_packets_high[0x20]; 5875 5876 u8 np_ecn_marked_roce_packets_low[0x20]; 5877 5878 u8 np_cnp_sent_high[0x20]; 5879 5880 u8 np_cnp_sent_low[0x20]; 5881 5882 u8 reserved_at_320[0x560]; 5883 }; 5884 5885 struct mlx5_ifc_query_cong_statistics_in_bits { 5886 u8 opcode[0x10]; 5887 u8 reserved_at_10[0x10]; 5888 5889 u8 reserved_at_20[0x10]; 5890 u8 op_mod[0x10]; 5891 5892 u8 clear[0x1]; 5893 u8 reserved_at_41[0x1f]; 5894 5895 u8 reserved_at_60[0x20]; 5896 }; 5897 5898 struct mlx5_ifc_query_cong_params_out_bits { 5899 u8 status[0x8]; 5900 u8 reserved_at_8[0x18]; 5901 5902 u8 syndrome[0x20]; 5903 5904 u8 reserved_at_40[0x40]; 5905 5906 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5907 }; 5908 5909 struct mlx5_ifc_query_cong_params_in_bits { 5910 u8 opcode[0x10]; 5911 u8 reserved_at_10[0x10]; 5912 5913 u8 reserved_at_20[0x10]; 5914 u8 op_mod[0x10]; 5915 5916 u8 reserved_at_40[0x1c]; 5917 u8 cong_protocol[0x4]; 5918 5919 u8 reserved_at_60[0x20]; 5920 }; 5921 5922 struct mlx5_ifc_query_adapter_out_bits { 5923 u8 status[0x8]; 5924 u8 reserved_at_8[0x18]; 5925 5926 u8 syndrome[0x20]; 5927 5928 u8 reserved_at_40[0x40]; 5929 5930 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5931 }; 5932 5933 struct mlx5_ifc_query_adapter_in_bits { 5934 u8 opcode[0x10]; 5935 u8 reserved_at_10[0x10]; 5936 5937 u8 reserved_at_20[0x10]; 5938 u8 op_mod[0x10]; 5939 5940 u8 reserved_at_40[0x40]; 5941 }; 5942 5943 struct mlx5_ifc_qp_2rst_out_bits { 5944 u8 status[0x8]; 5945 u8 reserved_at_8[0x18]; 5946 5947 u8 syndrome[0x20]; 5948 5949 u8 reserved_at_40[0x40]; 5950 }; 5951 5952 struct mlx5_ifc_qp_2rst_in_bits { 5953 u8 opcode[0x10]; 5954 u8 uid[0x10]; 5955 5956 u8 reserved_at_20[0x10]; 5957 u8 op_mod[0x10]; 5958 5959 u8 reserved_at_40[0x8]; 5960 u8 qpn[0x18]; 5961 5962 u8 reserved_at_60[0x20]; 5963 }; 5964 5965 struct mlx5_ifc_qp_2err_out_bits { 5966 u8 status[0x8]; 5967 u8 reserved_at_8[0x18]; 5968 5969 u8 syndrome[0x20]; 5970 5971 u8 reserved_at_40[0x40]; 5972 }; 5973 5974 struct mlx5_ifc_qp_2err_in_bits { 5975 u8 opcode[0x10]; 5976 u8 uid[0x10]; 5977 5978 u8 reserved_at_20[0x10]; 5979 u8 op_mod[0x10]; 5980 5981 u8 reserved_at_40[0x8]; 5982 u8 qpn[0x18]; 5983 5984 u8 reserved_at_60[0x20]; 5985 }; 5986 5987 struct mlx5_ifc_page_fault_resume_out_bits { 5988 u8 status[0x8]; 5989 u8 reserved_at_8[0x18]; 5990 5991 u8 syndrome[0x20]; 5992 5993 u8 reserved_at_40[0x40]; 5994 }; 5995 5996 struct mlx5_ifc_page_fault_resume_in_bits { 5997 u8 opcode[0x10]; 5998 u8 reserved_at_10[0x10]; 5999 6000 u8 reserved_at_20[0x10]; 6001 u8 op_mod[0x10]; 6002 6003 u8 error[0x1]; 6004 u8 reserved_at_41[0x4]; 6005 u8 page_fault_type[0x3]; 6006 u8 wq_number[0x18]; 6007 6008 u8 reserved_at_60[0x8]; 6009 u8 token[0x18]; 6010 }; 6011 6012 struct mlx5_ifc_nop_out_bits { 6013 u8 status[0x8]; 6014 u8 reserved_at_8[0x18]; 6015 6016 u8 syndrome[0x20]; 6017 6018 u8 reserved_at_40[0x40]; 6019 }; 6020 6021 struct mlx5_ifc_nop_in_bits { 6022 u8 opcode[0x10]; 6023 u8 reserved_at_10[0x10]; 6024 6025 u8 reserved_at_20[0x10]; 6026 u8 op_mod[0x10]; 6027 6028 u8 reserved_at_40[0x40]; 6029 }; 6030 6031 struct mlx5_ifc_modify_vport_state_out_bits { 6032 u8 status[0x8]; 6033 u8 reserved_at_8[0x18]; 6034 6035 u8 syndrome[0x20]; 6036 6037 u8 reserved_at_40[0x40]; 6038 }; 6039 6040 struct mlx5_ifc_modify_vport_state_in_bits { 6041 u8 opcode[0x10]; 6042 u8 reserved_at_10[0x10]; 6043 6044 u8 reserved_at_20[0x10]; 6045 u8 op_mod[0x10]; 6046 6047 u8 other_vport[0x1]; 6048 u8 reserved_at_41[0xf]; 6049 u8 vport_number[0x10]; 6050 6051 u8 reserved_at_60[0x18]; 6052 u8 admin_state[0x4]; 6053 u8 reserved_at_7c[0x4]; 6054 }; 6055 6056 struct mlx5_ifc_modify_tis_out_bits { 6057 u8 status[0x8]; 6058 u8 reserved_at_8[0x18]; 6059 6060 u8 syndrome[0x20]; 6061 6062 u8 reserved_at_40[0x40]; 6063 }; 6064 6065 struct mlx5_ifc_modify_tis_bitmask_bits { 6066 u8 reserved_at_0[0x20]; 6067 6068 u8 reserved_at_20[0x1d]; 6069 u8 lag_tx_port_affinity[0x1]; 6070 u8 strict_lag_tx_port_affinity[0x1]; 6071 u8 prio[0x1]; 6072 }; 6073 6074 struct mlx5_ifc_modify_tis_in_bits { 6075 u8 opcode[0x10]; 6076 u8 uid[0x10]; 6077 6078 u8 reserved_at_20[0x10]; 6079 u8 op_mod[0x10]; 6080 6081 u8 reserved_at_40[0x8]; 6082 u8 tisn[0x18]; 6083 6084 u8 reserved_at_60[0x20]; 6085 6086 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6087 6088 u8 reserved_at_c0[0x40]; 6089 6090 struct mlx5_ifc_tisc_bits ctx; 6091 }; 6092 6093 struct mlx5_ifc_modify_tir_bitmask_bits { 6094 u8 reserved_at_0[0x20]; 6095 6096 u8 reserved_at_20[0x1b]; 6097 u8 self_lb_en[0x1]; 6098 u8 reserved_at_3c[0x1]; 6099 u8 hash[0x1]; 6100 u8 reserved_at_3e[0x1]; 6101 u8 lro[0x1]; 6102 }; 6103 6104 struct mlx5_ifc_modify_tir_out_bits { 6105 u8 status[0x8]; 6106 u8 reserved_at_8[0x18]; 6107 6108 u8 syndrome[0x20]; 6109 6110 u8 reserved_at_40[0x40]; 6111 }; 6112 6113 struct mlx5_ifc_modify_tir_in_bits { 6114 u8 opcode[0x10]; 6115 u8 uid[0x10]; 6116 6117 u8 reserved_at_20[0x10]; 6118 u8 op_mod[0x10]; 6119 6120 u8 reserved_at_40[0x8]; 6121 u8 tirn[0x18]; 6122 6123 u8 reserved_at_60[0x20]; 6124 6125 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6126 6127 u8 reserved_at_c0[0x40]; 6128 6129 struct mlx5_ifc_tirc_bits ctx; 6130 }; 6131 6132 struct mlx5_ifc_modify_sq_out_bits { 6133 u8 status[0x8]; 6134 u8 reserved_at_8[0x18]; 6135 6136 u8 syndrome[0x20]; 6137 6138 u8 reserved_at_40[0x40]; 6139 }; 6140 6141 struct mlx5_ifc_modify_sq_in_bits { 6142 u8 opcode[0x10]; 6143 u8 uid[0x10]; 6144 6145 u8 reserved_at_20[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 sq_state[0x4]; 6149 u8 reserved_at_44[0x4]; 6150 u8 sqn[0x18]; 6151 6152 u8 reserved_at_60[0x20]; 6153 6154 u8 modify_bitmask[0x40]; 6155 6156 u8 reserved_at_c0[0x40]; 6157 6158 struct mlx5_ifc_sqc_bits ctx; 6159 }; 6160 6161 struct mlx5_ifc_modify_scheduling_element_out_bits { 6162 u8 status[0x8]; 6163 u8 reserved_at_8[0x18]; 6164 6165 u8 syndrome[0x20]; 6166 6167 u8 reserved_at_40[0x1c0]; 6168 }; 6169 6170 enum { 6171 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6172 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6173 }; 6174 6175 struct mlx5_ifc_modify_scheduling_element_in_bits { 6176 u8 opcode[0x10]; 6177 u8 reserved_at_10[0x10]; 6178 6179 u8 reserved_at_20[0x10]; 6180 u8 op_mod[0x10]; 6181 6182 u8 scheduling_hierarchy[0x8]; 6183 u8 reserved_at_48[0x18]; 6184 6185 u8 scheduling_element_id[0x20]; 6186 6187 u8 reserved_at_80[0x20]; 6188 6189 u8 modify_bitmask[0x20]; 6190 6191 u8 reserved_at_c0[0x40]; 6192 6193 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6194 6195 u8 reserved_at_300[0x100]; 6196 }; 6197 6198 struct mlx5_ifc_modify_rqt_out_bits { 6199 u8 status[0x8]; 6200 u8 reserved_at_8[0x18]; 6201 6202 u8 syndrome[0x20]; 6203 6204 u8 reserved_at_40[0x40]; 6205 }; 6206 6207 struct mlx5_ifc_rqt_bitmask_bits { 6208 u8 reserved_at_0[0x20]; 6209 6210 u8 reserved_at_20[0x1f]; 6211 u8 rqn_list[0x1]; 6212 }; 6213 6214 struct mlx5_ifc_modify_rqt_in_bits { 6215 u8 opcode[0x10]; 6216 u8 uid[0x10]; 6217 6218 u8 reserved_at_20[0x10]; 6219 u8 op_mod[0x10]; 6220 6221 u8 reserved_at_40[0x8]; 6222 u8 rqtn[0x18]; 6223 6224 u8 reserved_at_60[0x20]; 6225 6226 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6227 6228 u8 reserved_at_c0[0x40]; 6229 6230 struct mlx5_ifc_rqtc_bits ctx; 6231 }; 6232 6233 struct mlx5_ifc_modify_rq_out_bits { 6234 u8 status[0x8]; 6235 u8 reserved_at_8[0x18]; 6236 6237 u8 syndrome[0x20]; 6238 6239 u8 reserved_at_40[0x40]; 6240 }; 6241 6242 enum { 6243 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6244 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6245 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6246 }; 6247 6248 struct mlx5_ifc_modify_rq_in_bits { 6249 u8 opcode[0x10]; 6250 u8 uid[0x10]; 6251 6252 u8 reserved_at_20[0x10]; 6253 u8 op_mod[0x10]; 6254 6255 u8 rq_state[0x4]; 6256 u8 reserved_at_44[0x4]; 6257 u8 rqn[0x18]; 6258 6259 u8 reserved_at_60[0x20]; 6260 6261 u8 modify_bitmask[0x40]; 6262 6263 u8 reserved_at_c0[0x40]; 6264 6265 struct mlx5_ifc_rqc_bits ctx; 6266 }; 6267 6268 struct mlx5_ifc_modify_rmp_out_bits { 6269 u8 status[0x8]; 6270 u8 reserved_at_8[0x18]; 6271 6272 u8 syndrome[0x20]; 6273 6274 u8 reserved_at_40[0x40]; 6275 }; 6276 6277 struct mlx5_ifc_rmp_bitmask_bits { 6278 u8 reserved_at_0[0x20]; 6279 6280 u8 reserved_at_20[0x1f]; 6281 u8 lwm[0x1]; 6282 }; 6283 6284 struct mlx5_ifc_modify_rmp_in_bits { 6285 u8 opcode[0x10]; 6286 u8 uid[0x10]; 6287 6288 u8 reserved_at_20[0x10]; 6289 u8 op_mod[0x10]; 6290 6291 u8 rmp_state[0x4]; 6292 u8 reserved_at_44[0x4]; 6293 u8 rmpn[0x18]; 6294 6295 u8 reserved_at_60[0x20]; 6296 6297 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6298 6299 u8 reserved_at_c0[0x40]; 6300 6301 struct mlx5_ifc_rmpc_bits ctx; 6302 }; 6303 6304 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6305 u8 status[0x8]; 6306 u8 reserved_at_8[0x18]; 6307 6308 u8 syndrome[0x20]; 6309 6310 u8 reserved_at_40[0x40]; 6311 }; 6312 6313 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6314 u8 reserved_at_0[0x12]; 6315 u8 affiliation[0x1]; 6316 u8 reserved_at_13[0x1]; 6317 u8 disable_uc_local_lb[0x1]; 6318 u8 disable_mc_local_lb[0x1]; 6319 u8 node_guid[0x1]; 6320 u8 port_guid[0x1]; 6321 u8 min_inline[0x1]; 6322 u8 mtu[0x1]; 6323 u8 change_event[0x1]; 6324 u8 promisc[0x1]; 6325 u8 permanent_address[0x1]; 6326 u8 addresses_list[0x1]; 6327 u8 roce_en[0x1]; 6328 u8 reserved_at_1f[0x1]; 6329 }; 6330 6331 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6332 u8 opcode[0x10]; 6333 u8 reserved_at_10[0x10]; 6334 6335 u8 reserved_at_20[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 other_vport[0x1]; 6339 u8 reserved_at_41[0xf]; 6340 u8 vport_number[0x10]; 6341 6342 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6343 6344 u8 reserved_at_80[0x780]; 6345 6346 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6347 }; 6348 6349 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6350 u8 status[0x8]; 6351 u8 reserved_at_8[0x18]; 6352 6353 u8 syndrome[0x20]; 6354 6355 u8 reserved_at_40[0x40]; 6356 }; 6357 6358 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6359 u8 opcode[0x10]; 6360 u8 reserved_at_10[0x10]; 6361 6362 u8 reserved_at_20[0x10]; 6363 u8 op_mod[0x10]; 6364 6365 u8 other_vport[0x1]; 6366 u8 reserved_at_41[0xb]; 6367 u8 port_num[0x4]; 6368 u8 vport_number[0x10]; 6369 6370 u8 reserved_at_60[0x20]; 6371 6372 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6373 }; 6374 6375 struct mlx5_ifc_modify_cq_out_bits { 6376 u8 status[0x8]; 6377 u8 reserved_at_8[0x18]; 6378 6379 u8 syndrome[0x20]; 6380 6381 u8 reserved_at_40[0x40]; 6382 }; 6383 6384 enum { 6385 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6386 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6387 }; 6388 6389 struct mlx5_ifc_modify_cq_in_bits { 6390 u8 opcode[0x10]; 6391 u8 uid[0x10]; 6392 6393 u8 reserved_at_20[0x10]; 6394 u8 op_mod[0x10]; 6395 6396 u8 reserved_at_40[0x8]; 6397 u8 cqn[0x18]; 6398 6399 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6400 6401 struct mlx5_ifc_cqc_bits cq_context; 6402 6403 u8 reserved_at_280[0x60]; 6404 6405 u8 cq_umem_valid[0x1]; 6406 u8 reserved_at_2e1[0x1f]; 6407 6408 u8 reserved_at_300[0x580]; 6409 6410 u8 pas[0][0x40]; 6411 }; 6412 6413 struct mlx5_ifc_modify_cong_status_out_bits { 6414 u8 status[0x8]; 6415 u8 reserved_at_8[0x18]; 6416 6417 u8 syndrome[0x20]; 6418 6419 u8 reserved_at_40[0x40]; 6420 }; 6421 6422 struct mlx5_ifc_modify_cong_status_in_bits { 6423 u8 opcode[0x10]; 6424 u8 reserved_at_10[0x10]; 6425 6426 u8 reserved_at_20[0x10]; 6427 u8 op_mod[0x10]; 6428 6429 u8 reserved_at_40[0x18]; 6430 u8 priority[0x4]; 6431 u8 cong_protocol[0x4]; 6432 6433 u8 enable[0x1]; 6434 u8 tag_enable[0x1]; 6435 u8 reserved_at_62[0x1e]; 6436 }; 6437 6438 struct mlx5_ifc_modify_cong_params_out_bits { 6439 u8 status[0x8]; 6440 u8 reserved_at_8[0x18]; 6441 6442 u8 syndrome[0x20]; 6443 6444 u8 reserved_at_40[0x40]; 6445 }; 6446 6447 struct mlx5_ifc_modify_cong_params_in_bits { 6448 u8 opcode[0x10]; 6449 u8 reserved_at_10[0x10]; 6450 6451 u8 reserved_at_20[0x10]; 6452 u8 op_mod[0x10]; 6453 6454 u8 reserved_at_40[0x1c]; 6455 u8 cong_protocol[0x4]; 6456 6457 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6458 6459 u8 reserved_at_80[0x80]; 6460 6461 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6462 }; 6463 6464 struct mlx5_ifc_manage_pages_out_bits { 6465 u8 status[0x8]; 6466 u8 reserved_at_8[0x18]; 6467 6468 u8 syndrome[0x20]; 6469 6470 u8 output_num_entries[0x20]; 6471 6472 u8 reserved_at_60[0x20]; 6473 6474 u8 pas[0][0x40]; 6475 }; 6476 6477 enum { 6478 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6479 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6480 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6481 }; 6482 6483 struct mlx5_ifc_manage_pages_in_bits { 6484 u8 opcode[0x10]; 6485 u8 reserved_at_10[0x10]; 6486 6487 u8 reserved_at_20[0x10]; 6488 u8 op_mod[0x10]; 6489 6490 u8 embedded_cpu_function[0x1]; 6491 u8 reserved_at_41[0xf]; 6492 u8 function_id[0x10]; 6493 6494 u8 input_num_entries[0x20]; 6495 6496 u8 pas[0][0x40]; 6497 }; 6498 6499 struct mlx5_ifc_mad_ifc_out_bits { 6500 u8 status[0x8]; 6501 u8 reserved_at_8[0x18]; 6502 6503 u8 syndrome[0x20]; 6504 6505 u8 reserved_at_40[0x40]; 6506 6507 u8 response_mad_packet[256][0x8]; 6508 }; 6509 6510 struct mlx5_ifc_mad_ifc_in_bits { 6511 u8 opcode[0x10]; 6512 u8 reserved_at_10[0x10]; 6513 6514 u8 reserved_at_20[0x10]; 6515 u8 op_mod[0x10]; 6516 6517 u8 remote_lid[0x10]; 6518 u8 reserved_at_50[0x8]; 6519 u8 port[0x8]; 6520 6521 u8 reserved_at_60[0x20]; 6522 6523 u8 mad[256][0x8]; 6524 }; 6525 6526 struct mlx5_ifc_init_hca_out_bits { 6527 u8 status[0x8]; 6528 u8 reserved_at_8[0x18]; 6529 6530 u8 syndrome[0x20]; 6531 6532 u8 reserved_at_40[0x40]; 6533 }; 6534 6535 struct mlx5_ifc_init_hca_in_bits { 6536 u8 opcode[0x10]; 6537 u8 reserved_at_10[0x10]; 6538 6539 u8 reserved_at_20[0x10]; 6540 u8 op_mod[0x10]; 6541 6542 u8 reserved_at_40[0x40]; 6543 u8 sw_owner_id[4][0x20]; 6544 }; 6545 6546 struct mlx5_ifc_init2rtr_qp_out_bits { 6547 u8 status[0x8]; 6548 u8 reserved_at_8[0x18]; 6549 6550 u8 syndrome[0x20]; 6551 6552 u8 reserved_at_40[0x40]; 6553 }; 6554 6555 struct mlx5_ifc_init2rtr_qp_in_bits { 6556 u8 opcode[0x10]; 6557 u8 uid[0x10]; 6558 6559 u8 reserved_at_20[0x10]; 6560 u8 op_mod[0x10]; 6561 6562 u8 reserved_at_40[0x8]; 6563 u8 qpn[0x18]; 6564 6565 u8 reserved_at_60[0x20]; 6566 6567 u8 opt_param_mask[0x20]; 6568 6569 u8 reserved_at_a0[0x20]; 6570 6571 struct mlx5_ifc_qpc_bits qpc; 6572 6573 u8 reserved_at_800[0x80]; 6574 }; 6575 6576 struct mlx5_ifc_init2init_qp_out_bits { 6577 u8 status[0x8]; 6578 u8 reserved_at_8[0x18]; 6579 6580 u8 syndrome[0x20]; 6581 6582 u8 reserved_at_40[0x40]; 6583 }; 6584 6585 struct mlx5_ifc_init2init_qp_in_bits { 6586 u8 opcode[0x10]; 6587 u8 uid[0x10]; 6588 6589 u8 reserved_at_20[0x10]; 6590 u8 op_mod[0x10]; 6591 6592 u8 reserved_at_40[0x8]; 6593 u8 qpn[0x18]; 6594 6595 u8 reserved_at_60[0x20]; 6596 6597 u8 opt_param_mask[0x20]; 6598 6599 u8 reserved_at_a0[0x20]; 6600 6601 struct mlx5_ifc_qpc_bits qpc; 6602 6603 u8 reserved_at_800[0x80]; 6604 }; 6605 6606 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6607 u8 status[0x8]; 6608 u8 reserved_at_8[0x18]; 6609 6610 u8 syndrome[0x20]; 6611 6612 u8 reserved_at_40[0x40]; 6613 6614 u8 packet_headers_log[128][0x8]; 6615 6616 u8 packet_syndrome[64][0x8]; 6617 }; 6618 6619 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6620 u8 opcode[0x10]; 6621 u8 reserved_at_10[0x10]; 6622 6623 u8 reserved_at_20[0x10]; 6624 u8 op_mod[0x10]; 6625 6626 u8 reserved_at_40[0x40]; 6627 }; 6628 6629 struct mlx5_ifc_gen_eqe_in_bits { 6630 u8 opcode[0x10]; 6631 u8 reserved_at_10[0x10]; 6632 6633 u8 reserved_at_20[0x10]; 6634 u8 op_mod[0x10]; 6635 6636 u8 reserved_at_40[0x18]; 6637 u8 eq_number[0x8]; 6638 6639 u8 reserved_at_60[0x20]; 6640 6641 u8 eqe[64][0x8]; 6642 }; 6643 6644 struct mlx5_ifc_gen_eq_out_bits { 6645 u8 status[0x8]; 6646 u8 reserved_at_8[0x18]; 6647 6648 u8 syndrome[0x20]; 6649 6650 u8 reserved_at_40[0x40]; 6651 }; 6652 6653 struct mlx5_ifc_enable_hca_out_bits { 6654 u8 status[0x8]; 6655 u8 reserved_at_8[0x18]; 6656 6657 u8 syndrome[0x20]; 6658 6659 u8 reserved_at_40[0x20]; 6660 }; 6661 6662 struct mlx5_ifc_enable_hca_in_bits { 6663 u8 opcode[0x10]; 6664 u8 reserved_at_10[0x10]; 6665 6666 u8 reserved_at_20[0x10]; 6667 u8 op_mod[0x10]; 6668 6669 u8 embedded_cpu_function[0x1]; 6670 u8 reserved_at_41[0xf]; 6671 u8 function_id[0x10]; 6672 6673 u8 reserved_at_60[0x20]; 6674 }; 6675 6676 struct mlx5_ifc_drain_dct_out_bits { 6677 u8 status[0x8]; 6678 u8 reserved_at_8[0x18]; 6679 6680 u8 syndrome[0x20]; 6681 6682 u8 reserved_at_40[0x40]; 6683 }; 6684 6685 struct mlx5_ifc_drain_dct_in_bits { 6686 u8 opcode[0x10]; 6687 u8 uid[0x10]; 6688 6689 u8 reserved_at_20[0x10]; 6690 u8 op_mod[0x10]; 6691 6692 u8 reserved_at_40[0x8]; 6693 u8 dctn[0x18]; 6694 6695 u8 reserved_at_60[0x20]; 6696 }; 6697 6698 struct mlx5_ifc_disable_hca_out_bits { 6699 u8 status[0x8]; 6700 u8 reserved_at_8[0x18]; 6701 6702 u8 syndrome[0x20]; 6703 6704 u8 reserved_at_40[0x20]; 6705 }; 6706 6707 struct mlx5_ifc_disable_hca_in_bits { 6708 u8 opcode[0x10]; 6709 u8 reserved_at_10[0x10]; 6710 6711 u8 reserved_at_20[0x10]; 6712 u8 op_mod[0x10]; 6713 6714 u8 embedded_cpu_function[0x1]; 6715 u8 reserved_at_41[0xf]; 6716 u8 function_id[0x10]; 6717 6718 u8 reserved_at_60[0x20]; 6719 }; 6720 6721 struct mlx5_ifc_detach_from_mcg_out_bits { 6722 u8 status[0x8]; 6723 u8 reserved_at_8[0x18]; 6724 6725 u8 syndrome[0x20]; 6726 6727 u8 reserved_at_40[0x40]; 6728 }; 6729 6730 struct mlx5_ifc_detach_from_mcg_in_bits { 6731 u8 opcode[0x10]; 6732 u8 uid[0x10]; 6733 6734 u8 reserved_at_20[0x10]; 6735 u8 op_mod[0x10]; 6736 6737 u8 reserved_at_40[0x8]; 6738 u8 qpn[0x18]; 6739 6740 u8 reserved_at_60[0x20]; 6741 6742 u8 multicast_gid[16][0x8]; 6743 }; 6744 6745 struct mlx5_ifc_destroy_xrq_out_bits { 6746 u8 status[0x8]; 6747 u8 reserved_at_8[0x18]; 6748 6749 u8 syndrome[0x20]; 6750 6751 u8 reserved_at_40[0x40]; 6752 }; 6753 6754 struct mlx5_ifc_destroy_xrq_in_bits { 6755 u8 opcode[0x10]; 6756 u8 uid[0x10]; 6757 6758 u8 reserved_at_20[0x10]; 6759 u8 op_mod[0x10]; 6760 6761 u8 reserved_at_40[0x8]; 6762 u8 xrqn[0x18]; 6763 6764 u8 reserved_at_60[0x20]; 6765 }; 6766 6767 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_at_8[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 reserved_at_40[0x40]; 6774 }; 6775 6776 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6777 u8 opcode[0x10]; 6778 u8 uid[0x10]; 6779 6780 u8 reserved_at_20[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 reserved_at_40[0x8]; 6784 u8 xrc_srqn[0x18]; 6785 6786 u8 reserved_at_60[0x20]; 6787 }; 6788 6789 struct mlx5_ifc_destroy_tis_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_at_8[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 reserved_at_40[0x40]; 6796 }; 6797 6798 struct mlx5_ifc_destroy_tis_in_bits { 6799 u8 opcode[0x10]; 6800 u8 uid[0x10]; 6801 6802 u8 reserved_at_20[0x10]; 6803 u8 op_mod[0x10]; 6804 6805 u8 reserved_at_40[0x8]; 6806 u8 tisn[0x18]; 6807 6808 u8 reserved_at_60[0x20]; 6809 }; 6810 6811 struct mlx5_ifc_destroy_tir_out_bits { 6812 u8 status[0x8]; 6813 u8 reserved_at_8[0x18]; 6814 6815 u8 syndrome[0x20]; 6816 6817 u8 reserved_at_40[0x40]; 6818 }; 6819 6820 struct mlx5_ifc_destroy_tir_in_bits { 6821 u8 opcode[0x10]; 6822 u8 uid[0x10]; 6823 6824 u8 reserved_at_20[0x10]; 6825 u8 op_mod[0x10]; 6826 6827 u8 reserved_at_40[0x8]; 6828 u8 tirn[0x18]; 6829 6830 u8 reserved_at_60[0x20]; 6831 }; 6832 6833 struct mlx5_ifc_destroy_srq_out_bits { 6834 u8 status[0x8]; 6835 u8 reserved_at_8[0x18]; 6836 6837 u8 syndrome[0x20]; 6838 6839 u8 reserved_at_40[0x40]; 6840 }; 6841 6842 struct mlx5_ifc_destroy_srq_in_bits { 6843 u8 opcode[0x10]; 6844 u8 uid[0x10]; 6845 6846 u8 reserved_at_20[0x10]; 6847 u8 op_mod[0x10]; 6848 6849 u8 reserved_at_40[0x8]; 6850 u8 srqn[0x18]; 6851 6852 u8 reserved_at_60[0x20]; 6853 }; 6854 6855 struct mlx5_ifc_destroy_sq_out_bits { 6856 u8 status[0x8]; 6857 u8 reserved_at_8[0x18]; 6858 6859 u8 syndrome[0x20]; 6860 6861 u8 reserved_at_40[0x40]; 6862 }; 6863 6864 struct mlx5_ifc_destroy_sq_in_bits { 6865 u8 opcode[0x10]; 6866 u8 uid[0x10]; 6867 6868 u8 reserved_at_20[0x10]; 6869 u8 op_mod[0x10]; 6870 6871 u8 reserved_at_40[0x8]; 6872 u8 sqn[0x18]; 6873 6874 u8 reserved_at_60[0x20]; 6875 }; 6876 6877 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6878 u8 status[0x8]; 6879 u8 reserved_at_8[0x18]; 6880 6881 u8 syndrome[0x20]; 6882 6883 u8 reserved_at_40[0x1c0]; 6884 }; 6885 6886 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6887 u8 opcode[0x10]; 6888 u8 reserved_at_10[0x10]; 6889 6890 u8 reserved_at_20[0x10]; 6891 u8 op_mod[0x10]; 6892 6893 u8 scheduling_hierarchy[0x8]; 6894 u8 reserved_at_48[0x18]; 6895 6896 u8 scheduling_element_id[0x20]; 6897 6898 u8 reserved_at_80[0x180]; 6899 }; 6900 6901 struct mlx5_ifc_destroy_rqt_out_bits { 6902 u8 status[0x8]; 6903 u8 reserved_at_8[0x18]; 6904 6905 u8 syndrome[0x20]; 6906 6907 u8 reserved_at_40[0x40]; 6908 }; 6909 6910 struct mlx5_ifc_destroy_rqt_in_bits { 6911 u8 opcode[0x10]; 6912 u8 uid[0x10]; 6913 6914 u8 reserved_at_20[0x10]; 6915 u8 op_mod[0x10]; 6916 6917 u8 reserved_at_40[0x8]; 6918 u8 rqtn[0x18]; 6919 6920 u8 reserved_at_60[0x20]; 6921 }; 6922 6923 struct mlx5_ifc_destroy_rq_out_bits { 6924 u8 status[0x8]; 6925 u8 reserved_at_8[0x18]; 6926 6927 u8 syndrome[0x20]; 6928 6929 u8 reserved_at_40[0x40]; 6930 }; 6931 6932 struct mlx5_ifc_destroy_rq_in_bits { 6933 u8 opcode[0x10]; 6934 u8 uid[0x10]; 6935 6936 u8 reserved_at_20[0x10]; 6937 u8 op_mod[0x10]; 6938 6939 u8 reserved_at_40[0x8]; 6940 u8 rqn[0x18]; 6941 6942 u8 reserved_at_60[0x20]; 6943 }; 6944 6945 struct mlx5_ifc_set_delay_drop_params_in_bits { 6946 u8 opcode[0x10]; 6947 u8 reserved_at_10[0x10]; 6948 6949 u8 reserved_at_20[0x10]; 6950 u8 op_mod[0x10]; 6951 6952 u8 reserved_at_40[0x20]; 6953 6954 u8 reserved_at_60[0x10]; 6955 u8 delay_drop_timeout[0x10]; 6956 }; 6957 6958 struct mlx5_ifc_set_delay_drop_params_out_bits { 6959 u8 status[0x8]; 6960 u8 reserved_at_8[0x18]; 6961 6962 u8 syndrome[0x20]; 6963 6964 u8 reserved_at_40[0x40]; 6965 }; 6966 6967 struct mlx5_ifc_destroy_rmp_out_bits { 6968 u8 status[0x8]; 6969 u8 reserved_at_8[0x18]; 6970 6971 u8 syndrome[0x20]; 6972 6973 u8 reserved_at_40[0x40]; 6974 }; 6975 6976 struct mlx5_ifc_destroy_rmp_in_bits { 6977 u8 opcode[0x10]; 6978 u8 uid[0x10]; 6979 6980 u8 reserved_at_20[0x10]; 6981 u8 op_mod[0x10]; 6982 6983 u8 reserved_at_40[0x8]; 6984 u8 rmpn[0x18]; 6985 6986 u8 reserved_at_60[0x20]; 6987 }; 6988 6989 struct mlx5_ifc_destroy_qp_out_bits { 6990 u8 status[0x8]; 6991 u8 reserved_at_8[0x18]; 6992 6993 u8 syndrome[0x20]; 6994 6995 u8 reserved_at_40[0x40]; 6996 }; 6997 6998 struct mlx5_ifc_destroy_qp_in_bits { 6999 u8 opcode[0x10]; 7000 u8 uid[0x10]; 7001 7002 u8 reserved_at_20[0x10]; 7003 u8 op_mod[0x10]; 7004 7005 u8 reserved_at_40[0x8]; 7006 u8 qpn[0x18]; 7007 7008 u8 reserved_at_60[0x20]; 7009 }; 7010 7011 struct mlx5_ifc_destroy_psv_out_bits { 7012 u8 status[0x8]; 7013 u8 reserved_at_8[0x18]; 7014 7015 u8 syndrome[0x20]; 7016 7017 u8 reserved_at_40[0x40]; 7018 }; 7019 7020 struct mlx5_ifc_destroy_psv_in_bits { 7021 u8 opcode[0x10]; 7022 u8 reserved_at_10[0x10]; 7023 7024 u8 reserved_at_20[0x10]; 7025 u8 op_mod[0x10]; 7026 7027 u8 reserved_at_40[0x8]; 7028 u8 psvn[0x18]; 7029 7030 u8 reserved_at_60[0x20]; 7031 }; 7032 7033 struct mlx5_ifc_destroy_mkey_out_bits { 7034 u8 status[0x8]; 7035 u8 reserved_at_8[0x18]; 7036 7037 u8 syndrome[0x20]; 7038 7039 u8 reserved_at_40[0x40]; 7040 }; 7041 7042 struct mlx5_ifc_destroy_mkey_in_bits { 7043 u8 opcode[0x10]; 7044 u8 reserved_at_10[0x10]; 7045 7046 u8 reserved_at_20[0x10]; 7047 u8 op_mod[0x10]; 7048 7049 u8 reserved_at_40[0x8]; 7050 u8 mkey_index[0x18]; 7051 7052 u8 reserved_at_60[0x20]; 7053 }; 7054 7055 struct mlx5_ifc_destroy_flow_table_out_bits { 7056 u8 status[0x8]; 7057 u8 reserved_at_8[0x18]; 7058 7059 u8 syndrome[0x20]; 7060 7061 u8 reserved_at_40[0x40]; 7062 }; 7063 7064 struct mlx5_ifc_destroy_flow_table_in_bits { 7065 u8 opcode[0x10]; 7066 u8 reserved_at_10[0x10]; 7067 7068 u8 reserved_at_20[0x10]; 7069 u8 op_mod[0x10]; 7070 7071 u8 other_vport[0x1]; 7072 u8 reserved_at_41[0xf]; 7073 u8 vport_number[0x10]; 7074 7075 u8 reserved_at_60[0x20]; 7076 7077 u8 table_type[0x8]; 7078 u8 reserved_at_88[0x18]; 7079 7080 u8 reserved_at_a0[0x8]; 7081 u8 table_id[0x18]; 7082 7083 u8 reserved_at_c0[0x140]; 7084 }; 7085 7086 struct mlx5_ifc_destroy_flow_group_out_bits { 7087 u8 status[0x8]; 7088 u8 reserved_at_8[0x18]; 7089 7090 u8 syndrome[0x20]; 7091 7092 u8 reserved_at_40[0x40]; 7093 }; 7094 7095 struct mlx5_ifc_destroy_flow_group_in_bits { 7096 u8 opcode[0x10]; 7097 u8 reserved_at_10[0x10]; 7098 7099 u8 reserved_at_20[0x10]; 7100 u8 op_mod[0x10]; 7101 7102 u8 other_vport[0x1]; 7103 u8 reserved_at_41[0xf]; 7104 u8 vport_number[0x10]; 7105 7106 u8 reserved_at_60[0x20]; 7107 7108 u8 table_type[0x8]; 7109 u8 reserved_at_88[0x18]; 7110 7111 u8 reserved_at_a0[0x8]; 7112 u8 table_id[0x18]; 7113 7114 u8 group_id[0x20]; 7115 7116 u8 reserved_at_e0[0x120]; 7117 }; 7118 7119 struct mlx5_ifc_destroy_eq_out_bits { 7120 u8 status[0x8]; 7121 u8 reserved_at_8[0x18]; 7122 7123 u8 syndrome[0x20]; 7124 7125 u8 reserved_at_40[0x40]; 7126 }; 7127 7128 struct mlx5_ifc_destroy_eq_in_bits { 7129 u8 opcode[0x10]; 7130 u8 reserved_at_10[0x10]; 7131 7132 u8 reserved_at_20[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 reserved_at_40[0x18]; 7136 u8 eq_number[0x8]; 7137 7138 u8 reserved_at_60[0x20]; 7139 }; 7140 7141 struct mlx5_ifc_destroy_dct_out_bits { 7142 u8 status[0x8]; 7143 u8 reserved_at_8[0x18]; 7144 7145 u8 syndrome[0x20]; 7146 7147 u8 reserved_at_40[0x40]; 7148 }; 7149 7150 struct mlx5_ifc_destroy_dct_in_bits { 7151 u8 opcode[0x10]; 7152 u8 uid[0x10]; 7153 7154 u8 reserved_at_20[0x10]; 7155 u8 op_mod[0x10]; 7156 7157 u8 reserved_at_40[0x8]; 7158 u8 dctn[0x18]; 7159 7160 u8 reserved_at_60[0x20]; 7161 }; 7162 7163 struct mlx5_ifc_destroy_cq_out_bits { 7164 u8 status[0x8]; 7165 u8 reserved_at_8[0x18]; 7166 7167 u8 syndrome[0x20]; 7168 7169 u8 reserved_at_40[0x40]; 7170 }; 7171 7172 struct mlx5_ifc_destroy_cq_in_bits { 7173 u8 opcode[0x10]; 7174 u8 uid[0x10]; 7175 7176 u8 reserved_at_20[0x10]; 7177 u8 op_mod[0x10]; 7178 7179 u8 reserved_at_40[0x8]; 7180 u8 cqn[0x18]; 7181 7182 u8 reserved_at_60[0x20]; 7183 }; 7184 7185 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7186 u8 status[0x8]; 7187 u8 reserved_at_8[0x18]; 7188 7189 u8 syndrome[0x20]; 7190 7191 u8 reserved_at_40[0x40]; 7192 }; 7193 7194 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7195 u8 opcode[0x10]; 7196 u8 reserved_at_10[0x10]; 7197 7198 u8 reserved_at_20[0x10]; 7199 u8 op_mod[0x10]; 7200 7201 u8 reserved_at_40[0x20]; 7202 7203 u8 reserved_at_60[0x10]; 7204 u8 vxlan_udp_port[0x10]; 7205 }; 7206 7207 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7208 u8 status[0x8]; 7209 u8 reserved_at_8[0x18]; 7210 7211 u8 syndrome[0x20]; 7212 7213 u8 reserved_at_40[0x40]; 7214 }; 7215 7216 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7217 u8 opcode[0x10]; 7218 u8 reserved_at_10[0x10]; 7219 7220 u8 reserved_at_20[0x10]; 7221 u8 op_mod[0x10]; 7222 7223 u8 reserved_at_40[0x60]; 7224 7225 u8 reserved_at_a0[0x8]; 7226 u8 table_index[0x18]; 7227 7228 u8 reserved_at_c0[0x140]; 7229 }; 7230 7231 struct mlx5_ifc_delete_fte_out_bits { 7232 u8 status[0x8]; 7233 u8 reserved_at_8[0x18]; 7234 7235 u8 syndrome[0x20]; 7236 7237 u8 reserved_at_40[0x40]; 7238 }; 7239 7240 struct mlx5_ifc_delete_fte_in_bits { 7241 u8 opcode[0x10]; 7242 u8 reserved_at_10[0x10]; 7243 7244 u8 reserved_at_20[0x10]; 7245 u8 op_mod[0x10]; 7246 7247 u8 other_vport[0x1]; 7248 u8 reserved_at_41[0xf]; 7249 u8 vport_number[0x10]; 7250 7251 u8 reserved_at_60[0x20]; 7252 7253 u8 table_type[0x8]; 7254 u8 reserved_at_88[0x18]; 7255 7256 u8 reserved_at_a0[0x8]; 7257 u8 table_id[0x18]; 7258 7259 u8 reserved_at_c0[0x40]; 7260 7261 u8 flow_index[0x20]; 7262 7263 u8 reserved_at_120[0xe0]; 7264 }; 7265 7266 struct mlx5_ifc_dealloc_xrcd_out_bits { 7267 u8 status[0x8]; 7268 u8 reserved_at_8[0x18]; 7269 7270 u8 syndrome[0x20]; 7271 7272 u8 reserved_at_40[0x40]; 7273 }; 7274 7275 struct mlx5_ifc_dealloc_xrcd_in_bits { 7276 u8 opcode[0x10]; 7277 u8 uid[0x10]; 7278 7279 u8 reserved_at_20[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 reserved_at_40[0x8]; 7283 u8 xrcd[0x18]; 7284 7285 u8 reserved_at_60[0x20]; 7286 }; 7287 7288 struct mlx5_ifc_dealloc_uar_out_bits { 7289 u8 status[0x8]; 7290 u8 reserved_at_8[0x18]; 7291 7292 u8 syndrome[0x20]; 7293 7294 u8 reserved_at_40[0x40]; 7295 }; 7296 7297 struct mlx5_ifc_dealloc_uar_in_bits { 7298 u8 opcode[0x10]; 7299 u8 reserved_at_10[0x10]; 7300 7301 u8 reserved_at_20[0x10]; 7302 u8 op_mod[0x10]; 7303 7304 u8 reserved_at_40[0x8]; 7305 u8 uar[0x18]; 7306 7307 u8 reserved_at_60[0x20]; 7308 }; 7309 7310 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7311 u8 status[0x8]; 7312 u8 reserved_at_8[0x18]; 7313 7314 u8 syndrome[0x20]; 7315 7316 u8 reserved_at_40[0x40]; 7317 }; 7318 7319 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7320 u8 opcode[0x10]; 7321 u8 uid[0x10]; 7322 7323 u8 reserved_at_20[0x10]; 7324 u8 op_mod[0x10]; 7325 7326 u8 reserved_at_40[0x8]; 7327 u8 transport_domain[0x18]; 7328 7329 u8 reserved_at_60[0x20]; 7330 }; 7331 7332 struct mlx5_ifc_dealloc_q_counter_out_bits { 7333 u8 status[0x8]; 7334 u8 reserved_at_8[0x18]; 7335 7336 u8 syndrome[0x20]; 7337 7338 u8 reserved_at_40[0x40]; 7339 }; 7340 7341 struct mlx5_ifc_dealloc_q_counter_in_bits { 7342 u8 opcode[0x10]; 7343 u8 reserved_at_10[0x10]; 7344 7345 u8 reserved_at_20[0x10]; 7346 u8 op_mod[0x10]; 7347 7348 u8 reserved_at_40[0x18]; 7349 u8 counter_set_id[0x8]; 7350 7351 u8 reserved_at_60[0x20]; 7352 }; 7353 7354 struct mlx5_ifc_dealloc_pd_out_bits { 7355 u8 status[0x8]; 7356 u8 reserved_at_8[0x18]; 7357 7358 u8 syndrome[0x20]; 7359 7360 u8 reserved_at_40[0x40]; 7361 }; 7362 7363 struct mlx5_ifc_dealloc_pd_in_bits { 7364 u8 opcode[0x10]; 7365 u8 uid[0x10]; 7366 7367 u8 reserved_at_20[0x10]; 7368 u8 op_mod[0x10]; 7369 7370 u8 reserved_at_40[0x8]; 7371 u8 pd[0x18]; 7372 7373 u8 reserved_at_60[0x20]; 7374 }; 7375 7376 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7377 u8 status[0x8]; 7378 u8 reserved_at_8[0x18]; 7379 7380 u8 syndrome[0x20]; 7381 7382 u8 reserved_at_40[0x40]; 7383 }; 7384 7385 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7386 u8 opcode[0x10]; 7387 u8 reserved_at_10[0x10]; 7388 7389 u8 reserved_at_20[0x10]; 7390 u8 op_mod[0x10]; 7391 7392 u8 flow_counter_id[0x20]; 7393 7394 u8 reserved_at_60[0x20]; 7395 }; 7396 7397 struct mlx5_ifc_create_xrq_out_bits { 7398 u8 status[0x8]; 7399 u8 reserved_at_8[0x18]; 7400 7401 u8 syndrome[0x20]; 7402 7403 u8 reserved_at_40[0x8]; 7404 u8 xrqn[0x18]; 7405 7406 u8 reserved_at_60[0x20]; 7407 }; 7408 7409 struct mlx5_ifc_create_xrq_in_bits { 7410 u8 opcode[0x10]; 7411 u8 uid[0x10]; 7412 7413 u8 reserved_at_20[0x10]; 7414 u8 op_mod[0x10]; 7415 7416 u8 reserved_at_40[0x40]; 7417 7418 struct mlx5_ifc_xrqc_bits xrq_context; 7419 }; 7420 7421 struct mlx5_ifc_create_xrc_srq_out_bits { 7422 u8 status[0x8]; 7423 u8 reserved_at_8[0x18]; 7424 7425 u8 syndrome[0x20]; 7426 7427 u8 reserved_at_40[0x8]; 7428 u8 xrc_srqn[0x18]; 7429 7430 u8 reserved_at_60[0x20]; 7431 }; 7432 7433 struct mlx5_ifc_create_xrc_srq_in_bits { 7434 u8 opcode[0x10]; 7435 u8 uid[0x10]; 7436 7437 u8 reserved_at_20[0x10]; 7438 u8 op_mod[0x10]; 7439 7440 u8 reserved_at_40[0x40]; 7441 7442 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7443 7444 u8 reserved_at_280[0x60]; 7445 7446 u8 xrc_srq_umem_valid[0x1]; 7447 u8 reserved_at_2e1[0x1f]; 7448 7449 u8 reserved_at_300[0x580]; 7450 7451 u8 pas[0][0x40]; 7452 }; 7453 7454 struct mlx5_ifc_create_tis_out_bits { 7455 u8 status[0x8]; 7456 u8 reserved_at_8[0x18]; 7457 7458 u8 syndrome[0x20]; 7459 7460 u8 reserved_at_40[0x8]; 7461 u8 tisn[0x18]; 7462 7463 u8 reserved_at_60[0x20]; 7464 }; 7465 7466 struct mlx5_ifc_create_tis_in_bits { 7467 u8 opcode[0x10]; 7468 u8 uid[0x10]; 7469 7470 u8 reserved_at_20[0x10]; 7471 u8 op_mod[0x10]; 7472 7473 u8 reserved_at_40[0xc0]; 7474 7475 struct mlx5_ifc_tisc_bits ctx; 7476 }; 7477 7478 struct mlx5_ifc_create_tir_out_bits { 7479 u8 status[0x8]; 7480 u8 icm_address_63_40[0x18]; 7481 7482 u8 syndrome[0x20]; 7483 7484 u8 icm_address_39_32[0x8]; 7485 u8 tirn[0x18]; 7486 7487 u8 icm_address_31_0[0x20]; 7488 }; 7489 7490 struct mlx5_ifc_create_tir_in_bits { 7491 u8 opcode[0x10]; 7492 u8 uid[0x10]; 7493 7494 u8 reserved_at_20[0x10]; 7495 u8 op_mod[0x10]; 7496 7497 u8 reserved_at_40[0xc0]; 7498 7499 struct mlx5_ifc_tirc_bits ctx; 7500 }; 7501 7502 struct mlx5_ifc_create_srq_out_bits { 7503 u8 status[0x8]; 7504 u8 reserved_at_8[0x18]; 7505 7506 u8 syndrome[0x20]; 7507 7508 u8 reserved_at_40[0x8]; 7509 u8 srqn[0x18]; 7510 7511 u8 reserved_at_60[0x20]; 7512 }; 7513 7514 struct mlx5_ifc_create_srq_in_bits { 7515 u8 opcode[0x10]; 7516 u8 uid[0x10]; 7517 7518 u8 reserved_at_20[0x10]; 7519 u8 op_mod[0x10]; 7520 7521 u8 reserved_at_40[0x40]; 7522 7523 struct mlx5_ifc_srqc_bits srq_context_entry; 7524 7525 u8 reserved_at_280[0x600]; 7526 7527 u8 pas[0][0x40]; 7528 }; 7529 7530 struct mlx5_ifc_create_sq_out_bits { 7531 u8 status[0x8]; 7532 u8 reserved_at_8[0x18]; 7533 7534 u8 syndrome[0x20]; 7535 7536 u8 reserved_at_40[0x8]; 7537 u8 sqn[0x18]; 7538 7539 u8 reserved_at_60[0x20]; 7540 }; 7541 7542 struct mlx5_ifc_create_sq_in_bits { 7543 u8 opcode[0x10]; 7544 u8 uid[0x10]; 7545 7546 u8 reserved_at_20[0x10]; 7547 u8 op_mod[0x10]; 7548 7549 u8 reserved_at_40[0xc0]; 7550 7551 struct mlx5_ifc_sqc_bits ctx; 7552 }; 7553 7554 struct mlx5_ifc_create_scheduling_element_out_bits { 7555 u8 status[0x8]; 7556 u8 reserved_at_8[0x18]; 7557 7558 u8 syndrome[0x20]; 7559 7560 u8 reserved_at_40[0x40]; 7561 7562 u8 scheduling_element_id[0x20]; 7563 7564 u8 reserved_at_a0[0x160]; 7565 }; 7566 7567 struct mlx5_ifc_create_scheduling_element_in_bits { 7568 u8 opcode[0x10]; 7569 u8 reserved_at_10[0x10]; 7570 7571 u8 reserved_at_20[0x10]; 7572 u8 op_mod[0x10]; 7573 7574 u8 scheduling_hierarchy[0x8]; 7575 u8 reserved_at_48[0x18]; 7576 7577 u8 reserved_at_60[0xa0]; 7578 7579 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7580 7581 u8 reserved_at_300[0x100]; 7582 }; 7583 7584 struct mlx5_ifc_create_rqt_out_bits { 7585 u8 status[0x8]; 7586 u8 reserved_at_8[0x18]; 7587 7588 u8 syndrome[0x20]; 7589 7590 u8 reserved_at_40[0x8]; 7591 u8 rqtn[0x18]; 7592 7593 u8 reserved_at_60[0x20]; 7594 }; 7595 7596 struct mlx5_ifc_create_rqt_in_bits { 7597 u8 opcode[0x10]; 7598 u8 uid[0x10]; 7599 7600 u8 reserved_at_20[0x10]; 7601 u8 op_mod[0x10]; 7602 7603 u8 reserved_at_40[0xc0]; 7604 7605 struct mlx5_ifc_rqtc_bits rqt_context; 7606 }; 7607 7608 struct mlx5_ifc_create_rq_out_bits { 7609 u8 status[0x8]; 7610 u8 reserved_at_8[0x18]; 7611 7612 u8 syndrome[0x20]; 7613 7614 u8 reserved_at_40[0x8]; 7615 u8 rqn[0x18]; 7616 7617 u8 reserved_at_60[0x20]; 7618 }; 7619 7620 struct mlx5_ifc_create_rq_in_bits { 7621 u8 opcode[0x10]; 7622 u8 uid[0x10]; 7623 7624 u8 reserved_at_20[0x10]; 7625 u8 op_mod[0x10]; 7626 7627 u8 reserved_at_40[0xc0]; 7628 7629 struct mlx5_ifc_rqc_bits ctx; 7630 }; 7631 7632 struct mlx5_ifc_create_rmp_out_bits { 7633 u8 status[0x8]; 7634 u8 reserved_at_8[0x18]; 7635 7636 u8 syndrome[0x20]; 7637 7638 u8 reserved_at_40[0x8]; 7639 u8 rmpn[0x18]; 7640 7641 u8 reserved_at_60[0x20]; 7642 }; 7643 7644 struct mlx5_ifc_create_rmp_in_bits { 7645 u8 opcode[0x10]; 7646 u8 uid[0x10]; 7647 7648 u8 reserved_at_20[0x10]; 7649 u8 op_mod[0x10]; 7650 7651 u8 reserved_at_40[0xc0]; 7652 7653 struct mlx5_ifc_rmpc_bits ctx; 7654 }; 7655 7656 struct mlx5_ifc_create_qp_out_bits { 7657 u8 status[0x8]; 7658 u8 reserved_at_8[0x18]; 7659 7660 u8 syndrome[0x20]; 7661 7662 u8 reserved_at_40[0x8]; 7663 u8 qpn[0x18]; 7664 7665 u8 reserved_at_60[0x20]; 7666 }; 7667 7668 struct mlx5_ifc_create_qp_in_bits { 7669 u8 opcode[0x10]; 7670 u8 uid[0x10]; 7671 7672 u8 reserved_at_20[0x10]; 7673 u8 op_mod[0x10]; 7674 7675 u8 reserved_at_40[0x40]; 7676 7677 u8 opt_param_mask[0x20]; 7678 7679 u8 reserved_at_a0[0x20]; 7680 7681 struct mlx5_ifc_qpc_bits qpc; 7682 7683 u8 reserved_at_800[0x60]; 7684 7685 u8 wq_umem_valid[0x1]; 7686 u8 reserved_at_861[0x1f]; 7687 7688 u8 pas[0][0x40]; 7689 }; 7690 7691 struct mlx5_ifc_create_psv_out_bits { 7692 u8 status[0x8]; 7693 u8 reserved_at_8[0x18]; 7694 7695 u8 syndrome[0x20]; 7696 7697 u8 reserved_at_40[0x40]; 7698 7699 u8 reserved_at_80[0x8]; 7700 u8 psv0_index[0x18]; 7701 7702 u8 reserved_at_a0[0x8]; 7703 u8 psv1_index[0x18]; 7704 7705 u8 reserved_at_c0[0x8]; 7706 u8 psv2_index[0x18]; 7707 7708 u8 reserved_at_e0[0x8]; 7709 u8 psv3_index[0x18]; 7710 }; 7711 7712 struct mlx5_ifc_create_psv_in_bits { 7713 u8 opcode[0x10]; 7714 u8 reserved_at_10[0x10]; 7715 7716 u8 reserved_at_20[0x10]; 7717 u8 op_mod[0x10]; 7718 7719 u8 num_psv[0x4]; 7720 u8 reserved_at_44[0x4]; 7721 u8 pd[0x18]; 7722 7723 u8 reserved_at_60[0x20]; 7724 }; 7725 7726 struct mlx5_ifc_create_mkey_out_bits { 7727 u8 status[0x8]; 7728 u8 reserved_at_8[0x18]; 7729 7730 u8 syndrome[0x20]; 7731 7732 u8 reserved_at_40[0x8]; 7733 u8 mkey_index[0x18]; 7734 7735 u8 reserved_at_60[0x20]; 7736 }; 7737 7738 struct mlx5_ifc_create_mkey_in_bits { 7739 u8 opcode[0x10]; 7740 u8 reserved_at_10[0x10]; 7741 7742 u8 reserved_at_20[0x10]; 7743 u8 op_mod[0x10]; 7744 7745 u8 reserved_at_40[0x20]; 7746 7747 u8 pg_access[0x1]; 7748 u8 mkey_umem_valid[0x1]; 7749 u8 reserved_at_62[0x1e]; 7750 7751 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7752 7753 u8 reserved_at_280[0x80]; 7754 7755 u8 translations_octword_actual_size[0x20]; 7756 7757 u8 reserved_at_320[0x560]; 7758 7759 u8 klm_pas_mtt[0][0x20]; 7760 }; 7761 7762 enum { 7763 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7764 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7765 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7766 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7767 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7768 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7769 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7770 }; 7771 7772 struct mlx5_ifc_create_flow_table_out_bits { 7773 u8 status[0x8]; 7774 u8 icm_address_63_40[0x18]; 7775 7776 u8 syndrome[0x20]; 7777 7778 u8 icm_address_39_32[0x8]; 7779 u8 table_id[0x18]; 7780 7781 u8 icm_address_31_0[0x20]; 7782 }; 7783 7784 struct mlx5_ifc_create_flow_table_in_bits { 7785 u8 opcode[0x10]; 7786 u8 reserved_at_10[0x10]; 7787 7788 u8 reserved_at_20[0x10]; 7789 u8 op_mod[0x10]; 7790 7791 u8 other_vport[0x1]; 7792 u8 reserved_at_41[0xf]; 7793 u8 vport_number[0x10]; 7794 7795 u8 reserved_at_60[0x20]; 7796 7797 u8 table_type[0x8]; 7798 u8 reserved_at_88[0x18]; 7799 7800 u8 reserved_at_a0[0x20]; 7801 7802 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7803 }; 7804 7805 struct mlx5_ifc_create_flow_group_out_bits { 7806 u8 status[0x8]; 7807 u8 reserved_at_8[0x18]; 7808 7809 u8 syndrome[0x20]; 7810 7811 u8 reserved_at_40[0x8]; 7812 u8 group_id[0x18]; 7813 7814 u8 reserved_at_60[0x20]; 7815 }; 7816 7817 enum { 7818 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7819 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7820 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7821 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7822 }; 7823 7824 struct mlx5_ifc_create_flow_group_in_bits { 7825 u8 opcode[0x10]; 7826 u8 reserved_at_10[0x10]; 7827 7828 u8 reserved_at_20[0x10]; 7829 u8 op_mod[0x10]; 7830 7831 u8 other_vport[0x1]; 7832 u8 reserved_at_41[0xf]; 7833 u8 vport_number[0x10]; 7834 7835 u8 reserved_at_60[0x20]; 7836 7837 u8 table_type[0x8]; 7838 u8 reserved_at_88[0x18]; 7839 7840 u8 reserved_at_a0[0x8]; 7841 u8 table_id[0x18]; 7842 7843 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7844 7845 u8 reserved_at_c1[0x1f]; 7846 7847 u8 start_flow_index[0x20]; 7848 7849 u8 reserved_at_100[0x20]; 7850 7851 u8 end_flow_index[0x20]; 7852 7853 u8 reserved_at_140[0xa0]; 7854 7855 u8 reserved_at_1e0[0x18]; 7856 u8 match_criteria_enable[0x8]; 7857 7858 struct mlx5_ifc_fte_match_param_bits match_criteria; 7859 7860 u8 reserved_at_1200[0xe00]; 7861 }; 7862 7863 struct mlx5_ifc_create_eq_out_bits { 7864 u8 status[0x8]; 7865 u8 reserved_at_8[0x18]; 7866 7867 u8 syndrome[0x20]; 7868 7869 u8 reserved_at_40[0x18]; 7870 u8 eq_number[0x8]; 7871 7872 u8 reserved_at_60[0x20]; 7873 }; 7874 7875 struct mlx5_ifc_create_eq_in_bits { 7876 u8 opcode[0x10]; 7877 u8 uid[0x10]; 7878 7879 u8 reserved_at_20[0x10]; 7880 u8 op_mod[0x10]; 7881 7882 u8 reserved_at_40[0x40]; 7883 7884 struct mlx5_ifc_eqc_bits eq_context_entry; 7885 7886 u8 reserved_at_280[0x40]; 7887 7888 u8 event_bitmask[4][0x40]; 7889 7890 u8 reserved_at_3c0[0x4c0]; 7891 7892 u8 pas[0][0x40]; 7893 }; 7894 7895 struct mlx5_ifc_create_dct_out_bits { 7896 u8 status[0x8]; 7897 u8 reserved_at_8[0x18]; 7898 7899 u8 syndrome[0x20]; 7900 7901 u8 reserved_at_40[0x8]; 7902 u8 dctn[0x18]; 7903 7904 u8 reserved_at_60[0x20]; 7905 }; 7906 7907 struct mlx5_ifc_create_dct_in_bits { 7908 u8 opcode[0x10]; 7909 u8 uid[0x10]; 7910 7911 u8 reserved_at_20[0x10]; 7912 u8 op_mod[0x10]; 7913 7914 u8 reserved_at_40[0x40]; 7915 7916 struct mlx5_ifc_dctc_bits dct_context_entry; 7917 7918 u8 reserved_at_280[0x180]; 7919 }; 7920 7921 struct mlx5_ifc_create_cq_out_bits { 7922 u8 status[0x8]; 7923 u8 reserved_at_8[0x18]; 7924 7925 u8 syndrome[0x20]; 7926 7927 u8 reserved_at_40[0x8]; 7928 u8 cqn[0x18]; 7929 7930 u8 reserved_at_60[0x20]; 7931 }; 7932 7933 struct mlx5_ifc_create_cq_in_bits { 7934 u8 opcode[0x10]; 7935 u8 uid[0x10]; 7936 7937 u8 reserved_at_20[0x10]; 7938 u8 op_mod[0x10]; 7939 7940 u8 reserved_at_40[0x40]; 7941 7942 struct mlx5_ifc_cqc_bits cq_context; 7943 7944 u8 reserved_at_280[0x60]; 7945 7946 u8 cq_umem_valid[0x1]; 7947 u8 reserved_at_2e1[0x59f]; 7948 7949 u8 pas[0][0x40]; 7950 }; 7951 7952 struct mlx5_ifc_config_int_moderation_out_bits { 7953 u8 status[0x8]; 7954 u8 reserved_at_8[0x18]; 7955 7956 u8 syndrome[0x20]; 7957 7958 u8 reserved_at_40[0x4]; 7959 u8 min_delay[0xc]; 7960 u8 int_vector[0x10]; 7961 7962 u8 reserved_at_60[0x20]; 7963 }; 7964 7965 enum { 7966 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7967 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7968 }; 7969 7970 struct mlx5_ifc_config_int_moderation_in_bits { 7971 u8 opcode[0x10]; 7972 u8 reserved_at_10[0x10]; 7973 7974 u8 reserved_at_20[0x10]; 7975 u8 op_mod[0x10]; 7976 7977 u8 reserved_at_40[0x4]; 7978 u8 min_delay[0xc]; 7979 u8 int_vector[0x10]; 7980 7981 u8 reserved_at_60[0x20]; 7982 }; 7983 7984 struct mlx5_ifc_attach_to_mcg_out_bits { 7985 u8 status[0x8]; 7986 u8 reserved_at_8[0x18]; 7987 7988 u8 syndrome[0x20]; 7989 7990 u8 reserved_at_40[0x40]; 7991 }; 7992 7993 struct mlx5_ifc_attach_to_mcg_in_bits { 7994 u8 opcode[0x10]; 7995 u8 uid[0x10]; 7996 7997 u8 reserved_at_20[0x10]; 7998 u8 op_mod[0x10]; 7999 8000 u8 reserved_at_40[0x8]; 8001 u8 qpn[0x18]; 8002 8003 u8 reserved_at_60[0x20]; 8004 8005 u8 multicast_gid[16][0x8]; 8006 }; 8007 8008 struct mlx5_ifc_arm_xrq_out_bits { 8009 u8 status[0x8]; 8010 u8 reserved_at_8[0x18]; 8011 8012 u8 syndrome[0x20]; 8013 8014 u8 reserved_at_40[0x40]; 8015 }; 8016 8017 struct mlx5_ifc_arm_xrq_in_bits { 8018 u8 opcode[0x10]; 8019 u8 reserved_at_10[0x10]; 8020 8021 u8 reserved_at_20[0x10]; 8022 u8 op_mod[0x10]; 8023 8024 u8 reserved_at_40[0x8]; 8025 u8 xrqn[0x18]; 8026 8027 u8 reserved_at_60[0x10]; 8028 u8 lwm[0x10]; 8029 }; 8030 8031 struct mlx5_ifc_arm_xrc_srq_out_bits { 8032 u8 status[0x8]; 8033 u8 reserved_at_8[0x18]; 8034 8035 u8 syndrome[0x20]; 8036 8037 u8 reserved_at_40[0x40]; 8038 }; 8039 8040 enum { 8041 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8042 }; 8043 8044 struct mlx5_ifc_arm_xrc_srq_in_bits { 8045 u8 opcode[0x10]; 8046 u8 uid[0x10]; 8047 8048 u8 reserved_at_20[0x10]; 8049 u8 op_mod[0x10]; 8050 8051 u8 reserved_at_40[0x8]; 8052 u8 xrc_srqn[0x18]; 8053 8054 u8 reserved_at_60[0x10]; 8055 u8 lwm[0x10]; 8056 }; 8057 8058 struct mlx5_ifc_arm_rq_out_bits { 8059 u8 status[0x8]; 8060 u8 reserved_at_8[0x18]; 8061 8062 u8 syndrome[0x20]; 8063 8064 u8 reserved_at_40[0x40]; 8065 }; 8066 8067 enum { 8068 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8069 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8070 }; 8071 8072 struct mlx5_ifc_arm_rq_in_bits { 8073 u8 opcode[0x10]; 8074 u8 uid[0x10]; 8075 8076 u8 reserved_at_20[0x10]; 8077 u8 op_mod[0x10]; 8078 8079 u8 reserved_at_40[0x8]; 8080 u8 srq_number[0x18]; 8081 8082 u8 reserved_at_60[0x10]; 8083 u8 lwm[0x10]; 8084 }; 8085 8086 struct mlx5_ifc_arm_dct_out_bits { 8087 u8 status[0x8]; 8088 u8 reserved_at_8[0x18]; 8089 8090 u8 syndrome[0x20]; 8091 8092 u8 reserved_at_40[0x40]; 8093 }; 8094 8095 struct mlx5_ifc_arm_dct_in_bits { 8096 u8 opcode[0x10]; 8097 u8 reserved_at_10[0x10]; 8098 8099 u8 reserved_at_20[0x10]; 8100 u8 op_mod[0x10]; 8101 8102 u8 reserved_at_40[0x8]; 8103 u8 dct_number[0x18]; 8104 8105 u8 reserved_at_60[0x20]; 8106 }; 8107 8108 struct mlx5_ifc_alloc_xrcd_out_bits { 8109 u8 status[0x8]; 8110 u8 reserved_at_8[0x18]; 8111 8112 u8 syndrome[0x20]; 8113 8114 u8 reserved_at_40[0x8]; 8115 u8 xrcd[0x18]; 8116 8117 u8 reserved_at_60[0x20]; 8118 }; 8119 8120 struct mlx5_ifc_alloc_xrcd_in_bits { 8121 u8 opcode[0x10]; 8122 u8 uid[0x10]; 8123 8124 u8 reserved_at_20[0x10]; 8125 u8 op_mod[0x10]; 8126 8127 u8 reserved_at_40[0x40]; 8128 }; 8129 8130 struct mlx5_ifc_alloc_uar_out_bits { 8131 u8 status[0x8]; 8132 u8 reserved_at_8[0x18]; 8133 8134 u8 syndrome[0x20]; 8135 8136 u8 reserved_at_40[0x8]; 8137 u8 uar[0x18]; 8138 8139 u8 reserved_at_60[0x20]; 8140 }; 8141 8142 struct mlx5_ifc_alloc_uar_in_bits { 8143 u8 opcode[0x10]; 8144 u8 reserved_at_10[0x10]; 8145 8146 u8 reserved_at_20[0x10]; 8147 u8 op_mod[0x10]; 8148 8149 u8 reserved_at_40[0x40]; 8150 }; 8151 8152 struct mlx5_ifc_alloc_transport_domain_out_bits { 8153 u8 status[0x8]; 8154 u8 reserved_at_8[0x18]; 8155 8156 u8 syndrome[0x20]; 8157 8158 u8 reserved_at_40[0x8]; 8159 u8 transport_domain[0x18]; 8160 8161 u8 reserved_at_60[0x20]; 8162 }; 8163 8164 struct mlx5_ifc_alloc_transport_domain_in_bits { 8165 u8 opcode[0x10]; 8166 u8 uid[0x10]; 8167 8168 u8 reserved_at_20[0x10]; 8169 u8 op_mod[0x10]; 8170 8171 u8 reserved_at_40[0x40]; 8172 }; 8173 8174 struct mlx5_ifc_alloc_q_counter_out_bits { 8175 u8 status[0x8]; 8176 u8 reserved_at_8[0x18]; 8177 8178 u8 syndrome[0x20]; 8179 8180 u8 reserved_at_40[0x18]; 8181 u8 counter_set_id[0x8]; 8182 8183 u8 reserved_at_60[0x20]; 8184 }; 8185 8186 struct mlx5_ifc_alloc_q_counter_in_bits { 8187 u8 opcode[0x10]; 8188 u8 uid[0x10]; 8189 8190 u8 reserved_at_20[0x10]; 8191 u8 op_mod[0x10]; 8192 8193 u8 reserved_at_40[0x40]; 8194 }; 8195 8196 struct mlx5_ifc_alloc_pd_out_bits { 8197 u8 status[0x8]; 8198 u8 reserved_at_8[0x18]; 8199 8200 u8 syndrome[0x20]; 8201 8202 u8 reserved_at_40[0x8]; 8203 u8 pd[0x18]; 8204 8205 u8 reserved_at_60[0x20]; 8206 }; 8207 8208 struct mlx5_ifc_alloc_pd_in_bits { 8209 u8 opcode[0x10]; 8210 u8 uid[0x10]; 8211 8212 u8 reserved_at_20[0x10]; 8213 u8 op_mod[0x10]; 8214 8215 u8 reserved_at_40[0x40]; 8216 }; 8217 8218 struct mlx5_ifc_alloc_flow_counter_out_bits { 8219 u8 status[0x8]; 8220 u8 reserved_at_8[0x18]; 8221 8222 u8 syndrome[0x20]; 8223 8224 u8 flow_counter_id[0x20]; 8225 8226 u8 reserved_at_60[0x20]; 8227 }; 8228 8229 struct mlx5_ifc_alloc_flow_counter_in_bits { 8230 u8 opcode[0x10]; 8231 u8 reserved_at_10[0x10]; 8232 8233 u8 reserved_at_20[0x10]; 8234 u8 op_mod[0x10]; 8235 8236 u8 reserved_at_40[0x38]; 8237 u8 flow_counter_bulk[0x8]; 8238 }; 8239 8240 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8241 u8 status[0x8]; 8242 u8 reserved_at_8[0x18]; 8243 8244 u8 syndrome[0x20]; 8245 8246 u8 reserved_at_40[0x40]; 8247 }; 8248 8249 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8250 u8 opcode[0x10]; 8251 u8 reserved_at_10[0x10]; 8252 8253 u8 reserved_at_20[0x10]; 8254 u8 op_mod[0x10]; 8255 8256 u8 reserved_at_40[0x20]; 8257 8258 u8 reserved_at_60[0x10]; 8259 u8 vxlan_udp_port[0x10]; 8260 }; 8261 8262 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8263 u8 status[0x8]; 8264 u8 reserved_at_8[0x18]; 8265 8266 u8 syndrome[0x20]; 8267 8268 u8 reserved_at_40[0x40]; 8269 }; 8270 8271 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8272 u8 rate_limit[0x20]; 8273 8274 u8 burst_upper_bound[0x20]; 8275 8276 u8 reserved_at_40[0x10]; 8277 u8 typical_packet_size[0x10]; 8278 8279 u8 reserved_at_60[0x120]; 8280 }; 8281 8282 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8283 u8 opcode[0x10]; 8284 u8 uid[0x10]; 8285 8286 u8 reserved_at_20[0x10]; 8287 u8 op_mod[0x10]; 8288 8289 u8 reserved_at_40[0x10]; 8290 u8 rate_limit_index[0x10]; 8291 8292 u8 reserved_at_60[0x20]; 8293 8294 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8295 }; 8296 8297 struct mlx5_ifc_access_register_out_bits { 8298 u8 status[0x8]; 8299 u8 reserved_at_8[0x18]; 8300 8301 u8 syndrome[0x20]; 8302 8303 u8 reserved_at_40[0x40]; 8304 8305 u8 register_data[0][0x20]; 8306 }; 8307 8308 enum { 8309 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8310 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8311 }; 8312 8313 struct mlx5_ifc_access_register_in_bits { 8314 u8 opcode[0x10]; 8315 u8 reserved_at_10[0x10]; 8316 8317 u8 reserved_at_20[0x10]; 8318 u8 op_mod[0x10]; 8319 8320 u8 reserved_at_40[0x10]; 8321 u8 register_id[0x10]; 8322 8323 u8 argument[0x20]; 8324 8325 u8 register_data[0][0x20]; 8326 }; 8327 8328 struct mlx5_ifc_sltp_reg_bits { 8329 u8 status[0x4]; 8330 u8 version[0x4]; 8331 u8 local_port[0x8]; 8332 u8 pnat[0x2]; 8333 u8 reserved_at_12[0x2]; 8334 u8 lane[0x4]; 8335 u8 reserved_at_18[0x8]; 8336 8337 u8 reserved_at_20[0x20]; 8338 8339 u8 reserved_at_40[0x7]; 8340 u8 polarity[0x1]; 8341 u8 ob_tap0[0x8]; 8342 u8 ob_tap1[0x8]; 8343 u8 ob_tap2[0x8]; 8344 8345 u8 reserved_at_60[0xc]; 8346 u8 ob_preemp_mode[0x4]; 8347 u8 ob_reg[0x8]; 8348 u8 ob_bias[0x8]; 8349 8350 u8 reserved_at_80[0x20]; 8351 }; 8352 8353 struct mlx5_ifc_slrg_reg_bits { 8354 u8 status[0x4]; 8355 u8 version[0x4]; 8356 u8 local_port[0x8]; 8357 u8 pnat[0x2]; 8358 u8 reserved_at_12[0x2]; 8359 u8 lane[0x4]; 8360 u8 reserved_at_18[0x8]; 8361 8362 u8 time_to_link_up[0x10]; 8363 u8 reserved_at_30[0xc]; 8364 u8 grade_lane_speed[0x4]; 8365 8366 u8 grade_version[0x8]; 8367 u8 grade[0x18]; 8368 8369 u8 reserved_at_60[0x4]; 8370 u8 height_grade_type[0x4]; 8371 u8 height_grade[0x18]; 8372 8373 u8 height_dz[0x10]; 8374 u8 height_dv[0x10]; 8375 8376 u8 reserved_at_a0[0x10]; 8377 u8 height_sigma[0x10]; 8378 8379 u8 reserved_at_c0[0x20]; 8380 8381 u8 reserved_at_e0[0x4]; 8382 u8 phase_grade_type[0x4]; 8383 u8 phase_grade[0x18]; 8384 8385 u8 reserved_at_100[0x8]; 8386 u8 phase_eo_pos[0x8]; 8387 u8 reserved_at_110[0x8]; 8388 u8 phase_eo_neg[0x8]; 8389 8390 u8 ffe_set_tested[0x10]; 8391 u8 test_errors_per_lane[0x10]; 8392 }; 8393 8394 struct mlx5_ifc_pvlc_reg_bits { 8395 u8 reserved_at_0[0x8]; 8396 u8 local_port[0x8]; 8397 u8 reserved_at_10[0x10]; 8398 8399 u8 reserved_at_20[0x1c]; 8400 u8 vl_hw_cap[0x4]; 8401 8402 u8 reserved_at_40[0x1c]; 8403 u8 vl_admin[0x4]; 8404 8405 u8 reserved_at_60[0x1c]; 8406 u8 vl_operational[0x4]; 8407 }; 8408 8409 struct mlx5_ifc_pude_reg_bits { 8410 u8 swid[0x8]; 8411 u8 local_port[0x8]; 8412 u8 reserved_at_10[0x4]; 8413 u8 admin_status[0x4]; 8414 u8 reserved_at_18[0x4]; 8415 u8 oper_status[0x4]; 8416 8417 u8 reserved_at_20[0x60]; 8418 }; 8419 8420 struct mlx5_ifc_ptys_reg_bits { 8421 u8 reserved_at_0[0x1]; 8422 u8 an_disable_admin[0x1]; 8423 u8 an_disable_cap[0x1]; 8424 u8 reserved_at_3[0x5]; 8425 u8 local_port[0x8]; 8426 u8 reserved_at_10[0xd]; 8427 u8 proto_mask[0x3]; 8428 8429 u8 an_status[0x4]; 8430 u8 reserved_at_24[0xc]; 8431 u8 data_rate_oper[0x10]; 8432 8433 u8 ext_eth_proto_capability[0x20]; 8434 8435 u8 eth_proto_capability[0x20]; 8436 8437 u8 ib_link_width_capability[0x10]; 8438 u8 ib_proto_capability[0x10]; 8439 8440 u8 ext_eth_proto_admin[0x20]; 8441 8442 u8 eth_proto_admin[0x20]; 8443 8444 u8 ib_link_width_admin[0x10]; 8445 u8 ib_proto_admin[0x10]; 8446 8447 u8 ext_eth_proto_oper[0x20]; 8448 8449 u8 eth_proto_oper[0x20]; 8450 8451 u8 ib_link_width_oper[0x10]; 8452 u8 ib_proto_oper[0x10]; 8453 8454 u8 reserved_at_160[0x1c]; 8455 u8 connector_type[0x4]; 8456 8457 u8 eth_proto_lp_advertise[0x20]; 8458 8459 u8 reserved_at_1a0[0x60]; 8460 }; 8461 8462 struct mlx5_ifc_mlcr_reg_bits { 8463 u8 reserved_at_0[0x8]; 8464 u8 local_port[0x8]; 8465 u8 reserved_at_10[0x20]; 8466 8467 u8 beacon_duration[0x10]; 8468 u8 reserved_at_40[0x10]; 8469 8470 u8 beacon_remain[0x10]; 8471 }; 8472 8473 struct mlx5_ifc_ptas_reg_bits { 8474 u8 reserved_at_0[0x20]; 8475 8476 u8 algorithm_options[0x10]; 8477 u8 reserved_at_30[0x4]; 8478 u8 repetitions_mode[0x4]; 8479 u8 num_of_repetitions[0x8]; 8480 8481 u8 grade_version[0x8]; 8482 u8 height_grade_type[0x4]; 8483 u8 phase_grade_type[0x4]; 8484 u8 height_grade_weight[0x8]; 8485 u8 phase_grade_weight[0x8]; 8486 8487 u8 gisim_measure_bits[0x10]; 8488 u8 adaptive_tap_measure_bits[0x10]; 8489 8490 u8 ber_bath_high_error_threshold[0x10]; 8491 u8 ber_bath_mid_error_threshold[0x10]; 8492 8493 u8 ber_bath_low_error_threshold[0x10]; 8494 u8 one_ratio_high_threshold[0x10]; 8495 8496 u8 one_ratio_high_mid_threshold[0x10]; 8497 u8 one_ratio_low_mid_threshold[0x10]; 8498 8499 u8 one_ratio_low_threshold[0x10]; 8500 u8 ndeo_error_threshold[0x10]; 8501 8502 u8 mixer_offset_step_size[0x10]; 8503 u8 reserved_at_110[0x8]; 8504 u8 mix90_phase_for_voltage_bath[0x8]; 8505 8506 u8 mixer_offset_start[0x10]; 8507 u8 mixer_offset_end[0x10]; 8508 8509 u8 reserved_at_140[0x15]; 8510 u8 ber_test_time[0xb]; 8511 }; 8512 8513 struct mlx5_ifc_pspa_reg_bits { 8514 u8 swid[0x8]; 8515 u8 local_port[0x8]; 8516 u8 sub_port[0x8]; 8517 u8 reserved_at_18[0x8]; 8518 8519 u8 reserved_at_20[0x20]; 8520 }; 8521 8522 struct mlx5_ifc_pqdr_reg_bits { 8523 u8 reserved_at_0[0x8]; 8524 u8 local_port[0x8]; 8525 u8 reserved_at_10[0x5]; 8526 u8 prio[0x3]; 8527 u8 reserved_at_18[0x6]; 8528 u8 mode[0x2]; 8529 8530 u8 reserved_at_20[0x20]; 8531 8532 u8 reserved_at_40[0x10]; 8533 u8 min_threshold[0x10]; 8534 8535 u8 reserved_at_60[0x10]; 8536 u8 max_threshold[0x10]; 8537 8538 u8 reserved_at_80[0x10]; 8539 u8 mark_probability_denominator[0x10]; 8540 8541 u8 reserved_at_a0[0x60]; 8542 }; 8543 8544 struct mlx5_ifc_ppsc_reg_bits { 8545 u8 reserved_at_0[0x8]; 8546 u8 local_port[0x8]; 8547 u8 reserved_at_10[0x10]; 8548 8549 u8 reserved_at_20[0x60]; 8550 8551 u8 reserved_at_80[0x1c]; 8552 u8 wrps_admin[0x4]; 8553 8554 u8 reserved_at_a0[0x1c]; 8555 u8 wrps_status[0x4]; 8556 8557 u8 reserved_at_c0[0x8]; 8558 u8 up_threshold[0x8]; 8559 u8 reserved_at_d0[0x8]; 8560 u8 down_threshold[0x8]; 8561 8562 u8 reserved_at_e0[0x20]; 8563 8564 u8 reserved_at_100[0x1c]; 8565 u8 srps_admin[0x4]; 8566 8567 u8 reserved_at_120[0x1c]; 8568 u8 srps_status[0x4]; 8569 8570 u8 reserved_at_140[0x40]; 8571 }; 8572 8573 struct mlx5_ifc_pplr_reg_bits { 8574 u8 reserved_at_0[0x8]; 8575 u8 local_port[0x8]; 8576 u8 reserved_at_10[0x10]; 8577 8578 u8 reserved_at_20[0x8]; 8579 u8 lb_cap[0x8]; 8580 u8 reserved_at_30[0x8]; 8581 u8 lb_en[0x8]; 8582 }; 8583 8584 struct mlx5_ifc_pplm_reg_bits { 8585 u8 reserved_at_0[0x8]; 8586 u8 local_port[0x8]; 8587 u8 reserved_at_10[0x10]; 8588 8589 u8 reserved_at_20[0x20]; 8590 8591 u8 port_profile_mode[0x8]; 8592 u8 static_port_profile[0x8]; 8593 u8 active_port_profile[0x8]; 8594 u8 reserved_at_58[0x8]; 8595 8596 u8 retransmission_active[0x8]; 8597 u8 fec_mode_active[0x18]; 8598 8599 u8 rs_fec_correction_bypass_cap[0x4]; 8600 u8 reserved_at_84[0x8]; 8601 u8 fec_override_cap_56g[0x4]; 8602 u8 fec_override_cap_100g[0x4]; 8603 u8 fec_override_cap_50g[0x4]; 8604 u8 fec_override_cap_25g[0x4]; 8605 u8 fec_override_cap_10g_40g[0x4]; 8606 8607 u8 rs_fec_correction_bypass_admin[0x4]; 8608 u8 reserved_at_a4[0x8]; 8609 u8 fec_override_admin_56g[0x4]; 8610 u8 fec_override_admin_100g[0x4]; 8611 u8 fec_override_admin_50g[0x4]; 8612 u8 fec_override_admin_25g[0x4]; 8613 u8 fec_override_admin_10g_40g[0x4]; 8614 8615 u8 fec_override_cap_400g_8x[0x10]; 8616 u8 fec_override_cap_200g_4x[0x10]; 8617 8618 u8 fec_override_cap_100g_2x[0x10]; 8619 u8 fec_override_cap_50g_1x[0x10]; 8620 8621 u8 fec_override_admin_400g_8x[0x10]; 8622 u8 fec_override_admin_200g_4x[0x10]; 8623 8624 u8 fec_override_admin_100g_2x[0x10]; 8625 u8 fec_override_admin_50g_1x[0x10]; 8626 }; 8627 8628 struct mlx5_ifc_ppcnt_reg_bits { 8629 u8 swid[0x8]; 8630 u8 local_port[0x8]; 8631 u8 pnat[0x2]; 8632 u8 reserved_at_12[0x8]; 8633 u8 grp[0x6]; 8634 8635 u8 clr[0x1]; 8636 u8 reserved_at_21[0x1c]; 8637 u8 prio_tc[0x3]; 8638 8639 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8640 }; 8641 8642 struct mlx5_ifc_mpein_reg_bits { 8643 u8 reserved_at_0[0x2]; 8644 u8 depth[0x6]; 8645 u8 pcie_index[0x8]; 8646 u8 node[0x8]; 8647 u8 reserved_at_18[0x8]; 8648 8649 u8 capability_mask[0x20]; 8650 8651 u8 reserved_at_40[0x8]; 8652 u8 link_width_enabled[0x8]; 8653 u8 link_speed_enabled[0x10]; 8654 8655 u8 lane0_physical_position[0x8]; 8656 u8 link_width_active[0x8]; 8657 u8 link_speed_active[0x10]; 8658 8659 u8 num_of_pfs[0x10]; 8660 u8 num_of_vfs[0x10]; 8661 8662 u8 bdf0[0x10]; 8663 u8 reserved_at_b0[0x10]; 8664 8665 u8 max_read_request_size[0x4]; 8666 u8 max_payload_size[0x4]; 8667 u8 reserved_at_c8[0x5]; 8668 u8 pwr_status[0x3]; 8669 u8 port_type[0x4]; 8670 u8 reserved_at_d4[0xb]; 8671 u8 lane_reversal[0x1]; 8672 8673 u8 reserved_at_e0[0x14]; 8674 u8 pci_power[0xc]; 8675 8676 u8 reserved_at_100[0x20]; 8677 8678 u8 device_status[0x10]; 8679 u8 port_state[0x8]; 8680 u8 reserved_at_138[0x8]; 8681 8682 u8 reserved_at_140[0x10]; 8683 u8 receiver_detect_result[0x10]; 8684 8685 u8 reserved_at_160[0x20]; 8686 }; 8687 8688 struct mlx5_ifc_mpcnt_reg_bits { 8689 u8 reserved_at_0[0x8]; 8690 u8 pcie_index[0x8]; 8691 u8 reserved_at_10[0xa]; 8692 u8 grp[0x6]; 8693 8694 u8 clr[0x1]; 8695 u8 reserved_at_21[0x1f]; 8696 8697 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8698 }; 8699 8700 struct mlx5_ifc_ppad_reg_bits { 8701 u8 reserved_at_0[0x3]; 8702 u8 single_mac[0x1]; 8703 u8 reserved_at_4[0x4]; 8704 u8 local_port[0x8]; 8705 u8 mac_47_32[0x10]; 8706 8707 u8 mac_31_0[0x20]; 8708 8709 u8 reserved_at_40[0x40]; 8710 }; 8711 8712 struct mlx5_ifc_pmtu_reg_bits { 8713 u8 reserved_at_0[0x8]; 8714 u8 local_port[0x8]; 8715 u8 reserved_at_10[0x10]; 8716 8717 u8 max_mtu[0x10]; 8718 u8 reserved_at_30[0x10]; 8719 8720 u8 admin_mtu[0x10]; 8721 u8 reserved_at_50[0x10]; 8722 8723 u8 oper_mtu[0x10]; 8724 u8 reserved_at_70[0x10]; 8725 }; 8726 8727 struct mlx5_ifc_pmpr_reg_bits { 8728 u8 reserved_at_0[0x8]; 8729 u8 module[0x8]; 8730 u8 reserved_at_10[0x10]; 8731 8732 u8 reserved_at_20[0x18]; 8733 u8 attenuation_5g[0x8]; 8734 8735 u8 reserved_at_40[0x18]; 8736 u8 attenuation_7g[0x8]; 8737 8738 u8 reserved_at_60[0x18]; 8739 u8 attenuation_12g[0x8]; 8740 }; 8741 8742 struct mlx5_ifc_pmpe_reg_bits { 8743 u8 reserved_at_0[0x8]; 8744 u8 module[0x8]; 8745 u8 reserved_at_10[0xc]; 8746 u8 module_status[0x4]; 8747 8748 u8 reserved_at_20[0x60]; 8749 }; 8750 8751 struct mlx5_ifc_pmpc_reg_bits { 8752 u8 module_state_updated[32][0x8]; 8753 }; 8754 8755 struct mlx5_ifc_pmlpn_reg_bits { 8756 u8 reserved_at_0[0x4]; 8757 u8 mlpn_status[0x4]; 8758 u8 local_port[0x8]; 8759 u8 reserved_at_10[0x10]; 8760 8761 u8 e[0x1]; 8762 u8 reserved_at_21[0x1f]; 8763 }; 8764 8765 struct mlx5_ifc_pmlp_reg_bits { 8766 u8 rxtx[0x1]; 8767 u8 reserved_at_1[0x7]; 8768 u8 local_port[0x8]; 8769 u8 reserved_at_10[0x8]; 8770 u8 width[0x8]; 8771 8772 u8 lane0_module_mapping[0x20]; 8773 8774 u8 lane1_module_mapping[0x20]; 8775 8776 u8 lane2_module_mapping[0x20]; 8777 8778 u8 lane3_module_mapping[0x20]; 8779 8780 u8 reserved_at_a0[0x160]; 8781 }; 8782 8783 struct mlx5_ifc_pmaos_reg_bits { 8784 u8 reserved_at_0[0x8]; 8785 u8 module[0x8]; 8786 u8 reserved_at_10[0x4]; 8787 u8 admin_status[0x4]; 8788 u8 reserved_at_18[0x4]; 8789 u8 oper_status[0x4]; 8790 8791 u8 ase[0x1]; 8792 u8 ee[0x1]; 8793 u8 reserved_at_22[0x1c]; 8794 u8 e[0x2]; 8795 8796 u8 reserved_at_40[0x40]; 8797 }; 8798 8799 struct mlx5_ifc_plpc_reg_bits { 8800 u8 reserved_at_0[0x4]; 8801 u8 profile_id[0xc]; 8802 u8 reserved_at_10[0x4]; 8803 u8 proto_mask[0x4]; 8804 u8 reserved_at_18[0x8]; 8805 8806 u8 reserved_at_20[0x10]; 8807 u8 lane_speed[0x10]; 8808 8809 u8 reserved_at_40[0x17]; 8810 u8 lpbf[0x1]; 8811 u8 fec_mode_policy[0x8]; 8812 8813 u8 retransmission_capability[0x8]; 8814 u8 fec_mode_capability[0x18]; 8815 8816 u8 retransmission_support_admin[0x8]; 8817 u8 fec_mode_support_admin[0x18]; 8818 8819 u8 retransmission_request_admin[0x8]; 8820 u8 fec_mode_request_admin[0x18]; 8821 8822 u8 reserved_at_c0[0x80]; 8823 }; 8824 8825 struct mlx5_ifc_plib_reg_bits { 8826 u8 reserved_at_0[0x8]; 8827 u8 local_port[0x8]; 8828 u8 reserved_at_10[0x8]; 8829 u8 ib_port[0x8]; 8830 8831 u8 reserved_at_20[0x60]; 8832 }; 8833 8834 struct mlx5_ifc_plbf_reg_bits { 8835 u8 reserved_at_0[0x8]; 8836 u8 local_port[0x8]; 8837 u8 reserved_at_10[0xd]; 8838 u8 lbf_mode[0x3]; 8839 8840 u8 reserved_at_20[0x20]; 8841 }; 8842 8843 struct mlx5_ifc_pipg_reg_bits { 8844 u8 reserved_at_0[0x8]; 8845 u8 local_port[0x8]; 8846 u8 reserved_at_10[0x10]; 8847 8848 u8 dic[0x1]; 8849 u8 reserved_at_21[0x19]; 8850 u8 ipg[0x4]; 8851 u8 reserved_at_3e[0x2]; 8852 }; 8853 8854 struct mlx5_ifc_pifr_reg_bits { 8855 u8 reserved_at_0[0x8]; 8856 u8 local_port[0x8]; 8857 u8 reserved_at_10[0x10]; 8858 8859 u8 reserved_at_20[0xe0]; 8860 8861 u8 port_filter[8][0x20]; 8862 8863 u8 port_filter_update_en[8][0x20]; 8864 }; 8865 8866 struct mlx5_ifc_pfcc_reg_bits { 8867 u8 reserved_at_0[0x8]; 8868 u8 local_port[0x8]; 8869 u8 reserved_at_10[0xb]; 8870 u8 ppan_mask_n[0x1]; 8871 u8 minor_stall_mask[0x1]; 8872 u8 critical_stall_mask[0x1]; 8873 u8 reserved_at_1e[0x2]; 8874 8875 u8 ppan[0x4]; 8876 u8 reserved_at_24[0x4]; 8877 u8 prio_mask_tx[0x8]; 8878 u8 reserved_at_30[0x8]; 8879 u8 prio_mask_rx[0x8]; 8880 8881 u8 pptx[0x1]; 8882 u8 aptx[0x1]; 8883 u8 pptx_mask_n[0x1]; 8884 u8 reserved_at_43[0x5]; 8885 u8 pfctx[0x8]; 8886 u8 reserved_at_50[0x10]; 8887 8888 u8 pprx[0x1]; 8889 u8 aprx[0x1]; 8890 u8 pprx_mask_n[0x1]; 8891 u8 reserved_at_63[0x5]; 8892 u8 pfcrx[0x8]; 8893 u8 reserved_at_70[0x10]; 8894 8895 u8 device_stall_minor_watermark[0x10]; 8896 u8 device_stall_critical_watermark[0x10]; 8897 8898 u8 reserved_at_a0[0x60]; 8899 }; 8900 8901 struct mlx5_ifc_pelc_reg_bits { 8902 u8 op[0x4]; 8903 u8 reserved_at_4[0x4]; 8904 u8 local_port[0x8]; 8905 u8 reserved_at_10[0x10]; 8906 8907 u8 op_admin[0x8]; 8908 u8 op_capability[0x8]; 8909 u8 op_request[0x8]; 8910 u8 op_active[0x8]; 8911 8912 u8 admin[0x40]; 8913 8914 u8 capability[0x40]; 8915 8916 u8 request[0x40]; 8917 8918 u8 active[0x40]; 8919 8920 u8 reserved_at_140[0x80]; 8921 }; 8922 8923 struct mlx5_ifc_peir_reg_bits { 8924 u8 reserved_at_0[0x8]; 8925 u8 local_port[0x8]; 8926 u8 reserved_at_10[0x10]; 8927 8928 u8 reserved_at_20[0xc]; 8929 u8 error_count[0x4]; 8930 u8 reserved_at_30[0x10]; 8931 8932 u8 reserved_at_40[0xc]; 8933 u8 lane[0x4]; 8934 u8 reserved_at_50[0x8]; 8935 u8 error_type[0x8]; 8936 }; 8937 8938 struct mlx5_ifc_mpegc_reg_bits { 8939 u8 reserved_at_0[0x30]; 8940 u8 field_select[0x10]; 8941 8942 u8 tx_overflow_sense[0x1]; 8943 u8 mark_cqe[0x1]; 8944 u8 mark_cnp[0x1]; 8945 u8 reserved_at_43[0x1b]; 8946 u8 tx_lossy_overflow_oper[0x2]; 8947 8948 u8 reserved_at_60[0x100]; 8949 }; 8950 8951 struct mlx5_ifc_pcam_enhanced_features_bits { 8952 u8 reserved_at_0[0x68]; 8953 u8 fec_50G_per_lane_in_pplm[0x1]; 8954 u8 reserved_at_69[0x4]; 8955 u8 rx_icrc_encapsulated_counter[0x1]; 8956 u8 reserved_at_6e[0x4]; 8957 u8 ptys_extended_ethernet[0x1]; 8958 u8 reserved_at_73[0x3]; 8959 u8 pfcc_mask[0x1]; 8960 u8 reserved_at_77[0x3]; 8961 u8 per_lane_error_counters[0x1]; 8962 u8 rx_buffer_fullness_counters[0x1]; 8963 u8 ptys_connector_type[0x1]; 8964 u8 reserved_at_7d[0x1]; 8965 u8 ppcnt_discard_group[0x1]; 8966 u8 ppcnt_statistical_group[0x1]; 8967 }; 8968 8969 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8970 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8971 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8972 8973 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8974 u8 pplm[0x1]; 8975 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8976 8977 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8978 u8 pbmc[0x1]; 8979 u8 pptb[0x1]; 8980 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8981 u8 ppcnt[0x1]; 8982 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8983 }; 8984 8985 struct mlx5_ifc_pcam_reg_bits { 8986 u8 reserved_at_0[0x8]; 8987 u8 feature_group[0x8]; 8988 u8 reserved_at_10[0x8]; 8989 u8 access_reg_group[0x8]; 8990 8991 u8 reserved_at_20[0x20]; 8992 8993 union { 8994 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8995 u8 reserved_at_0[0x80]; 8996 } port_access_reg_cap_mask; 8997 8998 u8 reserved_at_c0[0x80]; 8999 9000 union { 9001 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9002 u8 reserved_at_0[0x80]; 9003 } feature_cap_mask; 9004 9005 u8 reserved_at_1c0[0xc0]; 9006 }; 9007 9008 struct mlx5_ifc_mcam_enhanced_features_bits { 9009 u8 reserved_at_0[0x6e]; 9010 u8 pci_status_and_power[0x1]; 9011 u8 reserved_at_6f[0x5]; 9012 u8 mark_tx_action_cnp[0x1]; 9013 u8 mark_tx_action_cqe[0x1]; 9014 u8 dynamic_tx_overflow[0x1]; 9015 u8 reserved_at_77[0x4]; 9016 u8 pcie_outbound_stalled[0x1]; 9017 u8 tx_overflow_buffer_pkt[0x1]; 9018 u8 mtpps_enh_out_per_adj[0x1]; 9019 u8 mtpps_fs[0x1]; 9020 u8 pcie_performance_group[0x1]; 9021 }; 9022 9023 struct mlx5_ifc_mcam_access_reg_bits { 9024 u8 reserved_at_0[0x1c]; 9025 u8 mcda[0x1]; 9026 u8 mcc[0x1]; 9027 u8 mcqi[0x1]; 9028 u8 mcqs[0x1]; 9029 9030 u8 regs_95_to_87[0x9]; 9031 u8 mpegc[0x1]; 9032 u8 regs_85_to_68[0x12]; 9033 u8 tracer_registers[0x4]; 9034 9035 u8 regs_63_to_32[0x20]; 9036 u8 regs_31_to_0[0x20]; 9037 }; 9038 9039 struct mlx5_ifc_mcam_access_reg_bits1 { 9040 u8 regs_127_to_96[0x20]; 9041 9042 u8 regs_95_to_64[0x20]; 9043 9044 u8 regs_63_to_32[0x20]; 9045 9046 u8 regs_31_to_0[0x20]; 9047 }; 9048 9049 struct mlx5_ifc_mcam_access_reg_bits2 { 9050 u8 regs_127_to_99[0x1d]; 9051 u8 mirc[0x1]; 9052 u8 regs_97_to_96[0x2]; 9053 9054 u8 regs_95_to_64[0x20]; 9055 9056 u8 regs_63_to_32[0x20]; 9057 9058 u8 regs_31_to_0[0x20]; 9059 }; 9060 9061 struct mlx5_ifc_mcam_reg_bits { 9062 u8 reserved_at_0[0x8]; 9063 u8 feature_group[0x8]; 9064 u8 reserved_at_10[0x8]; 9065 u8 access_reg_group[0x8]; 9066 9067 u8 reserved_at_20[0x20]; 9068 9069 union { 9070 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9071 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9072 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9073 u8 reserved_at_0[0x80]; 9074 } mng_access_reg_cap_mask; 9075 9076 u8 reserved_at_c0[0x80]; 9077 9078 union { 9079 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9080 u8 reserved_at_0[0x80]; 9081 } mng_feature_cap_mask; 9082 9083 u8 reserved_at_1c0[0x80]; 9084 }; 9085 9086 struct mlx5_ifc_qcam_access_reg_cap_mask { 9087 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9088 u8 qpdpm[0x1]; 9089 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9090 u8 qdpm[0x1]; 9091 u8 qpts[0x1]; 9092 u8 qcap[0x1]; 9093 u8 qcam_access_reg_cap_mask_0[0x1]; 9094 }; 9095 9096 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9097 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9098 u8 qpts_trust_both[0x1]; 9099 }; 9100 9101 struct mlx5_ifc_qcam_reg_bits { 9102 u8 reserved_at_0[0x8]; 9103 u8 feature_group[0x8]; 9104 u8 reserved_at_10[0x8]; 9105 u8 access_reg_group[0x8]; 9106 u8 reserved_at_20[0x20]; 9107 9108 union { 9109 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9110 u8 reserved_at_0[0x80]; 9111 } qos_access_reg_cap_mask; 9112 9113 u8 reserved_at_c0[0x80]; 9114 9115 union { 9116 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9117 u8 reserved_at_0[0x80]; 9118 } qos_feature_cap_mask; 9119 9120 u8 reserved_at_1c0[0x80]; 9121 }; 9122 9123 struct mlx5_ifc_core_dump_reg_bits { 9124 u8 reserved_at_0[0x18]; 9125 u8 core_dump_type[0x8]; 9126 9127 u8 reserved_at_20[0x30]; 9128 u8 vhca_id[0x10]; 9129 9130 u8 reserved_at_60[0x8]; 9131 u8 qpn[0x18]; 9132 u8 reserved_at_80[0x180]; 9133 }; 9134 9135 struct mlx5_ifc_pcap_reg_bits { 9136 u8 reserved_at_0[0x8]; 9137 u8 local_port[0x8]; 9138 u8 reserved_at_10[0x10]; 9139 9140 u8 port_capability_mask[4][0x20]; 9141 }; 9142 9143 struct mlx5_ifc_paos_reg_bits { 9144 u8 swid[0x8]; 9145 u8 local_port[0x8]; 9146 u8 reserved_at_10[0x4]; 9147 u8 admin_status[0x4]; 9148 u8 reserved_at_18[0x4]; 9149 u8 oper_status[0x4]; 9150 9151 u8 ase[0x1]; 9152 u8 ee[0x1]; 9153 u8 reserved_at_22[0x1c]; 9154 u8 e[0x2]; 9155 9156 u8 reserved_at_40[0x40]; 9157 }; 9158 9159 struct mlx5_ifc_pamp_reg_bits { 9160 u8 reserved_at_0[0x8]; 9161 u8 opamp_group[0x8]; 9162 u8 reserved_at_10[0xc]; 9163 u8 opamp_group_type[0x4]; 9164 9165 u8 start_index[0x10]; 9166 u8 reserved_at_30[0x4]; 9167 u8 num_of_indices[0xc]; 9168 9169 u8 index_data[18][0x10]; 9170 }; 9171 9172 struct mlx5_ifc_pcmr_reg_bits { 9173 u8 reserved_at_0[0x8]; 9174 u8 local_port[0x8]; 9175 u8 reserved_at_10[0x10]; 9176 u8 entropy_force_cap[0x1]; 9177 u8 entropy_calc_cap[0x1]; 9178 u8 entropy_gre_calc_cap[0x1]; 9179 u8 reserved_at_23[0x1b]; 9180 u8 fcs_cap[0x1]; 9181 u8 reserved_at_3f[0x1]; 9182 u8 entropy_force[0x1]; 9183 u8 entropy_calc[0x1]; 9184 u8 entropy_gre_calc[0x1]; 9185 u8 reserved_at_43[0x1b]; 9186 u8 fcs_chk[0x1]; 9187 u8 reserved_at_5f[0x1]; 9188 }; 9189 9190 struct mlx5_ifc_lane_2_module_mapping_bits { 9191 u8 reserved_at_0[0x6]; 9192 u8 rx_lane[0x2]; 9193 u8 reserved_at_8[0x6]; 9194 u8 tx_lane[0x2]; 9195 u8 reserved_at_10[0x8]; 9196 u8 module[0x8]; 9197 }; 9198 9199 struct mlx5_ifc_bufferx_reg_bits { 9200 u8 reserved_at_0[0x6]; 9201 u8 lossy[0x1]; 9202 u8 epsb[0x1]; 9203 u8 reserved_at_8[0xc]; 9204 u8 size[0xc]; 9205 9206 u8 xoff_threshold[0x10]; 9207 u8 xon_threshold[0x10]; 9208 }; 9209 9210 struct mlx5_ifc_set_node_in_bits { 9211 u8 node_description[64][0x8]; 9212 }; 9213 9214 struct mlx5_ifc_register_power_settings_bits { 9215 u8 reserved_at_0[0x18]; 9216 u8 power_settings_level[0x8]; 9217 9218 u8 reserved_at_20[0x60]; 9219 }; 9220 9221 struct mlx5_ifc_register_host_endianness_bits { 9222 u8 he[0x1]; 9223 u8 reserved_at_1[0x1f]; 9224 9225 u8 reserved_at_20[0x60]; 9226 }; 9227 9228 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9229 u8 reserved_at_0[0x20]; 9230 9231 u8 mkey[0x20]; 9232 9233 u8 addressh_63_32[0x20]; 9234 9235 u8 addressl_31_0[0x20]; 9236 }; 9237 9238 struct mlx5_ifc_ud_adrs_vector_bits { 9239 u8 dc_key[0x40]; 9240 9241 u8 ext[0x1]; 9242 u8 reserved_at_41[0x7]; 9243 u8 destination_qp_dct[0x18]; 9244 9245 u8 static_rate[0x4]; 9246 u8 sl_eth_prio[0x4]; 9247 u8 fl[0x1]; 9248 u8 mlid[0x7]; 9249 u8 rlid_udp_sport[0x10]; 9250 9251 u8 reserved_at_80[0x20]; 9252 9253 u8 rmac_47_16[0x20]; 9254 9255 u8 rmac_15_0[0x10]; 9256 u8 tclass[0x8]; 9257 u8 hop_limit[0x8]; 9258 9259 u8 reserved_at_e0[0x1]; 9260 u8 grh[0x1]; 9261 u8 reserved_at_e2[0x2]; 9262 u8 src_addr_index[0x8]; 9263 u8 flow_label[0x14]; 9264 9265 u8 rgid_rip[16][0x8]; 9266 }; 9267 9268 struct mlx5_ifc_pages_req_event_bits { 9269 u8 reserved_at_0[0x10]; 9270 u8 function_id[0x10]; 9271 9272 u8 num_pages[0x20]; 9273 9274 u8 reserved_at_40[0xa0]; 9275 }; 9276 9277 struct mlx5_ifc_eqe_bits { 9278 u8 reserved_at_0[0x8]; 9279 u8 event_type[0x8]; 9280 u8 reserved_at_10[0x8]; 9281 u8 event_sub_type[0x8]; 9282 9283 u8 reserved_at_20[0xe0]; 9284 9285 union mlx5_ifc_event_auto_bits event_data; 9286 9287 u8 reserved_at_1e0[0x10]; 9288 u8 signature[0x8]; 9289 u8 reserved_at_1f8[0x7]; 9290 u8 owner[0x1]; 9291 }; 9292 9293 enum { 9294 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9295 }; 9296 9297 struct mlx5_ifc_cmd_queue_entry_bits { 9298 u8 type[0x8]; 9299 u8 reserved_at_8[0x18]; 9300 9301 u8 input_length[0x20]; 9302 9303 u8 input_mailbox_pointer_63_32[0x20]; 9304 9305 u8 input_mailbox_pointer_31_9[0x17]; 9306 u8 reserved_at_77[0x9]; 9307 9308 u8 command_input_inline_data[16][0x8]; 9309 9310 u8 command_output_inline_data[16][0x8]; 9311 9312 u8 output_mailbox_pointer_63_32[0x20]; 9313 9314 u8 output_mailbox_pointer_31_9[0x17]; 9315 u8 reserved_at_1b7[0x9]; 9316 9317 u8 output_length[0x20]; 9318 9319 u8 token[0x8]; 9320 u8 signature[0x8]; 9321 u8 reserved_at_1f0[0x8]; 9322 u8 status[0x7]; 9323 u8 ownership[0x1]; 9324 }; 9325 9326 struct mlx5_ifc_cmd_out_bits { 9327 u8 status[0x8]; 9328 u8 reserved_at_8[0x18]; 9329 9330 u8 syndrome[0x20]; 9331 9332 u8 command_output[0x20]; 9333 }; 9334 9335 struct mlx5_ifc_cmd_in_bits { 9336 u8 opcode[0x10]; 9337 u8 reserved_at_10[0x10]; 9338 9339 u8 reserved_at_20[0x10]; 9340 u8 op_mod[0x10]; 9341 9342 u8 command[0][0x20]; 9343 }; 9344 9345 struct mlx5_ifc_cmd_if_box_bits { 9346 u8 mailbox_data[512][0x8]; 9347 9348 u8 reserved_at_1000[0x180]; 9349 9350 u8 next_pointer_63_32[0x20]; 9351 9352 u8 next_pointer_31_10[0x16]; 9353 u8 reserved_at_11b6[0xa]; 9354 9355 u8 block_number[0x20]; 9356 9357 u8 reserved_at_11e0[0x8]; 9358 u8 token[0x8]; 9359 u8 ctrl_signature[0x8]; 9360 u8 signature[0x8]; 9361 }; 9362 9363 struct mlx5_ifc_mtt_bits { 9364 u8 ptag_63_32[0x20]; 9365 9366 u8 ptag_31_8[0x18]; 9367 u8 reserved_at_38[0x6]; 9368 u8 wr_en[0x1]; 9369 u8 rd_en[0x1]; 9370 }; 9371 9372 struct mlx5_ifc_query_wol_rol_out_bits { 9373 u8 status[0x8]; 9374 u8 reserved_at_8[0x18]; 9375 9376 u8 syndrome[0x20]; 9377 9378 u8 reserved_at_40[0x10]; 9379 u8 rol_mode[0x8]; 9380 u8 wol_mode[0x8]; 9381 9382 u8 reserved_at_60[0x20]; 9383 }; 9384 9385 struct mlx5_ifc_query_wol_rol_in_bits { 9386 u8 opcode[0x10]; 9387 u8 reserved_at_10[0x10]; 9388 9389 u8 reserved_at_20[0x10]; 9390 u8 op_mod[0x10]; 9391 9392 u8 reserved_at_40[0x40]; 9393 }; 9394 9395 struct mlx5_ifc_set_wol_rol_out_bits { 9396 u8 status[0x8]; 9397 u8 reserved_at_8[0x18]; 9398 9399 u8 syndrome[0x20]; 9400 9401 u8 reserved_at_40[0x40]; 9402 }; 9403 9404 struct mlx5_ifc_set_wol_rol_in_bits { 9405 u8 opcode[0x10]; 9406 u8 reserved_at_10[0x10]; 9407 9408 u8 reserved_at_20[0x10]; 9409 u8 op_mod[0x10]; 9410 9411 u8 rol_mode_valid[0x1]; 9412 u8 wol_mode_valid[0x1]; 9413 u8 reserved_at_42[0xe]; 9414 u8 rol_mode[0x8]; 9415 u8 wol_mode[0x8]; 9416 9417 u8 reserved_at_60[0x20]; 9418 }; 9419 9420 enum { 9421 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9422 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9423 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9424 }; 9425 9426 enum { 9427 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9428 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9429 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9430 }; 9431 9432 enum { 9433 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9434 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9435 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9436 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9437 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9438 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9439 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9440 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9441 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9442 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9443 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9444 }; 9445 9446 struct mlx5_ifc_initial_seg_bits { 9447 u8 fw_rev_minor[0x10]; 9448 u8 fw_rev_major[0x10]; 9449 9450 u8 cmd_interface_rev[0x10]; 9451 u8 fw_rev_subminor[0x10]; 9452 9453 u8 reserved_at_40[0x40]; 9454 9455 u8 cmdq_phy_addr_63_32[0x20]; 9456 9457 u8 cmdq_phy_addr_31_12[0x14]; 9458 u8 reserved_at_b4[0x2]; 9459 u8 nic_interface[0x2]; 9460 u8 log_cmdq_size[0x4]; 9461 u8 log_cmdq_stride[0x4]; 9462 9463 u8 command_doorbell_vector[0x20]; 9464 9465 u8 reserved_at_e0[0xf00]; 9466 9467 u8 initializing[0x1]; 9468 u8 reserved_at_fe1[0x4]; 9469 u8 nic_interface_supported[0x3]; 9470 u8 embedded_cpu[0x1]; 9471 u8 reserved_at_fe9[0x17]; 9472 9473 struct mlx5_ifc_health_buffer_bits health_buffer; 9474 9475 u8 no_dram_nic_offset[0x20]; 9476 9477 u8 reserved_at_1220[0x6e40]; 9478 9479 u8 reserved_at_8060[0x1f]; 9480 u8 clear_int[0x1]; 9481 9482 u8 health_syndrome[0x8]; 9483 u8 health_counter[0x18]; 9484 9485 u8 reserved_at_80a0[0x17fc0]; 9486 }; 9487 9488 struct mlx5_ifc_mtpps_reg_bits { 9489 u8 reserved_at_0[0xc]; 9490 u8 cap_number_of_pps_pins[0x4]; 9491 u8 reserved_at_10[0x4]; 9492 u8 cap_max_num_of_pps_in_pins[0x4]; 9493 u8 reserved_at_18[0x4]; 9494 u8 cap_max_num_of_pps_out_pins[0x4]; 9495 9496 u8 reserved_at_20[0x24]; 9497 u8 cap_pin_3_mode[0x4]; 9498 u8 reserved_at_48[0x4]; 9499 u8 cap_pin_2_mode[0x4]; 9500 u8 reserved_at_50[0x4]; 9501 u8 cap_pin_1_mode[0x4]; 9502 u8 reserved_at_58[0x4]; 9503 u8 cap_pin_0_mode[0x4]; 9504 9505 u8 reserved_at_60[0x4]; 9506 u8 cap_pin_7_mode[0x4]; 9507 u8 reserved_at_68[0x4]; 9508 u8 cap_pin_6_mode[0x4]; 9509 u8 reserved_at_70[0x4]; 9510 u8 cap_pin_5_mode[0x4]; 9511 u8 reserved_at_78[0x4]; 9512 u8 cap_pin_4_mode[0x4]; 9513 9514 u8 field_select[0x20]; 9515 u8 reserved_at_a0[0x60]; 9516 9517 u8 enable[0x1]; 9518 u8 reserved_at_101[0xb]; 9519 u8 pattern[0x4]; 9520 u8 reserved_at_110[0x4]; 9521 u8 pin_mode[0x4]; 9522 u8 pin[0x8]; 9523 9524 u8 reserved_at_120[0x20]; 9525 9526 u8 time_stamp[0x40]; 9527 9528 u8 out_pulse_duration[0x10]; 9529 u8 out_periodic_adjustment[0x10]; 9530 u8 enhanced_out_periodic_adjustment[0x20]; 9531 9532 u8 reserved_at_1c0[0x20]; 9533 }; 9534 9535 struct mlx5_ifc_mtppse_reg_bits { 9536 u8 reserved_at_0[0x18]; 9537 u8 pin[0x8]; 9538 u8 event_arm[0x1]; 9539 u8 reserved_at_21[0x1b]; 9540 u8 event_generation_mode[0x4]; 9541 u8 reserved_at_40[0x40]; 9542 }; 9543 9544 struct mlx5_ifc_mcqs_reg_bits { 9545 u8 last_index_flag[0x1]; 9546 u8 reserved_at_1[0x7]; 9547 u8 fw_device[0x8]; 9548 u8 component_index[0x10]; 9549 9550 u8 reserved_at_20[0x10]; 9551 u8 identifier[0x10]; 9552 9553 u8 reserved_at_40[0x17]; 9554 u8 component_status[0x5]; 9555 u8 component_update_state[0x4]; 9556 9557 u8 last_update_state_changer_type[0x4]; 9558 u8 last_update_state_changer_host_id[0x4]; 9559 u8 reserved_at_68[0x18]; 9560 }; 9561 9562 struct mlx5_ifc_mcqi_cap_bits { 9563 u8 supported_info_bitmask[0x20]; 9564 9565 u8 component_size[0x20]; 9566 9567 u8 max_component_size[0x20]; 9568 9569 u8 log_mcda_word_size[0x4]; 9570 u8 reserved_at_64[0xc]; 9571 u8 mcda_max_write_size[0x10]; 9572 9573 u8 rd_en[0x1]; 9574 u8 reserved_at_81[0x1]; 9575 u8 match_chip_id[0x1]; 9576 u8 match_psid[0x1]; 9577 u8 check_user_timestamp[0x1]; 9578 u8 match_base_guid_mac[0x1]; 9579 u8 reserved_at_86[0x1a]; 9580 }; 9581 9582 struct mlx5_ifc_mcqi_version_bits { 9583 u8 reserved_at_0[0x2]; 9584 u8 build_time_valid[0x1]; 9585 u8 user_defined_time_valid[0x1]; 9586 u8 reserved_at_4[0x14]; 9587 u8 version_string_length[0x8]; 9588 9589 u8 version[0x20]; 9590 9591 u8 build_time[0x40]; 9592 9593 u8 user_defined_time[0x40]; 9594 9595 u8 build_tool_version[0x20]; 9596 9597 u8 reserved_at_e0[0x20]; 9598 9599 u8 version_string[92][0x8]; 9600 }; 9601 9602 struct mlx5_ifc_mcqi_activation_method_bits { 9603 u8 pending_server_ac_power_cycle[0x1]; 9604 u8 pending_server_dc_power_cycle[0x1]; 9605 u8 pending_server_reboot[0x1]; 9606 u8 pending_fw_reset[0x1]; 9607 u8 auto_activate[0x1]; 9608 u8 all_hosts_sync[0x1]; 9609 u8 device_hw_reset[0x1]; 9610 u8 reserved_at_7[0x19]; 9611 }; 9612 9613 union mlx5_ifc_mcqi_reg_data_bits { 9614 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9615 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9616 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9617 }; 9618 9619 struct mlx5_ifc_mcqi_reg_bits { 9620 u8 read_pending_component[0x1]; 9621 u8 reserved_at_1[0xf]; 9622 u8 component_index[0x10]; 9623 9624 u8 reserved_at_20[0x20]; 9625 9626 u8 reserved_at_40[0x1b]; 9627 u8 info_type[0x5]; 9628 9629 u8 info_size[0x20]; 9630 9631 u8 offset[0x20]; 9632 9633 u8 reserved_at_a0[0x10]; 9634 u8 data_size[0x10]; 9635 9636 union mlx5_ifc_mcqi_reg_data_bits data[0]; 9637 }; 9638 9639 struct mlx5_ifc_mcc_reg_bits { 9640 u8 reserved_at_0[0x4]; 9641 u8 time_elapsed_since_last_cmd[0xc]; 9642 u8 reserved_at_10[0x8]; 9643 u8 instruction[0x8]; 9644 9645 u8 reserved_at_20[0x10]; 9646 u8 component_index[0x10]; 9647 9648 u8 reserved_at_40[0x8]; 9649 u8 update_handle[0x18]; 9650 9651 u8 handle_owner_type[0x4]; 9652 u8 handle_owner_host_id[0x4]; 9653 u8 reserved_at_68[0x1]; 9654 u8 control_progress[0x7]; 9655 u8 error_code[0x8]; 9656 u8 reserved_at_78[0x4]; 9657 u8 control_state[0x4]; 9658 9659 u8 component_size[0x20]; 9660 9661 u8 reserved_at_a0[0x60]; 9662 }; 9663 9664 struct mlx5_ifc_mcda_reg_bits { 9665 u8 reserved_at_0[0x8]; 9666 u8 update_handle[0x18]; 9667 9668 u8 offset[0x20]; 9669 9670 u8 reserved_at_40[0x10]; 9671 u8 size[0x10]; 9672 9673 u8 reserved_at_60[0x20]; 9674 9675 u8 data[0][0x20]; 9676 }; 9677 9678 struct mlx5_ifc_mirc_reg_bits { 9679 u8 reserved_at_0[0x18]; 9680 u8 status_code[0x8]; 9681 9682 u8 reserved_at_20[0x20]; 9683 }; 9684 9685 union mlx5_ifc_ports_control_registers_document_bits { 9686 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9687 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9688 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9689 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9690 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9691 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9692 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9693 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9694 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9695 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9696 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9697 struct mlx5_ifc_paos_reg_bits paos_reg; 9698 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9699 struct mlx5_ifc_peir_reg_bits peir_reg; 9700 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9701 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9702 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9703 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9704 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9705 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9706 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9707 struct mlx5_ifc_plib_reg_bits plib_reg; 9708 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9709 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9710 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9711 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9712 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9713 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9714 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9715 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9716 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9717 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9718 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9719 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9720 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9721 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9722 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9723 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9724 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9725 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9726 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9727 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9728 struct mlx5_ifc_pude_reg_bits pude_reg; 9729 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9730 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9731 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9732 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9733 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9734 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9735 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9736 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9737 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9738 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9739 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9740 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9741 u8 reserved_at_0[0x60e0]; 9742 }; 9743 9744 union mlx5_ifc_debug_enhancements_document_bits { 9745 struct mlx5_ifc_health_buffer_bits health_buffer; 9746 u8 reserved_at_0[0x200]; 9747 }; 9748 9749 union mlx5_ifc_uplink_pci_interface_document_bits { 9750 struct mlx5_ifc_initial_seg_bits initial_seg; 9751 u8 reserved_at_0[0x20060]; 9752 }; 9753 9754 struct mlx5_ifc_set_flow_table_root_out_bits { 9755 u8 status[0x8]; 9756 u8 reserved_at_8[0x18]; 9757 9758 u8 syndrome[0x20]; 9759 9760 u8 reserved_at_40[0x40]; 9761 }; 9762 9763 struct mlx5_ifc_set_flow_table_root_in_bits { 9764 u8 opcode[0x10]; 9765 u8 reserved_at_10[0x10]; 9766 9767 u8 reserved_at_20[0x10]; 9768 u8 op_mod[0x10]; 9769 9770 u8 other_vport[0x1]; 9771 u8 reserved_at_41[0xf]; 9772 u8 vport_number[0x10]; 9773 9774 u8 reserved_at_60[0x20]; 9775 9776 u8 table_type[0x8]; 9777 u8 reserved_at_88[0x18]; 9778 9779 u8 reserved_at_a0[0x8]; 9780 u8 table_id[0x18]; 9781 9782 u8 reserved_at_c0[0x8]; 9783 u8 underlay_qpn[0x18]; 9784 u8 reserved_at_e0[0x120]; 9785 }; 9786 9787 enum { 9788 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9789 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9790 }; 9791 9792 struct mlx5_ifc_modify_flow_table_out_bits { 9793 u8 status[0x8]; 9794 u8 reserved_at_8[0x18]; 9795 9796 u8 syndrome[0x20]; 9797 9798 u8 reserved_at_40[0x40]; 9799 }; 9800 9801 struct mlx5_ifc_modify_flow_table_in_bits { 9802 u8 opcode[0x10]; 9803 u8 reserved_at_10[0x10]; 9804 9805 u8 reserved_at_20[0x10]; 9806 u8 op_mod[0x10]; 9807 9808 u8 other_vport[0x1]; 9809 u8 reserved_at_41[0xf]; 9810 u8 vport_number[0x10]; 9811 9812 u8 reserved_at_60[0x10]; 9813 u8 modify_field_select[0x10]; 9814 9815 u8 table_type[0x8]; 9816 u8 reserved_at_88[0x18]; 9817 9818 u8 reserved_at_a0[0x8]; 9819 u8 table_id[0x18]; 9820 9821 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9822 }; 9823 9824 struct mlx5_ifc_ets_tcn_config_reg_bits { 9825 u8 g[0x1]; 9826 u8 b[0x1]; 9827 u8 r[0x1]; 9828 u8 reserved_at_3[0x9]; 9829 u8 group[0x4]; 9830 u8 reserved_at_10[0x9]; 9831 u8 bw_allocation[0x7]; 9832 9833 u8 reserved_at_20[0xc]; 9834 u8 max_bw_units[0x4]; 9835 u8 reserved_at_30[0x8]; 9836 u8 max_bw_value[0x8]; 9837 }; 9838 9839 struct mlx5_ifc_ets_global_config_reg_bits { 9840 u8 reserved_at_0[0x2]; 9841 u8 r[0x1]; 9842 u8 reserved_at_3[0x1d]; 9843 9844 u8 reserved_at_20[0xc]; 9845 u8 max_bw_units[0x4]; 9846 u8 reserved_at_30[0x8]; 9847 u8 max_bw_value[0x8]; 9848 }; 9849 9850 struct mlx5_ifc_qetc_reg_bits { 9851 u8 reserved_at_0[0x8]; 9852 u8 port_number[0x8]; 9853 u8 reserved_at_10[0x30]; 9854 9855 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9856 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9857 }; 9858 9859 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9860 u8 e[0x1]; 9861 u8 reserved_at_01[0x0b]; 9862 u8 prio[0x04]; 9863 }; 9864 9865 struct mlx5_ifc_qpdpm_reg_bits { 9866 u8 reserved_at_0[0x8]; 9867 u8 local_port[0x8]; 9868 u8 reserved_at_10[0x10]; 9869 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9870 }; 9871 9872 struct mlx5_ifc_qpts_reg_bits { 9873 u8 reserved_at_0[0x8]; 9874 u8 local_port[0x8]; 9875 u8 reserved_at_10[0x2d]; 9876 u8 trust_state[0x3]; 9877 }; 9878 9879 struct mlx5_ifc_pptb_reg_bits { 9880 u8 reserved_at_0[0x2]; 9881 u8 mm[0x2]; 9882 u8 reserved_at_4[0x4]; 9883 u8 local_port[0x8]; 9884 u8 reserved_at_10[0x6]; 9885 u8 cm[0x1]; 9886 u8 um[0x1]; 9887 u8 pm[0x8]; 9888 9889 u8 prio_x_buff[0x20]; 9890 9891 u8 pm_msb[0x8]; 9892 u8 reserved_at_48[0x10]; 9893 u8 ctrl_buff[0x4]; 9894 u8 untagged_buff[0x4]; 9895 }; 9896 9897 struct mlx5_ifc_pbmc_reg_bits { 9898 u8 reserved_at_0[0x8]; 9899 u8 local_port[0x8]; 9900 u8 reserved_at_10[0x10]; 9901 9902 u8 xoff_timer_value[0x10]; 9903 u8 xoff_refresh[0x10]; 9904 9905 u8 reserved_at_40[0x9]; 9906 u8 fullness_threshold[0x7]; 9907 u8 port_buffer_size[0x10]; 9908 9909 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9910 9911 u8 reserved_at_2e0[0x40]; 9912 }; 9913 9914 struct mlx5_ifc_qtct_reg_bits { 9915 u8 reserved_at_0[0x8]; 9916 u8 port_number[0x8]; 9917 u8 reserved_at_10[0xd]; 9918 u8 prio[0x3]; 9919 9920 u8 reserved_at_20[0x1d]; 9921 u8 tclass[0x3]; 9922 }; 9923 9924 struct mlx5_ifc_mcia_reg_bits { 9925 u8 l[0x1]; 9926 u8 reserved_at_1[0x7]; 9927 u8 module[0x8]; 9928 u8 reserved_at_10[0x8]; 9929 u8 status[0x8]; 9930 9931 u8 i2c_device_address[0x8]; 9932 u8 page_number[0x8]; 9933 u8 device_address[0x10]; 9934 9935 u8 reserved_at_40[0x10]; 9936 u8 size[0x10]; 9937 9938 u8 reserved_at_60[0x20]; 9939 9940 u8 dword_0[0x20]; 9941 u8 dword_1[0x20]; 9942 u8 dword_2[0x20]; 9943 u8 dword_3[0x20]; 9944 u8 dword_4[0x20]; 9945 u8 dword_5[0x20]; 9946 u8 dword_6[0x20]; 9947 u8 dword_7[0x20]; 9948 u8 dword_8[0x20]; 9949 u8 dword_9[0x20]; 9950 u8 dword_10[0x20]; 9951 u8 dword_11[0x20]; 9952 }; 9953 9954 struct mlx5_ifc_dcbx_param_bits { 9955 u8 dcbx_cee_cap[0x1]; 9956 u8 dcbx_ieee_cap[0x1]; 9957 u8 dcbx_standby_cap[0x1]; 9958 u8 reserved_at_3[0x5]; 9959 u8 port_number[0x8]; 9960 u8 reserved_at_10[0xa]; 9961 u8 max_application_table_size[6]; 9962 u8 reserved_at_20[0x15]; 9963 u8 version_oper[0x3]; 9964 u8 reserved_at_38[5]; 9965 u8 version_admin[0x3]; 9966 u8 willing_admin[0x1]; 9967 u8 reserved_at_41[0x3]; 9968 u8 pfc_cap_oper[0x4]; 9969 u8 reserved_at_48[0x4]; 9970 u8 pfc_cap_admin[0x4]; 9971 u8 reserved_at_50[0x4]; 9972 u8 num_of_tc_oper[0x4]; 9973 u8 reserved_at_58[0x4]; 9974 u8 num_of_tc_admin[0x4]; 9975 u8 remote_willing[0x1]; 9976 u8 reserved_at_61[3]; 9977 u8 remote_pfc_cap[4]; 9978 u8 reserved_at_68[0x14]; 9979 u8 remote_num_of_tc[0x4]; 9980 u8 reserved_at_80[0x18]; 9981 u8 error[0x8]; 9982 u8 reserved_at_a0[0x160]; 9983 }; 9984 9985 struct mlx5_ifc_lagc_bits { 9986 u8 reserved_at_0[0x1d]; 9987 u8 lag_state[0x3]; 9988 9989 u8 reserved_at_20[0x14]; 9990 u8 tx_remap_affinity_2[0x4]; 9991 u8 reserved_at_38[0x4]; 9992 u8 tx_remap_affinity_1[0x4]; 9993 }; 9994 9995 struct mlx5_ifc_create_lag_out_bits { 9996 u8 status[0x8]; 9997 u8 reserved_at_8[0x18]; 9998 9999 u8 syndrome[0x20]; 10000 10001 u8 reserved_at_40[0x40]; 10002 }; 10003 10004 struct mlx5_ifc_create_lag_in_bits { 10005 u8 opcode[0x10]; 10006 u8 reserved_at_10[0x10]; 10007 10008 u8 reserved_at_20[0x10]; 10009 u8 op_mod[0x10]; 10010 10011 struct mlx5_ifc_lagc_bits ctx; 10012 }; 10013 10014 struct mlx5_ifc_modify_lag_out_bits { 10015 u8 status[0x8]; 10016 u8 reserved_at_8[0x18]; 10017 10018 u8 syndrome[0x20]; 10019 10020 u8 reserved_at_40[0x40]; 10021 }; 10022 10023 struct mlx5_ifc_modify_lag_in_bits { 10024 u8 opcode[0x10]; 10025 u8 reserved_at_10[0x10]; 10026 10027 u8 reserved_at_20[0x10]; 10028 u8 op_mod[0x10]; 10029 10030 u8 reserved_at_40[0x20]; 10031 u8 field_select[0x20]; 10032 10033 struct mlx5_ifc_lagc_bits ctx; 10034 }; 10035 10036 struct mlx5_ifc_query_lag_out_bits { 10037 u8 status[0x8]; 10038 u8 reserved_at_8[0x18]; 10039 10040 u8 syndrome[0x20]; 10041 10042 struct mlx5_ifc_lagc_bits ctx; 10043 }; 10044 10045 struct mlx5_ifc_query_lag_in_bits { 10046 u8 opcode[0x10]; 10047 u8 reserved_at_10[0x10]; 10048 10049 u8 reserved_at_20[0x10]; 10050 u8 op_mod[0x10]; 10051 10052 u8 reserved_at_40[0x40]; 10053 }; 10054 10055 struct mlx5_ifc_destroy_lag_out_bits { 10056 u8 status[0x8]; 10057 u8 reserved_at_8[0x18]; 10058 10059 u8 syndrome[0x20]; 10060 10061 u8 reserved_at_40[0x40]; 10062 }; 10063 10064 struct mlx5_ifc_destroy_lag_in_bits { 10065 u8 opcode[0x10]; 10066 u8 reserved_at_10[0x10]; 10067 10068 u8 reserved_at_20[0x10]; 10069 u8 op_mod[0x10]; 10070 10071 u8 reserved_at_40[0x40]; 10072 }; 10073 10074 struct mlx5_ifc_create_vport_lag_out_bits { 10075 u8 status[0x8]; 10076 u8 reserved_at_8[0x18]; 10077 10078 u8 syndrome[0x20]; 10079 10080 u8 reserved_at_40[0x40]; 10081 }; 10082 10083 struct mlx5_ifc_create_vport_lag_in_bits { 10084 u8 opcode[0x10]; 10085 u8 reserved_at_10[0x10]; 10086 10087 u8 reserved_at_20[0x10]; 10088 u8 op_mod[0x10]; 10089 10090 u8 reserved_at_40[0x40]; 10091 }; 10092 10093 struct mlx5_ifc_destroy_vport_lag_out_bits { 10094 u8 status[0x8]; 10095 u8 reserved_at_8[0x18]; 10096 10097 u8 syndrome[0x20]; 10098 10099 u8 reserved_at_40[0x40]; 10100 }; 10101 10102 struct mlx5_ifc_destroy_vport_lag_in_bits { 10103 u8 opcode[0x10]; 10104 u8 reserved_at_10[0x10]; 10105 10106 u8 reserved_at_20[0x10]; 10107 u8 op_mod[0x10]; 10108 10109 u8 reserved_at_40[0x40]; 10110 }; 10111 10112 struct mlx5_ifc_alloc_memic_in_bits { 10113 u8 opcode[0x10]; 10114 u8 reserved_at_10[0x10]; 10115 10116 u8 reserved_at_20[0x10]; 10117 u8 op_mod[0x10]; 10118 10119 u8 reserved_at_30[0x20]; 10120 10121 u8 reserved_at_40[0x18]; 10122 u8 log_memic_addr_alignment[0x8]; 10123 10124 u8 range_start_addr[0x40]; 10125 10126 u8 range_size[0x20]; 10127 10128 u8 memic_size[0x20]; 10129 }; 10130 10131 struct mlx5_ifc_alloc_memic_out_bits { 10132 u8 status[0x8]; 10133 u8 reserved_at_8[0x18]; 10134 10135 u8 syndrome[0x20]; 10136 10137 u8 memic_start_addr[0x40]; 10138 }; 10139 10140 struct mlx5_ifc_dealloc_memic_in_bits { 10141 u8 opcode[0x10]; 10142 u8 reserved_at_10[0x10]; 10143 10144 u8 reserved_at_20[0x10]; 10145 u8 op_mod[0x10]; 10146 10147 u8 reserved_at_40[0x40]; 10148 10149 u8 memic_start_addr[0x40]; 10150 10151 u8 memic_size[0x20]; 10152 10153 u8 reserved_at_e0[0x20]; 10154 }; 10155 10156 struct mlx5_ifc_dealloc_memic_out_bits { 10157 u8 status[0x8]; 10158 u8 reserved_at_8[0x18]; 10159 10160 u8 syndrome[0x20]; 10161 10162 u8 reserved_at_40[0x40]; 10163 }; 10164 10165 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10166 u8 opcode[0x10]; 10167 u8 uid[0x10]; 10168 10169 u8 vhca_tunnel_id[0x10]; 10170 u8 obj_type[0x10]; 10171 10172 u8 obj_id[0x20]; 10173 10174 u8 reserved_at_60[0x20]; 10175 }; 10176 10177 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10178 u8 status[0x8]; 10179 u8 reserved_at_8[0x18]; 10180 10181 u8 syndrome[0x20]; 10182 10183 u8 obj_id[0x20]; 10184 10185 u8 reserved_at_60[0x20]; 10186 }; 10187 10188 struct mlx5_ifc_umem_bits { 10189 u8 reserved_at_0[0x80]; 10190 10191 u8 reserved_at_80[0x1b]; 10192 u8 log_page_size[0x5]; 10193 10194 u8 page_offset[0x20]; 10195 10196 u8 num_of_mtt[0x40]; 10197 10198 struct mlx5_ifc_mtt_bits mtt[0]; 10199 }; 10200 10201 struct mlx5_ifc_uctx_bits { 10202 u8 cap[0x20]; 10203 10204 u8 reserved_at_20[0x160]; 10205 }; 10206 10207 struct mlx5_ifc_sw_icm_bits { 10208 u8 modify_field_select[0x40]; 10209 10210 u8 reserved_at_40[0x18]; 10211 u8 log_sw_icm_size[0x8]; 10212 10213 u8 reserved_at_60[0x20]; 10214 10215 u8 sw_icm_start_addr[0x40]; 10216 10217 u8 reserved_at_c0[0x140]; 10218 }; 10219 10220 struct mlx5_ifc_geneve_tlv_option_bits { 10221 u8 modify_field_select[0x40]; 10222 10223 u8 reserved_at_40[0x18]; 10224 u8 geneve_option_fte_index[0x8]; 10225 10226 u8 option_class[0x10]; 10227 u8 option_type[0x8]; 10228 u8 reserved_at_78[0x3]; 10229 u8 option_data_length[0x5]; 10230 10231 u8 reserved_at_80[0x180]; 10232 }; 10233 10234 struct mlx5_ifc_create_umem_in_bits { 10235 u8 opcode[0x10]; 10236 u8 uid[0x10]; 10237 10238 u8 reserved_at_20[0x10]; 10239 u8 op_mod[0x10]; 10240 10241 u8 reserved_at_40[0x40]; 10242 10243 struct mlx5_ifc_umem_bits umem; 10244 }; 10245 10246 struct mlx5_ifc_create_uctx_in_bits { 10247 u8 opcode[0x10]; 10248 u8 reserved_at_10[0x10]; 10249 10250 u8 reserved_at_20[0x10]; 10251 u8 op_mod[0x10]; 10252 10253 u8 reserved_at_40[0x40]; 10254 10255 struct mlx5_ifc_uctx_bits uctx; 10256 }; 10257 10258 struct mlx5_ifc_destroy_uctx_in_bits { 10259 u8 opcode[0x10]; 10260 u8 reserved_at_10[0x10]; 10261 10262 u8 reserved_at_20[0x10]; 10263 u8 op_mod[0x10]; 10264 10265 u8 reserved_at_40[0x10]; 10266 u8 uid[0x10]; 10267 10268 u8 reserved_at_60[0x20]; 10269 }; 10270 10271 struct mlx5_ifc_create_sw_icm_in_bits { 10272 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10273 struct mlx5_ifc_sw_icm_bits sw_icm; 10274 }; 10275 10276 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10277 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10278 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10279 }; 10280 10281 struct mlx5_ifc_mtrc_string_db_param_bits { 10282 u8 string_db_base_address[0x20]; 10283 10284 u8 reserved_at_20[0x8]; 10285 u8 string_db_size[0x18]; 10286 }; 10287 10288 struct mlx5_ifc_mtrc_cap_bits { 10289 u8 trace_owner[0x1]; 10290 u8 trace_to_memory[0x1]; 10291 u8 reserved_at_2[0x4]; 10292 u8 trc_ver[0x2]; 10293 u8 reserved_at_8[0x14]; 10294 u8 num_string_db[0x4]; 10295 10296 u8 first_string_trace[0x8]; 10297 u8 num_string_trace[0x8]; 10298 u8 reserved_at_30[0x28]; 10299 10300 u8 log_max_trace_buffer_size[0x8]; 10301 10302 u8 reserved_at_60[0x20]; 10303 10304 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10305 10306 u8 reserved_at_280[0x180]; 10307 }; 10308 10309 struct mlx5_ifc_mtrc_conf_bits { 10310 u8 reserved_at_0[0x1c]; 10311 u8 trace_mode[0x4]; 10312 u8 reserved_at_20[0x18]; 10313 u8 log_trace_buffer_size[0x8]; 10314 u8 trace_mkey[0x20]; 10315 u8 reserved_at_60[0x3a0]; 10316 }; 10317 10318 struct mlx5_ifc_mtrc_stdb_bits { 10319 u8 string_db_index[0x4]; 10320 u8 reserved_at_4[0x4]; 10321 u8 read_size[0x18]; 10322 u8 start_offset[0x20]; 10323 u8 string_db_data[0]; 10324 }; 10325 10326 struct mlx5_ifc_mtrc_ctrl_bits { 10327 u8 trace_status[0x2]; 10328 u8 reserved_at_2[0x2]; 10329 u8 arm_event[0x1]; 10330 u8 reserved_at_5[0xb]; 10331 u8 modify_field_select[0x10]; 10332 u8 reserved_at_20[0x2b]; 10333 u8 current_timestamp52_32[0x15]; 10334 u8 current_timestamp31_0[0x20]; 10335 u8 reserved_at_80[0x180]; 10336 }; 10337 10338 struct mlx5_ifc_host_params_context_bits { 10339 u8 host_number[0x8]; 10340 u8 reserved_at_8[0x7]; 10341 u8 host_pf_disabled[0x1]; 10342 u8 host_num_of_vfs[0x10]; 10343 10344 u8 host_total_vfs[0x10]; 10345 u8 host_pci_bus[0x10]; 10346 10347 u8 reserved_at_40[0x10]; 10348 u8 host_pci_device[0x10]; 10349 10350 u8 reserved_at_60[0x10]; 10351 u8 host_pci_function[0x10]; 10352 10353 u8 reserved_at_80[0x180]; 10354 }; 10355 10356 struct mlx5_ifc_query_esw_functions_in_bits { 10357 u8 opcode[0x10]; 10358 u8 reserved_at_10[0x10]; 10359 10360 u8 reserved_at_20[0x10]; 10361 u8 op_mod[0x10]; 10362 10363 u8 reserved_at_40[0x40]; 10364 }; 10365 10366 struct mlx5_ifc_query_esw_functions_out_bits { 10367 u8 status[0x8]; 10368 u8 reserved_at_8[0x18]; 10369 10370 u8 syndrome[0x20]; 10371 10372 u8 reserved_at_40[0x40]; 10373 10374 struct mlx5_ifc_host_params_context_bits host_params_context; 10375 10376 u8 reserved_at_280[0x180]; 10377 u8 host_sf_enable[0][0x40]; 10378 }; 10379 10380 struct mlx5_ifc_sf_partition_bits { 10381 u8 reserved_at_0[0x10]; 10382 u8 log_num_sf[0x8]; 10383 u8 log_sf_bar_size[0x8]; 10384 }; 10385 10386 struct mlx5_ifc_query_sf_partitions_out_bits { 10387 u8 status[0x8]; 10388 u8 reserved_at_8[0x18]; 10389 10390 u8 syndrome[0x20]; 10391 10392 u8 reserved_at_40[0x18]; 10393 u8 num_sf_partitions[0x8]; 10394 10395 u8 reserved_at_60[0x20]; 10396 10397 struct mlx5_ifc_sf_partition_bits sf_partition[0]; 10398 }; 10399 10400 struct mlx5_ifc_query_sf_partitions_in_bits { 10401 u8 opcode[0x10]; 10402 u8 reserved_at_10[0x10]; 10403 10404 u8 reserved_at_20[0x10]; 10405 u8 op_mod[0x10]; 10406 10407 u8 reserved_at_40[0x40]; 10408 }; 10409 10410 struct mlx5_ifc_dealloc_sf_out_bits { 10411 u8 status[0x8]; 10412 u8 reserved_at_8[0x18]; 10413 10414 u8 syndrome[0x20]; 10415 10416 u8 reserved_at_40[0x40]; 10417 }; 10418 10419 struct mlx5_ifc_dealloc_sf_in_bits { 10420 u8 opcode[0x10]; 10421 u8 reserved_at_10[0x10]; 10422 10423 u8 reserved_at_20[0x10]; 10424 u8 op_mod[0x10]; 10425 10426 u8 reserved_at_40[0x10]; 10427 u8 function_id[0x10]; 10428 10429 u8 reserved_at_60[0x20]; 10430 }; 10431 10432 struct mlx5_ifc_alloc_sf_out_bits { 10433 u8 status[0x8]; 10434 u8 reserved_at_8[0x18]; 10435 10436 u8 syndrome[0x20]; 10437 10438 u8 reserved_at_40[0x40]; 10439 }; 10440 10441 struct mlx5_ifc_alloc_sf_in_bits { 10442 u8 opcode[0x10]; 10443 u8 reserved_at_10[0x10]; 10444 10445 u8 reserved_at_20[0x10]; 10446 u8 op_mod[0x10]; 10447 10448 u8 reserved_at_40[0x10]; 10449 u8 function_id[0x10]; 10450 10451 u8 reserved_at_60[0x20]; 10452 }; 10453 10454 struct mlx5_ifc_affiliated_event_header_bits { 10455 u8 reserved_at_0[0x10]; 10456 u8 obj_type[0x10]; 10457 10458 u8 obj_id[0x20]; 10459 }; 10460 10461 enum { 10462 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10463 }; 10464 10465 enum { 10466 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10467 }; 10468 10469 struct mlx5_ifc_encryption_key_obj_bits { 10470 u8 modify_field_select[0x40]; 10471 10472 u8 reserved_at_40[0x14]; 10473 u8 key_size[0x4]; 10474 u8 reserved_at_58[0x4]; 10475 u8 key_type[0x4]; 10476 10477 u8 reserved_at_60[0x8]; 10478 u8 pd[0x18]; 10479 10480 u8 reserved_at_80[0x180]; 10481 u8 key[8][0x20]; 10482 10483 u8 reserved_at_300[0x500]; 10484 }; 10485 10486 struct mlx5_ifc_create_encryption_key_in_bits { 10487 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10488 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10489 }; 10490 10491 enum { 10492 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10493 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10494 }; 10495 10496 enum { 10497 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10498 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10499 }; 10500 10501 struct mlx5_ifc_tls_static_params_bits { 10502 u8 const_2[0x2]; 10503 u8 tls_version[0x4]; 10504 u8 const_1[0x2]; 10505 u8 reserved_at_8[0x14]; 10506 u8 encryption_standard[0x4]; 10507 10508 u8 reserved_at_20[0x20]; 10509 10510 u8 initial_record_number[0x40]; 10511 10512 u8 resync_tcp_sn[0x20]; 10513 10514 u8 gcm_iv[0x20]; 10515 10516 u8 implicit_iv[0x40]; 10517 10518 u8 reserved_at_100[0x8]; 10519 u8 dek_index[0x18]; 10520 10521 u8 reserved_at_120[0xe0]; 10522 }; 10523 10524 struct mlx5_ifc_tls_progress_params_bits { 10525 u8 reserved_at_0[0x8]; 10526 u8 tisn[0x18]; 10527 10528 u8 next_record_tcp_sn[0x20]; 10529 10530 u8 hw_resync_tcp_sn[0x20]; 10531 10532 u8 record_tracker_state[0x2]; 10533 u8 auth_state[0x2]; 10534 u8 reserved_at_64[0x4]; 10535 u8 hw_offset_record_number[0x18]; 10536 }; 10537 10538 #endif /* MLX5_IFC_H */ 10539