1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 }; 64 65 enum { 66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 70 }; 71 72 enum { 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 75 }; 76 77 enum { 78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 80 MLX5_CMD_OP_INIT_HCA = 0x102, 81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 82 MLX5_CMD_OP_ENABLE_HCA = 0x104, 83 MLX5_CMD_OP_DISABLE_HCA = 0x105, 84 MLX5_CMD_OP_QUERY_PAGES = 0x107, 85 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 86 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 88 MLX5_CMD_OP_SET_ISSI = 0x10b, 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 90 MLX5_CMD_OP_CREATE_MKEY = 0x200, 91 MLX5_CMD_OP_QUERY_MKEY = 0x201, 92 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 97 MLX5_CMD_OP_CREATE_EQ = 0x301, 98 MLX5_CMD_OP_DESTROY_EQ = 0x302, 99 MLX5_CMD_OP_QUERY_EQ = 0x303, 100 MLX5_CMD_OP_GEN_EQE = 0x304, 101 MLX5_CMD_OP_CREATE_CQ = 0x400, 102 MLX5_CMD_OP_DESTROY_CQ = 0x401, 103 MLX5_CMD_OP_QUERY_CQ = 0x402, 104 MLX5_CMD_OP_MODIFY_CQ = 0x403, 105 MLX5_CMD_OP_CREATE_QP = 0x500, 106 MLX5_CMD_OP_DESTROY_QP = 0x501, 107 MLX5_CMD_OP_RST2INIT_QP = 0x502, 108 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 109 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 110 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 112 MLX5_CMD_OP_2ERR_QP = 0x507, 113 MLX5_CMD_OP_2RST_QP = 0x50a, 114 MLX5_CMD_OP_QUERY_QP = 0x50b, 115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 117 MLX5_CMD_OP_CREATE_PSV = 0x600, 118 MLX5_CMD_OP_DESTROY_PSV = 0x601, 119 MLX5_CMD_OP_CREATE_SRQ = 0x700, 120 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 121 MLX5_CMD_OP_QUERY_SRQ = 0x702, 122 MLX5_CMD_OP_ARM_RQ = 0x703, 123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 127 MLX5_CMD_OP_CREATE_DCT = 0x710, 128 MLX5_CMD_OP_DESTROY_DCT = 0x711, 129 MLX5_CMD_OP_DRAIN_DCT = 0x712, 130 MLX5_CMD_OP_QUERY_DCT = 0x713, 131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 132 MLX5_CMD_OP_CREATE_XRQ = 0x717, 133 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 134 MLX5_CMD_OP_QUERY_XRQ = 0x719, 135 MLX5_CMD_OP_ARM_XRQ = 0x71a, 136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 148 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 149 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 150 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 151 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 152 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 153 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 154 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 155 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 156 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 157 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 158 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 159 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 160 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 161 MLX5_CMD_OP_ALLOC_PD = 0x800, 162 MLX5_CMD_OP_DEALLOC_PD = 0x801, 163 MLX5_CMD_OP_ALLOC_UAR = 0x802, 164 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 165 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 166 MLX5_CMD_OP_ACCESS_REG = 0x805, 167 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 168 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 169 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 170 MLX5_CMD_OP_MAD_IFC = 0x50d, 171 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 172 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 173 MLX5_CMD_OP_NOP = 0x80d, 174 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 175 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 178 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 179 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 180 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 181 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 182 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 183 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 184 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 185 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 186 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 187 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 188 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 189 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 190 MLX5_CMD_OP_CREATE_LAG = 0x840, 191 MLX5_CMD_OP_MODIFY_LAG = 0x841, 192 MLX5_CMD_OP_QUERY_LAG = 0x842, 193 MLX5_CMD_OP_DESTROY_LAG = 0x843, 194 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 195 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 196 MLX5_CMD_OP_CREATE_TIR = 0x900, 197 MLX5_CMD_OP_MODIFY_TIR = 0x901, 198 MLX5_CMD_OP_DESTROY_TIR = 0x902, 199 MLX5_CMD_OP_QUERY_TIR = 0x903, 200 MLX5_CMD_OP_CREATE_SQ = 0x904, 201 MLX5_CMD_OP_MODIFY_SQ = 0x905, 202 MLX5_CMD_OP_DESTROY_SQ = 0x906, 203 MLX5_CMD_OP_QUERY_SQ = 0x907, 204 MLX5_CMD_OP_CREATE_RQ = 0x908, 205 MLX5_CMD_OP_MODIFY_RQ = 0x909, 206 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 207 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 208 MLX5_CMD_OP_QUERY_RQ = 0x90b, 209 MLX5_CMD_OP_CREATE_RMP = 0x90c, 210 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 211 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 212 MLX5_CMD_OP_QUERY_RMP = 0x90f, 213 MLX5_CMD_OP_CREATE_TIS = 0x912, 214 MLX5_CMD_OP_MODIFY_TIS = 0x913, 215 MLX5_CMD_OP_DESTROY_TIS = 0x914, 216 MLX5_CMD_OP_QUERY_TIS = 0x915, 217 MLX5_CMD_OP_CREATE_RQT = 0x916, 218 MLX5_CMD_OP_MODIFY_RQT = 0x917, 219 MLX5_CMD_OP_DESTROY_RQT = 0x918, 220 MLX5_CMD_OP_QUERY_RQT = 0x919, 221 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 222 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 223 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 224 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 225 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 226 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 227 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 228 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 229 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 231 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 232 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 233 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 234 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 235 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 236 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 237 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 238 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 239 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 240 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 241 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 242 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 243 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 244 MLX5_CMD_OP_MAX 245 }; 246 247 struct mlx5_ifc_flow_table_fields_supported_bits { 248 u8 outer_dmac[0x1]; 249 u8 outer_smac[0x1]; 250 u8 outer_ether_type[0x1]; 251 u8 outer_ip_version[0x1]; 252 u8 outer_first_prio[0x1]; 253 u8 outer_first_cfi[0x1]; 254 u8 outer_first_vid[0x1]; 255 u8 outer_ipv4_ttl[0x1]; 256 u8 outer_second_prio[0x1]; 257 u8 outer_second_cfi[0x1]; 258 u8 outer_second_vid[0x1]; 259 u8 reserved_at_b[0x1]; 260 u8 outer_sip[0x1]; 261 u8 outer_dip[0x1]; 262 u8 outer_frag[0x1]; 263 u8 outer_ip_protocol[0x1]; 264 u8 outer_ip_ecn[0x1]; 265 u8 outer_ip_dscp[0x1]; 266 u8 outer_udp_sport[0x1]; 267 u8 outer_udp_dport[0x1]; 268 u8 outer_tcp_sport[0x1]; 269 u8 outer_tcp_dport[0x1]; 270 u8 outer_tcp_flags[0x1]; 271 u8 outer_gre_protocol[0x1]; 272 u8 outer_gre_key[0x1]; 273 u8 outer_vxlan_vni[0x1]; 274 u8 reserved_at_1a[0x5]; 275 u8 source_eswitch_port[0x1]; 276 277 u8 inner_dmac[0x1]; 278 u8 inner_smac[0x1]; 279 u8 inner_ether_type[0x1]; 280 u8 inner_ip_version[0x1]; 281 u8 inner_first_prio[0x1]; 282 u8 inner_first_cfi[0x1]; 283 u8 inner_first_vid[0x1]; 284 u8 reserved_at_27[0x1]; 285 u8 inner_second_prio[0x1]; 286 u8 inner_second_cfi[0x1]; 287 u8 inner_second_vid[0x1]; 288 u8 reserved_at_2b[0x1]; 289 u8 inner_sip[0x1]; 290 u8 inner_dip[0x1]; 291 u8 inner_frag[0x1]; 292 u8 inner_ip_protocol[0x1]; 293 u8 inner_ip_ecn[0x1]; 294 u8 inner_ip_dscp[0x1]; 295 u8 inner_udp_sport[0x1]; 296 u8 inner_udp_dport[0x1]; 297 u8 inner_tcp_sport[0x1]; 298 u8 inner_tcp_dport[0x1]; 299 u8 inner_tcp_flags[0x1]; 300 u8 reserved_at_37[0x9]; 301 u8 reserved_at_40[0x17]; 302 u8 outer_esp_spi[0x1]; 303 u8 reserved_at_58[0x2]; 304 u8 bth_dst_qp[0x1]; 305 306 u8 reserved_at_5b[0x25]; 307 }; 308 309 struct mlx5_ifc_flow_table_prop_layout_bits { 310 u8 ft_support[0x1]; 311 u8 reserved_at_1[0x1]; 312 u8 flow_counter[0x1]; 313 u8 flow_modify_en[0x1]; 314 u8 modify_root[0x1]; 315 u8 identified_miss_table_mode[0x1]; 316 u8 flow_table_modify[0x1]; 317 u8 encap[0x1]; 318 u8 decap[0x1]; 319 u8 reserved_at_9[0x1]; 320 u8 pop_vlan[0x1]; 321 u8 push_vlan[0x1]; 322 u8 reserved_at_c[0x14]; 323 324 u8 reserved_at_20[0x2]; 325 u8 log_max_ft_size[0x6]; 326 u8 log_max_modify_header_context[0x8]; 327 u8 max_modify_header_actions[0x8]; 328 u8 max_ft_level[0x8]; 329 330 u8 reserved_at_40[0x20]; 331 332 u8 reserved_at_60[0x18]; 333 u8 log_max_ft_num[0x8]; 334 335 u8 reserved_at_80[0x18]; 336 u8 log_max_destination[0x8]; 337 338 u8 log_max_flow_counter[0x8]; 339 u8 reserved_at_a8[0x10]; 340 u8 log_max_flow[0x8]; 341 342 u8 reserved_at_c0[0x40]; 343 344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 345 346 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 347 }; 348 349 struct mlx5_ifc_odp_per_transport_service_cap_bits { 350 u8 send[0x1]; 351 u8 receive[0x1]; 352 u8 write[0x1]; 353 u8 read[0x1]; 354 u8 atomic[0x1]; 355 u8 srq_receive[0x1]; 356 u8 reserved_at_6[0x1a]; 357 }; 358 359 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 360 u8 smac_47_16[0x20]; 361 362 u8 smac_15_0[0x10]; 363 u8 ethertype[0x10]; 364 365 u8 dmac_47_16[0x20]; 366 367 u8 dmac_15_0[0x10]; 368 u8 first_prio[0x3]; 369 u8 first_cfi[0x1]; 370 u8 first_vid[0xc]; 371 372 u8 ip_protocol[0x8]; 373 u8 ip_dscp[0x6]; 374 u8 ip_ecn[0x2]; 375 u8 cvlan_tag[0x1]; 376 u8 svlan_tag[0x1]; 377 u8 frag[0x1]; 378 u8 ip_version[0x4]; 379 u8 tcp_flags[0x9]; 380 381 u8 tcp_sport[0x10]; 382 u8 tcp_dport[0x10]; 383 384 u8 reserved_at_c0[0x18]; 385 u8 ttl_hoplimit[0x8]; 386 387 u8 udp_sport[0x10]; 388 u8 udp_dport[0x10]; 389 390 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 391 392 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 393 }; 394 395 struct mlx5_ifc_fte_match_set_misc_bits { 396 u8 reserved_at_0[0x8]; 397 u8 source_sqn[0x18]; 398 399 u8 source_eswitch_owner_vhca_id[0x10]; 400 u8 source_port[0x10]; 401 402 u8 outer_second_prio[0x3]; 403 u8 outer_second_cfi[0x1]; 404 u8 outer_second_vid[0xc]; 405 u8 inner_second_prio[0x3]; 406 u8 inner_second_cfi[0x1]; 407 u8 inner_second_vid[0xc]; 408 409 u8 outer_second_cvlan_tag[0x1]; 410 u8 inner_second_cvlan_tag[0x1]; 411 u8 outer_second_svlan_tag[0x1]; 412 u8 inner_second_svlan_tag[0x1]; 413 u8 reserved_at_64[0xc]; 414 u8 gre_protocol[0x10]; 415 416 u8 gre_key_h[0x18]; 417 u8 gre_key_l[0x8]; 418 419 u8 vxlan_vni[0x18]; 420 u8 reserved_at_b8[0x8]; 421 422 u8 reserved_at_c0[0x20]; 423 424 u8 reserved_at_e0[0xc]; 425 u8 outer_ipv6_flow_label[0x14]; 426 427 u8 reserved_at_100[0xc]; 428 u8 inner_ipv6_flow_label[0x14]; 429 430 u8 reserved_at_120[0x28]; 431 u8 bth_dst_qp[0x18]; 432 u8 reserved_at_160[0x20]; 433 u8 outer_esp_spi[0x20]; 434 u8 reserved_at_1a0[0x60]; 435 }; 436 437 struct mlx5_ifc_cmd_pas_bits { 438 u8 pa_h[0x20]; 439 440 u8 pa_l[0x14]; 441 u8 reserved_at_34[0xc]; 442 }; 443 444 struct mlx5_ifc_uint64_bits { 445 u8 hi[0x20]; 446 447 u8 lo[0x20]; 448 }; 449 450 enum { 451 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 452 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 453 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 454 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 455 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 456 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 457 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 458 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 459 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 460 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 461 }; 462 463 struct mlx5_ifc_ads_bits { 464 u8 fl[0x1]; 465 u8 free_ar[0x1]; 466 u8 reserved_at_2[0xe]; 467 u8 pkey_index[0x10]; 468 469 u8 reserved_at_20[0x8]; 470 u8 grh[0x1]; 471 u8 mlid[0x7]; 472 u8 rlid[0x10]; 473 474 u8 ack_timeout[0x5]; 475 u8 reserved_at_45[0x3]; 476 u8 src_addr_index[0x8]; 477 u8 reserved_at_50[0x4]; 478 u8 stat_rate[0x4]; 479 u8 hop_limit[0x8]; 480 481 u8 reserved_at_60[0x4]; 482 u8 tclass[0x8]; 483 u8 flow_label[0x14]; 484 485 u8 rgid_rip[16][0x8]; 486 487 u8 reserved_at_100[0x4]; 488 u8 f_dscp[0x1]; 489 u8 f_ecn[0x1]; 490 u8 reserved_at_106[0x1]; 491 u8 f_eth_prio[0x1]; 492 u8 ecn[0x2]; 493 u8 dscp[0x6]; 494 u8 udp_sport[0x10]; 495 496 u8 dei_cfi[0x1]; 497 u8 eth_prio[0x3]; 498 u8 sl[0x4]; 499 u8 vhca_port_num[0x8]; 500 u8 rmac_47_32[0x10]; 501 502 u8 rmac_31_0[0x20]; 503 }; 504 505 struct mlx5_ifc_flow_table_nic_cap_bits { 506 u8 nic_rx_multi_path_tirs[0x1]; 507 u8 nic_rx_multi_path_tirs_fts[0x1]; 508 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 509 u8 reserved_at_3[0x1fd]; 510 511 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 512 513 u8 reserved_at_400[0x200]; 514 515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 516 517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 518 519 u8 reserved_at_a00[0x200]; 520 521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 522 523 u8 reserved_at_e00[0x7200]; 524 }; 525 526 struct mlx5_ifc_flow_table_eswitch_cap_bits { 527 u8 reserved_at_0[0x1c]; 528 u8 fdb_multi_path_to_table[0x1]; 529 u8 reserved_at_1d[0x1e3]; 530 531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 532 533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 534 535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 536 537 u8 reserved_at_800[0x7800]; 538 }; 539 540 struct mlx5_ifc_e_switch_cap_bits { 541 u8 vport_svlan_strip[0x1]; 542 u8 vport_cvlan_strip[0x1]; 543 u8 vport_svlan_insert[0x1]; 544 u8 vport_cvlan_insert_if_not_exist[0x1]; 545 u8 vport_cvlan_insert_overwrite[0x1]; 546 u8 reserved_at_5[0x18]; 547 u8 merged_eswitch[0x1]; 548 u8 nic_vport_node_guid_modify[0x1]; 549 u8 nic_vport_port_guid_modify[0x1]; 550 551 u8 vxlan_encap_decap[0x1]; 552 u8 nvgre_encap_decap[0x1]; 553 u8 reserved_at_22[0x9]; 554 u8 log_max_encap_headers[0x5]; 555 u8 reserved_2b[0x6]; 556 u8 max_encap_header_size[0xa]; 557 558 u8 reserved_40[0x7c0]; 559 560 }; 561 562 struct mlx5_ifc_qos_cap_bits { 563 u8 packet_pacing[0x1]; 564 u8 esw_scheduling[0x1]; 565 u8 esw_bw_share[0x1]; 566 u8 esw_rate_limit[0x1]; 567 u8 reserved_at_4[0x1]; 568 u8 packet_pacing_burst_bound[0x1]; 569 u8 packet_pacing_typical_size[0x1]; 570 u8 reserved_at_7[0x19]; 571 572 u8 reserved_at_20[0x20]; 573 574 u8 packet_pacing_max_rate[0x20]; 575 576 u8 packet_pacing_min_rate[0x20]; 577 578 u8 reserved_at_80[0x10]; 579 u8 packet_pacing_rate_table_size[0x10]; 580 581 u8 esw_element_type[0x10]; 582 u8 esw_tsar_type[0x10]; 583 584 u8 reserved_at_c0[0x10]; 585 u8 max_qos_para_vport[0x10]; 586 587 u8 max_tsar_bw_share[0x20]; 588 589 u8 reserved_at_100[0x700]; 590 }; 591 592 struct mlx5_ifc_debug_cap_bits { 593 u8 reserved_at_0[0x20]; 594 595 u8 reserved_at_20[0x2]; 596 u8 stall_detect[0x1]; 597 u8 reserved_at_23[0x1d]; 598 599 u8 reserved_at_40[0x7c0]; 600 }; 601 602 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 603 u8 csum_cap[0x1]; 604 u8 vlan_cap[0x1]; 605 u8 lro_cap[0x1]; 606 u8 lro_psh_flag[0x1]; 607 u8 lro_time_stamp[0x1]; 608 u8 reserved_at_5[0x2]; 609 u8 wqe_vlan_insert[0x1]; 610 u8 self_lb_en_modifiable[0x1]; 611 u8 reserved_at_9[0x2]; 612 u8 max_lso_cap[0x5]; 613 u8 multi_pkt_send_wqe[0x2]; 614 u8 wqe_inline_mode[0x2]; 615 u8 rss_ind_tbl_cap[0x4]; 616 u8 reg_umr_sq[0x1]; 617 u8 scatter_fcs[0x1]; 618 u8 enhanced_multi_pkt_send_wqe[0x1]; 619 u8 tunnel_lso_const_out_ip_id[0x1]; 620 u8 reserved_at_1c[0x2]; 621 u8 tunnel_stateless_gre[0x1]; 622 u8 tunnel_stateless_vxlan[0x1]; 623 624 u8 swp[0x1]; 625 u8 swp_csum[0x1]; 626 u8 swp_lso[0x1]; 627 u8 reserved_at_23[0x1b]; 628 u8 max_geneve_opt_len[0x1]; 629 u8 tunnel_stateless_geneve_rx[0x1]; 630 631 u8 reserved_at_40[0x10]; 632 u8 lro_min_mss_size[0x10]; 633 634 u8 reserved_at_60[0x120]; 635 636 u8 lro_timer_supported_periods[4][0x20]; 637 638 u8 reserved_at_200[0x600]; 639 }; 640 641 struct mlx5_ifc_roce_cap_bits { 642 u8 roce_apm[0x1]; 643 u8 reserved_at_1[0x1f]; 644 645 u8 reserved_at_20[0x60]; 646 647 u8 reserved_at_80[0xc]; 648 u8 l3_type[0x4]; 649 u8 reserved_at_90[0x8]; 650 u8 roce_version[0x8]; 651 652 u8 reserved_at_a0[0x10]; 653 u8 r_roce_dest_udp_port[0x10]; 654 655 u8 r_roce_max_src_udp_port[0x10]; 656 u8 r_roce_min_src_udp_port[0x10]; 657 658 u8 reserved_at_e0[0x10]; 659 u8 roce_address_table_size[0x10]; 660 661 u8 reserved_at_100[0x700]; 662 }; 663 664 struct mlx5_ifc_device_mem_cap_bits { 665 u8 memic[0x1]; 666 u8 reserved_at_1[0x1f]; 667 668 u8 reserved_at_20[0xb]; 669 u8 log_min_memic_alloc_size[0x5]; 670 u8 reserved_at_30[0x8]; 671 u8 log_max_memic_addr_alignment[0x8]; 672 673 u8 memic_bar_start_addr[0x40]; 674 675 u8 memic_bar_size[0x20]; 676 677 u8 max_memic_size[0x20]; 678 679 u8 reserved_at_c0[0x740]; 680 }; 681 682 enum { 683 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 684 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 690 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 691 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 692 }; 693 694 enum { 695 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 696 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 702 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 703 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 704 }; 705 706 struct mlx5_ifc_atomic_caps_bits { 707 u8 reserved_at_0[0x40]; 708 709 u8 atomic_req_8B_endianness_mode[0x2]; 710 u8 reserved_at_42[0x4]; 711 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 712 713 u8 reserved_at_47[0x19]; 714 715 u8 reserved_at_60[0x20]; 716 717 u8 reserved_at_80[0x10]; 718 u8 atomic_operations[0x10]; 719 720 u8 reserved_at_a0[0x10]; 721 u8 atomic_size_qp[0x10]; 722 723 u8 reserved_at_c0[0x10]; 724 u8 atomic_size_dc[0x10]; 725 726 u8 reserved_at_e0[0x720]; 727 }; 728 729 struct mlx5_ifc_odp_cap_bits { 730 u8 reserved_at_0[0x40]; 731 732 u8 sig[0x1]; 733 u8 reserved_at_41[0x1f]; 734 735 u8 reserved_at_60[0x20]; 736 737 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 738 739 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 740 741 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 742 743 u8 reserved_at_e0[0x720]; 744 }; 745 746 struct mlx5_ifc_calc_op { 747 u8 reserved_at_0[0x10]; 748 u8 reserved_at_10[0x9]; 749 u8 op_swap_endianness[0x1]; 750 u8 op_min[0x1]; 751 u8 op_xor[0x1]; 752 u8 op_or[0x1]; 753 u8 op_and[0x1]; 754 u8 op_max[0x1]; 755 u8 op_add[0x1]; 756 }; 757 758 struct mlx5_ifc_vector_calc_cap_bits { 759 u8 calc_matrix[0x1]; 760 u8 reserved_at_1[0x1f]; 761 u8 reserved_at_20[0x8]; 762 u8 max_vec_count[0x8]; 763 u8 reserved_at_30[0xd]; 764 u8 max_chunk_size[0x3]; 765 struct mlx5_ifc_calc_op calc0; 766 struct mlx5_ifc_calc_op calc1; 767 struct mlx5_ifc_calc_op calc2; 768 struct mlx5_ifc_calc_op calc3; 769 770 u8 reserved_at_e0[0x720]; 771 }; 772 773 enum { 774 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 775 MLX5_WQ_TYPE_CYCLIC = 0x1, 776 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 777 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 778 }; 779 780 enum { 781 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 782 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 783 }; 784 785 enum { 786 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 787 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 788 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 789 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 790 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 791 }; 792 793 enum { 794 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 795 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 796 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 797 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 798 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 799 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 800 }; 801 802 enum { 803 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 804 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 805 }; 806 807 enum { 808 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 809 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 810 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 811 }; 812 813 enum { 814 MLX5_CAP_PORT_TYPE_IB = 0x0, 815 MLX5_CAP_PORT_TYPE_ETH = 0x1, 816 }; 817 818 enum { 819 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 820 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 821 MLX5_CAP_UMR_FENCE_NONE = 0x2, 822 }; 823 824 struct mlx5_ifc_cmd_hca_cap_bits { 825 u8 reserved_at_0[0x30]; 826 u8 vhca_id[0x10]; 827 828 u8 reserved_at_40[0x40]; 829 830 u8 log_max_srq_sz[0x8]; 831 u8 log_max_qp_sz[0x8]; 832 u8 reserved_at_90[0xb]; 833 u8 log_max_qp[0x5]; 834 835 u8 reserved_at_a0[0xb]; 836 u8 log_max_srq[0x5]; 837 u8 reserved_at_b0[0x10]; 838 839 u8 reserved_at_c0[0x8]; 840 u8 log_max_cq_sz[0x8]; 841 u8 reserved_at_d0[0xb]; 842 u8 log_max_cq[0x5]; 843 844 u8 log_max_eq_sz[0x8]; 845 u8 reserved_at_e8[0x2]; 846 u8 log_max_mkey[0x6]; 847 u8 reserved_at_f0[0xc]; 848 u8 log_max_eq[0x4]; 849 850 u8 max_indirection[0x8]; 851 u8 fixed_buffer_size[0x1]; 852 u8 log_max_mrw_sz[0x7]; 853 u8 force_teardown[0x1]; 854 u8 reserved_at_111[0x1]; 855 u8 log_max_bsf_list_size[0x6]; 856 u8 umr_extended_translation_offset[0x1]; 857 u8 null_mkey[0x1]; 858 u8 log_max_klm_list_size[0x6]; 859 860 u8 reserved_at_120[0xa]; 861 u8 log_max_ra_req_dc[0x6]; 862 u8 reserved_at_130[0xa]; 863 u8 log_max_ra_res_dc[0x6]; 864 865 u8 reserved_at_140[0xa]; 866 u8 log_max_ra_req_qp[0x6]; 867 u8 reserved_at_150[0xa]; 868 u8 log_max_ra_res_qp[0x6]; 869 870 u8 end_pad[0x1]; 871 u8 cc_query_allowed[0x1]; 872 u8 cc_modify_allowed[0x1]; 873 u8 start_pad[0x1]; 874 u8 cache_line_128byte[0x1]; 875 u8 reserved_at_165[0xa]; 876 u8 qcam_reg[0x1]; 877 u8 gid_table_size[0x10]; 878 879 u8 out_of_seq_cnt[0x1]; 880 u8 vport_counters[0x1]; 881 u8 retransmission_q_counters[0x1]; 882 u8 debug[0x1]; 883 u8 modify_rq_counter_set_id[0x1]; 884 u8 rq_delay_drop[0x1]; 885 u8 max_qp_cnt[0xa]; 886 u8 pkey_table_size[0x10]; 887 888 u8 vport_group_manager[0x1]; 889 u8 vhca_group_manager[0x1]; 890 u8 ib_virt[0x1]; 891 u8 eth_virt[0x1]; 892 u8 vnic_env_queue_counters[0x1]; 893 u8 ets[0x1]; 894 u8 nic_flow_table[0x1]; 895 u8 eswitch_flow_table[0x1]; 896 u8 device_memory[0x1]; 897 u8 mcam_reg[0x1]; 898 u8 pcam_reg[0x1]; 899 u8 local_ca_ack_delay[0x5]; 900 u8 port_module_event[0x1]; 901 u8 enhanced_error_q_counters[0x1]; 902 u8 ports_check[0x1]; 903 u8 reserved_at_1b3[0x1]; 904 u8 disable_link_up[0x1]; 905 u8 beacon_led[0x1]; 906 u8 port_type[0x2]; 907 u8 num_ports[0x8]; 908 909 u8 reserved_at_1c0[0x1]; 910 u8 pps[0x1]; 911 u8 pps_modify[0x1]; 912 u8 log_max_msg[0x5]; 913 u8 reserved_at_1c8[0x4]; 914 u8 max_tc[0x4]; 915 u8 reserved_at_1d0[0x1]; 916 u8 dcbx[0x1]; 917 u8 general_notification_event[0x1]; 918 u8 reserved_at_1d3[0x2]; 919 u8 fpga[0x1]; 920 u8 rol_s[0x1]; 921 u8 rol_g[0x1]; 922 u8 reserved_at_1d8[0x1]; 923 u8 wol_s[0x1]; 924 u8 wol_g[0x1]; 925 u8 wol_a[0x1]; 926 u8 wol_b[0x1]; 927 u8 wol_m[0x1]; 928 u8 wol_u[0x1]; 929 u8 wol_p[0x1]; 930 931 u8 stat_rate_support[0x10]; 932 u8 reserved_at_1f0[0xc]; 933 u8 cqe_version[0x4]; 934 935 u8 compact_address_vector[0x1]; 936 u8 striding_rq[0x1]; 937 u8 reserved_at_202[0x1]; 938 u8 ipoib_enhanced_offloads[0x1]; 939 u8 ipoib_basic_offloads[0x1]; 940 u8 reserved_at_205[0x1]; 941 u8 repeated_block_disabled[0x1]; 942 u8 umr_modify_entity_size_disabled[0x1]; 943 u8 umr_modify_atomic_disabled[0x1]; 944 u8 umr_indirect_mkey_disabled[0x1]; 945 u8 umr_fence[0x2]; 946 u8 reserved_at_20c[0x3]; 947 u8 drain_sigerr[0x1]; 948 u8 cmdif_checksum[0x2]; 949 u8 sigerr_cqe[0x1]; 950 u8 reserved_at_213[0x1]; 951 u8 wq_signature[0x1]; 952 u8 sctr_data_cqe[0x1]; 953 u8 reserved_at_216[0x1]; 954 u8 sho[0x1]; 955 u8 tph[0x1]; 956 u8 rf[0x1]; 957 u8 dct[0x1]; 958 u8 qos[0x1]; 959 u8 eth_net_offloads[0x1]; 960 u8 roce[0x1]; 961 u8 atomic[0x1]; 962 u8 reserved_at_21f[0x1]; 963 964 u8 cq_oi[0x1]; 965 u8 cq_resize[0x1]; 966 u8 cq_moderation[0x1]; 967 u8 reserved_at_223[0x3]; 968 u8 cq_eq_remap[0x1]; 969 u8 pg[0x1]; 970 u8 block_lb_mc[0x1]; 971 u8 reserved_at_229[0x1]; 972 u8 scqe_break_moderation[0x1]; 973 u8 cq_period_start_from_cqe[0x1]; 974 u8 cd[0x1]; 975 u8 reserved_at_22d[0x1]; 976 u8 apm[0x1]; 977 u8 vector_calc[0x1]; 978 u8 umr_ptr_rlky[0x1]; 979 u8 imaicl[0x1]; 980 u8 reserved_at_232[0x4]; 981 u8 qkv[0x1]; 982 u8 pkv[0x1]; 983 u8 set_deth_sqpn[0x1]; 984 u8 reserved_at_239[0x3]; 985 u8 xrc[0x1]; 986 u8 ud[0x1]; 987 u8 uc[0x1]; 988 u8 rc[0x1]; 989 990 u8 uar_4k[0x1]; 991 u8 reserved_at_241[0x9]; 992 u8 uar_sz[0x6]; 993 u8 reserved_at_250[0x8]; 994 u8 log_pg_sz[0x8]; 995 996 u8 bf[0x1]; 997 u8 driver_version[0x1]; 998 u8 pad_tx_eth_packet[0x1]; 999 u8 reserved_at_263[0x8]; 1000 u8 log_bf_reg_size[0x5]; 1001 1002 u8 reserved_at_270[0xb]; 1003 u8 lag_master[0x1]; 1004 u8 num_lag_ports[0x4]; 1005 1006 u8 reserved_at_280[0x10]; 1007 u8 max_wqe_sz_sq[0x10]; 1008 1009 u8 reserved_at_2a0[0x10]; 1010 u8 max_wqe_sz_rq[0x10]; 1011 1012 u8 max_flow_counter_31_16[0x10]; 1013 u8 max_wqe_sz_sq_dc[0x10]; 1014 1015 u8 reserved_at_2e0[0x7]; 1016 u8 max_qp_mcg[0x19]; 1017 1018 u8 reserved_at_300[0x18]; 1019 u8 log_max_mcg[0x8]; 1020 1021 u8 reserved_at_320[0x3]; 1022 u8 log_max_transport_domain[0x5]; 1023 u8 reserved_at_328[0x3]; 1024 u8 log_max_pd[0x5]; 1025 u8 reserved_at_330[0xb]; 1026 u8 log_max_xrcd[0x5]; 1027 1028 u8 nic_receive_steering_discard[0x1]; 1029 u8 receive_discard_vport_down[0x1]; 1030 u8 transmit_discard_vport_down[0x1]; 1031 u8 reserved_at_343[0x5]; 1032 u8 log_max_flow_counter_bulk[0x8]; 1033 u8 max_flow_counter_15_0[0x10]; 1034 1035 1036 u8 reserved_at_360[0x3]; 1037 u8 log_max_rq[0x5]; 1038 u8 reserved_at_368[0x3]; 1039 u8 log_max_sq[0x5]; 1040 u8 reserved_at_370[0x3]; 1041 u8 log_max_tir[0x5]; 1042 u8 reserved_at_378[0x3]; 1043 u8 log_max_tis[0x5]; 1044 1045 u8 basic_cyclic_rcv_wqe[0x1]; 1046 u8 reserved_at_381[0x2]; 1047 u8 log_max_rmp[0x5]; 1048 u8 reserved_at_388[0x3]; 1049 u8 log_max_rqt[0x5]; 1050 u8 reserved_at_390[0x3]; 1051 u8 log_max_rqt_size[0x5]; 1052 u8 reserved_at_398[0x3]; 1053 u8 log_max_tis_per_sq[0x5]; 1054 1055 u8 ext_stride_num_range[0x1]; 1056 u8 reserved_at_3a1[0x2]; 1057 u8 log_max_stride_sz_rq[0x5]; 1058 u8 reserved_at_3a8[0x3]; 1059 u8 log_min_stride_sz_rq[0x5]; 1060 u8 reserved_at_3b0[0x3]; 1061 u8 log_max_stride_sz_sq[0x5]; 1062 u8 reserved_at_3b8[0x3]; 1063 u8 log_min_stride_sz_sq[0x5]; 1064 1065 u8 hairpin[0x1]; 1066 u8 reserved_at_3c1[0x2]; 1067 u8 log_max_hairpin_queues[0x5]; 1068 u8 reserved_at_3c8[0x3]; 1069 u8 log_max_hairpin_wq_data_sz[0x5]; 1070 u8 reserved_at_3d0[0x3]; 1071 u8 log_max_hairpin_num_packets[0x5]; 1072 u8 reserved_at_3d8[0x3]; 1073 u8 log_max_wq_sz[0x5]; 1074 1075 u8 nic_vport_change_event[0x1]; 1076 u8 disable_local_lb_uc[0x1]; 1077 u8 disable_local_lb_mc[0x1]; 1078 u8 log_min_hairpin_wq_data_sz[0x5]; 1079 u8 reserved_at_3e8[0x3]; 1080 u8 log_max_vlan_list[0x5]; 1081 u8 reserved_at_3f0[0x3]; 1082 u8 log_max_current_mc_list[0x5]; 1083 u8 reserved_at_3f8[0x3]; 1084 u8 log_max_current_uc_list[0x5]; 1085 1086 u8 reserved_at_400[0x80]; 1087 1088 u8 reserved_at_480[0x3]; 1089 u8 log_max_l2_table[0x5]; 1090 u8 reserved_at_488[0x8]; 1091 u8 log_uar_page_sz[0x10]; 1092 1093 u8 reserved_at_4a0[0x20]; 1094 u8 device_frequency_mhz[0x20]; 1095 u8 device_frequency_khz[0x20]; 1096 1097 u8 reserved_at_500[0x20]; 1098 u8 num_of_uars_per_page[0x20]; 1099 u8 reserved_at_540[0x40]; 1100 1101 u8 reserved_at_580[0x3d]; 1102 u8 cqe_128_always[0x1]; 1103 u8 cqe_compression_128[0x1]; 1104 u8 cqe_compression[0x1]; 1105 1106 u8 cqe_compression_timeout[0x10]; 1107 u8 cqe_compression_max_num[0x10]; 1108 1109 u8 reserved_at_5e0[0x10]; 1110 u8 tag_matching[0x1]; 1111 u8 rndv_offload_rc[0x1]; 1112 u8 rndv_offload_dc[0x1]; 1113 u8 log_tag_matching_list_sz[0x5]; 1114 u8 reserved_at_5f8[0x3]; 1115 u8 log_max_xrq[0x5]; 1116 1117 u8 affiliate_nic_vport_criteria[0x8]; 1118 u8 native_port_num[0x8]; 1119 u8 num_vhca_ports[0x8]; 1120 u8 reserved_at_618[0x6]; 1121 u8 sw_owner_id[0x1]; 1122 u8 reserved_at_61f[0x1e1]; 1123 }; 1124 1125 enum mlx5_flow_destination_type { 1126 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1127 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1128 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1129 1130 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1131 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1132 }; 1133 1134 struct mlx5_ifc_dest_format_struct_bits { 1135 u8 destination_type[0x8]; 1136 u8 destination_id[0x18]; 1137 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1138 u8 reserved_at_21[0xf]; 1139 u8 destination_eswitch_owner_vhca_id[0x10]; 1140 }; 1141 1142 struct mlx5_ifc_flow_counter_list_bits { 1143 u8 flow_counter_id[0x20]; 1144 1145 u8 reserved_at_20[0x20]; 1146 }; 1147 1148 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1149 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1150 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1151 u8 reserved_at_0[0x40]; 1152 }; 1153 1154 struct mlx5_ifc_fte_match_param_bits { 1155 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1156 1157 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1158 1159 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1160 1161 u8 reserved_at_600[0xa00]; 1162 }; 1163 1164 enum { 1165 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1166 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1167 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1168 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1169 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1170 }; 1171 1172 struct mlx5_ifc_rx_hash_field_select_bits { 1173 u8 l3_prot_type[0x1]; 1174 u8 l4_prot_type[0x1]; 1175 u8 selected_fields[0x1e]; 1176 }; 1177 1178 enum { 1179 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1180 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1181 }; 1182 1183 enum { 1184 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1185 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1186 }; 1187 1188 struct mlx5_ifc_wq_bits { 1189 u8 wq_type[0x4]; 1190 u8 wq_signature[0x1]; 1191 u8 end_padding_mode[0x2]; 1192 u8 cd_slave[0x1]; 1193 u8 reserved_at_8[0x18]; 1194 1195 u8 hds_skip_first_sge[0x1]; 1196 u8 log2_hds_buf_size[0x3]; 1197 u8 reserved_at_24[0x7]; 1198 u8 page_offset[0x5]; 1199 u8 lwm[0x10]; 1200 1201 u8 reserved_at_40[0x8]; 1202 u8 pd[0x18]; 1203 1204 u8 reserved_at_60[0x8]; 1205 u8 uar_page[0x18]; 1206 1207 u8 dbr_addr[0x40]; 1208 1209 u8 hw_counter[0x20]; 1210 1211 u8 sw_counter[0x20]; 1212 1213 u8 reserved_at_100[0xc]; 1214 u8 log_wq_stride[0x4]; 1215 u8 reserved_at_110[0x3]; 1216 u8 log_wq_pg_sz[0x5]; 1217 u8 reserved_at_118[0x3]; 1218 u8 log_wq_sz[0x5]; 1219 1220 u8 reserved_at_120[0x3]; 1221 u8 log_hairpin_num_packets[0x5]; 1222 u8 reserved_at_128[0x3]; 1223 u8 log_hairpin_data_sz[0x5]; 1224 1225 u8 reserved_at_130[0x4]; 1226 u8 log_wqe_num_of_strides[0x4]; 1227 u8 two_byte_shift_en[0x1]; 1228 u8 reserved_at_139[0x4]; 1229 u8 log_wqe_stride_size[0x3]; 1230 1231 u8 reserved_at_140[0x4c0]; 1232 1233 struct mlx5_ifc_cmd_pas_bits pas[0]; 1234 }; 1235 1236 struct mlx5_ifc_rq_num_bits { 1237 u8 reserved_at_0[0x8]; 1238 u8 rq_num[0x18]; 1239 }; 1240 1241 struct mlx5_ifc_mac_address_layout_bits { 1242 u8 reserved_at_0[0x10]; 1243 u8 mac_addr_47_32[0x10]; 1244 1245 u8 mac_addr_31_0[0x20]; 1246 }; 1247 1248 struct mlx5_ifc_vlan_layout_bits { 1249 u8 reserved_at_0[0x14]; 1250 u8 vlan[0x0c]; 1251 1252 u8 reserved_at_20[0x20]; 1253 }; 1254 1255 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1256 u8 reserved_at_0[0xa0]; 1257 1258 u8 min_time_between_cnps[0x20]; 1259 1260 u8 reserved_at_c0[0x12]; 1261 u8 cnp_dscp[0x6]; 1262 u8 reserved_at_d8[0x4]; 1263 u8 cnp_prio_mode[0x1]; 1264 u8 cnp_802p_prio[0x3]; 1265 1266 u8 reserved_at_e0[0x720]; 1267 }; 1268 1269 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1270 u8 reserved_at_0[0x60]; 1271 1272 u8 reserved_at_60[0x4]; 1273 u8 clamp_tgt_rate[0x1]; 1274 u8 reserved_at_65[0x3]; 1275 u8 clamp_tgt_rate_after_time_inc[0x1]; 1276 u8 reserved_at_69[0x17]; 1277 1278 u8 reserved_at_80[0x20]; 1279 1280 u8 rpg_time_reset[0x20]; 1281 1282 u8 rpg_byte_reset[0x20]; 1283 1284 u8 rpg_threshold[0x20]; 1285 1286 u8 rpg_max_rate[0x20]; 1287 1288 u8 rpg_ai_rate[0x20]; 1289 1290 u8 rpg_hai_rate[0x20]; 1291 1292 u8 rpg_gd[0x20]; 1293 1294 u8 rpg_min_dec_fac[0x20]; 1295 1296 u8 rpg_min_rate[0x20]; 1297 1298 u8 reserved_at_1c0[0xe0]; 1299 1300 u8 rate_to_set_on_first_cnp[0x20]; 1301 1302 u8 dce_tcp_g[0x20]; 1303 1304 u8 dce_tcp_rtt[0x20]; 1305 1306 u8 rate_reduce_monitor_period[0x20]; 1307 1308 u8 reserved_at_320[0x20]; 1309 1310 u8 initial_alpha_value[0x20]; 1311 1312 u8 reserved_at_360[0x4a0]; 1313 }; 1314 1315 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1316 u8 reserved_at_0[0x80]; 1317 1318 u8 rppp_max_rps[0x20]; 1319 1320 u8 rpg_time_reset[0x20]; 1321 1322 u8 rpg_byte_reset[0x20]; 1323 1324 u8 rpg_threshold[0x20]; 1325 1326 u8 rpg_max_rate[0x20]; 1327 1328 u8 rpg_ai_rate[0x20]; 1329 1330 u8 rpg_hai_rate[0x20]; 1331 1332 u8 rpg_gd[0x20]; 1333 1334 u8 rpg_min_dec_fac[0x20]; 1335 1336 u8 rpg_min_rate[0x20]; 1337 1338 u8 reserved_at_1c0[0x640]; 1339 }; 1340 1341 enum { 1342 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1343 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1344 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1345 }; 1346 1347 struct mlx5_ifc_resize_field_select_bits { 1348 u8 resize_field_select[0x20]; 1349 }; 1350 1351 enum { 1352 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1353 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1354 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1355 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1356 }; 1357 1358 struct mlx5_ifc_modify_field_select_bits { 1359 u8 modify_field_select[0x20]; 1360 }; 1361 1362 struct mlx5_ifc_field_select_r_roce_np_bits { 1363 u8 field_select_r_roce_np[0x20]; 1364 }; 1365 1366 struct mlx5_ifc_field_select_r_roce_rp_bits { 1367 u8 field_select_r_roce_rp[0x20]; 1368 }; 1369 1370 enum { 1371 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1375 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1376 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1377 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1378 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1379 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1380 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1381 }; 1382 1383 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1384 u8 field_select_8021qaurp[0x20]; 1385 }; 1386 1387 struct mlx5_ifc_phys_layer_cntrs_bits { 1388 u8 time_since_last_clear_high[0x20]; 1389 1390 u8 time_since_last_clear_low[0x20]; 1391 1392 u8 symbol_errors_high[0x20]; 1393 1394 u8 symbol_errors_low[0x20]; 1395 1396 u8 sync_headers_errors_high[0x20]; 1397 1398 u8 sync_headers_errors_low[0x20]; 1399 1400 u8 edpl_bip_errors_lane0_high[0x20]; 1401 1402 u8 edpl_bip_errors_lane0_low[0x20]; 1403 1404 u8 edpl_bip_errors_lane1_high[0x20]; 1405 1406 u8 edpl_bip_errors_lane1_low[0x20]; 1407 1408 u8 edpl_bip_errors_lane2_high[0x20]; 1409 1410 u8 edpl_bip_errors_lane2_low[0x20]; 1411 1412 u8 edpl_bip_errors_lane3_high[0x20]; 1413 1414 u8 edpl_bip_errors_lane3_low[0x20]; 1415 1416 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1417 1418 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1419 1420 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1421 1422 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1423 1424 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1425 1426 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1427 1428 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1429 1430 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1431 1432 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1433 1434 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1435 1436 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1437 1438 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1439 1440 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1441 1442 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1443 1444 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1445 1446 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1447 1448 u8 rs_fec_corrected_blocks_high[0x20]; 1449 1450 u8 rs_fec_corrected_blocks_low[0x20]; 1451 1452 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1453 1454 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1455 1456 u8 rs_fec_no_errors_blocks_high[0x20]; 1457 1458 u8 rs_fec_no_errors_blocks_low[0x20]; 1459 1460 u8 rs_fec_single_error_blocks_high[0x20]; 1461 1462 u8 rs_fec_single_error_blocks_low[0x20]; 1463 1464 u8 rs_fec_corrected_symbols_total_high[0x20]; 1465 1466 u8 rs_fec_corrected_symbols_total_low[0x20]; 1467 1468 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1469 1470 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1471 1472 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1473 1474 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1475 1476 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1477 1478 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1479 1480 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1481 1482 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1483 1484 u8 link_down_events[0x20]; 1485 1486 u8 successful_recovery_events[0x20]; 1487 1488 u8 reserved_at_640[0x180]; 1489 }; 1490 1491 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1492 u8 time_since_last_clear_high[0x20]; 1493 1494 u8 time_since_last_clear_low[0x20]; 1495 1496 u8 phy_received_bits_high[0x20]; 1497 1498 u8 phy_received_bits_low[0x20]; 1499 1500 u8 phy_symbol_errors_high[0x20]; 1501 1502 u8 phy_symbol_errors_low[0x20]; 1503 1504 u8 phy_corrected_bits_high[0x20]; 1505 1506 u8 phy_corrected_bits_low[0x20]; 1507 1508 u8 phy_corrected_bits_lane0_high[0x20]; 1509 1510 u8 phy_corrected_bits_lane0_low[0x20]; 1511 1512 u8 phy_corrected_bits_lane1_high[0x20]; 1513 1514 u8 phy_corrected_bits_lane1_low[0x20]; 1515 1516 u8 phy_corrected_bits_lane2_high[0x20]; 1517 1518 u8 phy_corrected_bits_lane2_low[0x20]; 1519 1520 u8 phy_corrected_bits_lane3_high[0x20]; 1521 1522 u8 phy_corrected_bits_lane3_low[0x20]; 1523 1524 u8 reserved_at_200[0x5c0]; 1525 }; 1526 1527 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1528 u8 symbol_error_counter[0x10]; 1529 1530 u8 link_error_recovery_counter[0x8]; 1531 1532 u8 link_downed_counter[0x8]; 1533 1534 u8 port_rcv_errors[0x10]; 1535 1536 u8 port_rcv_remote_physical_errors[0x10]; 1537 1538 u8 port_rcv_switch_relay_errors[0x10]; 1539 1540 u8 port_xmit_discards[0x10]; 1541 1542 u8 port_xmit_constraint_errors[0x8]; 1543 1544 u8 port_rcv_constraint_errors[0x8]; 1545 1546 u8 reserved_at_70[0x8]; 1547 1548 u8 link_overrun_errors[0x8]; 1549 1550 u8 reserved_at_80[0x10]; 1551 1552 u8 vl_15_dropped[0x10]; 1553 1554 u8 reserved_at_a0[0x80]; 1555 1556 u8 port_xmit_wait[0x20]; 1557 }; 1558 1559 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1560 u8 transmit_queue_high[0x20]; 1561 1562 u8 transmit_queue_low[0x20]; 1563 1564 u8 reserved_at_40[0x780]; 1565 }; 1566 1567 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1568 u8 rx_octets_high[0x20]; 1569 1570 u8 rx_octets_low[0x20]; 1571 1572 u8 reserved_at_40[0xc0]; 1573 1574 u8 rx_frames_high[0x20]; 1575 1576 u8 rx_frames_low[0x20]; 1577 1578 u8 tx_octets_high[0x20]; 1579 1580 u8 tx_octets_low[0x20]; 1581 1582 u8 reserved_at_180[0xc0]; 1583 1584 u8 tx_frames_high[0x20]; 1585 1586 u8 tx_frames_low[0x20]; 1587 1588 u8 rx_pause_high[0x20]; 1589 1590 u8 rx_pause_low[0x20]; 1591 1592 u8 rx_pause_duration_high[0x20]; 1593 1594 u8 rx_pause_duration_low[0x20]; 1595 1596 u8 tx_pause_high[0x20]; 1597 1598 u8 tx_pause_low[0x20]; 1599 1600 u8 tx_pause_duration_high[0x20]; 1601 1602 u8 tx_pause_duration_low[0x20]; 1603 1604 u8 rx_pause_transition_high[0x20]; 1605 1606 u8 rx_pause_transition_low[0x20]; 1607 1608 u8 reserved_at_3c0[0x40]; 1609 1610 u8 device_stall_minor_watermark_cnt_high[0x20]; 1611 1612 u8 device_stall_minor_watermark_cnt_low[0x20]; 1613 1614 u8 device_stall_critical_watermark_cnt_high[0x20]; 1615 1616 u8 device_stall_critical_watermark_cnt_low[0x20]; 1617 1618 u8 reserved_at_480[0x340]; 1619 }; 1620 1621 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1622 u8 port_transmit_wait_high[0x20]; 1623 1624 u8 port_transmit_wait_low[0x20]; 1625 1626 u8 reserved_at_40[0x100]; 1627 1628 u8 rx_buffer_almost_full_high[0x20]; 1629 1630 u8 rx_buffer_almost_full_low[0x20]; 1631 1632 u8 rx_buffer_full_high[0x20]; 1633 1634 u8 rx_buffer_full_low[0x20]; 1635 1636 u8 reserved_at_1c0[0x600]; 1637 }; 1638 1639 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1640 u8 dot3stats_alignment_errors_high[0x20]; 1641 1642 u8 dot3stats_alignment_errors_low[0x20]; 1643 1644 u8 dot3stats_fcs_errors_high[0x20]; 1645 1646 u8 dot3stats_fcs_errors_low[0x20]; 1647 1648 u8 dot3stats_single_collision_frames_high[0x20]; 1649 1650 u8 dot3stats_single_collision_frames_low[0x20]; 1651 1652 u8 dot3stats_multiple_collision_frames_high[0x20]; 1653 1654 u8 dot3stats_multiple_collision_frames_low[0x20]; 1655 1656 u8 dot3stats_sqe_test_errors_high[0x20]; 1657 1658 u8 dot3stats_sqe_test_errors_low[0x20]; 1659 1660 u8 dot3stats_deferred_transmissions_high[0x20]; 1661 1662 u8 dot3stats_deferred_transmissions_low[0x20]; 1663 1664 u8 dot3stats_late_collisions_high[0x20]; 1665 1666 u8 dot3stats_late_collisions_low[0x20]; 1667 1668 u8 dot3stats_excessive_collisions_high[0x20]; 1669 1670 u8 dot3stats_excessive_collisions_low[0x20]; 1671 1672 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1673 1674 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1675 1676 u8 dot3stats_carrier_sense_errors_high[0x20]; 1677 1678 u8 dot3stats_carrier_sense_errors_low[0x20]; 1679 1680 u8 dot3stats_frame_too_longs_high[0x20]; 1681 1682 u8 dot3stats_frame_too_longs_low[0x20]; 1683 1684 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1685 1686 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1687 1688 u8 dot3stats_symbol_errors_high[0x20]; 1689 1690 u8 dot3stats_symbol_errors_low[0x20]; 1691 1692 u8 dot3control_in_unknown_opcodes_high[0x20]; 1693 1694 u8 dot3control_in_unknown_opcodes_low[0x20]; 1695 1696 u8 dot3in_pause_frames_high[0x20]; 1697 1698 u8 dot3in_pause_frames_low[0x20]; 1699 1700 u8 dot3out_pause_frames_high[0x20]; 1701 1702 u8 dot3out_pause_frames_low[0x20]; 1703 1704 u8 reserved_at_400[0x3c0]; 1705 }; 1706 1707 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1708 u8 ether_stats_drop_events_high[0x20]; 1709 1710 u8 ether_stats_drop_events_low[0x20]; 1711 1712 u8 ether_stats_octets_high[0x20]; 1713 1714 u8 ether_stats_octets_low[0x20]; 1715 1716 u8 ether_stats_pkts_high[0x20]; 1717 1718 u8 ether_stats_pkts_low[0x20]; 1719 1720 u8 ether_stats_broadcast_pkts_high[0x20]; 1721 1722 u8 ether_stats_broadcast_pkts_low[0x20]; 1723 1724 u8 ether_stats_multicast_pkts_high[0x20]; 1725 1726 u8 ether_stats_multicast_pkts_low[0x20]; 1727 1728 u8 ether_stats_crc_align_errors_high[0x20]; 1729 1730 u8 ether_stats_crc_align_errors_low[0x20]; 1731 1732 u8 ether_stats_undersize_pkts_high[0x20]; 1733 1734 u8 ether_stats_undersize_pkts_low[0x20]; 1735 1736 u8 ether_stats_oversize_pkts_high[0x20]; 1737 1738 u8 ether_stats_oversize_pkts_low[0x20]; 1739 1740 u8 ether_stats_fragments_high[0x20]; 1741 1742 u8 ether_stats_fragments_low[0x20]; 1743 1744 u8 ether_stats_jabbers_high[0x20]; 1745 1746 u8 ether_stats_jabbers_low[0x20]; 1747 1748 u8 ether_stats_collisions_high[0x20]; 1749 1750 u8 ether_stats_collisions_low[0x20]; 1751 1752 u8 ether_stats_pkts64octets_high[0x20]; 1753 1754 u8 ether_stats_pkts64octets_low[0x20]; 1755 1756 u8 ether_stats_pkts65to127octets_high[0x20]; 1757 1758 u8 ether_stats_pkts65to127octets_low[0x20]; 1759 1760 u8 ether_stats_pkts128to255octets_high[0x20]; 1761 1762 u8 ether_stats_pkts128to255octets_low[0x20]; 1763 1764 u8 ether_stats_pkts256to511octets_high[0x20]; 1765 1766 u8 ether_stats_pkts256to511octets_low[0x20]; 1767 1768 u8 ether_stats_pkts512to1023octets_high[0x20]; 1769 1770 u8 ether_stats_pkts512to1023octets_low[0x20]; 1771 1772 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1773 1774 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1775 1776 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1777 1778 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1779 1780 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1781 1782 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1783 1784 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1785 1786 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1787 1788 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1789 1790 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1791 1792 u8 reserved_at_540[0x280]; 1793 }; 1794 1795 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1796 u8 if_in_octets_high[0x20]; 1797 1798 u8 if_in_octets_low[0x20]; 1799 1800 u8 if_in_ucast_pkts_high[0x20]; 1801 1802 u8 if_in_ucast_pkts_low[0x20]; 1803 1804 u8 if_in_discards_high[0x20]; 1805 1806 u8 if_in_discards_low[0x20]; 1807 1808 u8 if_in_errors_high[0x20]; 1809 1810 u8 if_in_errors_low[0x20]; 1811 1812 u8 if_in_unknown_protos_high[0x20]; 1813 1814 u8 if_in_unknown_protos_low[0x20]; 1815 1816 u8 if_out_octets_high[0x20]; 1817 1818 u8 if_out_octets_low[0x20]; 1819 1820 u8 if_out_ucast_pkts_high[0x20]; 1821 1822 u8 if_out_ucast_pkts_low[0x20]; 1823 1824 u8 if_out_discards_high[0x20]; 1825 1826 u8 if_out_discards_low[0x20]; 1827 1828 u8 if_out_errors_high[0x20]; 1829 1830 u8 if_out_errors_low[0x20]; 1831 1832 u8 if_in_multicast_pkts_high[0x20]; 1833 1834 u8 if_in_multicast_pkts_low[0x20]; 1835 1836 u8 if_in_broadcast_pkts_high[0x20]; 1837 1838 u8 if_in_broadcast_pkts_low[0x20]; 1839 1840 u8 if_out_multicast_pkts_high[0x20]; 1841 1842 u8 if_out_multicast_pkts_low[0x20]; 1843 1844 u8 if_out_broadcast_pkts_high[0x20]; 1845 1846 u8 if_out_broadcast_pkts_low[0x20]; 1847 1848 u8 reserved_at_340[0x480]; 1849 }; 1850 1851 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1852 u8 a_frames_transmitted_ok_high[0x20]; 1853 1854 u8 a_frames_transmitted_ok_low[0x20]; 1855 1856 u8 a_frames_received_ok_high[0x20]; 1857 1858 u8 a_frames_received_ok_low[0x20]; 1859 1860 u8 a_frame_check_sequence_errors_high[0x20]; 1861 1862 u8 a_frame_check_sequence_errors_low[0x20]; 1863 1864 u8 a_alignment_errors_high[0x20]; 1865 1866 u8 a_alignment_errors_low[0x20]; 1867 1868 u8 a_octets_transmitted_ok_high[0x20]; 1869 1870 u8 a_octets_transmitted_ok_low[0x20]; 1871 1872 u8 a_octets_received_ok_high[0x20]; 1873 1874 u8 a_octets_received_ok_low[0x20]; 1875 1876 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1877 1878 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1879 1880 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1881 1882 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1883 1884 u8 a_multicast_frames_received_ok_high[0x20]; 1885 1886 u8 a_multicast_frames_received_ok_low[0x20]; 1887 1888 u8 a_broadcast_frames_received_ok_high[0x20]; 1889 1890 u8 a_broadcast_frames_received_ok_low[0x20]; 1891 1892 u8 a_in_range_length_errors_high[0x20]; 1893 1894 u8 a_in_range_length_errors_low[0x20]; 1895 1896 u8 a_out_of_range_length_field_high[0x20]; 1897 1898 u8 a_out_of_range_length_field_low[0x20]; 1899 1900 u8 a_frame_too_long_errors_high[0x20]; 1901 1902 u8 a_frame_too_long_errors_low[0x20]; 1903 1904 u8 a_symbol_error_during_carrier_high[0x20]; 1905 1906 u8 a_symbol_error_during_carrier_low[0x20]; 1907 1908 u8 a_mac_control_frames_transmitted_high[0x20]; 1909 1910 u8 a_mac_control_frames_transmitted_low[0x20]; 1911 1912 u8 a_mac_control_frames_received_high[0x20]; 1913 1914 u8 a_mac_control_frames_received_low[0x20]; 1915 1916 u8 a_unsupported_opcodes_received_high[0x20]; 1917 1918 u8 a_unsupported_opcodes_received_low[0x20]; 1919 1920 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1921 1922 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1923 1924 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1925 1926 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1927 1928 u8 reserved_at_4c0[0x300]; 1929 }; 1930 1931 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1932 u8 life_time_counter_high[0x20]; 1933 1934 u8 life_time_counter_low[0x20]; 1935 1936 u8 rx_errors[0x20]; 1937 1938 u8 tx_errors[0x20]; 1939 1940 u8 l0_to_recovery_eieos[0x20]; 1941 1942 u8 l0_to_recovery_ts[0x20]; 1943 1944 u8 l0_to_recovery_framing[0x20]; 1945 1946 u8 l0_to_recovery_retrain[0x20]; 1947 1948 u8 crc_error_dllp[0x20]; 1949 1950 u8 crc_error_tlp[0x20]; 1951 1952 u8 tx_overflow_buffer_pkt_high[0x20]; 1953 1954 u8 tx_overflow_buffer_pkt_low[0x20]; 1955 1956 u8 outbound_stalled_reads[0x20]; 1957 1958 u8 outbound_stalled_writes[0x20]; 1959 1960 u8 outbound_stalled_reads_events[0x20]; 1961 1962 u8 outbound_stalled_writes_events[0x20]; 1963 1964 u8 reserved_at_200[0x5c0]; 1965 }; 1966 1967 struct mlx5_ifc_cmd_inter_comp_event_bits { 1968 u8 command_completion_vector[0x20]; 1969 1970 u8 reserved_at_20[0xc0]; 1971 }; 1972 1973 struct mlx5_ifc_stall_vl_event_bits { 1974 u8 reserved_at_0[0x18]; 1975 u8 port_num[0x1]; 1976 u8 reserved_at_19[0x3]; 1977 u8 vl[0x4]; 1978 1979 u8 reserved_at_20[0xa0]; 1980 }; 1981 1982 struct mlx5_ifc_db_bf_congestion_event_bits { 1983 u8 event_subtype[0x8]; 1984 u8 reserved_at_8[0x8]; 1985 u8 congestion_level[0x8]; 1986 u8 reserved_at_18[0x8]; 1987 1988 u8 reserved_at_20[0xa0]; 1989 }; 1990 1991 struct mlx5_ifc_gpio_event_bits { 1992 u8 reserved_at_0[0x60]; 1993 1994 u8 gpio_event_hi[0x20]; 1995 1996 u8 gpio_event_lo[0x20]; 1997 1998 u8 reserved_at_a0[0x40]; 1999 }; 2000 2001 struct mlx5_ifc_port_state_change_event_bits { 2002 u8 reserved_at_0[0x40]; 2003 2004 u8 port_num[0x4]; 2005 u8 reserved_at_44[0x1c]; 2006 2007 u8 reserved_at_60[0x80]; 2008 }; 2009 2010 struct mlx5_ifc_dropped_packet_logged_bits { 2011 u8 reserved_at_0[0xe0]; 2012 }; 2013 2014 enum { 2015 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2016 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2017 }; 2018 2019 struct mlx5_ifc_cq_error_bits { 2020 u8 reserved_at_0[0x8]; 2021 u8 cqn[0x18]; 2022 2023 u8 reserved_at_20[0x20]; 2024 2025 u8 reserved_at_40[0x18]; 2026 u8 syndrome[0x8]; 2027 2028 u8 reserved_at_60[0x80]; 2029 }; 2030 2031 struct mlx5_ifc_rdma_page_fault_event_bits { 2032 u8 bytes_committed[0x20]; 2033 2034 u8 r_key[0x20]; 2035 2036 u8 reserved_at_40[0x10]; 2037 u8 packet_len[0x10]; 2038 2039 u8 rdma_op_len[0x20]; 2040 2041 u8 rdma_va[0x40]; 2042 2043 u8 reserved_at_c0[0x5]; 2044 u8 rdma[0x1]; 2045 u8 write[0x1]; 2046 u8 requestor[0x1]; 2047 u8 qp_number[0x18]; 2048 }; 2049 2050 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2051 u8 bytes_committed[0x20]; 2052 2053 u8 reserved_at_20[0x10]; 2054 u8 wqe_index[0x10]; 2055 2056 u8 reserved_at_40[0x10]; 2057 u8 len[0x10]; 2058 2059 u8 reserved_at_60[0x60]; 2060 2061 u8 reserved_at_c0[0x5]; 2062 u8 rdma[0x1]; 2063 u8 write_read[0x1]; 2064 u8 requestor[0x1]; 2065 u8 qpn[0x18]; 2066 }; 2067 2068 struct mlx5_ifc_qp_events_bits { 2069 u8 reserved_at_0[0xa0]; 2070 2071 u8 type[0x8]; 2072 u8 reserved_at_a8[0x18]; 2073 2074 u8 reserved_at_c0[0x8]; 2075 u8 qpn_rqn_sqn[0x18]; 2076 }; 2077 2078 struct mlx5_ifc_dct_events_bits { 2079 u8 reserved_at_0[0xc0]; 2080 2081 u8 reserved_at_c0[0x8]; 2082 u8 dct_number[0x18]; 2083 }; 2084 2085 struct mlx5_ifc_comp_event_bits { 2086 u8 reserved_at_0[0xc0]; 2087 2088 u8 reserved_at_c0[0x8]; 2089 u8 cq_number[0x18]; 2090 }; 2091 2092 enum { 2093 MLX5_QPC_STATE_RST = 0x0, 2094 MLX5_QPC_STATE_INIT = 0x1, 2095 MLX5_QPC_STATE_RTR = 0x2, 2096 MLX5_QPC_STATE_RTS = 0x3, 2097 MLX5_QPC_STATE_SQER = 0x4, 2098 MLX5_QPC_STATE_ERR = 0x6, 2099 MLX5_QPC_STATE_SQD = 0x7, 2100 MLX5_QPC_STATE_SUSPENDED = 0x9, 2101 }; 2102 2103 enum { 2104 MLX5_QPC_ST_RC = 0x0, 2105 MLX5_QPC_ST_UC = 0x1, 2106 MLX5_QPC_ST_UD = 0x2, 2107 MLX5_QPC_ST_XRC = 0x3, 2108 MLX5_QPC_ST_DCI = 0x5, 2109 MLX5_QPC_ST_QP0 = 0x7, 2110 MLX5_QPC_ST_QP1 = 0x8, 2111 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2112 MLX5_QPC_ST_REG_UMR = 0xc, 2113 }; 2114 2115 enum { 2116 MLX5_QPC_PM_STATE_ARMED = 0x0, 2117 MLX5_QPC_PM_STATE_REARM = 0x1, 2118 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2119 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2120 }; 2121 2122 enum { 2123 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2124 }; 2125 2126 enum { 2127 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2128 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2129 }; 2130 2131 enum { 2132 MLX5_QPC_MTU_256_BYTES = 0x1, 2133 MLX5_QPC_MTU_512_BYTES = 0x2, 2134 MLX5_QPC_MTU_1K_BYTES = 0x3, 2135 MLX5_QPC_MTU_2K_BYTES = 0x4, 2136 MLX5_QPC_MTU_4K_BYTES = 0x5, 2137 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2138 }; 2139 2140 enum { 2141 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2142 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2143 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2144 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2145 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2146 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2147 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2148 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2149 }; 2150 2151 enum { 2152 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2153 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2154 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2155 }; 2156 2157 enum { 2158 MLX5_QPC_CS_RES_DISABLE = 0x0, 2159 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2160 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2161 }; 2162 2163 struct mlx5_ifc_qpc_bits { 2164 u8 state[0x4]; 2165 u8 lag_tx_port_affinity[0x4]; 2166 u8 st[0x8]; 2167 u8 reserved_at_10[0x3]; 2168 u8 pm_state[0x2]; 2169 u8 reserved_at_15[0x3]; 2170 u8 offload_type[0x4]; 2171 u8 end_padding_mode[0x2]; 2172 u8 reserved_at_1e[0x2]; 2173 2174 u8 wq_signature[0x1]; 2175 u8 block_lb_mc[0x1]; 2176 u8 atomic_like_write_en[0x1]; 2177 u8 latency_sensitive[0x1]; 2178 u8 reserved_at_24[0x1]; 2179 u8 drain_sigerr[0x1]; 2180 u8 reserved_at_26[0x2]; 2181 u8 pd[0x18]; 2182 2183 u8 mtu[0x3]; 2184 u8 log_msg_max[0x5]; 2185 u8 reserved_at_48[0x1]; 2186 u8 log_rq_size[0x4]; 2187 u8 log_rq_stride[0x3]; 2188 u8 no_sq[0x1]; 2189 u8 log_sq_size[0x4]; 2190 u8 reserved_at_55[0x6]; 2191 u8 rlky[0x1]; 2192 u8 ulp_stateless_offload_mode[0x4]; 2193 2194 u8 counter_set_id[0x8]; 2195 u8 uar_page[0x18]; 2196 2197 u8 reserved_at_80[0x8]; 2198 u8 user_index[0x18]; 2199 2200 u8 reserved_at_a0[0x3]; 2201 u8 log_page_size[0x5]; 2202 u8 remote_qpn[0x18]; 2203 2204 struct mlx5_ifc_ads_bits primary_address_path; 2205 2206 struct mlx5_ifc_ads_bits secondary_address_path; 2207 2208 u8 log_ack_req_freq[0x4]; 2209 u8 reserved_at_384[0x4]; 2210 u8 log_sra_max[0x3]; 2211 u8 reserved_at_38b[0x2]; 2212 u8 retry_count[0x3]; 2213 u8 rnr_retry[0x3]; 2214 u8 reserved_at_393[0x1]; 2215 u8 fre[0x1]; 2216 u8 cur_rnr_retry[0x3]; 2217 u8 cur_retry_count[0x3]; 2218 u8 reserved_at_39b[0x5]; 2219 2220 u8 reserved_at_3a0[0x20]; 2221 2222 u8 reserved_at_3c0[0x8]; 2223 u8 next_send_psn[0x18]; 2224 2225 u8 reserved_at_3e0[0x8]; 2226 u8 cqn_snd[0x18]; 2227 2228 u8 reserved_at_400[0x8]; 2229 u8 deth_sqpn[0x18]; 2230 2231 u8 reserved_at_420[0x20]; 2232 2233 u8 reserved_at_440[0x8]; 2234 u8 last_acked_psn[0x18]; 2235 2236 u8 reserved_at_460[0x8]; 2237 u8 ssn[0x18]; 2238 2239 u8 reserved_at_480[0x8]; 2240 u8 log_rra_max[0x3]; 2241 u8 reserved_at_48b[0x1]; 2242 u8 atomic_mode[0x4]; 2243 u8 rre[0x1]; 2244 u8 rwe[0x1]; 2245 u8 rae[0x1]; 2246 u8 reserved_at_493[0x1]; 2247 u8 page_offset[0x6]; 2248 u8 reserved_at_49a[0x3]; 2249 u8 cd_slave_receive[0x1]; 2250 u8 cd_slave_send[0x1]; 2251 u8 cd_master[0x1]; 2252 2253 u8 reserved_at_4a0[0x3]; 2254 u8 min_rnr_nak[0x5]; 2255 u8 next_rcv_psn[0x18]; 2256 2257 u8 reserved_at_4c0[0x8]; 2258 u8 xrcd[0x18]; 2259 2260 u8 reserved_at_4e0[0x8]; 2261 u8 cqn_rcv[0x18]; 2262 2263 u8 dbr_addr[0x40]; 2264 2265 u8 q_key[0x20]; 2266 2267 u8 reserved_at_560[0x5]; 2268 u8 rq_type[0x3]; 2269 u8 srqn_rmpn_xrqn[0x18]; 2270 2271 u8 reserved_at_580[0x8]; 2272 u8 rmsn[0x18]; 2273 2274 u8 hw_sq_wqebb_counter[0x10]; 2275 u8 sw_sq_wqebb_counter[0x10]; 2276 2277 u8 hw_rq_counter[0x20]; 2278 2279 u8 sw_rq_counter[0x20]; 2280 2281 u8 reserved_at_600[0x20]; 2282 2283 u8 reserved_at_620[0xf]; 2284 u8 cgs[0x1]; 2285 u8 cs_req[0x8]; 2286 u8 cs_res[0x8]; 2287 2288 u8 dc_access_key[0x40]; 2289 2290 u8 reserved_at_680[0xc0]; 2291 }; 2292 2293 struct mlx5_ifc_roce_addr_layout_bits { 2294 u8 source_l3_address[16][0x8]; 2295 2296 u8 reserved_at_80[0x3]; 2297 u8 vlan_valid[0x1]; 2298 u8 vlan_id[0xc]; 2299 u8 source_mac_47_32[0x10]; 2300 2301 u8 source_mac_31_0[0x20]; 2302 2303 u8 reserved_at_c0[0x14]; 2304 u8 roce_l3_type[0x4]; 2305 u8 roce_version[0x8]; 2306 2307 u8 reserved_at_e0[0x20]; 2308 }; 2309 2310 union mlx5_ifc_hca_cap_union_bits { 2311 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2312 struct mlx5_ifc_odp_cap_bits odp_cap; 2313 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2314 struct mlx5_ifc_roce_cap_bits roce_cap; 2315 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2316 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2317 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2318 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2319 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2320 struct mlx5_ifc_qos_cap_bits qos_cap; 2321 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2322 u8 reserved_at_0[0x8000]; 2323 }; 2324 2325 enum { 2326 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2327 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2328 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2329 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2330 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2331 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2332 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2333 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2334 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2335 }; 2336 2337 struct mlx5_ifc_vlan_bits { 2338 u8 ethtype[0x10]; 2339 u8 prio[0x3]; 2340 u8 cfi[0x1]; 2341 u8 vid[0xc]; 2342 }; 2343 2344 struct mlx5_ifc_flow_context_bits { 2345 struct mlx5_ifc_vlan_bits push_vlan; 2346 2347 u8 group_id[0x20]; 2348 2349 u8 reserved_at_40[0x8]; 2350 u8 flow_tag[0x18]; 2351 2352 u8 reserved_at_60[0x10]; 2353 u8 action[0x10]; 2354 2355 u8 reserved_at_80[0x8]; 2356 u8 destination_list_size[0x18]; 2357 2358 u8 reserved_at_a0[0x8]; 2359 u8 flow_counter_list_size[0x18]; 2360 2361 u8 encap_id[0x20]; 2362 2363 u8 modify_header_id[0x20]; 2364 2365 u8 reserved_at_100[0x100]; 2366 2367 struct mlx5_ifc_fte_match_param_bits match_value; 2368 2369 u8 reserved_at_1200[0x600]; 2370 2371 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2372 }; 2373 2374 enum { 2375 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2376 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2377 }; 2378 2379 struct mlx5_ifc_xrc_srqc_bits { 2380 u8 state[0x4]; 2381 u8 log_xrc_srq_size[0x4]; 2382 u8 reserved_at_8[0x18]; 2383 2384 u8 wq_signature[0x1]; 2385 u8 cont_srq[0x1]; 2386 u8 reserved_at_22[0x1]; 2387 u8 rlky[0x1]; 2388 u8 basic_cyclic_rcv_wqe[0x1]; 2389 u8 log_rq_stride[0x3]; 2390 u8 xrcd[0x18]; 2391 2392 u8 page_offset[0x6]; 2393 u8 reserved_at_46[0x2]; 2394 u8 cqn[0x18]; 2395 2396 u8 reserved_at_60[0x20]; 2397 2398 u8 user_index_equal_xrc_srqn[0x1]; 2399 u8 reserved_at_81[0x1]; 2400 u8 log_page_size[0x6]; 2401 u8 user_index[0x18]; 2402 2403 u8 reserved_at_a0[0x20]; 2404 2405 u8 reserved_at_c0[0x8]; 2406 u8 pd[0x18]; 2407 2408 u8 lwm[0x10]; 2409 u8 wqe_cnt[0x10]; 2410 2411 u8 reserved_at_100[0x40]; 2412 2413 u8 db_record_addr_h[0x20]; 2414 2415 u8 db_record_addr_l[0x1e]; 2416 u8 reserved_at_17e[0x2]; 2417 2418 u8 reserved_at_180[0x80]; 2419 }; 2420 2421 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2422 u8 counter_error_queues[0x20]; 2423 2424 u8 total_error_queues[0x20]; 2425 2426 u8 send_queue_priority_update_flow[0x20]; 2427 2428 u8 reserved_at_60[0x20]; 2429 2430 u8 nic_receive_steering_discard[0x40]; 2431 2432 u8 receive_discard_vport_down[0x40]; 2433 2434 u8 transmit_discard_vport_down[0x40]; 2435 2436 u8 reserved_at_140[0xec0]; 2437 }; 2438 2439 struct mlx5_ifc_traffic_counter_bits { 2440 u8 packets[0x40]; 2441 2442 u8 octets[0x40]; 2443 }; 2444 2445 struct mlx5_ifc_tisc_bits { 2446 u8 strict_lag_tx_port_affinity[0x1]; 2447 u8 reserved_at_1[0x3]; 2448 u8 lag_tx_port_affinity[0x04]; 2449 2450 u8 reserved_at_8[0x4]; 2451 u8 prio[0x4]; 2452 u8 reserved_at_10[0x10]; 2453 2454 u8 reserved_at_20[0x100]; 2455 2456 u8 reserved_at_120[0x8]; 2457 u8 transport_domain[0x18]; 2458 2459 u8 reserved_at_140[0x8]; 2460 u8 underlay_qpn[0x18]; 2461 u8 reserved_at_160[0x3a0]; 2462 }; 2463 2464 enum { 2465 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2466 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2467 }; 2468 2469 enum { 2470 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2471 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2472 }; 2473 2474 enum { 2475 MLX5_RX_HASH_FN_NONE = 0x0, 2476 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2477 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2478 }; 2479 2480 enum { 2481 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2482 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2483 }; 2484 2485 struct mlx5_ifc_tirc_bits { 2486 u8 reserved_at_0[0x20]; 2487 2488 u8 disp_type[0x4]; 2489 u8 reserved_at_24[0x1c]; 2490 2491 u8 reserved_at_40[0x40]; 2492 2493 u8 reserved_at_80[0x4]; 2494 u8 lro_timeout_period_usecs[0x10]; 2495 u8 lro_enable_mask[0x4]; 2496 u8 lro_max_ip_payload_size[0x8]; 2497 2498 u8 reserved_at_a0[0x40]; 2499 2500 u8 reserved_at_e0[0x8]; 2501 u8 inline_rqn[0x18]; 2502 2503 u8 rx_hash_symmetric[0x1]; 2504 u8 reserved_at_101[0x1]; 2505 u8 tunneled_offload_en[0x1]; 2506 u8 reserved_at_103[0x5]; 2507 u8 indirect_table[0x18]; 2508 2509 u8 rx_hash_fn[0x4]; 2510 u8 reserved_at_124[0x2]; 2511 u8 self_lb_block[0x2]; 2512 u8 transport_domain[0x18]; 2513 2514 u8 rx_hash_toeplitz_key[10][0x20]; 2515 2516 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2517 2518 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2519 2520 u8 reserved_at_2c0[0x4c0]; 2521 }; 2522 2523 enum { 2524 MLX5_SRQC_STATE_GOOD = 0x0, 2525 MLX5_SRQC_STATE_ERROR = 0x1, 2526 }; 2527 2528 struct mlx5_ifc_srqc_bits { 2529 u8 state[0x4]; 2530 u8 log_srq_size[0x4]; 2531 u8 reserved_at_8[0x18]; 2532 2533 u8 wq_signature[0x1]; 2534 u8 cont_srq[0x1]; 2535 u8 reserved_at_22[0x1]; 2536 u8 rlky[0x1]; 2537 u8 reserved_at_24[0x1]; 2538 u8 log_rq_stride[0x3]; 2539 u8 xrcd[0x18]; 2540 2541 u8 page_offset[0x6]; 2542 u8 reserved_at_46[0x2]; 2543 u8 cqn[0x18]; 2544 2545 u8 reserved_at_60[0x20]; 2546 2547 u8 reserved_at_80[0x2]; 2548 u8 log_page_size[0x6]; 2549 u8 reserved_at_88[0x18]; 2550 2551 u8 reserved_at_a0[0x20]; 2552 2553 u8 reserved_at_c0[0x8]; 2554 u8 pd[0x18]; 2555 2556 u8 lwm[0x10]; 2557 u8 wqe_cnt[0x10]; 2558 2559 u8 reserved_at_100[0x40]; 2560 2561 u8 dbr_addr[0x40]; 2562 2563 u8 reserved_at_180[0x80]; 2564 }; 2565 2566 enum { 2567 MLX5_SQC_STATE_RST = 0x0, 2568 MLX5_SQC_STATE_RDY = 0x1, 2569 MLX5_SQC_STATE_ERR = 0x3, 2570 }; 2571 2572 struct mlx5_ifc_sqc_bits { 2573 u8 rlky[0x1]; 2574 u8 cd_master[0x1]; 2575 u8 fre[0x1]; 2576 u8 flush_in_error_en[0x1]; 2577 u8 allow_multi_pkt_send_wqe[0x1]; 2578 u8 min_wqe_inline_mode[0x3]; 2579 u8 state[0x4]; 2580 u8 reg_umr[0x1]; 2581 u8 allow_swp[0x1]; 2582 u8 hairpin[0x1]; 2583 u8 reserved_at_f[0x11]; 2584 2585 u8 reserved_at_20[0x8]; 2586 u8 user_index[0x18]; 2587 2588 u8 reserved_at_40[0x8]; 2589 u8 cqn[0x18]; 2590 2591 u8 reserved_at_60[0x8]; 2592 u8 hairpin_peer_rq[0x18]; 2593 2594 u8 reserved_at_80[0x10]; 2595 u8 hairpin_peer_vhca[0x10]; 2596 2597 u8 reserved_at_a0[0x50]; 2598 2599 u8 packet_pacing_rate_limit_index[0x10]; 2600 u8 tis_lst_sz[0x10]; 2601 u8 reserved_at_110[0x10]; 2602 2603 u8 reserved_at_120[0x40]; 2604 2605 u8 reserved_at_160[0x8]; 2606 u8 tis_num_0[0x18]; 2607 2608 struct mlx5_ifc_wq_bits wq; 2609 }; 2610 2611 enum { 2612 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2613 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2614 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2615 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2616 }; 2617 2618 struct mlx5_ifc_scheduling_context_bits { 2619 u8 element_type[0x8]; 2620 u8 reserved_at_8[0x18]; 2621 2622 u8 element_attributes[0x20]; 2623 2624 u8 parent_element_id[0x20]; 2625 2626 u8 reserved_at_60[0x40]; 2627 2628 u8 bw_share[0x20]; 2629 2630 u8 max_average_bw[0x20]; 2631 2632 u8 reserved_at_e0[0x120]; 2633 }; 2634 2635 struct mlx5_ifc_rqtc_bits { 2636 u8 reserved_at_0[0xa0]; 2637 2638 u8 reserved_at_a0[0x10]; 2639 u8 rqt_max_size[0x10]; 2640 2641 u8 reserved_at_c0[0x10]; 2642 u8 rqt_actual_size[0x10]; 2643 2644 u8 reserved_at_e0[0x6a0]; 2645 2646 struct mlx5_ifc_rq_num_bits rq_num[0]; 2647 }; 2648 2649 enum { 2650 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2651 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2652 }; 2653 2654 enum { 2655 MLX5_RQC_STATE_RST = 0x0, 2656 MLX5_RQC_STATE_RDY = 0x1, 2657 MLX5_RQC_STATE_ERR = 0x3, 2658 }; 2659 2660 struct mlx5_ifc_rqc_bits { 2661 u8 rlky[0x1]; 2662 u8 delay_drop_en[0x1]; 2663 u8 scatter_fcs[0x1]; 2664 u8 vsd[0x1]; 2665 u8 mem_rq_type[0x4]; 2666 u8 state[0x4]; 2667 u8 reserved_at_c[0x1]; 2668 u8 flush_in_error_en[0x1]; 2669 u8 hairpin[0x1]; 2670 u8 reserved_at_f[0x11]; 2671 2672 u8 reserved_at_20[0x8]; 2673 u8 user_index[0x18]; 2674 2675 u8 reserved_at_40[0x8]; 2676 u8 cqn[0x18]; 2677 2678 u8 counter_set_id[0x8]; 2679 u8 reserved_at_68[0x18]; 2680 2681 u8 reserved_at_80[0x8]; 2682 u8 rmpn[0x18]; 2683 2684 u8 reserved_at_a0[0x8]; 2685 u8 hairpin_peer_sq[0x18]; 2686 2687 u8 reserved_at_c0[0x10]; 2688 u8 hairpin_peer_vhca[0x10]; 2689 2690 u8 reserved_at_e0[0xa0]; 2691 2692 struct mlx5_ifc_wq_bits wq; 2693 }; 2694 2695 enum { 2696 MLX5_RMPC_STATE_RDY = 0x1, 2697 MLX5_RMPC_STATE_ERR = 0x3, 2698 }; 2699 2700 struct mlx5_ifc_rmpc_bits { 2701 u8 reserved_at_0[0x8]; 2702 u8 state[0x4]; 2703 u8 reserved_at_c[0x14]; 2704 2705 u8 basic_cyclic_rcv_wqe[0x1]; 2706 u8 reserved_at_21[0x1f]; 2707 2708 u8 reserved_at_40[0x140]; 2709 2710 struct mlx5_ifc_wq_bits wq; 2711 }; 2712 2713 struct mlx5_ifc_nic_vport_context_bits { 2714 u8 reserved_at_0[0x5]; 2715 u8 min_wqe_inline_mode[0x3]; 2716 u8 reserved_at_8[0x15]; 2717 u8 disable_mc_local_lb[0x1]; 2718 u8 disable_uc_local_lb[0x1]; 2719 u8 roce_en[0x1]; 2720 2721 u8 arm_change_event[0x1]; 2722 u8 reserved_at_21[0x1a]; 2723 u8 event_on_mtu[0x1]; 2724 u8 event_on_promisc_change[0x1]; 2725 u8 event_on_vlan_change[0x1]; 2726 u8 event_on_mc_address_change[0x1]; 2727 u8 event_on_uc_address_change[0x1]; 2728 2729 u8 reserved_at_40[0xc]; 2730 2731 u8 affiliation_criteria[0x4]; 2732 u8 affiliated_vhca_id[0x10]; 2733 2734 u8 reserved_at_60[0xd0]; 2735 2736 u8 mtu[0x10]; 2737 2738 u8 system_image_guid[0x40]; 2739 u8 port_guid[0x40]; 2740 u8 node_guid[0x40]; 2741 2742 u8 reserved_at_200[0x140]; 2743 u8 qkey_violation_counter[0x10]; 2744 u8 reserved_at_350[0x430]; 2745 2746 u8 promisc_uc[0x1]; 2747 u8 promisc_mc[0x1]; 2748 u8 promisc_all[0x1]; 2749 u8 reserved_at_783[0x2]; 2750 u8 allowed_list_type[0x3]; 2751 u8 reserved_at_788[0xc]; 2752 u8 allowed_list_size[0xc]; 2753 2754 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2755 2756 u8 reserved_at_7e0[0x20]; 2757 2758 u8 current_uc_mac_address[0][0x40]; 2759 }; 2760 2761 enum { 2762 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2763 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2764 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2765 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2766 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2767 }; 2768 2769 struct mlx5_ifc_mkc_bits { 2770 u8 reserved_at_0[0x1]; 2771 u8 free[0x1]; 2772 u8 reserved_at_2[0x1]; 2773 u8 access_mode_4_2[0x3]; 2774 u8 reserved_at_6[0x7]; 2775 u8 relaxed_ordering_write[0x1]; 2776 u8 reserved_at_e[0x1]; 2777 u8 small_fence_on_rdma_read_response[0x1]; 2778 u8 umr_en[0x1]; 2779 u8 a[0x1]; 2780 u8 rw[0x1]; 2781 u8 rr[0x1]; 2782 u8 lw[0x1]; 2783 u8 lr[0x1]; 2784 u8 access_mode_1_0[0x2]; 2785 u8 reserved_at_18[0x8]; 2786 2787 u8 qpn[0x18]; 2788 u8 mkey_7_0[0x8]; 2789 2790 u8 reserved_at_40[0x20]; 2791 2792 u8 length64[0x1]; 2793 u8 bsf_en[0x1]; 2794 u8 sync_umr[0x1]; 2795 u8 reserved_at_63[0x2]; 2796 u8 expected_sigerr_count[0x1]; 2797 u8 reserved_at_66[0x1]; 2798 u8 en_rinval[0x1]; 2799 u8 pd[0x18]; 2800 2801 u8 start_addr[0x40]; 2802 2803 u8 len[0x40]; 2804 2805 u8 bsf_octword_size[0x20]; 2806 2807 u8 reserved_at_120[0x80]; 2808 2809 u8 translations_octword_size[0x20]; 2810 2811 u8 reserved_at_1c0[0x1b]; 2812 u8 log_page_size[0x5]; 2813 2814 u8 reserved_at_1e0[0x20]; 2815 }; 2816 2817 struct mlx5_ifc_pkey_bits { 2818 u8 reserved_at_0[0x10]; 2819 u8 pkey[0x10]; 2820 }; 2821 2822 struct mlx5_ifc_array128_auto_bits { 2823 u8 array128_auto[16][0x8]; 2824 }; 2825 2826 struct mlx5_ifc_hca_vport_context_bits { 2827 u8 field_select[0x20]; 2828 2829 u8 reserved_at_20[0xe0]; 2830 2831 u8 sm_virt_aware[0x1]; 2832 u8 has_smi[0x1]; 2833 u8 has_raw[0x1]; 2834 u8 grh_required[0x1]; 2835 u8 reserved_at_104[0xc]; 2836 u8 port_physical_state[0x4]; 2837 u8 vport_state_policy[0x4]; 2838 u8 port_state[0x4]; 2839 u8 vport_state[0x4]; 2840 2841 u8 reserved_at_120[0x20]; 2842 2843 u8 system_image_guid[0x40]; 2844 2845 u8 port_guid[0x40]; 2846 2847 u8 node_guid[0x40]; 2848 2849 u8 cap_mask1[0x20]; 2850 2851 u8 cap_mask1_field_select[0x20]; 2852 2853 u8 cap_mask2[0x20]; 2854 2855 u8 cap_mask2_field_select[0x20]; 2856 2857 u8 reserved_at_280[0x80]; 2858 2859 u8 lid[0x10]; 2860 u8 reserved_at_310[0x4]; 2861 u8 init_type_reply[0x4]; 2862 u8 lmc[0x3]; 2863 u8 subnet_timeout[0x5]; 2864 2865 u8 sm_lid[0x10]; 2866 u8 sm_sl[0x4]; 2867 u8 reserved_at_334[0xc]; 2868 2869 u8 qkey_violation_counter[0x10]; 2870 u8 pkey_violation_counter[0x10]; 2871 2872 u8 reserved_at_360[0xca0]; 2873 }; 2874 2875 struct mlx5_ifc_esw_vport_context_bits { 2876 u8 reserved_at_0[0x3]; 2877 u8 vport_svlan_strip[0x1]; 2878 u8 vport_cvlan_strip[0x1]; 2879 u8 vport_svlan_insert[0x1]; 2880 u8 vport_cvlan_insert[0x2]; 2881 u8 reserved_at_8[0x18]; 2882 2883 u8 reserved_at_20[0x20]; 2884 2885 u8 svlan_cfi[0x1]; 2886 u8 svlan_pcp[0x3]; 2887 u8 svlan_id[0xc]; 2888 u8 cvlan_cfi[0x1]; 2889 u8 cvlan_pcp[0x3]; 2890 u8 cvlan_id[0xc]; 2891 2892 u8 reserved_at_60[0x7a0]; 2893 }; 2894 2895 enum { 2896 MLX5_EQC_STATUS_OK = 0x0, 2897 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2898 }; 2899 2900 enum { 2901 MLX5_EQC_ST_ARMED = 0x9, 2902 MLX5_EQC_ST_FIRED = 0xa, 2903 }; 2904 2905 struct mlx5_ifc_eqc_bits { 2906 u8 status[0x4]; 2907 u8 reserved_at_4[0x9]; 2908 u8 ec[0x1]; 2909 u8 oi[0x1]; 2910 u8 reserved_at_f[0x5]; 2911 u8 st[0x4]; 2912 u8 reserved_at_18[0x8]; 2913 2914 u8 reserved_at_20[0x20]; 2915 2916 u8 reserved_at_40[0x14]; 2917 u8 page_offset[0x6]; 2918 u8 reserved_at_5a[0x6]; 2919 2920 u8 reserved_at_60[0x3]; 2921 u8 log_eq_size[0x5]; 2922 u8 uar_page[0x18]; 2923 2924 u8 reserved_at_80[0x20]; 2925 2926 u8 reserved_at_a0[0x18]; 2927 u8 intr[0x8]; 2928 2929 u8 reserved_at_c0[0x3]; 2930 u8 log_page_size[0x5]; 2931 u8 reserved_at_c8[0x18]; 2932 2933 u8 reserved_at_e0[0x60]; 2934 2935 u8 reserved_at_140[0x8]; 2936 u8 consumer_counter[0x18]; 2937 2938 u8 reserved_at_160[0x8]; 2939 u8 producer_counter[0x18]; 2940 2941 u8 reserved_at_180[0x80]; 2942 }; 2943 2944 enum { 2945 MLX5_DCTC_STATE_ACTIVE = 0x0, 2946 MLX5_DCTC_STATE_DRAINING = 0x1, 2947 MLX5_DCTC_STATE_DRAINED = 0x2, 2948 }; 2949 2950 enum { 2951 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2952 MLX5_DCTC_CS_RES_NA = 0x1, 2953 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2954 }; 2955 2956 enum { 2957 MLX5_DCTC_MTU_256_BYTES = 0x1, 2958 MLX5_DCTC_MTU_512_BYTES = 0x2, 2959 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2960 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2961 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2962 }; 2963 2964 struct mlx5_ifc_dctc_bits { 2965 u8 reserved_at_0[0x4]; 2966 u8 state[0x4]; 2967 u8 reserved_at_8[0x18]; 2968 2969 u8 reserved_at_20[0x8]; 2970 u8 user_index[0x18]; 2971 2972 u8 reserved_at_40[0x8]; 2973 u8 cqn[0x18]; 2974 2975 u8 counter_set_id[0x8]; 2976 u8 atomic_mode[0x4]; 2977 u8 rre[0x1]; 2978 u8 rwe[0x1]; 2979 u8 rae[0x1]; 2980 u8 atomic_like_write_en[0x1]; 2981 u8 latency_sensitive[0x1]; 2982 u8 rlky[0x1]; 2983 u8 free_ar[0x1]; 2984 u8 reserved_at_73[0xd]; 2985 2986 u8 reserved_at_80[0x8]; 2987 u8 cs_res[0x8]; 2988 u8 reserved_at_90[0x3]; 2989 u8 min_rnr_nak[0x5]; 2990 u8 reserved_at_98[0x8]; 2991 2992 u8 reserved_at_a0[0x8]; 2993 u8 srqn_xrqn[0x18]; 2994 2995 u8 reserved_at_c0[0x8]; 2996 u8 pd[0x18]; 2997 2998 u8 tclass[0x8]; 2999 u8 reserved_at_e8[0x4]; 3000 u8 flow_label[0x14]; 3001 3002 u8 dc_access_key[0x40]; 3003 3004 u8 reserved_at_140[0x5]; 3005 u8 mtu[0x3]; 3006 u8 port[0x8]; 3007 u8 pkey_index[0x10]; 3008 3009 u8 reserved_at_160[0x8]; 3010 u8 my_addr_index[0x8]; 3011 u8 reserved_at_170[0x8]; 3012 u8 hop_limit[0x8]; 3013 3014 u8 dc_access_key_violation_count[0x20]; 3015 3016 u8 reserved_at_1a0[0x14]; 3017 u8 dei_cfi[0x1]; 3018 u8 eth_prio[0x3]; 3019 u8 ecn[0x2]; 3020 u8 dscp[0x6]; 3021 3022 u8 reserved_at_1c0[0x40]; 3023 }; 3024 3025 enum { 3026 MLX5_CQC_STATUS_OK = 0x0, 3027 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3028 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3029 }; 3030 3031 enum { 3032 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3033 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3034 }; 3035 3036 enum { 3037 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3038 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3039 MLX5_CQC_ST_FIRED = 0xa, 3040 }; 3041 3042 enum { 3043 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3044 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3045 MLX5_CQ_PERIOD_NUM_MODES 3046 }; 3047 3048 struct mlx5_ifc_cqc_bits { 3049 u8 status[0x4]; 3050 u8 reserved_at_4[0x4]; 3051 u8 cqe_sz[0x3]; 3052 u8 cc[0x1]; 3053 u8 reserved_at_c[0x1]; 3054 u8 scqe_break_moderation_en[0x1]; 3055 u8 oi[0x1]; 3056 u8 cq_period_mode[0x2]; 3057 u8 cqe_comp_en[0x1]; 3058 u8 mini_cqe_res_format[0x2]; 3059 u8 st[0x4]; 3060 u8 reserved_at_18[0x8]; 3061 3062 u8 reserved_at_20[0x20]; 3063 3064 u8 reserved_at_40[0x14]; 3065 u8 page_offset[0x6]; 3066 u8 reserved_at_5a[0x6]; 3067 3068 u8 reserved_at_60[0x3]; 3069 u8 log_cq_size[0x5]; 3070 u8 uar_page[0x18]; 3071 3072 u8 reserved_at_80[0x4]; 3073 u8 cq_period[0xc]; 3074 u8 cq_max_count[0x10]; 3075 3076 u8 reserved_at_a0[0x18]; 3077 u8 c_eqn[0x8]; 3078 3079 u8 reserved_at_c0[0x3]; 3080 u8 log_page_size[0x5]; 3081 u8 reserved_at_c8[0x18]; 3082 3083 u8 reserved_at_e0[0x20]; 3084 3085 u8 reserved_at_100[0x8]; 3086 u8 last_notified_index[0x18]; 3087 3088 u8 reserved_at_120[0x8]; 3089 u8 last_solicit_index[0x18]; 3090 3091 u8 reserved_at_140[0x8]; 3092 u8 consumer_counter[0x18]; 3093 3094 u8 reserved_at_160[0x8]; 3095 u8 producer_counter[0x18]; 3096 3097 u8 reserved_at_180[0x40]; 3098 3099 u8 dbr_addr[0x40]; 3100 }; 3101 3102 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3103 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3104 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3105 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3106 u8 reserved_at_0[0x800]; 3107 }; 3108 3109 struct mlx5_ifc_query_adapter_param_block_bits { 3110 u8 reserved_at_0[0xc0]; 3111 3112 u8 reserved_at_c0[0x8]; 3113 u8 ieee_vendor_id[0x18]; 3114 3115 u8 reserved_at_e0[0x10]; 3116 u8 vsd_vendor_id[0x10]; 3117 3118 u8 vsd[208][0x8]; 3119 3120 u8 vsd_contd_psid[16][0x8]; 3121 }; 3122 3123 enum { 3124 MLX5_XRQC_STATE_GOOD = 0x0, 3125 MLX5_XRQC_STATE_ERROR = 0x1, 3126 }; 3127 3128 enum { 3129 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3130 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3131 }; 3132 3133 enum { 3134 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3135 }; 3136 3137 struct mlx5_ifc_tag_matching_topology_context_bits { 3138 u8 log_matching_list_sz[0x4]; 3139 u8 reserved_at_4[0xc]; 3140 u8 append_next_index[0x10]; 3141 3142 u8 sw_phase_cnt[0x10]; 3143 u8 hw_phase_cnt[0x10]; 3144 3145 u8 reserved_at_40[0x40]; 3146 }; 3147 3148 struct mlx5_ifc_xrqc_bits { 3149 u8 state[0x4]; 3150 u8 rlkey[0x1]; 3151 u8 reserved_at_5[0xf]; 3152 u8 topology[0x4]; 3153 u8 reserved_at_18[0x4]; 3154 u8 offload[0x4]; 3155 3156 u8 reserved_at_20[0x8]; 3157 u8 user_index[0x18]; 3158 3159 u8 reserved_at_40[0x8]; 3160 u8 cqn[0x18]; 3161 3162 u8 reserved_at_60[0xa0]; 3163 3164 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3165 3166 u8 reserved_at_180[0x280]; 3167 3168 struct mlx5_ifc_wq_bits wq; 3169 }; 3170 3171 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3172 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3173 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3174 u8 reserved_at_0[0x20]; 3175 }; 3176 3177 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3178 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3179 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3180 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3181 u8 reserved_at_0[0x20]; 3182 }; 3183 3184 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3185 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3186 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3187 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3188 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3189 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3190 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3191 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3192 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3193 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3194 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3195 u8 reserved_at_0[0x7c0]; 3196 }; 3197 3198 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3199 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3200 u8 reserved_at_0[0x7c0]; 3201 }; 3202 3203 union mlx5_ifc_event_auto_bits { 3204 struct mlx5_ifc_comp_event_bits comp_event; 3205 struct mlx5_ifc_dct_events_bits dct_events; 3206 struct mlx5_ifc_qp_events_bits qp_events; 3207 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3208 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3209 struct mlx5_ifc_cq_error_bits cq_error; 3210 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3211 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3212 struct mlx5_ifc_gpio_event_bits gpio_event; 3213 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3214 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3215 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3216 u8 reserved_at_0[0xe0]; 3217 }; 3218 3219 struct mlx5_ifc_health_buffer_bits { 3220 u8 reserved_at_0[0x100]; 3221 3222 u8 assert_existptr[0x20]; 3223 3224 u8 assert_callra[0x20]; 3225 3226 u8 reserved_at_140[0x40]; 3227 3228 u8 fw_version[0x20]; 3229 3230 u8 hw_id[0x20]; 3231 3232 u8 reserved_at_1c0[0x20]; 3233 3234 u8 irisc_index[0x8]; 3235 u8 synd[0x8]; 3236 u8 ext_synd[0x10]; 3237 }; 3238 3239 struct mlx5_ifc_register_loopback_control_bits { 3240 u8 no_lb[0x1]; 3241 u8 reserved_at_1[0x7]; 3242 u8 port[0x8]; 3243 u8 reserved_at_10[0x10]; 3244 3245 u8 reserved_at_20[0x60]; 3246 }; 3247 3248 struct mlx5_ifc_vport_tc_element_bits { 3249 u8 traffic_class[0x4]; 3250 u8 reserved_at_4[0xc]; 3251 u8 vport_number[0x10]; 3252 }; 3253 3254 struct mlx5_ifc_vport_element_bits { 3255 u8 reserved_at_0[0x10]; 3256 u8 vport_number[0x10]; 3257 }; 3258 3259 enum { 3260 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3261 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3262 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3263 }; 3264 3265 struct mlx5_ifc_tsar_element_bits { 3266 u8 reserved_at_0[0x8]; 3267 u8 tsar_type[0x8]; 3268 u8 reserved_at_10[0x10]; 3269 }; 3270 3271 enum { 3272 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3273 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3274 }; 3275 3276 struct mlx5_ifc_teardown_hca_out_bits { 3277 u8 status[0x8]; 3278 u8 reserved_at_8[0x18]; 3279 3280 u8 syndrome[0x20]; 3281 3282 u8 reserved_at_40[0x3f]; 3283 3284 u8 force_state[0x1]; 3285 }; 3286 3287 enum { 3288 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3289 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3290 }; 3291 3292 struct mlx5_ifc_teardown_hca_in_bits { 3293 u8 opcode[0x10]; 3294 u8 reserved_at_10[0x10]; 3295 3296 u8 reserved_at_20[0x10]; 3297 u8 op_mod[0x10]; 3298 3299 u8 reserved_at_40[0x10]; 3300 u8 profile[0x10]; 3301 3302 u8 reserved_at_60[0x20]; 3303 }; 3304 3305 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3306 u8 status[0x8]; 3307 u8 reserved_at_8[0x18]; 3308 3309 u8 syndrome[0x20]; 3310 3311 u8 reserved_at_40[0x40]; 3312 }; 3313 3314 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3315 u8 opcode[0x10]; 3316 u8 reserved_at_10[0x10]; 3317 3318 u8 reserved_at_20[0x10]; 3319 u8 op_mod[0x10]; 3320 3321 u8 reserved_at_40[0x8]; 3322 u8 qpn[0x18]; 3323 3324 u8 reserved_at_60[0x20]; 3325 3326 u8 opt_param_mask[0x20]; 3327 3328 u8 reserved_at_a0[0x20]; 3329 3330 struct mlx5_ifc_qpc_bits qpc; 3331 3332 u8 reserved_at_800[0x80]; 3333 }; 3334 3335 struct mlx5_ifc_sqd2rts_qp_out_bits { 3336 u8 status[0x8]; 3337 u8 reserved_at_8[0x18]; 3338 3339 u8 syndrome[0x20]; 3340 3341 u8 reserved_at_40[0x40]; 3342 }; 3343 3344 struct mlx5_ifc_sqd2rts_qp_in_bits { 3345 u8 opcode[0x10]; 3346 u8 reserved_at_10[0x10]; 3347 3348 u8 reserved_at_20[0x10]; 3349 u8 op_mod[0x10]; 3350 3351 u8 reserved_at_40[0x8]; 3352 u8 qpn[0x18]; 3353 3354 u8 reserved_at_60[0x20]; 3355 3356 u8 opt_param_mask[0x20]; 3357 3358 u8 reserved_at_a0[0x20]; 3359 3360 struct mlx5_ifc_qpc_bits qpc; 3361 3362 u8 reserved_at_800[0x80]; 3363 }; 3364 3365 struct mlx5_ifc_set_roce_address_out_bits { 3366 u8 status[0x8]; 3367 u8 reserved_at_8[0x18]; 3368 3369 u8 syndrome[0x20]; 3370 3371 u8 reserved_at_40[0x40]; 3372 }; 3373 3374 struct mlx5_ifc_set_roce_address_in_bits { 3375 u8 opcode[0x10]; 3376 u8 reserved_at_10[0x10]; 3377 3378 u8 reserved_at_20[0x10]; 3379 u8 op_mod[0x10]; 3380 3381 u8 roce_address_index[0x10]; 3382 u8 reserved_at_50[0xc]; 3383 u8 vhca_port_num[0x4]; 3384 3385 u8 reserved_at_60[0x20]; 3386 3387 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3388 }; 3389 3390 struct mlx5_ifc_set_mad_demux_out_bits { 3391 u8 status[0x8]; 3392 u8 reserved_at_8[0x18]; 3393 3394 u8 syndrome[0x20]; 3395 3396 u8 reserved_at_40[0x40]; 3397 }; 3398 3399 enum { 3400 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3401 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3402 }; 3403 3404 struct mlx5_ifc_set_mad_demux_in_bits { 3405 u8 opcode[0x10]; 3406 u8 reserved_at_10[0x10]; 3407 3408 u8 reserved_at_20[0x10]; 3409 u8 op_mod[0x10]; 3410 3411 u8 reserved_at_40[0x20]; 3412 3413 u8 reserved_at_60[0x6]; 3414 u8 demux_mode[0x2]; 3415 u8 reserved_at_68[0x18]; 3416 }; 3417 3418 struct mlx5_ifc_set_l2_table_entry_out_bits { 3419 u8 status[0x8]; 3420 u8 reserved_at_8[0x18]; 3421 3422 u8 syndrome[0x20]; 3423 3424 u8 reserved_at_40[0x40]; 3425 }; 3426 3427 struct mlx5_ifc_set_l2_table_entry_in_bits { 3428 u8 opcode[0x10]; 3429 u8 reserved_at_10[0x10]; 3430 3431 u8 reserved_at_20[0x10]; 3432 u8 op_mod[0x10]; 3433 3434 u8 reserved_at_40[0x60]; 3435 3436 u8 reserved_at_a0[0x8]; 3437 u8 table_index[0x18]; 3438 3439 u8 reserved_at_c0[0x20]; 3440 3441 u8 reserved_at_e0[0x13]; 3442 u8 vlan_valid[0x1]; 3443 u8 vlan[0xc]; 3444 3445 struct mlx5_ifc_mac_address_layout_bits mac_address; 3446 3447 u8 reserved_at_140[0xc0]; 3448 }; 3449 3450 struct mlx5_ifc_set_issi_out_bits { 3451 u8 status[0x8]; 3452 u8 reserved_at_8[0x18]; 3453 3454 u8 syndrome[0x20]; 3455 3456 u8 reserved_at_40[0x40]; 3457 }; 3458 3459 struct mlx5_ifc_set_issi_in_bits { 3460 u8 opcode[0x10]; 3461 u8 reserved_at_10[0x10]; 3462 3463 u8 reserved_at_20[0x10]; 3464 u8 op_mod[0x10]; 3465 3466 u8 reserved_at_40[0x10]; 3467 u8 current_issi[0x10]; 3468 3469 u8 reserved_at_60[0x20]; 3470 }; 3471 3472 struct mlx5_ifc_set_hca_cap_out_bits { 3473 u8 status[0x8]; 3474 u8 reserved_at_8[0x18]; 3475 3476 u8 syndrome[0x20]; 3477 3478 u8 reserved_at_40[0x40]; 3479 }; 3480 3481 struct mlx5_ifc_set_hca_cap_in_bits { 3482 u8 opcode[0x10]; 3483 u8 reserved_at_10[0x10]; 3484 3485 u8 reserved_at_20[0x10]; 3486 u8 op_mod[0x10]; 3487 3488 u8 reserved_at_40[0x40]; 3489 3490 union mlx5_ifc_hca_cap_union_bits capability; 3491 }; 3492 3493 enum { 3494 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3495 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3496 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3497 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3498 }; 3499 3500 struct mlx5_ifc_set_fte_out_bits { 3501 u8 status[0x8]; 3502 u8 reserved_at_8[0x18]; 3503 3504 u8 syndrome[0x20]; 3505 3506 u8 reserved_at_40[0x40]; 3507 }; 3508 3509 struct mlx5_ifc_set_fte_in_bits { 3510 u8 opcode[0x10]; 3511 u8 reserved_at_10[0x10]; 3512 3513 u8 reserved_at_20[0x10]; 3514 u8 op_mod[0x10]; 3515 3516 u8 other_vport[0x1]; 3517 u8 reserved_at_41[0xf]; 3518 u8 vport_number[0x10]; 3519 3520 u8 reserved_at_60[0x20]; 3521 3522 u8 table_type[0x8]; 3523 u8 reserved_at_88[0x18]; 3524 3525 u8 reserved_at_a0[0x8]; 3526 u8 table_id[0x18]; 3527 3528 u8 reserved_at_c0[0x18]; 3529 u8 modify_enable_mask[0x8]; 3530 3531 u8 reserved_at_e0[0x20]; 3532 3533 u8 flow_index[0x20]; 3534 3535 u8 reserved_at_120[0xe0]; 3536 3537 struct mlx5_ifc_flow_context_bits flow_context; 3538 }; 3539 3540 struct mlx5_ifc_rts2rts_qp_out_bits { 3541 u8 status[0x8]; 3542 u8 reserved_at_8[0x18]; 3543 3544 u8 syndrome[0x20]; 3545 3546 u8 reserved_at_40[0x40]; 3547 }; 3548 3549 struct mlx5_ifc_rts2rts_qp_in_bits { 3550 u8 opcode[0x10]; 3551 u8 reserved_at_10[0x10]; 3552 3553 u8 reserved_at_20[0x10]; 3554 u8 op_mod[0x10]; 3555 3556 u8 reserved_at_40[0x8]; 3557 u8 qpn[0x18]; 3558 3559 u8 reserved_at_60[0x20]; 3560 3561 u8 opt_param_mask[0x20]; 3562 3563 u8 reserved_at_a0[0x20]; 3564 3565 struct mlx5_ifc_qpc_bits qpc; 3566 3567 u8 reserved_at_800[0x80]; 3568 }; 3569 3570 struct mlx5_ifc_rtr2rts_qp_out_bits { 3571 u8 status[0x8]; 3572 u8 reserved_at_8[0x18]; 3573 3574 u8 syndrome[0x20]; 3575 3576 u8 reserved_at_40[0x40]; 3577 }; 3578 3579 struct mlx5_ifc_rtr2rts_qp_in_bits { 3580 u8 opcode[0x10]; 3581 u8 reserved_at_10[0x10]; 3582 3583 u8 reserved_at_20[0x10]; 3584 u8 op_mod[0x10]; 3585 3586 u8 reserved_at_40[0x8]; 3587 u8 qpn[0x18]; 3588 3589 u8 reserved_at_60[0x20]; 3590 3591 u8 opt_param_mask[0x20]; 3592 3593 u8 reserved_at_a0[0x20]; 3594 3595 struct mlx5_ifc_qpc_bits qpc; 3596 3597 u8 reserved_at_800[0x80]; 3598 }; 3599 3600 struct mlx5_ifc_rst2init_qp_out_bits { 3601 u8 status[0x8]; 3602 u8 reserved_at_8[0x18]; 3603 3604 u8 syndrome[0x20]; 3605 3606 u8 reserved_at_40[0x40]; 3607 }; 3608 3609 struct mlx5_ifc_rst2init_qp_in_bits { 3610 u8 opcode[0x10]; 3611 u8 reserved_at_10[0x10]; 3612 3613 u8 reserved_at_20[0x10]; 3614 u8 op_mod[0x10]; 3615 3616 u8 reserved_at_40[0x8]; 3617 u8 qpn[0x18]; 3618 3619 u8 reserved_at_60[0x20]; 3620 3621 u8 opt_param_mask[0x20]; 3622 3623 u8 reserved_at_a0[0x20]; 3624 3625 struct mlx5_ifc_qpc_bits qpc; 3626 3627 u8 reserved_at_800[0x80]; 3628 }; 3629 3630 struct mlx5_ifc_query_xrq_out_bits { 3631 u8 status[0x8]; 3632 u8 reserved_at_8[0x18]; 3633 3634 u8 syndrome[0x20]; 3635 3636 u8 reserved_at_40[0x40]; 3637 3638 struct mlx5_ifc_xrqc_bits xrq_context; 3639 }; 3640 3641 struct mlx5_ifc_query_xrq_in_bits { 3642 u8 opcode[0x10]; 3643 u8 reserved_at_10[0x10]; 3644 3645 u8 reserved_at_20[0x10]; 3646 u8 op_mod[0x10]; 3647 3648 u8 reserved_at_40[0x8]; 3649 u8 xrqn[0x18]; 3650 3651 u8 reserved_at_60[0x20]; 3652 }; 3653 3654 struct mlx5_ifc_query_xrc_srq_out_bits { 3655 u8 status[0x8]; 3656 u8 reserved_at_8[0x18]; 3657 3658 u8 syndrome[0x20]; 3659 3660 u8 reserved_at_40[0x40]; 3661 3662 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3663 3664 u8 reserved_at_280[0x600]; 3665 3666 u8 pas[0][0x40]; 3667 }; 3668 3669 struct mlx5_ifc_query_xrc_srq_in_bits { 3670 u8 opcode[0x10]; 3671 u8 reserved_at_10[0x10]; 3672 3673 u8 reserved_at_20[0x10]; 3674 u8 op_mod[0x10]; 3675 3676 u8 reserved_at_40[0x8]; 3677 u8 xrc_srqn[0x18]; 3678 3679 u8 reserved_at_60[0x20]; 3680 }; 3681 3682 enum { 3683 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3684 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3685 }; 3686 3687 struct mlx5_ifc_query_vport_state_out_bits { 3688 u8 status[0x8]; 3689 u8 reserved_at_8[0x18]; 3690 3691 u8 syndrome[0x20]; 3692 3693 u8 reserved_at_40[0x20]; 3694 3695 u8 reserved_at_60[0x18]; 3696 u8 admin_state[0x4]; 3697 u8 state[0x4]; 3698 }; 3699 3700 enum { 3701 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3702 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3703 }; 3704 3705 struct mlx5_ifc_query_vport_state_in_bits { 3706 u8 opcode[0x10]; 3707 u8 reserved_at_10[0x10]; 3708 3709 u8 reserved_at_20[0x10]; 3710 u8 op_mod[0x10]; 3711 3712 u8 other_vport[0x1]; 3713 u8 reserved_at_41[0xf]; 3714 u8 vport_number[0x10]; 3715 3716 u8 reserved_at_60[0x20]; 3717 }; 3718 3719 struct mlx5_ifc_query_vnic_env_out_bits { 3720 u8 status[0x8]; 3721 u8 reserved_at_8[0x18]; 3722 3723 u8 syndrome[0x20]; 3724 3725 u8 reserved_at_40[0x40]; 3726 3727 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3728 }; 3729 3730 enum { 3731 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3732 }; 3733 3734 struct mlx5_ifc_query_vnic_env_in_bits { 3735 u8 opcode[0x10]; 3736 u8 reserved_at_10[0x10]; 3737 3738 u8 reserved_at_20[0x10]; 3739 u8 op_mod[0x10]; 3740 3741 u8 other_vport[0x1]; 3742 u8 reserved_at_41[0xf]; 3743 u8 vport_number[0x10]; 3744 3745 u8 reserved_at_60[0x20]; 3746 }; 3747 3748 struct mlx5_ifc_query_vport_counter_out_bits { 3749 u8 status[0x8]; 3750 u8 reserved_at_8[0x18]; 3751 3752 u8 syndrome[0x20]; 3753 3754 u8 reserved_at_40[0x40]; 3755 3756 struct mlx5_ifc_traffic_counter_bits received_errors; 3757 3758 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3759 3760 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3761 3762 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3763 3764 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3765 3766 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3767 3768 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3769 3770 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3771 3772 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3773 3774 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3775 3776 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3777 3778 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3779 3780 u8 reserved_at_680[0xa00]; 3781 }; 3782 3783 enum { 3784 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3785 }; 3786 3787 struct mlx5_ifc_query_vport_counter_in_bits { 3788 u8 opcode[0x10]; 3789 u8 reserved_at_10[0x10]; 3790 3791 u8 reserved_at_20[0x10]; 3792 u8 op_mod[0x10]; 3793 3794 u8 other_vport[0x1]; 3795 u8 reserved_at_41[0xb]; 3796 u8 port_num[0x4]; 3797 u8 vport_number[0x10]; 3798 3799 u8 reserved_at_60[0x60]; 3800 3801 u8 clear[0x1]; 3802 u8 reserved_at_c1[0x1f]; 3803 3804 u8 reserved_at_e0[0x20]; 3805 }; 3806 3807 struct mlx5_ifc_query_tis_out_bits { 3808 u8 status[0x8]; 3809 u8 reserved_at_8[0x18]; 3810 3811 u8 syndrome[0x20]; 3812 3813 u8 reserved_at_40[0x40]; 3814 3815 struct mlx5_ifc_tisc_bits tis_context; 3816 }; 3817 3818 struct mlx5_ifc_query_tis_in_bits { 3819 u8 opcode[0x10]; 3820 u8 reserved_at_10[0x10]; 3821 3822 u8 reserved_at_20[0x10]; 3823 u8 op_mod[0x10]; 3824 3825 u8 reserved_at_40[0x8]; 3826 u8 tisn[0x18]; 3827 3828 u8 reserved_at_60[0x20]; 3829 }; 3830 3831 struct mlx5_ifc_query_tir_out_bits { 3832 u8 status[0x8]; 3833 u8 reserved_at_8[0x18]; 3834 3835 u8 syndrome[0x20]; 3836 3837 u8 reserved_at_40[0xc0]; 3838 3839 struct mlx5_ifc_tirc_bits tir_context; 3840 }; 3841 3842 struct mlx5_ifc_query_tir_in_bits { 3843 u8 opcode[0x10]; 3844 u8 reserved_at_10[0x10]; 3845 3846 u8 reserved_at_20[0x10]; 3847 u8 op_mod[0x10]; 3848 3849 u8 reserved_at_40[0x8]; 3850 u8 tirn[0x18]; 3851 3852 u8 reserved_at_60[0x20]; 3853 }; 3854 3855 struct mlx5_ifc_query_srq_out_bits { 3856 u8 status[0x8]; 3857 u8 reserved_at_8[0x18]; 3858 3859 u8 syndrome[0x20]; 3860 3861 u8 reserved_at_40[0x40]; 3862 3863 struct mlx5_ifc_srqc_bits srq_context_entry; 3864 3865 u8 reserved_at_280[0x600]; 3866 3867 u8 pas[0][0x40]; 3868 }; 3869 3870 struct mlx5_ifc_query_srq_in_bits { 3871 u8 opcode[0x10]; 3872 u8 reserved_at_10[0x10]; 3873 3874 u8 reserved_at_20[0x10]; 3875 u8 op_mod[0x10]; 3876 3877 u8 reserved_at_40[0x8]; 3878 u8 srqn[0x18]; 3879 3880 u8 reserved_at_60[0x20]; 3881 }; 3882 3883 struct mlx5_ifc_query_sq_out_bits { 3884 u8 status[0x8]; 3885 u8 reserved_at_8[0x18]; 3886 3887 u8 syndrome[0x20]; 3888 3889 u8 reserved_at_40[0xc0]; 3890 3891 struct mlx5_ifc_sqc_bits sq_context; 3892 }; 3893 3894 struct mlx5_ifc_query_sq_in_bits { 3895 u8 opcode[0x10]; 3896 u8 reserved_at_10[0x10]; 3897 3898 u8 reserved_at_20[0x10]; 3899 u8 op_mod[0x10]; 3900 3901 u8 reserved_at_40[0x8]; 3902 u8 sqn[0x18]; 3903 3904 u8 reserved_at_60[0x20]; 3905 }; 3906 3907 struct mlx5_ifc_query_special_contexts_out_bits { 3908 u8 status[0x8]; 3909 u8 reserved_at_8[0x18]; 3910 3911 u8 syndrome[0x20]; 3912 3913 u8 dump_fill_mkey[0x20]; 3914 3915 u8 resd_lkey[0x20]; 3916 3917 u8 null_mkey[0x20]; 3918 3919 u8 reserved_at_a0[0x60]; 3920 }; 3921 3922 struct mlx5_ifc_query_special_contexts_in_bits { 3923 u8 opcode[0x10]; 3924 u8 reserved_at_10[0x10]; 3925 3926 u8 reserved_at_20[0x10]; 3927 u8 op_mod[0x10]; 3928 3929 u8 reserved_at_40[0x40]; 3930 }; 3931 3932 struct mlx5_ifc_query_scheduling_element_out_bits { 3933 u8 opcode[0x10]; 3934 u8 reserved_at_10[0x10]; 3935 3936 u8 reserved_at_20[0x10]; 3937 u8 op_mod[0x10]; 3938 3939 u8 reserved_at_40[0xc0]; 3940 3941 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3942 3943 u8 reserved_at_300[0x100]; 3944 }; 3945 3946 enum { 3947 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3948 }; 3949 3950 struct mlx5_ifc_query_scheduling_element_in_bits { 3951 u8 opcode[0x10]; 3952 u8 reserved_at_10[0x10]; 3953 3954 u8 reserved_at_20[0x10]; 3955 u8 op_mod[0x10]; 3956 3957 u8 scheduling_hierarchy[0x8]; 3958 u8 reserved_at_48[0x18]; 3959 3960 u8 scheduling_element_id[0x20]; 3961 3962 u8 reserved_at_80[0x180]; 3963 }; 3964 3965 struct mlx5_ifc_query_rqt_out_bits { 3966 u8 status[0x8]; 3967 u8 reserved_at_8[0x18]; 3968 3969 u8 syndrome[0x20]; 3970 3971 u8 reserved_at_40[0xc0]; 3972 3973 struct mlx5_ifc_rqtc_bits rqt_context; 3974 }; 3975 3976 struct mlx5_ifc_query_rqt_in_bits { 3977 u8 opcode[0x10]; 3978 u8 reserved_at_10[0x10]; 3979 3980 u8 reserved_at_20[0x10]; 3981 u8 op_mod[0x10]; 3982 3983 u8 reserved_at_40[0x8]; 3984 u8 rqtn[0x18]; 3985 3986 u8 reserved_at_60[0x20]; 3987 }; 3988 3989 struct mlx5_ifc_query_rq_out_bits { 3990 u8 status[0x8]; 3991 u8 reserved_at_8[0x18]; 3992 3993 u8 syndrome[0x20]; 3994 3995 u8 reserved_at_40[0xc0]; 3996 3997 struct mlx5_ifc_rqc_bits rq_context; 3998 }; 3999 4000 struct mlx5_ifc_query_rq_in_bits { 4001 u8 opcode[0x10]; 4002 u8 reserved_at_10[0x10]; 4003 4004 u8 reserved_at_20[0x10]; 4005 u8 op_mod[0x10]; 4006 4007 u8 reserved_at_40[0x8]; 4008 u8 rqn[0x18]; 4009 4010 u8 reserved_at_60[0x20]; 4011 }; 4012 4013 struct mlx5_ifc_query_roce_address_out_bits { 4014 u8 status[0x8]; 4015 u8 reserved_at_8[0x18]; 4016 4017 u8 syndrome[0x20]; 4018 4019 u8 reserved_at_40[0x40]; 4020 4021 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4022 }; 4023 4024 struct mlx5_ifc_query_roce_address_in_bits { 4025 u8 opcode[0x10]; 4026 u8 reserved_at_10[0x10]; 4027 4028 u8 reserved_at_20[0x10]; 4029 u8 op_mod[0x10]; 4030 4031 u8 roce_address_index[0x10]; 4032 u8 reserved_at_50[0xc]; 4033 u8 vhca_port_num[0x4]; 4034 4035 u8 reserved_at_60[0x20]; 4036 }; 4037 4038 struct mlx5_ifc_query_rmp_out_bits { 4039 u8 status[0x8]; 4040 u8 reserved_at_8[0x18]; 4041 4042 u8 syndrome[0x20]; 4043 4044 u8 reserved_at_40[0xc0]; 4045 4046 struct mlx5_ifc_rmpc_bits rmp_context; 4047 }; 4048 4049 struct mlx5_ifc_query_rmp_in_bits { 4050 u8 opcode[0x10]; 4051 u8 reserved_at_10[0x10]; 4052 4053 u8 reserved_at_20[0x10]; 4054 u8 op_mod[0x10]; 4055 4056 u8 reserved_at_40[0x8]; 4057 u8 rmpn[0x18]; 4058 4059 u8 reserved_at_60[0x20]; 4060 }; 4061 4062 struct mlx5_ifc_query_qp_out_bits { 4063 u8 status[0x8]; 4064 u8 reserved_at_8[0x18]; 4065 4066 u8 syndrome[0x20]; 4067 4068 u8 reserved_at_40[0x40]; 4069 4070 u8 opt_param_mask[0x20]; 4071 4072 u8 reserved_at_a0[0x20]; 4073 4074 struct mlx5_ifc_qpc_bits qpc; 4075 4076 u8 reserved_at_800[0x80]; 4077 4078 u8 pas[0][0x40]; 4079 }; 4080 4081 struct mlx5_ifc_query_qp_in_bits { 4082 u8 opcode[0x10]; 4083 u8 reserved_at_10[0x10]; 4084 4085 u8 reserved_at_20[0x10]; 4086 u8 op_mod[0x10]; 4087 4088 u8 reserved_at_40[0x8]; 4089 u8 qpn[0x18]; 4090 4091 u8 reserved_at_60[0x20]; 4092 }; 4093 4094 struct mlx5_ifc_query_q_counter_out_bits { 4095 u8 status[0x8]; 4096 u8 reserved_at_8[0x18]; 4097 4098 u8 syndrome[0x20]; 4099 4100 u8 reserved_at_40[0x40]; 4101 4102 u8 rx_write_requests[0x20]; 4103 4104 u8 reserved_at_a0[0x20]; 4105 4106 u8 rx_read_requests[0x20]; 4107 4108 u8 reserved_at_e0[0x20]; 4109 4110 u8 rx_atomic_requests[0x20]; 4111 4112 u8 reserved_at_120[0x20]; 4113 4114 u8 rx_dct_connect[0x20]; 4115 4116 u8 reserved_at_160[0x20]; 4117 4118 u8 out_of_buffer[0x20]; 4119 4120 u8 reserved_at_1a0[0x20]; 4121 4122 u8 out_of_sequence[0x20]; 4123 4124 u8 reserved_at_1e0[0x20]; 4125 4126 u8 duplicate_request[0x20]; 4127 4128 u8 reserved_at_220[0x20]; 4129 4130 u8 rnr_nak_retry_err[0x20]; 4131 4132 u8 reserved_at_260[0x20]; 4133 4134 u8 packet_seq_err[0x20]; 4135 4136 u8 reserved_at_2a0[0x20]; 4137 4138 u8 implied_nak_seq_err[0x20]; 4139 4140 u8 reserved_at_2e0[0x20]; 4141 4142 u8 local_ack_timeout_err[0x20]; 4143 4144 u8 reserved_at_320[0xa0]; 4145 4146 u8 resp_local_length_error[0x20]; 4147 4148 u8 req_local_length_error[0x20]; 4149 4150 u8 resp_local_qp_error[0x20]; 4151 4152 u8 local_operation_error[0x20]; 4153 4154 u8 resp_local_protection[0x20]; 4155 4156 u8 req_local_protection[0x20]; 4157 4158 u8 resp_cqe_error[0x20]; 4159 4160 u8 req_cqe_error[0x20]; 4161 4162 u8 req_mw_binding[0x20]; 4163 4164 u8 req_bad_response[0x20]; 4165 4166 u8 req_remote_invalid_request[0x20]; 4167 4168 u8 resp_remote_invalid_request[0x20]; 4169 4170 u8 req_remote_access_errors[0x20]; 4171 4172 u8 resp_remote_access_errors[0x20]; 4173 4174 u8 req_remote_operation_errors[0x20]; 4175 4176 u8 req_transport_retries_exceeded[0x20]; 4177 4178 u8 cq_overflow[0x20]; 4179 4180 u8 resp_cqe_flush_error[0x20]; 4181 4182 u8 req_cqe_flush_error[0x20]; 4183 4184 u8 reserved_at_620[0x1e0]; 4185 }; 4186 4187 struct mlx5_ifc_query_q_counter_in_bits { 4188 u8 opcode[0x10]; 4189 u8 reserved_at_10[0x10]; 4190 4191 u8 reserved_at_20[0x10]; 4192 u8 op_mod[0x10]; 4193 4194 u8 reserved_at_40[0x80]; 4195 4196 u8 clear[0x1]; 4197 u8 reserved_at_c1[0x1f]; 4198 4199 u8 reserved_at_e0[0x18]; 4200 u8 counter_set_id[0x8]; 4201 }; 4202 4203 struct mlx5_ifc_query_pages_out_bits { 4204 u8 status[0x8]; 4205 u8 reserved_at_8[0x18]; 4206 4207 u8 syndrome[0x20]; 4208 4209 u8 reserved_at_40[0x10]; 4210 u8 function_id[0x10]; 4211 4212 u8 num_pages[0x20]; 4213 }; 4214 4215 enum { 4216 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4217 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4218 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4219 }; 4220 4221 struct mlx5_ifc_query_pages_in_bits { 4222 u8 opcode[0x10]; 4223 u8 reserved_at_10[0x10]; 4224 4225 u8 reserved_at_20[0x10]; 4226 u8 op_mod[0x10]; 4227 4228 u8 reserved_at_40[0x10]; 4229 u8 function_id[0x10]; 4230 4231 u8 reserved_at_60[0x20]; 4232 }; 4233 4234 struct mlx5_ifc_query_nic_vport_context_out_bits { 4235 u8 status[0x8]; 4236 u8 reserved_at_8[0x18]; 4237 4238 u8 syndrome[0x20]; 4239 4240 u8 reserved_at_40[0x40]; 4241 4242 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4243 }; 4244 4245 struct mlx5_ifc_query_nic_vport_context_in_bits { 4246 u8 opcode[0x10]; 4247 u8 reserved_at_10[0x10]; 4248 4249 u8 reserved_at_20[0x10]; 4250 u8 op_mod[0x10]; 4251 4252 u8 other_vport[0x1]; 4253 u8 reserved_at_41[0xf]; 4254 u8 vport_number[0x10]; 4255 4256 u8 reserved_at_60[0x5]; 4257 u8 allowed_list_type[0x3]; 4258 u8 reserved_at_68[0x18]; 4259 }; 4260 4261 struct mlx5_ifc_query_mkey_out_bits { 4262 u8 status[0x8]; 4263 u8 reserved_at_8[0x18]; 4264 4265 u8 syndrome[0x20]; 4266 4267 u8 reserved_at_40[0x40]; 4268 4269 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4270 4271 u8 reserved_at_280[0x600]; 4272 4273 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4274 4275 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4276 }; 4277 4278 struct mlx5_ifc_query_mkey_in_bits { 4279 u8 opcode[0x10]; 4280 u8 reserved_at_10[0x10]; 4281 4282 u8 reserved_at_20[0x10]; 4283 u8 op_mod[0x10]; 4284 4285 u8 reserved_at_40[0x8]; 4286 u8 mkey_index[0x18]; 4287 4288 u8 pg_access[0x1]; 4289 u8 reserved_at_61[0x1f]; 4290 }; 4291 4292 struct mlx5_ifc_query_mad_demux_out_bits { 4293 u8 status[0x8]; 4294 u8 reserved_at_8[0x18]; 4295 4296 u8 syndrome[0x20]; 4297 4298 u8 reserved_at_40[0x40]; 4299 4300 u8 mad_dumux_parameters_block[0x20]; 4301 }; 4302 4303 struct mlx5_ifc_query_mad_demux_in_bits { 4304 u8 opcode[0x10]; 4305 u8 reserved_at_10[0x10]; 4306 4307 u8 reserved_at_20[0x10]; 4308 u8 op_mod[0x10]; 4309 4310 u8 reserved_at_40[0x40]; 4311 }; 4312 4313 struct mlx5_ifc_query_l2_table_entry_out_bits { 4314 u8 status[0x8]; 4315 u8 reserved_at_8[0x18]; 4316 4317 u8 syndrome[0x20]; 4318 4319 u8 reserved_at_40[0xa0]; 4320 4321 u8 reserved_at_e0[0x13]; 4322 u8 vlan_valid[0x1]; 4323 u8 vlan[0xc]; 4324 4325 struct mlx5_ifc_mac_address_layout_bits mac_address; 4326 4327 u8 reserved_at_140[0xc0]; 4328 }; 4329 4330 struct mlx5_ifc_query_l2_table_entry_in_bits { 4331 u8 opcode[0x10]; 4332 u8 reserved_at_10[0x10]; 4333 4334 u8 reserved_at_20[0x10]; 4335 u8 op_mod[0x10]; 4336 4337 u8 reserved_at_40[0x60]; 4338 4339 u8 reserved_at_a0[0x8]; 4340 u8 table_index[0x18]; 4341 4342 u8 reserved_at_c0[0x140]; 4343 }; 4344 4345 struct mlx5_ifc_query_issi_out_bits { 4346 u8 status[0x8]; 4347 u8 reserved_at_8[0x18]; 4348 4349 u8 syndrome[0x20]; 4350 4351 u8 reserved_at_40[0x10]; 4352 u8 current_issi[0x10]; 4353 4354 u8 reserved_at_60[0xa0]; 4355 4356 u8 reserved_at_100[76][0x8]; 4357 u8 supported_issi_dw0[0x20]; 4358 }; 4359 4360 struct mlx5_ifc_query_issi_in_bits { 4361 u8 opcode[0x10]; 4362 u8 reserved_at_10[0x10]; 4363 4364 u8 reserved_at_20[0x10]; 4365 u8 op_mod[0x10]; 4366 4367 u8 reserved_at_40[0x40]; 4368 }; 4369 4370 struct mlx5_ifc_set_driver_version_out_bits { 4371 u8 status[0x8]; 4372 u8 reserved_0[0x18]; 4373 4374 u8 syndrome[0x20]; 4375 u8 reserved_1[0x40]; 4376 }; 4377 4378 struct mlx5_ifc_set_driver_version_in_bits { 4379 u8 opcode[0x10]; 4380 u8 reserved_0[0x10]; 4381 4382 u8 reserved_1[0x10]; 4383 u8 op_mod[0x10]; 4384 4385 u8 reserved_2[0x40]; 4386 u8 driver_version[64][0x8]; 4387 }; 4388 4389 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4390 u8 status[0x8]; 4391 u8 reserved_at_8[0x18]; 4392 4393 u8 syndrome[0x20]; 4394 4395 u8 reserved_at_40[0x40]; 4396 4397 struct mlx5_ifc_pkey_bits pkey[0]; 4398 }; 4399 4400 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4401 u8 opcode[0x10]; 4402 u8 reserved_at_10[0x10]; 4403 4404 u8 reserved_at_20[0x10]; 4405 u8 op_mod[0x10]; 4406 4407 u8 other_vport[0x1]; 4408 u8 reserved_at_41[0xb]; 4409 u8 port_num[0x4]; 4410 u8 vport_number[0x10]; 4411 4412 u8 reserved_at_60[0x10]; 4413 u8 pkey_index[0x10]; 4414 }; 4415 4416 enum { 4417 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4418 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4419 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4420 }; 4421 4422 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4423 u8 status[0x8]; 4424 u8 reserved_at_8[0x18]; 4425 4426 u8 syndrome[0x20]; 4427 4428 u8 reserved_at_40[0x20]; 4429 4430 u8 gids_num[0x10]; 4431 u8 reserved_at_70[0x10]; 4432 4433 struct mlx5_ifc_array128_auto_bits gid[0]; 4434 }; 4435 4436 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4437 u8 opcode[0x10]; 4438 u8 reserved_at_10[0x10]; 4439 4440 u8 reserved_at_20[0x10]; 4441 u8 op_mod[0x10]; 4442 4443 u8 other_vport[0x1]; 4444 u8 reserved_at_41[0xb]; 4445 u8 port_num[0x4]; 4446 u8 vport_number[0x10]; 4447 4448 u8 reserved_at_60[0x10]; 4449 u8 gid_index[0x10]; 4450 }; 4451 4452 struct mlx5_ifc_query_hca_vport_context_out_bits { 4453 u8 status[0x8]; 4454 u8 reserved_at_8[0x18]; 4455 4456 u8 syndrome[0x20]; 4457 4458 u8 reserved_at_40[0x40]; 4459 4460 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4461 }; 4462 4463 struct mlx5_ifc_query_hca_vport_context_in_bits { 4464 u8 opcode[0x10]; 4465 u8 reserved_at_10[0x10]; 4466 4467 u8 reserved_at_20[0x10]; 4468 u8 op_mod[0x10]; 4469 4470 u8 other_vport[0x1]; 4471 u8 reserved_at_41[0xb]; 4472 u8 port_num[0x4]; 4473 u8 vport_number[0x10]; 4474 4475 u8 reserved_at_60[0x20]; 4476 }; 4477 4478 struct mlx5_ifc_query_hca_cap_out_bits { 4479 u8 status[0x8]; 4480 u8 reserved_at_8[0x18]; 4481 4482 u8 syndrome[0x20]; 4483 4484 u8 reserved_at_40[0x40]; 4485 4486 union mlx5_ifc_hca_cap_union_bits capability; 4487 }; 4488 4489 struct mlx5_ifc_query_hca_cap_in_bits { 4490 u8 opcode[0x10]; 4491 u8 reserved_at_10[0x10]; 4492 4493 u8 reserved_at_20[0x10]; 4494 u8 op_mod[0x10]; 4495 4496 u8 reserved_at_40[0x40]; 4497 }; 4498 4499 struct mlx5_ifc_query_flow_table_out_bits { 4500 u8 status[0x8]; 4501 u8 reserved_at_8[0x18]; 4502 4503 u8 syndrome[0x20]; 4504 4505 u8 reserved_at_40[0x80]; 4506 4507 u8 reserved_at_c0[0x8]; 4508 u8 level[0x8]; 4509 u8 reserved_at_d0[0x8]; 4510 u8 log_size[0x8]; 4511 4512 u8 reserved_at_e0[0x120]; 4513 }; 4514 4515 struct mlx5_ifc_query_flow_table_in_bits { 4516 u8 opcode[0x10]; 4517 u8 reserved_at_10[0x10]; 4518 4519 u8 reserved_at_20[0x10]; 4520 u8 op_mod[0x10]; 4521 4522 u8 reserved_at_40[0x40]; 4523 4524 u8 table_type[0x8]; 4525 u8 reserved_at_88[0x18]; 4526 4527 u8 reserved_at_a0[0x8]; 4528 u8 table_id[0x18]; 4529 4530 u8 reserved_at_c0[0x140]; 4531 }; 4532 4533 struct mlx5_ifc_query_fte_out_bits { 4534 u8 status[0x8]; 4535 u8 reserved_at_8[0x18]; 4536 4537 u8 syndrome[0x20]; 4538 4539 u8 reserved_at_40[0x1c0]; 4540 4541 struct mlx5_ifc_flow_context_bits flow_context; 4542 }; 4543 4544 struct mlx5_ifc_query_fte_in_bits { 4545 u8 opcode[0x10]; 4546 u8 reserved_at_10[0x10]; 4547 4548 u8 reserved_at_20[0x10]; 4549 u8 op_mod[0x10]; 4550 4551 u8 reserved_at_40[0x40]; 4552 4553 u8 table_type[0x8]; 4554 u8 reserved_at_88[0x18]; 4555 4556 u8 reserved_at_a0[0x8]; 4557 u8 table_id[0x18]; 4558 4559 u8 reserved_at_c0[0x40]; 4560 4561 u8 flow_index[0x20]; 4562 4563 u8 reserved_at_120[0xe0]; 4564 }; 4565 4566 enum { 4567 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4568 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4569 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4570 }; 4571 4572 struct mlx5_ifc_query_flow_group_out_bits { 4573 u8 status[0x8]; 4574 u8 reserved_at_8[0x18]; 4575 4576 u8 syndrome[0x20]; 4577 4578 u8 reserved_at_40[0xa0]; 4579 4580 u8 start_flow_index[0x20]; 4581 4582 u8 reserved_at_100[0x20]; 4583 4584 u8 end_flow_index[0x20]; 4585 4586 u8 reserved_at_140[0xa0]; 4587 4588 u8 reserved_at_1e0[0x18]; 4589 u8 match_criteria_enable[0x8]; 4590 4591 struct mlx5_ifc_fte_match_param_bits match_criteria; 4592 4593 u8 reserved_at_1200[0xe00]; 4594 }; 4595 4596 struct mlx5_ifc_query_flow_group_in_bits { 4597 u8 opcode[0x10]; 4598 u8 reserved_at_10[0x10]; 4599 4600 u8 reserved_at_20[0x10]; 4601 u8 op_mod[0x10]; 4602 4603 u8 reserved_at_40[0x40]; 4604 4605 u8 table_type[0x8]; 4606 u8 reserved_at_88[0x18]; 4607 4608 u8 reserved_at_a0[0x8]; 4609 u8 table_id[0x18]; 4610 4611 u8 group_id[0x20]; 4612 4613 u8 reserved_at_e0[0x120]; 4614 }; 4615 4616 struct mlx5_ifc_query_flow_counter_out_bits { 4617 u8 status[0x8]; 4618 u8 reserved_at_8[0x18]; 4619 4620 u8 syndrome[0x20]; 4621 4622 u8 reserved_at_40[0x40]; 4623 4624 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4625 }; 4626 4627 struct mlx5_ifc_query_flow_counter_in_bits { 4628 u8 opcode[0x10]; 4629 u8 reserved_at_10[0x10]; 4630 4631 u8 reserved_at_20[0x10]; 4632 u8 op_mod[0x10]; 4633 4634 u8 reserved_at_40[0x80]; 4635 4636 u8 clear[0x1]; 4637 u8 reserved_at_c1[0xf]; 4638 u8 num_of_counters[0x10]; 4639 4640 u8 flow_counter_id[0x20]; 4641 }; 4642 4643 struct mlx5_ifc_query_esw_vport_context_out_bits { 4644 u8 status[0x8]; 4645 u8 reserved_at_8[0x18]; 4646 4647 u8 syndrome[0x20]; 4648 4649 u8 reserved_at_40[0x40]; 4650 4651 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4652 }; 4653 4654 struct mlx5_ifc_query_esw_vport_context_in_bits { 4655 u8 opcode[0x10]; 4656 u8 reserved_at_10[0x10]; 4657 4658 u8 reserved_at_20[0x10]; 4659 u8 op_mod[0x10]; 4660 4661 u8 other_vport[0x1]; 4662 u8 reserved_at_41[0xf]; 4663 u8 vport_number[0x10]; 4664 4665 u8 reserved_at_60[0x20]; 4666 }; 4667 4668 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4669 u8 status[0x8]; 4670 u8 reserved_at_8[0x18]; 4671 4672 u8 syndrome[0x20]; 4673 4674 u8 reserved_at_40[0x40]; 4675 }; 4676 4677 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4678 u8 reserved_at_0[0x1c]; 4679 u8 vport_cvlan_insert[0x1]; 4680 u8 vport_svlan_insert[0x1]; 4681 u8 vport_cvlan_strip[0x1]; 4682 u8 vport_svlan_strip[0x1]; 4683 }; 4684 4685 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4686 u8 opcode[0x10]; 4687 u8 reserved_at_10[0x10]; 4688 4689 u8 reserved_at_20[0x10]; 4690 u8 op_mod[0x10]; 4691 4692 u8 other_vport[0x1]; 4693 u8 reserved_at_41[0xf]; 4694 u8 vport_number[0x10]; 4695 4696 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4697 4698 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4699 }; 4700 4701 struct mlx5_ifc_query_eq_out_bits { 4702 u8 status[0x8]; 4703 u8 reserved_at_8[0x18]; 4704 4705 u8 syndrome[0x20]; 4706 4707 u8 reserved_at_40[0x40]; 4708 4709 struct mlx5_ifc_eqc_bits eq_context_entry; 4710 4711 u8 reserved_at_280[0x40]; 4712 4713 u8 event_bitmask[0x40]; 4714 4715 u8 reserved_at_300[0x580]; 4716 4717 u8 pas[0][0x40]; 4718 }; 4719 4720 struct mlx5_ifc_query_eq_in_bits { 4721 u8 opcode[0x10]; 4722 u8 reserved_at_10[0x10]; 4723 4724 u8 reserved_at_20[0x10]; 4725 u8 op_mod[0x10]; 4726 4727 u8 reserved_at_40[0x18]; 4728 u8 eq_number[0x8]; 4729 4730 u8 reserved_at_60[0x20]; 4731 }; 4732 4733 struct mlx5_ifc_encap_header_in_bits { 4734 u8 reserved_at_0[0x5]; 4735 u8 header_type[0x3]; 4736 u8 reserved_at_8[0xe]; 4737 u8 encap_header_size[0xa]; 4738 4739 u8 reserved_at_20[0x10]; 4740 u8 encap_header[2][0x8]; 4741 4742 u8 more_encap_header[0][0x8]; 4743 }; 4744 4745 struct mlx5_ifc_query_encap_header_out_bits { 4746 u8 status[0x8]; 4747 u8 reserved_at_8[0x18]; 4748 4749 u8 syndrome[0x20]; 4750 4751 u8 reserved_at_40[0xa0]; 4752 4753 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4754 }; 4755 4756 struct mlx5_ifc_query_encap_header_in_bits { 4757 u8 opcode[0x10]; 4758 u8 reserved_at_10[0x10]; 4759 4760 u8 reserved_at_20[0x10]; 4761 u8 op_mod[0x10]; 4762 4763 u8 encap_id[0x20]; 4764 4765 u8 reserved_at_60[0xa0]; 4766 }; 4767 4768 struct mlx5_ifc_alloc_encap_header_out_bits { 4769 u8 status[0x8]; 4770 u8 reserved_at_8[0x18]; 4771 4772 u8 syndrome[0x20]; 4773 4774 u8 encap_id[0x20]; 4775 4776 u8 reserved_at_60[0x20]; 4777 }; 4778 4779 struct mlx5_ifc_alloc_encap_header_in_bits { 4780 u8 opcode[0x10]; 4781 u8 reserved_at_10[0x10]; 4782 4783 u8 reserved_at_20[0x10]; 4784 u8 op_mod[0x10]; 4785 4786 u8 reserved_at_40[0xa0]; 4787 4788 struct mlx5_ifc_encap_header_in_bits encap_header; 4789 }; 4790 4791 struct mlx5_ifc_dealloc_encap_header_out_bits { 4792 u8 status[0x8]; 4793 u8 reserved_at_8[0x18]; 4794 4795 u8 syndrome[0x20]; 4796 4797 u8 reserved_at_40[0x40]; 4798 }; 4799 4800 struct mlx5_ifc_dealloc_encap_header_in_bits { 4801 u8 opcode[0x10]; 4802 u8 reserved_at_10[0x10]; 4803 4804 u8 reserved_20[0x10]; 4805 u8 op_mod[0x10]; 4806 4807 u8 encap_id[0x20]; 4808 4809 u8 reserved_60[0x20]; 4810 }; 4811 4812 struct mlx5_ifc_set_action_in_bits { 4813 u8 action_type[0x4]; 4814 u8 field[0xc]; 4815 u8 reserved_at_10[0x3]; 4816 u8 offset[0x5]; 4817 u8 reserved_at_18[0x3]; 4818 u8 length[0x5]; 4819 4820 u8 data[0x20]; 4821 }; 4822 4823 struct mlx5_ifc_add_action_in_bits { 4824 u8 action_type[0x4]; 4825 u8 field[0xc]; 4826 u8 reserved_at_10[0x10]; 4827 4828 u8 data[0x20]; 4829 }; 4830 4831 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4832 struct mlx5_ifc_set_action_in_bits set_action_in; 4833 struct mlx5_ifc_add_action_in_bits add_action_in; 4834 u8 reserved_at_0[0x40]; 4835 }; 4836 4837 enum { 4838 MLX5_ACTION_TYPE_SET = 0x1, 4839 MLX5_ACTION_TYPE_ADD = 0x2, 4840 }; 4841 4842 enum { 4843 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4844 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4845 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4846 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4847 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4848 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4849 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4850 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4851 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4852 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4853 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4854 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4855 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4856 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4857 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4858 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4859 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4860 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4861 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4862 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4863 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4864 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4865 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4866 }; 4867 4868 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4869 u8 status[0x8]; 4870 u8 reserved_at_8[0x18]; 4871 4872 u8 syndrome[0x20]; 4873 4874 u8 modify_header_id[0x20]; 4875 4876 u8 reserved_at_60[0x20]; 4877 }; 4878 4879 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4880 u8 opcode[0x10]; 4881 u8 reserved_at_10[0x10]; 4882 4883 u8 reserved_at_20[0x10]; 4884 u8 op_mod[0x10]; 4885 4886 u8 reserved_at_40[0x20]; 4887 4888 u8 table_type[0x8]; 4889 u8 reserved_at_68[0x10]; 4890 u8 num_of_actions[0x8]; 4891 4892 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4893 }; 4894 4895 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4896 u8 status[0x8]; 4897 u8 reserved_at_8[0x18]; 4898 4899 u8 syndrome[0x20]; 4900 4901 u8 reserved_at_40[0x40]; 4902 }; 4903 4904 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4905 u8 opcode[0x10]; 4906 u8 reserved_at_10[0x10]; 4907 4908 u8 reserved_at_20[0x10]; 4909 u8 op_mod[0x10]; 4910 4911 u8 modify_header_id[0x20]; 4912 4913 u8 reserved_at_60[0x20]; 4914 }; 4915 4916 struct mlx5_ifc_query_dct_out_bits { 4917 u8 status[0x8]; 4918 u8 reserved_at_8[0x18]; 4919 4920 u8 syndrome[0x20]; 4921 4922 u8 reserved_at_40[0x40]; 4923 4924 struct mlx5_ifc_dctc_bits dct_context_entry; 4925 4926 u8 reserved_at_280[0x180]; 4927 }; 4928 4929 struct mlx5_ifc_query_dct_in_bits { 4930 u8 opcode[0x10]; 4931 u8 reserved_at_10[0x10]; 4932 4933 u8 reserved_at_20[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 reserved_at_40[0x8]; 4937 u8 dctn[0x18]; 4938 4939 u8 reserved_at_60[0x20]; 4940 }; 4941 4942 struct mlx5_ifc_query_cq_out_bits { 4943 u8 status[0x8]; 4944 u8 reserved_at_8[0x18]; 4945 4946 u8 syndrome[0x20]; 4947 4948 u8 reserved_at_40[0x40]; 4949 4950 struct mlx5_ifc_cqc_bits cq_context; 4951 4952 u8 reserved_at_280[0x600]; 4953 4954 u8 pas[0][0x40]; 4955 }; 4956 4957 struct mlx5_ifc_query_cq_in_bits { 4958 u8 opcode[0x10]; 4959 u8 reserved_at_10[0x10]; 4960 4961 u8 reserved_at_20[0x10]; 4962 u8 op_mod[0x10]; 4963 4964 u8 reserved_at_40[0x8]; 4965 u8 cqn[0x18]; 4966 4967 u8 reserved_at_60[0x20]; 4968 }; 4969 4970 struct mlx5_ifc_query_cong_status_out_bits { 4971 u8 status[0x8]; 4972 u8 reserved_at_8[0x18]; 4973 4974 u8 syndrome[0x20]; 4975 4976 u8 reserved_at_40[0x20]; 4977 4978 u8 enable[0x1]; 4979 u8 tag_enable[0x1]; 4980 u8 reserved_at_62[0x1e]; 4981 }; 4982 4983 struct mlx5_ifc_query_cong_status_in_bits { 4984 u8 opcode[0x10]; 4985 u8 reserved_at_10[0x10]; 4986 4987 u8 reserved_at_20[0x10]; 4988 u8 op_mod[0x10]; 4989 4990 u8 reserved_at_40[0x18]; 4991 u8 priority[0x4]; 4992 u8 cong_protocol[0x4]; 4993 4994 u8 reserved_at_60[0x20]; 4995 }; 4996 4997 struct mlx5_ifc_query_cong_statistics_out_bits { 4998 u8 status[0x8]; 4999 u8 reserved_at_8[0x18]; 5000 5001 u8 syndrome[0x20]; 5002 5003 u8 reserved_at_40[0x40]; 5004 5005 u8 rp_cur_flows[0x20]; 5006 5007 u8 sum_flows[0x20]; 5008 5009 u8 rp_cnp_ignored_high[0x20]; 5010 5011 u8 rp_cnp_ignored_low[0x20]; 5012 5013 u8 rp_cnp_handled_high[0x20]; 5014 5015 u8 rp_cnp_handled_low[0x20]; 5016 5017 u8 reserved_at_140[0x100]; 5018 5019 u8 time_stamp_high[0x20]; 5020 5021 u8 time_stamp_low[0x20]; 5022 5023 u8 accumulators_period[0x20]; 5024 5025 u8 np_ecn_marked_roce_packets_high[0x20]; 5026 5027 u8 np_ecn_marked_roce_packets_low[0x20]; 5028 5029 u8 np_cnp_sent_high[0x20]; 5030 5031 u8 np_cnp_sent_low[0x20]; 5032 5033 u8 reserved_at_320[0x560]; 5034 }; 5035 5036 struct mlx5_ifc_query_cong_statistics_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_at_10[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 clear[0x1]; 5044 u8 reserved_at_41[0x1f]; 5045 5046 u8 reserved_at_60[0x20]; 5047 }; 5048 5049 struct mlx5_ifc_query_cong_params_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_at_8[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 reserved_at_40[0x40]; 5056 5057 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5058 }; 5059 5060 struct mlx5_ifc_query_cong_params_in_bits { 5061 u8 opcode[0x10]; 5062 u8 reserved_at_10[0x10]; 5063 5064 u8 reserved_at_20[0x10]; 5065 u8 op_mod[0x10]; 5066 5067 u8 reserved_at_40[0x1c]; 5068 u8 cong_protocol[0x4]; 5069 5070 u8 reserved_at_60[0x20]; 5071 }; 5072 5073 struct mlx5_ifc_query_adapter_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_at_8[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 reserved_at_40[0x40]; 5080 5081 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5082 }; 5083 5084 struct mlx5_ifc_query_adapter_in_bits { 5085 u8 opcode[0x10]; 5086 u8 reserved_at_10[0x10]; 5087 5088 u8 reserved_at_20[0x10]; 5089 u8 op_mod[0x10]; 5090 5091 u8 reserved_at_40[0x40]; 5092 }; 5093 5094 struct mlx5_ifc_qp_2rst_out_bits { 5095 u8 status[0x8]; 5096 u8 reserved_at_8[0x18]; 5097 5098 u8 syndrome[0x20]; 5099 5100 u8 reserved_at_40[0x40]; 5101 }; 5102 5103 struct mlx5_ifc_qp_2rst_in_bits { 5104 u8 opcode[0x10]; 5105 u8 reserved_at_10[0x10]; 5106 5107 u8 reserved_at_20[0x10]; 5108 u8 op_mod[0x10]; 5109 5110 u8 reserved_at_40[0x8]; 5111 u8 qpn[0x18]; 5112 5113 u8 reserved_at_60[0x20]; 5114 }; 5115 5116 struct mlx5_ifc_qp_2err_out_bits { 5117 u8 status[0x8]; 5118 u8 reserved_at_8[0x18]; 5119 5120 u8 syndrome[0x20]; 5121 5122 u8 reserved_at_40[0x40]; 5123 }; 5124 5125 struct mlx5_ifc_qp_2err_in_bits { 5126 u8 opcode[0x10]; 5127 u8 reserved_at_10[0x10]; 5128 5129 u8 reserved_at_20[0x10]; 5130 u8 op_mod[0x10]; 5131 5132 u8 reserved_at_40[0x8]; 5133 u8 qpn[0x18]; 5134 5135 u8 reserved_at_60[0x20]; 5136 }; 5137 5138 struct mlx5_ifc_page_fault_resume_out_bits { 5139 u8 status[0x8]; 5140 u8 reserved_at_8[0x18]; 5141 5142 u8 syndrome[0x20]; 5143 5144 u8 reserved_at_40[0x40]; 5145 }; 5146 5147 struct mlx5_ifc_page_fault_resume_in_bits { 5148 u8 opcode[0x10]; 5149 u8 reserved_at_10[0x10]; 5150 5151 u8 reserved_at_20[0x10]; 5152 u8 op_mod[0x10]; 5153 5154 u8 error[0x1]; 5155 u8 reserved_at_41[0x4]; 5156 u8 page_fault_type[0x3]; 5157 u8 wq_number[0x18]; 5158 5159 u8 reserved_at_60[0x8]; 5160 u8 token[0x18]; 5161 }; 5162 5163 struct mlx5_ifc_nop_out_bits { 5164 u8 status[0x8]; 5165 u8 reserved_at_8[0x18]; 5166 5167 u8 syndrome[0x20]; 5168 5169 u8 reserved_at_40[0x40]; 5170 }; 5171 5172 struct mlx5_ifc_nop_in_bits { 5173 u8 opcode[0x10]; 5174 u8 reserved_at_10[0x10]; 5175 5176 u8 reserved_at_20[0x10]; 5177 u8 op_mod[0x10]; 5178 5179 u8 reserved_at_40[0x40]; 5180 }; 5181 5182 struct mlx5_ifc_modify_vport_state_out_bits { 5183 u8 status[0x8]; 5184 u8 reserved_at_8[0x18]; 5185 5186 u8 syndrome[0x20]; 5187 5188 u8 reserved_at_40[0x40]; 5189 }; 5190 5191 struct mlx5_ifc_modify_vport_state_in_bits { 5192 u8 opcode[0x10]; 5193 u8 reserved_at_10[0x10]; 5194 5195 u8 reserved_at_20[0x10]; 5196 u8 op_mod[0x10]; 5197 5198 u8 other_vport[0x1]; 5199 u8 reserved_at_41[0xf]; 5200 u8 vport_number[0x10]; 5201 5202 u8 reserved_at_60[0x18]; 5203 u8 admin_state[0x4]; 5204 u8 reserved_at_7c[0x4]; 5205 }; 5206 5207 struct mlx5_ifc_modify_tis_out_bits { 5208 u8 status[0x8]; 5209 u8 reserved_at_8[0x18]; 5210 5211 u8 syndrome[0x20]; 5212 5213 u8 reserved_at_40[0x40]; 5214 }; 5215 5216 struct mlx5_ifc_modify_tis_bitmask_bits { 5217 u8 reserved_at_0[0x20]; 5218 5219 u8 reserved_at_20[0x1d]; 5220 u8 lag_tx_port_affinity[0x1]; 5221 u8 strict_lag_tx_port_affinity[0x1]; 5222 u8 prio[0x1]; 5223 }; 5224 5225 struct mlx5_ifc_modify_tis_in_bits { 5226 u8 opcode[0x10]; 5227 u8 reserved_at_10[0x10]; 5228 5229 u8 reserved_at_20[0x10]; 5230 u8 op_mod[0x10]; 5231 5232 u8 reserved_at_40[0x8]; 5233 u8 tisn[0x18]; 5234 5235 u8 reserved_at_60[0x20]; 5236 5237 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5238 5239 u8 reserved_at_c0[0x40]; 5240 5241 struct mlx5_ifc_tisc_bits ctx; 5242 }; 5243 5244 struct mlx5_ifc_modify_tir_bitmask_bits { 5245 u8 reserved_at_0[0x20]; 5246 5247 u8 reserved_at_20[0x1b]; 5248 u8 self_lb_en[0x1]; 5249 u8 reserved_at_3c[0x1]; 5250 u8 hash[0x1]; 5251 u8 reserved_at_3e[0x1]; 5252 u8 lro[0x1]; 5253 }; 5254 5255 struct mlx5_ifc_modify_tir_out_bits { 5256 u8 status[0x8]; 5257 u8 reserved_at_8[0x18]; 5258 5259 u8 syndrome[0x20]; 5260 5261 u8 reserved_at_40[0x40]; 5262 }; 5263 5264 struct mlx5_ifc_modify_tir_in_bits { 5265 u8 opcode[0x10]; 5266 u8 reserved_at_10[0x10]; 5267 5268 u8 reserved_at_20[0x10]; 5269 u8 op_mod[0x10]; 5270 5271 u8 reserved_at_40[0x8]; 5272 u8 tirn[0x18]; 5273 5274 u8 reserved_at_60[0x20]; 5275 5276 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5277 5278 u8 reserved_at_c0[0x40]; 5279 5280 struct mlx5_ifc_tirc_bits ctx; 5281 }; 5282 5283 struct mlx5_ifc_modify_sq_out_bits { 5284 u8 status[0x8]; 5285 u8 reserved_at_8[0x18]; 5286 5287 u8 syndrome[0x20]; 5288 5289 u8 reserved_at_40[0x40]; 5290 }; 5291 5292 struct mlx5_ifc_modify_sq_in_bits { 5293 u8 opcode[0x10]; 5294 u8 reserved_at_10[0x10]; 5295 5296 u8 reserved_at_20[0x10]; 5297 u8 op_mod[0x10]; 5298 5299 u8 sq_state[0x4]; 5300 u8 reserved_at_44[0x4]; 5301 u8 sqn[0x18]; 5302 5303 u8 reserved_at_60[0x20]; 5304 5305 u8 modify_bitmask[0x40]; 5306 5307 u8 reserved_at_c0[0x40]; 5308 5309 struct mlx5_ifc_sqc_bits ctx; 5310 }; 5311 5312 struct mlx5_ifc_modify_scheduling_element_out_bits { 5313 u8 status[0x8]; 5314 u8 reserved_at_8[0x18]; 5315 5316 u8 syndrome[0x20]; 5317 5318 u8 reserved_at_40[0x1c0]; 5319 }; 5320 5321 enum { 5322 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5323 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5324 }; 5325 5326 struct mlx5_ifc_modify_scheduling_element_in_bits { 5327 u8 opcode[0x10]; 5328 u8 reserved_at_10[0x10]; 5329 5330 u8 reserved_at_20[0x10]; 5331 u8 op_mod[0x10]; 5332 5333 u8 scheduling_hierarchy[0x8]; 5334 u8 reserved_at_48[0x18]; 5335 5336 u8 scheduling_element_id[0x20]; 5337 5338 u8 reserved_at_80[0x20]; 5339 5340 u8 modify_bitmask[0x20]; 5341 5342 u8 reserved_at_c0[0x40]; 5343 5344 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5345 5346 u8 reserved_at_300[0x100]; 5347 }; 5348 5349 struct mlx5_ifc_modify_rqt_out_bits { 5350 u8 status[0x8]; 5351 u8 reserved_at_8[0x18]; 5352 5353 u8 syndrome[0x20]; 5354 5355 u8 reserved_at_40[0x40]; 5356 }; 5357 5358 struct mlx5_ifc_rqt_bitmask_bits { 5359 u8 reserved_at_0[0x20]; 5360 5361 u8 reserved_at_20[0x1f]; 5362 u8 rqn_list[0x1]; 5363 }; 5364 5365 struct mlx5_ifc_modify_rqt_in_bits { 5366 u8 opcode[0x10]; 5367 u8 reserved_at_10[0x10]; 5368 5369 u8 reserved_at_20[0x10]; 5370 u8 op_mod[0x10]; 5371 5372 u8 reserved_at_40[0x8]; 5373 u8 rqtn[0x18]; 5374 5375 u8 reserved_at_60[0x20]; 5376 5377 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5378 5379 u8 reserved_at_c0[0x40]; 5380 5381 struct mlx5_ifc_rqtc_bits ctx; 5382 }; 5383 5384 struct mlx5_ifc_modify_rq_out_bits { 5385 u8 status[0x8]; 5386 u8 reserved_at_8[0x18]; 5387 5388 u8 syndrome[0x20]; 5389 5390 u8 reserved_at_40[0x40]; 5391 }; 5392 5393 enum { 5394 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5395 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5396 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5397 }; 5398 5399 struct mlx5_ifc_modify_rq_in_bits { 5400 u8 opcode[0x10]; 5401 u8 reserved_at_10[0x10]; 5402 5403 u8 reserved_at_20[0x10]; 5404 u8 op_mod[0x10]; 5405 5406 u8 rq_state[0x4]; 5407 u8 reserved_at_44[0x4]; 5408 u8 rqn[0x18]; 5409 5410 u8 reserved_at_60[0x20]; 5411 5412 u8 modify_bitmask[0x40]; 5413 5414 u8 reserved_at_c0[0x40]; 5415 5416 struct mlx5_ifc_rqc_bits ctx; 5417 }; 5418 5419 struct mlx5_ifc_modify_rmp_out_bits { 5420 u8 status[0x8]; 5421 u8 reserved_at_8[0x18]; 5422 5423 u8 syndrome[0x20]; 5424 5425 u8 reserved_at_40[0x40]; 5426 }; 5427 5428 struct mlx5_ifc_rmp_bitmask_bits { 5429 u8 reserved_at_0[0x20]; 5430 5431 u8 reserved_at_20[0x1f]; 5432 u8 lwm[0x1]; 5433 }; 5434 5435 struct mlx5_ifc_modify_rmp_in_bits { 5436 u8 opcode[0x10]; 5437 u8 reserved_at_10[0x10]; 5438 5439 u8 reserved_at_20[0x10]; 5440 u8 op_mod[0x10]; 5441 5442 u8 rmp_state[0x4]; 5443 u8 reserved_at_44[0x4]; 5444 u8 rmpn[0x18]; 5445 5446 u8 reserved_at_60[0x20]; 5447 5448 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5449 5450 u8 reserved_at_c0[0x40]; 5451 5452 struct mlx5_ifc_rmpc_bits ctx; 5453 }; 5454 5455 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5456 u8 status[0x8]; 5457 u8 reserved_at_8[0x18]; 5458 5459 u8 syndrome[0x20]; 5460 5461 u8 reserved_at_40[0x40]; 5462 }; 5463 5464 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5465 u8 reserved_at_0[0x12]; 5466 u8 affiliation[0x1]; 5467 u8 reserved_at_e[0x1]; 5468 u8 disable_uc_local_lb[0x1]; 5469 u8 disable_mc_local_lb[0x1]; 5470 u8 node_guid[0x1]; 5471 u8 port_guid[0x1]; 5472 u8 min_inline[0x1]; 5473 u8 mtu[0x1]; 5474 u8 change_event[0x1]; 5475 u8 promisc[0x1]; 5476 u8 permanent_address[0x1]; 5477 u8 addresses_list[0x1]; 5478 u8 roce_en[0x1]; 5479 u8 reserved_at_1f[0x1]; 5480 }; 5481 5482 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5483 u8 opcode[0x10]; 5484 u8 reserved_at_10[0x10]; 5485 5486 u8 reserved_at_20[0x10]; 5487 u8 op_mod[0x10]; 5488 5489 u8 other_vport[0x1]; 5490 u8 reserved_at_41[0xf]; 5491 u8 vport_number[0x10]; 5492 5493 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5494 5495 u8 reserved_at_80[0x780]; 5496 5497 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5498 }; 5499 5500 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5501 u8 status[0x8]; 5502 u8 reserved_at_8[0x18]; 5503 5504 u8 syndrome[0x20]; 5505 5506 u8 reserved_at_40[0x40]; 5507 }; 5508 5509 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5510 u8 opcode[0x10]; 5511 u8 reserved_at_10[0x10]; 5512 5513 u8 reserved_at_20[0x10]; 5514 u8 op_mod[0x10]; 5515 5516 u8 other_vport[0x1]; 5517 u8 reserved_at_41[0xb]; 5518 u8 port_num[0x4]; 5519 u8 vport_number[0x10]; 5520 5521 u8 reserved_at_60[0x20]; 5522 5523 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5524 }; 5525 5526 struct mlx5_ifc_modify_cq_out_bits { 5527 u8 status[0x8]; 5528 u8 reserved_at_8[0x18]; 5529 5530 u8 syndrome[0x20]; 5531 5532 u8 reserved_at_40[0x40]; 5533 }; 5534 5535 enum { 5536 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5537 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5538 }; 5539 5540 struct mlx5_ifc_modify_cq_in_bits { 5541 u8 opcode[0x10]; 5542 u8 reserved_at_10[0x10]; 5543 5544 u8 reserved_at_20[0x10]; 5545 u8 op_mod[0x10]; 5546 5547 u8 reserved_at_40[0x8]; 5548 u8 cqn[0x18]; 5549 5550 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5551 5552 struct mlx5_ifc_cqc_bits cq_context; 5553 5554 u8 reserved_at_280[0x600]; 5555 5556 u8 pas[0][0x40]; 5557 }; 5558 5559 struct mlx5_ifc_modify_cong_status_out_bits { 5560 u8 status[0x8]; 5561 u8 reserved_at_8[0x18]; 5562 5563 u8 syndrome[0x20]; 5564 5565 u8 reserved_at_40[0x40]; 5566 }; 5567 5568 struct mlx5_ifc_modify_cong_status_in_bits { 5569 u8 opcode[0x10]; 5570 u8 reserved_at_10[0x10]; 5571 5572 u8 reserved_at_20[0x10]; 5573 u8 op_mod[0x10]; 5574 5575 u8 reserved_at_40[0x18]; 5576 u8 priority[0x4]; 5577 u8 cong_protocol[0x4]; 5578 5579 u8 enable[0x1]; 5580 u8 tag_enable[0x1]; 5581 u8 reserved_at_62[0x1e]; 5582 }; 5583 5584 struct mlx5_ifc_modify_cong_params_out_bits { 5585 u8 status[0x8]; 5586 u8 reserved_at_8[0x18]; 5587 5588 u8 syndrome[0x20]; 5589 5590 u8 reserved_at_40[0x40]; 5591 }; 5592 5593 struct mlx5_ifc_modify_cong_params_in_bits { 5594 u8 opcode[0x10]; 5595 u8 reserved_at_10[0x10]; 5596 5597 u8 reserved_at_20[0x10]; 5598 u8 op_mod[0x10]; 5599 5600 u8 reserved_at_40[0x1c]; 5601 u8 cong_protocol[0x4]; 5602 5603 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5604 5605 u8 reserved_at_80[0x80]; 5606 5607 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5608 }; 5609 5610 struct mlx5_ifc_manage_pages_out_bits { 5611 u8 status[0x8]; 5612 u8 reserved_at_8[0x18]; 5613 5614 u8 syndrome[0x20]; 5615 5616 u8 output_num_entries[0x20]; 5617 5618 u8 reserved_at_60[0x20]; 5619 5620 u8 pas[0][0x40]; 5621 }; 5622 5623 enum { 5624 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5625 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5626 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5627 }; 5628 5629 struct mlx5_ifc_manage_pages_in_bits { 5630 u8 opcode[0x10]; 5631 u8 reserved_at_10[0x10]; 5632 5633 u8 reserved_at_20[0x10]; 5634 u8 op_mod[0x10]; 5635 5636 u8 reserved_at_40[0x10]; 5637 u8 function_id[0x10]; 5638 5639 u8 input_num_entries[0x20]; 5640 5641 u8 pas[0][0x40]; 5642 }; 5643 5644 struct mlx5_ifc_mad_ifc_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_at_8[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 5650 u8 reserved_at_40[0x40]; 5651 5652 u8 response_mad_packet[256][0x8]; 5653 }; 5654 5655 struct mlx5_ifc_mad_ifc_in_bits { 5656 u8 opcode[0x10]; 5657 u8 reserved_at_10[0x10]; 5658 5659 u8 reserved_at_20[0x10]; 5660 u8 op_mod[0x10]; 5661 5662 u8 remote_lid[0x10]; 5663 u8 reserved_at_50[0x8]; 5664 u8 port[0x8]; 5665 5666 u8 reserved_at_60[0x20]; 5667 5668 u8 mad[256][0x8]; 5669 }; 5670 5671 struct mlx5_ifc_init_hca_out_bits { 5672 u8 status[0x8]; 5673 u8 reserved_at_8[0x18]; 5674 5675 u8 syndrome[0x20]; 5676 5677 u8 reserved_at_40[0x40]; 5678 }; 5679 5680 struct mlx5_ifc_init_hca_in_bits { 5681 u8 opcode[0x10]; 5682 u8 reserved_at_10[0x10]; 5683 5684 u8 reserved_at_20[0x10]; 5685 u8 op_mod[0x10]; 5686 5687 u8 reserved_at_40[0x40]; 5688 u8 sw_owner_id[4][0x20]; 5689 }; 5690 5691 struct mlx5_ifc_init2rtr_qp_out_bits { 5692 u8 status[0x8]; 5693 u8 reserved_at_8[0x18]; 5694 5695 u8 syndrome[0x20]; 5696 5697 u8 reserved_at_40[0x40]; 5698 }; 5699 5700 struct mlx5_ifc_init2rtr_qp_in_bits { 5701 u8 opcode[0x10]; 5702 u8 reserved_at_10[0x10]; 5703 5704 u8 reserved_at_20[0x10]; 5705 u8 op_mod[0x10]; 5706 5707 u8 reserved_at_40[0x8]; 5708 u8 qpn[0x18]; 5709 5710 u8 reserved_at_60[0x20]; 5711 5712 u8 opt_param_mask[0x20]; 5713 5714 u8 reserved_at_a0[0x20]; 5715 5716 struct mlx5_ifc_qpc_bits qpc; 5717 5718 u8 reserved_at_800[0x80]; 5719 }; 5720 5721 struct mlx5_ifc_init2init_qp_out_bits { 5722 u8 status[0x8]; 5723 u8 reserved_at_8[0x18]; 5724 5725 u8 syndrome[0x20]; 5726 5727 u8 reserved_at_40[0x40]; 5728 }; 5729 5730 struct mlx5_ifc_init2init_qp_in_bits { 5731 u8 opcode[0x10]; 5732 u8 reserved_at_10[0x10]; 5733 5734 u8 reserved_at_20[0x10]; 5735 u8 op_mod[0x10]; 5736 5737 u8 reserved_at_40[0x8]; 5738 u8 qpn[0x18]; 5739 5740 u8 reserved_at_60[0x20]; 5741 5742 u8 opt_param_mask[0x20]; 5743 5744 u8 reserved_at_a0[0x20]; 5745 5746 struct mlx5_ifc_qpc_bits qpc; 5747 5748 u8 reserved_at_800[0x80]; 5749 }; 5750 5751 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5752 u8 status[0x8]; 5753 u8 reserved_at_8[0x18]; 5754 5755 u8 syndrome[0x20]; 5756 5757 u8 reserved_at_40[0x40]; 5758 5759 u8 packet_headers_log[128][0x8]; 5760 5761 u8 packet_syndrome[64][0x8]; 5762 }; 5763 5764 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5765 u8 opcode[0x10]; 5766 u8 reserved_at_10[0x10]; 5767 5768 u8 reserved_at_20[0x10]; 5769 u8 op_mod[0x10]; 5770 5771 u8 reserved_at_40[0x40]; 5772 }; 5773 5774 struct mlx5_ifc_gen_eqe_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 reserved_at_40[0x18]; 5782 u8 eq_number[0x8]; 5783 5784 u8 reserved_at_60[0x20]; 5785 5786 u8 eqe[64][0x8]; 5787 }; 5788 5789 struct mlx5_ifc_gen_eq_out_bits { 5790 u8 status[0x8]; 5791 u8 reserved_at_8[0x18]; 5792 5793 u8 syndrome[0x20]; 5794 5795 u8 reserved_at_40[0x40]; 5796 }; 5797 5798 struct mlx5_ifc_enable_hca_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_at_8[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 reserved_at_40[0x20]; 5805 }; 5806 5807 struct mlx5_ifc_enable_hca_in_bits { 5808 u8 opcode[0x10]; 5809 u8 reserved_at_10[0x10]; 5810 5811 u8 reserved_at_20[0x10]; 5812 u8 op_mod[0x10]; 5813 5814 u8 reserved_at_40[0x10]; 5815 u8 function_id[0x10]; 5816 5817 u8 reserved_at_60[0x20]; 5818 }; 5819 5820 struct mlx5_ifc_drain_dct_out_bits { 5821 u8 status[0x8]; 5822 u8 reserved_at_8[0x18]; 5823 5824 u8 syndrome[0x20]; 5825 5826 u8 reserved_at_40[0x40]; 5827 }; 5828 5829 struct mlx5_ifc_drain_dct_in_bits { 5830 u8 opcode[0x10]; 5831 u8 reserved_at_10[0x10]; 5832 5833 u8 reserved_at_20[0x10]; 5834 u8 op_mod[0x10]; 5835 5836 u8 reserved_at_40[0x8]; 5837 u8 dctn[0x18]; 5838 5839 u8 reserved_at_60[0x20]; 5840 }; 5841 5842 struct mlx5_ifc_disable_hca_out_bits { 5843 u8 status[0x8]; 5844 u8 reserved_at_8[0x18]; 5845 5846 u8 syndrome[0x20]; 5847 5848 u8 reserved_at_40[0x20]; 5849 }; 5850 5851 struct mlx5_ifc_disable_hca_in_bits { 5852 u8 opcode[0x10]; 5853 u8 reserved_at_10[0x10]; 5854 5855 u8 reserved_at_20[0x10]; 5856 u8 op_mod[0x10]; 5857 5858 u8 reserved_at_40[0x10]; 5859 u8 function_id[0x10]; 5860 5861 u8 reserved_at_60[0x20]; 5862 }; 5863 5864 struct mlx5_ifc_detach_from_mcg_out_bits { 5865 u8 status[0x8]; 5866 u8 reserved_at_8[0x18]; 5867 5868 u8 syndrome[0x20]; 5869 5870 u8 reserved_at_40[0x40]; 5871 }; 5872 5873 struct mlx5_ifc_detach_from_mcg_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_at_10[0x10]; 5876 5877 u8 reserved_at_20[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 reserved_at_40[0x8]; 5881 u8 qpn[0x18]; 5882 5883 u8 reserved_at_60[0x20]; 5884 5885 u8 multicast_gid[16][0x8]; 5886 }; 5887 5888 struct mlx5_ifc_destroy_xrq_out_bits { 5889 u8 status[0x8]; 5890 u8 reserved_at_8[0x18]; 5891 5892 u8 syndrome[0x20]; 5893 5894 u8 reserved_at_40[0x40]; 5895 }; 5896 5897 struct mlx5_ifc_destroy_xrq_in_bits { 5898 u8 opcode[0x10]; 5899 u8 reserved_at_10[0x10]; 5900 5901 u8 reserved_at_20[0x10]; 5902 u8 op_mod[0x10]; 5903 5904 u8 reserved_at_40[0x8]; 5905 u8 xrqn[0x18]; 5906 5907 u8 reserved_at_60[0x20]; 5908 }; 5909 5910 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5911 u8 status[0x8]; 5912 u8 reserved_at_8[0x18]; 5913 5914 u8 syndrome[0x20]; 5915 5916 u8 reserved_at_40[0x40]; 5917 }; 5918 5919 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5920 u8 opcode[0x10]; 5921 u8 reserved_at_10[0x10]; 5922 5923 u8 reserved_at_20[0x10]; 5924 u8 op_mod[0x10]; 5925 5926 u8 reserved_at_40[0x8]; 5927 u8 xrc_srqn[0x18]; 5928 5929 u8 reserved_at_60[0x20]; 5930 }; 5931 5932 struct mlx5_ifc_destroy_tis_out_bits { 5933 u8 status[0x8]; 5934 u8 reserved_at_8[0x18]; 5935 5936 u8 syndrome[0x20]; 5937 5938 u8 reserved_at_40[0x40]; 5939 }; 5940 5941 struct mlx5_ifc_destroy_tis_in_bits { 5942 u8 opcode[0x10]; 5943 u8 reserved_at_10[0x10]; 5944 5945 u8 reserved_at_20[0x10]; 5946 u8 op_mod[0x10]; 5947 5948 u8 reserved_at_40[0x8]; 5949 u8 tisn[0x18]; 5950 5951 u8 reserved_at_60[0x20]; 5952 }; 5953 5954 struct mlx5_ifc_destroy_tir_out_bits { 5955 u8 status[0x8]; 5956 u8 reserved_at_8[0x18]; 5957 5958 u8 syndrome[0x20]; 5959 5960 u8 reserved_at_40[0x40]; 5961 }; 5962 5963 struct mlx5_ifc_destroy_tir_in_bits { 5964 u8 opcode[0x10]; 5965 u8 reserved_at_10[0x10]; 5966 5967 u8 reserved_at_20[0x10]; 5968 u8 op_mod[0x10]; 5969 5970 u8 reserved_at_40[0x8]; 5971 u8 tirn[0x18]; 5972 5973 u8 reserved_at_60[0x20]; 5974 }; 5975 5976 struct mlx5_ifc_destroy_srq_out_bits { 5977 u8 status[0x8]; 5978 u8 reserved_at_8[0x18]; 5979 5980 u8 syndrome[0x20]; 5981 5982 u8 reserved_at_40[0x40]; 5983 }; 5984 5985 struct mlx5_ifc_destroy_srq_in_bits { 5986 u8 opcode[0x10]; 5987 u8 reserved_at_10[0x10]; 5988 5989 u8 reserved_at_20[0x10]; 5990 u8 op_mod[0x10]; 5991 5992 u8 reserved_at_40[0x8]; 5993 u8 srqn[0x18]; 5994 5995 u8 reserved_at_60[0x20]; 5996 }; 5997 5998 struct mlx5_ifc_destroy_sq_out_bits { 5999 u8 status[0x8]; 6000 u8 reserved_at_8[0x18]; 6001 6002 u8 syndrome[0x20]; 6003 6004 u8 reserved_at_40[0x40]; 6005 }; 6006 6007 struct mlx5_ifc_destroy_sq_in_bits { 6008 u8 opcode[0x10]; 6009 u8 reserved_at_10[0x10]; 6010 6011 u8 reserved_at_20[0x10]; 6012 u8 op_mod[0x10]; 6013 6014 u8 reserved_at_40[0x8]; 6015 u8 sqn[0x18]; 6016 6017 u8 reserved_at_60[0x20]; 6018 }; 6019 6020 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6021 u8 status[0x8]; 6022 u8 reserved_at_8[0x18]; 6023 6024 u8 syndrome[0x20]; 6025 6026 u8 reserved_at_40[0x1c0]; 6027 }; 6028 6029 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6030 u8 opcode[0x10]; 6031 u8 reserved_at_10[0x10]; 6032 6033 u8 reserved_at_20[0x10]; 6034 u8 op_mod[0x10]; 6035 6036 u8 scheduling_hierarchy[0x8]; 6037 u8 reserved_at_48[0x18]; 6038 6039 u8 scheduling_element_id[0x20]; 6040 6041 u8 reserved_at_80[0x180]; 6042 }; 6043 6044 struct mlx5_ifc_destroy_rqt_out_bits { 6045 u8 status[0x8]; 6046 u8 reserved_at_8[0x18]; 6047 6048 u8 syndrome[0x20]; 6049 6050 u8 reserved_at_40[0x40]; 6051 }; 6052 6053 struct mlx5_ifc_destroy_rqt_in_bits { 6054 u8 opcode[0x10]; 6055 u8 reserved_at_10[0x10]; 6056 6057 u8 reserved_at_20[0x10]; 6058 u8 op_mod[0x10]; 6059 6060 u8 reserved_at_40[0x8]; 6061 u8 rqtn[0x18]; 6062 6063 u8 reserved_at_60[0x20]; 6064 }; 6065 6066 struct mlx5_ifc_destroy_rq_out_bits { 6067 u8 status[0x8]; 6068 u8 reserved_at_8[0x18]; 6069 6070 u8 syndrome[0x20]; 6071 6072 u8 reserved_at_40[0x40]; 6073 }; 6074 6075 struct mlx5_ifc_destroy_rq_in_bits { 6076 u8 opcode[0x10]; 6077 u8 reserved_at_10[0x10]; 6078 6079 u8 reserved_at_20[0x10]; 6080 u8 op_mod[0x10]; 6081 6082 u8 reserved_at_40[0x8]; 6083 u8 rqn[0x18]; 6084 6085 u8 reserved_at_60[0x20]; 6086 }; 6087 6088 struct mlx5_ifc_set_delay_drop_params_in_bits { 6089 u8 opcode[0x10]; 6090 u8 reserved_at_10[0x10]; 6091 6092 u8 reserved_at_20[0x10]; 6093 u8 op_mod[0x10]; 6094 6095 u8 reserved_at_40[0x20]; 6096 6097 u8 reserved_at_60[0x10]; 6098 u8 delay_drop_timeout[0x10]; 6099 }; 6100 6101 struct mlx5_ifc_set_delay_drop_params_out_bits { 6102 u8 status[0x8]; 6103 u8 reserved_at_8[0x18]; 6104 6105 u8 syndrome[0x20]; 6106 6107 u8 reserved_at_40[0x40]; 6108 }; 6109 6110 struct mlx5_ifc_destroy_rmp_out_bits { 6111 u8 status[0x8]; 6112 u8 reserved_at_8[0x18]; 6113 6114 u8 syndrome[0x20]; 6115 6116 u8 reserved_at_40[0x40]; 6117 }; 6118 6119 struct mlx5_ifc_destroy_rmp_in_bits { 6120 u8 opcode[0x10]; 6121 u8 reserved_at_10[0x10]; 6122 6123 u8 reserved_at_20[0x10]; 6124 u8 op_mod[0x10]; 6125 6126 u8 reserved_at_40[0x8]; 6127 u8 rmpn[0x18]; 6128 6129 u8 reserved_at_60[0x20]; 6130 }; 6131 6132 struct mlx5_ifc_destroy_qp_out_bits { 6133 u8 status[0x8]; 6134 u8 reserved_at_8[0x18]; 6135 6136 u8 syndrome[0x20]; 6137 6138 u8 reserved_at_40[0x40]; 6139 }; 6140 6141 struct mlx5_ifc_destroy_qp_in_bits { 6142 u8 opcode[0x10]; 6143 u8 reserved_at_10[0x10]; 6144 6145 u8 reserved_at_20[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 reserved_at_40[0x8]; 6149 u8 qpn[0x18]; 6150 6151 u8 reserved_at_60[0x20]; 6152 }; 6153 6154 struct mlx5_ifc_destroy_psv_out_bits { 6155 u8 status[0x8]; 6156 u8 reserved_at_8[0x18]; 6157 6158 u8 syndrome[0x20]; 6159 6160 u8 reserved_at_40[0x40]; 6161 }; 6162 6163 struct mlx5_ifc_destroy_psv_in_bits { 6164 u8 opcode[0x10]; 6165 u8 reserved_at_10[0x10]; 6166 6167 u8 reserved_at_20[0x10]; 6168 u8 op_mod[0x10]; 6169 6170 u8 reserved_at_40[0x8]; 6171 u8 psvn[0x18]; 6172 6173 u8 reserved_at_60[0x20]; 6174 }; 6175 6176 struct mlx5_ifc_destroy_mkey_out_bits { 6177 u8 status[0x8]; 6178 u8 reserved_at_8[0x18]; 6179 6180 u8 syndrome[0x20]; 6181 6182 u8 reserved_at_40[0x40]; 6183 }; 6184 6185 struct mlx5_ifc_destroy_mkey_in_bits { 6186 u8 opcode[0x10]; 6187 u8 reserved_at_10[0x10]; 6188 6189 u8 reserved_at_20[0x10]; 6190 u8 op_mod[0x10]; 6191 6192 u8 reserved_at_40[0x8]; 6193 u8 mkey_index[0x18]; 6194 6195 u8 reserved_at_60[0x20]; 6196 }; 6197 6198 struct mlx5_ifc_destroy_flow_table_out_bits { 6199 u8 status[0x8]; 6200 u8 reserved_at_8[0x18]; 6201 6202 u8 syndrome[0x20]; 6203 6204 u8 reserved_at_40[0x40]; 6205 }; 6206 6207 struct mlx5_ifc_destroy_flow_table_in_bits { 6208 u8 opcode[0x10]; 6209 u8 reserved_at_10[0x10]; 6210 6211 u8 reserved_at_20[0x10]; 6212 u8 op_mod[0x10]; 6213 6214 u8 other_vport[0x1]; 6215 u8 reserved_at_41[0xf]; 6216 u8 vport_number[0x10]; 6217 6218 u8 reserved_at_60[0x20]; 6219 6220 u8 table_type[0x8]; 6221 u8 reserved_at_88[0x18]; 6222 6223 u8 reserved_at_a0[0x8]; 6224 u8 table_id[0x18]; 6225 6226 u8 reserved_at_c0[0x140]; 6227 }; 6228 6229 struct mlx5_ifc_destroy_flow_group_out_bits { 6230 u8 status[0x8]; 6231 u8 reserved_at_8[0x18]; 6232 6233 u8 syndrome[0x20]; 6234 6235 u8 reserved_at_40[0x40]; 6236 }; 6237 6238 struct mlx5_ifc_destroy_flow_group_in_bits { 6239 u8 opcode[0x10]; 6240 u8 reserved_at_10[0x10]; 6241 6242 u8 reserved_at_20[0x10]; 6243 u8 op_mod[0x10]; 6244 6245 u8 other_vport[0x1]; 6246 u8 reserved_at_41[0xf]; 6247 u8 vport_number[0x10]; 6248 6249 u8 reserved_at_60[0x20]; 6250 6251 u8 table_type[0x8]; 6252 u8 reserved_at_88[0x18]; 6253 6254 u8 reserved_at_a0[0x8]; 6255 u8 table_id[0x18]; 6256 6257 u8 group_id[0x20]; 6258 6259 u8 reserved_at_e0[0x120]; 6260 }; 6261 6262 struct mlx5_ifc_destroy_eq_out_bits { 6263 u8 status[0x8]; 6264 u8 reserved_at_8[0x18]; 6265 6266 u8 syndrome[0x20]; 6267 6268 u8 reserved_at_40[0x40]; 6269 }; 6270 6271 struct mlx5_ifc_destroy_eq_in_bits { 6272 u8 opcode[0x10]; 6273 u8 reserved_at_10[0x10]; 6274 6275 u8 reserved_at_20[0x10]; 6276 u8 op_mod[0x10]; 6277 6278 u8 reserved_at_40[0x18]; 6279 u8 eq_number[0x8]; 6280 6281 u8 reserved_at_60[0x20]; 6282 }; 6283 6284 struct mlx5_ifc_destroy_dct_out_bits { 6285 u8 status[0x8]; 6286 u8 reserved_at_8[0x18]; 6287 6288 u8 syndrome[0x20]; 6289 6290 u8 reserved_at_40[0x40]; 6291 }; 6292 6293 struct mlx5_ifc_destroy_dct_in_bits { 6294 u8 opcode[0x10]; 6295 u8 reserved_at_10[0x10]; 6296 6297 u8 reserved_at_20[0x10]; 6298 u8 op_mod[0x10]; 6299 6300 u8 reserved_at_40[0x8]; 6301 u8 dctn[0x18]; 6302 6303 u8 reserved_at_60[0x20]; 6304 }; 6305 6306 struct mlx5_ifc_destroy_cq_out_bits { 6307 u8 status[0x8]; 6308 u8 reserved_at_8[0x18]; 6309 6310 u8 syndrome[0x20]; 6311 6312 u8 reserved_at_40[0x40]; 6313 }; 6314 6315 struct mlx5_ifc_destroy_cq_in_bits { 6316 u8 opcode[0x10]; 6317 u8 reserved_at_10[0x10]; 6318 6319 u8 reserved_at_20[0x10]; 6320 u8 op_mod[0x10]; 6321 6322 u8 reserved_at_40[0x8]; 6323 u8 cqn[0x18]; 6324 6325 u8 reserved_at_60[0x20]; 6326 }; 6327 6328 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6329 u8 status[0x8]; 6330 u8 reserved_at_8[0x18]; 6331 6332 u8 syndrome[0x20]; 6333 6334 u8 reserved_at_40[0x40]; 6335 }; 6336 6337 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6338 u8 opcode[0x10]; 6339 u8 reserved_at_10[0x10]; 6340 6341 u8 reserved_at_20[0x10]; 6342 u8 op_mod[0x10]; 6343 6344 u8 reserved_at_40[0x20]; 6345 6346 u8 reserved_at_60[0x10]; 6347 u8 vxlan_udp_port[0x10]; 6348 }; 6349 6350 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6351 u8 status[0x8]; 6352 u8 reserved_at_8[0x18]; 6353 6354 u8 syndrome[0x20]; 6355 6356 u8 reserved_at_40[0x40]; 6357 }; 6358 6359 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6360 u8 opcode[0x10]; 6361 u8 reserved_at_10[0x10]; 6362 6363 u8 reserved_at_20[0x10]; 6364 u8 op_mod[0x10]; 6365 6366 u8 reserved_at_40[0x60]; 6367 6368 u8 reserved_at_a0[0x8]; 6369 u8 table_index[0x18]; 6370 6371 u8 reserved_at_c0[0x140]; 6372 }; 6373 6374 struct mlx5_ifc_delete_fte_out_bits { 6375 u8 status[0x8]; 6376 u8 reserved_at_8[0x18]; 6377 6378 u8 syndrome[0x20]; 6379 6380 u8 reserved_at_40[0x40]; 6381 }; 6382 6383 struct mlx5_ifc_delete_fte_in_bits { 6384 u8 opcode[0x10]; 6385 u8 reserved_at_10[0x10]; 6386 6387 u8 reserved_at_20[0x10]; 6388 u8 op_mod[0x10]; 6389 6390 u8 other_vport[0x1]; 6391 u8 reserved_at_41[0xf]; 6392 u8 vport_number[0x10]; 6393 6394 u8 reserved_at_60[0x20]; 6395 6396 u8 table_type[0x8]; 6397 u8 reserved_at_88[0x18]; 6398 6399 u8 reserved_at_a0[0x8]; 6400 u8 table_id[0x18]; 6401 6402 u8 reserved_at_c0[0x40]; 6403 6404 u8 flow_index[0x20]; 6405 6406 u8 reserved_at_120[0xe0]; 6407 }; 6408 6409 struct mlx5_ifc_dealloc_xrcd_out_bits { 6410 u8 status[0x8]; 6411 u8 reserved_at_8[0x18]; 6412 6413 u8 syndrome[0x20]; 6414 6415 u8 reserved_at_40[0x40]; 6416 }; 6417 6418 struct mlx5_ifc_dealloc_xrcd_in_bits { 6419 u8 opcode[0x10]; 6420 u8 reserved_at_10[0x10]; 6421 6422 u8 reserved_at_20[0x10]; 6423 u8 op_mod[0x10]; 6424 6425 u8 reserved_at_40[0x8]; 6426 u8 xrcd[0x18]; 6427 6428 u8 reserved_at_60[0x20]; 6429 }; 6430 6431 struct mlx5_ifc_dealloc_uar_out_bits { 6432 u8 status[0x8]; 6433 u8 reserved_at_8[0x18]; 6434 6435 u8 syndrome[0x20]; 6436 6437 u8 reserved_at_40[0x40]; 6438 }; 6439 6440 struct mlx5_ifc_dealloc_uar_in_bits { 6441 u8 opcode[0x10]; 6442 u8 reserved_at_10[0x10]; 6443 6444 u8 reserved_at_20[0x10]; 6445 u8 op_mod[0x10]; 6446 6447 u8 reserved_at_40[0x8]; 6448 u8 uar[0x18]; 6449 6450 u8 reserved_at_60[0x20]; 6451 }; 6452 6453 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6454 u8 status[0x8]; 6455 u8 reserved_at_8[0x18]; 6456 6457 u8 syndrome[0x20]; 6458 6459 u8 reserved_at_40[0x40]; 6460 }; 6461 6462 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6463 u8 opcode[0x10]; 6464 u8 reserved_at_10[0x10]; 6465 6466 u8 reserved_at_20[0x10]; 6467 u8 op_mod[0x10]; 6468 6469 u8 reserved_at_40[0x8]; 6470 u8 transport_domain[0x18]; 6471 6472 u8 reserved_at_60[0x20]; 6473 }; 6474 6475 struct mlx5_ifc_dealloc_q_counter_out_bits { 6476 u8 status[0x8]; 6477 u8 reserved_at_8[0x18]; 6478 6479 u8 syndrome[0x20]; 6480 6481 u8 reserved_at_40[0x40]; 6482 }; 6483 6484 struct mlx5_ifc_dealloc_q_counter_in_bits { 6485 u8 opcode[0x10]; 6486 u8 reserved_at_10[0x10]; 6487 6488 u8 reserved_at_20[0x10]; 6489 u8 op_mod[0x10]; 6490 6491 u8 reserved_at_40[0x18]; 6492 u8 counter_set_id[0x8]; 6493 6494 u8 reserved_at_60[0x20]; 6495 }; 6496 6497 struct mlx5_ifc_dealloc_pd_out_bits { 6498 u8 status[0x8]; 6499 u8 reserved_at_8[0x18]; 6500 6501 u8 syndrome[0x20]; 6502 6503 u8 reserved_at_40[0x40]; 6504 }; 6505 6506 struct mlx5_ifc_dealloc_pd_in_bits { 6507 u8 opcode[0x10]; 6508 u8 reserved_at_10[0x10]; 6509 6510 u8 reserved_at_20[0x10]; 6511 u8 op_mod[0x10]; 6512 6513 u8 reserved_at_40[0x8]; 6514 u8 pd[0x18]; 6515 6516 u8 reserved_at_60[0x20]; 6517 }; 6518 6519 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6520 u8 status[0x8]; 6521 u8 reserved_at_8[0x18]; 6522 6523 u8 syndrome[0x20]; 6524 6525 u8 reserved_at_40[0x40]; 6526 }; 6527 6528 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6529 u8 opcode[0x10]; 6530 u8 reserved_at_10[0x10]; 6531 6532 u8 reserved_at_20[0x10]; 6533 u8 op_mod[0x10]; 6534 6535 u8 flow_counter_id[0x20]; 6536 6537 u8 reserved_at_60[0x20]; 6538 }; 6539 6540 struct mlx5_ifc_create_xrq_out_bits { 6541 u8 status[0x8]; 6542 u8 reserved_at_8[0x18]; 6543 6544 u8 syndrome[0x20]; 6545 6546 u8 reserved_at_40[0x8]; 6547 u8 xrqn[0x18]; 6548 6549 u8 reserved_at_60[0x20]; 6550 }; 6551 6552 struct mlx5_ifc_create_xrq_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_at_10[0x10]; 6555 6556 u8 reserved_at_20[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 reserved_at_40[0x40]; 6560 6561 struct mlx5_ifc_xrqc_bits xrq_context; 6562 }; 6563 6564 struct mlx5_ifc_create_xrc_srq_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_at_8[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_at_40[0x8]; 6571 u8 xrc_srqn[0x18]; 6572 6573 u8 reserved_at_60[0x20]; 6574 }; 6575 6576 struct mlx5_ifc_create_xrc_srq_in_bits { 6577 u8 opcode[0x10]; 6578 u8 reserved_at_10[0x10]; 6579 6580 u8 reserved_at_20[0x10]; 6581 u8 op_mod[0x10]; 6582 6583 u8 reserved_at_40[0x40]; 6584 6585 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6586 6587 u8 reserved_at_280[0x600]; 6588 6589 u8 pas[0][0x40]; 6590 }; 6591 6592 struct mlx5_ifc_create_tis_out_bits { 6593 u8 status[0x8]; 6594 u8 reserved_at_8[0x18]; 6595 6596 u8 syndrome[0x20]; 6597 6598 u8 reserved_at_40[0x8]; 6599 u8 tisn[0x18]; 6600 6601 u8 reserved_at_60[0x20]; 6602 }; 6603 6604 struct mlx5_ifc_create_tis_in_bits { 6605 u8 opcode[0x10]; 6606 u8 reserved_at_10[0x10]; 6607 6608 u8 reserved_at_20[0x10]; 6609 u8 op_mod[0x10]; 6610 6611 u8 reserved_at_40[0xc0]; 6612 6613 struct mlx5_ifc_tisc_bits ctx; 6614 }; 6615 6616 struct mlx5_ifc_create_tir_out_bits { 6617 u8 status[0x8]; 6618 u8 reserved_at_8[0x18]; 6619 6620 u8 syndrome[0x20]; 6621 6622 u8 reserved_at_40[0x8]; 6623 u8 tirn[0x18]; 6624 6625 u8 reserved_at_60[0x20]; 6626 }; 6627 6628 struct mlx5_ifc_create_tir_in_bits { 6629 u8 opcode[0x10]; 6630 u8 reserved_at_10[0x10]; 6631 6632 u8 reserved_at_20[0x10]; 6633 u8 op_mod[0x10]; 6634 6635 u8 reserved_at_40[0xc0]; 6636 6637 struct mlx5_ifc_tirc_bits ctx; 6638 }; 6639 6640 struct mlx5_ifc_create_srq_out_bits { 6641 u8 status[0x8]; 6642 u8 reserved_at_8[0x18]; 6643 6644 u8 syndrome[0x20]; 6645 6646 u8 reserved_at_40[0x8]; 6647 u8 srqn[0x18]; 6648 6649 u8 reserved_at_60[0x20]; 6650 }; 6651 6652 struct mlx5_ifc_create_srq_in_bits { 6653 u8 opcode[0x10]; 6654 u8 reserved_at_10[0x10]; 6655 6656 u8 reserved_at_20[0x10]; 6657 u8 op_mod[0x10]; 6658 6659 u8 reserved_at_40[0x40]; 6660 6661 struct mlx5_ifc_srqc_bits srq_context_entry; 6662 6663 u8 reserved_at_280[0x600]; 6664 6665 u8 pas[0][0x40]; 6666 }; 6667 6668 struct mlx5_ifc_create_sq_out_bits { 6669 u8 status[0x8]; 6670 u8 reserved_at_8[0x18]; 6671 6672 u8 syndrome[0x20]; 6673 6674 u8 reserved_at_40[0x8]; 6675 u8 sqn[0x18]; 6676 6677 u8 reserved_at_60[0x20]; 6678 }; 6679 6680 struct mlx5_ifc_create_sq_in_bits { 6681 u8 opcode[0x10]; 6682 u8 reserved_at_10[0x10]; 6683 6684 u8 reserved_at_20[0x10]; 6685 u8 op_mod[0x10]; 6686 6687 u8 reserved_at_40[0xc0]; 6688 6689 struct mlx5_ifc_sqc_bits ctx; 6690 }; 6691 6692 struct mlx5_ifc_create_scheduling_element_out_bits { 6693 u8 status[0x8]; 6694 u8 reserved_at_8[0x18]; 6695 6696 u8 syndrome[0x20]; 6697 6698 u8 reserved_at_40[0x40]; 6699 6700 u8 scheduling_element_id[0x20]; 6701 6702 u8 reserved_at_a0[0x160]; 6703 }; 6704 6705 struct mlx5_ifc_create_scheduling_element_in_bits { 6706 u8 opcode[0x10]; 6707 u8 reserved_at_10[0x10]; 6708 6709 u8 reserved_at_20[0x10]; 6710 u8 op_mod[0x10]; 6711 6712 u8 scheduling_hierarchy[0x8]; 6713 u8 reserved_at_48[0x18]; 6714 6715 u8 reserved_at_60[0xa0]; 6716 6717 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6718 6719 u8 reserved_at_300[0x100]; 6720 }; 6721 6722 struct mlx5_ifc_create_rqt_out_bits { 6723 u8 status[0x8]; 6724 u8 reserved_at_8[0x18]; 6725 6726 u8 syndrome[0x20]; 6727 6728 u8 reserved_at_40[0x8]; 6729 u8 rqtn[0x18]; 6730 6731 u8 reserved_at_60[0x20]; 6732 }; 6733 6734 struct mlx5_ifc_create_rqt_in_bits { 6735 u8 opcode[0x10]; 6736 u8 reserved_at_10[0x10]; 6737 6738 u8 reserved_at_20[0x10]; 6739 u8 op_mod[0x10]; 6740 6741 u8 reserved_at_40[0xc0]; 6742 6743 struct mlx5_ifc_rqtc_bits rqt_context; 6744 }; 6745 6746 struct mlx5_ifc_create_rq_out_bits { 6747 u8 status[0x8]; 6748 u8 reserved_at_8[0x18]; 6749 6750 u8 syndrome[0x20]; 6751 6752 u8 reserved_at_40[0x8]; 6753 u8 rqn[0x18]; 6754 6755 u8 reserved_at_60[0x20]; 6756 }; 6757 6758 struct mlx5_ifc_create_rq_in_bits { 6759 u8 opcode[0x10]; 6760 u8 reserved_at_10[0x10]; 6761 6762 u8 reserved_at_20[0x10]; 6763 u8 op_mod[0x10]; 6764 6765 u8 reserved_at_40[0xc0]; 6766 6767 struct mlx5_ifc_rqc_bits ctx; 6768 }; 6769 6770 struct mlx5_ifc_create_rmp_out_bits { 6771 u8 status[0x8]; 6772 u8 reserved_at_8[0x18]; 6773 6774 u8 syndrome[0x20]; 6775 6776 u8 reserved_at_40[0x8]; 6777 u8 rmpn[0x18]; 6778 6779 u8 reserved_at_60[0x20]; 6780 }; 6781 6782 struct mlx5_ifc_create_rmp_in_bits { 6783 u8 opcode[0x10]; 6784 u8 reserved_at_10[0x10]; 6785 6786 u8 reserved_at_20[0x10]; 6787 u8 op_mod[0x10]; 6788 6789 u8 reserved_at_40[0xc0]; 6790 6791 struct mlx5_ifc_rmpc_bits ctx; 6792 }; 6793 6794 struct mlx5_ifc_create_qp_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_at_8[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 reserved_at_40[0x8]; 6801 u8 qpn[0x18]; 6802 6803 u8 reserved_at_60[0x20]; 6804 }; 6805 6806 struct mlx5_ifc_create_qp_in_bits { 6807 u8 opcode[0x10]; 6808 u8 reserved_at_10[0x10]; 6809 6810 u8 reserved_at_20[0x10]; 6811 u8 op_mod[0x10]; 6812 6813 u8 reserved_at_40[0x40]; 6814 6815 u8 opt_param_mask[0x20]; 6816 6817 u8 reserved_at_a0[0x20]; 6818 6819 struct mlx5_ifc_qpc_bits qpc; 6820 6821 u8 reserved_at_800[0x80]; 6822 6823 u8 pas[0][0x40]; 6824 }; 6825 6826 struct mlx5_ifc_create_psv_out_bits { 6827 u8 status[0x8]; 6828 u8 reserved_at_8[0x18]; 6829 6830 u8 syndrome[0x20]; 6831 6832 u8 reserved_at_40[0x40]; 6833 6834 u8 reserved_at_80[0x8]; 6835 u8 psv0_index[0x18]; 6836 6837 u8 reserved_at_a0[0x8]; 6838 u8 psv1_index[0x18]; 6839 6840 u8 reserved_at_c0[0x8]; 6841 u8 psv2_index[0x18]; 6842 6843 u8 reserved_at_e0[0x8]; 6844 u8 psv3_index[0x18]; 6845 }; 6846 6847 struct mlx5_ifc_create_psv_in_bits { 6848 u8 opcode[0x10]; 6849 u8 reserved_at_10[0x10]; 6850 6851 u8 reserved_at_20[0x10]; 6852 u8 op_mod[0x10]; 6853 6854 u8 num_psv[0x4]; 6855 u8 reserved_at_44[0x4]; 6856 u8 pd[0x18]; 6857 6858 u8 reserved_at_60[0x20]; 6859 }; 6860 6861 struct mlx5_ifc_create_mkey_out_bits { 6862 u8 status[0x8]; 6863 u8 reserved_at_8[0x18]; 6864 6865 u8 syndrome[0x20]; 6866 6867 u8 reserved_at_40[0x8]; 6868 u8 mkey_index[0x18]; 6869 6870 u8 reserved_at_60[0x20]; 6871 }; 6872 6873 struct mlx5_ifc_create_mkey_in_bits { 6874 u8 opcode[0x10]; 6875 u8 reserved_at_10[0x10]; 6876 6877 u8 reserved_at_20[0x10]; 6878 u8 op_mod[0x10]; 6879 6880 u8 reserved_at_40[0x20]; 6881 6882 u8 pg_access[0x1]; 6883 u8 reserved_at_61[0x1f]; 6884 6885 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6886 6887 u8 reserved_at_280[0x80]; 6888 6889 u8 translations_octword_actual_size[0x20]; 6890 6891 u8 reserved_at_320[0x560]; 6892 6893 u8 klm_pas_mtt[0][0x20]; 6894 }; 6895 6896 struct mlx5_ifc_create_flow_table_out_bits { 6897 u8 status[0x8]; 6898 u8 reserved_at_8[0x18]; 6899 6900 u8 syndrome[0x20]; 6901 6902 u8 reserved_at_40[0x8]; 6903 u8 table_id[0x18]; 6904 6905 u8 reserved_at_60[0x20]; 6906 }; 6907 6908 struct mlx5_ifc_flow_table_context_bits { 6909 u8 encap_en[0x1]; 6910 u8 decap_en[0x1]; 6911 u8 reserved_at_2[0x2]; 6912 u8 table_miss_action[0x4]; 6913 u8 level[0x8]; 6914 u8 reserved_at_10[0x8]; 6915 u8 log_size[0x8]; 6916 6917 u8 reserved_at_20[0x8]; 6918 u8 table_miss_id[0x18]; 6919 6920 u8 reserved_at_40[0x8]; 6921 u8 lag_master_next_table_id[0x18]; 6922 6923 u8 reserved_at_60[0xe0]; 6924 }; 6925 6926 struct mlx5_ifc_create_flow_table_in_bits { 6927 u8 opcode[0x10]; 6928 u8 reserved_at_10[0x10]; 6929 6930 u8 reserved_at_20[0x10]; 6931 u8 op_mod[0x10]; 6932 6933 u8 other_vport[0x1]; 6934 u8 reserved_at_41[0xf]; 6935 u8 vport_number[0x10]; 6936 6937 u8 reserved_at_60[0x20]; 6938 6939 u8 table_type[0x8]; 6940 u8 reserved_at_88[0x18]; 6941 6942 u8 reserved_at_a0[0x20]; 6943 6944 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6945 }; 6946 6947 struct mlx5_ifc_create_flow_group_out_bits { 6948 u8 status[0x8]; 6949 u8 reserved_at_8[0x18]; 6950 6951 u8 syndrome[0x20]; 6952 6953 u8 reserved_at_40[0x8]; 6954 u8 group_id[0x18]; 6955 6956 u8 reserved_at_60[0x20]; 6957 }; 6958 6959 enum { 6960 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6961 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6962 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6963 }; 6964 6965 struct mlx5_ifc_create_flow_group_in_bits { 6966 u8 opcode[0x10]; 6967 u8 reserved_at_10[0x10]; 6968 6969 u8 reserved_at_20[0x10]; 6970 u8 op_mod[0x10]; 6971 6972 u8 other_vport[0x1]; 6973 u8 reserved_at_41[0xf]; 6974 u8 vport_number[0x10]; 6975 6976 u8 reserved_at_60[0x20]; 6977 6978 u8 table_type[0x8]; 6979 u8 reserved_at_88[0x18]; 6980 6981 u8 reserved_at_a0[0x8]; 6982 u8 table_id[0x18]; 6983 6984 u8 source_eswitch_owner_vhca_id_valid[0x1]; 6985 6986 u8 reserved_at_c1[0x1f]; 6987 6988 u8 start_flow_index[0x20]; 6989 6990 u8 reserved_at_100[0x20]; 6991 6992 u8 end_flow_index[0x20]; 6993 6994 u8 reserved_at_140[0xa0]; 6995 6996 u8 reserved_at_1e0[0x18]; 6997 u8 match_criteria_enable[0x8]; 6998 6999 struct mlx5_ifc_fte_match_param_bits match_criteria; 7000 7001 u8 reserved_at_1200[0xe00]; 7002 }; 7003 7004 struct mlx5_ifc_create_eq_out_bits { 7005 u8 status[0x8]; 7006 u8 reserved_at_8[0x18]; 7007 7008 u8 syndrome[0x20]; 7009 7010 u8 reserved_at_40[0x18]; 7011 u8 eq_number[0x8]; 7012 7013 u8 reserved_at_60[0x20]; 7014 }; 7015 7016 struct mlx5_ifc_create_eq_in_bits { 7017 u8 opcode[0x10]; 7018 u8 reserved_at_10[0x10]; 7019 7020 u8 reserved_at_20[0x10]; 7021 u8 op_mod[0x10]; 7022 7023 u8 reserved_at_40[0x40]; 7024 7025 struct mlx5_ifc_eqc_bits eq_context_entry; 7026 7027 u8 reserved_at_280[0x40]; 7028 7029 u8 event_bitmask[0x40]; 7030 7031 u8 reserved_at_300[0x580]; 7032 7033 u8 pas[0][0x40]; 7034 }; 7035 7036 struct mlx5_ifc_create_dct_out_bits { 7037 u8 status[0x8]; 7038 u8 reserved_at_8[0x18]; 7039 7040 u8 syndrome[0x20]; 7041 7042 u8 reserved_at_40[0x8]; 7043 u8 dctn[0x18]; 7044 7045 u8 reserved_at_60[0x20]; 7046 }; 7047 7048 struct mlx5_ifc_create_dct_in_bits { 7049 u8 opcode[0x10]; 7050 u8 reserved_at_10[0x10]; 7051 7052 u8 reserved_at_20[0x10]; 7053 u8 op_mod[0x10]; 7054 7055 u8 reserved_at_40[0x40]; 7056 7057 struct mlx5_ifc_dctc_bits dct_context_entry; 7058 7059 u8 reserved_at_280[0x180]; 7060 }; 7061 7062 struct mlx5_ifc_create_cq_out_bits { 7063 u8 status[0x8]; 7064 u8 reserved_at_8[0x18]; 7065 7066 u8 syndrome[0x20]; 7067 7068 u8 reserved_at_40[0x8]; 7069 u8 cqn[0x18]; 7070 7071 u8 reserved_at_60[0x20]; 7072 }; 7073 7074 struct mlx5_ifc_create_cq_in_bits { 7075 u8 opcode[0x10]; 7076 u8 reserved_at_10[0x10]; 7077 7078 u8 reserved_at_20[0x10]; 7079 u8 op_mod[0x10]; 7080 7081 u8 reserved_at_40[0x40]; 7082 7083 struct mlx5_ifc_cqc_bits cq_context; 7084 7085 u8 reserved_at_280[0x600]; 7086 7087 u8 pas[0][0x40]; 7088 }; 7089 7090 struct mlx5_ifc_config_int_moderation_out_bits { 7091 u8 status[0x8]; 7092 u8 reserved_at_8[0x18]; 7093 7094 u8 syndrome[0x20]; 7095 7096 u8 reserved_at_40[0x4]; 7097 u8 min_delay[0xc]; 7098 u8 int_vector[0x10]; 7099 7100 u8 reserved_at_60[0x20]; 7101 }; 7102 7103 enum { 7104 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7105 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7106 }; 7107 7108 struct mlx5_ifc_config_int_moderation_in_bits { 7109 u8 opcode[0x10]; 7110 u8 reserved_at_10[0x10]; 7111 7112 u8 reserved_at_20[0x10]; 7113 u8 op_mod[0x10]; 7114 7115 u8 reserved_at_40[0x4]; 7116 u8 min_delay[0xc]; 7117 u8 int_vector[0x10]; 7118 7119 u8 reserved_at_60[0x20]; 7120 }; 7121 7122 struct mlx5_ifc_attach_to_mcg_out_bits { 7123 u8 status[0x8]; 7124 u8 reserved_at_8[0x18]; 7125 7126 u8 syndrome[0x20]; 7127 7128 u8 reserved_at_40[0x40]; 7129 }; 7130 7131 struct mlx5_ifc_attach_to_mcg_in_bits { 7132 u8 opcode[0x10]; 7133 u8 reserved_at_10[0x10]; 7134 7135 u8 reserved_at_20[0x10]; 7136 u8 op_mod[0x10]; 7137 7138 u8 reserved_at_40[0x8]; 7139 u8 qpn[0x18]; 7140 7141 u8 reserved_at_60[0x20]; 7142 7143 u8 multicast_gid[16][0x8]; 7144 }; 7145 7146 struct mlx5_ifc_arm_xrq_out_bits { 7147 u8 status[0x8]; 7148 u8 reserved_at_8[0x18]; 7149 7150 u8 syndrome[0x20]; 7151 7152 u8 reserved_at_40[0x40]; 7153 }; 7154 7155 struct mlx5_ifc_arm_xrq_in_bits { 7156 u8 opcode[0x10]; 7157 u8 reserved_at_10[0x10]; 7158 7159 u8 reserved_at_20[0x10]; 7160 u8 op_mod[0x10]; 7161 7162 u8 reserved_at_40[0x8]; 7163 u8 xrqn[0x18]; 7164 7165 u8 reserved_at_60[0x10]; 7166 u8 lwm[0x10]; 7167 }; 7168 7169 struct mlx5_ifc_arm_xrc_srq_out_bits { 7170 u8 status[0x8]; 7171 u8 reserved_at_8[0x18]; 7172 7173 u8 syndrome[0x20]; 7174 7175 u8 reserved_at_40[0x40]; 7176 }; 7177 7178 enum { 7179 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7180 }; 7181 7182 struct mlx5_ifc_arm_xrc_srq_in_bits { 7183 u8 opcode[0x10]; 7184 u8 reserved_at_10[0x10]; 7185 7186 u8 reserved_at_20[0x10]; 7187 u8 op_mod[0x10]; 7188 7189 u8 reserved_at_40[0x8]; 7190 u8 xrc_srqn[0x18]; 7191 7192 u8 reserved_at_60[0x10]; 7193 u8 lwm[0x10]; 7194 }; 7195 7196 struct mlx5_ifc_arm_rq_out_bits { 7197 u8 status[0x8]; 7198 u8 reserved_at_8[0x18]; 7199 7200 u8 syndrome[0x20]; 7201 7202 u8 reserved_at_40[0x40]; 7203 }; 7204 7205 enum { 7206 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7207 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7208 }; 7209 7210 struct mlx5_ifc_arm_rq_in_bits { 7211 u8 opcode[0x10]; 7212 u8 reserved_at_10[0x10]; 7213 7214 u8 reserved_at_20[0x10]; 7215 u8 op_mod[0x10]; 7216 7217 u8 reserved_at_40[0x8]; 7218 u8 srq_number[0x18]; 7219 7220 u8 reserved_at_60[0x10]; 7221 u8 lwm[0x10]; 7222 }; 7223 7224 struct mlx5_ifc_arm_dct_out_bits { 7225 u8 status[0x8]; 7226 u8 reserved_at_8[0x18]; 7227 7228 u8 syndrome[0x20]; 7229 7230 u8 reserved_at_40[0x40]; 7231 }; 7232 7233 struct mlx5_ifc_arm_dct_in_bits { 7234 u8 opcode[0x10]; 7235 u8 reserved_at_10[0x10]; 7236 7237 u8 reserved_at_20[0x10]; 7238 u8 op_mod[0x10]; 7239 7240 u8 reserved_at_40[0x8]; 7241 u8 dct_number[0x18]; 7242 7243 u8 reserved_at_60[0x20]; 7244 }; 7245 7246 struct mlx5_ifc_alloc_xrcd_out_bits { 7247 u8 status[0x8]; 7248 u8 reserved_at_8[0x18]; 7249 7250 u8 syndrome[0x20]; 7251 7252 u8 reserved_at_40[0x8]; 7253 u8 xrcd[0x18]; 7254 7255 u8 reserved_at_60[0x20]; 7256 }; 7257 7258 struct mlx5_ifc_alloc_xrcd_in_bits { 7259 u8 opcode[0x10]; 7260 u8 reserved_at_10[0x10]; 7261 7262 u8 reserved_at_20[0x10]; 7263 u8 op_mod[0x10]; 7264 7265 u8 reserved_at_40[0x40]; 7266 }; 7267 7268 struct mlx5_ifc_alloc_uar_out_bits { 7269 u8 status[0x8]; 7270 u8 reserved_at_8[0x18]; 7271 7272 u8 syndrome[0x20]; 7273 7274 u8 reserved_at_40[0x8]; 7275 u8 uar[0x18]; 7276 7277 u8 reserved_at_60[0x20]; 7278 }; 7279 7280 struct mlx5_ifc_alloc_uar_in_bits { 7281 u8 opcode[0x10]; 7282 u8 reserved_at_10[0x10]; 7283 7284 u8 reserved_at_20[0x10]; 7285 u8 op_mod[0x10]; 7286 7287 u8 reserved_at_40[0x40]; 7288 }; 7289 7290 struct mlx5_ifc_alloc_transport_domain_out_bits { 7291 u8 status[0x8]; 7292 u8 reserved_at_8[0x18]; 7293 7294 u8 syndrome[0x20]; 7295 7296 u8 reserved_at_40[0x8]; 7297 u8 transport_domain[0x18]; 7298 7299 u8 reserved_at_60[0x20]; 7300 }; 7301 7302 struct mlx5_ifc_alloc_transport_domain_in_bits { 7303 u8 opcode[0x10]; 7304 u8 reserved_at_10[0x10]; 7305 7306 u8 reserved_at_20[0x10]; 7307 u8 op_mod[0x10]; 7308 7309 u8 reserved_at_40[0x40]; 7310 }; 7311 7312 struct mlx5_ifc_alloc_q_counter_out_bits { 7313 u8 status[0x8]; 7314 u8 reserved_at_8[0x18]; 7315 7316 u8 syndrome[0x20]; 7317 7318 u8 reserved_at_40[0x18]; 7319 u8 counter_set_id[0x8]; 7320 7321 u8 reserved_at_60[0x20]; 7322 }; 7323 7324 struct mlx5_ifc_alloc_q_counter_in_bits { 7325 u8 opcode[0x10]; 7326 u8 reserved_at_10[0x10]; 7327 7328 u8 reserved_at_20[0x10]; 7329 u8 op_mod[0x10]; 7330 7331 u8 reserved_at_40[0x40]; 7332 }; 7333 7334 struct mlx5_ifc_alloc_pd_out_bits { 7335 u8 status[0x8]; 7336 u8 reserved_at_8[0x18]; 7337 7338 u8 syndrome[0x20]; 7339 7340 u8 reserved_at_40[0x8]; 7341 u8 pd[0x18]; 7342 7343 u8 reserved_at_60[0x20]; 7344 }; 7345 7346 struct mlx5_ifc_alloc_pd_in_bits { 7347 u8 opcode[0x10]; 7348 u8 reserved_at_10[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 reserved_at_40[0x40]; 7354 }; 7355 7356 struct mlx5_ifc_alloc_flow_counter_out_bits { 7357 u8 status[0x8]; 7358 u8 reserved_at_8[0x18]; 7359 7360 u8 syndrome[0x20]; 7361 7362 u8 flow_counter_id[0x20]; 7363 7364 u8 reserved_at_60[0x20]; 7365 }; 7366 7367 struct mlx5_ifc_alloc_flow_counter_in_bits { 7368 u8 opcode[0x10]; 7369 u8 reserved_at_10[0x10]; 7370 7371 u8 reserved_at_20[0x10]; 7372 u8 op_mod[0x10]; 7373 7374 u8 reserved_at_40[0x40]; 7375 }; 7376 7377 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7378 u8 status[0x8]; 7379 u8 reserved_at_8[0x18]; 7380 7381 u8 syndrome[0x20]; 7382 7383 u8 reserved_at_40[0x40]; 7384 }; 7385 7386 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7387 u8 opcode[0x10]; 7388 u8 reserved_at_10[0x10]; 7389 7390 u8 reserved_at_20[0x10]; 7391 u8 op_mod[0x10]; 7392 7393 u8 reserved_at_40[0x20]; 7394 7395 u8 reserved_at_60[0x10]; 7396 u8 vxlan_udp_port[0x10]; 7397 }; 7398 7399 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7400 u8 status[0x8]; 7401 u8 reserved_at_8[0x18]; 7402 7403 u8 syndrome[0x20]; 7404 7405 u8 reserved_at_40[0x40]; 7406 }; 7407 7408 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7409 u8 opcode[0x10]; 7410 u8 reserved_at_10[0x10]; 7411 7412 u8 reserved_at_20[0x10]; 7413 u8 op_mod[0x10]; 7414 7415 u8 reserved_at_40[0x10]; 7416 u8 rate_limit_index[0x10]; 7417 7418 u8 reserved_at_60[0x20]; 7419 7420 u8 rate_limit[0x20]; 7421 7422 u8 burst_upper_bound[0x20]; 7423 7424 u8 reserved_at_c0[0x10]; 7425 u8 typical_packet_size[0x10]; 7426 7427 u8 reserved_at_e0[0x120]; 7428 }; 7429 7430 struct mlx5_ifc_access_register_out_bits { 7431 u8 status[0x8]; 7432 u8 reserved_at_8[0x18]; 7433 7434 u8 syndrome[0x20]; 7435 7436 u8 reserved_at_40[0x40]; 7437 7438 u8 register_data[0][0x20]; 7439 }; 7440 7441 enum { 7442 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7443 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7444 }; 7445 7446 struct mlx5_ifc_access_register_in_bits { 7447 u8 opcode[0x10]; 7448 u8 reserved_at_10[0x10]; 7449 7450 u8 reserved_at_20[0x10]; 7451 u8 op_mod[0x10]; 7452 7453 u8 reserved_at_40[0x10]; 7454 u8 register_id[0x10]; 7455 7456 u8 argument[0x20]; 7457 7458 u8 register_data[0][0x20]; 7459 }; 7460 7461 struct mlx5_ifc_sltp_reg_bits { 7462 u8 status[0x4]; 7463 u8 version[0x4]; 7464 u8 local_port[0x8]; 7465 u8 pnat[0x2]; 7466 u8 reserved_at_12[0x2]; 7467 u8 lane[0x4]; 7468 u8 reserved_at_18[0x8]; 7469 7470 u8 reserved_at_20[0x20]; 7471 7472 u8 reserved_at_40[0x7]; 7473 u8 polarity[0x1]; 7474 u8 ob_tap0[0x8]; 7475 u8 ob_tap1[0x8]; 7476 u8 ob_tap2[0x8]; 7477 7478 u8 reserved_at_60[0xc]; 7479 u8 ob_preemp_mode[0x4]; 7480 u8 ob_reg[0x8]; 7481 u8 ob_bias[0x8]; 7482 7483 u8 reserved_at_80[0x20]; 7484 }; 7485 7486 struct mlx5_ifc_slrg_reg_bits { 7487 u8 status[0x4]; 7488 u8 version[0x4]; 7489 u8 local_port[0x8]; 7490 u8 pnat[0x2]; 7491 u8 reserved_at_12[0x2]; 7492 u8 lane[0x4]; 7493 u8 reserved_at_18[0x8]; 7494 7495 u8 time_to_link_up[0x10]; 7496 u8 reserved_at_30[0xc]; 7497 u8 grade_lane_speed[0x4]; 7498 7499 u8 grade_version[0x8]; 7500 u8 grade[0x18]; 7501 7502 u8 reserved_at_60[0x4]; 7503 u8 height_grade_type[0x4]; 7504 u8 height_grade[0x18]; 7505 7506 u8 height_dz[0x10]; 7507 u8 height_dv[0x10]; 7508 7509 u8 reserved_at_a0[0x10]; 7510 u8 height_sigma[0x10]; 7511 7512 u8 reserved_at_c0[0x20]; 7513 7514 u8 reserved_at_e0[0x4]; 7515 u8 phase_grade_type[0x4]; 7516 u8 phase_grade[0x18]; 7517 7518 u8 reserved_at_100[0x8]; 7519 u8 phase_eo_pos[0x8]; 7520 u8 reserved_at_110[0x8]; 7521 u8 phase_eo_neg[0x8]; 7522 7523 u8 ffe_set_tested[0x10]; 7524 u8 test_errors_per_lane[0x10]; 7525 }; 7526 7527 struct mlx5_ifc_pvlc_reg_bits { 7528 u8 reserved_at_0[0x8]; 7529 u8 local_port[0x8]; 7530 u8 reserved_at_10[0x10]; 7531 7532 u8 reserved_at_20[0x1c]; 7533 u8 vl_hw_cap[0x4]; 7534 7535 u8 reserved_at_40[0x1c]; 7536 u8 vl_admin[0x4]; 7537 7538 u8 reserved_at_60[0x1c]; 7539 u8 vl_operational[0x4]; 7540 }; 7541 7542 struct mlx5_ifc_pude_reg_bits { 7543 u8 swid[0x8]; 7544 u8 local_port[0x8]; 7545 u8 reserved_at_10[0x4]; 7546 u8 admin_status[0x4]; 7547 u8 reserved_at_18[0x4]; 7548 u8 oper_status[0x4]; 7549 7550 u8 reserved_at_20[0x60]; 7551 }; 7552 7553 struct mlx5_ifc_ptys_reg_bits { 7554 u8 reserved_at_0[0x1]; 7555 u8 an_disable_admin[0x1]; 7556 u8 an_disable_cap[0x1]; 7557 u8 reserved_at_3[0x5]; 7558 u8 local_port[0x8]; 7559 u8 reserved_at_10[0xd]; 7560 u8 proto_mask[0x3]; 7561 7562 u8 an_status[0x4]; 7563 u8 reserved_at_24[0x3c]; 7564 7565 u8 eth_proto_capability[0x20]; 7566 7567 u8 ib_link_width_capability[0x10]; 7568 u8 ib_proto_capability[0x10]; 7569 7570 u8 reserved_at_a0[0x20]; 7571 7572 u8 eth_proto_admin[0x20]; 7573 7574 u8 ib_link_width_admin[0x10]; 7575 u8 ib_proto_admin[0x10]; 7576 7577 u8 reserved_at_100[0x20]; 7578 7579 u8 eth_proto_oper[0x20]; 7580 7581 u8 ib_link_width_oper[0x10]; 7582 u8 ib_proto_oper[0x10]; 7583 7584 u8 reserved_at_160[0x1c]; 7585 u8 connector_type[0x4]; 7586 7587 u8 eth_proto_lp_advertise[0x20]; 7588 7589 u8 reserved_at_1a0[0x60]; 7590 }; 7591 7592 struct mlx5_ifc_mlcr_reg_bits { 7593 u8 reserved_at_0[0x8]; 7594 u8 local_port[0x8]; 7595 u8 reserved_at_10[0x20]; 7596 7597 u8 beacon_duration[0x10]; 7598 u8 reserved_at_40[0x10]; 7599 7600 u8 beacon_remain[0x10]; 7601 }; 7602 7603 struct mlx5_ifc_ptas_reg_bits { 7604 u8 reserved_at_0[0x20]; 7605 7606 u8 algorithm_options[0x10]; 7607 u8 reserved_at_30[0x4]; 7608 u8 repetitions_mode[0x4]; 7609 u8 num_of_repetitions[0x8]; 7610 7611 u8 grade_version[0x8]; 7612 u8 height_grade_type[0x4]; 7613 u8 phase_grade_type[0x4]; 7614 u8 height_grade_weight[0x8]; 7615 u8 phase_grade_weight[0x8]; 7616 7617 u8 gisim_measure_bits[0x10]; 7618 u8 adaptive_tap_measure_bits[0x10]; 7619 7620 u8 ber_bath_high_error_threshold[0x10]; 7621 u8 ber_bath_mid_error_threshold[0x10]; 7622 7623 u8 ber_bath_low_error_threshold[0x10]; 7624 u8 one_ratio_high_threshold[0x10]; 7625 7626 u8 one_ratio_high_mid_threshold[0x10]; 7627 u8 one_ratio_low_mid_threshold[0x10]; 7628 7629 u8 one_ratio_low_threshold[0x10]; 7630 u8 ndeo_error_threshold[0x10]; 7631 7632 u8 mixer_offset_step_size[0x10]; 7633 u8 reserved_at_110[0x8]; 7634 u8 mix90_phase_for_voltage_bath[0x8]; 7635 7636 u8 mixer_offset_start[0x10]; 7637 u8 mixer_offset_end[0x10]; 7638 7639 u8 reserved_at_140[0x15]; 7640 u8 ber_test_time[0xb]; 7641 }; 7642 7643 struct mlx5_ifc_pspa_reg_bits { 7644 u8 swid[0x8]; 7645 u8 local_port[0x8]; 7646 u8 sub_port[0x8]; 7647 u8 reserved_at_18[0x8]; 7648 7649 u8 reserved_at_20[0x20]; 7650 }; 7651 7652 struct mlx5_ifc_pqdr_reg_bits { 7653 u8 reserved_at_0[0x8]; 7654 u8 local_port[0x8]; 7655 u8 reserved_at_10[0x5]; 7656 u8 prio[0x3]; 7657 u8 reserved_at_18[0x6]; 7658 u8 mode[0x2]; 7659 7660 u8 reserved_at_20[0x20]; 7661 7662 u8 reserved_at_40[0x10]; 7663 u8 min_threshold[0x10]; 7664 7665 u8 reserved_at_60[0x10]; 7666 u8 max_threshold[0x10]; 7667 7668 u8 reserved_at_80[0x10]; 7669 u8 mark_probability_denominator[0x10]; 7670 7671 u8 reserved_at_a0[0x60]; 7672 }; 7673 7674 struct mlx5_ifc_ppsc_reg_bits { 7675 u8 reserved_at_0[0x8]; 7676 u8 local_port[0x8]; 7677 u8 reserved_at_10[0x10]; 7678 7679 u8 reserved_at_20[0x60]; 7680 7681 u8 reserved_at_80[0x1c]; 7682 u8 wrps_admin[0x4]; 7683 7684 u8 reserved_at_a0[0x1c]; 7685 u8 wrps_status[0x4]; 7686 7687 u8 reserved_at_c0[0x8]; 7688 u8 up_threshold[0x8]; 7689 u8 reserved_at_d0[0x8]; 7690 u8 down_threshold[0x8]; 7691 7692 u8 reserved_at_e0[0x20]; 7693 7694 u8 reserved_at_100[0x1c]; 7695 u8 srps_admin[0x4]; 7696 7697 u8 reserved_at_120[0x1c]; 7698 u8 srps_status[0x4]; 7699 7700 u8 reserved_at_140[0x40]; 7701 }; 7702 7703 struct mlx5_ifc_pplr_reg_bits { 7704 u8 reserved_at_0[0x8]; 7705 u8 local_port[0x8]; 7706 u8 reserved_at_10[0x10]; 7707 7708 u8 reserved_at_20[0x8]; 7709 u8 lb_cap[0x8]; 7710 u8 reserved_at_30[0x8]; 7711 u8 lb_en[0x8]; 7712 }; 7713 7714 struct mlx5_ifc_pplm_reg_bits { 7715 u8 reserved_at_0[0x8]; 7716 u8 local_port[0x8]; 7717 u8 reserved_at_10[0x10]; 7718 7719 u8 reserved_at_20[0x20]; 7720 7721 u8 port_profile_mode[0x8]; 7722 u8 static_port_profile[0x8]; 7723 u8 active_port_profile[0x8]; 7724 u8 reserved_at_58[0x8]; 7725 7726 u8 retransmission_active[0x8]; 7727 u8 fec_mode_active[0x18]; 7728 7729 u8 reserved_at_80[0x20]; 7730 }; 7731 7732 struct mlx5_ifc_ppcnt_reg_bits { 7733 u8 swid[0x8]; 7734 u8 local_port[0x8]; 7735 u8 pnat[0x2]; 7736 u8 reserved_at_12[0x8]; 7737 u8 grp[0x6]; 7738 7739 u8 clr[0x1]; 7740 u8 reserved_at_21[0x1c]; 7741 u8 prio_tc[0x3]; 7742 7743 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7744 }; 7745 7746 struct mlx5_ifc_mpcnt_reg_bits { 7747 u8 reserved_at_0[0x8]; 7748 u8 pcie_index[0x8]; 7749 u8 reserved_at_10[0xa]; 7750 u8 grp[0x6]; 7751 7752 u8 clr[0x1]; 7753 u8 reserved_at_21[0x1f]; 7754 7755 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7756 }; 7757 7758 struct mlx5_ifc_ppad_reg_bits { 7759 u8 reserved_at_0[0x3]; 7760 u8 single_mac[0x1]; 7761 u8 reserved_at_4[0x4]; 7762 u8 local_port[0x8]; 7763 u8 mac_47_32[0x10]; 7764 7765 u8 mac_31_0[0x20]; 7766 7767 u8 reserved_at_40[0x40]; 7768 }; 7769 7770 struct mlx5_ifc_pmtu_reg_bits { 7771 u8 reserved_at_0[0x8]; 7772 u8 local_port[0x8]; 7773 u8 reserved_at_10[0x10]; 7774 7775 u8 max_mtu[0x10]; 7776 u8 reserved_at_30[0x10]; 7777 7778 u8 admin_mtu[0x10]; 7779 u8 reserved_at_50[0x10]; 7780 7781 u8 oper_mtu[0x10]; 7782 u8 reserved_at_70[0x10]; 7783 }; 7784 7785 struct mlx5_ifc_pmpr_reg_bits { 7786 u8 reserved_at_0[0x8]; 7787 u8 module[0x8]; 7788 u8 reserved_at_10[0x10]; 7789 7790 u8 reserved_at_20[0x18]; 7791 u8 attenuation_5g[0x8]; 7792 7793 u8 reserved_at_40[0x18]; 7794 u8 attenuation_7g[0x8]; 7795 7796 u8 reserved_at_60[0x18]; 7797 u8 attenuation_12g[0x8]; 7798 }; 7799 7800 struct mlx5_ifc_pmpe_reg_bits { 7801 u8 reserved_at_0[0x8]; 7802 u8 module[0x8]; 7803 u8 reserved_at_10[0xc]; 7804 u8 module_status[0x4]; 7805 7806 u8 reserved_at_20[0x60]; 7807 }; 7808 7809 struct mlx5_ifc_pmpc_reg_bits { 7810 u8 module_state_updated[32][0x8]; 7811 }; 7812 7813 struct mlx5_ifc_pmlpn_reg_bits { 7814 u8 reserved_at_0[0x4]; 7815 u8 mlpn_status[0x4]; 7816 u8 local_port[0x8]; 7817 u8 reserved_at_10[0x10]; 7818 7819 u8 e[0x1]; 7820 u8 reserved_at_21[0x1f]; 7821 }; 7822 7823 struct mlx5_ifc_pmlp_reg_bits { 7824 u8 rxtx[0x1]; 7825 u8 reserved_at_1[0x7]; 7826 u8 local_port[0x8]; 7827 u8 reserved_at_10[0x8]; 7828 u8 width[0x8]; 7829 7830 u8 lane0_module_mapping[0x20]; 7831 7832 u8 lane1_module_mapping[0x20]; 7833 7834 u8 lane2_module_mapping[0x20]; 7835 7836 u8 lane3_module_mapping[0x20]; 7837 7838 u8 reserved_at_a0[0x160]; 7839 }; 7840 7841 struct mlx5_ifc_pmaos_reg_bits { 7842 u8 reserved_at_0[0x8]; 7843 u8 module[0x8]; 7844 u8 reserved_at_10[0x4]; 7845 u8 admin_status[0x4]; 7846 u8 reserved_at_18[0x4]; 7847 u8 oper_status[0x4]; 7848 7849 u8 ase[0x1]; 7850 u8 ee[0x1]; 7851 u8 reserved_at_22[0x1c]; 7852 u8 e[0x2]; 7853 7854 u8 reserved_at_40[0x40]; 7855 }; 7856 7857 struct mlx5_ifc_plpc_reg_bits { 7858 u8 reserved_at_0[0x4]; 7859 u8 profile_id[0xc]; 7860 u8 reserved_at_10[0x4]; 7861 u8 proto_mask[0x4]; 7862 u8 reserved_at_18[0x8]; 7863 7864 u8 reserved_at_20[0x10]; 7865 u8 lane_speed[0x10]; 7866 7867 u8 reserved_at_40[0x17]; 7868 u8 lpbf[0x1]; 7869 u8 fec_mode_policy[0x8]; 7870 7871 u8 retransmission_capability[0x8]; 7872 u8 fec_mode_capability[0x18]; 7873 7874 u8 retransmission_support_admin[0x8]; 7875 u8 fec_mode_support_admin[0x18]; 7876 7877 u8 retransmission_request_admin[0x8]; 7878 u8 fec_mode_request_admin[0x18]; 7879 7880 u8 reserved_at_c0[0x80]; 7881 }; 7882 7883 struct mlx5_ifc_plib_reg_bits { 7884 u8 reserved_at_0[0x8]; 7885 u8 local_port[0x8]; 7886 u8 reserved_at_10[0x8]; 7887 u8 ib_port[0x8]; 7888 7889 u8 reserved_at_20[0x60]; 7890 }; 7891 7892 struct mlx5_ifc_plbf_reg_bits { 7893 u8 reserved_at_0[0x8]; 7894 u8 local_port[0x8]; 7895 u8 reserved_at_10[0xd]; 7896 u8 lbf_mode[0x3]; 7897 7898 u8 reserved_at_20[0x20]; 7899 }; 7900 7901 struct mlx5_ifc_pipg_reg_bits { 7902 u8 reserved_at_0[0x8]; 7903 u8 local_port[0x8]; 7904 u8 reserved_at_10[0x10]; 7905 7906 u8 dic[0x1]; 7907 u8 reserved_at_21[0x19]; 7908 u8 ipg[0x4]; 7909 u8 reserved_at_3e[0x2]; 7910 }; 7911 7912 struct mlx5_ifc_pifr_reg_bits { 7913 u8 reserved_at_0[0x8]; 7914 u8 local_port[0x8]; 7915 u8 reserved_at_10[0x10]; 7916 7917 u8 reserved_at_20[0xe0]; 7918 7919 u8 port_filter[8][0x20]; 7920 7921 u8 port_filter_update_en[8][0x20]; 7922 }; 7923 7924 struct mlx5_ifc_pfcc_reg_bits { 7925 u8 reserved_at_0[0x8]; 7926 u8 local_port[0x8]; 7927 u8 reserved_at_10[0xb]; 7928 u8 ppan_mask_n[0x1]; 7929 u8 minor_stall_mask[0x1]; 7930 u8 critical_stall_mask[0x1]; 7931 u8 reserved_at_1e[0x2]; 7932 7933 u8 ppan[0x4]; 7934 u8 reserved_at_24[0x4]; 7935 u8 prio_mask_tx[0x8]; 7936 u8 reserved_at_30[0x8]; 7937 u8 prio_mask_rx[0x8]; 7938 7939 u8 pptx[0x1]; 7940 u8 aptx[0x1]; 7941 u8 pptx_mask_n[0x1]; 7942 u8 reserved_at_43[0x5]; 7943 u8 pfctx[0x8]; 7944 u8 reserved_at_50[0x10]; 7945 7946 u8 pprx[0x1]; 7947 u8 aprx[0x1]; 7948 u8 pprx_mask_n[0x1]; 7949 u8 reserved_at_63[0x5]; 7950 u8 pfcrx[0x8]; 7951 u8 reserved_at_70[0x10]; 7952 7953 u8 device_stall_minor_watermark[0x10]; 7954 u8 device_stall_critical_watermark[0x10]; 7955 7956 u8 reserved_at_a0[0x60]; 7957 }; 7958 7959 struct mlx5_ifc_pelc_reg_bits { 7960 u8 op[0x4]; 7961 u8 reserved_at_4[0x4]; 7962 u8 local_port[0x8]; 7963 u8 reserved_at_10[0x10]; 7964 7965 u8 op_admin[0x8]; 7966 u8 op_capability[0x8]; 7967 u8 op_request[0x8]; 7968 u8 op_active[0x8]; 7969 7970 u8 admin[0x40]; 7971 7972 u8 capability[0x40]; 7973 7974 u8 request[0x40]; 7975 7976 u8 active[0x40]; 7977 7978 u8 reserved_at_140[0x80]; 7979 }; 7980 7981 struct mlx5_ifc_peir_reg_bits { 7982 u8 reserved_at_0[0x8]; 7983 u8 local_port[0x8]; 7984 u8 reserved_at_10[0x10]; 7985 7986 u8 reserved_at_20[0xc]; 7987 u8 error_count[0x4]; 7988 u8 reserved_at_30[0x10]; 7989 7990 u8 reserved_at_40[0xc]; 7991 u8 lane[0x4]; 7992 u8 reserved_at_50[0x8]; 7993 u8 error_type[0x8]; 7994 }; 7995 7996 struct mlx5_ifc_pcam_enhanced_features_bits { 7997 u8 reserved_at_0[0x76]; 7998 7999 u8 pfcc_mask[0x1]; 8000 u8 reserved_at_77[0x4]; 8001 u8 rx_buffer_fullness_counters[0x1]; 8002 u8 ptys_connector_type[0x1]; 8003 u8 reserved_at_7d[0x1]; 8004 u8 ppcnt_discard_group[0x1]; 8005 u8 ppcnt_statistical_group[0x1]; 8006 }; 8007 8008 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8009 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8010 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8011 u8 port_access_reg_cap_mask_63_to_32[0x20]; 8012 8013 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8014 u8 pbmc[0x1]; 8015 u8 pptb[0x1]; 8016 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8017 }; 8018 8019 struct mlx5_ifc_pcam_reg_bits { 8020 u8 reserved_at_0[0x8]; 8021 u8 feature_group[0x8]; 8022 u8 reserved_at_10[0x8]; 8023 u8 access_reg_group[0x8]; 8024 8025 u8 reserved_at_20[0x20]; 8026 8027 union { 8028 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8029 u8 reserved_at_0[0x80]; 8030 } port_access_reg_cap_mask; 8031 8032 u8 reserved_at_c0[0x80]; 8033 8034 union { 8035 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8036 u8 reserved_at_0[0x80]; 8037 } feature_cap_mask; 8038 8039 u8 reserved_at_1c0[0xc0]; 8040 }; 8041 8042 struct mlx5_ifc_mcam_enhanced_features_bits { 8043 u8 reserved_at_0[0x7b]; 8044 u8 pcie_outbound_stalled[0x1]; 8045 u8 tx_overflow_buffer_pkt[0x1]; 8046 u8 mtpps_enh_out_per_adj[0x1]; 8047 u8 mtpps_fs[0x1]; 8048 u8 pcie_performance_group[0x1]; 8049 }; 8050 8051 struct mlx5_ifc_mcam_access_reg_bits { 8052 u8 reserved_at_0[0x1c]; 8053 u8 mcda[0x1]; 8054 u8 mcc[0x1]; 8055 u8 mcqi[0x1]; 8056 u8 reserved_at_1f[0x1]; 8057 8058 u8 regs_95_to_64[0x20]; 8059 u8 regs_63_to_32[0x20]; 8060 u8 regs_31_to_0[0x20]; 8061 }; 8062 8063 struct mlx5_ifc_mcam_reg_bits { 8064 u8 reserved_at_0[0x8]; 8065 u8 feature_group[0x8]; 8066 u8 reserved_at_10[0x8]; 8067 u8 access_reg_group[0x8]; 8068 8069 u8 reserved_at_20[0x20]; 8070 8071 union { 8072 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8073 u8 reserved_at_0[0x80]; 8074 } mng_access_reg_cap_mask; 8075 8076 u8 reserved_at_c0[0x80]; 8077 8078 union { 8079 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8080 u8 reserved_at_0[0x80]; 8081 } mng_feature_cap_mask; 8082 8083 u8 reserved_at_1c0[0x80]; 8084 }; 8085 8086 struct mlx5_ifc_qcam_access_reg_cap_mask { 8087 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8088 u8 qpdpm[0x1]; 8089 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8090 u8 qdpm[0x1]; 8091 u8 qpts[0x1]; 8092 u8 qcap[0x1]; 8093 u8 qcam_access_reg_cap_mask_0[0x1]; 8094 }; 8095 8096 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8097 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8098 u8 qpts_trust_both[0x1]; 8099 }; 8100 8101 struct mlx5_ifc_qcam_reg_bits { 8102 u8 reserved_at_0[0x8]; 8103 u8 feature_group[0x8]; 8104 u8 reserved_at_10[0x8]; 8105 u8 access_reg_group[0x8]; 8106 u8 reserved_at_20[0x20]; 8107 8108 union { 8109 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8110 u8 reserved_at_0[0x80]; 8111 } qos_access_reg_cap_mask; 8112 8113 u8 reserved_at_c0[0x80]; 8114 8115 union { 8116 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8117 u8 reserved_at_0[0x80]; 8118 } qos_feature_cap_mask; 8119 8120 u8 reserved_at_1c0[0x80]; 8121 }; 8122 8123 struct mlx5_ifc_pcap_reg_bits { 8124 u8 reserved_at_0[0x8]; 8125 u8 local_port[0x8]; 8126 u8 reserved_at_10[0x10]; 8127 8128 u8 port_capability_mask[4][0x20]; 8129 }; 8130 8131 struct mlx5_ifc_paos_reg_bits { 8132 u8 swid[0x8]; 8133 u8 local_port[0x8]; 8134 u8 reserved_at_10[0x4]; 8135 u8 admin_status[0x4]; 8136 u8 reserved_at_18[0x4]; 8137 u8 oper_status[0x4]; 8138 8139 u8 ase[0x1]; 8140 u8 ee[0x1]; 8141 u8 reserved_at_22[0x1c]; 8142 u8 e[0x2]; 8143 8144 u8 reserved_at_40[0x40]; 8145 }; 8146 8147 struct mlx5_ifc_pamp_reg_bits { 8148 u8 reserved_at_0[0x8]; 8149 u8 opamp_group[0x8]; 8150 u8 reserved_at_10[0xc]; 8151 u8 opamp_group_type[0x4]; 8152 8153 u8 start_index[0x10]; 8154 u8 reserved_at_30[0x4]; 8155 u8 num_of_indices[0xc]; 8156 8157 u8 index_data[18][0x10]; 8158 }; 8159 8160 struct mlx5_ifc_pcmr_reg_bits { 8161 u8 reserved_at_0[0x8]; 8162 u8 local_port[0x8]; 8163 u8 reserved_at_10[0x2e]; 8164 u8 fcs_cap[0x1]; 8165 u8 reserved_at_3f[0x1f]; 8166 u8 fcs_chk[0x1]; 8167 u8 reserved_at_5f[0x1]; 8168 }; 8169 8170 struct mlx5_ifc_lane_2_module_mapping_bits { 8171 u8 reserved_at_0[0x6]; 8172 u8 rx_lane[0x2]; 8173 u8 reserved_at_8[0x6]; 8174 u8 tx_lane[0x2]; 8175 u8 reserved_at_10[0x8]; 8176 u8 module[0x8]; 8177 }; 8178 8179 struct mlx5_ifc_bufferx_reg_bits { 8180 u8 reserved_at_0[0x6]; 8181 u8 lossy[0x1]; 8182 u8 epsb[0x1]; 8183 u8 reserved_at_8[0xc]; 8184 u8 size[0xc]; 8185 8186 u8 xoff_threshold[0x10]; 8187 u8 xon_threshold[0x10]; 8188 }; 8189 8190 struct mlx5_ifc_set_node_in_bits { 8191 u8 node_description[64][0x8]; 8192 }; 8193 8194 struct mlx5_ifc_register_power_settings_bits { 8195 u8 reserved_at_0[0x18]; 8196 u8 power_settings_level[0x8]; 8197 8198 u8 reserved_at_20[0x60]; 8199 }; 8200 8201 struct mlx5_ifc_register_host_endianness_bits { 8202 u8 he[0x1]; 8203 u8 reserved_at_1[0x1f]; 8204 8205 u8 reserved_at_20[0x60]; 8206 }; 8207 8208 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8209 u8 reserved_at_0[0x20]; 8210 8211 u8 mkey[0x20]; 8212 8213 u8 addressh_63_32[0x20]; 8214 8215 u8 addressl_31_0[0x20]; 8216 }; 8217 8218 struct mlx5_ifc_ud_adrs_vector_bits { 8219 u8 dc_key[0x40]; 8220 8221 u8 ext[0x1]; 8222 u8 reserved_at_41[0x7]; 8223 u8 destination_qp_dct[0x18]; 8224 8225 u8 static_rate[0x4]; 8226 u8 sl_eth_prio[0x4]; 8227 u8 fl[0x1]; 8228 u8 mlid[0x7]; 8229 u8 rlid_udp_sport[0x10]; 8230 8231 u8 reserved_at_80[0x20]; 8232 8233 u8 rmac_47_16[0x20]; 8234 8235 u8 rmac_15_0[0x10]; 8236 u8 tclass[0x8]; 8237 u8 hop_limit[0x8]; 8238 8239 u8 reserved_at_e0[0x1]; 8240 u8 grh[0x1]; 8241 u8 reserved_at_e2[0x2]; 8242 u8 src_addr_index[0x8]; 8243 u8 flow_label[0x14]; 8244 8245 u8 rgid_rip[16][0x8]; 8246 }; 8247 8248 struct mlx5_ifc_pages_req_event_bits { 8249 u8 reserved_at_0[0x10]; 8250 u8 function_id[0x10]; 8251 8252 u8 num_pages[0x20]; 8253 8254 u8 reserved_at_40[0xa0]; 8255 }; 8256 8257 struct mlx5_ifc_eqe_bits { 8258 u8 reserved_at_0[0x8]; 8259 u8 event_type[0x8]; 8260 u8 reserved_at_10[0x8]; 8261 u8 event_sub_type[0x8]; 8262 8263 u8 reserved_at_20[0xe0]; 8264 8265 union mlx5_ifc_event_auto_bits event_data; 8266 8267 u8 reserved_at_1e0[0x10]; 8268 u8 signature[0x8]; 8269 u8 reserved_at_1f8[0x7]; 8270 u8 owner[0x1]; 8271 }; 8272 8273 enum { 8274 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8275 }; 8276 8277 struct mlx5_ifc_cmd_queue_entry_bits { 8278 u8 type[0x8]; 8279 u8 reserved_at_8[0x18]; 8280 8281 u8 input_length[0x20]; 8282 8283 u8 input_mailbox_pointer_63_32[0x20]; 8284 8285 u8 input_mailbox_pointer_31_9[0x17]; 8286 u8 reserved_at_77[0x9]; 8287 8288 u8 command_input_inline_data[16][0x8]; 8289 8290 u8 command_output_inline_data[16][0x8]; 8291 8292 u8 output_mailbox_pointer_63_32[0x20]; 8293 8294 u8 output_mailbox_pointer_31_9[0x17]; 8295 u8 reserved_at_1b7[0x9]; 8296 8297 u8 output_length[0x20]; 8298 8299 u8 token[0x8]; 8300 u8 signature[0x8]; 8301 u8 reserved_at_1f0[0x8]; 8302 u8 status[0x7]; 8303 u8 ownership[0x1]; 8304 }; 8305 8306 struct mlx5_ifc_cmd_out_bits { 8307 u8 status[0x8]; 8308 u8 reserved_at_8[0x18]; 8309 8310 u8 syndrome[0x20]; 8311 8312 u8 command_output[0x20]; 8313 }; 8314 8315 struct mlx5_ifc_cmd_in_bits { 8316 u8 opcode[0x10]; 8317 u8 reserved_at_10[0x10]; 8318 8319 u8 reserved_at_20[0x10]; 8320 u8 op_mod[0x10]; 8321 8322 u8 command[0][0x20]; 8323 }; 8324 8325 struct mlx5_ifc_cmd_if_box_bits { 8326 u8 mailbox_data[512][0x8]; 8327 8328 u8 reserved_at_1000[0x180]; 8329 8330 u8 next_pointer_63_32[0x20]; 8331 8332 u8 next_pointer_31_10[0x16]; 8333 u8 reserved_at_11b6[0xa]; 8334 8335 u8 block_number[0x20]; 8336 8337 u8 reserved_at_11e0[0x8]; 8338 u8 token[0x8]; 8339 u8 ctrl_signature[0x8]; 8340 u8 signature[0x8]; 8341 }; 8342 8343 struct mlx5_ifc_mtt_bits { 8344 u8 ptag_63_32[0x20]; 8345 8346 u8 ptag_31_8[0x18]; 8347 u8 reserved_at_38[0x6]; 8348 u8 wr_en[0x1]; 8349 u8 rd_en[0x1]; 8350 }; 8351 8352 struct mlx5_ifc_query_wol_rol_out_bits { 8353 u8 status[0x8]; 8354 u8 reserved_at_8[0x18]; 8355 8356 u8 syndrome[0x20]; 8357 8358 u8 reserved_at_40[0x10]; 8359 u8 rol_mode[0x8]; 8360 u8 wol_mode[0x8]; 8361 8362 u8 reserved_at_60[0x20]; 8363 }; 8364 8365 struct mlx5_ifc_query_wol_rol_in_bits { 8366 u8 opcode[0x10]; 8367 u8 reserved_at_10[0x10]; 8368 8369 u8 reserved_at_20[0x10]; 8370 u8 op_mod[0x10]; 8371 8372 u8 reserved_at_40[0x40]; 8373 }; 8374 8375 struct mlx5_ifc_set_wol_rol_out_bits { 8376 u8 status[0x8]; 8377 u8 reserved_at_8[0x18]; 8378 8379 u8 syndrome[0x20]; 8380 8381 u8 reserved_at_40[0x40]; 8382 }; 8383 8384 struct mlx5_ifc_set_wol_rol_in_bits { 8385 u8 opcode[0x10]; 8386 u8 reserved_at_10[0x10]; 8387 8388 u8 reserved_at_20[0x10]; 8389 u8 op_mod[0x10]; 8390 8391 u8 rol_mode_valid[0x1]; 8392 u8 wol_mode_valid[0x1]; 8393 u8 reserved_at_42[0xe]; 8394 u8 rol_mode[0x8]; 8395 u8 wol_mode[0x8]; 8396 8397 u8 reserved_at_60[0x20]; 8398 }; 8399 8400 enum { 8401 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8402 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8403 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8404 }; 8405 8406 enum { 8407 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8408 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8409 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8410 }; 8411 8412 enum { 8413 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8414 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8415 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8416 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8417 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8424 }; 8425 8426 struct mlx5_ifc_initial_seg_bits { 8427 u8 fw_rev_minor[0x10]; 8428 u8 fw_rev_major[0x10]; 8429 8430 u8 cmd_interface_rev[0x10]; 8431 u8 fw_rev_subminor[0x10]; 8432 8433 u8 reserved_at_40[0x40]; 8434 8435 u8 cmdq_phy_addr_63_32[0x20]; 8436 8437 u8 cmdq_phy_addr_31_12[0x14]; 8438 u8 reserved_at_b4[0x2]; 8439 u8 nic_interface[0x2]; 8440 u8 log_cmdq_size[0x4]; 8441 u8 log_cmdq_stride[0x4]; 8442 8443 u8 command_doorbell_vector[0x20]; 8444 8445 u8 reserved_at_e0[0xf00]; 8446 8447 u8 initializing[0x1]; 8448 u8 reserved_at_fe1[0x4]; 8449 u8 nic_interface_supported[0x3]; 8450 u8 reserved_at_fe8[0x18]; 8451 8452 struct mlx5_ifc_health_buffer_bits health_buffer; 8453 8454 u8 no_dram_nic_offset[0x20]; 8455 8456 u8 reserved_at_1220[0x6e40]; 8457 8458 u8 reserved_at_8060[0x1f]; 8459 u8 clear_int[0x1]; 8460 8461 u8 health_syndrome[0x8]; 8462 u8 health_counter[0x18]; 8463 8464 u8 reserved_at_80a0[0x17fc0]; 8465 }; 8466 8467 struct mlx5_ifc_mtpps_reg_bits { 8468 u8 reserved_at_0[0xc]; 8469 u8 cap_number_of_pps_pins[0x4]; 8470 u8 reserved_at_10[0x4]; 8471 u8 cap_max_num_of_pps_in_pins[0x4]; 8472 u8 reserved_at_18[0x4]; 8473 u8 cap_max_num_of_pps_out_pins[0x4]; 8474 8475 u8 reserved_at_20[0x24]; 8476 u8 cap_pin_3_mode[0x4]; 8477 u8 reserved_at_48[0x4]; 8478 u8 cap_pin_2_mode[0x4]; 8479 u8 reserved_at_50[0x4]; 8480 u8 cap_pin_1_mode[0x4]; 8481 u8 reserved_at_58[0x4]; 8482 u8 cap_pin_0_mode[0x4]; 8483 8484 u8 reserved_at_60[0x4]; 8485 u8 cap_pin_7_mode[0x4]; 8486 u8 reserved_at_68[0x4]; 8487 u8 cap_pin_6_mode[0x4]; 8488 u8 reserved_at_70[0x4]; 8489 u8 cap_pin_5_mode[0x4]; 8490 u8 reserved_at_78[0x4]; 8491 u8 cap_pin_4_mode[0x4]; 8492 8493 u8 field_select[0x20]; 8494 u8 reserved_at_a0[0x60]; 8495 8496 u8 enable[0x1]; 8497 u8 reserved_at_101[0xb]; 8498 u8 pattern[0x4]; 8499 u8 reserved_at_110[0x4]; 8500 u8 pin_mode[0x4]; 8501 u8 pin[0x8]; 8502 8503 u8 reserved_at_120[0x20]; 8504 8505 u8 time_stamp[0x40]; 8506 8507 u8 out_pulse_duration[0x10]; 8508 u8 out_periodic_adjustment[0x10]; 8509 u8 enhanced_out_periodic_adjustment[0x20]; 8510 8511 u8 reserved_at_1c0[0x20]; 8512 }; 8513 8514 struct mlx5_ifc_mtppse_reg_bits { 8515 u8 reserved_at_0[0x18]; 8516 u8 pin[0x8]; 8517 u8 event_arm[0x1]; 8518 u8 reserved_at_21[0x1b]; 8519 u8 event_generation_mode[0x4]; 8520 u8 reserved_at_40[0x40]; 8521 }; 8522 8523 struct mlx5_ifc_mcqi_cap_bits { 8524 u8 supported_info_bitmask[0x20]; 8525 8526 u8 component_size[0x20]; 8527 8528 u8 max_component_size[0x20]; 8529 8530 u8 log_mcda_word_size[0x4]; 8531 u8 reserved_at_64[0xc]; 8532 u8 mcda_max_write_size[0x10]; 8533 8534 u8 rd_en[0x1]; 8535 u8 reserved_at_81[0x1]; 8536 u8 match_chip_id[0x1]; 8537 u8 match_psid[0x1]; 8538 u8 check_user_timestamp[0x1]; 8539 u8 match_base_guid_mac[0x1]; 8540 u8 reserved_at_86[0x1a]; 8541 }; 8542 8543 struct mlx5_ifc_mcqi_reg_bits { 8544 u8 read_pending_component[0x1]; 8545 u8 reserved_at_1[0xf]; 8546 u8 component_index[0x10]; 8547 8548 u8 reserved_at_20[0x20]; 8549 8550 u8 reserved_at_40[0x1b]; 8551 u8 info_type[0x5]; 8552 8553 u8 info_size[0x20]; 8554 8555 u8 offset[0x20]; 8556 8557 u8 reserved_at_a0[0x10]; 8558 u8 data_size[0x10]; 8559 8560 u8 data[0][0x20]; 8561 }; 8562 8563 struct mlx5_ifc_mcc_reg_bits { 8564 u8 reserved_at_0[0x4]; 8565 u8 time_elapsed_since_last_cmd[0xc]; 8566 u8 reserved_at_10[0x8]; 8567 u8 instruction[0x8]; 8568 8569 u8 reserved_at_20[0x10]; 8570 u8 component_index[0x10]; 8571 8572 u8 reserved_at_40[0x8]; 8573 u8 update_handle[0x18]; 8574 8575 u8 handle_owner_type[0x4]; 8576 u8 handle_owner_host_id[0x4]; 8577 u8 reserved_at_68[0x1]; 8578 u8 control_progress[0x7]; 8579 u8 error_code[0x8]; 8580 u8 reserved_at_78[0x4]; 8581 u8 control_state[0x4]; 8582 8583 u8 component_size[0x20]; 8584 8585 u8 reserved_at_a0[0x60]; 8586 }; 8587 8588 struct mlx5_ifc_mcda_reg_bits { 8589 u8 reserved_at_0[0x8]; 8590 u8 update_handle[0x18]; 8591 8592 u8 offset[0x20]; 8593 8594 u8 reserved_at_40[0x10]; 8595 u8 size[0x10]; 8596 8597 u8 reserved_at_60[0x20]; 8598 8599 u8 data[0][0x20]; 8600 }; 8601 8602 union mlx5_ifc_ports_control_registers_document_bits { 8603 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8604 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8605 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8606 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8607 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8608 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8609 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8610 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8611 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8612 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8613 struct mlx5_ifc_paos_reg_bits paos_reg; 8614 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8615 struct mlx5_ifc_peir_reg_bits peir_reg; 8616 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8617 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8618 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8619 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8620 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8621 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8622 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8623 struct mlx5_ifc_plib_reg_bits plib_reg; 8624 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8625 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8626 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8627 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8628 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8629 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8630 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8631 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8632 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8633 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8634 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8635 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8636 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8637 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8638 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8639 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8640 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8641 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8642 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8643 struct mlx5_ifc_pude_reg_bits pude_reg; 8644 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8645 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8646 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8647 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8648 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8649 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8650 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8651 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8652 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8653 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8654 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8655 u8 reserved_at_0[0x60e0]; 8656 }; 8657 8658 union mlx5_ifc_debug_enhancements_document_bits { 8659 struct mlx5_ifc_health_buffer_bits health_buffer; 8660 u8 reserved_at_0[0x200]; 8661 }; 8662 8663 union mlx5_ifc_uplink_pci_interface_document_bits { 8664 struct mlx5_ifc_initial_seg_bits initial_seg; 8665 u8 reserved_at_0[0x20060]; 8666 }; 8667 8668 struct mlx5_ifc_set_flow_table_root_out_bits { 8669 u8 status[0x8]; 8670 u8 reserved_at_8[0x18]; 8671 8672 u8 syndrome[0x20]; 8673 8674 u8 reserved_at_40[0x40]; 8675 }; 8676 8677 struct mlx5_ifc_set_flow_table_root_in_bits { 8678 u8 opcode[0x10]; 8679 u8 reserved_at_10[0x10]; 8680 8681 u8 reserved_at_20[0x10]; 8682 u8 op_mod[0x10]; 8683 8684 u8 other_vport[0x1]; 8685 u8 reserved_at_41[0xf]; 8686 u8 vport_number[0x10]; 8687 8688 u8 reserved_at_60[0x20]; 8689 8690 u8 table_type[0x8]; 8691 u8 reserved_at_88[0x18]; 8692 8693 u8 reserved_at_a0[0x8]; 8694 u8 table_id[0x18]; 8695 8696 u8 reserved_at_c0[0x8]; 8697 u8 underlay_qpn[0x18]; 8698 u8 reserved_at_e0[0x120]; 8699 }; 8700 8701 enum { 8702 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8703 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8704 }; 8705 8706 struct mlx5_ifc_modify_flow_table_out_bits { 8707 u8 status[0x8]; 8708 u8 reserved_at_8[0x18]; 8709 8710 u8 syndrome[0x20]; 8711 8712 u8 reserved_at_40[0x40]; 8713 }; 8714 8715 struct mlx5_ifc_modify_flow_table_in_bits { 8716 u8 opcode[0x10]; 8717 u8 reserved_at_10[0x10]; 8718 8719 u8 reserved_at_20[0x10]; 8720 u8 op_mod[0x10]; 8721 8722 u8 other_vport[0x1]; 8723 u8 reserved_at_41[0xf]; 8724 u8 vport_number[0x10]; 8725 8726 u8 reserved_at_60[0x10]; 8727 u8 modify_field_select[0x10]; 8728 8729 u8 table_type[0x8]; 8730 u8 reserved_at_88[0x18]; 8731 8732 u8 reserved_at_a0[0x8]; 8733 u8 table_id[0x18]; 8734 8735 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8736 }; 8737 8738 struct mlx5_ifc_ets_tcn_config_reg_bits { 8739 u8 g[0x1]; 8740 u8 b[0x1]; 8741 u8 r[0x1]; 8742 u8 reserved_at_3[0x9]; 8743 u8 group[0x4]; 8744 u8 reserved_at_10[0x9]; 8745 u8 bw_allocation[0x7]; 8746 8747 u8 reserved_at_20[0xc]; 8748 u8 max_bw_units[0x4]; 8749 u8 reserved_at_30[0x8]; 8750 u8 max_bw_value[0x8]; 8751 }; 8752 8753 struct mlx5_ifc_ets_global_config_reg_bits { 8754 u8 reserved_at_0[0x2]; 8755 u8 r[0x1]; 8756 u8 reserved_at_3[0x1d]; 8757 8758 u8 reserved_at_20[0xc]; 8759 u8 max_bw_units[0x4]; 8760 u8 reserved_at_30[0x8]; 8761 u8 max_bw_value[0x8]; 8762 }; 8763 8764 struct mlx5_ifc_qetc_reg_bits { 8765 u8 reserved_at_0[0x8]; 8766 u8 port_number[0x8]; 8767 u8 reserved_at_10[0x30]; 8768 8769 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8770 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8771 }; 8772 8773 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8774 u8 e[0x1]; 8775 u8 reserved_at_01[0x0b]; 8776 u8 prio[0x04]; 8777 }; 8778 8779 struct mlx5_ifc_qpdpm_reg_bits { 8780 u8 reserved_at_0[0x8]; 8781 u8 local_port[0x8]; 8782 u8 reserved_at_10[0x10]; 8783 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8784 }; 8785 8786 struct mlx5_ifc_qpts_reg_bits { 8787 u8 reserved_at_0[0x8]; 8788 u8 local_port[0x8]; 8789 u8 reserved_at_10[0x2d]; 8790 u8 trust_state[0x3]; 8791 }; 8792 8793 struct mlx5_ifc_pptb_reg_bits { 8794 u8 reserved_at_0[0x2]; 8795 u8 mm[0x2]; 8796 u8 reserved_at_4[0x4]; 8797 u8 local_port[0x8]; 8798 u8 reserved_at_10[0x6]; 8799 u8 cm[0x1]; 8800 u8 um[0x1]; 8801 u8 pm[0x8]; 8802 8803 u8 prio_x_buff[0x20]; 8804 8805 u8 pm_msb[0x8]; 8806 u8 reserved_at_48[0x10]; 8807 u8 ctrl_buff[0x4]; 8808 u8 untagged_buff[0x4]; 8809 }; 8810 8811 struct mlx5_ifc_pbmc_reg_bits { 8812 u8 reserved_at_0[0x8]; 8813 u8 local_port[0x8]; 8814 u8 reserved_at_10[0x10]; 8815 8816 u8 xoff_timer_value[0x10]; 8817 u8 xoff_refresh[0x10]; 8818 8819 u8 reserved_at_40[0x9]; 8820 u8 fullness_threshold[0x7]; 8821 u8 port_buffer_size[0x10]; 8822 8823 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8824 8825 u8 reserved_at_2e0[0x40]; 8826 }; 8827 8828 struct mlx5_ifc_qtct_reg_bits { 8829 u8 reserved_at_0[0x8]; 8830 u8 port_number[0x8]; 8831 u8 reserved_at_10[0xd]; 8832 u8 prio[0x3]; 8833 8834 u8 reserved_at_20[0x1d]; 8835 u8 tclass[0x3]; 8836 }; 8837 8838 struct mlx5_ifc_mcia_reg_bits { 8839 u8 l[0x1]; 8840 u8 reserved_at_1[0x7]; 8841 u8 module[0x8]; 8842 u8 reserved_at_10[0x8]; 8843 u8 status[0x8]; 8844 8845 u8 i2c_device_address[0x8]; 8846 u8 page_number[0x8]; 8847 u8 device_address[0x10]; 8848 8849 u8 reserved_at_40[0x10]; 8850 u8 size[0x10]; 8851 8852 u8 reserved_at_60[0x20]; 8853 8854 u8 dword_0[0x20]; 8855 u8 dword_1[0x20]; 8856 u8 dword_2[0x20]; 8857 u8 dword_3[0x20]; 8858 u8 dword_4[0x20]; 8859 u8 dword_5[0x20]; 8860 u8 dword_6[0x20]; 8861 u8 dword_7[0x20]; 8862 u8 dword_8[0x20]; 8863 u8 dword_9[0x20]; 8864 u8 dword_10[0x20]; 8865 u8 dword_11[0x20]; 8866 }; 8867 8868 struct mlx5_ifc_dcbx_param_bits { 8869 u8 dcbx_cee_cap[0x1]; 8870 u8 dcbx_ieee_cap[0x1]; 8871 u8 dcbx_standby_cap[0x1]; 8872 u8 reserved_at_0[0x5]; 8873 u8 port_number[0x8]; 8874 u8 reserved_at_10[0xa]; 8875 u8 max_application_table_size[6]; 8876 u8 reserved_at_20[0x15]; 8877 u8 version_oper[0x3]; 8878 u8 reserved_at_38[5]; 8879 u8 version_admin[0x3]; 8880 u8 willing_admin[0x1]; 8881 u8 reserved_at_41[0x3]; 8882 u8 pfc_cap_oper[0x4]; 8883 u8 reserved_at_48[0x4]; 8884 u8 pfc_cap_admin[0x4]; 8885 u8 reserved_at_50[0x4]; 8886 u8 num_of_tc_oper[0x4]; 8887 u8 reserved_at_58[0x4]; 8888 u8 num_of_tc_admin[0x4]; 8889 u8 remote_willing[0x1]; 8890 u8 reserved_at_61[3]; 8891 u8 remote_pfc_cap[4]; 8892 u8 reserved_at_68[0x14]; 8893 u8 remote_num_of_tc[0x4]; 8894 u8 reserved_at_80[0x18]; 8895 u8 error[0x8]; 8896 u8 reserved_at_a0[0x160]; 8897 }; 8898 8899 struct mlx5_ifc_lagc_bits { 8900 u8 reserved_at_0[0x1d]; 8901 u8 lag_state[0x3]; 8902 8903 u8 reserved_at_20[0x14]; 8904 u8 tx_remap_affinity_2[0x4]; 8905 u8 reserved_at_38[0x4]; 8906 u8 tx_remap_affinity_1[0x4]; 8907 }; 8908 8909 struct mlx5_ifc_create_lag_out_bits { 8910 u8 status[0x8]; 8911 u8 reserved_at_8[0x18]; 8912 8913 u8 syndrome[0x20]; 8914 8915 u8 reserved_at_40[0x40]; 8916 }; 8917 8918 struct mlx5_ifc_create_lag_in_bits { 8919 u8 opcode[0x10]; 8920 u8 reserved_at_10[0x10]; 8921 8922 u8 reserved_at_20[0x10]; 8923 u8 op_mod[0x10]; 8924 8925 struct mlx5_ifc_lagc_bits ctx; 8926 }; 8927 8928 struct mlx5_ifc_modify_lag_out_bits { 8929 u8 status[0x8]; 8930 u8 reserved_at_8[0x18]; 8931 8932 u8 syndrome[0x20]; 8933 8934 u8 reserved_at_40[0x40]; 8935 }; 8936 8937 struct mlx5_ifc_modify_lag_in_bits { 8938 u8 opcode[0x10]; 8939 u8 reserved_at_10[0x10]; 8940 8941 u8 reserved_at_20[0x10]; 8942 u8 op_mod[0x10]; 8943 8944 u8 reserved_at_40[0x20]; 8945 u8 field_select[0x20]; 8946 8947 struct mlx5_ifc_lagc_bits ctx; 8948 }; 8949 8950 struct mlx5_ifc_query_lag_out_bits { 8951 u8 status[0x8]; 8952 u8 reserved_at_8[0x18]; 8953 8954 u8 syndrome[0x20]; 8955 8956 u8 reserved_at_40[0x40]; 8957 8958 struct mlx5_ifc_lagc_bits ctx; 8959 }; 8960 8961 struct mlx5_ifc_query_lag_in_bits { 8962 u8 opcode[0x10]; 8963 u8 reserved_at_10[0x10]; 8964 8965 u8 reserved_at_20[0x10]; 8966 u8 op_mod[0x10]; 8967 8968 u8 reserved_at_40[0x40]; 8969 }; 8970 8971 struct mlx5_ifc_destroy_lag_out_bits { 8972 u8 status[0x8]; 8973 u8 reserved_at_8[0x18]; 8974 8975 u8 syndrome[0x20]; 8976 8977 u8 reserved_at_40[0x40]; 8978 }; 8979 8980 struct mlx5_ifc_destroy_lag_in_bits { 8981 u8 opcode[0x10]; 8982 u8 reserved_at_10[0x10]; 8983 8984 u8 reserved_at_20[0x10]; 8985 u8 op_mod[0x10]; 8986 8987 u8 reserved_at_40[0x40]; 8988 }; 8989 8990 struct mlx5_ifc_create_vport_lag_out_bits { 8991 u8 status[0x8]; 8992 u8 reserved_at_8[0x18]; 8993 8994 u8 syndrome[0x20]; 8995 8996 u8 reserved_at_40[0x40]; 8997 }; 8998 8999 struct mlx5_ifc_create_vport_lag_in_bits { 9000 u8 opcode[0x10]; 9001 u8 reserved_at_10[0x10]; 9002 9003 u8 reserved_at_20[0x10]; 9004 u8 op_mod[0x10]; 9005 9006 u8 reserved_at_40[0x40]; 9007 }; 9008 9009 struct mlx5_ifc_destroy_vport_lag_out_bits { 9010 u8 status[0x8]; 9011 u8 reserved_at_8[0x18]; 9012 9013 u8 syndrome[0x20]; 9014 9015 u8 reserved_at_40[0x40]; 9016 }; 9017 9018 struct mlx5_ifc_destroy_vport_lag_in_bits { 9019 u8 opcode[0x10]; 9020 u8 reserved_at_10[0x10]; 9021 9022 u8 reserved_at_20[0x10]; 9023 u8 op_mod[0x10]; 9024 9025 u8 reserved_at_40[0x40]; 9026 }; 9027 9028 struct mlx5_ifc_alloc_memic_in_bits { 9029 u8 opcode[0x10]; 9030 u8 reserved_at_10[0x10]; 9031 9032 u8 reserved_at_20[0x10]; 9033 u8 op_mod[0x10]; 9034 9035 u8 reserved_at_30[0x20]; 9036 9037 u8 reserved_at_40[0x18]; 9038 u8 log_memic_addr_alignment[0x8]; 9039 9040 u8 range_start_addr[0x40]; 9041 9042 u8 range_size[0x20]; 9043 9044 u8 memic_size[0x20]; 9045 }; 9046 9047 struct mlx5_ifc_alloc_memic_out_bits { 9048 u8 status[0x8]; 9049 u8 reserved_at_8[0x18]; 9050 9051 u8 syndrome[0x20]; 9052 9053 u8 memic_start_addr[0x40]; 9054 }; 9055 9056 struct mlx5_ifc_dealloc_memic_in_bits { 9057 u8 opcode[0x10]; 9058 u8 reserved_at_10[0x10]; 9059 9060 u8 reserved_at_20[0x10]; 9061 u8 op_mod[0x10]; 9062 9063 u8 reserved_at_40[0x40]; 9064 9065 u8 memic_start_addr[0x40]; 9066 9067 u8 memic_size[0x20]; 9068 9069 u8 reserved_at_e0[0x20]; 9070 }; 9071 9072 struct mlx5_ifc_dealloc_memic_out_bits { 9073 u8 status[0x8]; 9074 u8 reserved_at_8[0x18]; 9075 9076 u8 syndrome[0x20]; 9077 9078 u8 reserved_at_40[0x40]; 9079 }; 9080 9081 #endif /* MLX5_IFC_H */ 9082