1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 }; 82 83 enum { 84 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 85 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 86 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 87 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 88 }; 89 90 enum { 91 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 92 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 93 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 94 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 95 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 129 MLX5_CMD_OP_RESUME_VHCA = 0x116, 130 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 131 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 132 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 133 MLX5_CMD_OP_CREATE_MKEY = 0x200, 134 MLX5_CMD_OP_QUERY_MKEY = 0x201, 135 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 136 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 137 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 138 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 139 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 140 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 141 MLX5_CMD_OP_CREATE_EQ = 0x301, 142 MLX5_CMD_OP_DESTROY_EQ = 0x302, 143 MLX5_CMD_OP_QUERY_EQ = 0x303, 144 MLX5_CMD_OP_GEN_EQE = 0x304, 145 MLX5_CMD_OP_CREATE_CQ = 0x400, 146 MLX5_CMD_OP_DESTROY_CQ = 0x401, 147 MLX5_CMD_OP_QUERY_CQ = 0x402, 148 MLX5_CMD_OP_MODIFY_CQ = 0x403, 149 MLX5_CMD_OP_CREATE_QP = 0x500, 150 MLX5_CMD_OP_DESTROY_QP = 0x501, 151 MLX5_CMD_OP_RST2INIT_QP = 0x502, 152 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 153 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 154 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 155 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 156 MLX5_CMD_OP_2ERR_QP = 0x507, 157 MLX5_CMD_OP_2RST_QP = 0x50a, 158 MLX5_CMD_OP_QUERY_QP = 0x50b, 159 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 160 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 161 MLX5_CMD_OP_CREATE_PSV = 0x600, 162 MLX5_CMD_OP_DESTROY_PSV = 0x601, 163 MLX5_CMD_OP_CREATE_SRQ = 0x700, 164 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 165 MLX5_CMD_OP_QUERY_SRQ = 0x702, 166 MLX5_CMD_OP_ARM_RQ = 0x703, 167 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 168 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 169 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 170 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 171 MLX5_CMD_OP_CREATE_DCT = 0x710, 172 MLX5_CMD_OP_DESTROY_DCT = 0x711, 173 MLX5_CMD_OP_DRAIN_DCT = 0x712, 174 MLX5_CMD_OP_QUERY_DCT = 0x713, 175 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 176 MLX5_CMD_OP_CREATE_XRQ = 0x717, 177 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 178 MLX5_CMD_OP_QUERY_XRQ = 0x719, 179 MLX5_CMD_OP_ARM_XRQ = 0x71a, 180 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 181 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 182 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 183 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 184 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 185 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 186 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 187 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 188 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 189 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 190 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 191 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 192 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 193 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 195 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 198 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 199 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 200 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 201 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 202 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 203 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 204 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 205 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 206 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 207 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 208 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 209 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 210 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 211 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 212 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 213 MLX5_CMD_OP_ALLOC_PD = 0x800, 214 MLX5_CMD_OP_DEALLOC_PD = 0x801, 215 MLX5_CMD_OP_ALLOC_UAR = 0x802, 216 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 217 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 218 MLX5_CMD_OP_ACCESS_REG = 0x805, 219 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 220 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 221 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 222 MLX5_CMD_OP_MAD_IFC = 0x50d, 223 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 224 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 225 MLX5_CMD_OP_NOP = 0x80d, 226 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 227 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 229 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 230 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 231 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 232 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 233 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 234 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 235 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 236 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 237 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 238 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 239 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 240 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 241 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 242 MLX5_CMD_OP_CREATE_LAG = 0x840, 243 MLX5_CMD_OP_MODIFY_LAG = 0x841, 244 MLX5_CMD_OP_QUERY_LAG = 0x842, 245 MLX5_CMD_OP_DESTROY_LAG = 0x843, 246 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 247 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 248 MLX5_CMD_OP_CREATE_TIR = 0x900, 249 MLX5_CMD_OP_MODIFY_TIR = 0x901, 250 MLX5_CMD_OP_DESTROY_TIR = 0x902, 251 MLX5_CMD_OP_QUERY_TIR = 0x903, 252 MLX5_CMD_OP_CREATE_SQ = 0x904, 253 MLX5_CMD_OP_MODIFY_SQ = 0x905, 254 MLX5_CMD_OP_DESTROY_SQ = 0x906, 255 MLX5_CMD_OP_QUERY_SQ = 0x907, 256 MLX5_CMD_OP_CREATE_RQ = 0x908, 257 MLX5_CMD_OP_MODIFY_RQ = 0x909, 258 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 259 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 260 MLX5_CMD_OP_QUERY_RQ = 0x90b, 261 MLX5_CMD_OP_CREATE_RMP = 0x90c, 262 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 263 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 264 MLX5_CMD_OP_QUERY_RMP = 0x90f, 265 MLX5_CMD_OP_CREATE_TIS = 0x912, 266 MLX5_CMD_OP_MODIFY_TIS = 0x913, 267 MLX5_CMD_OP_DESTROY_TIS = 0x914, 268 MLX5_CMD_OP_QUERY_TIS = 0x915, 269 MLX5_CMD_OP_CREATE_RQT = 0x916, 270 MLX5_CMD_OP_MODIFY_RQT = 0x917, 271 MLX5_CMD_OP_DESTROY_RQT = 0x918, 272 MLX5_CMD_OP_QUERY_RQT = 0x919, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 274 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 275 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 277 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 278 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 279 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 282 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 283 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 284 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 285 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 286 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 287 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 288 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 289 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 290 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 291 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 292 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 293 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 294 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 295 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 296 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 297 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 298 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 299 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 300 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 301 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 302 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 303 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 304 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 305 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 306 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 307 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 308 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 309 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 310 MLX5_CMD_OP_MAX 311 }; 312 313 /* Valid range for general commands that don't work over an object */ 314 enum { 315 MLX5_CMD_OP_GENERAL_START = 0xb00, 316 MLX5_CMD_OP_GENERAL_END = 0xd00, 317 }; 318 319 enum { 320 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 321 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 322 }; 323 324 struct mlx5_ifc_flow_table_fields_supported_bits { 325 u8 outer_dmac[0x1]; 326 u8 outer_smac[0x1]; 327 u8 outer_ether_type[0x1]; 328 u8 outer_ip_version[0x1]; 329 u8 outer_first_prio[0x1]; 330 u8 outer_first_cfi[0x1]; 331 u8 outer_first_vid[0x1]; 332 u8 outer_ipv4_ttl[0x1]; 333 u8 outer_second_prio[0x1]; 334 u8 outer_second_cfi[0x1]; 335 u8 outer_second_vid[0x1]; 336 u8 reserved_at_b[0x1]; 337 u8 outer_sip[0x1]; 338 u8 outer_dip[0x1]; 339 u8 outer_frag[0x1]; 340 u8 outer_ip_protocol[0x1]; 341 u8 outer_ip_ecn[0x1]; 342 u8 outer_ip_dscp[0x1]; 343 u8 outer_udp_sport[0x1]; 344 u8 outer_udp_dport[0x1]; 345 u8 outer_tcp_sport[0x1]; 346 u8 outer_tcp_dport[0x1]; 347 u8 outer_tcp_flags[0x1]; 348 u8 outer_gre_protocol[0x1]; 349 u8 outer_gre_key[0x1]; 350 u8 outer_vxlan_vni[0x1]; 351 u8 outer_geneve_vni[0x1]; 352 u8 outer_geneve_oam[0x1]; 353 u8 outer_geneve_protocol_type[0x1]; 354 u8 outer_geneve_opt_len[0x1]; 355 u8 source_vhca_port[0x1]; 356 u8 source_eswitch_port[0x1]; 357 358 u8 inner_dmac[0x1]; 359 u8 inner_smac[0x1]; 360 u8 inner_ether_type[0x1]; 361 u8 inner_ip_version[0x1]; 362 u8 inner_first_prio[0x1]; 363 u8 inner_first_cfi[0x1]; 364 u8 inner_first_vid[0x1]; 365 u8 reserved_at_27[0x1]; 366 u8 inner_second_prio[0x1]; 367 u8 inner_second_cfi[0x1]; 368 u8 inner_second_vid[0x1]; 369 u8 reserved_at_2b[0x1]; 370 u8 inner_sip[0x1]; 371 u8 inner_dip[0x1]; 372 u8 inner_frag[0x1]; 373 u8 inner_ip_protocol[0x1]; 374 u8 inner_ip_ecn[0x1]; 375 u8 inner_ip_dscp[0x1]; 376 u8 inner_udp_sport[0x1]; 377 u8 inner_udp_dport[0x1]; 378 u8 inner_tcp_sport[0x1]; 379 u8 inner_tcp_dport[0x1]; 380 u8 inner_tcp_flags[0x1]; 381 u8 reserved_at_37[0x9]; 382 383 u8 geneve_tlv_option_0_data[0x1]; 384 u8 geneve_tlv_option_0_exist[0x1]; 385 u8 reserved_at_42[0x3]; 386 u8 outer_first_mpls_over_udp[0x4]; 387 u8 outer_first_mpls_over_gre[0x4]; 388 u8 inner_first_mpls[0x4]; 389 u8 outer_first_mpls[0x4]; 390 u8 reserved_at_55[0x2]; 391 u8 outer_esp_spi[0x1]; 392 u8 reserved_at_58[0x2]; 393 u8 bth_dst_qp[0x1]; 394 u8 reserved_at_5b[0x5]; 395 396 u8 reserved_at_60[0x18]; 397 u8 metadata_reg_c_7[0x1]; 398 u8 metadata_reg_c_6[0x1]; 399 u8 metadata_reg_c_5[0x1]; 400 u8 metadata_reg_c_4[0x1]; 401 u8 metadata_reg_c_3[0x1]; 402 u8 metadata_reg_c_2[0x1]; 403 u8 metadata_reg_c_1[0x1]; 404 u8 metadata_reg_c_0[0x1]; 405 }; 406 407 /* Table 2170 - Flow Table Fields Supported 2 Format */ 408 struct mlx5_ifc_flow_table_fields_supported_2_bits { 409 u8 reserved_at_0[0xe]; 410 u8 bth_opcode[0x1]; 411 u8 reserved_at_f[0x1]; 412 u8 tunnel_header_0_1[0x1]; 413 u8 reserved_at_11[0xf]; 414 415 u8 reserved_at_20[0x60]; 416 }; 417 418 struct mlx5_ifc_flow_table_prop_layout_bits { 419 u8 ft_support[0x1]; 420 u8 reserved_at_1[0x1]; 421 u8 flow_counter[0x1]; 422 u8 flow_modify_en[0x1]; 423 u8 modify_root[0x1]; 424 u8 identified_miss_table_mode[0x1]; 425 u8 flow_table_modify[0x1]; 426 u8 reformat[0x1]; 427 u8 decap[0x1]; 428 u8 reserved_at_9[0x1]; 429 u8 pop_vlan[0x1]; 430 u8 push_vlan[0x1]; 431 u8 reserved_at_c[0x1]; 432 u8 pop_vlan_2[0x1]; 433 u8 push_vlan_2[0x1]; 434 u8 reformat_and_vlan_action[0x1]; 435 u8 reserved_at_10[0x1]; 436 u8 sw_owner[0x1]; 437 u8 reformat_l3_tunnel_to_l2[0x1]; 438 u8 reformat_l2_to_l3_tunnel[0x1]; 439 u8 reformat_and_modify_action[0x1]; 440 u8 ignore_flow_level[0x1]; 441 u8 reserved_at_16[0x1]; 442 u8 table_miss_action_domain[0x1]; 443 u8 termination_table[0x1]; 444 u8 reformat_and_fwd_to_table[0x1]; 445 u8 reserved_at_1a[0x2]; 446 u8 ipsec_encrypt[0x1]; 447 u8 ipsec_decrypt[0x1]; 448 u8 sw_owner_v2[0x1]; 449 u8 reserved_at_1f[0x1]; 450 451 u8 termination_table_raw_traffic[0x1]; 452 u8 reserved_at_21[0x1]; 453 u8 log_max_ft_size[0x6]; 454 u8 log_max_modify_header_context[0x8]; 455 u8 max_modify_header_actions[0x8]; 456 u8 max_ft_level[0x8]; 457 458 u8 reformat_add_esp_trasport[0x1]; 459 u8 reserved_at_41[0x2]; 460 u8 reformat_del_esp_trasport[0x1]; 461 u8 reserved_at_44[0x2]; 462 u8 execute_aso[0x1]; 463 u8 reserved_at_47[0x19]; 464 465 u8 reserved_at_60[0x2]; 466 u8 reformat_insert[0x1]; 467 u8 reformat_remove[0x1]; 468 u8 macsec_encrypt[0x1]; 469 u8 macsec_decrypt[0x1]; 470 u8 reserved_at_66[0x2]; 471 u8 reformat_add_macsec[0x1]; 472 u8 reformat_remove_macsec[0x1]; 473 u8 reserved_at_6a[0xe]; 474 u8 log_max_ft_num[0x8]; 475 476 u8 reserved_at_80[0x10]; 477 u8 log_max_flow_counter[0x8]; 478 u8 log_max_destination[0x8]; 479 480 u8 reserved_at_a0[0x18]; 481 u8 log_max_flow[0x8]; 482 483 u8 reserved_at_c0[0x40]; 484 485 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 486 487 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 488 }; 489 490 struct mlx5_ifc_odp_per_transport_service_cap_bits { 491 u8 send[0x1]; 492 u8 receive[0x1]; 493 u8 write[0x1]; 494 u8 read[0x1]; 495 u8 atomic[0x1]; 496 u8 srq_receive[0x1]; 497 u8 reserved_at_6[0x1a]; 498 }; 499 500 struct mlx5_ifc_ipv4_layout_bits { 501 u8 reserved_at_0[0x60]; 502 503 u8 ipv4[0x20]; 504 }; 505 506 struct mlx5_ifc_ipv6_layout_bits { 507 u8 ipv6[16][0x8]; 508 }; 509 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 511 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 512 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 513 u8 reserved_at_0[0x80]; 514 }; 515 516 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 517 u8 smac_47_16[0x20]; 518 519 u8 smac_15_0[0x10]; 520 u8 ethertype[0x10]; 521 522 u8 dmac_47_16[0x20]; 523 524 u8 dmac_15_0[0x10]; 525 u8 first_prio[0x3]; 526 u8 first_cfi[0x1]; 527 u8 first_vid[0xc]; 528 529 u8 ip_protocol[0x8]; 530 u8 ip_dscp[0x6]; 531 u8 ip_ecn[0x2]; 532 u8 cvlan_tag[0x1]; 533 u8 svlan_tag[0x1]; 534 u8 frag[0x1]; 535 u8 ip_version[0x4]; 536 u8 tcp_flags[0x9]; 537 538 u8 tcp_sport[0x10]; 539 u8 tcp_dport[0x10]; 540 541 u8 reserved_at_c0[0x10]; 542 u8 ipv4_ihl[0x4]; 543 u8 reserved_at_c4[0x4]; 544 545 u8 ttl_hoplimit[0x8]; 546 547 u8 udp_sport[0x10]; 548 u8 udp_dport[0x10]; 549 550 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 551 552 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 553 }; 554 555 struct mlx5_ifc_nvgre_key_bits { 556 u8 hi[0x18]; 557 u8 lo[0x8]; 558 }; 559 560 union mlx5_ifc_gre_key_bits { 561 struct mlx5_ifc_nvgre_key_bits nvgre; 562 u8 key[0x20]; 563 }; 564 565 struct mlx5_ifc_fte_match_set_misc_bits { 566 u8 gre_c_present[0x1]; 567 u8 reserved_at_1[0x1]; 568 u8 gre_k_present[0x1]; 569 u8 gre_s_present[0x1]; 570 u8 source_vhca_port[0x4]; 571 u8 source_sqn[0x18]; 572 573 u8 source_eswitch_owner_vhca_id[0x10]; 574 u8 source_port[0x10]; 575 576 u8 outer_second_prio[0x3]; 577 u8 outer_second_cfi[0x1]; 578 u8 outer_second_vid[0xc]; 579 u8 inner_second_prio[0x3]; 580 u8 inner_second_cfi[0x1]; 581 u8 inner_second_vid[0xc]; 582 583 u8 outer_second_cvlan_tag[0x1]; 584 u8 inner_second_cvlan_tag[0x1]; 585 u8 outer_second_svlan_tag[0x1]; 586 u8 inner_second_svlan_tag[0x1]; 587 u8 reserved_at_64[0xc]; 588 u8 gre_protocol[0x10]; 589 590 union mlx5_ifc_gre_key_bits gre_key; 591 592 u8 vxlan_vni[0x18]; 593 u8 bth_opcode[0x8]; 594 595 u8 geneve_vni[0x18]; 596 u8 reserved_at_d8[0x6]; 597 u8 geneve_tlv_option_0_exist[0x1]; 598 u8 geneve_oam[0x1]; 599 600 u8 reserved_at_e0[0xc]; 601 u8 outer_ipv6_flow_label[0x14]; 602 603 u8 reserved_at_100[0xc]; 604 u8 inner_ipv6_flow_label[0x14]; 605 606 u8 reserved_at_120[0xa]; 607 u8 geneve_opt_len[0x6]; 608 u8 geneve_protocol_type[0x10]; 609 610 u8 reserved_at_140[0x8]; 611 u8 bth_dst_qp[0x18]; 612 u8 reserved_at_160[0x20]; 613 u8 outer_esp_spi[0x20]; 614 u8 reserved_at_1a0[0x60]; 615 }; 616 617 struct mlx5_ifc_fte_match_mpls_bits { 618 u8 mpls_label[0x14]; 619 u8 mpls_exp[0x3]; 620 u8 mpls_s_bos[0x1]; 621 u8 mpls_ttl[0x8]; 622 }; 623 624 struct mlx5_ifc_fte_match_set_misc2_bits { 625 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 626 627 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 628 629 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 630 631 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 632 633 u8 metadata_reg_c_7[0x20]; 634 635 u8 metadata_reg_c_6[0x20]; 636 637 u8 metadata_reg_c_5[0x20]; 638 639 u8 metadata_reg_c_4[0x20]; 640 641 u8 metadata_reg_c_3[0x20]; 642 643 u8 metadata_reg_c_2[0x20]; 644 645 u8 metadata_reg_c_1[0x20]; 646 647 u8 metadata_reg_c_0[0x20]; 648 649 u8 metadata_reg_a[0x20]; 650 651 u8 reserved_at_1a0[0x8]; 652 653 u8 macsec_syndrome[0x8]; 654 u8 ipsec_syndrome[0x8]; 655 u8 reserved_at_1b8[0x8]; 656 657 u8 reserved_at_1c0[0x40]; 658 }; 659 660 struct mlx5_ifc_fte_match_set_misc3_bits { 661 u8 inner_tcp_seq_num[0x20]; 662 663 u8 outer_tcp_seq_num[0x20]; 664 665 u8 inner_tcp_ack_num[0x20]; 666 667 u8 outer_tcp_ack_num[0x20]; 668 669 u8 reserved_at_80[0x8]; 670 u8 outer_vxlan_gpe_vni[0x18]; 671 672 u8 outer_vxlan_gpe_next_protocol[0x8]; 673 u8 outer_vxlan_gpe_flags[0x8]; 674 u8 reserved_at_b0[0x10]; 675 676 u8 icmp_header_data[0x20]; 677 678 u8 icmpv6_header_data[0x20]; 679 680 u8 icmp_type[0x8]; 681 u8 icmp_code[0x8]; 682 u8 icmpv6_type[0x8]; 683 u8 icmpv6_code[0x8]; 684 685 u8 geneve_tlv_option_0_data[0x20]; 686 687 u8 gtpu_teid[0x20]; 688 689 u8 gtpu_msg_type[0x8]; 690 u8 gtpu_msg_flags[0x8]; 691 u8 reserved_at_170[0x10]; 692 693 u8 gtpu_dw_2[0x20]; 694 695 u8 gtpu_first_ext_dw_0[0x20]; 696 697 u8 gtpu_dw_0[0x20]; 698 699 u8 reserved_at_1e0[0x20]; 700 }; 701 702 struct mlx5_ifc_fte_match_set_misc4_bits { 703 u8 prog_sample_field_value_0[0x20]; 704 705 u8 prog_sample_field_id_0[0x20]; 706 707 u8 prog_sample_field_value_1[0x20]; 708 709 u8 prog_sample_field_id_1[0x20]; 710 711 u8 prog_sample_field_value_2[0x20]; 712 713 u8 prog_sample_field_id_2[0x20]; 714 715 u8 prog_sample_field_value_3[0x20]; 716 717 u8 prog_sample_field_id_3[0x20]; 718 719 u8 reserved_at_100[0x100]; 720 }; 721 722 struct mlx5_ifc_fte_match_set_misc5_bits { 723 u8 macsec_tag_0[0x20]; 724 725 u8 macsec_tag_1[0x20]; 726 727 u8 macsec_tag_2[0x20]; 728 729 u8 macsec_tag_3[0x20]; 730 731 u8 tunnel_header_0[0x20]; 732 733 u8 tunnel_header_1[0x20]; 734 735 u8 tunnel_header_2[0x20]; 736 737 u8 tunnel_header_3[0x20]; 738 739 u8 reserved_at_100[0x100]; 740 }; 741 742 struct mlx5_ifc_cmd_pas_bits { 743 u8 pa_h[0x20]; 744 745 u8 pa_l[0x14]; 746 u8 reserved_at_34[0xc]; 747 }; 748 749 struct mlx5_ifc_uint64_bits { 750 u8 hi[0x20]; 751 752 u8 lo[0x20]; 753 }; 754 755 enum { 756 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 757 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 758 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 759 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 760 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 761 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 762 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 763 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 764 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 765 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 766 }; 767 768 struct mlx5_ifc_ads_bits { 769 u8 fl[0x1]; 770 u8 free_ar[0x1]; 771 u8 reserved_at_2[0xe]; 772 u8 pkey_index[0x10]; 773 774 u8 reserved_at_20[0x8]; 775 u8 grh[0x1]; 776 u8 mlid[0x7]; 777 u8 rlid[0x10]; 778 779 u8 ack_timeout[0x5]; 780 u8 reserved_at_45[0x3]; 781 u8 src_addr_index[0x8]; 782 u8 reserved_at_50[0x4]; 783 u8 stat_rate[0x4]; 784 u8 hop_limit[0x8]; 785 786 u8 reserved_at_60[0x4]; 787 u8 tclass[0x8]; 788 u8 flow_label[0x14]; 789 790 u8 rgid_rip[16][0x8]; 791 792 u8 reserved_at_100[0x4]; 793 u8 f_dscp[0x1]; 794 u8 f_ecn[0x1]; 795 u8 reserved_at_106[0x1]; 796 u8 f_eth_prio[0x1]; 797 u8 ecn[0x2]; 798 u8 dscp[0x6]; 799 u8 udp_sport[0x10]; 800 801 u8 dei_cfi[0x1]; 802 u8 eth_prio[0x3]; 803 u8 sl[0x4]; 804 u8 vhca_port_num[0x8]; 805 u8 rmac_47_32[0x10]; 806 807 u8 rmac_31_0[0x20]; 808 }; 809 810 struct mlx5_ifc_flow_table_nic_cap_bits { 811 u8 nic_rx_multi_path_tirs[0x1]; 812 u8 nic_rx_multi_path_tirs_fts[0x1]; 813 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 814 u8 reserved_at_3[0x4]; 815 u8 sw_owner_reformat_supported[0x1]; 816 u8 reserved_at_8[0x18]; 817 818 u8 encap_general_header[0x1]; 819 u8 reserved_at_21[0xa]; 820 u8 log_max_packet_reformat_context[0x5]; 821 u8 reserved_at_30[0x6]; 822 u8 max_encap_header_size[0xa]; 823 u8 reserved_at_40[0x1c0]; 824 825 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 826 827 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 828 829 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 830 831 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 832 833 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 834 835 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 836 837 u8 reserved_at_e00[0x700]; 838 839 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 840 841 u8 reserved_at_1580[0x280]; 842 843 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 844 845 u8 reserved_at_1880[0x780]; 846 847 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 848 849 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 850 851 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 852 853 u8 reserved_at_20c0[0x5f40]; 854 }; 855 856 struct mlx5_ifc_port_selection_cap_bits { 857 u8 reserved_at_0[0x10]; 858 u8 port_select_flow_table[0x1]; 859 u8 reserved_at_11[0x1]; 860 u8 port_select_flow_table_bypass[0x1]; 861 u8 reserved_at_13[0xd]; 862 863 u8 reserved_at_20[0x1e0]; 864 865 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 866 867 u8 reserved_at_400[0x7c00]; 868 }; 869 870 enum { 871 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 872 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 873 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 874 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 875 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 876 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 877 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 878 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 879 }; 880 881 struct mlx5_ifc_flow_table_eswitch_cap_bits { 882 u8 fdb_to_vport_reg_c_id[0x8]; 883 u8 reserved_at_8[0xd]; 884 u8 fdb_modify_header_fwd_to_table[0x1]; 885 u8 fdb_ipv4_ttl_modify[0x1]; 886 u8 flow_source[0x1]; 887 u8 reserved_at_18[0x2]; 888 u8 multi_fdb_encap[0x1]; 889 u8 egress_acl_forward_to_vport[0x1]; 890 u8 fdb_multi_path_to_table[0x1]; 891 u8 reserved_at_1d[0x3]; 892 893 u8 reserved_at_20[0x1e0]; 894 895 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 896 897 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 898 899 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 900 901 u8 reserved_at_800[0xC00]; 902 903 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 904 905 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 906 907 u8 reserved_at_1500[0x300]; 908 909 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 910 911 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 912 913 u8 sw_steering_uplink_icm_address_rx[0x40]; 914 915 u8 sw_steering_uplink_icm_address_tx[0x40]; 916 917 u8 reserved_at_1900[0x6700]; 918 }; 919 920 enum { 921 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 922 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 923 }; 924 925 struct mlx5_ifc_e_switch_cap_bits { 926 u8 vport_svlan_strip[0x1]; 927 u8 vport_cvlan_strip[0x1]; 928 u8 vport_svlan_insert[0x1]; 929 u8 vport_cvlan_insert_if_not_exist[0x1]; 930 u8 vport_cvlan_insert_overwrite[0x1]; 931 u8 reserved_at_5[0x1]; 932 u8 vport_cvlan_insert_always[0x1]; 933 u8 esw_shared_ingress_acl[0x1]; 934 u8 esw_uplink_ingress_acl[0x1]; 935 u8 root_ft_on_other_esw[0x1]; 936 u8 reserved_at_a[0xf]; 937 u8 esw_functions_changed[0x1]; 938 u8 reserved_at_1a[0x1]; 939 u8 ecpf_vport_exists[0x1]; 940 u8 counter_eswitch_affinity[0x1]; 941 u8 merged_eswitch[0x1]; 942 u8 nic_vport_node_guid_modify[0x1]; 943 u8 nic_vport_port_guid_modify[0x1]; 944 945 u8 vxlan_encap_decap[0x1]; 946 u8 nvgre_encap_decap[0x1]; 947 u8 reserved_at_22[0x1]; 948 u8 log_max_fdb_encap_uplink[0x5]; 949 u8 reserved_at_21[0x3]; 950 u8 log_max_packet_reformat_context[0x5]; 951 u8 reserved_2b[0x6]; 952 u8 max_encap_header_size[0xa]; 953 954 u8 reserved_at_40[0xb]; 955 u8 log_max_esw_sf[0x5]; 956 u8 esw_sf_base_id[0x10]; 957 958 u8 reserved_at_60[0x7a0]; 959 960 }; 961 962 struct mlx5_ifc_qos_cap_bits { 963 u8 packet_pacing[0x1]; 964 u8 esw_scheduling[0x1]; 965 u8 esw_bw_share[0x1]; 966 u8 esw_rate_limit[0x1]; 967 u8 reserved_at_4[0x1]; 968 u8 packet_pacing_burst_bound[0x1]; 969 u8 packet_pacing_typical_size[0x1]; 970 u8 reserved_at_7[0x1]; 971 u8 nic_sq_scheduling[0x1]; 972 u8 nic_bw_share[0x1]; 973 u8 nic_rate_limit[0x1]; 974 u8 packet_pacing_uid[0x1]; 975 u8 log_esw_max_sched_depth[0x4]; 976 u8 reserved_at_10[0x10]; 977 978 u8 reserved_at_20[0xb]; 979 u8 log_max_qos_nic_queue_group[0x5]; 980 u8 reserved_at_30[0x10]; 981 982 u8 packet_pacing_max_rate[0x20]; 983 984 u8 packet_pacing_min_rate[0x20]; 985 986 u8 reserved_at_80[0x10]; 987 u8 packet_pacing_rate_table_size[0x10]; 988 989 u8 esw_element_type[0x10]; 990 u8 esw_tsar_type[0x10]; 991 992 u8 reserved_at_c0[0x10]; 993 u8 max_qos_para_vport[0x10]; 994 995 u8 max_tsar_bw_share[0x20]; 996 997 u8 reserved_at_100[0x20]; 998 999 u8 reserved_at_120[0x3]; 1000 u8 log_meter_aso_granularity[0x5]; 1001 u8 reserved_at_128[0x3]; 1002 u8 log_meter_aso_max_alloc[0x5]; 1003 u8 reserved_at_130[0x3]; 1004 u8 log_max_num_meter_aso[0x5]; 1005 u8 reserved_at_138[0x8]; 1006 1007 u8 reserved_at_140[0x6c0]; 1008 }; 1009 1010 struct mlx5_ifc_debug_cap_bits { 1011 u8 core_dump_general[0x1]; 1012 u8 core_dump_qp[0x1]; 1013 u8 reserved_at_2[0x7]; 1014 u8 resource_dump[0x1]; 1015 u8 reserved_at_a[0x16]; 1016 1017 u8 reserved_at_20[0x2]; 1018 u8 stall_detect[0x1]; 1019 u8 reserved_at_23[0x1d]; 1020 1021 u8 reserved_at_40[0x7c0]; 1022 }; 1023 1024 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1025 u8 csum_cap[0x1]; 1026 u8 vlan_cap[0x1]; 1027 u8 lro_cap[0x1]; 1028 u8 lro_psh_flag[0x1]; 1029 u8 lro_time_stamp[0x1]; 1030 u8 reserved_at_5[0x2]; 1031 u8 wqe_vlan_insert[0x1]; 1032 u8 self_lb_en_modifiable[0x1]; 1033 u8 reserved_at_9[0x2]; 1034 u8 max_lso_cap[0x5]; 1035 u8 multi_pkt_send_wqe[0x2]; 1036 u8 wqe_inline_mode[0x2]; 1037 u8 rss_ind_tbl_cap[0x4]; 1038 u8 reg_umr_sq[0x1]; 1039 u8 scatter_fcs[0x1]; 1040 u8 enhanced_multi_pkt_send_wqe[0x1]; 1041 u8 tunnel_lso_const_out_ip_id[0x1]; 1042 u8 tunnel_lro_gre[0x1]; 1043 u8 tunnel_lro_vxlan[0x1]; 1044 u8 tunnel_stateless_gre[0x1]; 1045 u8 tunnel_stateless_vxlan[0x1]; 1046 1047 u8 swp[0x1]; 1048 u8 swp_csum[0x1]; 1049 u8 swp_lso[0x1]; 1050 u8 cqe_checksum_full[0x1]; 1051 u8 tunnel_stateless_geneve_tx[0x1]; 1052 u8 tunnel_stateless_mpls_over_udp[0x1]; 1053 u8 tunnel_stateless_mpls_over_gre[0x1]; 1054 u8 tunnel_stateless_vxlan_gpe[0x1]; 1055 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1056 u8 tunnel_stateless_ip_over_ip[0x1]; 1057 u8 insert_trailer[0x1]; 1058 u8 reserved_at_2b[0x1]; 1059 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1060 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1061 u8 reserved_at_2e[0x2]; 1062 u8 max_vxlan_udp_ports[0x8]; 1063 u8 reserved_at_38[0x6]; 1064 u8 max_geneve_opt_len[0x1]; 1065 u8 tunnel_stateless_geneve_rx[0x1]; 1066 1067 u8 reserved_at_40[0x10]; 1068 u8 lro_min_mss_size[0x10]; 1069 1070 u8 reserved_at_60[0x120]; 1071 1072 u8 lro_timer_supported_periods[4][0x20]; 1073 1074 u8 reserved_at_200[0x600]; 1075 }; 1076 1077 enum { 1078 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1079 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1080 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1081 }; 1082 1083 struct mlx5_ifc_roce_cap_bits { 1084 u8 roce_apm[0x1]; 1085 u8 reserved_at_1[0x3]; 1086 u8 sw_r_roce_src_udp_port[0x1]; 1087 u8 fl_rc_qp_when_roce_disabled[0x1]; 1088 u8 fl_rc_qp_when_roce_enabled[0x1]; 1089 u8 reserved_at_7[0x17]; 1090 u8 qp_ts_format[0x2]; 1091 1092 u8 reserved_at_20[0x60]; 1093 1094 u8 reserved_at_80[0xc]; 1095 u8 l3_type[0x4]; 1096 u8 reserved_at_90[0x8]; 1097 u8 roce_version[0x8]; 1098 1099 u8 reserved_at_a0[0x10]; 1100 u8 r_roce_dest_udp_port[0x10]; 1101 1102 u8 r_roce_max_src_udp_port[0x10]; 1103 u8 r_roce_min_src_udp_port[0x10]; 1104 1105 u8 reserved_at_e0[0x10]; 1106 u8 roce_address_table_size[0x10]; 1107 1108 u8 reserved_at_100[0x700]; 1109 }; 1110 1111 struct mlx5_ifc_sync_steering_in_bits { 1112 u8 opcode[0x10]; 1113 u8 uid[0x10]; 1114 1115 u8 reserved_at_20[0x10]; 1116 u8 op_mod[0x10]; 1117 1118 u8 reserved_at_40[0xc0]; 1119 }; 1120 1121 struct mlx5_ifc_sync_steering_out_bits { 1122 u8 status[0x8]; 1123 u8 reserved_at_8[0x18]; 1124 1125 u8 syndrome[0x20]; 1126 1127 u8 reserved_at_40[0x40]; 1128 }; 1129 1130 struct mlx5_ifc_sync_crypto_in_bits { 1131 u8 opcode[0x10]; 1132 u8 uid[0x10]; 1133 1134 u8 reserved_at_20[0x10]; 1135 u8 op_mod[0x10]; 1136 1137 u8 reserved_at_40[0x20]; 1138 1139 u8 reserved_at_60[0x10]; 1140 u8 crypto_type[0x10]; 1141 1142 u8 reserved_at_80[0x80]; 1143 }; 1144 1145 struct mlx5_ifc_sync_crypto_out_bits { 1146 u8 status[0x8]; 1147 u8 reserved_at_8[0x18]; 1148 1149 u8 syndrome[0x20]; 1150 1151 u8 reserved_at_40[0x40]; 1152 }; 1153 1154 struct mlx5_ifc_device_mem_cap_bits { 1155 u8 memic[0x1]; 1156 u8 reserved_at_1[0x1f]; 1157 1158 u8 reserved_at_20[0xb]; 1159 u8 log_min_memic_alloc_size[0x5]; 1160 u8 reserved_at_30[0x8]; 1161 u8 log_max_memic_addr_alignment[0x8]; 1162 1163 u8 memic_bar_start_addr[0x40]; 1164 1165 u8 memic_bar_size[0x20]; 1166 1167 u8 max_memic_size[0x20]; 1168 1169 u8 steering_sw_icm_start_address[0x40]; 1170 1171 u8 reserved_at_100[0x8]; 1172 u8 log_header_modify_sw_icm_size[0x8]; 1173 u8 reserved_at_110[0x2]; 1174 u8 log_sw_icm_alloc_granularity[0x6]; 1175 u8 log_steering_sw_icm_size[0x8]; 1176 1177 u8 reserved_at_120[0x18]; 1178 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1179 1180 u8 header_modify_sw_icm_start_address[0x40]; 1181 1182 u8 reserved_at_180[0x40]; 1183 1184 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1185 1186 u8 memic_operations[0x20]; 1187 1188 u8 reserved_at_220[0x5e0]; 1189 }; 1190 1191 struct mlx5_ifc_device_event_cap_bits { 1192 u8 user_affiliated_events[4][0x40]; 1193 1194 u8 user_unaffiliated_events[4][0x40]; 1195 }; 1196 1197 struct mlx5_ifc_virtio_emulation_cap_bits { 1198 u8 desc_tunnel_offload_type[0x1]; 1199 u8 eth_frame_offload_type[0x1]; 1200 u8 virtio_version_1_0[0x1]; 1201 u8 device_features_bits_mask[0xd]; 1202 u8 event_mode[0x8]; 1203 u8 virtio_queue_type[0x8]; 1204 1205 u8 max_tunnel_desc[0x10]; 1206 u8 reserved_at_30[0x3]; 1207 u8 log_doorbell_stride[0x5]; 1208 u8 reserved_at_38[0x3]; 1209 u8 log_doorbell_bar_size[0x5]; 1210 1211 u8 doorbell_bar_offset[0x40]; 1212 1213 u8 max_emulated_devices[0x8]; 1214 u8 max_num_virtio_queues[0x18]; 1215 1216 u8 reserved_at_a0[0x60]; 1217 1218 u8 umem_1_buffer_param_a[0x20]; 1219 1220 u8 umem_1_buffer_param_b[0x20]; 1221 1222 u8 umem_2_buffer_param_a[0x20]; 1223 1224 u8 umem_2_buffer_param_b[0x20]; 1225 1226 u8 umem_3_buffer_param_a[0x20]; 1227 1228 u8 umem_3_buffer_param_b[0x20]; 1229 1230 u8 reserved_at_1c0[0x640]; 1231 }; 1232 1233 enum { 1234 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1235 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1236 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1237 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1238 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1239 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1240 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1241 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1242 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1243 }; 1244 1245 enum { 1246 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1247 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1248 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1249 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1255 }; 1256 1257 struct mlx5_ifc_atomic_caps_bits { 1258 u8 reserved_at_0[0x40]; 1259 1260 u8 atomic_req_8B_endianness_mode[0x2]; 1261 u8 reserved_at_42[0x4]; 1262 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1263 1264 u8 reserved_at_47[0x19]; 1265 1266 u8 reserved_at_60[0x20]; 1267 1268 u8 reserved_at_80[0x10]; 1269 u8 atomic_operations[0x10]; 1270 1271 u8 reserved_at_a0[0x10]; 1272 u8 atomic_size_qp[0x10]; 1273 1274 u8 reserved_at_c0[0x10]; 1275 u8 atomic_size_dc[0x10]; 1276 1277 u8 reserved_at_e0[0x720]; 1278 }; 1279 1280 struct mlx5_ifc_odp_cap_bits { 1281 u8 reserved_at_0[0x40]; 1282 1283 u8 sig[0x1]; 1284 u8 reserved_at_41[0x1f]; 1285 1286 u8 reserved_at_60[0x20]; 1287 1288 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1289 1290 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1291 1292 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1293 1294 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1295 1296 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1297 1298 u8 reserved_at_120[0x6E0]; 1299 }; 1300 1301 struct mlx5_ifc_calc_op { 1302 u8 reserved_at_0[0x10]; 1303 u8 reserved_at_10[0x9]; 1304 u8 op_swap_endianness[0x1]; 1305 u8 op_min[0x1]; 1306 u8 op_xor[0x1]; 1307 u8 op_or[0x1]; 1308 u8 op_and[0x1]; 1309 u8 op_max[0x1]; 1310 u8 op_add[0x1]; 1311 }; 1312 1313 struct mlx5_ifc_vector_calc_cap_bits { 1314 u8 calc_matrix[0x1]; 1315 u8 reserved_at_1[0x1f]; 1316 u8 reserved_at_20[0x8]; 1317 u8 max_vec_count[0x8]; 1318 u8 reserved_at_30[0xd]; 1319 u8 max_chunk_size[0x3]; 1320 struct mlx5_ifc_calc_op calc0; 1321 struct mlx5_ifc_calc_op calc1; 1322 struct mlx5_ifc_calc_op calc2; 1323 struct mlx5_ifc_calc_op calc3; 1324 1325 u8 reserved_at_c0[0x720]; 1326 }; 1327 1328 struct mlx5_ifc_tls_cap_bits { 1329 u8 tls_1_2_aes_gcm_128[0x1]; 1330 u8 tls_1_3_aes_gcm_128[0x1]; 1331 u8 tls_1_2_aes_gcm_256[0x1]; 1332 u8 tls_1_3_aes_gcm_256[0x1]; 1333 u8 reserved_at_4[0x1c]; 1334 1335 u8 reserved_at_20[0x7e0]; 1336 }; 1337 1338 struct mlx5_ifc_ipsec_cap_bits { 1339 u8 ipsec_full_offload[0x1]; 1340 u8 ipsec_crypto_offload[0x1]; 1341 u8 ipsec_esn[0x1]; 1342 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1343 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1344 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1345 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1346 u8 reserved_at_7[0x4]; 1347 u8 log_max_ipsec_offload[0x5]; 1348 u8 reserved_at_10[0x10]; 1349 1350 u8 min_log_ipsec_full_replay_window[0x8]; 1351 u8 max_log_ipsec_full_replay_window[0x8]; 1352 u8 reserved_at_30[0x7d0]; 1353 }; 1354 1355 struct mlx5_ifc_macsec_cap_bits { 1356 u8 macsec_epn[0x1]; 1357 u8 reserved_at_1[0x2]; 1358 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1359 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1360 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1361 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1362 u8 reserved_at_7[0x4]; 1363 u8 log_max_macsec_offload[0x5]; 1364 u8 reserved_at_10[0x10]; 1365 1366 u8 min_log_macsec_full_replay_window[0x8]; 1367 u8 max_log_macsec_full_replay_window[0x8]; 1368 u8 reserved_at_30[0x10]; 1369 1370 u8 reserved_at_40[0x7c0]; 1371 }; 1372 1373 enum { 1374 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1375 MLX5_WQ_TYPE_CYCLIC = 0x1, 1376 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1377 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1378 }; 1379 1380 enum { 1381 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1382 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1383 }; 1384 1385 enum { 1386 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1387 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1388 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1389 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1390 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1391 }; 1392 1393 enum { 1394 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1395 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1396 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1397 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1398 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1399 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1400 }; 1401 1402 enum { 1403 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1404 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1405 }; 1406 1407 enum { 1408 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1409 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1410 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1411 }; 1412 1413 enum { 1414 MLX5_CAP_PORT_TYPE_IB = 0x0, 1415 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1416 }; 1417 1418 enum { 1419 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1420 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1421 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1422 }; 1423 1424 enum { 1425 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1426 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1427 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1428 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1429 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1430 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1431 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1432 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1433 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1434 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1435 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1436 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1437 }; 1438 1439 enum { 1440 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1441 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1442 }; 1443 1444 #define MLX5_FC_BULK_SIZE_FACTOR 128 1445 1446 enum mlx5_fc_bulk_alloc_bitmask { 1447 MLX5_FC_BULK_128 = (1 << 0), 1448 MLX5_FC_BULK_256 = (1 << 1), 1449 MLX5_FC_BULK_512 = (1 << 2), 1450 MLX5_FC_BULK_1024 = (1 << 3), 1451 MLX5_FC_BULK_2048 = (1 << 4), 1452 MLX5_FC_BULK_4096 = (1 << 5), 1453 MLX5_FC_BULK_8192 = (1 << 6), 1454 MLX5_FC_BULK_16384 = (1 << 7), 1455 }; 1456 1457 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1458 1459 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1460 1461 enum { 1462 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1463 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1464 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1465 }; 1466 1467 struct mlx5_ifc_cmd_hca_cap_bits { 1468 u8 reserved_at_0[0x10]; 1469 u8 shared_object_to_user_object_allowed[0x1]; 1470 u8 reserved_at_13[0xe]; 1471 u8 vhca_resource_manager[0x1]; 1472 1473 u8 hca_cap_2[0x1]; 1474 u8 create_lag_when_not_master_up[0x1]; 1475 u8 dtor[0x1]; 1476 u8 event_on_vhca_state_teardown_request[0x1]; 1477 u8 event_on_vhca_state_in_use[0x1]; 1478 u8 event_on_vhca_state_active[0x1]; 1479 u8 event_on_vhca_state_allocated[0x1]; 1480 u8 event_on_vhca_state_invalid[0x1]; 1481 u8 reserved_at_28[0x8]; 1482 u8 vhca_id[0x10]; 1483 1484 u8 reserved_at_40[0x40]; 1485 1486 u8 log_max_srq_sz[0x8]; 1487 u8 log_max_qp_sz[0x8]; 1488 u8 event_cap[0x1]; 1489 u8 reserved_at_91[0x2]; 1490 u8 isolate_vl_tc_new[0x1]; 1491 u8 reserved_at_94[0x4]; 1492 u8 prio_tag_required[0x1]; 1493 u8 reserved_at_99[0x2]; 1494 u8 log_max_qp[0x5]; 1495 1496 u8 reserved_at_a0[0x3]; 1497 u8 ece_support[0x1]; 1498 u8 reserved_at_a4[0x5]; 1499 u8 reg_c_preserve[0x1]; 1500 u8 reserved_at_aa[0x1]; 1501 u8 log_max_srq[0x5]; 1502 u8 reserved_at_b0[0x1]; 1503 u8 uplink_follow[0x1]; 1504 u8 ts_cqe_to_dest_cqn[0x1]; 1505 u8 reserved_at_b3[0x7]; 1506 u8 shampo[0x1]; 1507 u8 reserved_at_bb[0x5]; 1508 1509 u8 max_sgl_for_optimized_performance[0x8]; 1510 u8 log_max_cq_sz[0x8]; 1511 u8 relaxed_ordering_write_umr[0x1]; 1512 u8 relaxed_ordering_read_umr[0x1]; 1513 u8 reserved_at_d2[0x7]; 1514 u8 virtio_net_device_emualtion_manager[0x1]; 1515 u8 virtio_blk_device_emualtion_manager[0x1]; 1516 u8 log_max_cq[0x5]; 1517 1518 u8 log_max_eq_sz[0x8]; 1519 u8 relaxed_ordering_write[0x1]; 1520 u8 relaxed_ordering_read[0x1]; 1521 u8 log_max_mkey[0x6]; 1522 u8 reserved_at_f0[0x6]; 1523 u8 terminate_scatter_list_mkey[0x1]; 1524 u8 repeated_mkey[0x1]; 1525 u8 dump_fill_mkey[0x1]; 1526 u8 reserved_at_f9[0x2]; 1527 u8 fast_teardown[0x1]; 1528 u8 log_max_eq[0x4]; 1529 1530 u8 max_indirection[0x8]; 1531 u8 fixed_buffer_size[0x1]; 1532 u8 log_max_mrw_sz[0x7]; 1533 u8 force_teardown[0x1]; 1534 u8 reserved_at_111[0x1]; 1535 u8 log_max_bsf_list_size[0x6]; 1536 u8 umr_extended_translation_offset[0x1]; 1537 u8 null_mkey[0x1]; 1538 u8 log_max_klm_list_size[0x6]; 1539 1540 u8 reserved_at_120[0x2]; 1541 u8 qpc_extension[0x1]; 1542 u8 reserved_at_123[0x7]; 1543 u8 log_max_ra_req_dc[0x6]; 1544 u8 reserved_at_130[0x2]; 1545 u8 eth_wqe_too_small[0x1]; 1546 u8 reserved_at_133[0x6]; 1547 u8 vnic_env_cq_overrun[0x1]; 1548 u8 log_max_ra_res_dc[0x6]; 1549 1550 u8 reserved_at_140[0x5]; 1551 u8 release_all_pages[0x1]; 1552 u8 must_not_use[0x1]; 1553 u8 reserved_at_147[0x2]; 1554 u8 roce_accl[0x1]; 1555 u8 log_max_ra_req_qp[0x6]; 1556 u8 reserved_at_150[0xa]; 1557 u8 log_max_ra_res_qp[0x6]; 1558 1559 u8 end_pad[0x1]; 1560 u8 cc_query_allowed[0x1]; 1561 u8 cc_modify_allowed[0x1]; 1562 u8 start_pad[0x1]; 1563 u8 cache_line_128byte[0x1]; 1564 u8 reserved_at_165[0x4]; 1565 u8 rts2rts_qp_counters_set_id[0x1]; 1566 u8 reserved_at_16a[0x2]; 1567 u8 vnic_env_int_rq_oob[0x1]; 1568 u8 sbcam_reg[0x1]; 1569 u8 reserved_at_16e[0x1]; 1570 u8 qcam_reg[0x1]; 1571 u8 gid_table_size[0x10]; 1572 1573 u8 out_of_seq_cnt[0x1]; 1574 u8 vport_counters[0x1]; 1575 u8 retransmission_q_counters[0x1]; 1576 u8 debug[0x1]; 1577 u8 modify_rq_counter_set_id[0x1]; 1578 u8 rq_delay_drop[0x1]; 1579 u8 max_qp_cnt[0xa]; 1580 u8 pkey_table_size[0x10]; 1581 1582 u8 vport_group_manager[0x1]; 1583 u8 vhca_group_manager[0x1]; 1584 u8 ib_virt[0x1]; 1585 u8 eth_virt[0x1]; 1586 u8 vnic_env_queue_counters[0x1]; 1587 u8 ets[0x1]; 1588 u8 nic_flow_table[0x1]; 1589 u8 eswitch_manager[0x1]; 1590 u8 device_memory[0x1]; 1591 u8 mcam_reg[0x1]; 1592 u8 pcam_reg[0x1]; 1593 u8 local_ca_ack_delay[0x5]; 1594 u8 port_module_event[0x1]; 1595 u8 enhanced_error_q_counters[0x1]; 1596 u8 ports_check[0x1]; 1597 u8 reserved_at_1b3[0x1]; 1598 u8 disable_link_up[0x1]; 1599 u8 beacon_led[0x1]; 1600 u8 port_type[0x2]; 1601 u8 num_ports[0x8]; 1602 1603 u8 reserved_at_1c0[0x1]; 1604 u8 pps[0x1]; 1605 u8 pps_modify[0x1]; 1606 u8 log_max_msg[0x5]; 1607 u8 reserved_at_1c8[0x4]; 1608 u8 max_tc[0x4]; 1609 u8 temp_warn_event[0x1]; 1610 u8 dcbx[0x1]; 1611 u8 general_notification_event[0x1]; 1612 u8 reserved_at_1d3[0x2]; 1613 u8 fpga[0x1]; 1614 u8 rol_s[0x1]; 1615 u8 rol_g[0x1]; 1616 u8 reserved_at_1d8[0x1]; 1617 u8 wol_s[0x1]; 1618 u8 wol_g[0x1]; 1619 u8 wol_a[0x1]; 1620 u8 wol_b[0x1]; 1621 u8 wol_m[0x1]; 1622 u8 wol_u[0x1]; 1623 u8 wol_p[0x1]; 1624 1625 u8 stat_rate_support[0x10]; 1626 u8 reserved_at_1f0[0x1]; 1627 u8 pci_sync_for_fw_update_event[0x1]; 1628 u8 reserved_at_1f2[0x6]; 1629 u8 init2_lag_tx_port_affinity[0x1]; 1630 u8 reserved_at_1fa[0x3]; 1631 u8 cqe_version[0x4]; 1632 1633 u8 compact_address_vector[0x1]; 1634 u8 striding_rq[0x1]; 1635 u8 reserved_at_202[0x1]; 1636 u8 ipoib_enhanced_offloads[0x1]; 1637 u8 ipoib_basic_offloads[0x1]; 1638 u8 reserved_at_205[0x1]; 1639 u8 repeated_block_disabled[0x1]; 1640 u8 umr_modify_entity_size_disabled[0x1]; 1641 u8 umr_modify_atomic_disabled[0x1]; 1642 u8 umr_indirect_mkey_disabled[0x1]; 1643 u8 umr_fence[0x2]; 1644 u8 dc_req_scat_data_cqe[0x1]; 1645 u8 reserved_at_20d[0x2]; 1646 u8 drain_sigerr[0x1]; 1647 u8 cmdif_checksum[0x2]; 1648 u8 sigerr_cqe[0x1]; 1649 u8 reserved_at_213[0x1]; 1650 u8 wq_signature[0x1]; 1651 u8 sctr_data_cqe[0x1]; 1652 u8 reserved_at_216[0x1]; 1653 u8 sho[0x1]; 1654 u8 tph[0x1]; 1655 u8 rf[0x1]; 1656 u8 dct[0x1]; 1657 u8 qos[0x1]; 1658 u8 eth_net_offloads[0x1]; 1659 u8 roce[0x1]; 1660 u8 atomic[0x1]; 1661 u8 reserved_at_21f[0x1]; 1662 1663 u8 cq_oi[0x1]; 1664 u8 cq_resize[0x1]; 1665 u8 cq_moderation[0x1]; 1666 u8 reserved_at_223[0x3]; 1667 u8 cq_eq_remap[0x1]; 1668 u8 pg[0x1]; 1669 u8 block_lb_mc[0x1]; 1670 u8 reserved_at_229[0x1]; 1671 u8 scqe_break_moderation[0x1]; 1672 u8 cq_period_start_from_cqe[0x1]; 1673 u8 cd[0x1]; 1674 u8 reserved_at_22d[0x1]; 1675 u8 apm[0x1]; 1676 u8 vector_calc[0x1]; 1677 u8 umr_ptr_rlky[0x1]; 1678 u8 imaicl[0x1]; 1679 u8 qp_packet_based[0x1]; 1680 u8 reserved_at_233[0x3]; 1681 u8 qkv[0x1]; 1682 u8 pkv[0x1]; 1683 u8 set_deth_sqpn[0x1]; 1684 u8 reserved_at_239[0x3]; 1685 u8 xrc[0x1]; 1686 u8 ud[0x1]; 1687 u8 uc[0x1]; 1688 u8 rc[0x1]; 1689 1690 u8 uar_4k[0x1]; 1691 u8 reserved_at_241[0x9]; 1692 u8 uar_sz[0x6]; 1693 u8 port_selection_cap[0x1]; 1694 u8 reserved_at_248[0x1]; 1695 u8 umem_uid_0[0x1]; 1696 u8 reserved_at_250[0x5]; 1697 u8 log_pg_sz[0x8]; 1698 1699 u8 bf[0x1]; 1700 u8 driver_version[0x1]; 1701 u8 pad_tx_eth_packet[0x1]; 1702 u8 reserved_at_263[0x3]; 1703 u8 mkey_by_name[0x1]; 1704 u8 reserved_at_267[0x4]; 1705 1706 u8 log_bf_reg_size[0x5]; 1707 1708 u8 reserved_at_270[0x3]; 1709 u8 qp_error_syndrome[0x1]; 1710 u8 reserved_at_274[0x2]; 1711 u8 lag_dct[0x2]; 1712 u8 lag_tx_port_affinity[0x1]; 1713 u8 lag_native_fdb_selection[0x1]; 1714 u8 reserved_at_27a[0x1]; 1715 u8 lag_master[0x1]; 1716 u8 num_lag_ports[0x4]; 1717 1718 u8 reserved_at_280[0x10]; 1719 u8 max_wqe_sz_sq[0x10]; 1720 1721 u8 reserved_at_2a0[0x10]; 1722 u8 max_wqe_sz_rq[0x10]; 1723 1724 u8 max_flow_counter_31_16[0x10]; 1725 u8 max_wqe_sz_sq_dc[0x10]; 1726 1727 u8 reserved_at_2e0[0x7]; 1728 u8 max_qp_mcg[0x19]; 1729 1730 u8 reserved_at_300[0x10]; 1731 u8 flow_counter_bulk_alloc[0x8]; 1732 u8 log_max_mcg[0x8]; 1733 1734 u8 reserved_at_320[0x3]; 1735 u8 log_max_transport_domain[0x5]; 1736 u8 reserved_at_328[0x3]; 1737 u8 log_max_pd[0x5]; 1738 u8 reserved_at_330[0xb]; 1739 u8 log_max_xrcd[0x5]; 1740 1741 u8 nic_receive_steering_discard[0x1]; 1742 u8 receive_discard_vport_down[0x1]; 1743 u8 transmit_discard_vport_down[0x1]; 1744 u8 eq_overrun_count[0x1]; 1745 u8 reserved_at_344[0x1]; 1746 u8 invalid_command_count[0x1]; 1747 u8 quota_exceeded_count[0x1]; 1748 u8 reserved_at_347[0x1]; 1749 u8 log_max_flow_counter_bulk[0x8]; 1750 u8 max_flow_counter_15_0[0x10]; 1751 1752 1753 u8 reserved_at_360[0x3]; 1754 u8 log_max_rq[0x5]; 1755 u8 reserved_at_368[0x3]; 1756 u8 log_max_sq[0x5]; 1757 u8 reserved_at_370[0x3]; 1758 u8 log_max_tir[0x5]; 1759 u8 reserved_at_378[0x3]; 1760 u8 log_max_tis[0x5]; 1761 1762 u8 basic_cyclic_rcv_wqe[0x1]; 1763 u8 reserved_at_381[0x2]; 1764 u8 log_max_rmp[0x5]; 1765 u8 reserved_at_388[0x3]; 1766 u8 log_max_rqt[0x5]; 1767 u8 reserved_at_390[0x3]; 1768 u8 log_max_rqt_size[0x5]; 1769 u8 reserved_at_398[0x3]; 1770 u8 log_max_tis_per_sq[0x5]; 1771 1772 u8 ext_stride_num_range[0x1]; 1773 u8 roce_rw_supported[0x1]; 1774 u8 log_max_current_uc_list_wr_supported[0x1]; 1775 u8 log_max_stride_sz_rq[0x5]; 1776 u8 reserved_at_3a8[0x3]; 1777 u8 log_min_stride_sz_rq[0x5]; 1778 u8 reserved_at_3b0[0x3]; 1779 u8 log_max_stride_sz_sq[0x5]; 1780 u8 reserved_at_3b8[0x3]; 1781 u8 log_min_stride_sz_sq[0x5]; 1782 1783 u8 hairpin[0x1]; 1784 u8 reserved_at_3c1[0x2]; 1785 u8 log_max_hairpin_queues[0x5]; 1786 u8 reserved_at_3c8[0x3]; 1787 u8 log_max_hairpin_wq_data_sz[0x5]; 1788 u8 reserved_at_3d0[0x3]; 1789 u8 log_max_hairpin_num_packets[0x5]; 1790 u8 reserved_at_3d8[0x3]; 1791 u8 log_max_wq_sz[0x5]; 1792 1793 u8 nic_vport_change_event[0x1]; 1794 u8 disable_local_lb_uc[0x1]; 1795 u8 disable_local_lb_mc[0x1]; 1796 u8 log_min_hairpin_wq_data_sz[0x5]; 1797 u8 reserved_at_3e8[0x2]; 1798 u8 vhca_state[0x1]; 1799 u8 log_max_vlan_list[0x5]; 1800 u8 reserved_at_3f0[0x3]; 1801 u8 log_max_current_mc_list[0x5]; 1802 u8 reserved_at_3f8[0x3]; 1803 u8 log_max_current_uc_list[0x5]; 1804 1805 u8 general_obj_types[0x40]; 1806 1807 u8 sq_ts_format[0x2]; 1808 u8 rq_ts_format[0x2]; 1809 u8 steering_format_version[0x4]; 1810 u8 create_qp_start_hint[0x18]; 1811 1812 u8 reserved_at_460[0x1]; 1813 u8 ats[0x1]; 1814 u8 reserved_at_462[0x1]; 1815 u8 log_max_uctx[0x5]; 1816 u8 reserved_at_468[0x1]; 1817 u8 crypto[0x1]; 1818 u8 ipsec_offload[0x1]; 1819 u8 log_max_umem[0x5]; 1820 u8 max_num_eqs[0x10]; 1821 1822 u8 reserved_at_480[0x1]; 1823 u8 tls_tx[0x1]; 1824 u8 tls_rx[0x1]; 1825 u8 log_max_l2_table[0x5]; 1826 u8 reserved_at_488[0x8]; 1827 u8 log_uar_page_sz[0x10]; 1828 1829 u8 reserved_at_4a0[0x20]; 1830 u8 device_frequency_mhz[0x20]; 1831 u8 device_frequency_khz[0x20]; 1832 1833 u8 reserved_at_500[0x20]; 1834 u8 num_of_uars_per_page[0x20]; 1835 1836 u8 flex_parser_protocols[0x20]; 1837 1838 u8 max_geneve_tlv_options[0x8]; 1839 u8 reserved_at_568[0x3]; 1840 u8 max_geneve_tlv_option_data_len[0x5]; 1841 u8 reserved_at_570[0x9]; 1842 u8 adv_virtualization[0x1]; 1843 u8 reserved_at_57a[0x6]; 1844 1845 u8 reserved_at_580[0xb]; 1846 u8 log_max_dci_stream_channels[0x5]; 1847 u8 reserved_at_590[0x3]; 1848 u8 log_max_dci_errored_streams[0x5]; 1849 u8 reserved_at_598[0x8]; 1850 1851 u8 reserved_at_5a0[0x10]; 1852 u8 enhanced_cqe_compression[0x1]; 1853 u8 reserved_at_5b1[0x2]; 1854 u8 log_max_dek[0x5]; 1855 u8 reserved_at_5b8[0x4]; 1856 u8 mini_cqe_resp_stride_index[0x1]; 1857 u8 cqe_128_always[0x1]; 1858 u8 cqe_compression_128[0x1]; 1859 u8 cqe_compression[0x1]; 1860 1861 u8 cqe_compression_timeout[0x10]; 1862 u8 cqe_compression_max_num[0x10]; 1863 1864 u8 reserved_at_5e0[0x8]; 1865 u8 flex_parser_id_gtpu_dw_0[0x4]; 1866 u8 reserved_at_5ec[0x4]; 1867 u8 tag_matching[0x1]; 1868 u8 rndv_offload_rc[0x1]; 1869 u8 rndv_offload_dc[0x1]; 1870 u8 log_tag_matching_list_sz[0x5]; 1871 u8 reserved_at_5f8[0x3]; 1872 u8 log_max_xrq[0x5]; 1873 1874 u8 affiliate_nic_vport_criteria[0x8]; 1875 u8 native_port_num[0x8]; 1876 u8 num_vhca_ports[0x8]; 1877 u8 flex_parser_id_gtpu_teid[0x4]; 1878 u8 reserved_at_61c[0x2]; 1879 u8 sw_owner_id[0x1]; 1880 u8 reserved_at_61f[0x1]; 1881 1882 u8 max_num_of_monitor_counters[0x10]; 1883 u8 num_ppcnt_monitor_counters[0x10]; 1884 1885 u8 max_num_sf[0x10]; 1886 u8 num_q_monitor_counters[0x10]; 1887 1888 u8 reserved_at_660[0x20]; 1889 1890 u8 sf[0x1]; 1891 u8 sf_set_partition[0x1]; 1892 u8 reserved_at_682[0x1]; 1893 u8 log_max_sf[0x5]; 1894 u8 apu[0x1]; 1895 u8 reserved_at_689[0x4]; 1896 u8 migration[0x1]; 1897 u8 reserved_at_68e[0x2]; 1898 u8 log_min_sf_size[0x8]; 1899 u8 max_num_sf_partitions[0x8]; 1900 1901 u8 uctx_cap[0x20]; 1902 1903 u8 reserved_at_6c0[0x4]; 1904 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1905 u8 flex_parser_id_icmp_dw1[0x4]; 1906 u8 flex_parser_id_icmp_dw0[0x4]; 1907 u8 flex_parser_id_icmpv6_dw1[0x4]; 1908 u8 flex_parser_id_icmpv6_dw0[0x4]; 1909 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1910 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1911 1912 u8 max_num_match_definer[0x10]; 1913 u8 sf_base_id[0x10]; 1914 1915 u8 flex_parser_id_gtpu_dw_2[0x4]; 1916 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1917 u8 num_total_dynamic_vf_msix[0x18]; 1918 u8 reserved_at_720[0x14]; 1919 u8 dynamic_msix_table_size[0xc]; 1920 u8 reserved_at_740[0xc]; 1921 u8 min_dynamic_vf_msix_table_size[0x4]; 1922 u8 reserved_at_750[0x4]; 1923 u8 max_dynamic_vf_msix_table_size[0xc]; 1924 1925 u8 reserved_at_760[0x20]; 1926 u8 vhca_tunnel_commands[0x40]; 1927 u8 match_definer_format_supported[0x40]; 1928 }; 1929 1930 struct mlx5_ifc_cmd_hca_cap_2_bits { 1931 u8 reserved_at_0[0x80]; 1932 1933 u8 migratable[0x1]; 1934 u8 reserved_at_81[0x1f]; 1935 1936 u8 max_reformat_insert_size[0x8]; 1937 u8 max_reformat_insert_offset[0x8]; 1938 u8 max_reformat_remove_size[0x8]; 1939 u8 max_reformat_remove_offset[0x8]; 1940 1941 u8 reserved_at_c0[0x8]; 1942 u8 migration_multi_load[0x1]; 1943 u8 migration_tracking_state[0x1]; 1944 u8 reserved_at_ca[0x16]; 1945 1946 u8 reserved_at_e0[0xc0]; 1947 1948 u8 flow_table_type_2_type[0x8]; 1949 u8 reserved_at_1a8[0x3]; 1950 u8 log_min_mkey_entity_size[0x5]; 1951 u8 reserved_at_1b0[0x10]; 1952 1953 u8 reserved_at_1c0[0x60]; 1954 1955 u8 reserved_at_220[0x1]; 1956 u8 sw_vhca_id_valid[0x1]; 1957 u8 sw_vhca_id[0xe]; 1958 u8 reserved_at_230[0x10]; 1959 1960 u8 reserved_at_240[0xb]; 1961 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1962 u8 reserved_at_250[0x10]; 1963 1964 u8 reserved_at_260[0x5a0]; 1965 }; 1966 1967 enum mlx5_ifc_flow_destination_type { 1968 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1969 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1970 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1971 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1972 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1973 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1974 }; 1975 1976 enum mlx5_flow_table_miss_action { 1977 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1978 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1979 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1980 }; 1981 1982 struct mlx5_ifc_dest_format_struct_bits { 1983 u8 destination_type[0x8]; 1984 u8 destination_id[0x18]; 1985 1986 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1987 u8 packet_reformat[0x1]; 1988 u8 reserved_at_22[0x6]; 1989 u8 destination_table_type[0x8]; 1990 u8 destination_eswitch_owner_vhca_id[0x10]; 1991 }; 1992 1993 struct mlx5_ifc_flow_counter_list_bits { 1994 u8 flow_counter_id[0x20]; 1995 1996 u8 reserved_at_20[0x20]; 1997 }; 1998 1999 struct mlx5_ifc_extended_dest_format_bits { 2000 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2001 2002 u8 packet_reformat_id[0x20]; 2003 2004 u8 reserved_at_60[0x20]; 2005 }; 2006 2007 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2008 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2009 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2010 }; 2011 2012 struct mlx5_ifc_fte_match_param_bits { 2013 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2014 2015 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2016 2017 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2018 2019 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2020 2021 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2022 2023 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2024 2025 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2026 2027 u8 reserved_at_e00[0x200]; 2028 }; 2029 2030 enum { 2031 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2032 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2033 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2034 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2035 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2036 }; 2037 2038 struct mlx5_ifc_rx_hash_field_select_bits { 2039 u8 l3_prot_type[0x1]; 2040 u8 l4_prot_type[0x1]; 2041 u8 selected_fields[0x1e]; 2042 }; 2043 2044 enum { 2045 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2046 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2047 }; 2048 2049 enum { 2050 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2051 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2052 }; 2053 2054 struct mlx5_ifc_wq_bits { 2055 u8 wq_type[0x4]; 2056 u8 wq_signature[0x1]; 2057 u8 end_padding_mode[0x2]; 2058 u8 cd_slave[0x1]; 2059 u8 reserved_at_8[0x18]; 2060 2061 u8 hds_skip_first_sge[0x1]; 2062 u8 log2_hds_buf_size[0x3]; 2063 u8 reserved_at_24[0x7]; 2064 u8 page_offset[0x5]; 2065 u8 lwm[0x10]; 2066 2067 u8 reserved_at_40[0x8]; 2068 u8 pd[0x18]; 2069 2070 u8 reserved_at_60[0x8]; 2071 u8 uar_page[0x18]; 2072 2073 u8 dbr_addr[0x40]; 2074 2075 u8 hw_counter[0x20]; 2076 2077 u8 sw_counter[0x20]; 2078 2079 u8 reserved_at_100[0xc]; 2080 u8 log_wq_stride[0x4]; 2081 u8 reserved_at_110[0x3]; 2082 u8 log_wq_pg_sz[0x5]; 2083 u8 reserved_at_118[0x3]; 2084 u8 log_wq_sz[0x5]; 2085 2086 u8 dbr_umem_valid[0x1]; 2087 u8 wq_umem_valid[0x1]; 2088 u8 reserved_at_122[0x1]; 2089 u8 log_hairpin_num_packets[0x5]; 2090 u8 reserved_at_128[0x3]; 2091 u8 log_hairpin_data_sz[0x5]; 2092 2093 u8 reserved_at_130[0x4]; 2094 u8 log_wqe_num_of_strides[0x4]; 2095 u8 two_byte_shift_en[0x1]; 2096 u8 reserved_at_139[0x4]; 2097 u8 log_wqe_stride_size[0x3]; 2098 2099 u8 reserved_at_140[0x80]; 2100 2101 u8 headers_mkey[0x20]; 2102 2103 u8 shampo_enable[0x1]; 2104 u8 reserved_at_1e1[0x4]; 2105 u8 log_reservation_size[0x3]; 2106 u8 reserved_at_1e8[0x5]; 2107 u8 log_max_num_of_packets_per_reservation[0x3]; 2108 u8 reserved_at_1f0[0x6]; 2109 u8 log_headers_entry_size[0x2]; 2110 u8 reserved_at_1f8[0x4]; 2111 u8 log_headers_buffer_entry_num[0x4]; 2112 2113 u8 reserved_at_200[0x400]; 2114 2115 struct mlx5_ifc_cmd_pas_bits pas[]; 2116 }; 2117 2118 struct mlx5_ifc_rq_num_bits { 2119 u8 reserved_at_0[0x8]; 2120 u8 rq_num[0x18]; 2121 }; 2122 2123 struct mlx5_ifc_mac_address_layout_bits { 2124 u8 reserved_at_0[0x10]; 2125 u8 mac_addr_47_32[0x10]; 2126 2127 u8 mac_addr_31_0[0x20]; 2128 }; 2129 2130 struct mlx5_ifc_vlan_layout_bits { 2131 u8 reserved_at_0[0x14]; 2132 u8 vlan[0x0c]; 2133 2134 u8 reserved_at_20[0x20]; 2135 }; 2136 2137 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2138 u8 reserved_at_0[0xa0]; 2139 2140 u8 min_time_between_cnps[0x20]; 2141 2142 u8 reserved_at_c0[0x12]; 2143 u8 cnp_dscp[0x6]; 2144 u8 reserved_at_d8[0x4]; 2145 u8 cnp_prio_mode[0x1]; 2146 u8 cnp_802p_prio[0x3]; 2147 2148 u8 reserved_at_e0[0x720]; 2149 }; 2150 2151 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2152 u8 reserved_at_0[0x60]; 2153 2154 u8 reserved_at_60[0x4]; 2155 u8 clamp_tgt_rate[0x1]; 2156 u8 reserved_at_65[0x3]; 2157 u8 clamp_tgt_rate_after_time_inc[0x1]; 2158 u8 reserved_at_69[0x17]; 2159 2160 u8 reserved_at_80[0x20]; 2161 2162 u8 rpg_time_reset[0x20]; 2163 2164 u8 rpg_byte_reset[0x20]; 2165 2166 u8 rpg_threshold[0x20]; 2167 2168 u8 rpg_max_rate[0x20]; 2169 2170 u8 rpg_ai_rate[0x20]; 2171 2172 u8 rpg_hai_rate[0x20]; 2173 2174 u8 rpg_gd[0x20]; 2175 2176 u8 rpg_min_dec_fac[0x20]; 2177 2178 u8 rpg_min_rate[0x20]; 2179 2180 u8 reserved_at_1c0[0xe0]; 2181 2182 u8 rate_to_set_on_first_cnp[0x20]; 2183 2184 u8 dce_tcp_g[0x20]; 2185 2186 u8 dce_tcp_rtt[0x20]; 2187 2188 u8 rate_reduce_monitor_period[0x20]; 2189 2190 u8 reserved_at_320[0x20]; 2191 2192 u8 initial_alpha_value[0x20]; 2193 2194 u8 reserved_at_360[0x4a0]; 2195 }; 2196 2197 struct mlx5_ifc_cong_control_r_roce_general_bits { 2198 u8 reserved_at_0[0x80]; 2199 2200 u8 reserved_at_80[0x10]; 2201 u8 rtt_resp_dscp_valid[0x1]; 2202 u8 reserved_at_91[0x9]; 2203 u8 rtt_resp_dscp[0x6]; 2204 2205 u8 reserved_at_a0[0x760]; 2206 }; 2207 2208 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2209 u8 reserved_at_0[0x80]; 2210 2211 u8 rppp_max_rps[0x20]; 2212 2213 u8 rpg_time_reset[0x20]; 2214 2215 u8 rpg_byte_reset[0x20]; 2216 2217 u8 rpg_threshold[0x20]; 2218 2219 u8 rpg_max_rate[0x20]; 2220 2221 u8 rpg_ai_rate[0x20]; 2222 2223 u8 rpg_hai_rate[0x20]; 2224 2225 u8 rpg_gd[0x20]; 2226 2227 u8 rpg_min_dec_fac[0x20]; 2228 2229 u8 rpg_min_rate[0x20]; 2230 2231 u8 reserved_at_1c0[0x640]; 2232 }; 2233 2234 enum { 2235 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2236 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2237 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2238 }; 2239 2240 struct mlx5_ifc_resize_field_select_bits { 2241 u8 resize_field_select[0x20]; 2242 }; 2243 2244 struct mlx5_ifc_resource_dump_bits { 2245 u8 more_dump[0x1]; 2246 u8 inline_dump[0x1]; 2247 u8 reserved_at_2[0xa]; 2248 u8 seq_num[0x4]; 2249 u8 segment_type[0x10]; 2250 2251 u8 reserved_at_20[0x10]; 2252 u8 vhca_id[0x10]; 2253 2254 u8 index1[0x20]; 2255 2256 u8 index2[0x20]; 2257 2258 u8 num_of_obj1[0x10]; 2259 u8 num_of_obj2[0x10]; 2260 2261 u8 reserved_at_a0[0x20]; 2262 2263 u8 device_opaque[0x40]; 2264 2265 u8 mkey[0x20]; 2266 2267 u8 size[0x20]; 2268 2269 u8 address[0x40]; 2270 2271 u8 inline_data[52][0x20]; 2272 }; 2273 2274 struct mlx5_ifc_resource_dump_menu_record_bits { 2275 u8 reserved_at_0[0x4]; 2276 u8 num_of_obj2_supports_active[0x1]; 2277 u8 num_of_obj2_supports_all[0x1]; 2278 u8 must_have_num_of_obj2[0x1]; 2279 u8 support_num_of_obj2[0x1]; 2280 u8 num_of_obj1_supports_active[0x1]; 2281 u8 num_of_obj1_supports_all[0x1]; 2282 u8 must_have_num_of_obj1[0x1]; 2283 u8 support_num_of_obj1[0x1]; 2284 u8 must_have_index2[0x1]; 2285 u8 support_index2[0x1]; 2286 u8 must_have_index1[0x1]; 2287 u8 support_index1[0x1]; 2288 u8 segment_type[0x10]; 2289 2290 u8 segment_name[4][0x20]; 2291 2292 u8 index1_name[4][0x20]; 2293 2294 u8 index2_name[4][0x20]; 2295 }; 2296 2297 struct mlx5_ifc_resource_dump_segment_header_bits { 2298 u8 length_dw[0x10]; 2299 u8 segment_type[0x10]; 2300 }; 2301 2302 struct mlx5_ifc_resource_dump_command_segment_bits { 2303 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2304 2305 u8 segment_called[0x10]; 2306 u8 vhca_id[0x10]; 2307 2308 u8 index1[0x20]; 2309 2310 u8 index2[0x20]; 2311 2312 u8 num_of_obj1[0x10]; 2313 u8 num_of_obj2[0x10]; 2314 }; 2315 2316 struct mlx5_ifc_resource_dump_error_segment_bits { 2317 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2318 2319 u8 reserved_at_20[0x10]; 2320 u8 syndrome_id[0x10]; 2321 2322 u8 reserved_at_40[0x40]; 2323 2324 u8 error[8][0x20]; 2325 }; 2326 2327 struct mlx5_ifc_resource_dump_info_segment_bits { 2328 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2329 2330 u8 reserved_at_20[0x18]; 2331 u8 dump_version[0x8]; 2332 2333 u8 hw_version[0x20]; 2334 2335 u8 fw_version[0x20]; 2336 }; 2337 2338 struct mlx5_ifc_resource_dump_menu_segment_bits { 2339 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2340 2341 u8 reserved_at_20[0x10]; 2342 u8 num_of_records[0x10]; 2343 2344 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2345 }; 2346 2347 struct mlx5_ifc_resource_dump_resource_segment_bits { 2348 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2349 2350 u8 reserved_at_20[0x20]; 2351 2352 u8 index1[0x20]; 2353 2354 u8 index2[0x20]; 2355 2356 u8 payload[][0x20]; 2357 }; 2358 2359 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2360 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2361 }; 2362 2363 struct mlx5_ifc_menu_resource_dump_response_bits { 2364 struct mlx5_ifc_resource_dump_info_segment_bits info; 2365 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2366 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2367 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2368 }; 2369 2370 enum { 2371 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2372 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2373 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2374 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2375 }; 2376 2377 struct mlx5_ifc_modify_field_select_bits { 2378 u8 modify_field_select[0x20]; 2379 }; 2380 2381 struct mlx5_ifc_field_select_r_roce_np_bits { 2382 u8 field_select_r_roce_np[0x20]; 2383 }; 2384 2385 struct mlx5_ifc_field_select_r_roce_rp_bits { 2386 u8 field_select_r_roce_rp[0x20]; 2387 }; 2388 2389 enum { 2390 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2391 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2392 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2393 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2394 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2395 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2396 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2397 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2398 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2399 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2400 }; 2401 2402 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2403 u8 field_select_8021qaurp[0x20]; 2404 }; 2405 2406 struct mlx5_ifc_phys_layer_cntrs_bits { 2407 u8 time_since_last_clear_high[0x20]; 2408 2409 u8 time_since_last_clear_low[0x20]; 2410 2411 u8 symbol_errors_high[0x20]; 2412 2413 u8 symbol_errors_low[0x20]; 2414 2415 u8 sync_headers_errors_high[0x20]; 2416 2417 u8 sync_headers_errors_low[0x20]; 2418 2419 u8 edpl_bip_errors_lane0_high[0x20]; 2420 2421 u8 edpl_bip_errors_lane0_low[0x20]; 2422 2423 u8 edpl_bip_errors_lane1_high[0x20]; 2424 2425 u8 edpl_bip_errors_lane1_low[0x20]; 2426 2427 u8 edpl_bip_errors_lane2_high[0x20]; 2428 2429 u8 edpl_bip_errors_lane2_low[0x20]; 2430 2431 u8 edpl_bip_errors_lane3_high[0x20]; 2432 2433 u8 edpl_bip_errors_lane3_low[0x20]; 2434 2435 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2436 2437 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2438 2439 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2440 2441 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2442 2443 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2444 2445 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2446 2447 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2448 2449 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2450 2451 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2452 2453 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2454 2455 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2456 2457 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2458 2459 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2460 2461 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2462 2463 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2464 2465 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2466 2467 u8 rs_fec_corrected_blocks_high[0x20]; 2468 2469 u8 rs_fec_corrected_blocks_low[0x20]; 2470 2471 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2472 2473 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2474 2475 u8 rs_fec_no_errors_blocks_high[0x20]; 2476 2477 u8 rs_fec_no_errors_blocks_low[0x20]; 2478 2479 u8 rs_fec_single_error_blocks_high[0x20]; 2480 2481 u8 rs_fec_single_error_blocks_low[0x20]; 2482 2483 u8 rs_fec_corrected_symbols_total_high[0x20]; 2484 2485 u8 rs_fec_corrected_symbols_total_low[0x20]; 2486 2487 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2488 2489 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2490 2491 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2492 2493 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2494 2495 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2496 2497 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2498 2499 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2500 2501 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2502 2503 u8 link_down_events[0x20]; 2504 2505 u8 successful_recovery_events[0x20]; 2506 2507 u8 reserved_at_640[0x180]; 2508 }; 2509 2510 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2511 u8 time_since_last_clear_high[0x20]; 2512 2513 u8 time_since_last_clear_low[0x20]; 2514 2515 u8 phy_received_bits_high[0x20]; 2516 2517 u8 phy_received_bits_low[0x20]; 2518 2519 u8 phy_symbol_errors_high[0x20]; 2520 2521 u8 phy_symbol_errors_low[0x20]; 2522 2523 u8 phy_corrected_bits_high[0x20]; 2524 2525 u8 phy_corrected_bits_low[0x20]; 2526 2527 u8 phy_corrected_bits_lane0_high[0x20]; 2528 2529 u8 phy_corrected_bits_lane0_low[0x20]; 2530 2531 u8 phy_corrected_bits_lane1_high[0x20]; 2532 2533 u8 phy_corrected_bits_lane1_low[0x20]; 2534 2535 u8 phy_corrected_bits_lane2_high[0x20]; 2536 2537 u8 phy_corrected_bits_lane2_low[0x20]; 2538 2539 u8 phy_corrected_bits_lane3_high[0x20]; 2540 2541 u8 phy_corrected_bits_lane3_low[0x20]; 2542 2543 u8 reserved_at_200[0x5c0]; 2544 }; 2545 2546 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2547 u8 symbol_error_counter[0x10]; 2548 2549 u8 link_error_recovery_counter[0x8]; 2550 2551 u8 link_downed_counter[0x8]; 2552 2553 u8 port_rcv_errors[0x10]; 2554 2555 u8 port_rcv_remote_physical_errors[0x10]; 2556 2557 u8 port_rcv_switch_relay_errors[0x10]; 2558 2559 u8 port_xmit_discards[0x10]; 2560 2561 u8 port_xmit_constraint_errors[0x8]; 2562 2563 u8 port_rcv_constraint_errors[0x8]; 2564 2565 u8 reserved_at_70[0x8]; 2566 2567 u8 link_overrun_errors[0x8]; 2568 2569 u8 reserved_at_80[0x10]; 2570 2571 u8 vl_15_dropped[0x10]; 2572 2573 u8 reserved_at_a0[0x80]; 2574 2575 u8 port_xmit_wait[0x20]; 2576 }; 2577 2578 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2579 u8 transmit_queue_high[0x20]; 2580 2581 u8 transmit_queue_low[0x20]; 2582 2583 u8 no_buffer_discard_uc_high[0x20]; 2584 2585 u8 no_buffer_discard_uc_low[0x20]; 2586 2587 u8 reserved_at_80[0x740]; 2588 }; 2589 2590 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2591 u8 wred_discard_high[0x20]; 2592 2593 u8 wred_discard_low[0x20]; 2594 2595 u8 ecn_marked_tc_high[0x20]; 2596 2597 u8 ecn_marked_tc_low[0x20]; 2598 2599 u8 reserved_at_80[0x740]; 2600 }; 2601 2602 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2603 u8 rx_octets_high[0x20]; 2604 2605 u8 rx_octets_low[0x20]; 2606 2607 u8 reserved_at_40[0xc0]; 2608 2609 u8 rx_frames_high[0x20]; 2610 2611 u8 rx_frames_low[0x20]; 2612 2613 u8 tx_octets_high[0x20]; 2614 2615 u8 tx_octets_low[0x20]; 2616 2617 u8 reserved_at_180[0xc0]; 2618 2619 u8 tx_frames_high[0x20]; 2620 2621 u8 tx_frames_low[0x20]; 2622 2623 u8 rx_pause_high[0x20]; 2624 2625 u8 rx_pause_low[0x20]; 2626 2627 u8 rx_pause_duration_high[0x20]; 2628 2629 u8 rx_pause_duration_low[0x20]; 2630 2631 u8 tx_pause_high[0x20]; 2632 2633 u8 tx_pause_low[0x20]; 2634 2635 u8 tx_pause_duration_high[0x20]; 2636 2637 u8 tx_pause_duration_low[0x20]; 2638 2639 u8 rx_pause_transition_high[0x20]; 2640 2641 u8 rx_pause_transition_low[0x20]; 2642 2643 u8 rx_discards_high[0x20]; 2644 2645 u8 rx_discards_low[0x20]; 2646 2647 u8 device_stall_minor_watermark_cnt_high[0x20]; 2648 2649 u8 device_stall_minor_watermark_cnt_low[0x20]; 2650 2651 u8 device_stall_critical_watermark_cnt_high[0x20]; 2652 2653 u8 device_stall_critical_watermark_cnt_low[0x20]; 2654 2655 u8 reserved_at_480[0x340]; 2656 }; 2657 2658 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2659 u8 port_transmit_wait_high[0x20]; 2660 2661 u8 port_transmit_wait_low[0x20]; 2662 2663 u8 reserved_at_40[0x100]; 2664 2665 u8 rx_buffer_almost_full_high[0x20]; 2666 2667 u8 rx_buffer_almost_full_low[0x20]; 2668 2669 u8 rx_buffer_full_high[0x20]; 2670 2671 u8 rx_buffer_full_low[0x20]; 2672 2673 u8 rx_icrc_encapsulated_high[0x20]; 2674 2675 u8 rx_icrc_encapsulated_low[0x20]; 2676 2677 u8 reserved_at_200[0x5c0]; 2678 }; 2679 2680 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2681 u8 dot3stats_alignment_errors_high[0x20]; 2682 2683 u8 dot3stats_alignment_errors_low[0x20]; 2684 2685 u8 dot3stats_fcs_errors_high[0x20]; 2686 2687 u8 dot3stats_fcs_errors_low[0x20]; 2688 2689 u8 dot3stats_single_collision_frames_high[0x20]; 2690 2691 u8 dot3stats_single_collision_frames_low[0x20]; 2692 2693 u8 dot3stats_multiple_collision_frames_high[0x20]; 2694 2695 u8 dot3stats_multiple_collision_frames_low[0x20]; 2696 2697 u8 dot3stats_sqe_test_errors_high[0x20]; 2698 2699 u8 dot3stats_sqe_test_errors_low[0x20]; 2700 2701 u8 dot3stats_deferred_transmissions_high[0x20]; 2702 2703 u8 dot3stats_deferred_transmissions_low[0x20]; 2704 2705 u8 dot3stats_late_collisions_high[0x20]; 2706 2707 u8 dot3stats_late_collisions_low[0x20]; 2708 2709 u8 dot3stats_excessive_collisions_high[0x20]; 2710 2711 u8 dot3stats_excessive_collisions_low[0x20]; 2712 2713 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2714 2715 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2716 2717 u8 dot3stats_carrier_sense_errors_high[0x20]; 2718 2719 u8 dot3stats_carrier_sense_errors_low[0x20]; 2720 2721 u8 dot3stats_frame_too_longs_high[0x20]; 2722 2723 u8 dot3stats_frame_too_longs_low[0x20]; 2724 2725 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2726 2727 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2728 2729 u8 dot3stats_symbol_errors_high[0x20]; 2730 2731 u8 dot3stats_symbol_errors_low[0x20]; 2732 2733 u8 dot3control_in_unknown_opcodes_high[0x20]; 2734 2735 u8 dot3control_in_unknown_opcodes_low[0x20]; 2736 2737 u8 dot3in_pause_frames_high[0x20]; 2738 2739 u8 dot3in_pause_frames_low[0x20]; 2740 2741 u8 dot3out_pause_frames_high[0x20]; 2742 2743 u8 dot3out_pause_frames_low[0x20]; 2744 2745 u8 reserved_at_400[0x3c0]; 2746 }; 2747 2748 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2749 u8 ether_stats_drop_events_high[0x20]; 2750 2751 u8 ether_stats_drop_events_low[0x20]; 2752 2753 u8 ether_stats_octets_high[0x20]; 2754 2755 u8 ether_stats_octets_low[0x20]; 2756 2757 u8 ether_stats_pkts_high[0x20]; 2758 2759 u8 ether_stats_pkts_low[0x20]; 2760 2761 u8 ether_stats_broadcast_pkts_high[0x20]; 2762 2763 u8 ether_stats_broadcast_pkts_low[0x20]; 2764 2765 u8 ether_stats_multicast_pkts_high[0x20]; 2766 2767 u8 ether_stats_multicast_pkts_low[0x20]; 2768 2769 u8 ether_stats_crc_align_errors_high[0x20]; 2770 2771 u8 ether_stats_crc_align_errors_low[0x20]; 2772 2773 u8 ether_stats_undersize_pkts_high[0x20]; 2774 2775 u8 ether_stats_undersize_pkts_low[0x20]; 2776 2777 u8 ether_stats_oversize_pkts_high[0x20]; 2778 2779 u8 ether_stats_oversize_pkts_low[0x20]; 2780 2781 u8 ether_stats_fragments_high[0x20]; 2782 2783 u8 ether_stats_fragments_low[0x20]; 2784 2785 u8 ether_stats_jabbers_high[0x20]; 2786 2787 u8 ether_stats_jabbers_low[0x20]; 2788 2789 u8 ether_stats_collisions_high[0x20]; 2790 2791 u8 ether_stats_collisions_low[0x20]; 2792 2793 u8 ether_stats_pkts64octets_high[0x20]; 2794 2795 u8 ether_stats_pkts64octets_low[0x20]; 2796 2797 u8 ether_stats_pkts65to127octets_high[0x20]; 2798 2799 u8 ether_stats_pkts65to127octets_low[0x20]; 2800 2801 u8 ether_stats_pkts128to255octets_high[0x20]; 2802 2803 u8 ether_stats_pkts128to255octets_low[0x20]; 2804 2805 u8 ether_stats_pkts256to511octets_high[0x20]; 2806 2807 u8 ether_stats_pkts256to511octets_low[0x20]; 2808 2809 u8 ether_stats_pkts512to1023octets_high[0x20]; 2810 2811 u8 ether_stats_pkts512to1023octets_low[0x20]; 2812 2813 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2814 2815 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2816 2817 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2818 2819 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2820 2821 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2822 2823 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2824 2825 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2826 2827 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2828 2829 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2830 2831 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2832 2833 u8 reserved_at_540[0x280]; 2834 }; 2835 2836 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2837 u8 if_in_octets_high[0x20]; 2838 2839 u8 if_in_octets_low[0x20]; 2840 2841 u8 if_in_ucast_pkts_high[0x20]; 2842 2843 u8 if_in_ucast_pkts_low[0x20]; 2844 2845 u8 if_in_discards_high[0x20]; 2846 2847 u8 if_in_discards_low[0x20]; 2848 2849 u8 if_in_errors_high[0x20]; 2850 2851 u8 if_in_errors_low[0x20]; 2852 2853 u8 if_in_unknown_protos_high[0x20]; 2854 2855 u8 if_in_unknown_protos_low[0x20]; 2856 2857 u8 if_out_octets_high[0x20]; 2858 2859 u8 if_out_octets_low[0x20]; 2860 2861 u8 if_out_ucast_pkts_high[0x20]; 2862 2863 u8 if_out_ucast_pkts_low[0x20]; 2864 2865 u8 if_out_discards_high[0x20]; 2866 2867 u8 if_out_discards_low[0x20]; 2868 2869 u8 if_out_errors_high[0x20]; 2870 2871 u8 if_out_errors_low[0x20]; 2872 2873 u8 if_in_multicast_pkts_high[0x20]; 2874 2875 u8 if_in_multicast_pkts_low[0x20]; 2876 2877 u8 if_in_broadcast_pkts_high[0x20]; 2878 2879 u8 if_in_broadcast_pkts_low[0x20]; 2880 2881 u8 if_out_multicast_pkts_high[0x20]; 2882 2883 u8 if_out_multicast_pkts_low[0x20]; 2884 2885 u8 if_out_broadcast_pkts_high[0x20]; 2886 2887 u8 if_out_broadcast_pkts_low[0x20]; 2888 2889 u8 reserved_at_340[0x480]; 2890 }; 2891 2892 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2893 u8 a_frames_transmitted_ok_high[0x20]; 2894 2895 u8 a_frames_transmitted_ok_low[0x20]; 2896 2897 u8 a_frames_received_ok_high[0x20]; 2898 2899 u8 a_frames_received_ok_low[0x20]; 2900 2901 u8 a_frame_check_sequence_errors_high[0x20]; 2902 2903 u8 a_frame_check_sequence_errors_low[0x20]; 2904 2905 u8 a_alignment_errors_high[0x20]; 2906 2907 u8 a_alignment_errors_low[0x20]; 2908 2909 u8 a_octets_transmitted_ok_high[0x20]; 2910 2911 u8 a_octets_transmitted_ok_low[0x20]; 2912 2913 u8 a_octets_received_ok_high[0x20]; 2914 2915 u8 a_octets_received_ok_low[0x20]; 2916 2917 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2918 2919 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2920 2921 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2922 2923 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2924 2925 u8 a_multicast_frames_received_ok_high[0x20]; 2926 2927 u8 a_multicast_frames_received_ok_low[0x20]; 2928 2929 u8 a_broadcast_frames_received_ok_high[0x20]; 2930 2931 u8 a_broadcast_frames_received_ok_low[0x20]; 2932 2933 u8 a_in_range_length_errors_high[0x20]; 2934 2935 u8 a_in_range_length_errors_low[0x20]; 2936 2937 u8 a_out_of_range_length_field_high[0x20]; 2938 2939 u8 a_out_of_range_length_field_low[0x20]; 2940 2941 u8 a_frame_too_long_errors_high[0x20]; 2942 2943 u8 a_frame_too_long_errors_low[0x20]; 2944 2945 u8 a_symbol_error_during_carrier_high[0x20]; 2946 2947 u8 a_symbol_error_during_carrier_low[0x20]; 2948 2949 u8 a_mac_control_frames_transmitted_high[0x20]; 2950 2951 u8 a_mac_control_frames_transmitted_low[0x20]; 2952 2953 u8 a_mac_control_frames_received_high[0x20]; 2954 2955 u8 a_mac_control_frames_received_low[0x20]; 2956 2957 u8 a_unsupported_opcodes_received_high[0x20]; 2958 2959 u8 a_unsupported_opcodes_received_low[0x20]; 2960 2961 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2962 2963 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2964 2965 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2966 2967 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2968 2969 u8 reserved_at_4c0[0x300]; 2970 }; 2971 2972 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2973 u8 life_time_counter_high[0x20]; 2974 2975 u8 life_time_counter_low[0x20]; 2976 2977 u8 rx_errors[0x20]; 2978 2979 u8 tx_errors[0x20]; 2980 2981 u8 l0_to_recovery_eieos[0x20]; 2982 2983 u8 l0_to_recovery_ts[0x20]; 2984 2985 u8 l0_to_recovery_framing[0x20]; 2986 2987 u8 l0_to_recovery_retrain[0x20]; 2988 2989 u8 crc_error_dllp[0x20]; 2990 2991 u8 crc_error_tlp[0x20]; 2992 2993 u8 tx_overflow_buffer_pkt_high[0x20]; 2994 2995 u8 tx_overflow_buffer_pkt_low[0x20]; 2996 2997 u8 outbound_stalled_reads[0x20]; 2998 2999 u8 outbound_stalled_writes[0x20]; 3000 3001 u8 outbound_stalled_reads_events[0x20]; 3002 3003 u8 outbound_stalled_writes_events[0x20]; 3004 3005 u8 reserved_at_200[0x5c0]; 3006 }; 3007 3008 struct mlx5_ifc_cmd_inter_comp_event_bits { 3009 u8 command_completion_vector[0x20]; 3010 3011 u8 reserved_at_20[0xc0]; 3012 }; 3013 3014 struct mlx5_ifc_stall_vl_event_bits { 3015 u8 reserved_at_0[0x18]; 3016 u8 port_num[0x1]; 3017 u8 reserved_at_19[0x3]; 3018 u8 vl[0x4]; 3019 3020 u8 reserved_at_20[0xa0]; 3021 }; 3022 3023 struct mlx5_ifc_db_bf_congestion_event_bits { 3024 u8 event_subtype[0x8]; 3025 u8 reserved_at_8[0x8]; 3026 u8 congestion_level[0x8]; 3027 u8 reserved_at_18[0x8]; 3028 3029 u8 reserved_at_20[0xa0]; 3030 }; 3031 3032 struct mlx5_ifc_gpio_event_bits { 3033 u8 reserved_at_0[0x60]; 3034 3035 u8 gpio_event_hi[0x20]; 3036 3037 u8 gpio_event_lo[0x20]; 3038 3039 u8 reserved_at_a0[0x40]; 3040 }; 3041 3042 struct mlx5_ifc_port_state_change_event_bits { 3043 u8 reserved_at_0[0x40]; 3044 3045 u8 port_num[0x4]; 3046 u8 reserved_at_44[0x1c]; 3047 3048 u8 reserved_at_60[0x80]; 3049 }; 3050 3051 struct mlx5_ifc_dropped_packet_logged_bits { 3052 u8 reserved_at_0[0xe0]; 3053 }; 3054 3055 struct mlx5_ifc_default_timeout_bits { 3056 u8 to_multiplier[0x3]; 3057 u8 reserved_at_3[0x9]; 3058 u8 to_value[0x14]; 3059 }; 3060 3061 struct mlx5_ifc_dtor_reg_bits { 3062 u8 reserved_at_0[0x20]; 3063 3064 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3065 3066 u8 reserved_at_40[0x60]; 3067 3068 struct mlx5_ifc_default_timeout_bits health_poll_to; 3069 3070 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3071 3072 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3073 3074 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3075 3076 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3077 3078 struct mlx5_ifc_default_timeout_bits tear_down_to; 3079 3080 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3081 3082 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3083 3084 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3085 3086 u8 reserved_at_1c0[0x40]; 3087 }; 3088 3089 enum { 3090 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3091 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3092 }; 3093 3094 struct mlx5_ifc_cq_error_bits { 3095 u8 reserved_at_0[0x8]; 3096 u8 cqn[0x18]; 3097 3098 u8 reserved_at_20[0x20]; 3099 3100 u8 reserved_at_40[0x18]; 3101 u8 syndrome[0x8]; 3102 3103 u8 reserved_at_60[0x80]; 3104 }; 3105 3106 struct mlx5_ifc_rdma_page_fault_event_bits { 3107 u8 bytes_committed[0x20]; 3108 3109 u8 r_key[0x20]; 3110 3111 u8 reserved_at_40[0x10]; 3112 u8 packet_len[0x10]; 3113 3114 u8 rdma_op_len[0x20]; 3115 3116 u8 rdma_va[0x40]; 3117 3118 u8 reserved_at_c0[0x5]; 3119 u8 rdma[0x1]; 3120 u8 write[0x1]; 3121 u8 requestor[0x1]; 3122 u8 qp_number[0x18]; 3123 }; 3124 3125 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3126 u8 bytes_committed[0x20]; 3127 3128 u8 reserved_at_20[0x10]; 3129 u8 wqe_index[0x10]; 3130 3131 u8 reserved_at_40[0x10]; 3132 u8 len[0x10]; 3133 3134 u8 reserved_at_60[0x60]; 3135 3136 u8 reserved_at_c0[0x5]; 3137 u8 rdma[0x1]; 3138 u8 write_read[0x1]; 3139 u8 requestor[0x1]; 3140 u8 qpn[0x18]; 3141 }; 3142 3143 struct mlx5_ifc_qp_events_bits { 3144 u8 reserved_at_0[0xa0]; 3145 3146 u8 type[0x8]; 3147 u8 reserved_at_a8[0x18]; 3148 3149 u8 reserved_at_c0[0x8]; 3150 u8 qpn_rqn_sqn[0x18]; 3151 }; 3152 3153 struct mlx5_ifc_dct_events_bits { 3154 u8 reserved_at_0[0xc0]; 3155 3156 u8 reserved_at_c0[0x8]; 3157 u8 dct_number[0x18]; 3158 }; 3159 3160 struct mlx5_ifc_comp_event_bits { 3161 u8 reserved_at_0[0xc0]; 3162 3163 u8 reserved_at_c0[0x8]; 3164 u8 cq_number[0x18]; 3165 }; 3166 3167 enum { 3168 MLX5_QPC_STATE_RST = 0x0, 3169 MLX5_QPC_STATE_INIT = 0x1, 3170 MLX5_QPC_STATE_RTR = 0x2, 3171 MLX5_QPC_STATE_RTS = 0x3, 3172 MLX5_QPC_STATE_SQER = 0x4, 3173 MLX5_QPC_STATE_ERR = 0x6, 3174 MLX5_QPC_STATE_SQD = 0x7, 3175 MLX5_QPC_STATE_SUSPENDED = 0x9, 3176 }; 3177 3178 enum { 3179 MLX5_QPC_ST_RC = 0x0, 3180 MLX5_QPC_ST_UC = 0x1, 3181 MLX5_QPC_ST_UD = 0x2, 3182 MLX5_QPC_ST_XRC = 0x3, 3183 MLX5_QPC_ST_DCI = 0x5, 3184 MLX5_QPC_ST_QP0 = 0x7, 3185 MLX5_QPC_ST_QP1 = 0x8, 3186 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3187 MLX5_QPC_ST_REG_UMR = 0xc, 3188 }; 3189 3190 enum { 3191 MLX5_QPC_PM_STATE_ARMED = 0x0, 3192 MLX5_QPC_PM_STATE_REARM = 0x1, 3193 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3194 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3195 }; 3196 3197 enum { 3198 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3199 }; 3200 3201 enum { 3202 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3203 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3204 }; 3205 3206 enum { 3207 MLX5_QPC_MTU_256_BYTES = 0x1, 3208 MLX5_QPC_MTU_512_BYTES = 0x2, 3209 MLX5_QPC_MTU_1K_BYTES = 0x3, 3210 MLX5_QPC_MTU_2K_BYTES = 0x4, 3211 MLX5_QPC_MTU_4K_BYTES = 0x5, 3212 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3213 }; 3214 3215 enum { 3216 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3217 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3218 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3219 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3220 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3221 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3222 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3223 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3224 }; 3225 3226 enum { 3227 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3228 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3229 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3230 }; 3231 3232 enum { 3233 MLX5_QPC_CS_RES_DISABLE = 0x0, 3234 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3235 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3236 }; 3237 3238 enum { 3239 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3240 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3241 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3242 }; 3243 3244 struct mlx5_ifc_qpc_bits { 3245 u8 state[0x4]; 3246 u8 lag_tx_port_affinity[0x4]; 3247 u8 st[0x8]; 3248 u8 reserved_at_10[0x2]; 3249 u8 isolate_vl_tc[0x1]; 3250 u8 pm_state[0x2]; 3251 u8 reserved_at_15[0x1]; 3252 u8 req_e2e_credit_mode[0x2]; 3253 u8 offload_type[0x4]; 3254 u8 end_padding_mode[0x2]; 3255 u8 reserved_at_1e[0x2]; 3256 3257 u8 wq_signature[0x1]; 3258 u8 block_lb_mc[0x1]; 3259 u8 atomic_like_write_en[0x1]; 3260 u8 latency_sensitive[0x1]; 3261 u8 reserved_at_24[0x1]; 3262 u8 drain_sigerr[0x1]; 3263 u8 reserved_at_26[0x2]; 3264 u8 pd[0x18]; 3265 3266 u8 mtu[0x3]; 3267 u8 log_msg_max[0x5]; 3268 u8 reserved_at_48[0x1]; 3269 u8 log_rq_size[0x4]; 3270 u8 log_rq_stride[0x3]; 3271 u8 no_sq[0x1]; 3272 u8 log_sq_size[0x4]; 3273 u8 reserved_at_55[0x3]; 3274 u8 ts_format[0x2]; 3275 u8 reserved_at_5a[0x1]; 3276 u8 rlky[0x1]; 3277 u8 ulp_stateless_offload_mode[0x4]; 3278 3279 u8 counter_set_id[0x8]; 3280 u8 uar_page[0x18]; 3281 3282 u8 reserved_at_80[0x8]; 3283 u8 user_index[0x18]; 3284 3285 u8 reserved_at_a0[0x3]; 3286 u8 log_page_size[0x5]; 3287 u8 remote_qpn[0x18]; 3288 3289 struct mlx5_ifc_ads_bits primary_address_path; 3290 3291 struct mlx5_ifc_ads_bits secondary_address_path; 3292 3293 u8 log_ack_req_freq[0x4]; 3294 u8 reserved_at_384[0x4]; 3295 u8 log_sra_max[0x3]; 3296 u8 reserved_at_38b[0x2]; 3297 u8 retry_count[0x3]; 3298 u8 rnr_retry[0x3]; 3299 u8 reserved_at_393[0x1]; 3300 u8 fre[0x1]; 3301 u8 cur_rnr_retry[0x3]; 3302 u8 cur_retry_count[0x3]; 3303 u8 reserved_at_39b[0x5]; 3304 3305 u8 reserved_at_3a0[0x20]; 3306 3307 u8 reserved_at_3c0[0x8]; 3308 u8 next_send_psn[0x18]; 3309 3310 u8 reserved_at_3e0[0x3]; 3311 u8 log_num_dci_stream_channels[0x5]; 3312 u8 cqn_snd[0x18]; 3313 3314 u8 reserved_at_400[0x3]; 3315 u8 log_num_dci_errored_streams[0x5]; 3316 u8 deth_sqpn[0x18]; 3317 3318 u8 reserved_at_420[0x20]; 3319 3320 u8 reserved_at_440[0x8]; 3321 u8 last_acked_psn[0x18]; 3322 3323 u8 reserved_at_460[0x8]; 3324 u8 ssn[0x18]; 3325 3326 u8 reserved_at_480[0x8]; 3327 u8 log_rra_max[0x3]; 3328 u8 reserved_at_48b[0x1]; 3329 u8 atomic_mode[0x4]; 3330 u8 rre[0x1]; 3331 u8 rwe[0x1]; 3332 u8 rae[0x1]; 3333 u8 reserved_at_493[0x1]; 3334 u8 page_offset[0x6]; 3335 u8 reserved_at_49a[0x3]; 3336 u8 cd_slave_receive[0x1]; 3337 u8 cd_slave_send[0x1]; 3338 u8 cd_master[0x1]; 3339 3340 u8 reserved_at_4a0[0x3]; 3341 u8 min_rnr_nak[0x5]; 3342 u8 next_rcv_psn[0x18]; 3343 3344 u8 reserved_at_4c0[0x8]; 3345 u8 xrcd[0x18]; 3346 3347 u8 reserved_at_4e0[0x8]; 3348 u8 cqn_rcv[0x18]; 3349 3350 u8 dbr_addr[0x40]; 3351 3352 u8 q_key[0x20]; 3353 3354 u8 reserved_at_560[0x5]; 3355 u8 rq_type[0x3]; 3356 u8 srqn_rmpn_xrqn[0x18]; 3357 3358 u8 reserved_at_580[0x8]; 3359 u8 rmsn[0x18]; 3360 3361 u8 hw_sq_wqebb_counter[0x10]; 3362 u8 sw_sq_wqebb_counter[0x10]; 3363 3364 u8 hw_rq_counter[0x20]; 3365 3366 u8 sw_rq_counter[0x20]; 3367 3368 u8 reserved_at_600[0x20]; 3369 3370 u8 reserved_at_620[0xf]; 3371 u8 cgs[0x1]; 3372 u8 cs_req[0x8]; 3373 u8 cs_res[0x8]; 3374 3375 u8 dc_access_key[0x40]; 3376 3377 u8 reserved_at_680[0x3]; 3378 u8 dbr_umem_valid[0x1]; 3379 3380 u8 reserved_at_684[0xbc]; 3381 }; 3382 3383 struct mlx5_ifc_roce_addr_layout_bits { 3384 u8 source_l3_address[16][0x8]; 3385 3386 u8 reserved_at_80[0x3]; 3387 u8 vlan_valid[0x1]; 3388 u8 vlan_id[0xc]; 3389 u8 source_mac_47_32[0x10]; 3390 3391 u8 source_mac_31_0[0x20]; 3392 3393 u8 reserved_at_c0[0x14]; 3394 u8 roce_l3_type[0x4]; 3395 u8 roce_version[0x8]; 3396 3397 u8 reserved_at_e0[0x20]; 3398 }; 3399 3400 struct mlx5_ifc_shampo_cap_bits { 3401 u8 reserved_at_0[0x3]; 3402 u8 shampo_log_max_reservation_size[0x5]; 3403 u8 reserved_at_8[0x3]; 3404 u8 shampo_log_min_reservation_size[0x5]; 3405 u8 shampo_min_mss_size[0x10]; 3406 3407 u8 reserved_at_20[0x3]; 3408 u8 shampo_max_log_headers_entry_size[0x5]; 3409 u8 reserved_at_28[0x18]; 3410 3411 u8 reserved_at_40[0x7c0]; 3412 }; 3413 3414 struct mlx5_ifc_crypto_cap_bits { 3415 u8 reserved_at_0[0x3]; 3416 u8 synchronize_dek[0x1]; 3417 u8 int_kek_manual[0x1]; 3418 u8 int_kek_auto[0x1]; 3419 u8 reserved_at_6[0x1a]; 3420 3421 u8 reserved_at_20[0x3]; 3422 u8 log_dek_max_alloc[0x5]; 3423 u8 reserved_at_28[0x3]; 3424 u8 log_max_num_deks[0x5]; 3425 u8 reserved_at_30[0x10]; 3426 3427 u8 reserved_at_40[0x20]; 3428 3429 u8 reserved_at_60[0x3]; 3430 u8 log_dek_granularity[0x5]; 3431 u8 reserved_at_68[0x3]; 3432 u8 log_max_num_int_kek[0x5]; 3433 u8 sw_wrapped_dek[0x10]; 3434 3435 u8 reserved_at_80[0x780]; 3436 }; 3437 3438 union mlx5_ifc_hca_cap_union_bits { 3439 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3440 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3441 struct mlx5_ifc_odp_cap_bits odp_cap; 3442 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3443 struct mlx5_ifc_roce_cap_bits roce_cap; 3444 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3445 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3446 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3447 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3448 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3449 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3450 struct mlx5_ifc_qos_cap_bits qos_cap; 3451 struct mlx5_ifc_debug_cap_bits debug_cap; 3452 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3453 struct mlx5_ifc_tls_cap_bits tls_cap; 3454 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3455 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3456 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3457 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3458 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3459 u8 reserved_at_0[0x8000]; 3460 }; 3461 3462 enum { 3463 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3464 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3465 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3466 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3467 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3468 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3469 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3470 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3471 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3472 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3473 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3474 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3475 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3476 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3477 }; 3478 3479 enum { 3480 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3481 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3482 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3483 }; 3484 3485 enum { 3486 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3487 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3488 }; 3489 3490 struct mlx5_ifc_vlan_bits { 3491 u8 ethtype[0x10]; 3492 u8 prio[0x3]; 3493 u8 cfi[0x1]; 3494 u8 vid[0xc]; 3495 }; 3496 3497 enum { 3498 MLX5_FLOW_METER_COLOR_RED = 0x0, 3499 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3500 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3501 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3502 }; 3503 3504 enum { 3505 MLX5_EXE_ASO_FLOW_METER = 0x2, 3506 }; 3507 3508 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3509 u8 return_reg_id[0x4]; 3510 u8 aso_type[0x4]; 3511 u8 reserved_at_8[0x14]; 3512 u8 action[0x1]; 3513 u8 init_color[0x2]; 3514 u8 meter_id[0x1]; 3515 }; 3516 3517 union mlx5_ifc_exe_aso_ctrl { 3518 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3519 }; 3520 3521 struct mlx5_ifc_execute_aso_bits { 3522 u8 valid[0x1]; 3523 u8 reserved_at_1[0x7]; 3524 u8 aso_object_id[0x18]; 3525 3526 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3527 }; 3528 3529 struct mlx5_ifc_flow_context_bits { 3530 struct mlx5_ifc_vlan_bits push_vlan; 3531 3532 u8 group_id[0x20]; 3533 3534 u8 reserved_at_40[0x8]; 3535 u8 flow_tag[0x18]; 3536 3537 u8 reserved_at_60[0x10]; 3538 u8 action[0x10]; 3539 3540 u8 extended_destination[0x1]; 3541 u8 reserved_at_81[0x1]; 3542 u8 flow_source[0x2]; 3543 u8 encrypt_decrypt_type[0x4]; 3544 u8 destination_list_size[0x18]; 3545 3546 u8 reserved_at_a0[0x8]; 3547 u8 flow_counter_list_size[0x18]; 3548 3549 u8 packet_reformat_id[0x20]; 3550 3551 u8 modify_header_id[0x20]; 3552 3553 struct mlx5_ifc_vlan_bits push_vlan_2; 3554 3555 u8 encrypt_decrypt_obj_id[0x20]; 3556 u8 reserved_at_140[0xc0]; 3557 3558 struct mlx5_ifc_fte_match_param_bits match_value; 3559 3560 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3561 3562 u8 reserved_at_1300[0x500]; 3563 3564 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3565 }; 3566 3567 enum { 3568 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3569 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3570 }; 3571 3572 struct mlx5_ifc_xrc_srqc_bits { 3573 u8 state[0x4]; 3574 u8 log_xrc_srq_size[0x4]; 3575 u8 reserved_at_8[0x18]; 3576 3577 u8 wq_signature[0x1]; 3578 u8 cont_srq[0x1]; 3579 u8 reserved_at_22[0x1]; 3580 u8 rlky[0x1]; 3581 u8 basic_cyclic_rcv_wqe[0x1]; 3582 u8 log_rq_stride[0x3]; 3583 u8 xrcd[0x18]; 3584 3585 u8 page_offset[0x6]; 3586 u8 reserved_at_46[0x1]; 3587 u8 dbr_umem_valid[0x1]; 3588 u8 cqn[0x18]; 3589 3590 u8 reserved_at_60[0x20]; 3591 3592 u8 user_index_equal_xrc_srqn[0x1]; 3593 u8 reserved_at_81[0x1]; 3594 u8 log_page_size[0x6]; 3595 u8 user_index[0x18]; 3596 3597 u8 reserved_at_a0[0x20]; 3598 3599 u8 reserved_at_c0[0x8]; 3600 u8 pd[0x18]; 3601 3602 u8 lwm[0x10]; 3603 u8 wqe_cnt[0x10]; 3604 3605 u8 reserved_at_100[0x40]; 3606 3607 u8 db_record_addr_h[0x20]; 3608 3609 u8 db_record_addr_l[0x1e]; 3610 u8 reserved_at_17e[0x2]; 3611 3612 u8 reserved_at_180[0x80]; 3613 }; 3614 3615 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3616 u8 counter_error_queues[0x20]; 3617 3618 u8 total_error_queues[0x20]; 3619 3620 u8 send_queue_priority_update_flow[0x20]; 3621 3622 u8 reserved_at_60[0x20]; 3623 3624 u8 nic_receive_steering_discard[0x40]; 3625 3626 u8 receive_discard_vport_down[0x40]; 3627 3628 u8 transmit_discard_vport_down[0x40]; 3629 3630 u8 async_eq_overrun[0x20]; 3631 3632 u8 comp_eq_overrun[0x20]; 3633 3634 u8 reserved_at_180[0x20]; 3635 3636 u8 invalid_command[0x20]; 3637 3638 u8 quota_exceeded_command[0x20]; 3639 3640 u8 internal_rq_out_of_buffer[0x20]; 3641 3642 u8 cq_overrun[0x20]; 3643 3644 u8 eth_wqe_too_small[0x20]; 3645 3646 u8 reserved_at_220[0xdc0]; 3647 }; 3648 3649 struct mlx5_ifc_traffic_counter_bits { 3650 u8 packets[0x40]; 3651 3652 u8 octets[0x40]; 3653 }; 3654 3655 struct mlx5_ifc_tisc_bits { 3656 u8 strict_lag_tx_port_affinity[0x1]; 3657 u8 tls_en[0x1]; 3658 u8 reserved_at_2[0x2]; 3659 u8 lag_tx_port_affinity[0x04]; 3660 3661 u8 reserved_at_8[0x4]; 3662 u8 prio[0x4]; 3663 u8 reserved_at_10[0x10]; 3664 3665 u8 reserved_at_20[0x100]; 3666 3667 u8 reserved_at_120[0x8]; 3668 u8 transport_domain[0x18]; 3669 3670 u8 reserved_at_140[0x8]; 3671 u8 underlay_qpn[0x18]; 3672 3673 u8 reserved_at_160[0x8]; 3674 u8 pd[0x18]; 3675 3676 u8 reserved_at_180[0x380]; 3677 }; 3678 3679 enum { 3680 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3681 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3682 }; 3683 3684 enum { 3685 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3686 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3687 }; 3688 3689 enum { 3690 MLX5_RX_HASH_FN_NONE = 0x0, 3691 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3692 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3693 }; 3694 3695 enum { 3696 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3697 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3698 }; 3699 3700 struct mlx5_ifc_tirc_bits { 3701 u8 reserved_at_0[0x20]; 3702 3703 u8 disp_type[0x4]; 3704 u8 tls_en[0x1]; 3705 u8 reserved_at_25[0x1b]; 3706 3707 u8 reserved_at_40[0x40]; 3708 3709 u8 reserved_at_80[0x4]; 3710 u8 lro_timeout_period_usecs[0x10]; 3711 u8 packet_merge_mask[0x4]; 3712 u8 lro_max_ip_payload_size[0x8]; 3713 3714 u8 reserved_at_a0[0x40]; 3715 3716 u8 reserved_at_e0[0x8]; 3717 u8 inline_rqn[0x18]; 3718 3719 u8 rx_hash_symmetric[0x1]; 3720 u8 reserved_at_101[0x1]; 3721 u8 tunneled_offload_en[0x1]; 3722 u8 reserved_at_103[0x5]; 3723 u8 indirect_table[0x18]; 3724 3725 u8 rx_hash_fn[0x4]; 3726 u8 reserved_at_124[0x2]; 3727 u8 self_lb_block[0x2]; 3728 u8 transport_domain[0x18]; 3729 3730 u8 rx_hash_toeplitz_key[10][0x20]; 3731 3732 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3733 3734 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3735 3736 u8 reserved_at_2c0[0x4c0]; 3737 }; 3738 3739 enum { 3740 MLX5_SRQC_STATE_GOOD = 0x0, 3741 MLX5_SRQC_STATE_ERROR = 0x1, 3742 }; 3743 3744 struct mlx5_ifc_srqc_bits { 3745 u8 state[0x4]; 3746 u8 log_srq_size[0x4]; 3747 u8 reserved_at_8[0x18]; 3748 3749 u8 wq_signature[0x1]; 3750 u8 cont_srq[0x1]; 3751 u8 reserved_at_22[0x1]; 3752 u8 rlky[0x1]; 3753 u8 reserved_at_24[0x1]; 3754 u8 log_rq_stride[0x3]; 3755 u8 xrcd[0x18]; 3756 3757 u8 page_offset[0x6]; 3758 u8 reserved_at_46[0x2]; 3759 u8 cqn[0x18]; 3760 3761 u8 reserved_at_60[0x20]; 3762 3763 u8 reserved_at_80[0x2]; 3764 u8 log_page_size[0x6]; 3765 u8 reserved_at_88[0x18]; 3766 3767 u8 reserved_at_a0[0x20]; 3768 3769 u8 reserved_at_c0[0x8]; 3770 u8 pd[0x18]; 3771 3772 u8 lwm[0x10]; 3773 u8 wqe_cnt[0x10]; 3774 3775 u8 reserved_at_100[0x40]; 3776 3777 u8 dbr_addr[0x40]; 3778 3779 u8 reserved_at_180[0x80]; 3780 }; 3781 3782 enum { 3783 MLX5_SQC_STATE_RST = 0x0, 3784 MLX5_SQC_STATE_RDY = 0x1, 3785 MLX5_SQC_STATE_ERR = 0x3, 3786 }; 3787 3788 struct mlx5_ifc_sqc_bits { 3789 u8 rlky[0x1]; 3790 u8 cd_master[0x1]; 3791 u8 fre[0x1]; 3792 u8 flush_in_error_en[0x1]; 3793 u8 allow_multi_pkt_send_wqe[0x1]; 3794 u8 min_wqe_inline_mode[0x3]; 3795 u8 state[0x4]; 3796 u8 reg_umr[0x1]; 3797 u8 allow_swp[0x1]; 3798 u8 hairpin[0x1]; 3799 u8 reserved_at_f[0xb]; 3800 u8 ts_format[0x2]; 3801 u8 reserved_at_1c[0x4]; 3802 3803 u8 reserved_at_20[0x8]; 3804 u8 user_index[0x18]; 3805 3806 u8 reserved_at_40[0x8]; 3807 u8 cqn[0x18]; 3808 3809 u8 reserved_at_60[0x8]; 3810 u8 hairpin_peer_rq[0x18]; 3811 3812 u8 reserved_at_80[0x10]; 3813 u8 hairpin_peer_vhca[0x10]; 3814 3815 u8 reserved_at_a0[0x20]; 3816 3817 u8 reserved_at_c0[0x8]; 3818 u8 ts_cqe_to_dest_cqn[0x18]; 3819 3820 u8 reserved_at_e0[0x10]; 3821 u8 packet_pacing_rate_limit_index[0x10]; 3822 u8 tis_lst_sz[0x10]; 3823 u8 qos_queue_group_id[0x10]; 3824 3825 u8 reserved_at_120[0x40]; 3826 3827 u8 reserved_at_160[0x8]; 3828 u8 tis_num_0[0x18]; 3829 3830 struct mlx5_ifc_wq_bits wq; 3831 }; 3832 3833 enum { 3834 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3835 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3836 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3837 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3838 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3839 }; 3840 3841 enum { 3842 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3843 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3844 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3845 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3846 }; 3847 3848 struct mlx5_ifc_scheduling_context_bits { 3849 u8 element_type[0x8]; 3850 u8 reserved_at_8[0x18]; 3851 3852 u8 element_attributes[0x20]; 3853 3854 u8 parent_element_id[0x20]; 3855 3856 u8 reserved_at_60[0x40]; 3857 3858 u8 bw_share[0x20]; 3859 3860 u8 max_average_bw[0x20]; 3861 3862 u8 reserved_at_e0[0x120]; 3863 }; 3864 3865 struct mlx5_ifc_rqtc_bits { 3866 u8 reserved_at_0[0xa0]; 3867 3868 u8 reserved_at_a0[0x5]; 3869 u8 list_q_type[0x3]; 3870 u8 reserved_at_a8[0x8]; 3871 u8 rqt_max_size[0x10]; 3872 3873 u8 rq_vhca_id_format[0x1]; 3874 u8 reserved_at_c1[0xf]; 3875 u8 rqt_actual_size[0x10]; 3876 3877 u8 reserved_at_e0[0x6a0]; 3878 3879 struct mlx5_ifc_rq_num_bits rq_num[]; 3880 }; 3881 3882 enum { 3883 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3884 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3885 }; 3886 3887 enum { 3888 MLX5_RQC_STATE_RST = 0x0, 3889 MLX5_RQC_STATE_RDY = 0x1, 3890 MLX5_RQC_STATE_ERR = 0x3, 3891 }; 3892 3893 enum { 3894 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3895 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3896 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3897 }; 3898 3899 enum { 3900 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3901 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3902 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3903 }; 3904 3905 struct mlx5_ifc_rqc_bits { 3906 u8 rlky[0x1]; 3907 u8 delay_drop_en[0x1]; 3908 u8 scatter_fcs[0x1]; 3909 u8 vsd[0x1]; 3910 u8 mem_rq_type[0x4]; 3911 u8 state[0x4]; 3912 u8 reserved_at_c[0x1]; 3913 u8 flush_in_error_en[0x1]; 3914 u8 hairpin[0x1]; 3915 u8 reserved_at_f[0xb]; 3916 u8 ts_format[0x2]; 3917 u8 reserved_at_1c[0x4]; 3918 3919 u8 reserved_at_20[0x8]; 3920 u8 user_index[0x18]; 3921 3922 u8 reserved_at_40[0x8]; 3923 u8 cqn[0x18]; 3924 3925 u8 counter_set_id[0x8]; 3926 u8 reserved_at_68[0x18]; 3927 3928 u8 reserved_at_80[0x8]; 3929 u8 rmpn[0x18]; 3930 3931 u8 reserved_at_a0[0x8]; 3932 u8 hairpin_peer_sq[0x18]; 3933 3934 u8 reserved_at_c0[0x10]; 3935 u8 hairpin_peer_vhca[0x10]; 3936 3937 u8 reserved_at_e0[0x46]; 3938 u8 shampo_no_match_alignment_granularity[0x2]; 3939 u8 reserved_at_128[0x6]; 3940 u8 shampo_match_criteria_type[0x2]; 3941 u8 reservation_timeout[0x10]; 3942 3943 u8 reserved_at_140[0x40]; 3944 3945 struct mlx5_ifc_wq_bits wq; 3946 }; 3947 3948 enum { 3949 MLX5_RMPC_STATE_RDY = 0x1, 3950 MLX5_RMPC_STATE_ERR = 0x3, 3951 }; 3952 3953 struct mlx5_ifc_rmpc_bits { 3954 u8 reserved_at_0[0x8]; 3955 u8 state[0x4]; 3956 u8 reserved_at_c[0x14]; 3957 3958 u8 basic_cyclic_rcv_wqe[0x1]; 3959 u8 reserved_at_21[0x1f]; 3960 3961 u8 reserved_at_40[0x140]; 3962 3963 struct mlx5_ifc_wq_bits wq; 3964 }; 3965 3966 enum { 3967 VHCA_ID_TYPE_HW = 0, 3968 VHCA_ID_TYPE_SW = 1, 3969 }; 3970 3971 struct mlx5_ifc_nic_vport_context_bits { 3972 u8 reserved_at_0[0x5]; 3973 u8 min_wqe_inline_mode[0x3]; 3974 u8 reserved_at_8[0x15]; 3975 u8 disable_mc_local_lb[0x1]; 3976 u8 disable_uc_local_lb[0x1]; 3977 u8 roce_en[0x1]; 3978 3979 u8 arm_change_event[0x1]; 3980 u8 reserved_at_21[0x1a]; 3981 u8 event_on_mtu[0x1]; 3982 u8 event_on_promisc_change[0x1]; 3983 u8 event_on_vlan_change[0x1]; 3984 u8 event_on_mc_address_change[0x1]; 3985 u8 event_on_uc_address_change[0x1]; 3986 3987 u8 vhca_id_type[0x1]; 3988 u8 reserved_at_41[0xb]; 3989 u8 affiliation_criteria[0x4]; 3990 u8 affiliated_vhca_id[0x10]; 3991 3992 u8 reserved_at_60[0xd0]; 3993 3994 u8 mtu[0x10]; 3995 3996 u8 system_image_guid[0x40]; 3997 u8 port_guid[0x40]; 3998 u8 node_guid[0x40]; 3999 4000 u8 reserved_at_200[0x140]; 4001 u8 qkey_violation_counter[0x10]; 4002 u8 reserved_at_350[0x430]; 4003 4004 u8 promisc_uc[0x1]; 4005 u8 promisc_mc[0x1]; 4006 u8 promisc_all[0x1]; 4007 u8 reserved_at_783[0x2]; 4008 u8 allowed_list_type[0x3]; 4009 u8 reserved_at_788[0xc]; 4010 u8 allowed_list_size[0xc]; 4011 4012 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4013 4014 u8 reserved_at_7e0[0x20]; 4015 4016 u8 current_uc_mac_address[][0x40]; 4017 }; 4018 4019 enum { 4020 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4021 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4022 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4023 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4024 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4025 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4026 }; 4027 4028 struct mlx5_ifc_mkc_bits { 4029 u8 reserved_at_0[0x1]; 4030 u8 free[0x1]; 4031 u8 reserved_at_2[0x1]; 4032 u8 access_mode_4_2[0x3]; 4033 u8 reserved_at_6[0x7]; 4034 u8 relaxed_ordering_write[0x1]; 4035 u8 reserved_at_e[0x1]; 4036 u8 small_fence_on_rdma_read_response[0x1]; 4037 u8 umr_en[0x1]; 4038 u8 a[0x1]; 4039 u8 rw[0x1]; 4040 u8 rr[0x1]; 4041 u8 lw[0x1]; 4042 u8 lr[0x1]; 4043 u8 access_mode_1_0[0x2]; 4044 u8 reserved_at_18[0x2]; 4045 u8 ma_translation_mode[0x2]; 4046 u8 reserved_at_1c[0x4]; 4047 4048 u8 qpn[0x18]; 4049 u8 mkey_7_0[0x8]; 4050 4051 u8 reserved_at_40[0x20]; 4052 4053 u8 length64[0x1]; 4054 u8 bsf_en[0x1]; 4055 u8 sync_umr[0x1]; 4056 u8 reserved_at_63[0x2]; 4057 u8 expected_sigerr_count[0x1]; 4058 u8 reserved_at_66[0x1]; 4059 u8 en_rinval[0x1]; 4060 u8 pd[0x18]; 4061 4062 u8 start_addr[0x40]; 4063 4064 u8 len[0x40]; 4065 4066 u8 bsf_octword_size[0x20]; 4067 4068 u8 reserved_at_120[0x80]; 4069 4070 u8 translations_octword_size[0x20]; 4071 4072 u8 reserved_at_1c0[0x19]; 4073 u8 relaxed_ordering_read[0x1]; 4074 u8 reserved_at_1d9[0x1]; 4075 u8 log_page_size[0x5]; 4076 4077 u8 reserved_at_1e0[0x20]; 4078 }; 4079 4080 struct mlx5_ifc_pkey_bits { 4081 u8 reserved_at_0[0x10]; 4082 u8 pkey[0x10]; 4083 }; 4084 4085 struct mlx5_ifc_array128_auto_bits { 4086 u8 array128_auto[16][0x8]; 4087 }; 4088 4089 struct mlx5_ifc_hca_vport_context_bits { 4090 u8 field_select[0x20]; 4091 4092 u8 reserved_at_20[0xe0]; 4093 4094 u8 sm_virt_aware[0x1]; 4095 u8 has_smi[0x1]; 4096 u8 has_raw[0x1]; 4097 u8 grh_required[0x1]; 4098 u8 reserved_at_104[0xc]; 4099 u8 port_physical_state[0x4]; 4100 u8 vport_state_policy[0x4]; 4101 u8 port_state[0x4]; 4102 u8 vport_state[0x4]; 4103 4104 u8 reserved_at_120[0x20]; 4105 4106 u8 system_image_guid[0x40]; 4107 4108 u8 port_guid[0x40]; 4109 4110 u8 node_guid[0x40]; 4111 4112 u8 cap_mask1[0x20]; 4113 4114 u8 cap_mask1_field_select[0x20]; 4115 4116 u8 cap_mask2[0x20]; 4117 4118 u8 cap_mask2_field_select[0x20]; 4119 4120 u8 reserved_at_280[0x80]; 4121 4122 u8 lid[0x10]; 4123 u8 reserved_at_310[0x4]; 4124 u8 init_type_reply[0x4]; 4125 u8 lmc[0x3]; 4126 u8 subnet_timeout[0x5]; 4127 4128 u8 sm_lid[0x10]; 4129 u8 sm_sl[0x4]; 4130 u8 reserved_at_334[0xc]; 4131 4132 u8 qkey_violation_counter[0x10]; 4133 u8 pkey_violation_counter[0x10]; 4134 4135 u8 reserved_at_360[0xca0]; 4136 }; 4137 4138 struct mlx5_ifc_esw_vport_context_bits { 4139 u8 fdb_to_vport_reg_c[0x1]; 4140 u8 reserved_at_1[0x2]; 4141 u8 vport_svlan_strip[0x1]; 4142 u8 vport_cvlan_strip[0x1]; 4143 u8 vport_svlan_insert[0x1]; 4144 u8 vport_cvlan_insert[0x2]; 4145 u8 fdb_to_vport_reg_c_id[0x8]; 4146 u8 reserved_at_10[0x10]; 4147 4148 u8 reserved_at_20[0x20]; 4149 4150 u8 svlan_cfi[0x1]; 4151 u8 svlan_pcp[0x3]; 4152 u8 svlan_id[0xc]; 4153 u8 cvlan_cfi[0x1]; 4154 u8 cvlan_pcp[0x3]; 4155 u8 cvlan_id[0xc]; 4156 4157 u8 reserved_at_60[0x720]; 4158 4159 u8 sw_steering_vport_icm_address_rx[0x40]; 4160 4161 u8 sw_steering_vport_icm_address_tx[0x40]; 4162 }; 4163 4164 enum { 4165 MLX5_EQC_STATUS_OK = 0x0, 4166 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4167 }; 4168 4169 enum { 4170 MLX5_EQC_ST_ARMED = 0x9, 4171 MLX5_EQC_ST_FIRED = 0xa, 4172 }; 4173 4174 struct mlx5_ifc_eqc_bits { 4175 u8 status[0x4]; 4176 u8 reserved_at_4[0x9]; 4177 u8 ec[0x1]; 4178 u8 oi[0x1]; 4179 u8 reserved_at_f[0x5]; 4180 u8 st[0x4]; 4181 u8 reserved_at_18[0x8]; 4182 4183 u8 reserved_at_20[0x20]; 4184 4185 u8 reserved_at_40[0x14]; 4186 u8 page_offset[0x6]; 4187 u8 reserved_at_5a[0x6]; 4188 4189 u8 reserved_at_60[0x3]; 4190 u8 log_eq_size[0x5]; 4191 u8 uar_page[0x18]; 4192 4193 u8 reserved_at_80[0x20]; 4194 4195 u8 reserved_at_a0[0x14]; 4196 u8 intr[0xc]; 4197 4198 u8 reserved_at_c0[0x3]; 4199 u8 log_page_size[0x5]; 4200 u8 reserved_at_c8[0x18]; 4201 4202 u8 reserved_at_e0[0x60]; 4203 4204 u8 reserved_at_140[0x8]; 4205 u8 consumer_counter[0x18]; 4206 4207 u8 reserved_at_160[0x8]; 4208 u8 producer_counter[0x18]; 4209 4210 u8 reserved_at_180[0x80]; 4211 }; 4212 4213 enum { 4214 MLX5_DCTC_STATE_ACTIVE = 0x0, 4215 MLX5_DCTC_STATE_DRAINING = 0x1, 4216 MLX5_DCTC_STATE_DRAINED = 0x2, 4217 }; 4218 4219 enum { 4220 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4221 MLX5_DCTC_CS_RES_NA = 0x1, 4222 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4223 }; 4224 4225 enum { 4226 MLX5_DCTC_MTU_256_BYTES = 0x1, 4227 MLX5_DCTC_MTU_512_BYTES = 0x2, 4228 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4229 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4230 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4231 }; 4232 4233 struct mlx5_ifc_dctc_bits { 4234 u8 reserved_at_0[0x4]; 4235 u8 state[0x4]; 4236 u8 reserved_at_8[0x18]; 4237 4238 u8 reserved_at_20[0x8]; 4239 u8 user_index[0x18]; 4240 4241 u8 reserved_at_40[0x8]; 4242 u8 cqn[0x18]; 4243 4244 u8 counter_set_id[0x8]; 4245 u8 atomic_mode[0x4]; 4246 u8 rre[0x1]; 4247 u8 rwe[0x1]; 4248 u8 rae[0x1]; 4249 u8 atomic_like_write_en[0x1]; 4250 u8 latency_sensitive[0x1]; 4251 u8 rlky[0x1]; 4252 u8 free_ar[0x1]; 4253 u8 reserved_at_73[0xd]; 4254 4255 u8 reserved_at_80[0x8]; 4256 u8 cs_res[0x8]; 4257 u8 reserved_at_90[0x3]; 4258 u8 min_rnr_nak[0x5]; 4259 u8 reserved_at_98[0x8]; 4260 4261 u8 reserved_at_a0[0x8]; 4262 u8 srqn_xrqn[0x18]; 4263 4264 u8 reserved_at_c0[0x8]; 4265 u8 pd[0x18]; 4266 4267 u8 tclass[0x8]; 4268 u8 reserved_at_e8[0x4]; 4269 u8 flow_label[0x14]; 4270 4271 u8 dc_access_key[0x40]; 4272 4273 u8 reserved_at_140[0x5]; 4274 u8 mtu[0x3]; 4275 u8 port[0x8]; 4276 u8 pkey_index[0x10]; 4277 4278 u8 reserved_at_160[0x8]; 4279 u8 my_addr_index[0x8]; 4280 u8 reserved_at_170[0x8]; 4281 u8 hop_limit[0x8]; 4282 4283 u8 dc_access_key_violation_count[0x20]; 4284 4285 u8 reserved_at_1a0[0x14]; 4286 u8 dei_cfi[0x1]; 4287 u8 eth_prio[0x3]; 4288 u8 ecn[0x2]; 4289 u8 dscp[0x6]; 4290 4291 u8 reserved_at_1c0[0x20]; 4292 u8 ece[0x20]; 4293 }; 4294 4295 enum { 4296 MLX5_CQC_STATUS_OK = 0x0, 4297 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4298 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4299 }; 4300 4301 enum { 4302 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4303 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4304 }; 4305 4306 enum { 4307 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4308 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4309 MLX5_CQC_ST_FIRED = 0xa, 4310 }; 4311 4312 enum { 4313 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4314 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4315 MLX5_CQ_PERIOD_NUM_MODES 4316 }; 4317 4318 struct mlx5_ifc_cqc_bits { 4319 u8 status[0x4]; 4320 u8 reserved_at_4[0x2]; 4321 u8 dbr_umem_valid[0x1]; 4322 u8 apu_cq[0x1]; 4323 u8 cqe_sz[0x3]; 4324 u8 cc[0x1]; 4325 u8 reserved_at_c[0x1]; 4326 u8 scqe_break_moderation_en[0x1]; 4327 u8 oi[0x1]; 4328 u8 cq_period_mode[0x2]; 4329 u8 cqe_comp_en[0x1]; 4330 u8 mini_cqe_res_format[0x2]; 4331 u8 st[0x4]; 4332 u8 reserved_at_18[0x6]; 4333 u8 cqe_compression_layout[0x2]; 4334 4335 u8 reserved_at_20[0x20]; 4336 4337 u8 reserved_at_40[0x14]; 4338 u8 page_offset[0x6]; 4339 u8 reserved_at_5a[0x6]; 4340 4341 u8 reserved_at_60[0x3]; 4342 u8 log_cq_size[0x5]; 4343 u8 uar_page[0x18]; 4344 4345 u8 reserved_at_80[0x4]; 4346 u8 cq_period[0xc]; 4347 u8 cq_max_count[0x10]; 4348 4349 u8 c_eqn_or_apu_element[0x20]; 4350 4351 u8 reserved_at_c0[0x3]; 4352 u8 log_page_size[0x5]; 4353 u8 reserved_at_c8[0x18]; 4354 4355 u8 reserved_at_e0[0x20]; 4356 4357 u8 reserved_at_100[0x8]; 4358 u8 last_notified_index[0x18]; 4359 4360 u8 reserved_at_120[0x8]; 4361 u8 last_solicit_index[0x18]; 4362 4363 u8 reserved_at_140[0x8]; 4364 u8 consumer_counter[0x18]; 4365 4366 u8 reserved_at_160[0x8]; 4367 u8 producer_counter[0x18]; 4368 4369 u8 reserved_at_180[0x40]; 4370 4371 u8 dbr_addr[0x40]; 4372 }; 4373 4374 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4375 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4376 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4377 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4378 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4379 u8 reserved_at_0[0x800]; 4380 }; 4381 4382 struct mlx5_ifc_query_adapter_param_block_bits { 4383 u8 reserved_at_0[0xc0]; 4384 4385 u8 reserved_at_c0[0x8]; 4386 u8 ieee_vendor_id[0x18]; 4387 4388 u8 reserved_at_e0[0x10]; 4389 u8 vsd_vendor_id[0x10]; 4390 4391 u8 vsd[208][0x8]; 4392 4393 u8 vsd_contd_psid[16][0x8]; 4394 }; 4395 4396 enum { 4397 MLX5_XRQC_STATE_GOOD = 0x0, 4398 MLX5_XRQC_STATE_ERROR = 0x1, 4399 }; 4400 4401 enum { 4402 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4403 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4404 }; 4405 4406 enum { 4407 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4408 }; 4409 4410 struct mlx5_ifc_tag_matching_topology_context_bits { 4411 u8 log_matching_list_sz[0x4]; 4412 u8 reserved_at_4[0xc]; 4413 u8 append_next_index[0x10]; 4414 4415 u8 sw_phase_cnt[0x10]; 4416 u8 hw_phase_cnt[0x10]; 4417 4418 u8 reserved_at_40[0x40]; 4419 }; 4420 4421 struct mlx5_ifc_xrqc_bits { 4422 u8 state[0x4]; 4423 u8 rlkey[0x1]; 4424 u8 reserved_at_5[0xf]; 4425 u8 topology[0x4]; 4426 u8 reserved_at_18[0x4]; 4427 u8 offload[0x4]; 4428 4429 u8 reserved_at_20[0x8]; 4430 u8 user_index[0x18]; 4431 4432 u8 reserved_at_40[0x8]; 4433 u8 cqn[0x18]; 4434 4435 u8 reserved_at_60[0xa0]; 4436 4437 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4438 4439 u8 reserved_at_180[0x280]; 4440 4441 struct mlx5_ifc_wq_bits wq; 4442 }; 4443 4444 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4445 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4446 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4447 u8 reserved_at_0[0x20]; 4448 }; 4449 4450 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4451 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4452 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4453 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4454 u8 reserved_at_0[0x20]; 4455 }; 4456 4457 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4458 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4459 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4460 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4461 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4462 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4463 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4464 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4465 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4466 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4467 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4468 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4469 u8 reserved_at_0[0x7c0]; 4470 }; 4471 4472 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4473 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4474 u8 reserved_at_0[0x7c0]; 4475 }; 4476 4477 union mlx5_ifc_event_auto_bits { 4478 struct mlx5_ifc_comp_event_bits comp_event; 4479 struct mlx5_ifc_dct_events_bits dct_events; 4480 struct mlx5_ifc_qp_events_bits qp_events; 4481 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4482 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4483 struct mlx5_ifc_cq_error_bits cq_error; 4484 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4485 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4486 struct mlx5_ifc_gpio_event_bits gpio_event; 4487 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4488 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4489 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4490 u8 reserved_at_0[0xe0]; 4491 }; 4492 4493 struct mlx5_ifc_health_buffer_bits { 4494 u8 reserved_at_0[0x100]; 4495 4496 u8 assert_existptr[0x20]; 4497 4498 u8 assert_callra[0x20]; 4499 4500 u8 reserved_at_140[0x20]; 4501 4502 u8 time[0x20]; 4503 4504 u8 fw_version[0x20]; 4505 4506 u8 hw_id[0x20]; 4507 4508 u8 rfr[0x1]; 4509 u8 reserved_at_1c1[0x3]; 4510 u8 valid[0x1]; 4511 u8 severity[0x3]; 4512 u8 reserved_at_1c8[0x18]; 4513 4514 u8 irisc_index[0x8]; 4515 u8 synd[0x8]; 4516 u8 ext_synd[0x10]; 4517 }; 4518 4519 struct mlx5_ifc_register_loopback_control_bits { 4520 u8 no_lb[0x1]; 4521 u8 reserved_at_1[0x7]; 4522 u8 port[0x8]; 4523 u8 reserved_at_10[0x10]; 4524 4525 u8 reserved_at_20[0x60]; 4526 }; 4527 4528 struct mlx5_ifc_vport_tc_element_bits { 4529 u8 traffic_class[0x4]; 4530 u8 reserved_at_4[0xc]; 4531 u8 vport_number[0x10]; 4532 }; 4533 4534 struct mlx5_ifc_vport_element_bits { 4535 u8 reserved_at_0[0x10]; 4536 u8 vport_number[0x10]; 4537 }; 4538 4539 enum { 4540 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4541 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4542 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4543 }; 4544 4545 struct mlx5_ifc_tsar_element_bits { 4546 u8 reserved_at_0[0x8]; 4547 u8 tsar_type[0x8]; 4548 u8 reserved_at_10[0x10]; 4549 }; 4550 4551 enum { 4552 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4553 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4554 }; 4555 4556 struct mlx5_ifc_teardown_hca_out_bits { 4557 u8 status[0x8]; 4558 u8 reserved_at_8[0x18]; 4559 4560 u8 syndrome[0x20]; 4561 4562 u8 reserved_at_40[0x3f]; 4563 4564 u8 state[0x1]; 4565 }; 4566 4567 enum { 4568 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4569 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4570 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4571 }; 4572 4573 struct mlx5_ifc_teardown_hca_in_bits { 4574 u8 opcode[0x10]; 4575 u8 reserved_at_10[0x10]; 4576 4577 u8 reserved_at_20[0x10]; 4578 u8 op_mod[0x10]; 4579 4580 u8 reserved_at_40[0x10]; 4581 u8 profile[0x10]; 4582 4583 u8 reserved_at_60[0x20]; 4584 }; 4585 4586 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4587 u8 status[0x8]; 4588 u8 reserved_at_8[0x18]; 4589 4590 u8 syndrome[0x20]; 4591 4592 u8 reserved_at_40[0x40]; 4593 }; 4594 4595 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4596 u8 opcode[0x10]; 4597 u8 uid[0x10]; 4598 4599 u8 reserved_at_20[0x10]; 4600 u8 op_mod[0x10]; 4601 4602 u8 reserved_at_40[0x8]; 4603 u8 qpn[0x18]; 4604 4605 u8 reserved_at_60[0x20]; 4606 4607 u8 opt_param_mask[0x20]; 4608 4609 u8 reserved_at_a0[0x20]; 4610 4611 struct mlx5_ifc_qpc_bits qpc; 4612 4613 u8 reserved_at_800[0x80]; 4614 }; 4615 4616 struct mlx5_ifc_sqd2rts_qp_out_bits { 4617 u8 status[0x8]; 4618 u8 reserved_at_8[0x18]; 4619 4620 u8 syndrome[0x20]; 4621 4622 u8 reserved_at_40[0x40]; 4623 }; 4624 4625 struct mlx5_ifc_sqd2rts_qp_in_bits { 4626 u8 opcode[0x10]; 4627 u8 uid[0x10]; 4628 4629 u8 reserved_at_20[0x10]; 4630 u8 op_mod[0x10]; 4631 4632 u8 reserved_at_40[0x8]; 4633 u8 qpn[0x18]; 4634 4635 u8 reserved_at_60[0x20]; 4636 4637 u8 opt_param_mask[0x20]; 4638 4639 u8 reserved_at_a0[0x20]; 4640 4641 struct mlx5_ifc_qpc_bits qpc; 4642 4643 u8 reserved_at_800[0x80]; 4644 }; 4645 4646 struct mlx5_ifc_set_roce_address_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_at_40[0x40]; 4653 }; 4654 4655 struct mlx5_ifc_set_roce_address_in_bits { 4656 u8 opcode[0x10]; 4657 u8 reserved_at_10[0x10]; 4658 4659 u8 reserved_at_20[0x10]; 4660 u8 op_mod[0x10]; 4661 4662 u8 roce_address_index[0x10]; 4663 u8 reserved_at_50[0xc]; 4664 u8 vhca_port_num[0x4]; 4665 4666 u8 reserved_at_60[0x20]; 4667 4668 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4669 }; 4670 4671 struct mlx5_ifc_set_mad_demux_out_bits { 4672 u8 status[0x8]; 4673 u8 reserved_at_8[0x18]; 4674 4675 u8 syndrome[0x20]; 4676 4677 u8 reserved_at_40[0x40]; 4678 }; 4679 4680 enum { 4681 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4682 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4683 }; 4684 4685 struct mlx5_ifc_set_mad_demux_in_bits { 4686 u8 opcode[0x10]; 4687 u8 reserved_at_10[0x10]; 4688 4689 u8 reserved_at_20[0x10]; 4690 u8 op_mod[0x10]; 4691 4692 u8 reserved_at_40[0x20]; 4693 4694 u8 reserved_at_60[0x6]; 4695 u8 demux_mode[0x2]; 4696 u8 reserved_at_68[0x18]; 4697 }; 4698 4699 struct mlx5_ifc_set_l2_table_entry_out_bits { 4700 u8 status[0x8]; 4701 u8 reserved_at_8[0x18]; 4702 4703 u8 syndrome[0x20]; 4704 4705 u8 reserved_at_40[0x40]; 4706 }; 4707 4708 struct mlx5_ifc_set_l2_table_entry_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 reserved_at_40[0x60]; 4716 4717 u8 reserved_at_a0[0x8]; 4718 u8 table_index[0x18]; 4719 4720 u8 reserved_at_c0[0x20]; 4721 4722 u8 reserved_at_e0[0x13]; 4723 u8 vlan_valid[0x1]; 4724 u8 vlan[0xc]; 4725 4726 struct mlx5_ifc_mac_address_layout_bits mac_address; 4727 4728 u8 reserved_at_140[0xc0]; 4729 }; 4730 4731 struct mlx5_ifc_set_issi_out_bits { 4732 u8 status[0x8]; 4733 u8 reserved_at_8[0x18]; 4734 4735 u8 syndrome[0x20]; 4736 4737 u8 reserved_at_40[0x40]; 4738 }; 4739 4740 struct mlx5_ifc_set_issi_in_bits { 4741 u8 opcode[0x10]; 4742 u8 reserved_at_10[0x10]; 4743 4744 u8 reserved_at_20[0x10]; 4745 u8 op_mod[0x10]; 4746 4747 u8 reserved_at_40[0x10]; 4748 u8 current_issi[0x10]; 4749 4750 u8 reserved_at_60[0x20]; 4751 }; 4752 4753 struct mlx5_ifc_set_hca_cap_out_bits { 4754 u8 status[0x8]; 4755 u8 reserved_at_8[0x18]; 4756 4757 u8 syndrome[0x20]; 4758 4759 u8 reserved_at_40[0x40]; 4760 }; 4761 4762 struct mlx5_ifc_set_hca_cap_in_bits { 4763 u8 opcode[0x10]; 4764 u8 reserved_at_10[0x10]; 4765 4766 u8 reserved_at_20[0x10]; 4767 u8 op_mod[0x10]; 4768 4769 u8 other_function[0x1]; 4770 u8 reserved_at_41[0xf]; 4771 u8 function_id[0x10]; 4772 4773 u8 reserved_at_60[0x20]; 4774 4775 union mlx5_ifc_hca_cap_union_bits capability; 4776 }; 4777 4778 enum { 4779 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4780 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4781 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4782 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4783 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4784 }; 4785 4786 struct mlx5_ifc_set_fte_out_bits { 4787 u8 status[0x8]; 4788 u8 reserved_at_8[0x18]; 4789 4790 u8 syndrome[0x20]; 4791 4792 u8 reserved_at_40[0x40]; 4793 }; 4794 4795 struct mlx5_ifc_set_fte_in_bits { 4796 u8 opcode[0x10]; 4797 u8 reserved_at_10[0x10]; 4798 4799 u8 reserved_at_20[0x10]; 4800 u8 op_mod[0x10]; 4801 4802 u8 other_vport[0x1]; 4803 u8 reserved_at_41[0xf]; 4804 u8 vport_number[0x10]; 4805 4806 u8 reserved_at_60[0x20]; 4807 4808 u8 table_type[0x8]; 4809 u8 reserved_at_88[0x18]; 4810 4811 u8 reserved_at_a0[0x8]; 4812 u8 table_id[0x18]; 4813 4814 u8 ignore_flow_level[0x1]; 4815 u8 reserved_at_c1[0x17]; 4816 u8 modify_enable_mask[0x8]; 4817 4818 u8 reserved_at_e0[0x20]; 4819 4820 u8 flow_index[0x20]; 4821 4822 u8 reserved_at_120[0xe0]; 4823 4824 struct mlx5_ifc_flow_context_bits flow_context; 4825 }; 4826 4827 struct mlx5_ifc_rts2rts_qp_out_bits { 4828 u8 status[0x8]; 4829 u8 reserved_at_8[0x18]; 4830 4831 u8 syndrome[0x20]; 4832 4833 u8 reserved_at_40[0x20]; 4834 u8 ece[0x20]; 4835 }; 4836 4837 struct mlx5_ifc_rts2rts_qp_in_bits { 4838 u8 opcode[0x10]; 4839 u8 uid[0x10]; 4840 4841 u8 reserved_at_20[0x10]; 4842 u8 op_mod[0x10]; 4843 4844 u8 reserved_at_40[0x8]; 4845 u8 qpn[0x18]; 4846 4847 u8 reserved_at_60[0x20]; 4848 4849 u8 opt_param_mask[0x20]; 4850 4851 u8 ece[0x20]; 4852 4853 struct mlx5_ifc_qpc_bits qpc; 4854 4855 u8 reserved_at_800[0x80]; 4856 }; 4857 4858 struct mlx5_ifc_rtr2rts_qp_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_at_8[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 reserved_at_40[0x20]; 4865 u8 ece[0x20]; 4866 }; 4867 4868 struct mlx5_ifc_rtr2rts_qp_in_bits { 4869 u8 opcode[0x10]; 4870 u8 uid[0x10]; 4871 4872 u8 reserved_at_20[0x10]; 4873 u8 op_mod[0x10]; 4874 4875 u8 reserved_at_40[0x8]; 4876 u8 qpn[0x18]; 4877 4878 u8 reserved_at_60[0x20]; 4879 4880 u8 opt_param_mask[0x20]; 4881 4882 u8 ece[0x20]; 4883 4884 struct mlx5_ifc_qpc_bits qpc; 4885 4886 u8 reserved_at_800[0x80]; 4887 }; 4888 4889 struct mlx5_ifc_rst2init_qp_out_bits { 4890 u8 status[0x8]; 4891 u8 reserved_at_8[0x18]; 4892 4893 u8 syndrome[0x20]; 4894 4895 u8 reserved_at_40[0x20]; 4896 u8 ece[0x20]; 4897 }; 4898 4899 struct mlx5_ifc_rst2init_qp_in_bits { 4900 u8 opcode[0x10]; 4901 u8 uid[0x10]; 4902 4903 u8 reserved_at_20[0x10]; 4904 u8 op_mod[0x10]; 4905 4906 u8 reserved_at_40[0x8]; 4907 u8 qpn[0x18]; 4908 4909 u8 reserved_at_60[0x20]; 4910 4911 u8 opt_param_mask[0x20]; 4912 4913 u8 ece[0x20]; 4914 4915 struct mlx5_ifc_qpc_bits qpc; 4916 4917 u8 reserved_at_800[0x80]; 4918 }; 4919 4920 struct mlx5_ifc_query_xrq_out_bits { 4921 u8 status[0x8]; 4922 u8 reserved_at_8[0x18]; 4923 4924 u8 syndrome[0x20]; 4925 4926 u8 reserved_at_40[0x40]; 4927 4928 struct mlx5_ifc_xrqc_bits xrq_context; 4929 }; 4930 4931 struct mlx5_ifc_query_xrq_in_bits { 4932 u8 opcode[0x10]; 4933 u8 reserved_at_10[0x10]; 4934 4935 u8 reserved_at_20[0x10]; 4936 u8 op_mod[0x10]; 4937 4938 u8 reserved_at_40[0x8]; 4939 u8 xrqn[0x18]; 4940 4941 u8 reserved_at_60[0x20]; 4942 }; 4943 4944 struct mlx5_ifc_query_xrc_srq_out_bits { 4945 u8 status[0x8]; 4946 u8 reserved_at_8[0x18]; 4947 4948 u8 syndrome[0x20]; 4949 4950 u8 reserved_at_40[0x40]; 4951 4952 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4953 4954 u8 reserved_at_280[0x600]; 4955 4956 u8 pas[][0x40]; 4957 }; 4958 4959 struct mlx5_ifc_query_xrc_srq_in_bits { 4960 u8 opcode[0x10]; 4961 u8 reserved_at_10[0x10]; 4962 4963 u8 reserved_at_20[0x10]; 4964 u8 op_mod[0x10]; 4965 4966 u8 reserved_at_40[0x8]; 4967 u8 xrc_srqn[0x18]; 4968 4969 u8 reserved_at_60[0x20]; 4970 }; 4971 4972 enum { 4973 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4974 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4975 }; 4976 4977 struct mlx5_ifc_query_vport_state_out_bits { 4978 u8 status[0x8]; 4979 u8 reserved_at_8[0x18]; 4980 4981 u8 syndrome[0x20]; 4982 4983 u8 reserved_at_40[0x20]; 4984 4985 u8 reserved_at_60[0x18]; 4986 u8 admin_state[0x4]; 4987 u8 state[0x4]; 4988 }; 4989 4990 enum { 4991 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4992 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4993 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4994 }; 4995 4996 struct mlx5_ifc_arm_monitor_counter_in_bits { 4997 u8 opcode[0x10]; 4998 u8 uid[0x10]; 4999 5000 u8 reserved_at_20[0x10]; 5001 u8 op_mod[0x10]; 5002 5003 u8 reserved_at_40[0x20]; 5004 5005 u8 reserved_at_60[0x20]; 5006 }; 5007 5008 struct mlx5_ifc_arm_monitor_counter_out_bits { 5009 u8 status[0x8]; 5010 u8 reserved_at_8[0x18]; 5011 5012 u8 syndrome[0x20]; 5013 5014 u8 reserved_at_40[0x40]; 5015 }; 5016 5017 enum { 5018 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5019 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5020 }; 5021 5022 enum mlx5_monitor_counter_ppcnt { 5023 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5024 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5025 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5026 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5027 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5028 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5029 }; 5030 5031 enum { 5032 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5033 }; 5034 5035 struct mlx5_ifc_monitor_counter_output_bits { 5036 u8 reserved_at_0[0x4]; 5037 u8 type[0x4]; 5038 u8 reserved_at_8[0x8]; 5039 u8 counter[0x10]; 5040 5041 u8 counter_group_id[0x20]; 5042 }; 5043 5044 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5045 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5046 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5047 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5048 5049 struct mlx5_ifc_set_monitor_counter_in_bits { 5050 u8 opcode[0x10]; 5051 u8 uid[0x10]; 5052 5053 u8 reserved_at_20[0x10]; 5054 u8 op_mod[0x10]; 5055 5056 u8 reserved_at_40[0x10]; 5057 u8 num_of_counters[0x10]; 5058 5059 u8 reserved_at_60[0x20]; 5060 5061 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5062 }; 5063 5064 struct mlx5_ifc_set_monitor_counter_out_bits { 5065 u8 status[0x8]; 5066 u8 reserved_at_8[0x18]; 5067 5068 u8 syndrome[0x20]; 5069 5070 u8 reserved_at_40[0x40]; 5071 }; 5072 5073 struct mlx5_ifc_query_vport_state_in_bits { 5074 u8 opcode[0x10]; 5075 u8 reserved_at_10[0x10]; 5076 5077 u8 reserved_at_20[0x10]; 5078 u8 op_mod[0x10]; 5079 5080 u8 other_vport[0x1]; 5081 u8 reserved_at_41[0xf]; 5082 u8 vport_number[0x10]; 5083 5084 u8 reserved_at_60[0x20]; 5085 }; 5086 5087 struct mlx5_ifc_query_vnic_env_out_bits { 5088 u8 status[0x8]; 5089 u8 reserved_at_8[0x18]; 5090 5091 u8 syndrome[0x20]; 5092 5093 u8 reserved_at_40[0x40]; 5094 5095 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5096 }; 5097 5098 enum { 5099 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5100 }; 5101 5102 struct mlx5_ifc_query_vnic_env_in_bits { 5103 u8 opcode[0x10]; 5104 u8 reserved_at_10[0x10]; 5105 5106 u8 reserved_at_20[0x10]; 5107 u8 op_mod[0x10]; 5108 5109 u8 other_vport[0x1]; 5110 u8 reserved_at_41[0xf]; 5111 u8 vport_number[0x10]; 5112 5113 u8 reserved_at_60[0x20]; 5114 }; 5115 5116 struct mlx5_ifc_query_vport_counter_out_bits { 5117 u8 status[0x8]; 5118 u8 reserved_at_8[0x18]; 5119 5120 u8 syndrome[0x20]; 5121 5122 u8 reserved_at_40[0x40]; 5123 5124 struct mlx5_ifc_traffic_counter_bits received_errors; 5125 5126 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5127 5128 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5129 5130 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5131 5132 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5133 5134 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5135 5136 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5137 5138 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5139 5140 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5141 5142 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5143 5144 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5145 5146 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5147 5148 u8 reserved_at_680[0xa00]; 5149 }; 5150 5151 enum { 5152 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5153 }; 5154 5155 struct mlx5_ifc_query_vport_counter_in_bits { 5156 u8 opcode[0x10]; 5157 u8 reserved_at_10[0x10]; 5158 5159 u8 reserved_at_20[0x10]; 5160 u8 op_mod[0x10]; 5161 5162 u8 other_vport[0x1]; 5163 u8 reserved_at_41[0xb]; 5164 u8 port_num[0x4]; 5165 u8 vport_number[0x10]; 5166 5167 u8 reserved_at_60[0x60]; 5168 5169 u8 clear[0x1]; 5170 u8 reserved_at_c1[0x1f]; 5171 5172 u8 reserved_at_e0[0x20]; 5173 }; 5174 5175 struct mlx5_ifc_query_tis_out_bits { 5176 u8 status[0x8]; 5177 u8 reserved_at_8[0x18]; 5178 5179 u8 syndrome[0x20]; 5180 5181 u8 reserved_at_40[0x40]; 5182 5183 struct mlx5_ifc_tisc_bits tis_context; 5184 }; 5185 5186 struct mlx5_ifc_query_tis_in_bits { 5187 u8 opcode[0x10]; 5188 u8 reserved_at_10[0x10]; 5189 5190 u8 reserved_at_20[0x10]; 5191 u8 op_mod[0x10]; 5192 5193 u8 reserved_at_40[0x8]; 5194 u8 tisn[0x18]; 5195 5196 u8 reserved_at_60[0x20]; 5197 }; 5198 5199 struct mlx5_ifc_query_tir_out_bits { 5200 u8 status[0x8]; 5201 u8 reserved_at_8[0x18]; 5202 5203 u8 syndrome[0x20]; 5204 5205 u8 reserved_at_40[0xc0]; 5206 5207 struct mlx5_ifc_tirc_bits tir_context; 5208 }; 5209 5210 struct mlx5_ifc_query_tir_in_bits { 5211 u8 opcode[0x10]; 5212 u8 reserved_at_10[0x10]; 5213 5214 u8 reserved_at_20[0x10]; 5215 u8 op_mod[0x10]; 5216 5217 u8 reserved_at_40[0x8]; 5218 u8 tirn[0x18]; 5219 5220 u8 reserved_at_60[0x20]; 5221 }; 5222 5223 struct mlx5_ifc_query_srq_out_bits { 5224 u8 status[0x8]; 5225 u8 reserved_at_8[0x18]; 5226 5227 u8 syndrome[0x20]; 5228 5229 u8 reserved_at_40[0x40]; 5230 5231 struct mlx5_ifc_srqc_bits srq_context_entry; 5232 5233 u8 reserved_at_280[0x600]; 5234 5235 u8 pas[][0x40]; 5236 }; 5237 5238 struct mlx5_ifc_query_srq_in_bits { 5239 u8 opcode[0x10]; 5240 u8 reserved_at_10[0x10]; 5241 5242 u8 reserved_at_20[0x10]; 5243 u8 op_mod[0x10]; 5244 5245 u8 reserved_at_40[0x8]; 5246 u8 srqn[0x18]; 5247 5248 u8 reserved_at_60[0x20]; 5249 }; 5250 5251 struct mlx5_ifc_query_sq_out_bits { 5252 u8 status[0x8]; 5253 u8 reserved_at_8[0x18]; 5254 5255 u8 syndrome[0x20]; 5256 5257 u8 reserved_at_40[0xc0]; 5258 5259 struct mlx5_ifc_sqc_bits sq_context; 5260 }; 5261 5262 struct mlx5_ifc_query_sq_in_bits { 5263 u8 opcode[0x10]; 5264 u8 reserved_at_10[0x10]; 5265 5266 u8 reserved_at_20[0x10]; 5267 u8 op_mod[0x10]; 5268 5269 u8 reserved_at_40[0x8]; 5270 u8 sqn[0x18]; 5271 5272 u8 reserved_at_60[0x20]; 5273 }; 5274 5275 struct mlx5_ifc_query_special_contexts_out_bits { 5276 u8 status[0x8]; 5277 u8 reserved_at_8[0x18]; 5278 5279 u8 syndrome[0x20]; 5280 5281 u8 dump_fill_mkey[0x20]; 5282 5283 u8 resd_lkey[0x20]; 5284 5285 u8 null_mkey[0x20]; 5286 5287 u8 terminate_scatter_list_mkey[0x20]; 5288 5289 u8 repeated_mkey[0x20]; 5290 5291 u8 reserved_at_a0[0x20]; 5292 }; 5293 5294 struct mlx5_ifc_query_special_contexts_in_bits { 5295 u8 opcode[0x10]; 5296 u8 reserved_at_10[0x10]; 5297 5298 u8 reserved_at_20[0x10]; 5299 u8 op_mod[0x10]; 5300 5301 u8 reserved_at_40[0x40]; 5302 }; 5303 5304 struct mlx5_ifc_query_scheduling_element_out_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 reserved_at_20[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_at_40[0xc0]; 5312 5313 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5314 5315 u8 reserved_at_300[0x100]; 5316 }; 5317 5318 enum { 5319 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5320 SCHEDULING_HIERARCHY_NIC = 0x3, 5321 }; 5322 5323 struct mlx5_ifc_query_scheduling_element_in_bits { 5324 u8 opcode[0x10]; 5325 u8 reserved_at_10[0x10]; 5326 5327 u8 reserved_at_20[0x10]; 5328 u8 op_mod[0x10]; 5329 5330 u8 scheduling_hierarchy[0x8]; 5331 u8 reserved_at_48[0x18]; 5332 5333 u8 scheduling_element_id[0x20]; 5334 5335 u8 reserved_at_80[0x180]; 5336 }; 5337 5338 struct mlx5_ifc_query_rqt_out_bits { 5339 u8 status[0x8]; 5340 u8 reserved_at_8[0x18]; 5341 5342 u8 syndrome[0x20]; 5343 5344 u8 reserved_at_40[0xc0]; 5345 5346 struct mlx5_ifc_rqtc_bits rqt_context; 5347 }; 5348 5349 struct mlx5_ifc_query_rqt_in_bits { 5350 u8 opcode[0x10]; 5351 u8 reserved_at_10[0x10]; 5352 5353 u8 reserved_at_20[0x10]; 5354 u8 op_mod[0x10]; 5355 5356 u8 reserved_at_40[0x8]; 5357 u8 rqtn[0x18]; 5358 5359 u8 reserved_at_60[0x20]; 5360 }; 5361 5362 struct mlx5_ifc_query_rq_out_bits { 5363 u8 status[0x8]; 5364 u8 reserved_at_8[0x18]; 5365 5366 u8 syndrome[0x20]; 5367 5368 u8 reserved_at_40[0xc0]; 5369 5370 struct mlx5_ifc_rqc_bits rq_context; 5371 }; 5372 5373 struct mlx5_ifc_query_rq_in_bits { 5374 u8 opcode[0x10]; 5375 u8 reserved_at_10[0x10]; 5376 5377 u8 reserved_at_20[0x10]; 5378 u8 op_mod[0x10]; 5379 5380 u8 reserved_at_40[0x8]; 5381 u8 rqn[0x18]; 5382 5383 u8 reserved_at_60[0x20]; 5384 }; 5385 5386 struct mlx5_ifc_query_roce_address_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_at_8[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_at_40[0x40]; 5393 5394 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5395 }; 5396 5397 struct mlx5_ifc_query_roce_address_in_bits { 5398 u8 opcode[0x10]; 5399 u8 reserved_at_10[0x10]; 5400 5401 u8 reserved_at_20[0x10]; 5402 u8 op_mod[0x10]; 5403 5404 u8 roce_address_index[0x10]; 5405 u8 reserved_at_50[0xc]; 5406 u8 vhca_port_num[0x4]; 5407 5408 u8 reserved_at_60[0x20]; 5409 }; 5410 5411 struct mlx5_ifc_query_rmp_out_bits { 5412 u8 status[0x8]; 5413 u8 reserved_at_8[0x18]; 5414 5415 u8 syndrome[0x20]; 5416 5417 u8 reserved_at_40[0xc0]; 5418 5419 struct mlx5_ifc_rmpc_bits rmp_context; 5420 }; 5421 5422 struct mlx5_ifc_query_rmp_in_bits { 5423 u8 opcode[0x10]; 5424 u8 reserved_at_10[0x10]; 5425 5426 u8 reserved_at_20[0x10]; 5427 u8 op_mod[0x10]; 5428 5429 u8 reserved_at_40[0x8]; 5430 u8 rmpn[0x18]; 5431 5432 u8 reserved_at_60[0x20]; 5433 }; 5434 5435 struct mlx5_ifc_cqe_error_syndrome_bits { 5436 u8 hw_error_syndrome[0x8]; 5437 u8 hw_syndrome_type[0x4]; 5438 u8 reserved_at_c[0x4]; 5439 u8 vendor_error_syndrome[0x8]; 5440 u8 syndrome[0x8]; 5441 }; 5442 5443 struct mlx5_ifc_qp_context_extension_bits { 5444 u8 reserved_at_0[0x60]; 5445 5446 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5447 5448 u8 reserved_at_80[0x580]; 5449 }; 5450 5451 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5452 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5453 5454 u8 pas[0][0x40]; 5455 }; 5456 5457 struct mlx5_ifc_qp_pas_list_in_bits { 5458 struct mlx5_ifc_cmd_pas_bits pas[0]; 5459 }; 5460 5461 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5462 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5463 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5464 }; 5465 5466 struct mlx5_ifc_query_qp_out_bits { 5467 u8 status[0x8]; 5468 u8 reserved_at_8[0x18]; 5469 5470 u8 syndrome[0x20]; 5471 5472 u8 reserved_at_40[0x40]; 5473 5474 u8 opt_param_mask[0x20]; 5475 5476 u8 ece[0x20]; 5477 5478 struct mlx5_ifc_qpc_bits qpc; 5479 5480 u8 reserved_at_800[0x80]; 5481 5482 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5483 }; 5484 5485 struct mlx5_ifc_query_qp_in_bits { 5486 u8 opcode[0x10]; 5487 u8 reserved_at_10[0x10]; 5488 5489 u8 reserved_at_20[0x10]; 5490 u8 op_mod[0x10]; 5491 5492 u8 qpc_ext[0x1]; 5493 u8 reserved_at_41[0x7]; 5494 u8 qpn[0x18]; 5495 5496 u8 reserved_at_60[0x20]; 5497 }; 5498 5499 struct mlx5_ifc_query_q_counter_out_bits { 5500 u8 status[0x8]; 5501 u8 reserved_at_8[0x18]; 5502 5503 u8 syndrome[0x20]; 5504 5505 u8 reserved_at_40[0x40]; 5506 5507 u8 rx_write_requests[0x20]; 5508 5509 u8 reserved_at_a0[0x20]; 5510 5511 u8 rx_read_requests[0x20]; 5512 5513 u8 reserved_at_e0[0x20]; 5514 5515 u8 rx_atomic_requests[0x20]; 5516 5517 u8 reserved_at_120[0x20]; 5518 5519 u8 rx_dct_connect[0x20]; 5520 5521 u8 reserved_at_160[0x20]; 5522 5523 u8 out_of_buffer[0x20]; 5524 5525 u8 reserved_at_1a0[0x20]; 5526 5527 u8 out_of_sequence[0x20]; 5528 5529 u8 reserved_at_1e0[0x20]; 5530 5531 u8 duplicate_request[0x20]; 5532 5533 u8 reserved_at_220[0x20]; 5534 5535 u8 rnr_nak_retry_err[0x20]; 5536 5537 u8 reserved_at_260[0x20]; 5538 5539 u8 packet_seq_err[0x20]; 5540 5541 u8 reserved_at_2a0[0x20]; 5542 5543 u8 implied_nak_seq_err[0x20]; 5544 5545 u8 reserved_at_2e0[0x20]; 5546 5547 u8 local_ack_timeout_err[0x20]; 5548 5549 u8 reserved_at_320[0xa0]; 5550 5551 u8 resp_local_length_error[0x20]; 5552 5553 u8 req_local_length_error[0x20]; 5554 5555 u8 resp_local_qp_error[0x20]; 5556 5557 u8 local_operation_error[0x20]; 5558 5559 u8 resp_local_protection[0x20]; 5560 5561 u8 req_local_protection[0x20]; 5562 5563 u8 resp_cqe_error[0x20]; 5564 5565 u8 req_cqe_error[0x20]; 5566 5567 u8 req_mw_binding[0x20]; 5568 5569 u8 req_bad_response[0x20]; 5570 5571 u8 req_remote_invalid_request[0x20]; 5572 5573 u8 resp_remote_invalid_request[0x20]; 5574 5575 u8 req_remote_access_errors[0x20]; 5576 5577 u8 resp_remote_access_errors[0x20]; 5578 5579 u8 req_remote_operation_errors[0x20]; 5580 5581 u8 req_transport_retries_exceeded[0x20]; 5582 5583 u8 cq_overflow[0x20]; 5584 5585 u8 resp_cqe_flush_error[0x20]; 5586 5587 u8 req_cqe_flush_error[0x20]; 5588 5589 u8 reserved_at_620[0x20]; 5590 5591 u8 roce_adp_retrans[0x20]; 5592 5593 u8 roce_adp_retrans_to[0x20]; 5594 5595 u8 roce_slow_restart[0x20]; 5596 5597 u8 roce_slow_restart_cnps[0x20]; 5598 5599 u8 roce_slow_restart_trans[0x20]; 5600 5601 u8 reserved_at_6e0[0x120]; 5602 }; 5603 5604 struct mlx5_ifc_query_q_counter_in_bits { 5605 u8 opcode[0x10]; 5606 u8 reserved_at_10[0x10]; 5607 5608 u8 reserved_at_20[0x10]; 5609 u8 op_mod[0x10]; 5610 5611 u8 reserved_at_40[0x80]; 5612 5613 u8 clear[0x1]; 5614 u8 reserved_at_c1[0x1f]; 5615 5616 u8 reserved_at_e0[0x18]; 5617 u8 counter_set_id[0x8]; 5618 }; 5619 5620 struct mlx5_ifc_query_pages_out_bits { 5621 u8 status[0x8]; 5622 u8 reserved_at_8[0x18]; 5623 5624 u8 syndrome[0x20]; 5625 5626 u8 embedded_cpu_function[0x1]; 5627 u8 reserved_at_41[0xf]; 5628 u8 function_id[0x10]; 5629 5630 u8 num_pages[0x20]; 5631 }; 5632 5633 enum { 5634 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5635 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5636 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5637 }; 5638 5639 struct mlx5_ifc_query_pages_in_bits { 5640 u8 opcode[0x10]; 5641 u8 reserved_at_10[0x10]; 5642 5643 u8 reserved_at_20[0x10]; 5644 u8 op_mod[0x10]; 5645 5646 u8 embedded_cpu_function[0x1]; 5647 u8 reserved_at_41[0xf]; 5648 u8 function_id[0x10]; 5649 5650 u8 reserved_at_60[0x20]; 5651 }; 5652 5653 struct mlx5_ifc_query_nic_vport_context_out_bits { 5654 u8 status[0x8]; 5655 u8 reserved_at_8[0x18]; 5656 5657 u8 syndrome[0x20]; 5658 5659 u8 reserved_at_40[0x40]; 5660 5661 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5662 }; 5663 5664 struct mlx5_ifc_query_nic_vport_context_in_bits { 5665 u8 opcode[0x10]; 5666 u8 reserved_at_10[0x10]; 5667 5668 u8 reserved_at_20[0x10]; 5669 u8 op_mod[0x10]; 5670 5671 u8 other_vport[0x1]; 5672 u8 reserved_at_41[0xf]; 5673 u8 vport_number[0x10]; 5674 5675 u8 reserved_at_60[0x5]; 5676 u8 allowed_list_type[0x3]; 5677 u8 reserved_at_68[0x18]; 5678 }; 5679 5680 struct mlx5_ifc_query_mkey_out_bits { 5681 u8 status[0x8]; 5682 u8 reserved_at_8[0x18]; 5683 5684 u8 syndrome[0x20]; 5685 5686 u8 reserved_at_40[0x40]; 5687 5688 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5689 5690 u8 reserved_at_280[0x600]; 5691 5692 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5693 5694 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5695 }; 5696 5697 struct mlx5_ifc_query_mkey_in_bits { 5698 u8 opcode[0x10]; 5699 u8 reserved_at_10[0x10]; 5700 5701 u8 reserved_at_20[0x10]; 5702 u8 op_mod[0x10]; 5703 5704 u8 reserved_at_40[0x8]; 5705 u8 mkey_index[0x18]; 5706 5707 u8 pg_access[0x1]; 5708 u8 reserved_at_61[0x1f]; 5709 }; 5710 5711 struct mlx5_ifc_query_mad_demux_out_bits { 5712 u8 status[0x8]; 5713 u8 reserved_at_8[0x18]; 5714 5715 u8 syndrome[0x20]; 5716 5717 u8 reserved_at_40[0x40]; 5718 5719 u8 mad_dumux_parameters_block[0x20]; 5720 }; 5721 5722 struct mlx5_ifc_query_mad_demux_in_bits { 5723 u8 opcode[0x10]; 5724 u8 reserved_at_10[0x10]; 5725 5726 u8 reserved_at_20[0x10]; 5727 u8 op_mod[0x10]; 5728 5729 u8 reserved_at_40[0x40]; 5730 }; 5731 5732 struct mlx5_ifc_query_l2_table_entry_out_bits { 5733 u8 status[0x8]; 5734 u8 reserved_at_8[0x18]; 5735 5736 u8 syndrome[0x20]; 5737 5738 u8 reserved_at_40[0xa0]; 5739 5740 u8 reserved_at_e0[0x13]; 5741 u8 vlan_valid[0x1]; 5742 u8 vlan[0xc]; 5743 5744 struct mlx5_ifc_mac_address_layout_bits mac_address; 5745 5746 u8 reserved_at_140[0xc0]; 5747 }; 5748 5749 struct mlx5_ifc_query_l2_table_entry_in_bits { 5750 u8 opcode[0x10]; 5751 u8 reserved_at_10[0x10]; 5752 5753 u8 reserved_at_20[0x10]; 5754 u8 op_mod[0x10]; 5755 5756 u8 reserved_at_40[0x60]; 5757 5758 u8 reserved_at_a0[0x8]; 5759 u8 table_index[0x18]; 5760 5761 u8 reserved_at_c0[0x140]; 5762 }; 5763 5764 struct mlx5_ifc_query_issi_out_bits { 5765 u8 status[0x8]; 5766 u8 reserved_at_8[0x18]; 5767 5768 u8 syndrome[0x20]; 5769 5770 u8 reserved_at_40[0x10]; 5771 u8 current_issi[0x10]; 5772 5773 u8 reserved_at_60[0xa0]; 5774 5775 u8 reserved_at_100[76][0x8]; 5776 u8 supported_issi_dw0[0x20]; 5777 }; 5778 5779 struct mlx5_ifc_query_issi_in_bits { 5780 u8 opcode[0x10]; 5781 u8 reserved_at_10[0x10]; 5782 5783 u8 reserved_at_20[0x10]; 5784 u8 op_mod[0x10]; 5785 5786 u8 reserved_at_40[0x40]; 5787 }; 5788 5789 struct mlx5_ifc_set_driver_version_out_bits { 5790 u8 status[0x8]; 5791 u8 reserved_0[0x18]; 5792 5793 u8 syndrome[0x20]; 5794 u8 reserved_1[0x40]; 5795 }; 5796 5797 struct mlx5_ifc_set_driver_version_in_bits { 5798 u8 opcode[0x10]; 5799 u8 reserved_0[0x10]; 5800 5801 u8 reserved_1[0x10]; 5802 u8 op_mod[0x10]; 5803 5804 u8 reserved_2[0x40]; 5805 u8 driver_version[64][0x8]; 5806 }; 5807 5808 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5809 u8 status[0x8]; 5810 u8 reserved_at_8[0x18]; 5811 5812 u8 syndrome[0x20]; 5813 5814 u8 reserved_at_40[0x40]; 5815 5816 struct mlx5_ifc_pkey_bits pkey[]; 5817 }; 5818 5819 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5820 u8 opcode[0x10]; 5821 u8 reserved_at_10[0x10]; 5822 5823 u8 reserved_at_20[0x10]; 5824 u8 op_mod[0x10]; 5825 5826 u8 other_vport[0x1]; 5827 u8 reserved_at_41[0xb]; 5828 u8 port_num[0x4]; 5829 u8 vport_number[0x10]; 5830 5831 u8 reserved_at_60[0x10]; 5832 u8 pkey_index[0x10]; 5833 }; 5834 5835 enum { 5836 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5837 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5838 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5839 }; 5840 5841 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5842 u8 status[0x8]; 5843 u8 reserved_at_8[0x18]; 5844 5845 u8 syndrome[0x20]; 5846 5847 u8 reserved_at_40[0x20]; 5848 5849 u8 gids_num[0x10]; 5850 u8 reserved_at_70[0x10]; 5851 5852 struct mlx5_ifc_array128_auto_bits gid[]; 5853 }; 5854 5855 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5856 u8 opcode[0x10]; 5857 u8 reserved_at_10[0x10]; 5858 5859 u8 reserved_at_20[0x10]; 5860 u8 op_mod[0x10]; 5861 5862 u8 other_vport[0x1]; 5863 u8 reserved_at_41[0xb]; 5864 u8 port_num[0x4]; 5865 u8 vport_number[0x10]; 5866 5867 u8 reserved_at_60[0x10]; 5868 u8 gid_index[0x10]; 5869 }; 5870 5871 struct mlx5_ifc_query_hca_vport_context_out_bits { 5872 u8 status[0x8]; 5873 u8 reserved_at_8[0x18]; 5874 5875 u8 syndrome[0x20]; 5876 5877 u8 reserved_at_40[0x40]; 5878 5879 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5880 }; 5881 5882 struct mlx5_ifc_query_hca_vport_context_in_bits { 5883 u8 opcode[0x10]; 5884 u8 reserved_at_10[0x10]; 5885 5886 u8 reserved_at_20[0x10]; 5887 u8 op_mod[0x10]; 5888 5889 u8 other_vport[0x1]; 5890 u8 reserved_at_41[0xb]; 5891 u8 port_num[0x4]; 5892 u8 vport_number[0x10]; 5893 5894 u8 reserved_at_60[0x20]; 5895 }; 5896 5897 struct mlx5_ifc_query_hca_cap_out_bits { 5898 u8 status[0x8]; 5899 u8 reserved_at_8[0x18]; 5900 5901 u8 syndrome[0x20]; 5902 5903 u8 reserved_at_40[0x40]; 5904 5905 union mlx5_ifc_hca_cap_union_bits capability; 5906 }; 5907 5908 struct mlx5_ifc_query_hca_cap_in_bits { 5909 u8 opcode[0x10]; 5910 u8 reserved_at_10[0x10]; 5911 5912 u8 reserved_at_20[0x10]; 5913 u8 op_mod[0x10]; 5914 5915 u8 other_function[0x1]; 5916 u8 reserved_at_41[0xf]; 5917 u8 function_id[0x10]; 5918 5919 u8 reserved_at_60[0x20]; 5920 }; 5921 5922 struct mlx5_ifc_other_hca_cap_bits { 5923 u8 roce[0x1]; 5924 u8 reserved_at_1[0x27f]; 5925 }; 5926 5927 struct mlx5_ifc_query_other_hca_cap_out_bits { 5928 u8 status[0x8]; 5929 u8 reserved_at_8[0x18]; 5930 5931 u8 syndrome[0x20]; 5932 5933 u8 reserved_at_40[0x40]; 5934 5935 struct mlx5_ifc_other_hca_cap_bits other_capability; 5936 }; 5937 5938 struct mlx5_ifc_query_other_hca_cap_in_bits { 5939 u8 opcode[0x10]; 5940 u8 reserved_at_10[0x10]; 5941 5942 u8 reserved_at_20[0x10]; 5943 u8 op_mod[0x10]; 5944 5945 u8 reserved_at_40[0x10]; 5946 u8 function_id[0x10]; 5947 5948 u8 reserved_at_60[0x20]; 5949 }; 5950 5951 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5952 u8 status[0x8]; 5953 u8 reserved_at_8[0x18]; 5954 5955 u8 syndrome[0x20]; 5956 5957 u8 reserved_at_40[0x40]; 5958 }; 5959 5960 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5961 u8 opcode[0x10]; 5962 u8 reserved_at_10[0x10]; 5963 5964 u8 reserved_at_20[0x10]; 5965 u8 op_mod[0x10]; 5966 5967 u8 reserved_at_40[0x10]; 5968 u8 function_id[0x10]; 5969 u8 field_select[0x20]; 5970 5971 struct mlx5_ifc_other_hca_cap_bits other_capability; 5972 }; 5973 5974 struct mlx5_ifc_flow_table_context_bits { 5975 u8 reformat_en[0x1]; 5976 u8 decap_en[0x1]; 5977 u8 sw_owner[0x1]; 5978 u8 termination_table[0x1]; 5979 u8 table_miss_action[0x4]; 5980 u8 level[0x8]; 5981 u8 reserved_at_10[0x8]; 5982 u8 log_size[0x8]; 5983 5984 u8 reserved_at_20[0x8]; 5985 u8 table_miss_id[0x18]; 5986 5987 u8 reserved_at_40[0x8]; 5988 u8 lag_master_next_table_id[0x18]; 5989 5990 u8 reserved_at_60[0x60]; 5991 5992 u8 sw_owner_icm_root_1[0x40]; 5993 5994 u8 sw_owner_icm_root_0[0x40]; 5995 5996 }; 5997 5998 struct mlx5_ifc_query_flow_table_out_bits { 5999 u8 status[0x8]; 6000 u8 reserved_at_8[0x18]; 6001 6002 u8 syndrome[0x20]; 6003 6004 u8 reserved_at_40[0x80]; 6005 6006 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6007 }; 6008 6009 struct mlx5_ifc_query_flow_table_in_bits { 6010 u8 opcode[0x10]; 6011 u8 reserved_at_10[0x10]; 6012 6013 u8 reserved_at_20[0x10]; 6014 u8 op_mod[0x10]; 6015 6016 u8 reserved_at_40[0x40]; 6017 6018 u8 table_type[0x8]; 6019 u8 reserved_at_88[0x18]; 6020 6021 u8 reserved_at_a0[0x8]; 6022 u8 table_id[0x18]; 6023 6024 u8 reserved_at_c0[0x140]; 6025 }; 6026 6027 struct mlx5_ifc_query_fte_out_bits { 6028 u8 status[0x8]; 6029 u8 reserved_at_8[0x18]; 6030 6031 u8 syndrome[0x20]; 6032 6033 u8 reserved_at_40[0x1c0]; 6034 6035 struct mlx5_ifc_flow_context_bits flow_context; 6036 }; 6037 6038 struct mlx5_ifc_query_fte_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_at_10[0x10]; 6041 6042 u8 reserved_at_20[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 reserved_at_40[0x40]; 6046 6047 u8 table_type[0x8]; 6048 u8 reserved_at_88[0x18]; 6049 6050 u8 reserved_at_a0[0x8]; 6051 u8 table_id[0x18]; 6052 6053 u8 reserved_at_c0[0x40]; 6054 6055 u8 flow_index[0x20]; 6056 6057 u8 reserved_at_120[0xe0]; 6058 }; 6059 6060 struct mlx5_ifc_match_definer_format_0_bits { 6061 u8 reserved_at_0[0x100]; 6062 6063 u8 metadata_reg_c_0[0x20]; 6064 6065 u8 metadata_reg_c_1[0x20]; 6066 6067 u8 outer_dmac_47_16[0x20]; 6068 6069 u8 outer_dmac_15_0[0x10]; 6070 u8 outer_ethertype[0x10]; 6071 6072 u8 reserved_at_180[0x1]; 6073 u8 sx_sniffer[0x1]; 6074 u8 functional_lb[0x1]; 6075 u8 outer_ip_frag[0x1]; 6076 u8 outer_qp_type[0x2]; 6077 u8 outer_encap_type[0x2]; 6078 u8 port_number[0x2]; 6079 u8 outer_l3_type[0x2]; 6080 u8 outer_l4_type[0x2]; 6081 u8 outer_first_vlan_type[0x2]; 6082 u8 outer_first_vlan_prio[0x3]; 6083 u8 outer_first_vlan_cfi[0x1]; 6084 u8 outer_first_vlan_vid[0xc]; 6085 6086 u8 outer_l4_type_ext[0x4]; 6087 u8 reserved_at_1a4[0x2]; 6088 u8 outer_ipsec_layer[0x2]; 6089 u8 outer_l2_type[0x2]; 6090 u8 force_lb[0x1]; 6091 u8 outer_l2_ok[0x1]; 6092 u8 outer_l3_ok[0x1]; 6093 u8 outer_l4_ok[0x1]; 6094 u8 outer_second_vlan_type[0x2]; 6095 u8 outer_second_vlan_prio[0x3]; 6096 u8 outer_second_vlan_cfi[0x1]; 6097 u8 outer_second_vlan_vid[0xc]; 6098 6099 u8 outer_smac_47_16[0x20]; 6100 6101 u8 outer_smac_15_0[0x10]; 6102 u8 inner_ipv4_checksum_ok[0x1]; 6103 u8 inner_l4_checksum_ok[0x1]; 6104 u8 outer_ipv4_checksum_ok[0x1]; 6105 u8 outer_l4_checksum_ok[0x1]; 6106 u8 inner_l3_ok[0x1]; 6107 u8 inner_l4_ok[0x1]; 6108 u8 outer_l3_ok_duplicate[0x1]; 6109 u8 outer_l4_ok_duplicate[0x1]; 6110 u8 outer_tcp_cwr[0x1]; 6111 u8 outer_tcp_ece[0x1]; 6112 u8 outer_tcp_urg[0x1]; 6113 u8 outer_tcp_ack[0x1]; 6114 u8 outer_tcp_psh[0x1]; 6115 u8 outer_tcp_rst[0x1]; 6116 u8 outer_tcp_syn[0x1]; 6117 u8 outer_tcp_fin[0x1]; 6118 }; 6119 6120 struct mlx5_ifc_match_definer_format_22_bits { 6121 u8 reserved_at_0[0x100]; 6122 6123 u8 outer_ip_src_addr[0x20]; 6124 6125 u8 outer_ip_dest_addr[0x20]; 6126 6127 u8 outer_l4_sport[0x10]; 6128 u8 outer_l4_dport[0x10]; 6129 6130 u8 reserved_at_160[0x1]; 6131 u8 sx_sniffer[0x1]; 6132 u8 functional_lb[0x1]; 6133 u8 outer_ip_frag[0x1]; 6134 u8 outer_qp_type[0x2]; 6135 u8 outer_encap_type[0x2]; 6136 u8 port_number[0x2]; 6137 u8 outer_l3_type[0x2]; 6138 u8 outer_l4_type[0x2]; 6139 u8 outer_first_vlan_type[0x2]; 6140 u8 outer_first_vlan_prio[0x3]; 6141 u8 outer_first_vlan_cfi[0x1]; 6142 u8 outer_first_vlan_vid[0xc]; 6143 6144 u8 metadata_reg_c_0[0x20]; 6145 6146 u8 outer_dmac_47_16[0x20]; 6147 6148 u8 outer_smac_47_16[0x20]; 6149 6150 u8 outer_smac_15_0[0x10]; 6151 u8 outer_dmac_15_0[0x10]; 6152 }; 6153 6154 struct mlx5_ifc_match_definer_format_23_bits { 6155 u8 reserved_at_0[0x100]; 6156 6157 u8 inner_ip_src_addr[0x20]; 6158 6159 u8 inner_ip_dest_addr[0x20]; 6160 6161 u8 inner_l4_sport[0x10]; 6162 u8 inner_l4_dport[0x10]; 6163 6164 u8 reserved_at_160[0x1]; 6165 u8 sx_sniffer[0x1]; 6166 u8 functional_lb[0x1]; 6167 u8 inner_ip_frag[0x1]; 6168 u8 inner_qp_type[0x2]; 6169 u8 inner_encap_type[0x2]; 6170 u8 port_number[0x2]; 6171 u8 inner_l3_type[0x2]; 6172 u8 inner_l4_type[0x2]; 6173 u8 inner_first_vlan_type[0x2]; 6174 u8 inner_first_vlan_prio[0x3]; 6175 u8 inner_first_vlan_cfi[0x1]; 6176 u8 inner_first_vlan_vid[0xc]; 6177 6178 u8 tunnel_header_0[0x20]; 6179 6180 u8 inner_dmac_47_16[0x20]; 6181 6182 u8 inner_smac_47_16[0x20]; 6183 6184 u8 inner_smac_15_0[0x10]; 6185 u8 inner_dmac_15_0[0x10]; 6186 }; 6187 6188 struct mlx5_ifc_match_definer_format_29_bits { 6189 u8 reserved_at_0[0xc0]; 6190 6191 u8 outer_ip_dest_addr[0x80]; 6192 6193 u8 outer_ip_src_addr[0x80]; 6194 6195 u8 outer_l4_sport[0x10]; 6196 u8 outer_l4_dport[0x10]; 6197 6198 u8 reserved_at_1e0[0x20]; 6199 }; 6200 6201 struct mlx5_ifc_match_definer_format_30_bits { 6202 u8 reserved_at_0[0xa0]; 6203 6204 u8 outer_ip_dest_addr[0x80]; 6205 6206 u8 outer_ip_src_addr[0x80]; 6207 6208 u8 outer_dmac_47_16[0x20]; 6209 6210 u8 outer_smac_47_16[0x20]; 6211 6212 u8 outer_smac_15_0[0x10]; 6213 u8 outer_dmac_15_0[0x10]; 6214 }; 6215 6216 struct mlx5_ifc_match_definer_format_31_bits { 6217 u8 reserved_at_0[0xc0]; 6218 6219 u8 inner_ip_dest_addr[0x80]; 6220 6221 u8 inner_ip_src_addr[0x80]; 6222 6223 u8 inner_l4_sport[0x10]; 6224 u8 inner_l4_dport[0x10]; 6225 6226 u8 reserved_at_1e0[0x20]; 6227 }; 6228 6229 struct mlx5_ifc_match_definer_format_32_bits { 6230 u8 reserved_at_0[0xa0]; 6231 6232 u8 inner_ip_dest_addr[0x80]; 6233 6234 u8 inner_ip_src_addr[0x80]; 6235 6236 u8 inner_dmac_47_16[0x20]; 6237 6238 u8 inner_smac_47_16[0x20]; 6239 6240 u8 inner_smac_15_0[0x10]; 6241 u8 inner_dmac_15_0[0x10]; 6242 }; 6243 6244 enum { 6245 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6246 }; 6247 6248 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6249 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6250 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6251 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6252 6253 struct mlx5_ifc_match_definer_match_mask_bits { 6254 u8 reserved_at_1c0[5][0x20]; 6255 u8 match_dw_8[0x20]; 6256 u8 match_dw_7[0x20]; 6257 u8 match_dw_6[0x20]; 6258 u8 match_dw_5[0x20]; 6259 u8 match_dw_4[0x20]; 6260 u8 match_dw_3[0x20]; 6261 u8 match_dw_2[0x20]; 6262 u8 match_dw_1[0x20]; 6263 u8 match_dw_0[0x20]; 6264 6265 u8 match_byte_7[0x8]; 6266 u8 match_byte_6[0x8]; 6267 u8 match_byte_5[0x8]; 6268 u8 match_byte_4[0x8]; 6269 6270 u8 match_byte_3[0x8]; 6271 u8 match_byte_2[0x8]; 6272 u8 match_byte_1[0x8]; 6273 u8 match_byte_0[0x8]; 6274 }; 6275 6276 struct mlx5_ifc_match_definer_bits { 6277 u8 modify_field_select[0x40]; 6278 6279 u8 reserved_at_40[0x40]; 6280 6281 u8 reserved_at_80[0x10]; 6282 u8 format_id[0x10]; 6283 6284 u8 reserved_at_a0[0x60]; 6285 6286 u8 format_select_dw3[0x8]; 6287 u8 format_select_dw2[0x8]; 6288 u8 format_select_dw1[0x8]; 6289 u8 format_select_dw0[0x8]; 6290 6291 u8 format_select_dw7[0x8]; 6292 u8 format_select_dw6[0x8]; 6293 u8 format_select_dw5[0x8]; 6294 u8 format_select_dw4[0x8]; 6295 6296 u8 reserved_at_100[0x18]; 6297 u8 format_select_dw8[0x8]; 6298 6299 u8 reserved_at_120[0x20]; 6300 6301 u8 format_select_byte3[0x8]; 6302 u8 format_select_byte2[0x8]; 6303 u8 format_select_byte1[0x8]; 6304 u8 format_select_byte0[0x8]; 6305 6306 u8 format_select_byte7[0x8]; 6307 u8 format_select_byte6[0x8]; 6308 u8 format_select_byte5[0x8]; 6309 u8 format_select_byte4[0x8]; 6310 6311 u8 reserved_at_180[0x40]; 6312 6313 union { 6314 struct { 6315 u8 match_mask[16][0x20]; 6316 }; 6317 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6318 }; 6319 }; 6320 6321 struct mlx5_ifc_general_obj_create_param_bits { 6322 u8 alias_object[0x1]; 6323 u8 reserved_at_1[0x2]; 6324 u8 log_obj_range[0x5]; 6325 u8 reserved_at_8[0x18]; 6326 }; 6327 6328 struct mlx5_ifc_general_obj_query_param_bits { 6329 u8 alias_object[0x1]; 6330 u8 obj_offset[0x1f]; 6331 }; 6332 6333 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6334 u8 opcode[0x10]; 6335 u8 uid[0x10]; 6336 6337 u8 vhca_tunnel_id[0x10]; 6338 u8 obj_type[0x10]; 6339 6340 u8 obj_id[0x20]; 6341 6342 union { 6343 struct mlx5_ifc_general_obj_create_param_bits create; 6344 struct mlx5_ifc_general_obj_query_param_bits query; 6345 } op_param; 6346 }; 6347 6348 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6349 u8 status[0x8]; 6350 u8 reserved_at_8[0x18]; 6351 6352 u8 syndrome[0x20]; 6353 6354 u8 obj_id[0x20]; 6355 6356 u8 reserved_at_60[0x20]; 6357 }; 6358 6359 struct mlx5_ifc_create_match_definer_in_bits { 6360 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6361 6362 struct mlx5_ifc_match_definer_bits obj_context; 6363 }; 6364 6365 struct mlx5_ifc_create_match_definer_out_bits { 6366 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6367 }; 6368 6369 enum { 6370 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6371 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6372 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6373 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6374 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6375 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6376 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6377 }; 6378 6379 struct mlx5_ifc_query_flow_group_out_bits { 6380 u8 status[0x8]; 6381 u8 reserved_at_8[0x18]; 6382 6383 u8 syndrome[0x20]; 6384 6385 u8 reserved_at_40[0xa0]; 6386 6387 u8 start_flow_index[0x20]; 6388 6389 u8 reserved_at_100[0x20]; 6390 6391 u8 end_flow_index[0x20]; 6392 6393 u8 reserved_at_140[0xa0]; 6394 6395 u8 reserved_at_1e0[0x18]; 6396 u8 match_criteria_enable[0x8]; 6397 6398 struct mlx5_ifc_fte_match_param_bits match_criteria; 6399 6400 u8 reserved_at_1200[0xe00]; 6401 }; 6402 6403 struct mlx5_ifc_query_flow_group_in_bits { 6404 u8 opcode[0x10]; 6405 u8 reserved_at_10[0x10]; 6406 6407 u8 reserved_at_20[0x10]; 6408 u8 op_mod[0x10]; 6409 6410 u8 reserved_at_40[0x40]; 6411 6412 u8 table_type[0x8]; 6413 u8 reserved_at_88[0x18]; 6414 6415 u8 reserved_at_a0[0x8]; 6416 u8 table_id[0x18]; 6417 6418 u8 group_id[0x20]; 6419 6420 u8 reserved_at_e0[0x120]; 6421 }; 6422 6423 struct mlx5_ifc_query_flow_counter_out_bits { 6424 u8 status[0x8]; 6425 u8 reserved_at_8[0x18]; 6426 6427 u8 syndrome[0x20]; 6428 6429 u8 reserved_at_40[0x40]; 6430 6431 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6432 }; 6433 6434 struct mlx5_ifc_query_flow_counter_in_bits { 6435 u8 opcode[0x10]; 6436 u8 reserved_at_10[0x10]; 6437 6438 u8 reserved_at_20[0x10]; 6439 u8 op_mod[0x10]; 6440 6441 u8 reserved_at_40[0x80]; 6442 6443 u8 clear[0x1]; 6444 u8 reserved_at_c1[0xf]; 6445 u8 num_of_counters[0x10]; 6446 6447 u8 flow_counter_id[0x20]; 6448 }; 6449 6450 struct mlx5_ifc_query_esw_vport_context_out_bits { 6451 u8 status[0x8]; 6452 u8 reserved_at_8[0x18]; 6453 6454 u8 syndrome[0x20]; 6455 6456 u8 reserved_at_40[0x40]; 6457 6458 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6459 }; 6460 6461 struct mlx5_ifc_query_esw_vport_context_in_bits { 6462 u8 opcode[0x10]; 6463 u8 reserved_at_10[0x10]; 6464 6465 u8 reserved_at_20[0x10]; 6466 u8 op_mod[0x10]; 6467 6468 u8 other_vport[0x1]; 6469 u8 reserved_at_41[0xf]; 6470 u8 vport_number[0x10]; 6471 6472 u8 reserved_at_60[0x20]; 6473 }; 6474 6475 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6476 u8 status[0x8]; 6477 u8 reserved_at_8[0x18]; 6478 6479 u8 syndrome[0x20]; 6480 6481 u8 reserved_at_40[0x40]; 6482 }; 6483 6484 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6485 u8 reserved_at_0[0x1b]; 6486 u8 fdb_to_vport_reg_c_id[0x1]; 6487 u8 vport_cvlan_insert[0x1]; 6488 u8 vport_svlan_insert[0x1]; 6489 u8 vport_cvlan_strip[0x1]; 6490 u8 vport_svlan_strip[0x1]; 6491 }; 6492 6493 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6494 u8 opcode[0x10]; 6495 u8 reserved_at_10[0x10]; 6496 6497 u8 reserved_at_20[0x10]; 6498 u8 op_mod[0x10]; 6499 6500 u8 other_vport[0x1]; 6501 u8 reserved_at_41[0xf]; 6502 u8 vport_number[0x10]; 6503 6504 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6505 6506 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6507 }; 6508 6509 struct mlx5_ifc_query_eq_out_bits { 6510 u8 status[0x8]; 6511 u8 reserved_at_8[0x18]; 6512 6513 u8 syndrome[0x20]; 6514 6515 u8 reserved_at_40[0x40]; 6516 6517 struct mlx5_ifc_eqc_bits eq_context_entry; 6518 6519 u8 reserved_at_280[0x40]; 6520 6521 u8 event_bitmask[0x40]; 6522 6523 u8 reserved_at_300[0x580]; 6524 6525 u8 pas[][0x40]; 6526 }; 6527 6528 struct mlx5_ifc_query_eq_in_bits { 6529 u8 opcode[0x10]; 6530 u8 reserved_at_10[0x10]; 6531 6532 u8 reserved_at_20[0x10]; 6533 u8 op_mod[0x10]; 6534 6535 u8 reserved_at_40[0x18]; 6536 u8 eq_number[0x8]; 6537 6538 u8 reserved_at_60[0x20]; 6539 }; 6540 6541 struct mlx5_ifc_packet_reformat_context_in_bits { 6542 u8 reformat_type[0x8]; 6543 u8 reserved_at_8[0x4]; 6544 u8 reformat_param_0[0x4]; 6545 u8 reserved_at_10[0x6]; 6546 u8 reformat_data_size[0xa]; 6547 6548 u8 reformat_param_1[0x8]; 6549 u8 reserved_at_28[0x8]; 6550 u8 reformat_data[2][0x8]; 6551 6552 u8 more_reformat_data[][0x8]; 6553 }; 6554 6555 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6556 u8 status[0x8]; 6557 u8 reserved_at_8[0x18]; 6558 6559 u8 syndrome[0x20]; 6560 6561 u8 reserved_at_40[0xa0]; 6562 6563 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6564 }; 6565 6566 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_at_10[0x10]; 6569 6570 u8 reserved_at_20[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 packet_reformat_id[0x20]; 6574 6575 u8 reserved_at_60[0xa0]; 6576 }; 6577 6578 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6579 u8 status[0x8]; 6580 u8 reserved_at_8[0x18]; 6581 6582 u8 syndrome[0x20]; 6583 6584 u8 packet_reformat_id[0x20]; 6585 6586 u8 reserved_at_60[0x20]; 6587 }; 6588 6589 enum { 6590 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6591 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6592 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6593 }; 6594 6595 enum mlx5_reformat_ctx_type { 6596 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6597 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6598 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6599 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6600 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6601 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6602 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6603 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6604 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6605 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6606 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6607 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6608 }; 6609 6610 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6611 u8 opcode[0x10]; 6612 u8 reserved_at_10[0x10]; 6613 6614 u8 reserved_at_20[0x10]; 6615 u8 op_mod[0x10]; 6616 6617 u8 reserved_at_40[0xa0]; 6618 6619 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6620 }; 6621 6622 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6623 u8 status[0x8]; 6624 u8 reserved_at_8[0x18]; 6625 6626 u8 syndrome[0x20]; 6627 6628 u8 reserved_at_40[0x40]; 6629 }; 6630 6631 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6632 u8 opcode[0x10]; 6633 u8 reserved_at_10[0x10]; 6634 6635 u8 reserved_20[0x10]; 6636 u8 op_mod[0x10]; 6637 6638 u8 packet_reformat_id[0x20]; 6639 6640 u8 reserved_60[0x20]; 6641 }; 6642 6643 struct mlx5_ifc_set_action_in_bits { 6644 u8 action_type[0x4]; 6645 u8 field[0xc]; 6646 u8 reserved_at_10[0x3]; 6647 u8 offset[0x5]; 6648 u8 reserved_at_18[0x3]; 6649 u8 length[0x5]; 6650 6651 u8 data[0x20]; 6652 }; 6653 6654 struct mlx5_ifc_add_action_in_bits { 6655 u8 action_type[0x4]; 6656 u8 field[0xc]; 6657 u8 reserved_at_10[0x10]; 6658 6659 u8 data[0x20]; 6660 }; 6661 6662 struct mlx5_ifc_copy_action_in_bits { 6663 u8 action_type[0x4]; 6664 u8 src_field[0xc]; 6665 u8 reserved_at_10[0x3]; 6666 u8 src_offset[0x5]; 6667 u8 reserved_at_18[0x3]; 6668 u8 length[0x5]; 6669 6670 u8 reserved_at_20[0x4]; 6671 u8 dst_field[0xc]; 6672 u8 reserved_at_30[0x3]; 6673 u8 dst_offset[0x5]; 6674 u8 reserved_at_38[0x8]; 6675 }; 6676 6677 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6678 struct mlx5_ifc_set_action_in_bits set_action_in; 6679 struct mlx5_ifc_add_action_in_bits add_action_in; 6680 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6681 u8 reserved_at_0[0x40]; 6682 }; 6683 6684 enum { 6685 MLX5_ACTION_TYPE_SET = 0x1, 6686 MLX5_ACTION_TYPE_ADD = 0x2, 6687 MLX5_ACTION_TYPE_COPY = 0x3, 6688 }; 6689 6690 enum { 6691 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6692 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6693 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6694 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6695 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6696 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6697 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6698 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6699 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6700 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6701 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6702 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6703 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6704 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6705 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6706 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6707 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6708 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6709 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6710 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6711 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6712 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6713 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6714 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6715 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6716 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6717 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6718 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6719 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6720 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6721 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6722 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6723 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6724 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6725 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6726 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6727 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6728 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6729 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6730 }; 6731 6732 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6733 u8 status[0x8]; 6734 u8 reserved_at_8[0x18]; 6735 6736 u8 syndrome[0x20]; 6737 6738 u8 modify_header_id[0x20]; 6739 6740 u8 reserved_at_60[0x20]; 6741 }; 6742 6743 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6744 u8 opcode[0x10]; 6745 u8 reserved_at_10[0x10]; 6746 6747 u8 reserved_at_20[0x10]; 6748 u8 op_mod[0x10]; 6749 6750 u8 reserved_at_40[0x20]; 6751 6752 u8 table_type[0x8]; 6753 u8 reserved_at_68[0x10]; 6754 u8 num_of_actions[0x8]; 6755 6756 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6757 }; 6758 6759 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6760 u8 status[0x8]; 6761 u8 reserved_at_8[0x18]; 6762 6763 u8 syndrome[0x20]; 6764 6765 u8 reserved_at_40[0x40]; 6766 }; 6767 6768 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6769 u8 opcode[0x10]; 6770 u8 reserved_at_10[0x10]; 6771 6772 u8 reserved_at_20[0x10]; 6773 u8 op_mod[0x10]; 6774 6775 u8 modify_header_id[0x20]; 6776 6777 u8 reserved_at_60[0x20]; 6778 }; 6779 6780 struct mlx5_ifc_query_modify_header_context_in_bits { 6781 u8 opcode[0x10]; 6782 u8 uid[0x10]; 6783 6784 u8 reserved_at_20[0x10]; 6785 u8 op_mod[0x10]; 6786 6787 u8 modify_header_id[0x20]; 6788 6789 u8 reserved_at_60[0xa0]; 6790 }; 6791 6792 struct mlx5_ifc_query_dct_out_bits { 6793 u8 status[0x8]; 6794 u8 reserved_at_8[0x18]; 6795 6796 u8 syndrome[0x20]; 6797 6798 u8 reserved_at_40[0x40]; 6799 6800 struct mlx5_ifc_dctc_bits dct_context_entry; 6801 6802 u8 reserved_at_280[0x180]; 6803 }; 6804 6805 struct mlx5_ifc_query_dct_in_bits { 6806 u8 opcode[0x10]; 6807 u8 reserved_at_10[0x10]; 6808 6809 u8 reserved_at_20[0x10]; 6810 u8 op_mod[0x10]; 6811 6812 u8 reserved_at_40[0x8]; 6813 u8 dctn[0x18]; 6814 6815 u8 reserved_at_60[0x20]; 6816 }; 6817 6818 struct mlx5_ifc_query_cq_out_bits { 6819 u8 status[0x8]; 6820 u8 reserved_at_8[0x18]; 6821 6822 u8 syndrome[0x20]; 6823 6824 u8 reserved_at_40[0x40]; 6825 6826 struct mlx5_ifc_cqc_bits cq_context; 6827 6828 u8 reserved_at_280[0x600]; 6829 6830 u8 pas[][0x40]; 6831 }; 6832 6833 struct mlx5_ifc_query_cq_in_bits { 6834 u8 opcode[0x10]; 6835 u8 reserved_at_10[0x10]; 6836 6837 u8 reserved_at_20[0x10]; 6838 u8 op_mod[0x10]; 6839 6840 u8 reserved_at_40[0x8]; 6841 u8 cqn[0x18]; 6842 6843 u8 reserved_at_60[0x20]; 6844 }; 6845 6846 struct mlx5_ifc_query_cong_status_out_bits { 6847 u8 status[0x8]; 6848 u8 reserved_at_8[0x18]; 6849 6850 u8 syndrome[0x20]; 6851 6852 u8 reserved_at_40[0x20]; 6853 6854 u8 enable[0x1]; 6855 u8 tag_enable[0x1]; 6856 u8 reserved_at_62[0x1e]; 6857 }; 6858 6859 struct mlx5_ifc_query_cong_status_in_bits { 6860 u8 opcode[0x10]; 6861 u8 reserved_at_10[0x10]; 6862 6863 u8 reserved_at_20[0x10]; 6864 u8 op_mod[0x10]; 6865 6866 u8 reserved_at_40[0x18]; 6867 u8 priority[0x4]; 6868 u8 cong_protocol[0x4]; 6869 6870 u8 reserved_at_60[0x20]; 6871 }; 6872 6873 struct mlx5_ifc_query_cong_statistics_out_bits { 6874 u8 status[0x8]; 6875 u8 reserved_at_8[0x18]; 6876 6877 u8 syndrome[0x20]; 6878 6879 u8 reserved_at_40[0x40]; 6880 6881 u8 rp_cur_flows[0x20]; 6882 6883 u8 sum_flows[0x20]; 6884 6885 u8 rp_cnp_ignored_high[0x20]; 6886 6887 u8 rp_cnp_ignored_low[0x20]; 6888 6889 u8 rp_cnp_handled_high[0x20]; 6890 6891 u8 rp_cnp_handled_low[0x20]; 6892 6893 u8 reserved_at_140[0x100]; 6894 6895 u8 time_stamp_high[0x20]; 6896 6897 u8 time_stamp_low[0x20]; 6898 6899 u8 accumulators_period[0x20]; 6900 6901 u8 np_ecn_marked_roce_packets_high[0x20]; 6902 6903 u8 np_ecn_marked_roce_packets_low[0x20]; 6904 6905 u8 np_cnp_sent_high[0x20]; 6906 6907 u8 np_cnp_sent_low[0x20]; 6908 6909 u8 reserved_at_320[0x560]; 6910 }; 6911 6912 struct mlx5_ifc_query_cong_statistics_in_bits { 6913 u8 opcode[0x10]; 6914 u8 reserved_at_10[0x10]; 6915 6916 u8 reserved_at_20[0x10]; 6917 u8 op_mod[0x10]; 6918 6919 u8 clear[0x1]; 6920 u8 reserved_at_41[0x1f]; 6921 6922 u8 reserved_at_60[0x20]; 6923 }; 6924 6925 struct mlx5_ifc_query_cong_params_out_bits { 6926 u8 status[0x8]; 6927 u8 reserved_at_8[0x18]; 6928 6929 u8 syndrome[0x20]; 6930 6931 u8 reserved_at_40[0x40]; 6932 6933 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6934 }; 6935 6936 struct mlx5_ifc_query_cong_params_in_bits { 6937 u8 opcode[0x10]; 6938 u8 reserved_at_10[0x10]; 6939 6940 u8 reserved_at_20[0x10]; 6941 u8 op_mod[0x10]; 6942 6943 u8 reserved_at_40[0x1c]; 6944 u8 cong_protocol[0x4]; 6945 6946 u8 reserved_at_60[0x20]; 6947 }; 6948 6949 struct mlx5_ifc_query_adapter_out_bits { 6950 u8 status[0x8]; 6951 u8 reserved_at_8[0x18]; 6952 6953 u8 syndrome[0x20]; 6954 6955 u8 reserved_at_40[0x40]; 6956 6957 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6958 }; 6959 6960 struct mlx5_ifc_query_adapter_in_bits { 6961 u8 opcode[0x10]; 6962 u8 reserved_at_10[0x10]; 6963 6964 u8 reserved_at_20[0x10]; 6965 u8 op_mod[0x10]; 6966 6967 u8 reserved_at_40[0x40]; 6968 }; 6969 6970 struct mlx5_ifc_qp_2rst_out_bits { 6971 u8 status[0x8]; 6972 u8 reserved_at_8[0x18]; 6973 6974 u8 syndrome[0x20]; 6975 6976 u8 reserved_at_40[0x40]; 6977 }; 6978 6979 struct mlx5_ifc_qp_2rst_in_bits { 6980 u8 opcode[0x10]; 6981 u8 uid[0x10]; 6982 6983 u8 reserved_at_20[0x10]; 6984 u8 op_mod[0x10]; 6985 6986 u8 reserved_at_40[0x8]; 6987 u8 qpn[0x18]; 6988 6989 u8 reserved_at_60[0x20]; 6990 }; 6991 6992 struct mlx5_ifc_qp_2err_out_bits { 6993 u8 status[0x8]; 6994 u8 reserved_at_8[0x18]; 6995 6996 u8 syndrome[0x20]; 6997 6998 u8 reserved_at_40[0x40]; 6999 }; 7000 7001 struct mlx5_ifc_qp_2err_in_bits { 7002 u8 opcode[0x10]; 7003 u8 uid[0x10]; 7004 7005 u8 reserved_at_20[0x10]; 7006 u8 op_mod[0x10]; 7007 7008 u8 reserved_at_40[0x8]; 7009 u8 qpn[0x18]; 7010 7011 u8 reserved_at_60[0x20]; 7012 }; 7013 7014 struct mlx5_ifc_page_fault_resume_out_bits { 7015 u8 status[0x8]; 7016 u8 reserved_at_8[0x18]; 7017 7018 u8 syndrome[0x20]; 7019 7020 u8 reserved_at_40[0x40]; 7021 }; 7022 7023 struct mlx5_ifc_page_fault_resume_in_bits { 7024 u8 opcode[0x10]; 7025 u8 reserved_at_10[0x10]; 7026 7027 u8 reserved_at_20[0x10]; 7028 u8 op_mod[0x10]; 7029 7030 u8 error[0x1]; 7031 u8 reserved_at_41[0x4]; 7032 u8 page_fault_type[0x3]; 7033 u8 wq_number[0x18]; 7034 7035 u8 reserved_at_60[0x8]; 7036 u8 token[0x18]; 7037 }; 7038 7039 struct mlx5_ifc_nop_out_bits { 7040 u8 status[0x8]; 7041 u8 reserved_at_8[0x18]; 7042 7043 u8 syndrome[0x20]; 7044 7045 u8 reserved_at_40[0x40]; 7046 }; 7047 7048 struct mlx5_ifc_nop_in_bits { 7049 u8 opcode[0x10]; 7050 u8 reserved_at_10[0x10]; 7051 7052 u8 reserved_at_20[0x10]; 7053 u8 op_mod[0x10]; 7054 7055 u8 reserved_at_40[0x40]; 7056 }; 7057 7058 struct mlx5_ifc_modify_vport_state_out_bits { 7059 u8 status[0x8]; 7060 u8 reserved_at_8[0x18]; 7061 7062 u8 syndrome[0x20]; 7063 7064 u8 reserved_at_40[0x40]; 7065 }; 7066 7067 struct mlx5_ifc_modify_vport_state_in_bits { 7068 u8 opcode[0x10]; 7069 u8 reserved_at_10[0x10]; 7070 7071 u8 reserved_at_20[0x10]; 7072 u8 op_mod[0x10]; 7073 7074 u8 other_vport[0x1]; 7075 u8 reserved_at_41[0xf]; 7076 u8 vport_number[0x10]; 7077 7078 u8 reserved_at_60[0x18]; 7079 u8 admin_state[0x4]; 7080 u8 reserved_at_7c[0x4]; 7081 }; 7082 7083 struct mlx5_ifc_modify_tis_out_bits { 7084 u8 status[0x8]; 7085 u8 reserved_at_8[0x18]; 7086 7087 u8 syndrome[0x20]; 7088 7089 u8 reserved_at_40[0x40]; 7090 }; 7091 7092 struct mlx5_ifc_modify_tis_bitmask_bits { 7093 u8 reserved_at_0[0x20]; 7094 7095 u8 reserved_at_20[0x1d]; 7096 u8 lag_tx_port_affinity[0x1]; 7097 u8 strict_lag_tx_port_affinity[0x1]; 7098 u8 prio[0x1]; 7099 }; 7100 7101 struct mlx5_ifc_modify_tis_in_bits { 7102 u8 opcode[0x10]; 7103 u8 uid[0x10]; 7104 7105 u8 reserved_at_20[0x10]; 7106 u8 op_mod[0x10]; 7107 7108 u8 reserved_at_40[0x8]; 7109 u8 tisn[0x18]; 7110 7111 u8 reserved_at_60[0x20]; 7112 7113 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7114 7115 u8 reserved_at_c0[0x40]; 7116 7117 struct mlx5_ifc_tisc_bits ctx; 7118 }; 7119 7120 struct mlx5_ifc_modify_tir_bitmask_bits { 7121 u8 reserved_at_0[0x20]; 7122 7123 u8 reserved_at_20[0x1b]; 7124 u8 self_lb_en[0x1]; 7125 u8 reserved_at_3c[0x1]; 7126 u8 hash[0x1]; 7127 u8 reserved_at_3e[0x1]; 7128 u8 packet_merge[0x1]; 7129 }; 7130 7131 struct mlx5_ifc_modify_tir_out_bits { 7132 u8 status[0x8]; 7133 u8 reserved_at_8[0x18]; 7134 7135 u8 syndrome[0x20]; 7136 7137 u8 reserved_at_40[0x40]; 7138 }; 7139 7140 struct mlx5_ifc_modify_tir_in_bits { 7141 u8 opcode[0x10]; 7142 u8 uid[0x10]; 7143 7144 u8 reserved_at_20[0x10]; 7145 u8 op_mod[0x10]; 7146 7147 u8 reserved_at_40[0x8]; 7148 u8 tirn[0x18]; 7149 7150 u8 reserved_at_60[0x20]; 7151 7152 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7153 7154 u8 reserved_at_c0[0x40]; 7155 7156 struct mlx5_ifc_tirc_bits ctx; 7157 }; 7158 7159 struct mlx5_ifc_modify_sq_out_bits { 7160 u8 status[0x8]; 7161 u8 reserved_at_8[0x18]; 7162 7163 u8 syndrome[0x20]; 7164 7165 u8 reserved_at_40[0x40]; 7166 }; 7167 7168 struct mlx5_ifc_modify_sq_in_bits { 7169 u8 opcode[0x10]; 7170 u8 uid[0x10]; 7171 7172 u8 reserved_at_20[0x10]; 7173 u8 op_mod[0x10]; 7174 7175 u8 sq_state[0x4]; 7176 u8 reserved_at_44[0x4]; 7177 u8 sqn[0x18]; 7178 7179 u8 reserved_at_60[0x20]; 7180 7181 u8 modify_bitmask[0x40]; 7182 7183 u8 reserved_at_c0[0x40]; 7184 7185 struct mlx5_ifc_sqc_bits ctx; 7186 }; 7187 7188 struct mlx5_ifc_modify_scheduling_element_out_bits { 7189 u8 status[0x8]; 7190 u8 reserved_at_8[0x18]; 7191 7192 u8 syndrome[0x20]; 7193 7194 u8 reserved_at_40[0x1c0]; 7195 }; 7196 7197 enum { 7198 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7199 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7200 }; 7201 7202 struct mlx5_ifc_modify_scheduling_element_in_bits { 7203 u8 opcode[0x10]; 7204 u8 reserved_at_10[0x10]; 7205 7206 u8 reserved_at_20[0x10]; 7207 u8 op_mod[0x10]; 7208 7209 u8 scheduling_hierarchy[0x8]; 7210 u8 reserved_at_48[0x18]; 7211 7212 u8 scheduling_element_id[0x20]; 7213 7214 u8 reserved_at_80[0x20]; 7215 7216 u8 modify_bitmask[0x20]; 7217 7218 u8 reserved_at_c0[0x40]; 7219 7220 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7221 7222 u8 reserved_at_300[0x100]; 7223 }; 7224 7225 struct mlx5_ifc_modify_rqt_out_bits { 7226 u8 status[0x8]; 7227 u8 reserved_at_8[0x18]; 7228 7229 u8 syndrome[0x20]; 7230 7231 u8 reserved_at_40[0x40]; 7232 }; 7233 7234 struct mlx5_ifc_rqt_bitmask_bits { 7235 u8 reserved_at_0[0x20]; 7236 7237 u8 reserved_at_20[0x1f]; 7238 u8 rqn_list[0x1]; 7239 }; 7240 7241 struct mlx5_ifc_modify_rqt_in_bits { 7242 u8 opcode[0x10]; 7243 u8 uid[0x10]; 7244 7245 u8 reserved_at_20[0x10]; 7246 u8 op_mod[0x10]; 7247 7248 u8 reserved_at_40[0x8]; 7249 u8 rqtn[0x18]; 7250 7251 u8 reserved_at_60[0x20]; 7252 7253 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7254 7255 u8 reserved_at_c0[0x40]; 7256 7257 struct mlx5_ifc_rqtc_bits ctx; 7258 }; 7259 7260 struct mlx5_ifc_modify_rq_out_bits { 7261 u8 status[0x8]; 7262 u8 reserved_at_8[0x18]; 7263 7264 u8 syndrome[0x20]; 7265 7266 u8 reserved_at_40[0x40]; 7267 }; 7268 7269 enum { 7270 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7271 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7272 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7273 }; 7274 7275 struct mlx5_ifc_modify_rq_in_bits { 7276 u8 opcode[0x10]; 7277 u8 uid[0x10]; 7278 7279 u8 reserved_at_20[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 rq_state[0x4]; 7283 u8 reserved_at_44[0x4]; 7284 u8 rqn[0x18]; 7285 7286 u8 reserved_at_60[0x20]; 7287 7288 u8 modify_bitmask[0x40]; 7289 7290 u8 reserved_at_c0[0x40]; 7291 7292 struct mlx5_ifc_rqc_bits ctx; 7293 }; 7294 7295 struct mlx5_ifc_modify_rmp_out_bits { 7296 u8 status[0x8]; 7297 u8 reserved_at_8[0x18]; 7298 7299 u8 syndrome[0x20]; 7300 7301 u8 reserved_at_40[0x40]; 7302 }; 7303 7304 struct mlx5_ifc_rmp_bitmask_bits { 7305 u8 reserved_at_0[0x20]; 7306 7307 u8 reserved_at_20[0x1f]; 7308 u8 lwm[0x1]; 7309 }; 7310 7311 struct mlx5_ifc_modify_rmp_in_bits { 7312 u8 opcode[0x10]; 7313 u8 uid[0x10]; 7314 7315 u8 reserved_at_20[0x10]; 7316 u8 op_mod[0x10]; 7317 7318 u8 rmp_state[0x4]; 7319 u8 reserved_at_44[0x4]; 7320 u8 rmpn[0x18]; 7321 7322 u8 reserved_at_60[0x20]; 7323 7324 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7325 7326 u8 reserved_at_c0[0x40]; 7327 7328 struct mlx5_ifc_rmpc_bits ctx; 7329 }; 7330 7331 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7332 u8 status[0x8]; 7333 u8 reserved_at_8[0x18]; 7334 7335 u8 syndrome[0x20]; 7336 7337 u8 reserved_at_40[0x40]; 7338 }; 7339 7340 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7341 u8 reserved_at_0[0x12]; 7342 u8 affiliation[0x1]; 7343 u8 reserved_at_13[0x1]; 7344 u8 disable_uc_local_lb[0x1]; 7345 u8 disable_mc_local_lb[0x1]; 7346 u8 node_guid[0x1]; 7347 u8 port_guid[0x1]; 7348 u8 min_inline[0x1]; 7349 u8 mtu[0x1]; 7350 u8 change_event[0x1]; 7351 u8 promisc[0x1]; 7352 u8 permanent_address[0x1]; 7353 u8 addresses_list[0x1]; 7354 u8 roce_en[0x1]; 7355 u8 reserved_at_1f[0x1]; 7356 }; 7357 7358 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7359 u8 opcode[0x10]; 7360 u8 reserved_at_10[0x10]; 7361 7362 u8 reserved_at_20[0x10]; 7363 u8 op_mod[0x10]; 7364 7365 u8 other_vport[0x1]; 7366 u8 reserved_at_41[0xf]; 7367 u8 vport_number[0x10]; 7368 7369 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7370 7371 u8 reserved_at_80[0x780]; 7372 7373 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7374 }; 7375 7376 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7377 u8 status[0x8]; 7378 u8 reserved_at_8[0x18]; 7379 7380 u8 syndrome[0x20]; 7381 7382 u8 reserved_at_40[0x40]; 7383 }; 7384 7385 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7386 u8 opcode[0x10]; 7387 u8 reserved_at_10[0x10]; 7388 7389 u8 reserved_at_20[0x10]; 7390 u8 op_mod[0x10]; 7391 7392 u8 other_vport[0x1]; 7393 u8 reserved_at_41[0xb]; 7394 u8 port_num[0x4]; 7395 u8 vport_number[0x10]; 7396 7397 u8 reserved_at_60[0x20]; 7398 7399 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7400 }; 7401 7402 struct mlx5_ifc_modify_cq_out_bits { 7403 u8 status[0x8]; 7404 u8 reserved_at_8[0x18]; 7405 7406 u8 syndrome[0x20]; 7407 7408 u8 reserved_at_40[0x40]; 7409 }; 7410 7411 enum { 7412 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7413 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7414 }; 7415 7416 struct mlx5_ifc_modify_cq_in_bits { 7417 u8 opcode[0x10]; 7418 u8 uid[0x10]; 7419 7420 u8 reserved_at_20[0x10]; 7421 u8 op_mod[0x10]; 7422 7423 u8 reserved_at_40[0x8]; 7424 u8 cqn[0x18]; 7425 7426 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7427 7428 struct mlx5_ifc_cqc_bits cq_context; 7429 7430 u8 reserved_at_280[0x60]; 7431 7432 u8 cq_umem_valid[0x1]; 7433 u8 reserved_at_2e1[0x1f]; 7434 7435 u8 reserved_at_300[0x580]; 7436 7437 u8 pas[][0x40]; 7438 }; 7439 7440 struct mlx5_ifc_modify_cong_status_out_bits { 7441 u8 status[0x8]; 7442 u8 reserved_at_8[0x18]; 7443 7444 u8 syndrome[0x20]; 7445 7446 u8 reserved_at_40[0x40]; 7447 }; 7448 7449 struct mlx5_ifc_modify_cong_status_in_bits { 7450 u8 opcode[0x10]; 7451 u8 reserved_at_10[0x10]; 7452 7453 u8 reserved_at_20[0x10]; 7454 u8 op_mod[0x10]; 7455 7456 u8 reserved_at_40[0x18]; 7457 u8 priority[0x4]; 7458 u8 cong_protocol[0x4]; 7459 7460 u8 enable[0x1]; 7461 u8 tag_enable[0x1]; 7462 u8 reserved_at_62[0x1e]; 7463 }; 7464 7465 struct mlx5_ifc_modify_cong_params_out_bits { 7466 u8 status[0x8]; 7467 u8 reserved_at_8[0x18]; 7468 7469 u8 syndrome[0x20]; 7470 7471 u8 reserved_at_40[0x40]; 7472 }; 7473 7474 struct mlx5_ifc_modify_cong_params_in_bits { 7475 u8 opcode[0x10]; 7476 u8 reserved_at_10[0x10]; 7477 7478 u8 reserved_at_20[0x10]; 7479 u8 op_mod[0x10]; 7480 7481 u8 reserved_at_40[0x1c]; 7482 u8 cong_protocol[0x4]; 7483 7484 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7485 7486 u8 reserved_at_80[0x80]; 7487 7488 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7489 }; 7490 7491 struct mlx5_ifc_manage_pages_out_bits { 7492 u8 status[0x8]; 7493 u8 reserved_at_8[0x18]; 7494 7495 u8 syndrome[0x20]; 7496 7497 u8 output_num_entries[0x20]; 7498 7499 u8 reserved_at_60[0x20]; 7500 7501 u8 pas[][0x40]; 7502 }; 7503 7504 enum { 7505 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7506 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7507 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7508 }; 7509 7510 struct mlx5_ifc_manage_pages_in_bits { 7511 u8 opcode[0x10]; 7512 u8 reserved_at_10[0x10]; 7513 7514 u8 reserved_at_20[0x10]; 7515 u8 op_mod[0x10]; 7516 7517 u8 embedded_cpu_function[0x1]; 7518 u8 reserved_at_41[0xf]; 7519 u8 function_id[0x10]; 7520 7521 u8 input_num_entries[0x20]; 7522 7523 u8 pas[][0x40]; 7524 }; 7525 7526 struct mlx5_ifc_mad_ifc_out_bits { 7527 u8 status[0x8]; 7528 u8 reserved_at_8[0x18]; 7529 7530 u8 syndrome[0x20]; 7531 7532 u8 reserved_at_40[0x40]; 7533 7534 u8 response_mad_packet[256][0x8]; 7535 }; 7536 7537 struct mlx5_ifc_mad_ifc_in_bits { 7538 u8 opcode[0x10]; 7539 u8 reserved_at_10[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 remote_lid[0x10]; 7545 u8 reserved_at_50[0x8]; 7546 u8 port[0x8]; 7547 7548 u8 reserved_at_60[0x20]; 7549 7550 u8 mad[256][0x8]; 7551 }; 7552 7553 struct mlx5_ifc_init_hca_out_bits { 7554 u8 status[0x8]; 7555 u8 reserved_at_8[0x18]; 7556 7557 u8 syndrome[0x20]; 7558 7559 u8 reserved_at_40[0x40]; 7560 }; 7561 7562 struct mlx5_ifc_init_hca_in_bits { 7563 u8 opcode[0x10]; 7564 u8 reserved_at_10[0x10]; 7565 7566 u8 reserved_at_20[0x10]; 7567 u8 op_mod[0x10]; 7568 7569 u8 reserved_at_40[0x20]; 7570 7571 u8 reserved_at_60[0x2]; 7572 u8 sw_vhca_id[0xe]; 7573 u8 reserved_at_70[0x10]; 7574 7575 u8 sw_owner_id[4][0x20]; 7576 }; 7577 7578 struct mlx5_ifc_init2rtr_qp_out_bits { 7579 u8 status[0x8]; 7580 u8 reserved_at_8[0x18]; 7581 7582 u8 syndrome[0x20]; 7583 7584 u8 reserved_at_40[0x20]; 7585 u8 ece[0x20]; 7586 }; 7587 7588 struct mlx5_ifc_init2rtr_qp_in_bits { 7589 u8 opcode[0x10]; 7590 u8 uid[0x10]; 7591 7592 u8 reserved_at_20[0x10]; 7593 u8 op_mod[0x10]; 7594 7595 u8 reserved_at_40[0x8]; 7596 u8 qpn[0x18]; 7597 7598 u8 reserved_at_60[0x20]; 7599 7600 u8 opt_param_mask[0x20]; 7601 7602 u8 ece[0x20]; 7603 7604 struct mlx5_ifc_qpc_bits qpc; 7605 7606 u8 reserved_at_800[0x80]; 7607 }; 7608 7609 struct mlx5_ifc_init2init_qp_out_bits { 7610 u8 status[0x8]; 7611 u8 reserved_at_8[0x18]; 7612 7613 u8 syndrome[0x20]; 7614 7615 u8 reserved_at_40[0x20]; 7616 u8 ece[0x20]; 7617 }; 7618 7619 struct mlx5_ifc_init2init_qp_in_bits { 7620 u8 opcode[0x10]; 7621 u8 uid[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 reserved_at_40[0x8]; 7627 u8 qpn[0x18]; 7628 7629 u8 reserved_at_60[0x20]; 7630 7631 u8 opt_param_mask[0x20]; 7632 7633 u8 ece[0x20]; 7634 7635 struct mlx5_ifc_qpc_bits qpc; 7636 7637 u8 reserved_at_800[0x80]; 7638 }; 7639 7640 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7641 u8 status[0x8]; 7642 u8 reserved_at_8[0x18]; 7643 7644 u8 syndrome[0x20]; 7645 7646 u8 reserved_at_40[0x40]; 7647 7648 u8 packet_headers_log[128][0x8]; 7649 7650 u8 packet_syndrome[64][0x8]; 7651 }; 7652 7653 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7654 u8 opcode[0x10]; 7655 u8 reserved_at_10[0x10]; 7656 7657 u8 reserved_at_20[0x10]; 7658 u8 op_mod[0x10]; 7659 7660 u8 reserved_at_40[0x40]; 7661 }; 7662 7663 struct mlx5_ifc_gen_eqe_in_bits { 7664 u8 opcode[0x10]; 7665 u8 reserved_at_10[0x10]; 7666 7667 u8 reserved_at_20[0x10]; 7668 u8 op_mod[0x10]; 7669 7670 u8 reserved_at_40[0x18]; 7671 u8 eq_number[0x8]; 7672 7673 u8 reserved_at_60[0x20]; 7674 7675 u8 eqe[64][0x8]; 7676 }; 7677 7678 struct mlx5_ifc_gen_eq_out_bits { 7679 u8 status[0x8]; 7680 u8 reserved_at_8[0x18]; 7681 7682 u8 syndrome[0x20]; 7683 7684 u8 reserved_at_40[0x40]; 7685 }; 7686 7687 struct mlx5_ifc_enable_hca_out_bits { 7688 u8 status[0x8]; 7689 u8 reserved_at_8[0x18]; 7690 7691 u8 syndrome[0x20]; 7692 7693 u8 reserved_at_40[0x20]; 7694 }; 7695 7696 struct mlx5_ifc_enable_hca_in_bits { 7697 u8 opcode[0x10]; 7698 u8 reserved_at_10[0x10]; 7699 7700 u8 reserved_at_20[0x10]; 7701 u8 op_mod[0x10]; 7702 7703 u8 embedded_cpu_function[0x1]; 7704 u8 reserved_at_41[0xf]; 7705 u8 function_id[0x10]; 7706 7707 u8 reserved_at_60[0x20]; 7708 }; 7709 7710 struct mlx5_ifc_drain_dct_out_bits { 7711 u8 status[0x8]; 7712 u8 reserved_at_8[0x18]; 7713 7714 u8 syndrome[0x20]; 7715 7716 u8 reserved_at_40[0x40]; 7717 }; 7718 7719 struct mlx5_ifc_drain_dct_in_bits { 7720 u8 opcode[0x10]; 7721 u8 uid[0x10]; 7722 7723 u8 reserved_at_20[0x10]; 7724 u8 op_mod[0x10]; 7725 7726 u8 reserved_at_40[0x8]; 7727 u8 dctn[0x18]; 7728 7729 u8 reserved_at_60[0x20]; 7730 }; 7731 7732 struct mlx5_ifc_disable_hca_out_bits { 7733 u8 status[0x8]; 7734 u8 reserved_at_8[0x18]; 7735 7736 u8 syndrome[0x20]; 7737 7738 u8 reserved_at_40[0x20]; 7739 }; 7740 7741 struct mlx5_ifc_disable_hca_in_bits { 7742 u8 opcode[0x10]; 7743 u8 reserved_at_10[0x10]; 7744 7745 u8 reserved_at_20[0x10]; 7746 u8 op_mod[0x10]; 7747 7748 u8 embedded_cpu_function[0x1]; 7749 u8 reserved_at_41[0xf]; 7750 u8 function_id[0x10]; 7751 7752 u8 reserved_at_60[0x20]; 7753 }; 7754 7755 struct mlx5_ifc_detach_from_mcg_out_bits { 7756 u8 status[0x8]; 7757 u8 reserved_at_8[0x18]; 7758 7759 u8 syndrome[0x20]; 7760 7761 u8 reserved_at_40[0x40]; 7762 }; 7763 7764 struct mlx5_ifc_detach_from_mcg_in_bits { 7765 u8 opcode[0x10]; 7766 u8 uid[0x10]; 7767 7768 u8 reserved_at_20[0x10]; 7769 u8 op_mod[0x10]; 7770 7771 u8 reserved_at_40[0x8]; 7772 u8 qpn[0x18]; 7773 7774 u8 reserved_at_60[0x20]; 7775 7776 u8 multicast_gid[16][0x8]; 7777 }; 7778 7779 struct mlx5_ifc_destroy_xrq_out_bits { 7780 u8 status[0x8]; 7781 u8 reserved_at_8[0x18]; 7782 7783 u8 syndrome[0x20]; 7784 7785 u8 reserved_at_40[0x40]; 7786 }; 7787 7788 struct mlx5_ifc_destroy_xrq_in_bits { 7789 u8 opcode[0x10]; 7790 u8 uid[0x10]; 7791 7792 u8 reserved_at_20[0x10]; 7793 u8 op_mod[0x10]; 7794 7795 u8 reserved_at_40[0x8]; 7796 u8 xrqn[0x18]; 7797 7798 u8 reserved_at_60[0x20]; 7799 }; 7800 7801 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7802 u8 status[0x8]; 7803 u8 reserved_at_8[0x18]; 7804 7805 u8 syndrome[0x20]; 7806 7807 u8 reserved_at_40[0x40]; 7808 }; 7809 7810 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7811 u8 opcode[0x10]; 7812 u8 uid[0x10]; 7813 7814 u8 reserved_at_20[0x10]; 7815 u8 op_mod[0x10]; 7816 7817 u8 reserved_at_40[0x8]; 7818 u8 xrc_srqn[0x18]; 7819 7820 u8 reserved_at_60[0x20]; 7821 }; 7822 7823 struct mlx5_ifc_destroy_tis_out_bits { 7824 u8 status[0x8]; 7825 u8 reserved_at_8[0x18]; 7826 7827 u8 syndrome[0x20]; 7828 7829 u8 reserved_at_40[0x40]; 7830 }; 7831 7832 struct mlx5_ifc_destroy_tis_in_bits { 7833 u8 opcode[0x10]; 7834 u8 uid[0x10]; 7835 7836 u8 reserved_at_20[0x10]; 7837 u8 op_mod[0x10]; 7838 7839 u8 reserved_at_40[0x8]; 7840 u8 tisn[0x18]; 7841 7842 u8 reserved_at_60[0x20]; 7843 }; 7844 7845 struct mlx5_ifc_destroy_tir_out_bits { 7846 u8 status[0x8]; 7847 u8 reserved_at_8[0x18]; 7848 7849 u8 syndrome[0x20]; 7850 7851 u8 reserved_at_40[0x40]; 7852 }; 7853 7854 struct mlx5_ifc_destroy_tir_in_bits { 7855 u8 opcode[0x10]; 7856 u8 uid[0x10]; 7857 7858 u8 reserved_at_20[0x10]; 7859 u8 op_mod[0x10]; 7860 7861 u8 reserved_at_40[0x8]; 7862 u8 tirn[0x18]; 7863 7864 u8 reserved_at_60[0x20]; 7865 }; 7866 7867 struct mlx5_ifc_destroy_srq_out_bits { 7868 u8 status[0x8]; 7869 u8 reserved_at_8[0x18]; 7870 7871 u8 syndrome[0x20]; 7872 7873 u8 reserved_at_40[0x40]; 7874 }; 7875 7876 struct mlx5_ifc_destroy_srq_in_bits { 7877 u8 opcode[0x10]; 7878 u8 uid[0x10]; 7879 7880 u8 reserved_at_20[0x10]; 7881 u8 op_mod[0x10]; 7882 7883 u8 reserved_at_40[0x8]; 7884 u8 srqn[0x18]; 7885 7886 u8 reserved_at_60[0x20]; 7887 }; 7888 7889 struct mlx5_ifc_destroy_sq_out_bits { 7890 u8 status[0x8]; 7891 u8 reserved_at_8[0x18]; 7892 7893 u8 syndrome[0x20]; 7894 7895 u8 reserved_at_40[0x40]; 7896 }; 7897 7898 struct mlx5_ifc_destroy_sq_in_bits { 7899 u8 opcode[0x10]; 7900 u8 uid[0x10]; 7901 7902 u8 reserved_at_20[0x10]; 7903 u8 op_mod[0x10]; 7904 7905 u8 reserved_at_40[0x8]; 7906 u8 sqn[0x18]; 7907 7908 u8 reserved_at_60[0x20]; 7909 }; 7910 7911 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7912 u8 status[0x8]; 7913 u8 reserved_at_8[0x18]; 7914 7915 u8 syndrome[0x20]; 7916 7917 u8 reserved_at_40[0x1c0]; 7918 }; 7919 7920 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7921 u8 opcode[0x10]; 7922 u8 reserved_at_10[0x10]; 7923 7924 u8 reserved_at_20[0x10]; 7925 u8 op_mod[0x10]; 7926 7927 u8 scheduling_hierarchy[0x8]; 7928 u8 reserved_at_48[0x18]; 7929 7930 u8 scheduling_element_id[0x20]; 7931 7932 u8 reserved_at_80[0x180]; 7933 }; 7934 7935 struct mlx5_ifc_destroy_rqt_out_bits { 7936 u8 status[0x8]; 7937 u8 reserved_at_8[0x18]; 7938 7939 u8 syndrome[0x20]; 7940 7941 u8 reserved_at_40[0x40]; 7942 }; 7943 7944 struct mlx5_ifc_destroy_rqt_in_bits { 7945 u8 opcode[0x10]; 7946 u8 uid[0x10]; 7947 7948 u8 reserved_at_20[0x10]; 7949 u8 op_mod[0x10]; 7950 7951 u8 reserved_at_40[0x8]; 7952 u8 rqtn[0x18]; 7953 7954 u8 reserved_at_60[0x20]; 7955 }; 7956 7957 struct mlx5_ifc_destroy_rq_out_bits { 7958 u8 status[0x8]; 7959 u8 reserved_at_8[0x18]; 7960 7961 u8 syndrome[0x20]; 7962 7963 u8 reserved_at_40[0x40]; 7964 }; 7965 7966 struct mlx5_ifc_destroy_rq_in_bits { 7967 u8 opcode[0x10]; 7968 u8 uid[0x10]; 7969 7970 u8 reserved_at_20[0x10]; 7971 u8 op_mod[0x10]; 7972 7973 u8 reserved_at_40[0x8]; 7974 u8 rqn[0x18]; 7975 7976 u8 reserved_at_60[0x20]; 7977 }; 7978 7979 struct mlx5_ifc_set_delay_drop_params_in_bits { 7980 u8 opcode[0x10]; 7981 u8 reserved_at_10[0x10]; 7982 7983 u8 reserved_at_20[0x10]; 7984 u8 op_mod[0x10]; 7985 7986 u8 reserved_at_40[0x20]; 7987 7988 u8 reserved_at_60[0x10]; 7989 u8 delay_drop_timeout[0x10]; 7990 }; 7991 7992 struct mlx5_ifc_set_delay_drop_params_out_bits { 7993 u8 status[0x8]; 7994 u8 reserved_at_8[0x18]; 7995 7996 u8 syndrome[0x20]; 7997 7998 u8 reserved_at_40[0x40]; 7999 }; 8000 8001 struct mlx5_ifc_destroy_rmp_out_bits { 8002 u8 status[0x8]; 8003 u8 reserved_at_8[0x18]; 8004 8005 u8 syndrome[0x20]; 8006 8007 u8 reserved_at_40[0x40]; 8008 }; 8009 8010 struct mlx5_ifc_destroy_rmp_in_bits { 8011 u8 opcode[0x10]; 8012 u8 uid[0x10]; 8013 8014 u8 reserved_at_20[0x10]; 8015 u8 op_mod[0x10]; 8016 8017 u8 reserved_at_40[0x8]; 8018 u8 rmpn[0x18]; 8019 8020 u8 reserved_at_60[0x20]; 8021 }; 8022 8023 struct mlx5_ifc_destroy_qp_out_bits { 8024 u8 status[0x8]; 8025 u8 reserved_at_8[0x18]; 8026 8027 u8 syndrome[0x20]; 8028 8029 u8 reserved_at_40[0x40]; 8030 }; 8031 8032 struct mlx5_ifc_destroy_qp_in_bits { 8033 u8 opcode[0x10]; 8034 u8 uid[0x10]; 8035 8036 u8 reserved_at_20[0x10]; 8037 u8 op_mod[0x10]; 8038 8039 u8 reserved_at_40[0x8]; 8040 u8 qpn[0x18]; 8041 8042 u8 reserved_at_60[0x20]; 8043 }; 8044 8045 struct mlx5_ifc_destroy_psv_out_bits { 8046 u8 status[0x8]; 8047 u8 reserved_at_8[0x18]; 8048 8049 u8 syndrome[0x20]; 8050 8051 u8 reserved_at_40[0x40]; 8052 }; 8053 8054 struct mlx5_ifc_destroy_psv_in_bits { 8055 u8 opcode[0x10]; 8056 u8 reserved_at_10[0x10]; 8057 8058 u8 reserved_at_20[0x10]; 8059 u8 op_mod[0x10]; 8060 8061 u8 reserved_at_40[0x8]; 8062 u8 psvn[0x18]; 8063 8064 u8 reserved_at_60[0x20]; 8065 }; 8066 8067 struct mlx5_ifc_destroy_mkey_out_bits { 8068 u8 status[0x8]; 8069 u8 reserved_at_8[0x18]; 8070 8071 u8 syndrome[0x20]; 8072 8073 u8 reserved_at_40[0x40]; 8074 }; 8075 8076 struct mlx5_ifc_destroy_mkey_in_bits { 8077 u8 opcode[0x10]; 8078 u8 uid[0x10]; 8079 8080 u8 reserved_at_20[0x10]; 8081 u8 op_mod[0x10]; 8082 8083 u8 reserved_at_40[0x8]; 8084 u8 mkey_index[0x18]; 8085 8086 u8 reserved_at_60[0x20]; 8087 }; 8088 8089 struct mlx5_ifc_destroy_flow_table_out_bits { 8090 u8 status[0x8]; 8091 u8 reserved_at_8[0x18]; 8092 8093 u8 syndrome[0x20]; 8094 8095 u8 reserved_at_40[0x40]; 8096 }; 8097 8098 struct mlx5_ifc_destroy_flow_table_in_bits { 8099 u8 opcode[0x10]; 8100 u8 reserved_at_10[0x10]; 8101 8102 u8 reserved_at_20[0x10]; 8103 u8 op_mod[0x10]; 8104 8105 u8 other_vport[0x1]; 8106 u8 reserved_at_41[0xf]; 8107 u8 vport_number[0x10]; 8108 8109 u8 reserved_at_60[0x20]; 8110 8111 u8 table_type[0x8]; 8112 u8 reserved_at_88[0x18]; 8113 8114 u8 reserved_at_a0[0x8]; 8115 u8 table_id[0x18]; 8116 8117 u8 reserved_at_c0[0x140]; 8118 }; 8119 8120 struct mlx5_ifc_destroy_flow_group_out_bits { 8121 u8 status[0x8]; 8122 u8 reserved_at_8[0x18]; 8123 8124 u8 syndrome[0x20]; 8125 8126 u8 reserved_at_40[0x40]; 8127 }; 8128 8129 struct mlx5_ifc_destroy_flow_group_in_bits { 8130 u8 opcode[0x10]; 8131 u8 reserved_at_10[0x10]; 8132 8133 u8 reserved_at_20[0x10]; 8134 u8 op_mod[0x10]; 8135 8136 u8 other_vport[0x1]; 8137 u8 reserved_at_41[0xf]; 8138 u8 vport_number[0x10]; 8139 8140 u8 reserved_at_60[0x20]; 8141 8142 u8 table_type[0x8]; 8143 u8 reserved_at_88[0x18]; 8144 8145 u8 reserved_at_a0[0x8]; 8146 u8 table_id[0x18]; 8147 8148 u8 group_id[0x20]; 8149 8150 u8 reserved_at_e0[0x120]; 8151 }; 8152 8153 struct mlx5_ifc_destroy_eq_out_bits { 8154 u8 status[0x8]; 8155 u8 reserved_at_8[0x18]; 8156 8157 u8 syndrome[0x20]; 8158 8159 u8 reserved_at_40[0x40]; 8160 }; 8161 8162 struct mlx5_ifc_destroy_eq_in_bits { 8163 u8 opcode[0x10]; 8164 u8 reserved_at_10[0x10]; 8165 8166 u8 reserved_at_20[0x10]; 8167 u8 op_mod[0x10]; 8168 8169 u8 reserved_at_40[0x18]; 8170 u8 eq_number[0x8]; 8171 8172 u8 reserved_at_60[0x20]; 8173 }; 8174 8175 struct mlx5_ifc_destroy_dct_out_bits { 8176 u8 status[0x8]; 8177 u8 reserved_at_8[0x18]; 8178 8179 u8 syndrome[0x20]; 8180 8181 u8 reserved_at_40[0x40]; 8182 }; 8183 8184 struct mlx5_ifc_destroy_dct_in_bits { 8185 u8 opcode[0x10]; 8186 u8 uid[0x10]; 8187 8188 u8 reserved_at_20[0x10]; 8189 u8 op_mod[0x10]; 8190 8191 u8 reserved_at_40[0x8]; 8192 u8 dctn[0x18]; 8193 8194 u8 reserved_at_60[0x20]; 8195 }; 8196 8197 struct mlx5_ifc_destroy_cq_out_bits { 8198 u8 status[0x8]; 8199 u8 reserved_at_8[0x18]; 8200 8201 u8 syndrome[0x20]; 8202 8203 u8 reserved_at_40[0x40]; 8204 }; 8205 8206 struct mlx5_ifc_destroy_cq_in_bits { 8207 u8 opcode[0x10]; 8208 u8 uid[0x10]; 8209 8210 u8 reserved_at_20[0x10]; 8211 u8 op_mod[0x10]; 8212 8213 u8 reserved_at_40[0x8]; 8214 u8 cqn[0x18]; 8215 8216 u8 reserved_at_60[0x20]; 8217 }; 8218 8219 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8220 u8 status[0x8]; 8221 u8 reserved_at_8[0x18]; 8222 8223 u8 syndrome[0x20]; 8224 8225 u8 reserved_at_40[0x40]; 8226 }; 8227 8228 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8229 u8 opcode[0x10]; 8230 u8 reserved_at_10[0x10]; 8231 8232 u8 reserved_at_20[0x10]; 8233 u8 op_mod[0x10]; 8234 8235 u8 reserved_at_40[0x20]; 8236 8237 u8 reserved_at_60[0x10]; 8238 u8 vxlan_udp_port[0x10]; 8239 }; 8240 8241 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 reserved_at_40[0x40]; 8248 }; 8249 8250 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8251 u8 opcode[0x10]; 8252 u8 reserved_at_10[0x10]; 8253 8254 u8 reserved_at_20[0x10]; 8255 u8 op_mod[0x10]; 8256 8257 u8 reserved_at_40[0x60]; 8258 8259 u8 reserved_at_a0[0x8]; 8260 u8 table_index[0x18]; 8261 8262 u8 reserved_at_c0[0x140]; 8263 }; 8264 8265 struct mlx5_ifc_delete_fte_out_bits { 8266 u8 status[0x8]; 8267 u8 reserved_at_8[0x18]; 8268 8269 u8 syndrome[0x20]; 8270 8271 u8 reserved_at_40[0x40]; 8272 }; 8273 8274 struct mlx5_ifc_delete_fte_in_bits { 8275 u8 opcode[0x10]; 8276 u8 reserved_at_10[0x10]; 8277 8278 u8 reserved_at_20[0x10]; 8279 u8 op_mod[0x10]; 8280 8281 u8 other_vport[0x1]; 8282 u8 reserved_at_41[0xf]; 8283 u8 vport_number[0x10]; 8284 8285 u8 reserved_at_60[0x20]; 8286 8287 u8 table_type[0x8]; 8288 u8 reserved_at_88[0x18]; 8289 8290 u8 reserved_at_a0[0x8]; 8291 u8 table_id[0x18]; 8292 8293 u8 reserved_at_c0[0x40]; 8294 8295 u8 flow_index[0x20]; 8296 8297 u8 reserved_at_120[0xe0]; 8298 }; 8299 8300 struct mlx5_ifc_dealloc_xrcd_out_bits { 8301 u8 status[0x8]; 8302 u8 reserved_at_8[0x18]; 8303 8304 u8 syndrome[0x20]; 8305 8306 u8 reserved_at_40[0x40]; 8307 }; 8308 8309 struct mlx5_ifc_dealloc_xrcd_in_bits { 8310 u8 opcode[0x10]; 8311 u8 uid[0x10]; 8312 8313 u8 reserved_at_20[0x10]; 8314 u8 op_mod[0x10]; 8315 8316 u8 reserved_at_40[0x8]; 8317 u8 xrcd[0x18]; 8318 8319 u8 reserved_at_60[0x20]; 8320 }; 8321 8322 struct mlx5_ifc_dealloc_uar_out_bits { 8323 u8 status[0x8]; 8324 u8 reserved_at_8[0x18]; 8325 8326 u8 syndrome[0x20]; 8327 8328 u8 reserved_at_40[0x40]; 8329 }; 8330 8331 struct mlx5_ifc_dealloc_uar_in_bits { 8332 u8 opcode[0x10]; 8333 u8 uid[0x10]; 8334 8335 u8 reserved_at_20[0x10]; 8336 u8 op_mod[0x10]; 8337 8338 u8 reserved_at_40[0x8]; 8339 u8 uar[0x18]; 8340 8341 u8 reserved_at_60[0x20]; 8342 }; 8343 8344 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8345 u8 status[0x8]; 8346 u8 reserved_at_8[0x18]; 8347 8348 u8 syndrome[0x20]; 8349 8350 u8 reserved_at_40[0x40]; 8351 }; 8352 8353 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8354 u8 opcode[0x10]; 8355 u8 uid[0x10]; 8356 8357 u8 reserved_at_20[0x10]; 8358 u8 op_mod[0x10]; 8359 8360 u8 reserved_at_40[0x8]; 8361 u8 transport_domain[0x18]; 8362 8363 u8 reserved_at_60[0x20]; 8364 }; 8365 8366 struct mlx5_ifc_dealloc_q_counter_out_bits { 8367 u8 status[0x8]; 8368 u8 reserved_at_8[0x18]; 8369 8370 u8 syndrome[0x20]; 8371 8372 u8 reserved_at_40[0x40]; 8373 }; 8374 8375 struct mlx5_ifc_dealloc_q_counter_in_bits { 8376 u8 opcode[0x10]; 8377 u8 reserved_at_10[0x10]; 8378 8379 u8 reserved_at_20[0x10]; 8380 u8 op_mod[0x10]; 8381 8382 u8 reserved_at_40[0x18]; 8383 u8 counter_set_id[0x8]; 8384 8385 u8 reserved_at_60[0x20]; 8386 }; 8387 8388 struct mlx5_ifc_dealloc_pd_out_bits { 8389 u8 status[0x8]; 8390 u8 reserved_at_8[0x18]; 8391 8392 u8 syndrome[0x20]; 8393 8394 u8 reserved_at_40[0x40]; 8395 }; 8396 8397 struct mlx5_ifc_dealloc_pd_in_bits { 8398 u8 opcode[0x10]; 8399 u8 uid[0x10]; 8400 8401 u8 reserved_at_20[0x10]; 8402 u8 op_mod[0x10]; 8403 8404 u8 reserved_at_40[0x8]; 8405 u8 pd[0x18]; 8406 8407 u8 reserved_at_60[0x20]; 8408 }; 8409 8410 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8411 u8 status[0x8]; 8412 u8 reserved_at_8[0x18]; 8413 8414 u8 syndrome[0x20]; 8415 8416 u8 reserved_at_40[0x40]; 8417 }; 8418 8419 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8420 u8 opcode[0x10]; 8421 u8 reserved_at_10[0x10]; 8422 8423 u8 reserved_at_20[0x10]; 8424 u8 op_mod[0x10]; 8425 8426 u8 flow_counter_id[0x20]; 8427 8428 u8 reserved_at_60[0x20]; 8429 }; 8430 8431 struct mlx5_ifc_create_xrq_out_bits { 8432 u8 status[0x8]; 8433 u8 reserved_at_8[0x18]; 8434 8435 u8 syndrome[0x20]; 8436 8437 u8 reserved_at_40[0x8]; 8438 u8 xrqn[0x18]; 8439 8440 u8 reserved_at_60[0x20]; 8441 }; 8442 8443 struct mlx5_ifc_create_xrq_in_bits { 8444 u8 opcode[0x10]; 8445 u8 uid[0x10]; 8446 8447 u8 reserved_at_20[0x10]; 8448 u8 op_mod[0x10]; 8449 8450 u8 reserved_at_40[0x40]; 8451 8452 struct mlx5_ifc_xrqc_bits xrq_context; 8453 }; 8454 8455 struct mlx5_ifc_create_xrc_srq_out_bits { 8456 u8 status[0x8]; 8457 u8 reserved_at_8[0x18]; 8458 8459 u8 syndrome[0x20]; 8460 8461 u8 reserved_at_40[0x8]; 8462 u8 xrc_srqn[0x18]; 8463 8464 u8 reserved_at_60[0x20]; 8465 }; 8466 8467 struct mlx5_ifc_create_xrc_srq_in_bits { 8468 u8 opcode[0x10]; 8469 u8 uid[0x10]; 8470 8471 u8 reserved_at_20[0x10]; 8472 u8 op_mod[0x10]; 8473 8474 u8 reserved_at_40[0x40]; 8475 8476 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8477 8478 u8 reserved_at_280[0x60]; 8479 8480 u8 xrc_srq_umem_valid[0x1]; 8481 u8 reserved_at_2e1[0x1f]; 8482 8483 u8 reserved_at_300[0x580]; 8484 8485 u8 pas[][0x40]; 8486 }; 8487 8488 struct mlx5_ifc_create_tis_out_bits { 8489 u8 status[0x8]; 8490 u8 reserved_at_8[0x18]; 8491 8492 u8 syndrome[0x20]; 8493 8494 u8 reserved_at_40[0x8]; 8495 u8 tisn[0x18]; 8496 8497 u8 reserved_at_60[0x20]; 8498 }; 8499 8500 struct mlx5_ifc_create_tis_in_bits { 8501 u8 opcode[0x10]; 8502 u8 uid[0x10]; 8503 8504 u8 reserved_at_20[0x10]; 8505 u8 op_mod[0x10]; 8506 8507 u8 reserved_at_40[0xc0]; 8508 8509 struct mlx5_ifc_tisc_bits ctx; 8510 }; 8511 8512 struct mlx5_ifc_create_tir_out_bits { 8513 u8 status[0x8]; 8514 u8 icm_address_63_40[0x18]; 8515 8516 u8 syndrome[0x20]; 8517 8518 u8 icm_address_39_32[0x8]; 8519 u8 tirn[0x18]; 8520 8521 u8 icm_address_31_0[0x20]; 8522 }; 8523 8524 struct mlx5_ifc_create_tir_in_bits { 8525 u8 opcode[0x10]; 8526 u8 uid[0x10]; 8527 8528 u8 reserved_at_20[0x10]; 8529 u8 op_mod[0x10]; 8530 8531 u8 reserved_at_40[0xc0]; 8532 8533 struct mlx5_ifc_tirc_bits ctx; 8534 }; 8535 8536 struct mlx5_ifc_create_srq_out_bits { 8537 u8 status[0x8]; 8538 u8 reserved_at_8[0x18]; 8539 8540 u8 syndrome[0x20]; 8541 8542 u8 reserved_at_40[0x8]; 8543 u8 srqn[0x18]; 8544 8545 u8 reserved_at_60[0x20]; 8546 }; 8547 8548 struct mlx5_ifc_create_srq_in_bits { 8549 u8 opcode[0x10]; 8550 u8 uid[0x10]; 8551 8552 u8 reserved_at_20[0x10]; 8553 u8 op_mod[0x10]; 8554 8555 u8 reserved_at_40[0x40]; 8556 8557 struct mlx5_ifc_srqc_bits srq_context_entry; 8558 8559 u8 reserved_at_280[0x600]; 8560 8561 u8 pas[][0x40]; 8562 }; 8563 8564 struct mlx5_ifc_create_sq_out_bits { 8565 u8 status[0x8]; 8566 u8 reserved_at_8[0x18]; 8567 8568 u8 syndrome[0x20]; 8569 8570 u8 reserved_at_40[0x8]; 8571 u8 sqn[0x18]; 8572 8573 u8 reserved_at_60[0x20]; 8574 }; 8575 8576 struct mlx5_ifc_create_sq_in_bits { 8577 u8 opcode[0x10]; 8578 u8 uid[0x10]; 8579 8580 u8 reserved_at_20[0x10]; 8581 u8 op_mod[0x10]; 8582 8583 u8 reserved_at_40[0xc0]; 8584 8585 struct mlx5_ifc_sqc_bits ctx; 8586 }; 8587 8588 struct mlx5_ifc_create_scheduling_element_out_bits { 8589 u8 status[0x8]; 8590 u8 reserved_at_8[0x18]; 8591 8592 u8 syndrome[0x20]; 8593 8594 u8 reserved_at_40[0x40]; 8595 8596 u8 scheduling_element_id[0x20]; 8597 8598 u8 reserved_at_a0[0x160]; 8599 }; 8600 8601 struct mlx5_ifc_create_scheduling_element_in_bits { 8602 u8 opcode[0x10]; 8603 u8 reserved_at_10[0x10]; 8604 8605 u8 reserved_at_20[0x10]; 8606 u8 op_mod[0x10]; 8607 8608 u8 scheduling_hierarchy[0x8]; 8609 u8 reserved_at_48[0x18]; 8610 8611 u8 reserved_at_60[0xa0]; 8612 8613 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8614 8615 u8 reserved_at_300[0x100]; 8616 }; 8617 8618 struct mlx5_ifc_create_rqt_out_bits { 8619 u8 status[0x8]; 8620 u8 reserved_at_8[0x18]; 8621 8622 u8 syndrome[0x20]; 8623 8624 u8 reserved_at_40[0x8]; 8625 u8 rqtn[0x18]; 8626 8627 u8 reserved_at_60[0x20]; 8628 }; 8629 8630 struct mlx5_ifc_create_rqt_in_bits { 8631 u8 opcode[0x10]; 8632 u8 uid[0x10]; 8633 8634 u8 reserved_at_20[0x10]; 8635 u8 op_mod[0x10]; 8636 8637 u8 reserved_at_40[0xc0]; 8638 8639 struct mlx5_ifc_rqtc_bits rqt_context; 8640 }; 8641 8642 struct mlx5_ifc_create_rq_out_bits { 8643 u8 status[0x8]; 8644 u8 reserved_at_8[0x18]; 8645 8646 u8 syndrome[0x20]; 8647 8648 u8 reserved_at_40[0x8]; 8649 u8 rqn[0x18]; 8650 8651 u8 reserved_at_60[0x20]; 8652 }; 8653 8654 struct mlx5_ifc_create_rq_in_bits { 8655 u8 opcode[0x10]; 8656 u8 uid[0x10]; 8657 8658 u8 reserved_at_20[0x10]; 8659 u8 op_mod[0x10]; 8660 8661 u8 reserved_at_40[0xc0]; 8662 8663 struct mlx5_ifc_rqc_bits ctx; 8664 }; 8665 8666 struct mlx5_ifc_create_rmp_out_bits { 8667 u8 status[0x8]; 8668 u8 reserved_at_8[0x18]; 8669 8670 u8 syndrome[0x20]; 8671 8672 u8 reserved_at_40[0x8]; 8673 u8 rmpn[0x18]; 8674 8675 u8 reserved_at_60[0x20]; 8676 }; 8677 8678 struct mlx5_ifc_create_rmp_in_bits { 8679 u8 opcode[0x10]; 8680 u8 uid[0x10]; 8681 8682 u8 reserved_at_20[0x10]; 8683 u8 op_mod[0x10]; 8684 8685 u8 reserved_at_40[0xc0]; 8686 8687 struct mlx5_ifc_rmpc_bits ctx; 8688 }; 8689 8690 struct mlx5_ifc_create_qp_out_bits { 8691 u8 status[0x8]; 8692 u8 reserved_at_8[0x18]; 8693 8694 u8 syndrome[0x20]; 8695 8696 u8 reserved_at_40[0x8]; 8697 u8 qpn[0x18]; 8698 8699 u8 ece[0x20]; 8700 }; 8701 8702 struct mlx5_ifc_create_qp_in_bits { 8703 u8 opcode[0x10]; 8704 u8 uid[0x10]; 8705 8706 u8 reserved_at_20[0x10]; 8707 u8 op_mod[0x10]; 8708 8709 u8 qpc_ext[0x1]; 8710 u8 reserved_at_41[0x7]; 8711 u8 input_qpn[0x18]; 8712 8713 u8 reserved_at_60[0x20]; 8714 u8 opt_param_mask[0x20]; 8715 8716 u8 ece[0x20]; 8717 8718 struct mlx5_ifc_qpc_bits qpc; 8719 8720 u8 reserved_at_800[0x60]; 8721 8722 u8 wq_umem_valid[0x1]; 8723 u8 reserved_at_861[0x1f]; 8724 8725 u8 pas[][0x40]; 8726 }; 8727 8728 struct mlx5_ifc_create_psv_out_bits { 8729 u8 status[0x8]; 8730 u8 reserved_at_8[0x18]; 8731 8732 u8 syndrome[0x20]; 8733 8734 u8 reserved_at_40[0x40]; 8735 8736 u8 reserved_at_80[0x8]; 8737 u8 psv0_index[0x18]; 8738 8739 u8 reserved_at_a0[0x8]; 8740 u8 psv1_index[0x18]; 8741 8742 u8 reserved_at_c0[0x8]; 8743 u8 psv2_index[0x18]; 8744 8745 u8 reserved_at_e0[0x8]; 8746 u8 psv3_index[0x18]; 8747 }; 8748 8749 struct mlx5_ifc_create_psv_in_bits { 8750 u8 opcode[0x10]; 8751 u8 reserved_at_10[0x10]; 8752 8753 u8 reserved_at_20[0x10]; 8754 u8 op_mod[0x10]; 8755 8756 u8 num_psv[0x4]; 8757 u8 reserved_at_44[0x4]; 8758 u8 pd[0x18]; 8759 8760 u8 reserved_at_60[0x20]; 8761 }; 8762 8763 struct mlx5_ifc_create_mkey_out_bits { 8764 u8 status[0x8]; 8765 u8 reserved_at_8[0x18]; 8766 8767 u8 syndrome[0x20]; 8768 8769 u8 reserved_at_40[0x8]; 8770 u8 mkey_index[0x18]; 8771 8772 u8 reserved_at_60[0x20]; 8773 }; 8774 8775 struct mlx5_ifc_create_mkey_in_bits { 8776 u8 opcode[0x10]; 8777 u8 uid[0x10]; 8778 8779 u8 reserved_at_20[0x10]; 8780 u8 op_mod[0x10]; 8781 8782 u8 reserved_at_40[0x20]; 8783 8784 u8 pg_access[0x1]; 8785 u8 mkey_umem_valid[0x1]; 8786 u8 reserved_at_62[0x1e]; 8787 8788 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8789 8790 u8 reserved_at_280[0x80]; 8791 8792 u8 translations_octword_actual_size[0x20]; 8793 8794 u8 reserved_at_320[0x560]; 8795 8796 u8 klm_pas_mtt[][0x20]; 8797 }; 8798 8799 enum { 8800 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8801 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8802 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8803 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8804 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8805 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8806 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8807 }; 8808 8809 struct mlx5_ifc_create_flow_table_out_bits { 8810 u8 status[0x8]; 8811 u8 icm_address_63_40[0x18]; 8812 8813 u8 syndrome[0x20]; 8814 8815 u8 icm_address_39_32[0x8]; 8816 u8 table_id[0x18]; 8817 8818 u8 icm_address_31_0[0x20]; 8819 }; 8820 8821 struct mlx5_ifc_create_flow_table_in_bits { 8822 u8 opcode[0x10]; 8823 u8 uid[0x10]; 8824 8825 u8 reserved_at_20[0x10]; 8826 u8 op_mod[0x10]; 8827 8828 u8 other_vport[0x1]; 8829 u8 reserved_at_41[0xf]; 8830 u8 vport_number[0x10]; 8831 8832 u8 reserved_at_60[0x20]; 8833 8834 u8 table_type[0x8]; 8835 u8 reserved_at_88[0x18]; 8836 8837 u8 reserved_at_a0[0x20]; 8838 8839 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8840 }; 8841 8842 struct mlx5_ifc_create_flow_group_out_bits { 8843 u8 status[0x8]; 8844 u8 reserved_at_8[0x18]; 8845 8846 u8 syndrome[0x20]; 8847 8848 u8 reserved_at_40[0x8]; 8849 u8 group_id[0x18]; 8850 8851 u8 reserved_at_60[0x20]; 8852 }; 8853 8854 enum { 8855 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8856 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8857 }; 8858 8859 enum { 8860 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8861 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8862 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8863 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8864 }; 8865 8866 struct mlx5_ifc_create_flow_group_in_bits { 8867 u8 opcode[0x10]; 8868 u8 reserved_at_10[0x10]; 8869 8870 u8 reserved_at_20[0x10]; 8871 u8 op_mod[0x10]; 8872 8873 u8 other_vport[0x1]; 8874 u8 reserved_at_41[0xf]; 8875 u8 vport_number[0x10]; 8876 8877 u8 reserved_at_60[0x20]; 8878 8879 u8 table_type[0x8]; 8880 u8 reserved_at_88[0x4]; 8881 u8 group_type[0x4]; 8882 u8 reserved_at_90[0x10]; 8883 8884 u8 reserved_at_a0[0x8]; 8885 u8 table_id[0x18]; 8886 8887 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8888 8889 u8 reserved_at_c1[0x1f]; 8890 8891 u8 start_flow_index[0x20]; 8892 8893 u8 reserved_at_100[0x20]; 8894 8895 u8 end_flow_index[0x20]; 8896 8897 u8 reserved_at_140[0x10]; 8898 u8 match_definer_id[0x10]; 8899 8900 u8 reserved_at_160[0x80]; 8901 8902 u8 reserved_at_1e0[0x18]; 8903 u8 match_criteria_enable[0x8]; 8904 8905 struct mlx5_ifc_fte_match_param_bits match_criteria; 8906 8907 u8 reserved_at_1200[0xe00]; 8908 }; 8909 8910 struct mlx5_ifc_create_eq_out_bits { 8911 u8 status[0x8]; 8912 u8 reserved_at_8[0x18]; 8913 8914 u8 syndrome[0x20]; 8915 8916 u8 reserved_at_40[0x18]; 8917 u8 eq_number[0x8]; 8918 8919 u8 reserved_at_60[0x20]; 8920 }; 8921 8922 struct mlx5_ifc_create_eq_in_bits { 8923 u8 opcode[0x10]; 8924 u8 uid[0x10]; 8925 8926 u8 reserved_at_20[0x10]; 8927 u8 op_mod[0x10]; 8928 8929 u8 reserved_at_40[0x40]; 8930 8931 struct mlx5_ifc_eqc_bits eq_context_entry; 8932 8933 u8 reserved_at_280[0x40]; 8934 8935 u8 event_bitmask[4][0x40]; 8936 8937 u8 reserved_at_3c0[0x4c0]; 8938 8939 u8 pas[][0x40]; 8940 }; 8941 8942 struct mlx5_ifc_create_dct_out_bits { 8943 u8 status[0x8]; 8944 u8 reserved_at_8[0x18]; 8945 8946 u8 syndrome[0x20]; 8947 8948 u8 reserved_at_40[0x8]; 8949 u8 dctn[0x18]; 8950 8951 u8 ece[0x20]; 8952 }; 8953 8954 struct mlx5_ifc_create_dct_in_bits { 8955 u8 opcode[0x10]; 8956 u8 uid[0x10]; 8957 8958 u8 reserved_at_20[0x10]; 8959 u8 op_mod[0x10]; 8960 8961 u8 reserved_at_40[0x40]; 8962 8963 struct mlx5_ifc_dctc_bits dct_context_entry; 8964 8965 u8 reserved_at_280[0x180]; 8966 }; 8967 8968 struct mlx5_ifc_create_cq_out_bits { 8969 u8 status[0x8]; 8970 u8 reserved_at_8[0x18]; 8971 8972 u8 syndrome[0x20]; 8973 8974 u8 reserved_at_40[0x8]; 8975 u8 cqn[0x18]; 8976 8977 u8 reserved_at_60[0x20]; 8978 }; 8979 8980 struct mlx5_ifc_create_cq_in_bits { 8981 u8 opcode[0x10]; 8982 u8 uid[0x10]; 8983 8984 u8 reserved_at_20[0x10]; 8985 u8 op_mod[0x10]; 8986 8987 u8 reserved_at_40[0x40]; 8988 8989 struct mlx5_ifc_cqc_bits cq_context; 8990 8991 u8 reserved_at_280[0x60]; 8992 8993 u8 cq_umem_valid[0x1]; 8994 u8 reserved_at_2e1[0x59f]; 8995 8996 u8 pas[][0x40]; 8997 }; 8998 8999 struct mlx5_ifc_config_int_moderation_out_bits { 9000 u8 status[0x8]; 9001 u8 reserved_at_8[0x18]; 9002 9003 u8 syndrome[0x20]; 9004 9005 u8 reserved_at_40[0x4]; 9006 u8 min_delay[0xc]; 9007 u8 int_vector[0x10]; 9008 9009 u8 reserved_at_60[0x20]; 9010 }; 9011 9012 enum { 9013 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9014 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9015 }; 9016 9017 struct mlx5_ifc_config_int_moderation_in_bits { 9018 u8 opcode[0x10]; 9019 u8 reserved_at_10[0x10]; 9020 9021 u8 reserved_at_20[0x10]; 9022 u8 op_mod[0x10]; 9023 9024 u8 reserved_at_40[0x4]; 9025 u8 min_delay[0xc]; 9026 u8 int_vector[0x10]; 9027 9028 u8 reserved_at_60[0x20]; 9029 }; 9030 9031 struct mlx5_ifc_attach_to_mcg_out_bits { 9032 u8 status[0x8]; 9033 u8 reserved_at_8[0x18]; 9034 9035 u8 syndrome[0x20]; 9036 9037 u8 reserved_at_40[0x40]; 9038 }; 9039 9040 struct mlx5_ifc_attach_to_mcg_in_bits { 9041 u8 opcode[0x10]; 9042 u8 uid[0x10]; 9043 9044 u8 reserved_at_20[0x10]; 9045 u8 op_mod[0x10]; 9046 9047 u8 reserved_at_40[0x8]; 9048 u8 qpn[0x18]; 9049 9050 u8 reserved_at_60[0x20]; 9051 9052 u8 multicast_gid[16][0x8]; 9053 }; 9054 9055 struct mlx5_ifc_arm_xrq_out_bits { 9056 u8 status[0x8]; 9057 u8 reserved_at_8[0x18]; 9058 9059 u8 syndrome[0x20]; 9060 9061 u8 reserved_at_40[0x40]; 9062 }; 9063 9064 struct mlx5_ifc_arm_xrq_in_bits { 9065 u8 opcode[0x10]; 9066 u8 reserved_at_10[0x10]; 9067 9068 u8 reserved_at_20[0x10]; 9069 u8 op_mod[0x10]; 9070 9071 u8 reserved_at_40[0x8]; 9072 u8 xrqn[0x18]; 9073 9074 u8 reserved_at_60[0x10]; 9075 u8 lwm[0x10]; 9076 }; 9077 9078 struct mlx5_ifc_arm_xrc_srq_out_bits { 9079 u8 status[0x8]; 9080 u8 reserved_at_8[0x18]; 9081 9082 u8 syndrome[0x20]; 9083 9084 u8 reserved_at_40[0x40]; 9085 }; 9086 9087 enum { 9088 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9089 }; 9090 9091 struct mlx5_ifc_arm_xrc_srq_in_bits { 9092 u8 opcode[0x10]; 9093 u8 uid[0x10]; 9094 9095 u8 reserved_at_20[0x10]; 9096 u8 op_mod[0x10]; 9097 9098 u8 reserved_at_40[0x8]; 9099 u8 xrc_srqn[0x18]; 9100 9101 u8 reserved_at_60[0x10]; 9102 u8 lwm[0x10]; 9103 }; 9104 9105 struct mlx5_ifc_arm_rq_out_bits { 9106 u8 status[0x8]; 9107 u8 reserved_at_8[0x18]; 9108 9109 u8 syndrome[0x20]; 9110 9111 u8 reserved_at_40[0x40]; 9112 }; 9113 9114 enum { 9115 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9116 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9117 }; 9118 9119 struct mlx5_ifc_arm_rq_in_bits { 9120 u8 opcode[0x10]; 9121 u8 uid[0x10]; 9122 9123 u8 reserved_at_20[0x10]; 9124 u8 op_mod[0x10]; 9125 9126 u8 reserved_at_40[0x8]; 9127 u8 srq_number[0x18]; 9128 9129 u8 reserved_at_60[0x10]; 9130 u8 lwm[0x10]; 9131 }; 9132 9133 struct mlx5_ifc_arm_dct_out_bits { 9134 u8 status[0x8]; 9135 u8 reserved_at_8[0x18]; 9136 9137 u8 syndrome[0x20]; 9138 9139 u8 reserved_at_40[0x40]; 9140 }; 9141 9142 struct mlx5_ifc_arm_dct_in_bits { 9143 u8 opcode[0x10]; 9144 u8 reserved_at_10[0x10]; 9145 9146 u8 reserved_at_20[0x10]; 9147 u8 op_mod[0x10]; 9148 9149 u8 reserved_at_40[0x8]; 9150 u8 dct_number[0x18]; 9151 9152 u8 reserved_at_60[0x20]; 9153 }; 9154 9155 struct mlx5_ifc_alloc_xrcd_out_bits { 9156 u8 status[0x8]; 9157 u8 reserved_at_8[0x18]; 9158 9159 u8 syndrome[0x20]; 9160 9161 u8 reserved_at_40[0x8]; 9162 u8 xrcd[0x18]; 9163 9164 u8 reserved_at_60[0x20]; 9165 }; 9166 9167 struct mlx5_ifc_alloc_xrcd_in_bits { 9168 u8 opcode[0x10]; 9169 u8 uid[0x10]; 9170 9171 u8 reserved_at_20[0x10]; 9172 u8 op_mod[0x10]; 9173 9174 u8 reserved_at_40[0x40]; 9175 }; 9176 9177 struct mlx5_ifc_alloc_uar_out_bits { 9178 u8 status[0x8]; 9179 u8 reserved_at_8[0x18]; 9180 9181 u8 syndrome[0x20]; 9182 9183 u8 reserved_at_40[0x8]; 9184 u8 uar[0x18]; 9185 9186 u8 reserved_at_60[0x20]; 9187 }; 9188 9189 struct mlx5_ifc_alloc_uar_in_bits { 9190 u8 opcode[0x10]; 9191 u8 uid[0x10]; 9192 9193 u8 reserved_at_20[0x10]; 9194 u8 op_mod[0x10]; 9195 9196 u8 reserved_at_40[0x40]; 9197 }; 9198 9199 struct mlx5_ifc_alloc_transport_domain_out_bits { 9200 u8 status[0x8]; 9201 u8 reserved_at_8[0x18]; 9202 9203 u8 syndrome[0x20]; 9204 9205 u8 reserved_at_40[0x8]; 9206 u8 transport_domain[0x18]; 9207 9208 u8 reserved_at_60[0x20]; 9209 }; 9210 9211 struct mlx5_ifc_alloc_transport_domain_in_bits { 9212 u8 opcode[0x10]; 9213 u8 uid[0x10]; 9214 9215 u8 reserved_at_20[0x10]; 9216 u8 op_mod[0x10]; 9217 9218 u8 reserved_at_40[0x40]; 9219 }; 9220 9221 struct mlx5_ifc_alloc_q_counter_out_bits { 9222 u8 status[0x8]; 9223 u8 reserved_at_8[0x18]; 9224 9225 u8 syndrome[0x20]; 9226 9227 u8 reserved_at_40[0x18]; 9228 u8 counter_set_id[0x8]; 9229 9230 u8 reserved_at_60[0x20]; 9231 }; 9232 9233 struct mlx5_ifc_alloc_q_counter_in_bits { 9234 u8 opcode[0x10]; 9235 u8 uid[0x10]; 9236 9237 u8 reserved_at_20[0x10]; 9238 u8 op_mod[0x10]; 9239 9240 u8 reserved_at_40[0x40]; 9241 }; 9242 9243 struct mlx5_ifc_alloc_pd_out_bits { 9244 u8 status[0x8]; 9245 u8 reserved_at_8[0x18]; 9246 9247 u8 syndrome[0x20]; 9248 9249 u8 reserved_at_40[0x8]; 9250 u8 pd[0x18]; 9251 9252 u8 reserved_at_60[0x20]; 9253 }; 9254 9255 struct mlx5_ifc_alloc_pd_in_bits { 9256 u8 opcode[0x10]; 9257 u8 uid[0x10]; 9258 9259 u8 reserved_at_20[0x10]; 9260 u8 op_mod[0x10]; 9261 9262 u8 reserved_at_40[0x40]; 9263 }; 9264 9265 struct mlx5_ifc_alloc_flow_counter_out_bits { 9266 u8 status[0x8]; 9267 u8 reserved_at_8[0x18]; 9268 9269 u8 syndrome[0x20]; 9270 9271 u8 flow_counter_id[0x20]; 9272 9273 u8 reserved_at_60[0x20]; 9274 }; 9275 9276 struct mlx5_ifc_alloc_flow_counter_in_bits { 9277 u8 opcode[0x10]; 9278 u8 reserved_at_10[0x10]; 9279 9280 u8 reserved_at_20[0x10]; 9281 u8 op_mod[0x10]; 9282 9283 u8 reserved_at_40[0x38]; 9284 u8 flow_counter_bulk[0x8]; 9285 }; 9286 9287 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9288 u8 status[0x8]; 9289 u8 reserved_at_8[0x18]; 9290 9291 u8 syndrome[0x20]; 9292 9293 u8 reserved_at_40[0x40]; 9294 }; 9295 9296 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9297 u8 opcode[0x10]; 9298 u8 reserved_at_10[0x10]; 9299 9300 u8 reserved_at_20[0x10]; 9301 u8 op_mod[0x10]; 9302 9303 u8 reserved_at_40[0x20]; 9304 9305 u8 reserved_at_60[0x10]; 9306 u8 vxlan_udp_port[0x10]; 9307 }; 9308 9309 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9310 u8 status[0x8]; 9311 u8 reserved_at_8[0x18]; 9312 9313 u8 syndrome[0x20]; 9314 9315 u8 reserved_at_40[0x40]; 9316 }; 9317 9318 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9319 u8 rate_limit[0x20]; 9320 9321 u8 burst_upper_bound[0x20]; 9322 9323 u8 reserved_at_40[0x10]; 9324 u8 typical_packet_size[0x10]; 9325 9326 u8 reserved_at_60[0x120]; 9327 }; 9328 9329 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9330 u8 opcode[0x10]; 9331 u8 uid[0x10]; 9332 9333 u8 reserved_at_20[0x10]; 9334 u8 op_mod[0x10]; 9335 9336 u8 reserved_at_40[0x10]; 9337 u8 rate_limit_index[0x10]; 9338 9339 u8 reserved_at_60[0x20]; 9340 9341 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9342 }; 9343 9344 struct mlx5_ifc_access_register_out_bits { 9345 u8 status[0x8]; 9346 u8 reserved_at_8[0x18]; 9347 9348 u8 syndrome[0x20]; 9349 9350 u8 reserved_at_40[0x40]; 9351 9352 u8 register_data[][0x20]; 9353 }; 9354 9355 enum { 9356 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9357 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9358 }; 9359 9360 struct mlx5_ifc_access_register_in_bits { 9361 u8 opcode[0x10]; 9362 u8 reserved_at_10[0x10]; 9363 9364 u8 reserved_at_20[0x10]; 9365 u8 op_mod[0x10]; 9366 9367 u8 reserved_at_40[0x10]; 9368 u8 register_id[0x10]; 9369 9370 u8 argument[0x20]; 9371 9372 u8 register_data[][0x20]; 9373 }; 9374 9375 struct mlx5_ifc_sltp_reg_bits { 9376 u8 status[0x4]; 9377 u8 version[0x4]; 9378 u8 local_port[0x8]; 9379 u8 pnat[0x2]; 9380 u8 reserved_at_12[0x2]; 9381 u8 lane[0x4]; 9382 u8 reserved_at_18[0x8]; 9383 9384 u8 reserved_at_20[0x20]; 9385 9386 u8 reserved_at_40[0x7]; 9387 u8 polarity[0x1]; 9388 u8 ob_tap0[0x8]; 9389 u8 ob_tap1[0x8]; 9390 u8 ob_tap2[0x8]; 9391 9392 u8 reserved_at_60[0xc]; 9393 u8 ob_preemp_mode[0x4]; 9394 u8 ob_reg[0x8]; 9395 u8 ob_bias[0x8]; 9396 9397 u8 reserved_at_80[0x20]; 9398 }; 9399 9400 struct mlx5_ifc_slrg_reg_bits { 9401 u8 status[0x4]; 9402 u8 version[0x4]; 9403 u8 local_port[0x8]; 9404 u8 pnat[0x2]; 9405 u8 reserved_at_12[0x2]; 9406 u8 lane[0x4]; 9407 u8 reserved_at_18[0x8]; 9408 9409 u8 time_to_link_up[0x10]; 9410 u8 reserved_at_30[0xc]; 9411 u8 grade_lane_speed[0x4]; 9412 9413 u8 grade_version[0x8]; 9414 u8 grade[0x18]; 9415 9416 u8 reserved_at_60[0x4]; 9417 u8 height_grade_type[0x4]; 9418 u8 height_grade[0x18]; 9419 9420 u8 height_dz[0x10]; 9421 u8 height_dv[0x10]; 9422 9423 u8 reserved_at_a0[0x10]; 9424 u8 height_sigma[0x10]; 9425 9426 u8 reserved_at_c0[0x20]; 9427 9428 u8 reserved_at_e0[0x4]; 9429 u8 phase_grade_type[0x4]; 9430 u8 phase_grade[0x18]; 9431 9432 u8 reserved_at_100[0x8]; 9433 u8 phase_eo_pos[0x8]; 9434 u8 reserved_at_110[0x8]; 9435 u8 phase_eo_neg[0x8]; 9436 9437 u8 ffe_set_tested[0x10]; 9438 u8 test_errors_per_lane[0x10]; 9439 }; 9440 9441 struct mlx5_ifc_pvlc_reg_bits { 9442 u8 reserved_at_0[0x8]; 9443 u8 local_port[0x8]; 9444 u8 reserved_at_10[0x10]; 9445 9446 u8 reserved_at_20[0x1c]; 9447 u8 vl_hw_cap[0x4]; 9448 9449 u8 reserved_at_40[0x1c]; 9450 u8 vl_admin[0x4]; 9451 9452 u8 reserved_at_60[0x1c]; 9453 u8 vl_operational[0x4]; 9454 }; 9455 9456 struct mlx5_ifc_pude_reg_bits { 9457 u8 swid[0x8]; 9458 u8 local_port[0x8]; 9459 u8 reserved_at_10[0x4]; 9460 u8 admin_status[0x4]; 9461 u8 reserved_at_18[0x4]; 9462 u8 oper_status[0x4]; 9463 9464 u8 reserved_at_20[0x60]; 9465 }; 9466 9467 struct mlx5_ifc_ptys_reg_bits { 9468 u8 reserved_at_0[0x1]; 9469 u8 an_disable_admin[0x1]; 9470 u8 an_disable_cap[0x1]; 9471 u8 reserved_at_3[0x5]; 9472 u8 local_port[0x8]; 9473 u8 reserved_at_10[0xd]; 9474 u8 proto_mask[0x3]; 9475 9476 u8 an_status[0x4]; 9477 u8 reserved_at_24[0xc]; 9478 u8 data_rate_oper[0x10]; 9479 9480 u8 ext_eth_proto_capability[0x20]; 9481 9482 u8 eth_proto_capability[0x20]; 9483 9484 u8 ib_link_width_capability[0x10]; 9485 u8 ib_proto_capability[0x10]; 9486 9487 u8 ext_eth_proto_admin[0x20]; 9488 9489 u8 eth_proto_admin[0x20]; 9490 9491 u8 ib_link_width_admin[0x10]; 9492 u8 ib_proto_admin[0x10]; 9493 9494 u8 ext_eth_proto_oper[0x20]; 9495 9496 u8 eth_proto_oper[0x20]; 9497 9498 u8 ib_link_width_oper[0x10]; 9499 u8 ib_proto_oper[0x10]; 9500 9501 u8 reserved_at_160[0x1c]; 9502 u8 connector_type[0x4]; 9503 9504 u8 eth_proto_lp_advertise[0x20]; 9505 9506 u8 reserved_at_1a0[0x60]; 9507 }; 9508 9509 struct mlx5_ifc_mlcr_reg_bits { 9510 u8 reserved_at_0[0x8]; 9511 u8 local_port[0x8]; 9512 u8 reserved_at_10[0x20]; 9513 9514 u8 beacon_duration[0x10]; 9515 u8 reserved_at_40[0x10]; 9516 9517 u8 beacon_remain[0x10]; 9518 }; 9519 9520 struct mlx5_ifc_ptas_reg_bits { 9521 u8 reserved_at_0[0x20]; 9522 9523 u8 algorithm_options[0x10]; 9524 u8 reserved_at_30[0x4]; 9525 u8 repetitions_mode[0x4]; 9526 u8 num_of_repetitions[0x8]; 9527 9528 u8 grade_version[0x8]; 9529 u8 height_grade_type[0x4]; 9530 u8 phase_grade_type[0x4]; 9531 u8 height_grade_weight[0x8]; 9532 u8 phase_grade_weight[0x8]; 9533 9534 u8 gisim_measure_bits[0x10]; 9535 u8 adaptive_tap_measure_bits[0x10]; 9536 9537 u8 ber_bath_high_error_threshold[0x10]; 9538 u8 ber_bath_mid_error_threshold[0x10]; 9539 9540 u8 ber_bath_low_error_threshold[0x10]; 9541 u8 one_ratio_high_threshold[0x10]; 9542 9543 u8 one_ratio_high_mid_threshold[0x10]; 9544 u8 one_ratio_low_mid_threshold[0x10]; 9545 9546 u8 one_ratio_low_threshold[0x10]; 9547 u8 ndeo_error_threshold[0x10]; 9548 9549 u8 mixer_offset_step_size[0x10]; 9550 u8 reserved_at_110[0x8]; 9551 u8 mix90_phase_for_voltage_bath[0x8]; 9552 9553 u8 mixer_offset_start[0x10]; 9554 u8 mixer_offset_end[0x10]; 9555 9556 u8 reserved_at_140[0x15]; 9557 u8 ber_test_time[0xb]; 9558 }; 9559 9560 struct mlx5_ifc_pspa_reg_bits { 9561 u8 swid[0x8]; 9562 u8 local_port[0x8]; 9563 u8 sub_port[0x8]; 9564 u8 reserved_at_18[0x8]; 9565 9566 u8 reserved_at_20[0x20]; 9567 }; 9568 9569 struct mlx5_ifc_pqdr_reg_bits { 9570 u8 reserved_at_0[0x8]; 9571 u8 local_port[0x8]; 9572 u8 reserved_at_10[0x5]; 9573 u8 prio[0x3]; 9574 u8 reserved_at_18[0x6]; 9575 u8 mode[0x2]; 9576 9577 u8 reserved_at_20[0x20]; 9578 9579 u8 reserved_at_40[0x10]; 9580 u8 min_threshold[0x10]; 9581 9582 u8 reserved_at_60[0x10]; 9583 u8 max_threshold[0x10]; 9584 9585 u8 reserved_at_80[0x10]; 9586 u8 mark_probability_denominator[0x10]; 9587 9588 u8 reserved_at_a0[0x60]; 9589 }; 9590 9591 struct mlx5_ifc_ppsc_reg_bits { 9592 u8 reserved_at_0[0x8]; 9593 u8 local_port[0x8]; 9594 u8 reserved_at_10[0x10]; 9595 9596 u8 reserved_at_20[0x60]; 9597 9598 u8 reserved_at_80[0x1c]; 9599 u8 wrps_admin[0x4]; 9600 9601 u8 reserved_at_a0[0x1c]; 9602 u8 wrps_status[0x4]; 9603 9604 u8 reserved_at_c0[0x8]; 9605 u8 up_threshold[0x8]; 9606 u8 reserved_at_d0[0x8]; 9607 u8 down_threshold[0x8]; 9608 9609 u8 reserved_at_e0[0x20]; 9610 9611 u8 reserved_at_100[0x1c]; 9612 u8 srps_admin[0x4]; 9613 9614 u8 reserved_at_120[0x1c]; 9615 u8 srps_status[0x4]; 9616 9617 u8 reserved_at_140[0x40]; 9618 }; 9619 9620 struct mlx5_ifc_pplr_reg_bits { 9621 u8 reserved_at_0[0x8]; 9622 u8 local_port[0x8]; 9623 u8 reserved_at_10[0x10]; 9624 9625 u8 reserved_at_20[0x8]; 9626 u8 lb_cap[0x8]; 9627 u8 reserved_at_30[0x8]; 9628 u8 lb_en[0x8]; 9629 }; 9630 9631 struct mlx5_ifc_pplm_reg_bits { 9632 u8 reserved_at_0[0x8]; 9633 u8 local_port[0x8]; 9634 u8 reserved_at_10[0x10]; 9635 9636 u8 reserved_at_20[0x20]; 9637 9638 u8 port_profile_mode[0x8]; 9639 u8 static_port_profile[0x8]; 9640 u8 active_port_profile[0x8]; 9641 u8 reserved_at_58[0x8]; 9642 9643 u8 retransmission_active[0x8]; 9644 u8 fec_mode_active[0x18]; 9645 9646 u8 rs_fec_correction_bypass_cap[0x4]; 9647 u8 reserved_at_84[0x8]; 9648 u8 fec_override_cap_56g[0x4]; 9649 u8 fec_override_cap_100g[0x4]; 9650 u8 fec_override_cap_50g[0x4]; 9651 u8 fec_override_cap_25g[0x4]; 9652 u8 fec_override_cap_10g_40g[0x4]; 9653 9654 u8 rs_fec_correction_bypass_admin[0x4]; 9655 u8 reserved_at_a4[0x8]; 9656 u8 fec_override_admin_56g[0x4]; 9657 u8 fec_override_admin_100g[0x4]; 9658 u8 fec_override_admin_50g[0x4]; 9659 u8 fec_override_admin_25g[0x4]; 9660 u8 fec_override_admin_10g_40g[0x4]; 9661 9662 u8 fec_override_cap_400g_8x[0x10]; 9663 u8 fec_override_cap_200g_4x[0x10]; 9664 9665 u8 fec_override_cap_100g_2x[0x10]; 9666 u8 fec_override_cap_50g_1x[0x10]; 9667 9668 u8 fec_override_admin_400g_8x[0x10]; 9669 u8 fec_override_admin_200g_4x[0x10]; 9670 9671 u8 fec_override_admin_100g_2x[0x10]; 9672 u8 fec_override_admin_50g_1x[0x10]; 9673 9674 u8 reserved_at_140[0x140]; 9675 }; 9676 9677 struct mlx5_ifc_ppcnt_reg_bits { 9678 u8 swid[0x8]; 9679 u8 local_port[0x8]; 9680 u8 pnat[0x2]; 9681 u8 reserved_at_12[0x8]; 9682 u8 grp[0x6]; 9683 9684 u8 clr[0x1]; 9685 u8 reserved_at_21[0x1c]; 9686 u8 prio_tc[0x3]; 9687 9688 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9689 }; 9690 9691 struct mlx5_ifc_mpein_reg_bits { 9692 u8 reserved_at_0[0x2]; 9693 u8 depth[0x6]; 9694 u8 pcie_index[0x8]; 9695 u8 node[0x8]; 9696 u8 reserved_at_18[0x8]; 9697 9698 u8 capability_mask[0x20]; 9699 9700 u8 reserved_at_40[0x8]; 9701 u8 link_width_enabled[0x8]; 9702 u8 link_speed_enabled[0x10]; 9703 9704 u8 lane0_physical_position[0x8]; 9705 u8 link_width_active[0x8]; 9706 u8 link_speed_active[0x10]; 9707 9708 u8 num_of_pfs[0x10]; 9709 u8 num_of_vfs[0x10]; 9710 9711 u8 bdf0[0x10]; 9712 u8 reserved_at_b0[0x10]; 9713 9714 u8 max_read_request_size[0x4]; 9715 u8 max_payload_size[0x4]; 9716 u8 reserved_at_c8[0x5]; 9717 u8 pwr_status[0x3]; 9718 u8 port_type[0x4]; 9719 u8 reserved_at_d4[0xb]; 9720 u8 lane_reversal[0x1]; 9721 9722 u8 reserved_at_e0[0x14]; 9723 u8 pci_power[0xc]; 9724 9725 u8 reserved_at_100[0x20]; 9726 9727 u8 device_status[0x10]; 9728 u8 port_state[0x8]; 9729 u8 reserved_at_138[0x8]; 9730 9731 u8 reserved_at_140[0x10]; 9732 u8 receiver_detect_result[0x10]; 9733 9734 u8 reserved_at_160[0x20]; 9735 }; 9736 9737 struct mlx5_ifc_mpcnt_reg_bits { 9738 u8 reserved_at_0[0x8]; 9739 u8 pcie_index[0x8]; 9740 u8 reserved_at_10[0xa]; 9741 u8 grp[0x6]; 9742 9743 u8 clr[0x1]; 9744 u8 reserved_at_21[0x1f]; 9745 9746 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9747 }; 9748 9749 struct mlx5_ifc_ppad_reg_bits { 9750 u8 reserved_at_0[0x3]; 9751 u8 single_mac[0x1]; 9752 u8 reserved_at_4[0x4]; 9753 u8 local_port[0x8]; 9754 u8 mac_47_32[0x10]; 9755 9756 u8 mac_31_0[0x20]; 9757 9758 u8 reserved_at_40[0x40]; 9759 }; 9760 9761 struct mlx5_ifc_pmtu_reg_bits { 9762 u8 reserved_at_0[0x8]; 9763 u8 local_port[0x8]; 9764 u8 reserved_at_10[0x10]; 9765 9766 u8 max_mtu[0x10]; 9767 u8 reserved_at_30[0x10]; 9768 9769 u8 admin_mtu[0x10]; 9770 u8 reserved_at_50[0x10]; 9771 9772 u8 oper_mtu[0x10]; 9773 u8 reserved_at_70[0x10]; 9774 }; 9775 9776 struct mlx5_ifc_pmpr_reg_bits { 9777 u8 reserved_at_0[0x8]; 9778 u8 module[0x8]; 9779 u8 reserved_at_10[0x10]; 9780 9781 u8 reserved_at_20[0x18]; 9782 u8 attenuation_5g[0x8]; 9783 9784 u8 reserved_at_40[0x18]; 9785 u8 attenuation_7g[0x8]; 9786 9787 u8 reserved_at_60[0x18]; 9788 u8 attenuation_12g[0x8]; 9789 }; 9790 9791 struct mlx5_ifc_pmpe_reg_bits { 9792 u8 reserved_at_0[0x8]; 9793 u8 module[0x8]; 9794 u8 reserved_at_10[0xc]; 9795 u8 module_status[0x4]; 9796 9797 u8 reserved_at_20[0x60]; 9798 }; 9799 9800 struct mlx5_ifc_pmpc_reg_bits { 9801 u8 module_state_updated[32][0x8]; 9802 }; 9803 9804 struct mlx5_ifc_pmlpn_reg_bits { 9805 u8 reserved_at_0[0x4]; 9806 u8 mlpn_status[0x4]; 9807 u8 local_port[0x8]; 9808 u8 reserved_at_10[0x10]; 9809 9810 u8 e[0x1]; 9811 u8 reserved_at_21[0x1f]; 9812 }; 9813 9814 struct mlx5_ifc_pmlp_reg_bits { 9815 u8 rxtx[0x1]; 9816 u8 reserved_at_1[0x7]; 9817 u8 local_port[0x8]; 9818 u8 reserved_at_10[0x8]; 9819 u8 width[0x8]; 9820 9821 u8 lane0_module_mapping[0x20]; 9822 9823 u8 lane1_module_mapping[0x20]; 9824 9825 u8 lane2_module_mapping[0x20]; 9826 9827 u8 lane3_module_mapping[0x20]; 9828 9829 u8 reserved_at_a0[0x160]; 9830 }; 9831 9832 struct mlx5_ifc_pmaos_reg_bits { 9833 u8 reserved_at_0[0x8]; 9834 u8 module[0x8]; 9835 u8 reserved_at_10[0x4]; 9836 u8 admin_status[0x4]; 9837 u8 reserved_at_18[0x4]; 9838 u8 oper_status[0x4]; 9839 9840 u8 ase[0x1]; 9841 u8 ee[0x1]; 9842 u8 reserved_at_22[0x1c]; 9843 u8 e[0x2]; 9844 9845 u8 reserved_at_40[0x40]; 9846 }; 9847 9848 struct mlx5_ifc_plpc_reg_bits { 9849 u8 reserved_at_0[0x4]; 9850 u8 profile_id[0xc]; 9851 u8 reserved_at_10[0x4]; 9852 u8 proto_mask[0x4]; 9853 u8 reserved_at_18[0x8]; 9854 9855 u8 reserved_at_20[0x10]; 9856 u8 lane_speed[0x10]; 9857 9858 u8 reserved_at_40[0x17]; 9859 u8 lpbf[0x1]; 9860 u8 fec_mode_policy[0x8]; 9861 9862 u8 retransmission_capability[0x8]; 9863 u8 fec_mode_capability[0x18]; 9864 9865 u8 retransmission_support_admin[0x8]; 9866 u8 fec_mode_support_admin[0x18]; 9867 9868 u8 retransmission_request_admin[0x8]; 9869 u8 fec_mode_request_admin[0x18]; 9870 9871 u8 reserved_at_c0[0x80]; 9872 }; 9873 9874 struct mlx5_ifc_plib_reg_bits { 9875 u8 reserved_at_0[0x8]; 9876 u8 local_port[0x8]; 9877 u8 reserved_at_10[0x8]; 9878 u8 ib_port[0x8]; 9879 9880 u8 reserved_at_20[0x60]; 9881 }; 9882 9883 struct mlx5_ifc_plbf_reg_bits { 9884 u8 reserved_at_0[0x8]; 9885 u8 local_port[0x8]; 9886 u8 reserved_at_10[0xd]; 9887 u8 lbf_mode[0x3]; 9888 9889 u8 reserved_at_20[0x20]; 9890 }; 9891 9892 struct mlx5_ifc_pipg_reg_bits { 9893 u8 reserved_at_0[0x8]; 9894 u8 local_port[0x8]; 9895 u8 reserved_at_10[0x10]; 9896 9897 u8 dic[0x1]; 9898 u8 reserved_at_21[0x19]; 9899 u8 ipg[0x4]; 9900 u8 reserved_at_3e[0x2]; 9901 }; 9902 9903 struct mlx5_ifc_pifr_reg_bits { 9904 u8 reserved_at_0[0x8]; 9905 u8 local_port[0x8]; 9906 u8 reserved_at_10[0x10]; 9907 9908 u8 reserved_at_20[0xe0]; 9909 9910 u8 port_filter[8][0x20]; 9911 9912 u8 port_filter_update_en[8][0x20]; 9913 }; 9914 9915 struct mlx5_ifc_pfcc_reg_bits { 9916 u8 reserved_at_0[0x8]; 9917 u8 local_port[0x8]; 9918 u8 reserved_at_10[0xb]; 9919 u8 ppan_mask_n[0x1]; 9920 u8 minor_stall_mask[0x1]; 9921 u8 critical_stall_mask[0x1]; 9922 u8 reserved_at_1e[0x2]; 9923 9924 u8 ppan[0x4]; 9925 u8 reserved_at_24[0x4]; 9926 u8 prio_mask_tx[0x8]; 9927 u8 reserved_at_30[0x8]; 9928 u8 prio_mask_rx[0x8]; 9929 9930 u8 pptx[0x1]; 9931 u8 aptx[0x1]; 9932 u8 pptx_mask_n[0x1]; 9933 u8 reserved_at_43[0x5]; 9934 u8 pfctx[0x8]; 9935 u8 reserved_at_50[0x10]; 9936 9937 u8 pprx[0x1]; 9938 u8 aprx[0x1]; 9939 u8 pprx_mask_n[0x1]; 9940 u8 reserved_at_63[0x5]; 9941 u8 pfcrx[0x8]; 9942 u8 reserved_at_70[0x10]; 9943 9944 u8 device_stall_minor_watermark[0x10]; 9945 u8 device_stall_critical_watermark[0x10]; 9946 9947 u8 reserved_at_a0[0x60]; 9948 }; 9949 9950 struct mlx5_ifc_pelc_reg_bits { 9951 u8 op[0x4]; 9952 u8 reserved_at_4[0x4]; 9953 u8 local_port[0x8]; 9954 u8 reserved_at_10[0x10]; 9955 9956 u8 op_admin[0x8]; 9957 u8 op_capability[0x8]; 9958 u8 op_request[0x8]; 9959 u8 op_active[0x8]; 9960 9961 u8 admin[0x40]; 9962 9963 u8 capability[0x40]; 9964 9965 u8 request[0x40]; 9966 9967 u8 active[0x40]; 9968 9969 u8 reserved_at_140[0x80]; 9970 }; 9971 9972 struct mlx5_ifc_peir_reg_bits { 9973 u8 reserved_at_0[0x8]; 9974 u8 local_port[0x8]; 9975 u8 reserved_at_10[0x10]; 9976 9977 u8 reserved_at_20[0xc]; 9978 u8 error_count[0x4]; 9979 u8 reserved_at_30[0x10]; 9980 9981 u8 reserved_at_40[0xc]; 9982 u8 lane[0x4]; 9983 u8 reserved_at_50[0x8]; 9984 u8 error_type[0x8]; 9985 }; 9986 9987 struct mlx5_ifc_mpegc_reg_bits { 9988 u8 reserved_at_0[0x30]; 9989 u8 field_select[0x10]; 9990 9991 u8 tx_overflow_sense[0x1]; 9992 u8 mark_cqe[0x1]; 9993 u8 mark_cnp[0x1]; 9994 u8 reserved_at_43[0x1b]; 9995 u8 tx_lossy_overflow_oper[0x2]; 9996 9997 u8 reserved_at_60[0x100]; 9998 }; 9999 10000 enum { 10001 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10002 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10003 }; 10004 10005 enum { 10006 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10007 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10008 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10009 }; 10010 10011 struct mlx5_ifc_mtutc_reg_bits { 10012 u8 reserved_at_0[0x5]; 10013 u8 freq_adj_units[0x3]; 10014 u8 reserved_at_8[0x14]; 10015 u8 operation[0x4]; 10016 10017 u8 freq_adjustment[0x20]; 10018 10019 u8 reserved_at_40[0x40]; 10020 10021 u8 utc_sec[0x20]; 10022 10023 u8 reserved_at_a0[0x2]; 10024 u8 utc_nsec[0x1e]; 10025 10026 u8 time_adjustment[0x20]; 10027 }; 10028 10029 struct mlx5_ifc_pcam_enhanced_features_bits { 10030 u8 reserved_at_0[0x68]; 10031 u8 fec_50G_per_lane_in_pplm[0x1]; 10032 u8 reserved_at_69[0x4]; 10033 u8 rx_icrc_encapsulated_counter[0x1]; 10034 u8 reserved_at_6e[0x4]; 10035 u8 ptys_extended_ethernet[0x1]; 10036 u8 reserved_at_73[0x3]; 10037 u8 pfcc_mask[0x1]; 10038 u8 reserved_at_77[0x3]; 10039 u8 per_lane_error_counters[0x1]; 10040 u8 rx_buffer_fullness_counters[0x1]; 10041 u8 ptys_connector_type[0x1]; 10042 u8 reserved_at_7d[0x1]; 10043 u8 ppcnt_discard_group[0x1]; 10044 u8 ppcnt_statistical_group[0x1]; 10045 }; 10046 10047 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10048 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10049 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10050 10051 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10052 u8 pplm[0x1]; 10053 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10054 10055 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10056 u8 pbmc[0x1]; 10057 u8 pptb[0x1]; 10058 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10059 u8 ppcnt[0x1]; 10060 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10061 }; 10062 10063 struct mlx5_ifc_pcam_reg_bits { 10064 u8 reserved_at_0[0x8]; 10065 u8 feature_group[0x8]; 10066 u8 reserved_at_10[0x8]; 10067 u8 access_reg_group[0x8]; 10068 10069 u8 reserved_at_20[0x20]; 10070 10071 union { 10072 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10073 u8 reserved_at_0[0x80]; 10074 } port_access_reg_cap_mask; 10075 10076 u8 reserved_at_c0[0x80]; 10077 10078 union { 10079 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10080 u8 reserved_at_0[0x80]; 10081 } feature_cap_mask; 10082 10083 u8 reserved_at_1c0[0xc0]; 10084 }; 10085 10086 struct mlx5_ifc_mcam_enhanced_features_bits { 10087 u8 reserved_at_0[0x50]; 10088 u8 mtutc_freq_adj_units[0x1]; 10089 u8 mtutc_time_adjustment_extended_range[0x1]; 10090 u8 reserved_at_52[0xb]; 10091 u8 mcia_32dwords[0x1]; 10092 u8 out_pulse_duration_ns[0x1]; 10093 u8 npps_period[0x1]; 10094 u8 reserved_at_60[0xa]; 10095 u8 reset_state[0x1]; 10096 u8 ptpcyc2realtime_modify[0x1]; 10097 u8 reserved_at_6c[0x2]; 10098 u8 pci_status_and_power[0x1]; 10099 u8 reserved_at_6f[0x5]; 10100 u8 mark_tx_action_cnp[0x1]; 10101 u8 mark_tx_action_cqe[0x1]; 10102 u8 dynamic_tx_overflow[0x1]; 10103 u8 reserved_at_77[0x4]; 10104 u8 pcie_outbound_stalled[0x1]; 10105 u8 tx_overflow_buffer_pkt[0x1]; 10106 u8 mtpps_enh_out_per_adj[0x1]; 10107 u8 mtpps_fs[0x1]; 10108 u8 pcie_performance_group[0x1]; 10109 }; 10110 10111 struct mlx5_ifc_mcam_access_reg_bits { 10112 u8 reserved_at_0[0x1c]; 10113 u8 mcda[0x1]; 10114 u8 mcc[0x1]; 10115 u8 mcqi[0x1]; 10116 u8 mcqs[0x1]; 10117 10118 u8 regs_95_to_87[0x9]; 10119 u8 mpegc[0x1]; 10120 u8 mtutc[0x1]; 10121 u8 regs_84_to_68[0x11]; 10122 u8 tracer_registers[0x4]; 10123 10124 u8 regs_63_to_46[0x12]; 10125 u8 mrtc[0x1]; 10126 u8 regs_44_to_32[0xd]; 10127 10128 u8 regs_31_to_0[0x20]; 10129 }; 10130 10131 struct mlx5_ifc_mcam_access_reg_bits1 { 10132 u8 regs_127_to_96[0x20]; 10133 10134 u8 regs_95_to_64[0x20]; 10135 10136 u8 regs_63_to_32[0x20]; 10137 10138 u8 regs_31_to_0[0x20]; 10139 }; 10140 10141 struct mlx5_ifc_mcam_access_reg_bits2 { 10142 u8 regs_127_to_99[0x1d]; 10143 u8 mirc[0x1]; 10144 u8 regs_97_to_96[0x2]; 10145 10146 u8 regs_95_to_64[0x20]; 10147 10148 u8 regs_63_to_32[0x20]; 10149 10150 u8 regs_31_to_0[0x20]; 10151 }; 10152 10153 struct mlx5_ifc_mcam_reg_bits { 10154 u8 reserved_at_0[0x8]; 10155 u8 feature_group[0x8]; 10156 u8 reserved_at_10[0x8]; 10157 u8 access_reg_group[0x8]; 10158 10159 u8 reserved_at_20[0x20]; 10160 10161 union { 10162 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10163 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10164 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10165 u8 reserved_at_0[0x80]; 10166 } mng_access_reg_cap_mask; 10167 10168 u8 reserved_at_c0[0x80]; 10169 10170 union { 10171 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10172 u8 reserved_at_0[0x80]; 10173 } mng_feature_cap_mask; 10174 10175 u8 reserved_at_1c0[0x80]; 10176 }; 10177 10178 struct mlx5_ifc_qcam_access_reg_cap_mask { 10179 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10180 u8 qpdpm[0x1]; 10181 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10182 u8 qdpm[0x1]; 10183 u8 qpts[0x1]; 10184 u8 qcap[0x1]; 10185 u8 qcam_access_reg_cap_mask_0[0x1]; 10186 }; 10187 10188 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10189 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10190 u8 qpts_trust_both[0x1]; 10191 }; 10192 10193 struct mlx5_ifc_qcam_reg_bits { 10194 u8 reserved_at_0[0x8]; 10195 u8 feature_group[0x8]; 10196 u8 reserved_at_10[0x8]; 10197 u8 access_reg_group[0x8]; 10198 u8 reserved_at_20[0x20]; 10199 10200 union { 10201 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10202 u8 reserved_at_0[0x80]; 10203 } qos_access_reg_cap_mask; 10204 10205 u8 reserved_at_c0[0x80]; 10206 10207 union { 10208 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10209 u8 reserved_at_0[0x80]; 10210 } qos_feature_cap_mask; 10211 10212 u8 reserved_at_1c0[0x80]; 10213 }; 10214 10215 struct mlx5_ifc_core_dump_reg_bits { 10216 u8 reserved_at_0[0x18]; 10217 u8 core_dump_type[0x8]; 10218 10219 u8 reserved_at_20[0x30]; 10220 u8 vhca_id[0x10]; 10221 10222 u8 reserved_at_60[0x8]; 10223 u8 qpn[0x18]; 10224 u8 reserved_at_80[0x180]; 10225 }; 10226 10227 struct mlx5_ifc_pcap_reg_bits { 10228 u8 reserved_at_0[0x8]; 10229 u8 local_port[0x8]; 10230 u8 reserved_at_10[0x10]; 10231 10232 u8 port_capability_mask[4][0x20]; 10233 }; 10234 10235 struct mlx5_ifc_paos_reg_bits { 10236 u8 swid[0x8]; 10237 u8 local_port[0x8]; 10238 u8 reserved_at_10[0x4]; 10239 u8 admin_status[0x4]; 10240 u8 reserved_at_18[0x4]; 10241 u8 oper_status[0x4]; 10242 10243 u8 ase[0x1]; 10244 u8 ee[0x1]; 10245 u8 reserved_at_22[0x1c]; 10246 u8 e[0x2]; 10247 10248 u8 reserved_at_40[0x40]; 10249 }; 10250 10251 struct mlx5_ifc_pamp_reg_bits { 10252 u8 reserved_at_0[0x8]; 10253 u8 opamp_group[0x8]; 10254 u8 reserved_at_10[0xc]; 10255 u8 opamp_group_type[0x4]; 10256 10257 u8 start_index[0x10]; 10258 u8 reserved_at_30[0x4]; 10259 u8 num_of_indices[0xc]; 10260 10261 u8 index_data[18][0x10]; 10262 }; 10263 10264 struct mlx5_ifc_pcmr_reg_bits { 10265 u8 reserved_at_0[0x8]; 10266 u8 local_port[0x8]; 10267 u8 reserved_at_10[0x10]; 10268 10269 u8 entropy_force_cap[0x1]; 10270 u8 entropy_calc_cap[0x1]; 10271 u8 entropy_gre_calc_cap[0x1]; 10272 u8 reserved_at_23[0xf]; 10273 u8 rx_ts_over_crc_cap[0x1]; 10274 u8 reserved_at_33[0xb]; 10275 u8 fcs_cap[0x1]; 10276 u8 reserved_at_3f[0x1]; 10277 10278 u8 entropy_force[0x1]; 10279 u8 entropy_calc[0x1]; 10280 u8 entropy_gre_calc[0x1]; 10281 u8 reserved_at_43[0xf]; 10282 u8 rx_ts_over_crc[0x1]; 10283 u8 reserved_at_53[0xb]; 10284 u8 fcs_chk[0x1]; 10285 u8 reserved_at_5f[0x1]; 10286 }; 10287 10288 struct mlx5_ifc_lane_2_module_mapping_bits { 10289 u8 reserved_at_0[0x4]; 10290 u8 rx_lane[0x4]; 10291 u8 reserved_at_8[0x4]; 10292 u8 tx_lane[0x4]; 10293 u8 reserved_at_10[0x8]; 10294 u8 module[0x8]; 10295 }; 10296 10297 struct mlx5_ifc_bufferx_reg_bits { 10298 u8 reserved_at_0[0x6]; 10299 u8 lossy[0x1]; 10300 u8 epsb[0x1]; 10301 u8 reserved_at_8[0x8]; 10302 u8 size[0x10]; 10303 10304 u8 xoff_threshold[0x10]; 10305 u8 xon_threshold[0x10]; 10306 }; 10307 10308 struct mlx5_ifc_set_node_in_bits { 10309 u8 node_description[64][0x8]; 10310 }; 10311 10312 struct mlx5_ifc_register_power_settings_bits { 10313 u8 reserved_at_0[0x18]; 10314 u8 power_settings_level[0x8]; 10315 10316 u8 reserved_at_20[0x60]; 10317 }; 10318 10319 struct mlx5_ifc_register_host_endianness_bits { 10320 u8 he[0x1]; 10321 u8 reserved_at_1[0x1f]; 10322 10323 u8 reserved_at_20[0x60]; 10324 }; 10325 10326 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10327 u8 reserved_at_0[0x20]; 10328 10329 u8 mkey[0x20]; 10330 10331 u8 addressh_63_32[0x20]; 10332 10333 u8 addressl_31_0[0x20]; 10334 }; 10335 10336 struct mlx5_ifc_ud_adrs_vector_bits { 10337 u8 dc_key[0x40]; 10338 10339 u8 ext[0x1]; 10340 u8 reserved_at_41[0x7]; 10341 u8 destination_qp_dct[0x18]; 10342 10343 u8 static_rate[0x4]; 10344 u8 sl_eth_prio[0x4]; 10345 u8 fl[0x1]; 10346 u8 mlid[0x7]; 10347 u8 rlid_udp_sport[0x10]; 10348 10349 u8 reserved_at_80[0x20]; 10350 10351 u8 rmac_47_16[0x20]; 10352 10353 u8 rmac_15_0[0x10]; 10354 u8 tclass[0x8]; 10355 u8 hop_limit[0x8]; 10356 10357 u8 reserved_at_e0[0x1]; 10358 u8 grh[0x1]; 10359 u8 reserved_at_e2[0x2]; 10360 u8 src_addr_index[0x8]; 10361 u8 flow_label[0x14]; 10362 10363 u8 rgid_rip[16][0x8]; 10364 }; 10365 10366 struct mlx5_ifc_pages_req_event_bits { 10367 u8 reserved_at_0[0x10]; 10368 u8 function_id[0x10]; 10369 10370 u8 num_pages[0x20]; 10371 10372 u8 reserved_at_40[0xa0]; 10373 }; 10374 10375 struct mlx5_ifc_eqe_bits { 10376 u8 reserved_at_0[0x8]; 10377 u8 event_type[0x8]; 10378 u8 reserved_at_10[0x8]; 10379 u8 event_sub_type[0x8]; 10380 10381 u8 reserved_at_20[0xe0]; 10382 10383 union mlx5_ifc_event_auto_bits event_data; 10384 10385 u8 reserved_at_1e0[0x10]; 10386 u8 signature[0x8]; 10387 u8 reserved_at_1f8[0x7]; 10388 u8 owner[0x1]; 10389 }; 10390 10391 enum { 10392 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10393 }; 10394 10395 struct mlx5_ifc_cmd_queue_entry_bits { 10396 u8 type[0x8]; 10397 u8 reserved_at_8[0x18]; 10398 10399 u8 input_length[0x20]; 10400 10401 u8 input_mailbox_pointer_63_32[0x20]; 10402 10403 u8 input_mailbox_pointer_31_9[0x17]; 10404 u8 reserved_at_77[0x9]; 10405 10406 u8 command_input_inline_data[16][0x8]; 10407 10408 u8 command_output_inline_data[16][0x8]; 10409 10410 u8 output_mailbox_pointer_63_32[0x20]; 10411 10412 u8 output_mailbox_pointer_31_9[0x17]; 10413 u8 reserved_at_1b7[0x9]; 10414 10415 u8 output_length[0x20]; 10416 10417 u8 token[0x8]; 10418 u8 signature[0x8]; 10419 u8 reserved_at_1f0[0x8]; 10420 u8 status[0x7]; 10421 u8 ownership[0x1]; 10422 }; 10423 10424 struct mlx5_ifc_cmd_out_bits { 10425 u8 status[0x8]; 10426 u8 reserved_at_8[0x18]; 10427 10428 u8 syndrome[0x20]; 10429 10430 u8 command_output[0x20]; 10431 }; 10432 10433 struct mlx5_ifc_cmd_in_bits { 10434 u8 opcode[0x10]; 10435 u8 reserved_at_10[0x10]; 10436 10437 u8 reserved_at_20[0x10]; 10438 u8 op_mod[0x10]; 10439 10440 u8 command[][0x20]; 10441 }; 10442 10443 struct mlx5_ifc_cmd_if_box_bits { 10444 u8 mailbox_data[512][0x8]; 10445 10446 u8 reserved_at_1000[0x180]; 10447 10448 u8 next_pointer_63_32[0x20]; 10449 10450 u8 next_pointer_31_10[0x16]; 10451 u8 reserved_at_11b6[0xa]; 10452 10453 u8 block_number[0x20]; 10454 10455 u8 reserved_at_11e0[0x8]; 10456 u8 token[0x8]; 10457 u8 ctrl_signature[0x8]; 10458 u8 signature[0x8]; 10459 }; 10460 10461 struct mlx5_ifc_mtt_bits { 10462 u8 ptag_63_32[0x20]; 10463 10464 u8 ptag_31_8[0x18]; 10465 u8 reserved_at_38[0x6]; 10466 u8 wr_en[0x1]; 10467 u8 rd_en[0x1]; 10468 }; 10469 10470 struct mlx5_ifc_query_wol_rol_out_bits { 10471 u8 status[0x8]; 10472 u8 reserved_at_8[0x18]; 10473 10474 u8 syndrome[0x20]; 10475 10476 u8 reserved_at_40[0x10]; 10477 u8 rol_mode[0x8]; 10478 u8 wol_mode[0x8]; 10479 10480 u8 reserved_at_60[0x20]; 10481 }; 10482 10483 struct mlx5_ifc_query_wol_rol_in_bits { 10484 u8 opcode[0x10]; 10485 u8 reserved_at_10[0x10]; 10486 10487 u8 reserved_at_20[0x10]; 10488 u8 op_mod[0x10]; 10489 10490 u8 reserved_at_40[0x40]; 10491 }; 10492 10493 struct mlx5_ifc_set_wol_rol_out_bits { 10494 u8 status[0x8]; 10495 u8 reserved_at_8[0x18]; 10496 10497 u8 syndrome[0x20]; 10498 10499 u8 reserved_at_40[0x40]; 10500 }; 10501 10502 struct mlx5_ifc_set_wol_rol_in_bits { 10503 u8 opcode[0x10]; 10504 u8 reserved_at_10[0x10]; 10505 10506 u8 reserved_at_20[0x10]; 10507 u8 op_mod[0x10]; 10508 10509 u8 rol_mode_valid[0x1]; 10510 u8 wol_mode_valid[0x1]; 10511 u8 reserved_at_42[0xe]; 10512 u8 rol_mode[0x8]; 10513 u8 wol_mode[0x8]; 10514 10515 u8 reserved_at_60[0x20]; 10516 }; 10517 10518 enum { 10519 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10520 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10521 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10522 }; 10523 10524 enum { 10525 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10526 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10527 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10528 }; 10529 10530 enum { 10531 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10532 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10533 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10534 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10535 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10536 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10537 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10538 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10539 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10540 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10541 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10542 }; 10543 10544 struct mlx5_ifc_initial_seg_bits { 10545 u8 fw_rev_minor[0x10]; 10546 u8 fw_rev_major[0x10]; 10547 10548 u8 cmd_interface_rev[0x10]; 10549 u8 fw_rev_subminor[0x10]; 10550 10551 u8 reserved_at_40[0x40]; 10552 10553 u8 cmdq_phy_addr_63_32[0x20]; 10554 10555 u8 cmdq_phy_addr_31_12[0x14]; 10556 u8 reserved_at_b4[0x2]; 10557 u8 nic_interface[0x2]; 10558 u8 log_cmdq_size[0x4]; 10559 u8 log_cmdq_stride[0x4]; 10560 10561 u8 command_doorbell_vector[0x20]; 10562 10563 u8 reserved_at_e0[0xf00]; 10564 10565 u8 initializing[0x1]; 10566 u8 reserved_at_fe1[0x4]; 10567 u8 nic_interface_supported[0x3]; 10568 u8 embedded_cpu[0x1]; 10569 u8 reserved_at_fe9[0x17]; 10570 10571 struct mlx5_ifc_health_buffer_bits health_buffer; 10572 10573 u8 no_dram_nic_offset[0x20]; 10574 10575 u8 reserved_at_1220[0x6e40]; 10576 10577 u8 reserved_at_8060[0x1f]; 10578 u8 clear_int[0x1]; 10579 10580 u8 health_syndrome[0x8]; 10581 u8 health_counter[0x18]; 10582 10583 u8 reserved_at_80a0[0x17fc0]; 10584 }; 10585 10586 struct mlx5_ifc_mtpps_reg_bits { 10587 u8 reserved_at_0[0xc]; 10588 u8 cap_number_of_pps_pins[0x4]; 10589 u8 reserved_at_10[0x4]; 10590 u8 cap_max_num_of_pps_in_pins[0x4]; 10591 u8 reserved_at_18[0x4]; 10592 u8 cap_max_num_of_pps_out_pins[0x4]; 10593 10594 u8 reserved_at_20[0x13]; 10595 u8 cap_log_min_npps_period[0x5]; 10596 u8 reserved_at_38[0x3]; 10597 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10598 10599 u8 reserved_at_40[0x4]; 10600 u8 cap_pin_3_mode[0x4]; 10601 u8 reserved_at_48[0x4]; 10602 u8 cap_pin_2_mode[0x4]; 10603 u8 reserved_at_50[0x4]; 10604 u8 cap_pin_1_mode[0x4]; 10605 u8 reserved_at_58[0x4]; 10606 u8 cap_pin_0_mode[0x4]; 10607 10608 u8 reserved_at_60[0x4]; 10609 u8 cap_pin_7_mode[0x4]; 10610 u8 reserved_at_68[0x4]; 10611 u8 cap_pin_6_mode[0x4]; 10612 u8 reserved_at_70[0x4]; 10613 u8 cap_pin_5_mode[0x4]; 10614 u8 reserved_at_78[0x4]; 10615 u8 cap_pin_4_mode[0x4]; 10616 10617 u8 field_select[0x20]; 10618 u8 reserved_at_a0[0x20]; 10619 10620 u8 npps_period[0x40]; 10621 10622 u8 enable[0x1]; 10623 u8 reserved_at_101[0xb]; 10624 u8 pattern[0x4]; 10625 u8 reserved_at_110[0x4]; 10626 u8 pin_mode[0x4]; 10627 u8 pin[0x8]; 10628 10629 u8 reserved_at_120[0x2]; 10630 u8 out_pulse_duration_ns[0x1e]; 10631 10632 u8 time_stamp[0x40]; 10633 10634 u8 out_pulse_duration[0x10]; 10635 u8 out_periodic_adjustment[0x10]; 10636 u8 enhanced_out_periodic_adjustment[0x20]; 10637 10638 u8 reserved_at_1c0[0x20]; 10639 }; 10640 10641 struct mlx5_ifc_mtppse_reg_bits { 10642 u8 reserved_at_0[0x18]; 10643 u8 pin[0x8]; 10644 u8 event_arm[0x1]; 10645 u8 reserved_at_21[0x1b]; 10646 u8 event_generation_mode[0x4]; 10647 u8 reserved_at_40[0x40]; 10648 }; 10649 10650 struct mlx5_ifc_mcqs_reg_bits { 10651 u8 last_index_flag[0x1]; 10652 u8 reserved_at_1[0x7]; 10653 u8 fw_device[0x8]; 10654 u8 component_index[0x10]; 10655 10656 u8 reserved_at_20[0x10]; 10657 u8 identifier[0x10]; 10658 10659 u8 reserved_at_40[0x17]; 10660 u8 component_status[0x5]; 10661 u8 component_update_state[0x4]; 10662 10663 u8 last_update_state_changer_type[0x4]; 10664 u8 last_update_state_changer_host_id[0x4]; 10665 u8 reserved_at_68[0x18]; 10666 }; 10667 10668 struct mlx5_ifc_mcqi_cap_bits { 10669 u8 supported_info_bitmask[0x20]; 10670 10671 u8 component_size[0x20]; 10672 10673 u8 max_component_size[0x20]; 10674 10675 u8 log_mcda_word_size[0x4]; 10676 u8 reserved_at_64[0xc]; 10677 u8 mcda_max_write_size[0x10]; 10678 10679 u8 rd_en[0x1]; 10680 u8 reserved_at_81[0x1]; 10681 u8 match_chip_id[0x1]; 10682 u8 match_psid[0x1]; 10683 u8 check_user_timestamp[0x1]; 10684 u8 match_base_guid_mac[0x1]; 10685 u8 reserved_at_86[0x1a]; 10686 }; 10687 10688 struct mlx5_ifc_mcqi_version_bits { 10689 u8 reserved_at_0[0x2]; 10690 u8 build_time_valid[0x1]; 10691 u8 user_defined_time_valid[0x1]; 10692 u8 reserved_at_4[0x14]; 10693 u8 version_string_length[0x8]; 10694 10695 u8 version[0x20]; 10696 10697 u8 build_time[0x40]; 10698 10699 u8 user_defined_time[0x40]; 10700 10701 u8 build_tool_version[0x20]; 10702 10703 u8 reserved_at_e0[0x20]; 10704 10705 u8 version_string[92][0x8]; 10706 }; 10707 10708 struct mlx5_ifc_mcqi_activation_method_bits { 10709 u8 pending_server_ac_power_cycle[0x1]; 10710 u8 pending_server_dc_power_cycle[0x1]; 10711 u8 pending_server_reboot[0x1]; 10712 u8 pending_fw_reset[0x1]; 10713 u8 auto_activate[0x1]; 10714 u8 all_hosts_sync[0x1]; 10715 u8 device_hw_reset[0x1]; 10716 u8 reserved_at_7[0x19]; 10717 }; 10718 10719 union mlx5_ifc_mcqi_reg_data_bits { 10720 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10721 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10722 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10723 }; 10724 10725 struct mlx5_ifc_mcqi_reg_bits { 10726 u8 read_pending_component[0x1]; 10727 u8 reserved_at_1[0xf]; 10728 u8 component_index[0x10]; 10729 10730 u8 reserved_at_20[0x20]; 10731 10732 u8 reserved_at_40[0x1b]; 10733 u8 info_type[0x5]; 10734 10735 u8 info_size[0x20]; 10736 10737 u8 offset[0x20]; 10738 10739 u8 reserved_at_a0[0x10]; 10740 u8 data_size[0x10]; 10741 10742 union mlx5_ifc_mcqi_reg_data_bits data[]; 10743 }; 10744 10745 struct mlx5_ifc_mcc_reg_bits { 10746 u8 reserved_at_0[0x4]; 10747 u8 time_elapsed_since_last_cmd[0xc]; 10748 u8 reserved_at_10[0x8]; 10749 u8 instruction[0x8]; 10750 10751 u8 reserved_at_20[0x10]; 10752 u8 component_index[0x10]; 10753 10754 u8 reserved_at_40[0x8]; 10755 u8 update_handle[0x18]; 10756 10757 u8 handle_owner_type[0x4]; 10758 u8 handle_owner_host_id[0x4]; 10759 u8 reserved_at_68[0x1]; 10760 u8 control_progress[0x7]; 10761 u8 error_code[0x8]; 10762 u8 reserved_at_78[0x4]; 10763 u8 control_state[0x4]; 10764 10765 u8 component_size[0x20]; 10766 10767 u8 reserved_at_a0[0x60]; 10768 }; 10769 10770 struct mlx5_ifc_mcda_reg_bits { 10771 u8 reserved_at_0[0x8]; 10772 u8 update_handle[0x18]; 10773 10774 u8 offset[0x20]; 10775 10776 u8 reserved_at_40[0x10]; 10777 u8 size[0x10]; 10778 10779 u8 reserved_at_60[0x20]; 10780 10781 u8 data[][0x20]; 10782 }; 10783 10784 enum { 10785 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10786 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10787 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10788 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10789 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10790 }; 10791 10792 enum { 10793 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10794 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10795 }; 10796 10797 enum { 10798 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10799 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10800 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10801 }; 10802 10803 struct mlx5_ifc_mfrl_reg_bits { 10804 u8 reserved_at_0[0x20]; 10805 10806 u8 reserved_at_20[0x2]; 10807 u8 pci_sync_for_fw_update_start[0x1]; 10808 u8 pci_sync_for_fw_update_resp[0x2]; 10809 u8 rst_type_sel[0x3]; 10810 u8 reserved_at_28[0x4]; 10811 u8 reset_state[0x4]; 10812 u8 reset_type[0x8]; 10813 u8 reset_level[0x8]; 10814 }; 10815 10816 struct mlx5_ifc_mirc_reg_bits { 10817 u8 reserved_at_0[0x18]; 10818 u8 status_code[0x8]; 10819 10820 u8 reserved_at_20[0x20]; 10821 }; 10822 10823 struct mlx5_ifc_pddr_monitor_opcode_bits { 10824 u8 reserved_at_0[0x10]; 10825 u8 monitor_opcode[0x10]; 10826 }; 10827 10828 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10829 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10830 u8 reserved_at_0[0x20]; 10831 }; 10832 10833 enum { 10834 /* Monitor opcodes */ 10835 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10836 }; 10837 10838 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10839 u8 reserved_at_0[0x10]; 10840 u8 group_opcode[0x10]; 10841 10842 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10843 10844 u8 reserved_at_40[0x20]; 10845 10846 u8 status_message[59][0x20]; 10847 }; 10848 10849 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10850 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10851 u8 reserved_at_0[0x7c0]; 10852 }; 10853 10854 enum { 10855 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10856 }; 10857 10858 struct mlx5_ifc_pddr_reg_bits { 10859 u8 reserved_at_0[0x8]; 10860 u8 local_port[0x8]; 10861 u8 pnat[0x2]; 10862 u8 reserved_at_12[0xe]; 10863 10864 u8 reserved_at_20[0x18]; 10865 u8 page_select[0x8]; 10866 10867 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10868 }; 10869 10870 struct mlx5_ifc_mrtc_reg_bits { 10871 u8 time_synced[0x1]; 10872 u8 reserved_at_1[0x1f]; 10873 10874 u8 reserved_at_20[0x20]; 10875 10876 u8 time_h[0x20]; 10877 10878 u8 time_l[0x20]; 10879 }; 10880 10881 struct mlx5_ifc_mtmp_reg_bits { 10882 u8 reserved_at_0[0x14]; 10883 u8 sensor_index[0xc]; 10884 10885 u8 reserved_at_20[0x10]; 10886 u8 temperature[0x10]; 10887 10888 u8 mte[0x1]; 10889 u8 mtr[0x1]; 10890 u8 reserved_at_42[0xe]; 10891 u8 max_temperature[0x10]; 10892 10893 u8 tee[0x2]; 10894 u8 reserved_at_62[0xe]; 10895 u8 temp_threshold_hi[0x10]; 10896 10897 u8 reserved_at_80[0x10]; 10898 u8 temp_threshold_lo[0x10]; 10899 10900 u8 reserved_at_a0[0x20]; 10901 10902 u8 sensor_name_hi[0x20]; 10903 u8 sensor_name_lo[0x20]; 10904 }; 10905 10906 union mlx5_ifc_ports_control_registers_document_bits { 10907 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10908 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10909 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10910 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10911 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10912 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10913 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10914 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10915 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10916 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10917 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10918 struct mlx5_ifc_paos_reg_bits paos_reg; 10919 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10920 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10921 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10922 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10923 struct mlx5_ifc_peir_reg_bits peir_reg; 10924 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10925 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10926 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10927 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10928 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10929 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10930 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10931 struct mlx5_ifc_plib_reg_bits plib_reg; 10932 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10933 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10934 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10935 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10936 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10937 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10938 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10939 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10940 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10941 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10942 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10943 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10944 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10945 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10946 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10947 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10948 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10949 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10950 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10951 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10952 struct mlx5_ifc_pude_reg_bits pude_reg; 10953 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10954 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10955 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10956 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10957 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10958 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10959 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10960 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10961 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10962 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10963 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10964 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10965 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10966 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10967 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10968 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 10969 u8 reserved_at_0[0x60e0]; 10970 }; 10971 10972 union mlx5_ifc_debug_enhancements_document_bits { 10973 struct mlx5_ifc_health_buffer_bits health_buffer; 10974 u8 reserved_at_0[0x200]; 10975 }; 10976 10977 union mlx5_ifc_uplink_pci_interface_document_bits { 10978 struct mlx5_ifc_initial_seg_bits initial_seg; 10979 u8 reserved_at_0[0x20060]; 10980 }; 10981 10982 struct mlx5_ifc_set_flow_table_root_out_bits { 10983 u8 status[0x8]; 10984 u8 reserved_at_8[0x18]; 10985 10986 u8 syndrome[0x20]; 10987 10988 u8 reserved_at_40[0x40]; 10989 }; 10990 10991 struct mlx5_ifc_set_flow_table_root_in_bits { 10992 u8 opcode[0x10]; 10993 u8 reserved_at_10[0x10]; 10994 10995 u8 reserved_at_20[0x10]; 10996 u8 op_mod[0x10]; 10997 10998 u8 other_vport[0x1]; 10999 u8 reserved_at_41[0xf]; 11000 u8 vport_number[0x10]; 11001 11002 u8 reserved_at_60[0x20]; 11003 11004 u8 table_type[0x8]; 11005 u8 reserved_at_88[0x7]; 11006 u8 table_of_other_vport[0x1]; 11007 u8 table_vport_number[0x10]; 11008 11009 u8 reserved_at_a0[0x8]; 11010 u8 table_id[0x18]; 11011 11012 u8 reserved_at_c0[0x8]; 11013 u8 underlay_qpn[0x18]; 11014 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11015 u8 reserved_at_e1[0xf]; 11016 u8 table_eswitch_owner_vhca_id[0x10]; 11017 u8 reserved_at_100[0x100]; 11018 }; 11019 11020 enum { 11021 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11022 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11023 }; 11024 11025 struct mlx5_ifc_modify_flow_table_out_bits { 11026 u8 status[0x8]; 11027 u8 reserved_at_8[0x18]; 11028 11029 u8 syndrome[0x20]; 11030 11031 u8 reserved_at_40[0x40]; 11032 }; 11033 11034 struct mlx5_ifc_modify_flow_table_in_bits { 11035 u8 opcode[0x10]; 11036 u8 reserved_at_10[0x10]; 11037 11038 u8 reserved_at_20[0x10]; 11039 u8 op_mod[0x10]; 11040 11041 u8 other_vport[0x1]; 11042 u8 reserved_at_41[0xf]; 11043 u8 vport_number[0x10]; 11044 11045 u8 reserved_at_60[0x10]; 11046 u8 modify_field_select[0x10]; 11047 11048 u8 table_type[0x8]; 11049 u8 reserved_at_88[0x18]; 11050 11051 u8 reserved_at_a0[0x8]; 11052 u8 table_id[0x18]; 11053 11054 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11055 }; 11056 11057 struct mlx5_ifc_ets_tcn_config_reg_bits { 11058 u8 g[0x1]; 11059 u8 b[0x1]; 11060 u8 r[0x1]; 11061 u8 reserved_at_3[0x9]; 11062 u8 group[0x4]; 11063 u8 reserved_at_10[0x9]; 11064 u8 bw_allocation[0x7]; 11065 11066 u8 reserved_at_20[0xc]; 11067 u8 max_bw_units[0x4]; 11068 u8 reserved_at_30[0x8]; 11069 u8 max_bw_value[0x8]; 11070 }; 11071 11072 struct mlx5_ifc_ets_global_config_reg_bits { 11073 u8 reserved_at_0[0x2]; 11074 u8 r[0x1]; 11075 u8 reserved_at_3[0x1d]; 11076 11077 u8 reserved_at_20[0xc]; 11078 u8 max_bw_units[0x4]; 11079 u8 reserved_at_30[0x8]; 11080 u8 max_bw_value[0x8]; 11081 }; 11082 11083 struct mlx5_ifc_qetc_reg_bits { 11084 u8 reserved_at_0[0x8]; 11085 u8 port_number[0x8]; 11086 u8 reserved_at_10[0x30]; 11087 11088 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11089 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11090 }; 11091 11092 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11093 u8 e[0x1]; 11094 u8 reserved_at_01[0x0b]; 11095 u8 prio[0x04]; 11096 }; 11097 11098 struct mlx5_ifc_qpdpm_reg_bits { 11099 u8 reserved_at_0[0x8]; 11100 u8 local_port[0x8]; 11101 u8 reserved_at_10[0x10]; 11102 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11103 }; 11104 11105 struct mlx5_ifc_qpts_reg_bits { 11106 u8 reserved_at_0[0x8]; 11107 u8 local_port[0x8]; 11108 u8 reserved_at_10[0x2d]; 11109 u8 trust_state[0x3]; 11110 }; 11111 11112 struct mlx5_ifc_pptb_reg_bits { 11113 u8 reserved_at_0[0x2]; 11114 u8 mm[0x2]; 11115 u8 reserved_at_4[0x4]; 11116 u8 local_port[0x8]; 11117 u8 reserved_at_10[0x6]; 11118 u8 cm[0x1]; 11119 u8 um[0x1]; 11120 u8 pm[0x8]; 11121 11122 u8 prio_x_buff[0x20]; 11123 11124 u8 pm_msb[0x8]; 11125 u8 reserved_at_48[0x10]; 11126 u8 ctrl_buff[0x4]; 11127 u8 untagged_buff[0x4]; 11128 }; 11129 11130 struct mlx5_ifc_sbcam_reg_bits { 11131 u8 reserved_at_0[0x8]; 11132 u8 feature_group[0x8]; 11133 u8 reserved_at_10[0x8]; 11134 u8 access_reg_group[0x8]; 11135 11136 u8 reserved_at_20[0x20]; 11137 11138 u8 sb_access_reg_cap_mask[4][0x20]; 11139 11140 u8 reserved_at_c0[0x80]; 11141 11142 u8 sb_feature_cap_mask[4][0x20]; 11143 11144 u8 reserved_at_1c0[0x40]; 11145 11146 u8 cap_total_buffer_size[0x20]; 11147 11148 u8 cap_cell_size[0x10]; 11149 u8 cap_max_pg_buffers[0x8]; 11150 u8 cap_num_pool_supported[0x8]; 11151 11152 u8 reserved_at_240[0x8]; 11153 u8 cap_sbsr_stat_size[0x8]; 11154 u8 cap_max_tclass_data[0x8]; 11155 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11156 }; 11157 11158 struct mlx5_ifc_pbmc_reg_bits { 11159 u8 reserved_at_0[0x8]; 11160 u8 local_port[0x8]; 11161 u8 reserved_at_10[0x10]; 11162 11163 u8 xoff_timer_value[0x10]; 11164 u8 xoff_refresh[0x10]; 11165 11166 u8 reserved_at_40[0x9]; 11167 u8 fullness_threshold[0x7]; 11168 u8 port_buffer_size[0x10]; 11169 11170 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11171 11172 u8 reserved_at_2e0[0x80]; 11173 }; 11174 11175 struct mlx5_ifc_sbpr_reg_bits { 11176 u8 desc[0x1]; 11177 u8 snap[0x1]; 11178 u8 reserved_at_2[0x4]; 11179 u8 dir[0x2]; 11180 u8 reserved_at_8[0x14]; 11181 u8 pool[0x4]; 11182 11183 u8 infi_size[0x1]; 11184 u8 reserved_at_21[0x7]; 11185 u8 size[0x18]; 11186 11187 u8 reserved_at_40[0x1c]; 11188 u8 mode[0x4]; 11189 11190 u8 reserved_at_60[0x8]; 11191 u8 buff_occupancy[0x18]; 11192 11193 u8 clr[0x1]; 11194 u8 reserved_at_81[0x7]; 11195 u8 max_buff_occupancy[0x18]; 11196 11197 u8 reserved_at_a0[0x8]; 11198 u8 ext_buff_occupancy[0x18]; 11199 }; 11200 11201 struct mlx5_ifc_sbcm_reg_bits { 11202 u8 desc[0x1]; 11203 u8 snap[0x1]; 11204 u8 reserved_at_2[0x6]; 11205 u8 local_port[0x8]; 11206 u8 pnat[0x2]; 11207 u8 pg_buff[0x6]; 11208 u8 reserved_at_18[0x6]; 11209 u8 dir[0x2]; 11210 11211 u8 reserved_at_20[0x1f]; 11212 u8 exc[0x1]; 11213 11214 u8 reserved_at_40[0x40]; 11215 11216 u8 reserved_at_80[0x8]; 11217 u8 buff_occupancy[0x18]; 11218 11219 u8 clr[0x1]; 11220 u8 reserved_at_a1[0x7]; 11221 u8 max_buff_occupancy[0x18]; 11222 11223 u8 reserved_at_c0[0x8]; 11224 u8 min_buff[0x18]; 11225 11226 u8 infi_max[0x1]; 11227 u8 reserved_at_e1[0x7]; 11228 u8 max_buff[0x18]; 11229 11230 u8 reserved_at_100[0x20]; 11231 11232 u8 reserved_at_120[0x1c]; 11233 u8 pool[0x4]; 11234 }; 11235 11236 struct mlx5_ifc_qtct_reg_bits { 11237 u8 reserved_at_0[0x8]; 11238 u8 port_number[0x8]; 11239 u8 reserved_at_10[0xd]; 11240 u8 prio[0x3]; 11241 11242 u8 reserved_at_20[0x1d]; 11243 u8 tclass[0x3]; 11244 }; 11245 11246 struct mlx5_ifc_mcia_reg_bits { 11247 u8 l[0x1]; 11248 u8 reserved_at_1[0x7]; 11249 u8 module[0x8]; 11250 u8 reserved_at_10[0x8]; 11251 u8 status[0x8]; 11252 11253 u8 i2c_device_address[0x8]; 11254 u8 page_number[0x8]; 11255 u8 device_address[0x10]; 11256 11257 u8 reserved_at_40[0x10]; 11258 u8 size[0x10]; 11259 11260 u8 reserved_at_60[0x20]; 11261 11262 u8 dword_0[0x20]; 11263 u8 dword_1[0x20]; 11264 u8 dword_2[0x20]; 11265 u8 dword_3[0x20]; 11266 u8 dword_4[0x20]; 11267 u8 dword_5[0x20]; 11268 u8 dword_6[0x20]; 11269 u8 dword_7[0x20]; 11270 u8 dword_8[0x20]; 11271 u8 dword_9[0x20]; 11272 u8 dword_10[0x20]; 11273 u8 dword_11[0x20]; 11274 }; 11275 11276 struct mlx5_ifc_dcbx_param_bits { 11277 u8 dcbx_cee_cap[0x1]; 11278 u8 dcbx_ieee_cap[0x1]; 11279 u8 dcbx_standby_cap[0x1]; 11280 u8 reserved_at_3[0x5]; 11281 u8 port_number[0x8]; 11282 u8 reserved_at_10[0xa]; 11283 u8 max_application_table_size[6]; 11284 u8 reserved_at_20[0x15]; 11285 u8 version_oper[0x3]; 11286 u8 reserved_at_38[5]; 11287 u8 version_admin[0x3]; 11288 u8 willing_admin[0x1]; 11289 u8 reserved_at_41[0x3]; 11290 u8 pfc_cap_oper[0x4]; 11291 u8 reserved_at_48[0x4]; 11292 u8 pfc_cap_admin[0x4]; 11293 u8 reserved_at_50[0x4]; 11294 u8 num_of_tc_oper[0x4]; 11295 u8 reserved_at_58[0x4]; 11296 u8 num_of_tc_admin[0x4]; 11297 u8 remote_willing[0x1]; 11298 u8 reserved_at_61[3]; 11299 u8 remote_pfc_cap[4]; 11300 u8 reserved_at_68[0x14]; 11301 u8 remote_num_of_tc[0x4]; 11302 u8 reserved_at_80[0x18]; 11303 u8 error[0x8]; 11304 u8 reserved_at_a0[0x160]; 11305 }; 11306 11307 enum { 11308 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11309 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11310 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11311 }; 11312 11313 struct mlx5_ifc_lagc_bits { 11314 u8 fdb_selection_mode[0x1]; 11315 u8 reserved_at_1[0x14]; 11316 u8 port_select_mode[0x3]; 11317 u8 reserved_at_18[0x5]; 11318 u8 lag_state[0x3]; 11319 11320 u8 reserved_at_20[0xc]; 11321 u8 active_port[0x4]; 11322 u8 reserved_at_30[0x4]; 11323 u8 tx_remap_affinity_2[0x4]; 11324 u8 reserved_at_38[0x4]; 11325 u8 tx_remap_affinity_1[0x4]; 11326 }; 11327 11328 struct mlx5_ifc_create_lag_out_bits { 11329 u8 status[0x8]; 11330 u8 reserved_at_8[0x18]; 11331 11332 u8 syndrome[0x20]; 11333 11334 u8 reserved_at_40[0x40]; 11335 }; 11336 11337 struct mlx5_ifc_create_lag_in_bits { 11338 u8 opcode[0x10]; 11339 u8 reserved_at_10[0x10]; 11340 11341 u8 reserved_at_20[0x10]; 11342 u8 op_mod[0x10]; 11343 11344 struct mlx5_ifc_lagc_bits ctx; 11345 }; 11346 11347 struct mlx5_ifc_modify_lag_out_bits { 11348 u8 status[0x8]; 11349 u8 reserved_at_8[0x18]; 11350 11351 u8 syndrome[0x20]; 11352 11353 u8 reserved_at_40[0x40]; 11354 }; 11355 11356 struct mlx5_ifc_modify_lag_in_bits { 11357 u8 opcode[0x10]; 11358 u8 reserved_at_10[0x10]; 11359 11360 u8 reserved_at_20[0x10]; 11361 u8 op_mod[0x10]; 11362 11363 u8 reserved_at_40[0x20]; 11364 u8 field_select[0x20]; 11365 11366 struct mlx5_ifc_lagc_bits ctx; 11367 }; 11368 11369 struct mlx5_ifc_query_lag_out_bits { 11370 u8 status[0x8]; 11371 u8 reserved_at_8[0x18]; 11372 11373 u8 syndrome[0x20]; 11374 11375 struct mlx5_ifc_lagc_bits ctx; 11376 }; 11377 11378 struct mlx5_ifc_query_lag_in_bits { 11379 u8 opcode[0x10]; 11380 u8 reserved_at_10[0x10]; 11381 11382 u8 reserved_at_20[0x10]; 11383 u8 op_mod[0x10]; 11384 11385 u8 reserved_at_40[0x40]; 11386 }; 11387 11388 struct mlx5_ifc_destroy_lag_out_bits { 11389 u8 status[0x8]; 11390 u8 reserved_at_8[0x18]; 11391 11392 u8 syndrome[0x20]; 11393 11394 u8 reserved_at_40[0x40]; 11395 }; 11396 11397 struct mlx5_ifc_destroy_lag_in_bits { 11398 u8 opcode[0x10]; 11399 u8 reserved_at_10[0x10]; 11400 11401 u8 reserved_at_20[0x10]; 11402 u8 op_mod[0x10]; 11403 11404 u8 reserved_at_40[0x40]; 11405 }; 11406 11407 struct mlx5_ifc_create_vport_lag_out_bits { 11408 u8 status[0x8]; 11409 u8 reserved_at_8[0x18]; 11410 11411 u8 syndrome[0x20]; 11412 11413 u8 reserved_at_40[0x40]; 11414 }; 11415 11416 struct mlx5_ifc_create_vport_lag_in_bits { 11417 u8 opcode[0x10]; 11418 u8 reserved_at_10[0x10]; 11419 11420 u8 reserved_at_20[0x10]; 11421 u8 op_mod[0x10]; 11422 11423 u8 reserved_at_40[0x40]; 11424 }; 11425 11426 struct mlx5_ifc_destroy_vport_lag_out_bits { 11427 u8 status[0x8]; 11428 u8 reserved_at_8[0x18]; 11429 11430 u8 syndrome[0x20]; 11431 11432 u8 reserved_at_40[0x40]; 11433 }; 11434 11435 struct mlx5_ifc_destroy_vport_lag_in_bits { 11436 u8 opcode[0x10]; 11437 u8 reserved_at_10[0x10]; 11438 11439 u8 reserved_at_20[0x10]; 11440 u8 op_mod[0x10]; 11441 11442 u8 reserved_at_40[0x40]; 11443 }; 11444 11445 enum { 11446 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11447 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11448 }; 11449 11450 struct mlx5_ifc_modify_memic_in_bits { 11451 u8 opcode[0x10]; 11452 u8 uid[0x10]; 11453 11454 u8 reserved_at_20[0x10]; 11455 u8 op_mod[0x10]; 11456 11457 u8 reserved_at_40[0x20]; 11458 11459 u8 reserved_at_60[0x18]; 11460 u8 memic_operation_type[0x8]; 11461 11462 u8 memic_start_addr[0x40]; 11463 11464 u8 reserved_at_c0[0x140]; 11465 }; 11466 11467 struct mlx5_ifc_modify_memic_out_bits { 11468 u8 status[0x8]; 11469 u8 reserved_at_8[0x18]; 11470 11471 u8 syndrome[0x20]; 11472 11473 u8 reserved_at_40[0x40]; 11474 11475 u8 memic_operation_addr[0x40]; 11476 11477 u8 reserved_at_c0[0x140]; 11478 }; 11479 11480 struct mlx5_ifc_alloc_memic_in_bits { 11481 u8 opcode[0x10]; 11482 u8 reserved_at_10[0x10]; 11483 11484 u8 reserved_at_20[0x10]; 11485 u8 op_mod[0x10]; 11486 11487 u8 reserved_at_30[0x20]; 11488 11489 u8 reserved_at_40[0x18]; 11490 u8 log_memic_addr_alignment[0x8]; 11491 11492 u8 range_start_addr[0x40]; 11493 11494 u8 range_size[0x20]; 11495 11496 u8 memic_size[0x20]; 11497 }; 11498 11499 struct mlx5_ifc_alloc_memic_out_bits { 11500 u8 status[0x8]; 11501 u8 reserved_at_8[0x18]; 11502 11503 u8 syndrome[0x20]; 11504 11505 u8 memic_start_addr[0x40]; 11506 }; 11507 11508 struct mlx5_ifc_dealloc_memic_in_bits { 11509 u8 opcode[0x10]; 11510 u8 reserved_at_10[0x10]; 11511 11512 u8 reserved_at_20[0x10]; 11513 u8 op_mod[0x10]; 11514 11515 u8 reserved_at_40[0x40]; 11516 11517 u8 memic_start_addr[0x40]; 11518 11519 u8 memic_size[0x20]; 11520 11521 u8 reserved_at_e0[0x20]; 11522 }; 11523 11524 struct mlx5_ifc_dealloc_memic_out_bits { 11525 u8 status[0x8]; 11526 u8 reserved_at_8[0x18]; 11527 11528 u8 syndrome[0x20]; 11529 11530 u8 reserved_at_40[0x40]; 11531 }; 11532 11533 struct mlx5_ifc_umem_bits { 11534 u8 reserved_at_0[0x80]; 11535 11536 u8 ats[0x1]; 11537 u8 reserved_at_81[0x1a]; 11538 u8 log_page_size[0x5]; 11539 11540 u8 page_offset[0x20]; 11541 11542 u8 num_of_mtt[0x40]; 11543 11544 struct mlx5_ifc_mtt_bits mtt[]; 11545 }; 11546 11547 struct mlx5_ifc_uctx_bits { 11548 u8 cap[0x20]; 11549 11550 u8 reserved_at_20[0x160]; 11551 }; 11552 11553 struct mlx5_ifc_sw_icm_bits { 11554 u8 modify_field_select[0x40]; 11555 11556 u8 reserved_at_40[0x18]; 11557 u8 log_sw_icm_size[0x8]; 11558 11559 u8 reserved_at_60[0x20]; 11560 11561 u8 sw_icm_start_addr[0x40]; 11562 11563 u8 reserved_at_c0[0x140]; 11564 }; 11565 11566 struct mlx5_ifc_geneve_tlv_option_bits { 11567 u8 modify_field_select[0x40]; 11568 11569 u8 reserved_at_40[0x18]; 11570 u8 geneve_option_fte_index[0x8]; 11571 11572 u8 option_class[0x10]; 11573 u8 option_type[0x8]; 11574 u8 reserved_at_78[0x3]; 11575 u8 option_data_length[0x5]; 11576 11577 u8 reserved_at_80[0x180]; 11578 }; 11579 11580 struct mlx5_ifc_create_umem_in_bits { 11581 u8 opcode[0x10]; 11582 u8 uid[0x10]; 11583 11584 u8 reserved_at_20[0x10]; 11585 u8 op_mod[0x10]; 11586 11587 u8 reserved_at_40[0x40]; 11588 11589 struct mlx5_ifc_umem_bits umem; 11590 }; 11591 11592 struct mlx5_ifc_create_umem_out_bits { 11593 u8 status[0x8]; 11594 u8 reserved_at_8[0x18]; 11595 11596 u8 syndrome[0x20]; 11597 11598 u8 reserved_at_40[0x8]; 11599 u8 umem_id[0x18]; 11600 11601 u8 reserved_at_60[0x20]; 11602 }; 11603 11604 struct mlx5_ifc_destroy_umem_in_bits { 11605 u8 opcode[0x10]; 11606 u8 uid[0x10]; 11607 11608 u8 reserved_at_20[0x10]; 11609 u8 op_mod[0x10]; 11610 11611 u8 reserved_at_40[0x8]; 11612 u8 umem_id[0x18]; 11613 11614 u8 reserved_at_60[0x20]; 11615 }; 11616 11617 struct mlx5_ifc_destroy_umem_out_bits { 11618 u8 status[0x8]; 11619 u8 reserved_at_8[0x18]; 11620 11621 u8 syndrome[0x20]; 11622 11623 u8 reserved_at_40[0x40]; 11624 }; 11625 11626 struct mlx5_ifc_create_uctx_in_bits { 11627 u8 opcode[0x10]; 11628 u8 reserved_at_10[0x10]; 11629 11630 u8 reserved_at_20[0x10]; 11631 u8 op_mod[0x10]; 11632 11633 u8 reserved_at_40[0x40]; 11634 11635 struct mlx5_ifc_uctx_bits uctx; 11636 }; 11637 11638 struct mlx5_ifc_create_uctx_out_bits { 11639 u8 status[0x8]; 11640 u8 reserved_at_8[0x18]; 11641 11642 u8 syndrome[0x20]; 11643 11644 u8 reserved_at_40[0x10]; 11645 u8 uid[0x10]; 11646 11647 u8 reserved_at_60[0x20]; 11648 }; 11649 11650 struct mlx5_ifc_destroy_uctx_in_bits { 11651 u8 opcode[0x10]; 11652 u8 reserved_at_10[0x10]; 11653 11654 u8 reserved_at_20[0x10]; 11655 u8 op_mod[0x10]; 11656 11657 u8 reserved_at_40[0x10]; 11658 u8 uid[0x10]; 11659 11660 u8 reserved_at_60[0x20]; 11661 }; 11662 11663 struct mlx5_ifc_destroy_uctx_out_bits { 11664 u8 status[0x8]; 11665 u8 reserved_at_8[0x18]; 11666 11667 u8 syndrome[0x20]; 11668 11669 u8 reserved_at_40[0x40]; 11670 }; 11671 11672 struct mlx5_ifc_create_sw_icm_in_bits { 11673 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11674 struct mlx5_ifc_sw_icm_bits sw_icm; 11675 }; 11676 11677 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11678 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11679 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11680 }; 11681 11682 struct mlx5_ifc_mtrc_string_db_param_bits { 11683 u8 string_db_base_address[0x20]; 11684 11685 u8 reserved_at_20[0x8]; 11686 u8 string_db_size[0x18]; 11687 }; 11688 11689 struct mlx5_ifc_mtrc_cap_bits { 11690 u8 trace_owner[0x1]; 11691 u8 trace_to_memory[0x1]; 11692 u8 reserved_at_2[0x4]; 11693 u8 trc_ver[0x2]; 11694 u8 reserved_at_8[0x14]; 11695 u8 num_string_db[0x4]; 11696 11697 u8 first_string_trace[0x8]; 11698 u8 num_string_trace[0x8]; 11699 u8 reserved_at_30[0x28]; 11700 11701 u8 log_max_trace_buffer_size[0x8]; 11702 11703 u8 reserved_at_60[0x20]; 11704 11705 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11706 11707 u8 reserved_at_280[0x180]; 11708 }; 11709 11710 struct mlx5_ifc_mtrc_conf_bits { 11711 u8 reserved_at_0[0x1c]; 11712 u8 trace_mode[0x4]; 11713 u8 reserved_at_20[0x18]; 11714 u8 log_trace_buffer_size[0x8]; 11715 u8 trace_mkey[0x20]; 11716 u8 reserved_at_60[0x3a0]; 11717 }; 11718 11719 struct mlx5_ifc_mtrc_stdb_bits { 11720 u8 string_db_index[0x4]; 11721 u8 reserved_at_4[0x4]; 11722 u8 read_size[0x18]; 11723 u8 start_offset[0x20]; 11724 u8 string_db_data[]; 11725 }; 11726 11727 struct mlx5_ifc_mtrc_ctrl_bits { 11728 u8 trace_status[0x2]; 11729 u8 reserved_at_2[0x2]; 11730 u8 arm_event[0x1]; 11731 u8 reserved_at_5[0xb]; 11732 u8 modify_field_select[0x10]; 11733 u8 reserved_at_20[0x2b]; 11734 u8 current_timestamp52_32[0x15]; 11735 u8 current_timestamp31_0[0x20]; 11736 u8 reserved_at_80[0x180]; 11737 }; 11738 11739 struct mlx5_ifc_host_params_context_bits { 11740 u8 host_number[0x8]; 11741 u8 reserved_at_8[0x7]; 11742 u8 host_pf_disabled[0x1]; 11743 u8 host_num_of_vfs[0x10]; 11744 11745 u8 host_total_vfs[0x10]; 11746 u8 host_pci_bus[0x10]; 11747 11748 u8 reserved_at_40[0x10]; 11749 u8 host_pci_device[0x10]; 11750 11751 u8 reserved_at_60[0x10]; 11752 u8 host_pci_function[0x10]; 11753 11754 u8 reserved_at_80[0x180]; 11755 }; 11756 11757 struct mlx5_ifc_query_esw_functions_in_bits { 11758 u8 opcode[0x10]; 11759 u8 reserved_at_10[0x10]; 11760 11761 u8 reserved_at_20[0x10]; 11762 u8 op_mod[0x10]; 11763 11764 u8 reserved_at_40[0x40]; 11765 }; 11766 11767 struct mlx5_ifc_query_esw_functions_out_bits { 11768 u8 status[0x8]; 11769 u8 reserved_at_8[0x18]; 11770 11771 u8 syndrome[0x20]; 11772 11773 u8 reserved_at_40[0x40]; 11774 11775 struct mlx5_ifc_host_params_context_bits host_params_context; 11776 11777 u8 reserved_at_280[0x180]; 11778 u8 host_sf_enable[][0x40]; 11779 }; 11780 11781 struct mlx5_ifc_sf_partition_bits { 11782 u8 reserved_at_0[0x10]; 11783 u8 log_num_sf[0x8]; 11784 u8 log_sf_bar_size[0x8]; 11785 }; 11786 11787 struct mlx5_ifc_query_sf_partitions_out_bits { 11788 u8 status[0x8]; 11789 u8 reserved_at_8[0x18]; 11790 11791 u8 syndrome[0x20]; 11792 11793 u8 reserved_at_40[0x18]; 11794 u8 num_sf_partitions[0x8]; 11795 11796 u8 reserved_at_60[0x20]; 11797 11798 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11799 }; 11800 11801 struct mlx5_ifc_query_sf_partitions_in_bits { 11802 u8 opcode[0x10]; 11803 u8 reserved_at_10[0x10]; 11804 11805 u8 reserved_at_20[0x10]; 11806 u8 op_mod[0x10]; 11807 11808 u8 reserved_at_40[0x40]; 11809 }; 11810 11811 struct mlx5_ifc_dealloc_sf_out_bits { 11812 u8 status[0x8]; 11813 u8 reserved_at_8[0x18]; 11814 11815 u8 syndrome[0x20]; 11816 11817 u8 reserved_at_40[0x40]; 11818 }; 11819 11820 struct mlx5_ifc_dealloc_sf_in_bits { 11821 u8 opcode[0x10]; 11822 u8 reserved_at_10[0x10]; 11823 11824 u8 reserved_at_20[0x10]; 11825 u8 op_mod[0x10]; 11826 11827 u8 reserved_at_40[0x10]; 11828 u8 function_id[0x10]; 11829 11830 u8 reserved_at_60[0x20]; 11831 }; 11832 11833 struct mlx5_ifc_alloc_sf_out_bits { 11834 u8 status[0x8]; 11835 u8 reserved_at_8[0x18]; 11836 11837 u8 syndrome[0x20]; 11838 11839 u8 reserved_at_40[0x40]; 11840 }; 11841 11842 struct mlx5_ifc_alloc_sf_in_bits { 11843 u8 opcode[0x10]; 11844 u8 reserved_at_10[0x10]; 11845 11846 u8 reserved_at_20[0x10]; 11847 u8 op_mod[0x10]; 11848 11849 u8 reserved_at_40[0x10]; 11850 u8 function_id[0x10]; 11851 11852 u8 reserved_at_60[0x20]; 11853 }; 11854 11855 struct mlx5_ifc_affiliated_event_header_bits { 11856 u8 reserved_at_0[0x10]; 11857 u8 obj_type[0x10]; 11858 11859 u8 obj_id[0x20]; 11860 }; 11861 11862 enum { 11863 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11864 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11865 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11866 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11867 }; 11868 11869 enum { 11870 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11871 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11872 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11873 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11874 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11875 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11876 }; 11877 11878 enum { 11879 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11880 }; 11881 11882 enum { 11883 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11884 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11885 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11886 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11887 }; 11888 11889 enum { 11890 MLX5_IPSEC_ASO_MODE = 0x0, 11891 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11892 MLX5_IPSEC_ASO_INC_SN = 0x2, 11893 }; 11894 11895 struct mlx5_ifc_ipsec_aso_bits { 11896 u8 valid[0x1]; 11897 u8 reserved_at_201[0x1]; 11898 u8 mode[0x2]; 11899 u8 window_sz[0x2]; 11900 u8 soft_lft_arm[0x1]; 11901 u8 hard_lft_arm[0x1]; 11902 u8 remove_flow_enable[0x1]; 11903 u8 esn_event_arm[0x1]; 11904 u8 reserved_at_20a[0x16]; 11905 11906 u8 remove_flow_pkt_cnt[0x20]; 11907 11908 u8 remove_flow_soft_lft[0x20]; 11909 11910 u8 reserved_at_260[0x80]; 11911 11912 u8 mode_parameter[0x20]; 11913 11914 u8 replay_protection_window[0x100]; 11915 }; 11916 11917 struct mlx5_ifc_ipsec_obj_bits { 11918 u8 modify_field_select[0x40]; 11919 u8 full_offload[0x1]; 11920 u8 reserved_at_41[0x1]; 11921 u8 esn_en[0x1]; 11922 u8 esn_overlap[0x1]; 11923 u8 reserved_at_44[0x2]; 11924 u8 icv_length[0x2]; 11925 u8 reserved_at_48[0x4]; 11926 u8 aso_return_reg[0x4]; 11927 u8 reserved_at_50[0x10]; 11928 11929 u8 esn_msb[0x20]; 11930 11931 u8 reserved_at_80[0x8]; 11932 u8 dekn[0x18]; 11933 11934 u8 salt[0x20]; 11935 11936 u8 implicit_iv[0x40]; 11937 11938 u8 reserved_at_100[0x8]; 11939 u8 ipsec_aso_access_pd[0x18]; 11940 u8 reserved_at_120[0xe0]; 11941 11942 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11943 }; 11944 11945 struct mlx5_ifc_create_ipsec_obj_in_bits { 11946 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11947 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11948 }; 11949 11950 enum { 11951 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11952 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11953 }; 11954 11955 struct mlx5_ifc_query_ipsec_obj_out_bits { 11956 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11957 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11958 }; 11959 11960 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11961 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11962 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11963 }; 11964 11965 enum { 11966 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11967 }; 11968 11969 enum { 11970 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11971 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11972 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11973 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11974 }; 11975 11976 #define MLX5_MACSEC_ASO_INC_SN 0x2 11977 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11978 11979 struct mlx5_ifc_macsec_aso_bits { 11980 u8 valid[0x1]; 11981 u8 reserved_at_1[0x1]; 11982 u8 mode[0x2]; 11983 u8 window_size[0x2]; 11984 u8 soft_lifetime_arm[0x1]; 11985 u8 hard_lifetime_arm[0x1]; 11986 u8 remove_flow_enable[0x1]; 11987 u8 epn_event_arm[0x1]; 11988 u8 reserved_at_a[0x16]; 11989 11990 u8 remove_flow_packet_count[0x20]; 11991 11992 u8 remove_flow_soft_lifetime[0x20]; 11993 11994 u8 reserved_at_60[0x80]; 11995 11996 u8 mode_parameter[0x20]; 11997 11998 u8 replay_protection_window[8][0x20]; 11999 }; 12000 12001 struct mlx5_ifc_macsec_offload_obj_bits { 12002 u8 modify_field_select[0x40]; 12003 12004 u8 confidentiality_en[0x1]; 12005 u8 reserved_at_41[0x1]; 12006 u8 epn_en[0x1]; 12007 u8 epn_overlap[0x1]; 12008 u8 reserved_at_44[0x2]; 12009 u8 confidentiality_offset[0x2]; 12010 u8 reserved_at_48[0x4]; 12011 u8 aso_return_reg[0x4]; 12012 u8 reserved_at_50[0x10]; 12013 12014 u8 epn_msb[0x20]; 12015 12016 u8 reserved_at_80[0x8]; 12017 u8 dekn[0x18]; 12018 12019 u8 reserved_at_a0[0x20]; 12020 12021 u8 sci[0x40]; 12022 12023 u8 reserved_at_100[0x8]; 12024 u8 macsec_aso_access_pd[0x18]; 12025 12026 u8 reserved_at_120[0x60]; 12027 12028 u8 salt[3][0x20]; 12029 12030 u8 reserved_at_1e0[0x20]; 12031 12032 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12033 }; 12034 12035 struct mlx5_ifc_create_macsec_obj_in_bits { 12036 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12037 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12038 }; 12039 12040 struct mlx5_ifc_modify_macsec_obj_in_bits { 12041 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12042 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12043 }; 12044 12045 enum { 12046 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12047 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12048 }; 12049 12050 struct mlx5_ifc_query_macsec_obj_out_bits { 12051 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12052 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12053 }; 12054 12055 struct mlx5_ifc_wrapped_dek_bits { 12056 u8 gcm_iv[0x60]; 12057 12058 u8 reserved_at_60[0x20]; 12059 12060 u8 const0[0x1]; 12061 u8 key_size[0x1]; 12062 u8 reserved_at_82[0x2]; 12063 u8 key2_invalid[0x1]; 12064 u8 reserved_at_85[0x3]; 12065 u8 pd[0x18]; 12066 12067 u8 key_purpose[0x5]; 12068 u8 reserved_at_a5[0x13]; 12069 u8 kek_id[0x8]; 12070 12071 u8 reserved_at_c0[0x40]; 12072 12073 u8 key1[0x8][0x20]; 12074 12075 u8 key2[0x8][0x20]; 12076 12077 u8 reserved_at_300[0x40]; 12078 12079 u8 const1[0x1]; 12080 u8 reserved_at_341[0x1f]; 12081 12082 u8 reserved_at_360[0x20]; 12083 12084 u8 auth_tag[0x80]; 12085 }; 12086 12087 struct mlx5_ifc_encryption_key_obj_bits { 12088 u8 modify_field_select[0x40]; 12089 12090 u8 state[0x8]; 12091 u8 sw_wrapped[0x1]; 12092 u8 reserved_at_49[0xb]; 12093 u8 key_size[0x4]; 12094 u8 reserved_at_58[0x4]; 12095 u8 key_purpose[0x4]; 12096 12097 u8 reserved_at_60[0x8]; 12098 u8 pd[0x18]; 12099 12100 u8 reserved_at_80[0x100]; 12101 12102 u8 opaque[0x40]; 12103 12104 u8 reserved_at_1c0[0x40]; 12105 12106 u8 key[8][0x80]; 12107 12108 u8 sw_wrapped_dek[8][0x80]; 12109 12110 u8 reserved_at_a00[0x600]; 12111 }; 12112 12113 struct mlx5_ifc_create_encryption_key_in_bits { 12114 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12115 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12116 }; 12117 12118 struct mlx5_ifc_modify_encryption_key_in_bits { 12119 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12120 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12121 }; 12122 12123 enum { 12124 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12125 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12126 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12127 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12128 }; 12129 12130 struct mlx5_ifc_flow_meter_parameters_bits { 12131 u8 valid[0x1]; 12132 u8 bucket_overflow[0x1]; 12133 u8 start_color[0x2]; 12134 u8 both_buckets_on_green[0x1]; 12135 u8 reserved_at_5[0x1]; 12136 u8 meter_mode[0x2]; 12137 u8 reserved_at_8[0x18]; 12138 12139 u8 reserved_at_20[0x20]; 12140 12141 u8 reserved_at_40[0x3]; 12142 u8 cbs_exponent[0x5]; 12143 u8 cbs_mantissa[0x8]; 12144 u8 reserved_at_50[0x3]; 12145 u8 cir_exponent[0x5]; 12146 u8 cir_mantissa[0x8]; 12147 12148 u8 reserved_at_60[0x20]; 12149 12150 u8 reserved_at_80[0x3]; 12151 u8 ebs_exponent[0x5]; 12152 u8 ebs_mantissa[0x8]; 12153 u8 reserved_at_90[0x3]; 12154 u8 eir_exponent[0x5]; 12155 u8 eir_mantissa[0x8]; 12156 12157 u8 reserved_at_a0[0x60]; 12158 }; 12159 12160 struct mlx5_ifc_flow_meter_aso_obj_bits { 12161 u8 modify_field_select[0x40]; 12162 12163 u8 reserved_at_40[0x40]; 12164 12165 u8 reserved_at_80[0x8]; 12166 u8 meter_aso_access_pd[0x18]; 12167 12168 u8 reserved_at_a0[0x160]; 12169 12170 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12171 }; 12172 12173 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12174 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12175 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12176 }; 12177 12178 struct mlx5_ifc_int_kek_obj_bits { 12179 u8 modify_field_select[0x40]; 12180 12181 u8 state[0x8]; 12182 u8 auto_gen[0x1]; 12183 u8 reserved_at_49[0xb]; 12184 u8 key_size[0x4]; 12185 u8 reserved_at_58[0x8]; 12186 12187 u8 reserved_at_60[0x8]; 12188 u8 pd[0x18]; 12189 12190 u8 reserved_at_80[0x180]; 12191 u8 key[8][0x80]; 12192 12193 u8 reserved_at_600[0x200]; 12194 }; 12195 12196 struct mlx5_ifc_create_int_kek_obj_in_bits { 12197 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12198 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12199 }; 12200 12201 struct mlx5_ifc_create_int_kek_obj_out_bits { 12202 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12203 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12204 }; 12205 12206 struct mlx5_ifc_sampler_obj_bits { 12207 u8 modify_field_select[0x40]; 12208 12209 u8 table_type[0x8]; 12210 u8 level[0x8]; 12211 u8 reserved_at_50[0xf]; 12212 u8 ignore_flow_level[0x1]; 12213 12214 u8 sample_ratio[0x20]; 12215 12216 u8 reserved_at_80[0x8]; 12217 u8 sample_table_id[0x18]; 12218 12219 u8 reserved_at_a0[0x8]; 12220 u8 default_table_id[0x18]; 12221 12222 u8 sw_steering_icm_address_rx[0x40]; 12223 u8 sw_steering_icm_address_tx[0x40]; 12224 12225 u8 reserved_at_140[0xa0]; 12226 }; 12227 12228 struct mlx5_ifc_create_sampler_obj_in_bits { 12229 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12230 struct mlx5_ifc_sampler_obj_bits sampler_object; 12231 }; 12232 12233 struct mlx5_ifc_query_sampler_obj_out_bits { 12234 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12235 struct mlx5_ifc_sampler_obj_bits sampler_object; 12236 }; 12237 12238 enum { 12239 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12240 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12241 }; 12242 12243 enum { 12244 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12245 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12246 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12247 }; 12248 12249 struct mlx5_ifc_tls_static_params_bits { 12250 u8 const_2[0x2]; 12251 u8 tls_version[0x4]; 12252 u8 const_1[0x2]; 12253 u8 reserved_at_8[0x14]; 12254 u8 encryption_standard[0x4]; 12255 12256 u8 reserved_at_20[0x20]; 12257 12258 u8 initial_record_number[0x40]; 12259 12260 u8 resync_tcp_sn[0x20]; 12261 12262 u8 gcm_iv[0x20]; 12263 12264 u8 implicit_iv[0x40]; 12265 12266 u8 reserved_at_100[0x8]; 12267 u8 dek_index[0x18]; 12268 12269 u8 reserved_at_120[0xe0]; 12270 }; 12271 12272 struct mlx5_ifc_tls_progress_params_bits { 12273 u8 next_record_tcp_sn[0x20]; 12274 12275 u8 hw_resync_tcp_sn[0x20]; 12276 12277 u8 record_tracker_state[0x2]; 12278 u8 auth_state[0x2]; 12279 u8 reserved_at_44[0x4]; 12280 u8 hw_offset_record_number[0x18]; 12281 }; 12282 12283 enum { 12284 MLX5_MTT_PERM_READ = 1 << 0, 12285 MLX5_MTT_PERM_WRITE = 1 << 1, 12286 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12287 }; 12288 12289 enum { 12290 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12291 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12292 }; 12293 12294 struct mlx5_ifc_suspend_vhca_in_bits { 12295 u8 opcode[0x10]; 12296 u8 uid[0x10]; 12297 12298 u8 reserved_at_20[0x10]; 12299 u8 op_mod[0x10]; 12300 12301 u8 reserved_at_40[0x10]; 12302 u8 vhca_id[0x10]; 12303 12304 u8 reserved_at_60[0x20]; 12305 }; 12306 12307 struct mlx5_ifc_suspend_vhca_out_bits { 12308 u8 status[0x8]; 12309 u8 reserved_at_8[0x18]; 12310 12311 u8 syndrome[0x20]; 12312 12313 u8 reserved_at_40[0x40]; 12314 }; 12315 12316 enum { 12317 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12318 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12319 }; 12320 12321 struct mlx5_ifc_resume_vhca_in_bits { 12322 u8 opcode[0x10]; 12323 u8 uid[0x10]; 12324 12325 u8 reserved_at_20[0x10]; 12326 u8 op_mod[0x10]; 12327 12328 u8 reserved_at_40[0x10]; 12329 u8 vhca_id[0x10]; 12330 12331 u8 reserved_at_60[0x20]; 12332 }; 12333 12334 struct mlx5_ifc_resume_vhca_out_bits { 12335 u8 status[0x8]; 12336 u8 reserved_at_8[0x18]; 12337 12338 u8 syndrome[0x20]; 12339 12340 u8 reserved_at_40[0x40]; 12341 }; 12342 12343 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12344 u8 opcode[0x10]; 12345 u8 uid[0x10]; 12346 12347 u8 reserved_at_20[0x10]; 12348 u8 op_mod[0x10]; 12349 12350 u8 incremental[0x1]; 12351 u8 reserved_at_41[0xf]; 12352 u8 vhca_id[0x10]; 12353 12354 u8 reserved_at_60[0x20]; 12355 }; 12356 12357 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12358 u8 status[0x8]; 12359 u8 reserved_at_8[0x18]; 12360 12361 u8 syndrome[0x20]; 12362 12363 u8 reserved_at_40[0x40]; 12364 12365 u8 required_umem_size[0x20]; 12366 12367 u8 reserved_at_a0[0x160]; 12368 }; 12369 12370 struct mlx5_ifc_save_vhca_state_in_bits { 12371 u8 opcode[0x10]; 12372 u8 uid[0x10]; 12373 12374 u8 reserved_at_20[0x10]; 12375 u8 op_mod[0x10]; 12376 12377 u8 incremental[0x1]; 12378 u8 set_track[0x1]; 12379 u8 reserved_at_42[0xe]; 12380 u8 vhca_id[0x10]; 12381 12382 u8 reserved_at_60[0x20]; 12383 12384 u8 va[0x40]; 12385 12386 u8 mkey[0x20]; 12387 12388 u8 size[0x20]; 12389 }; 12390 12391 struct mlx5_ifc_save_vhca_state_out_bits { 12392 u8 status[0x8]; 12393 u8 reserved_at_8[0x18]; 12394 12395 u8 syndrome[0x20]; 12396 12397 u8 actual_image_size[0x20]; 12398 12399 u8 reserved_at_60[0x20]; 12400 }; 12401 12402 struct mlx5_ifc_load_vhca_state_in_bits { 12403 u8 opcode[0x10]; 12404 u8 uid[0x10]; 12405 12406 u8 reserved_at_20[0x10]; 12407 u8 op_mod[0x10]; 12408 12409 u8 reserved_at_40[0x10]; 12410 u8 vhca_id[0x10]; 12411 12412 u8 reserved_at_60[0x20]; 12413 12414 u8 va[0x40]; 12415 12416 u8 mkey[0x20]; 12417 12418 u8 size[0x20]; 12419 }; 12420 12421 struct mlx5_ifc_load_vhca_state_out_bits { 12422 u8 status[0x8]; 12423 u8 reserved_at_8[0x18]; 12424 12425 u8 syndrome[0x20]; 12426 12427 u8 reserved_at_40[0x40]; 12428 }; 12429 12430 struct mlx5_ifc_adv_virtualization_cap_bits { 12431 u8 reserved_at_0[0x3]; 12432 u8 pg_track_log_max_num[0x5]; 12433 u8 pg_track_max_num_range[0x8]; 12434 u8 pg_track_log_min_addr_space[0x8]; 12435 u8 pg_track_log_max_addr_space[0x8]; 12436 12437 u8 reserved_at_20[0x3]; 12438 u8 pg_track_log_min_msg_size[0x5]; 12439 u8 reserved_at_28[0x3]; 12440 u8 pg_track_log_max_msg_size[0x5]; 12441 u8 reserved_at_30[0x3]; 12442 u8 pg_track_log_min_page_size[0x5]; 12443 u8 reserved_at_38[0x3]; 12444 u8 pg_track_log_max_page_size[0x5]; 12445 12446 u8 reserved_at_40[0x7c0]; 12447 }; 12448 12449 struct mlx5_ifc_page_track_report_entry_bits { 12450 u8 dirty_address_high[0x20]; 12451 12452 u8 dirty_address_low[0x20]; 12453 }; 12454 12455 enum { 12456 MLX5_PAGE_TRACK_STATE_TRACKING, 12457 MLX5_PAGE_TRACK_STATE_REPORTING, 12458 MLX5_PAGE_TRACK_STATE_ERROR, 12459 }; 12460 12461 struct mlx5_ifc_page_track_range_bits { 12462 u8 start_address[0x40]; 12463 12464 u8 length[0x40]; 12465 }; 12466 12467 struct mlx5_ifc_page_track_bits { 12468 u8 modify_field_select[0x40]; 12469 12470 u8 reserved_at_40[0x10]; 12471 u8 vhca_id[0x10]; 12472 12473 u8 reserved_at_60[0x20]; 12474 12475 u8 state[0x4]; 12476 u8 track_type[0x4]; 12477 u8 log_addr_space_size[0x8]; 12478 u8 reserved_at_90[0x3]; 12479 u8 log_page_size[0x5]; 12480 u8 reserved_at_98[0x3]; 12481 u8 log_msg_size[0x5]; 12482 12483 u8 reserved_at_a0[0x8]; 12484 u8 reporting_qpn[0x18]; 12485 12486 u8 reserved_at_c0[0x18]; 12487 u8 num_ranges[0x8]; 12488 12489 u8 reserved_at_e0[0x20]; 12490 12491 u8 range_start_address[0x40]; 12492 12493 u8 length[0x40]; 12494 12495 struct mlx5_ifc_page_track_range_bits track_range[0]; 12496 }; 12497 12498 struct mlx5_ifc_create_page_track_obj_in_bits { 12499 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12500 struct mlx5_ifc_page_track_bits obj_context; 12501 }; 12502 12503 struct mlx5_ifc_modify_page_track_obj_in_bits { 12504 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12505 struct mlx5_ifc_page_track_bits obj_context; 12506 }; 12507 12508 #endif /* MLX5_IFC_H */ 12509