1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 92 MLX5_OBJ_TYPE_MKEY = 0xff01, 93 MLX5_OBJ_TYPE_QP = 0xff02, 94 MLX5_OBJ_TYPE_PSV = 0xff03, 95 MLX5_OBJ_TYPE_RMP = 0xff04, 96 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 97 MLX5_OBJ_TYPE_RQ = 0xff06, 98 MLX5_OBJ_TYPE_SQ = 0xff07, 99 MLX5_OBJ_TYPE_TIR = 0xff08, 100 MLX5_OBJ_TYPE_TIS = 0xff09, 101 MLX5_OBJ_TYPE_DCT = 0xff0a, 102 MLX5_OBJ_TYPE_XRQ = 0xff0b, 103 MLX5_OBJ_TYPE_RQT = 0xff0e, 104 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 105 MLX5_OBJ_TYPE_CQ = 0xff10, 106 }; 107 108 enum { 109 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 110 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 111 MLX5_CMD_OP_INIT_HCA = 0x102, 112 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 113 MLX5_CMD_OP_ENABLE_HCA = 0x104, 114 MLX5_CMD_OP_DISABLE_HCA = 0x105, 115 MLX5_CMD_OP_QUERY_PAGES = 0x107, 116 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 117 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 118 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 119 MLX5_CMD_OP_SET_ISSI = 0x10b, 120 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 121 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 122 MLX5_CMD_OP_ALLOC_SF = 0x113, 123 MLX5_CMD_OP_DEALLOC_SF = 0x114, 124 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 125 MLX5_CMD_OP_RESUME_VHCA = 0x116, 126 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 127 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 128 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 source_vhca_port[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 geneve_tlv_option_0_exist[0x1]; 375 u8 reserved_at_42[0x3]; 376 u8 outer_first_mpls_over_udp[0x4]; 377 u8 outer_first_mpls_over_gre[0x4]; 378 u8 inner_first_mpls[0x4]; 379 u8 outer_first_mpls[0x4]; 380 u8 reserved_at_55[0x2]; 381 u8 outer_esp_spi[0x1]; 382 u8 reserved_at_58[0x2]; 383 u8 bth_dst_qp[0x1]; 384 u8 reserved_at_5b[0x5]; 385 386 u8 reserved_at_60[0x18]; 387 u8 metadata_reg_c_7[0x1]; 388 u8 metadata_reg_c_6[0x1]; 389 u8 metadata_reg_c_5[0x1]; 390 u8 metadata_reg_c_4[0x1]; 391 u8 metadata_reg_c_3[0x1]; 392 u8 metadata_reg_c_2[0x1]; 393 u8 metadata_reg_c_1[0x1]; 394 u8 metadata_reg_c_0[0x1]; 395 }; 396 397 struct mlx5_ifc_flow_table_fields_supported_2_bits { 398 u8 reserved_at_0[0xe]; 399 u8 bth_opcode[0x1]; 400 u8 reserved_at_f[0x11]; 401 402 u8 reserved_at_20[0x60]; 403 }; 404 405 struct mlx5_ifc_flow_table_prop_layout_bits { 406 u8 ft_support[0x1]; 407 u8 reserved_at_1[0x1]; 408 u8 flow_counter[0x1]; 409 u8 flow_modify_en[0x1]; 410 u8 modify_root[0x1]; 411 u8 identified_miss_table_mode[0x1]; 412 u8 flow_table_modify[0x1]; 413 u8 reformat[0x1]; 414 u8 decap[0x1]; 415 u8 reserved_at_9[0x1]; 416 u8 pop_vlan[0x1]; 417 u8 push_vlan[0x1]; 418 u8 reserved_at_c[0x1]; 419 u8 pop_vlan_2[0x1]; 420 u8 push_vlan_2[0x1]; 421 u8 reformat_and_vlan_action[0x1]; 422 u8 reserved_at_10[0x1]; 423 u8 sw_owner[0x1]; 424 u8 reformat_l3_tunnel_to_l2[0x1]; 425 u8 reformat_l2_to_l3_tunnel[0x1]; 426 u8 reformat_and_modify_action[0x1]; 427 u8 ignore_flow_level[0x1]; 428 u8 reserved_at_16[0x1]; 429 u8 table_miss_action_domain[0x1]; 430 u8 termination_table[0x1]; 431 u8 reformat_and_fwd_to_table[0x1]; 432 u8 reserved_at_1a[0x2]; 433 u8 ipsec_encrypt[0x1]; 434 u8 ipsec_decrypt[0x1]; 435 u8 sw_owner_v2[0x1]; 436 u8 reserved_at_1f[0x1]; 437 438 u8 termination_table_raw_traffic[0x1]; 439 u8 reserved_at_21[0x1]; 440 u8 log_max_ft_size[0x6]; 441 u8 log_max_modify_header_context[0x8]; 442 u8 max_modify_header_actions[0x8]; 443 u8 max_ft_level[0x8]; 444 445 u8 reserved_at_40[0x6]; 446 u8 execute_aso[0x1]; 447 u8 reserved_at_47[0x19]; 448 449 u8 reserved_at_60[0x2]; 450 u8 reformat_insert[0x1]; 451 u8 reformat_remove[0x1]; 452 u8 reserver_at_64[0x14]; 453 u8 log_max_ft_num[0x8]; 454 455 u8 reserved_at_80[0x10]; 456 u8 log_max_flow_counter[0x8]; 457 u8 log_max_destination[0x8]; 458 459 u8 reserved_at_a0[0x18]; 460 u8 log_max_flow[0x8]; 461 462 u8 reserved_at_c0[0x40]; 463 464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 465 466 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 467 }; 468 469 struct mlx5_ifc_odp_per_transport_service_cap_bits { 470 u8 send[0x1]; 471 u8 receive[0x1]; 472 u8 write[0x1]; 473 u8 read[0x1]; 474 u8 atomic[0x1]; 475 u8 srq_receive[0x1]; 476 u8 reserved_at_6[0x1a]; 477 }; 478 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 480 u8 smac_47_16[0x20]; 481 482 u8 smac_15_0[0x10]; 483 u8 ethertype[0x10]; 484 485 u8 dmac_47_16[0x20]; 486 487 u8 dmac_15_0[0x10]; 488 u8 first_prio[0x3]; 489 u8 first_cfi[0x1]; 490 u8 first_vid[0xc]; 491 492 u8 ip_protocol[0x8]; 493 u8 ip_dscp[0x6]; 494 u8 ip_ecn[0x2]; 495 u8 cvlan_tag[0x1]; 496 u8 svlan_tag[0x1]; 497 u8 frag[0x1]; 498 u8 ip_version[0x4]; 499 u8 tcp_flags[0x9]; 500 501 u8 tcp_sport[0x10]; 502 u8 tcp_dport[0x10]; 503 504 u8 reserved_at_c0[0x10]; 505 u8 ipv4_ihl[0x4]; 506 u8 reserved_at_c4[0x4]; 507 508 u8 ttl_hoplimit[0x8]; 509 510 u8 udp_sport[0x10]; 511 u8 udp_dport[0x10]; 512 513 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 514 515 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 516 }; 517 518 struct mlx5_ifc_nvgre_key_bits { 519 u8 hi[0x18]; 520 u8 lo[0x8]; 521 }; 522 523 union mlx5_ifc_gre_key_bits { 524 struct mlx5_ifc_nvgre_key_bits nvgre; 525 u8 key[0x20]; 526 }; 527 528 struct mlx5_ifc_fte_match_set_misc_bits { 529 u8 gre_c_present[0x1]; 530 u8 reserved_at_1[0x1]; 531 u8 gre_k_present[0x1]; 532 u8 gre_s_present[0x1]; 533 u8 source_vhca_port[0x4]; 534 u8 source_sqn[0x18]; 535 536 u8 source_eswitch_owner_vhca_id[0x10]; 537 u8 source_port[0x10]; 538 539 u8 outer_second_prio[0x3]; 540 u8 outer_second_cfi[0x1]; 541 u8 outer_second_vid[0xc]; 542 u8 inner_second_prio[0x3]; 543 u8 inner_second_cfi[0x1]; 544 u8 inner_second_vid[0xc]; 545 546 u8 outer_second_cvlan_tag[0x1]; 547 u8 inner_second_cvlan_tag[0x1]; 548 u8 outer_second_svlan_tag[0x1]; 549 u8 inner_second_svlan_tag[0x1]; 550 u8 reserved_at_64[0xc]; 551 u8 gre_protocol[0x10]; 552 553 union mlx5_ifc_gre_key_bits gre_key; 554 555 u8 vxlan_vni[0x18]; 556 u8 bth_opcode[0x8]; 557 558 u8 geneve_vni[0x18]; 559 u8 reserved_at_d8[0x6]; 560 u8 geneve_tlv_option_0_exist[0x1]; 561 u8 geneve_oam[0x1]; 562 563 u8 reserved_at_e0[0xc]; 564 u8 outer_ipv6_flow_label[0x14]; 565 566 u8 reserved_at_100[0xc]; 567 u8 inner_ipv6_flow_label[0x14]; 568 569 u8 reserved_at_120[0xa]; 570 u8 geneve_opt_len[0x6]; 571 u8 geneve_protocol_type[0x10]; 572 573 u8 reserved_at_140[0x8]; 574 u8 bth_dst_qp[0x18]; 575 u8 reserved_at_160[0x20]; 576 u8 outer_esp_spi[0x20]; 577 u8 reserved_at_1a0[0x60]; 578 }; 579 580 struct mlx5_ifc_fte_match_mpls_bits { 581 u8 mpls_label[0x14]; 582 u8 mpls_exp[0x3]; 583 u8 mpls_s_bos[0x1]; 584 u8 mpls_ttl[0x8]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc2_bits { 588 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 589 590 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 591 592 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 593 594 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 595 596 u8 metadata_reg_c_7[0x20]; 597 598 u8 metadata_reg_c_6[0x20]; 599 600 u8 metadata_reg_c_5[0x20]; 601 602 u8 metadata_reg_c_4[0x20]; 603 604 u8 metadata_reg_c_3[0x20]; 605 606 u8 metadata_reg_c_2[0x20]; 607 608 u8 metadata_reg_c_1[0x20]; 609 610 u8 metadata_reg_c_0[0x20]; 611 612 u8 metadata_reg_a[0x20]; 613 614 u8 reserved_at_1a0[0x60]; 615 }; 616 617 struct mlx5_ifc_fte_match_set_misc3_bits { 618 u8 inner_tcp_seq_num[0x20]; 619 620 u8 outer_tcp_seq_num[0x20]; 621 622 u8 inner_tcp_ack_num[0x20]; 623 624 u8 outer_tcp_ack_num[0x20]; 625 626 u8 reserved_at_80[0x8]; 627 u8 outer_vxlan_gpe_vni[0x18]; 628 629 u8 outer_vxlan_gpe_next_protocol[0x8]; 630 u8 outer_vxlan_gpe_flags[0x8]; 631 u8 reserved_at_b0[0x10]; 632 633 u8 icmp_header_data[0x20]; 634 635 u8 icmpv6_header_data[0x20]; 636 637 u8 icmp_type[0x8]; 638 u8 icmp_code[0x8]; 639 u8 icmpv6_type[0x8]; 640 u8 icmpv6_code[0x8]; 641 642 u8 geneve_tlv_option_0_data[0x20]; 643 644 u8 gtpu_teid[0x20]; 645 646 u8 gtpu_msg_type[0x8]; 647 u8 gtpu_msg_flags[0x8]; 648 u8 reserved_at_170[0x10]; 649 650 u8 gtpu_dw_2[0x20]; 651 652 u8 gtpu_first_ext_dw_0[0x20]; 653 654 u8 gtpu_dw_0[0x20]; 655 656 u8 reserved_at_1e0[0x20]; 657 }; 658 659 struct mlx5_ifc_fte_match_set_misc4_bits { 660 u8 prog_sample_field_value_0[0x20]; 661 662 u8 prog_sample_field_id_0[0x20]; 663 664 u8 prog_sample_field_value_1[0x20]; 665 666 u8 prog_sample_field_id_1[0x20]; 667 668 u8 prog_sample_field_value_2[0x20]; 669 670 u8 prog_sample_field_id_2[0x20]; 671 672 u8 prog_sample_field_value_3[0x20]; 673 674 u8 prog_sample_field_id_3[0x20]; 675 676 u8 reserved_at_100[0x100]; 677 }; 678 679 struct mlx5_ifc_fte_match_set_misc5_bits { 680 u8 macsec_tag_0[0x20]; 681 682 u8 macsec_tag_1[0x20]; 683 684 u8 macsec_tag_2[0x20]; 685 686 u8 macsec_tag_3[0x20]; 687 688 u8 tunnel_header_0[0x20]; 689 690 u8 tunnel_header_1[0x20]; 691 692 u8 tunnel_header_2[0x20]; 693 694 u8 tunnel_header_3[0x20]; 695 696 u8 reserved_at_100[0x100]; 697 }; 698 699 struct mlx5_ifc_cmd_pas_bits { 700 u8 pa_h[0x20]; 701 702 u8 pa_l[0x14]; 703 u8 reserved_at_34[0xc]; 704 }; 705 706 struct mlx5_ifc_uint64_bits { 707 u8 hi[0x20]; 708 709 u8 lo[0x20]; 710 }; 711 712 enum { 713 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 714 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 715 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 716 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 717 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 718 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 719 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 720 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 721 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 722 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 723 }; 724 725 struct mlx5_ifc_ads_bits { 726 u8 fl[0x1]; 727 u8 free_ar[0x1]; 728 u8 reserved_at_2[0xe]; 729 u8 pkey_index[0x10]; 730 731 u8 reserved_at_20[0x8]; 732 u8 grh[0x1]; 733 u8 mlid[0x7]; 734 u8 rlid[0x10]; 735 736 u8 ack_timeout[0x5]; 737 u8 reserved_at_45[0x3]; 738 u8 src_addr_index[0x8]; 739 u8 reserved_at_50[0x4]; 740 u8 stat_rate[0x4]; 741 u8 hop_limit[0x8]; 742 743 u8 reserved_at_60[0x4]; 744 u8 tclass[0x8]; 745 u8 flow_label[0x14]; 746 747 u8 rgid_rip[16][0x8]; 748 749 u8 reserved_at_100[0x4]; 750 u8 f_dscp[0x1]; 751 u8 f_ecn[0x1]; 752 u8 reserved_at_106[0x1]; 753 u8 f_eth_prio[0x1]; 754 u8 ecn[0x2]; 755 u8 dscp[0x6]; 756 u8 udp_sport[0x10]; 757 758 u8 dei_cfi[0x1]; 759 u8 eth_prio[0x3]; 760 u8 sl[0x4]; 761 u8 vhca_port_num[0x8]; 762 u8 rmac_47_32[0x10]; 763 764 u8 rmac_31_0[0x20]; 765 }; 766 767 struct mlx5_ifc_flow_table_nic_cap_bits { 768 u8 nic_rx_multi_path_tirs[0x1]; 769 u8 nic_rx_multi_path_tirs_fts[0x1]; 770 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 771 u8 reserved_at_3[0x4]; 772 u8 sw_owner_reformat_supported[0x1]; 773 u8 reserved_at_8[0x18]; 774 775 u8 encap_general_header[0x1]; 776 u8 reserved_at_21[0xa]; 777 u8 log_max_packet_reformat_context[0x5]; 778 u8 reserved_at_30[0x6]; 779 u8 max_encap_header_size[0xa]; 780 u8 reserved_at_40[0x1c0]; 781 782 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 783 784 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 785 786 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 787 788 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 789 790 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 791 792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 793 794 u8 reserved_at_e00[0x700]; 795 796 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 797 798 u8 reserved_at_1580[0x280]; 799 800 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 801 802 u8 reserved_at_1880[0x780]; 803 804 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 805 806 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 807 808 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 809 810 u8 reserved_at_20c0[0x5f40]; 811 }; 812 813 struct mlx5_ifc_port_selection_cap_bits { 814 u8 reserved_at_0[0x10]; 815 u8 port_select_flow_table[0x1]; 816 u8 reserved_at_11[0xf]; 817 818 u8 reserved_at_20[0x1e0]; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 821 822 u8 reserved_at_400[0x7c00]; 823 }; 824 825 enum { 826 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 827 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 828 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 829 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 830 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 831 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 832 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 833 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 834 }; 835 836 struct mlx5_ifc_flow_table_eswitch_cap_bits { 837 u8 fdb_to_vport_reg_c_id[0x8]; 838 u8 reserved_at_8[0xd]; 839 u8 fdb_modify_header_fwd_to_table[0x1]; 840 u8 fdb_ipv4_ttl_modify[0x1]; 841 u8 flow_source[0x1]; 842 u8 reserved_at_18[0x2]; 843 u8 multi_fdb_encap[0x1]; 844 u8 egress_acl_forward_to_vport[0x1]; 845 u8 fdb_multi_path_to_table[0x1]; 846 u8 reserved_at_1d[0x3]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 851 852 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 853 854 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 855 856 u8 reserved_at_800[0x1000]; 857 858 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 859 860 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 861 862 u8 sw_steering_uplink_icm_address_rx[0x40]; 863 864 u8 sw_steering_uplink_icm_address_tx[0x40]; 865 866 u8 reserved_at_1900[0x6700]; 867 }; 868 869 enum { 870 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 871 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 872 }; 873 874 struct mlx5_ifc_e_switch_cap_bits { 875 u8 vport_svlan_strip[0x1]; 876 u8 vport_cvlan_strip[0x1]; 877 u8 vport_svlan_insert[0x1]; 878 u8 vport_cvlan_insert_if_not_exist[0x1]; 879 u8 vport_cvlan_insert_overwrite[0x1]; 880 u8 reserved_at_5[0x2]; 881 u8 esw_shared_ingress_acl[0x1]; 882 u8 esw_uplink_ingress_acl[0x1]; 883 u8 root_ft_on_other_esw[0x1]; 884 u8 reserved_at_a[0xf]; 885 u8 esw_functions_changed[0x1]; 886 u8 reserved_at_1a[0x1]; 887 u8 ecpf_vport_exists[0x1]; 888 u8 counter_eswitch_affinity[0x1]; 889 u8 merged_eswitch[0x1]; 890 u8 nic_vport_node_guid_modify[0x1]; 891 u8 nic_vport_port_guid_modify[0x1]; 892 893 u8 vxlan_encap_decap[0x1]; 894 u8 nvgre_encap_decap[0x1]; 895 u8 reserved_at_22[0x1]; 896 u8 log_max_fdb_encap_uplink[0x5]; 897 u8 reserved_at_21[0x3]; 898 u8 log_max_packet_reformat_context[0x5]; 899 u8 reserved_2b[0x6]; 900 u8 max_encap_header_size[0xa]; 901 902 u8 reserved_at_40[0xb]; 903 u8 log_max_esw_sf[0x5]; 904 u8 esw_sf_base_id[0x10]; 905 906 u8 reserved_at_60[0x7a0]; 907 908 }; 909 910 struct mlx5_ifc_qos_cap_bits { 911 u8 packet_pacing[0x1]; 912 u8 esw_scheduling[0x1]; 913 u8 esw_bw_share[0x1]; 914 u8 esw_rate_limit[0x1]; 915 u8 reserved_at_4[0x1]; 916 u8 packet_pacing_burst_bound[0x1]; 917 u8 packet_pacing_typical_size[0x1]; 918 u8 reserved_at_7[0x1]; 919 u8 nic_sq_scheduling[0x1]; 920 u8 nic_bw_share[0x1]; 921 u8 nic_rate_limit[0x1]; 922 u8 packet_pacing_uid[0x1]; 923 u8 log_esw_max_sched_depth[0x4]; 924 u8 reserved_at_10[0x10]; 925 926 u8 reserved_at_20[0xb]; 927 u8 log_max_qos_nic_queue_group[0x5]; 928 u8 reserved_at_30[0x10]; 929 930 u8 packet_pacing_max_rate[0x20]; 931 932 u8 packet_pacing_min_rate[0x20]; 933 934 u8 reserved_at_80[0x10]; 935 u8 packet_pacing_rate_table_size[0x10]; 936 937 u8 esw_element_type[0x10]; 938 u8 esw_tsar_type[0x10]; 939 940 u8 reserved_at_c0[0x10]; 941 u8 max_qos_para_vport[0x10]; 942 943 u8 max_tsar_bw_share[0x20]; 944 945 u8 reserved_at_100[0x20]; 946 947 u8 reserved_at_120[0x3]; 948 u8 log_meter_aso_granularity[0x5]; 949 u8 reserved_at_128[0x3]; 950 u8 log_meter_aso_max_alloc[0x5]; 951 u8 reserved_at_130[0x3]; 952 u8 log_max_num_meter_aso[0x5]; 953 u8 reserved_at_138[0x8]; 954 955 u8 reserved_at_140[0x6c0]; 956 }; 957 958 struct mlx5_ifc_debug_cap_bits { 959 u8 core_dump_general[0x1]; 960 u8 core_dump_qp[0x1]; 961 u8 reserved_at_2[0x7]; 962 u8 resource_dump[0x1]; 963 u8 reserved_at_a[0x16]; 964 965 u8 reserved_at_20[0x2]; 966 u8 stall_detect[0x1]; 967 u8 reserved_at_23[0x1d]; 968 969 u8 reserved_at_40[0x7c0]; 970 }; 971 972 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 973 u8 csum_cap[0x1]; 974 u8 vlan_cap[0x1]; 975 u8 lro_cap[0x1]; 976 u8 lro_psh_flag[0x1]; 977 u8 lro_time_stamp[0x1]; 978 u8 reserved_at_5[0x2]; 979 u8 wqe_vlan_insert[0x1]; 980 u8 self_lb_en_modifiable[0x1]; 981 u8 reserved_at_9[0x2]; 982 u8 max_lso_cap[0x5]; 983 u8 multi_pkt_send_wqe[0x2]; 984 u8 wqe_inline_mode[0x2]; 985 u8 rss_ind_tbl_cap[0x4]; 986 u8 reg_umr_sq[0x1]; 987 u8 scatter_fcs[0x1]; 988 u8 enhanced_multi_pkt_send_wqe[0x1]; 989 u8 tunnel_lso_const_out_ip_id[0x1]; 990 u8 tunnel_lro_gre[0x1]; 991 u8 tunnel_lro_vxlan[0x1]; 992 u8 tunnel_stateless_gre[0x1]; 993 u8 tunnel_stateless_vxlan[0x1]; 994 995 u8 swp[0x1]; 996 u8 swp_csum[0x1]; 997 u8 swp_lso[0x1]; 998 u8 cqe_checksum_full[0x1]; 999 u8 tunnel_stateless_geneve_tx[0x1]; 1000 u8 tunnel_stateless_mpls_over_udp[0x1]; 1001 u8 tunnel_stateless_mpls_over_gre[0x1]; 1002 u8 tunnel_stateless_vxlan_gpe[0x1]; 1003 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1004 u8 tunnel_stateless_ip_over_ip[0x1]; 1005 u8 insert_trailer[0x1]; 1006 u8 reserved_at_2b[0x1]; 1007 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1008 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1009 u8 reserved_at_2e[0x2]; 1010 u8 max_vxlan_udp_ports[0x8]; 1011 u8 reserved_at_38[0x6]; 1012 u8 max_geneve_opt_len[0x1]; 1013 u8 tunnel_stateless_geneve_rx[0x1]; 1014 1015 u8 reserved_at_40[0x10]; 1016 u8 lro_min_mss_size[0x10]; 1017 1018 u8 reserved_at_60[0x120]; 1019 1020 u8 lro_timer_supported_periods[4][0x20]; 1021 1022 u8 reserved_at_200[0x600]; 1023 }; 1024 1025 enum { 1026 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1027 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1028 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1029 }; 1030 1031 struct mlx5_ifc_roce_cap_bits { 1032 u8 roce_apm[0x1]; 1033 u8 reserved_at_1[0x3]; 1034 u8 sw_r_roce_src_udp_port[0x1]; 1035 u8 fl_rc_qp_when_roce_disabled[0x1]; 1036 u8 fl_rc_qp_when_roce_enabled[0x1]; 1037 u8 reserved_at_7[0x17]; 1038 u8 qp_ts_format[0x2]; 1039 1040 u8 reserved_at_20[0x60]; 1041 1042 u8 reserved_at_80[0xc]; 1043 u8 l3_type[0x4]; 1044 u8 reserved_at_90[0x8]; 1045 u8 roce_version[0x8]; 1046 1047 u8 reserved_at_a0[0x10]; 1048 u8 r_roce_dest_udp_port[0x10]; 1049 1050 u8 r_roce_max_src_udp_port[0x10]; 1051 u8 r_roce_min_src_udp_port[0x10]; 1052 1053 u8 reserved_at_e0[0x10]; 1054 u8 roce_address_table_size[0x10]; 1055 1056 u8 reserved_at_100[0x700]; 1057 }; 1058 1059 struct mlx5_ifc_sync_steering_in_bits { 1060 u8 opcode[0x10]; 1061 u8 uid[0x10]; 1062 1063 u8 reserved_at_20[0x10]; 1064 u8 op_mod[0x10]; 1065 1066 u8 reserved_at_40[0xc0]; 1067 }; 1068 1069 struct mlx5_ifc_sync_steering_out_bits { 1070 u8 status[0x8]; 1071 u8 reserved_at_8[0x18]; 1072 1073 u8 syndrome[0x20]; 1074 1075 u8 reserved_at_40[0x40]; 1076 }; 1077 1078 struct mlx5_ifc_device_mem_cap_bits { 1079 u8 memic[0x1]; 1080 u8 reserved_at_1[0x1f]; 1081 1082 u8 reserved_at_20[0xb]; 1083 u8 log_min_memic_alloc_size[0x5]; 1084 u8 reserved_at_30[0x8]; 1085 u8 log_max_memic_addr_alignment[0x8]; 1086 1087 u8 memic_bar_start_addr[0x40]; 1088 1089 u8 memic_bar_size[0x20]; 1090 1091 u8 max_memic_size[0x20]; 1092 1093 u8 steering_sw_icm_start_address[0x40]; 1094 1095 u8 reserved_at_100[0x8]; 1096 u8 log_header_modify_sw_icm_size[0x8]; 1097 u8 reserved_at_110[0x2]; 1098 u8 log_sw_icm_alloc_granularity[0x6]; 1099 u8 log_steering_sw_icm_size[0x8]; 1100 1101 u8 reserved_at_120[0x18]; 1102 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1103 1104 u8 header_modify_sw_icm_start_address[0x40]; 1105 1106 u8 reserved_at_180[0x40]; 1107 1108 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1109 1110 u8 memic_operations[0x20]; 1111 1112 u8 reserved_at_220[0x5e0]; 1113 }; 1114 1115 struct mlx5_ifc_device_event_cap_bits { 1116 u8 user_affiliated_events[4][0x40]; 1117 1118 u8 user_unaffiliated_events[4][0x40]; 1119 }; 1120 1121 struct mlx5_ifc_virtio_emulation_cap_bits { 1122 u8 desc_tunnel_offload_type[0x1]; 1123 u8 eth_frame_offload_type[0x1]; 1124 u8 virtio_version_1_0[0x1]; 1125 u8 device_features_bits_mask[0xd]; 1126 u8 event_mode[0x8]; 1127 u8 virtio_queue_type[0x8]; 1128 1129 u8 max_tunnel_desc[0x10]; 1130 u8 reserved_at_30[0x3]; 1131 u8 log_doorbell_stride[0x5]; 1132 u8 reserved_at_38[0x3]; 1133 u8 log_doorbell_bar_size[0x5]; 1134 1135 u8 doorbell_bar_offset[0x40]; 1136 1137 u8 max_emulated_devices[0x8]; 1138 u8 max_num_virtio_queues[0x18]; 1139 1140 u8 reserved_at_a0[0x60]; 1141 1142 u8 umem_1_buffer_param_a[0x20]; 1143 1144 u8 umem_1_buffer_param_b[0x20]; 1145 1146 u8 umem_2_buffer_param_a[0x20]; 1147 1148 u8 umem_2_buffer_param_b[0x20]; 1149 1150 u8 umem_3_buffer_param_a[0x20]; 1151 1152 u8 umem_3_buffer_param_b[0x20]; 1153 1154 u8 reserved_at_1c0[0x640]; 1155 }; 1156 1157 enum { 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1164 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1165 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1166 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1167 }; 1168 1169 enum { 1170 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1171 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1172 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1173 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1174 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1175 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1176 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1177 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1178 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1179 }; 1180 1181 struct mlx5_ifc_atomic_caps_bits { 1182 u8 reserved_at_0[0x40]; 1183 1184 u8 atomic_req_8B_endianness_mode[0x2]; 1185 u8 reserved_at_42[0x4]; 1186 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1187 1188 u8 reserved_at_47[0x19]; 1189 1190 u8 reserved_at_60[0x20]; 1191 1192 u8 reserved_at_80[0x10]; 1193 u8 atomic_operations[0x10]; 1194 1195 u8 reserved_at_a0[0x10]; 1196 u8 atomic_size_qp[0x10]; 1197 1198 u8 reserved_at_c0[0x10]; 1199 u8 atomic_size_dc[0x10]; 1200 1201 u8 reserved_at_e0[0x720]; 1202 }; 1203 1204 struct mlx5_ifc_odp_cap_bits { 1205 u8 reserved_at_0[0x40]; 1206 1207 u8 sig[0x1]; 1208 u8 reserved_at_41[0x1f]; 1209 1210 u8 reserved_at_60[0x20]; 1211 1212 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1213 1214 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1215 1216 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1217 1218 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1219 1220 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1221 1222 u8 reserved_at_120[0x6E0]; 1223 }; 1224 1225 struct mlx5_ifc_calc_op { 1226 u8 reserved_at_0[0x10]; 1227 u8 reserved_at_10[0x9]; 1228 u8 op_swap_endianness[0x1]; 1229 u8 op_min[0x1]; 1230 u8 op_xor[0x1]; 1231 u8 op_or[0x1]; 1232 u8 op_and[0x1]; 1233 u8 op_max[0x1]; 1234 u8 op_add[0x1]; 1235 }; 1236 1237 struct mlx5_ifc_vector_calc_cap_bits { 1238 u8 calc_matrix[0x1]; 1239 u8 reserved_at_1[0x1f]; 1240 u8 reserved_at_20[0x8]; 1241 u8 max_vec_count[0x8]; 1242 u8 reserved_at_30[0xd]; 1243 u8 max_chunk_size[0x3]; 1244 struct mlx5_ifc_calc_op calc0; 1245 struct mlx5_ifc_calc_op calc1; 1246 struct mlx5_ifc_calc_op calc2; 1247 struct mlx5_ifc_calc_op calc3; 1248 1249 u8 reserved_at_c0[0x720]; 1250 }; 1251 1252 struct mlx5_ifc_tls_cap_bits { 1253 u8 tls_1_2_aes_gcm_128[0x1]; 1254 u8 tls_1_3_aes_gcm_128[0x1]; 1255 u8 tls_1_2_aes_gcm_256[0x1]; 1256 u8 tls_1_3_aes_gcm_256[0x1]; 1257 u8 reserved_at_4[0x1c]; 1258 1259 u8 reserved_at_20[0x7e0]; 1260 }; 1261 1262 struct mlx5_ifc_ipsec_cap_bits { 1263 u8 ipsec_full_offload[0x1]; 1264 u8 ipsec_crypto_offload[0x1]; 1265 u8 ipsec_esn[0x1]; 1266 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1267 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1268 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1269 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1270 u8 reserved_at_7[0x4]; 1271 u8 log_max_ipsec_offload[0x5]; 1272 u8 reserved_at_10[0x10]; 1273 1274 u8 min_log_ipsec_full_replay_window[0x8]; 1275 u8 max_log_ipsec_full_replay_window[0x8]; 1276 u8 reserved_at_30[0x7d0]; 1277 }; 1278 1279 enum { 1280 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1281 MLX5_WQ_TYPE_CYCLIC = 0x1, 1282 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1283 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1284 }; 1285 1286 enum { 1287 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1288 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1289 }; 1290 1291 enum { 1292 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1293 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1294 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1295 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1296 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1297 }; 1298 1299 enum { 1300 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1301 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1302 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1303 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1304 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1306 }; 1307 1308 enum { 1309 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1310 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1311 }; 1312 1313 enum { 1314 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1315 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1316 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1317 }; 1318 1319 enum { 1320 MLX5_CAP_PORT_TYPE_IB = 0x0, 1321 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1322 }; 1323 1324 enum { 1325 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1326 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1327 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1328 }; 1329 1330 enum { 1331 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1332 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1333 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1334 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1335 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1336 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1337 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1338 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1339 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1340 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1341 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1342 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1343 }; 1344 1345 enum { 1346 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1347 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1348 }; 1349 1350 #define MLX5_FC_BULK_SIZE_FACTOR 128 1351 1352 enum mlx5_fc_bulk_alloc_bitmask { 1353 MLX5_FC_BULK_128 = (1 << 0), 1354 MLX5_FC_BULK_256 = (1 << 1), 1355 MLX5_FC_BULK_512 = (1 << 2), 1356 MLX5_FC_BULK_1024 = (1 << 3), 1357 MLX5_FC_BULK_2048 = (1 << 4), 1358 MLX5_FC_BULK_4096 = (1 << 5), 1359 MLX5_FC_BULK_8192 = (1 << 6), 1360 MLX5_FC_BULK_16384 = (1 << 7), 1361 }; 1362 1363 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1364 1365 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1366 1367 enum { 1368 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1369 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1370 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1371 }; 1372 1373 struct mlx5_ifc_cmd_hca_cap_bits { 1374 u8 reserved_at_0[0x10]; 1375 u8 shared_object_to_user_object_allowed[0x1]; 1376 u8 reserved_at_13[0xe]; 1377 u8 vhca_resource_manager[0x1]; 1378 1379 u8 hca_cap_2[0x1]; 1380 u8 create_lag_when_not_master_up[0x1]; 1381 u8 dtor[0x1]; 1382 u8 event_on_vhca_state_teardown_request[0x1]; 1383 u8 event_on_vhca_state_in_use[0x1]; 1384 u8 event_on_vhca_state_active[0x1]; 1385 u8 event_on_vhca_state_allocated[0x1]; 1386 u8 event_on_vhca_state_invalid[0x1]; 1387 u8 reserved_at_28[0x8]; 1388 u8 vhca_id[0x10]; 1389 1390 u8 reserved_at_40[0x40]; 1391 1392 u8 log_max_srq_sz[0x8]; 1393 u8 log_max_qp_sz[0x8]; 1394 u8 event_cap[0x1]; 1395 u8 reserved_at_91[0x2]; 1396 u8 isolate_vl_tc_new[0x1]; 1397 u8 reserved_at_94[0x4]; 1398 u8 prio_tag_required[0x1]; 1399 u8 reserved_at_99[0x2]; 1400 u8 log_max_qp[0x5]; 1401 1402 u8 reserved_at_a0[0x3]; 1403 u8 ece_support[0x1]; 1404 u8 reserved_at_a4[0x5]; 1405 u8 reg_c_preserve[0x1]; 1406 u8 reserved_at_aa[0x1]; 1407 u8 log_max_srq[0x5]; 1408 u8 reserved_at_b0[0x1]; 1409 u8 uplink_follow[0x1]; 1410 u8 ts_cqe_to_dest_cqn[0x1]; 1411 u8 reserved_at_b3[0x7]; 1412 u8 shampo[0x1]; 1413 u8 reserved_at_bb[0x5]; 1414 1415 u8 max_sgl_for_optimized_performance[0x8]; 1416 u8 log_max_cq_sz[0x8]; 1417 u8 relaxed_ordering_write_umr[0x1]; 1418 u8 relaxed_ordering_read_umr[0x1]; 1419 u8 reserved_at_d2[0x7]; 1420 u8 virtio_net_device_emualtion_manager[0x1]; 1421 u8 virtio_blk_device_emualtion_manager[0x1]; 1422 u8 log_max_cq[0x5]; 1423 1424 u8 log_max_eq_sz[0x8]; 1425 u8 relaxed_ordering_write[0x1]; 1426 u8 relaxed_ordering_read[0x1]; 1427 u8 log_max_mkey[0x6]; 1428 u8 reserved_at_f0[0x8]; 1429 u8 dump_fill_mkey[0x1]; 1430 u8 reserved_at_f9[0x2]; 1431 u8 fast_teardown[0x1]; 1432 u8 log_max_eq[0x4]; 1433 1434 u8 max_indirection[0x8]; 1435 u8 fixed_buffer_size[0x1]; 1436 u8 log_max_mrw_sz[0x7]; 1437 u8 force_teardown[0x1]; 1438 u8 reserved_at_111[0x1]; 1439 u8 log_max_bsf_list_size[0x6]; 1440 u8 umr_extended_translation_offset[0x1]; 1441 u8 null_mkey[0x1]; 1442 u8 log_max_klm_list_size[0x6]; 1443 1444 u8 reserved_at_120[0xa]; 1445 u8 log_max_ra_req_dc[0x6]; 1446 u8 reserved_at_130[0x9]; 1447 u8 vnic_env_cq_overrun[0x1]; 1448 u8 log_max_ra_res_dc[0x6]; 1449 1450 u8 reserved_at_140[0x5]; 1451 u8 release_all_pages[0x1]; 1452 u8 must_not_use[0x1]; 1453 u8 reserved_at_147[0x2]; 1454 u8 roce_accl[0x1]; 1455 u8 log_max_ra_req_qp[0x6]; 1456 u8 reserved_at_150[0xa]; 1457 u8 log_max_ra_res_qp[0x6]; 1458 1459 u8 end_pad[0x1]; 1460 u8 cc_query_allowed[0x1]; 1461 u8 cc_modify_allowed[0x1]; 1462 u8 start_pad[0x1]; 1463 u8 cache_line_128byte[0x1]; 1464 u8 reserved_at_165[0x4]; 1465 u8 rts2rts_qp_counters_set_id[0x1]; 1466 u8 reserved_at_16a[0x2]; 1467 u8 vnic_env_int_rq_oob[0x1]; 1468 u8 sbcam_reg[0x1]; 1469 u8 reserved_at_16e[0x1]; 1470 u8 qcam_reg[0x1]; 1471 u8 gid_table_size[0x10]; 1472 1473 u8 out_of_seq_cnt[0x1]; 1474 u8 vport_counters[0x1]; 1475 u8 retransmission_q_counters[0x1]; 1476 u8 debug[0x1]; 1477 u8 modify_rq_counter_set_id[0x1]; 1478 u8 rq_delay_drop[0x1]; 1479 u8 max_qp_cnt[0xa]; 1480 u8 pkey_table_size[0x10]; 1481 1482 u8 vport_group_manager[0x1]; 1483 u8 vhca_group_manager[0x1]; 1484 u8 ib_virt[0x1]; 1485 u8 eth_virt[0x1]; 1486 u8 vnic_env_queue_counters[0x1]; 1487 u8 ets[0x1]; 1488 u8 nic_flow_table[0x1]; 1489 u8 eswitch_manager[0x1]; 1490 u8 device_memory[0x1]; 1491 u8 mcam_reg[0x1]; 1492 u8 pcam_reg[0x1]; 1493 u8 local_ca_ack_delay[0x5]; 1494 u8 port_module_event[0x1]; 1495 u8 enhanced_error_q_counters[0x1]; 1496 u8 ports_check[0x1]; 1497 u8 reserved_at_1b3[0x1]; 1498 u8 disable_link_up[0x1]; 1499 u8 beacon_led[0x1]; 1500 u8 port_type[0x2]; 1501 u8 num_ports[0x8]; 1502 1503 u8 reserved_at_1c0[0x1]; 1504 u8 pps[0x1]; 1505 u8 pps_modify[0x1]; 1506 u8 log_max_msg[0x5]; 1507 u8 reserved_at_1c8[0x4]; 1508 u8 max_tc[0x4]; 1509 u8 temp_warn_event[0x1]; 1510 u8 dcbx[0x1]; 1511 u8 general_notification_event[0x1]; 1512 u8 reserved_at_1d3[0x2]; 1513 u8 fpga[0x1]; 1514 u8 rol_s[0x1]; 1515 u8 rol_g[0x1]; 1516 u8 reserved_at_1d8[0x1]; 1517 u8 wol_s[0x1]; 1518 u8 wol_g[0x1]; 1519 u8 wol_a[0x1]; 1520 u8 wol_b[0x1]; 1521 u8 wol_m[0x1]; 1522 u8 wol_u[0x1]; 1523 u8 wol_p[0x1]; 1524 1525 u8 stat_rate_support[0x10]; 1526 u8 reserved_at_1f0[0x1]; 1527 u8 pci_sync_for_fw_update_event[0x1]; 1528 u8 reserved_at_1f2[0x6]; 1529 u8 init2_lag_tx_port_affinity[0x1]; 1530 u8 reserved_at_1fa[0x3]; 1531 u8 cqe_version[0x4]; 1532 1533 u8 compact_address_vector[0x1]; 1534 u8 striding_rq[0x1]; 1535 u8 reserved_at_202[0x1]; 1536 u8 ipoib_enhanced_offloads[0x1]; 1537 u8 ipoib_basic_offloads[0x1]; 1538 u8 reserved_at_205[0x1]; 1539 u8 repeated_block_disabled[0x1]; 1540 u8 umr_modify_entity_size_disabled[0x1]; 1541 u8 umr_modify_atomic_disabled[0x1]; 1542 u8 umr_indirect_mkey_disabled[0x1]; 1543 u8 umr_fence[0x2]; 1544 u8 dc_req_scat_data_cqe[0x1]; 1545 u8 reserved_at_20d[0x2]; 1546 u8 drain_sigerr[0x1]; 1547 u8 cmdif_checksum[0x2]; 1548 u8 sigerr_cqe[0x1]; 1549 u8 reserved_at_213[0x1]; 1550 u8 wq_signature[0x1]; 1551 u8 sctr_data_cqe[0x1]; 1552 u8 reserved_at_216[0x1]; 1553 u8 sho[0x1]; 1554 u8 tph[0x1]; 1555 u8 rf[0x1]; 1556 u8 dct[0x1]; 1557 u8 qos[0x1]; 1558 u8 eth_net_offloads[0x1]; 1559 u8 roce[0x1]; 1560 u8 atomic[0x1]; 1561 u8 reserved_at_21f[0x1]; 1562 1563 u8 cq_oi[0x1]; 1564 u8 cq_resize[0x1]; 1565 u8 cq_moderation[0x1]; 1566 u8 reserved_at_223[0x3]; 1567 u8 cq_eq_remap[0x1]; 1568 u8 pg[0x1]; 1569 u8 block_lb_mc[0x1]; 1570 u8 reserved_at_229[0x1]; 1571 u8 scqe_break_moderation[0x1]; 1572 u8 cq_period_start_from_cqe[0x1]; 1573 u8 cd[0x1]; 1574 u8 reserved_at_22d[0x1]; 1575 u8 apm[0x1]; 1576 u8 vector_calc[0x1]; 1577 u8 umr_ptr_rlky[0x1]; 1578 u8 imaicl[0x1]; 1579 u8 qp_packet_based[0x1]; 1580 u8 reserved_at_233[0x3]; 1581 u8 qkv[0x1]; 1582 u8 pkv[0x1]; 1583 u8 set_deth_sqpn[0x1]; 1584 u8 reserved_at_239[0x3]; 1585 u8 xrc[0x1]; 1586 u8 ud[0x1]; 1587 u8 uc[0x1]; 1588 u8 rc[0x1]; 1589 1590 u8 uar_4k[0x1]; 1591 u8 reserved_at_241[0x9]; 1592 u8 uar_sz[0x6]; 1593 u8 port_selection_cap[0x1]; 1594 u8 reserved_at_248[0x1]; 1595 u8 umem_uid_0[0x1]; 1596 u8 reserved_at_250[0x5]; 1597 u8 log_pg_sz[0x8]; 1598 1599 u8 bf[0x1]; 1600 u8 driver_version[0x1]; 1601 u8 pad_tx_eth_packet[0x1]; 1602 u8 reserved_at_263[0x3]; 1603 u8 mkey_by_name[0x1]; 1604 u8 reserved_at_267[0x4]; 1605 1606 u8 log_bf_reg_size[0x5]; 1607 1608 u8 reserved_at_270[0x6]; 1609 u8 lag_dct[0x2]; 1610 u8 lag_tx_port_affinity[0x1]; 1611 u8 lag_native_fdb_selection[0x1]; 1612 u8 reserved_at_27a[0x1]; 1613 u8 lag_master[0x1]; 1614 u8 num_lag_ports[0x4]; 1615 1616 u8 reserved_at_280[0x10]; 1617 u8 max_wqe_sz_sq[0x10]; 1618 1619 u8 reserved_at_2a0[0x10]; 1620 u8 max_wqe_sz_rq[0x10]; 1621 1622 u8 max_flow_counter_31_16[0x10]; 1623 u8 max_wqe_sz_sq_dc[0x10]; 1624 1625 u8 reserved_at_2e0[0x7]; 1626 u8 max_qp_mcg[0x19]; 1627 1628 u8 reserved_at_300[0x10]; 1629 u8 flow_counter_bulk_alloc[0x8]; 1630 u8 log_max_mcg[0x8]; 1631 1632 u8 reserved_at_320[0x3]; 1633 u8 log_max_transport_domain[0x5]; 1634 u8 reserved_at_328[0x3]; 1635 u8 log_max_pd[0x5]; 1636 u8 reserved_at_330[0xb]; 1637 u8 log_max_xrcd[0x5]; 1638 1639 u8 nic_receive_steering_discard[0x1]; 1640 u8 receive_discard_vport_down[0x1]; 1641 u8 transmit_discard_vport_down[0x1]; 1642 u8 eq_overrun_count[0x1]; 1643 u8 reserved_at_344[0x1]; 1644 u8 invalid_command_count[0x1]; 1645 u8 quota_exceeded_count[0x1]; 1646 u8 reserved_at_347[0x1]; 1647 u8 log_max_flow_counter_bulk[0x8]; 1648 u8 max_flow_counter_15_0[0x10]; 1649 1650 1651 u8 reserved_at_360[0x3]; 1652 u8 log_max_rq[0x5]; 1653 u8 reserved_at_368[0x3]; 1654 u8 log_max_sq[0x5]; 1655 u8 reserved_at_370[0x3]; 1656 u8 log_max_tir[0x5]; 1657 u8 reserved_at_378[0x3]; 1658 u8 log_max_tis[0x5]; 1659 1660 u8 basic_cyclic_rcv_wqe[0x1]; 1661 u8 reserved_at_381[0x2]; 1662 u8 log_max_rmp[0x5]; 1663 u8 reserved_at_388[0x3]; 1664 u8 log_max_rqt[0x5]; 1665 u8 reserved_at_390[0x3]; 1666 u8 log_max_rqt_size[0x5]; 1667 u8 reserved_at_398[0x3]; 1668 u8 log_max_tis_per_sq[0x5]; 1669 1670 u8 ext_stride_num_range[0x1]; 1671 u8 roce_rw_supported[0x1]; 1672 u8 log_max_current_uc_list_wr_supported[0x1]; 1673 u8 log_max_stride_sz_rq[0x5]; 1674 u8 reserved_at_3a8[0x3]; 1675 u8 log_min_stride_sz_rq[0x5]; 1676 u8 reserved_at_3b0[0x3]; 1677 u8 log_max_stride_sz_sq[0x5]; 1678 u8 reserved_at_3b8[0x3]; 1679 u8 log_min_stride_sz_sq[0x5]; 1680 1681 u8 hairpin[0x1]; 1682 u8 reserved_at_3c1[0x2]; 1683 u8 log_max_hairpin_queues[0x5]; 1684 u8 reserved_at_3c8[0x3]; 1685 u8 log_max_hairpin_wq_data_sz[0x5]; 1686 u8 reserved_at_3d0[0x3]; 1687 u8 log_max_hairpin_num_packets[0x5]; 1688 u8 reserved_at_3d8[0x3]; 1689 u8 log_max_wq_sz[0x5]; 1690 1691 u8 nic_vport_change_event[0x1]; 1692 u8 disable_local_lb_uc[0x1]; 1693 u8 disable_local_lb_mc[0x1]; 1694 u8 log_min_hairpin_wq_data_sz[0x5]; 1695 u8 reserved_at_3e8[0x2]; 1696 u8 vhca_state[0x1]; 1697 u8 log_max_vlan_list[0x5]; 1698 u8 reserved_at_3f0[0x3]; 1699 u8 log_max_current_mc_list[0x5]; 1700 u8 reserved_at_3f8[0x3]; 1701 u8 log_max_current_uc_list[0x5]; 1702 1703 u8 general_obj_types[0x40]; 1704 1705 u8 sq_ts_format[0x2]; 1706 u8 rq_ts_format[0x2]; 1707 u8 steering_format_version[0x4]; 1708 u8 create_qp_start_hint[0x18]; 1709 1710 u8 reserved_at_460[0x3]; 1711 u8 log_max_uctx[0x5]; 1712 u8 reserved_at_468[0x2]; 1713 u8 ipsec_offload[0x1]; 1714 u8 log_max_umem[0x5]; 1715 u8 max_num_eqs[0x10]; 1716 1717 u8 reserved_at_480[0x1]; 1718 u8 tls_tx[0x1]; 1719 u8 tls_rx[0x1]; 1720 u8 log_max_l2_table[0x5]; 1721 u8 reserved_at_488[0x8]; 1722 u8 log_uar_page_sz[0x10]; 1723 1724 u8 reserved_at_4a0[0x20]; 1725 u8 device_frequency_mhz[0x20]; 1726 u8 device_frequency_khz[0x20]; 1727 1728 u8 reserved_at_500[0x20]; 1729 u8 num_of_uars_per_page[0x20]; 1730 1731 u8 flex_parser_protocols[0x20]; 1732 1733 u8 max_geneve_tlv_options[0x8]; 1734 u8 reserved_at_568[0x3]; 1735 u8 max_geneve_tlv_option_data_len[0x5]; 1736 u8 reserved_at_570[0x10]; 1737 1738 u8 reserved_at_580[0xb]; 1739 u8 log_max_dci_stream_channels[0x5]; 1740 u8 reserved_at_590[0x3]; 1741 u8 log_max_dci_errored_streams[0x5]; 1742 u8 reserved_at_598[0x8]; 1743 1744 u8 reserved_at_5a0[0x10]; 1745 u8 enhanced_cqe_compression[0x1]; 1746 u8 reserved_at_5b1[0x2]; 1747 u8 log_max_dek[0x5]; 1748 u8 reserved_at_5b8[0x4]; 1749 u8 mini_cqe_resp_stride_index[0x1]; 1750 u8 cqe_128_always[0x1]; 1751 u8 cqe_compression_128[0x1]; 1752 u8 cqe_compression[0x1]; 1753 1754 u8 cqe_compression_timeout[0x10]; 1755 u8 cqe_compression_max_num[0x10]; 1756 1757 u8 reserved_at_5e0[0x8]; 1758 u8 flex_parser_id_gtpu_dw_0[0x4]; 1759 u8 reserved_at_5ec[0x4]; 1760 u8 tag_matching[0x1]; 1761 u8 rndv_offload_rc[0x1]; 1762 u8 rndv_offload_dc[0x1]; 1763 u8 log_tag_matching_list_sz[0x5]; 1764 u8 reserved_at_5f8[0x3]; 1765 u8 log_max_xrq[0x5]; 1766 1767 u8 affiliate_nic_vport_criteria[0x8]; 1768 u8 native_port_num[0x8]; 1769 u8 num_vhca_ports[0x8]; 1770 u8 flex_parser_id_gtpu_teid[0x4]; 1771 u8 reserved_at_61c[0x2]; 1772 u8 sw_owner_id[0x1]; 1773 u8 reserved_at_61f[0x1]; 1774 1775 u8 max_num_of_monitor_counters[0x10]; 1776 u8 num_ppcnt_monitor_counters[0x10]; 1777 1778 u8 max_num_sf[0x10]; 1779 u8 num_q_monitor_counters[0x10]; 1780 1781 u8 reserved_at_660[0x20]; 1782 1783 u8 sf[0x1]; 1784 u8 sf_set_partition[0x1]; 1785 u8 reserved_at_682[0x1]; 1786 u8 log_max_sf[0x5]; 1787 u8 apu[0x1]; 1788 u8 reserved_at_689[0x4]; 1789 u8 migration[0x1]; 1790 u8 reserved_at_68e[0x2]; 1791 u8 log_min_sf_size[0x8]; 1792 u8 max_num_sf_partitions[0x8]; 1793 1794 u8 uctx_cap[0x20]; 1795 1796 u8 reserved_at_6c0[0x4]; 1797 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1798 u8 flex_parser_id_icmp_dw1[0x4]; 1799 u8 flex_parser_id_icmp_dw0[0x4]; 1800 u8 flex_parser_id_icmpv6_dw1[0x4]; 1801 u8 flex_parser_id_icmpv6_dw0[0x4]; 1802 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1803 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1804 1805 u8 max_num_match_definer[0x10]; 1806 u8 sf_base_id[0x10]; 1807 1808 u8 flex_parser_id_gtpu_dw_2[0x4]; 1809 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1810 u8 num_total_dynamic_vf_msix[0x18]; 1811 u8 reserved_at_720[0x14]; 1812 u8 dynamic_msix_table_size[0xc]; 1813 u8 reserved_at_740[0xc]; 1814 u8 min_dynamic_vf_msix_table_size[0x4]; 1815 u8 reserved_at_750[0x4]; 1816 u8 max_dynamic_vf_msix_table_size[0xc]; 1817 1818 u8 reserved_at_760[0x20]; 1819 u8 vhca_tunnel_commands[0x40]; 1820 u8 match_definer_format_supported[0x40]; 1821 }; 1822 1823 struct mlx5_ifc_cmd_hca_cap_2_bits { 1824 u8 reserved_at_0[0xa0]; 1825 1826 u8 max_reformat_insert_size[0x8]; 1827 u8 max_reformat_insert_offset[0x8]; 1828 u8 max_reformat_remove_size[0x8]; 1829 u8 max_reformat_remove_offset[0x8]; 1830 1831 u8 reserved_at_c0[0x160]; 1832 1833 u8 reserved_at_220[0x1]; 1834 u8 sw_vhca_id_valid[0x1]; 1835 u8 sw_vhca_id[0xe]; 1836 u8 reserved_at_230[0x10]; 1837 1838 u8 reserved_at_240[0xb]; 1839 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1840 u8 reserved_at_250[0x10]; 1841 1842 u8 reserved_at_260[0x5a0]; 1843 }; 1844 1845 enum mlx5_ifc_flow_destination_type { 1846 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1847 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1848 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1849 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1850 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1851 }; 1852 1853 enum mlx5_flow_table_miss_action { 1854 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1855 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1856 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1857 }; 1858 1859 struct mlx5_ifc_dest_format_struct_bits { 1860 u8 destination_type[0x8]; 1861 u8 destination_id[0x18]; 1862 1863 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1864 u8 packet_reformat[0x1]; 1865 u8 reserved_at_22[0xe]; 1866 u8 destination_eswitch_owner_vhca_id[0x10]; 1867 }; 1868 1869 struct mlx5_ifc_flow_counter_list_bits { 1870 u8 flow_counter_id[0x20]; 1871 1872 u8 reserved_at_20[0x20]; 1873 }; 1874 1875 struct mlx5_ifc_extended_dest_format_bits { 1876 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1877 1878 u8 packet_reformat_id[0x20]; 1879 1880 u8 reserved_at_60[0x20]; 1881 }; 1882 1883 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1884 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1885 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1886 }; 1887 1888 struct mlx5_ifc_fte_match_param_bits { 1889 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1890 1891 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1892 1893 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1894 1895 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1896 1897 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1898 1899 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1900 1901 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1902 1903 u8 reserved_at_e00[0x200]; 1904 }; 1905 1906 enum { 1907 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1908 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1909 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1910 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1911 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1912 }; 1913 1914 struct mlx5_ifc_rx_hash_field_select_bits { 1915 u8 l3_prot_type[0x1]; 1916 u8 l4_prot_type[0x1]; 1917 u8 selected_fields[0x1e]; 1918 }; 1919 1920 enum { 1921 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1922 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1923 }; 1924 1925 enum { 1926 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1927 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1928 }; 1929 1930 struct mlx5_ifc_wq_bits { 1931 u8 wq_type[0x4]; 1932 u8 wq_signature[0x1]; 1933 u8 end_padding_mode[0x2]; 1934 u8 cd_slave[0x1]; 1935 u8 reserved_at_8[0x18]; 1936 1937 u8 hds_skip_first_sge[0x1]; 1938 u8 log2_hds_buf_size[0x3]; 1939 u8 reserved_at_24[0x7]; 1940 u8 page_offset[0x5]; 1941 u8 lwm[0x10]; 1942 1943 u8 reserved_at_40[0x8]; 1944 u8 pd[0x18]; 1945 1946 u8 reserved_at_60[0x8]; 1947 u8 uar_page[0x18]; 1948 1949 u8 dbr_addr[0x40]; 1950 1951 u8 hw_counter[0x20]; 1952 1953 u8 sw_counter[0x20]; 1954 1955 u8 reserved_at_100[0xc]; 1956 u8 log_wq_stride[0x4]; 1957 u8 reserved_at_110[0x3]; 1958 u8 log_wq_pg_sz[0x5]; 1959 u8 reserved_at_118[0x3]; 1960 u8 log_wq_sz[0x5]; 1961 1962 u8 dbr_umem_valid[0x1]; 1963 u8 wq_umem_valid[0x1]; 1964 u8 reserved_at_122[0x1]; 1965 u8 log_hairpin_num_packets[0x5]; 1966 u8 reserved_at_128[0x3]; 1967 u8 log_hairpin_data_sz[0x5]; 1968 1969 u8 reserved_at_130[0x4]; 1970 u8 log_wqe_num_of_strides[0x4]; 1971 u8 two_byte_shift_en[0x1]; 1972 u8 reserved_at_139[0x4]; 1973 u8 log_wqe_stride_size[0x3]; 1974 1975 u8 reserved_at_140[0x80]; 1976 1977 u8 headers_mkey[0x20]; 1978 1979 u8 shampo_enable[0x1]; 1980 u8 reserved_at_1e1[0x4]; 1981 u8 log_reservation_size[0x3]; 1982 u8 reserved_at_1e8[0x5]; 1983 u8 log_max_num_of_packets_per_reservation[0x3]; 1984 u8 reserved_at_1f0[0x6]; 1985 u8 log_headers_entry_size[0x2]; 1986 u8 reserved_at_1f8[0x4]; 1987 u8 log_headers_buffer_entry_num[0x4]; 1988 1989 u8 reserved_at_200[0x400]; 1990 1991 struct mlx5_ifc_cmd_pas_bits pas[]; 1992 }; 1993 1994 struct mlx5_ifc_rq_num_bits { 1995 u8 reserved_at_0[0x8]; 1996 u8 rq_num[0x18]; 1997 }; 1998 1999 struct mlx5_ifc_mac_address_layout_bits { 2000 u8 reserved_at_0[0x10]; 2001 u8 mac_addr_47_32[0x10]; 2002 2003 u8 mac_addr_31_0[0x20]; 2004 }; 2005 2006 struct mlx5_ifc_vlan_layout_bits { 2007 u8 reserved_at_0[0x14]; 2008 u8 vlan[0x0c]; 2009 2010 u8 reserved_at_20[0x20]; 2011 }; 2012 2013 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2014 u8 reserved_at_0[0xa0]; 2015 2016 u8 min_time_between_cnps[0x20]; 2017 2018 u8 reserved_at_c0[0x12]; 2019 u8 cnp_dscp[0x6]; 2020 u8 reserved_at_d8[0x4]; 2021 u8 cnp_prio_mode[0x1]; 2022 u8 cnp_802p_prio[0x3]; 2023 2024 u8 reserved_at_e0[0x720]; 2025 }; 2026 2027 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2028 u8 reserved_at_0[0x60]; 2029 2030 u8 reserved_at_60[0x4]; 2031 u8 clamp_tgt_rate[0x1]; 2032 u8 reserved_at_65[0x3]; 2033 u8 clamp_tgt_rate_after_time_inc[0x1]; 2034 u8 reserved_at_69[0x17]; 2035 2036 u8 reserved_at_80[0x20]; 2037 2038 u8 rpg_time_reset[0x20]; 2039 2040 u8 rpg_byte_reset[0x20]; 2041 2042 u8 rpg_threshold[0x20]; 2043 2044 u8 rpg_max_rate[0x20]; 2045 2046 u8 rpg_ai_rate[0x20]; 2047 2048 u8 rpg_hai_rate[0x20]; 2049 2050 u8 rpg_gd[0x20]; 2051 2052 u8 rpg_min_dec_fac[0x20]; 2053 2054 u8 rpg_min_rate[0x20]; 2055 2056 u8 reserved_at_1c0[0xe0]; 2057 2058 u8 rate_to_set_on_first_cnp[0x20]; 2059 2060 u8 dce_tcp_g[0x20]; 2061 2062 u8 dce_tcp_rtt[0x20]; 2063 2064 u8 rate_reduce_monitor_period[0x20]; 2065 2066 u8 reserved_at_320[0x20]; 2067 2068 u8 initial_alpha_value[0x20]; 2069 2070 u8 reserved_at_360[0x4a0]; 2071 }; 2072 2073 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2074 u8 reserved_at_0[0x80]; 2075 2076 u8 rppp_max_rps[0x20]; 2077 2078 u8 rpg_time_reset[0x20]; 2079 2080 u8 rpg_byte_reset[0x20]; 2081 2082 u8 rpg_threshold[0x20]; 2083 2084 u8 rpg_max_rate[0x20]; 2085 2086 u8 rpg_ai_rate[0x20]; 2087 2088 u8 rpg_hai_rate[0x20]; 2089 2090 u8 rpg_gd[0x20]; 2091 2092 u8 rpg_min_dec_fac[0x20]; 2093 2094 u8 rpg_min_rate[0x20]; 2095 2096 u8 reserved_at_1c0[0x640]; 2097 }; 2098 2099 enum { 2100 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2101 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2102 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2103 }; 2104 2105 struct mlx5_ifc_resize_field_select_bits { 2106 u8 resize_field_select[0x20]; 2107 }; 2108 2109 struct mlx5_ifc_resource_dump_bits { 2110 u8 more_dump[0x1]; 2111 u8 inline_dump[0x1]; 2112 u8 reserved_at_2[0xa]; 2113 u8 seq_num[0x4]; 2114 u8 segment_type[0x10]; 2115 2116 u8 reserved_at_20[0x10]; 2117 u8 vhca_id[0x10]; 2118 2119 u8 index1[0x20]; 2120 2121 u8 index2[0x20]; 2122 2123 u8 num_of_obj1[0x10]; 2124 u8 num_of_obj2[0x10]; 2125 2126 u8 reserved_at_a0[0x20]; 2127 2128 u8 device_opaque[0x40]; 2129 2130 u8 mkey[0x20]; 2131 2132 u8 size[0x20]; 2133 2134 u8 address[0x40]; 2135 2136 u8 inline_data[52][0x20]; 2137 }; 2138 2139 struct mlx5_ifc_resource_dump_menu_record_bits { 2140 u8 reserved_at_0[0x4]; 2141 u8 num_of_obj2_supports_active[0x1]; 2142 u8 num_of_obj2_supports_all[0x1]; 2143 u8 must_have_num_of_obj2[0x1]; 2144 u8 support_num_of_obj2[0x1]; 2145 u8 num_of_obj1_supports_active[0x1]; 2146 u8 num_of_obj1_supports_all[0x1]; 2147 u8 must_have_num_of_obj1[0x1]; 2148 u8 support_num_of_obj1[0x1]; 2149 u8 must_have_index2[0x1]; 2150 u8 support_index2[0x1]; 2151 u8 must_have_index1[0x1]; 2152 u8 support_index1[0x1]; 2153 u8 segment_type[0x10]; 2154 2155 u8 segment_name[4][0x20]; 2156 2157 u8 index1_name[4][0x20]; 2158 2159 u8 index2_name[4][0x20]; 2160 }; 2161 2162 struct mlx5_ifc_resource_dump_segment_header_bits { 2163 u8 length_dw[0x10]; 2164 u8 segment_type[0x10]; 2165 }; 2166 2167 struct mlx5_ifc_resource_dump_command_segment_bits { 2168 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2169 2170 u8 segment_called[0x10]; 2171 u8 vhca_id[0x10]; 2172 2173 u8 index1[0x20]; 2174 2175 u8 index2[0x20]; 2176 2177 u8 num_of_obj1[0x10]; 2178 u8 num_of_obj2[0x10]; 2179 }; 2180 2181 struct mlx5_ifc_resource_dump_error_segment_bits { 2182 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2183 2184 u8 reserved_at_20[0x10]; 2185 u8 syndrome_id[0x10]; 2186 2187 u8 reserved_at_40[0x40]; 2188 2189 u8 error[8][0x20]; 2190 }; 2191 2192 struct mlx5_ifc_resource_dump_info_segment_bits { 2193 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2194 2195 u8 reserved_at_20[0x18]; 2196 u8 dump_version[0x8]; 2197 2198 u8 hw_version[0x20]; 2199 2200 u8 fw_version[0x20]; 2201 }; 2202 2203 struct mlx5_ifc_resource_dump_menu_segment_bits { 2204 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2205 2206 u8 reserved_at_20[0x10]; 2207 u8 num_of_records[0x10]; 2208 2209 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2210 }; 2211 2212 struct mlx5_ifc_resource_dump_resource_segment_bits { 2213 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2214 2215 u8 reserved_at_20[0x20]; 2216 2217 u8 index1[0x20]; 2218 2219 u8 index2[0x20]; 2220 2221 u8 payload[][0x20]; 2222 }; 2223 2224 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2225 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2226 }; 2227 2228 struct mlx5_ifc_menu_resource_dump_response_bits { 2229 struct mlx5_ifc_resource_dump_info_segment_bits info; 2230 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2231 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2232 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2233 }; 2234 2235 enum { 2236 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2237 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2238 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2239 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2240 }; 2241 2242 struct mlx5_ifc_modify_field_select_bits { 2243 u8 modify_field_select[0x20]; 2244 }; 2245 2246 struct mlx5_ifc_field_select_r_roce_np_bits { 2247 u8 field_select_r_roce_np[0x20]; 2248 }; 2249 2250 struct mlx5_ifc_field_select_r_roce_rp_bits { 2251 u8 field_select_r_roce_rp[0x20]; 2252 }; 2253 2254 enum { 2255 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2256 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2257 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2258 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2263 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2265 }; 2266 2267 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2268 u8 field_select_8021qaurp[0x20]; 2269 }; 2270 2271 struct mlx5_ifc_phys_layer_cntrs_bits { 2272 u8 time_since_last_clear_high[0x20]; 2273 2274 u8 time_since_last_clear_low[0x20]; 2275 2276 u8 symbol_errors_high[0x20]; 2277 2278 u8 symbol_errors_low[0x20]; 2279 2280 u8 sync_headers_errors_high[0x20]; 2281 2282 u8 sync_headers_errors_low[0x20]; 2283 2284 u8 edpl_bip_errors_lane0_high[0x20]; 2285 2286 u8 edpl_bip_errors_lane0_low[0x20]; 2287 2288 u8 edpl_bip_errors_lane1_high[0x20]; 2289 2290 u8 edpl_bip_errors_lane1_low[0x20]; 2291 2292 u8 edpl_bip_errors_lane2_high[0x20]; 2293 2294 u8 edpl_bip_errors_lane2_low[0x20]; 2295 2296 u8 edpl_bip_errors_lane3_high[0x20]; 2297 2298 u8 edpl_bip_errors_lane3_low[0x20]; 2299 2300 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2301 2302 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2303 2304 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2305 2306 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2307 2308 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2309 2310 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2311 2312 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2313 2314 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2315 2316 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2317 2318 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2319 2320 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2321 2322 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2323 2324 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2325 2326 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2327 2328 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2329 2330 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2331 2332 u8 rs_fec_corrected_blocks_high[0x20]; 2333 2334 u8 rs_fec_corrected_blocks_low[0x20]; 2335 2336 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2337 2338 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2339 2340 u8 rs_fec_no_errors_blocks_high[0x20]; 2341 2342 u8 rs_fec_no_errors_blocks_low[0x20]; 2343 2344 u8 rs_fec_single_error_blocks_high[0x20]; 2345 2346 u8 rs_fec_single_error_blocks_low[0x20]; 2347 2348 u8 rs_fec_corrected_symbols_total_high[0x20]; 2349 2350 u8 rs_fec_corrected_symbols_total_low[0x20]; 2351 2352 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2353 2354 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2355 2356 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2357 2358 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2359 2360 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2361 2362 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2363 2364 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2365 2366 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2367 2368 u8 link_down_events[0x20]; 2369 2370 u8 successful_recovery_events[0x20]; 2371 2372 u8 reserved_at_640[0x180]; 2373 }; 2374 2375 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2376 u8 time_since_last_clear_high[0x20]; 2377 2378 u8 time_since_last_clear_low[0x20]; 2379 2380 u8 phy_received_bits_high[0x20]; 2381 2382 u8 phy_received_bits_low[0x20]; 2383 2384 u8 phy_symbol_errors_high[0x20]; 2385 2386 u8 phy_symbol_errors_low[0x20]; 2387 2388 u8 phy_corrected_bits_high[0x20]; 2389 2390 u8 phy_corrected_bits_low[0x20]; 2391 2392 u8 phy_corrected_bits_lane0_high[0x20]; 2393 2394 u8 phy_corrected_bits_lane0_low[0x20]; 2395 2396 u8 phy_corrected_bits_lane1_high[0x20]; 2397 2398 u8 phy_corrected_bits_lane1_low[0x20]; 2399 2400 u8 phy_corrected_bits_lane2_high[0x20]; 2401 2402 u8 phy_corrected_bits_lane2_low[0x20]; 2403 2404 u8 phy_corrected_bits_lane3_high[0x20]; 2405 2406 u8 phy_corrected_bits_lane3_low[0x20]; 2407 2408 u8 reserved_at_200[0x5c0]; 2409 }; 2410 2411 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2412 u8 symbol_error_counter[0x10]; 2413 2414 u8 link_error_recovery_counter[0x8]; 2415 2416 u8 link_downed_counter[0x8]; 2417 2418 u8 port_rcv_errors[0x10]; 2419 2420 u8 port_rcv_remote_physical_errors[0x10]; 2421 2422 u8 port_rcv_switch_relay_errors[0x10]; 2423 2424 u8 port_xmit_discards[0x10]; 2425 2426 u8 port_xmit_constraint_errors[0x8]; 2427 2428 u8 port_rcv_constraint_errors[0x8]; 2429 2430 u8 reserved_at_70[0x8]; 2431 2432 u8 link_overrun_errors[0x8]; 2433 2434 u8 reserved_at_80[0x10]; 2435 2436 u8 vl_15_dropped[0x10]; 2437 2438 u8 reserved_at_a0[0x80]; 2439 2440 u8 port_xmit_wait[0x20]; 2441 }; 2442 2443 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2444 u8 transmit_queue_high[0x20]; 2445 2446 u8 transmit_queue_low[0x20]; 2447 2448 u8 no_buffer_discard_uc_high[0x20]; 2449 2450 u8 no_buffer_discard_uc_low[0x20]; 2451 2452 u8 reserved_at_80[0x740]; 2453 }; 2454 2455 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2456 u8 wred_discard_high[0x20]; 2457 2458 u8 wred_discard_low[0x20]; 2459 2460 u8 ecn_marked_tc_high[0x20]; 2461 2462 u8 ecn_marked_tc_low[0x20]; 2463 2464 u8 reserved_at_80[0x740]; 2465 }; 2466 2467 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2468 u8 rx_octets_high[0x20]; 2469 2470 u8 rx_octets_low[0x20]; 2471 2472 u8 reserved_at_40[0xc0]; 2473 2474 u8 rx_frames_high[0x20]; 2475 2476 u8 rx_frames_low[0x20]; 2477 2478 u8 tx_octets_high[0x20]; 2479 2480 u8 tx_octets_low[0x20]; 2481 2482 u8 reserved_at_180[0xc0]; 2483 2484 u8 tx_frames_high[0x20]; 2485 2486 u8 tx_frames_low[0x20]; 2487 2488 u8 rx_pause_high[0x20]; 2489 2490 u8 rx_pause_low[0x20]; 2491 2492 u8 rx_pause_duration_high[0x20]; 2493 2494 u8 rx_pause_duration_low[0x20]; 2495 2496 u8 tx_pause_high[0x20]; 2497 2498 u8 tx_pause_low[0x20]; 2499 2500 u8 tx_pause_duration_high[0x20]; 2501 2502 u8 tx_pause_duration_low[0x20]; 2503 2504 u8 rx_pause_transition_high[0x20]; 2505 2506 u8 rx_pause_transition_low[0x20]; 2507 2508 u8 rx_discards_high[0x20]; 2509 2510 u8 rx_discards_low[0x20]; 2511 2512 u8 device_stall_minor_watermark_cnt_high[0x20]; 2513 2514 u8 device_stall_minor_watermark_cnt_low[0x20]; 2515 2516 u8 device_stall_critical_watermark_cnt_high[0x20]; 2517 2518 u8 device_stall_critical_watermark_cnt_low[0x20]; 2519 2520 u8 reserved_at_480[0x340]; 2521 }; 2522 2523 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2524 u8 port_transmit_wait_high[0x20]; 2525 2526 u8 port_transmit_wait_low[0x20]; 2527 2528 u8 reserved_at_40[0x100]; 2529 2530 u8 rx_buffer_almost_full_high[0x20]; 2531 2532 u8 rx_buffer_almost_full_low[0x20]; 2533 2534 u8 rx_buffer_full_high[0x20]; 2535 2536 u8 rx_buffer_full_low[0x20]; 2537 2538 u8 rx_icrc_encapsulated_high[0x20]; 2539 2540 u8 rx_icrc_encapsulated_low[0x20]; 2541 2542 u8 reserved_at_200[0x5c0]; 2543 }; 2544 2545 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2546 u8 dot3stats_alignment_errors_high[0x20]; 2547 2548 u8 dot3stats_alignment_errors_low[0x20]; 2549 2550 u8 dot3stats_fcs_errors_high[0x20]; 2551 2552 u8 dot3stats_fcs_errors_low[0x20]; 2553 2554 u8 dot3stats_single_collision_frames_high[0x20]; 2555 2556 u8 dot3stats_single_collision_frames_low[0x20]; 2557 2558 u8 dot3stats_multiple_collision_frames_high[0x20]; 2559 2560 u8 dot3stats_multiple_collision_frames_low[0x20]; 2561 2562 u8 dot3stats_sqe_test_errors_high[0x20]; 2563 2564 u8 dot3stats_sqe_test_errors_low[0x20]; 2565 2566 u8 dot3stats_deferred_transmissions_high[0x20]; 2567 2568 u8 dot3stats_deferred_transmissions_low[0x20]; 2569 2570 u8 dot3stats_late_collisions_high[0x20]; 2571 2572 u8 dot3stats_late_collisions_low[0x20]; 2573 2574 u8 dot3stats_excessive_collisions_high[0x20]; 2575 2576 u8 dot3stats_excessive_collisions_low[0x20]; 2577 2578 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2579 2580 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2581 2582 u8 dot3stats_carrier_sense_errors_high[0x20]; 2583 2584 u8 dot3stats_carrier_sense_errors_low[0x20]; 2585 2586 u8 dot3stats_frame_too_longs_high[0x20]; 2587 2588 u8 dot3stats_frame_too_longs_low[0x20]; 2589 2590 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2591 2592 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2593 2594 u8 dot3stats_symbol_errors_high[0x20]; 2595 2596 u8 dot3stats_symbol_errors_low[0x20]; 2597 2598 u8 dot3control_in_unknown_opcodes_high[0x20]; 2599 2600 u8 dot3control_in_unknown_opcodes_low[0x20]; 2601 2602 u8 dot3in_pause_frames_high[0x20]; 2603 2604 u8 dot3in_pause_frames_low[0x20]; 2605 2606 u8 dot3out_pause_frames_high[0x20]; 2607 2608 u8 dot3out_pause_frames_low[0x20]; 2609 2610 u8 reserved_at_400[0x3c0]; 2611 }; 2612 2613 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2614 u8 ether_stats_drop_events_high[0x20]; 2615 2616 u8 ether_stats_drop_events_low[0x20]; 2617 2618 u8 ether_stats_octets_high[0x20]; 2619 2620 u8 ether_stats_octets_low[0x20]; 2621 2622 u8 ether_stats_pkts_high[0x20]; 2623 2624 u8 ether_stats_pkts_low[0x20]; 2625 2626 u8 ether_stats_broadcast_pkts_high[0x20]; 2627 2628 u8 ether_stats_broadcast_pkts_low[0x20]; 2629 2630 u8 ether_stats_multicast_pkts_high[0x20]; 2631 2632 u8 ether_stats_multicast_pkts_low[0x20]; 2633 2634 u8 ether_stats_crc_align_errors_high[0x20]; 2635 2636 u8 ether_stats_crc_align_errors_low[0x20]; 2637 2638 u8 ether_stats_undersize_pkts_high[0x20]; 2639 2640 u8 ether_stats_undersize_pkts_low[0x20]; 2641 2642 u8 ether_stats_oversize_pkts_high[0x20]; 2643 2644 u8 ether_stats_oversize_pkts_low[0x20]; 2645 2646 u8 ether_stats_fragments_high[0x20]; 2647 2648 u8 ether_stats_fragments_low[0x20]; 2649 2650 u8 ether_stats_jabbers_high[0x20]; 2651 2652 u8 ether_stats_jabbers_low[0x20]; 2653 2654 u8 ether_stats_collisions_high[0x20]; 2655 2656 u8 ether_stats_collisions_low[0x20]; 2657 2658 u8 ether_stats_pkts64octets_high[0x20]; 2659 2660 u8 ether_stats_pkts64octets_low[0x20]; 2661 2662 u8 ether_stats_pkts65to127octets_high[0x20]; 2663 2664 u8 ether_stats_pkts65to127octets_low[0x20]; 2665 2666 u8 ether_stats_pkts128to255octets_high[0x20]; 2667 2668 u8 ether_stats_pkts128to255octets_low[0x20]; 2669 2670 u8 ether_stats_pkts256to511octets_high[0x20]; 2671 2672 u8 ether_stats_pkts256to511octets_low[0x20]; 2673 2674 u8 ether_stats_pkts512to1023octets_high[0x20]; 2675 2676 u8 ether_stats_pkts512to1023octets_low[0x20]; 2677 2678 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2679 2680 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2681 2682 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2683 2684 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2685 2686 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2687 2688 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2689 2690 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2691 2692 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2693 2694 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2695 2696 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2697 2698 u8 reserved_at_540[0x280]; 2699 }; 2700 2701 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2702 u8 if_in_octets_high[0x20]; 2703 2704 u8 if_in_octets_low[0x20]; 2705 2706 u8 if_in_ucast_pkts_high[0x20]; 2707 2708 u8 if_in_ucast_pkts_low[0x20]; 2709 2710 u8 if_in_discards_high[0x20]; 2711 2712 u8 if_in_discards_low[0x20]; 2713 2714 u8 if_in_errors_high[0x20]; 2715 2716 u8 if_in_errors_low[0x20]; 2717 2718 u8 if_in_unknown_protos_high[0x20]; 2719 2720 u8 if_in_unknown_protos_low[0x20]; 2721 2722 u8 if_out_octets_high[0x20]; 2723 2724 u8 if_out_octets_low[0x20]; 2725 2726 u8 if_out_ucast_pkts_high[0x20]; 2727 2728 u8 if_out_ucast_pkts_low[0x20]; 2729 2730 u8 if_out_discards_high[0x20]; 2731 2732 u8 if_out_discards_low[0x20]; 2733 2734 u8 if_out_errors_high[0x20]; 2735 2736 u8 if_out_errors_low[0x20]; 2737 2738 u8 if_in_multicast_pkts_high[0x20]; 2739 2740 u8 if_in_multicast_pkts_low[0x20]; 2741 2742 u8 if_in_broadcast_pkts_high[0x20]; 2743 2744 u8 if_in_broadcast_pkts_low[0x20]; 2745 2746 u8 if_out_multicast_pkts_high[0x20]; 2747 2748 u8 if_out_multicast_pkts_low[0x20]; 2749 2750 u8 if_out_broadcast_pkts_high[0x20]; 2751 2752 u8 if_out_broadcast_pkts_low[0x20]; 2753 2754 u8 reserved_at_340[0x480]; 2755 }; 2756 2757 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2758 u8 a_frames_transmitted_ok_high[0x20]; 2759 2760 u8 a_frames_transmitted_ok_low[0x20]; 2761 2762 u8 a_frames_received_ok_high[0x20]; 2763 2764 u8 a_frames_received_ok_low[0x20]; 2765 2766 u8 a_frame_check_sequence_errors_high[0x20]; 2767 2768 u8 a_frame_check_sequence_errors_low[0x20]; 2769 2770 u8 a_alignment_errors_high[0x20]; 2771 2772 u8 a_alignment_errors_low[0x20]; 2773 2774 u8 a_octets_transmitted_ok_high[0x20]; 2775 2776 u8 a_octets_transmitted_ok_low[0x20]; 2777 2778 u8 a_octets_received_ok_high[0x20]; 2779 2780 u8 a_octets_received_ok_low[0x20]; 2781 2782 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2783 2784 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2785 2786 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2787 2788 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2789 2790 u8 a_multicast_frames_received_ok_high[0x20]; 2791 2792 u8 a_multicast_frames_received_ok_low[0x20]; 2793 2794 u8 a_broadcast_frames_received_ok_high[0x20]; 2795 2796 u8 a_broadcast_frames_received_ok_low[0x20]; 2797 2798 u8 a_in_range_length_errors_high[0x20]; 2799 2800 u8 a_in_range_length_errors_low[0x20]; 2801 2802 u8 a_out_of_range_length_field_high[0x20]; 2803 2804 u8 a_out_of_range_length_field_low[0x20]; 2805 2806 u8 a_frame_too_long_errors_high[0x20]; 2807 2808 u8 a_frame_too_long_errors_low[0x20]; 2809 2810 u8 a_symbol_error_during_carrier_high[0x20]; 2811 2812 u8 a_symbol_error_during_carrier_low[0x20]; 2813 2814 u8 a_mac_control_frames_transmitted_high[0x20]; 2815 2816 u8 a_mac_control_frames_transmitted_low[0x20]; 2817 2818 u8 a_mac_control_frames_received_high[0x20]; 2819 2820 u8 a_mac_control_frames_received_low[0x20]; 2821 2822 u8 a_unsupported_opcodes_received_high[0x20]; 2823 2824 u8 a_unsupported_opcodes_received_low[0x20]; 2825 2826 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2827 2828 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2829 2830 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2831 2832 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2833 2834 u8 reserved_at_4c0[0x300]; 2835 }; 2836 2837 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2838 u8 life_time_counter_high[0x20]; 2839 2840 u8 life_time_counter_low[0x20]; 2841 2842 u8 rx_errors[0x20]; 2843 2844 u8 tx_errors[0x20]; 2845 2846 u8 l0_to_recovery_eieos[0x20]; 2847 2848 u8 l0_to_recovery_ts[0x20]; 2849 2850 u8 l0_to_recovery_framing[0x20]; 2851 2852 u8 l0_to_recovery_retrain[0x20]; 2853 2854 u8 crc_error_dllp[0x20]; 2855 2856 u8 crc_error_tlp[0x20]; 2857 2858 u8 tx_overflow_buffer_pkt_high[0x20]; 2859 2860 u8 tx_overflow_buffer_pkt_low[0x20]; 2861 2862 u8 outbound_stalled_reads[0x20]; 2863 2864 u8 outbound_stalled_writes[0x20]; 2865 2866 u8 outbound_stalled_reads_events[0x20]; 2867 2868 u8 outbound_stalled_writes_events[0x20]; 2869 2870 u8 reserved_at_200[0x5c0]; 2871 }; 2872 2873 struct mlx5_ifc_cmd_inter_comp_event_bits { 2874 u8 command_completion_vector[0x20]; 2875 2876 u8 reserved_at_20[0xc0]; 2877 }; 2878 2879 struct mlx5_ifc_stall_vl_event_bits { 2880 u8 reserved_at_0[0x18]; 2881 u8 port_num[0x1]; 2882 u8 reserved_at_19[0x3]; 2883 u8 vl[0x4]; 2884 2885 u8 reserved_at_20[0xa0]; 2886 }; 2887 2888 struct mlx5_ifc_db_bf_congestion_event_bits { 2889 u8 event_subtype[0x8]; 2890 u8 reserved_at_8[0x8]; 2891 u8 congestion_level[0x8]; 2892 u8 reserved_at_18[0x8]; 2893 2894 u8 reserved_at_20[0xa0]; 2895 }; 2896 2897 struct mlx5_ifc_gpio_event_bits { 2898 u8 reserved_at_0[0x60]; 2899 2900 u8 gpio_event_hi[0x20]; 2901 2902 u8 gpio_event_lo[0x20]; 2903 2904 u8 reserved_at_a0[0x40]; 2905 }; 2906 2907 struct mlx5_ifc_port_state_change_event_bits { 2908 u8 reserved_at_0[0x40]; 2909 2910 u8 port_num[0x4]; 2911 u8 reserved_at_44[0x1c]; 2912 2913 u8 reserved_at_60[0x80]; 2914 }; 2915 2916 struct mlx5_ifc_dropped_packet_logged_bits { 2917 u8 reserved_at_0[0xe0]; 2918 }; 2919 2920 struct mlx5_ifc_default_timeout_bits { 2921 u8 to_multiplier[0x3]; 2922 u8 reserved_at_3[0x9]; 2923 u8 to_value[0x14]; 2924 }; 2925 2926 struct mlx5_ifc_dtor_reg_bits { 2927 u8 reserved_at_0[0x20]; 2928 2929 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2930 2931 u8 reserved_at_40[0x60]; 2932 2933 struct mlx5_ifc_default_timeout_bits health_poll_to; 2934 2935 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2936 2937 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2938 2939 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2940 2941 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2942 2943 struct mlx5_ifc_default_timeout_bits tear_down_to; 2944 2945 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2946 2947 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2948 2949 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2950 2951 u8 reserved_at_1c0[0x40]; 2952 }; 2953 2954 enum { 2955 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2956 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2957 }; 2958 2959 struct mlx5_ifc_cq_error_bits { 2960 u8 reserved_at_0[0x8]; 2961 u8 cqn[0x18]; 2962 2963 u8 reserved_at_20[0x20]; 2964 2965 u8 reserved_at_40[0x18]; 2966 u8 syndrome[0x8]; 2967 2968 u8 reserved_at_60[0x80]; 2969 }; 2970 2971 struct mlx5_ifc_rdma_page_fault_event_bits { 2972 u8 bytes_committed[0x20]; 2973 2974 u8 r_key[0x20]; 2975 2976 u8 reserved_at_40[0x10]; 2977 u8 packet_len[0x10]; 2978 2979 u8 rdma_op_len[0x20]; 2980 2981 u8 rdma_va[0x40]; 2982 2983 u8 reserved_at_c0[0x5]; 2984 u8 rdma[0x1]; 2985 u8 write[0x1]; 2986 u8 requestor[0x1]; 2987 u8 qp_number[0x18]; 2988 }; 2989 2990 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2991 u8 bytes_committed[0x20]; 2992 2993 u8 reserved_at_20[0x10]; 2994 u8 wqe_index[0x10]; 2995 2996 u8 reserved_at_40[0x10]; 2997 u8 len[0x10]; 2998 2999 u8 reserved_at_60[0x60]; 3000 3001 u8 reserved_at_c0[0x5]; 3002 u8 rdma[0x1]; 3003 u8 write_read[0x1]; 3004 u8 requestor[0x1]; 3005 u8 qpn[0x18]; 3006 }; 3007 3008 struct mlx5_ifc_qp_events_bits { 3009 u8 reserved_at_0[0xa0]; 3010 3011 u8 type[0x8]; 3012 u8 reserved_at_a8[0x18]; 3013 3014 u8 reserved_at_c0[0x8]; 3015 u8 qpn_rqn_sqn[0x18]; 3016 }; 3017 3018 struct mlx5_ifc_dct_events_bits { 3019 u8 reserved_at_0[0xc0]; 3020 3021 u8 reserved_at_c0[0x8]; 3022 u8 dct_number[0x18]; 3023 }; 3024 3025 struct mlx5_ifc_comp_event_bits { 3026 u8 reserved_at_0[0xc0]; 3027 3028 u8 reserved_at_c0[0x8]; 3029 u8 cq_number[0x18]; 3030 }; 3031 3032 enum { 3033 MLX5_QPC_STATE_RST = 0x0, 3034 MLX5_QPC_STATE_INIT = 0x1, 3035 MLX5_QPC_STATE_RTR = 0x2, 3036 MLX5_QPC_STATE_RTS = 0x3, 3037 MLX5_QPC_STATE_SQER = 0x4, 3038 MLX5_QPC_STATE_ERR = 0x6, 3039 MLX5_QPC_STATE_SQD = 0x7, 3040 MLX5_QPC_STATE_SUSPENDED = 0x9, 3041 }; 3042 3043 enum { 3044 MLX5_QPC_ST_RC = 0x0, 3045 MLX5_QPC_ST_UC = 0x1, 3046 MLX5_QPC_ST_UD = 0x2, 3047 MLX5_QPC_ST_XRC = 0x3, 3048 MLX5_QPC_ST_DCI = 0x5, 3049 MLX5_QPC_ST_QP0 = 0x7, 3050 MLX5_QPC_ST_QP1 = 0x8, 3051 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3052 MLX5_QPC_ST_REG_UMR = 0xc, 3053 }; 3054 3055 enum { 3056 MLX5_QPC_PM_STATE_ARMED = 0x0, 3057 MLX5_QPC_PM_STATE_REARM = 0x1, 3058 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3059 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3060 }; 3061 3062 enum { 3063 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3064 }; 3065 3066 enum { 3067 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3068 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3069 }; 3070 3071 enum { 3072 MLX5_QPC_MTU_256_BYTES = 0x1, 3073 MLX5_QPC_MTU_512_BYTES = 0x2, 3074 MLX5_QPC_MTU_1K_BYTES = 0x3, 3075 MLX5_QPC_MTU_2K_BYTES = 0x4, 3076 MLX5_QPC_MTU_4K_BYTES = 0x5, 3077 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3078 }; 3079 3080 enum { 3081 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3082 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3083 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3084 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3085 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3086 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3087 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3088 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3089 }; 3090 3091 enum { 3092 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3093 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3094 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3095 }; 3096 3097 enum { 3098 MLX5_QPC_CS_RES_DISABLE = 0x0, 3099 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3100 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3101 }; 3102 3103 enum { 3104 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3105 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3106 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3107 }; 3108 3109 struct mlx5_ifc_qpc_bits { 3110 u8 state[0x4]; 3111 u8 lag_tx_port_affinity[0x4]; 3112 u8 st[0x8]; 3113 u8 reserved_at_10[0x2]; 3114 u8 isolate_vl_tc[0x1]; 3115 u8 pm_state[0x2]; 3116 u8 reserved_at_15[0x1]; 3117 u8 req_e2e_credit_mode[0x2]; 3118 u8 offload_type[0x4]; 3119 u8 end_padding_mode[0x2]; 3120 u8 reserved_at_1e[0x2]; 3121 3122 u8 wq_signature[0x1]; 3123 u8 block_lb_mc[0x1]; 3124 u8 atomic_like_write_en[0x1]; 3125 u8 latency_sensitive[0x1]; 3126 u8 reserved_at_24[0x1]; 3127 u8 drain_sigerr[0x1]; 3128 u8 reserved_at_26[0x2]; 3129 u8 pd[0x18]; 3130 3131 u8 mtu[0x3]; 3132 u8 log_msg_max[0x5]; 3133 u8 reserved_at_48[0x1]; 3134 u8 log_rq_size[0x4]; 3135 u8 log_rq_stride[0x3]; 3136 u8 no_sq[0x1]; 3137 u8 log_sq_size[0x4]; 3138 u8 reserved_at_55[0x3]; 3139 u8 ts_format[0x2]; 3140 u8 reserved_at_5a[0x1]; 3141 u8 rlky[0x1]; 3142 u8 ulp_stateless_offload_mode[0x4]; 3143 3144 u8 counter_set_id[0x8]; 3145 u8 uar_page[0x18]; 3146 3147 u8 reserved_at_80[0x8]; 3148 u8 user_index[0x18]; 3149 3150 u8 reserved_at_a0[0x3]; 3151 u8 log_page_size[0x5]; 3152 u8 remote_qpn[0x18]; 3153 3154 struct mlx5_ifc_ads_bits primary_address_path; 3155 3156 struct mlx5_ifc_ads_bits secondary_address_path; 3157 3158 u8 log_ack_req_freq[0x4]; 3159 u8 reserved_at_384[0x4]; 3160 u8 log_sra_max[0x3]; 3161 u8 reserved_at_38b[0x2]; 3162 u8 retry_count[0x3]; 3163 u8 rnr_retry[0x3]; 3164 u8 reserved_at_393[0x1]; 3165 u8 fre[0x1]; 3166 u8 cur_rnr_retry[0x3]; 3167 u8 cur_retry_count[0x3]; 3168 u8 reserved_at_39b[0x5]; 3169 3170 u8 reserved_at_3a0[0x20]; 3171 3172 u8 reserved_at_3c0[0x8]; 3173 u8 next_send_psn[0x18]; 3174 3175 u8 reserved_at_3e0[0x3]; 3176 u8 log_num_dci_stream_channels[0x5]; 3177 u8 cqn_snd[0x18]; 3178 3179 u8 reserved_at_400[0x3]; 3180 u8 log_num_dci_errored_streams[0x5]; 3181 u8 deth_sqpn[0x18]; 3182 3183 u8 reserved_at_420[0x20]; 3184 3185 u8 reserved_at_440[0x8]; 3186 u8 last_acked_psn[0x18]; 3187 3188 u8 reserved_at_460[0x8]; 3189 u8 ssn[0x18]; 3190 3191 u8 reserved_at_480[0x8]; 3192 u8 log_rra_max[0x3]; 3193 u8 reserved_at_48b[0x1]; 3194 u8 atomic_mode[0x4]; 3195 u8 rre[0x1]; 3196 u8 rwe[0x1]; 3197 u8 rae[0x1]; 3198 u8 reserved_at_493[0x1]; 3199 u8 page_offset[0x6]; 3200 u8 reserved_at_49a[0x3]; 3201 u8 cd_slave_receive[0x1]; 3202 u8 cd_slave_send[0x1]; 3203 u8 cd_master[0x1]; 3204 3205 u8 reserved_at_4a0[0x3]; 3206 u8 min_rnr_nak[0x5]; 3207 u8 next_rcv_psn[0x18]; 3208 3209 u8 reserved_at_4c0[0x8]; 3210 u8 xrcd[0x18]; 3211 3212 u8 reserved_at_4e0[0x8]; 3213 u8 cqn_rcv[0x18]; 3214 3215 u8 dbr_addr[0x40]; 3216 3217 u8 q_key[0x20]; 3218 3219 u8 reserved_at_560[0x5]; 3220 u8 rq_type[0x3]; 3221 u8 srqn_rmpn_xrqn[0x18]; 3222 3223 u8 reserved_at_580[0x8]; 3224 u8 rmsn[0x18]; 3225 3226 u8 hw_sq_wqebb_counter[0x10]; 3227 u8 sw_sq_wqebb_counter[0x10]; 3228 3229 u8 hw_rq_counter[0x20]; 3230 3231 u8 sw_rq_counter[0x20]; 3232 3233 u8 reserved_at_600[0x20]; 3234 3235 u8 reserved_at_620[0xf]; 3236 u8 cgs[0x1]; 3237 u8 cs_req[0x8]; 3238 u8 cs_res[0x8]; 3239 3240 u8 dc_access_key[0x40]; 3241 3242 u8 reserved_at_680[0x3]; 3243 u8 dbr_umem_valid[0x1]; 3244 3245 u8 reserved_at_684[0xbc]; 3246 }; 3247 3248 struct mlx5_ifc_roce_addr_layout_bits { 3249 u8 source_l3_address[16][0x8]; 3250 3251 u8 reserved_at_80[0x3]; 3252 u8 vlan_valid[0x1]; 3253 u8 vlan_id[0xc]; 3254 u8 source_mac_47_32[0x10]; 3255 3256 u8 source_mac_31_0[0x20]; 3257 3258 u8 reserved_at_c0[0x14]; 3259 u8 roce_l3_type[0x4]; 3260 u8 roce_version[0x8]; 3261 3262 u8 reserved_at_e0[0x20]; 3263 }; 3264 3265 struct mlx5_ifc_shampo_cap_bits { 3266 u8 reserved_at_0[0x3]; 3267 u8 shampo_log_max_reservation_size[0x5]; 3268 u8 reserved_at_8[0x3]; 3269 u8 shampo_log_min_reservation_size[0x5]; 3270 u8 shampo_min_mss_size[0x10]; 3271 3272 u8 reserved_at_20[0x3]; 3273 u8 shampo_max_log_headers_entry_size[0x5]; 3274 u8 reserved_at_28[0x18]; 3275 3276 u8 reserved_at_40[0x7c0]; 3277 }; 3278 3279 union mlx5_ifc_hca_cap_union_bits { 3280 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3281 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3282 struct mlx5_ifc_odp_cap_bits odp_cap; 3283 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3284 struct mlx5_ifc_roce_cap_bits roce_cap; 3285 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3286 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3287 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3288 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3289 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3290 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3291 struct mlx5_ifc_qos_cap_bits qos_cap; 3292 struct mlx5_ifc_debug_cap_bits debug_cap; 3293 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3294 struct mlx5_ifc_tls_cap_bits tls_cap; 3295 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3296 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3297 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3298 u8 reserved_at_0[0x8000]; 3299 }; 3300 3301 enum { 3302 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3303 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3304 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3305 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3306 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3307 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3308 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3309 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3310 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3311 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3312 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3313 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3314 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3315 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3316 }; 3317 3318 enum { 3319 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3320 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3321 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3322 }; 3323 3324 struct mlx5_ifc_vlan_bits { 3325 u8 ethtype[0x10]; 3326 u8 prio[0x3]; 3327 u8 cfi[0x1]; 3328 u8 vid[0xc]; 3329 }; 3330 3331 enum { 3332 MLX5_FLOW_METER_COLOR_RED = 0x0, 3333 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3334 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3335 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3336 }; 3337 3338 enum { 3339 MLX5_EXE_ASO_FLOW_METER = 0x2, 3340 }; 3341 3342 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3343 u8 return_reg_id[0x4]; 3344 u8 aso_type[0x4]; 3345 u8 reserved_at_8[0x14]; 3346 u8 action[0x1]; 3347 u8 init_color[0x2]; 3348 u8 meter_id[0x1]; 3349 }; 3350 3351 union mlx5_ifc_exe_aso_ctrl { 3352 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3353 }; 3354 3355 struct mlx5_ifc_execute_aso_bits { 3356 u8 valid[0x1]; 3357 u8 reserved_at_1[0x7]; 3358 u8 aso_object_id[0x18]; 3359 3360 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3361 }; 3362 3363 struct mlx5_ifc_flow_context_bits { 3364 struct mlx5_ifc_vlan_bits push_vlan; 3365 3366 u8 group_id[0x20]; 3367 3368 u8 reserved_at_40[0x8]; 3369 u8 flow_tag[0x18]; 3370 3371 u8 reserved_at_60[0x10]; 3372 u8 action[0x10]; 3373 3374 u8 extended_destination[0x1]; 3375 u8 reserved_at_81[0x1]; 3376 u8 flow_source[0x2]; 3377 u8 reserved_at_84[0x4]; 3378 u8 destination_list_size[0x18]; 3379 3380 u8 reserved_at_a0[0x8]; 3381 u8 flow_counter_list_size[0x18]; 3382 3383 u8 packet_reformat_id[0x20]; 3384 3385 u8 modify_header_id[0x20]; 3386 3387 struct mlx5_ifc_vlan_bits push_vlan_2; 3388 3389 u8 ipsec_obj_id[0x20]; 3390 u8 reserved_at_140[0xc0]; 3391 3392 struct mlx5_ifc_fte_match_param_bits match_value; 3393 3394 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3395 3396 u8 reserved_at_1300[0x500]; 3397 3398 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3399 }; 3400 3401 enum { 3402 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3403 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3404 }; 3405 3406 struct mlx5_ifc_xrc_srqc_bits { 3407 u8 state[0x4]; 3408 u8 log_xrc_srq_size[0x4]; 3409 u8 reserved_at_8[0x18]; 3410 3411 u8 wq_signature[0x1]; 3412 u8 cont_srq[0x1]; 3413 u8 reserved_at_22[0x1]; 3414 u8 rlky[0x1]; 3415 u8 basic_cyclic_rcv_wqe[0x1]; 3416 u8 log_rq_stride[0x3]; 3417 u8 xrcd[0x18]; 3418 3419 u8 page_offset[0x6]; 3420 u8 reserved_at_46[0x1]; 3421 u8 dbr_umem_valid[0x1]; 3422 u8 cqn[0x18]; 3423 3424 u8 reserved_at_60[0x20]; 3425 3426 u8 user_index_equal_xrc_srqn[0x1]; 3427 u8 reserved_at_81[0x1]; 3428 u8 log_page_size[0x6]; 3429 u8 user_index[0x18]; 3430 3431 u8 reserved_at_a0[0x20]; 3432 3433 u8 reserved_at_c0[0x8]; 3434 u8 pd[0x18]; 3435 3436 u8 lwm[0x10]; 3437 u8 wqe_cnt[0x10]; 3438 3439 u8 reserved_at_100[0x40]; 3440 3441 u8 db_record_addr_h[0x20]; 3442 3443 u8 db_record_addr_l[0x1e]; 3444 u8 reserved_at_17e[0x2]; 3445 3446 u8 reserved_at_180[0x80]; 3447 }; 3448 3449 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3450 u8 counter_error_queues[0x20]; 3451 3452 u8 total_error_queues[0x20]; 3453 3454 u8 send_queue_priority_update_flow[0x20]; 3455 3456 u8 reserved_at_60[0x20]; 3457 3458 u8 nic_receive_steering_discard[0x40]; 3459 3460 u8 receive_discard_vport_down[0x40]; 3461 3462 u8 transmit_discard_vport_down[0x40]; 3463 3464 u8 async_eq_overrun[0x20]; 3465 3466 u8 comp_eq_overrun[0x20]; 3467 3468 u8 reserved_at_180[0x20]; 3469 3470 u8 invalid_command[0x20]; 3471 3472 u8 quota_exceeded_command[0x20]; 3473 3474 u8 internal_rq_out_of_buffer[0x20]; 3475 3476 u8 cq_overrun[0x20]; 3477 3478 u8 reserved_at_220[0xde0]; 3479 }; 3480 3481 struct mlx5_ifc_traffic_counter_bits { 3482 u8 packets[0x40]; 3483 3484 u8 octets[0x40]; 3485 }; 3486 3487 struct mlx5_ifc_tisc_bits { 3488 u8 strict_lag_tx_port_affinity[0x1]; 3489 u8 tls_en[0x1]; 3490 u8 reserved_at_2[0x2]; 3491 u8 lag_tx_port_affinity[0x04]; 3492 3493 u8 reserved_at_8[0x4]; 3494 u8 prio[0x4]; 3495 u8 reserved_at_10[0x10]; 3496 3497 u8 reserved_at_20[0x100]; 3498 3499 u8 reserved_at_120[0x8]; 3500 u8 transport_domain[0x18]; 3501 3502 u8 reserved_at_140[0x8]; 3503 u8 underlay_qpn[0x18]; 3504 3505 u8 reserved_at_160[0x8]; 3506 u8 pd[0x18]; 3507 3508 u8 reserved_at_180[0x380]; 3509 }; 3510 3511 enum { 3512 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3513 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3514 }; 3515 3516 enum { 3517 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3518 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3519 }; 3520 3521 enum { 3522 MLX5_RX_HASH_FN_NONE = 0x0, 3523 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3524 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3525 }; 3526 3527 enum { 3528 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3529 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3530 }; 3531 3532 struct mlx5_ifc_tirc_bits { 3533 u8 reserved_at_0[0x20]; 3534 3535 u8 disp_type[0x4]; 3536 u8 tls_en[0x1]; 3537 u8 reserved_at_25[0x1b]; 3538 3539 u8 reserved_at_40[0x40]; 3540 3541 u8 reserved_at_80[0x4]; 3542 u8 lro_timeout_period_usecs[0x10]; 3543 u8 packet_merge_mask[0x4]; 3544 u8 lro_max_ip_payload_size[0x8]; 3545 3546 u8 reserved_at_a0[0x40]; 3547 3548 u8 reserved_at_e0[0x8]; 3549 u8 inline_rqn[0x18]; 3550 3551 u8 rx_hash_symmetric[0x1]; 3552 u8 reserved_at_101[0x1]; 3553 u8 tunneled_offload_en[0x1]; 3554 u8 reserved_at_103[0x5]; 3555 u8 indirect_table[0x18]; 3556 3557 u8 rx_hash_fn[0x4]; 3558 u8 reserved_at_124[0x2]; 3559 u8 self_lb_block[0x2]; 3560 u8 transport_domain[0x18]; 3561 3562 u8 rx_hash_toeplitz_key[10][0x20]; 3563 3564 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3565 3566 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3567 3568 u8 reserved_at_2c0[0x4c0]; 3569 }; 3570 3571 enum { 3572 MLX5_SRQC_STATE_GOOD = 0x0, 3573 MLX5_SRQC_STATE_ERROR = 0x1, 3574 }; 3575 3576 struct mlx5_ifc_srqc_bits { 3577 u8 state[0x4]; 3578 u8 log_srq_size[0x4]; 3579 u8 reserved_at_8[0x18]; 3580 3581 u8 wq_signature[0x1]; 3582 u8 cont_srq[0x1]; 3583 u8 reserved_at_22[0x1]; 3584 u8 rlky[0x1]; 3585 u8 reserved_at_24[0x1]; 3586 u8 log_rq_stride[0x3]; 3587 u8 xrcd[0x18]; 3588 3589 u8 page_offset[0x6]; 3590 u8 reserved_at_46[0x2]; 3591 u8 cqn[0x18]; 3592 3593 u8 reserved_at_60[0x20]; 3594 3595 u8 reserved_at_80[0x2]; 3596 u8 log_page_size[0x6]; 3597 u8 reserved_at_88[0x18]; 3598 3599 u8 reserved_at_a0[0x20]; 3600 3601 u8 reserved_at_c0[0x8]; 3602 u8 pd[0x18]; 3603 3604 u8 lwm[0x10]; 3605 u8 wqe_cnt[0x10]; 3606 3607 u8 reserved_at_100[0x40]; 3608 3609 u8 dbr_addr[0x40]; 3610 3611 u8 reserved_at_180[0x80]; 3612 }; 3613 3614 enum { 3615 MLX5_SQC_STATE_RST = 0x0, 3616 MLX5_SQC_STATE_RDY = 0x1, 3617 MLX5_SQC_STATE_ERR = 0x3, 3618 }; 3619 3620 struct mlx5_ifc_sqc_bits { 3621 u8 rlky[0x1]; 3622 u8 cd_master[0x1]; 3623 u8 fre[0x1]; 3624 u8 flush_in_error_en[0x1]; 3625 u8 allow_multi_pkt_send_wqe[0x1]; 3626 u8 min_wqe_inline_mode[0x3]; 3627 u8 state[0x4]; 3628 u8 reg_umr[0x1]; 3629 u8 allow_swp[0x1]; 3630 u8 hairpin[0x1]; 3631 u8 reserved_at_f[0xb]; 3632 u8 ts_format[0x2]; 3633 u8 reserved_at_1c[0x4]; 3634 3635 u8 reserved_at_20[0x8]; 3636 u8 user_index[0x18]; 3637 3638 u8 reserved_at_40[0x8]; 3639 u8 cqn[0x18]; 3640 3641 u8 reserved_at_60[0x8]; 3642 u8 hairpin_peer_rq[0x18]; 3643 3644 u8 reserved_at_80[0x10]; 3645 u8 hairpin_peer_vhca[0x10]; 3646 3647 u8 reserved_at_a0[0x20]; 3648 3649 u8 reserved_at_c0[0x8]; 3650 u8 ts_cqe_to_dest_cqn[0x18]; 3651 3652 u8 reserved_at_e0[0x10]; 3653 u8 packet_pacing_rate_limit_index[0x10]; 3654 u8 tis_lst_sz[0x10]; 3655 u8 qos_queue_group_id[0x10]; 3656 3657 u8 reserved_at_120[0x40]; 3658 3659 u8 reserved_at_160[0x8]; 3660 u8 tis_num_0[0x18]; 3661 3662 struct mlx5_ifc_wq_bits wq; 3663 }; 3664 3665 enum { 3666 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3667 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3668 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3669 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3670 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3671 }; 3672 3673 enum { 3674 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3675 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3676 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3677 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3678 }; 3679 3680 struct mlx5_ifc_scheduling_context_bits { 3681 u8 element_type[0x8]; 3682 u8 reserved_at_8[0x18]; 3683 3684 u8 element_attributes[0x20]; 3685 3686 u8 parent_element_id[0x20]; 3687 3688 u8 reserved_at_60[0x40]; 3689 3690 u8 bw_share[0x20]; 3691 3692 u8 max_average_bw[0x20]; 3693 3694 u8 reserved_at_e0[0x120]; 3695 }; 3696 3697 struct mlx5_ifc_rqtc_bits { 3698 u8 reserved_at_0[0xa0]; 3699 3700 u8 reserved_at_a0[0x5]; 3701 u8 list_q_type[0x3]; 3702 u8 reserved_at_a8[0x8]; 3703 u8 rqt_max_size[0x10]; 3704 3705 u8 rq_vhca_id_format[0x1]; 3706 u8 reserved_at_c1[0xf]; 3707 u8 rqt_actual_size[0x10]; 3708 3709 u8 reserved_at_e0[0x6a0]; 3710 3711 struct mlx5_ifc_rq_num_bits rq_num[]; 3712 }; 3713 3714 enum { 3715 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3716 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3717 }; 3718 3719 enum { 3720 MLX5_RQC_STATE_RST = 0x0, 3721 MLX5_RQC_STATE_RDY = 0x1, 3722 MLX5_RQC_STATE_ERR = 0x3, 3723 }; 3724 3725 enum { 3726 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3727 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3728 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3729 }; 3730 3731 enum { 3732 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3733 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3734 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3735 }; 3736 3737 struct mlx5_ifc_rqc_bits { 3738 u8 rlky[0x1]; 3739 u8 delay_drop_en[0x1]; 3740 u8 scatter_fcs[0x1]; 3741 u8 vsd[0x1]; 3742 u8 mem_rq_type[0x4]; 3743 u8 state[0x4]; 3744 u8 reserved_at_c[0x1]; 3745 u8 flush_in_error_en[0x1]; 3746 u8 hairpin[0x1]; 3747 u8 reserved_at_f[0xb]; 3748 u8 ts_format[0x2]; 3749 u8 reserved_at_1c[0x4]; 3750 3751 u8 reserved_at_20[0x8]; 3752 u8 user_index[0x18]; 3753 3754 u8 reserved_at_40[0x8]; 3755 u8 cqn[0x18]; 3756 3757 u8 counter_set_id[0x8]; 3758 u8 reserved_at_68[0x18]; 3759 3760 u8 reserved_at_80[0x8]; 3761 u8 rmpn[0x18]; 3762 3763 u8 reserved_at_a0[0x8]; 3764 u8 hairpin_peer_sq[0x18]; 3765 3766 u8 reserved_at_c0[0x10]; 3767 u8 hairpin_peer_vhca[0x10]; 3768 3769 u8 reserved_at_e0[0x46]; 3770 u8 shampo_no_match_alignment_granularity[0x2]; 3771 u8 reserved_at_128[0x6]; 3772 u8 shampo_match_criteria_type[0x2]; 3773 u8 reservation_timeout[0x10]; 3774 3775 u8 reserved_at_140[0x40]; 3776 3777 struct mlx5_ifc_wq_bits wq; 3778 }; 3779 3780 enum { 3781 MLX5_RMPC_STATE_RDY = 0x1, 3782 MLX5_RMPC_STATE_ERR = 0x3, 3783 }; 3784 3785 struct mlx5_ifc_rmpc_bits { 3786 u8 reserved_at_0[0x8]; 3787 u8 state[0x4]; 3788 u8 reserved_at_c[0x14]; 3789 3790 u8 basic_cyclic_rcv_wqe[0x1]; 3791 u8 reserved_at_21[0x1f]; 3792 3793 u8 reserved_at_40[0x140]; 3794 3795 struct mlx5_ifc_wq_bits wq; 3796 }; 3797 3798 enum { 3799 VHCA_ID_TYPE_HW = 0, 3800 VHCA_ID_TYPE_SW = 1, 3801 }; 3802 3803 struct mlx5_ifc_nic_vport_context_bits { 3804 u8 reserved_at_0[0x5]; 3805 u8 min_wqe_inline_mode[0x3]; 3806 u8 reserved_at_8[0x15]; 3807 u8 disable_mc_local_lb[0x1]; 3808 u8 disable_uc_local_lb[0x1]; 3809 u8 roce_en[0x1]; 3810 3811 u8 arm_change_event[0x1]; 3812 u8 reserved_at_21[0x1a]; 3813 u8 event_on_mtu[0x1]; 3814 u8 event_on_promisc_change[0x1]; 3815 u8 event_on_vlan_change[0x1]; 3816 u8 event_on_mc_address_change[0x1]; 3817 u8 event_on_uc_address_change[0x1]; 3818 3819 u8 vhca_id_type[0x1]; 3820 u8 reserved_at_41[0xb]; 3821 u8 affiliation_criteria[0x4]; 3822 u8 affiliated_vhca_id[0x10]; 3823 3824 u8 reserved_at_60[0xd0]; 3825 3826 u8 mtu[0x10]; 3827 3828 u8 system_image_guid[0x40]; 3829 u8 port_guid[0x40]; 3830 u8 node_guid[0x40]; 3831 3832 u8 reserved_at_200[0x140]; 3833 u8 qkey_violation_counter[0x10]; 3834 u8 reserved_at_350[0x430]; 3835 3836 u8 promisc_uc[0x1]; 3837 u8 promisc_mc[0x1]; 3838 u8 promisc_all[0x1]; 3839 u8 reserved_at_783[0x2]; 3840 u8 allowed_list_type[0x3]; 3841 u8 reserved_at_788[0xc]; 3842 u8 allowed_list_size[0xc]; 3843 3844 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3845 3846 u8 reserved_at_7e0[0x20]; 3847 3848 u8 current_uc_mac_address[][0x40]; 3849 }; 3850 3851 enum { 3852 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3853 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3854 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3855 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3856 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3857 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3858 }; 3859 3860 struct mlx5_ifc_mkc_bits { 3861 u8 reserved_at_0[0x1]; 3862 u8 free[0x1]; 3863 u8 reserved_at_2[0x1]; 3864 u8 access_mode_4_2[0x3]; 3865 u8 reserved_at_6[0x7]; 3866 u8 relaxed_ordering_write[0x1]; 3867 u8 reserved_at_e[0x1]; 3868 u8 small_fence_on_rdma_read_response[0x1]; 3869 u8 umr_en[0x1]; 3870 u8 a[0x1]; 3871 u8 rw[0x1]; 3872 u8 rr[0x1]; 3873 u8 lw[0x1]; 3874 u8 lr[0x1]; 3875 u8 access_mode_1_0[0x2]; 3876 u8 reserved_at_18[0x8]; 3877 3878 u8 qpn[0x18]; 3879 u8 mkey_7_0[0x8]; 3880 3881 u8 reserved_at_40[0x20]; 3882 3883 u8 length64[0x1]; 3884 u8 bsf_en[0x1]; 3885 u8 sync_umr[0x1]; 3886 u8 reserved_at_63[0x2]; 3887 u8 expected_sigerr_count[0x1]; 3888 u8 reserved_at_66[0x1]; 3889 u8 en_rinval[0x1]; 3890 u8 pd[0x18]; 3891 3892 u8 start_addr[0x40]; 3893 3894 u8 len[0x40]; 3895 3896 u8 bsf_octword_size[0x20]; 3897 3898 u8 reserved_at_120[0x80]; 3899 3900 u8 translations_octword_size[0x20]; 3901 3902 u8 reserved_at_1c0[0x19]; 3903 u8 relaxed_ordering_read[0x1]; 3904 u8 reserved_at_1d9[0x1]; 3905 u8 log_page_size[0x5]; 3906 3907 u8 reserved_at_1e0[0x20]; 3908 }; 3909 3910 struct mlx5_ifc_pkey_bits { 3911 u8 reserved_at_0[0x10]; 3912 u8 pkey[0x10]; 3913 }; 3914 3915 struct mlx5_ifc_array128_auto_bits { 3916 u8 array128_auto[16][0x8]; 3917 }; 3918 3919 struct mlx5_ifc_hca_vport_context_bits { 3920 u8 field_select[0x20]; 3921 3922 u8 reserved_at_20[0xe0]; 3923 3924 u8 sm_virt_aware[0x1]; 3925 u8 has_smi[0x1]; 3926 u8 has_raw[0x1]; 3927 u8 grh_required[0x1]; 3928 u8 reserved_at_104[0xc]; 3929 u8 port_physical_state[0x4]; 3930 u8 vport_state_policy[0x4]; 3931 u8 port_state[0x4]; 3932 u8 vport_state[0x4]; 3933 3934 u8 reserved_at_120[0x20]; 3935 3936 u8 system_image_guid[0x40]; 3937 3938 u8 port_guid[0x40]; 3939 3940 u8 node_guid[0x40]; 3941 3942 u8 cap_mask1[0x20]; 3943 3944 u8 cap_mask1_field_select[0x20]; 3945 3946 u8 cap_mask2[0x20]; 3947 3948 u8 cap_mask2_field_select[0x20]; 3949 3950 u8 reserved_at_280[0x80]; 3951 3952 u8 lid[0x10]; 3953 u8 reserved_at_310[0x4]; 3954 u8 init_type_reply[0x4]; 3955 u8 lmc[0x3]; 3956 u8 subnet_timeout[0x5]; 3957 3958 u8 sm_lid[0x10]; 3959 u8 sm_sl[0x4]; 3960 u8 reserved_at_334[0xc]; 3961 3962 u8 qkey_violation_counter[0x10]; 3963 u8 pkey_violation_counter[0x10]; 3964 3965 u8 reserved_at_360[0xca0]; 3966 }; 3967 3968 struct mlx5_ifc_esw_vport_context_bits { 3969 u8 fdb_to_vport_reg_c[0x1]; 3970 u8 reserved_at_1[0x2]; 3971 u8 vport_svlan_strip[0x1]; 3972 u8 vport_cvlan_strip[0x1]; 3973 u8 vport_svlan_insert[0x1]; 3974 u8 vport_cvlan_insert[0x2]; 3975 u8 fdb_to_vport_reg_c_id[0x8]; 3976 u8 reserved_at_10[0x10]; 3977 3978 u8 reserved_at_20[0x20]; 3979 3980 u8 svlan_cfi[0x1]; 3981 u8 svlan_pcp[0x3]; 3982 u8 svlan_id[0xc]; 3983 u8 cvlan_cfi[0x1]; 3984 u8 cvlan_pcp[0x3]; 3985 u8 cvlan_id[0xc]; 3986 3987 u8 reserved_at_60[0x720]; 3988 3989 u8 sw_steering_vport_icm_address_rx[0x40]; 3990 3991 u8 sw_steering_vport_icm_address_tx[0x40]; 3992 }; 3993 3994 enum { 3995 MLX5_EQC_STATUS_OK = 0x0, 3996 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3997 }; 3998 3999 enum { 4000 MLX5_EQC_ST_ARMED = 0x9, 4001 MLX5_EQC_ST_FIRED = 0xa, 4002 }; 4003 4004 struct mlx5_ifc_eqc_bits { 4005 u8 status[0x4]; 4006 u8 reserved_at_4[0x9]; 4007 u8 ec[0x1]; 4008 u8 oi[0x1]; 4009 u8 reserved_at_f[0x5]; 4010 u8 st[0x4]; 4011 u8 reserved_at_18[0x8]; 4012 4013 u8 reserved_at_20[0x20]; 4014 4015 u8 reserved_at_40[0x14]; 4016 u8 page_offset[0x6]; 4017 u8 reserved_at_5a[0x6]; 4018 4019 u8 reserved_at_60[0x3]; 4020 u8 log_eq_size[0x5]; 4021 u8 uar_page[0x18]; 4022 4023 u8 reserved_at_80[0x20]; 4024 4025 u8 reserved_at_a0[0x14]; 4026 u8 intr[0xc]; 4027 4028 u8 reserved_at_c0[0x3]; 4029 u8 log_page_size[0x5]; 4030 u8 reserved_at_c8[0x18]; 4031 4032 u8 reserved_at_e0[0x60]; 4033 4034 u8 reserved_at_140[0x8]; 4035 u8 consumer_counter[0x18]; 4036 4037 u8 reserved_at_160[0x8]; 4038 u8 producer_counter[0x18]; 4039 4040 u8 reserved_at_180[0x80]; 4041 }; 4042 4043 enum { 4044 MLX5_DCTC_STATE_ACTIVE = 0x0, 4045 MLX5_DCTC_STATE_DRAINING = 0x1, 4046 MLX5_DCTC_STATE_DRAINED = 0x2, 4047 }; 4048 4049 enum { 4050 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4051 MLX5_DCTC_CS_RES_NA = 0x1, 4052 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4053 }; 4054 4055 enum { 4056 MLX5_DCTC_MTU_256_BYTES = 0x1, 4057 MLX5_DCTC_MTU_512_BYTES = 0x2, 4058 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4059 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4060 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4061 }; 4062 4063 struct mlx5_ifc_dctc_bits { 4064 u8 reserved_at_0[0x4]; 4065 u8 state[0x4]; 4066 u8 reserved_at_8[0x18]; 4067 4068 u8 reserved_at_20[0x8]; 4069 u8 user_index[0x18]; 4070 4071 u8 reserved_at_40[0x8]; 4072 u8 cqn[0x18]; 4073 4074 u8 counter_set_id[0x8]; 4075 u8 atomic_mode[0x4]; 4076 u8 rre[0x1]; 4077 u8 rwe[0x1]; 4078 u8 rae[0x1]; 4079 u8 atomic_like_write_en[0x1]; 4080 u8 latency_sensitive[0x1]; 4081 u8 rlky[0x1]; 4082 u8 free_ar[0x1]; 4083 u8 reserved_at_73[0xd]; 4084 4085 u8 reserved_at_80[0x8]; 4086 u8 cs_res[0x8]; 4087 u8 reserved_at_90[0x3]; 4088 u8 min_rnr_nak[0x5]; 4089 u8 reserved_at_98[0x8]; 4090 4091 u8 reserved_at_a0[0x8]; 4092 u8 srqn_xrqn[0x18]; 4093 4094 u8 reserved_at_c0[0x8]; 4095 u8 pd[0x18]; 4096 4097 u8 tclass[0x8]; 4098 u8 reserved_at_e8[0x4]; 4099 u8 flow_label[0x14]; 4100 4101 u8 dc_access_key[0x40]; 4102 4103 u8 reserved_at_140[0x5]; 4104 u8 mtu[0x3]; 4105 u8 port[0x8]; 4106 u8 pkey_index[0x10]; 4107 4108 u8 reserved_at_160[0x8]; 4109 u8 my_addr_index[0x8]; 4110 u8 reserved_at_170[0x8]; 4111 u8 hop_limit[0x8]; 4112 4113 u8 dc_access_key_violation_count[0x20]; 4114 4115 u8 reserved_at_1a0[0x14]; 4116 u8 dei_cfi[0x1]; 4117 u8 eth_prio[0x3]; 4118 u8 ecn[0x2]; 4119 u8 dscp[0x6]; 4120 4121 u8 reserved_at_1c0[0x20]; 4122 u8 ece[0x20]; 4123 }; 4124 4125 enum { 4126 MLX5_CQC_STATUS_OK = 0x0, 4127 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4128 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4129 }; 4130 4131 enum { 4132 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4133 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4134 }; 4135 4136 enum { 4137 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4138 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4139 MLX5_CQC_ST_FIRED = 0xa, 4140 }; 4141 4142 enum { 4143 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4144 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4145 MLX5_CQ_PERIOD_NUM_MODES 4146 }; 4147 4148 struct mlx5_ifc_cqc_bits { 4149 u8 status[0x4]; 4150 u8 reserved_at_4[0x2]; 4151 u8 dbr_umem_valid[0x1]; 4152 u8 apu_cq[0x1]; 4153 u8 cqe_sz[0x3]; 4154 u8 cc[0x1]; 4155 u8 reserved_at_c[0x1]; 4156 u8 scqe_break_moderation_en[0x1]; 4157 u8 oi[0x1]; 4158 u8 cq_period_mode[0x2]; 4159 u8 cqe_comp_en[0x1]; 4160 u8 mini_cqe_res_format[0x2]; 4161 u8 st[0x4]; 4162 u8 reserved_at_18[0x6]; 4163 u8 cqe_compression_layout[0x2]; 4164 4165 u8 reserved_at_20[0x20]; 4166 4167 u8 reserved_at_40[0x14]; 4168 u8 page_offset[0x6]; 4169 u8 reserved_at_5a[0x6]; 4170 4171 u8 reserved_at_60[0x3]; 4172 u8 log_cq_size[0x5]; 4173 u8 uar_page[0x18]; 4174 4175 u8 reserved_at_80[0x4]; 4176 u8 cq_period[0xc]; 4177 u8 cq_max_count[0x10]; 4178 4179 u8 c_eqn_or_apu_element[0x20]; 4180 4181 u8 reserved_at_c0[0x3]; 4182 u8 log_page_size[0x5]; 4183 u8 reserved_at_c8[0x18]; 4184 4185 u8 reserved_at_e0[0x20]; 4186 4187 u8 reserved_at_100[0x8]; 4188 u8 last_notified_index[0x18]; 4189 4190 u8 reserved_at_120[0x8]; 4191 u8 last_solicit_index[0x18]; 4192 4193 u8 reserved_at_140[0x8]; 4194 u8 consumer_counter[0x18]; 4195 4196 u8 reserved_at_160[0x8]; 4197 u8 producer_counter[0x18]; 4198 4199 u8 reserved_at_180[0x40]; 4200 4201 u8 dbr_addr[0x40]; 4202 }; 4203 4204 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4205 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4206 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4207 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4208 u8 reserved_at_0[0x800]; 4209 }; 4210 4211 struct mlx5_ifc_query_adapter_param_block_bits { 4212 u8 reserved_at_0[0xc0]; 4213 4214 u8 reserved_at_c0[0x8]; 4215 u8 ieee_vendor_id[0x18]; 4216 4217 u8 reserved_at_e0[0x10]; 4218 u8 vsd_vendor_id[0x10]; 4219 4220 u8 vsd[208][0x8]; 4221 4222 u8 vsd_contd_psid[16][0x8]; 4223 }; 4224 4225 enum { 4226 MLX5_XRQC_STATE_GOOD = 0x0, 4227 MLX5_XRQC_STATE_ERROR = 0x1, 4228 }; 4229 4230 enum { 4231 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4232 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4233 }; 4234 4235 enum { 4236 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4237 }; 4238 4239 struct mlx5_ifc_tag_matching_topology_context_bits { 4240 u8 log_matching_list_sz[0x4]; 4241 u8 reserved_at_4[0xc]; 4242 u8 append_next_index[0x10]; 4243 4244 u8 sw_phase_cnt[0x10]; 4245 u8 hw_phase_cnt[0x10]; 4246 4247 u8 reserved_at_40[0x40]; 4248 }; 4249 4250 struct mlx5_ifc_xrqc_bits { 4251 u8 state[0x4]; 4252 u8 rlkey[0x1]; 4253 u8 reserved_at_5[0xf]; 4254 u8 topology[0x4]; 4255 u8 reserved_at_18[0x4]; 4256 u8 offload[0x4]; 4257 4258 u8 reserved_at_20[0x8]; 4259 u8 user_index[0x18]; 4260 4261 u8 reserved_at_40[0x8]; 4262 u8 cqn[0x18]; 4263 4264 u8 reserved_at_60[0xa0]; 4265 4266 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4267 4268 u8 reserved_at_180[0x280]; 4269 4270 struct mlx5_ifc_wq_bits wq; 4271 }; 4272 4273 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4274 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4275 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4276 u8 reserved_at_0[0x20]; 4277 }; 4278 4279 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4280 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4281 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4282 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4283 u8 reserved_at_0[0x20]; 4284 }; 4285 4286 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4287 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4288 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4289 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4290 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4291 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4292 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4293 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4294 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4295 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4296 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4297 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4298 u8 reserved_at_0[0x7c0]; 4299 }; 4300 4301 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4302 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4303 u8 reserved_at_0[0x7c0]; 4304 }; 4305 4306 union mlx5_ifc_event_auto_bits { 4307 struct mlx5_ifc_comp_event_bits comp_event; 4308 struct mlx5_ifc_dct_events_bits dct_events; 4309 struct mlx5_ifc_qp_events_bits qp_events; 4310 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4311 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4312 struct mlx5_ifc_cq_error_bits cq_error; 4313 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4314 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4315 struct mlx5_ifc_gpio_event_bits gpio_event; 4316 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4317 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4318 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4319 u8 reserved_at_0[0xe0]; 4320 }; 4321 4322 struct mlx5_ifc_health_buffer_bits { 4323 u8 reserved_at_0[0x100]; 4324 4325 u8 assert_existptr[0x20]; 4326 4327 u8 assert_callra[0x20]; 4328 4329 u8 reserved_at_140[0x20]; 4330 4331 u8 time[0x20]; 4332 4333 u8 fw_version[0x20]; 4334 4335 u8 hw_id[0x20]; 4336 4337 u8 rfr[0x1]; 4338 u8 reserved_at_1c1[0x3]; 4339 u8 valid[0x1]; 4340 u8 severity[0x3]; 4341 u8 reserved_at_1c8[0x18]; 4342 4343 u8 irisc_index[0x8]; 4344 u8 synd[0x8]; 4345 u8 ext_synd[0x10]; 4346 }; 4347 4348 struct mlx5_ifc_register_loopback_control_bits { 4349 u8 no_lb[0x1]; 4350 u8 reserved_at_1[0x7]; 4351 u8 port[0x8]; 4352 u8 reserved_at_10[0x10]; 4353 4354 u8 reserved_at_20[0x60]; 4355 }; 4356 4357 struct mlx5_ifc_vport_tc_element_bits { 4358 u8 traffic_class[0x4]; 4359 u8 reserved_at_4[0xc]; 4360 u8 vport_number[0x10]; 4361 }; 4362 4363 struct mlx5_ifc_vport_element_bits { 4364 u8 reserved_at_0[0x10]; 4365 u8 vport_number[0x10]; 4366 }; 4367 4368 enum { 4369 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4370 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4371 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4372 }; 4373 4374 struct mlx5_ifc_tsar_element_bits { 4375 u8 reserved_at_0[0x8]; 4376 u8 tsar_type[0x8]; 4377 u8 reserved_at_10[0x10]; 4378 }; 4379 4380 enum { 4381 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4382 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4383 }; 4384 4385 struct mlx5_ifc_teardown_hca_out_bits { 4386 u8 status[0x8]; 4387 u8 reserved_at_8[0x18]; 4388 4389 u8 syndrome[0x20]; 4390 4391 u8 reserved_at_40[0x3f]; 4392 4393 u8 state[0x1]; 4394 }; 4395 4396 enum { 4397 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4398 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4399 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4400 }; 4401 4402 struct mlx5_ifc_teardown_hca_in_bits { 4403 u8 opcode[0x10]; 4404 u8 reserved_at_10[0x10]; 4405 4406 u8 reserved_at_20[0x10]; 4407 u8 op_mod[0x10]; 4408 4409 u8 reserved_at_40[0x10]; 4410 u8 profile[0x10]; 4411 4412 u8 reserved_at_60[0x20]; 4413 }; 4414 4415 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4416 u8 status[0x8]; 4417 u8 reserved_at_8[0x18]; 4418 4419 u8 syndrome[0x20]; 4420 4421 u8 reserved_at_40[0x40]; 4422 }; 4423 4424 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4425 u8 opcode[0x10]; 4426 u8 uid[0x10]; 4427 4428 u8 reserved_at_20[0x10]; 4429 u8 op_mod[0x10]; 4430 4431 u8 reserved_at_40[0x8]; 4432 u8 qpn[0x18]; 4433 4434 u8 reserved_at_60[0x20]; 4435 4436 u8 opt_param_mask[0x20]; 4437 4438 u8 reserved_at_a0[0x20]; 4439 4440 struct mlx5_ifc_qpc_bits qpc; 4441 4442 u8 reserved_at_800[0x80]; 4443 }; 4444 4445 struct mlx5_ifc_sqd2rts_qp_out_bits { 4446 u8 status[0x8]; 4447 u8 reserved_at_8[0x18]; 4448 4449 u8 syndrome[0x20]; 4450 4451 u8 reserved_at_40[0x40]; 4452 }; 4453 4454 struct mlx5_ifc_sqd2rts_qp_in_bits { 4455 u8 opcode[0x10]; 4456 u8 uid[0x10]; 4457 4458 u8 reserved_at_20[0x10]; 4459 u8 op_mod[0x10]; 4460 4461 u8 reserved_at_40[0x8]; 4462 u8 qpn[0x18]; 4463 4464 u8 reserved_at_60[0x20]; 4465 4466 u8 opt_param_mask[0x20]; 4467 4468 u8 reserved_at_a0[0x20]; 4469 4470 struct mlx5_ifc_qpc_bits qpc; 4471 4472 u8 reserved_at_800[0x80]; 4473 }; 4474 4475 struct mlx5_ifc_set_roce_address_out_bits { 4476 u8 status[0x8]; 4477 u8 reserved_at_8[0x18]; 4478 4479 u8 syndrome[0x20]; 4480 4481 u8 reserved_at_40[0x40]; 4482 }; 4483 4484 struct mlx5_ifc_set_roce_address_in_bits { 4485 u8 opcode[0x10]; 4486 u8 reserved_at_10[0x10]; 4487 4488 u8 reserved_at_20[0x10]; 4489 u8 op_mod[0x10]; 4490 4491 u8 roce_address_index[0x10]; 4492 u8 reserved_at_50[0xc]; 4493 u8 vhca_port_num[0x4]; 4494 4495 u8 reserved_at_60[0x20]; 4496 4497 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4498 }; 4499 4500 struct mlx5_ifc_set_mad_demux_out_bits { 4501 u8 status[0x8]; 4502 u8 reserved_at_8[0x18]; 4503 4504 u8 syndrome[0x20]; 4505 4506 u8 reserved_at_40[0x40]; 4507 }; 4508 4509 enum { 4510 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4511 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4512 }; 4513 4514 struct mlx5_ifc_set_mad_demux_in_bits { 4515 u8 opcode[0x10]; 4516 u8 reserved_at_10[0x10]; 4517 4518 u8 reserved_at_20[0x10]; 4519 u8 op_mod[0x10]; 4520 4521 u8 reserved_at_40[0x20]; 4522 4523 u8 reserved_at_60[0x6]; 4524 u8 demux_mode[0x2]; 4525 u8 reserved_at_68[0x18]; 4526 }; 4527 4528 struct mlx5_ifc_set_l2_table_entry_out_bits { 4529 u8 status[0x8]; 4530 u8 reserved_at_8[0x18]; 4531 4532 u8 syndrome[0x20]; 4533 4534 u8 reserved_at_40[0x40]; 4535 }; 4536 4537 struct mlx5_ifc_set_l2_table_entry_in_bits { 4538 u8 opcode[0x10]; 4539 u8 reserved_at_10[0x10]; 4540 4541 u8 reserved_at_20[0x10]; 4542 u8 op_mod[0x10]; 4543 4544 u8 reserved_at_40[0x60]; 4545 4546 u8 reserved_at_a0[0x8]; 4547 u8 table_index[0x18]; 4548 4549 u8 reserved_at_c0[0x20]; 4550 4551 u8 reserved_at_e0[0x13]; 4552 u8 vlan_valid[0x1]; 4553 u8 vlan[0xc]; 4554 4555 struct mlx5_ifc_mac_address_layout_bits mac_address; 4556 4557 u8 reserved_at_140[0xc0]; 4558 }; 4559 4560 struct mlx5_ifc_set_issi_out_bits { 4561 u8 status[0x8]; 4562 u8 reserved_at_8[0x18]; 4563 4564 u8 syndrome[0x20]; 4565 4566 u8 reserved_at_40[0x40]; 4567 }; 4568 4569 struct mlx5_ifc_set_issi_in_bits { 4570 u8 opcode[0x10]; 4571 u8 reserved_at_10[0x10]; 4572 4573 u8 reserved_at_20[0x10]; 4574 u8 op_mod[0x10]; 4575 4576 u8 reserved_at_40[0x10]; 4577 u8 current_issi[0x10]; 4578 4579 u8 reserved_at_60[0x20]; 4580 }; 4581 4582 struct mlx5_ifc_set_hca_cap_out_bits { 4583 u8 status[0x8]; 4584 u8 reserved_at_8[0x18]; 4585 4586 u8 syndrome[0x20]; 4587 4588 u8 reserved_at_40[0x40]; 4589 }; 4590 4591 struct mlx5_ifc_set_hca_cap_in_bits { 4592 u8 opcode[0x10]; 4593 u8 reserved_at_10[0x10]; 4594 4595 u8 reserved_at_20[0x10]; 4596 u8 op_mod[0x10]; 4597 4598 u8 other_function[0x1]; 4599 u8 reserved_at_41[0xf]; 4600 u8 function_id[0x10]; 4601 4602 u8 reserved_at_60[0x20]; 4603 4604 union mlx5_ifc_hca_cap_union_bits capability; 4605 }; 4606 4607 enum { 4608 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4609 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4610 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4611 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4612 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4613 }; 4614 4615 struct mlx5_ifc_set_fte_out_bits { 4616 u8 status[0x8]; 4617 u8 reserved_at_8[0x18]; 4618 4619 u8 syndrome[0x20]; 4620 4621 u8 reserved_at_40[0x40]; 4622 }; 4623 4624 struct mlx5_ifc_set_fte_in_bits { 4625 u8 opcode[0x10]; 4626 u8 reserved_at_10[0x10]; 4627 4628 u8 reserved_at_20[0x10]; 4629 u8 op_mod[0x10]; 4630 4631 u8 other_vport[0x1]; 4632 u8 reserved_at_41[0xf]; 4633 u8 vport_number[0x10]; 4634 4635 u8 reserved_at_60[0x20]; 4636 4637 u8 table_type[0x8]; 4638 u8 reserved_at_88[0x18]; 4639 4640 u8 reserved_at_a0[0x8]; 4641 u8 table_id[0x18]; 4642 4643 u8 ignore_flow_level[0x1]; 4644 u8 reserved_at_c1[0x17]; 4645 u8 modify_enable_mask[0x8]; 4646 4647 u8 reserved_at_e0[0x20]; 4648 4649 u8 flow_index[0x20]; 4650 4651 u8 reserved_at_120[0xe0]; 4652 4653 struct mlx5_ifc_flow_context_bits flow_context; 4654 }; 4655 4656 struct mlx5_ifc_rts2rts_qp_out_bits { 4657 u8 status[0x8]; 4658 u8 reserved_at_8[0x18]; 4659 4660 u8 syndrome[0x20]; 4661 4662 u8 reserved_at_40[0x20]; 4663 u8 ece[0x20]; 4664 }; 4665 4666 struct mlx5_ifc_rts2rts_qp_in_bits { 4667 u8 opcode[0x10]; 4668 u8 uid[0x10]; 4669 4670 u8 reserved_at_20[0x10]; 4671 u8 op_mod[0x10]; 4672 4673 u8 reserved_at_40[0x8]; 4674 u8 qpn[0x18]; 4675 4676 u8 reserved_at_60[0x20]; 4677 4678 u8 opt_param_mask[0x20]; 4679 4680 u8 ece[0x20]; 4681 4682 struct mlx5_ifc_qpc_bits qpc; 4683 4684 u8 reserved_at_800[0x80]; 4685 }; 4686 4687 struct mlx5_ifc_rtr2rts_qp_out_bits { 4688 u8 status[0x8]; 4689 u8 reserved_at_8[0x18]; 4690 4691 u8 syndrome[0x20]; 4692 4693 u8 reserved_at_40[0x20]; 4694 u8 ece[0x20]; 4695 }; 4696 4697 struct mlx5_ifc_rtr2rts_qp_in_bits { 4698 u8 opcode[0x10]; 4699 u8 uid[0x10]; 4700 4701 u8 reserved_at_20[0x10]; 4702 u8 op_mod[0x10]; 4703 4704 u8 reserved_at_40[0x8]; 4705 u8 qpn[0x18]; 4706 4707 u8 reserved_at_60[0x20]; 4708 4709 u8 opt_param_mask[0x20]; 4710 4711 u8 ece[0x20]; 4712 4713 struct mlx5_ifc_qpc_bits qpc; 4714 4715 u8 reserved_at_800[0x80]; 4716 }; 4717 4718 struct mlx5_ifc_rst2init_qp_out_bits { 4719 u8 status[0x8]; 4720 u8 reserved_at_8[0x18]; 4721 4722 u8 syndrome[0x20]; 4723 4724 u8 reserved_at_40[0x20]; 4725 u8 ece[0x20]; 4726 }; 4727 4728 struct mlx5_ifc_rst2init_qp_in_bits { 4729 u8 opcode[0x10]; 4730 u8 uid[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x8]; 4736 u8 qpn[0x18]; 4737 4738 u8 reserved_at_60[0x20]; 4739 4740 u8 opt_param_mask[0x20]; 4741 4742 u8 ece[0x20]; 4743 4744 struct mlx5_ifc_qpc_bits qpc; 4745 4746 u8 reserved_at_800[0x80]; 4747 }; 4748 4749 struct mlx5_ifc_query_xrq_out_bits { 4750 u8 status[0x8]; 4751 u8 reserved_at_8[0x18]; 4752 4753 u8 syndrome[0x20]; 4754 4755 u8 reserved_at_40[0x40]; 4756 4757 struct mlx5_ifc_xrqc_bits xrq_context; 4758 }; 4759 4760 struct mlx5_ifc_query_xrq_in_bits { 4761 u8 opcode[0x10]; 4762 u8 reserved_at_10[0x10]; 4763 4764 u8 reserved_at_20[0x10]; 4765 u8 op_mod[0x10]; 4766 4767 u8 reserved_at_40[0x8]; 4768 u8 xrqn[0x18]; 4769 4770 u8 reserved_at_60[0x20]; 4771 }; 4772 4773 struct mlx5_ifc_query_xrc_srq_out_bits { 4774 u8 status[0x8]; 4775 u8 reserved_at_8[0x18]; 4776 4777 u8 syndrome[0x20]; 4778 4779 u8 reserved_at_40[0x40]; 4780 4781 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4782 4783 u8 reserved_at_280[0x600]; 4784 4785 u8 pas[][0x40]; 4786 }; 4787 4788 struct mlx5_ifc_query_xrc_srq_in_bits { 4789 u8 opcode[0x10]; 4790 u8 reserved_at_10[0x10]; 4791 4792 u8 reserved_at_20[0x10]; 4793 u8 op_mod[0x10]; 4794 4795 u8 reserved_at_40[0x8]; 4796 u8 xrc_srqn[0x18]; 4797 4798 u8 reserved_at_60[0x20]; 4799 }; 4800 4801 enum { 4802 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4803 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4804 }; 4805 4806 struct mlx5_ifc_query_vport_state_out_bits { 4807 u8 status[0x8]; 4808 u8 reserved_at_8[0x18]; 4809 4810 u8 syndrome[0x20]; 4811 4812 u8 reserved_at_40[0x20]; 4813 4814 u8 reserved_at_60[0x18]; 4815 u8 admin_state[0x4]; 4816 u8 state[0x4]; 4817 }; 4818 4819 enum { 4820 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4821 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4822 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4823 }; 4824 4825 struct mlx5_ifc_arm_monitor_counter_in_bits { 4826 u8 opcode[0x10]; 4827 u8 uid[0x10]; 4828 4829 u8 reserved_at_20[0x10]; 4830 u8 op_mod[0x10]; 4831 4832 u8 reserved_at_40[0x20]; 4833 4834 u8 reserved_at_60[0x20]; 4835 }; 4836 4837 struct mlx5_ifc_arm_monitor_counter_out_bits { 4838 u8 status[0x8]; 4839 u8 reserved_at_8[0x18]; 4840 4841 u8 syndrome[0x20]; 4842 4843 u8 reserved_at_40[0x40]; 4844 }; 4845 4846 enum { 4847 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4848 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4849 }; 4850 4851 enum mlx5_monitor_counter_ppcnt { 4852 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4853 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4854 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4855 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4856 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4857 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4858 }; 4859 4860 enum { 4861 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4862 }; 4863 4864 struct mlx5_ifc_monitor_counter_output_bits { 4865 u8 reserved_at_0[0x4]; 4866 u8 type[0x4]; 4867 u8 reserved_at_8[0x8]; 4868 u8 counter[0x10]; 4869 4870 u8 counter_group_id[0x20]; 4871 }; 4872 4873 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4874 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4875 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4876 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4877 4878 struct mlx5_ifc_set_monitor_counter_in_bits { 4879 u8 opcode[0x10]; 4880 u8 uid[0x10]; 4881 4882 u8 reserved_at_20[0x10]; 4883 u8 op_mod[0x10]; 4884 4885 u8 reserved_at_40[0x10]; 4886 u8 num_of_counters[0x10]; 4887 4888 u8 reserved_at_60[0x20]; 4889 4890 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4891 }; 4892 4893 struct mlx5_ifc_set_monitor_counter_out_bits { 4894 u8 status[0x8]; 4895 u8 reserved_at_8[0x18]; 4896 4897 u8 syndrome[0x20]; 4898 4899 u8 reserved_at_40[0x40]; 4900 }; 4901 4902 struct mlx5_ifc_query_vport_state_in_bits { 4903 u8 opcode[0x10]; 4904 u8 reserved_at_10[0x10]; 4905 4906 u8 reserved_at_20[0x10]; 4907 u8 op_mod[0x10]; 4908 4909 u8 other_vport[0x1]; 4910 u8 reserved_at_41[0xf]; 4911 u8 vport_number[0x10]; 4912 4913 u8 reserved_at_60[0x20]; 4914 }; 4915 4916 struct mlx5_ifc_query_vnic_env_out_bits { 4917 u8 status[0x8]; 4918 u8 reserved_at_8[0x18]; 4919 4920 u8 syndrome[0x20]; 4921 4922 u8 reserved_at_40[0x40]; 4923 4924 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4925 }; 4926 4927 enum { 4928 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4929 }; 4930 4931 struct mlx5_ifc_query_vnic_env_in_bits { 4932 u8 opcode[0x10]; 4933 u8 reserved_at_10[0x10]; 4934 4935 u8 reserved_at_20[0x10]; 4936 u8 op_mod[0x10]; 4937 4938 u8 other_vport[0x1]; 4939 u8 reserved_at_41[0xf]; 4940 u8 vport_number[0x10]; 4941 4942 u8 reserved_at_60[0x20]; 4943 }; 4944 4945 struct mlx5_ifc_query_vport_counter_out_bits { 4946 u8 status[0x8]; 4947 u8 reserved_at_8[0x18]; 4948 4949 u8 syndrome[0x20]; 4950 4951 u8 reserved_at_40[0x40]; 4952 4953 struct mlx5_ifc_traffic_counter_bits received_errors; 4954 4955 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4956 4957 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4958 4959 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4960 4961 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4962 4963 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4964 4965 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4966 4967 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4968 4969 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4970 4971 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4972 4973 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4974 4975 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4976 4977 u8 reserved_at_680[0xa00]; 4978 }; 4979 4980 enum { 4981 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4982 }; 4983 4984 struct mlx5_ifc_query_vport_counter_in_bits { 4985 u8 opcode[0x10]; 4986 u8 reserved_at_10[0x10]; 4987 4988 u8 reserved_at_20[0x10]; 4989 u8 op_mod[0x10]; 4990 4991 u8 other_vport[0x1]; 4992 u8 reserved_at_41[0xb]; 4993 u8 port_num[0x4]; 4994 u8 vport_number[0x10]; 4995 4996 u8 reserved_at_60[0x60]; 4997 4998 u8 clear[0x1]; 4999 u8 reserved_at_c1[0x1f]; 5000 5001 u8 reserved_at_e0[0x20]; 5002 }; 5003 5004 struct mlx5_ifc_query_tis_out_bits { 5005 u8 status[0x8]; 5006 u8 reserved_at_8[0x18]; 5007 5008 u8 syndrome[0x20]; 5009 5010 u8 reserved_at_40[0x40]; 5011 5012 struct mlx5_ifc_tisc_bits tis_context; 5013 }; 5014 5015 struct mlx5_ifc_query_tis_in_bits { 5016 u8 opcode[0x10]; 5017 u8 reserved_at_10[0x10]; 5018 5019 u8 reserved_at_20[0x10]; 5020 u8 op_mod[0x10]; 5021 5022 u8 reserved_at_40[0x8]; 5023 u8 tisn[0x18]; 5024 5025 u8 reserved_at_60[0x20]; 5026 }; 5027 5028 struct mlx5_ifc_query_tir_out_bits { 5029 u8 status[0x8]; 5030 u8 reserved_at_8[0x18]; 5031 5032 u8 syndrome[0x20]; 5033 5034 u8 reserved_at_40[0xc0]; 5035 5036 struct mlx5_ifc_tirc_bits tir_context; 5037 }; 5038 5039 struct mlx5_ifc_query_tir_in_bits { 5040 u8 opcode[0x10]; 5041 u8 reserved_at_10[0x10]; 5042 5043 u8 reserved_at_20[0x10]; 5044 u8 op_mod[0x10]; 5045 5046 u8 reserved_at_40[0x8]; 5047 u8 tirn[0x18]; 5048 5049 u8 reserved_at_60[0x20]; 5050 }; 5051 5052 struct mlx5_ifc_query_srq_out_bits { 5053 u8 status[0x8]; 5054 u8 reserved_at_8[0x18]; 5055 5056 u8 syndrome[0x20]; 5057 5058 u8 reserved_at_40[0x40]; 5059 5060 struct mlx5_ifc_srqc_bits srq_context_entry; 5061 5062 u8 reserved_at_280[0x600]; 5063 5064 u8 pas[][0x40]; 5065 }; 5066 5067 struct mlx5_ifc_query_srq_in_bits { 5068 u8 opcode[0x10]; 5069 u8 reserved_at_10[0x10]; 5070 5071 u8 reserved_at_20[0x10]; 5072 u8 op_mod[0x10]; 5073 5074 u8 reserved_at_40[0x8]; 5075 u8 srqn[0x18]; 5076 5077 u8 reserved_at_60[0x20]; 5078 }; 5079 5080 struct mlx5_ifc_query_sq_out_bits { 5081 u8 status[0x8]; 5082 u8 reserved_at_8[0x18]; 5083 5084 u8 syndrome[0x20]; 5085 5086 u8 reserved_at_40[0xc0]; 5087 5088 struct mlx5_ifc_sqc_bits sq_context; 5089 }; 5090 5091 struct mlx5_ifc_query_sq_in_bits { 5092 u8 opcode[0x10]; 5093 u8 reserved_at_10[0x10]; 5094 5095 u8 reserved_at_20[0x10]; 5096 u8 op_mod[0x10]; 5097 5098 u8 reserved_at_40[0x8]; 5099 u8 sqn[0x18]; 5100 5101 u8 reserved_at_60[0x20]; 5102 }; 5103 5104 struct mlx5_ifc_query_special_contexts_out_bits { 5105 u8 status[0x8]; 5106 u8 reserved_at_8[0x18]; 5107 5108 u8 syndrome[0x20]; 5109 5110 u8 dump_fill_mkey[0x20]; 5111 5112 u8 resd_lkey[0x20]; 5113 5114 u8 null_mkey[0x20]; 5115 5116 u8 reserved_at_a0[0x60]; 5117 }; 5118 5119 struct mlx5_ifc_query_special_contexts_in_bits { 5120 u8 opcode[0x10]; 5121 u8 reserved_at_10[0x10]; 5122 5123 u8 reserved_at_20[0x10]; 5124 u8 op_mod[0x10]; 5125 5126 u8 reserved_at_40[0x40]; 5127 }; 5128 5129 struct mlx5_ifc_query_scheduling_element_out_bits { 5130 u8 opcode[0x10]; 5131 u8 reserved_at_10[0x10]; 5132 5133 u8 reserved_at_20[0x10]; 5134 u8 op_mod[0x10]; 5135 5136 u8 reserved_at_40[0xc0]; 5137 5138 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5139 5140 u8 reserved_at_300[0x100]; 5141 }; 5142 5143 enum { 5144 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5145 SCHEDULING_HIERARCHY_NIC = 0x3, 5146 }; 5147 5148 struct mlx5_ifc_query_scheduling_element_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_at_10[0x10]; 5151 5152 u8 reserved_at_20[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 scheduling_hierarchy[0x8]; 5156 u8 reserved_at_48[0x18]; 5157 5158 u8 scheduling_element_id[0x20]; 5159 5160 u8 reserved_at_80[0x180]; 5161 }; 5162 5163 struct mlx5_ifc_query_rqt_out_bits { 5164 u8 status[0x8]; 5165 u8 reserved_at_8[0x18]; 5166 5167 u8 syndrome[0x20]; 5168 5169 u8 reserved_at_40[0xc0]; 5170 5171 struct mlx5_ifc_rqtc_bits rqt_context; 5172 }; 5173 5174 struct mlx5_ifc_query_rqt_in_bits { 5175 u8 opcode[0x10]; 5176 u8 reserved_at_10[0x10]; 5177 5178 u8 reserved_at_20[0x10]; 5179 u8 op_mod[0x10]; 5180 5181 u8 reserved_at_40[0x8]; 5182 u8 rqtn[0x18]; 5183 5184 u8 reserved_at_60[0x20]; 5185 }; 5186 5187 struct mlx5_ifc_query_rq_out_bits { 5188 u8 status[0x8]; 5189 u8 reserved_at_8[0x18]; 5190 5191 u8 syndrome[0x20]; 5192 5193 u8 reserved_at_40[0xc0]; 5194 5195 struct mlx5_ifc_rqc_bits rq_context; 5196 }; 5197 5198 struct mlx5_ifc_query_rq_in_bits { 5199 u8 opcode[0x10]; 5200 u8 reserved_at_10[0x10]; 5201 5202 u8 reserved_at_20[0x10]; 5203 u8 op_mod[0x10]; 5204 5205 u8 reserved_at_40[0x8]; 5206 u8 rqn[0x18]; 5207 5208 u8 reserved_at_60[0x20]; 5209 }; 5210 5211 struct mlx5_ifc_query_roce_address_out_bits { 5212 u8 status[0x8]; 5213 u8 reserved_at_8[0x18]; 5214 5215 u8 syndrome[0x20]; 5216 5217 u8 reserved_at_40[0x40]; 5218 5219 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5220 }; 5221 5222 struct mlx5_ifc_query_roce_address_in_bits { 5223 u8 opcode[0x10]; 5224 u8 reserved_at_10[0x10]; 5225 5226 u8 reserved_at_20[0x10]; 5227 u8 op_mod[0x10]; 5228 5229 u8 roce_address_index[0x10]; 5230 u8 reserved_at_50[0xc]; 5231 u8 vhca_port_num[0x4]; 5232 5233 u8 reserved_at_60[0x20]; 5234 }; 5235 5236 struct mlx5_ifc_query_rmp_out_bits { 5237 u8 status[0x8]; 5238 u8 reserved_at_8[0x18]; 5239 5240 u8 syndrome[0x20]; 5241 5242 u8 reserved_at_40[0xc0]; 5243 5244 struct mlx5_ifc_rmpc_bits rmp_context; 5245 }; 5246 5247 struct mlx5_ifc_query_rmp_in_bits { 5248 u8 opcode[0x10]; 5249 u8 reserved_at_10[0x10]; 5250 5251 u8 reserved_at_20[0x10]; 5252 u8 op_mod[0x10]; 5253 5254 u8 reserved_at_40[0x8]; 5255 u8 rmpn[0x18]; 5256 5257 u8 reserved_at_60[0x20]; 5258 }; 5259 5260 struct mlx5_ifc_query_qp_out_bits { 5261 u8 status[0x8]; 5262 u8 reserved_at_8[0x18]; 5263 5264 u8 syndrome[0x20]; 5265 5266 u8 reserved_at_40[0x40]; 5267 5268 u8 opt_param_mask[0x20]; 5269 5270 u8 ece[0x20]; 5271 5272 struct mlx5_ifc_qpc_bits qpc; 5273 5274 u8 reserved_at_800[0x80]; 5275 5276 u8 pas[][0x40]; 5277 }; 5278 5279 struct mlx5_ifc_query_qp_in_bits { 5280 u8 opcode[0x10]; 5281 u8 reserved_at_10[0x10]; 5282 5283 u8 reserved_at_20[0x10]; 5284 u8 op_mod[0x10]; 5285 5286 u8 reserved_at_40[0x8]; 5287 u8 qpn[0x18]; 5288 5289 u8 reserved_at_60[0x20]; 5290 }; 5291 5292 struct mlx5_ifc_query_q_counter_out_bits { 5293 u8 status[0x8]; 5294 u8 reserved_at_8[0x18]; 5295 5296 u8 syndrome[0x20]; 5297 5298 u8 reserved_at_40[0x40]; 5299 5300 u8 rx_write_requests[0x20]; 5301 5302 u8 reserved_at_a0[0x20]; 5303 5304 u8 rx_read_requests[0x20]; 5305 5306 u8 reserved_at_e0[0x20]; 5307 5308 u8 rx_atomic_requests[0x20]; 5309 5310 u8 reserved_at_120[0x20]; 5311 5312 u8 rx_dct_connect[0x20]; 5313 5314 u8 reserved_at_160[0x20]; 5315 5316 u8 out_of_buffer[0x20]; 5317 5318 u8 reserved_at_1a0[0x20]; 5319 5320 u8 out_of_sequence[0x20]; 5321 5322 u8 reserved_at_1e0[0x20]; 5323 5324 u8 duplicate_request[0x20]; 5325 5326 u8 reserved_at_220[0x20]; 5327 5328 u8 rnr_nak_retry_err[0x20]; 5329 5330 u8 reserved_at_260[0x20]; 5331 5332 u8 packet_seq_err[0x20]; 5333 5334 u8 reserved_at_2a0[0x20]; 5335 5336 u8 implied_nak_seq_err[0x20]; 5337 5338 u8 reserved_at_2e0[0x20]; 5339 5340 u8 local_ack_timeout_err[0x20]; 5341 5342 u8 reserved_at_320[0xa0]; 5343 5344 u8 resp_local_length_error[0x20]; 5345 5346 u8 req_local_length_error[0x20]; 5347 5348 u8 resp_local_qp_error[0x20]; 5349 5350 u8 local_operation_error[0x20]; 5351 5352 u8 resp_local_protection[0x20]; 5353 5354 u8 req_local_protection[0x20]; 5355 5356 u8 resp_cqe_error[0x20]; 5357 5358 u8 req_cqe_error[0x20]; 5359 5360 u8 req_mw_binding[0x20]; 5361 5362 u8 req_bad_response[0x20]; 5363 5364 u8 req_remote_invalid_request[0x20]; 5365 5366 u8 resp_remote_invalid_request[0x20]; 5367 5368 u8 req_remote_access_errors[0x20]; 5369 5370 u8 resp_remote_access_errors[0x20]; 5371 5372 u8 req_remote_operation_errors[0x20]; 5373 5374 u8 req_transport_retries_exceeded[0x20]; 5375 5376 u8 cq_overflow[0x20]; 5377 5378 u8 resp_cqe_flush_error[0x20]; 5379 5380 u8 req_cqe_flush_error[0x20]; 5381 5382 u8 reserved_at_620[0x20]; 5383 5384 u8 roce_adp_retrans[0x20]; 5385 5386 u8 roce_adp_retrans_to[0x20]; 5387 5388 u8 roce_slow_restart[0x20]; 5389 5390 u8 roce_slow_restart_cnps[0x20]; 5391 5392 u8 roce_slow_restart_trans[0x20]; 5393 5394 u8 reserved_at_6e0[0x120]; 5395 }; 5396 5397 struct mlx5_ifc_query_q_counter_in_bits { 5398 u8 opcode[0x10]; 5399 u8 reserved_at_10[0x10]; 5400 5401 u8 reserved_at_20[0x10]; 5402 u8 op_mod[0x10]; 5403 5404 u8 reserved_at_40[0x80]; 5405 5406 u8 clear[0x1]; 5407 u8 reserved_at_c1[0x1f]; 5408 5409 u8 reserved_at_e0[0x18]; 5410 u8 counter_set_id[0x8]; 5411 }; 5412 5413 struct mlx5_ifc_query_pages_out_bits { 5414 u8 status[0x8]; 5415 u8 reserved_at_8[0x18]; 5416 5417 u8 syndrome[0x20]; 5418 5419 u8 embedded_cpu_function[0x1]; 5420 u8 reserved_at_41[0xf]; 5421 u8 function_id[0x10]; 5422 5423 u8 num_pages[0x20]; 5424 }; 5425 5426 enum { 5427 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5428 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5429 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5430 }; 5431 5432 struct mlx5_ifc_query_pages_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_at_10[0x10]; 5435 5436 u8 reserved_at_20[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 embedded_cpu_function[0x1]; 5440 u8 reserved_at_41[0xf]; 5441 u8 function_id[0x10]; 5442 5443 u8 reserved_at_60[0x20]; 5444 }; 5445 5446 struct mlx5_ifc_query_nic_vport_context_out_bits { 5447 u8 status[0x8]; 5448 u8 reserved_at_8[0x18]; 5449 5450 u8 syndrome[0x20]; 5451 5452 u8 reserved_at_40[0x40]; 5453 5454 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5455 }; 5456 5457 struct mlx5_ifc_query_nic_vport_context_in_bits { 5458 u8 opcode[0x10]; 5459 u8 reserved_at_10[0x10]; 5460 5461 u8 reserved_at_20[0x10]; 5462 u8 op_mod[0x10]; 5463 5464 u8 other_vport[0x1]; 5465 u8 reserved_at_41[0xf]; 5466 u8 vport_number[0x10]; 5467 5468 u8 reserved_at_60[0x5]; 5469 u8 allowed_list_type[0x3]; 5470 u8 reserved_at_68[0x18]; 5471 }; 5472 5473 struct mlx5_ifc_query_mkey_out_bits { 5474 u8 status[0x8]; 5475 u8 reserved_at_8[0x18]; 5476 5477 u8 syndrome[0x20]; 5478 5479 u8 reserved_at_40[0x40]; 5480 5481 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5482 5483 u8 reserved_at_280[0x600]; 5484 5485 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5486 5487 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5488 }; 5489 5490 struct mlx5_ifc_query_mkey_in_bits { 5491 u8 opcode[0x10]; 5492 u8 reserved_at_10[0x10]; 5493 5494 u8 reserved_at_20[0x10]; 5495 u8 op_mod[0x10]; 5496 5497 u8 reserved_at_40[0x8]; 5498 u8 mkey_index[0x18]; 5499 5500 u8 pg_access[0x1]; 5501 u8 reserved_at_61[0x1f]; 5502 }; 5503 5504 struct mlx5_ifc_query_mad_demux_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_at_8[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_at_40[0x40]; 5511 5512 u8 mad_dumux_parameters_block[0x20]; 5513 }; 5514 5515 struct mlx5_ifc_query_mad_demux_in_bits { 5516 u8 opcode[0x10]; 5517 u8 reserved_at_10[0x10]; 5518 5519 u8 reserved_at_20[0x10]; 5520 u8 op_mod[0x10]; 5521 5522 u8 reserved_at_40[0x40]; 5523 }; 5524 5525 struct mlx5_ifc_query_l2_table_entry_out_bits { 5526 u8 status[0x8]; 5527 u8 reserved_at_8[0x18]; 5528 5529 u8 syndrome[0x20]; 5530 5531 u8 reserved_at_40[0xa0]; 5532 5533 u8 reserved_at_e0[0x13]; 5534 u8 vlan_valid[0x1]; 5535 u8 vlan[0xc]; 5536 5537 struct mlx5_ifc_mac_address_layout_bits mac_address; 5538 5539 u8 reserved_at_140[0xc0]; 5540 }; 5541 5542 struct mlx5_ifc_query_l2_table_entry_in_bits { 5543 u8 opcode[0x10]; 5544 u8 reserved_at_10[0x10]; 5545 5546 u8 reserved_at_20[0x10]; 5547 u8 op_mod[0x10]; 5548 5549 u8 reserved_at_40[0x60]; 5550 5551 u8 reserved_at_a0[0x8]; 5552 u8 table_index[0x18]; 5553 5554 u8 reserved_at_c0[0x140]; 5555 }; 5556 5557 struct mlx5_ifc_query_issi_out_bits { 5558 u8 status[0x8]; 5559 u8 reserved_at_8[0x18]; 5560 5561 u8 syndrome[0x20]; 5562 5563 u8 reserved_at_40[0x10]; 5564 u8 current_issi[0x10]; 5565 5566 u8 reserved_at_60[0xa0]; 5567 5568 u8 reserved_at_100[76][0x8]; 5569 u8 supported_issi_dw0[0x20]; 5570 }; 5571 5572 struct mlx5_ifc_query_issi_in_bits { 5573 u8 opcode[0x10]; 5574 u8 reserved_at_10[0x10]; 5575 5576 u8 reserved_at_20[0x10]; 5577 u8 op_mod[0x10]; 5578 5579 u8 reserved_at_40[0x40]; 5580 }; 5581 5582 struct mlx5_ifc_set_driver_version_out_bits { 5583 u8 status[0x8]; 5584 u8 reserved_0[0x18]; 5585 5586 u8 syndrome[0x20]; 5587 u8 reserved_1[0x40]; 5588 }; 5589 5590 struct mlx5_ifc_set_driver_version_in_bits { 5591 u8 opcode[0x10]; 5592 u8 reserved_0[0x10]; 5593 5594 u8 reserved_1[0x10]; 5595 u8 op_mod[0x10]; 5596 5597 u8 reserved_2[0x40]; 5598 u8 driver_version[64][0x8]; 5599 }; 5600 5601 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5602 u8 status[0x8]; 5603 u8 reserved_at_8[0x18]; 5604 5605 u8 syndrome[0x20]; 5606 5607 u8 reserved_at_40[0x40]; 5608 5609 struct mlx5_ifc_pkey_bits pkey[]; 5610 }; 5611 5612 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5613 u8 opcode[0x10]; 5614 u8 reserved_at_10[0x10]; 5615 5616 u8 reserved_at_20[0x10]; 5617 u8 op_mod[0x10]; 5618 5619 u8 other_vport[0x1]; 5620 u8 reserved_at_41[0xb]; 5621 u8 port_num[0x4]; 5622 u8 vport_number[0x10]; 5623 5624 u8 reserved_at_60[0x10]; 5625 u8 pkey_index[0x10]; 5626 }; 5627 5628 enum { 5629 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5630 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5631 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5632 }; 5633 5634 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5635 u8 status[0x8]; 5636 u8 reserved_at_8[0x18]; 5637 5638 u8 syndrome[0x20]; 5639 5640 u8 reserved_at_40[0x20]; 5641 5642 u8 gids_num[0x10]; 5643 u8 reserved_at_70[0x10]; 5644 5645 struct mlx5_ifc_array128_auto_bits gid[]; 5646 }; 5647 5648 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5649 u8 opcode[0x10]; 5650 u8 reserved_at_10[0x10]; 5651 5652 u8 reserved_at_20[0x10]; 5653 u8 op_mod[0x10]; 5654 5655 u8 other_vport[0x1]; 5656 u8 reserved_at_41[0xb]; 5657 u8 port_num[0x4]; 5658 u8 vport_number[0x10]; 5659 5660 u8 reserved_at_60[0x10]; 5661 u8 gid_index[0x10]; 5662 }; 5663 5664 struct mlx5_ifc_query_hca_vport_context_out_bits { 5665 u8 status[0x8]; 5666 u8 reserved_at_8[0x18]; 5667 5668 u8 syndrome[0x20]; 5669 5670 u8 reserved_at_40[0x40]; 5671 5672 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5673 }; 5674 5675 struct mlx5_ifc_query_hca_vport_context_in_bits { 5676 u8 opcode[0x10]; 5677 u8 reserved_at_10[0x10]; 5678 5679 u8 reserved_at_20[0x10]; 5680 u8 op_mod[0x10]; 5681 5682 u8 other_vport[0x1]; 5683 u8 reserved_at_41[0xb]; 5684 u8 port_num[0x4]; 5685 u8 vport_number[0x10]; 5686 5687 u8 reserved_at_60[0x20]; 5688 }; 5689 5690 struct mlx5_ifc_query_hca_cap_out_bits { 5691 u8 status[0x8]; 5692 u8 reserved_at_8[0x18]; 5693 5694 u8 syndrome[0x20]; 5695 5696 u8 reserved_at_40[0x40]; 5697 5698 union mlx5_ifc_hca_cap_union_bits capability; 5699 }; 5700 5701 struct mlx5_ifc_query_hca_cap_in_bits { 5702 u8 opcode[0x10]; 5703 u8 reserved_at_10[0x10]; 5704 5705 u8 reserved_at_20[0x10]; 5706 u8 op_mod[0x10]; 5707 5708 u8 other_function[0x1]; 5709 u8 reserved_at_41[0xf]; 5710 u8 function_id[0x10]; 5711 5712 u8 reserved_at_60[0x20]; 5713 }; 5714 5715 struct mlx5_ifc_other_hca_cap_bits { 5716 u8 roce[0x1]; 5717 u8 reserved_at_1[0x27f]; 5718 }; 5719 5720 struct mlx5_ifc_query_other_hca_cap_out_bits { 5721 u8 status[0x8]; 5722 u8 reserved_at_8[0x18]; 5723 5724 u8 syndrome[0x20]; 5725 5726 u8 reserved_at_40[0x40]; 5727 5728 struct mlx5_ifc_other_hca_cap_bits other_capability; 5729 }; 5730 5731 struct mlx5_ifc_query_other_hca_cap_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 reserved_at_40[0x10]; 5739 u8 function_id[0x10]; 5740 5741 u8 reserved_at_60[0x20]; 5742 }; 5743 5744 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_at_8[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_at_40[0x40]; 5751 }; 5752 5753 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5754 u8 opcode[0x10]; 5755 u8 reserved_at_10[0x10]; 5756 5757 u8 reserved_at_20[0x10]; 5758 u8 op_mod[0x10]; 5759 5760 u8 reserved_at_40[0x10]; 5761 u8 function_id[0x10]; 5762 u8 field_select[0x20]; 5763 5764 struct mlx5_ifc_other_hca_cap_bits other_capability; 5765 }; 5766 5767 struct mlx5_ifc_flow_table_context_bits { 5768 u8 reformat_en[0x1]; 5769 u8 decap_en[0x1]; 5770 u8 sw_owner[0x1]; 5771 u8 termination_table[0x1]; 5772 u8 table_miss_action[0x4]; 5773 u8 level[0x8]; 5774 u8 reserved_at_10[0x8]; 5775 u8 log_size[0x8]; 5776 5777 u8 reserved_at_20[0x8]; 5778 u8 table_miss_id[0x18]; 5779 5780 u8 reserved_at_40[0x8]; 5781 u8 lag_master_next_table_id[0x18]; 5782 5783 u8 reserved_at_60[0x60]; 5784 5785 u8 sw_owner_icm_root_1[0x40]; 5786 5787 u8 sw_owner_icm_root_0[0x40]; 5788 5789 }; 5790 5791 struct mlx5_ifc_query_flow_table_out_bits { 5792 u8 status[0x8]; 5793 u8 reserved_at_8[0x18]; 5794 5795 u8 syndrome[0x20]; 5796 5797 u8 reserved_at_40[0x80]; 5798 5799 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5800 }; 5801 5802 struct mlx5_ifc_query_flow_table_in_bits { 5803 u8 opcode[0x10]; 5804 u8 reserved_at_10[0x10]; 5805 5806 u8 reserved_at_20[0x10]; 5807 u8 op_mod[0x10]; 5808 5809 u8 reserved_at_40[0x40]; 5810 5811 u8 table_type[0x8]; 5812 u8 reserved_at_88[0x18]; 5813 5814 u8 reserved_at_a0[0x8]; 5815 u8 table_id[0x18]; 5816 5817 u8 reserved_at_c0[0x140]; 5818 }; 5819 5820 struct mlx5_ifc_query_fte_out_bits { 5821 u8 status[0x8]; 5822 u8 reserved_at_8[0x18]; 5823 5824 u8 syndrome[0x20]; 5825 5826 u8 reserved_at_40[0x1c0]; 5827 5828 struct mlx5_ifc_flow_context_bits flow_context; 5829 }; 5830 5831 struct mlx5_ifc_query_fte_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_at_10[0x10]; 5834 5835 u8 reserved_at_20[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 reserved_at_40[0x40]; 5839 5840 u8 table_type[0x8]; 5841 u8 reserved_at_88[0x18]; 5842 5843 u8 reserved_at_a0[0x8]; 5844 u8 table_id[0x18]; 5845 5846 u8 reserved_at_c0[0x40]; 5847 5848 u8 flow_index[0x20]; 5849 5850 u8 reserved_at_120[0xe0]; 5851 }; 5852 5853 struct mlx5_ifc_match_definer_format_0_bits { 5854 u8 reserved_at_0[0x100]; 5855 5856 u8 metadata_reg_c_0[0x20]; 5857 5858 u8 metadata_reg_c_1[0x20]; 5859 5860 u8 outer_dmac_47_16[0x20]; 5861 5862 u8 outer_dmac_15_0[0x10]; 5863 u8 outer_ethertype[0x10]; 5864 5865 u8 reserved_at_180[0x1]; 5866 u8 sx_sniffer[0x1]; 5867 u8 functional_lb[0x1]; 5868 u8 outer_ip_frag[0x1]; 5869 u8 outer_qp_type[0x2]; 5870 u8 outer_encap_type[0x2]; 5871 u8 port_number[0x2]; 5872 u8 outer_l3_type[0x2]; 5873 u8 outer_l4_type[0x2]; 5874 u8 outer_first_vlan_type[0x2]; 5875 u8 outer_first_vlan_prio[0x3]; 5876 u8 outer_first_vlan_cfi[0x1]; 5877 u8 outer_first_vlan_vid[0xc]; 5878 5879 u8 outer_l4_type_ext[0x4]; 5880 u8 reserved_at_1a4[0x2]; 5881 u8 outer_ipsec_layer[0x2]; 5882 u8 outer_l2_type[0x2]; 5883 u8 force_lb[0x1]; 5884 u8 outer_l2_ok[0x1]; 5885 u8 outer_l3_ok[0x1]; 5886 u8 outer_l4_ok[0x1]; 5887 u8 outer_second_vlan_type[0x2]; 5888 u8 outer_second_vlan_prio[0x3]; 5889 u8 outer_second_vlan_cfi[0x1]; 5890 u8 outer_second_vlan_vid[0xc]; 5891 5892 u8 outer_smac_47_16[0x20]; 5893 5894 u8 outer_smac_15_0[0x10]; 5895 u8 inner_ipv4_checksum_ok[0x1]; 5896 u8 inner_l4_checksum_ok[0x1]; 5897 u8 outer_ipv4_checksum_ok[0x1]; 5898 u8 outer_l4_checksum_ok[0x1]; 5899 u8 inner_l3_ok[0x1]; 5900 u8 inner_l4_ok[0x1]; 5901 u8 outer_l3_ok_duplicate[0x1]; 5902 u8 outer_l4_ok_duplicate[0x1]; 5903 u8 outer_tcp_cwr[0x1]; 5904 u8 outer_tcp_ece[0x1]; 5905 u8 outer_tcp_urg[0x1]; 5906 u8 outer_tcp_ack[0x1]; 5907 u8 outer_tcp_psh[0x1]; 5908 u8 outer_tcp_rst[0x1]; 5909 u8 outer_tcp_syn[0x1]; 5910 u8 outer_tcp_fin[0x1]; 5911 }; 5912 5913 struct mlx5_ifc_match_definer_format_22_bits { 5914 u8 reserved_at_0[0x100]; 5915 5916 u8 outer_ip_src_addr[0x20]; 5917 5918 u8 outer_ip_dest_addr[0x20]; 5919 5920 u8 outer_l4_sport[0x10]; 5921 u8 outer_l4_dport[0x10]; 5922 5923 u8 reserved_at_160[0x1]; 5924 u8 sx_sniffer[0x1]; 5925 u8 functional_lb[0x1]; 5926 u8 outer_ip_frag[0x1]; 5927 u8 outer_qp_type[0x2]; 5928 u8 outer_encap_type[0x2]; 5929 u8 port_number[0x2]; 5930 u8 outer_l3_type[0x2]; 5931 u8 outer_l4_type[0x2]; 5932 u8 outer_first_vlan_type[0x2]; 5933 u8 outer_first_vlan_prio[0x3]; 5934 u8 outer_first_vlan_cfi[0x1]; 5935 u8 outer_first_vlan_vid[0xc]; 5936 5937 u8 metadata_reg_c_0[0x20]; 5938 5939 u8 outer_dmac_47_16[0x20]; 5940 5941 u8 outer_smac_47_16[0x20]; 5942 5943 u8 outer_smac_15_0[0x10]; 5944 u8 outer_dmac_15_0[0x10]; 5945 }; 5946 5947 struct mlx5_ifc_match_definer_format_23_bits { 5948 u8 reserved_at_0[0x100]; 5949 5950 u8 inner_ip_src_addr[0x20]; 5951 5952 u8 inner_ip_dest_addr[0x20]; 5953 5954 u8 inner_l4_sport[0x10]; 5955 u8 inner_l4_dport[0x10]; 5956 5957 u8 reserved_at_160[0x1]; 5958 u8 sx_sniffer[0x1]; 5959 u8 functional_lb[0x1]; 5960 u8 inner_ip_frag[0x1]; 5961 u8 inner_qp_type[0x2]; 5962 u8 inner_encap_type[0x2]; 5963 u8 port_number[0x2]; 5964 u8 inner_l3_type[0x2]; 5965 u8 inner_l4_type[0x2]; 5966 u8 inner_first_vlan_type[0x2]; 5967 u8 inner_first_vlan_prio[0x3]; 5968 u8 inner_first_vlan_cfi[0x1]; 5969 u8 inner_first_vlan_vid[0xc]; 5970 5971 u8 tunnel_header_0[0x20]; 5972 5973 u8 inner_dmac_47_16[0x20]; 5974 5975 u8 inner_smac_47_16[0x20]; 5976 5977 u8 inner_smac_15_0[0x10]; 5978 u8 inner_dmac_15_0[0x10]; 5979 }; 5980 5981 struct mlx5_ifc_match_definer_format_29_bits { 5982 u8 reserved_at_0[0xc0]; 5983 5984 u8 outer_ip_dest_addr[0x80]; 5985 5986 u8 outer_ip_src_addr[0x80]; 5987 5988 u8 outer_l4_sport[0x10]; 5989 u8 outer_l4_dport[0x10]; 5990 5991 u8 reserved_at_1e0[0x20]; 5992 }; 5993 5994 struct mlx5_ifc_match_definer_format_30_bits { 5995 u8 reserved_at_0[0xa0]; 5996 5997 u8 outer_ip_dest_addr[0x80]; 5998 5999 u8 outer_ip_src_addr[0x80]; 6000 6001 u8 outer_dmac_47_16[0x20]; 6002 6003 u8 outer_smac_47_16[0x20]; 6004 6005 u8 outer_smac_15_0[0x10]; 6006 u8 outer_dmac_15_0[0x10]; 6007 }; 6008 6009 struct mlx5_ifc_match_definer_format_31_bits { 6010 u8 reserved_at_0[0xc0]; 6011 6012 u8 inner_ip_dest_addr[0x80]; 6013 6014 u8 inner_ip_src_addr[0x80]; 6015 6016 u8 inner_l4_sport[0x10]; 6017 u8 inner_l4_dport[0x10]; 6018 6019 u8 reserved_at_1e0[0x20]; 6020 }; 6021 6022 struct mlx5_ifc_match_definer_format_32_bits { 6023 u8 reserved_at_0[0xa0]; 6024 6025 u8 inner_ip_dest_addr[0x80]; 6026 6027 u8 inner_ip_src_addr[0x80]; 6028 6029 u8 inner_dmac_47_16[0x20]; 6030 6031 u8 inner_smac_47_16[0x20]; 6032 6033 u8 inner_smac_15_0[0x10]; 6034 u8 inner_dmac_15_0[0x10]; 6035 }; 6036 6037 struct mlx5_ifc_match_definer_bits { 6038 u8 modify_field_select[0x40]; 6039 6040 u8 reserved_at_40[0x40]; 6041 6042 u8 reserved_at_80[0x10]; 6043 u8 format_id[0x10]; 6044 6045 u8 reserved_at_a0[0x160]; 6046 6047 u8 match_mask[16][0x20]; 6048 }; 6049 6050 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6051 u8 opcode[0x10]; 6052 u8 uid[0x10]; 6053 6054 u8 vhca_tunnel_id[0x10]; 6055 u8 obj_type[0x10]; 6056 6057 u8 obj_id[0x20]; 6058 6059 u8 reserved_at_60[0x3]; 6060 u8 log_obj_range[0x5]; 6061 u8 reserved_at_68[0x18]; 6062 }; 6063 6064 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6065 u8 status[0x8]; 6066 u8 reserved_at_8[0x18]; 6067 6068 u8 syndrome[0x20]; 6069 6070 u8 obj_id[0x20]; 6071 6072 u8 reserved_at_60[0x20]; 6073 }; 6074 6075 struct mlx5_ifc_create_match_definer_in_bits { 6076 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6077 6078 struct mlx5_ifc_match_definer_bits obj_context; 6079 }; 6080 6081 struct mlx5_ifc_create_match_definer_out_bits { 6082 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6083 }; 6084 6085 enum { 6086 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6087 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6088 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6089 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6090 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6091 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6092 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6093 }; 6094 6095 struct mlx5_ifc_query_flow_group_out_bits { 6096 u8 status[0x8]; 6097 u8 reserved_at_8[0x18]; 6098 6099 u8 syndrome[0x20]; 6100 6101 u8 reserved_at_40[0xa0]; 6102 6103 u8 start_flow_index[0x20]; 6104 6105 u8 reserved_at_100[0x20]; 6106 6107 u8 end_flow_index[0x20]; 6108 6109 u8 reserved_at_140[0xa0]; 6110 6111 u8 reserved_at_1e0[0x18]; 6112 u8 match_criteria_enable[0x8]; 6113 6114 struct mlx5_ifc_fte_match_param_bits match_criteria; 6115 6116 u8 reserved_at_1200[0xe00]; 6117 }; 6118 6119 struct mlx5_ifc_query_flow_group_in_bits { 6120 u8 opcode[0x10]; 6121 u8 reserved_at_10[0x10]; 6122 6123 u8 reserved_at_20[0x10]; 6124 u8 op_mod[0x10]; 6125 6126 u8 reserved_at_40[0x40]; 6127 6128 u8 table_type[0x8]; 6129 u8 reserved_at_88[0x18]; 6130 6131 u8 reserved_at_a0[0x8]; 6132 u8 table_id[0x18]; 6133 6134 u8 group_id[0x20]; 6135 6136 u8 reserved_at_e0[0x120]; 6137 }; 6138 6139 struct mlx5_ifc_query_flow_counter_out_bits { 6140 u8 status[0x8]; 6141 u8 reserved_at_8[0x18]; 6142 6143 u8 syndrome[0x20]; 6144 6145 u8 reserved_at_40[0x40]; 6146 6147 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6148 }; 6149 6150 struct mlx5_ifc_query_flow_counter_in_bits { 6151 u8 opcode[0x10]; 6152 u8 reserved_at_10[0x10]; 6153 6154 u8 reserved_at_20[0x10]; 6155 u8 op_mod[0x10]; 6156 6157 u8 reserved_at_40[0x80]; 6158 6159 u8 clear[0x1]; 6160 u8 reserved_at_c1[0xf]; 6161 u8 num_of_counters[0x10]; 6162 6163 u8 flow_counter_id[0x20]; 6164 }; 6165 6166 struct mlx5_ifc_query_esw_vport_context_out_bits { 6167 u8 status[0x8]; 6168 u8 reserved_at_8[0x18]; 6169 6170 u8 syndrome[0x20]; 6171 6172 u8 reserved_at_40[0x40]; 6173 6174 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6175 }; 6176 6177 struct mlx5_ifc_query_esw_vport_context_in_bits { 6178 u8 opcode[0x10]; 6179 u8 reserved_at_10[0x10]; 6180 6181 u8 reserved_at_20[0x10]; 6182 u8 op_mod[0x10]; 6183 6184 u8 other_vport[0x1]; 6185 u8 reserved_at_41[0xf]; 6186 u8 vport_number[0x10]; 6187 6188 u8 reserved_at_60[0x20]; 6189 }; 6190 6191 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6192 u8 status[0x8]; 6193 u8 reserved_at_8[0x18]; 6194 6195 u8 syndrome[0x20]; 6196 6197 u8 reserved_at_40[0x40]; 6198 }; 6199 6200 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6201 u8 reserved_at_0[0x1b]; 6202 u8 fdb_to_vport_reg_c_id[0x1]; 6203 u8 vport_cvlan_insert[0x1]; 6204 u8 vport_svlan_insert[0x1]; 6205 u8 vport_cvlan_strip[0x1]; 6206 u8 vport_svlan_strip[0x1]; 6207 }; 6208 6209 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6210 u8 opcode[0x10]; 6211 u8 reserved_at_10[0x10]; 6212 6213 u8 reserved_at_20[0x10]; 6214 u8 op_mod[0x10]; 6215 6216 u8 other_vport[0x1]; 6217 u8 reserved_at_41[0xf]; 6218 u8 vport_number[0x10]; 6219 6220 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6221 6222 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6223 }; 6224 6225 struct mlx5_ifc_query_eq_out_bits { 6226 u8 status[0x8]; 6227 u8 reserved_at_8[0x18]; 6228 6229 u8 syndrome[0x20]; 6230 6231 u8 reserved_at_40[0x40]; 6232 6233 struct mlx5_ifc_eqc_bits eq_context_entry; 6234 6235 u8 reserved_at_280[0x40]; 6236 6237 u8 event_bitmask[0x40]; 6238 6239 u8 reserved_at_300[0x580]; 6240 6241 u8 pas[][0x40]; 6242 }; 6243 6244 struct mlx5_ifc_query_eq_in_bits { 6245 u8 opcode[0x10]; 6246 u8 reserved_at_10[0x10]; 6247 6248 u8 reserved_at_20[0x10]; 6249 u8 op_mod[0x10]; 6250 6251 u8 reserved_at_40[0x18]; 6252 u8 eq_number[0x8]; 6253 6254 u8 reserved_at_60[0x20]; 6255 }; 6256 6257 struct mlx5_ifc_packet_reformat_context_in_bits { 6258 u8 reformat_type[0x8]; 6259 u8 reserved_at_8[0x4]; 6260 u8 reformat_param_0[0x4]; 6261 u8 reserved_at_10[0x6]; 6262 u8 reformat_data_size[0xa]; 6263 6264 u8 reformat_param_1[0x8]; 6265 u8 reserved_at_28[0x8]; 6266 u8 reformat_data[2][0x8]; 6267 6268 u8 more_reformat_data[][0x8]; 6269 }; 6270 6271 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6272 u8 status[0x8]; 6273 u8 reserved_at_8[0x18]; 6274 6275 u8 syndrome[0x20]; 6276 6277 u8 reserved_at_40[0xa0]; 6278 6279 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6280 }; 6281 6282 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6283 u8 opcode[0x10]; 6284 u8 reserved_at_10[0x10]; 6285 6286 u8 reserved_at_20[0x10]; 6287 u8 op_mod[0x10]; 6288 6289 u8 packet_reformat_id[0x20]; 6290 6291 u8 reserved_at_60[0xa0]; 6292 }; 6293 6294 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6295 u8 status[0x8]; 6296 u8 reserved_at_8[0x18]; 6297 6298 u8 syndrome[0x20]; 6299 6300 u8 packet_reformat_id[0x20]; 6301 6302 u8 reserved_at_60[0x20]; 6303 }; 6304 6305 enum { 6306 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6307 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6308 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6309 }; 6310 6311 enum mlx5_reformat_ctx_type { 6312 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6313 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6314 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6315 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6316 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6317 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6318 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6319 }; 6320 6321 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6322 u8 opcode[0x10]; 6323 u8 reserved_at_10[0x10]; 6324 6325 u8 reserved_at_20[0x10]; 6326 u8 op_mod[0x10]; 6327 6328 u8 reserved_at_40[0xa0]; 6329 6330 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6331 }; 6332 6333 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6334 u8 status[0x8]; 6335 u8 reserved_at_8[0x18]; 6336 6337 u8 syndrome[0x20]; 6338 6339 u8 reserved_at_40[0x40]; 6340 }; 6341 6342 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6343 u8 opcode[0x10]; 6344 u8 reserved_at_10[0x10]; 6345 6346 u8 reserved_20[0x10]; 6347 u8 op_mod[0x10]; 6348 6349 u8 packet_reformat_id[0x20]; 6350 6351 u8 reserved_60[0x20]; 6352 }; 6353 6354 struct mlx5_ifc_set_action_in_bits { 6355 u8 action_type[0x4]; 6356 u8 field[0xc]; 6357 u8 reserved_at_10[0x3]; 6358 u8 offset[0x5]; 6359 u8 reserved_at_18[0x3]; 6360 u8 length[0x5]; 6361 6362 u8 data[0x20]; 6363 }; 6364 6365 struct mlx5_ifc_add_action_in_bits { 6366 u8 action_type[0x4]; 6367 u8 field[0xc]; 6368 u8 reserved_at_10[0x10]; 6369 6370 u8 data[0x20]; 6371 }; 6372 6373 struct mlx5_ifc_copy_action_in_bits { 6374 u8 action_type[0x4]; 6375 u8 src_field[0xc]; 6376 u8 reserved_at_10[0x3]; 6377 u8 src_offset[0x5]; 6378 u8 reserved_at_18[0x3]; 6379 u8 length[0x5]; 6380 6381 u8 reserved_at_20[0x4]; 6382 u8 dst_field[0xc]; 6383 u8 reserved_at_30[0x3]; 6384 u8 dst_offset[0x5]; 6385 u8 reserved_at_38[0x8]; 6386 }; 6387 6388 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6389 struct mlx5_ifc_set_action_in_bits set_action_in; 6390 struct mlx5_ifc_add_action_in_bits add_action_in; 6391 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6392 u8 reserved_at_0[0x40]; 6393 }; 6394 6395 enum { 6396 MLX5_ACTION_TYPE_SET = 0x1, 6397 MLX5_ACTION_TYPE_ADD = 0x2, 6398 MLX5_ACTION_TYPE_COPY = 0x3, 6399 }; 6400 6401 enum { 6402 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6403 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6404 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6405 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6406 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6407 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6408 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6409 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6410 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6411 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6412 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6413 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6414 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6415 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6416 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6417 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6418 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6419 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6420 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6421 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6422 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6423 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6424 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6425 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6426 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6427 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6428 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6429 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6430 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6431 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6432 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6433 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6434 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6435 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6436 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6437 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6438 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6439 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6440 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6441 }; 6442 6443 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6444 u8 status[0x8]; 6445 u8 reserved_at_8[0x18]; 6446 6447 u8 syndrome[0x20]; 6448 6449 u8 modify_header_id[0x20]; 6450 6451 u8 reserved_at_60[0x20]; 6452 }; 6453 6454 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6455 u8 opcode[0x10]; 6456 u8 reserved_at_10[0x10]; 6457 6458 u8 reserved_at_20[0x10]; 6459 u8 op_mod[0x10]; 6460 6461 u8 reserved_at_40[0x20]; 6462 6463 u8 table_type[0x8]; 6464 u8 reserved_at_68[0x10]; 6465 u8 num_of_actions[0x8]; 6466 6467 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6468 }; 6469 6470 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6471 u8 status[0x8]; 6472 u8 reserved_at_8[0x18]; 6473 6474 u8 syndrome[0x20]; 6475 6476 u8 reserved_at_40[0x40]; 6477 }; 6478 6479 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6480 u8 opcode[0x10]; 6481 u8 reserved_at_10[0x10]; 6482 6483 u8 reserved_at_20[0x10]; 6484 u8 op_mod[0x10]; 6485 6486 u8 modify_header_id[0x20]; 6487 6488 u8 reserved_at_60[0x20]; 6489 }; 6490 6491 struct mlx5_ifc_query_modify_header_context_in_bits { 6492 u8 opcode[0x10]; 6493 u8 uid[0x10]; 6494 6495 u8 reserved_at_20[0x10]; 6496 u8 op_mod[0x10]; 6497 6498 u8 modify_header_id[0x20]; 6499 6500 u8 reserved_at_60[0xa0]; 6501 }; 6502 6503 struct mlx5_ifc_query_dct_out_bits { 6504 u8 status[0x8]; 6505 u8 reserved_at_8[0x18]; 6506 6507 u8 syndrome[0x20]; 6508 6509 u8 reserved_at_40[0x40]; 6510 6511 struct mlx5_ifc_dctc_bits dct_context_entry; 6512 6513 u8 reserved_at_280[0x180]; 6514 }; 6515 6516 struct mlx5_ifc_query_dct_in_bits { 6517 u8 opcode[0x10]; 6518 u8 reserved_at_10[0x10]; 6519 6520 u8 reserved_at_20[0x10]; 6521 u8 op_mod[0x10]; 6522 6523 u8 reserved_at_40[0x8]; 6524 u8 dctn[0x18]; 6525 6526 u8 reserved_at_60[0x20]; 6527 }; 6528 6529 struct mlx5_ifc_query_cq_out_bits { 6530 u8 status[0x8]; 6531 u8 reserved_at_8[0x18]; 6532 6533 u8 syndrome[0x20]; 6534 6535 u8 reserved_at_40[0x40]; 6536 6537 struct mlx5_ifc_cqc_bits cq_context; 6538 6539 u8 reserved_at_280[0x600]; 6540 6541 u8 pas[][0x40]; 6542 }; 6543 6544 struct mlx5_ifc_query_cq_in_bits { 6545 u8 opcode[0x10]; 6546 u8 reserved_at_10[0x10]; 6547 6548 u8 reserved_at_20[0x10]; 6549 u8 op_mod[0x10]; 6550 6551 u8 reserved_at_40[0x8]; 6552 u8 cqn[0x18]; 6553 6554 u8 reserved_at_60[0x20]; 6555 }; 6556 6557 struct mlx5_ifc_query_cong_status_out_bits { 6558 u8 status[0x8]; 6559 u8 reserved_at_8[0x18]; 6560 6561 u8 syndrome[0x20]; 6562 6563 u8 reserved_at_40[0x20]; 6564 6565 u8 enable[0x1]; 6566 u8 tag_enable[0x1]; 6567 u8 reserved_at_62[0x1e]; 6568 }; 6569 6570 struct mlx5_ifc_query_cong_status_in_bits { 6571 u8 opcode[0x10]; 6572 u8 reserved_at_10[0x10]; 6573 6574 u8 reserved_at_20[0x10]; 6575 u8 op_mod[0x10]; 6576 6577 u8 reserved_at_40[0x18]; 6578 u8 priority[0x4]; 6579 u8 cong_protocol[0x4]; 6580 6581 u8 reserved_at_60[0x20]; 6582 }; 6583 6584 struct mlx5_ifc_query_cong_statistics_out_bits { 6585 u8 status[0x8]; 6586 u8 reserved_at_8[0x18]; 6587 6588 u8 syndrome[0x20]; 6589 6590 u8 reserved_at_40[0x40]; 6591 6592 u8 rp_cur_flows[0x20]; 6593 6594 u8 sum_flows[0x20]; 6595 6596 u8 rp_cnp_ignored_high[0x20]; 6597 6598 u8 rp_cnp_ignored_low[0x20]; 6599 6600 u8 rp_cnp_handled_high[0x20]; 6601 6602 u8 rp_cnp_handled_low[0x20]; 6603 6604 u8 reserved_at_140[0x100]; 6605 6606 u8 time_stamp_high[0x20]; 6607 6608 u8 time_stamp_low[0x20]; 6609 6610 u8 accumulators_period[0x20]; 6611 6612 u8 np_ecn_marked_roce_packets_high[0x20]; 6613 6614 u8 np_ecn_marked_roce_packets_low[0x20]; 6615 6616 u8 np_cnp_sent_high[0x20]; 6617 6618 u8 np_cnp_sent_low[0x20]; 6619 6620 u8 reserved_at_320[0x560]; 6621 }; 6622 6623 struct mlx5_ifc_query_cong_statistics_in_bits { 6624 u8 opcode[0x10]; 6625 u8 reserved_at_10[0x10]; 6626 6627 u8 reserved_at_20[0x10]; 6628 u8 op_mod[0x10]; 6629 6630 u8 clear[0x1]; 6631 u8 reserved_at_41[0x1f]; 6632 6633 u8 reserved_at_60[0x20]; 6634 }; 6635 6636 struct mlx5_ifc_query_cong_params_out_bits { 6637 u8 status[0x8]; 6638 u8 reserved_at_8[0x18]; 6639 6640 u8 syndrome[0x20]; 6641 6642 u8 reserved_at_40[0x40]; 6643 6644 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6645 }; 6646 6647 struct mlx5_ifc_query_cong_params_in_bits { 6648 u8 opcode[0x10]; 6649 u8 reserved_at_10[0x10]; 6650 6651 u8 reserved_at_20[0x10]; 6652 u8 op_mod[0x10]; 6653 6654 u8 reserved_at_40[0x1c]; 6655 u8 cong_protocol[0x4]; 6656 6657 u8 reserved_at_60[0x20]; 6658 }; 6659 6660 struct mlx5_ifc_query_adapter_out_bits { 6661 u8 status[0x8]; 6662 u8 reserved_at_8[0x18]; 6663 6664 u8 syndrome[0x20]; 6665 6666 u8 reserved_at_40[0x40]; 6667 6668 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6669 }; 6670 6671 struct mlx5_ifc_query_adapter_in_bits { 6672 u8 opcode[0x10]; 6673 u8 reserved_at_10[0x10]; 6674 6675 u8 reserved_at_20[0x10]; 6676 u8 op_mod[0x10]; 6677 6678 u8 reserved_at_40[0x40]; 6679 }; 6680 6681 struct mlx5_ifc_qp_2rst_out_bits { 6682 u8 status[0x8]; 6683 u8 reserved_at_8[0x18]; 6684 6685 u8 syndrome[0x20]; 6686 6687 u8 reserved_at_40[0x40]; 6688 }; 6689 6690 struct mlx5_ifc_qp_2rst_in_bits { 6691 u8 opcode[0x10]; 6692 u8 uid[0x10]; 6693 6694 u8 reserved_at_20[0x10]; 6695 u8 op_mod[0x10]; 6696 6697 u8 reserved_at_40[0x8]; 6698 u8 qpn[0x18]; 6699 6700 u8 reserved_at_60[0x20]; 6701 }; 6702 6703 struct mlx5_ifc_qp_2err_out_bits { 6704 u8 status[0x8]; 6705 u8 reserved_at_8[0x18]; 6706 6707 u8 syndrome[0x20]; 6708 6709 u8 reserved_at_40[0x40]; 6710 }; 6711 6712 struct mlx5_ifc_qp_2err_in_bits { 6713 u8 opcode[0x10]; 6714 u8 uid[0x10]; 6715 6716 u8 reserved_at_20[0x10]; 6717 u8 op_mod[0x10]; 6718 6719 u8 reserved_at_40[0x8]; 6720 u8 qpn[0x18]; 6721 6722 u8 reserved_at_60[0x20]; 6723 }; 6724 6725 struct mlx5_ifc_page_fault_resume_out_bits { 6726 u8 status[0x8]; 6727 u8 reserved_at_8[0x18]; 6728 6729 u8 syndrome[0x20]; 6730 6731 u8 reserved_at_40[0x40]; 6732 }; 6733 6734 struct mlx5_ifc_page_fault_resume_in_bits { 6735 u8 opcode[0x10]; 6736 u8 reserved_at_10[0x10]; 6737 6738 u8 reserved_at_20[0x10]; 6739 u8 op_mod[0x10]; 6740 6741 u8 error[0x1]; 6742 u8 reserved_at_41[0x4]; 6743 u8 page_fault_type[0x3]; 6744 u8 wq_number[0x18]; 6745 6746 u8 reserved_at_60[0x8]; 6747 u8 token[0x18]; 6748 }; 6749 6750 struct mlx5_ifc_nop_out_bits { 6751 u8 status[0x8]; 6752 u8 reserved_at_8[0x18]; 6753 6754 u8 syndrome[0x20]; 6755 6756 u8 reserved_at_40[0x40]; 6757 }; 6758 6759 struct mlx5_ifc_nop_in_bits { 6760 u8 opcode[0x10]; 6761 u8 reserved_at_10[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 reserved_at_40[0x40]; 6767 }; 6768 6769 struct mlx5_ifc_modify_vport_state_out_bits { 6770 u8 status[0x8]; 6771 u8 reserved_at_8[0x18]; 6772 6773 u8 syndrome[0x20]; 6774 6775 u8 reserved_at_40[0x40]; 6776 }; 6777 6778 struct mlx5_ifc_modify_vport_state_in_bits { 6779 u8 opcode[0x10]; 6780 u8 reserved_at_10[0x10]; 6781 6782 u8 reserved_at_20[0x10]; 6783 u8 op_mod[0x10]; 6784 6785 u8 other_vport[0x1]; 6786 u8 reserved_at_41[0xf]; 6787 u8 vport_number[0x10]; 6788 6789 u8 reserved_at_60[0x18]; 6790 u8 admin_state[0x4]; 6791 u8 reserved_at_7c[0x4]; 6792 }; 6793 6794 struct mlx5_ifc_modify_tis_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_at_8[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 reserved_at_40[0x40]; 6801 }; 6802 6803 struct mlx5_ifc_modify_tis_bitmask_bits { 6804 u8 reserved_at_0[0x20]; 6805 6806 u8 reserved_at_20[0x1d]; 6807 u8 lag_tx_port_affinity[0x1]; 6808 u8 strict_lag_tx_port_affinity[0x1]; 6809 u8 prio[0x1]; 6810 }; 6811 6812 struct mlx5_ifc_modify_tis_in_bits { 6813 u8 opcode[0x10]; 6814 u8 uid[0x10]; 6815 6816 u8 reserved_at_20[0x10]; 6817 u8 op_mod[0x10]; 6818 6819 u8 reserved_at_40[0x8]; 6820 u8 tisn[0x18]; 6821 6822 u8 reserved_at_60[0x20]; 6823 6824 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6825 6826 u8 reserved_at_c0[0x40]; 6827 6828 struct mlx5_ifc_tisc_bits ctx; 6829 }; 6830 6831 struct mlx5_ifc_modify_tir_bitmask_bits { 6832 u8 reserved_at_0[0x20]; 6833 6834 u8 reserved_at_20[0x1b]; 6835 u8 self_lb_en[0x1]; 6836 u8 reserved_at_3c[0x1]; 6837 u8 hash[0x1]; 6838 u8 reserved_at_3e[0x1]; 6839 u8 packet_merge[0x1]; 6840 }; 6841 6842 struct mlx5_ifc_modify_tir_out_bits { 6843 u8 status[0x8]; 6844 u8 reserved_at_8[0x18]; 6845 6846 u8 syndrome[0x20]; 6847 6848 u8 reserved_at_40[0x40]; 6849 }; 6850 6851 struct mlx5_ifc_modify_tir_in_bits { 6852 u8 opcode[0x10]; 6853 u8 uid[0x10]; 6854 6855 u8 reserved_at_20[0x10]; 6856 u8 op_mod[0x10]; 6857 6858 u8 reserved_at_40[0x8]; 6859 u8 tirn[0x18]; 6860 6861 u8 reserved_at_60[0x20]; 6862 6863 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6864 6865 u8 reserved_at_c0[0x40]; 6866 6867 struct mlx5_ifc_tirc_bits ctx; 6868 }; 6869 6870 struct mlx5_ifc_modify_sq_out_bits { 6871 u8 status[0x8]; 6872 u8 reserved_at_8[0x18]; 6873 6874 u8 syndrome[0x20]; 6875 6876 u8 reserved_at_40[0x40]; 6877 }; 6878 6879 struct mlx5_ifc_modify_sq_in_bits { 6880 u8 opcode[0x10]; 6881 u8 uid[0x10]; 6882 6883 u8 reserved_at_20[0x10]; 6884 u8 op_mod[0x10]; 6885 6886 u8 sq_state[0x4]; 6887 u8 reserved_at_44[0x4]; 6888 u8 sqn[0x18]; 6889 6890 u8 reserved_at_60[0x20]; 6891 6892 u8 modify_bitmask[0x40]; 6893 6894 u8 reserved_at_c0[0x40]; 6895 6896 struct mlx5_ifc_sqc_bits ctx; 6897 }; 6898 6899 struct mlx5_ifc_modify_scheduling_element_out_bits { 6900 u8 status[0x8]; 6901 u8 reserved_at_8[0x18]; 6902 6903 u8 syndrome[0x20]; 6904 6905 u8 reserved_at_40[0x1c0]; 6906 }; 6907 6908 enum { 6909 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6910 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6911 }; 6912 6913 struct mlx5_ifc_modify_scheduling_element_in_bits { 6914 u8 opcode[0x10]; 6915 u8 reserved_at_10[0x10]; 6916 6917 u8 reserved_at_20[0x10]; 6918 u8 op_mod[0x10]; 6919 6920 u8 scheduling_hierarchy[0x8]; 6921 u8 reserved_at_48[0x18]; 6922 6923 u8 scheduling_element_id[0x20]; 6924 6925 u8 reserved_at_80[0x20]; 6926 6927 u8 modify_bitmask[0x20]; 6928 6929 u8 reserved_at_c0[0x40]; 6930 6931 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6932 6933 u8 reserved_at_300[0x100]; 6934 }; 6935 6936 struct mlx5_ifc_modify_rqt_out_bits { 6937 u8 status[0x8]; 6938 u8 reserved_at_8[0x18]; 6939 6940 u8 syndrome[0x20]; 6941 6942 u8 reserved_at_40[0x40]; 6943 }; 6944 6945 struct mlx5_ifc_rqt_bitmask_bits { 6946 u8 reserved_at_0[0x20]; 6947 6948 u8 reserved_at_20[0x1f]; 6949 u8 rqn_list[0x1]; 6950 }; 6951 6952 struct mlx5_ifc_modify_rqt_in_bits { 6953 u8 opcode[0x10]; 6954 u8 uid[0x10]; 6955 6956 u8 reserved_at_20[0x10]; 6957 u8 op_mod[0x10]; 6958 6959 u8 reserved_at_40[0x8]; 6960 u8 rqtn[0x18]; 6961 6962 u8 reserved_at_60[0x20]; 6963 6964 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6965 6966 u8 reserved_at_c0[0x40]; 6967 6968 struct mlx5_ifc_rqtc_bits ctx; 6969 }; 6970 6971 struct mlx5_ifc_modify_rq_out_bits { 6972 u8 status[0x8]; 6973 u8 reserved_at_8[0x18]; 6974 6975 u8 syndrome[0x20]; 6976 6977 u8 reserved_at_40[0x40]; 6978 }; 6979 6980 enum { 6981 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6982 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6983 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6984 }; 6985 6986 struct mlx5_ifc_modify_rq_in_bits { 6987 u8 opcode[0x10]; 6988 u8 uid[0x10]; 6989 6990 u8 reserved_at_20[0x10]; 6991 u8 op_mod[0x10]; 6992 6993 u8 rq_state[0x4]; 6994 u8 reserved_at_44[0x4]; 6995 u8 rqn[0x18]; 6996 6997 u8 reserved_at_60[0x20]; 6998 6999 u8 modify_bitmask[0x40]; 7000 7001 u8 reserved_at_c0[0x40]; 7002 7003 struct mlx5_ifc_rqc_bits ctx; 7004 }; 7005 7006 struct mlx5_ifc_modify_rmp_out_bits { 7007 u8 status[0x8]; 7008 u8 reserved_at_8[0x18]; 7009 7010 u8 syndrome[0x20]; 7011 7012 u8 reserved_at_40[0x40]; 7013 }; 7014 7015 struct mlx5_ifc_rmp_bitmask_bits { 7016 u8 reserved_at_0[0x20]; 7017 7018 u8 reserved_at_20[0x1f]; 7019 u8 lwm[0x1]; 7020 }; 7021 7022 struct mlx5_ifc_modify_rmp_in_bits { 7023 u8 opcode[0x10]; 7024 u8 uid[0x10]; 7025 7026 u8 reserved_at_20[0x10]; 7027 u8 op_mod[0x10]; 7028 7029 u8 rmp_state[0x4]; 7030 u8 reserved_at_44[0x4]; 7031 u8 rmpn[0x18]; 7032 7033 u8 reserved_at_60[0x20]; 7034 7035 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7036 7037 u8 reserved_at_c0[0x40]; 7038 7039 struct mlx5_ifc_rmpc_bits ctx; 7040 }; 7041 7042 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7043 u8 status[0x8]; 7044 u8 reserved_at_8[0x18]; 7045 7046 u8 syndrome[0x20]; 7047 7048 u8 reserved_at_40[0x40]; 7049 }; 7050 7051 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7052 u8 reserved_at_0[0x12]; 7053 u8 affiliation[0x1]; 7054 u8 reserved_at_13[0x1]; 7055 u8 disable_uc_local_lb[0x1]; 7056 u8 disable_mc_local_lb[0x1]; 7057 u8 node_guid[0x1]; 7058 u8 port_guid[0x1]; 7059 u8 min_inline[0x1]; 7060 u8 mtu[0x1]; 7061 u8 change_event[0x1]; 7062 u8 promisc[0x1]; 7063 u8 permanent_address[0x1]; 7064 u8 addresses_list[0x1]; 7065 u8 roce_en[0x1]; 7066 u8 reserved_at_1f[0x1]; 7067 }; 7068 7069 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7070 u8 opcode[0x10]; 7071 u8 reserved_at_10[0x10]; 7072 7073 u8 reserved_at_20[0x10]; 7074 u8 op_mod[0x10]; 7075 7076 u8 other_vport[0x1]; 7077 u8 reserved_at_41[0xf]; 7078 u8 vport_number[0x10]; 7079 7080 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7081 7082 u8 reserved_at_80[0x780]; 7083 7084 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7085 }; 7086 7087 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7088 u8 status[0x8]; 7089 u8 reserved_at_8[0x18]; 7090 7091 u8 syndrome[0x20]; 7092 7093 u8 reserved_at_40[0x40]; 7094 }; 7095 7096 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7097 u8 opcode[0x10]; 7098 u8 reserved_at_10[0x10]; 7099 7100 u8 reserved_at_20[0x10]; 7101 u8 op_mod[0x10]; 7102 7103 u8 other_vport[0x1]; 7104 u8 reserved_at_41[0xb]; 7105 u8 port_num[0x4]; 7106 u8 vport_number[0x10]; 7107 7108 u8 reserved_at_60[0x20]; 7109 7110 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7111 }; 7112 7113 struct mlx5_ifc_modify_cq_out_bits { 7114 u8 status[0x8]; 7115 u8 reserved_at_8[0x18]; 7116 7117 u8 syndrome[0x20]; 7118 7119 u8 reserved_at_40[0x40]; 7120 }; 7121 7122 enum { 7123 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7124 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7125 }; 7126 7127 struct mlx5_ifc_modify_cq_in_bits { 7128 u8 opcode[0x10]; 7129 u8 uid[0x10]; 7130 7131 u8 reserved_at_20[0x10]; 7132 u8 op_mod[0x10]; 7133 7134 u8 reserved_at_40[0x8]; 7135 u8 cqn[0x18]; 7136 7137 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7138 7139 struct mlx5_ifc_cqc_bits cq_context; 7140 7141 u8 reserved_at_280[0x60]; 7142 7143 u8 cq_umem_valid[0x1]; 7144 u8 reserved_at_2e1[0x1f]; 7145 7146 u8 reserved_at_300[0x580]; 7147 7148 u8 pas[][0x40]; 7149 }; 7150 7151 struct mlx5_ifc_modify_cong_status_out_bits { 7152 u8 status[0x8]; 7153 u8 reserved_at_8[0x18]; 7154 7155 u8 syndrome[0x20]; 7156 7157 u8 reserved_at_40[0x40]; 7158 }; 7159 7160 struct mlx5_ifc_modify_cong_status_in_bits { 7161 u8 opcode[0x10]; 7162 u8 reserved_at_10[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 reserved_at_40[0x18]; 7168 u8 priority[0x4]; 7169 u8 cong_protocol[0x4]; 7170 7171 u8 enable[0x1]; 7172 u8 tag_enable[0x1]; 7173 u8 reserved_at_62[0x1e]; 7174 }; 7175 7176 struct mlx5_ifc_modify_cong_params_out_bits { 7177 u8 status[0x8]; 7178 u8 reserved_at_8[0x18]; 7179 7180 u8 syndrome[0x20]; 7181 7182 u8 reserved_at_40[0x40]; 7183 }; 7184 7185 struct mlx5_ifc_modify_cong_params_in_bits { 7186 u8 opcode[0x10]; 7187 u8 reserved_at_10[0x10]; 7188 7189 u8 reserved_at_20[0x10]; 7190 u8 op_mod[0x10]; 7191 7192 u8 reserved_at_40[0x1c]; 7193 u8 cong_protocol[0x4]; 7194 7195 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7196 7197 u8 reserved_at_80[0x80]; 7198 7199 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7200 }; 7201 7202 struct mlx5_ifc_manage_pages_out_bits { 7203 u8 status[0x8]; 7204 u8 reserved_at_8[0x18]; 7205 7206 u8 syndrome[0x20]; 7207 7208 u8 output_num_entries[0x20]; 7209 7210 u8 reserved_at_60[0x20]; 7211 7212 u8 pas[][0x40]; 7213 }; 7214 7215 enum { 7216 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7217 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7218 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7219 }; 7220 7221 struct mlx5_ifc_manage_pages_in_bits { 7222 u8 opcode[0x10]; 7223 u8 reserved_at_10[0x10]; 7224 7225 u8 reserved_at_20[0x10]; 7226 u8 op_mod[0x10]; 7227 7228 u8 embedded_cpu_function[0x1]; 7229 u8 reserved_at_41[0xf]; 7230 u8 function_id[0x10]; 7231 7232 u8 input_num_entries[0x20]; 7233 7234 u8 pas[][0x40]; 7235 }; 7236 7237 struct mlx5_ifc_mad_ifc_out_bits { 7238 u8 status[0x8]; 7239 u8 reserved_at_8[0x18]; 7240 7241 u8 syndrome[0x20]; 7242 7243 u8 reserved_at_40[0x40]; 7244 7245 u8 response_mad_packet[256][0x8]; 7246 }; 7247 7248 struct mlx5_ifc_mad_ifc_in_bits { 7249 u8 opcode[0x10]; 7250 u8 reserved_at_10[0x10]; 7251 7252 u8 reserved_at_20[0x10]; 7253 u8 op_mod[0x10]; 7254 7255 u8 remote_lid[0x10]; 7256 u8 reserved_at_50[0x8]; 7257 u8 port[0x8]; 7258 7259 u8 reserved_at_60[0x20]; 7260 7261 u8 mad[256][0x8]; 7262 }; 7263 7264 struct mlx5_ifc_init_hca_out_bits { 7265 u8 status[0x8]; 7266 u8 reserved_at_8[0x18]; 7267 7268 u8 syndrome[0x20]; 7269 7270 u8 reserved_at_40[0x40]; 7271 }; 7272 7273 struct mlx5_ifc_init_hca_in_bits { 7274 u8 opcode[0x10]; 7275 u8 reserved_at_10[0x10]; 7276 7277 u8 reserved_at_20[0x10]; 7278 u8 op_mod[0x10]; 7279 7280 u8 reserved_at_40[0x20]; 7281 7282 u8 reserved_at_60[0x2]; 7283 u8 sw_vhca_id[0xe]; 7284 u8 reserved_at_70[0x10]; 7285 7286 u8 sw_owner_id[4][0x20]; 7287 }; 7288 7289 struct mlx5_ifc_init2rtr_qp_out_bits { 7290 u8 status[0x8]; 7291 u8 reserved_at_8[0x18]; 7292 7293 u8 syndrome[0x20]; 7294 7295 u8 reserved_at_40[0x20]; 7296 u8 ece[0x20]; 7297 }; 7298 7299 struct mlx5_ifc_init2rtr_qp_in_bits { 7300 u8 opcode[0x10]; 7301 u8 uid[0x10]; 7302 7303 u8 reserved_at_20[0x10]; 7304 u8 op_mod[0x10]; 7305 7306 u8 reserved_at_40[0x8]; 7307 u8 qpn[0x18]; 7308 7309 u8 reserved_at_60[0x20]; 7310 7311 u8 opt_param_mask[0x20]; 7312 7313 u8 ece[0x20]; 7314 7315 struct mlx5_ifc_qpc_bits qpc; 7316 7317 u8 reserved_at_800[0x80]; 7318 }; 7319 7320 struct mlx5_ifc_init2init_qp_out_bits { 7321 u8 status[0x8]; 7322 u8 reserved_at_8[0x18]; 7323 7324 u8 syndrome[0x20]; 7325 7326 u8 reserved_at_40[0x20]; 7327 u8 ece[0x20]; 7328 }; 7329 7330 struct mlx5_ifc_init2init_qp_in_bits { 7331 u8 opcode[0x10]; 7332 u8 uid[0x10]; 7333 7334 u8 reserved_at_20[0x10]; 7335 u8 op_mod[0x10]; 7336 7337 u8 reserved_at_40[0x8]; 7338 u8 qpn[0x18]; 7339 7340 u8 reserved_at_60[0x20]; 7341 7342 u8 opt_param_mask[0x20]; 7343 7344 u8 ece[0x20]; 7345 7346 struct mlx5_ifc_qpc_bits qpc; 7347 7348 u8 reserved_at_800[0x80]; 7349 }; 7350 7351 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7352 u8 status[0x8]; 7353 u8 reserved_at_8[0x18]; 7354 7355 u8 syndrome[0x20]; 7356 7357 u8 reserved_at_40[0x40]; 7358 7359 u8 packet_headers_log[128][0x8]; 7360 7361 u8 packet_syndrome[64][0x8]; 7362 }; 7363 7364 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7365 u8 opcode[0x10]; 7366 u8 reserved_at_10[0x10]; 7367 7368 u8 reserved_at_20[0x10]; 7369 u8 op_mod[0x10]; 7370 7371 u8 reserved_at_40[0x40]; 7372 }; 7373 7374 struct mlx5_ifc_gen_eqe_in_bits { 7375 u8 opcode[0x10]; 7376 u8 reserved_at_10[0x10]; 7377 7378 u8 reserved_at_20[0x10]; 7379 u8 op_mod[0x10]; 7380 7381 u8 reserved_at_40[0x18]; 7382 u8 eq_number[0x8]; 7383 7384 u8 reserved_at_60[0x20]; 7385 7386 u8 eqe[64][0x8]; 7387 }; 7388 7389 struct mlx5_ifc_gen_eq_out_bits { 7390 u8 status[0x8]; 7391 u8 reserved_at_8[0x18]; 7392 7393 u8 syndrome[0x20]; 7394 7395 u8 reserved_at_40[0x40]; 7396 }; 7397 7398 struct mlx5_ifc_enable_hca_out_bits { 7399 u8 status[0x8]; 7400 u8 reserved_at_8[0x18]; 7401 7402 u8 syndrome[0x20]; 7403 7404 u8 reserved_at_40[0x20]; 7405 }; 7406 7407 struct mlx5_ifc_enable_hca_in_bits { 7408 u8 opcode[0x10]; 7409 u8 reserved_at_10[0x10]; 7410 7411 u8 reserved_at_20[0x10]; 7412 u8 op_mod[0x10]; 7413 7414 u8 embedded_cpu_function[0x1]; 7415 u8 reserved_at_41[0xf]; 7416 u8 function_id[0x10]; 7417 7418 u8 reserved_at_60[0x20]; 7419 }; 7420 7421 struct mlx5_ifc_drain_dct_out_bits { 7422 u8 status[0x8]; 7423 u8 reserved_at_8[0x18]; 7424 7425 u8 syndrome[0x20]; 7426 7427 u8 reserved_at_40[0x40]; 7428 }; 7429 7430 struct mlx5_ifc_drain_dct_in_bits { 7431 u8 opcode[0x10]; 7432 u8 uid[0x10]; 7433 7434 u8 reserved_at_20[0x10]; 7435 u8 op_mod[0x10]; 7436 7437 u8 reserved_at_40[0x8]; 7438 u8 dctn[0x18]; 7439 7440 u8 reserved_at_60[0x20]; 7441 }; 7442 7443 struct mlx5_ifc_disable_hca_out_bits { 7444 u8 status[0x8]; 7445 u8 reserved_at_8[0x18]; 7446 7447 u8 syndrome[0x20]; 7448 7449 u8 reserved_at_40[0x20]; 7450 }; 7451 7452 struct mlx5_ifc_disable_hca_in_bits { 7453 u8 opcode[0x10]; 7454 u8 reserved_at_10[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 embedded_cpu_function[0x1]; 7460 u8 reserved_at_41[0xf]; 7461 u8 function_id[0x10]; 7462 7463 u8 reserved_at_60[0x20]; 7464 }; 7465 7466 struct mlx5_ifc_detach_from_mcg_out_bits { 7467 u8 status[0x8]; 7468 u8 reserved_at_8[0x18]; 7469 7470 u8 syndrome[0x20]; 7471 7472 u8 reserved_at_40[0x40]; 7473 }; 7474 7475 struct mlx5_ifc_detach_from_mcg_in_bits { 7476 u8 opcode[0x10]; 7477 u8 uid[0x10]; 7478 7479 u8 reserved_at_20[0x10]; 7480 u8 op_mod[0x10]; 7481 7482 u8 reserved_at_40[0x8]; 7483 u8 qpn[0x18]; 7484 7485 u8 reserved_at_60[0x20]; 7486 7487 u8 multicast_gid[16][0x8]; 7488 }; 7489 7490 struct mlx5_ifc_destroy_xrq_out_bits { 7491 u8 status[0x8]; 7492 u8 reserved_at_8[0x18]; 7493 7494 u8 syndrome[0x20]; 7495 7496 u8 reserved_at_40[0x40]; 7497 }; 7498 7499 struct mlx5_ifc_destroy_xrq_in_bits { 7500 u8 opcode[0x10]; 7501 u8 uid[0x10]; 7502 7503 u8 reserved_at_20[0x10]; 7504 u8 op_mod[0x10]; 7505 7506 u8 reserved_at_40[0x8]; 7507 u8 xrqn[0x18]; 7508 7509 u8 reserved_at_60[0x20]; 7510 }; 7511 7512 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7513 u8 status[0x8]; 7514 u8 reserved_at_8[0x18]; 7515 7516 u8 syndrome[0x20]; 7517 7518 u8 reserved_at_40[0x40]; 7519 }; 7520 7521 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7522 u8 opcode[0x10]; 7523 u8 uid[0x10]; 7524 7525 u8 reserved_at_20[0x10]; 7526 u8 op_mod[0x10]; 7527 7528 u8 reserved_at_40[0x8]; 7529 u8 xrc_srqn[0x18]; 7530 7531 u8 reserved_at_60[0x20]; 7532 }; 7533 7534 struct mlx5_ifc_destroy_tis_out_bits { 7535 u8 status[0x8]; 7536 u8 reserved_at_8[0x18]; 7537 7538 u8 syndrome[0x20]; 7539 7540 u8 reserved_at_40[0x40]; 7541 }; 7542 7543 struct mlx5_ifc_destroy_tis_in_bits { 7544 u8 opcode[0x10]; 7545 u8 uid[0x10]; 7546 7547 u8 reserved_at_20[0x10]; 7548 u8 op_mod[0x10]; 7549 7550 u8 reserved_at_40[0x8]; 7551 u8 tisn[0x18]; 7552 7553 u8 reserved_at_60[0x20]; 7554 }; 7555 7556 struct mlx5_ifc_destroy_tir_out_bits { 7557 u8 status[0x8]; 7558 u8 reserved_at_8[0x18]; 7559 7560 u8 syndrome[0x20]; 7561 7562 u8 reserved_at_40[0x40]; 7563 }; 7564 7565 struct mlx5_ifc_destroy_tir_in_bits { 7566 u8 opcode[0x10]; 7567 u8 uid[0x10]; 7568 7569 u8 reserved_at_20[0x10]; 7570 u8 op_mod[0x10]; 7571 7572 u8 reserved_at_40[0x8]; 7573 u8 tirn[0x18]; 7574 7575 u8 reserved_at_60[0x20]; 7576 }; 7577 7578 struct mlx5_ifc_destroy_srq_out_bits { 7579 u8 status[0x8]; 7580 u8 reserved_at_8[0x18]; 7581 7582 u8 syndrome[0x20]; 7583 7584 u8 reserved_at_40[0x40]; 7585 }; 7586 7587 struct mlx5_ifc_destroy_srq_in_bits { 7588 u8 opcode[0x10]; 7589 u8 uid[0x10]; 7590 7591 u8 reserved_at_20[0x10]; 7592 u8 op_mod[0x10]; 7593 7594 u8 reserved_at_40[0x8]; 7595 u8 srqn[0x18]; 7596 7597 u8 reserved_at_60[0x20]; 7598 }; 7599 7600 struct mlx5_ifc_destroy_sq_out_bits { 7601 u8 status[0x8]; 7602 u8 reserved_at_8[0x18]; 7603 7604 u8 syndrome[0x20]; 7605 7606 u8 reserved_at_40[0x40]; 7607 }; 7608 7609 struct mlx5_ifc_destroy_sq_in_bits { 7610 u8 opcode[0x10]; 7611 u8 uid[0x10]; 7612 7613 u8 reserved_at_20[0x10]; 7614 u8 op_mod[0x10]; 7615 7616 u8 reserved_at_40[0x8]; 7617 u8 sqn[0x18]; 7618 7619 u8 reserved_at_60[0x20]; 7620 }; 7621 7622 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7623 u8 status[0x8]; 7624 u8 reserved_at_8[0x18]; 7625 7626 u8 syndrome[0x20]; 7627 7628 u8 reserved_at_40[0x1c0]; 7629 }; 7630 7631 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7632 u8 opcode[0x10]; 7633 u8 reserved_at_10[0x10]; 7634 7635 u8 reserved_at_20[0x10]; 7636 u8 op_mod[0x10]; 7637 7638 u8 scheduling_hierarchy[0x8]; 7639 u8 reserved_at_48[0x18]; 7640 7641 u8 scheduling_element_id[0x20]; 7642 7643 u8 reserved_at_80[0x180]; 7644 }; 7645 7646 struct mlx5_ifc_destroy_rqt_out_bits { 7647 u8 status[0x8]; 7648 u8 reserved_at_8[0x18]; 7649 7650 u8 syndrome[0x20]; 7651 7652 u8 reserved_at_40[0x40]; 7653 }; 7654 7655 struct mlx5_ifc_destroy_rqt_in_bits { 7656 u8 opcode[0x10]; 7657 u8 uid[0x10]; 7658 7659 u8 reserved_at_20[0x10]; 7660 u8 op_mod[0x10]; 7661 7662 u8 reserved_at_40[0x8]; 7663 u8 rqtn[0x18]; 7664 7665 u8 reserved_at_60[0x20]; 7666 }; 7667 7668 struct mlx5_ifc_destroy_rq_out_bits { 7669 u8 status[0x8]; 7670 u8 reserved_at_8[0x18]; 7671 7672 u8 syndrome[0x20]; 7673 7674 u8 reserved_at_40[0x40]; 7675 }; 7676 7677 struct mlx5_ifc_destroy_rq_in_bits { 7678 u8 opcode[0x10]; 7679 u8 uid[0x10]; 7680 7681 u8 reserved_at_20[0x10]; 7682 u8 op_mod[0x10]; 7683 7684 u8 reserved_at_40[0x8]; 7685 u8 rqn[0x18]; 7686 7687 u8 reserved_at_60[0x20]; 7688 }; 7689 7690 struct mlx5_ifc_set_delay_drop_params_in_bits { 7691 u8 opcode[0x10]; 7692 u8 reserved_at_10[0x10]; 7693 7694 u8 reserved_at_20[0x10]; 7695 u8 op_mod[0x10]; 7696 7697 u8 reserved_at_40[0x20]; 7698 7699 u8 reserved_at_60[0x10]; 7700 u8 delay_drop_timeout[0x10]; 7701 }; 7702 7703 struct mlx5_ifc_set_delay_drop_params_out_bits { 7704 u8 status[0x8]; 7705 u8 reserved_at_8[0x18]; 7706 7707 u8 syndrome[0x20]; 7708 7709 u8 reserved_at_40[0x40]; 7710 }; 7711 7712 struct mlx5_ifc_destroy_rmp_out_bits { 7713 u8 status[0x8]; 7714 u8 reserved_at_8[0x18]; 7715 7716 u8 syndrome[0x20]; 7717 7718 u8 reserved_at_40[0x40]; 7719 }; 7720 7721 struct mlx5_ifc_destroy_rmp_in_bits { 7722 u8 opcode[0x10]; 7723 u8 uid[0x10]; 7724 7725 u8 reserved_at_20[0x10]; 7726 u8 op_mod[0x10]; 7727 7728 u8 reserved_at_40[0x8]; 7729 u8 rmpn[0x18]; 7730 7731 u8 reserved_at_60[0x20]; 7732 }; 7733 7734 struct mlx5_ifc_destroy_qp_out_bits { 7735 u8 status[0x8]; 7736 u8 reserved_at_8[0x18]; 7737 7738 u8 syndrome[0x20]; 7739 7740 u8 reserved_at_40[0x40]; 7741 }; 7742 7743 struct mlx5_ifc_destroy_qp_in_bits { 7744 u8 opcode[0x10]; 7745 u8 uid[0x10]; 7746 7747 u8 reserved_at_20[0x10]; 7748 u8 op_mod[0x10]; 7749 7750 u8 reserved_at_40[0x8]; 7751 u8 qpn[0x18]; 7752 7753 u8 reserved_at_60[0x20]; 7754 }; 7755 7756 struct mlx5_ifc_destroy_psv_out_bits { 7757 u8 status[0x8]; 7758 u8 reserved_at_8[0x18]; 7759 7760 u8 syndrome[0x20]; 7761 7762 u8 reserved_at_40[0x40]; 7763 }; 7764 7765 struct mlx5_ifc_destroy_psv_in_bits { 7766 u8 opcode[0x10]; 7767 u8 reserved_at_10[0x10]; 7768 7769 u8 reserved_at_20[0x10]; 7770 u8 op_mod[0x10]; 7771 7772 u8 reserved_at_40[0x8]; 7773 u8 psvn[0x18]; 7774 7775 u8 reserved_at_60[0x20]; 7776 }; 7777 7778 struct mlx5_ifc_destroy_mkey_out_bits { 7779 u8 status[0x8]; 7780 u8 reserved_at_8[0x18]; 7781 7782 u8 syndrome[0x20]; 7783 7784 u8 reserved_at_40[0x40]; 7785 }; 7786 7787 struct mlx5_ifc_destroy_mkey_in_bits { 7788 u8 opcode[0x10]; 7789 u8 uid[0x10]; 7790 7791 u8 reserved_at_20[0x10]; 7792 u8 op_mod[0x10]; 7793 7794 u8 reserved_at_40[0x8]; 7795 u8 mkey_index[0x18]; 7796 7797 u8 reserved_at_60[0x20]; 7798 }; 7799 7800 struct mlx5_ifc_destroy_flow_table_out_bits { 7801 u8 status[0x8]; 7802 u8 reserved_at_8[0x18]; 7803 7804 u8 syndrome[0x20]; 7805 7806 u8 reserved_at_40[0x40]; 7807 }; 7808 7809 struct mlx5_ifc_destroy_flow_table_in_bits { 7810 u8 opcode[0x10]; 7811 u8 reserved_at_10[0x10]; 7812 7813 u8 reserved_at_20[0x10]; 7814 u8 op_mod[0x10]; 7815 7816 u8 other_vport[0x1]; 7817 u8 reserved_at_41[0xf]; 7818 u8 vport_number[0x10]; 7819 7820 u8 reserved_at_60[0x20]; 7821 7822 u8 table_type[0x8]; 7823 u8 reserved_at_88[0x18]; 7824 7825 u8 reserved_at_a0[0x8]; 7826 u8 table_id[0x18]; 7827 7828 u8 reserved_at_c0[0x140]; 7829 }; 7830 7831 struct mlx5_ifc_destroy_flow_group_out_bits { 7832 u8 status[0x8]; 7833 u8 reserved_at_8[0x18]; 7834 7835 u8 syndrome[0x20]; 7836 7837 u8 reserved_at_40[0x40]; 7838 }; 7839 7840 struct mlx5_ifc_destroy_flow_group_in_bits { 7841 u8 opcode[0x10]; 7842 u8 reserved_at_10[0x10]; 7843 7844 u8 reserved_at_20[0x10]; 7845 u8 op_mod[0x10]; 7846 7847 u8 other_vport[0x1]; 7848 u8 reserved_at_41[0xf]; 7849 u8 vport_number[0x10]; 7850 7851 u8 reserved_at_60[0x20]; 7852 7853 u8 table_type[0x8]; 7854 u8 reserved_at_88[0x18]; 7855 7856 u8 reserved_at_a0[0x8]; 7857 u8 table_id[0x18]; 7858 7859 u8 group_id[0x20]; 7860 7861 u8 reserved_at_e0[0x120]; 7862 }; 7863 7864 struct mlx5_ifc_destroy_eq_out_bits { 7865 u8 status[0x8]; 7866 u8 reserved_at_8[0x18]; 7867 7868 u8 syndrome[0x20]; 7869 7870 u8 reserved_at_40[0x40]; 7871 }; 7872 7873 struct mlx5_ifc_destroy_eq_in_bits { 7874 u8 opcode[0x10]; 7875 u8 reserved_at_10[0x10]; 7876 7877 u8 reserved_at_20[0x10]; 7878 u8 op_mod[0x10]; 7879 7880 u8 reserved_at_40[0x18]; 7881 u8 eq_number[0x8]; 7882 7883 u8 reserved_at_60[0x20]; 7884 }; 7885 7886 struct mlx5_ifc_destroy_dct_out_bits { 7887 u8 status[0x8]; 7888 u8 reserved_at_8[0x18]; 7889 7890 u8 syndrome[0x20]; 7891 7892 u8 reserved_at_40[0x40]; 7893 }; 7894 7895 struct mlx5_ifc_destroy_dct_in_bits { 7896 u8 opcode[0x10]; 7897 u8 uid[0x10]; 7898 7899 u8 reserved_at_20[0x10]; 7900 u8 op_mod[0x10]; 7901 7902 u8 reserved_at_40[0x8]; 7903 u8 dctn[0x18]; 7904 7905 u8 reserved_at_60[0x20]; 7906 }; 7907 7908 struct mlx5_ifc_destroy_cq_out_bits { 7909 u8 status[0x8]; 7910 u8 reserved_at_8[0x18]; 7911 7912 u8 syndrome[0x20]; 7913 7914 u8 reserved_at_40[0x40]; 7915 }; 7916 7917 struct mlx5_ifc_destroy_cq_in_bits { 7918 u8 opcode[0x10]; 7919 u8 uid[0x10]; 7920 7921 u8 reserved_at_20[0x10]; 7922 u8 op_mod[0x10]; 7923 7924 u8 reserved_at_40[0x8]; 7925 u8 cqn[0x18]; 7926 7927 u8 reserved_at_60[0x20]; 7928 }; 7929 7930 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7931 u8 status[0x8]; 7932 u8 reserved_at_8[0x18]; 7933 7934 u8 syndrome[0x20]; 7935 7936 u8 reserved_at_40[0x40]; 7937 }; 7938 7939 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7940 u8 opcode[0x10]; 7941 u8 reserved_at_10[0x10]; 7942 7943 u8 reserved_at_20[0x10]; 7944 u8 op_mod[0x10]; 7945 7946 u8 reserved_at_40[0x20]; 7947 7948 u8 reserved_at_60[0x10]; 7949 u8 vxlan_udp_port[0x10]; 7950 }; 7951 7952 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7953 u8 status[0x8]; 7954 u8 reserved_at_8[0x18]; 7955 7956 u8 syndrome[0x20]; 7957 7958 u8 reserved_at_40[0x40]; 7959 }; 7960 7961 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7962 u8 opcode[0x10]; 7963 u8 reserved_at_10[0x10]; 7964 7965 u8 reserved_at_20[0x10]; 7966 u8 op_mod[0x10]; 7967 7968 u8 reserved_at_40[0x60]; 7969 7970 u8 reserved_at_a0[0x8]; 7971 u8 table_index[0x18]; 7972 7973 u8 reserved_at_c0[0x140]; 7974 }; 7975 7976 struct mlx5_ifc_delete_fte_out_bits { 7977 u8 status[0x8]; 7978 u8 reserved_at_8[0x18]; 7979 7980 u8 syndrome[0x20]; 7981 7982 u8 reserved_at_40[0x40]; 7983 }; 7984 7985 struct mlx5_ifc_delete_fte_in_bits { 7986 u8 opcode[0x10]; 7987 u8 reserved_at_10[0x10]; 7988 7989 u8 reserved_at_20[0x10]; 7990 u8 op_mod[0x10]; 7991 7992 u8 other_vport[0x1]; 7993 u8 reserved_at_41[0xf]; 7994 u8 vport_number[0x10]; 7995 7996 u8 reserved_at_60[0x20]; 7997 7998 u8 table_type[0x8]; 7999 u8 reserved_at_88[0x18]; 8000 8001 u8 reserved_at_a0[0x8]; 8002 u8 table_id[0x18]; 8003 8004 u8 reserved_at_c0[0x40]; 8005 8006 u8 flow_index[0x20]; 8007 8008 u8 reserved_at_120[0xe0]; 8009 }; 8010 8011 struct mlx5_ifc_dealloc_xrcd_out_bits { 8012 u8 status[0x8]; 8013 u8 reserved_at_8[0x18]; 8014 8015 u8 syndrome[0x20]; 8016 8017 u8 reserved_at_40[0x40]; 8018 }; 8019 8020 struct mlx5_ifc_dealloc_xrcd_in_bits { 8021 u8 opcode[0x10]; 8022 u8 uid[0x10]; 8023 8024 u8 reserved_at_20[0x10]; 8025 u8 op_mod[0x10]; 8026 8027 u8 reserved_at_40[0x8]; 8028 u8 xrcd[0x18]; 8029 8030 u8 reserved_at_60[0x20]; 8031 }; 8032 8033 struct mlx5_ifc_dealloc_uar_out_bits { 8034 u8 status[0x8]; 8035 u8 reserved_at_8[0x18]; 8036 8037 u8 syndrome[0x20]; 8038 8039 u8 reserved_at_40[0x40]; 8040 }; 8041 8042 struct mlx5_ifc_dealloc_uar_in_bits { 8043 u8 opcode[0x10]; 8044 u8 uid[0x10]; 8045 8046 u8 reserved_at_20[0x10]; 8047 u8 op_mod[0x10]; 8048 8049 u8 reserved_at_40[0x8]; 8050 u8 uar[0x18]; 8051 8052 u8 reserved_at_60[0x20]; 8053 }; 8054 8055 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8056 u8 status[0x8]; 8057 u8 reserved_at_8[0x18]; 8058 8059 u8 syndrome[0x20]; 8060 8061 u8 reserved_at_40[0x40]; 8062 }; 8063 8064 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8065 u8 opcode[0x10]; 8066 u8 uid[0x10]; 8067 8068 u8 reserved_at_20[0x10]; 8069 u8 op_mod[0x10]; 8070 8071 u8 reserved_at_40[0x8]; 8072 u8 transport_domain[0x18]; 8073 8074 u8 reserved_at_60[0x20]; 8075 }; 8076 8077 struct mlx5_ifc_dealloc_q_counter_out_bits { 8078 u8 status[0x8]; 8079 u8 reserved_at_8[0x18]; 8080 8081 u8 syndrome[0x20]; 8082 8083 u8 reserved_at_40[0x40]; 8084 }; 8085 8086 struct mlx5_ifc_dealloc_q_counter_in_bits { 8087 u8 opcode[0x10]; 8088 u8 reserved_at_10[0x10]; 8089 8090 u8 reserved_at_20[0x10]; 8091 u8 op_mod[0x10]; 8092 8093 u8 reserved_at_40[0x18]; 8094 u8 counter_set_id[0x8]; 8095 8096 u8 reserved_at_60[0x20]; 8097 }; 8098 8099 struct mlx5_ifc_dealloc_pd_out_bits { 8100 u8 status[0x8]; 8101 u8 reserved_at_8[0x18]; 8102 8103 u8 syndrome[0x20]; 8104 8105 u8 reserved_at_40[0x40]; 8106 }; 8107 8108 struct mlx5_ifc_dealloc_pd_in_bits { 8109 u8 opcode[0x10]; 8110 u8 uid[0x10]; 8111 8112 u8 reserved_at_20[0x10]; 8113 u8 op_mod[0x10]; 8114 8115 u8 reserved_at_40[0x8]; 8116 u8 pd[0x18]; 8117 8118 u8 reserved_at_60[0x20]; 8119 }; 8120 8121 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8122 u8 status[0x8]; 8123 u8 reserved_at_8[0x18]; 8124 8125 u8 syndrome[0x20]; 8126 8127 u8 reserved_at_40[0x40]; 8128 }; 8129 8130 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8131 u8 opcode[0x10]; 8132 u8 reserved_at_10[0x10]; 8133 8134 u8 reserved_at_20[0x10]; 8135 u8 op_mod[0x10]; 8136 8137 u8 flow_counter_id[0x20]; 8138 8139 u8 reserved_at_60[0x20]; 8140 }; 8141 8142 struct mlx5_ifc_create_xrq_out_bits { 8143 u8 status[0x8]; 8144 u8 reserved_at_8[0x18]; 8145 8146 u8 syndrome[0x20]; 8147 8148 u8 reserved_at_40[0x8]; 8149 u8 xrqn[0x18]; 8150 8151 u8 reserved_at_60[0x20]; 8152 }; 8153 8154 struct mlx5_ifc_create_xrq_in_bits { 8155 u8 opcode[0x10]; 8156 u8 uid[0x10]; 8157 8158 u8 reserved_at_20[0x10]; 8159 u8 op_mod[0x10]; 8160 8161 u8 reserved_at_40[0x40]; 8162 8163 struct mlx5_ifc_xrqc_bits xrq_context; 8164 }; 8165 8166 struct mlx5_ifc_create_xrc_srq_out_bits { 8167 u8 status[0x8]; 8168 u8 reserved_at_8[0x18]; 8169 8170 u8 syndrome[0x20]; 8171 8172 u8 reserved_at_40[0x8]; 8173 u8 xrc_srqn[0x18]; 8174 8175 u8 reserved_at_60[0x20]; 8176 }; 8177 8178 struct mlx5_ifc_create_xrc_srq_in_bits { 8179 u8 opcode[0x10]; 8180 u8 uid[0x10]; 8181 8182 u8 reserved_at_20[0x10]; 8183 u8 op_mod[0x10]; 8184 8185 u8 reserved_at_40[0x40]; 8186 8187 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8188 8189 u8 reserved_at_280[0x60]; 8190 8191 u8 xrc_srq_umem_valid[0x1]; 8192 u8 reserved_at_2e1[0x1f]; 8193 8194 u8 reserved_at_300[0x580]; 8195 8196 u8 pas[][0x40]; 8197 }; 8198 8199 struct mlx5_ifc_create_tis_out_bits { 8200 u8 status[0x8]; 8201 u8 reserved_at_8[0x18]; 8202 8203 u8 syndrome[0x20]; 8204 8205 u8 reserved_at_40[0x8]; 8206 u8 tisn[0x18]; 8207 8208 u8 reserved_at_60[0x20]; 8209 }; 8210 8211 struct mlx5_ifc_create_tis_in_bits { 8212 u8 opcode[0x10]; 8213 u8 uid[0x10]; 8214 8215 u8 reserved_at_20[0x10]; 8216 u8 op_mod[0x10]; 8217 8218 u8 reserved_at_40[0xc0]; 8219 8220 struct mlx5_ifc_tisc_bits ctx; 8221 }; 8222 8223 struct mlx5_ifc_create_tir_out_bits { 8224 u8 status[0x8]; 8225 u8 icm_address_63_40[0x18]; 8226 8227 u8 syndrome[0x20]; 8228 8229 u8 icm_address_39_32[0x8]; 8230 u8 tirn[0x18]; 8231 8232 u8 icm_address_31_0[0x20]; 8233 }; 8234 8235 struct mlx5_ifc_create_tir_in_bits { 8236 u8 opcode[0x10]; 8237 u8 uid[0x10]; 8238 8239 u8 reserved_at_20[0x10]; 8240 u8 op_mod[0x10]; 8241 8242 u8 reserved_at_40[0xc0]; 8243 8244 struct mlx5_ifc_tirc_bits ctx; 8245 }; 8246 8247 struct mlx5_ifc_create_srq_out_bits { 8248 u8 status[0x8]; 8249 u8 reserved_at_8[0x18]; 8250 8251 u8 syndrome[0x20]; 8252 8253 u8 reserved_at_40[0x8]; 8254 u8 srqn[0x18]; 8255 8256 u8 reserved_at_60[0x20]; 8257 }; 8258 8259 struct mlx5_ifc_create_srq_in_bits { 8260 u8 opcode[0x10]; 8261 u8 uid[0x10]; 8262 8263 u8 reserved_at_20[0x10]; 8264 u8 op_mod[0x10]; 8265 8266 u8 reserved_at_40[0x40]; 8267 8268 struct mlx5_ifc_srqc_bits srq_context_entry; 8269 8270 u8 reserved_at_280[0x600]; 8271 8272 u8 pas[][0x40]; 8273 }; 8274 8275 struct mlx5_ifc_create_sq_out_bits { 8276 u8 status[0x8]; 8277 u8 reserved_at_8[0x18]; 8278 8279 u8 syndrome[0x20]; 8280 8281 u8 reserved_at_40[0x8]; 8282 u8 sqn[0x18]; 8283 8284 u8 reserved_at_60[0x20]; 8285 }; 8286 8287 struct mlx5_ifc_create_sq_in_bits { 8288 u8 opcode[0x10]; 8289 u8 uid[0x10]; 8290 8291 u8 reserved_at_20[0x10]; 8292 u8 op_mod[0x10]; 8293 8294 u8 reserved_at_40[0xc0]; 8295 8296 struct mlx5_ifc_sqc_bits ctx; 8297 }; 8298 8299 struct mlx5_ifc_create_scheduling_element_out_bits { 8300 u8 status[0x8]; 8301 u8 reserved_at_8[0x18]; 8302 8303 u8 syndrome[0x20]; 8304 8305 u8 reserved_at_40[0x40]; 8306 8307 u8 scheduling_element_id[0x20]; 8308 8309 u8 reserved_at_a0[0x160]; 8310 }; 8311 8312 struct mlx5_ifc_create_scheduling_element_in_bits { 8313 u8 opcode[0x10]; 8314 u8 reserved_at_10[0x10]; 8315 8316 u8 reserved_at_20[0x10]; 8317 u8 op_mod[0x10]; 8318 8319 u8 scheduling_hierarchy[0x8]; 8320 u8 reserved_at_48[0x18]; 8321 8322 u8 reserved_at_60[0xa0]; 8323 8324 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8325 8326 u8 reserved_at_300[0x100]; 8327 }; 8328 8329 struct mlx5_ifc_create_rqt_out_bits { 8330 u8 status[0x8]; 8331 u8 reserved_at_8[0x18]; 8332 8333 u8 syndrome[0x20]; 8334 8335 u8 reserved_at_40[0x8]; 8336 u8 rqtn[0x18]; 8337 8338 u8 reserved_at_60[0x20]; 8339 }; 8340 8341 struct mlx5_ifc_create_rqt_in_bits { 8342 u8 opcode[0x10]; 8343 u8 uid[0x10]; 8344 8345 u8 reserved_at_20[0x10]; 8346 u8 op_mod[0x10]; 8347 8348 u8 reserved_at_40[0xc0]; 8349 8350 struct mlx5_ifc_rqtc_bits rqt_context; 8351 }; 8352 8353 struct mlx5_ifc_create_rq_out_bits { 8354 u8 status[0x8]; 8355 u8 reserved_at_8[0x18]; 8356 8357 u8 syndrome[0x20]; 8358 8359 u8 reserved_at_40[0x8]; 8360 u8 rqn[0x18]; 8361 8362 u8 reserved_at_60[0x20]; 8363 }; 8364 8365 struct mlx5_ifc_create_rq_in_bits { 8366 u8 opcode[0x10]; 8367 u8 uid[0x10]; 8368 8369 u8 reserved_at_20[0x10]; 8370 u8 op_mod[0x10]; 8371 8372 u8 reserved_at_40[0xc0]; 8373 8374 struct mlx5_ifc_rqc_bits ctx; 8375 }; 8376 8377 struct mlx5_ifc_create_rmp_out_bits { 8378 u8 status[0x8]; 8379 u8 reserved_at_8[0x18]; 8380 8381 u8 syndrome[0x20]; 8382 8383 u8 reserved_at_40[0x8]; 8384 u8 rmpn[0x18]; 8385 8386 u8 reserved_at_60[0x20]; 8387 }; 8388 8389 struct mlx5_ifc_create_rmp_in_bits { 8390 u8 opcode[0x10]; 8391 u8 uid[0x10]; 8392 8393 u8 reserved_at_20[0x10]; 8394 u8 op_mod[0x10]; 8395 8396 u8 reserved_at_40[0xc0]; 8397 8398 struct mlx5_ifc_rmpc_bits ctx; 8399 }; 8400 8401 struct mlx5_ifc_create_qp_out_bits { 8402 u8 status[0x8]; 8403 u8 reserved_at_8[0x18]; 8404 8405 u8 syndrome[0x20]; 8406 8407 u8 reserved_at_40[0x8]; 8408 u8 qpn[0x18]; 8409 8410 u8 ece[0x20]; 8411 }; 8412 8413 struct mlx5_ifc_create_qp_in_bits { 8414 u8 opcode[0x10]; 8415 u8 uid[0x10]; 8416 8417 u8 reserved_at_20[0x10]; 8418 u8 op_mod[0x10]; 8419 8420 u8 reserved_at_40[0x8]; 8421 u8 input_qpn[0x18]; 8422 8423 u8 reserved_at_60[0x20]; 8424 u8 opt_param_mask[0x20]; 8425 8426 u8 ece[0x20]; 8427 8428 struct mlx5_ifc_qpc_bits qpc; 8429 8430 u8 reserved_at_800[0x60]; 8431 8432 u8 wq_umem_valid[0x1]; 8433 u8 reserved_at_861[0x1f]; 8434 8435 u8 pas[][0x40]; 8436 }; 8437 8438 struct mlx5_ifc_create_psv_out_bits { 8439 u8 status[0x8]; 8440 u8 reserved_at_8[0x18]; 8441 8442 u8 syndrome[0x20]; 8443 8444 u8 reserved_at_40[0x40]; 8445 8446 u8 reserved_at_80[0x8]; 8447 u8 psv0_index[0x18]; 8448 8449 u8 reserved_at_a0[0x8]; 8450 u8 psv1_index[0x18]; 8451 8452 u8 reserved_at_c0[0x8]; 8453 u8 psv2_index[0x18]; 8454 8455 u8 reserved_at_e0[0x8]; 8456 u8 psv3_index[0x18]; 8457 }; 8458 8459 struct mlx5_ifc_create_psv_in_bits { 8460 u8 opcode[0x10]; 8461 u8 reserved_at_10[0x10]; 8462 8463 u8 reserved_at_20[0x10]; 8464 u8 op_mod[0x10]; 8465 8466 u8 num_psv[0x4]; 8467 u8 reserved_at_44[0x4]; 8468 u8 pd[0x18]; 8469 8470 u8 reserved_at_60[0x20]; 8471 }; 8472 8473 struct mlx5_ifc_create_mkey_out_bits { 8474 u8 status[0x8]; 8475 u8 reserved_at_8[0x18]; 8476 8477 u8 syndrome[0x20]; 8478 8479 u8 reserved_at_40[0x8]; 8480 u8 mkey_index[0x18]; 8481 8482 u8 reserved_at_60[0x20]; 8483 }; 8484 8485 struct mlx5_ifc_create_mkey_in_bits { 8486 u8 opcode[0x10]; 8487 u8 uid[0x10]; 8488 8489 u8 reserved_at_20[0x10]; 8490 u8 op_mod[0x10]; 8491 8492 u8 reserved_at_40[0x20]; 8493 8494 u8 pg_access[0x1]; 8495 u8 mkey_umem_valid[0x1]; 8496 u8 reserved_at_62[0x1e]; 8497 8498 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8499 8500 u8 reserved_at_280[0x80]; 8501 8502 u8 translations_octword_actual_size[0x20]; 8503 8504 u8 reserved_at_320[0x560]; 8505 8506 u8 klm_pas_mtt[][0x20]; 8507 }; 8508 8509 enum { 8510 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8511 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8512 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8513 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8514 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8515 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8516 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8517 }; 8518 8519 struct mlx5_ifc_create_flow_table_out_bits { 8520 u8 status[0x8]; 8521 u8 icm_address_63_40[0x18]; 8522 8523 u8 syndrome[0x20]; 8524 8525 u8 icm_address_39_32[0x8]; 8526 u8 table_id[0x18]; 8527 8528 u8 icm_address_31_0[0x20]; 8529 }; 8530 8531 struct mlx5_ifc_create_flow_table_in_bits { 8532 u8 opcode[0x10]; 8533 u8 uid[0x10]; 8534 8535 u8 reserved_at_20[0x10]; 8536 u8 op_mod[0x10]; 8537 8538 u8 other_vport[0x1]; 8539 u8 reserved_at_41[0xf]; 8540 u8 vport_number[0x10]; 8541 8542 u8 reserved_at_60[0x20]; 8543 8544 u8 table_type[0x8]; 8545 u8 reserved_at_88[0x18]; 8546 8547 u8 reserved_at_a0[0x20]; 8548 8549 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8550 }; 8551 8552 struct mlx5_ifc_create_flow_group_out_bits { 8553 u8 status[0x8]; 8554 u8 reserved_at_8[0x18]; 8555 8556 u8 syndrome[0x20]; 8557 8558 u8 reserved_at_40[0x8]; 8559 u8 group_id[0x18]; 8560 8561 u8 reserved_at_60[0x20]; 8562 }; 8563 8564 enum { 8565 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8566 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8567 }; 8568 8569 enum { 8570 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8571 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8572 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8573 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8574 }; 8575 8576 struct mlx5_ifc_create_flow_group_in_bits { 8577 u8 opcode[0x10]; 8578 u8 reserved_at_10[0x10]; 8579 8580 u8 reserved_at_20[0x10]; 8581 u8 op_mod[0x10]; 8582 8583 u8 other_vport[0x1]; 8584 u8 reserved_at_41[0xf]; 8585 u8 vport_number[0x10]; 8586 8587 u8 reserved_at_60[0x20]; 8588 8589 u8 table_type[0x8]; 8590 u8 reserved_at_88[0x4]; 8591 u8 group_type[0x4]; 8592 u8 reserved_at_90[0x10]; 8593 8594 u8 reserved_at_a0[0x8]; 8595 u8 table_id[0x18]; 8596 8597 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8598 8599 u8 reserved_at_c1[0x1f]; 8600 8601 u8 start_flow_index[0x20]; 8602 8603 u8 reserved_at_100[0x20]; 8604 8605 u8 end_flow_index[0x20]; 8606 8607 u8 reserved_at_140[0x10]; 8608 u8 match_definer_id[0x10]; 8609 8610 u8 reserved_at_160[0x80]; 8611 8612 u8 reserved_at_1e0[0x18]; 8613 u8 match_criteria_enable[0x8]; 8614 8615 struct mlx5_ifc_fte_match_param_bits match_criteria; 8616 8617 u8 reserved_at_1200[0xe00]; 8618 }; 8619 8620 struct mlx5_ifc_create_eq_out_bits { 8621 u8 status[0x8]; 8622 u8 reserved_at_8[0x18]; 8623 8624 u8 syndrome[0x20]; 8625 8626 u8 reserved_at_40[0x18]; 8627 u8 eq_number[0x8]; 8628 8629 u8 reserved_at_60[0x20]; 8630 }; 8631 8632 struct mlx5_ifc_create_eq_in_bits { 8633 u8 opcode[0x10]; 8634 u8 uid[0x10]; 8635 8636 u8 reserved_at_20[0x10]; 8637 u8 op_mod[0x10]; 8638 8639 u8 reserved_at_40[0x40]; 8640 8641 struct mlx5_ifc_eqc_bits eq_context_entry; 8642 8643 u8 reserved_at_280[0x40]; 8644 8645 u8 event_bitmask[4][0x40]; 8646 8647 u8 reserved_at_3c0[0x4c0]; 8648 8649 u8 pas[][0x40]; 8650 }; 8651 8652 struct mlx5_ifc_create_dct_out_bits { 8653 u8 status[0x8]; 8654 u8 reserved_at_8[0x18]; 8655 8656 u8 syndrome[0x20]; 8657 8658 u8 reserved_at_40[0x8]; 8659 u8 dctn[0x18]; 8660 8661 u8 ece[0x20]; 8662 }; 8663 8664 struct mlx5_ifc_create_dct_in_bits { 8665 u8 opcode[0x10]; 8666 u8 uid[0x10]; 8667 8668 u8 reserved_at_20[0x10]; 8669 u8 op_mod[0x10]; 8670 8671 u8 reserved_at_40[0x40]; 8672 8673 struct mlx5_ifc_dctc_bits dct_context_entry; 8674 8675 u8 reserved_at_280[0x180]; 8676 }; 8677 8678 struct mlx5_ifc_create_cq_out_bits { 8679 u8 status[0x8]; 8680 u8 reserved_at_8[0x18]; 8681 8682 u8 syndrome[0x20]; 8683 8684 u8 reserved_at_40[0x8]; 8685 u8 cqn[0x18]; 8686 8687 u8 reserved_at_60[0x20]; 8688 }; 8689 8690 struct mlx5_ifc_create_cq_in_bits { 8691 u8 opcode[0x10]; 8692 u8 uid[0x10]; 8693 8694 u8 reserved_at_20[0x10]; 8695 u8 op_mod[0x10]; 8696 8697 u8 reserved_at_40[0x40]; 8698 8699 struct mlx5_ifc_cqc_bits cq_context; 8700 8701 u8 reserved_at_280[0x60]; 8702 8703 u8 cq_umem_valid[0x1]; 8704 u8 reserved_at_2e1[0x59f]; 8705 8706 u8 pas[][0x40]; 8707 }; 8708 8709 struct mlx5_ifc_config_int_moderation_out_bits { 8710 u8 status[0x8]; 8711 u8 reserved_at_8[0x18]; 8712 8713 u8 syndrome[0x20]; 8714 8715 u8 reserved_at_40[0x4]; 8716 u8 min_delay[0xc]; 8717 u8 int_vector[0x10]; 8718 8719 u8 reserved_at_60[0x20]; 8720 }; 8721 8722 enum { 8723 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8724 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8725 }; 8726 8727 struct mlx5_ifc_config_int_moderation_in_bits { 8728 u8 opcode[0x10]; 8729 u8 reserved_at_10[0x10]; 8730 8731 u8 reserved_at_20[0x10]; 8732 u8 op_mod[0x10]; 8733 8734 u8 reserved_at_40[0x4]; 8735 u8 min_delay[0xc]; 8736 u8 int_vector[0x10]; 8737 8738 u8 reserved_at_60[0x20]; 8739 }; 8740 8741 struct mlx5_ifc_attach_to_mcg_out_bits { 8742 u8 status[0x8]; 8743 u8 reserved_at_8[0x18]; 8744 8745 u8 syndrome[0x20]; 8746 8747 u8 reserved_at_40[0x40]; 8748 }; 8749 8750 struct mlx5_ifc_attach_to_mcg_in_bits { 8751 u8 opcode[0x10]; 8752 u8 uid[0x10]; 8753 8754 u8 reserved_at_20[0x10]; 8755 u8 op_mod[0x10]; 8756 8757 u8 reserved_at_40[0x8]; 8758 u8 qpn[0x18]; 8759 8760 u8 reserved_at_60[0x20]; 8761 8762 u8 multicast_gid[16][0x8]; 8763 }; 8764 8765 struct mlx5_ifc_arm_xrq_out_bits { 8766 u8 status[0x8]; 8767 u8 reserved_at_8[0x18]; 8768 8769 u8 syndrome[0x20]; 8770 8771 u8 reserved_at_40[0x40]; 8772 }; 8773 8774 struct mlx5_ifc_arm_xrq_in_bits { 8775 u8 opcode[0x10]; 8776 u8 reserved_at_10[0x10]; 8777 8778 u8 reserved_at_20[0x10]; 8779 u8 op_mod[0x10]; 8780 8781 u8 reserved_at_40[0x8]; 8782 u8 xrqn[0x18]; 8783 8784 u8 reserved_at_60[0x10]; 8785 u8 lwm[0x10]; 8786 }; 8787 8788 struct mlx5_ifc_arm_xrc_srq_out_bits { 8789 u8 status[0x8]; 8790 u8 reserved_at_8[0x18]; 8791 8792 u8 syndrome[0x20]; 8793 8794 u8 reserved_at_40[0x40]; 8795 }; 8796 8797 enum { 8798 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8799 }; 8800 8801 struct mlx5_ifc_arm_xrc_srq_in_bits { 8802 u8 opcode[0x10]; 8803 u8 uid[0x10]; 8804 8805 u8 reserved_at_20[0x10]; 8806 u8 op_mod[0x10]; 8807 8808 u8 reserved_at_40[0x8]; 8809 u8 xrc_srqn[0x18]; 8810 8811 u8 reserved_at_60[0x10]; 8812 u8 lwm[0x10]; 8813 }; 8814 8815 struct mlx5_ifc_arm_rq_out_bits { 8816 u8 status[0x8]; 8817 u8 reserved_at_8[0x18]; 8818 8819 u8 syndrome[0x20]; 8820 8821 u8 reserved_at_40[0x40]; 8822 }; 8823 8824 enum { 8825 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8826 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8827 }; 8828 8829 struct mlx5_ifc_arm_rq_in_bits { 8830 u8 opcode[0x10]; 8831 u8 uid[0x10]; 8832 8833 u8 reserved_at_20[0x10]; 8834 u8 op_mod[0x10]; 8835 8836 u8 reserved_at_40[0x8]; 8837 u8 srq_number[0x18]; 8838 8839 u8 reserved_at_60[0x10]; 8840 u8 lwm[0x10]; 8841 }; 8842 8843 struct mlx5_ifc_arm_dct_out_bits { 8844 u8 status[0x8]; 8845 u8 reserved_at_8[0x18]; 8846 8847 u8 syndrome[0x20]; 8848 8849 u8 reserved_at_40[0x40]; 8850 }; 8851 8852 struct mlx5_ifc_arm_dct_in_bits { 8853 u8 opcode[0x10]; 8854 u8 reserved_at_10[0x10]; 8855 8856 u8 reserved_at_20[0x10]; 8857 u8 op_mod[0x10]; 8858 8859 u8 reserved_at_40[0x8]; 8860 u8 dct_number[0x18]; 8861 8862 u8 reserved_at_60[0x20]; 8863 }; 8864 8865 struct mlx5_ifc_alloc_xrcd_out_bits { 8866 u8 status[0x8]; 8867 u8 reserved_at_8[0x18]; 8868 8869 u8 syndrome[0x20]; 8870 8871 u8 reserved_at_40[0x8]; 8872 u8 xrcd[0x18]; 8873 8874 u8 reserved_at_60[0x20]; 8875 }; 8876 8877 struct mlx5_ifc_alloc_xrcd_in_bits { 8878 u8 opcode[0x10]; 8879 u8 uid[0x10]; 8880 8881 u8 reserved_at_20[0x10]; 8882 u8 op_mod[0x10]; 8883 8884 u8 reserved_at_40[0x40]; 8885 }; 8886 8887 struct mlx5_ifc_alloc_uar_out_bits { 8888 u8 status[0x8]; 8889 u8 reserved_at_8[0x18]; 8890 8891 u8 syndrome[0x20]; 8892 8893 u8 reserved_at_40[0x8]; 8894 u8 uar[0x18]; 8895 8896 u8 reserved_at_60[0x20]; 8897 }; 8898 8899 struct mlx5_ifc_alloc_uar_in_bits { 8900 u8 opcode[0x10]; 8901 u8 uid[0x10]; 8902 8903 u8 reserved_at_20[0x10]; 8904 u8 op_mod[0x10]; 8905 8906 u8 reserved_at_40[0x40]; 8907 }; 8908 8909 struct mlx5_ifc_alloc_transport_domain_out_bits { 8910 u8 status[0x8]; 8911 u8 reserved_at_8[0x18]; 8912 8913 u8 syndrome[0x20]; 8914 8915 u8 reserved_at_40[0x8]; 8916 u8 transport_domain[0x18]; 8917 8918 u8 reserved_at_60[0x20]; 8919 }; 8920 8921 struct mlx5_ifc_alloc_transport_domain_in_bits { 8922 u8 opcode[0x10]; 8923 u8 uid[0x10]; 8924 8925 u8 reserved_at_20[0x10]; 8926 u8 op_mod[0x10]; 8927 8928 u8 reserved_at_40[0x40]; 8929 }; 8930 8931 struct mlx5_ifc_alloc_q_counter_out_bits { 8932 u8 status[0x8]; 8933 u8 reserved_at_8[0x18]; 8934 8935 u8 syndrome[0x20]; 8936 8937 u8 reserved_at_40[0x18]; 8938 u8 counter_set_id[0x8]; 8939 8940 u8 reserved_at_60[0x20]; 8941 }; 8942 8943 struct mlx5_ifc_alloc_q_counter_in_bits { 8944 u8 opcode[0x10]; 8945 u8 uid[0x10]; 8946 8947 u8 reserved_at_20[0x10]; 8948 u8 op_mod[0x10]; 8949 8950 u8 reserved_at_40[0x40]; 8951 }; 8952 8953 struct mlx5_ifc_alloc_pd_out_bits { 8954 u8 status[0x8]; 8955 u8 reserved_at_8[0x18]; 8956 8957 u8 syndrome[0x20]; 8958 8959 u8 reserved_at_40[0x8]; 8960 u8 pd[0x18]; 8961 8962 u8 reserved_at_60[0x20]; 8963 }; 8964 8965 struct mlx5_ifc_alloc_pd_in_bits { 8966 u8 opcode[0x10]; 8967 u8 uid[0x10]; 8968 8969 u8 reserved_at_20[0x10]; 8970 u8 op_mod[0x10]; 8971 8972 u8 reserved_at_40[0x40]; 8973 }; 8974 8975 struct mlx5_ifc_alloc_flow_counter_out_bits { 8976 u8 status[0x8]; 8977 u8 reserved_at_8[0x18]; 8978 8979 u8 syndrome[0x20]; 8980 8981 u8 flow_counter_id[0x20]; 8982 8983 u8 reserved_at_60[0x20]; 8984 }; 8985 8986 struct mlx5_ifc_alloc_flow_counter_in_bits { 8987 u8 opcode[0x10]; 8988 u8 reserved_at_10[0x10]; 8989 8990 u8 reserved_at_20[0x10]; 8991 u8 op_mod[0x10]; 8992 8993 u8 reserved_at_40[0x38]; 8994 u8 flow_counter_bulk[0x8]; 8995 }; 8996 8997 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8998 u8 status[0x8]; 8999 u8 reserved_at_8[0x18]; 9000 9001 u8 syndrome[0x20]; 9002 9003 u8 reserved_at_40[0x40]; 9004 }; 9005 9006 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9007 u8 opcode[0x10]; 9008 u8 reserved_at_10[0x10]; 9009 9010 u8 reserved_at_20[0x10]; 9011 u8 op_mod[0x10]; 9012 9013 u8 reserved_at_40[0x20]; 9014 9015 u8 reserved_at_60[0x10]; 9016 u8 vxlan_udp_port[0x10]; 9017 }; 9018 9019 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9020 u8 status[0x8]; 9021 u8 reserved_at_8[0x18]; 9022 9023 u8 syndrome[0x20]; 9024 9025 u8 reserved_at_40[0x40]; 9026 }; 9027 9028 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9029 u8 rate_limit[0x20]; 9030 9031 u8 burst_upper_bound[0x20]; 9032 9033 u8 reserved_at_40[0x10]; 9034 u8 typical_packet_size[0x10]; 9035 9036 u8 reserved_at_60[0x120]; 9037 }; 9038 9039 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9040 u8 opcode[0x10]; 9041 u8 uid[0x10]; 9042 9043 u8 reserved_at_20[0x10]; 9044 u8 op_mod[0x10]; 9045 9046 u8 reserved_at_40[0x10]; 9047 u8 rate_limit_index[0x10]; 9048 9049 u8 reserved_at_60[0x20]; 9050 9051 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9052 }; 9053 9054 struct mlx5_ifc_access_register_out_bits { 9055 u8 status[0x8]; 9056 u8 reserved_at_8[0x18]; 9057 9058 u8 syndrome[0x20]; 9059 9060 u8 reserved_at_40[0x40]; 9061 9062 u8 register_data[][0x20]; 9063 }; 9064 9065 enum { 9066 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9067 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9068 }; 9069 9070 struct mlx5_ifc_access_register_in_bits { 9071 u8 opcode[0x10]; 9072 u8 reserved_at_10[0x10]; 9073 9074 u8 reserved_at_20[0x10]; 9075 u8 op_mod[0x10]; 9076 9077 u8 reserved_at_40[0x10]; 9078 u8 register_id[0x10]; 9079 9080 u8 argument[0x20]; 9081 9082 u8 register_data[][0x20]; 9083 }; 9084 9085 struct mlx5_ifc_sltp_reg_bits { 9086 u8 status[0x4]; 9087 u8 version[0x4]; 9088 u8 local_port[0x8]; 9089 u8 pnat[0x2]; 9090 u8 reserved_at_12[0x2]; 9091 u8 lane[0x4]; 9092 u8 reserved_at_18[0x8]; 9093 9094 u8 reserved_at_20[0x20]; 9095 9096 u8 reserved_at_40[0x7]; 9097 u8 polarity[0x1]; 9098 u8 ob_tap0[0x8]; 9099 u8 ob_tap1[0x8]; 9100 u8 ob_tap2[0x8]; 9101 9102 u8 reserved_at_60[0xc]; 9103 u8 ob_preemp_mode[0x4]; 9104 u8 ob_reg[0x8]; 9105 u8 ob_bias[0x8]; 9106 9107 u8 reserved_at_80[0x20]; 9108 }; 9109 9110 struct mlx5_ifc_slrg_reg_bits { 9111 u8 status[0x4]; 9112 u8 version[0x4]; 9113 u8 local_port[0x8]; 9114 u8 pnat[0x2]; 9115 u8 reserved_at_12[0x2]; 9116 u8 lane[0x4]; 9117 u8 reserved_at_18[0x8]; 9118 9119 u8 time_to_link_up[0x10]; 9120 u8 reserved_at_30[0xc]; 9121 u8 grade_lane_speed[0x4]; 9122 9123 u8 grade_version[0x8]; 9124 u8 grade[0x18]; 9125 9126 u8 reserved_at_60[0x4]; 9127 u8 height_grade_type[0x4]; 9128 u8 height_grade[0x18]; 9129 9130 u8 height_dz[0x10]; 9131 u8 height_dv[0x10]; 9132 9133 u8 reserved_at_a0[0x10]; 9134 u8 height_sigma[0x10]; 9135 9136 u8 reserved_at_c0[0x20]; 9137 9138 u8 reserved_at_e0[0x4]; 9139 u8 phase_grade_type[0x4]; 9140 u8 phase_grade[0x18]; 9141 9142 u8 reserved_at_100[0x8]; 9143 u8 phase_eo_pos[0x8]; 9144 u8 reserved_at_110[0x8]; 9145 u8 phase_eo_neg[0x8]; 9146 9147 u8 ffe_set_tested[0x10]; 9148 u8 test_errors_per_lane[0x10]; 9149 }; 9150 9151 struct mlx5_ifc_pvlc_reg_bits { 9152 u8 reserved_at_0[0x8]; 9153 u8 local_port[0x8]; 9154 u8 reserved_at_10[0x10]; 9155 9156 u8 reserved_at_20[0x1c]; 9157 u8 vl_hw_cap[0x4]; 9158 9159 u8 reserved_at_40[0x1c]; 9160 u8 vl_admin[0x4]; 9161 9162 u8 reserved_at_60[0x1c]; 9163 u8 vl_operational[0x4]; 9164 }; 9165 9166 struct mlx5_ifc_pude_reg_bits { 9167 u8 swid[0x8]; 9168 u8 local_port[0x8]; 9169 u8 reserved_at_10[0x4]; 9170 u8 admin_status[0x4]; 9171 u8 reserved_at_18[0x4]; 9172 u8 oper_status[0x4]; 9173 9174 u8 reserved_at_20[0x60]; 9175 }; 9176 9177 struct mlx5_ifc_ptys_reg_bits { 9178 u8 reserved_at_0[0x1]; 9179 u8 an_disable_admin[0x1]; 9180 u8 an_disable_cap[0x1]; 9181 u8 reserved_at_3[0x5]; 9182 u8 local_port[0x8]; 9183 u8 reserved_at_10[0xd]; 9184 u8 proto_mask[0x3]; 9185 9186 u8 an_status[0x4]; 9187 u8 reserved_at_24[0xc]; 9188 u8 data_rate_oper[0x10]; 9189 9190 u8 ext_eth_proto_capability[0x20]; 9191 9192 u8 eth_proto_capability[0x20]; 9193 9194 u8 ib_link_width_capability[0x10]; 9195 u8 ib_proto_capability[0x10]; 9196 9197 u8 ext_eth_proto_admin[0x20]; 9198 9199 u8 eth_proto_admin[0x20]; 9200 9201 u8 ib_link_width_admin[0x10]; 9202 u8 ib_proto_admin[0x10]; 9203 9204 u8 ext_eth_proto_oper[0x20]; 9205 9206 u8 eth_proto_oper[0x20]; 9207 9208 u8 ib_link_width_oper[0x10]; 9209 u8 ib_proto_oper[0x10]; 9210 9211 u8 reserved_at_160[0x1c]; 9212 u8 connector_type[0x4]; 9213 9214 u8 eth_proto_lp_advertise[0x20]; 9215 9216 u8 reserved_at_1a0[0x60]; 9217 }; 9218 9219 struct mlx5_ifc_mlcr_reg_bits { 9220 u8 reserved_at_0[0x8]; 9221 u8 local_port[0x8]; 9222 u8 reserved_at_10[0x20]; 9223 9224 u8 beacon_duration[0x10]; 9225 u8 reserved_at_40[0x10]; 9226 9227 u8 beacon_remain[0x10]; 9228 }; 9229 9230 struct mlx5_ifc_ptas_reg_bits { 9231 u8 reserved_at_0[0x20]; 9232 9233 u8 algorithm_options[0x10]; 9234 u8 reserved_at_30[0x4]; 9235 u8 repetitions_mode[0x4]; 9236 u8 num_of_repetitions[0x8]; 9237 9238 u8 grade_version[0x8]; 9239 u8 height_grade_type[0x4]; 9240 u8 phase_grade_type[0x4]; 9241 u8 height_grade_weight[0x8]; 9242 u8 phase_grade_weight[0x8]; 9243 9244 u8 gisim_measure_bits[0x10]; 9245 u8 adaptive_tap_measure_bits[0x10]; 9246 9247 u8 ber_bath_high_error_threshold[0x10]; 9248 u8 ber_bath_mid_error_threshold[0x10]; 9249 9250 u8 ber_bath_low_error_threshold[0x10]; 9251 u8 one_ratio_high_threshold[0x10]; 9252 9253 u8 one_ratio_high_mid_threshold[0x10]; 9254 u8 one_ratio_low_mid_threshold[0x10]; 9255 9256 u8 one_ratio_low_threshold[0x10]; 9257 u8 ndeo_error_threshold[0x10]; 9258 9259 u8 mixer_offset_step_size[0x10]; 9260 u8 reserved_at_110[0x8]; 9261 u8 mix90_phase_for_voltage_bath[0x8]; 9262 9263 u8 mixer_offset_start[0x10]; 9264 u8 mixer_offset_end[0x10]; 9265 9266 u8 reserved_at_140[0x15]; 9267 u8 ber_test_time[0xb]; 9268 }; 9269 9270 struct mlx5_ifc_pspa_reg_bits { 9271 u8 swid[0x8]; 9272 u8 local_port[0x8]; 9273 u8 sub_port[0x8]; 9274 u8 reserved_at_18[0x8]; 9275 9276 u8 reserved_at_20[0x20]; 9277 }; 9278 9279 struct mlx5_ifc_pqdr_reg_bits { 9280 u8 reserved_at_0[0x8]; 9281 u8 local_port[0x8]; 9282 u8 reserved_at_10[0x5]; 9283 u8 prio[0x3]; 9284 u8 reserved_at_18[0x6]; 9285 u8 mode[0x2]; 9286 9287 u8 reserved_at_20[0x20]; 9288 9289 u8 reserved_at_40[0x10]; 9290 u8 min_threshold[0x10]; 9291 9292 u8 reserved_at_60[0x10]; 9293 u8 max_threshold[0x10]; 9294 9295 u8 reserved_at_80[0x10]; 9296 u8 mark_probability_denominator[0x10]; 9297 9298 u8 reserved_at_a0[0x60]; 9299 }; 9300 9301 struct mlx5_ifc_ppsc_reg_bits { 9302 u8 reserved_at_0[0x8]; 9303 u8 local_port[0x8]; 9304 u8 reserved_at_10[0x10]; 9305 9306 u8 reserved_at_20[0x60]; 9307 9308 u8 reserved_at_80[0x1c]; 9309 u8 wrps_admin[0x4]; 9310 9311 u8 reserved_at_a0[0x1c]; 9312 u8 wrps_status[0x4]; 9313 9314 u8 reserved_at_c0[0x8]; 9315 u8 up_threshold[0x8]; 9316 u8 reserved_at_d0[0x8]; 9317 u8 down_threshold[0x8]; 9318 9319 u8 reserved_at_e0[0x20]; 9320 9321 u8 reserved_at_100[0x1c]; 9322 u8 srps_admin[0x4]; 9323 9324 u8 reserved_at_120[0x1c]; 9325 u8 srps_status[0x4]; 9326 9327 u8 reserved_at_140[0x40]; 9328 }; 9329 9330 struct mlx5_ifc_pplr_reg_bits { 9331 u8 reserved_at_0[0x8]; 9332 u8 local_port[0x8]; 9333 u8 reserved_at_10[0x10]; 9334 9335 u8 reserved_at_20[0x8]; 9336 u8 lb_cap[0x8]; 9337 u8 reserved_at_30[0x8]; 9338 u8 lb_en[0x8]; 9339 }; 9340 9341 struct mlx5_ifc_pplm_reg_bits { 9342 u8 reserved_at_0[0x8]; 9343 u8 local_port[0x8]; 9344 u8 reserved_at_10[0x10]; 9345 9346 u8 reserved_at_20[0x20]; 9347 9348 u8 port_profile_mode[0x8]; 9349 u8 static_port_profile[0x8]; 9350 u8 active_port_profile[0x8]; 9351 u8 reserved_at_58[0x8]; 9352 9353 u8 retransmission_active[0x8]; 9354 u8 fec_mode_active[0x18]; 9355 9356 u8 rs_fec_correction_bypass_cap[0x4]; 9357 u8 reserved_at_84[0x8]; 9358 u8 fec_override_cap_56g[0x4]; 9359 u8 fec_override_cap_100g[0x4]; 9360 u8 fec_override_cap_50g[0x4]; 9361 u8 fec_override_cap_25g[0x4]; 9362 u8 fec_override_cap_10g_40g[0x4]; 9363 9364 u8 rs_fec_correction_bypass_admin[0x4]; 9365 u8 reserved_at_a4[0x8]; 9366 u8 fec_override_admin_56g[0x4]; 9367 u8 fec_override_admin_100g[0x4]; 9368 u8 fec_override_admin_50g[0x4]; 9369 u8 fec_override_admin_25g[0x4]; 9370 u8 fec_override_admin_10g_40g[0x4]; 9371 9372 u8 fec_override_cap_400g_8x[0x10]; 9373 u8 fec_override_cap_200g_4x[0x10]; 9374 9375 u8 fec_override_cap_100g_2x[0x10]; 9376 u8 fec_override_cap_50g_1x[0x10]; 9377 9378 u8 fec_override_admin_400g_8x[0x10]; 9379 u8 fec_override_admin_200g_4x[0x10]; 9380 9381 u8 fec_override_admin_100g_2x[0x10]; 9382 u8 fec_override_admin_50g_1x[0x10]; 9383 9384 u8 reserved_at_140[0x140]; 9385 }; 9386 9387 struct mlx5_ifc_ppcnt_reg_bits { 9388 u8 swid[0x8]; 9389 u8 local_port[0x8]; 9390 u8 pnat[0x2]; 9391 u8 reserved_at_12[0x8]; 9392 u8 grp[0x6]; 9393 9394 u8 clr[0x1]; 9395 u8 reserved_at_21[0x1c]; 9396 u8 prio_tc[0x3]; 9397 9398 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9399 }; 9400 9401 struct mlx5_ifc_mpein_reg_bits { 9402 u8 reserved_at_0[0x2]; 9403 u8 depth[0x6]; 9404 u8 pcie_index[0x8]; 9405 u8 node[0x8]; 9406 u8 reserved_at_18[0x8]; 9407 9408 u8 capability_mask[0x20]; 9409 9410 u8 reserved_at_40[0x8]; 9411 u8 link_width_enabled[0x8]; 9412 u8 link_speed_enabled[0x10]; 9413 9414 u8 lane0_physical_position[0x8]; 9415 u8 link_width_active[0x8]; 9416 u8 link_speed_active[0x10]; 9417 9418 u8 num_of_pfs[0x10]; 9419 u8 num_of_vfs[0x10]; 9420 9421 u8 bdf0[0x10]; 9422 u8 reserved_at_b0[0x10]; 9423 9424 u8 max_read_request_size[0x4]; 9425 u8 max_payload_size[0x4]; 9426 u8 reserved_at_c8[0x5]; 9427 u8 pwr_status[0x3]; 9428 u8 port_type[0x4]; 9429 u8 reserved_at_d4[0xb]; 9430 u8 lane_reversal[0x1]; 9431 9432 u8 reserved_at_e0[0x14]; 9433 u8 pci_power[0xc]; 9434 9435 u8 reserved_at_100[0x20]; 9436 9437 u8 device_status[0x10]; 9438 u8 port_state[0x8]; 9439 u8 reserved_at_138[0x8]; 9440 9441 u8 reserved_at_140[0x10]; 9442 u8 receiver_detect_result[0x10]; 9443 9444 u8 reserved_at_160[0x20]; 9445 }; 9446 9447 struct mlx5_ifc_mpcnt_reg_bits { 9448 u8 reserved_at_0[0x8]; 9449 u8 pcie_index[0x8]; 9450 u8 reserved_at_10[0xa]; 9451 u8 grp[0x6]; 9452 9453 u8 clr[0x1]; 9454 u8 reserved_at_21[0x1f]; 9455 9456 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9457 }; 9458 9459 struct mlx5_ifc_ppad_reg_bits { 9460 u8 reserved_at_0[0x3]; 9461 u8 single_mac[0x1]; 9462 u8 reserved_at_4[0x4]; 9463 u8 local_port[0x8]; 9464 u8 mac_47_32[0x10]; 9465 9466 u8 mac_31_0[0x20]; 9467 9468 u8 reserved_at_40[0x40]; 9469 }; 9470 9471 struct mlx5_ifc_pmtu_reg_bits { 9472 u8 reserved_at_0[0x8]; 9473 u8 local_port[0x8]; 9474 u8 reserved_at_10[0x10]; 9475 9476 u8 max_mtu[0x10]; 9477 u8 reserved_at_30[0x10]; 9478 9479 u8 admin_mtu[0x10]; 9480 u8 reserved_at_50[0x10]; 9481 9482 u8 oper_mtu[0x10]; 9483 u8 reserved_at_70[0x10]; 9484 }; 9485 9486 struct mlx5_ifc_pmpr_reg_bits { 9487 u8 reserved_at_0[0x8]; 9488 u8 module[0x8]; 9489 u8 reserved_at_10[0x10]; 9490 9491 u8 reserved_at_20[0x18]; 9492 u8 attenuation_5g[0x8]; 9493 9494 u8 reserved_at_40[0x18]; 9495 u8 attenuation_7g[0x8]; 9496 9497 u8 reserved_at_60[0x18]; 9498 u8 attenuation_12g[0x8]; 9499 }; 9500 9501 struct mlx5_ifc_pmpe_reg_bits { 9502 u8 reserved_at_0[0x8]; 9503 u8 module[0x8]; 9504 u8 reserved_at_10[0xc]; 9505 u8 module_status[0x4]; 9506 9507 u8 reserved_at_20[0x60]; 9508 }; 9509 9510 struct mlx5_ifc_pmpc_reg_bits { 9511 u8 module_state_updated[32][0x8]; 9512 }; 9513 9514 struct mlx5_ifc_pmlpn_reg_bits { 9515 u8 reserved_at_0[0x4]; 9516 u8 mlpn_status[0x4]; 9517 u8 local_port[0x8]; 9518 u8 reserved_at_10[0x10]; 9519 9520 u8 e[0x1]; 9521 u8 reserved_at_21[0x1f]; 9522 }; 9523 9524 struct mlx5_ifc_pmlp_reg_bits { 9525 u8 rxtx[0x1]; 9526 u8 reserved_at_1[0x7]; 9527 u8 local_port[0x8]; 9528 u8 reserved_at_10[0x8]; 9529 u8 width[0x8]; 9530 9531 u8 lane0_module_mapping[0x20]; 9532 9533 u8 lane1_module_mapping[0x20]; 9534 9535 u8 lane2_module_mapping[0x20]; 9536 9537 u8 lane3_module_mapping[0x20]; 9538 9539 u8 reserved_at_a0[0x160]; 9540 }; 9541 9542 struct mlx5_ifc_pmaos_reg_bits { 9543 u8 reserved_at_0[0x8]; 9544 u8 module[0x8]; 9545 u8 reserved_at_10[0x4]; 9546 u8 admin_status[0x4]; 9547 u8 reserved_at_18[0x4]; 9548 u8 oper_status[0x4]; 9549 9550 u8 ase[0x1]; 9551 u8 ee[0x1]; 9552 u8 reserved_at_22[0x1c]; 9553 u8 e[0x2]; 9554 9555 u8 reserved_at_40[0x40]; 9556 }; 9557 9558 struct mlx5_ifc_plpc_reg_bits { 9559 u8 reserved_at_0[0x4]; 9560 u8 profile_id[0xc]; 9561 u8 reserved_at_10[0x4]; 9562 u8 proto_mask[0x4]; 9563 u8 reserved_at_18[0x8]; 9564 9565 u8 reserved_at_20[0x10]; 9566 u8 lane_speed[0x10]; 9567 9568 u8 reserved_at_40[0x17]; 9569 u8 lpbf[0x1]; 9570 u8 fec_mode_policy[0x8]; 9571 9572 u8 retransmission_capability[0x8]; 9573 u8 fec_mode_capability[0x18]; 9574 9575 u8 retransmission_support_admin[0x8]; 9576 u8 fec_mode_support_admin[0x18]; 9577 9578 u8 retransmission_request_admin[0x8]; 9579 u8 fec_mode_request_admin[0x18]; 9580 9581 u8 reserved_at_c0[0x80]; 9582 }; 9583 9584 struct mlx5_ifc_plib_reg_bits { 9585 u8 reserved_at_0[0x8]; 9586 u8 local_port[0x8]; 9587 u8 reserved_at_10[0x8]; 9588 u8 ib_port[0x8]; 9589 9590 u8 reserved_at_20[0x60]; 9591 }; 9592 9593 struct mlx5_ifc_plbf_reg_bits { 9594 u8 reserved_at_0[0x8]; 9595 u8 local_port[0x8]; 9596 u8 reserved_at_10[0xd]; 9597 u8 lbf_mode[0x3]; 9598 9599 u8 reserved_at_20[0x20]; 9600 }; 9601 9602 struct mlx5_ifc_pipg_reg_bits { 9603 u8 reserved_at_0[0x8]; 9604 u8 local_port[0x8]; 9605 u8 reserved_at_10[0x10]; 9606 9607 u8 dic[0x1]; 9608 u8 reserved_at_21[0x19]; 9609 u8 ipg[0x4]; 9610 u8 reserved_at_3e[0x2]; 9611 }; 9612 9613 struct mlx5_ifc_pifr_reg_bits { 9614 u8 reserved_at_0[0x8]; 9615 u8 local_port[0x8]; 9616 u8 reserved_at_10[0x10]; 9617 9618 u8 reserved_at_20[0xe0]; 9619 9620 u8 port_filter[8][0x20]; 9621 9622 u8 port_filter_update_en[8][0x20]; 9623 }; 9624 9625 struct mlx5_ifc_pfcc_reg_bits { 9626 u8 reserved_at_0[0x8]; 9627 u8 local_port[0x8]; 9628 u8 reserved_at_10[0xb]; 9629 u8 ppan_mask_n[0x1]; 9630 u8 minor_stall_mask[0x1]; 9631 u8 critical_stall_mask[0x1]; 9632 u8 reserved_at_1e[0x2]; 9633 9634 u8 ppan[0x4]; 9635 u8 reserved_at_24[0x4]; 9636 u8 prio_mask_tx[0x8]; 9637 u8 reserved_at_30[0x8]; 9638 u8 prio_mask_rx[0x8]; 9639 9640 u8 pptx[0x1]; 9641 u8 aptx[0x1]; 9642 u8 pptx_mask_n[0x1]; 9643 u8 reserved_at_43[0x5]; 9644 u8 pfctx[0x8]; 9645 u8 reserved_at_50[0x10]; 9646 9647 u8 pprx[0x1]; 9648 u8 aprx[0x1]; 9649 u8 pprx_mask_n[0x1]; 9650 u8 reserved_at_63[0x5]; 9651 u8 pfcrx[0x8]; 9652 u8 reserved_at_70[0x10]; 9653 9654 u8 device_stall_minor_watermark[0x10]; 9655 u8 device_stall_critical_watermark[0x10]; 9656 9657 u8 reserved_at_a0[0x60]; 9658 }; 9659 9660 struct mlx5_ifc_pelc_reg_bits { 9661 u8 op[0x4]; 9662 u8 reserved_at_4[0x4]; 9663 u8 local_port[0x8]; 9664 u8 reserved_at_10[0x10]; 9665 9666 u8 op_admin[0x8]; 9667 u8 op_capability[0x8]; 9668 u8 op_request[0x8]; 9669 u8 op_active[0x8]; 9670 9671 u8 admin[0x40]; 9672 9673 u8 capability[0x40]; 9674 9675 u8 request[0x40]; 9676 9677 u8 active[0x40]; 9678 9679 u8 reserved_at_140[0x80]; 9680 }; 9681 9682 struct mlx5_ifc_peir_reg_bits { 9683 u8 reserved_at_0[0x8]; 9684 u8 local_port[0x8]; 9685 u8 reserved_at_10[0x10]; 9686 9687 u8 reserved_at_20[0xc]; 9688 u8 error_count[0x4]; 9689 u8 reserved_at_30[0x10]; 9690 9691 u8 reserved_at_40[0xc]; 9692 u8 lane[0x4]; 9693 u8 reserved_at_50[0x8]; 9694 u8 error_type[0x8]; 9695 }; 9696 9697 struct mlx5_ifc_mpegc_reg_bits { 9698 u8 reserved_at_0[0x30]; 9699 u8 field_select[0x10]; 9700 9701 u8 tx_overflow_sense[0x1]; 9702 u8 mark_cqe[0x1]; 9703 u8 mark_cnp[0x1]; 9704 u8 reserved_at_43[0x1b]; 9705 u8 tx_lossy_overflow_oper[0x2]; 9706 9707 u8 reserved_at_60[0x100]; 9708 }; 9709 9710 enum { 9711 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9712 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9713 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9714 }; 9715 9716 struct mlx5_ifc_mtutc_reg_bits { 9717 u8 reserved_at_0[0x1c]; 9718 u8 operation[0x4]; 9719 9720 u8 freq_adjustment[0x20]; 9721 9722 u8 reserved_at_40[0x40]; 9723 9724 u8 utc_sec[0x20]; 9725 9726 u8 reserved_at_a0[0x2]; 9727 u8 utc_nsec[0x1e]; 9728 9729 u8 time_adjustment[0x20]; 9730 }; 9731 9732 struct mlx5_ifc_pcam_enhanced_features_bits { 9733 u8 reserved_at_0[0x68]; 9734 u8 fec_50G_per_lane_in_pplm[0x1]; 9735 u8 reserved_at_69[0x4]; 9736 u8 rx_icrc_encapsulated_counter[0x1]; 9737 u8 reserved_at_6e[0x4]; 9738 u8 ptys_extended_ethernet[0x1]; 9739 u8 reserved_at_73[0x3]; 9740 u8 pfcc_mask[0x1]; 9741 u8 reserved_at_77[0x3]; 9742 u8 per_lane_error_counters[0x1]; 9743 u8 rx_buffer_fullness_counters[0x1]; 9744 u8 ptys_connector_type[0x1]; 9745 u8 reserved_at_7d[0x1]; 9746 u8 ppcnt_discard_group[0x1]; 9747 u8 ppcnt_statistical_group[0x1]; 9748 }; 9749 9750 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9751 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9752 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9753 9754 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9755 u8 pplm[0x1]; 9756 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9757 9758 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9759 u8 pbmc[0x1]; 9760 u8 pptb[0x1]; 9761 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9762 u8 ppcnt[0x1]; 9763 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9764 }; 9765 9766 struct mlx5_ifc_pcam_reg_bits { 9767 u8 reserved_at_0[0x8]; 9768 u8 feature_group[0x8]; 9769 u8 reserved_at_10[0x8]; 9770 u8 access_reg_group[0x8]; 9771 9772 u8 reserved_at_20[0x20]; 9773 9774 union { 9775 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9776 u8 reserved_at_0[0x80]; 9777 } port_access_reg_cap_mask; 9778 9779 u8 reserved_at_c0[0x80]; 9780 9781 union { 9782 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9783 u8 reserved_at_0[0x80]; 9784 } feature_cap_mask; 9785 9786 u8 reserved_at_1c0[0xc0]; 9787 }; 9788 9789 struct mlx5_ifc_mcam_enhanced_features_bits { 9790 u8 reserved_at_0[0x5d]; 9791 u8 mcia_32dwords[0x1]; 9792 u8 reserved_at_5e[0xc]; 9793 u8 reset_state[0x1]; 9794 u8 ptpcyc2realtime_modify[0x1]; 9795 u8 reserved_at_6c[0x2]; 9796 u8 pci_status_and_power[0x1]; 9797 u8 reserved_at_6f[0x5]; 9798 u8 mark_tx_action_cnp[0x1]; 9799 u8 mark_tx_action_cqe[0x1]; 9800 u8 dynamic_tx_overflow[0x1]; 9801 u8 reserved_at_77[0x4]; 9802 u8 pcie_outbound_stalled[0x1]; 9803 u8 tx_overflow_buffer_pkt[0x1]; 9804 u8 mtpps_enh_out_per_adj[0x1]; 9805 u8 mtpps_fs[0x1]; 9806 u8 pcie_performance_group[0x1]; 9807 }; 9808 9809 struct mlx5_ifc_mcam_access_reg_bits { 9810 u8 reserved_at_0[0x1c]; 9811 u8 mcda[0x1]; 9812 u8 mcc[0x1]; 9813 u8 mcqi[0x1]; 9814 u8 mcqs[0x1]; 9815 9816 u8 regs_95_to_87[0x9]; 9817 u8 mpegc[0x1]; 9818 u8 mtutc[0x1]; 9819 u8 regs_84_to_68[0x11]; 9820 u8 tracer_registers[0x4]; 9821 9822 u8 regs_63_to_46[0x12]; 9823 u8 mrtc[0x1]; 9824 u8 regs_44_to_32[0xd]; 9825 9826 u8 regs_31_to_0[0x20]; 9827 }; 9828 9829 struct mlx5_ifc_mcam_access_reg_bits1 { 9830 u8 regs_127_to_96[0x20]; 9831 9832 u8 regs_95_to_64[0x20]; 9833 9834 u8 regs_63_to_32[0x20]; 9835 9836 u8 regs_31_to_0[0x20]; 9837 }; 9838 9839 struct mlx5_ifc_mcam_access_reg_bits2 { 9840 u8 regs_127_to_99[0x1d]; 9841 u8 mirc[0x1]; 9842 u8 regs_97_to_96[0x2]; 9843 9844 u8 regs_95_to_64[0x20]; 9845 9846 u8 regs_63_to_32[0x20]; 9847 9848 u8 regs_31_to_0[0x20]; 9849 }; 9850 9851 struct mlx5_ifc_mcam_reg_bits { 9852 u8 reserved_at_0[0x8]; 9853 u8 feature_group[0x8]; 9854 u8 reserved_at_10[0x8]; 9855 u8 access_reg_group[0x8]; 9856 9857 u8 reserved_at_20[0x20]; 9858 9859 union { 9860 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9861 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9862 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9863 u8 reserved_at_0[0x80]; 9864 } mng_access_reg_cap_mask; 9865 9866 u8 reserved_at_c0[0x80]; 9867 9868 union { 9869 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9870 u8 reserved_at_0[0x80]; 9871 } mng_feature_cap_mask; 9872 9873 u8 reserved_at_1c0[0x80]; 9874 }; 9875 9876 struct mlx5_ifc_qcam_access_reg_cap_mask { 9877 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9878 u8 qpdpm[0x1]; 9879 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9880 u8 qdpm[0x1]; 9881 u8 qpts[0x1]; 9882 u8 qcap[0x1]; 9883 u8 qcam_access_reg_cap_mask_0[0x1]; 9884 }; 9885 9886 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9887 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9888 u8 qpts_trust_both[0x1]; 9889 }; 9890 9891 struct mlx5_ifc_qcam_reg_bits { 9892 u8 reserved_at_0[0x8]; 9893 u8 feature_group[0x8]; 9894 u8 reserved_at_10[0x8]; 9895 u8 access_reg_group[0x8]; 9896 u8 reserved_at_20[0x20]; 9897 9898 union { 9899 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9900 u8 reserved_at_0[0x80]; 9901 } qos_access_reg_cap_mask; 9902 9903 u8 reserved_at_c0[0x80]; 9904 9905 union { 9906 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9907 u8 reserved_at_0[0x80]; 9908 } qos_feature_cap_mask; 9909 9910 u8 reserved_at_1c0[0x80]; 9911 }; 9912 9913 struct mlx5_ifc_core_dump_reg_bits { 9914 u8 reserved_at_0[0x18]; 9915 u8 core_dump_type[0x8]; 9916 9917 u8 reserved_at_20[0x30]; 9918 u8 vhca_id[0x10]; 9919 9920 u8 reserved_at_60[0x8]; 9921 u8 qpn[0x18]; 9922 u8 reserved_at_80[0x180]; 9923 }; 9924 9925 struct mlx5_ifc_pcap_reg_bits { 9926 u8 reserved_at_0[0x8]; 9927 u8 local_port[0x8]; 9928 u8 reserved_at_10[0x10]; 9929 9930 u8 port_capability_mask[4][0x20]; 9931 }; 9932 9933 struct mlx5_ifc_paos_reg_bits { 9934 u8 swid[0x8]; 9935 u8 local_port[0x8]; 9936 u8 reserved_at_10[0x4]; 9937 u8 admin_status[0x4]; 9938 u8 reserved_at_18[0x4]; 9939 u8 oper_status[0x4]; 9940 9941 u8 ase[0x1]; 9942 u8 ee[0x1]; 9943 u8 reserved_at_22[0x1c]; 9944 u8 e[0x2]; 9945 9946 u8 reserved_at_40[0x40]; 9947 }; 9948 9949 struct mlx5_ifc_pamp_reg_bits { 9950 u8 reserved_at_0[0x8]; 9951 u8 opamp_group[0x8]; 9952 u8 reserved_at_10[0xc]; 9953 u8 opamp_group_type[0x4]; 9954 9955 u8 start_index[0x10]; 9956 u8 reserved_at_30[0x4]; 9957 u8 num_of_indices[0xc]; 9958 9959 u8 index_data[18][0x10]; 9960 }; 9961 9962 struct mlx5_ifc_pcmr_reg_bits { 9963 u8 reserved_at_0[0x8]; 9964 u8 local_port[0x8]; 9965 u8 reserved_at_10[0x10]; 9966 9967 u8 entropy_force_cap[0x1]; 9968 u8 entropy_calc_cap[0x1]; 9969 u8 entropy_gre_calc_cap[0x1]; 9970 u8 reserved_at_23[0xf]; 9971 u8 rx_ts_over_crc_cap[0x1]; 9972 u8 reserved_at_33[0xb]; 9973 u8 fcs_cap[0x1]; 9974 u8 reserved_at_3f[0x1]; 9975 9976 u8 entropy_force[0x1]; 9977 u8 entropy_calc[0x1]; 9978 u8 entropy_gre_calc[0x1]; 9979 u8 reserved_at_43[0xf]; 9980 u8 rx_ts_over_crc[0x1]; 9981 u8 reserved_at_53[0xb]; 9982 u8 fcs_chk[0x1]; 9983 u8 reserved_at_5f[0x1]; 9984 }; 9985 9986 struct mlx5_ifc_lane_2_module_mapping_bits { 9987 u8 reserved_at_0[0x4]; 9988 u8 rx_lane[0x4]; 9989 u8 reserved_at_8[0x4]; 9990 u8 tx_lane[0x4]; 9991 u8 reserved_at_10[0x8]; 9992 u8 module[0x8]; 9993 }; 9994 9995 struct mlx5_ifc_bufferx_reg_bits { 9996 u8 reserved_at_0[0x6]; 9997 u8 lossy[0x1]; 9998 u8 epsb[0x1]; 9999 u8 reserved_at_8[0x8]; 10000 u8 size[0x10]; 10001 10002 u8 xoff_threshold[0x10]; 10003 u8 xon_threshold[0x10]; 10004 }; 10005 10006 struct mlx5_ifc_set_node_in_bits { 10007 u8 node_description[64][0x8]; 10008 }; 10009 10010 struct mlx5_ifc_register_power_settings_bits { 10011 u8 reserved_at_0[0x18]; 10012 u8 power_settings_level[0x8]; 10013 10014 u8 reserved_at_20[0x60]; 10015 }; 10016 10017 struct mlx5_ifc_register_host_endianness_bits { 10018 u8 he[0x1]; 10019 u8 reserved_at_1[0x1f]; 10020 10021 u8 reserved_at_20[0x60]; 10022 }; 10023 10024 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10025 u8 reserved_at_0[0x20]; 10026 10027 u8 mkey[0x20]; 10028 10029 u8 addressh_63_32[0x20]; 10030 10031 u8 addressl_31_0[0x20]; 10032 }; 10033 10034 struct mlx5_ifc_ud_adrs_vector_bits { 10035 u8 dc_key[0x40]; 10036 10037 u8 ext[0x1]; 10038 u8 reserved_at_41[0x7]; 10039 u8 destination_qp_dct[0x18]; 10040 10041 u8 static_rate[0x4]; 10042 u8 sl_eth_prio[0x4]; 10043 u8 fl[0x1]; 10044 u8 mlid[0x7]; 10045 u8 rlid_udp_sport[0x10]; 10046 10047 u8 reserved_at_80[0x20]; 10048 10049 u8 rmac_47_16[0x20]; 10050 10051 u8 rmac_15_0[0x10]; 10052 u8 tclass[0x8]; 10053 u8 hop_limit[0x8]; 10054 10055 u8 reserved_at_e0[0x1]; 10056 u8 grh[0x1]; 10057 u8 reserved_at_e2[0x2]; 10058 u8 src_addr_index[0x8]; 10059 u8 flow_label[0x14]; 10060 10061 u8 rgid_rip[16][0x8]; 10062 }; 10063 10064 struct mlx5_ifc_pages_req_event_bits { 10065 u8 reserved_at_0[0x10]; 10066 u8 function_id[0x10]; 10067 10068 u8 num_pages[0x20]; 10069 10070 u8 reserved_at_40[0xa0]; 10071 }; 10072 10073 struct mlx5_ifc_eqe_bits { 10074 u8 reserved_at_0[0x8]; 10075 u8 event_type[0x8]; 10076 u8 reserved_at_10[0x8]; 10077 u8 event_sub_type[0x8]; 10078 10079 u8 reserved_at_20[0xe0]; 10080 10081 union mlx5_ifc_event_auto_bits event_data; 10082 10083 u8 reserved_at_1e0[0x10]; 10084 u8 signature[0x8]; 10085 u8 reserved_at_1f8[0x7]; 10086 u8 owner[0x1]; 10087 }; 10088 10089 enum { 10090 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10091 }; 10092 10093 struct mlx5_ifc_cmd_queue_entry_bits { 10094 u8 type[0x8]; 10095 u8 reserved_at_8[0x18]; 10096 10097 u8 input_length[0x20]; 10098 10099 u8 input_mailbox_pointer_63_32[0x20]; 10100 10101 u8 input_mailbox_pointer_31_9[0x17]; 10102 u8 reserved_at_77[0x9]; 10103 10104 u8 command_input_inline_data[16][0x8]; 10105 10106 u8 command_output_inline_data[16][0x8]; 10107 10108 u8 output_mailbox_pointer_63_32[0x20]; 10109 10110 u8 output_mailbox_pointer_31_9[0x17]; 10111 u8 reserved_at_1b7[0x9]; 10112 10113 u8 output_length[0x20]; 10114 10115 u8 token[0x8]; 10116 u8 signature[0x8]; 10117 u8 reserved_at_1f0[0x8]; 10118 u8 status[0x7]; 10119 u8 ownership[0x1]; 10120 }; 10121 10122 struct mlx5_ifc_cmd_out_bits { 10123 u8 status[0x8]; 10124 u8 reserved_at_8[0x18]; 10125 10126 u8 syndrome[0x20]; 10127 10128 u8 command_output[0x20]; 10129 }; 10130 10131 struct mlx5_ifc_cmd_in_bits { 10132 u8 opcode[0x10]; 10133 u8 reserved_at_10[0x10]; 10134 10135 u8 reserved_at_20[0x10]; 10136 u8 op_mod[0x10]; 10137 10138 u8 command[][0x20]; 10139 }; 10140 10141 struct mlx5_ifc_cmd_if_box_bits { 10142 u8 mailbox_data[512][0x8]; 10143 10144 u8 reserved_at_1000[0x180]; 10145 10146 u8 next_pointer_63_32[0x20]; 10147 10148 u8 next_pointer_31_10[0x16]; 10149 u8 reserved_at_11b6[0xa]; 10150 10151 u8 block_number[0x20]; 10152 10153 u8 reserved_at_11e0[0x8]; 10154 u8 token[0x8]; 10155 u8 ctrl_signature[0x8]; 10156 u8 signature[0x8]; 10157 }; 10158 10159 struct mlx5_ifc_mtt_bits { 10160 u8 ptag_63_32[0x20]; 10161 10162 u8 ptag_31_8[0x18]; 10163 u8 reserved_at_38[0x6]; 10164 u8 wr_en[0x1]; 10165 u8 rd_en[0x1]; 10166 }; 10167 10168 struct mlx5_ifc_query_wol_rol_out_bits { 10169 u8 status[0x8]; 10170 u8 reserved_at_8[0x18]; 10171 10172 u8 syndrome[0x20]; 10173 10174 u8 reserved_at_40[0x10]; 10175 u8 rol_mode[0x8]; 10176 u8 wol_mode[0x8]; 10177 10178 u8 reserved_at_60[0x20]; 10179 }; 10180 10181 struct mlx5_ifc_query_wol_rol_in_bits { 10182 u8 opcode[0x10]; 10183 u8 reserved_at_10[0x10]; 10184 10185 u8 reserved_at_20[0x10]; 10186 u8 op_mod[0x10]; 10187 10188 u8 reserved_at_40[0x40]; 10189 }; 10190 10191 struct mlx5_ifc_set_wol_rol_out_bits { 10192 u8 status[0x8]; 10193 u8 reserved_at_8[0x18]; 10194 10195 u8 syndrome[0x20]; 10196 10197 u8 reserved_at_40[0x40]; 10198 }; 10199 10200 struct mlx5_ifc_set_wol_rol_in_bits { 10201 u8 opcode[0x10]; 10202 u8 reserved_at_10[0x10]; 10203 10204 u8 reserved_at_20[0x10]; 10205 u8 op_mod[0x10]; 10206 10207 u8 rol_mode_valid[0x1]; 10208 u8 wol_mode_valid[0x1]; 10209 u8 reserved_at_42[0xe]; 10210 u8 rol_mode[0x8]; 10211 u8 wol_mode[0x8]; 10212 10213 u8 reserved_at_60[0x20]; 10214 }; 10215 10216 enum { 10217 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10218 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10219 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10220 }; 10221 10222 enum { 10223 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10224 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10225 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10226 }; 10227 10228 enum { 10229 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10230 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10231 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10232 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10233 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10234 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10237 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10238 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10239 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10240 }; 10241 10242 struct mlx5_ifc_initial_seg_bits { 10243 u8 fw_rev_minor[0x10]; 10244 u8 fw_rev_major[0x10]; 10245 10246 u8 cmd_interface_rev[0x10]; 10247 u8 fw_rev_subminor[0x10]; 10248 10249 u8 reserved_at_40[0x40]; 10250 10251 u8 cmdq_phy_addr_63_32[0x20]; 10252 10253 u8 cmdq_phy_addr_31_12[0x14]; 10254 u8 reserved_at_b4[0x2]; 10255 u8 nic_interface[0x2]; 10256 u8 log_cmdq_size[0x4]; 10257 u8 log_cmdq_stride[0x4]; 10258 10259 u8 command_doorbell_vector[0x20]; 10260 10261 u8 reserved_at_e0[0xf00]; 10262 10263 u8 initializing[0x1]; 10264 u8 reserved_at_fe1[0x4]; 10265 u8 nic_interface_supported[0x3]; 10266 u8 embedded_cpu[0x1]; 10267 u8 reserved_at_fe9[0x17]; 10268 10269 struct mlx5_ifc_health_buffer_bits health_buffer; 10270 10271 u8 no_dram_nic_offset[0x20]; 10272 10273 u8 reserved_at_1220[0x6e40]; 10274 10275 u8 reserved_at_8060[0x1f]; 10276 u8 clear_int[0x1]; 10277 10278 u8 health_syndrome[0x8]; 10279 u8 health_counter[0x18]; 10280 10281 u8 reserved_at_80a0[0x17fc0]; 10282 }; 10283 10284 struct mlx5_ifc_mtpps_reg_bits { 10285 u8 reserved_at_0[0xc]; 10286 u8 cap_number_of_pps_pins[0x4]; 10287 u8 reserved_at_10[0x4]; 10288 u8 cap_max_num_of_pps_in_pins[0x4]; 10289 u8 reserved_at_18[0x4]; 10290 u8 cap_max_num_of_pps_out_pins[0x4]; 10291 10292 u8 reserved_at_20[0x24]; 10293 u8 cap_pin_3_mode[0x4]; 10294 u8 reserved_at_48[0x4]; 10295 u8 cap_pin_2_mode[0x4]; 10296 u8 reserved_at_50[0x4]; 10297 u8 cap_pin_1_mode[0x4]; 10298 u8 reserved_at_58[0x4]; 10299 u8 cap_pin_0_mode[0x4]; 10300 10301 u8 reserved_at_60[0x4]; 10302 u8 cap_pin_7_mode[0x4]; 10303 u8 reserved_at_68[0x4]; 10304 u8 cap_pin_6_mode[0x4]; 10305 u8 reserved_at_70[0x4]; 10306 u8 cap_pin_5_mode[0x4]; 10307 u8 reserved_at_78[0x4]; 10308 u8 cap_pin_4_mode[0x4]; 10309 10310 u8 field_select[0x20]; 10311 u8 reserved_at_a0[0x60]; 10312 10313 u8 enable[0x1]; 10314 u8 reserved_at_101[0xb]; 10315 u8 pattern[0x4]; 10316 u8 reserved_at_110[0x4]; 10317 u8 pin_mode[0x4]; 10318 u8 pin[0x8]; 10319 10320 u8 reserved_at_120[0x20]; 10321 10322 u8 time_stamp[0x40]; 10323 10324 u8 out_pulse_duration[0x10]; 10325 u8 out_periodic_adjustment[0x10]; 10326 u8 enhanced_out_periodic_adjustment[0x20]; 10327 10328 u8 reserved_at_1c0[0x20]; 10329 }; 10330 10331 struct mlx5_ifc_mtppse_reg_bits { 10332 u8 reserved_at_0[0x18]; 10333 u8 pin[0x8]; 10334 u8 event_arm[0x1]; 10335 u8 reserved_at_21[0x1b]; 10336 u8 event_generation_mode[0x4]; 10337 u8 reserved_at_40[0x40]; 10338 }; 10339 10340 struct mlx5_ifc_mcqs_reg_bits { 10341 u8 last_index_flag[0x1]; 10342 u8 reserved_at_1[0x7]; 10343 u8 fw_device[0x8]; 10344 u8 component_index[0x10]; 10345 10346 u8 reserved_at_20[0x10]; 10347 u8 identifier[0x10]; 10348 10349 u8 reserved_at_40[0x17]; 10350 u8 component_status[0x5]; 10351 u8 component_update_state[0x4]; 10352 10353 u8 last_update_state_changer_type[0x4]; 10354 u8 last_update_state_changer_host_id[0x4]; 10355 u8 reserved_at_68[0x18]; 10356 }; 10357 10358 struct mlx5_ifc_mcqi_cap_bits { 10359 u8 supported_info_bitmask[0x20]; 10360 10361 u8 component_size[0x20]; 10362 10363 u8 max_component_size[0x20]; 10364 10365 u8 log_mcda_word_size[0x4]; 10366 u8 reserved_at_64[0xc]; 10367 u8 mcda_max_write_size[0x10]; 10368 10369 u8 rd_en[0x1]; 10370 u8 reserved_at_81[0x1]; 10371 u8 match_chip_id[0x1]; 10372 u8 match_psid[0x1]; 10373 u8 check_user_timestamp[0x1]; 10374 u8 match_base_guid_mac[0x1]; 10375 u8 reserved_at_86[0x1a]; 10376 }; 10377 10378 struct mlx5_ifc_mcqi_version_bits { 10379 u8 reserved_at_0[0x2]; 10380 u8 build_time_valid[0x1]; 10381 u8 user_defined_time_valid[0x1]; 10382 u8 reserved_at_4[0x14]; 10383 u8 version_string_length[0x8]; 10384 10385 u8 version[0x20]; 10386 10387 u8 build_time[0x40]; 10388 10389 u8 user_defined_time[0x40]; 10390 10391 u8 build_tool_version[0x20]; 10392 10393 u8 reserved_at_e0[0x20]; 10394 10395 u8 version_string[92][0x8]; 10396 }; 10397 10398 struct mlx5_ifc_mcqi_activation_method_bits { 10399 u8 pending_server_ac_power_cycle[0x1]; 10400 u8 pending_server_dc_power_cycle[0x1]; 10401 u8 pending_server_reboot[0x1]; 10402 u8 pending_fw_reset[0x1]; 10403 u8 auto_activate[0x1]; 10404 u8 all_hosts_sync[0x1]; 10405 u8 device_hw_reset[0x1]; 10406 u8 reserved_at_7[0x19]; 10407 }; 10408 10409 union mlx5_ifc_mcqi_reg_data_bits { 10410 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10411 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10412 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10413 }; 10414 10415 struct mlx5_ifc_mcqi_reg_bits { 10416 u8 read_pending_component[0x1]; 10417 u8 reserved_at_1[0xf]; 10418 u8 component_index[0x10]; 10419 10420 u8 reserved_at_20[0x20]; 10421 10422 u8 reserved_at_40[0x1b]; 10423 u8 info_type[0x5]; 10424 10425 u8 info_size[0x20]; 10426 10427 u8 offset[0x20]; 10428 10429 u8 reserved_at_a0[0x10]; 10430 u8 data_size[0x10]; 10431 10432 union mlx5_ifc_mcqi_reg_data_bits data[]; 10433 }; 10434 10435 struct mlx5_ifc_mcc_reg_bits { 10436 u8 reserved_at_0[0x4]; 10437 u8 time_elapsed_since_last_cmd[0xc]; 10438 u8 reserved_at_10[0x8]; 10439 u8 instruction[0x8]; 10440 10441 u8 reserved_at_20[0x10]; 10442 u8 component_index[0x10]; 10443 10444 u8 reserved_at_40[0x8]; 10445 u8 update_handle[0x18]; 10446 10447 u8 handle_owner_type[0x4]; 10448 u8 handle_owner_host_id[0x4]; 10449 u8 reserved_at_68[0x1]; 10450 u8 control_progress[0x7]; 10451 u8 error_code[0x8]; 10452 u8 reserved_at_78[0x4]; 10453 u8 control_state[0x4]; 10454 10455 u8 component_size[0x20]; 10456 10457 u8 reserved_at_a0[0x60]; 10458 }; 10459 10460 struct mlx5_ifc_mcda_reg_bits { 10461 u8 reserved_at_0[0x8]; 10462 u8 update_handle[0x18]; 10463 10464 u8 offset[0x20]; 10465 10466 u8 reserved_at_40[0x10]; 10467 u8 size[0x10]; 10468 10469 u8 reserved_at_60[0x20]; 10470 10471 u8 data[][0x20]; 10472 }; 10473 10474 enum { 10475 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10476 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10477 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10478 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10479 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10480 }; 10481 10482 enum { 10483 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10484 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10485 }; 10486 10487 enum { 10488 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10489 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10490 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10491 }; 10492 10493 struct mlx5_ifc_mfrl_reg_bits { 10494 u8 reserved_at_0[0x20]; 10495 10496 u8 reserved_at_20[0x2]; 10497 u8 pci_sync_for_fw_update_start[0x1]; 10498 u8 pci_sync_for_fw_update_resp[0x2]; 10499 u8 rst_type_sel[0x3]; 10500 u8 reserved_at_28[0x4]; 10501 u8 reset_state[0x4]; 10502 u8 reset_type[0x8]; 10503 u8 reset_level[0x8]; 10504 }; 10505 10506 struct mlx5_ifc_mirc_reg_bits { 10507 u8 reserved_at_0[0x18]; 10508 u8 status_code[0x8]; 10509 10510 u8 reserved_at_20[0x20]; 10511 }; 10512 10513 struct mlx5_ifc_pddr_monitor_opcode_bits { 10514 u8 reserved_at_0[0x10]; 10515 u8 monitor_opcode[0x10]; 10516 }; 10517 10518 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10519 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10520 u8 reserved_at_0[0x20]; 10521 }; 10522 10523 enum { 10524 /* Monitor opcodes */ 10525 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10526 }; 10527 10528 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10529 u8 reserved_at_0[0x10]; 10530 u8 group_opcode[0x10]; 10531 10532 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10533 10534 u8 reserved_at_40[0x20]; 10535 10536 u8 status_message[59][0x20]; 10537 }; 10538 10539 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10540 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10541 u8 reserved_at_0[0x7c0]; 10542 }; 10543 10544 enum { 10545 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10546 }; 10547 10548 struct mlx5_ifc_pddr_reg_bits { 10549 u8 reserved_at_0[0x8]; 10550 u8 local_port[0x8]; 10551 u8 pnat[0x2]; 10552 u8 reserved_at_12[0xe]; 10553 10554 u8 reserved_at_20[0x18]; 10555 u8 page_select[0x8]; 10556 10557 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10558 }; 10559 10560 struct mlx5_ifc_mrtc_reg_bits { 10561 u8 time_synced[0x1]; 10562 u8 reserved_at_1[0x1f]; 10563 10564 u8 reserved_at_20[0x20]; 10565 10566 u8 time_h[0x20]; 10567 10568 u8 time_l[0x20]; 10569 }; 10570 10571 union mlx5_ifc_ports_control_registers_document_bits { 10572 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10573 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10574 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10575 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10576 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10577 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10578 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10579 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10580 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10581 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10582 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10583 struct mlx5_ifc_paos_reg_bits paos_reg; 10584 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10585 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10586 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10587 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10588 struct mlx5_ifc_peir_reg_bits peir_reg; 10589 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10590 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10591 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10592 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10593 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10594 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10595 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10596 struct mlx5_ifc_plib_reg_bits plib_reg; 10597 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10598 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10599 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10600 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10601 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10602 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10603 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10604 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10605 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10606 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10607 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10608 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10609 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10610 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10611 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10612 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10613 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10614 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10615 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10616 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10617 struct mlx5_ifc_pude_reg_bits pude_reg; 10618 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10619 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10620 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10621 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10622 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10623 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10624 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10625 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10626 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10627 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10628 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10629 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10630 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10631 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10632 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10633 u8 reserved_at_0[0x60e0]; 10634 }; 10635 10636 union mlx5_ifc_debug_enhancements_document_bits { 10637 struct mlx5_ifc_health_buffer_bits health_buffer; 10638 u8 reserved_at_0[0x200]; 10639 }; 10640 10641 union mlx5_ifc_uplink_pci_interface_document_bits { 10642 struct mlx5_ifc_initial_seg_bits initial_seg; 10643 u8 reserved_at_0[0x20060]; 10644 }; 10645 10646 struct mlx5_ifc_set_flow_table_root_out_bits { 10647 u8 status[0x8]; 10648 u8 reserved_at_8[0x18]; 10649 10650 u8 syndrome[0x20]; 10651 10652 u8 reserved_at_40[0x40]; 10653 }; 10654 10655 struct mlx5_ifc_set_flow_table_root_in_bits { 10656 u8 opcode[0x10]; 10657 u8 reserved_at_10[0x10]; 10658 10659 u8 reserved_at_20[0x10]; 10660 u8 op_mod[0x10]; 10661 10662 u8 other_vport[0x1]; 10663 u8 reserved_at_41[0xf]; 10664 u8 vport_number[0x10]; 10665 10666 u8 reserved_at_60[0x20]; 10667 10668 u8 table_type[0x8]; 10669 u8 reserved_at_88[0x7]; 10670 u8 table_of_other_vport[0x1]; 10671 u8 table_vport_number[0x10]; 10672 10673 u8 reserved_at_a0[0x8]; 10674 u8 table_id[0x18]; 10675 10676 u8 reserved_at_c0[0x8]; 10677 u8 underlay_qpn[0x18]; 10678 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10679 u8 reserved_at_e1[0xf]; 10680 u8 table_eswitch_owner_vhca_id[0x10]; 10681 u8 reserved_at_100[0x100]; 10682 }; 10683 10684 enum { 10685 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10686 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10687 }; 10688 10689 struct mlx5_ifc_modify_flow_table_out_bits { 10690 u8 status[0x8]; 10691 u8 reserved_at_8[0x18]; 10692 10693 u8 syndrome[0x20]; 10694 10695 u8 reserved_at_40[0x40]; 10696 }; 10697 10698 struct mlx5_ifc_modify_flow_table_in_bits { 10699 u8 opcode[0x10]; 10700 u8 reserved_at_10[0x10]; 10701 10702 u8 reserved_at_20[0x10]; 10703 u8 op_mod[0x10]; 10704 10705 u8 other_vport[0x1]; 10706 u8 reserved_at_41[0xf]; 10707 u8 vport_number[0x10]; 10708 10709 u8 reserved_at_60[0x10]; 10710 u8 modify_field_select[0x10]; 10711 10712 u8 table_type[0x8]; 10713 u8 reserved_at_88[0x18]; 10714 10715 u8 reserved_at_a0[0x8]; 10716 u8 table_id[0x18]; 10717 10718 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10719 }; 10720 10721 struct mlx5_ifc_ets_tcn_config_reg_bits { 10722 u8 g[0x1]; 10723 u8 b[0x1]; 10724 u8 r[0x1]; 10725 u8 reserved_at_3[0x9]; 10726 u8 group[0x4]; 10727 u8 reserved_at_10[0x9]; 10728 u8 bw_allocation[0x7]; 10729 10730 u8 reserved_at_20[0xc]; 10731 u8 max_bw_units[0x4]; 10732 u8 reserved_at_30[0x8]; 10733 u8 max_bw_value[0x8]; 10734 }; 10735 10736 struct mlx5_ifc_ets_global_config_reg_bits { 10737 u8 reserved_at_0[0x2]; 10738 u8 r[0x1]; 10739 u8 reserved_at_3[0x1d]; 10740 10741 u8 reserved_at_20[0xc]; 10742 u8 max_bw_units[0x4]; 10743 u8 reserved_at_30[0x8]; 10744 u8 max_bw_value[0x8]; 10745 }; 10746 10747 struct mlx5_ifc_qetc_reg_bits { 10748 u8 reserved_at_0[0x8]; 10749 u8 port_number[0x8]; 10750 u8 reserved_at_10[0x30]; 10751 10752 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10753 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10754 }; 10755 10756 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10757 u8 e[0x1]; 10758 u8 reserved_at_01[0x0b]; 10759 u8 prio[0x04]; 10760 }; 10761 10762 struct mlx5_ifc_qpdpm_reg_bits { 10763 u8 reserved_at_0[0x8]; 10764 u8 local_port[0x8]; 10765 u8 reserved_at_10[0x10]; 10766 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10767 }; 10768 10769 struct mlx5_ifc_qpts_reg_bits { 10770 u8 reserved_at_0[0x8]; 10771 u8 local_port[0x8]; 10772 u8 reserved_at_10[0x2d]; 10773 u8 trust_state[0x3]; 10774 }; 10775 10776 struct mlx5_ifc_pptb_reg_bits { 10777 u8 reserved_at_0[0x2]; 10778 u8 mm[0x2]; 10779 u8 reserved_at_4[0x4]; 10780 u8 local_port[0x8]; 10781 u8 reserved_at_10[0x6]; 10782 u8 cm[0x1]; 10783 u8 um[0x1]; 10784 u8 pm[0x8]; 10785 10786 u8 prio_x_buff[0x20]; 10787 10788 u8 pm_msb[0x8]; 10789 u8 reserved_at_48[0x10]; 10790 u8 ctrl_buff[0x4]; 10791 u8 untagged_buff[0x4]; 10792 }; 10793 10794 struct mlx5_ifc_sbcam_reg_bits { 10795 u8 reserved_at_0[0x8]; 10796 u8 feature_group[0x8]; 10797 u8 reserved_at_10[0x8]; 10798 u8 access_reg_group[0x8]; 10799 10800 u8 reserved_at_20[0x20]; 10801 10802 u8 sb_access_reg_cap_mask[4][0x20]; 10803 10804 u8 reserved_at_c0[0x80]; 10805 10806 u8 sb_feature_cap_mask[4][0x20]; 10807 10808 u8 reserved_at_1c0[0x40]; 10809 10810 u8 cap_total_buffer_size[0x20]; 10811 10812 u8 cap_cell_size[0x10]; 10813 u8 cap_max_pg_buffers[0x8]; 10814 u8 cap_num_pool_supported[0x8]; 10815 10816 u8 reserved_at_240[0x8]; 10817 u8 cap_sbsr_stat_size[0x8]; 10818 u8 cap_max_tclass_data[0x8]; 10819 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10820 }; 10821 10822 struct mlx5_ifc_pbmc_reg_bits { 10823 u8 reserved_at_0[0x8]; 10824 u8 local_port[0x8]; 10825 u8 reserved_at_10[0x10]; 10826 10827 u8 xoff_timer_value[0x10]; 10828 u8 xoff_refresh[0x10]; 10829 10830 u8 reserved_at_40[0x9]; 10831 u8 fullness_threshold[0x7]; 10832 u8 port_buffer_size[0x10]; 10833 10834 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10835 10836 u8 reserved_at_2e0[0x80]; 10837 }; 10838 10839 struct mlx5_ifc_qtct_reg_bits { 10840 u8 reserved_at_0[0x8]; 10841 u8 port_number[0x8]; 10842 u8 reserved_at_10[0xd]; 10843 u8 prio[0x3]; 10844 10845 u8 reserved_at_20[0x1d]; 10846 u8 tclass[0x3]; 10847 }; 10848 10849 struct mlx5_ifc_mcia_reg_bits { 10850 u8 l[0x1]; 10851 u8 reserved_at_1[0x7]; 10852 u8 module[0x8]; 10853 u8 reserved_at_10[0x8]; 10854 u8 status[0x8]; 10855 10856 u8 i2c_device_address[0x8]; 10857 u8 page_number[0x8]; 10858 u8 device_address[0x10]; 10859 10860 u8 reserved_at_40[0x10]; 10861 u8 size[0x10]; 10862 10863 u8 reserved_at_60[0x20]; 10864 10865 u8 dword_0[0x20]; 10866 u8 dword_1[0x20]; 10867 u8 dword_2[0x20]; 10868 u8 dword_3[0x20]; 10869 u8 dword_4[0x20]; 10870 u8 dword_5[0x20]; 10871 u8 dword_6[0x20]; 10872 u8 dword_7[0x20]; 10873 u8 dword_8[0x20]; 10874 u8 dword_9[0x20]; 10875 u8 dword_10[0x20]; 10876 u8 dword_11[0x20]; 10877 }; 10878 10879 struct mlx5_ifc_dcbx_param_bits { 10880 u8 dcbx_cee_cap[0x1]; 10881 u8 dcbx_ieee_cap[0x1]; 10882 u8 dcbx_standby_cap[0x1]; 10883 u8 reserved_at_3[0x5]; 10884 u8 port_number[0x8]; 10885 u8 reserved_at_10[0xa]; 10886 u8 max_application_table_size[6]; 10887 u8 reserved_at_20[0x15]; 10888 u8 version_oper[0x3]; 10889 u8 reserved_at_38[5]; 10890 u8 version_admin[0x3]; 10891 u8 willing_admin[0x1]; 10892 u8 reserved_at_41[0x3]; 10893 u8 pfc_cap_oper[0x4]; 10894 u8 reserved_at_48[0x4]; 10895 u8 pfc_cap_admin[0x4]; 10896 u8 reserved_at_50[0x4]; 10897 u8 num_of_tc_oper[0x4]; 10898 u8 reserved_at_58[0x4]; 10899 u8 num_of_tc_admin[0x4]; 10900 u8 remote_willing[0x1]; 10901 u8 reserved_at_61[3]; 10902 u8 remote_pfc_cap[4]; 10903 u8 reserved_at_68[0x14]; 10904 u8 remote_num_of_tc[0x4]; 10905 u8 reserved_at_80[0x18]; 10906 u8 error[0x8]; 10907 u8 reserved_at_a0[0x160]; 10908 }; 10909 10910 enum { 10911 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10912 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10913 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10914 }; 10915 10916 struct mlx5_ifc_lagc_bits { 10917 u8 fdb_selection_mode[0x1]; 10918 u8 reserved_at_1[0x14]; 10919 u8 port_select_mode[0x3]; 10920 u8 reserved_at_18[0x5]; 10921 u8 lag_state[0x3]; 10922 10923 u8 reserved_at_20[0x14]; 10924 u8 tx_remap_affinity_2[0x4]; 10925 u8 reserved_at_38[0x4]; 10926 u8 tx_remap_affinity_1[0x4]; 10927 }; 10928 10929 struct mlx5_ifc_create_lag_out_bits { 10930 u8 status[0x8]; 10931 u8 reserved_at_8[0x18]; 10932 10933 u8 syndrome[0x20]; 10934 10935 u8 reserved_at_40[0x40]; 10936 }; 10937 10938 struct mlx5_ifc_create_lag_in_bits { 10939 u8 opcode[0x10]; 10940 u8 reserved_at_10[0x10]; 10941 10942 u8 reserved_at_20[0x10]; 10943 u8 op_mod[0x10]; 10944 10945 struct mlx5_ifc_lagc_bits ctx; 10946 }; 10947 10948 struct mlx5_ifc_modify_lag_out_bits { 10949 u8 status[0x8]; 10950 u8 reserved_at_8[0x18]; 10951 10952 u8 syndrome[0x20]; 10953 10954 u8 reserved_at_40[0x40]; 10955 }; 10956 10957 struct mlx5_ifc_modify_lag_in_bits { 10958 u8 opcode[0x10]; 10959 u8 reserved_at_10[0x10]; 10960 10961 u8 reserved_at_20[0x10]; 10962 u8 op_mod[0x10]; 10963 10964 u8 reserved_at_40[0x20]; 10965 u8 field_select[0x20]; 10966 10967 struct mlx5_ifc_lagc_bits ctx; 10968 }; 10969 10970 struct mlx5_ifc_query_lag_out_bits { 10971 u8 status[0x8]; 10972 u8 reserved_at_8[0x18]; 10973 10974 u8 syndrome[0x20]; 10975 10976 struct mlx5_ifc_lagc_bits ctx; 10977 }; 10978 10979 struct mlx5_ifc_query_lag_in_bits { 10980 u8 opcode[0x10]; 10981 u8 reserved_at_10[0x10]; 10982 10983 u8 reserved_at_20[0x10]; 10984 u8 op_mod[0x10]; 10985 10986 u8 reserved_at_40[0x40]; 10987 }; 10988 10989 struct mlx5_ifc_destroy_lag_out_bits { 10990 u8 status[0x8]; 10991 u8 reserved_at_8[0x18]; 10992 10993 u8 syndrome[0x20]; 10994 10995 u8 reserved_at_40[0x40]; 10996 }; 10997 10998 struct mlx5_ifc_destroy_lag_in_bits { 10999 u8 opcode[0x10]; 11000 u8 reserved_at_10[0x10]; 11001 11002 u8 reserved_at_20[0x10]; 11003 u8 op_mod[0x10]; 11004 11005 u8 reserved_at_40[0x40]; 11006 }; 11007 11008 struct mlx5_ifc_create_vport_lag_out_bits { 11009 u8 status[0x8]; 11010 u8 reserved_at_8[0x18]; 11011 11012 u8 syndrome[0x20]; 11013 11014 u8 reserved_at_40[0x40]; 11015 }; 11016 11017 struct mlx5_ifc_create_vport_lag_in_bits { 11018 u8 opcode[0x10]; 11019 u8 reserved_at_10[0x10]; 11020 11021 u8 reserved_at_20[0x10]; 11022 u8 op_mod[0x10]; 11023 11024 u8 reserved_at_40[0x40]; 11025 }; 11026 11027 struct mlx5_ifc_destroy_vport_lag_out_bits { 11028 u8 status[0x8]; 11029 u8 reserved_at_8[0x18]; 11030 11031 u8 syndrome[0x20]; 11032 11033 u8 reserved_at_40[0x40]; 11034 }; 11035 11036 struct mlx5_ifc_destroy_vport_lag_in_bits { 11037 u8 opcode[0x10]; 11038 u8 reserved_at_10[0x10]; 11039 11040 u8 reserved_at_20[0x10]; 11041 u8 op_mod[0x10]; 11042 11043 u8 reserved_at_40[0x40]; 11044 }; 11045 11046 enum { 11047 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11048 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11049 }; 11050 11051 struct mlx5_ifc_modify_memic_in_bits { 11052 u8 opcode[0x10]; 11053 u8 uid[0x10]; 11054 11055 u8 reserved_at_20[0x10]; 11056 u8 op_mod[0x10]; 11057 11058 u8 reserved_at_40[0x20]; 11059 11060 u8 reserved_at_60[0x18]; 11061 u8 memic_operation_type[0x8]; 11062 11063 u8 memic_start_addr[0x40]; 11064 11065 u8 reserved_at_c0[0x140]; 11066 }; 11067 11068 struct mlx5_ifc_modify_memic_out_bits { 11069 u8 status[0x8]; 11070 u8 reserved_at_8[0x18]; 11071 11072 u8 syndrome[0x20]; 11073 11074 u8 reserved_at_40[0x40]; 11075 11076 u8 memic_operation_addr[0x40]; 11077 11078 u8 reserved_at_c0[0x140]; 11079 }; 11080 11081 struct mlx5_ifc_alloc_memic_in_bits { 11082 u8 opcode[0x10]; 11083 u8 reserved_at_10[0x10]; 11084 11085 u8 reserved_at_20[0x10]; 11086 u8 op_mod[0x10]; 11087 11088 u8 reserved_at_30[0x20]; 11089 11090 u8 reserved_at_40[0x18]; 11091 u8 log_memic_addr_alignment[0x8]; 11092 11093 u8 range_start_addr[0x40]; 11094 11095 u8 range_size[0x20]; 11096 11097 u8 memic_size[0x20]; 11098 }; 11099 11100 struct mlx5_ifc_alloc_memic_out_bits { 11101 u8 status[0x8]; 11102 u8 reserved_at_8[0x18]; 11103 11104 u8 syndrome[0x20]; 11105 11106 u8 memic_start_addr[0x40]; 11107 }; 11108 11109 struct mlx5_ifc_dealloc_memic_in_bits { 11110 u8 opcode[0x10]; 11111 u8 reserved_at_10[0x10]; 11112 11113 u8 reserved_at_20[0x10]; 11114 u8 op_mod[0x10]; 11115 11116 u8 reserved_at_40[0x40]; 11117 11118 u8 memic_start_addr[0x40]; 11119 11120 u8 memic_size[0x20]; 11121 11122 u8 reserved_at_e0[0x20]; 11123 }; 11124 11125 struct mlx5_ifc_dealloc_memic_out_bits { 11126 u8 status[0x8]; 11127 u8 reserved_at_8[0x18]; 11128 11129 u8 syndrome[0x20]; 11130 11131 u8 reserved_at_40[0x40]; 11132 }; 11133 11134 struct mlx5_ifc_umem_bits { 11135 u8 reserved_at_0[0x80]; 11136 11137 u8 reserved_at_80[0x1b]; 11138 u8 log_page_size[0x5]; 11139 11140 u8 page_offset[0x20]; 11141 11142 u8 num_of_mtt[0x40]; 11143 11144 struct mlx5_ifc_mtt_bits mtt[]; 11145 }; 11146 11147 struct mlx5_ifc_uctx_bits { 11148 u8 cap[0x20]; 11149 11150 u8 reserved_at_20[0x160]; 11151 }; 11152 11153 struct mlx5_ifc_sw_icm_bits { 11154 u8 modify_field_select[0x40]; 11155 11156 u8 reserved_at_40[0x18]; 11157 u8 log_sw_icm_size[0x8]; 11158 11159 u8 reserved_at_60[0x20]; 11160 11161 u8 sw_icm_start_addr[0x40]; 11162 11163 u8 reserved_at_c0[0x140]; 11164 }; 11165 11166 struct mlx5_ifc_geneve_tlv_option_bits { 11167 u8 modify_field_select[0x40]; 11168 11169 u8 reserved_at_40[0x18]; 11170 u8 geneve_option_fte_index[0x8]; 11171 11172 u8 option_class[0x10]; 11173 u8 option_type[0x8]; 11174 u8 reserved_at_78[0x3]; 11175 u8 option_data_length[0x5]; 11176 11177 u8 reserved_at_80[0x180]; 11178 }; 11179 11180 struct mlx5_ifc_create_umem_in_bits { 11181 u8 opcode[0x10]; 11182 u8 uid[0x10]; 11183 11184 u8 reserved_at_20[0x10]; 11185 u8 op_mod[0x10]; 11186 11187 u8 reserved_at_40[0x40]; 11188 11189 struct mlx5_ifc_umem_bits umem; 11190 }; 11191 11192 struct mlx5_ifc_create_umem_out_bits { 11193 u8 status[0x8]; 11194 u8 reserved_at_8[0x18]; 11195 11196 u8 syndrome[0x20]; 11197 11198 u8 reserved_at_40[0x8]; 11199 u8 umem_id[0x18]; 11200 11201 u8 reserved_at_60[0x20]; 11202 }; 11203 11204 struct mlx5_ifc_destroy_umem_in_bits { 11205 u8 opcode[0x10]; 11206 u8 uid[0x10]; 11207 11208 u8 reserved_at_20[0x10]; 11209 u8 op_mod[0x10]; 11210 11211 u8 reserved_at_40[0x8]; 11212 u8 umem_id[0x18]; 11213 11214 u8 reserved_at_60[0x20]; 11215 }; 11216 11217 struct mlx5_ifc_destroy_umem_out_bits { 11218 u8 status[0x8]; 11219 u8 reserved_at_8[0x18]; 11220 11221 u8 syndrome[0x20]; 11222 11223 u8 reserved_at_40[0x40]; 11224 }; 11225 11226 struct mlx5_ifc_create_uctx_in_bits { 11227 u8 opcode[0x10]; 11228 u8 reserved_at_10[0x10]; 11229 11230 u8 reserved_at_20[0x10]; 11231 u8 op_mod[0x10]; 11232 11233 u8 reserved_at_40[0x40]; 11234 11235 struct mlx5_ifc_uctx_bits uctx; 11236 }; 11237 11238 struct mlx5_ifc_create_uctx_out_bits { 11239 u8 status[0x8]; 11240 u8 reserved_at_8[0x18]; 11241 11242 u8 syndrome[0x20]; 11243 11244 u8 reserved_at_40[0x10]; 11245 u8 uid[0x10]; 11246 11247 u8 reserved_at_60[0x20]; 11248 }; 11249 11250 struct mlx5_ifc_destroy_uctx_in_bits { 11251 u8 opcode[0x10]; 11252 u8 reserved_at_10[0x10]; 11253 11254 u8 reserved_at_20[0x10]; 11255 u8 op_mod[0x10]; 11256 11257 u8 reserved_at_40[0x10]; 11258 u8 uid[0x10]; 11259 11260 u8 reserved_at_60[0x20]; 11261 }; 11262 11263 struct mlx5_ifc_destroy_uctx_out_bits { 11264 u8 status[0x8]; 11265 u8 reserved_at_8[0x18]; 11266 11267 u8 syndrome[0x20]; 11268 11269 u8 reserved_at_40[0x40]; 11270 }; 11271 11272 struct mlx5_ifc_create_sw_icm_in_bits { 11273 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11274 struct mlx5_ifc_sw_icm_bits sw_icm; 11275 }; 11276 11277 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11278 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11279 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11280 }; 11281 11282 struct mlx5_ifc_mtrc_string_db_param_bits { 11283 u8 string_db_base_address[0x20]; 11284 11285 u8 reserved_at_20[0x8]; 11286 u8 string_db_size[0x18]; 11287 }; 11288 11289 struct mlx5_ifc_mtrc_cap_bits { 11290 u8 trace_owner[0x1]; 11291 u8 trace_to_memory[0x1]; 11292 u8 reserved_at_2[0x4]; 11293 u8 trc_ver[0x2]; 11294 u8 reserved_at_8[0x14]; 11295 u8 num_string_db[0x4]; 11296 11297 u8 first_string_trace[0x8]; 11298 u8 num_string_trace[0x8]; 11299 u8 reserved_at_30[0x28]; 11300 11301 u8 log_max_trace_buffer_size[0x8]; 11302 11303 u8 reserved_at_60[0x20]; 11304 11305 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11306 11307 u8 reserved_at_280[0x180]; 11308 }; 11309 11310 struct mlx5_ifc_mtrc_conf_bits { 11311 u8 reserved_at_0[0x1c]; 11312 u8 trace_mode[0x4]; 11313 u8 reserved_at_20[0x18]; 11314 u8 log_trace_buffer_size[0x8]; 11315 u8 trace_mkey[0x20]; 11316 u8 reserved_at_60[0x3a0]; 11317 }; 11318 11319 struct mlx5_ifc_mtrc_stdb_bits { 11320 u8 string_db_index[0x4]; 11321 u8 reserved_at_4[0x4]; 11322 u8 read_size[0x18]; 11323 u8 start_offset[0x20]; 11324 u8 string_db_data[]; 11325 }; 11326 11327 struct mlx5_ifc_mtrc_ctrl_bits { 11328 u8 trace_status[0x2]; 11329 u8 reserved_at_2[0x2]; 11330 u8 arm_event[0x1]; 11331 u8 reserved_at_5[0xb]; 11332 u8 modify_field_select[0x10]; 11333 u8 reserved_at_20[0x2b]; 11334 u8 current_timestamp52_32[0x15]; 11335 u8 current_timestamp31_0[0x20]; 11336 u8 reserved_at_80[0x180]; 11337 }; 11338 11339 struct mlx5_ifc_host_params_context_bits { 11340 u8 host_number[0x8]; 11341 u8 reserved_at_8[0x7]; 11342 u8 host_pf_disabled[0x1]; 11343 u8 host_num_of_vfs[0x10]; 11344 11345 u8 host_total_vfs[0x10]; 11346 u8 host_pci_bus[0x10]; 11347 11348 u8 reserved_at_40[0x10]; 11349 u8 host_pci_device[0x10]; 11350 11351 u8 reserved_at_60[0x10]; 11352 u8 host_pci_function[0x10]; 11353 11354 u8 reserved_at_80[0x180]; 11355 }; 11356 11357 struct mlx5_ifc_query_esw_functions_in_bits { 11358 u8 opcode[0x10]; 11359 u8 reserved_at_10[0x10]; 11360 11361 u8 reserved_at_20[0x10]; 11362 u8 op_mod[0x10]; 11363 11364 u8 reserved_at_40[0x40]; 11365 }; 11366 11367 struct mlx5_ifc_query_esw_functions_out_bits { 11368 u8 status[0x8]; 11369 u8 reserved_at_8[0x18]; 11370 11371 u8 syndrome[0x20]; 11372 11373 u8 reserved_at_40[0x40]; 11374 11375 struct mlx5_ifc_host_params_context_bits host_params_context; 11376 11377 u8 reserved_at_280[0x180]; 11378 u8 host_sf_enable[][0x40]; 11379 }; 11380 11381 struct mlx5_ifc_sf_partition_bits { 11382 u8 reserved_at_0[0x10]; 11383 u8 log_num_sf[0x8]; 11384 u8 log_sf_bar_size[0x8]; 11385 }; 11386 11387 struct mlx5_ifc_query_sf_partitions_out_bits { 11388 u8 status[0x8]; 11389 u8 reserved_at_8[0x18]; 11390 11391 u8 syndrome[0x20]; 11392 11393 u8 reserved_at_40[0x18]; 11394 u8 num_sf_partitions[0x8]; 11395 11396 u8 reserved_at_60[0x20]; 11397 11398 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11399 }; 11400 11401 struct mlx5_ifc_query_sf_partitions_in_bits { 11402 u8 opcode[0x10]; 11403 u8 reserved_at_10[0x10]; 11404 11405 u8 reserved_at_20[0x10]; 11406 u8 op_mod[0x10]; 11407 11408 u8 reserved_at_40[0x40]; 11409 }; 11410 11411 struct mlx5_ifc_dealloc_sf_out_bits { 11412 u8 status[0x8]; 11413 u8 reserved_at_8[0x18]; 11414 11415 u8 syndrome[0x20]; 11416 11417 u8 reserved_at_40[0x40]; 11418 }; 11419 11420 struct mlx5_ifc_dealloc_sf_in_bits { 11421 u8 opcode[0x10]; 11422 u8 reserved_at_10[0x10]; 11423 11424 u8 reserved_at_20[0x10]; 11425 u8 op_mod[0x10]; 11426 11427 u8 reserved_at_40[0x10]; 11428 u8 function_id[0x10]; 11429 11430 u8 reserved_at_60[0x20]; 11431 }; 11432 11433 struct mlx5_ifc_alloc_sf_out_bits { 11434 u8 status[0x8]; 11435 u8 reserved_at_8[0x18]; 11436 11437 u8 syndrome[0x20]; 11438 11439 u8 reserved_at_40[0x40]; 11440 }; 11441 11442 struct mlx5_ifc_alloc_sf_in_bits { 11443 u8 opcode[0x10]; 11444 u8 reserved_at_10[0x10]; 11445 11446 u8 reserved_at_20[0x10]; 11447 u8 op_mod[0x10]; 11448 11449 u8 reserved_at_40[0x10]; 11450 u8 function_id[0x10]; 11451 11452 u8 reserved_at_60[0x20]; 11453 }; 11454 11455 struct mlx5_ifc_affiliated_event_header_bits { 11456 u8 reserved_at_0[0x10]; 11457 u8 obj_type[0x10]; 11458 11459 u8 obj_id[0x20]; 11460 }; 11461 11462 enum { 11463 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11464 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11465 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11466 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11467 }; 11468 11469 enum { 11470 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11471 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11472 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11473 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11474 }; 11475 11476 enum { 11477 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11478 }; 11479 11480 struct mlx5_ifc_ipsec_obj_bits { 11481 u8 modify_field_select[0x40]; 11482 u8 full_offload[0x1]; 11483 u8 reserved_at_41[0x1]; 11484 u8 esn_en[0x1]; 11485 u8 esn_overlap[0x1]; 11486 u8 reserved_at_44[0x2]; 11487 u8 icv_length[0x2]; 11488 u8 reserved_at_48[0x4]; 11489 u8 aso_return_reg[0x4]; 11490 u8 reserved_at_50[0x10]; 11491 11492 u8 esn_msb[0x20]; 11493 11494 u8 reserved_at_80[0x8]; 11495 u8 dekn[0x18]; 11496 11497 u8 salt[0x20]; 11498 11499 u8 implicit_iv[0x40]; 11500 11501 u8 reserved_at_100[0x700]; 11502 }; 11503 11504 struct mlx5_ifc_create_ipsec_obj_in_bits { 11505 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11506 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11507 }; 11508 11509 enum { 11510 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11511 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11512 }; 11513 11514 struct mlx5_ifc_query_ipsec_obj_out_bits { 11515 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11516 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11517 }; 11518 11519 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11520 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11521 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11522 }; 11523 11524 struct mlx5_ifc_encryption_key_obj_bits { 11525 u8 modify_field_select[0x40]; 11526 11527 u8 reserved_at_40[0x14]; 11528 u8 key_size[0x4]; 11529 u8 reserved_at_58[0x4]; 11530 u8 key_type[0x4]; 11531 11532 u8 reserved_at_60[0x8]; 11533 u8 pd[0x18]; 11534 11535 u8 reserved_at_80[0x180]; 11536 u8 key[8][0x20]; 11537 11538 u8 reserved_at_300[0x500]; 11539 }; 11540 11541 struct mlx5_ifc_create_encryption_key_in_bits { 11542 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11543 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11544 }; 11545 11546 enum { 11547 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11548 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11549 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11550 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11551 }; 11552 11553 struct mlx5_ifc_flow_meter_parameters_bits { 11554 u8 valid[0x1]; 11555 u8 bucket_overflow[0x1]; 11556 u8 start_color[0x2]; 11557 u8 both_buckets_on_green[0x1]; 11558 u8 reserved_at_5[0x1]; 11559 u8 meter_mode[0x2]; 11560 u8 reserved_at_8[0x18]; 11561 11562 u8 reserved_at_20[0x20]; 11563 11564 u8 reserved_at_40[0x3]; 11565 u8 cbs_exponent[0x5]; 11566 u8 cbs_mantissa[0x8]; 11567 u8 reserved_at_50[0x3]; 11568 u8 cir_exponent[0x5]; 11569 u8 cir_mantissa[0x8]; 11570 11571 u8 reserved_at_60[0x20]; 11572 11573 u8 reserved_at_80[0x3]; 11574 u8 ebs_exponent[0x5]; 11575 u8 ebs_mantissa[0x8]; 11576 u8 reserved_at_90[0x3]; 11577 u8 eir_exponent[0x5]; 11578 u8 eir_mantissa[0x8]; 11579 11580 u8 reserved_at_a0[0x60]; 11581 }; 11582 11583 struct mlx5_ifc_flow_meter_aso_obj_bits { 11584 u8 modify_field_select[0x40]; 11585 11586 u8 reserved_at_40[0x40]; 11587 11588 u8 reserved_at_80[0x8]; 11589 u8 meter_aso_access_pd[0x18]; 11590 11591 u8 reserved_at_a0[0x160]; 11592 11593 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11594 }; 11595 11596 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11597 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11598 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11599 }; 11600 11601 struct mlx5_ifc_sampler_obj_bits { 11602 u8 modify_field_select[0x40]; 11603 11604 u8 table_type[0x8]; 11605 u8 level[0x8]; 11606 u8 reserved_at_50[0xf]; 11607 u8 ignore_flow_level[0x1]; 11608 11609 u8 sample_ratio[0x20]; 11610 11611 u8 reserved_at_80[0x8]; 11612 u8 sample_table_id[0x18]; 11613 11614 u8 reserved_at_a0[0x8]; 11615 u8 default_table_id[0x18]; 11616 11617 u8 sw_steering_icm_address_rx[0x40]; 11618 u8 sw_steering_icm_address_tx[0x40]; 11619 11620 u8 reserved_at_140[0xa0]; 11621 }; 11622 11623 struct mlx5_ifc_create_sampler_obj_in_bits { 11624 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11625 struct mlx5_ifc_sampler_obj_bits sampler_object; 11626 }; 11627 11628 struct mlx5_ifc_query_sampler_obj_out_bits { 11629 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11630 struct mlx5_ifc_sampler_obj_bits sampler_object; 11631 }; 11632 11633 enum { 11634 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11635 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11636 }; 11637 11638 enum { 11639 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11640 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11641 }; 11642 11643 struct mlx5_ifc_tls_static_params_bits { 11644 u8 const_2[0x2]; 11645 u8 tls_version[0x4]; 11646 u8 const_1[0x2]; 11647 u8 reserved_at_8[0x14]; 11648 u8 encryption_standard[0x4]; 11649 11650 u8 reserved_at_20[0x20]; 11651 11652 u8 initial_record_number[0x40]; 11653 11654 u8 resync_tcp_sn[0x20]; 11655 11656 u8 gcm_iv[0x20]; 11657 11658 u8 implicit_iv[0x40]; 11659 11660 u8 reserved_at_100[0x8]; 11661 u8 dek_index[0x18]; 11662 11663 u8 reserved_at_120[0xe0]; 11664 }; 11665 11666 struct mlx5_ifc_tls_progress_params_bits { 11667 u8 next_record_tcp_sn[0x20]; 11668 11669 u8 hw_resync_tcp_sn[0x20]; 11670 11671 u8 record_tracker_state[0x2]; 11672 u8 auth_state[0x2]; 11673 u8 reserved_at_44[0x4]; 11674 u8 hw_offset_record_number[0x18]; 11675 }; 11676 11677 enum { 11678 MLX5_MTT_PERM_READ = 1 << 0, 11679 MLX5_MTT_PERM_WRITE = 1 << 1, 11680 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11681 }; 11682 11683 enum { 11684 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11685 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11686 }; 11687 11688 struct mlx5_ifc_suspend_vhca_in_bits { 11689 u8 opcode[0x10]; 11690 u8 uid[0x10]; 11691 11692 u8 reserved_at_20[0x10]; 11693 u8 op_mod[0x10]; 11694 11695 u8 reserved_at_40[0x10]; 11696 u8 vhca_id[0x10]; 11697 11698 u8 reserved_at_60[0x20]; 11699 }; 11700 11701 struct mlx5_ifc_suspend_vhca_out_bits { 11702 u8 status[0x8]; 11703 u8 reserved_at_8[0x18]; 11704 11705 u8 syndrome[0x20]; 11706 11707 u8 reserved_at_40[0x40]; 11708 }; 11709 11710 enum { 11711 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11712 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11713 }; 11714 11715 struct mlx5_ifc_resume_vhca_in_bits { 11716 u8 opcode[0x10]; 11717 u8 uid[0x10]; 11718 11719 u8 reserved_at_20[0x10]; 11720 u8 op_mod[0x10]; 11721 11722 u8 reserved_at_40[0x10]; 11723 u8 vhca_id[0x10]; 11724 11725 u8 reserved_at_60[0x20]; 11726 }; 11727 11728 struct mlx5_ifc_resume_vhca_out_bits { 11729 u8 status[0x8]; 11730 u8 reserved_at_8[0x18]; 11731 11732 u8 syndrome[0x20]; 11733 11734 u8 reserved_at_40[0x40]; 11735 }; 11736 11737 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11738 u8 opcode[0x10]; 11739 u8 uid[0x10]; 11740 11741 u8 reserved_at_20[0x10]; 11742 u8 op_mod[0x10]; 11743 11744 u8 reserved_at_40[0x10]; 11745 u8 vhca_id[0x10]; 11746 11747 u8 reserved_at_60[0x20]; 11748 }; 11749 11750 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11751 u8 status[0x8]; 11752 u8 reserved_at_8[0x18]; 11753 11754 u8 syndrome[0x20]; 11755 11756 u8 reserved_at_40[0x40]; 11757 11758 u8 required_umem_size[0x20]; 11759 11760 u8 reserved_at_a0[0x160]; 11761 }; 11762 11763 struct mlx5_ifc_save_vhca_state_in_bits { 11764 u8 opcode[0x10]; 11765 u8 uid[0x10]; 11766 11767 u8 reserved_at_20[0x10]; 11768 u8 op_mod[0x10]; 11769 11770 u8 reserved_at_40[0x10]; 11771 u8 vhca_id[0x10]; 11772 11773 u8 reserved_at_60[0x20]; 11774 11775 u8 va[0x40]; 11776 11777 u8 mkey[0x20]; 11778 11779 u8 size[0x20]; 11780 }; 11781 11782 struct mlx5_ifc_save_vhca_state_out_bits { 11783 u8 status[0x8]; 11784 u8 reserved_at_8[0x18]; 11785 11786 u8 syndrome[0x20]; 11787 11788 u8 actual_image_size[0x20]; 11789 11790 u8 reserved_at_60[0x20]; 11791 }; 11792 11793 struct mlx5_ifc_load_vhca_state_in_bits { 11794 u8 opcode[0x10]; 11795 u8 uid[0x10]; 11796 11797 u8 reserved_at_20[0x10]; 11798 u8 op_mod[0x10]; 11799 11800 u8 reserved_at_40[0x10]; 11801 u8 vhca_id[0x10]; 11802 11803 u8 reserved_at_60[0x20]; 11804 11805 u8 va[0x40]; 11806 11807 u8 mkey[0x20]; 11808 11809 u8 size[0x20]; 11810 }; 11811 11812 struct mlx5_ifc_load_vhca_state_out_bits { 11813 u8 status[0x8]; 11814 u8 reserved_at_8[0x18]; 11815 11816 u8 syndrome[0x20]; 11817 11818 u8 reserved_at_40[0x40]; 11819 }; 11820 11821 #endif /* MLX5_IFC_H */ 11822