1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 304 MLX5_CMD_OP_MAX 305 }; 306 307 /* Valid range for general commands that don't work over an object */ 308 enum { 309 MLX5_CMD_OP_GENERAL_START = 0xb00, 310 MLX5_CMD_OP_GENERAL_END = 0xd00, 311 }; 312 313 struct mlx5_ifc_flow_table_fields_supported_bits { 314 u8 outer_dmac[0x1]; 315 u8 outer_smac[0x1]; 316 u8 outer_ether_type[0x1]; 317 u8 outer_ip_version[0x1]; 318 u8 outer_first_prio[0x1]; 319 u8 outer_first_cfi[0x1]; 320 u8 outer_first_vid[0x1]; 321 u8 outer_ipv4_ttl[0x1]; 322 u8 outer_second_prio[0x1]; 323 u8 outer_second_cfi[0x1]; 324 u8 outer_second_vid[0x1]; 325 u8 reserved_at_b[0x1]; 326 u8 outer_sip[0x1]; 327 u8 outer_dip[0x1]; 328 u8 outer_frag[0x1]; 329 u8 outer_ip_protocol[0x1]; 330 u8 outer_ip_ecn[0x1]; 331 u8 outer_ip_dscp[0x1]; 332 u8 outer_udp_sport[0x1]; 333 u8 outer_udp_dport[0x1]; 334 u8 outer_tcp_sport[0x1]; 335 u8 outer_tcp_dport[0x1]; 336 u8 outer_tcp_flags[0x1]; 337 u8 outer_gre_protocol[0x1]; 338 u8 outer_gre_key[0x1]; 339 u8 outer_vxlan_vni[0x1]; 340 u8 outer_geneve_vni[0x1]; 341 u8 outer_geneve_oam[0x1]; 342 u8 outer_geneve_protocol_type[0x1]; 343 u8 outer_geneve_opt_len[0x1]; 344 u8 reserved_at_1e[0x1]; 345 u8 source_eswitch_port[0x1]; 346 347 u8 inner_dmac[0x1]; 348 u8 inner_smac[0x1]; 349 u8 inner_ether_type[0x1]; 350 u8 inner_ip_version[0x1]; 351 u8 inner_first_prio[0x1]; 352 u8 inner_first_cfi[0x1]; 353 u8 inner_first_vid[0x1]; 354 u8 reserved_at_27[0x1]; 355 u8 inner_second_prio[0x1]; 356 u8 inner_second_cfi[0x1]; 357 u8 inner_second_vid[0x1]; 358 u8 reserved_at_2b[0x1]; 359 u8 inner_sip[0x1]; 360 u8 inner_dip[0x1]; 361 u8 inner_frag[0x1]; 362 u8 inner_ip_protocol[0x1]; 363 u8 inner_ip_ecn[0x1]; 364 u8 inner_ip_dscp[0x1]; 365 u8 inner_udp_sport[0x1]; 366 u8 inner_udp_dport[0x1]; 367 u8 inner_tcp_sport[0x1]; 368 u8 inner_tcp_dport[0x1]; 369 u8 inner_tcp_flags[0x1]; 370 u8 reserved_at_37[0x9]; 371 372 u8 geneve_tlv_option_0_data[0x1]; 373 u8 reserved_at_41[0x4]; 374 u8 outer_first_mpls_over_udp[0x4]; 375 u8 outer_first_mpls_over_gre[0x4]; 376 u8 inner_first_mpls[0x4]; 377 u8 outer_first_mpls[0x4]; 378 u8 reserved_at_55[0x2]; 379 u8 outer_esp_spi[0x1]; 380 u8 reserved_at_58[0x2]; 381 u8 bth_dst_qp[0x1]; 382 u8 reserved_at_5b[0x5]; 383 384 u8 reserved_at_60[0x18]; 385 u8 metadata_reg_c_7[0x1]; 386 u8 metadata_reg_c_6[0x1]; 387 u8 metadata_reg_c_5[0x1]; 388 u8 metadata_reg_c_4[0x1]; 389 u8 metadata_reg_c_3[0x1]; 390 u8 metadata_reg_c_2[0x1]; 391 u8 metadata_reg_c_1[0x1]; 392 u8 metadata_reg_c_0[0x1]; 393 }; 394 395 struct mlx5_ifc_flow_table_prop_layout_bits { 396 u8 ft_support[0x1]; 397 u8 reserved_at_1[0x1]; 398 u8 flow_counter[0x1]; 399 u8 flow_modify_en[0x1]; 400 u8 modify_root[0x1]; 401 u8 identified_miss_table_mode[0x1]; 402 u8 flow_table_modify[0x1]; 403 u8 reformat[0x1]; 404 u8 decap[0x1]; 405 u8 reserved_at_9[0x1]; 406 u8 pop_vlan[0x1]; 407 u8 push_vlan[0x1]; 408 u8 reserved_at_c[0x1]; 409 u8 pop_vlan_2[0x1]; 410 u8 push_vlan_2[0x1]; 411 u8 reformat_and_vlan_action[0x1]; 412 u8 reserved_at_10[0x1]; 413 u8 sw_owner[0x1]; 414 u8 reformat_l3_tunnel_to_l2[0x1]; 415 u8 reformat_l2_to_l3_tunnel[0x1]; 416 u8 reformat_and_modify_action[0x1]; 417 u8 ignore_flow_level[0x1]; 418 u8 reserved_at_16[0x1]; 419 u8 table_miss_action_domain[0x1]; 420 u8 termination_table[0x1]; 421 u8 reformat_and_fwd_to_table[0x1]; 422 u8 reserved_at_1a[0x2]; 423 u8 ipsec_encrypt[0x1]; 424 u8 ipsec_decrypt[0x1]; 425 u8 sw_owner_v2[0x1]; 426 u8 reserved_at_1f[0x1]; 427 428 u8 termination_table_raw_traffic[0x1]; 429 u8 reserved_at_21[0x1]; 430 u8 log_max_ft_size[0x6]; 431 u8 log_max_modify_header_context[0x8]; 432 u8 max_modify_header_actions[0x8]; 433 u8 max_ft_level[0x8]; 434 435 u8 reserved_at_40[0x20]; 436 437 u8 reserved_at_60[0x18]; 438 u8 log_max_ft_num[0x8]; 439 440 u8 reserved_at_80[0x18]; 441 u8 log_max_destination[0x8]; 442 443 u8 log_max_flow_counter[0x8]; 444 u8 reserved_at_a8[0x10]; 445 u8 log_max_flow[0x8]; 446 447 u8 reserved_at_c0[0x40]; 448 449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 452 }; 453 454 struct mlx5_ifc_odp_per_transport_service_cap_bits { 455 u8 send[0x1]; 456 u8 receive[0x1]; 457 u8 write[0x1]; 458 u8 read[0x1]; 459 u8 atomic[0x1]; 460 u8 srq_receive[0x1]; 461 u8 reserved_at_6[0x1a]; 462 }; 463 464 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 465 u8 smac_47_16[0x20]; 466 467 u8 smac_15_0[0x10]; 468 u8 ethertype[0x10]; 469 470 u8 dmac_47_16[0x20]; 471 472 u8 dmac_15_0[0x10]; 473 u8 first_prio[0x3]; 474 u8 first_cfi[0x1]; 475 u8 first_vid[0xc]; 476 477 u8 ip_protocol[0x8]; 478 u8 ip_dscp[0x6]; 479 u8 ip_ecn[0x2]; 480 u8 cvlan_tag[0x1]; 481 u8 svlan_tag[0x1]; 482 u8 frag[0x1]; 483 u8 ip_version[0x4]; 484 u8 tcp_flags[0x9]; 485 486 u8 tcp_sport[0x10]; 487 u8 tcp_dport[0x10]; 488 489 u8 reserved_at_c0[0x18]; 490 u8 ttl_hoplimit[0x8]; 491 492 u8 udp_sport[0x10]; 493 u8 udp_dport[0x10]; 494 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 498 }; 499 500 struct mlx5_ifc_nvgre_key_bits { 501 u8 hi[0x18]; 502 u8 lo[0x8]; 503 }; 504 505 union mlx5_ifc_gre_key_bits { 506 struct mlx5_ifc_nvgre_key_bits nvgre; 507 u8 key[0x20]; 508 }; 509 510 struct mlx5_ifc_fte_match_set_misc_bits { 511 u8 gre_c_present[0x1]; 512 u8 reserved_at_1[0x1]; 513 u8 gre_k_present[0x1]; 514 u8 gre_s_present[0x1]; 515 u8 source_vhca_port[0x4]; 516 u8 source_sqn[0x18]; 517 518 u8 source_eswitch_owner_vhca_id[0x10]; 519 u8 source_port[0x10]; 520 521 u8 outer_second_prio[0x3]; 522 u8 outer_second_cfi[0x1]; 523 u8 outer_second_vid[0xc]; 524 u8 inner_second_prio[0x3]; 525 u8 inner_second_cfi[0x1]; 526 u8 inner_second_vid[0xc]; 527 528 u8 outer_second_cvlan_tag[0x1]; 529 u8 inner_second_cvlan_tag[0x1]; 530 u8 outer_second_svlan_tag[0x1]; 531 u8 inner_second_svlan_tag[0x1]; 532 u8 reserved_at_64[0xc]; 533 u8 gre_protocol[0x10]; 534 535 union mlx5_ifc_gre_key_bits gre_key; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_at_b8[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved_at_d8[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_at_e0[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_at_100[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_at_120[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_at_140[0x8]; 555 u8 bth_dst_qp[0x18]; 556 u8 reserved_at_160[0x20]; 557 u8 outer_esp_spi[0x20]; 558 u8 reserved_at_1a0[0x60]; 559 }; 560 561 struct mlx5_ifc_fte_match_mpls_bits { 562 u8 mpls_label[0x14]; 563 u8 mpls_exp[0x3]; 564 u8 mpls_s_bos[0x1]; 565 u8 mpls_ttl[0x8]; 566 }; 567 568 struct mlx5_ifc_fte_match_set_misc2_bits { 569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 570 571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 572 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 574 575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 576 577 u8 metadata_reg_c_7[0x20]; 578 579 u8 metadata_reg_c_6[0x20]; 580 581 u8 metadata_reg_c_5[0x20]; 582 583 u8 metadata_reg_c_4[0x20]; 584 585 u8 metadata_reg_c_3[0x20]; 586 587 u8 metadata_reg_c_2[0x20]; 588 589 u8 metadata_reg_c_1[0x20]; 590 591 u8 metadata_reg_c_0[0x20]; 592 593 u8 metadata_reg_a[0x20]; 594 595 u8 reserved_at_1a0[0x60]; 596 }; 597 598 struct mlx5_ifc_fte_match_set_misc3_bits { 599 u8 inner_tcp_seq_num[0x20]; 600 601 u8 outer_tcp_seq_num[0x20]; 602 603 u8 inner_tcp_ack_num[0x20]; 604 605 u8 outer_tcp_ack_num[0x20]; 606 607 u8 reserved_at_80[0x8]; 608 u8 outer_vxlan_gpe_vni[0x18]; 609 610 u8 outer_vxlan_gpe_next_protocol[0x8]; 611 u8 outer_vxlan_gpe_flags[0x8]; 612 u8 reserved_at_b0[0x10]; 613 614 u8 icmp_header_data[0x20]; 615 616 u8 icmpv6_header_data[0x20]; 617 618 u8 icmp_type[0x8]; 619 u8 icmp_code[0x8]; 620 u8 icmpv6_type[0x8]; 621 u8 icmpv6_code[0x8]; 622 623 u8 geneve_tlv_option_0_data[0x20]; 624 625 u8 reserved_at_140[0xc0]; 626 }; 627 628 struct mlx5_ifc_fte_match_set_misc4_bits { 629 u8 prog_sample_field_value_0[0x20]; 630 631 u8 prog_sample_field_id_0[0x20]; 632 633 u8 prog_sample_field_value_1[0x20]; 634 635 u8 prog_sample_field_id_1[0x20]; 636 637 u8 prog_sample_field_value_2[0x20]; 638 639 u8 prog_sample_field_id_2[0x20]; 640 641 u8 prog_sample_field_value_3[0x20]; 642 643 u8 prog_sample_field_id_3[0x20]; 644 645 u8 reserved_at_100[0x100]; 646 }; 647 648 struct mlx5_ifc_cmd_pas_bits { 649 u8 pa_h[0x20]; 650 651 u8 pa_l[0x14]; 652 u8 reserved_at_34[0xc]; 653 }; 654 655 struct mlx5_ifc_uint64_bits { 656 u8 hi[0x20]; 657 658 u8 lo[0x20]; 659 }; 660 661 enum { 662 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 663 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 664 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 665 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 666 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 667 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 668 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 669 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 670 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 671 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 672 }; 673 674 struct mlx5_ifc_ads_bits { 675 u8 fl[0x1]; 676 u8 free_ar[0x1]; 677 u8 reserved_at_2[0xe]; 678 u8 pkey_index[0x10]; 679 680 u8 reserved_at_20[0x8]; 681 u8 grh[0x1]; 682 u8 mlid[0x7]; 683 u8 rlid[0x10]; 684 685 u8 ack_timeout[0x5]; 686 u8 reserved_at_45[0x3]; 687 u8 src_addr_index[0x8]; 688 u8 reserved_at_50[0x4]; 689 u8 stat_rate[0x4]; 690 u8 hop_limit[0x8]; 691 692 u8 reserved_at_60[0x4]; 693 u8 tclass[0x8]; 694 u8 flow_label[0x14]; 695 696 u8 rgid_rip[16][0x8]; 697 698 u8 reserved_at_100[0x4]; 699 u8 f_dscp[0x1]; 700 u8 f_ecn[0x1]; 701 u8 reserved_at_106[0x1]; 702 u8 f_eth_prio[0x1]; 703 u8 ecn[0x2]; 704 u8 dscp[0x6]; 705 u8 udp_sport[0x10]; 706 707 u8 dei_cfi[0x1]; 708 u8 eth_prio[0x3]; 709 u8 sl[0x4]; 710 u8 vhca_port_num[0x8]; 711 u8 rmac_47_32[0x10]; 712 713 u8 rmac_31_0[0x20]; 714 }; 715 716 struct mlx5_ifc_flow_table_nic_cap_bits { 717 u8 nic_rx_multi_path_tirs[0x1]; 718 u8 nic_rx_multi_path_tirs_fts[0x1]; 719 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 720 u8 reserved_at_3[0x4]; 721 u8 sw_owner_reformat_supported[0x1]; 722 u8 reserved_at_8[0x18]; 723 724 u8 encap_general_header[0x1]; 725 u8 reserved_at_21[0xa]; 726 u8 log_max_packet_reformat_context[0x5]; 727 u8 reserved_at_30[0x6]; 728 u8 max_encap_header_size[0xa]; 729 u8 reserved_at_40[0x1c0]; 730 731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 732 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 734 735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 736 737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 738 739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 740 741 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 742 743 u8 reserved_at_e00[0x1200]; 744 745 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 746 747 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 748 749 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 750 751 u8 reserved_at_20c0[0x5f40]; 752 }; 753 754 enum { 755 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 756 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 757 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 758 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 759 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 760 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 761 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 762 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 763 }; 764 765 struct mlx5_ifc_flow_table_eswitch_cap_bits { 766 u8 fdb_to_vport_reg_c_id[0x8]; 767 u8 reserved_at_8[0xd]; 768 u8 fdb_modify_header_fwd_to_table[0x1]; 769 u8 reserved_at_16[0x1]; 770 u8 flow_source[0x1]; 771 u8 reserved_at_18[0x2]; 772 u8 multi_fdb_encap[0x1]; 773 u8 egress_acl_forward_to_vport[0x1]; 774 u8 fdb_multi_path_to_table[0x1]; 775 u8 reserved_at_1d[0x3]; 776 777 u8 reserved_at_20[0x1e0]; 778 779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 780 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 784 785 u8 reserved_at_800[0x1000]; 786 787 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 788 789 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 790 791 u8 sw_steering_uplink_icm_address_rx[0x40]; 792 793 u8 sw_steering_uplink_icm_address_tx[0x40]; 794 795 u8 reserved_at_1900[0x6700]; 796 }; 797 798 enum { 799 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 800 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 801 }; 802 803 struct mlx5_ifc_e_switch_cap_bits { 804 u8 vport_svlan_strip[0x1]; 805 u8 vport_cvlan_strip[0x1]; 806 u8 vport_svlan_insert[0x1]; 807 u8 vport_cvlan_insert_if_not_exist[0x1]; 808 u8 vport_cvlan_insert_overwrite[0x1]; 809 u8 reserved_at_5[0x3]; 810 u8 esw_uplink_ingress_acl[0x1]; 811 u8 reserved_at_9[0x10]; 812 u8 esw_functions_changed[0x1]; 813 u8 reserved_at_1a[0x1]; 814 u8 ecpf_vport_exists[0x1]; 815 u8 counter_eswitch_affinity[0x1]; 816 u8 merged_eswitch[0x1]; 817 u8 nic_vport_node_guid_modify[0x1]; 818 u8 nic_vport_port_guid_modify[0x1]; 819 820 u8 vxlan_encap_decap[0x1]; 821 u8 nvgre_encap_decap[0x1]; 822 u8 reserved_at_22[0x1]; 823 u8 log_max_fdb_encap_uplink[0x5]; 824 u8 reserved_at_21[0x3]; 825 u8 log_max_packet_reformat_context[0x5]; 826 u8 reserved_2b[0x6]; 827 u8 max_encap_header_size[0xa]; 828 829 u8 reserved_at_40[0xb]; 830 u8 log_max_esw_sf[0x5]; 831 u8 esw_sf_base_id[0x10]; 832 833 u8 reserved_at_60[0x7a0]; 834 835 }; 836 837 struct mlx5_ifc_qos_cap_bits { 838 u8 packet_pacing[0x1]; 839 u8 esw_scheduling[0x1]; 840 u8 esw_bw_share[0x1]; 841 u8 esw_rate_limit[0x1]; 842 u8 reserved_at_4[0x1]; 843 u8 packet_pacing_burst_bound[0x1]; 844 u8 packet_pacing_typical_size[0x1]; 845 u8 reserved_at_7[0x1]; 846 u8 nic_sq_scheduling[0x1]; 847 u8 nic_bw_share[0x1]; 848 u8 nic_rate_limit[0x1]; 849 u8 packet_pacing_uid[0x1]; 850 u8 reserved_at_c[0x14]; 851 852 u8 reserved_at_20[0xb]; 853 u8 log_max_qos_nic_queue_group[0x5]; 854 u8 reserved_at_30[0x10]; 855 856 u8 packet_pacing_max_rate[0x20]; 857 858 u8 packet_pacing_min_rate[0x20]; 859 860 u8 reserved_at_80[0x10]; 861 u8 packet_pacing_rate_table_size[0x10]; 862 863 u8 esw_element_type[0x10]; 864 u8 esw_tsar_type[0x10]; 865 866 u8 reserved_at_c0[0x10]; 867 u8 max_qos_para_vport[0x10]; 868 869 u8 max_tsar_bw_share[0x20]; 870 871 u8 reserved_at_100[0x700]; 872 }; 873 874 struct mlx5_ifc_debug_cap_bits { 875 u8 core_dump_general[0x1]; 876 u8 core_dump_qp[0x1]; 877 u8 reserved_at_2[0x7]; 878 u8 resource_dump[0x1]; 879 u8 reserved_at_a[0x16]; 880 881 u8 reserved_at_20[0x2]; 882 u8 stall_detect[0x1]; 883 u8 reserved_at_23[0x1d]; 884 885 u8 reserved_at_40[0x7c0]; 886 }; 887 888 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 889 u8 csum_cap[0x1]; 890 u8 vlan_cap[0x1]; 891 u8 lro_cap[0x1]; 892 u8 lro_psh_flag[0x1]; 893 u8 lro_time_stamp[0x1]; 894 u8 reserved_at_5[0x2]; 895 u8 wqe_vlan_insert[0x1]; 896 u8 self_lb_en_modifiable[0x1]; 897 u8 reserved_at_9[0x2]; 898 u8 max_lso_cap[0x5]; 899 u8 multi_pkt_send_wqe[0x2]; 900 u8 wqe_inline_mode[0x2]; 901 u8 rss_ind_tbl_cap[0x4]; 902 u8 reg_umr_sq[0x1]; 903 u8 scatter_fcs[0x1]; 904 u8 enhanced_multi_pkt_send_wqe[0x1]; 905 u8 tunnel_lso_const_out_ip_id[0x1]; 906 u8 reserved_at_1c[0x2]; 907 u8 tunnel_stateless_gre[0x1]; 908 u8 tunnel_stateless_vxlan[0x1]; 909 910 u8 swp[0x1]; 911 u8 swp_csum[0x1]; 912 u8 swp_lso[0x1]; 913 u8 cqe_checksum_full[0x1]; 914 u8 tunnel_stateless_geneve_tx[0x1]; 915 u8 tunnel_stateless_mpls_over_udp[0x1]; 916 u8 tunnel_stateless_mpls_over_gre[0x1]; 917 u8 tunnel_stateless_vxlan_gpe[0x1]; 918 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 919 u8 tunnel_stateless_ip_over_ip[0x1]; 920 u8 insert_trailer[0x1]; 921 u8 reserved_at_2b[0x1]; 922 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 923 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 924 u8 reserved_at_2e[0x2]; 925 u8 max_vxlan_udp_ports[0x8]; 926 u8 reserved_at_38[0x6]; 927 u8 max_geneve_opt_len[0x1]; 928 u8 tunnel_stateless_geneve_rx[0x1]; 929 930 u8 reserved_at_40[0x10]; 931 u8 lro_min_mss_size[0x10]; 932 933 u8 reserved_at_60[0x120]; 934 935 u8 lro_timer_supported_periods[4][0x20]; 936 937 u8 reserved_at_200[0x600]; 938 }; 939 940 enum { 941 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 942 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 943 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 944 }; 945 946 struct mlx5_ifc_roce_cap_bits { 947 u8 roce_apm[0x1]; 948 u8 reserved_at_1[0x3]; 949 u8 sw_r_roce_src_udp_port[0x1]; 950 u8 reserved_at_5[0x19]; 951 u8 qp_ts_format[0x2]; 952 953 u8 reserved_at_20[0x60]; 954 955 u8 reserved_at_80[0xc]; 956 u8 l3_type[0x4]; 957 u8 reserved_at_90[0x8]; 958 u8 roce_version[0x8]; 959 960 u8 reserved_at_a0[0x10]; 961 u8 r_roce_dest_udp_port[0x10]; 962 963 u8 r_roce_max_src_udp_port[0x10]; 964 u8 r_roce_min_src_udp_port[0x10]; 965 966 u8 reserved_at_e0[0x10]; 967 u8 roce_address_table_size[0x10]; 968 969 u8 reserved_at_100[0x700]; 970 }; 971 972 struct mlx5_ifc_sync_steering_in_bits { 973 u8 opcode[0x10]; 974 u8 uid[0x10]; 975 976 u8 reserved_at_20[0x10]; 977 u8 op_mod[0x10]; 978 979 u8 reserved_at_40[0xc0]; 980 }; 981 982 struct mlx5_ifc_sync_steering_out_bits { 983 u8 status[0x8]; 984 u8 reserved_at_8[0x18]; 985 986 u8 syndrome[0x20]; 987 988 u8 reserved_at_40[0x40]; 989 }; 990 991 struct mlx5_ifc_device_mem_cap_bits { 992 u8 memic[0x1]; 993 u8 reserved_at_1[0x1f]; 994 995 u8 reserved_at_20[0xb]; 996 u8 log_min_memic_alloc_size[0x5]; 997 u8 reserved_at_30[0x8]; 998 u8 log_max_memic_addr_alignment[0x8]; 999 1000 u8 memic_bar_start_addr[0x40]; 1001 1002 u8 memic_bar_size[0x20]; 1003 1004 u8 max_memic_size[0x20]; 1005 1006 u8 steering_sw_icm_start_address[0x40]; 1007 1008 u8 reserved_at_100[0x8]; 1009 u8 log_header_modify_sw_icm_size[0x8]; 1010 u8 reserved_at_110[0x2]; 1011 u8 log_sw_icm_alloc_granularity[0x6]; 1012 u8 log_steering_sw_icm_size[0x8]; 1013 1014 u8 reserved_at_120[0x20]; 1015 1016 u8 header_modify_sw_icm_start_address[0x40]; 1017 1018 u8 reserved_at_180[0x680]; 1019 }; 1020 1021 struct mlx5_ifc_device_event_cap_bits { 1022 u8 user_affiliated_events[4][0x40]; 1023 1024 u8 user_unaffiliated_events[4][0x40]; 1025 }; 1026 1027 struct mlx5_ifc_virtio_emulation_cap_bits { 1028 u8 desc_tunnel_offload_type[0x1]; 1029 u8 eth_frame_offload_type[0x1]; 1030 u8 virtio_version_1_0[0x1]; 1031 u8 device_features_bits_mask[0xd]; 1032 u8 event_mode[0x8]; 1033 u8 virtio_queue_type[0x8]; 1034 1035 u8 max_tunnel_desc[0x10]; 1036 u8 reserved_at_30[0x3]; 1037 u8 log_doorbell_stride[0x5]; 1038 u8 reserved_at_38[0x3]; 1039 u8 log_doorbell_bar_size[0x5]; 1040 1041 u8 doorbell_bar_offset[0x40]; 1042 1043 u8 max_emulated_devices[0x8]; 1044 u8 max_num_virtio_queues[0x18]; 1045 1046 u8 reserved_at_a0[0x60]; 1047 1048 u8 umem_1_buffer_param_a[0x20]; 1049 1050 u8 umem_1_buffer_param_b[0x20]; 1051 1052 u8 umem_2_buffer_param_a[0x20]; 1053 1054 u8 umem_2_buffer_param_b[0x20]; 1055 1056 u8 umem_3_buffer_param_a[0x20]; 1057 1058 u8 umem_3_buffer_param_b[0x20]; 1059 1060 u8 reserved_at_1c0[0x640]; 1061 }; 1062 1063 enum { 1064 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1065 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1066 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1067 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1068 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1069 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1070 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1071 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1072 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1073 }; 1074 1075 enum { 1076 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1077 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1078 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1079 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1080 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1081 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1082 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1083 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1084 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1085 }; 1086 1087 struct mlx5_ifc_atomic_caps_bits { 1088 u8 reserved_at_0[0x40]; 1089 1090 u8 atomic_req_8B_endianness_mode[0x2]; 1091 u8 reserved_at_42[0x4]; 1092 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1093 1094 u8 reserved_at_47[0x19]; 1095 1096 u8 reserved_at_60[0x20]; 1097 1098 u8 reserved_at_80[0x10]; 1099 u8 atomic_operations[0x10]; 1100 1101 u8 reserved_at_a0[0x10]; 1102 u8 atomic_size_qp[0x10]; 1103 1104 u8 reserved_at_c0[0x10]; 1105 u8 atomic_size_dc[0x10]; 1106 1107 u8 reserved_at_e0[0x720]; 1108 }; 1109 1110 struct mlx5_ifc_odp_cap_bits { 1111 u8 reserved_at_0[0x40]; 1112 1113 u8 sig[0x1]; 1114 u8 reserved_at_41[0x1f]; 1115 1116 u8 reserved_at_60[0x20]; 1117 1118 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1119 1120 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1121 1122 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1123 1124 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1125 1126 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1127 1128 u8 reserved_at_120[0x6E0]; 1129 }; 1130 1131 struct mlx5_ifc_calc_op { 1132 u8 reserved_at_0[0x10]; 1133 u8 reserved_at_10[0x9]; 1134 u8 op_swap_endianness[0x1]; 1135 u8 op_min[0x1]; 1136 u8 op_xor[0x1]; 1137 u8 op_or[0x1]; 1138 u8 op_and[0x1]; 1139 u8 op_max[0x1]; 1140 u8 op_add[0x1]; 1141 }; 1142 1143 struct mlx5_ifc_vector_calc_cap_bits { 1144 u8 calc_matrix[0x1]; 1145 u8 reserved_at_1[0x1f]; 1146 u8 reserved_at_20[0x8]; 1147 u8 max_vec_count[0x8]; 1148 u8 reserved_at_30[0xd]; 1149 u8 max_chunk_size[0x3]; 1150 struct mlx5_ifc_calc_op calc0; 1151 struct mlx5_ifc_calc_op calc1; 1152 struct mlx5_ifc_calc_op calc2; 1153 struct mlx5_ifc_calc_op calc3; 1154 1155 u8 reserved_at_c0[0x720]; 1156 }; 1157 1158 struct mlx5_ifc_tls_cap_bits { 1159 u8 tls_1_2_aes_gcm_128[0x1]; 1160 u8 tls_1_3_aes_gcm_128[0x1]; 1161 u8 tls_1_2_aes_gcm_256[0x1]; 1162 u8 tls_1_3_aes_gcm_256[0x1]; 1163 u8 reserved_at_4[0x1c]; 1164 1165 u8 reserved_at_20[0x7e0]; 1166 }; 1167 1168 struct mlx5_ifc_ipsec_cap_bits { 1169 u8 ipsec_full_offload[0x1]; 1170 u8 ipsec_crypto_offload[0x1]; 1171 u8 ipsec_esn[0x1]; 1172 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1173 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1174 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1175 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1176 u8 reserved_at_7[0x4]; 1177 u8 log_max_ipsec_offload[0x5]; 1178 u8 reserved_at_10[0x10]; 1179 1180 u8 min_log_ipsec_full_replay_window[0x8]; 1181 u8 max_log_ipsec_full_replay_window[0x8]; 1182 u8 reserved_at_30[0x7d0]; 1183 }; 1184 1185 enum { 1186 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1187 MLX5_WQ_TYPE_CYCLIC = 0x1, 1188 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1189 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1190 }; 1191 1192 enum { 1193 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1194 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1195 }; 1196 1197 enum { 1198 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1199 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1200 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1201 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1202 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1203 }; 1204 1205 enum { 1206 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1207 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1208 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1209 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1210 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1211 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1212 }; 1213 1214 enum { 1215 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1216 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1217 }; 1218 1219 enum { 1220 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1221 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1222 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1223 }; 1224 1225 enum { 1226 MLX5_CAP_PORT_TYPE_IB = 0x0, 1227 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1228 }; 1229 1230 enum { 1231 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1232 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1233 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1234 }; 1235 1236 enum { 1237 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1238 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1239 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1240 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1241 }; 1242 1243 enum { 1244 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1245 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1246 }; 1247 1248 #define MLX5_FC_BULK_SIZE_FACTOR 128 1249 1250 enum mlx5_fc_bulk_alloc_bitmask { 1251 MLX5_FC_BULK_128 = (1 << 0), 1252 MLX5_FC_BULK_256 = (1 << 1), 1253 MLX5_FC_BULK_512 = (1 << 2), 1254 MLX5_FC_BULK_1024 = (1 << 3), 1255 MLX5_FC_BULK_2048 = (1 << 4), 1256 MLX5_FC_BULK_4096 = (1 << 5), 1257 MLX5_FC_BULK_8192 = (1 << 6), 1258 MLX5_FC_BULK_16384 = (1 << 7), 1259 }; 1260 1261 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1262 1263 enum { 1264 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1265 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1266 }; 1267 1268 enum { 1269 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1270 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1271 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1272 }; 1273 1274 enum { 1275 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1276 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1277 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1278 }; 1279 1280 struct mlx5_ifc_cmd_hca_cap_bits { 1281 u8 reserved_at_0[0x1f]; 1282 u8 vhca_resource_manager[0x1]; 1283 1284 u8 reserved_at_20[0x3]; 1285 u8 event_on_vhca_state_teardown_request[0x1]; 1286 u8 event_on_vhca_state_in_use[0x1]; 1287 u8 event_on_vhca_state_active[0x1]; 1288 u8 event_on_vhca_state_allocated[0x1]; 1289 u8 event_on_vhca_state_invalid[0x1]; 1290 u8 reserved_at_28[0x8]; 1291 u8 vhca_id[0x10]; 1292 1293 u8 reserved_at_40[0x40]; 1294 1295 u8 log_max_srq_sz[0x8]; 1296 u8 log_max_qp_sz[0x8]; 1297 u8 event_cap[0x1]; 1298 u8 reserved_at_91[0x7]; 1299 u8 prio_tag_required[0x1]; 1300 u8 reserved_at_99[0x2]; 1301 u8 log_max_qp[0x5]; 1302 1303 u8 reserved_at_a0[0x3]; 1304 u8 ece_support[0x1]; 1305 u8 reserved_at_a4[0x5]; 1306 u8 reg_c_preserve[0x1]; 1307 u8 reserved_at_aa[0x1]; 1308 u8 log_max_srq[0x5]; 1309 u8 reserved_at_b0[0x1]; 1310 u8 uplink_follow[0x1]; 1311 u8 ts_cqe_to_dest_cqn[0x1]; 1312 u8 reserved_at_b3[0xd]; 1313 1314 u8 max_sgl_for_optimized_performance[0x8]; 1315 u8 log_max_cq_sz[0x8]; 1316 u8 relaxed_ordering_write_umr[0x1]; 1317 u8 relaxed_ordering_read_umr[0x1]; 1318 u8 reserved_at_d2[0x7]; 1319 u8 virtio_net_device_emualtion_manager[0x1]; 1320 u8 virtio_blk_device_emualtion_manager[0x1]; 1321 u8 log_max_cq[0x5]; 1322 1323 u8 log_max_eq_sz[0x8]; 1324 u8 relaxed_ordering_write[0x1]; 1325 u8 relaxed_ordering_read[0x1]; 1326 u8 log_max_mkey[0x6]; 1327 u8 reserved_at_f0[0x8]; 1328 u8 dump_fill_mkey[0x1]; 1329 u8 reserved_at_f9[0x2]; 1330 u8 fast_teardown[0x1]; 1331 u8 log_max_eq[0x4]; 1332 1333 u8 max_indirection[0x8]; 1334 u8 fixed_buffer_size[0x1]; 1335 u8 log_max_mrw_sz[0x7]; 1336 u8 force_teardown[0x1]; 1337 u8 reserved_at_111[0x1]; 1338 u8 log_max_bsf_list_size[0x6]; 1339 u8 umr_extended_translation_offset[0x1]; 1340 u8 null_mkey[0x1]; 1341 u8 log_max_klm_list_size[0x6]; 1342 1343 u8 reserved_at_120[0xa]; 1344 u8 log_max_ra_req_dc[0x6]; 1345 u8 reserved_at_130[0xa]; 1346 u8 log_max_ra_res_dc[0x6]; 1347 1348 u8 reserved_at_140[0x6]; 1349 u8 release_all_pages[0x1]; 1350 u8 reserved_at_147[0x2]; 1351 u8 roce_accl[0x1]; 1352 u8 log_max_ra_req_qp[0x6]; 1353 u8 reserved_at_150[0xa]; 1354 u8 log_max_ra_res_qp[0x6]; 1355 1356 u8 end_pad[0x1]; 1357 u8 cc_query_allowed[0x1]; 1358 u8 cc_modify_allowed[0x1]; 1359 u8 start_pad[0x1]; 1360 u8 cache_line_128byte[0x1]; 1361 u8 reserved_at_165[0x4]; 1362 u8 rts2rts_qp_counters_set_id[0x1]; 1363 u8 reserved_at_16a[0x2]; 1364 u8 vnic_env_int_rq_oob[0x1]; 1365 u8 sbcam_reg[0x1]; 1366 u8 reserved_at_16e[0x1]; 1367 u8 qcam_reg[0x1]; 1368 u8 gid_table_size[0x10]; 1369 1370 u8 out_of_seq_cnt[0x1]; 1371 u8 vport_counters[0x1]; 1372 u8 retransmission_q_counters[0x1]; 1373 u8 debug[0x1]; 1374 u8 modify_rq_counter_set_id[0x1]; 1375 u8 rq_delay_drop[0x1]; 1376 u8 max_qp_cnt[0xa]; 1377 u8 pkey_table_size[0x10]; 1378 1379 u8 vport_group_manager[0x1]; 1380 u8 vhca_group_manager[0x1]; 1381 u8 ib_virt[0x1]; 1382 u8 eth_virt[0x1]; 1383 u8 vnic_env_queue_counters[0x1]; 1384 u8 ets[0x1]; 1385 u8 nic_flow_table[0x1]; 1386 u8 eswitch_manager[0x1]; 1387 u8 device_memory[0x1]; 1388 u8 mcam_reg[0x1]; 1389 u8 pcam_reg[0x1]; 1390 u8 local_ca_ack_delay[0x5]; 1391 u8 port_module_event[0x1]; 1392 u8 enhanced_error_q_counters[0x1]; 1393 u8 ports_check[0x1]; 1394 u8 reserved_at_1b3[0x1]; 1395 u8 disable_link_up[0x1]; 1396 u8 beacon_led[0x1]; 1397 u8 port_type[0x2]; 1398 u8 num_ports[0x8]; 1399 1400 u8 reserved_at_1c0[0x1]; 1401 u8 pps[0x1]; 1402 u8 pps_modify[0x1]; 1403 u8 log_max_msg[0x5]; 1404 u8 reserved_at_1c8[0x4]; 1405 u8 max_tc[0x4]; 1406 u8 temp_warn_event[0x1]; 1407 u8 dcbx[0x1]; 1408 u8 general_notification_event[0x1]; 1409 u8 reserved_at_1d3[0x2]; 1410 u8 fpga[0x1]; 1411 u8 rol_s[0x1]; 1412 u8 rol_g[0x1]; 1413 u8 reserved_at_1d8[0x1]; 1414 u8 wol_s[0x1]; 1415 u8 wol_g[0x1]; 1416 u8 wol_a[0x1]; 1417 u8 wol_b[0x1]; 1418 u8 wol_m[0x1]; 1419 u8 wol_u[0x1]; 1420 u8 wol_p[0x1]; 1421 1422 u8 stat_rate_support[0x10]; 1423 u8 reserved_at_1f0[0x1]; 1424 u8 pci_sync_for_fw_update_event[0x1]; 1425 u8 reserved_at_1f2[0x6]; 1426 u8 init2_lag_tx_port_affinity[0x1]; 1427 u8 reserved_at_1fa[0x3]; 1428 u8 cqe_version[0x4]; 1429 1430 u8 compact_address_vector[0x1]; 1431 u8 striding_rq[0x1]; 1432 u8 reserved_at_202[0x1]; 1433 u8 ipoib_enhanced_offloads[0x1]; 1434 u8 ipoib_basic_offloads[0x1]; 1435 u8 reserved_at_205[0x1]; 1436 u8 repeated_block_disabled[0x1]; 1437 u8 umr_modify_entity_size_disabled[0x1]; 1438 u8 umr_modify_atomic_disabled[0x1]; 1439 u8 umr_indirect_mkey_disabled[0x1]; 1440 u8 umr_fence[0x2]; 1441 u8 dc_req_scat_data_cqe[0x1]; 1442 u8 reserved_at_20d[0x2]; 1443 u8 drain_sigerr[0x1]; 1444 u8 cmdif_checksum[0x2]; 1445 u8 sigerr_cqe[0x1]; 1446 u8 reserved_at_213[0x1]; 1447 u8 wq_signature[0x1]; 1448 u8 sctr_data_cqe[0x1]; 1449 u8 reserved_at_216[0x1]; 1450 u8 sho[0x1]; 1451 u8 tph[0x1]; 1452 u8 rf[0x1]; 1453 u8 dct[0x1]; 1454 u8 qos[0x1]; 1455 u8 eth_net_offloads[0x1]; 1456 u8 roce[0x1]; 1457 u8 atomic[0x1]; 1458 u8 reserved_at_21f[0x1]; 1459 1460 u8 cq_oi[0x1]; 1461 u8 cq_resize[0x1]; 1462 u8 cq_moderation[0x1]; 1463 u8 reserved_at_223[0x3]; 1464 u8 cq_eq_remap[0x1]; 1465 u8 pg[0x1]; 1466 u8 block_lb_mc[0x1]; 1467 u8 reserved_at_229[0x1]; 1468 u8 scqe_break_moderation[0x1]; 1469 u8 cq_period_start_from_cqe[0x1]; 1470 u8 cd[0x1]; 1471 u8 reserved_at_22d[0x1]; 1472 u8 apm[0x1]; 1473 u8 vector_calc[0x1]; 1474 u8 umr_ptr_rlky[0x1]; 1475 u8 imaicl[0x1]; 1476 u8 qp_packet_based[0x1]; 1477 u8 reserved_at_233[0x3]; 1478 u8 qkv[0x1]; 1479 u8 pkv[0x1]; 1480 u8 set_deth_sqpn[0x1]; 1481 u8 reserved_at_239[0x3]; 1482 u8 xrc[0x1]; 1483 u8 ud[0x1]; 1484 u8 uc[0x1]; 1485 u8 rc[0x1]; 1486 1487 u8 uar_4k[0x1]; 1488 u8 reserved_at_241[0x9]; 1489 u8 uar_sz[0x6]; 1490 u8 reserved_at_250[0x8]; 1491 u8 log_pg_sz[0x8]; 1492 1493 u8 bf[0x1]; 1494 u8 driver_version[0x1]; 1495 u8 pad_tx_eth_packet[0x1]; 1496 u8 reserved_at_263[0x3]; 1497 u8 mkey_by_name[0x1]; 1498 u8 reserved_at_267[0x4]; 1499 1500 u8 log_bf_reg_size[0x5]; 1501 1502 u8 reserved_at_270[0x6]; 1503 u8 lag_dct[0x2]; 1504 u8 lag_tx_port_affinity[0x1]; 1505 u8 reserved_at_279[0x2]; 1506 u8 lag_master[0x1]; 1507 u8 num_lag_ports[0x4]; 1508 1509 u8 reserved_at_280[0x10]; 1510 u8 max_wqe_sz_sq[0x10]; 1511 1512 u8 reserved_at_2a0[0x10]; 1513 u8 max_wqe_sz_rq[0x10]; 1514 1515 u8 max_flow_counter_31_16[0x10]; 1516 u8 max_wqe_sz_sq_dc[0x10]; 1517 1518 u8 reserved_at_2e0[0x7]; 1519 u8 max_qp_mcg[0x19]; 1520 1521 u8 reserved_at_300[0x10]; 1522 u8 flow_counter_bulk_alloc[0x8]; 1523 u8 log_max_mcg[0x8]; 1524 1525 u8 reserved_at_320[0x3]; 1526 u8 log_max_transport_domain[0x5]; 1527 u8 reserved_at_328[0x3]; 1528 u8 log_max_pd[0x5]; 1529 u8 reserved_at_330[0xb]; 1530 u8 log_max_xrcd[0x5]; 1531 1532 u8 nic_receive_steering_discard[0x1]; 1533 u8 receive_discard_vport_down[0x1]; 1534 u8 transmit_discard_vport_down[0x1]; 1535 u8 reserved_at_343[0x5]; 1536 u8 log_max_flow_counter_bulk[0x8]; 1537 u8 max_flow_counter_15_0[0x10]; 1538 1539 1540 u8 reserved_at_360[0x3]; 1541 u8 log_max_rq[0x5]; 1542 u8 reserved_at_368[0x3]; 1543 u8 log_max_sq[0x5]; 1544 u8 reserved_at_370[0x3]; 1545 u8 log_max_tir[0x5]; 1546 u8 reserved_at_378[0x3]; 1547 u8 log_max_tis[0x5]; 1548 1549 u8 basic_cyclic_rcv_wqe[0x1]; 1550 u8 reserved_at_381[0x2]; 1551 u8 log_max_rmp[0x5]; 1552 u8 reserved_at_388[0x3]; 1553 u8 log_max_rqt[0x5]; 1554 u8 reserved_at_390[0x3]; 1555 u8 log_max_rqt_size[0x5]; 1556 u8 reserved_at_398[0x3]; 1557 u8 log_max_tis_per_sq[0x5]; 1558 1559 u8 ext_stride_num_range[0x1]; 1560 u8 reserved_at_3a1[0x2]; 1561 u8 log_max_stride_sz_rq[0x5]; 1562 u8 reserved_at_3a8[0x3]; 1563 u8 log_min_stride_sz_rq[0x5]; 1564 u8 reserved_at_3b0[0x3]; 1565 u8 log_max_stride_sz_sq[0x5]; 1566 u8 reserved_at_3b8[0x3]; 1567 u8 log_min_stride_sz_sq[0x5]; 1568 1569 u8 hairpin[0x1]; 1570 u8 reserved_at_3c1[0x2]; 1571 u8 log_max_hairpin_queues[0x5]; 1572 u8 reserved_at_3c8[0x3]; 1573 u8 log_max_hairpin_wq_data_sz[0x5]; 1574 u8 reserved_at_3d0[0x3]; 1575 u8 log_max_hairpin_num_packets[0x5]; 1576 u8 reserved_at_3d8[0x3]; 1577 u8 log_max_wq_sz[0x5]; 1578 1579 u8 nic_vport_change_event[0x1]; 1580 u8 disable_local_lb_uc[0x1]; 1581 u8 disable_local_lb_mc[0x1]; 1582 u8 log_min_hairpin_wq_data_sz[0x5]; 1583 u8 reserved_at_3e8[0x2]; 1584 u8 vhca_state[0x1]; 1585 u8 log_max_vlan_list[0x5]; 1586 u8 reserved_at_3f0[0x3]; 1587 u8 log_max_current_mc_list[0x5]; 1588 u8 reserved_at_3f8[0x3]; 1589 u8 log_max_current_uc_list[0x5]; 1590 1591 u8 general_obj_types[0x40]; 1592 1593 u8 sq_ts_format[0x2]; 1594 u8 rq_ts_format[0x2]; 1595 u8 steering_format_version[0x4]; 1596 u8 create_qp_start_hint[0x18]; 1597 1598 u8 reserved_at_460[0x3]; 1599 u8 log_max_uctx[0x5]; 1600 u8 reserved_at_468[0x2]; 1601 u8 ipsec_offload[0x1]; 1602 u8 log_max_umem[0x5]; 1603 u8 max_num_eqs[0x10]; 1604 1605 u8 reserved_at_480[0x1]; 1606 u8 tls_tx[0x1]; 1607 u8 tls_rx[0x1]; 1608 u8 log_max_l2_table[0x5]; 1609 u8 reserved_at_488[0x8]; 1610 u8 log_uar_page_sz[0x10]; 1611 1612 u8 reserved_at_4a0[0x20]; 1613 u8 device_frequency_mhz[0x20]; 1614 u8 device_frequency_khz[0x20]; 1615 1616 u8 reserved_at_500[0x20]; 1617 u8 num_of_uars_per_page[0x20]; 1618 1619 u8 flex_parser_protocols[0x20]; 1620 1621 u8 max_geneve_tlv_options[0x8]; 1622 u8 reserved_at_568[0x3]; 1623 u8 max_geneve_tlv_option_data_len[0x5]; 1624 u8 reserved_at_570[0x10]; 1625 1626 u8 reserved_at_580[0x33]; 1627 u8 log_max_dek[0x5]; 1628 u8 reserved_at_5b8[0x4]; 1629 u8 mini_cqe_resp_stride_index[0x1]; 1630 u8 cqe_128_always[0x1]; 1631 u8 cqe_compression_128[0x1]; 1632 u8 cqe_compression[0x1]; 1633 1634 u8 cqe_compression_timeout[0x10]; 1635 u8 cqe_compression_max_num[0x10]; 1636 1637 u8 reserved_at_5e0[0x10]; 1638 u8 tag_matching[0x1]; 1639 u8 rndv_offload_rc[0x1]; 1640 u8 rndv_offload_dc[0x1]; 1641 u8 log_tag_matching_list_sz[0x5]; 1642 u8 reserved_at_5f8[0x3]; 1643 u8 log_max_xrq[0x5]; 1644 1645 u8 affiliate_nic_vport_criteria[0x8]; 1646 u8 native_port_num[0x8]; 1647 u8 num_vhca_ports[0x8]; 1648 u8 reserved_at_618[0x6]; 1649 u8 sw_owner_id[0x1]; 1650 u8 reserved_at_61f[0x1]; 1651 1652 u8 max_num_of_monitor_counters[0x10]; 1653 u8 num_ppcnt_monitor_counters[0x10]; 1654 1655 u8 max_num_sf[0x10]; 1656 u8 num_q_monitor_counters[0x10]; 1657 1658 u8 reserved_at_660[0x20]; 1659 1660 u8 sf[0x1]; 1661 u8 sf_set_partition[0x1]; 1662 u8 reserved_at_682[0x1]; 1663 u8 log_max_sf[0x5]; 1664 u8 reserved_at_688[0x8]; 1665 u8 log_min_sf_size[0x8]; 1666 u8 max_num_sf_partitions[0x8]; 1667 1668 u8 uctx_cap[0x20]; 1669 1670 u8 reserved_at_6c0[0x4]; 1671 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1672 u8 flex_parser_id_icmp_dw1[0x4]; 1673 u8 flex_parser_id_icmp_dw0[0x4]; 1674 u8 flex_parser_id_icmpv6_dw1[0x4]; 1675 u8 flex_parser_id_icmpv6_dw0[0x4]; 1676 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1677 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1678 1679 u8 reserved_at_6e0[0x10]; 1680 u8 sf_base_id[0x10]; 1681 1682 u8 reserved_at_700[0x80]; 1683 u8 vhca_tunnel_commands[0x40]; 1684 u8 reserved_at_7c0[0x40]; 1685 }; 1686 1687 enum mlx5_flow_destination_type { 1688 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1689 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1690 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1691 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1692 1693 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1694 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1695 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1696 }; 1697 1698 enum mlx5_flow_table_miss_action { 1699 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1700 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1701 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1702 }; 1703 1704 struct mlx5_ifc_dest_format_struct_bits { 1705 u8 destination_type[0x8]; 1706 u8 destination_id[0x18]; 1707 1708 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1709 u8 packet_reformat[0x1]; 1710 u8 reserved_at_22[0xe]; 1711 u8 destination_eswitch_owner_vhca_id[0x10]; 1712 }; 1713 1714 struct mlx5_ifc_flow_counter_list_bits { 1715 u8 flow_counter_id[0x20]; 1716 1717 u8 reserved_at_20[0x20]; 1718 }; 1719 1720 struct mlx5_ifc_extended_dest_format_bits { 1721 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1722 1723 u8 packet_reformat_id[0x20]; 1724 1725 u8 reserved_at_60[0x20]; 1726 }; 1727 1728 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1729 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1730 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1731 }; 1732 1733 struct mlx5_ifc_fte_match_param_bits { 1734 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1735 1736 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1737 1738 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1739 1740 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1741 1742 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1743 1744 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1745 1746 u8 reserved_at_c00[0x400]; 1747 }; 1748 1749 enum { 1750 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1751 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1752 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1753 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1754 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1755 }; 1756 1757 struct mlx5_ifc_rx_hash_field_select_bits { 1758 u8 l3_prot_type[0x1]; 1759 u8 l4_prot_type[0x1]; 1760 u8 selected_fields[0x1e]; 1761 }; 1762 1763 enum { 1764 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1765 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1766 }; 1767 1768 enum { 1769 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1770 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1771 }; 1772 1773 struct mlx5_ifc_wq_bits { 1774 u8 wq_type[0x4]; 1775 u8 wq_signature[0x1]; 1776 u8 end_padding_mode[0x2]; 1777 u8 cd_slave[0x1]; 1778 u8 reserved_at_8[0x18]; 1779 1780 u8 hds_skip_first_sge[0x1]; 1781 u8 log2_hds_buf_size[0x3]; 1782 u8 reserved_at_24[0x7]; 1783 u8 page_offset[0x5]; 1784 u8 lwm[0x10]; 1785 1786 u8 reserved_at_40[0x8]; 1787 u8 pd[0x18]; 1788 1789 u8 reserved_at_60[0x8]; 1790 u8 uar_page[0x18]; 1791 1792 u8 dbr_addr[0x40]; 1793 1794 u8 hw_counter[0x20]; 1795 1796 u8 sw_counter[0x20]; 1797 1798 u8 reserved_at_100[0xc]; 1799 u8 log_wq_stride[0x4]; 1800 u8 reserved_at_110[0x3]; 1801 u8 log_wq_pg_sz[0x5]; 1802 u8 reserved_at_118[0x3]; 1803 u8 log_wq_sz[0x5]; 1804 1805 u8 dbr_umem_valid[0x1]; 1806 u8 wq_umem_valid[0x1]; 1807 u8 reserved_at_122[0x1]; 1808 u8 log_hairpin_num_packets[0x5]; 1809 u8 reserved_at_128[0x3]; 1810 u8 log_hairpin_data_sz[0x5]; 1811 1812 u8 reserved_at_130[0x4]; 1813 u8 log_wqe_num_of_strides[0x4]; 1814 u8 two_byte_shift_en[0x1]; 1815 u8 reserved_at_139[0x4]; 1816 u8 log_wqe_stride_size[0x3]; 1817 1818 u8 reserved_at_140[0x4c0]; 1819 1820 struct mlx5_ifc_cmd_pas_bits pas[]; 1821 }; 1822 1823 struct mlx5_ifc_rq_num_bits { 1824 u8 reserved_at_0[0x8]; 1825 u8 rq_num[0x18]; 1826 }; 1827 1828 struct mlx5_ifc_mac_address_layout_bits { 1829 u8 reserved_at_0[0x10]; 1830 u8 mac_addr_47_32[0x10]; 1831 1832 u8 mac_addr_31_0[0x20]; 1833 }; 1834 1835 struct mlx5_ifc_vlan_layout_bits { 1836 u8 reserved_at_0[0x14]; 1837 u8 vlan[0x0c]; 1838 1839 u8 reserved_at_20[0x20]; 1840 }; 1841 1842 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1843 u8 reserved_at_0[0xa0]; 1844 1845 u8 min_time_between_cnps[0x20]; 1846 1847 u8 reserved_at_c0[0x12]; 1848 u8 cnp_dscp[0x6]; 1849 u8 reserved_at_d8[0x4]; 1850 u8 cnp_prio_mode[0x1]; 1851 u8 cnp_802p_prio[0x3]; 1852 1853 u8 reserved_at_e0[0x720]; 1854 }; 1855 1856 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1857 u8 reserved_at_0[0x60]; 1858 1859 u8 reserved_at_60[0x4]; 1860 u8 clamp_tgt_rate[0x1]; 1861 u8 reserved_at_65[0x3]; 1862 u8 clamp_tgt_rate_after_time_inc[0x1]; 1863 u8 reserved_at_69[0x17]; 1864 1865 u8 reserved_at_80[0x20]; 1866 1867 u8 rpg_time_reset[0x20]; 1868 1869 u8 rpg_byte_reset[0x20]; 1870 1871 u8 rpg_threshold[0x20]; 1872 1873 u8 rpg_max_rate[0x20]; 1874 1875 u8 rpg_ai_rate[0x20]; 1876 1877 u8 rpg_hai_rate[0x20]; 1878 1879 u8 rpg_gd[0x20]; 1880 1881 u8 rpg_min_dec_fac[0x20]; 1882 1883 u8 rpg_min_rate[0x20]; 1884 1885 u8 reserved_at_1c0[0xe0]; 1886 1887 u8 rate_to_set_on_first_cnp[0x20]; 1888 1889 u8 dce_tcp_g[0x20]; 1890 1891 u8 dce_tcp_rtt[0x20]; 1892 1893 u8 rate_reduce_monitor_period[0x20]; 1894 1895 u8 reserved_at_320[0x20]; 1896 1897 u8 initial_alpha_value[0x20]; 1898 1899 u8 reserved_at_360[0x4a0]; 1900 }; 1901 1902 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1903 u8 reserved_at_0[0x80]; 1904 1905 u8 rppp_max_rps[0x20]; 1906 1907 u8 rpg_time_reset[0x20]; 1908 1909 u8 rpg_byte_reset[0x20]; 1910 1911 u8 rpg_threshold[0x20]; 1912 1913 u8 rpg_max_rate[0x20]; 1914 1915 u8 rpg_ai_rate[0x20]; 1916 1917 u8 rpg_hai_rate[0x20]; 1918 1919 u8 rpg_gd[0x20]; 1920 1921 u8 rpg_min_dec_fac[0x20]; 1922 1923 u8 rpg_min_rate[0x20]; 1924 1925 u8 reserved_at_1c0[0x640]; 1926 }; 1927 1928 enum { 1929 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1930 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1931 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1932 }; 1933 1934 struct mlx5_ifc_resize_field_select_bits { 1935 u8 resize_field_select[0x20]; 1936 }; 1937 1938 struct mlx5_ifc_resource_dump_bits { 1939 u8 more_dump[0x1]; 1940 u8 inline_dump[0x1]; 1941 u8 reserved_at_2[0xa]; 1942 u8 seq_num[0x4]; 1943 u8 segment_type[0x10]; 1944 1945 u8 reserved_at_20[0x10]; 1946 u8 vhca_id[0x10]; 1947 1948 u8 index1[0x20]; 1949 1950 u8 index2[0x20]; 1951 1952 u8 num_of_obj1[0x10]; 1953 u8 num_of_obj2[0x10]; 1954 1955 u8 reserved_at_a0[0x20]; 1956 1957 u8 device_opaque[0x40]; 1958 1959 u8 mkey[0x20]; 1960 1961 u8 size[0x20]; 1962 1963 u8 address[0x40]; 1964 1965 u8 inline_data[52][0x20]; 1966 }; 1967 1968 struct mlx5_ifc_resource_dump_menu_record_bits { 1969 u8 reserved_at_0[0x4]; 1970 u8 num_of_obj2_supports_active[0x1]; 1971 u8 num_of_obj2_supports_all[0x1]; 1972 u8 must_have_num_of_obj2[0x1]; 1973 u8 support_num_of_obj2[0x1]; 1974 u8 num_of_obj1_supports_active[0x1]; 1975 u8 num_of_obj1_supports_all[0x1]; 1976 u8 must_have_num_of_obj1[0x1]; 1977 u8 support_num_of_obj1[0x1]; 1978 u8 must_have_index2[0x1]; 1979 u8 support_index2[0x1]; 1980 u8 must_have_index1[0x1]; 1981 u8 support_index1[0x1]; 1982 u8 segment_type[0x10]; 1983 1984 u8 segment_name[4][0x20]; 1985 1986 u8 index1_name[4][0x20]; 1987 1988 u8 index2_name[4][0x20]; 1989 }; 1990 1991 struct mlx5_ifc_resource_dump_segment_header_bits { 1992 u8 length_dw[0x10]; 1993 u8 segment_type[0x10]; 1994 }; 1995 1996 struct mlx5_ifc_resource_dump_command_segment_bits { 1997 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1998 1999 u8 segment_called[0x10]; 2000 u8 vhca_id[0x10]; 2001 2002 u8 index1[0x20]; 2003 2004 u8 index2[0x20]; 2005 2006 u8 num_of_obj1[0x10]; 2007 u8 num_of_obj2[0x10]; 2008 }; 2009 2010 struct mlx5_ifc_resource_dump_error_segment_bits { 2011 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2012 2013 u8 reserved_at_20[0x10]; 2014 u8 syndrome_id[0x10]; 2015 2016 u8 reserved_at_40[0x40]; 2017 2018 u8 error[8][0x20]; 2019 }; 2020 2021 struct mlx5_ifc_resource_dump_info_segment_bits { 2022 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2023 2024 u8 reserved_at_20[0x18]; 2025 u8 dump_version[0x8]; 2026 2027 u8 hw_version[0x20]; 2028 2029 u8 fw_version[0x20]; 2030 }; 2031 2032 struct mlx5_ifc_resource_dump_menu_segment_bits { 2033 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2034 2035 u8 reserved_at_20[0x10]; 2036 u8 num_of_records[0x10]; 2037 2038 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2039 }; 2040 2041 struct mlx5_ifc_resource_dump_resource_segment_bits { 2042 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2043 2044 u8 reserved_at_20[0x20]; 2045 2046 u8 index1[0x20]; 2047 2048 u8 index2[0x20]; 2049 2050 u8 payload[][0x20]; 2051 }; 2052 2053 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2054 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2055 }; 2056 2057 struct mlx5_ifc_menu_resource_dump_response_bits { 2058 struct mlx5_ifc_resource_dump_info_segment_bits info; 2059 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2060 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2061 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2062 }; 2063 2064 enum { 2065 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2066 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2067 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2068 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2069 }; 2070 2071 struct mlx5_ifc_modify_field_select_bits { 2072 u8 modify_field_select[0x20]; 2073 }; 2074 2075 struct mlx5_ifc_field_select_r_roce_np_bits { 2076 u8 field_select_r_roce_np[0x20]; 2077 }; 2078 2079 struct mlx5_ifc_field_select_r_roce_rp_bits { 2080 u8 field_select_r_roce_rp[0x20]; 2081 }; 2082 2083 enum { 2084 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2085 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2086 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2087 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2088 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2089 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2090 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2091 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2092 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2093 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2094 }; 2095 2096 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2097 u8 field_select_8021qaurp[0x20]; 2098 }; 2099 2100 struct mlx5_ifc_phys_layer_cntrs_bits { 2101 u8 time_since_last_clear_high[0x20]; 2102 2103 u8 time_since_last_clear_low[0x20]; 2104 2105 u8 symbol_errors_high[0x20]; 2106 2107 u8 symbol_errors_low[0x20]; 2108 2109 u8 sync_headers_errors_high[0x20]; 2110 2111 u8 sync_headers_errors_low[0x20]; 2112 2113 u8 edpl_bip_errors_lane0_high[0x20]; 2114 2115 u8 edpl_bip_errors_lane0_low[0x20]; 2116 2117 u8 edpl_bip_errors_lane1_high[0x20]; 2118 2119 u8 edpl_bip_errors_lane1_low[0x20]; 2120 2121 u8 edpl_bip_errors_lane2_high[0x20]; 2122 2123 u8 edpl_bip_errors_lane2_low[0x20]; 2124 2125 u8 edpl_bip_errors_lane3_high[0x20]; 2126 2127 u8 edpl_bip_errors_lane3_low[0x20]; 2128 2129 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2130 2131 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2132 2133 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2134 2135 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2136 2137 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2138 2139 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2140 2141 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2142 2143 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2144 2145 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2146 2147 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2148 2149 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2150 2151 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2152 2153 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2154 2155 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2156 2157 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2158 2159 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2160 2161 u8 rs_fec_corrected_blocks_high[0x20]; 2162 2163 u8 rs_fec_corrected_blocks_low[0x20]; 2164 2165 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2166 2167 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2168 2169 u8 rs_fec_no_errors_blocks_high[0x20]; 2170 2171 u8 rs_fec_no_errors_blocks_low[0x20]; 2172 2173 u8 rs_fec_single_error_blocks_high[0x20]; 2174 2175 u8 rs_fec_single_error_blocks_low[0x20]; 2176 2177 u8 rs_fec_corrected_symbols_total_high[0x20]; 2178 2179 u8 rs_fec_corrected_symbols_total_low[0x20]; 2180 2181 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2182 2183 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2184 2185 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2186 2187 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2188 2189 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2190 2191 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2192 2193 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2194 2195 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2196 2197 u8 link_down_events[0x20]; 2198 2199 u8 successful_recovery_events[0x20]; 2200 2201 u8 reserved_at_640[0x180]; 2202 }; 2203 2204 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2205 u8 time_since_last_clear_high[0x20]; 2206 2207 u8 time_since_last_clear_low[0x20]; 2208 2209 u8 phy_received_bits_high[0x20]; 2210 2211 u8 phy_received_bits_low[0x20]; 2212 2213 u8 phy_symbol_errors_high[0x20]; 2214 2215 u8 phy_symbol_errors_low[0x20]; 2216 2217 u8 phy_corrected_bits_high[0x20]; 2218 2219 u8 phy_corrected_bits_low[0x20]; 2220 2221 u8 phy_corrected_bits_lane0_high[0x20]; 2222 2223 u8 phy_corrected_bits_lane0_low[0x20]; 2224 2225 u8 phy_corrected_bits_lane1_high[0x20]; 2226 2227 u8 phy_corrected_bits_lane1_low[0x20]; 2228 2229 u8 phy_corrected_bits_lane2_high[0x20]; 2230 2231 u8 phy_corrected_bits_lane2_low[0x20]; 2232 2233 u8 phy_corrected_bits_lane3_high[0x20]; 2234 2235 u8 phy_corrected_bits_lane3_low[0x20]; 2236 2237 u8 reserved_at_200[0x5c0]; 2238 }; 2239 2240 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2241 u8 symbol_error_counter[0x10]; 2242 2243 u8 link_error_recovery_counter[0x8]; 2244 2245 u8 link_downed_counter[0x8]; 2246 2247 u8 port_rcv_errors[0x10]; 2248 2249 u8 port_rcv_remote_physical_errors[0x10]; 2250 2251 u8 port_rcv_switch_relay_errors[0x10]; 2252 2253 u8 port_xmit_discards[0x10]; 2254 2255 u8 port_xmit_constraint_errors[0x8]; 2256 2257 u8 port_rcv_constraint_errors[0x8]; 2258 2259 u8 reserved_at_70[0x8]; 2260 2261 u8 link_overrun_errors[0x8]; 2262 2263 u8 reserved_at_80[0x10]; 2264 2265 u8 vl_15_dropped[0x10]; 2266 2267 u8 reserved_at_a0[0x80]; 2268 2269 u8 port_xmit_wait[0x20]; 2270 }; 2271 2272 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2273 u8 transmit_queue_high[0x20]; 2274 2275 u8 transmit_queue_low[0x20]; 2276 2277 u8 no_buffer_discard_uc_high[0x20]; 2278 2279 u8 no_buffer_discard_uc_low[0x20]; 2280 2281 u8 reserved_at_80[0x740]; 2282 }; 2283 2284 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2285 u8 wred_discard_high[0x20]; 2286 2287 u8 wred_discard_low[0x20]; 2288 2289 u8 ecn_marked_tc_high[0x20]; 2290 2291 u8 ecn_marked_tc_low[0x20]; 2292 2293 u8 reserved_at_80[0x740]; 2294 }; 2295 2296 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2297 u8 rx_octets_high[0x20]; 2298 2299 u8 rx_octets_low[0x20]; 2300 2301 u8 reserved_at_40[0xc0]; 2302 2303 u8 rx_frames_high[0x20]; 2304 2305 u8 rx_frames_low[0x20]; 2306 2307 u8 tx_octets_high[0x20]; 2308 2309 u8 tx_octets_low[0x20]; 2310 2311 u8 reserved_at_180[0xc0]; 2312 2313 u8 tx_frames_high[0x20]; 2314 2315 u8 tx_frames_low[0x20]; 2316 2317 u8 rx_pause_high[0x20]; 2318 2319 u8 rx_pause_low[0x20]; 2320 2321 u8 rx_pause_duration_high[0x20]; 2322 2323 u8 rx_pause_duration_low[0x20]; 2324 2325 u8 tx_pause_high[0x20]; 2326 2327 u8 tx_pause_low[0x20]; 2328 2329 u8 tx_pause_duration_high[0x20]; 2330 2331 u8 tx_pause_duration_low[0x20]; 2332 2333 u8 rx_pause_transition_high[0x20]; 2334 2335 u8 rx_pause_transition_low[0x20]; 2336 2337 u8 rx_discards_high[0x20]; 2338 2339 u8 rx_discards_low[0x20]; 2340 2341 u8 device_stall_minor_watermark_cnt_high[0x20]; 2342 2343 u8 device_stall_minor_watermark_cnt_low[0x20]; 2344 2345 u8 device_stall_critical_watermark_cnt_high[0x20]; 2346 2347 u8 device_stall_critical_watermark_cnt_low[0x20]; 2348 2349 u8 reserved_at_480[0x340]; 2350 }; 2351 2352 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2353 u8 port_transmit_wait_high[0x20]; 2354 2355 u8 port_transmit_wait_low[0x20]; 2356 2357 u8 reserved_at_40[0x100]; 2358 2359 u8 rx_buffer_almost_full_high[0x20]; 2360 2361 u8 rx_buffer_almost_full_low[0x20]; 2362 2363 u8 rx_buffer_full_high[0x20]; 2364 2365 u8 rx_buffer_full_low[0x20]; 2366 2367 u8 rx_icrc_encapsulated_high[0x20]; 2368 2369 u8 rx_icrc_encapsulated_low[0x20]; 2370 2371 u8 reserved_at_200[0x5c0]; 2372 }; 2373 2374 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2375 u8 dot3stats_alignment_errors_high[0x20]; 2376 2377 u8 dot3stats_alignment_errors_low[0x20]; 2378 2379 u8 dot3stats_fcs_errors_high[0x20]; 2380 2381 u8 dot3stats_fcs_errors_low[0x20]; 2382 2383 u8 dot3stats_single_collision_frames_high[0x20]; 2384 2385 u8 dot3stats_single_collision_frames_low[0x20]; 2386 2387 u8 dot3stats_multiple_collision_frames_high[0x20]; 2388 2389 u8 dot3stats_multiple_collision_frames_low[0x20]; 2390 2391 u8 dot3stats_sqe_test_errors_high[0x20]; 2392 2393 u8 dot3stats_sqe_test_errors_low[0x20]; 2394 2395 u8 dot3stats_deferred_transmissions_high[0x20]; 2396 2397 u8 dot3stats_deferred_transmissions_low[0x20]; 2398 2399 u8 dot3stats_late_collisions_high[0x20]; 2400 2401 u8 dot3stats_late_collisions_low[0x20]; 2402 2403 u8 dot3stats_excessive_collisions_high[0x20]; 2404 2405 u8 dot3stats_excessive_collisions_low[0x20]; 2406 2407 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2408 2409 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2410 2411 u8 dot3stats_carrier_sense_errors_high[0x20]; 2412 2413 u8 dot3stats_carrier_sense_errors_low[0x20]; 2414 2415 u8 dot3stats_frame_too_longs_high[0x20]; 2416 2417 u8 dot3stats_frame_too_longs_low[0x20]; 2418 2419 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2420 2421 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2422 2423 u8 dot3stats_symbol_errors_high[0x20]; 2424 2425 u8 dot3stats_symbol_errors_low[0x20]; 2426 2427 u8 dot3control_in_unknown_opcodes_high[0x20]; 2428 2429 u8 dot3control_in_unknown_opcodes_low[0x20]; 2430 2431 u8 dot3in_pause_frames_high[0x20]; 2432 2433 u8 dot3in_pause_frames_low[0x20]; 2434 2435 u8 dot3out_pause_frames_high[0x20]; 2436 2437 u8 dot3out_pause_frames_low[0x20]; 2438 2439 u8 reserved_at_400[0x3c0]; 2440 }; 2441 2442 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2443 u8 ether_stats_drop_events_high[0x20]; 2444 2445 u8 ether_stats_drop_events_low[0x20]; 2446 2447 u8 ether_stats_octets_high[0x20]; 2448 2449 u8 ether_stats_octets_low[0x20]; 2450 2451 u8 ether_stats_pkts_high[0x20]; 2452 2453 u8 ether_stats_pkts_low[0x20]; 2454 2455 u8 ether_stats_broadcast_pkts_high[0x20]; 2456 2457 u8 ether_stats_broadcast_pkts_low[0x20]; 2458 2459 u8 ether_stats_multicast_pkts_high[0x20]; 2460 2461 u8 ether_stats_multicast_pkts_low[0x20]; 2462 2463 u8 ether_stats_crc_align_errors_high[0x20]; 2464 2465 u8 ether_stats_crc_align_errors_low[0x20]; 2466 2467 u8 ether_stats_undersize_pkts_high[0x20]; 2468 2469 u8 ether_stats_undersize_pkts_low[0x20]; 2470 2471 u8 ether_stats_oversize_pkts_high[0x20]; 2472 2473 u8 ether_stats_oversize_pkts_low[0x20]; 2474 2475 u8 ether_stats_fragments_high[0x20]; 2476 2477 u8 ether_stats_fragments_low[0x20]; 2478 2479 u8 ether_stats_jabbers_high[0x20]; 2480 2481 u8 ether_stats_jabbers_low[0x20]; 2482 2483 u8 ether_stats_collisions_high[0x20]; 2484 2485 u8 ether_stats_collisions_low[0x20]; 2486 2487 u8 ether_stats_pkts64octets_high[0x20]; 2488 2489 u8 ether_stats_pkts64octets_low[0x20]; 2490 2491 u8 ether_stats_pkts65to127octets_high[0x20]; 2492 2493 u8 ether_stats_pkts65to127octets_low[0x20]; 2494 2495 u8 ether_stats_pkts128to255octets_high[0x20]; 2496 2497 u8 ether_stats_pkts128to255octets_low[0x20]; 2498 2499 u8 ether_stats_pkts256to511octets_high[0x20]; 2500 2501 u8 ether_stats_pkts256to511octets_low[0x20]; 2502 2503 u8 ether_stats_pkts512to1023octets_high[0x20]; 2504 2505 u8 ether_stats_pkts512to1023octets_low[0x20]; 2506 2507 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2508 2509 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2510 2511 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2512 2513 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2514 2515 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2516 2517 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2518 2519 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2520 2521 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2522 2523 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2524 2525 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2526 2527 u8 reserved_at_540[0x280]; 2528 }; 2529 2530 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2531 u8 if_in_octets_high[0x20]; 2532 2533 u8 if_in_octets_low[0x20]; 2534 2535 u8 if_in_ucast_pkts_high[0x20]; 2536 2537 u8 if_in_ucast_pkts_low[0x20]; 2538 2539 u8 if_in_discards_high[0x20]; 2540 2541 u8 if_in_discards_low[0x20]; 2542 2543 u8 if_in_errors_high[0x20]; 2544 2545 u8 if_in_errors_low[0x20]; 2546 2547 u8 if_in_unknown_protos_high[0x20]; 2548 2549 u8 if_in_unknown_protos_low[0x20]; 2550 2551 u8 if_out_octets_high[0x20]; 2552 2553 u8 if_out_octets_low[0x20]; 2554 2555 u8 if_out_ucast_pkts_high[0x20]; 2556 2557 u8 if_out_ucast_pkts_low[0x20]; 2558 2559 u8 if_out_discards_high[0x20]; 2560 2561 u8 if_out_discards_low[0x20]; 2562 2563 u8 if_out_errors_high[0x20]; 2564 2565 u8 if_out_errors_low[0x20]; 2566 2567 u8 if_in_multicast_pkts_high[0x20]; 2568 2569 u8 if_in_multicast_pkts_low[0x20]; 2570 2571 u8 if_in_broadcast_pkts_high[0x20]; 2572 2573 u8 if_in_broadcast_pkts_low[0x20]; 2574 2575 u8 if_out_multicast_pkts_high[0x20]; 2576 2577 u8 if_out_multicast_pkts_low[0x20]; 2578 2579 u8 if_out_broadcast_pkts_high[0x20]; 2580 2581 u8 if_out_broadcast_pkts_low[0x20]; 2582 2583 u8 reserved_at_340[0x480]; 2584 }; 2585 2586 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2587 u8 a_frames_transmitted_ok_high[0x20]; 2588 2589 u8 a_frames_transmitted_ok_low[0x20]; 2590 2591 u8 a_frames_received_ok_high[0x20]; 2592 2593 u8 a_frames_received_ok_low[0x20]; 2594 2595 u8 a_frame_check_sequence_errors_high[0x20]; 2596 2597 u8 a_frame_check_sequence_errors_low[0x20]; 2598 2599 u8 a_alignment_errors_high[0x20]; 2600 2601 u8 a_alignment_errors_low[0x20]; 2602 2603 u8 a_octets_transmitted_ok_high[0x20]; 2604 2605 u8 a_octets_transmitted_ok_low[0x20]; 2606 2607 u8 a_octets_received_ok_high[0x20]; 2608 2609 u8 a_octets_received_ok_low[0x20]; 2610 2611 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2612 2613 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2614 2615 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2616 2617 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2618 2619 u8 a_multicast_frames_received_ok_high[0x20]; 2620 2621 u8 a_multicast_frames_received_ok_low[0x20]; 2622 2623 u8 a_broadcast_frames_received_ok_high[0x20]; 2624 2625 u8 a_broadcast_frames_received_ok_low[0x20]; 2626 2627 u8 a_in_range_length_errors_high[0x20]; 2628 2629 u8 a_in_range_length_errors_low[0x20]; 2630 2631 u8 a_out_of_range_length_field_high[0x20]; 2632 2633 u8 a_out_of_range_length_field_low[0x20]; 2634 2635 u8 a_frame_too_long_errors_high[0x20]; 2636 2637 u8 a_frame_too_long_errors_low[0x20]; 2638 2639 u8 a_symbol_error_during_carrier_high[0x20]; 2640 2641 u8 a_symbol_error_during_carrier_low[0x20]; 2642 2643 u8 a_mac_control_frames_transmitted_high[0x20]; 2644 2645 u8 a_mac_control_frames_transmitted_low[0x20]; 2646 2647 u8 a_mac_control_frames_received_high[0x20]; 2648 2649 u8 a_mac_control_frames_received_low[0x20]; 2650 2651 u8 a_unsupported_opcodes_received_high[0x20]; 2652 2653 u8 a_unsupported_opcodes_received_low[0x20]; 2654 2655 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2656 2657 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2658 2659 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2660 2661 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2662 2663 u8 reserved_at_4c0[0x300]; 2664 }; 2665 2666 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2667 u8 life_time_counter_high[0x20]; 2668 2669 u8 life_time_counter_low[0x20]; 2670 2671 u8 rx_errors[0x20]; 2672 2673 u8 tx_errors[0x20]; 2674 2675 u8 l0_to_recovery_eieos[0x20]; 2676 2677 u8 l0_to_recovery_ts[0x20]; 2678 2679 u8 l0_to_recovery_framing[0x20]; 2680 2681 u8 l0_to_recovery_retrain[0x20]; 2682 2683 u8 crc_error_dllp[0x20]; 2684 2685 u8 crc_error_tlp[0x20]; 2686 2687 u8 tx_overflow_buffer_pkt_high[0x20]; 2688 2689 u8 tx_overflow_buffer_pkt_low[0x20]; 2690 2691 u8 outbound_stalled_reads[0x20]; 2692 2693 u8 outbound_stalled_writes[0x20]; 2694 2695 u8 outbound_stalled_reads_events[0x20]; 2696 2697 u8 outbound_stalled_writes_events[0x20]; 2698 2699 u8 reserved_at_200[0x5c0]; 2700 }; 2701 2702 struct mlx5_ifc_cmd_inter_comp_event_bits { 2703 u8 command_completion_vector[0x20]; 2704 2705 u8 reserved_at_20[0xc0]; 2706 }; 2707 2708 struct mlx5_ifc_stall_vl_event_bits { 2709 u8 reserved_at_0[0x18]; 2710 u8 port_num[0x1]; 2711 u8 reserved_at_19[0x3]; 2712 u8 vl[0x4]; 2713 2714 u8 reserved_at_20[0xa0]; 2715 }; 2716 2717 struct mlx5_ifc_db_bf_congestion_event_bits { 2718 u8 event_subtype[0x8]; 2719 u8 reserved_at_8[0x8]; 2720 u8 congestion_level[0x8]; 2721 u8 reserved_at_18[0x8]; 2722 2723 u8 reserved_at_20[0xa0]; 2724 }; 2725 2726 struct mlx5_ifc_gpio_event_bits { 2727 u8 reserved_at_0[0x60]; 2728 2729 u8 gpio_event_hi[0x20]; 2730 2731 u8 gpio_event_lo[0x20]; 2732 2733 u8 reserved_at_a0[0x40]; 2734 }; 2735 2736 struct mlx5_ifc_port_state_change_event_bits { 2737 u8 reserved_at_0[0x40]; 2738 2739 u8 port_num[0x4]; 2740 u8 reserved_at_44[0x1c]; 2741 2742 u8 reserved_at_60[0x80]; 2743 }; 2744 2745 struct mlx5_ifc_dropped_packet_logged_bits { 2746 u8 reserved_at_0[0xe0]; 2747 }; 2748 2749 enum { 2750 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2751 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2752 }; 2753 2754 struct mlx5_ifc_cq_error_bits { 2755 u8 reserved_at_0[0x8]; 2756 u8 cqn[0x18]; 2757 2758 u8 reserved_at_20[0x20]; 2759 2760 u8 reserved_at_40[0x18]; 2761 u8 syndrome[0x8]; 2762 2763 u8 reserved_at_60[0x80]; 2764 }; 2765 2766 struct mlx5_ifc_rdma_page_fault_event_bits { 2767 u8 bytes_committed[0x20]; 2768 2769 u8 r_key[0x20]; 2770 2771 u8 reserved_at_40[0x10]; 2772 u8 packet_len[0x10]; 2773 2774 u8 rdma_op_len[0x20]; 2775 2776 u8 rdma_va[0x40]; 2777 2778 u8 reserved_at_c0[0x5]; 2779 u8 rdma[0x1]; 2780 u8 write[0x1]; 2781 u8 requestor[0x1]; 2782 u8 qp_number[0x18]; 2783 }; 2784 2785 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2786 u8 bytes_committed[0x20]; 2787 2788 u8 reserved_at_20[0x10]; 2789 u8 wqe_index[0x10]; 2790 2791 u8 reserved_at_40[0x10]; 2792 u8 len[0x10]; 2793 2794 u8 reserved_at_60[0x60]; 2795 2796 u8 reserved_at_c0[0x5]; 2797 u8 rdma[0x1]; 2798 u8 write_read[0x1]; 2799 u8 requestor[0x1]; 2800 u8 qpn[0x18]; 2801 }; 2802 2803 struct mlx5_ifc_qp_events_bits { 2804 u8 reserved_at_0[0xa0]; 2805 2806 u8 type[0x8]; 2807 u8 reserved_at_a8[0x18]; 2808 2809 u8 reserved_at_c0[0x8]; 2810 u8 qpn_rqn_sqn[0x18]; 2811 }; 2812 2813 struct mlx5_ifc_dct_events_bits { 2814 u8 reserved_at_0[0xc0]; 2815 2816 u8 reserved_at_c0[0x8]; 2817 u8 dct_number[0x18]; 2818 }; 2819 2820 struct mlx5_ifc_comp_event_bits { 2821 u8 reserved_at_0[0xc0]; 2822 2823 u8 reserved_at_c0[0x8]; 2824 u8 cq_number[0x18]; 2825 }; 2826 2827 enum { 2828 MLX5_QPC_STATE_RST = 0x0, 2829 MLX5_QPC_STATE_INIT = 0x1, 2830 MLX5_QPC_STATE_RTR = 0x2, 2831 MLX5_QPC_STATE_RTS = 0x3, 2832 MLX5_QPC_STATE_SQER = 0x4, 2833 MLX5_QPC_STATE_ERR = 0x6, 2834 MLX5_QPC_STATE_SQD = 0x7, 2835 MLX5_QPC_STATE_SUSPENDED = 0x9, 2836 }; 2837 2838 enum { 2839 MLX5_QPC_ST_RC = 0x0, 2840 MLX5_QPC_ST_UC = 0x1, 2841 MLX5_QPC_ST_UD = 0x2, 2842 MLX5_QPC_ST_XRC = 0x3, 2843 MLX5_QPC_ST_DCI = 0x5, 2844 MLX5_QPC_ST_QP0 = 0x7, 2845 MLX5_QPC_ST_QP1 = 0x8, 2846 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2847 MLX5_QPC_ST_REG_UMR = 0xc, 2848 }; 2849 2850 enum { 2851 MLX5_QPC_PM_STATE_ARMED = 0x0, 2852 MLX5_QPC_PM_STATE_REARM = 0x1, 2853 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2854 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2855 }; 2856 2857 enum { 2858 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2859 }; 2860 2861 enum { 2862 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2863 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2864 }; 2865 2866 enum { 2867 MLX5_QPC_MTU_256_BYTES = 0x1, 2868 MLX5_QPC_MTU_512_BYTES = 0x2, 2869 MLX5_QPC_MTU_1K_BYTES = 0x3, 2870 MLX5_QPC_MTU_2K_BYTES = 0x4, 2871 MLX5_QPC_MTU_4K_BYTES = 0x5, 2872 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2873 }; 2874 2875 enum { 2876 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2877 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2878 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2879 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2880 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2881 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2882 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2883 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2884 }; 2885 2886 enum { 2887 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2888 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2889 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2890 }; 2891 2892 enum { 2893 MLX5_QPC_CS_RES_DISABLE = 0x0, 2894 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2895 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2896 }; 2897 2898 enum { 2899 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2900 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2901 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2902 }; 2903 2904 struct mlx5_ifc_qpc_bits { 2905 u8 state[0x4]; 2906 u8 lag_tx_port_affinity[0x4]; 2907 u8 st[0x8]; 2908 u8 reserved_at_10[0x3]; 2909 u8 pm_state[0x2]; 2910 u8 reserved_at_15[0x1]; 2911 u8 req_e2e_credit_mode[0x2]; 2912 u8 offload_type[0x4]; 2913 u8 end_padding_mode[0x2]; 2914 u8 reserved_at_1e[0x2]; 2915 2916 u8 wq_signature[0x1]; 2917 u8 block_lb_mc[0x1]; 2918 u8 atomic_like_write_en[0x1]; 2919 u8 latency_sensitive[0x1]; 2920 u8 reserved_at_24[0x1]; 2921 u8 drain_sigerr[0x1]; 2922 u8 reserved_at_26[0x2]; 2923 u8 pd[0x18]; 2924 2925 u8 mtu[0x3]; 2926 u8 log_msg_max[0x5]; 2927 u8 reserved_at_48[0x1]; 2928 u8 log_rq_size[0x4]; 2929 u8 log_rq_stride[0x3]; 2930 u8 no_sq[0x1]; 2931 u8 log_sq_size[0x4]; 2932 u8 reserved_at_55[0x3]; 2933 u8 ts_format[0x2]; 2934 u8 reserved_at_5a[0x1]; 2935 u8 rlky[0x1]; 2936 u8 ulp_stateless_offload_mode[0x4]; 2937 2938 u8 counter_set_id[0x8]; 2939 u8 uar_page[0x18]; 2940 2941 u8 reserved_at_80[0x8]; 2942 u8 user_index[0x18]; 2943 2944 u8 reserved_at_a0[0x3]; 2945 u8 log_page_size[0x5]; 2946 u8 remote_qpn[0x18]; 2947 2948 struct mlx5_ifc_ads_bits primary_address_path; 2949 2950 struct mlx5_ifc_ads_bits secondary_address_path; 2951 2952 u8 log_ack_req_freq[0x4]; 2953 u8 reserved_at_384[0x4]; 2954 u8 log_sra_max[0x3]; 2955 u8 reserved_at_38b[0x2]; 2956 u8 retry_count[0x3]; 2957 u8 rnr_retry[0x3]; 2958 u8 reserved_at_393[0x1]; 2959 u8 fre[0x1]; 2960 u8 cur_rnr_retry[0x3]; 2961 u8 cur_retry_count[0x3]; 2962 u8 reserved_at_39b[0x5]; 2963 2964 u8 reserved_at_3a0[0x20]; 2965 2966 u8 reserved_at_3c0[0x8]; 2967 u8 next_send_psn[0x18]; 2968 2969 u8 reserved_at_3e0[0x8]; 2970 u8 cqn_snd[0x18]; 2971 2972 u8 reserved_at_400[0x8]; 2973 u8 deth_sqpn[0x18]; 2974 2975 u8 reserved_at_420[0x20]; 2976 2977 u8 reserved_at_440[0x8]; 2978 u8 last_acked_psn[0x18]; 2979 2980 u8 reserved_at_460[0x8]; 2981 u8 ssn[0x18]; 2982 2983 u8 reserved_at_480[0x8]; 2984 u8 log_rra_max[0x3]; 2985 u8 reserved_at_48b[0x1]; 2986 u8 atomic_mode[0x4]; 2987 u8 rre[0x1]; 2988 u8 rwe[0x1]; 2989 u8 rae[0x1]; 2990 u8 reserved_at_493[0x1]; 2991 u8 page_offset[0x6]; 2992 u8 reserved_at_49a[0x3]; 2993 u8 cd_slave_receive[0x1]; 2994 u8 cd_slave_send[0x1]; 2995 u8 cd_master[0x1]; 2996 2997 u8 reserved_at_4a0[0x3]; 2998 u8 min_rnr_nak[0x5]; 2999 u8 next_rcv_psn[0x18]; 3000 3001 u8 reserved_at_4c0[0x8]; 3002 u8 xrcd[0x18]; 3003 3004 u8 reserved_at_4e0[0x8]; 3005 u8 cqn_rcv[0x18]; 3006 3007 u8 dbr_addr[0x40]; 3008 3009 u8 q_key[0x20]; 3010 3011 u8 reserved_at_560[0x5]; 3012 u8 rq_type[0x3]; 3013 u8 srqn_rmpn_xrqn[0x18]; 3014 3015 u8 reserved_at_580[0x8]; 3016 u8 rmsn[0x18]; 3017 3018 u8 hw_sq_wqebb_counter[0x10]; 3019 u8 sw_sq_wqebb_counter[0x10]; 3020 3021 u8 hw_rq_counter[0x20]; 3022 3023 u8 sw_rq_counter[0x20]; 3024 3025 u8 reserved_at_600[0x20]; 3026 3027 u8 reserved_at_620[0xf]; 3028 u8 cgs[0x1]; 3029 u8 cs_req[0x8]; 3030 u8 cs_res[0x8]; 3031 3032 u8 dc_access_key[0x40]; 3033 3034 u8 reserved_at_680[0x3]; 3035 u8 dbr_umem_valid[0x1]; 3036 3037 u8 reserved_at_684[0xbc]; 3038 }; 3039 3040 struct mlx5_ifc_roce_addr_layout_bits { 3041 u8 source_l3_address[16][0x8]; 3042 3043 u8 reserved_at_80[0x3]; 3044 u8 vlan_valid[0x1]; 3045 u8 vlan_id[0xc]; 3046 u8 source_mac_47_32[0x10]; 3047 3048 u8 source_mac_31_0[0x20]; 3049 3050 u8 reserved_at_c0[0x14]; 3051 u8 roce_l3_type[0x4]; 3052 u8 roce_version[0x8]; 3053 3054 u8 reserved_at_e0[0x20]; 3055 }; 3056 3057 union mlx5_ifc_hca_cap_union_bits { 3058 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3059 struct mlx5_ifc_odp_cap_bits odp_cap; 3060 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3061 struct mlx5_ifc_roce_cap_bits roce_cap; 3062 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3063 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3064 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3065 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3066 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3067 struct mlx5_ifc_qos_cap_bits qos_cap; 3068 struct mlx5_ifc_debug_cap_bits debug_cap; 3069 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3070 struct mlx5_ifc_tls_cap_bits tls_cap; 3071 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3072 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3073 u8 reserved_at_0[0x8000]; 3074 }; 3075 3076 enum { 3077 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3078 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3079 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3080 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3081 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3082 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3083 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3084 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3085 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3086 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3087 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3088 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3089 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3090 }; 3091 3092 enum { 3093 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3094 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3095 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3096 }; 3097 3098 struct mlx5_ifc_vlan_bits { 3099 u8 ethtype[0x10]; 3100 u8 prio[0x3]; 3101 u8 cfi[0x1]; 3102 u8 vid[0xc]; 3103 }; 3104 3105 struct mlx5_ifc_flow_context_bits { 3106 struct mlx5_ifc_vlan_bits push_vlan; 3107 3108 u8 group_id[0x20]; 3109 3110 u8 reserved_at_40[0x8]; 3111 u8 flow_tag[0x18]; 3112 3113 u8 reserved_at_60[0x10]; 3114 u8 action[0x10]; 3115 3116 u8 extended_destination[0x1]; 3117 u8 reserved_at_81[0x1]; 3118 u8 flow_source[0x2]; 3119 u8 reserved_at_84[0x4]; 3120 u8 destination_list_size[0x18]; 3121 3122 u8 reserved_at_a0[0x8]; 3123 u8 flow_counter_list_size[0x18]; 3124 3125 u8 packet_reformat_id[0x20]; 3126 3127 u8 modify_header_id[0x20]; 3128 3129 struct mlx5_ifc_vlan_bits push_vlan_2; 3130 3131 u8 ipsec_obj_id[0x20]; 3132 u8 reserved_at_140[0xc0]; 3133 3134 struct mlx5_ifc_fte_match_param_bits match_value; 3135 3136 u8 reserved_at_1200[0x600]; 3137 3138 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3139 }; 3140 3141 enum { 3142 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3143 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3144 }; 3145 3146 struct mlx5_ifc_xrc_srqc_bits { 3147 u8 state[0x4]; 3148 u8 log_xrc_srq_size[0x4]; 3149 u8 reserved_at_8[0x18]; 3150 3151 u8 wq_signature[0x1]; 3152 u8 cont_srq[0x1]; 3153 u8 reserved_at_22[0x1]; 3154 u8 rlky[0x1]; 3155 u8 basic_cyclic_rcv_wqe[0x1]; 3156 u8 log_rq_stride[0x3]; 3157 u8 xrcd[0x18]; 3158 3159 u8 page_offset[0x6]; 3160 u8 reserved_at_46[0x1]; 3161 u8 dbr_umem_valid[0x1]; 3162 u8 cqn[0x18]; 3163 3164 u8 reserved_at_60[0x20]; 3165 3166 u8 user_index_equal_xrc_srqn[0x1]; 3167 u8 reserved_at_81[0x1]; 3168 u8 log_page_size[0x6]; 3169 u8 user_index[0x18]; 3170 3171 u8 reserved_at_a0[0x20]; 3172 3173 u8 reserved_at_c0[0x8]; 3174 u8 pd[0x18]; 3175 3176 u8 lwm[0x10]; 3177 u8 wqe_cnt[0x10]; 3178 3179 u8 reserved_at_100[0x40]; 3180 3181 u8 db_record_addr_h[0x20]; 3182 3183 u8 db_record_addr_l[0x1e]; 3184 u8 reserved_at_17e[0x2]; 3185 3186 u8 reserved_at_180[0x80]; 3187 }; 3188 3189 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3190 u8 counter_error_queues[0x20]; 3191 3192 u8 total_error_queues[0x20]; 3193 3194 u8 send_queue_priority_update_flow[0x20]; 3195 3196 u8 reserved_at_60[0x20]; 3197 3198 u8 nic_receive_steering_discard[0x40]; 3199 3200 u8 receive_discard_vport_down[0x40]; 3201 3202 u8 transmit_discard_vport_down[0x40]; 3203 3204 u8 reserved_at_140[0xa0]; 3205 3206 u8 internal_rq_out_of_buffer[0x20]; 3207 3208 u8 reserved_at_200[0xe00]; 3209 }; 3210 3211 struct mlx5_ifc_traffic_counter_bits { 3212 u8 packets[0x40]; 3213 3214 u8 octets[0x40]; 3215 }; 3216 3217 struct mlx5_ifc_tisc_bits { 3218 u8 strict_lag_tx_port_affinity[0x1]; 3219 u8 tls_en[0x1]; 3220 u8 reserved_at_2[0x2]; 3221 u8 lag_tx_port_affinity[0x04]; 3222 3223 u8 reserved_at_8[0x4]; 3224 u8 prio[0x4]; 3225 u8 reserved_at_10[0x10]; 3226 3227 u8 reserved_at_20[0x100]; 3228 3229 u8 reserved_at_120[0x8]; 3230 u8 transport_domain[0x18]; 3231 3232 u8 reserved_at_140[0x8]; 3233 u8 underlay_qpn[0x18]; 3234 3235 u8 reserved_at_160[0x8]; 3236 u8 pd[0x18]; 3237 3238 u8 reserved_at_180[0x380]; 3239 }; 3240 3241 enum { 3242 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3243 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3244 }; 3245 3246 enum { 3247 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3248 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3249 }; 3250 3251 enum { 3252 MLX5_RX_HASH_FN_NONE = 0x0, 3253 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3254 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3255 }; 3256 3257 enum { 3258 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3259 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3260 }; 3261 3262 struct mlx5_ifc_tirc_bits { 3263 u8 reserved_at_0[0x20]; 3264 3265 u8 disp_type[0x4]; 3266 u8 tls_en[0x1]; 3267 u8 reserved_at_25[0x1b]; 3268 3269 u8 reserved_at_40[0x40]; 3270 3271 u8 reserved_at_80[0x4]; 3272 u8 lro_timeout_period_usecs[0x10]; 3273 u8 lro_enable_mask[0x4]; 3274 u8 lro_max_ip_payload_size[0x8]; 3275 3276 u8 reserved_at_a0[0x40]; 3277 3278 u8 reserved_at_e0[0x8]; 3279 u8 inline_rqn[0x18]; 3280 3281 u8 rx_hash_symmetric[0x1]; 3282 u8 reserved_at_101[0x1]; 3283 u8 tunneled_offload_en[0x1]; 3284 u8 reserved_at_103[0x5]; 3285 u8 indirect_table[0x18]; 3286 3287 u8 rx_hash_fn[0x4]; 3288 u8 reserved_at_124[0x2]; 3289 u8 self_lb_block[0x2]; 3290 u8 transport_domain[0x18]; 3291 3292 u8 rx_hash_toeplitz_key[10][0x20]; 3293 3294 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3295 3296 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3297 3298 u8 reserved_at_2c0[0x4c0]; 3299 }; 3300 3301 enum { 3302 MLX5_SRQC_STATE_GOOD = 0x0, 3303 MLX5_SRQC_STATE_ERROR = 0x1, 3304 }; 3305 3306 struct mlx5_ifc_srqc_bits { 3307 u8 state[0x4]; 3308 u8 log_srq_size[0x4]; 3309 u8 reserved_at_8[0x18]; 3310 3311 u8 wq_signature[0x1]; 3312 u8 cont_srq[0x1]; 3313 u8 reserved_at_22[0x1]; 3314 u8 rlky[0x1]; 3315 u8 reserved_at_24[0x1]; 3316 u8 log_rq_stride[0x3]; 3317 u8 xrcd[0x18]; 3318 3319 u8 page_offset[0x6]; 3320 u8 reserved_at_46[0x2]; 3321 u8 cqn[0x18]; 3322 3323 u8 reserved_at_60[0x20]; 3324 3325 u8 reserved_at_80[0x2]; 3326 u8 log_page_size[0x6]; 3327 u8 reserved_at_88[0x18]; 3328 3329 u8 reserved_at_a0[0x20]; 3330 3331 u8 reserved_at_c0[0x8]; 3332 u8 pd[0x18]; 3333 3334 u8 lwm[0x10]; 3335 u8 wqe_cnt[0x10]; 3336 3337 u8 reserved_at_100[0x40]; 3338 3339 u8 dbr_addr[0x40]; 3340 3341 u8 reserved_at_180[0x80]; 3342 }; 3343 3344 enum { 3345 MLX5_SQC_STATE_RST = 0x0, 3346 MLX5_SQC_STATE_RDY = 0x1, 3347 MLX5_SQC_STATE_ERR = 0x3, 3348 }; 3349 3350 enum { 3351 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3352 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3353 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3354 }; 3355 3356 struct mlx5_ifc_sqc_bits { 3357 u8 rlky[0x1]; 3358 u8 cd_master[0x1]; 3359 u8 fre[0x1]; 3360 u8 flush_in_error_en[0x1]; 3361 u8 allow_multi_pkt_send_wqe[0x1]; 3362 u8 min_wqe_inline_mode[0x3]; 3363 u8 state[0x4]; 3364 u8 reg_umr[0x1]; 3365 u8 allow_swp[0x1]; 3366 u8 hairpin[0x1]; 3367 u8 reserved_at_f[0xb]; 3368 u8 ts_format[0x2]; 3369 u8 reserved_at_1c[0x4]; 3370 3371 u8 reserved_at_20[0x8]; 3372 u8 user_index[0x18]; 3373 3374 u8 reserved_at_40[0x8]; 3375 u8 cqn[0x18]; 3376 3377 u8 reserved_at_60[0x8]; 3378 u8 hairpin_peer_rq[0x18]; 3379 3380 u8 reserved_at_80[0x10]; 3381 u8 hairpin_peer_vhca[0x10]; 3382 3383 u8 reserved_at_a0[0x20]; 3384 3385 u8 reserved_at_c0[0x8]; 3386 u8 ts_cqe_to_dest_cqn[0x18]; 3387 3388 u8 reserved_at_e0[0x10]; 3389 u8 packet_pacing_rate_limit_index[0x10]; 3390 u8 tis_lst_sz[0x10]; 3391 u8 qos_queue_group_id[0x10]; 3392 3393 u8 reserved_at_120[0x40]; 3394 3395 u8 reserved_at_160[0x8]; 3396 u8 tis_num_0[0x18]; 3397 3398 struct mlx5_ifc_wq_bits wq; 3399 }; 3400 3401 enum { 3402 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3403 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3404 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3405 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3406 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3407 }; 3408 3409 enum { 3410 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3411 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3412 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3413 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3414 }; 3415 3416 struct mlx5_ifc_scheduling_context_bits { 3417 u8 element_type[0x8]; 3418 u8 reserved_at_8[0x18]; 3419 3420 u8 element_attributes[0x20]; 3421 3422 u8 parent_element_id[0x20]; 3423 3424 u8 reserved_at_60[0x40]; 3425 3426 u8 bw_share[0x20]; 3427 3428 u8 max_average_bw[0x20]; 3429 3430 u8 reserved_at_e0[0x120]; 3431 }; 3432 3433 struct mlx5_ifc_rqtc_bits { 3434 u8 reserved_at_0[0xa0]; 3435 3436 u8 reserved_at_a0[0x5]; 3437 u8 list_q_type[0x3]; 3438 u8 reserved_at_a8[0x8]; 3439 u8 rqt_max_size[0x10]; 3440 3441 u8 rq_vhca_id_format[0x1]; 3442 u8 reserved_at_c1[0xf]; 3443 u8 rqt_actual_size[0x10]; 3444 3445 u8 reserved_at_e0[0x6a0]; 3446 3447 struct mlx5_ifc_rq_num_bits rq_num[]; 3448 }; 3449 3450 enum { 3451 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3452 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3453 }; 3454 3455 enum { 3456 MLX5_RQC_STATE_RST = 0x0, 3457 MLX5_RQC_STATE_RDY = 0x1, 3458 MLX5_RQC_STATE_ERR = 0x3, 3459 }; 3460 3461 enum { 3462 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3463 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3464 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3465 }; 3466 3467 struct mlx5_ifc_rqc_bits { 3468 u8 rlky[0x1]; 3469 u8 delay_drop_en[0x1]; 3470 u8 scatter_fcs[0x1]; 3471 u8 vsd[0x1]; 3472 u8 mem_rq_type[0x4]; 3473 u8 state[0x4]; 3474 u8 reserved_at_c[0x1]; 3475 u8 flush_in_error_en[0x1]; 3476 u8 hairpin[0x1]; 3477 u8 reserved_at_f[0xb]; 3478 u8 ts_format[0x2]; 3479 u8 reserved_at_1c[0x4]; 3480 3481 u8 reserved_at_20[0x8]; 3482 u8 user_index[0x18]; 3483 3484 u8 reserved_at_40[0x8]; 3485 u8 cqn[0x18]; 3486 3487 u8 counter_set_id[0x8]; 3488 u8 reserved_at_68[0x18]; 3489 3490 u8 reserved_at_80[0x8]; 3491 u8 rmpn[0x18]; 3492 3493 u8 reserved_at_a0[0x8]; 3494 u8 hairpin_peer_sq[0x18]; 3495 3496 u8 reserved_at_c0[0x10]; 3497 u8 hairpin_peer_vhca[0x10]; 3498 3499 u8 reserved_at_e0[0xa0]; 3500 3501 struct mlx5_ifc_wq_bits wq; 3502 }; 3503 3504 enum { 3505 MLX5_RMPC_STATE_RDY = 0x1, 3506 MLX5_RMPC_STATE_ERR = 0x3, 3507 }; 3508 3509 struct mlx5_ifc_rmpc_bits { 3510 u8 reserved_at_0[0x8]; 3511 u8 state[0x4]; 3512 u8 reserved_at_c[0x14]; 3513 3514 u8 basic_cyclic_rcv_wqe[0x1]; 3515 u8 reserved_at_21[0x1f]; 3516 3517 u8 reserved_at_40[0x140]; 3518 3519 struct mlx5_ifc_wq_bits wq; 3520 }; 3521 3522 struct mlx5_ifc_nic_vport_context_bits { 3523 u8 reserved_at_0[0x5]; 3524 u8 min_wqe_inline_mode[0x3]; 3525 u8 reserved_at_8[0x15]; 3526 u8 disable_mc_local_lb[0x1]; 3527 u8 disable_uc_local_lb[0x1]; 3528 u8 roce_en[0x1]; 3529 3530 u8 arm_change_event[0x1]; 3531 u8 reserved_at_21[0x1a]; 3532 u8 event_on_mtu[0x1]; 3533 u8 event_on_promisc_change[0x1]; 3534 u8 event_on_vlan_change[0x1]; 3535 u8 event_on_mc_address_change[0x1]; 3536 u8 event_on_uc_address_change[0x1]; 3537 3538 u8 reserved_at_40[0xc]; 3539 3540 u8 affiliation_criteria[0x4]; 3541 u8 affiliated_vhca_id[0x10]; 3542 3543 u8 reserved_at_60[0xd0]; 3544 3545 u8 mtu[0x10]; 3546 3547 u8 system_image_guid[0x40]; 3548 u8 port_guid[0x40]; 3549 u8 node_guid[0x40]; 3550 3551 u8 reserved_at_200[0x140]; 3552 u8 qkey_violation_counter[0x10]; 3553 u8 reserved_at_350[0x430]; 3554 3555 u8 promisc_uc[0x1]; 3556 u8 promisc_mc[0x1]; 3557 u8 promisc_all[0x1]; 3558 u8 reserved_at_783[0x2]; 3559 u8 allowed_list_type[0x3]; 3560 u8 reserved_at_788[0xc]; 3561 u8 allowed_list_size[0xc]; 3562 3563 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3564 3565 u8 reserved_at_7e0[0x20]; 3566 3567 u8 current_uc_mac_address[][0x40]; 3568 }; 3569 3570 enum { 3571 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3572 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3573 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3574 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3575 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3576 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3577 }; 3578 3579 struct mlx5_ifc_mkc_bits { 3580 u8 reserved_at_0[0x1]; 3581 u8 free[0x1]; 3582 u8 reserved_at_2[0x1]; 3583 u8 access_mode_4_2[0x3]; 3584 u8 reserved_at_6[0x7]; 3585 u8 relaxed_ordering_write[0x1]; 3586 u8 reserved_at_e[0x1]; 3587 u8 small_fence_on_rdma_read_response[0x1]; 3588 u8 umr_en[0x1]; 3589 u8 a[0x1]; 3590 u8 rw[0x1]; 3591 u8 rr[0x1]; 3592 u8 lw[0x1]; 3593 u8 lr[0x1]; 3594 u8 access_mode_1_0[0x2]; 3595 u8 reserved_at_18[0x8]; 3596 3597 u8 qpn[0x18]; 3598 u8 mkey_7_0[0x8]; 3599 3600 u8 reserved_at_40[0x20]; 3601 3602 u8 length64[0x1]; 3603 u8 bsf_en[0x1]; 3604 u8 sync_umr[0x1]; 3605 u8 reserved_at_63[0x2]; 3606 u8 expected_sigerr_count[0x1]; 3607 u8 reserved_at_66[0x1]; 3608 u8 en_rinval[0x1]; 3609 u8 pd[0x18]; 3610 3611 u8 start_addr[0x40]; 3612 3613 u8 len[0x40]; 3614 3615 u8 bsf_octword_size[0x20]; 3616 3617 u8 reserved_at_120[0x80]; 3618 3619 u8 translations_octword_size[0x20]; 3620 3621 u8 reserved_at_1c0[0x19]; 3622 u8 relaxed_ordering_read[0x1]; 3623 u8 reserved_at_1d9[0x1]; 3624 u8 log_page_size[0x5]; 3625 3626 u8 reserved_at_1e0[0x20]; 3627 }; 3628 3629 struct mlx5_ifc_pkey_bits { 3630 u8 reserved_at_0[0x10]; 3631 u8 pkey[0x10]; 3632 }; 3633 3634 struct mlx5_ifc_array128_auto_bits { 3635 u8 array128_auto[16][0x8]; 3636 }; 3637 3638 struct mlx5_ifc_hca_vport_context_bits { 3639 u8 field_select[0x20]; 3640 3641 u8 reserved_at_20[0xe0]; 3642 3643 u8 sm_virt_aware[0x1]; 3644 u8 has_smi[0x1]; 3645 u8 has_raw[0x1]; 3646 u8 grh_required[0x1]; 3647 u8 reserved_at_104[0xc]; 3648 u8 port_physical_state[0x4]; 3649 u8 vport_state_policy[0x4]; 3650 u8 port_state[0x4]; 3651 u8 vport_state[0x4]; 3652 3653 u8 reserved_at_120[0x20]; 3654 3655 u8 system_image_guid[0x40]; 3656 3657 u8 port_guid[0x40]; 3658 3659 u8 node_guid[0x40]; 3660 3661 u8 cap_mask1[0x20]; 3662 3663 u8 cap_mask1_field_select[0x20]; 3664 3665 u8 cap_mask2[0x20]; 3666 3667 u8 cap_mask2_field_select[0x20]; 3668 3669 u8 reserved_at_280[0x80]; 3670 3671 u8 lid[0x10]; 3672 u8 reserved_at_310[0x4]; 3673 u8 init_type_reply[0x4]; 3674 u8 lmc[0x3]; 3675 u8 subnet_timeout[0x5]; 3676 3677 u8 sm_lid[0x10]; 3678 u8 sm_sl[0x4]; 3679 u8 reserved_at_334[0xc]; 3680 3681 u8 qkey_violation_counter[0x10]; 3682 u8 pkey_violation_counter[0x10]; 3683 3684 u8 reserved_at_360[0xca0]; 3685 }; 3686 3687 struct mlx5_ifc_esw_vport_context_bits { 3688 u8 fdb_to_vport_reg_c[0x1]; 3689 u8 reserved_at_1[0x2]; 3690 u8 vport_svlan_strip[0x1]; 3691 u8 vport_cvlan_strip[0x1]; 3692 u8 vport_svlan_insert[0x1]; 3693 u8 vport_cvlan_insert[0x2]; 3694 u8 fdb_to_vport_reg_c_id[0x8]; 3695 u8 reserved_at_10[0x10]; 3696 3697 u8 reserved_at_20[0x20]; 3698 3699 u8 svlan_cfi[0x1]; 3700 u8 svlan_pcp[0x3]; 3701 u8 svlan_id[0xc]; 3702 u8 cvlan_cfi[0x1]; 3703 u8 cvlan_pcp[0x3]; 3704 u8 cvlan_id[0xc]; 3705 3706 u8 reserved_at_60[0x720]; 3707 3708 u8 sw_steering_vport_icm_address_rx[0x40]; 3709 3710 u8 sw_steering_vport_icm_address_tx[0x40]; 3711 }; 3712 3713 enum { 3714 MLX5_EQC_STATUS_OK = 0x0, 3715 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3716 }; 3717 3718 enum { 3719 MLX5_EQC_ST_ARMED = 0x9, 3720 MLX5_EQC_ST_FIRED = 0xa, 3721 }; 3722 3723 struct mlx5_ifc_eqc_bits { 3724 u8 status[0x4]; 3725 u8 reserved_at_4[0x9]; 3726 u8 ec[0x1]; 3727 u8 oi[0x1]; 3728 u8 reserved_at_f[0x5]; 3729 u8 st[0x4]; 3730 u8 reserved_at_18[0x8]; 3731 3732 u8 reserved_at_20[0x20]; 3733 3734 u8 reserved_at_40[0x14]; 3735 u8 page_offset[0x6]; 3736 u8 reserved_at_5a[0x6]; 3737 3738 u8 reserved_at_60[0x3]; 3739 u8 log_eq_size[0x5]; 3740 u8 uar_page[0x18]; 3741 3742 u8 reserved_at_80[0x20]; 3743 3744 u8 reserved_at_a0[0x18]; 3745 u8 intr[0x8]; 3746 3747 u8 reserved_at_c0[0x3]; 3748 u8 log_page_size[0x5]; 3749 u8 reserved_at_c8[0x18]; 3750 3751 u8 reserved_at_e0[0x60]; 3752 3753 u8 reserved_at_140[0x8]; 3754 u8 consumer_counter[0x18]; 3755 3756 u8 reserved_at_160[0x8]; 3757 u8 producer_counter[0x18]; 3758 3759 u8 reserved_at_180[0x80]; 3760 }; 3761 3762 enum { 3763 MLX5_DCTC_STATE_ACTIVE = 0x0, 3764 MLX5_DCTC_STATE_DRAINING = 0x1, 3765 MLX5_DCTC_STATE_DRAINED = 0x2, 3766 }; 3767 3768 enum { 3769 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3770 MLX5_DCTC_CS_RES_NA = 0x1, 3771 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3772 }; 3773 3774 enum { 3775 MLX5_DCTC_MTU_256_BYTES = 0x1, 3776 MLX5_DCTC_MTU_512_BYTES = 0x2, 3777 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3778 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3779 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3780 }; 3781 3782 struct mlx5_ifc_dctc_bits { 3783 u8 reserved_at_0[0x4]; 3784 u8 state[0x4]; 3785 u8 reserved_at_8[0x18]; 3786 3787 u8 reserved_at_20[0x8]; 3788 u8 user_index[0x18]; 3789 3790 u8 reserved_at_40[0x8]; 3791 u8 cqn[0x18]; 3792 3793 u8 counter_set_id[0x8]; 3794 u8 atomic_mode[0x4]; 3795 u8 rre[0x1]; 3796 u8 rwe[0x1]; 3797 u8 rae[0x1]; 3798 u8 atomic_like_write_en[0x1]; 3799 u8 latency_sensitive[0x1]; 3800 u8 rlky[0x1]; 3801 u8 free_ar[0x1]; 3802 u8 reserved_at_73[0xd]; 3803 3804 u8 reserved_at_80[0x8]; 3805 u8 cs_res[0x8]; 3806 u8 reserved_at_90[0x3]; 3807 u8 min_rnr_nak[0x5]; 3808 u8 reserved_at_98[0x8]; 3809 3810 u8 reserved_at_a0[0x8]; 3811 u8 srqn_xrqn[0x18]; 3812 3813 u8 reserved_at_c0[0x8]; 3814 u8 pd[0x18]; 3815 3816 u8 tclass[0x8]; 3817 u8 reserved_at_e8[0x4]; 3818 u8 flow_label[0x14]; 3819 3820 u8 dc_access_key[0x40]; 3821 3822 u8 reserved_at_140[0x5]; 3823 u8 mtu[0x3]; 3824 u8 port[0x8]; 3825 u8 pkey_index[0x10]; 3826 3827 u8 reserved_at_160[0x8]; 3828 u8 my_addr_index[0x8]; 3829 u8 reserved_at_170[0x8]; 3830 u8 hop_limit[0x8]; 3831 3832 u8 dc_access_key_violation_count[0x20]; 3833 3834 u8 reserved_at_1a0[0x14]; 3835 u8 dei_cfi[0x1]; 3836 u8 eth_prio[0x3]; 3837 u8 ecn[0x2]; 3838 u8 dscp[0x6]; 3839 3840 u8 reserved_at_1c0[0x20]; 3841 u8 ece[0x20]; 3842 }; 3843 3844 enum { 3845 MLX5_CQC_STATUS_OK = 0x0, 3846 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3847 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3848 }; 3849 3850 enum { 3851 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3852 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3853 }; 3854 3855 enum { 3856 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3857 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3858 MLX5_CQC_ST_FIRED = 0xa, 3859 }; 3860 3861 enum { 3862 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3863 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3864 MLX5_CQ_PERIOD_NUM_MODES 3865 }; 3866 3867 struct mlx5_ifc_cqc_bits { 3868 u8 status[0x4]; 3869 u8 reserved_at_4[0x2]; 3870 u8 dbr_umem_valid[0x1]; 3871 u8 reserved_at_7[0x1]; 3872 u8 cqe_sz[0x3]; 3873 u8 cc[0x1]; 3874 u8 reserved_at_c[0x1]; 3875 u8 scqe_break_moderation_en[0x1]; 3876 u8 oi[0x1]; 3877 u8 cq_period_mode[0x2]; 3878 u8 cqe_comp_en[0x1]; 3879 u8 mini_cqe_res_format[0x2]; 3880 u8 st[0x4]; 3881 u8 reserved_at_18[0x8]; 3882 3883 u8 reserved_at_20[0x20]; 3884 3885 u8 reserved_at_40[0x14]; 3886 u8 page_offset[0x6]; 3887 u8 reserved_at_5a[0x6]; 3888 3889 u8 reserved_at_60[0x3]; 3890 u8 log_cq_size[0x5]; 3891 u8 uar_page[0x18]; 3892 3893 u8 reserved_at_80[0x4]; 3894 u8 cq_period[0xc]; 3895 u8 cq_max_count[0x10]; 3896 3897 u8 reserved_at_a0[0x18]; 3898 u8 c_eqn[0x8]; 3899 3900 u8 reserved_at_c0[0x3]; 3901 u8 log_page_size[0x5]; 3902 u8 reserved_at_c8[0x18]; 3903 3904 u8 reserved_at_e0[0x20]; 3905 3906 u8 reserved_at_100[0x8]; 3907 u8 last_notified_index[0x18]; 3908 3909 u8 reserved_at_120[0x8]; 3910 u8 last_solicit_index[0x18]; 3911 3912 u8 reserved_at_140[0x8]; 3913 u8 consumer_counter[0x18]; 3914 3915 u8 reserved_at_160[0x8]; 3916 u8 producer_counter[0x18]; 3917 3918 u8 reserved_at_180[0x40]; 3919 3920 u8 dbr_addr[0x40]; 3921 }; 3922 3923 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3924 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3925 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3926 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3927 u8 reserved_at_0[0x800]; 3928 }; 3929 3930 struct mlx5_ifc_query_adapter_param_block_bits { 3931 u8 reserved_at_0[0xc0]; 3932 3933 u8 reserved_at_c0[0x8]; 3934 u8 ieee_vendor_id[0x18]; 3935 3936 u8 reserved_at_e0[0x10]; 3937 u8 vsd_vendor_id[0x10]; 3938 3939 u8 vsd[208][0x8]; 3940 3941 u8 vsd_contd_psid[16][0x8]; 3942 }; 3943 3944 enum { 3945 MLX5_XRQC_STATE_GOOD = 0x0, 3946 MLX5_XRQC_STATE_ERROR = 0x1, 3947 }; 3948 3949 enum { 3950 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3951 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3952 }; 3953 3954 enum { 3955 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3956 }; 3957 3958 struct mlx5_ifc_tag_matching_topology_context_bits { 3959 u8 log_matching_list_sz[0x4]; 3960 u8 reserved_at_4[0xc]; 3961 u8 append_next_index[0x10]; 3962 3963 u8 sw_phase_cnt[0x10]; 3964 u8 hw_phase_cnt[0x10]; 3965 3966 u8 reserved_at_40[0x40]; 3967 }; 3968 3969 struct mlx5_ifc_xrqc_bits { 3970 u8 state[0x4]; 3971 u8 rlkey[0x1]; 3972 u8 reserved_at_5[0xf]; 3973 u8 topology[0x4]; 3974 u8 reserved_at_18[0x4]; 3975 u8 offload[0x4]; 3976 3977 u8 reserved_at_20[0x8]; 3978 u8 user_index[0x18]; 3979 3980 u8 reserved_at_40[0x8]; 3981 u8 cqn[0x18]; 3982 3983 u8 reserved_at_60[0xa0]; 3984 3985 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3986 3987 u8 reserved_at_180[0x280]; 3988 3989 struct mlx5_ifc_wq_bits wq; 3990 }; 3991 3992 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3993 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3994 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3995 u8 reserved_at_0[0x20]; 3996 }; 3997 3998 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3999 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4000 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4001 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4002 u8 reserved_at_0[0x20]; 4003 }; 4004 4005 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4006 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4007 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4008 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4009 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4010 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4011 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4012 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4013 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4014 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4015 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4016 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4017 u8 reserved_at_0[0x7c0]; 4018 }; 4019 4020 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4021 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4022 u8 reserved_at_0[0x7c0]; 4023 }; 4024 4025 union mlx5_ifc_event_auto_bits { 4026 struct mlx5_ifc_comp_event_bits comp_event; 4027 struct mlx5_ifc_dct_events_bits dct_events; 4028 struct mlx5_ifc_qp_events_bits qp_events; 4029 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4030 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4031 struct mlx5_ifc_cq_error_bits cq_error; 4032 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4033 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4034 struct mlx5_ifc_gpio_event_bits gpio_event; 4035 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4036 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4037 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4038 u8 reserved_at_0[0xe0]; 4039 }; 4040 4041 struct mlx5_ifc_health_buffer_bits { 4042 u8 reserved_at_0[0x100]; 4043 4044 u8 assert_existptr[0x20]; 4045 4046 u8 assert_callra[0x20]; 4047 4048 u8 reserved_at_140[0x40]; 4049 4050 u8 fw_version[0x20]; 4051 4052 u8 hw_id[0x20]; 4053 4054 u8 reserved_at_1c0[0x20]; 4055 4056 u8 irisc_index[0x8]; 4057 u8 synd[0x8]; 4058 u8 ext_synd[0x10]; 4059 }; 4060 4061 struct mlx5_ifc_register_loopback_control_bits { 4062 u8 no_lb[0x1]; 4063 u8 reserved_at_1[0x7]; 4064 u8 port[0x8]; 4065 u8 reserved_at_10[0x10]; 4066 4067 u8 reserved_at_20[0x60]; 4068 }; 4069 4070 struct mlx5_ifc_vport_tc_element_bits { 4071 u8 traffic_class[0x4]; 4072 u8 reserved_at_4[0xc]; 4073 u8 vport_number[0x10]; 4074 }; 4075 4076 struct mlx5_ifc_vport_element_bits { 4077 u8 reserved_at_0[0x10]; 4078 u8 vport_number[0x10]; 4079 }; 4080 4081 enum { 4082 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4083 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4084 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4085 }; 4086 4087 struct mlx5_ifc_tsar_element_bits { 4088 u8 reserved_at_0[0x8]; 4089 u8 tsar_type[0x8]; 4090 u8 reserved_at_10[0x10]; 4091 }; 4092 4093 enum { 4094 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4095 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4096 }; 4097 4098 struct mlx5_ifc_teardown_hca_out_bits { 4099 u8 status[0x8]; 4100 u8 reserved_at_8[0x18]; 4101 4102 u8 syndrome[0x20]; 4103 4104 u8 reserved_at_40[0x3f]; 4105 4106 u8 state[0x1]; 4107 }; 4108 4109 enum { 4110 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4111 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4112 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4113 }; 4114 4115 struct mlx5_ifc_teardown_hca_in_bits { 4116 u8 opcode[0x10]; 4117 u8 reserved_at_10[0x10]; 4118 4119 u8 reserved_at_20[0x10]; 4120 u8 op_mod[0x10]; 4121 4122 u8 reserved_at_40[0x10]; 4123 u8 profile[0x10]; 4124 4125 u8 reserved_at_60[0x20]; 4126 }; 4127 4128 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4129 u8 status[0x8]; 4130 u8 reserved_at_8[0x18]; 4131 4132 u8 syndrome[0x20]; 4133 4134 u8 reserved_at_40[0x40]; 4135 }; 4136 4137 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4138 u8 opcode[0x10]; 4139 u8 uid[0x10]; 4140 4141 u8 reserved_at_20[0x10]; 4142 u8 op_mod[0x10]; 4143 4144 u8 reserved_at_40[0x8]; 4145 u8 qpn[0x18]; 4146 4147 u8 reserved_at_60[0x20]; 4148 4149 u8 opt_param_mask[0x20]; 4150 4151 u8 reserved_at_a0[0x20]; 4152 4153 struct mlx5_ifc_qpc_bits qpc; 4154 4155 u8 reserved_at_800[0x80]; 4156 }; 4157 4158 struct mlx5_ifc_sqd2rts_qp_out_bits { 4159 u8 status[0x8]; 4160 u8 reserved_at_8[0x18]; 4161 4162 u8 syndrome[0x20]; 4163 4164 u8 reserved_at_40[0x40]; 4165 }; 4166 4167 struct mlx5_ifc_sqd2rts_qp_in_bits { 4168 u8 opcode[0x10]; 4169 u8 uid[0x10]; 4170 4171 u8 reserved_at_20[0x10]; 4172 u8 op_mod[0x10]; 4173 4174 u8 reserved_at_40[0x8]; 4175 u8 qpn[0x18]; 4176 4177 u8 reserved_at_60[0x20]; 4178 4179 u8 opt_param_mask[0x20]; 4180 4181 u8 reserved_at_a0[0x20]; 4182 4183 struct mlx5_ifc_qpc_bits qpc; 4184 4185 u8 reserved_at_800[0x80]; 4186 }; 4187 4188 struct mlx5_ifc_set_roce_address_out_bits { 4189 u8 status[0x8]; 4190 u8 reserved_at_8[0x18]; 4191 4192 u8 syndrome[0x20]; 4193 4194 u8 reserved_at_40[0x40]; 4195 }; 4196 4197 struct mlx5_ifc_set_roce_address_in_bits { 4198 u8 opcode[0x10]; 4199 u8 reserved_at_10[0x10]; 4200 4201 u8 reserved_at_20[0x10]; 4202 u8 op_mod[0x10]; 4203 4204 u8 roce_address_index[0x10]; 4205 u8 reserved_at_50[0xc]; 4206 u8 vhca_port_num[0x4]; 4207 4208 u8 reserved_at_60[0x20]; 4209 4210 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4211 }; 4212 4213 struct mlx5_ifc_set_mad_demux_out_bits { 4214 u8 status[0x8]; 4215 u8 reserved_at_8[0x18]; 4216 4217 u8 syndrome[0x20]; 4218 4219 u8 reserved_at_40[0x40]; 4220 }; 4221 4222 enum { 4223 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4224 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4225 }; 4226 4227 struct mlx5_ifc_set_mad_demux_in_bits { 4228 u8 opcode[0x10]; 4229 u8 reserved_at_10[0x10]; 4230 4231 u8 reserved_at_20[0x10]; 4232 u8 op_mod[0x10]; 4233 4234 u8 reserved_at_40[0x20]; 4235 4236 u8 reserved_at_60[0x6]; 4237 u8 demux_mode[0x2]; 4238 u8 reserved_at_68[0x18]; 4239 }; 4240 4241 struct mlx5_ifc_set_l2_table_entry_out_bits { 4242 u8 status[0x8]; 4243 u8 reserved_at_8[0x18]; 4244 4245 u8 syndrome[0x20]; 4246 4247 u8 reserved_at_40[0x40]; 4248 }; 4249 4250 struct mlx5_ifc_set_l2_table_entry_in_bits { 4251 u8 opcode[0x10]; 4252 u8 reserved_at_10[0x10]; 4253 4254 u8 reserved_at_20[0x10]; 4255 u8 op_mod[0x10]; 4256 4257 u8 reserved_at_40[0x60]; 4258 4259 u8 reserved_at_a0[0x8]; 4260 u8 table_index[0x18]; 4261 4262 u8 reserved_at_c0[0x20]; 4263 4264 u8 reserved_at_e0[0x13]; 4265 u8 vlan_valid[0x1]; 4266 u8 vlan[0xc]; 4267 4268 struct mlx5_ifc_mac_address_layout_bits mac_address; 4269 4270 u8 reserved_at_140[0xc0]; 4271 }; 4272 4273 struct mlx5_ifc_set_issi_out_bits { 4274 u8 status[0x8]; 4275 u8 reserved_at_8[0x18]; 4276 4277 u8 syndrome[0x20]; 4278 4279 u8 reserved_at_40[0x40]; 4280 }; 4281 4282 struct mlx5_ifc_set_issi_in_bits { 4283 u8 opcode[0x10]; 4284 u8 reserved_at_10[0x10]; 4285 4286 u8 reserved_at_20[0x10]; 4287 u8 op_mod[0x10]; 4288 4289 u8 reserved_at_40[0x10]; 4290 u8 current_issi[0x10]; 4291 4292 u8 reserved_at_60[0x20]; 4293 }; 4294 4295 struct mlx5_ifc_set_hca_cap_out_bits { 4296 u8 status[0x8]; 4297 u8 reserved_at_8[0x18]; 4298 4299 u8 syndrome[0x20]; 4300 4301 u8 reserved_at_40[0x40]; 4302 }; 4303 4304 struct mlx5_ifc_set_hca_cap_in_bits { 4305 u8 opcode[0x10]; 4306 u8 reserved_at_10[0x10]; 4307 4308 u8 reserved_at_20[0x10]; 4309 u8 op_mod[0x10]; 4310 4311 u8 other_function[0x1]; 4312 u8 reserved_at_41[0xf]; 4313 u8 function_id[0x10]; 4314 4315 u8 reserved_at_60[0x20]; 4316 4317 union mlx5_ifc_hca_cap_union_bits capability; 4318 }; 4319 4320 enum { 4321 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4322 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4323 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4324 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4325 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4326 }; 4327 4328 struct mlx5_ifc_set_fte_out_bits { 4329 u8 status[0x8]; 4330 u8 reserved_at_8[0x18]; 4331 4332 u8 syndrome[0x20]; 4333 4334 u8 reserved_at_40[0x40]; 4335 }; 4336 4337 struct mlx5_ifc_set_fte_in_bits { 4338 u8 opcode[0x10]; 4339 u8 reserved_at_10[0x10]; 4340 4341 u8 reserved_at_20[0x10]; 4342 u8 op_mod[0x10]; 4343 4344 u8 other_vport[0x1]; 4345 u8 reserved_at_41[0xf]; 4346 u8 vport_number[0x10]; 4347 4348 u8 reserved_at_60[0x20]; 4349 4350 u8 table_type[0x8]; 4351 u8 reserved_at_88[0x18]; 4352 4353 u8 reserved_at_a0[0x8]; 4354 u8 table_id[0x18]; 4355 4356 u8 ignore_flow_level[0x1]; 4357 u8 reserved_at_c1[0x17]; 4358 u8 modify_enable_mask[0x8]; 4359 4360 u8 reserved_at_e0[0x20]; 4361 4362 u8 flow_index[0x20]; 4363 4364 u8 reserved_at_120[0xe0]; 4365 4366 struct mlx5_ifc_flow_context_bits flow_context; 4367 }; 4368 4369 struct mlx5_ifc_rts2rts_qp_out_bits { 4370 u8 status[0x8]; 4371 u8 reserved_at_8[0x18]; 4372 4373 u8 syndrome[0x20]; 4374 4375 u8 reserved_at_40[0x20]; 4376 u8 ece[0x20]; 4377 }; 4378 4379 struct mlx5_ifc_rts2rts_qp_in_bits { 4380 u8 opcode[0x10]; 4381 u8 uid[0x10]; 4382 4383 u8 reserved_at_20[0x10]; 4384 u8 op_mod[0x10]; 4385 4386 u8 reserved_at_40[0x8]; 4387 u8 qpn[0x18]; 4388 4389 u8 reserved_at_60[0x20]; 4390 4391 u8 opt_param_mask[0x20]; 4392 4393 u8 ece[0x20]; 4394 4395 struct mlx5_ifc_qpc_bits qpc; 4396 4397 u8 reserved_at_800[0x80]; 4398 }; 4399 4400 struct mlx5_ifc_rtr2rts_qp_out_bits { 4401 u8 status[0x8]; 4402 u8 reserved_at_8[0x18]; 4403 4404 u8 syndrome[0x20]; 4405 4406 u8 reserved_at_40[0x20]; 4407 u8 ece[0x20]; 4408 }; 4409 4410 struct mlx5_ifc_rtr2rts_qp_in_bits { 4411 u8 opcode[0x10]; 4412 u8 uid[0x10]; 4413 4414 u8 reserved_at_20[0x10]; 4415 u8 op_mod[0x10]; 4416 4417 u8 reserved_at_40[0x8]; 4418 u8 qpn[0x18]; 4419 4420 u8 reserved_at_60[0x20]; 4421 4422 u8 opt_param_mask[0x20]; 4423 4424 u8 ece[0x20]; 4425 4426 struct mlx5_ifc_qpc_bits qpc; 4427 4428 u8 reserved_at_800[0x80]; 4429 }; 4430 4431 struct mlx5_ifc_rst2init_qp_out_bits { 4432 u8 status[0x8]; 4433 u8 reserved_at_8[0x18]; 4434 4435 u8 syndrome[0x20]; 4436 4437 u8 reserved_at_40[0x20]; 4438 u8 ece[0x20]; 4439 }; 4440 4441 struct mlx5_ifc_rst2init_qp_in_bits { 4442 u8 opcode[0x10]; 4443 u8 uid[0x10]; 4444 4445 u8 reserved_at_20[0x10]; 4446 u8 op_mod[0x10]; 4447 4448 u8 reserved_at_40[0x8]; 4449 u8 qpn[0x18]; 4450 4451 u8 reserved_at_60[0x20]; 4452 4453 u8 opt_param_mask[0x20]; 4454 4455 u8 ece[0x20]; 4456 4457 struct mlx5_ifc_qpc_bits qpc; 4458 4459 u8 reserved_at_800[0x80]; 4460 }; 4461 4462 struct mlx5_ifc_query_xrq_out_bits { 4463 u8 status[0x8]; 4464 u8 reserved_at_8[0x18]; 4465 4466 u8 syndrome[0x20]; 4467 4468 u8 reserved_at_40[0x40]; 4469 4470 struct mlx5_ifc_xrqc_bits xrq_context; 4471 }; 4472 4473 struct mlx5_ifc_query_xrq_in_bits { 4474 u8 opcode[0x10]; 4475 u8 reserved_at_10[0x10]; 4476 4477 u8 reserved_at_20[0x10]; 4478 u8 op_mod[0x10]; 4479 4480 u8 reserved_at_40[0x8]; 4481 u8 xrqn[0x18]; 4482 4483 u8 reserved_at_60[0x20]; 4484 }; 4485 4486 struct mlx5_ifc_query_xrc_srq_out_bits { 4487 u8 status[0x8]; 4488 u8 reserved_at_8[0x18]; 4489 4490 u8 syndrome[0x20]; 4491 4492 u8 reserved_at_40[0x40]; 4493 4494 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4495 4496 u8 reserved_at_280[0x600]; 4497 4498 u8 pas[][0x40]; 4499 }; 4500 4501 struct mlx5_ifc_query_xrc_srq_in_bits { 4502 u8 opcode[0x10]; 4503 u8 reserved_at_10[0x10]; 4504 4505 u8 reserved_at_20[0x10]; 4506 u8 op_mod[0x10]; 4507 4508 u8 reserved_at_40[0x8]; 4509 u8 xrc_srqn[0x18]; 4510 4511 u8 reserved_at_60[0x20]; 4512 }; 4513 4514 enum { 4515 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4516 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4517 }; 4518 4519 struct mlx5_ifc_query_vport_state_out_bits { 4520 u8 status[0x8]; 4521 u8 reserved_at_8[0x18]; 4522 4523 u8 syndrome[0x20]; 4524 4525 u8 reserved_at_40[0x20]; 4526 4527 u8 reserved_at_60[0x18]; 4528 u8 admin_state[0x4]; 4529 u8 state[0x4]; 4530 }; 4531 4532 enum { 4533 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4534 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4535 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4536 }; 4537 4538 struct mlx5_ifc_arm_monitor_counter_in_bits { 4539 u8 opcode[0x10]; 4540 u8 uid[0x10]; 4541 4542 u8 reserved_at_20[0x10]; 4543 u8 op_mod[0x10]; 4544 4545 u8 reserved_at_40[0x20]; 4546 4547 u8 reserved_at_60[0x20]; 4548 }; 4549 4550 struct mlx5_ifc_arm_monitor_counter_out_bits { 4551 u8 status[0x8]; 4552 u8 reserved_at_8[0x18]; 4553 4554 u8 syndrome[0x20]; 4555 4556 u8 reserved_at_40[0x40]; 4557 }; 4558 4559 enum { 4560 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4561 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4562 }; 4563 4564 enum mlx5_monitor_counter_ppcnt { 4565 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4566 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4567 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4568 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4569 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4570 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4571 }; 4572 4573 enum { 4574 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4575 }; 4576 4577 struct mlx5_ifc_monitor_counter_output_bits { 4578 u8 reserved_at_0[0x4]; 4579 u8 type[0x4]; 4580 u8 reserved_at_8[0x8]; 4581 u8 counter[0x10]; 4582 4583 u8 counter_group_id[0x20]; 4584 }; 4585 4586 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4587 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4588 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4589 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4590 4591 struct mlx5_ifc_set_monitor_counter_in_bits { 4592 u8 opcode[0x10]; 4593 u8 uid[0x10]; 4594 4595 u8 reserved_at_20[0x10]; 4596 u8 op_mod[0x10]; 4597 4598 u8 reserved_at_40[0x10]; 4599 u8 num_of_counters[0x10]; 4600 4601 u8 reserved_at_60[0x20]; 4602 4603 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4604 }; 4605 4606 struct mlx5_ifc_set_monitor_counter_out_bits { 4607 u8 status[0x8]; 4608 u8 reserved_at_8[0x18]; 4609 4610 u8 syndrome[0x20]; 4611 4612 u8 reserved_at_40[0x40]; 4613 }; 4614 4615 struct mlx5_ifc_query_vport_state_in_bits { 4616 u8 opcode[0x10]; 4617 u8 reserved_at_10[0x10]; 4618 4619 u8 reserved_at_20[0x10]; 4620 u8 op_mod[0x10]; 4621 4622 u8 other_vport[0x1]; 4623 u8 reserved_at_41[0xf]; 4624 u8 vport_number[0x10]; 4625 4626 u8 reserved_at_60[0x20]; 4627 }; 4628 4629 struct mlx5_ifc_query_vnic_env_out_bits { 4630 u8 status[0x8]; 4631 u8 reserved_at_8[0x18]; 4632 4633 u8 syndrome[0x20]; 4634 4635 u8 reserved_at_40[0x40]; 4636 4637 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4638 }; 4639 4640 enum { 4641 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4642 }; 4643 4644 struct mlx5_ifc_query_vnic_env_in_bits { 4645 u8 opcode[0x10]; 4646 u8 reserved_at_10[0x10]; 4647 4648 u8 reserved_at_20[0x10]; 4649 u8 op_mod[0x10]; 4650 4651 u8 other_vport[0x1]; 4652 u8 reserved_at_41[0xf]; 4653 u8 vport_number[0x10]; 4654 4655 u8 reserved_at_60[0x20]; 4656 }; 4657 4658 struct mlx5_ifc_query_vport_counter_out_bits { 4659 u8 status[0x8]; 4660 u8 reserved_at_8[0x18]; 4661 4662 u8 syndrome[0x20]; 4663 4664 u8 reserved_at_40[0x40]; 4665 4666 struct mlx5_ifc_traffic_counter_bits received_errors; 4667 4668 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4669 4670 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4671 4672 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4673 4674 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4675 4676 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4677 4678 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4679 4680 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4681 4682 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4683 4684 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4685 4686 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4687 4688 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4689 4690 u8 reserved_at_680[0xa00]; 4691 }; 4692 4693 enum { 4694 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4695 }; 4696 4697 struct mlx5_ifc_query_vport_counter_in_bits { 4698 u8 opcode[0x10]; 4699 u8 reserved_at_10[0x10]; 4700 4701 u8 reserved_at_20[0x10]; 4702 u8 op_mod[0x10]; 4703 4704 u8 other_vport[0x1]; 4705 u8 reserved_at_41[0xb]; 4706 u8 port_num[0x4]; 4707 u8 vport_number[0x10]; 4708 4709 u8 reserved_at_60[0x60]; 4710 4711 u8 clear[0x1]; 4712 u8 reserved_at_c1[0x1f]; 4713 4714 u8 reserved_at_e0[0x20]; 4715 }; 4716 4717 struct mlx5_ifc_query_tis_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_at_8[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_at_40[0x40]; 4724 4725 struct mlx5_ifc_tisc_bits tis_context; 4726 }; 4727 4728 struct mlx5_ifc_query_tis_in_bits { 4729 u8 opcode[0x10]; 4730 u8 reserved_at_10[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x8]; 4736 u8 tisn[0x18]; 4737 4738 u8 reserved_at_60[0x20]; 4739 }; 4740 4741 struct mlx5_ifc_query_tir_out_bits { 4742 u8 status[0x8]; 4743 u8 reserved_at_8[0x18]; 4744 4745 u8 syndrome[0x20]; 4746 4747 u8 reserved_at_40[0xc0]; 4748 4749 struct mlx5_ifc_tirc_bits tir_context; 4750 }; 4751 4752 struct mlx5_ifc_query_tir_in_bits { 4753 u8 opcode[0x10]; 4754 u8 reserved_at_10[0x10]; 4755 4756 u8 reserved_at_20[0x10]; 4757 u8 op_mod[0x10]; 4758 4759 u8 reserved_at_40[0x8]; 4760 u8 tirn[0x18]; 4761 4762 u8 reserved_at_60[0x20]; 4763 }; 4764 4765 struct mlx5_ifc_query_srq_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_at_8[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 reserved_at_40[0x40]; 4772 4773 struct mlx5_ifc_srqc_bits srq_context_entry; 4774 4775 u8 reserved_at_280[0x600]; 4776 4777 u8 pas[][0x40]; 4778 }; 4779 4780 struct mlx5_ifc_query_srq_in_bits { 4781 u8 opcode[0x10]; 4782 u8 reserved_at_10[0x10]; 4783 4784 u8 reserved_at_20[0x10]; 4785 u8 op_mod[0x10]; 4786 4787 u8 reserved_at_40[0x8]; 4788 u8 srqn[0x18]; 4789 4790 u8 reserved_at_60[0x20]; 4791 }; 4792 4793 struct mlx5_ifc_query_sq_out_bits { 4794 u8 status[0x8]; 4795 u8 reserved_at_8[0x18]; 4796 4797 u8 syndrome[0x20]; 4798 4799 u8 reserved_at_40[0xc0]; 4800 4801 struct mlx5_ifc_sqc_bits sq_context; 4802 }; 4803 4804 struct mlx5_ifc_query_sq_in_bits { 4805 u8 opcode[0x10]; 4806 u8 reserved_at_10[0x10]; 4807 4808 u8 reserved_at_20[0x10]; 4809 u8 op_mod[0x10]; 4810 4811 u8 reserved_at_40[0x8]; 4812 u8 sqn[0x18]; 4813 4814 u8 reserved_at_60[0x20]; 4815 }; 4816 4817 struct mlx5_ifc_query_special_contexts_out_bits { 4818 u8 status[0x8]; 4819 u8 reserved_at_8[0x18]; 4820 4821 u8 syndrome[0x20]; 4822 4823 u8 dump_fill_mkey[0x20]; 4824 4825 u8 resd_lkey[0x20]; 4826 4827 u8 null_mkey[0x20]; 4828 4829 u8 reserved_at_a0[0x60]; 4830 }; 4831 4832 struct mlx5_ifc_query_special_contexts_in_bits { 4833 u8 opcode[0x10]; 4834 u8 reserved_at_10[0x10]; 4835 4836 u8 reserved_at_20[0x10]; 4837 u8 op_mod[0x10]; 4838 4839 u8 reserved_at_40[0x40]; 4840 }; 4841 4842 struct mlx5_ifc_query_scheduling_element_out_bits { 4843 u8 opcode[0x10]; 4844 u8 reserved_at_10[0x10]; 4845 4846 u8 reserved_at_20[0x10]; 4847 u8 op_mod[0x10]; 4848 4849 u8 reserved_at_40[0xc0]; 4850 4851 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4852 4853 u8 reserved_at_300[0x100]; 4854 }; 4855 4856 enum { 4857 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4858 SCHEDULING_HIERARCHY_NIC = 0x3, 4859 }; 4860 4861 struct mlx5_ifc_query_scheduling_element_in_bits { 4862 u8 opcode[0x10]; 4863 u8 reserved_at_10[0x10]; 4864 4865 u8 reserved_at_20[0x10]; 4866 u8 op_mod[0x10]; 4867 4868 u8 scheduling_hierarchy[0x8]; 4869 u8 reserved_at_48[0x18]; 4870 4871 u8 scheduling_element_id[0x20]; 4872 4873 u8 reserved_at_80[0x180]; 4874 }; 4875 4876 struct mlx5_ifc_query_rqt_out_bits { 4877 u8 status[0x8]; 4878 u8 reserved_at_8[0x18]; 4879 4880 u8 syndrome[0x20]; 4881 4882 u8 reserved_at_40[0xc0]; 4883 4884 struct mlx5_ifc_rqtc_bits rqt_context; 4885 }; 4886 4887 struct mlx5_ifc_query_rqt_in_bits { 4888 u8 opcode[0x10]; 4889 u8 reserved_at_10[0x10]; 4890 4891 u8 reserved_at_20[0x10]; 4892 u8 op_mod[0x10]; 4893 4894 u8 reserved_at_40[0x8]; 4895 u8 rqtn[0x18]; 4896 4897 u8 reserved_at_60[0x20]; 4898 }; 4899 4900 struct mlx5_ifc_query_rq_out_bits { 4901 u8 status[0x8]; 4902 u8 reserved_at_8[0x18]; 4903 4904 u8 syndrome[0x20]; 4905 4906 u8 reserved_at_40[0xc0]; 4907 4908 struct mlx5_ifc_rqc_bits rq_context; 4909 }; 4910 4911 struct mlx5_ifc_query_rq_in_bits { 4912 u8 opcode[0x10]; 4913 u8 reserved_at_10[0x10]; 4914 4915 u8 reserved_at_20[0x10]; 4916 u8 op_mod[0x10]; 4917 4918 u8 reserved_at_40[0x8]; 4919 u8 rqn[0x18]; 4920 4921 u8 reserved_at_60[0x20]; 4922 }; 4923 4924 struct mlx5_ifc_query_roce_address_out_bits { 4925 u8 status[0x8]; 4926 u8 reserved_at_8[0x18]; 4927 4928 u8 syndrome[0x20]; 4929 4930 u8 reserved_at_40[0x40]; 4931 4932 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4933 }; 4934 4935 struct mlx5_ifc_query_roce_address_in_bits { 4936 u8 opcode[0x10]; 4937 u8 reserved_at_10[0x10]; 4938 4939 u8 reserved_at_20[0x10]; 4940 u8 op_mod[0x10]; 4941 4942 u8 roce_address_index[0x10]; 4943 u8 reserved_at_50[0xc]; 4944 u8 vhca_port_num[0x4]; 4945 4946 u8 reserved_at_60[0x20]; 4947 }; 4948 4949 struct mlx5_ifc_query_rmp_out_bits { 4950 u8 status[0x8]; 4951 u8 reserved_at_8[0x18]; 4952 4953 u8 syndrome[0x20]; 4954 4955 u8 reserved_at_40[0xc0]; 4956 4957 struct mlx5_ifc_rmpc_bits rmp_context; 4958 }; 4959 4960 struct mlx5_ifc_query_rmp_in_bits { 4961 u8 opcode[0x10]; 4962 u8 reserved_at_10[0x10]; 4963 4964 u8 reserved_at_20[0x10]; 4965 u8 op_mod[0x10]; 4966 4967 u8 reserved_at_40[0x8]; 4968 u8 rmpn[0x18]; 4969 4970 u8 reserved_at_60[0x20]; 4971 }; 4972 4973 struct mlx5_ifc_query_qp_out_bits { 4974 u8 status[0x8]; 4975 u8 reserved_at_8[0x18]; 4976 4977 u8 syndrome[0x20]; 4978 4979 u8 reserved_at_40[0x20]; 4980 u8 ece[0x20]; 4981 4982 u8 opt_param_mask[0x20]; 4983 4984 u8 reserved_at_a0[0x20]; 4985 4986 struct mlx5_ifc_qpc_bits qpc; 4987 4988 u8 reserved_at_800[0x80]; 4989 4990 u8 pas[][0x40]; 4991 }; 4992 4993 struct mlx5_ifc_query_qp_in_bits { 4994 u8 opcode[0x10]; 4995 u8 reserved_at_10[0x10]; 4996 4997 u8 reserved_at_20[0x10]; 4998 u8 op_mod[0x10]; 4999 5000 u8 reserved_at_40[0x8]; 5001 u8 qpn[0x18]; 5002 5003 u8 reserved_at_60[0x20]; 5004 }; 5005 5006 struct mlx5_ifc_query_q_counter_out_bits { 5007 u8 status[0x8]; 5008 u8 reserved_at_8[0x18]; 5009 5010 u8 syndrome[0x20]; 5011 5012 u8 reserved_at_40[0x40]; 5013 5014 u8 rx_write_requests[0x20]; 5015 5016 u8 reserved_at_a0[0x20]; 5017 5018 u8 rx_read_requests[0x20]; 5019 5020 u8 reserved_at_e0[0x20]; 5021 5022 u8 rx_atomic_requests[0x20]; 5023 5024 u8 reserved_at_120[0x20]; 5025 5026 u8 rx_dct_connect[0x20]; 5027 5028 u8 reserved_at_160[0x20]; 5029 5030 u8 out_of_buffer[0x20]; 5031 5032 u8 reserved_at_1a0[0x20]; 5033 5034 u8 out_of_sequence[0x20]; 5035 5036 u8 reserved_at_1e0[0x20]; 5037 5038 u8 duplicate_request[0x20]; 5039 5040 u8 reserved_at_220[0x20]; 5041 5042 u8 rnr_nak_retry_err[0x20]; 5043 5044 u8 reserved_at_260[0x20]; 5045 5046 u8 packet_seq_err[0x20]; 5047 5048 u8 reserved_at_2a0[0x20]; 5049 5050 u8 implied_nak_seq_err[0x20]; 5051 5052 u8 reserved_at_2e0[0x20]; 5053 5054 u8 local_ack_timeout_err[0x20]; 5055 5056 u8 reserved_at_320[0xa0]; 5057 5058 u8 resp_local_length_error[0x20]; 5059 5060 u8 req_local_length_error[0x20]; 5061 5062 u8 resp_local_qp_error[0x20]; 5063 5064 u8 local_operation_error[0x20]; 5065 5066 u8 resp_local_protection[0x20]; 5067 5068 u8 req_local_protection[0x20]; 5069 5070 u8 resp_cqe_error[0x20]; 5071 5072 u8 req_cqe_error[0x20]; 5073 5074 u8 req_mw_binding[0x20]; 5075 5076 u8 req_bad_response[0x20]; 5077 5078 u8 req_remote_invalid_request[0x20]; 5079 5080 u8 resp_remote_invalid_request[0x20]; 5081 5082 u8 req_remote_access_errors[0x20]; 5083 5084 u8 resp_remote_access_errors[0x20]; 5085 5086 u8 req_remote_operation_errors[0x20]; 5087 5088 u8 req_transport_retries_exceeded[0x20]; 5089 5090 u8 cq_overflow[0x20]; 5091 5092 u8 resp_cqe_flush_error[0x20]; 5093 5094 u8 req_cqe_flush_error[0x20]; 5095 5096 u8 reserved_at_620[0x20]; 5097 5098 u8 roce_adp_retrans[0x20]; 5099 5100 u8 roce_adp_retrans_to[0x20]; 5101 5102 u8 roce_slow_restart[0x20]; 5103 5104 u8 roce_slow_restart_cnps[0x20]; 5105 5106 u8 roce_slow_restart_trans[0x20]; 5107 5108 u8 reserved_at_6e0[0x120]; 5109 }; 5110 5111 struct mlx5_ifc_query_q_counter_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_at_10[0x10]; 5114 5115 u8 reserved_at_20[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_at_40[0x80]; 5119 5120 u8 clear[0x1]; 5121 u8 reserved_at_c1[0x1f]; 5122 5123 u8 reserved_at_e0[0x18]; 5124 u8 counter_set_id[0x8]; 5125 }; 5126 5127 struct mlx5_ifc_query_pages_out_bits { 5128 u8 status[0x8]; 5129 u8 reserved_at_8[0x18]; 5130 5131 u8 syndrome[0x20]; 5132 5133 u8 embedded_cpu_function[0x1]; 5134 u8 reserved_at_41[0xf]; 5135 u8 function_id[0x10]; 5136 5137 u8 num_pages[0x20]; 5138 }; 5139 5140 enum { 5141 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5142 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5143 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5144 }; 5145 5146 struct mlx5_ifc_query_pages_in_bits { 5147 u8 opcode[0x10]; 5148 u8 reserved_at_10[0x10]; 5149 5150 u8 reserved_at_20[0x10]; 5151 u8 op_mod[0x10]; 5152 5153 u8 embedded_cpu_function[0x1]; 5154 u8 reserved_at_41[0xf]; 5155 u8 function_id[0x10]; 5156 5157 u8 reserved_at_60[0x20]; 5158 }; 5159 5160 struct mlx5_ifc_query_nic_vport_context_out_bits { 5161 u8 status[0x8]; 5162 u8 reserved_at_8[0x18]; 5163 5164 u8 syndrome[0x20]; 5165 5166 u8 reserved_at_40[0x40]; 5167 5168 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5169 }; 5170 5171 struct mlx5_ifc_query_nic_vport_context_in_bits { 5172 u8 opcode[0x10]; 5173 u8 reserved_at_10[0x10]; 5174 5175 u8 reserved_at_20[0x10]; 5176 u8 op_mod[0x10]; 5177 5178 u8 other_vport[0x1]; 5179 u8 reserved_at_41[0xf]; 5180 u8 vport_number[0x10]; 5181 5182 u8 reserved_at_60[0x5]; 5183 u8 allowed_list_type[0x3]; 5184 u8 reserved_at_68[0x18]; 5185 }; 5186 5187 struct mlx5_ifc_query_mkey_out_bits { 5188 u8 status[0x8]; 5189 u8 reserved_at_8[0x18]; 5190 5191 u8 syndrome[0x20]; 5192 5193 u8 reserved_at_40[0x40]; 5194 5195 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5196 5197 u8 reserved_at_280[0x600]; 5198 5199 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5200 5201 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5202 }; 5203 5204 struct mlx5_ifc_query_mkey_in_bits { 5205 u8 opcode[0x10]; 5206 u8 reserved_at_10[0x10]; 5207 5208 u8 reserved_at_20[0x10]; 5209 u8 op_mod[0x10]; 5210 5211 u8 reserved_at_40[0x8]; 5212 u8 mkey_index[0x18]; 5213 5214 u8 pg_access[0x1]; 5215 u8 reserved_at_61[0x1f]; 5216 }; 5217 5218 struct mlx5_ifc_query_mad_demux_out_bits { 5219 u8 status[0x8]; 5220 u8 reserved_at_8[0x18]; 5221 5222 u8 syndrome[0x20]; 5223 5224 u8 reserved_at_40[0x40]; 5225 5226 u8 mad_dumux_parameters_block[0x20]; 5227 }; 5228 5229 struct mlx5_ifc_query_mad_demux_in_bits { 5230 u8 opcode[0x10]; 5231 u8 reserved_at_10[0x10]; 5232 5233 u8 reserved_at_20[0x10]; 5234 u8 op_mod[0x10]; 5235 5236 u8 reserved_at_40[0x40]; 5237 }; 5238 5239 struct mlx5_ifc_query_l2_table_entry_out_bits { 5240 u8 status[0x8]; 5241 u8 reserved_at_8[0x18]; 5242 5243 u8 syndrome[0x20]; 5244 5245 u8 reserved_at_40[0xa0]; 5246 5247 u8 reserved_at_e0[0x13]; 5248 u8 vlan_valid[0x1]; 5249 u8 vlan[0xc]; 5250 5251 struct mlx5_ifc_mac_address_layout_bits mac_address; 5252 5253 u8 reserved_at_140[0xc0]; 5254 }; 5255 5256 struct mlx5_ifc_query_l2_table_entry_in_bits { 5257 u8 opcode[0x10]; 5258 u8 reserved_at_10[0x10]; 5259 5260 u8 reserved_at_20[0x10]; 5261 u8 op_mod[0x10]; 5262 5263 u8 reserved_at_40[0x60]; 5264 5265 u8 reserved_at_a0[0x8]; 5266 u8 table_index[0x18]; 5267 5268 u8 reserved_at_c0[0x140]; 5269 }; 5270 5271 struct mlx5_ifc_query_issi_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0x10]; 5278 u8 current_issi[0x10]; 5279 5280 u8 reserved_at_60[0xa0]; 5281 5282 u8 reserved_at_100[76][0x8]; 5283 u8 supported_issi_dw0[0x20]; 5284 }; 5285 5286 struct mlx5_ifc_query_issi_in_bits { 5287 u8 opcode[0x10]; 5288 u8 reserved_at_10[0x10]; 5289 5290 u8 reserved_at_20[0x10]; 5291 u8 op_mod[0x10]; 5292 5293 u8 reserved_at_40[0x40]; 5294 }; 5295 5296 struct mlx5_ifc_set_driver_version_out_bits { 5297 u8 status[0x8]; 5298 u8 reserved_0[0x18]; 5299 5300 u8 syndrome[0x20]; 5301 u8 reserved_1[0x40]; 5302 }; 5303 5304 struct mlx5_ifc_set_driver_version_in_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_0[0x10]; 5307 5308 u8 reserved_1[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_2[0x40]; 5312 u8 driver_version[64][0x8]; 5313 }; 5314 5315 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5316 u8 status[0x8]; 5317 u8 reserved_at_8[0x18]; 5318 5319 u8 syndrome[0x20]; 5320 5321 u8 reserved_at_40[0x40]; 5322 5323 struct mlx5_ifc_pkey_bits pkey[]; 5324 }; 5325 5326 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5327 u8 opcode[0x10]; 5328 u8 reserved_at_10[0x10]; 5329 5330 u8 reserved_at_20[0x10]; 5331 u8 op_mod[0x10]; 5332 5333 u8 other_vport[0x1]; 5334 u8 reserved_at_41[0xb]; 5335 u8 port_num[0x4]; 5336 u8 vport_number[0x10]; 5337 5338 u8 reserved_at_60[0x10]; 5339 u8 pkey_index[0x10]; 5340 }; 5341 5342 enum { 5343 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5344 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5345 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5346 }; 5347 5348 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5349 u8 status[0x8]; 5350 u8 reserved_at_8[0x18]; 5351 5352 u8 syndrome[0x20]; 5353 5354 u8 reserved_at_40[0x20]; 5355 5356 u8 gids_num[0x10]; 5357 u8 reserved_at_70[0x10]; 5358 5359 struct mlx5_ifc_array128_auto_bits gid[]; 5360 }; 5361 5362 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5363 u8 opcode[0x10]; 5364 u8 reserved_at_10[0x10]; 5365 5366 u8 reserved_at_20[0x10]; 5367 u8 op_mod[0x10]; 5368 5369 u8 other_vport[0x1]; 5370 u8 reserved_at_41[0xb]; 5371 u8 port_num[0x4]; 5372 u8 vport_number[0x10]; 5373 5374 u8 reserved_at_60[0x10]; 5375 u8 gid_index[0x10]; 5376 }; 5377 5378 struct mlx5_ifc_query_hca_vport_context_out_bits { 5379 u8 status[0x8]; 5380 u8 reserved_at_8[0x18]; 5381 5382 u8 syndrome[0x20]; 5383 5384 u8 reserved_at_40[0x40]; 5385 5386 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5387 }; 5388 5389 struct mlx5_ifc_query_hca_vport_context_in_bits { 5390 u8 opcode[0x10]; 5391 u8 reserved_at_10[0x10]; 5392 5393 u8 reserved_at_20[0x10]; 5394 u8 op_mod[0x10]; 5395 5396 u8 other_vport[0x1]; 5397 u8 reserved_at_41[0xb]; 5398 u8 port_num[0x4]; 5399 u8 vport_number[0x10]; 5400 5401 u8 reserved_at_60[0x20]; 5402 }; 5403 5404 struct mlx5_ifc_query_hca_cap_out_bits { 5405 u8 status[0x8]; 5406 u8 reserved_at_8[0x18]; 5407 5408 u8 syndrome[0x20]; 5409 5410 u8 reserved_at_40[0x40]; 5411 5412 union mlx5_ifc_hca_cap_union_bits capability; 5413 }; 5414 5415 struct mlx5_ifc_query_hca_cap_in_bits { 5416 u8 opcode[0x10]; 5417 u8 reserved_at_10[0x10]; 5418 5419 u8 reserved_at_20[0x10]; 5420 u8 op_mod[0x10]; 5421 5422 u8 other_function[0x1]; 5423 u8 reserved_at_41[0xf]; 5424 u8 function_id[0x10]; 5425 5426 u8 reserved_at_60[0x20]; 5427 }; 5428 5429 struct mlx5_ifc_other_hca_cap_bits { 5430 u8 roce[0x1]; 5431 u8 reserved_at_1[0x27f]; 5432 }; 5433 5434 struct mlx5_ifc_query_other_hca_cap_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_at_8[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_at_40[0x40]; 5441 5442 struct mlx5_ifc_other_hca_cap_bits other_capability; 5443 }; 5444 5445 struct mlx5_ifc_query_other_hca_cap_in_bits { 5446 u8 opcode[0x10]; 5447 u8 reserved_at_10[0x10]; 5448 5449 u8 reserved_at_20[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_at_40[0x10]; 5453 u8 function_id[0x10]; 5454 5455 u8 reserved_at_60[0x20]; 5456 }; 5457 5458 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5459 u8 status[0x8]; 5460 u8 reserved_at_8[0x18]; 5461 5462 u8 syndrome[0x20]; 5463 5464 u8 reserved_at_40[0x40]; 5465 }; 5466 5467 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5468 u8 opcode[0x10]; 5469 u8 reserved_at_10[0x10]; 5470 5471 u8 reserved_at_20[0x10]; 5472 u8 op_mod[0x10]; 5473 5474 u8 reserved_at_40[0x10]; 5475 u8 function_id[0x10]; 5476 u8 field_select[0x20]; 5477 5478 struct mlx5_ifc_other_hca_cap_bits other_capability; 5479 }; 5480 5481 struct mlx5_ifc_flow_table_context_bits { 5482 u8 reformat_en[0x1]; 5483 u8 decap_en[0x1]; 5484 u8 sw_owner[0x1]; 5485 u8 termination_table[0x1]; 5486 u8 table_miss_action[0x4]; 5487 u8 level[0x8]; 5488 u8 reserved_at_10[0x8]; 5489 u8 log_size[0x8]; 5490 5491 u8 reserved_at_20[0x8]; 5492 u8 table_miss_id[0x18]; 5493 5494 u8 reserved_at_40[0x8]; 5495 u8 lag_master_next_table_id[0x18]; 5496 5497 u8 reserved_at_60[0x60]; 5498 5499 u8 sw_owner_icm_root_1[0x40]; 5500 5501 u8 sw_owner_icm_root_0[0x40]; 5502 5503 }; 5504 5505 struct mlx5_ifc_query_flow_table_out_bits { 5506 u8 status[0x8]; 5507 u8 reserved_at_8[0x18]; 5508 5509 u8 syndrome[0x20]; 5510 5511 u8 reserved_at_40[0x80]; 5512 5513 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5514 }; 5515 5516 struct mlx5_ifc_query_flow_table_in_bits { 5517 u8 opcode[0x10]; 5518 u8 reserved_at_10[0x10]; 5519 5520 u8 reserved_at_20[0x10]; 5521 u8 op_mod[0x10]; 5522 5523 u8 reserved_at_40[0x40]; 5524 5525 u8 table_type[0x8]; 5526 u8 reserved_at_88[0x18]; 5527 5528 u8 reserved_at_a0[0x8]; 5529 u8 table_id[0x18]; 5530 5531 u8 reserved_at_c0[0x140]; 5532 }; 5533 5534 struct mlx5_ifc_query_fte_out_bits { 5535 u8 status[0x8]; 5536 u8 reserved_at_8[0x18]; 5537 5538 u8 syndrome[0x20]; 5539 5540 u8 reserved_at_40[0x1c0]; 5541 5542 struct mlx5_ifc_flow_context_bits flow_context; 5543 }; 5544 5545 struct mlx5_ifc_query_fte_in_bits { 5546 u8 opcode[0x10]; 5547 u8 reserved_at_10[0x10]; 5548 5549 u8 reserved_at_20[0x10]; 5550 u8 op_mod[0x10]; 5551 5552 u8 reserved_at_40[0x40]; 5553 5554 u8 table_type[0x8]; 5555 u8 reserved_at_88[0x18]; 5556 5557 u8 reserved_at_a0[0x8]; 5558 u8 table_id[0x18]; 5559 5560 u8 reserved_at_c0[0x40]; 5561 5562 u8 flow_index[0x20]; 5563 5564 u8 reserved_at_120[0xe0]; 5565 }; 5566 5567 enum { 5568 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5569 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5570 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5571 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5572 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5573 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5574 }; 5575 5576 struct mlx5_ifc_query_flow_group_out_bits { 5577 u8 status[0x8]; 5578 u8 reserved_at_8[0x18]; 5579 5580 u8 syndrome[0x20]; 5581 5582 u8 reserved_at_40[0xa0]; 5583 5584 u8 start_flow_index[0x20]; 5585 5586 u8 reserved_at_100[0x20]; 5587 5588 u8 end_flow_index[0x20]; 5589 5590 u8 reserved_at_140[0xa0]; 5591 5592 u8 reserved_at_1e0[0x18]; 5593 u8 match_criteria_enable[0x8]; 5594 5595 struct mlx5_ifc_fte_match_param_bits match_criteria; 5596 5597 u8 reserved_at_1200[0xe00]; 5598 }; 5599 5600 struct mlx5_ifc_query_flow_group_in_bits { 5601 u8 opcode[0x10]; 5602 u8 reserved_at_10[0x10]; 5603 5604 u8 reserved_at_20[0x10]; 5605 u8 op_mod[0x10]; 5606 5607 u8 reserved_at_40[0x40]; 5608 5609 u8 table_type[0x8]; 5610 u8 reserved_at_88[0x18]; 5611 5612 u8 reserved_at_a0[0x8]; 5613 u8 table_id[0x18]; 5614 5615 u8 group_id[0x20]; 5616 5617 u8 reserved_at_e0[0x120]; 5618 }; 5619 5620 struct mlx5_ifc_query_flow_counter_out_bits { 5621 u8 status[0x8]; 5622 u8 reserved_at_8[0x18]; 5623 5624 u8 syndrome[0x20]; 5625 5626 u8 reserved_at_40[0x40]; 5627 5628 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5629 }; 5630 5631 struct mlx5_ifc_query_flow_counter_in_bits { 5632 u8 opcode[0x10]; 5633 u8 reserved_at_10[0x10]; 5634 5635 u8 reserved_at_20[0x10]; 5636 u8 op_mod[0x10]; 5637 5638 u8 reserved_at_40[0x80]; 5639 5640 u8 clear[0x1]; 5641 u8 reserved_at_c1[0xf]; 5642 u8 num_of_counters[0x10]; 5643 5644 u8 flow_counter_id[0x20]; 5645 }; 5646 5647 struct mlx5_ifc_query_esw_vport_context_out_bits { 5648 u8 status[0x8]; 5649 u8 reserved_at_8[0x18]; 5650 5651 u8 syndrome[0x20]; 5652 5653 u8 reserved_at_40[0x40]; 5654 5655 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5656 }; 5657 5658 struct mlx5_ifc_query_esw_vport_context_in_bits { 5659 u8 opcode[0x10]; 5660 u8 reserved_at_10[0x10]; 5661 5662 u8 reserved_at_20[0x10]; 5663 u8 op_mod[0x10]; 5664 5665 u8 other_vport[0x1]; 5666 u8 reserved_at_41[0xf]; 5667 u8 vport_number[0x10]; 5668 5669 u8 reserved_at_60[0x20]; 5670 }; 5671 5672 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 reserved_at_40[0x40]; 5679 }; 5680 5681 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5682 u8 reserved_at_0[0x1b]; 5683 u8 fdb_to_vport_reg_c_id[0x1]; 5684 u8 vport_cvlan_insert[0x1]; 5685 u8 vport_svlan_insert[0x1]; 5686 u8 vport_cvlan_strip[0x1]; 5687 u8 vport_svlan_strip[0x1]; 5688 }; 5689 5690 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5691 u8 opcode[0x10]; 5692 u8 reserved_at_10[0x10]; 5693 5694 u8 reserved_at_20[0x10]; 5695 u8 op_mod[0x10]; 5696 5697 u8 other_vport[0x1]; 5698 u8 reserved_at_41[0xf]; 5699 u8 vport_number[0x10]; 5700 5701 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5702 5703 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5704 }; 5705 5706 struct mlx5_ifc_query_eq_out_bits { 5707 u8 status[0x8]; 5708 u8 reserved_at_8[0x18]; 5709 5710 u8 syndrome[0x20]; 5711 5712 u8 reserved_at_40[0x40]; 5713 5714 struct mlx5_ifc_eqc_bits eq_context_entry; 5715 5716 u8 reserved_at_280[0x40]; 5717 5718 u8 event_bitmask[0x40]; 5719 5720 u8 reserved_at_300[0x580]; 5721 5722 u8 pas[][0x40]; 5723 }; 5724 5725 struct mlx5_ifc_query_eq_in_bits { 5726 u8 opcode[0x10]; 5727 u8 reserved_at_10[0x10]; 5728 5729 u8 reserved_at_20[0x10]; 5730 u8 op_mod[0x10]; 5731 5732 u8 reserved_at_40[0x18]; 5733 u8 eq_number[0x8]; 5734 5735 u8 reserved_at_60[0x20]; 5736 }; 5737 5738 struct mlx5_ifc_packet_reformat_context_in_bits { 5739 u8 reserved_at_0[0x5]; 5740 u8 reformat_type[0x3]; 5741 u8 reserved_at_8[0xe]; 5742 u8 reformat_data_size[0xa]; 5743 5744 u8 reserved_at_20[0x10]; 5745 u8 reformat_data[2][0x8]; 5746 5747 u8 more_reformat_data[][0x8]; 5748 }; 5749 5750 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5751 u8 status[0x8]; 5752 u8 reserved_at_8[0x18]; 5753 5754 u8 syndrome[0x20]; 5755 5756 u8 reserved_at_40[0xa0]; 5757 5758 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5759 }; 5760 5761 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5762 u8 opcode[0x10]; 5763 u8 reserved_at_10[0x10]; 5764 5765 u8 reserved_at_20[0x10]; 5766 u8 op_mod[0x10]; 5767 5768 u8 packet_reformat_id[0x20]; 5769 5770 u8 reserved_at_60[0xa0]; 5771 }; 5772 5773 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5774 u8 status[0x8]; 5775 u8 reserved_at_8[0x18]; 5776 5777 u8 syndrome[0x20]; 5778 5779 u8 packet_reformat_id[0x20]; 5780 5781 u8 reserved_at_60[0x20]; 5782 }; 5783 5784 enum mlx5_reformat_ctx_type { 5785 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5786 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5787 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5788 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5789 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5790 }; 5791 5792 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5793 u8 opcode[0x10]; 5794 u8 reserved_at_10[0x10]; 5795 5796 u8 reserved_at_20[0x10]; 5797 u8 op_mod[0x10]; 5798 5799 u8 reserved_at_40[0xa0]; 5800 5801 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5802 }; 5803 5804 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5805 u8 status[0x8]; 5806 u8 reserved_at_8[0x18]; 5807 5808 u8 syndrome[0x20]; 5809 5810 u8 reserved_at_40[0x40]; 5811 }; 5812 5813 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5814 u8 opcode[0x10]; 5815 u8 reserved_at_10[0x10]; 5816 5817 u8 reserved_20[0x10]; 5818 u8 op_mod[0x10]; 5819 5820 u8 packet_reformat_id[0x20]; 5821 5822 u8 reserved_60[0x20]; 5823 }; 5824 5825 struct mlx5_ifc_set_action_in_bits { 5826 u8 action_type[0x4]; 5827 u8 field[0xc]; 5828 u8 reserved_at_10[0x3]; 5829 u8 offset[0x5]; 5830 u8 reserved_at_18[0x3]; 5831 u8 length[0x5]; 5832 5833 u8 data[0x20]; 5834 }; 5835 5836 struct mlx5_ifc_add_action_in_bits { 5837 u8 action_type[0x4]; 5838 u8 field[0xc]; 5839 u8 reserved_at_10[0x10]; 5840 5841 u8 data[0x20]; 5842 }; 5843 5844 struct mlx5_ifc_copy_action_in_bits { 5845 u8 action_type[0x4]; 5846 u8 src_field[0xc]; 5847 u8 reserved_at_10[0x3]; 5848 u8 src_offset[0x5]; 5849 u8 reserved_at_18[0x3]; 5850 u8 length[0x5]; 5851 5852 u8 reserved_at_20[0x4]; 5853 u8 dst_field[0xc]; 5854 u8 reserved_at_30[0x3]; 5855 u8 dst_offset[0x5]; 5856 u8 reserved_at_38[0x8]; 5857 }; 5858 5859 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5860 struct mlx5_ifc_set_action_in_bits set_action_in; 5861 struct mlx5_ifc_add_action_in_bits add_action_in; 5862 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5863 u8 reserved_at_0[0x40]; 5864 }; 5865 5866 enum { 5867 MLX5_ACTION_TYPE_SET = 0x1, 5868 MLX5_ACTION_TYPE_ADD = 0x2, 5869 MLX5_ACTION_TYPE_COPY = 0x3, 5870 }; 5871 5872 enum { 5873 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5874 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5875 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5876 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5877 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5878 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5879 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5880 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5881 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5882 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5883 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5884 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5885 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5886 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5887 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5888 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5889 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5890 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5891 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5892 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5893 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5894 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5895 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5896 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5897 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5898 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5899 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5900 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5901 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5902 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5903 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5904 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5905 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5906 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5907 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5908 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5909 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5910 }; 5911 5912 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5913 u8 status[0x8]; 5914 u8 reserved_at_8[0x18]; 5915 5916 u8 syndrome[0x20]; 5917 5918 u8 modify_header_id[0x20]; 5919 5920 u8 reserved_at_60[0x20]; 5921 }; 5922 5923 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5924 u8 opcode[0x10]; 5925 u8 reserved_at_10[0x10]; 5926 5927 u8 reserved_at_20[0x10]; 5928 u8 op_mod[0x10]; 5929 5930 u8 reserved_at_40[0x20]; 5931 5932 u8 table_type[0x8]; 5933 u8 reserved_at_68[0x10]; 5934 u8 num_of_actions[0x8]; 5935 5936 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5937 }; 5938 5939 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5940 u8 status[0x8]; 5941 u8 reserved_at_8[0x18]; 5942 5943 u8 syndrome[0x20]; 5944 5945 u8 reserved_at_40[0x40]; 5946 }; 5947 5948 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5949 u8 opcode[0x10]; 5950 u8 reserved_at_10[0x10]; 5951 5952 u8 reserved_at_20[0x10]; 5953 u8 op_mod[0x10]; 5954 5955 u8 modify_header_id[0x20]; 5956 5957 u8 reserved_at_60[0x20]; 5958 }; 5959 5960 struct mlx5_ifc_query_modify_header_context_in_bits { 5961 u8 opcode[0x10]; 5962 u8 uid[0x10]; 5963 5964 u8 reserved_at_20[0x10]; 5965 u8 op_mod[0x10]; 5966 5967 u8 modify_header_id[0x20]; 5968 5969 u8 reserved_at_60[0xa0]; 5970 }; 5971 5972 struct mlx5_ifc_query_dct_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_at_8[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 reserved_at_40[0x40]; 5979 5980 struct mlx5_ifc_dctc_bits dct_context_entry; 5981 5982 u8 reserved_at_280[0x180]; 5983 }; 5984 5985 struct mlx5_ifc_query_dct_in_bits { 5986 u8 opcode[0x10]; 5987 u8 reserved_at_10[0x10]; 5988 5989 u8 reserved_at_20[0x10]; 5990 u8 op_mod[0x10]; 5991 5992 u8 reserved_at_40[0x8]; 5993 u8 dctn[0x18]; 5994 5995 u8 reserved_at_60[0x20]; 5996 }; 5997 5998 struct mlx5_ifc_query_cq_out_bits { 5999 u8 status[0x8]; 6000 u8 reserved_at_8[0x18]; 6001 6002 u8 syndrome[0x20]; 6003 6004 u8 reserved_at_40[0x40]; 6005 6006 struct mlx5_ifc_cqc_bits cq_context; 6007 6008 u8 reserved_at_280[0x600]; 6009 6010 u8 pas[][0x40]; 6011 }; 6012 6013 struct mlx5_ifc_query_cq_in_bits { 6014 u8 opcode[0x10]; 6015 u8 reserved_at_10[0x10]; 6016 6017 u8 reserved_at_20[0x10]; 6018 u8 op_mod[0x10]; 6019 6020 u8 reserved_at_40[0x8]; 6021 u8 cqn[0x18]; 6022 6023 u8 reserved_at_60[0x20]; 6024 }; 6025 6026 struct mlx5_ifc_query_cong_status_out_bits { 6027 u8 status[0x8]; 6028 u8 reserved_at_8[0x18]; 6029 6030 u8 syndrome[0x20]; 6031 6032 u8 reserved_at_40[0x20]; 6033 6034 u8 enable[0x1]; 6035 u8 tag_enable[0x1]; 6036 u8 reserved_at_62[0x1e]; 6037 }; 6038 6039 struct mlx5_ifc_query_cong_status_in_bits { 6040 u8 opcode[0x10]; 6041 u8 reserved_at_10[0x10]; 6042 6043 u8 reserved_at_20[0x10]; 6044 u8 op_mod[0x10]; 6045 6046 u8 reserved_at_40[0x18]; 6047 u8 priority[0x4]; 6048 u8 cong_protocol[0x4]; 6049 6050 u8 reserved_at_60[0x20]; 6051 }; 6052 6053 struct mlx5_ifc_query_cong_statistics_out_bits { 6054 u8 status[0x8]; 6055 u8 reserved_at_8[0x18]; 6056 6057 u8 syndrome[0x20]; 6058 6059 u8 reserved_at_40[0x40]; 6060 6061 u8 rp_cur_flows[0x20]; 6062 6063 u8 sum_flows[0x20]; 6064 6065 u8 rp_cnp_ignored_high[0x20]; 6066 6067 u8 rp_cnp_ignored_low[0x20]; 6068 6069 u8 rp_cnp_handled_high[0x20]; 6070 6071 u8 rp_cnp_handled_low[0x20]; 6072 6073 u8 reserved_at_140[0x100]; 6074 6075 u8 time_stamp_high[0x20]; 6076 6077 u8 time_stamp_low[0x20]; 6078 6079 u8 accumulators_period[0x20]; 6080 6081 u8 np_ecn_marked_roce_packets_high[0x20]; 6082 6083 u8 np_ecn_marked_roce_packets_low[0x20]; 6084 6085 u8 np_cnp_sent_high[0x20]; 6086 6087 u8 np_cnp_sent_low[0x20]; 6088 6089 u8 reserved_at_320[0x560]; 6090 }; 6091 6092 struct mlx5_ifc_query_cong_statistics_in_bits { 6093 u8 opcode[0x10]; 6094 u8 reserved_at_10[0x10]; 6095 6096 u8 reserved_at_20[0x10]; 6097 u8 op_mod[0x10]; 6098 6099 u8 clear[0x1]; 6100 u8 reserved_at_41[0x1f]; 6101 6102 u8 reserved_at_60[0x20]; 6103 }; 6104 6105 struct mlx5_ifc_query_cong_params_out_bits { 6106 u8 status[0x8]; 6107 u8 reserved_at_8[0x18]; 6108 6109 u8 syndrome[0x20]; 6110 6111 u8 reserved_at_40[0x40]; 6112 6113 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6114 }; 6115 6116 struct mlx5_ifc_query_cong_params_in_bits { 6117 u8 opcode[0x10]; 6118 u8 reserved_at_10[0x10]; 6119 6120 u8 reserved_at_20[0x10]; 6121 u8 op_mod[0x10]; 6122 6123 u8 reserved_at_40[0x1c]; 6124 u8 cong_protocol[0x4]; 6125 6126 u8 reserved_at_60[0x20]; 6127 }; 6128 6129 struct mlx5_ifc_query_adapter_out_bits { 6130 u8 status[0x8]; 6131 u8 reserved_at_8[0x18]; 6132 6133 u8 syndrome[0x20]; 6134 6135 u8 reserved_at_40[0x40]; 6136 6137 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6138 }; 6139 6140 struct mlx5_ifc_query_adapter_in_bits { 6141 u8 opcode[0x10]; 6142 u8 reserved_at_10[0x10]; 6143 6144 u8 reserved_at_20[0x10]; 6145 u8 op_mod[0x10]; 6146 6147 u8 reserved_at_40[0x40]; 6148 }; 6149 6150 struct mlx5_ifc_qp_2rst_out_bits { 6151 u8 status[0x8]; 6152 u8 reserved_at_8[0x18]; 6153 6154 u8 syndrome[0x20]; 6155 6156 u8 reserved_at_40[0x40]; 6157 }; 6158 6159 struct mlx5_ifc_qp_2rst_in_bits { 6160 u8 opcode[0x10]; 6161 u8 uid[0x10]; 6162 6163 u8 reserved_at_20[0x10]; 6164 u8 op_mod[0x10]; 6165 6166 u8 reserved_at_40[0x8]; 6167 u8 qpn[0x18]; 6168 6169 u8 reserved_at_60[0x20]; 6170 }; 6171 6172 struct mlx5_ifc_qp_2err_out_bits { 6173 u8 status[0x8]; 6174 u8 reserved_at_8[0x18]; 6175 6176 u8 syndrome[0x20]; 6177 6178 u8 reserved_at_40[0x40]; 6179 }; 6180 6181 struct mlx5_ifc_qp_2err_in_bits { 6182 u8 opcode[0x10]; 6183 u8 uid[0x10]; 6184 6185 u8 reserved_at_20[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 reserved_at_40[0x8]; 6189 u8 qpn[0x18]; 6190 6191 u8 reserved_at_60[0x20]; 6192 }; 6193 6194 struct mlx5_ifc_page_fault_resume_out_bits { 6195 u8 status[0x8]; 6196 u8 reserved_at_8[0x18]; 6197 6198 u8 syndrome[0x20]; 6199 6200 u8 reserved_at_40[0x40]; 6201 }; 6202 6203 struct mlx5_ifc_page_fault_resume_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_at_10[0x10]; 6206 6207 u8 reserved_at_20[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 error[0x1]; 6211 u8 reserved_at_41[0x4]; 6212 u8 page_fault_type[0x3]; 6213 u8 wq_number[0x18]; 6214 6215 u8 reserved_at_60[0x8]; 6216 u8 token[0x18]; 6217 }; 6218 6219 struct mlx5_ifc_nop_out_bits { 6220 u8 status[0x8]; 6221 u8 reserved_at_8[0x18]; 6222 6223 u8 syndrome[0x20]; 6224 6225 u8 reserved_at_40[0x40]; 6226 }; 6227 6228 struct mlx5_ifc_nop_in_bits { 6229 u8 opcode[0x10]; 6230 u8 reserved_at_10[0x10]; 6231 6232 u8 reserved_at_20[0x10]; 6233 u8 op_mod[0x10]; 6234 6235 u8 reserved_at_40[0x40]; 6236 }; 6237 6238 struct mlx5_ifc_modify_vport_state_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 }; 6246 6247 struct mlx5_ifc_modify_vport_state_in_bits { 6248 u8 opcode[0x10]; 6249 u8 reserved_at_10[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 other_vport[0x1]; 6255 u8 reserved_at_41[0xf]; 6256 u8 vport_number[0x10]; 6257 6258 u8 reserved_at_60[0x18]; 6259 u8 admin_state[0x4]; 6260 u8 reserved_at_7c[0x4]; 6261 }; 6262 6263 struct mlx5_ifc_modify_tis_out_bits { 6264 u8 status[0x8]; 6265 u8 reserved_at_8[0x18]; 6266 6267 u8 syndrome[0x20]; 6268 6269 u8 reserved_at_40[0x40]; 6270 }; 6271 6272 struct mlx5_ifc_modify_tis_bitmask_bits { 6273 u8 reserved_at_0[0x20]; 6274 6275 u8 reserved_at_20[0x1d]; 6276 u8 lag_tx_port_affinity[0x1]; 6277 u8 strict_lag_tx_port_affinity[0x1]; 6278 u8 prio[0x1]; 6279 }; 6280 6281 struct mlx5_ifc_modify_tis_in_bits { 6282 u8 opcode[0x10]; 6283 u8 uid[0x10]; 6284 6285 u8 reserved_at_20[0x10]; 6286 u8 op_mod[0x10]; 6287 6288 u8 reserved_at_40[0x8]; 6289 u8 tisn[0x18]; 6290 6291 u8 reserved_at_60[0x20]; 6292 6293 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6294 6295 u8 reserved_at_c0[0x40]; 6296 6297 struct mlx5_ifc_tisc_bits ctx; 6298 }; 6299 6300 struct mlx5_ifc_modify_tir_bitmask_bits { 6301 u8 reserved_at_0[0x20]; 6302 6303 u8 reserved_at_20[0x1b]; 6304 u8 self_lb_en[0x1]; 6305 u8 reserved_at_3c[0x1]; 6306 u8 hash[0x1]; 6307 u8 reserved_at_3e[0x1]; 6308 u8 lro[0x1]; 6309 }; 6310 6311 struct mlx5_ifc_modify_tir_out_bits { 6312 u8 status[0x8]; 6313 u8 reserved_at_8[0x18]; 6314 6315 u8 syndrome[0x20]; 6316 6317 u8 reserved_at_40[0x40]; 6318 }; 6319 6320 struct mlx5_ifc_modify_tir_in_bits { 6321 u8 opcode[0x10]; 6322 u8 uid[0x10]; 6323 6324 u8 reserved_at_20[0x10]; 6325 u8 op_mod[0x10]; 6326 6327 u8 reserved_at_40[0x8]; 6328 u8 tirn[0x18]; 6329 6330 u8 reserved_at_60[0x20]; 6331 6332 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6333 6334 u8 reserved_at_c0[0x40]; 6335 6336 struct mlx5_ifc_tirc_bits ctx; 6337 }; 6338 6339 struct mlx5_ifc_modify_sq_out_bits { 6340 u8 status[0x8]; 6341 u8 reserved_at_8[0x18]; 6342 6343 u8 syndrome[0x20]; 6344 6345 u8 reserved_at_40[0x40]; 6346 }; 6347 6348 struct mlx5_ifc_modify_sq_in_bits { 6349 u8 opcode[0x10]; 6350 u8 uid[0x10]; 6351 6352 u8 reserved_at_20[0x10]; 6353 u8 op_mod[0x10]; 6354 6355 u8 sq_state[0x4]; 6356 u8 reserved_at_44[0x4]; 6357 u8 sqn[0x18]; 6358 6359 u8 reserved_at_60[0x20]; 6360 6361 u8 modify_bitmask[0x40]; 6362 6363 u8 reserved_at_c0[0x40]; 6364 6365 struct mlx5_ifc_sqc_bits ctx; 6366 }; 6367 6368 struct mlx5_ifc_modify_scheduling_element_out_bits { 6369 u8 status[0x8]; 6370 u8 reserved_at_8[0x18]; 6371 6372 u8 syndrome[0x20]; 6373 6374 u8 reserved_at_40[0x1c0]; 6375 }; 6376 6377 enum { 6378 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6379 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6380 }; 6381 6382 struct mlx5_ifc_modify_scheduling_element_in_bits { 6383 u8 opcode[0x10]; 6384 u8 reserved_at_10[0x10]; 6385 6386 u8 reserved_at_20[0x10]; 6387 u8 op_mod[0x10]; 6388 6389 u8 scheduling_hierarchy[0x8]; 6390 u8 reserved_at_48[0x18]; 6391 6392 u8 scheduling_element_id[0x20]; 6393 6394 u8 reserved_at_80[0x20]; 6395 6396 u8 modify_bitmask[0x20]; 6397 6398 u8 reserved_at_c0[0x40]; 6399 6400 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6401 6402 u8 reserved_at_300[0x100]; 6403 }; 6404 6405 struct mlx5_ifc_modify_rqt_out_bits { 6406 u8 status[0x8]; 6407 u8 reserved_at_8[0x18]; 6408 6409 u8 syndrome[0x20]; 6410 6411 u8 reserved_at_40[0x40]; 6412 }; 6413 6414 struct mlx5_ifc_rqt_bitmask_bits { 6415 u8 reserved_at_0[0x20]; 6416 6417 u8 reserved_at_20[0x1f]; 6418 u8 rqn_list[0x1]; 6419 }; 6420 6421 struct mlx5_ifc_modify_rqt_in_bits { 6422 u8 opcode[0x10]; 6423 u8 uid[0x10]; 6424 6425 u8 reserved_at_20[0x10]; 6426 u8 op_mod[0x10]; 6427 6428 u8 reserved_at_40[0x8]; 6429 u8 rqtn[0x18]; 6430 6431 u8 reserved_at_60[0x20]; 6432 6433 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6434 6435 u8 reserved_at_c0[0x40]; 6436 6437 struct mlx5_ifc_rqtc_bits ctx; 6438 }; 6439 6440 struct mlx5_ifc_modify_rq_out_bits { 6441 u8 status[0x8]; 6442 u8 reserved_at_8[0x18]; 6443 6444 u8 syndrome[0x20]; 6445 6446 u8 reserved_at_40[0x40]; 6447 }; 6448 6449 enum { 6450 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6451 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6452 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6453 }; 6454 6455 struct mlx5_ifc_modify_rq_in_bits { 6456 u8 opcode[0x10]; 6457 u8 uid[0x10]; 6458 6459 u8 reserved_at_20[0x10]; 6460 u8 op_mod[0x10]; 6461 6462 u8 rq_state[0x4]; 6463 u8 reserved_at_44[0x4]; 6464 u8 rqn[0x18]; 6465 6466 u8 reserved_at_60[0x20]; 6467 6468 u8 modify_bitmask[0x40]; 6469 6470 u8 reserved_at_c0[0x40]; 6471 6472 struct mlx5_ifc_rqc_bits ctx; 6473 }; 6474 6475 struct mlx5_ifc_modify_rmp_out_bits { 6476 u8 status[0x8]; 6477 u8 reserved_at_8[0x18]; 6478 6479 u8 syndrome[0x20]; 6480 6481 u8 reserved_at_40[0x40]; 6482 }; 6483 6484 struct mlx5_ifc_rmp_bitmask_bits { 6485 u8 reserved_at_0[0x20]; 6486 6487 u8 reserved_at_20[0x1f]; 6488 u8 lwm[0x1]; 6489 }; 6490 6491 struct mlx5_ifc_modify_rmp_in_bits { 6492 u8 opcode[0x10]; 6493 u8 uid[0x10]; 6494 6495 u8 reserved_at_20[0x10]; 6496 u8 op_mod[0x10]; 6497 6498 u8 rmp_state[0x4]; 6499 u8 reserved_at_44[0x4]; 6500 u8 rmpn[0x18]; 6501 6502 u8 reserved_at_60[0x20]; 6503 6504 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6505 6506 u8 reserved_at_c0[0x40]; 6507 6508 struct mlx5_ifc_rmpc_bits ctx; 6509 }; 6510 6511 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6512 u8 status[0x8]; 6513 u8 reserved_at_8[0x18]; 6514 6515 u8 syndrome[0x20]; 6516 6517 u8 reserved_at_40[0x40]; 6518 }; 6519 6520 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6521 u8 reserved_at_0[0x12]; 6522 u8 affiliation[0x1]; 6523 u8 reserved_at_13[0x1]; 6524 u8 disable_uc_local_lb[0x1]; 6525 u8 disable_mc_local_lb[0x1]; 6526 u8 node_guid[0x1]; 6527 u8 port_guid[0x1]; 6528 u8 min_inline[0x1]; 6529 u8 mtu[0x1]; 6530 u8 change_event[0x1]; 6531 u8 promisc[0x1]; 6532 u8 permanent_address[0x1]; 6533 u8 addresses_list[0x1]; 6534 u8 roce_en[0x1]; 6535 u8 reserved_at_1f[0x1]; 6536 }; 6537 6538 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6539 u8 opcode[0x10]; 6540 u8 reserved_at_10[0x10]; 6541 6542 u8 reserved_at_20[0x10]; 6543 u8 op_mod[0x10]; 6544 6545 u8 other_vport[0x1]; 6546 u8 reserved_at_41[0xf]; 6547 u8 vport_number[0x10]; 6548 6549 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6550 6551 u8 reserved_at_80[0x780]; 6552 6553 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6554 }; 6555 6556 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6557 u8 status[0x8]; 6558 u8 reserved_at_8[0x18]; 6559 6560 u8 syndrome[0x20]; 6561 6562 u8 reserved_at_40[0x40]; 6563 }; 6564 6565 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6566 u8 opcode[0x10]; 6567 u8 reserved_at_10[0x10]; 6568 6569 u8 reserved_at_20[0x10]; 6570 u8 op_mod[0x10]; 6571 6572 u8 other_vport[0x1]; 6573 u8 reserved_at_41[0xb]; 6574 u8 port_num[0x4]; 6575 u8 vport_number[0x10]; 6576 6577 u8 reserved_at_60[0x20]; 6578 6579 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6580 }; 6581 6582 struct mlx5_ifc_modify_cq_out_bits { 6583 u8 status[0x8]; 6584 u8 reserved_at_8[0x18]; 6585 6586 u8 syndrome[0x20]; 6587 6588 u8 reserved_at_40[0x40]; 6589 }; 6590 6591 enum { 6592 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6593 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6594 }; 6595 6596 struct mlx5_ifc_modify_cq_in_bits { 6597 u8 opcode[0x10]; 6598 u8 uid[0x10]; 6599 6600 u8 reserved_at_20[0x10]; 6601 u8 op_mod[0x10]; 6602 6603 u8 reserved_at_40[0x8]; 6604 u8 cqn[0x18]; 6605 6606 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6607 6608 struct mlx5_ifc_cqc_bits cq_context; 6609 6610 u8 reserved_at_280[0x60]; 6611 6612 u8 cq_umem_valid[0x1]; 6613 u8 reserved_at_2e1[0x1f]; 6614 6615 u8 reserved_at_300[0x580]; 6616 6617 u8 pas[][0x40]; 6618 }; 6619 6620 struct mlx5_ifc_modify_cong_status_out_bits { 6621 u8 status[0x8]; 6622 u8 reserved_at_8[0x18]; 6623 6624 u8 syndrome[0x20]; 6625 6626 u8 reserved_at_40[0x40]; 6627 }; 6628 6629 struct mlx5_ifc_modify_cong_status_in_bits { 6630 u8 opcode[0x10]; 6631 u8 reserved_at_10[0x10]; 6632 6633 u8 reserved_at_20[0x10]; 6634 u8 op_mod[0x10]; 6635 6636 u8 reserved_at_40[0x18]; 6637 u8 priority[0x4]; 6638 u8 cong_protocol[0x4]; 6639 6640 u8 enable[0x1]; 6641 u8 tag_enable[0x1]; 6642 u8 reserved_at_62[0x1e]; 6643 }; 6644 6645 struct mlx5_ifc_modify_cong_params_out_bits { 6646 u8 status[0x8]; 6647 u8 reserved_at_8[0x18]; 6648 6649 u8 syndrome[0x20]; 6650 6651 u8 reserved_at_40[0x40]; 6652 }; 6653 6654 struct mlx5_ifc_modify_cong_params_in_bits { 6655 u8 opcode[0x10]; 6656 u8 reserved_at_10[0x10]; 6657 6658 u8 reserved_at_20[0x10]; 6659 u8 op_mod[0x10]; 6660 6661 u8 reserved_at_40[0x1c]; 6662 u8 cong_protocol[0x4]; 6663 6664 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6665 6666 u8 reserved_at_80[0x80]; 6667 6668 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6669 }; 6670 6671 struct mlx5_ifc_manage_pages_out_bits { 6672 u8 status[0x8]; 6673 u8 reserved_at_8[0x18]; 6674 6675 u8 syndrome[0x20]; 6676 6677 u8 output_num_entries[0x20]; 6678 6679 u8 reserved_at_60[0x20]; 6680 6681 u8 pas[][0x40]; 6682 }; 6683 6684 enum { 6685 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6686 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6687 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6688 }; 6689 6690 struct mlx5_ifc_manage_pages_in_bits { 6691 u8 opcode[0x10]; 6692 u8 reserved_at_10[0x10]; 6693 6694 u8 reserved_at_20[0x10]; 6695 u8 op_mod[0x10]; 6696 6697 u8 embedded_cpu_function[0x1]; 6698 u8 reserved_at_41[0xf]; 6699 u8 function_id[0x10]; 6700 6701 u8 input_num_entries[0x20]; 6702 6703 u8 pas[][0x40]; 6704 }; 6705 6706 struct mlx5_ifc_mad_ifc_out_bits { 6707 u8 status[0x8]; 6708 u8 reserved_at_8[0x18]; 6709 6710 u8 syndrome[0x20]; 6711 6712 u8 reserved_at_40[0x40]; 6713 6714 u8 response_mad_packet[256][0x8]; 6715 }; 6716 6717 struct mlx5_ifc_mad_ifc_in_bits { 6718 u8 opcode[0x10]; 6719 u8 reserved_at_10[0x10]; 6720 6721 u8 reserved_at_20[0x10]; 6722 u8 op_mod[0x10]; 6723 6724 u8 remote_lid[0x10]; 6725 u8 reserved_at_50[0x8]; 6726 u8 port[0x8]; 6727 6728 u8 reserved_at_60[0x20]; 6729 6730 u8 mad[256][0x8]; 6731 }; 6732 6733 struct mlx5_ifc_init_hca_out_bits { 6734 u8 status[0x8]; 6735 u8 reserved_at_8[0x18]; 6736 6737 u8 syndrome[0x20]; 6738 6739 u8 reserved_at_40[0x40]; 6740 }; 6741 6742 struct mlx5_ifc_init_hca_in_bits { 6743 u8 opcode[0x10]; 6744 u8 reserved_at_10[0x10]; 6745 6746 u8 reserved_at_20[0x10]; 6747 u8 op_mod[0x10]; 6748 6749 u8 reserved_at_40[0x40]; 6750 u8 sw_owner_id[4][0x20]; 6751 }; 6752 6753 struct mlx5_ifc_init2rtr_qp_out_bits { 6754 u8 status[0x8]; 6755 u8 reserved_at_8[0x18]; 6756 6757 u8 syndrome[0x20]; 6758 6759 u8 reserved_at_40[0x20]; 6760 u8 ece[0x20]; 6761 }; 6762 6763 struct mlx5_ifc_init2rtr_qp_in_bits { 6764 u8 opcode[0x10]; 6765 u8 uid[0x10]; 6766 6767 u8 reserved_at_20[0x10]; 6768 u8 op_mod[0x10]; 6769 6770 u8 reserved_at_40[0x8]; 6771 u8 qpn[0x18]; 6772 6773 u8 reserved_at_60[0x20]; 6774 6775 u8 opt_param_mask[0x20]; 6776 6777 u8 ece[0x20]; 6778 6779 struct mlx5_ifc_qpc_bits qpc; 6780 6781 u8 reserved_at_800[0x80]; 6782 }; 6783 6784 struct mlx5_ifc_init2init_qp_out_bits { 6785 u8 status[0x8]; 6786 u8 reserved_at_8[0x18]; 6787 6788 u8 syndrome[0x20]; 6789 6790 u8 reserved_at_40[0x20]; 6791 u8 ece[0x20]; 6792 }; 6793 6794 struct mlx5_ifc_init2init_qp_in_bits { 6795 u8 opcode[0x10]; 6796 u8 uid[0x10]; 6797 6798 u8 reserved_at_20[0x10]; 6799 u8 op_mod[0x10]; 6800 6801 u8 reserved_at_40[0x8]; 6802 u8 qpn[0x18]; 6803 6804 u8 reserved_at_60[0x20]; 6805 6806 u8 opt_param_mask[0x20]; 6807 6808 u8 ece[0x20]; 6809 6810 struct mlx5_ifc_qpc_bits qpc; 6811 6812 u8 reserved_at_800[0x80]; 6813 }; 6814 6815 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6816 u8 status[0x8]; 6817 u8 reserved_at_8[0x18]; 6818 6819 u8 syndrome[0x20]; 6820 6821 u8 reserved_at_40[0x40]; 6822 6823 u8 packet_headers_log[128][0x8]; 6824 6825 u8 packet_syndrome[64][0x8]; 6826 }; 6827 6828 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6829 u8 opcode[0x10]; 6830 u8 reserved_at_10[0x10]; 6831 6832 u8 reserved_at_20[0x10]; 6833 u8 op_mod[0x10]; 6834 6835 u8 reserved_at_40[0x40]; 6836 }; 6837 6838 struct mlx5_ifc_gen_eqe_in_bits { 6839 u8 opcode[0x10]; 6840 u8 reserved_at_10[0x10]; 6841 6842 u8 reserved_at_20[0x10]; 6843 u8 op_mod[0x10]; 6844 6845 u8 reserved_at_40[0x18]; 6846 u8 eq_number[0x8]; 6847 6848 u8 reserved_at_60[0x20]; 6849 6850 u8 eqe[64][0x8]; 6851 }; 6852 6853 struct mlx5_ifc_gen_eq_out_bits { 6854 u8 status[0x8]; 6855 u8 reserved_at_8[0x18]; 6856 6857 u8 syndrome[0x20]; 6858 6859 u8 reserved_at_40[0x40]; 6860 }; 6861 6862 struct mlx5_ifc_enable_hca_out_bits { 6863 u8 status[0x8]; 6864 u8 reserved_at_8[0x18]; 6865 6866 u8 syndrome[0x20]; 6867 6868 u8 reserved_at_40[0x20]; 6869 }; 6870 6871 struct mlx5_ifc_enable_hca_in_bits { 6872 u8 opcode[0x10]; 6873 u8 reserved_at_10[0x10]; 6874 6875 u8 reserved_at_20[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 embedded_cpu_function[0x1]; 6879 u8 reserved_at_41[0xf]; 6880 u8 function_id[0x10]; 6881 6882 u8 reserved_at_60[0x20]; 6883 }; 6884 6885 struct mlx5_ifc_drain_dct_out_bits { 6886 u8 status[0x8]; 6887 u8 reserved_at_8[0x18]; 6888 6889 u8 syndrome[0x20]; 6890 6891 u8 reserved_at_40[0x40]; 6892 }; 6893 6894 struct mlx5_ifc_drain_dct_in_bits { 6895 u8 opcode[0x10]; 6896 u8 uid[0x10]; 6897 6898 u8 reserved_at_20[0x10]; 6899 u8 op_mod[0x10]; 6900 6901 u8 reserved_at_40[0x8]; 6902 u8 dctn[0x18]; 6903 6904 u8 reserved_at_60[0x20]; 6905 }; 6906 6907 struct mlx5_ifc_disable_hca_out_bits { 6908 u8 status[0x8]; 6909 u8 reserved_at_8[0x18]; 6910 6911 u8 syndrome[0x20]; 6912 6913 u8 reserved_at_40[0x20]; 6914 }; 6915 6916 struct mlx5_ifc_disable_hca_in_bits { 6917 u8 opcode[0x10]; 6918 u8 reserved_at_10[0x10]; 6919 6920 u8 reserved_at_20[0x10]; 6921 u8 op_mod[0x10]; 6922 6923 u8 embedded_cpu_function[0x1]; 6924 u8 reserved_at_41[0xf]; 6925 u8 function_id[0x10]; 6926 6927 u8 reserved_at_60[0x20]; 6928 }; 6929 6930 struct mlx5_ifc_detach_from_mcg_out_bits { 6931 u8 status[0x8]; 6932 u8 reserved_at_8[0x18]; 6933 6934 u8 syndrome[0x20]; 6935 6936 u8 reserved_at_40[0x40]; 6937 }; 6938 6939 struct mlx5_ifc_detach_from_mcg_in_bits { 6940 u8 opcode[0x10]; 6941 u8 uid[0x10]; 6942 6943 u8 reserved_at_20[0x10]; 6944 u8 op_mod[0x10]; 6945 6946 u8 reserved_at_40[0x8]; 6947 u8 qpn[0x18]; 6948 6949 u8 reserved_at_60[0x20]; 6950 6951 u8 multicast_gid[16][0x8]; 6952 }; 6953 6954 struct mlx5_ifc_destroy_xrq_out_bits { 6955 u8 status[0x8]; 6956 u8 reserved_at_8[0x18]; 6957 6958 u8 syndrome[0x20]; 6959 6960 u8 reserved_at_40[0x40]; 6961 }; 6962 6963 struct mlx5_ifc_destroy_xrq_in_bits { 6964 u8 opcode[0x10]; 6965 u8 uid[0x10]; 6966 6967 u8 reserved_at_20[0x10]; 6968 u8 op_mod[0x10]; 6969 6970 u8 reserved_at_40[0x8]; 6971 u8 xrqn[0x18]; 6972 6973 u8 reserved_at_60[0x20]; 6974 }; 6975 6976 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6977 u8 status[0x8]; 6978 u8 reserved_at_8[0x18]; 6979 6980 u8 syndrome[0x20]; 6981 6982 u8 reserved_at_40[0x40]; 6983 }; 6984 6985 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6986 u8 opcode[0x10]; 6987 u8 uid[0x10]; 6988 6989 u8 reserved_at_20[0x10]; 6990 u8 op_mod[0x10]; 6991 6992 u8 reserved_at_40[0x8]; 6993 u8 xrc_srqn[0x18]; 6994 6995 u8 reserved_at_60[0x20]; 6996 }; 6997 6998 struct mlx5_ifc_destroy_tis_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x40]; 7005 }; 7006 7007 struct mlx5_ifc_destroy_tis_in_bits { 7008 u8 opcode[0x10]; 7009 u8 uid[0x10]; 7010 7011 u8 reserved_at_20[0x10]; 7012 u8 op_mod[0x10]; 7013 7014 u8 reserved_at_40[0x8]; 7015 u8 tisn[0x18]; 7016 7017 u8 reserved_at_60[0x20]; 7018 }; 7019 7020 struct mlx5_ifc_destroy_tir_out_bits { 7021 u8 status[0x8]; 7022 u8 reserved_at_8[0x18]; 7023 7024 u8 syndrome[0x20]; 7025 7026 u8 reserved_at_40[0x40]; 7027 }; 7028 7029 struct mlx5_ifc_destroy_tir_in_bits { 7030 u8 opcode[0x10]; 7031 u8 uid[0x10]; 7032 7033 u8 reserved_at_20[0x10]; 7034 u8 op_mod[0x10]; 7035 7036 u8 reserved_at_40[0x8]; 7037 u8 tirn[0x18]; 7038 7039 u8 reserved_at_60[0x20]; 7040 }; 7041 7042 struct mlx5_ifc_destroy_srq_out_bits { 7043 u8 status[0x8]; 7044 u8 reserved_at_8[0x18]; 7045 7046 u8 syndrome[0x20]; 7047 7048 u8 reserved_at_40[0x40]; 7049 }; 7050 7051 struct mlx5_ifc_destroy_srq_in_bits { 7052 u8 opcode[0x10]; 7053 u8 uid[0x10]; 7054 7055 u8 reserved_at_20[0x10]; 7056 u8 op_mod[0x10]; 7057 7058 u8 reserved_at_40[0x8]; 7059 u8 srqn[0x18]; 7060 7061 u8 reserved_at_60[0x20]; 7062 }; 7063 7064 struct mlx5_ifc_destroy_sq_out_bits { 7065 u8 status[0x8]; 7066 u8 reserved_at_8[0x18]; 7067 7068 u8 syndrome[0x20]; 7069 7070 u8 reserved_at_40[0x40]; 7071 }; 7072 7073 struct mlx5_ifc_destroy_sq_in_bits { 7074 u8 opcode[0x10]; 7075 u8 uid[0x10]; 7076 7077 u8 reserved_at_20[0x10]; 7078 u8 op_mod[0x10]; 7079 7080 u8 reserved_at_40[0x8]; 7081 u8 sqn[0x18]; 7082 7083 u8 reserved_at_60[0x20]; 7084 }; 7085 7086 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7087 u8 status[0x8]; 7088 u8 reserved_at_8[0x18]; 7089 7090 u8 syndrome[0x20]; 7091 7092 u8 reserved_at_40[0x1c0]; 7093 }; 7094 7095 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7096 u8 opcode[0x10]; 7097 u8 reserved_at_10[0x10]; 7098 7099 u8 reserved_at_20[0x10]; 7100 u8 op_mod[0x10]; 7101 7102 u8 scheduling_hierarchy[0x8]; 7103 u8 reserved_at_48[0x18]; 7104 7105 u8 scheduling_element_id[0x20]; 7106 7107 u8 reserved_at_80[0x180]; 7108 }; 7109 7110 struct mlx5_ifc_destroy_rqt_out_bits { 7111 u8 status[0x8]; 7112 u8 reserved_at_8[0x18]; 7113 7114 u8 syndrome[0x20]; 7115 7116 u8 reserved_at_40[0x40]; 7117 }; 7118 7119 struct mlx5_ifc_destroy_rqt_in_bits { 7120 u8 opcode[0x10]; 7121 u8 uid[0x10]; 7122 7123 u8 reserved_at_20[0x10]; 7124 u8 op_mod[0x10]; 7125 7126 u8 reserved_at_40[0x8]; 7127 u8 rqtn[0x18]; 7128 7129 u8 reserved_at_60[0x20]; 7130 }; 7131 7132 struct mlx5_ifc_destroy_rq_out_bits { 7133 u8 status[0x8]; 7134 u8 reserved_at_8[0x18]; 7135 7136 u8 syndrome[0x20]; 7137 7138 u8 reserved_at_40[0x40]; 7139 }; 7140 7141 struct mlx5_ifc_destroy_rq_in_bits { 7142 u8 opcode[0x10]; 7143 u8 uid[0x10]; 7144 7145 u8 reserved_at_20[0x10]; 7146 u8 op_mod[0x10]; 7147 7148 u8 reserved_at_40[0x8]; 7149 u8 rqn[0x18]; 7150 7151 u8 reserved_at_60[0x20]; 7152 }; 7153 7154 struct mlx5_ifc_set_delay_drop_params_in_bits { 7155 u8 opcode[0x10]; 7156 u8 reserved_at_10[0x10]; 7157 7158 u8 reserved_at_20[0x10]; 7159 u8 op_mod[0x10]; 7160 7161 u8 reserved_at_40[0x20]; 7162 7163 u8 reserved_at_60[0x10]; 7164 u8 delay_drop_timeout[0x10]; 7165 }; 7166 7167 struct mlx5_ifc_set_delay_drop_params_out_bits { 7168 u8 status[0x8]; 7169 u8 reserved_at_8[0x18]; 7170 7171 u8 syndrome[0x20]; 7172 7173 u8 reserved_at_40[0x40]; 7174 }; 7175 7176 struct mlx5_ifc_destroy_rmp_out_bits { 7177 u8 status[0x8]; 7178 u8 reserved_at_8[0x18]; 7179 7180 u8 syndrome[0x20]; 7181 7182 u8 reserved_at_40[0x40]; 7183 }; 7184 7185 struct mlx5_ifc_destroy_rmp_in_bits { 7186 u8 opcode[0x10]; 7187 u8 uid[0x10]; 7188 7189 u8 reserved_at_20[0x10]; 7190 u8 op_mod[0x10]; 7191 7192 u8 reserved_at_40[0x8]; 7193 u8 rmpn[0x18]; 7194 7195 u8 reserved_at_60[0x20]; 7196 }; 7197 7198 struct mlx5_ifc_destroy_qp_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_at_8[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_at_40[0x40]; 7205 }; 7206 7207 struct mlx5_ifc_destroy_qp_in_bits { 7208 u8 opcode[0x10]; 7209 u8 uid[0x10]; 7210 7211 u8 reserved_at_20[0x10]; 7212 u8 op_mod[0x10]; 7213 7214 u8 reserved_at_40[0x8]; 7215 u8 qpn[0x18]; 7216 7217 u8 reserved_at_60[0x20]; 7218 }; 7219 7220 struct mlx5_ifc_destroy_psv_out_bits { 7221 u8 status[0x8]; 7222 u8 reserved_at_8[0x18]; 7223 7224 u8 syndrome[0x20]; 7225 7226 u8 reserved_at_40[0x40]; 7227 }; 7228 7229 struct mlx5_ifc_destroy_psv_in_bits { 7230 u8 opcode[0x10]; 7231 u8 reserved_at_10[0x10]; 7232 7233 u8 reserved_at_20[0x10]; 7234 u8 op_mod[0x10]; 7235 7236 u8 reserved_at_40[0x8]; 7237 u8 psvn[0x18]; 7238 7239 u8 reserved_at_60[0x20]; 7240 }; 7241 7242 struct mlx5_ifc_destroy_mkey_out_bits { 7243 u8 status[0x8]; 7244 u8 reserved_at_8[0x18]; 7245 7246 u8 syndrome[0x20]; 7247 7248 u8 reserved_at_40[0x40]; 7249 }; 7250 7251 struct mlx5_ifc_destroy_mkey_in_bits { 7252 u8 opcode[0x10]; 7253 u8 uid[0x10]; 7254 7255 u8 reserved_at_20[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 reserved_at_40[0x8]; 7259 u8 mkey_index[0x18]; 7260 7261 u8 reserved_at_60[0x20]; 7262 }; 7263 7264 struct mlx5_ifc_destroy_flow_table_out_bits { 7265 u8 status[0x8]; 7266 u8 reserved_at_8[0x18]; 7267 7268 u8 syndrome[0x20]; 7269 7270 u8 reserved_at_40[0x40]; 7271 }; 7272 7273 struct mlx5_ifc_destroy_flow_table_in_bits { 7274 u8 opcode[0x10]; 7275 u8 reserved_at_10[0x10]; 7276 7277 u8 reserved_at_20[0x10]; 7278 u8 op_mod[0x10]; 7279 7280 u8 other_vport[0x1]; 7281 u8 reserved_at_41[0xf]; 7282 u8 vport_number[0x10]; 7283 7284 u8 reserved_at_60[0x20]; 7285 7286 u8 table_type[0x8]; 7287 u8 reserved_at_88[0x18]; 7288 7289 u8 reserved_at_a0[0x8]; 7290 u8 table_id[0x18]; 7291 7292 u8 reserved_at_c0[0x140]; 7293 }; 7294 7295 struct mlx5_ifc_destroy_flow_group_out_bits { 7296 u8 status[0x8]; 7297 u8 reserved_at_8[0x18]; 7298 7299 u8 syndrome[0x20]; 7300 7301 u8 reserved_at_40[0x40]; 7302 }; 7303 7304 struct mlx5_ifc_destroy_flow_group_in_bits { 7305 u8 opcode[0x10]; 7306 u8 reserved_at_10[0x10]; 7307 7308 u8 reserved_at_20[0x10]; 7309 u8 op_mod[0x10]; 7310 7311 u8 other_vport[0x1]; 7312 u8 reserved_at_41[0xf]; 7313 u8 vport_number[0x10]; 7314 7315 u8 reserved_at_60[0x20]; 7316 7317 u8 table_type[0x8]; 7318 u8 reserved_at_88[0x18]; 7319 7320 u8 reserved_at_a0[0x8]; 7321 u8 table_id[0x18]; 7322 7323 u8 group_id[0x20]; 7324 7325 u8 reserved_at_e0[0x120]; 7326 }; 7327 7328 struct mlx5_ifc_destroy_eq_out_bits { 7329 u8 status[0x8]; 7330 u8 reserved_at_8[0x18]; 7331 7332 u8 syndrome[0x20]; 7333 7334 u8 reserved_at_40[0x40]; 7335 }; 7336 7337 struct mlx5_ifc_destroy_eq_in_bits { 7338 u8 opcode[0x10]; 7339 u8 reserved_at_10[0x10]; 7340 7341 u8 reserved_at_20[0x10]; 7342 u8 op_mod[0x10]; 7343 7344 u8 reserved_at_40[0x18]; 7345 u8 eq_number[0x8]; 7346 7347 u8 reserved_at_60[0x20]; 7348 }; 7349 7350 struct mlx5_ifc_destroy_dct_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_at_8[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 reserved_at_40[0x40]; 7357 }; 7358 7359 struct mlx5_ifc_destroy_dct_in_bits { 7360 u8 opcode[0x10]; 7361 u8 uid[0x10]; 7362 7363 u8 reserved_at_20[0x10]; 7364 u8 op_mod[0x10]; 7365 7366 u8 reserved_at_40[0x8]; 7367 u8 dctn[0x18]; 7368 7369 u8 reserved_at_60[0x20]; 7370 }; 7371 7372 struct mlx5_ifc_destroy_cq_out_bits { 7373 u8 status[0x8]; 7374 u8 reserved_at_8[0x18]; 7375 7376 u8 syndrome[0x20]; 7377 7378 u8 reserved_at_40[0x40]; 7379 }; 7380 7381 struct mlx5_ifc_destroy_cq_in_bits { 7382 u8 opcode[0x10]; 7383 u8 uid[0x10]; 7384 7385 u8 reserved_at_20[0x10]; 7386 u8 op_mod[0x10]; 7387 7388 u8 reserved_at_40[0x8]; 7389 u8 cqn[0x18]; 7390 7391 u8 reserved_at_60[0x20]; 7392 }; 7393 7394 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7395 u8 status[0x8]; 7396 u8 reserved_at_8[0x18]; 7397 7398 u8 syndrome[0x20]; 7399 7400 u8 reserved_at_40[0x40]; 7401 }; 7402 7403 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7404 u8 opcode[0x10]; 7405 u8 reserved_at_10[0x10]; 7406 7407 u8 reserved_at_20[0x10]; 7408 u8 op_mod[0x10]; 7409 7410 u8 reserved_at_40[0x20]; 7411 7412 u8 reserved_at_60[0x10]; 7413 u8 vxlan_udp_port[0x10]; 7414 }; 7415 7416 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7417 u8 status[0x8]; 7418 u8 reserved_at_8[0x18]; 7419 7420 u8 syndrome[0x20]; 7421 7422 u8 reserved_at_40[0x40]; 7423 }; 7424 7425 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7426 u8 opcode[0x10]; 7427 u8 reserved_at_10[0x10]; 7428 7429 u8 reserved_at_20[0x10]; 7430 u8 op_mod[0x10]; 7431 7432 u8 reserved_at_40[0x60]; 7433 7434 u8 reserved_at_a0[0x8]; 7435 u8 table_index[0x18]; 7436 7437 u8 reserved_at_c0[0x140]; 7438 }; 7439 7440 struct mlx5_ifc_delete_fte_out_bits { 7441 u8 status[0x8]; 7442 u8 reserved_at_8[0x18]; 7443 7444 u8 syndrome[0x20]; 7445 7446 u8 reserved_at_40[0x40]; 7447 }; 7448 7449 struct mlx5_ifc_delete_fte_in_bits { 7450 u8 opcode[0x10]; 7451 u8 reserved_at_10[0x10]; 7452 7453 u8 reserved_at_20[0x10]; 7454 u8 op_mod[0x10]; 7455 7456 u8 other_vport[0x1]; 7457 u8 reserved_at_41[0xf]; 7458 u8 vport_number[0x10]; 7459 7460 u8 reserved_at_60[0x20]; 7461 7462 u8 table_type[0x8]; 7463 u8 reserved_at_88[0x18]; 7464 7465 u8 reserved_at_a0[0x8]; 7466 u8 table_id[0x18]; 7467 7468 u8 reserved_at_c0[0x40]; 7469 7470 u8 flow_index[0x20]; 7471 7472 u8 reserved_at_120[0xe0]; 7473 }; 7474 7475 struct mlx5_ifc_dealloc_xrcd_out_bits { 7476 u8 status[0x8]; 7477 u8 reserved_at_8[0x18]; 7478 7479 u8 syndrome[0x20]; 7480 7481 u8 reserved_at_40[0x40]; 7482 }; 7483 7484 struct mlx5_ifc_dealloc_xrcd_in_bits { 7485 u8 opcode[0x10]; 7486 u8 uid[0x10]; 7487 7488 u8 reserved_at_20[0x10]; 7489 u8 op_mod[0x10]; 7490 7491 u8 reserved_at_40[0x8]; 7492 u8 xrcd[0x18]; 7493 7494 u8 reserved_at_60[0x20]; 7495 }; 7496 7497 struct mlx5_ifc_dealloc_uar_out_bits { 7498 u8 status[0x8]; 7499 u8 reserved_at_8[0x18]; 7500 7501 u8 syndrome[0x20]; 7502 7503 u8 reserved_at_40[0x40]; 7504 }; 7505 7506 struct mlx5_ifc_dealloc_uar_in_bits { 7507 u8 opcode[0x10]; 7508 u8 reserved_at_10[0x10]; 7509 7510 u8 reserved_at_20[0x10]; 7511 u8 op_mod[0x10]; 7512 7513 u8 reserved_at_40[0x8]; 7514 u8 uar[0x18]; 7515 7516 u8 reserved_at_60[0x20]; 7517 }; 7518 7519 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7520 u8 status[0x8]; 7521 u8 reserved_at_8[0x18]; 7522 7523 u8 syndrome[0x20]; 7524 7525 u8 reserved_at_40[0x40]; 7526 }; 7527 7528 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7529 u8 opcode[0x10]; 7530 u8 uid[0x10]; 7531 7532 u8 reserved_at_20[0x10]; 7533 u8 op_mod[0x10]; 7534 7535 u8 reserved_at_40[0x8]; 7536 u8 transport_domain[0x18]; 7537 7538 u8 reserved_at_60[0x20]; 7539 }; 7540 7541 struct mlx5_ifc_dealloc_q_counter_out_bits { 7542 u8 status[0x8]; 7543 u8 reserved_at_8[0x18]; 7544 7545 u8 syndrome[0x20]; 7546 7547 u8 reserved_at_40[0x40]; 7548 }; 7549 7550 struct mlx5_ifc_dealloc_q_counter_in_bits { 7551 u8 opcode[0x10]; 7552 u8 reserved_at_10[0x10]; 7553 7554 u8 reserved_at_20[0x10]; 7555 u8 op_mod[0x10]; 7556 7557 u8 reserved_at_40[0x18]; 7558 u8 counter_set_id[0x8]; 7559 7560 u8 reserved_at_60[0x20]; 7561 }; 7562 7563 struct mlx5_ifc_dealloc_pd_out_bits { 7564 u8 status[0x8]; 7565 u8 reserved_at_8[0x18]; 7566 7567 u8 syndrome[0x20]; 7568 7569 u8 reserved_at_40[0x40]; 7570 }; 7571 7572 struct mlx5_ifc_dealloc_pd_in_bits { 7573 u8 opcode[0x10]; 7574 u8 uid[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 reserved_at_40[0x8]; 7580 u8 pd[0x18]; 7581 7582 u8 reserved_at_60[0x20]; 7583 }; 7584 7585 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7586 u8 status[0x8]; 7587 u8 reserved_at_8[0x18]; 7588 7589 u8 syndrome[0x20]; 7590 7591 u8 reserved_at_40[0x40]; 7592 }; 7593 7594 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7595 u8 opcode[0x10]; 7596 u8 reserved_at_10[0x10]; 7597 7598 u8 reserved_at_20[0x10]; 7599 u8 op_mod[0x10]; 7600 7601 u8 flow_counter_id[0x20]; 7602 7603 u8 reserved_at_60[0x20]; 7604 }; 7605 7606 struct mlx5_ifc_create_xrq_out_bits { 7607 u8 status[0x8]; 7608 u8 reserved_at_8[0x18]; 7609 7610 u8 syndrome[0x20]; 7611 7612 u8 reserved_at_40[0x8]; 7613 u8 xrqn[0x18]; 7614 7615 u8 reserved_at_60[0x20]; 7616 }; 7617 7618 struct mlx5_ifc_create_xrq_in_bits { 7619 u8 opcode[0x10]; 7620 u8 uid[0x10]; 7621 7622 u8 reserved_at_20[0x10]; 7623 u8 op_mod[0x10]; 7624 7625 u8 reserved_at_40[0x40]; 7626 7627 struct mlx5_ifc_xrqc_bits xrq_context; 7628 }; 7629 7630 struct mlx5_ifc_create_xrc_srq_out_bits { 7631 u8 status[0x8]; 7632 u8 reserved_at_8[0x18]; 7633 7634 u8 syndrome[0x20]; 7635 7636 u8 reserved_at_40[0x8]; 7637 u8 xrc_srqn[0x18]; 7638 7639 u8 reserved_at_60[0x20]; 7640 }; 7641 7642 struct mlx5_ifc_create_xrc_srq_in_bits { 7643 u8 opcode[0x10]; 7644 u8 uid[0x10]; 7645 7646 u8 reserved_at_20[0x10]; 7647 u8 op_mod[0x10]; 7648 7649 u8 reserved_at_40[0x40]; 7650 7651 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7652 7653 u8 reserved_at_280[0x60]; 7654 7655 u8 xrc_srq_umem_valid[0x1]; 7656 u8 reserved_at_2e1[0x1f]; 7657 7658 u8 reserved_at_300[0x580]; 7659 7660 u8 pas[][0x40]; 7661 }; 7662 7663 struct mlx5_ifc_create_tis_out_bits { 7664 u8 status[0x8]; 7665 u8 reserved_at_8[0x18]; 7666 7667 u8 syndrome[0x20]; 7668 7669 u8 reserved_at_40[0x8]; 7670 u8 tisn[0x18]; 7671 7672 u8 reserved_at_60[0x20]; 7673 }; 7674 7675 struct mlx5_ifc_create_tis_in_bits { 7676 u8 opcode[0x10]; 7677 u8 uid[0x10]; 7678 7679 u8 reserved_at_20[0x10]; 7680 u8 op_mod[0x10]; 7681 7682 u8 reserved_at_40[0xc0]; 7683 7684 struct mlx5_ifc_tisc_bits ctx; 7685 }; 7686 7687 struct mlx5_ifc_create_tir_out_bits { 7688 u8 status[0x8]; 7689 u8 icm_address_63_40[0x18]; 7690 7691 u8 syndrome[0x20]; 7692 7693 u8 icm_address_39_32[0x8]; 7694 u8 tirn[0x18]; 7695 7696 u8 icm_address_31_0[0x20]; 7697 }; 7698 7699 struct mlx5_ifc_create_tir_in_bits { 7700 u8 opcode[0x10]; 7701 u8 uid[0x10]; 7702 7703 u8 reserved_at_20[0x10]; 7704 u8 op_mod[0x10]; 7705 7706 u8 reserved_at_40[0xc0]; 7707 7708 struct mlx5_ifc_tirc_bits ctx; 7709 }; 7710 7711 struct mlx5_ifc_create_srq_out_bits { 7712 u8 status[0x8]; 7713 u8 reserved_at_8[0x18]; 7714 7715 u8 syndrome[0x20]; 7716 7717 u8 reserved_at_40[0x8]; 7718 u8 srqn[0x18]; 7719 7720 u8 reserved_at_60[0x20]; 7721 }; 7722 7723 struct mlx5_ifc_create_srq_in_bits { 7724 u8 opcode[0x10]; 7725 u8 uid[0x10]; 7726 7727 u8 reserved_at_20[0x10]; 7728 u8 op_mod[0x10]; 7729 7730 u8 reserved_at_40[0x40]; 7731 7732 struct mlx5_ifc_srqc_bits srq_context_entry; 7733 7734 u8 reserved_at_280[0x600]; 7735 7736 u8 pas[][0x40]; 7737 }; 7738 7739 struct mlx5_ifc_create_sq_out_bits { 7740 u8 status[0x8]; 7741 u8 reserved_at_8[0x18]; 7742 7743 u8 syndrome[0x20]; 7744 7745 u8 reserved_at_40[0x8]; 7746 u8 sqn[0x18]; 7747 7748 u8 reserved_at_60[0x20]; 7749 }; 7750 7751 struct mlx5_ifc_create_sq_in_bits { 7752 u8 opcode[0x10]; 7753 u8 uid[0x10]; 7754 7755 u8 reserved_at_20[0x10]; 7756 u8 op_mod[0x10]; 7757 7758 u8 reserved_at_40[0xc0]; 7759 7760 struct mlx5_ifc_sqc_bits ctx; 7761 }; 7762 7763 struct mlx5_ifc_create_scheduling_element_out_bits { 7764 u8 status[0x8]; 7765 u8 reserved_at_8[0x18]; 7766 7767 u8 syndrome[0x20]; 7768 7769 u8 reserved_at_40[0x40]; 7770 7771 u8 scheduling_element_id[0x20]; 7772 7773 u8 reserved_at_a0[0x160]; 7774 }; 7775 7776 struct mlx5_ifc_create_scheduling_element_in_bits { 7777 u8 opcode[0x10]; 7778 u8 reserved_at_10[0x10]; 7779 7780 u8 reserved_at_20[0x10]; 7781 u8 op_mod[0x10]; 7782 7783 u8 scheduling_hierarchy[0x8]; 7784 u8 reserved_at_48[0x18]; 7785 7786 u8 reserved_at_60[0xa0]; 7787 7788 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7789 7790 u8 reserved_at_300[0x100]; 7791 }; 7792 7793 struct mlx5_ifc_create_rqt_out_bits { 7794 u8 status[0x8]; 7795 u8 reserved_at_8[0x18]; 7796 7797 u8 syndrome[0x20]; 7798 7799 u8 reserved_at_40[0x8]; 7800 u8 rqtn[0x18]; 7801 7802 u8 reserved_at_60[0x20]; 7803 }; 7804 7805 struct mlx5_ifc_create_rqt_in_bits { 7806 u8 opcode[0x10]; 7807 u8 uid[0x10]; 7808 7809 u8 reserved_at_20[0x10]; 7810 u8 op_mod[0x10]; 7811 7812 u8 reserved_at_40[0xc0]; 7813 7814 struct mlx5_ifc_rqtc_bits rqt_context; 7815 }; 7816 7817 struct mlx5_ifc_create_rq_out_bits { 7818 u8 status[0x8]; 7819 u8 reserved_at_8[0x18]; 7820 7821 u8 syndrome[0x20]; 7822 7823 u8 reserved_at_40[0x8]; 7824 u8 rqn[0x18]; 7825 7826 u8 reserved_at_60[0x20]; 7827 }; 7828 7829 struct mlx5_ifc_create_rq_in_bits { 7830 u8 opcode[0x10]; 7831 u8 uid[0x10]; 7832 7833 u8 reserved_at_20[0x10]; 7834 u8 op_mod[0x10]; 7835 7836 u8 reserved_at_40[0xc0]; 7837 7838 struct mlx5_ifc_rqc_bits ctx; 7839 }; 7840 7841 struct mlx5_ifc_create_rmp_out_bits { 7842 u8 status[0x8]; 7843 u8 reserved_at_8[0x18]; 7844 7845 u8 syndrome[0x20]; 7846 7847 u8 reserved_at_40[0x8]; 7848 u8 rmpn[0x18]; 7849 7850 u8 reserved_at_60[0x20]; 7851 }; 7852 7853 struct mlx5_ifc_create_rmp_in_bits { 7854 u8 opcode[0x10]; 7855 u8 uid[0x10]; 7856 7857 u8 reserved_at_20[0x10]; 7858 u8 op_mod[0x10]; 7859 7860 u8 reserved_at_40[0xc0]; 7861 7862 struct mlx5_ifc_rmpc_bits ctx; 7863 }; 7864 7865 struct mlx5_ifc_create_qp_out_bits { 7866 u8 status[0x8]; 7867 u8 reserved_at_8[0x18]; 7868 7869 u8 syndrome[0x20]; 7870 7871 u8 reserved_at_40[0x8]; 7872 u8 qpn[0x18]; 7873 7874 u8 ece[0x20]; 7875 }; 7876 7877 struct mlx5_ifc_create_qp_in_bits { 7878 u8 opcode[0x10]; 7879 u8 uid[0x10]; 7880 7881 u8 reserved_at_20[0x10]; 7882 u8 op_mod[0x10]; 7883 7884 u8 reserved_at_40[0x8]; 7885 u8 input_qpn[0x18]; 7886 7887 u8 reserved_at_60[0x20]; 7888 u8 opt_param_mask[0x20]; 7889 7890 u8 ece[0x20]; 7891 7892 struct mlx5_ifc_qpc_bits qpc; 7893 7894 u8 reserved_at_800[0x60]; 7895 7896 u8 wq_umem_valid[0x1]; 7897 u8 reserved_at_861[0x1f]; 7898 7899 u8 pas[][0x40]; 7900 }; 7901 7902 struct mlx5_ifc_create_psv_out_bits { 7903 u8 status[0x8]; 7904 u8 reserved_at_8[0x18]; 7905 7906 u8 syndrome[0x20]; 7907 7908 u8 reserved_at_40[0x40]; 7909 7910 u8 reserved_at_80[0x8]; 7911 u8 psv0_index[0x18]; 7912 7913 u8 reserved_at_a0[0x8]; 7914 u8 psv1_index[0x18]; 7915 7916 u8 reserved_at_c0[0x8]; 7917 u8 psv2_index[0x18]; 7918 7919 u8 reserved_at_e0[0x8]; 7920 u8 psv3_index[0x18]; 7921 }; 7922 7923 struct mlx5_ifc_create_psv_in_bits { 7924 u8 opcode[0x10]; 7925 u8 reserved_at_10[0x10]; 7926 7927 u8 reserved_at_20[0x10]; 7928 u8 op_mod[0x10]; 7929 7930 u8 num_psv[0x4]; 7931 u8 reserved_at_44[0x4]; 7932 u8 pd[0x18]; 7933 7934 u8 reserved_at_60[0x20]; 7935 }; 7936 7937 struct mlx5_ifc_create_mkey_out_bits { 7938 u8 status[0x8]; 7939 u8 reserved_at_8[0x18]; 7940 7941 u8 syndrome[0x20]; 7942 7943 u8 reserved_at_40[0x8]; 7944 u8 mkey_index[0x18]; 7945 7946 u8 reserved_at_60[0x20]; 7947 }; 7948 7949 struct mlx5_ifc_create_mkey_in_bits { 7950 u8 opcode[0x10]; 7951 u8 uid[0x10]; 7952 7953 u8 reserved_at_20[0x10]; 7954 u8 op_mod[0x10]; 7955 7956 u8 reserved_at_40[0x20]; 7957 7958 u8 pg_access[0x1]; 7959 u8 mkey_umem_valid[0x1]; 7960 u8 reserved_at_62[0x1e]; 7961 7962 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7963 7964 u8 reserved_at_280[0x80]; 7965 7966 u8 translations_octword_actual_size[0x20]; 7967 7968 u8 reserved_at_320[0x560]; 7969 7970 u8 klm_pas_mtt[][0x20]; 7971 }; 7972 7973 enum { 7974 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7975 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7976 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7977 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7978 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7979 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7980 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7981 }; 7982 7983 struct mlx5_ifc_create_flow_table_out_bits { 7984 u8 status[0x8]; 7985 u8 icm_address_63_40[0x18]; 7986 7987 u8 syndrome[0x20]; 7988 7989 u8 icm_address_39_32[0x8]; 7990 u8 table_id[0x18]; 7991 7992 u8 icm_address_31_0[0x20]; 7993 }; 7994 7995 struct mlx5_ifc_create_flow_table_in_bits { 7996 u8 opcode[0x10]; 7997 u8 reserved_at_10[0x10]; 7998 7999 u8 reserved_at_20[0x10]; 8000 u8 op_mod[0x10]; 8001 8002 u8 other_vport[0x1]; 8003 u8 reserved_at_41[0xf]; 8004 u8 vport_number[0x10]; 8005 8006 u8 reserved_at_60[0x20]; 8007 8008 u8 table_type[0x8]; 8009 u8 reserved_at_88[0x18]; 8010 8011 u8 reserved_at_a0[0x20]; 8012 8013 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8014 }; 8015 8016 struct mlx5_ifc_create_flow_group_out_bits { 8017 u8 status[0x8]; 8018 u8 reserved_at_8[0x18]; 8019 8020 u8 syndrome[0x20]; 8021 8022 u8 reserved_at_40[0x8]; 8023 u8 group_id[0x18]; 8024 8025 u8 reserved_at_60[0x20]; 8026 }; 8027 8028 enum { 8029 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8030 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8031 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8032 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8033 }; 8034 8035 struct mlx5_ifc_create_flow_group_in_bits { 8036 u8 opcode[0x10]; 8037 u8 reserved_at_10[0x10]; 8038 8039 u8 reserved_at_20[0x10]; 8040 u8 op_mod[0x10]; 8041 8042 u8 other_vport[0x1]; 8043 u8 reserved_at_41[0xf]; 8044 u8 vport_number[0x10]; 8045 8046 u8 reserved_at_60[0x20]; 8047 8048 u8 table_type[0x8]; 8049 u8 reserved_at_88[0x18]; 8050 8051 u8 reserved_at_a0[0x8]; 8052 u8 table_id[0x18]; 8053 8054 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8055 8056 u8 reserved_at_c1[0x1f]; 8057 8058 u8 start_flow_index[0x20]; 8059 8060 u8 reserved_at_100[0x20]; 8061 8062 u8 end_flow_index[0x20]; 8063 8064 u8 reserved_at_140[0xa0]; 8065 8066 u8 reserved_at_1e0[0x18]; 8067 u8 match_criteria_enable[0x8]; 8068 8069 struct mlx5_ifc_fte_match_param_bits match_criteria; 8070 8071 u8 reserved_at_1200[0xe00]; 8072 }; 8073 8074 struct mlx5_ifc_create_eq_out_bits { 8075 u8 status[0x8]; 8076 u8 reserved_at_8[0x18]; 8077 8078 u8 syndrome[0x20]; 8079 8080 u8 reserved_at_40[0x18]; 8081 u8 eq_number[0x8]; 8082 8083 u8 reserved_at_60[0x20]; 8084 }; 8085 8086 struct mlx5_ifc_create_eq_in_bits { 8087 u8 opcode[0x10]; 8088 u8 uid[0x10]; 8089 8090 u8 reserved_at_20[0x10]; 8091 u8 op_mod[0x10]; 8092 8093 u8 reserved_at_40[0x40]; 8094 8095 struct mlx5_ifc_eqc_bits eq_context_entry; 8096 8097 u8 reserved_at_280[0x40]; 8098 8099 u8 event_bitmask[4][0x40]; 8100 8101 u8 reserved_at_3c0[0x4c0]; 8102 8103 u8 pas[][0x40]; 8104 }; 8105 8106 struct mlx5_ifc_create_dct_out_bits { 8107 u8 status[0x8]; 8108 u8 reserved_at_8[0x18]; 8109 8110 u8 syndrome[0x20]; 8111 8112 u8 reserved_at_40[0x8]; 8113 u8 dctn[0x18]; 8114 8115 u8 ece[0x20]; 8116 }; 8117 8118 struct mlx5_ifc_create_dct_in_bits { 8119 u8 opcode[0x10]; 8120 u8 uid[0x10]; 8121 8122 u8 reserved_at_20[0x10]; 8123 u8 op_mod[0x10]; 8124 8125 u8 reserved_at_40[0x40]; 8126 8127 struct mlx5_ifc_dctc_bits dct_context_entry; 8128 8129 u8 reserved_at_280[0x180]; 8130 }; 8131 8132 struct mlx5_ifc_create_cq_out_bits { 8133 u8 status[0x8]; 8134 u8 reserved_at_8[0x18]; 8135 8136 u8 syndrome[0x20]; 8137 8138 u8 reserved_at_40[0x8]; 8139 u8 cqn[0x18]; 8140 8141 u8 reserved_at_60[0x20]; 8142 }; 8143 8144 struct mlx5_ifc_create_cq_in_bits { 8145 u8 opcode[0x10]; 8146 u8 uid[0x10]; 8147 8148 u8 reserved_at_20[0x10]; 8149 u8 op_mod[0x10]; 8150 8151 u8 reserved_at_40[0x40]; 8152 8153 struct mlx5_ifc_cqc_bits cq_context; 8154 8155 u8 reserved_at_280[0x60]; 8156 8157 u8 cq_umem_valid[0x1]; 8158 u8 reserved_at_2e1[0x59f]; 8159 8160 u8 pas[][0x40]; 8161 }; 8162 8163 struct mlx5_ifc_config_int_moderation_out_bits { 8164 u8 status[0x8]; 8165 u8 reserved_at_8[0x18]; 8166 8167 u8 syndrome[0x20]; 8168 8169 u8 reserved_at_40[0x4]; 8170 u8 min_delay[0xc]; 8171 u8 int_vector[0x10]; 8172 8173 u8 reserved_at_60[0x20]; 8174 }; 8175 8176 enum { 8177 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8178 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8179 }; 8180 8181 struct mlx5_ifc_config_int_moderation_in_bits { 8182 u8 opcode[0x10]; 8183 u8 reserved_at_10[0x10]; 8184 8185 u8 reserved_at_20[0x10]; 8186 u8 op_mod[0x10]; 8187 8188 u8 reserved_at_40[0x4]; 8189 u8 min_delay[0xc]; 8190 u8 int_vector[0x10]; 8191 8192 u8 reserved_at_60[0x20]; 8193 }; 8194 8195 struct mlx5_ifc_attach_to_mcg_out_bits { 8196 u8 status[0x8]; 8197 u8 reserved_at_8[0x18]; 8198 8199 u8 syndrome[0x20]; 8200 8201 u8 reserved_at_40[0x40]; 8202 }; 8203 8204 struct mlx5_ifc_attach_to_mcg_in_bits { 8205 u8 opcode[0x10]; 8206 u8 uid[0x10]; 8207 8208 u8 reserved_at_20[0x10]; 8209 u8 op_mod[0x10]; 8210 8211 u8 reserved_at_40[0x8]; 8212 u8 qpn[0x18]; 8213 8214 u8 reserved_at_60[0x20]; 8215 8216 u8 multicast_gid[16][0x8]; 8217 }; 8218 8219 struct mlx5_ifc_arm_xrq_out_bits { 8220 u8 status[0x8]; 8221 u8 reserved_at_8[0x18]; 8222 8223 u8 syndrome[0x20]; 8224 8225 u8 reserved_at_40[0x40]; 8226 }; 8227 8228 struct mlx5_ifc_arm_xrq_in_bits { 8229 u8 opcode[0x10]; 8230 u8 reserved_at_10[0x10]; 8231 8232 u8 reserved_at_20[0x10]; 8233 u8 op_mod[0x10]; 8234 8235 u8 reserved_at_40[0x8]; 8236 u8 xrqn[0x18]; 8237 8238 u8 reserved_at_60[0x10]; 8239 u8 lwm[0x10]; 8240 }; 8241 8242 struct mlx5_ifc_arm_xrc_srq_out_bits { 8243 u8 status[0x8]; 8244 u8 reserved_at_8[0x18]; 8245 8246 u8 syndrome[0x20]; 8247 8248 u8 reserved_at_40[0x40]; 8249 }; 8250 8251 enum { 8252 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8253 }; 8254 8255 struct mlx5_ifc_arm_xrc_srq_in_bits { 8256 u8 opcode[0x10]; 8257 u8 uid[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 reserved_at_40[0x8]; 8263 u8 xrc_srqn[0x18]; 8264 8265 u8 reserved_at_60[0x10]; 8266 u8 lwm[0x10]; 8267 }; 8268 8269 struct mlx5_ifc_arm_rq_out_bits { 8270 u8 status[0x8]; 8271 u8 reserved_at_8[0x18]; 8272 8273 u8 syndrome[0x20]; 8274 8275 u8 reserved_at_40[0x40]; 8276 }; 8277 8278 enum { 8279 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8280 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8281 }; 8282 8283 struct mlx5_ifc_arm_rq_in_bits { 8284 u8 opcode[0x10]; 8285 u8 uid[0x10]; 8286 8287 u8 reserved_at_20[0x10]; 8288 u8 op_mod[0x10]; 8289 8290 u8 reserved_at_40[0x8]; 8291 u8 srq_number[0x18]; 8292 8293 u8 reserved_at_60[0x10]; 8294 u8 lwm[0x10]; 8295 }; 8296 8297 struct mlx5_ifc_arm_dct_out_bits { 8298 u8 status[0x8]; 8299 u8 reserved_at_8[0x18]; 8300 8301 u8 syndrome[0x20]; 8302 8303 u8 reserved_at_40[0x40]; 8304 }; 8305 8306 struct mlx5_ifc_arm_dct_in_bits { 8307 u8 opcode[0x10]; 8308 u8 reserved_at_10[0x10]; 8309 8310 u8 reserved_at_20[0x10]; 8311 u8 op_mod[0x10]; 8312 8313 u8 reserved_at_40[0x8]; 8314 u8 dct_number[0x18]; 8315 8316 u8 reserved_at_60[0x20]; 8317 }; 8318 8319 struct mlx5_ifc_alloc_xrcd_out_bits { 8320 u8 status[0x8]; 8321 u8 reserved_at_8[0x18]; 8322 8323 u8 syndrome[0x20]; 8324 8325 u8 reserved_at_40[0x8]; 8326 u8 xrcd[0x18]; 8327 8328 u8 reserved_at_60[0x20]; 8329 }; 8330 8331 struct mlx5_ifc_alloc_xrcd_in_bits { 8332 u8 opcode[0x10]; 8333 u8 uid[0x10]; 8334 8335 u8 reserved_at_20[0x10]; 8336 u8 op_mod[0x10]; 8337 8338 u8 reserved_at_40[0x40]; 8339 }; 8340 8341 struct mlx5_ifc_alloc_uar_out_bits { 8342 u8 status[0x8]; 8343 u8 reserved_at_8[0x18]; 8344 8345 u8 syndrome[0x20]; 8346 8347 u8 reserved_at_40[0x8]; 8348 u8 uar[0x18]; 8349 8350 u8 reserved_at_60[0x20]; 8351 }; 8352 8353 struct mlx5_ifc_alloc_uar_in_bits { 8354 u8 opcode[0x10]; 8355 u8 reserved_at_10[0x10]; 8356 8357 u8 reserved_at_20[0x10]; 8358 u8 op_mod[0x10]; 8359 8360 u8 reserved_at_40[0x40]; 8361 }; 8362 8363 struct mlx5_ifc_alloc_transport_domain_out_bits { 8364 u8 status[0x8]; 8365 u8 reserved_at_8[0x18]; 8366 8367 u8 syndrome[0x20]; 8368 8369 u8 reserved_at_40[0x8]; 8370 u8 transport_domain[0x18]; 8371 8372 u8 reserved_at_60[0x20]; 8373 }; 8374 8375 struct mlx5_ifc_alloc_transport_domain_in_bits { 8376 u8 opcode[0x10]; 8377 u8 uid[0x10]; 8378 8379 u8 reserved_at_20[0x10]; 8380 u8 op_mod[0x10]; 8381 8382 u8 reserved_at_40[0x40]; 8383 }; 8384 8385 struct mlx5_ifc_alloc_q_counter_out_bits { 8386 u8 status[0x8]; 8387 u8 reserved_at_8[0x18]; 8388 8389 u8 syndrome[0x20]; 8390 8391 u8 reserved_at_40[0x18]; 8392 u8 counter_set_id[0x8]; 8393 8394 u8 reserved_at_60[0x20]; 8395 }; 8396 8397 struct mlx5_ifc_alloc_q_counter_in_bits { 8398 u8 opcode[0x10]; 8399 u8 uid[0x10]; 8400 8401 u8 reserved_at_20[0x10]; 8402 u8 op_mod[0x10]; 8403 8404 u8 reserved_at_40[0x40]; 8405 }; 8406 8407 struct mlx5_ifc_alloc_pd_out_bits { 8408 u8 status[0x8]; 8409 u8 reserved_at_8[0x18]; 8410 8411 u8 syndrome[0x20]; 8412 8413 u8 reserved_at_40[0x8]; 8414 u8 pd[0x18]; 8415 8416 u8 reserved_at_60[0x20]; 8417 }; 8418 8419 struct mlx5_ifc_alloc_pd_in_bits { 8420 u8 opcode[0x10]; 8421 u8 uid[0x10]; 8422 8423 u8 reserved_at_20[0x10]; 8424 u8 op_mod[0x10]; 8425 8426 u8 reserved_at_40[0x40]; 8427 }; 8428 8429 struct mlx5_ifc_alloc_flow_counter_out_bits { 8430 u8 status[0x8]; 8431 u8 reserved_at_8[0x18]; 8432 8433 u8 syndrome[0x20]; 8434 8435 u8 flow_counter_id[0x20]; 8436 8437 u8 reserved_at_60[0x20]; 8438 }; 8439 8440 struct mlx5_ifc_alloc_flow_counter_in_bits { 8441 u8 opcode[0x10]; 8442 u8 reserved_at_10[0x10]; 8443 8444 u8 reserved_at_20[0x10]; 8445 u8 op_mod[0x10]; 8446 8447 u8 reserved_at_40[0x38]; 8448 u8 flow_counter_bulk[0x8]; 8449 }; 8450 8451 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8452 u8 status[0x8]; 8453 u8 reserved_at_8[0x18]; 8454 8455 u8 syndrome[0x20]; 8456 8457 u8 reserved_at_40[0x40]; 8458 }; 8459 8460 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8461 u8 opcode[0x10]; 8462 u8 reserved_at_10[0x10]; 8463 8464 u8 reserved_at_20[0x10]; 8465 u8 op_mod[0x10]; 8466 8467 u8 reserved_at_40[0x20]; 8468 8469 u8 reserved_at_60[0x10]; 8470 u8 vxlan_udp_port[0x10]; 8471 }; 8472 8473 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8474 u8 status[0x8]; 8475 u8 reserved_at_8[0x18]; 8476 8477 u8 syndrome[0x20]; 8478 8479 u8 reserved_at_40[0x40]; 8480 }; 8481 8482 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8483 u8 rate_limit[0x20]; 8484 8485 u8 burst_upper_bound[0x20]; 8486 8487 u8 reserved_at_40[0x10]; 8488 u8 typical_packet_size[0x10]; 8489 8490 u8 reserved_at_60[0x120]; 8491 }; 8492 8493 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8494 u8 opcode[0x10]; 8495 u8 uid[0x10]; 8496 8497 u8 reserved_at_20[0x10]; 8498 u8 op_mod[0x10]; 8499 8500 u8 reserved_at_40[0x10]; 8501 u8 rate_limit_index[0x10]; 8502 8503 u8 reserved_at_60[0x20]; 8504 8505 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8506 }; 8507 8508 struct mlx5_ifc_access_register_out_bits { 8509 u8 status[0x8]; 8510 u8 reserved_at_8[0x18]; 8511 8512 u8 syndrome[0x20]; 8513 8514 u8 reserved_at_40[0x40]; 8515 8516 u8 register_data[][0x20]; 8517 }; 8518 8519 enum { 8520 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8521 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8522 }; 8523 8524 struct mlx5_ifc_access_register_in_bits { 8525 u8 opcode[0x10]; 8526 u8 reserved_at_10[0x10]; 8527 8528 u8 reserved_at_20[0x10]; 8529 u8 op_mod[0x10]; 8530 8531 u8 reserved_at_40[0x10]; 8532 u8 register_id[0x10]; 8533 8534 u8 argument[0x20]; 8535 8536 u8 register_data[][0x20]; 8537 }; 8538 8539 struct mlx5_ifc_sltp_reg_bits { 8540 u8 status[0x4]; 8541 u8 version[0x4]; 8542 u8 local_port[0x8]; 8543 u8 pnat[0x2]; 8544 u8 reserved_at_12[0x2]; 8545 u8 lane[0x4]; 8546 u8 reserved_at_18[0x8]; 8547 8548 u8 reserved_at_20[0x20]; 8549 8550 u8 reserved_at_40[0x7]; 8551 u8 polarity[0x1]; 8552 u8 ob_tap0[0x8]; 8553 u8 ob_tap1[0x8]; 8554 u8 ob_tap2[0x8]; 8555 8556 u8 reserved_at_60[0xc]; 8557 u8 ob_preemp_mode[0x4]; 8558 u8 ob_reg[0x8]; 8559 u8 ob_bias[0x8]; 8560 8561 u8 reserved_at_80[0x20]; 8562 }; 8563 8564 struct mlx5_ifc_slrg_reg_bits { 8565 u8 status[0x4]; 8566 u8 version[0x4]; 8567 u8 local_port[0x8]; 8568 u8 pnat[0x2]; 8569 u8 reserved_at_12[0x2]; 8570 u8 lane[0x4]; 8571 u8 reserved_at_18[0x8]; 8572 8573 u8 time_to_link_up[0x10]; 8574 u8 reserved_at_30[0xc]; 8575 u8 grade_lane_speed[0x4]; 8576 8577 u8 grade_version[0x8]; 8578 u8 grade[0x18]; 8579 8580 u8 reserved_at_60[0x4]; 8581 u8 height_grade_type[0x4]; 8582 u8 height_grade[0x18]; 8583 8584 u8 height_dz[0x10]; 8585 u8 height_dv[0x10]; 8586 8587 u8 reserved_at_a0[0x10]; 8588 u8 height_sigma[0x10]; 8589 8590 u8 reserved_at_c0[0x20]; 8591 8592 u8 reserved_at_e0[0x4]; 8593 u8 phase_grade_type[0x4]; 8594 u8 phase_grade[0x18]; 8595 8596 u8 reserved_at_100[0x8]; 8597 u8 phase_eo_pos[0x8]; 8598 u8 reserved_at_110[0x8]; 8599 u8 phase_eo_neg[0x8]; 8600 8601 u8 ffe_set_tested[0x10]; 8602 u8 test_errors_per_lane[0x10]; 8603 }; 8604 8605 struct mlx5_ifc_pvlc_reg_bits { 8606 u8 reserved_at_0[0x8]; 8607 u8 local_port[0x8]; 8608 u8 reserved_at_10[0x10]; 8609 8610 u8 reserved_at_20[0x1c]; 8611 u8 vl_hw_cap[0x4]; 8612 8613 u8 reserved_at_40[0x1c]; 8614 u8 vl_admin[0x4]; 8615 8616 u8 reserved_at_60[0x1c]; 8617 u8 vl_operational[0x4]; 8618 }; 8619 8620 struct mlx5_ifc_pude_reg_bits { 8621 u8 swid[0x8]; 8622 u8 local_port[0x8]; 8623 u8 reserved_at_10[0x4]; 8624 u8 admin_status[0x4]; 8625 u8 reserved_at_18[0x4]; 8626 u8 oper_status[0x4]; 8627 8628 u8 reserved_at_20[0x60]; 8629 }; 8630 8631 struct mlx5_ifc_ptys_reg_bits { 8632 u8 reserved_at_0[0x1]; 8633 u8 an_disable_admin[0x1]; 8634 u8 an_disable_cap[0x1]; 8635 u8 reserved_at_3[0x5]; 8636 u8 local_port[0x8]; 8637 u8 reserved_at_10[0xd]; 8638 u8 proto_mask[0x3]; 8639 8640 u8 an_status[0x4]; 8641 u8 reserved_at_24[0xc]; 8642 u8 data_rate_oper[0x10]; 8643 8644 u8 ext_eth_proto_capability[0x20]; 8645 8646 u8 eth_proto_capability[0x20]; 8647 8648 u8 ib_link_width_capability[0x10]; 8649 u8 ib_proto_capability[0x10]; 8650 8651 u8 ext_eth_proto_admin[0x20]; 8652 8653 u8 eth_proto_admin[0x20]; 8654 8655 u8 ib_link_width_admin[0x10]; 8656 u8 ib_proto_admin[0x10]; 8657 8658 u8 ext_eth_proto_oper[0x20]; 8659 8660 u8 eth_proto_oper[0x20]; 8661 8662 u8 ib_link_width_oper[0x10]; 8663 u8 ib_proto_oper[0x10]; 8664 8665 u8 reserved_at_160[0x1c]; 8666 u8 connector_type[0x4]; 8667 8668 u8 eth_proto_lp_advertise[0x20]; 8669 8670 u8 reserved_at_1a0[0x60]; 8671 }; 8672 8673 struct mlx5_ifc_mlcr_reg_bits { 8674 u8 reserved_at_0[0x8]; 8675 u8 local_port[0x8]; 8676 u8 reserved_at_10[0x20]; 8677 8678 u8 beacon_duration[0x10]; 8679 u8 reserved_at_40[0x10]; 8680 8681 u8 beacon_remain[0x10]; 8682 }; 8683 8684 struct mlx5_ifc_ptas_reg_bits { 8685 u8 reserved_at_0[0x20]; 8686 8687 u8 algorithm_options[0x10]; 8688 u8 reserved_at_30[0x4]; 8689 u8 repetitions_mode[0x4]; 8690 u8 num_of_repetitions[0x8]; 8691 8692 u8 grade_version[0x8]; 8693 u8 height_grade_type[0x4]; 8694 u8 phase_grade_type[0x4]; 8695 u8 height_grade_weight[0x8]; 8696 u8 phase_grade_weight[0x8]; 8697 8698 u8 gisim_measure_bits[0x10]; 8699 u8 adaptive_tap_measure_bits[0x10]; 8700 8701 u8 ber_bath_high_error_threshold[0x10]; 8702 u8 ber_bath_mid_error_threshold[0x10]; 8703 8704 u8 ber_bath_low_error_threshold[0x10]; 8705 u8 one_ratio_high_threshold[0x10]; 8706 8707 u8 one_ratio_high_mid_threshold[0x10]; 8708 u8 one_ratio_low_mid_threshold[0x10]; 8709 8710 u8 one_ratio_low_threshold[0x10]; 8711 u8 ndeo_error_threshold[0x10]; 8712 8713 u8 mixer_offset_step_size[0x10]; 8714 u8 reserved_at_110[0x8]; 8715 u8 mix90_phase_for_voltage_bath[0x8]; 8716 8717 u8 mixer_offset_start[0x10]; 8718 u8 mixer_offset_end[0x10]; 8719 8720 u8 reserved_at_140[0x15]; 8721 u8 ber_test_time[0xb]; 8722 }; 8723 8724 struct mlx5_ifc_pspa_reg_bits { 8725 u8 swid[0x8]; 8726 u8 local_port[0x8]; 8727 u8 sub_port[0x8]; 8728 u8 reserved_at_18[0x8]; 8729 8730 u8 reserved_at_20[0x20]; 8731 }; 8732 8733 struct mlx5_ifc_pqdr_reg_bits { 8734 u8 reserved_at_0[0x8]; 8735 u8 local_port[0x8]; 8736 u8 reserved_at_10[0x5]; 8737 u8 prio[0x3]; 8738 u8 reserved_at_18[0x6]; 8739 u8 mode[0x2]; 8740 8741 u8 reserved_at_20[0x20]; 8742 8743 u8 reserved_at_40[0x10]; 8744 u8 min_threshold[0x10]; 8745 8746 u8 reserved_at_60[0x10]; 8747 u8 max_threshold[0x10]; 8748 8749 u8 reserved_at_80[0x10]; 8750 u8 mark_probability_denominator[0x10]; 8751 8752 u8 reserved_at_a0[0x60]; 8753 }; 8754 8755 struct mlx5_ifc_ppsc_reg_bits { 8756 u8 reserved_at_0[0x8]; 8757 u8 local_port[0x8]; 8758 u8 reserved_at_10[0x10]; 8759 8760 u8 reserved_at_20[0x60]; 8761 8762 u8 reserved_at_80[0x1c]; 8763 u8 wrps_admin[0x4]; 8764 8765 u8 reserved_at_a0[0x1c]; 8766 u8 wrps_status[0x4]; 8767 8768 u8 reserved_at_c0[0x8]; 8769 u8 up_threshold[0x8]; 8770 u8 reserved_at_d0[0x8]; 8771 u8 down_threshold[0x8]; 8772 8773 u8 reserved_at_e0[0x20]; 8774 8775 u8 reserved_at_100[0x1c]; 8776 u8 srps_admin[0x4]; 8777 8778 u8 reserved_at_120[0x1c]; 8779 u8 srps_status[0x4]; 8780 8781 u8 reserved_at_140[0x40]; 8782 }; 8783 8784 struct mlx5_ifc_pplr_reg_bits { 8785 u8 reserved_at_0[0x8]; 8786 u8 local_port[0x8]; 8787 u8 reserved_at_10[0x10]; 8788 8789 u8 reserved_at_20[0x8]; 8790 u8 lb_cap[0x8]; 8791 u8 reserved_at_30[0x8]; 8792 u8 lb_en[0x8]; 8793 }; 8794 8795 struct mlx5_ifc_pplm_reg_bits { 8796 u8 reserved_at_0[0x8]; 8797 u8 local_port[0x8]; 8798 u8 reserved_at_10[0x10]; 8799 8800 u8 reserved_at_20[0x20]; 8801 8802 u8 port_profile_mode[0x8]; 8803 u8 static_port_profile[0x8]; 8804 u8 active_port_profile[0x8]; 8805 u8 reserved_at_58[0x8]; 8806 8807 u8 retransmission_active[0x8]; 8808 u8 fec_mode_active[0x18]; 8809 8810 u8 rs_fec_correction_bypass_cap[0x4]; 8811 u8 reserved_at_84[0x8]; 8812 u8 fec_override_cap_56g[0x4]; 8813 u8 fec_override_cap_100g[0x4]; 8814 u8 fec_override_cap_50g[0x4]; 8815 u8 fec_override_cap_25g[0x4]; 8816 u8 fec_override_cap_10g_40g[0x4]; 8817 8818 u8 rs_fec_correction_bypass_admin[0x4]; 8819 u8 reserved_at_a4[0x8]; 8820 u8 fec_override_admin_56g[0x4]; 8821 u8 fec_override_admin_100g[0x4]; 8822 u8 fec_override_admin_50g[0x4]; 8823 u8 fec_override_admin_25g[0x4]; 8824 u8 fec_override_admin_10g_40g[0x4]; 8825 8826 u8 fec_override_cap_400g_8x[0x10]; 8827 u8 fec_override_cap_200g_4x[0x10]; 8828 8829 u8 fec_override_cap_100g_2x[0x10]; 8830 u8 fec_override_cap_50g_1x[0x10]; 8831 8832 u8 fec_override_admin_400g_8x[0x10]; 8833 u8 fec_override_admin_200g_4x[0x10]; 8834 8835 u8 fec_override_admin_100g_2x[0x10]; 8836 u8 fec_override_admin_50g_1x[0x10]; 8837 }; 8838 8839 struct mlx5_ifc_ppcnt_reg_bits { 8840 u8 swid[0x8]; 8841 u8 local_port[0x8]; 8842 u8 pnat[0x2]; 8843 u8 reserved_at_12[0x8]; 8844 u8 grp[0x6]; 8845 8846 u8 clr[0x1]; 8847 u8 reserved_at_21[0x1c]; 8848 u8 prio_tc[0x3]; 8849 8850 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8851 }; 8852 8853 struct mlx5_ifc_mpein_reg_bits { 8854 u8 reserved_at_0[0x2]; 8855 u8 depth[0x6]; 8856 u8 pcie_index[0x8]; 8857 u8 node[0x8]; 8858 u8 reserved_at_18[0x8]; 8859 8860 u8 capability_mask[0x20]; 8861 8862 u8 reserved_at_40[0x8]; 8863 u8 link_width_enabled[0x8]; 8864 u8 link_speed_enabled[0x10]; 8865 8866 u8 lane0_physical_position[0x8]; 8867 u8 link_width_active[0x8]; 8868 u8 link_speed_active[0x10]; 8869 8870 u8 num_of_pfs[0x10]; 8871 u8 num_of_vfs[0x10]; 8872 8873 u8 bdf0[0x10]; 8874 u8 reserved_at_b0[0x10]; 8875 8876 u8 max_read_request_size[0x4]; 8877 u8 max_payload_size[0x4]; 8878 u8 reserved_at_c8[0x5]; 8879 u8 pwr_status[0x3]; 8880 u8 port_type[0x4]; 8881 u8 reserved_at_d4[0xb]; 8882 u8 lane_reversal[0x1]; 8883 8884 u8 reserved_at_e0[0x14]; 8885 u8 pci_power[0xc]; 8886 8887 u8 reserved_at_100[0x20]; 8888 8889 u8 device_status[0x10]; 8890 u8 port_state[0x8]; 8891 u8 reserved_at_138[0x8]; 8892 8893 u8 reserved_at_140[0x10]; 8894 u8 receiver_detect_result[0x10]; 8895 8896 u8 reserved_at_160[0x20]; 8897 }; 8898 8899 struct mlx5_ifc_mpcnt_reg_bits { 8900 u8 reserved_at_0[0x8]; 8901 u8 pcie_index[0x8]; 8902 u8 reserved_at_10[0xa]; 8903 u8 grp[0x6]; 8904 8905 u8 clr[0x1]; 8906 u8 reserved_at_21[0x1f]; 8907 8908 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8909 }; 8910 8911 struct mlx5_ifc_ppad_reg_bits { 8912 u8 reserved_at_0[0x3]; 8913 u8 single_mac[0x1]; 8914 u8 reserved_at_4[0x4]; 8915 u8 local_port[0x8]; 8916 u8 mac_47_32[0x10]; 8917 8918 u8 mac_31_0[0x20]; 8919 8920 u8 reserved_at_40[0x40]; 8921 }; 8922 8923 struct mlx5_ifc_pmtu_reg_bits { 8924 u8 reserved_at_0[0x8]; 8925 u8 local_port[0x8]; 8926 u8 reserved_at_10[0x10]; 8927 8928 u8 max_mtu[0x10]; 8929 u8 reserved_at_30[0x10]; 8930 8931 u8 admin_mtu[0x10]; 8932 u8 reserved_at_50[0x10]; 8933 8934 u8 oper_mtu[0x10]; 8935 u8 reserved_at_70[0x10]; 8936 }; 8937 8938 struct mlx5_ifc_pmpr_reg_bits { 8939 u8 reserved_at_0[0x8]; 8940 u8 module[0x8]; 8941 u8 reserved_at_10[0x10]; 8942 8943 u8 reserved_at_20[0x18]; 8944 u8 attenuation_5g[0x8]; 8945 8946 u8 reserved_at_40[0x18]; 8947 u8 attenuation_7g[0x8]; 8948 8949 u8 reserved_at_60[0x18]; 8950 u8 attenuation_12g[0x8]; 8951 }; 8952 8953 struct mlx5_ifc_pmpe_reg_bits { 8954 u8 reserved_at_0[0x8]; 8955 u8 module[0x8]; 8956 u8 reserved_at_10[0xc]; 8957 u8 module_status[0x4]; 8958 8959 u8 reserved_at_20[0x60]; 8960 }; 8961 8962 struct mlx5_ifc_pmpc_reg_bits { 8963 u8 module_state_updated[32][0x8]; 8964 }; 8965 8966 struct mlx5_ifc_pmlpn_reg_bits { 8967 u8 reserved_at_0[0x4]; 8968 u8 mlpn_status[0x4]; 8969 u8 local_port[0x8]; 8970 u8 reserved_at_10[0x10]; 8971 8972 u8 e[0x1]; 8973 u8 reserved_at_21[0x1f]; 8974 }; 8975 8976 struct mlx5_ifc_pmlp_reg_bits { 8977 u8 rxtx[0x1]; 8978 u8 reserved_at_1[0x7]; 8979 u8 local_port[0x8]; 8980 u8 reserved_at_10[0x8]; 8981 u8 width[0x8]; 8982 8983 u8 lane0_module_mapping[0x20]; 8984 8985 u8 lane1_module_mapping[0x20]; 8986 8987 u8 lane2_module_mapping[0x20]; 8988 8989 u8 lane3_module_mapping[0x20]; 8990 8991 u8 reserved_at_a0[0x160]; 8992 }; 8993 8994 struct mlx5_ifc_pmaos_reg_bits { 8995 u8 reserved_at_0[0x8]; 8996 u8 module[0x8]; 8997 u8 reserved_at_10[0x4]; 8998 u8 admin_status[0x4]; 8999 u8 reserved_at_18[0x4]; 9000 u8 oper_status[0x4]; 9001 9002 u8 ase[0x1]; 9003 u8 ee[0x1]; 9004 u8 reserved_at_22[0x1c]; 9005 u8 e[0x2]; 9006 9007 u8 reserved_at_40[0x40]; 9008 }; 9009 9010 struct mlx5_ifc_plpc_reg_bits { 9011 u8 reserved_at_0[0x4]; 9012 u8 profile_id[0xc]; 9013 u8 reserved_at_10[0x4]; 9014 u8 proto_mask[0x4]; 9015 u8 reserved_at_18[0x8]; 9016 9017 u8 reserved_at_20[0x10]; 9018 u8 lane_speed[0x10]; 9019 9020 u8 reserved_at_40[0x17]; 9021 u8 lpbf[0x1]; 9022 u8 fec_mode_policy[0x8]; 9023 9024 u8 retransmission_capability[0x8]; 9025 u8 fec_mode_capability[0x18]; 9026 9027 u8 retransmission_support_admin[0x8]; 9028 u8 fec_mode_support_admin[0x18]; 9029 9030 u8 retransmission_request_admin[0x8]; 9031 u8 fec_mode_request_admin[0x18]; 9032 9033 u8 reserved_at_c0[0x80]; 9034 }; 9035 9036 struct mlx5_ifc_plib_reg_bits { 9037 u8 reserved_at_0[0x8]; 9038 u8 local_port[0x8]; 9039 u8 reserved_at_10[0x8]; 9040 u8 ib_port[0x8]; 9041 9042 u8 reserved_at_20[0x60]; 9043 }; 9044 9045 struct mlx5_ifc_plbf_reg_bits { 9046 u8 reserved_at_0[0x8]; 9047 u8 local_port[0x8]; 9048 u8 reserved_at_10[0xd]; 9049 u8 lbf_mode[0x3]; 9050 9051 u8 reserved_at_20[0x20]; 9052 }; 9053 9054 struct mlx5_ifc_pipg_reg_bits { 9055 u8 reserved_at_0[0x8]; 9056 u8 local_port[0x8]; 9057 u8 reserved_at_10[0x10]; 9058 9059 u8 dic[0x1]; 9060 u8 reserved_at_21[0x19]; 9061 u8 ipg[0x4]; 9062 u8 reserved_at_3e[0x2]; 9063 }; 9064 9065 struct mlx5_ifc_pifr_reg_bits { 9066 u8 reserved_at_0[0x8]; 9067 u8 local_port[0x8]; 9068 u8 reserved_at_10[0x10]; 9069 9070 u8 reserved_at_20[0xe0]; 9071 9072 u8 port_filter[8][0x20]; 9073 9074 u8 port_filter_update_en[8][0x20]; 9075 }; 9076 9077 struct mlx5_ifc_pfcc_reg_bits { 9078 u8 reserved_at_0[0x8]; 9079 u8 local_port[0x8]; 9080 u8 reserved_at_10[0xb]; 9081 u8 ppan_mask_n[0x1]; 9082 u8 minor_stall_mask[0x1]; 9083 u8 critical_stall_mask[0x1]; 9084 u8 reserved_at_1e[0x2]; 9085 9086 u8 ppan[0x4]; 9087 u8 reserved_at_24[0x4]; 9088 u8 prio_mask_tx[0x8]; 9089 u8 reserved_at_30[0x8]; 9090 u8 prio_mask_rx[0x8]; 9091 9092 u8 pptx[0x1]; 9093 u8 aptx[0x1]; 9094 u8 pptx_mask_n[0x1]; 9095 u8 reserved_at_43[0x5]; 9096 u8 pfctx[0x8]; 9097 u8 reserved_at_50[0x10]; 9098 9099 u8 pprx[0x1]; 9100 u8 aprx[0x1]; 9101 u8 pprx_mask_n[0x1]; 9102 u8 reserved_at_63[0x5]; 9103 u8 pfcrx[0x8]; 9104 u8 reserved_at_70[0x10]; 9105 9106 u8 device_stall_minor_watermark[0x10]; 9107 u8 device_stall_critical_watermark[0x10]; 9108 9109 u8 reserved_at_a0[0x60]; 9110 }; 9111 9112 struct mlx5_ifc_pelc_reg_bits { 9113 u8 op[0x4]; 9114 u8 reserved_at_4[0x4]; 9115 u8 local_port[0x8]; 9116 u8 reserved_at_10[0x10]; 9117 9118 u8 op_admin[0x8]; 9119 u8 op_capability[0x8]; 9120 u8 op_request[0x8]; 9121 u8 op_active[0x8]; 9122 9123 u8 admin[0x40]; 9124 9125 u8 capability[0x40]; 9126 9127 u8 request[0x40]; 9128 9129 u8 active[0x40]; 9130 9131 u8 reserved_at_140[0x80]; 9132 }; 9133 9134 struct mlx5_ifc_peir_reg_bits { 9135 u8 reserved_at_0[0x8]; 9136 u8 local_port[0x8]; 9137 u8 reserved_at_10[0x10]; 9138 9139 u8 reserved_at_20[0xc]; 9140 u8 error_count[0x4]; 9141 u8 reserved_at_30[0x10]; 9142 9143 u8 reserved_at_40[0xc]; 9144 u8 lane[0x4]; 9145 u8 reserved_at_50[0x8]; 9146 u8 error_type[0x8]; 9147 }; 9148 9149 struct mlx5_ifc_mpegc_reg_bits { 9150 u8 reserved_at_0[0x30]; 9151 u8 field_select[0x10]; 9152 9153 u8 tx_overflow_sense[0x1]; 9154 u8 mark_cqe[0x1]; 9155 u8 mark_cnp[0x1]; 9156 u8 reserved_at_43[0x1b]; 9157 u8 tx_lossy_overflow_oper[0x2]; 9158 9159 u8 reserved_at_60[0x100]; 9160 }; 9161 9162 enum { 9163 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9164 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9165 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9166 }; 9167 9168 struct mlx5_ifc_mtutc_reg_bits { 9169 u8 reserved_at_0[0x1c]; 9170 u8 operation[0x4]; 9171 9172 u8 freq_adjustment[0x20]; 9173 9174 u8 reserved_at_40[0x40]; 9175 9176 u8 utc_sec[0x20]; 9177 9178 u8 reserved_at_a0[0x2]; 9179 u8 utc_nsec[0x1e]; 9180 9181 u8 time_adjustment[0x20]; 9182 }; 9183 9184 struct mlx5_ifc_pcam_enhanced_features_bits { 9185 u8 reserved_at_0[0x68]; 9186 u8 fec_50G_per_lane_in_pplm[0x1]; 9187 u8 reserved_at_69[0x4]; 9188 u8 rx_icrc_encapsulated_counter[0x1]; 9189 u8 reserved_at_6e[0x4]; 9190 u8 ptys_extended_ethernet[0x1]; 9191 u8 reserved_at_73[0x3]; 9192 u8 pfcc_mask[0x1]; 9193 u8 reserved_at_77[0x3]; 9194 u8 per_lane_error_counters[0x1]; 9195 u8 rx_buffer_fullness_counters[0x1]; 9196 u8 ptys_connector_type[0x1]; 9197 u8 reserved_at_7d[0x1]; 9198 u8 ppcnt_discard_group[0x1]; 9199 u8 ppcnt_statistical_group[0x1]; 9200 }; 9201 9202 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9203 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9204 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9205 9206 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9207 u8 pplm[0x1]; 9208 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9209 9210 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9211 u8 pbmc[0x1]; 9212 u8 pptb[0x1]; 9213 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9214 u8 ppcnt[0x1]; 9215 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9216 }; 9217 9218 struct mlx5_ifc_pcam_reg_bits { 9219 u8 reserved_at_0[0x8]; 9220 u8 feature_group[0x8]; 9221 u8 reserved_at_10[0x8]; 9222 u8 access_reg_group[0x8]; 9223 9224 u8 reserved_at_20[0x20]; 9225 9226 union { 9227 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9228 u8 reserved_at_0[0x80]; 9229 } port_access_reg_cap_mask; 9230 9231 u8 reserved_at_c0[0x80]; 9232 9233 union { 9234 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9235 u8 reserved_at_0[0x80]; 9236 } feature_cap_mask; 9237 9238 u8 reserved_at_1c0[0xc0]; 9239 }; 9240 9241 struct mlx5_ifc_mcam_enhanced_features_bits { 9242 u8 reserved_at_0[0x6b]; 9243 u8 ptpcyc2realtime_modify[0x1]; 9244 u8 reserved_at_6c[0x2]; 9245 u8 pci_status_and_power[0x1]; 9246 u8 reserved_at_6f[0x5]; 9247 u8 mark_tx_action_cnp[0x1]; 9248 u8 mark_tx_action_cqe[0x1]; 9249 u8 dynamic_tx_overflow[0x1]; 9250 u8 reserved_at_77[0x4]; 9251 u8 pcie_outbound_stalled[0x1]; 9252 u8 tx_overflow_buffer_pkt[0x1]; 9253 u8 mtpps_enh_out_per_adj[0x1]; 9254 u8 mtpps_fs[0x1]; 9255 u8 pcie_performance_group[0x1]; 9256 }; 9257 9258 struct mlx5_ifc_mcam_access_reg_bits { 9259 u8 reserved_at_0[0x1c]; 9260 u8 mcda[0x1]; 9261 u8 mcc[0x1]; 9262 u8 mcqi[0x1]; 9263 u8 mcqs[0x1]; 9264 9265 u8 regs_95_to_87[0x9]; 9266 u8 mpegc[0x1]; 9267 u8 mtutc[0x1]; 9268 u8 regs_84_to_68[0x11]; 9269 u8 tracer_registers[0x4]; 9270 9271 u8 regs_63_to_32[0x20]; 9272 u8 regs_31_to_0[0x20]; 9273 }; 9274 9275 struct mlx5_ifc_mcam_access_reg_bits1 { 9276 u8 regs_127_to_96[0x20]; 9277 9278 u8 regs_95_to_64[0x20]; 9279 9280 u8 regs_63_to_32[0x20]; 9281 9282 u8 regs_31_to_0[0x20]; 9283 }; 9284 9285 struct mlx5_ifc_mcam_access_reg_bits2 { 9286 u8 regs_127_to_99[0x1d]; 9287 u8 mirc[0x1]; 9288 u8 regs_97_to_96[0x2]; 9289 9290 u8 regs_95_to_64[0x20]; 9291 9292 u8 regs_63_to_32[0x20]; 9293 9294 u8 regs_31_to_0[0x20]; 9295 }; 9296 9297 struct mlx5_ifc_mcam_reg_bits { 9298 u8 reserved_at_0[0x8]; 9299 u8 feature_group[0x8]; 9300 u8 reserved_at_10[0x8]; 9301 u8 access_reg_group[0x8]; 9302 9303 u8 reserved_at_20[0x20]; 9304 9305 union { 9306 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9307 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9308 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9309 u8 reserved_at_0[0x80]; 9310 } mng_access_reg_cap_mask; 9311 9312 u8 reserved_at_c0[0x80]; 9313 9314 union { 9315 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9316 u8 reserved_at_0[0x80]; 9317 } mng_feature_cap_mask; 9318 9319 u8 reserved_at_1c0[0x80]; 9320 }; 9321 9322 struct mlx5_ifc_qcam_access_reg_cap_mask { 9323 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9324 u8 qpdpm[0x1]; 9325 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9326 u8 qdpm[0x1]; 9327 u8 qpts[0x1]; 9328 u8 qcap[0x1]; 9329 u8 qcam_access_reg_cap_mask_0[0x1]; 9330 }; 9331 9332 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9333 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9334 u8 qpts_trust_both[0x1]; 9335 }; 9336 9337 struct mlx5_ifc_qcam_reg_bits { 9338 u8 reserved_at_0[0x8]; 9339 u8 feature_group[0x8]; 9340 u8 reserved_at_10[0x8]; 9341 u8 access_reg_group[0x8]; 9342 u8 reserved_at_20[0x20]; 9343 9344 union { 9345 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9346 u8 reserved_at_0[0x80]; 9347 } qos_access_reg_cap_mask; 9348 9349 u8 reserved_at_c0[0x80]; 9350 9351 union { 9352 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9353 u8 reserved_at_0[0x80]; 9354 } qos_feature_cap_mask; 9355 9356 u8 reserved_at_1c0[0x80]; 9357 }; 9358 9359 struct mlx5_ifc_core_dump_reg_bits { 9360 u8 reserved_at_0[0x18]; 9361 u8 core_dump_type[0x8]; 9362 9363 u8 reserved_at_20[0x30]; 9364 u8 vhca_id[0x10]; 9365 9366 u8 reserved_at_60[0x8]; 9367 u8 qpn[0x18]; 9368 u8 reserved_at_80[0x180]; 9369 }; 9370 9371 struct mlx5_ifc_pcap_reg_bits { 9372 u8 reserved_at_0[0x8]; 9373 u8 local_port[0x8]; 9374 u8 reserved_at_10[0x10]; 9375 9376 u8 port_capability_mask[4][0x20]; 9377 }; 9378 9379 struct mlx5_ifc_paos_reg_bits { 9380 u8 swid[0x8]; 9381 u8 local_port[0x8]; 9382 u8 reserved_at_10[0x4]; 9383 u8 admin_status[0x4]; 9384 u8 reserved_at_18[0x4]; 9385 u8 oper_status[0x4]; 9386 9387 u8 ase[0x1]; 9388 u8 ee[0x1]; 9389 u8 reserved_at_22[0x1c]; 9390 u8 e[0x2]; 9391 9392 u8 reserved_at_40[0x40]; 9393 }; 9394 9395 struct mlx5_ifc_pamp_reg_bits { 9396 u8 reserved_at_0[0x8]; 9397 u8 opamp_group[0x8]; 9398 u8 reserved_at_10[0xc]; 9399 u8 opamp_group_type[0x4]; 9400 9401 u8 start_index[0x10]; 9402 u8 reserved_at_30[0x4]; 9403 u8 num_of_indices[0xc]; 9404 9405 u8 index_data[18][0x10]; 9406 }; 9407 9408 struct mlx5_ifc_pcmr_reg_bits { 9409 u8 reserved_at_0[0x8]; 9410 u8 local_port[0x8]; 9411 u8 reserved_at_10[0x10]; 9412 u8 entropy_force_cap[0x1]; 9413 u8 entropy_calc_cap[0x1]; 9414 u8 entropy_gre_calc_cap[0x1]; 9415 u8 reserved_at_23[0x1b]; 9416 u8 fcs_cap[0x1]; 9417 u8 reserved_at_3f[0x1]; 9418 u8 entropy_force[0x1]; 9419 u8 entropy_calc[0x1]; 9420 u8 entropy_gre_calc[0x1]; 9421 u8 reserved_at_43[0x1b]; 9422 u8 fcs_chk[0x1]; 9423 u8 reserved_at_5f[0x1]; 9424 }; 9425 9426 struct mlx5_ifc_lane_2_module_mapping_bits { 9427 u8 reserved_at_0[0x6]; 9428 u8 rx_lane[0x2]; 9429 u8 reserved_at_8[0x6]; 9430 u8 tx_lane[0x2]; 9431 u8 reserved_at_10[0x8]; 9432 u8 module[0x8]; 9433 }; 9434 9435 struct mlx5_ifc_bufferx_reg_bits { 9436 u8 reserved_at_0[0x6]; 9437 u8 lossy[0x1]; 9438 u8 epsb[0x1]; 9439 u8 reserved_at_8[0xc]; 9440 u8 size[0xc]; 9441 9442 u8 xoff_threshold[0x10]; 9443 u8 xon_threshold[0x10]; 9444 }; 9445 9446 struct mlx5_ifc_set_node_in_bits { 9447 u8 node_description[64][0x8]; 9448 }; 9449 9450 struct mlx5_ifc_register_power_settings_bits { 9451 u8 reserved_at_0[0x18]; 9452 u8 power_settings_level[0x8]; 9453 9454 u8 reserved_at_20[0x60]; 9455 }; 9456 9457 struct mlx5_ifc_register_host_endianness_bits { 9458 u8 he[0x1]; 9459 u8 reserved_at_1[0x1f]; 9460 9461 u8 reserved_at_20[0x60]; 9462 }; 9463 9464 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9465 u8 reserved_at_0[0x20]; 9466 9467 u8 mkey[0x20]; 9468 9469 u8 addressh_63_32[0x20]; 9470 9471 u8 addressl_31_0[0x20]; 9472 }; 9473 9474 struct mlx5_ifc_ud_adrs_vector_bits { 9475 u8 dc_key[0x40]; 9476 9477 u8 ext[0x1]; 9478 u8 reserved_at_41[0x7]; 9479 u8 destination_qp_dct[0x18]; 9480 9481 u8 static_rate[0x4]; 9482 u8 sl_eth_prio[0x4]; 9483 u8 fl[0x1]; 9484 u8 mlid[0x7]; 9485 u8 rlid_udp_sport[0x10]; 9486 9487 u8 reserved_at_80[0x20]; 9488 9489 u8 rmac_47_16[0x20]; 9490 9491 u8 rmac_15_0[0x10]; 9492 u8 tclass[0x8]; 9493 u8 hop_limit[0x8]; 9494 9495 u8 reserved_at_e0[0x1]; 9496 u8 grh[0x1]; 9497 u8 reserved_at_e2[0x2]; 9498 u8 src_addr_index[0x8]; 9499 u8 flow_label[0x14]; 9500 9501 u8 rgid_rip[16][0x8]; 9502 }; 9503 9504 struct mlx5_ifc_pages_req_event_bits { 9505 u8 reserved_at_0[0x10]; 9506 u8 function_id[0x10]; 9507 9508 u8 num_pages[0x20]; 9509 9510 u8 reserved_at_40[0xa0]; 9511 }; 9512 9513 struct mlx5_ifc_eqe_bits { 9514 u8 reserved_at_0[0x8]; 9515 u8 event_type[0x8]; 9516 u8 reserved_at_10[0x8]; 9517 u8 event_sub_type[0x8]; 9518 9519 u8 reserved_at_20[0xe0]; 9520 9521 union mlx5_ifc_event_auto_bits event_data; 9522 9523 u8 reserved_at_1e0[0x10]; 9524 u8 signature[0x8]; 9525 u8 reserved_at_1f8[0x7]; 9526 u8 owner[0x1]; 9527 }; 9528 9529 enum { 9530 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9531 }; 9532 9533 struct mlx5_ifc_cmd_queue_entry_bits { 9534 u8 type[0x8]; 9535 u8 reserved_at_8[0x18]; 9536 9537 u8 input_length[0x20]; 9538 9539 u8 input_mailbox_pointer_63_32[0x20]; 9540 9541 u8 input_mailbox_pointer_31_9[0x17]; 9542 u8 reserved_at_77[0x9]; 9543 9544 u8 command_input_inline_data[16][0x8]; 9545 9546 u8 command_output_inline_data[16][0x8]; 9547 9548 u8 output_mailbox_pointer_63_32[0x20]; 9549 9550 u8 output_mailbox_pointer_31_9[0x17]; 9551 u8 reserved_at_1b7[0x9]; 9552 9553 u8 output_length[0x20]; 9554 9555 u8 token[0x8]; 9556 u8 signature[0x8]; 9557 u8 reserved_at_1f0[0x8]; 9558 u8 status[0x7]; 9559 u8 ownership[0x1]; 9560 }; 9561 9562 struct mlx5_ifc_cmd_out_bits { 9563 u8 status[0x8]; 9564 u8 reserved_at_8[0x18]; 9565 9566 u8 syndrome[0x20]; 9567 9568 u8 command_output[0x20]; 9569 }; 9570 9571 struct mlx5_ifc_cmd_in_bits { 9572 u8 opcode[0x10]; 9573 u8 reserved_at_10[0x10]; 9574 9575 u8 reserved_at_20[0x10]; 9576 u8 op_mod[0x10]; 9577 9578 u8 command[][0x20]; 9579 }; 9580 9581 struct mlx5_ifc_cmd_if_box_bits { 9582 u8 mailbox_data[512][0x8]; 9583 9584 u8 reserved_at_1000[0x180]; 9585 9586 u8 next_pointer_63_32[0x20]; 9587 9588 u8 next_pointer_31_10[0x16]; 9589 u8 reserved_at_11b6[0xa]; 9590 9591 u8 block_number[0x20]; 9592 9593 u8 reserved_at_11e0[0x8]; 9594 u8 token[0x8]; 9595 u8 ctrl_signature[0x8]; 9596 u8 signature[0x8]; 9597 }; 9598 9599 struct mlx5_ifc_mtt_bits { 9600 u8 ptag_63_32[0x20]; 9601 9602 u8 ptag_31_8[0x18]; 9603 u8 reserved_at_38[0x6]; 9604 u8 wr_en[0x1]; 9605 u8 rd_en[0x1]; 9606 }; 9607 9608 struct mlx5_ifc_query_wol_rol_out_bits { 9609 u8 status[0x8]; 9610 u8 reserved_at_8[0x18]; 9611 9612 u8 syndrome[0x20]; 9613 9614 u8 reserved_at_40[0x10]; 9615 u8 rol_mode[0x8]; 9616 u8 wol_mode[0x8]; 9617 9618 u8 reserved_at_60[0x20]; 9619 }; 9620 9621 struct mlx5_ifc_query_wol_rol_in_bits { 9622 u8 opcode[0x10]; 9623 u8 reserved_at_10[0x10]; 9624 9625 u8 reserved_at_20[0x10]; 9626 u8 op_mod[0x10]; 9627 9628 u8 reserved_at_40[0x40]; 9629 }; 9630 9631 struct mlx5_ifc_set_wol_rol_out_bits { 9632 u8 status[0x8]; 9633 u8 reserved_at_8[0x18]; 9634 9635 u8 syndrome[0x20]; 9636 9637 u8 reserved_at_40[0x40]; 9638 }; 9639 9640 struct mlx5_ifc_set_wol_rol_in_bits { 9641 u8 opcode[0x10]; 9642 u8 reserved_at_10[0x10]; 9643 9644 u8 reserved_at_20[0x10]; 9645 u8 op_mod[0x10]; 9646 9647 u8 rol_mode_valid[0x1]; 9648 u8 wol_mode_valid[0x1]; 9649 u8 reserved_at_42[0xe]; 9650 u8 rol_mode[0x8]; 9651 u8 wol_mode[0x8]; 9652 9653 u8 reserved_at_60[0x20]; 9654 }; 9655 9656 enum { 9657 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9658 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9659 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9660 }; 9661 9662 enum { 9663 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9664 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9665 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9666 }; 9667 9668 enum { 9669 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9670 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9671 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9672 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9673 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9674 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9675 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9676 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9677 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9678 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9679 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9680 }; 9681 9682 struct mlx5_ifc_initial_seg_bits { 9683 u8 fw_rev_minor[0x10]; 9684 u8 fw_rev_major[0x10]; 9685 9686 u8 cmd_interface_rev[0x10]; 9687 u8 fw_rev_subminor[0x10]; 9688 9689 u8 reserved_at_40[0x40]; 9690 9691 u8 cmdq_phy_addr_63_32[0x20]; 9692 9693 u8 cmdq_phy_addr_31_12[0x14]; 9694 u8 reserved_at_b4[0x2]; 9695 u8 nic_interface[0x2]; 9696 u8 log_cmdq_size[0x4]; 9697 u8 log_cmdq_stride[0x4]; 9698 9699 u8 command_doorbell_vector[0x20]; 9700 9701 u8 reserved_at_e0[0xf00]; 9702 9703 u8 initializing[0x1]; 9704 u8 reserved_at_fe1[0x4]; 9705 u8 nic_interface_supported[0x3]; 9706 u8 embedded_cpu[0x1]; 9707 u8 reserved_at_fe9[0x17]; 9708 9709 struct mlx5_ifc_health_buffer_bits health_buffer; 9710 9711 u8 no_dram_nic_offset[0x20]; 9712 9713 u8 reserved_at_1220[0x6e40]; 9714 9715 u8 reserved_at_8060[0x1f]; 9716 u8 clear_int[0x1]; 9717 9718 u8 health_syndrome[0x8]; 9719 u8 health_counter[0x18]; 9720 9721 u8 reserved_at_80a0[0x17fc0]; 9722 }; 9723 9724 struct mlx5_ifc_mtpps_reg_bits { 9725 u8 reserved_at_0[0xc]; 9726 u8 cap_number_of_pps_pins[0x4]; 9727 u8 reserved_at_10[0x4]; 9728 u8 cap_max_num_of_pps_in_pins[0x4]; 9729 u8 reserved_at_18[0x4]; 9730 u8 cap_max_num_of_pps_out_pins[0x4]; 9731 9732 u8 reserved_at_20[0x24]; 9733 u8 cap_pin_3_mode[0x4]; 9734 u8 reserved_at_48[0x4]; 9735 u8 cap_pin_2_mode[0x4]; 9736 u8 reserved_at_50[0x4]; 9737 u8 cap_pin_1_mode[0x4]; 9738 u8 reserved_at_58[0x4]; 9739 u8 cap_pin_0_mode[0x4]; 9740 9741 u8 reserved_at_60[0x4]; 9742 u8 cap_pin_7_mode[0x4]; 9743 u8 reserved_at_68[0x4]; 9744 u8 cap_pin_6_mode[0x4]; 9745 u8 reserved_at_70[0x4]; 9746 u8 cap_pin_5_mode[0x4]; 9747 u8 reserved_at_78[0x4]; 9748 u8 cap_pin_4_mode[0x4]; 9749 9750 u8 field_select[0x20]; 9751 u8 reserved_at_a0[0x60]; 9752 9753 u8 enable[0x1]; 9754 u8 reserved_at_101[0xb]; 9755 u8 pattern[0x4]; 9756 u8 reserved_at_110[0x4]; 9757 u8 pin_mode[0x4]; 9758 u8 pin[0x8]; 9759 9760 u8 reserved_at_120[0x20]; 9761 9762 u8 time_stamp[0x40]; 9763 9764 u8 out_pulse_duration[0x10]; 9765 u8 out_periodic_adjustment[0x10]; 9766 u8 enhanced_out_periodic_adjustment[0x20]; 9767 9768 u8 reserved_at_1c0[0x20]; 9769 }; 9770 9771 struct mlx5_ifc_mtppse_reg_bits { 9772 u8 reserved_at_0[0x18]; 9773 u8 pin[0x8]; 9774 u8 event_arm[0x1]; 9775 u8 reserved_at_21[0x1b]; 9776 u8 event_generation_mode[0x4]; 9777 u8 reserved_at_40[0x40]; 9778 }; 9779 9780 struct mlx5_ifc_mcqs_reg_bits { 9781 u8 last_index_flag[0x1]; 9782 u8 reserved_at_1[0x7]; 9783 u8 fw_device[0x8]; 9784 u8 component_index[0x10]; 9785 9786 u8 reserved_at_20[0x10]; 9787 u8 identifier[0x10]; 9788 9789 u8 reserved_at_40[0x17]; 9790 u8 component_status[0x5]; 9791 u8 component_update_state[0x4]; 9792 9793 u8 last_update_state_changer_type[0x4]; 9794 u8 last_update_state_changer_host_id[0x4]; 9795 u8 reserved_at_68[0x18]; 9796 }; 9797 9798 struct mlx5_ifc_mcqi_cap_bits { 9799 u8 supported_info_bitmask[0x20]; 9800 9801 u8 component_size[0x20]; 9802 9803 u8 max_component_size[0x20]; 9804 9805 u8 log_mcda_word_size[0x4]; 9806 u8 reserved_at_64[0xc]; 9807 u8 mcda_max_write_size[0x10]; 9808 9809 u8 rd_en[0x1]; 9810 u8 reserved_at_81[0x1]; 9811 u8 match_chip_id[0x1]; 9812 u8 match_psid[0x1]; 9813 u8 check_user_timestamp[0x1]; 9814 u8 match_base_guid_mac[0x1]; 9815 u8 reserved_at_86[0x1a]; 9816 }; 9817 9818 struct mlx5_ifc_mcqi_version_bits { 9819 u8 reserved_at_0[0x2]; 9820 u8 build_time_valid[0x1]; 9821 u8 user_defined_time_valid[0x1]; 9822 u8 reserved_at_4[0x14]; 9823 u8 version_string_length[0x8]; 9824 9825 u8 version[0x20]; 9826 9827 u8 build_time[0x40]; 9828 9829 u8 user_defined_time[0x40]; 9830 9831 u8 build_tool_version[0x20]; 9832 9833 u8 reserved_at_e0[0x20]; 9834 9835 u8 version_string[92][0x8]; 9836 }; 9837 9838 struct mlx5_ifc_mcqi_activation_method_bits { 9839 u8 pending_server_ac_power_cycle[0x1]; 9840 u8 pending_server_dc_power_cycle[0x1]; 9841 u8 pending_server_reboot[0x1]; 9842 u8 pending_fw_reset[0x1]; 9843 u8 auto_activate[0x1]; 9844 u8 all_hosts_sync[0x1]; 9845 u8 device_hw_reset[0x1]; 9846 u8 reserved_at_7[0x19]; 9847 }; 9848 9849 union mlx5_ifc_mcqi_reg_data_bits { 9850 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9851 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9852 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9853 }; 9854 9855 struct mlx5_ifc_mcqi_reg_bits { 9856 u8 read_pending_component[0x1]; 9857 u8 reserved_at_1[0xf]; 9858 u8 component_index[0x10]; 9859 9860 u8 reserved_at_20[0x20]; 9861 9862 u8 reserved_at_40[0x1b]; 9863 u8 info_type[0x5]; 9864 9865 u8 info_size[0x20]; 9866 9867 u8 offset[0x20]; 9868 9869 u8 reserved_at_a0[0x10]; 9870 u8 data_size[0x10]; 9871 9872 union mlx5_ifc_mcqi_reg_data_bits data[]; 9873 }; 9874 9875 struct mlx5_ifc_mcc_reg_bits { 9876 u8 reserved_at_0[0x4]; 9877 u8 time_elapsed_since_last_cmd[0xc]; 9878 u8 reserved_at_10[0x8]; 9879 u8 instruction[0x8]; 9880 9881 u8 reserved_at_20[0x10]; 9882 u8 component_index[0x10]; 9883 9884 u8 reserved_at_40[0x8]; 9885 u8 update_handle[0x18]; 9886 9887 u8 handle_owner_type[0x4]; 9888 u8 handle_owner_host_id[0x4]; 9889 u8 reserved_at_68[0x1]; 9890 u8 control_progress[0x7]; 9891 u8 error_code[0x8]; 9892 u8 reserved_at_78[0x4]; 9893 u8 control_state[0x4]; 9894 9895 u8 component_size[0x20]; 9896 9897 u8 reserved_at_a0[0x60]; 9898 }; 9899 9900 struct mlx5_ifc_mcda_reg_bits { 9901 u8 reserved_at_0[0x8]; 9902 u8 update_handle[0x18]; 9903 9904 u8 offset[0x20]; 9905 9906 u8 reserved_at_40[0x10]; 9907 u8 size[0x10]; 9908 9909 u8 reserved_at_60[0x20]; 9910 9911 u8 data[][0x20]; 9912 }; 9913 9914 enum { 9915 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9916 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9917 }; 9918 9919 enum { 9920 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9921 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9922 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9923 }; 9924 9925 struct mlx5_ifc_mfrl_reg_bits { 9926 u8 reserved_at_0[0x20]; 9927 9928 u8 reserved_at_20[0x2]; 9929 u8 pci_sync_for_fw_update_start[0x1]; 9930 u8 pci_sync_for_fw_update_resp[0x2]; 9931 u8 rst_type_sel[0x3]; 9932 u8 reserved_at_28[0x8]; 9933 u8 reset_type[0x8]; 9934 u8 reset_level[0x8]; 9935 }; 9936 9937 struct mlx5_ifc_mirc_reg_bits { 9938 u8 reserved_at_0[0x18]; 9939 u8 status_code[0x8]; 9940 9941 u8 reserved_at_20[0x20]; 9942 }; 9943 9944 union mlx5_ifc_ports_control_registers_document_bits { 9945 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9946 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9947 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9948 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9949 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9950 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9951 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9952 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9953 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9954 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9955 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9956 struct mlx5_ifc_paos_reg_bits paos_reg; 9957 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9958 struct mlx5_ifc_peir_reg_bits peir_reg; 9959 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9960 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9961 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9962 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9963 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9964 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9965 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9966 struct mlx5_ifc_plib_reg_bits plib_reg; 9967 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9968 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9969 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9970 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9971 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9972 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9973 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9974 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9975 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9976 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9977 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9978 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9979 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9980 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9981 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9982 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9983 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9984 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9985 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9986 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9987 struct mlx5_ifc_pude_reg_bits pude_reg; 9988 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9989 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9990 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9991 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9992 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9993 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9994 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9995 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9996 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9997 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9998 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9999 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10000 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10001 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10002 u8 reserved_at_0[0x60e0]; 10003 }; 10004 10005 union mlx5_ifc_debug_enhancements_document_bits { 10006 struct mlx5_ifc_health_buffer_bits health_buffer; 10007 u8 reserved_at_0[0x200]; 10008 }; 10009 10010 union mlx5_ifc_uplink_pci_interface_document_bits { 10011 struct mlx5_ifc_initial_seg_bits initial_seg; 10012 u8 reserved_at_0[0x20060]; 10013 }; 10014 10015 struct mlx5_ifc_set_flow_table_root_out_bits { 10016 u8 status[0x8]; 10017 u8 reserved_at_8[0x18]; 10018 10019 u8 syndrome[0x20]; 10020 10021 u8 reserved_at_40[0x40]; 10022 }; 10023 10024 struct mlx5_ifc_set_flow_table_root_in_bits { 10025 u8 opcode[0x10]; 10026 u8 reserved_at_10[0x10]; 10027 10028 u8 reserved_at_20[0x10]; 10029 u8 op_mod[0x10]; 10030 10031 u8 other_vport[0x1]; 10032 u8 reserved_at_41[0xf]; 10033 u8 vport_number[0x10]; 10034 10035 u8 reserved_at_60[0x20]; 10036 10037 u8 table_type[0x8]; 10038 u8 reserved_at_88[0x18]; 10039 10040 u8 reserved_at_a0[0x8]; 10041 u8 table_id[0x18]; 10042 10043 u8 reserved_at_c0[0x8]; 10044 u8 underlay_qpn[0x18]; 10045 u8 reserved_at_e0[0x120]; 10046 }; 10047 10048 enum { 10049 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10050 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10051 }; 10052 10053 struct mlx5_ifc_modify_flow_table_out_bits { 10054 u8 status[0x8]; 10055 u8 reserved_at_8[0x18]; 10056 10057 u8 syndrome[0x20]; 10058 10059 u8 reserved_at_40[0x40]; 10060 }; 10061 10062 struct mlx5_ifc_modify_flow_table_in_bits { 10063 u8 opcode[0x10]; 10064 u8 reserved_at_10[0x10]; 10065 10066 u8 reserved_at_20[0x10]; 10067 u8 op_mod[0x10]; 10068 10069 u8 other_vport[0x1]; 10070 u8 reserved_at_41[0xf]; 10071 u8 vport_number[0x10]; 10072 10073 u8 reserved_at_60[0x10]; 10074 u8 modify_field_select[0x10]; 10075 10076 u8 table_type[0x8]; 10077 u8 reserved_at_88[0x18]; 10078 10079 u8 reserved_at_a0[0x8]; 10080 u8 table_id[0x18]; 10081 10082 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10083 }; 10084 10085 struct mlx5_ifc_ets_tcn_config_reg_bits { 10086 u8 g[0x1]; 10087 u8 b[0x1]; 10088 u8 r[0x1]; 10089 u8 reserved_at_3[0x9]; 10090 u8 group[0x4]; 10091 u8 reserved_at_10[0x9]; 10092 u8 bw_allocation[0x7]; 10093 10094 u8 reserved_at_20[0xc]; 10095 u8 max_bw_units[0x4]; 10096 u8 reserved_at_30[0x8]; 10097 u8 max_bw_value[0x8]; 10098 }; 10099 10100 struct mlx5_ifc_ets_global_config_reg_bits { 10101 u8 reserved_at_0[0x2]; 10102 u8 r[0x1]; 10103 u8 reserved_at_3[0x1d]; 10104 10105 u8 reserved_at_20[0xc]; 10106 u8 max_bw_units[0x4]; 10107 u8 reserved_at_30[0x8]; 10108 u8 max_bw_value[0x8]; 10109 }; 10110 10111 struct mlx5_ifc_qetc_reg_bits { 10112 u8 reserved_at_0[0x8]; 10113 u8 port_number[0x8]; 10114 u8 reserved_at_10[0x30]; 10115 10116 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10117 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10118 }; 10119 10120 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10121 u8 e[0x1]; 10122 u8 reserved_at_01[0x0b]; 10123 u8 prio[0x04]; 10124 }; 10125 10126 struct mlx5_ifc_qpdpm_reg_bits { 10127 u8 reserved_at_0[0x8]; 10128 u8 local_port[0x8]; 10129 u8 reserved_at_10[0x10]; 10130 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10131 }; 10132 10133 struct mlx5_ifc_qpts_reg_bits { 10134 u8 reserved_at_0[0x8]; 10135 u8 local_port[0x8]; 10136 u8 reserved_at_10[0x2d]; 10137 u8 trust_state[0x3]; 10138 }; 10139 10140 struct mlx5_ifc_pptb_reg_bits { 10141 u8 reserved_at_0[0x2]; 10142 u8 mm[0x2]; 10143 u8 reserved_at_4[0x4]; 10144 u8 local_port[0x8]; 10145 u8 reserved_at_10[0x6]; 10146 u8 cm[0x1]; 10147 u8 um[0x1]; 10148 u8 pm[0x8]; 10149 10150 u8 prio_x_buff[0x20]; 10151 10152 u8 pm_msb[0x8]; 10153 u8 reserved_at_48[0x10]; 10154 u8 ctrl_buff[0x4]; 10155 u8 untagged_buff[0x4]; 10156 }; 10157 10158 struct mlx5_ifc_sbcam_reg_bits { 10159 u8 reserved_at_0[0x8]; 10160 u8 feature_group[0x8]; 10161 u8 reserved_at_10[0x8]; 10162 u8 access_reg_group[0x8]; 10163 10164 u8 reserved_at_20[0x20]; 10165 10166 u8 sb_access_reg_cap_mask[4][0x20]; 10167 10168 u8 reserved_at_c0[0x80]; 10169 10170 u8 sb_feature_cap_mask[4][0x20]; 10171 10172 u8 reserved_at_1c0[0x40]; 10173 10174 u8 cap_total_buffer_size[0x20]; 10175 10176 u8 cap_cell_size[0x10]; 10177 u8 cap_max_pg_buffers[0x8]; 10178 u8 cap_num_pool_supported[0x8]; 10179 10180 u8 reserved_at_240[0x8]; 10181 u8 cap_sbsr_stat_size[0x8]; 10182 u8 cap_max_tclass_data[0x8]; 10183 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10184 }; 10185 10186 struct mlx5_ifc_pbmc_reg_bits { 10187 u8 reserved_at_0[0x8]; 10188 u8 local_port[0x8]; 10189 u8 reserved_at_10[0x10]; 10190 10191 u8 xoff_timer_value[0x10]; 10192 u8 xoff_refresh[0x10]; 10193 10194 u8 reserved_at_40[0x9]; 10195 u8 fullness_threshold[0x7]; 10196 u8 port_buffer_size[0x10]; 10197 10198 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10199 10200 u8 reserved_at_2e0[0x40]; 10201 }; 10202 10203 struct mlx5_ifc_qtct_reg_bits { 10204 u8 reserved_at_0[0x8]; 10205 u8 port_number[0x8]; 10206 u8 reserved_at_10[0xd]; 10207 u8 prio[0x3]; 10208 10209 u8 reserved_at_20[0x1d]; 10210 u8 tclass[0x3]; 10211 }; 10212 10213 struct mlx5_ifc_mcia_reg_bits { 10214 u8 l[0x1]; 10215 u8 reserved_at_1[0x7]; 10216 u8 module[0x8]; 10217 u8 reserved_at_10[0x8]; 10218 u8 status[0x8]; 10219 10220 u8 i2c_device_address[0x8]; 10221 u8 page_number[0x8]; 10222 u8 device_address[0x10]; 10223 10224 u8 reserved_at_40[0x10]; 10225 u8 size[0x10]; 10226 10227 u8 reserved_at_60[0x20]; 10228 10229 u8 dword_0[0x20]; 10230 u8 dword_1[0x20]; 10231 u8 dword_2[0x20]; 10232 u8 dword_3[0x20]; 10233 u8 dword_4[0x20]; 10234 u8 dword_5[0x20]; 10235 u8 dword_6[0x20]; 10236 u8 dword_7[0x20]; 10237 u8 dword_8[0x20]; 10238 u8 dword_9[0x20]; 10239 u8 dword_10[0x20]; 10240 u8 dword_11[0x20]; 10241 }; 10242 10243 struct mlx5_ifc_dcbx_param_bits { 10244 u8 dcbx_cee_cap[0x1]; 10245 u8 dcbx_ieee_cap[0x1]; 10246 u8 dcbx_standby_cap[0x1]; 10247 u8 reserved_at_3[0x5]; 10248 u8 port_number[0x8]; 10249 u8 reserved_at_10[0xa]; 10250 u8 max_application_table_size[6]; 10251 u8 reserved_at_20[0x15]; 10252 u8 version_oper[0x3]; 10253 u8 reserved_at_38[5]; 10254 u8 version_admin[0x3]; 10255 u8 willing_admin[0x1]; 10256 u8 reserved_at_41[0x3]; 10257 u8 pfc_cap_oper[0x4]; 10258 u8 reserved_at_48[0x4]; 10259 u8 pfc_cap_admin[0x4]; 10260 u8 reserved_at_50[0x4]; 10261 u8 num_of_tc_oper[0x4]; 10262 u8 reserved_at_58[0x4]; 10263 u8 num_of_tc_admin[0x4]; 10264 u8 remote_willing[0x1]; 10265 u8 reserved_at_61[3]; 10266 u8 remote_pfc_cap[4]; 10267 u8 reserved_at_68[0x14]; 10268 u8 remote_num_of_tc[0x4]; 10269 u8 reserved_at_80[0x18]; 10270 u8 error[0x8]; 10271 u8 reserved_at_a0[0x160]; 10272 }; 10273 10274 struct mlx5_ifc_lagc_bits { 10275 u8 reserved_at_0[0x1d]; 10276 u8 lag_state[0x3]; 10277 10278 u8 reserved_at_20[0x14]; 10279 u8 tx_remap_affinity_2[0x4]; 10280 u8 reserved_at_38[0x4]; 10281 u8 tx_remap_affinity_1[0x4]; 10282 }; 10283 10284 struct mlx5_ifc_create_lag_out_bits { 10285 u8 status[0x8]; 10286 u8 reserved_at_8[0x18]; 10287 10288 u8 syndrome[0x20]; 10289 10290 u8 reserved_at_40[0x40]; 10291 }; 10292 10293 struct mlx5_ifc_create_lag_in_bits { 10294 u8 opcode[0x10]; 10295 u8 reserved_at_10[0x10]; 10296 10297 u8 reserved_at_20[0x10]; 10298 u8 op_mod[0x10]; 10299 10300 struct mlx5_ifc_lagc_bits ctx; 10301 }; 10302 10303 struct mlx5_ifc_modify_lag_out_bits { 10304 u8 status[0x8]; 10305 u8 reserved_at_8[0x18]; 10306 10307 u8 syndrome[0x20]; 10308 10309 u8 reserved_at_40[0x40]; 10310 }; 10311 10312 struct mlx5_ifc_modify_lag_in_bits { 10313 u8 opcode[0x10]; 10314 u8 reserved_at_10[0x10]; 10315 10316 u8 reserved_at_20[0x10]; 10317 u8 op_mod[0x10]; 10318 10319 u8 reserved_at_40[0x20]; 10320 u8 field_select[0x20]; 10321 10322 struct mlx5_ifc_lagc_bits ctx; 10323 }; 10324 10325 struct mlx5_ifc_query_lag_out_bits { 10326 u8 status[0x8]; 10327 u8 reserved_at_8[0x18]; 10328 10329 u8 syndrome[0x20]; 10330 10331 struct mlx5_ifc_lagc_bits ctx; 10332 }; 10333 10334 struct mlx5_ifc_query_lag_in_bits { 10335 u8 opcode[0x10]; 10336 u8 reserved_at_10[0x10]; 10337 10338 u8 reserved_at_20[0x10]; 10339 u8 op_mod[0x10]; 10340 10341 u8 reserved_at_40[0x40]; 10342 }; 10343 10344 struct mlx5_ifc_destroy_lag_out_bits { 10345 u8 status[0x8]; 10346 u8 reserved_at_8[0x18]; 10347 10348 u8 syndrome[0x20]; 10349 10350 u8 reserved_at_40[0x40]; 10351 }; 10352 10353 struct mlx5_ifc_destroy_lag_in_bits { 10354 u8 opcode[0x10]; 10355 u8 reserved_at_10[0x10]; 10356 10357 u8 reserved_at_20[0x10]; 10358 u8 op_mod[0x10]; 10359 10360 u8 reserved_at_40[0x40]; 10361 }; 10362 10363 struct mlx5_ifc_create_vport_lag_out_bits { 10364 u8 status[0x8]; 10365 u8 reserved_at_8[0x18]; 10366 10367 u8 syndrome[0x20]; 10368 10369 u8 reserved_at_40[0x40]; 10370 }; 10371 10372 struct mlx5_ifc_create_vport_lag_in_bits { 10373 u8 opcode[0x10]; 10374 u8 reserved_at_10[0x10]; 10375 10376 u8 reserved_at_20[0x10]; 10377 u8 op_mod[0x10]; 10378 10379 u8 reserved_at_40[0x40]; 10380 }; 10381 10382 struct mlx5_ifc_destroy_vport_lag_out_bits { 10383 u8 status[0x8]; 10384 u8 reserved_at_8[0x18]; 10385 10386 u8 syndrome[0x20]; 10387 10388 u8 reserved_at_40[0x40]; 10389 }; 10390 10391 struct mlx5_ifc_destroy_vport_lag_in_bits { 10392 u8 opcode[0x10]; 10393 u8 reserved_at_10[0x10]; 10394 10395 u8 reserved_at_20[0x10]; 10396 u8 op_mod[0x10]; 10397 10398 u8 reserved_at_40[0x40]; 10399 }; 10400 10401 struct mlx5_ifc_alloc_memic_in_bits { 10402 u8 opcode[0x10]; 10403 u8 reserved_at_10[0x10]; 10404 10405 u8 reserved_at_20[0x10]; 10406 u8 op_mod[0x10]; 10407 10408 u8 reserved_at_30[0x20]; 10409 10410 u8 reserved_at_40[0x18]; 10411 u8 log_memic_addr_alignment[0x8]; 10412 10413 u8 range_start_addr[0x40]; 10414 10415 u8 range_size[0x20]; 10416 10417 u8 memic_size[0x20]; 10418 }; 10419 10420 struct mlx5_ifc_alloc_memic_out_bits { 10421 u8 status[0x8]; 10422 u8 reserved_at_8[0x18]; 10423 10424 u8 syndrome[0x20]; 10425 10426 u8 memic_start_addr[0x40]; 10427 }; 10428 10429 struct mlx5_ifc_dealloc_memic_in_bits { 10430 u8 opcode[0x10]; 10431 u8 reserved_at_10[0x10]; 10432 10433 u8 reserved_at_20[0x10]; 10434 u8 op_mod[0x10]; 10435 10436 u8 reserved_at_40[0x40]; 10437 10438 u8 memic_start_addr[0x40]; 10439 10440 u8 memic_size[0x20]; 10441 10442 u8 reserved_at_e0[0x20]; 10443 }; 10444 10445 struct mlx5_ifc_dealloc_memic_out_bits { 10446 u8 status[0x8]; 10447 u8 reserved_at_8[0x18]; 10448 10449 u8 syndrome[0x20]; 10450 10451 u8 reserved_at_40[0x40]; 10452 }; 10453 10454 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10455 u8 opcode[0x10]; 10456 u8 uid[0x10]; 10457 10458 u8 vhca_tunnel_id[0x10]; 10459 u8 obj_type[0x10]; 10460 10461 u8 obj_id[0x20]; 10462 10463 u8 reserved_at_60[0x20]; 10464 }; 10465 10466 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10467 u8 status[0x8]; 10468 u8 reserved_at_8[0x18]; 10469 10470 u8 syndrome[0x20]; 10471 10472 u8 obj_id[0x20]; 10473 10474 u8 reserved_at_60[0x20]; 10475 }; 10476 10477 struct mlx5_ifc_umem_bits { 10478 u8 reserved_at_0[0x80]; 10479 10480 u8 reserved_at_80[0x1b]; 10481 u8 log_page_size[0x5]; 10482 10483 u8 page_offset[0x20]; 10484 10485 u8 num_of_mtt[0x40]; 10486 10487 struct mlx5_ifc_mtt_bits mtt[]; 10488 }; 10489 10490 struct mlx5_ifc_uctx_bits { 10491 u8 cap[0x20]; 10492 10493 u8 reserved_at_20[0x160]; 10494 }; 10495 10496 struct mlx5_ifc_sw_icm_bits { 10497 u8 modify_field_select[0x40]; 10498 10499 u8 reserved_at_40[0x18]; 10500 u8 log_sw_icm_size[0x8]; 10501 10502 u8 reserved_at_60[0x20]; 10503 10504 u8 sw_icm_start_addr[0x40]; 10505 10506 u8 reserved_at_c0[0x140]; 10507 }; 10508 10509 struct mlx5_ifc_geneve_tlv_option_bits { 10510 u8 modify_field_select[0x40]; 10511 10512 u8 reserved_at_40[0x18]; 10513 u8 geneve_option_fte_index[0x8]; 10514 10515 u8 option_class[0x10]; 10516 u8 option_type[0x8]; 10517 u8 reserved_at_78[0x3]; 10518 u8 option_data_length[0x5]; 10519 10520 u8 reserved_at_80[0x180]; 10521 }; 10522 10523 struct mlx5_ifc_create_umem_in_bits { 10524 u8 opcode[0x10]; 10525 u8 uid[0x10]; 10526 10527 u8 reserved_at_20[0x10]; 10528 u8 op_mod[0x10]; 10529 10530 u8 reserved_at_40[0x40]; 10531 10532 struct mlx5_ifc_umem_bits umem; 10533 }; 10534 10535 struct mlx5_ifc_create_umem_out_bits { 10536 u8 status[0x8]; 10537 u8 reserved_at_8[0x18]; 10538 10539 u8 syndrome[0x20]; 10540 10541 u8 reserved_at_40[0x8]; 10542 u8 umem_id[0x18]; 10543 10544 u8 reserved_at_60[0x20]; 10545 }; 10546 10547 struct mlx5_ifc_destroy_umem_in_bits { 10548 u8 opcode[0x10]; 10549 u8 uid[0x10]; 10550 10551 u8 reserved_at_20[0x10]; 10552 u8 op_mod[0x10]; 10553 10554 u8 reserved_at_40[0x8]; 10555 u8 umem_id[0x18]; 10556 10557 u8 reserved_at_60[0x20]; 10558 }; 10559 10560 struct mlx5_ifc_destroy_umem_out_bits { 10561 u8 status[0x8]; 10562 u8 reserved_at_8[0x18]; 10563 10564 u8 syndrome[0x20]; 10565 10566 u8 reserved_at_40[0x40]; 10567 }; 10568 10569 struct mlx5_ifc_create_uctx_in_bits { 10570 u8 opcode[0x10]; 10571 u8 reserved_at_10[0x10]; 10572 10573 u8 reserved_at_20[0x10]; 10574 u8 op_mod[0x10]; 10575 10576 u8 reserved_at_40[0x40]; 10577 10578 struct mlx5_ifc_uctx_bits uctx; 10579 }; 10580 10581 struct mlx5_ifc_create_uctx_out_bits { 10582 u8 status[0x8]; 10583 u8 reserved_at_8[0x18]; 10584 10585 u8 syndrome[0x20]; 10586 10587 u8 reserved_at_40[0x10]; 10588 u8 uid[0x10]; 10589 10590 u8 reserved_at_60[0x20]; 10591 }; 10592 10593 struct mlx5_ifc_destroy_uctx_in_bits { 10594 u8 opcode[0x10]; 10595 u8 reserved_at_10[0x10]; 10596 10597 u8 reserved_at_20[0x10]; 10598 u8 op_mod[0x10]; 10599 10600 u8 reserved_at_40[0x10]; 10601 u8 uid[0x10]; 10602 10603 u8 reserved_at_60[0x20]; 10604 }; 10605 10606 struct mlx5_ifc_destroy_uctx_out_bits { 10607 u8 status[0x8]; 10608 u8 reserved_at_8[0x18]; 10609 10610 u8 syndrome[0x20]; 10611 10612 u8 reserved_at_40[0x40]; 10613 }; 10614 10615 struct mlx5_ifc_create_sw_icm_in_bits { 10616 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10617 struct mlx5_ifc_sw_icm_bits sw_icm; 10618 }; 10619 10620 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10621 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10622 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10623 }; 10624 10625 struct mlx5_ifc_mtrc_string_db_param_bits { 10626 u8 string_db_base_address[0x20]; 10627 10628 u8 reserved_at_20[0x8]; 10629 u8 string_db_size[0x18]; 10630 }; 10631 10632 struct mlx5_ifc_mtrc_cap_bits { 10633 u8 trace_owner[0x1]; 10634 u8 trace_to_memory[0x1]; 10635 u8 reserved_at_2[0x4]; 10636 u8 trc_ver[0x2]; 10637 u8 reserved_at_8[0x14]; 10638 u8 num_string_db[0x4]; 10639 10640 u8 first_string_trace[0x8]; 10641 u8 num_string_trace[0x8]; 10642 u8 reserved_at_30[0x28]; 10643 10644 u8 log_max_trace_buffer_size[0x8]; 10645 10646 u8 reserved_at_60[0x20]; 10647 10648 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10649 10650 u8 reserved_at_280[0x180]; 10651 }; 10652 10653 struct mlx5_ifc_mtrc_conf_bits { 10654 u8 reserved_at_0[0x1c]; 10655 u8 trace_mode[0x4]; 10656 u8 reserved_at_20[0x18]; 10657 u8 log_trace_buffer_size[0x8]; 10658 u8 trace_mkey[0x20]; 10659 u8 reserved_at_60[0x3a0]; 10660 }; 10661 10662 struct mlx5_ifc_mtrc_stdb_bits { 10663 u8 string_db_index[0x4]; 10664 u8 reserved_at_4[0x4]; 10665 u8 read_size[0x18]; 10666 u8 start_offset[0x20]; 10667 u8 string_db_data[]; 10668 }; 10669 10670 struct mlx5_ifc_mtrc_ctrl_bits { 10671 u8 trace_status[0x2]; 10672 u8 reserved_at_2[0x2]; 10673 u8 arm_event[0x1]; 10674 u8 reserved_at_5[0xb]; 10675 u8 modify_field_select[0x10]; 10676 u8 reserved_at_20[0x2b]; 10677 u8 current_timestamp52_32[0x15]; 10678 u8 current_timestamp31_0[0x20]; 10679 u8 reserved_at_80[0x180]; 10680 }; 10681 10682 struct mlx5_ifc_host_params_context_bits { 10683 u8 host_number[0x8]; 10684 u8 reserved_at_8[0x7]; 10685 u8 host_pf_disabled[0x1]; 10686 u8 host_num_of_vfs[0x10]; 10687 10688 u8 host_total_vfs[0x10]; 10689 u8 host_pci_bus[0x10]; 10690 10691 u8 reserved_at_40[0x10]; 10692 u8 host_pci_device[0x10]; 10693 10694 u8 reserved_at_60[0x10]; 10695 u8 host_pci_function[0x10]; 10696 10697 u8 reserved_at_80[0x180]; 10698 }; 10699 10700 struct mlx5_ifc_query_esw_functions_in_bits { 10701 u8 opcode[0x10]; 10702 u8 reserved_at_10[0x10]; 10703 10704 u8 reserved_at_20[0x10]; 10705 u8 op_mod[0x10]; 10706 10707 u8 reserved_at_40[0x40]; 10708 }; 10709 10710 struct mlx5_ifc_query_esw_functions_out_bits { 10711 u8 status[0x8]; 10712 u8 reserved_at_8[0x18]; 10713 10714 u8 syndrome[0x20]; 10715 10716 u8 reserved_at_40[0x40]; 10717 10718 struct mlx5_ifc_host_params_context_bits host_params_context; 10719 10720 u8 reserved_at_280[0x180]; 10721 u8 host_sf_enable[][0x40]; 10722 }; 10723 10724 struct mlx5_ifc_sf_partition_bits { 10725 u8 reserved_at_0[0x10]; 10726 u8 log_num_sf[0x8]; 10727 u8 log_sf_bar_size[0x8]; 10728 }; 10729 10730 struct mlx5_ifc_query_sf_partitions_out_bits { 10731 u8 status[0x8]; 10732 u8 reserved_at_8[0x18]; 10733 10734 u8 syndrome[0x20]; 10735 10736 u8 reserved_at_40[0x18]; 10737 u8 num_sf_partitions[0x8]; 10738 10739 u8 reserved_at_60[0x20]; 10740 10741 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10742 }; 10743 10744 struct mlx5_ifc_query_sf_partitions_in_bits { 10745 u8 opcode[0x10]; 10746 u8 reserved_at_10[0x10]; 10747 10748 u8 reserved_at_20[0x10]; 10749 u8 op_mod[0x10]; 10750 10751 u8 reserved_at_40[0x40]; 10752 }; 10753 10754 struct mlx5_ifc_dealloc_sf_out_bits { 10755 u8 status[0x8]; 10756 u8 reserved_at_8[0x18]; 10757 10758 u8 syndrome[0x20]; 10759 10760 u8 reserved_at_40[0x40]; 10761 }; 10762 10763 struct mlx5_ifc_dealloc_sf_in_bits { 10764 u8 opcode[0x10]; 10765 u8 reserved_at_10[0x10]; 10766 10767 u8 reserved_at_20[0x10]; 10768 u8 op_mod[0x10]; 10769 10770 u8 reserved_at_40[0x10]; 10771 u8 function_id[0x10]; 10772 10773 u8 reserved_at_60[0x20]; 10774 }; 10775 10776 struct mlx5_ifc_alloc_sf_out_bits { 10777 u8 status[0x8]; 10778 u8 reserved_at_8[0x18]; 10779 10780 u8 syndrome[0x20]; 10781 10782 u8 reserved_at_40[0x40]; 10783 }; 10784 10785 struct mlx5_ifc_alloc_sf_in_bits { 10786 u8 opcode[0x10]; 10787 u8 reserved_at_10[0x10]; 10788 10789 u8 reserved_at_20[0x10]; 10790 u8 op_mod[0x10]; 10791 10792 u8 reserved_at_40[0x10]; 10793 u8 function_id[0x10]; 10794 10795 u8 reserved_at_60[0x20]; 10796 }; 10797 10798 struct mlx5_ifc_affiliated_event_header_bits { 10799 u8 reserved_at_0[0x10]; 10800 u8 obj_type[0x10]; 10801 10802 u8 obj_id[0x20]; 10803 }; 10804 10805 enum { 10806 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10807 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10808 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10809 }; 10810 10811 enum { 10812 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10813 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10814 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10815 }; 10816 10817 enum { 10818 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10819 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10820 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10821 }; 10822 10823 struct mlx5_ifc_ipsec_obj_bits { 10824 u8 modify_field_select[0x40]; 10825 u8 full_offload[0x1]; 10826 u8 reserved_at_41[0x1]; 10827 u8 esn_en[0x1]; 10828 u8 esn_overlap[0x1]; 10829 u8 reserved_at_44[0x2]; 10830 u8 icv_length[0x2]; 10831 u8 reserved_at_48[0x4]; 10832 u8 aso_return_reg[0x4]; 10833 u8 reserved_at_50[0x10]; 10834 10835 u8 esn_msb[0x20]; 10836 10837 u8 reserved_at_80[0x8]; 10838 u8 dekn[0x18]; 10839 10840 u8 salt[0x20]; 10841 10842 u8 implicit_iv[0x40]; 10843 10844 u8 reserved_at_100[0x700]; 10845 }; 10846 10847 struct mlx5_ifc_create_ipsec_obj_in_bits { 10848 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10849 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10850 }; 10851 10852 enum { 10853 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10854 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10855 }; 10856 10857 struct mlx5_ifc_query_ipsec_obj_out_bits { 10858 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10859 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10860 }; 10861 10862 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10863 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10864 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10865 }; 10866 10867 struct mlx5_ifc_encryption_key_obj_bits { 10868 u8 modify_field_select[0x40]; 10869 10870 u8 reserved_at_40[0x14]; 10871 u8 key_size[0x4]; 10872 u8 reserved_at_58[0x4]; 10873 u8 key_type[0x4]; 10874 10875 u8 reserved_at_60[0x8]; 10876 u8 pd[0x18]; 10877 10878 u8 reserved_at_80[0x180]; 10879 u8 key[8][0x20]; 10880 10881 u8 reserved_at_300[0x500]; 10882 }; 10883 10884 struct mlx5_ifc_create_encryption_key_in_bits { 10885 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10886 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10887 }; 10888 10889 struct mlx5_ifc_sampler_obj_bits { 10890 u8 modify_field_select[0x40]; 10891 10892 u8 table_type[0x8]; 10893 u8 level[0x8]; 10894 u8 reserved_at_50[0xf]; 10895 u8 ignore_flow_level[0x1]; 10896 10897 u8 sample_ratio[0x20]; 10898 10899 u8 reserved_at_80[0x8]; 10900 u8 sample_table_id[0x18]; 10901 10902 u8 reserved_at_a0[0x8]; 10903 u8 default_table_id[0x18]; 10904 10905 u8 sw_steering_icm_address_rx[0x40]; 10906 u8 sw_steering_icm_address_tx[0x40]; 10907 10908 u8 reserved_at_140[0xa0]; 10909 }; 10910 10911 struct mlx5_ifc_create_sampler_obj_in_bits { 10912 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10913 struct mlx5_ifc_sampler_obj_bits sampler_object; 10914 }; 10915 10916 enum { 10917 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10918 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10919 }; 10920 10921 enum { 10922 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10923 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10924 }; 10925 10926 struct mlx5_ifc_tls_static_params_bits { 10927 u8 const_2[0x2]; 10928 u8 tls_version[0x4]; 10929 u8 const_1[0x2]; 10930 u8 reserved_at_8[0x14]; 10931 u8 encryption_standard[0x4]; 10932 10933 u8 reserved_at_20[0x20]; 10934 10935 u8 initial_record_number[0x40]; 10936 10937 u8 resync_tcp_sn[0x20]; 10938 10939 u8 gcm_iv[0x20]; 10940 10941 u8 implicit_iv[0x40]; 10942 10943 u8 reserved_at_100[0x8]; 10944 u8 dek_index[0x18]; 10945 10946 u8 reserved_at_120[0xe0]; 10947 }; 10948 10949 struct mlx5_ifc_tls_progress_params_bits { 10950 u8 next_record_tcp_sn[0x20]; 10951 10952 u8 hw_resync_tcp_sn[0x20]; 10953 10954 u8 record_tracker_state[0x2]; 10955 u8 auth_state[0x2]; 10956 u8 reserved_at_44[0x4]; 10957 u8 hw_offset_record_number[0x18]; 10958 }; 10959 10960 enum { 10961 MLX5_MTT_PERM_READ = 1 << 0, 10962 MLX5_MTT_PERM_WRITE = 1 << 1, 10963 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 10964 }; 10965 10966 #endif /* MLX5_IFC_H */ 10967