1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_CREATE_MKEY = 0x200, 129 MLX5_CMD_OP_QUERY_MKEY = 0x201, 130 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 131 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 132 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 133 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 134 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 135 MLX5_CMD_OP_CREATE_EQ = 0x301, 136 MLX5_CMD_OP_DESTROY_EQ = 0x302, 137 MLX5_CMD_OP_QUERY_EQ = 0x303, 138 MLX5_CMD_OP_GEN_EQE = 0x304, 139 MLX5_CMD_OP_CREATE_CQ = 0x400, 140 MLX5_CMD_OP_DESTROY_CQ = 0x401, 141 MLX5_CMD_OP_QUERY_CQ = 0x402, 142 MLX5_CMD_OP_MODIFY_CQ = 0x403, 143 MLX5_CMD_OP_CREATE_QP = 0x500, 144 MLX5_CMD_OP_DESTROY_QP = 0x501, 145 MLX5_CMD_OP_RST2INIT_QP = 0x502, 146 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 147 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 148 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 149 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 150 MLX5_CMD_OP_2ERR_QP = 0x507, 151 MLX5_CMD_OP_2RST_QP = 0x50a, 152 MLX5_CMD_OP_QUERY_QP = 0x50b, 153 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 154 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 155 MLX5_CMD_OP_CREATE_PSV = 0x600, 156 MLX5_CMD_OP_DESTROY_PSV = 0x601, 157 MLX5_CMD_OP_CREATE_SRQ = 0x700, 158 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 159 MLX5_CMD_OP_QUERY_SRQ = 0x702, 160 MLX5_CMD_OP_ARM_RQ = 0x703, 161 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 162 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 163 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 164 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 165 MLX5_CMD_OP_CREATE_DCT = 0x710, 166 MLX5_CMD_OP_DESTROY_DCT = 0x711, 167 MLX5_CMD_OP_DRAIN_DCT = 0x712, 168 MLX5_CMD_OP_QUERY_DCT = 0x713, 169 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 170 MLX5_CMD_OP_CREATE_XRQ = 0x717, 171 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 172 MLX5_CMD_OP_QUERY_XRQ = 0x719, 173 MLX5_CMD_OP_ARM_XRQ = 0x71a, 174 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 175 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 176 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 177 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 178 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 179 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 180 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 181 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 182 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 183 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 184 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 185 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 186 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 187 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 188 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 189 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 192 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 193 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 194 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 195 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 196 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 197 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 198 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 199 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 200 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 201 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 202 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 203 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 204 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 205 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 206 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 207 MLX5_CMD_OP_ALLOC_PD = 0x800, 208 MLX5_CMD_OP_DEALLOC_PD = 0x801, 209 MLX5_CMD_OP_ALLOC_UAR = 0x802, 210 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 211 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 212 MLX5_CMD_OP_ACCESS_REG = 0x805, 213 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 214 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 215 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 216 MLX5_CMD_OP_MAD_IFC = 0x50d, 217 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 218 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 219 MLX5_CMD_OP_NOP = 0x80d, 220 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 221 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 222 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 223 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 224 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 225 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 226 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 227 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 228 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 229 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 230 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 231 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 232 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 233 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 234 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 235 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 236 MLX5_CMD_OP_CREATE_LAG = 0x840, 237 MLX5_CMD_OP_MODIFY_LAG = 0x841, 238 MLX5_CMD_OP_QUERY_LAG = 0x842, 239 MLX5_CMD_OP_DESTROY_LAG = 0x843, 240 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 241 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 242 MLX5_CMD_OP_CREATE_TIR = 0x900, 243 MLX5_CMD_OP_MODIFY_TIR = 0x901, 244 MLX5_CMD_OP_DESTROY_TIR = 0x902, 245 MLX5_CMD_OP_QUERY_TIR = 0x903, 246 MLX5_CMD_OP_CREATE_SQ = 0x904, 247 MLX5_CMD_OP_MODIFY_SQ = 0x905, 248 MLX5_CMD_OP_DESTROY_SQ = 0x906, 249 MLX5_CMD_OP_QUERY_SQ = 0x907, 250 MLX5_CMD_OP_CREATE_RQ = 0x908, 251 MLX5_CMD_OP_MODIFY_RQ = 0x909, 252 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 253 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 254 MLX5_CMD_OP_QUERY_RQ = 0x90b, 255 MLX5_CMD_OP_CREATE_RMP = 0x90c, 256 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 257 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 258 MLX5_CMD_OP_QUERY_RMP = 0x90f, 259 MLX5_CMD_OP_CREATE_TIS = 0x912, 260 MLX5_CMD_OP_MODIFY_TIS = 0x913, 261 MLX5_CMD_OP_DESTROY_TIS = 0x914, 262 MLX5_CMD_OP_QUERY_TIS = 0x915, 263 MLX5_CMD_OP_CREATE_RQT = 0x916, 264 MLX5_CMD_OP_MODIFY_RQT = 0x917, 265 MLX5_CMD_OP_DESTROY_RQT = 0x918, 266 MLX5_CMD_OP_QUERY_RQT = 0x919, 267 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 268 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 269 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 270 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 271 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 272 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 273 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 274 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 276 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 277 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 278 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 279 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 280 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 281 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 282 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 283 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 284 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 285 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 286 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 287 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 288 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 289 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 290 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 291 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 292 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 293 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 294 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 295 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 296 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 297 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 298 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 299 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 300 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 301 MLX5_CMD_OP_MAX 302 }; 303 304 /* Valid range for general commands that don't work over an object */ 305 enum { 306 MLX5_CMD_OP_GENERAL_START = 0xb00, 307 MLX5_CMD_OP_GENERAL_END = 0xd00, 308 }; 309 310 struct mlx5_ifc_flow_table_fields_supported_bits { 311 u8 outer_dmac[0x1]; 312 u8 outer_smac[0x1]; 313 u8 outer_ether_type[0x1]; 314 u8 outer_ip_version[0x1]; 315 u8 outer_first_prio[0x1]; 316 u8 outer_first_cfi[0x1]; 317 u8 outer_first_vid[0x1]; 318 u8 outer_ipv4_ttl[0x1]; 319 u8 outer_second_prio[0x1]; 320 u8 outer_second_cfi[0x1]; 321 u8 outer_second_vid[0x1]; 322 u8 reserved_at_b[0x1]; 323 u8 outer_sip[0x1]; 324 u8 outer_dip[0x1]; 325 u8 outer_frag[0x1]; 326 u8 outer_ip_protocol[0x1]; 327 u8 outer_ip_ecn[0x1]; 328 u8 outer_ip_dscp[0x1]; 329 u8 outer_udp_sport[0x1]; 330 u8 outer_udp_dport[0x1]; 331 u8 outer_tcp_sport[0x1]; 332 u8 outer_tcp_dport[0x1]; 333 u8 outer_tcp_flags[0x1]; 334 u8 outer_gre_protocol[0x1]; 335 u8 outer_gre_key[0x1]; 336 u8 outer_vxlan_vni[0x1]; 337 u8 outer_geneve_vni[0x1]; 338 u8 outer_geneve_oam[0x1]; 339 u8 outer_geneve_protocol_type[0x1]; 340 u8 outer_geneve_opt_len[0x1]; 341 u8 reserved_at_1e[0x1]; 342 u8 source_eswitch_port[0x1]; 343 344 u8 inner_dmac[0x1]; 345 u8 inner_smac[0x1]; 346 u8 inner_ether_type[0x1]; 347 u8 inner_ip_version[0x1]; 348 u8 inner_first_prio[0x1]; 349 u8 inner_first_cfi[0x1]; 350 u8 inner_first_vid[0x1]; 351 u8 reserved_at_27[0x1]; 352 u8 inner_second_prio[0x1]; 353 u8 inner_second_cfi[0x1]; 354 u8 inner_second_vid[0x1]; 355 u8 reserved_at_2b[0x1]; 356 u8 inner_sip[0x1]; 357 u8 inner_dip[0x1]; 358 u8 inner_frag[0x1]; 359 u8 inner_ip_protocol[0x1]; 360 u8 inner_ip_ecn[0x1]; 361 u8 inner_ip_dscp[0x1]; 362 u8 inner_udp_sport[0x1]; 363 u8 inner_udp_dport[0x1]; 364 u8 inner_tcp_sport[0x1]; 365 u8 inner_tcp_dport[0x1]; 366 u8 inner_tcp_flags[0x1]; 367 u8 reserved_at_37[0x9]; 368 369 u8 geneve_tlv_option_0_data[0x1]; 370 u8 reserved_at_41[0x4]; 371 u8 outer_first_mpls_over_udp[0x4]; 372 u8 outer_first_mpls_over_gre[0x4]; 373 u8 inner_first_mpls[0x4]; 374 u8 outer_first_mpls[0x4]; 375 u8 reserved_at_55[0x2]; 376 u8 outer_esp_spi[0x1]; 377 u8 reserved_at_58[0x2]; 378 u8 bth_dst_qp[0x1]; 379 u8 reserved_at_5b[0x5]; 380 381 u8 reserved_at_60[0x18]; 382 u8 metadata_reg_c_7[0x1]; 383 u8 metadata_reg_c_6[0x1]; 384 u8 metadata_reg_c_5[0x1]; 385 u8 metadata_reg_c_4[0x1]; 386 u8 metadata_reg_c_3[0x1]; 387 u8 metadata_reg_c_2[0x1]; 388 u8 metadata_reg_c_1[0x1]; 389 u8 metadata_reg_c_0[0x1]; 390 }; 391 392 struct mlx5_ifc_flow_table_prop_layout_bits { 393 u8 ft_support[0x1]; 394 u8 reserved_at_1[0x1]; 395 u8 flow_counter[0x1]; 396 u8 flow_modify_en[0x1]; 397 u8 modify_root[0x1]; 398 u8 identified_miss_table_mode[0x1]; 399 u8 flow_table_modify[0x1]; 400 u8 reformat[0x1]; 401 u8 decap[0x1]; 402 u8 reserved_at_9[0x1]; 403 u8 pop_vlan[0x1]; 404 u8 push_vlan[0x1]; 405 u8 reserved_at_c[0x1]; 406 u8 pop_vlan_2[0x1]; 407 u8 push_vlan_2[0x1]; 408 u8 reformat_and_vlan_action[0x1]; 409 u8 reserved_at_10[0x1]; 410 u8 sw_owner[0x1]; 411 u8 reformat_l3_tunnel_to_l2[0x1]; 412 u8 reformat_l2_to_l3_tunnel[0x1]; 413 u8 reformat_and_modify_action[0x1]; 414 u8 ignore_flow_level[0x1]; 415 u8 reserved_at_16[0x1]; 416 u8 table_miss_action_domain[0x1]; 417 u8 termination_table[0x1]; 418 u8 reformat_and_fwd_to_table[0x1]; 419 u8 reserved_at_1a[0x6]; 420 u8 termination_table_raw_traffic[0x1]; 421 u8 reserved_at_21[0x1]; 422 u8 log_max_ft_size[0x6]; 423 u8 log_max_modify_header_context[0x8]; 424 u8 max_modify_header_actions[0x8]; 425 u8 max_ft_level[0x8]; 426 427 u8 reserved_at_40[0x20]; 428 429 u8 reserved_at_60[0x18]; 430 u8 log_max_ft_num[0x8]; 431 432 u8 reserved_at_80[0x18]; 433 u8 log_max_destination[0x8]; 434 435 u8 log_max_flow_counter[0x8]; 436 u8 reserved_at_a8[0x10]; 437 u8 log_max_flow[0x8]; 438 439 u8 reserved_at_c0[0x40]; 440 441 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 442 443 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 444 }; 445 446 struct mlx5_ifc_odp_per_transport_service_cap_bits { 447 u8 send[0x1]; 448 u8 receive[0x1]; 449 u8 write[0x1]; 450 u8 read[0x1]; 451 u8 atomic[0x1]; 452 u8 srq_receive[0x1]; 453 u8 reserved_at_6[0x1a]; 454 }; 455 456 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 457 u8 smac_47_16[0x20]; 458 459 u8 smac_15_0[0x10]; 460 u8 ethertype[0x10]; 461 462 u8 dmac_47_16[0x20]; 463 464 u8 dmac_15_0[0x10]; 465 u8 first_prio[0x3]; 466 u8 first_cfi[0x1]; 467 u8 first_vid[0xc]; 468 469 u8 ip_protocol[0x8]; 470 u8 ip_dscp[0x6]; 471 u8 ip_ecn[0x2]; 472 u8 cvlan_tag[0x1]; 473 u8 svlan_tag[0x1]; 474 u8 frag[0x1]; 475 u8 ip_version[0x4]; 476 u8 tcp_flags[0x9]; 477 478 u8 tcp_sport[0x10]; 479 u8 tcp_dport[0x10]; 480 481 u8 reserved_at_c0[0x18]; 482 u8 ttl_hoplimit[0x8]; 483 484 u8 udp_sport[0x10]; 485 u8 udp_dport[0x10]; 486 487 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 488 489 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 490 }; 491 492 struct mlx5_ifc_nvgre_key_bits { 493 u8 hi[0x18]; 494 u8 lo[0x8]; 495 }; 496 497 union mlx5_ifc_gre_key_bits { 498 struct mlx5_ifc_nvgre_key_bits nvgre; 499 u8 key[0x20]; 500 }; 501 502 struct mlx5_ifc_fte_match_set_misc_bits { 503 u8 gre_c_present[0x1]; 504 u8 reserved_at_1[0x1]; 505 u8 gre_k_present[0x1]; 506 u8 gre_s_present[0x1]; 507 u8 source_vhca_port[0x4]; 508 u8 source_sqn[0x18]; 509 510 u8 source_eswitch_owner_vhca_id[0x10]; 511 u8 source_port[0x10]; 512 513 u8 outer_second_prio[0x3]; 514 u8 outer_second_cfi[0x1]; 515 u8 outer_second_vid[0xc]; 516 u8 inner_second_prio[0x3]; 517 u8 inner_second_cfi[0x1]; 518 u8 inner_second_vid[0xc]; 519 520 u8 outer_second_cvlan_tag[0x1]; 521 u8 inner_second_cvlan_tag[0x1]; 522 u8 outer_second_svlan_tag[0x1]; 523 u8 inner_second_svlan_tag[0x1]; 524 u8 reserved_at_64[0xc]; 525 u8 gre_protocol[0x10]; 526 527 union mlx5_ifc_gre_key_bits gre_key; 528 529 u8 vxlan_vni[0x18]; 530 u8 reserved_at_b8[0x8]; 531 532 u8 geneve_vni[0x18]; 533 u8 reserved_at_d8[0x7]; 534 u8 geneve_oam[0x1]; 535 536 u8 reserved_at_e0[0xc]; 537 u8 outer_ipv6_flow_label[0x14]; 538 539 u8 reserved_at_100[0xc]; 540 u8 inner_ipv6_flow_label[0x14]; 541 542 u8 reserved_at_120[0xa]; 543 u8 geneve_opt_len[0x6]; 544 u8 geneve_protocol_type[0x10]; 545 546 u8 reserved_at_140[0x8]; 547 u8 bth_dst_qp[0x18]; 548 u8 reserved_at_160[0x20]; 549 u8 outer_esp_spi[0x20]; 550 u8 reserved_at_1a0[0x60]; 551 }; 552 553 struct mlx5_ifc_fte_match_mpls_bits { 554 u8 mpls_label[0x14]; 555 u8 mpls_exp[0x3]; 556 u8 mpls_s_bos[0x1]; 557 u8 mpls_ttl[0x8]; 558 }; 559 560 struct mlx5_ifc_fte_match_set_misc2_bits { 561 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 562 563 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 564 565 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 566 567 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 568 569 u8 metadata_reg_c_7[0x20]; 570 571 u8 metadata_reg_c_6[0x20]; 572 573 u8 metadata_reg_c_5[0x20]; 574 575 u8 metadata_reg_c_4[0x20]; 576 577 u8 metadata_reg_c_3[0x20]; 578 579 u8 metadata_reg_c_2[0x20]; 580 581 u8 metadata_reg_c_1[0x20]; 582 583 u8 metadata_reg_c_0[0x20]; 584 585 u8 metadata_reg_a[0x20]; 586 587 u8 reserved_at_1a0[0x60]; 588 }; 589 590 struct mlx5_ifc_fte_match_set_misc3_bits { 591 u8 inner_tcp_seq_num[0x20]; 592 593 u8 outer_tcp_seq_num[0x20]; 594 595 u8 inner_tcp_ack_num[0x20]; 596 597 u8 outer_tcp_ack_num[0x20]; 598 599 u8 reserved_at_80[0x8]; 600 u8 outer_vxlan_gpe_vni[0x18]; 601 602 u8 outer_vxlan_gpe_next_protocol[0x8]; 603 u8 outer_vxlan_gpe_flags[0x8]; 604 u8 reserved_at_b0[0x10]; 605 606 u8 icmp_header_data[0x20]; 607 608 u8 icmpv6_header_data[0x20]; 609 610 u8 icmp_type[0x8]; 611 u8 icmp_code[0x8]; 612 u8 icmpv6_type[0x8]; 613 u8 icmpv6_code[0x8]; 614 615 u8 geneve_tlv_option_0_data[0x20]; 616 617 u8 reserved_at_140[0xc0]; 618 }; 619 620 struct mlx5_ifc_cmd_pas_bits { 621 u8 pa_h[0x20]; 622 623 u8 pa_l[0x14]; 624 u8 reserved_at_34[0xc]; 625 }; 626 627 struct mlx5_ifc_uint64_bits { 628 u8 hi[0x20]; 629 630 u8 lo[0x20]; 631 }; 632 633 enum { 634 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 635 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 636 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 637 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 638 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 639 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 640 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 641 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 642 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 643 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 644 }; 645 646 struct mlx5_ifc_ads_bits { 647 u8 fl[0x1]; 648 u8 free_ar[0x1]; 649 u8 reserved_at_2[0xe]; 650 u8 pkey_index[0x10]; 651 652 u8 reserved_at_20[0x8]; 653 u8 grh[0x1]; 654 u8 mlid[0x7]; 655 u8 rlid[0x10]; 656 657 u8 ack_timeout[0x5]; 658 u8 reserved_at_45[0x3]; 659 u8 src_addr_index[0x8]; 660 u8 reserved_at_50[0x4]; 661 u8 stat_rate[0x4]; 662 u8 hop_limit[0x8]; 663 664 u8 reserved_at_60[0x4]; 665 u8 tclass[0x8]; 666 u8 flow_label[0x14]; 667 668 u8 rgid_rip[16][0x8]; 669 670 u8 reserved_at_100[0x4]; 671 u8 f_dscp[0x1]; 672 u8 f_ecn[0x1]; 673 u8 reserved_at_106[0x1]; 674 u8 f_eth_prio[0x1]; 675 u8 ecn[0x2]; 676 u8 dscp[0x6]; 677 u8 udp_sport[0x10]; 678 679 u8 dei_cfi[0x1]; 680 u8 eth_prio[0x3]; 681 u8 sl[0x4]; 682 u8 vhca_port_num[0x8]; 683 u8 rmac_47_32[0x10]; 684 685 u8 rmac_31_0[0x20]; 686 }; 687 688 struct mlx5_ifc_flow_table_nic_cap_bits { 689 u8 nic_rx_multi_path_tirs[0x1]; 690 u8 nic_rx_multi_path_tirs_fts[0x1]; 691 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 692 u8 reserved_at_3[0x4]; 693 u8 sw_owner_reformat_supported[0x1]; 694 u8 reserved_at_8[0x18]; 695 696 u8 encap_general_header[0x1]; 697 u8 reserved_at_21[0xa]; 698 u8 log_max_packet_reformat_context[0x5]; 699 u8 reserved_at_30[0x6]; 700 u8 max_encap_header_size[0xa]; 701 u8 reserved_at_40[0x1c0]; 702 703 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 704 705 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 706 707 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 708 709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 710 711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 712 713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 714 715 u8 reserved_at_e00[0x1200]; 716 717 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 718 719 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 720 721 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 722 723 u8 reserved_at_20c0[0x5f40]; 724 }; 725 726 enum { 727 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 728 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 729 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 730 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 731 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 732 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 733 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 734 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 735 }; 736 737 struct mlx5_ifc_flow_table_eswitch_cap_bits { 738 u8 fdb_to_vport_reg_c_id[0x8]; 739 u8 reserved_at_8[0xd]; 740 u8 fdb_modify_header_fwd_to_table[0x1]; 741 u8 reserved_at_16[0x1]; 742 u8 flow_source[0x1]; 743 u8 reserved_at_18[0x2]; 744 u8 multi_fdb_encap[0x1]; 745 u8 egress_acl_forward_to_vport[0x1]; 746 u8 fdb_multi_path_to_table[0x1]; 747 u8 reserved_at_1d[0x3]; 748 749 u8 reserved_at_20[0x1e0]; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 756 757 u8 reserved_at_800[0x1000]; 758 759 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 760 761 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 762 763 u8 sw_steering_uplink_icm_address_rx[0x40]; 764 765 u8 sw_steering_uplink_icm_address_tx[0x40]; 766 767 u8 reserved_at_1900[0x6700]; 768 }; 769 770 enum { 771 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 772 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 773 }; 774 775 struct mlx5_ifc_e_switch_cap_bits { 776 u8 vport_svlan_strip[0x1]; 777 u8 vport_cvlan_strip[0x1]; 778 u8 vport_svlan_insert[0x1]; 779 u8 vport_cvlan_insert_if_not_exist[0x1]; 780 u8 vport_cvlan_insert_overwrite[0x1]; 781 u8 reserved_at_5[0x3]; 782 u8 esw_uplink_ingress_acl[0x1]; 783 u8 reserved_at_9[0x10]; 784 u8 esw_functions_changed[0x1]; 785 u8 reserved_at_1a[0x1]; 786 u8 ecpf_vport_exists[0x1]; 787 u8 counter_eswitch_affinity[0x1]; 788 u8 merged_eswitch[0x1]; 789 u8 nic_vport_node_guid_modify[0x1]; 790 u8 nic_vport_port_guid_modify[0x1]; 791 792 u8 vxlan_encap_decap[0x1]; 793 u8 nvgre_encap_decap[0x1]; 794 u8 reserved_at_22[0x1]; 795 u8 log_max_fdb_encap_uplink[0x5]; 796 u8 reserved_at_21[0x3]; 797 u8 log_max_packet_reformat_context[0x5]; 798 u8 reserved_2b[0x6]; 799 u8 max_encap_header_size[0xa]; 800 801 u8 reserved_at_40[0xb]; 802 u8 log_max_esw_sf[0x5]; 803 u8 esw_sf_base_id[0x10]; 804 805 u8 reserved_at_60[0x7a0]; 806 807 }; 808 809 struct mlx5_ifc_qos_cap_bits { 810 u8 packet_pacing[0x1]; 811 u8 esw_scheduling[0x1]; 812 u8 esw_bw_share[0x1]; 813 u8 esw_rate_limit[0x1]; 814 u8 reserved_at_4[0x1]; 815 u8 packet_pacing_burst_bound[0x1]; 816 u8 packet_pacing_typical_size[0x1]; 817 u8 reserved_at_7[0x4]; 818 u8 packet_pacing_uid[0x1]; 819 u8 reserved_at_c[0x14]; 820 821 u8 reserved_at_20[0x20]; 822 823 u8 packet_pacing_max_rate[0x20]; 824 825 u8 packet_pacing_min_rate[0x20]; 826 827 u8 reserved_at_80[0x10]; 828 u8 packet_pacing_rate_table_size[0x10]; 829 830 u8 esw_element_type[0x10]; 831 u8 esw_tsar_type[0x10]; 832 833 u8 reserved_at_c0[0x10]; 834 u8 max_qos_para_vport[0x10]; 835 836 u8 max_tsar_bw_share[0x20]; 837 838 u8 reserved_at_100[0x700]; 839 }; 840 841 struct mlx5_ifc_debug_cap_bits { 842 u8 core_dump_general[0x1]; 843 u8 core_dump_qp[0x1]; 844 u8 reserved_at_2[0x7]; 845 u8 resource_dump[0x1]; 846 u8 reserved_at_a[0x16]; 847 848 u8 reserved_at_20[0x2]; 849 u8 stall_detect[0x1]; 850 u8 reserved_at_23[0x1d]; 851 852 u8 reserved_at_40[0x7c0]; 853 }; 854 855 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 856 u8 csum_cap[0x1]; 857 u8 vlan_cap[0x1]; 858 u8 lro_cap[0x1]; 859 u8 lro_psh_flag[0x1]; 860 u8 lro_time_stamp[0x1]; 861 u8 reserved_at_5[0x2]; 862 u8 wqe_vlan_insert[0x1]; 863 u8 self_lb_en_modifiable[0x1]; 864 u8 reserved_at_9[0x2]; 865 u8 max_lso_cap[0x5]; 866 u8 multi_pkt_send_wqe[0x2]; 867 u8 wqe_inline_mode[0x2]; 868 u8 rss_ind_tbl_cap[0x4]; 869 u8 reg_umr_sq[0x1]; 870 u8 scatter_fcs[0x1]; 871 u8 enhanced_multi_pkt_send_wqe[0x1]; 872 u8 tunnel_lso_const_out_ip_id[0x1]; 873 u8 reserved_at_1c[0x2]; 874 u8 tunnel_stateless_gre[0x1]; 875 u8 tunnel_stateless_vxlan[0x1]; 876 877 u8 swp[0x1]; 878 u8 swp_csum[0x1]; 879 u8 swp_lso[0x1]; 880 u8 cqe_checksum_full[0x1]; 881 u8 tunnel_stateless_geneve_tx[0x1]; 882 u8 tunnel_stateless_mpls_over_udp[0x1]; 883 u8 tunnel_stateless_mpls_over_gre[0x1]; 884 u8 tunnel_stateless_vxlan_gpe[0x1]; 885 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 886 u8 tunnel_stateless_ip_over_ip[0x1]; 887 u8 insert_trailer[0x1]; 888 u8 reserved_at_2b[0x5]; 889 u8 max_vxlan_udp_ports[0x8]; 890 u8 reserved_at_38[0x6]; 891 u8 max_geneve_opt_len[0x1]; 892 u8 tunnel_stateless_geneve_rx[0x1]; 893 894 u8 reserved_at_40[0x10]; 895 u8 lro_min_mss_size[0x10]; 896 897 u8 reserved_at_60[0x120]; 898 899 u8 lro_timer_supported_periods[4][0x20]; 900 901 u8 reserved_at_200[0x600]; 902 }; 903 904 struct mlx5_ifc_roce_cap_bits { 905 u8 roce_apm[0x1]; 906 u8 reserved_at_1[0x3]; 907 u8 sw_r_roce_src_udp_port[0x1]; 908 u8 reserved_at_5[0x1b]; 909 910 u8 reserved_at_20[0x60]; 911 912 u8 reserved_at_80[0xc]; 913 u8 l3_type[0x4]; 914 u8 reserved_at_90[0x8]; 915 u8 roce_version[0x8]; 916 917 u8 reserved_at_a0[0x10]; 918 u8 r_roce_dest_udp_port[0x10]; 919 920 u8 r_roce_max_src_udp_port[0x10]; 921 u8 r_roce_min_src_udp_port[0x10]; 922 923 u8 reserved_at_e0[0x10]; 924 u8 roce_address_table_size[0x10]; 925 926 u8 reserved_at_100[0x700]; 927 }; 928 929 struct mlx5_ifc_sync_steering_in_bits { 930 u8 opcode[0x10]; 931 u8 uid[0x10]; 932 933 u8 reserved_at_20[0x10]; 934 u8 op_mod[0x10]; 935 936 u8 reserved_at_40[0xc0]; 937 }; 938 939 struct mlx5_ifc_sync_steering_out_bits { 940 u8 status[0x8]; 941 u8 reserved_at_8[0x18]; 942 943 u8 syndrome[0x20]; 944 945 u8 reserved_at_40[0x40]; 946 }; 947 948 struct mlx5_ifc_device_mem_cap_bits { 949 u8 memic[0x1]; 950 u8 reserved_at_1[0x1f]; 951 952 u8 reserved_at_20[0xb]; 953 u8 log_min_memic_alloc_size[0x5]; 954 u8 reserved_at_30[0x8]; 955 u8 log_max_memic_addr_alignment[0x8]; 956 957 u8 memic_bar_start_addr[0x40]; 958 959 u8 memic_bar_size[0x20]; 960 961 u8 max_memic_size[0x20]; 962 963 u8 steering_sw_icm_start_address[0x40]; 964 965 u8 reserved_at_100[0x8]; 966 u8 log_header_modify_sw_icm_size[0x8]; 967 u8 reserved_at_110[0x2]; 968 u8 log_sw_icm_alloc_granularity[0x6]; 969 u8 log_steering_sw_icm_size[0x8]; 970 971 u8 reserved_at_120[0x20]; 972 973 u8 header_modify_sw_icm_start_address[0x40]; 974 975 u8 reserved_at_180[0x680]; 976 }; 977 978 struct mlx5_ifc_device_event_cap_bits { 979 u8 user_affiliated_events[4][0x40]; 980 981 u8 user_unaffiliated_events[4][0x40]; 982 }; 983 984 struct mlx5_ifc_device_virtio_emulation_cap_bits { 985 u8 reserved_at_0[0x20]; 986 987 u8 reserved_at_20[0x13]; 988 u8 log_doorbell_stride[0x5]; 989 u8 reserved_at_38[0x3]; 990 u8 log_doorbell_bar_size[0x5]; 991 992 u8 doorbell_bar_offset[0x40]; 993 994 u8 reserved_at_80[0x780]; 995 }; 996 997 enum { 998 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 999 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1000 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1001 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1007 }; 1008 1009 enum { 1010 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1011 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1012 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1013 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1014 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1015 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1016 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1017 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1018 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1019 }; 1020 1021 struct mlx5_ifc_atomic_caps_bits { 1022 u8 reserved_at_0[0x40]; 1023 1024 u8 atomic_req_8B_endianness_mode[0x2]; 1025 u8 reserved_at_42[0x4]; 1026 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1027 1028 u8 reserved_at_47[0x19]; 1029 1030 u8 reserved_at_60[0x20]; 1031 1032 u8 reserved_at_80[0x10]; 1033 u8 atomic_operations[0x10]; 1034 1035 u8 reserved_at_a0[0x10]; 1036 u8 atomic_size_qp[0x10]; 1037 1038 u8 reserved_at_c0[0x10]; 1039 u8 atomic_size_dc[0x10]; 1040 1041 u8 reserved_at_e0[0x720]; 1042 }; 1043 1044 struct mlx5_ifc_odp_cap_bits { 1045 u8 reserved_at_0[0x40]; 1046 1047 u8 sig[0x1]; 1048 u8 reserved_at_41[0x1f]; 1049 1050 u8 reserved_at_60[0x20]; 1051 1052 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1053 1054 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1055 1056 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1057 1058 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1059 1060 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1061 1062 u8 reserved_at_120[0x6E0]; 1063 }; 1064 1065 struct mlx5_ifc_calc_op { 1066 u8 reserved_at_0[0x10]; 1067 u8 reserved_at_10[0x9]; 1068 u8 op_swap_endianness[0x1]; 1069 u8 op_min[0x1]; 1070 u8 op_xor[0x1]; 1071 u8 op_or[0x1]; 1072 u8 op_and[0x1]; 1073 u8 op_max[0x1]; 1074 u8 op_add[0x1]; 1075 }; 1076 1077 struct mlx5_ifc_vector_calc_cap_bits { 1078 u8 calc_matrix[0x1]; 1079 u8 reserved_at_1[0x1f]; 1080 u8 reserved_at_20[0x8]; 1081 u8 max_vec_count[0x8]; 1082 u8 reserved_at_30[0xd]; 1083 u8 max_chunk_size[0x3]; 1084 struct mlx5_ifc_calc_op calc0; 1085 struct mlx5_ifc_calc_op calc1; 1086 struct mlx5_ifc_calc_op calc2; 1087 struct mlx5_ifc_calc_op calc3; 1088 1089 u8 reserved_at_c0[0x720]; 1090 }; 1091 1092 struct mlx5_ifc_tls_cap_bits { 1093 u8 tls_1_2_aes_gcm_128[0x1]; 1094 u8 tls_1_3_aes_gcm_128[0x1]; 1095 u8 tls_1_2_aes_gcm_256[0x1]; 1096 u8 tls_1_3_aes_gcm_256[0x1]; 1097 u8 reserved_at_4[0x1c]; 1098 1099 u8 reserved_at_20[0x7e0]; 1100 }; 1101 1102 struct mlx5_ifc_ipsec_cap_bits { 1103 u8 ipsec_full_offload[0x1]; 1104 u8 ipsec_crypto_offload[0x1]; 1105 u8 ipsec_esn[0x1]; 1106 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1107 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1108 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1109 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1110 u8 reserved_at_7[0x4]; 1111 u8 log_max_ipsec_offload[0x5]; 1112 u8 reserved_at_10[0x10]; 1113 1114 u8 min_log_ipsec_full_replay_window[0x8]; 1115 u8 max_log_ipsec_full_replay_window[0x8]; 1116 u8 reserved_at_30[0x7d0]; 1117 }; 1118 1119 enum { 1120 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1121 MLX5_WQ_TYPE_CYCLIC = 0x1, 1122 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1123 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1124 }; 1125 1126 enum { 1127 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1128 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1129 }; 1130 1131 enum { 1132 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1133 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1134 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1135 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1136 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1137 }; 1138 1139 enum { 1140 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1141 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1142 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1143 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1144 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1145 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1146 }; 1147 1148 enum { 1149 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1150 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1151 }; 1152 1153 enum { 1154 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1155 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1156 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1157 }; 1158 1159 enum { 1160 MLX5_CAP_PORT_TYPE_IB = 0x0, 1161 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1162 }; 1163 1164 enum { 1165 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1166 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1167 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1168 }; 1169 1170 enum { 1171 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1172 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1173 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1174 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1175 }; 1176 1177 enum { 1178 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1179 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1180 }; 1181 1182 #define MLX5_FC_BULK_SIZE_FACTOR 128 1183 1184 enum mlx5_fc_bulk_alloc_bitmask { 1185 MLX5_FC_BULK_128 = (1 << 0), 1186 MLX5_FC_BULK_256 = (1 << 1), 1187 MLX5_FC_BULK_512 = (1 << 2), 1188 MLX5_FC_BULK_1024 = (1 << 3), 1189 MLX5_FC_BULK_2048 = (1 << 4), 1190 MLX5_FC_BULK_4096 = (1 << 5), 1191 MLX5_FC_BULK_8192 = (1 << 6), 1192 MLX5_FC_BULK_16384 = (1 << 7), 1193 }; 1194 1195 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1196 1197 struct mlx5_ifc_cmd_hca_cap_bits { 1198 u8 reserved_at_0[0x30]; 1199 u8 vhca_id[0x10]; 1200 1201 u8 reserved_at_40[0x40]; 1202 1203 u8 log_max_srq_sz[0x8]; 1204 u8 log_max_qp_sz[0x8]; 1205 u8 event_cap[0x1]; 1206 u8 reserved_at_91[0x7]; 1207 u8 prio_tag_required[0x1]; 1208 u8 reserved_at_99[0x2]; 1209 u8 log_max_qp[0x5]; 1210 1211 u8 reserved_at_a0[0x3]; 1212 u8 ece_support[0x1]; 1213 u8 reserved_at_a4[0x7]; 1214 u8 log_max_srq[0x5]; 1215 u8 reserved_at_b0[0x10]; 1216 1217 u8 max_sgl_for_optimized_performance[0x8]; 1218 u8 log_max_cq_sz[0x8]; 1219 u8 reserved_at_d0[0xb]; 1220 u8 log_max_cq[0x5]; 1221 1222 u8 log_max_eq_sz[0x8]; 1223 u8 relaxed_ordering_write[0x1]; 1224 u8 relaxed_ordering_read[0x1]; 1225 u8 log_max_mkey[0x6]; 1226 u8 reserved_at_f0[0x8]; 1227 u8 dump_fill_mkey[0x1]; 1228 u8 reserved_at_f9[0x2]; 1229 u8 fast_teardown[0x1]; 1230 u8 log_max_eq[0x4]; 1231 1232 u8 max_indirection[0x8]; 1233 u8 fixed_buffer_size[0x1]; 1234 u8 log_max_mrw_sz[0x7]; 1235 u8 force_teardown[0x1]; 1236 u8 reserved_at_111[0x1]; 1237 u8 log_max_bsf_list_size[0x6]; 1238 u8 umr_extended_translation_offset[0x1]; 1239 u8 null_mkey[0x1]; 1240 u8 log_max_klm_list_size[0x6]; 1241 1242 u8 reserved_at_120[0xa]; 1243 u8 log_max_ra_req_dc[0x6]; 1244 u8 reserved_at_130[0xa]; 1245 u8 log_max_ra_res_dc[0x6]; 1246 1247 u8 reserved_at_140[0x6]; 1248 u8 release_all_pages[0x1]; 1249 u8 reserved_at_147[0x2]; 1250 u8 roce_accl[0x1]; 1251 u8 log_max_ra_req_qp[0x6]; 1252 u8 reserved_at_150[0xa]; 1253 u8 log_max_ra_res_qp[0x6]; 1254 1255 u8 end_pad[0x1]; 1256 u8 cc_query_allowed[0x1]; 1257 u8 cc_modify_allowed[0x1]; 1258 u8 start_pad[0x1]; 1259 u8 cache_line_128byte[0x1]; 1260 u8 reserved_at_165[0x4]; 1261 u8 rts2rts_qp_counters_set_id[0x1]; 1262 u8 reserved_at_16a[0x2]; 1263 u8 vnic_env_int_rq_oob[0x1]; 1264 u8 sbcam_reg[0x1]; 1265 u8 reserved_at_16e[0x1]; 1266 u8 qcam_reg[0x1]; 1267 u8 gid_table_size[0x10]; 1268 1269 u8 out_of_seq_cnt[0x1]; 1270 u8 vport_counters[0x1]; 1271 u8 retransmission_q_counters[0x1]; 1272 u8 debug[0x1]; 1273 u8 modify_rq_counter_set_id[0x1]; 1274 u8 rq_delay_drop[0x1]; 1275 u8 max_qp_cnt[0xa]; 1276 u8 pkey_table_size[0x10]; 1277 1278 u8 vport_group_manager[0x1]; 1279 u8 vhca_group_manager[0x1]; 1280 u8 ib_virt[0x1]; 1281 u8 eth_virt[0x1]; 1282 u8 vnic_env_queue_counters[0x1]; 1283 u8 ets[0x1]; 1284 u8 nic_flow_table[0x1]; 1285 u8 eswitch_manager[0x1]; 1286 u8 device_memory[0x1]; 1287 u8 mcam_reg[0x1]; 1288 u8 pcam_reg[0x1]; 1289 u8 local_ca_ack_delay[0x5]; 1290 u8 port_module_event[0x1]; 1291 u8 enhanced_error_q_counters[0x1]; 1292 u8 ports_check[0x1]; 1293 u8 reserved_at_1b3[0x1]; 1294 u8 disable_link_up[0x1]; 1295 u8 beacon_led[0x1]; 1296 u8 port_type[0x2]; 1297 u8 num_ports[0x8]; 1298 1299 u8 reserved_at_1c0[0x1]; 1300 u8 pps[0x1]; 1301 u8 pps_modify[0x1]; 1302 u8 log_max_msg[0x5]; 1303 u8 reserved_at_1c8[0x4]; 1304 u8 max_tc[0x4]; 1305 u8 temp_warn_event[0x1]; 1306 u8 dcbx[0x1]; 1307 u8 general_notification_event[0x1]; 1308 u8 reserved_at_1d3[0x2]; 1309 u8 fpga[0x1]; 1310 u8 rol_s[0x1]; 1311 u8 rol_g[0x1]; 1312 u8 reserved_at_1d8[0x1]; 1313 u8 wol_s[0x1]; 1314 u8 wol_g[0x1]; 1315 u8 wol_a[0x1]; 1316 u8 wol_b[0x1]; 1317 u8 wol_m[0x1]; 1318 u8 wol_u[0x1]; 1319 u8 wol_p[0x1]; 1320 1321 u8 stat_rate_support[0x10]; 1322 u8 reserved_at_1f0[0x1]; 1323 u8 pci_sync_for_fw_update_event[0x1]; 1324 u8 reserved_at_1f2[0x6]; 1325 u8 init2_lag_tx_port_affinity[0x1]; 1326 u8 reserved_at_1fa[0x3]; 1327 u8 cqe_version[0x4]; 1328 1329 u8 compact_address_vector[0x1]; 1330 u8 striding_rq[0x1]; 1331 u8 reserved_at_202[0x1]; 1332 u8 ipoib_enhanced_offloads[0x1]; 1333 u8 ipoib_basic_offloads[0x1]; 1334 u8 reserved_at_205[0x1]; 1335 u8 repeated_block_disabled[0x1]; 1336 u8 umr_modify_entity_size_disabled[0x1]; 1337 u8 umr_modify_atomic_disabled[0x1]; 1338 u8 umr_indirect_mkey_disabled[0x1]; 1339 u8 umr_fence[0x2]; 1340 u8 dc_req_scat_data_cqe[0x1]; 1341 u8 reserved_at_20d[0x2]; 1342 u8 drain_sigerr[0x1]; 1343 u8 cmdif_checksum[0x2]; 1344 u8 sigerr_cqe[0x1]; 1345 u8 reserved_at_213[0x1]; 1346 u8 wq_signature[0x1]; 1347 u8 sctr_data_cqe[0x1]; 1348 u8 reserved_at_216[0x1]; 1349 u8 sho[0x1]; 1350 u8 tph[0x1]; 1351 u8 rf[0x1]; 1352 u8 dct[0x1]; 1353 u8 qos[0x1]; 1354 u8 eth_net_offloads[0x1]; 1355 u8 roce[0x1]; 1356 u8 atomic[0x1]; 1357 u8 reserved_at_21f[0x1]; 1358 1359 u8 cq_oi[0x1]; 1360 u8 cq_resize[0x1]; 1361 u8 cq_moderation[0x1]; 1362 u8 reserved_at_223[0x3]; 1363 u8 cq_eq_remap[0x1]; 1364 u8 pg[0x1]; 1365 u8 block_lb_mc[0x1]; 1366 u8 reserved_at_229[0x1]; 1367 u8 scqe_break_moderation[0x1]; 1368 u8 cq_period_start_from_cqe[0x1]; 1369 u8 cd[0x1]; 1370 u8 reserved_at_22d[0x1]; 1371 u8 apm[0x1]; 1372 u8 vector_calc[0x1]; 1373 u8 umr_ptr_rlky[0x1]; 1374 u8 imaicl[0x1]; 1375 u8 qp_packet_based[0x1]; 1376 u8 reserved_at_233[0x3]; 1377 u8 qkv[0x1]; 1378 u8 pkv[0x1]; 1379 u8 set_deth_sqpn[0x1]; 1380 u8 reserved_at_239[0x3]; 1381 u8 xrc[0x1]; 1382 u8 ud[0x1]; 1383 u8 uc[0x1]; 1384 u8 rc[0x1]; 1385 1386 u8 uar_4k[0x1]; 1387 u8 reserved_at_241[0x9]; 1388 u8 uar_sz[0x6]; 1389 u8 reserved_at_250[0x8]; 1390 u8 log_pg_sz[0x8]; 1391 1392 u8 bf[0x1]; 1393 u8 driver_version[0x1]; 1394 u8 pad_tx_eth_packet[0x1]; 1395 u8 reserved_at_263[0x8]; 1396 u8 log_bf_reg_size[0x5]; 1397 1398 u8 reserved_at_270[0x8]; 1399 u8 lag_tx_port_affinity[0x1]; 1400 u8 reserved_at_279[0x2]; 1401 u8 lag_master[0x1]; 1402 u8 num_lag_ports[0x4]; 1403 1404 u8 reserved_at_280[0x10]; 1405 u8 max_wqe_sz_sq[0x10]; 1406 1407 u8 reserved_at_2a0[0x10]; 1408 u8 max_wqe_sz_rq[0x10]; 1409 1410 u8 max_flow_counter_31_16[0x10]; 1411 u8 max_wqe_sz_sq_dc[0x10]; 1412 1413 u8 reserved_at_2e0[0x7]; 1414 u8 max_qp_mcg[0x19]; 1415 1416 u8 reserved_at_300[0x10]; 1417 u8 flow_counter_bulk_alloc[0x8]; 1418 u8 log_max_mcg[0x8]; 1419 1420 u8 reserved_at_320[0x3]; 1421 u8 log_max_transport_domain[0x5]; 1422 u8 reserved_at_328[0x3]; 1423 u8 log_max_pd[0x5]; 1424 u8 reserved_at_330[0xb]; 1425 u8 log_max_xrcd[0x5]; 1426 1427 u8 nic_receive_steering_discard[0x1]; 1428 u8 receive_discard_vport_down[0x1]; 1429 u8 transmit_discard_vport_down[0x1]; 1430 u8 reserved_at_343[0x5]; 1431 u8 log_max_flow_counter_bulk[0x8]; 1432 u8 max_flow_counter_15_0[0x10]; 1433 1434 1435 u8 reserved_at_360[0x3]; 1436 u8 log_max_rq[0x5]; 1437 u8 reserved_at_368[0x3]; 1438 u8 log_max_sq[0x5]; 1439 u8 reserved_at_370[0x3]; 1440 u8 log_max_tir[0x5]; 1441 u8 reserved_at_378[0x3]; 1442 u8 log_max_tis[0x5]; 1443 1444 u8 basic_cyclic_rcv_wqe[0x1]; 1445 u8 reserved_at_381[0x2]; 1446 u8 log_max_rmp[0x5]; 1447 u8 reserved_at_388[0x3]; 1448 u8 log_max_rqt[0x5]; 1449 u8 reserved_at_390[0x3]; 1450 u8 log_max_rqt_size[0x5]; 1451 u8 reserved_at_398[0x3]; 1452 u8 log_max_tis_per_sq[0x5]; 1453 1454 u8 ext_stride_num_range[0x1]; 1455 u8 reserved_at_3a1[0x2]; 1456 u8 log_max_stride_sz_rq[0x5]; 1457 u8 reserved_at_3a8[0x3]; 1458 u8 log_min_stride_sz_rq[0x5]; 1459 u8 reserved_at_3b0[0x3]; 1460 u8 log_max_stride_sz_sq[0x5]; 1461 u8 reserved_at_3b8[0x3]; 1462 u8 log_min_stride_sz_sq[0x5]; 1463 1464 u8 hairpin[0x1]; 1465 u8 reserved_at_3c1[0x2]; 1466 u8 log_max_hairpin_queues[0x5]; 1467 u8 reserved_at_3c8[0x3]; 1468 u8 log_max_hairpin_wq_data_sz[0x5]; 1469 u8 reserved_at_3d0[0x3]; 1470 u8 log_max_hairpin_num_packets[0x5]; 1471 u8 reserved_at_3d8[0x3]; 1472 u8 log_max_wq_sz[0x5]; 1473 1474 u8 nic_vport_change_event[0x1]; 1475 u8 disable_local_lb_uc[0x1]; 1476 u8 disable_local_lb_mc[0x1]; 1477 u8 log_min_hairpin_wq_data_sz[0x5]; 1478 u8 reserved_at_3e8[0x3]; 1479 u8 log_max_vlan_list[0x5]; 1480 u8 reserved_at_3f0[0x3]; 1481 u8 log_max_current_mc_list[0x5]; 1482 u8 reserved_at_3f8[0x3]; 1483 u8 log_max_current_uc_list[0x5]; 1484 1485 u8 general_obj_types[0x40]; 1486 1487 u8 reserved_at_440[0x20]; 1488 1489 u8 reserved_at_460[0x3]; 1490 u8 log_max_uctx[0x5]; 1491 u8 reserved_at_468[0x2]; 1492 u8 ipsec_offload[0x1]; 1493 u8 log_max_umem[0x5]; 1494 u8 max_num_eqs[0x10]; 1495 1496 u8 reserved_at_480[0x1]; 1497 u8 tls_tx[0x1]; 1498 u8 tls_rx[0x1]; 1499 u8 log_max_l2_table[0x5]; 1500 u8 reserved_at_488[0x8]; 1501 u8 log_uar_page_sz[0x10]; 1502 1503 u8 reserved_at_4a0[0x20]; 1504 u8 device_frequency_mhz[0x20]; 1505 u8 device_frequency_khz[0x20]; 1506 1507 u8 reserved_at_500[0x20]; 1508 u8 num_of_uars_per_page[0x20]; 1509 1510 u8 flex_parser_protocols[0x20]; 1511 1512 u8 max_geneve_tlv_options[0x8]; 1513 u8 reserved_at_568[0x3]; 1514 u8 max_geneve_tlv_option_data_len[0x5]; 1515 u8 reserved_at_570[0x10]; 1516 1517 u8 reserved_at_580[0x33]; 1518 u8 log_max_dek[0x5]; 1519 u8 reserved_at_5b8[0x4]; 1520 u8 mini_cqe_resp_stride_index[0x1]; 1521 u8 cqe_128_always[0x1]; 1522 u8 cqe_compression_128[0x1]; 1523 u8 cqe_compression[0x1]; 1524 1525 u8 cqe_compression_timeout[0x10]; 1526 u8 cqe_compression_max_num[0x10]; 1527 1528 u8 reserved_at_5e0[0x10]; 1529 u8 tag_matching[0x1]; 1530 u8 rndv_offload_rc[0x1]; 1531 u8 rndv_offload_dc[0x1]; 1532 u8 log_tag_matching_list_sz[0x5]; 1533 u8 reserved_at_5f8[0x3]; 1534 u8 log_max_xrq[0x5]; 1535 1536 u8 affiliate_nic_vport_criteria[0x8]; 1537 u8 native_port_num[0x8]; 1538 u8 num_vhca_ports[0x8]; 1539 u8 reserved_at_618[0x6]; 1540 u8 sw_owner_id[0x1]; 1541 u8 reserved_at_61f[0x1]; 1542 1543 u8 max_num_of_monitor_counters[0x10]; 1544 u8 num_ppcnt_monitor_counters[0x10]; 1545 1546 u8 reserved_at_640[0x10]; 1547 u8 num_q_monitor_counters[0x10]; 1548 1549 u8 reserved_at_660[0x20]; 1550 1551 u8 sf[0x1]; 1552 u8 sf_set_partition[0x1]; 1553 u8 reserved_at_682[0x1]; 1554 u8 log_max_sf[0x5]; 1555 u8 reserved_at_688[0x8]; 1556 u8 log_min_sf_size[0x8]; 1557 u8 max_num_sf_partitions[0x8]; 1558 1559 u8 uctx_cap[0x20]; 1560 1561 u8 reserved_at_6c0[0x4]; 1562 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1563 u8 flex_parser_id_icmp_dw1[0x4]; 1564 u8 flex_parser_id_icmp_dw0[0x4]; 1565 u8 flex_parser_id_icmpv6_dw1[0x4]; 1566 u8 flex_parser_id_icmpv6_dw0[0x4]; 1567 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1568 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1569 1570 u8 reserved_at_6e0[0x10]; 1571 u8 sf_base_id[0x10]; 1572 1573 u8 reserved_at_700[0x80]; 1574 u8 vhca_tunnel_commands[0x40]; 1575 u8 reserved_at_7c0[0x40]; 1576 }; 1577 1578 enum mlx5_flow_destination_type { 1579 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1580 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1581 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1582 1583 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1584 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1585 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1586 }; 1587 1588 enum mlx5_flow_table_miss_action { 1589 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1590 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1591 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1592 }; 1593 1594 struct mlx5_ifc_dest_format_struct_bits { 1595 u8 destination_type[0x8]; 1596 u8 destination_id[0x18]; 1597 1598 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1599 u8 packet_reformat[0x1]; 1600 u8 reserved_at_22[0xe]; 1601 u8 destination_eswitch_owner_vhca_id[0x10]; 1602 }; 1603 1604 struct mlx5_ifc_flow_counter_list_bits { 1605 u8 flow_counter_id[0x20]; 1606 1607 u8 reserved_at_20[0x20]; 1608 }; 1609 1610 struct mlx5_ifc_extended_dest_format_bits { 1611 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1612 1613 u8 packet_reformat_id[0x20]; 1614 1615 u8 reserved_at_60[0x20]; 1616 }; 1617 1618 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1619 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1620 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1621 }; 1622 1623 struct mlx5_ifc_fte_match_param_bits { 1624 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1625 1626 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1627 1628 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1629 1630 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1631 1632 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1633 1634 u8 reserved_at_a00[0x600]; 1635 }; 1636 1637 enum { 1638 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1639 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1640 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1641 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1642 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1643 }; 1644 1645 struct mlx5_ifc_rx_hash_field_select_bits { 1646 u8 l3_prot_type[0x1]; 1647 u8 l4_prot_type[0x1]; 1648 u8 selected_fields[0x1e]; 1649 }; 1650 1651 enum { 1652 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1653 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1654 }; 1655 1656 enum { 1657 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1658 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1659 }; 1660 1661 struct mlx5_ifc_wq_bits { 1662 u8 wq_type[0x4]; 1663 u8 wq_signature[0x1]; 1664 u8 end_padding_mode[0x2]; 1665 u8 cd_slave[0x1]; 1666 u8 reserved_at_8[0x18]; 1667 1668 u8 hds_skip_first_sge[0x1]; 1669 u8 log2_hds_buf_size[0x3]; 1670 u8 reserved_at_24[0x7]; 1671 u8 page_offset[0x5]; 1672 u8 lwm[0x10]; 1673 1674 u8 reserved_at_40[0x8]; 1675 u8 pd[0x18]; 1676 1677 u8 reserved_at_60[0x8]; 1678 u8 uar_page[0x18]; 1679 1680 u8 dbr_addr[0x40]; 1681 1682 u8 hw_counter[0x20]; 1683 1684 u8 sw_counter[0x20]; 1685 1686 u8 reserved_at_100[0xc]; 1687 u8 log_wq_stride[0x4]; 1688 u8 reserved_at_110[0x3]; 1689 u8 log_wq_pg_sz[0x5]; 1690 u8 reserved_at_118[0x3]; 1691 u8 log_wq_sz[0x5]; 1692 1693 u8 dbr_umem_valid[0x1]; 1694 u8 wq_umem_valid[0x1]; 1695 u8 reserved_at_122[0x1]; 1696 u8 log_hairpin_num_packets[0x5]; 1697 u8 reserved_at_128[0x3]; 1698 u8 log_hairpin_data_sz[0x5]; 1699 1700 u8 reserved_at_130[0x4]; 1701 u8 log_wqe_num_of_strides[0x4]; 1702 u8 two_byte_shift_en[0x1]; 1703 u8 reserved_at_139[0x4]; 1704 u8 log_wqe_stride_size[0x3]; 1705 1706 u8 reserved_at_140[0x4c0]; 1707 1708 struct mlx5_ifc_cmd_pas_bits pas[]; 1709 }; 1710 1711 struct mlx5_ifc_rq_num_bits { 1712 u8 reserved_at_0[0x8]; 1713 u8 rq_num[0x18]; 1714 }; 1715 1716 struct mlx5_ifc_mac_address_layout_bits { 1717 u8 reserved_at_0[0x10]; 1718 u8 mac_addr_47_32[0x10]; 1719 1720 u8 mac_addr_31_0[0x20]; 1721 }; 1722 1723 struct mlx5_ifc_vlan_layout_bits { 1724 u8 reserved_at_0[0x14]; 1725 u8 vlan[0x0c]; 1726 1727 u8 reserved_at_20[0x20]; 1728 }; 1729 1730 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1731 u8 reserved_at_0[0xa0]; 1732 1733 u8 min_time_between_cnps[0x20]; 1734 1735 u8 reserved_at_c0[0x12]; 1736 u8 cnp_dscp[0x6]; 1737 u8 reserved_at_d8[0x4]; 1738 u8 cnp_prio_mode[0x1]; 1739 u8 cnp_802p_prio[0x3]; 1740 1741 u8 reserved_at_e0[0x720]; 1742 }; 1743 1744 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1745 u8 reserved_at_0[0x60]; 1746 1747 u8 reserved_at_60[0x4]; 1748 u8 clamp_tgt_rate[0x1]; 1749 u8 reserved_at_65[0x3]; 1750 u8 clamp_tgt_rate_after_time_inc[0x1]; 1751 u8 reserved_at_69[0x17]; 1752 1753 u8 reserved_at_80[0x20]; 1754 1755 u8 rpg_time_reset[0x20]; 1756 1757 u8 rpg_byte_reset[0x20]; 1758 1759 u8 rpg_threshold[0x20]; 1760 1761 u8 rpg_max_rate[0x20]; 1762 1763 u8 rpg_ai_rate[0x20]; 1764 1765 u8 rpg_hai_rate[0x20]; 1766 1767 u8 rpg_gd[0x20]; 1768 1769 u8 rpg_min_dec_fac[0x20]; 1770 1771 u8 rpg_min_rate[0x20]; 1772 1773 u8 reserved_at_1c0[0xe0]; 1774 1775 u8 rate_to_set_on_first_cnp[0x20]; 1776 1777 u8 dce_tcp_g[0x20]; 1778 1779 u8 dce_tcp_rtt[0x20]; 1780 1781 u8 rate_reduce_monitor_period[0x20]; 1782 1783 u8 reserved_at_320[0x20]; 1784 1785 u8 initial_alpha_value[0x20]; 1786 1787 u8 reserved_at_360[0x4a0]; 1788 }; 1789 1790 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1791 u8 reserved_at_0[0x80]; 1792 1793 u8 rppp_max_rps[0x20]; 1794 1795 u8 rpg_time_reset[0x20]; 1796 1797 u8 rpg_byte_reset[0x20]; 1798 1799 u8 rpg_threshold[0x20]; 1800 1801 u8 rpg_max_rate[0x20]; 1802 1803 u8 rpg_ai_rate[0x20]; 1804 1805 u8 rpg_hai_rate[0x20]; 1806 1807 u8 rpg_gd[0x20]; 1808 1809 u8 rpg_min_dec_fac[0x20]; 1810 1811 u8 rpg_min_rate[0x20]; 1812 1813 u8 reserved_at_1c0[0x640]; 1814 }; 1815 1816 enum { 1817 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1818 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1819 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1820 }; 1821 1822 struct mlx5_ifc_resize_field_select_bits { 1823 u8 resize_field_select[0x20]; 1824 }; 1825 1826 struct mlx5_ifc_resource_dump_bits { 1827 u8 more_dump[0x1]; 1828 u8 inline_dump[0x1]; 1829 u8 reserved_at_2[0xa]; 1830 u8 seq_num[0x4]; 1831 u8 segment_type[0x10]; 1832 1833 u8 reserved_at_20[0x10]; 1834 u8 vhca_id[0x10]; 1835 1836 u8 index1[0x20]; 1837 1838 u8 index2[0x20]; 1839 1840 u8 num_of_obj1[0x10]; 1841 u8 num_of_obj2[0x10]; 1842 1843 u8 reserved_at_a0[0x20]; 1844 1845 u8 device_opaque[0x40]; 1846 1847 u8 mkey[0x20]; 1848 1849 u8 size[0x20]; 1850 1851 u8 address[0x40]; 1852 1853 u8 inline_data[52][0x20]; 1854 }; 1855 1856 struct mlx5_ifc_resource_dump_menu_record_bits { 1857 u8 reserved_at_0[0x4]; 1858 u8 num_of_obj2_supports_active[0x1]; 1859 u8 num_of_obj2_supports_all[0x1]; 1860 u8 must_have_num_of_obj2[0x1]; 1861 u8 support_num_of_obj2[0x1]; 1862 u8 num_of_obj1_supports_active[0x1]; 1863 u8 num_of_obj1_supports_all[0x1]; 1864 u8 must_have_num_of_obj1[0x1]; 1865 u8 support_num_of_obj1[0x1]; 1866 u8 must_have_index2[0x1]; 1867 u8 support_index2[0x1]; 1868 u8 must_have_index1[0x1]; 1869 u8 support_index1[0x1]; 1870 u8 segment_type[0x10]; 1871 1872 u8 segment_name[4][0x20]; 1873 1874 u8 index1_name[4][0x20]; 1875 1876 u8 index2_name[4][0x20]; 1877 }; 1878 1879 struct mlx5_ifc_resource_dump_segment_header_bits { 1880 u8 length_dw[0x10]; 1881 u8 segment_type[0x10]; 1882 }; 1883 1884 struct mlx5_ifc_resource_dump_command_segment_bits { 1885 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1886 1887 u8 segment_called[0x10]; 1888 u8 vhca_id[0x10]; 1889 1890 u8 index1[0x20]; 1891 1892 u8 index2[0x20]; 1893 1894 u8 num_of_obj1[0x10]; 1895 u8 num_of_obj2[0x10]; 1896 }; 1897 1898 struct mlx5_ifc_resource_dump_error_segment_bits { 1899 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1900 1901 u8 reserved_at_20[0x10]; 1902 u8 syndrome_id[0x10]; 1903 1904 u8 reserved_at_40[0x40]; 1905 1906 u8 error[8][0x20]; 1907 }; 1908 1909 struct mlx5_ifc_resource_dump_info_segment_bits { 1910 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1911 1912 u8 reserved_at_20[0x18]; 1913 u8 dump_version[0x8]; 1914 1915 u8 hw_version[0x20]; 1916 1917 u8 fw_version[0x20]; 1918 }; 1919 1920 struct mlx5_ifc_resource_dump_menu_segment_bits { 1921 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1922 1923 u8 reserved_at_20[0x10]; 1924 u8 num_of_records[0x10]; 1925 1926 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 1927 }; 1928 1929 struct mlx5_ifc_resource_dump_resource_segment_bits { 1930 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1931 1932 u8 reserved_at_20[0x20]; 1933 1934 u8 index1[0x20]; 1935 1936 u8 index2[0x20]; 1937 1938 u8 payload[][0x20]; 1939 }; 1940 1941 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1942 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1943 }; 1944 1945 struct mlx5_ifc_menu_resource_dump_response_bits { 1946 struct mlx5_ifc_resource_dump_info_segment_bits info; 1947 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1948 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1949 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1950 }; 1951 1952 enum { 1953 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1954 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1955 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1956 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1957 }; 1958 1959 struct mlx5_ifc_modify_field_select_bits { 1960 u8 modify_field_select[0x20]; 1961 }; 1962 1963 struct mlx5_ifc_field_select_r_roce_np_bits { 1964 u8 field_select_r_roce_np[0x20]; 1965 }; 1966 1967 struct mlx5_ifc_field_select_r_roce_rp_bits { 1968 u8 field_select_r_roce_rp[0x20]; 1969 }; 1970 1971 enum { 1972 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1973 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1974 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1975 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1976 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1977 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1978 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1979 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1980 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1981 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1982 }; 1983 1984 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1985 u8 field_select_8021qaurp[0x20]; 1986 }; 1987 1988 struct mlx5_ifc_phys_layer_cntrs_bits { 1989 u8 time_since_last_clear_high[0x20]; 1990 1991 u8 time_since_last_clear_low[0x20]; 1992 1993 u8 symbol_errors_high[0x20]; 1994 1995 u8 symbol_errors_low[0x20]; 1996 1997 u8 sync_headers_errors_high[0x20]; 1998 1999 u8 sync_headers_errors_low[0x20]; 2000 2001 u8 edpl_bip_errors_lane0_high[0x20]; 2002 2003 u8 edpl_bip_errors_lane0_low[0x20]; 2004 2005 u8 edpl_bip_errors_lane1_high[0x20]; 2006 2007 u8 edpl_bip_errors_lane1_low[0x20]; 2008 2009 u8 edpl_bip_errors_lane2_high[0x20]; 2010 2011 u8 edpl_bip_errors_lane2_low[0x20]; 2012 2013 u8 edpl_bip_errors_lane3_high[0x20]; 2014 2015 u8 edpl_bip_errors_lane3_low[0x20]; 2016 2017 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2018 2019 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2020 2021 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2022 2023 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2024 2025 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2026 2027 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2028 2029 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2030 2031 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2032 2033 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2034 2035 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2036 2037 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2038 2039 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2040 2041 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2042 2043 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2044 2045 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2046 2047 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2048 2049 u8 rs_fec_corrected_blocks_high[0x20]; 2050 2051 u8 rs_fec_corrected_blocks_low[0x20]; 2052 2053 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2054 2055 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2056 2057 u8 rs_fec_no_errors_blocks_high[0x20]; 2058 2059 u8 rs_fec_no_errors_blocks_low[0x20]; 2060 2061 u8 rs_fec_single_error_blocks_high[0x20]; 2062 2063 u8 rs_fec_single_error_blocks_low[0x20]; 2064 2065 u8 rs_fec_corrected_symbols_total_high[0x20]; 2066 2067 u8 rs_fec_corrected_symbols_total_low[0x20]; 2068 2069 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2070 2071 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2072 2073 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2074 2075 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2076 2077 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2078 2079 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2080 2081 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2082 2083 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2084 2085 u8 link_down_events[0x20]; 2086 2087 u8 successful_recovery_events[0x20]; 2088 2089 u8 reserved_at_640[0x180]; 2090 }; 2091 2092 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2093 u8 time_since_last_clear_high[0x20]; 2094 2095 u8 time_since_last_clear_low[0x20]; 2096 2097 u8 phy_received_bits_high[0x20]; 2098 2099 u8 phy_received_bits_low[0x20]; 2100 2101 u8 phy_symbol_errors_high[0x20]; 2102 2103 u8 phy_symbol_errors_low[0x20]; 2104 2105 u8 phy_corrected_bits_high[0x20]; 2106 2107 u8 phy_corrected_bits_low[0x20]; 2108 2109 u8 phy_corrected_bits_lane0_high[0x20]; 2110 2111 u8 phy_corrected_bits_lane0_low[0x20]; 2112 2113 u8 phy_corrected_bits_lane1_high[0x20]; 2114 2115 u8 phy_corrected_bits_lane1_low[0x20]; 2116 2117 u8 phy_corrected_bits_lane2_high[0x20]; 2118 2119 u8 phy_corrected_bits_lane2_low[0x20]; 2120 2121 u8 phy_corrected_bits_lane3_high[0x20]; 2122 2123 u8 phy_corrected_bits_lane3_low[0x20]; 2124 2125 u8 reserved_at_200[0x5c0]; 2126 }; 2127 2128 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2129 u8 symbol_error_counter[0x10]; 2130 2131 u8 link_error_recovery_counter[0x8]; 2132 2133 u8 link_downed_counter[0x8]; 2134 2135 u8 port_rcv_errors[0x10]; 2136 2137 u8 port_rcv_remote_physical_errors[0x10]; 2138 2139 u8 port_rcv_switch_relay_errors[0x10]; 2140 2141 u8 port_xmit_discards[0x10]; 2142 2143 u8 port_xmit_constraint_errors[0x8]; 2144 2145 u8 port_rcv_constraint_errors[0x8]; 2146 2147 u8 reserved_at_70[0x8]; 2148 2149 u8 link_overrun_errors[0x8]; 2150 2151 u8 reserved_at_80[0x10]; 2152 2153 u8 vl_15_dropped[0x10]; 2154 2155 u8 reserved_at_a0[0x80]; 2156 2157 u8 port_xmit_wait[0x20]; 2158 }; 2159 2160 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2161 u8 transmit_queue_high[0x20]; 2162 2163 u8 transmit_queue_low[0x20]; 2164 2165 u8 no_buffer_discard_uc_high[0x20]; 2166 2167 u8 no_buffer_discard_uc_low[0x20]; 2168 2169 u8 reserved_at_80[0x740]; 2170 }; 2171 2172 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2173 u8 wred_discard_high[0x20]; 2174 2175 u8 wred_discard_low[0x20]; 2176 2177 u8 ecn_marked_tc_high[0x20]; 2178 2179 u8 ecn_marked_tc_low[0x20]; 2180 2181 u8 reserved_at_80[0x740]; 2182 }; 2183 2184 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2185 u8 rx_octets_high[0x20]; 2186 2187 u8 rx_octets_low[0x20]; 2188 2189 u8 reserved_at_40[0xc0]; 2190 2191 u8 rx_frames_high[0x20]; 2192 2193 u8 rx_frames_low[0x20]; 2194 2195 u8 tx_octets_high[0x20]; 2196 2197 u8 tx_octets_low[0x20]; 2198 2199 u8 reserved_at_180[0xc0]; 2200 2201 u8 tx_frames_high[0x20]; 2202 2203 u8 tx_frames_low[0x20]; 2204 2205 u8 rx_pause_high[0x20]; 2206 2207 u8 rx_pause_low[0x20]; 2208 2209 u8 rx_pause_duration_high[0x20]; 2210 2211 u8 rx_pause_duration_low[0x20]; 2212 2213 u8 tx_pause_high[0x20]; 2214 2215 u8 tx_pause_low[0x20]; 2216 2217 u8 tx_pause_duration_high[0x20]; 2218 2219 u8 tx_pause_duration_low[0x20]; 2220 2221 u8 rx_pause_transition_high[0x20]; 2222 2223 u8 rx_pause_transition_low[0x20]; 2224 2225 u8 rx_discards_high[0x20]; 2226 2227 u8 rx_discards_low[0x20]; 2228 2229 u8 device_stall_minor_watermark_cnt_high[0x20]; 2230 2231 u8 device_stall_minor_watermark_cnt_low[0x20]; 2232 2233 u8 device_stall_critical_watermark_cnt_high[0x20]; 2234 2235 u8 device_stall_critical_watermark_cnt_low[0x20]; 2236 2237 u8 reserved_at_480[0x340]; 2238 }; 2239 2240 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2241 u8 port_transmit_wait_high[0x20]; 2242 2243 u8 port_transmit_wait_low[0x20]; 2244 2245 u8 reserved_at_40[0x100]; 2246 2247 u8 rx_buffer_almost_full_high[0x20]; 2248 2249 u8 rx_buffer_almost_full_low[0x20]; 2250 2251 u8 rx_buffer_full_high[0x20]; 2252 2253 u8 rx_buffer_full_low[0x20]; 2254 2255 u8 rx_icrc_encapsulated_high[0x20]; 2256 2257 u8 rx_icrc_encapsulated_low[0x20]; 2258 2259 u8 reserved_at_200[0x5c0]; 2260 }; 2261 2262 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2263 u8 dot3stats_alignment_errors_high[0x20]; 2264 2265 u8 dot3stats_alignment_errors_low[0x20]; 2266 2267 u8 dot3stats_fcs_errors_high[0x20]; 2268 2269 u8 dot3stats_fcs_errors_low[0x20]; 2270 2271 u8 dot3stats_single_collision_frames_high[0x20]; 2272 2273 u8 dot3stats_single_collision_frames_low[0x20]; 2274 2275 u8 dot3stats_multiple_collision_frames_high[0x20]; 2276 2277 u8 dot3stats_multiple_collision_frames_low[0x20]; 2278 2279 u8 dot3stats_sqe_test_errors_high[0x20]; 2280 2281 u8 dot3stats_sqe_test_errors_low[0x20]; 2282 2283 u8 dot3stats_deferred_transmissions_high[0x20]; 2284 2285 u8 dot3stats_deferred_transmissions_low[0x20]; 2286 2287 u8 dot3stats_late_collisions_high[0x20]; 2288 2289 u8 dot3stats_late_collisions_low[0x20]; 2290 2291 u8 dot3stats_excessive_collisions_high[0x20]; 2292 2293 u8 dot3stats_excessive_collisions_low[0x20]; 2294 2295 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2296 2297 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2298 2299 u8 dot3stats_carrier_sense_errors_high[0x20]; 2300 2301 u8 dot3stats_carrier_sense_errors_low[0x20]; 2302 2303 u8 dot3stats_frame_too_longs_high[0x20]; 2304 2305 u8 dot3stats_frame_too_longs_low[0x20]; 2306 2307 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2308 2309 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2310 2311 u8 dot3stats_symbol_errors_high[0x20]; 2312 2313 u8 dot3stats_symbol_errors_low[0x20]; 2314 2315 u8 dot3control_in_unknown_opcodes_high[0x20]; 2316 2317 u8 dot3control_in_unknown_opcodes_low[0x20]; 2318 2319 u8 dot3in_pause_frames_high[0x20]; 2320 2321 u8 dot3in_pause_frames_low[0x20]; 2322 2323 u8 dot3out_pause_frames_high[0x20]; 2324 2325 u8 dot3out_pause_frames_low[0x20]; 2326 2327 u8 reserved_at_400[0x3c0]; 2328 }; 2329 2330 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2331 u8 ether_stats_drop_events_high[0x20]; 2332 2333 u8 ether_stats_drop_events_low[0x20]; 2334 2335 u8 ether_stats_octets_high[0x20]; 2336 2337 u8 ether_stats_octets_low[0x20]; 2338 2339 u8 ether_stats_pkts_high[0x20]; 2340 2341 u8 ether_stats_pkts_low[0x20]; 2342 2343 u8 ether_stats_broadcast_pkts_high[0x20]; 2344 2345 u8 ether_stats_broadcast_pkts_low[0x20]; 2346 2347 u8 ether_stats_multicast_pkts_high[0x20]; 2348 2349 u8 ether_stats_multicast_pkts_low[0x20]; 2350 2351 u8 ether_stats_crc_align_errors_high[0x20]; 2352 2353 u8 ether_stats_crc_align_errors_low[0x20]; 2354 2355 u8 ether_stats_undersize_pkts_high[0x20]; 2356 2357 u8 ether_stats_undersize_pkts_low[0x20]; 2358 2359 u8 ether_stats_oversize_pkts_high[0x20]; 2360 2361 u8 ether_stats_oversize_pkts_low[0x20]; 2362 2363 u8 ether_stats_fragments_high[0x20]; 2364 2365 u8 ether_stats_fragments_low[0x20]; 2366 2367 u8 ether_stats_jabbers_high[0x20]; 2368 2369 u8 ether_stats_jabbers_low[0x20]; 2370 2371 u8 ether_stats_collisions_high[0x20]; 2372 2373 u8 ether_stats_collisions_low[0x20]; 2374 2375 u8 ether_stats_pkts64octets_high[0x20]; 2376 2377 u8 ether_stats_pkts64octets_low[0x20]; 2378 2379 u8 ether_stats_pkts65to127octets_high[0x20]; 2380 2381 u8 ether_stats_pkts65to127octets_low[0x20]; 2382 2383 u8 ether_stats_pkts128to255octets_high[0x20]; 2384 2385 u8 ether_stats_pkts128to255octets_low[0x20]; 2386 2387 u8 ether_stats_pkts256to511octets_high[0x20]; 2388 2389 u8 ether_stats_pkts256to511octets_low[0x20]; 2390 2391 u8 ether_stats_pkts512to1023octets_high[0x20]; 2392 2393 u8 ether_stats_pkts512to1023octets_low[0x20]; 2394 2395 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2396 2397 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2398 2399 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2400 2401 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2402 2403 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2404 2405 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2406 2407 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2408 2409 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2410 2411 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2412 2413 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2414 2415 u8 reserved_at_540[0x280]; 2416 }; 2417 2418 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2419 u8 if_in_octets_high[0x20]; 2420 2421 u8 if_in_octets_low[0x20]; 2422 2423 u8 if_in_ucast_pkts_high[0x20]; 2424 2425 u8 if_in_ucast_pkts_low[0x20]; 2426 2427 u8 if_in_discards_high[0x20]; 2428 2429 u8 if_in_discards_low[0x20]; 2430 2431 u8 if_in_errors_high[0x20]; 2432 2433 u8 if_in_errors_low[0x20]; 2434 2435 u8 if_in_unknown_protos_high[0x20]; 2436 2437 u8 if_in_unknown_protos_low[0x20]; 2438 2439 u8 if_out_octets_high[0x20]; 2440 2441 u8 if_out_octets_low[0x20]; 2442 2443 u8 if_out_ucast_pkts_high[0x20]; 2444 2445 u8 if_out_ucast_pkts_low[0x20]; 2446 2447 u8 if_out_discards_high[0x20]; 2448 2449 u8 if_out_discards_low[0x20]; 2450 2451 u8 if_out_errors_high[0x20]; 2452 2453 u8 if_out_errors_low[0x20]; 2454 2455 u8 if_in_multicast_pkts_high[0x20]; 2456 2457 u8 if_in_multicast_pkts_low[0x20]; 2458 2459 u8 if_in_broadcast_pkts_high[0x20]; 2460 2461 u8 if_in_broadcast_pkts_low[0x20]; 2462 2463 u8 if_out_multicast_pkts_high[0x20]; 2464 2465 u8 if_out_multicast_pkts_low[0x20]; 2466 2467 u8 if_out_broadcast_pkts_high[0x20]; 2468 2469 u8 if_out_broadcast_pkts_low[0x20]; 2470 2471 u8 reserved_at_340[0x480]; 2472 }; 2473 2474 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2475 u8 a_frames_transmitted_ok_high[0x20]; 2476 2477 u8 a_frames_transmitted_ok_low[0x20]; 2478 2479 u8 a_frames_received_ok_high[0x20]; 2480 2481 u8 a_frames_received_ok_low[0x20]; 2482 2483 u8 a_frame_check_sequence_errors_high[0x20]; 2484 2485 u8 a_frame_check_sequence_errors_low[0x20]; 2486 2487 u8 a_alignment_errors_high[0x20]; 2488 2489 u8 a_alignment_errors_low[0x20]; 2490 2491 u8 a_octets_transmitted_ok_high[0x20]; 2492 2493 u8 a_octets_transmitted_ok_low[0x20]; 2494 2495 u8 a_octets_received_ok_high[0x20]; 2496 2497 u8 a_octets_received_ok_low[0x20]; 2498 2499 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2500 2501 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2502 2503 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2504 2505 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2506 2507 u8 a_multicast_frames_received_ok_high[0x20]; 2508 2509 u8 a_multicast_frames_received_ok_low[0x20]; 2510 2511 u8 a_broadcast_frames_received_ok_high[0x20]; 2512 2513 u8 a_broadcast_frames_received_ok_low[0x20]; 2514 2515 u8 a_in_range_length_errors_high[0x20]; 2516 2517 u8 a_in_range_length_errors_low[0x20]; 2518 2519 u8 a_out_of_range_length_field_high[0x20]; 2520 2521 u8 a_out_of_range_length_field_low[0x20]; 2522 2523 u8 a_frame_too_long_errors_high[0x20]; 2524 2525 u8 a_frame_too_long_errors_low[0x20]; 2526 2527 u8 a_symbol_error_during_carrier_high[0x20]; 2528 2529 u8 a_symbol_error_during_carrier_low[0x20]; 2530 2531 u8 a_mac_control_frames_transmitted_high[0x20]; 2532 2533 u8 a_mac_control_frames_transmitted_low[0x20]; 2534 2535 u8 a_mac_control_frames_received_high[0x20]; 2536 2537 u8 a_mac_control_frames_received_low[0x20]; 2538 2539 u8 a_unsupported_opcodes_received_high[0x20]; 2540 2541 u8 a_unsupported_opcodes_received_low[0x20]; 2542 2543 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2544 2545 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2546 2547 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2548 2549 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2550 2551 u8 reserved_at_4c0[0x300]; 2552 }; 2553 2554 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2555 u8 life_time_counter_high[0x20]; 2556 2557 u8 life_time_counter_low[0x20]; 2558 2559 u8 rx_errors[0x20]; 2560 2561 u8 tx_errors[0x20]; 2562 2563 u8 l0_to_recovery_eieos[0x20]; 2564 2565 u8 l0_to_recovery_ts[0x20]; 2566 2567 u8 l0_to_recovery_framing[0x20]; 2568 2569 u8 l0_to_recovery_retrain[0x20]; 2570 2571 u8 crc_error_dllp[0x20]; 2572 2573 u8 crc_error_tlp[0x20]; 2574 2575 u8 tx_overflow_buffer_pkt_high[0x20]; 2576 2577 u8 tx_overflow_buffer_pkt_low[0x20]; 2578 2579 u8 outbound_stalled_reads[0x20]; 2580 2581 u8 outbound_stalled_writes[0x20]; 2582 2583 u8 outbound_stalled_reads_events[0x20]; 2584 2585 u8 outbound_stalled_writes_events[0x20]; 2586 2587 u8 reserved_at_200[0x5c0]; 2588 }; 2589 2590 struct mlx5_ifc_cmd_inter_comp_event_bits { 2591 u8 command_completion_vector[0x20]; 2592 2593 u8 reserved_at_20[0xc0]; 2594 }; 2595 2596 struct mlx5_ifc_stall_vl_event_bits { 2597 u8 reserved_at_0[0x18]; 2598 u8 port_num[0x1]; 2599 u8 reserved_at_19[0x3]; 2600 u8 vl[0x4]; 2601 2602 u8 reserved_at_20[0xa0]; 2603 }; 2604 2605 struct mlx5_ifc_db_bf_congestion_event_bits { 2606 u8 event_subtype[0x8]; 2607 u8 reserved_at_8[0x8]; 2608 u8 congestion_level[0x8]; 2609 u8 reserved_at_18[0x8]; 2610 2611 u8 reserved_at_20[0xa0]; 2612 }; 2613 2614 struct mlx5_ifc_gpio_event_bits { 2615 u8 reserved_at_0[0x60]; 2616 2617 u8 gpio_event_hi[0x20]; 2618 2619 u8 gpio_event_lo[0x20]; 2620 2621 u8 reserved_at_a0[0x40]; 2622 }; 2623 2624 struct mlx5_ifc_port_state_change_event_bits { 2625 u8 reserved_at_0[0x40]; 2626 2627 u8 port_num[0x4]; 2628 u8 reserved_at_44[0x1c]; 2629 2630 u8 reserved_at_60[0x80]; 2631 }; 2632 2633 struct mlx5_ifc_dropped_packet_logged_bits { 2634 u8 reserved_at_0[0xe0]; 2635 }; 2636 2637 enum { 2638 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2639 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2640 }; 2641 2642 struct mlx5_ifc_cq_error_bits { 2643 u8 reserved_at_0[0x8]; 2644 u8 cqn[0x18]; 2645 2646 u8 reserved_at_20[0x20]; 2647 2648 u8 reserved_at_40[0x18]; 2649 u8 syndrome[0x8]; 2650 2651 u8 reserved_at_60[0x80]; 2652 }; 2653 2654 struct mlx5_ifc_rdma_page_fault_event_bits { 2655 u8 bytes_committed[0x20]; 2656 2657 u8 r_key[0x20]; 2658 2659 u8 reserved_at_40[0x10]; 2660 u8 packet_len[0x10]; 2661 2662 u8 rdma_op_len[0x20]; 2663 2664 u8 rdma_va[0x40]; 2665 2666 u8 reserved_at_c0[0x5]; 2667 u8 rdma[0x1]; 2668 u8 write[0x1]; 2669 u8 requestor[0x1]; 2670 u8 qp_number[0x18]; 2671 }; 2672 2673 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2674 u8 bytes_committed[0x20]; 2675 2676 u8 reserved_at_20[0x10]; 2677 u8 wqe_index[0x10]; 2678 2679 u8 reserved_at_40[0x10]; 2680 u8 len[0x10]; 2681 2682 u8 reserved_at_60[0x60]; 2683 2684 u8 reserved_at_c0[0x5]; 2685 u8 rdma[0x1]; 2686 u8 write_read[0x1]; 2687 u8 requestor[0x1]; 2688 u8 qpn[0x18]; 2689 }; 2690 2691 struct mlx5_ifc_qp_events_bits { 2692 u8 reserved_at_0[0xa0]; 2693 2694 u8 type[0x8]; 2695 u8 reserved_at_a8[0x18]; 2696 2697 u8 reserved_at_c0[0x8]; 2698 u8 qpn_rqn_sqn[0x18]; 2699 }; 2700 2701 struct mlx5_ifc_dct_events_bits { 2702 u8 reserved_at_0[0xc0]; 2703 2704 u8 reserved_at_c0[0x8]; 2705 u8 dct_number[0x18]; 2706 }; 2707 2708 struct mlx5_ifc_comp_event_bits { 2709 u8 reserved_at_0[0xc0]; 2710 2711 u8 reserved_at_c0[0x8]; 2712 u8 cq_number[0x18]; 2713 }; 2714 2715 enum { 2716 MLX5_QPC_STATE_RST = 0x0, 2717 MLX5_QPC_STATE_INIT = 0x1, 2718 MLX5_QPC_STATE_RTR = 0x2, 2719 MLX5_QPC_STATE_RTS = 0x3, 2720 MLX5_QPC_STATE_SQER = 0x4, 2721 MLX5_QPC_STATE_ERR = 0x6, 2722 MLX5_QPC_STATE_SQD = 0x7, 2723 MLX5_QPC_STATE_SUSPENDED = 0x9, 2724 }; 2725 2726 enum { 2727 MLX5_QPC_ST_RC = 0x0, 2728 MLX5_QPC_ST_UC = 0x1, 2729 MLX5_QPC_ST_UD = 0x2, 2730 MLX5_QPC_ST_XRC = 0x3, 2731 MLX5_QPC_ST_DCI = 0x5, 2732 MLX5_QPC_ST_QP0 = 0x7, 2733 MLX5_QPC_ST_QP1 = 0x8, 2734 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2735 MLX5_QPC_ST_REG_UMR = 0xc, 2736 }; 2737 2738 enum { 2739 MLX5_QPC_PM_STATE_ARMED = 0x0, 2740 MLX5_QPC_PM_STATE_REARM = 0x1, 2741 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2742 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2743 }; 2744 2745 enum { 2746 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2747 }; 2748 2749 enum { 2750 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2751 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2752 }; 2753 2754 enum { 2755 MLX5_QPC_MTU_256_BYTES = 0x1, 2756 MLX5_QPC_MTU_512_BYTES = 0x2, 2757 MLX5_QPC_MTU_1K_BYTES = 0x3, 2758 MLX5_QPC_MTU_2K_BYTES = 0x4, 2759 MLX5_QPC_MTU_4K_BYTES = 0x5, 2760 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2761 }; 2762 2763 enum { 2764 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2765 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2766 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2767 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2768 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2769 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2770 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2771 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2772 }; 2773 2774 enum { 2775 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2776 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2777 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2778 }; 2779 2780 enum { 2781 MLX5_QPC_CS_RES_DISABLE = 0x0, 2782 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2783 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2784 }; 2785 2786 struct mlx5_ifc_qpc_bits { 2787 u8 state[0x4]; 2788 u8 lag_tx_port_affinity[0x4]; 2789 u8 st[0x8]; 2790 u8 reserved_at_10[0x3]; 2791 u8 pm_state[0x2]; 2792 u8 reserved_at_15[0x1]; 2793 u8 req_e2e_credit_mode[0x2]; 2794 u8 offload_type[0x4]; 2795 u8 end_padding_mode[0x2]; 2796 u8 reserved_at_1e[0x2]; 2797 2798 u8 wq_signature[0x1]; 2799 u8 block_lb_mc[0x1]; 2800 u8 atomic_like_write_en[0x1]; 2801 u8 latency_sensitive[0x1]; 2802 u8 reserved_at_24[0x1]; 2803 u8 drain_sigerr[0x1]; 2804 u8 reserved_at_26[0x2]; 2805 u8 pd[0x18]; 2806 2807 u8 mtu[0x3]; 2808 u8 log_msg_max[0x5]; 2809 u8 reserved_at_48[0x1]; 2810 u8 log_rq_size[0x4]; 2811 u8 log_rq_stride[0x3]; 2812 u8 no_sq[0x1]; 2813 u8 log_sq_size[0x4]; 2814 u8 reserved_at_55[0x6]; 2815 u8 rlky[0x1]; 2816 u8 ulp_stateless_offload_mode[0x4]; 2817 2818 u8 counter_set_id[0x8]; 2819 u8 uar_page[0x18]; 2820 2821 u8 reserved_at_80[0x8]; 2822 u8 user_index[0x18]; 2823 2824 u8 reserved_at_a0[0x3]; 2825 u8 log_page_size[0x5]; 2826 u8 remote_qpn[0x18]; 2827 2828 struct mlx5_ifc_ads_bits primary_address_path; 2829 2830 struct mlx5_ifc_ads_bits secondary_address_path; 2831 2832 u8 log_ack_req_freq[0x4]; 2833 u8 reserved_at_384[0x4]; 2834 u8 log_sra_max[0x3]; 2835 u8 reserved_at_38b[0x2]; 2836 u8 retry_count[0x3]; 2837 u8 rnr_retry[0x3]; 2838 u8 reserved_at_393[0x1]; 2839 u8 fre[0x1]; 2840 u8 cur_rnr_retry[0x3]; 2841 u8 cur_retry_count[0x3]; 2842 u8 reserved_at_39b[0x5]; 2843 2844 u8 reserved_at_3a0[0x20]; 2845 2846 u8 reserved_at_3c0[0x8]; 2847 u8 next_send_psn[0x18]; 2848 2849 u8 reserved_at_3e0[0x8]; 2850 u8 cqn_snd[0x18]; 2851 2852 u8 reserved_at_400[0x8]; 2853 u8 deth_sqpn[0x18]; 2854 2855 u8 reserved_at_420[0x20]; 2856 2857 u8 reserved_at_440[0x8]; 2858 u8 last_acked_psn[0x18]; 2859 2860 u8 reserved_at_460[0x8]; 2861 u8 ssn[0x18]; 2862 2863 u8 reserved_at_480[0x8]; 2864 u8 log_rra_max[0x3]; 2865 u8 reserved_at_48b[0x1]; 2866 u8 atomic_mode[0x4]; 2867 u8 rre[0x1]; 2868 u8 rwe[0x1]; 2869 u8 rae[0x1]; 2870 u8 reserved_at_493[0x1]; 2871 u8 page_offset[0x6]; 2872 u8 reserved_at_49a[0x3]; 2873 u8 cd_slave_receive[0x1]; 2874 u8 cd_slave_send[0x1]; 2875 u8 cd_master[0x1]; 2876 2877 u8 reserved_at_4a0[0x3]; 2878 u8 min_rnr_nak[0x5]; 2879 u8 next_rcv_psn[0x18]; 2880 2881 u8 reserved_at_4c0[0x8]; 2882 u8 xrcd[0x18]; 2883 2884 u8 reserved_at_4e0[0x8]; 2885 u8 cqn_rcv[0x18]; 2886 2887 u8 dbr_addr[0x40]; 2888 2889 u8 q_key[0x20]; 2890 2891 u8 reserved_at_560[0x5]; 2892 u8 rq_type[0x3]; 2893 u8 srqn_rmpn_xrqn[0x18]; 2894 2895 u8 reserved_at_580[0x8]; 2896 u8 rmsn[0x18]; 2897 2898 u8 hw_sq_wqebb_counter[0x10]; 2899 u8 sw_sq_wqebb_counter[0x10]; 2900 2901 u8 hw_rq_counter[0x20]; 2902 2903 u8 sw_rq_counter[0x20]; 2904 2905 u8 reserved_at_600[0x20]; 2906 2907 u8 reserved_at_620[0xf]; 2908 u8 cgs[0x1]; 2909 u8 cs_req[0x8]; 2910 u8 cs_res[0x8]; 2911 2912 u8 dc_access_key[0x40]; 2913 2914 u8 reserved_at_680[0x3]; 2915 u8 dbr_umem_valid[0x1]; 2916 2917 u8 reserved_at_684[0xbc]; 2918 }; 2919 2920 struct mlx5_ifc_roce_addr_layout_bits { 2921 u8 source_l3_address[16][0x8]; 2922 2923 u8 reserved_at_80[0x3]; 2924 u8 vlan_valid[0x1]; 2925 u8 vlan_id[0xc]; 2926 u8 source_mac_47_32[0x10]; 2927 2928 u8 source_mac_31_0[0x20]; 2929 2930 u8 reserved_at_c0[0x14]; 2931 u8 roce_l3_type[0x4]; 2932 u8 roce_version[0x8]; 2933 2934 u8 reserved_at_e0[0x20]; 2935 }; 2936 2937 union mlx5_ifc_hca_cap_union_bits { 2938 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2939 struct mlx5_ifc_odp_cap_bits odp_cap; 2940 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2941 struct mlx5_ifc_roce_cap_bits roce_cap; 2942 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2943 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2944 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2945 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2946 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2947 struct mlx5_ifc_qos_cap_bits qos_cap; 2948 struct mlx5_ifc_debug_cap_bits debug_cap; 2949 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2950 struct mlx5_ifc_tls_cap_bits tls_cap; 2951 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2952 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap; 2953 u8 reserved_at_0[0x8000]; 2954 }; 2955 2956 enum { 2957 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2958 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2959 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2960 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2961 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2962 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2963 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2964 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2965 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2966 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2967 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2968 }; 2969 2970 enum { 2971 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2972 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2973 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2974 }; 2975 2976 struct mlx5_ifc_vlan_bits { 2977 u8 ethtype[0x10]; 2978 u8 prio[0x3]; 2979 u8 cfi[0x1]; 2980 u8 vid[0xc]; 2981 }; 2982 2983 struct mlx5_ifc_flow_context_bits { 2984 struct mlx5_ifc_vlan_bits push_vlan; 2985 2986 u8 group_id[0x20]; 2987 2988 u8 reserved_at_40[0x8]; 2989 u8 flow_tag[0x18]; 2990 2991 u8 reserved_at_60[0x10]; 2992 u8 action[0x10]; 2993 2994 u8 extended_destination[0x1]; 2995 u8 reserved_at_81[0x1]; 2996 u8 flow_source[0x2]; 2997 u8 reserved_at_84[0x4]; 2998 u8 destination_list_size[0x18]; 2999 3000 u8 reserved_at_a0[0x8]; 3001 u8 flow_counter_list_size[0x18]; 3002 3003 u8 packet_reformat_id[0x20]; 3004 3005 u8 modify_header_id[0x20]; 3006 3007 struct mlx5_ifc_vlan_bits push_vlan_2; 3008 3009 u8 reserved_at_120[0xe0]; 3010 3011 struct mlx5_ifc_fte_match_param_bits match_value; 3012 3013 u8 reserved_at_1200[0x600]; 3014 3015 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3016 }; 3017 3018 enum { 3019 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3020 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3021 }; 3022 3023 struct mlx5_ifc_xrc_srqc_bits { 3024 u8 state[0x4]; 3025 u8 log_xrc_srq_size[0x4]; 3026 u8 reserved_at_8[0x18]; 3027 3028 u8 wq_signature[0x1]; 3029 u8 cont_srq[0x1]; 3030 u8 reserved_at_22[0x1]; 3031 u8 rlky[0x1]; 3032 u8 basic_cyclic_rcv_wqe[0x1]; 3033 u8 log_rq_stride[0x3]; 3034 u8 xrcd[0x18]; 3035 3036 u8 page_offset[0x6]; 3037 u8 reserved_at_46[0x1]; 3038 u8 dbr_umem_valid[0x1]; 3039 u8 cqn[0x18]; 3040 3041 u8 reserved_at_60[0x20]; 3042 3043 u8 user_index_equal_xrc_srqn[0x1]; 3044 u8 reserved_at_81[0x1]; 3045 u8 log_page_size[0x6]; 3046 u8 user_index[0x18]; 3047 3048 u8 reserved_at_a0[0x20]; 3049 3050 u8 reserved_at_c0[0x8]; 3051 u8 pd[0x18]; 3052 3053 u8 lwm[0x10]; 3054 u8 wqe_cnt[0x10]; 3055 3056 u8 reserved_at_100[0x40]; 3057 3058 u8 db_record_addr_h[0x20]; 3059 3060 u8 db_record_addr_l[0x1e]; 3061 u8 reserved_at_17e[0x2]; 3062 3063 u8 reserved_at_180[0x80]; 3064 }; 3065 3066 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3067 u8 counter_error_queues[0x20]; 3068 3069 u8 total_error_queues[0x20]; 3070 3071 u8 send_queue_priority_update_flow[0x20]; 3072 3073 u8 reserved_at_60[0x20]; 3074 3075 u8 nic_receive_steering_discard[0x40]; 3076 3077 u8 receive_discard_vport_down[0x40]; 3078 3079 u8 transmit_discard_vport_down[0x40]; 3080 3081 u8 reserved_at_140[0xa0]; 3082 3083 u8 internal_rq_out_of_buffer[0x20]; 3084 3085 u8 reserved_at_200[0xe00]; 3086 }; 3087 3088 struct mlx5_ifc_traffic_counter_bits { 3089 u8 packets[0x40]; 3090 3091 u8 octets[0x40]; 3092 }; 3093 3094 struct mlx5_ifc_tisc_bits { 3095 u8 strict_lag_tx_port_affinity[0x1]; 3096 u8 tls_en[0x1]; 3097 u8 reserved_at_2[0x2]; 3098 u8 lag_tx_port_affinity[0x04]; 3099 3100 u8 reserved_at_8[0x4]; 3101 u8 prio[0x4]; 3102 u8 reserved_at_10[0x10]; 3103 3104 u8 reserved_at_20[0x100]; 3105 3106 u8 reserved_at_120[0x8]; 3107 u8 transport_domain[0x18]; 3108 3109 u8 reserved_at_140[0x8]; 3110 u8 underlay_qpn[0x18]; 3111 3112 u8 reserved_at_160[0x8]; 3113 u8 pd[0x18]; 3114 3115 u8 reserved_at_180[0x380]; 3116 }; 3117 3118 enum { 3119 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3120 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3121 }; 3122 3123 enum { 3124 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3125 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3126 }; 3127 3128 enum { 3129 MLX5_RX_HASH_FN_NONE = 0x0, 3130 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3131 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3132 }; 3133 3134 enum { 3135 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3136 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3137 }; 3138 3139 struct mlx5_ifc_tirc_bits { 3140 u8 reserved_at_0[0x20]; 3141 3142 u8 disp_type[0x4]; 3143 u8 tls_en[0x1]; 3144 u8 reserved_at_25[0x1b]; 3145 3146 u8 reserved_at_40[0x40]; 3147 3148 u8 reserved_at_80[0x4]; 3149 u8 lro_timeout_period_usecs[0x10]; 3150 u8 lro_enable_mask[0x4]; 3151 u8 lro_max_ip_payload_size[0x8]; 3152 3153 u8 reserved_at_a0[0x40]; 3154 3155 u8 reserved_at_e0[0x8]; 3156 u8 inline_rqn[0x18]; 3157 3158 u8 rx_hash_symmetric[0x1]; 3159 u8 reserved_at_101[0x1]; 3160 u8 tunneled_offload_en[0x1]; 3161 u8 reserved_at_103[0x5]; 3162 u8 indirect_table[0x18]; 3163 3164 u8 rx_hash_fn[0x4]; 3165 u8 reserved_at_124[0x2]; 3166 u8 self_lb_block[0x2]; 3167 u8 transport_domain[0x18]; 3168 3169 u8 rx_hash_toeplitz_key[10][0x20]; 3170 3171 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3172 3173 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3174 3175 u8 reserved_at_2c0[0x4c0]; 3176 }; 3177 3178 enum { 3179 MLX5_SRQC_STATE_GOOD = 0x0, 3180 MLX5_SRQC_STATE_ERROR = 0x1, 3181 }; 3182 3183 struct mlx5_ifc_srqc_bits { 3184 u8 state[0x4]; 3185 u8 log_srq_size[0x4]; 3186 u8 reserved_at_8[0x18]; 3187 3188 u8 wq_signature[0x1]; 3189 u8 cont_srq[0x1]; 3190 u8 reserved_at_22[0x1]; 3191 u8 rlky[0x1]; 3192 u8 reserved_at_24[0x1]; 3193 u8 log_rq_stride[0x3]; 3194 u8 xrcd[0x18]; 3195 3196 u8 page_offset[0x6]; 3197 u8 reserved_at_46[0x2]; 3198 u8 cqn[0x18]; 3199 3200 u8 reserved_at_60[0x20]; 3201 3202 u8 reserved_at_80[0x2]; 3203 u8 log_page_size[0x6]; 3204 u8 reserved_at_88[0x18]; 3205 3206 u8 reserved_at_a0[0x20]; 3207 3208 u8 reserved_at_c0[0x8]; 3209 u8 pd[0x18]; 3210 3211 u8 lwm[0x10]; 3212 u8 wqe_cnt[0x10]; 3213 3214 u8 reserved_at_100[0x40]; 3215 3216 u8 dbr_addr[0x40]; 3217 3218 u8 reserved_at_180[0x80]; 3219 }; 3220 3221 enum { 3222 MLX5_SQC_STATE_RST = 0x0, 3223 MLX5_SQC_STATE_RDY = 0x1, 3224 MLX5_SQC_STATE_ERR = 0x3, 3225 }; 3226 3227 struct mlx5_ifc_sqc_bits { 3228 u8 rlky[0x1]; 3229 u8 cd_master[0x1]; 3230 u8 fre[0x1]; 3231 u8 flush_in_error_en[0x1]; 3232 u8 allow_multi_pkt_send_wqe[0x1]; 3233 u8 min_wqe_inline_mode[0x3]; 3234 u8 state[0x4]; 3235 u8 reg_umr[0x1]; 3236 u8 allow_swp[0x1]; 3237 u8 hairpin[0x1]; 3238 u8 reserved_at_f[0x11]; 3239 3240 u8 reserved_at_20[0x8]; 3241 u8 user_index[0x18]; 3242 3243 u8 reserved_at_40[0x8]; 3244 u8 cqn[0x18]; 3245 3246 u8 reserved_at_60[0x8]; 3247 u8 hairpin_peer_rq[0x18]; 3248 3249 u8 reserved_at_80[0x10]; 3250 u8 hairpin_peer_vhca[0x10]; 3251 3252 u8 reserved_at_a0[0x50]; 3253 3254 u8 packet_pacing_rate_limit_index[0x10]; 3255 u8 tis_lst_sz[0x10]; 3256 u8 reserved_at_110[0x10]; 3257 3258 u8 reserved_at_120[0x40]; 3259 3260 u8 reserved_at_160[0x8]; 3261 u8 tis_num_0[0x18]; 3262 3263 struct mlx5_ifc_wq_bits wq; 3264 }; 3265 3266 enum { 3267 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3268 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3269 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3270 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3271 }; 3272 3273 enum { 3274 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3275 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3276 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3277 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3278 }; 3279 3280 struct mlx5_ifc_scheduling_context_bits { 3281 u8 element_type[0x8]; 3282 u8 reserved_at_8[0x18]; 3283 3284 u8 element_attributes[0x20]; 3285 3286 u8 parent_element_id[0x20]; 3287 3288 u8 reserved_at_60[0x40]; 3289 3290 u8 bw_share[0x20]; 3291 3292 u8 max_average_bw[0x20]; 3293 3294 u8 reserved_at_e0[0x120]; 3295 }; 3296 3297 struct mlx5_ifc_rqtc_bits { 3298 u8 reserved_at_0[0xa0]; 3299 3300 u8 reserved_at_a0[0x10]; 3301 u8 rqt_max_size[0x10]; 3302 3303 u8 reserved_at_c0[0x10]; 3304 u8 rqt_actual_size[0x10]; 3305 3306 u8 reserved_at_e0[0x6a0]; 3307 3308 struct mlx5_ifc_rq_num_bits rq_num[]; 3309 }; 3310 3311 enum { 3312 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3313 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3314 }; 3315 3316 enum { 3317 MLX5_RQC_STATE_RST = 0x0, 3318 MLX5_RQC_STATE_RDY = 0x1, 3319 MLX5_RQC_STATE_ERR = 0x3, 3320 }; 3321 3322 struct mlx5_ifc_rqc_bits { 3323 u8 rlky[0x1]; 3324 u8 delay_drop_en[0x1]; 3325 u8 scatter_fcs[0x1]; 3326 u8 vsd[0x1]; 3327 u8 mem_rq_type[0x4]; 3328 u8 state[0x4]; 3329 u8 reserved_at_c[0x1]; 3330 u8 flush_in_error_en[0x1]; 3331 u8 hairpin[0x1]; 3332 u8 reserved_at_f[0x11]; 3333 3334 u8 reserved_at_20[0x8]; 3335 u8 user_index[0x18]; 3336 3337 u8 reserved_at_40[0x8]; 3338 u8 cqn[0x18]; 3339 3340 u8 counter_set_id[0x8]; 3341 u8 reserved_at_68[0x18]; 3342 3343 u8 reserved_at_80[0x8]; 3344 u8 rmpn[0x18]; 3345 3346 u8 reserved_at_a0[0x8]; 3347 u8 hairpin_peer_sq[0x18]; 3348 3349 u8 reserved_at_c0[0x10]; 3350 u8 hairpin_peer_vhca[0x10]; 3351 3352 u8 reserved_at_e0[0xa0]; 3353 3354 struct mlx5_ifc_wq_bits wq; 3355 }; 3356 3357 enum { 3358 MLX5_RMPC_STATE_RDY = 0x1, 3359 MLX5_RMPC_STATE_ERR = 0x3, 3360 }; 3361 3362 struct mlx5_ifc_rmpc_bits { 3363 u8 reserved_at_0[0x8]; 3364 u8 state[0x4]; 3365 u8 reserved_at_c[0x14]; 3366 3367 u8 basic_cyclic_rcv_wqe[0x1]; 3368 u8 reserved_at_21[0x1f]; 3369 3370 u8 reserved_at_40[0x140]; 3371 3372 struct mlx5_ifc_wq_bits wq; 3373 }; 3374 3375 struct mlx5_ifc_nic_vport_context_bits { 3376 u8 reserved_at_0[0x5]; 3377 u8 min_wqe_inline_mode[0x3]; 3378 u8 reserved_at_8[0x15]; 3379 u8 disable_mc_local_lb[0x1]; 3380 u8 disable_uc_local_lb[0x1]; 3381 u8 roce_en[0x1]; 3382 3383 u8 arm_change_event[0x1]; 3384 u8 reserved_at_21[0x1a]; 3385 u8 event_on_mtu[0x1]; 3386 u8 event_on_promisc_change[0x1]; 3387 u8 event_on_vlan_change[0x1]; 3388 u8 event_on_mc_address_change[0x1]; 3389 u8 event_on_uc_address_change[0x1]; 3390 3391 u8 reserved_at_40[0xc]; 3392 3393 u8 affiliation_criteria[0x4]; 3394 u8 affiliated_vhca_id[0x10]; 3395 3396 u8 reserved_at_60[0xd0]; 3397 3398 u8 mtu[0x10]; 3399 3400 u8 system_image_guid[0x40]; 3401 u8 port_guid[0x40]; 3402 u8 node_guid[0x40]; 3403 3404 u8 reserved_at_200[0x140]; 3405 u8 qkey_violation_counter[0x10]; 3406 u8 reserved_at_350[0x430]; 3407 3408 u8 promisc_uc[0x1]; 3409 u8 promisc_mc[0x1]; 3410 u8 promisc_all[0x1]; 3411 u8 reserved_at_783[0x2]; 3412 u8 allowed_list_type[0x3]; 3413 u8 reserved_at_788[0xc]; 3414 u8 allowed_list_size[0xc]; 3415 3416 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3417 3418 u8 reserved_at_7e0[0x20]; 3419 3420 u8 current_uc_mac_address[][0x40]; 3421 }; 3422 3423 enum { 3424 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3425 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3426 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3427 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3428 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3429 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3430 }; 3431 3432 struct mlx5_ifc_mkc_bits { 3433 u8 reserved_at_0[0x1]; 3434 u8 free[0x1]; 3435 u8 reserved_at_2[0x1]; 3436 u8 access_mode_4_2[0x3]; 3437 u8 reserved_at_6[0x7]; 3438 u8 relaxed_ordering_write[0x1]; 3439 u8 reserved_at_e[0x1]; 3440 u8 small_fence_on_rdma_read_response[0x1]; 3441 u8 umr_en[0x1]; 3442 u8 a[0x1]; 3443 u8 rw[0x1]; 3444 u8 rr[0x1]; 3445 u8 lw[0x1]; 3446 u8 lr[0x1]; 3447 u8 access_mode_1_0[0x2]; 3448 u8 reserved_at_18[0x8]; 3449 3450 u8 qpn[0x18]; 3451 u8 mkey_7_0[0x8]; 3452 3453 u8 reserved_at_40[0x20]; 3454 3455 u8 length64[0x1]; 3456 u8 bsf_en[0x1]; 3457 u8 sync_umr[0x1]; 3458 u8 reserved_at_63[0x2]; 3459 u8 expected_sigerr_count[0x1]; 3460 u8 reserved_at_66[0x1]; 3461 u8 en_rinval[0x1]; 3462 u8 pd[0x18]; 3463 3464 u8 start_addr[0x40]; 3465 3466 u8 len[0x40]; 3467 3468 u8 bsf_octword_size[0x20]; 3469 3470 u8 reserved_at_120[0x80]; 3471 3472 u8 translations_octword_size[0x20]; 3473 3474 u8 reserved_at_1c0[0x19]; 3475 u8 relaxed_ordering_read[0x1]; 3476 u8 reserved_at_1d9[0x1]; 3477 u8 log_page_size[0x5]; 3478 3479 u8 reserved_at_1e0[0x20]; 3480 }; 3481 3482 struct mlx5_ifc_pkey_bits { 3483 u8 reserved_at_0[0x10]; 3484 u8 pkey[0x10]; 3485 }; 3486 3487 struct mlx5_ifc_array128_auto_bits { 3488 u8 array128_auto[16][0x8]; 3489 }; 3490 3491 struct mlx5_ifc_hca_vport_context_bits { 3492 u8 field_select[0x20]; 3493 3494 u8 reserved_at_20[0xe0]; 3495 3496 u8 sm_virt_aware[0x1]; 3497 u8 has_smi[0x1]; 3498 u8 has_raw[0x1]; 3499 u8 grh_required[0x1]; 3500 u8 reserved_at_104[0xc]; 3501 u8 port_physical_state[0x4]; 3502 u8 vport_state_policy[0x4]; 3503 u8 port_state[0x4]; 3504 u8 vport_state[0x4]; 3505 3506 u8 reserved_at_120[0x20]; 3507 3508 u8 system_image_guid[0x40]; 3509 3510 u8 port_guid[0x40]; 3511 3512 u8 node_guid[0x40]; 3513 3514 u8 cap_mask1[0x20]; 3515 3516 u8 cap_mask1_field_select[0x20]; 3517 3518 u8 cap_mask2[0x20]; 3519 3520 u8 cap_mask2_field_select[0x20]; 3521 3522 u8 reserved_at_280[0x80]; 3523 3524 u8 lid[0x10]; 3525 u8 reserved_at_310[0x4]; 3526 u8 init_type_reply[0x4]; 3527 u8 lmc[0x3]; 3528 u8 subnet_timeout[0x5]; 3529 3530 u8 sm_lid[0x10]; 3531 u8 sm_sl[0x4]; 3532 u8 reserved_at_334[0xc]; 3533 3534 u8 qkey_violation_counter[0x10]; 3535 u8 pkey_violation_counter[0x10]; 3536 3537 u8 reserved_at_360[0xca0]; 3538 }; 3539 3540 struct mlx5_ifc_esw_vport_context_bits { 3541 u8 fdb_to_vport_reg_c[0x1]; 3542 u8 reserved_at_1[0x2]; 3543 u8 vport_svlan_strip[0x1]; 3544 u8 vport_cvlan_strip[0x1]; 3545 u8 vport_svlan_insert[0x1]; 3546 u8 vport_cvlan_insert[0x2]; 3547 u8 fdb_to_vport_reg_c_id[0x8]; 3548 u8 reserved_at_10[0x10]; 3549 3550 u8 reserved_at_20[0x20]; 3551 3552 u8 svlan_cfi[0x1]; 3553 u8 svlan_pcp[0x3]; 3554 u8 svlan_id[0xc]; 3555 u8 cvlan_cfi[0x1]; 3556 u8 cvlan_pcp[0x3]; 3557 u8 cvlan_id[0xc]; 3558 3559 u8 reserved_at_60[0x720]; 3560 3561 u8 sw_steering_vport_icm_address_rx[0x40]; 3562 3563 u8 sw_steering_vport_icm_address_tx[0x40]; 3564 }; 3565 3566 enum { 3567 MLX5_EQC_STATUS_OK = 0x0, 3568 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3569 }; 3570 3571 enum { 3572 MLX5_EQC_ST_ARMED = 0x9, 3573 MLX5_EQC_ST_FIRED = 0xa, 3574 }; 3575 3576 struct mlx5_ifc_eqc_bits { 3577 u8 status[0x4]; 3578 u8 reserved_at_4[0x9]; 3579 u8 ec[0x1]; 3580 u8 oi[0x1]; 3581 u8 reserved_at_f[0x5]; 3582 u8 st[0x4]; 3583 u8 reserved_at_18[0x8]; 3584 3585 u8 reserved_at_20[0x20]; 3586 3587 u8 reserved_at_40[0x14]; 3588 u8 page_offset[0x6]; 3589 u8 reserved_at_5a[0x6]; 3590 3591 u8 reserved_at_60[0x3]; 3592 u8 log_eq_size[0x5]; 3593 u8 uar_page[0x18]; 3594 3595 u8 reserved_at_80[0x20]; 3596 3597 u8 reserved_at_a0[0x18]; 3598 u8 intr[0x8]; 3599 3600 u8 reserved_at_c0[0x3]; 3601 u8 log_page_size[0x5]; 3602 u8 reserved_at_c8[0x18]; 3603 3604 u8 reserved_at_e0[0x60]; 3605 3606 u8 reserved_at_140[0x8]; 3607 u8 consumer_counter[0x18]; 3608 3609 u8 reserved_at_160[0x8]; 3610 u8 producer_counter[0x18]; 3611 3612 u8 reserved_at_180[0x80]; 3613 }; 3614 3615 enum { 3616 MLX5_DCTC_STATE_ACTIVE = 0x0, 3617 MLX5_DCTC_STATE_DRAINING = 0x1, 3618 MLX5_DCTC_STATE_DRAINED = 0x2, 3619 }; 3620 3621 enum { 3622 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3623 MLX5_DCTC_CS_RES_NA = 0x1, 3624 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3625 }; 3626 3627 enum { 3628 MLX5_DCTC_MTU_256_BYTES = 0x1, 3629 MLX5_DCTC_MTU_512_BYTES = 0x2, 3630 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3631 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3632 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3633 }; 3634 3635 struct mlx5_ifc_dctc_bits { 3636 u8 reserved_at_0[0x4]; 3637 u8 state[0x4]; 3638 u8 reserved_at_8[0x18]; 3639 3640 u8 reserved_at_20[0x8]; 3641 u8 user_index[0x18]; 3642 3643 u8 reserved_at_40[0x8]; 3644 u8 cqn[0x18]; 3645 3646 u8 counter_set_id[0x8]; 3647 u8 atomic_mode[0x4]; 3648 u8 rre[0x1]; 3649 u8 rwe[0x1]; 3650 u8 rae[0x1]; 3651 u8 atomic_like_write_en[0x1]; 3652 u8 latency_sensitive[0x1]; 3653 u8 rlky[0x1]; 3654 u8 free_ar[0x1]; 3655 u8 reserved_at_73[0xd]; 3656 3657 u8 reserved_at_80[0x8]; 3658 u8 cs_res[0x8]; 3659 u8 reserved_at_90[0x3]; 3660 u8 min_rnr_nak[0x5]; 3661 u8 reserved_at_98[0x8]; 3662 3663 u8 reserved_at_a0[0x8]; 3664 u8 srqn_xrqn[0x18]; 3665 3666 u8 reserved_at_c0[0x8]; 3667 u8 pd[0x18]; 3668 3669 u8 tclass[0x8]; 3670 u8 reserved_at_e8[0x4]; 3671 u8 flow_label[0x14]; 3672 3673 u8 dc_access_key[0x40]; 3674 3675 u8 reserved_at_140[0x5]; 3676 u8 mtu[0x3]; 3677 u8 port[0x8]; 3678 u8 pkey_index[0x10]; 3679 3680 u8 reserved_at_160[0x8]; 3681 u8 my_addr_index[0x8]; 3682 u8 reserved_at_170[0x8]; 3683 u8 hop_limit[0x8]; 3684 3685 u8 dc_access_key_violation_count[0x20]; 3686 3687 u8 reserved_at_1a0[0x14]; 3688 u8 dei_cfi[0x1]; 3689 u8 eth_prio[0x3]; 3690 u8 ecn[0x2]; 3691 u8 dscp[0x6]; 3692 3693 u8 reserved_at_1c0[0x20]; 3694 u8 ece[0x20]; 3695 }; 3696 3697 enum { 3698 MLX5_CQC_STATUS_OK = 0x0, 3699 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3700 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3701 }; 3702 3703 enum { 3704 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3705 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3706 }; 3707 3708 enum { 3709 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3710 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3711 MLX5_CQC_ST_FIRED = 0xa, 3712 }; 3713 3714 enum { 3715 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3716 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3717 MLX5_CQ_PERIOD_NUM_MODES 3718 }; 3719 3720 struct mlx5_ifc_cqc_bits { 3721 u8 status[0x4]; 3722 u8 reserved_at_4[0x2]; 3723 u8 dbr_umem_valid[0x1]; 3724 u8 reserved_at_7[0x1]; 3725 u8 cqe_sz[0x3]; 3726 u8 cc[0x1]; 3727 u8 reserved_at_c[0x1]; 3728 u8 scqe_break_moderation_en[0x1]; 3729 u8 oi[0x1]; 3730 u8 cq_period_mode[0x2]; 3731 u8 cqe_comp_en[0x1]; 3732 u8 mini_cqe_res_format[0x2]; 3733 u8 st[0x4]; 3734 u8 reserved_at_18[0x8]; 3735 3736 u8 reserved_at_20[0x20]; 3737 3738 u8 reserved_at_40[0x14]; 3739 u8 page_offset[0x6]; 3740 u8 reserved_at_5a[0x6]; 3741 3742 u8 reserved_at_60[0x3]; 3743 u8 log_cq_size[0x5]; 3744 u8 uar_page[0x18]; 3745 3746 u8 reserved_at_80[0x4]; 3747 u8 cq_period[0xc]; 3748 u8 cq_max_count[0x10]; 3749 3750 u8 reserved_at_a0[0x18]; 3751 u8 c_eqn[0x8]; 3752 3753 u8 reserved_at_c0[0x3]; 3754 u8 log_page_size[0x5]; 3755 u8 reserved_at_c8[0x18]; 3756 3757 u8 reserved_at_e0[0x20]; 3758 3759 u8 reserved_at_100[0x8]; 3760 u8 last_notified_index[0x18]; 3761 3762 u8 reserved_at_120[0x8]; 3763 u8 last_solicit_index[0x18]; 3764 3765 u8 reserved_at_140[0x8]; 3766 u8 consumer_counter[0x18]; 3767 3768 u8 reserved_at_160[0x8]; 3769 u8 producer_counter[0x18]; 3770 3771 u8 reserved_at_180[0x40]; 3772 3773 u8 dbr_addr[0x40]; 3774 }; 3775 3776 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3777 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3778 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3779 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3780 u8 reserved_at_0[0x800]; 3781 }; 3782 3783 struct mlx5_ifc_query_adapter_param_block_bits { 3784 u8 reserved_at_0[0xc0]; 3785 3786 u8 reserved_at_c0[0x8]; 3787 u8 ieee_vendor_id[0x18]; 3788 3789 u8 reserved_at_e0[0x10]; 3790 u8 vsd_vendor_id[0x10]; 3791 3792 u8 vsd[208][0x8]; 3793 3794 u8 vsd_contd_psid[16][0x8]; 3795 }; 3796 3797 enum { 3798 MLX5_XRQC_STATE_GOOD = 0x0, 3799 MLX5_XRQC_STATE_ERROR = 0x1, 3800 }; 3801 3802 enum { 3803 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3804 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3805 }; 3806 3807 enum { 3808 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3809 }; 3810 3811 struct mlx5_ifc_tag_matching_topology_context_bits { 3812 u8 log_matching_list_sz[0x4]; 3813 u8 reserved_at_4[0xc]; 3814 u8 append_next_index[0x10]; 3815 3816 u8 sw_phase_cnt[0x10]; 3817 u8 hw_phase_cnt[0x10]; 3818 3819 u8 reserved_at_40[0x40]; 3820 }; 3821 3822 struct mlx5_ifc_xrqc_bits { 3823 u8 state[0x4]; 3824 u8 rlkey[0x1]; 3825 u8 reserved_at_5[0xf]; 3826 u8 topology[0x4]; 3827 u8 reserved_at_18[0x4]; 3828 u8 offload[0x4]; 3829 3830 u8 reserved_at_20[0x8]; 3831 u8 user_index[0x18]; 3832 3833 u8 reserved_at_40[0x8]; 3834 u8 cqn[0x18]; 3835 3836 u8 reserved_at_60[0xa0]; 3837 3838 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3839 3840 u8 reserved_at_180[0x280]; 3841 3842 struct mlx5_ifc_wq_bits wq; 3843 }; 3844 3845 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3846 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3847 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3848 u8 reserved_at_0[0x20]; 3849 }; 3850 3851 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3852 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3853 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3854 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3855 u8 reserved_at_0[0x20]; 3856 }; 3857 3858 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3859 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3860 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3861 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3862 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3863 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3864 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3865 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3866 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3867 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3868 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3869 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3870 u8 reserved_at_0[0x7c0]; 3871 }; 3872 3873 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3874 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3875 u8 reserved_at_0[0x7c0]; 3876 }; 3877 3878 union mlx5_ifc_event_auto_bits { 3879 struct mlx5_ifc_comp_event_bits comp_event; 3880 struct mlx5_ifc_dct_events_bits dct_events; 3881 struct mlx5_ifc_qp_events_bits qp_events; 3882 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3883 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3884 struct mlx5_ifc_cq_error_bits cq_error; 3885 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3886 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3887 struct mlx5_ifc_gpio_event_bits gpio_event; 3888 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3889 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3890 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3891 u8 reserved_at_0[0xe0]; 3892 }; 3893 3894 struct mlx5_ifc_health_buffer_bits { 3895 u8 reserved_at_0[0x100]; 3896 3897 u8 assert_existptr[0x20]; 3898 3899 u8 assert_callra[0x20]; 3900 3901 u8 reserved_at_140[0x40]; 3902 3903 u8 fw_version[0x20]; 3904 3905 u8 hw_id[0x20]; 3906 3907 u8 reserved_at_1c0[0x20]; 3908 3909 u8 irisc_index[0x8]; 3910 u8 synd[0x8]; 3911 u8 ext_synd[0x10]; 3912 }; 3913 3914 struct mlx5_ifc_register_loopback_control_bits { 3915 u8 no_lb[0x1]; 3916 u8 reserved_at_1[0x7]; 3917 u8 port[0x8]; 3918 u8 reserved_at_10[0x10]; 3919 3920 u8 reserved_at_20[0x60]; 3921 }; 3922 3923 struct mlx5_ifc_vport_tc_element_bits { 3924 u8 traffic_class[0x4]; 3925 u8 reserved_at_4[0xc]; 3926 u8 vport_number[0x10]; 3927 }; 3928 3929 struct mlx5_ifc_vport_element_bits { 3930 u8 reserved_at_0[0x10]; 3931 u8 vport_number[0x10]; 3932 }; 3933 3934 enum { 3935 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3936 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3937 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3938 }; 3939 3940 struct mlx5_ifc_tsar_element_bits { 3941 u8 reserved_at_0[0x8]; 3942 u8 tsar_type[0x8]; 3943 u8 reserved_at_10[0x10]; 3944 }; 3945 3946 enum { 3947 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3948 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3949 }; 3950 3951 struct mlx5_ifc_teardown_hca_out_bits { 3952 u8 status[0x8]; 3953 u8 reserved_at_8[0x18]; 3954 3955 u8 syndrome[0x20]; 3956 3957 u8 reserved_at_40[0x3f]; 3958 3959 u8 state[0x1]; 3960 }; 3961 3962 enum { 3963 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3964 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3965 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3966 }; 3967 3968 struct mlx5_ifc_teardown_hca_in_bits { 3969 u8 opcode[0x10]; 3970 u8 reserved_at_10[0x10]; 3971 3972 u8 reserved_at_20[0x10]; 3973 u8 op_mod[0x10]; 3974 3975 u8 reserved_at_40[0x10]; 3976 u8 profile[0x10]; 3977 3978 u8 reserved_at_60[0x20]; 3979 }; 3980 3981 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3982 u8 status[0x8]; 3983 u8 reserved_at_8[0x18]; 3984 3985 u8 syndrome[0x20]; 3986 3987 u8 reserved_at_40[0x40]; 3988 }; 3989 3990 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3991 u8 opcode[0x10]; 3992 u8 uid[0x10]; 3993 3994 u8 reserved_at_20[0x10]; 3995 u8 op_mod[0x10]; 3996 3997 u8 reserved_at_40[0x8]; 3998 u8 qpn[0x18]; 3999 4000 u8 reserved_at_60[0x20]; 4001 4002 u8 opt_param_mask[0x20]; 4003 4004 u8 reserved_at_a0[0x20]; 4005 4006 struct mlx5_ifc_qpc_bits qpc; 4007 4008 u8 reserved_at_800[0x80]; 4009 }; 4010 4011 struct mlx5_ifc_sqd2rts_qp_out_bits { 4012 u8 status[0x8]; 4013 u8 reserved_at_8[0x18]; 4014 4015 u8 syndrome[0x20]; 4016 4017 u8 reserved_at_40[0x40]; 4018 }; 4019 4020 struct mlx5_ifc_sqd2rts_qp_in_bits { 4021 u8 opcode[0x10]; 4022 u8 uid[0x10]; 4023 4024 u8 reserved_at_20[0x10]; 4025 u8 op_mod[0x10]; 4026 4027 u8 reserved_at_40[0x8]; 4028 u8 qpn[0x18]; 4029 4030 u8 reserved_at_60[0x20]; 4031 4032 u8 opt_param_mask[0x20]; 4033 4034 u8 reserved_at_a0[0x20]; 4035 4036 struct mlx5_ifc_qpc_bits qpc; 4037 4038 u8 reserved_at_800[0x80]; 4039 }; 4040 4041 struct mlx5_ifc_set_roce_address_out_bits { 4042 u8 status[0x8]; 4043 u8 reserved_at_8[0x18]; 4044 4045 u8 syndrome[0x20]; 4046 4047 u8 reserved_at_40[0x40]; 4048 }; 4049 4050 struct mlx5_ifc_set_roce_address_in_bits { 4051 u8 opcode[0x10]; 4052 u8 reserved_at_10[0x10]; 4053 4054 u8 reserved_at_20[0x10]; 4055 u8 op_mod[0x10]; 4056 4057 u8 roce_address_index[0x10]; 4058 u8 reserved_at_50[0xc]; 4059 u8 vhca_port_num[0x4]; 4060 4061 u8 reserved_at_60[0x20]; 4062 4063 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4064 }; 4065 4066 struct mlx5_ifc_set_mad_demux_out_bits { 4067 u8 status[0x8]; 4068 u8 reserved_at_8[0x18]; 4069 4070 u8 syndrome[0x20]; 4071 4072 u8 reserved_at_40[0x40]; 4073 }; 4074 4075 enum { 4076 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4077 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4078 }; 4079 4080 struct mlx5_ifc_set_mad_demux_in_bits { 4081 u8 opcode[0x10]; 4082 u8 reserved_at_10[0x10]; 4083 4084 u8 reserved_at_20[0x10]; 4085 u8 op_mod[0x10]; 4086 4087 u8 reserved_at_40[0x20]; 4088 4089 u8 reserved_at_60[0x6]; 4090 u8 demux_mode[0x2]; 4091 u8 reserved_at_68[0x18]; 4092 }; 4093 4094 struct mlx5_ifc_set_l2_table_entry_out_bits { 4095 u8 status[0x8]; 4096 u8 reserved_at_8[0x18]; 4097 4098 u8 syndrome[0x20]; 4099 4100 u8 reserved_at_40[0x40]; 4101 }; 4102 4103 struct mlx5_ifc_set_l2_table_entry_in_bits { 4104 u8 opcode[0x10]; 4105 u8 reserved_at_10[0x10]; 4106 4107 u8 reserved_at_20[0x10]; 4108 u8 op_mod[0x10]; 4109 4110 u8 reserved_at_40[0x60]; 4111 4112 u8 reserved_at_a0[0x8]; 4113 u8 table_index[0x18]; 4114 4115 u8 reserved_at_c0[0x20]; 4116 4117 u8 reserved_at_e0[0x13]; 4118 u8 vlan_valid[0x1]; 4119 u8 vlan[0xc]; 4120 4121 struct mlx5_ifc_mac_address_layout_bits mac_address; 4122 4123 u8 reserved_at_140[0xc0]; 4124 }; 4125 4126 struct mlx5_ifc_set_issi_out_bits { 4127 u8 status[0x8]; 4128 u8 reserved_at_8[0x18]; 4129 4130 u8 syndrome[0x20]; 4131 4132 u8 reserved_at_40[0x40]; 4133 }; 4134 4135 struct mlx5_ifc_set_issi_in_bits { 4136 u8 opcode[0x10]; 4137 u8 reserved_at_10[0x10]; 4138 4139 u8 reserved_at_20[0x10]; 4140 u8 op_mod[0x10]; 4141 4142 u8 reserved_at_40[0x10]; 4143 u8 current_issi[0x10]; 4144 4145 u8 reserved_at_60[0x20]; 4146 }; 4147 4148 struct mlx5_ifc_set_hca_cap_out_bits { 4149 u8 status[0x8]; 4150 u8 reserved_at_8[0x18]; 4151 4152 u8 syndrome[0x20]; 4153 4154 u8 reserved_at_40[0x40]; 4155 }; 4156 4157 struct mlx5_ifc_set_hca_cap_in_bits { 4158 u8 opcode[0x10]; 4159 u8 reserved_at_10[0x10]; 4160 4161 u8 reserved_at_20[0x10]; 4162 u8 op_mod[0x10]; 4163 4164 u8 reserved_at_40[0x40]; 4165 4166 union mlx5_ifc_hca_cap_union_bits capability; 4167 }; 4168 4169 enum { 4170 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4171 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4172 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4173 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4174 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4175 }; 4176 4177 struct mlx5_ifc_set_fte_out_bits { 4178 u8 status[0x8]; 4179 u8 reserved_at_8[0x18]; 4180 4181 u8 syndrome[0x20]; 4182 4183 u8 reserved_at_40[0x40]; 4184 }; 4185 4186 struct mlx5_ifc_set_fte_in_bits { 4187 u8 opcode[0x10]; 4188 u8 reserved_at_10[0x10]; 4189 4190 u8 reserved_at_20[0x10]; 4191 u8 op_mod[0x10]; 4192 4193 u8 other_vport[0x1]; 4194 u8 reserved_at_41[0xf]; 4195 u8 vport_number[0x10]; 4196 4197 u8 reserved_at_60[0x20]; 4198 4199 u8 table_type[0x8]; 4200 u8 reserved_at_88[0x18]; 4201 4202 u8 reserved_at_a0[0x8]; 4203 u8 table_id[0x18]; 4204 4205 u8 ignore_flow_level[0x1]; 4206 u8 reserved_at_c1[0x17]; 4207 u8 modify_enable_mask[0x8]; 4208 4209 u8 reserved_at_e0[0x20]; 4210 4211 u8 flow_index[0x20]; 4212 4213 u8 reserved_at_120[0xe0]; 4214 4215 struct mlx5_ifc_flow_context_bits flow_context; 4216 }; 4217 4218 struct mlx5_ifc_rts2rts_qp_out_bits { 4219 u8 status[0x8]; 4220 u8 reserved_at_8[0x18]; 4221 4222 u8 syndrome[0x20]; 4223 4224 u8 reserved_at_40[0x20]; 4225 u8 ece[0x20]; 4226 }; 4227 4228 struct mlx5_ifc_rts2rts_qp_in_bits { 4229 u8 opcode[0x10]; 4230 u8 uid[0x10]; 4231 4232 u8 reserved_at_20[0x10]; 4233 u8 op_mod[0x10]; 4234 4235 u8 reserved_at_40[0x8]; 4236 u8 qpn[0x18]; 4237 4238 u8 reserved_at_60[0x20]; 4239 4240 u8 opt_param_mask[0x20]; 4241 4242 u8 ece[0x20]; 4243 4244 struct mlx5_ifc_qpc_bits qpc; 4245 4246 u8 reserved_at_800[0x80]; 4247 }; 4248 4249 struct mlx5_ifc_rtr2rts_qp_out_bits { 4250 u8 status[0x8]; 4251 u8 reserved_at_8[0x18]; 4252 4253 u8 syndrome[0x20]; 4254 4255 u8 reserved_at_40[0x20]; 4256 u8 ece[0x20]; 4257 }; 4258 4259 struct mlx5_ifc_rtr2rts_qp_in_bits { 4260 u8 opcode[0x10]; 4261 u8 uid[0x10]; 4262 4263 u8 reserved_at_20[0x10]; 4264 u8 op_mod[0x10]; 4265 4266 u8 reserved_at_40[0x8]; 4267 u8 qpn[0x18]; 4268 4269 u8 reserved_at_60[0x20]; 4270 4271 u8 opt_param_mask[0x20]; 4272 4273 u8 ece[0x20]; 4274 4275 struct mlx5_ifc_qpc_bits qpc; 4276 4277 u8 reserved_at_800[0x80]; 4278 }; 4279 4280 struct mlx5_ifc_rst2init_qp_out_bits { 4281 u8 status[0x8]; 4282 u8 reserved_at_8[0x18]; 4283 4284 u8 syndrome[0x20]; 4285 4286 u8 reserved_at_40[0x20]; 4287 u8 ece[0x20]; 4288 }; 4289 4290 struct mlx5_ifc_rst2init_qp_in_bits { 4291 u8 opcode[0x10]; 4292 u8 uid[0x10]; 4293 4294 u8 reserved_at_20[0x10]; 4295 u8 op_mod[0x10]; 4296 4297 u8 reserved_at_40[0x8]; 4298 u8 qpn[0x18]; 4299 4300 u8 reserved_at_60[0x20]; 4301 4302 u8 opt_param_mask[0x20]; 4303 4304 u8 ece[0x20]; 4305 4306 struct mlx5_ifc_qpc_bits qpc; 4307 4308 u8 reserved_at_800[0x80]; 4309 }; 4310 4311 struct mlx5_ifc_query_xrq_out_bits { 4312 u8 status[0x8]; 4313 u8 reserved_at_8[0x18]; 4314 4315 u8 syndrome[0x20]; 4316 4317 u8 reserved_at_40[0x40]; 4318 4319 struct mlx5_ifc_xrqc_bits xrq_context; 4320 }; 4321 4322 struct mlx5_ifc_query_xrq_in_bits { 4323 u8 opcode[0x10]; 4324 u8 reserved_at_10[0x10]; 4325 4326 u8 reserved_at_20[0x10]; 4327 u8 op_mod[0x10]; 4328 4329 u8 reserved_at_40[0x8]; 4330 u8 xrqn[0x18]; 4331 4332 u8 reserved_at_60[0x20]; 4333 }; 4334 4335 struct mlx5_ifc_query_xrc_srq_out_bits { 4336 u8 status[0x8]; 4337 u8 reserved_at_8[0x18]; 4338 4339 u8 syndrome[0x20]; 4340 4341 u8 reserved_at_40[0x40]; 4342 4343 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4344 4345 u8 reserved_at_280[0x600]; 4346 4347 u8 pas[][0x40]; 4348 }; 4349 4350 struct mlx5_ifc_query_xrc_srq_in_bits { 4351 u8 opcode[0x10]; 4352 u8 reserved_at_10[0x10]; 4353 4354 u8 reserved_at_20[0x10]; 4355 u8 op_mod[0x10]; 4356 4357 u8 reserved_at_40[0x8]; 4358 u8 xrc_srqn[0x18]; 4359 4360 u8 reserved_at_60[0x20]; 4361 }; 4362 4363 enum { 4364 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4365 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4366 }; 4367 4368 struct mlx5_ifc_query_vport_state_out_bits { 4369 u8 status[0x8]; 4370 u8 reserved_at_8[0x18]; 4371 4372 u8 syndrome[0x20]; 4373 4374 u8 reserved_at_40[0x20]; 4375 4376 u8 reserved_at_60[0x18]; 4377 u8 admin_state[0x4]; 4378 u8 state[0x4]; 4379 }; 4380 4381 enum { 4382 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4383 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4384 }; 4385 4386 struct mlx5_ifc_arm_monitor_counter_in_bits { 4387 u8 opcode[0x10]; 4388 u8 uid[0x10]; 4389 4390 u8 reserved_at_20[0x10]; 4391 u8 op_mod[0x10]; 4392 4393 u8 reserved_at_40[0x20]; 4394 4395 u8 reserved_at_60[0x20]; 4396 }; 4397 4398 struct mlx5_ifc_arm_monitor_counter_out_bits { 4399 u8 status[0x8]; 4400 u8 reserved_at_8[0x18]; 4401 4402 u8 syndrome[0x20]; 4403 4404 u8 reserved_at_40[0x40]; 4405 }; 4406 4407 enum { 4408 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4409 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4410 }; 4411 4412 enum mlx5_monitor_counter_ppcnt { 4413 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4414 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4415 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4416 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4417 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4418 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4419 }; 4420 4421 enum { 4422 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4423 }; 4424 4425 struct mlx5_ifc_monitor_counter_output_bits { 4426 u8 reserved_at_0[0x4]; 4427 u8 type[0x4]; 4428 u8 reserved_at_8[0x8]; 4429 u8 counter[0x10]; 4430 4431 u8 counter_group_id[0x20]; 4432 }; 4433 4434 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4435 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4436 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4437 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4438 4439 struct mlx5_ifc_set_monitor_counter_in_bits { 4440 u8 opcode[0x10]; 4441 u8 uid[0x10]; 4442 4443 u8 reserved_at_20[0x10]; 4444 u8 op_mod[0x10]; 4445 4446 u8 reserved_at_40[0x10]; 4447 u8 num_of_counters[0x10]; 4448 4449 u8 reserved_at_60[0x20]; 4450 4451 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4452 }; 4453 4454 struct mlx5_ifc_set_monitor_counter_out_bits { 4455 u8 status[0x8]; 4456 u8 reserved_at_8[0x18]; 4457 4458 u8 syndrome[0x20]; 4459 4460 u8 reserved_at_40[0x40]; 4461 }; 4462 4463 struct mlx5_ifc_query_vport_state_in_bits { 4464 u8 opcode[0x10]; 4465 u8 reserved_at_10[0x10]; 4466 4467 u8 reserved_at_20[0x10]; 4468 u8 op_mod[0x10]; 4469 4470 u8 other_vport[0x1]; 4471 u8 reserved_at_41[0xf]; 4472 u8 vport_number[0x10]; 4473 4474 u8 reserved_at_60[0x20]; 4475 }; 4476 4477 struct mlx5_ifc_query_vnic_env_out_bits { 4478 u8 status[0x8]; 4479 u8 reserved_at_8[0x18]; 4480 4481 u8 syndrome[0x20]; 4482 4483 u8 reserved_at_40[0x40]; 4484 4485 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4486 }; 4487 4488 enum { 4489 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4490 }; 4491 4492 struct mlx5_ifc_query_vnic_env_in_bits { 4493 u8 opcode[0x10]; 4494 u8 reserved_at_10[0x10]; 4495 4496 u8 reserved_at_20[0x10]; 4497 u8 op_mod[0x10]; 4498 4499 u8 other_vport[0x1]; 4500 u8 reserved_at_41[0xf]; 4501 u8 vport_number[0x10]; 4502 4503 u8 reserved_at_60[0x20]; 4504 }; 4505 4506 struct mlx5_ifc_query_vport_counter_out_bits { 4507 u8 status[0x8]; 4508 u8 reserved_at_8[0x18]; 4509 4510 u8 syndrome[0x20]; 4511 4512 u8 reserved_at_40[0x40]; 4513 4514 struct mlx5_ifc_traffic_counter_bits received_errors; 4515 4516 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4517 4518 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4519 4520 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4521 4522 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4523 4524 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4525 4526 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4527 4528 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4529 4530 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4531 4532 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4533 4534 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4535 4536 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4537 4538 u8 reserved_at_680[0xa00]; 4539 }; 4540 4541 enum { 4542 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4543 }; 4544 4545 struct mlx5_ifc_query_vport_counter_in_bits { 4546 u8 opcode[0x10]; 4547 u8 reserved_at_10[0x10]; 4548 4549 u8 reserved_at_20[0x10]; 4550 u8 op_mod[0x10]; 4551 4552 u8 other_vport[0x1]; 4553 u8 reserved_at_41[0xb]; 4554 u8 port_num[0x4]; 4555 u8 vport_number[0x10]; 4556 4557 u8 reserved_at_60[0x60]; 4558 4559 u8 clear[0x1]; 4560 u8 reserved_at_c1[0x1f]; 4561 4562 u8 reserved_at_e0[0x20]; 4563 }; 4564 4565 struct mlx5_ifc_query_tis_out_bits { 4566 u8 status[0x8]; 4567 u8 reserved_at_8[0x18]; 4568 4569 u8 syndrome[0x20]; 4570 4571 u8 reserved_at_40[0x40]; 4572 4573 struct mlx5_ifc_tisc_bits tis_context; 4574 }; 4575 4576 struct mlx5_ifc_query_tis_in_bits { 4577 u8 opcode[0x10]; 4578 u8 reserved_at_10[0x10]; 4579 4580 u8 reserved_at_20[0x10]; 4581 u8 op_mod[0x10]; 4582 4583 u8 reserved_at_40[0x8]; 4584 u8 tisn[0x18]; 4585 4586 u8 reserved_at_60[0x20]; 4587 }; 4588 4589 struct mlx5_ifc_query_tir_out_bits { 4590 u8 status[0x8]; 4591 u8 reserved_at_8[0x18]; 4592 4593 u8 syndrome[0x20]; 4594 4595 u8 reserved_at_40[0xc0]; 4596 4597 struct mlx5_ifc_tirc_bits tir_context; 4598 }; 4599 4600 struct mlx5_ifc_query_tir_in_bits { 4601 u8 opcode[0x10]; 4602 u8 reserved_at_10[0x10]; 4603 4604 u8 reserved_at_20[0x10]; 4605 u8 op_mod[0x10]; 4606 4607 u8 reserved_at_40[0x8]; 4608 u8 tirn[0x18]; 4609 4610 u8 reserved_at_60[0x20]; 4611 }; 4612 4613 struct mlx5_ifc_query_srq_out_bits { 4614 u8 status[0x8]; 4615 u8 reserved_at_8[0x18]; 4616 4617 u8 syndrome[0x20]; 4618 4619 u8 reserved_at_40[0x40]; 4620 4621 struct mlx5_ifc_srqc_bits srq_context_entry; 4622 4623 u8 reserved_at_280[0x600]; 4624 4625 u8 pas[][0x40]; 4626 }; 4627 4628 struct mlx5_ifc_query_srq_in_bits { 4629 u8 opcode[0x10]; 4630 u8 reserved_at_10[0x10]; 4631 4632 u8 reserved_at_20[0x10]; 4633 u8 op_mod[0x10]; 4634 4635 u8 reserved_at_40[0x8]; 4636 u8 srqn[0x18]; 4637 4638 u8 reserved_at_60[0x20]; 4639 }; 4640 4641 struct mlx5_ifc_query_sq_out_bits { 4642 u8 status[0x8]; 4643 u8 reserved_at_8[0x18]; 4644 4645 u8 syndrome[0x20]; 4646 4647 u8 reserved_at_40[0xc0]; 4648 4649 struct mlx5_ifc_sqc_bits sq_context; 4650 }; 4651 4652 struct mlx5_ifc_query_sq_in_bits { 4653 u8 opcode[0x10]; 4654 u8 reserved_at_10[0x10]; 4655 4656 u8 reserved_at_20[0x10]; 4657 u8 op_mod[0x10]; 4658 4659 u8 reserved_at_40[0x8]; 4660 u8 sqn[0x18]; 4661 4662 u8 reserved_at_60[0x20]; 4663 }; 4664 4665 struct mlx5_ifc_query_special_contexts_out_bits { 4666 u8 status[0x8]; 4667 u8 reserved_at_8[0x18]; 4668 4669 u8 syndrome[0x20]; 4670 4671 u8 dump_fill_mkey[0x20]; 4672 4673 u8 resd_lkey[0x20]; 4674 4675 u8 null_mkey[0x20]; 4676 4677 u8 reserved_at_a0[0x60]; 4678 }; 4679 4680 struct mlx5_ifc_query_special_contexts_in_bits { 4681 u8 opcode[0x10]; 4682 u8 reserved_at_10[0x10]; 4683 4684 u8 reserved_at_20[0x10]; 4685 u8 op_mod[0x10]; 4686 4687 u8 reserved_at_40[0x40]; 4688 }; 4689 4690 struct mlx5_ifc_query_scheduling_element_out_bits { 4691 u8 opcode[0x10]; 4692 u8 reserved_at_10[0x10]; 4693 4694 u8 reserved_at_20[0x10]; 4695 u8 op_mod[0x10]; 4696 4697 u8 reserved_at_40[0xc0]; 4698 4699 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4700 4701 u8 reserved_at_300[0x100]; 4702 }; 4703 4704 enum { 4705 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4706 }; 4707 4708 struct mlx5_ifc_query_scheduling_element_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 scheduling_hierarchy[0x8]; 4716 u8 reserved_at_48[0x18]; 4717 4718 u8 scheduling_element_id[0x20]; 4719 4720 u8 reserved_at_80[0x180]; 4721 }; 4722 4723 struct mlx5_ifc_query_rqt_out_bits { 4724 u8 status[0x8]; 4725 u8 reserved_at_8[0x18]; 4726 4727 u8 syndrome[0x20]; 4728 4729 u8 reserved_at_40[0xc0]; 4730 4731 struct mlx5_ifc_rqtc_bits rqt_context; 4732 }; 4733 4734 struct mlx5_ifc_query_rqt_in_bits { 4735 u8 opcode[0x10]; 4736 u8 reserved_at_10[0x10]; 4737 4738 u8 reserved_at_20[0x10]; 4739 u8 op_mod[0x10]; 4740 4741 u8 reserved_at_40[0x8]; 4742 u8 rqtn[0x18]; 4743 4744 u8 reserved_at_60[0x20]; 4745 }; 4746 4747 struct mlx5_ifc_query_rq_out_bits { 4748 u8 status[0x8]; 4749 u8 reserved_at_8[0x18]; 4750 4751 u8 syndrome[0x20]; 4752 4753 u8 reserved_at_40[0xc0]; 4754 4755 struct mlx5_ifc_rqc_bits rq_context; 4756 }; 4757 4758 struct mlx5_ifc_query_rq_in_bits { 4759 u8 opcode[0x10]; 4760 u8 reserved_at_10[0x10]; 4761 4762 u8 reserved_at_20[0x10]; 4763 u8 op_mod[0x10]; 4764 4765 u8 reserved_at_40[0x8]; 4766 u8 rqn[0x18]; 4767 4768 u8 reserved_at_60[0x20]; 4769 }; 4770 4771 struct mlx5_ifc_query_roce_address_out_bits { 4772 u8 status[0x8]; 4773 u8 reserved_at_8[0x18]; 4774 4775 u8 syndrome[0x20]; 4776 4777 u8 reserved_at_40[0x40]; 4778 4779 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4780 }; 4781 4782 struct mlx5_ifc_query_roce_address_in_bits { 4783 u8 opcode[0x10]; 4784 u8 reserved_at_10[0x10]; 4785 4786 u8 reserved_at_20[0x10]; 4787 u8 op_mod[0x10]; 4788 4789 u8 roce_address_index[0x10]; 4790 u8 reserved_at_50[0xc]; 4791 u8 vhca_port_num[0x4]; 4792 4793 u8 reserved_at_60[0x20]; 4794 }; 4795 4796 struct mlx5_ifc_query_rmp_out_bits { 4797 u8 status[0x8]; 4798 u8 reserved_at_8[0x18]; 4799 4800 u8 syndrome[0x20]; 4801 4802 u8 reserved_at_40[0xc0]; 4803 4804 struct mlx5_ifc_rmpc_bits rmp_context; 4805 }; 4806 4807 struct mlx5_ifc_query_rmp_in_bits { 4808 u8 opcode[0x10]; 4809 u8 reserved_at_10[0x10]; 4810 4811 u8 reserved_at_20[0x10]; 4812 u8 op_mod[0x10]; 4813 4814 u8 reserved_at_40[0x8]; 4815 u8 rmpn[0x18]; 4816 4817 u8 reserved_at_60[0x20]; 4818 }; 4819 4820 struct mlx5_ifc_query_qp_out_bits { 4821 u8 status[0x8]; 4822 u8 reserved_at_8[0x18]; 4823 4824 u8 syndrome[0x20]; 4825 4826 u8 reserved_at_40[0x20]; 4827 u8 ece[0x20]; 4828 4829 u8 opt_param_mask[0x20]; 4830 4831 u8 reserved_at_a0[0x20]; 4832 4833 struct mlx5_ifc_qpc_bits qpc; 4834 4835 u8 reserved_at_800[0x80]; 4836 4837 u8 pas[][0x40]; 4838 }; 4839 4840 struct mlx5_ifc_query_qp_in_bits { 4841 u8 opcode[0x10]; 4842 u8 reserved_at_10[0x10]; 4843 4844 u8 reserved_at_20[0x10]; 4845 u8 op_mod[0x10]; 4846 4847 u8 reserved_at_40[0x8]; 4848 u8 qpn[0x18]; 4849 4850 u8 reserved_at_60[0x20]; 4851 }; 4852 4853 struct mlx5_ifc_query_q_counter_out_bits { 4854 u8 status[0x8]; 4855 u8 reserved_at_8[0x18]; 4856 4857 u8 syndrome[0x20]; 4858 4859 u8 reserved_at_40[0x40]; 4860 4861 u8 rx_write_requests[0x20]; 4862 4863 u8 reserved_at_a0[0x20]; 4864 4865 u8 rx_read_requests[0x20]; 4866 4867 u8 reserved_at_e0[0x20]; 4868 4869 u8 rx_atomic_requests[0x20]; 4870 4871 u8 reserved_at_120[0x20]; 4872 4873 u8 rx_dct_connect[0x20]; 4874 4875 u8 reserved_at_160[0x20]; 4876 4877 u8 out_of_buffer[0x20]; 4878 4879 u8 reserved_at_1a0[0x20]; 4880 4881 u8 out_of_sequence[0x20]; 4882 4883 u8 reserved_at_1e0[0x20]; 4884 4885 u8 duplicate_request[0x20]; 4886 4887 u8 reserved_at_220[0x20]; 4888 4889 u8 rnr_nak_retry_err[0x20]; 4890 4891 u8 reserved_at_260[0x20]; 4892 4893 u8 packet_seq_err[0x20]; 4894 4895 u8 reserved_at_2a0[0x20]; 4896 4897 u8 implied_nak_seq_err[0x20]; 4898 4899 u8 reserved_at_2e0[0x20]; 4900 4901 u8 local_ack_timeout_err[0x20]; 4902 4903 u8 reserved_at_320[0xa0]; 4904 4905 u8 resp_local_length_error[0x20]; 4906 4907 u8 req_local_length_error[0x20]; 4908 4909 u8 resp_local_qp_error[0x20]; 4910 4911 u8 local_operation_error[0x20]; 4912 4913 u8 resp_local_protection[0x20]; 4914 4915 u8 req_local_protection[0x20]; 4916 4917 u8 resp_cqe_error[0x20]; 4918 4919 u8 req_cqe_error[0x20]; 4920 4921 u8 req_mw_binding[0x20]; 4922 4923 u8 req_bad_response[0x20]; 4924 4925 u8 req_remote_invalid_request[0x20]; 4926 4927 u8 resp_remote_invalid_request[0x20]; 4928 4929 u8 req_remote_access_errors[0x20]; 4930 4931 u8 resp_remote_access_errors[0x20]; 4932 4933 u8 req_remote_operation_errors[0x20]; 4934 4935 u8 req_transport_retries_exceeded[0x20]; 4936 4937 u8 cq_overflow[0x20]; 4938 4939 u8 resp_cqe_flush_error[0x20]; 4940 4941 u8 req_cqe_flush_error[0x20]; 4942 4943 u8 reserved_at_620[0x20]; 4944 4945 u8 roce_adp_retrans[0x20]; 4946 4947 u8 roce_adp_retrans_to[0x20]; 4948 4949 u8 roce_slow_restart[0x20]; 4950 4951 u8 roce_slow_restart_cnps[0x20]; 4952 4953 u8 roce_slow_restart_trans[0x20]; 4954 4955 u8 reserved_at_6e0[0x120]; 4956 }; 4957 4958 struct mlx5_ifc_query_q_counter_in_bits { 4959 u8 opcode[0x10]; 4960 u8 reserved_at_10[0x10]; 4961 4962 u8 reserved_at_20[0x10]; 4963 u8 op_mod[0x10]; 4964 4965 u8 reserved_at_40[0x80]; 4966 4967 u8 clear[0x1]; 4968 u8 reserved_at_c1[0x1f]; 4969 4970 u8 reserved_at_e0[0x18]; 4971 u8 counter_set_id[0x8]; 4972 }; 4973 4974 struct mlx5_ifc_query_pages_out_bits { 4975 u8 status[0x8]; 4976 u8 reserved_at_8[0x18]; 4977 4978 u8 syndrome[0x20]; 4979 4980 u8 embedded_cpu_function[0x1]; 4981 u8 reserved_at_41[0xf]; 4982 u8 function_id[0x10]; 4983 4984 u8 num_pages[0x20]; 4985 }; 4986 4987 enum { 4988 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4989 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4990 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4991 }; 4992 4993 struct mlx5_ifc_query_pages_in_bits { 4994 u8 opcode[0x10]; 4995 u8 reserved_at_10[0x10]; 4996 4997 u8 reserved_at_20[0x10]; 4998 u8 op_mod[0x10]; 4999 5000 u8 embedded_cpu_function[0x1]; 5001 u8 reserved_at_41[0xf]; 5002 u8 function_id[0x10]; 5003 5004 u8 reserved_at_60[0x20]; 5005 }; 5006 5007 struct mlx5_ifc_query_nic_vport_context_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_at_8[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_at_40[0x40]; 5014 5015 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5016 }; 5017 5018 struct mlx5_ifc_query_nic_vport_context_in_bits { 5019 u8 opcode[0x10]; 5020 u8 reserved_at_10[0x10]; 5021 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 other_vport[0x1]; 5026 u8 reserved_at_41[0xf]; 5027 u8 vport_number[0x10]; 5028 5029 u8 reserved_at_60[0x5]; 5030 u8 allowed_list_type[0x3]; 5031 u8 reserved_at_68[0x18]; 5032 }; 5033 5034 struct mlx5_ifc_query_mkey_out_bits { 5035 u8 status[0x8]; 5036 u8 reserved_at_8[0x18]; 5037 5038 u8 syndrome[0x20]; 5039 5040 u8 reserved_at_40[0x40]; 5041 5042 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5043 5044 u8 reserved_at_280[0x600]; 5045 5046 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5047 5048 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5049 }; 5050 5051 struct mlx5_ifc_query_mkey_in_bits { 5052 u8 opcode[0x10]; 5053 u8 reserved_at_10[0x10]; 5054 5055 u8 reserved_at_20[0x10]; 5056 u8 op_mod[0x10]; 5057 5058 u8 reserved_at_40[0x8]; 5059 u8 mkey_index[0x18]; 5060 5061 u8 pg_access[0x1]; 5062 u8 reserved_at_61[0x1f]; 5063 }; 5064 5065 struct mlx5_ifc_query_mad_demux_out_bits { 5066 u8 status[0x8]; 5067 u8 reserved_at_8[0x18]; 5068 5069 u8 syndrome[0x20]; 5070 5071 u8 reserved_at_40[0x40]; 5072 5073 u8 mad_dumux_parameters_block[0x20]; 5074 }; 5075 5076 struct mlx5_ifc_query_mad_demux_in_bits { 5077 u8 opcode[0x10]; 5078 u8 reserved_at_10[0x10]; 5079 5080 u8 reserved_at_20[0x10]; 5081 u8 op_mod[0x10]; 5082 5083 u8 reserved_at_40[0x40]; 5084 }; 5085 5086 struct mlx5_ifc_query_l2_table_entry_out_bits { 5087 u8 status[0x8]; 5088 u8 reserved_at_8[0x18]; 5089 5090 u8 syndrome[0x20]; 5091 5092 u8 reserved_at_40[0xa0]; 5093 5094 u8 reserved_at_e0[0x13]; 5095 u8 vlan_valid[0x1]; 5096 u8 vlan[0xc]; 5097 5098 struct mlx5_ifc_mac_address_layout_bits mac_address; 5099 5100 u8 reserved_at_140[0xc0]; 5101 }; 5102 5103 struct mlx5_ifc_query_l2_table_entry_in_bits { 5104 u8 opcode[0x10]; 5105 u8 reserved_at_10[0x10]; 5106 5107 u8 reserved_at_20[0x10]; 5108 u8 op_mod[0x10]; 5109 5110 u8 reserved_at_40[0x60]; 5111 5112 u8 reserved_at_a0[0x8]; 5113 u8 table_index[0x18]; 5114 5115 u8 reserved_at_c0[0x140]; 5116 }; 5117 5118 struct mlx5_ifc_query_issi_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x10]; 5125 u8 current_issi[0x10]; 5126 5127 u8 reserved_at_60[0xa0]; 5128 5129 u8 reserved_at_100[76][0x8]; 5130 u8 supported_issi_dw0[0x20]; 5131 }; 5132 5133 struct mlx5_ifc_query_issi_in_bits { 5134 u8 opcode[0x10]; 5135 u8 reserved_at_10[0x10]; 5136 5137 u8 reserved_at_20[0x10]; 5138 u8 op_mod[0x10]; 5139 5140 u8 reserved_at_40[0x40]; 5141 }; 5142 5143 struct mlx5_ifc_set_driver_version_out_bits { 5144 u8 status[0x8]; 5145 u8 reserved_0[0x18]; 5146 5147 u8 syndrome[0x20]; 5148 u8 reserved_1[0x40]; 5149 }; 5150 5151 struct mlx5_ifc_set_driver_version_in_bits { 5152 u8 opcode[0x10]; 5153 u8 reserved_0[0x10]; 5154 5155 u8 reserved_1[0x10]; 5156 u8 op_mod[0x10]; 5157 5158 u8 reserved_2[0x40]; 5159 u8 driver_version[64][0x8]; 5160 }; 5161 5162 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5163 u8 status[0x8]; 5164 u8 reserved_at_8[0x18]; 5165 5166 u8 syndrome[0x20]; 5167 5168 u8 reserved_at_40[0x40]; 5169 5170 struct mlx5_ifc_pkey_bits pkey[]; 5171 }; 5172 5173 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5174 u8 opcode[0x10]; 5175 u8 reserved_at_10[0x10]; 5176 5177 u8 reserved_at_20[0x10]; 5178 u8 op_mod[0x10]; 5179 5180 u8 other_vport[0x1]; 5181 u8 reserved_at_41[0xb]; 5182 u8 port_num[0x4]; 5183 u8 vport_number[0x10]; 5184 5185 u8 reserved_at_60[0x10]; 5186 u8 pkey_index[0x10]; 5187 }; 5188 5189 enum { 5190 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5191 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5192 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5193 }; 5194 5195 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5196 u8 status[0x8]; 5197 u8 reserved_at_8[0x18]; 5198 5199 u8 syndrome[0x20]; 5200 5201 u8 reserved_at_40[0x20]; 5202 5203 u8 gids_num[0x10]; 5204 u8 reserved_at_70[0x10]; 5205 5206 struct mlx5_ifc_array128_auto_bits gid[]; 5207 }; 5208 5209 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5210 u8 opcode[0x10]; 5211 u8 reserved_at_10[0x10]; 5212 5213 u8 reserved_at_20[0x10]; 5214 u8 op_mod[0x10]; 5215 5216 u8 other_vport[0x1]; 5217 u8 reserved_at_41[0xb]; 5218 u8 port_num[0x4]; 5219 u8 vport_number[0x10]; 5220 5221 u8 reserved_at_60[0x10]; 5222 u8 gid_index[0x10]; 5223 }; 5224 5225 struct mlx5_ifc_query_hca_vport_context_out_bits { 5226 u8 status[0x8]; 5227 u8 reserved_at_8[0x18]; 5228 5229 u8 syndrome[0x20]; 5230 5231 u8 reserved_at_40[0x40]; 5232 5233 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5234 }; 5235 5236 struct mlx5_ifc_query_hca_vport_context_in_bits { 5237 u8 opcode[0x10]; 5238 u8 reserved_at_10[0x10]; 5239 5240 u8 reserved_at_20[0x10]; 5241 u8 op_mod[0x10]; 5242 5243 u8 other_vport[0x1]; 5244 u8 reserved_at_41[0xb]; 5245 u8 port_num[0x4]; 5246 u8 vport_number[0x10]; 5247 5248 u8 reserved_at_60[0x20]; 5249 }; 5250 5251 struct mlx5_ifc_query_hca_cap_out_bits { 5252 u8 status[0x8]; 5253 u8 reserved_at_8[0x18]; 5254 5255 u8 syndrome[0x20]; 5256 5257 u8 reserved_at_40[0x40]; 5258 5259 union mlx5_ifc_hca_cap_union_bits capability; 5260 }; 5261 5262 struct mlx5_ifc_query_hca_cap_in_bits { 5263 u8 opcode[0x10]; 5264 u8 reserved_at_10[0x10]; 5265 5266 u8 reserved_at_20[0x10]; 5267 u8 op_mod[0x10]; 5268 5269 u8 other_function[0x1]; 5270 u8 reserved_at_41[0xf]; 5271 u8 function_id[0x10]; 5272 5273 u8 reserved_at_60[0x20]; 5274 }; 5275 5276 struct mlx5_ifc_other_hca_cap_bits { 5277 u8 roce[0x1]; 5278 u8 reserved_at_1[0x27f]; 5279 }; 5280 5281 struct mlx5_ifc_query_other_hca_cap_out_bits { 5282 u8 status[0x8]; 5283 u8 reserved_at_8[0x18]; 5284 5285 u8 syndrome[0x20]; 5286 5287 u8 reserved_at_40[0x40]; 5288 5289 struct mlx5_ifc_other_hca_cap_bits other_capability; 5290 }; 5291 5292 struct mlx5_ifc_query_other_hca_cap_in_bits { 5293 u8 opcode[0x10]; 5294 u8 reserved_at_10[0x10]; 5295 5296 u8 reserved_at_20[0x10]; 5297 u8 op_mod[0x10]; 5298 5299 u8 reserved_at_40[0x10]; 5300 u8 function_id[0x10]; 5301 5302 u8 reserved_at_60[0x20]; 5303 }; 5304 5305 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5306 u8 status[0x8]; 5307 u8 reserved_at_8[0x18]; 5308 5309 u8 syndrome[0x20]; 5310 5311 u8 reserved_at_40[0x40]; 5312 }; 5313 5314 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5315 u8 opcode[0x10]; 5316 u8 reserved_at_10[0x10]; 5317 5318 u8 reserved_at_20[0x10]; 5319 u8 op_mod[0x10]; 5320 5321 u8 reserved_at_40[0x10]; 5322 u8 function_id[0x10]; 5323 u8 field_select[0x20]; 5324 5325 struct mlx5_ifc_other_hca_cap_bits other_capability; 5326 }; 5327 5328 struct mlx5_ifc_flow_table_context_bits { 5329 u8 reformat_en[0x1]; 5330 u8 decap_en[0x1]; 5331 u8 sw_owner[0x1]; 5332 u8 termination_table[0x1]; 5333 u8 table_miss_action[0x4]; 5334 u8 level[0x8]; 5335 u8 reserved_at_10[0x8]; 5336 u8 log_size[0x8]; 5337 5338 u8 reserved_at_20[0x8]; 5339 u8 table_miss_id[0x18]; 5340 5341 u8 reserved_at_40[0x8]; 5342 u8 lag_master_next_table_id[0x18]; 5343 5344 u8 reserved_at_60[0x60]; 5345 5346 u8 sw_owner_icm_root_1[0x40]; 5347 5348 u8 sw_owner_icm_root_0[0x40]; 5349 5350 }; 5351 5352 struct mlx5_ifc_query_flow_table_out_bits { 5353 u8 status[0x8]; 5354 u8 reserved_at_8[0x18]; 5355 5356 u8 syndrome[0x20]; 5357 5358 u8 reserved_at_40[0x80]; 5359 5360 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5361 }; 5362 5363 struct mlx5_ifc_query_flow_table_in_bits { 5364 u8 opcode[0x10]; 5365 u8 reserved_at_10[0x10]; 5366 5367 u8 reserved_at_20[0x10]; 5368 u8 op_mod[0x10]; 5369 5370 u8 reserved_at_40[0x40]; 5371 5372 u8 table_type[0x8]; 5373 u8 reserved_at_88[0x18]; 5374 5375 u8 reserved_at_a0[0x8]; 5376 u8 table_id[0x18]; 5377 5378 u8 reserved_at_c0[0x140]; 5379 }; 5380 5381 struct mlx5_ifc_query_fte_out_bits { 5382 u8 status[0x8]; 5383 u8 reserved_at_8[0x18]; 5384 5385 u8 syndrome[0x20]; 5386 5387 u8 reserved_at_40[0x1c0]; 5388 5389 struct mlx5_ifc_flow_context_bits flow_context; 5390 }; 5391 5392 struct mlx5_ifc_query_fte_in_bits { 5393 u8 opcode[0x10]; 5394 u8 reserved_at_10[0x10]; 5395 5396 u8 reserved_at_20[0x10]; 5397 u8 op_mod[0x10]; 5398 5399 u8 reserved_at_40[0x40]; 5400 5401 u8 table_type[0x8]; 5402 u8 reserved_at_88[0x18]; 5403 5404 u8 reserved_at_a0[0x8]; 5405 u8 table_id[0x18]; 5406 5407 u8 reserved_at_c0[0x40]; 5408 5409 u8 flow_index[0x20]; 5410 5411 u8 reserved_at_120[0xe0]; 5412 }; 5413 5414 enum { 5415 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5416 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5417 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5418 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5419 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5420 }; 5421 5422 struct mlx5_ifc_query_flow_group_out_bits { 5423 u8 status[0x8]; 5424 u8 reserved_at_8[0x18]; 5425 5426 u8 syndrome[0x20]; 5427 5428 u8 reserved_at_40[0xa0]; 5429 5430 u8 start_flow_index[0x20]; 5431 5432 u8 reserved_at_100[0x20]; 5433 5434 u8 end_flow_index[0x20]; 5435 5436 u8 reserved_at_140[0xa0]; 5437 5438 u8 reserved_at_1e0[0x18]; 5439 u8 match_criteria_enable[0x8]; 5440 5441 struct mlx5_ifc_fte_match_param_bits match_criteria; 5442 5443 u8 reserved_at_1200[0xe00]; 5444 }; 5445 5446 struct mlx5_ifc_query_flow_group_in_bits { 5447 u8 opcode[0x10]; 5448 u8 reserved_at_10[0x10]; 5449 5450 u8 reserved_at_20[0x10]; 5451 u8 op_mod[0x10]; 5452 5453 u8 reserved_at_40[0x40]; 5454 5455 u8 table_type[0x8]; 5456 u8 reserved_at_88[0x18]; 5457 5458 u8 reserved_at_a0[0x8]; 5459 u8 table_id[0x18]; 5460 5461 u8 group_id[0x20]; 5462 5463 u8 reserved_at_e0[0x120]; 5464 }; 5465 5466 struct mlx5_ifc_query_flow_counter_out_bits { 5467 u8 status[0x8]; 5468 u8 reserved_at_8[0x18]; 5469 5470 u8 syndrome[0x20]; 5471 5472 u8 reserved_at_40[0x40]; 5473 5474 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5475 }; 5476 5477 struct mlx5_ifc_query_flow_counter_in_bits { 5478 u8 opcode[0x10]; 5479 u8 reserved_at_10[0x10]; 5480 5481 u8 reserved_at_20[0x10]; 5482 u8 op_mod[0x10]; 5483 5484 u8 reserved_at_40[0x80]; 5485 5486 u8 clear[0x1]; 5487 u8 reserved_at_c1[0xf]; 5488 u8 num_of_counters[0x10]; 5489 5490 u8 flow_counter_id[0x20]; 5491 }; 5492 5493 struct mlx5_ifc_query_esw_vport_context_out_bits { 5494 u8 status[0x8]; 5495 u8 reserved_at_8[0x18]; 5496 5497 u8 syndrome[0x20]; 5498 5499 u8 reserved_at_40[0x40]; 5500 5501 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5502 }; 5503 5504 struct mlx5_ifc_query_esw_vport_context_in_bits { 5505 u8 opcode[0x10]; 5506 u8 reserved_at_10[0x10]; 5507 5508 u8 reserved_at_20[0x10]; 5509 u8 op_mod[0x10]; 5510 5511 u8 other_vport[0x1]; 5512 u8 reserved_at_41[0xf]; 5513 u8 vport_number[0x10]; 5514 5515 u8 reserved_at_60[0x20]; 5516 }; 5517 5518 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5519 u8 status[0x8]; 5520 u8 reserved_at_8[0x18]; 5521 5522 u8 syndrome[0x20]; 5523 5524 u8 reserved_at_40[0x40]; 5525 }; 5526 5527 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5528 u8 reserved_at_0[0x1b]; 5529 u8 fdb_to_vport_reg_c_id[0x1]; 5530 u8 vport_cvlan_insert[0x1]; 5531 u8 vport_svlan_insert[0x1]; 5532 u8 vport_cvlan_strip[0x1]; 5533 u8 vport_svlan_strip[0x1]; 5534 }; 5535 5536 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5537 u8 opcode[0x10]; 5538 u8 reserved_at_10[0x10]; 5539 5540 u8 reserved_at_20[0x10]; 5541 u8 op_mod[0x10]; 5542 5543 u8 other_vport[0x1]; 5544 u8 reserved_at_41[0xf]; 5545 u8 vport_number[0x10]; 5546 5547 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5548 5549 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5550 }; 5551 5552 struct mlx5_ifc_query_eq_out_bits { 5553 u8 status[0x8]; 5554 u8 reserved_at_8[0x18]; 5555 5556 u8 syndrome[0x20]; 5557 5558 u8 reserved_at_40[0x40]; 5559 5560 struct mlx5_ifc_eqc_bits eq_context_entry; 5561 5562 u8 reserved_at_280[0x40]; 5563 5564 u8 event_bitmask[0x40]; 5565 5566 u8 reserved_at_300[0x580]; 5567 5568 u8 pas[][0x40]; 5569 }; 5570 5571 struct mlx5_ifc_query_eq_in_bits { 5572 u8 opcode[0x10]; 5573 u8 reserved_at_10[0x10]; 5574 5575 u8 reserved_at_20[0x10]; 5576 u8 op_mod[0x10]; 5577 5578 u8 reserved_at_40[0x18]; 5579 u8 eq_number[0x8]; 5580 5581 u8 reserved_at_60[0x20]; 5582 }; 5583 5584 struct mlx5_ifc_packet_reformat_context_in_bits { 5585 u8 reserved_at_0[0x5]; 5586 u8 reformat_type[0x3]; 5587 u8 reserved_at_8[0xe]; 5588 u8 reformat_data_size[0xa]; 5589 5590 u8 reserved_at_20[0x10]; 5591 u8 reformat_data[2][0x8]; 5592 5593 u8 more_reformat_data[][0x8]; 5594 }; 5595 5596 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5597 u8 status[0x8]; 5598 u8 reserved_at_8[0x18]; 5599 5600 u8 syndrome[0x20]; 5601 5602 u8 reserved_at_40[0xa0]; 5603 5604 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5605 }; 5606 5607 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5608 u8 opcode[0x10]; 5609 u8 reserved_at_10[0x10]; 5610 5611 u8 reserved_at_20[0x10]; 5612 u8 op_mod[0x10]; 5613 5614 u8 packet_reformat_id[0x20]; 5615 5616 u8 reserved_at_60[0xa0]; 5617 }; 5618 5619 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5620 u8 status[0x8]; 5621 u8 reserved_at_8[0x18]; 5622 5623 u8 syndrome[0x20]; 5624 5625 u8 packet_reformat_id[0x20]; 5626 5627 u8 reserved_at_60[0x20]; 5628 }; 5629 5630 enum mlx5_reformat_ctx_type { 5631 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5632 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5633 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5634 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5635 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5636 }; 5637 5638 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5639 u8 opcode[0x10]; 5640 u8 reserved_at_10[0x10]; 5641 5642 u8 reserved_at_20[0x10]; 5643 u8 op_mod[0x10]; 5644 5645 u8 reserved_at_40[0xa0]; 5646 5647 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5648 }; 5649 5650 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5651 u8 status[0x8]; 5652 u8 reserved_at_8[0x18]; 5653 5654 u8 syndrome[0x20]; 5655 5656 u8 reserved_at_40[0x40]; 5657 }; 5658 5659 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5660 u8 opcode[0x10]; 5661 u8 reserved_at_10[0x10]; 5662 5663 u8 reserved_20[0x10]; 5664 u8 op_mod[0x10]; 5665 5666 u8 packet_reformat_id[0x20]; 5667 5668 u8 reserved_60[0x20]; 5669 }; 5670 5671 struct mlx5_ifc_set_action_in_bits { 5672 u8 action_type[0x4]; 5673 u8 field[0xc]; 5674 u8 reserved_at_10[0x3]; 5675 u8 offset[0x5]; 5676 u8 reserved_at_18[0x3]; 5677 u8 length[0x5]; 5678 5679 u8 data[0x20]; 5680 }; 5681 5682 struct mlx5_ifc_add_action_in_bits { 5683 u8 action_type[0x4]; 5684 u8 field[0xc]; 5685 u8 reserved_at_10[0x10]; 5686 5687 u8 data[0x20]; 5688 }; 5689 5690 struct mlx5_ifc_copy_action_in_bits { 5691 u8 action_type[0x4]; 5692 u8 src_field[0xc]; 5693 u8 reserved_at_10[0x3]; 5694 u8 src_offset[0x5]; 5695 u8 reserved_at_18[0x3]; 5696 u8 length[0x5]; 5697 5698 u8 reserved_at_20[0x4]; 5699 u8 dst_field[0xc]; 5700 u8 reserved_at_30[0x3]; 5701 u8 dst_offset[0x5]; 5702 u8 reserved_at_38[0x8]; 5703 }; 5704 5705 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5706 struct mlx5_ifc_set_action_in_bits set_action_in; 5707 struct mlx5_ifc_add_action_in_bits add_action_in; 5708 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5709 u8 reserved_at_0[0x40]; 5710 }; 5711 5712 enum { 5713 MLX5_ACTION_TYPE_SET = 0x1, 5714 MLX5_ACTION_TYPE_ADD = 0x2, 5715 MLX5_ACTION_TYPE_COPY = 0x3, 5716 }; 5717 5718 enum { 5719 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5720 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5721 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5722 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5723 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5724 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5725 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5726 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5727 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5728 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5729 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5730 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5731 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5732 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5733 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5734 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5735 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5736 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5737 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5738 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5739 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5740 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5741 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5742 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5743 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5744 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5745 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5746 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5747 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5748 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5749 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5750 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5751 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5752 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5753 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5754 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5755 }; 5756 5757 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5758 u8 status[0x8]; 5759 u8 reserved_at_8[0x18]; 5760 5761 u8 syndrome[0x20]; 5762 5763 u8 modify_header_id[0x20]; 5764 5765 u8 reserved_at_60[0x20]; 5766 }; 5767 5768 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5769 u8 opcode[0x10]; 5770 u8 reserved_at_10[0x10]; 5771 5772 u8 reserved_at_20[0x10]; 5773 u8 op_mod[0x10]; 5774 5775 u8 reserved_at_40[0x20]; 5776 5777 u8 table_type[0x8]; 5778 u8 reserved_at_68[0x10]; 5779 u8 num_of_actions[0x8]; 5780 5781 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0]; 5782 }; 5783 5784 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5785 u8 status[0x8]; 5786 u8 reserved_at_8[0x18]; 5787 5788 u8 syndrome[0x20]; 5789 5790 u8 reserved_at_40[0x40]; 5791 }; 5792 5793 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5794 u8 opcode[0x10]; 5795 u8 reserved_at_10[0x10]; 5796 5797 u8 reserved_at_20[0x10]; 5798 u8 op_mod[0x10]; 5799 5800 u8 modify_header_id[0x20]; 5801 5802 u8 reserved_at_60[0x20]; 5803 }; 5804 5805 struct mlx5_ifc_query_dct_out_bits { 5806 u8 status[0x8]; 5807 u8 reserved_at_8[0x18]; 5808 5809 u8 syndrome[0x20]; 5810 5811 u8 reserved_at_40[0x40]; 5812 5813 struct mlx5_ifc_dctc_bits dct_context_entry; 5814 5815 u8 reserved_at_280[0x180]; 5816 }; 5817 5818 struct mlx5_ifc_query_dct_in_bits { 5819 u8 opcode[0x10]; 5820 u8 reserved_at_10[0x10]; 5821 5822 u8 reserved_at_20[0x10]; 5823 u8 op_mod[0x10]; 5824 5825 u8 reserved_at_40[0x8]; 5826 u8 dctn[0x18]; 5827 5828 u8 reserved_at_60[0x20]; 5829 }; 5830 5831 struct mlx5_ifc_query_cq_out_bits { 5832 u8 status[0x8]; 5833 u8 reserved_at_8[0x18]; 5834 5835 u8 syndrome[0x20]; 5836 5837 u8 reserved_at_40[0x40]; 5838 5839 struct mlx5_ifc_cqc_bits cq_context; 5840 5841 u8 reserved_at_280[0x600]; 5842 5843 u8 pas[][0x40]; 5844 }; 5845 5846 struct mlx5_ifc_query_cq_in_bits { 5847 u8 opcode[0x10]; 5848 u8 reserved_at_10[0x10]; 5849 5850 u8 reserved_at_20[0x10]; 5851 u8 op_mod[0x10]; 5852 5853 u8 reserved_at_40[0x8]; 5854 u8 cqn[0x18]; 5855 5856 u8 reserved_at_60[0x20]; 5857 }; 5858 5859 struct mlx5_ifc_query_cong_status_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_at_8[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_at_40[0x20]; 5866 5867 u8 enable[0x1]; 5868 u8 tag_enable[0x1]; 5869 u8 reserved_at_62[0x1e]; 5870 }; 5871 5872 struct mlx5_ifc_query_cong_status_in_bits { 5873 u8 opcode[0x10]; 5874 u8 reserved_at_10[0x10]; 5875 5876 u8 reserved_at_20[0x10]; 5877 u8 op_mod[0x10]; 5878 5879 u8 reserved_at_40[0x18]; 5880 u8 priority[0x4]; 5881 u8 cong_protocol[0x4]; 5882 5883 u8 reserved_at_60[0x20]; 5884 }; 5885 5886 struct mlx5_ifc_query_cong_statistics_out_bits { 5887 u8 status[0x8]; 5888 u8 reserved_at_8[0x18]; 5889 5890 u8 syndrome[0x20]; 5891 5892 u8 reserved_at_40[0x40]; 5893 5894 u8 rp_cur_flows[0x20]; 5895 5896 u8 sum_flows[0x20]; 5897 5898 u8 rp_cnp_ignored_high[0x20]; 5899 5900 u8 rp_cnp_ignored_low[0x20]; 5901 5902 u8 rp_cnp_handled_high[0x20]; 5903 5904 u8 rp_cnp_handled_low[0x20]; 5905 5906 u8 reserved_at_140[0x100]; 5907 5908 u8 time_stamp_high[0x20]; 5909 5910 u8 time_stamp_low[0x20]; 5911 5912 u8 accumulators_period[0x20]; 5913 5914 u8 np_ecn_marked_roce_packets_high[0x20]; 5915 5916 u8 np_ecn_marked_roce_packets_low[0x20]; 5917 5918 u8 np_cnp_sent_high[0x20]; 5919 5920 u8 np_cnp_sent_low[0x20]; 5921 5922 u8 reserved_at_320[0x560]; 5923 }; 5924 5925 struct mlx5_ifc_query_cong_statistics_in_bits { 5926 u8 opcode[0x10]; 5927 u8 reserved_at_10[0x10]; 5928 5929 u8 reserved_at_20[0x10]; 5930 u8 op_mod[0x10]; 5931 5932 u8 clear[0x1]; 5933 u8 reserved_at_41[0x1f]; 5934 5935 u8 reserved_at_60[0x20]; 5936 }; 5937 5938 struct mlx5_ifc_query_cong_params_out_bits { 5939 u8 status[0x8]; 5940 u8 reserved_at_8[0x18]; 5941 5942 u8 syndrome[0x20]; 5943 5944 u8 reserved_at_40[0x40]; 5945 5946 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5947 }; 5948 5949 struct mlx5_ifc_query_cong_params_in_bits { 5950 u8 opcode[0x10]; 5951 u8 reserved_at_10[0x10]; 5952 5953 u8 reserved_at_20[0x10]; 5954 u8 op_mod[0x10]; 5955 5956 u8 reserved_at_40[0x1c]; 5957 u8 cong_protocol[0x4]; 5958 5959 u8 reserved_at_60[0x20]; 5960 }; 5961 5962 struct mlx5_ifc_query_adapter_out_bits { 5963 u8 status[0x8]; 5964 u8 reserved_at_8[0x18]; 5965 5966 u8 syndrome[0x20]; 5967 5968 u8 reserved_at_40[0x40]; 5969 5970 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5971 }; 5972 5973 struct mlx5_ifc_query_adapter_in_bits { 5974 u8 opcode[0x10]; 5975 u8 reserved_at_10[0x10]; 5976 5977 u8 reserved_at_20[0x10]; 5978 u8 op_mod[0x10]; 5979 5980 u8 reserved_at_40[0x40]; 5981 }; 5982 5983 struct mlx5_ifc_qp_2rst_out_bits { 5984 u8 status[0x8]; 5985 u8 reserved_at_8[0x18]; 5986 5987 u8 syndrome[0x20]; 5988 5989 u8 reserved_at_40[0x40]; 5990 }; 5991 5992 struct mlx5_ifc_qp_2rst_in_bits { 5993 u8 opcode[0x10]; 5994 u8 uid[0x10]; 5995 5996 u8 reserved_at_20[0x10]; 5997 u8 op_mod[0x10]; 5998 5999 u8 reserved_at_40[0x8]; 6000 u8 qpn[0x18]; 6001 6002 u8 reserved_at_60[0x20]; 6003 }; 6004 6005 struct mlx5_ifc_qp_2err_out_bits { 6006 u8 status[0x8]; 6007 u8 reserved_at_8[0x18]; 6008 6009 u8 syndrome[0x20]; 6010 6011 u8 reserved_at_40[0x40]; 6012 }; 6013 6014 struct mlx5_ifc_qp_2err_in_bits { 6015 u8 opcode[0x10]; 6016 u8 uid[0x10]; 6017 6018 u8 reserved_at_20[0x10]; 6019 u8 op_mod[0x10]; 6020 6021 u8 reserved_at_40[0x8]; 6022 u8 qpn[0x18]; 6023 6024 u8 reserved_at_60[0x20]; 6025 }; 6026 6027 struct mlx5_ifc_page_fault_resume_out_bits { 6028 u8 status[0x8]; 6029 u8 reserved_at_8[0x18]; 6030 6031 u8 syndrome[0x20]; 6032 6033 u8 reserved_at_40[0x40]; 6034 }; 6035 6036 struct mlx5_ifc_page_fault_resume_in_bits { 6037 u8 opcode[0x10]; 6038 u8 reserved_at_10[0x10]; 6039 6040 u8 reserved_at_20[0x10]; 6041 u8 op_mod[0x10]; 6042 6043 u8 error[0x1]; 6044 u8 reserved_at_41[0x4]; 6045 u8 page_fault_type[0x3]; 6046 u8 wq_number[0x18]; 6047 6048 u8 reserved_at_60[0x8]; 6049 u8 token[0x18]; 6050 }; 6051 6052 struct mlx5_ifc_nop_out_bits { 6053 u8 status[0x8]; 6054 u8 reserved_at_8[0x18]; 6055 6056 u8 syndrome[0x20]; 6057 6058 u8 reserved_at_40[0x40]; 6059 }; 6060 6061 struct mlx5_ifc_nop_in_bits { 6062 u8 opcode[0x10]; 6063 u8 reserved_at_10[0x10]; 6064 6065 u8 reserved_at_20[0x10]; 6066 u8 op_mod[0x10]; 6067 6068 u8 reserved_at_40[0x40]; 6069 }; 6070 6071 struct mlx5_ifc_modify_vport_state_out_bits { 6072 u8 status[0x8]; 6073 u8 reserved_at_8[0x18]; 6074 6075 u8 syndrome[0x20]; 6076 6077 u8 reserved_at_40[0x40]; 6078 }; 6079 6080 struct mlx5_ifc_modify_vport_state_in_bits { 6081 u8 opcode[0x10]; 6082 u8 reserved_at_10[0x10]; 6083 6084 u8 reserved_at_20[0x10]; 6085 u8 op_mod[0x10]; 6086 6087 u8 other_vport[0x1]; 6088 u8 reserved_at_41[0xf]; 6089 u8 vport_number[0x10]; 6090 6091 u8 reserved_at_60[0x18]; 6092 u8 admin_state[0x4]; 6093 u8 reserved_at_7c[0x4]; 6094 }; 6095 6096 struct mlx5_ifc_modify_tis_out_bits { 6097 u8 status[0x8]; 6098 u8 reserved_at_8[0x18]; 6099 6100 u8 syndrome[0x20]; 6101 6102 u8 reserved_at_40[0x40]; 6103 }; 6104 6105 struct mlx5_ifc_modify_tis_bitmask_bits { 6106 u8 reserved_at_0[0x20]; 6107 6108 u8 reserved_at_20[0x1d]; 6109 u8 lag_tx_port_affinity[0x1]; 6110 u8 strict_lag_tx_port_affinity[0x1]; 6111 u8 prio[0x1]; 6112 }; 6113 6114 struct mlx5_ifc_modify_tis_in_bits { 6115 u8 opcode[0x10]; 6116 u8 uid[0x10]; 6117 6118 u8 reserved_at_20[0x10]; 6119 u8 op_mod[0x10]; 6120 6121 u8 reserved_at_40[0x8]; 6122 u8 tisn[0x18]; 6123 6124 u8 reserved_at_60[0x20]; 6125 6126 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6127 6128 u8 reserved_at_c0[0x40]; 6129 6130 struct mlx5_ifc_tisc_bits ctx; 6131 }; 6132 6133 struct mlx5_ifc_modify_tir_bitmask_bits { 6134 u8 reserved_at_0[0x20]; 6135 6136 u8 reserved_at_20[0x1b]; 6137 u8 self_lb_en[0x1]; 6138 u8 reserved_at_3c[0x1]; 6139 u8 hash[0x1]; 6140 u8 reserved_at_3e[0x1]; 6141 u8 lro[0x1]; 6142 }; 6143 6144 struct mlx5_ifc_modify_tir_out_bits { 6145 u8 status[0x8]; 6146 u8 reserved_at_8[0x18]; 6147 6148 u8 syndrome[0x20]; 6149 6150 u8 reserved_at_40[0x40]; 6151 }; 6152 6153 struct mlx5_ifc_modify_tir_in_bits { 6154 u8 opcode[0x10]; 6155 u8 uid[0x10]; 6156 6157 u8 reserved_at_20[0x10]; 6158 u8 op_mod[0x10]; 6159 6160 u8 reserved_at_40[0x8]; 6161 u8 tirn[0x18]; 6162 6163 u8 reserved_at_60[0x20]; 6164 6165 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6166 6167 u8 reserved_at_c0[0x40]; 6168 6169 struct mlx5_ifc_tirc_bits ctx; 6170 }; 6171 6172 struct mlx5_ifc_modify_sq_out_bits { 6173 u8 status[0x8]; 6174 u8 reserved_at_8[0x18]; 6175 6176 u8 syndrome[0x20]; 6177 6178 u8 reserved_at_40[0x40]; 6179 }; 6180 6181 struct mlx5_ifc_modify_sq_in_bits { 6182 u8 opcode[0x10]; 6183 u8 uid[0x10]; 6184 6185 u8 reserved_at_20[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 sq_state[0x4]; 6189 u8 reserved_at_44[0x4]; 6190 u8 sqn[0x18]; 6191 6192 u8 reserved_at_60[0x20]; 6193 6194 u8 modify_bitmask[0x40]; 6195 6196 u8 reserved_at_c0[0x40]; 6197 6198 struct mlx5_ifc_sqc_bits ctx; 6199 }; 6200 6201 struct mlx5_ifc_modify_scheduling_element_out_bits { 6202 u8 status[0x8]; 6203 u8 reserved_at_8[0x18]; 6204 6205 u8 syndrome[0x20]; 6206 6207 u8 reserved_at_40[0x1c0]; 6208 }; 6209 6210 enum { 6211 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6212 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6213 }; 6214 6215 struct mlx5_ifc_modify_scheduling_element_in_bits { 6216 u8 opcode[0x10]; 6217 u8 reserved_at_10[0x10]; 6218 6219 u8 reserved_at_20[0x10]; 6220 u8 op_mod[0x10]; 6221 6222 u8 scheduling_hierarchy[0x8]; 6223 u8 reserved_at_48[0x18]; 6224 6225 u8 scheduling_element_id[0x20]; 6226 6227 u8 reserved_at_80[0x20]; 6228 6229 u8 modify_bitmask[0x20]; 6230 6231 u8 reserved_at_c0[0x40]; 6232 6233 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6234 6235 u8 reserved_at_300[0x100]; 6236 }; 6237 6238 struct mlx5_ifc_modify_rqt_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 }; 6246 6247 struct mlx5_ifc_rqt_bitmask_bits { 6248 u8 reserved_at_0[0x20]; 6249 6250 u8 reserved_at_20[0x1f]; 6251 u8 rqn_list[0x1]; 6252 }; 6253 6254 struct mlx5_ifc_modify_rqt_in_bits { 6255 u8 opcode[0x10]; 6256 u8 uid[0x10]; 6257 6258 u8 reserved_at_20[0x10]; 6259 u8 op_mod[0x10]; 6260 6261 u8 reserved_at_40[0x8]; 6262 u8 rqtn[0x18]; 6263 6264 u8 reserved_at_60[0x20]; 6265 6266 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6267 6268 u8 reserved_at_c0[0x40]; 6269 6270 struct mlx5_ifc_rqtc_bits ctx; 6271 }; 6272 6273 struct mlx5_ifc_modify_rq_out_bits { 6274 u8 status[0x8]; 6275 u8 reserved_at_8[0x18]; 6276 6277 u8 syndrome[0x20]; 6278 6279 u8 reserved_at_40[0x40]; 6280 }; 6281 6282 enum { 6283 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6284 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6285 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6286 }; 6287 6288 struct mlx5_ifc_modify_rq_in_bits { 6289 u8 opcode[0x10]; 6290 u8 uid[0x10]; 6291 6292 u8 reserved_at_20[0x10]; 6293 u8 op_mod[0x10]; 6294 6295 u8 rq_state[0x4]; 6296 u8 reserved_at_44[0x4]; 6297 u8 rqn[0x18]; 6298 6299 u8 reserved_at_60[0x20]; 6300 6301 u8 modify_bitmask[0x40]; 6302 6303 u8 reserved_at_c0[0x40]; 6304 6305 struct mlx5_ifc_rqc_bits ctx; 6306 }; 6307 6308 struct mlx5_ifc_modify_rmp_out_bits { 6309 u8 status[0x8]; 6310 u8 reserved_at_8[0x18]; 6311 6312 u8 syndrome[0x20]; 6313 6314 u8 reserved_at_40[0x40]; 6315 }; 6316 6317 struct mlx5_ifc_rmp_bitmask_bits { 6318 u8 reserved_at_0[0x20]; 6319 6320 u8 reserved_at_20[0x1f]; 6321 u8 lwm[0x1]; 6322 }; 6323 6324 struct mlx5_ifc_modify_rmp_in_bits { 6325 u8 opcode[0x10]; 6326 u8 uid[0x10]; 6327 6328 u8 reserved_at_20[0x10]; 6329 u8 op_mod[0x10]; 6330 6331 u8 rmp_state[0x4]; 6332 u8 reserved_at_44[0x4]; 6333 u8 rmpn[0x18]; 6334 6335 u8 reserved_at_60[0x20]; 6336 6337 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6338 6339 u8 reserved_at_c0[0x40]; 6340 6341 struct mlx5_ifc_rmpc_bits ctx; 6342 }; 6343 6344 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6345 u8 status[0x8]; 6346 u8 reserved_at_8[0x18]; 6347 6348 u8 syndrome[0x20]; 6349 6350 u8 reserved_at_40[0x40]; 6351 }; 6352 6353 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6354 u8 reserved_at_0[0x12]; 6355 u8 affiliation[0x1]; 6356 u8 reserved_at_13[0x1]; 6357 u8 disable_uc_local_lb[0x1]; 6358 u8 disable_mc_local_lb[0x1]; 6359 u8 node_guid[0x1]; 6360 u8 port_guid[0x1]; 6361 u8 min_inline[0x1]; 6362 u8 mtu[0x1]; 6363 u8 change_event[0x1]; 6364 u8 promisc[0x1]; 6365 u8 permanent_address[0x1]; 6366 u8 addresses_list[0x1]; 6367 u8 roce_en[0x1]; 6368 u8 reserved_at_1f[0x1]; 6369 }; 6370 6371 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6372 u8 opcode[0x10]; 6373 u8 reserved_at_10[0x10]; 6374 6375 u8 reserved_at_20[0x10]; 6376 u8 op_mod[0x10]; 6377 6378 u8 other_vport[0x1]; 6379 u8 reserved_at_41[0xf]; 6380 u8 vport_number[0x10]; 6381 6382 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6383 6384 u8 reserved_at_80[0x780]; 6385 6386 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6387 }; 6388 6389 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6390 u8 status[0x8]; 6391 u8 reserved_at_8[0x18]; 6392 6393 u8 syndrome[0x20]; 6394 6395 u8 reserved_at_40[0x40]; 6396 }; 6397 6398 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6399 u8 opcode[0x10]; 6400 u8 reserved_at_10[0x10]; 6401 6402 u8 reserved_at_20[0x10]; 6403 u8 op_mod[0x10]; 6404 6405 u8 other_vport[0x1]; 6406 u8 reserved_at_41[0xb]; 6407 u8 port_num[0x4]; 6408 u8 vport_number[0x10]; 6409 6410 u8 reserved_at_60[0x20]; 6411 6412 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6413 }; 6414 6415 struct mlx5_ifc_modify_cq_out_bits { 6416 u8 status[0x8]; 6417 u8 reserved_at_8[0x18]; 6418 6419 u8 syndrome[0x20]; 6420 6421 u8 reserved_at_40[0x40]; 6422 }; 6423 6424 enum { 6425 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6426 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6427 }; 6428 6429 struct mlx5_ifc_modify_cq_in_bits { 6430 u8 opcode[0x10]; 6431 u8 uid[0x10]; 6432 6433 u8 reserved_at_20[0x10]; 6434 u8 op_mod[0x10]; 6435 6436 u8 reserved_at_40[0x8]; 6437 u8 cqn[0x18]; 6438 6439 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6440 6441 struct mlx5_ifc_cqc_bits cq_context; 6442 6443 u8 reserved_at_280[0x60]; 6444 6445 u8 cq_umem_valid[0x1]; 6446 u8 reserved_at_2e1[0x1f]; 6447 6448 u8 reserved_at_300[0x580]; 6449 6450 u8 pas[][0x40]; 6451 }; 6452 6453 struct mlx5_ifc_modify_cong_status_out_bits { 6454 u8 status[0x8]; 6455 u8 reserved_at_8[0x18]; 6456 6457 u8 syndrome[0x20]; 6458 6459 u8 reserved_at_40[0x40]; 6460 }; 6461 6462 struct mlx5_ifc_modify_cong_status_in_bits { 6463 u8 opcode[0x10]; 6464 u8 reserved_at_10[0x10]; 6465 6466 u8 reserved_at_20[0x10]; 6467 u8 op_mod[0x10]; 6468 6469 u8 reserved_at_40[0x18]; 6470 u8 priority[0x4]; 6471 u8 cong_protocol[0x4]; 6472 6473 u8 enable[0x1]; 6474 u8 tag_enable[0x1]; 6475 u8 reserved_at_62[0x1e]; 6476 }; 6477 6478 struct mlx5_ifc_modify_cong_params_out_bits { 6479 u8 status[0x8]; 6480 u8 reserved_at_8[0x18]; 6481 6482 u8 syndrome[0x20]; 6483 6484 u8 reserved_at_40[0x40]; 6485 }; 6486 6487 struct mlx5_ifc_modify_cong_params_in_bits { 6488 u8 opcode[0x10]; 6489 u8 reserved_at_10[0x10]; 6490 6491 u8 reserved_at_20[0x10]; 6492 u8 op_mod[0x10]; 6493 6494 u8 reserved_at_40[0x1c]; 6495 u8 cong_protocol[0x4]; 6496 6497 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6498 6499 u8 reserved_at_80[0x80]; 6500 6501 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6502 }; 6503 6504 struct mlx5_ifc_manage_pages_out_bits { 6505 u8 status[0x8]; 6506 u8 reserved_at_8[0x18]; 6507 6508 u8 syndrome[0x20]; 6509 6510 u8 output_num_entries[0x20]; 6511 6512 u8 reserved_at_60[0x20]; 6513 6514 u8 pas[][0x40]; 6515 }; 6516 6517 enum { 6518 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6519 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6520 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6521 }; 6522 6523 struct mlx5_ifc_manage_pages_in_bits { 6524 u8 opcode[0x10]; 6525 u8 reserved_at_10[0x10]; 6526 6527 u8 reserved_at_20[0x10]; 6528 u8 op_mod[0x10]; 6529 6530 u8 embedded_cpu_function[0x1]; 6531 u8 reserved_at_41[0xf]; 6532 u8 function_id[0x10]; 6533 6534 u8 input_num_entries[0x20]; 6535 6536 u8 pas[][0x40]; 6537 }; 6538 6539 struct mlx5_ifc_mad_ifc_out_bits { 6540 u8 status[0x8]; 6541 u8 reserved_at_8[0x18]; 6542 6543 u8 syndrome[0x20]; 6544 6545 u8 reserved_at_40[0x40]; 6546 6547 u8 response_mad_packet[256][0x8]; 6548 }; 6549 6550 struct mlx5_ifc_mad_ifc_in_bits { 6551 u8 opcode[0x10]; 6552 u8 reserved_at_10[0x10]; 6553 6554 u8 reserved_at_20[0x10]; 6555 u8 op_mod[0x10]; 6556 6557 u8 remote_lid[0x10]; 6558 u8 reserved_at_50[0x8]; 6559 u8 port[0x8]; 6560 6561 u8 reserved_at_60[0x20]; 6562 6563 u8 mad[256][0x8]; 6564 }; 6565 6566 struct mlx5_ifc_init_hca_out_bits { 6567 u8 status[0x8]; 6568 u8 reserved_at_8[0x18]; 6569 6570 u8 syndrome[0x20]; 6571 6572 u8 reserved_at_40[0x40]; 6573 }; 6574 6575 struct mlx5_ifc_init_hca_in_bits { 6576 u8 opcode[0x10]; 6577 u8 reserved_at_10[0x10]; 6578 6579 u8 reserved_at_20[0x10]; 6580 u8 op_mod[0x10]; 6581 6582 u8 reserved_at_40[0x40]; 6583 u8 sw_owner_id[4][0x20]; 6584 }; 6585 6586 struct mlx5_ifc_init2rtr_qp_out_bits { 6587 u8 status[0x8]; 6588 u8 reserved_at_8[0x18]; 6589 6590 u8 syndrome[0x20]; 6591 6592 u8 reserved_at_40[0x20]; 6593 u8 ece[0x20]; 6594 }; 6595 6596 struct mlx5_ifc_init2rtr_qp_in_bits { 6597 u8 opcode[0x10]; 6598 u8 uid[0x10]; 6599 6600 u8 reserved_at_20[0x10]; 6601 u8 op_mod[0x10]; 6602 6603 u8 reserved_at_40[0x8]; 6604 u8 qpn[0x18]; 6605 6606 u8 reserved_at_60[0x20]; 6607 6608 u8 opt_param_mask[0x20]; 6609 6610 u8 ece[0x20]; 6611 6612 struct mlx5_ifc_qpc_bits qpc; 6613 6614 u8 reserved_at_800[0x80]; 6615 }; 6616 6617 struct mlx5_ifc_init2init_qp_out_bits { 6618 u8 status[0x8]; 6619 u8 reserved_at_8[0x18]; 6620 6621 u8 syndrome[0x20]; 6622 6623 u8 reserved_at_40[0x20]; 6624 u8 ece[0x20]; 6625 }; 6626 6627 struct mlx5_ifc_init2init_qp_in_bits { 6628 u8 opcode[0x10]; 6629 u8 uid[0x10]; 6630 6631 u8 reserved_at_20[0x10]; 6632 u8 op_mod[0x10]; 6633 6634 u8 reserved_at_40[0x8]; 6635 u8 qpn[0x18]; 6636 6637 u8 reserved_at_60[0x20]; 6638 6639 u8 opt_param_mask[0x20]; 6640 6641 u8 ece[0x20]; 6642 6643 struct mlx5_ifc_qpc_bits qpc; 6644 6645 u8 reserved_at_800[0x80]; 6646 }; 6647 6648 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6649 u8 status[0x8]; 6650 u8 reserved_at_8[0x18]; 6651 6652 u8 syndrome[0x20]; 6653 6654 u8 reserved_at_40[0x40]; 6655 6656 u8 packet_headers_log[128][0x8]; 6657 6658 u8 packet_syndrome[64][0x8]; 6659 }; 6660 6661 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6662 u8 opcode[0x10]; 6663 u8 reserved_at_10[0x10]; 6664 6665 u8 reserved_at_20[0x10]; 6666 u8 op_mod[0x10]; 6667 6668 u8 reserved_at_40[0x40]; 6669 }; 6670 6671 struct mlx5_ifc_gen_eqe_in_bits { 6672 u8 opcode[0x10]; 6673 u8 reserved_at_10[0x10]; 6674 6675 u8 reserved_at_20[0x10]; 6676 u8 op_mod[0x10]; 6677 6678 u8 reserved_at_40[0x18]; 6679 u8 eq_number[0x8]; 6680 6681 u8 reserved_at_60[0x20]; 6682 6683 u8 eqe[64][0x8]; 6684 }; 6685 6686 struct mlx5_ifc_gen_eq_out_bits { 6687 u8 status[0x8]; 6688 u8 reserved_at_8[0x18]; 6689 6690 u8 syndrome[0x20]; 6691 6692 u8 reserved_at_40[0x40]; 6693 }; 6694 6695 struct mlx5_ifc_enable_hca_out_bits { 6696 u8 status[0x8]; 6697 u8 reserved_at_8[0x18]; 6698 6699 u8 syndrome[0x20]; 6700 6701 u8 reserved_at_40[0x20]; 6702 }; 6703 6704 struct mlx5_ifc_enable_hca_in_bits { 6705 u8 opcode[0x10]; 6706 u8 reserved_at_10[0x10]; 6707 6708 u8 reserved_at_20[0x10]; 6709 u8 op_mod[0x10]; 6710 6711 u8 embedded_cpu_function[0x1]; 6712 u8 reserved_at_41[0xf]; 6713 u8 function_id[0x10]; 6714 6715 u8 reserved_at_60[0x20]; 6716 }; 6717 6718 struct mlx5_ifc_drain_dct_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_at_8[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 reserved_at_40[0x40]; 6725 }; 6726 6727 struct mlx5_ifc_drain_dct_in_bits { 6728 u8 opcode[0x10]; 6729 u8 uid[0x10]; 6730 6731 u8 reserved_at_20[0x10]; 6732 u8 op_mod[0x10]; 6733 6734 u8 reserved_at_40[0x8]; 6735 u8 dctn[0x18]; 6736 6737 u8 reserved_at_60[0x20]; 6738 }; 6739 6740 struct mlx5_ifc_disable_hca_out_bits { 6741 u8 status[0x8]; 6742 u8 reserved_at_8[0x18]; 6743 6744 u8 syndrome[0x20]; 6745 6746 u8 reserved_at_40[0x20]; 6747 }; 6748 6749 struct mlx5_ifc_disable_hca_in_bits { 6750 u8 opcode[0x10]; 6751 u8 reserved_at_10[0x10]; 6752 6753 u8 reserved_at_20[0x10]; 6754 u8 op_mod[0x10]; 6755 6756 u8 embedded_cpu_function[0x1]; 6757 u8 reserved_at_41[0xf]; 6758 u8 function_id[0x10]; 6759 6760 u8 reserved_at_60[0x20]; 6761 }; 6762 6763 struct mlx5_ifc_detach_from_mcg_out_bits { 6764 u8 status[0x8]; 6765 u8 reserved_at_8[0x18]; 6766 6767 u8 syndrome[0x20]; 6768 6769 u8 reserved_at_40[0x40]; 6770 }; 6771 6772 struct mlx5_ifc_detach_from_mcg_in_bits { 6773 u8 opcode[0x10]; 6774 u8 uid[0x10]; 6775 6776 u8 reserved_at_20[0x10]; 6777 u8 op_mod[0x10]; 6778 6779 u8 reserved_at_40[0x8]; 6780 u8 qpn[0x18]; 6781 6782 u8 reserved_at_60[0x20]; 6783 6784 u8 multicast_gid[16][0x8]; 6785 }; 6786 6787 struct mlx5_ifc_destroy_xrq_out_bits { 6788 u8 status[0x8]; 6789 u8 reserved_at_8[0x18]; 6790 6791 u8 syndrome[0x20]; 6792 6793 u8 reserved_at_40[0x40]; 6794 }; 6795 6796 struct mlx5_ifc_destroy_xrq_in_bits { 6797 u8 opcode[0x10]; 6798 u8 uid[0x10]; 6799 6800 u8 reserved_at_20[0x10]; 6801 u8 op_mod[0x10]; 6802 6803 u8 reserved_at_40[0x8]; 6804 u8 xrqn[0x18]; 6805 6806 u8 reserved_at_60[0x20]; 6807 }; 6808 6809 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6810 u8 status[0x8]; 6811 u8 reserved_at_8[0x18]; 6812 6813 u8 syndrome[0x20]; 6814 6815 u8 reserved_at_40[0x40]; 6816 }; 6817 6818 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6819 u8 opcode[0x10]; 6820 u8 uid[0x10]; 6821 6822 u8 reserved_at_20[0x10]; 6823 u8 op_mod[0x10]; 6824 6825 u8 reserved_at_40[0x8]; 6826 u8 xrc_srqn[0x18]; 6827 6828 u8 reserved_at_60[0x20]; 6829 }; 6830 6831 struct mlx5_ifc_destroy_tis_out_bits { 6832 u8 status[0x8]; 6833 u8 reserved_at_8[0x18]; 6834 6835 u8 syndrome[0x20]; 6836 6837 u8 reserved_at_40[0x40]; 6838 }; 6839 6840 struct mlx5_ifc_destroy_tis_in_bits { 6841 u8 opcode[0x10]; 6842 u8 uid[0x10]; 6843 6844 u8 reserved_at_20[0x10]; 6845 u8 op_mod[0x10]; 6846 6847 u8 reserved_at_40[0x8]; 6848 u8 tisn[0x18]; 6849 6850 u8 reserved_at_60[0x20]; 6851 }; 6852 6853 struct mlx5_ifc_destroy_tir_out_bits { 6854 u8 status[0x8]; 6855 u8 reserved_at_8[0x18]; 6856 6857 u8 syndrome[0x20]; 6858 6859 u8 reserved_at_40[0x40]; 6860 }; 6861 6862 struct mlx5_ifc_destroy_tir_in_bits { 6863 u8 opcode[0x10]; 6864 u8 uid[0x10]; 6865 6866 u8 reserved_at_20[0x10]; 6867 u8 op_mod[0x10]; 6868 6869 u8 reserved_at_40[0x8]; 6870 u8 tirn[0x18]; 6871 6872 u8 reserved_at_60[0x20]; 6873 }; 6874 6875 struct mlx5_ifc_destroy_srq_out_bits { 6876 u8 status[0x8]; 6877 u8 reserved_at_8[0x18]; 6878 6879 u8 syndrome[0x20]; 6880 6881 u8 reserved_at_40[0x40]; 6882 }; 6883 6884 struct mlx5_ifc_destroy_srq_in_bits { 6885 u8 opcode[0x10]; 6886 u8 uid[0x10]; 6887 6888 u8 reserved_at_20[0x10]; 6889 u8 op_mod[0x10]; 6890 6891 u8 reserved_at_40[0x8]; 6892 u8 srqn[0x18]; 6893 6894 u8 reserved_at_60[0x20]; 6895 }; 6896 6897 struct mlx5_ifc_destroy_sq_out_bits { 6898 u8 status[0x8]; 6899 u8 reserved_at_8[0x18]; 6900 6901 u8 syndrome[0x20]; 6902 6903 u8 reserved_at_40[0x40]; 6904 }; 6905 6906 struct mlx5_ifc_destroy_sq_in_bits { 6907 u8 opcode[0x10]; 6908 u8 uid[0x10]; 6909 6910 u8 reserved_at_20[0x10]; 6911 u8 op_mod[0x10]; 6912 6913 u8 reserved_at_40[0x8]; 6914 u8 sqn[0x18]; 6915 6916 u8 reserved_at_60[0x20]; 6917 }; 6918 6919 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6920 u8 status[0x8]; 6921 u8 reserved_at_8[0x18]; 6922 6923 u8 syndrome[0x20]; 6924 6925 u8 reserved_at_40[0x1c0]; 6926 }; 6927 6928 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6929 u8 opcode[0x10]; 6930 u8 reserved_at_10[0x10]; 6931 6932 u8 reserved_at_20[0x10]; 6933 u8 op_mod[0x10]; 6934 6935 u8 scheduling_hierarchy[0x8]; 6936 u8 reserved_at_48[0x18]; 6937 6938 u8 scheduling_element_id[0x20]; 6939 6940 u8 reserved_at_80[0x180]; 6941 }; 6942 6943 struct mlx5_ifc_destroy_rqt_out_bits { 6944 u8 status[0x8]; 6945 u8 reserved_at_8[0x18]; 6946 6947 u8 syndrome[0x20]; 6948 6949 u8 reserved_at_40[0x40]; 6950 }; 6951 6952 struct mlx5_ifc_destroy_rqt_in_bits { 6953 u8 opcode[0x10]; 6954 u8 uid[0x10]; 6955 6956 u8 reserved_at_20[0x10]; 6957 u8 op_mod[0x10]; 6958 6959 u8 reserved_at_40[0x8]; 6960 u8 rqtn[0x18]; 6961 6962 u8 reserved_at_60[0x20]; 6963 }; 6964 6965 struct mlx5_ifc_destroy_rq_out_bits { 6966 u8 status[0x8]; 6967 u8 reserved_at_8[0x18]; 6968 6969 u8 syndrome[0x20]; 6970 6971 u8 reserved_at_40[0x40]; 6972 }; 6973 6974 struct mlx5_ifc_destroy_rq_in_bits { 6975 u8 opcode[0x10]; 6976 u8 uid[0x10]; 6977 6978 u8 reserved_at_20[0x10]; 6979 u8 op_mod[0x10]; 6980 6981 u8 reserved_at_40[0x8]; 6982 u8 rqn[0x18]; 6983 6984 u8 reserved_at_60[0x20]; 6985 }; 6986 6987 struct mlx5_ifc_set_delay_drop_params_in_bits { 6988 u8 opcode[0x10]; 6989 u8 reserved_at_10[0x10]; 6990 6991 u8 reserved_at_20[0x10]; 6992 u8 op_mod[0x10]; 6993 6994 u8 reserved_at_40[0x20]; 6995 6996 u8 reserved_at_60[0x10]; 6997 u8 delay_drop_timeout[0x10]; 6998 }; 6999 7000 struct mlx5_ifc_set_delay_drop_params_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_at_8[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_at_40[0x40]; 7007 }; 7008 7009 struct mlx5_ifc_destroy_rmp_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x40]; 7016 }; 7017 7018 struct mlx5_ifc_destroy_rmp_in_bits { 7019 u8 opcode[0x10]; 7020 u8 uid[0x10]; 7021 7022 u8 reserved_at_20[0x10]; 7023 u8 op_mod[0x10]; 7024 7025 u8 reserved_at_40[0x8]; 7026 u8 rmpn[0x18]; 7027 7028 u8 reserved_at_60[0x20]; 7029 }; 7030 7031 struct mlx5_ifc_destroy_qp_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x40]; 7038 }; 7039 7040 struct mlx5_ifc_destroy_qp_in_bits { 7041 u8 opcode[0x10]; 7042 u8 uid[0x10]; 7043 7044 u8 reserved_at_20[0x10]; 7045 u8 op_mod[0x10]; 7046 7047 u8 reserved_at_40[0x8]; 7048 u8 qpn[0x18]; 7049 7050 u8 reserved_at_60[0x20]; 7051 }; 7052 7053 struct mlx5_ifc_destroy_psv_out_bits { 7054 u8 status[0x8]; 7055 u8 reserved_at_8[0x18]; 7056 7057 u8 syndrome[0x20]; 7058 7059 u8 reserved_at_40[0x40]; 7060 }; 7061 7062 struct mlx5_ifc_destroy_psv_in_bits { 7063 u8 opcode[0x10]; 7064 u8 reserved_at_10[0x10]; 7065 7066 u8 reserved_at_20[0x10]; 7067 u8 op_mod[0x10]; 7068 7069 u8 reserved_at_40[0x8]; 7070 u8 psvn[0x18]; 7071 7072 u8 reserved_at_60[0x20]; 7073 }; 7074 7075 struct mlx5_ifc_destroy_mkey_out_bits { 7076 u8 status[0x8]; 7077 u8 reserved_at_8[0x18]; 7078 7079 u8 syndrome[0x20]; 7080 7081 u8 reserved_at_40[0x40]; 7082 }; 7083 7084 struct mlx5_ifc_destroy_mkey_in_bits { 7085 u8 opcode[0x10]; 7086 u8 reserved_at_10[0x10]; 7087 7088 u8 reserved_at_20[0x10]; 7089 u8 op_mod[0x10]; 7090 7091 u8 reserved_at_40[0x8]; 7092 u8 mkey_index[0x18]; 7093 7094 u8 reserved_at_60[0x20]; 7095 }; 7096 7097 struct mlx5_ifc_destroy_flow_table_out_bits { 7098 u8 status[0x8]; 7099 u8 reserved_at_8[0x18]; 7100 7101 u8 syndrome[0x20]; 7102 7103 u8 reserved_at_40[0x40]; 7104 }; 7105 7106 struct mlx5_ifc_destroy_flow_table_in_bits { 7107 u8 opcode[0x10]; 7108 u8 reserved_at_10[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 other_vport[0x1]; 7114 u8 reserved_at_41[0xf]; 7115 u8 vport_number[0x10]; 7116 7117 u8 reserved_at_60[0x20]; 7118 7119 u8 table_type[0x8]; 7120 u8 reserved_at_88[0x18]; 7121 7122 u8 reserved_at_a0[0x8]; 7123 u8 table_id[0x18]; 7124 7125 u8 reserved_at_c0[0x140]; 7126 }; 7127 7128 struct mlx5_ifc_destroy_flow_group_out_bits { 7129 u8 status[0x8]; 7130 u8 reserved_at_8[0x18]; 7131 7132 u8 syndrome[0x20]; 7133 7134 u8 reserved_at_40[0x40]; 7135 }; 7136 7137 struct mlx5_ifc_destroy_flow_group_in_bits { 7138 u8 opcode[0x10]; 7139 u8 reserved_at_10[0x10]; 7140 7141 u8 reserved_at_20[0x10]; 7142 u8 op_mod[0x10]; 7143 7144 u8 other_vport[0x1]; 7145 u8 reserved_at_41[0xf]; 7146 u8 vport_number[0x10]; 7147 7148 u8 reserved_at_60[0x20]; 7149 7150 u8 table_type[0x8]; 7151 u8 reserved_at_88[0x18]; 7152 7153 u8 reserved_at_a0[0x8]; 7154 u8 table_id[0x18]; 7155 7156 u8 group_id[0x20]; 7157 7158 u8 reserved_at_e0[0x120]; 7159 }; 7160 7161 struct mlx5_ifc_destroy_eq_out_bits { 7162 u8 status[0x8]; 7163 u8 reserved_at_8[0x18]; 7164 7165 u8 syndrome[0x20]; 7166 7167 u8 reserved_at_40[0x40]; 7168 }; 7169 7170 struct mlx5_ifc_destroy_eq_in_bits { 7171 u8 opcode[0x10]; 7172 u8 reserved_at_10[0x10]; 7173 7174 u8 reserved_at_20[0x10]; 7175 u8 op_mod[0x10]; 7176 7177 u8 reserved_at_40[0x18]; 7178 u8 eq_number[0x8]; 7179 7180 u8 reserved_at_60[0x20]; 7181 }; 7182 7183 struct mlx5_ifc_destroy_dct_out_bits { 7184 u8 status[0x8]; 7185 u8 reserved_at_8[0x18]; 7186 7187 u8 syndrome[0x20]; 7188 7189 u8 reserved_at_40[0x40]; 7190 }; 7191 7192 struct mlx5_ifc_destroy_dct_in_bits { 7193 u8 opcode[0x10]; 7194 u8 uid[0x10]; 7195 7196 u8 reserved_at_20[0x10]; 7197 u8 op_mod[0x10]; 7198 7199 u8 reserved_at_40[0x8]; 7200 u8 dctn[0x18]; 7201 7202 u8 reserved_at_60[0x20]; 7203 }; 7204 7205 struct mlx5_ifc_destroy_cq_out_bits { 7206 u8 status[0x8]; 7207 u8 reserved_at_8[0x18]; 7208 7209 u8 syndrome[0x20]; 7210 7211 u8 reserved_at_40[0x40]; 7212 }; 7213 7214 struct mlx5_ifc_destroy_cq_in_bits { 7215 u8 opcode[0x10]; 7216 u8 uid[0x10]; 7217 7218 u8 reserved_at_20[0x10]; 7219 u8 op_mod[0x10]; 7220 7221 u8 reserved_at_40[0x8]; 7222 u8 cqn[0x18]; 7223 7224 u8 reserved_at_60[0x20]; 7225 }; 7226 7227 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7228 u8 status[0x8]; 7229 u8 reserved_at_8[0x18]; 7230 7231 u8 syndrome[0x20]; 7232 7233 u8 reserved_at_40[0x40]; 7234 }; 7235 7236 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7237 u8 opcode[0x10]; 7238 u8 reserved_at_10[0x10]; 7239 7240 u8 reserved_at_20[0x10]; 7241 u8 op_mod[0x10]; 7242 7243 u8 reserved_at_40[0x20]; 7244 7245 u8 reserved_at_60[0x10]; 7246 u8 vxlan_udp_port[0x10]; 7247 }; 7248 7249 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7250 u8 status[0x8]; 7251 u8 reserved_at_8[0x18]; 7252 7253 u8 syndrome[0x20]; 7254 7255 u8 reserved_at_40[0x40]; 7256 }; 7257 7258 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7259 u8 opcode[0x10]; 7260 u8 reserved_at_10[0x10]; 7261 7262 u8 reserved_at_20[0x10]; 7263 u8 op_mod[0x10]; 7264 7265 u8 reserved_at_40[0x60]; 7266 7267 u8 reserved_at_a0[0x8]; 7268 u8 table_index[0x18]; 7269 7270 u8 reserved_at_c0[0x140]; 7271 }; 7272 7273 struct mlx5_ifc_delete_fte_out_bits { 7274 u8 status[0x8]; 7275 u8 reserved_at_8[0x18]; 7276 7277 u8 syndrome[0x20]; 7278 7279 u8 reserved_at_40[0x40]; 7280 }; 7281 7282 struct mlx5_ifc_delete_fte_in_bits { 7283 u8 opcode[0x10]; 7284 u8 reserved_at_10[0x10]; 7285 7286 u8 reserved_at_20[0x10]; 7287 u8 op_mod[0x10]; 7288 7289 u8 other_vport[0x1]; 7290 u8 reserved_at_41[0xf]; 7291 u8 vport_number[0x10]; 7292 7293 u8 reserved_at_60[0x20]; 7294 7295 u8 table_type[0x8]; 7296 u8 reserved_at_88[0x18]; 7297 7298 u8 reserved_at_a0[0x8]; 7299 u8 table_id[0x18]; 7300 7301 u8 reserved_at_c0[0x40]; 7302 7303 u8 flow_index[0x20]; 7304 7305 u8 reserved_at_120[0xe0]; 7306 }; 7307 7308 struct mlx5_ifc_dealloc_xrcd_out_bits { 7309 u8 status[0x8]; 7310 u8 reserved_at_8[0x18]; 7311 7312 u8 syndrome[0x20]; 7313 7314 u8 reserved_at_40[0x40]; 7315 }; 7316 7317 struct mlx5_ifc_dealloc_xrcd_in_bits { 7318 u8 opcode[0x10]; 7319 u8 uid[0x10]; 7320 7321 u8 reserved_at_20[0x10]; 7322 u8 op_mod[0x10]; 7323 7324 u8 reserved_at_40[0x8]; 7325 u8 xrcd[0x18]; 7326 7327 u8 reserved_at_60[0x20]; 7328 }; 7329 7330 struct mlx5_ifc_dealloc_uar_out_bits { 7331 u8 status[0x8]; 7332 u8 reserved_at_8[0x18]; 7333 7334 u8 syndrome[0x20]; 7335 7336 u8 reserved_at_40[0x40]; 7337 }; 7338 7339 struct mlx5_ifc_dealloc_uar_in_bits { 7340 u8 opcode[0x10]; 7341 u8 reserved_at_10[0x10]; 7342 7343 u8 reserved_at_20[0x10]; 7344 u8 op_mod[0x10]; 7345 7346 u8 reserved_at_40[0x8]; 7347 u8 uar[0x18]; 7348 7349 u8 reserved_at_60[0x20]; 7350 }; 7351 7352 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7353 u8 status[0x8]; 7354 u8 reserved_at_8[0x18]; 7355 7356 u8 syndrome[0x20]; 7357 7358 u8 reserved_at_40[0x40]; 7359 }; 7360 7361 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7362 u8 opcode[0x10]; 7363 u8 uid[0x10]; 7364 7365 u8 reserved_at_20[0x10]; 7366 u8 op_mod[0x10]; 7367 7368 u8 reserved_at_40[0x8]; 7369 u8 transport_domain[0x18]; 7370 7371 u8 reserved_at_60[0x20]; 7372 }; 7373 7374 struct mlx5_ifc_dealloc_q_counter_out_bits { 7375 u8 status[0x8]; 7376 u8 reserved_at_8[0x18]; 7377 7378 u8 syndrome[0x20]; 7379 7380 u8 reserved_at_40[0x40]; 7381 }; 7382 7383 struct mlx5_ifc_dealloc_q_counter_in_bits { 7384 u8 opcode[0x10]; 7385 u8 reserved_at_10[0x10]; 7386 7387 u8 reserved_at_20[0x10]; 7388 u8 op_mod[0x10]; 7389 7390 u8 reserved_at_40[0x18]; 7391 u8 counter_set_id[0x8]; 7392 7393 u8 reserved_at_60[0x20]; 7394 }; 7395 7396 struct mlx5_ifc_dealloc_pd_out_bits { 7397 u8 status[0x8]; 7398 u8 reserved_at_8[0x18]; 7399 7400 u8 syndrome[0x20]; 7401 7402 u8 reserved_at_40[0x40]; 7403 }; 7404 7405 struct mlx5_ifc_dealloc_pd_in_bits { 7406 u8 opcode[0x10]; 7407 u8 uid[0x10]; 7408 7409 u8 reserved_at_20[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 reserved_at_40[0x8]; 7413 u8 pd[0x18]; 7414 7415 u8 reserved_at_60[0x20]; 7416 }; 7417 7418 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7419 u8 status[0x8]; 7420 u8 reserved_at_8[0x18]; 7421 7422 u8 syndrome[0x20]; 7423 7424 u8 reserved_at_40[0x40]; 7425 }; 7426 7427 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7428 u8 opcode[0x10]; 7429 u8 reserved_at_10[0x10]; 7430 7431 u8 reserved_at_20[0x10]; 7432 u8 op_mod[0x10]; 7433 7434 u8 flow_counter_id[0x20]; 7435 7436 u8 reserved_at_60[0x20]; 7437 }; 7438 7439 struct mlx5_ifc_create_xrq_out_bits { 7440 u8 status[0x8]; 7441 u8 reserved_at_8[0x18]; 7442 7443 u8 syndrome[0x20]; 7444 7445 u8 reserved_at_40[0x8]; 7446 u8 xrqn[0x18]; 7447 7448 u8 reserved_at_60[0x20]; 7449 }; 7450 7451 struct mlx5_ifc_create_xrq_in_bits { 7452 u8 opcode[0x10]; 7453 u8 uid[0x10]; 7454 7455 u8 reserved_at_20[0x10]; 7456 u8 op_mod[0x10]; 7457 7458 u8 reserved_at_40[0x40]; 7459 7460 struct mlx5_ifc_xrqc_bits xrq_context; 7461 }; 7462 7463 struct mlx5_ifc_create_xrc_srq_out_bits { 7464 u8 status[0x8]; 7465 u8 reserved_at_8[0x18]; 7466 7467 u8 syndrome[0x20]; 7468 7469 u8 reserved_at_40[0x8]; 7470 u8 xrc_srqn[0x18]; 7471 7472 u8 reserved_at_60[0x20]; 7473 }; 7474 7475 struct mlx5_ifc_create_xrc_srq_in_bits { 7476 u8 opcode[0x10]; 7477 u8 uid[0x10]; 7478 7479 u8 reserved_at_20[0x10]; 7480 u8 op_mod[0x10]; 7481 7482 u8 reserved_at_40[0x40]; 7483 7484 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7485 7486 u8 reserved_at_280[0x60]; 7487 7488 u8 xrc_srq_umem_valid[0x1]; 7489 u8 reserved_at_2e1[0x1f]; 7490 7491 u8 reserved_at_300[0x580]; 7492 7493 u8 pas[][0x40]; 7494 }; 7495 7496 struct mlx5_ifc_create_tis_out_bits { 7497 u8 status[0x8]; 7498 u8 reserved_at_8[0x18]; 7499 7500 u8 syndrome[0x20]; 7501 7502 u8 reserved_at_40[0x8]; 7503 u8 tisn[0x18]; 7504 7505 u8 reserved_at_60[0x20]; 7506 }; 7507 7508 struct mlx5_ifc_create_tis_in_bits { 7509 u8 opcode[0x10]; 7510 u8 uid[0x10]; 7511 7512 u8 reserved_at_20[0x10]; 7513 u8 op_mod[0x10]; 7514 7515 u8 reserved_at_40[0xc0]; 7516 7517 struct mlx5_ifc_tisc_bits ctx; 7518 }; 7519 7520 struct mlx5_ifc_create_tir_out_bits { 7521 u8 status[0x8]; 7522 u8 icm_address_63_40[0x18]; 7523 7524 u8 syndrome[0x20]; 7525 7526 u8 icm_address_39_32[0x8]; 7527 u8 tirn[0x18]; 7528 7529 u8 icm_address_31_0[0x20]; 7530 }; 7531 7532 struct mlx5_ifc_create_tir_in_bits { 7533 u8 opcode[0x10]; 7534 u8 uid[0x10]; 7535 7536 u8 reserved_at_20[0x10]; 7537 u8 op_mod[0x10]; 7538 7539 u8 reserved_at_40[0xc0]; 7540 7541 struct mlx5_ifc_tirc_bits ctx; 7542 }; 7543 7544 struct mlx5_ifc_create_srq_out_bits { 7545 u8 status[0x8]; 7546 u8 reserved_at_8[0x18]; 7547 7548 u8 syndrome[0x20]; 7549 7550 u8 reserved_at_40[0x8]; 7551 u8 srqn[0x18]; 7552 7553 u8 reserved_at_60[0x20]; 7554 }; 7555 7556 struct mlx5_ifc_create_srq_in_bits { 7557 u8 opcode[0x10]; 7558 u8 uid[0x10]; 7559 7560 u8 reserved_at_20[0x10]; 7561 u8 op_mod[0x10]; 7562 7563 u8 reserved_at_40[0x40]; 7564 7565 struct mlx5_ifc_srqc_bits srq_context_entry; 7566 7567 u8 reserved_at_280[0x600]; 7568 7569 u8 pas[][0x40]; 7570 }; 7571 7572 struct mlx5_ifc_create_sq_out_bits { 7573 u8 status[0x8]; 7574 u8 reserved_at_8[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 reserved_at_40[0x8]; 7579 u8 sqn[0x18]; 7580 7581 u8 reserved_at_60[0x20]; 7582 }; 7583 7584 struct mlx5_ifc_create_sq_in_bits { 7585 u8 opcode[0x10]; 7586 u8 uid[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 reserved_at_40[0xc0]; 7592 7593 struct mlx5_ifc_sqc_bits ctx; 7594 }; 7595 7596 struct mlx5_ifc_create_scheduling_element_out_bits { 7597 u8 status[0x8]; 7598 u8 reserved_at_8[0x18]; 7599 7600 u8 syndrome[0x20]; 7601 7602 u8 reserved_at_40[0x40]; 7603 7604 u8 scheduling_element_id[0x20]; 7605 7606 u8 reserved_at_a0[0x160]; 7607 }; 7608 7609 struct mlx5_ifc_create_scheduling_element_in_bits { 7610 u8 opcode[0x10]; 7611 u8 reserved_at_10[0x10]; 7612 7613 u8 reserved_at_20[0x10]; 7614 u8 op_mod[0x10]; 7615 7616 u8 scheduling_hierarchy[0x8]; 7617 u8 reserved_at_48[0x18]; 7618 7619 u8 reserved_at_60[0xa0]; 7620 7621 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7622 7623 u8 reserved_at_300[0x100]; 7624 }; 7625 7626 struct mlx5_ifc_create_rqt_out_bits { 7627 u8 status[0x8]; 7628 u8 reserved_at_8[0x18]; 7629 7630 u8 syndrome[0x20]; 7631 7632 u8 reserved_at_40[0x8]; 7633 u8 rqtn[0x18]; 7634 7635 u8 reserved_at_60[0x20]; 7636 }; 7637 7638 struct mlx5_ifc_create_rqt_in_bits { 7639 u8 opcode[0x10]; 7640 u8 uid[0x10]; 7641 7642 u8 reserved_at_20[0x10]; 7643 u8 op_mod[0x10]; 7644 7645 u8 reserved_at_40[0xc0]; 7646 7647 struct mlx5_ifc_rqtc_bits rqt_context; 7648 }; 7649 7650 struct mlx5_ifc_create_rq_out_bits { 7651 u8 status[0x8]; 7652 u8 reserved_at_8[0x18]; 7653 7654 u8 syndrome[0x20]; 7655 7656 u8 reserved_at_40[0x8]; 7657 u8 rqn[0x18]; 7658 7659 u8 reserved_at_60[0x20]; 7660 }; 7661 7662 struct mlx5_ifc_create_rq_in_bits { 7663 u8 opcode[0x10]; 7664 u8 uid[0x10]; 7665 7666 u8 reserved_at_20[0x10]; 7667 u8 op_mod[0x10]; 7668 7669 u8 reserved_at_40[0xc0]; 7670 7671 struct mlx5_ifc_rqc_bits ctx; 7672 }; 7673 7674 struct mlx5_ifc_create_rmp_out_bits { 7675 u8 status[0x8]; 7676 u8 reserved_at_8[0x18]; 7677 7678 u8 syndrome[0x20]; 7679 7680 u8 reserved_at_40[0x8]; 7681 u8 rmpn[0x18]; 7682 7683 u8 reserved_at_60[0x20]; 7684 }; 7685 7686 struct mlx5_ifc_create_rmp_in_bits { 7687 u8 opcode[0x10]; 7688 u8 uid[0x10]; 7689 7690 u8 reserved_at_20[0x10]; 7691 u8 op_mod[0x10]; 7692 7693 u8 reserved_at_40[0xc0]; 7694 7695 struct mlx5_ifc_rmpc_bits ctx; 7696 }; 7697 7698 struct mlx5_ifc_create_qp_out_bits { 7699 u8 status[0x8]; 7700 u8 reserved_at_8[0x18]; 7701 7702 u8 syndrome[0x20]; 7703 7704 u8 reserved_at_40[0x8]; 7705 u8 qpn[0x18]; 7706 7707 u8 ece[0x20]; 7708 }; 7709 7710 struct mlx5_ifc_create_qp_in_bits { 7711 u8 opcode[0x10]; 7712 u8 uid[0x10]; 7713 7714 u8 reserved_at_20[0x10]; 7715 u8 op_mod[0x10]; 7716 7717 u8 reserved_at_40[0x40]; 7718 7719 u8 opt_param_mask[0x20]; 7720 7721 u8 ece[0x20]; 7722 7723 struct mlx5_ifc_qpc_bits qpc; 7724 7725 u8 reserved_at_800[0x60]; 7726 7727 u8 wq_umem_valid[0x1]; 7728 u8 reserved_at_861[0x1f]; 7729 7730 u8 pas[][0x40]; 7731 }; 7732 7733 struct mlx5_ifc_create_psv_out_bits { 7734 u8 status[0x8]; 7735 u8 reserved_at_8[0x18]; 7736 7737 u8 syndrome[0x20]; 7738 7739 u8 reserved_at_40[0x40]; 7740 7741 u8 reserved_at_80[0x8]; 7742 u8 psv0_index[0x18]; 7743 7744 u8 reserved_at_a0[0x8]; 7745 u8 psv1_index[0x18]; 7746 7747 u8 reserved_at_c0[0x8]; 7748 u8 psv2_index[0x18]; 7749 7750 u8 reserved_at_e0[0x8]; 7751 u8 psv3_index[0x18]; 7752 }; 7753 7754 struct mlx5_ifc_create_psv_in_bits { 7755 u8 opcode[0x10]; 7756 u8 reserved_at_10[0x10]; 7757 7758 u8 reserved_at_20[0x10]; 7759 u8 op_mod[0x10]; 7760 7761 u8 num_psv[0x4]; 7762 u8 reserved_at_44[0x4]; 7763 u8 pd[0x18]; 7764 7765 u8 reserved_at_60[0x20]; 7766 }; 7767 7768 struct mlx5_ifc_create_mkey_out_bits { 7769 u8 status[0x8]; 7770 u8 reserved_at_8[0x18]; 7771 7772 u8 syndrome[0x20]; 7773 7774 u8 reserved_at_40[0x8]; 7775 u8 mkey_index[0x18]; 7776 7777 u8 reserved_at_60[0x20]; 7778 }; 7779 7780 struct mlx5_ifc_create_mkey_in_bits { 7781 u8 opcode[0x10]; 7782 u8 reserved_at_10[0x10]; 7783 7784 u8 reserved_at_20[0x10]; 7785 u8 op_mod[0x10]; 7786 7787 u8 reserved_at_40[0x20]; 7788 7789 u8 pg_access[0x1]; 7790 u8 mkey_umem_valid[0x1]; 7791 u8 reserved_at_62[0x1e]; 7792 7793 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7794 7795 u8 reserved_at_280[0x80]; 7796 7797 u8 translations_octword_actual_size[0x20]; 7798 7799 u8 reserved_at_320[0x560]; 7800 7801 u8 klm_pas_mtt[][0x20]; 7802 }; 7803 7804 enum { 7805 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7806 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7807 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7808 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7809 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7810 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7811 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7812 }; 7813 7814 struct mlx5_ifc_create_flow_table_out_bits { 7815 u8 status[0x8]; 7816 u8 icm_address_63_40[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 icm_address_39_32[0x8]; 7821 u8 table_id[0x18]; 7822 7823 u8 icm_address_31_0[0x20]; 7824 }; 7825 7826 struct mlx5_ifc_create_flow_table_in_bits { 7827 u8 opcode[0x10]; 7828 u8 reserved_at_10[0x10]; 7829 7830 u8 reserved_at_20[0x10]; 7831 u8 op_mod[0x10]; 7832 7833 u8 other_vport[0x1]; 7834 u8 reserved_at_41[0xf]; 7835 u8 vport_number[0x10]; 7836 7837 u8 reserved_at_60[0x20]; 7838 7839 u8 table_type[0x8]; 7840 u8 reserved_at_88[0x18]; 7841 7842 u8 reserved_at_a0[0x20]; 7843 7844 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7845 }; 7846 7847 struct mlx5_ifc_create_flow_group_out_bits { 7848 u8 status[0x8]; 7849 u8 reserved_at_8[0x18]; 7850 7851 u8 syndrome[0x20]; 7852 7853 u8 reserved_at_40[0x8]; 7854 u8 group_id[0x18]; 7855 7856 u8 reserved_at_60[0x20]; 7857 }; 7858 7859 enum { 7860 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7861 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7862 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7863 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7864 }; 7865 7866 struct mlx5_ifc_create_flow_group_in_bits { 7867 u8 opcode[0x10]; 7868 u8 reserved_at_10[0x10]; 7869 7870 u8 reserved_at_20[0x10]; 7871 u8 op_mod[0x10]; 7872 7873 u8 other_vport[0x1]; 7874 u8 reserved_at_41[0xf]; 7875 u8 vport_number[0x10]; 7876 7877 u8 reserved_at_60[0x20]; 7878 7879 u8 table_type[0x8]; 7880 u8 reserved_at_88[0x18]; 7881 7882 u8 reserved_at_a0[0x8]; 7883 u8 table_id[0x18]; 7884 7885 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7886 7887 u8 reserved_at_c1[0x1f]; 7888 7889 u8 start_flow_index[0x20]; 7890 7891 u8 reserved_at_100[0x20]; 7892 7893 u8 end_flow_index[0x20]; 7894 7895 u8 reserved_at_140[0xa0]; 7896 7897 u8 reserved_at_1e0[0x18]; 7898 u8 match_criteria_enable[0x8]; 7899 7900 struct mlx5_ifc_fte_match_param_bits match_criteria; 7901 7902 u8 reserved_at_1200[0xe00]; 7903 }; 7904 7905 struct mlx5_ifc_create_eq_out_bits { 7906 u8 status[0x8]; 7907 u8 reserved_at_8[0x18]; 7908 7909 u8 syndrome[0x20]; 7910 7911 u8 reserved_at_40[0x18]; 7912 u8 eq_number[0x8]; 7913 7914 u8 reserved_at_60[0x20]; 7915 }; 7916 7917 struct mlx5_ifc_create_eq_in_bits { 7918 u8 opcode[0x10]; 7919 u8 uid[0x10]; 7920 7921 u8 reserved_at_20[0x10]; 7922 u8 op_mod[0x10]; 7923 7924 u8 reserved_at_40[0x40]; 7925 7926 struct mlx5_ifc_eqc_bits eq_context_entry; 7927 7928 u8 reserved_at_280[0x40]; 7929 7930 u8 event_bitmask[4][0x40]; 7931 7932 u8 reserved_at_3c0[0x4c0]; 7933 7934 u8 pas[][0x40]; 7935 }; 7936 7937 struct mlx5_ifc_create_dct_out_bits { 7938 u8 status[0x8]; 7939 u8 reserved_at_8[0x18]; 7940 7941 u8 syndrome[0x20]; 7942 7943 u8 reserved_at_40[0x8]; 7944 u8 dctn[0x18]; 7945 7946 u8 ece[0x20]; 7947 }; 7948 7949 struct mlx5_ifc_create_dct_in_bits { 7950 u8 opcode[0x10]; 7951 u8 uid[0x10]; 7952 7953 u8 reserved_at_20[0x10]; 7954 u8 op_mod[0x10]; 7955 7956 u8 reserved_at_40[0x40]; 7957 7958 struct mlx5_ifc_dctc_bits dct_context_entry; 7959 7960 u8 reserved_at_280[0x180]; 7961 }; 7962 7963 struct mlx5_ifc_create_cq_out_bits { 7964 u8 status[0x8]; 7965 u8 reserved_at_8[0x18]; 7966 7967 u8 syndrome[0x20]; 7968 7969 u8 reserved_at_40[0x8]; 7970 u8 cqn[0x18]; 7971 7972 u8 reserved_at_60[0x20]; 7973 }; 7974 7975 struct mlx5_ifc_create_cq_in_bits { 7976 u8 opcode[0x10]; 7977 u8 uid[0x10]; 7978 7979 u8 reserved_at_20[0x10]; 7980 u8 op_mod[0x10]; 7981 7982 u8 reserved_at_40[0x40]; 7983 7984 struct mlx5_ifc_cqc_bits cq_context; 7985 7986 u8 reserved_at_280[0x60]; 7987 7988 u8 cq_umem_valid[0x1]; 7989 u8 reserved_at_2e1[0x59f]; 7990 7991 u8 pas[][0x40]; 7992 }; 7993 7994 struct mlx5_ifc_config_int_moderation_out_bits { 7995 u8 status[0x8]; 7996 u8 reserved_at_8[0x18]; 7997 7998 u8 syndrome[0x20]; 7999 8000 u8 reserved_at_40[0x4]; 8001 u8 min_delay[0xc]; 8002 u8 int_vector[0x10]; 8003 8004 u8 reserved_at_60[0x20]; 8005 }; 8006 8007 enum { 8008 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8009 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8010 }; 8011 8012 struct mlx5_ifc_config_int_moderation_in_bits { 8013 u8 opcode[0x10]; 8014 u8 reserved_at_10[0x10]; 8015 8016 u8 reserved_at_20[0x10]; 8017 u8 op_mod[0x10]; 8018 8019 u8 reserved_at_40[0x4]; 8020 u8 min_delay[0xc]; 8021 u8 int_vector[0x10]; 8022 8023 u8 reserved_at_60[0x20]; 8024 }; 8025 8026 struct mlx5_ifc_attach_to_mcg_out_bits { 8027 u8 status[0x8]; 8028 u8 reserved_at_8[0x18]; 8029 8030 u8 syndrome[0x20]; 8031 8032 u8 reserved_at_40[0x40]; 8033 }; 8034 8035 struct mlx5_ifc_attach_to_mcg_in_bits { 8036 u8 opcode[0x10]; 8037 u8 uid[0x10]; 8038 8039 u8 reserved_at_20[0x10]; 8040 u8 op_mod[0x10]; 8041 8042 u8 reserved_at_40[0x8]; 8043 u8 qpn[0x18]; 8044 8045 u8 reserved_at_60[0x20]; 8046 8047 u8 multicast_gid[16][0x8]; 8048 }; 8049 8050 struct mlx5_ifc_arm_xrq_out_bits { 8051 u8 status[0x8]; 8052 u8 reserved_at_8[0x18]; 8053 8054 u8 syndrome[0x20]; 8055 8056 u8 reserved_at_40[0x40]; 8057 }; 8058 8059 struct mlx5_ifc_arm_xrq_in_bits { 8060 u8 opcode[0x10]; 8061 u8 reserved_at_10[0x10]; 8062 8063 u8 reserved_at_20[0x10]; 8064 u8 op_mod[0x10]; 8065 8066 u8 reserved_at_40[0x8]; 8067 u8 xrqn[0x18]; 8068 8069 u8 reserved_at_60[0x10]; 8070 u8 lwm[0x10]; 8071 }; 8072 8073 struct mlx5_ifc_arm_xrc_srq_out_bits { 8074 u8 status[0x8]; 8075 u8 reserved_at_8[0x18]; 8076 8077 u8 syndrome[0x20]; 8078 8079 u8 reserved_at_40[0x40]; 8080 }; 8081 8082 enum { 8083 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8084 }; 8085 8086 struct mlx5_ifc_arm_xrc_srq_in_bits { 8087 u8 opcode[0x10]; 8088 u8 uid[0x10]; 8089 8090 u8 reserved_at_20[0x10]; 8091 u8 op_mod[0x10]; 8092 8093 u8 reserved_at_40[0x8]; 8094 u8 xrc_srqn[0x18]; 8095 8096 u8 reserved_at_60[0x10]; 8097 u8 lwm[0x10]; 8098 }; 8099 8100 struct mlx5_ifc_arm_rq_out_bits { 8101 u8 status[0x8]; 8102 u8 reserved_at_8[0x18]; 8103 8104 u8 syndrome[0x20]; 8105 8106 u8 reserved_at_40[0x40]; 8107 }; 8108 8109 enum { 8110 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8111 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8112 }; 8113 8114 struct mlx5_ifc_arm_rq_in_bits { 8115 u8 opcode[0x10]; 8116 u8 uid[0x10]; 8117 8118 u8 reserved_at_20[0x10]; 8119 u8 op_mod[0x10]; 8120 8121 u8 reserved_at_40[0x8]; 8122 u8 srq_number[0x18]; 8123 8124 u8 reserved_at_60[0x10]; 8125 u8 lwm[0x10]; 8126 }; 8127 8128 struct mlx5_ifc_arm_dct_out_bits { 8129 u8 status[0x8]; 8130 u8 reserved_at_8[0x18]; 8131 8132 u8 syndrome[0x20]; 8133 8134 u8 reserved_at_40[0x40]; 8135 }; 8136 8137 struct mlx5_ifc_arm_dct_in_bits { 8138 u8 opcode[0x10]; 8139 u8 reserved_at_10[0x10]; 8140 8141 u8 reserved_at_20[0x10]; 8142 u8 op_mod[0x10]; 8143 8144 u8 reserved_at_40[0x8]; 8145 u8 dct_number[0x18]; 8146 8147 u8 reserved_at_60[0x20]; 8148 }; 8149 8150 struct mlx5_ifc_alloc_xrcd_out_bits { 8151 u8 status[0x8]; 8152 u8 reserved_at_8[0x18]; 8153 8154 u8 syndrome[0x20]; 8155 8156 u8 reserved_at_40[0x8]; 8157 u8 xrcd[0x18]; 8158 8159 u8 reserved_at_60[0x20]; 8160 }; 8161 8162 struct mlx5_ifc_alloc_xrcd_in_bits { 8163 u8 opcode[0x10]; 8164 u8 uid[0x10]; 8165 8166 u8 reserved_at_20[0x10]; 8167 u8 op_mod[0x10]; 8168 8169 u8 reserved_at_40[0x40]; 8170 }; 8171 8172 struct mlx5_ifc_alloc_uar_out_bits { 8173 u8 status[0x8]; 8174 u8 reserved_at_8[0x18]; 8175 8176 u8 syndrome[0x20]; 8177 8178 u8 reserved_at_40[0x8]; 8179 u8 uar[0x18]; 8180 8181 u8 reserved_at_60[0x20]; 8182 }; 8183 8184 struct mlx5_ifc_alloc_uar_in_bits { 8185 u8 opcode[0x10]; 8186 u8 reserved_at_10[0x10]; 8187 8188 u8 reserved_at_20[0x10]; 8189 u8 op_mod[0x10]; 8190 8191 u8 reserved_at_40[0x40]; 8192 }; 8193 8194 struct mlx5_ifc_alloc_transport_domain_out_bits { 8195 u8 status[0x8]; 8196 u8 reserved_at_8[0x18]; 8197 8198 u8 syndrome[0x20]; 8199 8200 u8 reserved_at_40[0x8]; 8201 u8 transport_domain[0x18]; 8202 8203 u8 reserved_at_60[0x20]; 8204 }; 8205 8206 struct mlx5_ifc_alloc_transport_domain_in_bits { 8207 u8 opcode[0x10]; 8208 u8 uid[0x10]; 8209 8210 u8 reserved_at_20[0x10]; 8211 u8 op_mod[0x10]; 8212 8213 u8 reserved_at_40[0x40]; 8214 }; 8215 8216 struct mlx5_ifc_alloc_q_counter_out_bits { 8217 u8 status[0x8]; 8218 u8 reserved_at_8[0x18]; 8219 8220 u8 syndrome[0x20]; 8221 8222 u8 reserved_at_40[0x18]; 8223 u8 counter_set_id[0x8]; 8224 8225 u8 reserved_at_60[0x20]; 8226 }; 8227 8228 struct mlx5_ifc_alloc_q_counter_in_bits { 8229 u8 opcode[0x10]; 8230 u8 uid[0x10]; 8231 8232 u8 reserved_at_20[0x10]; 8233 u8 op_mod[0x10]; 8234 8235 u8 reserved_at_40[0x40]; 8236 }; 8237 8238 struct mlx5_ifc_alloc_pd_out_bits { 8239 u8 status[0x8]; 8240 u8 reserved_at_8[0x18]; 8241 8242 u8 syndrome[0x20]; 8243 8244 u8 reserved_at_40[0x8]; 8245 u8 pd[0x18]; 8246 8247 u8 reserved_at_60[0x20]; 8248 }; 8249 8250 struct mlx5_ifc_alloc_pd_in_bits { 8251 u8 opcode[0x10]; 8252 u8 uid[0x10]; 8253 8254 u8 reserved_at_20[0x10]; 8255 u8 op_mod[0x10]; 8256 8257 u8 reserved_at_40[0x40]; 8258 }; 8259 8260 struct mlx5_ifc_alloc_flow_counter_out_bits { 8261 u8 status[0x8]; 8262 u8 reserved_at_8[0x18]; 8263 8264 u8 syndrome[0x20]; 8265 8266 u8 flow_counter_id[0x20]; 8267 8268 u8 reserved_at_60[0x20]; 8269 }; 8270 8271 struct mlx5_ifc_alloc_flow_counter_in_bits { 8272 u8 opcode[0x10]; 8273 u8 reserved_at_10[0x10]; 8274 8275 u8 reserved_at_20[0x10]; 8276 u8 op_mod[0x10]; 8277 8278 u8 reserved_at_40[0x38]; 8279 u8 flow_counter_bulk[0x8]; 8280 }; 8281 8282 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8283 u8 status[0x8]; 8284 u8 reserved_at_8[0x18]; 8285 8286 u8 syndrome[0x20]; 8287 8288 u8 reserved_at_40[0x40]; 8289 }; 8290 8291 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8292 u8 opcode[0x10]; 8293 u8 reserved_at_10[0x10]; 8294 8295 u8 reserved_at_20[0x10]; 8296 u8 op_mod[0x10]; 8297 8298 u8 reserved_at_40[0x20]; 8299 8300 u8 reserved_at_60[0x10]; 8301 u8 vxlan_udp_port[0x10]; 8302 }; 8303 8304 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8305 u8 status[0x8]; 8306 u8 reserved_at_8[0x18]; 8307 8308 u8 syndrome[0x20]; 8309 8310 u8 reserved_at_40[0x40]; 8311 }; 8312 8313 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8314 u8 rate_limit[0x20]; 8315 8316 u8 burst_upper_bound[0x20]; 8317 8318 u8 reserved_at_40[0x10]; 8319 u8 typical_packet_size[0x10]; 8320 8321 u8 reserved_at_60[0x120]; 8322 }; 8323 8324 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8325 u8 opcode[0x10]; 8326 u8 uid[0x10]; 8327 8328 u8 reserved_at_20[0x10]; 8329 u8 op_mod[0x10]; 8330 8331 u8 reserved_at_40[0x10]; 8332 u8 rate_limit_index[0x10]; 8333 8334 u8 reserved_at_60[0x20]; 8335 8336 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8337 }; 8338 8339 struct mlx5_ifc_access_register_out_bits { 8340 u8 status[0x8]; 8341 u8 reserved_at_8[0x18]; 8342 8343 u8 syndrome[0x20]; 8344 8345 u8 reserved_at_40[0x40]; 8346 8347 u8 register_data[][0x20]; 8348 }; 8349 8350 enum { 8351 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8352 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8353 }; 8354 8355 struct mlx5_ifc_access_register_in_bits { 8356 u8 opcode[0x10]; 8357 u8 reserved_at_10[0x10]; 8358 8359 u8 reserved_at_20[0x10]; 8360 u8 op_mod[0x10]; 8361 8362 u8 reserved_at_40[0x10]; 8363 u8 register_id[0x10]; 8364 8365 u8 argument[0x20]; 8366 8367 u8 register_data[][0x20]; 8368 }; 8369 8370 struct mlx5_ifc_sltp_reg_bits { 8371 u8 status[0x4]; 8372 u8 version[0x4]; 8373 u8 local_port[0x8]; 8374 u8 pnat[0x2]; 8375 u8 reserved_at_12[0x2]; 8376 u8 lane[0x4]; 8377 u8 reserved_at_18[0x8]; 8378 8379 u8 reserved_at_20[0x20]; 8380 8381 u8 reserved_at_40[0x7]; 8382 u8 polarity[0x1]; 8383 u8 ob_tap0[0x8]; 8384 u8 ob_tap1[0x8]; 8385 u8 ob_tap2[0x8]; 8386 8387 u8 reserved_at_60[0xc]; 8388 u8 ob_preemp_mode[0x4]; 8389 u8 ob_reg[0x8]; 8390 u8 ob_bias[0x8]; 8391 8392 u8 reserved_at_80[0x20]; 8393 }; 8394 8395 struct mlx5_ifc_slrg_reg_bits { 8396 u8 status[0x4]; 8397 u8 version[0x4]; 8398 u8 local_port[0x8]; 8399 u8 pnat[0x2]; 8400 u8 reserved_at_12[0x2]; 8401 u8 lane[0x4]; 8402 u8 reserved_at_18[0x8]; 8403 8404 u8 time_to_link_up[0x10]; 8405 u8 reserved_at_30[0xc]; 8406 u8 grade_lane_speed[0x4]; 8407 8408 u8 grade_version[0x8]; 8409 u8 grade[0x18]; 8410 8411 u8 reserved_at_60[0x4]; 8412 u8 height_grade_type[0x4]; 8413 u8 height_grade[0x18]; 8414 8415 u8 height_dz[0x10]; 8416 u8 height_dv[0x10]; 8417 8418 u8 reserved_at_a0[0x10]; 8419 u8 height_sigma[0x10]; 8420 8421 u8 reserved_at_c0[0x20]; 8422 8423 u8 reserved_at_e0[0x4]; 8424 u8 phase_grade_type[0x4]; 8425 u8 phase_grade[0x18]; 8426 8427 u8 reserved_at_100[0x8]; 8428 u8 phase_eo_pos[0x8]; 8429 u8 reserved_at_110[0x8]; 8430 u8 phase_eo_neg[0x8]; 8431 8432 u8 ffe_set_tested[0x10]; 8433 u8 test_errors_per_lane[0x10]; 8434 }; 8435 8436 struct mlx5_ifc_pvlc_reg_bits { 8437 u8 reserved_at_0[0x8]; 8438 u8 local_port[0x8]; 8439 u8 reserved_at_10[0x10]; 8440 8441 u8 reserved_at_20[0x1c]; 8442 u8 vl_hw_cap[0x4]; 8443 8444 u8 reserved_at_40[0x1c]; 8445 u8 vl_admin[0x4]; 8446 8447 u8 reserved_at_60[0x1c]; 8448 u8 vl_operational[0x4]; 8449 }; 8450 8451 struct mlx5_ifc_pude_reg_bits { 8452 u8 swid[0x8]; 8453 u8 local_port[0x8]; 8454 u8 reserved_at_10[0x4]; 8455 u8 admin_status[0x4]; 8456 u8 reserved_at_18[0x4]; 8457 u8 oper_status[0x4]; 8458 8459 u8 reserved_at_20[0x60]; 8460 }; 8461 8462 struct mlx5_ifc_ptys_reg_bits { 8463 u8 reserved_at_0[0x1]; 8464 u8 an_disable_admin[0x1]; 8465 u8 an_disable_cap[0x1]; 8466 u8 reserved_at_3[0x5]; 8467 u8 local_port[0x8]; 8468 u8 reserved_at_10[0xd]; 8469 u8 proto_mask[0x3]; 8470 8471 u8 an_status[0x4]; 8472 u8 reserved_at_24[0xc]; 8473 u8 data_rate_oper[0x10]; 8474 8475 u8 ext_eth_proto_capability[0x20]; 8476 8477 u8 eth_proto_capability[0x20]; 8478 8479 u8 ib_link_width_capability[0x10]; 8480 u8 ib_proto_capability[0x10]; 8481 8482 u8 ext_eth_proto_admin[0x20]; 8483 8484 u8 eth_proto_admin[0x20]; 8485 8486 u8 ib_link_width_admin[0x10]; 8487 u8 ib_proto_admin[0x10]; 8488 8489 u8 ext_eth_proto_oper[0x20]; 8490 8491 u8 eth_proto_oper[0x20]; 8492 8493 u8 ib_link_width_oper[0x10]; 8494 u8 ib_proto_oper[0x10]; 8495 8496 u8 reserved_at_160[0x1c]; 8497 u8 connector_type[0x4]; 8498 8499 u8 eth_proto_lp_advertise[0x20]; 8500 8501 u8 reserved_at_1a0[0x60]; 8502 }; 8503 8504 struct mlx5_ifc_mlcr_reg_bits { 8505 u8 reserved_at_0[0x8]; 8506 u8 local_port[0x8]; 8507 u8 reserved_at_10[0x20]; 8508 8509 u8 beacon_duration[0x10]; 8510 u8 reserved_at_40[0x10]; 8511 8512 u8 beacon_remain[0x10]; 8513 }; 8514 8515 struct mlx5_ifc_ptas_reg_bits { 8516 u8 reserved_at_0[0x20]; 8517 8518 u8 algorithm_options[0x10]; 8519 u8 reserved_at_30[0x4]; 8520 u8 repetitions_mode[0x4]; 8521 u8 num_of_repetitions[0x8]; 8522 8523 u8 grade_version[0x8]; 8524 u8 height_grade_type[0x4]; 8525 u8 phase_grade_type[0x4]; 8526 u8 height_grade_weight[0x8]; 8527 u8 phase_grade_weight[0x8]; 8528 8529 u8 gisim_measure_bits[0x10]; 8530 u8 adaptive_tap_measure_bits[0x10]; 8531 8532 u8 ber_bath_high_error_threshold[0x10]; 8533 u8 ber_bath_mid_error_threshold[0x10]; 8534 8535 u8 ber_bath_low_error_threshold[0x10]; 8536 u8 one_ratio_high_threshold[0x10]; 8537 8538 u8 one_ratio_high_mid_threshold[0x10]; 8539 u8 one_ratio_low_mid_threshold[0x10]; 8540 8541 u8 one_ratio_low_threshold[0x10]; 8542 u8 ndeo_error_threshold[0x10]; 8543 8544 u8 mixer_offset_step_size[0x10]; 8545 u8 reserved_at_110[0x8]; 8546 u8 mix90_phase_for_voltage_bath[0x8]; 8547 8548 u8 mixer_offset_start[0x10]; 8549 u8 mixer_offset_end[0x10]; 8550 8551 u8 reserved_at_140[0x15]; 8552 u8 ber_test_time[0xb]; 8553 }; 8554 8555 struct mlx5_ifc_pspa_reg_bits { 8556 u8 swid[0x8]; 8557 u8 local_port[0x8]; 8558 u8 sub_port[0x8]; 8559 u8 reserved_at_18[0x8]; 8560 8561 u8 reserved_at_20[0x20]; 8562 }; 8563 8564 struct mlx5_ifc_pqdr_reg_bits { 8565 u8 reserved_at_0[0x8]; 8566 u8 local_port[0x8]; 8567 u8 reserved_at_10[0x5]; 8568 u8 prio[0x3]; 8569 u8 reserved_at_18[0x6]; 8570 u8 mode[0x2]; 8571 8572 u8 reserved_at_20[0x20]; 8573 8574 u8 reserved_at_40[0x10]; 8575 u8 min_threshold[0x10]; 8576 8577 u8 reserved_at_60[0x10]; 8578 u8 max_threshold[0x10]; 8579 8580 u8 reserved_at_80[0x10]; 8581 u8 mark_probability_denominator[0x10]; 8582 8583 u8 reserved_at_a0[0x60]; 8584 }; 8585 8586 struct mlx5_ifc_ppsc_reg_bits { 8587 u8 reserved_at_0[0x8]; 8588 u8 local_port[0x8]; 8589 u8 reserved_at_10[0x10]; 8590 8591 u8 reserved_at_20[0x60]; 8592 8593 u8 reserved_at_80[0x1c]; 8594 u8 wrps_admin[0x4]; 8595 8596 u8 reserved_at_a0[0x1c]; 8597 u8 wrps_status[0x4]; 8598 8599 u8 reserved_at_c0[0x8]; 8600 u8 up_threshold[0x8]; 8601 u8 reserved_at_d0[0x8]; 8602 u8 down_threshold[0x8]; 8603 8604 u8 reserved_at_e0[0x20]; 8605 8606 u8 reserved_at_100[0x1c]; 8607 u8 srps_admin[0x4]; 8608 8609 u8 reserved_at_120[0x1c]; 8610 u8 srps_status[0x4]; 8611 8612 u8 reserved_at_140[0x40]; 8613 }; 8614 8615 struct mlx5_ifc_pplr_reg_bits { 8616 u8 reserved_at_0[0x8]; 8617 u8 local_port[0x8]; 8618 u8 reserved_at_10[0x10]; 8619 8620 u8 reserved_at_20[0x8]; 8621 u8 lb_cap[0x8]; 8622 u8 reserved_at_30[0x8]; 8623 u8 lb_en[0x8]; 8624 }; 8625 8626 struct mlx5_ifc_pplm_reg_bits { 8627 u8 reserved_at_0[0x8]; 8628 u8 local_port[0x8]; 8629 u8 reserved_at_10[0x10]; 8630 8631 u8 reserved_at_20[0x20]; 8632 8633 u8 port_profile_mode[0x8]; 8634 u8 static_port_profile[0x8]; 8635 u8 active_port_profile[0x8]; 8636 u8 reserved_at_58[0x8]; 8637 8638 u8 retransmission_active[0x8]; 8639 u8 fec_mode_active[0x18]; 8640 8641 u8 rs_fec_correction_bypass_cap[0x4]; 8642 u8 reserved_at_84[0x8]; 8643 u8 fec_override_cap_56g[0x4]; 8644 u8 fec_override_cap_100g[0x4]; 8645 u8 fec_override_cap_50g[0x4]; 8646 u8 fec_override_cap_25g[0x4]; 8647 u8 fec_override_cap_10g_40g[0x4]; 8648 8649 u8 rs_fec_correction_bypass_admin[0x4]; 8650 u8 reserved_at_a4[0x8]; 8651 u8 fec_override_admin_56g[0x4]; 8652 u8 fec_override_admin_100g[0x4]; 8653 u8 fec_override_admin_50g[0x4]; 8654 u8 fec_override_admin_25g[0x4]; 8655 u8 fec_override_admin_10g_40g[0x4]; 8656 8657 u8 fec_override_cap_400g_8x[0x10]; 8658 u8 fec_override_cap_200g_4x[0x10]; 8659 8660 u8 fec_override_cap_100g_2x[0x10]; 8661 u8 fec_override_cap_50g_1x[0x10]; 8662 8663 u8 fec_override_admin_400g_8x[0x10]; 8664 u8 fec_override_admin_200g_4x[0x10]; 8665 8666 u8 fec_override_admin_100g_2x[0x10]; 8667 u8 fec_override_admin_50g_1x[0x10]; 8668 }; 8669 8670 struct mlx5_ifc_ppcnt_reg_bits { 8671 u8 swid[0x8]; 8672 u8 local_port[0x8]; 8673 u8 pnat[0x2]; 8674 u8 reserved_at_12[0x8]; 8675 u8 grp[0x6]; 8676 8677 u8 clr[0x1]; 8678 u8 reserved_at_21[0x1c]; 8679 u8 prio_tc[0x3]; 8680 8681 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8682 }; 8683 8684 struct mlx5_ifc_mpein_reg_bits { 8685 u8 reserved_at_0[0x2]; 8686 u8 depth[0x6]; 8687 u8 pcie_index[0x8]; 8688 u8 node[0x8]; 8689 u8 reserved_at_18[0x8]; 8690 8691 u8 capability_mask[0x20]; 8692 8693 u8 reserved_at_40[0x8]; 8694 u8 link_width_enabled[0x8]; 8695 u8 link_speed_enabled[0x10]; 8696 8697 u8 lane0_physical_position[0x8]; 8698 u8 link_width_active[0x8]; 8699 u8 link_speed_active[0x10]; 8700 8701 u8 num_of_pfs[0x10]; 8702 u8 num_of_vfs[0x10]; 8703 8704 u8 bdf0[0x10]; 8705 u8 reserved_at_b0[0x10]; 8706 8707 u8 max_read_request_size[0x4]; 8708 u8 max_payload_size[0x4]; 8709 u8 reserved_at_c8[0x5]; 8710 u8 pwr_status[0x3]; 8711 u8 port_type[0x4]; 8712 u8 reserved_at_d4[0xb]; 8713 u8 lane_reversal[0x1]; 8714 8715 u8 reserved_at_e0[0x14]; 8716 u8 pci_power[0xc]; 8717 8718 u8 reserved_at_100[0x20]; 8719 8720 u8 device_status[0x10]; 8721 u8 port_state[0x8]; 8722 u8 reserved_at_138[0x8]; 8723 8724 u8 reserved_at_140[0x10]; 8725 u8 receiver_detect_result[0x10]; 8726 8727 u8 reserved_at_160[0x20]; 8728 }; 8729 8730 struct mlx5_ifc_mpcnt_reg_bits { 8731 u8 reserved_at_0[0x8]; 8732 u8 pcie_index[0x8]; 8733 u8 reserved_at_10[0xa]; 8734 u8 grp[0x6]; 8735 8736 u8 clr[0x1]; 8737 u8 reserved_at_21[0x1f]; 8738 8739 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8740 }; 8741 8742 struct mlx5_ifc_ppad_reg_bits { 8743 u8 reserved_at_0[0x3]; 8744 u8 single_mac[0x1]; 8745 u8 reserved_at_4[0x4]; 8746 u8 local_port[0x8]; 8747 u8 mac_47_32[0x10]; 8748 8749 u8 mac_31_0[0x20]; 8750 8751 u8 reserved_at_40[0x40]; 8752 }; 8753 8754 struct mlx5_ifc_pmtu_reg_bits { 8755 u8 reserved_at_0[0x8]; 8756 u8 local_port[0x8]; 8757 u8 reserved_at_10[0x10]; 8758 8759 u8 max_mtu[0x10]; 8760 u8 reserved_at_30[0x10]; 8761 8762 u8 admin_mtu[0x10]; 8763 u8 reserved_at_50[0x10]; 8764 8765 u8 oper_mtu[0x10]; 8766 u8 reserved_at_70[0x10]; 8767 }; 8768 8769 struct mlx5_ifc_pmpr_reg_bits { 8770 u8 reserved_at_0[0x8]; 8771 u8 module[0x8]; 8772 u8 reserved_at_10[0x10]; 8773 8774 u8 reserved_at_20[0x18]; 8775 u8 attenuation_5g[0x8]; 8776 8777 u8 reserved_at_40[0x18]; 8778 u8 attenuation_7g[0x8]; 8779 8780 u8 reserved_at_60[0x18]; 8781 u8 attenuation_12g[0x8]; 8782 }; 8783 8784 struct mlx5_ifc_pmpe_reg_bits { 8785 u8 reserved_at_0[0x8]; 8786 u8 module[0x8]; 8787 u8 reserved_at_10[0xc]; 8788 u8 module_status[0x4]; 8789 8790 u8 reserved_at_20[0x60]; 8791 }; 8792 8793 struct mlx5_ifc_pmpc_reg_bits { 8794 u8 module_state_updated[32][0x8]; 8795 }; 8796 8797 struct mlx5_ifc_pmlpn_reg_bits { 8798 u8 reserved_at_0[0x4]; 8799 u8 mlpn_status[0x4]; 8800 u8 local_port[0x8]; 8801 u8 reserved_at_10[0x10]; 8802 8803 u8 e[0x1]; 8804 u8 reserved_at_21[0x1f]; 8805 }; 8806 8807 struct mlx5_ifc_pmlp_reg_bits { 8808 u8 rxtx[0x1]; 8809 u8 reserved_at_1[0x7]; 8810 u8 local_port[0x8]; 8811 u8 reserved_at_10[0x8]; 8812 u8 width[0x8]; 8813 8814 u8 lane0_module_mapping[0x20]; 8815 8816 u8 lane1_module_mapping[0x20]; 8817 8818 u8 lane2_module_mapping[0x20]; 8819 8820 u8 lane3_module_mapping[0x20]; 8821 8822 u8 reserved_at_a0[0x160]; 8823 }; 8824 8825 struct mlx5_ifc_pmaos_reg_bits { 8826 u8 reserved_at_0[0x8]; 8827 u8 module[0x8]; 8828 u8 reserved_at_10[0x4]; 8829 u8 admin_status[0x4]; 8830 u8 reserved_at_18[0x4]; 8831 u8 oper_status[0x4]; 8832 8833 u8 ase[0x1]; 8834 u8 ee[0x1]; 8835 u8 reserved_at_22[0x1c]; 8836 u8 e[0x2]; 8837 8838 u8 reserved_at_40[0x40]; 8839 }; 8840 8841 struct mlx5_ifc_plpc_reg_bits { 8842 u8 reserved_at_0[0x4]; 8843 u8 profile_id[0xc]; 8844 u8 reserved_at_10[0x4]; 8845 u8 proto_mask[0x4]; 8846 u8 reserved_at_18[0x8]; 8847 8848 u8 reserved_at_20[0x10]; 8849 u8 lane_speed[0x10]; 8850 8851 u8 reserved_at_40[0x17]; 8852 u8 lpbf[0x1]; 8853 u8 fec_mode_policy[0x8]; 8854 8855 u8 retransmission_capability[0x8]; 8856 u8 fec_mode_capability[0x18]; 8857 8858 u8 retransmission_support_admin[0x8]; 8859 u8 fec_mode_support_admin[0x18]; 8860 8861 u8 retransmission_request_admin[0x8]; 8862 u8 fec_mode_request_admin[0x18]; 8863 8864 u8 reserved_at_c0[0x80]; 8865 }; 8866 8867 struct mlx5_ifc_plib_reg_bits { 8868 u8 reserved_at_0[0x8]; 8869 u8 local_port[0x8]; 8870 u8 reserved_at_10[0x8]; 8871 u8 ib_port[0x8]; 8872 8873 u8 reserved_at_20[0x60]; 8874 }; 8875 8876 struct mlx5_ifc_plbf_reg_bits { 8877 u8 reserved_at_0[0x8]; 8878 u8 local_port[0x8]; 8879 u8 reserved_at_10[0xd]; 8880 u8 lbf_mode[0x3]; 8881 8882 u8 reserved_at_20[0x20]; 8883 }; 8884 8885 struct mlx5_ifc_pipg_reg_bits { 8886 u8 reserved_at_0[0x8]; 8887 u8 local_port[0x8]; 8888 u8 reserved_at_10[0x10]; 8889 8890 u8 dic[0x1]; 8891 u8 reserved_at_21[0x19]; 8892 u8 ipg[0x4]; 8893 u8 reserved_at_3e[0x2]; 8894 }; 8895 8896 struct mlx5_ifc_pifr_reg_bits { 8897 u8 reserved_at_0[0x8]; 8898 u8 local_port[0x8]; 8899 u8 reserved_at_10[0x10]; 8900 8901 u8 reserved_at_20[0xe0]; 8902 8903 u8 port_filter[8][0x20]; 8904 8905 u8 port_filter_update_en[8][0x20]; 8906 }; 8907 8908 struct mlx5_ifc_pfcc_reg_bits { 8909 u8 reserved_at_0[0x8]; 8910 u8 local_port[0x8]; 8911 u8 reserved_at_10[0xb]; 8912 u8 ppan_mask_n[0x1]; 8913 u8 minor_stall_mask[0x1]; 8914 u8 critical_stall_mask[0x1]; 8915 u8 reserved_at_1e[0x2]; 8916 8917 u8 ppan[0x4]; 8918 u8 reserved_at_24[0x4]; 8919 u8 prio_mask_tx[0x8]; 8920 u8 reserved_at_30[0x8]; 8921 u8 prio_mask_rx[0x8]; 8922 8923 u8 pptx[0x1]; 8924 u8 aptx[0x1]; 8925 u8 pptx_mask_n[0x1]; 8926 u8 reserved_at_43[0x5]; 8927 u8 pfctx[0x8]; 8928 u8 reserved_at_50[0x10]; 8929 8930 u8 pprx[0x1]; 8931 u8 aprx[0x1]; 8932 u8 pprx_mask_n[0x1]; 8933 u8 reserved_at_63[0x5]; 8934 u8 pfcrx[0x8]; 8935 u8 reserved_at_70[0x10]; 8936 8937 u8 device_stall_minor_watermark[0x10]; 8938 u8 device_stall_critical_watermark[0x10]; 8939 8940 u8 reserved_at_a0[0x60]; 8941 }; 8942 8943 struct mlx5_ifc_pelc_reg_bits { 8944 u8 op[0x4]; 8945 u8 reserved_at_4[0x4]; 8946 u8 local_port[0x8]; 8947 u8 reserved_at_10[0x10]; 8948 8949 u8 op_admin[0x8]; 8950 u8 op_capability[0x8]; 8951 u8 op_request[0x8]; 8952 u8 op_active[0x8]; 8953 8954 u8 admin[0x40]; 8955 8956 u8 capability[0x40]; 8957 8958 u8 request[0x40]; 8959 8960 u8 active[0x40]; 8961 8962 u8 reserved_at_140[0x80]; 8963 }; 8964 8965 struct mlx5_ifc_peir_reg_bits { 8966 u8 reserved_at_0[0x8]; 8967 u8 local_port[0x8]; 8968 u8 reserved_at_10[0x10]; 8969 8970 u8 reserved_at_20[0xc]; 8971 u8 error_count[0x4]; 8972 u8 reserved_at_30[0x10]; 8973 8974 u8 reserved_at_40[0xc]; 8975 u8 lane[0x4]; 8976 u8 reserved_at_50[0x8]; 8977 u8 error_type[0x8]; 8978 }; 8979 8980 struct mlx5_ifc_mpegc_reg_bits { 8981 u8 reserved_at_0[0x30]; 8982 u8 field_select[0x10]; 8983 8984 u8 tx_overflow_sense[0x1]; 8985 u8 mark_cqe[0x1]; 8986 u8 mark_cnp[0x1]; 8987 u8 reserved_at_43[0x1b]; 8988 u8 tx_lossy_overflow_oper[0x2]; 8989 8990 u8 reserved_at_60[0x100]; 8991 }; 8992 8993 struct mlx5_ifc_pcam_enhanced_features_bits { 8994 u8 reserved_at_0[0x68]; 8995 u8 fec_50G_per_lane_in_pplm[0x1]; 8996 u8 reserved_at_69[0x4]; 8997 u8 rx_icrc_encapsulated_counter[0x1]; 8998 u8 reserved_at_6e[0x4]; 8999 u8 ptys_extended_ethernet[0x1]; 9000 u8 reserved_at_73[0x3]; 9001 u8 pfcc_mask[0x1]; 9002 u8 reserved_at_77[0x3]; 9003 u8 per_lane_error_counters[0x1]; 9004 u8 rx_buffer_fullness_counters[0x1]; 9005 u8 ptys_connector_type[0x1]; 9006 u8 reserved_at_7d[0x1]; 9007 u8 ppcnt_discard_group[0x1]; 9008 u8 ppcnt_statistical_group[0x1]; 9009 }; 9010 9011 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9012 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9013 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9014 9015 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9016 u8 pplm[0x1]; 9017 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9018 9019 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9020 u8 pbmc[0x1]; 9021 u8 pptb[0x1]; 9022 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9023 u8 ppcnt[0x1]; 9024 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9025 }; 9026 9027 struct mlx5_ifc_pcam_reg_bits { 9028 u8 reserved_at_0[0x8]; 9029 u8 feature_group[0x8]; 9030 u8 reserved_at_10[0x8]; 9031 u8 access_reg_group[0x8]; 9032 9033 u8 reserved_at_20[0x20]; 9034 9035 union { 9036 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9037 u8 reserved_at_0[0x80]; 9038 } port_access_reg_cap_mask; 9039 9040 u8 reserved_at_c0[0x80]; 9041 9042 union { 9043 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9044 u8 reserved_at_0[0x80]; 9045 } feature_cap_mask; 9046 9047 u8 reserved_at_1c0[0xc0]; 9048 }; 9049 9050 struct mlx5_ifc_mcam_enhanced_features_bits { 9051 u8 reserved_at_0[0x6e]; 9052 u8 pci_status_and_power[0x1]; 9053 u8 reserved_at_6f[0x5]; 9054 u8 mark_tx_action_cnp[0x1]; 9055 u8 mark_tx_action_cqe[0x1]; 9056 u8 dynamic_tx_overflow[0x1]; 9057 u8 reserved_at_77[0x4]; 9058 u8 pcie_outbound_stalled[0x1]; 9059 u8 tx_overflow_buffer_pkt[0x1]; 9060 u8 mtpps_enh_out_per_adj[0x1]; 9061 u8 mtpps_fs[0x1]; 9062 u8 pcie_performance_group[0x1]; 9063 }; 9064 9065 struct mlx5_ifc_mcam_access_reg_bits { 9066 u8 reserved_at_0[0x1c]; 9067 u8 mcda[0x1]; 9068 u8 mcc[0x1]; 9069 u8 mcqi[0x1]; 9070 u8 mcqs[0x1]; 9071 9072 u8 regs_95_to_87[0x9]; 9073 u8 mpegc[0x1]; 9074 u8 regs_85_to_68[0x12]; 9075 u8 tracer_registers[0x4]; 9076 9077 u8 regs_63_to_32[0x20]; 9078 u8 regs_31_to_0[0x20]; 9079 }; 9080 9081 struct mlx5_ifc_mcam_access_reg_bits1 { 9082 u8 regs_127_to_96[0x20]; 9083 9084 u8 regs_95_to_64[0x20]; 9085 9086 u8 regs_63_to_32[0x20]; 9087 9088 u8 regs_31_to_0[0x20]; 9089 }; 9090 9091 struct mlx5_ifc_mcam_access_reg_bits2 { 9092 u8 regs_127_to_99[0x1d]; 9093 u8 mirc[0x1]; 9094 u8 regs_97_to_96[0x2]; 9095 9096 u8 regs_95_to_64[0x20]; 9097 9098 u8 regs_63_to_32[0x20]; 9099 9100 u8 regs_31_to_0[0x20]; 9101 }; 9102 9103 struct mlx5_ifc_mcam_reg_bits { 9104 u8 reserved_at_0[0x8]; 9105 u8 feature_group[0x8]; 9106 u8 reserved_at_10[0x8]; 9107 u8 access_reg_group[0x8]; 9108 9109 u8 reserved_at_20[0x20]; 9110 9111 union { 9112 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9113 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9114 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9115 u8 reserved_at_0[0x80]; 9116 } mng_access_reg_cap_mask; 9117 9118 u8 reserved_at_c0[0x80]; 9119 9120 union { 9121 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9122 u8 reserved_at_0[0x80]; 9123 } mng_feature_cap_mask; 9124 9125 u8 reserved_at_1c0[0x80]; 9126 }; 9127 9128 struct mlx5_ifc_qcam_access_reg_cap_mask { 9129 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9130 u8 qpdpm[0x1]; 9131 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9132 u8 qdpm[0x1]; 9133 u8 qpts[0x1]; 9134 u8 qcap[0x1]; 9135 u8 qcam_access_reg_cap_mask_0[0x1]; 9136 }; 9137 9138 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9139 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9140 u8 qpts_trust_both[0x1]; 9141 }; 9142 9143 struct mlx5_ifc_qcam_reg_bits { 9144 u8 reserved_at_0[0x8]; 9145 u8 feature_group[0x8]; 9146 u8 reserved_at_10[0x8]; 9147 u8 access_reg_group[0x8]; 9148 u8 reserved_at_20[0x20]; 9149 9150 union { 9151 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9152 u8 reserved_at_0[0x80]; 9153 } qos_access_reg_cap_mask; 9154 9155 u8 reserved_at_c0[0x80]; 9156 9157 union { 9158 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9159 u8 reserved_at_0[0x80]; 9160 } qos_feature_cap_mask; 9161 9162 u8 reserved_at_1c0[0x80]; 9163 }; 9164 9165 struct mlx5_ifc_core_dump_reg_bits { 9166 u8 reserved_at_0[0x18]; 9167 u8 core_dump_type[0x8]; 9168 9169 u8 reserved_at_20[0x30]; 9170 u8 vhca_id[0x10]; 9171 9172 u8 reserved_at_60[0x8]; 9173 u8 qpn[0x18]; 9174 u8 reserved_at_80[0x180]; 9175 }; 9176 9177 struct mlx5_ifc_pcap_reg_bits { 9178 u8 reserved_at_0[0x8]; 9179 u8 local_port[0x8]; 9180 u8 reserved_at_10[0x10]; 9181 9182 u8 port_capability_mask[4][0x20]; 9183 }; 9184 9185 struct mlx5_ifc_paos_reg_bits { 9186 u8 swid[0x8]; 9187 u8 local_port[0x8]; 9188 u8 reserved_at_10[0x4]; 9189 u8 admin_status[0x4]; 9190 u8 reserved_at_18[0x4]; 9191 u8 oper_status[0x4]; 9192 9193 u8 ase[0x1]; 9194 u8 ee[0x1]; 9195 u8 reserved_at_22[0x1c]; 9196 u8 e[0x2]; 9197 9198 u8 reserved_at_40[0x40]; 9199 }; 9200 9201 struct mlx5_ifc_pamp_reg_bits { 9202 u8 reserved_at_0[0x8]; 9203 u8 opamp_group[0x8]; 9204 u8 reserved_at_10[0xc]; 9205 u8 opamp_group_type[0x4]; 9206 9207 u8 start_index[0x10]; 9208 u8 reserved_at_30[0x4]; 9209 u8 num_of_indices[0xc]; 9210 9211 u8 index_data[18][0x10]; 9212 }; 9213 9214 struct mlx5_ifc_pcmr_reg_bits { 9215 u8 reserved_at_0[0x8]; 9216 u8 local_port[0x8]; 9217 u8 reserved_at_10[0x10]; 9218 u8 entropy_force_cap[0x1]; 9219 u8 entropy_calc_cap[0x1]; 9220 u8 entropy_gre_calc_cap[0x1]; 9221 u8 reserved_at_23[0x1b]; 9222 u8 fcs_cap[0x1]; 9223 u8 reserved_at_3f[0x1]; 9224 u8 entropy_force[0x1]; 9225 u8 entropy_calc[0x1]; 9226 u8 entropy_gre_calc[0x1]; 9227 u8 reserved_at_43[0x1b]; 9228 u8 fcs_chk[0x1]; 9229 u8 reserved_at_5f[0x1]; 9230 }; 9231 9232 struct mlx5_ifc_lane_2_module_mapping_bits { 9233 u8 reserved_at_0[0x6]; 9234 u8 rx_lane[0x2]; 9235 u8 reserved_at_8[0x6]; 9236 u8 tx_lane[0x2]; 9237 u8 reserved_at_10[0x8]; 9238 u8 module[0x8]; 9239 }; 9240 9241 struct mlx5_ifc_bufferx_reg_bits { 9242 u8 reserved_at_0[0x6]; 9243 u8 lossy[0x1]; 9244 u8 epsb[0x1]; 9245 u8 reserved_at_8[0xc]; 9246 u8 size[0xc]; 9247 9248 u8 xoff_threshold[0x10]; 9249 u8 xon_threshold[0x10]; 9250 }; 9251 9252 struct mlx5_ifc_set_node_in_bits { 9253 u8 node_description[64][0x8]; 9254 }; 9255 9256 struct mlx5_ifc_register_power_settings_bits { 9257 u8 reserved_at_0[0x18]; 9258 u8 power_settings_level[0x8]; 9259 9260 u8 reserved_at_20[0x60]; 9261 }; 9262 9263 struct mlx5_ifc_register_host_endianness_bits { 9264 u8 he[0x1]; 9265 u8 reserved_at_1[0x1f]; 9266 9267 u8 reserved_at_20[0x60]; 9268 }; 9269 9270 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9271 u8 reserved_at_0[0x20]; 9272 9273 u8 mkey[0x20]; 9274 9275 u8 addressh_63_32[0x20]; 9276 9277 u8 addressl_31_0[0x20]; 9278 }; 9279 9280 struct mlx5_ifc_ud_adrs_vector_bits { 9281 u8 dc_key[0x40]; 9282 9283 u8 ext[0x1]; 9284 u8 reserved_at_41[0x7]; 9285 u8 destination_qp_dct[0x18]; 9286 9287 u8 static_rate[0x4]; 9288 u8 sl_eth_prio[0x4]; 9289 u8 fl[0x1]; 9290 u8 mlid[0x7]; 9291 u8 rlid_udp_sport[0x10]; 9292 9293 u8 reserved_at_80[0x20]; 9294 9295 u8 rmac_47_16[0x20]; 9296 9297 u8 rmac_15_0[0x10]; 9298 u8 tclass[0x8]; 9299 u8 hop_limit[0x8]; 9300 9301 u8 reserved_at_e0[0x1]; 9302 u8 grh[0x1]; 9303 u8 reserved_at_e2[0x2]; 9304 u8 src_addr_index[0x8]; 9305 u8 flow_label[0x14]; 9306 9307 u8 rgid_rip[16][0x8]; 9308 }; 9309 9310 struct mlx5_ifc_pages_req_event_bits { 9311 u8 reserved_at_0[0x10]; 9312 u8 function_id[0x10]; 9313 9314 u8 num_pages[0x20]; 9315 9316 u8 reserved_at_40[0xa0]; 9317 }; 9318 9319 struct mlx5_ifc_eqe_bits { 9320 u8 reserved_at_0[0x8]; 9321 u8 event_type[0x8]; 9322 u8 reserved_at_10[0x8]; 9323 u8 event_sub_type[0x8]; 9324 9325 u8 reserved_at_20[0xe0]; 9326 9327 union mlx5_ifc_event_auto_bits event_data; 9328 9329 u8 reserved_at_1e0[0x10]; 9330 u8 signature[0x8]; 9331 u8 reserved_at_1f8[0x7]; 9332 u8 owner[0x1]; 9333 }; 9334 9335 enum { 9336 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9337 }; 9338 9339 struct mlx5_ifc_cmd_queue_entry_bits { 9340 u8 type[0x8]; 9341 u8 reserved_at_8[0x18]; 9342 9343 u8 input_length[0x20]; 9344 9345 u8 input_mailbox_pointer_63_32[0x20]; 9346 9347 u8 input_mailbox_pointer_31_9[0x17]; 9348 u8 reserved_at_77[0x9]; 9349 9350 u8 command_input_inline_data[16][0x8]; 9351 9352 u8 command_output_inline_data[16][0x8]; 9353 9354 u8 output_mailbox_pointer_63_32[0x20]; 9355 9356 u8 output_mailbox_pointer_31_9[0x17]; 9357 u8 reserved_at_1b7[0x9]; 9358 9359 u8 output_length[0x20]; 9360 9361 u8 token[0x8]; 9362 u8 signature[0x8]; 9363 u8 reserved_at_1f0[0x8]; 9364 u8 status[0x7]; 9365 u8 ownership[0x1]; 9366 }; 9367 9368 struct mlx5_ifc_cmd_out_bits { 9369 u8 status[0x8]; 9370 u8 reserved_at_8[0x18]; 9371 9372 u8 syndrome[0x20]; 9373 9374 u8 command_output[0x20]; 9375 }; 9376 9377 struct mlx5_ifc_cmd_in_bits { 9378 u8 opcode[0x10]; 9379 u8 reserved_at_10[0x10]; 9380 9381 u8 reserved_at_20[0x10]; 9382 u8 op_mod[0x10]; 9383 9384 u8 command[][0x20]; 9385 }; 9386 9387 struct mlx5_ifc_cmd_if_box_bits { 9388 u8 mailbox_data[512][0x8]; 9389 9390 u8 reserved_at_1000[0x180]; 9391 9392 u8 next_pointer_63_32[0x20]; 9393 9394 u8 next_pointer_31_10[0x16]; 9395 u8 reserved_at_11b6[0xa]; 9396 9397 u8 block_number[0x20]; 9398 9399 u8 reserved_at_11e0[0x8]; 9400 u8 token[0x8]; 9401 u8 ctrl_signature[0x8]; 9402 u8 signature[0x8]; 9403 }; 9404 9405 struct mlx5_ifc_mtt_bits { 9406 u8 ptag_63_32[0x20]; 9407 9408 u8 ptag_31_8[0x18]; 9409 u8 reserved_at_38[0x6]; 9410 u8 wr_en[0x1]; 9411 u8 rd_en[0x1]; 9412 }; 9413 9414 struct mlx5_ifc_query_wol_rol_out_bits { 9415 u8 status[0x8]; 9416 u8 reserved_at_8[0x18]; 9417 9418 u8 syndrome[0x20]; 9419 9420 u8 reserved_at_40[0x10]; 9421 u8 rol_mode[0x8]; 9422 u8 wol_mode[0x8]; 9423 9424 u8 reserved_at_60[0x20]; 9425 }; 9426 9427 struct mlx5_ifc_query_wol_rol_in_bits { 9428 u8 opcode[0x10]; 9429 u8 reserved_at_10[0x10]; 9430 9431 u8 reserved_at_20[0x10]; 9432 u8 op_mod[0x10]; 9433 9434 u8 reserved_at_40[0x40]; 9435 }; 9436 9437 struct mlx5_ifc_set_wol_rol_out_bits { 9438 u8 status[0x8]; 9439 u8 reserved_at_8[0x18]; 9440 9441 u8 syndrome[0x20]; 9442 9443 u8 reserved_at_40[0x40]; 9444 }; 9445 9446 struct mlx5_ifc_set_wol_rol_in_bits { 9447 u8 opcode[0x10]; 9448 u8 reserved_at_10[0x10]; 9449 9450 u8 reserved_at_20[0x10]; 9451 u8 op_mod[0x10]; 9452 9453 u8 rol_mode_valid[0x1]; 9454 u8 wol_mode_valid[0x1]; 9455 u8 reserved_at_42[0xe]; 9456 u8 rol_mode[0x8]; 9457 u8 wol_mode[0x8]; 9458 9459 u8 reserved_at_60[0x20]; 9460 }; 9461 9462 enum { 9463 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9464 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9465 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9466 }; 9467 9468 enum { 9469 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9470 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9471 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9472 }; 9473 9474 enum { 9475 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9476 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9477 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9478 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9479 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9480 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9481 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9482 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9483 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9484 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9485 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9486 }; 9487 9488 struct mlx5_ifc_initial_seg_bits { 9489 u8 fw_rev_minor[0x10]; 9490 u8 fw_rev_major[0x10]; 9491 9492 u8 cmd_interface_rev[0x10]; 9493 u8 fw_rev_subminor[0x10]; 9494 9495 u8 reserved_at_40[0x40]; 9496 9497 u8 cmdq_phy_addr_63_32[0x20]; 9498 9499 u8 cmdq_phy_addr_31_12[0x14]; 9500 u8 reserved_at_b4[0x2]; 9501 u8 nic_interface[0x2]; 9502 u8 log_cmdq_size[0x4]; 9503 u8 log_cmdq_stride[0x4]; 9504 9505 u8 command_doorbell_vector[0x20]; 9506 9507 u8 reserved_at_e0[0xf00]; 9508 9509 u8 initializing[0x1]; 9510 u8 reserved_at_fe1[0x4]; 9511 u8 nic_interface_supported[0x3]; 9512 u8 embedded_cpu[0x1]; 9513 u8 reserved_at_fe9[0x17]; 9514 9515 struct mlx5_ifc_health_buffer_bits health_buffer; 9516 9517 u8 no_dram_nic_offset[0x20]; 9518 9519 u8 reserved_at_1220[0x6e40]; 9520 9521 u8 reserved_at_8060[0x1f]; 9522 u8 clear_int[0x1]; 9523 9524 u8 health_syndrome[0x8]; 9525 u8 health_counter[0x18]; 9526 9527 u8 reserved_at_80a0[0x17fc0]; 9528 }; 9529 9530 struct mlx5_ifc_mtpps_reg_bits { 9531 u8 reserved_at_0[0xc]; 9532 u8 cap_number_of_pps_pins[0x4]; 9533 u8 reserved_at_10[0x4]; 9534 u8 cap_max_num_of_pps_in_pins[0x4]; 9535 u8 reserved_at_18[0x4]; 9536 u8 cap_max_num_of_pps_out_pins[0x4]; 9537 9538 u8 reserved_at_20[0x24]; 9539 u8 cap_pin_3_mode[0x4]; 9540 u8 reserved_at_48[0x4]; 9541 u8 cap_pin_2_mode[0x4]; 9542 u8 reserved_at_50[0x4]; 9543 u8 cap_pin_1_mode[0x4]; 9544 u8 reserved_at_58[0x4]; 9545 u8 cap_pin_0_mode[0x4]; 9546 9547 u8 reserved_at_60[0x4]; 9548 u8 cap_pin_7_mode[0x4]; 9549 u8 reserved_at_68[0x4]; 9550 u8 cap_pin_6_mode[0x4]; 9551 u8 reserved_at_70[0x4]; 9552 u8 cap_pin_5_mode[0x4]; 9553 u8 reserved_at_78[0x4]; 9554 u8 cap_pin_4_mode[0x4]; 9555 9556 u8 field_select[0x20]; 9557 u8 reserved_at_a0[0x60]; 9558 9559 u8 enable[0x1]; 9560 u8 reserved_at_101[0xb]; 9561 u8 pattern[0x4]; 9562 u8 reserved_at_110[0x4]; 9563 u8 pin_mode[0x4]; 9564 u8 pin[0x8]; 9565 9566 u8 reserved_at_120[0x20]; 9567 9568 u8 time_stamp[0x40]; 9569 9570 u8 out_pulse_duration[0x10]; 9571 u8 out_periodic_adjustment[0x10]; 9572 u8 enhanced_out_periodic_adjustment[0x20]; 9573 9574 u8 reserved_at_1c0[0x20]; 9575 }; 9576 9577 struct mlx5_ifc_mtppse_reg_bits { 9578 u8 reserved_at_0[0x18]; 9579 u8 pin[0x8]; 9580 u8 event_arm[0x1]; 9581 u8 reserved_at_21[0x1b]; 9582 u8 event_generation_mode[0x4]; 9583 u8 reserved_at_40[0x40]; 9584 }; 9585 9586 struct mlx5_ifc_mcqs_reg_bits { 9587 u8 last_index_flag[0x1]; 9588 u8 reserved_at_1[0x7]; 9589 u8 fw_device[0x8]; 9590 u8 component_index[0x10]; 9591 9592 u8 reserved_at_20[0x10]; 9593 u8 identifier[0x10]; 9594 9595 u8 reserved_at_40[0x17]; 9596 u8 component_status[0x5]; 9597 u8 component_update_state[0x4]; 9598 9599 u8 last_update_state_changer_type[0x4]; 9600 u8 last_update_state_changer_host_id[0x4]; 9601 u8 reserved_at_68[0x18]; 9602 }; 9603 9604 struct mlx5_ifc_mcqi_cap_bits { 9605 u8 supported_info_bitmask[0x20]; 9606 9607 u8 component_size[0x20]; 9608 9609 u8 max_component_size[0x20]; 9610 9611 u8 log_mcda_word_size[0x4]; 9612 u8 reserved_at_64[0xc]; 9613 u8 mcda_max_write_size[0x10]; 9614 9615 u8 rd_en[0x1]; 9616 u8 reserved_at_81[0x1]; 9617 u8 match_chip_id[0x1]; 9618 u8 match_psid[0x1]; 9619 u8 check_user_timestamp[0x1]; 9620 u8 match_base_guid_mac[0x1]; 9621 u8 reserved_at_86[0x1a]; 9622 }; 9623 9624 struct mlx5_ifc_mcqi_version_bits { 9625 u8 reserved_at_0[0x2]; 9626 u8 build_time_valid[0x1]; 9627 u8 user_defined_time_valid[0x1]; 9628 u8 reserved_at_4[0x14]; 9629 u8 version_string_length[0x8]; 9630 9631 u8 version[0x20]; 9632 9633 u8 build_time[0x40]; 9634 9635 u8 user_defined_time[0x40]; 9636 9637 u8 build_tool_version[0x20]; 9638 9639 u8 reserved_at_e0[0x20]; 9640 9641 u8 version_string[92][0x8]; 9642 }; 9643 9644 struct mlx5_ifc_mcqi_activation_method_bits { 9645 u8 pending_server_ac_power_cycle[0x1]; 9646 u8 pending_server_dc_power_cycle[0x1]; 9647 u8 pending_server_reboot[0x1]; 9648 u8 pending_fw_reset[0x1]; 9649 u8 auto_activate[0x1]; 9650 u8 all_hosts_sync[0x1]; 9651 u8 device_hw_reset[0x1]; 9652 u8 reserved_at_7[0x19]; 9653 }; 9654 9655 union mlx5_ifc_mcqi_reg_data_bits { 9656 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9657 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9658 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9659 }; 9660 9661 struct mlx5_ifc_mcqi_reg_bits { 9662 u8 read_pending_component[0x1]; 9663 u8 reserved_at_1[0xf]; 9664 u8 component_index[0x10]; 9665 9666 u8 reserved_at_20[0x20]; 9667 9668 u8 reserved_at_40[0x1b]; 9669 u8 info_type[0x5]; 9670 9671 u8 info_size[0x20]; 9672 9673 u8 offset[0x20]; 9674 9675 u8 reserved_at_a0[0x10]; 9676 u8 data_size[0x10]; 9677 9678 union mlx5_ifc_mcqi_reg_data_bits data[]; 9679 }; 9680 9681 struct mlx5_ifc_mcc_reg_bits { 9682 u8 reserved_at_0[0x4]; 9683 u8 time_elapsed_since_last_cmd[0xc]; 9684 u8 reserved_at_10[0x8]; 9685 u8 instruction[0x8]; 9686 9687 u8 reserved_at_20[0x10]; 9688 u8 component_index[0x10]; 9689 9690 u8 reserved_at_40[0x8]; 9691 u8 update_handle[0x18]; 9692 9693 u8 handle_owner_type[0x4]; 9694 u8 handle_owner_host_id[0x4]; 9695 u8 reserved_at_68[0x1]; 9696 u8 control_progress[0x7]; 9697 u8 error_code[0x8]; 9698 u8 reserved_at_78[0x4]; 9699 u8 control_state[0x4]; 9700 9701 u8 component_size[0x20]; 9702 9703 u8 reserved_at_a0[0x60]; 9704 }; 9705 9706 struct mlx5_ifc_mcda_reg_bits { 9707 u8 reserved_at_0[0x8]; 9708 u8 update_handle[0x18]; 9709 9710 u8 offset[0x20]; 9711 9712 u8 reserved_at_40[0x10]; 9713 u8 size[0x10]; 9714 9715 u8 reserved_at_60[0x20]; 9716 9717 u8 data[0][0x20]; 9718 }; 9719 9720 enum { 9721 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9722 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9723 }; 9724 9725 enum { 9726 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9727 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9728 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9729 }; 9730 9731 struct mlx5_ifc_mfrl_reg_bits { 9732 u8 reserved_at_0[0x20]; 9733 9734 u8 reserved_at_20[0x2]; 9735 u8 pci_sync_for_fw_update_start[0x1]; 9736 u8 pci_sync_for_fw_update_resp[0x2]; 9737 u8 rst_type_sel[0x3]; 9738 u8 reserved_at_28[0x8]; 9739 u8 reset_type[0x8]; 9740 u8 reset_level[0x8]; 9741 }; 9742 9743 struct mlx5_ifc_mirc_reg_bits { 9744 u8 reserved_at_0[0x18]; 9745 u8 status_code[0x8]; 9746 9747 u8 reserved_at_20[0x20]; 9748 }; 9749 9750 union mlx5_ifc_ports_control_registers_document_bits { 9751 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9752 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9753 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9754 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9755 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9756 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9757 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9758 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9759 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9760 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9761 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9762 struct mlx5_ifc_paos_reg_bits paos_reg; 9763 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9764 struct mlx5_ifc_peir_reg_bits peir_reg; 9765 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9766 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9767 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9768 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9769 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9770 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9771 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9772 struct mlx5_ifc_plib_reg_bits plib_reg; 9773 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9774 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9775 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9776 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9777 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9778 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9779 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9780 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9781 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9782 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9783 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9784 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9785 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9786 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9787 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9788 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9789 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9790 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9791 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9792 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9793 struct mlx5_ifc_pude_reg_bits pude_reg; 9794 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9795 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9796 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9797 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9798 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9799 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9800 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9801 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9802 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9803 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9804 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9805 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9806 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9807 u8 reserved_at_0[0x60e0]; 9808 }; 9809 9810 union mlx5_ifc_debug_enhancements_document_bits { 9811 struct mlx5_ifc_health_buffer_bits health_buffer; 9812 u8 reserved_at_0[0x200]; 9813 }; 9814 9815 union mlx5_ifc_uplink_pci_interface_document_bits { 9816 struct mlx5_ifc_initial_seg_bits initial_seg; 9817 u8 reserved_at_0[0x20060]; 9818 }; 9819 9820 struct mlx5_ifc_set_flow_table_root_out_bits { 9821 u8 status[0x8]; 9822 u8 reserved_at_8[0x18]; 9823 9824 u8 syndrome[0x20]; 9825 9826 u8 reserved_at_40[0x40]; 9827 }; 9828 9829 struct mlx5_ifc_set_flow_table_root_in_bits { 9830 u8 opcode[0x10]; 9831 u8 reserved_at_10[0x10]; 9832 9833 u8 reserved_at_20[0x10]; 9834 u8 op_mod[0x10]; 9835 9836 u8 other_vport[0x1]; 9837 u8 reserved_at_41[0xf]; 9838 u8 vport_number[0x10]; 9839 9840 u8 reserved_at_60[0x20]; 9841 9842 u8 table_type[0x8]; 9843 u8 reserved_at_88[0x18]; 9844 9845 u8 reserved_at_a0[0x8]; 9846 u8 table_id[0x18]; 9847 9848 u8 reserved_at_c0[0x8]; 9849 u8 underlay_qpn[0x18]; 9850 u8 reserved_at_e0[0x120]; 9851 }; 9852 9853 enum { 9854 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9855 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9856 }; 9857 9858 struct mlx5_ifc_modify_flow_table_out_bits { 9859 u8 status[0x8]; 9860 u8 reserved_at_8[0x18]; 9861 9862 u8 syndrome[0x20]; 9863 9864 u8 reserved_at_40[0x40]; 9865 }; 9866 9867 struct mlx5_ifc_modify_flow_table_in_bits { 9868 u8 opcode[0x10]; 9869 u8 reserved_at_10[0x10]; 9870 9871 u8 reserved_at_20[0x10]; 9872 u8 op_mod[0x10]; 9873 9874 u8 other_vport[0x1]; 9875 u8 reserved_at_41[0xf]; 9876 u8 vport_number[0x10]; 9877 9878 u8 reserved_at_60[0x10]; 9879 u8 modify_field_select[0x10]; 9880 9881 u8 table_type[0x8]; 9882 u8 reserved_at_88[0x18]; 9883 9884 u8 reserved_at_a0[0x8]; 9885 u8 table_id[0x18]; 9886 9887 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9888 }; 9889 9890 struct mlx5_ifc_ets_tcn_config_reg_bits { 9891 u8 g[0x1]; 9892 u8 b[0x1]; 9893 u8 r[0x1]; 9894 u8 reserved_at_3[0x9]; 9895 u8 group[0x4]; 9896 u8 reserved_at_10[0x9]; 9897 u8 bw_allocation[0x7]; 9898 9899 u8 reserved_at_20[0xc]; 9900 u8 max_bw_units[0x4]; 9901 u8 reserved_at_30[0x8]; 9902 u8 max_bw_value[0x8]; 9903 }; 9904 9905 struct mlx5_ifc_ets_global_config_reg_bits { 9906 u8 reserved_at_0[0x2]; 9907 u8 r[0x1]; 9908 u8 reserved_at_3[0x1d]; 9909 9910 u8 reserved_at_20[0xc]; 9911 u8 max_bw_units[0x4]; 9912 u8 reserved_at_30[0x8]; 9913 u8 max_bw_value[0x8]; 9914 }; 9915 9916 struct mlx5_ifc_qetc_reg_bits { 9917 u8 reserved_at_0[0x8]; 9918 u8 port_number[0x8]; 9919 u8 reserved_at_10[0x30]; 9920 9921 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9922 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9923 }; 9924 9925 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9926 u8 e[0x1]; 9927 u8 reserved_at_01[0x0b]; 9928 u8 prio[0x04]; 9929 }; 9930 9931 struct mlx5_ifc_qpdpm_reg_bits { 9932 u8 reserved_at_0[0x8]; 9933 u8 local_port[0x8]; 9934 u8 reserved_at_10[0x10]; 9935 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9936 }; 9937 9938 struct mlx5_ifc_qpts_reg_bits { 9939 u8 reserved_at_0[0x8]; 9940 u8 local_port[0x8]; 9941 u8 reserved_at_10[0x2d]; 9942 u8 trust_state[0x3]; 9943 }; 9944 9945 struct mlx5_ifc_pptb_reg_bits { 9946 u8 reserved_at_0[0x2]; 9947 u8 mm[0x2]; 9948 u8 reserved_at_4[0x4]; 9949 u8 local_port[0x8]; 9950 u8 reserved_at_10[0x6]; 9951 u8 cm[0x1]; 9952 u8 um[0x1]; 9953 u8 pm[0x8]; 9954 9955 u8 prio_x_buff[0x20]; 9956 9957 u8 pm_msb[0x8]; 9958 u8 reserved_at_48[0x10]; 9959 u8 ctrl_buff[0x4]; 9960 u8 untagged_buff[0x4]; 9961 }; 9962 9963 struct mlx5_ifc_pbmc_reg_bits { 9964 u8 reserved_at_0[0x8]; 9965 u8 local_port[0x8]; 9966 u8 reserved_at_10[0x10]; 9967 9968 u8 xoff_timer_value[0x10]; 9969 u8 xoff_refresh[0x10]; 9970 9971 u8 reserved_at_40[0x9]; 9972 u8 fullness_threshold[0x7]; 9973 u8 port_buffer_size[0x10]; 9974 9975 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9976 9977 u8 reserved_at_2e0[0x40]; 9978 }; 9979 9980 struct mlx5_ifc_qtct_reg_bits { 9981 u8 reserved_at_0[0x8]; 9982 u8 port_number[0x8]; 9983 u8 reserved_at_10[0xd]; 9984 u8 prio[0x3]; 9985 9986 u8 reserved_at_20[0x1d]; 9987 u8 tclass[0x3]; 9988 }; 9989 9990 struct mlx5_ifc_mcia_reg_bits { 9991 u8 l[0x1]; 9992 u8 reserved_at_1[0x7]; 9993 u8 module[0x8]; 9994 u8 reserved_at_10[0x8]; 9995 u8 status[0x8]; 9996 9997 u8 i2c_device_address[0x8]; 9998 u8 page_number[0x8]; 9999 u8 device_address[0x10]; 10000 10001 u8 reserved_at_40[0x10]; 10002 u8 size[0x10]; 10003 10004 u8 reserved_at_60[0x20]; 10005 10006 u8 dword_0[0x20]; 10007 u8 dword_1[0x20]; 10008 u8 dword_2[0x20]; 10009 u8 dword_3[0x20]; 10010 u8 dword_4[0x20]; 10011 u8 dword_5[0x20]; 10012 u8 dword_6[0x20]; 10013 u8 dword_7[0x20]; 10014 u8 dword_8[0x20]; 10015 u8 dword_9[0x20]; 10016 u8 dword_10[0x20]; 10017 u8 dword_11[0x20]; 10018 }; 10019 10020 struct mlx5_ifc_dcbx_param_bits { 10021 u8 dcbx_cee_cap[0x1]; 10022 u8 dcbx_ieee_cap[0x1]; 10023 u8 dcbx_standby_cap[0x1]; 10024 u8 reserved_at_3[0x5]; 10025 u8 port_number[0x8]; 10026 u8 reserved_at_10[0xa]; 10027 u8 max_application_table_size[6]; 10028 u8 reserved_at_20[0x15]; 10029 u8 version_oper[0x3]; 10030 u8 reserved_at_38[5]; 10031 u8 version_admin[0x3]; 10032 u8 willing_admin[0x1]; 10033 u8 reserved_at_41[0x3]; 10034 u8 pfc_cap_oper[0x4]; 10035 u8 reserved_at_48[0x4]; 10036 u8 pfc_cap_admin[0x4]; 10037 u8 reserved_at_50[0x4]; 10038 u8 num_of_tc_oper[0x4]; 10039 u8 reserved_at_58[0x4]; 10040 u8 num_of_tc_admin[0x4]; 10041 u8 remote_willing[0x1]; 10042 u8 reserved_at_61[3]; 10043 u8 remote_pfc_cap[4]; 10044 u8 reserved_at_68[0x14]; 10045 u8 remote_num_of_tc[0x4]; 10046 u8 reserved_at_80[0x18]; 10047 u8 error[0x8]; 10048 u8 reserved_at_a0[0x160]; 10049 }; 10050 10051 struct mlx5_ifc_lagc_bits { 10052 u8 reserved_at_0[0x1d]; 10053 u8 lag_state[0x3]; 10054 10055 u8 reserved_at_20[0x14]; 10056 u8 tx_remap_affinity_2[0x4]; 10057 u8 reserved_at_38[0x4]; 10058 u8 tx_remap_affinity_1[0x4]; 10059 }; 10060 10061 struct mlx5_ifc_create_lag_out_bits { 10062 u8 status[0x8]; 10063 u8 reserved_at_8[0x18]; 10064 10065 u8 syndrome[0x20]; 10066 10067 u8 reserved_at_40[0x40]; 10068 }; 10069 10070 struct mlx5_ifc_create_lag_in_bits { 10071 u8 opcode[0x10]; 10072 u8 reserved_at_10[0x10]; 10073 10074 u8 reserved_at_20[0x10]; 10075 u8 op_mod[0x10]; 10076 10077 struct mlx5_ifc_lagc_bits ctx; 10078 }; 10079 10080 struct mlx5_ifc_modify_lag_out_bits { 10081 u8 status[0x8]; 10082 u8 reserved_at_8[0x18]; 10083 10084 u8 syndrome[0x20]; 10085 10086 u8 reserved_at_40[0x40]; 10087 }; 10088 10089 struct mlx5_ifc_modify_lag_in_bits { 10090 u8 opcode[0x10]; 10091 u8 reserved_at_10[0x10]; 10092 10093 u8 reserved_at_20[0x10]; 10094 u8 op_mod[0x10]; 10095 10096 u8 reserved_at_40[0x20]; 10097 u8 field_select[0x20]; 10098 10099 struct mlx5_ifc_lagc_bits ctx; 10100 }; 10101 10102 struct mlx5_ifc_query_lag_out_bits { 10103 u8 status[0x8]; 10104 u8 reserved_at_8[0x18]; 10105 10106 u8 syndrome[0x20]; 10107 10108 struct mlx5_ifc_lagc_bits ctx; 10109 }; 10110 10111 struct mlx5_ifc_query_lag_in_bits { 10112 u8 opcode[0x10]; 10113 u8 reserved_at_10[0x10]; 10114 10115 u8 reserved_at_20[0x10]; 10116 u8 op_mod[0x10]; 10117 10118 u8 reserved_at_40[0x40]; 10119 }; 10120 10121 struct mlx5_ifc_destroy_lag_out_bits { 10122 u8 status[0x8]; 10123 u8 reserved_at_8[0x18]; 10124 10125 u8 syndrome[0x20]; 10126 10127 u8 reserved_at_40[0x40]; 10128 }; 10129 10130 struct mlx5_ifc_destroy_lag_in_bits { 10131 u8 opcode[0x10]; 10132 u8 reserved_at_10[0x10]; 10133 10134 u8 reserved_at_20[0x10]; 10135 u8 op_mod[0x10]; 10136 10137 u8 reserved_at_40[0x40]; 10138 }; 10139 10140 struct mlx5_ifc_create_vport_lag_out_bits { 10141 u8 status[0x8]; 10142 u8 reserved_at_8[0x18]; 10143 10144 u8 syndrome[0x20]; 10145 10146 u8 reserved_at_40[0x40]; 10147 }; 10148 10149 struct mlx5_ifc_create_vport_lag_in_bits { 10150 u8 opcode[0x10]; 10151 u8 reserved_at_10[0x10]; 10152 10153 u8 reserved_at_20[0x10]; 10154 u8 op_mod[0x10]; 10155 10156 u8 reserved_at_40[0x40]; 10157 }; 10158 10159 struct mlx5_ifc_destroy_vport_lag_out_bits { 10160 u8 status[0x8]; 10161 u8 reserved_at_8[0x18]; 10162 10163 u8 syndrome[0x20]; 10164 10165 u8 reserved_at_40[0x40]; 10166 }; 10167 10168 struct mlx5_ifc_destroy_vport_lag_in_bits { 10169 u8 opcode[0x10]; 10170 u8 reserved_at_10[0x10]; 10171 10172 u8 reserved_at_20[0x10]; 10173 u8 op_mod[0x10]; 10174 10175 u8 reserved_at_40[0x40]; 10176 }; 10177 10178 struct mlx5_ifc_alloc_memic_in_bits { 10179 u8 opcode[0x10]; 10180 u8 reserved_at_10[0x10]; 10181 10182 u8 reserved_at_20[0x10]; 10183 u8 op_mod[0x10]; 10184 10185 u8 reserved_at_30[0x20]; 10186 10187 u8 reserved_at_40[0x18]; 10188 u8 log_memic_addr_alignment[0x8]; 10189 10190 u8 range_start_addr[0x40]; 10191 10192 u8 range_size[0x20]; 10193 10194 u8 memic_size[0x20]; 10195 }; 10196 10197 struct mlx5_ifc_alloc_memic_out_bits { 10198 u8 status[0x8]; 10199 u8 reserved_at_8[0x18]; 10200 10201 u8 syndrome[0x20]; 10202 10203 u8 memic_start_addr[0x40]; 10204 }; 10205 10206 struct mlx5_ifc_dealloc_memic_in_bits { 10207 u8 opcode[0x10]; 10208 u8 reserved_at_10[0x10]; 10209 10210 u8 reserved_at_20[0x10]; 10211 u8 op_mod[0x10]; 10212 10213 u8 reserved_at_40[0x40]; 10214 10215 u8 memic_start_addr[0x40]; 10216 10217 u8 memic_size[0x20]; 10218 10219 u8 reserved_at_e0[0x20]; 10220 }; 10221 10222 struct mlx5_ifc_dealloc_memic_out_bits { 10223 u8 status[0x8]; 10224 u8 reserved_at_8[0x18]; 10225 10226 u8 syndrome[0x20]; 10227 10228 u8 reserved_at_40[0x40]; 10229 }; 10230 10231 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10232 u8 opcode[0x10]; 10233 u8 uid[0x10]; 10234 10235 u8 vhca_tunnel_id[0x10]; 10236 u8 obj_type[0x10]; 10237 10238 u8 obj_id[0x20]; 10239 10240 u8 reserved_at_60[0x20]; 10241 }; 10242 10243 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10244 u8 status[0x8]; 10245 u8 reserved_at_8[0x18]; 10246 10247 u8 syndrome[0x20]; 10248 10249 u8 obj_id[0x20]; 10250 10251 u8 reserved_at_60[0x20]; 10252 }; 10253 10254 struct mlx5_ifc_umem_bits { 10255 u8 reserved_at_0[0x80]; 10256 10257 u8 reserved_at_80[0x1b]; 10258 u8 log_page_size[0x5]; 10259 10260 u8 page_offset[0x20]; 10261 10262 u8 num_of_mtt[0x40]; 10263 10264 struct mlx5_ifc_mtt_bits mtt[]; 10265 }; 10266 10267 struct mlx5_ifc_uctx_bits { 10268 u8 cap[0x20]; 10269 10270 u8 reserved_at_20[0x160]; 10271 }; 10272 10273 struct mlx5_ifc_sw_icm_bits { 10274 u8 modify_field_select[0x40]; 10275 10276 u8 reserved_at_40[0x18]; 10277 u8 log_sw_icm_size[0x8]; 10278 10279 u8 reserved_at_60[0x20]; 10280 10281 u8 sw_icm_start_addr[0x40]; 10282 10283 u8 reserved_at_c0[0x140]; 10284 }; 10285 10286 struct mlx5_ifc_geneve_tlv_option_bits { 10287 u8 modify_field_select[0x40]; 10288 10289 u8 reserved_at_40[0x18]; 10290 u8 geneve_option_fte_index[0x8]; 10291 10292 u8 option_class[0x10]; 10293 u8 option_type[0x8]; 10294 u8 reserved_at_78[0x3]; 10295 u8 option_data_length[0x5]; 10296 10297 u8 reserved_at_80[0x180]; 10298 }; 10299 10300 struct mlx5_ifc_create_umem_in_bits { 10301 u8 opcode[0x10]; 10302 u8 uid[0x10]; 10303 10304 u8 reserved_at_20[0x10]; 10305 u8 op_mod[0x10]; 10306 10307 u8 reserved_at_40[0x40]; 10308 10309 struct mlx5_ifc_umem_bits umem; 10310 }; 10311 10312 struct mlx5_ifc_create_uctx_in_bits { 10313 u8 opcode[0x10]; 10314 u8 reserved_at_10[0x10]; 10315 10316 u8 reserved_at_20[0x10]; 10317 u8 op_mod[0x10]; 10318 10319 u8 reserved_at_40[0x40]; 10320 10321 struct mlx5_ifc_uctx_bits uctx; 10322 }; 10323 10324 struct mlx5_ifc_destroy_uctx_in_bits { 10325 u8 opcode[0x10]; 10326 u8 reserved_at_10[0x10]; 10327 10328 u8 reserved_at_20[0x10]; 10329 u8 op_mod[0x10]; 10330 10331 u8 reserved_at_40[0x10]; 10332 u8 uid[0x10]; 10333 10334 u8 reserved_at_60[0x20]; 10335 }; 10336 10337 struct mlx5_ifc_create_sw_icm_in_bits { 10338 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10339 struct mlx5_ifc_sw_icm_bits sw_icm; 10340 }; 10341 10342 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10343 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10344 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10345 }; 10346 10347 struct mlx5_ifc_mtrc_string_db_param_bits { 10348 u8 string_db_base_address[0x20]; 10349 10350 u8 reserved_at_20[0x8]; 10351 u8 string_db_size[0x18]; 10352 }; 10353 10354 struct mlx5_ifc_mtrc_cap_bits { 10355 u8 trace_owner[0x1]; 10356 u8 trace_to_memory[0x1]; 10357 u8 reserved_at_2[0x4]; 10358 u8 trc_ver[0x2]; 10359 u8 reserved_at_8[0x14]; 10360 u8 num_string_db[0x4]; 10361 10362 u8 first_string_trace[0x8]; 10363 u8 num_string_trace[0x8]; 10364 u8 reserved_at_30[0x28]; 10365 10366 u8 log_max_trace_buffer_size[0x8]; 10367 10368 u8 reserved_at_60[0x20]; 10369 10370 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10371 10372 u8 reserved_at_280[0x180]; 10373 }; 10374 10375 struct mlx5_ifc_mtrc_conf_bits { 10376 u8 reserved_at_0[0x1c]; 10377 u8 trace_mode[0x4]; 10378 u8 reserved_at_20[0x18]; 10379 u8 log_trace_buffer_size[0x8]; 10380 u8 trace_mkey[0x20]; 10381 u8 reserved_at_60[0x3a0]; 10382 }; 10383 10384 struct mlx5_ifc_mtrc_stdb_bits { 10385 u8 string_db_index[0x4]; 10386 u8 reserved_at_4[0x4]; 10387 u8 read_size[0x18]; 10388 u8 start_offset[0x20]; 10389 u8 string_db_data[]; 10390 }; 10391 10392 struct mlx5_ifc_mtrc_ctrl_bits { 10393 u8 trace_status[0x2]; 10394 u8 reserved_at_2[0x2]; 10395 u8 arm_event[0x1]; 10396 u8 reserved_at_5[0xb]; 10397 u8 modify_field_select[0x10]; 10398 u8 reserved_at_20[0x2b]; 10399 u8 current_timestamp52_32[0x15]; 10400 u8 current_timestamp31_0[0x20]; 10401 u8 reserved_at_80[0x180]; 10402 }; 10403 10404 struct mlx5_ifc_host_params_context_bits { 10405 u8 host_number[0x8]; 10406 u8 reserved_at_8[0x7]; 10407 u8 host_pf_disabled[0x1]; 10408 u8 host_num_of_vfs[0x10]; 10409 10410 u8 host_total_vfs[0x10]; 10411 u8 host_pci_bus[0x10]; 10412 10413 u8 reserved_at_40[0x10]; 10414 u8 host_pci_device[0x10]; 10415 10416 u8 reserved_at_60[0x10]; 10417 u8 host_pci_function[0x10]; 10418 10419 u8 reserved_at_80[0x180]; 10420 }; 10421 10422 struct mlx5_ifc_query_esw_functions_in_bits { 10423 u8 opcode[0x10]; 10424 u8 reserved_at_10[0x10]; 10425 10426 u8 reserved_at_20[0x10]; 10427 u8 op_mod[0x10]; 10428 10429 u8 reserved_at_40[0x40]; 10430 }; 10431 10432 struct mlx5_ifc_query_esw_functions_out_bits { 10433 u8 status[0x8]; 10434 u8 reserved_at_8[0x18]; 10435 10436 u8 syndrome[0x20]; 10437 10438 u8 reserved_at_40[0x40]; 10439 10440 struct mlx5_ifc_host_params_context_bits host_params_context; 10441 10442 u8 reserved_at_280[0x180]; 10443 u8 host_sf_enable[][0x40]; 10444 }; 10445 10446 struct mlx5_ifc_sf_partition_bits { 10447 u8 reserved_at_0[0x10]; 10448 u8 log_num_sf[0x8]; 10449 u8 log_sf_bar_size[0x8]; 10450 }; 10451 10452 struct mlx5_ifc_query_sf_partitions_out_bits { 10453 u8 status[0x8]; 10454 u8 reserved_at_8[0x18]; 10455 10456 u8 syndrome[0x20]; 10457 10458 u8 reserved_at_40[0x18]; 10459 u8 num_sf_partitions[0x8]; 10460 10461 u8 reserved_at_60[0x20]; 10462 10463 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10464 }; 10465 10466 struct mlx5_ifc_query_sf_partitions_in_bits { 10467 u8 opcode[0x10]; 10468 u8 reserved_at_10[0x10]; 10469 10470 u8 reserved_at_20[0x10]; 10471 u8 op_mod[0x10]; 10472 10473 u8 reserved_at_40[0x40]; 10474 }; 10475 10476 struct mlx5_ifc_dealloc_sf_out_bits { 10477 u8 status[0x8]; 10478 u8 reserved_at_8[0x18]; 10479 10480 u8 syndrome[0x20]; 10481 10482 u8 reserved_at_40[0x40]; 10483 }; 10484 10485 struct mlx5_ifc_dealloc_sf_in_bits { 10486 u8 opcode[0x10]; 10487 u8 reserved_at_10[0x10]; 10488 10489 u8 reserved_at_20[0x10]; 10490 u8 op_mod[0x10]; 10491 10492 u8 reserved_at_40[0x10]; 10493 u8 function_id[0x10]; 10494 10495 u8 reserved_at_60[0x20]; 10496 }; 10497 10498 struct mlx5_ifc_alloc_sf_out_bits { 10499 u8 status[0x8]; 10500 u8 reserved_at_8[0x18]; 10501 10502 u8 syndrome[0x20]; 10503 10504 u8 reserved_at_40[0x40]; 10505 }; 10506 10507 struct mlx5_ifc_alloc_sf_in_bits { 10508 u8 opcode[0x10]; 10509 u8 reserved_at_10[0x10]; 10510 10511 u8 reserved_at_20[0x10]; 10512 u8 op_mod[0x10]; 10513 10514 u8 reserved_at_40[0x10]; 10515 u8 function_id[0x10]; 10516 10517 u8 reserved_at_60[0x20]; 10518 }; 10519 10520 struct mlx5_ifc_affiliated_event_header_bits { 10521 u8 reserved_at_0[0x10]; 10522 u8 obj_type[0x10]; 10523 10524 u8 obj_id[0x20]; 10525 }; 10526 10527 enum { 10528 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10529 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13), 10530 }; 10531 10532 enum { 10533 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10534 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10535 }; 10536 10537 enum { 10538 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10539 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10540 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10541 }; 10542 10543 struct mlx5_ifc_ipsec_obj_bits { 10544 u8 modify_field_select[0x40]; 10545 u8 full_offload[0x1]; 10546 u8 reserved_at_41[0x1]; 10547 u8 esn_en[0x1]; 10548 u8 esn_overlap[0x1]; 10549 u8 reserved_at_44[0x2]; 10550 u8 icv_length[0x2]; 10551 u8 reserved_at_48[0x4]; 10552 u8 aso_return_reg[0x4]; 10553 u8 reserved_at_50[0x10]; 10554 10555 u8 esn_msb[0x20]; 10556 10557 u8 reserved_at_80[0x8]; 10558 u8 dekn[0x18]; 10559 10560 u8 salt[0x20]; 10561 10562 u8 implicit_iv[0x40]; 10563 10564 u8 reserved_at_100[0x700]; 10565 }; 10566 10567 struct mlx5_ifc_create_ipsec_obj_in_bits { 10568 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10569 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10570 }; 10571 10572 enum { 10573 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10574 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10575 }; 10576 10577 struct mlx5_ifc_query_ipsec_obj_out_bits { 10578 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10579 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10580 }; 10581 10582 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10583 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10584 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10585 }; 10586 10587 struct mlx5_ifc_encryption_key_obj_bits { 10588 u8 modify_field_select[0x40]; 10589 10590 u8 reserved_at_40[0x14]; 10591 u8 key_size[0x4]; 10592 u8 reserved_at_58[0x4]; 10593 u8 key_type[0x4]; 10594 10595 u8 reserved_at_60[0x8]; 10596 u8 pd[0x18]; 10597 10598 u8 reserved_at_80[0x180]; 10599 u8 key[8][0x20]; 10600 10601 u8 reserved_at_300[0x500]; 10602 }; 10603 10604 struct mlx5_ifc_create_encryption_key_in_bits { 10605 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10606 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10607 }; 10608 10609 enum { 10610 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10611 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10612 }; 10613 10614 enum { 10615 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10616 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10617 }; 10618 10619 struct mlx5_ifc_tls_static_params_bits { 10620 u8 const_2[0x2]; 10621 u8 tls_version[0x4]; 10622 u8 const_1[0x2]; 10623 u8 reserved_at_8[0x14]; 10624 u8 encryption_standard[0x4]; 10625 10626 u8 reserved_at_20[0x20]; 10627 10628 u8 initial_record_number[0x40]; 10629 10630 u8 resync_tcp_sn[0x20]; 10631 10632 u8 gcm_iv[0x20]; 10633 10634 u8 implicit_iv[0x40]; 10635 10636 u8 reserved_at_100[0x8]; 10637 u8 dek_index[0x18]; 10638 10639 u8 reserved_at_120[0xe0]; 10640 }; 10641 10642 struct mlx5_ifc_tls_progress_params_bits { 10643 u8 reserved_at_0[0x8]; 10644 u8 tisn[0x18]; 10645 10646 u8 next_record_tcp_sn[0x20]; 10647 10648 u8 hw_resync_tcp_sn[0x20]; 10649 10650 u8 record_tracker_state[0x2]; 10651 u8 auth_state[0x2]; 10652 u8 reserved_at_64[0x4]; 10653 u8 hw_offset_record_number[0x18]; 10654 }; 10655 10656 #endif /* MLX5_IFC_H */ 10657