1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 72 }; 73 74 enum { 75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 77 MLX5_CMD_OP_INIT_HCA = 0x102, 78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 79 MLX5_CMD_OP_ENABLE_HCA = 0x104, 80 MLX5_CMD_OP_DISABLE_HCA = 0x105, 81 MLX5_CMD_OP_QUERY_PAGES = 0x107, 82 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 83 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 85 MLX5_CMD_OP_SET_ISSI = 0x10b, 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 87 MLX5_CMD_OP_CREATE_MKEY = 0x200, 88 MLX5_CMD_OP_QUERY_MKEY = 0x201, 89 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 92 MLX5_CMD_OP_CREATE_EQ = 0x301, 93 MLX5_CMD_OP_DESTROY_EQ = 0x302, 94 MLX5_CMD_OP_QUERY_EQ = 0x303, 95 MLX5_CMD_OP_GEN_EQE = 0x304, 96 MLX5_CMD_OP_CREATE_CQ = 0x400, 97 MLX5_CMD_OP_DESTROY_CQ = 0x401, 98 MLX5_CMD_OP_QUERY_CQ = 0x402, 99 MLX5_CMD_OP_MODIFY_CQ = 0x403, 100 MLX5_CMD_OP_CREATE_QP = 0x500, 101 MLX5_CMD_OP_DESTROY_QP = 0x501, 102 MLX5_CMD_OP_RST2INIT_QP = 0x502, 103 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 104 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 105 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 107 MLX5_CMD_OP_2ERR_QP = 0x507, 108 MLX5_CMD_OP_2RST_QP = 0x50a, 109 MLX5_CMD_OP_QUERY_QP = 0x50b, 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 112 MLX5_CMD_OP_CREATE_PSV = 0x600, 113 MLX5_CMD_OP_DESTROY_PSV = 0x601, 114 MLX5_CMD_OP_CREATE_SRQ = 0x700, 115 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 116 MLX5_CMD_OP_QUERY_SRQ = 0x702, 117 MLX5_CMD_OP_ARM_RQ = 0x703, 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 122 MLX5_CMD_OP_CREATE_DCT = 0x710, 123 MLX5_CMD_OP_DESTROY_DCT = 0x711, 124 MLX5_CMD_OP_DRAIN_DCT = 0x712, 125 MLX5_CMD_OP_QUERY_DCT = 0x713, 126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 127 MLX5_CMD_OP_CREATE_XRQ = 0x717, 128 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 129 MLX5_CMD_OP_QUERY_XRQ = 0x719, 130 MLX5_CMD_OP_ARM_XRQ = 0x71a, 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 155 MLX5_CMD_OP_ALLOC_PD = 0x800, 156 MLX5_CMD_OP_DEALLOC_PD = 0x801, 157 MLX5_CMD_OP_ALLOC_UAR = 0x802, 158 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 160 MLX5_CMD_OP_ACCESS_REG = 0x805, 161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 164 MLX5_CMD_OP_MAD_IFC = 0x50d, 165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 167 MLX5_CMD_OP_NOP = 0x80d, 168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 184 MLX5_CMD_OP_CREATE_LAG = 0x840, 185 MLX5_CMD_OP_MODIFY_LAG = 0x841, 186 MLX5_CMD_OP_QUERY_LAG = 0x842, 187 MLX5_CMD_OP_DESTROY_LAG = 0x843, 188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 190 MLX5_CMD_OP_CREATE_TIR = 0x900, 191 MLX5_CMD_OP_MODIFY_TIR = 0x901, 192 MLX5_CMD_OP_DESTROY_TIR = 0x902, 193 MLX5_CMD_OP_QUERY_TIR = 0x903, 194 MLX5_CMD_OP_CREATE_SQ = 0x904, 195 MLX5_CMD_OP_MODIFY_SQ = 0x905, 196 MLX5_CMD_OP_DESTROY_SQ = 0x906, 197 MLX5_CMD_OP_QUERY_SQ = 0x907, 198 MLX5_CMD_OP_CREATE_RQ = 0x908, 199 MLX5_CMD_OP_MODIFY_RQ = 0x909, 200 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 201 MLX5_CMD_OP_QUERY_RQ = 0x90b, 202 MLX5_CMD_OP_CREATE_RMP = 0x90c, 203 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 204 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 205 MLX5_CMD_OP_QUERY_RMP = 0x90f, 206 MLX5_CMD_OP_CREATE_TIS = 0x912, 207 MLX5_CMD_OP_MODIFY_TIS = 0x913, 208 MLX5_CMD_OP_DESTROY_TIS = 0x914, 209 MLX5_CMD_OP_QUERY_TIS = 0x915, 210 MLX5_CMD_OP_CREATE_RQT = 0x916, 211 MLX5_CMD_OP_MODIFY_RQT = 0x917, 212 MLX5_CMD_OP_DESTROY_RQT = 0x918, 213 MLX5_CMD_OP_QUERY_RQT = 0x919, 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 230 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 231 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 232 MLX5_CMD_OP_MAX 233 }; 234 235 struct mlx5_ifc_flow_table_fields_supported_bits { 236 u8 outer_dmac[0x1]; 237 u8 outer_smac[0x1]; 238 u8 outer_ether_type[0x1]; 239 u8 reserved_at_3[0x1]; 240 u8 outer_first_prio[0x1]; 241 u8 outer_first_cfi[0x1]; 242 u8 outer_first_vid[0x1]; 243 u8 reserved_at_7[0x1]; 244 u8 outer_second_prio[0x1]; 245 u8 outer_second_cfi[0x1]; 246 u8 outer_second_vid[0x1]; 247 u8 reserved_at_b[0x1]; 248 u8 outer_sip[0x1]; 249 u8 outer_dip[0x1]; 250 u8 outer_frag[0x1]; 251 u8 outer_ip_protocol[0x1]; 252 u8 outer_ip_ecn[0x1]; 253 u8 outer_ip_dscp[0x1]; 254 u8 outer_udp_sport[0x1]; 255 u8 outer_udp_dport[0x1]; 256 u8 outer_tcp_sport[0x1]; 257 u8 outer_tcp_dport[0x1]; 258 u8 outer_tcp_flags[0x1]; 259 u8 outer_gre_protocol[0x1]; 260 u8 outer_gre_key[0x1]; 261 u8 outer_vxlan_vni[0x1]; 262 u8 reserved_at_1a[0x5]; 263 u8 source_eswitch_port[0x1]; 264 265 u8 inner_dmac[0x1]; 266 u8 inner_smac[0x1]; 267 u8 inner_ether_type[0x1]; 268 u8 reserved_at_23[0x1]; 269 u8 inner_first_prio[0x1]; 270 u8 inner_first_cfi[0x1]; 271 u8 inner_first_vid[0x1]; 272 u8 reserved_at_27[0x1]; 273 u8 inner_second_prio[0x1]; 274 u8 inner_second_cfi[0x1]; 275 u8 inner_second_vid[0x1]; 276 u8 reserved_at_2b[0x1]; 277 u8 inner_sip[0x1]; 278 u8 inner_dip[0x1]; 279 u8 inner_frag[0x1]; 280 u8 inner_ip_protocol[0x1]; 281 u8 inner_ip_ecn[0x1]; 282 u8 inner_ip_dscp[0x1]; 283 u8 inner_udp_sport[0x1]; 284 u8 inner_udp_dport[0x1]; 285 u8 inner_tcp_sport[0x1]; 286 u8 inner_tcp_dport[0x1]; 287 u8 inner_tcp_flags[0x1]; 288 u8 reserved_at_37[0x9]; 289 290 u8 reserved_at_40[0x40]; 291 }; 292 293 struct mlx5_ifc_flow_table_prop_layout_bits { 294 u8 ft_support[0x1]; 295 u8 reserved_at_1[0x1]; 296 u8 flow_counter[0x1]; 297 u8 flow_modify_en[0x1]; 298 u8 modify_root[0x1]; 299 u8 identified_miss_table_mode[0x1]; 300 u8 flow_table_modify[0x1]; 301 u8 encap[0x1]; 302 u8 decap[0x1]; 303 u8 reserved_at_9[0x17]; 304 305 u8 reserved_at_20[0x2]; 306 u8 log_max_ft_size[0x6]; 307 u8 log_max_modify_header_context[0x8]; 308 u8 max_modify_header_actions[0x8]; 309 u8 max_ft_level[0x8]; 310 311 u8 reserved_at_40[0x20]; 312 313 u8 reserved_at_60[0x18]; 314 u8 log_max_ft_num[0x8]; 315 316 u8 reserved_at_80[0x18]; 317 u8 log_max_destination[0x8]; 318 319 u8 reserved_at_a0[0x18]; 320 u8 log_max_flow[0x8]; 321 322 u8 reserved_at_c0[0x40]; 323 324 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 325 326 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 327 }; 328 329 struct mlx5_ifc_odp_per_transport_service_cap_bits { 330 u8 send[0x1]; 331 u8 receive[0x1]; 332 u8 write[0x1]; 333 u8 read[0x1]; 334 u8 atomic[0x1]; 335 u8 srq_receive[0x1]; 336 u8 reserved_at_6[0x1a]; 337 }; 338 339 struct mlx5_ifc_ipv4_layout_bits { 340 u8 reserved_at_0[0x60]; 341 342 u8 ipv4[0x20]; 343 }; 344 345 struct mlx5_ifc_ipv6_layout_bits { 346 u8 ipv6[16][0x8]; 347 }; 348 349 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 350 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 351 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 352 u8 reserved_at_0[0x80]; 353 }; 354 355 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 356 u8 smac_47_16[0x20]; 357 358 u8 smac_15_0[0x10]; 359 u8 ethertype[0x10]; 360 361 u8 dmac_47_16[0x20]; 362 363 u8 dmac_15_0[0x10]; 364 u8 first_prio[0x3]; 365 u8 first_cfi[0x1]; 366 u8 first_vid[0xc]; 367 368 u8 ip_protocol[0x8]; 369 u8 ip_dscp[0x6]; 370 u8 ip_ecn[0x2]; 371 u8 cvlan_tag[0x1]; 372 u8 svlan_tag[0x1]; 373 u8 frag[0x1]; 374 u8 reserved_at_93[0x4]; 375 u8 tcp_flags[0x9]; 376 377 u8 tcp_sport[0x10]; 378 u8 tcp_dport[0x10]; 379 380 u8 reserved_at_c0[0x20]; 381 382 u8 udp_sport[0x10]; 383 u8 udp_dport[0x10]; 384 385 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 386 387 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 388 }; 389 390 struct mlx5_ifc_fte_match_set_misc_bits { 391 u8 reserved_at_0[0x8]; 392 u8 source_sqn[0x18]; 393 394 u8 reserved_at_20[0x10]; 395 u8 source_port[0x10]; 396 397 u8 outer_second_prio[0x3]; 398 u8 outer_second_cfi[0x1]; 399 u8 outer_second_vid[0xc]; 400 u8 inner_second_prio[0x3]; 401 u8 inner_second_cfi[0x1]; 402 u8 inner_second_vid[0xc]; 403 404 u8 outer_second_cvlan_tag[0x1]; 405 u8 inner_second_cvlan_tag[0x1]; 406 u8 outer_second_svlan_tag[0x1]; 407 u8 inner_second_svlan_tag[0x1]; 408 u8 reserved_at_64[0xc]; 409 u8 gre_protocol[0x10]; 410 411 u8 gre_key_h[0x18]; 412 u8 gre_key_l[0x8]; 413 414 u8 vxlan_vni[0x18]; 415 u8 reserved_at_b8[0x8]; 416 417 u8 reserved_at_c0[0x20]; 418 419 u8 reserved_at_e0[0xc]; 420 u8 outer_ipv6_flow_label[0x14]; 421 422 u8 reserved_at_100[0xc]; 423 u8 inner_ipv6_flow_label[0x14]; 424 425 u8 reserved_at_120[0xe0]; 426 }; 427 428 struct mlx5_ifc_cmd_pas_bits { 429 u8 pa_h[0x20]; 430 431 u8 pa_l[0x14]; 432 u8 reserved_at_34[0xc]; 433 }; 434 435 struct mlx5_ifc_uint64_bits { 436 u8 hi[0x20]; 437 438 u8 lo[0x20]; 439 }; 440 441 enum { 442 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 443 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 444 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 445 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 446 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 447 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 448 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 449 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 450 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 451 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 452 }; 453 454 struct mlx5_ifc_ads_bits { 455 u8 fl[0x1]; 456 u8 free_ar[0x1]; 457 u8 reserved_at_2[0xe]; 458 u8 pkey_index[0x10]; 459 460 u8 reserved_at_20[0x8]; 461 u8 grh[0x1]; 462 u8 mlid[0x7]; 463 u8 rlid[0x10]; 464 465 u8 ack_timeout[0x5]; 466 u8 reserved_at_45[0x3]; 467 u8 src_addr_index[0x8]; 468 u8 reserved_at_50[0x4]; 469 u8 stat_rate[0x4]; 470 u8 hop_limit[0x8]; 471 472 u8 reserved_at_60[0x4]; 473 u8 tclass[0x8]; 474 u8 flow_label[0x14]; 475 476 u8 rgid_rip[16][0x8]; 477 478 u8 reserved_at_100[0x4]; 479 u8 f_dscp[0x1]; 480 u8 f_ecn[0x1]; 481 u8 reserved_at_106[0x1]; 482 u8 f_eth_prio[0x1]; 483 u8 ecn[0x2]; 484 u8 dscp[0x6]; 485 u8 udp_sport[0x10]; 486 487 u8 dei_cfi[0x1]; 488 u8 eth_prio[0x3]; 489 u8 sl[0x4]; 490 u8 port[0x8]; 491 u8 rmac_47_32[0x10]; 492 493 u8 rmac_31_0[0x20]; 494 }; 495 496 struct mlx5_ifc_flow_table_nic_cap_bits { 497 u8 nic_rx_multi_path_tirs[0x1]; 498 u8 nic_rx_multi_path_tirs_fts[0x1]; 499 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 500 u8 reserved_at_3[0x1fd]; 501 502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 503 504 u8 reserved_at_400[0x200]; 505 506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 507 508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 509 510 u8 reserved_at_a00[0x200]; 511 512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 513 514 u8 reserved_at_e00[0x7200]; 515 }; 516 517 struct mlx5_ifc_flow_table_eswitch_cap_bits { 518 u8 reserved_at_0[0x200]; 519 520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 521 522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 523 524 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 525 526 u8 reserved_at_800[0x7800]; 527 }; 528 529 struct mlx5_ifc_e_switch_cap_bits { 530 u8 vport_svlan_strip[0x1]; 531 u8 vport_cvlan_strip[0x1]; 532 u8 vport_svlan_insert[0x1]; 533 u8 vport_cvlan_insert_if_not_exist[0x1]; 534 u8 vport_cvlan_insert_overwrite[0x1]; 535 u8 reserved_at_5[0x19]; 536 u8 nic_vport_node_guid_modify[0x1]; 537 u8 nic_vport_port_guid_modify[0x1]; 538 539 u8 vxlan_encap_decap[0x1]; 540 u8 nvgre_encap_decap[0x1]; 541 u8 reserved_at_22[0x9]; 542 u8 log_max_encap_headers[0x5]; 543 u8 reserved_2b[0x6]; 544 u8 max_encap_header_size[0xa]; 545 546 u8 reserved_40[0x7c0]; 547 548 }; 549 550 struct mlx5_ifc_qos_cap_bits { 551 u8 packet_pacing[0x1]; 552 u8 esw_scheduling[0x1]; 553 u8 esw_bw_share[0x1]; 554 u8 esw_rate_limit[0x1]; 555 u8 reserved_at_4[0x1c]; 556 557 u8 reserved_at_20[0x20]; 558 559 u8 packet_pacing_max_rate[0x20]; 560 561 u8 packet_pacing_min_rate[0x20]; 562 563 u8 reserved_at_80[0x10]; 564 u8 packet_pacing_rate_table_size[0x10]; 565 566 u8 esw_element_type[0x10]; 567 u8 esw_tsar_type[0x10]; 568 569 u8 reserved_at_c0[0x10]; 570 u8 max_qos_para_vport[0x10]; 571 572 u8 max_tsar_bw_share[0x20]; 573 574 u8 reserved_at_100[0x700]; 575 }; 576 577 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 578 u8 csum_cap[0x1]; 579 u8 vlan_cap[0x1]; 580 u8 lro_cap[0x1]; 581 u8 lro_psh_flag[0x1]; 582 u8 lro_time_stamp[0x1]; 583 u8 reserved_at_5[0x2]; 584 u8 wqe_vlan_insert[0x1]; 585 u8 self_lb_en_modifiable[0x1]; 586 u8 reserved_at_9[0x2]; 587 u8 max_lso_cap[0x5]; 588 u8 multi_pkt_send_wqe[0x2]; 589 u8 wqe_inline_mode[0x2]; 590 u8 rss_ind_tbl_cap[0x4]; 591 u8 reg_umr_sq[0x1]; 592 u8 scatter_fcs[0x1]; 593 u8 reserved_at_1a[0x1]; 594 u8 tunnel_lso_const_out_ip_id[0x1]; 595 u8 reserved_at_1c[0x2]; 596 u8 tunnel_statless_gre[0x1]; 597 u8 tunnel_stateless_vxlan[0x1]; 598 599 u8 reserved_at_20[0x20]; 600 601 u8 reserved_at_40[0x10]; 602 u8 lro_min_mss_size[0x10]; 603 604 u8 reserved_at_60[0x120]; 605 606 u8 lro_timer_supported_periods[4][0x20]; 607 608 u8 reserved_at_200[0x600]; 609 }; 610 611 struct mlx5_ifc_roce_cap_bits { 612 u8 roce_apm[0x1]; 613 u8 reserved_at_1[0x1f]; 614 615 u8 reserved_at_20[0x60]; 616 617 u8 reserved_at_80[0xc]; 618 u8 l3_type[0x4]; 619 u8 reserved_at_90[0x8]; 620 u8 roce_version[0x8]; 621 622 u8 reserved_at_a0[0x10]; 623 u8 r_roce_dest_udp_port[0x10]; 624 625 u8 r_roce_max_src_udp_port[0x10]; 626 u8 r_roce_min_src_udp_port[0x10]; 627 628 u8 reserved_at_e0[0x10]; 629 u8 roce_address_table_size[0x10]; 630 631 u8 reserved_at_100[0x700]; 632 }; 633 634 enum { 635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 644 }; 645 646 enum { 647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 656 }; 657 658 struct mlx5_ifc_atomic_caps_bits { 659 u8 reserved_at_0[0x40]; 660 661 u8 atomic_req_8B_endianess_mode[0x2]; 662 u8 reserved_at_42[0x4]; 663 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 664 665 u8 reserved_at_47[0x19]; 666 667 u8 reserved_at_60[0x20]; 668 669 u8 reserved_at_80[0x10]; 670 u8 atomic_operations[0x10]; 671 672 u8 reserved_at_a0[0x10]; 673 u8 atomic_size_qp[0x10]; 674 675 u8 reserved_at_c0[0x10]; 676 u8 atomic_size_dc[0x10]; 677 678 u8 reserved_at_e0[0x720]; 679 }; 680 681 struct mlx5_ifc_odp_cap_bits { 682 u8 reserved_at_0[0x40]; 683 684 u8 sig[0x1]; 685 u8 reserved_at_41[0x1f]; 686 687 u8 reserved_at_60[0x20]; 688 689 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 690 691 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 692 693 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 694 695 u8 reserved_at_e0[0x720]; 696 }; 697 698 struct mlx5_ifc_calc_op { 699 u8 reserved_at_0[0x10]; 700 u8 reserved_at_10[0x9]; 701 u8 op_swap_endianness[0x1]; 702 u8 op_min[0x1]; 703 u8 op_xor[0x1]; 704 u8 op_or[0x1]; 705 u8 op_and[0x1]; 706 u8 op_max[0x1]; 707 u8 op_add[0x1]; 708 }; 709 710 struct mlx5_ifc_vector_calc_cap_bits { 711 u8 calc_matrix[0x1]; 712 u8 reserved_at_1[0x1f]; 713 u8 reserved_at_20[0x8]; 714 u8 max_vec_count[0x8]; 715 u8 reserved_at_30[0xd]; 716 u8 max_chunk_size[0x3]; 717 struct mlx5_ifc_calc_op calc0; 718 struct mlx5_ifc_calc_op calc1; 719 struct mlx5_ifc_calc_op calc2; 720 struct mlx5_ifc_calc_op calc3; 721 722 u8 reserved_at_e0[0x720]; 723 }; 724 725 enum { 726 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 727 MLX5_WQ_TYPE_CYCLIC = 0x1, 728 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 729 }; 730 731 enum { 732 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 733 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 734 }; 735 736 enum { 737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 738 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 739 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 740 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 742 }; 743 744 enum { 745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 747 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 748 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 751 }; 752 753 enum { 754 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 755 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 756 }; 757 758 enum { 759 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 760 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 761 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 762 }; 763 764 enum { 765 MLX5_CAP_PORT_TYPE_IB = 0x0, 766 MLX5_CAP_PORT_TYPE_ETH = 0x1, 767 }; 768 769 struct mlx5_ifc_cmd_hca_cap_bits { 770 u8 reserved_at_0[0x80]; 771 772 u8 log_max_srq_sz[0x8]; 773 u8 log_max_qp_sz[0x8]; 774 u8 reserved_at_90[0xb]; 775 u8 log_max_qp[0x5]; 776 777 u8 reserved_at_a0[0xb]; 778 u8 log_max_srq[0x5]; 779 u8 reserved_at_b0[0x10]; 780 781 u8 reserved_at_c0[0x8]; 782 u8 log_max_cq_sz[0x8]; 783 u8 reserved_at_d0[0xb]; 784 u8 log_max_cq[0x5]; 785 786 u8 log_max_eq_sz[0x8]; 787 u8 reserved_at_e8[0x2]; 788 u8 log_max_mkey[0x6]; 789 u8 reserved_at_f0[0xc]; 790 u8 log_max_eq[0x4]; 791 792 u8 max_indirection[0x8]; 793 u8 fixed_buffer_size[0x1]; 794 u8 log_max_mrw_sz[0x7]; 795 u8 reserved_at_110[0x2]; 796 u8 log_max_bsf_list_size[0x6]; 797 u8 umr_extended_translation_offset[0x1]; 798 u8 null_mkey[0x1]; 799 u8 log_max_klm_list_size[0x6]; 800 801 u8 reserved_at_120[0xa]; 802 u8 log_max_ra_req_dc[0x6]; 803 u8 reserved_at_130[0xa]; 804 u8 log_max_ra_res_dc[0x6]; 805 806 u8 reserved_at_140[0xa]; 807 u8 log_max_ra_req_qp[0x6]; 808 u8 reserved_at_150[0xa]; 809 u8 log_max_ra_res_qp[0x6]; 810 811 u8 end_pad[0x1]; 812 u8 cc_query_allowed[0x1]; 813 u8 cc_modify_allowed[0x1]; 814 u8 start_pad[0x1]; 815 u8 cache_line_128byte[0x1]; 816 u8 reserved_at_163[0xb]; 817 u8 gid_table_size[0x10]; 818 819 u8 out_of_seq_cnt[0x1]; 820 u8 vport_counters[0x1]; 821 u8 retransmission_q_counters[0x1]; 822 u8 reserved_at_183[0x1]; 823 u8 modify_rq_counter_set_id[0x1]; 824 u8 reserved_at_185[0x1]; 825 u8 max_qp_cnt[0xa]; 826 u8 pkey_table_size[0x10]; 827 828 u8 vport_group_manager[0x1]; 829 u8 vhca_group_manager[0x1]; 830 u8 ib_virt[0x1]; 831 u8 eth_virt[0x1]; 832 u8 reserved_at_1a4[0x1]; 833 u8 ets[0x1]; 834 u8 nic_flow_table[0x1]; 835 u8 eswitch_flow_table[0x1]; 836 u8 early_vf_enable[0x1]; 837 u8 mcam_reg[0x1]; 838 u8 pcam_reg[0x1]; 839 u8 local_ca_ack_delay[0x5]; 840 u8 port_module_event[0x1]; 841 u8 reserved_at_1b1[0x1]; 842 u8 ports_check[0x1]; 843 u8 reserved_at_1b3[0x1]; 844 u8 disable_link_up[0x1]; 845 u8 beacon_led[0x1]; 846 u8 port_type[0x2]; 847 u8 num_ports[0x8]; 848 849 u8 reserved_at_1c0[0x1]; 850 u8 pps[0x1]; 851 u8 pps_modify[0x1]; 852 u8 log_max_msg[0x5]; 853 u8 reserved_at_1c8[0x4]; 854 u8 max_tc[0x4]; 855 u8 reserved_at_1d0[0x1]; 856 u8 dcbx[0x1]; 857 u8 reserved_at_1d2[0x4]; 858 u8 rol_s[0x1]; 859 u8 rol_g[0x1]; 860 u8 reserved_at_1d8[0x1]; 861 u8 wol_s[0x1]; 862 u8 wol_g[0x1]; 863 u8 wol_a[0x1]; 864 u8 wol_b[0x1]; 865 u8 wol_m[0x1]; 866 u8 wol_u[0x1]; 867 u8 wol_p[0x1]; 868 869 u8 stat_rate_support[0x10]; 870 u8 reserved_at_1f0[0xc]; 871 u8 cqe_version[0x4]; 872 873 u8 compact_address_vector[0x1]; 874 u8 striding_rq[0x1]; 875 u8 reserved_at_202[0x2]; 876 u8 ipoib_basic_offloads[0x1]; 877 u8 reserved_at_205[0xa]; 878 u8 drain_sigerr[0x1]; 879 u8 cmdif_checksum[0x2]; 880 u8 sigerr_cqe[0x1]; 881 u8 reserved_at_213[0x1]; 882 u8 wq_signature[0x1]; 883 u8 sctr_data_cqe[0x1]; 884 u8 reserved_at_216[0x1]; 885 u8 sho[0x1]; 886 u8 tph[0x1]; 887 u8 rf[0x1]; 888 u8 dct[0x1]; 889 u8 qos[0x1]; 890 u8 eth_net_offloads[0x1]; 891 u8 roce[0x1]; 892 u8 atomic[0x1]; 893 u8 reserved_at_21f[0x1]; 894 895 u8 cq_oi[0x1]; 896 u8 cq_resize[0x1]; 897 u8 cq_moderation[0x1]; 898 u8 reserved_at_223[0x3]; 899 u8 cq_eq_remap[0x1]; 900 u8 pg[0x1]; 901 u8 block_lb_mc[0x1]; 902 u8 reserved_at_229[0x1]; 903 u8 scqe_break_moderation[0x1]; 904 u8 cq_period_start_from_cqe[0x1]; 905 u8 cd[0x1]; 906 u8 reserved_at_22d[0x1]; 907 u8 apm[0x1]; 908 u8 vector_calc[0x1]; 909 u8 umr_ptr_rlky[0x1]; 910 u8 imaicl[0x1]; 911 u8 reserved_at_232[0x4]; 912 u8 qkv[0x1]; 913 u8 pkv[0x1]; 914 u8 set_deth_sqpn[0x1]; 915 u8 reserved_at_239[0x3]; 916 u8 xrc[0x1]; 917 u8 ud[0x1]; 918 u8 uc[0x1]; 919 u8 rc[0x1]; 920 921 u8 uar_4k[0x1]; 922 u8 reserved_at_241[0x9]; 923 u8 uar_sz[0x6]; 924 u8 reserved_at_250[0x8]; 925 u8 log_pg_sz[0x8]; 926 927 u8 bf[0x1]; 928 u8 driver_version[0x1]; 929 u8 pad_tx_eth_packet[0x1]; 930 u8 reserved_at_263[0x8]; 931 u8 log_bf_reg_size[0x5]; 932 933 u8 reserved_at_270[0xb]; 934 u8 lag_master[0x1]; 935 u8 num_lag_ports[0x4]; 936 937 u8 reserved_at_280[0x10]; 938 u8 max_wqe_sz_sq[0x10]; 939 940 u8 reserved_at_2a0[0x10]; 941 u8 max_wqe_sz_rq[0x10]; 942 943 u8 reserved_at_2c0[0x10]; 944 u8 max_wqe_sz_sq_dc[0x10]; 945 946 u8 reserved_at_2e0[0x7]; 947 u8 max_qp_mcg[0x19]; 948 949 u8 reserved_at_300[0x18]; 950 u8 log_max_mcg[0x8]; 951 952 u8 reserved_at_320[0x3]; 953 u8 log_max_transport_domain[0x5]; 954 u8 reserved_at_328[0x3]; 955 u8 log_max_pd[0x5]; 956 u8 reserved_at_330[0xb]; 957 u8 log_max_xrcd[0x5]; 958 959 u8 reserved_at_340[0x8]; 960 u8 log_max_flow_counter_bulk[0x8]; 961 u8 max_flow_counter[0x10]; 962 963 964 u8 reserved_at_360[0x3]; 965 u8 log_max_rq[0x5]; 966 u8 reserved_at_368[0x3]; 967 u8 log_max_sq[0x5]; 968 u8 reserved_at_370[0x3]; 969 u8 log_max_tir[0x5]; 970 u8 reserved_at_378[0x3]; 971 u8 log_max_tis[0x5]; 972 973 u8 basic_cyclic_rcv_wqe[0x1]; 974 u8 reserved_at_381[0x2]; 975 u8 log_max_rmp[0x5]; 976 u8 reserved_at_388[0x3]; 977 u8 log_max_rqt[0x5]; 978 u8 reserved_at_390[0x3]; 979 u8 log_max_rqt_size[0x5]; 980 u8 reserved_at_398[0x3]; 981 u8 log_max_tis_per_sq[0x5]; 982 983 u8 reserved_at_3a0[0x3]; 984 u8 log_max_stride_sz_rq[0x5]; 985 u8 reserved_at_3a8[0x3]; 986 u8 log_min_stride_sz_rq[0x5]; 987 u8 reserved_at_3b0[0x3]; 988 u8 log_max_stride_sz_sq[0x5]; 989 u8 reserved_at_3b8[0x3]; 990 u8 log_min_stride_sz_sq[0x5]; 991 992 u8 reserved_at_3c0[0x1b]; 993 u8 log_max_wq_sz[0x5]; 994 995 u8 nic_vport_change_event[0x1]; 996 u8 reserved_at_3e1[0xa]; 997 u8 log_max_vlan_list[0x5]; 998 u8 reserved_at_3f0[0x3]; 999 u8 log_max_current_mc_list[0x5]; 1000 u8 reserved_at_3f8[0x3]; 1001 u8 log_max_current_uc_list[0x5]; 1002 1003 u8 reserved_at_400[0x80]; 1004 1005 u8 reserved_at_480[0x3]; 1006 u8 log_max_l2_table[0x5]; 1007 u8 reserved_at_488[0x8]; 1008 u8 log_uar_page_sz[0x10]; 1009 1010 u8 reserved_at_4a0[0x20]; 1011 u8 device_frequency_mhz[0x20]; 1012 u8 device_frequency_khz[0x20]; 1013 1014 u8 reserved_at_500[0x20]; 1015 u8 num_of_uars_per_page[0x20]; 1016 u8 reserved_at_540[0x40]; 1017 1018 u8 reserved_at_580[0x3f]; 1019 u8 cqe_compression[0x1]; 1020 1021 u8 cqe_compression_timeout[0x10]; 1022 u8 cqe_compression_max_num[0x10]; 1023 1024 u8 reserved_at_5e0[0x10]; 1025 u8 tag_matching[0x1]; 1026 u8 rndv_offload_rc[0x1]; 1027 u8 rndv_offload_dc[0x1]; 1028 u8 log_tag_matching_list_sz[0x5]; 1029 u8 reserved_at_5f8[0x3]; 1030 u8 log_max_xrq[0x5]; 1031 1032 u8 reserved_at_600[0x200]; 1033 }; 1034 1035 enum mlx5_flow_destination_type { 1036 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1037 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1038 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1039 1040 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1041 }; 1042 1043 struct mlx5_ifc_dest_format_struct_bits { 1044 u8 destination_type[0x8]; 1045 u8 destination_id[0x18]; 1046 1047 u8 reserved_at_20[0x20]; 1048 }; 1049 1050 struct mlx5_ifc_flow_counter_list_bits { 1051 u8 clear[0x1]; 1052 u8 num_of_counters[0xf]; 1053 u8 flow_counter_id[0x10]; 1054 1055 u8 reserved_at_20[0x20]; 1056 }; 1057 1058 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1059 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1060 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1061 u8 reserved_at_0[0x40]; 1062 }; 1063 1064 struct mlx5_ifc_fte_match_param_bits { 1065 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1066 1067 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1068 1069 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1070 1071 u8 reserved_at_600[0xa00]; 1072 }; 1073 1074 enum { 1075 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1076 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1077 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1078 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1079 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1080 }; 1081 1082 struct mlx5_ifc_rx_hash_field_select_bits { 1083 u8 l3_prot_type[0x1]; 1084 u8 l4_prot_type[0x1]; 1085 u8 selected_fields[0x1e]; 1086 }; 1087 1088 enum { 1089 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1090 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1091 }; 1092 1093 enum { 1094 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1095 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1096 }; 1097 1098 struct mlx5_ifc_wq_bits { 1099 u8 wq_type[0x4]; 1100 u8 wq_signature[0x1]; 1101 u8 end_padding_mode[0x2]; 1102 u8 cd_slave[0x1]; 1103 u8 reserved_at_8[0x18]; 1104 1105 u8 hds_skip_first_sge[0x1]; 1106 u8 log2_hds_buf_size[0x3]; 1107 u8 reserved_at_24[0x7]; 1108 u8 page_offset[0x5]; 1109 u8 lwm[0x10]; 1110 1111 u8 reserved_at_40[0x8]; 1112 u8 pd[0x18]; 1113 1114 u8 reserved_at_60[0x8]; 1115 u8 uar_page[0x18]; 1116 1117 u8 dbr_addr[0x40]; 1118 1119 u8 hw_counter[0x20]; 1120 1121 u8 sw_counter[0x20]; 1122 1123 u8 reserved_at_100[0xc]; 1124 u8 log_wq_stride[0x4]; 1125 u8 reserved_at_110[0x3]; 1126 u8 log_wq_pg_sz[0x5]; 1127 u8 reserved_at_118[0x3]; 1128 u8 log_wq_sz[0x5]; 1129 1130 u8 reserved_at_120[0x15]; 1131 u8 log_wqe_num_of_strides[0x3]; 1132 u8 two_byte_shift_en[0x1]; 1133 u8 reserved_at_139[0x4]; 1134 u8 log_wqe_stride_size[0x3]; 1135 1136 u8 reserved_at_140[0x4c0]; 1137 1138 struct mlx5_ifc_cmd_pas_bits pas[0]; 1139 }; 1140 1141 struct mlx5_ifc_rq_num_bits { 1142 u8 reserved_at_0[0x8]; 1143 u8 rq_num[0x18]; 1144 }; 1145 1146 struct mlx5_ifc_mac_address_layout_bits { 1147 u8 reserved_at_0[0x10]; 1148 u8 mac_addr_47_32[0x10]; 1149 1150 u8 mac_addr_31_0[0x20]; 1151 }; 1152 1153 struct mlx5_ifc_vlan_layout_bits { 1154 u8 reserved_at_0[0x14]; 1155 u8 vlan[0x0c]; 1156 1157 u8 reserved_at_20[0x20]; 1158 }; 1159 1160 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1161 u8 reserved_at_0[0xa0]; 1162 1163 u8 min_time_between_cnps[0x20]; 1164 1165 u8 reserved_at_c0[0x12]; 1166 u8 cnp_dscp[0x6]; 1167 u8 reserved_at_d8[0x5]; 1168 u8 cnp_802p_prio[0x3]; 1169 1170 u8 reserved_at_e0[0x720]; 1171 }; 1172 1173 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1174 u8 reserved_at_0[0x60]; 1175 1176 u8 reserved_at_60[0x4]; 1177 u8 clamp_tgt_rate[0x1]; 1178 u8 reserved_at_65[0x3]; 1179 u8 clamp_tgt_rate_after_time_inc[0x1]; 1180 u8 reserved_at_69[0x17]; 1181 1182 u8 reserved_at_80[0x20]; 1183 1184 u8 rpg_time_reset[0x20]; 1185 1186 u8 rpg_byte_reset[0x20]; 1187 1188 u8 rpg_threshold[0x20]; 1189 1190 u8 rpg_max_rate[0x20]; 1191 1192 u8 rpg_ai_rate[0x20]; 1193 1194 u8 rpg_hai_rate[0x20]; 1195 1196 u8 rpg_gd[0x20]; 1197 1198 u8 rpg_min_dec_fac[0x20]; 1199 1200 u8 rpg_min_rate[0x20]; 1201 1202 u8 reserved_at_1c0[0xe0]; 1203 1204 u8 rate_to_set_on_first_cnp[0x20]; 1205 1206 u8 dce_tcp_g[0x20]; 1207 1208 u8 dce_tcp_rtt[0x20]; 1209 1210 u8 rate_reduce_monitor_period[0x20]; 1211 1212 u8 reserved_at_320[0x20]; 1213 1214 u8 initial_alpha_value[0x20]; 1215 1216 u8 reserved_at_360[0x4a0]; 1217 }; 1218 1219 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1220 u8 reserved_at_0[0x80]; 1221 1222 u8 rppp_max_rps[0x20]; 1223 1224 u8 rpg_time_reset[0x20]; 1225 1226 u8 rpg_byte_reset[0x20]; 1227 1228 u8 rpg_threshold[0x20]; 1229 1230 u8 rpg_max_rate[0x20]; 1231 1232 u8 rpg_ai_rate[0x20]; 1233 1234 u8 rpg_hai_rate[0x20]; 1235 1236 u8 rpg_gd[0x20]; 1237 1238 u8 rpg_min_dec_fac[0x20]; 1239 1240 u8 rpg_min_rate[0x20]; 1241 1242 u8 reserved_at_1c0[0x640]; 1243 }; 1244 1245 enum { 1246 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1247 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1248 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1249 }; 1250 1251 struct mlx5_ifc_resize_field_select_bits { 1252 u8 resize_field_select[0x20]; 1253 }; 1254 1255 enum { 1256 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1257 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1258 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1259 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1260 }; 1261 1262 struct mlx5_ifc_modify_field_select_bits { 1263 u8 modify_field_select[0x20]; 1264 }; 1265 1266 struct mlx5_ifc_field_select_r_roce_np_bits { 1267 u8 field_select_r_roce_np[0x20]; 1268 }; 1269 1270 struct mlx5_ifc_field_select_r_roce_rp_bits { 1271 u8 field_select_r_roce_rp[0x20]; 1272 }; 1273 1274 enum { 1275 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1277 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1278 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1279 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1280 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1281 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1282 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1283 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1284 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1285 }; 1286 1287 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1288 u8 field_select_8021qaurp[0x20]; 1289 }; 1290 1291 struct mlx5_ifc_phys_layer_cntrs_bits { 1292 u8 time_since_last_clear_high[0x20]; 1293 1294 u8 time_since_last_clear_low[0x20]; 1295 1296 u8 symbol_errors_high[0x20]; 1297 1298 u8 symbol_errors_low[0x20]; 1299 1300 u8 sync_headers_errors_high[0x20]; 1301 1302 u8 sync_headers_errors_low[0x20]; 1303 1304 u8 edpl_bip_errors_lane0_high[0x20]; 1305 1306 u8 edpl_bip_errors_lane0_low[0x20]; 1307 1308 u8 edpl_bip_errors_lane1_high[0x20]; 1309 1310 u8 edpl_bip_errors_lane1_low[0x20]; 1311 1312 u8 edpl_bip_errors_lane2_high[0x20]; 1313 1314 u8 edpl_bip_errors_lane2_low[0x20]; 1315 1316 u8 edpl_bip_errors_lane3_high[0x20]; 1317 1318 u8 edpl_bip_errors_lane3_low[0x20]; 1319 1320 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1321 1322 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1323 1324 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1325 1326 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1327 1328 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1329 1330 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1331 1332 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1333 1334 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1335 1336 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1337 1338 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1339 1340 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1341 1342 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1343 1344 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1345 1346 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1347 1348 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1349 1350 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1351 1352 u8 rs_fec_corrected_blocks_high[0x20]; 1353 1354 u8 rs_fec_corrected_blocks_low[0x20]; 1355 1356 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1357 1358 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1359 1360 u8 rs_fec_no_errors_blocks_high[0x20]; 1361 1362 u8 rs_fec_no_errors_blocks_low[0x20]; 1363 1364 u8 rs_fec_single_error_blocks_high[0x20]; 1365 1366 u8 rs_fec_single_error_blocks_low[0x20]; 1367 1368 u8 rs_fec_corrected_symbols_total_high[0x20]; 1369 1370 u8 rs_fec_corrected_symbols_total_low[0x20]; 1371 1372 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1373 1374 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1375 1376 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1377 1378 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1379 1380 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1381 1382 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1383 1384 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1385 1386 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1387 1388 u8 link_down_events[0x20]; 1389 1390 u8 successful_recovery_events[0x20]; 1391 1392 u8 reserved_at_640[0x180]; 1393 }; 1394 1395 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1396 u8 time_since_last_clear_high[0x20]; 1397 1398 u8 time_since_last_clear_low[0x20]; 1399 1400 u8 phy_received_bits_high[0x20]; 1401 1402 u8 phy_received_bits_low[0x20]; 1403 1404 u8 phy_symbol_errors_high[0x20]; 1405 1406 u8 phy_symbol_errors_low[0x20]; 1407 1408 u8 phy_corrected_bits_high[0x20]; 1409 1410 u8 phy_corrected_bits_low[0x20]; 1411 1412 u8 phy_corrected_bits_lane0_high[0x20]; 1413 1414 u8 phy_corrected_bits_lane0_low[0x20]; 1415 1416 u8 phy_corrected_bits_lane1_high[0x20]; 1417 1418 u8 phy_corrected_bits_lane1_low[0x20]; 1419 1420 u8 phy_corrected_bits_lane2_high[0x20]; 1421 1422 u8 phy_corrected_bits_lane2_low[0x20]; 1423 1424 u8 phy_corrected_bits_lane3_high[0x20]; 1425 1426 u8 phy_corrected_bits_lane3_low[0x20]; 1427 1428 u8 reserved_at_200[0x5c0]; 1429 }; 1430 1431 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1432 u8 symbol_error_counter[0x10]; 1433 1434 u8 link_error_recovery_counter[0x8]; 1435 1436 u8 link_downed_counter[0x8]; 1437 1438 u8 port_rcv_errors[0x10]; 1439 1440 u8 port_rcv_remote_physical_errors[0x10]; 1441 1442 u8 port_rcv_switch_relay_errors[0x10]; 1443 1444 u8 port_xmit_discards[0x10]; 1445 1446 u8 port_xmit_constraint_errors[0x8]; 1447 1448 u8 port_rcv_constraint_errors[0x8]; 1449 1450 u8 reserved_at_70[0x8]; 1451 1452 u8 link_overrun_errors[0x8]; 1453 1454 u8 reserved_at_80[0x10]; 1455 1456 u8 vl_15_dropped[0x10]; 1457 1458 u8 reserved_at_a0[0xa0]; 1459 }; 1460 1461 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1462 u8 transmit_queue_high[0x20]; 1463 1464 u8 transmit_queue_low[0x20]; 1465 1466 u8 reserved_at_40[0x780]; 1467 }; 1468 1469 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1470 u8 rx_octets_high[0x20]; 1471 1472 u8 rx_octets_low[0x20]; 1473 1474 u8 reserved_at_40[0xc0]; 1475 1476 u8 rx_frames_high[0x20]; 1477 1478 u8 rx_frames_low[0x20]; 1479 1480 u8 tx_octets_high[0x20]; 1481 1482 u8 tx_octets_low[0x20]; 1483 1484 u8 reserved_at_180[0xc0]; 1485 1486 u8 tx_frames_high[0x20]; 1487 1488 u8 tx_frames_low[0x20]; 1489 1490 u8 rx_pause_high[0x20]; 1491 1492 u8 rx_pause_low[0x20]; 1493 1494 u8 rx_pause_duration_high[0x20]; 1495 1496 u8 rx_pause_duration_low[0x20]; 1497 1498 u8 tx_pause_high[0x20]; 1499 1500 u8 tx_pause_low[0x20]; 1501 1502 u8 tx_pause_duration_high[0x20]; 1503 1504 u8 tx_pause_duration_low[0x20]; 1505 1506 u8 rx_pause_transition_high[0x20]; 1507 1508 u8 rx_pause_transition_low[0x20]; 1509 1510 u8 reserved_at_3c0[0x400]; 1511 }; 1512 1513 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1514 u8 port_transmit_wait_high[0x20]; 1515 1516 u8 port_transmit_wait_low[0x20]; 1517 1518 u8 reserved_at_40[0x780]; 1519 }; 1520 1521 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1522 u8 dot3stats_alignment_errors_high[0x20]; 1523 1524 u8 dot3stats_alignment_errors_low[0x20]; 1525 1526 u8 dot3stats_fcs_errors_high[0x20]; 1527 1528 u8 dot3stats_fcs_errors_low[0x20]; 1529 1530 u8 dot3stats_single_collision_frames_high[0x20]; 1531 1532 u8 dot3stats_single_collision_frames_low[0x20]; 1533 1534 u8 dot3stats_multiple_collision_frames_high[0x20]; 1535 1536 u8 dot3stats_multiple_collision_frames_low[0x20]; 1537 1538 u8 dot3stats_sqe_test_errors_high[0x20]; 1539 1540 u8 dot3stats_sqe_test_errors_low[0x20]; 1541 1542 u8 dot3stats_deferred_transmissions_high[0x20]; 1543 1544 u8 dot3stats_deferred_transmissions_low[0x20]; 1545 1546 u8 dot3stats_late_collisions_high[0x20]; 1547 1548 u8 dot3stats_late_collisions_low[0x20]; 1549 1550 u8 dot3stats_excessive_collisions_high[0x20]; 1551 1552 u8 dot3stats_excessive_collisions_low[0x20]; 1553 1554 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1555 1556 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1557 1558 u8 dot3stats_carrier_sense_errors_high[0x20]; 1559 1560 u8 dot3stats_carrier_sense_errors_low[0x20]; 1561 1562 u8 dot3stats_frame_too_longs_high[0x20]; 1563 1564 u8 dot3stats_frame_too_longs_low[0x20]; 1565 1566 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1567 1568 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1569 1570 u8 dot3stats_symbol_errors_high[0x20]; 1571 1572 u8 dot3stats_symbol_errors_low[0x20]; 1573 1574 u8 dot3control_in_unknown_opcodes_high[0x20]; 1575 1576 u8 dot3control_in_unknown_opcodes_low[0x20]; 1577 1578 u8 dot3in_pause_frames_high[0x20]; 1579 1580 u8 dot3in_pause_frames_low[0x20]; 1581 1582 u8 dot3out_pause_frames_high[0x20]; 1583 1584 u8 dot3out_pause_frames_low[0x20]; 1585 1586 u8 reserved_at_400[0x3c0]; 1587 }; 1588 1589 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1590 u8 ether_stats_drop_events_high[0x20]; 1591 1592 u8 ether_stats_drop_events_low[0x20]; 1593 1594 u8 ether_stats_octets_high[0x20]; 1595 1596 u8 ether_stats_octets_low[0x20]; 1597 1598 u8 ether_stats_pkts_high[0x20]; 1599 1600 u8 ether_stats_pkts_low[0x20]; 1601 1602 u8 ether_stats_broadcast_pkts_high[0x20]; 1603 1604 u8 ether_stats_broadcast_pkts_low[0x20]; 1605 1606 u8 ether_stats_multicast_pkts_high[0x20]; 1607 1608 u8 ether_stats_multicast_pkts_low[0x20]; 1609 1610 u8 ether_stats_crc_align_errors_high[0x20]; 1611 1612 u8 ether_stats_crc_align_errors_low[0x20]; 1613 1614 u8 ether_stats_undersize_pkts_high[0x20]; 1615 1616 u8 ether_stats_undersize_pkts_low[0x20]; 1617 1618 u8 ether_stats_oversize_pkts_high[0x20]; 1619 1620 u8 ether_stats_oversize_pkts_low[0x20]; 1621 1622 u8 ether_stats_fragments_high[0x20]; 1623 1624 u8 ether_stats_fragments_low[0x20]; 1625 1626 u8 ether_stats_jabbers_high[0x20]; 1627 1628 u8 ether_stats_jabbers_low[0x20]; 1629 1630 u8 ether_stats_collisions_high[0x20]; 1631 1632 u8 ether_stats_collisions_low[0x20]; 1633 1634 u8 ether_stats_pkts64octets_high[0x20]; 1635 1636 u8 ether_stats_pkts64octets_low[0x20]; 1637 1638 u8 ether_stats_pkts65to127octets_high[0x20]; 1639 1640 u8 ether_stats_pkts65to127octets_low[0x20]; 1641 1642 u8 ether_stats_pkts128to255octets_high[0x20]; 1643 1644 u8 ether_stats_pkts128to255octets_low[0x20]; 1645 1646 u8 ether_stats_pkts256to511octets_high[0x20]; 1647 1648 u8 ether_stats_pkts256to511octets_low[0x20]; 1649 1650 u8 ether_stats_pkts512to1023octets_high[0x20]; 1651 1652 u8 ether_stats_pkts512to1023octets_low[0x20]; 1653 1654 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1655 1656 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1657 1658 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1659 1660 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1661 1662 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1663 1664 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1665 1666 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1667 1668 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1669 1670 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1671 1672 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1673 1674 u8 reserved_at_540[0x280]; 1675 }; 1676 1677 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1678 u8 if_in_octets_high[0x20]; 1679 1680 u8 if_in_octets_low[0x20]; 1681 1682 u8 if_in_ucast_pkts_high[0x20]; 1683 1684 u8 if_in_ucast_pkts_low[0x20]; 1685 1686 u8 if_in_discards_high[0x20]; 1687 1688 u8 if_in_discards_low[0x20]; 1689 1690 u8 if_in_errors_high[0x20]; 1691 1692 u8 if_in_errors_low[0x20]; 1693 1694 u8 if_in_unknown_protos_high[0x20]; 1695 1696 u8 if_in_unknown_protos_low[0x20]; 1697 1698 u8 if_out_octets_high[0x20]; 1699 1700 u8 if_out_octets_low[0x20]; 1701 1702 u8 if_out_ucast_pkts_high[0x20]; 1703 1704 u8 if_out_ucast_pkts_low[0x20]; 1705 1706 u8 if_out_discards_high[0x20]; 1707 1708 u8 if_out_discards_low[0x20]; 1709 1710 u8 if_out_errors_high[0x20]; 1711 1712 u8 if_out_errors_low[0x20]; 1713 1714 u8 if_in_multicast_pkts_high[0x20]; 1715 1716 u8 if_in_multicast_pkts_low[0x20]; 1717 1718 u8 if_in_broadcast_pkts_high[0x20]; 1719 1720 u8 if_in_broadcast_pkts_low[0x20]; 1721 1722 u8 if_out_multicast_pkts_high[0x20]; 1723 1724 u8 if_out_multicast_pkts_low[0x20]; 1725 1726 u8 if_out_broadcast_pkts_high[0x20]; 1727 1728 u8 if_out_broadcast_pkts_low[0x20]; 1729 1730 u8 reserved_at_340[0x480]; 1731 }; 1732 1733 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1734 u8 a_frames_transmitted_ok_high[0x20]; 1735 1736 u8 a_frames_transmitted_ok_low[0x20]; 1737 1738 u8 a_frames_received_ok_high[0x20]; 1739 1740 u8 a_frames_received_ok_low[0x20]; 1741 1742 u8 a_frame_check_sequence_errors_high[0x20]; 1743 1744 u8 a_frame_check_sequence_errors_low[0x20]; 1745 1746 u8 a_alignment_errors_high[0x20]; 1747 1748 u8 a_alignment_errors_low[0x20]; 1749 1750 u8 a_octets_transmitted_ok_high[0x20]; 1751 1752 u8 a_octets_transmitted_ok_low[0x20]; 1753 1754 u8 a_octets_received_ok_high[0x20]; 1755 1756 u8 a_octets_received_ok_low[0x20]; 1757 1758 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1759 1760 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1761 1762 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1763 1764 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1765 1766 u8 a_multicast_frames_received_ok_high[0x20]; 1767 1768 u8 a_multicast_frames_received_ok_low[0x20]; 1769 1770 u8 a_broadcast_frames_received_ok_high[0x20]; 1771 1772 u8 a_broadcast_frames_received_ok_low[0x20]; 1773 1774 u8 a_in_range_length_errors_high[0x20]; 1775 1776 u8 a_in_range_length_errors_low[0x20]; 1777 1778 u8 a_out_of_range_length_field_high[0x20]; 1779 1780 u8 a_out_of_range_length_field_low[0x20]; 1781 1782 u8 a_frame_too_long_errors_high[0x20]; 1783 1784 u8 a_frame_too_long_errors_low[0x20]; 1785 1786 u8 a_symbol_error_during_carrier_high[0x20]; 1787 1788 u8 a_symbol_error_during_carrier_low[0x20]; 1789 1790 u8 a_mac_control_frames_transmitted_high[0x20]; 1791 1792 u8 a_mac_control_frames_transmitted_low[0x20]; 1793 1794 u8 a_mac_control_frames_received_high[0x20]; 1795 1796 u8 a_mac_control_frames_received_low[0x20]; 1797 1798 u8 a_unsupported_opcodes_received_high[0x20]; 1799 1800 u8 a_unsupported_opcodes_received_low[0x20]; 1801 1802 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1803 1804 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1805 1806 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1807 1808 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1809 1810 u8 reserved_at_4c0[0x300]; 1811 }; 1812 1813 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1814 u8 life_time_counter_high[0x20]; 1815 1816 u8 life_time_counter_low[0x20]; 1817 1818 u8 rx_errors[0x20]; 1819 1820 u8 tx_errors[0x20]; 1821 1822 u8 l0_to_recovery_eieos[0x20]; 1823 1824 u8 l0_to_recovery_ts[0x20]; 1825 1826 u8 l0_to_recovery_framing[0x20]; 1827 1828 u8 l0_to_recovery_retrain[0x20]; 1829 1830 u8 crc_error_dllp[0x20]; 1831 1832 u8 crc_error_tlp[0x20]; 1833 1834 u8 reserved_at_140[0x680]; 1835 }; 1836 1837 struct mlx5_ifc_cmd_inter_comp_event_bits { 1838 u8 command_completion_vector[0x20]; 1839 1840 u8 reserved_at_20[0xc0]; 1841 }; 1842 1843 struct mlx5_ifc_stall_vl_event_bits { 1844 u8 reserved_at_0[0x18]; 1845 u8 port_num[0x1]; 1846 u8 reserved_at_19[0x3]; 1847 u8 vl[0x4]; 1848 1849 u8 reserved_at_20[0xa0]; 1850 }; 1851 1852 struct mlx5_ifc_db_bf_congestion_event_bits { 1853 u8 event_subtype[0x8]; 1854 u8 reserved_at_8[0x8]; 1855 u8 congestion_level[0x8]; 1856 u8 reserved_at_18[0x8]; 1857 1858 u8 reserved_at_20[0xa0]; 1859 }; 1860 1861 struct mlx5_ifc_gpio_event_bits { 1862 u8 reserved_at_0[0x60]; 1863 1864 u8 gpio_event_hi[0x20]; 1865 1866 u8 gpio_event_lo[0x20]; 1867 1868 u8 reserved_at_a0[0x40]; 1869 }; 1870 1871 struct mlx5_ifc_port_state_change_event_bits { 1872 u8 reserved_at_0[0x40]; 1873 1874 u8 port_num[0x4]; 1875 u8 reserved_at_44[0x1c]; 1876 1877 u8 reserved_at_60[0x80]; 1878 }; 1879 1880 struct mlx5_ifc_dropped_packet_logged_bits { 1881 u8 reserved_at_0[0xe0]; 1882 }; 1883 1884 enum { 1885 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1886 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1887 }; 1888 1889 struct mlx5_ifc_cq_error_bits { 1890 u8 reserved_at_0[0x8]; 1891 u8 cqn[0x18]; 1892 1893 u8 reserved_at_20[0x20]; 1894 1895 u8 reserved_at_40[0x18]; 1896 u8 syndrome[0x8]; 1897 1898 u8 reserved_at_60[0x80]; 1899 }; 1900 1901 struct mlx5_ifc_rdma_page_fault_event_bits { 1902 u8 bytes_committed[0x20]; 1903 1904 u8 r_key[0x20]; 1905 1906 u8 reserved_at_40[0x10]; 1907 u8 packet_len[0x10]; 1908 1909 u8 rdma_op_len[0x20]; 1910 1911 u8 rdma_va[0x40]; 1912 1913 u8 reserved_at_c0[0x5]; 1914 u8 rdma[0x1]; 1915 u8 write[0x1]; 1916 u8 requestor[0x1]; 1917 u8 qp_number[0x18]; 1918 }; 1919 1920 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1921 u8 bytes_committed[0x20]; 1922 1923 u8 reserved_at_20[0x10]; 1924 u8 wqe_index[0x10]; 1925 1926 u8 reserved_at_40[0x10]; 1927 u8 len[0x10]; 1928 1929 u8 reserved_at_60[0x60]; 1930 1931 u8 reserved_at_c0[0x5]; 1932 u8 rdma[0x1]; 1933 u8 write_read[0x1]; 1934 u8 requestor[0x1]; 1935 u8 qpn[0x18]; 1936 }; 1937 1938 struct mlx5_ifc_qp_events_bits { 1939 u8 reserved_at_0[0xa0]; 1940 1941 u8 type[0x8]; 1942 u8 reserved_at_a8[0x18]; 1943 1944 u8 reserved_at_c0[0x8]; 1945 u8 qpn_rqn_sqn[0x18]; 1946 }; 1947 1948 struct mlx5_ifc_dct_events_bits { 1949 u8 reserved_at_0[0xc0]; 1950 1951 u8 reserved_at_c0[0x8]; 1952 u8 dct_number[0x18]; 1953 }; 1954 1955 struct mlx5_ifc_comp_event_bits { 1956 u8 reserved_at_0[0xc0]; 1957 1958 u8 reserved_at_c0[0x8]; 1959 u8 cq_number[0x18]; 1960 }; 1961 1962 enum { 1963 MLX5_QPC_STATE_RST = 0x0, 1964 MLX5_QPC_STATE_INIT = 0x1, 1965 MLX5_QPC_STATE_RTR = 0x2, 1966 MLX5_QPC_STATE_RTS = 0x3, 1967 MLX5_QPC_STATE_SQER = 0x4, 1968 MLX5_QPC_STATE_ERR = 0x6, 1969 MLX5_QPC_STATE_SQD = 0x7, 1970 MLX5_QPC_STATE_SUSPENDED = 0x9, 1971 }; 1972 1973 enum { 1974 MLX5_QPC_ST_RC = 0x0, 1975 MLX5_QPC_ST_UC = 0x1, 1976 MLX5_QPC_ST_UD = 0x2, 1977 MLX5_QPC_ST_XRC = 0x3, 1978 MLX5_QPC_ST_DCI = 0x5, 1979 MLX5_QPC_ST_QP0 = 0x7, 1980 MLX5_QPC_ST_QP1 = 0x8, 1981 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1982 MLX5_QPC_ST_REG_UMR = 0xc, 1983 }; 1984 1985 enum { 1986 MLX5_QPC_PM_STATE_ARMED = 0x0, 1987 MLX5_QPC_PM_STATE_REARM = 0x1, 1988 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1989 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1990 }; 1991 1992 enum { 1993 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1994 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1995 }; 1996 1997 enum { 1998 MLX5_QPC_MTU_256_BYTES = 0x1, 1999 MLX5_QPC_MTU_512_BYTES = 0x2, 2000 MLX5_QPC_MTU_1K_BYTES = 0x3, 2001 MLX5_QPC_MTU_2K_BYTES = 0x4, 2002 MLX5_QPC_MTU_4K_BYTES = 0x5, 2003 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2004 }; 2005 2006 enum { 2007 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2008 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2009 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2010 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2011 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2012 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2013 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2014 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2015 }; 2016 2017 enum { 2018 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2019 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2020 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2021 }; 2022 2023 enum { 2024 MLX5_QPC_CS_RES_DISABLE = 0x0, 2025 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2026 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2027 }; 2028 2029 struct mlx5_ifc_qpc_bits { 2030 u8 state[0x4]; 2031 u8 lag_tx_port_affinity[0x4]; 2032 u8 st[0x8]; 2033 u8 reserved_at_10[0x3]; 2034 u8 pm_state[0x2]; 2035 u8 reserved_at_15[0x7]; 2036 u8 end_padding_mode[0x2]; 2037 u8 reserved_at_1e[0x2]; 2038 2039 u8 wq_signature[0x1]; 2040 u8 block_lb_mc[0x1]; 2041 u8 atomic_like_write_en[0x1]; 2042 u8 latency_sensitive[0x1]; 2043 u8 reserved_at_24[0x1]; 2044 u8 drain_sigerr[0x1]; 2045 u8 reserved_at_26[0x2]; 2046 u8 pd[0x18]; 2047 2048 u8 mtu[0x3]; 2049 u8 log_msg_max[0x5]; 2050 u8 reserved_at_48[0x1]; 2051 u8 log_rq_size[0x4]; 2052 u8 log_rq_stride[0x3]; 2053 u8 no_sq[0x1]; 2054 u8 log_sq_size[0x4]; 2055 u8 reserved_at_55[0x6]; 2056 u8 rlky[0x1]; 2057 u8 ulp_stateless_offload_mode[0x4]; 2058 2059 u8 counter_set_id[0x8]; 2060 u8 uar_page[0x18]; 2061 2062 u8 reserved_at_80[0x8]; 2063 u8 user_index[0x18]; 2064 2065 u8 reserved_at_a0[0x3]; 2066 u8 log_page_size[0x5]; 2067 u8 remote_qpn[0x18]; 2068 2069 struct mlx5_ifc_ads_bits primary_address_path; 2070 2071 struct mlx5_ifc_ads_bits secondary_address_path; 2072 2073 u8 log_ack_req_freq[0x4]; 2074 u8 reserved_at_384[0x4]; 2075 u8 log_sra_max[0x3]; 2076 u8 reserved_at_38b[0x2]; 2077 u8 retry_count[0x3]; 2078 u8 rnr_retry[0x3]; 2079 u8 reserved_at_393[0x1]; 2080 u8 fre[0x1]; 2081 u8 cur_rnr_retry[0x3]; 2082 u8 cur_retry_count[0x3]; 2083 u8 reserved_at_39b[0x5]; 2084 2085 u8 reserved_at_3a0[0x20]; 2086 2087 u8 reserved_at_3c0[0x8]; 2088 u8 next_send_psn[0x18]; 2089 2090 u8 reserved_at_3e0[0x8]; 2091 u8 cqn_snd[0x18]; 2092 2093 u8 reserved_at_400[0x8]; 2094 u8 deth_sqpn[0x18]; 2095 2096 u8 reserved_at_420[0x20]; 2097 2098 u8 reserved_at_440[0x8]; 2099 u8 last_acked_psn[0x18]; 2100 2101 u8 reserved_at_460[0x8]; 2102 u8 ssn[0x18]; 2103 2104 u8 reserved_at_480[0x8]; 2105 u8 log_rra_max[0x3]; 2106 u8 reserved_at_48b[0x1]; 2107 u8 atomic_mode[0x4]; 2108 u8 rre[0x1]; 2109 u8 rwe[0x1]; 2110 u8 rae[0x1]; 2111 u8 reserved_at_493[0x1]; 2112 u8 page_offset[0x6]; 2113 u8 reserved_at_49a[0x3]; 2114 u8 cd_slave_receive[0x1]; 2115 u8 cd_slave_send[0x1]; 2116 u8 cd_master[0x1]; 2117 2118 u8 reserved_at_4a0[0x3]; 2119 u8 min_rnr_nak[0x5]; 2120 u8 next_rcv_psn[0x18]; 2121 2122 u8 reserved_at_4c0[0x8]; 2123 u8 xrcd[0x18]; 2124 2125 u8 reserved_at_4e0[0x8]; 2126 u8 cqn_rcv[0x18]; 2127 2128 u8 dbr_addr[0x40]; 2129 2130 u8 q_key[0x20]; 2131 2132 u8 reserved_at_560[0x5]; 2133 u8 rq_type[0x3]; 2134 u8 srqn_rmpn_xrqn[0x18]; 2135 2136 u8 reserved_at_580[0x8]; 2137 u8 rmsn[0x18]; 2138 2139 u8 hw_sq_wqebb_counter[0x10]; 2140 u8 sw_sq_wqebb_counter[0x10]; 2141 2142 u8 hw_rq_counter[0x20]; 2143 2144 u8 sw_rq_counter[0x20]; 2145 2146 u8 reserved_at_600[0x20]; 2147 2148 u8 reserved_at_620[0xf]; 2149 u8 cgs[0x1]; 2150 u8 cs_req[0x8]; 2151 u8 cs_res[0x8]; 2152 2153 u8 dc_access_key[0x40]; 2154 2155 u8 reserved_at_680[0xc0]; 2156 }; 2157 2158 struct mlx5_ifc_roce_addr_layout_bits { 2159 u8 source_l3_address[16][0x8]; 2160 2161 u8 reserved_at_80[0x3]; 2162 u8 vlan_valid[0x1]; 2163 u8 vlan_id[0xc]; 2164 u8 source_mac_47_32[0x10]; 2165 2166 u8 source_mac_31_0[0x20]; 2167 2168 u8 reserved_at_c0[0x14]; 2169 u8 roce_l3_type[0x4]; 2170 u8 roce_version[0x8]; 2171 2172 u8 reserved_at_e0[0x20]; 2173 }; 2174 2175 union mlx5_ifc_hca_cap_union_bits { 2176 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2177 struct mlx5_ifc_odp_cap_bits odp_cap; 2178 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2179 struct mlx5_ifc_roce_cap_bits roce_cap; 2180 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2181 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2182 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2183 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2184 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2185 struct mlx5_ifc_qos_cap_bits qos_cap; 2186 u8 reserved_at_0[0x8000]; 2187 }; 2188 2189 enum { 2190 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2191 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2192 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2193 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2194 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2195 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2196 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2197 }; 2198 2199 struct mlx5_ifc_flow_context_bits { 2200 u8 reserved_at_0[0x20]; 2201 2202 u8 group_id[0x20]; 2203 2204 u8 reserved_at_40[0x8]; 2205 u8 flow_tag[0x18]; 2206 2207 u8 reserved_at_60[0x10]; 2208 u8 action[0x10]; 2209 2210 u8 reserved_at_80[0x8]; 2211 u8 destination_list_size[0x18]; 2212 2213 u8 reserved_at_a0[0x8]; 2214 u8 flow_counter_list_size[0x18]; 2215 2216 u8 encap_id[0x20]; 2217 2218 u8 modify_header_id[0x20]; 2219 2220 u8 reserved_at_100[0x100]; 2221 2222 struct mlx5_ifc_fte_match_param_bits match_value; 2223 2224 u8 reserved_at_1200[0x600]; 2225 2226 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2227 }; 2228 2229 enum { 2230 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2231 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2232 }; 2233 2234 struct mlx5_ifc_xrc_srqc_bits { 2235 u8 state[0x4]; 2236 u8 log_xrc_srq_size[0x4]; 2237 u8 reserved_at_8[0x18]; 2238 2239 u8 wq_signature[0x1]; 2240 u8 cont_srq[0x1]; 2241 u8 reserved_at_22[0x1]; 2242 u8 rlky[0x1]; 2243 u8 basic_cyclic_rcv_wqe[0x1]; 2244 u8 log_rq_stride[0x3]; 2245 u8 xrcd[0x18]; 2246 2247 u8 page_offset[0x6]; 2248 u8 reserved_at_46[0x2]; 2249 u8 cqn[0x18]; 2250 2251 u8 reserved_at_60[0x20]; 2252 2253 u8 user_index_equal_xrc_srqn[0x1]; 2254 u8 reserved_at_81[0x1]; 2255 u8 log_page_size[0x6]; 2256 u8 user_index[0x18]; 2257 2258 u8 reserved_at_a0[0x20]; 2259 2260 u8 reserved_at_c0[0x8]; 2261 u8 pd[0x18]; 2262 2263 u8 lwm[0x10]; 2264 u8 wqe_cnt[0x10]; 2265 2266 u8 reserved_at_100[0x40]; 2267 2268 u8 db_record_addr_h[0x20]; 2269 2270 u8 db_record_addr_l[0x1e]; 2271 u8 reserved_at_17e[0x2]; 2272 2273 u8 reserved_at_180[0x80]; 2274 }; 2275 2276 struct mlx5_ifc_traffic_counter_bits { 2277 u8 packets[0x40]; 2278 2279 u8 octets[0x40]; 2280 }; 2281 2282 struct mlx5_ifc_tisc_bits { 2283 u8 strict_lag_tx_port_affinity[0x1]; 2284 u8 reserved_at_1[0x3]; 2285 u8 lag_tx_port_affinity[0x04]; 2286 2287 u8 reserved_at_8[0x4]; 2288 u8 prio[0x4]; 2289 u8 reserved_at_10[0x10]; 2290 2291 u8 reserved_at_20[0x100]; 2292 2293 u8 reserved_at_120[0x8]; 2294 u8 transport_domain[0x18]; 2295 2296 u8 reserved_at_140[0x3c0]; 2297 }; 2298 2299 enum { 2300 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2301 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2302 }; 2303 2304 enum { 2305 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2306 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2307 }; 2308 2309 enum { 2310 MLX5_RX_HASH_FN_NONE = 0x0, 2311 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2312 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2313 }; 2314 2315 enum { 2316 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2317 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2318 }; 2319 2320 struct mlx5_ifc_tirc_bits { 2321 u8 reserved_at_0[0x20]; 2322 2323 u8 disp_type[0x4]; 2324 u8 reserved_at_24[0x1c]; 2325 2326 u8 reserved_at_40[0x40]; 2327 2328 u8 reserved_at_80[0x4]; 2329 u8 lro_timeout_period_usecs[0x10]; 2330 u8 lro_enable_mask[0x4]; 2331 u8 lro_max_ip_payload_size[0x8]; 2332 2333 u8 reserved_at_a0[0x40]; 2334 2335 u8 reserved_at_e0[0x8]; 2336 u8 inline_rqn[0x18]; 2337 2338 u8 rx_hash_symmetric[0x1]; 2339 u8 reserved_at_101[0x1]; 2340 u8 tunneled_offload_en[0x1]; 2341 u8 reserved_at_103[0x5]; 2342 u8 indirect_table[0x18]; 2343 2344 u8 rx_hash_fn[0x4]; 2345 u8 reserved_at_124[0x2]; 2346 u8 self_lb_block[0x2]; 2347 u8 transport_domain[0x18]; 2348 2349 u8 rx_hash_toeplitz_key[10][0x20]; 2350 2351 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2352 2353 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2354 2355 u8 reserved_at_2c0[0x4c0]; 2356 }; 2357 2358 enum { 2359 MLX5_SRQC_STATE_GOOD = 0x0, 2360 MLX5_SRQC_STATE_ERROR = 0x1, 2361 }; 2362 2363 struct mlx5_ifc_srqc_bits { 2364 u8 state[0x4]; 2365 u8 log_srq_size[0x4]; 2366 u8 reserved_at_8[0x18]; 2367 2368 u8 wq_signature[0x1]; 2369 u8 cont_srq[0x1]; 2370 u8 reserved_at_22[0x1]; 2371 u8 rlky[0x1]; 2372 u8 reserved_at_24[0x1]; 2373 u8 log_rq_stride[0x3]; 2374 u8 xrcd[0x18]; 2375 2376 u8 page_offset[0x6]; 2377 u8 reserved_at_46[0x2]; 2378 u8 cqn[0x18]; 2379 2380 u8 reserved_at_60[0x20]; 2381 2382 u8 reserved_at_80[0x2]; 2383 u8 log_page_size[0x6]; 2384 u8 reserved_at_88[0x18]; 2385 2386 u8 reserved_at_a0[0x20]; 2387 2388 u8 reserved_at_c0[0x8]; 2389 u8 pd[0x18]; 2390 2391 u8 lwm[0x10]; 2392 u8 wqe_cnt[0x10]; 2393 2394 u8 reserved_at_100[0x40]; 2395 2396 u8 dbr_addr[0x40]; 2397 2398 u8 reserved_at_180[0x80]; 2399 }; 2400 2401 enum { 2402 MLX5_SQC_STATE_RST = 0x0, 2403 MLX5_SQC_STATE_RDY = 0x1, 2404 MLX5_SQC_STATE_ERR = 0x3, 2405 }; 2406 2407 struct mlx5_ifc_sqc_bits { 2408 u8 rlky[0x1]; 2409 u8 cd_master[0x1]; 2410 u8 fre[0x1]; 2411 u8 flush_in_error_en[0x1]; 2412 u8 reserved_at_4[0x1]; 2413 u8 min_wqe_inline_mode[0x3]; 2414 u8 state[0x4]; 2415 u8 reg_umr[0x1]; 2416 u8 reserved_at_d[0x13]; 2417 2418 u8 reserved_at_20[0x8]; 2419 u8 user_index[0x18]; 2420 2421 u8 reserved_at_40[0x8]; 2422 u8 cqn[0x18]; 2423 2424 u8 reserved_at_60[0x90]; 2425 2426 u8 packet_pacing_rate_limit_index[0x10]; 2427 u8 tis_lst_sz[0x10]; 2428 u8 reserved_at_110[0x10]; 2429 2430 u8 reserved_at_120[0x40]; 2431 2432 u8 reserved_at_160[0x8]; 2433 u8 tis_num_0[0x18]; 2434 2435 struct mlx5_ifc_wq_bits wq; 2436 }; 2437 2438 enum { 2439 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2440 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2441 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2442 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2443 }; 2444 2445 struct mlx5_ifc_scheduling_context_bits { 2446 u8 element_type[0x8]; 2447 u8 reserved_at_8[0x18]; 2448 2449 u8 element_attributes[0x20]; 2450 2451 u8 parent_element_id[0x20]; 2452 2453 u8 reserved_at_60[0x40]; 2454 2455 u8 bw_share[0x20]; 2456 2457 u8 max_average_bw[0x20]; 2458 2459 u8 reserved_at_e0[0x120]; 2460 }; 2461 2462 struct mlx5_ifc_rqtc_bits { 2463 u8 reserved_at_0[0xa0]; 2464 2465 u8 reserved_at_a0[0x10]; 2466 u8 rqt_max_size[0x10]; 2467 2468 u8 reserved_at_c0[0x10]; 2469 u8 rqt_actual_size[0x10]; 2470 2471 u8 reserved_at_e0[0x6a0]; 2472 2473 struct mlx5_ifc_rq_num_bits rq_num[0]; 2474 }; 2475 2476 enum { 2477 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2478 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2479 }; 2480 2481 enum { 2482 MLX5_RQC_STATE_RST = 0x0, 2483 MLX5_RQC_STATE_RDY = 0x1, 2484 MLX5_RQC_STATE_ERR = 0x3, 2485 }; 2486 2487 struct mlx5_ifc_rqc_bits { 2488 u8 rlky[0x1]; 2489 u8 reserved_at_1[0x1]; 2490 u8 scatter_fcs[0x1]; 2491 u8 vsd[0x1]; 2492 u8 mem_rq_type[0x4]; 2493 u8 state[0x4]; 2494 u8 reserved_at_c[0x1]; 2495 u8 flush_in_error_en[0x1]; 2496 u8 reserved_at_e[0x12]; 2497 2498 u8 reserved_at_20[0x8]; 2499 u8 user_index[0x18]; 2500 2501 u8 reserved_at_40[0x8]; 2502 u8 cqn[0x18]; 2503 2504 u8 counter_set_id[0x8]; 2505 u8 reserved_at_68[0x18]; 2506 2507 u8 reserved_at_80[0x8]; 2508 u8 rmpn[0x18]; 2509 2510 u8 reserved_at_a0[0xe0]; 2511 2512 struct mlx5_ifc_wq_bits wq; 2513 }; 2514 2515 enum { 2516 MLX5_RMPC_STATE_RDY = 0x1, 2517 MLX5_RMPC_STATE_ERR = 0x3, 2518 }; 2519 2520 struct mlx5_ifc_rmpc_bits { 2521 u8 reserved_at_0[0x8]; 2522 u8 state[0x4]; 2523 u8 reserved_at_c[0x14]; 2524 2525 u8 basic_cyclic_rcv_wqe[0x1]; 2526 u8 reserved_at_21[0x1f]; 2527 2528 u8 reserved_at_40[0x140]; 2529 2530 struct mlx5_ifc_wq_bits wq; 2531 }; 2532 2533 struct mlx5_ifc_nic_vport_context_bits { 2534 u8 reserved_at_0[0x5]; 2535 u8 min_wqe_inline_mode[0x3]; 2536 u8 reserved_at_8[0x17]; 2537 u8 roce_en[0x1]; 2538 2539 u8 arm_change_event[0x1]; 2540 u8 reserved_at_21[0x1a]; 2541 u8 event_on_mtu[0x1]; 2542 u8 event_on_promisc_change[0x1]; 2543 u8 event_on_vlan_change[0x1]; 2544 u8 event_on_mc_address_change[0x1]; 2545 u8 event_on_uc_address_change[0x1]; 2546 2547 u8 reserved_at_40[0xf0]; 2548 2549 u8 mtu[0x10]; 2550 2551 u8 system_image_guid[0x40]; 2552 u8 port_guid[0x40]; 2553 u8 node_guid[0x40]; 2554 2555 u8 reserved_at_200[0x140]; 2556 u8 qkey_violation_counter[0x10]; 2557 u8 reserved_at_350[0x430]; 2558 2559 u8 promisc_uc[0x1]; 2560 u8 promisc_mc[0x1]; 2561 u8 promisc_all[0x1]; 2562 u8 reserved_at_783[0x2]; 2563 u8 allowed_list_type[0x3]; 2564 u8 reserved_at_788[0xc]; 2565 u8 allowed_list_size[0xc]; 2566 2567 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2568 2569 u8 reserved_at_7e0[0x20]; 2570 2571 u8 current_uc_mac_address[0][0x40]; 2572 }; 2573 2574 enum { 2575 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2576 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2577 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2578 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2579 }; 2580 2581 struct mlx5_ifc_mkc_bits { 2582 u8 reserved_at_0[0x1]; 2583 u8 free[0x1]; 2584 u8 reserved_at_2[0xd]; 2585 u8 small_fence_on_rdma_read_response[0x1]; 2586 u8 umr_en[0x1]; 2587 u8 a[0x1]; 2588 u8 rw[0x1]; 2589 u8 rr[0x1]; 2590 u8 lw[0x1]; 2591 u8 lr[0x1]; 2592 u8 access_mode[0x2]; 2593 u8 reserved_at_18[0x8]; 2594 2595 u8 qpn[0x18]; 2596 u8 mkey_7_0[0x8]; 2597 2598 u8 reserved_at_40[0x20]; 2599 2600 u8 length64[0x1]; 2601 u8 bsf_en[0x1]; 2602 u8 sync_umr[0x1]; 2603 u8 reserved_at_63[0x2]; 2604 u8 expected_sigerr_count[0x1]; 2605 u8 reserved_at_66[0x1]; 2606 u8 en_rinval[0x1]; 2607 u8 pd[0x18]; 2608 2609 u8 start_addr[0x40]; 2610 2611 u8 len[0x40]; 2612 2613 u8 bsf_octword_size[0x20]; 2614 2615 u8 reserved_at_120[0x80]; 2616 2617 u8 translations_octword_size[0x20]; 2618 2619 u8 reserved_at_1c0[0x1b]; 2620 u8 log_page_size[0x5]; 2621 2622 u8 reserved_at_1e0[0x20]; 2623 }; 2624 2625 struct mlx5_ifc_pkey_bits { 2626 u8 reserved_at_0[0x10]; 2627 u8 pkey[0x10]; 2628 }; 2629 2630 struct mlx5_ifc_array128_auto_bits { 2631 u8 array128_auto[16][0x8]; 2632 }; 2633 2634 struct mlx5_ifc_hca_vport_context_bits { 2635 u8 field_select[0x20]; 2636 2637 u8 reserved_at_20[0xe0]; 2638 2639 u8 sm_virt_aware[0x1]; 2640 u8 has_smi[0x1]; 2641 u8 has_raw[0x1]; 2642 u8 grh_required[0x1]; 2643 u8 reserved_at_104[0xc]; 2644 u8 port_physical_state[0x4]; 2645 u8 vport_state_policy[0x4]; 2646 u8 port_state[0x4]; 2647 u8 vport_state[0x4]; 2648 2649 u8 reserved_at_120[0x20]; 2650 2651 u8 system_image_guid[0x40]; 2652 2653 u8 port_guid[0x40]; 2654 2655 u8 node_guid[0x40]; 2656 2657 u8 cap_mask1[0x20]; 2658 2659 u8 cap_mask1_field_select[0x20]; 2660 2661 u8 cap_mask2[0x20]; 2662 2663 u8 cap_mask2_field_select[0x20]; 2664 2665 u8 reserved_at_280[0x80]; 2666 2667 u8 lid[0x10]; 2668 u8 reserved_at_310[0x4]; 2669 u8 init_type_reply[0x4]; 2670 u8 lmc[0x3]; 2671 u8 subnet_timeout[0x5]; 2672 2673 u8 sm_lid[0x10]; 2674 u8 sm_sl[0x4]; 2675 u8 reserved_at_334[0xc]; 2676 2677 u8 qkey_violation_counter[0x10]; 2678 u8 pkey_violation_counter[0x10]; 2679 2680 u8 reserved_at_360[0xca0]; 2681 }; 2682 2683 struct mlx5_ifc_esw_vport_context_bits { 2684 u8 reserved_at_0[0x3]; 2685 u8 vport_svlan_strip[0x1]; 2686 u8 vport_cvlan_strip[0x1]; 2687 u8 vport_svlan_insert[0x1]; 2688 u8 vport_cvlan_insert[0x2]; 2689 u8 reserved_at_8[0x18]; 2690 2691 u8 reserved_at_20[0x20]; 2692 2693 u8 svlan_cfi[0x1]; 2694 u8 svlan_pcp[0x3]; 2695 u8 svlan_id[0xc]; 2696 u8 cvlan_cfi[0x1]; 2697 u8 cvlan_pcp[0x3]; 2698 u8 cvlan_id[0xc]; 2699 2700 u8 reserved_at_60[0x7a0]; 2701 }; 2702 2703 enum { 2704 MLX5_EQC_STATUS_OK = 0x0, 2705 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2706 }; 2707 2708 enum { 2709 MLX5_EQC_ST_ARMED = 0x9, 2710 MLX5_EQC_ST_FIRED = 0xa, 2711 }; 2712 2713 struct mlx5_ifc_eqc_bits { 2714 u8 status[0x4]; 2715 u8 reserved_at_4[0x9]; 2716 u8 ec[0x1]; 2717 u8 oi[0x1]; 2718 u8 reserved_at_f[0x5]; 2719 u8 st[0x4]; 2720 u8 reserved_at_18[0x8]; 2721 2722 u8 reserved_at_20[0x20]; 2723 2724 u8 reserved_at_40[0x14]; 2725 u8 page_offset[0x6]; 2726 u8 reserved_at_5a[0x6]; 2727 2728 u8 reserved_at_60[0x3]; 2729 u8 log_eq_size[0x5]; 2730 u8 uar_page[0x18]; 2731 2732 u8 reserved_at_80[0x20]; 2733 2734 u8 reserved_at_a0[0x18]; 2735 u8 intr[0x8]; 2736 2737 u8 reserved_at_c0[0x3]; 2738 u8 log_page_size[0x5]; 2739 u8 reserved_at_c8[0x18]; 2740 2741 u8 reserved_at_e0[0x60]; 2742 2743 u8 reserved_at_140[0x8]; 2744 u8 consumer_counter[0x18]; 2745 2746 u8 reserved_at_160[0x8]; 2747 u8 producer_counter[0x18]; 2748 2749 u8 reserved_at_180[0x80]; 2750 }; 2751 2752 enum { 2753 MLX5_DCTC_STATE_ACTIVE = 0x0, 2754 MLX5_DCTC_STATE_DRAINING = 0x1, 2755 MLX5_DCTC_STATE_DRAINED = 0x2, 2756 }; 2757 2758 enum { 2759 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2760 MLX5_DCTC_CS_RES_NA = 0x1, 2761 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2762 }; 2763 2764 enum { 2765 MLX5_DCTC_MTU_256_BYTES = 0x1, 2766 MLX5_DCTC_MTU_512_BYTES = 0x2, 2767 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2768 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2769 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2770 }; 2771 2772 struct mlx5_ifc_dctc_bits { 2773 u8 reserved_at_0[0x4]; 2774 u8 state[0x4]; 2775 u8 reserved_at_8[0x18]; 2776 2777 u8 reserved_at_20[0x8]; 2778 u8 user_index[0x18]; 2779 2780 u8 reserved_at_40[0x8]; 2781 u8 cqn[0x18]; 2782 2783 u8 counter_set_id[0x8]; 2784 u8 atomic_mode[0x4]; 2785 u8 rre[0x1]; 2786 u8 rwe[0x1]; 2787 u8 rae[0x1]; 2788 u8 atomic_like_write_en[0x1]; 2789 u8 latency_sensitive[0x1]; 2790 u8 rlky[0x1]; 2791 u8 free_ar[0x1]; 2792 u8 reserved_at_73[0xd]; 2793 2794 u8 reserved_at_80[0x8]; 2795 u8 cs_res[0x8]; 2796 u8 reserved_at_90[0x3]; 2797 u8 min_rnr_nak[0x5]; 2798 u8 reserved_at_98[0x8]; 2799 2800 u8 reserved_at_a0[0x8]; 2801 u8 srqn_xrqn[0x18]; 2802 2803 u8 reserved_at_c0[0x8]; 2804 u8 pd[0x18]; 2805 2806 u8 tclass[0x8]; 2807 u8 reserved_at_e8[0x4]; 2808 u8 flow_label[0x14]; 2809 2810 u8 dc_access_key[0x40]; 2811 2812 u8 reserved_at_140[0x5]; 2813 u8 mtu[0x3]; 2814 u8 port[0x8]; 2815 u8 pkey_index[0x10]; 2816 2817 u8 reserved_at_160[0x8]; 2818 u8 my_addr_index[0x8]; 2819 u8 reserved_at_170[0x8]; 2820 u8 hop_limit[0x8]; 2821 2822 u8 dc_access_key_violation_count[0x20]; 2823 2824 u8 reserved_at_1a0[0x14]; 2825 u8 dei_cfi[0x1]; 2826 u8 eth_prio[0x3]; 2827 u8 ecn[0x2]; 2828 u8 dscp[0x6]; 2829 2830 u8 reserved_at_1c0[0x40]; 2831 }; 2832 2833 enum { 2834 MLX5_CQC_STATUS_OK = 0x0, 2835 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2836 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2837 }; 2838 2839 enum { 2840 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2841 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2842 }; 2843 2844 enum { 2845 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2846 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2847 MLX5_CQC_ST_FIRED = 0xa, 2848 }; 2849 2850 enum { 2851 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2852 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2853 MLX5_CQ_PERIOD_NUM_MODES 2854 }; 2855 2856 struct mlx5_ifc_cqc_bits { 2857 u8 status[0x4]; 2858 u8 reserved_at_4[0x4]; 2859 u8 cqe_sz[0x3]; 2860 u8 cc[0x1]; 2861 u8 reserved_at_c[0x1]; 2862 u8 scqe_break_moderation_en[0x1]; 2863 u8 oi[0x1]; 2864 u8 cq_period_mode[0x2]; 2865 u8 cqe_comp_en[0x1]; 2866 u8 mini_cqe_res_format[0x2]; 2867 u8 st[0x4]; 2868 u8 reserved_at_18[0x8]; 2869 2870 u8 reserved_at_20[0x20]; 2871 2872 u8 reserved_at_40[0x14]; 2873 u8 page_offset[0x6]; 2874 u8 reserved_at_5a[0x6]; 2875 2876 u8 reserved_at_60[0x3]; 2877 u8 log_cq_size[0x5]; 2878 u8 uar_page[0x18]; 2879 2880 u8 reserved_at_80[0x4]; 2881 u8 cq_period[0xc]; 2882 u8 cq_max_count[0x10]; 2883 2884 u8 reserved_at_a0[0x18]; 2885 u8 c_eqn[0x8]; 2886 2887 u8 reserved_at_c0[0x3]; 2888 u8 log_page_size[0x5]; 2889 u8 reserved_at_c8[0x18]; 2890 2891 u8 reserved_at_e0[0x20]; 2892 2893 u8 reserved_at_100[0x8]; 2894 u8 last_notified_index[0x18]; 2895 2896 u8 reserved_at_120[0x8]; 2897 u8 last_solicit_index[0x18]; 2898 2899 u8 reserved_at_140[0x8]; 2900 u8 consumer_counter[0x18]; 2901 2902 u8 reserved_at_160[0x8]; 2903 u8 producer_counter[0x18]; 2904 2905 u8 reserved_at_180[0x40]; 2906 2907 u8 dbr_addr[0x40]; 2908 }; 2909 2910 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2911 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2912 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2913 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2914 u8 reserved_at_0[0x800]; 2915 }; 2916 2917 struct mlx5_ifc_query_adapter_param_block_bits { 2918 u8 reserved_at_0[0xc0]; 2919 2920 u8 reserved_at_c0[0x8]; 2921 u8 ieee_vendor_id[0x18]; 2922 2923 u8 reserved_at_e0[0x10]; 2924 u8 vsd_vendor_id[0x10]; 2925 2926 u8 vsd[208][0x8]; 2927 2928 u8 vsd_contd_psid[16][0x8]; 2929 }; 2930 2931 enum { 2932 MLX5_XRQC_STATE_GOOD = 0x0, 2933 MLX5_XRQC_STATE_ERROR = 0x1, 2934 }; 2935 2936 enum { 2937 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 2938 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 2939 }; 2940 2941 enum { 2942 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 2943 }; 2944 2945 struct mlx5_ifc_tag_matching_topology_context_bits { 2946 u8 log_matching_list_sz[0x4]; 2947 u8 reserved_at_4[0xc]; 2948 u8 append_next_index[0x10]; 2949 2950 u8 sw_phase_cnt[0x10]; 2951 u8 hw_phase_cnt[0x10]; 2952 2953 u8 reserved_at_40[0x40]; 2954 }; 2955 2956 struct mlx5_ifc_xrqc_bits { 2957 u8 state[0x4]; 2958 u8 rlkey[0x1]; 2959 u8 reserved_at_5[0xf]; 2960 u8 topology[0x4]; 2961 u8 reserved_at_18[0x4]; 2962 u8 offload[0x4]; 2963 2964 u8 reserved_at_20[0x8]; 2965 u8 user_index[0x18]; 2966 2967 u8 reserved_at_40[0x8]; 2968 u8 cqn[0x18]; 2969 2970 u8 reserved_at_60[0xa0]; 2971 2972 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 2973 2974 u8 reserved_at_180[0x880]; 2975 2976 struct mlx5_ifc_wq_bits wq; 2977 }; 2978 2979 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2980 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2981 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2982 u8 reserved_at_0[0x20]; 2983 }; 2984 2985 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2986 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2987 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2988 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2989 u8 reserved_at_0[0x20]; 2990 }; 2991 2992 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2993 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2994 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2995 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2996 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2997 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2998 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2999 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3000 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3001 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3002 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3003 u8 reserved_at_0[0x7c0]; 3004 }; 3005 3006 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3007 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3008 u8 reserved_at_0[0x7c0]; 3009 }; 3010 3011 union mlx5_ifc_event_auto_bits { 3012 struct mlx5_ifc_comp_event_bits comp_event; 3013 struct mlx5_ifc_dct_events_bits dct_events; 3014 struct mlx5_ifc_qp_events_bits qp_events; 3015 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3016 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3017 struct mlx5_ifc_cq_error_bits cq_error; 3018 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3019 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3020 struct mlx5_ifc_gpio_event_bits gpio_event; 3021 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3022 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3023 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3024 u8 reserved_at_0[0xe0]; 3025 }; 3026 3027 struct mlx5_ifc_health_buffer_bits { 3028 u8 reserved_at_0[0x100]; 3029 3030 u8 assert_existptr[0x20]; 3031 3032 u8 assert_callra[0x20]; 3033 3034 u8 reserved_at_140[0x40]; 3035 3036 u8 fw_version[0x20]; 3037 3038 u8 hw_id[0x20]; 3039 3040 u8 reserved_at_1c0[0x20]; 3041 3042 u8 irisc_index[0x8]; 3043 u8 synd[0x8]; 3044 u8 ext_synd[0x10]; 3045 }; 3046 3047 struct mlx5_ifc_register_loopback_control_bits { 3048 u8 no_lb[0x1]; 3049 u8 reserved_at_1[0x7]; 3050 u8 port[0x8]; 3051 u8 reserved_at_10[0x10]; 3052 3053 u8 reserved_at_20[0x60]; 3054 }; 3055 3056 struct mlx5_ifc_vport_tc_element_bits { 3057 u8 traffic_class[0x4]; 3058 u8 reserved_at_4[0xc]; 3059 u8 vport_number[0x10]; 3060 }; 3061 3062 struct mlx5_ifc_vport_element_bits { 3063 u8 reserved_at_0[0x10]; 3064 u8 vport_number[0x10]; 3065 }; 3066 3067 enum { 3068 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3069 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3070 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3071 }; 3072 3073 struct mlx5_ifc_tsar_element_bits { 3074 u8 reserved_at_0[0x8]; 3075 u8 tsar_type[0x8]; 3076 u8 reserved_at_10[0x10]; 3077 }; 3078 3079 struct mlx5_ifc_teardown_hca_out_bits { 3080 u8 status[0x8]; 3081 u8 reserved_at_8[0x18]; 3082 3083 u8 syndrome[0x20]; 3084 3085 u8 reserved_at_40[0x40]; 3086 }; 3087 3088 enum { 3089 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3090 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 3091 }; 3092 3093 struct mlx5_ifc_teardown_hca_in_bits { 3094 u8 opcode[0x10]; 3095 u8 reserved_at_10[0x10]; 3096 3097 u8 reserved_at_20[0x10]; 3098 u8 op_mod[0x10]; 3099 3100 u8 reserved_at_40[0x10]; 3101 u8 profile[0x10]; 3102 3103 u8 reserved_at_60[0x20]; 3104 }; 3105 3106 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3107 u8 status[0x8]; 3108 u8 reserved_at_8[0x18]; 3109 3110 u8 syndrome[0x20]; 3111 3112 u8 reserved_at_40[0x40]; 3113 }; 3114 3115 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3116 u8 opcode[0x10]; 3117 u8 reserved_at_10[0x10]; 3118 3119 u8 reserved_at_20[0x10]; 3120 u8 op_mod[0x10]; 3121 3122 u8 reserved_at_40[0x8]; 3123 u8 qpn[0x18]; 3124 3125 u8 reserved_at_60[0x20]; 3126 3127 u8 opt_param_mask[0x20]; 3128 3129 u8 reserved_at_a0[0x20]; 3130 3131 struct mlx5_ifc_qpc_bits qpc; 3132 3133 u8 reserved_at_800[0x80]; 3134 }; 3135 3136 struct mlx5_ifc_sqd2rts_qp_out_bits { 3137 u8 status[0x8]; 3138 u8 reserved_at_8[0x18]; 3139 3140 u8 syndrome[0x20]; 3141 3142 u8 reserved_at_40[0x40]; 3143 }; 3144 3145 struct mlx5_ifc_sqd2rts_qp_in_bits { 3146 u8 opcode[0x10]; 3147 u8 reserved_at_10[0x10]; 3148 3149 u8 reserved_at_20[0x10]; 3150 u8 op_mod[0x10]; 3151 3152 u8 reserved_at_40[0x8]; 3153 u8 qpn[0x18]; 3154 3155 u8 reserved_at_60[0x20]; 3156 3157 u8 opt_param_mask[0x20]; 3158 3159 u8 reserved_at_a0[0x20]; 3160 3161 struct mlx5_ifc_qpc_bits qpc; 3162 3163 u8 reserved_at_800[0x80]; 3164 }; 3165 3166 struct mlx5_ifc_set_roce_address_out_bits { 3167 u8 status[0x8]; 3168 u8 reserved_at_8[0x18]; 3169 3170 u8 syndrome[0x20]; 3171 3172 u8 reserved_at_40[0x40]; 3173 }; 3174 3175 struct mlx5_ifc_set_roce_address_in_bits { 3176 u8 opcode[0x10]; 3177 u8 reserved_at_10[0x10]; 3178 3179 u8 reserved_at_20[0x10]; 3180 u8 op_mod[0x10]; 3181 3182 u8 roce_address_index[0x10]; 3183 u8 reserved_at_50[0x10]; 3184 3185 u8 reserved_at_60[0x20]; 3186 3187 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3188 }; 3189 3190 struct mlx5_ifc_set_mad_demux_out_bits { 3191 u8 status[0x8]; 3192 u8 reserved_at_8[0x18]; 3193 3194 u8 syndrome[0x20]; 3195 3196 u8 reserved_at_40[0x40]; 3197 }; 3198 3199 enum { 3200 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3201 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3202 }; 3203 3204 struct mlx5_ifc_set_mad_demux_in_bits { 3205 u8 opcode[0x10]; 3206 u8 reserved_at_10[0x10]; 3207 3208 u8 reserved_at_20[0x10]; 3209 u8 op_mod[0x10]; 3210 3211 u8 reserved_at_40[0x20]; 3212 3213 u8 reserved_at_60[0x6]; 3214 u8 demux_mode[0x2]; 3215 u8 reserved_at_68[0x18]; 3216 }; 3217 3218 struct mlx5_ifc_set_l2_table_entry_out_bits { 3219 u8 status[0x8]; 3220 u8 reserved_at_8[0x18]; 3221 3222 u8 syndrome[0x20]; 3223 3224 u8 reserved_at_40[0x40]; 3225 }; 3226 3227 struct mlx5_ifc_set_l2_table_entry_in_bits { 3228 u8 opcode[0x10]; 3229 u8 reserved_at_10[0x10]; 3230 3231 u8 reserved_at_20[0x10]; 3232 u8 op_mod[0x10]; 3233 3234 u8 reserved_at_40[0x60]; 3235 3236 u8 reserved_at_a0[0x8]; 3237 u8 table_index[0x18]; 3238 3239 u8 reserved_at_c0[0x20]; 3240 3241 u8 reserved_at_e0[0x13]; 3242 u8 vlan_valid[0x1]; 3243 u8 vlan[0xc]; 3244 3245 struct mlx5_ifc_mac_address_layout_bits mac_address; 3246 3247 u8 reserved_at_140[0xc0]; 3248 }; 3249 3250 struct mlx5_ifc_set_issi_out_bits { 3251 u8 status[0x8]; 3252 u8 reserved_at_8[0x18]; 3253 3254 u8 syndrome[0x20]; 3255 3256 u8 reserved_at_40[0x40]; 3257 }; 3258 3259 struct mlx5_ifc_set_issi_in_bits { 3260 u8 opcode[0x10]; 3261 u8 reserved_at_10[0x10]; 3262 3263 u8 reserved_at_20[0x10]; 3264 u8 op_mod[0x10]; 3265 3266 u8 reserved_at_40[0x10]; 3267 u8 current_issi[0x10]; 3268 3269 u8 reserved_at_60[0x20]; 3270 }; 3271 3272 struct mlx5_ifc_set_hca_cap_out_bits { 3273 u8 status[0x8]; 3274 u8 reserved_at_8[0x18]; 3275 3276 u8 syndrome[0x20]; 3277 3278 u8 reserved_at_40[0x40]; 3279 }; 3280 3281 struct mlx5_ifc_set_hca_cap_in_bits { 3282 u8 opcode[0x10]; 3283 u8 reserved_at_10[0x10]; 3284 3285 u8 reserved_at_20[0x10]; 3286 u8 op_mod[0x10]; 3287 3288 u8 reserved_at_40[0x40]; 3289 3290 union mlx5_ifc_hca_cap_union_bits capability; 3291 }; 3292 3293 enum { 3294 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3295 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3296 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3297 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3298 }; 3299 3300 struct mlx5_ifc_set_fte_out_bits { 3301 u8 status[0x8]; 3302 u8 reserved_at_8[0x18]; 3303 3304 u8 syndrome[0x20]; 3305 3306 u8 reserved_at_40[0x40]; 3307 }; 3308 3309 struct mlx5_ifc_set_fte_in_bits { 3310 u8 opcode[0x10]; 3311 u8 reserved_at_10[0x10]; 3312 3313 u8 reserved_at_20[0x10]; 3314 u8 op_mod[0x10]; 3315 3316 u8 other_vport[0x1]; 3317 u8 reserved_at_41[0xf]; 3318 u8 vport_number[0x10]; 3319 3320 u8 reserved_at_60[0x20]; 3321 3322 u8 table_type[0x8]; 3323 u8 reserved_at_88[0x18]; 3324 3325 u8 reserved_at_a0[0x8]; 3326 u8 table_id[0x18]; 3327 3328 u8 reserved_at_c0[0x18]; 3329 u8 modify_enable_mask[0x8]; 3330 3331 u8 reserved_at_e0[0x20]; 3332 3333 u8 flow_index[0x20]; 3334 3335 u8 reserved_at_120[0xe0]; 3336 3337 struct mlx5_ifc_flow_context_bits flow_context; 3338 }; 3339 3340 struct mlx5_ifc_rts2rts_qp_out_bits { 3341 u8 status[0x8]; 3342 u8 reserved_at_8[0x18]; 3343 3344 u8 syndrome[0x20]; 3345 3346 u8 reserved_at_40[0x40]; 3347 }; 3348 3349 struct mlx5_ifc_rts2rts_qp_in_bits { 3350 u8 opcode[0x10]; 3351 u8 reserved_at_10[0x10]; 3352 3353 u8 reserved_at_20[0x10]; 3354 u8 op_mod[0x10]; 3355 3356 u8 reserved_at_40[0x8]; 3357 u8 qpn[0x18]; 3358 3359 u8 reserved_at_60[0x20]; 3360 3361 u8 opt_param_mask[0x20]; 3362 3363 u8 reserved_at_a0[0x20]; 3364 3365 struct mlx5_ifc_qpc_bits qpc; 3366 3367 u8 reserved_at_800[0x80]; 3368 }; 3369 3370 struct mlx5_ifc_rtr2rts_qp_out_bits { 3371 u8 status[0x8]; 3372 u8 reserved_at_8[0x18]; 3373 3374 u8 syndrome[0x20]; 3375 3376 u8 reserved_at_40[0x40]; 3377 }; 3378 3379 struct mlx5_ifc_rtr2rts_qp_in_bits { 3380 u8 opcode[0x10]; 3381 u8 reserved_at_10[0x10]; 3382 3383 u8 reserved_at_20[0x10]; 3384 u8 op_mod[0x10]; 3385 3386 u8 reserved_at_40[0x8]; 3387 u8 qpn[0x18]; 3388 3389 u8 reserved_at_60[0x20]; 3390 3391 u8 opt_param_mask[0x20]; 3392 3393 u8 reserved_at_a0[0x20]; 3394 3395 struct mlx5_ifc_qpc_bits qpc; 3396 3397 u8 reserved_at_800[0x80]; 3398 }; 3399 3400 struct mlx5_ifc_rst2init_qp_out_bits { 3401 u8 status[0x8]; 3402 u8 reserved_at_8[0x18]; 3403 3404 u8 syndrome[0x20]; 3405 3406 u8 reserved_at_40[0x40]; 3407 }; 3408 3409 struct mlx5_ifc_rst2init_qp_in_bits { 3410 u8 opcode[0x10]; 3411 u8 reserved_at_10[0x10]; 3412 3413 u8 reserved_at_20[0x10]; 3414 u8 op_mod[0x10]; 3415 3416 u8 reserved_at_40[0x8]; 3417 u8 qpn[0x18]; 3418 3419 u8 reserved_at_60[0x20]; 3420 3421 u8 opt_param_mask[0x20]; 3422 3423 u8 reserved_at_a0[0x20]; 3424 3425 struct mlx5_ifc_qpc_bits qpc; 3426 3427 u8 reserved_at_800[0x80]; 3428 }; 3429 3430 struct mlx5_ifc_query_xrq_out_bits { 3431 u8 status[0x8]; 3432 u8 reserved_at_8[0x18]; 3433 3434 u8 syndrome[0x20]; 3435 3436 u8 reserved_at_40[0x40]; 3437 3438 struct mlx5_ifc_xrqc_bits xrq_context; 3439 }; 3440 3441 struct mlx5_ifc_query_xrq_in_bits { 3442 u8 opcode[0x10]; 3443 u8 reserved_at_10[0x10]; 3444 3445 u8 reserved_at_20[0x10]; 3446 u8 op_mod[0x10]; 3447 3448 u8 reserved_at_40[0x8]; 3449 u8 xrqn[0x18]; 3450 3451 u8 reserved_at_60[0x20]; 3452 }; 3453 3454 struct mlx5_ifc_query_xrc_srq_out_bits { 3455 u8 status[0x8]; 3456 u8 reserved_at_8[0x18]; 3457 3458 u8 syndrome[0x20]; 3459 3460 u8 reserved_at_40[0x40]; 3461 3462 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3463 3464 u8 reserved_at_280[0x600]; 3465 3466 u8 pas[0][0x40]; 3467 }; 3468 3469 struct mlx5_ifc_query_xrc_srq_in_bits { 3470 u8 opcode[0x10]; 3471 u8 reserved_at_10[0x10]; 3472 3473 u8 reserved_at_20[0x10]; 3474 u8 op_mod[0x10]; 3475 3476 u8 reserved_at_40[0x8]; 3477 u8 xrc_srqn[0x18]; 3478 3479 u8 reserved_at_60[0x20]; 3480 }; 3481 3482 enum { 3483 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3484 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3485 }; 3486 3487 struct mlx5_ifc_query_vport_state_out_bits { 3488 u8 status[0x8]; 3489 u8 reserved_at_8[0x18]; 3490 3491 u8 syndrome[0x20]; 3492 3493 u8 reserved_at_40[0x20]; 3494 3495 u8 reserved_at_60[0x18]; 3496 u8 admin_state[0x4]; 3497 u8 state[0x4]; 3498 }; 3499 3500 enum { 3501 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3502 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3503 }; 3504 3505 struct mlx5_ifc_query_vport_state_in_bits { 3506 u8 opcode[0x10]; 3507 u8 reserved_at_10[0x10]; 3508 3509 u8 reserved_at_20[0x10]; 3510 u8 op_mod[0x10]; 3511 3512 u8 other_vport[0x1]; 3513 u8 reserved_at_41[0xf]; 3514 u8 vport_number[0x10]; 3515 3516 u8 reserved_at_60[0x20]; 3517 }; 3518 3519 struct mlx5_ifc_query_vport_counter_out_bits { 3520 u8 status[0x8]; 3521 u8 reserved_at_8[0x18]; 3522 3523 u8 syndrome[0x20]; 3524 3525 u8 reserved_at_40[0x40]; 3526 3527 struct mlx5_ifc_traffic_counter_bits received_errors; 3528 3529 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3530 3531 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3532 3533 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3534 3535 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3536 3537 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3538 3539 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3540 3541 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3542 3543 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3544 3545 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3546 3547 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3548 3549 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3550 3551 u8 reserved_at_680[0xa00]; 3552 }; 3553 3554 enum { 3555 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3556 }; 3557 3558 struct mlx5_ifc_query_vport_counter_in_bits { 3559 u8 opcode[0x10]; 3560 u8 reserved_at_10[0x10]; 3561 3562 u8 reserved_at_20[0x10]; 3563 u8 op_mod[0x10]; 3564 3565 u8 other_vport[0x1]; 3566 u8 reserved_at_41[0xb]; 3567 u8 port_num[0x4]; 3568 u8 vport_number[0x10]; 3569 3570 u8 reserved_at_60[0x60]; 3571 3572 u8 clear[0x1]; 3573 u8 reserved_at_c1[0x1f]; 3574 3575 u8 reserved_at_e0[0x20]; 3576 }; 3577 3578 struct mlx5_ifc_query_tis_out_bits { 3579 u8 status[0x8]; 3580 u8 reserved_at_8[0x18]; 3581 3582 u8 syndrome[0x20]; 3583 3584 u8 reserved_at_40[0x40]; 3585 3586 struct mlx5_ifc_tisc_bits tis_context; 3587 }; 3588 3589 struct mlx5_ifc_query_tis_in_bits { 3590 u8 opcode[0x10]; 3591 u8 reserved_at_10[0x10]; 3592 3593 u8 reserved_at_20[0x10]; 3594 u8 op_mod[0x10]; 3595 3596 u8 reserved_at_40[0x8]; 3597 u8 tisn[0x18]; 3598 3599 u8 reserved_at_60[0x20]; 3600 }; 3601 3602 struct mlx5_ifc_query_tir_out_bits { 3603 u8 status[0x8]; 3604 u8 reserved_at_8[0x18]; 3605 3606 u8 syndrome[0x20]; 3607 3608 u8 reserved_at_40[0xc0]; 3609 3610 struct mlx5_ifc_tirc_bits tir_context; 3611 }; 3612 3613 struct mlx5_ifc_query_tir_in_bits { 3614 u8 opcode[0x10]; 3615 u8 reserved_at_10[0x10]; 3616 3617 u8 reserved_at_20[0x10]; 3618 u8 op_mod[0x10]; 3619 3620 u8 reserved_at_40[0x8]; 3621 u8 tirn[0x18]; 3622 3623 u8 reserved_at_60[0x20]; 3624 }; 3625 3626 struct mlx5_ifc_query_srq_out_bits { 3627 u8 status[0x8]; 3628 u8 reserved_at_8[0x18]; 3629 3630 u8 syndrome[0x20]; 3631 3632 u8 reserved_at_40[0x40]; 3633 3634 struct mlx5_ifc_srqc_bits srq_context_entry; 3635 3636 u8 reserved_at_280[0x600]; 3637 3638 u8 pas[0][0x40]; 3639 }; 3640 3641 struct mlx5_ifc_query_srq_in_bits { 3642 u8 opcode[0x10]; 3643 u8 reserved_at_10[0x10]; 3644 3645 u8 reserved_at_20[0x10]; 3646 u8 op_mod[0x10]; 3647 3648 u8 reserved_at_40[0x8]; 3649 u8 srqn[0x18]; 3650 3651 u8 reserved_at_60[0x20]; 3652 }; 3653 3654 struct mlx5_ifc_query_sq_out_bits { 3655 u8 status[0x8]; 3656 u8 reserved_at_8[0x18]; 3657 3658 u8 syndrome[0x20]; 3659 3660 u8 reserved_at_40[0xc0]; 3661 3662 struct mlx5_ifc_sqc_bits sq_context; 3663 }; 3664 3665 struct mlx5_ifc_query_sq_in_bits { 3666 u8 opcode[0x10]; 3667 u8 reserved_at_10[0x10]; 3668 3669 u8 reserved_at_20[0x10]; 3670 u8 op_mod[0x10]; 3671 3672 u8 reserved_at_40[0x8]; 3673 u8 sqn[0x18]; 3674 3675 u8 reserved_at_60[0x20]; 3676 }; 3677 3678 struct mlx5_ifc_query_special_contexts_out_bits { 3679 u8 status[0x8]; 3680 u8 reserved_at_8[0x18]; 3681 3682 u8 syndrome[0x20]; 3683 3684 u8 dump_fill_mkey[0x20]; 3685 3686 u8 resd_lkey[0x20]; 3687 3688 u8 null_mkey[0x20]; 3689 3690 u8 reserved_at_a0[0x60]; 3691 }; 3692 3693 struct mlx5_ifc_query_special_contexts_in_bits { 3694 u8 opcode[0x10]; 3695 u8 reserved_at_10[0x10]; 3696 3697 u8 reserved_at_20[0x10]; 3698 u8 op_mod[0x10]; 3699 3700 u8 reserved_at_40[0x40]; 3701 }; 3702 3703 struct mlx5_ifc_query_scheduling_element_out_bits { 3704 u8 opcode[0x10]; 3705 u8 reserved_at_10[0x10]; 3706 3707 u8 reserved_at_20[0x10]; 3708 u8 op_mod[0x10]; 3709 3710 u8 reserved_at_40[0xc0]; 3711 3712 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3713 3714 u8 reserved_at_300[0x100]; 3715 }; 3716 3717 enum { 3718 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3719 }; 3720 3721 struct mlx5_ifc_query_scheduling_element_in_bits { 3722 u8 opcode[0x10]; 3723 u8 reserved_at_10[0x10]; 3724 3725 u8 reserved_at_20[0x10]; 3726 u8 op_mod[0x10]; 3727 3728 u8 scheduling_hierarchy[0x8]; 3729 u8 reserved_at_48[0x18]; 3730 3731 u8 scheduling_element_id[0x20]; 3732 3733 u8 reserved_at_80[0x180]; 3734 }; 3735 3736 struct mlx5_ifc_query_rqt_out_bits { 3737 u8 status[0x8]; 3738 u8 reserved_at_8[0x18]; 3739 3740 u8 syndrome[0x20]; 3741 3742 u8 reserved_at_40[0xc0]; 3743 3744 struct mlx5_ifc_rqtc_bits rqt_context; 3745 }; 3746 3747 struct mlx5_ifc_query_rqt_in_bits { 3748 u8 opcode[0x10]; 3749 u8 reserved_at_10[0x10]; 3750 3751 u8 reserved_at_20[0x10]; 3752 u8 op_mod[0x10]; 3753 3754 u8 reserved_at_40[0x8]; 3755 u8 rqtn[0x18]; 3756 3757 u8 reserved_at_60[0x20]; 3758 }; 3759 3760 struct mlx5_ifc_query_rq_out_bits { 3761 u8 status[0x8]; 3762 u8 reserved_at_8[0x18]; 3763 3764 u8 syndrome[0x20]; 3765 3766 u8 reserved_at_40[0xc0]; 3767 3768 struct mlx5_ifc_rqc_bits rq_context; 3769 }; 3770 3771 struct mlx5_ifc_query_rq_in_bits { 3772 u8 opcode[0x10]; 3773 u8 reserved_at_10[0x10]; 3774 3775 u8 reserved_at_20[0x10]; 3776 u8 op_mod[0x10]; 3777 3778 u8 reserved_at_40[0x8]; 3779 u8 rqn[0x18]; 3780 3781 u8 reserved_at_60[0x20]; 3782 }; 3783 3784 struct mlx5_ifc_query_roce_address_out_bits { 3785 u8 status[0x8]; 3786 u8 reserved_at_8[0x18]; 3787 3788 u8 syndrome[0x20]; 3789 3790 u8 reserved_at_40[0x40]; 3791 3792 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3793 }; 3794 3795 struct mlx5_ifc_query_roce_address_in_bits { 3796 u8 opcode[0x10]; 3797 u8 reserved_at_10[0x10]; 3798 3799 u8 reserved_at_20[0x10]; 3800 u8 op_mod[0x10]; 3801 3802 u8 roce_address_index[0x10]; 3803 u8 reserved_at_50[0x10]; 3804 3805 u8 reserved_at_60[0x20]; 3806 }; 3807 3808 struct mlx5_ifc_query_rmp_out_bits { 3809 u8 status[0x8]; 3810 u8 reserved_at_8[0x18]; 3811 3812 u8 syndrome[0x20]; 3813 3814 u8 reserved_at_40[0xc0]; 3815 3816 struct mlx5_ifc_rmpc_bits rmp_context; 3817 }; 3818 3819 struct mlx5_ifc_query_rmp_in_bits { 3820 u8 opcode[0x10]; 3821 u8 reserved_at_10[0x10]; 3822 3823 u8 reserved_at_20[0x10]; 3824 u8 op_mod[0x10]; 3825 3826 u8 reserved_at_40[0x8]; 3827 u8 rmpn[0x18]; 3828 3829 u8 reserved_at_60[0x20]; 3830 }; 3831 3832 struct mlx5_ifc_query_qp_out_bits { 3833 u8 status[0x8]; 3834 u8 reserved_at_8[0x18]; 3835 3836 u8 syndrome[0x20]; 3837 3838 u8 reserved_at_40[0x40]; 3839 3840 u8 opt_param_mask[0x20]; 3841 3842 u8 reserved_at_a0[0x20]; 3843 3844 struct mlx5_ifc_qpc_bits qpc; 3845 3846 u8 reserved_at_800[0x80]; 3847 3848 u8 pas[0][0x40]; 3849 }; 3850 3851 struct mlx5_ifc_query_qp_in_bits { 3852 u8 opcode[0x10]; 3853 u8 reserved_at_10[0x10]; 3854 3855 u8 reserved_at_20[0x10]; 3856 u8 op_mod[0x10]; 3857 3858 u8 reserved_at_40[0x8]; 3859 u8 qpn[0x18]; 3860 3861 u8 reserved_at_60[0x20]; 3862 }; 3863 3864 struct mlx5_ifc_query_q_counter_out_bits { 3865 u8 status[0x8]; 3866 u8 reserved_at_8[0x18]; 3867 3868 u8 syndrome[0x20]; 3869 3870 u8 reserved_at_40[0x40]; 3871 3872 u8 rx_write_requests[0x20]; 3873 3874 u8 reserved_at_a0[0x20]; 3875 3876 u8 rx_read_requests[0x20]; 3877 3878 u8 reserved_at_e0[0x20]; 3879 3880 u8 rx_atomic_requests[0x20]; 3881 3882 u8 reserved_at_120[0x20]; 3883 3884 u8 rx_dct_connect[0x20]; 3885 3886 u8 reserved_at_160[0x20]; 3887 3888 u8 out_of_buffer[0x20]; 3889 3890 u8 reserved_at_1a0[0x20]; 3891 3892 u8 out_of_sequence[0x20]; 3893 3894 u8 reserved_at_1e0[0x20]; 3895 3896 u8 duplicate_request[0x20]; 3897 3898 u8 reserved_at_220[0x20]; 3899 3900 u8 rnr_nak_retry_err[0x20]; 3901 3902 u8 reserved_at_260[0x20]; 3903 3904 u8 packet_seq_err[0x20]; 3905 3906 u8 reserved_at_2a0[0x20]; 3907 3908 u8 implied_nak_seq_err[0x20]; 3909 3910 u8 reserved_at_2e0[0x20]; 3911 3912 u8 local_ack_timeout_err[0x20]; 3913 3914 u8 reserved_at_320[0x4e0]; 3915 }; 3916 3917 struct mlx5_ifc_query_q_counter_in_bits { 3918 u8 opcode[0x10]; 3919 u8 reserved_at_10[0x10]; 3920 3921 u8 reserved_at_20[0x10]; 3922 u8 op_mod[0x10]; 3923 3924 u8 reserved_at_40[0x80]; 3925 3926 u8 clear[0x1]; 3927 u8 reserved_at_c1[0x1f]; 3928 3929 u8 reserved_at_e0[0x18]; 3930 u8 counter_set_id[0x8]; 3931 }; 3932 3933 struct mlx5_ifc_query_pages_out_bits { 3934 u8 status[0x8]; 3935 u8 reserved_at_8[0x18]; 3936 3937 u8 syndrome[0x20]; 3938 3939 u8 reserved_at_40[0x10]; 3940 u8 function_id[0x10]; 3941 3942 u8 num_pages[0x20]; 3943 }; 3944 3945 enum { 3946 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3947 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3948 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3949 }; 3950 3951 struct mlx5_ifc_query_pages_in_bits { 3952 u8 opcode[0x10]; 3953 u8 reserved_at_10[0x10]; 3954 3955 u8 reserved_at_20[0x10]; 3956 u8 op_mod[0x10]; 3957 3958 u8 reserved_at_40[0x10]; 3959 u8 function_id[0x10]; 3960 3961 u8 reserved_at_60[0x20]; 3962 }; 3963 3964 struct mlx5_ifc_query_nic_vport_context_out_bits { 3965 u8 status[0x8]; 3966 u8 reserved_at_8[0x18]; 3967 3968 u8 syndrome[0x20]; 3969 3970 u8 reserved_at_40[0x40]; 3971 3972 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3973 }; 3974 3975 struct mlx5_ifc_query_nic_vport_context_in_bits { 3976 u8 opcode[0x10]; 3977 u8 reserved_at_10[0x10]; 3978 3979 u8 reserved_at_20[0x10]; 3980 u8 op_mod[0x10]; 3981 3982 u8 other_vport[0x1]; 3983 u8 reserved_at_41[0xf]; 3984 u8 vport_number[0x10]; 3985 3986 u8 reserved_at_60[0x5]; 3987 u8 allowed_list_type[0x3]; 3988 u8 reserved_at_68[0x18]; 3989 }; 3990 3991 struct mlx5_ifc_query_mkey_out_bits { 3992 u8 status[0x8]; 3993 u8 reserved_at_8[0x18]; 3994 3995 u8 syndrome[0x20]; 3996 3997 u8 reserved_at_40[0x40]; 3998 3999 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4000 4001 u8 reserved_at_280[0x600]; 4002 4003 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4004 4005 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4006 }; 4007 4008 struct mlx5_ifc_query_mkey_in_bits { 4009 u8 opcode[0x10]; 4010 u8 reserved_at_10[0x10]; 4011 4012 u8 reserved_at_20[0x10]; 4013 u8 op_mod[0x10]; 4014 4015 u8 reserved_at_40[0x8]; 4016 u8 mkey_index[0x18]; 4017 4018 u8 pg_access[0x1]; 4019 u8 reserved_at_61[0x1f]; 4020 }; 4021 4022 struct mlx5_ifc_query_mad_demux_out_bits { 4023 u8 status[0x8]; 4024 u8 reserved_at_8[0x18]; 4025 4026 u8 syndrome[0x20]; 4027 4028 u8 reserved_at_40[0x40]; 4029 4030 u8 mad_dumux_parameters_block[0x20]; 4031 }; 4032 4033 struct mlx5_ifc_query_mad_demux_in_bits { 4034 u8 opcode[0x10]; 4035 u8 reserved_at_10[0x10]; 4036 4037 u8 reserved_at_20[0x10]; 4038 u8 op_mod[0x10]; 4039 4040 u8 reserved_at_40[0x40]; 4041 }; 4042 4043 struct mlx5_ifc_query_l2_table_entry_out_bits { 4044 u8 status[0x8]; 4045 u8 reserved_at_8[0x18]; 4046 4047 u8 syndrome[0x20]; 4048 4049 u8 reserved_at_40[0xa0]; 4050 4051 u8 reserved_at_e0[0x13]; 4052 u8 vlan_valid[0x1]; 4053 u8 vlan[0xc]; 4054 4055 struct mlx5_ifc_mac_address_layout_bits mac_address; 4056 4057 u8 reserved_at_140[0xc0]; 4058 }; 4059 4060 struct mlx5_ifc_query_l2_table_entry_in_bits { 4061 u8 opcode[0x10]; 4062 u8 reserved_at_10[0x10]; 4063 4064 u8 reserved_at_20[0x10]; 4065 u8 op_mod[0x10]; 4066 4067 u8 reserved_at_40[0x60]; 4068 4069 u8 reserved_at_a0[0x8]; 4070 u8 table_index[0x18]; 4071 4072 u8 reserved_at_c0[0x140]; 4073 }; 4074 4075 struct mlx5_ifc_query_issi_out_bits { 4076 u8 status[0x8]; 4077 u8 reserved_at_8[0x18]; 4078 4079 u8 syndrome[0x20]; 4080 4081 u8 reserved_at_40[0x10]; 4082 u8 current_issi[0x10]; 4083 4084 u8 reserved_at_60[0xa0]; 4085 4086 u8 reserved_at_100[76][0x8]; 4087 u8 supported_issi_dw0[0x20]; 4088 }; 4089 4090 struct mlx5_ifc_query_issi_in_bits { 4091 u8 opcode[0x10]; 4092 u8 reserved_at_10[0x10]; 4093 4094 u8 reserved_at_20[0x10]; 4095 u8 op_mod[0x10]; 4096 4097 u8 reserved_at_40[0x40]; 4098 }; 4099 4100 struct mlx5_ifc_set_driver_version_out_bits { 4101 u8 status[0x8]; 4102 u8 reserved_0[0x18]; 4103 4104 u8 syndrome[0x20]; 4105 u8 reserved_1[0x40]; 4106 }; 4107 4108 struct mlx5_ifc_set_driver_version_in_bits { 4109 u8 opcode[0x10]; 4110 u8 reserved_0[0x10]; 4111 4112 u8 reserved_1[0x10]; 4113 u8 op_mod[0x10]; 4114 4115 u8 reserved_2[0x40]; 4116 u8 driver_version[64][0x8]; 4117 }; 4118 4119 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4120 u8 status[0x8]; 4121 u8 reserved_at_8[0x18]; 4122 4123 u8 syndrome[0x20]; 4124 4125 u8 reserved_at_40[0x40]; 4126 4127 struct mlx5_ifc_pkey_bits pkey[0]; 4128 }; 4129 4130 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4131 u8 opcode[0x10]; 4132 u8 reserved_at_10[0x10]; 4133 4134 u8 reserved_at_20[0x10]; 4135 u8 op_mod[0x10]; 4136 4137 u8 other_vport[0x1]; 4138 u8 reserved_at_41[0xb]; 4139 u8 port_num[0x4]; 4140 u8 vport_number[0x10]; 4141 4142 u8 reserved_at_60[0x10]; 4143 u8 pkey_index[0x10]; 4144 }; 4145 4146 enum { 4147 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4148 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4149 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4150 }; 4151 4152 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4153 u8 status[0x8]; 4154 u8 reserved_at_8[0x18]; 4155 4156 u8 syndrome[0x20]; 4157 4158 u8 reserved_at_40[0x20]; 4159 4160 u8 gids_num[0x10]; 4161 u8 reserved_at_70[0x10]; 4162 4163 struct mlx5_ifc_array128_auto_bits gid[0]; 4164 }; 4165 4166 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4167 u8 opcode[0x10]; 4168 u8 reserved_at_10[0x10]; 4169 4170 u8 reserved_at_20[0x10]; 4171 u8 op_mod[0x10]; 4172 4173 u8 other_vport[0x1]; 4174 u8 reserved_at_41[0xb]; 4175 u8 port_num[0x4]; 4176 u8 vport_number[0x10]; 4177 4178 u8 reserved_at_60[0x10]; 4179 u8 gid_index[0x10]; 4180 }; 4181 4182 struct mlx5_ifc_query_hca_vport_context_out_bits { 4183 u8 status[0x8]; 4184 u8 reserved_at_8[0x18]; 4185 4186 u8 syndrome[0x20]; 4187 4188 u8 reserved_at_40[0x40]; 4189 4190 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4191 }; 4192 4193 struct mlx5_ifc_query_hca_vport_context_in_bits { 4194 u8 opcode[0x10]; 4195 u8 reserved_at_10[0x10]; 4196 4197 u8 reserved_at_20[0x10]; 4198 u8 op_mod[0x10]; 4199 4200 u8 other_vport[0x1]; 4201 u8 reserved_at_41[0xb]; 4202 u8 port_num[0x4]; 4203 u8 vport_number[0x10]; 4204 4205 u8 reserved_at_60[0x20]; 4206 }; 4207 4208 struct mlx5_ifc_query_hca_cap_out_bits { 4209 u8 status[0x8]; 4210 u8 reserved_at_8[0x18]; 4211 4212 u8 syndrome[0x20]; 4213 4214 u8 reserved_at_40[0x40]; 4215 4216 union mlx5_ifc_hca_cap_union_bits capability; 4217 }; 4218 4219 struct mlx5_ifc_query_hca_cap_in_bits { 4220 u8 opcode[0x10]; 4221 u8 reserved_at_10[0x10]; 4222 4223 u8 reserved_at_20[0x10]; 4224 u8 op_mod[0x10]; 4225 4226 u8 reserved_at_40[0x40]; 4227 }; 4228 4229 struct mlx5_ifc_query_flow_table_out_bits { 4230 u8 status[0x8]; 4231 u8 reserved_at_8[0x18]; 4232 4233 u8 syndrome[0x20]; 4234 4235 u8 reserved_at_40[0x80]; 4236 4237 u8 reserved_at_c0[0x8]; 4238 u8 level[0x8]; 4239 u8 reserved_at_d0[0x8]; 4240 u8 log_size[0x8]; 4241 4242 u8 reserved_at_e0[0x120]; 4243 }; 4244 4245 struct mlx5_ifc_query_flow_table_in_bits { 4246 u8 opcode[0x10]; 4247 u8 reserved_at_10[0x10]; 4248 4249 u8 reserved_at_20[0x10]; 4250 u8 op_mod[0x10]; 4251 4252 u8 reserved_at_40[0x40]; 4253 4254 u8 table_type[0x8]; 4255 u8 reserved_at_88[0x18]; 4256 4257 u8 reserved_at_a0[0x8]; 4258 u8 table_id[0x18]; 4259 4260 u8 reserved_at_c0[0x140]; 4261 }; 4262 4263 struct mlx5_ifc_query_fte_out_bits { 4264 u8 status[0x8]; 4265 u8 reserved_at_8[0x18]; 4266 4267 u8 syndrome[0x20]; 4268 4269 u8 reserved_at_40[0x1c0]; 4270 4271 struct mlx5_ifc_flow_context_bits flow_context; 4272 }; 4273 4274 struct mlx5_ifc_query_fte_in_bits { 4275 u8 opcode[0x10]; 4276 u8 reserved_at_10[0x10]; 4277 4278 u8 reserved_at_20[0x10]; 4279 u8 op_mod[0x10]; 4280 4281 u8 reserved_at_40[0x40]; 4282 4283 u8 table_type[0x8]; 4284 u8 reserved_at_88[0x18]; 4285 4286 u8 reserved_at_a0[0x8]; 4287 u8 table_id[0x18]; 4288 4289 u8 reserved_at_c0[0x40]; 4290 4291 u8 flow_index[0x20]; 4292 4293 u8 reserved_at_120[0xe0]; 4294 }; 4295 4296 enum { 4297 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4298 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4299 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4300 }; 4301 4302 struct mlx5_ifc_query_flow_group_out_bits { 4303 u8 status[0x8]; 4304 u8 reserved_at_8[0x18]; 4305 4306 u8 syndrome[0x20]; 4307 4308 u8 reserved_at_40[0xa0]; 4309 4310 u8 start_flow_index[0x20]; 4311 4312 u8 reserved_at_100[0x20]; 4313 4314 u8 end_flow_index[0x20]; 4315 4316 u8 reserved_at_140[0xa0]; 4317 4318 u8 reserved_at_1e0[0x18]; 4319 u8 match_criteria_enable[0x8]; 4320 4321 struct mlx5_ifc_fte_match_param_bits match_criteria; 4322 4323 u8 reserved_at_1200[0xe00]; 4324 }; 4325 4326 struct mlx5_ifc_query_flow_group_in_bits { 4327 u8 opcode[0x10]; 4328 u8 reserved_at_10[0x10]; 4329 4330 u8 reserved_at_20[0x10]; 4331 u8 op_mod[0x10]; 4332 4333 u8 reserved_at_40[0x40]; 4334 4335 u8 table_type[0x8]; 4336 u8 reserved_at_88[0x18]; 4337 4338 u8 reserved_at_a0[0x8]; 4339 u8 table_id[0x18]; 4340 4341 u8 group_id[0x20]; 4342 4343 u8 reserved_at_e0[0x120]; 4344 }; 4345 4346 struct mlx5_ifc_query_flow_counter_out_bits { 4347 u8 status[0x8]; 4348 u8 reserved_at_8[0x18]; 4349 4350 u8 syndrome[0x20]; 4351 4352 u8 reserved_at_40[0x40]; 4353 4354 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4355 }; 4356 4357 struct mlx5_ifc_query_flow_counter_in_bits { 4358 u8 opcode[0x10]; 4359 u8 reserved_at_10[0x10]; 4360 4361 u8 reserved_at_20[0x10]; 4362 u8 op_mod[0x10]; 4363 4364 u8 reserved_at_40[0x80]; 4365 4366 u8 clear[0x1]; 4367 u8 reserved_at_c1[0xf]; 4368 u8 num_of_counters[0x10]; 4369 4370 u8 reserved_at_e0[0x10]; 4371 u8 flow_counter_id[0x10]; 4372 }; 4373 4374 struct mlx5_ifc_query_esw_vport_context_out_bits { 4375 u8 status[0x8]; 4376 u8 reserved_at_8[0x18]; 4377 4378 u8 syndrome[0x20]; 4379 4380 u8 reserved_at_40[0x40]; 4381 4382 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4383 }; 4384 4385 struct mlx5_ifc_query_esw_vport_context_in_bits { 4386 u8 opcode[0x10]; 4387 u8 reserved_at_10[0x10]; 4388 4389 u8 reserved_at_20[0x10]; 4390 u8 op_mod[0x10]; 4391 4392 u8 other_vport[0x1]; 4393 u8 reserved_at_41[0xf]; 4394 u8 vport_number[0x10]; 4395 4396 u8 reserved_at_60[0x20]; 4397 }; 4398 4399 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4400 u8 status[0x8]; 4401 u8 reserved_at_8[0x18]; 4402 4403 u8 syndrome[0x20]; 4404 4405 u8 reserved_at_40[0x40]; 4406 }; 4407 4408 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4409 u8 reserved_at_0[0x1c]; 4410 u8 vport_cvlan_insert[0x1]; 4411 u8 vport_svlan_insert[0x1]; 4412 u8 vport_cvlan_strip[0x1]; 4413 u8 vport_svlan_strip[0x1]; 4414 }; 4415 4416 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4417 u8 opcode[0x10]; 4418 u8 reserved_at_10[0x10]; 4419 4420 u8 reserved_at_20[0x10]; 4421 u8 op_mod[0x10]; 4422 4423 u8 other_vport[0x1]; 4424 u8 reserved_at_41[0xf]; 4425 u8 vport_number[0x10]; 4426 4427 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4428 4429 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4430 }; 4431 4432 struct mlx5_ifc_query_eq_out_bits { 4433 u8 status[0x8]; 4434 u8 reserved_at_8[0x18]; 4435 4436 u8 syndrome[0x20]; 4437 4438 u8 reserved_at_40[0x40]; 4439 4440 struct mlx5_ifc_eqc_bits eq_context_entry; 4441 4442 u8 reserved_at_280[0x40]; 4443 4444 u8 event_bitmask[0x40]; 4445 4446 u8 reserved_at_300[0x580]; 4447 4448 u8 pas[0][0x40]; 4449 }; 4450 4451 struct mlx5_ifc_query_eq_in_bits { 4452 u8 opcode[0x10]; 4453 u8 reserved_at_10[0x10]; 4454 4455 u8 reserved_at_20[0x10]; 4456 u8 op_mod[0x10]; 4457 4458 u8 reserved_at_40[0x18]; 4459 u8 eq_number[0x8]; 4460 4461 u8 reserved_at_60[0x20]; 4462 }; 4463 4464 struct mlx5_ifc_encap_header_in_bits { 4465 u8 reserved_at_0[0x5]; 4466 u8 header_type[0x3]; 4467 u8 reserved_at_8[0xe]; 4468 u8 encap_header_size[0xa]; 4469 4470 u8 reserved_at_20[0x10]; 4471 u8 encap_header[2][0x8]; 4472 4473 u8 more_encap_header[0][0x8]; 4474 }; 4475 4476 struct mlx5_ifc_query_encap_header_out_bits { 4477 u8 status[0x8]; 4478 u8 reserved_at_8[0x18]; 4479 4480 u8 syndrome[0x20]; 4481 4482 u8 reserved_at_40[0xa0]; 4483 4484 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4485 }; 4486 4487 struct mlx5_ifc_query_encap_header_in_bits { 4488 u8 opcode[0x10]; 4489 u8 reserved_at_10[0x10]; 4490 4491 u8 reserved_at_20[0x10]; 4492 u8 op_mod[0x10]; 4493 4494 u8 encap_id[0x20]; 4495 4496 u8 reserved_at_60[0xa0]; 4497 }; 4498 4499 struct mlx5_ifc_alloc_encap_header_out_bits { 4500 u8 status[0x8]; 4501 u8 reserved_at_8[0x18]; 4502 4503 u8 syndrome[0x20]; 4504 4505 u8 encap_id[0x20]; 4506 4507 u8 reserved_at_60[0x20]; 4508 }; 4509 4510 struct mlx5_ifc_alloc_encap_header_in_bits { 4511 u8 opcode[0x10]; 4512 u8 reserved_at_10[0x10]; 4513 4514 u8 reserved_at_20[0x10]; 4515 u8 op_mod[0x10]; 4516 4517 u8 reserved_at_40[0xa0]; 4518 4519 struct mlx5_ifc_encap_header_in_bits encap_header; 4520 }; 4521 4522 struct mlx5_ifc_dealloc_encap_header_out_bits { 4523 u8 status[0x8]; 4524 u8 reserved_at_8[0x18]; 4525 4526 u8 syndrome[0x20]; 4527 4528 u8 reserved_at_40[0x40]; 4529 }; 4530 4531 struct mlx5_ifc_dealloc_encap_header_in_bits { 4532 u8 opcode[0x10]; 4533 u8 reserved_at_10[0x10]; 4534 4535 u8 reserved_20[0x10]; 4536 u8 op_mod[0x10]; 4537 4538 u8 encap_id[0x20]; 4539 4540 u8 reserved_60[0x20]; 4541 }; 4542 4543 struct mlx5_ifc_set_action_in_bits { 4544 u8 action_type[0x4]; 4545 u8 field[0xc]; 4546 u8 reserved_at_10[0x3]; 4547 u8 offset[0x5]; 4548 u8 reserved_at_18[0x3]; 4549 u8 length[0x5]; 4550 4551 u8 data[0x20]; 4552 }; 4553 4554 struct mlx5_ifc_add_action_in_bits { 4555 u8 action_type[0x4]; 4556 u8 field[0xc]; 4557 u8 reserved_at_10[0x10]; 4558 4559 u8 data[0x20]; 4560 }; 4561 4562 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4563 struct mlx5_ifc_set_action_in_bits set_action_in; 4564 struct mlx5_ifc_add_action_in_bits add_action_in; 4565 u8 reserved_at_0[0x40]; 4566 }; 4567 4568 enum { 4569 MLX5_ACTION_TYPE_SET = 0x1, 4570 MLX5_ACTION_TYPE_ADD = 0x2, 4571 }; 4572 4573 enum { 4574 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4575 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4576 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4577 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4578 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4579 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4580 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4581 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4582 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4583 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4584 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4585 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4586 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4587 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4588 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4589 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4590 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4591 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4592 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4593 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4594 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4595 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4596 }; 4597 4598 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4599 u8 status[0x8]; 4600 u8 reserved_at_8[0x18]; 4601 4602 u8 syndrome[0x20]; 4603 4604 u8 modify_header_id[0x20]; 4605 4606 u8 reserved_at_60[0x20]; 4607 }; 4608 4609 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4610 u8 opcode[0x10]; 4611 u8 reserved_at_10[0x10]; 4612 4613 u8 reserved_at_20[0x10]; 4614 u8 op_mod[0x10]; 4615 4616 u8 reserved_at_40[0x20]; 4617 4618 u8 table_type[0x8]; 4619 u8 reserved_at_68[0x10]; 4620 u8 num_of_actions[0x8]; 4621 4622 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4623 }; 4624 4625 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4626 u8 status[0x8]; 4627 u8 reserved_at_8[0x18]; 4628 4629 u8 syndrome[0x20]; 4630 4631 u8 reserved_at_40[0x40]; 4632 }; 4633 4634 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4635 u8 opcode[0x10]; 4636 u8 reserved_at_10[0x10]; 4637 4638 u8 reserved_at_20[0x10]; 4639 u8 op_mod[0x10]; 4640 4641 u8 modify_header_id[0x20]; 4642 4643 u8 reserved_at_60[0x20]; 4644 }; 4645 4646 struct mlx5_ifc_query_dct_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_at_40[0x40]; 4653 4654 struct mlx5_ifc_dctc_bits dct_context_entry; 4655 4656 u8 reserved_at_280[0x180]; 4657 }; 4658 4659 struct mlx5_ifc_query_dct_in_bits { 4660 u8 opcode[0x10]; 4661 u8 reserved_at_10[0x10]; 4662 4663 u8 reserved_at_20[0x10]; 4664 u8 op_mod[0x10]; 4665 4666 u8 reserved_at_40[0x8]; 4667 u8 dctn[0x18]; 4668 4669 u8 reserved_at_60[0x20]; 4670 }; 4671 4672 struct mlx5_ifc_query_cq_out_bits { 4673 u8 status[0x8]; 4674 u8 reserved_at_8[0x18]; 4675 4676 u8 syndrome[0x20]; 4677 4678 u8 reserved_at_40[0x40]; 4679 4680 struct mlx5_ifc_cqc_bits cq_context; 4681 4682 u8 reserved_at_280[0x600]; 4683 4684 u8 pas[0][0x40]; 4685 }; 4686 4687 struct mlx5_ifc_query_cq_in_bits { 4688 u8 opcode[0x10]; 4689 u8 reserved_at_10[0x10]; 4690 4691 u8 reserved_at_20[0x10]; 4692 u8 op_mod[0x10]; 4693 4694 u8 reserved_at_40[0x8]; 4695 u8 cqn[0x18]; 4696 4697 u8 reserved_at_60[0x20]; 4698 }; 4699 4700 struct mlx5_ifc_query_cong_status_out_bits { 4701 u8 status[0x8]; 4702 u8 reserved_at_8[0x18]; 4703 4704 u8 syndrome[0x20]; 4705 4706 u8 reserved_at_40[0x20]; 4707 4708 u8 enable[0x1]; 4709 u8 tag_enable[0x1]; 4710 u8 reserved_at_62[0x1e]; 4711 }; 4712 4713 struct mlx5_ifc_query_cong_status_in_bits { 4714 u8 opcode[0x10]; 4715 u8 reserved_at_10[0x10]; 4716 4717 u8 reserved_at_20[0x10]; 4718 u8 op_mod[0x10]; 4719 4720 u8 reserved_at_40[0x18]; 4721 u8 priority[0x4]; 4722 u8 cong_protocol[0x4]; 4723 4724 u8 reserved_at_60[0x20]; 4725 }; 4726 4727 struct mlx5_ifc_query_cong_statistics_out_bits { 4728 u8 status[0x8]; 4729 u8 reserved_at_8[0x18]; 4730 4731 u8 syndrome[0x20]; 4732 4733 u8 reserved_at_40[0x40]; 4734 4735 u8 cur_flows[0x20]; 4736 4737 u8 sum_flows[0x20]; 4738 4739 u8 cnp_ignored_high[0x20]; 4740 4741 u8 cnp_ignored_low[0x20]; 4742 4743 u8 cnp_handled_high[0x20]; 4744 4745 u8 cnp_handled_low[0x20]; 4746 4747 u8 reserved_at_140[0x100]; 4748 4749 u8 time_stamp_high[0x20]; 4750 4751 u8 time_stamp_low[0x20]; 4752 4753 u8 accumulators_period[0x20]; 4754 4755 u8 ecn_marked_roce_packets_high[0x20]; 4756 4757 u8 ecn_marked_roce_packets_low[0x20]; 4758 4759 u8 cnps_sent_high[0x20]; 4760 4761 u8 cnps_sent_low[0x20]; 4762 4763 u8 reserved_at_320[0x560]; 4764 }; 4765 4766 struct mlx5_ifc_query_cong_statistics_in_bits { 4767 u8 opcode[0x10]; 4768 u8 reserved_at_10[0x10]; 4769 4770 u8 reserved_at_20[0x10]; 4771 u8 op_mod[0x10]; 4772 4773 u8 clear[0x1]; 4774 u8 reserved_at_41[0x1f]; 4775 4776 u8 reserved_at_60[0x20]; 4777 }; 4778 4779 struct mlx5_ifc_query_cong_params_out_bits { 4780 u8 status[0x8]; 4781 u8 reserved_at_8[0x18]; 4782 4783 u8 syndrome[0x20]; 4784 4785 u8 reserved_at_40[0x40]; 4786 4787 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4788 }; 4789 4790 struct mlx5_ifc_query_cong_params_in_bits { 4791 u8 opcode[0x10]; 4792 u8 reserved_at_10[0x10]; 4793 4794 u8 reserved_at_20[0x10]; 4795 u8 op_mod[0x10]; 4796 4797 u8 reserved_at_40[0x1c]; 4798 u8 cong_protocol[0x4]; 4799 4800 u8 reserved_at_60[0x20]; 4801 }; 4802 4803 struct mlx5_ifc_query_adapter_out_bits { 4804 u8 status[0x8]; 4805 u8 reserved_at_8[0x18]; 4806 4807 u8 syndrome[0x20]; 4808 4809 u8 reserved_at_40[0x40]; 4810 4811 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4812 }; 4813 4814 struct mlx5_ifc_query_adapter_in_bits { 4815 u8 opcode[0x10]; 4816 u8 reserved_at_10[0x10]; 4817 4818 u8 reserved_at_20[0x10]; 4819 u8 op_mod[0x10]; 4820 4821 u8 reserved_at_40[0x40]; 4822 }; 4823 4824 struct mlx5_ifc_qp_2rst_out_bits { 4825 u8 status[0x8]; 4826 u8 reserved_at_8[0x18]; 4827 4828 u8 syndrome[0x20]; 4829 4830 u8 reserved_at_40[0x40]; 4831 }; 4832 4833 struct mlx5_ifc_qp_2rst_in_bits { 4834 u8 opcode[0x10]; 4835 u8 reserved_at_10[0x10]; 4836 4837 u8 reserved_at_20[0x10]; 4838 u8 op_mod[0x10]; 4839 4840 u8 reserved_at_40[0x8]; 4841 u8 qpn[0x18]; 4842 4843 u8 reserved_at_60[0x20]; 4844 }; 4845 4846 struct mlx5_ifc_qp_2err_out_bits { 4847 u8 status[0x8]; 4848 u8 reserved_at_8[0x18]; 4849 4850 u8 syndrome[0x20]; 4851 4852 u8 reserved_at_40[0x40]; 4853 }; 4854 4855 struct mlx5_ifc_qp_2err_in_bits { 4856 u8 opcode[0x10]; 4857 u8 reserved_at_10[0x10]; 4858 4859 u8 reserved_at_20[0x10]; 4860 u8 op_mod[0x10]; 4861 4862 u8 reserved_at_40[0x8]; 4863 u8 qpn[0x18]; 4864 4865 u8 reserved_at_60[0x20]; 4866 }; 4867 4868 struct mlx5_ifc_page_fault_resume_out_bits { 4869 u8 status[0x8]; 4870 u8 reserved_at_8[0x18]; 4871 4872 u8 syndrome[0x20]; 4873 4874 u8 reserved_at_40[0x40]; 4875 }; 4876 4877 struct mlx5_ifc_page_fault_resume_in_bits { 4878 u8 opcode[0x10]; 4879 u8 reserved_at_10[0x10]; 4880 4881 u8 reserved_at_20[0x10]; 4882 u8 op_mod[0x10]; 4883 4884 u8 error[0x1]; 4885 u8 reserved_at_41[0x4]; 4886 u8 page_fault_type[0x3]; 4887 u8 wq_number[0x18]; 4888 4889 u8 reserved_at_60[0x8]; 4890 u8 token[0x18]; 4891 }; 4892 4893 struct mlx5_ifc_nop_out_bits { 4894 u8 status[0x8]; 4895 u8 reserved_at_8[0x18]; 4896 4897 u8 syndrome[0x20]; 4898 4899 u8 reserved_at_40[0x40]; 4900 }; 4901 4902 struct mlx5_ifc_nop_in_bits { 4903 u8 opcode[0x10]; 4904 u8 reserved_at_10[0x10]; 4905 4906 u8 reserved_at_20[0x10]; 4907 u8 op_mod[0x10]; 4908 4909 u8 reserved_at_40[0x40]; 4910 }; 4911 4912 struct mlx5_ifc_modify_vport_state_out_bits { 4913 u8 status[0x8]; 4914 u8 reserved_at_8[0x18]; 4915 4916 u8 syndrome[0x20]; 4917 4918 u8 reserved_at_40[0x40]; 4919 }; 4920 4921 struct mlx5_ifc_modify_vport_state_in_bits { 4922 u8 opcode[0x10]; 4923 u8 reserved_at_10[0x10]; 4924 4925 u8 reserved_at_20[0x10]; 4926 u8 op_mod[0x10]; 4927 4928 u8 other_vport[0x1]; 4929 u8 reserved_at_41[0xf]; 4930 u8 vport_number[0x10]; 4931 4932 u8 reserved_at_60[0x18]; 4933 u8 admin_state[0x4]; 4934 u8 reserved_at_7c[0x4]; 4935 }; 4936 4937 struct mlx5_ifc_modify_tis_out_bits { 4938 u8 status[0x8]; 4939 u8 reserved_at_8[0x18]; 4940 4941 u8 syndrome[0x20]; 4942 4943 u8 reserved_at_40[0x40]; 4944 }; 4945 4946 struct mlx5_ifc_modify_tis_bitmask_bits { 4947 u8 reserved_at_0[0x20]; 4948 4949 u8 reserved_at_20[0x1d]; 4950 u8 lag_tx_port_affinity[0x1]; 4951 u8 strict_lag_tx_port_affinity[0x1]; 4952 u8 prio[0x1]; 4953 }; 4954 4955 struct mlx5_ifc_modify_tis_in_bits { 4956 u8 opcode[0x10]; 4957 u8 reserved_at_10[0x10]; 4958 4959 u8 reserved_at_20[0x10]; 4960 u8 op_mod[0x10]; 4961 4962 u8 reserved_at_40[0x8]; 4963 u8 tisn[0x18]; 4964 4965 u8 reserved_at_60[0x20]; 4966 4967 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4968 4969 u8 reserved_at_c0[0x40]; 4970 4971 struct mlx5_ifc_tisc_bits ctx; 4972 }; 4973 4974 struct mlx5_ifc_modify_tir_bitmask_bits { 4975 u8 reserved_at_0[0x20]; 4976 4977 u8 reserved_at_20[0x1b]; 4978 u8 self_lb_en[0x1]; 4979 u8 reserved_at_3c[0x1]; 4980 u8 hash[0x1]; 4981 u8 reserved_at_3e[0x1]; 4982 u8 lro[0x1]; 4983 }; 4984 4985 struct mlx5_ifc_modify_tir_out_bits { 4986 u8 status[0x8]; 4987 u8 reserved_at_8[0x18]; 4988 4989 u8 syndrome[0x20]; 4990 4991 u8 reserved_at_40[0x40]; 4992 }; 4993 4994 struct mlx5_ifc_modify_tir_in_bits { 4995 u8 opcode[0x10]; 4996 u8 reserved_at_10[0x10]; 4997 4998 u8 reserved_at_20[0x10]; 4999 u8 op_mod[0x10]; 5000 5001 u8 reserved_at_40[0x8]; 5002 u8 tirn[0x18]; 5003 5004 u8 reserved_at_60[0x20]; 5005 5006 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5007 5008 u8 reserved_at_c0[0x40]; 5009 5010 struct mlx5_ifc_tirc_bits ctx; 5011 }; 5012 5013 struct mlx5_ifc_modify_sq_out_bits { 5014 u8 status[0x8]; 5015 u8 reserved_at_8[0x18]; 5016 5017 u8 syndrome[0x20]; 5018 5019 u8 reserved_at_40[0x40]; 5020 }; 5021 5022 struct mlx5_ifc_modify_sq_in_bits { 5023 u8 opcode[0x10]; 5024 u8 reserved_at_10[0x10]; 5025 5026 u8 reserved_at_20[0x10]; 5027 u8 op_mod[0x10]; 5028 5029 u8 sq_state[0x4]; 5030 u8 reserved_at_44[0x4]; 5031 u8 sqn[0x18]; 5032 5033 u8 reserved_at_60[0x20]; 5034 5035 u8 modify_bitmask[0x40]; 5036 5037 u8 reserved_at_c0[0x40]; 5038 5039 struct mlx5_ifc_sqc_bits ctx; 5040 }; 5041 5042 struct mlx5_ifc_modify_scheduling_element_out_bits { 5043 u8 status[0x8]; 5044 u8 reserved_at_8[0x18]; 5045 5046 u8 syndrome[0x20]; 5047 5048 u8 reserved_at_40[0x1c0]; 5049 }; 5050 5051 enum { 5052 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5053 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5054 }; 5055 5056 struct mlx5_ifc_modify_scheduling_element_in_bits { 5057 u8 opcode[0x10]; 5058 u8 reserved_at_10[0x10]; 5059 5060 u8 reserved_at_20[0x10]; 5061 u8 op_mod[0x10]; 5062 5063 u8 scheduling_hierarchy[0x8]; 5064 u8 reserved_at_48[0x18]; 5065 5066 u8 scheduling_element_id[0x20]; 5067 5068 u8 reserved_at_80[0x20]; 5069 5070 u8 modify_bitmask[0x20]; 5071 5072 u8 reserved_at_c0[0x40]; 5073 5074 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5075 5076 u8 reserved_at_300[0x100]; 5077 }; 5078 5079 struct mlx5_ifc_modify_rqt_out_bits { 5080 u8 status[0x8]; 5081 u8 reserved_at_8[0x18]; 5082 5083 u8 syndrome[0x20]; 5084 5085 u8 reserved_at_40[0x40]; 5086 }; 5087 5088 struct mlx5_ifc_rqt_bitmask_bits { 5089 u8 reserved_at_0[0x20]; 5090 5091 u8 reserved_at_20[0x1f]; 5092 u8 rqn_list[0x1]; 5093 }; 5094 5095 struct mlx5_ifc_modify_rqt_in_bits { 5096 u8 opcode[0x10]; 5097 u8 reserved_at_10[0x10]; 5098 5099 u8 reserved_at_20[0x10]; 5100 u8 op_mod[0x10]; 5101 5102 u8 reserved_at_40[0x8]; 5103 u8 rqtn[0x18]; 5104 5105 u8 reserved_at_60[0x20]; 5106 5107 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5108 5109 u8 reserved_at_c0[0x40]; 5110 5111 struct mlx5_ifc_rqtc_bits ctx; 5112 }; 5113 5114 struct mlx5_ifc_modify_rq_out_bits { 5115 u8 status[0x8]; 5116 u8 reserved_at_8[0x18]; 5117 5118 u8 syndrome[0x20]; 5119 5120 u8 reserved_at_40[0x40]; 5121 }; 5122 5123 enum { 5124 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5125 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5126 }; 5127 5128 struct mlx5_ifc_modify_rq_in_bits { 5129 u8 opcode[0x10]; 5130 u8 reserved_at_10[0x10]; 5131 5132 u8 reserved_at_20[0x10]; 5133 u8 op_mod[0x10]; 5134 5135 u8 rq_state[0x4]; 5136 u8 reserved_at_44[0x4]; 5137 u8 rqn[0x18]; 5138 5139 u8 reserved_at_60[0x20]; 5140 5141 u8 modify_bitmask[0x40]; 5142 5143 u8 reserved_at_c0[0x40]; 5144 5145 struct mlx5_ifc_rqc_bits ctx; 5146 }; 5147 5148 struct mlx5_ifc_modify_rmp_out_bits { 5149 u8 status[0x8]; 5150 u8 reserved_at_8[0x18]; 5151 5152 u8 syndrome[0x20]; 5153 5154 u8 reserved_at_40[0x40]; 5155 }; 5156 5157 struct mlx5_ifc_rmp_bitmask_bits { 5158 u8 reserved_at_0[0x20]; 5159 5160 u8 reserved_at_20[0x1f]; 5161 u8 lwm[0x1]; 5162 }; 5163 5164 struct mlx5_ifc_modify_rmp_in_bits { 5165 u8 opcode[0x10]; 5166 u8 reserved_at_10[0x10]; 5167 5168 u8 reserved_at_20[0x10]; 5169 u8 op_mod[0x10]; 5170 5171 u8 rmp_state[0x4]; 5172 u8 reserved_at_44[0x4]; 5173 u8 rmpn[0x18]; 5174 5175 u8 reserved_at_60[0x20]; 5176 5177 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5178 5179 u8 reserved_at_c0[0x40]; 5180 5181 struct mlx5_ifc_rmpc_bits ctx; 5182 }; 5183 5184 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5185 u8 status[0x8]; 5186 u8 reserved_at_8[0x18]; 5187 5188 u8 syndrome[0x20]; 5189 5190 u8 reserved_at_40[0x40]; 5191 }; 5192 5193 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5194 u8 reserved_at_0[0x16]; 5195 u8 node_guid[0x1]; 5196 u8 port_guid[0x1]; 5197 u8 min_inline[0x1]; 5198 u8 mtu[0x1]; 5199 u8 change_event[0x1]; 5200 u8 promisc[0x1]; 5201 u8 permanent_address[0x1]; 5202 u8 addresses_list[0x1]; 5203 u8 roce_en[0x1]; 5204 u8 reserved_at_1f[0x1]; 5205 }; 5206 5207 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5208 u8 opcode[0x10]; 5209 u8 reserved_at_10[0x10]; 5210 5211 u8 reserved_at_20[0x10]; 5212 u8 op_mod[0x10]; 5213 5214 u8 other_vport[0x1]; 5215 u8 reserved_at_41[0xf]; 5216 u8 vport_number[0x10]; 5217 5218 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5219 5220 u8 reserved_at_80[0x780]; 5221 5222 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5223 }; 5224 5225 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5226 u8 status[0x8]; 5227 u8 reserved_at_8[0x18]; 5228 5229 u8 syndrome[0x20]; 5230 5231 u8 reserved_at_40[0x40]; 5232 }; 5233 5234 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5235 u8 opcode[0x10]; 5236 u8 reserved_at_10[0x10]; 5237 5238 u8 reserved_at_20[0x10]; 5239 u8 op_mod[0x10]; 5240 5241 u8 other_vport[0x1]; 5242 u8 reserved_at_41[0xb]; 5243 u8 port_num[0x4]; 5244 u8 vport_number[0x10]; 5245 5246 u8 reserved_at_60[0x20]; 5247 5248 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5249 }; 5250 5251 struct mlx5_ifc_modify_cq_out_bits { 5252 u8 status[0x8]; 5253 u8 reserved_at_8[0x18]; 5254 5255 u8 syndrome[0x20]; 5256 5257 u8 reserved_at_40[0x40]; 5258 }; 5259 5260 enum { 5261 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5262 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5263 }; 5264 5265 struct mlx5_ifc_modify_cq_in_bits { 5266 u8 opcode[0x10]; 5267 u8 reserved_at_10[0x10]; 5268 5269 u8 reserved_at_20[0x10]; 5270 u8 op_mod[0x10]; 5271 5272 u8 reserved_at_40[0x8]; 5273 u8 cqn[0x18]; 5274 5275 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5276 5277 struct mlx5_ifc_cqc_bits cq_context; 5278 5279 u8 reserved_at_280[0x600]; 5280 5281 u8 pas[0][0x40]; 5282 }; 5283 5284 struct mlx5_ifc_modify_cong_status_out_bits { 5285 u8 status[0x8]; 5286 u8 reserved_at_8[0x18]; 5287 5288 u8 syndrome[0x20]; 5289 5290 u8 reserved_at_40[0x40]; 5291 }; 5292 5293 struct mlx5_ifc_modify_cong_status_in_bits { 5294 u8 opcode[0x10]; 5295 u8 reserved_at_10[0x10]; 5296 5297 u8 reserved_at_20[0x10]; 5298 u8 op_mod[0x10]; 5299 5300 u8 reserved_at_40[0x18]; 5301 u8 priority[0x4]; 5302 u8 cong_protocol[0x4]; 5303 5304 u8 enable[0x1]; 5305 u8 tag_enable[0x1]; 5306 u8 reserved_at_62[0x1e]; 5307 }; 5308 5309 struct mlx5_ifc_modify_cong_params_out_bits { 5310 u8 status[0x8]; 5311 u8 reserved_at_8[0x18]; 5312 5313 u8 syndrome[0x20]; 5314 5315 u8 reserved_at_40[0x40]; 5316 }; 5317 5318 struct mlx5_ifc_modify_cong_params_in_bits { 5319 u8 opcode[0x10]; 5320 u8 reserved_at_10[0x10]; 5321 5322 u8 reserved_at_20[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 reserved_at_40[0x1c]; 5326 u8 cong_protocol[0x4]; 5327 5328 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5329 5330 u8 reserved_at_80[0x80]; 5331 5332 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5333 }; 5334 5335 struct mlx5_ifc_manage_pages_out_bits { 5336 u8 status[0x8]; 5337 u8 reserved_at_8[0x18]; 5338 5339 u8 syndrome[0x20]; 5340 5341 u8 output_num_entries[0x20]; 5342 5343 u8 reserved_at_60[0x20]; 5344 5345 u8 pas[0][0x40]; 5346 }; 5347 5348 enum { 5349 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5350 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5351 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5352 }; 5353 5354 struct mlx5_ifc_manage_pages_in_bits { 5355 u8 opcode[0x10]; 5356 u8 reserved_at_10[0x10]; 5357 5358 u8 reserved_at_20[0x10]; 5359 u8 op_mod[0x10]; 5360 5361 u8 reserved_at_40[0x10]; 5362 u8 function_id[0x10]; 5363 5364 u8 input_num_entries[0x20]; 5365 5366 u8 pas[0][0x40]; 5367 }; 5368 5369 struct mlx5_ifc_mad_ifc_out_bits { 5370 u8 status[0x8]; 5371 u8 reserved_at_8[0x18]; 5372 5373 u8 syndrome[0x20]; 5374 5375 u8 reserved_at_40[0x40]; 5376 5377 u8 response_mad_packet[256][0x8]; 5378 }; 5379 5380 struct mlx5_ifc_mad_ifc_in_bits { 5381 u8 opcode[0x10]; 5382 u8 reserved_at_10[0x10]; 5383 5384 u8 reserved_at_20[0x10]; 5385 u8 op_mod[0x10]; 5386 5387 u8 remote_lid[0x10]; 5388 u8 reserved_at_50[0x8]; 5389 u8 port[0x8]; 5390 5391 u8 reserved_at_60[0x20]; 5392 5393 u8 mad[256][0x8]; 5394 }; 5395 5396 struct mlx5_ifc_init_hca_out_bits { 5397 u8 status[0x8]; 5398 u8 reserved_at_8[0x18]; 5399 5400 u8 syndrome[0x20]; 5401 5402 u8 reserved_at_40[0x40]; 5403 }; 5404 5405 struct mlx5_ifc_init_hca_in_bits { 5406 u8 opcode[0x10]; 5407 u8 reserved_at_10[0x10]; 5408 5409 u8 reserved_at_20[0x10]; 5410 u8 op_mod[0x10]; 5411 5412 u8 reserved_at_40[0x40]; 5413 }; 5414 5415 struct mlx5_ifc_init2rtr_qp_out_bits { 5416 u8 status[0x8]; 5417 u8 reserved_at_8[0x18]; 5418 5419 u8 syndrome[0x20]; 5420 5421 u8 reserved_at_40[0x40]; 5422 }; 5423 5424 struct mlx5_ifc_init2rtr_qp_in_bits { 5425 u8 opcode[0x10]; 5426 u8 reserved_at_10[0x10]; 5427 5428 u8 reserved_at_20[0x10]; 5429 u8 op_mod[0x10]; 5430 5431 u8 reserved_at_40[0x8]; 5432 u8 qpn[0x18]; 5433 5434 u8 reserved_at_60[0x20]; 5435 5436 u8 opt_param_mask[0x20]; 5437 5438 u8 reserved_at_a0[0x20]; 5439 5440 struct mlx5_ifc_qpc_bits qpc; 5441 5442 u8 reserved_at_800[0x80]; 5443 }; 5444 5445 struct mlx5_ifc_init2init_qp_out_bits { 5446 u8 status[0x8]; 5447 u8 reserved_at_8[0x18]; 5448 5449 u8 syndrome[0x20]; 5450 5451 u8 reserved_at_40[0x40]; 5452 }; 5453 5454 struct mlx5_ifc_init2init_qp_in_bits { 5455 u8 opcode[0x10]; 5456 u8 reserved_at_10[0x10]; 5457 5458 u8 reserved_at_20[0x10]; 5459 u8 op_mod[0x10]; 5460 5461 u8 reserved_at_40[0x8]; 5462 u8 qpn[0x18]; 5463 5464 u8 reserved_at_60[0x20]; 5465 5466 u8 opt_param_mask[0x20]; 5467 5468 u8 reserved_at_a0[0x20]; 5469 5470 struct mlx5_ifc_qpc_bits qpc; 5471 5472 u8 reserved_at_800[0x80]; 5473 }; 5474 5475 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_at_8[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 reserved_at_40[0x40]; 5482 5483 u8 packet_headers_log[128][0x8]; 5484 5485 u8 packet_syndrome[64][0x8]; 5486 }; 5487 5488 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5489 u8 opcode[0x10]; 5490 u8 reserved_at_10[0x10]; 5491 5492 u8 reserved_at_20[0x10]; 5493 u8 op_mod[0x10]; 5494 5495 u8 reserved_at_40[0x40]; 5496 }; 5497 5498 struct mlx5_ifc_gen_eqe_in_bits { 5499 u8 opcode[0x10]; 5500 u8 reserved_at_10[0x10]; 5501 5502 u8 reserved_at_20[0x10]; 5503 u8 op_mod[0x10]; 5504 5505 u8 reserved_at_40[0x18]; 5506 u8 eq_number[0x8]; 5507 5508 u8 reserved_at_60[0x20]; 5509 5510 u8 eqe[64][0x8]; 5511 }; 5512 5513 struct mlx5_ifc_gen_eq_out_bits { 5514 u8 status[0x8]; 5515 u8 reserved_at_8[0x18]; 5516 5517 u8 syndrome[0x20]; 5518 5519 u8 reserved_at_40[0x40]; 5520 }; 5521 5522 struct mlx5_ifc_enable_hca_out_bits { 5523 u8 status[0x8]; 5524 u8 reserved_at_8[0x18]; 5525 5526 u8 syndrome[0x20]; 5527 5528 u8 reserved_at_40[0x20]; 5529 }; 5530 5531 struct mlx5_ifc_enable_hca_in_bits { 5532 u8 opcode[0x10]; 5533 u8 reserved_at_10[0x10]; 5534 5535 u8 reserved_at_20[0x10]; 5536 u8 op_mod[0x10]; 5537 5538 u8 reserved_at_40[0x10]; 5539 u8 function_id[0x10]; 5540 5541 u8 reserved_at_60[0x20]; 5542 }; 5543 5544 struct mlx5_ifc_drain_dct_out_bits { 5545 u8 status[0x8]; 5546 u8 reserved_at_8[0x18]; 5547 5548 u8 syndrome[0x20]; 5549 5550 u8 reserved_at_40[0x40]; 5551 }; 5552 5553 struct mlx5_ifc_drain_dct_in_bits { 5554 u8 opcode[0x10]; 5555 u8 reserved_at_10[0x10]; 5556 5557 u8 reserved_at_20[0x10]; 5558 u8 op_mod[0x10]; 5559 5560 u8 reserved_at_40[0x8]; 5561 u8 dctn[0x18]; 5562 5563 u8 reserved_at_60[0x20]; 5564 }; 5565 5566 struct mlx5_ifc_disable_hca_out_bits { 5567 u8 status[0x8]; 5568 u8 reserved_at_8[0x18]; 5569 5570 u8 syndrome[0x20]; 5571 5572 u8 reserved_at_40[0x20]; 5573 }; 5574 5575 struct mlx5_ifc_disable_hca_in_bits { 5576 u8 opcode[0x10]; 5577 u8 reserved_at_10[0x10]; 5578 5579 u8 reserved_at_20[0x10]; 5580 u8 op_mod[0x10]; 5581 5582 u8 reserved_at_40[0x10]; 5583 u8 function_id[0x10]; 5584 5585 u8 reserved_at_60[0x20]; 5586 }; 5587 5588 struct mlx5_ifc_detach_from_mcg_out_bits { 5589 u8 status[0x8]; 5590 u8 reserved_at_8[0x18]; 5591 5592 u8 syndrome[0x20]; 5593 5594 u8 reserved_at_40[0x40]; 5595 }; 5596 5597 struct mlx5_ifc_detach_from_mcg_in_bits { 5598 u8 opcode[0x10]; 5599 u8 reserved_at_10[0x10]; 5600 5601 u8 reserved_at_20[0x10]; 5602 u8 op_mod[0x10]; 5603 5604 u8 reserved_at_40[0x8]; 5605 u8 qpn[0x18]; 5606 5607 u8 reserved_at_60[0x20]; 5608 5609 u8 multicast_gid[16][0x8]; 5610 }; 5611 5612 struct mlx5_ifc_destroy_xrq_out_bits { 5613 u8 status[0x8]; 5614 u8 reserved_at_8[0x18]; 5615 5616 u8 syndrome[0x20]; 5617 5618 u8 reserved_at_40[0x40]; 5619 }; 5620 5621 struct mlx5_ifc_destroy_xrq_in_bits { 5622 u8 opcode[0x10]; 5623 u8 reserved_at_10[0x10]; 5624 5625 u8 reserved_at_20[0x10]; 5626 u8 op_mod[0x10]; 5627 5628 u8 reserved_at_40[0x8]; 5629 u8 xrqn[0x18]; 5630 5631 u8 reserved_at_60[0x20]; 5632 }; 5633 5634 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5635 u8 status[0x8]; 5636 u8 reserved_at_8[0x18]; 5637 5638 u8 syndrome[0x20]; 5639 5640 u8 reserved_at_40[0x40]; 5641 }; 5642 5643 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5644 u8 opcode[0x10]; 5645 u8 reserved_at_10[0x10]; 5646 5647 u8 reserved_at_20[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 reserved_at_40[0x8]; 5651 u8 xrc_srqn[0x18]; 5652 5653 u8 reserved_at_60[0x20]; 5654 }; 5655 5656 struct mlx5_ifc_destroy_tis_out_bits { 5657 u8 status[0x8]; 5658 u8 reserved_at_8[0x18]; 5659 5660 u8 syndrome[0x20]; 5661 5662 u8 reserved_at_40[0x40]; 5663 }; 5664 5665 struct mlx5_ifc_destroy_tis_in_bits { 5666 u8 opcode[0x10]; 5667 u8 reserved_at_10[0x10]; 5668 5669 u8 reserved_at_20[0x10]; 5670 u8 op_mod[0x10]; 5671 5672 u8 reserved_at_40[0x8]; 5673 u8 tisn[0x18]; 5674 5675 u8 reserved_at_60[0x20]; 5676 }; 5677 5678 struct mlx5_ifc_destroy_tir_out_bits { 5679 u8 status[0x8]; 5680 u8 reserved_at_8[0x18]; 5681 5682 u8 syndrome[0x20]; 5683 5684 u8 reserved_at_40[0x40]; 5685 }; 5686 5687 struct mlx5_ifc_destroy_tir_in_bits { 5688 u8 opcode[0x10]; 5689 u8 reserved_at_10[0x10]; 5690 5691 u8 reserved_at_20[0x10]; 5692 u8 op_mod[0x10]; 5693 5694 u8 reserved_at_40[0x8]; 5695 u8 tirn[0x18]; 5696 5697 u8 reserved_at_60[0x20]; 5698 }; 5699 5700 struct mlx5_ifc_destroy_srq_out_bits { 5701 u8 status[0x8]; 5702 u8 reserved_at_8[0x18]; 5703 5704 u8 syndrome[0x20]; 5705 5706 u8 reserved_at_40[0x40]; 5707 }; 5708 5709 struct mlx5_ifc_destroy_srq_in_bits { 5710 u8 opcode[0x10]; 5711 u8 reserved_at_10[0x10]; 5712 5713 u8 reserved_at_20[0x10]; 5714 u8 op_mod[0x10]; 5715 5716 u8 reserved_at_40[0x8]; 5717 u8 srqn[0x18]; 5718 5719 u8 reserved_at_60[0x20]; 5720 }; 5721 5722 struct mlx5_ifc_destroy_sq_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_at_8[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_at_40[0x40]; 5729 }; 5730 5731 struct mlx5_ifc_destroy_sq_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 reserved_at_40[0x8]; 5739 u8 sqn[0x18]; 5740 5741 u8 reserved_at_60[0x20]; 5742 }; 5743 5744 struct mlx5_ifc_destroy_scheduling_element_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_at_8[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_at_40[0x1c0]; 5751 }; 5752 5753 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5754 u8 opcode[0x10]; 5755 u8 reserved_at_10[0x10]; 5756 5757 u8 reserved_at_20[0x10]; 5758 u8 op_mod[0x10]; 5759 5760 u8 scheduling_hierarchy[0x8]; 5761 u8 reserved_at_48[0x18]; 5762 5763 u8 scheduling_element_id[0x20]; 5764 5765 u8 reserved_at_80[0x180]; 5766 }; 5767 5768 struct mlx5_ifc_destroy_rqt_out_bits { 5769 u8 status[0x8]; 5770 u8 reserved_at_8[0x18]; 5771 5772 u8 syndrome[0x20]; 5773 5774 u8 reserved_at_40[0x40]; 5775 }; 5776 5777 struct mlx5_ifc_destroy_rqt_in_bits { 5778 u8 opcode[0x10]; 5779 u8 reserved_at_10[0x10]; 5780 5781 u8 reserved_at_20[0x10]; 5782 u8 op_mod[0x10]; 5783 5784 u8 reserved_at_40[0x8]; 5785 u8 rqtn[0x18]; 5786 5787 u8 reserved_at_60[0x20]; 5788 }; 5789 5790 struct mlx5_ifc_destroy_rq_out_bits { 5791 u8 status[0x8]; 5792 u8 reserved_at_8[0x18]; 5793 5794 u8 syndrome[0x20]; 5795 5796 u8 reserved_at_40[0x40]; 5797 }; 5798 5799 struct mlx5_ifc_destroy_rq_in_bits { 5800 u8 opcode[0x10]; 5801 u8 reserved_at_10[0x10]; 5802 5803 u8 reserved_at_20[0x10]; 5804 u8 op_mod[0x10]; 5805 5806 u8 reserved_at_40[0x8]; 5807 u8 rqn[0x18]; 5808 5809 u8 reserved_at_60[0x20]; 5810 }; 5811 5812 struct mlx5_ifc_destroy_rmp_out_bits { 5813 u8 status[0x8]; 5814 u8 reserved_at_8[0x18]; 5815 5816 u8 syndrome[0x20]; 5817 5818 u8 reserved_at_40[0x40]; 5819 }; 5820 5821 struct mlx5_ifc_destroy_rmp_in_bits { 5822 u8 opcode[0x10]; 5823 u8 reserved_at_10[0x10]; 5824 5825 u8 reserved_at_20[0x10]; 5826 u8 op_mod[0x10]; 5827 5828 u8 reserved_at_40[0x8]; 5829 u8 rmpn[0x18]; 5830 5831 u8 reserved_at_60[0x20]; 5832 }; 5833 5834 struct mlx5_ifc_destroy_qp_out_bits { 5835 u8 status[0x8]; 5836 u8 reserved_at_8[0x18]; 5837 5838 u8 syndrome[0x20]; 5839 5840 u8 reserved_at_40[0x40]; 5841 }; 5842 5843 struct mlx5_ifc_destroy_qp_in_bits { 5844 u8 opcode[0x10]; 5845 u8 reserved_at_10[0x10]; 5846 5847 u8 reserved_at_20[0x10]; 5848 u8 op_mod[0x10]; 5849 5850 u8 reserved_at_40[0x8]; 5851 u8 qpn[0x18]; 5852 5853 u8 reserved_at_60[0x20]; 5854 }; 5855 5856 struct mlx5_ifc_destroy_psv_out_bits { 5857 u8 status[0x8]; 5858 u8 reserved_at_8[0x18]; 5859 5860 u8 syndrome[0x20]; 5861 5862 u8 reserved_at_40[0x40]; 5863 }; 5864 5865 struct mlx5_ifc_destroy_psv_in_bits { 5866 u8 opcode[0x10]; 5867 u8 reserved_at_10[0x10]; 5868 5869 u8 reserved_at_20[0x10]; 5870 u8 op_mod[0x10]; 5871 5872 u8 reserved_at_40[0x8]; 5873 u8 psvn[0x18]; 5874 5875 u8 reserved_at_60[0x20]; 5876 }; 5877 5878 struct mlx5_ifc_destroy_mkey_out_bits { 5879 u8 status[0x8]; 5880 u8 reserved_at_8[0x18]; 5881 5882 u8 syndrome[0x20]; 5883 5884 u8 reserved_at_40[0x40]; 5885 }; 5886 5887 struct mlx5_ifc_destroy_mkey_in_bits { 5888 u8 opcode[0x10]; 5889 u8 reserved_at_10[0x10]; 5890 5891 u8 reserved_at_20[0x10]; 5892 u8 op_mod[0x10]; 5893 5894 u8 reserved_at_40[0x8]; 5895 u8 mkey_index[0x18]; 5896 5897 u8 reserved_at_60[0x20]; 5898 }; 5899 5900 struct mlx5_ifc_destroy_flow_table_out_bits { 5901 u8 status[0x8]; 5902 u8 reserved_at_8[0x18]; 5903 5904 u8 syndrome[0x20]; 5905 5906 u8 reserved_at_40[0x40]; 5907 }; 5908 5909 struct mlx5_ifc_destroy_flow_table_in_bits { 5910 u8 opcode[0x10]; 5911 u8 reserved_at_10[0x10]; 5912 5913 u8 reserved_at_20[0x10]; 5914 u8 op_mod[0x10]; 5915 5916 u8 other_vport[0x1]; 5917 u8 reserved_at_41[0xf]; 5918 u8 vport_number[0x10]; 5919 5920 u8 reserved_at_60[0x20]; 5921 5922 u8 table_type[0x8]; 5923 u8 reserved_at_88[0x18]; 5924 5925 u8 reserved_at_a0[0x8]; 5926 u8 table_id[0x18]; 5927 5928 u8 reserved_at_c0[0x140]; 5929 }; 5930 5931 struct mlx5_ifc_destroy_flow_group_out_bits { 5932 u8 status[0x8]; 5933 u8 reserved_at_8[0x18]; 5934 5935 u8 syndrome[0x20]; 5936 5937 u8 reserved_at_40[0x40]; 5938 }; 5939 5940 struct mlx5_ifc_destroy_flow_group_in_bits { 5941 u8 opcode[0x10]; 5942 u8 reserved_at_10[0x10]; 5943 5944 u8 reserved_at_20[0x10]; 5945 u8 op_mod[0x10]; 5946 5947 u8 other_vport[0x1]; 5948 u8 reserved_at_41[0xf]; 5949 u8 vport_number[0x10]; 5950 5951 u8 reserved_at_60[0x20]; 5952 5953 u8 table_type[0x8]; 5954 u8 reserved_at_88[0x18]; 5955 5956 u8 reserved_at_a0[0x8]; 5957 u8 table_id[0x18]; 5958 5959 u8 group_id[0x20]; 5960 5961 u8 reserved_at_e0[0x120]; 5962 }; 5963 5964 struct mlx5_ifc_destroy_eq_out_bits { 5965 u8 status[0x8]; 5966 u8 reserved_at_8[0x18]; 5967 5968 u8 syndrome[0x20]; 5969 5970 u8 reserved_at_40[0x40]; 5971 }; 5972 5973 struct mlx5_ifc_destroy_eq_in_bits { 5974 u8 opcode[0x10]; 5975 u8 reserved_at_10[0x10]; 5976 5977 u8 reserved_at_20[0x10]; 5978 u8 op_mod[0x10]; 5979 5980 u8 reserved_at_40[0x18]; 5981 u8 eq_number[0x8]; 5982 5983 u8 reserved_at_60[0x20]; 5984 }; 5985 5986 struct mlx5_ifc_destroy_dct_out_bits { 5987 u8 status[0x8]; 5988 u8 reserved_at_8[0x18]; 5989 5990 u8 syndrome[0x20]; 5991 5992 u8 reserved_at_40[0x40]; 5993 }; 5994 5995 struct mlx5_ifc_destroy_dct_in_bits { 5996 u8 opcode[0x10]; 5997 u8 reserved_at_10[0x10]; 5998 5999 u8 reserved_at_20[0x10]; 6000 u8 op_mod[0x10]; 6001 6002 u8 reserved_at_40[0x8]; 6003 u8 dctn[0x18]; 6004 6005 u8 reserved_at_60[0x20]; 6006 }; 6007 6008 struct mlx5_ifc_destroy_cq_out_bits { 6009 u8 status[0x8]; 6010 u8 reserved_at_8[0x18]; 6011 6012 u8 syndrome[0x20]; 6013 6014 u8 reserved_at_40[0x40]; 6015 }; 6016 6017 struct mlx5_ifc_destroy_cq_in_bits { 6018 u8 opcode[0x10]; 6019 u8 reserved_at_10[0x10]; 6020 6021 u8 reserved_at_20[0x10]; 6022 u8 op_mod[0x10]; 6023 6024 u8 reserved_at_40[0x8]; 6025 u8 cqn[0x18]; 6026 6027 u8 reserved_at_60[0x20]; 6028 }; 6029 6030 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6031 u8 status[0x8]; 6032 u8 reserved_at_8[0x18]; 6033 6034 u8 syndrome[0x20]; 6035 6036 u8 reserved_at_40[0x40]; 6037 }; 6038 6039 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6040 u8 opcode[0x10]; 6041 u8 reserved_at_10[0x10]; 6042 6043 u8 reserved_at_20[0x10]; 6044 u8 op_mod[0x10]; 6045 6046 u8 reserved_at_40[0x20]; 6047 6048 u8 reserved_at_60[0x10]; 6049 u8 vxlan_udp_port[0x10]; 6050 }; 6051 6052 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6053 u8 status[0x8]; 6054 u8 reserved_at_8[0x18]; 6055 6056 u8 syndrome[0x20]; 6057 6058 u8 reserved_at_40[0x40]; 6059 }; 6060 6061 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6062 u8 opcode[0x10]; 6063 u8 reserved_at_10[0x10]; 6064 6065 u8 reserved_at_20[0x10]; 6066 u8 op_mod[0x10]; 6067 6068 u8 reserved_at_40[0x60]; 6069 6070 u8 reserved_at_a0[0x8]; 6071 u8 table_index[0x18]; 6072 6073 u8 reserved_at_c0[0x140]; 6074 }; 6075 6076 struct mlx5_ifc_delete_fte_out_bits { 6077 u8 status[0x8]; 6078 u8 reserved_at_8[0x18]; 6079 6080 u8 syndrome[0x20]; 6081 6082 u8 reserved_at_40[0x40]; 6083 }; 6084 6085 struct mlx5_ifc_delete_fte_in_bits { 6086 u8 opcode[0x10]; 6087 u8 reserved_at_10[0x10]; 6088 6089 u8 reserved_at_20[0x10]; 6090 u8 op_mod[0x10]; 6091 6092 u8 other_vport[0x1]; 6093 u8 reserved_at_41[0xf]; 6094 u8 vport_number[0x10]; 6095 6096 u8 reserved_at_60[0x20]; 6097 6098 u8 table_type[0x8]; 6099 u8 reserved_at_88[0x18]; 6100 6101 u8 reserved_at_a0[0x8]; 6102 u8 table_id[0x18]; 6103 6104 u8 reserved_at_c0[0x40]; 6105 6106 u8 flow_index[0x20]; 6107 6108 u8 reserved_at_120[0xe0]; 6109 }; 6110 6111 struct mlx5_ifc_dealloc_xrcd_out_bits { 6112 u8 status[0x8]; 6113 u8 reserved_at_8[0x18]; 6114 6115 u8 syndrome[0x20]; 6116 6117 u8 reserved_at_40[0x40]; 6118 }; 6119 6120 struct mlx5_ifc_dealloc_xrcd_in_bits { 6121 u8 opcode[0x10]; 6122 u8 reserved_at_10[0x10]; 6123 6124 u8 reserved_at_20[0x10]; 6125 u8 op_mod[0x10]; 6126 6127 u8 reserved_at_40[0x8]; 6128 u8 xrcd[0x18]; 6129 6130 u8 reserved_at_60[0x20]; 6131 }; 6132 6133 struct mlx5_ifc_dealloc_uar_out_bits { 6134 u8 status[0x8]; 6135 u8 reserved_at_8[0x18]; 6136 6137 u8 syndrome[0x20]; 6138 6139 u8 reserved_at_40[0x40]; 6140 }; 6141 6142 struct mlx5_ifc_dealloc_uar_in_bits { 6143 u8 opcode[0x10]; 6144 u8 reserved_at_10[0x10]; 6145 6146 u8 reserved_at_20[0x10]; 6147 u8 op_mod[0x10]; 6148 6149 u8 reserved_at_40[0x8]; 6150 u8 uar[0x18]; 6151 6152 u8 reserved_at_60[0x20]; 6153 }; 6154 6155 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6156 u8 status[0x8]; 6157 u8 reserved_at_8[0x18]; 6158 6159 u8 syndrome[0x20]; 6160 6161 u8 reserved_at_40[0x40]; 6162 }; 6163 6164 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6165 u8 opcode[0x10]; 6166 u8 reserved_at_10[0x10]; 6167 6168 u8 reserved_at_20[0x10]; 6169 u8 op_mod[0x10]; 6170 6171 u8 reserved_at_40[0x8]; 6172 u8 transport_domain[0x18]; 6173 6174 u8 reserved_at_60[0x20]; 6175 }; 6176 6177 struct mlx5_ifc_dealloc_q_counter_out_bits { 6178 u8 status[0x8]; 6179 u8 reserved_at_8[0x18]; 6180 6181 u8 syndrome[0x20]; 6182 6183 u8 reserved_at_40[0x40]; 6184 }; 6185 6186 struct mlx5_ifc_dealloc_q_counter_in_bits { 6187 u8 opcode[0x10]; 6188 u8 reserved_at_10[0x10]; 6189 6190 u8 reserved_at_20[0x10]; 6191 u8 op_mod[0x10]; 6192 6193 u8 reserved_at_40[0x18]; 6194 u8 counter_set_id[0x8]; 6195 6196 u8 reserved_at_60[0x20]; 6197 }; 6198 6199 struct mlx5_ifc_dealloc_pd_out_bits { 6200 u8 status[0x8]; 6201 u8 reserved_at_8[0x18]; 6202 6203 u8 syndrome[0x20]; 6204 6205 u8 reserved_at_40[0x40]; 6206 }; 6207 6208 struct mlx5_ifc_dealloc_pd_in_bits { 6209 u8 opcode[0x10]; 6210 u8 reserved_at_10[0x10]; 6211 6212 u8 reserved_at_20[0x10]; 6213 u8 op_mod[0x10]; 6214 6215 u8 reserved_at_40[0x8]; 6216 u8 pd[0x18]; 6217 6218 u8 reserved_at_60[0x20]; 6219 }; 6220 6221 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6222 u8 status[0x8]; 6223 u8 reserved_at_8[0x18]; 6224 6225 u8 syndrome[0x20]; 6226 6227 u8 reserved_at_40[0x40]; 6228 }; 6229 6230 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6231 u8 opcode[0x10]; 6232 u8 reserved_at_10[0x10]; 6233 6234 u8 reserved_at_20[0x10]; 6235 u8 op_mod[0x10]; 6236 6237 u8 reserved_at_40[0x10]; 6238 u8 flow_counter_id[0x10]; 6239 6240 u8 reserved_at_60[0x20]; 6241 }; 6242 6243 struct mlx5_ifc_create_xrq_out_bits { 6244 u8 status[0x8]; 6245 u8 reserved_at_8[0x18]; 6246 6247 u8 syndrome[0x20]; 6248 6249 u8 reserved_at_40[0x8]; 6250 u8 xrqn[0x18]; 6251 6252 u8 reserved_at_60[0x20]; 6253 }; 6254 6255 struct mlx5_ifc_create_xrq_in_bits { 6256 u8 opcode[0x10]; 6257 u8 reserved_at_10[0x10]; 6258 6259 u8 reserved_at_20[0x10]; 6260 u8 op_mod[0x10]; 6261 6262 u8 reserved_at_40[0x40]; 6263 6264 struct mlx5_ifc_xrqc_bits xrq_context; 6265 }; 6266 6267 struct mlx5_ifc_create_xrc_srq_out_bits { 6268 u8 status[0x8]; 6269 u8 reserved_at_8[0x18]; 6270 6271 u8 syndrome[0x20]; 6272 6273 u8 reserved_at_40[0x8]; 6274 u8 xrc_srqn[0x18]; 6275 6276 u8 reserved_at_60[0x20]; 6277 }; 6278 6279 struct mlx5_ifc_create_xrc_srq_in_bits { 6280 u8 opcode[0x10]; 6281 u8 reserved_at_10[0x10]; 6282 6283 u8 reserved_at_20[0x10]; 6284 u8 op_mod[0x10]; 6285 6286 u8 reserved_at_40[0x40]; 6287 6288 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6289 6290 u8 reserved_at_280[0x600]; 6291 6292 u8 pas[0][0x40]; 6293 }; 6294 6295 struct mlx5_ifc_create_tis_out_bits { 6296 u8 status[0x8]; 6297 u8 reserved_at_8[0x18]; 6298 6299 u8 syndrome[0x20]; 6300 6301 u8 reserved_at_40[0x8]; 6302 u8 tisn[0x18]; 6303 6304 u8 reserved_at_60[0x20]; 6305 }; 6306 6307 struct mlx5_ifc_create_tis_in_bits { 6308 u8 opcode[0x10]; 6309 u8 reserved_at_10[0x10]; 6310 6311 u8 reserved_at_20[0x10]; 6312 u8 op_mod[0x10]; 6313 6314 u8 reserved_at_40[0xc0]; 6315 6316 struct mlx5_ifc_tisc_bits ctx; 6317 }; 6318 6319 struct mlx5_ifc_create_tir_out_bits { 6320 u8 status[0x8]; 6321 u8 reserved_at_8[0x18]; 6322 6323 u8 syndrome[0x20]; 6324 6325 u8 reserved_at_40[0x8]; 6326 u8 tirn[0x18]; 6327 6328 u8 reserved_at_60[0x20]; 6329 }; 6330 6331 struct mlx5_ifc_create_tir_in_bits { 6332 u8 opcode[0x10]; 6333 u8 reserved_at_10[0x10]; 6334 6335 u8 reserved_at_20[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 reserved_at_40[0xc0]; 6339 6340 struct mlx5_ifc_tirc_bits ctx; 6341 }; 6342 6343 struct mlx5_ifc_create_srq_out_bits { 6344 u8 status[0x8]; 6345 u8 reserved_at_8[0x18]; 6346 6347 u8 syndrome[0x20]; 6348 6349 u8 reserved_at_40[0x8]; 6350 u8 srqn[0x18]; 6351 6352 u8 reserved_at_60[0x20]; 6353 }; 6354 6355 struct mlx5_ifc_create_srq_in_bits { 6356 u8 opcode[0x10]; 6357 u8 reserved_at_10[0x10]; 6358 6359 u8 reserved_at_20[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 reserved_at_40[0x40]; 6363 6364 struct mlx5_ifc_srqc_bits srq_context_entry; 6365 6366 u8 reserved_at_280[0x600]; 6367 6368 u8 pas[0][0x40]; 6369 }; 6370 6371 struct mlx5_ifc_create_sq_out_bits { 6372 u8 status[0x8]; 6373 u8 reserved_at_8[0x18]; 6374 6375 u8 syndrome[0x20]; 6376 6377 u8 reserved_at_40[0x8]; 6378 u8 sqn[0x18]; 6379 6380 u8 reserved_at_60[0x20]; 6381 }; 6382 6383 struct mlx5_ifc_create_sq_in_bits { 6384 u8 opcode[0x10]; 6385 u8 reserved_at_10[0x10]; 6386 6387 u8 reserved_at_20[0x10]; 6388 u8 op_mod[0x10]; 6389 6390 u8 reserved_at_40[0xc0]; 6391 6392 struct mlx5_ifc_sqc_bits ctx; 6393 }; 6394 6395 struct mlx5_ifc_create_scheduling_element_out_bits { 6396 u8 status[0x8]; 6397 u8 reserved_at_8[0x18]; 6398 6399 u8 syndrome[0x20]; 6400 6401 u8 reserved_at_40[0x40]; 6402 6403 u8 scheduling_element_id[0x20]; 6404 6405 u8 reserved_at_a0[0x160]; 6406 }; 6407 6408 struct mlx5_ifc_create_scheduling_element_in_bits { 6409 u8 opcode[0x10]; 6410 u8 reserved_at_10[0x10]; 6411 6412 u8 reserved_at_20[0x10]; 6413 u8 op_mod[0x10]; 6414 6415 u8 scheduling_hierarchy[0x8]; 6416 u8 reserved_at_48[0x18]; 6417 6418 u8 reserved_at_60[0xa0]; 6419 6420 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6421 6422 u8 reserved_at_300[0x100]; 6423 }; 6424 6425 struct mlx5_ifc_create_rqt_out_bits { 6426 u8 status[0x8]; 6427 u8 reserved_at_8[0x18]; 6428 6429 u8 syndrome[0x20]; 6430 6431 u8 reserved_at_40[0x8]; 6432 u8 rqtn[0x18]; 6433 6434 u8 reserved_at_60[0x20]; 6435 }; 6436 6437 struct mlx5_ifc_create_rqt_in_bits { 6438 u8 opcode[0x10]; 6439 u8 reserved_at_10[0x10]; 6440 6441 u8 reserved_at_20[0x10]; 6442 u8 op_mod[0x10]; 6443 6444 u8 reserved_at_40[0xc0]; 6445 6446 struct mlx5_ifc_rqtc_bits rqt_context; 6447 }; 6448 6449 struct mlx5_ifc_create_rq_out_bits { 6450 u8 status[0x8]; 6451 u8 reserved_at_8[0x18]; 6452 6453 u8 syndrome[0x20]; 6454 6455 u8 reserved_at_40[0x8]; 6456 u8 rqn[0x18]; 6457 6458 u8 reserved_at_60[0x20]; 6459 }; 6460 6461 struct mlx5_ifc_create_rq_in_bits { 6462 u8 opcode[0x10]; 6463 u8 reserved_at_10[0x10]; 6464 6465 u8 reserved_at_20[0x10]; 6466 u8 op_mod[0x10]; 6467 6468 u8 reserved_at_40[0xc0]; 6469 6470 struct mlx5_ifc_rqc_bits ctx; 6471 }; 6472 6473 struct mlx5_ifc_create_rmp_out_bits { 6474 u8 status[0x8]; 6475 u8 reserved_at_8[0x18]; 6476 6477 u8 syndrome[0x20]; 6478 6479 u8 reserved_at_40[0x8]; 6480 u8 rmpn[0x18]; 6481 6482 u8 reserved_at_60[0x20]; 6483 }; 6484 6485 struct mlx5_ifc_create_rmp_in_bits { 6486 u8 opcode[0x10]; 6487 u8 reserved_at_10[0x10]; 6488 6489 u8 reserved_at_20[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 reserved_at_40[0xc0]; 6493 6494 struct mlx5_ifc_rmpc_bits ctx; 6495 }; 6496 6497 struct mlx5_ifc_create_qp_out_bits { 6498 u8 status[0x8]; 6499 u8 reserved_at_8[0x18]; 6500 6501 u8 syndrome[0x20]; 6502 6503 u8 reserved_at_40[0x8]; 6504 u8 qpn[0x18]; 6505 6506 u8 reserved_at_60[0x20]; 6507 }; 6508 6509 struct mlx5_ifc_create_qp_in_bits { 6510 u8 opcode[0x10]; 6511 u8 reserved_at_10[0x10]; 6512 6513 u8 reserved_at_20[0x10]; 6514 u8 op_mod[0x10]; 6515 6516 u8 reserved_at_40[0x40]; 6517 6518 u8 opt_param_mask[0x20]; 6519 6520 u8 reserved_at_a0[0x20]; 6521 6522 struct mlx5_ifc_qpc_bits qpc; 6523 6524 u8 reserved_at_800[0x80]; 6525 6526 u8 pas[0][0x40]; 6527 }; 6528 6529 struct mlx5_ifc_create_psv_out_bits { 6530 u8 status[0x8]; 6531 u8 reserved_at_8[0x18]; 6532 6533 u8 syndrome[0x20]; 6534 6535 u8 reserved_at_40[0x40]; 6536 6537 u8 reserved_at_80[0x8]; 6538 u8 psv0_index[0x18]; 6539 6540 u8 reserved_at_a0[0x8]; 6541 u8 psv1_index[0x18]; 6542 6543 u8 reserved_at_c0[0x8]; 6544 u8 psv2_index[0x18]; 6545 6546 u8 reserved_at_e0[0x8]; 6547 u8 psv3_index[0x18]; 6548 }; 6549 6550 struct mlx5_ifc_create_psv_in_bits { 6551 u8 opcode[0x10]; 6552 u8 reserved_at_10[0x10]; 6553 6554 u8 reserved_at_20[0x10]; 6555 u8 op_mod[0x10]; 6556 6557 u8 num_psv[0x4]; 6558 u8 reserved_at_44[0x4]; 6559 u8 pd[0x18]; 6560 6561 u8 reserved_at_60[0x20]; 6562 }; 6563 6564 struct mlx5_ifc_create_mkey_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_at_8[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_at_40[0x8]; 6571 u8 mkey_index[0x18]; 6572 6573 u8 reserved_at_60[0x20]; 6574 }; 6575 6576 struct mlx5_ifc_create_mkey_in_bits { 6577 u8 opcode[0x10]; 6578 u8 reserved_at_10[0x10]; 6579 6580 u8 reserved_at_20[0x10]; 6581 u8 op_mod[0x10]; 6582 6583 u8 reserved_at_40[0x20]; 6584 6585 u8 pg_access[0x1]; 6586 u8 reserved_at_61[0x1f]; 6587 6588 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6589 6590 u8 reserved_at_280[0x80]; 6591 6592 u8 translations_octword_actual_size[0x20]; 6593 6594 u8 reserved_at_320[0x560]; 6595 6596 u8 klm_pas_mtt[0][0x20]; 6597 }; 6598 6599 struct mlx5_ifc_create_flow_table_out_bits { 6600 u8 status[0x8]; 6601 u8 reserved_at_8[0x18]; 6602 6603 u8 syndrome[0x20]; 6604 6605 u8 reserved_at_40[0x8]; 6606 u8 table_id[0x18]; 6607 6608 u8 reserved_at_60[0x20]; 6609 }; 6610 6611 struct mlx5_ifc_create_flow_table_in_bits { 6612 u8 opcode[0x10]; 6613 u8 reserved_at_10[0x10]; 6614 6615 u8 reserved_at_20[0x10]; 6616 u8 op_mod[0x10]; 6617 6618 u8 other_vport[0x1]; 6619 u8 reserved_at_41[0xf]; 6620 u8 vport_number[0x10]; 6621 6622 u8 reserved_at_60[0x20]; 6623 6624 u8 table_type[0x8]; 6625 u8 reserved_at_88[0x18]; 6626 6627 u8 reserved_at_a0[0x20]; 6628 6629 u8 encap_en[0x1]; 6630 u8 decap_en[0x1]; 6631 u8 reserved_at_c2[0x2]; 6632 u8 table_miss_mode[0x4]; 6633 u8 level[0x8]; 6634 u8 reserved_at_d0[0x8]; 6635 u8 log_size[0x8]; 6636 6637 u8 reserved_at_e0[0x8]; 6638 u8 table_miss_id[0x18]; 6639 6640 u8 reserved_at_100[0x8]; 6641 u8 lag_master_next_table_id[0x18]; 6642 6643 u8 reserved_at_120[0x80]; 6644 }; 6645 6646 struct mlx5_ifc_create_flow_group_out_bits { 6647 u8 status[0x8]; 6648 u8 reserved_at_8[0x18]; 6649 6650 u8 syndrome[0x20]; 6651 6652 u8 reserved_at_40[0x8]; 6653 u8 group_id[0x18]; 6654 6655 u8 reserved_at_60[0x20]; 6656 }; 6657 6658 enum { 6659 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6660 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6661 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6662 }; 6663 6664 struct mlx5_ifc_create_flow_group_in_bits { 6665 u8 opcode[0x10]; 6666 u8 reserved_at_10[0x10]; 6667 6668 u8 reserved_at_20[0x10]; 6669 u8 op_mod[0x10]; 6670 6671 u8 other_vport[0x1]; 6672 u8 reserved_at_41[0xf]; 6673 u8 vport_number[0x10]; 6674 6675 u8 reserved_at_60[0x20]; 6676 6677 u8 table_type[0x8]; 6678 u8 reserved_at_88[0x18]; 6679 6680 u8 reserved_at_a0[0x8]; 6681 u8 table_id[0x18]; 6682 6683 u8 reserved_at_c0[0x20]; 6684 6685 u8 start_flow_index[0x20]; 6686 6687 u8 reserved_at_100[0x20]; 6688 6689 u8 end_flow_index[0x20]; 6690 6691 u8 reserved_at_140[0xa0]; 6692 6693 u8 reserved_at_1e0[0x18]; 6694 u8 match_criteria_enable[0x8]; 6695 6696 struct mlx5_ifc_fte_match_param_bits match_criteria; 6697 6698 u8 reserved_at_1200[0xe00]; 6699 }; 6700 6701 struct mlx5_ifc_create_eq_out_bits { 6702 u8 status[0x8]; 6703 u8 reserved_at_8[0x18]; 6704 6705 u8 syndrome[0x20]; 6706 6707 u8 reserved_at_40[0x18]; 6708 u8 eq_number[0x8]; 6709 6710 u8 reserved_at_60[0x20]; 6711 }; 6712 6713 struct mlx5_ifc_create_eq_in_bits { 6714 u8 opcode[0x10]; 6715 u8 reserved_at_10[0x10]; 6716 6717 u8 reserved_at_20[0x10]; 6718 u8 op_mod[0x10]; 6719 6720 u8 reserved_at_40[0x40]; 6721 6722 struct mlx5_ifc_eqc_bits eq_context_entry; 6723 6724 u8 reserved_at_280[0x40]; 6725 6726 u8 event_bitmask[0x40]; 6727 6728 u8 reserved_at_300[0x580]; 6729 6730 u8 pas[0][0x40]; 6731 }; 6732 6733 struct mlx5_ifc_create_dct_out_bits { 6734 u8 status[0x8]; 6735 u8 reserved_at_8[0x18]; 6736 6737 u8 syndrome[0x20]; 6738 6739 u8 reserved_at_40[0x8]; 6740 u8 dctn[0x18]; 6741 6742 u8 reserved_at_60[0x20]; 6743 }; 6744 6745 struct mlx5_ifc_create_dct_in_bits { 6746 u8 opcode[0x10]; 6747 u8 reserved_at_10[0x10]; 6748 6749 u8 reserved_at_20[0x10]; 6750 u8 op_mod[0x10]; 6751 6752 u8 reserved_at_40[0x40]; 6753 6754 struct mlx5_ifc_dctc_bits dct_context_entry; 6755 6756 u8 reserved_at_280[0x180]; 6757 }; 6758 6759 struct mlx5_ifc_create_cq_out_bits { 6760 u8 status[0x8]; 6761 u8 reserved_at_8[0x18]; 6762 6763 u8 syndrome[0x20]; 6764 6765 u8 reserved_at_40[0x8]; 6766 u8 cqn[0x18]; 6767 6768 u8 reserved_at_60[0x20]; 6769 }; 6770 6771 struct mlx5_ifc_create_cq_in_bits { 6772 u8 opcode[0x10]; 6773 u8 reserved_at_10[0x10]; 6774 6775 u8 reserved_at_20[0x10]; 6776 u8 op_mod[0x10]; 6777 6778 u8 reserved_at_40[0x40]; 6779 6780 struct mlx5_ifc_cqc_bits cq_context; 6781 6782 u8 reserved_at_280[0x600]; 6783 6784 u8 pas[0][0x40]; 6785 }; 6786 6787 struct mlx5_ifc_config_int_moderation_out_bits { 6788 u8 status[0x8]; 6789 u8 reserved_at_8[0x18]; 6790 6791 u8 syndrome[0x20]; 6792 6793 u8 reserved_at_40[0x4]; 6794 u8 min_delay[0xc]; 6795 u8 int_vector[0x10]; 6796 6797 u8 reserved_at_60[0x20]; 6798 }; 6799 6800 enum { 6801 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6802 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6803 }; 6804 6805 struct mlx5_ifc_config_int_moderation_in_bits { 6806 u8 opcode[0x10]; 6807 u8 reserved_at_10[0x10]; 6808 6809 u8 reserved_at_20[0x10]; 6810 u8 op_mod[0x10]; 6811 6812 u8 reserved_at_40[0x4]; 6813 u8 min_delay[0xc]; 6814 u8 int_vector[0x10]; 6815 6816 u8 reserved_at_60[0x20]; 6817 }; 6818 6819 struct mlx5_ifc_attach_to_mcg_out_bits { 6820 u8 status[0x8]; 6821 u8 reserved_at_8[0x18]; 6822 6823 u8 syndrome[0x20]; 6824 6825 u8 reserved_at_40[0x40]; 6826 }; 6827 6828 struct mlx5_ifc_attach_to_mcg_in_bits { 6829 u8 opcode[0x10]; 6830 u8 reserved_at_10[0x10]; 6831 6832 u8 reserved_at_20[0x10]; 6833 u8 op_mod[0x10]; 6834 6835 u8 reserved_at_40[0x8]; 6836 u8 qpn[0x18]; 6837 6838 u8 reserved_at_60[0x20]; 6839 6840 u8 multicast_gid[16][0x8]; 6841 }; 6842 6843 struct mlx5_ifc_arm_xrq_out_bits { 6844 u8 status[0x8]; 6845 u8 reserved_at_8[0x18]; 6846 6847 u8 syndrome[0x20]; 6848 6849 u8 reserved_at_40[0x40]; 6850 }; 6851 6852 struct mlx5_ifc_arm_xrq_in_bits { 6853 u8 opcode[0x10]; 6854 u8 reserved_at_10[0x10]; 6855 6856 u8 reserved_at_20[0x10]; 6857 u8 op_mod[0x10]; 6858 6859 u8 reserved_at_40[0x8]; 6860 u8 xrqn[0x18]; 6861 6862 u8 reserved_at_60[0x10]; 6863 u8 lwm[0x10]; 6864 }; 6865 6866 struct mlx5_ifc_arm_xrc_srq_out_bits { 6867 u8 status[0x8]; 6868 u8 reserved_at_8[0x18]; 6869 6870 u8 syndrome[0x20]; 6871 6872 u8 reserved_at_40[0x40]; 6873 }; 6874 6875 enum { 6876 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 6877 }; 6878 6879 struct mlx5_ifc_arm_xrc_srq_in_bits { 6880 u8 opcode[0x10]; 6881 u8 reserved_at_10[0x10]; 6882 6883 u8 reserved_at_20[0x10]; 6884 u8 op_mod[0x10]; 6885 6886 u8 reserved_at_40[0x8]; 6887 u8 xrc_srqn[0x18]; 6888 6889 u8 reserved_at_60[0x10]; 6890 u8 lwm[0x10]; 6891 }; 6892 6893 struct mlx5_ifc_arm_rq_out_bits { 6894 u8 status[0x8]; 6895 u8 reserved_at_8[0x18]; 6896 6897 u8 syndrome[0x20]; 6898 6899 u8 reserved_at_40[0x40]; 6900 }; 6901 6902 enum { 6903 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 6904 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 6905 }; 6906 6907 struct mlx5_ifc_arm_rq_in_bits { 6908 u8 opcode[0x10]; 6909 u8 reserved_at_10[0x10]; 6910 6911 u8 reserved_at_20[0x10]; 6912 u8 op_mod[0x10]; 6913 6914 u8 reserved_at_40[0x8]; 6915 u8 srq_number[0x18]; 6916 6917 u8 reserved_at_60[0x10]; 6918 u8 lwm[0x10]; 6919 }; 6920 6921 struct mlx5_ifc_arm_dct_out_bits { 6922 u8 status[0x8]; 6923 u8 reserved_at_8[0x18]; 6924 6925 u8 syndrome[0x20]; 6926 6927 u8 reserved_at_40[0x40]; 6928 }; 6929 6930 struct mlx5_ifc_arm_dct_in_bits { 6931 u8 opcode[0x10]; 6932 u8 reserved_at_10[0x10]; 6933 6934 u8 reserved_at_20[0x10]; 6935 u8 op_mod[0x10]; 6936 6937 u8 reserved_at_40[0x8]; 6938 u8 dct_number[0x18]; 6939 6940 u8 reserved_at_60[0x20]; 6941 }; 6942 6943 struct mlx5_ifc_alloc_xrcd_out_bits { 6944 u8 status[0x8]; 6945 u8 reserved_at_8[0x18]; 6946 6947 u8 syndrome[0x20]; 6948 6949 u8 reserved_at_40[0x8]; 6950 u8 xrcd[0x18]; 6951 6952 u8 reserved_at_60[0x20]; 6953 }; 6954 6955 struct mlx5_ifc_alloc_xrcd_in_bits { 6956 u8 opcode[0x10]; 6957 u8 reserved_at_10[0x10]; 6958 6959 u8 reserved_at_20[0x10]; 6960 u8 op_mod[0x10]; 6961 6962 u8 reserved_at_40[0x40]; 6963 }; 6964 6965 struct mlx5_ifc_alloc_uar_out_bits { 6966 u8 status[0x8]; 6967 u8 reserved_at_8[0x18]; 6968 6969 u8 syndrome[0x20]; 6970 6971 u8 reserved_at_40[0x8]; 6972 u8 uar[0x18]; 6973 6974 u8 reserved_at_60[0x20]; 6975 }; 6976 6977 struct mlx5_ifc_alloc_uar_in_bits { 6978 u8 opcode[0x10]; 6979 u8 reserved_at_10[0x10]; 6980 6981 u8 reserved_at_20[0x10]; 6982 u8 op_mod[0x10]; 6983 6984 u8 reserved_at_40[0x40]; 6985 }; 6986 6987 struct mlx5_ifc_alloc_transport_domain_out_bits { 6988 u8 status[0x8]; 6989 u8 reserved_at_8[0x18]; 6990 6991 u8 syndrome[0x20]; 6992 6993 u8 reserved_at_40[0x8]; 6994 u8 transport_domain[0x18]; 6995 6996 u8 reserved_at_60[0x20]; 6997 }; 6998 6999 struct mlx5_ifc_alloc_transport_domain_in_bits { 7000 u8 opcode[0x10]; 7001 u8 reserved_at_10[0x10]; 7002 7003 u8 reserved_at_20[0x10]; 7004 u8 op_mod[0x10]; 7005 7006 u8 reserved_at_40[0x40]; 7007 }; 7008 7009 struct mlx5_ifc_alloc_q_counter_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x18]; 7016 u8 counter_set_id[0x8]; 7017 7018 u8 reserved_at_60[0x20]; 7019 }; 7020 7021 struct mlx5_ifc_alloc_q_counter_in_bits { 7022 u8 opcode[0x10]; 7023 u8 reserved_at_10[0x10]; 7024 7025 u8 reserved_at_20[0x10]; 7026 u8 op_mod[0x10]; 7027 7028 u8 reserved_at_40[0x40]; 7029 }; 7030 7031 struct mlx5_ifc_alloc_pd_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x8]; 7038 u8 pd[0x18]; 7039 7040 u8 reserved_at_60[0x20]; 7041 }; 7042 7043 struct mlx5_ifc_alloc_pd_in_bits { 7044 u8 opcode[0x10]; 7045 u8 reserved_at_10[0x10]; 7046 7047 u8 reserved_at_20[0x10]; 7048 u8 op_mod[0x10]; 7049 7050 u8 reserved_at_40[0x40]; 7051 }; 7052 7053 struct mlx5_ifc_alloc_flow_counter_out_bits { 7054 u8 status[0x8]; 7055 u8 reserved_at_8[0x18]; 7056 7057 u8 syndrome[0x20]; 7058 7059 u8 reserved_at_40[0x10]; 7060 u8 flow_counter_id[0x10]; 7061 7062 u8 reserved_at_60[0x20]; 7063 }; 7064 7065 struct mlx5_ifc_alloc_flow_counter_in_bits { 7066 u8 opcode[0x10]; 7067 u8 reserved_at_10[0x10]; 7068 7069 u8 reserved_at_20[0x10]; 7070 u8 op_mod[0x10]; 7071 7072 u8 reserved_at_40[0x40]; 7073 }; 7074 7075 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7076 u8 status[0x8]; 7077 u8 reserved_at_8[0x18]; 7078 7079 u8 syndrome[0x20]; 7080 7081 u8 reserved_at_40[0x40]; 7082 }; 7083 7084 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7085 u8 opcode[0x10]; 7086 u8 reserved_at_10[0x10]; 7087 7088 u8 reserved_at_20[0x10]; 7089 u8 op_mod[0x10]; 7090 7091 u8 reserved_at_40[0x20]; 7092 7093 u8 reserved_at_60[0x10]; 7094 u8 vxlan_udp_port[0x10]; 7095 }; 7096 7097 struct mlx5_ifc_set_rate_limit_out_bits { 7098 u8 status[0x8]; 7099 u8 reserved_at_8[0x18]; 7100 7101 u8 syndrome[0x20]; 7102 7103 u8 reserved_at_40[0x40]; 7104 }; 7105 7106 struct mlx5_ifc_set_rate_limit_in_bits { 7107 u8 opcode[0x10]; 7108 u8 reserved_at_10[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0x10]; 7114 u8 rate_limit_index[0x10]; 7115 7116 u8 reserved_at_60[0x20]; 7117 7118 u8 rate_limit[0x20]; 7119 }; 7120 7121 struct mlx5_ifc_access_register_out_bits { 7122 u8 status[0x8]; 7123 u8 reserved_at_8[0x18]; 7124 7125 u8 syndrome[0x20]; 7126 7127 u8 reserved_at_40[0x40]; 7128 7129 u8 register_data[0][0x20]; 7130 }; 7131 7132 enum { 7133 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7134 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7135 }; 7136 7137 struct mlx5_ifc_access_register_in_bits { 7138 u8 opcode[0x10]; 7139 u8 reserved_at_10[0x10]; 7140 7141 u8 reserved_at_20[0x10]; 7142 u8 op_mod[0x10]; 7143 7144 u8 reserved_at_40[0x10]; 7145 u8 register_id[0x10]; 7146 7147 u8 argument[0x20]; 7148 7149 u8 register_data[0][0x20]; 7150 }; 7151 7152 struct mlx5_ifc_sltp_reg_bits { 7153 u8 status[0x4]; 7154 u8 version[0x4]; 7155 u8 local_port[0x8]; 7156 u8 pnat[0x2]; 7157 u8 reserved_at_12[0x2]; 7158 u8 lane[0x4]; 7159 u8 reserved_at_18[0x8]; 7160 7161 u8 reserved_at_20[0x20]; 7162 7163 u8 reserved_at_40[0x7]; 7164 u8 polarity[0x1]; 7165 u8 ob_tap0[0x8]; 7166 u8 ob_tap1[0x8]; 7167 u8 ob_tap2[0x8]; 7168 7169 u8 reserved_at_60[0xc]; 7170 u8 ob_preemp_mode[0x4]; 7171 u8 ob_reg[0x8]; 7172 u8 ob_bias[0x8]; 7173 7174 u8 reserved_at_80[0x20]; 7175 }; 7176 7177 struct mlx5_ifc_slrg_reg_bits { 7178 u8 status[0x4]; 7179 u8 version[0x4]; 7180 u8 local_port[0x8]; 7181 u8 pnat[0x2]; 7182 u8 reserved_at_12[0x2]; 7183 u8 lane[0x4]; 7184 u8 reserved_at_18[0x8]; 7185 7186 u8 time_to_link_up[0x10]; 7187 u8 reserved_at_30[0xc]; 7188 u8 grade_lane_speed[0x4]; 7189 7190 u8 grade_version[0x8]; 7191 u8 grade[0x18]; 7192 7193 u8 reserved_at_60[0x4]; 7194 u8 height_grade_type[0x4]; 7195 u8 height_grade[0x18]; 7196 7197 u8 height_dz[0x10]; 7198 u8 height_dv[0x10]; 7199 7200 u8 reserved_at_a0[0x10]; 7201 u8 height_sigma[0x10]; 7202 7203 u8 reserved_at_c0[0x20]; 7204 7205 u8 reserved_at_e0[0x4]; 7206 u8 phase_grade_type[0x4]; 7207 u8 phase_grade[0x18]; 7208 7209 u8 reserved_at_100[0x8]; 7210 u8 phase_eo_pos[0x8]; 7211 u8 reserved_at_110[0x8]; 7212 u8 phase_eo_neg[0x8]; 7213 7214 u8 ffe_set_tested[0x10]; 7215 u8 test_errors_per_lane[0x10]; 7216 }; 7217 7218 struct mlx5_ifc_pvlc_reg_bits { 7219 u8 reserved_at_0[0x8]; 7220 u8 local_port[0x8]; 7221 u8 reserved_at_10[0x10]; 7222 7223 u8 reserved_at_20[0x1c]; 7224 u8 vl_hw_cap[0x4]; 7225 7226 u8 reserved_at_40[0x1c]; 7227 u8 vl_admin[0x4]; 7228 7229 u8 reserved_at_60[0x1c]; 7230 u8 vl_operational[0x4]; 7231 }; 7232 7233 struct mlx5_ifc_pude_reg_bits { 7234 u8 swid[0x8]; 7235 u8 local_port[0x8]; 7236 u8 reserved_at_10[0x4]; 7237 u8 admin_status[0x4]; 7238 u8 reserved_at_18[0x4]; 7239 u8 oper_status[0x4]; 7240 7241 u8 reserved_at_20[0x60]; 7242 }; 7243 7244 struct mlx5_ifc_ptys_reg_bits { 7245 u8 reserved_at_0[0x1]; 7246 u8 an_disable_admin[0x1]; 7247 u8 an_disable_cap[0x1]; 7248 u8 reserved_at_3[0x5]; 7249 u8 local_port[0x8]; 7250 u8 reserved_at_10[0xd]; 7251 u8 proto_mask[0x3]; 7252 7253 u8 an_status[0x4]; 7254 u8 reserved_at_24[0x3c]; 7255 7256 u8 eth_proto_capability[0x20]; 7257 7258 u8 ib_link_width_capability[0x10]; 7259 u8 ib_proto_capability[0x10]; 7260 7261 u8 reserved_at_a0[0x20]; 7262 7263 u8 eth_proto_admin[0x20]; 7264 7265 u8 ib_link_width_admin[0x10]; 7266 u8 ib_proto_admin[0x10]; 7267 7268 u8 reserved_at_100[0x20]; 7269 7270 u8 eth_proto_oper[0x20]; 7271 7272 u8 ib_link_width_oper[0x10]; 7273 u8 ib_proto_oper[0x10]; 7274 7275 u8 reserved_at_160[0x20]; 7276 7277 u8 eth_proto_lp_advertise[0x20]; 7278 7279 u8 reserved_at_1a0[0x60]; 7280 }; 7281 7282 struct mlx5_ifc_mlcr_reg_bits { 7283 u8 reserved_at_0[0x8]; 7284 u8 local_port[0x8]; 7285 u8 reserved_at_10[0x20]; 7286 7287 u8 beacon_duration[0x10]; 7288 u8 reserved_at_40[0x10]; 7289 7290 u8 beacon_remain[0x10]; 7291 }; 7292 7293 struct mlx5_ifc_ptas_reg_bits { 7294 u8 reserved_at_0[0x20]; 7295 7296 u8 algorithm_options[0x10]; 7297 u8 reserved_at_30[0x4]; 7298 u8 repetitions_mode[0x4]; 7299 u8 num_of_repetitions[0x8]; 7300 7301 u8 grade_version[0x8]; 7302 u8 height_grade_type[0x4]; 7303 u8 phase_grade_type[0x4]; 7304 u8 height_grade_weight[0x8]; 7305 u8 phase_grade_weight[0x8]; 7306 7307 u8 gisim_measure_bits[0x10]; 7308 u8 adaptive_tap_measure_bits[0x10]; 7309 7310 u8 ber_bath_high_error_threshold[0x10]; 7311 u8 ber_bath_mid_error_threshold[0x10]; 7312 7313 u8 ber_bath_low_error_threshold[0x10]; 7314 u8 one_ratio_high_threshold[0x10]; 7315 7316 u8 one_ratio_high_mid_threshold[0x10]; 7317 u8 one_ratio_low_mid_threshold[0x10]; 7318 7319 u8 one_ratio_low_threshold[0x10]; 7320 u8 ndeo_error_threshold[0x10]; 7321 7322 u8 mixer_offset_step_size[0x10]; 7323 u8 reserved_at_110[0x8]; 7324 u8 mix90_phase_for_voltage_bath[0x8]; 7325 7326 u8 mixer_offset_start[0x10]; 7327 u8 mixer_offset_end[0x10]; 7328 7329 u8 reserved_at_140[0x15]; 7330 u8 ber_test_time[0xb]; 7331 }; 7332 7333 struct mlx5_ifc_pspa_reg_bits { 7334 u8 swid[0x8]; 7335 u8 local_port[0x8]; 7336 u8 sub_port[0x8]; 7337 u8 reserved_at_18[0x8]; 7338 7339 u8 reserved_at_20[0x20]; 7340 }; 7341 7342 struct mlx5_ifc_pqdr_reg_bits { 7343 u8 reserved_at_0[0x8]; 7344 u8 local_port[0x8]; 7345 u8 reserved_at_10[0x5]; 7346 u8 prio[0x3]; 7347 u8 reserved_at_18[0x6]; 7348 u8 mode[0x2]; 7349 7350 u8 reserved_at_20[0x20]; 7351 7352 u8 reserved_at_40[0x10]; 7353 u8 min_threshold[0x10]; 7354 7355 u8 reserved_at_60[0x10]; 7356 u8 max_threshold[0x10]; 7357 7358 u8 reserved_at_80[0x10]; 7359 u8 mark_probability_denominator[0x10]; 7360 7361 u8 reserved_at_a0[0x60]; 7362 }; 7363 7364 struct mlx5_ifc_ppsc_reg_bits { 7365 u8 reserved_at_0[0x8]; 7366 u8 local_port[0x8]; 7367 u8 reserved_at_10[0x10]; 7368 7369 u8 reserved_at_20[0x60]; 7370 7371 u8 reserved_at_80[0x1c]; 7372 u8 wrps_admin[0x4]; 7373 7374 u8 reserved_at_a0[0x1c]; 7375 u8 wrps_status[0x4]; 7376 7377 u8 reserved_at_c0[0x8]; 7378 u8 up_threshold[0x8]; 7379 u8 reserved_at_d0[0x8]; 7380 u8 down_threshold[0x8]; 7381 7382 u8 reserved_at_e0[0x20]; 7383 7384 u8 reserved_at_100[0x1c]; 7385 u8 srps_admin[0x4]; 7386 7387 u8 reserved_at_120[0x1c]; 7388 u8 srps_status[0x4]; 7389 7390 u8 reserved_at_140[0x40]; 7391 }; 7392 7393 struct mlx5_ifc_pplr_reg_bits { 7394 u8 reserved_at_0[0x8]; 7395 u8 local_port[0x8]; 7396 u8 reserved_at_10[0x10]; 7397 7398 u8 reserved_at_20[0x8]; 7399 u8 lb_cap[0x8]; 7400 u8 reserved_at_30[0x8]; 7401 u8 lb_en[0x8]; 7402 }; 7403 7404 struct mlx5_ifc_pplm_reg_bits { 7405 u8 reserved_at_0[0x8]; 7406 u8 local_port[0x8]; 7407 u8 reserved_at_10[0x10]; 7408 7409 u8 reserved_at_20[0x20]; 7410 7411 u8 port_profile_mode[0x8]; 7412 u8 static_port_profile[0x8]; 7413 u8 active_port_profile[0x8]; 7414 u8 reserved_at_58[0x8]; 7415 7416 u8 retransmission_active[0x8]; 7417 u8 fec_mode_active[0x18]; 7418 7419 u8 reserved_at_80[0x20]; 7420 }; 7421 7422 struct mlx5_ifc_ppcnt_reg_bits { 7423 u8 swid[0x8]; 7424 u8 local_port[0x8]; 7425 u8 pnat[0x2]; 7426 u8 reserved_at_12[0x8]; 7427 u8 grp[0x6]; 7428 7429 u8 clr[0x1]; 7430 u8 reserved_at_21[0x1c]; 7431 u8 prio_tc[0x3]; 7432 7433 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7434 }; 7435 7436 struct mlx5_ifc_mpcnt_reg_bits { 7437 u8 reserved_at_0[0x8]; 7438 u8 pcie_index[0x8]; 7439 u8 reserved_at_10[0xa]; 7440 u8 grp[0x6]; 7441 7442 u8 clr[0x1]; 7443 u8 reserved_at_21[0x1f]; 7444 7445 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7446 }; 7447 7448 struct mlx5_ifc_ppad_reg_bits { 7449 u8 reserved_at_0[0x3]; 7450 u8 single_mac[0x1]; 7451 u8 reserved_at_4[0x4]; 7452 u8 local_port[0x8]; 7453 u8 mac_47_32[0x10]; 7454 7455 u8 mac_31_0[0x20]; 7456 7457 u8 reserved_at_40[0x40]; 7458 }; 7459 7460 struct mlx5_ifc_pmtu_reg_bits { 7461 u8 reserved_at_0[0x8]; 7462 u8 local_port[0x8]; 7463 u8 reserved_at_10[0x10]; 7464 7465 u8 max_mtu[0x10]; 7466 u8 reserved_at_30[0x10]; 7467 7468 u8 admin_mtu[0x10]; 7469 u8 reserved_at_50[0x10]; 7470 7471 u8 oper_mtu[0x10]; 7472 u8 reserved_at_70[0x10]; 7473 }; 7474 7475 struct mlx5_ifc_pmpr_reg_bits { 7476 u8 reserved_at_0[0x8]; 7477 u8 module[0x8]; 7478 u8 reserved_at_10[0x10]; 7479 7480 u8 reserved_at_20[0x18]; 7481 u8 attenuation_5g[0x8]; 7482 7483 u8 reserved_at_40[0x18]; 7484 u8 attenuation_7g[0x8]; 7485 7486 u8 reserved_at_60[0x18]; 7487 u8 attenuation_12g[0x8]; 7488 }; 7489 7490 struct mlx5_ifc_pmpe_reg_bits { 7491 u8 reserved_at_0[0x8]; 7492 u8 module[0x8]; 7493 u8 reserved_at_10[0xc]; 7494 u8 module_status[0x4]; 7495 7496 u8 reserved_at_20[0x60]; 7497 }; 7498 7499 struct mlx5_ifc_pmpc_reg_bits { 7500 u8 module_state_updated[32][0x8]; 7501 }; 7502 7503 struct mlx5_ifc_pmlpn_reg_bits { 7504 u8 reserved_at_0[0x4]; 7505 u8 mlpn_status[0x4]; 7506 u8 local_port[0x8]; 7507 u8 reserved_at_10[0x10]; 7508 7509 u8 e[0x1]; 7510 u8 reserved_at_21[0x1f]; 7511 }; 7512 7513 struct mlx5_ifc_pmlp_reg_bits { 7514 u8 rxtx[0x1]; 7515 u8 reserved_at_1[0x7]; 7516 u8 local_port[0x8]; 7517 u8 reserved_at_10[0x8]; 7518 u8 width[0x8]; 7519 7520 u8 lane0_module_mapping[0x20]; 7521 7522 u8 lane1_module_mapping[0x20]; 7523 7524 u8 lane2_module_mapping[0x20]; 7525 7526 u8 lane3_module_mapping[0x20]; 7527 7528 u8 reserved_at_a0[0x160]; 7529 }; 7530 7531 struct mlx5_ifc_pmaos_reg_bits { 7532 u8 reserved_at_0[0x8]; 7533 u8 module[0x8]; 7534 u8 reserved_at_10[0x4]; 7535 u8 admin_status[0x4]; 7536 u8 reserved_at_18[0x4]; 7537 u8 oper_status[0x4]; 7538 7539 u8 ase[0x1]; 7540 u8 ee[0x1]; 7541 u8 reserved_at_22[0x1c]; 7542 u8 e[0x2]; 7543 7544 u8 reserved_at_40[0x40]; 7545 }; 7546 7547 struct mlx5_ifc_plpc_reg_bits { 7548 u8 reserved_at_0[0x4]; 7549 u8 profile_id[0xc]; 7550 u8 reserved_at_10[0x4]; 7551 u8 proto_mask[0x4]; 7552 u8 reserved_at_18[0x8]; 7553 7554 u8 reserved_at_20[0x10]; 7555 u8 lane_speed[0x10]; 7556 7557 u8 reserved_at_40[0x17]; 7558 u8 lpbf[0x1]; 7559 u8 fec_mode_policy[0x8]; 7560 7561 u8 retransmission_capability[0x8]; 7562 u8 fec_mode_capability[0x18]; 7563 7564 u8 retransmission_support_admin[0x8]; 7565 u8 fec_mode_support_admin[0x18]; 7566 7567 u8 retransmission_request_admin[0x8]; 7568 u8 fec_mode_request_admin[0x18]; 7569 7570 u8 reserved_at_c0[0x80]; 7571 }; 7572 7573 struct mlx5_ifc_plib_reg_bits { 7574 u8 reserved_at_0[0x8]; 7575 u8 local_port[0x8]; 7576 u8 reserved_at_10[0x8]; 7577 u8 ib_port[0x8]; 7578 7579 u8 reserved_at_20[0x60]; 7580 }; 7581 7582 struct mlx5_ifc_plbf_reg_bits { 7583 u8 reserved_at_0[0x8]; 7584 u8 local_port[0x8]; 7585 u8 reserved_at_10[0xd]; 7586 u8 lbf_mode[0x3]; 7587 7588 u8 reserved_at_20[0x20]; 7589 }; 7590 7591 struct mlx5_ifc_pipg_reg_bits { 7592 u8 reserved_at_0[0x8]; 7593 u8 local_port[0x8]; 7594 u8 reserved_at_10[0x10]; 7595 7596 u8 dic[0x1]; 7597 u8 reserved_at_21[0x19]; 7598 u8 ipg[0x4]; 7599 u8 reserved_at_3e[0x2]; 7600 }; 7601 7602 struct mlx5_ifc_pifr_reg_bits { 7603 u8 reserved_at_0[0x8]; 7604 u8 local_port[0x8]; 7605 u8 reserved_at_10[0x10]; 7606 7607 u8 reserved_at_20[0xe0]; 7608 7609 u8 port_filter[8][0x20]; 7610 7611 u8 port_filter_update_en[8][0x20]; 7612 }; 7613 7614 struct mlx5_ifc_pfcc_reg_bits { 7615 u8 reserved_at_0[0x8]; 7616 u8 local_port[0x8]; 7617 u8 reserved_at_10[0x10]; 7618 7619 u8 ppan[0x4]; 7620 u8 reserved_at_24[0x4]; 7621 u8 prio_mask_tx[0x8]; 7622 u8 reserved_at_30[0x8]; 7623 u8 prio_mask_rx[0x8]; 7624 7625 u8 pptx[0x1]; 7626 u8 aptx[0x1]; 7627 u8 reserved_at_42[0x6]; 7628 u8 pfctx[0x8]; 7629 u8 reserved_at_50[0x10]; 7630 7631 u8 pprx[0x1]; 7632 u8 aprx[0x1]; 7633 u8 reserved_at_62[0x6]; 7634 u8 pfcrx[0x8]; 7635 u8 reserved_at_70[0x10]; 7636 7637 u8 reserved_at_80[0x80]; 7638 }; 7639 7640 struct mlx5_ifc_pelc_reg_bits { 7641 u8 op[0x4]; 7642 u8 reserved_at_4[0x4]; 7643 u8 local_port[0x8]; 7644 u8 reserved_at_10[0x10]; 7645 7646 u8 op_admin[0x8]; 7647 u8 op_capability[0x8]; 7648 u8 op_request[0x8]; 7649 u8 op_active[0x8]; 7650 7651 u8 admin[0x40]; 7652 7653 u8 capability[0x40]; 7654 7655 u8 request[0x40]; 7656 7657 u8 active[0x40]; 7658 7659 u8 reserved_at_140[0x80]; 7660 }; 7661 7662 struct mlx5_ifc_peir_reg_bits { 7663 u8 reserved_at_0[0x8]; 7664 u8 local_port[0x8]; 7665 u8 reserved_at_10[0x10]; 7666 7667 u8 reserved_at_20[0xc]; 7668 u8 error_count[0x4]; 7669 u8 reserved_at_30[0x10]; 7670 7671 u8 reserved_at_40[0xc]; 7672 u8 lane[0x4]; 7673 u8 reserved_at_50[0x8]; 7674 u8 error_type[0x8]; 7675 }; 7676 7677 struct mlx5_ifc_pcam_enhanced_features_bits { 7678 u8 reserved_at_0[0x7e]; 7679 7680 u8 ppcnt_discard_group[0x1]; 7681 u8 ppcnt_statistical_group[0x1]; 7682 }; 7683 7684 struct mlx5_ifc_pcam_reg_bits { 7685 u8 reserved_at_0[0x8]; 7686 u8 feature_group[0x8]; 7687 u8 reserved_at_10[0x8]; 7688 u8 access_reg_group[0x8]; 7689 7690 u8 reserved_at_20[0x20]; 7691 7692 union { 7693 u8 reserved_at_0[0x80]; 7694 } port_access_reg_cap_mask; 7695 7696 u8 reserved_at_c0[0x80]; 7697 7698 union { 7699 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 7700 u8 reserved_at_0[0x80]; 7701 } feature_cap_mask; 7702 7703 u8 reserved_at_1c0[0xc0]; 7704 }; 7705 7706 struct mlx5_ifc_mcam_enhanced_features_bits { 7707 u8 reserved_at_0[0x7f]; 7708 7709 u8 pcie_performance_group[0x1]; 7710 }; 7711 7712 struct mlx5_ifc_mcam_reg_bits { 7713 u8 reserved_at_0[0x8]; 7714 u8 feature_group[0x8]; 7715 u8 reserved_at_10[0x8]; 7716 u8 access_reg_group[0x8]; 7717 7718 u8 reserved_at_20[0x20]; 7719 7720 union { 7721 u8 reserved_at_0[0x80]; 7722 } mng_access_reg_cap_mask; 7723 7724 u8 reserved_at_c0[0x80]; 7725 7726 union { 7727 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 7728 u8 reserved_at_0[0x80]; 7729 } mng_feature_cap_mask; 7730 7731 u8 reserved_at_1c0[0x80]; 7732 }; 7733 7734 struct mlx5_ifc_pcap_reg_bits { 7735 u8 reserved_at_0[0x8]; 7736 u8 local_port[0x8]; 7737 u8 reserved_at_10[0x10]; 7738 7739 u8 port_capability_mask[4][0x20]; 7740 }; 7741 7742 struct mlx5_ifc_paos_reg_bits { 7743 u8 swid[0x8]; 7744 u8 local_port[0x8]; 7745 u8 reserved_at_10[0x4]; 7746 u8 admin_status[0x4]; 7747 u8 reserved_at_18[0x4]; 7748 u8 oper_status[0x4]; 7749 7750 u8 ase[0x1]; 7751 u8 ee[0x1]; 7752 u8 reserved_at_22[0x1c]; 7753 u8 e[0x2]; 7754 7755 u8 reserved_at_40[0x40]; 7756 }; 7757 7758 struct mlx5_ifc_pamp_reg_bits { 7759 u8 reserved_at_0[0x8]; 7760 u8 opamp_group[0x8]; 7761 u8 reserved_at_10[0xc]; 7762 u8 opamp_group_type[0x4]; 7763 7764 u8 start_index[0x10]; 7765 u8 reserved_at_30[0x4]; 7766 u8 num_of_indices[0xc]; 7767 7768 u8 index_data[18][0x10]; 7769 }; 7770 7771 struct mlx5_ifc_pcmr_reg_bits { 7772 u8 reserved_at_0[0x8]; 7773 u8 local_port[0x8]; 7774 u8 reserved_at_10[0x2e]; 7775 u8 fcs_cap[0x1]; 7776 u8 reserved_at_3f[0x1f]; 7777 u8 fcs_chk[0x1]; 7778 u8 reserved_at_5f[0x1]; 7779 }; 7780 7781 struct mlx5_ifc_lane_2_module_mapping_bits { 7782 u8 reserved_at_0[0x6]; 7783 u8 rx_lane[0x2]; 7784 u8 reserved_at_8[0x6]; 7785 u8 tx_lane[0x2]; 7786 u8 reserved_at_10[0x8]; 7787 u8 module[0x8]; 7788 }; 7789 7790 struct mlx5_ifc_bufferx_reg_bits { 7791 u8 reserved_at_0[0x6]; 7792 u8 lossy[0x1]; 7793 u8 epsb[0x1]; 7794 u8 reserved_at_8[0xc]; 7795 u8 size[0xc]; 7796 7797 u8 xoff_threshold[0x10]; 7798 u8 xon_threshold[0x10]; 7799 }; 7800 7801 struct mlx5_ifc_set_node_in_bits { 7802 u8 node_description[64][0x8]; 7803 }; 7804 7805 struct mlx5_ifc_register_power_settings_bits { 7806 u8 reserved_at_0[0x18]; 7807 u8 power_settings_level[0x8]; 7808 7809 u8 reserved_at_20[0x60]; 7810 }; 7811 7812 struct mlx5_ifc_register_host_endianness_bits { 7813 u8 he[0x1]; 7814 u8 reserved_at_1[0x1f]; 7815 7816 u8 reserved_at_20[0x60]; 7817 }; 7818 7819 struct mlx5_ifc_umr_pointer_desc_argument_bits { 7820 u8 reserved_at_0[0x20]; 7821 7822 u8 mkey[0x20]; 7823 7824 u8 addressh_63_32[0x20]; 7825 7826 u8 addressl_31_0[0x20]; 7827 }; 7828 7829 struct mlx5_ifc_ud_adrs_vector_bits { 7830 u8 dc_key[0x40]; 7831 7832 u8 ext[0x1]; 7833 u8 reserved_at_41[0x7]; 7834 u8 destination_qp_dct[0x18]; 7835 7836 u8 static_rate[0x4]; 7837 u8 sl_eth_prio[0x4]; 7838 u8 fl[0x1]; 7839 u8 mlid[0x7]; 7840 u8 rlid_udp_sport[0x10]; 7841 7842 u8 reserved_at_80[0x20]; 7843 7844 u8 rmac_47_16[0x20]; 7845 7846 u8 rmac_15_0[0x10]; 7847 u8 tclass[0x8]; 7848 u8 hop_limit[0x8]; 7849 7850 u8 reserved_at_e0[0x1]; 7851 u8 grh[0x1]; 7852 u8 reserved_at_e2[0x2]; 7853 u8 src_addr_index[0x8]; 7854 u8 flow_label[0x14]; 7855 7856 u8 rgid_rip[16][0x8]; 7857 }; 7858 7859 struct mlx5_ifc_pages_req_event_bits { 7860 u8 reserved_at_0[0x10]; 7861 u8 function_id[0x10]; 7862 7863 u8 num_pages[0x20]; 7864 7865 u8 reserved_at_40[0xa0]; 7866 }; 7867 7868 struct mlx5_ifc_eqe_bits { 7869 u8 reserved_at_0[0x8]; 7870 u8 event_type[0x8]; 7871 u8 reserved_at_10[0x8]; 7872 u8 event_sub_type[0x8]; 7873 7874 u8 reserved_at_20[0xe0]; 7875 7876 union mlx5_ifc_event_auto_bits event_data; 7877 7878 u8 reserved_at_1e0[0x10]; 7879 u8 signature[0x8]; 7880 u8 reserved_at_1f8[0x7]; 7881 u8 owner[0x1]; 7882 }; 7883 7884 enum { 7885 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 7886 }; 7887 7888 struct mlx5_ifc_cmd_queue_entry_bits { 7889 u8 type[0x8]; 7890 u8 reserved_at_8[0x18]; 7891 7892 u8 input_length[0x20]; 7893 7894 u8 input_mailbox_pointer_63_32[0x20]; 7895 7896 u8 input_mailbox_pointer_31_9[0x17]; 7897 u8 reserved_at_77[0x9]; 7898 7899 u8 command_input_inline_data[16][0x8]; 7900 7901 u8 command_output_inline_data[16][0x8]; 7902 7903 u8 output_mailbox_pointer_63_32[0x20]; 7904 7905 u8 output_mailbox_pointer_31_9[0x17]; 7906 u8 reserved_at_1b7[0x9]; 7907 7908 u8 output_length[0x20]; 7909 7910 u8 token[0x8]; 7911 u8 signature[0x8]; 7912 u8 reserved_at_1f0[0x8]; 7913 u8 status[0x7]; 7914 u8 ownership[0x1]; 7915 }; 7916 7917 struct mlx5_ifc_cmd_out_bits { 7918 u8 status[0x8]; 7919 u8 reserved_at_8[0x18]; 7920 7921 u8 syndrome[0x20]; 7922 7923 u8 command_output[0x20]; 7924 }; 7925 7926 struct mlx5_ifc_cmd_in_bits { 7927 u8 opcode[0x10]; 7928 u8 reserved_at_10[0x10]; 7929 7930 u8 reserved_at_20[0x10]; 7931 u8 op_mod[0x10]; 7932 7933 u8 command[0][0x20]; 7934 }; 7935 7936 struct mlx5_ifc_cmd_if_box_bits { 7937 u8 mailbox_data[512][0x8]; 7938 7939 u8 reserved_at_1000[0x180]; 7940 7941 u8 next_pointer_63_32[0x20]; 7942 7943 u8 next_pointer_31_10[0x16]; 7944 u8 reserved_at_11b6[0xa]; 7945 7946 u8 block_number[0x20]; 7947 7948 u8 reserved_at_11e0[0x8]; 7949 u8 token[0x8]; 7950 u8 ctrl_signature[0x8]; 7951 u8 signature[0x8]; 7952 }; 7953 7954 struct mlx5_ifc_mtt_bits { 7955 u8 ptag_63_32[0x20]; 7956 7957 u8 ptag_31_8[0x18]; 7958 u8 reserved_at_38[0x6]; 7959 u8 wr_en[0x1]; 7960 u8 rd_en[0x1]; 7961 }; 7962 7963 struct mlx5_ifc_query_wol_rol_out_bits { 7964 u8 status[0x8]; 7965 u8 reserved_at_8[0x18]; 7966 7967 u8 syndrome[0x20]; 7968 7969 u8 reserved_at_40[0x10]; 7970 u8 rol_mode[0x8]; 7971 u8 wol_mode[0x8]; 7972 7973 u8 reserved_at_60[0x20]; 7974 }; 7975 7976 struct mlx5_ifc_query_wol_rol_in_bits { 7977 u8 opcode[0x10]; 7978 u8 reserved_at_10[0x10]; 7979 7980 u8 reserved_at_20[0x10]; 7981 u8 op_mod[0x10]; 7982 7983 u8 reserved_at_40[0x40]; 7984 }; 7985 7986 struct mlx5_ifc_set_wol_rol_out_bits { 7987 u8 status[0x8]; 7988 u8 reserved_at_8[0x18]; 7989 7990 u8 syndrome[0x20]; 7991 7992 u8 reserved_at_40[0x40]; 7993 }; 7994 7995 struct mlx5_ifc_set_wol_rol_in_bits { 7996 u8 opcode[0x10]; 7997 u8 reserved_at_10[0x10]; 7998 7999 u8 reserved_at_20[0x10]; 8000 u8 op_mod[0x10]; 8001 8002 u8 rol_mode_valid[0x1]; 8003 u8 wol_mode_valid[0x1]; 8004 u8 reserved_at_42[0xe]; 8005 u8 rol_mode[0x8]; 8006 u8 wol_mode[0x8]; 8007 8008 u8 reserved_at_60[0x20]; 8009 }; 8010 8011 enum { 8012 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8013 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8014 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8015 }; 8016 8017 enum { 8018 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8019 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8020 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8021 }; 8022 8023 enum { 8024 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8025 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8026 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8027 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8028 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8029 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8030 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8031 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8032 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8034 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8035 }; 8036 8037 struct mlx5_ifc_initial_seg_bits { 8038 u8 fw_rev_minor[0x10]; 8039 u8 fw_rev_major[0x10]; 8040 8041 u8 cmd_interface_rev[0x10]; 8042 u8 fw_rev_subminor[0x10]; 8043 8044 u8 reserved_at_40[0x40]; 8045 8046 u8 cmdq_phy_addr_63_32[0x20]; 8047 8048 u8 cmdq_phy_addr_31_12[0x14]; 8049 u8 reserved_at_b4[0x2]; 8050 u8 nic_interface[0x2]; 8051 u8 log_cmdq_size[0x4]; 8052 u8 log_cmdq_stride[0x4]; 8053 8054 u8 command_doorbell_vector[0x20]; 8055 8056 u8 reserved_at_e0[0xf00]; 8057 8058 u8 initializing[0x1]; 8059 u8 reserved_at_fe1[0x4]; 8060 u8 nic_interface_supported[0x3]; 8061 u8 reserved_at_fe8[0x18]; 8062 8063 struct mlx5_ifc_health_buffer_bits health_buffer; 8064 8065 u8 no_dram_nic_offset[0x20]; 8066 8067 u8 reserved_at_1220[0x6e40]; 8068 8069 u8 reserved_at_8060[0x1f]; 8070 u8 clear_int[0x1]; 8071 8072 u8 health_syndrome[0x8]; 8073 u8 health_counter[0x18]; 8074 8075 u8 reserved_at_80a0[0x17fc0]; 8076 }; 8077 8078 struct mlx5_ifc_mtpps_reg_bits { 8079 u8 reserved_at_0[0xc]; 8080 u8 cap_number_of_pps_pins[0x4]; 8081 u8 reserved_at_10[0x4]; 8082 u8 cap_max_num_of_pps_in_pins[0x4]; 8083 u8 reserved_at_18[0x4]; 8084 u8 cap_max_num_of_pps_out_pins[0x4]; 8085 8086 u8 reserved_at_20[0x24]; 8087 u8 cap_pin_3_mode[0x4]; 8088 u8 reserved_at_48[0x4]; 8089 u8 cap_pin_2_mode[0x4]; 8090 u8 reserved_at_50[0x4]; 8091 u8 cap_pin_1_mode[0x4]; 8092 u8 reserved_at_58[0x4]; 8093 u8 cap_pin_0_mode[0x4]; 8094 8095 u8 reserved_at_60[0x4]; 8096 u8 cap_pin_7_mode[0x4]; 8097 u8 reserved_at_68[0x4]; 8098 u8 cap_pin_6_mode[0x4]; 8099 u8 reserved_at_70[0x4]; 8100 u8 cap_pin_5_mode[0x4]; 8101 u8 reserved_at_78[0x4]; 8102 u8 cap_pin_4_mode[0x4]; 8103 8104 u8 reserved_at_80[0x80]; 8105 8106 u8 enable[0x1]; 8107 u8 reserved_at_101[0xb]; 8108 u8 pattern[0x4]; 8109 u8 reserved_at_110[0x4]; 8110 u8 pin_mode[0x4]; 8111 u8 pin[0x8]; 8112 8113 u8 reserved_at_120[0x20]; 8114 8115 u8 time_stamp[0x40]; 8116 8117 u8 out_pulse_duration[0x10]; 8118 u8 out_periodic_adjustment[0x10]; 8119 8120 u8 reserved_at_1a0[0x60]; 8121 }; 8122 8123 struct mlx5_ifc_mtppse_reg_bits { 8124 u8 reserved_at_0[0x18]; 8125 u8 pin[0x8]; 8126 u8 event_arm[0x1]; 8127 u8 reserved_at_21[0x1b]; 8128 u8 event_generation_mode[0x4]; 8129 u8 reserved_at_40[0x40]; 8130 }; 8131 8132 union mlx5_ifc_ports_control_registers_document_bits { 8133 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8134 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8135 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8136 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8137 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8138 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8139 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8140 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8141 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8142 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8143 struct mlx5_ifc_paos_reg_bits paos_reg; 8144 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8145 struct mlx5_ifc_peir_reg_bits peir_reg; 8146 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8147 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8148 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8149 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8150 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8151 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8152 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8153 struct mlx5_ifc_plib_reg_bits plib_reg; 8154 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8155 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8156 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8157 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8158 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8159 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8160 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8161 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8162 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8163 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8164 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8165 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8166 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8167 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8168 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8169 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8170 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8171 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8172 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8173 struct mlx5_ifc_pude_reg_bits pude_reg; 8174 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8175 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8176 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8177 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8178 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8179 u8 reserved_at_0[0x60e0]; 8180 }; 8181 8182 union mlx5_ifc_debug_enhancements_document_bits { 8183 struct mlx5_ifc_health_buffer_bits health_buffer; 8184 u8 reserved_at_0[0x200]; 8185 }; 8186 8187 union mlx5_ifc_uplink_pci_interface_document_bits { 8188 struct mlx5_ifc_initial_seg_bits initial_seg; 8189 u8 reserved_at_0[0x20060]; 8190 }; 8191 8192 struct mlx5_ifc_set_flow_table_root_out_bits { 8193 u8 status[0x8]; 8194 u8 reserved_at_8[0x18]; 8195 8196 u8 syndrome[0x20]; 8197 8198 u8 reserved_at_40[0x40]; 8199 }; 8200 8201 struct mlx5_ifc_set_flow_table_root_in_bits { 8202 u8 opcode[0x10]; 8203 u8 reserved_at_10[0x10]; 8204 8205 u8 reserved_at_20[0x10]; 8206 u8 op_mod[0x10]; 8207 8208 u8 other_vport[0x1]; 8209 u8 reserved_at_41[0xf]; 8210 u8 vport_number[0x10]; 8211 8212 u8 reserved_at_60[0x20]; 8213 8214 u8 table_type[0x8]; 8215 u8 reserved_at_88[0x18]; 8216 8217 u8 reserved_at_a0[0x8]; 8218 u8 table_id[0x18]; 8219 8220 u8 reserved_at_c0[0x140]; 8221 }; 8222 8223 enum { 8224 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8225 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8226 }; 8227 8228 struct mlx5_ifc_modify_flow_table_out_bits { 8229 u8 status[0x8]; 8230 u8 reserved_at_8[0x18]; 8231 8232 u8 syndrome[0x20]; 8233 8234 u8 reserved_at_40[0x40]; 8235 }; 8236 8237 struct mlx5_ifc_modify_flow_table_in_bits { 8238 u8 opcode[0x10]; 8239 u8 reserved_at_10[0x10]; 8240 8241 u8 reserved_at_20[0x10]; 8242 u8 op_mod[0x10]; 8243 8244 u8 other_vport[0x1]; 8245 u8 reserved_at_41[0xf]; 8246 u8 vport_number[0x10]; 8247 8248 u8 reserved_at_60[0x10]; 8249 u8 modify_field_select[0x10]; 8250 8251 u8 table_type[0x8]; 8252 u8 reserved_at_88[0x18]; 8253 8254 u8 reserved_at_a0[0x8]; 8255 u8 table_id[0x18]; 8256 8257 u8 reserved_at_c0[0x4]; 8258 u8 table_miss_mode[0x4]; 8259 u8 reserved_at_c8[0x18]; 8260 8261 u8 reserved_at_e0[0x8]; 8262 u8 table_miss_id[0x18]; 8263 8264 u8 reserved_at_100[0x8]; 8265 u8 lag_master_next_table_id[0x18]; 8266 8267 u8 reserved_at_120[0x80]; 8268 }; 8269 8270 struct mlx5_ifc_ets_tcn_config_reg_bits { 8271 u8 g[0x1]; 8272 u8 b[0x1]; 8273 u8 r[0x1]; 8274 u8 reserved_at_3[0x9]; 8275 u8 group[0x4]; 8276 u8 reserved_at_10[0x9]; 8277 u8 bw_allocation[0x7]; 8278 8279 u8 reserved_at_20[0xc]; 8280 u8 max_bw_units[0x4]; 8281 u8 reserved_at_30[0x8]; 8282 u8 max_bw_value[0x8]; 8283 }; 8284 8285 struct mlx5_ifc_ets_global_config_reg_bits { 8286 u8 reserved_at_0[0x2]; 8287 u8 r[0x1]; 8288 u8 reserved_at_3[0x1d]; 8289 8290 u8 reserved_at_20[0xc]; 8291 u8 max_bw_units[0x4]; 8292 u8 reserved_at_30[0x8]; 8293 u8 max_bw_value[0x8]; 8294 }; 8295 8296 struct mlx5_ifc_qetc_reg_bits { 8297 u8 reserved_at_0[0x8]; 8298 u8 port_number[0x8]; 8299 u8 reserved_at_10[0x30]; 8300 8301 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8302 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8303 }; 8304 8305 struct mlx5_ifc_qtct_reg_bits { 8306 u8 reserved_at_0[0x8]; 8307 u8 port_number[0x8]; 8308 u8 reserved_at_10[0xd]; 8309 u8 prio[0x3]; 8310 8311 u8 reserved_at_20[0x1d]; 8312 u8 tclass[0x3]; 8313 }; 8314 8315 struct mlx5_ifc_mcia_reg_bits { 8316 u8 l[0x1]; 8317 u8 reserved_at_1[0x7]; 8318 u8 module[0x8]; 8319 u8 reserved_at_10[0x8]; 8320 u8 status[0x8]; 8321 8322 u8 i2c_device_address[0x8]; 8323 u8 page_number[0x8]; 8324 u8 device_address[0x10]; 8325 8326 u8 reserved_at_40[0x10]; 8327 u8 size[0x10]; 8328 8329 u8 reserved_at_60[0x20]; 8330 8331 u8 dword_0[0x20]; 8332 u8 dword_1[0x20]; 8333 u8 dword_2[0x20]; 8334 u8 dword_3[0x20]; 8335 u8 dword_4[0x20]; 8336 u8 dword_5[0x20]; 8337 u8 dword_6[0x20]; 8338 u8 dword_7[0x20]; 8339 u8 dword_8[0x20]; 8340 u8 dword_9[0x20]; 8341 u8 dword_10[0x20]; 8342 u8 dword_11[0x20]; 8343 }; 8344 8345 struct mlx5_ifc_dcbx_param_bits { 8346 u8 dcbx_cee_cap[0x1]; 8347 u8 dcbx_ieee_cap[0x1]; 8348 u8 dcbx_standby_cap[0x1]; 8349 u8 reserved_at_0[0x5]; 8350 u8 port_number[0x8]; 8351 u8 reserved_at_10[0xa]; 8352 u8 max_application_table_size[6]; 8353 u8 reserved_at_20[0x15]; 8354 u8 version_oper[0x3]; 8355 u8 reserved_at_38[5]; 8356 u8 version_admin[0x3]; 8357 u8 willing_admin[0x1]; 8358 u8 reserved_at_41[0x3]; 8359 u8 pfc_cap_oper[0x4]; 8360 u8 reserved_at_48[0x4]; 8361 u8 pfc_cap_admin[0x4]; 8362 u8 reserved_at_50[0x4]; 8363 u8 num_of_tc_oper[0x4]; 8364 u8 reserved_at_58[0x4]; 8365 u8 num_of_tc_admin[0x4]; 8366 u8 remote_willing[0x1]; 8367 u8 reserved_at_61[3]; 8368 u8 remote_pfc_cap[4]; 8369 u8 reserved_at_68[0x14]; 8370 u8 remote_num_of_tc[0x4]; 8371 u8 reserved_at_80[0x18]; 8372 u8 error[0x8]; 8373 u8 reserved_at_a0[0x160]; 8374 }; 8375 8376 struct mlx5_ifc_lagc_bits { 8377 u8 reserved_at_0[0x1d]; 8378 u8 lag_state[0x3]; 8379 8380 u8 reserved_at_20[0x14]; 8381 u8 tx_remap_affinity_2[0x4]; 8382 u8 reserved_at_38[0x4]; 8383 u8 tx_remap_affinity_1[0x4]; 8384 }; 8385 8386 struct mlx5_ifc_create_lag_out_bits { 8387 u8 status[0x8]; 8388 u8 reserved_at_8[0x18]; 8389 8390 u8 syndrome[0x20]; 8391 8392 u8 reserved_at_40[0x40]; 8393 }; 8394 8395 struct mlx5_ifc_create_lag_in_bits { 8396 u8 opcode[0x10]; 8397 u8 reserved_at_10[0x10]; 8398 8399 u8 reserved_at_20[0x10]; 8400 u8 op_mod[0x10]; 8401 8402 struct mlx5_ifc_lagc_bits ctx; 8403 }; 8404 8405 struct mlx5_ifc_modify_lag_out_bits { 8406 u8 status[0x8]; 8407 u8 reserved_at_8[0x18]; 8408 8409 u8 syndrome[0x20]; 8410 8411 u8 reserved_at_40[0x40]; 8412 }; 8413 8414 struct mlx5_ifc_modify_lag_in_bits { 8415 u8 opcode[0x10]; 8416 u8 reserved_at_10[0x10]; 8417 8418 u8 reserved_at_20[0x10]; 8419 u8 op_mod[0x10]; 8420 8421 u8 reserved_at_40[0x20]; 8422 u8 field_select[0x20]; 8423 8424 struct mlx5_ifc_lagc_bits ctx; 8425 }; 8426 8427 struct mlx5_ifc_query_lag_out_bits { 8428 u8 status[0x8]; 8429 u8 reserved_at_8[0x18]; 8430 8431 u8 syndrome[0x20]; 8432 8433 u8 reserved_at_40[0x40]; 8434 8435 struct mlx5_ifc_lagc_bits ctx; 8436 }; 8437 8438 struct mlx5_ifc_query_lag_in_bits { 8439 u8 opcode[0x10]; 8440 u8 reserved_at_10[0x10]; 8441 8442 u8 reserved_at_20[0x10]; 8443 u8 op_mod[0x10]; 8444 8445 u8 reserved_at_40[0x40]; 8446 }; 8447 8448 struct mlx5_ifc_destroy_lag_out_bits { 8449 u8 status[0x8]; 8450 u8 reserved_at_8[0x18]; 8451 8452 u8 syndrome[0x20]; 8453 8454 u8 reserved_at_40[0x40]; 8455 }; 8456 8457 struct mlx5_ifc_destroy_lag_in_bits { 8458 u8 opcode[0x10]; 8459 u8 reserved_at_10[0x10]; 8460 8461 u8 reserved_at_20[0x10]; 8462 u8 op_mod[0x10]; 8463 8464 u8 reserved_at_40[0x40]; 8465 }; 8466 8467 struct mlx5_ifc_create_vport_lag_out_bits { 8468 u8 status[0x8]; 8469 u8 reserved_at_8[0x18]; 8470 8471 u8 syndrome[0x20]; 8472 8473 u8 reserved_at_40[0x40]; 8474 }; 8475 8476 struct mlx5_ifc_create_vport_lag_in_bits { 8477 u8 opcode[0x10]; 8478 u8 reserved_at_10[0x10]; 8479 8480 u8 reserved_at_20[0x10]; 8481 u8 op_mod[0x10]; 8482 8483 u8 reserved_at_40[0x40]; 8484 }; 8485 8486 struct mlx5_ifc_destroy_vport_lag_out_bits { 8487 u8 status[0x8]; 8488 u8 reserved_at_8[0x18]; 8489 8490 u8 syndrome[0x20]; 8491 8492 u8 reserved_at_40[0x40]; 8493 }; 8494 8495 struct mlx5_ifc_destroy_vport_lag_in_bits { 8496 u8 opcode[0x10]; 8497 u8 reserved_at_10[0x10]; 8498 8499 u8 reserved_at_20[0x10]; 8500 u8 op_mod[0x10]; 8501 8502 u8 reserved_at_40[0x40]; 8503 }; 8504 8505 #endif /* MLX5_IFC_H */ 8506