1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4), 80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5), 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_UCTX = 0x0004, 85 MLX5_OBJ_TYPE_UMEM = 0x0005, 86 }; 87 88 enum { 89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 91 MLX5_CMD_OP_INIT_HCA = 0x102, 92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 93 MLX5_CMD_OP_ENABLE_HCA = 0x104, 94 MLX5_CMD_OP_DISABLE_HCA = 0x105, 95 MLX5_CMD_OP_QUERY_PAGES = 0x107, 96 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 97 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 98 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 99 MLX5_CMD_OP_SET_ISSI = 0x10b, 100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 108 MLX5_CMD_OP_CREATE_EQ = 0x301, 109 MLX5_CMD_OP_DESTROY_EQ = 0x302, 110 MLX5_CMD_OP_QUERY_EQ = 0x303, 111 MLX5_CMD_OP_GEN_EQE = 0x304, 112 MLX5_CMD_OP_CREATE_CQ = 0x400, 113 MLX5_CMD_OP_DESTROY_CQ = 0x401, 114 MLX5_CMD_OP_QUERY_CQ = 0x402, 115 MLX5_CMD_OP_MODIFY_CQ = 0x403, 116 MLX5_CMD_OP_CREATE_QP = 0x500, 117 MLX5_CMD_OP_DESTROY_QP = 0x501, 118 MLX5_CMD_OP_RST2INIT_QP = 0x502, 119 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 120 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 121 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 123 MLX5_CMD_OP_2ERR_QP = 0x507, 124 MLX5_CMD_OP_2RST_QP = 0x50a, 125 MLX5_CMD_OP_QUERY_QP = 0x50b, 126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 128 MLX5_CMD_OP_CREATE_PSV = 0x600, 129 MLX5_CMD_OP_DESTROY_PSV = 0x601, 130 MLX5_CMD_OP_CREATE_SRQ = 0x700, 131 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 132 MLX5_CMD_OP_QUERY_SRQ = 0x702, 133 MLX5_CMD_OP_ARM_RQ = 0x703, 134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 138 MLX5_CMD_OP_CREATE_DCT = 0x710, 139 MLX5_CMD_OP_DESTROY_DCT = 0x711, 140 MLX5_CMD_OP_DRAIN_DCT = 0x712, 141 MLX5_CMD_OP_QUERY_DCT = 0x713, 142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 143 MLX5_CMD_OP_CREATE_XRQ = 0x717, 144 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 145 MLX5_CMD_OP_QUERY_XRQ = 0x719, 146 MLX5_CMD_OP_ARM_XRQ = 0x71a, 147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 172 MLX5_CMD_OP_ALLOC_PD = 0x800, 173 MLX5_CMD_OP_DEALLOC_PD = 0x801, 174 MLX5_CMD_OP_ALLOC_UAR = 0x802, 175 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 177 MLX5_CMD_OP_ACCESS_REG = 0x805, 178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 181 MLX5_CMD_OP_MAD_IFC = 0x50d, 182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 184 MLX5_CMD_OP_NOP = 0x80d, 185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_CREATE_TIS = 0x912, 225 MLX5_CMD_OP_MODIFY_TIS = 0x913, 226 MLX5_CMD_OP_DESTROY_TIS = 0x914, 227 MLX5_CMD_OP_QUERY_TIS = 0x915, 228 MLX5_CMD_OP_CREATE_RQT = 0x916, 229 MLX5_CMD_OP_MODIFY_RQT = 0x917, 230 MLX5_CMD_OP_DESTROY_RQT = 0x918, 231 MLX5_CMD_OP_QUERY_RQT = 0x919, 232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 246 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 247 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 260 MLX5_CMD_OP_MAX 261 }; 262 263 struct mlx5_ifc_flow_table_fields_supported_bits { 264 u8 outer_dmac[0x1]; 265 u8 outer_smac[0x1]; 266 u8 outer_ether_type[0x1]; 267 u8 outer_ip_version[0x1]; 268 u8 outer_first_prio[0x1]; 269 u8 outer_first_cfi[0x1]; 270 u8 outer_first_vid[0x1]; 271 u8 outer_ipv4_ttl[0x1]; 272 u8 outer_second_prio[0x1]; 273 u8 outer_second_cfi[0x1]; 274 u8 outer_second_vid[0x1]; 275 u8 reserved_at_b[0x1]; 276 u8 outer_sip[0x1]; 277 u8 outer_dip[0x1]; 278 u8 outer_frag[0x1]; 279 u8 outer_ip_protocol[0x1]; 280 u8 outer_ip_ecn[0x1]; 281 u8 outer_ip_dscp[0x1]; 282 u8 outer_udp_sport[0x1]; 283 u8 outer_udp_dport[0x1]; 284 u8 outer_tcp_sport[0x1]; 285 u8 outer_tcp_dport[0x1]; 286 u8 outer_tcp_flags[0x1]; 287 u8 outer_gre_protocol[0x1]; 288 u8 outer_gre_key[0x1]; 289 u8 outer_vxlan_vni[0x1]; 290 u8 reserved_at_1a[0x5]; 291 u8 source_eswitch_port[0x1]; 292 293 u8 inner_dmac[0x1]; 294 u8 inner_smac[0x1]; 295 u8 inner_ether_type[0x1]; 296 u8 inner_ip_version[0x1]; 297 u8 inner_first_prio[0x1]; 298 u8 inner_first_cfi[0x1]; 299 u8 inner_first_vid[0x1]; 300 u8 reserved_at_27[0x1]; 301 u8 inner_second_prio[0x1]; 302 u8 inner_second_cfi[0x1]; 303 u8 inner_second_vid[0x1]; 304 u8 reserved_at_2b[0x1]; 305 u8 inner_sip[0x1]; 306 u8 inner_dip[0x1]; 307 u8 inner_frag[0x1]; 308 u8 inner_ip_protocol[0x1]; 309 u8 inner_ip_ecn[0x1]; 310 u8 inner_ip_dscp[0x1]; 311 u8 inner_udp_sport[0x1]; 312 u8 inner_udp_dport[0x1]; 313 u8 inner_tcp_sport[0x1]; 314 u8 inner_tcp_dport[0x1]; 315 u8 inner_tcp_flags[0x1]; 316 u8 reserved_at_37[0x9]; 317 318 u8 reserved_at_40[0x5]; 319 u8 outer_first_mpls_over_udp[0x4]; 320 u8 outer_first_mpls_over_gre[0x4]; 321 u8 inner_first_mpls[0x4]; 322 u8 outer_first_mpls[0x4]; 323 u8 reserved_at_55[0x2]; 324 u8 outer_esp_spi[0x1]; 325 u8 reserved_at_58[0x2]; 326 u8 bth_dst_qp[0x1]; 327 328 u8 reserved_at_5b[0x25]; 329 }; 330 331 struct mlx5_ifc_flow_table_prop_layout_bits { 332 u8 ft_support[0x1]; 333 u8 reserved_at_1[0x1]; 334 u8 flow_counter[0x1]; 335 u8 flow_modify_en[0x1]; 336 u8 modify_root[0x1]; 337 u8 identified_miss_table_mode[0x1]; 338 u8 flow_table_modify[0x1]; 339 u8 reformat[0x1]; 340 u8 decap[0x1]; 341 u8 reserved_at_9[0x1]; 342 u8 pop_vlan[0x1]; 343 u8 push_vlan[0x1]; 344 u8 reserved_at_c[0x1]; 345 u8 pop_vlan_2[0x1]; 346 u8 push_vlan_2[0x1]; 347 u8 reformat_and_vlan_action[0x1]; 348 u8 reserved_at_10[0x2]; 349 u8 reformat_l3_tunnel_to_l2[0x1]; 350 u8 reformat_l2_to_l3_tunnel[0x1]; 351 u8 reformat_and_modify_action[0x1]; 352 u8 reserved_at_14[0xb]; 353 u8 reserved_at_20[0x2]; 354 u8 log_max_ft_size[0x6]; 355 u8 log_max_modify_header_context[0x8]; 356 u8 max_modify_header_actions[0x8]; 357 u8 max_ft_level[0x8]; 358 359 u8 reserved_at_40[0x20]; 360 361 u8 reserved_at_60[0x18]; 362 u8 log_max_ft_num[0x8]; 363 364 u8 reserved_at_80[0x18]; 365 u8 log_max_destination[0x8]; 366 367 u8 log_max_flow_counter[0x8]; 368 u8 reserved_at_a8[0x10]; 369 u8 log_max_flow[0x8]; 370 371 u8 reserved_at_c0[0x40]; 372 373 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 374 375 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 376 }; 377 378 struct mlx5_ifc_odp_per_transport_service_cap_bits { 379 u8 send[0x1]; 380 u8 receive[0x1]; 381 u8 write[0x1]; 382 u8 read[0x1]; 383 u8 atomic[0x1]; 384 u8 srq_receive[0x1]; 385 u8 reserved_at_6[0x1a]; 386 }; 387 388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 389 u8 smac_47_16[0x20]; 390 391 u8 smac_15_0[0x10]; 392 u8 ethertype[0x10]; 393 394 u8 dmac_47_16[0x20]; 395 396 u8 dmac_15_0[0x10]; 397 u8 first_prio[0x3]; 398 u8 first_cfi[0x1]; 399 u8 first_vid[0xc]; 400 401 u8 ip_protocol[0x8]; 402 u8 ip_dscp[0x6]; 403 u8 ip_ecn[0x2]; 404 u8 cvlan_tag[0x1]; 405 u8 svlan_tag[0x1]; 406 u8 frag[0x1]; 407 u8 ip_version[0x4]; 408 u8 tcp_flags[0x9]; 409 410 u8 tcp_sport[0x10]; 411 u8 tcp_dport[0x10]; 412 413 u8 reserved_at_c0[0x18]; 414 u8 ttl_hoplimit[0x8]; 415 416 u8 udp_sport[0x10]; 417 u8 udp_dport[0x10]; 418 419 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 420 421 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 422 }; 423 424 struct mlx5_ifc_fte_match_set_misc_bits { 425 u8 reserved_at_0[0x8]; 426 u8 source_sqn[0x18]; 427 428 u8 source_eswitch_owner_vhca_id[0x10]; 429 u8 source_port[0x10]; 430 431 u8 outer_second_prio[0x3]; 432 u8 outer_second_cfi[0x1]; 433 u8 outer_second_vid[0xc]; 434 u8 inner_second_prio[0x3]; 435 u8 inner_second_cfi[0x1]; 436 u8 inner_second_vid[0xc]; 437 438 u8 outer_second_cvlan_tag[0x1]; 439 u8 inner_second_cvlan_tag[0x1]; 440 u8 outer_second_svlan_tag[0x1]; 441 u8 inner_second_svlan_tag[0x1]; 442 u8 reserved_at_64[0xc]; 443 u8 gre_protocol[0x10]; 444 445 u8 gre_key_h[0x18]; 446 u8 gre_key_l[0x8]; 447 448 u8 vxlan_vni[0x18]; 449 u8 reserved_at_b8[0x8]; 450 451 u8 reserved_at_c0[0x20]; 452 453 u8 reserved_at_e0[0xc]; 454 u8 outer_ipv6_flow_label[0x14]; 455 456 u8 reserved_at_100[0xc]; 457 u8 inner_ipv6_flow_label[0x14]; 458 459 u8 reserved_at_120[0x28]; 460 u8 bth_dst_qp[0x18]; 461 u8 reserved_at_160[0x20]; 462 u8 outer_esp_spi[0x20]; 463 u8 reserved_at_1a0[0x60]; 464 }; 465 466 struct mlx5_ifc_fte_match_mpls_bits { 467 u8 mpls_label[0x14]; 468 u8 mpls_exp[0x3]; 469 u8 mpls_s_bos[0x1]; 470 u8 mpls_ttl[0x8]; 471 }; 472 473 struct mlx5_ifc_fte_match_set_misc2_bits { 474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 475 476 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 477 478 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 479 480 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 481 482 u8 reserved_at_80[0x100]; 483 484 u8 metadata_reg_a[0x20]; 485 486 u8 reserved_at_1a0[0x60]; 487 }; 488 489 struct mlx5_ifc_cmd_pas_bits { 490 u8 pa_h[0x20]; 491 492 u8 pa_l[0x14]; 493 u8 reserved_at_34[0xc]; 494 }; 495 496 struct mlx5_ifc_uint64_bits { 497 u8 hi[0x20]; 498 499 u8 lo[0x20]; 500 }; 501 502 enum { 503 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 504 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 505 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 506 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 507 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 508 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 509 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 510 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 511 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 512 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 513 }; 514 515 struct mlx5_ifc_ads_bits { 516 u8 fl[0x1]; 517 u8 free_ar[0x1]; 518 u8 reserved_at_2[0xe]; 519 u8 pkey_index[0x10]; 520 521 u8 reserved_at_20[0x8]; 522 u8 grh[0x1]; 523 u8 mlid[0x7]; 524 u8 rlid[0x10]; 525 526 u8 ack_timeout[0x5]; 527 u8 reserved_at_45[0x3]; 528 u8 src_addr_index[0x8]; 529 u8 reserved_at_50[0x4]; 530 u8 stat_rate[0x4]; 531 u8 hop_limit[0x8]; 532 533 u8 reserved_at_60[0x4]; 534 u8 tclass[0x8]; 535 u8 flow_label[0x14]; 536 537 u8 rgid_rip[16][0x8]; 538 539 u8 reserved_at_100[0x4]; 540 u8 f_dscp[0x1]; 541 u8 f_ecn[0x1]; 542 u8 reserved_at_106[0x1]; 543 u8 f_eth_prio[0x1]; 544 u8 ecn[0x2]; 545 u8 dscp[0x6]; 546 u8 udp_sport[0x10]; 547 548 u8 dei_cfi[0x1]; 549 u8 eth_prio[0x3]; 550 u8 sl[0x4]; 551 u8 vhca_port_num[0x8]; 552 u8 rmac_47_32[0x10]; 553 554 u8 rmac_31_0[0x20]; 555 }; 556 557 struct mlx5_ifc_flow_table_nic_cap_bits { 558 u8 nic_rx_multi_path_tirs[0x1]; 559 u8 nic_rx_multi_path_tirs_fts[0x1]; 560 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 561 u8 reserved_at_3[0x1d]; 562 u8 encap_general_header[0x1]; 563 u8 reserved_at_21[0xa]; 564 u8 log_max_packet_reformat_context[0x5]; 565 u8 reserved_at_30[0x6]; 566 u8 max_encap_header_size[0xa]; 567 u8 reserved_at_40[0x1c0]; 568 569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 570 571 u8 reserved_at_400[0x200]; 572 573 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 574 575 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 576 577 u8 reserved_at_a00[0x200]; 578 579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 580 581 u8 reserved_at_e00[0x7200]; 582 }; 583 584 struct mlx5_ifc_flow_table_eswitch_cap_bits { 585 u8 reserved_at_0[0x1c]; 586 u8 fdb_multi_path_to_table[0x1]; 587 u8 reserved_at_1d[0x1]; 588 u8 multi_fdb_encap[0x1]; 589 u8 reserved_at_1e[0x1e1]; 590 591 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 592 593 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 594 595 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 596 597 u8 reserved_at_800[0x7800]; 598 }; 599 600 struct mlx5_ifc_e_switch_cap_bits { 601 u8 vport_svlan_strip[0x1]; 602 u8 vport_cvlan_strip[0x1]; 603 u8 vport_svlan_insert[0x1]; 604 u8 vport_cvlan_insert_if_not_exist[0x1]; 605 u8 vport_cvlan_insert_overwrite[0x1]; 606 u8 reserved_at_5[0x18]; 607 u8 merged_eswitch[0x1]; 608 u8 nic_vport_node_guid_modify[0x1]; 609 u8 nic_vport_port_guid_modify[0x1]; 610 611 u8 vxlan_encap_decap[0x1]; 612 u8 nvgre_encap_decap[0x1]; 613 u8 reserved_at_22[0x9]; 614 u8 log_max_packet_reformat_context[0x5]; 615 u8 reserved_2b[0x6]; 616 u8 max_encap_header_size[0xa]; 617 618 u8 reserved_40[0x7c0]; 619 620 }; 621 622 struct mlx5_ifc_qos_cap_bits { 623 u8 packet_pacing[0x1]; 624 u8 esw_scheduling[0x1]; 625 u8 esw_bw_share[0x1]; 626 u8 esw_rate_limit[0x1]; 627 u8 reserved_at_4[0x1]; 628 u8 packet_pacing_burst_bound[0x1]; 629 u8 packet_pacing_typical_size[0x1]; 630 u8 reserved_at_7[0x19]; 631 632 u8 reserved_at_20[0x20]; 633 634 u8 packet_pacing_max_rate[0x20]; 635 636 u8 packet_pacing_min_rate[0x20]; 637 638 u8 reserved_at_80[0x10]; 639 u8 packet_pacing_rate_table_size[0x10]; 640 641 u8 esw_element_type[0x10]; 642 u8 esw_tsar_type[0x10]; 643 644 u8 reserved_at_c0[0x10]; 645 u8 max_qos_para_vport[0x10]; 646 647 u8 max_tsar_bw_share[0x20]; 648 649 u8 reserved_at_100[0x700]; 650 }; 651 652 struct mlx5_ifc_debug_cap_bits { 653 u8 reserved_at_0[0x20]; 654 655 u8 reserved_at_20[0x2]; 656 u8 stall_detect[0x1]; 657 u8 reserved_at_23[0x1d]; 658 659 u8 reserved_at_40[0x7c0]; 660 }; 661 662 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 663 u8 csum_cap[0x1]; 664 u8 vlan_cap[0x1]; 665 u8 lro_cap[0x1]; 666 u8 lro_psh_flag[0x1]; 667 u8 lro_time_stamp[0x1]; 668 u8 reserved_at_5[0x2]; 669 u8 wqe_vlan_insert[0x1]; 670 u8 self_lb_en_modifiable[0x1]; 671 u8 reserved_at_9[0x2]; 672 u8 max_lso_cap[0x5]; 673 u8 multi_pkt_send_wqe[0x2]; 674 u8 wqe_inline_mode[0x2]; 675 u8 rss_ind_tbl_cap[0x4]; 676 u8 reg_umr_sq[0x1]; 677 u8 scatter_fcs[0x1]; 678 u8 enhanced_multi_pkt_send_wqe[0x1]; 679 u8 tunnel_lso_const_out_ip_id[0x1]; 680 u8 reserved_at_1c[0x2]; 681 u8 tunnel_stateless_gre[0x1]; 682 u8 tunnel_stateless_vxlan[0x1]; 683 684 u8 swp[0x1]; 685 u8 swp_csum[0x1]; 686 u8 swp_lso[0x1]; 687 u8 reserved_at_23[0xd]; 688 u8 max_vxlan_udp_ports[0x8]; 689 u8 reserved_at_38[0x6]; 690 u8 max_geneve_opt_len[0x1]; 691 u8 tunnel_stateless_geneve_rx[0x1]; 692 693 u8 reserved_at_40[0x10]; 694 u8 lro_min_mss_size[0x10]; 695 696 u8 reserved_at_60[0x120]; 697 698 u8 lro_timer_supported_periods[4][0x20]; 699 700 u8 reserved_at_200[0x600]; 701 }; 702 703 struct mlx5_ifc_roce_cap_bits { 704 u8 roce_apm[0x1]; 705 u8 reserved_at_1[0x1f]; 706 707 u8 reserved_at_20[0x60]; 708 709 u8 reserved_at_80[0xc]; 710 u8 l3_type[0x4]; 711 u8 reserved_at_90[0x8]; 712 u8 roce_version[0x8]; 713 714 u8 reserved_at_a0[0x10]; 715 u8 r_roce_dest_udp_port[0x10]; 716 717 u8 r_roce_max_src_udp_port[0x10]; 718 u8 r_roce_min_src_udp_port[0x10]; 719 720 u8 reserved_at_e0[0x10]; 721 u8 roce_address_table_size[0x10]; 722 723 u8 reserved_at_100[0x700]; 724 }; 725 726 struct mlx5_ifc_device_mem_cap_bits { 727 u8 memic[0x1]; 728 u8 reserved_at_1[0x1f]; 729 730 u8 reserved_at_20[0xb]; 731 u8 log_min_memic_alloc_size[0x5]; 732 u8 reserved_at_30[0x8]; 733 u8 log_max_memic_addr_alignment[0x8]; 734 735 u8 memic_bar_start_addr[0x40]; 736 737 u8 memic_bar_size[0x20]; 738 739 u8 max_memic_size[0x20]; 740 741 u8 reserved_at_c0[0x740]; 742 }; 743 744 enum { 745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 749 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 750 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 751 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 754 }; 755 756 enum { 757 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 758 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 759 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 760 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 761 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 762 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 763 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 764 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 765 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 766 }; 767 768 struct mlx5_ifc_atomic_caps_bits { 769 u8 reserved_at_0[0x40]; 770 771 u8 atomic_req_8B_endianness_mode[0x2]; 772 u8 reserved_at_42[0x4]; 773 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 774 775 u8 reserved_at_47[0x19]; 776 777 u8 reserved_at_60[0x20]; 778 779 u8 reserved_at_80[0x10]; 780 u8 atomic_operations[0x10]; 781 782 u8 reserved_at_a0[0x10]; 783 u8 atomic_size_qp[0x10]; 784 785 u8 reserved_at_c0[0x10]; 786 u8 atomic_size_dc[0x10]; 787 788 u8 reserved_at_e0[0x720]; 789 }; 790 791 struct mlx5_ifc_odp_cap_bits { 792 u8 reserved_at_0[0x40]; 793 794 u8 sig[0x1]; 795 u8 reserved_at_41[0x1f]; 796 797 u8 reserved_at_60[0x20]; 798 799 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 800 801 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 802 803 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 804 805 u8 reserved_at_e0[0x720]; 806 }; 807 808 struct mlx5_ifc_calc_op { 809 u8 reserved_at_0[0x10]; 810 u8 reserved_at_10[0x9]; 811 u8 op_swap_endianness[0x1]; 812 u8 op_min[0x1]; 813 u8 op_xor[0x1]; 814 u8 op_or[0x1]; 815 u8 op_and[0x1]; 816 u8 op_max[0x1]; 817 u8 op_add[0x1]; 818 }; 819 820 struct mlx5_ifc_vector_calc_cap_bits { 821 u8 calc_matrix[0x1]; 822 u8 reserved_at_1[0x1f]; 823 u8 reserved_at_20[0x8]; 824 u8 max_vec_count[0x8]; 825 u8 reserved_at_30[0xd]; 826 u8 max_chunk_size[0x3]; 827 struct mlx5_ifc_calc_op calc0; 828 struct mlx5_ifc_calc_op calc1; 829 struct mlx5_ifc_calc_op calc2; 830 struct mlx5_ifc_calc_op calc3; 831 832 u8 reserved_at_e0[0x720]; 833 }; 834 835 enum { 836 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 837 MLX5_WQ_TYPE_CYCLIC = 0x1, 838 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 839 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 840 }; 841 842 enum { 843 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 844 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 845 }; 846 847 enum { 848 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 849 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 850 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 851 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 852 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 853 }; 854 855 enum { 856 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 857 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 858 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 859 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 860 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 861 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 862 }; 863 864 enum { 865 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 866 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 867 }; 868 869 enum { 870 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 871 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 872 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 873 }; 874 875 enum { 876 MLX5_CAP_PORT_TYPE_IB = 0x0, 877 MLX5_CAP_PORT_TYPE_ETH = 0x1, 878 }; 879 880 enum { 881 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 882 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 883 MLX5_CAP_UMR_FENCE_NONE = 0x2, 884 }; 885 886 struct mlx5_ifc_cmd_hca_cap_bits { 887 u8 reserved_at_0[0x30]; 888 u8 vhca_id[0x10]; 889 890 u8 reserved_at_40[0x40]; 891 892 u8 log_max_srq_sz[0x8]; 893 u8 log_max_qp_sz[0x8]; 894 u8 reserved_at_90[0xb]; 895 u8 log_max_qp[0x5]; 896 897 u8 reserved_at_a0[0xb]; 898 u8 log_max_srq[0x5]; 899 u8 reserved_at_b0[0x10]; 900 901 u8 reserved_at_c0[0x8]; 902 u8 log_max_cq_sz[0x8]; 903 u8 reserved_at_d0[0xb]; 904 u8 log_max_cq[0x5]; 905 906 u8 log_max_eq_sz[0x8]; 907 u8 reserved_at_e8[0x2]; 908 u8 log_max_mkey[0x6]; 909 u8 reserved_at_f0[0x8]; 910 u8 dump_fill_mkey[0x1]; 911 u8 reserved_at_f9[0x2]; 912 u8 fast_teardown[0x1]; 913 u8 log_max_eq[0x4]; 914 915 u8 max_indirection[0x8]; 916 u8 fixed_buffer_size[0x1]; 917 u8 log_max_mrw_sz[0x7]; 918 u8 force_teardown[0x1]; 919 u8 reserved_at_111[0x1]; 920 u8 log_max_bsf_list_size[0x6]; 921 u8 umr_extended_translation_offset[0x1]; 922 u8 null_mkey[0x1]; 923 u8 log_max_klm_list_size[0x6]; 924 925 u8 reserved_at_120[0xa]; 926 u8 log_max_ra_req_dc[0x6]; 927 u8 reserved_at_130[0xa]; 928 u8 log_max_ra_res_dc[0x6]; 929 930 u8 reserved_at_140[0xa]; 931 u8 log_max_ra_req_qp[0x6]; 932 u8 reserved_at_150[0xa]; 933 u8 log_max_ra_res_qp[0x6]; 934 935 u8 end_pad[0x1]; 936 u8 cc_query_allowed[0x1]; 937 u8 cc_modify_allowed[0x1]; 938 u8 start_pad[0x1]; 939 u8 cache_line_128byte[0x1]; 940 u8 reserved_at_165[0xa]; 941 u8 qcam_reg[0x1]; 942 u8 gid_table_size[0x10]; 943 944 u8 out_of_seq_cnt[0x1]; 945 u8 vport_counters[0x1]; 946 u8 retransmission_q_counters[0x1]; 947 u8 debug[0x1]; 948 u8 modify_rq_counter_set_id[0x1]; 949 u8 rq_delay_drop[0x1]; 950 u8 max_qp_cnt[0xa]; 951 u8 pkey_table_size[0x10]; 952 953 u8 vport_group_manager[0x1]; 954 u8 vhca_group_manager[0x1]; 955 u8 ib_virt[0x1]; 956 u8 eth_virt[0x1]; 957 u8 vnic_env_queue_counters[0x1]; 958 u8 ets[0x1]; 959 u8 nic_flow_table[0x1]; 960 u8 eswitch_manager[0x1]; 961 u8 device_memory[0x1]; 962 u8 mcam_reg[0x1]; 963 u8 pcam_reg[0x1]; 964 u8 local_ca_ack_delay[0x5]; 965 u8 port_module_event[0x1]; 966 u8 enhanced_error_q_counters[0x1]; 967 u8 ports_check[0x1]; 968 u8 reserved_at_1b3[0x1]; 969 u8 disable_link_up[0x1]; 970 u8 beacon_led[0x1]; 971 u8 port_type[0x2]; 972 u8 num_ports[0x8]; 973 974 u8 reserved_at_1c0[0x1]; 975 u8 pps[0x1]; 976 u8 pps_modify[0x1]; 977 u8 log_max_msg[0x5]; 978 u8 reserved_at_1c8[0x4]; 979 u8 max_tc[0x4]; 980 u8 temp_warn_event[0x1]; 981 u8 dcbx[0x1]; 982 u8 general_notification_event[0x1]; 983 u8 reserved_at_1d3[0x2]; 984 u8 fpga[0x1]; 985 u8 rol_s[0x1]; 986 u8 rol_g[0x1]; 987 u8 reserved_at_1d8[0x1]; 988 u8 wol_s[0x1]; 989 u8 wol_g[0x1]; 990 u8 wol_a[0x1]; 991 u8 wol_b[0x1]; 992 u8 wol_m[0x1]; 993 u8 wol_u[0x1]; 994 u8 wol_p[0x1]; 995 996 u8 stat_rate_support[0x10]; 997 u8 reserved_at_1f0[0xc]; 998 u8 cqe_version[0x4]; 999 1000 u8 compact_address_vector[0x1]; 1001 u8 striding_rq[0x1]; 1002 u8 reserved_at_202[0x1]; 1003 u8 ipoib_enhanced_offloads[0x1]; 1004 u8 ipoib_basic_offloads[0x1]; 1005 u8 reserved_at_205[0x1]; 1006 u8 repeated_block_disabled[0x1]; 1007 u8 umr_modify_entity_size_disabled[0x1]; 1008 u8 umr_modify_atomic_disabled[0x1]; 1009 u8 umr_indirect_mkey_disabled[0x1]; 1010 u8 umr_fence[0x2]; 1011 u8 dc_req_scat_data_cqe[0x1]; 1012 u8 reserved_at_20d[0x2]; 1013 u8 drain_sigerr[0x1]; 1014 u8 cmdif_checksum[0x2]; 1015 u8 sigerr_cqe[0x1]; 1016 u8 reserved_at_213[0x1]; 1017 u8 wq_signature[0x1]; 1018 u8 sctr_data_cqe[0x1]; 1019 u8 reserved_at_216[0x1]; 1020 u8 sho[0x1]; 1021 u8 tph[0x1]; 1022 u8 rf[0x1]; 1023 u8 dct[0x1]; 1024 u8 qos[0x1]; 1025 u8 eth_net_offloads[0x1]; 1026 u8 roce[0x1]; 1027 u8 atomic[0x1]; 1028 u8 reserved_at_21f[0x1]; 1029 1030 u8 cq_oi[0x1]; 1031 u8 cq_resize[0x1]; 1032 u8 cq_moderation[0x1]; 1033 u8 reserved_at_223[0x3]; 1034 u8 cq_eq_remap[0x1]; 1035 u8 pg[0x1]; 1036 u8 block_lb_mc[0x1]; 1037 u8 reserved_at_229[0x1]; 1038 u8 scqe_break_moderation[0x1]; 1039 u8 cq_period_start_from_cqe[0x1]; 1040 u8 cd[0x1]; 1041 u8 reserved_at_22d[0x1]; 1042 u8 apm[0x1]; 1043 u8 vector_calc[0x1]; 1044 u8 umr_ptr_rlky[0x1]; 1045 u8 imaicl[0x1]; 1046 u8 reserved_at_232[0x4]; 1047 u8 qkv[0x1]; 1048 u8 pkv[0x1]; 1049 u8 set_deth_sqpn[0x1]; 1050 u8 reserved_at_239[0x3]; 1051 u8 xrc[0x1]; 1052 u8 ud[0x1]; 1053 u8 uc[0x1]; 1054 u8 rc[0x1]; 1055 1056 u8 uar_4k[0x1]; 1057 u8 reserved_at_241[0x9]; 1058 u8 uar_sz[0x6]; 1059 u8 reserved_at_250[0x8]; 1060 u8 log_pg_sz[0x8]; 1061 1062 u8 bf[0x1]; 1063 u8 driver_version[0x1]; 1064 u8 pad_tx_eth_packet[0x1]; 1065 u8 reserved_at_263[0x8]; 1066 u8 log_bf_reg_size[0x5]; 1067 1068 u8 reserved_at_270[0xb]; 1069 u8 lag_master[0x1]; 1070 u8 num_lag_ports[0x4]; 1071 1072 u8 reserved_at_280[0x10]; 1073 u8 max_wqe_sz_sq[0x10]; 1074 1075 u8 reserved_at_2a0[0x10]; 1076 u8 max_wqe_sz_rq[0x10]; 1077 1078 u8 max_flow_counter_31_16[0x10]; 1079 u8 max_wqe_sz_sq_dc[0x10]; 1080 1081 u8 reserved_at_2e0[0x7]; 1082 u8 max_qp_mcg[0x19]; 1083 1084 u8 reserved_at_300[0x18]; 1085 u8 log_max_mcg[0x8]; 1086 1087 u8 reserved_at_320[0x3]; 1088 u8 log_max_transport_domain[0x5]; 1089 u8 reserved_at_328[0x3]; 1090 u8 log_max_pd[0x5]; 1091 u8 reserved_at_330[0xb]; 1092 u8 log_max_xrcd[0x5]; 1093 1094 u8 nic_receive_steering_discard[0x1]; 1095 u8 receive_discard_vport_down[0x1]; 1096 u8 transmit_discard_vport_down[0x1]; 1097 u8 reserved_at_343[0x5]; 1098 u8 log_max_flow_counter_bulk[0x8]; 1099 u8 max_flow_counter_15_0[0x10]; 1100 1101 1102 u8 reserved_at_360[0x3]; 1103 u8 log_max_rq[0x5]; 1104 u8 reserved_at_368[0x3]; 1105 u8 log_max_sq[0x5]; 1106 u8 reserved_at_370[0x3]; 1107 u8 log_max_tir[0x5]; 1108 u8 reserved_at_378[0x3]; 1109 u8 log_max_tis[0x5]; 1110 1111 u8 basic_cyclic_rcv_wqe[0x1]; 1112 u8 reserved_at_381[0x2]; 1113 u8 log_max_rmp[0x5]; 1114 u8 reserved_at_388[0x3]; 1115 u8 log_max_rqt[0x5]; 1116 u8 reserved_at_390[0x3]; 1117 u8 log_max_rqt_size[0x5]; 1118 u8 reserved_at_398[0x3]; 1119 u8 log_max_tis_per_sq[0x5]; 1120 1121 u8 ext_stride_num_range[0x1]; 1122 u8 reserved_at_3a1[0x2]; 1123 u8 log_max_stride_sz_rq[0x5]; 1124 u8 reserved_at_3a8[0x3]; 1125 u8 log_min_stride_sz_rq[0x5]; 1126 u8 reserved_at_3b0[0x3]; 1127 u8 log_max_stride_sz_sq[0x5]; 1128 u8 reserved_at_3b8[0x3]; 1129 u8 log_min_stride_sz_sq[0x5]; 1130 1131 u8 hairpin[0x1]; 1132 u8 reserved_at_3c1[0x2]; 1133 u8 log_max_hairpin_queues[0x5]; 1134 u8 reserved_at_3c8[0x3]; 1135 u8 log_max_hairpin_wq_data_sz[0x5]; 1136 u8 reserved_at_3d0[0x3]; 1137 u8 log_max_hairpin_num_packets[0x5]; 1138 u8 reserved_at_3d8[0x3]; 1139 u8 log_max_wq_sz[0x5]; 1140 1141 u8 nic_vport_change_event[0x1]; 1142 u8 disable_local_lb_uc[0x1]; 1143 u8 disable_local_lb_mc[0x1]; 1144 u8 log_min_hairpin_wq_data_sz[0x5]; 1145 u8 reserved_at_3e8[0x3]; 1146 u8 log_max_vlan_list[0x5]; 1147 u8 reserved_at_3f0[0x3]; 1148 u8 log_max_current_mc_list[0x5]; 1149 u8 reserved_at_3f8[0x3]; 1150 u8 log_max_current_uc_list[0x5]; 1151 1152 u8 general_obj_types[0x40]; 1153 1154 u8 reserved_at_440[0x20]; 1155 1156 u8 reserved_at_460[0x10]; 1157 u8 max_num_eqs[0x10]; 1158 1159 u8 reserved_at_480[0x3]; 1160 u8 log_max_l2_table[0x5]; 1161 u8 reserved_at_488[0x8]; 1162 u8 log_uar_page_sz[0x10]; 1163 1164 u8 reserved_at_4a0[0x20]; 1165 u8 device_frequency_mhz[0x20]; 1166 u8 device_frequency_khz[0x20]; 1167 1168 u8 reserved_at_500[0x20]; 1169 u8 num_of_uars_per_page[0x20]; 1170 1171 u8 flex_parser_protocols[0x20]; 1172 u8 reserved_at_560[0x20]; 1173 1174 u8 reserved_at_580[0x3c]; 1175 u8 mini_cqe_resp_stride_index[0x1]; 1176 u8 cqe_128_always[0x1]; 1177 u8 cqe_compression_128[0x1]; 1178 u8 cqe_compression[0x1]; 1179 1180 u8 cqe_compression_timeout[0x10]; 1181 u8 cqe_compression_max_num[0x10]; 1182 1183 u8 reserved_at_5e0[0x10]; 1184 u8 tag_matching[0x1]; 1185 u8 rndv_offload_rc[0x1]; 1186 u8 rndv_offload_dc[0x1]; 1187 u8 log_tag_matching_list_sz[0x5]; 1188 u8 reserved_at_5f8[0x3]; 1189 u8 log_max_xrq[0x5]; 1190 1191 u8 affiliate_nic_vport_criteria[0x8]; 1192 u8 native_port_num[0x8]; 1193 u8 num_vhca_ports[0x8]; 1194 u8 reserved_at_618[0x6]; 1195 u8 sw_owner_id[0x1]; 1196 u8 reserved_at_61f[0x1e1]; 1197 }; 1198 1199 enum mlx5_flow_destination_type { 1200 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1201 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1202 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1203 1204 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1205 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1206 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1207 }; 1208 1209 struct mlx5_ifc_dest_format_struct_bits { 1210 u8 destination_type[0x8]; 1211 u8 destination_id[0x18]; 1212 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1213 u8 reserved_at_21[0xf]; 1214 u8 destination_eswitch_owner_vhca_id[0x10]; 1215 }; 1216 1217 struct mlx5_ifc_flow_counter_list_bits { 1218 u8 flow_counter_id[0x20]; 1219 1220 u8 reserved_at_20[0x20]; 1221 }; 1222 1223 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1224 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1225 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1226 u8 reserved_at_0[0x40]; 1227 }; 1228 1229 struct mlx5_ifc_fte_match_param_bits { 1230 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1231 1232 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1233 1234 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1235 1236 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1237 1238 u8 reserved_at_800[0x800]; 1239 }; 1240 1241 enum { 1242 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1243 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1244 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1245 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1246 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1247 }; 1248 1249 struct mlx5_ifc_rx_hash_field_select_bits { 1250 u8 l3_prot_type[0x1]; 1251 u8 l4_prot_type[0x1]; 1252 u8 selected_fields[0x1e]; 1253 }; 1254 1255 enum { 1256 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1257 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1258 }; 1259 1260 enum { 1261 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1262 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1263 }; 1264 1265 struct mlx5_ifc_wq_bits { 1266 u8 wq_type[0x4]; 1267 u8 wq_signature[0x1]; 1268 u8 end_padding_mode[0x2]; 1269 u8 cd_slave[0x1]; 1270 u8 reserved_at_8[0x18]; 1271 1272 u8 hds_skip_first_sge[0x1]; 1273 u8 log2_hds_buf_size[0x3]; 1274 u8 reserved_at_24[0x7]; 1275 u8 page_offset[0x5]; 1276 u8 lwm[0x10]; 1277 1278 u8 reserved_at_40[0x8]; 1279 u8 pd[0x18]; 1280 1281 u8 reserved_at_60[0x8]; 1282 u8 uar_page[0x18]; 1283 1284 u8 dbr_addr[0x40]; 1285 1286 u8 hw_counter[0x20]; 1287 1288 u8 sw_counter[0x20]; 1289 1290 u8 reserved_at_100[0xc]; 1291 u8 log_wq_stride[0x4]; 1292 u8 reserved_at_110[0x3]; 1293 u8 log_wq_pg_sz[0x5]; 1294 u8 reserved_at_118[0x3]; 1295 u8 log_wq_sz[0x5]; 1296 1297 u8 dbr_umem_valid[0x1]; 1298 u8 wq_umem_valid[0x1]; 1299 u8 reserved_at_122[0x1]; 1300 u8 log_hairpin_num_packets[0x5]; 1301 u8 reserved_at_128[0x3]; 1302 u8 log_hairpin_data_sz[0x5]; 1303 1304 u8 reserved_at_130[0x4]; 1305 u8 log_wqe_num_of_strides[0x4]; 1306 u8 two_byte_shift_en[0x1]; 1307 u8 reserved_at_139[0x4]; 1308 u8 log_wqe_stride_size[0x3]; 1309 1310 u8 reserved_at_140[0x4c0]; 1311 1312 struct mlx5_ifc_cmd_pas_bits pas[0]; 1313 }; 1314 1315 struct mlx5_ifc_rq_num_bits { 1316 u8 reserved_at_0[0x8]; 1317 u8 rq_num[0x18]; 1318 }; 1319 1320 struct mlx5_ifc_mac_address_layout_bits { 1321 u8 reserved_at_0[0x10]; 1322 u8 mac_addr_47_32[0x10]; 1323 1324 u8 mac_addr_31_0[0x20]; 1325 }; 1326 1327 struct mlx5_ifc_vlan_layout_bits { 1328 u8 reserved_at_0[0x14]; 1329 u8 vlan[0x0c]; 1330 1331 u8 reserved_at_20[0x20]; 1332 }; 1333 1334 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1335 u8 reserved_at_0[0xa0]; 1336 1337 u8 min_time_between_cnps[0x20]; 1338 1339 u8 reserved_at_c0[0x12]; 1340 u8 cnp_dscp[0x6]; 1341 u8 reserved_at_d8[0x4]; 1342 u8 cnp_prio_mode[0x1]; 1343 u8 cnp_802p_prio[0x3]; 1344 1345 u8 reserved_at_e0[0x720]; 1346 }; 1347 1348 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1349 u8 reserved_at_0[0x60]; 1350 1351 u8 reserved_at_60[0x4]; 1352 u8 clamp_tgt_rate[0x1]; 1353 u8 reserved_at_65[0x3]; 1354 u8 clamp_tgt_rate_after_time_inc[0x1]; 1355 u8 reserved_at_69[0x17]; 1356 1357 u8 reserved_at_80[0x20]; 1358 1359 u8 rpg_time_reset[0x20]; 1360 1361 u8 rpg_byte_reset[0x20]; 1362 1363 u8 rpg_threshold[0x20]; 1364 1365 u8 rpg_max_rate[0x20]; 1366 1367 u8 rpg_ai_rate[0x20]; 1368 1369 u8 rpg_hai_rate[0x20]; 1370 1371 u8 rpg_gd[0x20]; 1372 1373 u8 rpg_min_dec_fac[0x20]; 1374 1375 u8 rpg_min_rate[0x20]; 1376 1377 u8 reserved_at_1c0[0xe0]; 1378 1379 u8 rate_to_set_on_first_cnp[0x20]; 1380 1381 u8 dce_tcp_g[0x20]; 1382 1383 u8 dce_tcp_rtt[0x20]; 1384 1385 u8 rate_reduce_monitor_period[0x20]; 1386 1387 u8 reserved_at_320[0x20]; 1388 1389 u8 initial_alpha_value[0x20]; 1390 1391 u8 reserved_at_360[0x4a0]; 1392 }; 1393 1394 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1395 u8 reserved_at_0[0x80]; 1396 1397 u8 rppp_max_rps[0x20]; 1398 1399 u8 rpg_time_reset[0x20]; 1400 1401 u8 rpg_byte_reset[0x20]; 1402 1403 u8 rpg_threshold[0x20]; 1404 1405 u8 rpg_max_rate[0x20]; 1406 1407 u8 rpg_ai_rate[0x20]; 1408 1409 u8 rpg_hai_rate[0x20]; 1410 1411 u8 rpg_gd[0x20]; 1412 1413 u8 rpg_min_dec_fac[0x20]; 1414 1415 u8 rpg_min_rate[0x20]; 1416 1417 u8 reserved_at_1c0[0x640]; 1418 }; 1419 1420 enum { 1421 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1422 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1423 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1424 }; 1425 1426 struct mlx5_ifc_resize_field_select_bits { 1427 u8 resize_field_select[0x20]; 1428 }; 1429 1430 enum { 1431 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1432 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1433 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1434 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1435 }; 1436 1437 struct mlx5_ifc_modify_field_select_bits { 1438 u8 modify_field_select[0x20]; 1439 }; 1440 1441 struct mlx5_ifc_field_select_r_roce_np_bits { 1442 u8 field_select_r_roce_np[0x20]; 1443 }; 1444 1445 struct mlx5_ifc_field_select_r_roce_rp_bits { 1446 u8 field_select_r_roce_rp[0x20]; 1447 }; 1448 1449 enum { 1450 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1451 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1452 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1453 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1454 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1455 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1456 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1457 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1458 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1459 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1460 }; 1461 1462 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1463 u8 field_select_8021qaurp[0x20]; 1464 }; 1465 1466 struct mlx5_ifc_phys_layer_cntrs_bits { 1467 u8 time_since_last_clear_high[0x20]; 1468 1469 u8 time_since_last_clear_low[0x20]; 1470 1471 u8 symbol_errors_high[0x20]; 1472 1473 u8 symbol_errors_low[0x20]; 1474 1475 u8 sync_headers_errors_high[0x20]; 1476 1477 u8 sync_headers_errors_low[0x20]; 1478 1479 u8 edpl_bip_errors_lane0_high[0x20]; 1480 1481 u8 edpl_bip_errors_lane0_low[0x20]; 1482 1483 u8 edpl_bip_errors_lane1_high[0x20]; 1484 1485 u8 edpl_bip_errors_lane1_low[0x20]; 1486 1487 u8 edpl_bip_errors_lane2_high[0x20]; 1488 1489 u8 edpl_bip_errors_lane2_low[0x20]; 1490 1491 u8 edpl_bip_errors_lane3_high[0x20]; 1492 1493 u8 edpl_bip_errors_lane3_low[0x20]; 1494 1495 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1496 1497 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1498 1499 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1500 1501 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1502 1503 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1504 1505 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1506 1507 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1508 1509 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1510 1511 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1512 1513 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1514 1515 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1516 1517 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1518 1519 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1520 1521 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1522 1523 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1524 1525 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1526 1527 u8 rs_fec_corrected_blocks_high[0x20]; 1528 1529 u8 rs_fec_corrected_blocks_low[0x20]; 1530 1531 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1532 1533 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1534 1535 u8 rs_fec_no_errors_blocks_high[0x20]; 1536 1537 u8 rs_fec_no_errors_blocks_low[0x20]; 1538 1539 u8 rs_fec_single_error_blocks_high[0x20]; 1540 1541 u8 rs_fec_single_error_blocks_low[0x20]; 1542 1543 u8 rs_fec_corrected_symbols_total_high[0x20]; 1544 1545 u8 rs_fec_corrected_symbols_total_low[0x20]; 1546 1547 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1548 1549 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1550 1551 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1552 1553 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1554 1555 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1556 1557 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1558 1559 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1560 1561 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1562 1563 u8 link_down_events[0x20]; 1564 1565 u8 successful_recovery_events[0x20]; 1566 1567 u8 reserved_at_640[0x180]; 1568 }; 1569 1570 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1571 u8 time_since_last_clear_high[0x20]; 1572 1573 u8 time_since_last_clear_low[0x20]; 1574 1575 u8 phy_received_bits_high[0x20]; 1576 1577 u8 phy_received_bits_low[0x20]; 1578 1579 u8 phy_symbol_errors_high[0x20]; 1580 1581 u8 phy_symbol_errors_low[0x20]; 1582 1583 u8 phy_corrected_bits_high[0x20]; 1584 1585 u8 phy_corrected_bits_low[0x20]; 1586 1587 u8 phy_corrected_bits_lane0_high[0x20]; 1588 1589 u8 phy_corrected_bits_lane0_low[0x20]; 1590 1591 u8 phy_corrected_bits_lane1_high[0x20]; 1592 1593 u8 phy_corrected_bits_lane1_low[0x20]; 1594 1595 u8 phy_corrected_bits_lane2_high[0x20]; 1596 1597 u8 phy_corrected_bits_lane2_low[0x20]; 1598 1599 u8 phy_corrected_bits_lane3_high[0x20]; 1600 1601 u8 phy_corrected_bits_lane3_low[0x20]; 1602 1603 u8 reserved_at_200[0x5c0]; 1604 }; 1605 1606 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1607 u8 symbol_error_counter[0x10]; 1608 1609 u8 link_error_recovery_counter[0x8]; 1610 1611 u8 link_downed_counter[0x8]; 1612 1613 u8 port_rcv_errors[0x10]; 1614 1615 u8 port_rcv_remote_physical_errors[0x10]; 1616 1617 u8 port_rcv_switch_relay_errors[0x10]; 1618 1619 u8 port_xmit_discards[0x10]; 1620 1621 u8 port_xmit_constraint_errors[0x8]; 1622 1623 u8 port_rcv_constraint_errors[0x8]; 1624 1625 u8 reserved_at_70[0x8]; 1626 1627 u8 link_overrun_errors[0x8]; 1628 1629 u8 reserved_at_80[0x10]; 1630 1631 u8 vl_15_dropped[0x10]; 1632 1633 u8 reserved_at_a0[0x80]; 1634 1635 u8 port_xmit_wait[0x20]; 1636 }; 1637 1638 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1639 u8 transmit_queue_high[0x20]; 1640 1641 u8 transmit_queue_low[0x20]; 1642 1643 u8 reserved_at_40[0x780]; 1644 }; 1645 1646 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1647 u8 rx_octets_high[0x20]; 1648 1649 u8 rx_octets_low[0x20]; 1650 1651 u8 reserved_at_40[0xc0]; 1652 1653 u8 rx_frames_high[0x20]; 1654 1655 u8 rx_frames_low[0x20]; 1656 1657 u8 tx_octets_high[0x20]; 1658 1659 u8 tx_octets_low[0x20]; 1660 1661 u8 reserved_at_180[0xc0]; 1662 1663 u8 tx_frames_high[0x20]; 1664 1665 u8 tx_frames_low[0x20]; 1666 1667 u8 rx_pause_high[0x20]; 1668 1669 u8 rx_pause_low[0x20]; 1670 1671 u8 rx_pause_duration_high[0x20]; 1672 1673 u8 rx_pause_duration_low[0x20]; 1674 1675 u8 tx_pause_high[0x20]; 1676 1677 u8 tx_pause_low[0x20]; 1678 1679 u8 tx_pause_duration_high[0x20]; 1680 1681 u8 tx_pause_duration_low[0x20]; 1682 1683 u8 rx_pause_transition_high[0x20]; 1684 1685 u8 rx_pause_transition_low[0x20]; 1686 1687 u8 reserved_at_3c0[0x40]; 1688 1689 u8 device_stall_minor_watermark_cnt_high[0x20]; 1690 1691 u8 device_stall_minor_watermark_cnt_low[0x20]; 1692 1693 u8 device_stall_critical_watermark_cnt_high[0x20]; 1694 1695 u8 device_stall_critical_watermark_cnt_low[0x20]; 1696 1697 u8 reserved_at_480[0x340]; 1698 }; 1699 1700 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1701 u8 port_transmit_wait_high[0x20]; 1702 1703 u8 port_transmit_wait_low[0x20]; 1704 1705 u8 reserved_at_40[0x100]; 1706 1707 u8 rx_buffer_almost_full_high[0x20]; 1708 1709 u8 rx_buffer_almost_full_low[0x20]; 1710 1711 u8 rx_buffer_full_high[0x20]; 1712 1713 u8 rx_buffer_full_low[0x20]; 1714 1715 u8 rx_icrc_encapsulated_high[0x20]; 1716 1717 u8 rx_icrc_encapsulated_low[0x20]; 1718 1719 u8 reserved_at_200[0x5c0]; 1720 }; 1721 1722 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1723 u8 dot3stats_alignment_errors_high[0x20]; 1724 1725 u8 dot3stats_alignment_errors_low[0x20]; 1726 1727 u8 dot3stats_fcs_errors_high[0x20]; 1728 1729 u8 dot3stats_fcs_errors_low[0x20]; 1730 1731 u8 dot3stats_single_collision_frames_high[0x20]; 1732 1733 u8 dot3stats_single_collision_frames_low[0x20]; 1734 1735 u8 dot3stats_multiple_collision_frames_high[0x20]; 1736 1737 u8 dot3stats_multiple_collision_frames_low[0x20]; 1738 1739 u8 dot3stats_sqe_test_errors_high[0x20]; 1740 1741 u8 dot3stats_sqe_test_errors_low[0x20]; 1742 1743 u8 dot3stats_deferred_transmissions_high[0x20]; 1744 1745 u8 dot3stats_deferred_transmissions_low[0x20]; 1746 1747 u8 dot3stats_late_collisions_high[0x20]; 1748 1749 u8 dot3stats_late_collisions_low[0x20]; 1750 1751 u8 dot3stats_excessive_collisions_high[0x20]; 1752 1753 u8 dot3stats_excessive_collisions_low[0x20]; 1754 1755 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1756 1757 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1758 1759 u8 dot3stats_carrier_sense_errors_high[0x20]; 1760 1761 u8 dot3stats_carrier_sense_errors_low[0x20]; 1762 1763 u8 dot3stats_frame_too_longs_high[0x20]; 1764 1765 u8 dot3stats_frame_too_longs_low[0x20]; 1766 1767 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1768 1769 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1770 1771 u8 dot3stats_symbol_errors_high[0x20]; 1772 1773 u8 dot3stats_symbol_errors_low[0x20]; 1774 1775 u8 dot3control_in_unknown_opcodes_high[0x20]; 1776 1777 u8 dot3control_in_unknown_opcodes_low[0x20]; 1778 1779 u8 dot3in_pause_frames_high[0x20]; 1780 1781 u8 dot3in_pause_frames_low[0x20]; 1782 1783 u8 dot3out_pause_frames_high[0x20]; 1784 1785 u8 dot3out_pause_frames_low[0x20]; 1786 1787 u8 reserved_at_400[0x3c0]; 1788 }; 1789 1790 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1791 u8 ether_stats_drop_events_high[0x20]; 1792 1793 u8 ether_stats_drop_events_low[0x20]; 1794 1795 u8 ether_stats_octets_high[0x20]; 1796 1797 u8 ether_stats_octets_low[0x20]; 1798 1799 u8 ether_stats_pkts_high[0x20]; 1800 1801 u8 ether_stats_pkts_low[0x20]; 1802 1803 u8 ether_stats_broadcast_pkts_high[0x20]; 1804 1805 u8 ether_stats_broadcast_pkts_low[0x20]; 1806 1807 u8 ether_stats_multicast_pkts_high[0x20]; 1808 1809 u8 ether_stats_multicast_pkts_low[0x20]; 1810 1811 u8 ether_stats_crc_align_errors_high[0x20]; 1812 1813 u8 ether_stats_crc_align_errors_low[0x20]; 1814 1815 u8 ether_stats_undersize_pkts_high[0x20]; 1816 1817 u8 ether_stats_undersize_pkts_low[0x20]; 1818 1819 u8 ether_stats_oversize_pkts_high[0x20]; 1820 1821 u8 ether_stats_oversize_pkts_low[0x20]; 1822 1823 u8 ether_stats_fragments_high[0x20]; 1824 1825 u8 ether_stats_fragments_low[0x20]; 1826 1827 u8 ether_stats_jabbers_high[0x20]; 1828 1829 u8 ether_stats_jabbers_low[0x20]; 1830 1831 u8 ether_stats_collisions_high[0x20]; 1832 1833 u8 ether_stats_collisions_low[0x20]; 1834 1835 u8 ether_stats_pkts64octets_high[0x20]; 1836 1837 u8 ether_stats_pkts64octets_low[0x20]; 1838 1839 u8 ether_stats_pkts65to127octets_high[0x20]; 1840 1841 u8 ether_stats_pkts65to127octets_low[0x20]; 1842 1843 u8 ether_stats_pkts128to255octets_high[0x20]; 1844 1845 u8 ether_stats_pkts128to255octets_low[0x20]; 1846 1847 u8 ether_stats_pkts256to511octets_high[0x20]; 1848 1849 u8 ether_stats_pkts256to511octets_low[0x20]; 1850 1851 u8 ether_stats_pkts512to1023octets_high[0x20]; 1852 1853 u8 ether_stats_pkts512to1023octets_low[0x20]; 1854 1855 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1856 1857 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1858 1859 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1860 1861 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1862 1863 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1864 1865 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1866 1867 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1868 1869 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1870 1871 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1872 1873 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1874 1875 u8 reserved_at_540[0x280]; 1876 }; 1877 1878 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1879 u8 if_in_octets_high[0x20]; 1880 1881 u8 if_in_octets_low[0x20]; 1882 1883 u8 if_in_ucast_pkts_high[0x20]; 1884 1885 u8 if_in_ucast_pkts_low[0x20]; 1886 1887 u8 if_in_discards_high[0x20]; 1888 1889 u8 if_in_discards_low[0x20]; 1890 1891 u8 if_in_errors_high[0x20]; 1892 1893 u8 if_in_errors_low[0x20]; 1894 1895 u8 if_in_unknown_protos_high[0x20]; 1896 1897 u8 if_in_unknown_protos_low[0x20]; 1898 1899 u8 if_out_octets_high[0x20]; 1900 1901 u8 if_out_octets_low[0x20]; 1902 1903 u8 if_out_ucast_pkts_high[0x20]; 1904 1905 u8 if_out_ucast_pkts_low[0x20]; 1906 1907 u8 if_out_discards_high[0x20]; 1908 1909 u8 if_out_discards_low[0x20]; 1910 1911 u8 if_out_errors_high[0x20]; 1912 1913 u8 if_out_errors_low[0x20]; 1914 1915 u8 if_in_multicast_pkts_high[0x20]; 1916 1917 u8 if_in_multicast_pkts_low[0x20]; 1918 1919 u8 if_in_broadcast_pkts_high[0x20]; 1920 1921 u8 if_in_broadcast_pkts_low[0x20]; 1922 1923 u8 if_out_multicast_pkts_high[0x20]; 1924 1925 u8 if_out_multicast_pkts_low[0x20]; 1926 1927 u8 if_out_broadcast_pkts_high[0x20]; 1928 1929 u8 if_out_broadcast_pkts_low[0x20]; 1930 1931 u8 reserved_at_340[0x480]; 1932 }; 1933 1934 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1935 u8 a_frames_transmitted_ok_high[0x20]; 1936 1937 u8 a_frames_transmitted_ok_low[0x20]; 1938 1939 u8 a_frames_received_ok_high[0x20]; 1940 1941 u8 a_frames_received_ok_low[0x20]; 1942 1943 u8 a_frame_check_sequence_errors_high[0x20]; 1944 1945 u8 a_frame_check_sequence_errors_low[0x20]; 1946 1947 u8 a_alignment_errors_high[0x20]; 1948 1949 u8 a_alignment_errors_low[0x20]; 1950 1951 u8 a_octets_transmitted_ok_high[0x20]; 1952 1953 u8 a_octets_transmitted_ok_low[0x20]; 1954 1955 u8 a_octets_received_ok_high[0x20]; 1956 1957 u8 a_octets_received_ok_low[0x20]; 1958 1959 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1960 1961 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1962 1963 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1964 1965 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1966 1967 u8 a_multicast_frames_received_ok_high[0x20]; 1968 1969 u8 a_multicast_frames_received_ok_low[0x20]; 1970 1971 u8 a_broadcast_frames_received_ok_high[0x20]; 1972 1973 u8 a_broadcast_frames_received_ok_low[0x20]; 1974 1975 u8 a_in_range_length_errors_high[0x20]; 1976 1977 u8 a_in_range_length_errors_low[0x20]; 1978 1979 u8 a_out_of_range_length_field_high[0x20]; 1980 1981 u8 a_out_of_range_length_field_low[0x20]; 1982 1983 u8 a_frame_too_long_errors_high[0x20]; 1984 1985 u8 a_frame_too_long_errors_low[0x20]; 1986 1987 u8 a_symbol_error_during_carrier_high[0x20]; 1988 1989 u8 a_symbol_error_during_carrier_low[0x20]; 1990 1991 u8 a_mac_control_frames_transmitted_high[0x20]; 1992 1993 u8 a_mac_control_frames_transmitted_low[0x20]; 1994 1995 u8 a_mac_control_frames_received_high[0x20]; 1996 1997 u8 a_mac_control_frames_received_low[0x20]; 1998 1999 u8 a_unsupported_opcodes_received_high[0x20]; 2000 2001 u8 a_unsupported_opcodes_received_low[0x20]; 2002 2003 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2004 2005 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2006 2007 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2008 2009 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2010 2011 u8 reserved_at_4c0[0x300]; 2012 }; 2013 2014 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2015 u8 life_time_counter_high[0x20]; 2016 2017 u8 life_time_counter_low[0x20]; 2018 2019 u8 rx_errors[0x20]; 2020 2021 u8 tx_errors[0x20]; 2022 2023 u8 l0_to_recovery_eieos[0x20]; 2024 2025 u8 l0_to_recovery_ts[0x20]; 2026 2027 u8 l0_to_recovery_framing[0x20]; 2028 2029 u8 l0_to_recovery_retrain[0x20]; 2030 2031 u8 crc_error_dllp[0x20]; 2032 2033 u8 crc_error_tlp[0x20]; 2034 2035 u8 tx_overflow_buffer_pkt_high[0x20]; 2036 2037 u8 tx_overflow_buffer_pkt_low[0x20]; 2038 2039 u8 outbound_stalled_reads[0x20]; 2040 2041 u8 outbound_stalled_writes[0x20]; 2042 2043 u8 outbound_stalled_reads_events[0x20]; 2044 2045 u8 outbound_stalled_writes_events[0x20]; 2046 2047 u8 reserved_at_200[0x5c0]; 2048 }; 2049 2050 struct mlx5_ifc_cmd_inter_comp_event_bits { 2051 u8 command_completion_vector[0x20]; 2052 2053 u8 reserved_at_20[0xc0]; 2054 }; 2055 2056 struct mlx5_ifc_stall_vl_event_bits { 2057 u8 reserved_at_0[0x18]; 2058 u8 port_num[0x1]; 2059 u8 reserved_at_19[0x3]; 2060 u8 vl[0x4]; 2061 2062 u8 reserved_at_20[0xa0]; 2063 }; 2064 2065 struct mlx5_ifc_db_bf_congestion_event_bits { 2066 u8 event_subtype[0x8]; 2067 u8 reserved_at_8[0x8]; 2068 u8 congestion_level[0x8]; 2069 u8 reserved_at_18[0x8]; 2070 2071 u8 reserved_at_20[0xa0]; 2072 }; 2073 2074 struct mlx5_ifc_gpio_event_bits { 2075 u8 reserved_at_0[0x60]; 2076 2077 u8 gpio_event_hi[0x20]; 2078 2079 u8 gpio_event_lo[0x20]; 2080 2081 u8 reserved_at_a0[0x40]; 2082 }; 2083 2084 struct mlx5_ifc_port_state_change_event_bits { 2085 u8 reserved_at_0[0x40]; 2086 2087 u8 port_num[0x4]; 2088 u8 reserved_at_44[0x1c]; 2089 2090 u8 reserved_at_60[0x80]; 2091 }; 2092 2093 struct mlx5_ifc_dropped_packet_logged_bits { 2094 u8 reserved_at_0[0xe0]; 2095 }; 2096 2097 enum { 2098 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2099 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2100 }; 2101 2102 struct mlx5_ifc_cq_error_bits { 2103 u8 reserved_at_0[0x8]; 2104 u8 cqn[0x18]; 2105 2106 u8 reserved_at_20[0x20]; 2107 2108 u8 reserved_at_40[0x18]; 2109 u8 syndrome[0x8]; 2110 2111 u8 reserved_at_60[0x80]; 2112 }; 2113 2114 struct mlx5_ifc_rdma_page_fault_event_bits { 2115 u8 bytes_committed[0x20]; 2116 2117 u8 r_key[0x20]; 2118 2119 u8 reserved_at_40[0x10]; 2120 u8 packet_len[0x10]; 2121 2122 u8 rdma_op_len[0x20]; 2123 2124 u8 rdma_va[0x40]; 2125 2126 u8 reserved_at_c0[0x5]; 2127 u8 rdma[0x1]; 2128 u8 write[0x1]; 2129 u8 requestor[0x1]; 2130 u8 qp_number[0x18]; 2131 }; 2132 2133 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2134 u8 bytes_committed[0x20]; 2135 2136 u8 reserved_at_20[0x10]; 2137 u8 wqe_index[0x10]; 2138 2139 u8 reserved_at_40[0x10]; 2140 u8 len[0x10]; 2141 2142 u8 reserved_at_60[0x60]; 2143 2144 u8 reserved_at_c0[0x5]; 2145 u8 rdma[0x1]; 2146 u8 write_read[0x1]; 2147 u8 requestor[0x1]; 2148 u8 qpn[0x18]; 2149 }; 2150 2151 struct mlx5_ifc_qp_events_bits { 2152 u8 reserved_at_0[0xa0]; 2153 2154 u8 type[0x8]; 2155 u8 reserved_at_a8[0x18]; 2156 2157 u8 reserved_at_c0[0x8]; 2158 u8 qpn_rqn_sqn[0x18]; 2159 }; 2160 2161 struct mlx5_ifc_dct_events_bits { 2162 u8 reserved_at_0[0xc0]; 2163 2164 u8 reserved_at_c0[0x8]; 2165 u8 dct_number[0x18]; 2166 }; 2167 2168 struct mlx5_ifc_comp_event_bits { 2169 u8 reserved_at_0[0xc0]; 2170 2171 u8 reserved_at_c0[0x8]; 2172 u8 cq_number[0x18]; 2173 }; 2174 2175 enum { 2176 MLX5_QPC_STATE_RST = 0x0, 2177 MLX5_QPC_STATE_INIT = 0x1, 2178 MLX5_QPC_STATE_RTR = 0x2, 2179 MLX5_QPC_STATE_RTS = 0x3, 2180 MLX5_QPC_STATE_SQER = 0x4, 2181 MLX5_QPC_STATE_ERR = 0x6, 2182 MLX5_QPC_STATE_SQD = 0x7, 2183 MLX5_QPC_STATE_SUSPENDED = 0x9, 2184 }; 2185 2186 enum { 2187 MLX5_QPC_ST_RC = 0x0, 2188 MLX5_QPC_ST_UC = 0x1, 2189 MLX5_QPC_ST_UD = 0x2, 2190 MLX5_QPC_ST_XRC = 0x3, 2191 MLX5_QPC_ST_DCI = 0x5, 2192 MLX5_QPC_ST_QP0 = 0x7, 2193 MLX5_QPC_ST_QP1 = 0x8, 2194 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2195 MLX5_QPC_ST_REG_UMR = 0xc, 2196 }; 2197 2198 enum { 2199 MLX5_QPC_PM_STATE_ARMED = 0x0, 2200 MLX5_QPC_PM_STATE_REARM = 0x1, 2201 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2202 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2203 }; 2204 2205 enum { 2206 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2207 }; 2208 2209 enum { 2210 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2211 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2212 }; 2213 2214 enum { 2215 MLX5_QPC_MTU_256_BYTES = 0x1, 2216 MLX5_QPC_MTU_512_BYTES = 0x2, 2217 MLX5_QPC_MTU_1K_BYTES = 0x3, 2218 MLX5_QPC_MTU_2K_BYTES = 0x4, 2219 MLX5_QPC_MTU_4K_BYTES = 0x5, 2220 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2221 }; 2222 2223 enum { 2224 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2225 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2226 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2227 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2228 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2229 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2230 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2231 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2232 }; 2233 2234 enum { 2235 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2236 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2237 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2238 }; 2239 2240 enum { 2241 MLX5_QPC_CS_RES_DISABLE = 0x0, 2242 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2243 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2244 }; 2245 2246 struct mlx5_ifc_qpc_bits { 2247 u8 state[0x4]; 2248 u8 lag_tx_port_affinity[0x4]; 2249 u8 st[0x8]; 2250 u8 reserved_at_10[0x3]; 2251 u8 pm_state[0x2]; 2252 u8 reserved_at_15[0x3]; 2253 u8 offload_type[0x4]; 2254 u8 end_padding_mode[0x2]; 2255 u8 reserved_at_1e[0x2]; 2256 2257 u8 wq_signature[0x1]; 2258 u8 block_lb_mc[0x1]; 2259 u8 atomic_like_write_en[0x1]; 2260 u8 latency_sensitive[0x1]; 2261 u8 reserved_at_24[0x1]; 2262 u8 drain_sigerr[0x1]; 2263 u8 reserved_at_26[0x2]; 2264 u8 pd[0x18]; 2265 2266 u8 mtu[0x3]; 2267 u8 log_msg_max[0x5]; 2268 u8 reserved_at_48[0x1]; 2269 u8 log_rq_size[0x4]; 2270 u8 log_rq_stride[0x3]; 2271 u8 no_sq[0x1]; 2272 u8 log_sq_size[0x4]; 2273 u8 reserved_at_55[0x6]; 2274 u8 rlky[0x1]; 2275 u8 ulp_stateless_offload_mode[0x4]; 2276 2277 u8 counter_set_id[0x8]; 2278 u8 uar_page[0x18]; 2279 2280 u8 reserved_at_80[0x8]; 2281 u8 user_index[0x18]; 2282 2283 u8 reserved_at_a0[0x3]; 2284 u8 log_page_size[0x5]; 2285 u8 remote_qpn[0x18]; 2286 2287 struct mlx5_ifc_ads_bits primary_address_path; 2288 2289 struct mlx5_ifc_ads_bits secondary_address_path; 2290 2291 u8 log_ack_req_freq[0x4]; 2292 u8 reserved_at_384[0x4]; 2293 u8 log_sra_max[0x3]; 2294 u8 reserved_at_38b[0x2]; 2295 u8 retry_count[0x3]; 2296 u8 rnr_retry[0x3]; 2297 u8 reserved_at_393[0x1]; 2298 u8 fre[0x1]; 2299 u8 cur_rnr_retry[0x3]; 2300 u8 cur_retry_count[0x3]; 2301 u8 reserved_at_39b[0x5]; 2302 2303 u8 reserved_at_3a0[0x20]; 2304 2305 u8 reserved_at_3c0[0x8]; 2306 u8 next_send_psn[0x18]; 2307 2308 u8 reserved_at_3e0[0x8]; 2309 u8 cqn_snd[0x18]; 2310 2311 u8 reserved_at_400[0x8]; 2312 u8 deth_sqpn[0x18]; 2313 2314 u8 reserved_at_420[0x20]; 2315 2316 u8 reserved_at_440[0x8]; 2317 u8 last_acked_psn[0x18]; 2318 2319 u8 reserved_at_460[0x8]; 2320 u8 ssn[0x18]; 2321 2322 u8 reserved_at_480[0x8]; 2323 u8 log_rra_max[0x3]; 2324 u8 reserved_at_48b[0x1]; 2325 u8 atomic_mode[0x4]; 2326 u8 rre[0x1]; 2327 u8 rwe[0x1]; 2328 u8 rae[0x1]; 2329 u8 reserved_at_493[0x1]; 2330 u8 page_offset[0x6]; 2331 u8 reserved_at_49a[0x3]; 2332 u8 cd_slave_receive[0x1]; 2333 u8 cd_slave_send[0x1]; 2334 u8 cd_master[0x1]; 2335 2336 u8 reserved_at_4a0[0x3]; 2337 u8 min_rnr_nak[0x5]; 2338 u8 next_rcv_psn[0x18]; 2339 2340 u8 reserved_at_4c0[0x8]; 2341 u8 xrcd[0x18]; 2342 2343 u8 reserved_at_4e0[0x8]; 2344 u8 cqn_rcv[0x18]; 2345 2346 u8 dbr_addr[0x40]; 2347 2348 u8 q_key[0x20]; 2349 2350 u8 reserved_at_560[0x5]; 2351 u8 rq_type[0x3]; 2352 u8 srqn_rmpn_xrqn[0x18]; 2353 2354 u8 reserved_at_580[0x8]; 2355 u8 rmsn[0x18]; 2356 2357 u8 hw_sq_wqebb_counter[0x10]; 2358 u8 sw_sq_wqebb_counter[0x10]; 2359 2360 u8 hw_rq_counter[0x20]; 2361 2362 u8 sw_rq_counter[0x20]; 2363 2364 u8 reserved_at_600[0x20]; 2365 2366 u8 reserved_at_620[0xf]; 2367 u8 cgs[0x1]; 2368 u8 cs_req[0x8]; 2369 u8 cs_res[0x8]; 2370 2371 u8 dc_access_key[0x40]; 2372 2373 u8 reserved_at_680[0x3]; 2374 u8 dbr_umem_valid[0x1]; 2375 2376 u8 reserved_at_684[0xbc]; 2377 }; 2378 2379 struct mlx5_ifc_roce_addr_layout_bits { 2380 u8 source_l3_address[16][0x8]; 2381 2382 u8 reserved_at_80[0x3]; 2383 u8 vlan_valid[0x1]; 2384 u8 vlan_id[0xc]; 2385 u8 source_mac_47_32[0x10]; 2386 2387 u8 source_mac_31_0[0x20]; 2388 2389 u8 reserved_at_c0[0x14]; 2390 u8 roce_l3_type[0x4]; 2391 u8 roce_version[0x8]; 2392 2393 u8 reserved_at_e0[0x20]; 2394 }; 2395 2396 union mlx5_ifc_hca_cap_union_bits { 2397 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2398 struct mlx5_ifc_odp_cap_bits odp_cap; 2399 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2400 struct mlx5_ifc_roce_cap_bits roce_cap; 2401 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2402 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2403 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2404 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2405 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2406 struct mlx5_ifc_qos_cap_bits qos_cap; 2407 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2408 u8 reserved_at_0[0x8000]; 2409 }; 2410 2411 enum { 2412 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2413 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2414 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2415 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2416 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2417 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2418 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2419 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2420 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2421 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2422 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2423 }; 2424 2425 struct mlx5_ifc_vlan_bits { 2426 u8 ethtype[0x10]; 2427 u8 prio[0x3]; 2428 u8 cfi[0x1]; 2429 u8 vid[0xc]; 2430 }; 2431 2432 struct mlx5_ifc_flow_context_bits { 2433 struct mlx5_ifc_vlan_bits push_vlan; 2434 2435 u8 group_id[0x20]; 2436 2437 u8 reserved_at_40[0x8]; 2438 u8 flow_tag[0x18]; 2439 2440 u8 reserved_at_60[0x10]; 2441 u8 action[0x10]; 2442 2443 u8 reserved_at_80[0x8]; 2444 u8 destination_list_size[0x18]; 2445 2446 u8 reserved_at_a0[0x8]; 2447 u8 flow_counter_list_size[0x18]; 2448 2449 u8 packet_reformat_id[0x20]; 2450 2451 u8 modify_header_id[0x20]; 2452 2453 struct mlx5_ifc_vlan_bits push_vlan_2; 2454 2455 u8 reserved_at_120[0xe0]; 2456 2457 struct mlx5_ifc_fte_match_param_bits match_value; 2458 2459 u8 reserved_at_1200[0x600]; 2460 2461 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2462 }; 2463 2464 enum { 2465 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2466 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2467 }; 2468 2469 struct mlx5_ifc_xrc_srqc_bits { 2470 u8 state[0x4]; 2471 u8 log_xrc_srq_size[0x4]; 2472 u8 reserved_at_8[0x18]; 2473 2474 u8 wq_signature[0x1]; 2475 u8 cont_srq[0x1]; 2476 u8 dbr_umem_valid[0x1]; 2477 u8 rlky[0x1]; 2478 u8 basic_cyclic_rcv_wqe[0x1]; 2479 u8 log_rq_stride[0x3]; 2480 u8 xrcd[0x18]; 2481 2482 u8 page_offset[0x6]; 2483 u8 reserved_at_46[0x2]; 2484 u8 cqn[0x18]; 2485 2486 u8 reserved_at_60[0x20]; 2487 2488 u8 user_index_equal_xrc_srqn[0x1]; 2489 u8 reserved_at_81[0x1]; 2490 u8 log_page_size[0x6]; 2491 u8 user_index[0x18]; 2492 2493 u8 reserved_at_a0[0x20]; 2494 2495 u8 reserved_at_c0[0x8]; 2496 u8 pd[0x18]; 2497 2498 u8 lwm[0x10]; 2499 u8 wqe_cnt[0x10]; 2500 2501 u8 reserved_at_100[0x40]; 2502 2503 u8 db_record_addr_h[0x20]; 2504 2505 u8 db_record_addr_l[0x1e]; 2506 u8 reserved_at_17e[0x2]; 2507 2508 u8 reserved_at_180[0x80]; 2509 }; 2510 2511 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2512 u8 counter_error_queues[0x20]; 2513 2514 u8 total_error_queues[0x20]; 2515 2516 u8 send_queue_priority_update_flow[0x20]; 2517 2518 u8 reserved_at_60[0x20]; 2519 2520 u8 nic_receive_steering_discard[0x40]; 2521 2522 u8 receive_discard_vport_down[0x40]; 2523 2524 u8 transmit_discard_vport_down[0x40]; 2525 2526 u8 reserved_at_140[0xec0]; 2527 }; 2528 2529 struct mlx5_ifc_traffic_counter_bits { 2530 u8 packets[0x40]; 2531 2532 u8 octets[0x40]; 2533 }; 2534 2535 struct mlx5_ifc_tisc_bits { 2536 u8 strict_lag_tx_port_affinity[0x1]; 2537 u8 reserved_at_1[0x3]; 2538 u8 lag_tx_port_affinity[0x04]; 2539 2540 u8 reserved_at_8[0x4]; 2541 u8 prio[0x4]; 2542 u8 reserved_at_10[0x10]; 2543 2544 u8 reserved_at_20[0x100]; 2545 2546 u8 reserved_at_120[0x8]; 2547 u8 transport_domain[0x18]; 2548 2549 u8 reserved_at_140[0x8]; 2550 u8 underlay_qpn[0x18]; 2551 u8 reserved_at_160[0x3a0]; 2552 }; 2553 2554 enum { 2555 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2556 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2557 }; 2558 2559 enum { 2560 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2561 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2562 }; 2563 2564 enum { 2565 MLX5_RX_HASH_FN_NONE = 0x0, 2566 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2567 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2568 }; 2569 2570 enum { 2571 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2572 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2573 }; 2574 2575 struct mlx5_ifc_tirc_bits { 2576 u8 reserved_at_0[0x20]; 2577 2578 u8 disp_type[0x4]; 2579 u8 reserved_at_24[0x1c]; 2580 2581 u8 reserved_at_40[0x40]; 2582 2583 u8 reserved_at_80[0x4]; 2584 u8 lro_timeout_period_usecs[0x10]; 2585 u8 lro_enable_mask[0x4]; 2586 u8 lro_max_ip_payload_size[0x8]; 2587 2588 u8 reserved_at_a0[0x40]; 2589 2590 u8 reserved_at_e0[0x8]; 2591 u8 inline_rqn[0x18]; 2592 2593 u8 rx_hash_symmetric[0x1]; 2594 u8 reserved_at_101[0x1]; 2595 u8 tunneled_offload_en[0x1]; 2596 u8 reserved_at_103[0x5]; 2597 u8 indirect_table[0x18]; 2598 2599 u8 rx_hash_fn[0x4]; 2600 u8 reserved_at_124[0x2]; 2601 u8 self_lb_block[0x2]; 2602 u8 transport_domain[0x18]; 2603 2604 u8 rx_hash_toeplitz_key[10][0x20]; 2605 2606 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2607 2608 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2609 2610 u8 reserved_at_2c0[0x4c0]; 2611 }; 2612 2613 enum { 2614 MLX5_SRQC_STATE_GOOD = 0x0, 2615 MLX5_SRQC_STATE_ERROR = 0x1, 2616 }; 2617 2618 struct mlx5_ifc_srqc_bits { 2619 u8 state[0x4]; 2620 u8 log_srq_size[0x4]; 2621 u8 reserved_at_8[0x18]; 2622 2623 u8 wq_signature[0x1]; 2624 u8 cont_srq[0x1]; 2625 u8 reserved_at_22[0x1]; 2626 u8 rlky[0x1]; 2627 u8 reserved_at_24[0x1]; 2628 u8 log_rq_stride[0x3]; 2629 u8 xrcd[0x18]; 2630 2631 u8 page_offset[0x6]; 2632 u8 reserved_at_46[0x2]; 2633 u8 cqn[0x18]; 2634 2635 u8 reserved_at_60[0x20]; 2636 2637 u8 reserved_at_80[0x2]; 2638 u8 log_page_size[0x6]; 2639 u8 reserved_at_88[0x18]; 2640 2641 u8 reserved_at_a0[0x20]; 2642 2643 u8 reserved_at_c0[0x8]; 2644 u8 pd[0x18]; 2645 2646 u8 lwm[0x10]; 2647 u8 wqe_cnt[0x10]; 2648 2649 u8 reserved_at_100[0x40]; 2650 2651 u8 dbr_addr[0x40]; 2652 2653 u8 reserved_at_180[0x80]; 2654 }; 2655 2656 enum { 2657 MLX5_SQC_STATE_RST = 0x0, 2658 MLX5_SQC_STATE_RDY = 0x1, 2659 MLX5_SQC_STATE_ERR = 0x3, 2660 }; 2661 2662 struct mlx5_ifc_sqc_bits { 2663 u8 rlky[0x1]; 2664 u8 cd_master[0x1]; 2665 u8 fre[0x1]; 2666 u8 flush_in_error_en[0x1]; 2667 u8 allow_multi_pkt_send_wqe[0x1]; 2668 u8 min_wqe_inline_mode[0x3]; 2669 u8 state[0x4]; 2670 u8 reg_umr[0x1]; 2671 u8 allow_swp[0x1]; 2672 u8 hairpin[0x1]; 2673 u8 reserved_at_f[0x11]; 2674 2675 u8 reserved_at_20[0x8]; 2676 u8 user_index[0x18]; 2677 2678 u8 reserved_at_40[0x8]; 2679 u8 cqn[0x18]; 2680 2681 u8 reserved_at_60[0x8]; 2682 u8 hairpin_peer_rq[0x18]; 2683 2684 u8 reserved_at_80[0x10]; 2685 u8 hairpin_peer_vhca[0x10]; 2686 2687 u8 reserved_at_a0[0x50]; 2688 2689 u8 packet_pacing_rate_limit_index[0x10]; 2690 u8 tis_lst_sz[0x10]; 2691 u8 reserved_at_110[0x10]; 2692 2693 u8 reserved_at_120[0x40]; 2694 2695 u8 reserved_at_160[0x8]; 2696 u8 tis_num_0[0x18]; 2697 2698 struct mlx5_ifc_wq_bits wq; 2699 }; 2700 2701 enum { 2702 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2703 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2704 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2705 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2706 }; 2707 2708 struct mlx5_ifc_scheduling_context_bits { 2709 u8 element_type[0x8]; 2710 u8 reserved_at_8[0x18]; 2711 2712 u8 element_attributes[0x20]; 2713 2714 u8 parent_element_id[0x20]; 2715 2716 u8 reserved_at_60[0x40]; 2717 2718 u8 bw_share[0x20]; 2719 2720 u8 max_average_bw[0x20]; 2721 2722 u8 reserved_at_e0[0x120]; 2723 }; 2724 2725 struct mlx5_ifc_rqtc_bits { 2726 u8 reserved_at_0[0xa0]; 2727 2728 u8 reserved_at_a0[0x10]; 2729 u8 rqt_max_size[0x10]; 2730 2731 u8 reserved_at_c0[0x10]; 2732 u8 rqt_actual_size[0x10]; 2733 2734 u8 reserved_at_e0[0x6a0]; 2735 2736 struct mlx5_ifc_rq_num_bits rq_num[0]; 2737 }; 2738 2739 enum { 2740 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2741 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2742 }; 2743 2744 enum { 2745 MLX5_RQC_STATE_RST = 0x0, 2746 MLX5_RQC_STATE_RDY = 0x1, 2747 MLX5_RQC_STATE_ERR = 0x3, 2748 }; 2749 2750 struct mlx5_ifc_rqc_bits { 2751 u8 rlky[0x1]; 2752 u8 delay_drop_en[0x1]; 2753 u8 scatter_fcs[0x1]; 2754 u8 vsd[0x1]; 2755 u8 mem_rq_type[0x4]; 2756 u8 state[0x4]; 2757 u8 reserved_at_c[0x1]; 2758 u8 flush_in_error_en[0x1]; 2759 u8 hairpin[0x1]; 2760 u8 reserved_at_f[0x11]; 2761 2762 u8 reserved_at_20[0x8]; 2763 u8 user_index[0x18]; 2764 2765 u8 reserved_at_40[0x8]; 2766 u8 cqn[0x18]; 2767 2768 u8 counter_set_id[0x8]; 2769 u8 reserved_at_68[0x18]; 2770 2771 u8 reserved_at_80[0x8]; 2772 u8 rmpn[0x18]; 2773 2774 u8 reserved_at_a0[0x8]; 2775 u8 hairpin_peer_sq[0x18]; 2776 2777 u8 reserved_at_c0[0x10]; 2778 u8 hairpin_peer_vhca[0x10]; 2779 2780 u8 reserved_at_e0[0xa0]; 2781 2782 struct mlx5_ifc_wq_bits wq; 2783 }; 2784 2785 enum { 2786 MLX5_RMPC_STATE_RDY = 0x1, 2787 MLX5_RMPC_STATE_ERR = 0x3, 2788 }; 2789 2790 struct mlx5_ifc_rmpc_bits { 2791 u8 reserved_at_0[0x8]; 2792 u8 state[0x4]; 2793 u8 reserved_at_c[0x14]; 2794 2795 u8 basic_cyclic_rcv_wqe[0x1]; 2796 u8 reserved_at_21[0x1f]; 2797 2798 u8 reserved_at_40[0x140]; 2799 2800 struct mlx5_ifc_wq_bits wq; 2801 }; 2802 2803 struct mlx5_ifc_nic_vport_context_bits { 2804 u8 reserved_at_0[0x5]; 2805 u8 min_wqe_inline_mode[0x3]; 2806 u8 reserved_at_8[0x15]; 2807 u8 disable_mc_local_lb[0x1]; 2808 u8 disable_uc_local_lb[0x1]; 2809 u8 roce_en[0x1]; 2810 2811 u8 arm_change_event[0x1]; 2812 u8 reserved_at_21[0x1a]; 2813 u8 event_on_mtu[0x1]; 2814 u8 event_on_promisc_change[0x1]; 2815 u8 event_on_vlan_change[0x1]; 2816 u8 event_on_mc_address_change[0x1]; 2817 u8 event_on_uc_address_change[0x1]; 2818 2819 u8 reserved_at_40[0xc]; 2820 2821 u8 affiliation_criteria[0x4]; 2822 u8 affiliated_vhca_id[0x10]; 2823 2824 u8 reserved_at_60[0xd0]; 2825 2826 u8 mtu[0x10]; 2827 2828 u8 system_image_guid[0x40]; 2829 u8 port_guid[0x40]; 2830 u8 node_guid[0x40]; 2831 2832 u8 reserved_at_200[0x140]; 2833 u8 qkey_violation_counter[0x10]; 2834 u8 reserved_at_350[0x430]; 2835 2836 u8 promisc_uc[0x1]; 2837 u8 promisc_mc[0x1]; 2838 u8 promisc_all[0x1]; 2839 u8 reserved_at_783[0x2]; 2840 u8 allowed_list_type[0x3]; 2841 u8 reserved_at_788[0xc]; 2842 u8 allowed_list_size[0xc]; 2843 2844 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2845 2846 u8 reserved_at_7e0[0x20]; 2847 2848 u8 current_uc_mac_address[0][0x40]; 2849 }; 2850 2851 enum { 2852 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2853 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2854 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2855 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2856 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2857 }; 2858 2859 struct mlx5_ifc_mkc_bits { 2860 u8 reserved_at_0[0x1]; 2861 u8 free[0x1]; 2862 u8 reserved_at_2[0x1]; 2863 u8 access_mode_4_2[0x3]; 2864 u8 reserved_at_6[0x7]; 2865 u8 relaxed_ordering_write[0x1]; 2866 u8 reserved_at_e[0x1]; 2867 u8 small_fence_on_rdma_read_response[0x1]; 2868 u8 umr_en[0x1]; 2869 u8 a[0x1]; 2870 u8 rw[0x1]; 2871 u8 rr[0x1]; 2872 u8 lw[0x1]; 2873 u8 lr[0x1]; 2874 u8 access_mode_1_0[0x2]; 2875 u8 reserved_at_18[0x8]; 2876 2877 u8 qpn[0x18]; 2878 u8 mkey_7_0[0x8]; 2879 2880 u8 reserved_at_40[0x20]; 2881 2882 u8 length64[0x1]; 2883 u8 bsf_en[0x1]; 2884 u8 sync_umr[0x1]; 2885 u8 reserved_at_63[0x2]; 2886 u8 expected_sigerr_count[0x1]; 2887 u8 reserved_at_66[0x1]; 2888 u8 en_rinval[0x1]; 2889 u8 pd[0x18]; 2890 2891 u8 start_addr[0x40]; 2892 2893 u8 len[0x40]; 2894 2895 u8 bsf_octword_size[0x20]; 2896 2897 u8 reserved_at_120[0x80]; 2898 2899 u8 translations_octword_size[0x20]; 2900 2901 u8 reserved_at_1c0[0x1b]; 2902 u8 log_page_size[0x5]; 2903 2904 u8 reserved_at_1e0[0x20]; 2905 }; 2906 2907 struct mlx5_ifc_pkey_bits { 2908 u8 reserved_at_0[0x10]; 2909 u8 pkey[0x10]; 2910 }; 2911 2912 struct mlx5_ifc_array128_auto_bits { 2913 u8 array128_auto[16][0x8]; 2914 }; 2915 2916 struct mlx5_ifc_hca_vport_context_bits { 2917 u8 field_select[0x20]; 2918 2919 u8 reserved_at_20[0xe0]; 2920 2921 u8 sm_virt_aware[0x1]; 2922 u8 has_smi[0x1]; 2923 u8 has_raw[0x1]; 2924 u8 grh_required[0x1]; 2925 u8 reserved_at_104[0xc]; 2926 u8 port_physical_state[0x4]; 2927 u8 vport_state_policy[0x4]; 2928 u8 port_state[0x4]; 2929 u8 vport_state[0x4]; 2930 2931 u8 reserved_at_120[0x20]; 2932 2933 u8 system_image_guid[0x40]; 2934 2935 u8 port_guid[0x40]; 2936 2937 u8 node_guid[0x40]; 2938 2939 u8 cap_mask1[0x20]; 2940 2941 u8 cap_mask1_field_select[0x20]; 2942 2943 u8 cap_mask2[0x20]; 2944 2945 u8 cap_mask2_field_select[0x20]; 2946 2947 u8 reserved_at_280[0x80]; 2948 2949 u8 lid[0x10]; 2950 u8 reserved_at_310[0x4]; 2951 u8 init_type_reply[0x4]; 2952 u8 lmc[0x3]; 2953 u8 subnet_timeout[0x5]; 2954 2955 u8 sm_lid[0x10]; 2956 u8 sm_sl[0x4]; 2957 u8 reserved_at_334[0xc]; 2958 2959 u8 qkey_violation_counter[0x10]; 2960 u8 pkey_violation_counter[0x10]; 2961 2962 u8 reserved_at_360[0xca0]; 2963 }; 2964 2965 struct mlx5_ifc_esw_vport_context_bits { 2966 u8 reserved_at_0[0x3]; 2967 u8 vport_svlan_strip[0x1]; 2968 u8 vport_cvlan_strip[0x1]; 2969 u8 vport_svlan_insert[0x1]; 2970 u8 vport_cvlan_insert[0x2]; 2971 u8 reserved_at_8[0x18]; 2972 2973 u8 reserved_at_20[0x20]; 2974 2975 u8 svlan_cfi[0x1]; 2976 u8 svlan_pcp[0x3]; 2977 u8 svlan_id[0xc]; 2978 u8 cvlan_cfi[0x1]; 2979 u8 cvlan_pcp[0x3]; 2980 u8 cvlan_id[0xc]; 2981 2982 u8 reserved_at_60[0x7a0]; 2983 }; 2984 2985 enum { 2986 MLX5_EQC_STATUS_OK = 0x0, 2987 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2988 }; 2989 2990 enum { 2991 MLX5_EQC_ST_ARMED = 0x9, 2992 MLX5_EQC_ST_FIRED = 0xa, 2993 }; 2994 2995 struct mlx5_ifc_eqc_bits { 2996 u8 status[0x4]; 2997 u8 reserved_at_4[0x9]; 2998 u8 ec[0x1]; 2999 u8 oi[0x1]; 3000 u8 reserved_at_f[0x5]; 3001 u8 st[0x4]; 3002 u8 reserved_at_18[0x8]; 3003 3004 u8 reserved_at_20[0x20]; 3005 3006 u8 reserved_at_40[0x14]; 3007 u8 page_offset[0x6]; 3008 u8 reserved_at_5a[0x6]; 3009 3010 u8 reserved_at_60[0x3]; 3011 u8 log_eq_size[0x5]; 3012 u8 uar_page[0x18]; 3013 3014 u8 reserved_at_80[0x20]; 3015 3016 u8 reserved_at_a0[0x18]; 3017 u8 intr[0x8]; 3018 3019 u8 reserved_at_c0[0x3]; 3020 u8 log_page_size[0x5]; 3021 u8 reserved_at_c8[0x18]; 3022 3023 u8 reserved_at_e0[0x60]; 3024 3025 u8 reserved_at_140[0x8]; 3026 u8 consumer_counter[0x18]; 3027 3028 u8 reserved_at_160[0x8]; 3029 u8 producer_counter[0x18]; 3030 3031 u8 reserved_at_180[0x80]; 3032 }; 3033 3034 enum { 3035 MLX5_DCTC_STATE_ACTIVE = 0x0, 3036 MLX5_DCTC_STATE_DRAINING = 0x1, 3037 MLX5_DCTC_STATE_DRAINED = 0x2, 3038 }; 3039 3040 enum { 3041 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3042 MLX5_DCTC_CS_RES_NA = 0x1, 3043 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3044 }; 3045 3046 enum { 3047 MLX5_DCTC_MTU_256_BYTES = 0x1, 3048 MLX5_DCTC_MTU_512_BYTES = 0x2, 3049 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3050 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3051 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3052 }; 3053 3054 struct mlx5_ifc_dctc_bits { 3055 u8 reserved_at_0[0x4]; 3056 u8 state[0x4]; 3057 u8 reserved_at_8[0x18]; 3058 3059 u8 reserved_at_20[0x8]; 3060 u8 user_index[0x18]; 3061 3062 u8 reserved_at_40[0x8]; 3063 u8 cqn[0x18]; 3064 3065 u8 counter_set_id[0x8]; 3066 u8 atomic_mode[0x4]; 3067 u8 rre[0x1]; 3068 u8 rwe[0x1]; 3069 u8 rae[0x1]; 3070 u8 atomic_like_write_en[0x1]; 3071 u8 latency_sensitive[0x1]; 3072 u8 rlky[0x1]; 3073 u8 free_ar[0x1]; 3074 u8 reserved_at_73[0xd]; 3075 3076 u8 reserved_at_80[0x8]; 3077 u8 cs_res[0x8]; 3078 u8 reserved_at_90[0x3]; 3079 u8 min_rnr_nak[0x5]; 3080 u8 reserved_at_98[0x8]; 3081 3082 u8 reserved_at_a0[0x8]; 3083 u8 srqn_xrqn[0x18]; 3084 3085 u8 reserved_at_c0[0x8]; 3086 u8 pd[0x18]; 3087 3088 u8 tclass[0x8]; 3089 u8 reserved_at_e8[0x4]; 3090 u8 flow_label[0x14]; 3091 3092 u8 dc_access_key[0x40]; 3093 3094 u8 reserved_at_140[0x5]; 3095 u8 mtu[0x3]; 3096 u8 port[0x8]; 3097 u8 pkey_index[0x10]; 3098 3099 u8 reserved_at_160[0x8]; 3100 u8 my_addr_index[0x8]; 3101 u8 reserved_at_170[0x8]; 3102 u8 hop_limit[0x8]; 3103 3104 u8 dc_access_key_violation_count[0x20]; 3105 3106 u8 reserved_at_1a0[0x14]; 3107 u8 dei_cfi[0x1]; 3108 u8 eth_prio[0x3]; 3109 u8 ecn[0x2]; 3110 u8 dscp[0x6]; 3111 3112 u8 reserved_at_1c0[0x40]; 3113 }; 3114 3115 enum { 3116 MLX5_CQC_STATUS_OK = 0x0, 3117 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3118 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3119 }; 3120 3121 enum { 3122 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3123 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3124 }; 3125 3126 enum { 3127 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3128 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3129 MLX5_CQC_ST_FIRED = 0xa, 3130 }; 3131 3132 enum { 3133 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3134 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3135 MLX5_CQ_PERIOD_NUM_MODES 3136 }; 3137 3138 struct mlx5_ifc_cqc_bits { 3139 u8 status[0x4]; 3140 u8 reserved_at_4[0x2]; 3141 u8 dbr_umem_valid[0x1]; 3142 u8 reserved_at_7[0x1]; 3143 u8 cqe_sz[0x3]; 3144 u8 cc[0x1]; 3145 u8 reserved_at_c[0x1]; 3146 u8 scqe_break_moderation_en[0x1]; 3147 u8 oi[0x1]; 3148 u8 cq_period_mode[0x2]; 3149 u8 cqe_comp_en[0x1]; 3150 u8 mini_cqe_res_format[0x2]; 3151 u8 st[0x4]; 3152 u8 reserved_at_18[0x8]; 3153 3154 u8 reserved_at_20[0x20]; 3155 3156 u8 reserved_at_40[0x14]; 3157 u8 page_offset[0x6]; 3158 u8 reserved_at_5a[0x6]; 3159 3160 u8 reserved_at_60[0x3]; 3161 u8 log_cq_size[0x5]; 3162 u8 uar_page[0x18]; 3163 3164 u8 reserved_at_80[0x4]; 3165 u8 cq_period[0xc]; 3166 u8 cq_max_count[0x10]; 3167 3168 u8 reserved_at_a0[0x18]; 3169 u8 c_eqn[0x8]; 3170 3171 u8 reserved_at_c0[0x3]; 3172 u8 log_page_size[0x5]; 3173 u8 reserved_at_c8[0x18]; 3174 3175 u8 reserved_at_e0[0x20]; 3176 3177 u8 reserved_at_100[0x8]; 3178 u8 last_notified_index[0x18]; 3179 3180 u8 reserved_at_120[0x8]; 3181 u8 last_solicit_index[0x18]; 3182 3183 u8 reserved_at_140[0x8]; 3184 u8 consumer_counter[0x18]; 3185 3186 u8 reserved_at_160[0x8]; 3187 u8 producer_counter[0x18]; 3188 3189 u8 reserved_at_180[0x40]; 3190 3191 u8 dbr_addr[0x40]; 3192 }; 3193 3194 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3195 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3196 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3197 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3198 u8 reserved_at_0[0x800]; 3199 }; 3200 3201 struct mlx5_ifc_query_adapter_param_block_bits { 3202 u8 reserved_at_0[0xc0]; 3203 3204 u8 reserved_at_c0[0x8]; 3205 u8 ieee_vendor_id[0x18]; 3206 3207 u8 reserved_at_e0[0x10]; 3208 u8 vsd_vendor_id[0x10]; 3209 3210 u8 vsd[208][0x8]; 3211 3212 u8 vsd_contd_psid[16][0x8]; 3213 }; 3214 3215 enum { 3216 MLX5_XRQC_STATE_GOOD = 0x0, 3217 MLX5_XRQC_STATE_ERROR = 0x1, 3218 }; 3219 3220 enum { 3221 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3222 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3223 }; 3224 3225 enum { 3226 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3227 }; 3228 3229 struct mlx5_ifc_tag_matching_topology_context_bits { 3230 u8 log_matching_list_sz[0x4]; 3231 u8 reserved_at_4[0xc]; 3232 u8 append_next_index[0x10]; 3233 3234 u8 sw_phase_cnt[0x10]; 3235 u8 hw_phase_cnt[0x10]; 3236 3237 u8 reserved_at_40[0x40]; 3238 }; 3239 3240 struct mlx5_ifc_xrqc_bits { 3241 u8 state[0x4]; 3242 u8 rlkey[0x1]; 3243 u8 reserved_at_5[0xf]; 3244 u8 topology[0x4]; 3245 u8 reserved_at_18[0x4]; 3246 u8 offload[0x4]; 3247 3248 u8 reserved_at_20[0x8]; 3249 u8 user_index[0x18]; 3250 3251 u8 reserved_at_40[0x8]; 3252 u8 cqn[0x18]; 3253 3254 u8 reserved_at_60[0xa0]; 3255 3256 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3257 3258 u8 reserved_at_180[0x280]; 3259 3260 struct mlx5_ifc_wq_bits wq; 3261 }; 3262 3263 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3264 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3265 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3266 u8 reserved_at_0[0x20]; 3267 }; 3268 3269 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3270 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3271 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3272 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3273 u8 reserved_at_0[0x20]; 3274 }; 3275 3276 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3277 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3278 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3279 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3280 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3281 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3282 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3283 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3284 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3285 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3286 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3287 u8 reserved_at_0[0x7c0]; 3288 }; 3289 3290 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3291 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3292 u8 reserved_at_0[0x7c0]; 3293 }; 3294 3295 union mlx5_ifc_event_auto_bits { 3296 struct mlx5_ifc_comp_event_bits comp_event; 3297 struct mlx5_ifc_dct_events_bits dct_events; 3298 struct mlx5_ifc_qp_events_bits qp_events; 3299 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3300 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3301 struct mlx5_ifc_cq_error_bits cq_error; 3302 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3303 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3304 struct mlx5_ifc_gpio_event_bits gpio_event; 3305 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3306 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3307 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3308 u8 reserved_at_0[0xe0]; 3309 }; 3310 3311 struct mlx5_ifc_health_buffer_bits { 3312 u8 reserved_at_0[0x100]; 3313 3314 u8 assert_existptr[0x20]; 3315 3316 u8 assert_callra[0x20]; 3317 3318 u8 reserved_at_140[0x40]; 3319 3320 u8 fw_version[0x20]; 3321 3322 u8 hw_id[0x20]; 3323 3324 u8 reserved_at_1c0[0x20]; 3325 3326 u8 irisc_index[0x8]; 3327 u8 synd[0x8]; 3328 u8 ext_synd[0x10]; 3329 }; 3330 3331 struct mlx5_ifc_register_loopback_control_bits { 3332 u8 no_lb[0x1]; 3333 u8 reserved_at_1[0x7]; 3334 u8 port[0x8]; 3335 u8 reserved_at_10[0x10]; 3336 3337 u8 reserved_at_20[0x60]; 3338 }; 3339 3340 struct mlx5_ifc_vport_tc_element_bits { 3341 u8 traffic_class[0x4]; 3342 u8 reserved_at_4[0xc]; 3343 u8 vport_number[0x10]; 3344 }; 3345 3346 struct mlx5_ifc_vport_element_bits { 3347 u8 reserved_at_0[0x10]; 3348 u8 vport_number[0x10]; 3349 }; 3350 3351 enum { 3352 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3353 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3354 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3355 }; 3356 3357 struct mlx5_ifc_tsar_element_bits { 3358 u8 reserved_at_0[0x8]; 3359 u8 tsar_type[0x8]; 3360 u8 reserved_at_10[0x10]; 3361 }; 3362 3363 enum { 3364 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3365 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3366 }; 3367 3368 struct mlx5_ifc_teardown_hca_out_bits { 3369 u8 status[0x8]; 3370 u8 reserved_at_8[0x18]; 3371 3372 u8 syndrome[0x20]; 3373 3374 u8 reserved_at_40[0x3f]; 3375 3376 u8 state[0x1]; 3377 }; 3378 3379 enum { 3380 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3381 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3382 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3383 }; 3384 3385 struct mlx5_ifc_teardown_hca_in_bits { 3386 u8 opcode[0x10]; 3387 u8 reserved_at_10[0x10]; 3388 3389 u8 reserved_at_20[0x10]; 3390 u8 op_mod[0x10]; 3391 3392 u8 reserved_at_40[0x10]; 3393 u8 profile[0x10]; 3394 3395 u8 reserved_at_60[0x20]; 3396 }; 3397 3398 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3399 u8 status[0x8]; 3400 u8 reserved_at_8[0x18]; 3401 3402 u8 syndrome[0x20]; 3403 3404 u8 reserved_at_40[0x40]; 3405 }; 3406 3407 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3408 u8 opcode[0x10]; 3409 u8 uid[0x10]; 3410 3411 u8 reserved_at_20[0x10]; 3412 u8 op_mod[0x10]; 3413 3414 u8 reserved_at_40[0x8]; 3415 u8 qpn[0x18]; 3416 3417 u8 reserved_at_60[0x20]; 3418 3419 u8 opt_param_mask[0x20]; 3420 3421 u8 reserved_at_a0[0x20]; 3422 3423 struct mlx5_ifc_qpc_bits qpc; 3424 3425 u8 reserved_at_800[0x80]; 3426 }; 3427 3428 struct mlx5_ifc_sqd2rts_qp_out_bits { 3429 u8 status[0x8]; 3430 u8 reserved_at_8[0x18]; 3431 3432 u8 syndrome[0x20]; 3433 3434 u8 reserved_at_40[0x40]; 3435 }; 3436 3437 struct mlx5_ifc_sqd2rts_qp_in_bits { 3438 u8 opcode[0x10]; 3439 u8 uid[0x10]; 3440 3441 u8 reserved_at_20[0x10]; 3442 u8 op_mod[0x10]; 3443 3444 u8 reserved_at_40[0x8]; 3445 u8 qpn[0x18]; 3446 3447 u8 reserved_at_60[0x20]; 3448 3449 u8 opt_param_mask[0x20]; 3450 3451 u8 reserved_at_a0[0x20]; 3452 3453 struct mlx5_ifc_qpc_bits qpc; 3454 3455 u8 reserved_at_800[0x80]; 3456 }; 3457 3458 struct mlx5_ifc_set_roce_address_out_bits { 3459 u8 status[0x8]; 3460 u8 reserved_at_8[0x18]; 3461 3462 u8 syndrome[0x20]; 3463 3464 u8 reserved_at_40[0x40]; 3465 }; 3466 3467 struct mlx5_ifc_set_roce_address_in_bits { 3468 u8 opcode[0x10]; 3469 u8 reserved_at_10[0x10]; 3470 3471 u8 reserved_at_20[0x10]; 3472 u8 op_mod[0x10]; 3473 3474 u8 roce_address_index[0x10]; 3475 u8 reserved_at_50[0xc]; 3476 u8 vhca_port_num[0x4]; 3477 3478 u8 reserved_at_60[0x20]; 3479 3480 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3481 }; 3482 3483 struct mlx5_ifc_set_mad_demux_out_bits { 3484 u8 status[0x8]; 3485 u8 reserved_at_8[0x18]; 3486 3487 u8 syndrome[0x20]; 3488 3489 u8 reserved_at_40[0x40]; 3490 }; 3491 3492 enum { 3493 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3494 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3495 }; 3496 3497 struct mlx5_ifc_set_mad_demux_in_bits { 3498 u8 opcode[0x10]; 3499 u8 reserved_at_10[0x10]; 3500 3501 u8 reserved_at_20[0x10]; 3502 u8 op_mod[0x10]; 3503 3504 u8 reserved_at_40[0x20]; 3505 3506 u8 reserved_at_60[0x6]; 3507 u8 demux_mode[0x2]; 3508 u8 reserved_at_68[0x18]; 3509 }; 3510 3511 struct mlx5_ifc_set_l2_table_entry_out_bits { 3512 u8 status[0x8]; 3513 u8 reserved_at_8[0x18]; 3514 3515 u8 syndrome[0x20]; 3516 3517 u8 reserved_at_40[0x40]; 3518 }; 3519 3520 struct mlx5_ifc_set_l2_table_entry_in_bits { 3521 u8 opcode[0x10]; 3522 u8 reserved_at_10[0x10]; 3523 3524 u8 reserved_at_20[0x10]; 3525 u8 op_mod[0x10]; 3526 3527 u8 reserved_at_40[0x60]; 3528 3529 u8 reserved_at_a0[0x8]; 3530 u8 table_index[0x18]; 3531 3532 u8 reserved_at_c0[0x20]; 3533 3534 u8 reserved_at_e0[0x13]; 3535 u8 vlan_valid[0x1]; 3536 u8 vlan[0xc]; 3537 3538 struct mlx5_ifc_mac_address_layout_bits mac_address; 3539 3540 u8 reserved_at_140[0xc0]; 3541 }; 3542 3543 struct mlx5_ifc_set_issi_out_bits { 3544 u8 status[0x8]; 3545 u8 reserved_at_8[0x18]; 3546 3547 u8 syndrome[0x20]; 3548 3549 u8 reserved_at_40[0x40]; 3550 }; 3551 3552 struct mlx5_ifc_set_issi_in_bits { 3553 u8 opcode[0x10]; 3554 u8 reserved_at_10[0x10]; 3555 3556 u8 reserved_at_20[0x10]; 3557 u8 op_mod[0x10]; 3558 3559 u8 reserved_at_40[0x10]; 3560 u8 current_issi[0x10]; 3561 3562 u8 reserved_at_60[0x20]; 3563 }; 3564 3565 struct mlx5_ifc_set_hca_cap_out_bits { 3566 u8 status[0x8]; 3567 u8 reserved_at_8[0x18]; 3568 3569 u8 syndrome[0x20]; 3570 3571 u8 reserved_at_40[0x40]; 3572 }; 3573 3574 struct mlx5_ifc_set_hca_cap_in_bits { 3575 u8 opcode[0x10]; 3576 u8 reserved_at_10[0x10]; 3577 3578 u8 reserved_at_20[0x10]; 3579 u8 op_mod[0x10]; 3580 3581 u8 reserved_at_40[0x40]; 3582 3583 union mlx5_ifc_hca_cap_union_bits capability; 3584 }; 3585 3586 enum { 3587 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3588 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3589 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3590 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3591 }; 3592 3593 struct mlx5_ifc_set_fte_out_bits { 3594 u8 status[0x8]; 3595 u8 reserved_at_8[0x18]; 3596 3597 u8 syndrome[0x20]; 3598 3599 u8 reserved_at_40[0x40]; 3600 }; 3601 3602 struct mlx5_ifc_set_fte_in_bits { 3603 u8 opcode[0x10]; 3604 u8 reserved_at_10[0x10]; 3605 3606 u8 reserved_at_20[0x10]; 3607 u8 op_mod[0x10]; 3608 3609 u8 other_vport[0x1]; 3610 u8 reserved_at_41[0xf]; 3611 u8 vport_number[0x10]; 3612 3613 u8 reserved_at_60[0x20]; 3614 3615 u8 table_type[0x8]; 3616 u8 reserved_at_88[0x18]; 3617 3618 u8 reserved_at_a0[0x8]; 3619 u8 table_id[0x18]; 3620 3621 u8 reserved_at_c0[0x18]; 3622 u8 modify_enable_mask[0x8]; 3623 3624 u8 reserved_at_e0[0x20]; 3625 3626 u8 flow_index[0x20]; 3627 3628 u8 reserved_at_120[0xe0]; 3629 3630 struct mlx5_ifc_flow_context_bits flow_context; 3631 }; 3632 3633 struct mlx5_ifc_rts2rts_qp_out_bits { 3634 u8 status[0x8]; 3635 u8 reserved_at_8[0x18]; 3636 3637 u8 syndrome[0x20]; 3638 3639 u8 reserved_at_40[0x40]; 3640 }; 3641 3642 struct mlx5_ifc_rts2rts_qp_in_bits { 3643 u8 opcode[0x10]; 3644 u8 uid[0x10]; 3645 3646 u8 reserved_at_20[0x10]; 3647 u8 op_mod[0x10]; 3648 3649 u8 reserved_at_40[0x8]; 3650 u8 qpn[0x18]; 3651 3652 u8 reserved_at_60[0x20]; 3653 3654 u8 opt_param_mask[0x20]; 3655 3656 u8 reserved_at_a0[0x20]; 3657 3658 struct mlx5_ifc_qpc_bits qpc; 3659 3660 u8 reserved_at_800[0x80]; 3661 }; 3662 3663 struct mlx5_ifc_rtr2rts_qp_out_bits { 3664 u8 status[0x8]; 3665 u8 reserved_at_8[0x18]; 3666 3667 u8 syndrome[0x20]; 3668 3669 u8 reserved_at_40[0x40]; 3670 }; 3671 3672 struct mlx5_ifc_rtr2rts_qp_in_bits { 3673 u8 opcode[0x10]; 3674 u8 uid[0x10]; 3675 3676 u8 reserved_at_20[0x10]; 3677 u8 op_mod[0x10]; 3678 3679 u8 reserved_at_40[0x8]; 3680 u8 qpn[0x18]; 3681 3682 u8 reserved_at_60[0x20]; 3683 3684 u8 opt_param_mask[0x20]; 3685 3686 u8 reserved_at_a0[0x20]; 3687 3688 struct mlx5_ifc_qpc_bits qpc; 3689 3690 u8 reserved_at_800[0x80]; 3691 }; 3692 3693 struct mlx5_ifc_rst2init_qp_out_bits { 3694 u8 status[0x8]; 3695 u8 reserved_at_8[0x18]; 3696 3697 u8 syndrome[0x20]; 3698 3699 u8 reserved_at_40[0x40]; 3700 }; 3701 3702 struct mlx5_ifc_rst2init_qp_in_bits { 3703 u8 opcode[0x10]; 3704 u8 uid[0x10]; 3705 3706 u8 reserved_at_20[0x10]; 3707 u8 op_mod[0x10]; 3708 3709 u8 reserved_at_40[0x8]; 3710 u8 qpn[0x18]; 3711 3712 u8 reserved_at_60[0x20]; 3713 3714 u8 opt_param_mask[0x20]; 3715 3716 u8 reserved_at_a0[0x20]; 3717 3718 struct mlx5_ifc_qpc_bits qpc; 3719 3720 u8 reserved_at_800[0x80]; 3721 }; 3722 3723 struct mlx5_ifc_query_xrq_out_bits { 3724 u8 status[0x8]; 3725 u8 reserved_at_8[0x18]; 3726 3727 u8 syndrome[0x20]; 3728 3729 u8 reserved_at_40[0x40]; 3730 3731 struct mlx5_ifc_xrqc_bits xrq_context; 3732 }; 3733 3734 struct mlx5_ifc_query_xrq_in_bits { 3735 u8 opcode[0x10]; 3736 u8 reserved_at_10[0x10]; 3737 3738 u8 reserved_at_20[0x10]; 3739 u8 op_mod[0x10]; 3740 3741 u8 reserved_at_40[0x8]; 3742 u8 xrqn[0x18]; 3743 3744 u8 reserved_at_60[0x20]; 3745 }; 3746 3747 struct mlx5_ifc_query_xrc_srq_out_bits { 3748 u8 status[0x8]; 3749 u8 reserved_at_8[0x18]; 3750 3751 u8 syndrome[0x20]; 3752 3753 u8 reserved_at_40[0x40]; 3754 3755 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3756 3757 u8 reserved_at_280[0x600]; 3758 3759 u8 pas[0][0x40]; 3760 }; 3761 3762 struct mlx5_ifc_query_xrc_srq_in_bits { 3763 u8 opcode[0x10]; 3764 u8 reserved_at_10[0x10]; 3765 3766 u8 reserved_at_20[0x10]; 3767 u8 op_mod[0x10]; 3768 3769 u8 reserved_at_40[0x8]; 3770 u8 xrc_srqn[0x18]; 3771 3772 u8 reserved_at_60[0x20]; 3773 }; 3774 3775 enum { 3776 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3777 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3778 }; 3779 3780 struct mlx5_ifc_query_vport_state_out_bits { 3781 u8 status[0x8]; 3782 u8 reserved_at_8[0x18]; 3783 3784 u8 syndrome[0x20]; 3785 3786 u8 reserved_at_40[0x20]; 3787 3788 u8 reserved_at_60[0x18]; 3789 u8 admin_state[0x4]; 3790 u8 state[0x4]; 3791 }; 3792 3793 enum { 3794 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3795 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3796 }; 3797 3798 struct mlx5_ifc_query_vport_state_in_bits { 3799 u8 opcode[0x10]; 3800 u8 reserved_at_10[0x10]; 3801 3802 u8 reserved_at_20[0x10]; 3803 u8 op_mod[0x10]; 3804 3805 u8 other_vport[0x1]; 3806 u8 reserved_at_41[0xf]; 3807 u8 vport_number[0x10]; 3808 3809 u8 reserved_at_60[0x20]; 3810 }; 3811 3812 struct mlx5_ifc_query_vnic_env_out_bits { 3813 u8 status[0x8]; 3814 u8 reserved_at_8[0x18]; 3815 3816 u8 syndrome[0x20]; 3817 3818 u8 reserved_at_40[0x40]; 3819 3820 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3821 }; 3822 3823 enum { 3824 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3825 }; 3826 3827 struct mlx5_ifc_query_vnic_env_in_bits { 3828 u8 opcode[0x10]; 3829 u8 reserved_at_10[0x10]; 3830 3831 u8 reserved_at_20[0x10]; 3832 u8 op_mod[0x10]; 3833 3834 u8 other_vport[0x1]; 3835 u8 reserved_at_41[0xf]; 3836 u8 vport_number[0x10]; 3837 3838 u8 reserved_at_60[0x20]; 3839 }; 3840 3841 struct mlx5_ifc_query_vport_counter_out_bits { 3842 u8 status[0x8]; 3843 u8 reserved_at_8[0x18]; 3844 3845 u8 syndrome[0x20]; 3846 3847 u8 reserved_at_40[0x40]; 3848 3849 struct mlx5_ifc_traffic_counter_bits received_errors; 3850 3851 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3852 3853 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3854 3855 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3856 3857 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3858 3859 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3860 3861 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3862 3863 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3864 3865 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3866 3867 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3868 3869 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3870 3871 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3872 3873 u8 reserved_at_680[0xa00]; 3874 }; 3875 3876 enum { 3877 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3878 }; 3879 3880 struct mlx5_ifc_query_vport_counter_in_bits { 3881 u8 opcode[0x10]; 3882 u8 reserved_at_10[0x10]; 3883 3884 u8 reserved_at_20[0x10]; 3885 u8 op_mod[0x10]; 3886 3887 u8 other_vport[0x1]; 3888 u8 reserved_at_41[0xb]; 3889 u8 port_num[0x4]; 3890 u8 vport_number[0x10]; 3891 3892 u8 reserved_at_60[0x60]; 3893 3894 u8 clear[0x1]; 3895 u8 reserved_at_c1[0x1f]; 3896 3897 u8 reserved_at_e0[0x20]; 3898 }; 3899 3900 struct mlx5_ifc_query_tis_out_bits { 3901 u8 status[0x8]; 3902 u8 reserved_at_8[0x18]; 3903 3904 u8 syndrome[0x20]; 3905 3906 u8 reserved_at_40[0x40]; 3907 3908 struct mlx5_ifc_tisc_bits tis_context; 3909 }; 3910 3911 struct mlx5_ifc_query_tis_in_bits { 3912 u8 opcode[0x10]; 3913 u8 reserved_at_10[0x10]; 3914 3915 u8 reserved_at_20[0x10]; 3916 u8 op_mod[0x10]; 3917 3918 u8 reserved_at_40[0x8]; 3919 u8 tisn[0x18]; 3920 3921 u8 reserved_at_60[0x20]; 3922 }; 3923 3924 struct mlx5_ifc_query_tir_out_bits { 3925 u8 status[0x8]; 3926 u8 reserved_at_8[0x18]; 3927 3928 u8 syndrome[0x20]; 3929 3930 u8 reserved_at_40[0xc0]; 3931 3932 struct mlx5_ifc_tirc_bits tir_context; 3933 }; 3934 3935 struct mlx5_ifc_query_tir_in_bits { 3936 u8 opcode[0x10]; 3937 u8 reserved_at_10[0x10]; 3938 3939 u8 reserved_at_20[0x10]; 3940 u8 op_mod[0x10]; 3941 3942 u8 reserved_at_40[0x8]; 3943 u8 tirn[0x18]; 3944 3945 u8 reserved_at_60[0x20]; 3946 }; 3947 3948 struct mlx5_ifc_query_srq_out_bits { 3949 u8 status[0x8]; 3950 u8 reserved_at_8[0x18]; 3951 3952 u8 syndrome[0x20]; 3953 3954 u8 reserved_at_40[0x40]; 3955 3956 struct mlx5_ifc_srqc_bits srq_context_entry; 3957 3958 u8 reserved_at_280[0x600]; 3959 3960 u8 pas[0][0x40]; 3961 }; 3962 3963 struct mlx5_ifc_query_srq_in_bits { 3964 u8 opcode[0x10]; 3965 u8 reserved_at_10[0x10]; 3966 3967 u8 reserved_at_20[0x10]; 3968 u8 op_mod[0x10]; 3969 3970 u8 reserved_at_40[0x8]; 3971 u8 srqn[0x18]; 3972 3973 u8 reserved_at_60[0x20]; 3974 }; 3975 3976 struct mlx5_ifc_query_sq_out_bits { 3977 u8 status[0x8]; 3978 u8 reserved_at_8[0x18]; 3979 3980 u8 syndrome[0x20]; 3981 3982 u8 reserved_at_40[0xc0]; 3983 3984 struct mlx5_ifc_sqc_bits sq_context; 3985 }; 3986 3987 struct mlx5_ifc_query_sq_in_bits { 3988 u8 opcode[0x10]; 3989 u8 reserved_at_10[0x10]; 3990 3991 u8 reserved_at_20[0x10]; 3992 u8 op_mod[0x10]; 3993 3994 u8 reserved_at_40[0x8]; 3995 u8 sqn[0x18]; 3996 3997 u8 reserved_at_60[0x20]; 3998 }; 3999 4000 struct mlx5_ifc_query_special_contexts_out_bits { 4001 u8 status[0x8]; 4002 u8 reserved_at_8[0x18]; 4003 4004 u8 syndrome[0x20]; 4005 4006 u8 dump_fill_mkey[0x20]; 4007 4008 u8 resd_lkey[0x20]; 4009 4010 u8 null_mkey[0x20]; 4011 4012 u8 reserved_at_a0[0x60]; 4013 }; 4014 4015 struct mlx5_ifc_query_special_contexts_in_bits { 4016 u8 opcode[0x10]; 4017 u8 reserved_at_10[0x10]; 4018 4019 u8 reserved_at_20[0x10]; 4020 u8 op_mod[0x10]; 4021 4022 u8 reserved_at_40[0x40]; 4023 }; 4024 4025 struct mlx5_ifc_query_scheduling_element_out_bits { 4026 u8 opcode[0x10]; 4027 u8 reserved_at_10[0x10]; 4028 4029 u8 reserved_at_20[0x10]; 4030 u8 op_mod[0x10]; 4031 4032 u8 reserved_at_40[0xc0]; 4033 4034 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4035 4036 u8 reserved_at_300[0x100]; 4037 }; 4038 4039 enum { 4040 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4041 }; 4042 4043 struct mlx5_ifc_query_scheduling_element_in_bits { 4044 u8 opcode[0x10]; 4045 u8 reserved_at_10[0x10]; 4046 4047 u8 reserved_at_20[0x10]; 4048 u8 op_mod[0x10]; 4049 4050 u8 scheduling_hierarchy[0x8]; 4051 u8 reserved_at_48[0x18]; 4052 4053 u8 scheduling_element_id[0x20]; 4054 4055 u8 reserved_at_80[0x180]; 4056 }; 4057 4058 struct mlx5_ifc_query_rqt_out_bits { 4059 u8 status[0x8]; 4060 u8 reserved_at_8[0x18]; 4061 4062 u8 syndrome[0x20]; 4063 4064 u8 reserved_at_40[0xc0]; 4065 4066 struct mlx5_ifc_rqtc_bits rqt_context; 4067 }; 4068 4069 struct mlx5_ifc_query_rqt_in_bits { 4070 u8 opcode[0x10]; 4071 u8 reserved_at_10[0x10]; 4072 4073 u8 reserved_at_20[0x10]; 4074 u8 op_mod[0x10]; 4075 4076 u8 reserved_at_40[0x8]; 4077 u8 rqtn[0x18]; 4078 4079 u8 reserved_at_60[0x20]; 4080 }; 4081 4082 struct mlx5_ifc_query_rq_out_bits { 4083 u8 status[0x8]; 4084 u8 reserved_at_8[0x18]; 4085 4086 u8 syndrome[0x20]; 4087 4088 u8 reserved_at_40[0xc0]; 4089 4090 struct mlx5_ifc_rqc_bits rq_context; 4091 }; 4092 4093 struct mlx5_ifc_query_rq_in_bits { 4094 u8 opcode[0x10]; 4095 u8 reserved_at_10[0x10]; 4096 4097 u8 reserved_at_20[0x10]; 4098 u8 op_mod[0x10]; 4099 4100 u8 reserved_at_40[0x8]; 4101 u8 rqn[0x18]; 4102 4103 u8 reserved_at_60[0x20]; 4104 }; 4105 4106 struct mlx5_ifc_query_roce_address_out_bits { 4107 u8 status[0x8]; 4108 u8 reserved_at_8[0x18]; 4109 4110 u8 syndrome[0x20]; 4111 4112 u8 reserved_at_40[0x40]; 4113 4114 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4115 }; 4116 4117 struct mlx5_ifc_query_roce_address_in_bits { 4118 u8 opcode[0x10]; 4119 u8 reserved_at_10[0x10]; 4120 4121 u8 reserved_at_20[0x10]; 4122 u8 op_mod[0x10]; 4123 4124 u8 roce_address_index[0x10]; 4125 u8 reserved_at_50[0xc]; 4126 u8 vhca_port_num[0x4]; 4127 4128 u8 reserved_at_60[0x20]; 4129 }; 4130 4131 struct mlx5_ifc_query_rmp_out_bits { 4132 u8 status[0x8]; 4133 u8 reserved_at_8[0x18]; 4134 4135 u8 syndrome[0x20]; 4136 4137 u8 reserved_at_40[0xc0]; 4138 4139 struct mlx5_ifc_rmpc_bits rmp_context; 4140 }; 4141 4142 struct mlx5_ifc_query_rmp_in_bits { 4143 u8 opcode[0x10]; 4144 u8 reserved_at_10[0x10]; 4145 4146 u8 reserved_at_20[0x10]; 4147 u8 op_mod[0x10]; 4148 4149 u8 reserved_at_40[0x8]; 4150 u8 rmpn[0x18]; 4151 4152 u8 reserved_at_60[0x20]; 4153 }; 4154 4155 struct mlx5_ifc_query_qp_out_bits { 4156 u8 status[0x8]; 4157 u8 reserved_at_8[0x18]; 4158 4159 u8 syndrome[0x20]; 4160 4161 u8 reserved_at_40[0x40]; 4162 4163 u8 opt_param_mask[0x20]; 4164 4165 u8 reserved_at_a0[0x20]; 4166 4167 struct mlx5_ifc_qpc_bits qpc; 4168 4169 u8 reserved_at_800[0x80]; 4170 4171 u8 pas[0][0x40]; 4172 }; 4173 4174 struct mlx5_ifc_query_qp_in_bits { 4175 u8 opcode[0x10]; 4176 u8 reserved_at_10[0x10]; 4177 4178 u8 reserved_at_20[0x10]; 4179 u8 op_mod[0x10]; 4180 4181 u8 reserved_at_40[0x8]; 4182 u8 qpn[0x18]; 4183 4184 u8 reserved_at_60[0x20]; 4185 }; 4186 4187 struct mlx5_ifc_query_q_counter_out_bits { 4188 u8 status[0x8]; 4189 u8 reserved_at_8[0x18]; 4190 4191 u8 syndrome[0x20]; 4192 4193 u8 reserved_at_40[0x40]; 4194 4195 u8 rx_write_requests[0x20]; 4196 4197 u8 reserved_at_a0[0x20]; 4198 4199 u8 rx_read_requests[0x20]; 4200 4201 u8 reserved_at_e0[0x20]; 4202 4203 u8 rx_atomic_requests[0x20]; 4204 4205 u8 reserved_at_120[0x20]; 4206 4207 u8 rx_dct_connect[0x20]; 4208 4209 u8 reserved_at_160[0x20]; 4210 4211 u8 out_of_buffer[0x20]; 4212 4213 u8 reserved_at_1a0[0x20]; 4214 4215 u8 out_of_sequence[0x20]; 4216 4217 u8 reserved_at_1e0[0x20]; 4218 4219 u8 duplicate_request[0x20]; 4220 4221 u8 reserved_at_220[0x20]; 4222 4223 u8 rnr_nak_retry_err[0x20]; 4224 4225 u8 reserved_at_260[0x20]; 4226 4227 u8 packet_seq_err[0x20]; 4228 4229 u8 reserved_at_2a0[0x20]; 4230 4231 u8 implied_nak_seq_err[0x20]; 4232 4233 u8 reserved_at_2e0[0x20]; 4234 4235 u8 local_ack_timeout_err[0x20]; 4236 4237 u8 reserved_at_320[0xa0]; 4238 4239 u8 resp_local_length_error[0x20]; 4240 4241 u8 req_local_length_error[0x20]; 4242 4243 u8 resp_local_qp_error[0x20]; 4244 4245 u8 local_operation_error[0x20]; 4246 4247 u8 resp_local_protection[0x20]; 4248 4249 u8 req_local_protection[0x20]; 4250 4251 u8 resp_cqe_error[0x20]; 4252 4253 u8 req_cqe_error[0x20]; 4254 4255 u8 req_mw_binding[0x20]; 4256 4257 u8 req_bad_response[0x20]; 4258 4259 u8 req_remote_invalid_request[0x20]; 4260 4261 u8 resp_remote_invalid_request[0x20]; 4262 4263 u8 req_remote_access_errors[0x20]; 4264 4265 u8 resp_remote_access_errors[0x20]; 4266 4267 u8 req_remote_operation_errors[0x20]; 4268 4269 u8 req_transport_retries_exceeded[0x20]; 4270 4271 u8 cq_overflow[0x20]; 4272 4273 u8 resp_cqe_flush_error[0x20]; 4274 4275 u8 req_cqe_flush_error[0x20]; 4276 4277 u8 reserved_at_620[0x1e0]; 4278 }; 4279 4280 struct mlx5_ifc_query_q_counter_in_bits { 4281 u8 opcode[0x10]; 4282 u8 reserved_at_10[0x10]; 4283 4284 u8 reserved_at_20[0x10]; 4285 u8 op_mod[0x10]; 4286 4287 u8 reserved_at_40[0x80]; 4288 4289 u8 clear[0x1]; 4290 u8 reserved_at_c1[0x1f]; 4291 4292 u8 reserved_at_e0[0x18]; 4293 u8 counter_set_id[0x8]; 4294 }; 4295 4296 struct mlx5_ifc_query_pages_out_bits { 4297 u8 status[0x8]; 4298 u8 reserved_at_8[0x18]; 4299 4300 u8 syndrome[0x20]; 4301 4302 u8 reserved_at_40[0x10]; 4303 u8 function_id[0x10]; 4304 4305 u8 num_pages[0x20]; 4306 }; 4307 4308 enum { 4309 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4310 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4311 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4312 }; 4313 4314 struct mlx5_ifc_query_pages_in_bits { 4315 u8 opcode[0x10]; 4316 u8 reserved_at_10[0x10]; 4317 4318 u8 reserved_at_20[0x10]; 4319 u8 op_mod[0x10]; 4320 4321 u8 reserved_at_40[0x10]; 4322 u8 function_id[0x10]; 4323 4324 u8 reserved_at_60[0x20]; 4325 }; 4326 4327 struct mlx5_ifc_query_nic_vport_context_out_bits { 4328 u8 status[0x8]; 4329 u8 reserved_at_8[0x18]; 4330 4331 u8 syndrome[0x20]; 4332 4333 u8 reserved_at_40[0x40]; 4334 4335 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4336 }; 4337 4338 struct mlx5_ifc_query_nic_vport_context_in_bits { 4339 u8 opcode[0x10]; 4340 u8 reserved_at_10[0x10]; 4341 4342 u8 reserved_at_20[0x10]; 4343 u8 op_mod[0x10]; 4344 4345 u8 other_vport[0x1]; 4346 u8 reserved_at_41[0xf]; 4347 u8 vport_number[0x10]; 4348 4349 u8 reserved_at_60[0x5]; 4350 u8 allowed_list_type[0x3]; 4351 u8 reserved_at_68[0x18]; 4352 }; 4353 4354 struct mlx5_ifc_query_mkey_out_bits { 4355 u8 status[0x8]; 4356 u8 reserved_at_8[0x18]; 4357 4358 u8 syndrome[0x20]; 4359 4360 u8 reserved_at_40[0x40]; 4361 4362 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4363 4364 u8 reserved_at_280[0x600]; 4365 4366 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4367 4368 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4369 }; 4370 4371 struct mlx5_ifc_query_mkey_in_bits { 4372 u8 opcode[0x10]; 4373 u8 reserved_at_10[0x10]; 4374 4375 u8 reserved_at_20[0x10]; 4376 u8 op_mod[0x10]; 4377 4378 u8 reserved_at_40[0x8]; 4379 u8 mkey_index[0x18]; 4380 4381 u8 pg_access[0x1]; 4382 u8 reserved_at_61[0x1f]; 4383 }; 4384 4385 struct mlx5_ifc_query_mad_demux_out_bits { 4386 u8 status[0x8]; 4387 u8 reserved_at_8[0x18]; 4388 4389 u8 syndrome[0x20]; 4390 4391 u8 reserved_at_40[0x40]; 4392 4393 u8 mad_dumux_parameters_block[0x20]; 4394 }; 4395 4396 struct mlx5_ifc_query_mad_demux_in_bits { 4397 u8 opcode[0x10]; 4398 u8 reserved_at_10[0x10]; 4399 4400 u8 reserved_at_20[0x10]; 4401 u8 op_mod[0x10]; 4402 4403 u8 reserved_at_40[0x40]; 4404 }; 4405 4406 struct mlx5_ifc_query_l2_table_entry_out_bits { 4407 u8 status[0x8]; 4408 u8 reserved_at_8[0x18]; 4409 4410 u8 syndrome[0x20]; 4411 4412 u8 reserved_at_40[0xa0]; 4413 4414 u8 reserved_at_e0[0x13]; 4415 u8 vlan_valid[0x1]; 4416 u8 vlan[0xc]; 4417 4418 struct mlx5_ifc_mac_address_layout_bits mac_address; 4419 4420 u8 reserved_at_140[0xc0]; 4421 }; 4422 4423 struct mlx5_ifc_query_l2_table_entry_in_bits { 4424 u8 opcode[0x10]; 4425 u8 reserved_at_10[0x10]; 4426 4427 u8 reserved_at_20[0x10]; 4428 u8 op_mod[0x10]; 4429 4430 u8 reserved_at_40[0x60]; 4431 4432 u8 reserved_at_a0[0x8]; 4433 u8 table_index[0x18]; 4434 4435 u8 reserved_at_c0[0x140]; 4436 }; 4437 4438 struct mlx5_ifc_query_issi_out_bits { 4439 u8 status[0x8]; 4440 u8 reserved_at_8[0x18]; 4441 4442 u8 syndrome[0x20]; 4443 4444 u8 reserved_at_40[0x10]; 4445 u8 current_issi[0x10]; 4446 4447 u8 reserved_at_60[0xa0]; 4448 4449 u8 reserved_at_100[76][0x8]; 4450 u8 supported_issi_dw0[0x20]; 4451 }; 4452 4453 struct mlx5_ifc_query_issi_in_bits { 4454 u8 opcode[0x10]; 4455 u8 reserved_at_10[0x10]; 4456 4457 u8 reserved_at_20[0x10]; 4458 u8 op_mod[0x10]; 4459 4460 u8 reserved_at_40[0x40]; 4461 }; 4462 4463 struct mlx5_ifc_set_driver_version_out_bits { 4464 u8 status[0x8]; 4465 u8 reserved_0[0x18]; 4466 4467 u8 syndrome[0x20]; 4468 u8 reserved_1[0x40]; 4469 }; 4470 4471 struct mlx5_ifc_set_driver_version_in_bits { 4472 u8 opcode[0x10]; 4473 u8 reserved_0[0x10]; 4474 4475 u8 reserved_1[0x10]; 4476 u8 op_mod[0x10]; 4477 4478 u8 reserved_2[0x40]; 4479 u8 driver_version[64][0x8]; 4480 }; 4481 4482 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4483 u8 status[0x8]; 4484 u8 reserved_at_8[0x18]; 4485 4486 u8 syndrome[0x20]; 4487 4488 u8 reserved_at_40[0x40]; 4489 4490 struct mlx5_ifc_pkey_bits pkey[0]; 4491 }; 4492 4493 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4494 u8 opcode[0x10]; 4495 u8 reserved_at_10[0x10]; 4496 4497 u8 reserved_at_20[0x10]; 4498 u8 op_mod[0x10]; 4499 4500 u8 other_vport[0x1]; 4501 u8 reserved_at_41[0xb]; 4502 u8 port_num[0x4]; 4503 u8 vport_number[0x10]; 4504 4505 u8 reserved_at_60[0x10]; 4506 u8 pkey_index[0x10]; 4507 }; 4508 4509 enum { 4510 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4511 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4512 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4513 }; 4514 4515 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4516 u8 status[0x8]; 4517 u8 reserved_at_8[0x18]; 4518 4519 u8 syndrome[0x20]; 4520 4521 u8 reserved_at_40[0x20]; 4522 4523 u8 gids_num[0x10]; 4524 u8 reserved_at_70[0x10]; 4525 4526 struct mlx5_ifc_array128_auto_bits gid[0]; 4527 }; 4528 4529 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4530 u8 opcode[0x10]; 4531 u8 reserved_at_10[0x10]; 4532 4533 u8 reserved_at_20[0x10]; 4534 u8 op_mod[0x10]; 4535 4536 u8 other_vport[0x1]; 4537 u8 reserved_at_41[0xb]; 4538 u8 port_num[0x4]; 4539 u8 vport_number[0x10]; 4540 4541 u8 reserved_at_60[0x10]; 4542 u8 gid_index[0x10]; 4543 }; 4544 4545 struct mlx5_ifc_query_hca_vport_context_out_bits { 4546 u8 status[0x8]; 4547 u8 reserved_at_8[0x18]; 4548 4549 u8 syndrome[0x20]; 4550 4551 u8 reserved_at_40[0x40]; 4552 4553 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4554 }; 4555 4556 struct mlx5_ifc_query_hca_vport_context_in_bits { 4557 u8 opcode[0x10]; 4558 u8 reserved_at_10[0x10]; 4559 4560 u8 reserved_at_20[0x10]; 4561 u8 op_mod[0x10]; 4562 4563 u8 other_vport[0x1]; 4564 u8 reserved_at_41[0xb]; 4565 u8 port_num[0x4]; 4566 u8 vport_number[0x10]; 4567 4568 u8 reserved_at_60[0x20]; 4569 }; 4570 4571 struct mlx5_ifc_query_hca_cap_out_bits { 4572 u8 status[0x8]; 4573 u8 reserved_at_8[0x18]; 4574 4575 u8 syndrome[0x20]; 4576 4577 u8 reserved_at_40[0x40]; 4578 4579 union mlx5_ifc_hca_cap_union_bits capability; 4580 }; 4581 4582 struct mlx5_ifc_query_hca_cap_in_bits { 4583 u8 opcode[0x10]; 4584 u8 reserved_at_10[0x10]; 4585 4586 u8 reserved_at_20[0x10]; 4587 u8 op_mod[0x10]; 4588 4589 u8 reserved_at_40[0x40]; 4590 }; 4591 4592 struct mlx5_ifc_query_flow_table_out_bits { 4593 u8 status[0x8]; 4594 u8 reserved_at_8[0x18]; 4595 4596 u8 syndrome[0x20]; 4597 4598 u8 reserved_at_40[0x80]; 4599 4600 u8 reserved_at_c0[0x8]; 4601 u8 level[0x8]; 4602 u8 reserved_at_d0[0x8]; 4603 u8 log_size[0x8]; 4604 4605 u8 reserved_at_e0[0x120]; 4606 }; 4607 4608 struct mlx5_ifc_query_flow_table_in_bits { 4609 u8 opcode[0x10]; 4610 u8 reserved_at_10[0x10]; 4611 4612 u8 reserved_at_20[0x10]; 4613 u8 op_mod[0x10]; 4614 4615 u8 reserved_at_40[0x40]; 4616 4617 u8 table_type[0x8]; 4618 u8 reserved_at_88[0x18]; 4619 4620 u8 reserved_at_a0[0x8]; 4621 u8 table_id[0x18]; 4622 4623 u8 reserved_at_c0[0x140]; 4624 }; 4625 4626 struct mlx5_ifc_query_fte_out_bits { 4627 u8 status[0x8]; 4628 u8 reserved_at_8[0x18]; 4629 4630 u8 syndrome[0x20]; 4631 4632 u8 reserved_at_40[0x1c0]; 4633 4634 struct mlx5_ifc_flow_context_bits flow_context; 4635 }; 4636 4637 struct mlx5_ifc_query_fte_in_bits { 4638 u8 opcode[0x10]; 4639 u8 reserved_at_10[0x10]; 4640 4641 u8 reserved_at_20[0x10]; 4642 u8 op_mod[0x10]; 4643 4644 u8 reserved_at_40[0x40]; 4645 4646 u8 table_type[0x8]; 4647 u8 reserved_at_88[0x18]; 4648 4649 u8 reserved_at_a0[0x8]; 4650 u8 table_id[0x18]; 4651 4652 u8 reserved_at_c0[0x40]; 4653 4654 u8 flow_index[0x20]; 4655 4656 u8 reserved_at_120[0xe0]; 4657 }; 4658 4659 enum { 4660 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4661 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4662 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4663 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3, 4664 }; 4665 4666 struct mlx5_ifc_query_flow_group_out_bits { 4667 u8 status[0x8]; 4668 u8 reserved_at_8[0x18]; 4669 4670 u8 syndrome[0x20]; 4671 4672 u8 reserved_at_40[0xa0]; 4673 4674 u8 start_flow_index[0x20]; 4675 4676 u8 reserved_at_100[0x20]; 4677 4678 u8 end_flow_index[0x20]; 4679 4680 u8 reserved_at_140[0xa0]; 4681 4682 u8 reserved_at_1e0[0x18]; 4683 u8 match_criteria_enable[0x8]; 4684 4685 struct mlx5_ifc_fte_match_param_bits match_criteria; 4686 4687 u8 reserved_at_1200[0xe00]; 4688 }; 4689 4690 struct mlx5_ifc_query_flow_group_in_bits { 4691 u8 opcode[0x10]; 4692 u8 reserved_at_10[0x10]; 4693 4694 u8 reserved_at_20[0x10]; 4695 u8 op_mod[0x10]; 4696 4697 u8 reserved_at_40[0x40]; 4698 4699 u8 table_type[0x8]; 4700 u8 reserved_at_88[0x18]; 4701 4702 u8 reserved_at_a0[0x8]; 4703 u8 table_id[0x18]; 4704 4705 u8 group_id[0x20]; 4706 4707 u8 reserved_at_e0[0x120]; 4708 }; 4709 4710 struct mlx5_ifc_query_flow_counter_out_bits { 4711 u8 status[0x8]; 4712 u8 reserved_at_8[0x18]; 4713 4714 u8 syndrome[0x20]; 4715 4716 u8 reserved_at_40[0x40]; 4717 4718 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4719 }; 4720 4721 struct mlx5_ifc_query_flow_counter_in_bits { 4722 u8 opcode[0x10]; 4723 u8 reserved_at_10[0x10]; 4724 4725 u8 reserved_at_20[0x10]; 4726 u8 op_mod[0x10]; 4727 4728 u8 reserved_at_40[0x80]; 4729 4730 u8 clear[0x1]; 4731 u8 reserved_at_c1[0xf]; 4732 u8 num_of_counters[0x10]; 4733 4734 u8 flow_counter_id[0x20]; 4735 }; 4736 4737 struct mlx5_ifc_query_esw_vport_context_out_bits { 4738 u8 status[0x8]; 4739 u8 reserved_at_8[0x18]; 4740 4741 u8 syndrome[0x20]; 4742 4743 u8 reserved_at_40[0x40]; 4744 4745 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4746 }; 4747 4748 struct mlx5_ifc_query_esw_vport_context_in_bits { 4749 u8 opcode[0x10]; 4750 u8 reserved_at_10[0x10]; 4751 4752 u8 reserved_at_20[0x10]; 4753 u8 op_mod[0x10]; 4754 4755 u8 other_vport[0x1]; 4756 u8 reserved_at_41[0xf]; 4757 u8 vport_number[0x10]; 4758 4759 u8 reserved_at_60[0x20]; 4760 }; 4761 4762 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4763 u8 status[0x8]; 4764 u8 reserved_at_8[0x18]; 4765 4766 u8 syndrome[0x20]; 4767 4768 u8 reserved_at_40[0x40]; 4769 }; 4770 4771 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4772 u8 reserved_at_0[0x1c]; 4773 u8 vport_cvlan_insert[0x1]; 4774 u8 vport_svlan_insert[0x1]; 4775 u8 vport_cvlan_strip[0x1]; 4776 u8 vport_svlan_strip[0x1]; 4777 }; 4778 4779 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4780 u8 opcode[0x10]; 4781 u8 reserved_at_10[0x10]; 4782 4783 u8 reserved_at_20[0x10]; 4784 u8 op_mod[0x10]; 4785 4786 u8 other_vport[0x1]; 4787 u8 reserved_at_41[0xf]; 4788 u8 vport_number[0x10]; 4789 4790 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4791 4792 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4793 }; 4794 4795 struct mlx5_ifc_query_eq_out_bits { 4796 u8 status[0x8]; 4797 u8 reserved_at_8[0x18]; 4798 4799 u8 syndrome[0x20]; 4800 4801 u8 reserved_at_40[0x40]; 4802 4803 struct mlx5_ifc_eqc_bits eq_context_entry; 4804 4805 u8 reserved_at_280[0x40]; 4806 4807 u8 event_bitmask[0x40]; 4808 4809 u8 reserved_at_300[0x580]; 4810 4811 u8 pas[0][0x40]; 4812 }; 4813 4814 struct mlx5_ifc_query_eq_in_bits { 4815 u8 opcode[0x10]; 4816 u8 reserved_at_10[0x10]; 4817 4818 u8 reserved_at_20[0x10]; 4819 u8 op_mod[0x10]; 4820 4821 u8 reserved_at_40[0x18]; 4822 u8 eq_number[0x8]; 4823 4824 u8 reserved_at_60[0x20]; 4825 }; 4826 4827 struct mlx5_ifc_packet_reformat_context_in_bits { 4828 u8 reserved_at_0[0x5]; 4829 u8 reformat_type[0x3]; 4830 u8 reserved_at_8[0xe]; 4831 u8 reformat_data_size[0xa]; 4832 4833 u8 reserved_at_20[0x10]; 4834 u8 reformat_data[2][0x8]; 4835 4836 u8 more_reformat_data[0][0x8]; 4837 }; 4838 4839 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4840 u8 status[0x8]; 4841 u8 reserved_at_8[0x18]; 4842 4843 u8 syndrome[0x20]; 4844 4845 u8 reserved_at_40[0xa0]; 4846 4847 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4848 }; 4849 4850 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4851 u8 opcode[0x10]; 4852 u8 reserved_at_10[0x10]; 4853 4854 u8 reserved_at_20[0x10]; 4855 u8 op_mod[0x10]; 4856 4857 u8 packet_reformat_id[0x20]; 4858 4859 u8 reserved_at_60[0xa0]; 4860 }; 4861 4862 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 4863 u8 status[0x8]; 4864 u8 reserved_at_8[0x18]; 4865 4866 u8 syndrome[0x20]; 4867 4868 u8 packet_reformat_id[0x20]; 4869 4870 u8 reserved_at_60[0x20]; 4871 }; 4872 4873 enum { 4874 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 4875 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 4876 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 4877 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 4878 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 4879 }; 4880 4881 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 4882 u8 opcode[0x10]; 4883 u8 reserved_at_10[0x10]; 4884 4885 u8 reserved_at_20[0x10]; 4886 u8 op_mod[0x10]; 4887 4888 u8 reserved_at_40[0xa0]; 4889 4890 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 4891 }; 4892 4893 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 4894 u8 status[0x8]; 4895 u8 reserved_at_8[0x18]; 4896 4897 u8 syndrome[0x20]; 4898 4899 u8 reserved_at_40[0x40]; 4900 }; 4901 4902 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 4903 u8 opcode[0x10]; 4904 u8 reserved_at_10[0x10]; 4905 4906 u8 reserved_20[0x10]; 4907 u8 op_mod[0x10]; 4908 4909 u8 packet_reformat_id[0x20]; 4910 4911 u8 reserved_60[0x20]; 4912 }; 4913 4914 struct mlx5_ifc_set_action_in_bits { 4915 u8 action_type[0x4]; 4916 u8 field[0xc]; 4917 u8 reserved_at_10[0x3]; 4918 u8 offset[0x5]; 4919 u8 reserved_at_18[0x3]; 4920 u8 length[0x5]; 4921 4922 u8 data[0x20]; 4923 }; 4924 4925 struct mlx5_ifc_add_action_in_bits { 4926 u8 action_type[0x4]; 4927 u8 field[0xc]; 4928 u8 reserved_at_10[0x10]; 4929 4930 u8 data[0x20]; 4931 }; 4932 4933 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4934 struct mlx5_ifc_set_action_in_bits set_action_in; 4935 struct mlx5_ifc_add_action_in_bits add_action_in; 4936 u8 reserved_at_0[0x40]; 4937 }; 4938 4939 enum { 4940 MLX5_ACTION_TYPE_SET = 0x1, 4941 MLX5_ACTION_TYPE_ADD = 0x2, 4942 }; 4943 4944 enum { 4945 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4946 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4947 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4948 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4949 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4950 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4951 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4952 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4953 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4954 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4955 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4956 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4957 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4958 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4959 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4960 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4961 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4962 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4963 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4964 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4965 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4966 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4967 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4968 }; 4969 4970 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4971 u8 status[0x8]; 4972 u8 reserved_at_8[0x18]; 4973 4974 u8 syndrome[0x20]; 4975 4976 u8 modify_header_id[0x20]; 4977 4978 u8 reserved_at_60[0x20]; 4979 }; 4980 4981 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4982 u8 opcode[0x10]; 4983 u8 reserved_at_10[0x10]; 4984 4985 u8 reserved_at_20[0x10]; 4986 u8 op_mod[0x10]; 4987 4988 u8 reserved_at_40[0x20]; 4989 4990 u8 table_type[0x8]; 4991 u8 reserved_at_68[0x10]; 4992 u8 num_of_actions[0x8]; 4993 4994 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4995 }; 4996 4997 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4998 u8 status[0x8]; 4999 u8 reserved_at_8[0x18]; 5000 5001 u8 syndrome[0x20]; 5002 5003 u8 reserved_at_40[0x40]; 5004 }; 5005 5006 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5007 u8 opcode[0x10]; 5008 u8 reserved_at_10[0x10]; 5009 5010 u8 reserved_at_20[0x10]; 5011 u8 op_mod[0x10]; 5012 5013 u8 modify_header_id[0x20]; 5014 5015 u8 reserved_at_60[0x20]; 5016 }; 5017 5018 struct mlx5_ifc_query_dct_out_bits { 5019 u8 status[0x8]; 5020 u8 reserved_at_8[0x18]; 5021 5022 u8 syndrome[0x20]; 5023 5024 u8 reserved_at_40[0x40]; 5025 5026 struct mlx5_ifc_dctc_bits dct_context_entry; 5027 5028 u8 reserved_at_280[0x180]; 5029 }; 5030 5031 struct mlx5_ifc_query_dct_in_bits { 5032 u8 opcode[0x10]; 5033 u8 reserved_at_10[0x10]; 5034 5035 u8 reserved_at_20[0x10]; 5036 u8 op_mod[0x10]; 5037 5038 u8 reserved_at_40[0x8]; 5039 u8 dctn[0x18]; 5040 5041 u8 reserved_at_60[0x20]; 5042 }; 5043 5044 struct mlx5_ifc_query_cq_out_bits { 5045 u8 status[0x8]; 5046 u8 reserved_at_8[0x18]; 5047 5048 u8 syndrome[0x20]; 5049 5050 u8 reserved_at_40[0x40]; 5051 5052 struct mlx5_ifc_cqc_bits cq_context; 5053 5054 u8 reserved_at_280[0x600]; 5055 5056 u8 pas[0][0x40]; 5057 }; 5058 5059 struct mlx5_ifc_query_cq_in_bits { 5060 u8 opcode[0x10]; 5061 u8 reserved_at_10[0x10]; 5062 5063 u8 reserved_at_20[0x10]; 5064 u8 op_mod[0x10]; 5065 5066 u8 reserved_at_40[0x8]; 5067 u8 cqn[0x18]; 5068 5069 u8 reserved_at_60[0x20]; 5070 }; 5071 5072 struct mlx5_ifc_query_cong_status_out_bits { 5073 u8 status[0x8]; 5074 u8 reserved_at_8[0x18]; 5075 5076 u8 syndrome[0x20]; 5077 5078 u8 reserved_at_40[0x20]; 5079 5080 u8 enable[0x1]; 5081 u8 tag_enable[0x1]; 5082 u8 reserved_at_62[0x1e]; 5083 }; 5084 5085 struct mlx5_ifc_query_cong_status_in_bits { 5086 u8 opcode[0x10]; 5087 u8 reserved_at_10[0x10]; 5088 5089 u8 reserved_at_20[0x10]; 5090 u8 op_mod[0x10]; 5091 5092 u8 reserved_at_40[0x18]; 5093 u8 priority[0x4]; 5094 u8 cong_protocol[0x4]; 5095 5096 u8 reserved_at_60[0x20]; 5097 }; 5098 5099 struct mlx5_ifc_query_cong_statistics_out_bits { 5100 u8 status[0x8]; 5101 u8 reserved_at_8[0x18]; 5102 5103 u8 syndrome[0x20]; 5104 5105 u8 reserved_at_40[0x40]; 5106 5107 u8 rp_cur_flows[0x20]; 5108 5109 u8 sum_flows[0x20]; 5110 5111 u8 rp_cnp_ignored_high[0x20]; 5112 5113 u8 rp_cnp_ignored_low[0x20]; 5114 5115 u8 rp_cnp_handled_high[0x20]; 5116 5117 u8 rp_cnp_handled_low[0x20]; 5118 5119 u8 reserved_at_140[0x100]; 5120 5121 u8 time_stamp_high[0x20]; 5122 5123 u8 time_stamp_low[0x20]; 5124 5125 u8 accumulators_period[0x20]; 5126 5127 u8 np_ecn_marked_roce_packets_high[0x20]; 5128 5129 u8 np_ecn_marked_roce_packets_low[0x20]; 5130 5131 u8 np_cnp_sent_high[0x20]; 5132 5133 u8 np_cnp_sent_low[0x20]; 5134 5135 u8 reserved_at_320[0x560]; 5136 }; 5137 5138 struct mlx5_ifc_query_cong_statistics_in_bits { 5139 u8 opcode[0x10]; 5140 u8 reserved_at_10[0x10]; 5141 5142 u8 reserved_at_20[0x10]; 5143 u8 op_mod[0x10]; 5144 5145 u8 clear[0x1]; 5146 u8 reserved_at_41[0x1f]; 5147 5148 u8 reserved_at_60[0x20]; 5149 }; 5150 5151 struct mlx5_ifc_query_cong_params_out_bits { 5152 u8 status[0x8]; 5153 u8 reserved_at_8[0x18]; 5154 5155 u8 syndrome[0x20]; 5156 5157 u8 reserved_at_40[0x40]; 5158 5159 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5160 }; 5161 5162 struct mlx5_ifc_query_cong_params_in_bits { 5163 u8 opcode[0x10]; 5164 u8 reserved_at_10[0x10]; 5165 5166 u8 reserved_at_20[0x10]; 5167 u8 op_mod[0x10]; 5168 5169 u8 reserved_at_40[0x1c]; 5170 u8 cong_protocol[0x4]; 5171 5172 u8 reserved_at_60[0x20]; 5173 }; 5174 5175 struct mlx5_ifc_query_adapter_out_bits { 5176 u8 status[0x8]; 5177 u8 reserved_at_8[0x18]; 5178 5179 u8 syndrome[0x20]; 5180 5181 u8 reserved_at_40[0x40]; 5182 5183 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5184 }; 5185 5186 struct mlx5_ifc_query_adapter_in_bits { 5187 u8 opcode[0x10]; 5188 u8 reserved_at_10[0x10]; 5189 5190 u8 reserved_at_20[0x10]; 5191 u8 op_mod[0x10]; 5192 5193 u8 reserved_at_40[0x40]; 5194 }; 5195 5196 struct mlx5_ifc_qp_2rst_out_bits { 5197 u8 status[0x8]; 5198 u8 reserved_at_8[0x18]; 5199 5200 u8 syndrome[0x20]; 5201 5202 u8 reserved_at_40[0x40]; 5203 }; 5204 5205 struct mlx5_ifc_qp_2rst_in_bits { 5206 u8 opcode[0x10]; 5207 u8 uid[0x10]; 5208 5209 u8 reserved_at_20[0x10]; 5210 u8 op_mod[0x10]; 5211 5212 u8 reserved_at_40[0x8]; 5213 u8 qpn[0x18]; 5214 5215 u8 reserved_at_60[0x20]; 5216 }; 5217 5218 struct mlx5_ifc_qp_2err_out_bits { 5219 u8 status[0x8]; 5220 u8 reserved_at_8[0x18]; 5221 5222 u8 syndrome[0x20]; 5223 5224 u8 reserved_at_40[0x40]; 5225 }; 5226 5227 struct mlx5_ifc_qp_2err_in_bits { 5228 u8 opcode[0x10]; 5229 u8 uid[0x10]; 5230 5231 u8 reserved_at_20[0x10]; 5232 u8 op_mod[0x10]; 5233 5234 u8 reserved_at_40[0x8]; 5235 u8 qpn[0x18]; 5236 5237 u8 reserved_at_60[0x20]; 5238 }; 5239 5240 struct mlx5_ifc_page_fault_resume_out_bits { 5241 u8 status[0x8]; 5242 u8 reserved_at_8[0x18]; 5243 5244 u8 syndrome[0x20]; 5245 5246 u8 reserved_at_40[0x40]; 5247 }; 5248 5249 struct mlx5_ifc_page_fault_resume_in_bits { 5250 u8 opcode[0x10]; 5251 u8 reserved_at_10[0x10]; 5252 5253 u8 reserved_at_20[0x10]; 5254 u8 op_mod[0x10]; 5255 5256 u8 error[0x1]; 5257 u8 reserved_at_41[0x4]; 5258 u8 page_fault_type[0x3]; 5259 u8 wq_number[0x18]; 5260 5261 u8 reserved_at_60[0x8]; 5262 u8 token[0x18]; 5263 }; 5264 5265 struct mlx5_ifc_nop_out_bits { 5266 u8 status[0x8]; 5267 u8 reserved_at_8[0x18]; 5268 5269 u8 syndrome[0x20]; 5270 5271 u8 reserved_at_40[0x40]; 5272 }; 5273 5274 struct mlx5_ifc_nop_in_bits { 5275 u8 opcode[0x10]; 5276 u8 reserved_at_10[0x10]; 5277 5278 u8 reserved_at_20[0x10]; 5279 u8 op_mod[0x10]; 5280 5281 u8 reserved_at_40[0x40]; 5282 }; 5283 5284 struct mlx5_ifc_modify_vport_state_out_bits { 5285 u8 status[0x8]; 5286 u8 reserved_at_8[0x18]; 5287 5288 u8 syndrome[0x20]; 5289 5290 u8 reserved_at_40[0x40]; 5291 }; 5292 5293 struct mlx5_ifc_modify_vport_state_in_bits { 5294 u8 opcode[0x10]; 5295 u8 reserved_at_10[0x10]; 5296 5297 u8 reserved_at_20[0x10]; 5298 u8 op_mod[0x10]; 5299 5300 u8 other_vport[0x1]; 5301 u8 reserved_at_41[0xf]; 5302 u8 vport_number[0x10]; 5303 5304 u8 reserved_at_60[0x18]; 5305 u8 admin_state[0x4]; 5306 u8 reserved_at_7c[0x4]; 5307 }; 5308 5309 struct mlx5_ifc_modify_tis_out_bits { 5310 u8 status[0x8]; 5311 u8 reserved_at_8[0x18]; 5312 5313 u8 syndrome[0x20]; 5314 5315 u8 reserved_at_40[0x40]; 5316 }; 5317 5318 struct mlx5_ifc_modify_tis_bitmask_bits { 5319 u8 reserved_at_0[0x20]; 5320 5321 u8 reserved_at_20[0x1d]; 5322 u8 lag_tx_port_affinity[0x1]; 5323 u8 strict_lag_tx_port_affinity[0x1]; 5324 u8 prio[0x1]; 5325 }; 5326 5327 struct mlx5_ifc_modify_tis_in_bits { 5328 u8 opcode[0x10]; 5329 u8 uid[0x10]; 5330 5331 u8 reserved_at_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 reserved_at_40[0x8]; 5335 u8 tisn[0x18]; 5336 5337 u8 reserved_at_60[0x20]; 5338 5339 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5340 5341 u8 reserved_at_c0[0x40]; 5342 5343 struct mlx5_ifc_tisc_bits ctx; 5344 }; 5345 5346 struct mlx5_ifc_modify_tir_bitmask_bits { 5347 u8 reserved_at_0[0x20]; 5348 5349 u8 reserved_at_20[0x1b]; 5350 u8 self_lb_en[0x1]; 5351 u8 reserved_at_3c[0x1]; 5352 u8 hash[0x1]; 5353 u8 reserved_at_3e[0x1]; 5354 u8 lro[0x1]; 5355 }; 5356 5357 struct mlx5_ifc_modify_tir_out_bits { 5358 u8 status[0x8]; 5359 u8 reserved_at_8[0x18]; 5360 5361 u8 syndrome[0x20]; 5362 5363 u8 reserved_at_40[0x40]; 5364 }; 5365 5366 struct mlx5_ifc_modify_tir_in_bits { 5367 u8 opcode[0x10]; 5368 u8 uid[0x10]; 5369 5370 u8 reserved_at_20[0x10]; 5371 u8 op_mod[0x10]; 5372 5373 u8 reserved_at_40[0x8]; 5374 u8 tirn[0x18]; 5375 5376 u8 reserved_at_60[0x20]; 5377 5378 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5379 5380 u8 reserved_at_c0[0x40]; 5381 5382 struct mlx5_ifc_tirc_bits ctx; 5383 }; 5384 5385 struct mlx5_ifc_modify_sq_out_bits { 5386 u8 status[0x8]; 5387 u8 reserved_at_8[0x18]; 5388 5389 u8 syndrome[0x20]; 5390 5391 u8 reserved_at_40[0x40]; 5392 }; 5393 5394 struct mlx5_ifc_modify_sq_in_bits { 5395 u8 opcode[0x10]; 5396 u8 uid[0x10]; 5397 5398 u8 reserved_at_20[0x10]; 5399 u8 op_mod[0x10]; 5400 5401 u8 sq_state[0x4]; 5402 u8 reserved_at_44[0x4]; 5403 u8 sqn[0x18]; 5404 5405 u8 reserved_at_60[0x20]; 5406 5407 u8 modify_bitmask[0x40]; 5408 5409 u8 reserved_at_c0[0x40]; 5410 5411 struct mlx5_ifc_sqc_bits ctx; 5412 }; 5413 5414 struct mlx5_ifc_modify_scheduling_element_out_bits { 5415 u8 status[0x8]; 5416 u8 reserved_at_8[0x18]; 5417 5418 u8 syndrome[0x20]; 5419 5420 u8 reserved_at_40[0x1c0]; 5421 }; 5422 5423 enum { 5424 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5425 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5426 }; 5427 5428 struct mlx5_ifc_modify_scheduling_element_in_bits { 5429 u8 opcode[0x10]; 5430 u8 reserved_at_10[0x10]; 5431 5432 u8 reserved_at_20[0x10]; 5433 u8 op_mod[0x10]; 5434 5435 u8 scheduling_hierarchy[0x8]; 5436 u8 reserved_at_48[0x18]; 5437 5438 u8 scheduling_element_id[0x20]; 5439 5440 u8 reserved_at_80[0x20]; 5441 5442 u8 modify_bitmask[0x20]; 5443 5444 u8 reserved_at_c0[0x40]; 5445 5446 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5447 5448 u8 reserved_at_300[0x100]; 5449 }; 5450 5451 struct mlx5_ifc_modify_rqt_out_bits { 5452 u8 status[0x8]; 5453 u8 reserved_at_8[0x18]; 5454 5455 u8 syndrome[0x20]; 5456 5457 u8 reserved_at_40[0x40]; 5458 }; 5459 5460 struct mlx5_ifc_rqt_bitmask_bits { 5461 u8 reserved_at_0[0x20]; 5462 5463 u8 reserved_at_20[0x1f]; 5464 u8 rqn_list[0x1]; 5465 }; 5466 5467 struct mlx5_ifc_modify_rqt_in_bits { 5468 u8 opcode[0x10]; 5469 u8 uid[0x10]; 5470 5471 u8 reserved_at_20[0x10]; 5472 u8 op_mod[0x10]; 5473 5474 u8 reserved_at_40[0x8]; 5475 u8 rqtn[0x18]; 5476 5477 u8 reserved_at_60[0x20]; 5478 5479 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5480 5481 u8 reserved_at_c0[0x40]; 5482 5483 struct mlx5_ifc_rqtc_bits ctx; 5484 }; 5485 5486 struct mlx5_ifc_modify_rq_out_bits { 5487 u8 status[0x8]; 5488 u8 reserved_at_8[0x18]; 5489 5490 u8 syndrome[0x20]; 5491 5492 u8 reserved_at_40[0x40]; 5493 }; 5494 5495 enum { 5496 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5497 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5498 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5499 }; 5500 5501 struct mlx5_ifc_modify_rq_in_bits { 5502 u8 opcode[0x10]; 5503 u8 uid[0x10]; 5504 5505 u8 reserved_at_20[0x10]; 5506 u8 op_mod[0x10]; 5507 5508 u8 rq_state[0x4]; 5509 u8 reserved_at_44[0x4]; 5510 u8 rqn[0x18]; 5511 5512 u8 reserved_at_60[0x20]; 5513 5514 u8 modify_bitmask[0x40]; 5515 5516 u8 reserved_at_c0[0x40]; 5517 5518 struct mlx5_ifc_rqc_bits ctx; 5519 }; 5520 5521 struct mlx5_ifc_modify_rmp_out_bits { 5522 u8 status[0x8]; 5523 u8 reserved_at_8[0x18]; 5524 5525 u8 syndrome[0x20]; 5526 5527 u8 reserved_at_40[0x40]; 5528 }; 5529 5530 struct mlx5_ifc_rmp_bitmask_bits { 5531 u8 reserved_at_0[0x20]; 5532 5533 u8 reserved_at_20[0x1f]; 5534 u8 lwm[0x1]; 5535 }; 5536 5537 struct mlx5_ifc_modify_rmp_in_bits { 5538 u8 opcode[0x10]; 5539 u8 uid[0x10]; 5540 5541 u8 reserved_at_20[0x10]; 5542 u8 op_mod[0x10]; 5543 5544 u8 rmp_state[0x4]; 5545 u8 reserved_at_44[0x4]; 5546 u8 rmpn[0x18]; 5547 5548 u8 reserved_at_60[0x20]; 5549 5550 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5551 5552 u8 reserved_at_c0[0x40]; 5553 5554 struct mlx5_ifc_rmpc_bits ctx; 5555 }; 5556 5557 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5558 u8 status[0x8]; 5559 u8 reserved_at_8[0x18]; 5560 5561 u8 syndrome[0x20]; 5562 5563 u8 reserved_at_40[0x40]; 5564 }; 5565 5566 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5567 u8 reserved_at_0[0x12]; 5568 u8 affiliation[0x1]; 5569 u8 reserved_at_e[0x1]; 5570 u8 disable_uc_local_lb[0x1]; 5571 u8 disable_mc_local_lb[0x1]; 5572 u8 node_guid[0x1]; 5573 u8 port_guid[0x1]; 5574 u8 min_inline[0x1]; 5575 u8 mtu[0x1]; 5576 u8 change_event[0x1]; 5577 u8 promisc[0x1]; 5578 u8 permanent_address[0x1]; 5579 u8 addresses_list[0x1]; 5580 u8 roce_en[0x1]; 5581 u8 reserved_at_1f[0x1]; 5582 }; 5583 5584 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5585 u8 opcode[0x10]; 5586 u8 reserved_at_10[0x10]; 5587 5588 u8 reserved_at_20[0x10]; 5589 u8 op_mod[0x10]; 5590 5591 u8 other_vport[0x1]; 5592 u8 reserved_at_41[0xf]; 5593 u8 vport_number[0x10]; 5594 5595 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5596 5597 u8 reserved_at_80[0x780]; 5598 5599 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5600 }; 5601 5602 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5603 u8 status[0x8]; 5604 u8 reserved_at_8[0x18]; 5605 5606 u8 syndrome[0x20]; 5607 5608 u8 reserved_at_40[0x40]; 5609 }; 5610 5611 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5612 u8 opcode[0x10]; 5613 u8 reserved_at_10[0x10]; 5614 5615 u8 reserved_at_20[0x10]; 5616 u8 op_mod[0x10]; 5617 5618 u8 other_vport[0x1]; 5619 u8 reserved_at_41[0xb]; 5620 u8 port_num[0x4]; 5621 u8 vport_number[0x10]; 5622 5623 u8 reserved_at_60[0x20]; 5624 5625 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5626 }; 5627 5628 struct mlx5_ifc_modify_cq_out_bits { 5629 u8 status[0x8]; 5630 u8 reserved_at_8[0x18]; 5631 5632 u8 syndrome[0x20]; 5633 5634 u8 reserved_at_40[0x40]; 5635 }; 5636 5637 enum { 5638 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5639 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5640 }; 5641 5642 struct mlx5_ifc_modify_cq_in_bits { 5643 u8 opcode[0x10]; 5644 u8 uid[0x10]; 5645 5646 u8 reserved_at_20[0x10]; 5647 u8 op_mod[0x10]; 5648 5649 u8 reserved_at_40[0x8]; 5650 u8 cqn[0x18]; 5651 5652 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5653 5654 struct mlx5_ifc_cqc_bits cq_context; 5655 5656 u8 reserved_at_280[0x40]; 5657 5658 u8 cq_umem_valid[0x1]; 5659 u8 reserved_at_2c1[0x5bf]; 5660 5661 u8 pas[0][0x40]; 5662 }; 5663 5664 struct mlx5_ifc_modify_cong_status_out_bits { 5665 u8 status[0x8]; 5666 u8 reserved_at_8[0x18]; 5667 5668 u8 syndrome[0x20]; 5669 5670 u8 reserved_at_40[0x40]; 5671 }; 5672 5673 struct mlx5_ifc_modify_cong_status_in_bits { 5674 u8 opcode[0x10]; 5675 u8 reserved_at_10[0x10]; 5676 5677 u8 reserved_at_20[0x10]; 5678 u8 op_mod[0x10]; 5679 5680 u8 reserved_at_40[0x18]; 5681 u8 priority[0x4]; 5682 u8 cong_protocol[0x4]; 5683 5684 u8 enable[0x1]; 5685 u8 tag_enable[0x1]; 5686 u8 reserved_at_62[0x1e]; 5687 }; 5688 5689 struct mlx5_ifc_modify_cong_params_out_bits { 5690 u8 status[0x8]; 5691 u8 reserved_at_8[0x18]; 5692 5693 u8 syndrome[0x20]; 5694 5695 u8 reserved_at_40[0x40]; 5696 }; 5697 5698 struct mlx5_ifc_modify_cong_params_in_bits { 5699 u8 opcode[0x10]; 5700 u8 reserved_at_10[0x10]; 5701 5702 u8 reserved_at_20[0x10]; 5703 u8 op_mod[0x10]; 5704 5705 u8 reserved_at_40[0x1c]; 5706 u8 cong_protocol[0x4]; 5707 5708 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5709 5710 u8 reserved_at_80[0x80]; 5711 5712 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5713 }; 5714 5715 struct mlx5_ifc_manage_pages_out_bits { 5716 u8 status[0x8]; 5717 u8 reserved_at_8[0x18]; 5718 5719 u8 syndrome[0x20]; 5720 5721 u8 output_num_entries[0x20]; 5722 5723 u8 reserved_at_60[0x20]; 5724 5725 u8 pas[0][0x40]; 5726 }; 5727 5728 enum { 5729 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5730 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5731 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5732 }; 5733 5734 struct mlx5_ifc_manage_pages_in_bits { 5735 u8 opcode[0x10]; 5736 u8 reserved_at_10[0x10]; 5737 5738 u8 reserved_at_20[0x10]; 5739 u8 op_mod[0x10]; 5740 5741 u8 reserved_at_40[0x10]; 5742 u8 function_id[0x10]; 5743 5744 u8 input_num_entries[0x20]; 5745 5746 u8 pas[0][0x40]; 5747 }; 5748 5749 struct mlx5_ifc_mad_ifc_out_bits { 5750 u8 status[0x8]; 5751 u8 reserved_at_8[0x18]; 5752 5753 u8 syndrome[0x20]; 5754 5755 u8 reserved_at_40[0x40]; 5756 5757 u8 response_mad_packet[256][0x8]; 5758 }; 5759 5760 struct mlx5_ifc_mad_ifc_in_bits { 5761 u8 opcode[0x10]; 5762 u8 reserved_at_10[0x10]; 5763 5764 u8 reserved_at_20[0x10]; 5765 u8 op_mod[0x10]; 5766 5767 u8 remote_lid[0x10]; 5768 u8 reserved_at_50[0x8]; 5769 u8 port[0x8]; 5770 5771 u8 reserved_at_60[0x20]; 5772 5773 u8 mad[256][0x8]; 5774 }; 5775 5776 struct mlx5_ifc_init_hca_out_bits { 5777 u8 status[0x8]; 5778 u8 reserved_at_8[0x18]; 5779 5780 u8 syndrome[0x20]; 5781 5782 u8 reserved_at_40[0x40]; 5783 }; 5784 5785 struct mlx5_ifc_init_hca_in_bits { 5786 u8 opcode[0x10]; 5787 u8 reserved_at_10[0x10]; 5788 5789 u8 reserved_at_20[0x10]; 5790 u8 op_mod[0x10]; 5791 5792 u8 reserved_at_40[0x40]; 5793 u8 sw_owner_id[4][0x20]; 5794 }; 5795 5796 struct mlx5_ifc_init2rtr_qp_out_bits { 5797 u8 status[0x8]; 5798 u8 reserved_at_8[0x18]; 5799 5800 u8 syndrome[0x20]; 5801 5802 u8 reserved_at_40[0x40]; 5803 }; 5804 5805 struct mlx5_ifc_init2rtr_qp_in_bits { 5806 u8 opcode[0x10]; 5807 u8 uid[0x10]; 5808 5809 u8 reserved_at_20[0x10]; 5810 u8 op_mod[0x10]; 5811 5812 u8 reserved_at_40[0x8]; 5813 u8 qpn[0x18]; 5814 5815 u8 reserved_at_60[0x20]; 5816 5817 u8 opt_param_mask[0x20]; 5818 5819 u8 reserved_at_a0[0x20]; 5820 5821 struct mlx5_ifc_qpc_bits qpc; 5822 5823 u8 reserved_at_800[0x80]; 5824 }; 5825 5826 struct mlx5_ifc_init2init_qp_out_bits { 5827 u8 status[0x8]; 5828 u8 reserved_at_8[0x18]; 5829 5830 u8 syndrome[0x20]; 5831 5832 u8 reserved_at_40[0x40]; 5833 }; 5834 5835 struct mlx5_ifc_init2init_qp_in_bits { 5836 u8 opcode[0x10]; 5837 u8 uid[0x10]; 5838 5839 u8 reserved_at_20[0x10]; 5840 u8 op_mod[0x10]; 5841 5842 u8 reserved_at_40[0x8]; 5843 u8 qpn[0x18]; 5844 5845 u8 reserved_at_60[0x20]; 5846 5847 u8 opt_param_mask[0x20]; 5848 5849 u8 reserved_at_a0[0x20]; 5850 5851 struct mlx5_ifc_qpc_bits qpc; 5852 5853 u8 reserved_at_800[0x80]; 5854 }; 5855 5856 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5857 u8 status[0x8]; 5858 u8 reserved_at_8[0x18]; 5859 5860 u8 syndrome[0x20]; 5861 5862 u8 reserved_at_40[0x40]; 5863 5864 u8 packet_headers_log[128][0x8]; 5865 5866 u8 packet_syndrome[64][0x8]; 5867 }; 5868 5869 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5870 u8 opcode[0x10]; 5871 u8 reserved_at_10[0x10]; 5872 5873 u8 reserved_at_20[0x10]; 5874 u8 op_mod[0x10]; 5875 5876 u8 reserved_at_40[0x40]; 5877 }; 5878 5879 struct mlx5_ifc_gen_eqe_in_bits { 5880 u8 opcode[0x10]; 5881 u8 reserved_at_10[0x10]; 5882 5883 u8 reserved_at_20[0x10]; 5884 u8 op_mod[0x10]; 5885 5886 u8 reserved_at_40[0x18]; 5887 u8 eq_number[0x8]; 5888 5889 u8 reserved_at_60[0x20]; 5890 5891 u8 eqe[64][0x8]; 5892 }; 5893 5894 struct mlx5_ifc_gen_eq_out_bits { 5895 u8 status[0x8]; 5896 u8 reserved_at_8[0x18]; 5897 5898 u8 syndrome[0x20]; 5899 5900 u8 reserved_at_40[0x40]; 5901 }; 5902 5903 struct mlx5_ifc_enable_hca_out_bits { 5904 u8 status[0x8]; 5905 u8 reserved_at_8[0x18]; 5906 5907 u8 syndrome[0x20]; 5908 5909 u8 reserved_at_40[0x20]; 5910 }; 5911 5912 struct mlx5_ifc_enable_hca_in_bits { 5913 u8 opcode[0x10]; 5914 u8 reserved_at_10[0x10]; 5915 5916 u8 reserved_at_20[0x10]; 5917 u8 op_mod[0x10]; 5918 5919 u8 reserved_at_40[0x10]; 5920 u8 function_id[0x10]; 5921 5922 u8 reserved_at_60[0x20]; 5923 }; 5924 5925 struct mlx5_ifc_drain_dct_out_bits { 5926 u8 status[0x8]; 5927 u8 reserved_at_8[0x18]; 5928 5929 u8 syndrome[0x20]; 5930 5931 u8 reserved_at_40[0x40]; 5932 }; 5933 5934 struct mlx5_ifc_drain_dct_in_bits { 5935 u8 opcode[0x10]; 5936 u8 uid[0x10]; 5937 5938 u8 reserved_at_20[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 reserved_at_40[0x8]; 5942 u8 dctn[0x18]; 5943 5944 u8 reserved_at_60[0x20]; 5945 }; 5946 5947 struct mlx5_ifc_disable_hca_out_bits { 5948 u8 status[0x8]; 5949 u8 reserved_at_8[0x18]; 5950 5951 u8 syndrome[0x20]; 5952 5953 u8 reserved_at_40[0x20]; 5954 }; 5955 5956 struct mlx5_ifc_disable_hca_in_bits { 5957 u8 opcode[0x10]; 5958 u8 reserved_at_10[0x10]; 5959 5960 u8 reserved_at_20[0x10]; 5961 u8 op_mod[0x10]; 5962 5963 u8 reserved_at_40[0x10]; 5964 u8 function_id[0x10]; 5965 5966 u8 reserved_at_60[0x20]; 5967 }; 5968 5969 struct mlx5_ifc_detach_from_mcg_out_bits { 5970 u8 status[0x8]; 5971 u8 reserved_at_8[0x18]; 5972 5973 u8 syndrome[0x20]; 5974 5975 u8 reserved_at_40[0x40]; 5976 }; 5977 5978 struct mlx5_ifc_detach_from_mcg_in_bits { 5979 u8 opcode[0x10]; 5980 u8 uid[0x10]; 5981 5982 u8 reserved_at_20[0x10]; 5983 u8 op_mod[0x10]; 5984 5985 u8 reserved_at_40[0x8]; 5986 u8 qpn[0x18]; 5987 5988 u8 reserved_at_60[0x20]; 5989 5990 u8 multicast_gid[16][0x8]; 5991 }; 5992 5993 struct mlx5_ifc_destroy_xrq_out_bits { 5994 u8 status[0x8]; 5995 u8 reserved_at_8[0x18]; 5996 5997 u8 syndrome[0x20]; 5998 5999 u8 reserved_at_40[0x40]; 6000 }; 6001 6002 struct mlx5_ifc_destroy_xrq_in_bits { 6003 u8 opcode[0x10]; 6004 u8 uid[0x10]; 6005 6006 u8 reserved_at_20[0x10]; 6007 u8 op_mod[0x10]; 6008 6009 u8 reserved_at_40[0x8]; 6010 u8 xrqn[0x18]; 6011 6012 u8 reserved_at_60[0x20]; 6013 }; 6014 6015 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6016 u8 status[0x8]; 6017 u8 reserved_at_8[0x18]; 6018 6019 u8 syndrome[0x20]; 6020 6021 u8 reserved_at_40[0x40]; 6022 }; 6023 6024 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6025 u8 opcode[0x10]; 6026 u8 uid[0x10]; 6027 6028 u8 reserved_at_20[0x10]; 6029 u8 op_mod[0x10]; 6030 6031 u8 reserved_at_40[0x8]; 6032 u8 xrc_srqn[0x18]; 6033 6034 u8 reserved_at_60[0x20]; 6035 }; 6036 6037 struct mlx5_ifc_destroy_tis_out_bits { 6038 u8 status[0x8]; 6039 u8 reserved_at_8[0x18]; 6040 6041 u8 syndrome[0x20]; 6042 6043 u8 reserved_at_40[0x40]; 6044 }; 6045 6046 struct mlx5_ifc_destroy_tis_in_bits { 6047 u8 opcode[0x10]; 6048 u8 uid[0x10]; 6049 6050 u8 reserved_at_20[0x10]; 6051 u8 op_mod[0x10]; 6052 6053 u8 reserved_at_40[0x8]; 6054 u8 tisn[0x18]; 6055 6056 u8 reserved_at_60[0x20]; 6057 }; 6058 6059 struct mlx5_ifc_destroy_tir_out_bits { 6060 u8 status[0x8]; 6061 u8 reserved_at_8[0x18]; 6062 6063 u8 syndrome[0x20]; 6064 6065 u8 reserved_at_40[0x40]; 6066 }; 6067 6068 struct mlx5_ifc_destroy_tir_in_bits { 6069 u8 opcode[0x10]; 6070 u8 uid[0x10]; 6071 6072 u8 reserved_at_20[0x10]; 6073 u8 op_mod[0x10]; 6074 6075 u8 reserved_at_40[0x8]; 6076 u8 tirn[0x18]; 6077 6078 u8 reserved_at_60[0x20]; 6079 }; 6080 6081 struct mlx5_ifc_destroy_srq_out_bits { 6082 u8 status[0x8]; 6083 u8 reserved_at_8[0x18]; 6084 6085 u8 syndrome[0x20]; 6086 6087 u8 reserved_at_40[0x40]; 6088 }; 6089 6090 struct mlx5_ifc_destroy_srq_in_bits { 6091 u8 opcode[0x10]; 6092 u8 uid[0x10]; 6093 6094 u8 reserved_at_20[0x10]; 6095 u8 op_mod[0x10]; 6096 6097 u8 reserved_at_40[0x8]; 6098 u8 srqn[0x18]; 6099 6100 u8 reserved_at_60[0x20]; 6101 }; 6102 6103 struct mlx5_ifc_destroy_sq_out_bits { 6104 u8 status[0x8]; 6105 u8 reserved_at_8[0x18]; 6106 6107 u8 syndrome[0x20]; 6108 6109 u8 reserved_at_40[0x40]; 6110 }; 6111 6112 struct mlx5_ifc_destroy_sq_in_bits { 6113 u8 opcode[0x10]; 6114 u8 uid[0x10]; 6115 6116 u8 reserved_at_20[0x10]; 6117 u8 op_mod[0x10]; 6118 6119 u8 reserved_at_40[0x8]; 6120 u8 sqn[0x18]; 6121 6122 u8 reserved_at_60[0x20]; 6123 }; 6124 6125 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6126 u8 status[0x8]; 6127 u8 reserved_at_8[0x18]; 6128 6129 u8 syndrome[0x20]; 6130 6131 u8 reserved_at_40[0x1c0]; 6132 }; 6133 6134 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6135 u8 opcode[0x10]; 6136 u8 reserved_at_10[0x10]; 6137 6138 u8 reserved_at_20[0x10]; 6139 u8 op_mod[0x10]; 6140 6141 u8 scheduling_hierarchy[0x8]; 6142 u8 reserved_at_48[0x18]; 6143 6144 u8 scheduling_element_id[0x20]; 6145 6146 u8 reserved_at_80[0x180]; 6147 }; 6148 6149 struct mlx5_ifc_destroy_rqt_out_bits { 6150 u8 status[0x8]; 6151 u8 reserved_at_8[0x18]; 6152 6153 u8 syndrome[0x20]; 6154 6155 u8 reserved_at_40[0x40]; 6156 }; 6157 6158 struct mlx5_ifc_destroy_rqt_in_bits { 6159 u8 opcode[0x10]; 6160 u8 uid[0x10]; 6161 6162 u8 reserved_at_20[0x10]; 6163 u8 op_mod[0x10]; 6164 6165 u8 reserved_at_40[0x8]; 6166 u8 rqtn[0x18]; 6167 6168 u8 reserved_at_60[0x20]; 6169 }; 6170 6171 struct mlx5_ifc_destroy_rq_out_bits { 6172 u8 status[0x8]; 6173 u8 reserved_at_8[0x18]; 6174 6175 u8 syndrome[0x20]; 6176 6177 u8 reserved_at_40[0x40]; 6178 }; 6179 6180 struct mlx5_ifc_destroy_rq_in_bits { 6181 u8 opcode[0x10]; 6182 u8 uid[0x10]; 6183 6184 u8 reserved_at_20[0x10]; 6185 u8 op_mod[0x10]; 6186 6187 u8 reserved_at_40[0x8]; 6188 u8 rqn[0x18]; 6189 6190 u8 reserved_at_60[0x20]; 6191 }; 6192 6193 struct mlx5_ifc_set_delay_drop_params_in_bits { 6194 u8 opcode[0x10]; 6195 u8 reserved_at_10[0x10]; 6196 6197 u8 reserved_at_20[0x10]; 6198 u8 op_mod[0x10]; 6199 6200 u8 reserved_at_40[0x20]; 6201 6202 u8 reserved_at_60[0x10]; 6203 u8 delay_drop_timeout[0x10]; 6204 }; 6205 6206 struct mlx5_ifc_set_delay_drop_params_out_bits { 6207 u8 status[0x8]; 6208 u8 reserved_at_8[0x18]; 6209 6210 u8 syndrome[0x20]; 6211 6212 u8 reserved_at_40[0x40]; 6213 }; 6214 6215 struct mlx5_ifc_destroy_rmp_out_bits { 6216 u8 status[0x8]; 6217 u8 reserved_at_8[0x18]; 6218 6219 u8 syndrome[0x20]; 6220 6221 u8 reserved_at_40[0x40]; 6222 }; 6223 6224 struct mlx5_ifc_destroy_rmp_in_bits { 6225 u8 opcode[0x10]; 6226 u8 uid[0x10]; 6227 6228 u8 reserved_at_20[0x10]; 6229 u8 op_mod[0x10]; 6230 6231 u8 reserved_at_40[0x8]; 6232 u8 rmpn[0x18]; 6233 6234 u8 reserved_at_60[0x20]; 6235 }; 6236 6237 struct mlx5_ifc_destroy_qp_out_bits { 6238 u8 status[0x8]; 6239 u8 reserved_at_8[0x18]; 6240 6241 u8 syndrome[0x20]; 6242 6243 u8 reserved_at_40[0x40]; 6244 }; 6245 6246 struct mlx5_ifc_destroy_qp_in_bits { 6247 u8 opcode[0x10]; 6248 u8 uid[0x10]; 6249 6250 u8 reserved_at_20[0x10]; 6251 u8 op_mod[0x10]; 6252 6253 u8 reserved_at_40[0x8]; 6254 u8 qpn[0x18]; 6255 6256 u8 reserved_at_60[0x20]; 6257 }; 6258 6259 struct mlx5_ifc_destroy_psv_out_bits { 6260 u8 status[0x8]; 6261 u8 reserved_at_8[0x18]; 6262 6263 u8 syndrome[0x20]; 6264 6265 u8 reserved_at_40[0x40]; 6266 }; 6267 6268 struct mlx5_ifc_destroy_psv_in_bits { 6269 u8 opcode[0x10]; 6270 u8 reserved_at_10[0x10]; 6271 6272 u8 reserved_at_20[0x10]; 6273 u8 op_mod[0x10]; 6274 6275 u8 reserved_at_40[0x8]; 6276 u8 psvn[0x18]; 6277 6278 u8 reserved_at_60[0x20]; 6279 }; 6280 6281 struct mlx5_ifc_destroy_mkey_out_bits { 6282 u8 status[0x8]; 6283 u8 reserved_at_8[0x18]; 6284 6285 u8 syndrome[0x20]; 6286 6287 u8 reserved_at_40[0x40]; 6288 }; 6289 6290 struct mlx5_ifc_destroy_mkey_in_bits { 6291 u8 opcode[0x10]; 6292 u8 reserved_at_10[0x10]; 6293 6294 u8 reserved_at_20[0x10]; 6295 u8 op_mod[0x10]; 6296 6297 u8 reserved_at_40[0x8]; 6298 u8 mkey_index[0x18]; 6299 6300 u8 reserved_at_60[0x20]; 6301 }; 6302 6303 struct mlx5_ifc_destroy_flow_table_out_bits { 6304 u8 status[0x8]; 6305 u8 reserved_at_8[0x18]; 6306 6307 u8 syndrome[0x20]; 6308 6309 u8 reserved_at_40[0x40]; 6310 }; 6311 6312 struct mlx5_ifc_destroy_flow_table_in_bits { 6313 u8 opcode[0x10]; 6314 u8 reserved_at_10[0x10]; 6315 6316 u8 reserved_at_20[0x10]; 6317 u8 op_mod[0x10]; 6318 6319 u8 other_vport[0x1]; 6320 u8 reserved_at_41[0xf]; 6321 u8 vport_number[0x10]; 6322 6323 u8 reserved_at_60[0x20]; 6324 6325 u8 table_type[0x8]; 6326 u8 reserved_at_88[0x18]; 6327 6328 u8 reserved_at_a0[0x8]; 6329 u8 table_id[0x18]; 6330 6331 u8 reserved_at_c0[0x140]; 6332 }; 6333 6334 struct mlx5_ifc_destroy_flow_group_out_bits { 6335 u8 status[0x8]; 6336 u8 reserved_at_8[0x18]; 6337 6338 u8 syndrome[0x20]; 6339 6340 u8 reserved_at_40[0x40]; 6341 }; 6342 6343 struct mlx5_ifc_destroy_flow_group_in_bits { 6344 u8 opcode[0x10]; 6345 u8 reserved_at_10[0x10]; 6346 6347 u8 reserved_at_20[0x10]; 6348 u8 op_mod[0x10]; 6349 6350 u8 other_vport[0x1]; 6351 u8 reserved_at_41[0xf]; 6352 u8 vport_number[0x10]; 6353 6354 u8 reserved_at_60[0x20]; 6355 6356 u8 table_type[0x8]; 6357 u8 reserved_at_88[0x18]; 6358 6359 u8 reserved_at_a0[0x8]; 6360 u8 table_id[0x18]; 6361 6362 u8 group_id[0x20]; 6363 6364 u8 reserved_at_e0[0x120]; 6365 }; 6366 6367 struct mlx5_ifc_destroy_eq_out_bits { 6368 u8 status[0x8]; 6369 u8 reserved_at_8[0x18]; 6370 6371 u8 syndrome[0x20]; 6372 6373 u8 reserved_at_40[0x40]; 6374 }; 6375 6376 struct mlx5_ifc_destroy_eq_in_bits { 6377 u8 opcode[0x10]; 6378 u8 reserved_at_10[0x10]; 6379 6380 u8 reserved_at_20[0x10]; 6381 u8 op_mod[0x10]; 6382 6383 u8 reserved_at_40[0x18]; 6384 u8 eq_number[0x8]; 6385 6386 u8 reserved_at_60[0x20]; 6387 }; 6388 6389 struct mlx5_ifc_destroy_dct_out_bits { 6390 u8 status[0x8]; 6391 u8 reserved_at_8[0x18]; 6392 6393 u8 syndrome[0x20]; 6394 6395 u8 reserved_at_40[0x40]; 6396 }; 6397 6398 struct mlx5_ifc_destroy_dct_in_bits { 6399 u8 opcode[0x10]; 6400 u8 uid[0x10]; 6401 6402 u8 reserved_at_20[0x10]; 6403 u8 op_mod[0x10]; 6404 6405 u8 reserved_at_40[0x8]; 6406 u8 dctn[0x18]; 6407 6408 u8 reserved_at_60[0x20]; 6409 }; 6410 6411 struct mlx5_ifc_destroy_cq_out_bits { 6412 u8 status[0x8]; 6413 u8 reserved_at_8[0x18]; 6414 6415 u8 syndrome[0x20]; 6416 6417 u8 reserved_at_40[0x40]; 6418 }; 6419 6420 struct mlx5_ifc_destroy_cq_in_bits { 6421 u8 opcode[0x10]; 6422 u8 uid[0x10]; 6423 6424 u8 reserved_at_20[0x10]; 6425 u8 op_mod[0x10]; 6426 6427 u8 reserved_at_40[0x8]; 6428 u8 cqn[0x18]; 6429 6430 u8 reserved_at_60[0x20]; 6431 }; 6432 6433 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6434 u8 status[0x8]; 6435 u8 reserved_at_8[0x18]; 6436 6437 u8 syndrome[0x20]; 6438 6439 u8 reserved_at_40[0x40]; 6440 }; 6441 6442 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6443 u8 opcode[0x10]; 6444 u8 reserved_at_10[0x10]; 6445 6446 u8 reserved_at_20[0x10]; 6447 u8 op_mod[0x10]; 6448 6449 u8 reserved_at_40[0x20]; 6450 6451 u8 reserved_at_60[0x10]; 6452 u8 vxlan_udp_port[0x10]; 6453 }; 6454 6455 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_at_8[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_at_40[0x40]; 6462 }; 6463 6464 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6465 u8 opcode[0x10]; 6466 u8 reserved_at_10[0x10]; 6467 6468 u8 reserved_at_20[0x10]; 6469 u8 op_mod[0x10]; 6470 6471 u8 reserved_at_40[0x60]; 6472 6473 u8 reserved_at_a0[0x8]; 6474 u8 table_index[0x18]; 6475 6476 u8 reserved_at_c0[0x140]; 6477 }; 6478 6479 struct mlx5_ifc_delete_fte_out_bits { 6480 u8 status[0x8]; 6481 u8 reserved_at_8[0x18]; 6482 6483 u8 syndrome[0x20]; 6484 6485 u8 reserved_at_40[0x40]; 6486 }; 6487 6488 struct mlx5_ifc_delete_fte_in_bits { 6489 u8 opcode[0x10]; 6490 u8 reserved_at_10[0x10]; 6491 6492 u8 reserved_at_20[0x10]; 6493 u8 op_mod[0x10]; 6494 6495 u8 other_vport[0x1]; 6496 u8 reserved_at_41[0xf]; 6497 u8 vport_number[0x10]; 6498 6499 u8 reserved_at_60[0x20]; 6500 6501 u8 table_type[0x8]; 6502 u8 reserved_at_88[0x18]; 6503 6504 u8 reserved_at_a0[0x8]; 6505 u8 table_id[0x18]; 6506 6507 u8 reserved_at_c0[0x40]; 6508 6509 u8 flow_index[0x20]; 6510 6511 u8 reserved_at_120[0xe0]; 6512 }; 6513 6514 struct mlx5_ifc_dealloc_xrcd_out_bits { 6515 u8 status[0x8]; 6516 u8 reserved_at_8[0x18]; 6517 6518 u8 syndrome[0x20]; 6519 6520 u8 reserved_at_40[0x40]; 6521 }; 6522 6523 struct mlx5_ifc_dealloc_xrcd_in_bits { 6524 u8 opcode[0x10]; 6525 u8 uid[0x10]; 6526 6527 u8 reserved_at_20[0x10]; 6528 u8 op_mod[0x10]; 6529 6530 u8 reserved_at_40[0x8]; 6531 u8 xrcd[0x18]; 6532 6533 u8 reserved_at_60[0x20]; 6534 }; 6535 6536 struct mlx5_ifc_dealloc_uar_out_bits { 6537 u8 status[0x8]; 6538 u8 reserved_at_8[0x18]; 6539 6540 u8 syndrome[0x20]; 6541 6542 u8 reserved_at_40[0x40]; 6543 }; 6544 6545 struct mlx5_ifc_dealloc_uar_in_bits { 6546 u8 opcode[0x10]; 6547 u8 reserved_at_10[0x10]; 6548 6549 u8 reserved_at_20[0x10]; 6550 u8 op_mod[0x10]; 6551 6552 u8 reserved_at_40[0x8]; 6553 u8 uar[0x18]; 6554 6555 u8 reserved_at_60[0x20]; 6556 }; 6557 6558 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6559 u8 status[0x8]; 6560 u8 reserved_at_8[0x18]; 6561 6562 u8 syndrome[0x20]; 6563 6564 u8 reserved_at_40[0x40]; 6565 }; 6566 6567 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6568 u8 opcode[0x10]; 6569 u8 reserved_at_10[0x10]; 6570 6571 u8 reserved_at_20[0x10]; 6572 u8 op_mod[0x10]; 6573 6574 u8 reserved_at_40[0x8]; 6575 u8 transport_domain[0x18]; 6576 6577 u8 reserved_at_60[0x20]; 6578 }; 6579 6580 struct mlx5_ifc_dealloc_q_counter_out_bits { 6581 u8 status[0x8]; 6582 u8 reserved_at_8[0x18]; 6583 6584 u8 syndrome[0x20]; 6585 6586 u8 reserved_at_40[0x40]; 6587 }; 6588 6589 struct mlx5_ifc_dealloc_q_counter_in_bits { 6590 u8 opcode[0x10]; 6591 u8 reserved_at_10[0x10]; 6592 6593 u8 reserved_at_20[0x10]; 6594 u8 op_mod[0x10]; 6595 6596 u8 reserved_at_40[0x18]; 6597 u8 counter_set_id[0x8]; 6598 6599 u8 reserved_at_60[0x20]; 6600 }; 6601 6602 struct mlx5_ifc_dealloc_pd_out_bits { 6603 u8 status[0x8]; 6604 u8 reserved_at_8[0x18]; 6605 6606 u8 syndrome[0x20]; 6607 6608 u8 reserved_at_40[0x40]; 6609 }; 6610 6611 struct mlx5_ifc_dealloc_pd_in_bits { 6612 u8 opcode[0x10]; 6613 u8 uid[0x10]; 6614 6615 u8 reserved_at_20[0x10]; 6616 u8 op_mod[0x10]; 6617 6618 u8 reserved_at_40[0x8]; 6619 u8 pd[0x18]; 6620 6621 u8 reserved_at_60[0x20]; 6622 }; 6623 6624 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6625 u8 status[0x8]; 6626 u8 reserved_at_8[0x18]; 6627 6628 u8 syndrome[0x20]; 6629 6630 u8 reserved_at_40[0x40]; 6631 }; 6632 6633 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6634 u8 opcode[0x10]; 6635 u8 reserved_at_10[0x10]; 6636 6637 u8 reserved_at_20[0x10]; 6638 u8 op_mod[0x10]; 6639 6640 u8 flow_counter_id[0x20]; 6641 6642 u8 reserved_at_60[0x20]; 6643 }; 6644 6645 struct mlx5_ifc_create_xrq_out_bits { 6646 u8 status[0x8]; 6647 u8 reserved_at_8[0x18]; 6648 6649 u8 syndrome[0x20]; 6650 6651 u8 reserved_at_40[0x8]; 6652 u8 xrqn[0x18]; 6653 6654 u8 reserved_at_60[0x20]; 6655 }; 6656 6657 struct mlx5_ifc_create_xrq_in_bits { 6658 u8 opcode[0x10]; 6659 u8 uid[0x10]; 6660 6661 u8 reserved_at_20[0x10]; 6662 u8 op_mod[0x10]; 6663 6664 u8 reserved_at_40[0x40]; 6665 6666 struct mlx5_ifc_xrqc_bits xrq_context; 6667 }; 6668 6669 struct mlx5_ifc_create_xrc_srq_out_bits { 6670 u8 status[0x8]; 6671 u8 reserved_at_8[0x18]; 6672 6673 u8 syndrome[0x20]; 6674 6675 u8 reserved_at_40[0x8]; 6676 u8 xrc_srqn[0x18]; 6677 6678 u8 reserved_at_60[0x20]; 6679 }; 6680 6681 struct mlx5_ifc_create_xrc_srq_in_bits { 6682 u8 opcode[0x10]; 6683 u8 uid[0x10]; 6684 6685 u8 reserved_at_20[0x10]; 6686 u8 op_mod[0x10]; 6687 6688 u8 reserved_at_40[0x40]; 6689 6690 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6691 6692 u8 reserved_at_280[0x40]; 6693 u8 xrc_srq_umem_valid[0x1]; 6694 u8 reserved_at_2c1[0x5bf]; 6695 6696 u8 pas[0][0x40]; 6697 }; 6698 6699 struct mlx5_ifc_create_tis_out_bits { 6700 u8 status[0x8]; 6701 u8 reserved_at_8[0x18]; 6702 6703 u8 syndrome[0x20]; 6704 6705 u8 reserved_at_40[0x8]; 6706 u8 tisn[0x18]; 6707 6708 u8 reserved_at_60[0x20]; 6709 }; 6710 6711 struct mlx5_ifc_create_tis_in_bits { 6712 u8 opcode[0x10]; 6713 u8 uid[0x10]; 6714 6715 u8 reserved_at_20[0x10]; 6716 u8 op_mod[0x10]; 6717 6718 u8 reserved_at_40[0xc0]; 6719 6720 struct mlx5_ifc_tisc_bits ctx; 6721 }; 6722 6723 struct mlx5_ifc_create_tir_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_at_8[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 reserved_at_40[0x8]; 6730 u8 tirn[0x18]; 6731 6732 u8 reserved_at_60[0x20]; 6733 }; 6734 6735 struct mlx5_ifc_create_tir_in_bits { 6736 u8 opcode[0x10]; 6737 u8 uid[0x10]; 6738 6739 u8 reserved_at_20[0x10]; 6740 u8 op_mod[0x10]; 6741 6742 u8 reserved_at_40[0xc0]; 6743 6744 struct mlx5_ifc_tirc_bits ctx; 6745 }; 6746 6747 struct mlx5_ifc_create_srq_out_bits { 6748 u8 status[0x8]; 6749 u8 reserved_at_8[0x18]; 6750 6751 u8 syndrome[0x20]; 6752 6753 u8 reserved_at_40[0x8]; 6754 u8 srqn[0x18]; 6755 6756 u8 reserved_at_60[0x20]; 6757 }; 6758 6759 struct mlx5_ifc_create_srq_in_bits { 6760 u8 opcode[0x10]; 6761 u8 uid[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 reserved_at_40[0x40]; 6767 6768 struct mlx5_ifc_srqc_bits srq_context_entry; 6769 6770 u8 reserved_at_280[0x600]; 6771 6772 u8 pas[0][0x40]; 6773 }; 6774 6775 struct mlx5_ifc_create_sq_out_bits { 6776 u8 status[0x8]; 6777 u8 reserved_at_8[0x18]; 6778 6779 u8 syndrome[0x20]; 6780 6781 u8 reserved_at_40[0x8]; 6782 u8 sqn[0x18]; 6783 6784 u8 reserved_at_60[0x20]; 6785 }; 6786 6787 struct mlx5_ifc_create_sq_in_bits { 6788 u8 opcode[0x10]; 6789 u8 uid[0x10]; 6790 6791 u8 reserved_at_20[0x10]; 6792 u8 op_mod[0x10]; 6793 6794 u8 reserved_at_40[0xc0]; 6795 6796 struct mlx5_ifc_sqc_bits ctx; 6797 }; 6798 6799 struct mlx5_ifc_create_scheduling_element_out_bits { 6800 u8 status[0x8]; 6801 u8 reserved_at_8[0x18]; 6802 6803 u8 syndrome[0x20]; 6804 6805 u8 reserved_at_40[0x40]; 6806 6807 u8 scheduling_element_id[0x20]; 6808 6809 u8 reserved_at_a0[0x160]; 6810 }; 6811 6812 struct mlx5_ifc_create_scheduling_element_in_bits { 6813 u8 opcode[0x10]; 6814 u8 reserved_at_10[0x10]; 6815 6816 u8 reserved_at_20[0x10]; 6817 u8 op_mod[0x10]; 6818 6819 u8 scheduling_hierarchy[0x8]; 6820 u8 reserved_at_48[0x18]; 6821 6822 u8 reserved_at_60[0xa0]; 6823 6824 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6825 6826 u8 reserved_at_300[0x100]; 6827 }; 6828 6829 struct mlx5_ifc_create_rqt_out_bits { 6830 u8 status[0x8]; 6831 u8 reserved_at_8[0x18]; 6832 6833 u8 syndrome[0x20]; 6834 6835 u8 reserved_at_40[0x8]; 6836 u8 rqtn[0x18]; 6837 6838 u8 reserved_at_60[0x20]; 6839 }; 6840 6841 struct mlx5_ifc_create_rqt_in_bits { 6842 u8 opcode[0x10]; 6843 u8 uid[0x10]; 6844 6845 u8 reserved_at_20[0x10]; 6846 u8 op_mod[0x10]; 6847 6848 u8 reserved_at_40[0xc0]; 6849 6850 struct mlx5_ifc_rqtc_bits rqt_context; 6851 }; 6852 6853 struct mlx5_ifc_create_rq_out_bits { 6854 u8 status[0x8]; 6855 u8 reserved_at_8[0x18]; 6856 6857 u8 syndrome[0x20]; 6858 6859 u8 reserved_at_40[0x8]; 6860 u8 rqn[0x18]; 6861 6862 u8 reserved_at_60[0x20]; 6863 }; 6864 6865 struct mlx5_ifc_create_rq_in_bits { 6866 u8 opcode[0x10]; 6867 u8 uid[0x10]; 6868 6869 u8 reserved_at_20[0x10]; 6870 u8 op_mod[0x10]; 6871 6872 u8 reserved_at_40[0xc0]; 6873 6874 struct mlx5_ifc_rqc_bits ctx; 6875 }; 6876 6877 struct mlx5_ifc_create_rmp_out_bits { 6878 u8 status[0x8]; 6879 u8 reserved_at_8[0x18]; 6880 6881 u8 syndrome[0x20]; 6882 6883 u8 reserved_at_40[0x8]; 6884 u8 rmpn[0x18]; 6885 6886 u8 reserved_at_60[0x20]; 6887 }; 6888 6889 struct mlx5_ifc_create_rmp_in_bits { 6890 u8 opcode[0x10]; 6891 u8 uid[0x10]; 6892 6893 u8 reserved_at_20[0x10]; 6894 u8 op_mod[0x10]; 6895 6896 u8 reserved_at_40[0xc0]; 6897 6898 struct mlx5_ifc_rmpc_bits ctx; 6899 }; 6900 6901 struct mlx5_ifc_create_qp_out_bits { 6902 u8 status[0x8]; 6903 u8 reserved_at_8[0x18]; 6904 6905 u8 syndrome[0x20]; 6906 6907 u8 reserved_at_40[0x8]; 6908 u8 qpn[0x18]; 6909 6910 u8 reserved_at_60[0x20]; 6911 }; 6912 6913 struct mlx5_ifc_create_qp_in_bits { 6914 u8 opcode[0x10]; 6915 u8 uid[0x10]; 6916 6917 u8 reserved_at_20[0x10]; 6918 u8 op_mod[0x10]; 6919 6920 u8 reserved_at_40[0x40]; 6921 6922 u8 opt_param_mask[0x20]; 6923 6924 u8 reserved_at_a0[0x20]; 6925 6926 struct mlx5_ifc_qpc_bits qpc; 6927 6928 u8 reserved_at_800[0x60]; 6929 6930 u8 wq_umem_valid[0x1]; 6931 u8 reserved_at_861[0x1f]; 6932 6933 u8 pas[0][0x40]; 6934 }; 6935 6936 struct mlx5_ifc_create_psv_out_bits { 6937 u8 status[0x8]; 6938 u8 reserved_at_8[0x18]; 6939 6940 u8 syndrome[0x20]; 6941 6942 u8 reserved_at_40[0x40]; 6943 6944 u8 reserved_at_80[0x8]; 6945 u8 psv0_index[0x18]; 6946 6947 u8 reserved_at_a0[0x8]; 6948 u8 psv1_index[0x18]; 6949 6950 u8 reserved_at_c0[0x8]; 6951 u8 psv2_index[0x18]; 6952 6953 u8 reserved_at_e0[0x8]; 6954 u8 psv3_index[0x18]; 6955 }; 6956 6957 struct mlx5_ifc_create_psv_in_bits { 6958 u8 opcode[0x10]; 6959 u8 reserved_at_10[0x10]; 6960 6961 u8 reserved_at_20[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 num_psv[0x4]; 6965 u8 reserved_at_44[0x4]; 6966 u8 pd[0x18]; 6967 6968 u8 reserved_at_60[0x20]; 6969 }; 6970 6971 struct mlx5_ifc_create_mkey_out_bits { 6972 u8 status[0x8]; 6973 u8 reserved_at_8[0x18]; 6974 6975 u8 syndrome[0x20]; 6976 6977 u8 reserved_at_40[0x8]; 6978 u8 mkey_index[0x18]; 6979 6980 u8 reserved_at_60[0x20]; 6981 }; 6982 6983 struct mlx5_ifc_create_mkey_in_bits { 6984 u8 opcode[0x10]; 6985 u8 reserved_at_10[0x10]; 6986 6987 u8 reserved_at_20[0x10]; 6988 u8 op_mod[0x10]; 6989 6990 u8 reserved_at_40[0x20]; 6991 6992 u8 pg_access[0x1]; 6993 u8 mkey_umem_valid[0x1]; 6994 u8 reserved_at_62[0x1e]; 6995 6996 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6997 6998 u8 reserved_at_280[0x80]; 6999 7000 u8 translations_octword_actual_size[0x20]; 7001 7002 u8 reserved_at_320[0x560]; 7003 7004 u8 klm_pas_mtt[0][0x20]; 7005 }; 7006 7007 struct mlx5_ifc_create_flow_table_out_bits { 7008 u8 status[0x8]; 7009 u8 reserved_at_8[0x18]; 7010 7011 u8 syndrome[0x20]; 7012 7013 u8 reserved_at_40[0x8]; 7014 u8 table_id[0x18]; 7015 7016 u8 reserved_at_60[0x20]; 7017 }; 7018 7019 struct mlx5_ifc_flow_table_context_bits { 7020 u8 reformat_en[0x1]; 7021 u8 decap_en[0x1]; 7022 u8 reserved_at_2[0x2]; 7023 u8 table_miss_action[0x4]; 7024 u8 level[0x8]; 7025 u8 reserved_at_10[0x8]; 7026 u8 log_size[0x8]; 7027 7028 u8 reserved_at_20[0x8]; 7029 u8 table_miss_id[0x18]; 7030 7031 u8 reserved_at_40[0x8]; 7032 u8 lag_master_next_table_id[0x18]; 7033 7034 u8 reserved_at_60[0xe0]; 7035 }; 7036 7037 struct mlx5_ifc_create_flow_table_in_bits { 7038 u8 opcode[0x10]; 7039 u8 reserved_at_10[0x10]; 7040 7041 u8 reserved_at_20[0x10]; 7042 u8 op_mod[0x10]; 7043 7044 u8 other_vport[0x1]; 7045 u8 reserved_at_41[0xf]; 7046 u8 vport_number[0x10]; 7047 7048 u8 reserved_at_60[0x20]; 7049 7050 u8 table_type[0x8]; 7051 u8 reserved_at_88[0x18]; 7052 7053 u8 reserved_at_a0[0x20]; 7054 7055 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7056 }; 7057 7058 struct mlx5_ifc_create_flow_group_out_bits { 7059 u8 status[0x8]; 7060 u8 reserved_at_8[0x18]; 7061 7062 u8 syndrome[0x20]; 7063 7064 u8 reserved_at_40[0x8]; 7065 u8 group_id[0x18]; 7066 7067 u8 reserved_at_60[0x20]; 7068 }; 7069 7070 enum { 7071 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7072 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7073 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7074 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7075 }; 7076 7077 struct mlx5_ifc_create_flow_group_in_bits { 7078 u8 opcode[0x10]; 7079 u8 reserved_at_10[0x10]; 7080 7081 u8 reserved_at_20[0x10]; 7082 u8 op_mod[0x10]; 7083 7084 u8 other_vport[0x1]; 7085 u8 reserved_at_41[0xf]; 7086 u8 vport_number[0x10]; 7087 7088 u8 reserved_at_60[0x20]; 7089 7090 u8 table_type[0x8]; 7091 u8 reserved_at_88[0x18]; 7092 7093 u8 reserved_at_a0[0x8]; 7094 u8 table_id[0x18]; 7095 7096 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7097 7098 u8 reserved_at_c1[0x1f]; 7099 7100 u8 start_flow_index[0x20]; 7101 7102 u8 reserved_at_100[0x20]; 7103 7104 u8 end_flow_index[0x20]; 7105 7106 u8 reserved_at_140[0xa0]; 7107 7108 u8 reserved_at_1e0[0x18]; 7109 u8 match_criteria_enable[0x8]; 7110 7111 struct mlx5_ifc_fte_match_param_bits match_criteria; 7112 7113 u8 reserved_at_1200[0xe00]; 7114 }; 7115 7116 struct mlx5_ifc_create_eq_out_bits { 7117 u8 status[0x8]; 7118 u8 reserved_at_8[0x18]; 7119 7120 u8 syndrome[0x20]; 7121 7122 u8 reserved_at_40[0x18]; 7123 u8 eq_number[0x8]; 7124 7125 u8 reserved_at_60[0x20]; 7126 }; 7127 7128 struct mlx5_ifc_create_eq_in_bits { 7129 u8 opcode[0x10]; 7130 u8 reserved_at_10[0x10]; 7131 7132 u8 reserved_at_20[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 reserved_at_40[0x40]; 7136 7137 struct mlx5_ifc_eqc_bits eq_context_entry; 7138 7139 u8 reserved_at_280[0x40]; 7140 7141 u8 event_bitmask[0x40]; 7142 7143 u8 reserved_at_300[0x580]; 7144 7145 u8 pas[0][0x40]; 7146 }; 7147 7148 struct mlx5_ifc_create_dct_out_bits { 7149 u8 status[0x8]; 7150 u8 reserved_at_8[0x18]; 7151 7152 u8 syndrome[0x20]; 7153 7154 u8 reserved_at_40[0x8]; 7155 u8 dctn[0x18]; 7156 7157 u8 reserved_at_60[0x20]; 7158 }; 7159 7160 struct mlx5_ifc_create_dct_in_bits { 7161 u8 opcode[0x10]; 7162 u8 uid[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 reserved_at_40[0x40]; 7168 7169 struct mlx5_ifc_dctc_bits dct_context_entry; 7170 7171 u8 reserved_at_280[0x180]; 7172 }; 7173 7174 struct mlx5_ifc_create_cq_out_bits { 7175 u8 status[0x8]; 7176 u8 reserved_at_8[0x18]; 7177 7178 u8 syndrome[0x20]; 7179 7180 u8 reserved_at_40[0x8]; 7181 u8 cqn[0x18]; 7182 7183 u8 reserved_at_60[0x20]; 7184 }; 7185 7186 struct mlx5_ifc_create_cq_in_bits { 7187 u8 opcode[0x10]; 7188 u8 uid[0x10]; 7189 7190 u8 reserved_at_20[0x10]; 7191 u8 op_mod[0x10]; 7192 7193 u8 reserved_at_40[0x40]; 7194 7195 struct mlx5_ifc_cqc_bits cq_context; 7196 7197 u8 reserved_at_280[0x60]; 7198 7199 u8 cq_umem_valid[0x1]; 7200 u8 reserved_at_2e1[0x59f]; 7201 7202 u8 pas[0][0x40]; 7203 }; 7204 7205 struct mlx5_ifc_config_int_moderation_out_bits { 7206 u8 status[0x8]; 7207 u8 reserved_at_8[0x18]; 7208 7209 u8 syndrome[0x20]; 7210 7211 u8 reserved_at_40[0x4]; 7212 u8 min_delay[0xc]; 7213 u8 int_vector[0x10]; 7214 7215 u8 reserved_at_60[0x20]; 7216 }; 7217 7218 enum { 7219 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7220 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7221 }; 7222 7223 struct mlx5_ifc_config_int_moderation_in_bits { 7224 u8 opcode[0x10]; 7225 u8 reserved_at_10[0x10]; 7226 7227 u8 reserved_at_20[0x10]; 7228 u8 op_mod[0x10]; 7229 7230 u8 reserved_at_40[0x4]; 7231 u8 min_delay[0xc]; 7232 u8 int_vector[0x10]; 7233 7234 u8 reserved_at_60[0x20]; 7235 }; 7236 7237 struct mlx5_ifc_attach_to_mcg_out_bits { 7238 u8 status[0x8]; 7239 u8 reserved_at_8[0x18]; 7240 7241 u8 syndrome[0x20]; 7242 7243 u8 reserved_at_40[0x40]; 7244 }; 7245 7246 struct mlx5_ifc_attach_to_mcg_in_bits { 7247 u8 opcode[0x10]; 7248 u8 uid[0x10]; 7249 7250 u8 reserved_at_20[0x10]; 7251 u8 op_mod[0x10]; 7252 7253 u8 reserved_at_40[0x8]; 7254 u8 qpn[0x18]; 7255 7256 u8 reserved_at_60[0x20]; 7257 7258 u8 multicast_gid[16][0x8]; 7259 }; 7260 7261 struct mlx5_ifc_arm_xrq_out_bits { 7262 u8 status[0x8]; 7263 u8 reserved_at_8[0x18]; 7264 7265 u8 syndrome[0x20]; 7266 7267 u8 reserved_at_40[0x40]; 7268 }; 7269 7270 struct mlx5_ifc_arm_xrq_in_bits { 7271 u8 opcode[0x10]; 7272 u8 reserved_at_10[0x10]; 7273 7274 u8 reserved_at_20[0x10]; 7275 u8 op_mod[0x10]; 7276 7277 u8 reserved_at_40[0x8]; 7278 u8 xrqn[0x18]; 7279 7280 u8 reserved_at_60[0x10]; 7281 u8 lwm[0x10]; 7282 }; 7283 7284 struct mlx5_ifc_arm_xrc_srq_out_bits { 7285 u8 status[0x8]; 7286 u8 reserved_at_8[0x18]; 7287 7288 u8 syndrome[0x20]; 7289 7290 u8 reserved_at_40[0x40]; 7291 }; 7292 7293 enum { 7294 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7295 }; 7296 7297 struct mlx5_ifc_arm_xrc_srq_in_bits { 7298 u8 opcode[0x10]; 7299 u8 uid[0x10]; 7300 7301 u8 reserved_at_20[0x10]; 7302 u8 op_mod[0x10]; 7303 7304 u8 reserved_at_40[0x8]; 7305 u8 xrc_srqn[0x18]; 7306 7307 u8 reserved_at_60[0x10]; 7308 u8 lwm[0x10]; 7309 }; 7310 7311 struct mlx5_ifc_arm_rq_out_bits { 7312 u8 status[0x8]; 7313 u8 reserved_at_8[0x18]; 7314 7315 u8 syndrome[0x20]; 7316 7317 u8 reserved_at_40[0x40]; 7318 }; 7319 7320 enum { 7321 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7322 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7323 }; 7324 7325 struct mlx5_ifc_arm_rq_in_bits { 7326 u8 opcode[0x10]; 7327 u8 uid[0x10]; 7328 7329 u8 reserved_at_20[0x10]; 7330 u8 op_mod[0x10]; 7331 7332 u8 reserved_at_40[0x8]; 7333 u8 srq_number[0x18]; 7334 7335 u8 reserved_at_60[0x10]; 7336 u8 lwm[0x10]; 7337 }; 7338 7339 struct mlx5_ifc_arm_dct_out_bits { 7340 u8 status[0x8]; 7341 u8 reserved_at_8[0x18]; 7342 7343 u8 syndrome[0x20]; 7344 7345 u8 reserved_at_40[0x40]; 7346 }; 7347 7348 struct mlx5_ifc_arm_dct_in_bits { 7349 u8 opcode[0x10]; 7350 u8 reserved_at_10[0x10]; 7351 7352 u8 reserved_at_20[0x10]; 7353 u8 op_mod[0x10]; 7354 7355 u8 reserved_at_40[0x8]; 7356 u8 dct_number[0x18]; 7357 7358 u8 reserved_at_60[0x20]; 7359 }; 7360 7361 struct mlx5_ifc_alloc_xrcd_out_bits { 7362 u8 status[0x8]; 7363 u8 reserved_at_8[0x18]; 7364 7365 u8 syndrome[0x20]; 7366 7367 u8 reserved_at_40[0x8]; 7368 u8 xrcd[0x18]; 7369 7370 u8 reserved_at_60[0x20]; 7371 }; 7372 7373 struct mlx5_ifc_alloc_xrcd_in_bits { 7374 u8 opcode[0x10]; 7375 u8 uid[0x10]; 7376 7377 u8 reserved_at_20[0x10]; 7378 u8 op_mod[0x10]; 7379 7380 u8 reserved_at_40[0x40]; 7381 }; 7382 7383 struct mlx5_ifc_alloc_uar_out_bits { 7384 u8 status[0x8]; 7385 u8 reserved_at_8[0x18]; 7386 7387 u8 syndrome[0x20]; 7388 7389 u8 reserved_at_40[0x8]; 7390 u8 uar[0x18]; 7391 7392 u8 reserved_at_60[0x20]; 7393 }; 7394 7395 struct mlx5_ifc_alloc_uar_in_bits { 7396 u8 opcode[0x10]; 7397 u8 reserved_at_10[0x10]; 7398 7399 u8 reserved_at_20[0x10]; 7400 u8 op_mod[0x10]; 7401 7402 u8 reserved_at_40[0x40]; 7403 }; 7404 7405 struct mlx5_ifc_alloc_transport_domain_out_bits { 7406 u8 status[0x8]; 7407 u8 reserved_at_8[0x18]; 7408 7409 u8 syndrome[0x20]; 7410 7411 u8 reserved_at_40[0x8]; 7412 u8 transport_domain[0x18]; 7413 7414 u8 reserved_at_60[0x20]; 7415 }; 7416 7417 struct mlx5_ifc_alloc_transport_domain_in_bits { 7418 u8 opcode[0x10]; 7419 u8 reserved_at_10[0x10]; 7420 7421 u8 reserved_at_20[0x10]; 7422 u8 op_mod[0x10]; 7423 7424 u8 reserved_at_40[0x40]; 7425 }; 7426 7427 struct mlx5_ifc_alloc_q_counter_out_bits { 7428 u8 status[0x8]; 7429 u8 reserved_at_8[0x18]; 7430 7431 u8 syndrome[0x20]; 7432 7433 u8 reserved_at_40[0x18]; 7434 u8 counter_set_id[0x8]; 7435 7436 u8 reserved_at_60[0x20]; 7437 }; 7438 7439 struct mlx5_ifc_alloc_q_counter_in_bits { 7440 u8 opcode[0x10]; 7441 u8 reserved_at_10[0x10]; 7442 7443 u8 reserved_at_20[0x10]; 7444 u8 op_mod[0x10]; 7445 7446 u8 reserved_at_40[0x40]; 7447 }; 7448 7449 struct mlx5_ifc_alloc_pd_out_bits { 7450 u8 status[0x8]; 7451 u8 reserved_at_8[0x18]; 7452 7453 u8 syndrome[0x20]; 7454 7455 u8 reserved_at_40[0x8]; 7456 u8 pd[0x18]; 7457 7458 u8 reserved_at_60[0x20]; 7459 }; 7460 7461 struct mlx5_ifc_alloc_pd_in_bits { 7462 u8 opcode[0x10]; 7463 u8 uid[0x10]; 7464 7465 u8 reserved_at_20[0x10]; 7466 u8 op_mod[0x10]; 7467 7468 u8 reserved_at_40[0x40]; 7469 }; 7470 7471 struct mlx5_ifc_alloc_flow_counter_out_bits { 7472 u8 status[0x8]; 7473 u8 reserved_at_8[0x18]; 7474 7475 u8 syndrome[0x20]; 7476 7477 u8 flow_counter_id[0x20]; 7478 7479 u8 reserved_at_60[0x20]; 7480 }; 7481 7482 struct mlx5_ifc_alloc_flow_counter_in_bits { 7483 u8 opcode[0x10]; 7484 u8 reserved_at_10[0x10]; 7485 7486 u8 reserved_at_20[0x10]; 7487 u8 op_mod[0x10]; 7488 7489 u8 reserved_at_40[0x40]; 7490 }; 7491 7492 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7493 u8 status[0x8]; 7494 u8 reserved_at_8[0x18]; 7495 7496 u8 syndrome[0x20]; 7497 7498 u8 reserved_at_40[0x40]; 7499 }; 7500 7501 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7502 u8 opcode[0x10]; 7503 u8 reserved_at_10[0x10]; 7504 7505 u8 reserved_at_20[0x10]; 7506 u8 op_mod[0x10]; 7507 7508 u8 reserved_at_40[0x20]; 7509 7510 u8 reserved_at_60[0x10]; 7511 u8 vxlan_udp_port[0x10]; 7512 }; 7513 7514 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7515 u8 status[0x8]; 7516 u8 reserved_at_8[0x18]; 7517 7518 u8 syndrome[0x20]; 7519 7520 u8 reserved_at_40[0x40]; 7521 }; 7522 7523 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7524 u8 opcode[0x10]; 7525 u8 reserved_at_10[0x10]; 7526 7527 u8 reserved_at_20[0x10]; 7528 u8 op_mod[0x10]; 7529 7530 u8 reserved_at_40[0x10]; 7531 u8 rate_limit_index[0x10]; 7532 7533 u8 reserved_at_60[0x20]; 7534 7535 u8 rate_limit[0x20]; 7536 7537 u8 burst_upper_bound[0x20]; 7538 7539 u8 reserved_at_c0[0x10]; 7540 u8 typical_packet_size[0x10]; 7541 7542 u8 reserved_at_e0[0x120]; 7543 }; 7544 7545 struct mlx5_ifc_access_register_out_bits { 7546 u8 status[0x8]; 7547 u8 reserved_at_8[0x18]; 7548 7549 u8 syndrome[0x20]; 7550 7551 u8 reserved_at_40[0x40]; 7552 7553 u8 register_data[0][0x20]; 7554 }; 7555 7556 enum { 7557 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7558 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7559 }; 7560 7561 struct mlx5_ifc_access_register_in_bits { 7562 u8 opcode[0x10]; 7563 u8 reserved_at_10[0x10]; 7564 7565 u8 reserved_at_20[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 reserved_at_40[0x10]; 7569 u8 register_id[0x10]; 7570 7571 u8 argument[0x20]; 7572 7573 u8 register_data[0][0x20]; 7574 }; 7575 7576 struct mlx5_ifc_sltp_reg_bits { 7577 u8 status[0x4]; 7578 u8 version[0x4]; 7579 u8 local_port[0x8]; 7580 u8 pnat[0x2]; 7581 u8 reserved_at_12[0x2]; 7582 u8 lane[0x4]; 7583 u8 reserved_at_18[0x8]; 7584 7585 u8 reserved_at_20[0x20]; 7586 7587 u8 reserved_at_40[0x7]; 7588 u8 polarity[0x1]; 7589 u8 ob_tap0[0x8]; 7590 u8 ob_tap1[0x8]; 7591 u8 ob_tap2[0x8]; 7592 7593 u8 reserved_at_60[0xc]; 7594 u8 ob_preemp_mode[0x4]; 7595 u8 ob_reg[0x8]; 7596 u8 ob_bias[0x8]; 7597 7598 u8 reserved_at_80[0x20]; 7599 }; 7600 7601 struct mlx5_ifc_slrg_reg_bits { 7602 u8 status[0x4]; 7603 u8 version[0x4]; 7604 u8 local_port[0x8]; 7605 u8 pnat[0x2]; 7606 u8 reserved_at_12[0x2]; 7607 u8 lane[0x4]; 7608 u8 reserved_at_18[0x8]; 7609 7610 u8 time_to_link_up[0x10]; 7611 u8 reserved_at_30[0xc]; 7612 u8 grade_lane_speed[0x4]; 7613 7614 u8 grade_version[0x8]; 7615 u8 grade[0x18]; 7616 7617 u8 reserved_at_60[0x4]; 7618 u8 height_grade_type[0x4]; 7619 u8 height_grade[0x18]; 7620 7621 u8 height_dz[0x10]; 7622 u8 height_dv[0x10]; 7623 7624 u8 reserved_at_a0[0x10]; 7625 u8 height_sigma[0x10]; 7626 7627 u8 reserved_at_c0[0x20]; 7628 7629 u8 reserved_at_e0[0x4]; 7630 u8 phase_grade_type[0x4]; 7631 u8 phase_grade[0x18]; 7632 7633 u8 reserved_at_100[0x8]; 7634 u8 phase_eo_pos[0x8]; 7635 u8 reserved_at_110[0x8]; 7636 u8 phase_eo_neg[0x8]; 7637 7638 u8 ffe_set_tested[0x10]; 7639 u8 test_errors_per_lane[0x10]; 7640 }; 7641 7642 struct mlx5_ifc_pvlc_reg_bits { 7643 u8 reserved_at_0[0x8]; 7644 u8 local_port[0x8]; 7645 u8 reserved_at_10[0x10]; 7646 7647 u8 reserved_at_20[0x1c]; 7648 u8 vl_hw_cap[0x4]; 7649 7650 u8 reserved_at_40[0x1c]; 7651 u8 vl_admin[0x4]; 7652 7653 u8 reserved_at_60[0x1c]; 7654 u8 vl_operational[0x4]; 7655 }; 7656 7657 struct mlx5_ifc_pude_reg_bits { 7658 u8 swid[0x8]; 7659 u8 local_port[0x8]; 7660 u8 reserved_at_10[0x4]; 7661 u8 admin_status[0x4]; 7662 u8 reserved_at_18[0x4]; 7663 u8 oper_status[0x4]; 7664 7665 u8 reserved_at_20[0x60]; 7666 }; 7667 7668 struct mlx5_ifc_ptys_reg_bits { 7669 u8 reserved_at_0[0x1]; 7670 u8 an_disable_admin[0x1]; 7671 u8 an_disable_cap[0x1]; 7672 u8 reserved_at_3[0x5]; 7673 u8 local_port[0x8]; 7674 u8 reserved_at_10[0xd]; 7675 u8 proto_mask[0x3]; 7676 7677 u8 an_status[0x4]; 7678 u8 reserved_at_24[0x3c]; 7679 7680 u8 eth_proto_capability[0x20]; 7681 7682 u8 ib_link_width_capability[0x10]; 7683 u8 ib_proto_capability[0x10]; 7684 7685 u8 reserved_at_a0[0x20]; 7686 7687 u8 eth_proto_admin[0x20]; 7688 7689 u8 ib_link_width_admin[0x10]; 7690 u8 ib_proto_admin[0x10]; 7691 7692 u8 reserved_at_100[0x20]; 7693 7694 u8 eth_proto_oper[0x20]; 7695 7696 u8 ib_link_width_oper[0x10]; 7697 u8 ib_proto_oper[0x10]; 7698 7699 u8 reserved_at_160[0x1c]; 7700 u8 connector_type[0x4]; 7701 7702 u8 eth_proto_lp_advertise[0x20]; 7703 7704 u8 reserved_at_1a0[0x60]; 7705 }; 7706 7707 struct mlx5_ifc_mlcr_reg_bits { 7708 u8 reserved_at_0[0x8]; 7709 u8 local_port[0x8]; 7710 u8 reserved_at_10[0x20]; 7711 7712 u8 beacon_duration[0x10]; 7713 u8 reserved_at_40[0x10]; 7714 7715 u8 beacon_remain[0x10]; 7716 }; 7717 7718 struct mlx5_ifc_ptas_reg_bits { 7719 u8 reserved_at_0[0x20]; 7720 7721 u8 algorithm_options[0x10]; 7722 u8 reserved_at_30[0x4]; 7723 u8 repetitions_mode[0x4]; 7724 u8 num_of_repetitions[0x8]; 7725 7726 u8 grade_version[0x8]; 7727 u8 height_grade_type[0x4]; 7728 u8 phase_grade_type[0x4]; 7729 u8 height_grade_weight[0x8]; 7730 u8 phase_grade_weight[0x8]; 7731 7732 u8 gisim_measure_bits[0x10]; 7733 u8 adaptive_tap_measure_bits[0x10]; 7734 7735 u8 ber_bath_high_error_threshold[0x10]; 7736 u8 ber_bath_mid_error_threshold[0x10]; 7737 7738 u8 ber_bath_low_error_threshold[0x10]; 7739 u8 one_ratio_high_threshold[0x10]; 7740 7741 u8 one_ratio_high_mid_threshold[0x10]; 7742 u8 one_ratio_low_mid_threshold[0x10]; 7743 7744 u8 one_ratio_low_threshold[0x10]; 7745 u8 ndeo_error_threshold[0x10]; 7746 7747 u8 mixer_offset_step_size[0x10]; 7748 u8 reserved_at_110[0x8]; 7749 u8 mix90_phase_for_voltage_bath[0x8]; 7750 7751 u8 mixer_offset_start[0x10]; 7752 u8 mixer_offset_end[0x10]; 7753 7754 u8 reserved_at_140[0x15]; 7755 u8 ber_test_time[0xb]; 7756 }; 7757 7758 struct mlx5_ifc_pspa_reg_bits { 7759 u8 swid[0x8]; 7760 u8 local_port[0x8]; 7761 u8 sub_port[0x8]; 7762 u8 reserved_at_18[0x8]; 7763 7764 u8 reserved_at_20[0x20]; 7765 }; 7766 7767 struct mlx5_ifc_pqdr_reg_bits { 7768 u8 reserved_at_0[0x8]; 7769 u8 local_port[0x8]; 7770 u8 reserved_at_10[0x5]; 7771 u8 prio[0x3]; 7772 u8 reserved_at_18[0x6]; 7773 u8 mode[0x2]; 7774 7775 u8 reserved_at_20[0x20]; 7776 7777 u8 reserved_at_40[0x10]; 7778 u8 min_threshold[0x10]; 7779 7780 u8 reserved_at_60[0x10]; 7781 u8 max_threshold[0x10]; 7782 7783 u8 reserved_at_80[0x10]; 7784 u8 mark_probability_denominator[0x10]; 7785 7786 u8 reserved_at_a0[0x60]; 7787 }; 7788 7789 struct mlx5_ifc_ppsc_reg_bits { 7790 u8 reserved_at_0[0x8]; 7791 u8 local_port[0x8]; 7792 u8 reserved_at_10[0x10]; 7793 7794 u8 reserved_at_20[0x60]; 7795 7796 u8 reserved_at_80[0x1c]; 7797 u8 wrps_admin[0x4]; 7798 7799 u8 reserved_at_a0[0x1c]; 7800 u8 wrps_status[0x4]; 7801 7802 u8 reserved_at_c0[0x8]; 7803 u8 up_threshold[0x8]; 7804 u8 reserved_at_d0[0x8]; 7805 u8 down_threshold[0x8]; 7806 7807 u8 reserved_at_e0[0x20]; 7808 7809 u8 reserved_at_100[0x1c]; 7810 u8 srps_admin[0x4]; 7811 7812 u8 reserved_at_120[0x1c]; 7813 u8 srps_status[0x4]; 7814 7815 u8 reserved_at_140[0x40]; 7816 }; 7817 7818 struct mlx5_ifc_pplr_reg_bits { 7819 u8 reserved_at_0[0x8]; 7820 u8 local_port[0x8]; 7821 u8 reserved_at_10[0x10]; 7822 7823 u8 reserved_at_20[0x8]; 7824 u8 lb_cap[0x8]; 7825 u8 reserved_at_30[0x8]; 7826 u8 lb_en[0x8]; 7827 }; 7828 7829 struct mlx5_ifc_pplm_reg_bits { 7830 u8 reserved_at_0[0x8]; 7831 u8 local_port[0x8]; 7832 u8 reserved_at_10[0x10]; 7833 7834 u8 reserved_at_20[0x20]; 7835 7836 u8 port_profile_mode[0x8]; 7837 u8 static_port_profile[0x8]; 7838 u8 active_port_profile[0x8]; 7839 u8 reserved_at_58[0x8]; 7840 7841 u8 retransmission_active[0x8]; 7842 u8 fec_mode_active[0x18]; 7843 7844 u8 rs_fec_correction_bypass_cap[0x4]; 7845 u8 reserved_at_84[0x8]; 7846 u8 fec_override_cap_56g[0x4]; 7847 u8 fec_override_cap_100g[0x4]; 7848 u8 fec_override_cap_50g[0x4]; 7849 u8 fec_override_cap_25g[0x4]; 7850 u8 fec_override_cap_10g_40g[0x4]; 7851 7852 u8 rs_fec_correction_bypass_admin[0x4]; 7853 u8 reserved_at_a4[0x8]; 7854 u8 fec_override_admin_56g[0x4]; 7855 u8 fec_override_admin_100g[0x4]; 7856 u8 fec_override_admin_50g[0x4]; 7857 u8 fec_override_admin_25g[0x4]; 7858 u8 fec_override_admin_10g_40g[0x4]; 7859 }; 7860 7861 struct mlx5_ifc_ppcnt_reg_bits { 7862 u8 swid[0x8]; 7863 u8 local_port[0x8]; 7864 u8 pnat[0x2]; 7865 u8 reserved_at_12[0x8]; 7866 u8 grp[0x6]; 7867 7868 u8 clr[0x1]; 7869 u8 reserved_at_21[0x1c]; 7870 u8 prio_tc[0x3]; 7871 7872 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7873 }; 7874 7875 struct mlx5_ifc_mpcnt_reg_bits { 7876 u8 reserved_at_0[0x8]; 7877 u8 pcie_index[0x8]; 7878 u8 reserved_at_10[0xa]; 7879 u8 grp[0x6]; 7880 7881 u8 clr[0x1]; 7882 u8 reserved_at_21[0x1f]; 7883 7884 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7885 }; 7886 7887 struct mlx5_ifc_ppad_reg_bits { 7888 u8 reserved_at_0[0x3]; 7889 u8 single_mac[0x1]; 7890 u8 reserved_at_4[0x4]; 7891 u8 local_port[0x8]; 7892 u8 mac_47_32[0x10]; 7893 7894 u8 mac_31_0[0x20]; 7895 7896 u8 reserved_at_40[0x40]; 7897 }; 7898 7899 struct mlx5_ifc_pmtu_reg_bits { 7900 u8 reserved_at_0[0x8]; 7901 u8 local_port[0x8]; 7902 u8 reserved_at_10[0x10]; 7903 7904 u8 max_mtu[0x10]; 7905 u8 reserved_at_30[0x10]; 7906 7907 u8 admin_mtu[0x10]; 7908 u8 reserved_at_50[0x10]; 7909 7910 u8 oper_mtu[0x10]; 7911 u8 reserved_at_70[0x10]; 7912 }; 7913 7914 struct mlx5_ifc_pmpr_reg_bits { 7915 u8 reserved_at_0[0x8]; 7916 u8 module[0x8]; 7917 u8 reserved_at_10[0x10]; 7918 7919 u8 reserved_at_20[0x18]; 7920 u8 attenuation_5g[0x8]; 7921 7922 u8 reserved_at_40[0x18]; 7923 u8 attenuation_7g[0x8]; 7924 7925 u8 reserved_at_60[0x18]; 7926 u8 attenuation_12g[0x8]; 7927 }; 7928 7929 struct mlx5_ifc_pmpe_reg_bits { 7930 u8 reserved_at_0[0x8]; 7931 u8 module[0x8]; 7932 u8 reserved_at_10[0xc]; 7933 u8 module_status[0x4]; 7934 7935 u8 reserved_at_20[0x60]; 7936 }; 7937 7938 struct mlx5_ifc_pmpc_reg_bits { 7939 u8 module_state_updated[32][0x8]; 7940 }; 7941 7942 struct mlx5_ifc_pmlpn_reg_bits { 7943 u8 reserved_at_0[0x4]; 7944 u8 mlpn_status[0x4]; 7945 u8 local_port[0x8]; 7946 u8 reserved_at_10[0x10]; 7947 7948 u8 e[0x1]; 7949 u8 reserved_at_21[0x1f]; 7950 }; 7951 7952 struct mlx5_ifc_pmlp_reg_bits { 7953 u8 rxtx[0x1]; 7954 u8 reserved_at_1[0x7]; 7955 u8 local_port[0x8]; 7956 u8 reserved_at_10[0x8]; 7957 u8 width[0x8]; 7958 7959 u8 lane0_module_mapping[0x20]; 7960 7961 u8 lane1_module_mapping[0x20]; 7962 7963 u8 lane2_module_mapping[0x20]; 7964 7965 u8 lane3_module_mapping[0x20]; 7966 7967 u8 reserved_at_a0[0x160]; 7968 }; 7969 7970 struct mlx5_ifc_pmaos_reg_bits { 7971 u8 reserved_at_0[0x8]; 7972 u8 module[0x8]; 7973 u8 reserved_at_10[0x4]; 7974 u8 admin_status[0x4]; 7975 u8 reserved_at_18[0x4]; 7976 u8 oper_status[0x4]; 7977 7978 u8 ase[0x1]; 7979 u8 ee[0x1]; 7980 u8 reserved_at_22[0x1c]; 7981 u8 e[0x2]; 7982 7983 u8 reserved_at_40[0x40]; 7984 }; 7985 7986 struct mlx5_ifc_plpc_reg_bits { 7987 u8 reserved_at_0[0x4]; 7988 u8 profile_id[0xc]; 7989 u8 reserved_at_10[0x4]; 7990 u8 proto_mask[0x4]; 7991 u8 reserved_at_18[0x8]; 7992 7993 u8 reserved_at_20[0x10]; 7994 u8 lane_speed[0x10]; 7995 7996 u8 reserved_at_40[0x17]; 7997 u8 lpbf[0x1]; 7998 u8 fec_mode_policy[0x8]; 7999 8000 u8 retransmission_capability[0x8]; 8001 u8 fec_mode_capability[0x18]; 8002 8003 u8 retransmission_support_admin[0x8]; 8004 u8 fec_mode_support_admin[0x18]; 8005 8006 u8 retransmission_request_admin[0x8]; 8007 u8 fec_mode_request_admin[0x18]; 8008 8009 u8 reserved_at_c0[0x80]; 8010 }; 8011 8012 struct mlx5_ifc_plib_reg_bits { 8013 u8 reserved_at_0[0x8]; 8014 u8 local_port[0x8]; 8015 u8 reserved_at_10[0x8]; 8016 u8 ib_port[0x8]; 8017 8018 u8 reserved_at_20[0x60]; 8019 }; 8020 8021 struct mlx5_ifc_plbf_reg_bits { 8022 u8 reserved_at_0[0x8]; 8023 u8 local_port[0x8]; 8024 u8 reserved_at_10[0xd]; 8025 u8 lbf_mode[0x3]; 8026 8027 u8 reserved_at_20[0x20]; 8028 }; 8029 8030 struct mlx5_ifc_pipg_reg_bits { 8031 u8 reserved_at_0[0x8]; 8032 u8 local_port[0x8]; 8033 u8 reserved_at_10[0x10]; 8034 8035 u8 dic[0x1]; 8036 u8 reserved_at_21[0x19]; 8037 u8 ipg[0x4]; 8038 u8 reserved_at_3e[0x2]; 8039 }; 8040 8041 struct mlx5_ifc_pifr_reg_bits { 8042 u8 reserved_at_0[0x8]; 8043 u8 local_port[0x8]; 8044 u8 reserved_at_10[0x10]; 8045 8046 u8 reserved_at_20[0xe0]; 8047 8048 u8 port_filter[8][0x20]; 8049 8050 u8 port_filter_update_en[8][0x20]; 8051 }; 8052 8053 struct mlx5_ifc_pfcc_reg_bits { 8054 u8 reserved_at_0[0x8]; 8055 u8 local_port[0x8]; 8056 u8 reserved_at_10[0xb]; 8057 u8 ppan_mask_n[0x1]; 8058 u8 minor_stall_mask[0x1]; 8059 u8 critical_stall_mask[0x1]; 8060 u8 reserved_at_1e[0x2]; 8061 8062 u8 ppan[0x4]; 8063 u8 reserved_at_24[0x4]; 8064 u8 prio_mask_tx[0x8]; 8065 u8 reserved_at_30[0x8]; 8066 u8 prio_mask_rx[0x8]; 8067 8068 u8 pptx[0x1]; 8069 u8 aptx[0x1]; 8070 u8 pptx_mask_n[0x1]; 8071 u8 reserved_at_43[0x5]; 8072 u8 pfctx[0x8]; 8073 u8 reserved_at_50[0x10]; 8074 8075 u8 pprx[0x1]; 8076 u8 aprx[0x1]; 8077 u8 pprx_mask_n[0x1]; 8078 u8 reserved_at_63[0x5]; 8079 u8 pfcrx[0x8]; 8080 u8 reserved_at_70[0x10]; 8081 8082 u8 device_stall_minor_watermark[0x10]; 8083 u8 device_stall_critical_watermark[0x10]; 8084 8085 u8 reserved_at_a0[0x60]; 8086 }; 8087 8088 struct mlx5_ifc_pelc_reg_bits { 8089 u8 op[0x4]; 8090 u8 reserved_at_4[0x4]; 8091 u8 local_port[0x8]; 8092 u8 reserved_at_10[0x10]; 8093 8094 u8 op_admin[0x8]; 8095 u8 op_capability[0x8]; 8096 u8 op_request[0x8]; 8097 u8 op_active[0x8]; 8098 8099 u8 admin[0x40]; 8100 8101 u8 capability[0x40]; 8102 8103 u8 request[0x40]; 8104 8105 u8 active[0x40]; 8106 8107 u8 reserved_at_140[0x80]; 8108 }; 8109 8110 struct mlx5_ifc_peir_reg_bits { 8111 u8 reserved_at_0[0x8]; 8112 u8 local_port[0x8]; 8113 u8 reserved_at_10[0x10]; 8114 8115 u8 reserved_at_20[0xc]; 8116 u8 error_count[0x4]; 8117 u8 reserved_at_30[0x10]; 8118 8119 u8 reserved_at_40[0xc]; 8120 u8 lane[0x4]; 8121 u8 reserved_at_50[0x8]; 8122 u8 error_type[0x8]; 8123 }; 8124 8125 struct mlx5_ifc_mpegc_reg_bits { 8126 u8 reserved_at_0[0x30]; 8127 u8 field_select[0x10]; 8128 8129 u8 tx_overflow_sense[0x1]; 8130 u8 mark_cqe[0x1]; 8131 u8 mark_cnp[0x1]; 8132 u8 reserved_at_43[0x1b]; 8133 u8 tx_lossy_overflow_oper[0x2]; 8134 8135 u8 reserved_at_60[0x100]; 8136 }; 8137 8138 struct mlx5_ifc_pcam_enhanced_features_bits { 8139 u8 reserved_at_0[0x6d]; 8140 u8 rx_icrc_encapsulated_counter[0x1]; 8141 u8 reserved_at_6e[0x8]; 8142 u8 pfcc_mask[0x1]; 8143 u8 reserved_at_77[0x3]; 8144 u8 per_lane_error_counters[0x1]; 8145 u8 rx_buffer_fullness_counters[0x1]; 8146 u8 ptys_connector_type[0x1]; 8147 u8 reserved_at_7d[0x1]; 8148 u8 ppcnt_discard_group[0x1]; 8149 u8 ppcnt_statistical_group[0x1]; 8150 }; 8151 8152 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8153 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8154 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8155 8156 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8157 u8 pplm[0x1]; 8158 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8159 8160 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8161 u8 pbmc[0x1]; 8162 u8 pptb[0x1]; 8163 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8164 }; 8165 8166 struct mlx5_ifc_pcam_reg_bits { 8167 u8 reserved_at_0[0x8]; 8168 u8 feature_group[0x8]; 8169 u8 reserved_at_10[0x8]; 8170 u8 access_reg_group[0x8]; 8171 8172 u8 reserved_at_20[0x20]; 8173 8174 union { 8175 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8176 u8 reserved_at_0[0x80]; 8177 } port_access_reg_cap_mask; 8178 8179 u8 reserved_at_c0[0x80]; 8180 8181 union { 8182 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8183 u8 reserved_at_0[0x80]; 8184 } feature_cap_mask; 8185 8186 u8 reserved_at_1c0[0xc0]; 8187 }; 8188 8189 struct mlx5_ifc_mcam_enhanced_features_bits { 8190 u8 reserved_at_0[0x74]; 8191 u8 mark_tx_action_cnp[0x1]; 8192 u8 mark_tx_action_cqe[0x1]; 8193 u8 dynamic_tx_overflow[0x1]; 8194 u8 reserved_at_77[0x4]; 8195 u8 pcie_outbound_stalled[0x1]; 8196 u8 tx_overflow_buffer_pkt[0x1]; 8197 u8 mtpps_enh_out_per_adj[0x1]; 8198 u8 mtpps_fs[0x1]; 8199 u8 pcie_performance_group[0x1]; 8200 }; 8201 8202 struct mlx5_ifc_mcam_access_reg_bits { 8203 u8 reserved_at_0[0x1c]; 8204 u8 mcda[0x1]; 8205 u8 mcc[0x1]; 8206 u8 mcqi[0x1]; 8207 u8 reserved_at_1f[0x1]; 8208 8209 u8 regs_95_to_87[0x9]; 8210 u8 mpegc[0x1]; 8211 u8 regs_85_to_68[0x12]; 8212 u8 tracer_registers[0x4]; 8213 8214 u8 regs_63_to_32[0x20]; 8215 u8 regs_31_to_0[0x20]; 8216 }; 8217 8218 struct mlx5_ifc_mcam_reg_bits { 8219 u8 reserved_at_0[0x8]; 8220 u8 feature_group[0x8]; 8221 u8 reserved_at_10[0x8]; 8222 u8 access_reg_group[0x8]; 8223 8224 u8 reserved_at_20[0x20]; 8225 8226 union { 8227 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8228 u8 reserved_at_0[0x80]; 8229 } mng_access_reg_cap_mask; 8230 8231 u8 reserved_at_c0[0x80]; 8232 8233 union { 8234 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8235 u8 reserved_at_0[0x80]; 8236 } mng_feature_cap_mask; 8237 8238 u8 reserved_at_1c0[0x80]; 8239 }; 8240 8241 struct mlx5_ifc_qcam_access_reg_cap_mask { 8242 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8243 u8 qpdpm[0x1]; 8244 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8245 u8 qdpm[0x1]; 8246 u8 qpts[0x1]; 8247 u8 qcap[0x1]; 8248 u8 qcam_access_reg_cap_mask_0[0x1]; 8249 }; 8250 8251 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8252 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8253 u8 qpts_trust_both[0x1]; 8254 }; 8255 8256 struct mlx5_ifc_qcam_reg_bits { 8257 u8 reserved_at_0[0x8]; 8258 u8 feature_group[0x8]; 8259 u8 reserved_at_10[0x8]; 8260 u8 access_reg_group[0x8]; 8261 u8 reserved_at_20[0x20]; 8262 8263 union { 8264 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8265 u8 reserved_at_0[0x80]; 8266 } qos_access_reg_cap_mask; 8267 8268 u8 reserved_at_c0[0x80]; 8269 8270 union { 8271 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8272 u8 reserved_at_0[0x80]; 8273 } qos_feature_cap_mask; 8274 8275 u8 reserved_at_1c0[0x80]; 8276 }; 8277 8278 struct mlx5_ifc_pcap_reg_bits { 8279 u8 reserved_at_0[0x8]; 8280 u8 local_port[0x8]; 8281 u8 reserved_at_10[0x10]; 8282 8283 u8 port_capability_mask[4][0x20]; 8284 }; 8285 8286 struct mlx5_ifc_paos_reg_bits { 8287 u8 swid[0x8]; 8288 u8 local_port[0x8]; 8289 u8 reserved_at_10[0x4]; 8290 u8 admin_status[0x4]; 8291 u8 reserved_at_18[0x4]; 8292 u8 oper_status[0x4]; 8293 8294 u8 ase[0x1]; 8295 u8 ee[0x1]; 8296 u8 reserved_at_22[0x1c]; 8297 u8 e[0x2]; 8298 8299 u8 reserved_at_40[0x40]; 8300 }; 8301 8302 struct mlx5_ifc_pamp_reg_bits { 8303 u8 reserved_at_0[0x8]; 8304 u8 opamp_group[0x8]; 8305 u8 reserved_at_10[0xc]; 8306 u8 opamp_group_type[0x4]; 8307 8308 u8 start_index[0x10]; 8309 u8 reserved_at_30[0x4]; 8310 u8 num_of_indices[0xc]; 8311 8312 u8 index_data[18][0x10]; 8313 }; 8314 8315 struct mlx5_ifc_pcmr_reg_bits { 8316 u8 reserved_at_0[0x8]; 8317 u8 local_port[0x8]; 8318 u8 reserved_at_10[0x2e]; 8319 u8 fcs_cap[0x1]; 8320 u8 reserved_at_3f[0x1f]; 8321 u8 fcs_chk[0x1]; 8322 u8 reserved_at_5f[0x1]; 8323 }; 8324 8325 struct mlx5_ifc_lane_2_module_mapping_bits { 8326 u8 reserved_at_0[0x6]; 8327 u8 rx_lane[0x2]; 8328 u8 reserved_at_8[0x6]; 8329 u8 tx_lane[0x2]; 8330 u8 reserved_at_10[0x8]; 8331 u8 module[0x8]; 8332 }; 8333 8334 struct mlx5_ifc_bufferx_reg_bits { 8335 u8 reserved_at_0[0x6]; 8336 u8 lossy[0x1]; 8337 u8 epsb[0x1]; 8338 u8 reserved_at_8[0xc]; 8339 u8 size[0xc]; 8340 8341 u8 xoff_threshold[0x10]; 8342 u8 xon_threshold[0x10]; 8343 }; 8344 8345 struct mlx5_ifc_set_node_in_bits { 8346 u8 node_description[64][0x8]; 8347 }; 8348 8349 struct mlx5_ifc_register_power_settings_bits { 8350 u8 reserved_at_0[0x18]; 8351 u8 power_settings_level[0x8]; 8352 8353 u8 reserved_at_20[0x60]; 8354 }; 8355 8356 struct mlx5_ifc_register_host_endianness_bits { 8357 u8 he[0x1]; 8358 u8 reserved_at_1[0x1f]; 8359 8360 u8 reserved_at_20[0x60]; 8361 }; 8362 8363 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8364 u8 reserved_at_0[0x20]; 8365 8366 u8 mkey[0x20]; 8367 8368 u8 addressh_63_32[0x20]; 8369 8370 u8 addressl_31_0[0x20]; 8371 }; 8372 8373 struct mlx5_ifc_ud_adrs_vector_bits { 8374 u8 dc_key[0x40]; 8375 8376 u8 ext[0x1]; 8377 u8 reserved_at_41[0x7]; 8378 u8 destination_qp_dct[0x18]; 8379 8380 u8 static_rate[0x4]; 8381 u8 sl_eth_prio[0x4]; 8382 u8 fl[0x1]; 8383 u8 mlid[0x7]; 8384 u8 rlid_udp_sport[0x10]; 8385 8386 u8 reserved_at_80[0x20]; 8387 8388 u8 rmac_47_16[0x20]; 8389 8390 u8 rmac_15_0[0x10]; 8391 u8 tclass[0x8]; 8392 u8 hop_limit[0x8]; 8393 8394 u8 reserved_at_e0[0x1]; 8395 u8 grh[0x1]; 8396 u8 reserved_at_e2[0x2]; 8397 u8 src_addr_index[0x8]; 8398 u8 flow_label[0x14]; 8399 8400 u8 rgid_rip[16][0x8]; 8401 }; 8402 8403 struct mlx5_ifc_pages_req_event_bits { 8404 u8 reserved_at_0[0x10]; 8405 u8 function_id[0x10]; 8406 8407 u8 num_pages[0x20]; 8408 8409 u8 reserved_at_40[0xa0]; 8410 }; 8411 8412 struct mlx5_ifc_eqe_bits { 8413 u8 reserved_at_0[0x8]; 8414 u8 event_type[0x8]; 8415 u8 reserved_at_10[0x8]; 8416 u8 event_sub_type[0x8]; 8417 8418 u8 reserved_at_20[0xe0]; 8419 8420 union mlx5_ifc_event_auto_bits event_data; 8421 8422 u8 reserved_at_1e0[0x10]; 8423 u8 signature[0x8]; 8424 u8 reserved_at_1f8[0x7]; 8425 u8 owner[0x1]; 8426 }; 8427 8428 enum { 8429 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8430 }; 8431 8432 struct mlx5_ifc_cmd_queue_entry_bits { 8433 u8 type[0x8]; 8434 u8 reserved_at_8[0x18]; 8435 8436 u8 input_length[0x20]; 8437 8438 u8 input_mailbox_pointer_63_32[0x20]; 8439 8440 u8 input_mailbox_pointer_31_9[0x17]; 8441 u8 reserved_at_77[0x9]; 8442 8443 u8 command_input_inline_data[16][0x8]; 8444 8445 u8 command_output_inline_data[16][0x8]; 8446 8447 u8 output_mailbox_pointer_63_32[0x20]; 8448 8449 u8 output_mailbox_pointer_31_9[0x17]; 8450 u8 reserved_at_1b7[0x9]; 8451 8452 u8 output_length[0x20]; 8453 8454 u8 token[0x8]; 8455 u8 signature[0x8]; 8456 u8 reserved_at_1f0[0x8]; 8457 u8 status[0x7]; 8458 u8 ownership[0x1]; 8459 }; 8460 8461 struct mlx5_ifc_cmd_out_bits { 8462 u8 status[0x8]; 8463 u8 reserved_at_8[0x18]; 8464 8465 u8 syndrome[0x20]; 8466 8467 u8 command_output[0x20]; 8468 }; 8469 8470 struct mlx5_ifc_cmd_in_bits { 8471 u8 opcode[0x10]; 8472 u8 reserved_at_10[0x10]; 8473 8474 u8 reserved_at_20[0x10]; 8475 u8 op_mod[0x10]; 8476 8477 u8 command[0][0x20]; 8478 }; 8479 8480 struct mlx5_ifc_cmd_if_box_bits { 8481 u8 mailbox_data[512][0x8]; 8482 8483 u8 reserved_at_1000[0x180]; 8484 8485 u8 next_pointer_63_32[0x20]; 8486 8487 u8 next_pointer_31_10[0x16]; 8488 u8 reserved_at_11b6[0xa]; 8489 8490 u8 block_number[0x20]; 8491 8492 u8 reserved_at_11e0[0x8]; 8493 u8 token[0x8]; 8494 u8 ctrl_signature[0x8]; 8495 u8 signature[0x8]; 8496 }; 8497 8498 struct mlx5_ifc_mtt_bits { 8499 u8 ptag_63_32[0x20]; 8500 8501 u8 ptag_31_8[0x18]; 8502 u8 reserved_at_38[0x6]; 8503 u8 wr_en[0x1]; 8504 u8 rd_en[0x1]; 8505 }; 8506 8507 struct mlx5_ifc_query_wol_rol_out_bits { 8508 u8 status[0x8]; 8509 u8 reserved_at_8[0x18]; 8510 8511 u8 syndrome[0x20]; 8512 8513 u8 reserved_at_40[0x10]; 8514 u8 rol_mode[0x8]; 8515 u8 wol_mode[0x8]; 8516 8517 u8 reserved_at_60[0x20]; 8518 }; 8519 8520 struct mlx5_ifc_query_wol_rol_in_bits { 8521 u8 opcode[0x10]; 8522 u8 reserved_at_10[0x10]; 8523 8524 u8 reserved_at_20[0x10]; 8525 u8 op_mod[0x10]; 8526 8527 u8 reserved_at_40[0x40]; 8528 }; 8529 8530 struct mlx5_ifc_set_wol_rol_out_bits { 8531 u8 status[0x8]; 8532 u8 reserved_at_8[0x18]; 8533 8534 u8 syndrome[0x20]; 8535 8536 u8 reserved_at_40[0x40]; 8537 }; 8538 8539 struct mlx5_ifc_set_wol_rol_in_bits { 8540 u8 opcode[0x10]; 8541 u8 reserved_at_10[0x10]; 8542 8543 u8 reserved_at_20[0x10]; 8544 u8 op_mod[0x10]; 8545 8546 u8 rol_mode_valid[0x1]; 8547 u8 wol_mode_valid[0x1]; 8548 u8 reserved_at_42[0xe]; 8549 u8 rol_mode[0x8]; 8550 u8 wol_mode[0x8]; 8551 8552 u8 reserved_at_60[0x20]; 8553 }; 8554 8555 enum { 8556 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8557 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8558 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8559 }; 8560 8561 enum { 8562 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8563 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8564 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8565 }; 8566 8567 enum { 8568 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8569 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8570 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8571 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8572 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8573 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8574 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8575 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8576 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8577 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8578 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8579 }; 8580 8581 struct mlx5_ifc_initial_seg_bits { 8582 u8 fw_rev_minor[0x10]; 8583 u8 fw_rev_major[0x10]; 8584 8585 u8 cmd_interface_rev[0x10]; 8586 u8 fw_rev_subminor[0x10]; 8587 8588 u8 reserved_at_40[0x40]; 8589 8590 u8 cmdq_phy_addr_63_32[0x20]; 8591 8592 u8 cmdq_phy_addr_31_12[0x14]; 8593 u8 reserved_at_b4[0x2]; 8594 u8 nic_interface[0x2]; 8595 u8 log_cmdq_size[0x4]; 8596 u8 log_cmdq_stride[0x4]; 8597 8598 u8 command_doorbell_vector[0x20]; 8599 8600 u8 reserved_at_e0[0xf00]; 8601 8602 u8 initializing[0x1]; 8603 u8 reserved_at_fe1[0x4]; 8604 u8 nic_interface_supported[0x3]; 8605 u8 reserved_at_fe8[0x18]; 8606 8607 struct mlx5_ifc_health_buffer_bits health_buffer; 8608 8609 u8 no_dram_nic_offset[0x20]; 8610 8611 u8 reserved_at_1220[0x6e40]; 8612 8613 u8 reserved_at_8060[0x1f]; 8614 u8 clear_int[0x1]; 8615 8616 u8 health_syndrome[0x8]; 8617 u8 health_counter[0x18]; 8618 8619 u8 reserved_at_80a0[0x17fc0]; 8620 }; 8621 8622 struct mlx5_ifc_mtpps_reg_bits { 8623 u8 reserved_at_0[0xc]; 8624 u8 cap_number_of_pps_pins[0x4]; 8625 u8 reserved_at_10[0x4]; 8626 u8 cap_max_num_of_pps_in_pins[0x4]; 8627 u8 reserved_at_18[0x4]; 8628 u8 cap_max_num_of_pps_out_pins[0x4]; 8629 8630 u8 reserved_at_20[0x24]; 8631 u8 cap_pin_3_mode[0x4]; 8632 u8 reserved_at_48[0x4]; 8633 u8 cap_pin_2_mode[0x4]; 8634 u8 reserved_at_50[0x4]; 8635 u8 cap_pin_1_mode[0x4]; 8636 u8 reserved_at_58[0x4]; 8637 u8 cap_pin_0_mode[0x4]; 8638 8639 u8 reserved_at_60[0x4]; 8640 u8 cap_pin_7_mode[0x4]; 8641 u8 reserved_at_68[0x4]; 8642 u8 cap_pin_6_mode[0x4]; 8643 u8 reserved_at_70[0x4]; 8644 u8 cap_pin_5_mode[0x4]; 8645 u8 reserved_at_78[0x4]; 8646 u8 cap_pin_4_mode[0x4]; 8647 8648 u8 field_select[0x20]; 8649 u8 reserved_at_a0[0x60]; 8650 8651 u8 enable[0x1]; 8652 u8 reserved_at_101[0xb]; 8653 u8 pattern[0x4]; 8654 u8 reserved_at_110[0x4]; 8655 u8 pin_mode[0x4]; 8656 u8 pin[0x8]; 8657 8658 u8 reserved_at_120[0x20]; 8659 8660 u8 time_stamp[0x40]; 8661 8662 u8 out_pulse_duration[0x10]; 8663 u8 out_periodic_adjustment[0x10]; 8664 u8 enhanced_out_periodic_adjustment[0x20]; 8665 8666 u8 reserved_at_1c0[0x20]; 8667 }; 8668 8669 struct mlx5_ifc_mtppse_reg_bits { 8670 u8 reserved_at_0[0x18]; 8671 u8 pin[0x8]; 8672 u8 event_arm[0x1]; 8673 u8 reserved_at_21[0x1b]; 8674 u8 event_generation_mode[0x4]; 8675 u8 reserved_at_40[0x40]; 8676 }; 8677 8678 struct mlx5_ifc_mcqi_cap_bits { 8679 u8 supported_info_bitmask[0x20]; 8680 8681 u8 component_size[0x20]; 8682 8683 u8 max_component_size[0x20]; 8684 8685 u8 log_mcda_word_size[0x4]; 8686 u8 reserved_at_64[0xc]; 8687 u8 mcda_max_write_size[0x10]; 8688 8689 u8 rd_en[0x1]; 8690 u8 reserved_at_81[0x1]; 8691 u8 match_chip_id[0x1]; 8692 u8 match_psid[0x1]; 8693 u8 check_user_timestamp[0x1]; 8694 u8 match_base_guid_mac[0x1]; 8695 u8 reserved_at_86[0x1a]; 8696 }; 8697 8698 struct mlx5_ifc_mcqi_reg_bits { 8699 u8 read_pending_component[0x1]; 8700 u8 reserved_at_1[0xf]; 8701 u8 component_index[0x10]; 8702 8703 u8 reserved_at_20[0x20]; 8704 8705 u8 reserved_at_40[0x1b]; 8706 u8 info_type[0x5]; 8707 8708 u8 info_size[0x20]; 8709 8710 u8 offset[0x20]; 8711 8712 u8 reserved_at_a0[0x10]; 8713 u8 data_size[0x10]; 8714 8715 u8 data[0][0x20]; 8716 }; 8717 8718 struct mlx5_ifc_mcc_reg_bits { 8719 u8 reserved_at_0[0x4]; 8720 u8 time_elapsed_since_last_cmd[0xc]; 8721 u8 reserved_at_10[0x8]; 8722 u8 instruction[0x8]; 8723 8724 u8 reserved_at_20[0x10]; 8725 u8 component_index[0x10]; 8726 8727 u8 reserved_at_40[0x8]; 8728 u8 update_handle[0x18]; 8729 8730 u8 handle_owner_type[0x4]; 8731 u8 handle_owner_host_id[0x4]; 8732 u8 reserved_at_68[0x1]; 8733 u8 control_progress[0x7]; 8734 u8 error_code[0x8]; 8735 u8 reserved_at_78[0x4]; 8736 u8 control_state[0x4]; 8737 8738 u8 component_size[0x20]; 8739 8740 u8 reserved_at_a0[0x60]; 8741 }; 8742 8743 struct mlx5_ifc_mcda_reg_bits { 8744 u8 reserved_at_0[0x8]; 8745 u8 update_handle[0x18]; 8746 8747 u8 offset[0x20]; 8748 8749 u8 reserved_at_40[0x10]; 8750 u8 size[0x10]; 8751 8752 u8 reserved_at_60[0x20]; 8753 8754 u8 data[0][0x20]; 8755 }; 8756 8757 union mlx5_ifc_ports_control_registers_document_bits { 8758 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8759 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8760 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8761 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8762 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8763 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8764 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8765 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8766 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8767 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8768 struct mlx5_ifc_paos_reg_bits paos_reg; 8769 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8770 struct mlx5_ifc_peir_reg_bits peir_reg; 8771 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8772 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8773 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8774 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8775 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8776 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8777 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8778 struct mlx5_ifc_plib_reg_bits plib_reg; 8779 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8780 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8781 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8782 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8783 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8784 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8785 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8786 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8787 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8788 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8789 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8790 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8791 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8792 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8793 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8794 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8795 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8796 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8797 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8798 struct mlx5_ifc_pude_reg_bits pude_reg; 8799 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8800 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8801 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8802 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8803 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8804 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8805 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8806 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8807 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8808 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8809 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8810 u8 reserved_at_0[0x60e0]; 8811 }; 8812 8813 union mlx5_ifc_debug_enhancements_document_bits { 8814 struct mlx5_ifc_health_buffer_bits health_buffer; 8815 u8 reserved_at_0[0x200]; 8816 }; 8817 8818 union mlx5_ifc_uplink_pci_interface_document_bits { 8819 struct mlx5_ifc_initial_seg_bits initial_seg; 8820 u8 reserved_at_0[0x20060]; 8821 }; 8822 8823 struct mlx5_ifc_set_flow_table_root_out_bits { 8824 u8 status[0x8]; 8825 u8 reserved_at_8[0x18]; 8826 8827 u8 syndrome[0x20]; 8828 8829 u8 reserved_at_40[0x40]; 8830 }; 8831 8832 struct mlx5_ifc_set_flow_table_root_in_bits { 8833 u8 opcode[0x10]; 8834 u8 reserved_at_10[0x10]; 8835 8836 u8 reserved_at_20[0x10]; 8837 u8 op_mod[0x10]; 8838 8839 u8 other_vport[0x1]; 8840 u8 reserved_at_41[0xf]; 8841 u8 vport_number[0x10]; 8842 8843 u8 reserved_at_60[0x20]; 8844 8845 u8 table_type[0x8]; 8846 u8 reserved_at_88[0x18]; 8847 8848 u8 reserved_at_a0[0x8]; 8849 u8 table_id[0x18]; 8850 8851 u8 reserved_at_c0[0x8]; 8852 u8 underlay_qpn[0x18]; 8853 u8 reserved_at_e0[0x120]; 8854 }; 8855 8856 enum { 8857 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8858 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8859 }; 8860 8861 struct mlx5_ifc_modify_flow_table_out_bits { 8862 u8 status[0x8]; 8863 u8 reserved_at_8[0x18]; 8864 8865 u8 syndrome[0x20]; 8866 8867 u8 reserved_at_40[0x40]; 8868 }; 8869 8870 struct mlx5_ifc_modify_flow_table_in_bits { 8871 u8 opcode[0x10]; 8872 u8 reserved_at_10[0x10]; 8873 8874 u8 reserved_at_20[0x10]; 8875 u8 op_mod[0x10]; 8876 8877 u8 other_vport[0x1]; 8878 u8 reserved_at_41[0xf]; 8879 u8 vport_number[0x10]; 8880 8881 u8 reserved_at_60[0x10]; 8882 u8 modify_field_select[0x10]; 8883 8884 u8 table_type[0x8]; 8885 u8 reserved_at_88[0x18]; 8886 8887 u8 reserved_at_a0[0x8]; 8888 u8 table_id[0x18]; 8889 8890 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8891 }; 8892 8893 struct mlx5_ifc_ets_tcn_config_reg_bits { 8894 u8 g[0x1]; 8895 u8 b[0x1]; 8896 u8 r[0x1]; 8897 u8 reserved_at_3[0x9]; 8898 u8 group[0x4]; 8899 u8 reserved_at_10[0x9]; 8900 u8 bw_allocation[0x7]; 8901 8902 u8 reserved_at_20[0xc]; 8903 u8 max_bw_units[0x4]; 8904 u8 reserved_at_30[0x8]; 8905 u8 max_bw_value[0x8]; 8906 }; 8907 8908 struct mlx5_ifc_ets_global_config_reg_bits { 8909 u8 reserved_at_0[0x2]; 8910 u8 r[0x1]; 8911 u8 reserved_at_3[0x1d]; 8912 8913 u8 reserved_at_20[0xc]; 8914 u8 max_bw_units[0x4]; 8915 u8 reserved_at_30[0x8]; 8916 u8 max_bw_value[0x8]; 8917 }; 8918 8919 struct mlx5_ifc_qetc_reg_bits { 8920 u8 reserved_at_0[0x8]; 8921 u8 port_number[0x8]; 8922 u8 reserved_at_10[0x30]; 8923 8924 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8925 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8926 }; 8927 8928 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8929 u8 e[0x1]; 8930 u8 reserved_at_01[0x0b]; 8931 u8 prio[0x04]; 8932 }; 8933 8934 struct mlx5_ifc_qpdpm_reg_bits { 8935 u8 reserved_at_0[0x8]; 8936 u8 local_port[0x8]; 8937 u8 reserved_at_10[0x10]; 8938 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8939 }; 8940 8941 struct mlx5_ifc_qpts_reg_bits { 8942 u8 reserved_at_0[0x8]; 8943 u8 local_port[0x8]; 8944 u8 reserved_at_10[0x2d]; 8945 u8 trust_state[0x3]; 8946 }; 8947 8948 struct mlx5_ifc_pptb_reg_bits { 8949 u8 reserved_at_0[0x2]; 8950 u8 mm[0x2]; 8951 u8 reserved_at_4[0x4]; 8952 u8 local_port[0x8]; 8953 u8 reserved_at_10[0x6]; 8954 u8 cm[0x1]; 8955 u8 um[0x1]; 8956 u8 pm[0x8]; 8957 8958 u8 prio_x_buff[0x20]; 8959 8960 u8 pm_msb[0x8]; 8961 u8 reserved_at_48[0x10]; 8962 u8 ctrl_buff[0x4]; 8963 u8 untagged_buff[0x4]; 8964 }; 8965 8966 struct mlx5_ifc_pbmc_reg_bits { 8967 u8 reserved_at_0[0x8]; 8968 u8 local_port[0x8]; 8969 u8 reserved_at_10[0x10]; 8970 8971 u8 xoff_timer_value[0x10]; 8972 u8 xoff_refresh[0x10]; 8973 8974 u8 reserved_at_40[0x9]; 8975 u8 fullness_threshold[0x7]; 8976 u8 port_buffer_size[0x10]; 8977 8978 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8979 8980 u8 reserved_at_2e0[0x40]; 8981 }; 8982 8983 struct mlx5_ifc_qtct_reg_bits { 8984 u8 reserved_at_0[0x8]; 8985 u8 port_number[0x8]; 8986 u8 reserved_at_10[0xd]; 8987 u8 prio[0x3]; 8988 8989 u8 reserved_at_20[0x1d]; 8990 u8 tclass[0x3]; 8991 }; 8992 8993 struct mlx5_ifc_mcia_reg_bits { 8994 u8 l[0x1]; 8995 u8 reserved_at_1[0x7]; 8996 u8 module[0x8]; 8997 u8 reserved_at_10[0x8]; 8998 u8 status[0x8]; 8999 9000 u8 i2c_device_address[0x8]; 9001 u8 page_number[0x8]; 9002 u8 device_address[0x10]; 9003 9004 u8 reserved_at_40[0x10]; 9005 u8 size[0x10]; 9006 9007 u8 reserved_at_60[0x20]; 9008 9009 u8 dword_0[0x20]; 9010 u8 dword_1[0x20]; 9011 u8 dword_2[0x20]; 9012 u8 dword_3[0x20]; 9013 u8 dword_4[0x20]; 9014 u8 dword_5[0x20]; 9015 u8 dword_6[0x20]; 9016 u8 dword_7[0x20]; 9017 u8 dword_8[0x20]; 9018 u8 dword_9[0x20]; 9019 u8 dword_10[0x20]; 9020 u8 dword_11[0x20]; 9021 }; 9022 9023 struct mlx5_ifc_dcbx_param_bits { 9024 u8 dcbx_cee_cap[0x1]; 9025 u8 dcbx_ieee_cap[0x1]; 9026 u8 dcbx_standby_cap[0x1]; 9027 u8 reserved_at_0[0x5]; 9028 u8 port_number[0x8]; 9029 u8 reserved_at_10[0xa]; 9030 u8 max_application_table_size[6]; 9031 u8 reserved_at_20[0x15]; 9032 u8 version_oper[0x3]; 9033 u8 reserved_at_38[5]; 9034 u8 version_admin[0x3]; 9035 u8 willing_admin[0x1]; 9036 u8 reserved_at_41[0x3]; 9037 u8 pfc_cap_oper[0x4]; 9038 u8 reserved_at_48[0x4]; 9039 u8 pfc_cap_admin[0x4]; 9040 u8 reserved_at_50[0x4]; 9041 u8 num_of_tc_oper[0x4]; 9042 u8 reserved_at_58[0x4]; 9043 u8 num_of_tc_admin[0x4]; 9044 u8 remote_willing[0x1]; 9045 u8 reserved_at_61[3]; 9046 u8 remote_pfc_cap[4]; 9047 u8 reserved_at_68[0x14]; 9048 u8 remote_num_of_tc[0x4]; 9049 u8 reserved_at_80[0x18]; 9050 u8 error[0x8]; 9051 u8 reserved_at_a0[0x160]; 9052 }; 9053 9054 struct mlx5_ifc_lagc_bits { 9055 u8 reserved_at_0[0x1d]; 9056 u8 lag_state[0x3]; 9057 9058 u8 reserved_at_20[0x14]; 9059 u8 tx_remap_affinity_2[0x4]; 9060 u8 reserved_at_38[0x4]; 9061 u8 tx_remap_affinity_1[0x4]; 9062 }; 9063 9064 struct mlx5_ifc_create_lag_out_bits { 9065 u8 status[0x8]; 9066 u8 reserved_at_8[0x18]; 9067 9068 u8 syndrome[0x20]; 9069 9070 u8 reserved_at_40[0x40]; 9071 }; 9072 9073 struct mlx5_ifc_create_lag_in_bits { 9074 u8 opcode[0x10]; 9075 u8 reserved_at_10[0x10]; 9076 9077 u8 reserved_at_20[0x10]; 9078 u8 op_mod[0x10]; 9079 9080 struct mlx5_ifc_lagc_bits ctx; 9081 }; 9082 9083 struct mlx5_ifc_modify_lag_out_bits { 9084 u8 status[0x8]; 9085 u8 reserved_at_8[0x18]; 9086 9087 u8 syndrome[0x20]; 9088 9089 u8 reserved_at_40[0x40]; 9090 }; 9091 9092 struct mlx5_ifc_modify_lag_in_bits { 9093 u8 opcode[0x10]; 9094 u8 reserved_at_10[0x10]; 9095 9096 u8 reserved_at_20[0x10]; 9097 u8 op_mod[0x10]; 9098 9099 u8 reserved_at_40[0x20]; 9100 u8 field_select[0x20]; 9101 9102 struct mlx5_ifc_lagc_bits ctx; 9103 }; 9104 9105 struct mlx5_ifc_query_lag_out_bits { 9106 u8 status[0x8]; 9107 u8 reserved_at_8[0x18]; 9108 9109 u8 syndrome[0x20]; 9110 9111 u8 reserved_at_40[0x40]; 9112 9113 struct mlx5_ifc_lagc_bits ctx; 9114 }; 9115 9116 struct mlx5_ifc_query_lag_in_bits { 9117 u8 opcode[0x10]; 9118 u8 reserved_at_10[0x10]; 9119 9120 u8 reserved_at_20[0x10]; 9121 u8 op_mod[0x10]; 9122 9123 u8 reserved_at_40[0x40]; 9124 }; 9125 9126 struct mlx5_ifc_destroy_lag_out_bits { 9127 u8 status[0x8]; 9128 u8 reserved_at_8[0x18]; 9129 9130 u8 syndrome[0x20]; 9131 9132 u8 reserved_at_40[0x40]; 9133 }; 9134 9135 struct mlx5_ifc_destroy_lag_in_bits { 9136 u8 opcode[0x10]; 9137 u8 reserved_at_10[0x10]; 9138 9139 u8 reserved_at_20[0x10]; 9140 u8 op_mod[0x10]; 9141 9142 u8 reserved_at_40[0x40]; 9143 }; 9144 9145 struct mlx5_ifc_create_vport_lag_out_bits { 9146 u8 status[0x8]; 9147 u8 reserved_at_8[0x18]; 9148 9149 u8 syndrome[0x20]; 9150 9151 u8 reserved_at_40[0x40]; 9152 }; 9153 9154 struct mlx5_ifc_create_vport_lag_in_bits { 9155 u8 opcode[0x10]; 9156 u8 reserved_at_10[0x10]; 9157 9158 u8 reserved_at_20[0x10]; 9159 u8 op_mod[0x10]; 9160 9161 u8 reserved_at_40[0x40]; 9162 }; 9163 9164 struct mlx5_ifc_destroy_vport_lag_out_bits { 9165 u8 status[0x8]; 9166 u8 reserved_at_8[0x18]; 9167 9168 u8 syndrome[0x20]; 9169 9170 u8 reserved_at_40[0x40]; 9171 }; 9172 9173 struct mlx5_ifc_destroy_vport_lag_in_bits { 9174 u8 opcode[0x10]; 9175 u8 reserved_at_10[0x10]; 9176 9177 u8 reserved_at_20[0x10]; 9178 u8 op_mod[0x10]; 9179 9180 u8 reserved_at_40[0x40]; 9181 }; 9182 9183 struct mlx5_ifc_alloc_memic_in_bits { 9184 u8 opcode[0x10]; 9185 u8 reserved_at_10[0x10]; 9186 9187 u8 reserved_at_20[0x10]; 9188 u8 op_mod[0x10]; 9189 9190 u8 reserved_at_30[0x20]; 9191 9192 u8 reserved_at_40[0x18]; 9193 u8 log_memic_addr_alignment[0x8]; 9194 9195 u8 range_start_addr[0x40]; 9196 9197 u8 range_size[0x20]; 9198 9199 u8 memic_size[0x20]; 9200 }; 9201 9202 struct mlx5_ifc_alloc_memic_out_bits { 9203 u8 status[0x8]; 9204 u8 reserved_at_8[0x18]; 9205 9206 u8 syndrome[0x20]; 9207 9208 u8 memic_start_addr[0x40]; 9209 }; 9210 9211 struct mlx5_ifc_dealloc_memic_in_bits { 9212 u8 opcode[0x10]; 9213 u8 reserved_at_10[0x10]; 9214 9215 u8 reserved_at_20[0x10]; 9216 u8 op_mod[0x10]; 9217 9218 u8 reserved_at_40[0x40]; 9219 9220 u8 memic_start_addr[0x40]; 9221 9222 u8 memic_size[0x20]; 9223 9224 u8 reserved_at_e0[0x20]; 9225 }; 9226 9227 struct mlx5_ifc_dealloc_memic_out_bits { 9228 u8 status[0x8]; 9229 u8 reserved_at_8[0x18]; 9230 9231 u8 syndrome[0x20]; 9232 9233 u8 reserved_at_40[0x40]; 9234 }; 9235 9236 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9237 u8 opcode[0x10]; 9238 u8 uid[0x10]; 9239 9240 u8 reserved_at_20[0x10]; 9241 u8 obj_type[0x10]; 9242 9243 u8 obj_id[0x20]; 9244 9245 u8 reserved_at_60[0x20]; 9246 }; 9247 9248 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9249 u8 status[0x8]; 9250 u8 reserved_at_8[0x18]; 9251 9252 u8 syndrome[0x20]; 9253 9254 u8 obj_id[0x20]; 9255 9256 u8 reserved_at_60[0x20]; 9257 }; 9258 9259 struct mlx5_ifc_umem_bits { 9260 u8 modify_field_select[0x40]; 9261 9262 u8 reserved_at_40[0x5b]; 9263 u8 log_page_size[0x5]; 9264 9265 u8 page_offset[0x20]; 9266 9267 u8 num_of_mtt[0x40]; 9268 9269 struct mlx5_ifc_mtt_bits mtt[0]; 9270 }; 9271 9272 struct mlx5_ifc_uctx_bits { 9273 u8 modify_field_select[0x40]; 9274 9275 u8 reserved_at_40[0x1c0]; 9276 }; 9277 9278 struct mlx5_ifc_create_umem_in_bits { 9279 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9280 struct mlx5_ifc_umem_bits umem; 9281 }; 9282 9283 struct mlx5_ifc_create_uctx_in_bits { 9284 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9285 struct mlx5_ifc_uctx_bits uctx; 9286 }; 9287 9288 struct mlx5_ifc_mtrc_string_db_param_bits { 9289 u8 string_db_base_address[0x20]; 9290 9291 u8 reserved_at_20[0x8]; 9292 u8 string_db_size[0x18]; 9293 }; 9294 9295 struct mlx5_ifc_mtrc_cap_bits { 9296 u8 trace_owner[0x1]; 9297 u8 trace_to_memory[0x1]; 9298 u8 reserved_at_2[0x4]; 9299 u8 trc_ver[0x2]; 9300 u8 reserved_at_8[0x14]; 9301 u8 num_string_db[0x4]; 9302 9303 u8 first_string_trace[0x8]; 9304 u8 num_string_trace[0x8]; 9305 u8 reserved_at_30[0x28]; 9306 9307 u8 log_max_trace_buffer_size[0x8]; 9308 9309 u8 reserved_at_60[0x20]; 9310 9311 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9312 9313 u8 reserved_at_280[0x180]; 9314 }; 9315 9316 struct mlx5_ifc_mtrc_conf_bits { 9317 u8 reserved_at_0[0x1c]; 9318 u8 trace_mode[0x4]; 9319 u8 reserved_at_20[0x18]; 9320 u8 log_trace_buffer_size[0x8]; 9321 u8 trace_mkey[0x20]; 9322 u8 reserved_at_60[0x3a0]; 9323 }; 9324 9325 struct mlx5_ifc_mtrc_stdb_bits { 9326 u8 string_db_index[0x4]; 9327 u8 reserved_at_4[0x4]; 9328 u8 read_size[0x18]; 9329 u8 start_offset[0x20]; 9330 u8 string_db_data[0]; 9331 }; 9332 9333 struct mlx5_ifc_mtrc_ctrl_bits { 9334 u8 trace_status[0x2]; 9335 u8 reserved_at_2[0x2]; 9336 u8 arm_event[0x1]; 9337 u8 reserved_at_5[0xb]; 9338 u8 modify_field_select[0x10]; 9339 u8 reserved_at_20[0x2b]; 9340 u8 current_timestamp52_32[0x15]; 9341 u8 current_timestamp31_0[0x20]; 9342 u8 reserved_at_80[0x180]; 9343 }; 9344 9345 #endif /* MLX5_IFC_H */ 9346