1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 91 MLX5_OBJ_TYPE_MKEY = 0xff01, 92 MLX5_OBJ_TYPE_QP = 0xff02, 93 MLX5_OBJ_TYPE_PSV = 0xff03, 94 MLX5_OBJ_TYPE_RMP = 0xff04, 95 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 96 MLX5_OBJ_TYPE_RQ = 0xff06, 97 MLX5_OBJ_TYPE_SQ = 0xff07, 98 MLX5_OBJ_TYPE_TIR = 0xff08, 99 MLX5_OBJ_TYPE_TIS = 0xff09, 100 MLX5_OBJ_TYPE_DCT = 0xff0a, 101 MLX5_OBJ_TYPE_XRQ = 0xff0b, 102 MLX5_OBJ_TYPE_RQT = 0xff0e, 103 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 104 MLX5_OBJ_TYPE_CQ = 0xff10, 105 }; 106 107 enum { 108 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 109 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 110 MLX5_CMD_OP_INIT_HCA = 0x102, 111 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 112 MLX5_CMD_OP_ENABLE_HCA = 0x104, 113 MLX5_CMD_OP_DISABLE_HCA = 0x105, 114 MLX5_CMD_OP_QUERY_PAGES = 0x107, 115 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 116 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 117 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 118 MLX5_CMD_OP_SET_ISSI = 0x10b, 119 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 120 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 121 MLX5_CMD_OP_ALLOC_SF = 0x113, 122 MLX5_CMD_OP_DEALLOC_SF = 0x114, 123 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 124 MLX5_CMD_OP_RESUME_VHCA = 0x116, 125 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 126 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 127 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 128 MLX5_CMD_OP_CREATE_MKEY = 0x200, 129 MLX5_CMD_OP_QUERY_MKEY = 0x201, 130 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 131 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 132 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 133 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 134 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 135 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 304 MLX5_CMD_OP_MAX 305 }; 306 307 /* Valid range for general commands that don't work over an object */ 308 enum { 309 MLX5_CMD_OP_GENERAL_START = 0xb00, 310 MLX5_CMD_OP_GENERAL_END = 0xd00, 311 }; 312 313 struct mlx5_ifc_flow_table_fields_supported_bits { 314 u8 outer_dmac[0x1]; 315 u8 outer_smac[0x1]; 316 u8 outer_ether_type[0x1]; 317 u8 outer_ip_version[0x1]; 318 u8 outer_first_prio[0x1]; 319 u8 outer_first_cfi[0x1]; 320 u8 outer_first_vid[0x1]; 321 u8 outer_ipv4_ttl[0x1]; 322 u8 outer_second_prio[0x1]; 323 u8 outer_second_cfi[0x1]; 324 u8 outer_second_vid[0x1]; 325 u8 reserved_at_b[0x1]; 326 u8 outer_sip[0x1]; 327 u8 outer_dip[0x1]; 328 u8 outer_frag[0x1]; 329 u8 outer_ip_protocol[0x1]; 330 u8 outer_ip_ecn[0x1]; 331 u8 outer_ip_dscp[0x1]; 332 u8 outer_udp_sport[0x1]; 333 u8 outer_udp_dport[0x1]; 334 u8 outer_tcp_sport[0x1]; 335 u8 outer_tcp_dport[0x1]; 336 u8 outer_tcp_flags[0x1]; 337 u8 outer_gre_protocol[0x1]; 338 u8 outer_gre_key[0x1]; 339 u8 outer_vxlan_vni[0x1]; 340 u8 outer_geneve_vni[0x1]; 341 u8 outer_geneve_oam[0x1]; 342 u8 outer_geneve_protocol_type[0x1]; 343 u8 outer_geneve_opt_len[0x1]; 344 u8 source_vhca_port[0x1]; 345 u8 source_eswitch_port[0x1]; 346 347 u8 inner_dmac[0x1]; 348 u8 inner_smac[0x1]; 349 u8 inner_ether_type[0x1]; 350 u8 inner_ip_version[0x1]; 351 u8 inner_first_prio[0x1]; 352 u8 inner_first_cfi[0x1]; 353 u8 inner_first_vid[0x1]; 354 u8 reserved_at_27[0x1]; 355 u8 inner_second_prio[0x1]; 356 u8 inner_second_cfi[0x1]; 357 u8 inner_second_vid[0x1]; 358 u8 reserved_at_2b[0x1]; 359 u8 inner_sip[0x1]; 360 u8 inner_dip[0x1]; 361 u8 inner_frag[0x1]; 362 u8 inner_ip_protocol[0x1]; 363 u8 inner_ip_ecn[0x1]; 364 u8 inner_ip_dscp[0x1]; 365 u8 inner_udp_sport[0x1]; 366 u8 inner_udp_dport[0x1]; 367 u8 inner_tcp_sport[0x1]; 368 u8 inner_tcp_dport[0x1]; 369 u8 inner_tcp_flags[0x1]; 370 u8 reserved_at_37[0x9]; 371 372 u8 geneve_tlv_option_0_data[0x1]; 373 u8 geneve_tlv_option_0_exist[0x1]; 374 u8 reserved_at_42[0x3]; 375 u8 outer_first_mpls_over_udp[0x4]; 376 u8 outer_first_mpls_over_gre[0x4]; 377 u8 inner_first_mpls[0x4]; 378 u8 outer_first_mpls[0x4]; 379 u8 reserved_at_55[0x2]; 380 u8 outer_esp_spi[0x1]; 381 u8 reserved_at_58[0x2]; 382 u8 bth_dst_qp[0x1]; 383 u8 reserved_at_5b[0x5]; 384 385 u8 reserved_at_60[0x18]; 386 u8 metadata_reg_c_7[0x1]; 387 u8 metadata_reg_c_6[0x1]; 388 u8 metadata_reg_c_5[0x1]; 389 u8 metadata_reg_c_4[0x1]; 390 u8 metadata_reg_c_3[0x1]; 391 u8 metadata_reg_c_2[0x1]; 392 u8 metadata_reg_c_1[0x1]; 393 u8 metadata_reg_c_0[0x1]; 394 }; 395 396 struct mlx5_ifc_flow_table_fields_supported_2_bits { 397 u8 reserved_at_0[0xe]; 398 u8 bth_opcode[0x1]; 399 u8 reserved_at_f[0x11]; 400 401 u8 reserved_at_20[0x60]; 402 }; 403 404 struct mlx5_ifc_flow_table_prop_layout_bits { 405 u8 ft_support[0x1]; 406 u8 reserved_at_1[0x1]; 407 u8 flow_counter[0x1]; 408 u8 flow_modify_en[0x1]; 409 u8 modify_root[0x1]; 410 u8 identified_miss_table_mode[0x1]; 411 u8 flow_table_modify[0x1]; 412 u8 reformat[0x1]; 413 u8 decap[0x1]; 414 u8 reserved_at_9[0x1]; 415 u8 pop_vlan[0x1]; 416 u8 push_vlan[0x1]; 417 u8 reserved_at_c[0x1]; 418 u8 pop_vlan_2[0x1]; 419 u8 push_vlan_2[0x1]; 420 u8 reformat_and_vlan_action[0x1]; 421 u8 reserved_at_10[0x1]; 422 u8 sw_owner[0x1]; 423 u8 reformat_l3_tunnel_to_l2[0x1]; 424 u8 reformat_l2_to_l3_tunnel[0x1]; 425 u8 reformat_and_modify_action[0x1]; 426 u8 ignore_flow_level[0x1]; 427 u8 reserved_at_16[0x1]; 428 u8 table_miss_action_domain[0x1]; 429 u8 termination_table[0x1]; 430 u8 reformat_and_fwd_to_table[0x1]; 431 u8 reserved_at_1a[0x2]; 432 u8 ipsec_encrypt[0x1]; 433 u8 ipsec_decrypt[0x1]; 434 u8 sw_owner_v2[0x1]; 435 u8 reserved_at_1f[0x1]; 436 437 u8 termination_table_raw_traffic[0x1]; 438 u8 reserved_at_21[0x1]; 439 u8 log_max_ft_size[0x6]; 440 u8 log_max_modify_header_context[0x8]; 441 u8 max_modify_header_actions[0x8]; 442 u8 max_ft_level[0x8]; 443 444 u8 reserved_at_40[0x20]; 445 446 u8 reserved_at_60[0x2]; 447 u8 reformat_insert[0x1]; 448 u8 reformat_remove[0x1]; 449 u8 reserver_at_64[0x14]; 450 u8 log_max_ft_num[0x8]; 451 452 u8 reserved_at_80[0x10]; 453 u8 log_max_flow_counter[0x8]; 454 u8 log_max_destination[0x8]; 455 456 u8 reserved_at_a0[0x18]; 457 u8 log_max_flow[0x8]; 458 459 u8 reserved_at_c0[0x40]; 460 461 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 462 463 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 464 }; 465 466 struct mlx5_ifc_odp_per_transport_service_cap_bits { 467 u8 send[0x1]; 468 u8 receive[0x1]; 469 u8 write[0x1]; 470 u8 read[0x1]; 471 u8 atomic[0x1]; 472 u8 srq_receive[0x1]; 473 u8 reserved_at_6[0x1a]; 474 }; 475 476 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 477 u8 smac_47_16[0x20]; 478 479 u8 smac_15_0[0x10]; 480 u8 ethertype[0x10]; 481 482 u8 dmac_47_16[0x20]; 483 484 u8 dmac_15_0[0x10]; 485 u8 first_prio[0x3]; 486 u8 first_cfi[0x1]; 487 u8 first_vid[0xc]; 488 489 u8 ip_protocol[0x8]; 490 u8 ip_dscp[0x6]; 491 u8 ip_ecn[0x2]; 492 u8 cvlan_tag[0x1]; 493 u8 svlan_tag[0x1]; 494 u8 frag[0x1]; 495 u8 ip_version[0x4]; 496 u8 tcp_flags[0x9]; 497 498 u8 tcp_sport[0x10]; 499 u8 tcp_dport[0x10]; 500 501 u8 reserved_at_c0[0x10]; 502 u8 ipv4_ihl[0x4]; 503 u8 reserved_at_c4[0x4]; 504 505 u8 ttl_hoplimit[0x8]; 506 507 u8 udp_sport[0x10]; 508 u8 udp_dport[0x10]; 509 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 511 512 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 513 }; 514 515 struct mlx5_ifc_nvgre_key_bits { 516 u8 hi[0x18]; 517 u8 lo[0x8]; 518 }; 519 520 union mlx5_ifc_gre_key_bits { 521 struct mlx5_ifc_nvgre_key_bits nvgre; 522 u8 key[0x20]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_misc_bits { 526 u8 gre_c_present[0x1]; 527 u8 reserved_at_1[0x1]; 528 u8 gre_k_present[0x1]; 529 u8 gre_s_present[0x1]; 530 u8 source_vhca_port[0x4]; 531 u8 source_sqn[0x18]; 532 533 u8 source_eswitch_owner_vhca_id[0x10]; 534 u8 source_port[0x10]; 535 536 u8 outer_second_prio[0x3]; 537 u8 outer_second_cfi[0x1]; 538 u8 outer_second_vid[0xc]; 539 u8 inner_second_prio[0x3]; 540 u8 inner_second_cfi[0x1]; 541 u8 inner_second_vid[0xc]; 542 543 u8 outer_second_cvlan_tag[0x1]; 544 u8 inner_second_cvlan_tag[0x1]; 545 u8 outer_second_svlan_tag[0x1]; 546 u8 inner_second_svlan_tag[0x1]; 547 u8 reserved_at_64[0xc]; 548 u8 gre_protocol[0x10]; 549 550 union mlx5_ifc_gre_key_bits gre_key; 551 552 u8 vxlan_vni[0x18]; 553 u8 bth_opcode[0x8]; 554 555 u8 geneve_vni[0x18]; 556 u8 reserved_at_d8[0x6]; 557 u8 geneve_tlv_option_0_exist[0x1]; 558 u8 geneve_oam[0x1]; 559 560 u8 reserved_at_e0[0xc]; 561 u8 outer_ipv6_flow_label[0x14]; 562 563 u8 reserved_at_100[0xc]; 564 u8 inner_ipv6_flow_label[0x14]; 565 566 u8 reserved_at_120[0xa]; 567 u8 geneve_opt_len[0x6]; 568 u8 geneve_protocol_type[0x10]; 569 570 u8 reserved_at_140[0x8]; 571 u8 bth_dst_qp[0x18]; 572 u8 reserved_at_160[0x20]; 573 u8 outer_esp_spi[0x20]; 574 u8 reserved_at_1a0[0x60]; 575 }; 576 577 struct mlx5_ifc_fte_match_mpls_bits { 578 u8 mpls_label[0x14]; 579 u8 mpls_exp[0x3]; 580 u8 mpls_s_bos[0x1]; 581 u8 mpls_ttl[0x8]; 582 }; 583 584 struct mlx5_ifc_fte_match_set_misc2_bits { 585 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 586 587 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 588 589 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 590 591 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 592 593 u8 metadata_reg_c_7[0x20]; 594 595 u8 metadata_reg_c_6[0x20]; 596 597 u8 metadata_reg_c_5[0x20]; 598 599 u8 metadata_reg_c_4[0x20]; 600 601 u8 metadata_reg_c_3[0x20]; 602 603 u8 metadata_reg_c_2[0x20]; 604 605 u8 metadata_reg_c_1[0x20]; 606 607 u8 metadata_reg_c_0[0x20]; 608 609 u8 metadata_reg_a[0x20]; 610 611 u8 reserved_at_1a0[0x60]; 612 }; 613 614 struct mlx5_ifc_fte_match_set_misc3_bits { 615 u8 inner_tcp_seq_num[0x20]; 616 617 u8 outer_tcp_seq_num[0x20]; 618 619 u8 inner_tcp_ack_num[0x20]; 620 621 u8 outer_tcp_ack_num[0x20]; 622 623 u8 reserved_at_80[0x8]; 624 u8 outer_vxlan_gpe_vni[0x18]; 625 626 u8 outer_vxlan_gpe_next_protocol[0x8]; 627 u8 outer_vxlan_gpe_flags[0x8]; 628 u8 reserved_at_b0[0x10]; 629 630 u8 icmp_header_data[0x20]; 631 632 u8 icmpv6_header_data[0x20]; 633 634 u8 icmp_type[0x8]; 635 u8 icmp_code[0x8]; 636 u8 icmpv6_type[0x8]; 637 u8 icmpv6_code[0x8]; 638 639 u8 geneve_tlv_option_0_data[0x20]; 640 641 u8 gtpu_teid[0x20]; 642 643 u8 gtpu_msg_type[0x8]; 644 u8 gtpu_msg_flags[0x8]; 645 u8 reserved_at_170[0x10]; 646 647 u8 gtpu_dw_2[0x20]; 648 649 u8 gtpu_first_ext_dw_0[0x20]; 650 651 u8 gtpu_dw_0[0x20]; 652 653 u8 reserved_at_1e0[0x20]; 654 }; 655 656 struct mlx5_ifc_fte_match_set_misc4_bits { 657 u8 prog_sample_field_value_0[0x20]; 658 659 u8 prog_sample_field_id_0[0x20]; 660 661 u8 prog_sample_field_value_1[0x20]; 662 663 u8 prog_sample_field_id_1[0x20]; 664 665 u8 prog_sample_field_value_2[0x20]; 666 667 u8 prog_sample_field_id_2[0x20]; 668 669 u8 prog_sample_field_value_3[0x20]; 670 671 u8 prog_sample_field_id_3[0x20]; 672 673 u8 reserved_at_100[0x100]; 674 }; 675 676 struct mlx5_ifc_fte_match_set_misc5_bits { 677 u8 macsec_tag_0[0x20]; 678 679 u8 macsec_tag_1[0x20]; 680 681 u8 macsec_tag_2[0x20]; 682 683 u8 macsec_tag_3[0x20]; 684 685 u8 tunnel_header_0[0x20]; 686 687 u8 tunnel_header_1[0x20]; 688 689 u8 tunnel_header_2[0x20]; 690 691 u8 tunnel_header_3[0x20]; 692 693 u8 reserved_at_100[0x100]; 694 }; 695 696 struct mlx5_ifc_cmd_pas_bits { 697 u8 pa_h[0x20]; 698 699 u8 pa_l[0x14]; 700 u8 reserved_at_34[0xc]; 701 }; 702 703 struct mlx5_ifc_uint64_bits { 704 u8 hi[0x20]; 705 706 u8 lo[0x20]; 707 }; 708 709 enum { 710 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 711 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 712 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 713 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 714 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 715 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 716 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 717 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 718 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 719 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 720 }; 721 722 struct mlx5_ifc_ads_bits { 723 u8 fl[0x1]; 724 u8 free_ar[0x1]; 725 u8 reserved_at_2[0xe]; 726 u8 pkey_index[0x10]; 727 728 u8 reserved_at_20[0x8]; 729 u8 grh[0x1]; 730 u8 mlid[0x7]; 731 u8 rlid[0x10]; 732 733 u8 ack_timeout[0x5]; 734 u8 reserved_at_45[0x3]; 735 u8 src_addr_index[0x8]; 736 u8 reserved_at_50[0x4]; 737 u8 stat_rate[0x4]; 738 u8 hop_limit[0x8]; 739 740 u8 reserved_at_60[0x4]; 741 u8 tclass[0x8]; 742 u8 flow_label[0x14]; 743 744 u8 rgid_rip[16][0x8]; 745 746 u8 reserved_at_100[0x4]; 747 u8 f_dscp[0x1]; 748 u8 f_ecn[0x1]; 749 u8 reserved_at_106[0x1]; 750 u8 f_eth_prio[0x1]; 751 u8 ecn[0x2]; 752 u8 dscp[0x6]; 753 u8 udp_sport[0x10]; 754 755 u8 dei_cfi[0x1]; 756 u8 eth_prio[0x3]; 757 u8 sl[0x4]; 758 u8 vhca_port_num[0x8]; 759 u8 rmac_47_32[0x10]; 760 761 u8 rmac_31_0[0x20]; 762 }; 763 764 struct mlx5_ifc_flow_table_nic_cap_bits { 765 u8 nic_rx_multi_path_tirs[0x1]; 766 u8 nic_rx_multi_path_tirs_fts[0x1]; 767 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 768 u8 reserved_at_3[0x4]; 769 u8 sw_owner_reformat_supported[0x1]; 770 u8 reserved_at_8[0x18]; 771 772 u8 encap_general_header[0x1]; 773 u8 reserved_at_21[0xa]; 774 u8 log_max_packet_reformat_context[0x5]; 775 u8 reserved_at_30[0x6]; 776 u8 max_encap_header_size[0xa]; 777 u8 reserved_at_40[0x1c0]; 778 779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 780 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 784 785 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 786 787 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 788 789 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 790 791 u8 reserved_at_e00[0x700]; 792 793 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 794 795 u8 reserved_at_1580[0x280]; 796 797 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 798 799 u8 reserved_at_1880[0x780]; 800 801 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 802 803 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 804 805 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 806 807 u8 reserved_at_20c0[0x5f40]; 808 }; 809 810 struct mlx5_ifc_port_selection_cap_bits { 811 u8 reserved_at_0[0x10]; 812 u8 port_select_flow_table[0x1]; 813 u8 reserved_at_11[0xf]; 814 815 u8 reserved_at_20[0x1e0]; 816 817 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 818 819 u8 reserved_at_400[0x7c00]; 820 }; 821 822 enum { 823 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 824 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 825 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 826 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 827 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 828 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 829 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 830 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 831 }; 832 833 struct mlx5_ifc_flow_table_eswitch_cap_bits { 834 u8 fdb_to_vport_reg_c_id[0x8]; 835 u8 reserved_at_8[0xd]; 836 u8 fdb_modify_header_fwd_to_table[0x1]; 837 u8 fdb_ipv4_ttl_modify[0x1]; 838 u8 flow_source[0x1]; 839 u8 reserved_at_18[0x2]; 840 u8 multi_fdb_encap[0x1]; 841 u8 egress_acl_forward_to_vport[0x1]; 842 u8 fdb_multi_path_to_table[0x1]; 843 u8 reserved_at_1d[0x3]; 844 845 u8 reserved_at_20[0x1e0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 852 853 u8 reserved_at_800[0x1000]; 854 855 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 856 857 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 858 859 u8 sw_steering_uplink_icm_address_rx[0x40]; 860 861 u8 sw_steering_uplink_icm_address_tx[0x40]; 862 863 u8 reserved_at_1900[0x6700]; 864 }; 865 866 enum { 867 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 868 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 869 }; 870 871 struct mlx5_ifc_e_switch_cap_bits { 872 u8 vport_svlan_strip[0x1]; 873 u8 vport_cvlan_strip[0x1]; 874 u8 vport_svlan_insert[0x1]; 875 u8 vport_cvlan_insert_if_not_exist[0x1]; 876 u8 vport_cvlan_insert_overwrite[0x1]; 877 u8 reserved_at_5[0x2]; 878 u8 esw_shared_ingress_acl[0x1]; 879 u8 esw_uplink_ingress_acl[0x1]; 880 u8 root_ft_on_other_esw[0x1]; 881 u8 reserved_at_a[0xf]; 882 u8 esw_functions_changed[0x1]; 883 u8 reserved_at_1a[0x1]; 884 u8 ecpf_vport_exists[0x1]; 885 u8 counter_eswitch_affinity[0x1]; 886 u8 merged_eswitch[0x1]; 887 u8 nic_vport_node_guid_modify[0x1]; 888 u8 nic_vport_port_guid_modify[0x1]; 889 890 u8 vxlan_encap_decap[0x1]; 891 u8 nvgre_encap_decap[0x1]; 892 u8 reserved_at_22[0x1]; 893 u8 log_max_fdb_encap_uplink[0x5]; 894 u8 reserved_at_21[0x3]; 895 u8 log_max_packet_reformat_context[0x5]; 896 u8 reserved_2b[0x6]; 897 u8 max_encap_header_size[0xa]; 898 899 u8 reserved_at_40[0xb]; 900 u8 log_max_esw_sf[0x5]; 901 u8 esw_sf_base_id[0x10]; 902 903 u8 reserved_at_60[0x7a0]; 904 905 }; 906 907 struct mlx5_ifc_qos_cap_bits { 908 u8 packet_pacing[0x1]; 909 u8 esw_scheduling[0x1]; 910 u8 esw_bw_share[0x1]; 911 u8 esw_rate_limit[0x1]; 912 u8 reserved_at_4[0x1]; 913 u8 packet_pacing_burst_bound[0x1]; 914 u8 packet_pacing_typical_size[0x1]; 915 u8 reserved_at_7[0x1]; 916 u8 nic_sq_scheduling[0x1]; 917 u8 nic_bw_share[0x1]; 918 u8 nic_rate_limit[0x1]; 919 u8 packet_pacing_uid[0x1]; 920 u8 log_esw_max_sched_depth[0x4]; 921 u8 reserved_at_10[0x10]; 922 923 u8 reserved_at_20[0xb]; 924 u8 log_max_qos_nic_queue_group[0x5]; 925 u8 reserved_at_30[0x10]; 926 927 u8 packet_pacing_max_rate[0x20]; 928 929 u8 packet_pacing_min_rate[0x20]; 930 931 u8 reserved_at_80[0x10]; 932 u8 packet_pacing_rate_table_size[0x10]; 933 934 u8 esw_element_type[0x10]; 935 u8 esw_tsar_type[0x10]; 936 937 u8 reserved_at_c0[0x10]; 938 u8 max_qos_para_vport[0x10]; 939 940 u8 max_tsar_bw_share[0x20]; 941 942 u8 reserved_at_100[0x700]; 943 }; 944 945 struct mlx5_ifc_debug_cap_bits { 946 u8 core_dump_general[0x1]; 947 u8 core_dump_qp[0x1]; 948 u8 reserved_at_2[0x7]; 949 u8 resource_dump[0x1]; 950 u8 reserved_at_a[0x16]; 951 952 u8 reserved_at_20[0x2]; 953 u8 stall_detect[0x1]; 954 u8 reserved_at_23[0x1d]; 955 956 u8 reserved_at_40[0x7c0]; 957 }; 958 959 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 960 u8 csum_cap[0x1]; 961 u8 vlan_cap[0x1]; 962 u8 lro_cap[0x1]; 963 u8 lro_psh_flag[0x1]; 964 u8 lro_time_stamp[0x1]; 965 u8 reserved_at_5[0x2]; 966 u8 wqe_vlan_insert[0x1]; 967 u8 self_lb_en_modifiable[0x1]; 968 u8 reserved_at_9[0x2]; 969 u8 max_lso_cap[0x5]; 970 u8 multi_pkt_send_wqe[0x2]; 971 u8 wqe_inline_mode[0x2]; 972 u8 rss_ind_tbl_cap[0x4]; 973 u8 reg_umr_sq[0x1]; 974 u8 scatter_fcs[0x1]; 975 u8 enhanced_multi_pkt_send_wqe[0x1]; 976 u8 tunnel_lso_const_out_ip_id[0x1]; 977 u8 tunnel_lro_gre[0x1]; 978 u8 tunnel_lro_vxlan[0x1]; 979 u8 tunnel_stateless_gre[0x1]; 980 u8 tunnel_stateless_vxlan[0x1]; 981 982 u8 swp[0x1]; 983 u8 swp_csum[0x1]; 984 u8 swp_lso[0x1]; 985 u8 cqe_checksum_full[0x1]; 986 u8 tunnel_stateless_geneve_tx[0x1]; 987 u8 tunnel_stateless_mpls_over_udp[0x1]; 988 u8 tunnel_stateless_mpls_over_gre[0x1]; 989 u8 tunnel_stateless_vxlan_gpe[0x1]; 990 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 991 u8 tunnel_stateless_ip_over_ip[0x1]; 992 u8 insert_trailer[0x1]; 993 u8 reserved_at_2b[0x1]; 994 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 995 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 996 u8 reserved_at_2e[0x2]; 997 u8 max_vxlan_udp_ports[0x8]; 998 u8 reserved_at_38[0x6]; 999 u8 max_geneve_opt_len[0x1]; 1000 u8 tunnel_stateless_geneve_rx[0x1]; 1001 1002 u8 reserved_at_40[0x10]; 1003 u8 lro_min_mss_size[0x10]; 1004 1005 u8 reserved_at_60[0x120]; 1006 1007 u8 lro_timer_supported_periods[4][0x20]; 1008 1009 u8 reserved_at_200[0x600]; 1010 }; 1011 1012 enum { 1013 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1014 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1015 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1016 }; 1017 1018 struct mlx5_ifc_roce_cap_bits { 1019 u8 roce_apm[0x1]; 1020 u8 reserved_at_1[0x3]; 1021 u8 sw_r_roce_src_udp_port[0x1]; 1022 u8 fl_rc_qp_when_roce_disabled[0x1]; 1023 u8 fl_rc_qp_when_roce_enabled[0x1]; 1024 u8 reserved_at_7[0x17]; 1025 u8 qp_ts_format[0x2]; 1026 1027 u8 reserved_at_20[0x60]; 1028 1029 u8 reserved_at_80[0xc]; 1030 u8 l3_type[0x4]; 1031 u8 reserved_at_90[0x8]; 1032 u8 roce_version[0x8]; 1033 1034 u8 reserved_at_a0[0x10]; 1035 u8 r_roce_dest_udp_port[0x10]; 1036 1037 u8 r_roce_max_src_udp_port[0x10]; 1038 u8 r_roce_min_src_udp_port[0x10]; 1039 1040 u8 reserved_at_e0[0x10]; 1041 u8 roce_address_table_size[0x10]; 1042 1043 u8 reserved_at_100[0x700]; 1044 }; 1045 1046 struct mlx5_ifc_sync_steering_in_bits { 1047 u8 opcode[0x10]; 1048 u8 uid[0x10]; 1049 1050 u8 reserved_at_20[0x10]; 1051 u8 op_mod[0x10]; 1052 1053 u8 reserved_at_40[0xc0]; 1054 }; 1055 1056 struct mlx5_ifc_sync_steering_out_bits { 1057 u8 status[0x8]; 1058 u8 reserved_at_8[0x18]; 1059 1060 u8 syndrome[0x20]; 1061 1062 u8 reserved_at_40[0x40]; 1063 }; 1064 1065 struct mlx5_ifc_device_mem_cap_bits { 1066 u8 memic[0x1]; 1067 u8 reserved_at_1[0x1f]; 1068 1069 u8 reserved_at_20[0xb]; 1070 u8 log_min_memic_alloc_size[0x5]; 1071 u8 reserved_at_30[0x8]; 1072 u8 log_max_memic_addr_alignment[0x8]; 1073 1074 u8 memic_bar_start_addr[0x40]; 1075 1076 u8 memic_bar_size[0x20]; 1077 1078 u8 max_memic_size[0x20]; 1079 1080 u8 steering_sw_icm_start_address[0x40]; 1081 1082 u8 reserved_at_100[0x8]; 1083 u8 log_header_modify_sw_icm_size[0x8]; 1084 u8 reserved_at_110[0x2]; 1085 u8 log_sw_icm_alloc_granularity[0x6]; 1086 u8 log_steering_sw_icm_size[0x8]; 1087 1088 u8 reserved_at_120[0x20]; 1089 1090 u8 header_modify_sw_icm_start_address[0x40]; 1091 1092 u8 reserved_at_180[0x80]; 1093 1094 u8 memic_operations[0x20]; 1095 1096 u8 reserved_at_220[0x5e0]; 1097 }; 1098 1099 struct mlx5_ifc_device_event_cap_bits { 1100 u8 user_affiliated_events[4][0x40]; 1101 1102 u8 user_unaffiliated_events[4][0x40]; 1103 }; 1104 1105 struct mlx5_ifc_virtio_emulation_cap_bits { 1106 u8 desc_tunnel_offload_type[0x1]; 1107 u8 eth_frame_offload_type[0x1]; 1108 u8 virtio_version_1_0[0x1]; 1109 u8 device_features_bits_mask[0xd]; 1110 u8 event_mode[0x8]; 1111 u8 virtio_queue_type[0x8]; 1112 1113 u8 max_tunnel_desc[0x10]; 1114 u8 reserved_at_30[0x3]; 1115 u8 log_doorbell_stride[0x5]; 1116 u8 reserved_at_38[0x3]; 1117 u8 log_doorbell_bar_size[0x5]; 1118 1119 u8 doorbell_bar_offset[0x40]; 1120 1121 u8 max_emulated_devices[0x8]; 1122 u8 max_num_virtio_queues[0x18]; 1123 1124 u8 reserved_at_a0[0x60]; 1125 1126 u8 umem_1_buffer_param_a[0x20]; 1127 1128 u8 umem_1_buffer_param_b[0x20]; 1129 1130 u8 umem_2_buffer_param_a[0x20]; 1131 1132 u8 umem_2_buffer_param_b[0x20]; 1133 1134 u8 umem_3_buffer_param_a[0x20]; 1135 1136 u8 umem_3_buffer_param_b[0x20]; 1137 1138 u8 reserved_at_1c0[0x640]; 1139 }; 1140 1141 enum { 1142 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1143 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1144 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1145 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1146 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1147 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1148 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1149 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1150 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1151 }; 1152 1153 enum { 1154 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1155 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1156 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1157 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1163 }; 1164 1165 struct mlx5_ifc_atomic_caps_bits { 1166 u8 reserved_at_0[0x40]; 1167 1168 u8 atomic_req_8B_endianness_mode[0x2]; 1169 u8 reserved_at_42[0x4]; 1170 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1171 1172 u8 reserved_at_47[0x19]; 1173 1174 u8 reserved_at_60[0x20]; 1175 1176 u8 reserved_at_80[0x10]; 1177 u8 atomic_operations[0x10]; 1178 1179 u8 reserved_at_a0[0x10]; 1180 u8 atomic_size_qp[0x10]; 1181 1182 u8 reserved_at_c0[0x10]; 1183 u8 atomic_size_dc[0x10]; 1184 1185 u8 reserved_at_e0[0x720]; 1186 }; 1187 1188 struct mlx5_ifc_odp_cap_bits { 1189 u8 reserved_at_0[0x40]; 1190 1191 u8 sig[0x1]; 1192 u8 reserved_at_41[0x1f]; 1193 1194 u8 reserved_at_60[0x20]; 1195 1196 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1197 1198 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1199 1200 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1201 1202 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1203 1204 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1205 1206 u8 reserved_at_120[0x6E0]; 1207 }; 1208 1209 struct mlx5_ifc_calc_op { 1210 u8 reserved_at_0[0x10]; 1211 u8 reserved_at_10[0x9]; 1212 u8 op_swap_endianness[0x1]; 1213 u8 op_min[0x1]; 1214 u8 op_xor[0x1]; 1215 u8 op_or[0x1]; 1216 u8 op_and[0x1]; 1217 u8 op_max[0x1]; 1218 u8 op_add[0x1]; 1219 }; 1220 1221 struct mlx5_ifc_vector_calc_cap_bits { 1222 u8 calc_matrix[0x1]; 1223 u8 reserved_at_1[0x1f]; 1224 u8 reserved_at_20[0x8]; 1225 u8 max_vec_count[0x8]; 1226 u8 reserved_at_30[0xd]; 1227 u8 max_chunk_size[0x3]; 1228 struct mlx5_ifc_calc_op calc0; 1229 struct mlx5_ifc_calc_op calc1; 1230 struct mlx5_ifc_calc_op calc2; 1231 struct mlx5_ifc_calc_op calc3; 1232 1233 u8 reserved_at_c0[0x720]; 1234 }; 1235 1236 struct mlx5_ifc_tls_cap_bits { 1237 u8 tls_1_2_aes_gcm_128[0x1]; 1238 u8 tls_1_3_aes_gcm_128[0x1]; 1239 u8 tls_1_2_aes_gcm_256[0x1]; 1240 u8 tls_1_3_aes_gcm_256[0x1]; 1241 u8 reserved_at_4[0x1c]; 1242 1243 u8 reserved_at_20[0x7e0]; 1244 }; 1245 1246 struct mlx5_ifc_ipsec_cap_bits { 1247 u8 ipsec_full_offload[0x1]; 1248 u8 ipsec_crypto_offload[0x1]; 1249 u8 ipsec_esn[0x1]; 1250 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1251 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1252 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1253 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1254 u8 reserved_at_7[0x4]; 1255 u8 log_max_ipsec_offload[0x5]; 1256 u8 reserved_at_10[0x10]; 1257 1258 u8 min_log_ipsec_full_replay_window[0x8]; 1259 u8 max_log_ipsec_full_replay_window[0x8]; 1260 u8 reserved_at_30[0x7d0]; 1261 }; 1262 1263 enum { 1264 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1265 MLX5_WQ_TYPE_CYCLIC = 0x1, 1266 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1267 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1268 }; 1269 1270 enum { 1271 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1272 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1273 }; 1274 1275 enum { 1276 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1277 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1278 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1279 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1280 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1281 }; 1282 1283 enum { 1284 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1285 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1286 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1287 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1288 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1289 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1290 }; 1291 1292 enum { 1293 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1294 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1295 }; 1296 1297 enum { 1298 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1299 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1300 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1301 }; 1302 1303 enum { 1304 MLX5_CAP_PORT_TYPE_IB = 0x0, 1305 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1306 }; 1307 1308 enum { 1309 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1310 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1311 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1312 }; 1313 1314 enum { 1315 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1316 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1317 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1318 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1319 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1320 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1321 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1322 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1323 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1324 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1325 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1326 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1327 }; 1328 1329 enum { 1330 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1331 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1332 }; 1333 1334 #define MLX5_FC_BULK_SIZE_FACTOR 128 1335 1336 enum mlx5_fc_bulk_alloc_bitmask { 1337 MLX5_FC_BULK_128 = (1 << 0), 1338 MLX5_FC_BULK_256 = (1 << 1), 1339 MLX5_FC_BULK_512 = (1 << 2), 1340 MLX5_FC_BULK_1024 = (1 << 3), 1341 MLX5_FC_BULK_2048 = (1 << 4), 1342 MLX5_FC_BULK_4096 = (1 << 5), 1343 MLX5_FC_BULK_8192 = (1 << 6), 1344 MLX5_FC_BULK_16384 = (1 << 7), 1345 }; 1346 1347 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1348 1349 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1350 1351 enum { 1352 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1353 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1354 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1355 }; 1356 1357 struct mlx5_ifc_cmd_hca_cap_bits { 1358 u8 reserved_at_0[0x1f]; 1359 u8 vhca_resource_manager[0x1]; 1360 1361 u8 hca_cap_2[0x1]; 1362 u8 reserved_at_21[0x1]; 1363 u8 dtor[0x1]; 1364 u8 event_on_vhca_state_teardown_request[0x1]; 1365 u8 event_on_vhca_state_in_use[0x1]; 1366 u8 event_on_vhca_state_active[0x1]; 1367 u8 event_on_vhca_state_allocated[0x1]; 1368 u8 event_on_vhca_state_invalid[0x1]; 1369 u8 reserved_at_28[0x8]; 1370 u8 vhca_id[0x10]; 1371 1372 u8 reserved_at_40[0x40]; 1373 1374 u8 log_max_srq_sz[0x8]; 1375 u8 log_max_qp_sz[0x8]; 1376 u8 event_cap[0x1]; 1377 u8 reserved_at_91[0x2]; 1378 u8 isolate_vl_tc_new[0x1]; 1379 u8 reserved_at_94[0x4]; 1380 u8 prio_tag_required[0x1]; 1381 u8 reserved_at_99[0x2]; 1382 u8 log_max_qp[0x5]; 1383 1384 u8 reserved_at_a0[0x3]; 1385 u8 ece_support[0x1]; 1386 u8 reserved_at_a4[0x5]; 1387 u8 reg_c_preserve[0x1]; 1388 u8 reserved_at_aa[0x1]; 1389 u8 log_max_srq[0x5]; 1390 u8 reserved_at_b0[0x1]; 1391 u8 uplink_follow[0x1]; 1392 u8 ts_cqe_to_dest_cqn[0x1]; 1393 u8 reserved_at_b3[0x7]; 1394 u8 shampo[0x1]; 1395 u8 reserved_at_bb[0x5]; 1396 1397 u8 max_sgl_for_optimized_performance[0x8]; 1398 u8 log_max_cq_sz[0x8]; 1399 u8 relaxed_ordering_write_umr[0x1]; 1400 u8 relaxed_ordering_read_umr[0x1]; 1401 u8 reserved_at_d2[0x7]; 1402 u8 virtio_net_device_emualtion_manager[0x1]; 1403 u8 virtio_blk_device_emualtion_manager[0x1]; 1404 u8 log_max_cq[0x5]; 1405 1406 u8 log_max_eq_sz[0x8]; 1407 u8 relaxed_ordering_write[0x1]; 1408 u8 relaxed_ordering_read[0x1]; 1409 u8 log_max_mkey[0x6]; 1410 u8 reserved_at_f0[0x8]; 1411 u8 dump_fill_mkey[0x1]; 1412 u8 reserved_at_f9[0x2]; 1413 u8 fast_teardown[0x1]; 1414 u8 log_max_eq[0x4]; 1415 1416 u8 max_indirection[0x8]; 1417 u8 fixed_buffer_size[0x1]; 1418 u8 log_max_mrw_sz[0x7]; 1419 u8 force_teardown[0x1]; 1420 u8 reserved_at_111[0x1]; 1421 u8 log_max_bsf_list_size[0x6]; 1422 u8 umr_extended_translation_offset[0x1]; 1423 u8 null_mkey[0x1]; 1424 u8 log_max_klm_list_size[0x6]; 1425 1426 u8 reserved_at_120[0xa]; 1427 u8 log_max_ra_req_dc[0x6]; 1428 u8 reserved_at_130[0xa]; 1429 u8 log_max_ra_res_dc[0x6]; 1430 1431 u8 reserved_at_140[0x5]; 1432 u8 release_all_pages[0x1]; 1433 u8 must_not_use[0x1]; 1434 u8 reserved_at_147[0x2]; 1435 u8 roce_accl[0x1]; 1436 u8 log_max_ra_req_qp[0x6]; 1437 u8 reserved_at_150[0xa]; 1438 u8 log_max_ra_res_qp[0x6]; 1439 1440 u8 end_pad[0x1]; 1441 u8 cc_query_allowed[0x1]; 1442 u8 cc_modify_allowed[0x1]; 1443 u8 start_pad[0x1]; 1444 u8 cache_line_128byte[0x1]; 1445 u8 reserved_at_165[0x4]; 1446 u8 rts2rts_qp_counters_set_id[0x1]; 1447 u8 reserved_at_16a[0x2]; 1448 u8 vnic_env_int_rq_oob[0x1]; 1449 u8 sbcam_reg[0x1]; 1450 u8 reserved_at_16e[0x1]; 1451 u8 qcam_reg[0x1]; 1452 u8 gid_table_size[0x10]; 1453 1454 u8 out_of_seq_cnt[0x1]; 1455 u8 vport_counters[0x1]; 1456 u8 retransmission_q_counters[0x1]; 1457 u8 debug[0x1]; 1458 u8 modify_rq_counter_set_id[0x1]; 1459 u8 rq_delay_drop[0x1]; 1460 u8 max_qp_cnt[0xa]; 1461 u8 pkey_table_size[0x10]; 1462 1463 u8 vport_group_manager[0x1]; 1464 u8 vhca_group_manager[0x1]; 1465 u8 ib_virt[0x1]; 1466 u8 eth_virt[0x1]; 1467 u8 vnic_env_queue_counters[0x1]; 1468 u8 ets[0x1]; 1469 u8 nic_flow_table[0x1]; 1470 u8 eswitch_manager[0x1]; 1471 u8 device_memory[0x1]; 1472 u8 mcam_reg[0x1]; 1473 u8 pcam_reg[0x1]; 1474 u8 local_ca_ack_delay[0x5]; 1475 u8 port_module_event[0x1]; 1476 u8 enhanced_error_q_counters[0x1]; 1477 u8 ports_check[0x1]; 1478 u8 reserved_at_1b3[0x1]; 1479 u8 disable_link_up[0x1]; 1480 u8 beacon_led[0x1]; 1481 u8 port_type[0x2]; 1482 u8 num_ports[0x8]; 1483 1484 u8 reserved_at_1c0[0x1]; 1485 u8 pps[0x1]; 1486 u8 pps_modify[0x1]; 1487 u8 log_max_msg[0x5]; 1488 u8 reserved_at_1c8[0x4]; 1489 u8 max_tc[0x4]; 1490 u8 temp_warn_event[0x1]; 1491 u8 dcbx[0x1]; 1492 u8 general_notification_event[0x1]; 1493 u8 reserved_at_1d3[0x2]; 1494 u8 fpga[0x1]; 1495 u8 rol_s[0x1]; 1496 u8 rol_g[0x1]; 1497 u8 reserved_at_1d8[0x1]; 1498 u8 wol_s[0x1]; 1499 u8 wol_g[0x1]; 1500 u8 wol_a[0x1]; 1501 u8 wol_b[0x1]; 1502 u8 wol_m[0x1]; 1503 u8 wol_u[0x1]; 1504 u8 wol_p[0x1]; 1505 1506 u8 stat_rate_support[0x10]; 1507 u8 reserved_at_1f0[0x1]; 1508 u8 pci_sync_for_fw_update_event[0x1]; 1509 u8 reserved_at_1f2[0x6]; 1510 u8 init2_lag_tx_port_affinity[0x1]; 1511 u8 reserved_at_1fa[0x3]; 1512 u8 cqe_version[0x4]; 1513 1514 u8 compact_address_vector[0x1]; 1515 u8 striding_rq[0x1]; 1516 u8 reserved_at_202[0x1]; 1517 u8 ipoib_enhanced_offloads[0x1]; 1518 u8 ipoib_basic_offloads[0x1]; 1519 u8 reserved_at_205[0x1]; 1520 u8 repeated_block_disabled[0x1]; 1521 u8 umr_modify_entity_size_disabled[0x1]; 1522 u8 umr_modify_atomic_disabled[0x1]; 1523 u8 umr_indirect_mkey_disabled[0x1]; 1524 u8 umr_fence[0x2]; 1525 u8 dc_req_scat_data_cqe[0x1]; 1526 u8 reserved_at_20d[0x2]; 1527 u8 drain_sigerr[0x1]; 1528 u8 cmdif_checksum[0x2]; 1529 u8 sigerr_cqe[0x1]; 1530 u8 reserved_at_213[0x1]; 1531 u8 wq_signature[0x1]; 1532 u8 sctr_data_cqe[0x1]; 1533 u8 reserved_at_216[0x1]; 1534 u8 sho[0x1]; 1535 u8 tph[0x1]; 1536 u8 rf[0x1]; 1537 u8 dct[0x1]; 1538 u8 qos[0x1]; 1539 u8 eth_net_offloads[0x1]; 1540 u8 roce[0x1]; 1541 u8 atomic[0x1]; 1542 u8 reserved_at_21f[0x1]; 1543 1544 u8 cq_oi[0x1]; 1545 u8 cq_resize[0x1]; 1546 u8 cq_moderation[0x1]; 1547 u8 reserved_at_223[0x3]; 1548 u8 cq_eq_remap[0x1]; 1549 u8 pg[0x1]; 1550 u8 block_lb_mc[0x1]; 1551 u8 reserved_at_229[0x1]; 1552 u8 scqe_break_moderation[0x1]; 1553 u8 cq_period_start_from_cqe[0x1]; 1554 u8 cd[0x1]; 1555 u8 reserved_at_22d[0x1]; 1556 u8 apm[0x1]; 1557 u8 vector_calc[0x1]; 1558 u8 umr_ptr_rlky[0x1]; 1559 u8 imaicl[0x1]; 1560 u8 qp_packet_based[0x1]; 1561 u8 reserved_at_233[0x3]; 1562 u8 qkv[0x1]; 1563 u8 pkv[0x1]; 1564 u8 set_deth_sqpn[0x1]; 1565 u8 reserved_at_239[0x3]; 1566 u8 xrc[0x1]; 1567 u8 ud[0x1]; 1568 u8 uc[0x1]; 1569 u8 rc[0x1]; 1570 1571 u8 uar_4k[0x1]; 1572 u8 reserved_at_241[0x9]; 1573 u8 uar_sz[0x6]; 1574 u8 port_selection_cap[0x1]; 1575 u8 reserved_at_248[0x1]; 1576 u8 umem_uid_0[0x1]; 1577 u8 reserved_at_250[0x5]; 1578 u8 log_pg_sz[0x8]; 1579 1580 u8 bf[0x1]; 1581 u8 driver_version[0x1]; 1582 u8 pad_tx_eth_packet[0x1]; 1583 u8 reserved_at_263[0x3]; 1584 u8 mkey_by_name[0x1]; 1585 u8 reserved_at_267[0x4]; 1586 1587 u8 log_bf_reg_size[0x5]; 1588 1589 u8 reserved_at_270[0x6]; 1590 u8 lag_dct[0x2]; 1591 u8 lag_tx_port_affinity[0x1]; 1592 u8 lag_native_fdb_selection[0x1]; 1593 u8 reserved_at_27a[0x1]; 1594 u8 lag_master[0x1]; 1595 u8 num_lag_ports[0x4]; 1596 1597 u8 reserved_at_280[0x10]; 1598 u8 max_wqe_sz_sq[0x10]; 1599 1600 u8 reserved_at_2a0[0x10]; 1601 u8 max_wqe_sz_rq[0x10]; 1602 1603 u8 max_flow_counter_31_16[0x10]; 1604 u8 max_wqe_sz_sq_dc[0x10]; 1605 1606 u8 reserved_at_2e0[0x7]; 1607 u8 max_qp_mcg[0x19]; 1608 1609 u8 reserved_at_300[0x10]; 1610 u8 flow_counter_bulk_alloc[0x8]; 1611 u8 log_max_mcg[0x8]; 1612 1613 u8 reserved_at_320[0x3]; 1614 u8 log_max_transport_domain[0x5]; 1615 u8 reserved_at_328[0x3]; 1616 u8 log_max_pd[0x5]; 1617 u8 reserved_at_330[0xb]; 1618 u8 log_max_xrcd[0x5]; 1619 1620 u8 nic_receive_steering_discard[0x1]; 1621 u8 receive_discard_vport_down[0x1]; 1622 u8 transmit_discard_vport_down[0x1]; 1623 u8 reserved_at_343[0x5]; 1624 u8 log_max_flow_counter_bulk[0x8]; 1625 u8 max_flow_counter_15_0[0x10]; 1626 1627 1628 u8 reserved_at_360[0x3]; 1629 u8 log_max_rq[0x5]; 1630 u8 reserved_at_368[0x3]; 1631 u8 log_max_sq[0x5]; 1632 u8 reserved_at_370[0x3]; 1633 u8 log_max_tir[0x5]; 1634 u8 reserved_at_378[0x3]; 1635 u8 log_max_tis[0x5]; 1636 1637 u8 basic_cyclic_rcv_wqe[0x1]; 1638 u8 reserved_at_381[0x2]; 1639 u8 log_max_rmp[0x5]; 1640 u8 reserved_at_388[0x3]; 1641 u8 log_max_rqt[0x5]; 1642 u8 reserved_at_390[0x3]; 1643 u8 log_max_rqt_size[0x5]; 1644 u8 reserved_at_398[0x3]; 1645 u8 log_max_tis_per_sq[0x5]; 1646 1647 u8 ext_stride_num_range[0x1]; 1648 u8 roce_rw_supported[0x1]; 1649 u8 log_max_current_uc_list_wr_supported[0x1]; 1650 u8 log_max_stride_sz_rq[0x5]; 1651 u8 reserved_at_3a8[0x3]; 1652 u8 log_min_stride_sz_rq[0x5]; 1653 u8 reserved_at_3b0[0x3]; 1654 u8 log_max_stride_sz_sq[0x5]; 1655 u8 reserved_at_3b8[0x3]; 1656 u8 log_min_stride_sz_sq[0x5]; 1657 1658 u8 hairpin[0x1]; 1659 u8 reserved_at_3c1[0x2]; 1660 u8 log_max_hairpin_queues[0x5]; 1661 u8 reserved_at_3c8[0x3]; 1662 u8 log_max_hairpin_wq_data_sz[0x5]; 1663 u8 reserved_at_3d0[0x3]; 1664 u8 log_max_hairpin_num_packets[0x5]; 1665 u8 reserved_at_3d8[0x3]; 1666 u8 log_max_wq_sz[0x5]; 1667 1668 u8 nic_vport_change_event[0x1]; 1669 u8 disable_local_lb_uc[0x1]; 1670 u8 disable_local_lb_mc[0x1]; 1671 u8 log_min_hairpin_wq_data_sz[0x5]; 1672 u8 reserved_at_3e8[0x2]; 1673 u8 vhca_state[0x1]; 1674 u8 log_max_vlan_list[0x5]; 1675 u8 reserved_at_3f0[0x3]; 1676 u8 log_max_current_mc_list[0x5]; 1677 u8 reserved_at_3f8[0x3]; 1678 u8 log_max_current_uc_list[0x5]; 1679 1680 u8 general_obj_types[0x40]; 1681 1682 u8 sq_ts_format[0x2]; 1683 u8 rq_ts_format[0x2]; 1684 u8 steering_format_version[0x4]; 1685 u8 create_qp_start_hint[0x18]; 1686 1687 u8 reserved_at_460[0x3]; 1688 u8 log_max_uctx[0x5]; 1689 u8 reserved_at_468[0x2]; 1690 u8 ipsec_offload[0x1]; 1691 u8 log_max_umem[0x5]; 1692 u8 max_num_eqs[0x10]; 1693 1694 u8 reserved_at_480[0x1]; 1695 u8 tls_tx[0x1]; 1696 u8 tls_rx[0x1]; 1697 u8 log_max_l2_table[0x5]; 1698 u8 reserved_at_488[0x8]; 1699 u8 log_uar_page_sz[0x10]; 1700 1701 u8 reserved_at_4a0[0x20]; 1702 u8 device_frequency_mhz[0x20]; 1703 u8 device_frequency_khz[0x20]; 1704 1705 u8 reserved_at_500[0x20]; 1706 u8 num_of_uars_per_page[0x20]; 1707 1708 u8 flex_parser_protocols[0x20]; 1709 1710 u8 max_geneve_tlv_options[0x8]; 1711 u8 reserved_at_568[0x3]; 1712 u8 max_geneve_tlv_option_data_len[0x5]; 1713 u8 reserved_at_570[0x10]; 1714 1715 u8 reserved_at_580[0xb]; 1716 u8 log_max_dci_stream_channels[0x5]; 1717 u8 reserved_at_590[0x3]; 1718 u8 log_max_dci_errored_streams[0x5]; 1719 u8 reserved_at_598[0x8]; 1720 1721 u8 reserved_at_5a0[0x13]; 1722 u8 log_max_dek[0x5]; 1723 u8 reserved_at_5b8[0x4]; 1724 u8 mini_cqe_resp_stride_index[0x1]; 1725 u8 cqe_128_always[0x1]; 1726 u8 cqe_compression_128[0x1]; 1727 u8 cqe_compression[0x1]; 1728 1729 u8 cqe_compression_timeout[0x10]; 1730 u8 cqe_compression_max_num[0x10]; 1731 1732 u8 reserved_at_5e0[0x8]; 1733 u8 flex_parser_id_gtpu_dw_0[0x4]; 1734 u8 reserved_at_5ec[0x4]; 1735 u8 tag_matching[0x1]; 1736 u8 rndv_offload_rc[0x1]; 1737 u8 rndv_offload_dc[0x1]; 1738 u8 log_tag_matching_list_sz[0x5]; 1739 u8 reserved_at_5f8[0x3]; 1740 u8 log_max_xrq[0x5]; 1741 1742 u8 affiliate_nic_vport_criteria[0x8]; 1743 u8 native_port_num[0x8]; 1744 u8 num_vhca_ports[0x8]; 1745 u8 flex_parser_id_gtpu_teid[0x4]; 1746 u8 reserved_at_61c[0x2]; 1747 u8 sw_owner_id[0x1]; 1748 u8 reserved_at_61f[0x1]; 1749 1750 u8 max_num_of_monitor_counters[0x10]; 1751 u8 num_ppcnt_monitor_counters[0x10]; 1752 1753 u8 max_num_sf[0x10]; 1754 u8 num_q_monitor_counters[0x10]; 1755 1756 u8 reserved_at_660[0x20]; 1757 1758 u8 sf[0x1]; 1759 u8 sf_set_partition[0x1]; 1760 u8 reserved_at_682[0x1]; 1761 u8 log_max_sf[0x5]; 1762 u8 apu[0x1]; 1763 u8 reserved_at_689[0x4]; 1764 u8 migration[0x1]; 1765 u8 reserved_at_68e[0x2]; 1766 u8 log_min_sf_size[0x8]; 1767 u8 max_num_sf_partitions[0x8]; 1768 1769 u8 uctx_cap[0x20]; 1770 1771 u8 reserved_at_6c0[0x4]; 1772 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1773 u8 flex_parser_id_icmp_dw1[0x4]; 1774 u8 flex_parser_id_icmp_dw0[0x4]; 1775 u8 flex_parser_id_icmpv6_dw1[0x4]; 1776 u8 flex_parser_id_icmpv6_dw0[0x4]; 1777 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1778 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1779 1780 u8 max_num_match_definer[0x10]; 1781 u8 sf_base_id[0x10]; 1782 1783 u8 flex_parser_id_gtpu_dw_2[0x4]; 1784 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1785 u8 num_total_dynamic_vf_msix[0x18]; 1786 u8 reserved_at_720[0x14]; 1787 u8 dynamic_msix_table_size[0xc]; 1788 u8 reserved_at_740[0xc]; 1789 u8 min_dynamic_vf_msix_table_size[0x4]; 1790 u8 reserved_at_750[0x4]; 1791 u8 max_dynamic_vf_msix_table_size[0xc]; 1792 1793 u8 reserved_at_760[0x20]; 1794 u8 vhca_tunnel_commands[0x40]; 1795 u8 match_definer_format_supported[0x40]; 1796 }; 1797 1798 struct mlx5_ifc_cmd_hca_cap_2_bits { 1799 u8 reserved_at_0[0xa0]; 1800 1801 u8 max_reformat_insert_size[0x8]; 1802 u8 max_reformat_insert_offset[0x8]; 1803 u8 max_reformat_remove_size[0x8]; 1804 u8 max_reformat_remove_offset[0x8]; 1805 1806 u8 reserved_at_c0[0x740]; 1807 }; 1808 1809 enum mlx5_flow_destination_type { 1810 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1811 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1812 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1813 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1814 MLX5_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1815 1816 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1817 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1818 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1819 }; 1820 1821 enum mlx5_flow_table_miss_action { 1822 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1823 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1824 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1825 }; 1826 1827 struct mlx5_ifc_dest_format_struct_bits { 1828 u8 destination_type[0x8]; 1829 u8 destination_id[0x18]; 1830 1831 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1832 u8 packet_reformat[0x1]; 1833 u8 reserved_at_22[0xe]; 1834 u8 destination_eswitch_owner_vhca_id[0x10]; 1835 }; 1836 1837 struct mlx5_ifc_flow_counter_list_bits { 1838 u8 flow_counter_id[0x20]; 1839 1840 u8 reserved_at_20[0x20]; 1841 }; 1842 1843 struct mlx5_ifc_extended_dest_format_bits { 1844 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1845 1846 u8 packet_reformat_id[0x20]; 1847 1848 u8 reserved_at_60[0x20]; 1849 }; 1850 1851 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1852 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1853 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1854 }; 1855 1856 struct mlx5_ifc_fte_match_param_bits { 1857 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1858 1859 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1860 1861 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1862 1863 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1864 1865 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1866 1867 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1868 1869 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1870 1871 u8 reserved_at_e00[0x200]; 1872 }; 1873 1874 enum { 1875 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1876 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1877 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1878 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1879 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1880 }; 1881 1882 struct mlx5_ifc_rx_hash_field_select_bits { 1883 u8 l3_prot_type[0x1]; 1884 u8 l4_prot_type[0x1]; 1885 u8 selected_fields[0x1e]; 1886 }; 1887 1888 enum { 1889 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1890 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1891 }; 1892 1893 enum { 1894 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1895 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1896 }; 1897 1898 struct mlx5_ifc_wq_bits { 1899 u8 wq_type[0x4]; 1900 u8 wq_signature[0x1]; 1901 u8 end_padding_mode[0x2]; 1902 u8 cd_slave[0x1]; 1903 u8 reserved_at_8[0x18]; 1904 1905 u8 hds_skip_first_sge[0x1]; 1906 u8 log2_hds_buf_size[0x3]; 1907 u8 reserved_at_24[0x7]; 1908 u8 page_offset[0x5]; 1909 u8 lwm[0x10]; 1910 1911 u8 reserved_at_40[0x8]; 1912 u8 pd[0x18]; 1913 1914 u8 reserved_at_60[0x8]; 1915 u8 uar_page[0x18]; 1916 1917 u8 dbr_addr[0x40]; 1918 1919 u8 hw_counter[0x20]; 1920 1921 u8 sw_counter[0x20]; 1922 1923 u8 reserved_at_100[0xc]; 1924 u8 log_wq_stride[0x4]; 1925 u8 reserved_at_110[0x3]; 1926 u8 log_wq_pg_sz[0x5]; 1927 u8 reserved_at_118[0x3]; 1928 u8 log_wq_sz[0x5]; 1929 1930 u8 dbr_umem_valid[0x1]; 1931 u8 wq_umem_valid[0x1]; 1932 u8 reserved_at_122[0x1]; 1933 u8 log_hairpin_num_packets[0x5]; 1934 u8 reserved_at_128[0x3]; 1935 u8 log_hairpin_data_sz[0x5]; 1936 1937 u8 reserved_at_130[0x4]; 1938 u8 log_wqe_num_of_strides[0x4]; 1939 u8 two_byte_shift_en[0x1]; 1940 u8 reserved_at_139[0x4]; 1941 u8 log_wqe_stride_size[0x3]; 1942 1943 u8 reserved_at_140[0x80]; 1944 1945 u8 headers_mkey[0x20]; 1946 1947 u8 shampo_enable[0x1]; 1948 u8 reserved_at_1e1[0x4]; 1949 u8 log_reservation_size[0x3]; 1950 u8 reserved_at_1e8[0x5]; 1951 u8 log_max_num_of_packets_per_reservation[0x3]; 1952 u8 reserved_at_1f0[0x6]; 1953 u8 log_headers_entry_size[0x2]; 1954 u8 reserved_at_1f8[0x4]; 1955 u8 log_headers_buffer_entry_num[0x4]; 1956 1957 u8 reserved_at_200[0x400]; 1958 1959 struct mlx5_ifc_cmd_pas_bits pas[]; 1960 }; 1961 1962 struct mlx5_ifc_rq_num_bits { 1963 u8 reserved_at_0[0x8]; 1964 u8 rq_num[0x18]; 1965 }; 1966 1967 struct mlx5_ifc_mac_address_layout_bits { 1968 u8 reserved_at_0[0x10]; 1969 u8 mac_addr_47_32[0x10]; 1970 1971 u8 mac_addr_31_0[0x20]; 1972 }; 1973 1974 struct mlx5_ifc_vlan_layout_bits { 1975 u8 reserved_at_0[0x14]; 1976 u8 vlan[0x0c]; 1977 1978 u8 reserved_at_20[0x20]; 1979 }; 1980 1981 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1982 u8 reserved_at_0[0xa0]; 1983 1984 u8 min_time_between_cnps[0x20]; 1985 1986 u8 reserved_at_c0[0x12]; 1987 u8 cnp_dscp[0x6]; 1988 u8 reserved_at_d8[0x4]; 1989 u8 cnp_prio_mode[0x1]; 1990 u8 cnp_802p_prio[0x3]; 1991 1992 u8 reserved_at_e0[0x720]; 1993 }; 1994 1995 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1996 u8 reserved_at_0[0x60]; 1997 1998 u8 reserved_at_60[0x4]; 1999 u8 clamp_tgt_rate[0x1]; 2000 u8 reserved_at_65[0x3]; 2001 u8 clamp_tgt_rate_after_time_inc[0x1]; 2002 u8 reserved_at_69[0x17]; 2003 2004 u8 reserved_at_80[0x20]; 2005 2006 u8 rpg_time_reset[0x20]; 2007 2008 u8 rpg_byte_reset[0x20]; 2009 2010 u8 rpg_threshold[0x20]; 2011 2012 u8 rpg_max_rate[0x20]; 2013 2014 u8 rpg_ai_rate[0x20]; 2015 2016 u8 rpg_hai_rate[0x20]; 2017 2018 u8 rpg_gd[0x20]; 2019 2020 u8 rpg_min_dec_fac[0x20]; 2021 2022 u8 rpg_min_rate[0x20]; 2023 2024 u8 reserved_at_1c0[0xe0]; 2025 2026 u8 rate_to_set_on_first_cnp[0x20]; 2027 2028 u8 dce_tcp_g[0x20]; 2029 2030 u8 dce_tcp_rtt[0x20]; 2031 2032 u8 rate_reduce_monitor_period[0x20]; 2033 2034 u8 reserved_at_320[0x20]; 2035 2036 u8 initial_alpha_value[0x20]; 2037 2038 u8 reserved_at_360[0x4a0]; 2039 }; 2040 2041 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2042 u8 reserved_at_0[0x80]; 2043 2044 u8 rppp_max_rps[0x20]; 2045 2046 u8 rpg_time_reset[0x20]; 2047 2048 u8 rpg_byte_reset[0x20]; 2049 2050 u8 rpg_threshold[0x20]; 2051 2052 u8 rpg_max_rate[0x20]; 2053 2054 u8 rpg_ai_rate[0x20]; 2055 2056 u8 rpg_hai_rate[0x20]; 2057 2058 u8 rpg_gd[0x20]; 2059 2060 u8 rpg_min_dec_fac[0x20]; 2061 2062 u8 rpg_min_rate[0x20]; 2063 2064 u8 reserved_at_1c0[0x640]; 2065 }; 2066 2067 enum { 2068 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2069 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2070 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2071 }; 2072 2073 struct mlx5_ifc_resize_field_select_bits { 2074 u8 resize_field_select[0x20]; 2075 }; 2076 2077 struct mlx5_ifc_resource_dump_bits { 2078 u8 more_dump[0x1]; 2079 u8 inline_dump[0x1]; 2080 u8 reserved_at_2[0xa]; 2081 u8 seq_num[0x4]; 2082 u8 segment_type[0x10]; 2083 2084 u8 reserved_at_20[0x10]; 2085 u8 vhca_id[0x10]; 2086 2087 u8 index1[0x20]; 2088 2089 u8 index2[0x20]; 2090 2091 u8 num_of_obj1[0x10]; 2092 u8 num_of_obj2[0x10]; 2093 2094 u8 reserved_at_a0[0x20]; 2095 2096 u8 device_opaque[0x40]; 2097 2098 u8 mkey[0x20]; 2099 2100 u8 size[0x20]; 2101 2102 u8 address[0x40]; 2103 2104 u8 inline_data[52][0x20]; 2105 }; 2106 2107 struct mlx5_ifc_resource_dump_menu_record_bits { 2108 u8 reserved_at_0[0x4]; 2109 u8 num_of_obj2_supports_active[0x1]; 2110 u8 num_of_obj2_supports_all[0x1]; 2111 u8 must_have_num_of_obj2[0x1]; 2112 u8 support_num_of_obj2[0x1]; 2113 u8 num_of_obj1_supports_active[0x1]; 2114 u8 num_of_obj1_supports_all[0x1]; 2115 u8 must_have_num_of_obj1[0x1]; 2116 u8 support_num_of_obj1[0x1]; 2117 u8 must_have_index2[0x1]; 2118 u8 support_index2[0x1]; 2119 u8 must_have_index1[0x1]; 2120 u8 support_index1[0x1]; 2121 u8 segment_type[0x10]; 2122 2123 u8 segment_name[4][0x20]; 2124 2125 u8 index1_name[4][0x20]; 2126 2127 u8 index2_name[4][0x20]; 2128 }; 2129 2130 struct mlx5_ifc_resource_dump_segment_header_bits { 2131 u8 length_dw[0x10]; 2132 u8 segment_type[0x10]; 2133 }; 2134 2135 struct mlx5_ifc_resource_dump_command_segment_bits { 2136 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2137 2138 u8 segment_called[0x10]; 2139 u8 vhca_id[0x10]; 2140 2141 u8 index1[0x20]; 2142 2143 u8 index2[0x20]; 2144 2145 u8 num_of_obj1[0x10]; 2146 u8 num_of_obj2[0x10]; 2147 }; 2148 2149 struct mlx5_ifc_resource_dump_error_segment_bits { 2150 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2151 2152 u8 reserved_at_20[0x10]; 2153 u8 syndrome_id[0x10]; 2154 2155 u8 reserved_at_40[0x40]; 2156 2157 u8 error[8][0x20]; 2158 }; 2159 2160 struct mlx5_ifc_resource_dump_info_segment_bits { 2161 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2162 2163 u8 reserved_at_20[0x18]; 2164 u8 dump_version[0x8]; 2165 2166 u8 hw_version[0x20]; 2167 2168 u8 fw_version[0x20]; 2169 }; 2170 2171 struct mlx5_ifc_resource_dump_menu_segment_bits { 2172 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2173 2174 u8 reserved_at_20[0x10]; 2175 u8 num_of_records[0x10]; 2176 2177 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2178 }; 2179 2180 struct mlx5_ifc_resource_dump_resource_segment_bits { 2181 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2182 2183 u8 reserved_at_20[0x20]; 2184 2185 u8 index1[0x20]; 2186 2187 u8 index2[0x20]; 2188 2189 u8 payload[][0x20]; 2190 }; 2191 2192 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2193 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2194 }; 2195 2196 struct mlx5_ifc_menu_resource_dump_response_bits { 2197 struct mlx5_ifc_resource_dump_info_segment_bits info; 2198 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2199 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2200 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2201 }; 2202 2203 enum { 2204 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2205 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2206 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2207 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2208 }; 2209 2210 struct mlx5_ifc_modify_field_select_bits { 2211 u8 modify_field_select[0x20]; 2212 }; 2213 2214 struct mlx5_ifc_field_select_r_roce_np_bits { 2215 u8 field_select_r_roce_np[0x20]; 2216 }; 2217 2218 struct mlx5_ifc_field_select_r_roce_rp_bits { 2219 u8 field_select_r_roce_rp[0x20]; 2220 }; 2221 2222 enum { 2223 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2224 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2225 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2226 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2227 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2228 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2229 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2230 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2231 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2232 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2233 }; 2234 2235 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2236 u8 field_select_8021qaurp[0x20]; 2237 }; 2238 2239 struct mlx5_ifc_phys_layer_cntrs_bits { 2240 u8 time_since_last_clear_high[0x20]; 2241 2242 u8 time_since_last_clear_low[0x20]; 2243 2244 u8 symbol_errors_high[0x20]; 2245 2246 u8 symbol_errors_low[0x20]; 2247 2248 u8 sync_headers_errors_high[0x20]; 2249 2250 u8 sync_headers_errors_low[0x20]; 2251 2252 u8 edpl_bip_errors_lane0_high[0x20]; 2253 2254 u8 edpl_bip_errors_lane0_low[0x20]; 2255 2256 u8 edpl_bip_errors_lane1_high[0x20]; 2257 2258 u8 edpl_bip_errors_lane1_low[0x20]; 2259 2260 u8 edpl_bip_errors_lane2_high[0x20]; 2261 2262 u8 edpl_bip_errors_lane2_low[0x20]; 2263 2264 u8 edpl_bip_errors_lane3_high[0x20]; 2265 2266 u8 edpl_bip_errors_lane3_low[0x20]; 2267 2268 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2269 2270 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2271 2272 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2273 2274 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2275 2276 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2277 2278 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2279 2280 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2281 2282 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2283 2284 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2285 2286 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2287 2288 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2289 2290 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2291 2292 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2293 2294 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2295 2296 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2297 2298 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2299 2300 u8 rs_fec_corrected_blocks_high[0x20]; 2301 2302 u8 rs_fec_corrected_blocks_low[0x20]; 2303 2304 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2305 2306 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2307 2308 u8 rs_fec_no_errors_blocks_high[0x20]; 2309 2310 u8 rs_fec_no_errors_blocks_low[0x20]; 2311 2312 u8 rs_fec_single_error_blocks_high[0x20]; 2313 2314 u8 rs_fec_single_error_blocks_low[0x20]; 2315 2316 u8 rs_fec_corrected_symbols_total_high[0x20]; 2317 2318 u8 rs_fec_corrected_symbols_total_low[0x20]; 2319 2320 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2321 2322 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2323 2324 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2325 2326 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2327 2328 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2329 2330 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2331 2332 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2333 2334 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2335 2336 u8 link_down_events[0x20]; 2337 2338 u8 successful_recovery_events[0x20]; 2339 2340 u8 reserved_at_640[0x180]; 2341 }; 2342 2343 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2344 u8 time_since_last_clear_high[0x20]; 2345 2346 u8 time_since_last_clear_low[0x20]; 2347 2348 u8 phy_received_bits_high[0x20]; 2349 2350 u8 phy_received_bits_low[0x20]; 2351 2352 u8 phy_symbol_errors_high[0x20]; 2353 2354 u8 phy_symbol_errors_low[0x20]; 2355 2356 u8 phy_corrected_bits_high[0x20]; 2357 2358 u8 phy_corrected_bits_low[0x20]; 2359 2360 u8 phy_corrected_bits_lane0_high[0x20]; 2361 2362 u8 phy_corrected_bits_lane0_low[0x20]; 2363 2364 u8 phy_corrected_bits_lane1_high[0x20]; 2365 2366 u8 phy_corrected_bits_lane1_low[0x20]; 2367 2368 u8 phy_corrected_bits_lane2_high[0x20]; 2369 2370 u8 phy_corrected_bits_lane2_low[0x20]; 2371 2372 u8 phy_corrected_bits_lane3_high[0x20]; 2373 2374 u8 phy_corrected_bits_lane3_low[0x20]; 2375 2376 u8 reserved_at_200[0x5c0]; 2377 }; 2378 2379 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2380 u8 symbol_error_counter[0x10]; 2381 2382 u8 link_error_recovery_counter[0x8]; 2383 2384 u8 link_downed_counter[0x8]; 2385 2386 u8 port_rcv_errors[0x10]; 2387 2388 u8 port_rcv_remote_physical_errors[0x10]; 2389 2390 u8 port_rcv_switch_relay_errors[0x10]; 2391 2392 u8 port_xmit_discards[0x10]; 2393 2394 u8 port_xmit_constraint_errors[0x8]; 2395 2396 u8 port_rcv_constraint_errors[0x8]; 2397 2398 u8 reserved_at_70[0x8]; 2399 2400 u8 link_overrun_errors[0x8]; 2401 2402 u8 reserved_at_80[0x10]; 2403 2404 u8 vl_15_dropped[0x10]; 2405 2406 u8 reserved_at_a0[0x80]; 2407 2408 u8 port_xmit_wait[0x20]; 2409 }; 2410 2411 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2412 u8 transmit_queue_high[0x20]; 2413 2414 u8 transmit_queue_low[0x20]; 2415 2416 u8 no_buffer_discard_uc_high[0x20]; 2417 2418 u8 no_buffer_discard_uc_low[0x20]; 2419 2420 u8 reserved_at_80[0x740]; 2421 }; 2422 2423 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2424 u8 wred_discard_high[0x20]; 2425 2426 u8 wred_discard_low[0x20]; 2427 2428 u8 ecn_marked_tc_high[0x20]; 2429 2430 u8 ecn_marked_tc_low[0x20]; 2431 2432 u8 reserved_at_80[0x740]; 2433 }; 2434 2435 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2436 u8 rx_octets_high[0x20]; 2437 2438 u8 rx_octets_low[0x20]; 2439 2440 u8 reserved_at_40[0xc0]; 2441 2442 u8 rx_frames_high[0x20]; 2443 2444 u8 rx_frames_low[0x20]; 2445 2446 u8 tx_octets_high[0x20]; 2447 2448 u8 tx_octets_low[0x20]; 2449 2450 u8 reserved_at_180[0xc0]; 2451 2452 u8 tx_frames_high[0x20]; 2453 2454 u8 tx_frames_low[0x20]; 2455 2456 u8 rx_pause_high[0x20]; 2457 2458 u8 rx_pause_low[0x20]; 2459 2460 u8 rx_pause_duration_high[0x20]; 2461 2462 u8 rx_pause_duration_low[0x20]; 2463 2464 u8 tx_pause_high[0x20]; 2465 2466 u8 tx_pause_low[0x20]; 2467 2468 u8 tx_pause_duration_high[0x20]; 2469 2470 u8 tx_pause_duration_low[0x20]; 2471 2472 u8 rx_pause_transition_high[0x20]; 2473 2474 u8 rx_pause_transition_low[0x20]; 2475 2476 u8 rx_discards_high[0x20]; 2477 2478 u8 rx_discards_low[0x20]; 2479 2480 u8 device_stall_minor_watermark_cnt_high[0x20]; 2481 2482 u8 device_stall_minor_watermark_cnt_low[0x20]; 2483 2484 u8 device_stall_critical_watermark_cnt_high[0x20]; 2485 2486 u8 device_stall_critical_watermark_cnt_low[0x20]; 2487 2488 u8 reserved_at_480[0x340]; 2489 }; 2490 2491 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2492 u8 port_transmit_wait_high[0x20]; 2493 2494 u8 port_transmit_wait_low[0x20]; 2495 2496 u8 reserved_at_40[0x100]; 2497 2498 u8 rx_buffer_almost_full_high[0x20]; 2499 2500 u8 rx_buffer_almost_full_low[0x20]; 2501 2502 u8 rx_buffer_full_high[0x20]; 2503 2504 u8 rx_buffer_full_low[0x20]; 2505 2506 u8 rx_icrc_encapsulated_high[0x20]; 2507 2508 u8 rx_icrc_encapsulated_low[0x20]; 2509 2510 u8 reserved_at_200[0x5c0]; 2511 }; 2512 2513 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2514 u8 dot3stats_alignment_errors_high[0x20]; 2515 2516 u8 dot3stats_alignment_errors_low[0x20]; 2517 2518 u8 dot3stats_fcs_errors_high[0x20]; 2519 2520 u8 dot3stats_fcs_errors_low[0x20]; 2521 2522 u8 dot3stats_single_collision_frames_high[0x20]; 2523 2524 u8 dot3stats_single_collision_frames_low[0x20]; 2525 2526 u8 dot3stats_multiple_collision_frames_high[0x20]; 2527 2528 u8 dot3stats_multiple_collision_frames_low[0x20]; 2529 2530 u8 dot3stats_sqe_test_errors_high[0x20]; 2531 2532 u8 dot3stats_sqe_test_errors_low[0x20]; 2533 2534 u8 dot3stats_deferred_transmissions_high[0x20]; 2535 2536 u8 dot3stats_deferred_transmissions_low[0x20]; 2537 2538 u8 dot3stats_late_collisions_high[0x20]; 2539 2540 u8 dot3stats_late_collisions_low[0x20]; 2541 2542 u8 dot3stats_excessive_collisions_high[0x20]; 2543 2544 u8 dot3stats_excessive_collisions_low[0x20]; 2545 2546 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2547 2548 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2549 2550 u8 dot3stats_carrier_sense_errors_high[0x20]; 2551 2552 u8 dot3stats_carrier_sense_errors_low[0x20]; 2553 2554 u8 dot3stats_frame_too_longs_high[0x20]; 2555 2556 u8 dot3stats_frame_too_longs_low[0x20]; 2557 2558 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2559 2560 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2561 2562 u8 dot3stats_symbol_errors_high[0x20]; 2563 2564 u8 dot3stats_symbol_errors_low[0x20]; 2565 2566 u8 dot3control_in_unknown_opcodes_high[0x20]; 2567 2568 u8 dot3control_in_unknown_opcodes_low[0x20]; 2569 2570 u8 dot3in_pause_frames_high[0x20]; 2571 2572 u8 dot3in_pause_frames_low[0x20]; 2573 2574 u8 dot3out_pause_frames_high[0x20]; 2575 2576 u8 dot3out_pause_frames_low[0x20]; 2577 2578 u8 reserved_at_400[0x3c0]; 2579 }; 2580 2581 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2582 u8 ether_stats_drop_events_high[0x20]; 2583 2584 u8 ether_stats_drop_events_low[0x20]; 2585 2586 u8 ether_stats_octets_high[0x20]; 2587 2588 u8 ether_stats_octets_low[0x20]; 2589 2590 u8 ether_stats_pkts_high[0x20]; 2591 2592 u8 ether_stats_pkts_low[0x20]; 2593 2594 u8 ether_stats_broadcast_pkts_high[0x20]; 2595 2596 u8 ether_stats_broadcast_pkts_low[0x20]; 2597 2598 u8 ether_stats_multicast_pkts_high[0x20]; 2599 2600 u8 ether_stats_multicast_pkts_low[0x20]; 2601 2602 u8 ether_stats_crc_align_errors_high[0x20]; 2603 2604 u8 ether_stats_crc_align_errors_low[0x20]; 2605 2606 u8 ether_stats_undersize_pkts_high[0x20]; 2607 2608 u8 ether_stats_undersize_pkts_low[0x20]; 2609 2610 u8 ether_stats_oversize_pkts_high[0x20]; 2611 2612 u8 ether_stats_oversize_pkts_low[0x20]; 2613 2614 u8 ether_stats_fragments_high[0x20]; 2615 2616 u8 ether_stats_fragments_low[0x20]; 2617 2618 u8 ether_stats_jabbers_high[0x20]; 2619 2620 u8 ether_stats_jabbers_low[0x20]; 2621 2622 u8 ether_stats_collisions_high[0x20]; 2623 2624 u8 ether_stats_collisions_low[0x20]; 2625 2626 u8 ether_stats_pkts64octets_high[0x20]; 2627 2628 u8 ether_stats_pkts64octets_low[0x20]; 2629 2630 u8 ether_stats_pkts65to127octets_high[0x20]; 2631 2632 u8 ether_stats_pkts65to127octets_low[0x20]; 2633 2634 u8 ether_stats_pkts128to255octets_high[0x20]; 2635 2636 u8 ether_stats_pkts128to255octets_low[0x20]; 2637 2638 u8 ether_stats_pkts256to511octets_high[0x20]; 2639 2640 u8 ether_stats_pkts256to511octets_low[0x20]; 2641 2642 u8 ether_stats_pkts512to1023octets_high[0x20]; 2643 2644 u8 ether_stats_pkts512to1023octets_low[0x20]; 2645 2646 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2647 2648 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2649 2650 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2651 2652 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2653 2654 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2655 2656 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2657 2658 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2659 2660 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2661 2662 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2663 2664 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2665 2666 u8 reserved_at_540[0x280]; 2667 }; 2668 2669 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2670 u8 if_in_octets_high[0x20]; 2671 2672 u8 if_in_octets_low[0x20]; 2673 2674 u8 if_in_ucast_pkts_high[0x20]; 2675 2676 u8 if_in_ucast_pkts_low[0x20]; 2677 2678 u8 if_in_discards_high[0x20]; 2679 2680 u8 if_in_discards_low[0x20]; 2681 2682 u8 if_in_errors_high[0x20]; 2683 2684 u8 if_in_errors_low[0x20]; 2685 2686 u8 if_in_unknown_protos_high[0x20]; 2687 2688 u8 if_in_unknown_protos_low[0x20]; 2689 2690 u8 if_out_octets_high[0x20]; 2691 2692 u8 if_out_octets_low[0x20]; 2693 2694 u8 if_out_ucast_pkts_high[0x20]; 2695 2696 u8 if_out_ucast_pkts_low[0x20]; 2697 2698 u8 if_out_discards_high[0x20]; 2699 2700 u8 if_out_discards_low[0x20]; 2701 2702 u8 if_out_errors_high[0x20]; 2703 2704 u8 if_out_errors_low[0x20]; 2705 2706 u8 if_in_multicast_pkts_high[0x20]; 2707 2708 u8 if_in_multicast_pkts_low[0x20]; 2709 2710 u8 if_in_broadcast_pkts_high[0x20]; 2711 2712 u8 if_in_broadcast_pkts_low[0x20]; 2713 2714 u8 if_out_multicast_pkts_high[0x20]; 2715 2716 u8 if_out_multicast_pkts_low[0x20]; 2717 2718 u8 if_out_broadcast_pkts_high[0x20]; 2719 2720 u8 if_out_broadcast_pkts_low[0x20]; 2721 2722 u8 reserved_at_340[0x480]; 2723 }; 2724 2725 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2726 u8 a_frames_transmitted_ok_high[0x20]; 2727 2728 u8 a_frames_transmitted_ok_low[0x20]; 2729 2730 u8 a_frames_received_ok_high[0x20]; 2731 2732 u8 a_frames_received_ok_low[0x20]; 2733 2734 u8 a_frame_check_sequence_errors_high[0x20]; 2735 2736 u8 a_frame_check_sequence_errors_low[0x20]; 2737 2738 u8 a_alignment_errors_high[0x20]; 2739 2740 u8 a_alignment_errors_low[0x20]; 2741 2742 u8 a_octets_transmitted_ok_high[0x20]; 2743 2744 u8 a_octets_transmitted_ok_low[0x20]; 2745 2746 u8 a_octets_received_ok_high[0x20]; 2747 2748 u8 a_octets_received_ok_low[0x20]; 2749 2750 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2751 2752 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2753 2754 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2755 2756 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2757 2758 u8 a_multicast_frames_received_ok_high[0x20]; 2759 2760 u8 a_multicast_frames_received_ok_low[0x20]; 2761 2762 u8 a_broadcast_frames_received_ok_high[0x20]; 2763 2764 u8 a_broadcast_frames_received_ok_low[0x20]; 2765 2766 u8 a_in_range_length_errors_high[0x20]; 2767 2768 u8 a_in_range_length_errors_low[0x20]; 2769 2770 u8 a_out_of_range_length_field_high[0x20]; 2771 2772 u8 a_out_of_range_length_field_low[0x20]; 2773 2774 u8 a_frame_too_long_errors_high[0x20]; 2775 2776 u8 a_frame_too_long_errors_low[0x20]; 2777 2778 u8 a_symbol_error_during_carrier_high[0x20]; 2779 2780 u8 a_symbol_error_during_carrier_low[0x20]; 2781 2782 u8 a_mac_control_frames_transmitted_high[0x20]; 2783 2784 u8 a_mac_control_frames_transmitted_low[0x20]; 2785 2786 u8 a_mac_control_frames_received_high[0x20]; 2787 2788 u8 a_mac_control_frames_received_low[0x20]; 2789 2790 u8 a_unsupported_opcodes_received_high[0x20]; 2791 2792 u8 a_unsupported_opcodes_received_low[0x20]; 2793 2794 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2795 2796 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2797 2798 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2799 2800 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2801 2802 u8 reserved_at_4c0[0x300]; 2803 }; 2804 2805 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2806 u8 life_time_counter_high[0x20]; 2807 2808 u8 life_time_counter_low[0x20]; 2809 2810 u8 rx_errors[0x20]; 2811 2812 u8 tx_errors[0x20]; 2813 2814 u8 l0_to_recovery_eieos[0x20]; 2815 2816 u8 l0_to_recovery_ts[0x20]; 2817 2818 u8 l0_to_recovery_framing[0x20]; 2819 2820 u8 l0_to_recovery_retrain[0x20]; 2821 2822 u8 crc_error_dllp[0x20]; 2823 2824 u8 crc_error_tlp[0x20]; 2825 2826 u8 tx_overflow_buffer_pkt_high[0x20]; 2827 2828 u8 tx_overflow_buffer_pkt_low[0x20]; 2829 2830 u8 outbound_stalled_reads[0x20]; 2831 2832 u8 outbound_stalled_writes[0x20]; 2833 2834 u8 outbound_stalled_reads_events[0x20]; 2835 2836 u8 outbound_stalled_writes_events[0x20]; 2837 2838 u8 reserved_at_200[0x5c0]; 2839 }; 2840 2841 struct mlx5_ifc_cmd_inter_comp_event_bits { 2842 u8 command_completion_vector[0x20]; 2843 2844 u8 reserved_at_20[0xc0]; 2845 }; 2846 2847 struct mlx5_ifc_stall_vl_event_bits { 2848 u8 reserved_at_0[0x18]; 2849 u8 port_num[0x1]; 2850 u8 reserved_at_19[0x3]; 2851 u8 vl[0x4]; 2852 2853 u8 reserved_at_20[0xa0]; 2854 }; 2855 2856 struct mlx5_ifc_db_bf_congestion_event_bits { 2857 u8 event_subtype[0x8]; 2858 u8 reserved_at_8[0x8]; 2859 u8 congestion_level[0x8]; 2860 u8 reserved_at_18[0x8]; 2861 2862 u8 reserved_at_20[0xa0]; 2863 }; 2864 2865 struct mlx5_ifc_gpio_event_bits { 2866 u8 reserved_at_0[0x60]; 2867 2868 u8 gpio_event_hi[0x20]; 2869 2870 u8 gpio_event_lo[0x20]; 2871 2872 u8 reserved_at_a0[0x40]; 2873 }; 2874 2875 struct mlx5_ifc_port_state_change_event_bits { 2876 u8 reserved_at_0[0x40]; 2877 2878 u8 port_num[0x4]; 2879 u8 reserved_at_44[0x1c]; 2880 2881 u8 reserved_at_60[0x80]; 2882 }; 2883 2884 struct mlx5_ifc_dropped_packet_logged_bits { 2885 u8 reserved_at_0[0xe0]; 2886 }; 2887 2888 struct mlx5_ifc_default_timeout_bits { 2889 u8 to_multiplier[0x3]; 2890 u8 reserved_at_3[0x9]; 2891 u8 to_value[0x14]; 2892 }; 2893 2894 struct mlx5_ifc_dtor_reg_bits { 2895 u8 reserved_at_0[0x20]; 2896 2897 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2898 2899 u8 reserved_at_40[0x60]; 2900 2901 struct mlx5_ifc_default_timeout_bits health_poll_to; 2902 2903 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2904 2905 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2906 2907 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2908 2909 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2910 2911 struct mlx5_ifc_default_timeout_bits tear_down_to; 2912 2913 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2914 2915 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2916 2917 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2918 2919 u8 reserved_at_1c0[0x40]; 2920 }; 2921 2922 enum { 2923 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2924 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2925 }; 2926 2927 struct mlx5_ifc_cq_error_bits { 2928 u8 reserved_at_0[0x8]; 2929 u8 cqn[0x18]; 2930 2931 u8 reserved_at_20[0x20]; 2932 2933 u8 reserved_at_40[0x18]; 2934 u8 syndrome[0x8]; 2935 2936 u8 reserved_at_60[0x80]; 2937 }; 2938 2939 struct mlx5_ifc_rdma_page_fault_event_bits { 2940 u8 bytes_committed[0x20]; 2941 2942 u8 r_key[0x20]; 2943 2944 u8 reserved_at_40[0x10]; 2945 u8 packet_len[0x10]; 2946 2947 u8 rdma_op_len[0x20]; 2948 2949 u8 rdma_va[0x40]; 2950 2951 u8 reserved_at_c0[0x5]; 2952 u8 rdma[0x1]; 2953 u8 write[0x1]; 2954 u8 requestor[0x1]; 2955 u8 qp_number[0x18]; 2956 }; 2957 2958 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2959 u8 bytes_committed[0x20]; 2960 2961 u8 reserved_at_20[0x10]; 2962 u8 wqe_index[0x10]; 2963 2964 u8 reserved_at_40[0x10]; 2965 u8 len[0x10]; 2966 2967 u8 reserved_at_60[0x60]; 2968 2969 u8 reserved_at_c0[0x5]; 2970 u8 rdma[0x1]; 2971 u8 write_read[0x1]; 2972 u8 requestor[0x1]; 2973 u8 qpn[0x18]; 2974 }; 2975 2976 struct mlx5_ifc_qp_events_bits { 2977 u8 reserved_at_0[0xa0]; 2978 2979 u8 type[0x8]; 2980 u8 reserved_at_a8[0x18]; 2981 2982 u8 reserved_at_c0[0x8]; 2983 u8 qpn_rqn_sqn[0x18]; 2984 }; 2985 2986 struct mlx5_ifc_dct_events_bits { 2987 u8 reserved_at_0[0xc0]; 2988 2989 u8 reserved_at_c0[0x8]; 2990 u8 dct_number[0x18]; 2991 }; 2992 2993 struct mlx5_ifc_comp_event_bits { 2994 u8 reserved_at_0[0xc0]; 2995 2996 u8 reserved_at_c0[0x8]; 2997 u8 cq_number[0x18]; 2998 }; 2999 3000 enum { 3001 MLX5_QPC_STATE_RST = 0x0, 3002 MLX5_QPC_STATE_INIT = 0x1, 3003 MLX5_QPC_STATE_RTR = 0x2, 3004 MLX5_QPC_STATE_RTS = 0x3, 3005 MLX5_QPC_STATE_SQER = 0x4, 3006 MLX5_QPC_STATE_ERR = 0x6, 3007 MLX5_QPC_STATE_SQD = 0x7, 3008 MLX5_QPC_STATE_SUSPENDED = 0x9, 3009 }; 3010 3011 enum { 3012 MLX5_QPC_ST_RC = 0x0, 3013 MLX5_QPC_ST_UC = 0x1, 3014 MLX5_QPC_ST_UD = 0x2, 3015 MLX5_QPC_ST_XRC = 0x3, 3016 MLX5_QPC_ST_DCI = 0x5, 3017 MLX5_QPC_ST_QP0 = 0x7, 3018 MLX5_QPC_ST_QP1 = 0x8, 3019 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3020 MLX5_QPC_ST_REG_UMR = 0xc, 3021 }; 3022 3023 enum { 3024 MLX5_QPC_PM_STATE_ARMED = 0x0, 3025 MLX5_QPC_PM_STATE_REARM = 0x1, 3026 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3027 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3028 }; 3029 3030 enum { 3031 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3032 }; 3033 3034 enum { 3035 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3036 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3037 }; 3038 3039 enum { 3040 MLX5_QPC_MTU_256_BYTES = 0x1, 3041 MLX5_QPC_MTU_512_BYTES = 0x2, 3042 MLX5_QPC_MTU_1K_BYTES = 0x3, 3043 MLX5_QPC_MTU_2K_BYTES = 0x4, 3044 MLX5_QPC_MTU_4K_BYTES = 0x5, 3045 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3046 }; 3047 3048 enum { 3049 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3050 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3051 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3052 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3053 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3054 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3055 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3056 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3057 }; 3058 3059 enum { 3060 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3061 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3062 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3063 }; 3064 3065 enum { 3066 MLX5_QPC_CS_RES_DISABLE = 0x0, 3067 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3068 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3069 }; 3070 3071 enum { 3072 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3073 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3074 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3075 }; 3076 3077 struct mlx5_ifc_qpc_bits { 3078 u8 state[0x4]; 3079 u8 lag_tx_port_affinity[0x4]; 3080 u8 st[0x8]; 3081 u8 reserved_at_10[0x2]; 3082 u8 isolate_vl_tc[0x1]; 3083 u8 pm_state[0x2]; 3084 u8 reserved_at_15[0x1]; 3085 u8 req_e2e_credit_mode[0x2]; 3086 u8 offload_type[0x4]; 3087 u8 end_padding_mode[0x2]; 3088 u8 reserved_at_1e[0x2]; 3089 3090 u8 wq_signature[0x1]; 3091 u8 block_lb_mc[0x1]; 3092 u8 atomic_like_write_en[0x1]; 3093 u8 latency_sensitive[0x1]; 3094 u8 reserved_at_24[0x1]; 3095 u8 drain_sigerr[0x1]; 3096 u8 reserved_at_26[0x2]; 3097 u8 pd[0x18]; 3098 3099 u8 mtu[0x3]; 3100 u8 log_msg_max[0x5]; 3101 u8 reserved_at_48[0x1]; 3102 u8 log_rq_size[0x4]; 3103 u8 log_rq_stride[0x3]; 3104 u8 no_sq[0x1]; 3105 u8 log_sq_size[0x4]; 3106 u8 reserved_at_55[0x3]; 3107 u8 ts_format[0x2]; 3108 u8 reserved_at_5a[0x1]; 3109 u8 rlky[0x1]; 3110 u8 ulp_stateless_offload_mode[0x4]; 3111 3112 u8 counter_set_id[0x8]; 3113 u8 uar_page[0x18]; 3114 3115 u8 reserved_at_80[0x8]; 3116 u8 user_index[0x18]; 3117 3118 u8 reserved_at_a0[0x3]; 3119 u8 log_page_size[0x5]; 3120 u8 remote_qpn[0x18]; 3121 3122 struct mlx5_ifc_ads_bits primary_address_path; 3123 3124 struct mlx5_ifc_ads_bits secondary_address_path; 3125 3126 u8 log_ack_req_freq[0x4]; 3127 u8 reserved_at_384[0x4]; 3128 u8 log_sra_max[0x3]; 3129 u8 reserved_at_38b[0x2]; 3130 u8 retry_count[0x3]; 3131 u8 rnr_retry[0x3]; 3132 u8 reserved_at_393[0x1]; 3133 u8 fre[0x1]; 3134 u8 cur_rnr_retry[0x3]; 3135 u8 cur_retry_count[0x3]; 3136 u8 reserved_at_39b[0x5]; 3137 3138 u8 reserved_at_3a0[0x20]; 3139 3140 u8 reserved_at_3c0[0x8]; 3141 u8 next_send_psn[0x18]; 3142 3143 u8 reserved_at_3e0[0x3]; 3144 u8 log_num_dci_stream_channels[0x5]; 3145 u8 cqn_snd[0x18]; 3146 3147 u8 reserved_at_400[0x3]; 3148 u8 log_num_dci_errored_streams[0x5]; 3149 u8 deth_sqpn[0x18]; 3150 3151 u8 reserved_at_420[0x20]; 3152 3153 u8 reserved_at_440[0x8]; 3154 u8 last_acked_psn[0x18]; 3155 3156 u8 reserved_at_460[0x8]; 3157 u8 ssn[0x18]; 3158 3159 u8 reserved_at_480[0x8]; 3160 u8 log_rra_max[0x3]; 3161 u8 reserved_at_48b[0x1]; 3162 u8 atomic_mode[0x4]; 3163 u8 rre[0x1]; 3164 u8 rwe[0x1]; 3165 u8 rae[0x1]; 3166 u8 reserved_at_493[0x1]; 3167 u8 page_offset[0x6]; 3168 u8 reserved_at_49a[0x3]; 3169 u8 cd_slave_receive[0x1]; 3170 u8 cd_slave_send[0x1]; 3171 u8 cd_master[0x1]; 3172 3173 u8 reserved_at_4a0[0x3]; 3174 u8 min_rnr_nak[0x5]; 3175 u8 next_rcv_psn[0x18]; 3176 3177 u8 reserved_at_4c0[0x8]; 3178 u8 xrcd[0x18]; 3179 3180 u8 reserved_at_4e0[0x8]; 3181 u8 cqn_rcv[0x18]; 3182 3183 u8 dbr_addr[0x40]; 3184 3185 u8 q_key[0x20]; 3186 3187 u8 reserved_at_560[0x5]; 3188 u8 rq_type[0x3]; 3189 u8 srqn_rmpn_xrqn[0x18]; 3190 3191 u8 reserved_at_580[0x8]; 3192 u8 rmsn[0x18]; 3193 3194 u8 hw_sq_wqebb_counter[0x10]; 3195 u8 sw_sq_wqebb_counter[0x10]; 3196 3197 u8 hw_rq_counter[0x20]; 3198 3199 u8 sw_rq_counter[0x20]; 3200 3201 u8 reserved_at_600[0x20]; 3202 3203 u8 reserved_at_620[0xf]; 3204 u8 cgs[0x1]; 3205 u8 cs_req[0x8]; 3206 u8 cs_res[0x8]; 3207 3208 u8 dc_access_key[0x40]; 3209 3210 u8 reserved_at_680[0x3]; 3211 u8 dbr_umem_valid[0x1]; 3212 3213 u8 reserved_at_684[0xbc]; 3214 }; 3215 3216 struct mlx5_ifc_roce_addr_layout_bits { 3217 u8 source_l3_address[16][0x8]; 3218 3219 u8 reserved_at_80[0x3]; 3220 u8 vlan_valid[0x1]; 3221 u8 vlan_id[0xc]; 3222 u8 source_mac_47_32[0x10]; 3223 3224 u8 source_mac_31_0[0x20]; 3225 3226 u8 reserved_at_c0[0x14]; 3227 u8 roce_l3_type[0x4]; 3228 u8 roce_version[0x8]; 3229 3230 u8 reserved_at_e0[0x20]; 3231 }; 3232 3233 struct mlx5_ifc_shampo_cap_bits { 3234 u8 reserved_at_0[0x3]; 3235 u8 shampo_log_max_reservation_size[0x5]; 3236 u8 reserved_at_8[0x3]; 3237 u8 shampo_log_min_reservation_size[0x5]; 3238 u8 shampo_min_mss_size[0x10]; 3239 3240 u8 reserved_at_20[0x3]; 3241 u8 shampo_max_log_headers_entry_size[0x5]; 3242 u8 reserved_at_28[0x18]; 3243 3244 u8 reserved_at_40[0x7c0]; 3245 }; 3246 3247 union mlx5_ifc_hca_cap_union_bits { 3248 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3249 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3250 struct mlx5_ifc_odp_cap_bits odp_cap; 3251 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3252 struct mlx5_ifc_roce_cap_bits roce_cap; 3253 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3254 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3255 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3256 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3257 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3258 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3259 struct mlx5_ifc_qos_cap_bits qos_cap; 3260 struct mlx5_ifc_debug_cap_bits debug_cap; 3261 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3262 struct mlx5_ifc_tls_cap_bits tls_cap; 3263 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3264 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3265 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3266 u8 reserved_at_0[0x8000]; 3267 }; 3268 3269 enum { 3270 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3271 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3272 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3273 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3274 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3275 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3276 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3277 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3278 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3279 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3280 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3281 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3282 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3283 }; 3284 3285 enum { 3286 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3287 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3288 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3289 }; 3290 3291 struct mlx5_ifc_vlan_bits { 3292 u8 ethtype[0x10]; 3293 u8 prio[0x3]; 3294 u8 cfi[0x1]; 3295 u8 vid[0xc]; 3296 }; 3297 3298 struct mlx5_ifc_flow_context_bits { 3299 struct mlx5_ifc_vlan_bits push_vlan; 3300 3301 u8 group_id[0x20]; 3302 3303 u8 reserved_at_40[0x8]; 3304 u8 flow_tag[0x18]; 3305 3306 u8 reserved_at_60[0x10]; 3307 u8 action[0x10]; 3308 3309 u8 extended_destination[0x1]; 3310 u8 reserved_at_81[0x1]; 3311 u8 flow_source[0x2]; 3312 u8 reserved_at_84[0x4]; 3313 u8 destination_list_size[0x18]; 3314 3315 u8 reserved_at_a0[0x8]; 3316 u8 flow_counter_list_size[0x18]; 3317 3318 u8 packet_reformat_id[0x20]; 3319 3320 u8 modify_header_id[0x20]; 3321 3322 struct mlx5_ifc_vlan_bits push_vlan_2; 3323 3324 u8 ipsec_obj_id[0x20]; 3325 u8 reserved_at_140[0xc0]; 3326 3327 struct mlx5_ifc_fte_match_param_bits match_value; 3328 3329 u8 reserved_at_1200[0x600]; 3330 3331 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3332 }; 3333 3334 enum { 3335 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3336 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3337 }; 3338 3339 struct mlx5_ifc_xrc_srqc_bits { 3340 u8 state[0x4]; 3341 u8 log_xrc_srq_size[0x4]; 3342 u8 reserved_at_8[0x18]; 3343 3344 u8 wq_signature[0x1]; 3345 u8 cont_srq[0x1]; 3346 u8 reserved_at_22[0x1]; 3347 u8 rlky[0x1]; 3348 u8 basic_cyclic_rcv_wqe[0x1]; 3349 u8 log_rq_stride[0x3]; 3350 u8 xrcd[0x18]; 3351 3352 u8 page_offset[0x6]; 3353 u8 reserved_at_46[0x1]; 3354 u8 dbr_umem_valid[0x1]; 3355 u8 cqn[0x18]; 3356 3357 u8 reserved_at_60[0x20]; 3358 3359 u8 user_index_equal_xrc_srqn[0x1]; 3360 u8 reserved_at_81[0x1]; 3361 u8 log_page_size[0x6]; 3362 u8 user_index[0x18]; 3363 3364 u8 reserved_at_a0[0x20]; 3365 3366 u8 reserved_at_c0[0x8]; 3367 u8 pd[0x18]; 3368 3369 u8 lwm[0x10]; 3370 u8 wqe_cnt[0x10]; 3371 3372 u8 reserved_at_100[0x40]; 3373 3374 u8 db_record_addr_h[0x20]; 3375 3376 u8 db_record_addr_l[0x1e]; 3377 u8 reserved_at_17e[0x2]; 3378 3379 u8 reserved_at_180[0x80]; 3380 }; 3381 3382 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3383 u8 counter_error_queues[0x20]; 3384 3385 u8 total_error_queues[0x20]; 3386 3387 u8 send_queue_priority_update_flow[0x20]; 3388 3389 u8 reserved_at_60[0x20]; 3390 3391 u8 nic_receive_steering_discard[0x40]; 3392 3393 u8 receive_discard_vport_down[0x40]; 3394 3395 u8 transmit_discard_vport_down[0x40]; 3396 3397 u8 reserved_at_140[0xa0]; 3398 3399 u8 internal_rq_out_of_buffer[0x20]; 3400 3401 u8 reserved_at_200[0xe00]; 3402 }; 3403 3404 struct mlx5_ifc_traffic_counter_bits { 3405 u8 packets[0x40]; 3406 3407 u8 octets[0x40]; 3408 }; 3409 3410 struct mlx5_ifc_tisc_bits { 3411 u8 strict_lag_tx_port_affinity[0x1]; 3412 u8 tls_en[0x1]; 3413 u8 reserved_at_2[0x2]; 3414 u8 lag_tx_port_affinity[0x04]; 3415 3416 u8 reserved_at_8[0x4]; 3417 u8 prio[0x4]; 3418 u8 reserved_at_10[0x10]; 3419 3420 u8 reserved_at_20[0x100]; 3421 3422 u8 reserved_at_120[0x8]; 3423 u8 transport_domain[0x18]; 3424 3425 u8 reserved_at_140[0x8]; 3426 u8 underlay_qpn[0x18]; 3427 3428 u8 reserved_at_160[0x8]; 3429 u8 pd[0x18]; 3430 3431 u8 reserved_at_180[0x380]; 3432 }; 3433 3434 enum { 3435 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3436 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3437 }; 3438 3439 enum { 3440 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3441 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3442 }; 3443 3444 enum { 3445 MLX5_RX_HASH_FN_NONE = 0x0, 3446 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3447 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3448 }; 3449 3450 enum { 3451 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3452 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3453 }; 3454 3455 struct mlx5_ifc_tirc_bits { 3456 u8 reserved_at_0[0x20]; 3457 3458 u8 disp_type[0x4]; 3459 u8 tls_en[0x1]; 3460 u8 reserved_at_25[0x1b]; 3461 3462 u8 reserved_at_40[0x40]; 3463 3464 u8 reserved_at_80[0x4]; 3465 u8 lro_timeout_period_usecs[0x10]; 3466 u8 packet_merge_mask[0x4]; 3467 u8 lro_max_ip_payload_size[0x8]; 3468 3469 u8 reserved_at_a0[0x40]; 3470 3471 u8 reserved_at_e0[0x8]; 3472 u8 inline_rqn[0x18]; 3473 3474 u8 rx_hash_symmetric[0x1]; 3475 u8 reserved_at_101[0x1]; 3476 u8 tunneled_offload_en[0x1]; 3477 u8 reserved_at_103[0x5]; 3478 u8 indirect_table[0x18]; 3479 3480 u8 rx_hash_fn[0x4]; 3481 u8 reserved_at_124[0x2]; 3482 u8 self_lb_block[0x2]; 3483 u8 transport_domain[0x18]; 3484 3485 u8 rx_hash_toeplitz_key[10][0x20]; 3486 3487 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3488 3489 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3490 3491 u8 reserved_at_2c0[0x4c0]; 3492 }; 3493 3494 enum { 3495 MLX5_SRQC_STATE_GOOD = 0x0, 3496 MLX5_SRQC_STATE_ERROR = 0x1, 3497 }; 3498 3499 struct mlx5_ifc_srqc_bits { 3500 u8 state[0x4]; 3501 u8 log_srq_size[0x4]; 3502 u8 reserved_at_8[0x18]; 3503 3504 u8 wq_signature[0x1]; 3505 u8 cont_srq[0x1]; 3506 u8 reserved_at_22[0x1]; 3507 u8 rlky[0x1]; 3508 u8 reserved_at_24[0x1]; 3509 u8 log_rq_stride[0x3]; 3510 u8 xrcd[0x18]; 3511 3512 u8 page_offset[0x6]; 3513 u8 reserved_at_46[0x2]; 3514 u8 cqn[0x18]; 3515 3516 u8 reserved_at_60[0x20]; 3517 3518 u8 reserved_at_80[0x2]; 3519 u8 log_page_size[0x6]; 3520 u8 reserved_at_88[0x18]; 3521 3522 u8 reserved_at_a0[0x20]; 3523 3524 u8 reserved_at_c0[0x8]; 3525 u8 pd[0x18]; 3526 3527 u8 lwm[0x10]; 3528 u8 wqe_cnt[0x10]; 3529 3530 u8 reserved_at_100[0x40]; 3531 3532 u8 dbr_addr[0x40]; 3533 3534 u8 reserved_at_180[0x80]; 3535 }; 3536 3537 enum { 3538 MLX5_SQC_STATE_RST = 0x0, 3539 MLX5_SQC_STATE_RDY = 0x1, 3540 MLX5_SQC_STATE_ERR = 0x3, 3541 }; 3542 3543 struct mlx5_ifc_sqc_bits { 3544 u8 rlky[0x1]; 3545 u8 cd_master[0x1]; 3546 u8 fre[0x1]; 3547 u8 flush_in_error_en[0x1]; 3548 u8 allow_multi_pkt_send_wqe[0x1]; 3549 u8 min_wqe_inline_mode[0x3]; 3550 u8 state[0x4]; 3551 u8 reg_umr[0x1]; 3552 u8 allow_swp[0x1]; 3553 u8 hairpin[0x1]; 3554 u8 reserved_at_f[0xb]; 3555 u8 ts_format[0x2]; 3556 u8 reserved_at_1c[0x4]; 3557 3558 u8 reserved_at_20[0x8]; 3559 u8 user_index[0x18]; 3560 3561 u8 reserved_at_40[0x8]; 3562 u8 cqn[0x18]; 3563 3564 u8 reserved_at_60[0x8]; 3565 u8 hairpin_peer_rq[0x18]; 3566 3567 u8 reserved_at_80[0x10]; 3568 u8 hairpin_peer_vhca[0x10]; 3569 3570 u8 reserved_at_a0[0x20]; 3571 3572 u8 reserved_at_c0[0x8]; 3573 u8 ts_cqe_to_dest_cqn[0x18]; 3574 3575 u8 reserved_at_e0[0x10]; 3576 u8 packet_pacing_rate_limit_index[0x10]; 3577 u8 tis_lst_sz[0x10]; 3578 u8 qos_queue_group_id[0x10]; 3579 3580 u8 reserved_at_120[0x40]; 3581 3582 u8 reserved_at_160[0x8]; 3583 u8 tis_num_0[0x18]; 3584 3585 struct mlx5_ifc_wq_bits wq; 3586 }; 3587 3588 enum { 3589 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3590 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3591 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3592 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3593 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3594 }; 3595 3596 enum { 3597 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3598 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3599 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3600 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3601 }; 3602 3603 struct mlx5_ifc_scheduling_context_bits { 3604 u8 element_type[0x8]; 3605 u8 reserved_at_8[0x18]; 3606 3607 u8 element_attributes[0x20]; 3608 3609 u8 parent_element_id[0x20]; 3610 3611 u8 reserved_at_60[0x40]; 3612 3613 u8 bw_share[0x20]; 3614 3615 u8 max_average_bw[0x20]; 3616 3617 u8 reserved_at_e0[0x120]; 3618 }; 3619 3620 struct mlx5_ifc_rqtc_bits { 3621 u8 reserved_at_0[0xa0]; 3622 3623 u8 reserved_at_a0[0x5]; 3624 u8 list_q_type[0x3]; 3625 u8 reserved_at_a8[0x8]; 3626 u8 rqt_max_size[0x10]; 3627 3628 u8 rq_vhca_id_format[0x1]; 3629 u8 reserved_at_c1[0xf]; 3630 u8 rqt_actual_size[0x10]; 3631 3632 u8 reserved_at_e0[0x6a0]; 3633 3634 struct mlx5_ifc_rq_num_bits rq_num[]; 3635 }; 3636 3637 enum { 3638 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3639 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3640 }; 3641 3642 enum { 3643 MLX5_RQC_STATE_RST = 0x0, 3644 MLX5_RQC_STATE_RDY = 0x1, 3645 MLX5_RQC_STATE_ERR = 0x3, 3646 }; 3647 3648 enum { 3649 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3650 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3651 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3652 }; 3653 3654 enum { 3655 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3656 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3657 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3658 }; 3659 3660 struct mlx5_ifc_rqc_bits { 3661 u8 rlky[0x1]; 3662 u8 delay_drop_en[0x1]; 3663 u8 scatter_fcs[0x1]; 3664 u8 vsd[0x1]; 3665 u8 mem_rq_type[0x4]; 3666 u8 state[0x4]; 3667 u8 reserved_at_c[0x1]; 3668 u8 flush_in_error_en[0x1]; 3669 u8 hairpin[0x1]; 3670 u8 reserved_at_f[0xb]; 3671 u8 ts_format[0x2]; 3672 u8 reserved_at_1c[0x4]; 3673 3674 u8 reserved_at_20[0x8]; 3675 u8 user_index[0x18]; 3676 3677 u8 reserved_at_40[0x8]; 3678 u8 cqn[0x18]; 3679 3680 u8 counter_set_id[0x8]; 3681 u8 reserved_at_68[0x18]; 3682 3683 u8 reserved_at_80[0x8]; 3684 u8 rmpn[0x18]; 3685 3686 u8 reserved_at_a0[0x8]; 3687 u8 hairpin_peer_sq[0x18]; 3688 3689 u8 reserved_at_c0[0x10]; 3690 u8 hairpin_peer_vhca[0x10]; 3691 3692 u8 reserved_at_e0[0x46]; 3693 u8 shampo_no_match_alignment_granularity[0x2]; 3694 u8 reserved_at_128[0x6]; 3695 u8 shampo_match_criteria_type[0x2]; 3696 u8 reservation_timeout[0x10]; 3697 3698 u8 reserved_at_140[0x40]; 3699 3700 struct mlx5_ifc_wq_bits wq; 3701 }; 3702 3703 enum { 3704 MLX5_RMPC_STATE_RDY = 0x1, 3705 MLX5_RMPC_STATE_ERR = 0x3, 3706 }; 3707 3708 struct mlx5_ifc_rmpc_bits { 3709 u8 reserved_at_0[0x8]; 3710 u8 state[0x4]; 3711 u8 reserved_at_c[0x14]; 3712 3713 u8 basic_cyclic_rcv_wqe[0x1]; 3714 u8 reserved_at_21[0x1f]; 3715 3716 u8 reserved_at_40[0x140]; 3717 3718 struct mlx5_ifc_wq_bits wq; 3719 }; 3720 3721 struct mlx5_ifc_nic_vport_context_bits { 3722 u8 reserved_at_0[0x5]; 3723 u8 min_wqe_inline_mode[0x3]; 3724 u8 reserved_at_8[0x15]; 3725 u8 disable_mc_local_lb[0x1]; 3726 u8 disable_uc_local_lb[0x1]; 3727 u8 roce_en[0x1]; 3728 3729 u8 arm_change_event[0x1]; 3730 u8 reserved_at_21[0x1a]; 3731 u8 event_on_mtu[0x1]; 3732 u8 event_on_promisc_change[0x1]; 3733 u8 event_on_vlan_change[0x1]; 3734 u8 event_on_mc_address_change[0x1]; 3735 u8 event_on_uc_address_change[0x1]; 3736 3737 u8 reserved_at_40[0xc]; 3738 3739 u8 affiliation_criteria[0x4]; 3740 u8 affiliated_vhca_id[0x10]; 3741 3742 u8 reserved_at_60[0xd0]; 3743 3744 u8 mtu[0x10]; 3745 3746 u8 system_image_guid[0x40]; 3747 u8 port_guid[0x40]; 3748 u8 node_guid[0x40]; 3749 3750 u8 reserved_at_200[0x140]; 3751 u8 qkey_violation_counter[0x10]; 3752 u8 reserved_at_350[0x430]; 3753 3754 u8 promisc_uc[0x1]; 3755 u8 promisc_mc[0x1]; 3756 u8 promisc_all[0x1]; 3757 u8 reserved_at_783[0x2]; 3758 u8 allowed_list_type[0x3]; 3759 u8 reserved_at_788[0xc]; 3760 u8 allowed_list_size[0xc]; 3761 3762 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3763 3764 u8 reserved_at_7e0[0x20]; 3765 3766 u8 current_uc_mac_address[][0x40]; 3767 }; 3768 3769 enum { 3770 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3771 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3772 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3773 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3774 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3775 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3776 }; 3777 3778 struct mlx5_ifc_mkc_bits { 3779 u8 reserved_at_0[0x1]; 3780 u8 free[0x1]; 3781 u8 reserved_at_2[0x1]; 3782 u8 access_mode_4_2[0x3]; 3783 u8 reserved_at_6[0x7]; 3784 u8 relaxed_ordering_write[0x1]; 3785 u8 reserved_at_e[0x1]; 3786 u8 small_fence_on_rdma_read_response[0x1]; 3787 u8 umr_en[0x1]; 3788 u8 a[0x1]; 3789 u8 rw[0x1]; 3790 u8 rr[0x1]; 3791 u8 lw[0x1]; 3792 u8 lr[0x1]; 3793 u8 access_mode_1_0[0x2]; 3794 u8 reserved_at_18[0x8]; 3795 3796 u8 qpn[0x18]; 3797 u8 mkey_7_0[0x8]; 3798 3799 u8 reserved_at_40[0x20]; 3800 3801 u8 length64[0x1]; 3802 u8 bsf_en[0x1]; 3803 u8 sync_umr[0x1]; 3804 u8 reserved_at_63[0x2]; 3805 u8 expected_sigerr_count[0x1]; 3806 u8 reserved_at_66[0x1]; 3807 u8 en_rinval[0x1]; 3808 u8 pd[0x18]; 3809 3810 u8 start_addr[0x40]; 3811 3812 u8 len[0x40]; 3813 3814 u8 bsf_octword_size[0x20]; 3815 3816 u8 reserved_at_120[0x80]; 3817 3818 u8 translations_octword_size[0x20]; 3819 3820 u8 reserved_at_1c0[0x19]; 3821 u8 relaxed_ordering_read[0x1]; 3822 u8 reserved_at_1d9[0x1]; 3823 u8 log_page_size[0x5]; 3824 3825 u8 reserved_at_1e0[0x20]; 3826 }; 3827 3828 struct mlx5_ifc_pkey_bits { 3829 u8 reserved_at_0[0x10]; 3830 u8 pkey[0x10]; 3831 }; 3832 3833 struct mlx5_ifc_array128_auto_bits { 3834 u8 array128_auto[16][0x8]; 3835 }; 3836 3837 struct mlx5_ifc_hca_vport_context_bits { 3838 u8 field_select[0x20]; 3839 3840 u8 reserved_at_20[0xe0]; 3841 3842 u8 sm_virt_aware[0x1]; 3843 u8 has_smi[0x1]; 3844 u8 has_raw[0x1]; 3845 u8 grh_required[0x1]; 3846 u8 reserved_at_104[0xc]; 3847 u8 port_physical_state[0x4]; 3848 u8 vport_state_policy[0x4]; 3849 u8 port_state[0x4]; 3850 u8 vport_state[0x4]; 3851 3852 u8 reserved_at_120[0x20]; 3853 3854 u8 system_image_guid[0x40]; 3855 3856 u8 port_guid[0x40]; 3857 3858 u8 node_guid[0x40]; 3859 3860 u8 cap_mask1[0x20]; 3861 3862 u8 cap_mask1_field_select[0x20]; 3863 3864 u8 cap_mask2[0x20]; 3865 3866 u8 cap_mask2_field_select[0x20]; 3867 3868 u8 reserved_at_280[0x80]; 3869 3870 u8 lid[0x10]; 3871 u8 reserved_at_310[0x4]; 3872 u8 init_type_reply[0x4]; 3873 u8 lmc[0x3]; 3874 u8 subnet_timeout[0x5]; 3875 3876 u8 sm_lid[0x10]; 3877 u8 sm_sl[0x4]; 3878 u8 reserved_at_334[0xc]; 3879 3880 u8 qkey_violation_counter[0x10]; 3881 u8 pkey_violation_counter[0x10]; 3882 3883 u8 reserved_at_360[0xca0]; 3884 }; 3885 3886 struct mlx5_ifc_esw_vport_context_bits { 3887 u8 fdb_to_vport_reg_c[0x1]; 3888 u8 reserved_at_1[0x2]; 3889 u8 vport_svlan_strip[0x1]; 3890 u8 vport_cvlan_strip[0x1]; 3891 u8 vport_svlan_insert[0x1]; 3892 u8 vport_cvlan_insert[0x2]; 3893 u8 fdb_to_vport_reg_c_id[0x8]; 3894 u8 reserved_at_10[0x10]; 3895 3896 u8 reserved_at_20[0x20]; 3897 3898 u8 svlan_cfi[0x1]; 3899 u8 svlan_pcp[0x3]; 3900 u8 svlan_id[0xc]; 3901 u8 cvlan_cfi[0x1]; 3902 u8 cvlan_pcp[0x3]; 3903 u8 cvlan_id[0xc]; 3904 3905 u8 reserved_at_60[0x720]; 3906 3907 u8 sw_steering_vport_icm_address_rx[0x40]; 3908 3909 u8 sw_steering_vport_icm_address_tx[0x40]; 3910 }; 3911 3912 enum { 3913 MLX5_EQC_STATUS_OK = 0x0, 3914 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3915 }; 3916 3917 enum { 3918 MLX5_EQC_ST_ARMED = 0x9, 3919 MLX5_EQC_ST_FIRED = 0xa, 3920 }; 3921 3922 struct mlx5_ifc_eqc_bits { 3923 u8 status[0x4]; 3924 u8 reserved_at_4[0x9]; 3925 u8 ec[0x1]; 3926 u8 oi[0x1]; 3927 u8 reserved_at_f[0x5]; 3928 u8 st[0x4]; 3929 u8 reserved_at_18[0x8]; 3930 3931 u8 reserved_at_20[0x20]; 3932 3933 u8 reserved_at_40[0x14]; 3934 u8 page_offset[0x6]; 3935 u8 reserved_at_5a[0x6]; 3936 3937 u8 reserved_at_60[0x3]; 3938 u8 log_eq_size[0x5]; 3939 u8 uar_page[0x18]; 3940 3941 u8 reserved_at_80[0x20]; 3942 3943 u8 reserved_at_a0[0x14]; 3944 u8 intr[0xc]; 3945 3946 u8 reserved_at_c0[0x3]; 3947 u8 log_page_size[0x5]; 3948 u8 reserved_at_c8[0x18]; 3949 3950 u8 reserved_at_e0[0x60]; 3951 3952 u8 reserved_at_140[0x8]; 3953 u8 consumer_counter[0x18]; 3954 3955 u8 reserved_at_160[0x8]; 3956 u8 producer_counter[0x18]; 3957 3958 u8 reserved_at_180[0x80]; 3959 }; 3960 3961 enum { 3962 MLX5_DCTC_STATE_ACTIVE = 0x0, 3963 MLX5_DCTC_STATE_DRAINING = 0x1, 3964 MLX5_DCTC_STATE_DRAINED = 0x2, 3965 }; 3966 3967 enum { 3968 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3969 MLX5_DCTC_CS_RES_NA = 0x1, 3970 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3971 }; 3972 3973 enum { 3974 MLX5_DCTC_MTU_256_BYTES = 0x1, 3975 MLX5_DCTC_MTU_512_BYTES = 0x2, 3976 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3977 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3978 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3979 }; 3980 3981 struct mlx5_ifc_dctc_bits { 3982 u8 reserved_at_0[0x4]; 3983 u8 state[0x4]; 3984 u8 reserved_at_8[0x18]; 3985 3986 u8 reserved_at_20[0x8]; 3987 u8 user_index[0x18]; 3988 3989 u8 reserved_at_40[0x8]; 3990 u8 cqn[0x18]; 3991 3992 u8 counter_set_id[0x8]; 3993 u8 atomic_mode[0x4]; 3994 u8 rre[0x1]; 3995 u8 rwe[0x1]; 3996 u8 rae[0x1]; 3997 u8 atomic_like_write_en[0x1]; 3998 u8 latency_sensitive[0x1]; 3999 u8 rlky[0x1]; 4000 u8 free_ar[0x1]; 4001 u8 reserved_at_73[0xd]; 4002 4003 u8 reserved_at_80[0x8]; 4004 u8 cs_res[0x8]; 4005 u8 reserved_at_90[0x3]; 4006 u8 min_rnr_nak[0x5]; 4007 u8 reserved_at_98[0x8]; 4008 4009 u8 reserved_at_a0[0x8]; 4010 u8 srqn_xrqn[0x18]; 4011 4012 u8 reserved_at_c0[0x8]; 4013 u8 pd[0x18]; 4014 4015 u8 tclass[0x8]; 4016 u8 reserved_at_e8[0x4]; 4017 u8 flow_label[0x14]; 4018 4019 u8 dc_access_key[0x40]; 4020 4021 u8 reserved_at_140[0x5]; 4022 u8 mtu[0x3]; 4023 u8 port[0x8]; 4024 u8 pkey_index[0x10]; 4025 4026 u8 reserved_at_160[0x8]; 4027 u8 my_addr_index[0x8]; 4028 u8 reserved_at_170[0x8]; 4029 u8 hop_limit[0x8]; 4030 4031 u8 dc_access_key_violation_count[0x20]; 4032 4033 u8 reserved_at_1a0[0x14]; 4034 u8 dei_cfi[0x1]; 4035 u8 eth_prio[0x3]; 4036 u8 ecn[0x2]; 4037 u8 dscp[0x6]; 4038 4039 u8 reserved_at_1c0[0x20]; 4040 u8 ece[0x20]; 4041 }; 4042 4043 enum { 4044 MLX5_CQC_STATUS_OK = 0x0, 4045 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4046 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4047 }; 4048 4049 enum { 4050 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4051 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4052 }; 4053 4054 enum { 4055 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4056 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4057 MLX5_CQC_ST_FIRED = 0xa, 4058 }; 4059 4060 enum { 4061 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4062 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4063 MLX5_CQ_PERIOD_NUM_MODES 4064 }; 4065 4066 struct mlx5_ifc_cqc_bits { 4067 u8 status[0x4]; 4068 u8 reserved_at_4[0x2]; 4069 u8 dbr_umem_valid[0x1]; 4070 u8 apu_cq[0x1]; 4071 u8 cqe_sz[0x3]; 4072 u8 cc[0x1]; 4073 u8 reserved_at_c[0x1]; 4074 u8 scqe_break_moderation_en[0x1]; 4075 u8 oi[0x1]; 4076 u8 cq_period_mode[0x2]; 4077 u8 cqe_comp_en[0x1]; 4078 u8 mini_cqe_res_format[0x2]; 4079 u8 st[0x4]; 4080 u8 reserved_at_18[0x8]; 4081 4082 u8 reserved_at_20[0x20]; 4083 4084 u8 reserved_at_40[0x14]; 4085 u8 page_offset[0x6]; 4086 u8 reserved_at_5a[0x6]; 4087 4088 u8 reserved_at_60[0x3]; 4089 u8 log_cq_size[0x5]; 4090 u8 uar_page[0x18]; 4091 4092 u8 reserved_at_80[0x4]; 4093 u8 cq_period[0xc]; 4094 u8 cq_max_count[0x10]; 4095 4096 u8 c_eqn_or_apu_element[0x20]; 4097 4098 u8 reserved_at_c0[0x3]; 4099 u8 log_page_size[0x5]; 4100 u8 reserved_at_c8[0x18]; 4101 4102 u8 reserved_at_e0[0x20]; 4103 4104 u8 reserved_at_100[0x8]; 4105 u8 last_notified_index[0x18]; 4106 4107 u8 reserved_at_120[0x8]; 4108 u8 last_solicit_index[0x18]; 4109 4110 u8 reserved_at_140[0x8]; 4111 u8 consumer_counter[0x18]; 4112 4113 u8 reserved_at_160[0x8]; 4114 u8 producer_counter[0x18]; 4115 4116 u8 reserved_at_180[0x40]; 4117 4118 u8 dbr_addr[0x40]; 4119 }; 4120 4121 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4122 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4123 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4124 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4125 u8 reserved_at_0[0x800]; 4126 }; 4127 4128 struct mlx5_ifc_query_adapter_param_block_bits { 4129 u8 reserved_at_0[0xc0]; 4130 4131 u8 reserved_at_c0[0x8]; 4132 u8 ieee_vendor_id[0x18]; 4133 4134 u8 reserved_at_e0[0x10]; 4135 u8 vsd_vendor_id[0x10]; 4136 4137 u8 vsd[208][0x8]; 4138 4139 u8 vsd_contd_psid[16][0x8]; 4140 }; 4141 4142 enum { 4143 MLX5_XRQC_STATE_GOOD = 0x0, 4144 MLX5_XRQC_STATE_ERROR = 0x1, 4145 }; 4146 4147 enum { 4148 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4149 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4150 }; 4151 4152 enum { 4153 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4154 }; 4155 4156 struct mlx5_ifc_tag_matching_topology_context_bits { 4157 u8 log_matching_list_sz[0x4]; 4158 u8 reserved_at_4[0xc]; 4159 u8 append_next_index[0x10]; 4160 4161 u8 sw_phase_cnt[0x10]; 4162 u8 hw_phase_cnt[0x10]; 4163 4164 u8 reserved_at_40[0x40]; 4165 }; 4166 4167 struct mlx5_ifc_xrqc_bits { 4168 u8 state[0x4]; 4169 u8 rlkey[0x1]; 4170 u8 reserved_at_5[0xf]; 4171 u8 topology[0x4]; 4172 u8 reserved_at_18[0x4]; 4173 u8 offload[0x4]; 4174 4175 u8 reserved_at_20[0x8]; 4176 u8 user_index[0x18]; 4177 4178 u8 reserved_at_40[0x8]; 4179 u8 cqn[0x18]; 4180 4181 u8 reserved_at_60[0xa0]; 4182 4183 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4184 4185 u8 reserved_at_180[0x280]; 4186 4187 struct mlx5_ifc_wq_bits wq; 4188 }; 4189 4190 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4191 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4192 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4193 u8 reserved_at_0[0x20]; 4194 }; 4195 4196 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4197 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4198 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4199 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4200 u8 reserved_at_0[0x20]; 4201 }; 4202 4203 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4204 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4205 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4206 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4207 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4208 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4209 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4210 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4211 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4212 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4213 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4214 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4215 u8 reserved_at_0[0x7c0]; 4216 }; 4217 4218 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4219 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4220 u8 reserved_at_0[0x7c0]; 4221 }; 4222 4223 union mlx5_ifc_event_auto_bits { 4224 struct mlx5_ifc_comp_event_bits comp_event; 4225 struct mlx5_ifc_dct_events_bits dct_events; 4226 struct mlx5_ifc_qp_events_bits qp_events; 4227 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4228 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4229 struct mlx5_ifc_cq_error_bits cq_error; 4230 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4231 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4232 struct mlx5_ifc_gpio_event_bits gpio_event; 4233 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4234 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4235 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4236 u8 reserved_at_0[0xe0]; 4237 }; 4238 4239 struct mlx5_ifc_health_buffer_bits { 4240 u8 reserved_at_0[0x100]; 4241 4242 u8 assert_existptr[0x20]; 4243 4244 u8 assert_callra[0x20]; 4245 4246 u8 reserved_at_140[0x20]; 4247 4248 u8 time[0x20]; 4249 4250 u8 fw_version[0x20]; 4251 4252 u8 hw_id[0x20]; 4253 4254 u8 rfr[0x1]; 4255 u8 reserved_at_1c1[0x3]; 4256 u8 valid[0x1]; 4257 u8 severity[0x3]; 4258 u8 reserved_at_1c8[0x18]; 4259 4260 u8 irisc_index[0x8]; 4261 u8 synd[0x8]; 4262 u8 ext_synd[0x10]; 4263 }; 4264 4265 struct mlx5_ifc_register_loopback_control_bits { 4266 u8 no_lb[0x1]; 4267 u8 reserved_at_1[0x7]; 4268 u8 port[0x8]; 4269 u8 reserved_at_10[0x10]; 4270 4271 u8 reserved_at_20[0x60]; 4272 }; 4273 4274 struct mlx5_ifc_vport_tc_element_bits { 4275 u8 traffic_class[0x4]; 4276 u8 reserved_at_4[0xc]; 4277 u8 vport_number[0x10]; 4278 }; 4279 4280 struct mlx5_ifc_vport_element_bits { 4281 u8 reserved_at_0[0x10]; 4282 u8 vport_number[0x10]; 4283 }; 4284 4285 enum { 4286 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4287 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4288 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4289 }; 4290 4291 struct mlx5_ifc_tsar_element_bits { 4292 u8 reserved_at_0[0x8]; 4293 u8 tsar_type[0x8]; 4294 u8 reserved_at_10[0x10]; 4295 }; 4296 4297 enum { 4298 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4299 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4300 }; 4301 4302 struct mlx5_ifc_teardown_hca_out_bits { 4303 u8 status[0x8]; 4304 u8 reserved_at_8[0x18]; 4305 4306 u8 syndrome[0x20]; 4307 4308 u8 reserved_at_40[0x3f]; 4309 4310 u8 state[0x1]; 4311 }; 4312 4313 enum { 4314 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4315 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4316 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4317 }; 4318 4319 struct mlx5_ifc_teardown_hca_in_bits { 4320 u8 opcode[0x10]; 4321 u8 reserved_at_10[0x10]; 4322 4323 u8 reserved_at_20[0x10]; 4324 u8 op_mod[0x10]; 4325 4326 u8 reserved_at_40[0x10]; 4327 u8 profile[0x10]; 4328 4329 u8 reserved_at_60[0x20]; 4330 }; 4331 4332 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4333 u8 status[0x8]; 4334 u8 reserved_at_8[0x18]; 4335 4336 u8 syndrome[0x20]; 4337 4338 u8 reserved_at_40[0x40]; 4339 }; 4340 4341 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4342 u8 opcode[0x10]; 4343 u8 uid[0x10]; 4344 4345 u8 reserved_at_20[0x10]; 4346 u8 op_mod[0x10]; 4347 4348 u8 reserved_at_40[0x8]; 4349 u8 qpn[0x18]; 4350 4351 u8 reserved_at_60[0x20]; 4352 4353 u8 opt_param_mask[0x20]; 4354 4355 u8 reserved_at_a0[0x20]; 4356 4357 struct mlx5_ifc_qpc_bits qpc; 4358 4359 u8 reserved_at_800[0x80]; 4360 }; 4361 4362 struct mlx5_ifc_sqd2rts_qp_out_bits { 4363 u8 status[0x8]; 4364 u8 reserved_at_8[0x18]; 4365 4366 u8 syndrome[0x20]; 4367 4368 u8 reserved_at_40[0x40]; 4369 }; 4370 4371 struct mlx5_ifc_sqd2rts_qp_in_bits { 4372 u8 opcode[0x10]; 4373 u8 uid[0x10]; 4374 4375 u8 reserved_at_20[0x10]; 4376 u8 op_mod[0x10]; 4377 4378 u8 reserved_at_40[0x8]; 4379 u8 qpn[0x18]; 4380 4381 u8 reserved_at_60[0x20]; 4382 4383 u8 opt_param_mask[0x20]; 4384 4385 u8 reserved_at_a0[0x20]; 4386 4387 struct mlx5_ifc_qpc_bits qpc; 4388 4389 u8 reserved_at_800[0x80]; 4390 }; 4391 4392 struct mlx5_ifc_set_roce_address_out_bits { 4393 u8 status[0x8]; 4394 u8 reserved_at_8[0x18]; 4395 4396 u8 syndrome[0x20]; 4397 4398 u8 reserved_at_40[0x40]; 4399 }; 4400 4401 struct mlx5_ifc_set_roce_address_in_bits { 4402 u8 opcode[0x10]; 4403 u8 reserved_at_10[0x10]; 4404 4405 u8 reserved_at_20[0x10]; 4406 u8 op_mod[0x10]; 4407 4408 u8 roce_address_index[0x10]; 4409 u8 reserved_at_50[0xc]; 4410 u8 vhca_port_num[0x4]; 4411 4412 u8 reserved_at_60[0x20]; 4413 4414 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4415 }; 4416 4417 struct mlx5_ifc_set_mad_demux_out_bits { 4418 u8 status[0x8]; 4419 u8 reserved_at_8[0x18]; 4420 4421 u8 syndrome[0x20]; 4422 4423 u8 reserved_at_40[0x40]; 4424 }; 4425 4426 enum { 4427 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4428 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4429 }; 4430 4431 struct mlx5_ifc_set_mad_demux_in_bits { 4432 u8 opcode[0x10]; 4433 u8 reserved_at_10[0x10]; 4434 4435 u8 reserved_at_20[0x10]; 4436 u8 op_mod[0x10]; 4437 4438 u8 reserved_at_40[0x20]; 4439 4440 u8 reserved_at_60[0x6]; 4441 u8 demux_mode[0x2]; 4442 u8 reserved_at_68[0x18]; 4443 }; 4444 4445 struct mlx5_ifc_set_l2_table_entry_out_bits { 4446 u8 status[0x8]; 4447 u8 reserved_at_8[0x18]; 4448 4449 u8 syndrome[0x20]; 4450 4451 u8 reserved_at_40[0x40]; 4452 }; 4453 4454 struct mlx5_ifc_set_l2_table_entry_in_bits { 4455 u8 opcode[0x10]; 4456 u8 reserved_at_10[0x10]; 4457 4458 u8 reserved_at_20[0x10]; 4459 u8 op_mod[0x10]; 4460 4461 u8 reserved_at_40[0x60]; 4462 4463 u8 reserved_at_a0[0x8]; 4464 u8 table_index[0x18]; 4465 4466 u8 reserved_at_c0[0x20]; 4467 4468 u8 reserved_at_e0[0x13]; 4469 u8 vlan_valid[0x1]; 4470 u8 vlan[0xc]; 4471 4472 struct mlx5_ifc_mac_address_layout_bits mac_address; 4473 4474 u8 reserved_at_140[0xc0]; 4475 }; 4476 4477 struct mlx5_ifc_set_issi_out_bits { 4478 u8 status[0x8]; 4479 u8 reserved_at_8[0x18]; 4480 4481 u8 syndrome[0x20]; 4482 4483 u8 reserved_at_40[0x40]; 4484 }; 4485 4486 struct mlx5_ifc_set_issi_in_bits { 4487 u8 opcode[0x10]; 4488 u8 reserved_at_10[0x10]; 4489 4490 u8 reserved_at_20[0x10]; 4491 u8 op_mod[0x10]; 4492 4493 u8 reserved_at_40[0x10]; 4494 u8 current_issi[0x10]; 4495 4496 u8 reserved_at_60[0x20]; 4497 }; 4498 4499 struct mlx5_ifc_set_hca_cap_out_bits { 4500 u8 status[0x8]; 4501 u8 reserved_at_8[0x18]; 4502 4503 u8 syndrome[0x20]; 4504 4505 u8 reserved_at_40[0x40]; 4506 }; 4507 4508 struct mlx5_ifc_set_hca_cap_in_bits { 4509 u8 opcode[0x10]; 4510 u8 reserved_at_10[0x10]; 4511 4512 u8 reserved_at_20[0x10]; 4513 u8 op_mod[0x10]; 4514 4515 u8 other_function[0x1]; 4516 u8 reserved_at_41[0xf]; 4517 u8 function_id[0x10]; 4518 4519 u8 reserved_at_60[0x20]; 4520 4521 union mlx5_ifc_hca_cap_union_bits capability; 4522 }; 4523 4524 enum { 4525 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4526 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4527 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4528 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4529 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4530 }; 4531 4532 struct mlx5_ifc_set_fte_out_bits { 4533 u8 status[0x8]; 4534 u8 reserved_at_8[0x18]; 4535 4536 u8 syndrome[0x20]; 4537 4538 u8 reserved_at_40[0x40]; 4539 }; 4540 4541 struct mlx5_ifc_set_fte_in_bits { 4542 u8 opcode[0x10]; 4543 u8 reserved_at_10[0x10]; 4544 4545 u8 reserved_at_20[0x10]; 4546 u8 op_mod[0x10]; 4547 4548 u8 other_vport[0x1]; 4549 u8 reserved_at_41[0xf]; 4550 u8 vport_number[0x10]; 4551 4552 u8 reserved_at_60[0x20]; 4553 4554 u8 table_type[0x8]; 4555 u8 reserved_at_88[0x18]; 4556 4557 u8 reserved_at_a0[0x8]; 4558 u8 table_id[0x18]; 4559 4560 u8 ignore_flow_level[0x1]; 4561 u8 reserved_at_c1[0x17]; 4562 u8 modify_enable_mask[0x8]; 4563 4564 u8 reserved_at_e0[0x20]; 4565 4566 u8 flow_index[0x20]; 4567 4568 u8 reserved_at_120[0xe0]; 4569 4570 struct mlx5_ifc_flow_context_bits flow_context; 4571 }; 4572 4573 struct mlx5_ifc_rts2rts_qp_out_bits { 4574 u8 status[0x8]; 4575 u8 reserved_at_8[0x18]; 4576 4577 u8 syndrome[0x20]; 4578 4579 u8 reserved_at_40[0x20]; 4580 u8 ece[0x20]; 4581 }; 4582 4583 struct mlx5_ifc_rts2rts_qp_in_bits { 4584 u8 opcode[0x10]; 4585 u8 uid[0x10]; 4586 4587 u8 reserved_at_20[0x10]; 4588 u8 op_mod[0x10]; 4589 4590 u8 reserved_at_40[0x8]; 4591 u8 qpn[0x18]; 4592 4593 u8 reserved_at_60[0x20]; 4594 4595 u8 opt_param_mask[0x20]; 4596 4597 u8 ece[0x20]; 4598 4599 struct mlx5_ifc_qpc_bits qpc; 4600 4601 u8 reserved_at_800[0x80]; 4602 }; 4603 4604 struct mlx5_ifc_rtr2rts_qp_out_bits { 4605 u8 status[0x8]; 4606 u8 reserved_at_8[0x18]; 4607 4608 u8 syndrome[0x20]; 4609 4610 u8 reserved_at_40[0x20]; 4611 u8 ece[0x20]; 4612 }; 4613 4614 struct mlx5_ifc_rtr2rts_qp_in_bits { 4615 u8 opcode[0x10]; 4616 u8 uid[0x10]; 4617 4618 u8 reserved_at_20[0x10]; 4619 u8 op_mod[0x10]; 4620 4621 u8 reserved_at_40[0x8]; 4622 u8 qpn[0x18]; 4623 4624 u8 reserved_at_60[0x20]; 4625 4626 u8 opt_param_mask[0x20]; 4627 4628 u8 ece[0x20]; 4629 4630 struct mlx5_ifc_qpc_bits qpc; 4631 4632 u8 reserved_at_800[0x80]; 4633 }; 4634 4635 struct mlx5_ifc_rst2init_qp_out_bits { 4636 u8 status[0x8]; 4637 u8 reserved_at_8[0x18]; 4638 4639 u8 syndrome[0x20]; 4640 4641 u8 reserved_at_40[0x20]; 4642 u8 ece[0x20]; 4643 }; 4644 4645 struct mlx5_ifc_rst2init_qp_in_bits { 4646 u8 opcode[0x10]; 4647 u8 uid[0x10]; 4648 4649 u8 reserved_at_20[0x10]; 4650 u8 op_mod[0x10]; 4651 4652 u8 reserved_at_40[0x8]; 4653 u8 qpn[0x18]; 4654 4655 u8 reserved_at_60[0x20]; 4656 4657 u8 opt_param_mask[0x20]; 4658 4659 u8 ece[0x20]; 4660 4661 struct mlx5_ifc_qpc_bits qpc; 4662 4663 u8 reserved_at_800[0x80]; 4664 }; 4665 4666 struct mlx5_ifc_query_xrq_out_bits { 4667 u8 status[0x8]; 4668 u8 reserved_at_8[0x18]; 4669 4670 u8 syndrome[0x20]; 4671 4672 u8 reserved_at_40[0x40]; 4673 4674 struct mlx5_ifc_xrqc_bits xrq_context; 4675 }; 4676 4677 struct mlx5_ifc_query_xrq_in_bits { 4678 u8 opcode[0x10]; 4679 u8 reserved_at_10[0x10]; 4680 4681 u8 reserved_at_20[0x10]; 4682 u8 op_mod[0x10]; 4683 4684 u8 reserved_at_40[0x8]; 4685 u8 xrqn[0x18]; 4686 4687 u8 reserved_at_60[0x20]; 4688 }; 4689 4690 struct mlx5_ifc_query_xrc_srq_out_bits { 4691 u8 status[0x8]; 4692 u8 reserved_at_8[0x18]; 4693 4694 u8 syndrome[0x20]; 4695 4696 u8 reserved_at_40[0x40]; 4697 4698 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4699 4700 u8 reserved_at_280[0x600]; 4701 4702 u8 pas[][0x40]; 4703 }; 4704 4705 struct mlx5_ifc_query_xrc_srq_in_bits { 4706 u8 opcode[0x10]; 4707 u8 reserved_at_10[0x10]; 4708 4709 u8 reserved_at_20[0x10]; 4710 u8 op_mod[0x10]; 4711 4712 u8 reserved_at_40[0x8]; 4713 u8 xrc_srqn[0x18]; 4714 4715 u8 reserved_at_60[0x20]; 4716 }; 4717 4718 enum { 4719 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4720 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4721 }; 4722 4723 struct mlx5_ifc_query_vport_state_out_bits { 4724 u8 status[0x8]; 4725 u8 reserved_at_8[0x18]; 4726 4727 u8 syndrome[0x20]; 4728 4729 u8 reserved_at_40[0x20]; 4730 4731 u8 reserved_at_60[0x18]; 4732 u8 admin_state[0x4]; 4733 u8 state[0x4]; 4734 }; 4735 4736 enum { 4737 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4738 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4739 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4740 }; 4741 4742 struct mlx5_ifc_arm_monitor_counter_in_bits { 4743 u8 opcode[0x10]; 4744 u8 uid[0x10]; 4745 4746 u8 reserved_at_20[0x10]; 4747 u8 op_mod[0x10]; 4748 4749 u8 reserved_at_40[0x20]; 4750 4751 u8 reserved_at_60[0x20]; 4752 }; 4753 4754 struct mlx5_ifc_arm_monitor_counter_out_bits { 4755 u8 status[0x8]; 4756 u8 reserved_at_8[0x18]; 4757 4758 u8 syndrome[0x20]; 4759 4760 u8 reserved_at_40[0x40]; 4761 }; 4762 4763 enum { 4764 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4765 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4766 }; 4767 4768 enum mlx5_monitor_counter_ppcnt { 4769 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4770 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4771 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4772 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4773 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4774 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4775 }; 4776 4777 enum { 4778 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4779 }; 4780 4781 struct mlx5_ifc_monitor_counter_output_bits { 4782 u8 reserved_at_0[0x4]; 4783 u8 type[0x4]; 4784 u8 reserved_at_8[0x8]; 4785 u8 counter[0x10]; 4786 4787 u8 counter_group_id[0x20]; 4788 }; 4789 4790 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4791 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4792 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4793 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4794 4795 struct mlx5_ifc_set_monitor_counter_in_bits { 4796 u8 opcode[0x10]; 4797 u8 uid[0x10]; 4798 4799 u8 reserved_at_20[0x10]; 4800 u8 op_mod[0x10]; 4801 4802 u8 reserved_at_40[0x10]; 4803 u8 num_of_counters[0x10]; 4804 4805 u8 reserved_at_60[0x20]; 4806 4807 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4808 }; 4809 4810 struct mlx5_ifc_set_monitor_counter_out_bits { 4811 u8 status[0x8]; 4812 u8 reserved_at_8[0x18]; 4813 4814 u8 syndrome[0x20]; 4815 4816 u8 reserved_at_40[0x40]; 4817 }; 4818 4819 struct mlx5_ifc_query_vport_state_in_bits { 4820 u8 opcode[0x10]; 4821 u8 reserved_at_10[0x10]; 4822 4823 u8 reserved_at_20[0x10]; 4824 u8 op_mod[0x10]; 4825 4826 u8 other_vport[0x1]; 4827 u8 reserved_at_41[0xf]; 4828 u8 vport_number[0x10]; 4829 4830 u8 reserved_at_60[0x20]; 4831 }; 4832 4833 struct mlx5_ifc_query_vnic_env_out_bits { 4834 u8 status[0x8]; 4835 u8 reserved_at_8[0x18]; 4836 4837 u8 syndrome[0x20]; 4838 4839 u8 reserved_at_40[0x40]; 4840 4841 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4842 }; 4843 4844 enum { 4845 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4846 }; 4847 4848 struct mlx5_ifc_query_vnic_env_in_bits { 4849 u8 opcode[0x10]; 4850 u8 reserved_at_10[0x10]; 4851 4852 u8 reserved_at_20[0x10]; 4853 u8 op_mod[0x10]; 4854 4855 u8 other_vport[0x1]; 4856 u8 reserved_at_41[0xf]; 4857 u8 vport_number[0x10]; 4858 4859 u8 reserved_at_60[0x20]; 4860 }; 4861 4862 struct mlx5_ifc_query_vport_counter_out_bits { 4863 u8 status[0x8]; 4864 u8 reserved_at_8[0x18]; 4865 4866 u8 syndrome[0x20]; 4867 4868 u8 reserved_at_40[0x40]; 4869 4870 struct mlx5_ifc_traffic_counter_bits received_errors; 4871 4872 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4873 4874 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4875 4876 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4877 4878 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4879 4880 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4881 4882 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4883 4884 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4885 4886 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4887 4888 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4889 4890 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4891 4892 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4893 4894 u8 reserved_at_680[0xa00]; 4895 }; 4896 4897 enum { 4898 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4899 }; 4900 4901 struct mlx5_ifc_query_vport_counter_in_bits { 4902 u8 opcode[0x10]; 4903 u8 reserved_at_10[0x10]; 4904 4905 u8 reserved_at_20[0x10]; 4906 u8 op_mod[0x10]; 4907 4908 u8 other_vport[0x1]; 4909 u8 reserved_at_41[0xb]; 4910 u8 port_num[0x4]; 4911 u8 vport_number[0x10]; 4912 4913 u8 reserved_at_60[0x60]; 4914 4915 u8 clear[0x1]; 4916 u8 reserved_at_c1[0x1f]; 4917 4918 u8 reserved_at_e0[0x20]; 4919 }; 4920 4921 struct mlx5_ifc_query_tis_out_bits { 4922 u8 status[0x8]; 4923 u8 reserved_at_8[0x18]; 4924 4925 u8 syndrome[0x20]; 4926 4927 u8 reserved_at_40[0x40]; 4928 4929 struct mlx5_ifc_tisc_bits tis_context; 4930 }; 4931 4932 struct mlx5_ifc_query_tis_in_bits { 4933 u8 opcode[0x10]; 4934 u8 reserved_at_10[0x10]; 4935 4936 u8 reserved_at_20[0x10]; 4937 u8 op_mod[0x10]; 4938 4939 u8 reserved_at_40[0x8]; 4940 u8 tisn[0x18]; 4941 4942 u8 reserved_at_60[0x20]; 4943 }; 4944 4945 struct mlx5_ifc_query_tir_out_bits { 4946 u8 status[0x8]; 4947 u8 reserved_at_8[0x18]; 4948 4949 u8 syndrome[0x20]; 4950 4951 u8 reserved_at_40[0xc0]; 4952 4953 struct mlx5_ifc_tirc_bits tir_context; 4954 }; 4955 4956 struct mlx5_ifc_query_tir_in_bits { 4957 u8 opcode[0x10]; 4958 u8 reserved_at_10[0x10]; 4959 4960 u8 reserved_at_20[0x10]; 4961 u8 op_mod[0x10]; 4962 4963 u8 reserved_at_40[0x8]; 4964 u8 tirn[0x18]; 4965 4966 u8 reserved_at_60[0x20]; 4967 }; 4968 4969 struct mlx5_ifc_query_srq_out_bits { 4970 u8 status[0x8]; 4971 u8 reserved_at_8[0x18]; 4972 4973 u8 syndrome[0x20]; 4974 4975 u8 reserved_at_40[0x40]; 4976 4977 struct mlx5_ifc_srqc_bits srq_context_entry; 4978 4979 u8 reserved_at_280[0x600]; 4980 4981 u8 pas[][0x40]; 4982 }; 4983 4984 struct mlx5_ifc_query_srq_in_bits { 4985 u8 opcode[0x10]; 4986 u8 reserved_at_10[0x10]; 4987 4988 u8 reserved_at_20[0x10]; 4989 u8 op_mod[0x10]; 4990 4991 u8 reserved_at_40[0x8]; 4992 u8 srqn[0x18]; 4993 4994 u8 reserved_at_60[0x20]; 4995 }; 4996 4997 struct mlx5_ifc_query_sq_out_bits { 4998 u8 status[0x8]; 4999 u8 reserved_at_8[0x18]; 5000 5001 u8 syndrome[0x20]; 5002 5003 u8 reserved_at_40[0xc0]; 5004 5005 struct mlx5_ifc_sqc_bits sq_context; 5006 }; 5007 5008 struct mlx5_ifc_query_sq_in_bits { 5009 u8 opcode[0x10]; 5010 u8 reserved_at_10[0x10]; 5011 5012 u8 reserved_at_20[0x10]; 5013 u8 op_mod[0x10]; 5014 5015 u8 reserved_at_40[0x8]; 5016 u8 sqn[0x18]; 5017 5018 u8 reserved_at_60[0x20]; 5019 }; 5020 5021 struct mlx5_ifc_query_special_contexts_out_bits { 5022 u8 status[0x8]; 5023 u8 reserved_at_8[0x18]; 5024 5025 u8 syndrome[0x20]; 5026 5027 u8 dump_fill_mkey[0x20]; 5028 5029 u8 resd_lkey[0x20]; 5030 5031 u8 null_mkey[0x20]; 5032 5033 u8 reserved_at_a0[0x60]; 5034 }; 5035 5036 struct mlx5_ifc_query_special_contexts_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_at_10[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 reserved_at_40[0x40]; 5044 }; 5045 5046 struct mlx5_ifc_query_scheduling_element_out_bits { 5047 u8 opcode[0x10]; 5048 u8 reserved_at_10[0x10]; 5049 5050 u8 reserved_at_20[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 reserved_at_40[0xc0]; 5054 5055 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5056 5057 u8 reserved_at_300[0x100]; 5058 }; 5059 5060 enum { 5061 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5062 SCHEDULING_HIERARCHY_NIC = 0x3, 5063 }; 5064 5065 struct mlx5_ifc_query_scheduling_element_in_bits { 5066 u8 opcode[0x10]; 5067 u8 reserved_at_10[0x10]; 5068 5069 u8 reserved_at_20[0x10]; 5070 u8 op_mod[0x10]; 5071 5072 u8 scheduling_hierarchy[0x8]; 5073 u8 reserved_at_48[0x18]; 5074 5075 u8 scheduling_element_id[0x20]; 5076 5077 u8 reserved_at_80[0x180]; 5078 }; 5079 5080 struct mlx5_ifc_query_rqt_out_bits { 5081 u8 status[0x8]; 5082 u8 reserved_at_8[0x18]; 5083 5084 u8 syndrome[0x20]; 5085 5086 u8 reserved_at_40[0xc0]; 5087 5088 struct mlx5_ifc_rqtc_bits rqt_context; 5089 }; 5090 5091 struct mlx5_ifc_query_rqt_in_bits { 5092 u8 opcode[0x10]; 5093 u8 reserved_at_10[0x10]; 5094 5095 u8 reserved_at_20[0x10]; 5096 u8 op_mod[0x10]; 5097 5098 u8 reserved_at_40[0x8]; 5099 u8 rqtn[0x18]; 5100 5101 u8 reserved_at_60[0x20]; 5102 }; 5103 5104 struct mlx5_ifc_query_rq_out_bits { 5105 u8 status[0x8]; 5106 u8 reserved_at_8[0x18]; 5107 5108 u8 syndrome[0x20]; 5109 5110 u8 reserved_at_40[0xc0]; 5111 5112 struct mlx5_ifc_rqc_bits rq_context; 5113 }; 5114 5115 struct mlx5_ifc_query_rq_in_bits { 5116 u8 opcode[0x10]; 5117 u8 reserved_at_10[0x10]; 5118 5119 u8 reserved_at_20[0x10]; 5120 u8 op_mod[0x10]; 5121 5122 u8 reserved_at_40[0x8]; 5123 u8 rqn[0x18]; 5124 5125 u8 reserved_at_60[0x20]; 5126 }; 5127 5128 struct mlx5_ifc_query_roce_address_out_bits { 5129 u8 status[0x8]; 5130 u8 reserved_at_8[0x18]; 5131 5132 u8 syndrome[0x20]; 5133 5134 u8 reserved_at_40[0x40]; 5135 5136 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5137 }; 5138 5139 struct mlx5_ifc_query_roce_address_in_bits { 5140 u8 opcode[0x10]; 5141 u8 reserved_at_10[0x10]; 5142 5143 u8 reserved_at_20[0x10]; 5144 u8 op_mod[0x10]; 5145 5146 u8 roce_address_index[0x10]; 5147 u8 reserved_at_50[0xc]; 5148 u8 vhca_port_num[0x4]; 5149 5150 u8 reserved_at_60[0x20]; 5151 }; 5152 5153 struct mlx5_ifc_query_rmp_out_bits { 5154 u8 status[0x8]; 5155 u8 reserved_at_8[0x18]; 5156 5157 u8 syndrome[0x20]; 5158 5159 u8 reserved_at_40[0xc0]; 5160 5161 struct mlx5_ifc_rmpc_bits rmp_context; 5162 }; 5163 5164 struct mlx5_ifc_query_rmp_in_bits { 5165 u8 opcode[0x10]; 5166 u8 reserved_at_10[0x10]; 5167 5168 u8 reserved_at_20[0x10]; 5169 u8 op_mod[0x10]; 5170 5171 u8 reserved_at_40[0x8]; 5172 u8 rmpn[0x18]; 5173 5174 u8 reserved_at_60[0x20]; 5175 }; 5176 5177 struct mlx5_ifc_query_qp_out_bits { 5178 u8 status[0x8]; 5179 u8 reserved_at_8[0x18]; 5180 5181 u8 syndrome[0x20]; 5182 5183 u8 reserved_at_40[0x20]; 5184 u8 ece[0x20]; 5185 5186 u8 opt_param_mask[0x20]; 5187 5188 u8 reserved_at_a0[0x20]; 5189 5190 struct mlx5_ifc_qpc_bits qpc; 5191 5192 u8 reserved_at_800[0x80]; 5193 5194 u8 pas[][0x40]; 5195 }; 5196 5197 struct mlx5_ifc_query_qp_in_bits { 5198 u8 opcode[0x10]; 5199 u8 reserved_at_10[0x10]; 5200 5201 u8 reserved_at_20[0x10]; 5202 u8 op_mod[0x10]; 5203 5204 u8 reserved_at_40[0x8]; 5205 u8 qpn[0x18]; 5206 5207 u8 reserved_at_60[0x20]; 5208 }; 5209 5210 struct mlx5_ifc_query_q_counter_out_bits { 5211 u8 status[0x8]; 5212 u8 reserved_at_8[0x18]; 5213 5214 u8 syndrome[0x20]; 5215 5216 u8 reserved_at_40[0x40]; 5217 5218 u8 rx_write_requests[0x20]; 5219 5220 u8 reserved_at_a0[0x20]; 5221 5222 u8 rx_read_requests[0x20]; 5223 5224 u8 reserved_at_e0[0x20]; 5225 5226 u8 rx_atomic_requests[0x20]; 5227 5228 u8 reserved_at_120[0x20]; 5229 5230 u8 rx_dct_connect[0x20]; 5231 5232 u8 reserved_at_160[0x20]; 5233 5234 u8 out_of_buffer[0x20]; 5235 5236 u8 reserved_at_1a0[0x20]; 5237 5238 u8 out_of_sequence[0x20]; 5239 5240 u8 reserved_at_1e0[0x20]; 5241 5242 u8 duplicate_request[0x20]; 5243 5244 u8 reserved_at_220[0x20]; 5245 5246 u8 rnr_nak_retry_err[0x20]; 5247 5248 u8 reserved_at_260[0x20]; 5249 5250 u8 packet_seq_err[0x20]; 5251 5252 u8 reserved_at_2a0[0x20]; 5253 5254 u8 implied_nak_seq_err[0x20]; 5255 5256 u8 reserved_at_2e0[0x20]; 5257 5258 u8 local_ack_timeout_err[0x20]; 5259 5260 u8 reserved_at_320[0xa0]; 5261 5262 u8 resp_local_length_error[0x20]; 5263 5264 u8 req_local_length_error[0x20]; 5265 5266 u8 resp_local_qp_error[0x20]; 5267 5268 u8 local_operation_error[0x20]; 5269 5270 u8 resp_local_protection[0x20]; 5271 5272 u8 req_local_protection[0x20]; 5273 5274 u8 resp_cqe_error[0x20]; 5275 5276 u8 req_cqe_error[0x20]; 5277 5278 u8 req_mw_binding[0x20]; 5279 5280 u8 req_bad_response[0x20]; 5281 5282 u8 req_remote_invalid_request[0x20]; 5283 5284 u8 resp_remote_invalid_request[0x20]; 5285 5286 u8 req_remote_access_errors[0x20]; 5287 5288 u8 resp_remote_access_errors[0x20]; 5289 5290 u8 req_remote_operation_errors[0x20]; 5291 5292 u8 req_transport_retries_exceeded[0x20]; 5293 5294 u8 cq_overflow[0x20]; 5295 5296 u8 resp_cqe_flush_error[0x20]; 5297 5298 u8 req_cqe_flush_error[0x20]; 5299 5300 u8 reserved_at_620[0x20]; 5301 5302 u8 roce_adp_retrans[0x20]; 5303 5304 u8 roce_adp_retrans_to[0x20]; 5305 5306 u8 roce_slow_restart[0x20]; 5307 5308 u8 roce_slow_restart_cnps[0x20]; 5309 5310 u8 roce_slow_restart_trans[0x20]; 5311 5312 u8 reserved_at_6e0[0x120]; 5313 }; 5314 5315 struct mlx5_ifc_query_q_counter_in_bits { 5316 u8 opcode[0x10]; 5317 u8 reserved_at_10[0x10]; 5318 5319 u8 reserved_at_20[0x10]; 5320 u8 op_mod[0x10]; 5321 5322 u8 reserved_at_40[0x80]; 5323 5324 u8 clear[0x1]; 5325 u8 reserved_at_c1[0x1f]; 5326 5327 u8 reserved_at_e0[0x18]; 5328 u8 counter_set_id[0x8]; 5329 }; 5330 5331 struct mlx5_ifc_query_pages_out_bits { 5332 u8 status[0x8]; 5333 u8 reserved_at_8[0x18]; 5334 5335 u8 syndrome[0x20]; 5336 5337 u8 embedded_cpu_function[0x1]; 5338 u8 reserved_at_41[0xf]; 5339 u8 function_id[0x10]; 5340 5341 u8 num_pages[0x20]; 5342 }; 5343 5344 enum { 5345 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5346 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5347 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5348 }; 5349 5350 struct mlx5_ifc_query_pages_in_bits { 5351 u8 opcode[0x10]; 5352 u8 reserved_at_10[0x10]; 5353 5354 u8 reserved_at_20[0x10]; 5355 u8 op_mod[0x10]; 5356 5357 u8 embedded_cpu_function[0x1]; 5358 u8 reserved_at_41[0xf]; 5359 u8 function_id[0x10]; 5360 5361 u8 reserved_at_60[0x20]; 5362 }; 5363 5364 struct mlx5_ifc_query_nic_vport_context_out_bits { 5365 u8 status[0x8]; 5366 u8 reserved_at_8[0x18]; 5367 5368 u8 syndrome[0x20]; 5369 5370 u8 reserved_at_40[0x40]; 5371 5372 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5373 }; 5374 5375 struct mlx5_ifc_query_nic_vport_context_in_bits { 5376 u8 opcode[0x10]; 5377 u8 reserved_at_10[0x10]; 5378 5379 u8 reserved_at_20[0x10]; 5380 u8 op_mod[0x10]; 5381 5382 u8 other_vport[0x1]; 5383 u8 reserved_at_41[0xf]; 5384 u8 vport_number[0x10]; 5385 5386 u8 reserved_at_60[0x5]; 5387 u8 allowed_list_type[0x3]; 5388 u8 reserved_at_68[0x18]; 5389 }; 5390 5391 struct mlx5_ifc_query_mkey_out_bits { 5392 u8 status[0x8]; 5393 u8 reserved_at_8[0x18]; 5394 5395 u8 syndrome[0x20]; 5396 5397 u8 reserved_at_40[0x40]; 5398 5399 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5400 5401 u8 reserved_at_280[0x600]; 5402 5403 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5404 5405 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5406 }; 5407 5408 struct mlx5_ifc_query_mkey_in_bits { 5409 u8 opcode[0x10]; 5410 u8 reserved_at_10[0x10]; 5411 5412 u8 reserved_at_20[0x10]; 5413 u8 op_mod[0x10]; 5414 5415 u8 reserved_at_40[0x8]; 5416 u8 mkey_index[0x18]; 5417 5418 u8 pg_access[0x1]; 5419 u8 reserved_at_61[0x1f]; 5420 }; 5421 5422 struct mlx5_ifc_query_mad_demux_out_bits { 5423 u8 status[0x8]; 5424 u8 reserved_at_8[0x18]; 5425 5426 u8 syndrome[0x20]; 5427 5428 u8 reserved_at_40[0x40]; 5429 5430 u8 mad_dumux_parameters_block[0x20]; 5431 }; 5432 5433 struct mlx5_ifc_query_mad_demux_in_bits { 5434 u8 opcode[0x10]; 5435 u8 reserved_at_10[0x10]; 5436 5437 u8 reserved_at_20[0x10]; 5438 u8 op_mod[0x10]; 5439 5440 u8 reserved_at_40[0x40]; 5441 }; 5442 5443 struct mlx5_ifc_query_l2_table_entry_out_bits { 5444 u8 status[0x8]; 5445 u8 reserved_at_8[0x18]; 5446 5447 u8 syndrome[0x20]; 5448 5449 u8 reserved_at_40[0xa0]; 5450 5451 u8 reserved_at_e0[0x13]; 5452 u8 vlan_valid[0x1]; 5453 u8 vlan[0xc]; 5454 5455 struct mlx5_ifc_mac_address_layout_bits mac_address; 5456 5457 u8 reserved_at_140[0xc0]; 5458 }; 5459 5460 struct mlx5_ifc_query_l2_table_entry_in_bits { 5461 u8 opcode[0x10]; 5462 u8 reserved_at_10[0x10]; 5463 5464 u8 reserved_at_20[0x10]; 5465 u8 op_mod[0x10]; 5466 5467 u8 reserved_at_40[0x60]; 5468 5469 u8 reserved_at_a0[0x8]; 5470 u8 table_index[0x18]; 5471 5472 u8 reserved_at_c0[0x140]; 5473 }; 5474 5475 struct mlx5_ifc_query_issi_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_at_8[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 reserved_at_40[0x10]; 5482 u8 current_issi[0x10]; 5483 5484 u8 reserved_at_60[0xa0]; 5485 5486 u8 reserved_at_100[76][0x8]; 5487 u8 supported_issi_dw0[0x20]; 5488 }; 5489 5490 struct mlx5_ifc_query_issi_in_bits { 5491 u8 opcode[0x10]; 5492 u8 reserved_at_10[0x10]; 5493 5494 u8 reserved_at_20[0x10]; 5495 u8 op_mod[0x10]; 5496 5497 u8 reserved_at_40[0x40]; 5498 }; 5499 5500 struct mlx5_ifc_set_driver_version_out_bits { 5501 u8 status[0x8]; 5502 u8 reserved_0[0x18]; 5503 5504 u8 syndrome[0x20]; 5505 u8 reserved_1[0x40]; 5506 }; 5507 5508 struct mlx5_ifc_set_driver_version_in_bits { 5509 u8 opcode[0x10]; 5510 u8 reserved_0[0x10]; 5511 5512 u8 reserved_1[0x10]; 5513 u8 op_mod[0x10]; 5514 5515 u8 reserved_2[0x40]; 5516 u8 driver_version[64][0x8]; 5517 }; 5518 5519 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5520 u8 status[0x8]; 5521 u8 reserved_at_8[0x18]; 5522 5523 u8 syndrome[0x20]; 5524 5525 u8 reserved_at_40[0x40]; 5526 5527 struct mlx5_ifc_pkey_bits pkey[]; 5528 }; 5529 5530 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5531 u8 opcode[0x10]; 5532 u8 reserved_at_10[0x10]; 5533 5534 u8 reserved_at_20[0x10]; 5535 u8 op_mod[0x10]; 5536 5537 u8 other_vport[0x1]; 5538 u8 reserved_at_41[0xb]; 5539 u8 port_num[0x4]; 5540 u8 vport_number[0x10]; 5541 5542 u8 reserved_at_60[0x10]; 5543 u8 pkey_index[0x10]; 5544 }; 5545 5546 enum { 5547 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5548 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5549 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5550 }; 5551 5552 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5553 u8 status[0x8]; 5554 u8 reserved_at_8[0x18]; 5555 5556 u8 syndrome[0x20]; 5557 5558 u8 reserved_at_40[0x20]; 5559 5560 u8 gids_num[0x10]; 5561 u8 reserved_at_70[0x10]; 5562 5563 struct mlx5_ifc_array128_auto_bits gid[]; 5564 }; 5565 5566 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5567 u8 opcode[0x10]; 5568 u8 reserved_at_10[0x10]; 5569 5570 u8 reserved_at_20[0x10]; 5571 u8 op_mod[0x10]; 5572 5573 u8 other_vport[0x1]; 5574 u8 reserved_at_41[0xb]; 5575 u8 port_num[0x4]; 5576 u8 vport_number[0x10]; 5577 5578 u8 reserved_at_60[0x10]; 5579 u8 gid_index[0x10]; 5580 }; 5581 5582 struct mlx5_ifc_query_hca_vport_context_out_bits { 5583 u8 status[0x8]; 5584 u8 reserved_at_8[0x18]; 5585 5586 u8 syndrome[0x20]; 5587 5588 u8 reserved_at_40[0x40]; 5589 5590 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5591 }; 5592 5593 struct mlx5_ifc_query_hca_vport_context_in_bits { 5594 u8 opcode[0x10]; 5595 u8 reserved_at_10[0x10]; 5596 5597 u8 reserved_at_20[0x10]; 5598 u8 op_mod[0x10]; 5599 5600 u8 other_vport[0x1]; 5601 u8 reserved_at_41[0xb]; 5602 u8 port_num[0x4]; 5603 u8 vport_number[0x10]; 5604 5605 u8 reserved_at_60[0x20]; 5606 }; 5607 5608 struct mlx5_ifc_query_hca_cap_out_bits { 5609 u8 status[0x8]; 5610 u8 reserved_at_8[0x18]; 5611 5612 u8 syndrome[0x20]; 5613 5614 u8 reserved_at_40[0x40]; 5615 5616 union mlx5_ifc_hca_cap_union_bits capability; 5617 }; 5618 5619 struct mlx5_ifc_query_hca_cap_in_bits { 5620 u8 opcode[0x10]; 5621 u8 reserved_at_10[0x10]; 5622 5623 u8 reserved_at_20[0x10]; 5624 u8 op_mod[0x10]; 5625 5626 u8 other_function[0x1]; 5627 u8 reserved_at_41[0xf]; 5628 u8 function_id[0x10]; 5629 5630 u8 reserved_at_60[0x20]; 5631 }; 5632 5633 struct mlx5_ifc_other_hca_cap_bits { 5634 u8 roce[0x1]; 5635 u8 reserved_at_1[0x27f]; 5636 }; 5637 5638 struct mlx5_ifc_query_other_hca_cap_out_bits { 5639 u8 status[0x8]; 5640 u8 reserved_at_8[0x18]; 5641 5642 u8 syndrome[0x20]; 5643 5644 u8 reserved_at_40[0x40]; 5645 5646 struct mlx5_ifc_other_hca_cap_bits other_capability; 5647 }; 5648 5649 struct mlx5_ifc_query_other_hca_cap_in_bits { 5650 u8 opcode[0x10]; 5651 u8 reserved_at_10[0x10]; 5652 5653 u8 reserved_at_20[0x10]; 5654 u8 op_mod[0x10]; 5655 5656 u8 reserved_at_40[0x10]; 5657 u8 function_id[0x10]; 5658 5659 u8 reserved_at_60[0x20]; 5660 }; 5661 5662 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5663 u8 status[0x8]; 5664 u8 reserved_at_8[0x18]; 5665 5666 u8 syndrome[0x20]; 5667 5668 u8 reserved_at_40[0x40]; 5669 }; 5670 5671 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5672 u8 opcode[0x10]; 5673 u8 reserved_at_10[0x10]; 5674 5675 u8 reserved_at_20[0x10]; 5676 u8 op_mod[0x10]; 5677 5678 u8 reserved_at_40[0x10]; 5679 u8 function_id[0x10]; 5680 u8 field_select[0x20]; 5681 5682 struct mlx5_ifc_other_hca_cap_bits other_capability; 5683 }; 5684 5685 struct mlx5_ifc_flow_table_context_bits { 5686 u8 reformat_en[0x1]; 5687 u8 decap_en[0x1]; 5688 u8 sw_owner[0x1]; 5689 u8 termination_table[0x1]; 5690 u8 table_miss_action[0x4]; 5691 u8 level[0x8]; 5692 u8 reserved_at_10[0x8]; 5693 u8 log_size[0x8]; 5694 5695 u8 reserved_at_20[0x8]; 5696 u8 table_miss_id[0x18]; 5697 5698 u8 reserved_at_40[0x8]; 5699 u8 lag_master_next_table_id[0x18]; 5700 5701 u8 reserved_at_60[0x60]; 5702 5703 u8 sw_owner_icm_root_1[0x40]; 5704 5705 u8 sw_owner_icm_root_0[0x40]; 5706 5707 }; 5708 5709 struct mlx5_ifc_query_flow_table_out_bits { 5710 u8 status[0x8]; 5711 u8 reserved_at_8[0x18]; 5712 5713 u8 syndrome[0x20]; 5714 5715 u8 reserved_at_40[0x80]; 5716 5717 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5718 }; 5719 5720 struct mlx5_ifc_query_flow_table_in_bits { 5721 u8 opcode[0x10]; 5722 u8 reserved_at_10[0x10]; 5723 5724 u8 reserved_at_20[0x10]; 5725 u8 op_mod[0x10]; 5726 5727 u8 reserved_at_40[0x40]; 5728 5729 u8 table_type[0x8]; 5730 u8 reserved_at_88[0x18]; 5731 5732 u8 reserved_at_a0[0x8]; 5733 u8 table_id[0x18]; 5734 5735 u8 reserved_at_c0[0x140]; 5736 }; 5737 5738 struct mlx5_ifc_query_fte_out_bits { 5739 u8 status[0x8]; 5740 u8 reserved_at_8[0x18]; 5741 5742 u8 syndrome[0x20]; 5743 5744 u8 reserved_at_40[0x1c0]; 5745 5746 struct mlx5_ifc_flow_context_bits flow_context; 5747 }; 5748 5749 struct mlx5_ifc_query_fte_in_bits { 5750 u8 opcode[0x10]; 5751 u8 reserved_at_10[0x10]; 5752 5753 u8 reserved_at_20[0x10]; 5754 u8 op_mod[0x10]; 5755 5756 u8 reserved_at_40[0x40]; 5757 5758 u8 table_type[0x8]; 5759 u8 reserved_at_88[0x18]; 5760 5761 u8 reserved_at_a0[0x8]; 5762 u8 table_id[0x18]; 5763 5764 u8 reserved_at_c0[0x40]; 5765 5766 u8 flow_index[0x20]; 5767 5768 u8 reserved_at_120[0xe0]; 5769 }; 5770 5771 struct mlx5_ifc_match_definer_format_0_bits { 5772 u8 reserved_at_0[0x100]; 5773 5774 u8 metadata_reg_c_0[0x20]; 5775 5776 u8 metadata_reg_c_1[0x20]; 5777 5778 u8 outer_dmac_47_16[0x20]; 5779 5780 u8 outer_dmac_15_0[0x10]; 5781 u8 outer_ethertype[0x10]; 5782 5783 u8 reserved_at_180[0x1]; 5784 u8 sx_sniffer[0x1]; 5785 u8 functional_lb[0x1]; 5786 u8 outer_ip_frag[0x1]; 5787 u8 outer_qp_type[0x2]; 5788 u8 outer_encap_type[0x2]; 5789 u8 port_number[0x2]; 5790 u8 outer_l3_type[0x2]; 5791 u8 outer_l4_type[0x2]; 5792 u8 outer_first_vlan_type[0x2]; 5793 u8 outer_first_vlan_prio[0x3]; 5794 u8 outer_first_vlan_cfi[0x1]; 5795 u8 outer_first_vlan_vid[0xc]; 5796 5797 u8 outer_l4_type_ext[0x4]; 5798 u8 reserved_at_1a4[0x2]; 5799 u8 outer_ipsec_layer[0x2]; 5800 u8 outer_l2_type[0x2]; 5801 u8 force_lb[0x1]; 5802 u8 outer_l2_ok[0x1]; 5803 u8 outer_l3_ok[0x1]; 5804 u8 outer_l4_ok[0x1]; 5805 u8 outer_second_vlan_type[0x2]; 5806 u8 outer_second_vlan_prio[0x3]; 5807 u8 outer_second_vlan_cfi[0x1]; 5808 u8 outer_second_vlan_vid[0xc]; 5809 5810 u8 outer_smac_47_16[0x20]; 5811 5812 u8 outer_smac_15_0[0x10]; 5813 u8 inner_ipv4_checksum_ok[0x1]; 5814 u8 inner_l4_checksum_ok[0x1]; 5815 u8 outer_ipv4_checksum_ok[0x1]; 5816 u8 outer_l4_checksum_ok[0x1]; 5817 u8 inner_l3_ok[0x1]; 5818 u8 inner_l4_ok[0x1]; 5819 u8 outer_l3_ok_duplicate[0x1]; 5820 u8 outer_l4_ok_duplicate[0x1]; 5821 u8 outer_tcp_cwr[0x1]; 5822 u8 outer_tcp_ece[0x1]; 5823 u8 outer_tcp_urg[0x1]; 5824 u8 outer_tcp_ack[0x1]; 5825 u8 outer_tcp_psh[0x1]; 5826 u8 outer_tcp_rst[0x1]; 5827 u8 outer_tcp_syn[0x1]; 5828 u8 outer_tcp_fin[0x1]; 5829 }; 5830 5831 struct mlx5_ifc_match_definer_format_22_bits { 5832 u8 reserved_at_0[0x100]; 5833 5834 u8 outer_ip_src_addr[0x20]; 5835 5836 u8 outer_ip_dest_addr[0x20]; 5837 5838 u8 outer_l4_sport[0x10]; 5839 u8 outer_l4_dport[0x10]; 5840 5841 u8 reserved_at_160[0x1]; 5842 u8 sx_sniffer[0x1]; 5843 u8 functional_lb[0x1]; 5844 u8 outer_ip_frag[0x1]; 5845 u8 outer_qp_type[0x2]; 5846 u8 outer_encap_type[0x2]; 5847 u8 port_number[0x2]; 5848 u8 outer_l3_type[0x2]; 5849 u8 outer_l4_type[0x2]; 5850 u8 outer_first_vlan_type[0x2]; 5851 u8 outer_first_vlan_prio[0x3]; 5852 u8 outer_first_vlan_cfi[0x1]; 5853 u8 outer_first_vlan_vid[0xc]; 5854 5855 u8 metadata_reg_c_0[0x20]; 5856 5857 u8 outer_dmac_47_16[0x20]; 5858 5859 u8 outer_smac_47_16[0x20]; 5860 5861 u8 outer_smac_15_0[0x10]; 5862 u8 outer_dmac_15_0[0x10]; 5863 }; 5864 5865 struct mlx5_ifc_match_definer_format_23_bits { 5866 u8 reserved_at_0[0x100]; 5867 5868 u8 inner_ip_src_addr[0x20]; 5869 5870 u8 inner_ip_dest_addr[0x20]; 5871 5872 u8 inner_l4_sport[0x10]; 5873 u8 inner_l4_dport[0x10]; 5874 5875 u8 reserved_at_160[0x1]; 5876 u8 sx_sniffer[0x1]; 5877 u8 functional_lb[0x1]; 5878 u8 inner_ip_frag[0x1]; 5879 u8 inner_qp_type[0x2]; 5880 u8 inner_encap_type[0x2]; 5881 u8 port_number[0x2]; 5882 u8 inner_l3_type[0x2]; 5883 u8 inner_l4_type[0x2]; 5884 u8 inner_first_vlan_type[0x2]; 5885 u8 inner_first_vlan_prio[0x3]; 5886 u8 inner_first_vlan_cfi[0x1]; 5887 u8 inner_first_vlan_vid[0xc]; 5888 5889 u8 tunnel_header_0[0x20]; 5890 5891 u8 inner_dmac_47_16[0x20]; 5892 5893 u8 inner_smac_47_16[0x20]; 5894 5895 u8 inner_smac_15_0[0x10]; 5896 u8 inner_dmac_15_0[0x10]; 5897 }; 5898 5899 struct mlx5_ifc_match_definer_format_29_bits { 5900 u8 reserved_at_0[0xc0]; 5901 5902 u8 outer_ip_dest_addr[0x80]; 5903 5904 u8 outer_ip_src_addr[0x80]; 5905 5906 u8 outer_l4_sport[0x10]; 5907 u8 outer_l4_dport[0x10]; 5908 5909 u8 reserved_at_1e0[0x20]; 5910 }; 5911 5912 struct mlx5_ifc_match_definer_format_30_bits { 5913 u8 reserved_at_0[0xa0]; 5914 5915 u8 outer_ip_dest_addr[0x80]; 5916 5917 u8 outer_ip_src_addr[0x80]; 5918 5919 u8 outer_dmac_47_16[0x20]; 5920 5921 u8 outer_smac_47_16[0x20]; 5922 5923 u8 outer_smac_15_0[0x10]; 5924 u8 outer_dmac_15_0[0x10]; 5925 }; 5926 5927 struct mlx5_ifc_match_definer_format_31_bits { 5928 u8 reserved_at_0[0xc0]; 5929 5930 u8 inner_ip_dest_addr[0x80]; 5931 5932 u8 inner_ip_src_addr[0x80]; 5933 5934 u8 inner_l4_sport[0x10]; 5935 u8 inner_l4_dport[0x10]; 5936 5937 u8 reserved_at_1e0[0x20]; 5938 }; 5939 5940 struct mlx5_ifc_match_definer_format_32_bits { 5941 u8 reserved_at_0[0xa0]; 5942 5943 u8 inner_ip_dest_addr[0x80]; 5944 5945 u8 inner_ip_src_addr[0x80]; 5946 5947 u8 inner_dmac_47_16[0x20]; 5948 5949 u8 inner_smac_47_16[0x20]; 5950 5951 u8 inner_smac_15_0[0x10]; 5952 u8 inner_dmac_15_0[0x10]; 5953 }; 5954 5955 struct mlx5_ifc_match_definer_bits { 5956 u8 modify_field_select[0x40]; 5957 5958 u8 reserved_at_40[0x40]; 5959 5960 u8 reserved_at_80[0x10]; 5961 u8 format_id[0x10]; 5962 5963 u8 reserved_at_a0[0x160]; 5964 5965 u8 match_mask[16][0x20]; 5966 }; 5967 5968 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 5969 u8 opcode[0x10]; 5970 u8 uid[0x10]; 5971 5972 u8 vhca_tunnel_id[0x10]; 5973 u8 obj_type[0x10]; 5974 5975 u8 obj_id[0x20]; 5976 5977 u8 reserved_at_60[0x20]; 5978 }; 5979 5980 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 5981 u8 status[0x8]; 5982 u8 reserved_at_8[0x18]; 5983 5984 u8 syndrome[0x20]; 5985 5986 u8 obj_id[0x20]; 5987 5988 u8 reserved_at_60[0x20]; 5989 }; 5990 5991 struct mlx5_ifc_create_match_definer_in_bits { 5992 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 5993 5994 struct mlx5_ifc_match_definer_bits obj_context; 5995 }; 5996 5997 struct mlx5_ifc_create_match_definer_out_bits { 5998 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 5999 }; 6000 6001 enum { 6002 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6003 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6004 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6005 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6006 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6007 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6008 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6009 }; 6010 6011 struct mlx5_ifc_query_flow_group_out_bits { 6012 u8 status[0x8]; 6013 u8 reserved_at_8[0x18]; 6014 6015 u8 syndrome[0x20]; 6016 6017 u8 reserved_at_40[0xa0]; 6018 6019 u8 start_flow_index[0x20]; 6020 6021 u8 reserved_at_100[0x20]; 6022 6023 u8 end_flow_index[0x20]; 6024 6025 u8 reserved_at_140[0xa0]; 6026 6027 u8 reserved_at_1e0[0x18]; 6028 u8 match_criteria_enable[0x8]; 6029 6030 struct mlx5_ifc_fte_match_param_bits match_criteria; 6031 6032 u8 reserved_at_1200[0xe00]; 6033 }; 6034 6035 struct mlx5_ifc_query_flow_group_in_bits { 6036 u8 opcode[0x10]; 6037 u8 reserved_at_10[0x10]; 6038 6039 u8 reserved_at_20[0x10]; 6040 u8 op_mod[0x10]; 6041 6042 u8 reserved_at_40[0x40]; 6043 6044 u8 table_type[0x8]; 6045 u8 reserved_at_88[0x18]; 6046 6047 u8 reserved_at_a0[0x8]; 6048 u8 table_id[0x18]; 6049 6050 u8 group_id[0x20]; 6051 6052 u8 reserved_at_e0[0x120]; 6053 }; 6054 6055 struct mlx5_ifc_query_flow_counter_out_bits { 6056 u8 status[0x8]; 6057 u8 reserved_at_8[0x18]; 6058 6059 u8 syndrome[0x20]; 6060 6061 u8 reserved_at_40[0x40]; 6062 6063 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6064 }; 6065 6066 struct mlx5_ifc_query_flow_counter_in_bits { 6067 u8 opcode[0x10]; 6068 u8 reserved_at_10[0x10]; 6069 6070 u8 reserved_at_20[0x10]; 6071 u8 op_mod[0x10]; 6072 6073 u8 reserved_at_40[0x80]; 6074 6075 u8 clear[0x1]; 6076 u8 reserved_at_c1[0xf]; 6077 u8 num_of_counters[0x10]; 6078 6079 u8 flow_counter_id[0x20]; 6080 }; 6081 6082 struct mlx5_ifc_query_esw_vport_context_out_bits { 6083 u8 status[0x8]; 6084 u8 reserved_at_8[0x18]; 6085 6086 u8 syndrome[0x20]; 6087 6088 u8 reserved_at_40[0x40]; 6089 6090 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6091 }; 6092 6093 struct mlx5_ifc_query_esw_vport_context_in_bits { 6094 u8 opcode[0x10]; 6095 u8 reserved_at_10[0x10]; 6096 6097 u8 reserved_at_20[0x10]; 6098 u8 op_mod[0x10]; 6099 6100 u8 other_vport[0x1]; 6101 u8 reserved_at_41[0xf]; 6102 u8 vport_number[0x10]; 6103 6104 u8 reserved_at_60[0x20]; 6105 }; 6106 6107 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6108 u8 status[0x8]; 6109 u8 reserved_at_8[0x18]; 6110 6111 u8 syndrome[0x20]; 6112 6113 u8 reserved_at_40[0x40]; 6114 }; 6115 6116 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6117 u8 reserved_at_0[0x1b]; 6118 u8 fdb_to_vport_reg_c_id[0x1]; 6119 u8 vport_cvlan_insert[0x1]; 6120 u8 vport_svlan_insert[0x1]; 6121 u8 vport_cvlan_strip[0x1]; 6122 u8 vport_svlan_strip[0x1]; 6123 }; 6124 6125 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6126 u8 opcode[0x10]; 6127 u8 reserved_at_10[0x10]; 6128 6129 u8 reserved_at_20[0x10]; 6130 u8 op_mod[0x10]; 6131 6132 u8 other_vport[0x1]; 6133 u8 reserved_at_41[0xf]; 6134 u8 vport_number[0x10]; 6135 6136 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6137 6138 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6139 }; 6140 6141 struct mlx5_ifc_query_eq_out_bits { 6142 u8 status[0x8]; 6143 u8 reserved_at_8[0x18]; 6144 6145 u8 syndrome[0x20]; 6146 6147 u8 reserved_at_40[0x40]; 6148 6149 struct mlx5_ifc_eqc_bits eq_context_entry; 6150 6151 u8 reserved_at_280[0x40]; 6152 6153 u8 event_bitmask[0x40]; 6154 6155 u8 reserved_at_300[0x580]; 6156 6157 u8 pas[][0x40]; 6158 }; 6159 6160 struct mlx5_ifc_query_eq_in_bits { 6161 u8 opcode[0x10]; 6162 u8 reserved_at_10[0x10]; 6163 6164 u8 reserved_at_20[0x10]; 6165 u8 op_mod[0x10]; 6166 6167 u8 reserved_at_40[0x18]; 6168 u8 eq_number[0x8]; 6169 6170 u8 reserved_at_60[0x20]; 6171 }; 6172 6173 struct mlx5_ifc_packet_reformat_context_in_bits { 6174 u8 reformat_type[0x8]; 6175 u8 reserved_at_8[0x4]; 6176 u8 reformat_param_0[0x4]; 6177 u8 reserved_at_10[0x6]; 6178 u8 reformat_data_size[0xa]; 6179 6180 u8 reformat_param_1[0x8]; 6181 u8 reserved_at_28[0x8]; 6182 u8 reformat_data[2][0x8]; 6183 6184 u8 more_reformat_data[][0x8]; 6185 }; 6186 6187 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6188 u8 status[0x8]; 6189 u8 reserved_at_8[0x18]; 6190 6191 u8 syndrome[0x20]; 6192 6193 u8 reserved_at_40[0xa0]; 6194 6195 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6196 }; 6197 6198 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6199 u8 opcode[0x10]; 6200 u8 reserved_at_10[0x10]; 6201 6202 u8 reserved_at_20[0x10]; 6203 u8 op_mod[0x10]; 6204 6205 u8 packet_reformat_id[0x20]; 6206 6207 u8 reserved_at_60[0xa0]; 6208 }; 6209 6210 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6211 u8 status[0x8]; 6212 u8 reserved_at_8[0x18]; 6213 6214 u8 syndrome[0x20]; 6215 6216 u8 packet_reformat_id[0x20]; 6217 6218 u8 reserved_at_60[0x20]; 6219 }; 6220 6221 enum { 6222 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6223 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6224 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6225 }; 6226 6227 enum mlx5_reformat_ctx_type { 6228 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6229 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6230 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6231 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6232 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6233 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6234 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6235 }; 6236 6237 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6238 u8 opcode[0x10]; 6239 u8 reserved_at_10[0x10]; 6240 6241 u8 reserved_at_20[0x10]; 6242 u8 op_mod[0x10]; 6243 6244 u8 reserved_at_40[0xa0]; 6245 6246 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6247 }; 6248 6249 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6250 u8 status[0x8]; 6251 u8 reserved_at_8[0x18]; 6252 6253 u8 syndrome[0x20]; 6254 6255 u8 reserved_at_40[0x40]; 6256 }; 6257 6258 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6259 u8 opcode[0x10]; 6260 u8 reserved_at_10[0x10]; 6261 6262 u8 reserved_20[0x10]; 6263 u8 op_mod[0x10]; 6264 6265 u8 packet_reformat_id[0x20]; 6266 6267 u8 reserved_60[0x20]; 6268 }; 6269 6270 struct mlx5_ifc_set_action_in_bits { 6271 u8 action_type[0x4]; 6272 u8 field[0xc]; 6273 u8 reserved_at_10[0x3]; 6274 u8 offset[0x5]; 6275 u8 reserved_at_18[0x3]; 6276 u8 length[0x5]; 6277 6278 u8 data[0x20]; 6279 }; 6280 6281 struct mlx5_ifc_add_action_in_bits { 6282 u8 action_type[0x4]; 6283 u8 field[0xc]; 6284 u8 reserved_at_10[0x10]; 6285 6286 u8 data[0x20]; 6287 }; 6288 6289 struct mlx5_ifc_copy_action_in_bits { 6290 u8 action_type[0x4]; 6291 u8 src_field[0xc]; 6292 u8 reserved_at_10[0x3]; 6293 u8 src_offset[0x5]; 6294 u8 reserved_at_18[0x3]; 6295 u8 length[0x5]; 6296 6297 u8 reserved_at_20[0x4]; 6298 u8 dst_field[0xc]; 6299 u8 reserved_at_30[0x3]; 6300 u8 dst_offset[0x5]; 6301 u8 reserved_at_38[0x8]; 6302 }; 6303 6304 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6305 struct mlx5_ifc_set_action_in_bits set_action_in; 6306 struct mlx5_ifc_add_action_in_bits add_action_in; 6307 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6308 u8 reserved_at_0[0x40]; 6309 }; 6310 6311 enum { 6312 MLX5_ACTION_TYPE_SET = 0x1, 6313 MLX5_ACTION_TYPE_ADD = 0x2, 6314 MLX5_ACTION_TYPE_COPY = 0x3, 6315 }; 6316 6317 enum { 6318 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6319 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6320 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6321 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6322 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6323 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6324 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6325 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6326 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6327 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6328 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6329 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6330 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6331 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6332 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6333 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6334 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6335 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6336 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6337 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6338 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6339 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6340 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6341 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6342 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6343 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6344 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6345 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6346 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6347 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6348 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6349 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6350 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6351 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6352 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6353 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6354 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6355 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6356 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6357 }; 6358 6359 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6360 u8 status[0x8]; 6361 u8 reserved_at_8[0x18]; 6362 6363 u8 syndrome[0x20]; 6364 6365 u8 modify_header_id[0x20]; 6366 6367 u8 reserved_at_60[0x20]; 6368 }; 6369 6370 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6371 u8 opcode[0x10]; 6372 u8 reserved_at_10[0x10]; 6373 6374 u8 reserved_at_20[0x10]; 6375 u8 op_mod[0x10]; 6376 6377 u8 reserved_at_40[0x20]; 6378 6379 u8 table_type[0x8]; 6380 u8 reserved_at_68[0x10]; 6381 u8 num_of_actions[0x8]; 6382 6383 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6384 }; 6385 6386 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6387 u8 status[0x8]; 6388 u8 reserved_at_8[0x18]; 6389 6390 u8 syndrome[0x20]; 6391 6392 u8 reserved_at_40[0x40]; 6393 }; 6394 6395 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6396 u8 opcode[0x10]; 6397 u8 reserved_at_10[0x10]; 6398 6399 u8 reserved_at_20[0x10]; 6400 u8 op_mod[0x10]; 6401 6402 u8 modify_header_id[0x20]; 6403 6404 u8 reserved_at_60[0x20]; 6405 }; 6406 6407 struct mlx5_ifc_query_modify_header_context_in_bits { 6408 u8 opcode[0x10]; 6409 u8 uid[0x10]; 6410 6411 u8 reserved_at_20[0x10]; 6412 u8 op_mod[0x10]; 6413 6414 u8 modify_header_id[0x20]; 6415 6416 u8 reserved_at_60[0xa0]; 6417 }; 6418 6419 struct mlx5_ifc_query_dct_out_bits { 6420 u8 status[0x8]; 6421 u8 reserved_at_8[0x18]; 6422 6423 u8 syndrome[0x20]; 6424 6425 u8 reserved_at_40[0x40]; 6426 6427 struct mlx5_ifc_dctc_bits dct_context_entry; 6428 6429 u8 reserved_at_280[0x180]; 6430 }; 6431 6432 struct mlx5_ifc_query_dct_in_bits { 6433 u8 opcode[0x10]; 6434 u8 reserved_at_10[0x10]; 6435 6436 u8 reserved_at_20[0x10]; 6437 u8 op_mod[0x10]; 6438 6439 u8 reserved_at_40[0x8]; 6440 u8 dctn[0x18]; 6441 6442 u8 reserved_at_60[0x20]; 6443 }; 6444 6445 struct mlx5_ifc_query_cq_out_bits { 6446 u8 status[0x8]; 6447 u8 reserved_at_8[0x18]; 6448 6449 u8 syndrome[0x20]; 6450 6451 u8 reserved_at_40[0x40]; 6452 6453 struct mlx5_ifc_cqc_bits cq_context; 6454 6455 u8 reserved_at_280[0x600]; 6456 6457 u8 pas[][0x40]; 6458 }; 6459 6460 struct mlx5_ifc_query_cq_in_bits { 6461 u8 opcode[0x10]; 6462 u8 reserved_at_10[0x10]; 6463 6464 u8 reserved_at_20[0x10]; 6465 u8 op_mod[0x10]; 6466 6467 u8 reserved_at_40[0x8]; 6468 u8 cqn[0x18]; 6469 6470 u8 reserved_at_60[0x20]; 6471 }; 6472 6473 struct mlx5_ifc_query_cong_status_out_bits { 6474 u8 status[0x8]; 6475 u8 reserved_at_8[0x18]; 6476 6477 u8 syndrome[0x20]; 6478 6479 u8 reserved_at_40[0x20]; 6480 6481 u8 enable[0x1]; 6482 u8 tag_enable[0x1]; 6483 u8 reserved_at_62[0x1e]; 6484 }; 6485 6486 struct mlx5_ifc_query_cong_status_in_bits { 6487 u8 opcode[0x10]; 6488 u8 reserved_at_10[0x10]; 6489 6490 u8 reserved_at_20[0x10]; 6491 u8 op_mod[0x10]; 6492 6493 u8 reserved_at_40[0x18]; 6494 u8 priority[0x4]; 6495 u8 cong_protocol[0x4]; 6496 6497 u8 reserved_at_60[0x20]; 6498 }; 6499 6500 struct mlx5_ifc_query_cong_statistics_out_bits { 6501 u8 status[0x8]; 6502 u8 reserved_at_8[0x18]; 6503 6504 u8 syndrome[0x20]; 6505 6506 u8 reserved_at_40[0x40]; 6507 6508 u8 rp_cur_flows[0x20]; 6509 6510 u8 sum_flows[0x20]; 6511 6512 u8 rp_cnp_ignored_high[0x20]; 6513 6514 u8 rp_cnp_ignored_low[0x20]; 6515 6516 u8 rp_cnp_handled_high[0x20]; 6517 6518 u8 rp_cnp_handled_low[0x20]; 6519 6520 u8 reserved_at_140[0x100]; 6521 6522 u8 time_stamp_high[0x20]; 6523 6524 u8 time_stamp_low[0x20]; 6525 6526 u8 accumulators_period[0x20]; 6527 6528 u8 np_ecn_marked_roce_packets_high[0x20]; 6529 6530 u8 np_ecn_marked_roce_packets_low[0x20]; 6531 6532 u8 np_cnp_sent_high[0x20]; 6533 6534 u8 np_cnp_sent_low[0x20]; 6535 6536 u8 reserved_at_320[0x560]; 6537 }; 6538 6539 struct mlx5_ifc_query_cong_statistics_in_bits { 6540 u8 opcode[0x10]; 6541 u8 reserved_at_10[0x10]; 6542 6543 u8 reserved_at_20[0x10]; 6544 u8 op_mod[0x10]; 6545 6546 u8 clear[0x1]; 6547 u8 reserved_at_41[0x1f]; 6548 6549 u8 reserved_at_60[0x20]; 6550 }; 6551 6552 struct mlx5_ifc_query_cong_params_out_bits { 6553 u8 status[0x8]; 6554 u8 reserved_at_8[0x18]; 6555 6556 u8 syndrome[0x20]; 6557 6558 u8 reserved_at_40[0x40]; 6559 6560 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6561 }; 6562 6563 struct mlx5_ifc_query_cong_params_in_bits { 6564 u8 opcode[0x10]; 6565 u8 reserved_at_10[0x10]; 6566 6567 u8 reserved_at_20[0x10]; 6568 u8 op_mod[0x10]; 6569 6570 u8 reserved_at_40[0x1c]; 6571 u8 cong_protocol[0x4]; 6572 6573 u8 reserved_at_60[0x20]; 6574 }; 6575 6576 struct mlx5_ifc_query_adapter_out_bits { 6577 u8 status[0x8]; 6578 u8 reserved_at_8[0x18]; 6579 6580 u8 syndrome[0x20]; 6581 6582 u8 reserved_at_40[0x40]; 6583 6584 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6585 }; 6586 6587 struct mlx5_ifc_query_adapter_in_bits { 6588 u8 opcode[0x10]; 6589 u8 reserved_at_10[0x10]; 6590 6591 u8 reserved_at_20[0x10]; 6592 u8 op_mod[0x10]; 6593 6594 u8 reserved_at_40[0x40]; 6595 }; 6596 6597 struct mlx5_ifc_qp_2rst_out_bits { 6598 u8 status[0x8]; 6599 u8 reserved_at_8[0x18]; 6600 6601 u8 syndrome[0x20]; 6602 6603 u8 reserved_at_40[0x40]; 6604 }; 6605 6606 struct mlx5_ifc_qp_2rst_in_bits { 6607 u8 opcode[0x10]; 6608 u8 uid[0x10]; 6609 6610 u8 reserved_at_20[0x10]; 6611 u8 op_mod[0x10]; 6612 6613 u8 reserved_at_40[0x8]; 6614 u8 qpn[0x18]; 6615 6616 u8 reserved_at_60[0x20]; 6617 }; 6618 6619 struct mlx5_ifc_qp_2err_out_bits { 6620 u8 status[0x8]; 6621 u8 reserved_at_8[0x18]; 6622 6623 u8 syndrome[0x20]; 6624 6625 u8 reserved_at_40[0x40]; 6626 }; 6627 6628 struct mlx5_ifc_qp_2err_in_bits { 6629 u8 opcode[0x10]; 6630 u8 uid[0x10]; 6631 6632 u8 reserved_at_20[0x10]; 6633 u8 op_mod[0x10]; 6634 6635 u8 reserved_at_40[0x8]; 6636 u8 qpn[0x18]; 6637 6638 u8 reserved_at_60[0x20]; 6639 }; 6640 6641 struct mlx5_ifc_page_fault_resume_out_bits { 6642 u8 status[0x8]; 6643 u8 reserved_at_8[0x18]; 6644 6645 u8 syndrome[0x20]; 6646 6647 u8 reserved_at_40[0x40]; 6648 }; 6649 6650 struct mlx5_ifc_page_fault_resume_in_bits { 6651 u8 opcode[0x10]; 6652 u8 reserved_at_10[0x10]; 6653 6654 u8 reserved_at_20[0x10]; 6655 u8 op_mod[0x10]; 6656 6657 u8 error[0x1]; 6658 u8 reserved_at_41[0x4]; 6659 u8 page_fault_type[0x3]; 6660 u8 wq_number[0x18]; 6661 6662 u8 reserved_at_60[0x8]; 6663 u8 token[0x18]; 6664 }; 6665 6666 struct mlx5_ifc_nop_out_bits { 6667 u8 status[0x8]; 6668 u8 reserved_at_8[0x18]; 6669 6670 u8 syndrome[0x20]; 6671 6672 u8 reserved_at_40[0x40]; 6673 }; 6674 6675 struct mlx5_ifc_nop_in_bits { 6676 u8 opcode[0x10]; 6677 u8 reserved_at_10[0x10]; 6678 6679 u8 reserved_at_20[0x10]; 6680 u8 op_mod[0x10]; 6681 6682 u8 reserved_at_40[0x40]; 6683 }; 6684 6685 struct mlx5_ifc_modify_vport_state_out_bits { 6686 u8 status[0x8]; 6687 u8 reserved_at_8[0x18]; 6688 6689 u8 syndrome[0x20]; 6690 6691 u8 reserved_at_40[0x40]; 6692 }; 6693 6694 struct mlx5_ifc_modify_vport_state_in_bits { 6695 u8 opcode[0x10]; 6696 u8 reserved_at_10[0x10]; 6697 6698 u8 reserved_at_20[0x10]; 6699 u8 op_mod[0x10]; 6700 6701 u8 other_vport[0x1]; 6702 u8 reserved_at_41[0xf]; 6703 u8 vport_number[0x10]; 6704 6705 u8 reserved_at_60[0x18]; 6706 u8 admin_state[0x4]; 6707 u8 reserved_at_7c[0x4]; 6708 }; 6709 6710 struct mlx5_ifc_modify_tis_out_bits { 6711 u8 status[0x8]; 6712 u8 reserved_at_8[0x18]; 6713 6714 u8 syndrome[0x20]; 6715 6716 u8 reserved_at_40[0x40]; 6717 }; 6718 6719 struct mlx5_ifc_modify_tis_bitmask_bits { 6720 u8 reserved_at_0[0x20]; 6721 6722 u8 reserved_at_20[0x1d]; 6723 u8 lag_tx_port_affinity[0x1]; 6724 u8 strict_lag_tx_port_affinity[0x1]; 6725 u8 prio[0x1]; 6726 }; 6727 6728 struct mlx5_ifc_modify_tis_in_bits { 6729 u8 opcode[0x10]; 6730 u8 uid[0x10]; 6731 6732 u8 reserved_at_20[0x10]; 6733 u8 op_mod[0x10]; 6734 6735 u8 reserved_at_40[0x8]; 6736 u8 tisn[0x18]; 6737 6738 u8 reserved_at_60[0x20]; 6739 6740 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6741 6742 u8 reserved_at_c0[0x40]; 6743 6744 struct mlx5_ifc_tisc_bits ctx; 6745 }; 6746 6747 struct mlx5_ifc_modify_tir_bitmask_bits { 6748 u8 reserved_at_0[0x20]; 6749 6750 u8 reserved_at_20[0x1b]; 6751 u8 self_lb_en[0x1]; 6752 u8 reserved_at_3c[0x1]; 6753 u8 hash[0x1]; 6754 u8 reserved_at_3e[0x1]; 6755 u8 packet_merge[0x1]; 6756 }; 6757 6758 struct mlx5_ifc_modify_tir_out_bits { 6759 u8 status[0x8]; 6760 u8 reserved_at_8[0x18]; 6761 6762 u8 syndrome[0x20]; 6763 6764 u8 reserved_at_40[0x40]; 6765 }; 6766 6767 struct mlx5_ifc_modify_tir_in_bits { 6768 u8 opcode[0x10]; 6769 u8 uid[0x10]; 6770 6771 u8 reserved_at_20[0x10]; 6772 u8 op_mod[0x10]; 6773 6774 u8 reserved_at_40[0x8]; 6775 u8 tirn[0x18]; 6776 6777 u8 reserved_at_60[0x20]; 6778 6779 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6780 6781 u8 reserved_at_c0[0x40]; 6782 6783 struct mlx5_ifc_tirc_bits ctx; 6784 }; 6785 6786 struct mlx5_ifc_modify_sq_out_bits { 6787 u8 status[0x8]; 6788 u8 reserved_at_8[0x18]; 6789 6790 u8 syndrome[0x20]; 6791 6792 u8 reserved_at_40[0x40]; 6793 }; 6794 6795 struct mlx5_ifc_modify_sq_in_bits { 6796 u8 opcode[0x10]; 6797 u8 uid[0x10]; 6798 6799 u8 reserved_at_20[0x10]; 6800 u8 op_mod[0x10]; 6801 6802 u8 sq_state[0x4]; 6803 u8 reserved_at_44[0x4]; 6804 u8 sqn[0x18]; 6805 6806 u8 reserved_at_60[0x20]; 6807 6808 u8 modify_bitmask[0x40]; 6809 6810 u8 reserved_at_c0[0x40]; 6811 6812 struct mlx5_ifc_sqc_bits ctx; 6813 }; 6814 6815 struct mlx5_ifc_modify_scheduling_element_out_bits { 6816 u8 status[0x8]; 6817 u8 reserved_at_8[0x18]; 6818 6819 u8 syndrome[0x20]; 6820 6821 u8 reserved_at_40[0x1c0]; 6822 }; 6823 6824 enum { 6825 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6826 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6827 }; 6828 6829 struct mlx5_ifc_modify_scheduling_element_in_bits { 6830 u8 opcode[0x10]; 6831 u8 reserved_at_10[0x10]; 6832 6833 u8 reserved_at_20[0x10]; 6834 u8 op_mod[0x10]; 6835 6836 u8 scheduling_hierarchy[0x8]; 6837 u8 reserved_at_48[0x18]; 6838 6839 u8 scheduling_element_id[0x20]; 6840 6841 u8 reserved_at_80[0x20]; 6842 6843 u8 modify_bitmask[0x20]; 6844 6845 u8 reserved_at_c0[0x40]; 6846 6847 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6848 6849 u8 reserved_at_300[0x100]; 6850 }; 6851 6852 struct mlx5_ifc_modify_rqt_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_at_8[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_at_40[0x40]; 6859 }; 6860 6861 struct mlx5_ifc_rqt_bitmask_bits { 6862 u8 reserved_at_0[0x20]; 6863 6864 u8 reserved_at_20[0x1f]; 6865 u8 rqn_list[0x1]; 6866 }; 6867 6868 struct mlx5_ifc_modify_rqt_in_bits { 6869 u8 opcode[0x10]; 6870 u8 uid[0x10]; 6871 6872 u8 reserved_at_20[0x10]; 6873 u8 op_mod[0x10]; 6874 6875 u8 reserved_at_40[0x8]; 6876 u8 rqtn[0x18]; 6877 6878 u8 reserved_at_60[0x20]; 6879 6880 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6881 6882 u8 reserved_at_c0[0x40]; 6883 6884 struct mlx5_ifc_rqtc_bits ctx; 6885 }; 6886 6887 struct mlx5_ifc_modify_rq_out_bits { 6888 u8 status[0x8]; 6889 u8 reserved_at_8[0x18]; 6890 6891 u8 syndrome[0x20]; 6892 6893 u8 reserved_at_40[0x40]; 6894 }; 6895 6896 enum { 6897 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6898 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6899 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6900 }; 6901 6902 struct mlx5_ifc_modify_rq_in_bits { 6903 u8 opcode[0x10]; 6904 u8 uid[0x10]; 6905 6906 u8 reserved_at_20[0x10]; 6907 u8 op_mod[0x10]; 6908 6909 u8 rq_state[0x4]; 6910 u8 reserved_at_44[0x4]; 6911 u8 rqn[0x18]; 6912 6913 u8 reserved_at_60[0x20]; 6914 6915 u8 modify_bitmask[0x40]; 6916 6917 u8 reserved_at_c0[0x40]; 6918 6919 struct mlx5_ifc_rqc_bits ctx; 6920 }; 6921 6922 struct mlx5_ifc_modify_rmp_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x40]; 6929 }; 6930 6931 struct mlx5_ifc_rmp_bitmask_bits { 6932 u8 reserved_at_0[0x20]; 6933 6934 u8 reserved_at_20[0x1f]; 6935 u8 lwm[0x1]; 6936 }; 6937 6938 struct mlx5_ifc_modify_rmp_in_bits { 6939 u8 opcode[0x10]; 6940 u8 uid[0x10]; 6941 6942 u8 reserved_at_20[0x10]; 6943 u8 op_mod[0x10]; 6944 6945 u8 rmp_state[0x4]; 6946 u8 reserved_at_44[0x4]; 6947 u8 rmpn[0x18]; 6948 6949 u8 reserved_at_60[0x20]; 6950 6951 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6952 6953 u8 reserved_at_c0[0x40]; 6954 6955 struct mlx5_ifc_rmpc_bits ctx; 6956 }; 6957 6958 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6959 u8 status[0x8]; 6960 u8 reserved_at_8[0x18]; 6961 6962 u8 syndrome[0x20]; 6963 6964 u8 reserved_at_40[0x40]; 6965 }; 6966 6967 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6968 u8 reserved_at_0[0x12]; 6969 u8 affiliation[0x1]; 6970 u8 reserved_at_13[0x1]; 6971 u8 disable_uc_local_lb[0x1]; 6972 u8 disable_mc_local_lb[0x1]; 6973 u8 node_guid[0x1]; 6974 u8 port_guid[0x1]; 6975 u8 min_inline[0x1]; 6976 u8 mtu[0x1]; 6977 u8 change_event[0x1]; 6978 u8 promisc[0x1]; 6979 u8 permanent_address[0x1]; 6980 u8 addresses_list[0x1]; 6981 u8 roce_en[0x1]; 6982 u8 reserved_at_1f[0x1]; 6983 }; 6984 6985 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6986 u8 opcode[0x10]; 6987 u8 reserved_at_10[0x10]; 6988 6989 u8 reserved_at_20[0x10]; 6990 u8 op_mod[0x10]; 6991 6992 u8 other_vport[0x1]; 6993 u8 reserved_at_41[0xf]; 6994 u8 vport_number[0x10]; 6995 6996 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6997 6998 u8 reserved_at_80[0x780]; 6999 7000 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7001 }; 7002 7003 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7004 u8 status[0x8]; 7005 u8 reserved_at_8[0x18]; 7006 7007 u8 syndrome[0x20]; 7008 7009 u8 reserved_at_40[0x40]; 7010 }; 7011 7012 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7013 u8 opcode[0x10]; 7014 u8 reserved_at_10[0x10]; 7015 7016 u8 reserved_at_20[0x10]; 7017 u8 op_mod[0x10]; 7018 7019 u8 other_vport[0x1]; 7020 u8 reserved_at_41[0xb]; 7021 u8 port_num[0x4]; 7022 u8 vport_number[0x10]; 7023 7024 u8 reserved_at_60[0x20]; 7025 7026 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7027 }; 7028 7029 struct mlx5_ifc_modify_cq_out_bits { 7030 u8 status[0x8]; 7031 u8 reserved_at_8[0x18]; 7032 7033 u8 syndrome[0x20]; 7034 7035 u8 reserved_at_40[0x40]; 7036 }; 7037 7038 enum { 7039 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7040 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7041 }; 7042 7043 struct mlx5_ifc_modify_cq_in_bits { 7044 u8 opcode[0x10]; 7045 u8 uid[0x10]; 7046 7047 u8 reserved_at_20[0x10]; 7048 u8 op_mod[0x10]; 7049 7050 u8 reserved_at_40[0x8]; 7051 u8 cqn[0x18]; 7052 7053 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7054 7055 struct mlx5_ifc_cqc_bits cq_context; 7056 7057 u8 reserved_at_280[0x60]; 7058 7059 u8 cq_umem_valid[0x1]; 7060 u8 reserved_at_2e1[0x1f]; 7061 7062 u8 reserved_at_300[0x580]; 7063 7064 u8 pas[][0x40]; 7065 }; 7066 7067 struct mlx5_ifc_modify_cong_status_out_bits { 7068 u8 status[0x8]; 7069 u8 reserved_at_8[0x18]; 7070 7071 u8 syndrome[0x20]; 7072 7073 u8 reserved_at_40[0x40]; 7074 }; 7075 7076 struct mlx5_ifc_modify_cong_status_in_bits { 7077 u8 opcode[0x10]; 7078 u8 reserved_at_10[0x10]; 7079 7080 u8 reserved_at_20[0x10]; 7081 u8 op_mod[0x10]; 7082 7083 u8 reserved_at_40[0x18]; 7084 u8 priority[0x4]; 7085 u8 cong_protocol[0x4]; 7086 7087 u8 enable[0x1]; 7088 u8 tag_enable[0x1]; 7089 u8 reserved_at_62[0x1e]; 7090 }; 7091 7092 struct mlx5_ifc_modify_cong_params_out_bits { 7093 u8 status[0x8]; 7094 u8 reserved_at_8[0x18]; 7095 7096 u8 syndrome[0x20]; 7097 7098 u8 reserved_at_40[0x40]; 7099 }; 7100 7101 struct mlx5_ifc_modify_cong_params_in_bits { 7102 u8 opcode[0x10]; 7103 u8 reserved_at_10[0x10]; 7104 7105 u8 reserved_at_20[0x10]; 7106 u8 op_mod[0x10]; 7107 7108 u8 reserved_at_40[0x1c]; 7109 u8 cong_protocol[0x4]; 7110 7111 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7112 7113 u8 reserved_at_80[0x80]; 7114 7115 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7116 }; 7117 7118 struct mlx5_ifc_manage_pages_out_bits { 7119 u8 status[0x8]; 7120 u8 reserved_at_8[0x18]; 7121 7122 u8 syndrome[0x20]; 7123 7124 u8 output_num_entries[0x20]; 7125 7126 u8 reserved_at_60[0x20]; 7127 7128 u8 pas[][0x40]; 7129 }; 7130 7131 enum { 7132 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7133 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7134 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7135 }; 7136 7137 struct mlx5_ifc_manage_pages_in_bits { 7138 u8 opcode[0x10]; 7139 u8 reserved_at_10[0x10]; 7140 7141 u8 reserved_at_20[0x10]; 7142 u8 op_mod[0x10]; 7143 7144 u8 embedded_cpu_function[0x1]; 7145 u8 reserved_at_41[0xf]; 7146 u8 function_id[0x10]; 7147 7148 u8 input_num_entries[0x20]; 7149 7150 u8 pas[][0x40]; 7151 }; 7152 7153 struct mlx5_ifc_mad_ifc_out_bits { 7154 u8 status[0x8]; 7155 u8 reserved_at_8[0x18]; 7156 7157 u8 syndrome[0x20]; 7158 7159 u8 reserved_at_40[0x40]; 7160 7161 u8 response_mad_packet[256][0x8]; 7162 }; 7163 7164 struct mlx5_ifc_mad_ifc_in_bits { 7165 u8 opcode[0x10]; 7166 u8 reserved_at_10[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 remote_lid[0x10]; 7172 u8 reserved_at_50[0x8]; 7173 u8 port[0x8]; 7174 7175 u8 reserved_at_60[0x20]; 7176 7177 u8 mad[256][0x8]; 7178 }; 7179 7180 struct mlx5_ifc_init_hca_out_bits { 7181 u8 status[0x8]; 7182 u8 reserved_at_8[0x18]; 7183 7184 u8 syndrome[0x20]; 7185 7186 u8 reserved_at_40[0x40]; 7187 }; 7188 7189 struct mlx5_ifc_init_hca_in_bits { 7190 u8 opcode[0x10]; 7191 u8 reserved_at_10[0x10]; 7192 7193 u8 reserved_at_20[0x10]; 7194 u8 op_mod[0x10]; 7195 7196 u8 reserved_at_40[0x40]; 7197 u8 sw_owner_id[4][0x20]; 7198 }; 7199 7200 struct mlx5_ifc_init2rtr_qp_out_bits { 7201 u8 status[0x8]; 7202 u8 reserved_at_8[0x18]; 7203 7204 u8 syndrome[0x20]; 7205 7206 u8 reserved_at_40[0x20]; 7207 u8 ece[0x20]; 7208 }; 7209 7210 struct mlx5_ifc_init2rtr_qp_in_bits { 7211 u8 opcode[0x10]; 7212 u8 uid[0x10]; 7213 7214 u8 reserved_at_20[0x10]; 7215 u8 op_mod[0x10]; 7216 7217 u8 reserved_at_40[0x8]; 7218 u8 qpn[0x18]; 7219 7220 u8 reserved_at_60[0x20]; 7221 7222 u8 opt_param_mask[0x20]; 7223 7224 u8 ece[0x20]; 7225 7226 struct mlx5_ifc_qpc_bits qpc; 7227 7228 u8 reserved_at_800[0x80]; 7229 }; 7230 7231 struct mlx5_ifc_init2init_qp_out_bits { 7232 u8 status[0x8]; 7233 u8 reserved_at_8[0x18]; 7234 7235 u8 syndrome[0x20]; 7236 7237 u8 reserved_at_40[0x20]; 7238 u8 ece[0x20]; 7239 }; 7240 7241 struct mlx5_ifc_init2init_qp_in_bits { 7242 u8 opcode[0x10]; 7243 u8 uid[0x10]; 7244 7245 u8 reserved_at_20[0x10]; 7246 u8 op_mod[0x10]; 7247 7248 u8 reserved_at_40[0x8]; 7249 u8 qpn[0x18]; 7250 7251 u8 reserved_at_60[0x20]; 7252 7253 u8 opt_param_mask[0x20]; 7254 7255 u8 ece[0x20]; 7256 7257 struct mlx5_ifc_qpc_bits qpc; 7258 7259 u8 reserved_at_800[0x80]; 7260 }; 7261 7262 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_at_8[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_at_40[0x40]; 7269 7270 u8 packet_headers_log[128][0x8]; 7271 7272 u8 packet_syndrome[64][0x8]; 7273 }; 7274 7275 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7276 u8 opcode[0x10]; 7277 u8 reserved_at_10[0x10]; 7278 7279 u8 reserved_at_20[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 reserved_at_40[0x40]; 7283 }; 7284 7285 struct mlx5_ifc_gen_eqe_in_bits { 7286 u8 opcode[0x10]; 7287 u8 reserved_at_10[0x10]; 7288 7289 u8 reserved_at_20[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 reserved_at_40[0x18]; 7293 u8 eq_number[0x8]; 7294 7295 u8 reserved_at_60[0x20]; 7296 7297 u8 eqe[64][0x8]; 7298 }; 7299 7300 struct mlx5_ifc_gen_eq_out_bits { 7301 u8 status[0x8]; 7302 u8 reserved_at_8[0x18]; 7303 7304 u8 syndrome[0x20]; 7305 7306 u8 reserved_at_40[0x40]; 7307 }; 7308 7309 struct mlx5_ifc_enable_hca_out_bits { 7310 u8 status[0x8]; 7311 u8 reserved_at_8[0x18]; 7312 7313 u8 syndrome[0x20]; 7314 7315 u8 reserved_at_40[0x20]; 7316 }; 7317 7318 struct mlx5_ifc_enable_hca_in_bits { 7319 u8 opcode[0x10]; 7320 u8 reserved_at_10[0x10]; 7321 7322 u8 reserved_at_20[0x10]; 7323 u8 op_mod[0x10]; 7324 7325 u8 embedded_cpu_function[0x1]; 7326 u8 reserved_at_41[0xf]; 7327 u8 function_id[0x10]; 7328 7329 u8 reserved_at_60[0x20]; 7330 }; 7331 7332 struct mlx5_ifc_drain_dct_out_bits { 7333 u8 status[0x8]; 7334 u8 reserved_at_8[0x18]; 7335 7336 u8 syndrome[0x20]; 7337 7338 u8 reserved_at_40[0x40]; 7339 }; 7340 7341 struct mlx5_ifc_drain_dct_in_bits { 7342 u8 opcode[0x10]; 7343 u8 uid[0x10]; 7344 7345 u8 reserved_at_20[0x10]; 7346 u8 op_mod[0x10]; 7347 7348 u8 reserved_at_40[0x8]; 7349 u8 dctn[0x18]; 7350 7351 u8 reserved_at_60[0x20]; 7352 }; 7353 7354 struct mlx5_ifc_disable_hca_out_bits { 7355 u8 status[0x8]; 7356 u8 reserved_at_8[0x18]; 7357 7358 u8 syndrome[0x20]; 7359 7360 u8 reserved_at_40[0x20]; 7361 }; 7362 7363 struct mlx5_ifc_disable_hca_in_bits { 7364 u8 opcode[0x10]; 7365 u8 reserved_at_10[0x10]; 7366 7367 u8 reserved_at_20[0x10]; 7368 u8 op_mod[0x10]; 7369 7370 u8 embedded_cpu_function[0x1]; 7371 u8 reserved_at_41[0xf]; 7372 u8 function_id[0x10]; 7373 7374 u8 reserved_at_60[0x20]; 7375 }; 7376 7377 struct mlx5_ifc_detach_from_mcg_out_bits { 7378 u8 status[0x8]; 7379 u8 reserved_at_8[0x18]; 7380 7381 u8 syndrome[0x20]; 7382 7383 u8 reserved_at_40[0x40]; 7384 }; 7385 7386 struct mlx5_ifc_detach_from_mcg_in_bits { 7387 u8 opcode[0x10]; 7388 u8 uid[0x10]; 7389 7390 u8 reserved_at_20[0x10]; 7391 u8 op_mod[0x10]; 7392 7393 u8 reserved_at_40[0x8]; 7394 u8 qpn[0x18]; 7395 7396 u8 reserved_at_60[0x20]; 7397 7398 u8 multicast_gid[16][0x8]; 7399 }; 7400 7401 struct mlx5_ifc_destroy_xrq_out_bits { 7402 u8 status[0x8]; 7403 u8 reserved_at_8[0x18]; 7404 7405 u8 syndrome[0x20]; 7406 7407 u8 reserved_at_40[0x40]; 7408 }; 7409 7410 struct mlx5_ifc_destroy_xrq_in_bits { 7411 u8 opcode[0x10]; 7412 u8 uid[0x10]; 7413 7414 u8 reserved_at_20[0x10]; 7415 u8 op_mod[0x10]; 7416 7417 u8 reserved_at_40[0x8]; 7418 u8 xrqn[0x18]; 7419 7420 u8 reserved_at_60[0x20]; 7421 }; 7422 7423 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7424 u8 status[0x8]; 7425 u8 reserved_at_8[0x18]; 7426 7427 u8 syndrome[0x20]; 7428 7429 u8 reserved_at_40[0x40]; 7430 }; 7431 7432 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7433 u8 opcode[0x10]; 7434 u8 uid[0x10]; 7435 7436 u8 reserved_at_20[0x10]; 7437 u8 op_mod[0x10]; 7438 7439 u8 reserved_at_40[0x8]; 7440 u8 xrc_srqn[0x18]; 7441 7442 u8 reserved_at_60[0x20]; 7443 }; 7444 7445 struct mlx5_ifc_destroy_tis_out_bits { 7446 u8 status[0x8]; 7447 u8 reserved_at_8[0x18]; 7448 7449 u8 syndrome[0x20]; 7450 7451 u8 reserved_at_40[0x40]; 7452 }; 7453 7454 struct mlx5_ifc_destroy_tis_in_bits { 7455 u8 opcode[0x10]; 7456 u8 uid[0x10]; 7457 7458 u8 reserved_at_20[0x10]; 7459 u8 op_mod[0x10]; 7460 7461 u8 reserved_at_40[0x8]; 7462 u8 tisn[0x18]; 7463 7464 u8 reserved_at_60[0x20]; 7465 }; 7466 7467 struct mlx5_ifc_destroy_tir_out_bits { 7468 u8 status[0x8]; 7469 u8 reserved_at_8[0x18]; 7470 7471 u8 syndrome[0x20]; 7472 7473 u8 reserved_at_40[0x40]; 7474 }; 7475 7476 struct mlx5_ifc_destroy_tir_in_bits { 7477 u8 opcode[0x10]; 7478 u8 uid[0x10]; 7479 7480 u8 reserved_at_20[0x10]; 7481 u8 op_mod[0x10]; 7482 7483 u8 reserved_at_40[0x8]; 7484 u8 tirn[0x18]; 7485 7486 u8 reserved_at_60[0x20]; 7487 }; 7488 7489 struct mlx5_ifc_destroy_srq_out_bits { 7490 u8 status[0x8]; 7491 u8 reserved_at_8[0x18]; 7492 7493 u8 syndrome[0x20]; 7494 7495 u8 reserved_at_40[0x40]; 7496 }; 7497 7498 struct mlx5_ifc_destroy_srq_in_bits { 7499 u8 opcode[0x10]; 7500 u8 uid[0x10]; 7501 7502 u8 reserved_at_20[0x10]; 7503 u8 op_mod[0x10]; 7504 7505 u8 reserved_at_40[0x8]; 7506 u8 srqn[0x18]; 7507 7508 u8 reserved_at_60[0x20]; 7509 }; 7510 7511 struct mlx5_ifc_destroy_sq_out_bits { 7512 u8 status[0x8]; 7513 u8 reserved_at_8[0x18]; 7514 7515 u8 syndrome[0x20]; 7516 7517 u8 reserved_at_40[0x40]; 7518 }; 7519 7520 struct mlx5_ifc_destroy_sq_in_bits { 7521 u8 opcode[0x10]; 7522 u8 uid[0x10]; 7523 7524 u8 reserved_at_20[0x10]; 7525 u8 op_mod[0x10]; 7526 7527 u8 reserved_at_40[0x8]; 7528 u8 sqn[0x18]; 7529 7530 u8 reserved_at_60[0x20]; 7531 }; 7532 7533 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7534 u8 status[0x8]; 7535 u8 reserved_at_8[0x18]; 7536 7537 u8 syndrome[0x20]; 7538 7539 u8 reserved_at_40[0x1c0]; 7540 }; 7541 7542 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7543 u8 opcode[0x10]; 7544 u8 reserved_at_10[0x10]; 7545 7546 u8 reserved_at_20[0x10]; 7547 u8 op_mod[0x10]; 7548 7549 u8 scheduling_hierarchy[0x8]; 7550 u8 reserved_at_48[0x18]; 7551 7552 u8 scheduling_element_id[0x20]; 7553 7554 u8 reserved_at_80[0x180]; 7555 }; 7556 7557 struct mlx5_ifc_destroy_rqt_out_bits { 7558 u8 status[0x8]; 7559 u8 reserved_at_8[0x18]; 7560 7561 u8 syndrome[0x20]; 7562 7563 u8 reserved_at_40[0x40]; 7564 }; 7565 7566 struct mlx5_ifc_destroy_rqt_in_bits { 7567 u8 opcode[0x10]; 7568 u8 uid[0x10]; 7569 7570 u8 reserved_at_20[0x10]; 7571 u8 op_mod[0x10]; 7572 7573 u8 reserved_at_40[0x8]; 7574 u8 rqtn[0x18]; 7575 7576 u8 reserved_at_60[0x20]; 7577 }; 7578 7579 struct mlx5_ifc_destroy_rq_out_bits { 7580 u8 status[0x8]; 7581 u8 reserved_at_8[0x18]; 7582 7583 u8 syndrome[0x20]; 7584 7585 u8 reserved_at_40[0x40]; 7586 }; 7587 7588 struct mlx5_ifc_destroy_rq_in_bits { 7589 u8 opcode[0x10]; 7590 u8 uid[0x10]; 7591 7592 u8 reserved_at_20[0x10]; 7593 u8 op_mod[0x10]; 7594 7595 u8 reserved_at_40[0x8]; 7596 u8 rqn[0x18]; 7597 7598 u8 reserved_at_60[0x20]; 7599 }; 7600 7601 struct mlx5_ifc_set_delay_drop_params_in_bits { 7602 u8 opcode[0x10]; 7603 u8 reserved_at_10[0x10]; 7604 7605 u8 reserved_at_20[0x10]; 7606 u8 op_mod[0x10]; 7607 7608 u8 reserved_at_40[0x20]; 7609 7610 u8 reserved_at_60[0x10]; 7611 u8 delay_drop_timeout[0x10]; 7612 }; 7613 7614 struct mlx5_ifc_set_delay_drop_params_out_bits { 7615 u8 status[0x8]; 7616 u8 reserved_at_8[0x18]; 7617 7618 u8 syndrome[0x20]; 7619 7620 u8 reserved_at_40[0x40]; 7621 }; 7622 7623 struct mlx5_ifc_destroy_rmp_out_bits { 7624 u8 status[0x8]; 7625 u8 reserved_at_8[0x18]; 7626 7627 u8 syndrome[0x20]; 7628 7629 u8 reserved_at_40[0x40]; 7630 }; 7631 7632 struct mlx5_ifc_destroy_rmp_in_bits { 7633 u8 opcode[0x10]; 7634 u8 uid[0x10]; 7635 7636 u8 reserved_at_20[0x10]; 7637 u8 op_mod[0x10]; 7638 7639 u8 reserved_at_40[0x8]; 7640 u8 rmpn[0x18]; 7641 7642 u8 reserved_at_60[0x20]; 7643 }; 7644 7645 struct mlx5_ifc_destroy_qp_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_at_8[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_at_40[0x40]; 7652 }; 7653 7654 struct mlx5_ifc_destroy_qp_in_bits { 7655 u8 opcode[0x10]; 7656 u8 uid[0x10]; 7657 7658 u8 reserved_at_20[0x10]; 7659 u8 op_mod[0x10]; 7660 7661 u8 reserved_at_40[0x8]; 7662 u8 qpn[0x18]; 7663 7664 u8 reserved_at_60[0x20]; 7665 }; 7666 7667 struct mlx5_ifc_destroy_psv_out_bits { 7668 u8 status[0x8]; 7669 u8 reserved_at_8[0x18]; 7670 7671 u8 syndrome[0x20]; 7672 7673 u8 reserved_at_40[0x40]; 7674 }; 7675 7676 struct mlx5_ifc_destroy_psv_in_bits { 7677 u8 opcode[0x10]; 7678 u8 reserved_at_10[0x10]; 7679 7680 u8 reserved_at_20[0x10]; 7681 u8 op_mod[0x10]; 7682 7683 u8 reserved_at_40[0x8]; 7684 u8 psvn[0x18]; 7685 7686 u8 reserved_at_60[0x20]; 7687 }; 7688 7689 struct mlx5_ifc_destroy_mkey_out_bits { 7690 u8 status[0x8]; 7691 u8 reserved_at_8[0x18]; 7692 7693 u8 syndrome[0x20]; 7694 7695 u8 reserved_at_40[0x40]; 7696 }; 7697 7698 struct mlx5_ifc_destroy_mkey_in_bits { 7699 u8 opcode[0x10]; 7700 u8 uid[0x10]; 7701 7702 u8 reserved_at_20[0x10]; 7703 u8 op_mod[0x10]; 7704 7705 u8 reserved_at_40[0x8]; 7706 u8 mkey_index[0x18]; 7707 7708 u8 reserved_at_60[0x20]; 7709 }; 7710 7711 struct mlx5_ifc_destroy_flow_table_out_bits { 7712 u8 status[0x8]; 7713 u8 reserved_at_8[0x18]; 7714 7715 u8 syndrome[0x20]; 7716 7717 u8 reserved_at_40[0x40]; 7718 }; 7719 7720 struct mlx5_ifc_destroy_flow_table_in_bits { 7721 u8 opcode[0x10]; 7722 u8 reserved_at_10[0x10]; 7723 7724 u8 reserved_at_20[0x10]; 7725 u8 op_mod[0x10]; 7726 7727 u8 other_vport[0x1]; 7728 u8 reserved_at_41[0xf]; 7729 u8 vport_number[0x10]; 7730 7731 u8 reserved_at_60[0x20]; 7732 7733 u8 table_type[0x8]; 7734 u8 reserved_at_88[0x18]; 7735 7736 u8 reserved_at_a0[0x8]; 7737 u8 table_id[0x18]; 7738 7739 u8 reserved_at_c0[0x140]; 7740 }; 7741 7742 struct mlx5_ifc_destroy_flow_group_out_bits { 7743 u8 status[0x8]; 7744 u8 reserved_at_8[0x18]; 7745 7746 u8 syndrome[0x20]; 7747 7748 u8 reserved_at_40[0x40]; 7749 }; 7750 7751 struct mlx5_ifc_destroy_flow_group_in_bits { 7752 u8 opcode[0x10]; 7753 u8 reserved_at_10[0x10]; 7754 7755 u8 reserved_at_20[0x10]; 7756 u8 op_mod[0x10]; 7757 7758 u8 other_vport[0x1]; 7759 u8 reserved_at_41[0xf]; 7760 u8 vport_number[0x10]; 7761 7762 u8 reserved_at_60[0x20]; 7763 7764 u8 table_type[0x8]; 7765 u8 reserved_at_88[0x18]; 7766 7767 u8 reserved_at_a0[0x8]; 7768 u8 table_id[0x18]; 7769 7770 u8 group_id[0x20]; 7771 7772 u8 reserved_at_e0[0x120]; 7773 }; 7774 7775 struct mlx5_ifc_destroy_eq_out_bits { 7776 u8 status[0x8]; 7777 u8 reserved_at_8[0x18]; 7778 7779 u8 syndrome[0x20]; 7780 7781 u8 reserved_at_40[0x40]; 7782 }; 7783 7784 struct mlx5_ifc_destroy_eq_in_bits { 7785 u8 opcode[0x10]; 7786 u8 reserved_at_10[0x10]; 7787 7788 u8 reserved_at_20[0x10]; 7789 u8 op_mod[0x10]; 7790 7791 u8 reserved_at_40[0x18]; 7792 u8 eq_number[0x8]; 7793 7794 u8 reserved_at_60[0x20]; 7795 }; 7796 7797 struct mlx5_ifc_destroy_dct_out_bits { 7798 u8 status[0x8]; 7799 u8 reserved_at_8[0x18]; 7800 7801 u8 syndrome[0x20]; 7802 7803 u8 reserved_at_40[0x40]; 7804 }; 7805 7806 struct mlx5_ifc_destroy_dct_in_bits { 7807 u8 opcode[0x10]; 7808 u8 uid[0x10]; 7809 7810 u8 reserved_at_20[0x10]; 7811 u8 op_mod[0x10]; 7812 7813 u8 reserved_at_40[0x8]; 7814 u8 dctn[0x18]; 7815 7816 u8 reserved_at_60[0x20]; 7817 }; 7818 7819 struct mlx5_ifc_destroy_cq_out_bits { 7820 u8 status[0x8]; 7821 u8 reserved_at_8[0x18]; 7822 7823 u8 syndrome[0x20]; 7824 7825 u8 reserved_at_40[0x40]; 7826 }; 7827 7828 struct mlx5_ifc_destroy_cq_in_bits { 7829 u8 opcode[0x10]; 7830 u8 uid[0x10]; 7831 7832 u8 reserved_at_20[0x10]; 7833 u8 op_mod[0x10]; 7834 7835 u8 reserved_at_40[0x8]; 7836 u8 cqn[0x18]; 7837 7838 u8 reserved_at_60[0x20]; 7839 }; 7840 7841 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7842 u8 status[0x8]; 7843 u8 reserved_at_8[0x18]; 7844 7845 u8 syndrome[0x20]; 7846 7847 u8 reserved_at_40[0x40]; 7848 }; 7849 7850 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7851 u8 opcode[0x10]; 7852 u8 reserved_at_10[0x10]; 7853 7854 u8 reserved_at_20[0x10]; 7855 u8 op_mod[0x10]; 7856 7857 u8 reserved_at_40[0x20]; 7858 7859 u8 reserved_at_60[0x10]; 7860 u8 vxlan_udp_port[0x10]; 7861 }; 7862 7863 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7864 u8 status[0x8]; 7865 u8 reserved_at_8[0x18]; 7866 7867 u8 syndrome[0x20]; 7868 7869 u8 reserved_at_40[0x40]; 7870 }; 7871 7872 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7873 u8 opcode[0x10]; 7874 u8 reserved_at_10[0x10]; 7875 7876 u8 reserved_at_20[0x10]; 7877 u8 op_mod[0x10]; 7878 7879 u8 reserved_at_40[0x60]; 7880 7881 u8 reserved_at_a0[0x8]; 7882 u8 table_index[0x18]; 7883 7884 u8 reserved_at_c0[0x140]; 7885 }; 7886 7887 struct mlx5_ifc_delete_fte_out_bits { 7888 u8 status[0x8]; 7889 u8 reserved_at_8[0x18]; 7890 7891 u8 syndrome[0x20]; 7892 7893 u8 reserved_at_40[0x40]; 7894 }; 7895 7896 struct mlx5_ifc_delete_fte_in_bits { 7897 u8 opcode[0x10]; 7898 u8 reserved_at_10[0x10]; 7899 7900 u8 reserved_at_20[0x10]; 7901 u8 op_mod[0x10]; 7902 7903 u8 other_vport[0x1]; 7904 u8 reserved_at_41[0xf]; 7905 u8 vport_number[0x10]; 7906 7907 u8 reserved_at_60[0x20]; 7908 7909 u8 table_type[0x8]; 7910 u8 reserved_at_88[0x18]; 7911 7912 u8 reserved_at_a0[0x8]; 7913 u8 table_id[0x18]; 7914 7915 u8 reserved_at_c0[0x40]; 7916 7917 u8 flow_index[0x20]; 7918 7919 u8 reserved_at_120[0xe0]; 7920 }; 7921 7922 struct mlx5_ifc_dealloc_xrcd_out_bits { 7923 u8 status[0x8]; 7924 u8 reserved_at_8[0x18]; 7925 7926 u8 syndrome[0x20]; 7927 7928 u8 reserved_at_40[0x40]; 7929 }; 7930 7931 struct mlx5_ifc_dealloc_xrcd_in_bits { 7932 u8 opcode[0x10]; 7933 u8 uid[0x10]; 7934 7935 u8 reserved_at_20[0x10]; 7936 u8 op_mod[0x10]; 7937 7938 u8 reserved_at_40[0x8]; 7939 u8 xrcd[0x18]; 7940 7941 u8 reserved_at_60[0x20]; 7942 }; 7943 7944 struct mlx5_ifc_dealloc_uar_out_bits { 7945 u8 status[0x8]; 7946 u8 reserved_at_8[0x18]; 7947 7948 u8 syndrome[0x20]; 7949 7950 u8 reserved_at_40[0x40]; 7951 }; 7952 7953 struct mlx5_ifc_dealloc_uar_in_bits { 7954 u8 opcode[0x10]; 7955 u8 uid[0x10]; 7956 7957 u8 reserved_at_20[0x10]; 7958 u8 op_mod[0x10]; 7959 7960 u8 reserved_at_40[0x8]; 7961 u8 uar[0x18]; 7962 7963 u8 reserved_at_60[0x20]; 7964 }; 7965 7966 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7967 u8 status[0x8]; 7968 u8 reserved_at_8[0x18]; 7969 7970 u8 syndrome[0x20]; 7971 7972 u8 reserved_at_40[0x40]; 7973 }; 7974 7975 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7976 u8 opcode[0x10]; 7977 u8 uid[0x10]; 7978 7979 u8 reserved_at_20[0x10]; 7980 u8 op_mod[0x10]; 7981 7982 u8 reserved_at_40[0x8]; 7983 u8 transport_domain[0x18]; 7984 7985 u8 reserved_at_60[0x20]; 7986 }; 7987 7988 struct mlx5_ifc_dealloc_q_counter_out_bits { 7989 u8 status[0x8]; 7990 u8 reserved_at_8[0x18]; 7991 7992 u8 syndrome[0x20]; 7993 7994 u8 reserved_at_40[0x40]; 7995 }; 7996 7997 struct mlx5_ifc_dealloc_q_counter_in_bits { 7998 u8 opcode[0x10]; 7999 u8 reserved_at_10[0x10]; 8000 8001 u8 reserved_at_20[0x10]; 8002 u8 op_mod[0x10]; 8003 8004 u8 reserved_at_40[0x18]; 8005 u8 counter_set_id[0x8]; 8006 8007 u8 reserved_at_60[0x20]; 8008 }; 8009 8010 struct mlx5_ifc_dealloc_pd_out_bits { 8011 u8 status[0x8]; 8012 u8 reserved_at_8[0x18]; 8013 8014 u8 syndrome[0x20]; 8015 8016 u8 reserved_at_40[0x40]; 8017 }; 8018 8019 struct mlx5_ifc_dealloc_pd_in_bits { 8020 u8 opcode[0x10]; 8021 u8 uid[0x10]; 8022 8023 u8 reserved_at_20[0x10]; 8024 u8 op_mod[0x10]; 8025 8026 u8 reserved_at_40[0x8]; 8027 u8 pd[0x18]; 8028 8029 u8 reserved_at_60[0x20]; 8030 }; 8031 8032 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8033 u8 status[0x8]; 8034 u8 reserved_at_8[0x18]; 8035 8036 u8 syndrome[0x20]; 8037 8038 u8 reserved_at_40[0x40]; 8039 }; 8040 8041 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8042 u8 opcode[0x10]; 8043 u8 reserved_at_10[0x10]; 8044 8045 u8 reserved_at_20[0x10]; 8046 u8 op_mod[0x10]; 8047 8048 u8 flow_counter_id[0x20]; 8049 8050 u8 reserved_at_60[0x20]; 8051 }; 8052 8053 struct mlx5_ifc_create_xrq_out_bits { 8054 u8 status[0x8]; 8055 u8 reserved_at_8[0x18]; 8056 8057 u8 syndrome[0x20]; 8058 8059 u8 reserved_at_40[0x8]; 8060 u8 xrqn[0x18]; 8061 8062 u8 reserved_at_60[0x20]; 8063 }; 8064 8065 struct mlx5_ifc_create_xrq_in_bits { 8066 u8 opcode[0x10]; 8067 u8 uid[0x10]; 8068 8069 u8 reserved_at_20[0x10]; 8070 u8 op_mod[0x10]; 8071 8072 u8 reserved_at_40[0x40]; 8073 8074 struct mlx5_ifc_xrqc_bits xrq_context; 8075 }; 8076 8077 struct mlx5_ifc_create_xrc_srq_out_bits { 8078 u8 status[0x8]; 8079 u8 reserved_at_8[0x18]; 8080 8081 u8 syndrome[0x20]; 8082 8083 u8 reserved_at_40[0x8]; 8084 u8 xrc_srqn[0x18]; 8085 8086 u8 reserved_at_60[0x20]; 8087 }; 8088 8089 struct mlx5_ifc_create_xrc_srq_in_bits { 8090 u8 opcode[0x10]; 8091 u8 uid[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 reserved_at_40[0x40]; 8097 8098 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8099 8100 u8 reserved_at_280[0x60]; 8101 8102 u8 xrc_srq_umem_valid[0x1]; 8103 u8 reserved_at_2e1[0x1f]; 8104 8105 u8 reserved_at_300[0x580]; 8106 8107 u8 pas[][0x40]; 8108 }; 8109 8110 struct mlx5_ifc_create_tis_out_bits { 8111 u8 status[0x8]; 8112 u8 reserved_at_8[0x18]; 8113 8114 u8 syndrome[0x20]; 8115 8116 u8 reserved_at_40[0x8]; 8117 u8 tisn[0x18]; 8118 8119 u8 reserved_at_60[0x20]; 8120 }; 8121 8122 struct mlx5_ifc_create_tis_in_bits { 8123 u8 opcode[0x10]; 8124 u8 uid[0x10]; 8125 8126 u8 reserved_at_20[0x10]; 8127 u8 op_mod[0x10]; 8128 8129 u8 reserved_at_40[0xc0]; 8130 8131 struct mlx5_ifc_tisc_bits ctx; 8132 }; 8133 8134 struct mlx5_ifc_create_tir_out_bits { 8135 u8 status[0x8]; 8136 u8 icm_address_63_40[0x18]; 8137 8138 u8 syndrome[0x20]; 8139 8140 u8 icm_address_39_32[0x8]; 8141 u8 tirn[0x18]; 8142 8143 u8 icm_address_31_0[0x20]; 8144 }; 8145 8146 struct mlx5_ifc_create_tir_in_bits { 8147 u8 opcode[0x10]; 8148 u8 uid[0x10]; 8149 8150 u8 reserved_at_20[0x10]; 8151 u8 op_mod[0x10]; 8152 8153 u8 reserved_at_40[0xc0]; 8154 8155 struct mlx5_ifc_tirc_bits ctx; 8156 }; 8157 8158 struct mlx5_ifc_create_srq_out_bits { 8159 u8 status[0x8]; 8160 u8 reserved_at_8[0x18]; 8161 8162 u8 syndrome[0x20]; 8163 8164 u8 reserved_at_40[0x8]; 8165 u8 srqn[0x18]; 8166 8167 u8 reserved_at_60[0x20]; 8168 }; 8169 8170 struct mlx5_ifc_create_srq_in_bits { 8171 u8 opcode[0x10]; 8172 u8 uid[0x10]; 8173 8174 u8 reserved_at_20[0x10]; 8175 u8 op_mod[0x10]; 8176 8177 u8 reserved_at_40[0x40]; 8178 8179 struct mlx5_ifc_srqc_bits srq_context_entry; 8180 8181 u8 reserved_at_280[0x600]; 8182 8183 u8 pas[][0x40]; 8184 }; 8185 8186 struct mlx5_ifc_create_sq_out_bits { 8187 u8 status[0x8]; 8188 u8 reserved_at_8[0x18]; 8189 8190 u8 syndrome[0x20]; 8191 8192 u8 reserved_at_40[0x8]; 8193 u8 sqn[0x18]; 8194 8195 u8 reserved_at_60[0x20]; 8196 }; 8197 8198 struct mlx5_ifc_create_sq_in_bits { 8199 u8 opcode[0x10]; 8200 u8 uid[0x10]; 8201 8202 u8 reserved_at_20[0x10]; 8203 u8 op_mod[0x10]; 8204 8205 u8 reserved_at_40[0xc0]; 8206 8207 struct mlx5_ifc_sqc_bits ctx; 8208 }; 8209 8210 struct mlx5_ifc_create_scheduling_element_out_bits { 8211 u8 status[0x8]; 8212 u8 reserved_at_8[0x18]; 8213 8214 u8 syndrome[0x20]; 8215 8216 u8 reserved_at_40[0x40]; 8217 8218 u8 scheduling_element_id[0x20]; 8219 8220 u8 reserved_at_a0[0x160]; 8221 }; 8222 8223 struct mlx5_ifc_create_scheduling_element_in_bits { 8224 u8 opcode[0x10]; 8225 u8 reserved_at_10[0x10]; 8226 8227 u8 reserved_at_20[0x10]; 8228 u8 op_mod[0x10]; 8229 8230 u8 scheduling_hierarchy[0x8]; 8231 u8 reserved_at_48[0x18]; 8232 8233 u8 reserved_at_60[0xa0]; 8234 8235 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8236 8237 u8 reserved_at_300[0x100]; 8238 }; 8239 8240 struct mlx5_ifc_create_rqt_out_bits { 8241 u8 status[0x8]; 8242 u8 reserved_at_8[0x18]; 8243 8244 u8 syndrome[0x20]; 8245 8246 u8 reserved_at_40[0x8]; 8247 u8 rqtn[0x18]; 8248 8249 u8 reserved_at_60[0x20]; 8250 }; 8251 8252 struct mlx5_ifc_create_rqt_in_bits { 8253 u8 opcode[0x10]; 8254 u8 uid[0x10]; 8255 8256 u8 reserved_at_20[0x10]; 8257 u8 op_mod[0x10]; 8258 8259 u8 reserved_at_40[0xc0]; 8260 8261 struct mlx5_ifc_rqtc_bits rqt_context; 8262 }; 8263 8264 struct mlx5_ifc_create_rq_out_bits { 8265 u8 status[0x8]; 8266 u8 reserved_at_8[0x18]; 8267 8268 u8 syndrome[0x20]; 8269 8270 u8 reserved_at_40[0x8]; 8271 u8 rqn[0x18]; 8272 8273 u8 reserved_at_60[0x20]; 8274 }; 8275 8276 struct mlx5_ifc_create_rq_in_bits { 8277 u8 opcode[0x10]; 8278 u8 uid[0x10]; 8279 8280 u8 reserved_at_20[0x10]; 8281 u8 op_mod[0x10]; 8282 8283 u8 reserved_at_40[0xc0]; 8284 8285 struct mlx5_ifc_rqc_bits ctx; 8286 }; 8287 8288 struct mlx5_ifc_create_rmp_out_bits { 8289 u8 status[0x8]; 8290 u8 reserved_at_8[0x18]; 8291 8292 u8 syndrome[0x20]; 8293 8294 u8 reserved_at_40[0x8]; 8295 u8 rmpn[0x18]; 8296 8297 u8 reserved_at_60[0x20]; 8298 }; 8299 8300 struct mlx5_ifc_create_rmp_in_bits { 8301 u8 opcode[0x10]; 8302 u8 uid[0x10]; 8303 8304 u8 reserved_at_20[0x10]; 8305 u8 op_mod[0x10]; 8306 8307 u8 reserved_at_40[0xc0]; 8308 8309 struct mlx5_ifc_rmpc_bits ctx; 8310 }; 8311 8312 struct mlx5_ifc_create_qp_out_bits { 8313 u8 status[0x8]; 8314 u8 reserved_at_8[0x18]; 8315 8316 u8 syndrome[0x20]; 8317 8318 u8 reserved_at_40[0x8]; 8319 u8 qpn[0x18]; 8320 8321 u8 ece[0x20]; 8322 }; 8323 8324 struct mlx5_ifc_create_qp_in_bits { 8325 u8 opcode[0x10]; 8326 u8 uid[0x10]; 8327 8328 u8 reserved_at_20[0x10]; 8329 u8 op_mod[0x10]; 8330 8331 u8 reserved_at_40[0x8]; 8332 u8 input_qpn[0x18]; 8333 8334 u8 reserved_at_60[0x20]; 8335 u8 opt_param_mask[0x20]; 8336 8337 u8 ece[0x20]; 8338 8339 struct mlx5_ifc_qpc_bits qpc; 8340 8341 u8 reserved_at_800[0x60]; 8342 8343 u8 wq_umem_valid[0x1]; 8344 u8 reserved_at_861[0x1f]; 8345 8346 u8 pas[][0x40]; 8347 }; 8348 8349 struct mlx5_ifc_create_psv_out_bits { 8350 u8 status[0x8]; 8351 u8 reserved_at_8[0x18]; 8352 8353 u8 syndrome[0x20]; 8354 8355 u8 reserved_at_40[0x40]; 8356 8357 u8 reserved_at_80[0x8]; 8358 u8 psv0_index[0x18]; 8359 8360 u8 reserved_at_a0[0x8]; 8361 u8 psv1_index[0x18]; 8362 8363 u8 reserved_at_c0[0x8]; 8364 u8 psv2_index[0x18]; 8365 8366 u8 reserved_at_e0[0x8]; 8367 u8 psv3_index[0x18]; 8368 }; 8369 8370 struct mlx5_ifc_create_psv_in_bits { 8371 u8 opcode[0x10]; 8372 u8 reserved_at_10[0x10]; 8373 8374 u8 reserved_at_20[0x10]; 8375 u8 op_mod[0x10]; 8376 8377 u8 num_psv[0x4]; 8378 u8 reserved_at_44[0x4]; 8379 u8 pd[0x18]; 8380 8381 u8 reserved_at_60[0x20]; 8382 }; 8383 8384 struct mlx5_ifc_create_mkey_out_bits { 8385 u8 status[0x8]; 8386 u8 reserved_at_8[0x18]; 8387 8388 u8 syndrome[0x20]; 8389 8390 u8 reserved_at_40[0x8]; 8391 u8 mkey_index[0x18]; 8392 8393 u8 reserved_at_60[0x20]; 8394 }; 8395 8396 struct mlx5_ifc_create_mkey_in_bits { 8397 u8 opcode[0x10]; 8398 u8 uid[0x10]; 8399 8400 u8 reserved_at_20[0x10]; 8401 u8 op_mod[0x10]; 8402 8403 u8 reserved_at_40[0x20]; 8404 8405 u8 pg_access[0x1]; 8406 u8 mkey_umem_valid[0x1]; 8407 u8 reserved_at_62[0x1e]; 8408 8409 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8410 8411 u8 reserved_at_280[0x80]; 8412 8413 u8 translations_octword_actual_size[0x20]; 8414 8415 u8 reserved_at_320[0x560]; 8416 8417 u8 klm_pas_mtt[][0x20]; 8418 }; 8419 8420 enum { 8421 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8422 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8423 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8424 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8425 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8426 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8427 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8428 }; 8429 8430 struct mlx5_ifc_create_flow_table_out_bits { 8431 u8 status[0x8]; 8432 u8 icm_address_63_40[0x18]; 8433 8434 u8 syndrome[0x20]; 8435 8436 u8 icm_address_39_32[0x8]; 8437 u8 table_id[0x18]; 8438 8439 u8 icm_address_31_0[0x20]; 8440 }; 8441 8442 struct mlx5_ifc_create_flow_table_in_bits { 8443 u8 opcode[0x10]; 8444 u8 reserved_at_10[0x10]; 8445 8446 u8 reserved_at_20[0x10]; 8447 u8 op_mod[0x10]; 8448 8449 u8 other_vport[0x1]; 8450 u8 reserved_at_41[0xf]; 8451 u8 vport_number[0x10]; 8452 8453 u8 reserved_at_60[0x20]; 8454 8455 u8 table_type[0x8]; 8456 u8 reserved_at_88[0x18]; 8457 8458 u8 reserved_at_a0[0x20]; 8459 8460 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8461 }; 8462 8463 struct mlx5_ifc_create_flow_group_out_bits { 8464 u8 status[0x8]; 8465 u8 reserved_at_8[0x18]; 8466 8467 u8 syndrome[0x20]; 8468 8469 u8 reserved_at_40[0x8]; 8470 u8 group_id[0x18]; 8471 8472 u8 reserved_at_60[0x20]; 8473 }; 8474 8475 enum { 8476 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8477 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8478 }; 8479 8480 enum { 8481 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8482 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8483 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8484 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8485 }; 8486 8487 struct mlx5_ifc_create_flow_group_in_bits { 8488 u8 opcode[0x10]; 8489 u8 reserved_at_10[0x10]; 8490 8491 u8 reserved_at_20[0x10]; 8492 u8 op_mod[0x10]; 8493 8494 u8 other_vport[0x1]; 8495 u8 reserved_at_41[0xf]; 8496 u8 vport_number[0x10]; 8497 8498 u8 reserved_at_60[0x20]; 8499 8500 u8 table_type[0x8]; 8501 u8 reserved_at_88[0x4]; 8502 u8 group_type[0x4]; 8503 u8 reserved_at_90[0x10]; 8504 8505 u8 reserved_at_a0[0x8]; 8506 u8 table_id[0x18]; 8507 8508 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8509 8510 u8 reserved_at_c1[0x1f]; 8511 8512 u8 start_flow_index[0x20]; 8513 8514 u8 reserved_at_100[0x20]; 8515 8516 u8 end_flow_index[0x20]; 8517 8518 u8 reserved_at_140[0x10]; 8519 u8 match_definer_id[0x10]; 8520 8521 u8 reserved_at_160[0x80]; 8522 8523 u8 reserved_at_1e0[0x18]; 8524 u8 match_criteria_enable[0x8]; 8525 8526 struct mlx5_ifc_fte_match_param_bits match_criteria; 8527 8528 u8 reserved_at_1200[0xe00]; 8529 }; 8530 8531 struct mlx5_ifc_create_eq_out_bits { 8532 u8 status[0x8]; 8533 u8 reserved_at_8[0x18]; 8534 8535 u8 syndrome[0x20]; 8536 8537 u8 reserved_at_40[0x18]; 8538 u8 eq_number[0x8]; 8539 8540 u8 reserved_at_60[0x20]; 8541 }; 8542 8543 struct mlx5_ifc_create_eq_in_bits { 8544 u8 opcode[0x10]; 8545 u8 uid[0x10]; 8546 8547 u8 reserved_at_20[0x10]; 8548 u8 op_mod[0x10]; 8549 8550 u8 reserved_at_40[0x40]; 8551 8552 struct mlx5_ifc_eqc_bits eq_context_entry; 8553 8554 u8 reserved_at_280[0x40]; 8555 8556 u8 event_bitmask[4][0x40]; 8557 8558 u8 reserved_at_3c0[0x4c0]; 8559 8560 u8 pas[][0x40]; 8561 }; 8562 8563 struct mlx5_ifc_create_dct_out_bits { 8564 u8 status[0x8]; 8565 u8 reserved_at_8[0x18]; 8566 8567 u8 syndrome[0x20]; 8568 8569 u8 reserved_at_40[0x8]; 8570 u8 dctn[0x18]; 8571 8572 u8 ece[0x20]; 8573 }; 8574 8575 struct mlx5_ifc_create_dct_in_bits { 8576 u8 opcode[0x10]; 8577 u8 uid[0x10]; 8578 8579 u8 reserved_at_20[0x10]; 8580 u8 op_mod[0x10]; 8581 8582 u8 reserved_at_40[0x40]; 8583 8584 struct mlx5_ifc_dctc_bits dct_context_entry; 8585 8586 u8 reserved_at_280[0x180]; 8587 }; 8588 8589 struct mlx5_ifc_create_cq_out_bits { 8590 u8 status[0x8]; 8591 u8 reserved_at_8[0x18]; 8592 8593 u8 syndrome[0x20]; 8594 8595 u8 reserved_at_40[0x8]; 8596 u8 cqn[0x18]; 8597 8598 u8 reserved_at_60[0x20]; 8599 }; 8600 8601 struct mlx5_ifc_create_cq_in_bits { 8602 u8 opcode[0x10]; 8603 u8 uid[0x10]; 8604 8605 u8 reserved_at_20[0x10]; 8606 u8 op_mod[0x10]; 8607 8608 u8 reserved_at_40[0x40]; 8609 8610 struct mlx5_ifc_cqc_bits cq_context; 8611 8612 u8 reserved_at_280[0x60]; 8613 8614 u8 cq_umem_valid[0x1]; 8615 u8 reserved_at_2e1[0x59f]; 8616 8617 u8 pas[][0x40]; 8618 }; 8619 8620 struct mlx5_ifc_config_int_moderation_out_bits { 8621 u8 status[0x8]; 8622 u8 reserved_at_8[0x18]; 8623 8624 u8 syndrome[0x20]; 8625 8626 u8 reserved_at_40[0x4]; 8627 u8 min_delay[0xc]; 8628 u8 int_vector[0x10]; 8629 8630 u8 reserved_at_60[0x20]; 8631 }; 8632 8633 enum { 8634 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8635 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8636 }; 8637 8638 struct mlx5_ifc_config_int_moderation_in_bits { 8639 u8 opcode[0x10]; 8640 u8 reserved_at_10[0x10]; 8641 8642 u8 reserved_at_20[0x10]; 8643 u8 op_mod[0x10]; 8644 8645 u8 reserved_at_40[0x4]; 8646 u8 min_delay[0xc]; 8647 u8 int_vector[0x10]; 8648 8649 u8 reserved_at_60[0x20]; 8650 }; 8651 8652 struct mlx5_ifc_attach_to_mcg_out_bits { 8653 u8 status[0x8]; 8654 u8 reserved_at_8[0x18]; 8655 8656 u8 syndrome[0x20]; 8657 8658 u8 reserved_at_40[0x40]; 8659 }; 8660 8661 struct mlx5_ifc_attach_to_mcg_in_bits { 8662 u8 opcode[0x10]; 8663 u8 uid[0x10]; 8664 8665 u8 reserved_at_20[0x10]; 8666 u8 op_mod[0x10]; 8667 8668 u8 reserved_at_40[0x8]; 8669 u8 qpn[0x18]; 8670 8671 u8 reserved_at_60[0x20]; 8672 8673 u8 multicast_gid[16][0x8]; 8674 }; 8675 8676 struct mlx5_ifc_arm_xrq_out_bits { 8677 u8 status[0x8]; 8678 u8 reserved_at_8[0x18]; 8679 8680 u8 syndrome[0x20]; 8681 8682 u8 reserved_at_40[0x40]; 8683 }; 8684 8685 struct mlx5_ifc_arm_xrq_in_bits { 8686 u8 opcode[0x10]; 8687 u8 reserved_at_10[0x10]; 8688 8689 u8 reserved_at_20[0x10]; 8690 u8 op_mod[0x10]; 8691 8692 u8 reserved_at_40[0x8]; 8693 u8 xrqn[0x18]; 8694 8695 u8 reserved_at_60[0x10]; 8696 u8 lwm[0x10]; 8697 }; 8698 8699 struct mlx5_ifc_arm_xrc_srq_out_bits { 8700 u8 status[0x8]; 8701 u8 reserved_at_8[0x18]; 8702 8703 u8 syndrome[0x20]; 8704 8705 u8 reserved_at_40[0x40]; 8706 }; 8707 8708 enum { 8709 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8710 }; 8711 8712 struct mlx5_ifc_arm_xrc_srq_in_bits { 8713 u8 opcode[0x10]; 8714 u8 uid[0x10]; 8715 8716 u8 reserved_at_20[0x10]; 8717 u8 op_mod[0x10]; 8718 8719 u8 reserved_at_40[0x8]; 8720 u8 xrc_srqn[0x18]; 8721 8722 u8 reserved_at_60[0x10]; 8723 u8 lwm[0x10]; 8724 }; 8725 8726 struct mlx5_ifc_arm_rq_out_bits { 8727 u8 status[0x8]; 8728 u8 reserved_at_8[0x18]; 8729 8730 u8 syndrome[0x20]; 8731 8732 u8 reserved_at_40[0x40]; 8733 }; 8734 8735 enum { 8736 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8737 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8738 }; 8739 8740 struct mlx5_ifc_arm_rq_in_bits { 8741 u8 opcode[0x10]; 8742 u8 uid[0x10]; 8743 8744 u8 reserved_at_20[0x10]; 8745 u8 op_mod[0x10]; 8746 8747 u8 reserved_at_40[0x8]; 8748 u8 srq_number[0x18]; 8749 8750 u8 reserved_at_60[0x10]; 8751 u8 lwm[0x10]; 8752 }; 8753 8754 struct mlx5_ifc_arm_dct_out_bits { 8755 u8 status[0x8]; 8756 u8 reserved_at_8[0x18]; 8757 8758 u8 syndrome[0x20]; 8759 8760 u8 reserved_at_40[0x40]; 8761 }; 8762 8763 struct mlx5_ifc_arm_dct_in_bits { 8764 u8 opcode[0x10]; 8765 u8 reserved_at_10[0x10]; 8766 8767 u8 reserved_at_20[0x10]; 8768 u8 op_mod[0x10]; 8769 8770 u8 reserved_at_40[0x8]; 8771 u8 dct_number[0x18]; 8772 8773 u8 reserved_at_60[0x20]; 8774 }; 8775 8776 struct mlx5_ifc_alloc_xrcd_out_bits { 8777 u8 status[0x8]; 8778 u8 reserved_at_8[0x18]; 8779 8780 u8 syndrome[0x20]; 8781 8782 u8 reserved_at_40[0x8]; 8783 u8 xrcd[0x18]; 8784 8785 u8 reserved_at_60[0x20]; 8786 }; 8787 8788 struct mlx5_ifc_alloc_xrcd_in_bits { 8789 u8 opcode[0x10]; 8790 u8 uid[0x10]; 8791 8792 u8 reserved_at_20[0x10]; 8793 u8 op_mod[0x10]; 8794 8795 u8 reserved_at_40[0x40]; 8796 }; 8797 8798 struct mlx5_ifc_alloc_uar_out_bits { 8799 u8 status[0x8]; 8800 u8 reserved_at_8[0x18]; 8801 8802 u8 syndrome[0x20]; 8803 8804 u8 reserved_at_40[0x8]; 8805 u8 uar[0x18]; 8806 8807 u8 reserved_at_60[0x20]; 8808 }; 8809 8810 struct mlx5_ifc_alloc_uar_in_bits { 8811 u8 opcode[0x10]; 8812 u8 uid[0x10]; 8813 8814 u8 reserved_at_20[0x10]; 8815 u8 op_mod[0x10]; 8816 8817 u8 reserved_at_40[0x40]; 8818 }; 8819 8820 struct mlx5_ifc_alloc_transport_domain_out_bits { 8821 u8 status[0x8]; 8822 u8 reserved_at_8[0x18]; 8823 8824 u8 syndrome[0x20]; 8825 8826 u8 reserved_at_40[0x8]; 8827 u8 transport_domain[0x18]; 8828 8829 u8 reserved_at_60[0x20]; 8830 }; 8831 8832 struct mlx5_ifc_alloc_transport_domain_in_bits { 8833 u8 opcode[0x10]; 8834 u8 uid[0x10]; 8835 8836 u8 reserved_at_20[0x10]; 8837 u8 op_mod[0x10]; 8838 8839 u8 reserved_at_40[0x40]; 8840 }; 8841 8842 struct mlx5_ifc_alloc_q_counter_out_bits { 8843 u8 status[0x8]; 8844 u8 reserved_at_8[0x18]; 8845 8846 u8 syndrome[0x20]; 8847 8848 u8 reserved_at_40[0x18]; 8849 u8 counter_set_id[0x8]; 8850 8851 u8 reserved_at_60[0x20]; 8852 }; 8853 8854 struct mlx5_ifc_alloc_q_counter_in_bits { 8855 u8 opcode[0x10]; 8856 u8 uid[0x10]; 8857 8858 u8 reserved_at_20[0x10]; 8859 u8 op_mod[0x10]; 8860 8861 u8 reserved_at_40[0x40]; 8862 }; 8863 8864 struct mlx5_ifc_alloc_pd_out_bits { 8865 u8 status[0x8]; 8866 u8 reserved_at_8[0x18]; 8867 8868 u8 syndrome[0x20]; 8869 8870 u8 reserved_at_40[0x8]; 8871 u8 pd[0x18]; 8872 8873 u8 reserved_at_60[0x20]; 8874 }; 8875 8876 struct mlx5_ifc_alloc_pd_in_bits { 8877 u8 opcode[0x10]; 8878 u8 uid[0x10]; 8879 8880 u8 reserved_at_20[0x10]; 8881 u8 op_mod[0x10]; 8882 8883 u8 reserved_at_40[0x40]; 8884 }; 8885 8886 struct mlx5_ifc_alloc_flow_counter_out_bits { 8887 u8 status[0x8]; 8888 u8 reserved_at_8[0x18]; 8889 8890 u8 syndrome[0x20]; 8891 8892 u8 flow_counter_id[0x20]; 8893 8894 u8 reserved_at_60[0x20]; 8895 }; 8896 8897 struct mlx5_ifc_alloc_flow_counter_in_bits { 8898 u8 opcode[0x10]; 8899 u8 reserved_at_10[0x10]; 8900 8901 u8 reserved_at_20[0x10]; 8902 u8 op_mod[0x10]; 8903 8904 u8 reserved_at_40[0x38]; 8905 u8 flow_counter_bulk[0x8]; 8906 }; 8907 8908 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8909 u8 status[0x8]; 8910 u8 reserved_at_8[0x18]; 8911 8912 u8 syndrome[0x20]; 8913 8914 u8 reserved_at_40[0x40]; 8915 }; 8916 8917 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8918 u8 opcode[0x10]; 8919 u8 reserved_at_10[0x10]; 8920 8921 u8 reserved_at_20[0x10]; 8922 u8 op_mod[0x10]; 8923 8924 u8 reserved_at_40[0x20]; 8925 8926 u8 reserved_at_60[0x10]; 8927 u8 vxlan_udp_port[0x10]; 8928 }; 8929 8930 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8931 u8 status[0x8]; 8932 u8 reserved_at_8[0x18]; 8933 8934 u8 syndrome[0x20]; 8935 8936 u8 reserved_at_40[0x40]; 8937 }; 8938 8939 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8940 u8 rate_limit[0x20]; 8941 8942 u8 burst_upper_bound[0x20]; 8943 8944 u8 reserved_at_40[0x10]; 8945 u8 typical_packet_size[0x10]; 8946 8947 u8 reserved_at_60[0x120]; 8948 }; 8949 8950 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8951 u8 opcode[0x10]; 8952 u8 uid[0x10]; 8953 8954 u8 reserved_at_20[0x10]; 8955 u8 op_mod[0x10]; 8956 8957 u8 reserved_at_40[0x10]; 8958 u8 rate_limit_index[0x10]; 8959 8960 u8 reserved_at_60[0x20]; 8961 8962 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8963 }; 8964 8965 struct mlx5_ifc_access_register_out_bits { 8966 u8 status[0x8]; 8967 u8 reserved_at_8[0x18]; 8968 8969 u8 syndrome[0x20]; 8970 8971 u8 reserved_at_40[0x40]; 8972 8973 u8 register_data[][0x20]; 8974 }; 8975 8976 enum { 8977 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8978 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8979 }; 8980 8981 struct mlx5_ifc_access_register_in_bits { 8982 u8 opcode[0x10]; 8983 u8 reserved_at_10[0x10]; 8984 8985 u8 reserved_at_20[0x10]; 8986 u8 op_mod[0x10]; 8987 8988 u8 reserved_at_40[0x10]; 8989 u8 register_id[0x10]; 8990 8991 u8 argument[0x20]; 8992 8993 u8 register_data[][0x20]; 8994 }; 8995 8996 struct mlx5_ifc_sltp_reg_bits { 8997 u8 status[0x4]; 8998 u8 version[0x4]; 8999 u8 local_port[0x8]; 9000 u8 pnat[0x2]; 9001 u8 reserved_at_12[0x2]; 9002 u8 lane[0x4]; 9003 u8 reserved_at_18[0x8]; 9004 9005 u8 reserved_at_20[0x20]; 9006 9007 u8 reserved_at_40[0x7]; 9008 u8 polarity[0x1]; 9009 u8 ob_tap0[0x8]; 9010 u8 ob_tap1[0x8]; 9011 u8 ob_tap2[0x8]; 9012 9013 u8 reserved_at_60[0xc]; 9014 u8 ob_preemp_mode[0x4]; 9015 u8 ob_reg[0x8]; 9016 u8 ob_bias[0x8]; 9017 9018 u8 reserved_at_80[0x20]; 9019 }; 9020 9021 struct mlx5_ifc_slrg_reg_bits { 9022 u8 status[0x4]; 9023 u8 version[0x4]; 9024 u8 local_port[0x8]; 9025 u8 pnat[0x2]; 9026 u8 reserved_at_12[0x2]; 9027 u8 lane[0x4]; 9028 u8 reserved_at_18[0x8]; 9029 9030 u8 time_to_link_up[0x10]; 9031 u8 reserved_at_30[0xc]; 9032 u8 grade_lane_speed[0x4]; 9033 9034 u8 grade_version[0x8]; 9035 u8 grade[0x18]; 9036 9037 u8 reserved_at_60[0x4]; 9038 u8 height_grade_type[0x4]; 9039 u8 height_grade[0x18]; 9040 9041 u8 height_dz[0x10]; 9042 u8 height_dv[0x10]; 9043 9044 u8 reserved_at_a0[0x10]; 9045 u8 height_sigma[0x10]; 9046 9047 u8 reserved_at_c0[0x20]; 9048 9049 u8 reserved_at_e0[0x4]; 9050 u8 phase_grade_type[0x4]; 9051 u8 phase_grade[0x18]; 9052 9053 u8 reserved_at_100[0x8]; 9054 u8 phase_eo_pos[0x8]; 9055 u8 reserved_at_110[0x8]; 9056 u8 phase_eo_neg[0x8]; 9057 9058 u8 ffe_set_tested[0x10]; 9059 u8 test_errors_per_lane[0x10]; 9060 }; 9061 9062 struct mlx5_ifc_pvlc_reg_bits { 9063 u8 reserved_at_0[0x8]; 9064 u8 local_port[0x8]; 9065 u8 reserved_at_10[0x10]; 9066 9067 u8 reserved_at_20[0x1c]; 9068 u8 vl_hw_cap[0x4]; 9069 9070 u8 reserved_at_40[0x1c]; 9071 u8 vl_admin[0x4]; 9072 9073 u8 reserved_at_60[0x1c]; 9074 u8 vl_operational[0x4]; 9075 }; 9076 9077 struct mlx5_ifc_pude_reg_bits { 9078 u8 swid[0x8]; 9079 u8 local_port[0x8]; 9080 u8 reserved_at_10[0x4]; 9081 u8 admin_status[0x4]; 9082 u8 reserved_at_18[0x4]; 9083 u8 oper_status[0x4]; 9084 9085 u8 reserved_at_20[0x60]; 9086 }; 9087 9088 struct mlx5_ifc_ptys_reg_bits { 9089 u8 reserved_at_0[0x1]; 9090 u8 an_disable_admin[0x1]; 9091 u8 an_disable_cap[0x1]; 9092 u8 reserved_at_3[0x5]; 9093 u8 local_port[0x8]; 9094 u8 reserved_at_10[0xd]; 9095 u8 proto_mask[0x3]; 9096 9097 u8 an_status[0x4]; 9098 u8 reserved_at_24[0xc]; 9099 u8 data_rate_oper[0x10]; 9100 9101 u8 ext_eth_proto_capability[0x20]; 9102 9103 u8 eth_proto_capability[0x20]; 9104 9105 u8 ib_link_width_capability[0x10]; 9106 u8 ib_proto_capability[0x10]; 9107 9108 u8 ext_eth_proto_admin[0x20]; 9109 9110 u8 eth_proto_admin[0x20]; 9111 9112 u8 ib_link_width_admin[0x10]; 9113 u8 ib_proto_admin[0x10]; 9114 9115 u8 ext_eth_proto_oper[0x20]; 9116 9117 u8 eth_proto_oper[0x20]; 9118 9119 u8 ib_link_width_oper[0x10]; 9120 u8 ib_proto_oper[0x10]; 9121 9122 u8 reserved_at_160[0x1c]; 9123 u8 connector_type[0x4]; 9124 9125 u8 eth_proto_lp_advertise[0x20]; 9126 9127 u8 reserved_at_1a0[0x60]; 9128 }; 9129 9130 struct mlx5_ifc_mlcr_reg_bits { 9131 u8 reserved_at_0[0x8]; 9132 u8 local_port[0x8]; 9133 u8 reserved_at_10[0x20]; 9134 9135 u8 beacon_duration[0x10]; 9136 u8 reserved_at_40[0x10]; 9137 9138 u8 beacon_remain[0x10]; 9139 }; 9140 9141 struct mlx5_ifc_ptas_reg_bits { 9142 u8 reserved_at_0[0x20]; 9143 9144 u8 algorithm_options[0x10]; 9145 u8 reserved_at_30[0x4]; 9146 u8 repetitions_mode[0x4]; 9147 u8 num_of_repetitions[0x8]; 9148 9149 u8 grade_version[0x8]; 9150 u8 height_grade_type[0x4]; 9151 u8 phase_grade_type[0x4]; 9152 u8 height_grade_weight[0x8]; 9153 u8 phase_grade_weight[0x8]; 9154 9155 u8 gisim_measure_bits[0x10]; 9156 u8 adaptive_tap_measure_bits[0x10]; 9157 9158 u8 ber_bath_high_error_threshold[0x10]; 9159 u8 ber_bath_mid_error_threshold[0x10]; 9160 9161 u8 ber_bath_low_error_threshold[0x10]; 9162 u8 one_ratio_high_threshold[0x10]; 9163 9164 u8 one_ratio_high_mid_threshold[0x10]; 9165 u8 one_ratio_low_mid_threshold[0x10]; 9166 9167 u8 one_ratio_low_threshold[0x10]; 9168 u8 ndeo_error_threshold[0x10]; 9169 9170 u8 mixer_offset_step_size[0x10]; 9171 u8 reserved_at_110[0x8]; 9172 u8 mix90_phase_for_voltage_bath[0x8]; 9173 9174 u8 mixer_offset_start[0x10]; 9175 u8 mixer_offset_end[0x10]; 9176 9177 u8 reserved_at_140[0x15]; 9178 u8 ber_test_time[0xb]; 9179 }; 9180 9181 struct mlx5_ifc_pspa_reg_bits { 9182 u8 swid[0x8]; 9183 u8 local_port[0x8]; 9184 u8 sub_port[0x8]; 9185 u8 reserved_at_18[0x8]; 9186 9187 u8 reserved_at_20[0x20]; 9188 }; 9189 9190 struct mlx5_ifc_pqdr_reg_bits { 9191 u8 reserved_at_0[0x8]; 9192 u8 local_port[0x8]; 9193 u8 reserved_at_10[0x5]; 9194 u8 prio[0x3]; 9195 u8 reserved_at_18[0x6]; 9196 u8 mode[0x2]; 9197 9198 u8 reserved_at_20[0x20]; 9199 9200 u8 reserved_at_40[0x10]; 9201 u8 min_threshold[0x10]; 9202 9203 u8 reserved_at_60[0x10]; 9204 u8 max_threshold[0x10]; 9205 9206 u8 reserved_at_80[0x10]; 9207 u8 mark_probability_denominator[0x10]; 9208 9209 u8 reserved_at_a0[0x60]; 9210 }; 9211 9212 struct mlx5_ifc_ppsc_reg_bits { 9213 u8 reserved_at_0[0x8]; 9214 u8 local_port[0x8]; 9215 u8 reserved_at_10[0x10]; 9216 9217 u8 reserved_at_20[0x60]; 9218 9219 u8 reserved_at_80[0x1c]; 9220 u8 wrps_admin[0x4]; 9221 9222 u8 reserved_at_a0[0x1c]; 9223 u8 wrps_status[0x4]; 9224 9225 u8 reserved_at_c0[0x8]; 9226 u8 up_threshold[0x8]; 9227 u8 reserved_at_d0[0x8]; 9228 u8 down_threshold[0x8]; 9229 9230 u8 reserved_at_e0[0x20]; 9231 9232 u8 reserved_at_100[0x1c]; 9233 u8 srps_admin[0x4]; 9234 9235 u8 reserved_at_120[0x1c]; 9236 u8 srps_status[0x4]; 9237 9238 u8 reserved_at_140[0x40]; 9239 }; 9240 9241 struct mlx5_ifc_pplr_reg_bits { 9242 u8 reserved_at_0[0x8]; 9243 u8 local_port[0x8]; 9244 u8 reserved_at_10[0x10]; 9245 9246 u8 reserved_at_20[0x8]; 9247 u8 lb_cap[0x8]; 9248 u8 reserved_at_30[0x8]; 9249 u8 lb_en[0x8]; 9250 }; 9251 9252 struct mlx5_ifc_pplm_reg_bits { 9253 u8 reserved_at_0[0x8]; 9254 u8 local_port[0x8]; 9255 u8 reserved_at_10[0x10]; 9256 9257 u8 reserved_at_20[0x20]; 9258 9259 u8 port_profile_mode[0x8]; 9260 u8 static_port_profile[0x8]; 9261 u8 active_port_profile[0x8]; 9262 u8 reserved_at_58[0x8]; 9263 9264 u8 retransmission_active[0x8]; 9265 u8 fec_mode_active[0x18]; 9266 9267 u8 rs_fec_correction_bypass_cap[0x4]; 9268 u8 reserved_at_84[0x8]; 9269 u8 fec_override_cap_56g[0x4]; 9270 u8 fec_override_cap_100g[0x4]; 9271 u8 fec_override_cap_50g[0x4]; 9272 u8 fec_override_cap_25g[0x4]; 9273 u8 fec_override_cap_10g_40g[0x4]; 9274 9275 u8 rs_fec_correction_bypass_admin[0x4]; 9276 u8 reserved_at_a4[0x8]; 9277 u8 fec_override_admin_56g[0x4]; 9278 u8 fec_override_admin_100g[0x4]; 9279 u8 fec_override_admin_50g[0x4]; 9280 u8 fec_override_admin_25g[0x4]; 9281 u8 fec_override_admin_10g_40g[0x4]; 9282 9283 u8 fec_override_cap_400g_8x[0x10]; 9284 u8 fec_override_cap_200g_4x[0x10]; 9285 9286 u8 fec_override_cap_100g_2x[0x10]; 9287 u8 fec_override_cap_50g_1x[0x10]; 9288 9289 u8 fec_override_admin_400g_8x[0x10]; 9290 u8 fec_override_admin_200g_4x[0x10]; 9291 9292 u8 fec_override_admin_100g_2x[0x10]; 9293 u8 fec_override_admin_50g_1x[0x10]; 9294 9295 u8 reserved_at_140[0x140]; 9296 }; 9297 9298 struct mlx5_ifc_ppcnt_reg_bits { 9299 u8 swid[0x8]; 9300 u8 local_port[0x8]; 9301 u8 pnat[0x2]; 9302 u8 reserved_at_12[0x8]; 9303 u8 grp[0x6]; 9304 9305 u8 clr[0x1]; 9306 u8 reserved_at_21[0x1c]; 9307 u8 prio_tc[0x3]; 9308 9309 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9310 }; 9311 9312 struct mlx5_ifc_mpein_reg_bits { 9313 u8 reserved_at_0[0x2]; 9314 u8 depth[0x6]; 9315 u8 pcie_index[0x8]; 9316 u8 node[0x8]; 9317 u8 reserved_at_18[0x8]; 9318 9319 u8 capability_mask[0x20]; 9320 9321 u8 reserved_at_40[0x8]; 9322 u8 link_width_enabled[0x8]; 9323 u8 link_speed_enabled[0x10]; 9324 9325 u8 lane0_physical_position[0x8]; 9326 u8 link_width_active[0x8]; 9327 u8 link_speed_active[0x10]; 9328 9329 u8 num_of_pfs[0x10]; 9330 u8 num_of_vfs[0x10]; 9331 9332 u8 bdf0[0x10]; 9333 u8 reserved_at_b0[0x10]; 9334 9335 u8 max_read_request_size[0x4]; 9336 u8 max_payload_size[0x4]; 9337 u8 reserved_at_c8[0x5]; 9338 u8 pwr_status[0x3]; 9339 u8 port_type[0x4]; 9340 u8 reserved_at_d4[0xb]; 9341 u8 lane_reversal[0x1]; 9342 9343 u8 reserved_at_e0[0x14]; 9344 u8 pci_power[0xc]; 9345 9346 u8 reserved_at_100[0x20]; 9347 9348 u8 device_status[0x10]; 9349 u8 port_state[0x8]; 9350 u8 reserved_at_138[0x8]; 9351 9352 u8 reserved_at_140[0x10]; 9353 u8 receiver_detect_result[0x10]; 9354 9355 u8 reserved_at_160[0x20]; 9356 }; 9357 9358 struct mlx5_ifc_mpcnt_reg_bits { 9359 u8 reserved_at_0[0x8]; 9360 u8 pcie_index[0x8]; 9361 u8 reserved_at_10[0xa]; 9362 u8 grp[0x6]; 9363 9364 u8 clr[0x1]; 9365 u8 reserved_at_21[0x1f]; 9366 9367 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9368 }; 9369 9370 struct mlx5_ifc_ppad_reg_bits { 9371 u8 reserved_at_0[0x3]; 9372 u8 single_mac[0x1]; 9373 u8 reserved_at_4[0x4]; 9374 u8 local_port[0x8]; 9375 u8 mac_47_32[0x10]; 9376 9377 u8 mac_31_0[0x20]; 9378 9379 u8 reserved_at_40[0x40]; 9380 }; 9381 9382 struct mlx5_ifc_pmtu_reg_bits { 9383 u8 reserved_at_0[0x8]; 9384 u8 local_port[0x8]; 9385 u8 reserved_at_10[0x10]; 9386 9387 u8 max_mtu[0x10]; 9388 u8 reserved_at_30[0x10]; 9389 9390 u8 admin_mtu[0x10]; 9391 u8 reserved_at_50[0x10]; 9392 9393 u8 oper_mtu[0x10]; 9394 u8 reserved_at_70[0x10]; 9395 }; 9396 9397 struct mlx5_ifc_pmpr_reg_bits { 9398 u8 reserved_at_0[0x8]; 9399 u8 module[0x8]; 9400 u8 reserved_at_10[0x10]; 9401 9402 u8 reserved_at_20[0x18]; 9403 u8 attenuation_5g[0x8]; 9404 9405 u8 reserved_at_40[0x18]; 9406 u8 attenuation_7g[0x8]; 9407 9408 u8 reserved_at_60[0x18]; 9409 u8 attenuation_12g[0x8]; 9410 }; 9411 9412 struct mlx5_ifc_pmpe_reg_bits { 9413 u8 reserved_at_0[0x8]; 9414 u8 module[0x8]; 9415 u8 reserved_at_10[0xc]; 9416 u8 module_status[0x4]; 9417 9418 u8 reserved_at_20[0x60]; 9419 }; 9420 9421 struct mlx5_ifc_pmpc_reg_bits { 9422 u8 module_state_updated[32][0x8]; 9423 }; 9424 9425 struct mlx5_ifc_pmlpn_reg_bits { 9426 u8 reserved_at_0[0x4]; 9427 u8 mlpn_status[0x4]; 9428 u8 local_port[0x8]; 9429 u8 reserved_at_10[0x10]; 9430 9431 u8 e[0x1]; 9432 u8 reserved_at_21[0x1f]; 9433 }; 9434 9435 struct mlx5_ifc_pmlp_reg_bits { 9436 u8 rxtx[0x1]; 9437 u8 reserved_at_1[0x7]; 9438 u8 local_port[0x8]; 9439 u8 reserved_at_10[0x8]; 9440 u8 width[0x8]; 9441 9442 u8 lane0_module_mapping[0x20]; 9443 9444 u8 lane1_module_mapping[0x20]; 9445 9446 u8 lane2_module_mapping[0x20]; 9447 9448 u8 lane3_module_mapping[0x20]; 9449 9450 u8 reserved_at_a0[0x160]; 9451 }; 9452 9453 struct mlx5_ifc_pmaos_reg_bits { 9454 u8 reserved_at_0[0x8]; 9455 u8 module[0x8]; 9456 u8 reserved_at_10[0x4]; 9457 u8 admin_status[0x4]; 9458 u8 reserved_at_18[0x4]; 9459 u8 oper_status[0x4]; 9460 9461 u8 ase[0x1]; 9462 u8 ee[0x1]; 9463 u8 reserved_at_22[0x1c]; 9464 u8 e[0x2]; 9465 9466 u8 reserved_at_40[0x40]; 9467 }; 9468 9469 struct mlx5_ifc_plpc_reg_bits { 9470 u8 reserved_at_0[0x4]; 9471 u8 profile_id[0xc]; 9472 u8 reserved_at_10[0x4]; 9473 u8 proto_mask[0x4]; 9474 u8 reserved_at_18[0x8]; 9475 9476 u8 reserved_at_20[0x10]; 9477 u8 lane_speed[0x10]; 9478 9479 u8 reserved_at_40[0x17]; 9480 u8 lpbf[0x1]; 9481 u8 fec_mode_policy[0x8]; 9482 9483 u8 retransmission_capability[0x8]; 9484 u8 fec_mode_capability[0x18]; 9485 9486 u8 retransmission_support_admin[0x8]; 9487 u8 fec_mode_support_admin[0x18]; 9488 9489 u8 retransmission_request_admin[0x8]; 9490 u8 fec_mode_request_admin[0x18]; 9491 9492 u8 reserved_at_c0[0x80]; 9493 }; 9494 9495 struct mlx5_ifc_plib_reg_bits { 9496 u8 reserved_at_0[0x8]; 9497 u8 local_port[0x8]; 9498 u8 reserved_at_10[0x8]; 9499 u8 ib_port[0x8]; 9500 9501 u8 reserved_at_20[0x60]; 9502 }; 9503 9504 struct mlx5_ifc_plbf_reg_bits { 9505 u8 reserved_at_0[0x8]; 9506 u8 local_port[0x8]; 9507 u8 reserved_at_10[0xd]; 9508 u8 lbf_mode[0x3]; 9509 9510 u8 reserved_at_20[0x20]; 9511 }; 9512 9513 struct mlx5_ifc_pipg_reg_bits { 9514 u8 reserved_at_0[0x8]; 9515 u8 local_port[0x8]; 9516 u8 reserved_at_10[0x10]; 9517 9518 u8 dic[0x1]; 9519 u8 reserved_at_21[0x19]; 9520 u8 ipg[0x4]; 9521 u8 reserved_at_3e[0x2]; 9522 }; 9523 9524 struct mlx5_ifc_pifr_reg_bits { 9525 u8 reserved_at_0[0x8]; 9526 u8 local_port[0x8]; 9527 u8 reserved_at_10[0x10]; 9528 9529 u8 reserved_at_20[0xe0]; 9530 9531 u8 port_filter[8][0x20]; 9532 9533 u8 port_filter_update_en[8][0x20]; 9534 }; 9535 9536 struct mlx5_ifc_pfcc_reg_bits { 9537 u8 reserved_at_0[0x8]; 9538 u8 local_port[0x8]; 9539 u8 reserved_at_10[0xb]; 9540 u8 ppan_mask_n[0x1]; 9541 u8 minor_stall_mask[0x1]; 9542 u8 critical_stall_mask[0x1]; 9543 u8 reserved_at_1e[0x2]; 9544 9545 u8 ppan[0x4]; 9546 u8 reserved_at_24[0x4]; 9547 u8 prio_mask_tx[0x8]; 9548 u8 reserved_at_30[0x8]; 9549 u8 prio_mask_rx[0x8]; 9550 9551 u8 pptx[0x1]; 9552 u8 aptx[0x1]; 9553 u8 pptx_mask_n[0x1]; 9554 u8 reserved_at_43[0x5]; 9555 u8 pfctx[0x8]; 9556 u8 reserved_at_50[0x10]; 9557 9558 u8 pprx[0x1]; 9559 u8 aprx[0x1]; 9560 u8 pprx_mask_n[0x1]; 9561 u8 reserved_at_63[0x5]; 9562 u8 pfcrx[0x8]; 9563 u8 reserved_at_70[0x10]; 9564 9565 u8 device_stall_minor_watermark[0x10]; 9566 u8 device_stall_critical_watermark[0x10]; 9567 9568 u8 reserved_at_a0[0x60]; 9569 }; 9570 9571 struct mlx5_ifc_pelc_reg_bits { 9572 u8 op[0x4]; 9573 u8 reserved_at_4[0x4]; 9574 u8 local_port[0x8]; 9575 u8 reserved_at_10[0x10]; 9576 9577 u8 op_admin[0x8]; 9578 u8 op_capability[0x8]; 9579 u8 op_request[0x8]; 9580 u8 op_active[0x8]; 9581 9582 u8 admin[0x40]; 9583 9584 u8 capability[0x40]; 9585 9586 u8 request[0x40]; 9587 9588 u8 active[0x40]; 9589 9590 u8 reserved_at_140[0x80]; 9591 }; 9592 9593 struct mlx5_ifc_peir_reg_bits { 9594 u8 reserved_at_0[0x8]; 9595 u8 local_port[0x8]; 9596 u8 reserved_at_10[0x10]; 9597 9598 u8 reserved_at_20[0xc]; 9599 u8 error_count[0x4]; 9600 u8 reserved_at_30[0x10]; 9601 9602 u8 reserved_at_40[0xc]; 9603 u8 lane[0x4]; 9604 u8 reserved_at_50[0x8]; 9605 u8 error_type[0x8]; 9606 }; 9607 9608 struct mlx5_ifc_mpegc_reg_bits { 9609 u8 reserved_at_0[0x30]; 9610 u8 field_select[0x10]; 9611 9612 u8 tx_overflow_sense[0x1]; 9613 u8 mark_cqe[0x1]; 9614 u8 mark_cnp[0x1]; 9615 u8 reserved_at_43[0x1b]; 9616 u8 tx_lossy_overflow_oper[0x2]; 9617 9618 u8 reserved_at_60[0x100]; 9619 }; 9620 9621 enum { 9622 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9623 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9624 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9625 }; 9626 9627 struct mlx5_ifc_mtutc_reg_bits { 9628 u8 reserved_at_0[0x1c]; 9629 u8 operation[0x4]; 9630 9631 u8 freq_adjustment[0x20]; 9632 9633 u8 reserved_at_40[0x40]; 9634 9635 u8 utc_sec[0x20]; 9636 9637 u8 reserved_at_a0[0x2]; 9638 u8 utc_nsec[0x1e]; 9639 9640 u8 time_adjustment[0x20]; 9641 }; 9642 9643 struct mlx5_ifc_pcam_enhanced_features_bits { 9644 u8 reserved_at_0[0x68]; 9645 u8 fec_50G_per_lane_in_pplm[0x1]; 9646 u8 reserved_at_69[0x4]; 9647 u8 rx_icrc_encapsulated_counter[0x1]; 9648 u8 reserved_at_6e[0x4]; 9649 u8 ptys_extended_ethernet[0x1]; 9650 u8 reserved_at_73[0x3]; 9651 u8 pfcc_mask[0x1]; 9652 u8 reserved_at_77[0x3]; 9653 u8 per_lane_error_counters[0x1]; 9654 u8 rx_buffer_fullness_counters[0x1]; 9655 u8 ptys_connector_type[0x1]; 9656 u8 reserved_at_7d[0x1]; 9657 u8 ppcnt_discard_group[0x1]; 9658 u8 ppcnt_statistical_group[0x1]; 9659 }; 9660 9661 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9662 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9663 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9664 9665 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9666 u8 pplm[0x1]; 9667 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9668 9669 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9670 u8 pbmc[0x1]; 9671 u8 pptb[0x1]; 9672 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9673 u8 ppcnt[0x1]; 9674 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9675 }; 9676 9677 struct mlx5_ifc_pcam_reg_bits { 9678 u8 reserved_at_0[0x8]; 9679 u8 feature_group[0x8]; 9680 u8 reserved_at_10[0x8]; 9681 u8 access_reg_group[0x8]; 9682 9683 u8 reserved_at_20[0x20]; 9684 9685 union { 9686 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9687 u8 reserved_at_0[0x80]; 9688 } port_access_reg_cap_mask; 9689 9690 u8 reserved_at_c0[0x80]; 9691 9692 union { 9693 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9694 u8 reserved_at_0[0x80]; 9695 } feature_cap_mask; 9696 9697 u8 reserved_at_1c0[0xc0]; 9698 }; 9699 9700 struct mlx5_ifc_mcam_enhanced_features_bits { 9701 u8 reserved_at_0[0x5d]; 9702 u8 mcia_32dwords[0x1]; 9703 u8 reserved_at_5e[0xc]; 9704 u8 reset_state[0x1]; 9705 u8 ptpcyc2realtime_modify[0x1]; 9706 u8 reserved_at_6c[0x2]; 9707 u8 pci_status_and_power[0x1]; 9708 u8 reserved_at_6f[0x5]; 9709 u8 mark_tx_action_cnp[0x1]; 9710 u8 mark_tx_action_cqe[0x1]; 9711 u8 dynamic_tx_overflow[0x1]; 9712 u8 reserved_at_77[0x4]; 9713 u8 pcie_outbound_stalled[0x1]; 9714 u8 tx_overflow_buffer_pkt[0x1]; 9715 u8 mtpps_enh_out_per_adj[0x1]; 9716 u8 mtpps_fs[0x1]; 9717 u8 pcie_performance_group[0x1]; 9718 }; 9719 9720 struct mlx5_ifc_mcam_access_reg_bits { 9721 u8 reserved_at_0[0x1c]; 9722 u8 mcda[0x1]; 9723 u8 mcc[0x1]; 9724 u8 mcqi[0x1]; 9725 u8 mcqs[0x1]; 9726 9727 u8 regs_95_to_87[0x9]; 9728 u8 mpegc[0x1]; 9729 u8 mtutc[0x1]; 9730 u8 regs_84_to_68[0x11]; 9731 u8 tracer_registers[0x4]; 9732 9733 u8 regs_63_to_46[0x12]; 9734 u8 mrtc[0x1]; 9735 u8 regs_44_to_32[0xd]; 9736 9737 u8 regs_31_to_0[0x20]; 9738 }; 9739 9740 struct mlx5_ifc_mcam_access_reg_bits1 { 9741 u8 regs_127_to_96[0x20]; 9742 9743 u8 regs_95_to_64[0x20]; 9744 9745 u8 regs_63_to_32[0x20]; 9746 9747 u8 regs_31_to_0[0x20]; 9748 }; 9749 9750 struct mlx5_ifc_mcam_access_reg_bits2 { 9751 u8 regs_127_to_99[0x1d]; 9752 u8 mirc[0x1]; 9753 u8 regs_97_to_96[0x2]; 9754 9755 u8 regs_95_to_64[0x20]; 9756 9757 u8 regs_63_to_32[0x20]; 9758 9759 u8 regs_31_to_0[0x20]; 9760 }; 9761 9762 struct mlx5_ifc_mcam_reg_bits { 9763 u8 reserved_at_0[0x8]; 9764 u8 feature_group[0x8]; 9765 u8 reserved_at_10[0x8]; 9766 u8 access_reg_group[0x8]; 9767 9768 u8 reserved_at_20[0x20]; 9769 9770 union { 9771 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9772 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9773 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9774 u8 reserved_at_0[0x80]; 9775 } mng_access_reg_cap_mask; 9776 9777 u8 reserved_at_c0[0x80]; 9778 9779 union { 9780 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9781 u8 reserved_at_0[0x80]; 9782 } mng_feature_cap_mask; 9783 9784 u8 reserved_at_1c0[0x80]; 9785 }; 9786 9787 struct mlx5_ifc_qcam_access_reg_cap_mask { 9788 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9789 u8 qpdpm[0x1]; 9790 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9791 u8 qdpm[0x1]; 9792 u8 qpts[0x1]; 9793 u8 qcap[0x1]; 9794 u8 qcam_access_reg_cap_mask_0[0x1]; 9795 }; 9796 9797 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9798 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9799 u8 qpts_trust_both[0x1]; 9800 }; 9801 9802 struct mlx5_ifc_qcam_reg_bits { 9803 u8 reserved_at_0[0x8]; 9804 u8 feature_group[0x8]; 9805 u8 reserved_at_10[0x8]; 9806 u8 access_reg_group[0x8]; 9807 u8 reserved_at_20[0x20]; 9808 9809 union { 9810 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9811 u8 reserved_at_0[0x80]; 9812 } qos_access_reg_cap_mask; 9813 9814 u8 reserved_at_c0[0x80]; 9815 9816 union { 9817 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9818 u8 reserved_at_0[0x80]; 9819 } qos_feature_cap_mask; 9820 9821 u8 reserved_at_1c0[0x80]; 9822 }; 9823 9824 struct mlx5_ifc_core_dump_reg_bits { 9825 u8 reserved_at_0[0x18]; 9826 u8 core_dump_type[0x8]; 9827 9828 u8 reserved_at_20[0x30]; 9829 u8 vhca_id[0x10]; 9830 9831 u8 reserved_at_60[0x8]; 9832 u8 qpn[0x18]; 9833 u8 reserved_at_80[0x180]; 9834 }; 9835 9836 struct mlx5_ifc_pcap_reg_bits { 9837 u8 reserved_at_0[0x8]; 9838 u8 local_port[0x8]; 9839 u8 reserved_at_10[0x10]; 9840 9841 u8 port_capability_mask[4][0x20]; 9842 }; 9843 9844 struct mlx5_ifc_paos_reg_bits { 9845 u8 swid[0x8]; 9846 u8 local_port[0x8]; 9847 u8 reserved_at_10[0x4]; 9848 u8 admin_status[0x4]; 9849 u8 reserved_at_18[0x4]; 9850 u8 oper_status[0x4]; 9851 9852 u8 ase[0x1]; 9853 u8 ee[0x1]; 9854 u8 reserved_at_22[0x1c]; 9855 u8 e[0x2]; 9856 9857 u8 reserved_at_40[0x40]; 9858 }; 9859 9860 struct mlx5_ifc_pamp_reg_bits { 9861 u8 reserved_at_0[0x8]; 9862 u8 opamp_group[0x8]; 9863 u8 reserved_at_10[0xc]; 9864 u8 opamp_group_type[0x4]; 9865 9866 u8 start_index[0x10]; 9867 u8 reserved_at_30[0x4]; 9868 u8 num_of_indices[0xc]; 9869 9870 u8 index_data[18][0x10]; 9871 }; 9872 9873 struct mlx5_ifc_pcmr_reg_bits { 9874 u8 reserved_at_0[0x8]; 9875 u8 local_port[0x8]; 9876 u8 reserved_at_10[0x10]; 9877 9878 u8 entropy_force_cap[0x1]; 9879 u8 entropy_calc_cap[0x1]; 9880 u8 entropy_gre_calc_cap[0x1]; 9881 u8 reserved_at_23[0xf]; 9882 u8 rx_ts_over_crc_cap[0x1]; 9883 u8 reserved_at_33[0xb]; 9884 u8 fcs_cap[0x1]; 9885 u8 reserved_at_3f[0x1]; 9886 9887 u8 entropy_force[0x1]; 9888 u8 entropy_calc[0x1]; 9889 u8 entropy_gre_calc[0x1]; 9890 u8 reserved_at_43[0xf]; 9891 u8 rx_ts_over_crc[0x1]; 9892 u8 reserved_at_53[0xb]; 9893 u8 fcs_chk[0x1]; 9894 u8 reserved_at_5f[0x1]; 9895 }; 9896 9897 struct mlx5_ifc_lane_2_module_mapping_bits { 9898 u8 reserved_at_0[0x4]; 9899 u8 rx_lane[0x4]; 9900 u8 reserved_at_8[0x4]; 9901 u8 tx_lane[0x4]; 9902 u8 reserved_at_10[0x8]; 9903 u8 module[0x8]; 9904 }; 9905 9906 struct mlx5_ifc_bufferx_reg_bits { 9907 u8 reserved_at_0[0x6]; 9908 u8 lossy[0x1]; 9909 u8 epsb[0x1]; 9910 u8 reserved_at_8[0x8]; 9911 u8 size[0x10]; 9912 9913 u8 xoff_threshold[0x10]; 9914 u8 xon_threshold[0x10]; 9915 }; 9916 9917 struct mlx5_ifc_set_node_in_bits { 9918 u8 node_description[64][0x8]; 9919 }; 9920 9921 struct mlx5_ifc_register_power_settings_bits { 9922 u8 reserved_at_0[0x18]; 9923 u8 power_settings_level[0x8]; 9924 9925 u8 reserved_at_20[0x60]; 9926 }; 9927 9928 struct mlx5_ifc_register_host_endianness_bits { 9929 u8 he[0x1]; 9930 u8 reserved_at_1[0x1f]; 9931 9932 u8 reserved_at_20[0x60]; 9933 }; 9934 9935 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9936 u8 reserved_at_0[0x20]; 9937 9938 u8 mkey[0x20]; 9939 9940 u8 addressh_63_32[0x20]; 9941 9942 u8 addressl_31_0[0x20]; 9943 }; 9944 9945 struct mlx5_ifc_ud_adrs_vector_bits { 9946 u8 dc_key[0x40]; 9947 9948 u8 ext[0x1]; 9949 u8 reserved_at_41[0x7]; 9950 u8 destination_qp_dct[0x18]; 9951 9952 u8 static_rate[0x4]; 9953 u8 sl_eth_prio[0x4]; 9954 u8 fl[0x1]; 9955 u8 mlid[0x7]; 9956 u8 rlid_udp_sport[0x10]; 9957 9958 u8 reserved_at_80[0x20]; 9959 9960 u8 rmac_47_16[0x20]; 9961 9962 u8 rmac_15_0[0x10]; 9963 u8 tclass[0x8]; 9964 u8 hop_limit[0x8]; 9965 9966 u8 reserved_at_e0[0x1]; 9967 u8 grh[0x1]; 9968 u8 reserved_at_e2[0x2]; 9969 u8 src_addr_index[0x8]; 9970 u8 flow_label[0x14]; 9971 9972 u8 rgid_rip[16][0x8]; 9973 }; 9974 9975 struct mlx5_ifc_pages_req_event_bits { 9976 u8 reserved_at_0[0x10]; 9977 u8 function_id[0x10]; 9978 9979 u8 num_pages[0x20]; 9980 9981 u8 reserved_at_40[0xa0]; 9982 }; 9983 9984 struct mlx5_ifc_eqe_bits { 9985 u8 reserved_at_0[0x8]; 9986 u8 event_type[0x8]; 9987 u8 reserved_at_10[0x8]; 9988 u8 event_sub_type[0x8]; 9989 9990 u8 reserved_at_20[0xe0]; 9991 9992 union mlx5_ifc_event_auto_bits event_data; 9993 9994 u8 reserved_at_1e0[0x10]; 9995 u8 signature[0x8]; 9996 u8 reserved_at_1f8[0x7]; 9997 u8 owner[0x1]; 9998 }; 9999 10000 enum { 10001 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10002 }; 10003 10004 struct mlx5_ifc_cmd_queue_entry_bits { 10005 u8 type[0x8]; 10006 u8 reserved_at_8[0x18]; 10007 10008 u8 input_length[0x20]; 10009 10010 u8 input_mailbox_pointer_63_32[0x20]; 10011 10012 u8 input_mailbox_pointer_31_9[0x17]; 10013 u8 reserved_at_77[0x9]; 10014 10015 u8 command_input_inline_data[16][0x8]; 10016 10017 u8 command_output_inline_data[16][0x8]; 10018 10019 u8 output_mailbox_pointer_63_32[0x20]; 10020 10021 u8 output_mailbox_pointer_31_9[0x17]; 10022 u8 reserved_at_1b7[0x9]; 10023 10024 u8 output_length[0x20]; 10025 10026 u8 token[0x8]; 10027 u8 signature[0x8]; 10028 u8 reserved_at_1f0[0x8]; 10029 u8 status[0x7]; 10030 u8 ownership[0x1]; 10031 }; 10032 10033 struct mlx5_ifc_cmd_out_bits { 10034 u8 status[0x8]; 10035 u8 reserved_at_8[0x18]; 10036 10037 u8 syndrome[0x20]; 10038 10039 u8 command_output[0x20]; 10040 }; 10041 10042 struct mlx5_ifc_cmd_in_bits { 10043 u8 opcode[0x10]; 10044 u8 reserved_at_10[0x10]; 10045 10046 u8 reserved_at_20[0x10]; 10047 u8 op_mod[0x10]; 10048 10049 u8 command[][0x20]; 10050 }; 10051 10052 struct mlx5_ifc_cmd_if_box_bits { 10053 u8 mailbox_data[512][0x8]; 10054 10055 u8 reserved_at_1000[0x180]; 10056 10057 u8 next_pointer_63_32[0x20]; 10058 10059 u8 next_pointer_31_10[0x16]; 10060 u8 reserved_at_11b6[0xa]; 10061 10062 u8 block_number[0x20]; 10063 10064 u8 reserved_at_11e0[0x8]; 10065 u8 token[0x8]; 10066 u8 ctrl_signature[0x8]; 10067 u8 signature[0x8]; 10068 }; 10069 10070 struct mlx5_ifc_mtt_bits { 10071 u8 ptag_63_32[0x20]; 10072 10073 u8 ptag_31_8[0x18]; 10074 u8 reserved_at_38[0x6]; 10075 u8 wr_en[0x1]; 10076 u8 rd_en[0x1]; 10077 }; 10078 10079 struct mlx5_ifc_query_wol_rol_out_bits { 10080 u8 status[0x8]; 10081 u8 reserved_at_8[0x18]; 10082 10083 u8 syndrome[0x20]; 10084 10085 u8 reserved_at_40[0x10]; 10086 u8 rol_mode[0x8]; 10087 u8 wol_mode[0x8]; 10088 10089 u8 reserved_at_60[0x20]; 10090 }; 10091 10092 struct mlx5_ifc_query_wol_rol_in_bits { 10093 u8 opcode[0x10]; 10094 u8 reserved_at_10[0x10]; 10095 10096 u8 reserved_at_20[0x10]; 10097 u8 op_mod[0x10]; 10098 10099 u8 reserved_at_40[0x40]; 10100 }; 10101 10102 struct mlx5_ifc_set_wol_rol_out_bits { 10103 u8 status[0x8]; 10104 u8 reserved_at_8[0x18]; 10105 10106 u8 syndrome[0x20]; 10107 10108 u8 reserved_at_40[0x40]; 10109 }; 10110 10111 struct mlx5_ifc_set_wol_rol_in_bits { 10112 u8 opcode[0x10]; 10113 u8 reserved_at_10[0x10]; 10114 10115 u8 reserved_at_20[0x10]; 10116 u8 op_mod[0x10]; 10117 10118 u8 rol_mode_valid[0x1]; 10119 u8 wol_mode_valid[0x1]; 10120 u8 reserved_at_42[0xe]; 10121 u8 rol_mode[0x8]; 10122 u8 wol_mode[0x8]; 10123 10124 u8 reserved_at_60[0x20]; 10125 }; 10126 10127 enum { 10128 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10129 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10130 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10131 }; 10132 10133 enum { 10134 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10135 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10136 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10137 }; 10138 10139 enum { 10140 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10141 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10142 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10143 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10144 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10145 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10146 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10147 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10148 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10149 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10150 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10151 }; 10152 10153 struct mlx5_ifc_initial_seg_bits { 10154 u8 fw_rev_minor[0x10]; 10155 u8 fw_rev_major[0x10]; 10156 10157 u8 cmd_interface_rev[0x10]; 10158 u8 fw_rev_subminor[0x10]; 10159 10160 u8 reserved_at_40[0x40]; 10161 10162 u8 cmdq_phy_addr_63_32[0x20]; 10163 10164 u8 cmdq_phy_addr_31_12[0x14]; 10165 u8 reserved_at_b4[0x2]; 10166 u8 nic_interface[0x2]; 10167 u8 log_cmdq_size[0x4]; 10168 u8 log_cmdq_stride[0x4]; 10169 10170 u8 command_doorbell_vector[0x20]; 10171 10172 u8 reserved_at_e0[0xf00]; 10173 10174 u8 initializing[0x1]; 10175 u8 reserved_at_fe1[0x4]; 10176 u8 nic_interface_supported[0x3]; 10177 u8 embedded_cpu[0x1]; 10178 u8 reserved_at_fe9[0x17]; 10179 10180 struct mlx5_ifc_health_buffer_bits health_buffer; 10181 10182 u8 no_dram_nic_offset[0x20]; 10183 10184 u8 reserved_at_1220[0x6e40]; 10185 10186 u8 reserved_at_8060[0x1f]; 10187 u8 clear_int[0x1]; 10188 10189 u8 health_syndrome[0x8]; 10190 u8 health_counter[0x18]; 10191 10192 u8 reserved_at_80a0[0x17fc0]; 10193 }; 10194 10195 struct mlx5_ifc_mtpps_reg_bits { 10196 u8 reserved_at_0[0xc]; 10197 u8 cap_number_of_pps_pins[0x4]; 10198 u8 reserved_at_10[0x4]; 10199 u8 cap_max_num_of_pps_in_pins[0x4]; 10200 u8 reserved_at_18[0x4]; 10201 u8 cap_max_num_of_pps_out_pins[0x4]; 10202 10203 u8 reserved_at_20[0x24]; 10204 u8 cap_pin_3_mode[0x4]; 10205 u8 reserved_at_48[0x4]; 10206 u8 cap_pin_2_mode[0x4]; 10207 u8 reserved_at_50[0x4]; 10208 u8 cap_pin_1_mode[0x4]; 10209 u8 reserved_at_58[0x4]; 10210 u8 cap_pin_0_mode[0x4]; 10211 10212 u8 reserved_at_60[0x4]; 10213 u8 cap_pin_7_mode[0x4]; 10214 u8 reserved_at_68[0x4]; 10215 u8 cap_pin_6_mode[0x4]; 10216 u8 reserved_at_70[0x4]; 10217 u8 cap_pin_5_mode[0x4]; 10218 u8 reserved_at_78[0x4]; 10219 u8 cap_pin_4_mode[0x4]; 10220 10221 u8 field_select[0x20]; 10222 u8 reserved_at_a0[0x60]; 10223 10224 u8 enable[0x1]; 10225 u8 reserved_at_101[0xb]; 10226 u8 pattern[0x4]; 10227 u8 reserved_at_110[0x4]; 10228 u8 pin_mode[0x4]; 10229 u8 pin[0x8]; 10230 10231 u8 reserved_at_120[0x20]; 10232 10233 u8 time_stamp[0x40]; 10234 10235 u8 out_pulse_duration[0x10]; 10236 u8 out_periodic_adjustment[0x10]; 10237 u8 enhanced_out_periodic_adjustment[0x20]; 10238 10239 u8 reserved_at_1c0[0x20]; 10240 }; 10241 10242 struct mlx5_ifc_mtppse_reg_bits { 10243 u8 reserved_at_0[0x18]; 10244 u8 pin[0x8]; 10245 u8 event_arm[0x1]; 10246 u8 reserved_at_21[0x1b]; 10247 u8 event_generation_mode[0x4]; 10248 u8 reserved_at_40[0x40]; 10249 }; 10250 10251 struct mlx5_ifc_mcqs_reg_bits { 10252 u8 last_index_flag[0x1]; 10253 u8 reserved_at_1[0x7]; 10254 u8 fw_device[0x8]; 10255 u8 component_index[0x10]; 10256 10257 u8 reserved_at_20[0x10]; 10258 u8 identifier[0x10]; 10259 10260 u8 reserved_at_40[0x17]; 10261 u8 component_status[0x5]; 10262 u8 component_update_state[0x4]; 10263 10264 u8 last_update_state_changer_type[0x4]; 10265 u8 last_update_state_changer_host_id[0x4]; 10266 u8 reserved_at_68[0x18]; 10267 }; 10268 10269 struct mlx5_ifc_mcqi_cap_bits { 10270 u8 supported_info_bitmask[0x20]; 10271 10272 u8 component_size[0x20]; 10273 10274 u8 max_component_size[0x20]; 10275 10276 u8 log_mcda_word_size[0x4]; 10277 u8 reserved_at_64[0xc]; 10278 u8 mcda_max_write_size[0x10]; 10279 10280 u8 rd_en[0x1]; 10281 u8 reserved_at_81[0x1]; 10282 u8 match_chip_id[0x1]; 10283 u8 match_psid[0x1]; 10284 u8 check_user_timestamp[0x1]; 10285 u8 match_base_guid_mac[0x1]; 10286 u8 reserved_at_86[0x1a]; 10287 }; 10288 10289 struct mlx5_ifc_mcqi_version_bits { 10290 u8 reserved_at_0[0x2]; 10291 u8 build_time_valid[0x1]; 10292 u8 user_defined_time_valid[0x1]; 10293 u8 reserved_at_4[0x14]; 10294 u8 version_string_length[0x8]; 10295 10296 u8 version[0x20]; 10297 10298 u8 build_time[0x40]; 10299 10300 u8 user_defined_time[0x40]; 10301 10302 u8 build_tool_version[0x20]; 10303 10304 u8 reserved_at_e0[0x20]; 10305 10306 u8 version_string[92][0x8]; 10307 }; 10308 10309 struct mlx5_ifc_mcqi_activation_method_bits { 10310 u8 pending_server_ac_power_cycle[0x1]; 10311 u8 pending_server_dc_power_cycle[0x1]; 10312 u8 pending_server_reboot[0x1]; 10313 u8 pending_fw_reset[0x1]; 10314 u8 auto_activate[0x1]; 10315 u8 all_hosts_sync[0x1]; 10316 u8 device_hw_reset[0x1]; 10317 u8 reserved_at_7[0x19]; 10318 }; 10319 10320 union mlx5_ifc_mcqi_reg_data_bits { 10321 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10322 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10323 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10324 }; 10325 10326 struct mlx5_ifc_mcqi_reg_bits { 10327 u8 read_pending_component[0x1]; 10328 u8 reserved_at_1[0xf]; 10329 u8 component_index[0x10]; 10330 10331 u8 reserved_at_20[0x20]; 10332 10333 u8 reserved_at_40[0x1b]; 10334 u8 info_type[0x5]; 10335 10336 u8 info_size[0x20]; 10337 10338 u8 offset[0x20]; 10339 10340 u8 reserved_at_a0[0x10]; 10341 u8 data_size[0x10]; 10342 10343 union mlx5_ifc_mcqi_reg_data_bits data[]; 10344 }; 10345 10346 struct mlx5_ifc_mcc_reg_bits { 10347 u8 reserved_at_0[0x4]; 10348 u8 time_elapsed_since_last_cmd[0xc]; 10349 u8 reserved_at_10[0x8]; 10350 u8 instruction[0x8]; 10351 10352 u8 reserved_at_20[0x10]; 10353 u8 component_index[0x10]; 10354 10355 u8 reserved_at_40[0x8]; 10356 u8 update_handle[0x18]; 10357 10358 u8 handle_owner_type[0x4]; 10359 u8 handle_owner_host_id[0x4]; 10360 u8 reserved_at_68[0x1]; 10361 u8 control_progress[0x7]; 10362 u8 error_code[0x8]; 10363 u8 reserved_at_78[0x4]; 10364 u8 control_state[0x4]; 10365 10366 u8 component_size[0x20]; 10367 10368 u8 reserved_at_a0[0x60]; 10369 }; 10370 10371 struct mlx5_ifc_mcda_reg_bits { 10372 u8 reserved_at_0[0x8]; 10373 u8 update_handle[0x18]; 10374 10375 u8 offset[0x20]; 10376 10377 u8 reserved_at_40[0x10]; 10378 u8 size[0x10]; 10379 10380 u8 reserved_at_60[0x20]; 10381 10382 u8 data[][0x20]; 10383 }; 10384 10385 enum { 10386 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10387 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10388 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10389 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10390 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10391 }; 10392 10393 enum { 10394 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10395 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10396 }; 10397 10398 enum { 10399 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10400 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10401 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10402 }; 10403 10404 struct mlx5_ifc_mfrl_reg_bits { 10405 u8 reserved_at_0[0x20]; 10406 10407 u8 reserved_at_20[0x2]; 10408 u8 pci_sync_for_fw_update_start[0x1]; 10409 u8 pci_sync_for_fw_update_resp[0x2]; 10410 u8 rst_type_sel[0x3]; 10411 u8 reserved_at_28[0x4]; 10412 u8 reset_state[0x4]; 10413 u8 reset_type[0x8]; 10414 u8 reset_level[0x8]; 10415 }; 10416 10417 struct mlx5_ifc_mirc_reg_bits { 10418 u8 reserved_at_0[0x18]; 10419 u8 status_code[0x8]; 10420 10421 u8 reserved_at_20[0x20]; 10422 }; 10423 10424 struct mlx5_ifc_pddr_monitor_opcode_bits { 10425 u8 reserved_at_0[0x10]; 10426 u8 monitor_opcode[0x10]; 10427 }; 10428 10429 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10430 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10431 u8 reserved_at_0[0x20]; 10432 }; 10433 10434 enum { 10435 /* Monitor opcodes */ 10436 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10437 }; 10438 10439 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10440 u8 reserved_at_0[0x10]; 10441 u8 group_opcode[0x10]; 10442 10443 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10444 10445 u8 reserved_at_40[0x20]; 10446 10447 u8 status_message[59][0x20]; 10448 }; 10449 10450 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10451 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10452 u8 reserved_at_0[0x7c0]; 10453 }; 10454 10455 enum { 10456 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10457 }; 10458 10459 struct mlx5_ifc_pddr_reg_bits { 10460 u8 reserved_at_0[0x8]; 10461 u8 local_port[0x8]; 10462 u8 pnat[0x2]; 10463 u8 reserved_at_12[0xe]; 10464 10465 u8 reserved_at_20[0x18]; 10466 u8 page_select[0x8]; 10467 10468 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10469 }; 10470 10471 struct mlx5_ifc_mrtc_reg_bits { 10472 u8 time_synced[0x1]; 10473 u8 reserved_at_1[0x1f]; 10474 10475 u8 reserved_at_20[0x20]; 10476 10477 u8 time_h[0x20]; 10478 10479 u8 time_l[0x20]; 10480 }; 10481 10482 union mlx5_ifc_ports_control_registers_document_bits { 10483 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10484 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10485 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10486 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10487 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10488 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10489 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10490 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10491 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10492 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10493 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10494 struct mlx5_ifc_paos_reg_bits paos_reg; 10495 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10496 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10497 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10498 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10499 struct mlx5_ifc_peir_reg_bits peir_reg; 10500 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10501 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10502 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10503 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10504 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10505 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10506 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10507 struct mlx5_ifc_plib_reg_bits plib_reg; 10508 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10509 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10510 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10511 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10512 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10513 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10514 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10515 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10516 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10517 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10518 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10519 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10520 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10521 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10522 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10523 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10524 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10525 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10526 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10527 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10528 struct mlx5_ifc_pude_reg_bits pude_reg; 10529 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10530 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10531 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10532 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10533 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10534 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10535 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10536 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10537 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10538 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10539 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10540 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10541 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10542 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10543 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10544 u8 reserved_at_0[0x60e0]; 10545 }; 10546 10547 union mlx5_ifc_debug_enhancements_document_bits { 10548 struct mlx5_ifc_health_buffer_bits health_buffer; 10549 u8 reserved_at_0[0x200]; 10550 }; 10551 10552 union mlx5_ifc_uplink_pci_interface_document_bits { 10553 struct mlx5_ifc_initial_seg_bits initial_seg; 10554 u8 reserved_at_0[0x20060]; 10555 }; 10556 10557 struct mlx5_ifc_set_flow_table_root_out_bits { 10558 u8 status[0x8]; 10559 u8 reserved_at_8[0x18]; 10560 10561 u8 syndrome[0x20]; 10562 10563 u8 reserved_at_40[0x40]; 10564 }; 10565 10566 struct mlx5_ifc_set_flow_table_root_in_bits { 10567 u8 opcode[0x10]; 10568 u8 reserved_at_10[0x10]; 10569 10570 u8 reserved_at_20[0x10]; 10571 u8 op_mod[0x10]; 10572 10573 u8 other_vport[0x1]; 10574 u8 reserved_at_41[0xf]; 10575 u8 vport_number[0x10]; 10576 10577 u8 reserved_at_60[0x20]; 10578 10579 u8 table_type[0x8]; 10580 u8 reserved_at_88[0x7]; 10581 u8 table_of_other_vport[0x1]; 10582 u8 table_vport_number[0x10]; 10583 10584 u8 reserved_at_a0[0x8]; 10585 u8 table_id[0x18]; 10586 10587 u8 reserved_at_c0[0x8]; 10588 u8 underlay_qpn[0x18]; 10589 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10590 u8 reserved_at_e1[0xf]; 10591 u8 table_eswitch_owner_vhca_id[0x10]; 10592 u8 reserved_at_100[0x100]; 10593 }; 10594 10595 enum { 10596 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10597 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10598 }; 10599 10600 struct mlx5_ifc_modify_flow_table_out_bits { 10601 u8 status[0x8]; 10602 u8 reserved_at_8[0x18]; 10603 10604 u8 syndrome[0x20]; 10605 10606 u8 reserved_at_40[0x40]; 10607 }; 10608 10609 struct mlx5_ifc_modify_flow_table_in_bits { 10610 u8 opcode[0x10]; 10611 u8 reserved_at_10[0x10]; 10612 10613 u8 reserved_at_20[0x10]; 10614 u8 op_mod[0x10]; 10615 10616 u8 other_vport[0x1]; 10617 u8 reserved_at_41[0xf]; 10618 u8 vport_number[0x10]; 10619 10620 u8 reserved_at_60[0x10]; 10621 u8 modify_field_select[0x10]; 10622 10623 u8 table_type[0x8]; 10624 u8 reserved_at_88[0x18]; 10625 10626 u8 reserved_at_a0[0x8]; 10627 u8 table_id[0x18]; 10628 10629 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10630 }; 10631 10632 struct mlx5_ifc_ets_tcn_config_reg_bits { 10633 u8 g[0x1]; 10634 u8 b[0x1]; 10635 u8 r[0x1]; 10636 u8 reserved_at_3[0x9]; 10637 u8 group[0x4]; 10638 u8 reserved_at_10[0x9]; 10639 u8 bw_allocation[0x7]; 10640 10641 u8 reserved_at_20[0xc]; 10642 u8 max_bw_units[0x4]; 10643 u8 reserved_at_30[0x8]; 10644 u8 max_bw_value[0x8]; 10645 }; 10646 10647 struct mlx5_ifc_ets_global_config_reg_bits { 10648 u8 reserved_at_0[0x2]; 10649 u8 r[0x1]; 10650 u8 reserved_at_3[0x1d]; 10651 10652 u8 reserved_at_20[0xc]; 10653 u8 max_bw_units[0x4]; 10654 u8 reserved_at_30[0x8]; 10655 u8 max_bw_value[0x8]; 10656 }; 10657 10658 struct mlx5_ifc_qetc_reg_bits { 10659 u8 reserved_at_0[0x8]; 10660 u8 port_number[0x8]; 10661 u8 reserved_at_10[0x30]; 10662 10663 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10664 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10665 }; 10666 10667 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10668 u8 e[0x1]; 10669 u8 reserved_at_01[0x0b]; 10670 u8 prio[0x04]; 10671 }; 10672 10673 struct mlx5_ifc_qpdpm_reg_bits { 10674 u8 reserved_at_0[0x8]; 10675 u8 local_port[0x8]; 10676 u8 reserved_at_10[0x10]; 10677 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10678 }; 10679 10680 struct mlx5_ifc_qpts_reg_bits { 10681 u8 reserved_at_0[0x8]; 10682 u8 local_port[0x8]; 10683 u8 reserved_at_10[0x2d]; 10684 u8 trust_state[0x3]; 10685 }; 10686 10687 struct mlx5_ifc_pptb_reg_bits { 10688 u8 reserved_at_0[0x2]; 10689 u8 mm[0x2]; 10690 u8 reserved_at_4[0x4]; 10691 u8 local_port[0x8]; 10692 u8 reserved_at_10[0x6]; 10693 u8 cm[0x1]; 10694 u8 um[0x1]; 10695 u8 pm[0x8]; 10696 10697 u8 prio_x_buff[0x20]; 10698 10699 u8 pm_msb[0x8]; 10700 u8 reserved_at_48[0x10]; 10701 u8 ctrl_buff[0x4]; 10702 u8 untagged_buff[0x4]; 10703 }; 10704 10705 struct mlx5_ifc_sbcam_reg_bits { 10706 u8 reserved_at_0[0x8]; 10707 u8 feature_group[0x8]; 10708 u8 reserved_at_10[0x8]; 10709 u8 access_reg_group[0x8]; 10710 10711 u8 reserved_at_20[0x20]; 10712 10713 u8 sb_access_reg_cap_mask[4][0x20]; 10714 10715 u8 reserved_at_c0[0x80]; 10716 10717 u8 sb_feature_cap_mask[4][0x20]; 10718 10719 u8 reserved_at_1c0[0x40]; 10720 10721 u8 cap_total_buffer_size[0x20]; 10722 10723 u8 cap_cell_size[0x10]; 10724 u8 cap_max_pg_buffers[0x8]; 10725 u8 cap_num_pool_supported[0x8]; 10726 10727 u8 reserved_at_240[0x8]; 10728 u8 cap_sbsr_stat_size[0x8]; 10729 u8 cap_max_tclass_data[0x8]; 10730 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10731 }; 10732 10733 struct mlx5_ifc_pbmc_reg_bits { 10734 u8 reserved_at_0[0x8]; 10735 u8 local_port[0x8]; 10736 u8 reserved_at_10[0x10]; 10737 10738 u8 xoff_timer_value[0x10]; 10739 u8 xoff_refresh[0x10]; 10740 10741 u8 reserved_at_40[0x9]; 10742 u8 fullness_threshold[0x7]; 10743 u8 port_buffer_size[0x10]; 10744 10745 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10746 10747 u8 reserved_at_2e0[0x80]; 10748 }; 10749 10750 struct mlx5_ifc_qtct_reg_bits { 10751 u8 reserved_at_0[0x8]; 10752 u8 port_number[0x8]; 10753 u8 reserved_at_10[0xd]; 10754 u8 prio[0x3]; 10755 10756 u8 reserved_at_20[0x1d]; 10757 u8 tclass[0x3]; 10758 }; 10759 10760 struct mlx5_ifc_mcia_reg_bits { 10761 u8 l[0x1]; 10762 u8 reserved_at_1[0x7]; 10763 u8 module[0x8]; 10764 u8 reserved_at_10[0x8]; 10765 u8 status[0x8]; 10766 10767 u8 i2c_device_address[0x8]; 10768 u8 page_number[0x8]; 10769 u8 device_address[0x10]; 10770 10771 u8 reserved_at_40[0x10]; 10772 u8 size[0x10]; 10773 10774 u8 reserved_at_60[0x20]; 10775 10776 u8 dword_0[0x20]; 10777 u8 dword_1[0x20]; 10778 u8 dword_2[0x20]; 10779 u8 dword_3[0x20]; 10780 u8 dword_4[0x20]; 10781 u8 dword_5[0x20]; 10782 u8 dword_6[0x20]; 10783 u8 dword_7[0x20]; 10784 u8 dword_8[0x20]; 10785 u8 dword_9[0x20]; 10786 u8 dword_10[0x20]; 10787 u8 dword_11[0x20]; 10788 }; 10789 10790 struct mlx5_ifc_dcbx_param_bits { 10791 u8 dcbx_cee_cap[0x1]; 10792 u8 dcbx_ieee_cap[0x1]; 10793 u8 dcbx_standby_cap[0x1]; 10794 u8 reserved_at_3[0x5]; 10795 u8 port_number[0x8]; 10796 u8 reserved_at_10[0xa]; 10797 u8 max_application_table_size[6]; 10798 u8 reserved_at_20[0x15]; 10799 u8 version_oper[0x3]; 10800 u8 reserved_at_38[5]; 10801 u8 version_admin[0x3]; 10802 u8 willing_admin[0x1]; 10803 u8 reserved_at_41[0x3]; 10804 u8 pfc_cap_oper[0x4]; 10805 u8 reserved_at_48[0x4]; 10806 u8 pfc_cap_admin[0x4]; 10807 u8 reserved_at_50[0x4]; 10808 u8 num_of_tc_oper[0x4]; 10809 u8 reserved_at_58[0x4]; 10810 u8 num_of_tc_admin[0x4]; 10811 u8 remote_willing[0x1]; 10812 u8 reserved_at_61[3]; 10813 u8 remote_pfc_cap[4]; 10814 u8 reserved_at_68[0x14]; 10815 u8 remote_num_of_tc[0x4]; 10816 u8 reserved_at_80[0x18]; 10817 u8 error[0x8]; 10818 u8 reserved_at_a0[0x160]; 10819 }; 10820 10821 enum { 10822 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10823 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT, 10824 }; 10825 10826 struct mlx5_ifc_lagc_bits { 10827 u8 fdb_selection_mode[0x1]; 10828 u8 reserved_at_1[0x14]; 10829 u8 port_select_mode[0x3]; 10830 u8 reserved_at_18[0x5]; 10831 u8 lag_state[0x3]; 10832 10833 u8 reserved_at_20[0x14]; 10834 u8 tx_remap_affinity_2[0x4]; 10835 u8 reserved_at_38[0x4]; 10836 u8 tx_remap_affinity_1[0x4]; 10837 }; 10838 10839 struct mlx5_ifc_create_lag_out_bits { 10840 u8 status[0x8]; 10841 u8 reserved_at_8[0x18]; 10842 10843 u8 syndrome[0x20]; 10844 10845 u8 reserved_at_40[0x40]; 10846 }; 10847 10848 struct mlx5_ifc_create_lag_in_bits { 10849 u8 opcode[0x10]; 10850 u8 reserved_at_10[0x10]; 10851 10852 u8 reserved_at_20[0x10]; 10853 u8 op_mod[0x10]; 10854 10855 struct mlx5_ifc_lagc_bits ctx; 10856 }; 10857 10858 struct mlx5_ifc_modify_lag_out_bits { 10859 u8 status[0x8]; 10860 u8 reserved_at_8[0x18]; 10861 10862 u8 syndrome[0x20]; 10863 10864 u8 reserved_at_40[0x40]; 10865 }; 10866 10867 struct mlx5_ifc_modify_lag_in_bits { 10868 u8 opcode[0x10]; 10869 u8 reserved_at_10[0x10]; 10870 10871 u8 reserved_at_20[0x10]; 10872 u8 op_mod[0x10]; 10873 10874 u8 reserved_at_40[0x20]; 10875 u8 field_select[0x20]; 10876 10877 struct mlx5_ifc_lagc_bits ctx; 10878 }; 10879 10880 struct mlx5_ifc_query_lag_out_bits { 10881 u8 status[0x8]; 10882 u8 reserved_at_8[0x18]; 10883 10884 u8 syndrome[0x20]; 10885 10886 struct mlx5_ifc_lagc_bits ctx; 10887 }; 10888 10889 struct mlx5_ifc_query_lag_in_bits { 10890 u8 opcode[0x10]; 10891 u8 reserved_at_10[0x10]; 10892 10893 u8 reserved_at_20[0x10]; 10894 u8 op_mod[0x10]; 10895 10896 u8 reserved_at_40[0x40]; 10897 }; 10898 10899 struct mlx5_ifc_destroy_lag_out_bits { 10900 u8 status[0x8]; 10901 u8 reserved_at_8[0x18]; 10902 10903 u8 syndrome[0x20]; 10904 10905 u8 reserved_at_40[0x40]; 10906 }; 10907 10908 struct mlx5_ifc_destroy_lag_in_bits { 10909 u8 opcode[0x10]; 10910 u8 reserved_at_10[0x10]; 10911 10912 u8 reserved_at_20[0x10]; 10913 u8 op_mod[0x10]; 10914 10915 u8 reserved_at_40[0x40]; 10916 }; 10917 10918 struct mlx5_ifc_create_vport_lag_out_bits { 10919 u8 status[0x8]; 10920 u8 reserved_at_8[0x18]; 10921 10922 u8 syndrome[0x20]; 10923 10924 u8 reserved_at_40[0x40]; 10925 }; 10926 10927 struct mlx5_ifc_create_vport_lag_in_bits { 10928 u8 opcode[0x10]; 10929 u8 reserved_at_10[0x10]; 10930 10931 u8 reserved_at_20[0x10]; 10932 u8 op_mod[0x10]; 10933 10934 u8 reserved_at_40[0x40]; 10935 }; 10936 10937 struct mlx5_ifc_destroy_vport_lag_out_bits { 10938 u8 status[0x8]; 10939 u8 reserved_at_8[0x18]; 10940 10941 u8 syndrome[0x20]; 10942 10943 u8 reserved_at_40[0x40]; 10944 }; 10945 10946 struct mlx5_ifc_destroy_vport_lag_in_bits { 10947 u8 opcode[0x10]; 10948 u8 reserved_at_10[0x10]; 10949 10950 u8 reserved_at_20[0x10]; 10951 u8 op_mod[0x10]; 10952 10953 u8 reserved_at_40[0x40]; 10954 }; 10955 10956 enum { 10957 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10958 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10959 }; 10960 10961 struct mlx5_ifc_modify_memic_in_bits { 10962 u8 opcode[0x10]; 10963 u8 uid[0x10]; 10964 10965 u8 reserved_at_20[0x10]; 10966 u8 op_mod[0x10]; 10967 10968 u8 reserved_at_40[0x20]; 10969 10970 u8 reserved_at_60[0x18]; 10971 u8 memic_operation_type[0x8]; 10972 10973 u8 memic_start_addr[0x40]; 10974 10975 u8 reserved_at_c0[0x140]; 10976 }; 10977 10978 struct mlx5_ifc_modify_memic_out_bits { 10979 u8 status[0x8]; 10980 u8 reserved_at_8[0x18]; 10981 10982 u8 syndrome[0x20]; 10983 10984 u8 reserved_at_40[0x40]; 10985 10986 u8 memic_operation_addr[0x40]; 10987 10988 u8 reserved_at_c0[0x140]; 10989 }; 10990 10991 struct mlx5_ifc_alloc_memic_in_bits { 10992 u8 opcode[0x10]; 10993 u8 reserved_at_10[0x10]; 10994 10995 u8 reserved_at_20[0x10]; 10996 u8 op_mod[0x10]; 10997 10998 u8 reserved_at_30[0x20]; 10999 11000 u8 reserved_at_40[0x18]; 11001 u8 log_memic_addr_alignment[0x8]; 11002 11003 u8 range_start_addr[0x40]; 11004 11005 u8 range_size[0x20]; 11006 11007 u8 memic_size[0x20]; 11008 }; 11009 11010 struct mlx5_ifc_alloc_memic_out_bits { 11011 u8 status[0x8]; 11012 u8 reserved_at_8[0x18]; 11013 11014 u8 syndrome[0x20]; 11015 11016 u8 memic_start_addr[0x40]; 11017 }; 11018 11019 struct mlx5_ifc_dealloc_memic_in_bits { 11020 u8 opcode[0x10]; 11021 u8 reserved_at_10[0x10]; 11022 11023 u8 reserved_at_20[0x10]; 11024 u8 op_mod[0x10]; 11025 11026 u8 reserved_at_40[0x40]; 11027 11028 u8 memic_start_addr[0x40]; 11029 11030 u8 memic_size[0x20]; 11031 11032 u8 reserved_at_e0[0x20]; 11033 }; 11034 11035 struct mlx5_ifc_dealloc_memic_out_bits { 11036 u8 status[0x8]; 11037 u8 reserved_at_8[0x18]; 11038 11039 u8 syndrome[0x20]; 11040 11041 u8 reserved_at_40[0x40]; 11042 }; 11043 11044 struct mlx5_ifc_umem_bits { 11045 u8 reserved_at_0[0x80]; 11046 11047 u8 reserved_at_80[0x1b]; 11048 u8 log_page_size[0x5]; 11049 11050 u8 page_offset[0x20]; 11051 11052 u8 num_of_mtt[0x40]; 11053 11054 struct mlx5_ifc_mtt_bits mtt[]; 11055 }; 11056 11057 struct mlx5_ifc_uctx_bits { 11058 u8 cap[0x20]; 11059 11060 u8 reserved_at_20[0x160]; 11061 }; 11062 11063 struct mlx5_ifc_sw_icm_bits { 11064 u8 modify_field_select[0x40]; 11065 11066 u8 reserved_at_40[0x18]; 11067 u8 log_sw_icm_size[0x8]; 11068 11069 u8 reserved_at_60[0x20]; 11070 11071 u8 sw_icm_start_addr[0x40]; 11072 11073 u8 reserved_at_c0[0x140]; 11074 }; 11075 11076 struct mlx5_ifc_geneve_tlv_option_bits { 11077 u8 modify_field_select[0x40]; 11078 11079 u8 reserved_at_40[0x18]; 11080 u8 geneve_option_fte_index[0x8]; 11081 11082 u8 option_class[0x10]; 11083 u8 option_type[0x8]; 11084 u8 reserved_at_78[0x3]; 11085 u8 option_data_length[0x5]; 11086 11087 u8 reserved_at_80[0x180]; 11088 }; 11089 11090 struct mlx5_ifc_create_umem_in_bits { 11091 u8 opcode[0x10]; 11092 u8 uid[0x10]; 11093 11094 u8 reserved_at_20[0x10]; 11095 u8 op_mod[0x10]; 11096 11097 u8 reserved_at_40[0x40]; 11098 11099 struct mlx5_ifc_umem_bits umem; 11100 }; 11101 11102 struct mlx5_ifc_create_umem_out_bits { 11103 u8 status[0x8]; 11104 u8 reserved_at_8[0x18]; 11105 11106 u8 syndrome[0x20]; 11107 11108 u8 reserved_at_40[0x8]; 11109 u8 umem_id[0x18]; 11110 11111 u8 reserved_at_60[0x20]; 11112 }; 11113 11114 struct mlx5_ifc_destroy_umem_in_bits { 11115 u8 opcode[0x10]; 11116 u8 uid[0x10]; 11117 11118 u8 reserved_at_20[0x10]; 11119 u8 op_mod[0x10]; 11120 11121 u8 reserved_at_40[0x8]; 11122 u8 umem_id[0x18]; 11123 11124 u8 reserved_at_60[0x20]; 11125 }; 11126 11127 struct mlx5_ifc_destroy_umem_out_bits { 11128 u8 status[0x8]; 11129 u8 reserved_at_8[0x18]; 11130 11131 u8 syndrome[0x20]; 11132 11133 u8 reserved_at_40[0x40]; 11134 }; 11135 11136 struct mlx5_ifc_create_uctx_in_bits { 11137 u8 opcode[0x10]; 11138 u8 reserved_at_10[0x10]; 11139 11140 u8 reserved_at_20[0x10]; 11141 u8 op_mod[0x10]; 11142 11143 u8 reserved_at_40[0x40]; 11144 11145 struct mlx5_ifc_uctx_bits uctx; 11146 }; 11147 11148 struct mlx5_ifc_create_uctx_out_bits { 11149 u8 status[0x8]; 11150 u8 reserved_at_8[0x18]; 11151 11152 u8 syndrome[0x20]; 11153 11154 u8 reserved_at_40[0x10]; 11155 u8 uid[0x10]; 11156 11157 u8 reserved_at_60[0x20]; 11158 }; 11159 11160 struct mlx5_ifc_destroy_uctx_in_bits { 11161 u8 opcode[0x10]; 11162 u8 reserved_at_10[0x10]; 11163 11164 u8 reserved_at_20[0x10]; 11165 u8 op_mod[0x10]; 11166 11167 u8 reserved_at_40[0x10]; 11168 u8 uid[0x10]; 11169 11170 u8 reserved_at_60[0x20]; 11171 }; 11172 11173 struct mlx5_ifc_destroy_uctx_out_bits { 11174 u8 status[0x8]; 11175 u8 reserved_at_8[0x18]; 11176 11177 u8 syndrome[0x20]; 11178 11179 u8 reserved_at_40[0x40]; 11180 }; 11181 11182 struct mlx5_ifc_create_sw_icm_in_bits { 11183 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11184 struct mlx5_ifc_sw_icm_bits sw_icm; 11185 }; 11186 11187 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11188 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11189 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11190 }; 11191 11192 struct mlx5_ifc_mtrc_string_db_param_bits { 11193 u8 string_db_base_address[0x20]; 11194 11195 u8 reserved_at_20[0x8]; 11196 u8 string_db_size[0x18]; 11197 }; 11198 11199 struct mlx5_ifc_mtrc_cap_bits { 11200 u8 trace_owner[0x1]; 11201 u8 trace_to_memory[0x1]; 11202 u8 reserved_at_2[0x4]; 11203 u8 trc_ver[0x2]; 11204 u8 reserved_at_8[0x14]; 11205 u8 num_string_db[0x4]; 11206 11207 u8 first_string_trace[0x8]; 11208 u8 num_string_trace[0x8]; 11209 u8 reserved_at_30[0x28]; 11210 11211 u8 log_max_trace_buffer_size[0x8]; 11212 11213 u8 reserved_at_60[0x20]; 11214 11215 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11216 11217 u8 reserved_at_280[0x180]; 11218 }; 11219 11220 struct mlx5_ifc_mtrc_conf_bits { 11221 u8 reserved_at_0[0x1c]; 11222 u8 trace_mode[0x4]; 11223 u8 reserved_at_20[0x18]; 11224 u8 log_trace_buffer_size[0x8]; 11225 u8 trace_mkey[0x20]; 11226 u8 reserved_at_60[0x3a0]; 11227 }; 11228 11229 struct mlx5_ifc_mtrc_stdb_bits { 11230 u8 string_db_index[0x4]; 11231 u8 reserved_at_4[0x4]; 11232 u8 read_size[0x18]; 11233 u8 start_offset[0x20]; 11234 u8 string_db_data[]; 11235 }; 11236 11237 struct mlx5_ifc_mtrc_ctrl_bits { 11238 u8 trace_status[0x2]; 11239 u8 reserved_at_2[0x2]; 11240 u8 arm_event[0x1]; 11241 u8 reserved_at_5[0xb]; 11242 u8 modify_field_select[0x10]; 11243 u8 reserved_at_20[0x2b]; 11244 u8 current_timestamp52_32[0x15]; 11245 u8 current_timestamp31_0[0x20]; 11246 u8 reserved_at_80[0x180]; 11247 }; 11248 11249 struct mlx5_ifc_host_params_context_bits { 11250 u8 host_number[0x8]; 11251 u8 reserved_at_8[0x7]; 11252 u8 host_pf_disabled[0x1]; 11253 u8 host_num_of_vfs[0x10]; 11254 11255 u8 host_total_vfs[0x10]; 11256 u8 host_pci_bus[0x10]; 11257 11258 u8 reserved_at_40[0x10]; 11259 u8 host_pci_device[0x10]; 11260 11261 u8 reserved_at_60[0x10]; 11262 u8 host_pci_function[0x10]; 11263 11264 u8 reserved_at_80[0x180]; 11265 }; 11266 11267 struct mlx5_ifc_query_esw_functions_in_bits { 11268 u8 opcode[0x10]; 11269 u8 reserved_at_10[0x10]; 11270 11271 u8 reserved_at_20[0x10]; 11272 u8 op_mod[0x10]; 11273 11274 u8 reserved_at_40[0x40]; 11275 }; 11276 11277 struct mlx5_ifc_query_esw_functions_out_bits { 11278 u8 status[0x8]; 11279 u8 reserved_at_8[0x18]; 11280 11281 u8 syndrome[0x20]; 11282 11283 u8 reserved_at_40[0x40]; 11284 11285 struct mlx5_ifc_host_params_context_bits host_params_context; 11286 11287 u8 reserved_at_280[0x180]; 11288 u8 host_sf_enable[][0x40]; 11289 }; 11290 11291 struct mlx5_ifc_sf_partition_bits { 11292 u8 reserved_at_0[0x10]; 11293 u8 log_num_sf[0x8]; 11294 u8 log_sf_bar_size[0x8]; 11295 }; 11296 11297 struct mlx5_ifc_query_sf_partitions_out_bits { 11298 u8 status[0x8]; 11299 u8 reserved_at_8[0x18]; 11300 11301 u8 syndrome[0x20]; 11302 11303 u8 reserved_at_40[0x18]; 11304 u8 num_sf_partitions[0x8]; 11305 11306 u8 reserved_at_60[0x20]; 11307 11308 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11309 }; 11310 11311 struct mlx5_ifc_query_sf_partitions_in_bits { 11312 u8 opcode[0x10]; 11313 u8 reserved_at_10[0x10]; 11314 11315 u8 reserved_at_20[0x10]; 11316 u8 op_mod[0x10]; 11317 11318 u8 reserved_at_40[0x40]; 11319 }; 11320 11321 struct mlx5_ifc_dealloc_sf_out_bits { 11322 u8 status[0x8]; 11323 u8 reserved_at_8[0x18]; 11324 11325 u8 syndrome[0x20]; 11326 11327 u8 reserved_at_40[0x40]; 11328 }; 11329 11330 struct mlx5_ifc_dealloc_sf_in_bits { 11331 u8 opcode[0x10]; 11332 u8 reserved_at_10[0x10]; 11333 11334 u8 reserved_at_20[0x10]; 11335 u8 op_mod[0x10]; 11336 11337 u8 reserved_at_40[0x10]; 11338 u8 function_id[0x10]; 11339 11340 u8 reserved_at_60[0x20]; 11341 }; 11342 11343 struct mlx5_ifc_alloc_sf_out_bits { 11344 u8 status[0x8]; 11345 u8 reserved_at_8[0x18]; 11346 11347 u8 syndrome[0x20]; 11348 11349 u8 reserved_at_40[0x40]; 11350 }; 11351 11352 struct mlx5_ifc_alloc_sf_in_bits { 11353 u8 opcode[0x10]; 11354 u8 reserved_at_10[0x10]; 11355 11356 u8 reserved_at_20[0x10]; 11357 u8 op_mod[0x10]; 11358 11359 u8 reserved_at_40[0x10]; 11360 u8 function_id[0x10]; 11361 11362 u8 reserved_at_60[0x20]; 11363 }; 11364 11365 struct mlx5_ifc_affiliated_event_header_bits { 11366 u8 reserved_at_0[0x10]; 11367 u8 obj_type[0x10]; 11368 11369 u8 obj_id[0x20]; 11370 }; 11371 11372 enum { 11373 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11374 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11375 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11376 }; 11377 11378 enum { 11379 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11380 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11381 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11382 }; 11383 11384 enum { 11385 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11386 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 11387 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 11388 }; 11389 11390 struct mlx5_ifc_ipsec_obj_bits { 11391 u8 modify_field_select[0x40]; 11392 u8 full_offload[0x1]; 11393 u8 reserved_at_41[0x1]; 11394 u8 esn_en[0x1]; 11395 u8 esn_overlap[0x1]; 11396 u8 reserved_at_44[0x2]; 11397 u8 icv_length[0x2]; 11398 u8 reserved_at_48[0x4]; 11399 u8 aso_return_reg[0x4]; 11400 u8 reserved_at_50[0x10]; 11401 11402 u8 esn_msb[0x20]; 11403 11404 u8 reserved_at_80[0x8]; 11405 u8 dekn[0x18]; 11406 11407 u8 salt[0x20]; 11408 11409 u8 implicit_iv[0x40]; 11410 11411 u8 reserved_at_100[0x700]; 11412 }; 11413 11414 struct mlx5_ifc_create_ipsec_obj_in_bits { 11415 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11416 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11417 }; 11418 11419 enum { 11420 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11421 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11422 }; 11423 11424 struct mlx5_ifc_query_ipsec_obj_out_bits { 11425 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11426 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11427 }; 11428 11429 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11430 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11431 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11432 }; 11433 11434 struct mlx5_ifc_encryption_key_obj_bits { 11435 u8 modify_field_select[0x40]; 11436 11437 u8 reserved_at_40[0x14]; 11438 u8 key_size[0x4]; 11439 u8 reserved_at_58[0x4]; 11440 u8 key_type[0x4]; 11441 11442 u8 reserved_at_60[0x8]; 11443 u8 pd[0x18]; 11444 11445 u8 reserved_at_80[0x180]; 11446 u8 key[8][0x20]; 11447 11448 u8 reserved_at_300[0x500]; 11449 }; 11450 11451 struct mlx5_ifc_create_encryption_key_in_bits { 11452 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11453 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11454 }; 11455 11456 struct mlx5_ifc_sampler_obj_bits { 11457 u8 modify_field_select[0x40]; 11458 11459 u8 table_type[0x8]; 11460 u8 level[0x8]; 11461 u8 reserved_at_50[0xf]; 11462 u8 ignore_flow_level[0x1]; 11463 11464 u8 sample_ratio[0x20]; 11465 11466 u8 reserved_at_80[0x8]; 11467 u8 sample_table_id[0x18]; 11468 11469 u8 reserved_at_a0[0x8]; 11470 u8 default_table_id[0x18]; 11471 11472 u8 sw_steering_icm_address_rx[0x40]; 11473 u8 sw_steering_icm_address_tx[0x40]; 11474 11475 u8 reserved_at_140[0xa0]; 11476 }; 11477 11478 struct mlx5_ifc_create_sampler_obj_in_bits { 11479 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11480 struct mlx5_ifc_sampler_obj_bits sampler_object; 11481 }; 11482 11483 struct mlx5_ifc_query_sampler_obj_out_bits { 11484 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11485 struct mlx5_ifc_sampler_obj_bits sampler_object; 11486 }; 11487 11488 enum { 11489 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11490 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11491 }; 11492 11493 enum { 11494 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11495 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11496 }; 11497 11498 struct mlx5_ifc_tls_static_params_bits { 11499 u8 const_2[0x2]; 11500 u8 tls_version[0x4]; 11501 u8 const_1[0x2]; 11502 u8 reserved_at_8[0x14]; 11503 u8 encryption_standard[0x4]; 11504 11505 u8 reserved_at_20[0x20]; 11506 11507 u8 initial_record_number[0x40]; 11508 11509 u8 resync_tcp_sn[0x20]; 11510 11511 u8 gcm_iv[0x20]; 11512 11513 u8 implicit_iv[0x40]; 11514 11515 u8 reserved_at_100[0x8]; 11516 u8 dek_index[0x18]; 11517 11518 u8 reserved_at_120[0xe0]; 11519 }; 11520 11521 struct mlx5_ifc_tls_progress_params_bits { 11522 u8 next_record_tcp_sn[0x20]; 11523 11524 u8 hw_resync_tcp_sn[0x20]; 11525 11526 u8 record_tracker_state[0x2]; 11527 u8 auth_state[0x2]; 11528 u8 reserved_at_44[0x4]; 11529 u8 hw_offset_record_number[0x18]; 11530 }; 11531 11532 enum { 11533 MLX5_MTT_PERM_READ = 1 << 0, 11534 MLX5_MTT_PERM_WRITE = 1 << 1, 11535 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11536 }; 11537 11538 enum { 11539 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11540 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11541 }; 11542 11543 struct mlx5_ifc_suspend_vhca_in_bits { 11544 u8 opcode[0x10]; 11545 u8 uid[0x10]; 11546 11547 u8 reserved_at_20[0x10]; 11548 u8 op_mod[0x10]; 11549 11550 u8 reserved_at_40[0x10]; 11551 u8 vhca_id[0x10]; 11552 11553 u8 reserved_at_60[0x20]; 11554 }; 11555 11556 struct mlx5_ifc_suspend_vhca_out_bits { 11557 u8 status[0x8]; 11558 u8 reserved_at_8[0x18]; 11559 11560 u8 syndrome[0x20]; 11561 11562 u8 reserved_at_40[0x40]; 11563 }; 11564 11565 enum { 11566 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11567 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11568 }; 11569 11570 struct mlx5_ifc_resume_vhca_in_bits { 11571 u8 opcode[0x10]; 11572 u8 uid[0x10]; 11573 11574 u8 reserved_at_20[0x10]; 11575 u8 op_mod[0x10]; 11576 11577 u8 reserved_at_40[0x10]; 11578 u8 vhca_id[0x10]; 11579 11580 u8 reserved_at_60[0x20]; 11581 }; 11582 11583 struct mlx5_ifc_resume_vhca_out_bits { 11584 u8 status[0x8]; 11585 u8 reserved_at_8[0x18]; 11586 11587 u8 syndrome[0x20]; 11588 11589 u8 reserved_at_40[0x40]; 11590 }; 11591 11592 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11593 u8 opcode[0x10]; 11594 u8 uid[0x10]; 11595 11596 u8 reserved_at_20[0x10]; 11597 u8 op_mod[0x10]; 11598 11599 u8 reserved_at_40[0x10]; 11600 u8 vhca_id[0x10]; 11601 11602 u8 reserved_at_60[0x20]; 11603 }; 11604 11605 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11606 u8 status[0x8]; 11607 u8 reserved_at_8[0x18]; 11608 11609 u8 syndrome[0x20]; 11610 11611 u8 reserved_at_40[0x40]; 11612 11613 u8 required_umem_size[0x20]; 11614 11615 u8 reserved_at_a0[0x160]; 11616 }; 11617 11618 struct mlx5_ifc_save_vhca_state_in_bits { 11619 u8 opcode[0x10]; 11620 u8 uid[0x10]; 11621 11622 u8 reserved_at_20[0x10]; 11623 u8 op_mod[0x10]; 11624 11625 u8 reserved_at_40[0x10]; 11626 u8 vhca_id[0x10]; 11627 11628 u8 reserved_at_60[0x20]; 11629 11630 u8 va[0x40]; 11631 11632 u8 mkey[0x20]; 11633 11634 u8 size[0x20]; 11635 }; 11636 11637 struct mlx5_ifc_save_vhca_state_out_bits { 11638 u8 status[0x8]; 11639 u8 reserved_at_8[0x18]; 11640 11641 u8 syndrome[0x20]; 11642 11643 u8 actual_image_size[0x20]; 11644 11645 u8 reserved_at_60[0x20]; 11646 }; 11647 11648 struct mlx5_ifc_load_vhca_state_in_bits { 11649 u8 opcode[0x10]; 11650 u8 uid[0x10]; 11651 11652 u8 reserved_at_20[0x10]; 11653 u8 op_mod[0x10]; 11654 11655 u8 reserved_at_40[0x10]; 11656 u8 vhca_id[0x10]; 11657 11658 u8 reserved_at_60[0x20]; 11659 11660 u8 va[0x40]; 11661 11662 u8 mkey[0x20]; 11663 11664 u8 size[0x20]; 11665 }; 11666 11667 struct mlx5_ifc_load_vhca_state_out_bits { 11668 u8 status[0x8]; 11669 u8 reserved_at_8[0x18]; 11670 11671 u8 syndrome[0x20]; 11672 11673 u8 reserved_at_40[0x40]; 11674 }; 11675 11676 #endif /* MLX5_IFC_H */ 11677