1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 reserved_at_1e[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 reserved_at_41[0x4]; 375 u8 outer_first_mpls_over_udp[0x4]; 376 u8 outer_first_mpls_over_gre[0x4]; 377 u8 inner_first_mpls[0x4]; 378 u8 outer_first_mpls[0x4]; 379 u8 reserved_at_55[0x2]; 380 u8 outer_esp_spi[0x1]; 381 u8 reserved_at_58[0x2]; 382 u8 bth_dst_qp[0x1]; 383 u8 reserved_at_5b[0x5]; 384 385 u8 reserved_at_60[0x18]; 386 u8 metadata_reg_c_7[0x1]; 387 u8 metadata_reg_c_6[0x1]; 388 u8 metadata_reg_c_5[0x1]; 389 u8 metadata_reg_c_4[0x1]; 390 u8 metadata_reg_c_3[0x1]; 391 u8 metadata_reg_c_2[0x1]; 392 u8 metadata_reg_c_1[0x1]; 393 u8 metadata_reg_c_0[0x1]; 394 }; 395 396 struct mlx5_ifc_flow_table_prop_layout_bits { 397 u8 ft_support[0x1]; 398 u8 reserved_at_1[0x1]; 399 u8 flow_counter[0x1]; 400 u8 flow_modify_en[0x1]; 401 u8 modify_root[0x1]; 402 u8 identified_miss_table_mode[0x1]; 403 u8 flow_table_modify[0x1]; 404 u8 reformat[0x1]; 405 u8 decap[0x1]; 406 u8 reserved_at_9[0x1]; 407 u8 pop_vlan[0x1]; 408 u8 push_vlan[0x1]; 409 u8 reserved_at_c[0x1]; 410 u8 pop_vlan_2[0x1]; 411 u8 push_vlan_2[0x1]; 412 u8 reformat_and_vlan_action[0x1]; 413 u8 reserved_at_10[0x1]; 414 u8 sw_owner[0x1]; 415 u8 reformat_l3_tunnel_to_l2[0x1]; 416 u8 reformat_l2_to_l3_tunnel[0x1]; 417 u8 reformat_and_modify_action[0x1]; 418 u8 ignore_flow_level[0x1]; 419 u8 reserved_at_16[0x1]; 420 u8 table_miss_action_domain[0x1]; 421 u8 termination_table[0x1]; 422 u8 reformat_and_fwd_to_table[0x1]; 423 u8 reserved_at_1a[0x2]; 424 u8 ipsec_encrypt[0x1]; 425 u8 ipsec_decrypt[0x1]; 426 u8 sw_owner_v2[0x1]; 427 u8 reserved_at_1f[0x1]; 428 429 u8 termination_table_raw_traffic[0x1]; 430 u8 reserved_at_21[0x1]; 431 u8 log_max_ft_size[0x6]; 432 u8 log_max_modify_header_context[0x8]; 433 u8 max_modify_header_actions[0x8]; 434 u8 max_ft_level[0x8]; 435 436 u8 reserved_at_40[0x20]; 437 438 u8 reserved_at_60[0x2]; 439 u8 reformat_insert[0x1]; 440 u8 reformat_remove[0x1]; 441 u8 reserver_at_64[0x14]; 442 u8 log_max_ft_num[0x8]; 443 444 u8 reserved_at_80[0x10]; 445 u8 log_max_flow_counter[0x8]; 446 u8 log_max_destination[0x8]; 447 448 u8 reserved_at_a0[0x18]; 449 u8 log_max_flow[0x8]; 450 451 u8 reserved_at_c0[0x40]; 452 453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 454 455 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 456 }; 457 458 struct mlx5_ifc_odp_per_transport_service_cap_bits { 459 u8 send[0x1]; 460 u8 receive[0x1]; 461 u8 write[0x1]; 462 u8 read[0x1]; 463 u8 atomic[0x1]; 464 u8 srq_receive[0x1]; 465 u8 reserved_at_6[0x1a]; 466 }; 467 468 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 469 u8 smac_47_16[0x20]; 470 471 u8 smac_15_0[0x10]; 472 u8 ethertype[0x10]; 473 474 u8 dmac_47_16[0x20]; 475 476 u8 dmac_15_0[0x10]; 477 u8 first_prio[0x3]; 478 u8 first_cfi[0x1]; 479 u8 first_vid[0xc]; 480 481 u8 ip_protocol[0x8]; 482 u8 ip_dscp[0x6]; 483 u8 ip_ecn[0x2]; 484 u8 cvlan_tag[0x1]; 485 u8 svlan_tag[0x1]; 486 u8 frag[0x1]; 487 u8 ip_version[0x4]; 488 u8 tcp_flags[0x9]; 489 490 u8 tcp_sport[0x10]; 491 u8 tcp_dport[0x10]; 492 493 u8 reserved_at_c0[0x18]; 494 u8 ttl_hoplimit[0x8]; 495 496 u8 udp_sport[0x10]; 497 u8 udp_dport[0x10]; 498 499 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 500 501 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 502 }; 503 504 struct mlx5_ifc_nvgre_key_bits { 505 u8 hi[0x18]; 506 u8 lo[0x8]; 507 }; 508 509 union mlx5_ifc_gre_key_bits { 510 struct mlx5_ifc_nvgre_key_bits nvgre; 511 u8 key[0x20]; 512 }; 513 514 struct mlx5_ifc_fte_match_set_misc_bits { 515 u8 gre_c_present[0x1]; 516 u8 reserved_at_1[0x1]; 517 u8 gre_k_present[0x1]; 518 u8 gre_s_present[0x1]; 519 u8 source_vhca_port[0x4]; 520 u8 source_sqn[0x18]; 521 522 u8 source_eswitch_owner_vhca_id[0x10]; 523 u8 source_port[0x10]; 524 525 u8 outer_second_prio[0x3]; 526 u8 outer_second_cfi[0x1]; 527 u8 outer_second_vid[0xc]; 528 u8 inner_second_prio[0x3]; 529 u8 inner_second_cfi[0x1]; 530 u8 inner_second_vid[0xc]; 531 532 u8 outer_second_cvlan_tag[0x1]; 533 u8 inner_second_cvlan_tag[0x1]; 534 u8 outer_second_svlan_tag[0x1]; 535 u8 inner_second_svlan_tag[0x1]; 536 u8 reserved_at_64[0xc]; 537 u8 gre_protocol[0x10]; 538 539 union mlx5_ifc_gre_key_bits gre_key; 540 541 u8 vxlan_vni[0x18]; 542 u8 reserved_at_b8[0x8]; 543 544 u8 geneve_vni[0x18]; 545 u8 reserved_at_d8[0x7]; 546 u8 geneve_oam[0x1]; 547 548 u8 reserved_at_e0[0xc]; 549 u8 outer_ipv6_flow_label[0x14]; 550 551 u8 reserved_at_100[0xc]; 552 u8 inner_ipv6_flow_label[0x14]; 553 554 u8 reserved_at_120[0xa]; 555 u8 geneve_opt_len[0x6]; 556 u8 geneve_protocol_type[0x10]; 557 558 u8 reserved_at_140[0x8]; 559 u8 bth_dst_qp[0x18]; 560 u8 reserved_at_160[0x20]; 561 u8 outer_esp_spi[0x20]; 562 u8 reserved_at_1a0[0x60]; 563 }; 564 565 struct mlx5_ifc_fte_match_mpls_bits { 566 u8 mpls_label[0x14]; 567 u8 mpls_exp[0x3]; 568 u8 mpls_s_bos[0x1]; 569 u8 mpls_ttl[0x8]; 570 }; 571 572 struct mlx5_ifc_fte_match_set_misc2_bits { 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 574 575 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 576 577 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 578 579 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 580 581 u8 metadata_reg_c_7[0x20]; 582 583 u8 metadata_reg_c_6[0x20]; 584 585 u8 metadata_reg_c_5[0x20]; 586 587 u8 metadata_reg_c_4[0x20]; 588 589 u8 metadata_reg_c_3[0x20]; 590 591 u8 metadata_reg_c_2[0x20]; 592 593 u8 metadata_reg_c_1[0x20]; 594 595 u8 metadata_reg_c_0[0x20]; 596 597 u8 metadata_reg_a[0x20]; 598 599 u8 reserved_at_1a0[0x60]; 600 }; 601 602 struct mlx5_ifc_fte_match_set_misc3_bits { 603 u8 inner_tcp_seq_num[0x20]; 604 605 u8 outer_tcp_seq_num[0x20]; 606 607 u8 inner_tcp_ack_num[0x20]; 608 609 u8 outer_tcp_ack_num[0x20]; 610 611 u8 reserved_at_80[0x8]; 612 u8 outer_vxlan_gpe_vni[0x18]; 613 614 u8 outer_vxlan_gpe_next_protocol[0x8]; 615 u8 outer_vxlan_gpe_flags[0x8]; 616 u8 reserved_at_b0[0x10]; 617 618 u8 icmp_header_data[0x20]; 619 620 u8 icmpv6_header_data[0x20]; 621 622 u8 icmp_type[0x8]; 623 u8 icmp_code[0x8]; 624 u8 icmpv6_type[0x8]; 625 u8 icmpv6_code[0x8]; 626 627 u8 geneve_tlv_option_0_data[0x20]; 628 629 u8 gtpu_teid[0x20]; 630 631 u8 gtpu_msg_type[0x8]; 632 u8 gtpu_msg_flags[0x8]; 633 u8 reserved_at_170[0x10]; 634 635 u8 gtpu_dw_2[0x20]; 636 637 u8 gtpu_first_ext_dw_0[0x20]; 638 639 u8 gtpu_dw_0[0x20]; 640 641 u8 reserved_at_1e0[0x20]; 642 }; 643 644 struct mlx5_ifc_fte_match_set_misc4_bits { 645 u8 prog_sample_field_value_0[0x20]; 646 647 u8 prog_sample_field_id_0[0x20]; 648 649 u8 prog_sample_field_value_1[0x20]; 650 651 u8 prog_sample_field_id_1[0x20]; 652 653 u8 prog_sample_field_value_2[0x20]; 654 655 u8 prog_sample_field_id_2[0x20]; 656 657 u8 prog_sample_field_value_3[0x20]; 658 659 u8 prog_sample_field_id_3[0x20]; 660 661 u8 reserved_at_100[0x100]; 662 }; 663 664 struct mlx5_ifc_cmd_pas_bits { 665 u8 pa_h[0x20]; 666 667 u8 pa_l[0x14]; 668 u8 reserved_at_34[0xc]; 669 }; 670 671 struct mlx5_ifc_uint64_bits { 672 u8 hi[0x20]; 673 674 u8 lo[0x20]; 675 }; 676 677 enum { 678 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 679 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 680 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 681 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 682 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 683 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 684 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 685 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 686 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 687 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 688 }; 689 690 struct mlx5_ifc_ads_bits { 691 u8 fl[0x1]; 692 u8 free_ar[0x1]; 693 u8 reserved_at_2[0xe]; 694 u8 pkey_index[0x10]; 695 696 u8 reserved_at_20[0x8]; 697 u8 grh[0x1]; 698 u8 mlid[0x7]; 699 u8 rlid[0x10]; 700 701 u8 ack_timeout[0x5]; 702 u8 reserved_at_45[0x3]; 703 u8 src_addr_index[0x8]; 704 u8 reserved_at_50[0x4]; 705 u8 stat_rate[0x4]; 706 u8 hop_limit[0x8]; 707 708 u8 reserved_at_60[0x4]; 709 u8 tclass[0x8]; 710 u8 flow_label[0x14]; 711 712 u8 rgid_rip[16][0x8]; 713 714 u8 reserved_at_100[0x4]; 715 u8 f_dscp[0x1]; 716 u8 f_ecn[0x1]; 717 u8 reserved_at_106[0x1]; 718 u8 f_eth_prio[0x1]; 719 u8 ecn[0x2]; 720 u8 dscp[0x6]; 721 u8 udp_sport[0x10]; 722 723 u8 dei_cfi[0x1]; 724 u8 eth_prio[0x3]; 725 u8 sl[0x4]; 726 u8 vhca_port_num[0x8]; 727 u8 rmac_47_32[0x10]; 728 729 u8 rmac_31_0[0x20]; 730 }; 731 732 struct mlx5_ifc_flow_table_nic_cap_bits { 733 u8 nic_rx_multi_path_tirs[0x1]; 734 u8 nic_rx_multi_path_tirs_fts[0x1]; 735 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 736 u8 reserved_at_3[0x4]; 737 u8 sw_owner_reformat_supported[0x1]; 738 u8 reserved_at_8[0x18]; 739 740 u8 encap_general_header[0x1]; 741 u8 reserved_at_21[0xa]; 742 u8 log_max_packet_reformat_context[0x5]; 743 u8 reserved_at_30[0x6]; 744 u8 max_encap_header_size[0xa]; 745 u8 reserved_at_40[0x1c0]; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 758 759 u8 reserved_at_e00[0x1200]; 760 761 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 762 763 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 764 765 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 766 767 u8 reserved_at_20c0[0x5f40]; 768 }; 769 770 enum { 771 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 772 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 773 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 774 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 775 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 776 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 777 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 778 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 779 }; 780 781 struct mlx5_ifc_flow_table_eswitch_cap_bits { 782 u8 fdb_to_vport_reg_c_id[0x8]; 783 u8 reserved_at_8[0xd]; 784 u8 fdb_modify_header_fwd_to_table[0x1]; 785 u8 reserved_at_16[0x1]; 786 u8 flow_source[0x1]; 787 u8 reserved_at_18[0x2]; 788 u8 multi_fdb_encap[0x1]; 789 u8 egress_acl_forward_to_vport[0x1]; 790 u8 fdb_multi_path_to_table[0x1]; 791 u8 reserved_at_1d[0x3]; 792 793 u8 reserved_at_20[0x1e0]; 794 795 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 796 797 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 798 799 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 800 801 u8 reserved_at_800[0x1000]; 802 803 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 804 805 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 806 807 u8 sw_steering_uplink_icm_address_rx[0x40]; 808 809 u8 sw_steering_uplink_icm_address_tx[0x40]; 810 811 u8 reserved_at_1900[0x6700]; 812 }; 813 814 enum { 815 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 816 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 817 }; 818 819 struct mlx5_ifc_e_switch_cap_bits { 820 u8 vport_svlan_strip[0x1]; 821 u8 vport_cvlan_strip[0x1]; 822 u8 vport_svlan_insert[0x1]; 823 u8 vport_cvlan_insert_if_not_exist[0x1]; 824 u8 vport_cvlan_insert_overwrite[0x1]; 825 u8 reserved_at_5[0x2]; 826 u8 esw_shared_ingress_acl[0x1]; 827 u8 esw_uplink_ingress_acl[0x1]; 828 u8 root_ft_on_other_esw[0x1]; 829 u8 reserved_at_a[0xf]; 830 u8 esw_functions_changed[0x1]; 831 u8 reserved_at_1a[0x1]; 832 u8 ecpf_vport_exists[0x1]; 833 u8 counter_eswitch_affinity[0x1]; 834 u8 merged_eswitch[0x1]; 835 u8 nic_vport_node_guid_modify[0x1]; 836 u8 nic_vport_port_guid_modify[0x1]; 837 838 u8 vxlan_encap_decap[0x1]; 839 u8 nvgre_encap_decap[0x1]; 840 u8 reserved_at_22[0x1]; 841 u8 log_max_fdb_encap_uplink[0x5]; 842 u8 reserved_at_21[0x3]; 843 u8 log_max_packet_reformat_context[0x5]; 844 u8 reserved_2b[0x6]; 845 u8 max_encap_header_size[0xa]; 846 847 u8 reserved_at_40[0xb]; 848 u8 log_max_esw_sf[0x5]; 849 u8 esw_sf_base_id[0x10]; 850 851 u8 reserved_at_60[0x7a0]; 852 853 }; 854 855 struct mlx5_ifc_qos_cap_bits { 856 u8 packet_pacing[0x1]; 857 u8 esw_scheduling[0x1]; 858 u8 esw_bw_share[0x1]; 859 u8 esw_rate_limit[0x1]; 860 u8 reserved_at_4[0x1]; 861 u8 packet_pacing_burst_bound[0x1]; 862 u8 packet_pacing_typical_size[0x1]; 863 u8 reserved_at_7[0x1]; 864 u8 nic_sq_scheduling[0x1]; 865 u8 nic_bw_share[0x1]; 866 u8 nic_rate_limit[0x1]; 867 u8 packet_pacing_uid[0x1]; 868 u8 reserved_at_c[0x14]; 869 870 u8 reserved_at_20[0xb]; 871 u8 log_max_qos_nic_queue_group[0x5]; 872 u8 reserved_at_30[0x10]; 873 874 u8 packet_pacing_max_rate[0x20]; 875 876 u8 packet_pacing_min_rate[0x20]; 877 878 u8 reserved_at_80[0x10]; 879 u8 packet_pacing_rate_table_size[0x10]; 880 881 u8 esw_element_type[0x10]; 882 u8 esw_tsar_type[0x10]; 883 884 u8 reserved_at_c0[0x10]; 885 u8 max_qos_para_vport[0x10]; 886 887 u8 max_tsar_bw_share[0x20]; 888 889 u8 reserved_at_100[0x700]; 890 }; 891 892 struct mlx5_ifc_debug_cap_bits { 893 u8 core_dump_general[0x1]; 894 u8 core_dump_qp[0x1]; 895 u8 reserved_at_2[0x7]; 896 u8 resource_dump[0x1]; 897 u8 reserved_at_a[0x16]; 898 899 u8 reserved_at_20[0x2]; 900 u8 stall_detect[0x1]; 901 u8 reserved_at_23[0x1d]; 902 903 u8 reserved_at_40[0x7c0]; 904 }; 905 906 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 907 u8 csum_cap[0x1]; 908 u8 vlan_cap[0x1]; 909 u8 lro_cap[0x1]; 910 u8 lro_psh_flag[0x1]; 911 u8 lro_time_stamp[0x1]; 912 u8 reserved_at_5[0x2]; 913 u8 wqe_vlan_insert[0x1]; 914 u8 self_lb_en_modifiable[0x1]; 915 u8 reserved_at_9[0x2]; 916 u8 max_lso_cap[0x5]; 917 u8 multi_pkt_send_wqe[0x2]; 918 u8 wqe_inline_mode[0x2]; 919 u8 rss_ind_tbl_cap[0x4]; 920 u8 reg_umr_sq[0x1]; 921 u8 scatter_fcs[0x1]; 922 u8 enhanced_multi_pkt_send_wqe[0x1]; 923 u8 tunnel_lso_const_out_ip_id[0x1]; 924 u8 reserved_at_1c[0x2]; 925 u8 tunnel_stateless_gre[0x1]; 926 u8 tunnel_stateless_vxlan[0x1]; 927 928 u8 swp[0x1]; 929 u8 swp_csum[0x1]; 930 u8 swp_lso[0x1]; 931 u8 cqe_checksum_full[0x1]; 932 u8 tunnel_stateless_geneve_tx[0x1]; 933 u8 tunnel_stateless_mpls_over_udp[0x1]; 934 u8 tunnel_stateless_mpls_over_gre[0x1]; 935 u8 tunnel_stateless_vxlan_gpe[0x1]; 936 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 937 u8 tunnel_stateless_ip_over_ip[0x1]; 938 u8 insert_trailer[0x1]; 939 u8 reserved_at_2b[0x1]; 940 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 941 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 942 u8 reserved_at_2e[0x2]; 943 u8 max_vxlan_udp_ports[0x8]; 944 u8 reserved_at_38[0x6]; 945 u8 max_geneve_opt_len[0x1]; 946 u8 tunnel_stateless_geneve_rx[0x1]; 947 948 u8 reserved_at_40[0x10]; 949 u8 lro_min_mss_size[0x10]; 950 951 u8 reserved_at_60[0x120]; 952 953 u8 lro_timer_supported_periods[4][0x20]; 954 955 u8 reserved_at_200[0x600]; 956 }; 957 958 enum { 959 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 960 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 961 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 962 }; 963 964 struct mlx5_ifc_roce_cap_bits { 965 u8 roce_apm[0x1]; 966 u8 reserved_at_1[0x3]; 967 u8 sw_r_roce_src_udp_port[0x1]; 968 u8 fl_rc_qp_when_roce_disabled[0x1]; 969 u8 fl_rc_qp_when_roce_enabled[0x1]; 970 u8 reserved_at_7[0x17]; 971 u8 qp_ts_format[0x2]; 972 973 u8 reserved_at_20[0x60]; 974 975 u8 reserved_at_80[0xc]; 976 u8 l3_type[0x4]; 977 u8 reserved_at_90[0x8]; 978 u8 roce_version[0x8]; 979 980 u8 reserved_at_a0[0x10]; 981 u8 r_roce_dest_udp_port[0x10]; 982 983 u8 r_roce_max_src_udp_port[0x10]; 984 u8 r_roce_min_src_udp_port[0x10]; 985 986 u8 reserved_at_e0[0x10]; 987 u8 roce_address_table_size[0x10]; 988 989 u8 reserved_at_100[0x700]; 990 }; 991 992 struct mlx5_ifc_sync_steering_in_bits { 993 u8 opcode[0x10]; 994 u8 uid[0x10]; 995 996 u8 reserved_at_20[0x10]; 997 u8 op_mod[0x10]; 998 999 u8 reserved_at_40[0xc0]; 1000 }; 1001 1002 struct mlx5_ifc_sync_steering_out_bits { 1003 u8 status[0x8]; 1004 u8 reserved_at_8[0x18]; 1005 1006 u8 syndrome[0x20]; 1007 1008 u8 reserved_at_40[0x40]; 1009 }; 1010 1011 struct mlx5_ifc_device_mem_cap_bits { 1012 u8 memic[0x1]; 1013 u8 reserved_at_1[0x1f]; 1014 1015 u8 reserved_at_20[0xb]; 1016 u8 log_min_memic_alloc_size[0x5]; 1017 u8 reserved_at_30[0x8]; 1018 u8 log_max_memic_addr_alignment[0x8]; 1019 1020 u8 memic_bar_start_addr[0x40]; 1021 1022 u8 memic_bar_size[0x20]; 1023 1024 u8 max_memic_size[0x20]; 1025 1026 u8 steering_sw_icm_start_address[0x40]; 1027 1028 u8 reserved_at_100[0x8]; 1029 u8 log_header_modify_sw_icm_size[0x8]; 1030 u8 reserved_at_110[0x2]; 1031 u8 log_sw_icm_alloc_granularity[0x6]; 1032 u8 log_steering_sw_icm_size[0x8]; 1033 1034 u8 reserved_at_120[0x20]; 1035 1036 u8 header_modify_sw_icm_start_address[0x40]; 1037 1038 u8 reserved_at_180[0x80]; 1039 1040 u8 memic_operations[0x20]; 1041 1042 u8 reserved_at_220[0x5e0]; 1043 }; 1044 1045 struct mlx5_ifc_device_event_cap_bits { 1046 u8 user_affiliated_events[4][0x40]; 1047 1048 u8 user_unaffiliated_events[4][0x40]; 1049 }; 1050 1051 struct mlx5_ifc_virtio_emulation_cap_bits { 1052 u8 desc_tunnel_offload_type[0x1]; 1053 u8 eth_frame_offload_type[0x1]; 1054 u8 virtio_version_1_0[0x1]; 1055 u8 device_features_bits_mask[0xd]; 1056 u8 event_mode[0x8]; 1057 u8 virtio_queue_type[0x8]; 1058 1059 u8 max_tunnel_desc[0x10]; 1060 u8 reserved_at_30[0x3]; 1061 u8 log_doorbell_stride[0x5]; 1062 u8 reserved_at_38[0x3]; 1063 u8 log_doorbell_bar_size[0x5]; 1064 1065 u8 doorbell_bar_offset[0x40]; 1066 1067 u8 max_emulated_devices[0x8]; 1068 u8 max_num_virtio_queues[0x18]; 1069 1070 u8 reserved_at_a0[0x60]; 1071 1072 u8 umem_1_buffer_param_a[0x20]; 1073 1074 u8 umem_1_buffer_param_b[0x20]; 1075 1076 u8 umem_2_buffer_param_a[0x20]; 1077 1078 u8 umem_2_buffer_param_b[0x20]; 1079 1080 u8 umem_3_buffer_param_a[0x20]; 1081 1082 u8 umem_3_buffer_param_b[0x20]; 1083 1084 u8 reserved_at_1c0[0x640]; 1085 }; 1086 1087 enum { 1088 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1089 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1090 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1091 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1092 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1093 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1094 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1095 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1096 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1097 }; 1098 1099 enum { 1100 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1101 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1102 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1103 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1104 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1105 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1106 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1107 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1108 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1109 }; 1110 1111 struct mlx5_ifc_atomic_caps_bits { 1112 u8 reserved_at_0[0x40]; 1113 1114 u8 atomic_req_8B_endianness_mode[0x2]; 1115 u8 reserved_at_42[0x4]; 1116 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1117 1118 u8 reserved_at_47[0x19]; 1119 1120 u8 reserved_at_60[0x20]; 1121 1122 u8 reserved_at_80[0x10]; 1123 u8 atomic_operations[0x10]; 1124 1125 u8 reserved_at_a0[0x10]; 1126 u8 atomic_size_qp[0x10]; 1127 1128 u8 reserved_at_c0[0x10]; 1129 u8 atomic_size_dc[0x10]; 1130 1131 u8 reserved_at_e0[0x720]; 1132 }; 1133 1134 struct mlx5_ifc_odp_cap_bits { 1135 u8 reserved_at_0[0x40]; 1136 1137 u8 sig[0x1]; 1138 u8 reserved_at_41[0x1f]; 1139 1140 u8 reserved_at_60[0x20]; 1141 1142 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1143 1144 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1145 1146 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1147 1148 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1149 1150 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1151 1152 u8 reserved_at_120[0x6E0]; 1153 }; 1154 1155 struct mlx5_ifc_calc_op { 1156 u8 reserved_at_0[0x10]; 1157 u8 reserved_at_10[0x9]; 1158 u8 op_swap_endianness[0x1]; 1159 u8 op_min[0x1]; 1160 u8 op_xor[0x1]; 1161 u8 op_or[0x1]; 1162 u8 op_and[0x1]; 1163 u8 op_max[0x1]; 1164 u8 op_add[0x1]; 1165 }; 1166 1167 struct mlx5_ifc_vector_calc_cap_bits { 1168 u8 calc_matrix[0x1]; 1169 u8 reserved_at_1[0x1f]; 1170 u8 reserved_at_20[0x8]; 1171 u8 max_vec_count[0x8]; 1172 u8 reserved_at_30[0xd]; 1173 u8 max_chunk_size[0x3]; 1174 struct mlx5_ifc_calc_op calc0; 1175 struct mlx5_ifc_calc_op calc1; 1176 struct mlx5_ifc_calc_op calc2; 1177 struct mlx5_ifc_calc_op calc3; 1178 1179 u8 reserved_at_c0[0x720]; 1180 }; 1181 1182 struct mlx5_ifc_tls_cap_bits { 1183 u8 tls_1_2_aes_gcm_128[0x1]; 1184 u8 tls_1_3_aes_gcm_128[0x1]; 1185 u8 tls_1_2_aes_gcm_256[0x1]; 1186 u8 tls_1_3_aes_gcm_256[0x1]; 1187 u8 reserved_at_4[0x1c]; 1188 1189 u8 reserved_at_20[0x7e0]; 1190 }; 1191 1192 struct mlx5_ifc_ipsec_cap_bits { 1193 u8 ipsec_full_offload[0x1]; 1194 u8 ipsec_crypto_offload[0x1]; 1195 u8 ipsec_esn[0x1]; 1196 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1197 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1198 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1199 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1200 u8 reserved_at_7[0x4]; 1201 u8 log_max_ipsec_offload[0x5]; 1202 u8 reserved_at_10[0x10]; 1203 1204 u8 min_log_ipsec_full_replay_window[0x8]; 1205 u8 max_log_ipsec_full_replay_window[0x8]; 1206 u8 reserved_at_30[0x7d0]; 1207 }; 1208 1209 enum { 1210 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1211 MLX5_WQ_TYPE_CYCLIC = 0x1, 1212 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1213 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1214 }; 1215 1216 enum { 1217 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1218 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1219 }; 1220 1221 enum { 1222 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1223 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1224 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1225 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1226 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1227 }; 1228 1229 enum { 1230 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1231 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1232 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1233 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1234 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1235 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1236 }; 1237 1238 enum { 1239 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1240 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1241 }; 1242 1243 enum { 1244 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1245 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1246 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1247 }; 1248 1249 enum { 1250 MLX5_CAP_PORT_TYPE_IB = 0x0, 1251 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1252 }; 1253 1254 enum { 1255 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1256 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1257 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1258 }; 1259 1260 enum { 1261 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1262 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1263 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1264 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1265 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1266 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1267 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1268 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1269 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1270 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1271 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1272 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1273 }; 1274 1275 enum { 1276 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1277 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1278 }; 1279 1280 #define MLX5_FC_BULK_SIZE_FACTOR 128 1281 1282 enum mlx5_fc_bulk_alloc_bitmask { 1283 MLX5_FC_BULK_128 = (1 << 0), 1284 MLX5_FC_BULK_256 = (1 << 1), 1285 MLX5_FC_BULK_512 = (1 << 2), 1286 MLX5_FC_BULK_1024 = (1 << 3), 1287 MLX5_FC_BULK_2048 = (1 << 4), 1288 MLX5_FC_BULK_4096 = (1 << 5), 1289 MLX5_FC_BULK_8192 = (1 << 6), 1290 MLX5_FC_BULK_16384 = (1 << 7), 1291 }; 1292 1293 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1294 1295 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1296 1297 enum { 1298 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1299 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1300 }; 1301 1302 struct mlx5_ifc_cmd_hca_cap_bits { 1303 u8 reserved_at_0[0x1f]; 1304 u8 vhca_resource_manager[0x1]; 1305 1306 u8 hca_cap_2[0x1]; 1307 u8 reserved_at_21[0x2]; 1308 u8 event_on_vhca_state_teardown_request[0x1]; 1309 u8 event_on_vhca_state_in_use[0x1]; 1310 u8 event_on_vhca_state_active[0x1]; 1311 u8 event_on_vhca_state_allocated[0x1]; 1312 u8 event_on_vhca_state_invalid[0x1]; 1313 u8 reserved_at_28[0x8]; 1314 u8 vhca_id[0x10]; 1315 1316 u8 reserved_at_40[0x40]; 1317 1318 u8 log_max_srq_sz[0x8]; 1319 u8 log_max_qp_sz[0x8]; 1320 u8 event_cap[0x1]; 1321 u8 reserved_at_91[0x2]; 1322 u8 isolate_vl_tc_new[0x1]; 1323 u8 reserved_at_94[0x4]; 1324 u8 prio_tag_required[0x1]; 1325 u8 reserved_at_99[0x2]; 1326 u8 log_max_qp[0x5]; 1327 1328 u8 reserved_at_a0[0x3]; 1329 u8 ece_support[0x1]; 1330 u8 reserved_at_a4[0x5]; 1331 u8 reg_c_preserve[0x1]; 1332 u8 reserved_at_aa[0x1]; 1333 u8 log_max_srq[0x5]; 1334 u8 reserved_at_b0[0x1]; 1335 u8 uplink_follow[0x1]; 1336 u8 ts_cqe_to_dest_cqn[0x1]; 1337 u8 reserved_at_b3[0xd]; 1338 1339 u8 max_sgl_for_optimized_performance[0x8]; 1340 u8 log_max_cq_sz[0x8]; 1341 u8 relaxed_ordering_write_umr[0x1]; 1342 u8 relaxed_ordering_read_umr[0x1]; 1343 u8 reserved_at_d2[0x7]; 1344 u8 virtio_net_device_emualtion_manager[0x1]; 1345 u8 virtio_blk_device_emualtion_manager[0x1]; 1346 u8 log_max_cq[0x5]; 1347 1348 u8 log_max_eq_sz[0x8]; 1349 u8 relaxed_ordering_write[0x1]; 1350 u8 relaxed_ordering_read[0x1]; 1351 u8 log_max_mkey[0x6]; 1352 u8 reserved_at_f0[0x8]; 1353 u8 dump_fill_mkey[0x1]; 1354 u8 reserved_at_f9[0x2]; 1355 u8 fast_teardown[0x1]; 1356 u8 log_max_eq[0x4]; 1357 1358 u8 max_indirection[0x8]; 1359 u8 fixed_buffer_size[0x1]; 1360 u8 log_max_mrw_sz[0x7]; 1361 u8 force_teardown[0x1]; 1362 u8 reserved_at_111[0x1]; 1363 u8 log_max_bsf_list_size[0x6]; 1364 u8 umr_extended_translation_offset[0x1]; 1365 u8 null_mkey[0x1]; 1366 u8 log_max_klm_list_size[0x6]; 1367 1368 u8 reserved_at_120[0xa]; 1369 u8 log_max_ra_req_dc[0x6]; 1370 u8 reserved_at_130[0xa]; 1371 u8 log_max_ra_res_dc[0x6]; 1372 1373 u8 reserved_at_140[0x6]; 1374 u8 release_all_pages[0x1]; 1375 u8 reserved_at_147[0x2]; 1376 u8 roce_accl[0x1]; 1377 u8 log_max_ra_req_qp[0x6]; 1378 u8 reserved_at_150[0xa]; 1379 u8 log_max_ra_res_qp[0x6]; 1380 1381 u8 end_pad[0x1]; 1382 u8 cc_query_allowed[0x1]; 1383 u8 cc_modify_allowed[0x1]; 1384 u8 start_pad[0x1]; 1385 u8 cache_line_128byte[0x1]; 1386 u8 reserved_at_165[0x4]; 1387 u8 rts2rts_qp_counters_set_id[0x1]; 1388 u8 reserved_at_16a[0x2]; 1389 u8 vnic_env_int_rq_oob[0x1]; 1390 u8 sbcam_reg[0x1]; 1391 u8 reserved_at_16e[0x1]; 1392 u8 qcam_reg[0x1]; 1393 u8 gid_table_size[0x10]; 1394 1395 u8 out_of_seq_cnt[0x1]; 1396 u8 vport_counters[0x1]; 1397 u8 retransmission_q_counters[0x1]; 1398 u8 debug[0x1]; 1399 u8 modify_rq_counter_set_id[0x1]; 1400 u8 rq_delay_drop[0x1]; 1401 u8 max_qp_cnt[0xa]; 1402 u8 pkey_table_size[0x10]; 1403 1404 u8 vport_group_manager[0x1]; 1405 u8 vhca_group_manager[0x1]; 1406 u8 ib_virt[0x1]; 1407 u8 eth_virt[0x1]; 1408 u8 vnic_env_queue_counters[0x1]; 1409 u8 ets[0x1]; 1410 u8 nic_flow_table[0x1]; 1411 u8 eswitch_manager[0x1]; 1412 u8 device_memory[0x1]; 1413 u8 mcam_reg[0x1]; 1414 u8 pcam_reg[0x1]; 1415 u8 local_ca_ack_delay[0x5]; 1416 u8 port_module_event[0x1]; 1417 u8 enhanced_error_q_counters[0x1]; 1418 u8 ports_check[0x1]; 1419 u8 reserved_at_1b3[0x1]; 1420 u8 disable_link_up[0x1]; 1421 u8 beacon_led[0x1]; 1422 u8 port_type[0x2]; 1423 u8 num_ports[0x8]; 1424 1425 u8 reserved_at_1c0[0x1]; 1426 u8 pps[0x1]; 1427 u8 pps_modify[0x1]; 1428 u8 log_max_msg[0x5]; 1429 u8 reserved_at_1c8[0x4]; 1430 u8 max_tc[0x4]; 1431 u8 temp_warn_event[0x1]; 1432 u8 dcbx[0x1]; 1433 u8 general_notification_event[0x1]; 1434 u8 reserved_at_1d3[0x2]; 1435 u8 fpga[0x1]; 1436 u8 rol_s[0x1]; 1437 u8 rol_g[0x1]; 1438 u8 reserved_at_1d8[0x1]; 1439 u8 wol_s[0x1]; 1440 u8 wol_g[0x1]; 1441 u8 wol_a[0x1]; 1442 u8 wol_b[0x1]; 1443 u8 wol_m[0x1]; 1444 u8 wol_u[0x1]; 1445 u8 wol_p[0x1]; 1446 1447 u8 stat_rate_support[0x10]; 1448 u8 reserved_at_1f0[0x1]; 1449 u8 pci_sync_for_fw_update_event[0x1]; 1450 u8 reserved_at_1f2[0x6]; 1451 u8 init2_lag_tx_port_affinity[0x1]; 1452 u8 reserved_at_1fa[0x3]; 1453 u8 cqe_version[0x4]; 1454 1455 u8 compact_address_vector[0x1]; 1456 u8 striding_rq[0x1]; 1457 u8 reserved_at_202[0x1]; 1458 u8 ipoib_enhanced_offloads[0x1]; 1459 u8 ipoib_basic_offloads[0x1]; 1460 u8 reserved_at_205[0x1]; 1461 u8 repeated_block_disabled[0x1]; 1462 u8 umr_modify_entity_size_disabled[0x1]; 1463 u8 umr_modify_atomic_disabled[0x1]; 1464 u8 umr_indirect_mkey_disabled[0x1]; 1465 u8 umr_fence[0x2]; 1466 u8 dc_req_scat_data_cqe[0x1]; 1467 u8 reserved_at_20d[0x2]; 1468 u8 drain_sigerr[0x1]; 1469 u8 cmdif_checksum[0x2]; 1470 u8 sigerr_cqe[0x1]; 1471 u8 reserved_at_213[0x1]; 1472 u8 wq_signature[0x1]; 1473 u8 sctr_data_cqe[0x1]; 1474 u8 reserved_at_216[0x1]; 1475 u8 sho[0x1]; 1476 u8 tph[0x1]; 1477 u8 rf[0x1]; 1478 u8 dct[0x1]; 1479 u8 qos[0x1]; 1480 u8 eth_net_offloads[0x1]; 1481 u8 roce[0x1]; 1482 u8 atomic[0x1]; 1483 u8 reserved_at_21f[0x1]; 1484 1485 u8 cq_oi[0x1]; 1486 u8 cq_resize[0x1]; 1487 u8 cq_moderation[0x1]; 1488 u8 reserved_at_223[0x3]; 1489 u8 cq_eq_remap[0x1]; 1490 u8 pg[0x1]; 1491 u8 block_lb_mc[0x1]; 1492 u8 reserved_at_229[0x1]; 1493 u8 scqe_break_moderation[0x1]; 1494 u8 cq_period_start_from_cqe[0x1]; 1495 u8 cd[0x1]; 1496 u8 reserved_at_22d[0x1]; 1497 u8 apm[0x1]; 1498 u8 vector_calc[0x1]; 1499 u8 umr_ptr_rlky[0x1]; 1500 u8 imaicl[0x1]; 1501 u8 qp_packet_based[0x1]; 1502 u8 reserved_at_233[0x3]; 1503 u8 qkv[0x1]; 1504 u8 pkv[0x1]; 1505 u8 set_deth_sqpn[0x1]; 1506 u8 reserved_at_239[0x3]; 1507 u8 xrc[0x1]; 1508 u8 ud[0x1]; 1509 u8 uc[0x1]; 1510 u8 rc[0x1]; 1511 1512 u8 uar_4k[0x1]; 1513 u8 reserved_at_241[0x9]; 1514 u8 uar_sz[0x6]; 1515 u8 reserved_at_248[0x2]; 1516 u8 umem_uid_0[0x1]; 1517 u8 reserved_at_250[0x5]; 1518 u8 log_pg_sz[0x8]; 1519 1520 u8 bf[0x1]; 1521 u8 driver_version[0x1]; 1522 u8 pad_tx_eth_packet[0x1]; 1523 u8 reserved_at_263[0x3]; 1524 u8 mkey_by_name[0x1]; 1525 u8 reserved_at_267[0x4]; 1526 1527 u8 log_bf_reg_size[0x5]; 1528 1529 u8 reserved_at_270[0x6]; 1530 u8 lag_dct[0x2]; 1531 u8 lag_tx_port_affinity[0x1]; 1532 u8 lag_native_fdb_selection[0x1]; 1533 u8 reserved_at_27a[0x1]; 1534 u8 lag_master[0x1]; 1535 u8 num_lag_ports[0x4]; 1536 1537 u8 reserved_at_280[0x10]; 1538 u8 max_wqe_sz_sq[0x10]; 1539 1540 u8 reserved_at_2a0[0x10]; 1541 u8 max_wqe_sz_rq[0x10]; 1542 1543 u8 max_flow_counter_31_16[0x10]; 1544 u8 max_wqe_sz_sq_dc[0x10]; 1545 1546 u8 reserved_at_2e0[0x7]; 1547 u8 max_qp_mcg[0x19]; 1548 1549 u8 reserved_at_300[0x10]; 1550 u8 flow_counter_bulk_alloc[0x8]; 1551 u8 log_max_mcg[0x8]; 1552 1553 u8 reserved_at_320[0x3]; 1554 u8 log_max_transport_domain[0x5]; 1555 u8 reserved_at_328[0x3]; 1556 u8 log_max_pd[0x5]; 1557 u8 reserved_at_330[0xb]; 1558 u8 log_max_xrcd[0x5]; 1559 1560 u8 nic_receive_steering_discard[0x1]; 1561 u8 receive_discard_vport_down[0x1]; 1562 u8 transmit_discard_vport_down[0x1]; 1563 u8 reserved_at_343[0x5]; 1564 u8 log_max_flow_counter_bulk[0x8]; 1565 u8 max_flow_counter_15_0[0x10]; 1566 1567 1568 u8 reserved_at_360[0x3]; 1569 u8 log_max_rq[0x5]; 1570 u8 reserved_at_368[0x3]; 1571 u8 log_max_sq[0x5]; 1572 u8 reserved_at_370[0x3]; 1573 u8 log_max_tir[0x5]; 1574 u8 reserved_at_378[0x3]; 1575 u8 log_max_tis[0x5]; 1576 1577 u8 basic_cyclic_rcv_wqe[0x1]; 1578 u8 reserved_at_381[0x2]; 1579 u8 log_max_rmp[0x5]; 1580 u8 reserved_at_388[0x3]; 1581 u8 log_max_rqt[0x5]; 1582 u8 reserved_at_390[0x3]; 1583 u8 log_max_rqt_size[0x5]; 1584 u8 reserved_at_398[0x3]; 1585 u8 log_max_tis_per_sq[0x5]; 1586 1587 u8 ext_stride_num_range[0x1]; 1588 u8 reserved_at_3a1[0x2]; 1589 u8 log_max_stride_sz_rq[0x5]; 1590 u8 reserved_at_3a8[0x3]; 1591 u8 log_min_stride_sz_rq[0x5]; 1592 u8 reserved_at_3b0[0x3]; 1593 u8 log_max_stride_sz_sq[0x5]; 1594 u8 reserved_at_3b8[0x3]; 1595 u8 log_min_stride_sz_sq[0x5]; 1596 1597 u8 hairpin[0x1]; 1598 u8 reserved_at_3c1[0x2]; 1599 u8 log_max_hairpin_queues[0x5]; 1600 u8 reserved_at_3c8[0x3]; 1601 u8 log_max_hairpin_wq_data_sz[0x5]; 1602 u8 reserved_at_3d0[0x3]; 1603 u8 log_max_hairpin_num_packets[0x5]; 1604 u8 reserved_at_3d8[0x3]; 1605 u8 log_max_wq_sz[0x5]; 1606 1607 u8 nic_vport_change_event[0x1]; 1608 u8 disable_local_lb_uc[0x1]; 1609 u8 disable_local_lb_mc[0x1]; 1610 u8 log_min_hairpin_wq_data_sz[0x5]; 1611 u8 reserved_at_3e8[0x2]; 1612 u8 vhca_state[0x1]; 1613 u8 log_max_vlan_list[0x5]; 1614 u8 reserved_at_3f0[0x3]; 1615 u8 log_max_current_mc_list[0x5]; 1616 u8 reserved_at_3f8[0x3]; 1617 u8 log_max_current_uc_list[0x5]; 1618 1619 u8 general_obj_types[0x40]; 1620 1621 u8 sq_ts_format[0x2]; 1622 u8 rq_ts_format[0x2]; 1623 u8 steering_format_version[0x4]; 1624 u8 create_qp_start_hint[0x18]; 1625 1626 u8 reserved_at_460[0x3]; 1627 u8 log_max_uctx[0x5]; 1628 u8 reserved_at_468[0x2]; 1629 u8 ipsec_offload[0x1]; 1630 u8 log_max_umem[0x5]; 1631 u8 max_num_eqs[0x10]; 1632 1633 u8 reserved_at_480[0x1]; 1634 u8 tls_tx[0x1]; 1635 u8 tls_rx[0x1]; 1636 u8 log_max_l2_table[0x5]; 1637 u8 reserved_at_488[0x8]; 1638 u8 log_uar_page_sz[0x10]; 1639 1640 u8 reserved_at_4a0[0x20]; 1641 u8 device_frequency_mhz[0x20]; 1642 u8 device_frequency_khz[0x20]; 1643 1644 u8 reserved_at_500[0x20]; 1645 u8 num_of_uars_per_page[0x20]; 1646 1647 u8 flex_parser_protocols[0x20]; 1648 1649 u8 max_geneve_tlv_options[0x8]; 1650 u8 reserved_at_568[0x3]; 1651 u8 max_geneve_tlv_option_data_len[0x5]; 1652 u8 reserved_at_570[0x10]; 1653 1654 u8 reserved_at_580[0x33]; 1655 u8 log_max_dek[0x5]; 1656 u8 reserved_at_5b8[0x4]; 1657 u8 mini_cqe_resp_stride_index[0x1]; 1658 u8 cqe_128_always[0x1]; 1659 u8 cqe_compression_128[0x1]; 1660 u8 cqe_compression[0x1]; 1661 1662 u8 cqe_compression_timeout[0x10]; 1663 u8 cqe_compression_max_num[0x10]; 1664 1665 u8 reserved_at_5e0[0x8]; 1666 u8 flex_parser_id_gtpu_dw_0[0x4]; 1667 u8 reserved_at_5ec[0x4]; 1668 u8 tag_matching[0x1]; 1669 u8 rndv_offload_rc[0x1]; 1670 u8 rndv_offload_dc[0x1]; 1671 u8 log_tag_matching_list_sz[0x5]; 1672 u8 reserved_at_5f8[0x3]; 1673 u8 log_max_xrq[0x5]; 1674 1675 u8 affiliate_nic_vport_criteria[0x8]; 1676 u8 native_port_num[0x8]; 1677 u8 num_vhca_ports[0x8]; 1678 u8 flex_parser_id_gtpu_teid[0x4]; 1679 u8 reserved_at_61c[0x2]; 1680 u8 sw_owner_id[0x1]; 1681 u8 reserved_at_61f[0x1]; 1682 1683 u8 max_num_of_monitor_counters[0x10]; 1684 u8 num_ppcnt_monitor_counters[0x10]; 1685 1686 u8 max_num_sf[0x10]; 1687 u8 num_q_monitor_counters[0x10]; 1688 1689 u8 reserved_at_660[0x20]; 1690 1691 u8 sf[0x1]; 1692 u8 sf_set_partition[0x1]; 1693 u8 reserved_at_682[0x1]; 1694 u8 log_max_sf[0x5]; 1695 u8 apu[0x1]; 1696 u8 reserved_at_689[0x7]; 1697 u8 log_min_sf_size[0x8]; 1698 u8 max_num_sf_partitions[0x8]; 1699 1700 u8 uctx_cap[0x20]; 1701 1702 u8 reserved_at_6c0[0x4]; 1703 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1704 u8 flex_parser_id_icmp_dw1[0x4]; 1705 u8 flex_parser_id_icmp_dw0[0x4]; 1706 u8 flex_parser_id_icmpv6_dw1[0x4]; 1707 u8 flex_parser_id_icmpv6_dw0[0x4]; 1708 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1709 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1710 1711 u8 reserved_at_6e0[0x10]; 1712 u8 sf_base_id[0x10]; 1713 1714 u8 flex_parser_id_gtpu_dw_2[0x4]; 1715 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1716 u8 num_total_dynamic_vf_msix[0x18]; 1717 u8 reserved_at_720[0x14]; 1718 u8 dynamic_msix_table_size[0xc]; 1719 u8 reserved_at_740[0xc]; 1720 u8 min_dynamic_vf_msix_table_size[0x4]; 1721 u8 reserved_at_750[0x4]; 1722 u8 max_dynamic_vf_msix_table_size[0xc]; 1723 1724 u8 reserved_at_760[0x20]; 1725 u8 vhca_tunnel_commands[0x40]; 1726 u8 reserved_at_7c0[0x40]; 1727 }; 1728 1729 struct mlx5_ifc_cmd_hca_cap_2_bits { 1730 u8 reserved_at_0[0xa0]; 1731 1732 u8 max_reformat_insert_size[0x8]; 1733 u8 max_reformat_insert_offset[0x8]; 1734 u8 max_reformat_remove_size[0x8]; 1735 u8 max_reformat_remove_offset[0x8]; 1736 1737 u8 reserved_at_c0[0x740]; 1738 }; 1739 1740 enum mlx5_flow_destination_type { 1741 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1742 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1743 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1744 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1745 1746 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1747 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1748 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1749 }; 1750 1751 enum mlx5_flow_table_miss_action { 1752 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1753 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1754 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1755 }; 1756 1757 struct mlx5_ifc_dest_format_struct_bits { 1758 u8 destination_type[0x8]; 1759 u8 destination_id[0x18]; 1760 1761 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1762 u8 packet_reformat[0x1]; 1763 u8 reserved_at_22[0xe]; 1764 u8 destination_eswitch_owner_vhca_id[0x10]; 1765 }; 1766 1767 struct mlx5_ifc_flow_counter_list_bits { 1768 u8 flow_counter_id[0x20]; 1769 1770 u8 reserved_at_20[0x20]; 1771 }; 1772 1773 struct mlx5_ifc_extended_dest_format_bits { 1774 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1775 1776 u8 packet_reformat_id[0x20]; 1777 1778 u8 reserved_at_60[0x20]; 1779 }; 1780 1781 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1782 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1783 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1784 }; 1785 1786 struct mlx5_ifc_fte_match_param_bits { 1787 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1788 1789 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1790 1791 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1792 1793 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1794 1795 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1796 1797 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1798 1799 u8 reserved_at_c00[0x400]; 1800 }; 1801 1802 enum { 1803 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1804 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1805 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1806 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1807 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1808 }; 1809 1810 struct mlx5_ifc_rx_hash_field_select_bits { 1811 u8 l3_prot_type[0x1]; 1812 u8 l4_prot_type[0x1]; 1813 u8 selected_fields[0x1e]; 1814 }; 1815 1816 enum { 1817 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1818 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1819 }; 1820 1821 enum { 1822 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1823 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1824 }; 1825 1826 struct mlx5_ifc_wq_bits { 1827 u8 wq_type[0x4]; 1828 u8 wq_signature[0x1]; 1829 u8 end_padding_mode[0x2]; 1830 u8 cd_slave[0x1]; 1831 u8 reserved_at_8[0x18]; 1832 1833 u8 hds_skip_first_sge[0x1]; 1834 u8 log2_hds_buf_size[0x3]; 1835 u8 reserved_at_24[0x7]; 1836 u8 page_offset[0x5]; 1837 u8 lwm[0x10]; 1838 1839 u8 reserved_at_40[0x8]; 1840 u8 pd[0x18]; 1841 1842 u8 reserved_at_60[0x8]; 1843 u8 uar_page[0x18]; 1844 1845 u8 dbr_addr[0x40]; 1846 1847 u8 hw_counter[0x20]; 1848 1849 u8 sw_counter[0x20]; 1850 1851 u8 reserved_at_100[0xc]; 1852 u8 log_wq_stride[0x4]; 1853 u8 reserved_at_110[0x3]; 1854 u8 log_wq_pg_sz[0x5]; 1855 u8 reserved_at_118[0x3]; 1856 u8 log_wq_sz[0x5]; 1857 1858 u8 dbr_umem_valid[0x1]; 1859 u8 wq_umem_valid[0x1]; 1860 u8 reserved_at_122[0x1]; 1861 u8 log_hairpin_num_packets[0x5]; 1862 u8 reserved_at_128[0x3]; 1863 u8 log_hairpin_data_sz[0x5]; 1864 1865 u8 reserved_at_130[0x4]; 1866 u8 log_wqe_num_of_strides[0x4]; 1867 u8 two_byte_shift_en[0x1]; 1868 u8 reserved_at_139[0x4]; 1869 u8 log_wqe_stride_size[0x3]; 1870 1871 u8 reserved_at_140[0x4c0]; 1872 1873 struct mlx5_ifc_cmd_pas_bits pas[]; 1874 }; 1875 1876 struct mlx5_ifc_rq_num_bits { 1877 u8 reserved_at_0[0x8]; 1878 u8 rq_num[0x18]; 1879 }; 1880 1881 struct mlx5_ifc_mac_address_layout_bits { 1882 u8 reserved_at_0[0x10]; 1883 u8 mac_addr_47_32[0x10]; 1884 1885 u8 mac_addr_31_0[0x20]; 1886 }; 1887 1888 struct mlx5_ifc_vlan_layout_bits { 1889 u8 reserved_at_0[0x14]; 1890 u8 vlan[0x0c]; 1891 1892 u8 reserved_at_20[0x20]; 1893 }; 1894 1895 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1896 u8 reserved_at_0[0xa0]; 1897 1898 u8 min_time_between_cnps[0x20]; 1899 1900 u8 reserved_at_c0[0x12]; 1901 u8 cnp_dscp[0x6]; 1902 u8 reserved_at_d8[0x4]; 1903 u8 cnp_prio_mode[0x1]; 1904 u8 cnp_802p_prio[0x3]; 1905 1906 u8 reserved_at_e0[0x720]; 1907 }; 1908 1909 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1910 u8 reserved_at_0[0x60]; 1911 1912 u8 reserved_at_60[0x4]; 1913 u8 clamp_tgt_rate[0x1]; 1914 u8 reserved_at_65[0x3]; 1915 u8 clamp_tgt_rate_after_time_inc[0x1]; 1916 u8 reserved_at_69[0x17]; 1917 1918 u8 reserved_at_80[0x20]; 1919 1920 u8 rpg_time_reset[0x20]; 1921 1922 u8 rpg_byte_reset[0x20]; 1923 1924 u8 rpg_threshold[0x20]; 1925 1926 u8 rpg_max_rate[0x20]; 1927 1928 u8 rpg_ai_rate[0x20]; 1929 1930 u8 rpg_hai_rate[0x20]; 1931 1932 u8 rpg_gd[0x20]; 1933 1934 u8 rpg_min_dec_fac[0x20]; 1935 1936 u8 rpg_min_rate[0x20]; 1937 1938 u8 reserved_at_1c0[0xe0]; 1939 1940 u8 rate_to_set_on_first_cnp[0x20]; 1941 1942 u8 dce_tcp_g[0x20]; 1943 1944 u8 dce_tcp_rtt[0x20]; 1945 1946 u8 rate_reduce_monitor_period[0x20]; 1947 1948 u8 reserved_at_320[0x20]; 1949 1950 u8 initial_alpha_value[0x20]; 1951 1952 u8 reserved_at_360[0x4a0]; 1953 }; 1954 1955 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1956 u8 reserved_at_0[0x80]; 1957 1958 u8 rppp_max_rps[0x20]; 1959 1960 u8 rpg_time_reset[0x20]; 1961 1962 u8 rpg_byte_reset[0x20]; 1963 1964 u8 rpg_threshold[0x20]; 1965 1966 u8 rpg_max_rate[0x20]; 1967 1968 u8 rpg_ai_rate[0x20]; 1969 1970 u8 rpg_hai_rate[0x20]; 1971 1972 u8 rpg_gd[0x20]; 1973 1974 u8 rpg_min_dec_fac[0x20]; 1975 1976 u8 rpg_min_rate[0x20]; 1977 1978 u8 reserved_at_1c0[0x640]; 1979 }; 1980 1981 enum { 1982 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1983 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1984 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1985 }; 1986 1987 struct mlx5_ifc_resize_field_select_bits { 1988 u8 resize_field_select[0x20]; 1989 }; 1990 1991 struct mlx5_ifc_resource_dump_bits { 1992 u8 more_dump[0x1]; 1993 u8 inline_dump[0x1]; 1994 u8 reserved_at_2[0xa]; 1995 u8 seq_num[0x4]; 1996 u8 segment_type[0x10]; 1997 1998 u8 reserved_at_20[0x10]; 1999 u8 vhca_id[0x10]; 2000 2001 u8 index1[0x20]; 2002 2003 u8 index2[0x20]; 2004 2005 u8 num_of_obj1[0x10]; 2006 u8 num_of_obj2[0x10]; 2007 2008 u8 reserved_at_a0[0x20]; 2009 2010 u8 device_opaque[0x40]; 2011 2012 u8 mkey[0x20]; 2013 2014 u8 size[0x20]; 2015 2016 u8 address[0x40]; 2017 2018 u8 inline_data[52][0x20]; 2019 }; 2020 2021 struct mlx5_ifc_resource_dump_menu_record_bits { 2022 u8 reserved_at_0[0x4]; 2023 u8 num_of_obj2_supports_active[0x1]; 2024 u8 num_of_obj2_supports_all[0x1]; 2025 u8 must_have_num_of_obj2[0x1]; 2026 u8 support_num_of_obj2[0x1]; 2027 u8 num_of_obj1_supports_active[0x1]; 2028 u8 num_of_obj1_supports_all[0x1]; 2029 u8 must_have_num_of_obj1[0x1]; 2030 u8 support_num_of_obj1[0x1]; 2031 u8 must_have_index2[0x1]; 2032 u8 support_index2[0x1]; 2033 u8 must_have_index1[0x1]; 2034 u8 support_index1[0x1]; 2035 u8 segment_type[0x10]; 2036 2037 u8 segment_name[4][0x20]; 2038 2039 u8 index1_name[4][0x20]; 2040 2041 u8 index2_name[4][0x20]; 2042 }; 2043 2044 struct mlx5_ifc_resource_dump_segment_header_bits { 2045 u8 length_dw[0x10]; 2046 u8 segment_type[0x10]; 2047 }; 2048 2049 struct mlx5_ifc_resource_dump_command_segment_bits { 2050 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2051 2052 u8 segment_called[0x10]; 2053 u8 vhca_id[0x10]; 2054 2055 u8 index1[0x20]; 2056 2057 u8 index2[0x20]; 2058 2059 u8 num_of_obj1[0x10]; 2060 u8 num_of_obj2[0x10]; 2061 }; 2062 2063 struct mlx5_ifc_resource_dump_error_segment_bits { 2064 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2065 2066 u8 reserved_at_20[0x10]; 2067 u8 syndrome_id[0x10]; 2068 2069 u8 reserved_at_40[0x40]; 2070 2071 u8 error[8][0x20]; 2072 }; 2073 2074 struct mlx5_ifc_resource_dump_info_segment_bits { 2075 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2076 2077 u8 reserved_at_20[0x18]; 2078 u8 dump_version[0x8]; 2079 2080 u8 hw_version[0x20]; 2081 2082 u8 fw_version[0x20]; 2083 }; 2084 2085 struct mlx5_ifc_resource_dump_menu_segment_bits { 2086 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2087 2088 u8 reserved_at_20[0x10]; 2089 u8 num_of_records[0x10]; 2090 2091 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2092 }; 2093 2094 struct mlx5_ifc_resource_dump_resource_segment_bits { 2095 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2096 2097 u8 reserved_at_20[0x20]; 2098 2099 u8 index1[0x20]; 2100 2101 u8 index2[0x20]; 2102 2103 u8 payload[][0x20]; 2104 }; 2105 2106 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2107 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2108 }; 2109 2110 struct mlx5_ifc_menu_resource_dump_response_bits { 2111 struct mlx5_ifc_resource_dump_info_segment_bits info; 2112 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2113 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2114 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2115 }; 2116 2117 enum { 2118 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2119 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2120 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2121 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2122 }; 2123 2124 struct mlx5_ifc_modify_field_select_bits { 2125 u8 modify_field_select[0x20]; 2126 }; 2127 2128 struct mlx5_ifc_field_select_r_roce_np_bits { 2129 u8 field_select_r_roce_np[0x20]; 2130 }; 2131 2132 struct mlx5_ifc_field_select_r_roce_rp_bits { 2133 u8 field_select_r_roce_rp[0x20]; 2134 }; 2135 2136 enum { 2137 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2138 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2139 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2140 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2141 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2142 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2143 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2144 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2145 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2146 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2147 }; 2148 2149 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2150 u8 field_select_8021qaurp[0x20]; 2151 }; 2152 2153 struct mlx5_ifc_phys_layer_cntrs_bits { 2154 u8 time_since_last_clear_high[0x20]; 2155 2156 u8 time_since_last_clear_low[0x20]; 2157 2158 u8 symbol_errors_high[0x20]; 2159 2160 u8 symbol_errors_low[0x20]; 2161 2162 u8 sync_headers_errors_high[0x20]; 2163 2164 u8 sync_headers_errors_low[0x20]; 2165 2166 u8 edpl_bip_errors_lane0_high[0x20]; 2167 2168 u8 edpl_bip_errors_lane0_low[0x20]; 2169 2170 u8 edpl_bip_errors_lane1_high[0x20]; 2171 2172 u8 edpl_bip_errors_lane1_low[0x20]; 2173 2174 u8 edpl_bip_errors_lane2_high[0x20]; 2175 2176 u8 edpl_bip_errors_lane2_low[0x20]; 2177 2178 u8 edpl_bip_errors_lane3_high[0x20]; 2179 2180 u8 edpl_bip_errors_lane3_low[0x20]; 2181 2182 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2183 2184 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2185 2186 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2187 2188 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2189 2190 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2191 2192 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2193 2194 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2195 2196 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2197 2198 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2199 2200 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2201 2202 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2203 2204 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2205 2206 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2207 2208 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2209 2210 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2211 2212 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2213 2214 u8 rs_fec_corrected_blocks_high[0x20]; 2215 2216 u8 rs_fec_corrected_blocks_low[0x20]; 2217 2218 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2219 2220 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2221 2222 u8 rs_fec_no_errors_blocks_high[0x20]; 2223 2224 u8 rs_fec_no_errors_blocks_low[0x20]; 2225 2226 u8 rs_fec_single_error_blocks_high[0x20]; 2227 2228 u8 rs_fec_single_error_blocks_low[0x20]; 2229 2230 u8 rs_fec_corrected_symbols_total_high[0x20]; 2231 2232 u8 rs_fec_corrected_symbols_total_low[0x20]; 2233 2234 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2235 2236 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2237 2238 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2239 2240 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2241 2242 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2243 2244 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2245 2246 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2247 2248 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2249 2250 u8 link_down_events[0x20]; 2251 2252 u8 successful_recovery_events[0x20]; 2253 2254 u8 reserved_at_640[0x180]; 2255 }; 2256 2257 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2258 u8 time_since_last_clear_high[0x20]; 2259 2260 u8 time_since_last_clear_low[0x20]; 2261 2262 u8 phy_received_bits_high[0x20]; 2263 2264 u8 phy_received_bits_low[0x20]; 2265 2266 u8 phy_symbol_errors_high[0x20]; 2267 2268 u8 phy_symbol_errors_low[0x20]; 2269 2270 u8 phy_corrected_bits_high[0x20]; 2271 2272 u8 phy_corrected_bits_low[0x20]; 2273 2274 u8 phy_corrected_bits_lane0_high[0x20]; 2275 2276 u8 phy_corrected_bits_lane0_low[0x20]; 2277 2278 u8 phy_corrected_bits_lane1_high[0x20]; 2279 2280 u8 phy_corrected_bits_lane1_low[0x20]; 2281 2282 u8 phy_corrected_bits_lane2_high[0x20]; 2283 2284 u8 phy_corrected_bits_lane2_low[0x20]; 2285 2286 u8 phy_corrected_bits_lane3_high[0x20]; 2287 2288 u8 phy_corrected_bits_lane3_low[0x20]; 2289 2290 u8 reserved_at_200[0x5c0]; 2291 }; 2292 2293 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2294 u8 symbol_error_counter[0x10]; 2295 2296 u8 link_error_recovery_counter[0x8]; 2297 2298 u8 link_downed_counter[0x8]; 2299 2300 u8 port_rcv_errors[0x10]; 2301 2302 u8 port_rcv_remote_physical_errors[0x10]; 2303 2304 u8 port_rcv_switch_relay_errors[0x10]; 2305 2306 u8 port_xmit_discards[0x10]; 2307 2308 u8 port_xmit_constraint_errors[0x8]; 2309 2310 u8 port_rcv_constraint_errors[0x8]; 2311 2312 u8 reserved_at_70[0x8]; 2313 2314 u8 link_overrun_errors[0x8]; 2315 2316 u8 reserved_at_80[0x10]; 2317 2318 u8 vl_15_dropped[0x10]; 2319 2320 u8 reserved_at_a0[0x80]; 2321 2322 u8 port_xmit_wait[0x20]; 2323 }; 2324 2325 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2326 u8 transmit_queue_high[0x20]; 2327 2328 u8 transmit_queue_low[0x20]; 2329 2330 u8 no_buffer_discard_uc_high[0x20]; 2331 2332 u8 no_buffer_discard_uc_low[0x20]; 2333 2334 u8 reserved_at_80[0x740]; 2335 }; 2336 2337 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2338 u8 wred_discard_high[0x20]; 2339 2340 u8 wred_discard_low[0x20]; 2341 2342 u8 ecn_marked_tc_high[0x20]; 2343 2344 u8 ecn_marked_tc_low[0x20]; 2345 2346 u8 reserved_at_80[0x740]; 2347 }; 2348 2349 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2350 u8 rx_octets_high[0x20]; 2351 2352 u8 rx_octets_low[0x20]; 2353 2354 u8 reserved_at_40[0xc0]; 2355 2356 u8 rx_frames_high[0x20]; 2357 2358 u8 rx_frames_low[0x20]; 2359 2360 u8 tx_octets_high[0x20]; 2361 2362 u8 tx_octets_low[0x20]; 2363 2364 u8 reserved_at_180[0xc0]; 2365 2366 u8 tx_frames_high[0x20]; 2367 2368 u8 tx_frames_low[0x20]; 2369 2370 u8 rx_pause_high[0x20]; 2371 2372 u8 rx_pause_low[0x20]; 2373 2374 u8 rx_pause_duration_high[0x20]; 2375 2376 u8 rx_pause_duration_low[0x20]; 2377 2378 u8 tx_pause_high[0x20]; 2379 2380 u8 tx_pause_low[0x20]; 2381 2382 u8 tx_pause_duration_high[0x20]; 2383 2384 u8 tx_pause_duration_low[0x20]; 2385 2386 u8 rx_pause_transition_high[0x20]; 2387 2388 u8 rx_pause_transition_low[0x20]; 2389 2390 u8 rx_discards_high[0x20]; 2391 2392 u8 rx_discards_low[0x20]; 2393 2394 u8 device_stall_minor_watermark_cnt_high[0x20]; 2395 2396 u8 device_stall_minor_watermark_cnt_low[0x20]; 2397 2398 u8 device_stall_critical_watermark_cnt_high[0x20]; 2399 2400 u8 device_stall_critical_watermark_cnt_low[0x20]; 2401 2402 u8 reserved_at_480[0x340]; 2403 }; 2404 2405 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2406 u8 port_transmit_wait_high[0x20]; 2407 2408 u8 port_transmit_wait_low[0x20]; 2409 2410 u8 reserved_at_40[0x100]; 2411 2412 u8 rx_buffer_almost_full_high[0x20]; 2413 2414 u8 rx_buffer_almost_full_low[0x20]; 2415 2416 u8 rx_buffer_full_high[0x20]; 2417 2418 u8 rx_buffer_full_low[0x20]; 2419 2420 u8 rx_icrc_encapsulated_high[0x20]; 2421 2422 u8 rx_icrc_encapsulated_low[0x20]; 2423 2424 u8 reserved_at_200[0x5c0]; 2425 }; 2426 2427 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2428 u8 dot3stats_alignment_errors_high[0x20]; 2429 2430 u8 dot3stats_alignment_errors_low[0x20]; 2431 2432 u8 dot3stats_fcs_errors_high[0x20]; 2433 2434 u8 dot3stats_fcs_errors_low[0x20]; 2435 2436 u8 dot3stats_single_collision_frames_high[0x20]; 2437 2438 u8 dot3stats_single_collision_frames_low[0x20]; 2439 2440 u8 dot3stats_multiple_collision_frames_high[0x20]; 2441 2442 u8 dot3stats_multiple_collision_frames_low[0x20]; 2443 2444 u8 dot3stats_sqe_test_errors_high[0x20]; 2445 2446 u8 dot3stats_sqe_test_errors_low[0x20]; 2447 2448 u8 dot3stats_deferred_transmissions_high[0x20]; 2449 2450 u8 dot3stats_deferred_transmissions_low[0x20]; 2451 2452 u8 dot3stats_late_collisions_high[0x20]; 2453 2454 u8 dot3stats_late_collisions_low[0x20]; 2455 2456 u8 dot3stats_excessive_collisions_high[0x20]; 2457 2458 u8 dot3stats_excessive_collisions_low[0x20]; 2459 2460 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2461 2462 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2463 2464 u8 dot3stats_carrier_sense_errors_high[0x20]; 2465 2466 u8 dot3stats_carrier_sense_errors_low[0x20]; 2467 2468 u8 dot3stats_frame_too_longs_high[0x20]; 2469 2470 u8 dot3stats_frame_too_longs_low[0x20]; 2471 2472 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2473 2474 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2475 2476 u8 dot3stats_symbol_errors_high[0x20]; 2477 2478 u8 dot3stats_symbol_errors_low[0x20]; 2479 2480 u8 dot3control_in_unknown_opcodes_high[0x20]; 2481 2482 u8 dot3control_in_unknown_opcodes_low[0x20]; 2483 2484 u8 dot3in_pause_frames_high[0x20]; 2485 2486 u8 dot3in_pause_frames_low[0x20]; 2487 2488 u8 dot3out_pause_frames_high[0x20]; 2489 2490 u8 dot3out_pause_frames_low[0x20]; 2491 2492 u8 reserved_at_400[0x3c0]; 2493 }; 2494 2495 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2496 u8 ether_stats_drop_events_high[0x20]; 2497 2498 u8 ether_stats_drop_events_low[0x20]; 2499 2500 u8 ether_stats_octets_high[0x20]; 2501 2502 u8 ether_stats_octets_low[0x20]; 2503 2504 u8 ether_stats_pkts_high[0x20]; 2505 2506 u8 ether_stats_pkts_low[0x20]; 2507 2508 u8 ether_stats_broadcast_pkts_high[0x20]; 2509 2510 u8 ether_stats_broadcast_pkts_low[0x20]; 2511 2512 u8 ether_stats_multicast_pkts_high[0x20]; 2513 2514 u8 ether_stats_multicast_pkts_low[0x20]; 2515 2516 u8 ether_stats_crc_align_errors_high[0x20]; 2517 2518 u8 ether_stats_crc_align_errors_low[0x20]; 2519 2520 u8 ether_stats_undersize_pkts_high[0x20]; 2521 2522 u8 ether_stats_undersize_pkts_low[0x20]; 2523 2524 u8 ether_stats_oversize_pkts_high[0x20]; 2525 2526 u8 ether_stats_oversize_pkts_low[0x20]; 2527 2528 u8 ether_stats_fragments_high[0x20]; 2529 2530 u8 ether_stats_fragments_low[0x20]; 2531 2532 u8 ether_stats_jabbers_high[0x20]; 2533 2534 u8 ether_stats_jabbers_low[0x20]; 2535 2536 u8 ether_stats_collisions_high[0x20]; 2537 2538 u8 ether_stats_collisions_low[0x20]; 2539 2540 u8 ether_stats_pkts64octets_high[0x20]; 2541 2542 u8 ether_stats_pkts64octets_low[0x20]; 2543 2544 u8 ether_stats_pkts65to127octets_high[0x20]; 2545 2546 u8 ether_stats_pkts65to127octets_low[0x20]; 2547 2548 u8 ether_stats_pkts128to255octets_high[0x20]; 2549 2550 u8 ether_stats_pkts128to255octets_low[0x20]; 2551 2552 u8 ether_stats_pkts256to511octets_high[0x20]; 2553 2554 u8 ether_stats_pkts256to511octets_low[0x20]; 2555 2556 u8 ether_stats_pkts512to1023octets_high[0x20]; 2557 2558 u8 ether_stats_pkts512to1023octets_low[0x20]; 2559 2560 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2561 2562 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2563 2564 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2565 2566 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2567 2568 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2569 2570 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2571 2572 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2573 2574 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2575 2576 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2577 2578 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2579 2580 u8 reserved_at_540[0x280]; 2581 }; 2582 2583 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2584 u8 if_in_octets_high[0x20]; 2585 2586 u8 if_in_octets_low[0x20]; 2587 2588 u8 if_in_ucast_pkts_high[0x20]; 2589 2590 u8 if_in_ucast_pkts_low[0x20]; 2591 2592 u8 if_in_discards_high[0x20]; 2593 2594 u8 if_in_discards_low[0x20]; 2595 2596 u8 if_in_errors_high[0x20]; 2597 2598 u8 if_in_errors_low[0x20]; 2599 2600 u8 if_in_unknown_protos_high[0x20]; 2601 2602 u8 if_in_unknown_protos_low[0x20]; 2603 2604 u8 if_out_octets_high[0x20]; 2605 2606 u8 if_out_octets_low[0x20]; 2607 2608 u8 if_out_ucast_pkts_high[0x20]; 2609 2610 u8 if_out_ucast_pkts_low[0x20]; 2611 2612 u8 if_out_discards_high[0x20]; 2613 2614 u8 if_out_discards_low[0x20]; 2615 2616 u8 if_out_errors_high[0x20]; 2617 2618 u8 if_out_errors_low[0x20]; 2619 2620 u8 if_in_multicast_pkts_high[0x20]; 2621 2622 u8 if_in_multicast_pkts_low[0x20]; 2623 2624 u8 if_in_broadcast_pkts_high[0x20]; 2625 2626 u8 if_in_broadcast_pkts_low[0x20]; 2627 2628 u8 if_out_multicast_pkts_high[0x20]; 2629 2630 u8 if_out_multicast_pkts_low[0x20]; 2631 2632 u8 if_out_broadcast_pkts_high[0x20]; 2633 2634 u8 if_out_broadcast_pkts_low[0x20]; 2635 2636 u8 reserved_at_340[0x480]; 2637 }; 2638 2639 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2640 u8 a_frames_transmitted_ok_high[0x20]; 2641 2642 u8 a_frames_transmitted_ok_low[0x20]; 2643 2644 u8 a_frames_received_ok_high[0x20]; 2645 2646 u8 a_frames_received_ok_low[0x20]; 2647 2648 u8 a_frame_check_sequence_errors_high[0x20]; 2649 2650 u8 a_frame_check_sequence_errors_low[0x20]; 2651 2652 u8 a_alignment_errors_high[0x20]; 2653 2654 u8 a_alignment_errors_low[0x20]; 2655 2656 u8 a_octets_transmitted_ok_high[0x20]; 2657 2658 u8 a_octets_transmitted_ok_low[0x20]; 2659 2660 u8 a_octets_received_ok_high[0x20]; 2661 2662 u8 a_octets_received_ok_low[0x20]; 2663 2664 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2665 2666 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2667 2668 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2669 2670 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2671 2672 u8 a_multicast_frames_received_ok_high[0x20]; 2673 2674 u8 a_multicast_frames_received_ok_low[0x20]; 2675 2676 u8 a_broadcast_frames_received_ok_high[0x20]; 2677 2678 u8 a_broadcast_frames_received_ok_low[0x20]; 2679 2680 u8 a_in_range_length_errors_high[0x20]; 2681 2682 u8 a_in_range_length_errors_low[0x20]; 2683 2684 u8 a_out_of_range_length_field_high[0x20]; 2685 2686 u8 a_out_of_range_length_field_low[0x20]; 2687 2688 u8 a_frame_too_long_errors_high[0x20]; 2689 2690 u8 a_frame_too_long_errors_low[0x20]; 2691 2692 u8 a_symbol_error_during_carrier_high[0x20]; 2693 2694 u8 a_symbol_error_during_carrier_low[0x20]; 2695 2696 u8 a_mac_control_frames_transmitted_high[0x20]; 2697 2698 u8 a_mac_control_frames_transmitted_low[0x20]; 2699 2700 u8 a_mac_control_frames_received_high[0x20]; 2701 2702 u8 a_mac_control_frames_received_low[0x20]; 2703 2704 u8 a_unsupported_opcodes_received_high[0x20]; 2705 2706 u8 a_unsupported_opcodes_received_low[0x20]; 2707 2708 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2709 2710 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2711 2712 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2713 2714 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2715 2716 u8 reserved_at_4c0[0x300]; 2717 }; 2718 2719 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2720 u8 life_time_counter_high[0x20]; 2721 2722 u8 life_time_counter_low[0x20]; 2723 2724 u8 rx_errors[0x20]; 2725 2726 u8 tx_errors[0x20]; 2727 2728 u8 l0_to_recovery_eieos[0x20]; 2729 2730 u8 l0_to_recovery_ts[0x20]; 2731 2732 u8 l0_to_recovery_framing[0x20]; 2733 2734 u8 l0_to_recovery_retrain[0x20]; 2735 2736 u8 crc_error_dllp[0x20]; 2737 2738 u8 crc_error_tlp[0x20]; 2739 2740 u8 tx_overflow_buffer_pkt_high[0x20]; 2741 2742 u8 tx_overflow_buffer_pkt_low[0x20]; 2743 2744 u8 outbound_stalled_reads[0x20]; 2745 2746 u8 outbound_stalled_writes[0x20]; 2747 2748 u8 outbound_stalled_reads_events[0x20]; 2749 2750 u8 outbound_stalled_writes_events[0x20]; 2751 2752 u8 reserved_at_200[0x5c0]; 2753 }; 2754 2755 struct mlx5_ifc_cmd_inter_comp_event_bits { 2756 u8 command_completion_vector[0x20]; 2757 2758 u8 reserved_at_20[0xc0]; 2759 }; 2760 2761 struct mlx5_ifc_stall_vl_event_bits { 2762 u8 reserved_at_0[0x18]; 2763 u8 port_num[0x1]; 2764 u8 reserved_at_19[0x3]; 2765 u8 vl[0x4]; 2766 2767 u8 reserved_at_20[0xa0]; 2768 }; 2769 2770 struct mlx5_ifc_db_bf_congestion_event_bits { 2771 u8 event_subtype[0x8]; 2772 u8 reserved_at_8[0x8]; 2773 u8 congestion_level[0x8]; 2774 u8 reserved_at_18[0x8]; 2775 2776 u8 reserved_at_20[0xa0]; 2777 }; 2778 2779 struct mlx5_ifc_gpio_event_bits { 2780 u8 reserved_at_0[0x60]; 2781 2782 u8 gpio_event_hi[0x20]; 2783 2784 u8 gpio_event_lo[0x20]; 2785 2786 u8 reserved_at_a0[0x40]; 2787 }; 2788 2789 struct mlx5_ifc_port_state_change_event_bits { 2790 u8 reserved_at_0[0x40]; 2791 2792 u8 port_num[0x4]; 2793 u8 reserved_at_44[0x1c]; 2794 2795 u8 reserved_at_60[0x80]; 2796 }; 2797 2798 struct mlx5_ifc_dropped_packet_logged_bits { 2799 u8 reserved_at_0[0xe0]; 2800 }; 2801 2802 enum { 2803 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2804 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2805 }; 2806 2807 struct mlx5_ifc_cq_error_bits { 2808 u8 reserved_at_0[0x8]; 2809 u8 cqn[0x18]; 2810 2811 u8 reserved_at_20[0x20]; 2812 2813 u8 reserved_at_40[0x18]; 2814 u8 syndrome[0x8]; 2815 2816 u8 reserved_at_60[0x80]; 2817 }; 2818 2819 struct mlx5_ifc_rdma_page_fault_event_bits { 2820 u8 bytes_committed[0x20]; 2821 2822 u8 r_key[0x20]; 2823 2824 u8 reserved_at_40[0x10]; 2825 u8 packet_len[0x10]; 2826 2827 u8 rdma_op_len[0x20]; 2828 2829 u8 rdma_va[0x40]; 2830 2831 u8 reserved_at_c0[0x5]; 2832 u8 rdma[0x1]; 2833 u8 write[0x1]; 2834 u8 requestor[0x1]; 2835 u8 qp_number[0x18]; 2836 }; 2837 2838 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2839 u8 bytes_committed[0x20]; 2840 2841 u8 reserved_at_20[0x10]; 2842 u8 wqe_index[0x10]; 2843 2844 u8 reserved_at_40[0x10]; 2845 u8 len[0x10]; 2846 2847 u8 reserved_at_60[0x60]; 2848 2849 u8 reserved_at_c0[0x5]; 2850 u8 rdma[0x1]; 2851 u8 write_read[0x1]; 2852 u8 requestor[0x1]; 2853 u8 qpn[0x18]; 2854 }; 2855 2856 struct mlx5_ifc_qp_events_bits { 2857 u8 reserved_at_0[0xa0]; 2858 2859 u8 type[0x8]; 2860 u8 reserved_at_a8[0x18]; 2861 2862 u8 reserved_at_c0[0x8]; 2863 u8 qpn_rqn_sqn[0x18]; 2864 }; 2865 2866 struct mlx5_ifc_dct_events_bits { 2867 u8 reserved_at_0[0xc0]; 2868 2869 u8 reserved_at_c0[0x8]; 2870 u8 dct_number[0x18]; 2871 }; 2872 2873 struct mlx5_ifc_comp_event_bits { 2874 u8 reserved_at_0[0xc0]; 2875 2876 u8 reserved_at_c0[0x8]; 2877 u8 cq_number[0x18]; 2878 }; 2879 2880 enum { 2881 MLX5_QPC_STATE_RST = 0x0, 2882 MLX5_QPC_STATE_INIT = 0x1, 2883 MLX5_QPC_STATE_RTR = 0x2, 2884 MLX5_QPC_STATE_RTS = 0x3, 2885 MLX5_QPC_STATE_SQER = 0x4, 2886 MLX5_QPC_STATE_ERR = 0x6, 2887 MLX5_QPC_STATE_SQD = 0x7, 2888 MLX5_QPC_STATE_SUSPENDED = 0x9, 2889 }; 2890 2891 enum { 2892 MLX5_QPC_ST_RC = 0x0, 2893 MLX5_QPC_ST_UC = 0x1, 2894 MLX5_QPC_ST_UD = 0x2, 2895 MLX5_QPC_ST_XRC = 0x3, 2896 MLX5_QPC_ST_DCI = 0x5, 2897 MLX5_QPC_ST_QP0 = 0x7, 2898 MLX5_QPC_ST_QP1 = 0x8, 2899 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2900 MLX5_QPC_ST_REG_UMR = 0xc, 2901 }; 2902 2903 enum { 2904 MLX5_QPC_PM_STATE_ARMED = 0x0, 2905 MLX5_QPC_PM_STATE_REARM = 0x1, 2906 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2907 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2908 }; 2909 2910 enum { 2911 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2912 }; 2913 2914 enum { 2915 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2916 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2917 }; 2918 2919 enum { 2920 MLX5_QPC_MTU_256_BYTES = 0x1, 2921 MLX5_QPC_MTU_512_BYTES = 0x2, 2922 MLX5_QPC_MTU_1K_BYTES = 0x3, 2923 MLX5_QPC_MTU_2K_BYTES = 0x4, 2924 MLX5_QPC_MTU_4K_BYTES = 0x5, 2925 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2926 }; 2927 2928 enum { 2929 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2930 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2931 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2932 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2933 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2934 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2935 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2936 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2937 }; 2938 2939 enum { 2940 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2941 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2942 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2943 }; 2944 2945 enum { 2946 MLX5_QPC_CS_RES_DISABLE = 0x0, 2947 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2948 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2949 }; 2950 2951 enum { 2952 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2953 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2954 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2955 }; 2956 2957 struct mlx5_ifc_qpc_bits { 2958 u8 state[0x4]; 2959 u8 lag_tx_port_affinity[0x4]; 2960 u8 st[0x8]; 2961 u8 reserved_at_10[0x2]; 2962 u8 isolate_vl_tc[0x1]; 2963 u8 pm_state[0x2]; 2964 u8 reserved_at_15[0x1]; 2965 u8 req_e2e_credit_mode[0x2]; 2966 u8 offload_type[0x4]; 2967 u8 end_padding_mode[0x2]; 2968 u8 reserved_at_1e[0x2]; 2969 2970 u8 wq_signature[0x1]; 2971 u8 block_lb_mc[0x1]; 2972 u8 atomic_like_write_en[0x1]; 2973 u8 latency_sensitive[0x1]; 2974 u8 reserved_at_24[0x1]; 2975 u8 drain_sigerr[0x1]; 2976 u8 reserved_at_26[0x2]; 2977 u8 pd[0x18]; 2978 2979 u8 mtu[0x3]; 2980 u8 log_msg_max[0x5]; 2981 u8 reserved_at_48[0x1]; 2982 u8 log_rq_size[0x4]; 2983 u8 log_rq_stride[0x3]; 2984 u8 no_sq[0x1]; 2985 u8 log_sq_size[0x4]; 2986 u8 reserved_at_55[0x3]; 2987 u8 ts_format[0x2]; 2988 u8 reserved_at_5a[0x1]; 2989 u8 rlky[0x1]; 2990 u8 ulp_stateless_offload_mode[0x4]; 2991 2992 u8 counter_set_id[0x8]; 2993 u8 uar_page[0x18]; 2994 2995 u8 reserved_at_80[0x8]; 2996 u8 user_index[0x18]; 2997 2998 u8 reserved_at_a0[0x3]; 2999 u8 log_page_size[0x5]; 3000 u8 remote_qpn[0x18]; 3001 3002 struct mlx5_ifc_ads_bits primary_address_path; 3003 3004 struct mlx5_ifc_ads_bits secondary_address_path; 3005 3006 u8 log_ack_req_freq[0x4]; 3007 u8 reserved_at_384[0x4]; 3008 u8 log_sra_max[0x3]; 3009 u8 reserved_at_38b[0x2]; 3010 u8 retry_count[0x3]; 3011 u8 rnr_retry[0x3]; 3012 u8 reserved_at_393[0x1]; 3013 u8 fre[0x1]; 3014 u8 cur_rnr_retry[0x3]; 3015 u8 cur_retry_count[0x3]; 3016 u8 reserved_at_39b[0x5]; 3017 3018 u8 reserved_at_3a0[0x20]; 3019 3020 u8 reserved_at_3c0[0x8]; 3021 u8 next_send_psn[0x18]; 3022 3023 u8 reserved_at_3e0[0x8]; 3024 u8 cqn_snd[0x18]; 3025 3026 u8 reserved_at_400[0x8]; 3027 u8 deth_sqpn[0x18]; 3028 3029 u8 reserved_at_420[0x20]; 3030 3031 u8 reserved_at_440[0x8]; 3032 u8 last_acked_psn[0x18]; 3033 3034 u8 reserved_at_460[0x8]; 3035 u8 ssn[0x18]; 3036 3037 u8 reserved_at_480[0x8]; 3038 u8 log_rra_max[0x3]; 3039 u8 reserved_at_48b[0x1]; 3040 u8 atomic_mode[0x4]; 3041 u8 rre[0x1]; 3042 u8 rwe[0x1]; 3043 u8 rae[0x1]; 3044 u8 reserved_at_493[0x1]; 3045 u8 page_offset[0x6]; 3046 u8 reserved_at_49a[0x3]; 3047 u8 cd_slave_receive[0x1]; 3048 u8 cd_slave_send[0x1]; 3049 u8 cd_master[0x1]; 3050 3051 u8 reserved_at_4a0[0x3]; 3052 u8 min_rnr_nak[0x5]; 3053 u8 next_rcv_psn[0x18]; 3054 3055 u8 reserved_at_4c0[0x8]; 3056 u8 xrcd[0x18]; 3057 3058 u8 reserved_at_4e0[0x8]; 3059 u8 cqn_rcv[0x18]; 3060 3061 u8 dbr_addr[0x40]; 3062 3063 u8 q_key[0x20]; 3064 3065 u8 reserved_at_560[0x5]; 3066 u8 rq_type[0x3]; 3067 u8 srqn_rmpn_xrqn[0x18]; 3068 3069 u8 reserved_at_580[0x8]; 3070 u8 rmsn[0x18]; 3071 3072 u8 hw_sq_wqebb_counter[0x10]; 3073 u8 sw_sq_wqebb_counter[0x10]; 3074 3075 u8 hw_rq_counter[0x20]; 3076 3077 u8 sw_rq_counter[0x20]; 3078 3079 u8 reserved_at_600[0x20]; 3080 3081 u8 reserved_at_620[0xf]; 3082 u8 cgs[0x1]; 3083 u8 cs_req[0x8]; 3084 u8 cs_res[0x8]; 3085 3086 u8 dc_access_key[0x40]; 3087 3088 u8 reserved_at_680[0x3]; 3089 u8 dbr_umem_valid[0x1]; 3090 3091 u8 reserved_at_684[0xbc]; 3092 }; 3093 3094 struct mlx5_ifc_roce_addr_layout_bits { 3095 u8 source_l3_address[16][0x8]; 3096 3097 u8 reserved_at_80[0x3]; 3098 u8 vlan_valid[0x1]; 3099 u8 vlan_id[0xc]; 3100 u8 source_mac_47_32[0x10]; 3101 3102 u8 source_mac_31_0[0x20]; 3103 3104 u8 reserved_at_c0[0x14]; 3105 u8 roce_l3_type[0x4]; 3106 u8 roce_version[0x8]; 3107 3108 u8 reserved_at_e0[0x20]; 3109 }; 3110 3111 union mlx5_ifc_hca_cap_union_bits { 3112 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3113 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3114 struct mlx5_ifc_odp_cap_bits odp_cap; 3115 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3116 struct mlx5_ifc_roce_cap_bits roce_cap; 3117 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3118 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3119 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3120 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3121 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3122 struct mlx5_ifc_qos_cap_bits qos_cap; 3123 struct mlx5_ifc_debug_cap_bits debug_cap; 3124 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3125 struct mlx5_ifc_tls_cap_bits tls_cap; 3126 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3127 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3128 u8 reserved_at_0[0x8000]; 3129 }; 3130 3131 enum { 3132 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3133 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3134 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3135 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3136 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3137 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3138 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3139 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3140 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3141 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3142 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3143 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3144 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3145 }; 3146 3147 enum { 3148 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3149 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3150 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3151 }; 3152 3153 struct mlx5_ifc_vlan_bits { 3154 u8 ethtype[0x10]; 3155 u8 prio[0x3]; 3156 u8 cfi[0x1]; 3157 u8 vid[0xc]; 3158 }; 3159 3160 struct mlx5_ifc_flow_context_bits { 3161 struct mlx5_ifc_vlan_bits push_vlan; 3162 3163 u8 group_id[0x20]; 3164 3165 u8 reserved_at_40[0x8]; 3166 u8 flow_tag[0x18]; 3167 3168 u8 reserved_at_60[0x10]; 3169 u8 action[0x10]; 3170 3171 u8 extended_destination[0x1]; 3172 u8 reserved_at_81[0x1]; 3173 u8 flow_source[0x2]; 3174 u8 reserved_at_84[0x4]; 3175 u8 destination_list_size[0x18]; 3176 3177 u8 reserved_at_a0[0x8]; 3178 u8 flow_counter_list_size[0x18]; 3179 3180 u8 packet_reformat_id[0x20]; 3181 3182 u8 modify_header_id[0x20]; 3183 3184 struct mlx5_ifc_vlan_bits push_vlan_2; 3185 3186 u8 ipsec_obj_id[0x20]; 3187 u8 reserved_at_140[0xc0]; 3188 3189 struct mlx5_ifc_fte_match_param_bits match_value; 3190 3191 u8 reserved_at_1200[0x600]; 3192 3193 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3194 }; 3195 3196 enum { 3197 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3198 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3199 }; 3200 3201 struct mlx5_ifc_xrc_srqc_bits { 3202 u8 state[0x4]; 3203 u8 log_xrc_srq_size[0x4]; 3204 u8 reserved_at_8[0x18]; 3205 3206 u8 wq_signature[0x1]; 3207 u8 cont_srq[0x1]; 3208 u8 reserved_at_22[0x1]; 3209 u8 rlky[0x1]; 3210 u8 basic_cyclic_rcv_wqe[0x1]; 3211 u8 log_rq_stride[0x3]; 3212 u8 xrcd[0x18]; 3213 3214 u8 page_offset[0x6]; 3215 u8 reserved_at_46[0x1]; 3216 u8 dbr_umem_valid[0x1]; 3217 u8 cqn[0x18]; 3218 3219 u8 reserved_at_60[0x20]; 3220 3221 u8 user_index_equal_xrc_srqn[0x1]; 3222 u8 reserved_at_81[0x1]; 3223 u8 log_page_size[0x6]; 3224 u8 user_index[0x18]; 3225 3226 u8 reserved_at_a0[0x20]; 3227 3228 u8 reserved_at_c0[0x8]; 3229 u8 pd[0x18]; 3230 3231 u8 lwm[0x10]; 3232 u8 wqe_cnt[0x10]; 3233 3234 u8 reserved_at_100[0x40]; 3235 3236 u8 db_record_addr_h[0x20]; 3237 3238 u8 db_record_addr_l[0x1e]; 3239 u8 reserved_at_17e[0x2]; 3240 3241 u8 reserved_at_180[0x80]; 3242 }; 3243 3244 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3245 u8 counter_error_queues[0x20]; 3246 3247 u8 total_error_queues[0x20]; 3248 3249 u8 send_queue_priority_update_flow[0x20]; 3250 3251 u8 reserved_at_60[0x20]; 3252 3253 u8 nic_receive_steering_discard[0x40]; 3254 3255 u8 receive_discard_vport_down[0x40]; 3256 3257 u8 transmit_discard_vport_down[0x40]; 3258 3259 u8 reserved_at_140[0xa0]; 3260 3261 u8 internal_rq_out_of_buffer[0x20]; 3262 3263 u8 reserved_at_200[0xe00]; 3264 }; 3265 3266 struct mlx5_ifc_traffic_counter_bits { 3267 u8 packets[0x40]; 3268 3269 u8 octets[0x40]; 3270 }; 3271 3272 struct mlx5_ifc_tisc_bits { 3273 u8 strict_lag_tx_port_affinity[0x1]; 3274 u8 tls_en[0x1]; 3275 u8 reserved_at_2[0x2]; 3276 u8 lag_tx_port_affinity[0x04]; 3277 3278 u8 reserved_at_8[0x4]; 3279 u8 prio[0x4]; 3280 u8 reserved_at_10[0x10]; 3281 3282 u8 reserved_at_20[0x100]; 3283 3284 u8 reserved_at_120[0x8]; 3285 u8 transport_domain[0x18]; 3286 3287 u8 reserved_at_140[0x8]; 3288 u8 underlay_qpn[0x18]; 3289 3290 u8 reserved_at_160[0x8]; 3291 u8 pd[0x18]; 3292 3293 u8 reserved_at_180[0x380]; 3294 }; 3295 3296 enum { 3297 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3298 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3299 }; 3300 3301 enum { 3302 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3303 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3304 }; 3305 3306 enum { 3307 MLX5_RX_HASH_FN_NONE = 0x0, 3308 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3309 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3310 }; 3311 3312 enum { 3313 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3314 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3315 }; 3316 3317 struct mlx5_ifc_tirc_bits { 3318 u8 reserved_at_0[0x20]; 3319 3320 u8 disp_type[0x4]; 3321 u8 tls_en[0x1]; 3322 u8 reserved_at_25[0x1b]; 3323 3324 u8 reserved_at_40[0x40]; 3325 3326 u8 reserved_at_80[0x4]; 3327 u8 lro_timeout_period_usecs[0x10]; 3328 u8 lro_enable_mask[0x4]; 3329 u8 lro_max_ip_payload_size[0x8]; 3330 3331 u8 reserved_at_a0[0x40]; 3332 3333 u8 reserved_at_e0[0x8]; 3334 u8 inline_rqn[0x18]; 3335 3336 u8 rx_hash_symmetric[0x1]; 3337 u8 reserved_at_101[0x1]; 3338 u8 tunneled_offload_en[0x1]; 3339 u8 reserved_at_103[0x5]; 3340 u8 indirect_table[0x18]; 3341 3342 u8 rx_hash_fn[0x4]; 3343 u8 reserved_at_124[0x2]; 3344 u8 self_lb_block[0x2]; 3345 u8 transport_domain[0x18]; 3346 3347 u8 rx_hash_toeplitz_key[10][0x20]; 3348 3349 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3350 3351 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3352 3353 u8 reserved_at_2c0[0x4c0]; 3354 }; 3355 3356 enum { 3357 MLX5_SRQC_STATE_GOOD = 0x0, 3358 MLX5_SRQC_STATE_ERROR = 0x1, 3359 }; 3360 3361 struct mlx5_ifc_srqc_bits { 3362 u8 state[0x4]; 3363 u8 log_srq_size[0x4]; 3364 u8 reserved_at_8[0x18]; 3365 3366 u8 wq_signature[0x1]; 3367 u8 cont_srq[0x1]; 3368 u8 reserved_at_22[0x1]; 3369 u8 rlky[0x1]; 3370 u8 reserved_at_24[0x1]; 3371 u8 log_rq_stride[0x3]; 3372 u8 xrcd[0x18]; 3373 3374 u8 page_offset[0x6]; 3375 u8 reserved_at_46[0x2]; 3376 u8 cqn[0x18]; 3377 3378 u8 reserved_at_60[0x20]; 3379 3380 u8 reserved_at_80[0x2]; 3381 u8 log_page_size[0x6]; 3382 u8 reserved_at_88[0x18]; 3383 3384 u8 reserved_at_a0[0x20]; 3385 3386 u8 reserved_at_c0[0x8]; 3387 u8 pd[0x18]; 3388 3389 u8 lwm[0x10]; 3390 u8 wqe_cnt[0x10]; 3391 3392 u8 reserved_at_100[0x40]; 3393 3394 u8 dbr_addr[0x40]; 3395 3396 u8 reserved_at_180[0x80]; 3397 }; 3398 3399 enum { 3400 MLX5_SQC_STATE_RST = 0x0, 3401 MLX5_SQC_STATE_RDY = 0x1, 3402 MLX5_SQC_STATE_ERR = 0x3, 3403 }; 3404 3405 struct mlx5_ifc_sqc_bits { 3406 u8 rlky[0x1]; 3407 u8 cd_master[0x1]; 3408 u8 fre[0x1]; 3409 u8 flush_in_error_en[0x1]; 3410 u8 allow_multi_pkt_send_wqe[0x1]; 3411 u8 min_wqe_inline_mode[0x3]; 3412 u8 state[0x4]; 3413 u8 reg_umr[0x1]; 3414 u8 allow_swp[0x1]; 3415 u8 hairpin[0x1]; 3416 u8 reserved_at_f[0xb]; 3417 u8 ts_format[0x2]; 3418 u8 reserved_at_1c[0x4]; 3419 3420 u8 reserved_at_20[0x8]; 3421 u8 user_index[0x18]; 3422 3423 u8 reserved_at_40[0x8]; 3424 u8 cqn[0x18]; 3425 3426 u8 reserved_at_60[0x8]; 3427 u8 hairpin_peer_rq[0x18]; 3428 3429 u8 reserved_at_80[0x10]; 3430 u8 hairpin_peer_vhca[0x10]; 3431 3432 u8 reserved_at_a0[0x20]; 3433 3434 u8 reserved_at_c0[0x8]; 3435 u8 ts_cqe_to_dest_cqn[0x18]; 3436 3437 u8 reserved_at_e0[0x10]; 3438 u8 packet_pacing_rate_limit_index[0x10]; 3439 u8 tis_lst_sz[0x10]; 3440 u8 qos_queue_group_id[0x10]; 3441 3442 u8 reserved_at_120[0x40]; 3443 3444 u8 reserved_at_160[0x8]; 3445 u8 tis_num_0[0x18]; 3446 3447 struct mlx5_ifc_wq_bits wq; 3448 }; 3449 3450 enum { 3451 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3452 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3453 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3454 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3455 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3456 }; 3457 3458 enum { 3459 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3460 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3461 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3462 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3463 }; 3464 3465 struct mlx5_ifc_scheduling_context_bits { 3466 u8 element_type[0x8]; 3467 u8 reserved_at_8[0x18]; 3468 3469 u8 element_attributes[0x20]; 3470 3471 u8 parent_element_id[0x20]; 3472 3473 u8 reserved_at_60[0x40]; 3474 3475 u8 bw_share[0x20]; 3476 3477 u8 max_average_bw[0x20]; 3478 3479 u8 reserved_at_e0[0x120]; 3480 }; 3481 3482 struct mlx5_ifc_rqtc_bits { 3483 u8 reserved_at_0[0xa0]; 3484 3485 u8 reserved_at_a0[0x5]; 3486 u8 list_q_type[0x3]; 3487 u8 reserved_at_a8[0x8]; 3488 u8 rqt_max_size[0x10]; 3489 3490 u8 rq_vhca_id_format[0x1]; 3491 u8 reserved_at_c1[0xf]; 3492 u8 rqt_actual_size[0x10]; 3493 3494 u8 reserved_at_e0[0x6a0]; 3495 3496 struct mlx5_ifc_rq_num_bits rq_num[]; 3497 }; 3498 3499 enum { 3500 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3501 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3502 }; 3503 3504 enum { 3505 MLX5_RQC_STATE_RST = 0x0, 3506 MLX5_RQC_STATE_RDY = 0x1, 3507 MLX5_RQC_STATE_ERR = 0x3, 3508 }; 3509 3510 struct mlx5_ifc_rqc_bits { 3511 u8 rlky[0x1]; 3512 u8 delay_drop_en[0x1]; 3513 u8 scatter_fcs[0x1]; 3514 u8 vsd[0x1]; 3515 u8 mem_rq_type[0x4]; 3516 u8 state[0x4]; 3517 u8 reserved_at_c[0x1]; 3518 u8 flush_in_error_en[0x1]; 3519 u8 hairpin[0x1]; 3520 u8 reserved_at_f[0xb]; 3521 u8 ts_format[0x2]; 3522 u8 reserved_at_1c[0x4]; 3523 3524 u8 reserved_at_20[0x8]; 3525 u8 user_index[0x18]; 3526 3527 u8 reserved_at_40[0x8]; 3528 u8 cqn[0x18]; 3529 3530 u8 counter_set_id[0x8]; 3531 u8 reserved_at_68[0x18]; 3532 3533 u8 reserved_at_80[0x8]; 3534 u8 rmpn[0x18]; 3535 3536 u8 reserved_at_a0[0x8]; 3537 u8 hairpin_peer_sq[0x18]; 3538 3539 u8 reserved_at_c0[0x10]; 3540 u8 hairpin_peer_vhca[0x10]; 3541 3542 u8 reserved_at_e0[0xa0]; 3543 3544 struct mlx5_ifc_wq_bits wq; 3545 }; 3546 3547 enum { 3548 MLX5_RMPC_STATE_RDY = 0x1, 3549 MLX5_RMPC_STATE_ERR = 0x3, 3550 }; 3551 3552 struct mlx5_ifc_rmpc_bits { 3553 u8 reserved_at_0[0x8]; 3554 u8 state[0x4]; 3555 u8 reserved_at_c[0x14]; 3556 3557 u8 basic_cyclic_rcv_wqe[0x1]; 3558 u8 reserved_at_21[0x1f]; 3559 3560 u8 reserved_at_40[0x140]; 3561 3562 struct mlx5_ifc_wq_bits wq; 3563 }; 3564 3565 struct mlx5_ifc_nic_vport_context_bits { 3566 u8 reserved_at_0[0x5]; 3567 u8 min_wqe_inline_mode[0x3]; 3568 u8 reserved_at_8[0x15]; 3569 u8 disable_mc_local_lb[0x1]; 3570 u8 disable_uc_local_lb[0x1]; 3571 u8 roce_en[0x1]; 3572 3573 u8 arm_change_event[0x1]; 3574 u8 reserved_at_21[0x1a]; 3575 u8 event_on_mtu[0x1]; 3576 u8 event_on_promisc_change[0x1]; 3577 u8 event_on_vlan_change[0x1]; 3578 u8 event_on_mc_address_change[0x1]; 3579 u8 event_on_uc_address_change[0x1]; 3580 3581 u8 reserved_at_40[0xc]; 3582 3583 u8 affiliation_criteria[0x4]; 3584 u8 affiliated_vhca_id[0x10]; 3585 3586 u8 reserved_at_60[0xd0]; 3587 3588 u8 mtu[0x10]; 3589 3590 u8 system_image_guid[0x40]; 3591 u8 port_guid[0x40]; 3592 u8 node_guid[0x40]; 3593 3594 u8 reserved_at_200[0x140]; 3595 u8 qkey_violation_counter[0x10]; 3596 u8 reserved_at_350[0x430]; 3597 3598 u8 promisc_uc[0x1]; 3599 u8 promisc_mc[0x1]; 3600 u8 promisc_all[0x1]; 3601 u8 reserved_at_783[0x2]; 3602 u8 allowed_list_type[0x3]; 3603 u8 reserved_at_788[0xc]; 3604 u8 allowed_list_size[0xc]; 3605 3606 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3607 3608 u8 reserved_at_7e0[0x20]; 3609 3610 u8 current_uc_mac_address[][0x40]; 3611 }; 3612 3613 enum { 3614 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3615 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3616 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3617 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3618 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3619 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3620 }; 3621 3622 struct mlx5_ifc_mkc_bits { 3623 u8 reserved_at_0[0x1]; 3624 u8 free[0x1]; 3625 u8 reserved_at_2[0x1]; 3626 u8 access_mode_4_2[0x3]; 3627 u8 reserved_at_6[0x7]; 3628 u8 relaxed_ordering_write[0x1]; 3629 u8 reserved_at_e[0x1]; 3630 u8 small_fence_on_rdma_read_response[0x1]; 3631 u8 umr_en[0x1]; 3632 u8 a[0x1]; 3633 u8 rw[0x1]; 3634 u8 rr[0x1]; 3635 u8 lw[0x1]; 3636 u8 lr[0x1]; 3637 u8 access_mode_1_0[0x2]; 3638 u8 reserved_at_18[0x8]; 3639 3640 u8 qpn[0x18]; 3641 u8 mkey_7_0[0x8]; 3642 3643 u8 reserved_at_40[0x20]; 3644 3645 u8 length64[0x1]; 3646 u8 bsf_en[0x1]; 3647 u8 sync_umr[0x1]; 3648 u8 reserved_at_63[0x2]; 3649 u8 expected_sigerr_count[0x1]; 3650 u8 reserved_at_66[0x1]; 3651 u8 en_rinval[0x1]; 3652 u8 pd[0x18]; 3653 3654 u8 start_addr[0x40]; 3655 3656 u8 len[0x40]; 3657 3658 u8 bsf_octword_size[0x20]; 3659 3660 u8 reserved_at_120[0x80]; 3661 3662 u8 translations_octword_size[0x20]; 3663 3664 u8 reserved_at_1c0[0x19]; 3665 u8 relaxed_ordering_read[0x1]; 3666 u8 reserved_at_1d9[0x1]; 3667 u8 log_page_size[0x5]; 3668 3669 u8 reserved_at_1e0[0x20]; 3670 }; 3671 3672 struct mlx5_ifc_pkey_bits { 3673 u8 reserved_at_0[0x10]; 3674 u8 pkey[0x10]; 3675 }; 3676 3677 struct mlx5_ifc_array128_auto_bits { 3678 u8 array128_auto[16][0x8]; 3679 }; 3680 3681 struct mlx5_ifc_hca_vport_context_bits { 3682 u8 field_select[0x20]; 3683 3684 u8 reserved_at_20[0xe0]; 3685 3686 u8 sm_virt_aware[0x1]; 3687 u8 has_smi[0x1]; 3688 u8 has_raw[0x1]; 3689 u8 grh_required[0x1]; 3690 u8 reserved_at_104[0xc]; 3691 u8 port_physical_state[0x4]; 3692 u8 vport_state_policy[0x4]; 3693 u8 port_state[0x4]; 3694 u8 vport_state[0x4]; 3695 3696 u8 reserved_at_120[0x20]; 3697 3698 u8 system_image_guid[0x40]; 3699 3700 u8 port_guid[0x40]; 3701 3702 u8 node_guid[0x40]; 3703 3704 u8 cap_mask1[0x20]; 3705 3706 u8 cap_mask1_field_select[0x20]; 3707 3708 u8 cap_mask2[0x20]; 3709 3710 u8 cap_mask2_field_select[0x20]; 3711 3712 u8 reserved_at_280[0x80]; 3713 3714 u8 lid[0x10]; 3715 u8 reserved_at_310[0x4]; 3716 u8 init_type_reply[0x4]; 3717 u8 lmc[0x3]; 3718 u8 subnet_timeout[0x5]; 3719 3720 u8 sm_lid[0x10]; 3721 u8 sm_sl[0x4]; 3722 u8 reserved_at_334[0xc]; 3723 3724 u8 qkey_violation_counter[0x10]; 3725 u8 pkey_violation_counter[0x10]; 3726 3727 u8 reserved_at_360[0xca0]; 3728 }; 3729 3730 struct mlx5_ifc_esw_vport_context_bits { 3731 u8 fdb_to_vport_reg_c[0x1]; 3732 u8 reserved_at_1[0x2]; 3733 u8 vport_svlan_strip[0x1]; 3734 u8 vport_cvlan_strip[0x1]; 3735 u8 vport_svlan_insert[0x1]; 3736 u8 vport_cvlan_insert[0x2]; 3737 u8 fdb_to_vport_reg_c_id[0x8]; 3738 u8 reserved_at_10[0x10]; 3739 3740 u8 reserved_at_20[0x20]; 3741 3742 u8 svlan_cfi[0x1]; 3743 u8 svlan_pcp[0x3]; 3744 u8 svlan_id[0xc]; 3745 u8 cvlan_cfi[0x1]; 3746 u8 cvlan_pcp[0x3]; 3747 u8 cvlan_id[0xc]; 3748 3749 u8 reserved_at_60[0x720]; 3750 3751 u8 sw_steering_vport_icm_address_rx[0x40]; 3752 3753 u8 sw_steering_vport_icm_address_tx[0x40]; 3754 }; 3755 3756 enum { 3757 MLX5_EQC_STATUS_OK = 0x0, 3758 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3759 }; 3760 3761 enum { 3762 MLX5_EQC_ST_ARMED = 0x9, 3763 MLX5_EQC_ST_FIRED = 0xa, 3764 }; 3765 3766 struct mlx5_ifc_eqc_bits { 3767 u8 status[0x4]; 3768 u8 reserved_at_4[0x9]; 3769 u8 ec[0x1]; 3770 u8 oi[0x1]; 3771 u8 reserved_at_f[0x5]; 3772 u8 st[0x4]; 3773 u8 reserved_at_18[0x8]; 3774 3775 u8 reserved_at_20[0x20]; 3776 3777 u8 reserved_at_40[0x14]; 3778 u8 page_offset[0x6]; 3779 u8 reserved_at_5a[0x6]; 3780 3781 u8 reserved_at_60[0x3]; 3782 u8 log_eq_size[0x5]; 3783 u8 uar_page[0x18]; 3784 3785 u8 reserved_at_80[0x20]; 3786 3787 u8 reserved_at_a0[0x14]; 3788 u8 intr[0xc]; 3789 3790 u8 reserved_at_c0[0x3]; 3791 u8 log_page_size[0x5]; 3792 u8 reserved_at_c8[0x18]; 3793 3794 u8 reserved_at_e0[0x60]; 3795 3796 u8 reserved_at_140[0x8]; 3797 u8 consumer_counter[0x18]; 3798 3799 u8 reserved_at_160[0x8]; 3800 u8 producer_counter[0x18]; 3801 3802 u8 reserved_at_180[0x80]; 3803 }; 3804 3805 enum { 3806 MLX5_DCTC_STATE_ACTIVE = 0x0, 3807 MLX5_DCTC_STATE_DRAINING = 0x1, 3808 MLX5_DCTC_STATE_DRAINED = 0x2, 3809 }; 3810 3811 enum { 3812 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3813 MLX5_DCTC_CS_RES_NA = 0x1, 3814 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3815 }; 3816 3817 enum { 3818 MLX5_DCTC_MTU_256_BYTES = 0x1, 3819 MLX5_DCTC_MTU_512_BYTES = 0x2, 3820 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3821 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3822 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3823 }; 3824 3825 struct mlx5_ifc_dctc_bits { 3826 u8 reserved_at_0[0x4]; 3827 u8 state[0x4]; 3828 u8 reserved_at_8[0x18]; 3829 3830 u8 reserved_at_20[0x8]; 3831 u8 user_index[0x18]; 3832 3833 u8 reserved_at_40[0x8]; 3834 u8 cqn[0x18]; 3835 3836 u8 counter_set_id[0x8]; 3837 u8 atomic_mode[0x4]; 3838 u8 rre[0x1]; 3839 u8 rwe[0x1]; 3840 u8 rae[0x1]; 3841 u8 atomic_like_write_en[0x1]; 3842 u8 latency_sensitive[0x1]; 3843 u8 rlky[0x1]; 3844 u8 free_ar[0x1]; 3845 u8 reserved_at_73[0xd]; 3846 3847 u8 reserved_at_80[0x8]; 3848 u8 cs_res[0x8]; 3849 u8 reserved_at_90[0x3]; 3850 u8 min_rnr_nak[0x5]; 3851 u8 reserved_at_98[0x8]; 3852 3853 u8 reserved_at_a0[0x8]; 3854 u8 srqn_xrqn[0x18]; 3855 3856 u8 reserved_at_c0[0x8]; 3857 u8 pd[0x18]; 3858 3859 u8 tclass[0x8]; 3860 u8 reserved_at_e8[0x4]; 3861 u8 flow_label[0x14]; 3862 3863 u8 dc_access_key[0x40]; 3864 3865 u8 reserved_at_140[0x5]; 3866 u8 mtu[0x3]; 3867 u8 port[0x8]; 3868 u8 pkey_index[0x10]; 3869 3870 u8 reserved_at_160[0x8]; 3871 u8 my_addr_index[0x8]; 3872 u8 reserved_at_170[0x8]; 3873 u8 hop_limit[0x8]; 3874 3875 u8 dc_access_key_violation_count[0x20]; 3876 3877 u8 reserved_at_1a0[0x14]; 3878 u8 dei_cfi[0x1]; 3879 u8 eth_prio[0x3]; 3880 u8 ecn[0x2]; 3881 u8 dscp[0x6]; 3882 3883 u8 reserved_at_1c0[0x20]; 3884 u8 ece[0x20]; 3885 }; 3886 3887 enum { 3888 MLX5_CQC_STATUS_OK = 0x0, 3889 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3890 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3891 }; 3892 3893 enum { 3894 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3895 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3896 }; 3897 3898 enum { 3899 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3900 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3901 MLX5_CQC_ST_FIRED = 0xa, 3902 }; 3903 3904 enum { 3905 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3906 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3907 MLX5_CQ_PERIOD_NUM_MODES 3908 }; 3909 3910 struct mlx5_ifc_cqc_bits { 3911 u8 status[0x4]; 3912 u8 reserved_at_4[0x2]; 3913 u8 dbr_umem_valid[0x1]; 3914 u8 apu_thread_cq[0x1]; 3915 u8 cqe_sz[0x3]; 3916 u8 cc[0x1]; 3917 u8 reserved_at_c[0x1]; 3918 u8 scqe_break_moderation_en[0x1]; 3919 u8 oi[0x1]; 3920 u8 cq_period_mode[0x2]; 3921 u8 cqe_comp_en[0x1]; 3922 u8 mini_cqe_res_format[0x2]; 3923 u8 st[0x4]; 3924 u8 reserved_at_18[0x8]; 3925 3926 u8 reserved_at_20[0x20]; 3927 3928 u8 reserved_at_40[0x14]; 3929 u8 page_offset[0x6]; 3930 u8 reserved_at_5a[0x6]; 3931 3932 u8 reserved_at_60[0x3]; 3933 u8 log_cq_size[0x5]; 3934 u8 uar_page[0x18]; 3935 3936 u8 reserved_at_80[0x4]; 3937 u8 cq_period[0xc]; 3938 u8 cq_max_count[0x10]; 3939 3940 u8 reserved_at_a0[0x18]; 3941 u8 c_eqn[0x8]; 3942 3943 u8 reserved_at_c0[0x3]; 3944 u8 log_page_size[0x5]; 3945 u8 reserved_at_c8[0x18]; 3946 3947 u8 reserved_at_e0[0x20]; 3948 3949 u8 reserved_at_100[0x8]; 3950 u8 last_notified_index[0x18]; 3951 3952 u8 reserved_at_120[0x8]; 3953 u8 last_solicit_index[0x18]; 3954 3955 u8 reserved_at_140[0x8]; 3956 u8 consumer_counter[0x18]; 3957 3958 u8 reserved_at_160[0x8]; 3959 u8 producer_counter[0x18]; 3960 3961 u8 reserved_at_180[0x40]; 3962 3963 u8 dbr_addr[0x40]; 3964 }; 3965 3966 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3967 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3968 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3969 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3970 u8 reserved_at_0[0x800]; 3971 }; 3972 3973 struct mlx5_ifc_query_adapter_param_block_bits { 3974 u8 reserved_at_0[0xc0]; 3975 3976 u8 reserved_at_c0[0x8]; 3977 u8 ieee_vendor_id[0x18]; 3978 3979 u8 reserved_at_e0[0x10]; 3980 u8 vsd_vendor_id[0x10]; 3981 3982 u8 vsd[208][0x8]; 3983 3984 u8 vsd_contd_psid[16][0x8]; 3985 }; 3986 3987 enum { 3988 MLX5_XRQC_STATE_GOOD = 0x0, 3989 MLX5_XRQC_STATE_ERROR = 0x1, 3990 }; 3991 3992 enum { 3993 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3994 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3995 }; 3996 3997 enum { 3998 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3999 }; 4000 4001 struct mlx5_ifc_tag_matching_topology_context_bits { 4002 u8 log_matching_list_sz[0x4]; 4003 u8 reserved_at_4[0xc]; 4004 u8 append_next_index[0x10]; 4005 4006 u8 sw_phase_cnt[0x10]; 4007 u8 hw_phase_cnt[0x10]; 4008 4009 u8 reserved_at_40[0x40]; 4010 }; 4011 4012 struct mlx5_ifc_xrqc_bits { 4013 u8 state[0x4]; 4014 u8 rlkey[0x1]; 4015 u8 reserved_at_5[0xf]; 4016 u8 topology[0x4]; 4017 u8 reserved_at_18[0x4]; 4018 u8 offload[0x4]; 4019 4020 u8 reserved_at_20[0x8]; 4021 u8 user_index[0x18]; 4022 4023 u8 reserved_at_40[0x8]; 4024 u8 cqn[0x18]; 4025 4026 u8 reserved_at_60[0xa0]; 4027 4028 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4029 4030 u8 reserved_at_180[0x280]; 4031 4032 struct mlx5_ifc_wq_bits wq; 4033 }; 4034 4035 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4036 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4037 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4038 u8 reserved_at_0[0x20]; 4039 }; 4040 4041 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4042 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4043 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4044 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4045 u8 reserved_at_0[0x20]; 4046 }; 4047 4048 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4049 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4050 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4051 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4052 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4053 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4054 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4055 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4056 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4057 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4058 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4059 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4060 u8 reserved_at_0[0x7c0]; 4061 }; 4062 4063 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4064 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4065 u8 reserved_at_0[0x7c0]; 4066 }; 4067 4068 union mlx5_ifc_event_auto_bits { 4069 struct mlx5_ifc_comp_event_bits comp_event; 4070 struct mlx5_ifc_dct_events_bits dct_events; 4071 struct mlx5_ifc_qp_events_bits qp_events; 4072 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4073 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4074 struct mlx5_ifc_cq_error_bits cq_error; 4075 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4076 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4077 struct mlx5_ifc_gpio_event_bits gpio_event; 4078 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4079 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4080 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4081 u8 reserved_at_0[0xe0]; 4082 }; 4083 4084 struct mlx5_ifc_health_buffer_bits { 4085 u8 reserved_at_0[0x100]; 4086 4087 u8 assert_existptr[0x20]; 4088 4089 u8 assert_callra[0x20]; 4090 4091 u8 reserved_at_140[0x40]; 4092 4093 u8 fw_version[0x20]; 4094 4095 u8 hw_id[0x20]; 4096 4097 u8 reserved_at_1c0[0x20]; 4098 4099 u8 irisc_index[0x8]; 4100 u8 synd[0x8]; 4101 u8 ext_synd[0x10]; 4102 }; 4103 4104 struct mlx5_ifc_register_loopback_control_bits { 4105 u8 no_lb[0x1]; 4106 u8 reserved_at_1[0x7]; 4107 u8 port[0x8]; 4108 u8 reserved_at_10[0x10]; 4109 4110 u8 reserved_at_20[0x60]; 4111 }; 4112 4113 struct mlx5_ifc_vport_tc_element_bits { 4114 u8 traffic_class[0x4]; 4115 u8 reserved_at_4[0xc]; 4116 u8 vport_number[0x10]; 4117 }; 4118 4119 struct mlx5_ifc_vport_element_bits { 4120 u8 reserved_at_0[0x10]; 4121 u8 vport_number[0x10]; 4122 }; 4123 4124 enum { 4125 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4126 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4127 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4128 }; 4129 4130 struct mlx5_ifc_tsar_element_bits { 4131 u8 reserved_at_0[0x8]; 4132 u8 tsar_type[0x8]; 4133 u8 reserved_at_10[0x10]; 4134 }; 4135 4136 enum { 4137 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4138 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4139 }; 4140 4141 struct mlx5_ifc_teardown_hca_out_bits { 4142 u8 status[0x8]; 4143 u8 reserved_at_8[0x18]; 4144 4145 u8 syndrome[0x20]; 4146 4147 u8 reserved_at_40[0x3f]; 4148 4149 u8 state[0x1]; 4150 }; 4151 4152 enum { 4153 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4154 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4155 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4156 }; 4157 4158 struct mlx5_ifc_teardown_hca_in_bits { 4159 u8 opcode[0x10]; 4160 u8 reserved_at_10[0x10]; 4161 4162 u8 reserved_at_20[0x10]; 4163 u8 op_mod[0x10]; 4164 4165 u8 reserved_at_40[0x10]; 4166 u8 profile[0x10]; 4167 4168 u8 reserved_at_60[0x20]; 4169 }; 4170 4171 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4172 u8 status[0x8]; 4173 u8 reserved_at_8[0x18]; 4174 4175 u8 syndrome[0x20]; 4176 4177 u8 reserved_at_40[0x40]; 4178 }; 4179 4180 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4181 u8 opcode[0x10]; 4182 u8 uid[0x10]; 4183 4184 u8 reserved_at_20[0x10]; 4185 u8 op_mod[0x10]; 4186 4187 u8 reserved_at_40[0x8]; 4188 u8 qpn[0x18]; 4189 4190 u8 reserved_at_60[0x20]; 4191 4192 u8 opt_param_mask[0x20]; 4193 4194 u8 reserved_at_a0[0x20]; 4195 4196 struct mlx5_ifc_qpc_bits qpc; 4197 4198 u8 reserved_at_800[0x80]; 4199 }; 4200 4201 struct mlx5_ifc_sqd2rts_qp_out_bits { 4202 u8 status[0x8]; 4203 u8 reserved_at_8[0x18]; 4204 4205 u8 syndrome[0x20]; 4206 4207 u8 reserved_at_40[0x40]; 4208 }; 4209 4210 struct mlx5_ifc_sqd2rts_qp_in_bits { 4211 u8 opcode[0x10]; 4212 u8 uid[0x10]; 4213 4214 u8 reserved_at_20[0x10]; 4215 u8 op_mod[0x10]; 4216 4217 u8 reserved_at_40[0x8]; 4218 u8 qpn[0x18]; 4219 4220 u8 reserved_at_60[0x20]; 4221 4222 u8 opt_param_mask[0x20]; 4223 4224 u8 reserved_at_a0[0x20]; 4225 4226 struct mlx5_ifc_qpc_bits qpc; 4227 4228 u8 reserved_at_800[0x80]; 4229 }; 4230 4231 struct mlx5_ifc_set_roce_address_out_bits { 4232 u8 status[0x8]; 4233 u8 reserved_at_8[0x18]; 4234 4235 u8 syndrome[0x20]; 4236 4237 u8 reserved_at_40[0x40]; 4238 }; 4239 4240 struct mlx5_ifc_set_roce_address_in_bits { 4241 u8 opcode[0x10]; 4242 u8 reserved_at_10[0x10]; 4243 4244 u8 reserved_at_20[0x10]; 4245 u8 op_mod[0x10]; 4246 4247 u8 roce_address_index[0x10]; 4248 u8 reserved_at_50[0xc]; 4249 u8 vhca_port_num[0x4]; 4250 4251 u8 reserved_at_60[0x20]; 4252 4253 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4254 }; 4255 4256 struct mlx5_ifc_set_mad_demux_out_bits { 4257 u8 status[0x8]; 4258 u8 reserved_at_8[0x18]; 4259 4260 u8 syndrome[0x20]; 4261 4262 u8 reserved_at_40[0x40]; 4263 }; 4264 4265 enum { 4266 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4267 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4268 }; 4269 4270 struct mlx5_ifc_set_mad_demux_in_bits { 4271 u8 opcode[0x10]; 4272 u8 reserved_at_10[0x10]; 4273 4274 u8 reserved_at_20[0x10]; 4275 u8 op_mod[0x10]; 4276 4277 u8 reserved_at_40[0x20]; 4278 4279 u8 reserved_at_60[0x6]; 4280 u8 demux_mode[0x2]; 4281 u8 reserved_at_68[0x18]; 4282 }; 4283 4284 struct mlx5_ifc_set_l2_table_entry_out_bits { 4285 u8 status[0x8]; 4286 u8 reserved_at_8[0x18]; 4287 4288 u8 syndrome[0x20]; 4289 4290 u8 reserved_at_40[0x40]; 4291 }; 4292 4293 struct mlx5_ifc_set_l2_table_entry_in_bits { 4294 u8 opcode[0x10]; 4295 u8 reserved_at_10[0x10]; 4296 4297 u8 reserved_at_20[0x10]; 4298 u8 op_mod[0x10]; 4299 4300 u8 reserved_at_40[0x60]; 4301 4302 u8 reserved_at_a0[0x8]; 4303 u8 table_index[0x18]; 4304 4305 u8 reserved_at_c0[0x20]; 4306 4307 u8 reserved_at_e0[0x13]; 4308 u8 vlan_valid[0x1]; 4309 u8 vlan[0xc]; 4310 4311 struct mlx5_ifc_mac_address_layout_bits mac_address; 4312 4313 u8 reserved_at_140[0xc0]; 4314 }; 4315 4316 struct mlx5_ifc_set_issi_out_bits { 4317 u8 status[0x8]; 4318 u8 reserved_at_8[0x18]; 4319 4320 u8 syndrome[0x20]; 4321 4322 u8 reserved_at_40[0x40]; 4323 }; 4324 4325 struct mlx5_ifc_set_issi_in_bits { 4326 u8 opcode[0x10]; 4327 u8 reserved_at_10[0x10]; 4328 4329 u8 reserved_at_20[0x10]; 4330 u8 op_mod[0x10]; 4331 4332 u8 reserved_at_40[0x10]; 4333 u8 current_issi[0x10]; 4334 4335 u8 reserved_at_60[0x20]; 4336 }; 4337 4338 struct mlx5_ifc_set_hca_cap_out_bits { 4339 u8 status[0x8]; 4340 u8 reserved_at_8[0x18]; 4341 4342 u8 syndrome[0x20]; 4343 4344 u8 reserved_at_40[0x40]; 4345 }; 4346 4347 struct mlx5_ifc_set_hca_cap_in_bits { 4348 u8 opcode[0x10]; 4349 u8 reserved_at_10[0x10]; 4350 4351 u8 reserved_at_20[0x10]; 4352 u8 op_mod[0x10]; 4353 4354 u8 other_function[0x1]; 4355 u8 reserved_at_41[0xf]; 4356 u8 function_id[0x10]; 4357 4358 u8 reserved_at_60[0x20]; 4359 4360 union mlx5_ifc_hca_cap_union_bits capability; 4361 }; 4362 4363 enum { 4364 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4365 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4366 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4367 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4368 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4369 }; 4370 4371 struct mlx5_ifc_set_fte_out_bits { 4372 u8 status[0x8]; 4373 u8 reserved_at_8[0x18]; 4374 4375 u8 syndrome[0x20]; 4376 4377 u8 reserved_at_40[0x40]; 4378 }; 4379 4380 struct mlx5_ifc_set_fte_in_bits { 4381 u8 opcode[0x10]; 4382 u8 reserved_at_10[0x10]; 4383 4384 u8 reserved_at_20[0x10]; 4385 u8 op_mod[0x10]; 4386 4387 u8 other_vport[0x1]; 4388 u8 reserved_at_41[0xf]; 4389 u8 vport_number[0x10]; 4390 4391 u8 reserved_at_60[0x20]; 4392 4393 u8 table_type[0x8]; 4394 u8 reserved_at_88[0x18]; 4395 4396 u8 reserved_at_a0[0x8]; 4397 u8 table_id[0x18]; 4398 4399 u8 ignore_flow_level[0x1]; 4400 u8 reserved_at_c1[0x17]; 4401 u8 modify_enable_mask[0x8]; 4402 4403 u8 reserved_at_e0[0x20]; 4404 4405 u8 flow_index[0x20]; 4406 4407 u8 reserved_at_120[0xe0]; 4408 4409 struct mlx5_ifc_flow_context_bits flow_context; 4410 }; 4411 4412 struct mlx5_ifc_rts2rts_qp_out_bits { 4413 u8 status[0x8]; 4414 u8 reserved_at_8[0x18]; 4415 4416 u8 syndrome[0x20]; 4417 4418 u8 reserved_at_40[0x20]; 4419 u8 ece[0x20]; 4420 }; 4421 4422 struct mlx5_ifc_rts2rts_qp_in_bits { 4423 u8 opcode[0x10]; 4424 u8 uid[0x10]; 4425 4426 u8 reserved_at_20[0x10]; 4427 u8 op_mod[0x10]; 4428 4429 u8 reserved_at_40[0x8]; 4430 u8 qpn[0x18]; 4431 4432 u8 reserved_at_60[0x20]; 4433 4434 u8 opt_param_mask[0x20]; 4435 4436 u8 ece[0x20]; 4437 4438 struct mlx5_ifc_qpc_bits qpc; 4439 4440 u8 reserved_at_800[0x80]; 4441 }; 4442 4443 struct mlx5_ifc_rtr2rts_qp_out_bits { 4444 u8 status[0x8]; 4445 u8 reserved_at_8[0x18]; 4446 4447 u8 syndrome[0x20]; 4448 4449 u8 reserved_at_40[0x20]; 4450 u8 ece[0x20]; 4451 }; 4452 4453 struct mlx5_ifc_rtr2rts_qp_in_bits { 4454 u8 opcode[0x10]; 4455 u8 uid[0x10]; 4456 4457 u8 reserved_at_20[0x10]; 4458 u8 op_mod[0x10]; 4459 4460 u8 reserved_at_40[0x8]; 4461 u8 qpn[0x18]; 4462 4463 u8 reserved_at_60[0x20]; 4464 4465 u8 opt_param_mask[0x20]; 4466 4467 u8 ece[0x20]; 4468 4469 struct mlx5_ifc_qpc_bits qpc; 4470 4471 u8 reserved_at_800[0x80]; 4472 }; 4473 4474 struct mlx5_ifc_rst2init_qp_out_bits { 4475 u8 status[0x8]; 4476 u8 reserved_at_8[0x18]; 4477 4478 u8 syndrome[0x20]; 4479 4480 u8 reserved_at_40[0x20]; 4481 u8 ece[0x20]; 4482 }; 4483 4484 struct mlx5_ifc_rst2init_qp_in_bits { 4485 u8 opcode[0x10]; 4486 u8 uid[0x10]; 4487 4488 u8 reserved_at_20[0x10]; 4489 u8 op_mod[0x10]; 4490 4491 u8 reserved_at_40[0x8]; 4492 u8 qpn[0x18]; 4493 4494 u8 reserved_at_60[0x20]; 4495 4496 u8 opt_param_mask[0x20]; 4497 4498 u8 ece[0x20]; 4499 4500 struct mlx5_ifc_qpc_bits qpc; 4501 4502 u8 reserved_at_800[0x80]; 4503 }; 4504 4505 struct mlx5_ifc_query_xrq_out_bits { 4506 u8 status[0x8]; 4507 u8 reserved_at_8[0x18]; 4508 4509 u8 syndrome[0x20]; 4510 4511 u8 reserved_at_40[0x40]; 4512 4513 struct mlx5_ifc_xrqc_bits xrq_context; 4514 }; 4515 4516 struct mlx5_ifc_query_xrq_in_bits { 4517 u8 opcode[0x10]; 4518 u8 reserved_at_10[0x10]; 4519 4520 u8 reserved_at_20[0x10]; 4521 u8 op_mod[0x10]; 4522 4523 u8 reserved_at_40[0x8]; 4524 u8 xrqn[0x18]; 4525 4526 u8 reserved_at_60[0x20]; 4527 }; 4528 4529 struct mlx5_ifc_query_xrc_srq_out_bits { 4530 u8 status[0x8]; 4531 u8 reserved_at_8[0x18]; 4532 4533 u8 syndrome[0x20]; 4534 4535 u8 reserved_at_40[0x40]; 4536 4537 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4538 4539 u8 reserved_at_280[0x600]; 4540 4541 u8 pas[][0x40]; 4542 }; 4543 4544 struct mlx5_ifc_query_xrc_srq_in_bits { 4545 u8 opcode[0x10]; 4546 u8 reserved_at_10[0x10]; 4547 4548 u8 reserved_at_20[0x10]; 4549 u8 op_mod[0x10]; 4550 4551 u8 reserved_at_40[0x8]; 4552 u8 xrc_srqn[0x18]; 4553 4554 u8 reserved_at_60[0x20]; 4555 }; 4556 4557 enum { 4558 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4559 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4560 }; 4561 4562 struct mlx5_ifc_query_vport_state_out_bits { 4563 u8 status[0x8]; 4564 u8 reserved_at_8[0x18]; 4565 4566 u8 syndrome[0x20]; 4567 4568 u8 reserved_at_40[0x20]; 4569 4570 u8 reserved_at_60[0x18]; 4571 u8 admin_state[0x4]; 4572 u8 state[0x4]; 4573 }; 4574 4575 enum { 4576 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4577 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4578 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4579 }; 4580 4581 struct mlx5_ifc_arm_monitor_counter_in_bits { 4582 u8 opcode[0x10]; 4583 u8 uid[0x10]; 4584 4585 u8 reserved_at_20[0x10]; 4586 u8 op_mod[0x10]; 4587 4588 u8 reserved_at_40[0x20]; 4589 4590 u8 reserved_at_60[0x20]; 4591 }; 4592 4593 struct mlx5_ifc_arm_monitor_counter_out_bits { 4594 u8 status[0x8]; 4595 u8 reserved_at_8[0x18]; 4596 4597 u8 syndrome[0x20]; 4598 4599 u8 reserved_at_40[0x40]; 4600 }; 4601 4602 enum { 4603 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4604 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4605 }; 4606 4607 enum mlx5_monitor_counter_ppcnt { 4608 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4609 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4610 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4611 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4612 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4613 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4614 }; 4615 4616 enum { 4617 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4618 }; 4619 4620 struct mlx5_ifc_monitor_counter_output_bits { 4621 u8 reserved_at_0[0x4]; 4622 u8 type[0x4]; 4623 u8 reserved_at_8[0x8]; 4624 u8 counter[0x10]; 4625 4626 u8 counter_group_id[0x20]; 4627 }; 4628 4629 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4630 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4631 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4632 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4633 4634 struct mlx5_ifc_set_monitor_counter_in_bits { 4635 u8 opcode[0x10]; 4636 u8 uid[0x10]; 4637 4638 u8 reserved_at_20[0x10]; 4639 u8 op_mod[0x10]; 4640 4641 u8 reserved_at_40[0x10]; 4642 u8 num_of_counters[0x10]; 4643 4644 u8 reserved_at_60[0x20]; 4645 4646 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4647 }; 4648 4649 struct mlx5_ifc_set_monitor_counter_out_bits { 4650 u8 status[0x8]; 4651 u8 reserved_at_8[0x18]; 4652 4653 u8 syndrome[0x20]; 4654 4655 u8 reserved_at_40[0x40]; 4656 }; 4657 4658 struct mlx5_ifc_query_vport_state_in_bits { 4659 u8 opcode[0x10]; 4660 u8 reserved_at_10[0x10]; 4661 4662 u8 reserved_at_20[0x10]; 4663 u8 op_mod[0x10]; 4664 4665 u8 other_vport[0x1]; 4666 u8 reserved_at_41[0xf]; 4667 u8 vport_number[0x10]; 4668 4669 u8 reserved_at_60[0x20]; 4670 }; 4671 4672 struct mlx5_ifc_query_vnic_env_out_bits { 4673 u8 status[0x8]; 4674 u8 reserved_at_8[0x18]; 4675 4676 u8 syndrome[0x20]; 4677 4678 u8 reserved_at_40[0x40]; 4679 4680 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4681 }; 4682 4683 enum { 4684 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4685 }; 4686 4687 struct mlx5_ifc_query_vnic_env_in_bits { 4688 u8 opcode[0x10]; 4689 u8 reserved_at_10[0x10]; 4690 4691 u8 reserved_at_20[0x10]; 4692 u8 op_mod[0x10]; 4693 4694 u8 other_vport[0x1]; 4695 u8 reserved_at_41[0xf]; 4696 u8 vport_number[0x10]; 4697 4698 u8 reserved_at_60[0x20]; 4699 }; 4700 4701 struct mlx5_ifc_query_vport_counter_out_bits { 4702 u8 status[0x8]; 4703 u8 reserved_at_8[0x18]; 4704 4705 u8 syndrome[0x20]; 4706 4707 u8 reserved_at_40[0x40]; 4708 4709 struct mlx5_ifc_traffic_counter_bits received_errors; 4710 4711 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4712 4713 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4714 4715 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4716 4717 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4718 4719 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4720 4721 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4722 4723 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4724 4725 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4726 4727 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4728 4729 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4730 4731 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4732 4733 u8 reserved_at_680[0xa00]; 4734 }; 4735 4736 enum { 4737 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4738 }; 4739 4740 struct mlx5_ifc_query_vport_counter_in_bits { 4741 u8 opcode[0x10]; 4742 u8 reserved_at_10[0x10]; 4743 4744 u8 reserved_at_20[0x10]; 4745 u8 op_mod[0x10]; 4746 4747 u8 other_vport[0x1]; 4748 u8 reserved_at_41[0xb]; 4749 u8 port_num[0x4]; 4750 u8 vport_number[0x10]; 4751 4752 u8 reserved_at_60[0x60]; 4753 4754 u8 clear[0x1]; 4755 u8 reserved_at_c1[0x1f]; 4756 4757 u8 reserved_at_e0[0x20]; 4758 }; 4759 4760 struct mlx5_ifc_query_tis_out_bits { 4761 u8 status[0x8]; 4762 u8 reserved_at_8[0x18]; 4763 4764 u8 syndrome[0x20]; 4765 4766 u8 reserved_at_40[0x40]; 4767 4768 struct mlx5_ifc_tisc_bits tis_context; 4769 }; 4770 4771 struct mlx5_ifc_query_tis_in_bits { 4772 u8 opcode[0x10]; 4773 u8 reserved_at_10[0x10]; 4774 4775 u8 reserved_at_20[0x10]; 4776 u8 op_mod[0x10]; 4777 4778 u8 reserved_at_40[0x8]; 4779 u8 tisn[0x18]; 4780 4781 u8 reserved_at_60[0x20]; 4782 }; 4783 4784 struct mlx5_ifc_query_tir_out_bits { 4785 u8 status[0x8]; 4786 u8 reserved_at_8[0x18]; 4787 4788 u8 syndrome[0x20]; 4789 4790 u8 reserved_at_40[0xc0]; 4791 4792 struct mlx5_ifc_tirc_bits tir_context; 4793 }; 4794 4795 struct mlx5_ifc_query_tir_in_bits { 4796 u8 opcode[0x10]; 4797 u8 reserved_at_10[0x10]; 4798 4799 u8 reserved_at_20[0x10]; 4800 u8 op_mod[0x10]; 4801 4802 u8 reserved_at_40[0x8]; 4803 u8 tirn[0x18]; 4804 4805 u8 reserved_at_60[0x20]; 4806 }; 4807 4808 struct mlx5_ifc_query_srq_out_bits { 4809 u8 status[0x8]; 4810 u8 reserved_at_8[0x18]; 4811 4812 u8 syndrome[0x20]; 4813 4814 u8 reserved_at_40[0x40]; 4815 4816 struct mlx5_ifc_srqc_bits srq_context_entry; 4817 4818 u8 reserved_at_280[0x600]; 4819 4820 u8 pas[][0x40]; 4821 }; 4822 4823 struct mlx5_ifc_query_srq_in_bits { 4824 u8 opcode[0x10]; 4825 u8 reserved_at_10[0x10]; 4826 4827 u8 reserved_at_20[0x10]; 4828 u8 op_mod[0x10]; 4829 4830 u8 reserved_at_40[0x8]; 4831 u8 srqn[0x18]; 4832 4833 u8 reserved_at_60[0x20]; 4834 }; 4835 4836 struct mlx5_ifc_query_sq_out_bits { 4837 u8 status[0x8]; 4838 u8 reserved_at_8[0x18]; 4839 4840 u8 syndrome[0x20]; 4841 4842 u8 reserved_at_40[0xc0]; 4843 4844 struct mlx5_ifc_sqc_bits sq_context; 4845 }; 4846 4847 struct mlx5_ifc_query_sq_in_bits { 4848 u8 opcode[0x10]; 4849 u8 reserved_at_10[0x10]; 4850 4851 u8 reserved_at_20[0x10]; 4852 u8 op_mod[0x10]; 4853 4854 u8 reserved_at_40[0x8]; 4855 u8 sqn[0x18]; 4856 4857 u8 reserved_at_60[0x20]; 4858 }; 4859 4860 struct mlx5_ifc_query_special_contexts_out_bits { 4861 u8 status[0x8]; 4862 u8 reserved_at_8[0x18]; 4863 4864 u8 syndrome[0x20]; 4865 4866 u8 dump_fill_mkey[0x20]; 4867 4868 u8 resd_lkey[0x20]; 4869 4870 u8 null_mkey[0x20]; 4871 4872 u8 reserved_at_a0[0x60]; 4873 }; 4874 4875 struct mlx5_ifc_query_special_contexts_in_bits { 4876 u8 opcode[0x10]; 4877 u8 reserved_at_10[0x10]; 4878 4879 u8 reserved_at_20[0x10]; 4880 u8 op_mod[0x10]; 4881 4882 u8 reserved_at_40[0x40]; 4883 }; 4884 4885 struct mlx5_ifc_query_scheduling_element_out_bits { 4886 u8 opcode[0x10]; 4887 u8 reserved_at_10[0x10]; 4888 4889 u8 reserved_at_20[0x10]; 4890 u8 op_mod[0x10]; 4891 4892 u8 reserved_at_40[0xc0]; 4893 4894 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4895 4896 u8 reserved_at_300[0x100]; 4897 }; 4898 4899 enum { 4900 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4901 SCHEDULING_HIERARCHY_NIC = 0x3, 4902 }; 4903 4904 struct mlx5_ifc_query_scheduling_element_in_bits { 4905 u8 opcode[0x10]; 4906 u8 reserved_at_10[0x10]; 4907 4908 u8 reserved_at_20[0x10]; 4909 u8 op_mod[0x10]; 4910 4911 u8 scheduling_hierarchy[0x8]; 4912 u8 reserved_at_48[0x18]; 4913 4914 u8 scheduling_element_id[0x20]; 4915 4916 u8 reserved_at_80[0x180]; 4917 }; 4918 4919 struct mlx5_ifc_query_rqt_out_bits { 4920 u8 status[0x8]; 4921 u8 reserved_at_8[0x18]; 4922 4923 u8 syndrome[0x20]; 4924 4925 u8 reserved_at_40[0xc0]; 4926 4927 struct mlx5_ifc_rqtc_bits rqt_context; 4928 }; 4929 4930 struct mlx5_ifc_query_rqt_in_bits { 4931 u8 opcode[0x10]; 4932 u8 reserved_at_10[0x10]; 4933 4934 u8 reserved_at_20[0x10]; 4935 u8 op_mod[0x10]; 4936 4937 u8 reserved_at_40[0x8]; 4938 u8 rqtn[0x18]; 4939 4940 u8 reserved_at_60[0x20]; 4941 }; 4942 4943 struct mlx5_ifc_query_rq_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_at_8[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_at_40[0xc0]; 4950 4951 struct mlx5_ifc_rqc_bits rq_context; 4952 }; 4953 4954 struct mlx5_ifc_query_rq_in_bits { 4955 u8 opcode[0x10]; 4956 u8 reserved_at_10[0x10]; 4957 4958 u8 reserved_at_20[0x10]; 4959 u8 op_mod[0x10]; 4960 4961 u8 reserved_at_40[0x8]; 4962 u8 rqn[0x18]; 4963 4964 u8 reserved_at_60[0x20]; 4965 }; 4966 4967 struct mlx5_ifc_query_roce_address_out_bits { 4968 u8 status[0x8]; 4969 u8 reserved_at_8[0x18]; 4970 4971 u8 syndrome[0x20]; 4972 4973 u8 reserved_at_40[0x40]; 4974 4975 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4976 }; 4977 4978 struct mlx5_ifc_query_roce_address_in_bits { 4979 u8 opcode[0x10]; 4980 u8 reserved_at_10[0x10]; 4981 4982 u8 reserved_at_20[0x10]; 4983 u8 op_mod[0x10]; 4984 4985 u8 roce_address_index[0x10]; 4986 u8 reserved_at_50[0xc]; 4987 u8 vhca_port_num[0x4]; 4988 4989 u8 reserved_at_60[0x20]; 4990 }; 4991 4992 struct mlx5_ifc_query_rmp_out_bits { 4993 u8 status[0x8]; 4994 u8 reserved_at_8[0x18]; 4995 4996 u8 syndrome[0x20]; 4997 4998 u8 reserved_at_40[0xc0]; 4999 5000 struct mlx5_ifc_rmpc_bits rmp_context; 5001 }; 5002 5003 struct mlx5_ifc_query_rmp_in_bits { 5004 u8 opcode[0x10]; 5005 u8 reserved_at_10[0x10]; 5006 5007 u8 reserved_at_20[0x10]; 5008 u8 op_mod[0x10]; 5009 5010 u8 reserved_at_40[0x8]; 5011 u8 rmpn[0x18]; 5012 5013 u8 reserved_at_60[0x20]; 5014 }; 5015 5016 struct mlx5_ifc_query_qp_out_bits { 5017 u8 status[0x8]; 5018 u8 reserved_at_8[0x18]; 5019 5020 u8 syndrome[0x20]; 5021 5022 u8 reserved_at_40[0x20]; 5023 u8 ece[0x20]; 5024 5025 u8 opt_param_mask[0x20]; 5026 5027 u8 reserved_at_a0[0x20]; 5028 5029 struct mlx5_ifc_qpc_bits qpc; 5030 5031 u8 reserved_at_800[0x80]; 5032 5033 u8 pas[][0x40]; 5034 }; 5035 5036 struct mlx5_ifc_query_qp_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_at_10[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 reserved_at_40[0x8]; 5044 u8 qpn[0x18]; 5045 5046 u8 reserved_at_60[0x20]; 5047 }; 5048 5049 struct mlx5_ifc_query_q_counter_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_at_8[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 reserved_at_40[0x40]; 5056 5057 u8 rx_write_requests[0x20]; 5058 5059 u8 reserved_at_a0[0x20]; 5060 5061 u8 rx_read_requests[0x20]; 5062 5063 u8 reserved_at_e0[0x20]; 5064 5065 u8 rx_atomic_requests[0x20]; 5066 5067 u8 reserved_at_120[0x20]; 5068 5069 u8 rx_dct_connect[0x20]; 5070 5071 u8 reserved_at_160[0x20]; 5072 5073 u8 out_of_buffer[0x20]; 5074 5075 u8 reserved_at_1a0[0x20]; 5076 5077 u8 out_of_sequence[0x20]; 5078 5079 u8 reserved_at_1e0[0x20]; 5080 5081 u8 duplicate_request[0x20]; 5082 5083 u8 reserved_at_220[0x20]; 5084 5085 u8 rnr_nak_retry_err[0x20]; 5086 5087 u8 reserved_at_260[0x20]; 5088 5089 u8 packet_seq_err[0x20]; 5090 5091 u8 reserved_at_2a0[0x20]; 5092 5093 u8 implied_nak_seq_err[0x20]; 5094 5095 u8 reserved_at_2e0[0x20]; 5096 5097 u8 local_ack_timeout_err[0x20]; 5098 5099 u8 reserved_at_320[0xa0]; 5100 5101 u8 resp_local_length_error[0x20]; 5102 5103 u8 req_local_length_error[0x20]; 5104 5105 u8 resp_local_qp_error[0x20]; 5106 5107 u8 local_operation_error[0x20]; 5108 5109 u8 resp_local_protection[0x20]; 5110 5111 u8 req_local_protection[0x20]; 5112 5113 u8 resp_cqe_error[0x20]; 5114 5115 u8 req_cqe_error[0x20]; 5116 5117 u8 req_mw_binding[0x20]; 5118 5119 u8 req_bad_response[0x20]; 5120 5121 u8 req_remote_invalid_request[0x20]; 5122 5123 u8 resp_remote_invalid_request[0x20]; 5124 5125 u8 req_remote_access_errors[0x20]; 5126 5127 u8 resp_remote_access_errors[0x20]; 5128 5129 u8 req_remote_operation_errors[0x20]; 5130 5131 u8 req_transport_retries_exceeded[0x20]; 5132 5133 u8 cq_overflow[0x20]; 5134 5135 u8 resp_cqe_flush_error[0x20]; 5136 5137 u8 req_cqe_flush_error[0x20]; 5138 5139 u8 reserved_at_620[0x20]; 5140 5141 u8 roce_adp_retrans[0x20]; 5142 5143 u8 roce_adp_retrans_to[0x20]; 5144 5145 u8 roce_slow_restart[0x20]; 5146 5147 u8 roce_slow_restart_cnps[0x20]; 5148 5149 u8 roce_slow_restart_trans[0x20]; 5150 5151 u8 reserved_at_6e0[0x120]; 5152 }; 5153 5154 struct mlx5_ifc_query_q_counter_in_bits { 5155 u8 opcode[0x10]; 5156 u8 reserved_at_10[0x10]; 5157 5158 u8 reserved_at_20[0x10]; 5159 u8 op_mod[0x10]; 5160 5161 u8 reserved_at_40[0x80]; 5162 5163 u8 clear[0x1]; 5164 u8 reserved_at_c1[0x1f]; 5165 5166 u8 reserved_at_e0[0x18]; 5167 u8 counter_set_id[0x8]; 5168 }; 5169 5170 struct mlx5_ifc_query_pages_out_bits { 5171 u8 status[0x8]; 5172 u8 reserved_at_8[0x18]; 5173 5174 u8 syndrome[0x20]; 5175 5176 u8 embedded_cpu_function[0x1]; 5177 u8 reserved_at_41[0xf]; 5178 u8 function_id[0x10]; 5179 5180 u8 num_pages[0x20]; 5181 }; 5182 5183 enum { 5184 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5185 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5186 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5187 }; 5188 5189 struct mlx5_ifc_query_pages_in_bits { 5190 u8 opcode[0x10]; 5191 u8 reserved_at_10[0x10]; 5192 5193 u8 reserved_at_20[0x10]; 5194 u8 op_mod[0x10]; 5195 5196 u8 embedded_cpu_function[0x1]; 5197 u8 reserved_at_41[0xf]; 5198 u8 function_id[0x10]; 5199 5200 u8 reserved_at_60[0x20]; 5201 }; 5202 5203 struct mlx5_ifc_query_nic_vport_context_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_at_8[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_at_40[0x40]; 5210 5211 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5212 }; 5213 5214 struct mlx5_ifc_query_nic_vport_context_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_at_10[0x10]; 5217 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 other_vport[0x1]; 5222 u8 reserved_at_41[0xf]; 5223 u8 vport_number[0x10]; 5224 5225 u8 reserved_at_60[0x5]; 5226 u8 allowed_list_type[0x3]; 5227 u8 reserved_at_68[0x18]; 5228 }; 5229 5230 struct mlx5_ifc_query_mkey_out_bits { 5231 u8 status[0x8]; 5232 u8 reserved_at_8[0x18]; 5233 5234 u8 syndrome[0x20]; 5235 5236 u8 reserved_at_40[0x40]; 5237 5238 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5239 5240 u8 reserved_at_280[0x600]; 5241 5242 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5243 5244 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5245 }; 5246 5247 struct mlx5_ifc_query_mkey_in_bits { 5248 u8 opcode[0x10]; 5249 u8 reserved_at_10[0x10]; 5250 5251 u8 reserved_at_20[0x10]; 5252 u8 op_mod[0x10]; 5253 5254 u8 reserved_at_40[0x8]; 5255 u8 mkey_index[0x18]; 5256 5257 u8 pg_access[0x1]; 5258 u8 reserved_at_61[0x1f]; 5259 }; 5260 5261 struct mlx5_ifc_query_mad_demux_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 5269 u8 mad_dumux_parameters_block[0x20]; 5270 }; 5271 5272 struct mlx5_ifc_query_mad_demux_in_bits { 5273 u8 opcode[0x10]; 5274 u8 reserved_at_10[0x10]; 5275 5276 u8 reserved_at_20[0x10]; 5277 u8 op_mod[0x10]; 5278 5279 u8 reserved_at_40[0x40]; 5280 }; 5281 5282 struct mlx5_ifc_query_l2_table_entry_out_bits { 5283 u8 status[0x8]; 5284 u8 reserved_at_8[0x18]; 5285 5286 u8 syndrome[0x20]; 5287 5288 u8 reserved_at_40[0xa0]; 5289 5290 u8 reserved_at_e0[0x13]; 5291 u8 vlan_valid[0x1]; 5292 u8 vlan[0xc]; 5293 5294 struct mlx5_ifc_mac_address_layout_bits mac_address; 5295 5296 u8 reserved_at_140[0xc0]; 5297 }; 5298 5299 struct mlx5_ifc_query_l2_table_entry_in_bits { 5300 u8 opcode[0x10]; 5301 u8 reserved_at_10[0x10]; 5302 5303 u8 reserved_at_20[0x10]; 5304 u8 op_mod[0x10]; 5305 5306 u8 reserved_at_40[0x60]; 5307 5308 u8 reserved_at_a0[0x8]; 5309 u8 table_index[0x18]; 5310 5311 u8 reserved_at_c0[0x140]; 5312 }; 5313 5314 struct mlx5_ifc_query_issi_out_bits { 5315 u8 status[0x8]; 5316 u8 reserved_at_8[0x18]; 5317 5318 u8 syndrome[0x20]; 5319 5320 u8 reserved_at_40[0x10]; 5321 u8 current_issi[0x10]; 5322 5323 u8 reserved_at_60[0xa0]; 5324 5325 u8 reserved_at_100[76][0x8]; 5326 u8 supported_issi_dw0[0x20]; 5327 }; 5328 5329 struct mlx5_ifc_query_issi_in_bits { 5330 u8 opcode[0x10]; 5331 u8 reserved_at_10[0x10]; 5332 5333 u8 reserved_at_20[0x10]; 5334 u8 op_mod[0x10]; 5335 5336 u8 reserved_at_40[0x40]; 5337 }; 5338 5339 struct mlx5_ifc_set_driver_version_out_bits { 5340 u8 status[0x8]; 5341 u8 reserved_0[0x18]; 5342 5343 u8 syndrome[0x20]; 5344 u8 reserved_1[0x40]; 5345 }; 5346 5347 struct mlx5_ifc_set_driver_version_in_bits { 5348 u8 opcode[0x10]; 5349 u8 reserved_0[0x10]; 5350 5351 u8 reserved_1[0x10]; 5352 u8 op_mod[0x10]; 5353 5354 u8 reserved_2[0x40]; 5355 u8 driver_version[64][0x8]; 5356 }; 5357 5358 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_at_8[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 reserved_at_40[0x40]; 5365 5366 struct mlx5_ifc_pkey_bits pkey[]; 5367 }; 5368 5369 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5370 u8 opcode[0x10]; 5371 u8 reserved_at_10[0x10]; 5372 5373 u8 reserved_at_20[0x10]; 5374 u8 op_mod[0x10]; 5375 5376 u8 other_vport[0x1]; 5377 u8 reserved_at_41[0xb]; 5378 u8 port_num[0x4]; 5379 u8 vport_number[0x10]; 5380 5381 u8 reserved_at_60[0x10]; 5382 u8 pkey_index[0x10]; 5383 }; 5384 5385 enum { 5386 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5387 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5388 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5389 }; 5390 5391 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5392 u8 status[0x8]; 5393 u8 reserved_at_8[0x18]; 5394 5395 u8 syndrome[0x20]; 5396 5397 u8 reserved_at_40[0x20]; 5398 5399 u8 gids_num[0x10]; 5400 u8 reserved_at_70[0x10]; 5401 5402 struct mlx5_ifc_array128_auto_bits gid[]; 5403 }; 5404 5405 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5406 u8 opcode[0x10]; 5407 u8 reserved_at_10[0x10]; 5408 5409 u8 reserved_at_20[0x10]; 5410 u8 op_mod[0x10]; 5411 5412 u8 other_vport[0x1]; 5413 u8 reserved_at_41[0xb]; 5414 u8 port_num[0x4]; 5415 u8 vport_number[0x10]; 5416 5417 u8 reserved_at_60[0x10]; 5418 u8 gid_index[0x10]; 5419 }; 5420 5421 struct mlx5_ifc_query_hca_vport_context_out_bits { 5422 u8 status[0x8]; 5423 u8 reserved_at_8[0x18]; 5424 5425 u8 syndrome[0x20]; 5426 5427 u8 reserved_at_40[0x40]; 5428 5429 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5430 }; 5431 5432 struct mlx5_ifc_query_hca_vport_context_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_at_10[0x10]; 5435 5436 u8 reserved_at_20[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 other_vport[0x1]; 5440 u8 reserved_at_41[0xb]; 5441 u8 port_num[0x4]; 5442 u8 vport_number[0x10]; 5443 5444 u8 reserved_at_60[0x20]; 5445 }; 5446 5447 struct mlx5_ifc_query_hca_cap_out_bits { 5448 u8 status[0x8]; 5449 u8 reserved_at_8[0x18]; 5450 5451 u8 syndrome[0x20]; 5452 5453 u8 reserved_at_40[0x40]; 5454 5455 union mlx5_ifc_hca_cap_union_bits capability; 5456 }; 5457 5458 struct mlx5_ifc_query_hca_cap_in_bits { 5459 u8 opcode[0x10]; 5460 u8 reserved_at_10[0x10]; 5461 5462 u8 reserved_at_20[0x10]; 5463 u8 op_mod[0x10]; 5464 5465 u8 other_function[0x1]; 5466 u8 reserved_at_41[0xf]; 5467 u8 function_id[0x10]; 5468 5469 u8 reserved_at_60[0x20]; 5470 }; 5471 5472 struct mlx5_ifc_other_hca_cap_bits { 5473 u8 roce[0x1]; 5474 u8 reserved_at_1[0x27f]; 5475 }; 5476 5477 struct mlx5_ifc_query_other_hca_cap_out_bits { 5478 u8 status[0x8]; 5479 u8 reserved_at_8[0x18]; 5480 5481 u8 syndrome[0x20]; 5482 5483 u8 reserved_at_40[0x40]; 5484 5485 struct mlx5_ifc_other_hca_cap_bits other_capability; 5486 }; 5487 5488 struct mlx5_ifc_query_other_hca_cap_in_bits { 5489 u8 opcode[0x10]; 5490 u8 reserved_at_10[0x10]; 5491 5492 u8 reserved_at_20[0x10]; 5493 u8 op_mod[0x10]; 5494 5495 u8 reserved_at_40[0x10]; 5496 u8 function_id[0x10]; 5497 5498 u8 reserved_at_60[0x20]; 5499 }; 5500 5501 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5502 u8 status[0x8]; 5503 u8 reserved_at_8[0x18]; 5504 5505 u8 syndrome[0x20]; 5506 5507 u8 reserved_at_40[0x40]; 5508 }; 5509 5510 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5511 u8 opcode[0x10]; 5512 u8 reserved_at_10[0x10]; 5513 5514 u8 reserved_at_20[0x10]; 5515 u8 op_mod[0x10]; 5516 5517 u8 reserved_at_40[0x10]; 5518 u8 function_id[0x10]; 5519 u8 field_select[0x20]; 5520 5521 struct mlx5_ifc_other_hca_cap_bits other_capability; 5522 }; 5523 5524 struct mlx5_ifc_flow_table_context_bits { 5525 u8 reformat_en[0x1]; 5526 u8 decap_en[0x1]; 5527 u8 sw_owner[0x1]; 5528 u8 termination_table[0x1]; 5529 u8 table_miss_action[0x4]; 5530 u8 level[0x8]; 5531 u8 reserved_at_10[0x8]; 5532 u8 log_size[0x8]; 5533 5534 u8 reserved_at_20[0x8]; 5535 u8 table_miss_id[0x18]; 5536 5537 u8 reserved_at_40[0x8]; 5538 u8 lag_master_next_table_id[0x18]; 5539 5540 u8 reserved_at_60[0x60]; 5541 5542 u8 sw_owner_icm_root_1[0x40]; 5543 5544 u8 sw_owner_icm_root_0[0x40]; 5545 5546 }; 5547 5548 struct mlx5_ifc_query_flow_table_out_bits { 5549 u8 status[0x8]; 5550 u8 reserved_at_8[0x18]; 5551 5552 u8 syndrome[0x20]; 5553 5554 u8 reserved_at_40[0x80]; 5555 5556 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5557 }; 5558 5559 struct mlx5_ifc_query_flow_table_in_bits { 5560 u8 opcode[0x10]; 5561 u8 reserved_at_10[0x10]; 5562 5563 u8 reserved_at_20[0x10]; 5564 u8 op_mod[0x10]; 5565 5566 u8 reserved_at_40[0x40]; 5567 5568 u8 table_type[0x8]; 5569 u8 reserved_at_88[0x18]; 5570 5571 u8 reserved_at_a0[0x8]; 5572 u8 table_id[0x18]; 5573 5574 u8 reserved_at_c0[0x140]; 5575 }; 5576 5577 struct mlx5_ifc_query_fte_out_bits { 5578 u8 status[0x8]; 5579 u8 reserved_at_8[0x18]; 5580 5581 u8 syndrome[0x20]; 5582 5583 u8 reserved_at_40[0x1c0]; 5584 5585 struct mlx5_ifc_flow_context_bits flow_context; 5586 }; 5587 5588 struct mlx5_ifc_query_fte_in_bits { 5589 u8 opcode[0x10]; 5590 u8 reserved_at_10[0x10]; 5591 5592 u8 reserved_at_20[0x10]; 5593 u8 op_mod[0x10]; 5594 5595 u8 reserved_at_40[0x40]; 5596 5597 u8 table_type[0x8]; 5598 u8 reserved_at_88[0x18]; 5599 5600 u8 reserved_at_a0[0x8]; 5601 u8 table_id[0x18]; 5602 5603 u8 reserved_at_c0[0x40]; 5604 5605 u8 flow_index[0x20]; 5606 5607 u8 reserved_at_120[0xe0]; 5608 }; 5609 5610 enum { 5611 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5612 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5613 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5614 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5615 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5616 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5617 }; 5618 5619 struct mlx5_ifc_query_flow_group_out_bits { 5620 u8 status[0x8]; 5621 u8 reserved_at_8[0x18]; 5622 5623 u8 syndrome[0x20]; 5624 5625 u8 reserved_at_40[0xa0]; 5626 5627 u8 start_flow_index[0x20]; 5628 5629 u8 reserved_at_100[0x20]; 5630 5631 u8 end_flow_index[0x20]; 5632 5633 u8 reserved_at_140[0xa0]; 5634 5635 u8 reserved_at_1e0[0x18]; 5636 u8 match_criteria_enable[0x8]; 5637 5638 struct mlx5_ifc_fte_match_param_bits match_criteria; 5639 5640 u8 reserved_at_1200[0xe00]; 5641 }; 5642 5643 struct mlx5_ifc_query_flow_group_in_bits { 5644 u8 opcode[0x10]; 5645 u8 reserved_at_10[0x10]; 5646 5647 u8 reserved_at_20[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 reserved_at_40[0x40]; 5651 5652 u8 table_type[0x8]; 5653 u8 reserved_at_88[0x18]; 5654 5655 u8 reserved_at_a0[0x8]; 5656 u8 table_id[0x18]; 5657 5658 u8 group_id[0x20]; 5659 5660 u8 reserved_at_e0[0x120]; 5661 }; 5662 5663 struct mlx5_ifc_query_flow_counter_out_bits { 5664 u8 status[0x8]; 5665 u8 reserved_at_8[0x18]; 5666 5667 u8 syndrome[0x20]; 5668 5669 u8 reserved_at_40[0x40]; 5670 5671 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5672 }; 5673 5674 struct mlx5_ifc_query_flow_counter_in_bits { 5675 u8 opcode[0x10]; 5676 u8 reserved_at_10[0x10]; 5677 5678 u8 reserved_at_20[0x10]; 5679 u8 op_mod[0x10]; 5680 5681 u8 reserved_at_40[0x80]; 5682 5683 u8 clear[0x1]; 5684 u8 reserved_at_c1[0xf]; 5685 u8 num_of_counters[0x10]; 5686 5687 u8 flow_counter_id[0x20]; 5688 }; 5689 5690 struct mlx5_ifc_query_esw_vport_context_out_bits { 5691 u8 status[0x8]; 5692 u8 reserved_at_8[0x18]; 5693 5694 u8 syndrome[0x20]; 5695 5696 u8 reserved_at_40[0x40]; 5697 5698 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5699 }; 5700 5701 struct mlx5_ifc_query_esw_vport_context_in_bits { 5702 u8 opcode[0x10]; 5703 u8 reserved_at_10[0x10]; 5704 5705 u8 reserved_at_20[0x10]; 5706 u8 op_mod[0x10]; 5707 5708 u8 other_vport[0x1]; 5709 u8 reserved_at_41[0xf]; 5710 u8 vport_number[0x10]; 5711 5712 u8 reserved_at_60[0x20]; 5713 }; 5714 5715 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5716 u8 status[0x8]; 5717 u8 reserved_at_8[0x18]; 5718 5719 u8 syndrome[0x20]; 5720 5721 u8 reserved_at_40[0x40]; 5722 }; 5723 5724 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5725 u8 reserved_at_0[0x1b]; 5726 u8 fdb_to_vport_reg_c_id[0x1]; 5727 u8 vport_cvlan_insert[0x1]; 5728 u8 vport_svlan_insert[0x1]; 5729 u8 vport_cvlan_strip[0x1]; 5730 u8 vport_svlan_strip[0x1]; 5731 }; 5732 5733 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5734 u8 opcode[0x10]; 5735 u8 reserved_at_10[0x10]; 5736 5737 u8 reserved_at_20[0x10]; 5738 u8 op_mod[0x10]; 5739 5740 u8 other_vport[0x1]; 5741 u8 reserved_at_41[0xf]; 5742 u8 vport_number[0x10]; 5743 5744 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5745 5746 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5747 }; 5748 5749 struct mlx5_ifc_query_eq_out_bits { 5750 u8 status[0x8]; 5751 u8 reserved_at_8[0x18]; 5752 5753 u8 syndrome[0x20]; 5754 5755 u8 reserved_at_40[0x40]; 5756 5757 struct mlx5_ifc_eqc_bits eq_context_entry; 5758 5759 u8 reserved_at_280[0x40]; 5760 5761 u8 event_bitmask[0x40]; 5762 5763 u8 reserved_at_300[0x580]; 5764 5765 u8 pas[][0x40]; 5766 }; 5767 5768 struct mlx5_ifc_query_eq_in_bits { 5769 u8 opcode[0x10]; 5770 u8 reserved_at_10[0x10]; 5771 5772 u8 reserved_at_20[0x10]; 5773 u8 op_mod[0x10]; 5774 5775 u8 reserved_at_40[0x18]; 5776 u8 eq_number[0x8]; 5777 5778 u8 reserved_at_60[0x20]; 5779 }; 5780 5781 struct mlx5_ifc_packet_reformat_context_in_bits { 5782 u8 reformat_type[0x8]; 5783 u8 reserved_at_8[0x4]; 5784 u8 reformat_param_0[0x4]; 5785 u8 reserved_at_10[0x6]; 5786 u8 reformat_data_size[0xa]; 5787 5788 u8 reformat_param_1[0x8]; 5789 u8 reserved_at_28[0x8]; 5790 u8 reformat_data[2][0x8]; 5791 5792 u8 more_reformat_data[][0x8]; 5793 }; 5794 5795 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5796 u8 status[0x8]; 5797 u8 reserved_at_8[0x18]; 5798 5799 u8 syndrome[0x20]; 5800 5801 u8 reserved_at_40[0xa0]; 5802 5803 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5804 }; 5805 5806 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5807 u8 opcode[0x10]; 5808 u8 reserved_at_10[0x10]; 5809 5810 u8 reserved_at_20[0x10]; 5811 u8 op_mod[0x10]; 5812 5813 u8 packet_reformat_id[0x20]; 5814 5815 u8 reserved_at_60[0xa0]; 5816 }; 5817 5818 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5819 u8 status[0x8]; 5820 u8 reserved_at_8[0x18]; 5821 5822 u8 syndrome[0x20]; 5823 5824 u8 packet_reformat_id[0x20]; 5825 5826 u8 reserved_at_60[0x20]; 5827 }; 5828 5829 enum { 5830 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 5831 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 5832 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 5833 }; 5834 5835 enum mlx5_reformat_ctx_type { 5836 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5837 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5838 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5839 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5840 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5841 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 5842 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 5843 }; 5844 5845 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5846 u8 opcode[0x10]; 5847 u8 reserved_at_10[0x10]; 5848 5849 u8 reserved_at_20[0x10]; 5850 u8 op_mod[0x10]; 5851 5852 u8 reserved_at_40[0xa0]; 5853 5854 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5855 }; 5856 5857 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5858 u8 status[0x8]; 5859 u8 reserved_at_8[0x18]; 5860 5861 u8 syndrome[0x20]; 5862 5863 u8 reserved_at_40[0x40]; 5864 }; 5865 5866 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5867 u8 opcode[0x10]; 5868 u8 reserved_at_10[0x10]; 5869 5870 u8 reserved_20[0x10]; 5871 u8 op_mod[0x10]; 5872 5873 u8 packet_reformat_id[0x20]; 5874 5875 u8 reserved_60[0x20]; 5876 }; 5877 5878 struct mlx5_ifc_set_action_in_bits { 5879 u8 action_type[0x4]; 5880 u8 field[0xc]; 5881 u8 reserved_at_10[0x3]; 5882 u8 offset[0x5]; 5883 u8 reserved_at_18[0x3]; 5884 u8 length[0x5]; 5885 5886 u8 data[0x20]; 5887 }; 5888 5889 struct mlx5_ifc_add_action_in_bits { 5890 u8 action_type[0x4]; 5891 u8 field[0xc]; 5892 u8 reserved_at_10[0x10]; 5893 5894 u8 data[0x20]; 5895 }; 5896 5897 struct mlx5_ifc_copy_action_in_bits { 5898 u8 action_type[0x4]; 5899 u8 src_field[0xc]; 5900 u8 reserved_at_10[0x3]; 5901 u8 src_offset[0x5]; 5902 u8 reserved_at_18[0x3]; 5903 u8 length[0x5]; 5904 5905 u8 reserved_at_20[0x4]; 5906 u8 dst_field[0xc]; 5907 u8 reserved_at_30[0x3]; 5908 u8 dst_offset[0x5]; 5909 u8 reserved_at_38[0x8]; 5910 }; 5911 5912 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5913 struct mlx5_ifc_set_action_in_bits set_action_in; 5914 struct mlx5_ifc_add_action_in_bits add_action_in; 5915 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5916 u8 reserved_at_0[0x40]; 5917 }; 5918 5919 enum { 5920 MLX5_ACTION_TYPE_SET = 0x1, 5921 MLX5_ACTION_TYPE_ADD = 0x2, 5922 MLX5_ACTION_TYPE_COPY = 0x3, 5923 }; 5924 5925 enum { 5926 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5927 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5928 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5929 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5930 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5931 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5932 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5933 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5934 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5935 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5936 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5937 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5938 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5939 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5940 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5941 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5942 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5943 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5944 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5945 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5946 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5947 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5948 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5949 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5950 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5951 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5952 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5953 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5954 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5955 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5956 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5957 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5958 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5959 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5960 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5961 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5962 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5963 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 5964 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 5965 }; 5966 5967 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5968 u8 status[0x8]; 5969 u8 reserved_at_8[0x18]; 5970 5971 u8 syndrome[0x20]; 5972 5973 u8 modify_header_id[0x20]; 5974 5975 u8 reserved_at_60[0x20]; 5976 }; 5977 5978 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5979 u8 opcode[0x10]; 5980 u8 reserved_at_10[0x10]; 5981 5982 u8 reserved_at_20[0x10]; 5983 u8 op_mod[0x10]; 5984 5985 u8 reserved_at_40[0x20]; 5986 5987 u8 table_type[0x8]; 5988 u8 reserved_at_68[0x10]; 5989 u8 num_of_actions[0x8]; 5990 5991 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5992 }; 5993 5994 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_at_8[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_at_40[0x40]; 6001 }; 6002 6003 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 modify_header_id[0x20]; 6011 6012 u8 reserved_at_60[0x20]; 6013 }; 6014 6015 struct mlx5_ifc_query_modify_header_context_in_bits { 6016 u8 opcode[0x10]; 6017 u8 uid[0x10]; 6018 6019 u8 reserved_at_20[0x10]; 6020 u8 op_mod[0x10]; 6021 6022 u8 modify_header_id[0x20]; 6023 6024 u8 reserved_at_60[0xa0]; 6025 }; 6026 6027 struct mlx5_ifc_query_dct_out_bits { 6028 u8 status[0x8]; 6029 u8 reserved_at_8[0x18]; 6030 6031 u8 syndrome[0x20]; 6032 6033 u8 reserved_at_40[0x40]; 6034 6035 struct mlx5_ifc_dctc_bits dct_context_entry; 6036 6037 u8 reserved_at_280[0x180]; 6038 }; 6039 6040 struct mlx5_ifc_query_dct_in_bits { 6041 u8 opcode[0x10]; 6042 u8 reserved_at_10[0x10]; 6043 6044 u8 reserved_at_20[0x10]; 6045 u8 op_mod[0x10]; 6046 6047 u8 reserved_at_40[0x8]; 6048 u8 dctn[0x18]; 6049 6050 u8 reserved_at_60[0x20]; 6051 }; 6052 6053 struct mlx5_ifc_query_cq_out_bits { 6054 u8 status[0x8]; 6055 u8 reserved_at_8[0x18]; 6056 6057 u8 syndrome[0x20]; 6058 6059 u8 reserved_at_40[0x40]; 6060 6061 struct mlx5_ifc_cqc_bits cq_context; 6062 6063 u8 reserved_at_280[0x600]; 6064 6065 u8 pas[][0x40]; 6066 }; 6067 6068 struct mlx5_ifc_query_cq_in_bits { 6069 u8 opcode[0x10]; 6070 u8 reserved_at_10[0x10]; 6071 6072 u8 reserved_at_20[0x10]; 6073 u8 op_mod[0x10]; 6074 6075 u8 reserved_at_40[0x8]; 6076 u8 cqn[0x18]; 6077 6078 u8 reserved_at_60[0x20]; 6079 }; 6080 6081 struct mlx5_ifc_query_cong_status_out_bits { 6082 u8 status[0x8]; 6083 u8 reserved_at_8[0x18]; 6084 6085 u8 syndrome[0x20]; 6086 6087 u8 reserved_at_40[0x20]; 6088 6089 u8 enable[0x1]; 6090 u8 tag_enable[0x1]; 6091 u8 reserved_at_62[0x1e]; 6092 }; 6093 6094 struct mlx5_ifc_query_cong_status_in_bits { 6095 u8 opcode[0x10]; 6096 u8 reserved_at_10[0x10]; 6097 6098 u8 reserved_at_20[0x10]; 6099 u8 op_mod[0x10]; 6100 6101 u8 reserved_at_40[0x18]; 6102 u8 priority[0x4]; 6103 u8 cong_protocol[0x4]; 6104 6105 u8 reserved_at_60[0x20]; 6106 }; 6107 6108 struct mlx5_ifc_query_cong_statistics_out_bits { 6109 u8 status[0x8]; 6110 u8 reserved_at_8[0x18]; 6111 6112 u8 syndrome[0x20]; 6113 6114 u8 reserved_at_40[0x40]; 6115 6116 u8 rp_cur_flows[0x20]; 6117 6118 u8 sum_flows[0x20]; 6119 6120 u8 rp_cnp_ignored_high[0x20]; 6121 6122 u8 rp_cnp_ignored_low[0x20]; 6123 6124 u8 rp_cnp_handled_high[0x20]; 6125 6126 u8 rp_cnp_handled_low[0x20]; 6127 6128 u8 reserved_at_140[0x100]; 6129 6130 u8 time_stamp_high[0x20]; 6131 6132 u8 time_stamp_low[0x20]; 6133 6134 u8 accumulators_period[0x20]; 6135 6136 u8 np_ecn_marked_roce_packets_high[0x20]; 6137 6138 u8 np_ecn_marked_roce_packets_low[0x20]; 6139 6140 u8 np_cnp_sent_high[0x20]; 6141 6142 u8 np_cnp_sent_low[0x20]; 6143 6144 u8 reserved_at_320[0x560]; 6145 }; 6146 6147 struct mlx5_ifc_query_cong_statistics_in_bits { 6148 u8 opcode[0x10]; 6149 u8 reserved_at_10[0x10]; 6150 6151 u8 reserved_at_20[0x10]; 6152 u8 op_mod[0x10]; 6153 6154 u8 clear[0x1]; 6155 u8 reserved_at_41[0x1f]; 6156 6157 u8 reserved_at_60[0x20]; 6158 }; 6159 6160 struct mlx5_ifc_query_cong_params_out_bits { 6161 u8 status[0x8]; 6162 u8 reserved_at_8[0x18]; 6163 6164 u8 syndrome[0x20]; 6165 6166 u8 reserved_at_40[0x40]; 6167 6168 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6169 }; 6170 6171 struct mlx5_ifc_query_cong_params_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 reserved_at_40[0x1c]; 6179 u8 cong_protocol[0x4]; 6180 6181 u8 reserved_at_60[0x20]; 6182 }; 6183 6184 struct mlx5_ifc_query_adapter_out_bits { 6185 u8 status[0x8]; 6186 u8 reserved_at_8[0x18]; 6187 6188 u8 syndrome[0x20]; 6189 6190 u8 reserved_at_40[0x40]; 6191 6192 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6193 }; 6194 6195 struct mlx5_ifc_query_adapter_in_bits { 6196 u8 opcode[0x10]; 6197 u8 reserved_at_10[0x10]; 6198 6199 u8 reserved_at_20[0x10]; 6200 u8 op_mod[0x10]; 6201 6202 u8 reserved_at_40[0x40]; 6203 }; 6204 6205 struct mlx5_ifc_qp_2rst_out_bits { 6206 u8 status[0x8]; 6207 u8 reserved_at_8[0x18]; 6208 6209 u8 syndrome[0x20]; 6210 6211 u8 reserved_at_40[0x40]; 6212 }; 6213 6214 struct mlx5_ifc_qp_2rst_in_bits { 6215 u8 opcode[0x10]; 6216 u8 uid[0x10]; 6217 6218 u8 reserved_at_20[0x10]; 6219 u8 op_mod[0x10]; 6220 6221 u8 reserved_at_40[0x8]; 6222 u8 qpn[0x18]; 6223 6224 u8 reserved_at_60[0x20]; 6225 }; 6226 6227 struct mlx5_ifc_qp_2err_out_bits { 6228 u8 status[0x8]; 6229 u8 reserved_at_8[0x18]; 6230 6231 u8 syndrome[0x20]; 6232 6233 u8 reserved_at_40[0x40]; 6234 }; 6235 6236 struct mlx5_ifc_qp_2err_in_bits { 6237 u8 opcode[0x10]; 6238 u8 uid[0x10]; 6239 6240 u8 reserved_at_20[0x10]; 6241 u8 op_mod[0x10]; 6242 6243 u8 reserved_at_40[0x8]; 6244 u8 qpn[0x18]; 6245 6246 u8 reserved_at_60[0x20]; 6247 }; 6248 6249 struct mlx5_ifc_page_fault_resume_out_bits { 6250 u8 status[0x8]; 6251 u8 reserved_at_8[0x18]; 6252 6253 u8 syndrome[0x20]; 6254 6255 u8 reserved_at_40[0x40]; 6256 }; 6257 6258 struct mlx5_ifc_page_fault_resume_in_bits { 6259 u8 opcode[0x10]; 6260 u8 reserved_at_10[0x10]; 6261 6262 u8 reserved_at_20[0x10]; 6263 u8 op_mod[0x10]; 6264 6265 u8 error[0x1]; 6266 u8 reserved_at_41[0x4]; 6267 u8 page_fault_type[0x3]; 6268 u8 wq_number[0x18]; 6269 6270 u8 reserved_at_60[0x8]; 6271 u8 token[0x18]; 6272 }; 6273 6274 struct mlx5_ifc_nop_out_bits { 6275 u8 status[0x8]; 6276 u8 reserved_at_8[0x18]; 6277 6278 u8 syndrome[0x20]; 6279 6280 u8 reserved_at_40[0x40]; 6281 }; 6282 6283 struct mlx5_ifc_nop_in_bits { 6284 u8 opcode[0x10]; 6285 u8 reserved_at_10[0x10]; 6286 6287 u8 reserved_at_20[0x10]; 6288 u8 op_mod[0x10]; 6289 6290 u8 reserved_at_40[0x40]; 6291 }; 6292 6293 struct mlx5_ifc_modify_vport_state_out_bits { 6294 u8 status[0x8]; 6295 u8 reserved_at_8[0x18]; 6296 6297 u8 syndrome[0x20]; 6298 6299 u8 reserved_at_40[0x40]; 6300 }; 6301 6302 struct mlx5_ifc_modify_vport_state_in_bits { 6303 u8 opcode[0x10]; 6304 u8 reserved_at_10[0x10]; 6305 6306 u8 reserved_at_20[0x10]; 6307 u8 op_mod[0x10]; 6308 6309 u8 other_vport[0x1]; 6310 u8 reserved_at_41[0xf]; 6311 u8 vport_number[0x10]; 6312 6313 u8 reserved_at_60[0x18]; 6314 u8 admin_state[0x4]; 6315 u8 reserved_at_7c[0x4]; 6316 }; 6317 6318 struct mlx5_ifc_modify_tis_out_bits { 6319 u8 status[0x8]; 6320 u8 reserved_at_8[0x18]; 6321 6322 u8 syndrome[0x20]; 6323 6324 u8 reserved_at_40[0x40]; 6325 }; 6326 6327 struct mlx5_ifc_modify_tis_bitmask_bits { 6328 u8 reserved_at_0[0x20]; 6329 6330 u8 reserved_at_20[0x1d]; 6331 u8 lag_tx_port_affinity[0x1]; 6332 u8 strict_lag_tx_port_affinity[0x1]; 6333 u8 prio[0x1]; 6334 }; 6335 6336 struct mlx5_ifc_modify_tis_in_bits { 6337 u8 opcode[0x10]; 6338 u8 uid[0x10]; 6339 6340 u8 reserved_at_20[0x10]; 6341 u8 op_mod[0x10]; 6342 6343 u8 reserved_at_40[0x8]; 6344 u8 tisn[0x18]; 6345 6346 u8 reserved_at_60[0x20]; 6347 6348 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6349 6350 u8 reserved_at_c0[0x40]; 6351 6352 struct mlx5_ifc_tisc_bits ctx; 6353 }; 6354 6355 struct mlx5_ifc_modify_tir_bitmask_bits { 6356 u8 reserved_at_0[0x20]; 6357 6358 u8 reserved_at_20[0x1b]; 6359 u8 self_lb_en[0x1]; 6360 u8 reserved_at_3c[0x1]; 6361 u8 hash[0x1]; 6362 u8 reserved_at_3e[0x1]; 6363 u8 lro[0x1]; 6364 }; 6365 6366 struct mlx5_ifc_modify_tir_out_bits { 6367 u8 status[0x8]; 6368 u8 reserved_at_8[0x18]; 6369 6370 u8 syndrome[0x20]; 6371 6372 u8 reserved_at_40[0x40]; 6373 }; 6374 6375 struct mlx5_ifc_modify_tir_in_bits { 6376 u8 opcode[0x10]; 6377 u8 uid[0x10]; 6378 6379 u8 reserved_at_20[0x10]; 6380 u8 op_mod[0x10]; 6381 6382 u8 reserved_at_40[0x8]; 6383 u8 tirn[0x18]; 6384 6385 u8 reserved_at_60[0x20]; 6386 6387 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6388 6389 u8 reserved_at_c0[0x40]; 6390 6391 struct mlx5_ifc_tirc_bits ctx; 6392 }; 6393 6394 struct mlx5_ifc_modify_sq_out_bits { 6395 u8 status[0x8]; 6396 u8 reserved_at_8[0x18]; 6397 6398 u8 syndrome[0x20]; 6399 6400 u8 reserved_at_40[0x40]; 6401 }; 6402 6403 struct mlx5_ifc_modify_sq_in_bits { 6404 u8 opcode[0x10]; 6405 u8 uid[0x10]; 6406 6407 u8 reserved_at_20[0x10]; 6408 u8 op_mod[0x10]; 6409 6410 u8 sq_state[0x4]; 6411 u8 reserved_at_44[0x4]; 6412 u8 sqn[0x18]; 6413 6414 u8 reserved_at_60[0x20]; 6415 6416 u8 modify_bitmask[0x40]; 6417 6418 u8 reserved_at_c0[0x40]; 6419 6420 struct mlx5_ifc_sqc_bits ctx; 6421 }; 6422 6423 struct mlx5_ifc_modify_scheduling_element_out_bits { 6424 u8 status[0x8]; 6425 u8 reserved_at_8[0x18]; 6426 6427 u8 syndrome[0x20]; 6428 6429 u8 reserved_at_40[0x1c0]; 6430 }; 6431 6432 enum { 6433 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6434 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6435 }; 6436 6437 struct mlx5_ifc_modify_scheduling_element_in_bits { 6438 u8 opcode[0x10]; 6439 u8 reserved_at_10[0x10]; 6440 6441 u8 reserved_at_20[0x10]; 6442 u8 op_mod[0x10]; 6443 6444 u8 scheduling_hierarchy[0x8]; 6445 u8 reserved_at_48[0x18]; 6446 6447 u8 scheduling_element_id[0x20]; 6448 6449 u8 reserved_at_80[0x20]; 6450 6451 u8 modify_bitmask[0x20]; 6452 6453 u8 reserved_at_c0[0x40]; 6454 6455 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6456 6457 u8 reserved_at_300[0x100]; 6458 }; 6459 6460 struct mlx5_ifc_modify_rqt_out_bits { 6461 u8 status[0x8]; 6462 u8 reserved_at_8[0x18]; 6463 6464 u8 syndrome[0x20]; 6465 6466 u8 reserved_at_40[0x40]; 6467 }; 6468 6469 struct mlx5_ifc_rqt_bitmask_bits { 6470 u8 reserved_at_0[0x20]; 6471 6472 u8 reserved_at_20[0x1f]; 6473 u8 rqn_list[0x1]; 6474 }; 6475 6476 struct mlx5_ifc_modify_rqt_in_bits { 6477 u8 opcode[0x10]; 6478 u8 uid[0x10]; 6479 6480 u8 reserved_at_20[0x10]; 6481 u8 op_mod[0x10]; 6482 6483 u8 reserved_at_40[0x8]; 6484 u8 rqtn[0x18]; 6485 6486 u8 reserved_at_60[0x20]; 6487 6488 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6489 6490 u8 reserved_at_c0[0x40]; 6491 6492 struct mlx5_ifc_rqtc_bits ctx; 6493 }; 6494 6495 struct mlx5_ifc_modify_rq_out_bits { 6496 u8 status[0x8]; 6497 u8 reserved_at_8[0x18]; 6498 6499 u8 syndrome[0x20]; 6500 6501 u8 reserved_at_40[0x40]; 6502 }; 6503 6504 enum { 6505 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6506 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6507 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6508 }; 6509 6510 struct mlx5_ifc_modify_rq_in_bits { 6511 u8 opcode[0x10]; 6512 u8 uid[0x10]; 6513 6514 u8 reserved_at_20[0x10]; 6515 u8 op_mod[0x10]; 6516 6517 u8 rq_state[0x4]; 6518 u8 reserved_at_44[0x4]; 6519 u8 rqn[0x18]; 6520 6521 u8 reserved_at_60[0x20]; 6522 6523 u8 modify_bitmask[0x40]; 6524 6525 u8 reserved_at_c0[0x40]; 6526 6527 struct mlx5_ifc_rqc_bits ctx; 6528 }; 6529 6530 struct mlx5_ifc_modify_rmp_out_bits { 6531 u8 status[0x8]; 6532 u8 reserved_at_8[0x18]; 6533 6534 u8 syndrome[0x20]; 6535 6536 u8 reserved_at_40[0x40]; 6537 }; 6538 6539 struct mlx5_ifc_rmp_bitmask_bits { 6540 u8 reserved_at_0[0x20]; 6541 6542 u8 reserved_at_20[0x1f]; 6543 u8 lwm[0x1]; 6544 }; 6545 6546 struct mlx5_ifc_modify_rmp_in_bits { 6547 u8 opcode[0x10]; 6548 u8 uid[0x10]; 6549 6550 u8 reserved_at_20[0x10]; 6551 u8 op_mod[0x10]; 6552 6553 u8 rmp_state[0x4]; 6554 u8 reserved_at_44[0x4]; 6555 u8 rmpn[0x18]; 6556 6557 u8 reserved_at_60[0x20]; 6558 6559 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6560 6561 u8 reserved_at_c0[0x40]; 6562 6563 struct mlx5_ifc_rmpc_bits ctx; 6564 }; 6565 6566 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6567 u8 status[0x8]; 6568 u8 reserved_at_8[0x18]; 6569 6570 u8 syndrome[0x20]; 6571 6572 u8 reserved_at_40[0x40]; 6573 }; 6574 6575 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6576 u8 reserved_at_0[0x12]; 6577 u8 affiliation[0x1]; 6578 u8 reserved_at_13[0x1]; 6579 u8 disable_uc_local_lb[0x1]; 6580 u8 disable_mc_local_lb[0x1]; 6581 u8 node_guid[0x1]; 6582 u8 port_guid[0x1]; 6583 u8 min_inline[0x1]; 6584 u8 mtu[0x1]; 6585 u8 change_event[0x1]; 6586 u8 promisc[0x1]; 6587 u8 permanent_address[0x1]; 6588 u8 addresses_list[0x1]; 6589 u8 roce_en[0x1]; 6590 u8 reserved_at_1f[0x1]; 6591 }; 6592 6593 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6594 u8 opcode[0x10]; 6595 u8 reserved_at_10[0x10]; 6596 6597 u8 reserved_at_20[0x10]; 6598 u8 op_mod[0x10]; 6599 6600 u8 other_vport[0x1]; 6601 u8 reserved_at_41[0xf]; 6602 u8 vport_number[0x10]; 6603 6604 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6605 6606 u8 reserved_at_80[0x780]; 6607 6608 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6609 }; 6610 6611 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6612 u8 status[0x8]; 6613 u8 reserved_at_8[0x18]; 6614 6615 u8 syndrome[0x20]; 6616 6617 u8 reserved_at_40[0x40]; 6618 }; 6619 6620 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6621 u8 opcode[0x10]; 6622 u8 reserved_at_10[0x10]; 6623 6624 u8 reserved_at_20[0x10]; 6625 u8 op_mod[0x10]; 6626 6627 u8 other_vport[0x1]; 6628 u8 reserved_at_41[0xb]; 6629 u8 port_num[0x4]; 6630 u8 vport_number[0x10]; 6631 6632 u8 reserved_at_60[0x20]; 6633 6634 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6635 }; 6636 6637 struct mlx5_ifc_modify_cq_out_bits { 6638 u8 status[0x8]; 6639 u8 reserved_at_8[0x18]; 6640 6641 u8 syndrome[0x20]; 6642 6643 u8 reserved_at_40[0x40]; 6644 }; 6645 6646 enum { 6647 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6648 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6649 }; 6650 6651 struct mlx5_ifc_modify_cq_in_bits { 6652 u8 opcode[0x10]; 6653 u8 uid[0x10]; 6654 6655 u8 reserved_at_20[0x10]; 6656 u8 op_mod[0x10]; 6657 6658 u8 reserved_at_40[0x8]; 6659 u8 cqn[0x18]; 6660 6661 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6662 6663 struct mlx5_ifc_cqc_bits cq_context; 6664 6665 u8 reserved_at_280[0x60]; 6666 6667 u8 cq_umem_valid[0x1]; 6668 u8 reserved_at_2e1[0x1f]; 6669 6670 u8 reserved_at_300[0x580]; 6671 6672 u8 pas[][0x40]; 6673 }; 6674 6675 struct mlx5_ifc_modify_cong_status_out_bits { 6676 u8 status[0x8]; 6677 u8 reserved_at_8[0x18]; 6678 6679 u8 syndrome[0x20]; 6680 6681 u8 reserved_at_40[0x40]; 6682 }; 6683 6684 struct mlx5_ifc_modify_cong_status_in_bits { 6685 u8 opcode[0x10]; 6686 u8 reserved_at_10[0x10]; 6687 6688 u8 reserved_at_20[0x10]; 6689 u8 op_mod[0x10]; 6690 6691 u8 reserved_at_40[0x18]; 6692 u8 priority[0x4]; 6693 u8 cong_protocol[0x4]; 6694 6695 u8 enable[0x1]; 6696 u8 tag_enable[0x1]; 6697 u8 reserved_at_62[0x1e]; 6698 }; 6699 6700 struct mlx5_ifc_modify_cong_params_out_bits { 6701 u8 status[0x8]; 6702 u8 reserved_at_8[0x18]; 6703 6704 u8 syndrome[0x20]; 6705 6706 u8 reserved_at_40[0x40]; 6707 }; 6708 6709 struct mlx5_ifc_modify_cong_params_in_bits { 6710 u8 opcode[0x10]; 6711 u8 reserved_at_10[0x10]; 6712 6713 u8 reserved_at_20[0x10]; 6714 u8 op_mod[0x10]; 6715 6716 u8 reserved_at_40[0x1c]; 6717 u8 cong_protocol[0x4]; 6718 6719 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6720 6721 u8 reserved_at_80[0x80]; 6722 6723 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6724 }; 6725 6726 struct mlx5_ifc_manage_pages_out_bits { 6727 u8 status[0x8]; 6728 u8 reserved_at_8[0x18]; 6729 6730 u8 syndrome[0x20]; 6731 6732 u8 output_num_entries[0x20]; 6733 6734 u8 reserved_at_60[0x20]; 6735 6736 u8 pas[][0x40]; 6737 }; 6738 6739 enum { 6740 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6741 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6742 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6743 }; 6744 6745 struct mlx5_ifc_manage_pages_in_bits { 6746 u8 opcode[0x10]; 6747 u8 reserved_at_10[0x10]; 6748 6749 u8 reserved_at_20[0x10]; 6750 u8 op_mod[0x10]; 6751 6752 u8 embedded_cpu_function[0x1]; 6753 u8 reserved_at_41[0xf]; 6754 u8 function_id[0x10]; 6755 6756 u8 input_num_entries[0x20]; 6757 6758 u8 pas[][0x40]; 6759 }; 6760 6761 struct mlx5_ifc_mad_ifc_out_bits { 6762 u8 status[0x8]; 6763 u8 reserved_at_8[0x18]; 6764 6765 u8 syndrome[0x20]; 6766 6767 u8 reserved_at_40[0x40]; 6768 6769 u8 response_mad_packet[256][0x8]; 6770 }; 6771 6772 struct mlx5_ifc_mad_ifc_in_bits { 6773 u8 opcode[0x10]; 6774 u8 reserved_at_10[0x10]; 6775 6776 u8 reserved_at_20[0x10]; 6777 u8 op_mod[0x10]; 6778 6779 u8 remote_lid[0x10]; 6780 u8 reserved_at_50[0x8]; 6781 u8 port[0x8]; 6782 6783 u8 reserved_at_60[0x20]; 6784 6785 u8 mad[256][0x8]; 6786 }; 6787 6788 struct mlx5_ifc_init_hca_out_bits { 6789 u8 status[0x8]; 6790 u8 reserved_at_8[0x18]; 6791 6792 u8 syndrome[0x20]; 6793 6794 u8 reserved_at_40[0x40]; 6795 }; 6796 6797 struct mlx5_ifc_init_hca_in_bits { 6798 u8 opcode[0x10]; 6799 u8 reserved_at_10[0x10]; 6800 6801 u8 reserved_at_20[0x10]; 6802 u8 op_mod[0x10]; 6803 6804 u8 reserved_at_40[0x40]; 6805 u8 sw_owner_id[4][0x20]; 6806 }; 6807 6808 struct mlx5_ifc_init2rtr_qp_out_bits { 6809 u8 status[0x8]; 6810 u8 reserved_at_8[0x18]; 6811 6812 u8 syndrome[0x20]; 6813 6814 u8 reserved_at_40[0x20]; 6815 u8 ece[0x20]; 6816 }; 6817 6818 struct mlx5_ifc_init2rtr_qp_in_bits { 6819 u8 opcode[0x10]; 6820 u8 uid[0x10]; 6821 6822 u8 reserved_at_20[0x10]; 6823 u8 op_mod[0x10]; 6824 6825 u8 reserved_at_40[0x8]; 6826 u8 qpn[0x18]; 6827 6828 u8 reserved_at_60[0x20]; 6829 6830 u8 opt_param_mask[0x20]; 6831 6832 u8 ece[0x20]; 6833 6834 struct mlx5_ifc_qpc_bits qpc; 6835 6836 u8 reserved_at_800[0x80]; 6837 }; 6838 6839 struct mlx5_ifc_init2init_qp_out_bits { 6840 u8 status[0x8]; 6841 u8 reserved_at_8[0x18]; 6842 6843 u8 syndrome[0x20]; 6844 6845 u8 reserved_at_40[0x20]; 6846 u8 ece[0x20]; 6847 }; 6848 6849 struct mlx5_ifc_init2init_qp_in_bits { 6850 u8 opcode[0x10]; 6851 u8 uid[0x10]; 6852 6853 u8 reserved_at_20[0x10]; 6854 u8 op_mod[0x10]; 6855 6856 u8 reserved_at_40[0x8]; 6857 u8 qpn[0x18]; 6858 6859 u8 reserved_at_60[0x20]; 6860 6861 u8 opt_param_mask[0x20]; 6862 6863 u8 ece[0x20]; 6864 6865 struct mlx5_ifc_qpc_bits qpc; 6866 6867 u8 reserved_at_800[0x80]; 6868 }; 6869 6870 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6871 u8 status[0x8]; 6872 u8 reserved_at_8[0x18]; 6873 6874 u8 syndrome[0x20]; 6875 6876 u8 reserved_at_40[0x40]; 6877 6878 u8 packet_headers_log[128][0x8]; 6879 6880 u8 packet_syndrome[64][0x8]; 6881 }; 6882 6883 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6884 u8 opcode[0x10]; 6885 u8 reserved_at_10[0x10]; 6886 6887 u8 reserved_at_20[0x10]; 6888 u8 op_mod[0x10]; 6889 6890 u8 reserved_at_40[0x40]; 6891 }; 6892 6893 struct mlx5_ifc_gen_eqe_in_bits { 6894 u8 opcode[0x10]; 6895 u8 reserved_at_10[0x10]; 6896 6897 u8 reserved_at_20[0x10]; 6898 u8 op_mod[0x10]; 6899 6900 u8 reserved_at_40[0x18]; 6901 u8 eq_number[0x8]; 6902 6903 u8 reserved_at_60[0x20]; 6904 6905 u8 eqe[64][0x8]; 6906 }; 6907 6908 struct mlx5_ifc_gen_eq_out_bits { 6909 u8 status[0x8]; 6910 u8 reserved_at_8[0x18]; 6911 6912 u8 syndrome[0x20]; 6913 6914 u8 reserved_at_40[0x40]; 6915 }; 6916 6917 struct mlx5_ifc_enable_hca_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_at_8[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_at_40[0x20]; 6924 }; 6925 6926 struct mlx5_ifc_enable_hca_in_bits { 6927 u8 opcode[0x10]; 6928 u8 reserved_at_10[0x10]; 6929 6930 u8 reserved_at_20[0x10]; 6931 u8 op_mod[0x10]; 6932 6933 u8 embedded_cpu_function[0x1]; 6934 u8 reserved_at_41[0xf]; 6935 u8 function_id[0x10]; 6936 6937 u8 reserved_at_60[0x20]; 6938 }; 6939 6940 struct mlx5_ifc_drain_dct_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_at_8[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_at_40[0x40]; 6947 }; 6948 6949 struct mlx5_ifc_drain_dct_in_bits { 6950 u8 opcode[0x10]; 6951 u8 uid[0x10]; 6952 6953 u8 reserved_at_20[0x10]; 6954 u8 op_mod[0x10]; 6955 6956 u8 reserved_at_40[0x8]; 6957 u8 dctn[0x18]; 6958 6959 u8 reserved_at_60[0x20]; 6960 }; 6961 6962 struct mlx5_ifc_disable_hca_out_bits { 6963 u8 status[0x8]; 6964 u8 reserved_at_8[0x18]; 6965 6966 u8 syndrome[0x20]; 6967 6968 u8 reserved_at_40[0x20]; 6969 }; 6970 6971 struct mlx5_ifc_disable_hca_in_bits { 6972 u8 opcode[0x10]; 6973 u8 reserved_at_10[0x10]; 6974 6975 u8 reserved_at_20[0x10]; 6976 u8 op_mod[0x10]; 6977 6978 u8 embedded_cpu_function[0x1]; 6979 u8 reserved_at_41[0xf]; 6980 u8 function_id[0x10]; 6981 6982 u8 reserved_at_60[0x20]; 6983 }; 6984 6985 struct mlx5_ifc_detach_from_mcg_out_bits { 6986 u8 status[0x8]; 6987 u8 reserved_at_8[0x18]; 6988 6989 u8 syndrome[0x20]; 6990 6991 u8 reserved_at_40[0x40]; 6992 }; 6993 6994 struct mlx5_ifc_detach_from_mcg_in_bits { 6995 u8 opcode[0x10]; 6996 u8 uid[0x10]; 6997 6998 u8 reserved_at_20[0x10]; 6999 u8 op_mod[0x10]; 7000 7001 u8 reserved_at_40[0x8]; 7002 u8 qpn[0x18]; 7003 7004 u8 reserved_at_60[0x20]; 7005 7006 u8 multicast_gid[16][0x8]; 7007 }; 7008 7009 struct mlx5_ifc_destroy_xrq_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x40]; 7016 }; 7017 7018 struct mlx5_ifc_destroy_xrq_in_bits { 7019 u8 opcode[0x10]; 7020 u8 uid[0x10]; 7021 7022 u8 reserved_at_20[0x10]; 7023 u8 op_mod[0x10]; 7024 7025 u8 reserved_at_40[0x8]; 7026 u8 xrqn[0x18]; 7027 7028 u8 reserved_at_60[0x20]; 7029 }; 7030 7031 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x40]; 7038 }; 7039 7040 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7041 u8 opcode[0x10]; 7042 u8 uid[0x10]; 7043 7044 u8 reserved_at_20[0x10]; 7045 u8 op_mod[0x10]; 7046 7047 u8 reserved_at_40[0x8]; 7048 u8 xrc_srqn[0x18]; 7049 7050 u8 reserved_at_60[0x20]; 7051 }; 7052 7053 struct mlx5_ifc_destroy_tis_out_bits { 7054 u8 status[0x8]; 7055 u8 reserved_at_8[0x18]; 7056 7057 u8 syndrome[0x20]; 7058 7059 u8 reserved_at_40[0x40]; 7060 }; 7061 7062 struct mlx5_ifc_destroy_tis_in_bits { 7063 u8 opcode[0x10]; 7064 u8 uid[0x10]; 7065 7066 u8 reserved_at_20[0x10]; 7067 u8 op_mod[0x10]; 7068 7069 u8 reserved_at_40[0x8]; 7070 u8 tisn[0x18]; 7071 7072 u8 reserved_at_60[0x20]; 7073 }; 7074 7075 struct mlx5_ifc_destroy_tir_out_bits { 7076 u8 status[0x8]; 7077 u8 reserved_at_8[0x18]; 7078 7079 u8 syndrome[0x20]; 7080 7081 u8 reserved_at_40[0x40]; 7082 }; 7083 7084 struct mlx5_ifc_destroy_tir_in_bits { 7085 u8 opcode[0x10]; 7086 u8 uid[0x10]; 7087 7088 u8 reserved_at_20[0x10]; 7089 u8 op_mod[0x10]; 7090 7091 u8 reserved_at_40[0x8]; 7092 u8 tirn[0x18]; 7093 7094 u8 reserved_at_60[0x20]; 7095 }; 7096 7097 struct mlx5_ifc_destroy_srq_out_bits { 7098 u8 status[0x8]; 7099 u8 reserved_at_8[0x18]; 7100 7101 u8 syndrome[0x20]; 7102 7103 u8 reserved_at_40[0x40]; 7104 }; 7105 7106 struct mlx5_ifc_destroy_srq_in_bits { 7107 u8 opcode[0x10]; 7108 u8 uid[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0x8]; 7114 u8 srqn[0x18]; 7115 7116 u8 reserved_at_60[0x20]; 7117 }; 7118 7119 struct mlx5_ifc_destroy_sq_out_bits { 7120 u8 status[0x8]; 7121 u8 reserved_at_8[0x18]; 7122 7123 u8 syndrome[0x20]; 7124 7125 u8 reserved_at_40[0x40]; 7126 }; 7127 7128 struct mlx5_ifc_destroy_sq_in_bits { 7129 u8 opcode[0x10]; 7130 u8 uid[0x10]; 7131 7132 u8 reserved_at_20[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 reserved_at_40[0x8]; 7136 u8 sqn[0x18]; 7137 7138 u8 reserved_at_60[0x20]; 7139 }; 7140 7141 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7142 u8 status[0x8]; 7143 u8 reserved_at_8[0x18]; 7144 7145 u8 syndrome[0x20]; 7146 7147 u8 reserved_at_40[0x1c0]; 7148 }; 7149 7150 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7151 u8 opcode[0x10]; 7152 u8 reserved_at_10[0x10]; 7153 7154 u8 reserved_at_20[0x10]; 7155 u8 op_mod[0x10]; 7156 7157 u8 scheduling_hierarchy[0x8]; 7158 u8 reserved_at_48[0x18]; 7159 7160 u8 scheduling_element_id[0x20]; 7161 7162 u8 reserved_at_80[0x180]; 7163 }; 7164 7165 struct mlx5_ifc_destroy_rqt_out_bits { 7166 u8 status[0x8]; 7167 u8 reserved_at_8[0x18]; 7168 7169 u8 syndrome[0x20]; 7170 7171 u8 reserved_at_40[0x40]; 7172 }; 7173 7174 struct mlx5_ifc_destroy_rqt_in_bits { 7175 u8 opcode[0x10]; 7176 u8 uid[0x10]; 7177 7178 u8 reserved_at_20[0x10]; 7179 u8 op_mod[0x10]; 7180 7181 u8 reserved_at_40[0x8]; 7182 u8 rqtn[0x18]; 7183 7184 u8 reserved_at_60[0x20]; 7185 }; 7186 7187 struct mlx5_ifc_destroy_rq_out_bits { 7188 u8 status[0x8]; 7189 u8 reserved_at_8[0x18]; 7190 7191 u8 syndrome[0x20]; 7192 7193 u8 reserved_at_40[0x40]; 7194 }; 7195 7196 struct mlx5_ifc_destroy_rq_in_bits { 7197 u8 opcode[0x10]; 7198 u8 uid[0x10]; 7199 7200 u8 reserved_at_20[0x10]; 7201 u8 op_mod[0x10]; 7202 7203 u8 reserved_at_40[0x8]; 7204 u8 rqn[0x18]; 7205 7206 u8 reserved_at_60[0x20]; 7207 }; 7208 7209 struct mlx5_ifc_set_delay_drop_params_in_bits { 7210 u8 opcode[0x10]; 7211 u8 reserved_at_10[0x10]; 7212 7213 u8 reserved_at_20[0x10]; 7214 u8 op_mod[0x10]; 7215 7216 u8 reserved_at_40[0x20]; 7217 7218 u8 reserved_at_60[0x10]; 7219 u8 delay_drop_timeout[0x10]; 7220 }; 7221 7222 struct mlx5_ifc_set_delay_drop_params_out_bits { 7223 u8 status[0x8]; 7224 u8 reserved_at_8[0x18]; 7225 7226 u8 syndrome[0x20]; 7227 7228 u8 reserved_at_40[0x40]; 7229 }; 7230 7231 struct mlx5_ifc_destroy_rmp_out_bits { 7232 u8 status[0x8]; 7233 u8 reserved_at_8[0x18]; 7234 7235 u8 syndrome[0x20]; 7236 7237 u8 reserved_at_40[0x40]; 7238 }; 7239 7240 struct mlx5_ifc_destroy_rmp_in_bits { 7241 u8 opcode[0x10]; 7242 u8 uid[0x10]; 7243 7244 u8 reserved_at_20[0x10]; 7245 u8 op_mod[0x10]; 7246 7247 u8 reserved_at_40[0x8]; 7248 u8 rmpn[0x18]; 7249 7250 u8 reserved_at_60[0x20]; 7251 }; 7252 7253 struct mlx5_ifc_destroy_qp_out_bits { 7254 u8 status[0x8]; 7255 u8 reserved_at_8[0x18]; 7256 7257 u8 syndrome[0x20]; 7258 7259 u8 reserved_at_40[0x40]; 7260 }; 7261 7262 struct mlx5_ifc_destroy_qp_in_bits { 7263 u8 opcode[0x10]; 7264 u8 uid[0x10]; 7265 7266 u8 reserved_at_20[0x10]; 7267 u8 op_mod[0x10]; 7268 7269 u8 reserved_at_40[0x8]; 7270 u8 qpn[0x18]; 7271 7272 u8 reserved_at_60[0x20]; 7273 }; 7274 7275 struct mlx5_ifc_destroy_psv_out_bits { 7276 u8 status[0x8]; 7277 u8 reserved_at_8[0x18]; 7278 7279 u8 syndrome[0x20]; 7280 7281 u8 reserved_at_40[0x40]; 7282 }; 7283 7284 struct mlx5_ifc_destroy_psv_in_bits { 7285 u8 opcode[0x10]; 7286 u8 reserved_at_10[0x10]; 7287 7288 u8 reserved_at_20[0x10]; 7289 u8 op_mod[0x10]; 7290 7291 u8 reserved_at_40[0x8]; 7292 u8 psvn[0x18]; 7293 7294 u8 reserved_at_60[0x20]; 7295 }; 7296 7297 struct mlx5_ifc_destroy_mkey_out_bits { 7298 u8 status[0x8]; 7299 u8 reserved_at_8[0x18]; 7300 7301 u8 syndrome[0x20]; 7302 7303 u8 reserved_at_40[0x40]; 7304 }; 7305 7306 struct mlx5_ifc_destroy_mkey_in_bits { 7307 u8 opcode[0x10]; 7308 u8 uid[0x10]; 7309 7310 u8 reserved_at_20[0x10]; 7311 u8 op_mod[0x10]; 7312 7313 u8 reserved_at_40[0x8]; 7314 u8 mkey_index[0x18]; 7315 7316 u8 reserved_at_60[0x20]; 7317 }; 7318 7319 struct mlx5_ifc_destroy_flow_table_out_bits { 7320 u8 status[0x8]; 7321 u8 reserved_at_8[0x18]; 7322 7323 u8 syndrome[0x20]; 7324 7325 u8 reserved_at_40[0x40]; 7326 }; 7327 7328 struct mlx5_ifc_destroy_flow_table_in_bits { 7329 u8 opcode[0x10]; 7330 u8 reserved_at_10[0x10]; 7331 7332 u8 reserved_at_20[0x10]; 7333 u8 op_mod[0x10]; 7334 7335 u8 other_vport[0x1]; 7336 u8 reserved_at_41[0xf]; 7337 u8 vport_number[0x10]; 7338 7339 u8 reserved_at_60[0x20]; 7340 7341 u8 table_type[0x8]; 7342 u8 reserved_at_88[0x18]; 7343 7344 u8 reserved_at_a0[0x8]; 7345 u8 table_id[0x18]; 7346 7347 u8 reserved_at_c0[0x140]; 7348 }; 7349 7350 struct mlx5_ifc_destroy_flow_group_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_at_8[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 reserved_at_40[0x40]; 7357 }; 7358 7359 struct mlx5_ifc_destroy_flow_group_in_bits { 7360 u8 opcode[0x10]; 7361 u8 reserved_at_10[0x10]; 7362 7363 u8 reserved_at_20[0x10]; 7364 u8 op_mod[0x10]; 7365 7366 u8 other_vport[0x1]; 7367 u8 reserved_at_41[0xf]; 7368 u8 vport_number[0x10]; 7369 7370 u8 reserved_at_60[0x20]; 7371 7372 u8 table_type[0x8]; 7373 u8 reserved_at_88[0x18]; 7374 7375 u8 reserved_at_a0[0x8]; 7376 u8 table_id[0x18]; 7377 7378 u8 group_id[0x20]; 7379 7380 u8 reserved_at_e0[0x120]; 7381 }; 7382 7383 struct mlx5_ifc_destroy_eq_out_bits { 7384 u8 status[0x8]; 7385 u8 reserved_at_8[0x18]; 7386 7387 u8 syndrome[0x20]; 7388 7389 u8 reserved_at_40[0x40]; 7390 }; 7391 7392 struct mlx5_ifc_destroy_eq_in_bits { 7393 u8 opcode[0x10]; 7394 u8 reserved_at_10[0x10]; 7395 7396 u8 reserved_at_20[0x10]; 7397 u8 op_mod[0x10]; 7398 7399 u8 reserved_at_40[0x18]; 7400 u8 eq_number[0x8]; 7401 7402 u8 reserved_at_60[0x20]; 7403 }; 7404 7405 struct mlx5_ifc_destroy_dct_out_bits { 7406 u8 status[0x8]; 7407 u8 reserved_at_8[0x18]; 7408 7409 u8 syndrome[0x20]; 7410 7411 u8 reserved_at_40[0x40]; 7412 }; 7413 7414 struct mlx5_ifc_destroy_dct_in_bits { 7415 u8 opcode[0x10]; 7416 u8 uid[0x10]; 7417 7418 u8 reserved_at_20[0x10]; 7419 u8 op_mod[0x10]; 7420 7421 u8 reserved_at_40[0x8]; 7422 u8 dctn[0x18]; 7423 7424 u8 reserved_at_60[0x20]; 7425 }; 7426 7427 struct mlx5_ifc_destroy_cq_out_bits { 7428 u8 status[0x8]; 7429 u8 reserved_at_8[0x18]; 7430 7431 u8 syndrome[0x20]; 7432 7433 u8 reserved_at_40[0x40]; 7434 }; 7435 7436 struct mlx5_ifc_destroy_cq_in_bits { 7437 u8 opcode[0x10]; 7438 u8 uid[0x10]; 7439 7440 u8 reserved_at_20[0x10]; 7441 u8 op_mod[0x10]; 7442 7443 u8 reserved_at_40[0x8]; 7444 u8 cqn[0x18]; 7445 7446 u8 reserved_at_60[0x20]; 7447 }; 7448 7449 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7450 u8 status[0x8]; 7451 u8 reserved_at_8[0x18]; 7452 7453 u8 syndrome[0x20]; 7454 7455 u8 reserved_at_40[0x40]; 7456 }; 7457 7458 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7459 u8 opcode[0x10]; 7460 u8 reserved_at_10[0x10]; 7461 7462 u8 reserved_at_20[0x10]; 7463 u8 op_mod[0x10]; 7464 7465 u8 reserved_at_40[0x20]; 7466 7467 u8 reserved_at_60[0x10]; 7468 u8 vxlan_udp_port[0x10]; 7469 }; 7470 7471 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7472 u8 status[0x8]; 7473 u8 reserved_at_8[0x18]; 7474 7475 u8 syndrome[0x20]; 7476 7477 u8 reserved_at_40[0x40]; 7478 }; 7479 7480 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7481 u8 opcode[0x10]; 7482 u8 reserved_at_10[0x10]; 7483 7484 u8 reserved_at_20[0x10]; 7485 u8 op_mod[0x10]; 7486 7487 u8 reserved_at_40[0x60]; 7488 7489 u8 reserved_at_a0[0x8]; 7490 u8 table_index[0x18]; 7491 7492 u8 reserved_at_c0[0x140]; 7493 }; 7494 7495 struct mlx5_ifc_delete_fte_out_bits { 7496 u8 status[0x8]; 7497 u8 reserved_at_8[0x18]; 7498 7499 u8 syndrome[0x20]; 7500 7501 u8 reserved_at_40[0x40]; 7502 }; 7503 7504 struct mlx5_ifc_delete_fte_in_bits { 7505 u8 opcode[0x10]; 7506 u8 reserved_at_10[0x10]; 7507 7508 u8 reserved_at_20[0x10]; 7509 u8 op_mod[0x10]; 7510 7511 u8 other_vport[0x1]; 7512 u8 reserved_at_41[0xf]; 7513 u8 vport_number[0x10]; 7514 7515 u8 reserved_at_60[0x20]; 7516 7517 u8 table_type[0x8]; 7518 u8 reserved_at_88[0x18]; 7519 7520 u8 reserved_at_a0[0x8]; 7521 u8 table_id[0x18]; 7522 7523 u8 reserved_at_c0[0x40]; 7524 7525 u8 flow_index[0x20]; 7526 7527 u8 reserved_at_120[0xe0]; 7528 }; 7529 7530 struct mlx5_ifc_dealloc_xrcd_out_bits { 7531 u8 status[0x8]; 7532 u8 reserved_at_8[0x18]; 7533 7534 u8 syndrome[0x20]; 7535 7536 u8 reserved_at_40[0x40]; 7537 }; 7538 7539 struct mlx5_ifc_dealloc_xrcd_in_bits { 7540 u8 opcode[0x10]; 7541 u8 uid[0x10]; 7542 7543 u8 reserved_at_20[0x10]; 7544 u8 op_mod[0x10]; 7545 7546 u8 reserved_at_40[0x8]; 7547 u8 xrcd[0x18]; 7548 7549 u8 reserved_at_60[0x20]; 7550 }; 7551 7552 struct mlx5_ifc_dealloc_uar_out_bits { 7553 u8 status[0x8]; 7554 u8 reserved_at_8[0x18]; 7555 7556 u8 syndrome[0x20]; 7557 7558 u8 reserved_at_40[0x40]; 7559 }; 7560 7561 struct mlx5_ifc_dealloc_uar_in_bits { 7562 u8 opcode[0x10]; 7563 u8 reserved_at_10[0x10]; 7564 7565 u8 reserved_at_20[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 reserved_at_40[0x8]; 7569 u8 uar[0x18]; 7570 7571 u8 reserved_at_60[0x20]; 7572 }; 7573 7574 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7575 u8 status[0x8]; 7576 u8 reserved_at_8[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 reserved_at_40[0x40]; 7581 }; 7582 7583 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7584 u8 opcode[0x10]; 7585 u8 uid[0x10]; 7586 7587 u8 reserved_at_20[0x10]; 7588 u8 op_mod[0x10]; 7589 7590 u8 reserved_at_40[0x8]; 7591 u8 transport_domain[0x18]; 7592 7593 u8 reserved_at_60[0x20]; 7594 }; 7595 7596 struct mlx5_ifc_dealloc_q_counter_out_bits { 7597 u8 status[0x8]; 7598 u8 reserved_at_8[0x18]; 7599 7600 u8 syndrome[0x20]; 7601 7602 u8 reserved_at_40[0x40]; 7603 }; 7604 7605 struct mlx5_ifc_dealloc_q_counter_in_bits { 7606 u8 opcode[0x10]; 7607 u8 reserved_at_10[0x10]; 7608 7609 u8 reserved_at_20[0x10]; 7610 u8 op_mod[0x10]; 7611 7612 u8 reserved_at_40[0x18]; 7613 u8 counter_set_id[0x8]; 7614 7615 u8 reserved_at_60[0x20]; 7616 }; 7617 7618 struct mlx5_ifc_dealloc_pd_out_bits { 7619 u8 status[0x8]; 7620 u8 reserved_at_8[0x18]; 7621 7622 u8 syndrome[0x20]; 7623 7624 u8 reserved_at_40[0x40]; 7625 }; 7626 7627 struct mlx5_ifc_dealloc_pd_in_bits { 7628 u8 opcode[0x10]; 7629 u8 uid[0x10]; 7630 7631 u8 reserved_at_20[0x10]; 7632 u8 op_mod[0x10]; 7633 7634 u8 reserved_at_40[0x8]; 7635 u8 pd[0x18]; 7636 7637 u8 reserved_at_60[0x20]; 7638 }; 7639 7640 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7641 u8 status[0x8]; 7642 u8 reserved_at_8[0x18]; 7643 7644 u8 syndrome[0x20]; 7645 7646 u8 reserved_at_40[0x40]; 7647 }; 7648 7649 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7650 u8 opcode[0x10]; 7651 u8 reserved_at_10[0x10]; 7652 7653 u8 reserved_at_20[0x10]; 7654 u8 op_mod[0x10]; 7655 7656 u8 flow_counter_id[0x20]; 7657 7658 u8 reserved_at_60[0x20]; 7659 }; 7660 7661 struct mlx5_ifc_create_xrq_out_bits { 7662 u8 status[0x8]; 7663 u8 reserved_at_8[0x18]; 7664 7665 u8 syndrome[0x20]; 7666 7667 u8 reserved_at_40[0x8]; 7668 u8 xrqn[0x18]; 7669 7670 u8 reserved_at_60[0x20]; 7671 }; 7672 7673 struct mlx5_ifc_create_xrq_in_bits { 7674 u8 opcode[0x10]; 7675 u8 uid[0x10]; 7676 7677 u8 reserved_at_20[0x10]; 7678 u8 op_mod[0x10]; 7679 7680 u8 reserved_at_40[0x40]; 7681 7682 struct mlx5_ifc_xrqc_bits xrq_context; 7683 }; 7684 7685 struct mlx5_ifc_create_xrc_srq_out_bits { 7686 u8 status[0x8]; 7687 u8 reserved_at_8[0x18]; 7688 7689 u8 syndrome[0x20]; 7690 7691 u8 reserved_at_40[0x8]; 7692 u8 xrc_srqn[0x18]; 7693 7694 u8 reserved_at_60[0x20]; 7695 }; 7696 7697 struct mlx5_ifc_create_xrc_srq_in_bits { 7698 u8 opcode[0x10]; 7699 u8 uid[0x10]; 7700 7701 u8 reserved_at_20[0x10]; 7702 u8 op_mod[0x10]; 7703 7704 u8 reserved_at_40[0x40]; 7705 7706 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7707 7708 u8 reserved_at_280[0x60]; 7709 7710 u8 xrc_srq_umem_valid[0x1]; 7711 u8 reserved_at_2e1[0x1f]; 7712 7713 u8 reserved_at_300[0x580]; 7714 7715 u8 pas[][0x40]; 7716 }; 7717 7718 struct mlx5_ifc_create_tis_out_bits { 7719 u8 status[0x8]; 7720 u8 reserved_at_8[0x18]; 7721 7722 u8 syndrome[0x20]; 7723 7724 u8 reserved_at_40[0x8]; 7725 u8 tisn[0x18]; 7726 7727 u8 reserved_at_60[0x20]; 7728 }; 7729 7730 struct mlx5_ifc_create_tis_in_bits { 7731 u8 opcode[0x10]; 7732 u8 uid[0x10]; 7733 7734 u8 reserved_at_20[0x10]; 7735 u8 op_mod[0x10]; 7736 7737 u8 reserved_at_40[0xc0]; 7738 7739 struct mlx5_ifc_tisc_bits ctx; 7740 }; 7741 7742 struct mlx5_ifc_create_tir_out_bits { 7743 u8 status[0x8]; 7744 u8 icm_address_63_40[0x18]; 7745 7746 u8 syndrome[0x20]; 7747 7748 u8 icm_address_39_32[0x8]; 7749 u8 tirn[0x18]; 7750 7751 u8 icm_address_31_0[0x20]; 7752 }; 7753 7754 struct mlx5_ifc_create_tir_in_bits { 7755 u8 opcode[0x10]; 7756 u8 uid[0x10]; 7757 7758 u8 reserved_at_20[0x10]; 7759 u8 op_mod[0x10]; 7760 7761 u8 reserved_at_40[0xc0]; 7762 7763 struct mlx5_ifc_tirc_bits ctx; 7764 }; 7765 7766 struct mlx5_ifc_create_srq_out_bits { 7767 u8 status[0x8]; 7768 u8 reserved_at_8[0x18]; 7769 7770 u8 syndrome[0x20]; 7771 7772 u8 reserved_at_40[0x8]; 7773 u8 srqn[0x18]; 7774 7775 u8 reserved_at_60[0x20]; 7776 }; 7777 7778 struct mlx5_ifc_create_srq_in_bits { 7779 u8 opcode[0x10]; 7780 u8 uid[0x10]; 7781 7782 u8 reserved_at_20[0x10]; 7783 u8 op_mod[0x10]; 7784 7785 u8 reserved_at_40[0x40]; 7786 7787 struct mlx5_ifc_srqc_bits srq_context_entry; 7788 7789 u8 reserved_at_280[0x600]; 7790 7791 u8 pas[][0x40]; 7792 }; 7793 7794 struct mlx5_ifc_create_sq_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_at_8[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_at_40[0x8]; 7801 u8 sqn[0x18]; 7802 7803 u8 reserved_at_60[0x20]; 7804 }; 7805 7806 struct mlx5_ifc_create_sq_in_bits { 7807 u8 opcode[0x10]; 7808 u8 uid[0x10]; 7809 7810 u8 reserved_at_20[0x10]; 7811 u8 op_mod[0x10]; 7812 7813 u8 reserved_at_40[0xc0]; 7814 7815 struct mlx5_ifc_sqc_bits ctx; 7816 }; 7817 7818 struct mlx5_ifc_create_scheduling_element_out_bits { 7819 u8 status[0x8]; 7820 u8 reserved_at_8[0x18]; 7821 7822 u8 syndrome[0x20]; 7823 7824 u8 reserved_at_40[0x40]; 7825 7826 u8 scheduling_element_id[0x20]; 7827 7828 u8 reserved_at_a0[0x160]; 7829 }; 7830 7831 struct mlx5_ifc_create_scheduling_element_in_bits { 7832 u8 opcode[0x10]; 7833 u8 reserved_at_10[0x10]; 7834 7835 u8 reserved_at_20[0x10]; 7836 u8 op_mod[0x10]; 7837 7838 u8 scheduling_hierarchy[0x8]; 7839 u8 reserved_at_48[0x18]; 7840 7841 u8 reserved_at_60[0xa0]; 7842 7843 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7844 7845 u8 reserved_at_300[0x100]; 7846 }; 7847 7848 struct mlx5_ifc_create_rqt_out_bits { 7849 u8 status[0x8]; 7850 u8 reserved_at_8[0x18]; 7851 7852 u8 syndrome[0x20]; 7853 7854 u8 reserved_at_40[0x8]; 7855 u8 rqtn[0x18]; 7856 7857 u8 reserved_at_60[0x20]; 7858 }; 7859 7860 struct mlx5_ifc_create_rqt_in_bits { 7861 u8 opcode[0x10]; 7862 u8 uid[0x10]; 7863 7864 u8 reserved_at_20[0x10]; 7865 u8 op_mod[0x10]; 7866 7867 u8 reserved_at_40[0xc0]; 7868 7869 struct mlx5_ifc_rqtc_bits rqt_context; 7870 }; 7871 7872 struct mlx5_ifc_create_rq_out_bits { 7873 u8 status[0x8]; 7874 u8 reserved_at_8[0x18]; 7875 7876 u8 syndrome[0x20]; 7877 7878 u8 reserved_at_40[0x8]; 7879 u8 rqn[0x18]; 7880 7881 u8 reserved_at_60[0x20]; 7882 }; 7883 7884 struct mlx5_ifc_create_rq_in_bits { 7885 u8 opcode[0x10]; 7886 u8 uid[0x10]; 7887 7888 u8 reserved_at_20[0x10]; 7889 u8 op_mod[0x10]; 7890 7891 u8 reserved_at_40[0xc0]; 7892 7893 struct mlx5_ifc_rqc_bits ctx; 7894 }; 7895 7896 struct mlx5_ifc_create_rmp_out_bits { 7897 u8 status[0x8]; 7898 u8 reserved_at_8[0x18]; 7899 7900 u8 syndrome[0x20]; 7901 7902 u8 reserved_at_40[0x8]; 7903 u8 rmpn[0x18]; 7904 7905 u8 reserved_at_60[0x20]; 7906 }; 7907 7908 struct mlx5_ifc_create_rmp_in_bits { 7909 u8 opcode[0x10]; 7910 u8 uid[0x10]; 7911 7912 u8 reserved_at_20[0x10]; 7913 u8 op_mod[0x10]; 7914 7915 u8 reserved_at_40[0xc0]; 7916 7917 struct mlx5_ifc_rmpc_bits ctx; 7918 }; 7919 7920 struct mlx5_ifc_create_qp_out_bits { 7921 u8 status[0x8]; 7922 u8 reserved_at_8[0x18]; 7923 7924 u8 syndrome[0x20]; 7925 7926 u8 reserved_at_40[0x8]; 7927 u8 qpn[0x18]; 7928 7929 u8 ece[0x20]; 7930 }; 7931 7932 struct mlx5_ifc_create_qp_in_bits { 7933 u8 opcode[0x10]; 7934 u8 uid[0x10]; 7935 7936 u8 reserved_at_20[0x10]; 7937 u8 op_mod[0x10]; 7938 7939 u8 reserved_at_40[0x8]; 7940 u8 input_qpn[0x18]; 7941 7942 u8 reserved_at_60[0x20]; 7943 u8 opt_param_mask[0x20]; 7944 7945 u8 ece[0x20]; 7946 7947 struct mlx5_ifc_qpc_bits qpc; 7948 7949 u8 reserved_at_800[0x60]; 7950 7951 u8 wq_umem_valid[0x1]; 7952 u8 reserved_at_861[0x1f]; 7953 7954 u8 pas[][0x40]; 7955 }; 7956 7957 struct mlx5_ifc_create_psv_out_bits { 7958 u8 status[0x8]; 7959 u8 reserved_at_8[0x18]; 7960 7961 u8 syndrome[0x20]; 7962 7963 u8 reserved_at_40[0x40]; 7964 7965 u8 reserved_at_80[0x8]; 7966 u8 psv0_index[0x18]; 7967 7968 u8 reserved_at_a0[0x8]; 7969 u8 psv1_index[0x18]; 7970 7971 u8 reserved_at_c0[0x8]; 7972 u8 psv2_index[0x18]; 7973 7974 u8 reserved_at_e0[0x8]; 7975 u8 psv3_index[0x18]; 7976 }; 7977 7978 struct mlx5_ifc_create_psv_in_bits { 7979 u8 opcode[0x10]; 7980 u8 reserved_at_10[0x10]; 7981 7982 u8 reserved_at_20[0x10]; 7983 u8 op_mod[0x10]; 7984 7985 u8 num_psv[0x4]; 7986 u8 reserved_at_44[0x4]; 7987 u8 pd[0x18]; 7988 7989 u8 reserved_at_60[0x20]; 7990 }; 7991 7992 struct mlx5_ifc_create_mkey_out_bits { 7993 u8 status[0x8]; 7994 u8 reserved_at_8[0x18]; 7995 7996 u8 syndrome[0x20]; 7997 7998 u8 reserved_at_40[0x8]; 7999 u8 mkey_index[0x18]; 8000 8001 u8 reserved_at_60[0x20]; 8002 }; 8003 8004 struct mlx5_ifc_create_mkey_in_bits { 8005 u8 opcode[0x10]; 8006 u8 uid[0x10]; 8007 8008 u8 reserved_at_20[0x10]; 8009 u8 op_mod[0x10]; 8010 8011 u8 reserved_at_40[0x20]; 8012 8013 u8 pg_access[0x1]; 8014 u8 mkey_umem_valid[0x1]; 8015 u8 reserved_at_62[0x1e]; 8016 8017 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8018 8019 u8 reserved_at_280[0x80]; 8020 8021 u8 translations_octword_actual_size[0x20]; 8022 8023 u8 reserved_at_320[0x560]; 8024 8025 u8 klm_pas_mtt[][0x20]; 8026 }; 8027 8028 enum { 8029 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8030 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8031 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8032 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8033 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8034 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8035 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8036 }; 8037 8038 struct mlx5_ifc_create_flow_table_out_bits { 8039 u8 status[0x8]; 8040 u8 icm_address_63_40[0x18]; 8041 8042 u8 syndrome[0x20]; 8043 8044 u8 icm_address_39_32[0x8]; 8045 u8 table_id[0x18]; 8046 8047 u8 icm_address_31_0[0x20]; 8048 }; 8049 8050 struct mlx5_ifc_create_flow_table_in_bits { 8051 u8 opcode[0x10]; 8052 u8 reserved_at_10[0x10]; 8053 8054 u8 reserved_at_20[0x10]; 8055 u8 op_mod[0x10]; 8056 8057 u8 other_vport[0x1]; 8058 u8 reserved_at_41[0xf]; 8059 u8 vport_number[0x10]; 8060 8061 u8 reserved_at_60[0x20]; 8062 8063 u8 table_type[0x8]; 8064 u8 reserved_at_88[0x18]; 8065 8066 u8 reserved_at_a0[0x20]; 8067 8068 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8069 }; 8070 8071 struct mlx5_ifc_create_flow_group_out_bits { 8072 u8 status[0x8]; 8073 u8 reserved_at_8[0x18]; 8074 8075 u8 syndrome[0x20]; 8076 8077 u8 reserved_at_40[0x8]; 8078 u8 group_id[0x18]; 8079 8080 u8 reserved_at_60[0x20]; 8081 }; 8082 8083 enum { 8084 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8085 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8086 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8087 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8088 }; 8089 8090 struct mlx5_ifc_create_flow_group_in_bits { 8091 u8 opcode[0x10]; 8092 u8 reserved_at_10[0x10]; 8093 8094 u8 reserved_at_20[0x10]; 8095 u8 op_mod[0x10]; 8096 8097 u8 other_vport[0x1]; 8098 u8 reserved_at_41[0xf]; 8099 u8 vport_number[0x10]; 8100 8101 u8 reserved_at_60[0x20]; 8102 8103 u8 table_type[0x8]; 8104 u8 reserved_at_88[0x18]; 8105 8106 u8 reserved_at_a0[0x8]; 8107 u8 table_id[0x18]; 8108 8109 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8110 8111 u8 reserved_at_c1[0x1f]; 8112 8113 u8 start_flow_index[0x20]; 8114 8115 u8 reserved_at_100[0x20]; 8116 8117 u8 end_flow_index[0x20]; 8118 8119 u8 reserved_at_140[0xa0]; 8120 8121 u8 reserved_at_1e0[0x18]; 8122 u8 match_criteria_enable[0x8]; 8123 8124 struct mlx5_ifc_fte_match_param_bits match_criteria; 8125 8126 u8 reserved_at_1200[0xe00]; 8127 }; 8128 8129 struct mlx5_ifc_create_eq_out_bits { 8130 u8 status[0x8]; 8131 u8 reserved_at_8[0x18]; 8132 8133 u8 syndrome[0x20]; 8134 8135 u8 reserved_at_40[0x18]; 8136 u8 eq_number[0x8]; 8137 8138 u8 reserved_at_60[0x20]; 8139 }; 8140 8141 struct mlx5_ifc_create_eq_in_bits { 8142 u8 opcode[0x10]; 8143 u8 uid[0x10]; 8144 8145 u8 reserved_at_20[0x10]; 8146 u8 op_mod[0x10]; 8147 8148 u8 reserved_at_40[0x40]; 8149 8150 struct mlx5_ifc_eqc_bits eq_context_entry; 8151 8152 u8 reserved_at_280[0x40]; 8153 8154 u8 event_bitmask[4][0x40]; 8155 8156 u8 reserved_at_3c0[0x4c0]; 8157 8158 u8 pas[][0x40]; 8159 }; 8160 8161 struct mlx5_ifc_create_dct_out_bits { 8162 u8 status[0x8]; 8163 u8 reserved_at_8[0x18]; 8164 8165 u8 syndrome[0x20]; 8166 8167 u8 reserved_at_40[0x8]; 8168 u8 dctn[0x18]; 8169 8170 u8 ece[0x20]; 8171 }; 8172 8173 struct mlx5_ifc_create_dct_in_bits { 8174 u8 opcode[0x10]; 8175 u8 uid[0x10]; 8176 8177 u8 reserved_at_20[0x10]; 8178 u8 op_mod[0x10]; 8179 8180 u8 reserved_at_40[0x40]; 8181 8182 struct mlx5_ifc_dctc_bits dct_context_entry; 8183 8184 u8 reserved_at_280[0x180]; 8185 }; 8186 8187 struct mlx5_ifc_create_cq_out_bits { 8188 u8 status[0x8]; 8189 u8 reserved_at_8[0x18]; 8190 8191 u8 syndrome[0x20]; 8192 8193 u8 reserved_at_40[0x8]; 8194 u8 cqn[0x18]; 8195 8196 u8 reserved_at_60[0x20]; 8197 }; 8198 8199 struct mlx5_ifc_create_cq_in_bits { 8200 u8 opcode[0x10]; 8201 u8 uid[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 reserved_at_40[0x40]; 8207 8208 struct mlx5_ifc_cqc_bits cq_context; 8209 8210 u8 reserved_at_280[0x60]; 8211 8212 u8 cq_umem_valid[0x1]; 8213 u8 reserved_at_2e1[0x59f]; 8214 8215 u8 pas[][0x40]; 8216 }; 8217 8218 struct mlx5_ifc_config_int_moderation_out_bits { 8219 u8 status[0x8]; 8220 u8 reserved_at_8[0x18]; 8221 8222 u8 syndrome[0x20]; 8223 8224 u8 reserved_at_40[0x4]; 8225 u8 min_delay[0xc]; 8226 u8 int_vector[0x10]; 8227 8228 u8 reserved_at_60[0x20]; 8229 }; 8230 8231 enum { 8232 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8233 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8234 }; 8235 8236 struct mlx5_ifc_config_int_moderation_in_bits { 8237 u8 opcode[0x10]; 8238 u8 reserved_at_10[0x10]; 8239 8240 u8 reserved_at_20[0x10]; 8241 u8 op_mod[0x10]; 8242 8243 u8 reserved_at_40[0x4]; 8244 u8 min_delay[0xc]; 8245 u8 int_vector[0x10]; 8246 8247 u8 reserved_at_60[0x20]; 8248 }; 8249 8250 struct mlx5_ifc_attach_to_mcg_out_bits { 8251 u8 status[0x8]; 8252 u8 reserved_at_8[0x18]; 8253 8254 u8 syndrome[0x20]; 8255 8256 u8 reserved_at_40[0x40]; 8257 }; 8258 8259 struct mlx5_ifc_attach_to_mcg_in_bits { 8260 u8 opcode[0x10]; 8261 u8 uid[0x10]; 8262 8263 u8 reserved_at_20[0x10]; 8264 u8 op_mod[0x10]; 8265 8266 u8 reserved_at_40[0x8]; 8267 u8 qpn[0x18]; 8268 8269 u8 reserved_at_60[0x20]; 8270 8271 u8 multicast_gid[16][0x8]; 8272 }; 8273 8274 struct mlx5_ifc_arm_xrq_out_bits { 8275 u8 status[0x8]; 8276 u8 reserved_at_8[0x18]; 8277 8278 u8 syndrome[0x20]; 8279 8280 u8 reserved_at_40[0x40]; 8281 }; 8282 8283 struct mlx5_ifc_arm_xrq_in_bits { 8284 u8 opcode[0x10]; 8285 u8 reserved_at_10[0x10]; 8286 8287 u8 reserved_at_20[0x10]; 8288 u8 op_mod[0x10]; 8289 8290 u8 reserved_at_40[0x8]; 8291 u8 xrqn[0x18]; 8292 8293 u8 reserved_at_60[0x10]; 8294 u8 lwm[0x10]; 8295 }; 8296 8297 struct mlx5_ifc_arm_xrc_srq_out_bits { 8298 u8 status[0x8]; 8299 u8 reserved_at_8[0x18]; 8300 8301 u8 syndrome[0x20]; 8302 8303 u8 reserved_at_40[0x40]; 8304 }; 8305 8306 enum { 8307 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8308 }; 8309 8310 struct mlx5_ifc_arm_xrc_srq_in_bits { 8311 u8 opcode[0x10]; 8312 u8 uid[0x10]; 8313 8314 u8 reserved_at_20[0x10]; 8315 u8 op_mod[0x10]; 8316 8317 u8 reserved_at_40[0x8]; 8318 u8 xrc_srqn[0x18]; 8319 8320 u8 reserved_at_60[0x10]; 8321 u8 lwm[0x10]; 8322 }; 8323 8324 struct mlx5_ifc_arm_rq_out_bits { 8325 u8 status[0x8]; 8326 u8 reserved_at_8[0x18]; 8327 8328 u8 syndrome[0x20]; 8329 8330 u8 reserved_at_40[0x40]; 8331 }; 8332 8333 enum { 8334 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8335 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8336 }; 8337 8338 struct mlx5_ifc_arm_rq_in_bits { 8339 u8 opcode[0x10]; 8340 u8 uid[0x10]; 8341 8342 u8 reserved_at_20[0x10]; 8343 u8 op_mod[0x10]; 8344 8345 u8 reserved_at_40[0x8]; 8346 u8 srq_number[0x18]; 8347 8348 u8 reserved_at_60[0x10]; 8349 u8 lwm[0x10]; 8350 }; 8351 8352 struct mlx5_ifc_arm_dct_out_bits { 8353 u8 status[0x8]; 8354 u8 reserved_at_8[0x18]; 8355 8356 u8 syndrome[0x20]; 8357 8358 u8 reserved_at_40[0x40]; 8359 }; 8360 8361 struct mlx5_ifc_arm_dct_in_bits { 8362 u8 opcode[0x10]; 8363 u8 reserved_at_10[0x10]; 8364 8365 u8 reserved_at_20[0x10]; 8366 u8 op_mod[0x10]; 8367 8368 u8 reserved_at_40[0x8]; 8369 u8 dct_number[0x18]; 8370 8371 u8 reserved_at_60[0x20]; 8372 }; 8373 8374 struct mlx5_ifc_alloc_xrcd_out_bits { 8375 u8 status[0x8]; 8376 u8 reserved_at_8[0x18]; 8377 8378 u8 syndrome[0x20]; 8379 8380 u8 reserved_at_40[0x8]; 8381 u8 xrcd[0x18]; 8382 8383 u8 reserved_at_60[0x20]; 8384 }; 8385 8386 struct mlx5_ifc_alloc_xrcd_in_bits { 8387 u8 opcode[0x10]; 8388 u8 uid[0x10]; 8389 8390 u8 reserved_at_20[0x10]; 8391 u8 op_mod[0x10]; 8392 8393 u8 reserved_at_40[0x40]; 8394 }; 8395 8396 struct mlx5_ifc_alloc_uar_out_bits { 8397 u8 status[0x8]; 8398 u8 reserved_at_8[0x18]; 8399 8400 u8 syndrome[0x20]; 8401 8402 u8 reserved_at_40[0x8]; 8403 u8 uar[0x18]; 8404 8405 u8 reserved_at_60[0x20]; 8406 }; 8407 8408 struct mlx5_ifc_alloc_uar_in_bits { 8409 u8 opcode[0x10]; 8410 u8 reserved_at_10[0x10]; 8411 8412 u8 reserved_at_20[0x10]; 8413 u8 op_mod[0x10]; 8414 8415 u8 reserved_at_40[0x40]; 8416 }; 8417 8418 struct mlx5_ifc_alloc_transport_domain_out_bits { 8419 u8 status[0x8]; 8420 u8 reserved_at_8[0x18]; 8421 8422 u8 syndrome[0x20]; 8423 8424 u8 reserved_at_40[0x8]; 8425 u8 transport_domain[0x18]; 8426 8427 u8 reserved_at_60[0x20]; 8428 }; 8429 8430 struct mlx5_ifc_alloc_transport_domain_in_bits { 8431 u8 opcode[0x10]; 8432 u8 uid[0x10]; 8433 8434 u8 reserved_at_20[0x10]; 8435 u8 op_mod[0x10]; 8436 8437 u8 reserved_at_40[0x40]; 8438 }; 8439 8440 struct mlx5_ifc_alloc_q_counter_out_bits { 8441 u8 status[0x8]; 8442 u8 reserved_at_8[0x18]; 8443 8444 u8 syndrome[0x20]; 8445 8446 u8 reserved_at_40[0x18]; 8447 u8 counter_set_id[0x8]; 8448 8449 u8 reserved_at_60[0x20]; 8450 }; 8451 8452 struct mlx5_ifc_alloc_q_counter_in_bits { 8453 u8 opcode[0x10]; 8454 u8 uid[0x10]; 8455 8456 u8 reserved_at_20[0x10]; 8457 u8 op_mod[0x10]; 8458 8459 u8 reserved_at_40[0x40]; 8460 }; 8461 8462 struct mlx5_ifc_alloc_pd_out_bits { 8463 u8 status[0x8]; 8464 u8 reserved_at_8[0x18]; 8465 8466 u8 syndrome[0x20]; 8467 8468 u8 reserved_at_40[0x8]; 8469 u8 pd[0x18]; 8470 8471 u8 reserved_at_60[0x20]; 8472 }; 8473 8474 struct mlx5_ifc_alloc_pd_in_bits { 8475 u8 opcode[0x10]; 8476 u8 uid[0x10]; 8477 8478 u8 reserved_at_20[0x10]; 8479 u8 op_mod[0x10]; 8480 8481 u8 reserved_at_40[0x40]; 8482 }; 8483 8484 struct mlx5_ifc_alloc_flow_counter_out_bits { 8485 u8 status[0x8]; 8486 u8 reserved_at_8[0x18]; 8487 8488 u8 syndrome[0x20]; 8489 8490 u8 flow_counter_id[0x20]; 8491 8492 u8 reserved_at_60[0x20]; 8493 }; 8494 8495 struct mlx5_ifc_alloc_flow_counter_in_bits { 8496 u8 opcode[0x10]; 8497 u8 reserved_at_10[0x10]; 8498 8499 u8 reserved_at_20[0x10]; 8500 u8 op_mod[0x10]; 8501 8502 u8 reserved_at_40[0x38]; 8503 u8 flow_counter_bulk[0x8]; 8504 }; 8505 8506 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8507 u8 status[0x8]; 8508 u8 reserved_at_8[0x18]; 8509 8510 u8 syndrome[0x20]; 8511 8512 u8 reserved_at_40[0x40]; 8513 }; 8514 8515 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8516 u8 opcode[0x10]; 8517 u8 reserved_at_10[0x10]; 8518 8519 u8 reserved_at_20[0x10]; 8520 u8 op_mod[0x10]; 8521 8522 u8 reserved_at_40[0x20]; 8523 8524 u8 reserved_at_60[0x10]; 8525 u8 vxlan_udp_port[0x10]; 8526 }; 8527 8528 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8529 u8 status[0x8]; 8530 u8 reserved_at_8[0x18]; 8531 8532 u8 syndrome[0x20]; 8533 8534 u8 reserved_at_40[0x40]; 8535 }; 8536 8537 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8538 u8 rate_limit[0x20]; 8539 8540 u8 burst_upper_bound[0x20]; 8541 8542 u8 reserved_at_40[0x10]; 8543 u8 typical_packet_size[0x10]; 8544 8545 u8 reserved_at_60[0x120]; 8546 }; 8547 8548 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8549 u8 opcode[0x10]; 8550 u8 uid[0x10]; 8551 8552 u8 reserved_at_20[0x10]; 8553 u8 op_mod[0x10]; 8554 8555 u8 reserved_at_40[0x10]; 8556 u8 rate_limit_index[0x10]; 8557 8558 u8 reserved_at_60[0x20]; 8559 8560 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8561 }; 8562 8563 struct mlx5_ifc_access_register_out_bits { 8564 u8 status[0x8]; 8565 u8 reserved_at_8[0x18]; 8566 8567 u8 syndrome[0x20]; 8568 8569 u8 reserved_at_40[0x40]; 8570 8571 u8 register_data[][0x20]; 8572 }; 8573 8574 enum { 8575 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8576 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8577 }; 8578 8579 struct mlx5_ifc_access_register_in_bits { 8580 u8 opcode[0x10]; 8581 u8 reserved_at_10[0x10]; 8582 8583 u8 reserved_at_20[0x10]; 8584 u8 op_mod[0x10]; 8585 8586 u8 reserved_at_40[0x10]; 8587 u8 register_id[0x10]; 8588 8589 u8 argument[0x20]; 8590 8591 u8 register_data[][0x20]; 8592 }; 8593 8594 struct mlx5_ifc_sltp_reg_bits { 8595 u8 status[0x4]; 8596 u8 version[0x4]; 8597 u8 local_port[0x8]; 8598 u8 pnat[0x2]; 8599 u8 reserved_at_12[0x2]; 8600 u8 lane[0x4]; 8601 u8 reserved_at_18[0x8]; 8602 8603 u8 reserved_at_20[0x20]; 8604 8605 u8 reserved_at_40[0x7]; 8606 u8 polarity[0x1]; 8607 u8 ob_tap0[0x8]; 8608 u8 ob_tap1[0x8]; 8609 u8 ob_tap2[0x8]; 8610 8611 u8 reserved_at_60[0xc]; 8612 u8 ob_preemp_mode[0x4]; 8613 u8 ob_reg[0x8]; 8614 u8 ob_bias[0x8]; 8615 8616 u8 reserved_at_80[0x20]; 8617 }; 8618 8619 struct mlx5_ifc_slrg_reg_bits { 8620 u8 status[0x4]; 8621 u8 version[0x4]; 8622 u8 local_port[0x8]; 8623 u8 pnat[0x2]; 8624 u8 reserved_at_12[0x2]; 8625 u8 lane[0x4]; 8626 u8 reserved_at_18[0x8]; 8627 8628 u8 time_to_link_up[0x10]; 8629 u8 reserved_at_30[0xc]; 8630 u8 grade_lane_speed[0x4]; 8631 8632 u8 grade_version[0x8]; 8633 u8 grade[0x18]; 8634 8635 u8 reserved_at_60[0x4]; 8636 u8 height_grade_type[0x4]; 8637 u8 height_grade[0x18]; 8638 8639 u8 height_dz[0x10]; 8640 u8 height_dv[0x10]; 8641 8642 u8 reserved_at_a0[0x10]; 8643 u8 height_sigma[0x10]; 8644 8645 u8 reserved_at_c0[0x20]; 8646 8647 u8 reserved_at_e0[0x4]; 8648 u8 phase_grade_type[0x4]; 8649 u8 phase_grade[0x18]; 8650 8651 u8 reserved_at_100[0x8]; 8652 u8 phase_eo_pos[0x8]; 8653 u8 reserved_at_110[0x8]; 8654 u8 phase_eo_neg[0x8]; 8655 8656 u8 ffe_set_tested[0x10]; 8657 u8 test_errors_per_lane[0x10]; 8658 }; 8659 8660 struct mlx5_ifc_pvlc_reg_bits { 8661 u8 reserved_at_0[0x8]; 8662 u8 local_port[0x8]; 8663 u8 reserved_at_10[0x10]; 8664 8665 u8 reserved_at_20[0x1c]; 8666 u8 vl_hw_cap[0x4]; 8667 8668 u8 reserved_at_40[0x1c]; 8669 u8 vl_admin[0x4]; 8670 8671 u8 reserved_at_60[0x1c]; 8672 u8 vl_operational[0x4]; 8673 }; 8674 8675 struct mlx5_ifc_pude_reg_bits { 8676 u8 swid[0x8]; 8677 u8 local_port[0x8]; 8678 u8 reserved_at_10[0x4]; 8679 u8 admin_status[0x4]; 8680 u8 reserved_at_18[0x4]; 8681 u8 oper_status[0x4]; 8682 8683 u8 reserved_at_20[0x60]; 8684 }; 8685 8686 struct mlx5_ifc_ptys_reg_bits { 8687 u8 reserved_at_0[0x1]; 8688 u8 an_disable_admin[0x1]; 8689 u8 an_disable_cap[0x1]; 8690 u8 reserved_at_3[0x5]; 8691 u8 local_port[0x8]; 8692 u8 reserved_at_10[0xd]; 8693 u8 proto_mask[0x3]; 8694 8695 u8 an_status[0x4]; 8696 u8 reserved_at_24[0xc]; 8697 u8 data_rate_oper[0x10]; 8698 8699 u8 ext_eth_proto_capability[0x20]; 8700 8701 u8 eth_proto_capability[0x20]; 8702 8703 u8 ib_link_width_capability[0x10]; 8704 u8 ib_proto_capability[0x10]; 8705 8706 u8 ext_eth_proto_admin[0x20]; 8707 8708 u8 eth_proto_admin[0x20]; 8709 8710 u8 ib_link_width_admin[0x10]; 8711 u8 ib_proto_admin[0x10]; 8712 8713 u8 ext_eth_proto_oper[0x20]; 8714 8715 u8 eth_proto_oper[0x20]; 8716 8717 u8 ib_link_width_oper[0x10]; 8718 u8 ib_proto_oper[0x10]; 8719 8720 u8 reserved_at_160[0x1c]; 8721 u8 connector_type[0x4]; 8722 8723 u8 eth_proto_lp_advertise[0x20]; 8724 8725 u8 reserved_at_1a0[0x60]; 8726 }; 8727 8728 struct mlx5_ifc_mlcr_reg_bits { 8729 u8 reserved_at_0[0x8]; 8730 u8 local_port[0x8]; 8731 u8 reserved_at_10[0x20]; 8732 8733 u8 beacon_duration[0x10]; 8734 u8 reserved_at_40[0x10]; 8735 8736 u8 beacon_remain[0x10]; 8737 }; 8738 8739 struct mlx5_ifc_ptas_reg_bits { 8740 u8 reserved_at_0[0x20]; 8741 8742 u8 algorithm_options[0x10]; 8743 u8 reserved_at_30[0x4]; 8744 u8 repetitions_mode[0x4]; 8745 u8 num_of_repetitions[0x8]; 8746 8747 u8 grade_version[0x8]; 8748 u8 height_grade_type[0x4]; 8749 u8 phase_grade_type[0x4]; 8750 u8 height_grade_weight[0x8]; 8751 u8 phase_grade_weight[0x8]; 8752 8753 u8 gisim_measure_bits[0x10]; 8754 u8 adaptive_tap_measure_bits[0x10]; 8755 8756 u8 ber_bath_high_error_threshold[0x10]; 8757 u8 ber_bath_mid_error_threshold[0x10]; 8758 8759 u8 ber_bath_low_error_threshold[0x10]; 8760 u8 one_ratio_high_threshold[0x10]; 8761 8762 u8 one_ratio_high_mid_threshold[0x10]; 8763 u8 one_ratio_low_mid_threshold[0x10]; 8764 8765 u8 one_ratio_low_threshold[0x10]; 8766 u8 ndeo_error_threshold[0x10]; 8767 8768 u8 mixer_offset_step_size[0x10]; 8769 u8 reserved_at_110[0x8]; 8770 u8 mix90_phase_for_voltage_bath[0x8]; 8771 8772 u8 mixer_offset_start[0x10]; 8773 u8 mixer_offset_end[0x10]; 8774 8775 u8 reserved_at_140[0x15]; 8776 u8 ber_test_time[0xb]; 8777 }; 8778 8779 struct mlx5_ifc_pspa_reg_bits { 8780 u8 swid[0x8]; 8781 u8 local_port[0x8]; 8782 u8 sub_port[0x8]; 8783 u8 reserved_at_18[0x8]; 8784 8785 u8 reserved_at_20[0x20]; 8786 }; 8787 8788 struct mlx5_ifc_pqdr_reg_bits { 8789 u8 reserved_at_0[0x8]; 8790 u8 local_port[0x8]; 8791 u8 reserved_at_10[0x5]; 8792 u8 prio[0x3]; 8793 u8 reserved_at_18[0x6]; 8794 u8 mode[0x2]; 8795 8796 u8 reserved_at_20[0x20]; 8797 8798 u8 reserved_at_40[0x10]; 8799 u8 min_threshold[0x10]; 8800 8801 u8 reserved_at_60[0x10]; 8802 u8 max_threshold[0x10]; 8803 8804 u8 reserved_at_80[0x10]; 8805 u8 mark_probability_denominator[0x10]; 8806 8807 u8 reserved_at_a0[0x60]; 8808 }; 8809 8810 struct mlx5_ifc_ppsc_reg_bits { 8811 u8 reserved_at_0[0x8]; 8812 u8 local_port[0x8]; 8813 u8 reserved_at_10[0x10]; 8814 8815 u8 reserved_at_20[0x60]; 8816 8817 u8 reserved_at_80[0x1c]; 8818 u8 wrps_admin[0x4]; 8819 8820 u8 reserved_at_a0[0x1c]; 8821 u8 wrps_status[0x4]; 8822 8823 u8 reserved_at_c0[0x8]; 8824 u8 up_threshold[0x8]; 8825 u8 reserved_at_d0[0x8]; 8826 u8 down_threshold[0x8]; 8827 8828 u8 reserved_at_e0[0x20]; 8829 8830 u8 reserved_at_100[0x1c]; 8831 u8 srps_admin[0x4]; 8832 8833 u8 reserved_at_120[0x1c]; 8834 u8 srps_status[0x4]; 8835 8836 u8 reserved_at_140[0x40]; 8837 }; 8838 8839 struct mlx5_ifc_pplr_reg_bits { 8840 u8 reserved_at_0[0x8]; 8841 u8 local_port[0x8]; 8842 u8 reserved_at_10[0x10]; 8843 8844 u8 reserved_at_20[0x8]; 8845 u8 lb_cap[0x8]; 8846 u8 reserved_at_30[0x8]; 8847 u8 lb_en[0x8]; 8848 }; 8849 8850 struct mlx5_ifc_pplm_reg_bits { 8851 u8 reserved_at_0[0x8]; 8852 u8 local_port[0x8]; 8853 u8 reserved_at_10[0x10]; 8854 8855 u8 reserved_at_20[0x20]; 8856 8857 u8 port_profile_mode[0x8]; 8858 u8 static_port_profile[0x8]; 8859 u8 active_port_profile[0x8]; 8860 u8 reserved_at_58[0x8]; 8861 8862 u8 retransmission_active[0x8]; 8863 u8 fec_mode_active[0x18]; 8864 8865 u8 rs_fec_correction_bypass_cap[0x4]; 8866 u8 reserved_at_84[0x8]; 8867 u8 fec_override_cap_56g[0x4]; 8868 u8 fec_override_cap_100g[0x4]; 8869 u8 fec_override_cap_50g[0x4]; 8870 u8 fec_override_cap_25g[0x4]; 8871 u8 fec_override_cap_10g_40g[0x4]; 8872 8873 u8 rs_fec_correction_bypass_admin[0x4]; 8874 u8 reserved_at_a4[0x8]; 8875 u8 fec_override_admin_56g[0x4]; 8876 u8 fec_override_admin_100g[0x4]; 8877 u8 fec_override_admin_50g[0x4]; 8878 u8 fec_override_admin_25g[0x4]; 8879 u8 fec_override_admin_10g_40g[0x4]; 8880 8881 u8 fec_override_cap_400g_8x[0x10]; 8882 u8 fec_override_cap_200g_4x[0x10]; 8883 8884 u8 fec_override_cap_100g_2x[0x10]; 8885 u8 fec_override_cap_50g_1x[0x10]; 8886 8887 u8 fec_override_admin_400g_8x[0x10]; 8888 u8 fec_override_admin_200g_4x[0x10]; 8889 8890 u8 fec_override_admin_100g_2x[0x10]; 8891 u8 fec_override_admin_50g_1x[0x10]; 8892 8893 u8 reserved_at_140[0x140]; 8894 }; 8895 8896 struct mlx5_ifc_ppcnt_reg_bits { 8897 u8 swid[0x8]; 8898 u8 local_port[0x8]; 8899 u8 pnat[0x2]; 8900 u8 reserved_at_12[0x8]; 8901 u8 grp[0x6]; 8902 8903 u8 clr[0x1]; 8904 u8 reserved_at_21[0x1c]; 8905 u8 prio_tc[0x3]; 8906 8907 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8908 }; 8909 8910 struct mlx5_ifc_mpein_reg_bits { 8911 u8 reserved_at_0[0x2]; 8912 u8 depth[0x6]; 8913 u8 pcie_index[0x8]; 8914 u8 node[0x8]; 8915 u8 reserved_at_18[0x8]; 8916 8917 u8 capability_mask[0x20]; 8918 8919 u8 reserved_at_40[0x8]; 8920 u8 link_width_enabled[0x8]; 8921 u8 link_speed_enabled[0x10]; 8922 8923 u8 lane0_physical_position[0x8]; 8924 u8 link_width_active[0x8]; 8925 u8 link_speed_active[0x10]; 8926 8927 u8 num_of_pfs[0x10]; 8928 u8 num_of_vfs[0x10]; 8929 8930 u8 bdf0[0x10]; 8931 u8 reserved_at_b0[0x10]; 8932 8933 u8 max_read_request_size[0x4]; 8934 u8 max_payload_size[0x4]; 8935 u8 reserved_at_c8[0x5]; 8936 u8 pwr_status[0x3]; 8937 u8 port_type[0x4]; 8938 u8 reserved_at_d4[0xb]; 8939 u8 lane_reversal[0x1]; 8940 8941 u8 reserved_at_e0[0x14]; 8942 u8 pci_power[0xc]; 8943 8944 u8 reserved_at_100[0x20]; 8945 8946 u8 device_status[0x10]; 8947 u8 port_state[0x8]; 8948 u8 reserved_at_138[0x8]; 8949 8950 u8 reserved_at_140[0x10]; 8951 u8 receiver_detect_result[0x10]; 8952 8953 u8 reserved_at_160[0x20]; 8954 }; 8955 8956 struct mlx5_ifc_mpcnt_reg_bits { 8957 u8 reserved_at_0[0x8]; 8958 u8 pcie_index[0x8]; 8959 u8 reserved_at_10[0xa]; 8960 u8 grp[0x6]; 8961 8962 u8 clr[0x1]; 8963 u8 reserved_at_21[0x1f]; 8964 8965 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8966 }; 8967 8968 struct mlx5_ifc_ppad_reg_bits { 8969 u8 reserved_at_0[0x3]; 8970 u8 single_mac[0x1]; 8971 u8 reserved_at_4[0x4]; 8972 u8 local_port[0x8]; 8973 u8 mac_47_32[0x10]; 8974 8975 u8 mac_31_0[0x20]; 8976 8977 u8 reserved_at_40[0x40]; 8978 }; 8979 8980 struct mlx5_ifc_pmtu_reg_bits { 8981 u8 reserved_at_0[0x8]; 8982 u8 local_port[0x8]; 8983 u8 reserved_at_10[0x10]; 8984 8985 u8 max_mtu[0x10]; 8986 u8 reserved_at_30[0x10]; 8987 8988 u8 admin_mtu[0x10]; 8989 u8 reserved_at_50[0x10]; 8990 8991 u8 oper_mtu[0x10]; 8992 u8 reserved_at_70[0x10]; 8993 }; 8994 8995 struct mlx5_ifc_pmpr_reg_bits { 8996 u8 reserved_at_0[0x8]; 8997 u8 module[0x8]; 8998 u8 reserved_at_10[0x10]; 8999 9000 u8 reserved_at_20[0x18]; 9001 u8 attenuation_5g[0x8]; 9002 9003 u8 reserved_at_40[0x18]; 9004 u8 attenuation_7g[0x8]; 9005 9006 u8 reserved_at_60[0x18]; 9007 u8 attenuation_12g[0x8]; 9008 }; 9009 9010 struct mlx5_ifc_pmpe_reg_bits { 9011 u8 reserved_at_0[0x8]; 9012 u8 module[0x8]; 9013 u8 reserved_at_10[0xc]; 9014 u8 module_status[0x4]; 9015 9016 u8 reserved_at_20[0x60]; 9017 }; 9018 9019 struct mlx5_ifc_pmpc_reg_bits { 9020 u8 module_state_updated[32][0x8]; 9021 }; 9022 9023 struct mlx5_ifc_pmlpn_reg_bits { 9024 u8 reserved_at_0[0x4]; 9025 u8 mlpn_status[0x4]; 9026 u8 local_port[0x8]; 9027 u8 reserved_at_10[0x10]; 9028 9029 u8 e[0x1]; 9030 u8 reserved_at_21[0x1f]; 9031 }; 9032 9033 struct mlx5_ifc_pmlp_reg_bits { 9034 u8 rxtx[0x1]; 9035 u8 reserved_at_1[0x7]; 9036 u8 local_port[0x8]; 9037 u8 reserved_at_10[0x8]; 9038 u8 width[0x8]; 9039 9040 u8 lane0_module_mapping[0x20]; 9041 9042 u8 lane1_module_mapping[0x20]; 9043 9044 u8 lane2_module_mapping[0x20]; 9045 9046 u8 lane3_module_mapping[0x20]; 9047 9048 u8 reserved_at_a0[0x160]; 9049 }; 9050 9051 struct mlx5_ifc_pmaos_reg_bits { 9052 u8 reserved_at_0[0x8]; 9053 u8 module[0x8]; 9054 u8 reserved_at_10[0x4]; 9055 u8 admin_status[0x4]; 9056 u8 reserved_at_18[0x4]; 9057 u8 oper_status[0x4]; 9058 9059 u8 ase[0x1]; 9060 u8 ee[0x1]; 9061 u8 reserved_at_22[0x1c]; 9062 u8 e[0x2]; 9063 9064 u8 reserved_at_40[0x40]; 9065 }; 9066 9067 struct mlx5_ifc_plpc_reg_bits { 9068 u8 reserved_at_0[0x4]; 9069 u8 profile_id[0xc]; 9070 u8 reserved_at_10[0x4]; 9071 u8 proto_mask[0x4]; 9072 u8 reserved_at_18[0x8]; 9073 9074 u8 reserved_at_20[0x10]; 9075 u8 lane_speed[0x10]; 9076 9077 u8 reserved_at_40[0x17]; 9078 u8 lpbf[0x1]; 9079 u8 fec_mode_policy[0x8]; 9080 9081 u8 retransmission_capability[0x8]; 9082 u8 fec_mode_capability[0x18]; 9083 9084 u8 retransmission_support_admin[0x8]; 9085 u8 fec_mode_support_admin[0x18]; 9086 9087 u8 retransmission_request_admin[0x8]; 9088 u8 fec_mode_request_admin[0x18]; 9089 9090 u8 reserved_at_c0[0x80]; 9091 }; 9092 9093 struct mlx5_ifc_plib_reg_bits { 9094 u8 reserved_at_0[0x8]; 9095 u8 local_port[0x8]; 9096 u8 reserved_at_10[0x8]; 9097 u8 ib_port[0x8]; 9098 9099 u8 reserved_at_20[0x60]; 9100 }; 9101 9102 struct mlx5_ifc_plbf_reg_bits { 9103 u8 reserved_at_0[0x8]; 9104 u8 local_port[0x8]; 9105 u8 reserved_at_10[0xd]; 9106 u8 lbf_mode[0x3]; 9107 9108 u8 reserved_at_20[0x20]; 9109 }; 9110 9111 struct mlx5_ifc_pipg_reg_bits { 9112 u8 reserved_at_0[0x8]; 9113 u8 local_port[0x8]; 9114 u8 reserved_at_10[0x10]; 9115 9116 u8 dic[0x1]; 9117 u8 reserved_at_21[0x19]; 9118 u8 ipg[0x4]; 9119 u8 reserved_at_3e[0x2]; 9120 }; 9121 9122 struct mlx5_ifc_pifr_reg_bits { 9123 u8 reserved_at_0[0x8]; 9124 u8 local_port[0x8]; 9125 u8 reserved_at_10[0x10]; 9126 9127 u8 reserved_at_20[0xe0]; 9128 9129 u8 port_filter[8][0x20]; 9130 9131 u8 port_filter_update_en[8][0x20]; 9132 }; 9133 9134 struct mlx5_ifc_pfcc_reg_bits { 9135 u8 reserved_at_0[0x8]; 9136 u8 local_port[0x8]; 9137 u8 reserved_at_10[0xb]; 9138 u8 ppan_mask_n[0x1]; 9139 u8 minor_stall_mask[0x1]; 9140 u8 critical_stall_mask[0x1]; 9141 u8 reserved_at_1e[0x2]; 9142 9143 u8 ppan[0x4]; 9144 u8 reserved_at_24[0x4]; 9145 u8 prio_mask_tx[0x8]; 9146 u8 reserved_at_30[0x8]; 9147 u8 prio_mask_rx[0x8]; 9148 9149 u8 pptx[0x1]; 9150 u8 aptx[0x1]; 9151 u8 pptx_mask_n[0x1]; 9152 u8 reserved_at_43[0x5]; 9153 u8 pfctx[0x8]; 9154 u8 reserved_at_50[0x10]; 9155 9156 u8 pprx[0x1]; 9157 u8 aprx[0x1]; 9158 u8 pprx_mask_n[0x1]; 9159 u8 reserved_at_63[0x5]; 9160 u8 pfcrx[0x8]; 9161 u8 reserved_at_70[0x10]; 9162 9163 u8 device_stall_minor_watermark[0x10]; 9164 u8 device_stall_critical_watermark[0x10]; 9165 9166 u8 reserved_at_a0[0x60]; 9167 }; 9168 9169 struct mlx5_ifc_pelc_reg_bits { 9170 u8 op[0x4]; 9171 u8 reserved_at_4[0x4]; 9172 u8 local_port[0x8]; 9173 u8 reserved_at_10[0x10]; 9174 9175 u8 op_admin[0x8]; 9176 u8 op_capability[0x8]; 9177 u8 op_request[0x8]; 9178 u8 op_active[0x8]; 9179 9180 u8 admin[0x40]; 9181 9182 u8 capability[0x40]; 9183 9184 u8 request[0x40]; 9185 9186 u8 active[0x40]; 9187 9188 u8 reserved_at_140[0x80]; 9189 }; 9190 9191 struct mlx5_ifc_peir_reg_bits { 9192 u8 reserved_at_0[0x8]; 9193 u8 local_port[0x8]; 9194 u8 reserved_at_10[0x10]; 9195 9196 u8 reserved_at_20[0xc]; 9197 u8 error_count[0x4]; 9198 u8 reserved_at_30[0x10]; 9199 9200 u8 reserved_at_40[0xc]; 9201 u8 lane[0x4]; 9202 u8 reserved_at_50[0x8]; 9203 u8 error_type[0x8]; 9204 }; 9205 9206 struct mlx5_ifc_mpegc_reg_bits { 9207 u8 reserved_at_0[0x30]; 9208 u8 field_select[0x10]; 9209 9210 u8 tx_overflow_sense[0x1]; 9211 u8 mark_cqe[0x1]; 9212 u8 mark_cnp[0x1]; 9213 u8 reserved_at_43[0x1b]; 9214 u8 tx_lossy_overflow_oper[0x2]; 9215 9216 u8 reserved_at_60[0x100]; 9217 }; 9218 9219 enum { 9220 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9221 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9222 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9223 }; 9224 9225 struct mlx5_ifc_mtutc_reg_bits { 9226 u8 reserved_at_0[0x1c]; 9227 u8 operation[0x4]; 9228 9229 u8 freq_adjustment[0x20]; 9230 9231 u8 reserved_at_40[0x40]; 9232 9233 u8 utc_sec[0x20]; 9234 9235 u8 reserved_at_a0[0x2]; 9236 u8 utc_nsec[0x1e]; 9237 9238 u8 time_adjustment[0x20]; 9239 }; 9240 9241 struct mlx5_ifc_pcam_enhanced_features_bits { 9242 u8 reserved_at_0[0x68]; 9243 u8 fec_50G_per_lane_in_pplm[0x1]; 9244 u8 reserved_at_69[0x4]; 9245 u8 rx_icrc_encapsulated_counter[0x1]; 9246 u8 reserved_at_6e[0x4]; 9247 u8 ptys_extended_ethernet[0x1]; 9248 u8 reserved_at_73[0x3]; 9249 u8 pfcc_mask[0x1]; 9250 u8 reserved_at_77[0x3]; 9251 u8 per_lane_error_counters[0x1]; 9252 u8 rx_buffer_fullness_counters[0x1]; 9253 u8 ptys_connector_type[0x1]; 9254 u8 reserved_at_7d[0x1]; 9255 u8 ppcnt_discard_group[0x1]; 9256 u8 ppcnt_statistical_group[0x1]; 9257 }; 9258 9259 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9260 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9261 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9262 9263 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9264 u8 pplm[0x1]; 9265 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9266 9267 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9268 u8 pbmc[0x1]; 9269 u8 pptb[0x1]; 9270 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9271 u8 ppcnt[0x1]; 9272 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9273 }; 9274 9275 struct mlx5_ifc_pcam_reg_bits { 9276 u8 reserved_at_0[0x8]; 9277 u8 feature_group[0x8]; 9278 u8 reserved_at_10[0x8]; 9279 u8 access_reg_group[0x8]; 9280 9281 u8 reserved_at_20[0x20]; 9282 9283 union { 9284 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9285 u8 reserved_at_0[0x80]; 9286 } port_access_reg_cap_mask; 9287 9288 u8 reserved_at_c0[0x80]; 9289 9290 union { 9291 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9292 u8 reserved_at_0[0x80]; 9293 } feature_cap_mask; 9294 9295 u8 reserved_at_1c0[0xc0]; 9296 }; 9297 9298 struct mlx5_ifc_mcam_enhanced_features_bits { 9299 u8 reserved_at_0[0x6b]; 9300 u8 ptpcyc2realtime_modify[0x1]; 9301 u8 reserved_at_6c[0x2]; 9302 u8 pci_status_and_power[0x1]; 9303 u8 reserved_at_6f[0x5]; 9304 u8 mark_tx_action_cnp[0x1]; 9305 u8 mark_tx_action_cqe[0x1]; 9306 u8 dynamic_tx_overflow[0x1]; 9307 u8 reserved_at_77[0x4]; 9308 u8 pcie_outbound_stalled[0x1]; 9309 u8 tx_overflow_buffer_pkt[0x1]; 9310 u8 mtpps_enh_out_per_adj[0x1]; 9311 u8 mtpps_fs[0x1]; 9312 u8 pcie_performance_group[0x1]; 9313 }; 9314 9315 struct mlx5_ifc_mcam_access_reg_bits { 9316 u8 reserved_at_0[0x1c]; 9317 u8 mcda[0x1]; 9318 u8 mcc[0x1]; 9319 u8 mcqi[0x1]; 9320 u8 mcqs[0x1]; 9321 9322 u8 regs_95_to_87[0x9]; 9323 u8 mpegc[0x1]; 9324 u8 mtutc[0x1]; 9325 u8 regs_84_to_68[0x11]; 9326 u8 tracer_registers[0x4]; 9327 9328 u8 regs_63_to_32[0x20]; 9329 u8 regs_31_to_0[0x20]; 9330 }; 9331 9332 struct mlx5_ifc_mcam_access_reg_bits1 { 9333 u8 regs_127_to_96[0x20]; 9334 9335 u8 regs_95_to_64[0x20]; 9336 9337 u8 regs_63_to_32[0x20]; 9338 9339 u8 regs_31_to_0[0x20]; 9340 }; 9341 9342 struct mlx5_ifc_mcam_access_reg_bits2 { 9343 u8 regs_127_to_99[0x1d]; 9344 u8 mirc[0x1]; 9345 u8 regs_97_to_96[0x2]; 9346 9347 u8 regs_95_to_64[0x20]; 9348 9349 u8 regs_63_to_32[0x20]; 9350 9351 u8 regs_31_to_0[0x20]; 9352 }; 9353 9354 struct mlx5_ifc_mcam_reg_bits { 9355 u8 reserved_at_0[0x8]; 9356 u8 feature_group[0x8]; 9357 u8 reserved_at_10[0x8]; 9358 u8 access_reg_group[0x8]; 9359 9360 u8 reserved_at_20[0x20]; 9361 9362 union { 9363 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9364 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9365 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9366 u8 reserved_at_0[0x80]; 9367 } mng_access_reg_cap_mask; 9368 9369 u8 reserved_at_c0[0x80]; 9370 9371 union { 9372 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9373 u8 reserved_at_0[0x80]; 9374 } mng_feature_cap_mask; 9375 9376 u8 reserved_at_1c0[0x80]; 9377 }; 9378 9379 struct mlx5_ifc_qcam_access_reg_cap_mask { 9380 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9381 u8 qpdpm[0x1]; 9382 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9383 u8 qdpm[0x1]; 9384 u8 qpts[0x1]; 9385 u8 qcap[0x1]; 9386 u8 qcam_access_reg_cap_mask_0[0x1]; 9387 }; 9388 9389 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9390 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9391 u8 qpts_trust_both[0x1]; 9392 }; 9393 9394 struct mlx5_ifc_qcam_reg_bits { 9395 u8 reserved_at_0[0x8]; 9396 u8 feature_group[0x8]; 9397 u8 reserved_at_10[0x8]; 9398 u8 access_reg_group[0x8]; 9399 u8 reserved_at_20[0x20]; 9400 9401 union { 9402 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9403 u8 reserved_at_0[0x80]; 9404 } qos_access_reg_cap_mask; 9405 9406 u8 reserved_at_c0[0x80]; 9407 9408 union { 9409 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9410 u8 reserved_at_0[0x80]; 9411 } qos_feature_cap_mask; 9412 9413 u8 reserved_at_1c0[0x80]; 9414 }; 9415 9416 struct mlx5_ifc_core_dump_reg_bits { 9417 u8 reserved_at_0[0x18]; 9418 u8 core_dump_type[0x8]; 9419 9420 u8 reserved_at_20[0x30]; 9421 u8 vhca_id[0x10]; 9422 9423 u8 reserved_at_60[0x8]; 9424 u8 qpn[0x18]; 9425 u8 reserved_at_80[0x180]; 9426 }; 9427 9428 struct mlx5_ifc_pcap_reg_bits { 9429 u8 reserved_at_0[0x8]; 9430 u8 local_port[0x8]; 9431 u8 reserved_at_10[0x10]; 9432 9433 u8 port_capability_mask[4][0x20]; 9434 }; 9435 9436 struct mlx5_ifc_paos_reg_bits { 9437 u8 swid[0x8]; 9438 u8 local_port[0x8]; 9439 u8 reserved_at_10[0x4]; 9440 u8 admin_status[0x4]; 9441 u8 reserved_at_18[0x4]; 9442 u8 oper_status[0x4]; 9443 9444 u8 ase[0x1]; 9445 u8 ee[0x1]; 9446 u8 reserved_at_22[0x1c]; 9447 u8 e[0x2]; 9448 9449 u8 reserved_at_40[0x40]; 9450 }; 9451 9452 struct mlx5_ifc_pamp_reg_bits { 9453 u8 reserved_at_0[0x8]; 9454 u8 opamp_group[0x8]; 9455 u8 reserved_at_10[0xc]; 9456 u8 opamp_group_type[0x4]; 9457 9458 u8 start_index[0x10]; 9459 u8 reserved_at_30[0x4]; 9460 u8 num_of_indices[0xc]; 9461 9462 u8 index_data[18][0x10]; 9463 }; 9464 9465 struct mlx5_ifc_pcmr_reg_bits { 9466 u8 reserved_at_0[0x8]; 9467 u8 local_port[0x8]; 9468 u8 reserved_at_10[0x10]; 9469 u8 entropy_force_cap[0x1]; 9470 u8 entropy_calc_cap[0x1]; 9471 u8 entropy_gre_calc_cap[0x1]; 9472 u8 reserved_at_23[0x1b]; 9473 u8 fcs_cap[0x1]; 9474 u8 reserved_at_3f[0x1]; 9475 u8 entropy_force[0x1]; 9476 u8 entropy_calc[0x1]; 9477 u8 entropy_gre_calc[0x1]; 9478 u8 reserved_at_43[0x1b]; 9479 u8 fcs_chk[0x1]; 9480 u8 reserved_at_5f[0x1]; 9481 }; 9482 9483 struct mlx5_ifc_lane_2_module_mapping_bits { 9484 u8 reserved_at_0[0x6]; 9485 u8 rx_lane[0x2]; 9486 u8 reserved_at_8[0x6]; 9487 u8 tx_lane[0x2]; 9488 u8 reserved_at_10[0x8]; 9489 u8 module[0x8]; 9490 }; 9491 9492 struct mlx5_ifc_bufferx_reg_bits { 9493 u8 reserved_at_0[0x6]; 9494 u8 lossy[0x1]; 9495 u8 epsb[0x1]; 9496 u8 reserved_at_8[0xc]; 9497 u8 size[0xc]; 9498 9499 u8 xoff_threshold[0x10]; 9500 u8 xon_threshold[0x10]; 9501 }; 9502 9503 struct mlx5_ifc_set_node_in_bits { 9504 u8 node_description[64][0x8]; 9505 }; 9506 9507 struct mlx5_ifc_register_power_settings_bits { 9508 u8 reserved_at_0[0x18]; 9509 u8 power_settings_level[0x8]; 9510 9511 u8 reserved_at_20[0x60]; 9512 }; 9513 9514 struct mlx5_ifc_register_host_endianness_bits { 9515 u8 he[0x1]; 9516 u8 reserved_at_1[0x1f]; 9517 9518 u8 reserved_at_20[0x60]; 9519 }; 9520 9521 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9522 u8 reserved_at_0[0x20]; 9523 9524 u8 mkey[0x20]; 9525 9526 u8 addressh_63_32[0x20]; 9527 9528 u8 addressl_31_0[0x20]; 9529 }; 9530 9531 struct mlx5_ifc_ud_adrs_vector_bits { 9532 u8 dc_key[0x40]; 9533 9534 u8 ext[0x1]; 9535 u8 reserved_at_41[0x7]; 9536 u8 destination_qp_dct[0x18]; 9537 9538 u8 static_rate[0x4]; 9539 u8 sl_eth_prio[0x4]; 9540 u8 fl[0x1]; 9541 u8 mlid[0x7]; 9542 u8 rlid_udp_sport[0x10]; 9543 9544 u8 reserved_at_80[0x20]; 9545 9546 u8 rmac_47_16[0x20]; 9547 9548 u8 rmac_15_0[0x10]; 9549 u8 tclass[0x8]; 9550 u8 hop_limit[0x8]; 9551 9552 u8 reserved_at_e0[0x1]; 9553 u8 grh[0x1]; 9554 u8 reserved_at_e2[0x2]; 9555 u8 src_addr_index[0x8]; 9556 u8 flow_label[0x14]; 9557 9558 u8 rgid_rip[16][0x8]; 9559 }; 9560 9561 struct mlx5_ifc_pages_req_event_bits { 9562 u8 reserved_at_0[0x10]; 9563 u8 function_id[0x10]; 9564 9565 u8 num_pages[0x20]; 9566 9567 u8 reserved_at_40[0xa0]; 9568 }; 9569 9570 struct mlx5_ifc_eqe_bits { 9571 u8 reserved_at_0[0x8]; 9572 u8 event_type[0x8]; 9573 u8 reserved_at_10[0x8]; 9574 u8 event_sub_type[0x8]; 9575 9576 u8 reserved_at_20[0xe0]; 9577 9578 union mlx5_ifc_event_auto_bits event_data; 9579 9580 u8 reserved_at_1e0[0x10]; 9581 u8 signature[0x8]; 9582 u8 reserved_at_1f8[0x7]; 9583 u8 owner[0x1]; 9584 }; 9585 9586 enum { 9587 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9588 }; 9589 9590 struct mlx5_ifc_cmd_queue_entry_bits { 9591 u8 type[0x8]; 9592 u8 reserved_at_8[0x18]; 9593 9594 u8 input_length[0x20]; 9595 9596 u8 input_mailbox_pointer_63_32[0x20]; 9597 9598 u8 input_mailbox_pointer_31_9[0x17]; 9599 u8 reserved_at_77[0x9]; 9600 9601 u8 command_input_inline_data[16][0x8]; 9602 9603 u8 command_output_inline_data[16][0x8]; 9604 9605 u8 output_mailbox_pointer_63_32[0x20]; 9606 9607 u8 output_mailbox_pointer_31_9[0x17]; 9608 u8 reserved_at_1b7[0x9]; 9609 9610 u8 output_length[0x20]; 9611 9612 u8 token[0x8]; 9613 u8 signature[0x8]; 9614 u8 reserved_at_1f0[0x8]; 9615 u8 status[0x7]; 9616 u8 ownership[0x1]; 9617 }; 9618 9619 struct mlx5_ifc_cmd_out_bits { 9620 u8 status[0x8]; 9621 u8 reserved_at_8[0x18]; 9622 9623 u8 syndrome[0x20]; 9624 9625 u8 command_output[0x20]; 9626 }; 9627 9628 struct mlx5_ifc_cmd_in_bits { 9629 u8 opcode[0x10]; 9630 u8 reserved_at_10[0x10]; 9631 9632 u8 reserved_at_20[0x10]; 9633 u8 op_mod[0x10]; 9634 9635 u8 command[][0x20]; 9636 }; 9637 9638 struct mlx5_ifc_cmd_if_box_bits { 9639 u8 mailbox_data[512][0x8]; 9640 9641 u8 reserved_at_1000[0x180]; 9642 9643 u8 next_pointer_63_32[0x20]; 9644 9645 u8 next_pointer_31_10[0x16]; 9646 u8 reserved_at_11b6[0xa]; 9647 9648 u8 block_number[0x20]; 9649 9650 u8 reserved_at_11e0[0x8]; 9651 u8 token[0x8]; 9652 u8 ctrl_signature[0x8]; 9653 u8 signature[0x8]; 9654 }; 9655 9656 struct mlx5_ifc_mtt_bits { 9657 u8 ptag_63_32[0x20]; 9658 9659 u8 ptag_31_8[0x18]; 9660 u8 reserved_at_38[0x6]; 9661 u8 wr_en[0x1]; 9662 u8 rd_en[0x1]; 9663 }; 9664 9665 struct mlx5_ifc_query_wol_rol_out_bits { 9666 u8 status[0x8]; 9667 u8 reserved_at_8[0x18]; 9668 9669 u8 syndrome[0x20]; 9670 9671 u8 reserved_at_40[0x10]; 9672 u8 rol_mode[0x8]; 9673 u8 wol_mode[0x8]; 9674 9675 u8 reserved_at_60[0x20]; 9676 }; 9677 9678 struct mlx5_ifc_query_wol_rol_in_bits { 9679 u8 opcode[0x10]; 9680 u8 reserved_at_10[0x10]; 9681 9682 u8 reserved_at_20[0x10]; 9683 u8 op_mod[0x10]; 9684 9685 u8 reserved_at_40[0x40]; 9686 }; 9687 9688 struct mlx5_ifc_set_wol_rol_out_bits { 9689 u8 status[0x8]; 9690 u8 reserved_at_8[0x18]; 9691 9692 u8 syndrome[0x20]; 9693 9694 u8 reserved_at_40[0x40]; 9695 }; 9696 9697 struct mlx5_ifc_set_wol_rol_in_bits { 9698 u8 opcode[0x10]; 9699 u8 reserved_at_10[0x10]; 9700 9701 u8 reserved_at_20[0x10]; 9702 u8 op_mod[0x10]; 9703 9704 u8 rol_mode_valid[0x1]; 9705 u8 wol_mode_valid[0x1]; 9706 u8 reserved_at_42[0xe]; 9707 u8 rol_mode[0x8]; 9708 u8 wol_mode[0x8]; 9709 9710 u8 reserved_at_60[0x20]; 9711 }; 9712 9713 enum { 9714 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9715 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9716 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9717 }; 9718 9719 enum { 9720 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9721 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9722 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9723 }; 9724 9725 enum { 9726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9731 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9732 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9733 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9734 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9735 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9736 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9737 }; 9738 9739 struct mlx5_ifc_initial_seg_bits { 9740 u8 fw_rev_minor[0x10]; 9741 u8 fw_rev_major[0x10]; 9742 9743 u8 cmd_interface_rev[0x10]; 9744 u8 fw_rev_subminor[0x10]; 9745 9746 u8 reserved_at_40[0x40]; 9747 9748 u8 cmdq_phy_addr_63_32[0x20]; 9749 9750 u8 cmdq_phy_addr_31_12[0x14]; 9751 u8 reserved_at_b4[0x2]; 9752 u8 nic_interface[0x2]; 9753 u8 log_cmdq_size[0x4]; 9754 u8 log_cmdq_stride[0x4]; 9755 9756 u8 command_doorbell_vector[0x20]; 9757 9758 u8 reserved_at_e0[0xf00]; 9759 9760 u8 initializing[0x1]; 9761 u8 reserved_at_fe1[0x4]; 9762 u8 nic_interface_supported[0x3]; 9763 u8 embedded_cpu[0x1]; 9764 u8 reserved_at_fe9[0x17]; 9765 9766 struct mlx5_ifc_health_buffer_bits health_buffer; 9767 9768 u8 no_dram_nic_offset[0x20]; 9769 9770 u8 reserved_at_1220[0x6e40]; 9771 9772 u8 reserved_at_8060[0x1f]; 9773 u8 clear_int[0x1]; 9774 9775 u8 health_syndrome[0x8]; 9776 u8 health_counter[0x18]; 9777 9778 u8 reserved_at_80a0[0x17fc0]; 9779 }; 9780 9781 struct mlx5_ifc_mtpps_reg_bits { 9782 u8 reserved_at_0[0xc]; 9783 u8 cap_number_of_pps_pins[0x4]; 9784 u8 reserved_at_10[0x4]; 9785 u8 cap_max_num_of_pps_in_pins[0x4]; 9786 u8 reserved_at_18[0x4]; 9787 u8 cap_max_num_of_pps_out_pins[0x4]; 9788 9789 u8 reserved_at_20[0x24]; 9790 u8 cap_pin_3_mode[0x4]; 9791 u8 reserved_at_48[0x4]; 9792 u8 cap_pin_2_mode[0x4]; 9793 u8 reserved_at_50[0x4]; 9794 u8 cap_pin_1_mode[0x4]; 9795 u8 reserved_at_58[0x4]; 9796 u8 cap_pin_0_mode[0x4]; 9797 9798 u8 reserved_at_60[0x4]; 9799 u8 cap_pin_7_mode[0x4]; 9800 u8 reserved_at_68[0x4]; 9801 u8 cap_pin_6_mode[0x4]; 9802 u8 reserved_at_70[0x4]; 9803 u8 cap_pin_5_mode[0x4]; 9804 u8 reserved_at_78[0x4]; 9805 u8 cap_pin_4_mode[0x4]; 9806 9807 u8 field_select[0x20]; 9808 u8 reserved_at_a0[0x60]; 9809 9810 u8 enable[0x1]; 9811 u8 reserved_at_101[0xb]; 9812 u8 pattern[0x4]; 9813 u8 reserved_at_110[0x4]; 9814 u8 pin_mode[0x4]; 9815 u8 pin[0x8]; 9816 9817 u8 reserved_at_120[0x20]; 9818 9819 u8 time_stamp[0x40]; 9820 9821 u8 out_pulse_duration[0x10]; 9822 u8 out_periodic_adjustment[0x10]; 9823 u8 enhanced_out_periodic_adjustment[0x20]; 9824 9825 u8 reserved_at_1c0[0x20]; 9826 }; 9827 9828 struct mlx5_ifc_mtppse_reg_bits { 9829 u8 reserved_at_0[0x18]; 9830 u8 pin[0x8]; 9831 u8 event_arm[0x1]; 9832 u8 reserved_at_21[0x1b]; 9833 u8 event_generation_mode[0x4]; 9834 u8 reserved_at_40[0x40]; 9835 }; 9836 9837 struct mlx5_ifc_mcqs_reg_bits { 9838 u8 last_index_flag[0x1]; 9839 u8 reserved_at_1[0x7]; 9840 u8 fw_device[0x8]; 9841 u8 component_index[0x10]; 9842 9843 u8 reserved_at_20[0x10]; 9844 u8 identifier[0x10]; 9845 9846 u8 reserved_at_40[0x17]; 9847 u8 component_status[0x5]; 9848 u8 component_update_state[0x4]; 9849 9850 u8 last_update_state_changer_type[0x4]; 9851 u8 last_update_state_changer_host_id[0x4]; 9852 u8 reserved_at_68[0x18]; 9853 }; 9854 9855 struct mlx5_ifc_mcqi_cap_bits { 9856 u8 supported_info_bitmask[0x20]; 9857 9858 u8 component_size[0x20]; 9859 9860 u8 max_component_size[0x20]; 9861 9862 u8 log_mcda_word_size[0x4]; 9863 u8 reserved_at_64[0xc]; 9864 u8 mcda_max_write_size[0x10]; 9865 9866 u8 rd_en[0x1]; 9867 u8 reserved_at_81[0x1]; 9868 u8 match_chip_id[0x1]; 9869 u8 match_psid[0x1]; 9870 u8 check_user_timestamp[0x1]; 9871 u8 match_base_guid_mac[0x1]; 9872 u8 reserved_at_86[0x1a]; 9873 }; 9874 9875 struct mlx5_ifc_mcqi_version_bits { 9876 u8 reserved_at_0[0x2]; 9877 u8 build_time_valid[0x1]; 9878 u8 user_defined_time_valid[0x1]; 9879 u8 reserved_at_4[0x14]; 9880 u8 version_string_length[0x8]; 9881 9882 u8 version[0x20]; 9883 9884 u8 build_time[0x40]; 9885 9886 u8 user_defined_time[0x40]; 9887 9888 u8 build_tool_version[0x20]; 9889 9890 u8 reserved_at_e0[0x20]; 9891 9892 u8 version_string[92][0x8]; 9893 }; 9894 9895 struct mlx5_ifc_mcqi_activation_method_bits { 9896 u8 pending_server_ac_power_cycle[0x1]; 9897 u8 pending_server_dc_power_cycle[0x1]; 9898 u8 pending_server_reboot[0x1]; 9899 u8 pending_fw_reset[0x1]; 9900 u8 auto_activate[0x1]; 9901 u8 all_hosts_sync[0x1]; 9902 u8 device_hw_reset[0x1]; 9903 u8 reserved_at_7[0x19]; 9904 }; 9905 9906 union mlx5_ifc_mcqi_reg_data_bits { 9907 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9908 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9909 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9910 }; 9911 9912 struct mlx5_ifc_mcqi_reg_bits { 9913 u8 read_pending_component[0x1]; 9914 u8 reserved_at_1[0xf]; 9915 u8 component_index[0x10]; 9916 9917 u8 reserved_at_20[0x20]; 9918 9919 u8 reserved_at_40[0x1b]; 9920 u8 info_type[0x5]; 9921 9922 u8 info_size[0x20]; 9923 9924 u8 offset[0x20]; 9925 9926 u8 reserved_at_a0[0x10]; 9927 u8 data_size[0x10]; 9928 9929 union mlx5_ifc_mcqi_reg_data_bits data[]; 9930 }; 9931 9932 struct mlx5_ifc_mcc_reg_bits { 9933 u8 reserved_at_0[0x4]; 9934 u8 time_elapsed_since_last_cmd[0xc]; 9935 u8 reserved_at_10[0x8]; 9936 u8 instruction[0x8]; 9937 9938 u8 reserved_at_20[0x10]; 9939 u8 component_index[0x10]; 9940 9941 u8 reserved_at_40[0x8]; 9942 u8 update_handle[0x18]; 9943 9944 u8 handle_owner_type[0x4]; 9945 u8 handle_owner_host_id[0x4]; 9946 u8 reserved_at_68[0x1]; 9947 u8 control_progress[0x7]; 9948 u8 error_code[0x8]; 9949 u8 reserved_at_78[0x4]; 9950 u8 control_state[0x4]; 9951 9952 u8 component_size[0x20]; 9953 9954 u8 reserved_at_a0[0x60]; 9955 }; 9956 9957 struct mlx5_ifc_mcda_reg_bits { 9958 u8 reserved_at_0[0x8]; 9959 u8 update_handle[0x18]; 9960 9961 u8 offset[0x20]; 9962 9963 u8 reserved_at_40[0x10]; 9964 u8 size[0x10]; 9965 9966 u8 reserved_at_60[0x20]; 9967 9968 u8 data[][0x20]; 9969 }; 9970 9971 enum { 9972 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9973 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9974 }; 9975 9976 enum { 9977 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9978 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9979 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9980 }; 9981 9982 struct mlx5_ifc_mfrl_reg_bits { 9983 u8 reserved_at_0[0x20]; 9984 9985 u8 reserved_at_20[0x2]; 9986 u8 pci_sync_for_fw_update_start[0x1]; 9987 u8 pci_sync_for_fw_update_resp[0x2]; 9988 u8 rst_type_sel[0x3]; 9989 u8 reserved_at_28[0x8]; 9990 u8 reset_type[0x8]; 9991 u8 reset_level[0x8]; 9992 }; 9993 9994 struct mlx5_ifc_mirc_reg_bits { 9995 u8 reserved_at_0[0x18]; 9996 u8 status_code[0x8]; 9997 9998 u8 reserved_at_20[0x20]; 9999 }; 10000 10001 struct mlx5_ifc_pddr_monitor_opcode_bits { 10002 u8 reserved_at_0[0x10]; 10003 u8 monitor_opcode[0x10]; 10004 }; 10005 10006 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10007 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10008 u8 reserved_at_0[0x20]; 10009 }; 10010 10011 enum { 10012 /* Monitor opcodes */ 10013 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10014 }; 10015 10016 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10017 u8 reserved_at_0[0x10]; 10018 u8 group_opcode[0x10]; 10019 10020 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10021 10022 u8 reserved_at_40[0x20]; 10023 10024 u8 status_message[59][0x20]; 10025 }; 10026 10027 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10028 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10029 u8 reserved_at_0[0x7c0]; 10030 }; 10031 10032 enum { 10033 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10034 }; 10035 10036 struct mlx5_ifc_pddr_reg_bits { 10037 u8 reserved_at_0[0x8]; 10038 u8 local_port[0x8]; 10039 u8 pnat[0x2]; 10040 u8 reserved_at_12[0xe]; 10041 10042 u8 reserved_at_20[0x18]; 10043 u8 page_select[0x8]; 10044 10045 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10046 }; 10047 10048 union mlx5_ifc_ports_control_registers_document_bits { 10049 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10050 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10051 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10052 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10053 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10054 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10055 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10056 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10057 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10058 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10059 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10060 struct mlx5_ifc_paos_reg_bits paos_reg; 10061 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10062 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10063 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10064 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10065 struct mlx5_ifc_peir_reg_bits peir_reg; 10066 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10067 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10068 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10069 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10070 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10071 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10072 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10073 struct mlx5_ifc_plib_reg_bits plib_reg; 10074 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10075 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10076 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10077 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10078 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10079 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10080 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10081 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10082 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10083 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10084 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10085 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10086 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10087 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10088 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10089 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10090 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10091 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10092 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10093 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10094 struct mlx5_ifc_pude_reg_bits pude_reg; 10095 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10096 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10097 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10098 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10099 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10100 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10101 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10102 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10103 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10104 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10105 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10106 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10107 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10108 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10109 u8 reserved_at_0[0x60e0]; 10110 }; 10111 10112 union mlx5_ifc_debug_enhancements_document_bits { 10113 struct mlx5_ifc_health_buffer_bits health_buffer; 10114 u8 reserved_at_0[0x200]; 10115 }; 10116 10117 union mlx5_ifc_uplink_pci_interface_document_bits { 10118 struct mlx5_ifc_initial_seg_bits initial_seg; 10119 u8 reserved_at_0[0x20060]; 10120 }; 10121 10122 struct mlx5_ifc_set_flow_table_root_out_bits { 10123 u8 status[0x8]; 10124 u8 reserved_at_8[0x18]; 10125 10126 u8 syndrome[0x20]; 10127 10128 u8 reserved_at_40[0x40]; 10129 }; 10130 10131 struct mlx5_ifc_set_flow_table_root_in_bits { 10132 u8 opcode[0x10]; 10133 u8 reserved_at_10[0x10]; 10134 10135 u8 reserved_at_20[0x10]; 10136 u8 op_mod[0x10]; 10137 10138 u8 other_vport[0x1]; 10139 u8 reserved_at_41[0xf]; 10140 u8 vport_number[0x10]; 10141 10142 u8 reserved_at_60[0x20]; 10143 10144 u8 table_type[0x8]; 10145 u8 reserved_at_88[0x7]; 10146 u8 table_of_other_vport[0x1]; 10147 u8 table_vport_number[0x10]; 10148 10149 u8 reserved_at_a0[0x8]; 10150 u8 table_id[0x18]; 10151 10152 u8 reserved_at_c0[0x8]; 10153 u8 underlay_qpn[0x18]; 10154 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10155 u8 reserved_at_e1[0xf]; 10156 u8 table_eswitch_owner_vhca_id[0x10]; 10157 u8 reserved_at_100[0x100]; 10158 }; 10159 10160 enum { 10161 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10162 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10163 }; 10164 10165 struct mlx5_ifc_modify_flow_table_out_bits { 10166 u8 status[0x8]; 10167 u8 reserved_at_8[0x18]; 10168 10169 u8 syndrome[0x20]; 10170 10171 u8 reserved_at_40[0x40]; 10172 }; 10173 10174 struct mlx5_ifc_modify_flow_table_in_bits { 10175 u8 opcode[0x10]; 10176 u8 reserved_at_10[0x10]; 10177 10178 u8 reserved_at_20[0x10]; 10179 u8 op_mod[0x10]; 10180 10181 u8 other_vport[0x1]; 10182 u8 reserved_at_41[0xf]; 10183 u8 vport_number[0x10]; 10184 10185 u8 reserved_at_60[0x10]; 10186 u8 modify_field_select[0x10]; 10187 10188 u8 table_type[0x8]; 10189 u8 reserved_at_88[0x18]; 10190 10191 u8 reserved_at_a0[0x8]; 10192 u8 table_id[0x18]; 10193 10194 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10195 }; 10196 10197 struct mlx5_ifc_ets_tcn_config_reg_bits { 10198 u8 g[0x1]; 10199 u8 b[0x1]; 10200 u8 r[0x1]; 10201 u8 reserved_at_3[0x9]; 10202 u8 group[0x4]; 10203 u8 reserved_at_10[0x9]; 10204 u8 bw_allocation[0x7]; 10205 10206 u8 reserved_at_20[0xc]; 10207 u8 max_bw_units[0x4]; 10208 u8 reserved_at_30[0x8]; 10209 u8 max_bw_value[0x8]; 10210 }; 10211 10212 struct mlx5_ifc_ets_global_config_reg_bits { 10213 u8 reserved_at_0[0x2]; 10214 u8 r[0x1]; 10215 u8 reserved_at_3[0x1d]; 10216 10217 u8 reserved_at_20[0xc]; 10218 u8 max_bw_units[0x4]; 10219 u8 reserved_at_30[0x8]; 10220 u8 max_bw_value[0x8]; 10221 }; 10222 10223 struct mlx5_ifc_qetc_reg_bits { 10224 u8 reserved_at_0[0x8]; 10225 u8 port_number[0x8]; 10226 u8 reserved_at_10[0x30]; 10227 10228 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10229 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10230 }; 10231 10232 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10233 u8 e[0x1]; 10234 u8 reserved_at_01[0x0b]; 10235 u8 prio[0x04]; 10236 }; 10237 10238 struct mlx5_ifc_qpdpm_reg_bits { 10239 u8 reserved_at_0[0x8]; 10240 u8 local_port[0x8]; 10241 u8 reserved_at_10[0x10]; 10242 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10243 }; 10244 10245 struct mlx5_ifc_qpts_reg_bits { 10246 u8 reserved_at_0[0x8]; 10247 u8 local_port[0x8]; 10248 u8 reserved_at_10[0x2d]; 10249 u8 trust_state[0x3]; 10250 }; 10251 10252 struct mlx5_ifc_pptb_reg_bits { 10253 u8 reserved_at_0[0x2]; 10254 u8 mm[0x2]; 10255 u8 reserved_at_4[0x4]; 10256 u8 local_port[0x8]; 10257 u8 reserved_at_10[0x6]; 10258 u8 cm[0x1]; 10259 u8 um[0x1]; 10260 u8 pm[0x8]; 10261 10262 u8 prio_x_buff[0x20]; 10263 10264 u8 pm_msb[0x8]; 10265 u8 reserved_at_48[0x10]; 10266 u8 ctrl_buff[0x4]; 10267 u8 untagged_buff[0x4]; 10268 }; 10269 10270 struct mlx5_ifc_sbcam_reg_bits { 10271 u8 reserved_at_0[0x8]; 10272 u8 feature_group[0x8]; 10273 u8 reserved_at_10[0x8]; 10274 u8 access_reg_group[0x8]; 10275 10276 u8 reserved_at_20[0x20]; 10277 10278 u8 sb_access_reg_cap_mask[4][0x20]; 10279 10280 u8 reserved_at_c0[0x80]; 10281 10282 u8 sb_feature_cap_mask[4][0x20]; 10283 10284 u8 reserved_at_1c0[0x40]; 10285 10286 u8 cap_total_buffer_size[0x20]; 10287 10288 u8 cap_cell_size[0x10]; 10289 u8 cap_max_pg_buffers[0x8]; 10290 u8 cap_num_pool_supported[0x8]; 10291 10292 u8 reserved_at_240[0x8]; 10293 u8 cap_sbsr_stat_size[0x8]; 10294 u8 cap_max_tclass_data[0x8]; 10295 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10296 }; 10297 10298 struct mlx5_ifc_pbmc_reg_bits { 10299 u8 reserved_at_0[0x8]; 10300 u8 local_port[0x8]; 10301 u8 reserved_at_10[0x10]; 10302 10303 u8 xoff_timer_value[0x10]; 10304 u8 xoff_refresh[0x10]; 10305 10306 u8 reserved_at_40[0x9]; 10307 u8 fullness_threshold[0x7]; 10308 u8 port_buffer_size[0x10]; 10309 10310 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10311 10312 u8 reserved_at_2e0[0x80]; 10313 }; 10314 10315 struct mlx5_ifc_qtct_reg_bits { 10316 u8 reserved_at_0[0x8]; 10317 u8 port_number[0x8]; 10318 u8 reserved_at_10[0xd]; 10319 u8 prio[0x3]; 10320 10321 u8 reserved_at_20[0x1d]; 10322 u8 tclass[0x3]; 10323 }; 10324 10325 struct mlx5_ifc_mcia_reg_bits { 10326 u8 l[0x1]; 10327 u8 reserved_at_1[0x7]; 10328 u8 module[0x8]; 10329 u8 reserved_at_10[0x8]; 10330 u8 status[0x8]; 10331 10332 u8 i2c_device_address[0x8]; 10333 u8 page_number[0x8]; 10334 u8 device_address[0x10]; 10335 10336 u8 reserved_at_40[0x10]; 10337 u8 size[0x10]; 10338 10339 u8 reserved_at_60[0x20]; 10340 10341 u8 dword_0[0x20]; 10342 u8 dword_1[0x20]; 10343 u8 dword_2[0x20]; 10344 u8 dword_3[0x20]; 10345 u8 dword_4[0x20]; 10346 u8 dword_5[0x20]; 10347 u8 dword_6[0x20]; 10348 u8 dword_7[0x20]; 10349 u8 dword_8[0x20]; 10350 u8 dword_9[0x20]; 10351 u8 dword_10[0x20]; 10352 u8 dword_11[0x20]; 10353 }; 10354 10355 struct mlx5_ifc_dcbx_param_bits { 10356 u8 dcbx_cee_cap[0x1]; 10357 u8 dcbx_ieee_cap[0x1]; 10358 u8 dcbx_standby_cap[0x1]; 10359 u8 reserved_at_3[0x5]; 10360 u8 port_number[0x8]; 10361 u8 reserved_at_10[0xa]; 10362 u8 max_application_table_size[6]; 10363 u8 reserved_at_20[0x15]; 10364 u8 version_oper[0x3]; 10365 u8 reserved_at_38[5]; 10366 u8 version_admin[0x3]; 10367 u8 willing_admin[0x1]; 10368 u8 reserved_at_41[0x3]; 10369 u8 pfc_cap_oper[0x4]; 10370 u8 reserved_at_48[0x4]; 10371 u8 pfc_cap_admin[0x4]; 10372 u8 reserved_at_50[0x4]; 10373 u8 num_of_tc_oper[0x4]; 10374 u8 reserved_at_58[0x4]; 10375 u8 num_of_tc_admin[0x4]; 10376 u8 remote_willing[0x1]; 10377 u8 reserved_at_61[3]; 10378 u8 remote_pfc_cap[4]; 10379 u8 reserved_at_68[0x14]; 10380 u8 remote_num_of_tc[0x4]; 10381 u8 reserved_at_80[0x18]; 10382 u8 error[0x8]; 10383 u8 reserved_at_a0[0x160]; 10384 }; 10385 10386 struct mlx5_ifc_lagc_bits { 10387 u8 fdb_selection_mode[0x1]; 10388 u8 reserved_at_1[0x1c]; 10389 u8 lag_state[0x3]; 10390 10391 u8 reserved_at_20[0x14]; 10392 u8 tx_remap_affinity_2[0x4]; 10393 u8 reserved_at_38[0x4]; 10394 u8 tx_remap_affinity_1[0x4]; 10395 }; 10396 10397 struct mlx5_ifc_create_lag_out_bits { 10398 u8 status[0x8]; 10399 u8 reserved_at_8[0x18]; 10400 10401 u8 syndrome[0x20]; 10402 10403 u8 reserved_at_40[0x40]; 10404 }; 10405 10406 struct mlx5_ifc_create_lag_in_bits { 10407 u8 opcode[0x10]; 10408 u8 reserved_at_10[0x10]; 10409 10410 u8 reserved_at_20[0x10]; 10411 u8 op_mod[0x10]; 10412 10413 struct mlx5_ifc_lagc_bits ctx; 10414 }; 10415 10416 struct mlx5_ifc_modify_lag_out_bits { 10417 u8 status[0x8]; 10418 u8 reserved_at_8[0x18]; 10419 10420 u8 syndrome[0x20]; 10421 10422 u8 reserved_at_40[0x40]; 10423 }; 10424 10425 struct mlx5_ifc_modify_lag_in_bits { 10426 u8 opcode[0x10]; 10427 u8 reserved_at_10[0x10]; 10428 10429 u8 reserved_at_20[0x10]; 10430 u8 op_mod[0x10]; 10431 10432 u8 reserved_at_40[0x20]; 10433 u8 field_select[0x20]; 10434 10435 struct mlx5_ifc_lagc_bits ctx; 10436 }; 10437 10438 struct mlx5_ifc_query_lag_out_bits { 10439 u8 status[0x8]; 10440 u8 reserved_at_8[0x18]; 10441 10442 u8 syndrome[0x20]; 10443 10444 struct mlx5_ifc_lagc_bits ctx; 10445 }; 10446 10447 struct mlx5_ifc_query_lag_in_bits { 10448 u8 opcode[0x10]; 10449 u8 reserved_at_10[0x10]; 10450 10451 u8 reserved_at_20[0x10]; 10452 u8 op_mod[0x10]; 10453 10454 u8 reserved_at_40[0x40]; 10455 }; 10456 10457 struct mlx5_ifc_destroy_lag_out_bits { 10458 u8 status[0x8]; 10459 u8 reserved_at_8[0x18]; 10460 10461 u8 syndrome[0x20]; 10462 10463 u8 reserved_at_40[0x40]; 10464 }; 10465 10466 struct mlx5_ifc_destroy_lag_in_bits { 10467 u8 opcode[0x10]; 10468 u8 reserved_at_10[0x10]; 10469 10470 u8 reserved_at_20[0x10]; 10471 u8 op_mod[0x10]; 10472 10473 u8 reserved_at_40[0x40]; 10474 }; 10475 10476 struct mlx5_ifc_create_vport_lag_out_bits { 10477 u8 status[0x8]; 10478 u8 reserved_at_8[0x18]; 10479 10480 u8 syndrome[0x20]; 10481 10482 u8 reserved_at_40[0x40]; 10483 }; 10484 10485 struct mlx5_ifc_create_vport_lag_in_bits { 10486 u8 opcode[0x10]; 10487 u8 reserved_at_10[0x10]; 10488 10489 u8 reserved_at_20[0x10]; 10490 u8 op_mod[0x10]; 10491 10492 u8 reserved_at_40[0x40]; 10493 }; 10494 10495 struct mlx5_ifc_destroy_vport_lag_out_bits { 10496 u8 status[0x8]; 10497 u8 reserved_at_8[0x18]; 10498 10499 u8 syndrome[0x20]; 10500 10501 u8 reserved_at_40[0x40]; 10502 }; 10503 10504 struct mlx5_ifc_destroy_vport_lag_in_bits { 10505 u8 opcode[0x10]; 10506 u8 reserved_at_10[0x10]; 10507 10508 u8 reserved_at_20[0x10]; 10509 u8 op_mod[0x10]; 10510 10511 u8 reserved_at_40[0x40]; 10512 }; 10513 10514 enum { 10515 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10516 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10517 }; 10518 10519 struct mlx5_ifc_modify_memic_in_bits { 10520 u8 opcode[0x10]; 10521 u8 uid[0x10]; 10522 10523 u8 reserved_at_20[0x10]; 10524 u8 op_mod[0x10]; 10525 10526 u8 reserved_at_40[0x20]; 10527 10528 u8 reserved_at_60[0x18]; 10529 u8 memic_operation_type[0x8]; 10530 10531 u8 memic_start_addr[0x40]; 10532 10533 u8 reserved_at_c0[0x140]; 10534 }; 10535 10536 struct mlx5_ifc_modify_memic_out_bits { 10537 u8 status[0x8]; 10538 u8 reserved_at_8[0x18]; 10539 10540 u8 syndrome[0x20]; 10541 10542 u8 reserved_at_40[0x40]; 10543 10544 u8 memic_operation_addr[0x40]; 10545 10546 u8 reserved_at_c0[0x140]; 10547 }; 10548 10549 struct mlx5_ifc_alloc_memic_in_bits { 10550 u8 opcode[0x10]; 10551 u8 reserved_at_10[0x10]; 10552 10553 u8 reserved_at_20[0x10]; 10554 u8 op_mod[0x10]; 10555 10556 u8 reserved_at_30[0x20]; 10557 10558 u8 reserved_at_40[0x18]; 10559 u8 log_memic_addr_alignment[0x8]; 10560 10561 u8 range_start_addr[0x40]; 10562 10563 u8 range_size[0x20]; 10564 10565 u8 memic_size[0x20]; 10566 }; 10567 10568 struct mlx5_ifc_alloc_memic_out_bits { 10569 u8 status[0x8]; 10570 u8 reserved_at_8[0x18]; 10571 10572 u8 syndrome[0x20]; 10573 10574 u8 memic_start_addr[0x40]; 10575 }; 10576 10577 struct mlx5_ifc_dealloc_memic_in_bits { 10578 u8 opcode[0x10]; 10579 u8 reserved_at_10[0x10]; 10580 10581 u8 reserved_at_20[0x10]; 10582 u8 op_mod[0x10]; 10583 10584 u8 reserved_at_40[0x40]; 10585 10586 u8 memic_start_addr[0x40]; 10587 10588 u8 memic_size[0x20]; 10589 10590 u8 reserved_at_e0[0x20]; 10591 }; 10592 10593 struct mlx5_ifc_dealloc_memic_out_bits { 10594 u8 status[0x8]; 10595 u8 reserved_at_8[0x18]; 10596 10597 u8 syndrome[0x20]; 10598 10599 u8 reserved_at_40[0x40]; 10600 }; 10601 10602 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10603 u8 opcode[0x10]; 10604 u8 uid[0x10]; 10605 10606 u8 vhca_tunnel_id[0x10]; 10607 u8 obj_type[0x10]; 10608 10609 u8 obj_id[0x20]; 10610 10611 u8 reserved_at_60[0x20]; 10612 }; 10613 10614 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10615 u8 status[0x8]; 10616 u8 reserved_at_8[0x18]; 10617 10618 u8 syndrome[0x20]; 10619 10620 u8 obj_id[0x20]; 10621 10622 u8 reserved_at_60[0x20]; 10623 }; 10624 10625 struct mlx5_ifc_umem_bits { 10626 u8 reserved_at_0[0x80]; 10627 10628 u8 reserved_at_80[0x1b]; 10629 u8 log_page_size[0x5]; 10630 10631 u8 page_offset[0x20]; 10632 10633 u8 num_of_mtt[0x40]; 10634 10635 struct mlx5_ifc_mtt_bits mtt[]; 10636 }; 10637 10638 struct mlx5_ifc_uctx_bits { 10639 u8 cap[0x20]; 10640 10641 u8 reserved_at_20[0x160]; 10642 }; 10643 10644 struct mlx5_ifc_sw_icm_bits { 10645 u8 modify_field_select[0x40]; 10646 10647 u8 reserved_at_40[0x18]; 10648 u8 log_sw_icm_size[0x8]; 10649 10650 u8 reserved_at_60[0x20]; 10651 10652 u8 sw_icm_start_addr[0x40]; 10653 10654 u8 reserved_at_c0[0x140]; 10655 }; 10656 10657 struct mlx5_ifc_geneve_tlv_option_bits { 10658 u8 modify_field_select[0x40]; 10659 10660 u8 reserved_at_40[0x18]; 10661 u8 geneve_option_fte_index[0x8]; 10662 10663 u8 option_class[0x10]; 10664 u8 option_type[0x8]; 10665 u8 reserved_at_78[0x3]; 10666 u8 option_data_length[0x5]; 10667 10668 u8 reserved_at_80[0x180]; 10669 }; 10670 10671 struct mlx5_ifc_create_umem_in_bits { 10672 u8 opcode[0x10]; 10673 u8 uid[0x10]; 10674 10675 u8 reserved_at_20[0x10]; 10676 u8 op_mod[0x10]; 10677 10678 u8 reserved_at_40[0x40]; 10679 10680 struct mlx5_ifc_umem_bits umem; 10681 }; 10682 10683 struct mlx5_ifc_create_umem_out_bits { 10684 u8 status[0x8]; 10685 u8 reserved_at_8[0x18]; 10686 10687 u8 syndrome[0x20]; 10688 10689 u8 reserved_at_40[0x8]; 10690 u8 umem_id[0x18]; 10691 10692 u8 reserved_at_60[0x20]; 10693 }; 10694 10695 struct mlx5_ifc_destroy_umem_in_bits { 10696 u8 opcode[0x10]; 10697 u8 uid[0x10]; 10698 10699 u8 reserved_at_20[0x10]; 10700 u8 op_mod[0x10]; 10701 10702 u8 reserved_at_40[0x8]; 10703 u8 umem_id[0x18]; 10704 10705 u8 reserved_at_60[0x20]; 10706 }; 10707 10708 struct mlx5_ifc_destroy_umem_out_bits { 10709 u8 status[0x8]; 10710 u8 reserved_at_8[0x18]; 10711 10712 u8 syndrome[0x20]; 10713 10714 u8 reserved_at_40[0x40]; 10715 }; 10716 10717 struct mlx5_ifc_create_uctx_in_bits { 10718 u8 opcode[0x10]; 10719 u8 reserved_at_10[0x10]; 10720 10721 u8 reserved_at_20[0x10]; 10722 u8 op_mod[0x10]; 10723 10724 u8 reserved_at_40[0x40]; 10725 10726 struct mlx5_ifc_uctx_bits uctx; 10727 }; 10728 10729 struct mlx5_ifc_create_uctx_out_bits { 10730 u8 status[0x8]; 10731 u8 reserved_at_8[0x18]; 10732 10733 u8 syndrome[0x20]; 10734 10735 u8 reserved_at_40[0x10]; 10736 u8 uid[0x10]; 10737 10738 u8 reserved_at_60[0x20]; 10739 }; 10740 10741 struct mlx5_ifc_destroy_uctx_in_bits { 10742 u8 opcode[0x10]; 10743 u8 reserved_at_10[0x10]; 10744 10745 u8 reserved_at_20[0x10]; 10746 u8 op_mod[0x10]; 10747 10748 u8 reserved_at_40[0x10]; 10749 u8 uid[0x10]; 10750 10751 u8 reserved_at_60[0x20]; 10752 }; 10753 10754 struct mlx5_ifc_destroy_uctx_out_bits { 10755 u8 status[0x8]; 10756 u8 reserved_at_8[0x18]; 10757 10758 u8 syndrome[0x20]; 10759 10760 u8 reserved_at_40[0x40]; 10761 }; 10762 10763 struct mlx5_ifc_create_sw_icm_in_bits { 10764 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10765 struct mlx5_ifc_sw_icm_bits sw_icm; 10766 }; 10767 10768 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10769 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10770 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10771 }; 10772 10773 struct mlx5_ifc_mtrc_string_db_param_bits { 10774 u8 string_db_base_address[0x20]; 10775 10776 u8 reserved_at_20[0x8]; 10777 u8 string_db_size[0x18]; 10778 }; 10779 10780 struct mlx5_ifc_mtrc_cap_bits { 10781 u8 trace_owner[0x1]; 10782 u8 trace_to_memory[0x1]; 10783 u8 reserved_at_2[0x4]; 10784 u8 trc_ver[0x2]; 10785 u8 reserved_at_8[0x14]; 10786 u8 num_string_db[0x4]; 10787 10788 u8 first_string_trace[0x8]; 10789 u8 num_string_trace[0x8]; 10790 u8 reserved_at_30[0x28]; 10791 10792 u8 log_max_trace_buffer_size[0x8]; 10793 10794 u8 reserved_at_60[0x20]; 10795 10796 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10797 10798 u8 reserved_at_280[0x180]; 10799 }; 10800 10801 struct mlx5_ifc_mtrc_conf_bits { 10802 u8 reserved_at_0[0x1c]; 10803 u8 trace_mode[0x4]; 10804 u8 reserved_at_20[0x18]; 10805 u8 log_trace_buffer_size[0x8]; 10806 u8 trace_mkey[0x20]; 10807 u8 reserved_at_60[0x3a0]; 10808 }; 10809 10810 struct mlx5_ifc_mtrc_stdb_bits { 10811 u8 string_db_index[0x4]; 10812 u8 reserved_at_4[0x4]; 10813 u8 read_size[0x18]; 10814 u8 start_offset[0x20]; 10815 u8 string_db_data[]; 10816 }; 10817 10818 struct mlx5_ifc_mtrc_ctrl_bits { 10819 u8 trace_status[0x2]; 10820 u8 reserved_at_2[0x2]; 10821 u8 arm_event[0x1]; 10822 u8 reserved_at_5[0xb]; 10823 u8 modify_field_select[0x10]; 10824 u8 reserved_at_20[0x2b]; 10825 u8 current_timestamp52_32[0x15]; 10826 u8 current_timestamp31_0[0x20]; 10827 u8 reserved_at_80[0x180]; 10828 }; 10829 10830 struct mlx5_ifc_host_params_context_bits { 10831 u8 host_number[0x8]; 10832 u8 reserved_at_8[0x7]; 10833 u8 host_pf_disabled[0x1]; 10834 u8 host_num_of_vfs[0x10]; 10835 10836 u8 host_total_vfs[0x10]; 10837 u8 host_pci_bus[0x10]; 10838 10839 u8 reserved_at_40[0x10]; 10840 u8 host_pci_device[0x10]; 10841 10842 u8 reserved_at_60[0x10]; 10843 u8 host_pci_function[0x10]; 10844 10845 u8 reserved_at_80[0x180]; 10846 }; 10847 10848 struct mlx5_ifc_query_esw_functions_in_bits { 10849 u8 opcode[0x10]; 10850 u8 reserved_at_10[0x10]; 10851 10852 u8 reserved_at_20[0x10]; 10853 u8 op_mod[0x10]; 10854 10855 u8 reserved_at_40[0x40]; 10856 }; 10857 10858 struct mlx5_ifc_query_esw_functions_out_bits { 10859 u8 status[0x8]; 10860 u8 reserved_at_8[0x18]; 10861 10862 u8 syndrome[0x20]; 10863 10864 u8 reserved_at_40[0x40]; 10865 10866 struct mlx5_ifc_host_params_context_bits host_params_context; 10867 10868 u8 reserved_at_280[0x180]; 10869 u8 host_sf_enable[][0x40]; 10870 }; 10871 10872 struct mlx5_ifc_sf_partition_bits { 10873 u8 reserved_at_0[0x10]; 10874 u8 log_num_sf[0x8]; 10875 u8 log_sf_bar_size[0x8]; 10876 }; 10877 10878 struct mlx5_ifc_query_sf_partitions_out_bits { 10879 u8 status[0x8]; 10880 u8 reserved_at_8[0x18]; 10881 10882 u8 syndrome[0x20]; 10883 10884 u8 reserved_at_40[0x18]; 10885 u8 num_sf_partitions[0x8]; 10886 10887 u8 reserved_at_60[0x20]; 10888 10889 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10890 }; 10891 10892 struct mlx5_ifc_query_sf_partitions_in_bits { 10893 u8 opcode[0x10]; 10894 u8 reserved_at_10[0x10]; 10895 10896 u8 reserved_at_20[0x10]; 10897 u8 op_mod[0x10]; 10898 10899 u8 reserved_at_40[0x40]; 10900 }; 10901 10902 struct mlx5_ifc_dealloc_sf_out_bits { 10903 u8 status[0x8]; 10904 u8 reserved_at_8[0x18]; 10905 10906 u8 syndrome[0x20]; 10907 10908 u8 reserved_at_40[0x40]; 10909 }; 10910 10911 struct mlx5_ifc_dealloc_sf_in_bits { 10912 u8 opcode[0x10]; 10913 u8 reserved_at_10[0x10]; 10914 10915 u8 reserved_at_20[0x10]; 10916 u8 op_mod[0x10]; 10917 10918 u8 reserved_at_40[0x10]; 10919 u8 function_id[0x10]; 10920 10921 u8 reserved_at_60[0x20]; 10922 }; 10923 10924 struct mlx5_ifc_alloc_sf_out_bits { 10925 u8 status[0x8]; 10926 u8 reserved_at_8[0x18]; 10927 10928 u8 syndrome[0x20]; 10929 10930 u8 reserved_at_40[0x40]; 10931 }; 10932 10933 struct mlx5_ifc_alloc_sf_in_bits { 10934 u8 opcode[0x10]; 10935 u8 reserved_at_10[0x10]; 10936 10937 u8 reserved_at_20[0x10]; 10938 u8 op_mod[0x10]; 10939 10940 u8 reserved_at_40[0x10]; 10941 u8 function_id[0x10]; 10942 10943 u8 reserved_at_60[0x20]; 10944 }; 10945 10946 struct mlx5_ifc_affiliated_event_header_bits { 10947 u8 reserved_at_0[0x10]; 10948 u8 obj_type[0x10]; 10949 10950 u8 obj_id[0x20]; 10951 }; 10952 10953 enum { 10954 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10955 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10956 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10957 }; 10958 10959 enum { 10960 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10961 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10962 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10963 }; 10964 10965 enum { 10966 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10967 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10968 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10969 }; 10970 10971 struct mlx5_ifc_ipsec_obj_bits { 10972 u8 modify_field_select[0x40]; 10973 u8 full_offload[0x1]; 10974 u8 reserved_at_41[0x1]; 10975 u8 esn_en[0x1]; 10976 u8 esn_overlap[0x1]; 10977 u8 reserved_at_44[0x2]; 10978 u8 icv_length[0x2]; 10979 u8 reserved_at_48[0x4]; 10980 u8 aso_return_reg[0x4]; 10981 u8 reserved_at_50[0x10]; 10982 10983 u8 esn_msb[0x20]; 10984 10985 u8 reserved_at_80[0x8]; 10986 u8 dekn[0x18]; 10987 10988 u8 salt[0x20]; 10989 10990 u8 implicit_iv[0x40]; 10991 10992 u8 reserved_at_100[0x700]; 10993 }; 10994 10995 struct mlx5_ifc_create_ipsec_obj_in_bits { 10996 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10997 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10998 }; 10999 11000 enum { 11001 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11002 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11003 }; 11004 11005 struct mlx5_ifc_query_ipsec_obj_out_bits { 11006 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11007 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11008 }; 11009 11010 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11011 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11012 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11013 }; 11014 11015 struct mlx5_ifc_encryption_key_obj_bits { 11016 u8 modify_field_select[0x40]; 11017 11018 u8 reserved_at_40[0x14]; 11019 u8 key_size[0x4]; 11020 u8 reserved_at_58[0x4]; 11021 u8 key_type[0x4]; 11022 11023 u8 reserved_at_60[0x8]; 11024 u8 pd[0x18]; 11025 11026 u8 reserved_at_80[0x180]; 11027 u8 key[8][0x20]; 11028 11029 u8 reserved_at_300[0x500]; 11030 }; 11031 11032 struct mlx5_ifc_create_encryption_key_in_bits { 11033 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11034 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11035 }; 11036 11037 struct mlx5_ifc_sampler_obj_bits { 11038 u8 modify_field_select[0x40]; 11039 11040 u8 table_type[0x8]; 11041 u8 level[0x8]; 11042 u8 reserved_at_50[0xf]; 11043 u8 ignore_flow_level[0x1]; 11044 11045 u8 sample_ratio[0x20]; 11046 11047 u8 reserved_at_80[0x8]; 11048 u8 sample_table_id[0x18]; 11049 11050 u8 reserved_at_a0[0x8]; 11051 u8 default_table_id[0x18]; 11052 11053 u8 sw_steering_icm_address_rx[0x40]; 11054 u8 sw_steering_icm_address_tx[0x40]; 11055 11056 u8 reserved_at_140[0xa0]; 11057 }; 11058 11059 struct mlx5_ifc_create_sampler_obj_in_bits { 11060 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11061 struct mlx5_ifc_sampler_obj_bits sampler_object; 11062 }; 11063 11064 struct mlx5_ifc_query_sampler_obj_out_bits { 11065 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11066 struct mlx5_ifc_sampler_obj_bits sampler_object; 11067 }; 11068 11069 enum { 11070 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11071 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11072 }; 11073 11074 enum { 11075 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11076 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11077 }; 11078 11079 struct mlx5_ifc_tls_static_params_bits { 11080 u8 const_2[0x2]; 11081 u8 tls_version[0x4]; 11082 u8 const_1[0x2]; 11083 u8 reserved_at_8[0x14]; 11084 u8 encryption_standard[0x4]; 11085 11086 u8 reserved_at_20[0x20]; 11087 11088 u8 initial_record_number[0x40]; 11089 11090 u8 resync_tcp_sn[0x20]; 11091 11092 u8 gcm_iv[0x20]; 11093 11094 u8 implicit_iv[0x40]; 11095 11096 u8 reserved_at_100[0x8]; 11097 u8 dek_index[0x18]; 11098 11099 u8 reserved_at_120[0xe0]; 11100 }; 11101 11102 struct mlx5_ifc_tls_progress_params_bits { 11103 u8 next_record_tcp_sn[0x20]; 11104 11105 u8 hw_resync_tcp_sn[0x20]; 11106 11107 u8 record_tracker_state[0x2]; 11108 u8 auth_state[0x2]; 11109 u8 reserved_at_44[0x4]; 11110 u8 hw_offset_record_number[0x18]; 11111 }; 11112 11113 enum { 11114 MLX5_MTT_PERM_READ = 1 << 0, 11115 MLX5_MTT_PERM_WRITE = 1 << 1, 11116 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11117 }; 11118 11119 #endif /* MLX5_IFC_H */ 11120