1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 72 MLX5_CMD_OP_INIT_HCA = 0x102, 73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 74 MLX5_CMD_OP_ENABLE_HCA = 0x104, 75 MLX5_CMD_OP_DISABLE_HCA = 0x105, 76 MLX5_CMD_OP_QUERY_PAGES = 0x107, 77 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 78 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 79 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 80 MLX5_CMD_OP_SET_ISSI = 0x10b, 81 MLX5_CMD_OP_CREATE_MKEY = 0x200, 82 MLX5_CMD_OP_QUERY_MKEY = 0x201, 83 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 86 MLX5_CMD_OP_CREATE_EQ = 0x301, 87 MLX5_CMD_OP_DESTROY_EQ = 0x302, 88 MLX5_CMD_OP_QUERY_EQ = 0x303, 89 MLX5_CMD_OP_GEN_EQE = 0x304, 90 MLX5_CMD_OP_CREATE_CQ = 0x400, 91 MLX5_CMD_OP_DESTROY_CQ = 0x401, 92 MLX5_CMD_OP_QUERY_CQ = 0x402, 93 MLX5_CMD_OP_MODIFY_CQ = 0x403, 94 MLX5_CMD_OP_CREATE_QP = 0x500, 95 MLX5_CMD_OP_DESTROY_QP = 0x501, 96 MLX5_CMD_OP_RST2INIT_QP = 0x502, 97 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 98 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 99 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 101 MLX5_CMD_OP_2ERR_QP = 0x507, 102 MLX5_CMD_OP_2RST_QP = 0x50a, 103 MLX5_CMD_OP_QUERY_QP = 0x50b, 104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 106 MLX5_CMD_OP_CREATE_PSV = 0x600, 107 MLX5_CMD_OP_DESTROY_PSV = 0x601, 108 MLX5_CMD_OP_CREATE_SRQ = 0x700, 109 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 110 MLX5_CMD_OP_QUERY_SRQ = 0x702, 111 MLX5_CMD_OP_ARM_RQ = 0x703, 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 116 MLX5_CMD_OP_CREATE_DCT = 0x710, 117 MLX5_CMD_OP_DESTROY_DCT = 0x711, 118 MLX5_CMD_OP_DRAIN_DCT = 0x712, 119 MLX5_CMD_OP_QUERY_DCT = 0x713, 120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 137 MLX5_CMD_OP_ALLOC_PD = 0x800, 138 MLX5_CMD_OP_DEALLOC_PD = 0x801, 139 MLX5_CMD_OP_ALLOC_UAR = 0x802, 140 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 142 MLX5_CMD_OP_ACCESS_REG = 0x805, 143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807, 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 146 MLX5_CMD_OP_MAD_IFC = 0x50d, 147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 149 MLX5_CMD_OP_NOP = 0x80d, 150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 164 MLX5_CMD_OP_CREATE_TIR = 0x900, 165 MLX5_CMD_OP_MODIFY_TIR = 0x901, 166 MLX5_CMD_OP_DESTROY_TIR = 0x902, 167 MLX5_CMD_OP_QUERY_TIR = 0x903, 168 MLX5_CMD_OP_CREATE_SQ = 0x904, 169 MLX5_CMD_OP_MODIFY_SQ = 0x905, 170 MLX5_CMD_OP_DESTROY_SQ = 0x906, 171 MLX5_CMD_OP_QUERY_SQ = 0x907, 172 MLX5_CMD_OP_CREATE_RQ = 0x908, 173 MLX5_CMD_OP_MODIFY_RQ = 0x909, 174 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 175 MLX5_CMD_OP_QUERY_RQ = 0x90b, 176 MLX5_CMD_OP_CREATE_RMP = 0x90c, 177 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 178 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 179 MLX5_CMD_OP_QUERY_RMP = 0x90f, 180 MLX5_CMD_OP_CREATE_TIS = 0x912, 181 MLX5_CMD_OP_MODIFY_TIS = 0x913, 182 MLX5_CMD_OP_DESTROY_TIS = 0x914, 183 MLX5_CMD_OP_QUERY_TIS = 0x915, 184 MLX5_CMD_OP_CREATE_RQT = 0x916, 185 MLX5_CMD_OP_MODIFY_RQT = 0x917, 186 MLX5_CMD_OP_DESTROY_RQT = 0x918, 187 MLX5_CMD_OP_QUERY_RQT = 0x919, 188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938 197 }; 198 199 struct mlx5_ifc_flow_table_fields_supported_bits { 200 u8 outer_dmac[0x1]; 201 u8 outer_smac[0x1]; 202 u8 outer_ether_type[0x1]; 203 u8 reserved_0[0x1]; 204 u8 outer_first_prio[0x1]; 205 u8 outer_first_cfi[0x1]; 206 u8 outer_first_vid[0x1]; 207 u8 reserved_1[0x1]; 208 u8 outer_second_prio[0x1]; 209 u8 outer_second_cfi[0x1]; 210 u8 outer_second_vid[0x1]; 211 u8 reserved_2[0x1]; 212 u8 outer_sip[0x1]; 213 u8 outer_dip[0x1]; 214 u8 outer_frag[0x1]; 215 u8 outer_ip_protocol[0x1]; 216 u8 outer_ip_ecn[0x1]; 217 u8 outer_ip_dscp[0x1]; 218 u8 outer_udp_sport[0x1]; 219 u8 outer_udp_dport[0x1]; 220 u8 outer_tcp_sport[0x1]; 221 u8 outer_tcp_dport[0x1]; 222 u8 outer_tcp_flags[0x1]; 223 u8 outer_gre_protocol[0x1]; 224 u8 outer_gre_key[0x1]; 225 u8 outer_vxlan_vni[0x1]; 226 u8 reserved_3[0x5]; 227 u8 source_eswitch_port[0x1]; 228 229 u8 inner_dmac[0x1]; 230 u8 inner_smac[0x1]; 231 u8 inner_ether_type[0x1]; 232 u8 reserved_4[0x1]; 233 u8 inner_first_prio[0x1]; 234 u8 inner_first_cfi[0x1]; 235 u8 inner_first_vid[0x1]; 236 u8 reserved_5[0x1]; 237 u8 inner_second_prio[0x1]; 238 u8 inner_second_cfi[0x1]; 239 u8 inner_second_vid[0x1]; 240 u8 reserved_6[0x1]; 241 u8 inner_sip[0x1]; 242 u8 inner_dip[0x1]; 243 u8 inner_frag[0x1]; 244 u8 inner_ip_protocol[0x1]; 245 u8 inner_ip_ecn[0x1]; 246 u8 inner_ip_dscp[0x1]; 247 u8 inner_udp_sport[0x1]; 248 u8 inner_udp_dport[0x1]; 249 u8 inner_tcp_sport[0x1]; 250 u8 inner_tcp_dport[0x1]; 251 u8 inner_tcp_flags[0x1]; 252 u8 reserved_7[0x9]; 253 254 u8 reserved_8[0x40]; 255 }; 256 257 struct mlx5_ifc_flow_table_prop_layout_bits { 258 u8 ft_support[0x1]; 259 u8 reserved_0[0x1f]; 260 261 u8 reserved_1[0x2]; 262 u8 log_max_ft_size[0x6]; 263 u8 reserved_2[0x10]; 264 u8 max_ft_level[0x8]; 265 266 u8 reserved_3[0x20]; 267 268 u8 reserved_4[0x18]; 269 u8 log_max_ft_num[0x8]; 270 271 u8 reserved_5[0x18]; 272 u8 log_max_destination[0x8]; 273 274 u8 reserved_6[0x18]; 275 u8 log_max_flow[0x8]; 276 277 u8 reserved_7[0x40]; 278 279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 280 281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 282 }; 283 284 struct mlx5_ifc_odp_per_transport_service_cap_bits { 285 u8 send[0x1]; 286 u8 receive[0x1]; 287 u8 write[0x1]; 288 u8 read[0x1]; 289 u8 reserved_0[0x1]; 290 u8 srq_receive[0x1]; 291 u8 reserved_1[0x1a]; 292 }; 293 294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 295 u8 smac_47_16[0x20]; 296 297 u8 smac_15_0[0x10]; 298 u8 ethertype[0x10]; 299 300 u8 dmac_47_16[0x20]; 301 302 u8 dmac_15_0[0x10]; 303 u8 first_prio[0x3]; 304 u8 first_cfi[0x1]; 305 u8 first_vid[0xc]; 306 307 u8 ip_protocol[0x8]; 308 u8 ip_dscp[0x6]; 309 u8 ip_ecn[0x2]; 310 u8 vlan_tag[0x1]; 311 u8 reserved_0[0x1]; 312 u8 frag[0x1]; 313 u8 reserved_1[0x4]; 314 u8 tcp_flags[0x9]; 315 316 u8 tcp_sport[0x10]; 317 u8 tcp_dport[0x10]; 318 319 u8 reserved_2[0x20]; 320 321 u8 udp_sport[0x10]; 322 u8 udp_dport[0x10]; 323 324 u8 src_ip[4][0x20]; 325 326 u8 dst_ip[4][0x20]; 327 }; 328 329 struct mlx5_ifc_fte_match_set_misc_bits { 330 u8 reserved_0[0x20]; 331 332 u8 reserved_1[0x10]; 333 u8 source_port[0x10]; 334 335 u8 outer_second_prio[0x3]; 336 u8 outer_second_cfi[0x1]; 337 u8 outer_second_vid[0xc]; 338 u8 inner_second_prio[0x3]; 339 u8 inner_second_cfi[0x1]; 340 u8 inner_second_vid[0xc]; 341 342 u8 outer_second_vlan_tag[0x1]; 343 u8 inner_second_vlan_tag[0x1]; 344 u8 reserved_2[0xe]; 345 u8 gre_protocol[0x10]; 346 347 u8 gre_key_h[0x18]; 348 u8 gre_key_l[0x8]; 349 350 u8 vxlan_vni[0x18]; 351 u8 reserved_3[0x8]; 352 353 u8 reserved_4[0x20]; 354 355 u8 reserved_5[0xc]; 356 u8 outer_ipv6_flow_label[0x14]; 357 358 u8 reserved_6[0xc]; 359 u8 inner_ipv6_flow_label[0x14]; 360 361 u8 reserved_7[0xe0]; 362 }; 363 364 struct mlx5_ifc_cmd_pas_bits { 365 u8 pa_h[0x20]; 366 367 u8 pa_l[0x14]; 368 u8 reserved_0[0xc]; 369 }; 370 371 struct mlx5_ifc_uint64_bits { 372 u8 hi[0x20]; 373 374 u8 lo[0x20]; 375 }; 376 377 enum { 378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 380 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 381 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 382 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 383 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 384 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 385 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 386 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 387 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 388 }; 389 390 struct mlx5_ifc_ads_bits { 391 u8 fl[0x1]; 392 u8 free_ar[0x1]; 393 u8 reserved_0[0xe]; 394 u8 pkey_index[0x10]; 395 396 u8 reserved_1[0x8]; 397 u8 grh[0x1]; 398 u8 mlid[0x7]; 399 u8 rlid[0x10]; 400 401 u8 ack_timeout[0x5]; 402 u8 reserved_2[0x3]; 403 u8 src_addr_index[0x8]; 404 u8 reserved_3[0x4]; 405 u8 stat_rate[0x4]; 406 u8 hop_limit[0x8]; 407 408 u8 reserved_4[0x4]; 409 u8 tclass[0x8]; 410 u8 flow_label[0x14]; 411 412 u8 rgid_rip[16][0x8]; 413 414 u8 reserved_5[0x4]; 415 u8 f_dscp[0x1]; 416 u8 f_ecn[0x1]; 417 u8 reserved_6[0x1]; 418 u8 f_eth_prio[0x1]; 419 u8 ecn[0x2]; 420 u8 dscp[0x6]; 421 u8 udp_sport[0x10]; 422 423 u8 dei_cfi[0x1]; 424 u8 eth_prio[0x3]; 425 u8 sl[0x4]; 426 u8 port[0x8]; 427 u8 rmac_47_32[0x10]; 428 429 u8 rmac_31_0[0x20]; 430 }; 431 432 struct mlx5_ifc_flow_table_nic_cap_bits { 433 u8 reserved_0[0x200]; 434 435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 436 437 u8 reserved_1[0x200]; 438 439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 440 441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 442 443 u8 reserved_2[0x200]; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 446 447 u8 reserved_3[0x7200]; 448 }; 449 450 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 451 u8 csum_cap[0x1]; 452 u8 vlan_cap[0x1]; 453 u8 lro_cap[0x1]; 454 u8 lro_psh_flag[0x1]; 455 u8 lro_time_stamp[0x1]; 456 u8 reserved_0[0x3]; 457 u8 self_lb_en_modifiable[0x1]; 458 u8 reserved_1[0x2]; 459 u8 max_lso_cap[0x5]; 460 u8 reserved_2[0x4]; 461 u8 rss_ind_tbl_cap[0x4]; 462 u8 reserved_3[0x3]; 463 u8 tunnel_lso_const_out_ip_id[0x1]; 464 u8 reserved_4[0x2]; 465 u8 tunnel_statless_gre[0x1]; 466 u8 tunnel_stateless_vxlan[0x1]; 467 468 u8 reserved_5[0x20]; 469 470 u8 reserved_6[0x10]; 471 u8 lro_min_mss_size[0x10]; 472 473 u8 reserved_7[0x120]; 474 475 u8 lro_timer_supported_periods[4][0x20]; 476 477 u8 reserved_8[0x600]; 478 }; 479 480 struct mlx5_ifc_roce_cap_bits { 481 u8 roce_apm[0x1]; 482 u8 reserved_0[0x1f]; 483 484 u8 reserved_1[0x60]; 485 486 u8 reserved_2[0xc]; 487 u8 l3_type[0x4]; 488 u8 reserved_3[0x8]; 489 u8 roce_version[0x8]; 490 491 u8 reserved_4[0x10]; 492 u8 r_roce_dest_udp_port[0x10]; 493 494 u8 r_roce_max_src_udp_port[0x10]; 495 u8 r_roce_min_src_udp_port[0x10]; 496 497 u8 reserved_5[0x10]; 498 u8 roce_address_table_size[0x10]; 499 500 u8 reserved_6[0x700]; 501 }; 502 503 enum { 504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 511 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 512 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 513 }; 514 515 enum { 516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 525 }; 526 527 struct mlx5_ifc_atomic_caps_bits { 528 u8 reserved_0[0x40]; 529 530 u8 atomic_req_endianness[0x1]; 531 u8 reserved_1[0x1f]; 532 533 u8 reserved_2[0x20]; 534 535 u8 reserved_3[0x10]; 536 u8 atomic_operations[0x10]; 537 538 u8 reserved_4[0x10]; 539 u8 atomic_size_qp[0x10]; 540 541 u8 reserved_5[0x10]; 542 u8 atomic_size_dc[0x10]; 543 544 u8 reserved_6[0x720]; 545 }; 546 547 struct mlx5_ifc_odp_cap_bits { 548 u8 reserved_0[0x40]; 549 550 u8 sig[0x1]; 551 u8 reserved_1[0x1f]; 552 553 u8 reserved_2[0x20]; 554 555 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 556 557 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 558 559 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 560 561 u8 reserved_3[0x720]; 562 }; 563 564 enum { 565 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 566 MLX5_WQ_TYPE_CYCLIC = 0x1, 567 MLX5_WQ_TYPE_STRQ = 0x2, 568 }; 569 570 enum { 571 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 572 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 573 }; 574 575 enum { 576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 579 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 580 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 581 }; 582 583 enum { 584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 588 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 589 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 590 }; 591 592 enum { 593 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 594 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 595 }; 596 597 enum { 598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 599 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 600 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 601 }; 602 603 enum { 604 MLX5_CAP_PORT_TYPE_IB = 0x0, 605 MLX5_CAP_PORT_TYPE_ETH = 0x1, 606 }; 607 608 struct mlx5_ifc_cmd_hca_cap_bits { 609 u8 reserved_0[0x80]; 610 611 u8 log_max_srq_sz[0x8]; 612 u8 log_max_qp_sz[0x8]; 613 u8 reserved_1[0xb]; 614 u8 log_max_qp[0x5]; 615 616 u8 reserved_2[0xb]; 617 u8 log_max_srq[0x5]; 618 u8 reserved_3[0x10]; 619 620 u8 reserved_4[0x8]; 621 u8 log_max_cq_sz[0x8]; 622 u8 reserved_5[0xb]; 623 u8 log_max_cq[0x5]; 624 625 u8 log_max_eq_sz[0x8]; 626 u8 reserved_6[0x2]; 627 u8 log_max_mkey[0x6]; 628 u8 reserved_7[0xc]; 629 u8 log_max_eq[0x4]; 630 631 u8 max_indirection[0x8]; 632 u8 reserved_8[0x1]; 633 u8 log_max_mrw_sz[0x7]; 634 u8 reserved_9[0x2]; 635 u8 log_max_bsf_list_size[0x6]; 636 u8 reserved_10[0x2]; 637 u8 log_max_klm_list_size[0x6]; 638 639 u8 reserved_11[0xa]; 640 u8 log_max_ra_req_dc[0x6]; 641 u8 reserved_12[0xa]; 642 u8 log_max_ra_res_dc[0x6]; 643 644 u8 reserved_13[0xa]; 645 u8 log_max_ra_req_qp[0x6]; 646 u8 reserved_14[0xa]; 647 u8 log_max_ra_res_qp[0x6]; 648 649 u8 pad_cap[0x1]; 650 u8 cc_query_allowed[0x1]; 651 u8 cc_modify_allowed[0x1]; 652 u8 reserved_15[0xd]; 653 u8 gid_table_size[0x10]; 654 655 u8 out_of_seq_cnt[0x1]; 656 u8 vport_counters[0x1]; 657 u8 reserved_16[0x4]; 658 u8 max_qp_cnt[0xa]; 659 u8 pkey_table_size[0x10]; 660 661 u8 vport_group_manager[0x1]; 662 u8 vhca_group_manager[0x1]; 663 u8 ib_virt[0x1]; 664 u8 eth_virt[0x1]; 665 u8 reserved_17[0x1]; 666 u8 ets[0x1]; 667 u8 nic_flow_table[0x1]; 668 u8 reserved_18[0x4]; 669 u8 local_ca_ack_delay[0x5]; 670 u8 reserved_19[0x6]; 671 u8 port_type[0x2]; 672 u8 num_ports[0x8]; 673 674 u8 reserved_20[0x3]; 675 u8 log_max_msg[0x5]; 676 u8 reserved_21[0x18]; 677 678 u8 stat_rate_support[0x10]; 679 u8 reserved_22[0xc]; 680 u8 cqe_version[0x4]; 681 682 u8 compact_address_vector[0x1]; 683 u8 reserved_23[0xe]; 684 u8 drain_sigerr[0x1]; 685 u8 cmdif_checksum[0x2]; 686 u8 sigerr_cqe[0x1]; 687 u8 reserved_24[0x1]; 688 u8 wq_signature[0x1]; 689 u8 sctr_data_cqe[0x1]; 690 u8 reserved_25[0x1]; 691 u8 sho[0x1]; 692 u8 tph[0x1]; 693 u8 rf[0x1]; 694 u8 dct[0x1]; 695 u8 reserved_26[0x1]; 696 u8 eth_net_offloads[0x1]; 697 u8 roce[0x1]; 698 u8 atomic[0x1]; 699 u8 reserved_27[0x1]; 700 701 u8 cq_oi[0x1]; 702 u8 cq_resize[0x1]; 703 u8 cq_moderation[0x1]; 704 u8 reserved_28[0x3]; 705 u8 cq_eq_remap[0x1]; 706 u8 pg[0x1]; 707 u8 block_lb_mc[0x1]; 708 u8 reserved_29[0x1]; 709 u8 scqe_break_moderation[0x1]; 710 u8 reserved_30[0x1]; 711 u8 cd[0x1]; 712 u8 reserved_31[0x1]; 713 u8 apm[0x1]; 714 u8 reserved_32[0x7]; 715 u8 qkv[0x1]; 716 u8 pkv[0x1]; 717 u8 reserved_33[0x4]; 718 u8 xrc[0x1]; 719 u8 ud[0x1]; 720 u8 uc[0x1]; 721 u8 rc[0x1]; 722 723 u8 reserved_34[0xa]; 724 u8 uar_sz[0x6]; 725 u8 reserved_35[0x8]; 726 u8 log_pg_sz[0x8]; 727 728 u8 bf[0x1]; 729 u8 reserved_36[0x1]; 730 u8 pad_tx_eth_packet[0x1]; 731 u8 reserved_37[0x8]; 732 u8 log_bf_reg_size[0x5]; 733 u8 reserved_38[0x10]; 734 735 u8 reserved_39[0x10]; 736 u8 max_wqe_sz_sq[0x10]; 737 738 u8 reserved_40[0x10]; 739 u8 max_wqe_sz_rq[0x10]; 740 741 u8 reserved_41[0x10]; 742 u8 max_wqe_sz_sq_dc[0x10]; 743 744 u8 reserved_42[0x7]; 745 u8 max_qp_mcg[0x19]; 746 747 u8 reserved_43[0x18]; 748 u8 log_max_mcg[0x8]; 749 750 u8 reserved_44[0x3]; 751 u8 log_max_transport_domain[0x5]; 752 u8 reserved_45[0x3]; 753 u8 log_max_pd[0x5]; 754 u8 reserved_46[0xb]; 755 u8 log_max_xrcd[0x5]; 756 757 u8 reserved_47[0x20]; 758 759 u8 reserved_48[0x3]; 760 u8 log_max_rq[0x5]; 761 u8 reserved_49[0x3]; 762 u8 log_max_sq[0x5]; 763 u8 reserved_50[0x3]; 764 u8 log_max_tir[0x5]; 765 u8 reserved_51[0x3]; 766 u8 log_max_tis[0x5]; 767 768 u8 basic_cyclic_rcv_wqe[0x1]; 769 u8 reserved_52[0x2]; 770 u8 log_max_rmp[0x5]; 771 u8 reserved_53[0x3]; 772 u8 log_max_rqt[0x5]; 773 u8 reserved_54[0x3]; 774 u8 log_max_rqt_size[0x5]; 775 u8 reserved_55[0x3]; 776 u8 log_max_tis_per_sq[0x5]; 777 778 u8 reserved_56[0x3]; 779 u8 log_max_stride_sz_rq[0x5]; 780 u8 reserved_57[0x3]; 781 u8 log_min_stride_sz_rq[0x5]; 782 u8 reserved_58[0x3]; 783 u8 log_max_stride_sz_sq[0x5]; 784 u8 reserved_59[0x3]; 785 u8 log_min_stride_sz_sq[0x5]; 786 787 u8 reserved_60[0x1b]; 788 u8 log_max_wq_sz[0x5]; 789 790 u8 reserved_61[0xa0]; 791 792 u8 reserved_62[0x3]; 793 u8 log_max_l2_table[0x5]; 794 u8 reserved_63[0x8]; 795 u8 log_uar_page_sz[0x10]; 796 797 u8 reserved_64[0x100]; 798 799 u8 reserved_65[0x1f]; 800 u8 cqe_zip[0x1]; 801 802 u8 cqe_zip_timeout[0x10]; 803 u8 cqe_zip_max_num[0x10]; 804 805 u8 reserved_66[0x220]; 806 }; 807 808 enum { 809 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1, 810 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2, 811 }; 812 813 struct mlx5_ifc_dest_format_struct_bits { 814 u8 destination_type[0x8]; 815 u8 destination_id[0x18]; 816 817 u8 reserved_0[0x20]; 818 }; 819 820 struct mlx5_ifc_fte_match_param_bits { 821 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 822 823 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 824 825 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 826 827 u8 reserved_0[0xa00]; 828 }; 829 830 enum { 831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 832 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 833 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 834 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 835 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 836 }; 837 838 struct mlx5_ifc_rx_hash_field_select_bits { 839 u8 l3_prot_type[0x1]; 840 u8 l4_prot_type[0x1]; 841 u8 selected_fields[0x1e]; 842 }; 843 844 enum { 845 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 846 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 847 }; 848 849 enum { 850 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 851 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 852 }; 853 854 struct mlx5_ifc_wq_bits { 855 u8 wq_type[0x4]; 856 u8 wq_signature[0x1]; 857 u8 end_padding_mode[0x2]; 858 u8 cd_slave[0x1]; 859 u8 reserved_0[0x18]; 860 861 u8 hds_skip_first_sge[0x1]; 862 u8 log2_hds_buf_size[0x3]; 863 u8 reserved_1[0x7]; 864 u8 page_offset[0x5]; 865 u8 lwm[0x10]; 866 867 u8 reserved_2[0x8]; 868 u8 pd[0x18]; 869 870 u8 reserved_3[0x8]; 871 u8 uar_page[0x18]; 872 873 u8 dbr_addr[0x40]; 874 875 u8 hw_counter[0x20]; 876 877 u8 sw_counter[0x20]; 878 879 u8 reserved_4[0xc]; 880 u8 log_wq_stride[0x4]; 881 u8 reserved_5[0x3]; 882 u8 log_wq_pg_sz[0x5]; 883 u8 reserved_6[0x3]; 884 u8 log_wq_sz[0x5]; 885 886 u8 reserved_7[0x4e0]; 887 888 struct mlx5_ifc_cmd_pas_bits pas[0]; 889 }; 890 891 struct mlx5_ifc_rq_num_bits { 892 u8 reserved_0[0x8]; 893 u8 rq_num[0x18]; 894 }; 895 896 struct mlx5_ifc_mac_address_layout_bits { 897 u8 reserved_0[0x10]; 898 u8 mac_addr_47_32[0x10]; 899 900 u8 mac_addr_31_0[0x20]; 901 }; 902 903 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 904 u8 reserved_0[0xa0]; 905 906 u8 min_time_between_cnps[0x20]; 907 908 u8 reserved_1[0x12]; 909 u8 cnp_dscp[0x6]; 910 u8 reserved_2[0x5]; 911 u8 cnp_802p_prio[0x3]; 912 913 u8 reserved_3[0x720]; 914 }; 915 916 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 917 u8 reserved_0[0x60]; 918 919 u8 reserved_1[0x4]; 920 u8 clamp_tgt_rate[0x1]; 921 u8 reserved_2[0x3]; 922 u8 clamp_tgt_rate_after_time_inc[0x1]; 923 u8 reserved_3[0x17]; 924 925 u8 reserved_4[0x20]; 926 927 u8 rpg_time_reset[0x20]; 928 929 u8 rpg_byte_reset[0x20]; 930 931 u8 rpg_threshold[0x20]; 932 933 u8 rpg_max_rate[0x20]; 934 935 u8 rpg_ai_rate[0x20]; 936 937 u8 rpg_hai_rate[0x20]; 938 939 u8 rpg_gd[0x20]; 940 941 u8 rpg_min_dec_fac[0x20]; 942 943 u8 rpg_min_rate[0x20]; 944 945 u8 reserved_5[0xe0]; 946 947 u8 rate_to_set_on_first_cnp[0x20]; 948 949 u8 dce_tcp_g[0x20]; 950 951 u8 dce_tcp_rtt[0x20]; 952 953 u8 rate_reduce_monitor_period[0x20]; 954 955 u8 reserved_6[0x20]; 956 957 u8 initial_alpha_value[0x20]; 958 959 u8 reserved_7[0x4a0]; 960 }; 961 962 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 963 u8 reserved_0[0x80]; 964 965 u8 rppp_max_rps[0x20]; 966 967 u8 rpg_time_reset[0x20]; 968 969 u8 rpg_byte_reset[0x20]; 970 971 u8 rpg_threshold[0x20]; 972 973 u8 rpg_max_rate[0x20]; 974 975 u8 rpg_ai_rate[0x20]; 976 977 u8 rpg_hai_rate[0x20]; 978 979 u8 rpg_gd[0x20]; 980 981 u8 rpg_min_dec_fac[0x20]; 982 983 u8 rpg_min_rate[0x20]; 984 985 u8 reserved_1[0x640]; 986 }; 987 988 enum { 989 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 990 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 991 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 992 }; 993 994 struct mlx5_ifc_resize_field_select_bits { 995 u8 resize_field_select[0x20]; 996 }; 997 998 enum { 999 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1001 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1002 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1003 }; 1004 1005 struct mlx5_ifc_modify_field_select_bits { 1006 u8 modify_field_select[0x20]; 1007 }; 1008 1009 struct mlx5_ifc_field_select_r_roce_np_bits { 1010 u8 field_select_r_roce_np[0x20]; 1011 }; 1012 1013 struct mlx5_ifc_field_select_r_roce_rp_bits { 1014 u8 field_select_r_roce_rp[0x20]; 1015 }; 1016 1017 enum { 1018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1026 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1027 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1028 }; 1029 1030 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1031 u8 field_select_8021qaurp[0x20]; 1032 }; 1033 1034 struct mlx5_ifc_phys_layer_cntrs_bits { 1035 u8 time_since_last_clear_high[0x20]; 1036 1037 u8 time_since_last_clear_low[0x20]; 1038 1039 u8 symbol_errors_high[0x20]; 1040 1041 u8 symbol_errors_low[0x20]; 1042 1043 u8 sync_headers_errors_high[0x20]; 1044 1045 u8 sync_headers_errors_low[0x20]; 1046 1047 u8 edpl_bip_errors_lane0_high[0x20]; 1048 1049 u8 edpl_bip_errors_lane0_low[0x20]; 1050 1051 u8 edpl_bip_errors_lane1_high[0x20]; 1052 1053 u8 edpl_bip_errors_lane1_low[0x20]; 1054 1055 u8 edpl_bip_errors_lane2_high[0x20]; 1056 1057 u8 edpl_bip_errors_lane2_low[0x20]; 1058 1059 u8 edpl_bip_errors_lane3_high[0x20]; 1060 1061 u8 edpl_bip_errors_lane3_low[0x20]; 1062 1063 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1064 1065 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1066 1067 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1068 1069 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1070 1071 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1072 1073 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1074 1075 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1076 1077 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1078 1079 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1080 1081 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1082 1083 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1084 1085 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1086 1087 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1088 1089 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1090 1091 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1092 1093 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1094 1095 u8 rs_fec_corrected_blocks_high[0x20]; 1096 1097 u8 rs_fec_corrected_blocks_low[0x20]; 1098 1099 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1100 1101 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1102 1103 u8 rs_fec_no_errors_blocks_high[0x20]; 1104 1105 u8 rs_fec_no_errors_blocks_low[0x20]; 1106 1107 u8 rs_fec_single_error_blocks_high[0x20]; 1108 1109 u8 rs_fec_single_error_blocks_low[0x20]; 1110 1111 u8 rs_fec_corrected_symbols_total_high[0x20]; 1112 1113 u8 rs_fec_corrected_symbols_total_low[0x20]; 1114 1115 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1116 1117 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1118 1119 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1120 1121 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1122 1123 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1124 1125 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1126 1127 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1128 1129 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1130 1131 u8 link_down_events[0x20]; 1132 1133 u8 successful_recovery_events[0x20]; 1134 1135 u8 reserved_0[0x180]; 1136 }; 1137 1138 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1139 u8 transmit_queue_high[0x20]; 1140 1141 u8 transmit_queue_low[0x20]; 1142 1143 u8 reserved_0[0x780]; 1144 }; 1145 1146 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1147 u8 rx_octets_high[0x20]; 1148 1149 u8 rx_octets_low[0x20]; 1150 1151 u8 reserved_0[0xc0]; 1152 1153 u8 rx_frames_high[0x20]; 1154 1155 u8 rx_frames_low[0x20]; 1156 1157 u8 tx_octets_high[0x20]; 1158 1159 u8 tx_octets_low[0x20]; 1160 1161 u8 reserved_1[0xc0]; 1162 1163 u8 tx_frames_high[0x20]; 1164 1165 u8 tx_frames_low[0x20]; 1166 1167 u8 rx_pause_high[0x20]; 1168 1169 u8 rx_pause_low[0x20]; 1170 1171 u8 rx_pause_duration_high[0x20]; 1172 1173 u8 rx_pause_duration_low[0x20]; 1174 1175 u8 tx_pause_high[0x20]; 1176 1177 u8 tx_pause_low[0x20]; 1178 1179 u8 tx_pause_duration_high[0x20]; 1180 1181 u8 tx_pause_duration_low[0x20]; 1182 1183 u8 rx_pause_transition_high[0x20]; 1184 1185 u8 rx_pause_transition_low[0x20]; 1186 1187 u8 reserved_2[0x400]; 1188 }; 1189 1190 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1191 u8 port_transmit_wait_high[0x20]; 1192 1193 u8 port_transmit_wait_low[0x20]; 1194 1195 u8 reserved_0[0x780]; 1196 }; 1197 1198 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1199 u8 dot3stats_alignment_errors_high[0x20]; 1200 1201 u8 dot3stats_alignment_errors_low[0x20]; 1202 1203 u8 dot3stats_fcs_errors_high[0x20]; 1204 1205 u8 dot3stats_fcs_errors_low[0x20]; 1206 1207 u8 dot3stats_single_collision_frames_high[0x20]; 1208 1209 u8 dot3stats_single_collision_frames_low[0x20]; 1210 1211 u8 dot3stats_multiple_collision_frames_high[0x20]; 1212 1213 u8 dot3stats_multiple_collision_frames_low[0x20]; 1214 1215 u8 dot3stats_sqe_test_errors_high[0x20]; 1216 1217 u8 dot3stats_sqe_test_errors_low[0x20]; 1218 1219 u8 dot3stats_deferred_transmissions_high[0x20]; 1220 1221 u8 dot3stats_deferred_transmissions_low[0x20]; 1222 1223 u8 dot3stats_late_collisions_high[0x20]; 1224 1225 u8 dot3stats_late_collisions_low[0x20]; 1226 1227 u8 dot3stats_excessive_collisions_high[0x20]; 1228 1229 u8 dot3stats_excessive_collisions_low[0x20]; 1230 1231 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1232 1233 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1234 1235 u8 dot3stats_carrier_sense_errors_high[0x20]; 1236 1237 u8 dot3stats_carrier_sense_errors_low[0x20]; 1238 1239 u8 dot3stats_frame_too_longs_high[0x20]; 1240 1241 u8 dot3stats_frame_too_longs_low[0x20]; 1242 1243 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1244 1245 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1246 1247 u8 dot3stats_symbol_errors_high[0x20]; 1248 1249 u8 dot3stats_symbol_errors_low[0x20]; 1250 1251 u8 dot3control_in_unknown_opcodes_high[0x20]; 1252 1253 u8 dot3control_in_unknown_opcodes_low[0x20]; 1254 1255 u8 dot3in_pause_frames_high[0x20]; 1256 1257 u8 dot3in_pause_frames_low[0x20]; 1258 1259 u8 dot3out_pause_frames_high[0x20]; 1260 1261 u8 dot3out_pause_frames_low[0x20]; 1262 1263 u8 reserved_0[0x3c0]; 1264 }; 1265 1266 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1267 u8 ether_stats_drop_events_high[0x20]; 1268 1269 u8 ether_stats_drop_events_low[0x20]; 1270 1271 u8 ether_stats_octets_high[0x20]; 1272 1273 u8 ether_stats_octets_low[0x20]; 1274 1275 u8 ether_stats_pkts_high[0x20]; 1276 1277 u8 ether_stats_pkts_low[0x20]; 1278 1279 u8 ether_stats_broadcast_pkts_high[0x20]; 1280 1281 u8 ether_stats_broadcast_pkts_low[0x20]; 1282 1283 u8 ether_stats_multicast_pkts_high[0x20]; 1284 1285 u8 ether_stats_multicast_pkts_low[0x20]; 1286 1287 u8 ether_stats_crc_align_errors_high[0x20]; 1288 1289 u8 ether_stats_crc_align_errors_low[0x20]; 1290 1291 u8 ether_stats_undersize_pkts_high[0x20]; 1292 1293 u8 ether_stats_undersize_pkts_low[0x20]; 1294 1295 u8 ether_stats_oversize_pkts_high[0x20]; 1296 1297 u8 ether_stats_oversize_pkts_low[0x20]; 1298 1299 u8 ether_stats_fragments_high[0x20]; 1300 1301 u8 ether_stats_fragments_low[0x20]; 1302 1303 u8 ether_stats_jabbers_high[0x20]; 1304 1305 u8 ether_stats_jabbers_low[0x20]; 1306 1307 u8 ether_stats_collisions_high[0x20]; 1308 1309 u8 ether_stats_collisions_low[0x20]; 1310 1311 u8 ether_stats_pkts64octets_high[0x20]; 1312 1313 u8 ether_stats_pkts64octets_low[0x20]; 1314 1315 u8 ether_stats_pkts65to127octets_high[0x20]; 1316 1317 u8 ether_stats_pkts65to127octets_low[0x20]; 1318 1319 u8 ether_stats_pkts128to255octets_high[0x20]; 1320 1321 u8 ether_stats_pkts128to255octets_low[0x20]; 1322 1323 u8 ether_stats_pkts256to511octets_high[0x20]; 1324 1325 u8 ether_stats_pkts256to511octets_low[0x20]; 1326 1327 u8 ether_stats_pkts512to1023octets_high[0x20]; 1328 1329 u8 ether_stats_pkts512to1023octets_low[0x20]; 1330 1331 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1332 1333 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1334 1335 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1336 1337 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1338 1339 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1340 1341 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1342 1343 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1344 1345 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1346 1347 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1348 1349 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1350 1351 u8 reserved_0[0x280]; 1352 }; 1353 1354 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1355 u8 if_in_octets_high[0x20]; 1356 1357 u8 if_in_octets_low[0x20]; 1358 1359 u8 if_in_ucast_pkts_high[0x20]; 1360 1361 u8 if_in_ucast_pkts_low[0x20]; 1362 1363 u8 if_in_discards_high[0x20]; 1364 1365 u8 if_in_discards_low[0x20]; 1366 1367 u8 if_in_errors_high[0x20]; 1368 1369 u8 if_in_errors_low[0x20]; 1370 1371 u8 if_in_unknown_protos_high[0x20]; 1372 1373 u8 if_in_unknown_protos_low[0x20]; 1374 1375 u8 if_out_octets_high[0x20]; 1376 1377 u8 if_out_octets_low[0x20]; 1378 1379 u8 if_out_ucast_pkts_high[0x20]; 1380 1381 u8 if_out_ucast_pkts_low[0x20]; 1382 1383 u8 if_out_discards_high[0x20]; 1384 1385 u8 if_out_discards_low[0x20]; 1386 1387 u8 if_out_errors_high[0x20]; 1388 1389 u8 if_out_errors_low[0x20]; 1390 1391 u8 if_in_multicast_pkts_high[0x20]; 1392 1393 u8 if_in_multicast_pkts_low[0x20]; 1394 1395 u8 if_in_broadcast_pkts_high[0x20]; 1396 1397 u8 if_in_broadcast_pkts_low[0x20]; 1398 1399 u8 if_out_multicast_pkts_high[0x20]; 1400 1401 u8 if_out_multicast_pkts_low[0x20]; 1402 1403 u8 if_out_broadcast_pkts_high[0x20]; 1404 1405 u8 if_out_broadcast_pkts_low[0x20]; 1406 1407 u8 reserved_0[0x480]; 1408 }; 1409 1410 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1411 u8 a_frames_transmitted_ok_high[0x20]; 1412 1413 u8 a_frames_transmitted_ok_low[0x20]; 1414 1415 u8 a_frames_received_ok_high[0x20]; 1416 1417 u8 a_frames_received_ok_low[0x20]; 1418 1419 u8 a_frame_check_sequence_errors_high[0x20]; 1420 1421 u8 a_frame_check_sequence_errors_low[0x20]; 1422 1423 u8 a_alignment_errors_high[0x20]; 1424 1425 u8 a_alignment_errors_low[0x20]; 1426 1427 u8 a_octets_transmitted_ok_high[0x20]; 1428 1429 u8 a_octets_transmitted_ok_low[0x20]; 1430 1431 u8 a_octets_received_ok_high[0x20]; 1432 1433 u8 a_octets_received_ok_low[0x20]; 1434 1435 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1436 1437 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1438 1439 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1440 1441 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1442 1443 u8 a_multicast_frames_received_ok_high[0x20]; 1444 1445 u8 a_multicast_frames_received_ok_low[0x20]; 1446 1447 u8 a_broadcast_frames_received_ok_high[0x20]; 1448 1449 u8 a_broadcast_frames_received_ok_low[0x20]; 1450 1451 u8 a_in_range_length_errors_high[0x20]; 1452 1453 u8 a_in_range_length_errors_low[0x20]; 1454 1455 u8 a_out_of_range_length_field_high[0x20]; 1456 1457 u8 a_out_of_range_length_field_low[0x20]; 1458 1459 u8 a_frame_too_long_errors_high[0x20]; 1460 1461 u8 a_frame_too_long_errors_low[0x20]; 1462 1463 u8 a_symbol_error_during_carrier_high[0x20]; 1464 1465 u8 a_symbol_error_during_carrier_low[0x20]; 1466 1467 u8 a_mac_control_frames_transmitted_high[0x20]; 1468 1469 u8 a_mac_control_frames_transmitted_low[0x20]; 1470 1471 u8 a_mac_control_frames_received_high[0x20]; 1472 1473 u8 a_mac_control_frames_received_low[0x20]; 1474 1475 u8 a_unsupported_opcodes_received_high[0x20]; 1476 1477 u8 a_unsupported_opcodes_received_low[0x20]; 1478 1479 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1480 1481 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1482 1483 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1484 1485 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1486 1487 u8 reserved_0[0x300]; 1488 }; 1489 1490 struct mlx5_ifc_cmd_inter_comp_event_bits { 1491 u8 command_completion_vector[0x20]; 1492 1493 u8 reserved_0[0xc0]; 1494 }; 1495 1496 struct mlx5_ifc_stall_vl_event_bits { 1497 u8 reserved_0[0x18]; 1498 u8 port_num[0x1]; 1499 u8 reserved_1[0x3]; 1500 u8 vl[0x4]; 1501 1502 u8 reserved_2[0xa0]; 1503 }; 1504 1505 struct mlx5_ifc_db_bf_congestion_event_bits { 1506 u8 event_subtype[0x8]; 1507 u8 reserved_0[0x8]; 1508 u8 congestion_level[0x8]; 1509 u8 reserved_1[0x8]; 1510 1511 u8 reserved_2[0xa0]; 1512 }; 1513 1514 struct mlx5_ifc_gpio_event_bits { 1515 u8 reserved_0[0x60]; 1516 1517 u8 gpio_event_hi[0x20]; 1518 1519 u8 gpio_event_lo[0x20]; 1520 1521 u8 reserved_1[0x40]; 1522 }; 1523 1524 struct mlx5_ifc_port_state_change_event_bits { 1525 u8 reserved_0[0x40]; 1526 1527 u8 port_num[0x4]; 1528 u8 reserved_1[0x1c]; 1529 1530 u8 reserved_2[0x80]; 1531 }; 1532 1533 struct mlx5_ifc_dropped_packet_logged_bits { 1534 u8 reserved_0[0xe0]; 1535 }; 1536 1537 enum { 1538 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1539 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1540 }; 1541 1542 struct mlx5_ifc_cq_error_bits { 1543 u8 reserved_0[0x8]; 1544 u8 cqn[0x18]; 1545 1546 u8 reserved_1[0x20]; 1547 1548 u8 reserved_2[0x18]; 1549 u8 syndrome[0x8]; 1550 1551 u8 reserved_3[0x80]; 1552 }; 1553 1554 struct mlx5_ifc_rdma_page_fault_event_bits { 1555 u8 bytes_committed[0x20]; 1556 1557 u8 r_key[0x20]; 1558 1559 u8 reserved_0[0x10]; 1560 u8 packet_len[0x10]; 1561 1562 u8 rdma_op_len[0x20]; 1563 1564 u8 rdma_va[0x40]; 1565 1566 u8 reserved_1[0x5]; 1567 u8 rdma[0x1]; 1568 u8 write[0x1]; 1569 u8 requestor[0x1]; 1570 u8 qp_number[0x18]; 1571 }; 1572 1573 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1574 u8 bytes_committed[0x20]; 1575 1576 u8 reserved_0[0x10]; 1577 u8 wqe_index[0x10]; 1578 1579 u8 reserved_1[0x10]; 1580 u8 len[0x10]; 1581 1582 u8 reserved_2[0x60]; 1583 1584 u8 reserved_3[0x5]; 1585 u8 rdma[0x1]; 1586 u8 write_read[0x1]; 1587 u8 requestor[0x1]; 1588 u8 qpn[0x18]; 1589 }; 1590 1591 struct mlx5_ifc_qp_events_bits { 1592 u8 reserved_0[0xa0]; 1593 1594 u8 type[0x8]; 1595 u8 reserved_1[0x18]; 1596 1597 u8 reserved_2[0x8]; 1598 u8 qpn_rqn_sqn[0x18]; 1599 }; 1600 1601 struct mlx5_ifc_dct_events_bits { 1602 u8 reserved_0[0xc0]; 1603 1604 u8 reserved_1[0x8]; 1605 u8 dct_number[0x18]; 1606 }; 1607 1608 struct mlx5_ifc_comp_event_bits { 1609 u8 reserved_0[0xc0]; 1610 1611 u8 reserved_1[0x8]; 1612 u8 cq_number[0x18]; 1613 }; 1614 1615 enum { 1616 MLX5_QPC_STATE_RST = 0x0, 1617 MLX5_QPC_STATE_INIT = 0x1, 1618 MLX5_QPC_STATE_RTR = 0x2, 1619 MLX5_QPC_STATE_RTS = 0x3, 1620 MLX5_QPC_STATE_SQER = 0x4, 1621 MLX5_QPC_STATE_ERR = 0x6, 1622 MLX5_QPC_STATE_SQD = 0x7, 1623 MLX5_QPC_STATE_SUSPENDED = 0x9, 1624 }; 1625 1626 enum { 1627 MLX5_QPC_ST_RC = 0x0, 1628 MLX5_QPC_ST_UC = 0x1, 1629 MLX5_QPC_ST_UD = 0x2, 1630 MLX5_QPC_ST_XRC = 0x3, 1631 MLX5_QPC_ST_DCI = 0x5, 1632 MLX5_QPC_ST_QP0 = 0x7, 1633 MLX5_QPC_ST_QP1 = 0x8, 1634 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1635 MLX5_QPC_ST_REG_UMR = 0xc, 1636 }; 1637 1638 enum { 1639 MLX5_QPC_PM_STATE_ARMED = 0x0, 1640 MLX5_QPC_PM_STATE_REARM = 0x1, 1641 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1642 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1643 }; 1644 1645 enum { 1646 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1647 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1648 }; 1649 1650 enum { 1651 MLX5_QPC_MTU_256_BYTES = 0x1, 1652 MLX5_QPC_MTU_512_BYTES = 0x2, 1653 MLX5_QPC_MTU_1K_BYTES = 0x3, 1654 MLX5_QPC_MTU_2K_BYTES = 0x4, 1655 MLX5_QPC_MTU_4K_BYTES = 0x5, 1656 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1657 }; 1658 1659 enum { 1660 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1661 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1662 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1663 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1664 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1665 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1666 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1667 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1668 }; 1669 1670 enum { 1671 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1672 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1673 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1674 }; 1675 1676 enum { 1677 MLX5_QPC_CS_RES_DISABLE = 0x0, 1678 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1679 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1680 }; 1681 1682 struct mlx5_ifc_qpc_bits { 1683 u8 state[0x4]; 1684 u8 reserved_0[0x4]; 1685 u8 st[0x8]; 1686 u8 reserved_1[0x3]; 1687 u8 pm_state[0x2]; 1688 u8 reserved_2[0x7]; 1689 u8 end_padding_mode[0x2]; 1690 u8 reserved_3[0x2]; 1691 1692 u8 wq_signature[0x1]; 1693 u8 block_lb_mc[0x1]; 1694 u8 atomic_like_write_en[0x1]; 1695 u8 latency_sensitive[0x1]; 1696 u8 reserved_4[0x1]; 1697 u8 drain_sigerr[0x1]; 1698 u8 reserved_5[0x2]; 1699 u8 pd[0x18]; 1700 1701 u8 mtu[0x3]; 1702 u8 log_msg_max[0x5]; 1703 u8 reserved_6[0x1]; 1704 u8 log_rq_size[0x4]; 1705 u8 log_rq_stride[0x3]; 1706 u8 no_sq[0x1]; 1707 u8 log_sq_size[0x4]; 1708 u8 reserved_7[0x6]; 1709 u8 rlky[0x1]; 1710 u8 reserved_8[0x4]; 1711 1712 u8 counter_set_id[0x8]; 1713 u8 uar_page[0x18]; 1714 1715 u8 reserved_9[0x8]; 1716 u8 user_index[0x18]; 1717 1718 u8 reserved_10[0x3]; 1719 u8 log_page_size[0x5]; 1720 u8 remote_qpn[0x18]; 1721 1722 struct mlx5_ifc_ads_bits primary_address_path; 1723 1724 struct mlx5_ifc_ads_bits secondary_address_path; 1725 1726 u8 log_ack_req_freq[0x4]; 1727 u8 reserved_11[0x4]; 1728 u8 log_sra_max[0x3]; 1729 u8 reserved_12[0x2]; 1730 u8 retry_count[0x3]; 1731 u8 rnr_retry[0x3]; 1732 u8 reserved_13[0x1]; 1733 u8 fre[0x1]; 1734 u8 cur_rnr_retry[0x3]; 1735 u8 cur_retry_count[0x3]; 1736 u8 reserved_14[0x5]; 1737 1738 u8 reserved_15[0x20]; 1739 1740 u8 reserved_16[0x8]; 1741 u8 next_send_psn[0x18]; 1742 1743 u8 reserved_17[0x8]; 1744 u8 cqn_snd[0x18]; 1745 1746 u8 reserved_18[0x40]; 1747 1748 u8 reserved_19[0x8]; 1749 u8 last_acked_psn[0x18]; 1750 1751 u8 reserved_20[0x8]; 1752 u8 ssn[0x18]; 1753 1754 u8 reserved_21[0x8]; 1755 u8 log_rra_max[0x3]; 1756 u8 reserved_22[0x1]; 1757 u8 atomic_mode[0x4]; 1758 u8 rre[0x1]; 1759 u8 rwe[0x1]; 1760 u8 rae[0x1]; 1761 u8 reserved_23[0x1]; 1762 u8 page_offset[0x6]; 1763 u8 reserved_24[0x3]; 1764 u8 cd_slave_receive[0x1]; 1765 u8 cd_slave_send[0x1]; 1766 u8 cd_master[0x1]; 1767 1768 u8 reserved_25[0x3]; 1769 u8 min_rnr_nak[0x5]; 1770 u8 next_rcv_psn[0x18]; 1771 1772 u8 reserved_26[0x8]; 1773 u8 xrcd[0x18]; 1774 1775 u8 reserved_27[0x8]; 1776 u8 cqn_rcv[0x18]; 1777 1778 u8 dbr_addr[0x40]; 1779 1780 u8 q_key[0x20]; 1781 1782 u8 reserved_28[0x5]; 1783 u8 rq_type[0x3]; 1784 u8 srqn_rmpn[0x18]; 1785 1786 u8 reserved_29[0x8]; 1787 u8 rmsn[0x18]; 1788 1789 u8 hw_sq_wqebb_counter[0x10]; 1790 u8 sw_sq_wqebb_counter[0x10]; 1791 1792 u8 hw_rq_counter[0x20]; 1793 1794 u8 sw_rq_counter[0x20]; 1795 1796 u8 reserved_30[0x20]; 1797 1798 u8 reserved_31[0xf]; 1799 u8 cgs[0x1]; 1800 u8 cs_req[0x8]; 1801 u8 cs_res[0x8]; 1802 1803 u8 dc_access_key[0x40]; 1804 1805 u8 reserved_32[0xc0]; 1806 }; 1807 1808 struct mlx5_ifc_roce_addr_layout_bits { 1809 u8 source_l3_address[16][0x8]; 1810 1811 u8 reserved_0[0x3]; 1812 u8 vlan_valid[0x1]; 1813 u8 vlan_id[0xc]; 1814 u8 source_mac_47_32[0x10]; 1815 1816 u8 source_mac_31_0[0x20]; 1817 1818 u8 reserved_1[0x14]; 1819 u8 roce_l3_type[0x4]; 1820 u8 roce_version[0x8]; 1821 1822 u8 reserved_2[0x20]; 1823 }; 1824 1825 union mlx5_ifc_hca_cap_union_bits { 1826 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1827 struct mlx5_ifc_odp_cap_bits odp_cap; 1828 struct mlx5_ifc_atomic_caps_bits atomic_caps; 1829 struct mlx5_ifc_roce_cap_bits roce_cap; 1830 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 1831 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1832 u8 reserved_0[0x8000]; 1833 }; 1834 1835 enum { 1836 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 1837 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 1838 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 1839 }; 1840 1841 struct mlx5_ifc_flow_context_bits { 1842 u8 reserved_0[0x20]; 1843 1844 u8 group_id[0x20]; 1845 1846 u8 reserved_1[0x8]; 1847 u8 flow_tag[0x18]; 1848 1849 u8 reserved_2[0x10]; 1850 u8 action[0x10]; 1851 1852 u8 reserved_3[0x8]; 1853 u8 destination_list_size[0x18]; 1854 1855 u8 reserved_4[0x160]; 1856 1857 struct mlx5_ifc_fte_match_param_bits match_value; 1858 1859 u8 reserved_5[0x600]; 1860 1861 struct mlx5_ifc_dest_format_struct_bits destination[0]; 1862 }; 1863 1864 enum { 1865 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 1866 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 1867 }; 1868 1869 struct mlx5_ifc_xrc_srqc_bits { 1870 u8 state[0x4]; 1871 u8 log_xrc_srq_size[0x4]; 1872 u8 reserved_0[0x18]; 1873 1874 u8 wq_signature[0x1]; 1875 u8 cont_srq[0x1]; 1876 u8 reserved_1[0x1]; 1877 u8 rlky[0x1]; 1878 u8 basic_cyclic_rcv_wqe[0x1]; 1879 u8 log_rq_stride[0x3]; 1880 u8 xrcd[0x18]; 1881 1882 u8 page_offset[0x6]; 1883 u8 reserved_2[0x2]; 1884 u8 cqn[0x18]; 1885 1886 u8 reserved_3[0x20]; 1887 1888 u8 user_index_equal_xrc_srqn[0x1]; 1889 u8 reserved_4[0x1]; 1890 u8 log_page_size[0x6]; 1891 u8 user_index[0x18]; 1892 1893 u8 reserved_5[0x20]; 1894 1895 u8 reserved_6[0x8]; 1896 u8 pd[0x18]; 1897 1898 u8 lwm[0x10]; 1899 u8 wqe_cnt[0x10]; 1900 1901 u8 reserved_7[0x40]; 1902 1903 u8 db_record_addr_h[0x20]; 1904 1905 u8 db_record_addr_l[0x1e]; 1906 u8 reserved_8[0x2]; 1907 1908 u8 reserved_9[0x80]; 1909 }; 1910 1911 struct mlx5_ifc_traffic_counter_bits { 1912 u8 packets[0x40]; 1913 1914 u8 octets[0x40]; 1915 }; 1916 1917 struct mlx5_ifc_tisc_bits { 1918 u8 reserved_0[0xc]; 1919 u8 prio[0x4]; 1920 u8 reserved_1[0x10]; 1921 1922 u8 reserved_2[0x100]; 1923 1924 u8 reserved_3[0x8]; 1925 u8 transport_domain[0x18]; 1926 1927 u8 reserved_4[0x3c0]; 1928 }; 1929 1930 enum { 1931 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 1932 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 1933 }; 1934 1935 enum { 1936 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 1937 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 1938 }; 1939 1940 enum { 1941 MLX5_RX_HASH_FN_NONE = 0x0, 1942 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 1943 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 1944 }; 1945 1946 enum { 1947 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 1948 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 1949 }; 1950 1951 struct mlx5_ifc_tirc_bits { 1952 u8 reserved_0[0x20]; 1953 1954 u8 disp_type[0x4]; 1955 u8 reserved_1[0x1c]; 1956 1957 u8 reserved_2[0x40]; 1958 1959 u8 reserved_3[0x4]; 1960 u8 lro_timeout_period_usecs[0x10]; 1961 u8 lro_enable_mask[0x4]; 1962 u8 lro_max_ip_payload_size[0x8]; 1963 1964 u8 reserved_4[0x40]; 1965 1966 u8 reserved_5[0x8]; 1967 u8 inline_rqn[0x18]; 1968 1969 u8 rx_hash_symmetric[0x1]; 1970 u8 reserved_6[0x1]; 1971 u8 tunneled_offload_en[0x1]; 1972 u8 reserved_7[0x5]; 1973 u8 indirect_table[0x18]; 1974 1975 u8 rx_hash_fn[0x4]; 1976 u8 reserved_8[0x2]; 1977 u8 self_lb_block[0x2]; 1978 u8 transport_domain[0x18]; 1979 1980 u8 rx_hash_toeplitz_key[10][0x20]; 1981 1982 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 1983 1984 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 1985 1986 u8 reserved_9[0x4c0]; 1987 }; 1988 1989 enum { 1990 MLX5_SRQC_STATE_GOOD = 0x0, 1991 MLX5_SRQC_STATE_ERROR = 0x1, 1992 }; 1993 1994 struct mlx5_ifc_srqc_bits { 1995 u8 state[0x4]; 1996 u8 log_srq_size[0x4]; 1997 u8 reserved_0[0x18]; 1998 1999 u8 wq_signature[0x1]; 2000 u8 cont_srq[0x1]; 2001 u8 reserved_1[0x1]; 2002 u8 rlky[0x1]; 2003 u8 reserved_2[0x1]; 2004 u8 log_rq_stride[0x3]; 2005 u8 xrcd[0x18]; 2006 2007 u8 page_offset[0x6]; 2008 u8 reserved_3[0x2]; 2009 u8 cqn[0x18]; 2010 2011 u8 reserved_4[0x20]; 2012 2013 u8 reserved_5[0x2]; 2014 u8 log_page_size[0x6]; 2015 u8 reserved_6[0x18]; 2016 2017 u8 reserved_7[0x20]; 2018 2019 u8 reserved_8[0x8]; 2020 u8 pd[0x18]; 2021 2022 u8 lwm[0x10]; 2023 u8 wqe_cnt[0x10]; 2024 2025 u8 reserved_9[0x40]; 2026 2027 u8 dbr_addr[0x40]; 2028 2029 u8 reserved_10[0x80]; 2030 }; 2031 2032 enum { 2033 MLX5_SQC_STATE_RST = 0x0, 2034 MLX5_SQC_STATE_RDY = 0x1, 2035 MLX5_SQC_STATE_ERR = 0x3, 2036 }; 2037 2038 struct mlx5_ifc_sqc_bits { 2039 u8 rlky[0x1]; 2040 u8 cd_master[0x1]; 2041 u8 fre[0x1]; 2042 u8 flush_in_error_en[0x1]; 2043 u8 reserved_0[0x4]; 2044 u8 state[0x4]; 2045 u8 reserved_1[0x14]; 2046 2047 u8 reserved_2[0x8]; 2048 u8 user_index[0x18]; 2049 2050 u8 reserved_3[0x8]; 2051 u8 cqn[0x18]; 2052 2053 u8 reserved_4[0xa0]; 2054 2055 u8 tis_lst_sz[0x10]; 2056 u8 reserved_5[0x10]; 2057 2058 u8 reserved_6[0x40]; 2059 2060 u8 reserved_7[0x8]; 2061 u8 tis_num_0[0x18]; 2062 2063 struct mlx5_ifc_wq_bits wq; 2064 }; 2065 2066 struct mlx5_ifc_rqtc_bits { 2067 u8 reserved_0[0xa0]; 2068 2069 u8 reserved_1[0x10]; 2070 u8 rqt_max_size[0x10]; 2071 2072 u8 reserved_2[0x10]; 2073 u8 rqt_actual_size[0x10]; 2074 2075 u8 reserved_3[0x6a0]; 2076 2077 struct mlx5_ifc_rq_num_bits rq_num[0]; 2078 }; 2079 2080 enum { 2081 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2082 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2083 }; 2084 2085 enum { 2086 MLX5_RQC_STATE_RST = 0x0, 2087 MLX5_RQC_STATE_RDY = 0x1, 2088 MLX5_RQC_STATE_ERR = 0x3, 2089 }; 2090 2091 struct mlx5_ifc_rqc_bits { 2092 u8 rlky[0x1]; 2093 u8 reserved_0[0x2]; 2094 u8 vsd[0x1]; 2095 u8 mem_rq_type[0x4]; 2096 u8 state[0x4]; 2097 u8 reserved_1[0x1]; 2098 u8 flush_in_error_en[0x1]; 2099 u8 reserved_2[0x12]; 2100 2101 u8 reserved_3[0x8]; 2102 u8 user_index[0x18]; 2103 2104 u8 reserved_4[0x8]; 2105 u8 cqn[0x18]; 2106 2107 u8 counter_set_id[0x8]; 2108 u8 reserved_5[0x18]; 2109 2110 u8 reserved_6[0x8]; 2111 u8 rmpn[0x18]; 2112 2113 u8 reserved_7[0xe0]; 2114 2115 struct mlx5_ifc_wq_bits wq; 2116 }; 2117 2118 enum { 2119 MLX5_RMPC_STATE_RDY = 0x1, 2120 MLX5_RMPC_STATE_ERR = 0x3, 2121 }; 2122 2123 struct mlx5_ifc_rmpc_bits { 2124 u8 reserved_0[0x8]; 2125 u8 state[0x4]; 2126 u8 reserved_1[0x14]; 2127 2128 u8 basic_cyclic_rcv_wqe[0x1]; 2129 u8 reserved_2[0x1f]; 2130 2131 u8 reserved_3[0x140]; 2132 2133 struct mlx5_ifc_wq_bits wq; 2134 }; 2135 2136 enum { 2137 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2138 }; 2139 2140 struct mlx5_ifc_nic_vport_context_bits { 2141 u8 reserved_0[0x1f]; 2142 u8 roce_en[0x1]; 2143 2144 u8 reserved_1[0x760]; 2145 2146 u8 reserved_2[0x5]; 2147 u8 allowed_list_type[0x3]; 2148 u8 reserved_3[0xc]; 2149 u8 allowed_list_size[0xc]; 2150 2151 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2152 2153 u8 reserved_4[0x20]; 2154 2155 u8 current_uc_mac_address[0][0x40]; 2156 }; 2157 2158 enum { 2159 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2160 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2161 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2162 }; 2163 2164 struct mlx5_ifc_mkc_bits { 2165 u8 reserved_0[0x1]; 2166 u8 free[0x1]; 2167 u8 reserved_1[0xd]; 2168 u8 small_fence_on_rdma_read_response[0x1]; 2169 u8 umr_en[0x1]; 2170 u8 a[0x1]; 2171 u8 rw[0x1]; 2172 u8 rr[0x1]; 2173 u8 lw[0x1]; 2174 u8 lr[0x1]; 2175 u8 access_mode[0x2]; 2176 u8 reserved_2[0x8]; 2177 2178 u8 qpn[0x18]; 2179 u8 mkey_7_0[0x8]; 2180 2181 u8 reserved_3[0x20]; 2182 2183 u8 length64[0x1]; 2184 u8 bsf_en[0x1]; 2185 u8 sync_umr[0x1]; 2186 u8 reserved_4[0x2]; 2187 u8 expected_sigerr_count[0x1]; 2188 u8 reserved_5[0x1]; 2189 u8 en_rinval[0x1]; 2190 u8 pd[0x18]; 2191 2192 u8 start_addr[0x40]; 2193 2194 u8 len[0x40]; 2195 2196 u8 bsf_octword_size[0x20]; 2197 2198 u8 reserved_6[0x80]; 2199 2200 u8 translations_octword_size[0x20]; 2201 2202 u8 reserved_7[0x1b]; 2203 u8 log_page_size[0x5]; 2204 2205 u8 reserved_8[0x20]; 2206 }; 2207 2208 struct mlx5_ifc_pkey_bits { 2209 u8 reserved_0[0x10]; 2210 u8 pkey[0x10]; 2211 }; 2212 2213 struct mlx5_ifc_array128_auto_bits { 2214 u8 array128_auto[16][0x8]; 2215 }; 2216 2217 struct mlx5_ifc_hca_vport_context_bits { 2218 u8 field_select[0x20]; 2219 2220 u8 reserved_0[0xe0]; 2221 2222 u8 sm_virt_aware[0x1]; 2223 u8 has_smi[0x1]; 2224 u8 has_raw[0x1]; 2225 u8 grh_required[0x1]; 2226 u8 reserved_1[0xc]; 2227 u8 port_physical_state[0x4]; 2228 u8 vport_state_policy[0x4]; 2229 u8 port_state[0x4]; 2230 u8 vport_state[0x4]; 2231 2232 u8 reserved_2[0x20]; 2233 2234 u8 system_image_guid[0x40]; 2235 2236 u8 port_guid[0x40]; 2237 2238 u8 node_guid[0x40]; 2239 2240 u8 cap_mask1[0x20]; 2241 2242 u8 cap_mask1_field_select[0x20]; 2243 2244 u8 cap_mask2[0x20]; 2245 2246 u8 cap_mask2_field_select[0x20]; 2247 2248 u8 reserved_3[0x80]; 2249 2250 u8 lid[0x10]; 2251 u8 reserved_4[0x4]; 2252 u8 init_type_reply[0x4]; 2253 u8 lmc[0x3]; 2254 u8 subnet_timeout[0x5]; 2255 2256 u8 sm_lid[0x10]; 2257 u8 sm_sl[0x4]; 2258 u8 reserved_5[0xc]; 2259 2260 u8 qkey_violation_counter[0x10]; 2261 u8 pkey_violation_counter[0x10]; 2262 2263 u8 reserved_6[0xca0]; 2264 }; 2265 2266 enum { 2267 MLX5_EQC_STATUS_OK = 0x0, 2268 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2269 }; 2270 2271 enum { 2272 MLX5_EQC_ST_ARMED = 0x9, 2273 MLX5_EQC_ST_FIRED = 0xa, 2274 }; 2275 2276 struct mlx5_ifc_eqc_bits { 2277 u8 status[0x4]; 2278 u8 reserved_0[0x9]; 2279 u8 ec[0x1]; 2280 u8 oi[0x1]; 2281 u8 reserved_1[0x5]; 2282 u8 st[0x4]; 2283 u8 reserved_2[0x8]; 2284 2285 u8 reserved_3[0x20]; 2286 2287 u8 reserved_4[0x14]; 2288 u8 page_offset[0x6]; 2289 u8 reserved_5[0x6]; 2290 2291 u8 reserved_6[0x3]; 2292 u8 log_eq_size[0x5]; 2293 u8 uar_page[0x18]; 2294 2295 u8 reserved_7[0x20]; 2296 2297 u8 reserved_8[0x18]; 2298 u8 intr[0x8]; 2299 2300 u8 reserved_9[0x3]; 2301 u8 log_page_size[0x5]; 2302 u8 reserved_10[0x18]; 2303 2304 u8 reserved_11[0x60]; 2305 2306 u8 reserved_12[0x8]; 2307 u8 consumer_counter[0x18]; 2308 2309 u8 reserved_13[0x8]; 2310 u8 producer_counter[0x18]; 2311 2312 u8 reserved_14[0x80]; 2313 }; 2314 2315 enum { 2316 MLX5_DCTC_STATE_ACTIVE = 0x0, 2317 MLX5_DCTC_STATE_DRAINING = 0x1, 2318 MLX5_DCTC_STATE_DRAINED = 0x2, 2319 }; 2320 2321 enum { 2322 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2323 MLX5_DCTC_CS_RES_NA = 0x1, 2324 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2325 }; 2326 2327 enum { 2328 MLX5_DCTC_MTU_256_BYTES = 0x1, 2329 MLX5_DCTC_MTU_512_BYTES = 0x2, 2330 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2331 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2332 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2333 }; 2334 2335 struct mlx5_ifc_dctc_bits { 2336 u8 reserved_0[0x4]; 2337 u8 state[0x4]; 2338 u8 reserved_1[0x18]; 2339 2340 u8 reserved_2[0x8]; 2341 u8 user_index[0x18]; 2342 2343 u8 reserved_3[0x8]; 2344 u8 cqn[0x18]; 2345 2346 u8 counter_set_id[0x8]; 2347 u8 atomic_mode[0x4]; 2348 u8 rre[0x1]; 2349 u8 rwe[0x1]; 2350 u8 rae[0x1]; 2351 u8 atomic_like_write_en[0x1]; 2352 u8 latency_sensitive[0x1]; 2353 u8 rlky[0x1]; 2354 u8 free_ar[0x1]; 2355 u8 reserved_4[0xd]; 2356 2357 u8 reserved_5[0x8]; 2358 u8 cs_res[0x8]; 2359 u8 reserved_6[0x3]; 2360 u8 min_rnr_nak[0x5]; 2361 u8 reserved_7[0x8]; 2362 2363 u8 reserved_8[0x8]; 2364 u8 srqn[0x18]; 2365 2366 u8 reserved_9[0x8]; 2367 u8 pd[0x18]; 2368 2369 u8 tclass[0x8]; 2370 u8 reserved_10[0x4]; 2371 u8 flow_label[0x14]; 2372 2373 u8 dc_access_key[0x40]; 2374 2375 u8 reserved_11[0x5]; 2376 u8 mtu[0x3]; 2377 u8 port[0x8]; 2378 u8 pkey_index[0x10]; 2379 2380 u8 reserved_12[0x8]; 2381 u8 my_addr_index[0x8]; 2382 u8 reserved_13[0x8]; 2383 u8 hop_limit[0x8]; 2384 2385 u8 dc_access_key_violation_count[0x20]; 2386 2387 u8 reserved_14[0x14]; 2388 u8 dei_cfi[0x1]; 2389 u8 eth_prio[0x3]; 2390 u8 ecn[0x2]; 2391 u8 dscp[0x6]; 2392 2393 u8 reserved_15[0x40]; 2394 }; 2395 2396 enum { 2397 MLX5_CQC_STATUS_OK = 0x0, 2398 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2399 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2400 }; 2401 2402 enum { 2403 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2404 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2405 }; 2406 2407 enum { 2408 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2409 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2410 MLX5_CQC_ST_FIRED = 0xa, 2411 }; 2412 2413 struct mlx5_ifc_cqc_bits { 2414 u8 status[0x4]; 2415 u8 reserved_0[0x4]; 2416 u8 cqe_sz[0x3]; 2417 u8 cc[0x1]; 2418 u8 reserved_1[0x1]; 2419 u8 scqe_break_moderation_en[0x1]; 2420 u8 oi[0x1]; 2421 u8 reserved_2[0x2]; 2422 u8 cqe_zip_en[0x1]; 2423 u8 mini_cqe_res_format[0x2]; 2424 u8 st[0x4]; 2425 u8 reserved_3[0x8]; 2426 2427 u8 reserved_4[0x20]; 2428 2429 u8 reserved_5[0x14]; 2430 u8 page_offset[0x6]; 2431 u8 reserved_6[0x6]; 2432 2433 u8 reserved_7[0x3]; 2434 u8 log_cq_size[0x5]; 2435 u8 uar_page[0x18]; 2436 2437 u8 reserved_8[0x4]; 2438 u8 cq_period[0xc]; 2439 u8 cq_max_count[0x10]; 2440 2441 u8 reserved_9[0x18]; 2442 u8 c_eqn[0x8]; 2443 2444 u8 reserved_10[0x3]; 2445 u8 log_page_size[0x5]; 2446 u8 reserved_11[0x18]; 2447 2448 u8 reserved_12[0x20]; 2449 2450 u8 reserved_13[0x8]; 2451 u8 last_notified_index[0x18]; 2452 2453 u8 reserved_14[0x8]; 2454 u8 last_solicit_index[0x18]; 2455 2456 u8 reserved_15[0x8]; 2457 u8 consumer_counter[0x18]; 2458 2459 u8 reserved_16[0x8]; 2460 u8 producer_counter[0x18]; 2461 2462 u8 reserved_17[0x40]; 2463 2464 u8 dbr_addr[0x40]; 2465 }; 2466 2467 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2468 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2469 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2470 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2471 u8 reserved_0[0x800]; 2472 }; 2473 2474 struct mlx5_ifc_query_adapter_param_block_bits { 2475 u8 reserved_0[0xc0]; 2476 2477 u8 reserved_1[0x8]; 2478 u8 ieee_vendor_id[0x18]; 2479 2480 u8 reserved_2[0x10]; 2481 u8 vsd_vendor_id[0x10]; 2482 2483 u8 vsd[208][0x8]; 2484 2485 u8 vsd_contd_psid[16][0x8]; 2486 }; 2487 2488 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2489 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2490 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2491 u8 reserved_0[0x20]; 2492 }; 2493 2494 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2495 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2496 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2497 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2498 u8 reserved_0[0x20]; 2499 }; 2500 2501 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2502 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2503 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2504 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2505 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2506 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2507 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2508 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 2509 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 2510 u8 reserved_0[0x7c0]; 2511 }; 2512 2513 union mlx5_ifc_event_auto_bits { 2514 struct mlx5_ifc_comp_event_bits comp_event; 2515 struct mlx5_ifc_dct_events_bits dct_events; 2516 struct mlx5_ifc_qp_events_bits qp_events; 2517 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2518 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2519 struct mlx5_ifc_cq_error_bits cq_error; 2520 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2521 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2522 struct mlx5_ifc_gpio_event_bits gpio_event; 2523 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2524 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2525 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2526 u8 reserved_0[0xe0]; 2527 }; 2528 2529 struct mlx5_ifc_health_buffer_bits { 2530 u8 reserved_0[0x100]; 2531 2532 u8 assert_existptr[0x20]; 2533 2534 u8 assert_callra[0x20]; 2535 2536 u8 reserved_1[0x40]; 2537 2538 u8 fw_version[0x20]; 2539 2540 u8 hw_id[0x20]; 2541 2542 u8 reserved_2[0x20]; 2543 2544 u8 irisc_index[0x8]; 2545 u8 synd[0x8]; 2546 u8 ext_synd[0x10]; 2547 }; 2548 2549 struct mlx5_ifc_register_loopback_control_bits { 2550 u8 no_lb[0x1]; 2551 u8 reserved_0[0x7]; 2552 u8 port[0x8]; 2553 u8 reserved_1[0x10]; 2554 2555 u8 reserved_2[0x60]; 2556 }; 2557 2558 struct mlx5_ifc_teardown_hca_out_bits { 2559 u8 status[0x8]; 2560 u8 reserved_0[0x18]; 2561 2562 u8 syndrome[0x20]; 2563 2564 u8 reserved_1[0x40]; 2565 }; 2566 2567 enum { 2568 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 2569 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 2570 }; 2571 2572 struct mlx5_ifc_teardown_hca_in_bits { 2573 u8 opcode[0x10]; 2574 u8 reserved_0[0x10]; 2575 2576 u8 reserved_1[0x10]; 2577 u8 op_mod[0x10]; 2578 2579 u8 reserved_2[0x10]; 2580 u8 profile[0x10]; 2581 2582 u8 reserved_3[0x20]; 2583 }; 2584 2585 struct mlx5_ifc_sqerr2rts_qp_out_bits { 2586 u8 status[0x8]; 2587 u8 reserved_0[0x18]; 2588 2589 u8 syndrome[0x20]; 2590 2591 u8 reserved_1[0x40]; 2592 }; 2593 2594 struct mlx5_ifc_sqerr2rts_qp_in_bits { 2595 u8 opcode[0x10]; 2596 u8 reserved_0[0x10]; 2597 2598 u8 reserved_1[0x10]; 2599 u8 op_mod[0x10]; 2600 2601 u8 reserved_2[0x8]; 2602 u8 qpn[0x18]; 2603 2604 u8 reserved_3[0x20]; 2605 2606 u8 opt_param_mask[0x20]; 2607 2608 u8 reserved_4[0x20]; 2609 2610 struct mlx5_ifc_qpc_bits qpc; 2611 2612 u8 reserved_5[0x80]; 2613 }; 2614 2615 struct mlx5_ifc_sqd2rts_qp_out_bits { 2616 u8 status[0x8]; 2617 u8 reserved_0[0x18]; 2618 2619 u8 syndrome[0x20]; 2620 2621 u8 reserved_1[0x40]; 2622 }; 2623 2624 struct mlx5_ifc_sqd2rts_qp_in_bits { 2625 u8 opcode[0x10]; 2626 u8 reserved_0[0x10]; 2627 2628 u8 reserved_1[0x10]; 2629 u8 op_mod[0x10]; 2630 2631 u8 reserved_2[0x8]; 2632 u8 qpn[0x18]; 2633 2634 u8 reserved_3[0x20]; 2635 2636 u8 opt_param_mask[0x20]; 2637 2638 u8 reserved_4[0x20]; 2639 2640 struct mlx5_ifc_qpc_bits qpc; 2641 2642 u8 reserved_5[0x80]; 2643 }; 2644 2645 struct mlx5_ifc_set_roce_address_out_bits { 2646 u8 status[0x8]; 2647 u8 reserved_0[0x18]; 2648 2649 u8 syndrome[0x20]; 2650 2651 u8 reserved_1[0x40]; 2652 }; 2653 2654 struct mlx5_ifc_set_roce_address_in_bits { 2655 u8 opcode[0x10]; 2656 u8 reserved_0[0x10]; 2657 2658 u8 reserved_1[0x10]; 2659 u8 op_mod[0x10]; 2660 2661 u8 roce_address_index[0x10]; 2662 u8 reserved_2[0x10]; 2663 2664 u8 reserved_3[0x20]; 2665 2666 struct mlx5_ifc_roce_addr_layout_bits roce_address; 2667 }; 2668 2669 struct mlx5_ifc_set_mad_demux_out_bits { 2670 u8 status[0x8]; 2671 u8 reserved_0[0x18]; 2672 2673 u8 syndrome[0x20]; 2674 2675 u8 reserved_1[0x40]; 2676 }; 2677 2678 enum { 2679 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 2680 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 2681 }; 2682 2683 struct mlx5_ifc_set_mad_demux_in_bits { 2684 u8 opcode[0x10]; 2685 u8 reserved_0[0x10]; 2686 2687 u8 reserved_1[0x10]; 2688 u8 op_mod[0x10]; 2689 2690 u8 reserved_2[0x20]; 2691 2692 u8 reserved_3[0x6]; 2693 u8 demux_mode[0x2]; 2694 u8 reserved_4[0x18]; 2695 }; 2696 2697 struct mlx5_ifc_set_l2_table_entry_out_bits { 2698 u8 status[0x8]; 2699 u8 reserved_0[0x18]; 2700 2701 u8 syndrome[0x20]; 2702 2703 u8 reserved_1[0x40]; 2704 }; 2705 2706 struct mlx5_ifc_set_l2_table_entry_in_bits { 2707 u8 opcode[0x10]; 2708 u8 reserved_0[0x10]; 2709 2710 u8 reserved_1[0x10]; 2711 u8 op_mod[0x10]; 2712 2713 u8 reserved_2[0x60]; 2714 2715 u8 reserved_3[0x8]; 2716 u8 table_index[0x18]; 2717 2718 u8 reserved_4[0x20]; 2719 2720 u8 reserved_5[0x13]; 2721 u8 vlan_valid[0x1]; 2722 u8 vlan[0xc]; 2723 2724 struct mlx5_ifc_mac_address_layout_bits mac_address; 2725 2726 u8 reserved_6[0xc0]; 2727 }; 2728 2729 struct mlx5_ifc_set_issi_out_bits { 2730 u8 status[0x8]; 2731 u8 reserved_0[0x18]; 2732 2733 u8 syndrome[0x20]; 2734 2735 u8 reserved_1[0x40]; 2736 }; 2737 2738 struct mlx5_ifc_set_issi_in_bits { 2739 u8 opcode[0x10]; 2740 u8 reserved_0[0x10]; 2741 2742 u8 reserved_1[0x10]; 2743 u8 op_mod[0x10]; 2744 2745 u8 reserved_2[0x10]; 2746 u8 current_issi[0x10]; 2747 2748 u8 reserved_3[0x20]; 2749 }; 2750 2751 struct mlx5_ifc_set_hca_cap_out_bits { 2752 u8 status[0x8]; 2753 u8 reserved_0[0x18]; 2754 2755 u8 syndrome[0x20]; 2756 2757 u8 reserved_1[0x40]; 2758 }; 2759 2760 struct mlx5_ifc_set_hca_cap_in_bits { 2761 u8 opcode[0x10]; 2762 u8 reserved_0[0x10]; 2763 2764 u8 reserved_1[0x10]; 2765 u8 op_mod[0x10]; 2766 2767 u8 reserved_2[0x40]; 2768 2769 union mlx5_ifc_hca_cap_union_bits capability; 2770 }; 2771 2772 struct mlx5_ifc_set_fte_out_bits { 2773 u8 status[0x8]; 2774 u8 reserved_0[0x18]; 2775 2776 u8 syndrome[0x20]; 2777 2778 u8 reserved_1[0x40]; 2779 }; 2780 2781 struct mlx5_ifc_set_fte_in_bits { 2782 u8 opcode[0x10]; 2783 u8 reserved_0[0x10]; 2784 2785 u8 reserved_1[0x10]; 2786 u8 op_mod[0x10]; 2787 2788 u8 reserved_2[0x40]; 2789 2790 u8 table_type[0x8]; 2791 u8 reserved_3[0x18]; 2792 2793 u8 reserved_4[0x8]; 2794 u8 table_id[0x18]; 2795 2796 u8 reserved_5[0x40]; 2797 2798 u8 flow_index[0x20]; 2799 2800 u8 reserved_6[0xe0]; 2801 2802 struct mlx5_ifc_flow_context_bits flow_context; 2803 }; 2804 2805 struct mlx5_ifc_rts2rts_qp_out_bits { 2806 u8 status[0x8]; 2807 u8 reserved_0[0x18]; 2808 2809 u8 syndrome[0x20]; 2810 2811 u8 reserved_1[0x40]; 2812 }; 2813 2814 struct mlx5_ifc_rts2rts_qp_in_bits { 2815 u8 opcode[0x10]; 2816 u8 reserved_0[0x10]; 2817 2818 u8 reserved_1[0x10]; 2819 u8 op_mod[0x10]; 2820 2821 u8 reserved_2[0x8]; 2822 u8 qpn[0x18]; 2823 2824 u8 reserved_3[0x20]; 2825 2826 u8 opt_param_mask[0x20]; 2827 2828 u8 reserved_4[0x20]; 2829 2830 struct mlx5_ifc_qpc_bits qpc; 2831 2832 u8 reserved_5[0x80]; 2833 }; 2834 2835 struct mlx5_ifc_rtr2rts_qp_out_bits { 2836 u8 status[0x8]; 2837 u8 reserved_0[0x18]; 2838 2839 u8 syndrome[0x20]; 2840 2841 u8 reserved_1[0x40]; 2842 }; 2843 2844 struct mlx5_ifc_rtr2rts_qp_in_bits { 2845 u8 opcode[0x10]; 2846 u8 reserved_0[0x10]; 2847 2848 u8 reserved_1[0x10]; 2849 u8 op_mod[0x10]; 2850 2851 u8 reserved_2[0x8]; 2852 u8 qpn[0x18]; 2853 2854 u8 reserved_3[0x20]; 2855 2856 u8 opt_param_mask[0x20]; 2857 2858 u8 reserved_4[0x20]; 2859 2860 struct mlx5_ifc_qpc_bits qpc; 2861 2862 u8 reserved_5[0x80]; 2863 }; 2864 2865 struct mlx5_ifc_rst2init_qp_out_bits { 2866 u8 status[0x8]; 2867 u8 reserved_0[0x18]; 2868 2869 u8 syndrome[0x20]; 2870 2871 u8 reserved_1[0x40]; 2872 }; 2873 2874 struct mlx5_ifc_rst2init_qp_in_bits { 2875 u8 opcode[0x10]; 2876 u8 reserved_0[0x10]; 2877 2878 u8 reserved_1[0x10]; 2879 u8 op_mod[0x10]; 2880 2881 u8 reserved_2[0x8]; 2882 u8 qpn[0x18]; 2883 2884 u8 reserved_3[0x20]; 2885 2886 u8 opt_param_mask[0x20]; 2887 2888 u8 reserved_4[0x20]; 2889 2890 struct mlx5_ifc_qpc_bits qpc; 2891 2892 u8 reserved_5[0x80]; 2893 }; 2894 2895 struct mlx5_ifc_query_xrc_srq_out_bits { 2896 u8 status[0x8]; 2897 u8 reserved_0[0x18]; 2898 2899 u8 syndrome[0x20]; 2900 2901 u8 reserved_1[0x40]; 2902 2903 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 2904 2905 u8 reserved_2[0x600]; 2906 2907 u8 pas[0][0x40]; 2908 }; 2909 2910 struct mlx5_ifc_query_xrc_srq_in_bits { 2911 u8 opcode[0x10]; 2912 u8 reserved_0[0x10]; 2913 2914 u8 reserved_1[0x10]; 2915 u8 op_mod[0x10]; 2916 2917 u8 reserved_2[0x8]; 2918 u8 xrc_srqn[0x18]; 2919 2920 u8 reserved_3[0x20]; 2921 }; 2922 2923 enum { 2924 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 2925 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 2926 }; 2927 2928 struct mlx5_ifc_query_vport_state_out_bits { 2929 u8 status[0x8]; 2930 u8 reserved_0[0x18]; 2931 2932 u8 syndrome[0x20]; 2933 2934 u8 reserved_1[0x20]; 2935 2936 u8 reserved_2[0x18]; 2937 u8 admin_state[0x4]; 2938 u8 state[0x4]; 2939 }; 2940 2941 enum { 2942 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 2943 }; 2944 2945 struct mlx5_ifc_query_vport_state_in_bits { 2946 u8 opcode[0x10]; 2947 u8 reserved_0[0x10]; 2948 2949 u8 reserved_1[0x10]; 2950 u8 op_mod[0x10]; 2951 2952 u8 other_vport[0x1]; 2953 u8 reserved_2[0xf]; 2954 u8 vport_number[0x10]; 2955 2956 u8 reserved_3[0x20]; 2957 }; 2958 2959 struct mlx5_ifc_query_vport_counter_out_bits { 2960 u8 status[0x8]; 2961 u8 reserved_0[0x18]; 2962 2963 u8 syndrome[0x20]; 2964 2965 u8 reserved_1[0x40]; 2966 2967 struct mlx5_ifc_traffic_counter_bits received_errors; 2968 2969 struct mlx5_ifc_traffic_counter_bits transmit_errors; 2970 2971 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 2972 2973 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 2974 2975 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 2976 2977 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 2978 2979 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 2980 2981 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 2982 2983 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 2984 2985 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 2986 2987 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 2988 2989 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 2990 2991 u8 reserved_2[0xa00]; 2992 }; 2993 2994 enum { 2995 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 2996 }; 2997 2998 struct mlx5_ifc_query_vport_counter_in_bits { 2999 u8 opcode[0x10]; 3000 u8 reserved_0[0x10]; 3001 3002 u8 reserved_1[0x10]; 3003 u8 op_mod[0x10]; 3004 3005 u8 other_vport[0x1]; 3006 u8 reserved_2[0xf]; 3007 u8 vport_number[0x10]; 3008 3009 u8 reserved_3[0x60]; 3010 3011 u8 clear[0x1]; 3012 u8 reserved_4[0x1f]; 3013 3014 u8 reserved_5[0x20]; 3015 }; 3016 3017 struct mlx5_ifc_query_tis_out_bits { 3018 u8 status[0x8]; 3019 u8 reserved_0[0x18]; 3020 3021 u8 syndrome[0x20]; 3022 3023 u8 reserved_1[0x40]; 3024 3025 struct mlx5_ifc_tisc_bits tis_context; 3026 }; 3027 3028 struct mlx5_ifc_query_tis_in_bits { 3029 u8 opcode[0x10]; 3030 u8 reserved_0[0x10]; 3031 3032 u8 reserved_1[0x10]; 3033 u8 op_mod[0x10]; 3034 3035 u8 reserved_2[0x8]; 3036 u8 tisn[0x18]; 3037 3038 u8 reserved_3[0x20]; 3039 }; 3040 3041 struct mlx5_ifc_query_tir_out_bits { 3042 u8 status[0x8]; 3043 u8 reserved_0[0x18]; 3044 3045 u8 syndrome[0x20]; 3046 3047 u8 reserved_1[0xc0]; 3048 3049 struct mlx5_ifc_tirc_bits tir_context; 3050 }; 3051 3052 struct mlx5_ifc_query_tir_in_bits { 3053 u8 opcode[0x10]; 3054 u8 reserved_0[0x10]; 3055 3056 u8 reserved_1[0x10]; 3057 u8 op_mod[0x10]; 3058 3059 u8 reserved_2[0x8]; 3060 u8 tirn[0x18]; 3061 3062 u8 reserved_3[0x20]; 3063 }; 3064 3065 struct mlx5_ifc_query_srq_out_bits { 3066 u8 status[0x8]; 3067 u8 reserved_0[0x18]; 3068 3069 u8 syndrome[0x20]; 3070 3071 u8 reserved_1[0x40]; 3072 3073 struct mlx5_ifc_srqc_bits srq_context_entry; 3074 3075 u8 reserved_2[0x600]; 3076 3077 u8 pas[0][0x40]; 3078 }; 3079 3080 struct mlx5_ifc_query_srq_in_bits { 3081 u8 opcode[0x10]; 3082 u8 reserved_0[0x10]; 3083 3084 u8 reserved_1[0x10]; 3085 u8 op_mod[0x10]; 3086 3087 u8 reserved_2[0x8]; 3088 u8 srqn[0x18]; 3089 3090 u8 reserved_3[0x20]; 3091 }; 3092 3093 struct mlx5_ifc_query_sq_out_bits { 3094 u8 status[0x8]; 3095 u8 reserved_0[0x18]; 3096 3097 u8 syndrome[0x20]; 3098 3099 u8 reserved_1[0xc0]; 3100 3101 struct mlx5_ifc_sqc_bits sq_context; 3102 }; 3103 3104 struct mlx5_ifc_query_sq_in_bits { 3105 u8 opcode[0x10]; 3106 u8 reserved_0[0x10]; 3107 3108 u8 reserved_1[0x10]; 3109 u8 op_mod[0x10]; 3110 3111 u8 reserved_2[0x8]; 3112 u8 sqn[0x18]; 3113 3114 u8 reserved_3[0x20]; 3115 }; 3116 3117 struct mlx5_ifc_query_special_contexts_out_bits { 3118 u8 status[0x8]; 3119 u8 reserved_0[0x18]; 3120 3121 u8 syndrome[0x20]; 3122 3123 u8 reserved_1[0x20]; 3124 3125 u8 resd_lkey[0x20]; 3126 }; 3127 3128 struct mlx5_ifc_query_special_contexts_in_bits { 3129 u8 opcode[0x10]; 3130 u8 reserved_0[0x10]; 3131 3132 u8 reserved_1[0x10]; 3133 u8 op_mod[0x10]; 3134 3135 u8 reserved_2[0x40]; 3136 }; 3137 3138 struct mlx5_ifc_query_rqt_out_bits { 3139 u8 status[0x8]; 3140 u8 reserved_0[0x18]; 3141 3142 u8 syndrome[0x20]; 3143 3144 u8 reserved_1[0xc0]; 3145 3146 struct mlx5_ifc_rqtc_bits rqt_context; 3147 }; 3148 3149 struct mlx5_ifc_query_rqt_in_bits { 3150 u8 opcode[0x10]; 3151 u8 reserved_0[0x10]; 3152 3153 u8 reserved_1[0x10]; 3154 u8 op_mod[0x10]; 3155 3156 u8 reserved_2[0x8]; 3157 u8 rqtn[0x18]; 3158 3159 u8 reserved_3[0x20]; 3160 }; 3161 3162 struct mlx5_ifc_query_rq_out_bits { 3163 u8 status[0x8]; 3164 u8 reserved_0[0x18]; 3165 3166 u8 syndrome[0x20]; 3167 3168 u8 reserved_1[0xc0]; 3169 3170 struct mlx5_ifc_rqc_bits rq_context; 3171 }; 3172 3173 struct mlx5_ifc_query_rq_in_bits { 3174 u8 opcode[0x10]; 3175 u8 reserved_0[0x10]; 3176 3177 u8 reserved_1[0x10]; 3178 u8 op_mod[0x10]; 3179 3180 u8 reserved_2[0x8]; 3181 u8 rqn[0x18]; 3182 3183 u8 reserved_3[0x20]; 3184 }; 3185 3186 struct mlx5_ifc_query_roce_address_out_bits { 3187 u8 status[0x8]; 3188 u8 reserved_0[0x18]; 3189 3190 u8 syndrome[0x20]; 3191 3192 u8 reserved_1[0x40]; 3193 3194 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3195 }; 3196 3197 struct mlx5_ifc_query_roce_address_in_bits { 3198 u8 opcode[0x10]; 3199 u8 reserved_0[0x10]; 3200 3201 u8 reserved_1[0x10]; 3202 u8 op_mod[0x10]; 3203 3204 u8 roce_address_index[0x10]; 3205 u8 reserved_2[0x10]; 3206 3207 u8 reserved_3[0x20]; 3208 }; 3209 3210 struct mlx5_ifc_query_rmp_out_bits { 3211 u8 status[0x8]; 3212 u8 reserved_0[0x18]; 3213 3214 u8 syndrome[0x20]; 3215 3216 u8 reserved_1[0xc0]; 3217 3218 struct mlx5_ifc_rmpc_bits rmp_context; 3219 }; 3220 3221 struct mlx5_ifc_query_rmp_in_bits { 3222 u8 opcode[0x10]; 3223 u8 reserved_0[0x10]; 3224 3225 u8 reserved_1[0x10]; 3226 u8 op_mod[0x10]; 3227 3228 u8 reserved_2[0x8]; 3229 u8 rmpn[0x18]; 3230 3231 u8 reserved_3[0x20]; 3232 }; 3233 3234 struct mlx5_ifc_query_qp_out_bits { 3235 u8 status[0x8]; 3236 u8 reserved_0[0x18]; 3237 3238 u8 syndrome[0x20]; 3239 3240 u8 reserved_1[0x40]; 3241 3242 u8 opt_param_mask[0x20]; 3243 3244 u8 reserved_2[0x20]; 3245 3246 struct mlx5_ifc_qpc_bits qpc; 3247 3248 u8 reserved_3[0x80]; 3249 3250 u8 pas[0][0x40]; 3251 }; 3252 3253 struct mlx5_ifc_query_qp_in_bits { 3254 u8 opcode[0x10]; 3255 u8 reserved_0[0x10]; 3256 3257 u8 reserved_1[0x10]; 3258 u8 op_mod[0x10]; 3259 3260 u8 reserved_2[0x8]; 3261 u8 qpn[0x18]; 3262 3263 u8 reserved_3[0x20]; 3264 }; 3265 3266 struct mlx5_ifc_query_q_counter_out_bits { 3267 u8 status[0x8]; 3268 u8 reserved_0[0x18]; 3269 3270 u8 syndrome[0x20]; 3271 3272 u8 reserved_1[0x40]; 3273 3274 u8 rx_write_requests[0x20]; 3275 3276 u8 reserved_2[0x20]; 3277 3278 u8 rx_read_requests[0x20]; 3279 3280 u8 reserved_3[0x20]; 3281 3282 u8 rx_atomic_requests[0x20]; 3283 3284 u8 reserved_4[0x20]; 3285 3286 u8 rx_dct_connect[0x20]; 3287 3288 u8 reserved_5[0x20]; 3289 3290 u8 out_of_buffer[0x20]; 3291 3292 u8 reserved_6[0x20]; 3293 3294 u8 out_of_sequence[0x20]; 3295 3296 u8 reserved_7[0x620]; 3297 }; 3298 3299 struct mlx5_ifc_query_q_counter_in_bits { 3300 u8 opcode[0x10]; 3301 u8 reserved_0[0x10]; 3302 3303 u8 reserved_1[0x10]; 3304 u8 op_mod[0x10]; 3305 3306 u8 reserved_2[0x80]; 3307 3308 u8 clear[0x1]; 3309 u8 reserved_3[0x1f]; 3310 3311 u8 reserved_4[0x18]; 3312 u8 counter_set_id[0x8]; 3313 }; 3314 3315 struct mlx5_ifc_query_pages_out_bits { 3316 u8 status[0x8]; 3317 u8 reserved_0[0x18]; 3318 3319 u8 syndrome[0x20]; 3320 3321 u8 reserved_1[0x10]; 3322 u8 function_id[0x10]; 3323 3324 u8 num_pages[0x20]; 3325 }; 3326 3327 enum { 3328 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3329 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3330 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3331 }; 3332 3333 struct mlx5_ifc_query_pages_in_bits { 3334 u8 opcode[0x10]; 3335 u8 reserved_0[0x10]; 3336 3337 u8 reserved_1[0x10]; 3338 u8 op_mod[0x10]; 3339 3340 u8 reserved_2[0x10]; 3341 u8 function_id[0x10]; 3342 3343 u8 reserved_3[0x20]; 3344 }; 3345 3346 struct mlx5_ifc_query_nic_vport_context_out_bits { 3347 u8 status[0x8]; 3348 u8 reserved_0[0x18]; 3349 3350 u8 syndrome[0x20]; 3351 3352 u8 reserved_1[0x40]; 3353 3354 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3355 }; 3356 3357 struct mlx5_ifc_query_nic_vport_context_in_bits { 3358 u8 opcode[0x10]; 3359 u8 reserved_0[0x10]; 3360 3361 u8 reserved_1[0x10]; 3362 u8 op_mod[0x10]; 3363 3364 u8 other_vport[0x1]; 3365 u8 reserved_2[0xf]; 3366 u8 vport_number[0x10]; 3367 3368 u8 reserved_3[0x5]; 3369 u8 allowed_list_type[0x3]; 3370 u8 reserved_4[0x18]; 3371 }; 3372 3373 struct mlx5_ifc_query_mkey_out_bits { 3374 u8 status[0x8]; 3375 u8 reserved_0[0x18]; 3376 3377 u8 syndrome[0x20]; 3378 3379 u8 reserved_1[0x40]; 3380 3381 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 3382 3383 u8 reserved_2[0x600]; 3384 3385 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 3386 3387 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 3388 }; 3389 3390 struct mlx5_ifc_query_mkey_in_bits { 3391 u8 opcode[0x10]; 3392 u8 reserved_0[0x10]; 3393 3394 u8 reserved_1[0x10]; 3395 u8 op_mod[0x10]; 3396 3397 u8 reserved_2[0x8]; 3398 u8 mkey_index[0x18]; 3399 3400 u8 pg_access[0x1]; 3401 u8 reserved_3[0x1f]; 3402 }; 3403 3404 struct mlx5_ifc_query_mad_demux_out_bits { 3405 u8 status[0x8]; 3406 u8 reserved_0[0x18]; 3407 3408 u8 syndrome[0x20]; 3409 3410 u8 reserved_1[0x40]; 3411 3412 u8 mad_dumux_parameters_block[0x20]; 3413 }; 3414 3415 struct mlx5_ifc_query_mad_demux_in_bits { 3416 u8 opcode[0x10]; 3417 u8 reserved_0[0x10]; 3418 3419 u8 reserved_1[0x10]; 3420 u8 op_mod[0x10]; 3421 3422 u8 reserved_2[0x40]; 3423 }; 3424 3425 struct mlx5_ifc_query_l2_table_entry_out_bits { 3426 u8 status[0x8]; 3427 u8 reserved_0[0x18]; 3428 3429 u8 syndrome[0x20]; 3430 3431 u8 reserved_1[0xa0]; 3432 3433 u8 reserved_2[0x13]; 3434 u8 vlan_valid[0x1]; 3435 u8 vlan[0xc]; 3436 3437 struct mlx5_ifc_mac_address_layout_bits mac_address; 3438 3439 u8 reserved_3[0xc0]; 3440 }; 3441 3442 struct mlx5_ifc_query_l2_table_entry_in_bits { 3443 u8 opcode[0x10]; 3444 u8 reserved_0[0x10]; 3445 3446 u8 reserved_1[0x10]; 3447 u8 op_mod[0x10]; 3448 3449 u8 reserved_2[0x60]; 3450 3451 u8 reserved_3[0x8]; 3452 u8 table_index[0x18]; 3453 3454 u8 reserved_4[0x140]; 3455 }; 3456 3457 struct mlx5_ifc_query_issi_out_bits { 3458 u8 status[0x8]; 3459 u8 reserved_0[0x18]; 3460 3461 u8 syndrome[0x20]; 3462 3463 u8 reserved_1[0x10]; 3464 u8 current_issi[0x10]; 3465 3466 u8 reserved_2[0xa0]; 3467 3468 u8 supported_issi_reserved[76][0x8]; 3469 u8 supported_issi_dw0[0x20]; 3470 }; 3471 3472 struct mlx5_ifc_query_issi_in_bits { 3473 u8 opcode[0x10]; 3474 u8 reserved_0[0x10]; 3475 3476 u8 reserved_1[0x10]; 3477 u8 op_mod[0x10]; 3478 3479 u8 reserved_2[0x40]; 3480 }; 3481 3482 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 3483 u8 status[0x8]; 3484 u8 reserved_0[0x18]; 3485 3486 u8 syndrome[0x20]; 3487 3488 u8 reserved_1[0x40]; 3489 3490 struct mlx5_ifc_pkey_bits pkey[0]; 3491 }; 3492 3493 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 3494 u8 opcode[0x10]; 3495 u8 reserved_0[0x10]; 3496 3497 u8 reserved_1[0x10]; 3498 u8 op_mod[0x10]; 3499 3500 u8 other_vport[0x1]; 3501 u8 reserved_2[0xb]; 3502 u8 port_num[0x4]; 3503 u8 vport_number[0x10]; 3504 3505 u8 reserved_3[0x10]; 3506 u8 pkey_index[0x10]; 3507 }; 3508 3509 struct mlx5_ifc_query_hca_vport_gid_out_bits { 3510 u8 status[0x8]; 3511 u8 reserved_0[0x18]; 3512 3513 u8 syndrome[0x20]; 3514 3515 u8 reserved_1[0x20]; 3516 3517 u8 gids_num[0x10]; 3518 u8 reserved_2[0x10]; 3519 3520 struct mlx5_ifc_array128_auto_bits gid[0]; 3521 }; 3522 3523 struct mlx5_ifc_query_hca_vport_gid_in_bits { 3524 u8 opcode[0x10]; 3525 u8 reserved_0[0x10]; 3526 3527 u8 reserved_1[0x10]; 3528 u8 op_mod[0x10]; 3529 3530 u8 other_vport[0x1]; 3531 u8 reserved_2[0xb]; 3532 u8 port_num[0x4]; 3533 u8 vport_number[0x10]; 3534 3535 u8 reserved_3[0x10]; 3536 u8 gid_index[0x10]; 3537 }; 3538 3539 struct mlx5_ifc_query_hca_vport_context_out_bits { 3540 u8 status[0x8]; 3541 u8 reserved_0[0x18]; 3542 3543 u8 syndrome[0x20]; 3544 3545 u8 reserved_1[0x40]; 3546 3547 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 3548 }; 3549 3550 struct mlx5_ifc_query_hca_vport_context_in_bits { 3551 u8 opcode[0x10]; 3552 u8 reserved_0[0x10]; 3553 3554 u8 reserved_1[0x10]; 3555 u8 op_mod[0x10]; 3556 3557 u8 other_vport[0x1]; 3558 u8 reserved_2[0xb]; 3559 u8 port_num[0x4]; 3560 u8 vport_number[0x10]; 3561 3562 u8 reserved_3[0x20]; 3563 }; 3564 3565 struct mlx5_ifc_query_hca_cap_out_bits { 3566 u8 status[0x8]; 3567 u8 reserved_0[0x18]; 3568 3569 u8 syndrome[0x20]; 3570 3571 u8 reserved_1[0x40]; 3572 3573 union mlx5_ifc_hca_cap_union_bits capability; 3574 }; 3575 3576 struct mlx5_ifc_query_hca_cap_in_bits { 3577 u8 opcode[0x10]; 3578 u8 reserved_0[0x10]; 3579 3580 u8 reserved_1[0x10]; 3581 u8 op_mod[0x10]; 3582 3583 u8 reserved_2[0x40]; 3584 }; 3585 3586 struct mlx5_ifc_query_flow_table_out_bits { 3587 u8 status[0x8]; 3588 u8 reserved_0[0x18]; 3589 3590 u8 syndrome[0x20]; 3591 3592 u8 reserved_1[0x80]; 3593 3594 u8 reserved_2[0x8]; 3595 u8 level[0x8]; 3596 u8 reserved_3[0x8]; 3597 u8 log_size[0x8]; 3598 3599 u8 reserved_4[0x120]; 3600 }; 3601 3602 struct mlx5_ifc_query_flow_table_in_bits { 3603 u8 opcode[0x10]; 3604 u8 reserved_0[0x10]; 3605 3606 u8 reserved_1[0x10]; 3607 u8 op_mod[0x10]; 3608 3609 u8 reserved_2[0x40]; 3610 3611 u8 table_type[0x8]; 3612 u8 reserved_3[0x18]; 3613 3614 u8 reserved_4[0x8]; 3615 u8 table_id[0x18]; 3616 3617 u8 reserved_5[0x140]; 3618 }; 3619 3620 struct mlx5_ifc_query_fte_out_bits { 3621 u8 status[0x8]; 3622 u8 reserved_0[0x18]; 3623 3624 u8 syndrome[0x20]; 3625 3626 u8 reserved_1[0x1c0]; 3627 3628 struct mlx5_ifc_flow_context_bits flow_context; 3629 }; 3630 3631 struct mlx5_ifc_query_fte_in_bits { 3632 u8 opcode[0x10]; 3633 u8 reserved_0[0x10]; 3634 3635 u8 reserved_1[0x10]; 3636 u8 op_mod[0x10]; 3637 3638 u8 reserved_2[0x40]; 3639 3640 u8 table_type[0x8]; 3641 u8 reserved_3[0x18]; 3642 3643 u8 reserved_4[0x8]; 3644 u8 table_id[0x18]; 3645 3646 u8 reserved_5[0x40]; 3647 3648 u8 flow_index[0x20]; 3649 3650 u8 reserved_6[0xe0]; 3651 }; 3652 3653 enum { 3654 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 3655 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 3656 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 3657 }; 3658 3659 struct mlx5_ifc_query_flow_group_out_bits { 3660 u8 status[0x8]; 3661 u8 reserved_0[0x18]; 3662 3663 u8 syndrome[0x20]; 3664 3665 u8 reserved_1[0xa0]; 3666 3667 u8 start_flow_index[0x20]; 3668 3669 u8 reserved_2[0x20]; 3670 3671 u8 end_flow_index[0x20]; 3672 3673 u8 reserved_3[0xa0]; 3674 3675 u8 reserved_4[0x18]; 3676 u8 match_criteria_enable[0x8]; 3677 3678 struct mlx5_ifc_fte_match_param_bits match_criteria; 3679 3680 u8 reserved_5[0xe00]; 3681 }; 3682 3683 struct mlx5_ifc_query_flow_group_in_bits { 3684 u8 opcode[0x10]; 3685 u8 reserved_0[0x10]; 3686 3687 u8 reserved_1[0x10]; 3688 u8 op_mod[0x10]; 3689 3690 u8 reserved_2[0x40]; 3691 3692 u8 table_type[0x8]; 3693 u8 reserved_3[0x18]; 3694 3695 u8 reserved_4[0x8]; 3696 u8 table_id[0x18]; 3697 3698 u8 group_id[0x20]; 3699 3700 u8 reserved_5[0x120]; 3701 }; 3702 3703 struct mlx5_ifc_query_eq_out_bits { 3704 u8 status[0x8]; 3705 u8 reserved_0[0x18]; 3706 3707 u8 syndrome[0x20]; 3708 3709 u8 reserved_1[0x40]; 3710 3711 struct mlx5_ifc_eqc_bits eq_context_entry; 3712 3713 u8 reserved_2[0x40]; 3714 3715 u8 event_bitmask[0x40]; 3716 3717 u8 reserved_3[0x580]; 3718 3719 u8 pas[0][0x40]; 3720 }; 3721 3722 struct mlx5_ifc_query_eq_in_bits { 3723 u8 opcode[0x10]; 3724 u8 reserved_0[0x10]; 3725 3726 u8 reserved_1[0x10]; 3727 u8 op_mod[0x10]; 3728 3729 u8 reserved_2[0x18]; 3730 u8 eq_number[0x8]; 3731 3732 u8 reserved_3[0x20]; 3733 }; 3734 3735 struct mlx5_ifc_query_dct_out_bits { 3736 u8 status[0x8]; 3737 u8 reserved_0[0x18]; 3738 3739 u8 syndrome[0x20]; 3740 3741 u8 reserved_1[0x40]; 3742 3743 struct mlx5_ifc_dctc_bits dct_context_entry; 3744 3745 u8 reserved_2[0x180]; 3746 }; 3747 3748 struct mlx5_ifc_query_dct_in_bits { 3749 u8 opcode[0x10]; 3750 u8 reserved_0[0x10]; 3751 3752 u8 reserved_1[0x10]; 3753 u8 op_mod[0x10]; 3754 3755 u8 reserved_2[0x8]; 3756 u8 dctn[0x18]; 3757 3758 u8 reserved_3[0x20]; 3759 }; 3760 3761 struct mlx5_ifc_query_cq_out_bits { 3762 u8 status[0x8]; 3763 u8 reserved_0[0x18]; 3764 3765 u8 syndrome[0x20]; 3766 3767 u8 reserved_1[0x40]; 3768 3769 struct mlx5_ifc_cqc_bits cq_context; 3770 3771 u8 reserved_2[0x600]; 3772 3773 u8 pas[0][0x40]; 3774 }; 3775 3776 struct mlx5_ifc_query_cq_in_bits { 3777 u8 opcode[0x10]; 3778 u8 reserved_0[0x10]; 3779 3780 u8 reserved_1[0x10]; 3781 u8 op_mod[0x10]; 3782 3783 u8 reserved_2[0x8]; 3784 u8 cqn[0x18]; 3785 3786 u8 reserved_3[0x20]; 3787 }; 3788 3789 struct mlx5_ifc_query_cong_status_out_bits { 3790 u8 status[0x8]; 3791 u8 reserved_0[0x18]; 3792 3793 u8 syndrome[0x20]; 3794 3795 u8 reserved_1[0x20]; 3796 3797 u8 enable[0x1]; 3798 u8 tag_enable[0x1]; 3799 u8 reserved_2[0x1e]; 3800 }; 3801 3802 struct mlx5_ifc_query_cong_status_in_bits { 3803 u8 opcode[0x10]; 3804 u8 reserved_0[0x10]; 3805 3806 u8 reserved_1[0x10]; 3807 u8 op_mod[0x10]; 3808 3809 u8 reserved_2[0x18]; 3810 u8 priority[0x4]; 3811 u8 cong_protocol[0x4]; 3812 3813 u8 reserved_3[0x20]; 3814 }; 3815 3816 struct mlx5_ifc_query_cong_statistics_out_bits { 3817 u8 status[0x8]; 3818 u8 reserved_0[0x18]; 3819 3820 u8 syndrome[0x20]; 3821 3822 u8 reserved_1[0x40]; 3823 3824 u8 cur_flows[0x20]; 3825 3826 u8 sum_flows[0x20]; 3827 3828 u8 cnp_ignored_high[0x20]; 3829 3830 u8 cnp_ignored_low[0x20]; 3831 3832 u8 cnp_handled_high[0x20]; 3833 3834 u8 cnp_handled_low[0x20]; 3835 3836 u8 reserved_2[0x100]; 3837 3838 u8 time_stamp_high[0x20]; 3839 3840 u8 time_stamp_low[0x20]; 3841 3842 u8 accumulators_period[0x20]; 3843 3844 u8 ecn_marked_roce_packets_high[0x20]; 3845 3846 u8 ecn_marked_roce_packets_low[0x20]; 3847 3848 u8 cnps_sent_high[0x20]; 3849 3850 u8 cnps_sent_low[0x20]; 3851 3852 u8 reserved_3[0x560]; 3853 }; 3854 3855 struct mlx5_ifc_query_cong_statistics_in_bits { 3856 u8 opcode[0x10]; 3857 u8 reserved_0[0x10]; 3858 3859 u8 reserved_1[0x10]; 3860 u8 op_mod[0x10]; 3861 3862 u8 clear[0x1]; 3863 u8 reserved_2[0x1f]; 3864 3865 u8 reserved_3[0x20]; 3866 }; 3867 3868 struct mlx5_ifc_query_cong_params_out_bits { 3869 u8 status[0x8]; 3870 u8 reserved_0[0x18]; 3871 3872 u8 syndrome[0x20]; 3873 3874 u8 reserved_1[0x40]; 3875 3876 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 3877 }; 3878 3879 struct mlx5_ifc_query_cong_params_in_bits { 3880 u8 opcode[0x10]; 3881 u8 reserved_0[0x10]; 3882 3883 u8 reserved_1[0x10]; 3884 u8 op_mod[0x10]; 3885 3886 u8 reserved_2[0x1c]; 3887 u8 cong_protocol[0x4]; 3888 3889 u8 reserved_3[0x20]; 3890 }; 3891 3892 struct mlx5_ifc_query_adapter_out_bits { 3893 u8 status[0x8]; 3894 u8 reserved_0[0x18]; 3895 3896 u8 syndrome[0x20]; 3897 3898 u8 reserved_1[0x40]; 3899 3900 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 3901 }; 3902 3903 struct mlx5_ifc_query_adapter_in_bits { 3904 u8 opcode[0x10]; 3905 u8 reserved_0[0x10]; 3906 3907 u8 reserved_1[0x10]; 3908 u8 op_mod[0x10]; 3909 3910 u8 reserved_2[0x40]; 3911 }; 3912 3913 struct mlx5_ifc_qp_2rst_out_bits { 3914 u8 status[0x8]; 3915 u8 reserved_0[0x18]; 3916 3917 u8 syndrome[0x20]; 3918 3919 u8 reserved_1[0x40]; 3920 }; 3921 3922 struct mlx5_ifc_qp_2rst_in_bits { 3923 u8 opcode[0x10]; 3924 u8 reserved_0[0x10]; 3925 3926 u8 reserved_1[0x10]; 3927 u8 op_mod[0x10]; 3928 3929 u8 reserved_2[0x8]; 3930 u8 qpn[0x18]; 3931 3932 u8 reserved_3[0x20]; 3933 }; 3934 3935 struct mlx5_ifc_qp_2err_out_bits { 3936 u8 status[0x8]; 3937 u8 reserved_0[0x18]; 3938 3939 u8 syndrome[0x20]; 3940 3941 u8 reserved_1[0x40]; 3942 }; 3943 3944 struct mlx5_ifc_qp_2err_in_bits { 3945 u8 opcode[0x10]; 3946 u8 reserved_0[0x10]; 3947 3948 u8 reserved_1[0x10]; 3949 u8 op_mod[0x10]; 3950 3951 u8 reserved_2[0x8]; 3952 u8 qpn[0x18]; 3953 3954 u8 reserved_3[0x20]; 3955 }; 3956 3957 struct mlx5_ifc_page_fault_resume_out_bits { 3958 u8 status[0x8]; 3959 u8 reserved_0[0x18]; 3960 3961 u8 syndrome[0x20]; 3962 3963 u8 reserved_1[0x40]; 3964 }; 3965 3966 struct mlx5_ifc_page_fault_resume_in_bits { 3967 u8 opcode[0x10]; 3968 u8 reserved_0[0x10]; 3969 3970 u8 reserved_1[0x10]; 3971 u8 op_mod[0x10]; 3972 3973 u8 error[0x1]; 3974 u8 reserved_2[0x4]; 3975 u8 rdma[0x1]; 3976 u8 read_write[0x1]; 3977 u8 req_res[0x1]; 3978 u8 qpn[0x18]; 3979 3980 u8 reserved_3[0x20]; 3981 }; 3982 3983 struct mlx5_ifc_nop_out_bits { 3984 u8 status[0x8]; 3985 u8 reserved_0[0x18]; 3986 3987 u8 syndrome[0x20]; 3988 3989 u8 reserved_1[0x40]; 3990 }; 3991 3992 struct mlx5_ifc_nop_in_bits { 3993 u8 opcode[0x10]; 3994 u8 reserved_0[0x10]; 3995 3996 u8 reserved_1[0x10]; 3997 u8 op_mod[0x10]; 3998 3999 u8 reserved_2[0x40]; 4000 }; 4001 4002 struct mlx5_ifc_modify_vport_state_out_bits { 4003 u8 status[0x8]; 4004 u8 reserved_0[0x18]; 4005 4006 u8 syndrome[0x20]; 4007 4008 u8 reserved_1[0x40]; 4009 }; 4010 4011 struct mlx5_ifc_modify_vport_state_in_bits { 4012 u8 opcode[0x10]; 4013 u8 reserved_0[0x10]; 4014 4015 u8 reserved_1[0x10]; 4016 u8 op_mod[0x10]; 4017 4018 u8 other_vport[0x1]; 4019 u8 reserved_2[0xf]; 4020 u8 vport_number[0x10]; 4021 4022 u8 reserved_3[0x18]; 4023 u8 admin_state[0x4]; 4024 u8 reserved_4[0x4]; 4025 }; 4026 4027 struct mlx5_ifc_modify_tis_out_bits { 4028 u8 status[0x8]; 4029 u8 reserved_0[0x18]; 4030 4031 u8 syndrome[0x20]; 4032 4033 u8 reserved_1[0x40]; 4034 }; 4035 4036 struct mlx5_ifc_modify_tis_in_bits { 4037 u8 opcode[0x10]; 4038 u8 reserved_0[0x10]; 4039 4040 u8 reserved_1[0x10]; 4041 u8 op_mod[0x10]; 4042 4043 u8 reserved_2[0x8]; 4044 u8 tisn[0x18]; 4045 4046 u8 reserved_3[0x20]; 4047 4048 u8 modify_bitmask[0x40]; 4049 4050 u8 reserved_4[0x40]; 4051 4052 struct mlx5_ifc_tisc_bits ctx; 4053 }; 4054 4055 struct mlx5_ifc_modify_tir_bitmask_bits { 4056 u8 reserved_0[0x20]; 4057 4058 u8 reserved_1[0x1b]; 4059 u8 self_lb_en[0x1]; 4060 u8 reserved_2[0x3]; 4061 u8 lro[0x1]; 4062 }; 4063 4064 struct mlx5_ifc_modify_tir_out_bits { 4065 u8 status[0x8]; 4066 u8 reserved_0[0x18]; 4067 4068 u8 syndrome[0x20]; 4069 4070 u8 reserved_1[0x40]; 4071 }; 4072 4073 struct mlx5_ifc_modify_tir_in_bits { 4074 u8 opcode[0x10]; 4075 u8 reserved_0[0x10]; 4076 4077 u8 reserved_1[0x10]; 4078 u8 op_mod[0x10]; 4079 4080 u8 reserved_2[0x8]; 4081 u8 tirn[0x18]; 4082 4083 u8 reserved_3[0x20]; 4084 4085 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 4086 4087 u8 reserved_4[0x40]; 4088 4089 struct mlx5_ifc_tirc_bits ctx; 4090 }; 4091 4092 struct mlx5_ifc_modify_sq_out_bits { 4093 u8 status[0x8]; 4094 u8 reserved_0[0x18]; 4095 4096 u8 syndrome[0x20]; 4097 4098 u8 reserved_1[0x40]; 4099 }; 4100 4101 struct mlx5_ifc_modify_sq_in_bits { 4102 u8 opcode[0x10]; 4103 u8 reserved_0[0x10]; 4104 4105 u8 reserved_1[0x10]; 4106 u8 op_mod[0x10]; 4107 4108 u8 sq_state[0x4]; 4109 u8 reserved_2[0x4]; 4110 u8 sqn[0x18]; 4111 4112 u8 reserved_3[0x20]; 4113 4114 u8 modify_bitmask[0x40]; 4115 4116 u8 reserved_4[0x40]; 4117 4118 struct mlx5_ifc_sqc_bits ctx; 4119 }; 4120 4121 struct mlx5_ifc_modify_rqt_out_bits { 4122 u8 status[0x8]; 4123 u8 reserved_0[0x18]; 4124 4125 u8 syndrome[0x20]; 4126 4127 u8 reserved_1[0x40]; 4128 }; 4129 4130 struct mlx5_ifc_rqt_bitmask_bits { 4131 u8 reserved[0x20]; 4132 4133 u8 reserved1[0x1f]; 4134 u8 rqn_list[0x1]; 4135 }; 4136 4137 struct mlx5_ifc_modify_rqt_in_bits { 4138 u8 opcode[0x10]; 4139 u8 reserved_0[0x10]; 4140 4141 u8 reserved_1[0x10]; 4142 u8 op_mod[0x10]; 4143 4144 u8 reserved_2[0x8]; 4145 u8 rqtn[0x18]; 4146 4147 u8 reserved_3[0x20]; 4148 4149 struct mlx5_ifc_rqt_bitmask_bits bitmask; 4150 4151 u8 reserved_4[0x40]; 4152 4153 struct mlx5_ifc_rqtc_bits ctx; 4154 }; 4155 4156 struct mlx5_ifc_modify_rq_out_bits { 4157 u8 status[0x8]; 4158 u8 reserved_0[0x18]; 4159 4160 u8 syndrome[0x20]; 4161 4162 u8 reserved_1[0x40]; 4163 }; 4164 4165 struct mlx5_ifc_modify_rq_in_bits { 4166 u8 opcode[0x10]; 4167 u8 reserved_0[0x10]; 4168 4169 u8 reserved_1[0x10]; 4170 u8 op_mod[0x10]; 4171 4172 u8 rq_state[0x4]; 4173 u8 reserved_2[0x4]; 4174 u8 rqn[0x18]; 4175 4176 u8 reserved_3[0x20]; 4177 4178 u8 modify_bitmask[0x40]; 4179 4180 u8 reserved_4[0x40]; 4181 4182 struct mlx5_ifc_rqc_bits ctx; 4183 }; 4184 4185 struct mlx5_ifc_modify_rmp_out_bits { 4186 u8 status[0x8]; 4187 u8 reserved_0[0x18]; 4188 4189 u8 syndrome[0x20]; 4190 4191 u8 reserved_1[0x40]; 4192 }; 4193 4194 struct mlx5_ifc_rmp_bitmask_bits { 4195 u8 reserved[0x20]; 4196 4197 u8 reserved1[0x1f]; 4198 u8 lwm[0x1]; 4199 }; 4200 4201 struct mlx5_ifc_modify_rmp_in_bits { 4202 u8 opcode[0x10]; 4203 u8 reserved_0[0x10]; 4204 4205 u8 reserved_1[0x10]; 4206 u8 op_mod[0x10]; 4207 4208 u8 rmp_state[0x4]; 4209 u8 reserved_2[0x4]; 4210 u8 rmpn[0x18]; 4211 4212 u8 reserved_3[0x20]; 4213 4214 struct mlx5_ifc_rmp_bitmask_bits bitmask; 4215 4216 u8 reserved_4[0x40]; 4217 4218 struct mlx5_ifc_rmpc_bits ctx; 4219 }; 4220 4221 struct mlx5_ifc_modify_nic_vport_context_out_bits { 4222 u8 status[0x8]; 4223 u8 reserved_0[0x18]; 4224 4225 u8 syndrome[0x20]; 4226 4227 u8 reserved_1[0x40]; 4228 }; 4229 4230 struct mlx5_ifc_modify_nic_vport_field_select_bits { 4231 u8 reserved_0[0x1c]; 4232 u8 permanent_address[0x1]; 4233 u8 addresses_list[0x1]; 4234 u8 roce_en[0x1]; 4235 u8 reserved_1[0x1]; 4236 }; 4237 4238 struct mlx5_ifc_modify_nic_vport_context_in_bits { 4239 u8 opcode[0x10]; 4240 u8 reserved_0[0x10]; 4241 4242 u8 reserved_1[0x10]; 4243 u8 op_mod[0x10]; 4244 4245 u8 other_vport[0x1]; 4246 u8 reserved_2[0xf]; 4247 u8 vport_number[0x10]; 4248 4249 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 4250 4251 u8 reserved_3[0x780]; 4252 4253 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4254 }; 4255 4256 struct mlx5_ifc_modify_hca_vport_context_out_bits { 4257 u8 status[0x8]; 4258 u8 reserved_0[0x18]; 4259 4260 u8 syndrome[0x20]; 4261 4262 u8 reserved_1[0x40]; 4263 }; 4264 4265 struct mlx5_ifc_modify_hca_vport_context_in_bits { 4266 u8 opcode[0x10]; 4267 u8 reserved_0[0x10]; 4268 4269 u8 reserved_1[0x10]; 4270 u8 op_mod[0x10]; 4271 4272 u8 other_vport[0x1]; 4273 u8 reserved_2[0xb]; 4274 u8 port_num[0x4]; 4275 u8 vport_number[0x10]; 4276 4277 u8 reserved_3[0x20]; 4278 4279 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4280 }; 4281 4282 struct mlx5_ifc_modify_cq_out_bits { 4283 u8 status[0x8]; 4284 u8 reserved_0[0x18]; 4285 4286 u8 syndrome[0x20]; 4287 4288 u8 reserved_1[0x40]; 4289 }; 4290 4291 enum { 4292 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 4293 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 4294 }; 4295 4296 struct mlx5_ifc_modify_cq_in_bits { 4297 u8 opcode[0x10]; 4298 u8 reserved_0[0x10]; 4299 4300 u8 reserved_1[0x10]; 4301 u8 op_mod[0x10]; 4302 4303 u8 reserved_2[0x8]; 4304 u8 cqn[0x18]; 4305 4306 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 4307 4308 struct mlx5_ifc_cqc_bits cq_context; 4309 4310 u8 reserved_3[0x600]; 4311 4312 u8 pas[0][0x40]; 4313 }; 4314 4315 struct mlx5_ifc_modify_cong_status_out_bits { 4316 u8 status[0x8]; 4317 u8 reserved_0[0x18]; 4318 4319 u8 syndrome[0x20]; 4320 4321 u8 reserved_1[0x40]; 4322 }; 4323 4324 struct mlx5_ifc_modify_cong_status_in_bits { 4325 u8 opcode[0x10]; 4326 u8 reserved_0[0x10]; 4327 4328 u8 reserved_1[0x10]; 4329 u8 op_mod[0x10]; 4330 4331 u8 reserved_2[0x18]; 4332 u8 priority[0x4]; 4333 u8 cong_protocol[0x4]; 4334 4335 u8 enable[0x1]; 4336 u8 tag_enable[0x1]; 4337 u8 reserved_3[0x1e]; 4338 }; 4339 4340 struct mlx5_ifc_modify_cong_params_out_bits { 4341 u8 status[0x8]; 4342 u8 reserved_0[0x18]; 4343 4344 u8 syndrome[0x20]; 4345 4346 u8 reserved_1[0x40]; 4347 }; 4348 4349 struct mlx5_ifc_modify_cong_params_in_bits { 4350 u8 opcode[0x10]; 4351 u8 reserved_0[0x10]; 4352 4353 u8 reserved_1[0x10]; 4354 u8 op_mod[0x10]; 4355 4356 u8 reserved_2[0x1c]; 4357 u8 cong_protocol[0x4]; 4358 4359 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 4360 4361 u8 reserved_3[0x80]; 4362 4363 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4364 }; 4365 4366 struct mlx5_ifc_manage_pages_out_bits { 4367 u8 status[0x8]; 4368 u8 reserved_0[0x18]; 4369 4370 u8 syndrome[0x20]; 4371 4372 u8 output_num_entries[0x20]; 4373 4374 u8 reserved_1[0x20]; 4375 4376 u8 pas[0][0x40]; 4377 }; 4378 4379 enum { 4380 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 4381 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 4382 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 4383 }; 4384 4385 struct mlx5_ifc_manage_pages_in_bits { 4386 u8 opcode[0x10]; 4387 u8 reserved_0[0x10]; 4388 4389 u8 reserved_1[0x10]; 4390 u8 op_mod[0x10]; 4391 4392 u8 reserved_2[0x10]; 4393 u8 function_id[0x10]; 4394 4395 u8 input_num_entries[0x20]; 4396 4397 u8 pas[0][0x40]; 4398 }; 4399 4400 struct mlx5_ifc_mad_ifc_out_bits { 4401 u8 status[0x8]; 4402 u8 reserved_0[0x18]; 4403 4404 u8 syndrome[0x20]; 4405 4406 u8 reserved_1[0x40]; 4407 4408 u8 response_mad_packet[256][0x8]; 4409 }; 4410 4411 struct mlx5_ifc_mad_ifc_in_bits { 4412 u8 opcode[0x10]; 4413 u8 reserved_0[0x10]; 4414 4415 u8 reserved_1[0x10]; 4416 u8 op_mod[0x10]; 4417 4418 u8 remote_lid[0x10]; 4419 u8 reserved_2[0x8]; 4420 u8 port[0x8]; 4421 4422 u8 reserved_3[0x20]; 4423 4424 u8 mad[256][0x8]; 4425 }; 4426 4427 struct mlx5_ifc_init_hca_out_bits { 4428 u8 status[0x8]; 4429 u8 reserved_0[0x18]; 4430 4431 u8 syndrome[0x20]; 4432 4433 u8 reserved_1[0x40]; 4434 }; 4435 4436 struct mlx5_ifc_init_hca_in_bits { 4437 u8 opcode[0x10]; 4438 u8 reserved_0[0x10]; 4439 4440 u8 reserved_1[0x10]; 4441 u8 op_mod[0x10]; 4442 4443 u8 reserved_2[0x40]; 4444 }; 4445 4446 struct mlx5_ifc_init2rtr_qp_out_bits { 4447 u8 status[0x8]; 4448 u8 reserved_0[0x18]; 4449 4450 u8 syndrome[0x20]; 4451 4452 u8 reserved_1[0x40]; 4453 }; 4454 4455 struct mlx5_ifc_init2rtr_qp_in_bits { 4456 u8 opcode[0x10]; 4457 u8 reserved_0[0x10]; 4458 4459 u8 reserved_1[0x10]; 4460 u8 op_mod[0x10]; 4461 4462 u8 reserved_2[0x8]; 4463 u8 qpn[0x18]; 4464 4465 u8 reserved_3[0x20]; 4466 4467 u8 opt_param_mask[0x20]; 4468 4469 u8 reserved_4[0x20]; 4470 4471 struct mlx5_ifc_qpc_bits qpc; 4472 4473 u8 reserved_5[0x80]; 4474 }; 4475 4476 struct mlx5_ifc_init2init_qp_out_bits { 4477 u8 status[0x8]; 4478 u8 reserved_0[0x18]; 4479 4480 u8 syndrome[0x20]; 4481 4482 u8 reserved_1[0x40]; 4483 }; 4484 4485 struct mlx5_ifc_init2init_qp_in_bits { 4486 u8 opcode[0x10]; 4487 u8 reserved_0[0x10]; 4488 4489 u8 reserved_1[0x10]; 4490 u8 op_mod[0x10]; 4491 4492 u8 reserved_2[0x8]; 4493 u8 qpn[0x18]; 4494 4495 u8 reserved_3[0x20]; 4496 4497 u8 opt_param_mask[0x20]; 4498 4499 u8 reserved_4[0x20]; 4500 4501 struct mlx5_ifc_qpc_bits qpc; 4502 4503 u8 reserved_5[0x80]; 4504 }; 4505 4506 struct mlx5_ifc_get_dropped_packet_log_out_bits { 4507 u8 status[0x8]; 4508 u8 reserved_0[0x18]; 4509 4510 u8 syndrome[0x20]; 4511 4512 u8 reserved_1[0x40]; 4513 4514 u8 packet_headers_log[128][0x8]; 4515 4516 u8 packet_syndrome[64][0x8]; 4517 }; 4518 4519 struct mlx5_ifc_get_dropped_packet_log_in_bits { 4520 u8 opcode[0x10]; 4521 u8 reserved_0[0x10]; 4522 4523 u8 reserved_1[0x10]; 4524 u8 op_mod[0x10]; 4525 4526 u8 reserved_2[0x40]; 4527 }; 4528 4529 struct mlx5_ifc_gen_eqe_in_bits { 4530 u8 opcode[0x10]; 4531 u8 reserved_0[0x10]; 4532 4533 u8 reserved_1[0x10]; 4534 u8 op_mod[0x10]; 4535 4536 u8 reserved_2[0x18]; 4537 u8 eq_number[0x8]; 4538 4539 u8 reserved_3[0x20]; 4540 4541 u8 eqe[64][0x8]; 4542 }; 4543 4544 struct mlx5_ifc_gen_eq_out_bits { 4545 u8 status[0x8]; 4546 u8 reserved_0[0x18]; 4547 4548 u8 syndrome[0x20]; 4549 4550 u8 reserved_1[0x40]; 4551 }; 4552 4553 struct mlx5_ifc_enable_hca_out_bits { 4554 u8 status[0x8]; 4555 u8 reserved_0[0x18]; 4556 4557 u8 syndrome[0x20]; 4558 4559 u8 reserved_1[0x20]; 4560 }; 4561 4562 struct mlx5_ifc_enable_hca_in_bits { 4563 u8 opcode[0x10]; 4564 u8 reserved_0[0x10]; 4565 4566 u8 reserved_1[0x10]; 4567 u8 op_mod[0x10]; 4568 4569 u8 reserved_2[0x10]; 4570 u8 function_id[0x10]; 4571 4572 u8 reserved_3[0x20]; 4573 }; 4574 4575 struct mlx5_ifc_drain_dct_out_bits { 4576 u8 status[0x8]; 4577 u8 reserved_0[0x18]; 4578 4579 u8 syndrome[0x20]; 4580 4581 u8 reserved_1[0x40]; 4582 }; 4583 4584 struct mlx5_ifc_drain_dct_in_bits { 4585 u8 opcode[0x10]; 4586 u8 reserved_0[0x10]; 4587 4588 u8 reserved_1[0x10]; 4589 u8 op_mod[0x10]; 4590 4591 u8 reserved_2[0x8]; 4592 u8 dctn[0x18]; 4593 4594 u8 reserved_3[0x20]; 4595 }; 4596 4597 struct mlx5_ifc_disable_hca_out_bits { 4598 u8 status[0x8]; 4599 u8 reserved_0[0x18]; 4600 4601 u8 syndrome[0x20]; 4602 4603 u8 reserved_1[0x20]; 4604 }; 4605 4606 struct mlx5_ifc_disable_hca_in_bits { 4607 u8 opcode[0x10]; 4608 u8 reserved_0[0x10]; 4609 4610 u8 reserved_1[0x10]; 4611 u8 op_mod[0x10]; 4612 4613 u8 reserved_2[0x10]; 4614 u8 function_id[0x10]; 4615 4616 u8 reserved_3[0x20]; 4617 }; 4618 4619 struct mlx5_ifc_detach_from_mcg_out_bits { 4620 u8 status[0x8]; 4621 u8 reserved_0[0x18]; 4622 4623 u8 syndrome[0x20]; 4624 4625 u8 reserved_1[0x40]; 4626 }; 4627 4628 struct mlx5_ifc_detach_from_mcg_in_bits { 4629 u8 opcode[0x10]; 4630 u8 reserved_0[0x10]; 4631 4632 u8 reserved_1[0x10]; 4633 u8 op_mod[0x10]; 4634 4635 u8 reserved_2[0x8]; 4636 u8 qpn[0x18]; 4637 4638 u8 reserved_3[0x20]; 4639 4640 u8 multicast_gid[16][0x8]; 4641 }; 4642 4643 struct mlx5_ifc_destroy_xrc_srq_out_bits { 4644 u8 status[0x8]; 4645 u8 reserved_0[0x18]; 4646 4647 u8 syndrome[0x20]; 4648 4649 u8 reserved_1[0x40]; 4650 }; 4651 4652 struct mlx5_ifc_destroy_xrc_srq_in_bits { 4653 u8 opcode[0x10]; 4654 u8 reserved_0[0x10]; 4655 4656 u8 reserved_1[0x10]; 4657 u8 op_mod[0x10]; 4658 4659 u8 reserved_2[0x8]; 4660 u8 xrc_srqn[0x18]; 4661 4662 u8 reserved_3[0x20]; 4663 }; 4664 4665 struct mlx5_ifc_destroy_tis_out_bits { 4666 u8 status[0x8]; 4667 u8 reserved_0[0x18]; 4668 4669 u8 syndrome[0x20]; 4670 4671 u8 reserved_1[0x40]; 4672 }; 4673 4674 struct mlx5_ifc_destroy_tis_in_bits { 4675 u8 opcode[0x10]; 4676 u8 reserved_0[0x10]; 4677 4678 u8 reserved_1[0x10]; 4679 u8 op_mod[0x10]; 4680 4681 u8 reserved_2[0x8]; 4682 u8 tisn[0x18]; 4683 4684 u8 reserved_3[0x20]; 4685 }; 4686 4687 struct mlx5_ifc_destroy_tir_out_bits { 4688 u8 status[0x8]; 4689 u8 reserved_0[0x18]; 4690 4691 u8 syndrome[0x20]; 4692 4693 u8 reserved_1[0x40]; 4694 }; 4695 4696 struct mlx5_ifc_destroy_tir_in_bits { 4697 u8 opcode[0x10]; 4698 u8 reserved_0[0x10]; 4699 4700 u8 reserved_1[0x10]; 4701 u8 op_mod[0x10]; 4702 4703 u8 reserved_2[0x8]; 4704 u8 tirn[0x18]; 4705 4706 u8 reserved_3[0x20]; 4707 }; 4708 4709 struct mlx5_ifc_destroy_srq_out_bits { 4710 u8 status[0x8]; 4711 u8 reserved_0[0x18]; 4712 4713 u8 syndrome[0x20]; 4714 4715 u8 reserved_1[0x40]; 4716 }; 4717 4718 struct mlx5_ifc_destroy_srq_in_bits { 4719 u8 opcode[0x10]; 4720 u8 reserved_0[0x10]; 4721 4722 u8 reserved_1[0x10]; 4723 u8 op_mod[0x10]; 4724 4725 u8 reserved_2[0x8]; 4726 u8 srqn[0x18]; 4727 4728 u8 reserved_3[0x20]; 4729 }; 4730 4731 struct mlx5_ifc_destroy_sq_out_bits { 4732 u8 status[0x8]; 4733 u8 reserved_0[0x18]; 4734 4735 u8 syndrome[0x20]; 4736 4737 u8 reserved_1[0x40]; 4738 }; 4739 4740 struct mlx5_ifc_destroy_sq_in_bits { 4741 u8 opcode[0x10]; 4742 u8 reserved_0[0x10]; 4743 4744 u8 reserved_1[0x10]; 4745 u8 op_mod[0x10]; 4746 4747 u8 reserved_2[0x8]; 4748 u8 sqn[0x18]; 4749 4750 u8 reserved_3[0x20]; 4751 }; 4752 4753 struct mlx5_ifc_destroy_rqt_out_bits { 4754 u8 status[0x8]; 4755 u8 reserved_0[0x18]; 4756 4757 u8 syndrome[0x20]; 4758 4759 u8 reserved_1[0x40]; 4760 }; 4761 4762 struct mlx5_ifc_destroy_rqt_in_bits { 4763 u8 opcode[0x10]; 4764 u8 reserved_0[0x10]; 4765 4766 u8 reserved_1[0x10]; 4767 u8 op_mod[0x10]; 4768 4769 u8 reserved_2[0x8]; 4770 u8 rqtn[0x18]; 4771 4772 u8 reserved_3[0x20]; 4773 }; 4774 4775 struct mlx5_ifc_destroy_rq_out_bits { 4776 u8 status[0x8]; 4777 u8 reserved_0[0x18]; 4778 4779 u8 syndrome[0x20]; 4780 4781 u8 reserved_1[0x40]; 4782 }; 4783 4784 struct mlx5_ifc_destroy_rq_in_bits { 4785 u8 opcode[0x10]; 4786 u8 reserved_0[0x10]; 4787 4788 u8 reserved_1[0x10]; 4789 u8 op_mod[0x10]; 4790 4791 u8 reserved_2[0x8]; 4792 u8 rqn[0x18]; 4793 4794 u8 reserved_3[0x20]; 4795 }; 4796 4797 struct mlx5_ifc_destroy_rmp_out_bits { 4798 u8 status[0x8]; 4799 u8 reserved_0[0x18]; 4800 4801 u8 syndrome[0x20]; 4802 4803 u8 reserved_1[0x40]; 4804 }; 4805 4806 struct mlx5_ifc_destroy_rmp_in_bits { 4807 u8 opcode[0x10]; 4808 u8 reserved_0[0x10]; 4809 4810 u8 reserved_1[0x10]; 4811 u8 op_mod[0x10]; 4812 4813 u8 reserved_2[0x8]; 4814 u8 rmpn[0x18]; 4815 4816 u8 reserved_3[0x20]; 4817 }; 4818 4819 struct mlx5_ifc_destroy_qp_out_bits { 4820 u8 status[0x8]; 4821 u8 reserved_0[0x18]; 4822 4823 u8 syndrome[0x20]; 4824 4825 u8 reserved_1[0x40]; 4826 }; 4827 4828 struct mlx5_ifc_destroy_qp_in_bits { 4829 u8 opcode[0x10]; 4830 u8 reserved_0[0x10]; 4831 4832 u8 reserved_1[0x10]; 4833 u8 op_mod[0x10]; 4834 4835 u8 reserved_2[0x8]; 4836 u8 qpn[0x18]; 4837 4838 u8 reserved_3[0x20]; 4839 }; 4840 4841 struct mlx5_ifc_destroy_psv_out_bits { 4842 u8 status[0x8]; 4843 u8 reserved_0[0x18]; 4844 4845 u8 syndrome[0x20]; 4846 4847 u8 reserved_1[0x40]; 4848 }; 4849 4850 struct mlx5_ifc_destroy_psv_in_bits { 4851 u8 opcode[0x10]; 4852 u8 reserved_0[0x10]; 4853 4854 u8 reserved_1[0x10]; 4855 u8 op_mod[0x10]; 4856 4857 u8 reserved_2[0x8]; 4858 u8 psvn[0x18]; 4859 4860 u8 reserved_3[0x20]; 4861 }; 4862 4863 struct mlx5_ifc_destroy_mkey_out_bits { 4864 u8 status[0x8]; 4865 u8 reserved_0[0x18]; 4866 4867 u8 syndrome[0x20]; 4868 4869 u8 reserved_1[0x40]; 4870 }; 4871 4872 struct mlx5_ifc_destroy_mkey_in_bits { 4873 u8 opcode[0x10]; 4874 u8 reserved_0[0x10]; 4875 4876 u8 reserved_1[0x10]; 4877 u8 op_mod[0x10]; 4878 4879 u8 reserved_2[0x8]; 4880 u8 mkey_index[0x18]; 4881 4882 u8 reserved_3[0x20]; 4883 }; 4884 4885 struct mlx5_ifc_destroy_flow_table_out_bits { 4886 u8 status[0x8]; 4887 u8 reserved_0[0x18]; 4888 4889 u8 syndrome[0x20]; 4890 4891 u8 reserved_1[0x40]; 4892 }; 4893 4894 struct mlx5_ifc_destroy_flow_table_in_bits { 4895 u8 opcode[0x10]; 4896 u8 reserved_0[0x10]; 4897 4898 u8 reserved_1[0x10]; 4899 u8 op_mod[0x10]; 4900 4901 u8 reserved_2[0x40]; 4902 4903 u8 table_type[0x8]; 4904 u8 reserved_3[0x18]; 4905 4906 u8 reserved_4[0x8]; 4907 u8 table_id[0x18]; 4908 4909 u8 reserved_5[0x140]; 4910 }; 4911 4912 struct mlx5_ifc_destroy_flow_group_out_bits { 4913 u8 status[0x8]; 4914 u8 reserved_0[0x18]; 4915 4916 u8 syndrome[0x20]; 4917 4918 u8 reserved_1[0x40]; 4919 }; 4920 4921 struct mlx5_ifc_destroy_flow_group_in_bits { 4922 u8 opcode[0x10]; 4923 u8 reserved_0[0x10]; 4924 4925 u8 reserved_1[0x10]; 4926 u8 op_mod[0x10]; 4927 4928 u8 reserved_2[0x40]; 4929 4930 u8 table_type[0x8]; 4931 u8 reserved_3[0x18]; 4932 4933 u8 reserved_4[0x8]; 4934 u8 table_id[0x18]; 4935 4936 u8 group_id[0x20]; 4937 4938 u8 reserved_5[0x120]; 4939 }; 4940 4941 struct mlx5_ifc_destroy_eq_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_0[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_1[0x40]; 4948 }; 4949 4950 struct mlx5_ifc_destroy_eq_in_bits { 4951 u8 opcode[0x10]; 4952 u8 reserved_0[0x10]; 4953 4954 u8 reserved_1[0x10]; 4955 u8 op_mod[0x10]; 4956 4957 u8 reserved_2[0x18]; 4958 u8 eq_number[0x8]; 4959 4960 u8 reserved_3[0x20]; 4961 }; 4962 4963 struct mlx5_ifc_destroy_dct_out_bits { 4964 u8 status[0x8]; 4965 u8 reserved_0[0x18]; 4966 4967 u8 syndrome[0x20]; 4968 4969 u8 reserved_1[0x40]; 4970 }; 4971 4972 struct mlx5_ifc_destroy_dct_in_bits { 4973 u8 opcode[0x10]; 4974 u8 reserved_0[0x10]; 4975 4976 u8 reserved_1[0x10]; 4977 u8 op_mod[0x10]; 4978 4979 u8 reserved_2[0x8]; 4980 u8 dctn[0x18]; 4981 4982 u8 reserved_3[0x20]; 4983 }; 4984 4985 struct mlx5_ifc_destroy_cq_out_bits { 4986 u8 status[0x8]; 4987 u8 reserved_0[0x18]; 4988 4989 u8 syndrome[0x20]; 4990 4991 u8 reserved_1[0x40]; 4992 }; 4993 4994 struct mlx5_ifc_destroy_cq_in_bits { 4995 u8 opcode[0x10]; 4996 u8 reserved_0[0x10]; 4997 4998 u8 reserved_1[0x10]; 4999 u8 op_mod[0x10]; 5000 5001 u8 reserved_2[0x8]; 5002 u8 cqn[0x18]; 5003 5004 u8 reserved_3[0x20]; 5005 }; 5006 5007 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_0[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_1[0x40]; 5014 }; 5015 5016 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5017 u8 opcode[0x10]; 5018 u8 reserved_0[0x10]; 5019 5020 u8 reserved_1[0x10]; 5021 u8 op_mod[0x10]; 5022 5023 u8 reserved_2[0x20]; 5024 5025 u8 reserved_3[0x10]; 5026 u8 vxlan_udp_port[0x10]; 5027 }; 5028 5029 struct mlx5_ifc_delete_l2_table_entry_out_bits { 5030 u8 status[0x8]; 5031 u8 reserved_0[0x18]; 5032 5033 u8 syndrome[0x20]; 5034 5035 u8 reserved_1[0x40]; 5036 }; 5037 5038 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5039 u8 opcode[0x10]; 5040 u8 reserved_0[0x10]; 5041 5042 u8 reserved_1[0x10]; 5043 u8 op_mod[0x10]; 5044 5045 u8 reserved_2[0x60]; 5046 5047 u8 reserved_3[0x8]; 5048 u8 table_index[0x18]; 5049 5050 u8 reserved_4[0x140]; 5051 }; 5052 5053 struct mlx5_ifc_delete_fte_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_0[0x18]; 5056 5057 u8 syndrome[0x20]; 5058 5059 u8 reserved_1[0x40]; 5060 }; 5061 5062 struct mlx5_ifc_delete_fte_in_bits { 5063 u8 opcode[0x10]; 5064 u8 reserved_0[0x10]; 5065 5066 u8 reserved_1[0x10]; 5067 u8 op_mod[0x10]; 5068 5069 u8 reserved_2[0x40]; 5070 5071 u8 table_type[0x8]; 5072 u8 reserved_3[0x18]; 5073 5074 u8 reserved_4[0x8]; 5075 u8 table_id[0x18]; 5076 5077 u8 reserved_5[0x40]; 5078 5079 u8 flow_index[0x20]; 5080 5081 u8 reserved_6[0xe0]; 5082 }; 5083 5084 struct mlx5_ifc_dealloc_xrcd_out_bits { 5085 u8 status[0x8]; 5086 u8 reserved_0[0x18]; 5087 5088 u8 syndrome[0x20]; 5089 5090 u8 reserved_1[0x40]; 5091 }; 5092 5093 struct mlx5_ifc_dealloc_xrcd_in_bits { 5094 u8 opcode[0x10]; 5095 u8 reserved_0[0x10]; 5096 5097 u8 reserved_1[0x10]; 5098 u8 op_mod[0x10]; 5099 5100 u8 reserved_2[0x8]; 5101 u8 xrcd[0x18]; 5102 5103 u8 reserved_3[0x20]; 5104 }; 5105 5106 struct mlx5_ifc_dealloc_uar_out_bits { 5107 u8 status[0x8]; 5108 u8 reserved_0[0x18]; 5109 5110 u8 syndrome[0x20]; 5111 5112 u8 reserved_1[0x40]; 5113 }; 5114 5115 struct mlx5_ifc_dealloc_uar_in_bits { 5116 u8 opcode[0x10]; 5117 u8 reserved_0[0x10]; 5118 5119 u8 reserved_1[0x10]; 5120 u8 op_mod[0x10]; 5121 5122 u8 reserved_2[0x8]; 5123 u8 uar[0x18]; 5124 5125 u8 reserved_3[0x20]; 5126 }; 5127 5128 struct mlx5_ifc_dealloc_transport_domain_out_bits { 5129 u8 status[0x8]; 5130 u8 reserved_0[0x18]; 5131 5132 u8 syndrome[0x20]; 5133 5134 u8 reserved_1[0x40]; 5135 }; 5136 5137 struct mlx5_ifc_dealloc_transport_domain_in_bits { 5138 u8 opcode[0x10]; 5139 u8 reserved_0[0x10]; 5140 5141 u8 reserved_1[0x10]; 5142 u8 op_mod[0x10]; 5143 5144 u8 reserved_2[0x8]; 5145 u8 transport_domain[0x18]; 5146 5147 u8 reserved_3[0x20]; 5148 }; 5149 5150 struct mlx5_ifc_dealloc_q_counter_out_bits { 5151 u8 status[0x8]; 5152 u8 reserved_0[0x18]; 5153 5154 u8 syndrome[0x20]; 5155 5156 u8 reserved_1[0x40]; 5157 }; 5158 5159 struct mlx5_ifc_dealloc_q_counter_in_bits { 5160 u8 opcode[0x10]; 5161 u8 reserved_0[0x10]; 5162 5163 u8 reserved_1[0x10]; 5164 u8 op_mod[0x10]; 5165 5166 u8 reserved_2[0x18]; 5167 u8 counter_set_id[0x8]; 5168 5169 u8 reserved_3[0x20]; 5170 }; 5171 5172 struct mlx5_ifc_dealloc_pd_out_bits { 5173 u8 status[0x8]; 5174 u8 reserved_0[0x18]; 5175 5176 u8 syndrome[0x20]; 5177 5178 u8 reserved_1[0x40]; 5179 }; 5180 5181 struct mlx5_ifc_dealloc_pd_in_bits { 5182 u8 opcode[0x10]; 5183 u8 reserved_0[0x10]; 5184 5185 u8 reserved_1[0x10]; 5186 u8 op_mod[0x10]; 5187 5188 u8 reserved_2[0x8]; 5189 u8 pd[0x18]; 5190 5191 u8 reserved_3[0x20]; 5192 }; 5193 5194 struct mlx5_ifc_create_xrc_srq_out_bits { 5195 u8 status[0x8]; 5196 u8 reserved_0[0x18]; 5197 5198 u8 syndrome[0x20]; 5199 5200 u8 reserved_1[0x8]; 5201 u8 xrc_srqn[0x18]; 5202 5203 u8 reserved_2[0x20]; 5204 }; 5205 5206 struct mlx5_ifc_create_xrc_srq_in_bits { 5207 u8 opcode[0x10]; 5208 u8 reserved_0[0x10]; 5209 5210 u8 reserved_1[0x10]; 5211 u8 op_mod[0x10]; 5212 5213 u8 reserved_2[0x40]; 5214 5215 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5216 5217 u8 reserved_3[0x600]; 5218 5219 u8 pas[0][0x40]; 5220 }; 5221 5222 struct mlx5_ifc_create_tis_out_bits { 5223 u8 status[0x8]; 5224 u8 reserved_0[0x18]; 5225 5226 u8 syndrome[0x20]; 5227 5228 u8 reserved_1[0x8]; 5229 u8 tisn[0x18]; 5230 5231 u8 reserved_2[0x20]; 5232 }; 5233 5234 struct mlx5_ifc_create_tis_in_bits { 5235 u8 opcode[0x10]; 5236 u8 reserved_0[0x10]; 5237 5238 u8 reserved_1[0x10]; 5239 u8 op_mod[0x10]; 5240 5241 u8 reserved_2[0xc0]; 5242 5243 struct mlx5_ifc_tisc_bits ctx; 5244 }; 5245 5246 struct mlx5_ifc_create_tir_out_bits { 5247 u8 status[0x8]; 5248 u8 reserved_0[0x18]; 5249 5250 u8 syndrome[0x20]; 5251 5252 u8 reserved_1[0x8]; 5253 u8 tirn[0x18]; 5254 5255 u8 reserved_2[0x20]; 5256 }; 5257 5258 struct mlx5_ifc_create_tir_in_bits { 5259 u8 opcode[0x10]; 5260 u8 reserved_0[0x10]; 5261 5262 u8 reserved_1[0x10]; 5263 u8 op_mod[0x10]; 5264 5265 u8 reserved_2[0xc0]; 5266 5267 struct mlx5_ifc_tirc_bits ctx; 5268 }; 5269 5270 struct mlx5_ifc_create_srq_out_bits { 5271 u8 status[0x8]; 5272 u8 reserved_0[0x18]; 5273 5274 u8 syndrome[0x20]; 5275 5276 u8 reserved_1[0x8]; 5277 u8 srqn[0x18]; 5278 5279 u8 reserved_2[0x20]; 5280 }; 5281 5282 struct mlx5_ifc_create_srq_in_bits { 5283 u8 opcode[0x10]; 5284 u8 reserved_0[0x10]; 5285 5286 u8 reserved_1[0x10]; 5287 u8 op_mod[0x10]; 5288 5289 u8 reserved_2[0x40]; 5290 5291 struct mlx5_ifc_srqc_bits srq_context_entry; 5292 5293 u8 reserved_3[0x600]; 5294 5295 u8 pas[0][0x40]; 5296 }; 5297 5298 struct mlx5_ifc_create_sq_out_bits { 5299 u8 status[0x8]; 5300 u8 reserved_0[0x18]; 5301 5302 u8 syndrome[0x20]; 5303 5304 u8 reserved_1[0x8]; 5305 u8 sqn[0x18]; 5306 5307 u8 reserved_2[0x20]; 5308 }; 5309 5310 struct mlx5_ifc_create_sq_in_bits { 5311 u8 opcode[0x10]; 5312 u8 reserved_0[0x10]; 5313 5314 u8 reserved_1[0x10]; 5315 u8 op_mod[0x10]; 5316 5317 u8 reserved_2[0xc0]; 5318 5319 struct mlx5_ifc_sqc_bits ctx; 5320 }; 5321 5322 struct mlx5_ifc_create_rqt_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_0[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_1[0x8]; 5329 u8 rqtn[0x18]; 5330 5331 u8 reserved_2[0x20]; 5332 }; 5333 5334 struct mlx5_ifc_create_rqt_in_bits { 5335 u8 opcode[0x10]; 5336 u8 reserved_0[0x10]; 5337 5338 u8 reserved_1[0x10]; 5339 u8 op_mod[0x10]; 5340 5341 u8 reserved_2[0xc0]; 5342 5343 struct mlx5_ifc_rqtc_bits rqt_context; 5344 }; 5345 5346 struct mlx5_ifc_create_rq_out_bits { 5347 u8 status[0x8]; 5348 u8 reserved_0[0x18]; 5349 5350 u8 syndrome[0x20]; 5351 5352 u8 reserved_1[0x8]; 5353 u8 rqn[0x18]; 5354 5355 u8 reserved_2[0x20]; 5356 }; 5357 5358 struct mlx5_ifc_create_rq_in_bits { 5359 u8 opcode[0x10]; 5360 u8 reserved_0[0x10]; 5361 5362 u8 reserved_1[0x10]; 5363 u8 op_mod[0x10]; 5364 5365 u8 reserved_2[0xc0]; 5366 5367 struct mlx5_ifc_rqc_bits ctx; 5368 }; 5369 5370 struct mlx5_ifc_create_rmp_out_bits { 5371 u8 status[0x8]; 5372 u8 reserved_0[0x18]; 5373 5374 u8 syndrome[0x20]; 5375 5376 u8 reserved_1[0x8]; 5377 u8 rmpn[0x18]; 5378 5379 u8 reserved_2[0x20]; 5380 }; 5381 5382 struct mlx5_ifc_create_rmp_in_bits { 5383 u8 opcode[0x10]; 5384 u8 reserved_0[0x10]; 5385 5386 u8 reserved_1[0x10]; 5387 u8 op_mod[0x10]; 5388 5389 u8 reserved_2[0xc0]; 5390 5391 struct mlx5_ifc_rmpc_bits ctx; 5392 }; 5393 5394 struct mlx5_ifc_create_qp_out_bits { 5395 u8 status[0x8]; 5396 u8 reserved_0[0x18]; 5397 5398 u8 syndrome[0x20]; 5399 5400 u8 reserved_1[0x8]; 5401 u8 qpn[0x18]; 5402 5403 u8 reserved_2[0x20]; 5404 }; 5405 5406 struct mlx5_ifc_create_qp_in_bits { 5407 u8 opcode[0x10]; 5408 u8 reserved_0[0x10]; 5409 5410 u8 reserved_1[0x10]; 5411 u8 op_mod[0x10]; 5412 5413 u8 reserved_2[0x40]; 5414 5415 u8 opt_param_mask[0x20]; 5416 5417 u8 reserved_3[0x20]; 5418 5419 struct mlx5_ifc_qpc_bits qpc; 5420 5421 u8 reserved_4[0x80]; 5422 5423 u8 pas[0][0x40]; 5424 }; 5425 5426 struct mlx5_ifc_create_psv_out_bits { 5427 u8 status[0x8]; 5428 u8 reserved_0[0x18]; 5429 5430 u8 syndrome[0x20]; 5431 5432 u8 reserved_1[0x40]; 5433 5434 u8 reserved_2[0x8]; 5435 u8 psv0_index[0x18]; 5436 5437 u8 reserved_3[0x8]; 5438 u8 psv1_index[0x18]; 5439 5440 u8 reserved_4[0x8]; 5441 u8 psv2_index[0x18]; 5442 5443 u8 reserved_5[0x8]; 5444 u8 psv3_index[0x18]; 5445 }; 5446 5447 struct mlx5_ifc_create_psv_in_bits { 5448 u8 opcode[0x10]; 5449 u8 reserved_0[0x10]; 5450 5451 u8 reserved_1[0x10]; 5452 u8 op_mod[0x10]; 5453 5454 u8 num_psv[0x4]; 5455 u8 reserved_2[0x4]; 5456 u8 pd[0x18]; 5457 5458 u8 reserved_3[0x20]; 5459 }; 5460 5461 struct mlx5_ifc_create_mkey_out_bits { 5462 u8 status[0x8]; 5463 u8 reserved_0[0x18]; 5464 5465 u8 syndrome[0x20]; 5466 5467 u8 reserved_1[0x8]; 5468 u8 mkey_index[0x18]; 5469 5470 u8 reserved_2[0x20]; 5471 }; 5472 5473 struct mlx5_ifc_create_mkey_in_bits { 5474 u8 opcode[0x10]; 5475 u8 reserved_0[0x10]; 5476 5477 u8 reserved_1[0x10]; 5478 u8 op_mod[0x10]; 5479 5480 u8 reserved_2[0x20]; 5481 5482 u8 pg_access[0x1]; 5483 u8 reserved_3[0x1f]; 5484 5485 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5486 5487 u8 reserved_4[0x80]; 5488 5489 u8 translations_octword_actual_size[0x20]; 5490 5491 u8 reserved_5[0x560]; 5492 5493 u8 klm_pas_mtt[0][0x20]; 5494 }; 5495 5496 struct mlx5_ifc_create_flow_table_out_bits { 5497 u8 status[0x8]; 5498 u8 reserved_0[0x18]; 5499 5500 u8 syndrome[0x20]; 5501 5502 u8 reserved_1[0x8]; 5503 u8 table_id[0x18]; 5504 5505 u8 reserved_2[0x20]; 5506 }; 5507 5508 struct mlx5_ifc_create_flow_table_in_bits { 5509 u8 opcode[0x10]; 5510 u8 reserved_0[0x10]; 5511 5512 u8 reserved_1[0x10]; 5513 u8 op_mod[0x10]; 5514 5515 u8 reserved_2[0x40]; 5516 5517 u8 table_type[0x8]; 5518 u8 reserved_3[0x18]; 5519 5520 u8 reserved_4[0x20]; 5521 5522 u8 reserved_5[0x8]; 5523 u8 level[0x8]; 5524 u8 reserved_6[0x8]; 5525 u8 log_size[0x8]; 5526 5527 u8 reserved_7[0x120]; 5528 }; 5529 5530 struct mlx5_ifc_create_flow_group_out_bits { 5531 u8 status[0x8]; 5532 u8 reserved_0[0x18]; 5533 5534 u8 syndrome[0x20]; 5535 5536 u8 reserved_1[0x8]; 5537 u8 group_id[0x18]; 5538 5539 u8 reserved_2[0x20]; 5540 }; 5541 5542 enum { 5543 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5544 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5545 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5546 }; 5547 5548 struct mlx5_ifc_create_flow_group_in_bits { 5549 u8 opcode[0x10]; 5550 u8 reserved_0[0x10]; 5551 5552 u8 reserved_1[0x10]; 5553 u8 op_mod[0x10]; 5554 5555 u8 reserved_2[0x40]; 5556 5557 u8 table_type[0x8]; 5558 u8 reserved_3[0x18]; 5559 5560 u8 reserved_4[0x8]; 5561 u8 table_id[0x18]; 5562 5563 u8 reserved_5[0x20]; 5564 5565 u8 start_flow_index[0x20]; 5566 5567 u8 reserved_6[0x20]; 5568 5569 u8 end_flow_index[0x20]; 5570 5571 u8 reserved_7[0xa0]; 5572 5573 u8 reserved_8[0x18]; 5574 u8 match_criteria_enable[0x8]; 5575 5576 struct mlx5_ifc_fte_match_param_bits match_criteria; 5577 5578 u8 reserved_9[0xe00]; 5579 }; 5580 5581 struct mlx5_ifc_create_eq_out_bits { 5582 u8 status[0x8]; 5583 u8 reserved_0[0x18]; 5584 5585 u8 syndrome[0x20]; 5586 5587 u8 reserved_1[0x18]; 5588 u8 eq_number[0x8]; 5589 5590 u8 reserved_2[0x20]; 5591 }; 5592 5593 struct mlx5_ifc_create_eq_in_bits { 5594 u8 opcode[0x10]; 5595 u8 reserved_0[0x10]; 5596 5597 u8 reserved_1[0x10]; 5598 u8 op_mod[0x10]; 5599 5600 u8 reserved_2[0x40]; 5601 5602 struct mlx5_ifc_eqc_bits eq_context_entry; 5603 5604 u8 reserved_3[0x40]; 5605 5606 u8 event_bitmask[0x40]; 5607 5608 u8 reserved_4[0x580]; 5609 5610 u8 pas[0][0x40]; 5611 }; 5612 5613 struct mlx5_ifc_create_dct_out_bits { 5614 u8 status[0x8]; 5615 u8 reserved_0[0x18]; 5616 5617 u8 syndrome[0x20]; 5618 5619 u8 reserved_1[0x8]; 5620 u8 dctn[0x18]; 5621 5622 u8 reserved_2[0x20]; 5623 }; 5624 5625 struct mlx5_ifc_create_dct_in_bits { 5626 u8 opcode[0x10]; 5627 u8 reserved_0[0x10]; 5628 5629 u8 reserved_1[0x10]; 5630 u8 op_mod[0x10]; 5631 5632 u8 reserved_2[0x40]; 5633 5634 struct mlx5_ifc_dctc_bits dct_context_entry; 5635 5636 u8 reserved_3[0x180]; 5637 }; 5638 5639 struct mlx5_ifc_create_cq_out_bits { 5640 u8 status[0x8]; 5641 u8 reserved_0[0x18]; 5642 5643 u8 syndrome[0x20]; 5644 5645 u8 reserved_1[0x8]; 5646 u8 cqn[0x18]; 5647 5648 u8 reserved_2[0x20]; 5649 }; 5650 5651 struct mlx5_ifc_create_cq_in_bits { 5652 u8 opcode[0x10]; 5653 u8 reserved_0[0x10]; 5654 5655 u8 reserved_1[0x10]; 5656 u8 op_mod[0x10]; 5657 5658 u8 reserved_2[0x40]; 5659 5660 struct mlx5_ifc_cqc_bits cq_context; 5661 5662 u8 reserved_3[0x600]; 5663 5664 u8 pas[0][0x40]; 5665 }; 5666 5667 struct mlx5_ifc_config_int_moderation_out_bits { 5668 u8 status[0x8]; 5669 u8 reserved_0[0x18]; 5670 5671 u8 syndrome[0x20]; 5672 5673 u8 reserved_1[0x4]; 5674 u8 min_delay[0xc]; 5675 u8 int_vector[0x10]; 5676 5677 u8 reserved_2[0x20]; 5678 }; 5679 5680 enum { 5681 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 5682 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 5683 }; 5684 5685 struct mlx5_ifc_config_int_moderation_in_bits { 5686 u8 opcode[0x10]; 5687 u8 reserved_0[0x10]; 5688 5689 u8 reserved_1[0x10]; 5690 u8 op_mod[0x10]; 5691 5692 u8 reserved_2[0x4]; 5693 u8 min_delay[0xc]; 5694 u8 int_vector[0x10]; 5695 5696 u8 reserved_3[0x20]; 5697 }; 5698 5699 struct mlx5_ifc_attach_to_mcg_out_bits { 5700 u8 status[0x8]; 5701 u8 reserved_0[0x18]; 5702 5703 u8 syndrome[0x20]; 5704 5705 u8 reserved_1[0x40]; 5706 }; 5707 5708 struct mlx5_ifc_attach_to_mcg_in_bits { 5709 u8 opcode[0x10]; 5710 u8 reserved_0[0x10]; 5711 5712 u8 reserved_1[0x10]; 5713 u8 op_mod[0x10]; 5714 5715 u8 reserved_2[0x8]; 5716 u8 qpn[0x18]; 5717 5718 u8 reserved_3[0x20]; 5719 5720 u8 multicast_gid[16][0x8]; 5721 }; 5722 5723 struct mlx5_ifc_arm_xrc_srq_out_bits { 5724 u8 status[0x8]; 5725 u8 reserved_0[0x18]; 5726 5727 u8 syndrome[0x20]; 5728 5729 u8 reserved_1[0x40]; 5730 }; 5731 5732 enum { 5733 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 5734 }; 5735 5736 struct mlx5_ifc_arm_xrc_srq_in_bits { 5737 u8 opcode[0x10]; 5738 u8 reserved_0[0x10]; 5739 5740 u8 reserved_1[0x10]; 5741 u8 op_mod[0x10]; 5742 5743 u8 reserved_2[0x8]; 5744 u8 xrc_srqn[0x18]; 5745 5746 u8 reserved_3[0x10]; 5747 u8 lwm[0x10]; 5748 }; 5749 5750 struct mlx5_ifc_arm_rq_out_bits { 5751 u8 status[0x8]; 5752 u8 reserved_0[0x18]; 5753 5754 u8 syndrome[0x20]; 5755 5756 u8 reserved_1[0x40]; 5757 }; 5758 5759 enum { 5760 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1, 5761 }; 5762 5763 struct mlx5_ifc_arm_rq_in_bits { 5764 u8 opcode[0x10]; 5765 u8 reserved_0[0x10]; 5766 5767 u8 reserved_1[0x10]; 5768 u8 op_mod[0x10]; 5769 5770 u8 reserved_2[0x8]; 5771 u8 srq_number[0x18]; 5772 5773 u8 reserved_3[0x10]; 5774 u8 lwm[0x10]; 5775 }; 5776 5777 struct mlx5_ifc_arm_dct_out_bits { 5778 u8 status[0x8]; 5779 u8 reserved_0[0x18]; 5780 5781 u8 syndrome[0x20]; 5782 5783 u8 reserved_1[0x40]; 5784 }; 5785 5786 struct mlx5_ifc_arm_dct_in_bits { 5787 u8 opcode[0x10]; 5788 u8 reserved_0[0x10]; 5789 5790 u8 reserved_1[0x10]; 5791 u8 op_mod[0x10]; 5792 5793 u8 reserved_2[0x8]; 5794 u8 dct_number[0x18]; 5795 5796 u8 reserved_3[0x20]; 5797 }; 5798 5799 struct mlx5_ifc_alloc_xrcd_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_0[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_1[0x8]; 5806 u8 xrcd[0x18]; 5807 5808 u8 reserved_2[0x20]; 5809 }; 5810 5811 struct mlx5_ifc_alloc_xrcd_in_bits { 5812 u8 opcode[0x10]; 5813 u8 reserved_0[0x10]; 5814 5815 u8 reserved_1[0x10]; 5816 u8 op_mod[0x10]; 5817 5818 u8 reserved_2[0x40]; 5819 }; 5820 5821 struct mlx5_ifc_alloc_uar_out_bits { 5822 u8 status[0x8]; 5823 u8 reserved_0[0x18]; 5824 5825 u8 syndrome[0x20]; 5826 5827 u8 reserved_1[0x8]; 5828 u8 uar[0x18]; 5829 5830 u8 reserved_2[0x20]; 5831 }; 5832 5833 struct mlx5_ifc_alloc_uar_in_bits { 5834 u8 opcode[0x10]; 5835 u8 reserved_0[0x10]; 5836 5837 u8 reserved_1[0x10]; 5838 u8 op_mod[0x10]; 5839 5840 u8 reserved_2[0x40]; 5841 }; 5842 5843 struct mlx5_ifc_alloc_transport_domain_out_bits { 5844 u8 status[0x8]; 5845 u8 reserved_0[0x18]; 5846 5847 u8 syndrome[0x20]; 5848 5849 u8 reserved_1[0x8]; 5850 u8 transport_domain[0x18]; 5851 5852 u8 reserved_2[0x20]; 5853 }; 5854 5855 struct mlx5_ifc_alloc_transport_domain_in_bits { 5856 u8 opcode[0x10]; 5857 u8 reserved_0[0x10]; 5858 5859 u8 reserved_1[0x10]; 5860 u8 op_mod[0x10]; 5861 5862 u8 reserved_2[0x40]; 5863 }; 5864 5865 struct mlx5_ifc_alloc_q_counter_out_bits { 5866 u8 status[0x8]; 5867 u8 reserved_0[0x18]; 5868 5869 u8 syndrome[0x20]; 5870 5871 u8 reserved_1[0x18]; 5872 u8 counter_set_id[0x8]; 5873 5874 u8 reserved_2[0x20]; 5875 }; 5876 5877 struct mlx5_ifc_alloc_q_counter_in_bits { 5878 u8 opcode[0x10]; 5879 u8 reserved_0[0x10]; 5880 5881 u8 reserved_1[0x10]; 5882 u8 op_mod[0x10]; 5883 5884 u8 reserved_2[0x40]; 5885 }; 5886 5887 struct mlx5_ifc_alloc_pd_out_bits { 5888 u8 status[0x8]; 5889 u8 reserved_0[0x18]; 5890 5891 u8 syndrome[0x20]; 5892 5893 u8 reserved_1[0x8]; 5894 u8 pd[0x18]; 5895 5896 u8 reserved_2[0x20]; 5897 }; 5898 5899 struct mlx5_ifc_alloc_pd_in_bits { 5900 u8 opcode[0x10]; 5901 u8 reserved_0[0x10]; 5902 5903 u8 reserved_1[0x10]; 5904 u8 op_mod[0x10]; 5905 5906 u8 reserved_2[0x40]; 5907 }; 5908 5909 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 5910 u8 status[0x8]; 5911 u8 reserved_0[0x18]; 5912 5913 u8 syndrome[0x20]; 5914 5915 u8 reserved_1[0x40]; 5916 }; 5917 5918 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 5919 u8 opcode[0x10]; 5920 u8 reserved_0[0x10]; 5921 5922 u8 reserved_1[0x10]; 5923 u8 op_mod[0x10]; 5924 5925 u8 reserved_2[0x20]; 5926 5927 u8 reserved_3[0x10]; 5928 u8 vxlan_udp_port[0x10]; 5929 }; 5930 5931 struct mlx5_ifc_access_register_out_bits { 5932 u8 status[0x8]; 5933 u8 reserved_0[0x18]; 5934 5935 u8 syndrome[0x20]; 5936 5937 u8 reserved_1[0x40]; 5938 5939 u8 register_data[0][0x20]; 5940 }; 5941 5942 enum { 5943 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 5944 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 5945 }; 5946 5947 struct mlx5_ifc_access_register_in_bits { 5948 u8 opcode[0x10]; 5949 u8 reserved_0[0x10]; 5950 5951 u8 reserved_1[0x10]; 5952 u8 op_mod[0x10]; 5953 5954 u8 reserved_2[0x10]; 5955 u8 register_id[0x10]; 5956 5957 u8 argument[0x20]; 5958 5959 u8 register_data[0][0x20]; 5960 }; 5961 5962 struct mlx5_ifc_sltp_reg_bits { 5963 u8 status[0x4]; 5964 u8 version[0x4]; 5965 u8 local_port[0x8]; 5966 u8 pnat[0x2]; 5967 u8 reserved_0[0x2]; 5968 u8 lane[0x4]; 5969 u8 reserved_1[0x8]; 5970 5971 u8 reserved_2[0x20]; 5972 5973 u8 reserved_3[0x7]; 5974 u8 polarity[0x1]; 5975 u8 ob_tap0[0x8]; 5976 u8 ob_tap1[0x8]; 5977 u8 ob_tap2[0x8]; 5978 5979 u8 reserved_4[0xc]; 5980 u8 ob_preemp_mode[0x4]; 5981 u8 ob_reg[0x8]; 5982 u8 ob_bias[0x8]; 5983 5984 u8 reserved_5[0x20]; 5985 }; 5986 5987 struct mlx5_ifc_slrg_reg_bits { 5988 u8 status[0x4]; 5989 u8 version[0x4]; 5990 u8 local_port[0x8]; 5991 u8 pnat[0x2]; 5992 u8 reserved_0[0x2]; 5993 u8 lane[0x4]; 5994 u8 reserved_1[0x8]; 5995 5996 u8 time_to_link_up[0x10]; 5997 u8 reserved_2[0xc]; 5998 u8 grade_lane_speed[0x4]; 5999 6000 u8 grade_version[0x8]; 6001 u8 grade[0x18]; 6002 6003 u8 reserved_3[0x4]; 6004 u8 height_grade_type[0x4]; 6005 u8 height_grade[0x18]; 6006 6007 u8 height_dz[0x10]; 6008 u8 height_dv[0x10]; 6009 6010 u8 reserved_4[0x10]; 6011 u8 height_sigma[0x10]; 6012 6013 u8 reserved_5[0x20]; 6014 6015 u8 reserved_6[0x4]; 6016 u8 phase_grade_type[0x4]; 6017 u8 phase_grade[0x18]; 6018 6019 u8 reserved_7[0x8]; 6020 u8 phase_eo_pos[0x8]; 6021 u8 reserved_8[0x8]; 6022 u8 phase_eo_neg[0x8]; 6023 6024 u8 ffe_set_tested[0x10]; 6025 u8 test_errors_per_lane[0x10]; 6026 }; 6027 6028 struct mlx5_ifc_pvlc_reg_bits { 6029 u8 reserved_0[0x8]; 6030 u8 local_port[0x8]; 6031 u8 reserved_1[0x10]; 6032 6033 u8 reserved_2[0x1c]; 6034 u8 vl_hw_cap[0x4]; 6035 6036 u8 reserved_3[0x1c]; 6037 u8 vl_admin[0x4]; 6038 6039 u8 reserved_4[0x1c]; 6040 u8 vl_operational[0x4]; 6041 }; 6042 6043 struct mlx5_ifc_pude_reg_bits { 6044 u8 swid[0x8]; 6045 u8 local_port[0x8]; 6046 u8 reserved_0[0x4]; 6047 u8 admin_status[0x4]; 6048 u8 reserved_1[0x4]; 6049 u8 oper_status[0x4]; 6050 6051 u8 reserved_2[0x60]; 6052 }; 6053 6054 struct mlx5_ifc_ptys_reg_bits { 6055 u8 reserved_0[0x8]; 6056 u8 local_port[0x8]; 6057 u8 reserved_1[0xd]; 6058 u8 proto_mask[0x3]; 6059 6060 u8 reserved_2[0x40]; 6061 6062 u8 eth_proto_capability[0x20]; 6063 6064 u8 ib_link_width_capability[0x10]; 6065 u8 ib_proto_capability[0x10]; 6066 6067 u8 reserved_3[0x20]; 6068 6069 u8 eth_proto_admin[0x20]; 6070 6071 u8 ib_link_width_admin[0x10]; 6072 u8 ib_proto_admin[0x10]; 6073 6074 u8 reserved_4[0x20]; 6075 6076 u8 eth_proto_oper[0x20]; 6077 6078 u8 ib_link_width_oper[0x10]; 6079 u8 ib_proto_oper[0x10]; 6080 6081 u8 reserved_5[0x20]; 6082 6083 u8 eth_proto_lp_advertise[0x20]; 6084 6085 u8 reserved_6[0x60]; 6086 }; 6087 6088 struct mlx5_ifc_ptas_reg_bits { 6089 u8 reserved_0[0x20]; 6090 6091 u8 algorithm_options[0x10]; 6092 u8 reserved_1[0x4]; 6093 u8 repetitions_mode[0x4]; 6094 u8 num_of_repetitions[0x8]; 6095 6096 u8 grade_version[0x8]; 6097 u8 height_grade_type[0x4]; 6098 u8 phase_grade_type[0x4]; 6099 u8 height_grade_weight[0x8]; 6100 u8 phase_grade_weight[0x8]; 6101 6102 u8 gisim_measure_bits[0x10]; 6103 u8 adaptive_tap_measure_bits[0x10]; 6104 6105 u8 ber_bath_high_error_threshold[0x10]; 6106 u8 ber_bath_mid_error_threshold[0x10]; 6107 6108 u8 ber_bath_low_error_threshold[0x10]; 6109 u8 one_ratio_high_threshold[0x10]; 6110 6111 u8 one_ratio_high_mid_threshold[0x10]; 6112 u8 one_ratio_low_mid_threshold[0x10]; 6113 6114 u8 one_ratio_low_threshold[0x10]; 6115 u8 ndeo_error_threshold[0x10]; 6116 6117 u8 mixer_offset_step_size[0x10]; 6118 u8 reserved_2[0x8]; 6119 u8 mix90_phase_for_voltage_bath[0x8]; 6120 6121 u8 mixer_offset_start[0x10]; 6122 u8 mixer_offset_end[0x10]; 6123 6124 u8 reserved_3[0x15]; 6125 u8 ber_test_time[0xb]; 6126 }; 6127 6128 struct mlx5_ifc_pspa_reg_bits { 6129 u8 swid[0x8]; 6130 u8 local_port[0x8]; 6131 u8 sub_port[0x8]; 6132 u8 reserved_0[0x8]; 6133 6134 u8 reserved_1[0x20]; 6135 }; 6136 6137 struct mlx5_ifc_pqdr_reg_bits { 6138 u8 reserved_0[0x8]; 6139 u8 local_port[0x8]; 6140 u8 reserved_1[0x5]; 6141 u8 prio[0x3]; 6142 u8 reserved_2[0x6]; 6143 u8 mode[0x2]; 6144 6145 u8 reserved_3[0x20]; 6146 6147 u8 reserved_4[0x10]; 6148 u8 min_threshold[0x10]; 6149 6150 u8 reserved_5[0x10]; 6151 u8 max_threshold[0x10]; 6152 6153 u8 reserved_6[0x10]; 6154 u8 mark_probability_denominator[0x10]; 6155 6156 u8 reserved_7[0x60]; 6157 }; 6158 6159 struct mlx5_ifc_ppsc_reg_bits { 6160 u8 reserved_0[0x8]; 6161 u8 local_port[0x8]; 6162 u8 reserved_1[0x10]; 6163 6164 u8 reserved_2[0x60]; 6165 6166 u8 reserved_3[0x1c]; 6167 u8 wrps_admin[0x4]; 6168 6169 u8 reserved_4[0x1c]; 6170 u8 wrps_status[0x4]; 6171 6172 u8 reserved_5[0x8]; 6173 u8 up_threshold[0x8]; 6174 u8 reserved_6[0x8]; 6175 u8 down_threshold[0x8]; 6176 6177 u8 reserved_7[0x20]; 6178 6179 u8 reserved_8[0x1c]; 6180 u8 srps_admin[0x4]; 6181 6182 u8 reserved_9[0x1c]; 6183 u8 srps_status[0x4]; 6184 6185 u8 reserved_10[0x40]; 6186 }; 6187 6188 struct mlx5_ifc_pplr_reg_bits { 6189 u8 reserved_0[0x8]; 6190 u8 local_port[0x8]; 6191 u8 reserved_1[0x10]; 6192 6193 u8 reserved_2[0x8]; 6194 u8 lb_cap[0x8]; 6195 u8 reserved_3[0x8]; 6196 u8 lb_en[0x8]; 6197 }; 6198 6199 struct mlx5_ifc_pplm_reg_bits { 6200 u8 reserved_0[0x8]; 6201 u8 local_port[0x8]; 6202 u8 reserved_1[0x10]; 6203 6204 u8 reserved_2[0x20]; 6205 6206 u8 port_profile_mode[0x8]; 6207 u8 static_port_profile[0x8]; 6208 u8 active_port_profile[0x8]; 6209 u8 reserved_3[0x8]; 6210 6211 u8 retransmission_active[0x8]; 6212 u8 fec_mode_active[0x18]; 6213 6214 u8 reserved_4[0x20]; 6215 }; 6216 6217 struct mlx5_ifc_ppcnt_reg_bits { 6218 u8 swid[0x8]; 6219 u8 local_port[0x8]; 6220 u8 pnat[0x2]; 6221 u8 reserved_0[0x8]; 6222 u8 grp[0x6]; 6223 6224 u8 clr[0x1]; 6225 u8 reserved_1[0x1c]; 6226 u8 prio_tc[0x3]; 6227 6228 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 6229 }; 6230 6231 struct mlx5_ifc_ppad_reg_bits { 6232 u8 reserved_0[0x3]; 6233 u8 single_mac[0x1]; 6234 u8 reserved_1[0x4]; 6235 u8 local_port[0x8]; 6236 u8 mac_47_32[0x10]; 6237 6238 u8 mac_31_0[0x20]; 6239 6240 u8 reserved_2[0x40]; 6241 }; 6242 6243 struct mlx5_ifc_pmtu_reg_bits { 6244 u8 reserved_0[0x8]; 6245 u8 local_port[0x8]; 6246 u8 reserved_1[0x10]; 6247 6248 u8 max_mtu[0x10]; 6249 u8 reserved_2[0x10]; 6250 6251 u8 admin_mtu[0x10]; 6252 u8 reserved_3[0x10]; 6253 6254 u8 oper_mtu[0x10]; 6255 u8 reserved_4[0x10]; 6256 }; 6257 6258 struct mlx5_ifc_pmpr_reg_bits { 6259 u8 reserved_0[0x8]; 6260 u8 module[0x8]; 6261 u8 reserved_1[0x10]; 6262 6263 u8 reserved_2[0x18]; 6264 u8 attenuation_5g[0x8]; 6265 6266 u8 reserved_3[0x18]; 6267 u8 attenuation_7g[0x8]; 6268 6269 u8 reserved_4[0x18]; 6270 u8 attenuation_12g[0x8]; 6271 }; 6272 6273 struct mlx5_ifc_pmpe_reg_bits { 6274 u8 reserved_0[0x8]; 6275 u8 module[0x8]; 6276 u8 reserved_1[0xc]; 6277 u8 module_status[0x4]; 6278 6279 u8 reserved_2[0x60]; 6280 }; 6281 6282 struct mlx5_ifc_pmpc_reg_bits { 6283 u8 module_state_updated[32][0x8]; 6284 }; 6285 6286 struct mlx5_ifc_pmlpn_reg_bits { 6287 u8 reserved_0[0x4]; 6288 u8 mlpn_status[0x4]; 6289 u8 local_port[0x8]; 6290 u8 reserved_1[0x10]; 6291 6292 u8 e[0x1]; 6293 u8 reserved_2[0x1f]; 6294 }; 6295 6296 struct mlx5_ifc_pmlp_reg_bits { 6297 u8 rxtx[0x1]; 6298 u8 reserved_0[0x7]; 6299 u8 local_port[0x8]; 6300 u8 reserved_1[0x8]; 6301 u8 width[0x8]; 6302 6303 u8 lane0_module_mapping[0x20]; 6304 6305 u8 lane1_module_mapping[0x20]; 6306 6307 u8 lane2_module_mapping[0x20]; 6308 6309 u8 lane3_module_mapping[0x20]; 6310 6311 u8 reserved_2[0x160]; 6312 }; 6313 6314 struct mlx5_ifc_pmaos_reg_bits { 6315 u8 reserved_0[0x8]; 6316 u8 module[0x8]; 6317 u8 reserved_1[0x4]; 6318 u8 admin_status[0x4]; 6319 u8 reserved_2[0x4]; 6320 u8 oper_status[0x4]; 6321 6322 u8 ase[0x1]; 6323 u8 ee[0x1]; 6324 u8 reserved_3[0x1c]; 6325 u8 e[0x2]; 6326 6327 u8 reserved_4[0x40]; 6328 }; 6329 6330 struct mlx5_ifc_plpc_reg_bits { 6331 u8 reserved_0[0x4]; 6332 u8 profile_id[0xc]; 6333 u8 reserved_1[0x4]; 6334 u8 proto_mask[0x4]; 6335 u8 reserved_2[0x8]; 6336 6337 u8 reserved_3[0x10]; 6338 u8 lane_speed[0x10]; 6339 6340 u8 reserved_4[0x17]; 6341 u8 lpbf[0x1]; 6342 u8 fec_mode_policy[0x8]; 6343 6344 u8 retransmission_capability[0x8]; 6345 u8 fec_mode_capability[0x18]; 6346 6347 u8 retransmission_support_admin[0x8]; 6348 u8 fec_mode_support_admin[0x18]; 6349 6350 u8 retransmission_request_admin[0x8]; 6351 u8 fec_mode_request_admin[0x18]; 6352 6353 u8 reserved_5[0x80]; 6354 }; 6355 6356 struct mlx5_ifc_plib_reg_bits { 6357 u8 reserved_0[0x8]; 6358 u8 local_port[0x8]; 6359 u8 reserved_1[0x8]; 6360 u8 ib_port[0x8]; 6361 6362 u8 reserved_2[0x60]; 6363 }; 6364 6365 struct mlx5_ifc_plbf_reg_bits { 6366 u8 reserved_0[0x8]; 6367 u8 local_port[0x8]; 6368 u8 reserved_1[0xd]; 6369 u8 lbf_mode[0x3]; 6370 6371 u8 reserved_2[0x20]; 6372 }; 6373 6374 struct mlx5_ifc_pipg_reg_bits { 6375 u8 reserved_0[0x8]; 6376 u8 local_port[0x8]; 6377 u8 reserved_1[0x10]; 6378 6379 u8 dic[0x1]; 6380 u8 reserved_2[0x19]; 6381 u8 ipg[0x4]; 6382 u8 reserved_3[0x2]; 6383 }; 6384 6385 struct mlx5_ifc_pifr_reg_bits { 6386 u8 reserved_0[0x8]; 6387 u8 local_port[0x8]; 6388 u8 reserved_1[0x10]; 6389 6390 u8 reserved_2[0xe0]; 6391 6392 u8 port_filter[8][0x20]; 6393 6394 u8 port_filter_update_en[8][0x20]; 6395 }; 6396 6397 struct mlx5_ifc_pfcc_reg_bits { 6398 u8 reserved_0[0x8]; 6399 u8 local_port[0x8]; 6400 u8 reserved_1[0x10]; 6401 6402 u8 ppan[0x4]; 6403 u8 reserved_2[0x4]; 6404 u8 prio_mask_tx[0x8]; 6405 u8 reserved_3[0x8]; 6406 u8 prio_mask_rx[0x8]; 6407 6408 u8 pptx[0x1]; 6409 u8 aptx[0x1]; 6410 u8 reserved_4[0x6]; 6411 u8 pfctx[0x8]; 6412 u8 reserved_5[0x10]; 6413 6414 u8 pprx[0x1]; 6415 u8 aprx[0x1]; 6416 u8 reserved_6[0x6]; 6417 u8 pfcrx[0x8]; 6418 u8 reserved_7[0x10]; 6419 6420 u8 reserved_8[0x80]; 6421 }; 6422 6423 struct mlx5_ifc_pelc_reg_bits { 6424 u8 op[0x4]; 6425 u8 reserved_0[0x4]; 6426 u8 local_port[0x8]; 6427 u8 reserved_1[0x10]; 6428 6429 u8 op_admin[0x8]; 6430 u8 op_capability[0x8]; 6431 u8 op_request[0x8]; 6432 u8 op_active[0x8]; 6433 6434 u8 admin[0x40]; 6435 6436 u8 capability[0x40]; 6437 6438 u8 request[0x40]; 6439 6440 u8 active[0x40]; 6441 6442 u8 reserved_2[0x80]; 6443 }; 6444 6445 struct mlx5_ifc_peir_reg_bits { 6446 u8 reserved_0[0x8]; 6447 u8 local_port[0x8]; 6448 u8 reserved_1[0x10]; 6449 6450 u8 reserved_2[0xc]; 6451 u8 error_count[0x4]; 6452 u8 reserved_3[0x10]; 6453 6454 u8 reserved_4[0xc]; 6455 u8 lane[0x4]; 6456 u8 reserved_5[0x8]; 6457 u8 error_type[0x8]; 6458 }; 6459 6460 struct mlx5_ifc_pcap_reg_bits { 6461 u8 reserved_0[0x8]; 6462 u8 local_port[0x8]; 6463 u8 reserved_1[0x10]; 6464 6465 u8 port_capability_mask[4][0x20]; 6466 }; 6467 6468 struct mlx5_ifc_paos_reg_bits { 6469 u8 swid[0x8]; 6470 u8 local_port[0x8]; 6471 u8 reserved_0[0x4]; 6472 u8 admin_status[0x4]; 6473 u8 reserved_1[0x4]; 6474 u8 oper_status[0x4]; 6475 6476 u8 ase[0x1]; 6477 u8 ee[0x1]; 6478 u8 reserved_2[0x1c]; 6479 u8 e[0x2]; 6480 6481 u8 reserved_3[0x40]; 6482 }; 6483 6484 struct mlx5_ifc_pamp_reg_bits { 6485 u8 reserved_0[0x8]; 6486 u8 opamp_group[0x8]; 6487 u8 reserved_1[0xc]; 6488 u8 opamp_group_type[0x4]; 6489 6490 u8 start_index[0x10]; 6491 u8 reserved_2[0x4]; 6492 u8 num_of_indices[0xc]; 6493 6494 u8 index_data[18][0x10]; 6495 }; 6496 6497 struct mlx5_ifc_lane_2_module_mapping_bits { 6498 u8 reserved_0[0x6]; 6499 u8 rx_lane[0x2]; 6500 u8 reserved_1[0x6]; 6501 u8 tx_lane[0x2]; 6502 u8 reserved_2[0x8]; 6503 u8 module[0x8]; 6504 }; 6505 6506 struct mlx5_ifc_bufferx_reg_bits { 6507 u8 reserved_0[0x6]; 6508 u8 lossy[0x1]; 6509 u8 epsb[0x1]; 6510 u8 reserved_1[0xc]; 6511 u8 size[0xc]; 6512 6513 u8 xoff_threshold[0x10]; 6514 u8 xon_threshold[0x10]; 6515 }; 6516 6517 struct mlx5_ifc_set_node_in_bits { 6518 u8 node_description[64][0x8]; 6519 }; 6520 6521 struct mlx5_ifc_register_power_settings_bits { 6522 u8 reserved_0[0x18]; 6523 u8 power_settings_level[0x8]; 6524 6525 u8 reserved_1[0x60]; 6526 }; 6527 6528 struct mlx5_ifc_register_host_endianness_bits { 6529 u8 he[0x1]; 6530 u8 reserved_0[0x1f]; 6531 6532 u8 reserved_1[0x60]; 6533 }; 6534 6535 struct mlx5_ifc_umr_pointer_desc_argument_bits { 6536 u8 reserved_0[0x20]; 6537 6538 u8 mkey[0x20]; 6539 6540 u8 addressh_63_32[0x20]; 6541 6542 u8 addressl_31_0[0x20]; 6543 }; 6544 6545 struct mlx5_ifc_ud_adrs_vector_bits { 6546 u8 dc_key[0x40]; 6547 6548 u8 ext[0x1]; 6549 u8 reserved_0[0x7]; 6550 u8 destination_qp_dct[0x18]; 6551 6552 u8 static_rate[0x4]; 6553 u8 sl_eth_prio[0x4]; 6554 u8 fl[0x1]; 6555 u8 mlid[0x7]; 6556 u8 rlid_udp_sport[0x10]; 6557 6558 u8 reserved_1[0x20]; 6559 6560 u8 rmac_47_16[0x20]; 6561 6562 u8 rmac_15_0[0x10]; 6563 u8 tclass[0x8]; 6564 u8 hop_limit[0x8]; 6565 6566 u8 reserved_2[0x1]; 6567 u8 grh[0x1]; 6568 u8 reserved_3[0x2]; 6569 u8 src_addr_index[0x8]; 6570 u8 flow_label[0x14]; 6571 6572 u8 rgid_rip[16][0x8]; 6573 }; 6574 6575 struct mlx5_ifc_pages_req_event_bits { 6576 u8 reserved_0[0x10]; 6577 u8 function_id[0x10]; 6578 6579 u8 num_pages[0x20]; 6580 6581 u8 reserved_1[0xa0]; 6582 }; 6583 6584 struct mlx5_ifc_eqe_bits { 6585 u8 reserved_0[0x8]; 6586 u8 event_type[0x8]; 6587 u8 reserved_1[0x8]; 6588 u8 event_sub_type[0x8]; 6589 6590 u8 reserved_2[0xe0]; 6591 6592 union mlx5_ifc_event_auto_bits event_data; 6593 6594 u8 reserved_3[0x10]; 6595 u8 signature[0x8]; 6596 u8 reserved_4[0x7]; 6597 u8 owner[0x1]; 6598 }; 6599 6600 enum { 6601 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 6602 }; 6603 6604 struct mlx5_ifc_cmd_queue_entry_bits { 6605 u8 type[0x8]; 6606 u8 reserved_0[0x18]; 6607 6608 u8 input_length[0x20]; 6609 6610 u8 input_mailbox_pointer_63_32[0x20]; 6611 6612 u8 input_mailbox_pointer_31_9[0x17]; 6613 u8 reserved_1[0x9]; 6614 6615 u8 command_input_inline_data[16][0x8]; 6616 6617 u8 command_output_inline_data[16][0x8]; 6618 6619 u8 output_mailbox_pointer_63_32[0x20]; 6620 6621 u8 output_mailbox_pointer_31_9[0x17]; 6622 u8 reserved_2[0x9]; 6623 6624 u8 output_length[0x20]; 6625 6626 u8 token[0x8]; 6627 u8 signature[0x8]; 6628 u8 reserved_3[0x8]; 6629 u8 status[0x7]; 6630 u8 ownership[0x1]; 6631 }; 6632 6633 struct mlx5_ifc_cmd_out_bits { 6634 u8 status[0x8]; 6635 u8 reserved_0[0x18]; 6636 6637 u8 syndrome[0x20]; 6638 6639 u8 command_output[0x20]; 6640 }; 6641 6642 struct mlx5_ifc_cmd_in_bits { 6643 u8 opcode[0x10]; 6644 u8 reserved_0[0x10]; 6645 6646 u8 reserved_1[0x10]; 6647 u8 op_mod[0x10]; 6648 6649 u8 command[0][0x20]; 6650 }; 6651 6652 struct mlx5_ifc_cmd_if_box_bits { 6653 u8 mailbox_data[512][0x8]; 6654 6655 u8 reserved_0[0x180]; 6656 6657 u8 next_pointer_63_32[0x20]; 6658 6659 u8 next_pointer_31_10[0x16]; 6660 u8 reserved_1[0xa]; 6661 6662 u8 block_number[0x20]; 6663 6664 u8 reserved_2[0x8]; 6665 u8 token[0x8]; 6666 u8 ctrl_signature[0x8]; 6667 u8 signature[0x8]; 6668 }; 6669 6670 struct mlx5_ifc_mtt_bits { 6671 u8 ptag_63_32[0x20]; 6672 6673 u8 ptag_31_8[0x18]; 6674 u8 reserved_0[0x6]; 6675 u8 wr_en[0x1]; 6676 u8 rd_en[0x1]; 6677 }; 6678 6679 enum { 6680 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 6681 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 6682 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 6683 }; 6684 6685 enum { 6686 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 6687 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 6688 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 6689 }; 6690 6691 enum { 6692 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 6693 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 6694 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 6695 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 6696 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 6697 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 6698 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 6699 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 6700 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 6701 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 6702 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 6703 }; 6704 6705 struct mlx5_ifc_initial_seg_bits { 6706 u8 fw_rev_minor[0x10]; 6707 u8 fw_rev_major[0x10]; 6708 6709 u8 cmd_interface_rev[0x10]; 6710 u8 fw_rev_subminor[0x10]; 6711 6712 u8 reserved_0[0x40]; 6713 6714 u8 cmdq_phy_addr_63_32[0x20]; 6715 6716 u8 cmdq_phy_addr_31_12[0x14]; 6717 u8 reserved_1[0x2]; 6718 u8 nic_interface[0x2]; 6719 u8 log_cmdq_size[0x4]; 6720 u8 log_cmdq_stride[0x4]; 6721 6722 u8 command_doorbell_vector[0x20]; 6723 6724 u8 reserved_2[0xf00]; 6725 6726 u8 initializing[0x1]; 6727 u8 reserved_3[0x4]; 6728 u8 nic_interface_supported[0x3]; 6729 u8 reserved_4[0x18]; 6730 6731 struct mlx5_ifc_health_buffer_bits health_buffer; 6732 6733 u8 no_dram_nic_offset[0x20]; 6734 6735 u8 reserved_5[0x6e40]; 6736 6737 u8 reserved_6[0x1f]; 6738 u8 clear_int[0x1]; 6739 6740 u8 health_syndrome[0x8]; 6741 u8 health_counter[0x18]; 6742 6743 u8 reserved_7[0x17fc0]; 6744 }; 6745 6746 union mlx5_ifc_ports_control_registers_document_bits { 6747 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 6748 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 6749 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 6750 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 6751 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 6752 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 6753 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 6754 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 6755 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 6756 struct mlx5_ifc_pamp_reg_bits pamp_reg; 6757 struct mlx5_ifc_paos_reg_bits paos_reg; 6758 struct mlx5_ifc_pcap_reg_bits pcap_reg; 6759 struct mlx5_ifc_peir_reg_bits peir_reg; 6760 struct mlx5_ifc_pelc_reg_bits pelc_reg; 6761 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 6762 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 6763 struct mlx5_ifc_pifr_reg_bits pifr_reg; 6764 struct mlx5_ifc_pipg_reg_bits pipg_reg; 6765 struct mlx5_ifc_plbf_reg_bits plbf_reg; 6766 struct mlx5_ifc_plib_reg_bits plib_reg; 6767 struct mlx5_ifc_plpc_reg_bits plpc_reg; 6768 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 6769 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 6770 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 6771 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 6772 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 6773 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 6774 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 6775 struct mlx5_ifc_ppad_reg_bits ppad_reg; 6776 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 6777 struct mlx5_ifc_pplm_reg_bits pplm_reg; 6778 struct mlx5_ifc_pplr_reg_bits pplr_reg; 6779 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 6780 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 6781 struct mlx5_ifc_pspa_reg_bits pspa_reg; 6782 struct mlx5_ifc_ptas_reg_bits ptas_reg; 6783 struct mlx5_ifc_ptys_reg_bits ptys_reg; 6784 struct mlx5_ifc_pude_reg_bits pude_reg; 6785 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 6786 struct mlx5_ifc_slrg_reg_bits slrg_reg; 6787 struct mlx5_ifc_sltp_reg_bits sltp_reg; 6788 u8 reserved_0[0x60e0]; 6789 }; 6790 6791 union mlx5_ifc_debug_enhancements_document_bits { 6792 struct mlx5_ifc_health_buffer_bits health_buffer; 6793 u8 reserved_0[0x200]; 6794 }; 6795 6796 union mlx5_ifc_uplink_pci_interface_document_bits { 6797 struct mlx5_ifc_initial_seg_bits initial_seg; 6798 u8 reserved_0[0x20060]; 6799 }; 6800 6801 #endif /* MLX5_IFC_H */ 6802