1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 85 }; 86 87 enum { 88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 90 }; 91 92 enum { 93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 94 MLX5_OBJ_TYPE_MKEY = 0xff01, 95 MLX5_OBJ_TYPE_QP = 0xff02, 96 MLX5_OBJ_TYPE_PSV = 0xff03, 97 MLX5_OBJ_TYPE_RMP = 0xff04, 98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 99 MLX5_OBJ_TYPE_RQ = 0xff06, 100 MLX5_OBJ_TYPE_SQ = 0xff07, 101 MLX5_OBJ_TYPE_TIR = 0xff08, 102 MLX5_OBJ_TYPE_TIS = 0xff09, 103 MLX5_OBJ_TYPE_DCT = 0xff0a, 104 MLX5_OBJ_TYPE_XRQ = 0xff0b, 105 MLX5_OBJ_TYPE_RQT = 0xff0e, 106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 107 MLX5_OBJ_TYPE_CQ = 0xff10, 108 }; 109 110 enum { 111 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 112 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 113 MLX5_CMD_OP_INIT_HCA = 0x102, 114 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 115 MLX5_CMD_OP_ENABLE_HCA = 0x104, 116 MLX5_CMD_OP_DISABLE_HCA = 0x105, 117 MLX5_CMD_OP_QUERY_PAGES = 0x107, 118 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 119 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 120 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 121 MLX5_CMD_OP_SET_ISSI = 0x10b, 122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 124 MLX5_CMD_OP_ALLOC_SF = 0x113, 125 MLX5_CMD_OP_DEALLOC_SF = 0x114, 126 MLX5_CMD_OP_CREATE_MKEY = 0x200, 127 MLX5_CMD_OP_QUERY_MKEY = 0x201, 128 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 130 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 131 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 132 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 133 MLX5_CMD_OP_CREATE_EQ = 0x301, 134 MLX5_CMD_OP_DESTROY_EQ = 0x302, 135 MLX5_CMD_OP_QUERY_EQ = 0x303, 136 MLX5_CMD_OP_GEN_EQE = 0x304, 137 MLX5_CMD_OP_CREATE_CQ = 0x400, 138 MLX5_CMD_OP_DESTROY_CQ = 0x401, 139 MLX5_CMD_OP_QUERY_CQ = 0x402, 140 MLX5_CMD_OP_MODIFY_CQ = 0x403, 141 MLX5_CMD_OP_CREATE_QP = 0x500, 142 MLX5_CMD_OP_DESTROY_QP = 0x501, 143 MLX5_CMD_OP_RST2INIT_QP = 0x502, 144 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 145 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 146 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 147 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 148 MLX5_CMD_OP_2ERR_QP = 0x507, 149 MLX5_CMD_OP_2RST_QP = 0x50a, 150 MLX5_CMD_OP_QUERY_QP = 0x50b, 151 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 152 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 153 MLX5_CMD_OP_CREATE_PSV = 0x600, 154 MLX5_CMD_OP_DESTROY_PSV = 0x601, 155 MLX5_CMD_OP_CREATE_SRQ = 0x700, 156 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 157 MLX5_CMD_OP_QUERY_SRQ = 0x702, 158 MLX5_CMD_OP_ARM_RQ = 0x703, 159 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 160 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 161 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 162 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 163 MLX5_CMD_OP_CREATE_DCT = 0x710, 164 MLX5_CMD_OP_DESTROY_DCT = 0x711, 165 MLX5_CMD_OP_DRAIN_DCT = 0x712, 166 MLX5_CMD_OP_QUERY_DCT = 0x713, 167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 168 MLX5_CMD_OP_CREATE_XRQ = 0x717, 169 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 170 MLX5_CMD_OP_QUERY_XRQ = 0x719, 171 MLX5_CMD_OP_ARM_XRQ = 0x71a, 172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 175 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 176 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 177 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 178 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 179 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 180 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 181 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 182 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 183 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 184 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 185 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 186 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 187 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 188 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 190 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 191 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 192 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 193 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 194 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 195 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 196 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 197 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 198 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 199 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 200 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 201 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 202 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 203 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 204 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 205 MLX5_CMD_OP_ALLOC_PD = 0x800, 206 MLX5_CMD_OP_DEALLOC_PD = 0x801, 207 MLX5_CMD_OP_ALLOC_UAR = 0x802, 208 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 209 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 210 MLX5_CMD_OP_ACCESS_REG = 0x805, 211 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 212 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 213 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 214 MLX5_CMD_OP_MAD_IFC = 0x50d, 215 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 216 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 217 MLX5_CMD_OP_NOP = 0x80d, 218 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 219 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 220 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 221 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 222 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 223 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 224 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 225 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 226 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 227 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 228 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 229 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 230 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 231 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 232 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 233 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 234 MLX5_CMD_OP_CREATE_LAG = 0x840, 235 MLX5_CMD_OP_MODIFY_LAG = 0x841, 236 MLX5_CMD_OP_QUERY_LAG = 0x842, 237 MLX5_CMD_OP_DESTROY_LAG = 0x843, 238 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 239 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 240 MLX5_CMD_OP_CREATE_TIR = 0x900, 241 MLX5_CMD_OP_MODIFY_TIR = 0x901, 242 MLX5_CMD_OP_DESTROY_TIR = 0x902, 243 MLX5_CMD_OP_QUERY_TIR = 0x903, 244 MLX5_CMD_OP_CREATE_SQ = 0x904, 245 MLX5_CMD_OP_MODIFY_SQ = 0x905, 246 MLX5_CMD_OP_DESTROY_SQ = 0x906, 247 MLX5_CMD_OP_QUERY_SQ = 0x907, 248 MLX5_CMD_OP_CREATE_RQ = 0x908, 249 MLX5_CMD_OP_MODIFY_RQ = 0x909, 250 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 251 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 252 MLX5_CMD_OP_QUERY_RQ = 0x90b, 253 MLX5_CMD_OP_CREATE_RMP = 0x90c, 254 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 255 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 256 MLX5_CMD_OP_QUERY_RMP = 0x90f, 257 MLX5_CMD_OP_CREATE_TIS = 0x912, 258 MLX5_CMD_OP_MODIFY_TIS = 0x913, 259 MLX5_CMD_OP_DESTROY_TIS = 0x914, 260 MLX5_CMD_OP_QUERY_TIS = 0x915, 261 MLX5_CMD_OP_CREATE_RQT = 0x916, 262 MLX5_CMD_OP_MODIFY_RQT = 0x917, 263 MLX5_CMD_OP_DESTROY_RQT = 0x918, 264 MLX5_CMD_OP_QUERY_RQT = 0x919, 265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 266 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 267 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 268 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 269 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 270 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 271 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 277 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 278 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 288 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 290 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 291 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 292 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 293 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 294 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 295 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 296 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 297 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 298 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 299 MLX5_CMD_OP_MAX 300 }; 301 302 /* Valid range for general commands that don't work over an object */ 303 enum { 304 MLX5_CMD_OP_GENERAL_START = 0xb00, 305 MLX5_CMD_OP_GENERAL_END = 0xd00, 306 }; 307 308 struct mlx5_ifc_flow_table_fields_supported_bits { 309 u8 outer_dmac[0x1]; 310 u8 outer_smac[0x1]; 311 u8 outer_ether_type[0x1]; 312 u8 outer_ip_version[0x1]; 313 u8 outer_first_prio[0x1]; 314 u8 outer_first_cfi[0x1]; 315 u8 outer_first_vid[0x1]; 316 u8 outer_ipv4_ttl[0x1]; 317 u8 outer_second_prio[0x1]; 318 u8 outer_second_cfi[0x1]; 319 u8 outer_second_vid[0x1]; 320 u8 reserved_at_b[0x1]; 321 u8 outer_sip[0x1]; 322 u8 outer_dip[0x1]; 323 u8 outer_frag[0x1]; 324 u8 outer_ip_protocol[0x1]; 325 u8 outer_ip_ecn[0x1]; 326 u8 outer_ip_dscp[0x1]; 327 u8 outer_udp_sport[0x1]; 328 u8 outer_udp_dport[0x1]; 329 u8 outer_tcp_sport[0x1]; 330 u8 outer_tcp_dport[0x1]; 331 u8 outer_tcp_flags[0x1]; 332 u8 outer_gre_protocol[0x1]; 333 u8 outer_gre_key[0x1]; 334 u8 outer_vxlan_vni[0x1]; 335 u8 outer_geneve_vni[0x1]; 336 u8 outer_geneve_oam[0x1]; 337 u8 outer_geneve_protocol_type[0x1]; 338 u8 outer_geneve_opt_len[0x1]; 339 u8 reserved_at_1e[0x1]; 340 u8 source_eswitch_port[0x1]; 341 342 u8 inner_dmac[0x1]; 343 u8 inner_smac[0x1]; 344 u8 inner_ether_type[0x1]; 345 u8 inner_ip_version[0x1]; 346 u8 inner_first_prio[0x1]; 347 u8 inner_first_cfi[0x1]; 348 u8 inner_first_vid[0x1]; 349 u8 reserved_at_27[0x1]; 350 u8 inner_second_prio[0x1]; 351 u8 inner_second_cfi[0x1]; 352 u8 inner_second_vid[0x1]; 353 u8 reserved_at_2b[0x1]; 354 u8 inner_sip[0x1]; 355 u8 inner_dip[0x1]; 356 u8 inner_frag[0x1]; 357 u8 inner_ip_protocol[0x1]; 358 u8 inner_ip_ecn[0x1]; 359 u8 inner_ip_dscp[0x1]; 360 u8 inner_udp_sport[0x1]; 361 u8 inner_udp_dport[0x1]; 362 u8 inner_tcp_sport[0x1]; 363 u8 inner_tcp_dport[0x1]; 364 u8 inner_tcp_flags[0x1]; 365 u8 reserved_at_37[0x9]; 366 367 u8 geneve_tlv_option_0_data[0x1]; 368 u8 reserved_at_41[0x4]; 369 u8 outer_first_mpls_over_udp[0x4]; 370 u8 outer_first_mpls_over_gre[0x4]; 371 u8 inner_first_mpls[0x4]; 372 u8 outer_first_mpls[0x4]; 373 u8 reserved_at_55[0x2]; 374 u8 outer_esp_spi[0x1]; 375 u8 reserved_at_58[0x2]; 376 u8 bth_dst_qp[0x1]; 377 378 u8 reserved_at_5b[0x25]; 379 }; 380 381 struct mlx5_ifc_flow_table_prop_layout_bits { 382 u8 ft_support[0x1]; 383 u8 reserved_at_1[0x1]; 384 u8 flow_counter[0x1]; 385 u8 flow_modify_en[0x1]; 386 u8 modify_root[0x1]; 387 u8 identified_miss_table_mode[0x1]; 388 u8 flow_table_modify[0x1]; 389 u8 reformat[0x1]; 390 u8 decap[0x1]; 391 u8 reserved_at_9[0x1]; 392 u8 pop_vlan[0x1]; 393 u8 push_vlan[0x1]; 394 u8 reserved_at_c[0x1]; 395 u8 pop_vlan_2[0x1]; 396 u8 push_vlan_2[0x1]; 397 u8 reformat_and_vlan_action[0x1]; 398 u8 reserved_at_10[0x1]; 399 u8 sw_owner[0x1]; 400 u8 reformat_l3_tunnel_to_l2[0x1]; 401 u8 reformat_l2_to_l3_tunnel[0x1]; 402 u8 reformat_and_modify_action[0x1]; 403 u8 reserved_at_15[0x2]; 404 u8 table_miss_action_domain[0x1]; 405 u8 termination_table[0x1]; 406 u8 reserved_at_19[0x7]; 407 u8 reserved_at_20[0x2]; 408 u8 log_max_ft_size[0x6]; 409 u8 log_max_modify_header_context[0x8]; 410 u8 max_modify_header_actions[0x8]; 411 u8 max_ft_level[0x8]; 412 413 u8 reserved_at_40[0x20]; 414 415 u8 reserved_at_60[0x18]; 416 u8 log_max_ft_num[0x8]; 417 418 u8 reserved_at_80[0x18]; 419 u8 log_max_destination[0x8]; 420 421 u8 log_max_flow_counter[0x8]; 422 u8 reserved_at_a8[0x10]; 423 u8 log_max_flow[0x8]; 424 425 u8 reserved_at_c0[0x40]; 426 427 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 428 429 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 430 }; 431 432 struct mlx5_ifc_odp_per_transport_service_cap_bits { 433 u8 send[0x1]; 434 u8 receive[0x1]; 435 u8 write[0x1]; 436 u8 read[0x1]; 437 u8 atomic[0x1]; 438 u8 srq_receive[0x1]; 439 u8 reserved_at_6[0x1a]; 440 }; 441 442 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 443 u8 smac_47_16[0x20]; 444 445 u8 smac_15_0[0x10]; 446 u8 ethertype[0x10]; 447 448 u8 dmac_47_16[0x20]; 449 450 u8 dmac_15_0[0x10]; 451 u8 first_prio[0x3]; 452 u8 first_cfi[0x1]; 453 u8 first_vid[0xc]; 454 455 u8 ip_protocol[0x8]; 456 u8 ip_dscp[0x6]; 457 u8 ip_ecn[0x2]; 458 u8 cvlan_tag[0x1]; 459 u8 svlan_tag[0x1]; 460 u8 frag[0x1]; 461 u8 ip_version[0x4]; 462 u8 tcp_flags[0x9]; 463 464 u8 tcp_sport[0x10]; 465 u8 tcp_dport[0x10]; 466 467 u8 reserved_at_c0[0x18]; 468 u8 ttl_hoplimit[0x8]; 469 470 u8 udp_sport[0x10]; 471 u8 udp_dport[0x10]; 472 473 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 474 475 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 476 }; 477 478 struct mlx5_ifc_nvgre_key_bits { 479 u8 hi[0x18]; 480 u8 lo[0x8]; 481 }; 482 483 union mlx5_ifc_gre_key_bits { 484 struct mlx5_ifc_nvgre_key_bits nvgre; 485 u8 key[0x20]; 486 }; 487 488 struct mlx5_ifc_fte_match_set_misc_bits { 489 u8 gre_c_present[0x1]; 490 u8 reserved_at_1[0x1]; 491 u8 gre_k_present[0x1]; 492 u8 gre_s_present[0x1]; 493 u8 source_vhca_port[0x4]; 494 u8 source_sqn[0x18]; 495 496 u8 source_eswitch_owner_vhca_id[0x10]; 497 u8 source_port[0x10]; 498 499 u8 outer_second_prio[0x3]; 500 u8 outer_second_cfi[0x1]; 501 u8 outer_second_vid[0xc]; 502 u8 inner_second_prio[0x3]; 503 u8 inner_second_cfi[0x1]; 504 u8 inner_second_vid[0xc]; 505 506 u8 outer_second_cvlan_tag[0x1]; 507 u8 inner_second_cvlan_tag[0x1]; 508 u8 outer_second_svlan_tag[0x1]; 509 u8 inner_second_svlan_tag[0x1]; 510 u8 reserved_at_64[0xc]; 511 u8 gre_protocol[0x10]; 512 513 union mlx5_ifc_gre_key_bits gre_key; 514 515 u8 vxlan_vni[0x18]; 516 u8 reserved_at_b8[0x8]; 517 518 u8 geneve_vni[0x18]; 519 u8 reserved_at_d8[0x7]; 520 u8 geneve_oam[0x1]; 521 522 u8 reserved_at_e0[0xc]; 523 u8 outer_ipv6_flow_label[0x14]; 524 525 u8 reserved_at_100[0xc]; 526 u8 inner_ipv6_flow_label[0x14]; 527 528 u8 reserved_at_120[0xa]; 529 u8 geneve_opt_len[0x6]; 530 u8 geneve_protocol_type[0x10]; 531 532 u8 reserved_at_140[0x8]; 533 u8 bth_dst_qp[0x18]; 534 u8 reserved_at_160[0x20]; 535 u8 outer_esp_spi[0x20]; 536 u8 reserved_at_1a0[0x60]; 537 }; 538 539 struct mlx5_ifc_fte_match_mpls_bits { 540 u8 mpls_label[0x14]; 541 u8 mpls_exp[0x3]; 542 u8 mpls_s_bos[0x1]; 543 u8 mpls_ttl[0x8]; 544 }; 545 546 struct mlx5_ifc_fte_match_set_misc2_bits { 547 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 548 549 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 550 551 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 552 553 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 554 555 u8 metadata_reg_c_7[0x20]; 556 557 u8 metadata_reg_c_6[0x20]; 558 559 u8 metadata_reg_c_5[0x20]; 560 561 u8 metadata_reg_c_4[0x20]; 562 563 u8 metadata_reg_c_3[0x20]; 564 565 u8 metadata_reg_c_2[0x20]; 566 567 u8 metadata_reg_c_1[0x20]; 568 569 u8 metadata_reg_c_0[0x20]; 570 571 u8 metadata_reg_a[0x20]; 572 573 u8 metadata_reg_b[0x20]; 574 575 u8 reserved_at_1c0[0x40]; 576 }; 577 578 struct mlx5_ifc_fte_match_set_misc3_bits { 579 u8 inner_tcp_seq_num[0x20]; 580 581 u8 outer_tcp_seq_num[0x20]; 582 583 u8 inner_tcp_ack_num[0x20]; 584 585 u8 outer_tcp_ack_num[0x20]; 586 587 u8 reserved_at_80[0x8]; 588 u8 outer_vxlan_gpe_vni[0x18]; 589 590 u8 outer_vxlan_gpe_next_protocol[0x8]; 591 u8 outer_vxlan_gpe_flags[0x8]; 592 u8 reserved_at_b0[0x10]; 593 594 u8 icmp_header_data[0x20]; 595 596 u8 icmpv6_header_data[0x20]; 597 598 u8 icmp_type[0x8]; 599 u8 icmp_code[0x8]; 600 u8 icmpv6_type[0x8]; 601 u8 icmpv6_code[0x8]; 602 603 u8 geneve_tlv_option_0_data[0x20]; 604 605 u8 reserved_at_140[0xc0]; 606 }; 607 608 struct mlx5_ifc_cmd_pas_bits { 609 u8 pa_h[0x20]; 610 611 u8 pa_l[0x14]; 612 u8 reserved_at_34[0xc]; 613 }; 614 615 struct mlx5_ifc_uint64_bits { 616 u8 hi[0x20]; 617 618 u8 lo[0x20]; 619 }; 620 621 enum { 622 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 623 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 624 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 625 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 626 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 627 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 628 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 629 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 630 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 631 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 632 }; 633 634 struct mlx5_ifc_ads_bits { 635 u8 fl[0x1]; 636 u8 free_ar[0x1]; 637 u8 reserved_at_2[0xe]; 638 u8 pkey_index[0x10]; 639 640 u8 reserved_at_20[0x8]; 641 u8 grh[0x1]; 642 u8 mlid[0x7]; 643 u8 rlid[0x10]; 644 645 u8 ack_timeout[0x5]; 646 u8 reserved_at_45[0x3]; 647 u8 src_addr_index[0x8]; 648 u8 reserved_at_50[0x4]; 649 u8 stat_rate[0x4]; 650 u8 hop_limit[0x8]; 651 652 u8 reserved_at_60[0x4]; 653 u8 tclass[0x8]; 654 u8 flow_label[0x14]; 655 656 u8 rgid_rip[16][0x8]; 657 658 u8 reserved_at_100[0x4]; 659 u8 f_dscp[0x1]; 660 u8 f_ecn[0x1]; 661 u8 reserved_at_106[0x1]; 662 u8 f_eth_prio[0x1]; 663 u8 ecn[0x2]; 664 u8 dscp[0x6]; 665 u8 udp_sport[0x10]; 666 667 u8 dei_cfi[0x1]; 668 u8 eth_prio[0x3]; 669 u8 sl[0x4]; 670 u8 vhca_port_num[0x8]; 671 u8 rmac_47_32[0x10]; 672 673 u8 rmac_31_0[0x20]; 674 }; 675 676 struct mlx5_ifc_flow_table_nic_cap_bits { 677 u8 nic_rx_multi_path_tirs[0x1]; 678 u8 nic_rx_multi_path_tirs_fts[0x1]; 679 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 680 u8 reserved_at_3[0x1d]; 681 u8 encap_general_header[0x1]; 682 u8 reserved_at_21[0xa]; 683 u8 log_max_packet_reformat_context[0x5]; 684 u8 reserved_at_30[0x6]; 685 u8 max_encap_header_size[0xa]; 686 u8 reserved_at_40[0x1c0]; 687 688 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 689 690 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 691 692 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 693 694 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 695 696 u8 reserved_at_a00[0x200]; 697 698 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 699 700 u8 reserved_at_e00[0x1200]; 701 702 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 703 704 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 705 706 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 707 708 u8 reserved_at_20c0[0x5f40]; 709 }; 710 711 enum { 712 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 713 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 714 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 715 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 716 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 717 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 718 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 719 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 720 }; 721 722 struct mlx5_ifc_flow_table_eswitch_cap_bits { 723 u8 fdb_to_vport_reg_c_id[0x8]; 724 u8 reserved_at_8[0xf]; 725 u8 flow_source[0x1]; 726 u8 reserved_at_18[0x2]; 727 u8 multi_fdb_encap[0x1]; 728 u8 reserved_at_1b[0x1]; 729 u8 fdb_multi_path_to_table[0x1]; 730 u8 reserved_at_1d[0x3]; 731 732 u8 reserved_at_20[0x1e0]; 733 734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 735 736 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 737 738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 739 740 u8 reserved_at_800[0x1000]; 741 742 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 743 744 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 745 746 u8 sw_steering_uplink_icm_address_rx[0x40]; 747 748 u8 sw_steering_uplink_icm_address_tx[0x40]; 749 750 u8 reserved_at_1900[0x6700]; 751 }; 752 753 enum { 754 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 755 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 756 }; 757 758 struct mlx5_ifc_e_switch_cap_bits { 759 u8 vport_svlan_strip[0x1]; 760 u8 vport_cvlan_strip[0x1]; 761 u8 vport_svlan_insert[0x1]; 762 u8 vport_cvlan_insert_if_not_exist[0x1]; 763 u8 vport_cvlan_insert_overwrite[0x1]; 764 u8 reserved_at_5[0x3]; 765 u8 esw_uplink_ingress_acl[0x1]; 766 u8 reserved_at_9[0x10]; 767 u8 esw_functions_changed[0x1]; 768 u8 reserved_at_1a[0x1]; 769 u8 ecpf_vport_exists[0x1]; 770 u8 counter_eswitch_affinity[0x1]; 771 u8 merged_eswitch[0x1]; 772 u8 nic_vport_node_guid_modify[0x1]; 773 u8 nic_vport_port_guid_modify[0x1]; 774 775 u8 vxlan_encap_decap[0x1]; 776 u8 nvgre_encap_decap[0x1]; 777 u8 reserved_at_22[0x1]; 778 u8 log_max_fdb_encap_uplink[0x5]; 779 u8 reserved_at_21[0x3]; 780 u8 log_max_packet_reformat_context[0x5]; 781 u8 reserved_2b[0x6]; 782 u8 max_encap_header_size[0xa]; 783 784 u8 reserved_at_40[0xb]; 785 u8 log_max_esw_sf[0x5]; 786 u8 esw_sf_base_id[0x10]; 787 788 u8 reserved_at_60[0x7a0]; 789 790 }; 791 792 struct mlx5_ifc_qos_cap_bits { 793 u8 packet_pacing[0x1]; 794 u8 esw_scheduling[0x1]; 795 u8 esw_bw_share[0x1]; 796 u8 esw_rate_limit[0x1]; 797 u8 reserved_at_4[0x1]; 798 u8 packet_pacing_burst_bound[0x1]; 799 u8 packet_pacing_typical_size[0x1]; 800 u8 reserved_at_7[0x19]; 801 802 u8 reserved_at_20[0x20]; 803 804 u8 packet_pacing_max_rate[0x20]; 805 806 u8 packet_pacing_min_rate[0x20]; 807 808 u8 reserved_at_80[0x10]; 809 u8 packet_pacing_rate_table_size[0x10]; 810 811 u8 esw_element_type[0x10]; 812 u8 esw_tsar_type[0x10]; 813 814 u8 reserved_at_c0[0x10]; 815 u8 max_qos_para_vport[0x10]; 816 817 u8 max_tsar_bw_share[0x20]; 818 819 u8 reserved_at_100[0x700]; 820 }; 821 822 struct mlx5_ifc_debug_cap_bits { 823 u8 core_dump_general[0x1]; 824 u8 core_dump_qp[0x1]; 825 u8 reserved_at_2[0x1e]; 826 827 u8 reserved_at_20[0x2]; 828 u8 stall_detect[0x1]; 829 u8 reserved_at_23[0x1d]; 830 831 u8 reserved_at_40[0x7c0]; 832 }; 833 834 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 835 u8 csum_cap[0x1]; 836 u8 vlan_cap[0x1]; 837 u8 lro_cap[0x1]; 838 u8 lro_psh_flag[0x1]; 839 u8 lro_time_stamp[0x1]; 840 u8 reserved_at_5[0x2]; 841 u8 wqe_vlan_insert[0x1]; 842 u8 self_lb_en_modifiable[0x1]; 843 u8 reserved_at_9[0x2]; 844 u8 max_lso_cap[0x5]; 845 u8 multi_pkt_send_wqe[0x2]; 846 u8 wqe_inline_mode[0x2]; 847 u8 rss_ind_tbl_cap[0x4]; 848 u8 reg_umr_sq[0x1]; 849 u8 scatter_fcs[0x1]; 850 u8 enhanced_multi_pkt_send_wqe[0x1]; 851 u8 tunnel_lso_const_out_ip_id[0x1]; 852 u8 reserved_at_1c[0x2]; 853 u8 tunnel_stateless_gre[0x1]; 854 u8 tunnel_stateless_vxlan[0x1]; 855 856 u8 swp[0x1]; 857 u8 swp_csum[0x1]; 858 u8 swp_lso[0x1]; 859 u8 cqe_checksum_full[0x1]; 860 u8 reserved_at_24[0x5]; 861 u8 tunnel_stateless_ip_over_ip[0x1]; 862 u8 reserved_at_2a[0x6]; 863 u8 max_vxlan_udp_ports[0x8]; 864 u8 reserved_at_38[0x6]; 865 u8 max_geneve_opt_len[0x1]; 866 u8 tunnel_stateless_geneve_rx[0x1]; 867 868 u8 reserved_at_40[0x10]; 869 u8 lro_min_mss_size[0x10]; 870 871 u8 reserved_at_60[0x120]; 872 873 u8 lro_timer_supported_periods[4][0x20]; 874 875 u8 reserved_at_200[0x600]; 876 }; 877 878 struct mlx5_ifc_roce_cap_bits { 879 u8 roce_apm[0x1]; 880 u8 reserved_at_1[0x1f]; 881 882 u8 reserved_at_20[0x60]; 883 884 u8 reserved_at_80[0xc]; 885 u8 l3_type[0x4]; 886 u8 reserved_at_90[0x8]; 887 u8 roce_version[0x8]; 888 889 u8 reserved_at_a0[0x10]; 890 u8 r_roce_dest_udp_port[0x10]; 891 892 u8 r_roce_max_src_udp_port[0x10]; 893 u8 r_roce_min_src_udp_port[0x10]; 894 895 u8 reserved_at_e0[0x10]; 896 u8 roce_address_table_size[0x10]; 897 898 u8 reserved_at_100[0x700]; 899 }; 900 901 struct mlx5_ifc_sync_steering_in_bits { 902 u8 opcode[0x10]; 903 u8 uid[0x10]; 904 905 u8 reserved_at_20[0x10]; 906 u8 op_mod[0x10]; 907 908 u8 reserved_at_40[0xc0]; 909 }; 910 911 struct mlx5_ifc_sync_steering_out_bits { 912 u8 status[0x8]; 913 u8 reserved_at_8[0x18]; 914 915 u8 syndrome[0x20]; 916 917 u8 reserved_at_40[0x40]; 918 }; 919 920 struct mlx5_ifc_device_mem_cap_bits { 921 u8 memic[0x1]; 922 u8 reserved_at_1[0x1f]; 923 924 u8 reserved_at_20[0xb]; 925 u8 log_min_memic_alloc_size[0x5]; 926 u8 reserved_at_30[0x8]; 927 u8 log_max_memic_addr_alignment[0x8]; 928 929 u8 memic_bar_start_addr[0x40]; 930 931 u8 memic_bar_size[0x20]; 932 933 u8 max_memic_size[0x20]; 934 935 u8 steering_sw_icm_start_address[0x40]; 936 937 u8 reserved_at_100[0x8]; 938 u8 log_header_modify_sw_icm_size[0x8]; 939 u8 reserved_at_110[0x2]; 940 u8 log_sw_icm_alloc_granularity[0x6]; 941 u8 log_steering_sw_icm_size[0x8]; 942 943 u8 reserved_at_120[0x20]; 944 945 u8 header_modify_sw_icm_start_address[0x40]; 946 947 u8 reserved_at_180[0x680]; 948 }; 949 950 struct mlx5_ifc_device_event_cap_bits { 951 u8 user_affiliated_events[4][0x40]; 952 953 u8 user_unaffiliated_events[4][0x40]; 954 }; 955 956 enum { 957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 963 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 964 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 965 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 966 }; 967 968 enum { 969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 975 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 976 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 977 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 978 }; 979 980 struct mlx5_ifc_atomic_caps_bits { 981 u8 reserved_at_0[0x40]; 982 983 u8 atomic_req_8B_endianness_mode[0x2]; 984 u8 reserved_at_42[0x4]; 985 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 986 987 u8 reserved_at_47[0x19]; 988 989 u8 reserved_at_60[0x20]; 990 991 u8 reserved_at_80[0x10]; 992 u8 atomic_operations[0x10]; 993 994 u8 reserved_at_a0[0x10]; 995 u8 atomic_size_qp[0x10]; 996 997 u8 reserved_at_c0[0x10]; 998 u8 atomic_size_dc[0x10]; 999 1000 u8 reserved_at_e0[0x720]; 1001 }; 1002 1003 struct mlx5_ifc_odp_cap_bits { 1004 u8 reserved_at_0[0x40]; 1005 1006 u8 sig[0x1]; 1007 u8 reserved_at_41[0x1f]; 1008 1009 u8 reserved_at_60[0x20]; 1010 1011 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1012 1013 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1014 1015 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1016 1017 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1018 1019 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1020 1021 u8 reserved_at_120[0x6E0]; 1022 }; 1023 1024 struct mlx5_ifc_calc_op { 1025 u8 reserved_at_0[0x10]; 1026 u8 reserved_at_10[0x9]; 1027 u8 op_swap_endianness[0x1]; 1028 u8 op_min[0x1]; 1029 u8 op_xor[0x1]; 1030 u8 op_or[0x1]; 1031 u8 op_and[0x1]; 1032 u8 op_max[0x1]; 1033 u8 op_add[0x1]; 1034 }; 1035 1036 struct mlx5_ifc_vector_calc_cap_bits { 1037 u8 calc_matrix[0x1]; 1038 u8 reserved_at_1[0x1f]; 1039 u8 reserved_at_20[0x8]; 1040 u8 max_vec_count[0x8]; 1041 u8 reserved_at_30[0xd]; 1042 u8 max_chunk_size[0x3]; 1043 struct mlx5_ifc_calc_op calc0; 1044 struct mlx5_ifc_calc_op calc1; 1045 struct mlx5_ifc_calc_op calc2; 1046 struct mlx5_ifc_calc_op calc3; 1047 1048 u8 reserved_at_c0[0x720]; 1049 }; 1050 1051 struct mlx5_ifc_tls_cap_bits { 1052 u8 tls_1_2_aes_gcm_128[0x1]; 1053 u8 tls_1_3_aes_gcm_128[0x1]; 1054 u8 tls_1_2_aes_gcm_256[0x1]; 1055 u8 tls_1_3_aes_gcm_256[0x1]; 1056 u8 reserved_at_4[0x1c]; 1057 1058 u8 reserved_at_20[0x7e0]; 1059 }; 1060 1061 enum { 1062 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1063 MLX5_WQ_TYPE_CYCLIC = 0x1, 1064 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1065 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1066 }; 1067 1068 enum { 1069 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1070 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1071 }; 1072 1073 enum { 1074 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1075 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1076 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1077 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1078 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1079 }; 1080 1081 enum { 1082 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1083 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1084 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1085 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1086 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1087 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1088 }; 1089 1090 enum { 1091 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1092 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1093 }; 1094 1095 enum { 1096 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1097 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1098 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1099 }; 1100 1101 enum { 1102 MLX5_CAP_PORT_TYPE_IB = 0x0, 1103 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1104 }; 1105 1106 enum { 1107 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1108 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1109 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1110 }; 1111 1112 enum { 1113 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1114 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1115 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1116 }; 1117 1118 enum { 1119 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1120 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1121 }; 1122 1123 #define MLX5_FC_BULK_SIZE_FACTOR 128 1124 1125 enum mlx5_fc_bulk_alloc_bitmask { 1126 MLX5_FC_BULK_128 = (1 << 0), 1127 MLX5_FC_BULK_256 = (1 << 1), 1128 MLX5_FC_BULK_512 = (1 << 2), 1129 MLX5_FC_BULK_1024 = (1 << 3), 1130 MLX5_FC_BULK_2048 = (1 << 4), 1131 MLX5_FC_BULK_4096 = (1 << 5), 1132 MLX5_FC_BULK_8192 = (1 << 6), 1133 MLX5_FC_BULK_16384 = (1 << 7), 1134 }; 1135 1136 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1137 1138 struct mlx5_ifc_cmd_hca_cap_bits { 1139 u8 reserved_at_0[0x30]; 1140 u8 vhca_id[0x10]; 1141 1142 u8 reserved_at_40[0x40]; 1143 1144 u8 log_max_srq_sz[0x8]; 1145 u8 log_max_qp_sz[0x8]; 1146 u8 event_cap[0x1]; 1147 u8 reserved_at_91[0x7]; 1148 u8 prio_tag_required[0x1]; 1149 u8 reserved_at_99[0x2]; 1150 u8 log_max_qp[0x5]; 1151 1152 u8 reserved_at_a0[0xb]; 1153 u8 log_max_srq[0x5]; 1154 u8 reserved_at_b0[0x10]; 1155 1156 u8 reserved_at_c0[0x8]; 1157 u8 log_max_cq_sz[0x8]; 1158 u8 reserved_at_d0[0xb]; 1159 u8 log_max_cq[0x5]; 1160 1161 u8 log_max_eq_sz[0x8]; 1162 u8 reserved_at_e8[0x2]; 1163 u8 log_max_mkey[0x6]; 1164 u8 reserved_at_f0[0x8]; 1165 u8 dump_fill_mkey[0x1]; 1166 u8 reserved_at_f9[0x2]; 1167 u8 fast_teardown[0x1]; 1168 u8 log_max_eq[0x4]; 1169 1170 u8 max_indirection[0x8]; 1171 u8 fixed_buffer_size[0x1]; 1172 u8 log_max_mrw_sz[0x7]; 1173 u8 force_teardown[0x1]; 1174 u8 reserved_at_111[0x1]; 1175 u8 log_max_bsf_list_size[0x6]; 1176 u8 umr_extended_translation_offset[0x1]; 1177 u8 null_mkey[0x1]; 1178 u8 log_max_klm_list_size[0x6]; 1179 1180 u8 reserved_at_120[0xa]; 1181 u8 log_max_ra_req_dc[0x6]; 1182 u8 reserved_at_130[0xa]; 1183 u8 log_max_ra_res_dc[0x6]; 1184 1185 u8 reserved_at_140[0xa]; 1186 u8 log_max_ra_req_qp[0x6]; 1187 u8 reserved_at_150[0xa]; 1188 u8 log_max_ra_res_qp[0x6]; 1189 1190 u8 end_pad[0x1]; 1191 u8 cc_query_allowed[0x1]; 1192 u8 cc_modify_allowed[0x1]; 1193 u8 start_pad[0x1]; 1194 u8 cache_line_128byte[0x1]; 1195 u8 reserved_at_165[0x4]; 1196 u8 rts2rts_qp_counters_set_id[0x1]; 1197 u8 reserved_at_16a[0x2]; 1198 u8 vnic_env_int_rq_oob[0x1]; 1199 u8 sbcam_reg[0x1]; 1200 u8 reserved_at_16e[0x1]; 1201 u8 qcam_reg[0x1]; 1202 u8 gid_table_size[0x10]; 1203 1204 u8 out_of_seq_cnt[0x1]; 1205 u8 vport_counters[0x1]; 1206 u8 retransmission_q_counters[0x1]; 1207 u8 debug[0x1]; 1208 u8 modify_rq_counter_set_id[0x1]; 1209 u8 rq_delay_drop[0x1]; 1210 u8 max_qp_cnt[0xa]; 1211 u8 pkey_table_size[0x10]; 1212 1213 u8 vport_group_manager[0x1]; 1214 u8 vhca_group_manager[0x1]; 1215 u8 ib_virt[0x1]; 1216 u8 eth_virt[0x1]; 1217 u8 vnic_env_queue_counters[0x1]; 1218 u8 ets[0x1]; 1219 u8 nic_flow_table[0x1]; 1220 u8 eswitch_manager[0x1]; 1221 u8 device_memory[0x1]; 1222 u8 mcam_reg[0x1]; 1223 u8 pcam_reg[0x1]; 1224 u8 local_ca_ack_delay[0x5]; 1225 u8 port_module_event[0x1]; 1226 u8 enhanced_error_q_counters[0x1]; 1227 u8 ports_check[0x1]; 1228 u8 reserved_at_1b3[0x1]; 1229 u8 disable_link_up[0x1]; 1230 u8 beacon_led[0x1]; 1231 u8 port_type[0x2]; 1232 u8 num_ports[0x8]; 1233 1234 u8 reserved_at_1c0[0x1]; 1235 u8 pps[0x1]; 1236 u8 pps_modify[0x1]; 1237 u8 log_max_msg[0x5]; 1238 u8 reserved_at_1c8[0x4]; 1239 u8 max_tc[0x4]; 1240 u8 temp_warn_event[0x1]; 1241 u8 dcbx[0x1]; 1242 u8 general_notification_event[0x1]; 1243 u8 reserved_at_1d3[0x2]; 1244 u8 fpga[0x1]; 1245 u8 rol_s[0x1]; 1246 u8 rol_g[0x1]; 1247 u8 reserved_at_1d8[0x1]; 1248 u8 wol_s[0x1]; 1249 u8 wol_g[0x1]; 1250 u8 wol_a[0x1]; 1251 u8 wol_b[0x1]; 1252 u8 wol_m[0x1]; 1253 u8 wol_u[0x1]; 1254 u8 wol_p[0x1]; 1255 1256 u8 stat_rate_support[0x10]; 1257 u8 reserved_at_1f0[0xc]; 1258 u8 cqe_version[0x4]; 1259 1260 u8 compact_address_vector[0x1]; 1261 u8 striding_rq[0x1]; 1262 u8 reserved_at_202[0x1]; 1263 u8 ipoib_enhanced_offloads[0x1]; 1264 u8 ipoib_basic_offloads[0x1]; 1265 u8 reserved_at_205[0x1]; 1266 u8 repeated_block_disabled[0x1]; 1267 u8 umr_modify_entity_size_disabled[0x1]; 1268 u8 umr_modify_atomic_disabled[0x1]; 1269 u8 umr_indirect_mkey_disabled[0x1]; 1270 u8 umr_fence[0x2]; 1271 u8 dc_req_scat_data_cqe[0x1]; 1272 u8 reserved_at_20d[0x2]; 1273 u8 drain_sigerr[0x1]; 1274 u8 cmdif_checksum[0x2]; 1275 u8 sigerr_cqe[0x1]; 1276 u8 reserved_at_213[0x1]; 1277 u8 wq_signature[0x1]; 1278 u8 sctr_data_cqe[0x1]; 1279 u8 reserved_at_216[0x1]; 1280 u8 sho[0x1]; 1281 u8 tph[0x1]; 1282 u8 rf[0x1]; 1283 u8 dct[0x1]; 1284 u8 qos[0x1]; 1285 u8 eth_net_offloads[0x1]; 1286 u8 roce[0x1]; 1287 u8 atomic[0x1]; 1288 u8 reserved_at_21f[0x1]; 1289 1290 u8 cq_oi[0x1]; 1291 u8 cq_resize[0x1]; 1292 u8 cq_moderation[0x1]; 1293 u8 reserved_at_223[0x3]; 1294 u8 cq_eq_remap[0x1]; 1295 u8 pg[0x1]; 1296 u8 block_lb_mc[0x1]; 1297 u8 reserved_at_229[0x1]; 1298 u8 scqe_break_moderation[0x1]; 1299 u8 cq_period_start_from_cqe[0x1]; 1300 u8 cd[0x1]; 1301 u8 reserved_at_22d[0x1]; 1302 u8 apm[0x1]; 1303 u8 vector_calc[0x1]; 1304 u8 umr_ptr_rlky[0x1]; 1305 u8 imaicl[0x1]; 1306 u8 qp_packet_based[0x1]; 1307 u8 reserved_at_233[0x3]; 1308 u8 qkv[0x1]; 1309 u8 pkv[0x1]; 1310 u8 set_deth_sqpn[0x1]; 1311 u8 reserved_at_239[0x3]; 1312 u8 xrc[0x1]; 1313 u8 ud[0x1]; 1314 u8 uc[0x1]; 1315 u8 rc[0x1]; 1316 1317 u8 uar_4k[0x1]; 1318 u8 reserved_at_241[0x9]; 1319 u8 uar_sz[0x6]; 1320 u8 reserved_at_250[0x8]; 1321 u8 log_pg_sz[0x8]; 1322 1323 u8 bf[0x1]; 1324 u8 driver_version[0x1]; 1325 u8 pad_tx_eth_packet[0x1]; 1326 u8 reserved_at_263[0x8]; 1327 u8 log_bf_reg_size[0x5]; 1328 1329 u8 reserved_at_270[0x8]; 1330 u8 lag_tx_port_affinity[0x1]; 1331 u8 reserved_at_279[0x2]; 1332 u8 lag_master[0x1]; 1333 u8 num_lag_ports[0x4]; 1334 1335 u8 reserved_at_280[0x10]; 1336 u8 max_wqe_sz_sq[0x10]; 1337 1338 u8 reserved_at_2a0[0x10]; 1339 u8 max_wqe_sz_rq[0x10]; 1340 1341 u8 max_flow_counter_31_16[0x10]; 1342 u8 max_wqe_sz_sq_dc[0x10]; 1343 1344 u8 reserved_at_2e0[0x7]; 1345 u8 max_qp_mcg[0x19]; 1346 1347 u8 reserved_at_300[0x10]; 1348 u8 flow_counter_bulk_alloc[0x8]; 1349 u8 log_max_mcg[0x8]; 1350 1351 u8 reserved_at_320[0x3]; 1352 u8 log_max_transport_domain[0x5]; 1353 u8 reserved_at_328[0x3]; 1354 u8 log_max_pd[0x5]; 1355 u8 reserved_at_330[0xb]; 1356 u8 log_max_xrcd[0x5]; 1357 1358 u8 nic_receive_steering_discard[0x1]; 1359 u8 receive_discard_vport_down[0x1]; 1360 u8 transmit_discard_vport_down[0x1]; 1361 u8 reserved_at_343[0x5]; 1362 u8 log_max_flow_counter_bulk[0x8]; 1363 u8 max_flow_counter_15_0[0x10]; 1364 1365 1366 u8 reserved_at_360[0x3]; 1367 u8 log_max_rq[0x5]; 1368 u8 reserved_at_368[0x3]; 1369 u8 log_max_sq[0x5]; 1370 u8 reserved_at_370[0x3]; 1371 u8 log_max_tir[0x5]; 1372 u8 reserved_at_378[0x3]; 1373 u8 log_max_tis[0x5]; 1374 1375 u8 basic_cyclic_rcv_wqe[0x1]; 1376 u8 reserved_at_381[0x2]; 1377 u8 log_max_rmp[0x5]; 1378 u8 reserved_at_388[0x3]; 1379 u8 log_max_rqt[0x5]; 1380 u8 reserved_at_390[0x3]; 1381 u8 log_max_rqt_size[0x5]; 1382 u8 reserved_at_398[0x3]; 1383 u8 log_max_tis_per_sq[0x5]; 1384 1385 u8 ext_stride_num_range[0x1]; 1386 u8 reserved_at_3a1[0x2]; 1387 u8 log_max_stride_sz_rq[0x5]; 1388 u8 reserved_at_3a8[0x3]; 1389 u8 log_min_stride_sz_rq[0x5]; 1390 u8 reserved_at_3b0[0x3]; 1391 u8 log_max_stride_sz_sq[0x5]; 1392 u8 reserved_at_3b8[0x3]; 1393 u8 log_min_stride_sz_sq[0x5]; 1394 1395 u8 hairpin[0x1]; 1396 u8 reserved_at_3c1[0x2]; 1397 u8 log_max_hairpin_queues[0x5]; 1398 u8 reserved_at_3c8[0x3]; 1399 u8 log_max_hairpin_wq_data_sz[0x5]; 1400 u8 reserved_at_3d0[0x3]; 1401 u8 log_max_hairpin_num_packets[0x5]; 1402 u8 reserved_at_3d8[0x3]; 1403 u8 log_max_wq_sz[0x5]; 1404 1405 u8 nic_vport_change_event[0x1]; 1406 u8 disable_local_lb_uc[0x1]; 1407 u8 disable_local_lb_mc[0x1]; 1408 u8 log_min_hairpin_wq_data_sz[0x5]; 1409 u8 reserved_at_3e8[0x3]; 1410 u8 log_max_vlan_list[0x5]; 1411 u8 reserved_at_3f0[0x3]; 1412 u8 log_max_current_mc_list[0x5]; 1413 u8 reserved_at_3f8[0x3]; 1414 u8 log_max_current_uc_list[0x5]; 1415 1416 u8 general_obj_types[0x40]; 1417 1418 u8 reserved_at_440[0x20]; 1419 1420 u8 tls[0x1]; 1421 u8 reserved_at_461[0x2]; 1422 u8 log_max_uctx[0x5]; 1423 u8 reserved_at_468[0x3]; 1424 u8 log_max_umem[0x5]; 1425 u8 max_num_eqs[0x10]; 1426 1427 u8 reserved_at_480[0x3]; 1428 u8 log_max_l2_table[0x5]; 1429 u8 reserved_at_488[0x8]; 1430 u8 log_uar_page_sz[0x10]; 1431 1432 u8 reserved_at_4a0[0x20]; 1433 u8 device_frequency_mhz[0x20]; 1434 u8 device_frequency_khz[0x20]; 1435 1436 u8 reserved_at_500[0x20]; 1437 u8 num_of_uars_per_page[0x20]; 1438 1439 u8 flex_parser_protocols[0x20]; 1440 1441 u8 max_geneve_tlv_options[0x8]; 1442 u8 reserved_at_568[0x3]; 1443 u8 max_geneve_tlv_option_data_len[0x5]; 1444 u8 reserved_at_570[0x10]; 1445 1446 u8 reserved_at_580[0x33]; 1447 u8 log_max_dek[0x5]; 1448 u8 reserved_at_5b8[0x4]; 1449 u8 mini_cqe_resp_stride_index[0x1]; 1450 u8 cqe_128_always[0x1]; 1451 u8 cqe_compression_128[0x1]; 1452 u8 cqe_compression[0x1]; 1453 1454 u8 cqe_compression_timeout[0x10]; 1455 u8 cqe_compression_max_num[0x10]; 1456 1457 u8 reserved_at_5e0[0x10]; 1458 u8 tag_matching[0x1]; 1459 u8 rndv_offload_rc[0x1]; 1460 u8 rndv_offload_dc[0x1]; 1461 u8 log_tag_matching_list_sz[0x5]; 1462 u8 reserved_at_5f8[0x3]; 1463 u8 log_max_xrq[0x5]; 1464 1465 u8 affiliate_nic_vport_criteria[0x8]; 1466 u8 native_port_num[0x8]; 1467 u8 num_vhca_ports[0x8]; 1468 u8 reserved_at_618[0x6]; 1469 u8 sw_owner_id[0x1]; 1470 u8 reserved_at_61f[0x1]; 1471 1472 u8 max_num_of_monitor_counters[0x10]; 1473 u8 num_ppcnt_monitor_counters[0x10]; 1474 1475 u8 reserved_at_640[0x10]; 1476 u8 num_q_monitor_counters[0x10]; 1477 1478 u8 reserved_at_660[0x20]; 1479 1480 u8 sf[0x1]; 1481 u8 sf_set_partition[0x1]; 1482 u8 reserved_at_682[0x1]; 1483 u8 log_max_sf[0x5]; 1484 u8 reserved_at_688[0x8]; 1485 u8 log_min_sf_size[0x8]; 1486 u8 max_num_sf_partitions[0x8]; 1487 1488 u8 uctx_cap[0x20]; 1489 1490 u8 reserved_at_6c0[0x4]; 1491 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1492 u8 flex_parser_id_icmp_dw1[0x4]; 1493 u8 flex_parser_id_icmp_dw0[0x4]; 1494 u8 flex_parser_id_icmpv6_dw1[0x4]; 1495 u8 flex_parser_id_icmpv6_dw0[0x4]; 1496 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1497 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1498 1499 u8 reserved_at_6e0[0x10]; 1500 u8 sf_base_id[0x10]; 1501 1502 u8 reserved_at_700[0x80]; 1503 u8 vhca_tunnel_commands[0x40]; 1504 u8 reserved_at_7c0[0x40]; 1505 }; 1506 1507 enum mlx5_flow_destination_type { 1508 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1509 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1510 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1511 1512 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1513 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1514 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1515 }; 1516 1517 enum mlx5_flow_table_miss_action { 1518 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1519 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1520 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1521 }; 1522 1523 struct mlx5_ifc_dest_format_struct_bits { 1524 u8 destination_type[0x8]; 1525 u8 destination_id[0x18]; 1526 1527 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1528 u8 packet_reformat[0x1]; 1529 u8 reserved_at_22[0xe]; 1530 u8 destination_eswitch_owner_vhca_id[0x10]; 1531 }; 1532 1533 struct mlx5_ifc_flow_counter_list_bits { 1534 u8 flow_counter_id[0x20]; 1535 1536 u8 reserved_at_20[0x20]; 1537 }; 1538 1539 struct mlx5_ifc_extended_dest_format_bits { 1540 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1541 1542 u8 packet_reformat_id[0x20]; 1543 1544 u8 reserved_at_60[0x20]; 1545 }; 1546 1547 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1548 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1549 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1550 u8 reserved_at_0[0x40]; 1551 }; 1552 1553 struct mlx5_ifc_fte_match_param_bits { 1554 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1555 1556 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1557 1558 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1559 1560 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1561 1562 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1563 1564 u8 reserved_at_a00[0x600]; 1565 }; 1566 1567 enum { 1568 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1569 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1570 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1571 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1572 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1573 }; 1574 1575 struct mlx5_ifc_rx_hash_field_select_bits { 1576 u8 l3_prot_type[0x1]; 1577 u8 l4_prot_type[0x1]; 1578 u8 selected_fields[0x1e]; 1579 }; 1580 1581 enum { 1582 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1583 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1584 }; 1585 1586 enum { 1587 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1588 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1589 }; 1590 1591 struct mlx5_ifc_wq_bits { 1592 u8 wq_type[0x4]; 1593 u8 wq_signature[0x1]; 1594 u8 end_padding_mode[0x2]; 1595 u8 cd_slave[0x1]; 1596 u8 reserved_at_8[0x18]; 1597 1598 u8 hds_skip_first_sge[0x1]; 1599 u8 log2_hds_buf_size[0x3]; 1600 u8 reserved_at_24[0x7]; 1601 u8 page_offset[0x5]; 1602 u8 lwm[0x10]; 1603 1604 u8 reserved_at_40[0x8]; 1605 u8 pd[0x18]; 1606 1607 u8 reserved_at_60[0x8]; 1608 u8 uar_page[0x18]; 1609 1610 u8 dbr_addr[0x40]; 1611 1612 u8 hw_counter[0x20]; 1613 1614 u8 sw_counter[0x20]; 1615 1616 u8 reserved_at_100[0xc]; 1617 u8 log_wq_stride[0x4]; 1618 u8 reserved_at_110[0x3]; 1619 u8 log_wq_pg_sz[0x5]; 1620 u8 reserved_at_118[0x3]; 1621 u8 log_wq_sz[0x5]; 1622 1623 u8 dbr_umem_valid[0x1]; 1624 u8 wq_umem_valid[0x1]; 1625 u8 reserved_at_122[0x1]; 1626 u8 log_hairpin_num_packets[0x5]; 1627 u8 reserved_at_128[0x3]; 1628 u8 log_hairpin_data_sz[0x5]; 1629 1630 u8 reserved_at_130[0x4]; 1631 u8 log_wqe_num_of_strides[0x4]; 1632 u8 two_byte_shift_en[0x1]; 1633 u8 reserved_at_139[0x4]; 1634 u8 log_wqe_stride_size[0x3]; 1635 1636 u8 reserved_at_140[0x4c0]; 1637 1638 struct mlx5_ifc_cmd_pas_bits pas[0]; 1639 }; 1640 1641 struct mlx5_ifc_rq_num_bits { 1642 u8 reserved_at_0[0x8]; 1643 u8 rq_num[0x18]; 1644 }; 1645 1646 struct mlx5_ifc_mac_address_layout_bits { 1647 u8 reserved_at_0[0x10]; 1648 u8 mac_addr_47_32[0x10]; 1649 1650 u8 mac_addr_31_0[0x20]; 1651 }; 1652 1653 struct mlx5_ifc_vlan_layout_bits { 1654 u8 reserved_at_0[0x14]; 1655 u8 vlan[0x0c]; 1656 1657 u8 reserved_at_20[0x20]; 1658 }; 1659 1660 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1661 u8 reserved_at_0[0xa0]; 1662 1663 u8 min_time_between_cnps[0x20]; 1664 1665 u8 reserved_at_c0[0x12]; 1666 u8 cnp_dscp[0x6]; 1667 u8 reserved_at_d8[0x4]; 1668 u8 cnp_prio_mode[0x1]; 1669 u8 cnp_802p_prio[0x3]; 1670 1671 u8 reserved_at_e0[0x720]; 1672 }; 1673 1674 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1675 u8 reserved_at_0[0x60]; 1676 1677 u8 reserved_at_60[0x4]; 1678 u8 clamp_tgt_rate[0x1]; 1679 u8 reserved_at_65[0x3]; 1680 u8 clamp_tgt_rate_after_time_inc[0x1]; 1681 u8 reserved_at_69[0x17]; 1682 1683 u8 reserved_at_80[0x20]; 1684 1685 u8 rpg_time_reset[0x20]; 1686 1687 u8 rpg_byte_reset[0x20]; 1688 1689 u8 rpg_threshold[0x20]; 1690 1691 u8 rpg_max_rate[0x20]; 1692 1693 u8 rpg_ai_rate[0x20]; 1694 1695 u8 rpg_hai_rate[0x20]; 1696 1697 u8 rpg_gd[0x20]; 1698 1699 u8 rpg_min_dec_fac[0x20]; 1700 1701 u8 rpg_min_rate[0x20]; 1702 1703 u8 reserved_at_1c0[0xe0]; 1704 1705 u8 rate_to_set_on_first_cnp[0x20]; 1706 1707 u8 dce_tcp_g[0x20]; 1708 1709 u8 dce_tcp_rtt[0x20]; 1710 1711 u8 rate_reduce_monitor_period[0x20]; 1712 1713 u8 reserved_at_320[0x20]; 1714 1715 u8 initial_alpha_value[0x20]; 1716 1717 u8 reserved_at_360[0x4a0]; 1718 }; 1719 1720 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1721 u8 reserved_at_0[0x80]; 1722 1723 u8 rppp_max_rps[0x20]; 1724 1725 u8 rpg_time_reset[0x20]; 1726 1727 u8 rpg_byte_reset[0x20]; 1728 1729 u8 rpg_threshold[0x20]; 1730 1731 u8 rpg_max_rate[0x20]; 1732 1733 u8 rpg_ai_rate[0x20]; 1734 1735 u8 rpg_hai_rate[0x20]; 1736 1737 u8 rpg_gd[0x20]; 1738 1739 u8 rpg_min_dec_fac[0x20]; 1740 1741 u8 rpg_min_rate[0x20]; 1742 1743 u8 reserved_at_1c0[0x640]; 1744 }; 1745 1746 enum { 1747 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1748 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1749 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1750 }; 1751 1752 struct mlx5_ifc_resize_field_select_bits { 1753 u8 resize_field_select[0x20]; 1754 }; 1755 1756 enum { 1757 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1758 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1759 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1760 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1761 }; 1762 1763 struct mlx5_ifc_modify_field_select_bits { 1764 u8 modify_field_select[0x20]; 1765 }; 1766 1767 struct mlx5_ifc_field_select_r_roce_np_bits { 1768 u8 field_select_r_roce_np[0x20]; 1769 }; 1770 1771 struct mlx5_ifc_field_select_r_roce_rp_bits { 1772 u8 field_select_r_roce_rp[0x20]; 1773 }; 1774 1775 enum { 1776 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1777 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1778 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1779 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1780 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1781 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1782 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1783 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1784 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1785 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1786 }; 1787 1788 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1789 u8 field_select_8021qaurp[0x20]; 1790 }; 1791 1792 struct mlx5_ifc_phys_layer_cntrs_bits { 1793 u8 time_since_last_clear_high[0x20]; 1794 1795 u8 time_since_last_clear_low[0x20]; 1796 1797 u8 symbol_errors_high[0x20]; 1798 1799 u8 symbol_errors_low[0x20]; 1800 1801 u8 sync_headers_errors_high[0x20]; 1802 1803 u8 sync_headers_errors_low[0x20]; 1804 1805 u8 edpl_bip_errors_lane0_high[0x20]; 1806 1807 u8 edpl_bip_errors_lane0_low[0x20]; 1808 1809 u8 edpl_bip_errors_lane1_high[0x20]; 1810 1811 u8 edpl_bip_errors_lane1_low[0x20]; 1812 1813 u8 edpl_bip_errors_lane2_high[0x20]; 1814 1815 u8 edpl_bip_errors_lane2_low[0x20]; 1816 1817 u8 edpl_bip_errors_lane3_high[0x20]; 1818 1819 u8 edpl_bip_errors_lane3_low[0x20]; 1820 1821 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1822 1823 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1824 1825 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1826 1827 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1828 1829 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1830 1831 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1832 1833 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1834 1835 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1836 1837 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1838 1839 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1840 1841 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1842 1843 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1844 1845 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1846 1847 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1848 1849 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1850 1851 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1852 1853 u8 rs_fec_corrected_blocks_high[0x20]; 1854 1855 u8 rs_fec_corrected_blocks_low[0x20]; 1856 1857 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1858 1859 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1860 1861 u8 rs_fec_no_errors_blocks_high[0x20]; 1862 1863 u8 rs_fec_no_errors_blocks_low[0x20]; 1864 1865 u8 rs_fec_single_error_blocks_high[0x20]; 1866 1867 u8 rs_fec_single_error_blocks_low[0x20]; 1868 1869 u8 rs_fec_corrected_symbols_total_high[0x20]; 1870 1871 u8 rs_fec_corrected_symbols_total_low[0x20]; 1872 1873 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1874 1875 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1876 1877 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1878 1879 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1880 1881 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1882 1883 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1884 1885 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1886 1887 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1888 1889 u8 link_down_events[0x20]; 1890 1891 u8 successful_recovery_events[0x20]; 1892 1893 u8 reserved_at_640[0x180]; 1894 }; 1895 1896 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1897 u8 time_since_last_clear_high[0x20]; 1898 1899 u8 time_since_last_clear_low[0x20]; 1900 1901 u8 phy_received_bits_high[0x20]; 1902 1903 u8 phy_received_bits_low[0x20]; 1904 1905 u8 phy_symbol_errors_high[0x20]; 1906 1907 u8 phy_symbol_errors_low[0x20]; 1908 1909 u8 phy_corrected_bits_high[0x20]; 1910 1911 u8 phy_corrected_bits_low[0x20]; 1912 1913 u8 phy_corrected_bits_lane0_high[0x20]; 1914 1915 u8 phy_corrected_bits_lane0_low[0x20]; 1916 1917 u8 phy_corrected_bits_lane1_high[0x20]; 1918 1919 u8 phy_corrected_bits_lane1_low[0x20]; 1920 1921 u8 phy_corrected_bits_lane2_high[0x20]; 1922 1923 u8 phy_corrected_bits_lane2_low[0x20]; 1924 1925 u8 phy_corrected_bits_lane3_high[0x20]; 1926 1927 u8 phy_corrected_bits_lane3_low[0x20]; 1928 1929 u8 reserved_at_200[0x5c0]; 1930 }; 1931 1932 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1933 u8 symbol_error_counter[0x10]; 1934 1935 u8 link_error_recovery_counter[0x8]; 1936 1937 u8 link_downed_counter[0x8]; 1938 1939 u8 port_rcv_errors[0x10]; 1940 1941 u8 port_rcv_remote_physical_errors[0x10]; 1942 1943 u8 port_rcv_switch_relay_errors[0x10]; 1944 1945 u8 port_xmit_discards[0x10]; 1946 1947 u8 port_xmit_constraint_errors[0x8]; 1948 1949 u8 port_rcv_constraint_errors[0x8]; 1950 1951 u8 reserved_at_70[0x8]; 1952 1953 u8 link_overrun_errors[0x8]; 1954 1955 u8 reserved_at_80[0x10]; 1956 1957 u8 vl_15_dropped[0x10]; 1958 1959 u8 reserved_at_a0[0x80]; 1960 1961 u8 port_xmit_wait[0x20]; 1962 }; 1963 1964 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 1965 u8 transmit_queue_high[0x20]; 1966 1967 u8 transmit_queue_low[0x20]; 1968 1969 u8 no_buffer_discard_uc_high[0x20]; 1970 1971 u8 no_buffer_discard_uc_low[0x20]; 1972 1973 u8 reserved_at_80[0x740]; 1974 }; 1975 1976 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 1977 u8 wred_discard_high[0x20]; 1978 1979 u8 wred_discard_low[0x20]; 1980 1981 u8 ecn_marked_tc_high[0x20]; 1982 1983 u8 ecn_marked_tc_low[0x20]; 1984 1985 u8 reserved_at_80[0x740]; 1986 }; 1987 1988 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1989 u8 rx_octets_high[0x20]; 1990 1991 u8 rx_octets_low[0x20]; 1992 1993 u8 reserved_at_40[0xc0]; 1994 1995 u8 rx_frames_high[0x20]; 1996 1997 u8 rx_frames_low[0x20]; 1998 1999 u8 tx_octets_high[0x20]; 2000 2001 u8 tx_octets_low[0x20]; 2002 2003 u8 reserved_at_180[0xc0]; 2004 2005 u8 tx_frames_high[0x20]; 2006 2007 u8 tx_frames_low[0x20]; 2008 2009 u8 rx_pause_high[0x20]; 2010 2011 u8 rx_pause_low[0x20]; 2012 2013 u8 rx_pause_duration_high[0x20]; 2014 2015 u8 rx_pause_duration_low[0x20]; 2016 2017 u8 tx_pause_high[0x20]; 2018 2019 u8 tx_pause_low[0x20]; 2020 2021 u8 tx_pause_duration_high[0x20]; 2022 2023 u8 tx_pause_duration_low[0x20]; 2024 2025 u8 rx_pause_transition_high[0x20]; 2026 2027 u8 rx_pause_transition_low[0x20]; 2028 2029 u8 reserved_at_3c0[0x40]; 2030 2031 u8 device_stall_minor_watermark_cnt_high[0x20]; 2032 2033 u8 device_stall_minor_watermark_cnt_low[0x20]; 2034 2035 u8 device_stall_critical_watermark_cnt_high[0x20]; 2036 2037 u8 device_stall_critical_watermark_cnt_low[0x20]; 2038 2039 u8 reserved_at_480[0x340]; 2040 }; 2041 2042 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2043 u8 port_transmit_wait_high[0x20]; 2044 2045 u8 port_transmit_wait_low[0x20]; 2046 2047 u8 reserved_at_40[0x100]; 2048 2049 u8 rx_buffer_almost_full_high[0x20]; 2050 2051 u8 rx_buffer_almost_full_low[0x20]; 2052 2053 u8 rx_buffer_full_high[0x20]; 2054 2055 u8 rx_buffer_full_low[0x20]; 2056 2057 u8 rx_icrc_encapsulated_high[0x20]; 2058 2059 u8 rx_icrc_encapsulated_low[0x20]; 2060 2061 u8 reserved_at_200[0x5c0]; 2062 }; 2063 2064 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2065 u8 dot3stats_alignment_errors_high[0x20]; 2066 2067 u8 dot3stats_alignment_errors_low[0x20]; 2068 2069 u8 dot3stats_fcs_errors_high[0x20]; 2070 2071 u8 dot3stats_fcs_errors_low[0x20]; 2072 2073 u8 dot3stats_single_collision_frames_high[0x20]; 2074 2075 u8 dot3stats_single_collision_frames_low[0x20]; 2076 2077 u8 dot3stats_multiple_collision_frames_high[0x20]; 2078 2079 u8 dot3stats_multiple_collision_frames_low[0x20]; 2080 2081 u8 dot3stats_sqe_test_errors_high[0x20]; 2082 2083 u8 dot3stats_sqe_test_errors_low[0x20]; 2084 2085 u8 dot3stats_deferred_transmissions_high[0x20]; 2086 2087 u8 dot3stats_deferred_transmissions_low[0x20]; 2088 2089 u8 dot3stats_late_collisions_high[0x20]; 2090 2091 u8 dot3stats_late_collisions_low[0x20]; 2092 2093 u8 dot3stats_excessive_collisions_high[0x20]; 2094 2095 u8 dot3stats_excessive_collisions_low[0x20]; 2096 2097 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2098 2099 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2100 2101 u8 dot3stats_carrier_sense_errors_high[0x20]; 2102 2103 u8 dot3stats_carrier_sense_errors_low[0x20]; 2104 2105 u8 dot3stats_frame_too_longs_high[0x20]; 2106 2107 u8 dot3stats_frame_too_longs_low[0x20]; 2108 2109 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2110 2111 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2112 2113 u8 dot3stats_symbol_errors_high[0x20]; 2114 2115 u8 dot3stats_symbol_errors_low[0x20]; 2116 2117 u8 dot3control_in_unknown_opcodes_high[0x20]; 2118 2119 u8 dot3control_in_unknown_opcodes_low[0x20]; 2120 2121 u8 dot3in_pause_frames_high[0x20]; 2122 2123 u8 dot3in_pause_frames_low[0x20]; 2124 2125 u8 dot3out_pause_frames_high[0x20]; 2126 2127 u8 dot3out_pause_frames_low[0x20]; 2128 2129 u8 reserved_at_400[0x3c0]; 2130 }; 2131 2132 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2133 u8 ether_stats_drop_events_high[0x20]; 2134 2135 u8 ether_stats_drop_events_low[0x20]; 2136 2137 u8 ether_stats_octets_high[0x20]; 2138 2139 u8 ether_stats_octets_low[0x20]; 2140 2141 u8 ether_stats_pkts_high[0x20]; 2142 2143 u8 ether_stats_pkts_low[0x20]; 2144 2145 u8 ether_stats_broadcast_pkts_high[0x20]; 2146 2147 u8 ether_stats_broadcast_pkts_low[0x20]; 2148 2149 u8 ether_stats_multicast_pkts_high[0x20]; 2150 2151 u8 ether_stats_multicast_pkts_low[0x20]; 2152 2153 u8 ether_stats_crc_align_errors_high[0x20]; 2154 2155 u8 ether_stats_crc_align_errors_low[0x20]; 2156 2157 u8 ether_stats_undersize_pkts_high[0x20]; 2158 2159 u8 ether_stats_undersize_pkts_low[0x20]; 2160 2161 u8 ether_stats_oversize_pkts_high[0x20]; 2162 2163 u8 ether_stats_oversize_pkts_low[0x20]; 2164 2165 u8 ether_stats_fragments_high[0x20]; 2166 2167 u8 ether_stats_fragments_low[0x20]; 2168 2169 u8 ether_stats_jabbers_high[0x20]; 2170 2171 u8 ether_stats_jabbers_low[0x20]; 2172 2173 u8 ether_stats_collisions_high[0x20]; 2174 2175 u8 ether_stats_collisions_low[0x20]; 2176 2177 u8 ether_stats_pkts64octets_high[0x20]; 2178 2179 u8 ether_stats_pkts64octets_low[0x20]; 2180 2181 u8 ether_stats_pkts65to127octets_high[0x20]; 2182 2183 u8 ether_stats_pkts65to127octets_low[0x20]; 2184 2185 u8 ether_stats_pkts128to255octets_high[0x20]; 2186 2187 u8 ether_stats_pkts128to255octets_low[0x20]; 2188 2189 u8 ether_stats_pkts256to511octets_high[0x20]; 2190 2191 u8 ether_stats_pkts256to511octets_low[0x20]; 2192 2193 u8 ether_stats_pkts512to1023octets_high[0x20]; 2194 2195 u8 ether_stats_pkts512to1023octets_low[0x20]; 2196 2197 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2198 2199 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2200 2201 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2202 2203 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2204 2205 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2206 2207 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2208 2209 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2210 2211 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2212 2213 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2214 2215 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2216 2217 u8 reserved_at_540[0x280]; 2218 }; 2219 2220 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2221 u8 if_in_octets_high[0x20]; 2222 2223 u8 if_in_octets_low[0x20]; 2224 2225 u8 if_in_ucast_pkts_high[0x20]; 2226 2227 u8 if_in_ucast_pkts_low[0x20]; 2228 2229 u8 if_in_discards_high[0x20]; 2230 2231 u8 if_in_discards_low[0x20]; 2232 2233 u8 if_in_errors_high[0x20]; 2234 2235 u8 if_in_errors_low[0x20]; 2236 2237 u8 if_in_unknown_protos_high[0x20]; 2238 2239 u8 if_in_unknown_protos_low[0x20]; 2240 2241 u8 if_out_octets_high[0x20]; 2242 2243 u8 if_out_octets_low[0x20]; 2244 2245 u8 if_out_ucast_pkts_high[0x20]; 2246 2247 u8 if_out_ucast_pkts_low[0x20]; 2248 2249 u8 if_out_discards_high[0x20]; 2250 2251 u8 if_out_discards_low[0x20]; 2252 2253 u8 if_out_errors_high[0x20]; 2254 2255 u8 if_out_errors_low[0x20]; 2256 2257 u8 if_in_multicast_pkts_high[0x20]; 2258 2259 u8 if_in_multicast_pkts_low[0x20]; 2260 2261 u8 if_in_broadcast_pkts_high[0x20]; 2262 2263 u8 if_in_broadcast_pkts_low[0x20]; 2264 2265 u8 if_out_multicast_pkts_high[0x20]; 2266 2267 u8 if_out_multicast_pkts_low[0x20]; 2268 2269 u8 if_out_broadcast_pkts_high[0x20]; 2270 2271 u8 if_out_broadcast_pkts_low[0x20]; 2272 2273 u8 reserved_at_340[0x480]; 2274 }; 2275 2276 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2277 u8 a_frames_transmitted_ok_high[0x20]; 2278 2279 u8 a_frames_transmitted_ok_low[0x20]; 2280 2281 u8 a_frames_received_ok_high[0x20]; 2282 2283 u8 a_frames_received_ok_low[0x20]; 2284 2285 u8 a_frame_check_sequence_errors_high[0x20]; 2286 2287 u8 a_frame_check_sequence_errors_low[0x20]; 2288 2289 u8 a_alignment_errors_high[0x20]; 2290 2291 u8 a_alignment_errors_low[0x20]; 2292 2293 u8 a_octets_transmitted_ok_high[0x20]; 2294 2295 u8 a_octets_transmitted_ok_low[0x20]; 2296 2297 u8 a_octets_received_ok_high[0x20]; 2298 2299 u8 a_octets_received_ok_low[0x20]; 2300 2301 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2302 2303 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2304 2305 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2306 2307 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2308 2309 u8 a_multicast_frames_received_ok_high[0x20]; 2310 2311 u8 a_multicast_frames_received_ok_low[0x20]; 2312 2313 u8 a_broadcast_frames_received_ok_high[0x20]; 2314 2315 u8 a_broadcast_frames_received_ok_low[0x20]; 2316 2317 u8 a_in_range_length_errors_high[0x20]; 2318 2319 u8 a_in_range_length_errors_low[0x20]; 2320 2321 u8 a_out_of_range_length_field_high[0x20]; 2322 2323 u8 a_out_of_range_length_field_low[0x20]; 2324 2325 u8 a_frame_too_long_errors_high[0x20]; 2326 2327 u8 a_frame_too_long_errors_low[0x20]; 2328 2329 u8 a_symbol_error_during_carrier_high[0x20]; 2330 2331 u8 a_symbol_error_during_carrier_low[0x20]; 2332 2333 u8 a_mac_control_frames_transmitted_high[0x20]; 2334 2335 u8 a_mac_control_frames_transmitted_low[0x20]; 2336 2337 u8 a_mac_control_frames_received_high[0x20]; 2338 2339 u8 a_mac_control_frames_received_low[0x20]; 2340 2341 u8 a_unsupported_opcodes_received_high[0x20]; 2342 2343 u8 a_unsupported_opcodes_received_low[0x20]; 2344 2345 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2346 2347 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2348 2349 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2350 2351 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2352 2353 u8 reserved_at_4c0[0x300]; 2354 }; 2355 2356 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2357 u8 life_time_counter_high[0x20]; 2358 2359 u8 life_time_counter_low[0x20]; 2360 2361 u8 rx_errors[0x20]; 2362 2363 u8 tx_errors[0x20]; 2364 2365 u8 l0_to_recovery_eieos[0x20]; 2366 2367 u8 l0_to_recovery_ts[0x20]; 2368 2369 u8 l0_to_recovery_framing[0x20]; 2370 2371 u8 l0_to_recovery_retrain[0x20]; 2372 2373 u8 crc_error_dllp[0x20]; 2374 2375 u8 crc_error_tlp[0x20]; 2376 2377 u8 tx_overflow_buffer_pkt_high[0x20]; 2378 2379 u8 tx_overflow_buffer_pkt_low[0x20]; 2380 2381 u8 outbound_stalled_reads[0x20]; 2382 2383 u8 outbound_stalled_writes[0x20]; 2384 2385 u8 outbound_stalled_reads_events[0x20]; 2386 2387 u8 outbound_stalled_writes_events[0x20]; 2388 2389 u8 reserved_at_200[0x5c0]; 2390 }; 2391 2392 struct mlx5_ifc_cmd_inter_comp_event_bits { 2393 u8 command_completion_vector[0x20]; 2394 2395 u8 reserved_at_20[0xc0]; 2396 }; 2397 2398 struct mlx5_ifc_stall_vl_event_bits { 2399 u8 reserved_at_0[0x18]; 2400 u8 port_num[0x1]; 2401 u8 reserved_at_19[0x3]; 2402 u8 vl[0x4]; 2403 2404 u8 reserved_at_20[0xa0]; 2405 }; 2406 2407 struct mlx5_ifc_db_bf_congestion_event_bits { 2408 u8 event_subtype[0x8]; 2409 u8 reserved_at_8[0x8]; 2410 u8 congestion_level[0x8]; 2411 u8 reserved_at_18[0x8]; 2412 2413 u8 reserved_at_20[0xa0]; 2414 }; 2415 2416 struct mlx5_ifc_gpio_event_bits { 2417 u8 reserved_at_0[0x60]; 2418 2419 u8 gpio_event_hi[0x20]; 2420 2421 u8 gpio_event_lo[0x20]; 2422 2423 u8 reserved_at_a0[0x40]; 2424 }; 2425 2426 struct mlx5_ifc_port_state_change_event_bits { 2427 u8 reserved_at_0[0x40]; 2428 2429 u8 port_num[0x4]; 2430 u8 reserved_at_44[0x1c]; 2431 2432 u8 reserved_at_60[0x80]; 2433 }; 2434 2435 struct mlx5_ifc_dropped_packet_logged_bits { 2436 u8 reserved_at_0[0xe0]; 2437 }; 2438 2439 enum { 2440 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2441 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2442 }; 2443 2444 struct mlx5_ifc_cq_error_bits { 2445 u8 reserved_at_0[0x8]; 2446 u8 cqn[0x18]; 2447 2448 u8 reserved_at_20[0x20]; 2449 2450 u8 reserved_at_40[0x18]; 2451 u8 syndrome[0x8]; 2452 2453 u8 reserved_at_60[0x80]; 2454 }; 2455 2456 struct mlx5_ifc_rdma_page_fault_event_bits { 2457 u8 bytes_committed[0x20]; 2458 2459 u8 r_key[0x20]; 2460 2461 u8 reserved_at_40[0x10]; 2462 u8 packet_len[0x10]; 2463 2464 u8 rdma_op_len[0x20]; 2465 2466 u8 rdma_va[0x40]; 2467 2468 u8 reserved_at_c0[0x5]; 2469 u8 rdma[0x1]; 2470 u8 write[0x1]; 2471 u8 requestor[0x1]; 2472 u8 qp_number[0x18]; 2473 }; 2474 2475 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2476 u8 bytes_committed[0x20]; 2477 2478 u8 reserved_at_20[0x10]; 2479 u8 wqe_index[0x10]; 2480 2481 u8 reserved_at_40[0x10]; 2482 u8 len[0x10]; 2483 2484 u8 reserved_at_60[0x60]; 2485 2486 u8 reserved_at_c0[0x5]; 2487 u8 rdma[0x1]; 2488 u8 write_read[0x1]; 2489 u8 requestor[0x1]; 2490 u8 qpn[0x18]; 2491 }; 2492 2493 struct mlx5_ifc_qp_events_bits { 2494 u8 reserved_at_0[0xa0]; 2495 2496 u8 type[0x8]; 2497 u8 reserved_at_a8[0x18]; 2498 2499 u8 reserved_at_c0[0x8]; 2500 u8 qpn_rqn_sqn[0x18]; 2501 }; 2502 2503 struct mlx5_ifc_dct_events_bits { 2504 u8 reserved_at_0[0xc0]; 2505 2506 u8 reserved_at_c0[0x8]; 2507 u8 dct_number[0x18]; 2508 }; 2509 2510 struct mlx5_ifc_comp_event_bits { 2511 u8 reserved_at_0[0xc0]; 2512 2513 u8 reserved_at_c0[0x8]; 2514 u8 cq_number[0x18]; 2515 }; 2516 2517 enum { 2518 MLX5_QPC_STATE_RST = 0x0, 2519 MLX5_QPC_STATE_INIT = 0x1, 2520 MLX5_QPC_STATE_RTR = 0x2, 2521 MLX5_QPC_STATE_RTS = 0x3, 2522 MLX5_QPC_STATE_SQER = 0x4, 2523 MLX5_QPC_STATE_ERR = 0x6, 2524 MLX5_QPC_STATE_SQD = 0x7, 2525 MLX5_QPC_STATE_SUSPENDED = 0x9, 2526 }; 2527 2528 enum { 2529 MLX5_QPC_ST_RC = 0x0, 2530 MLX5_QPC_ST_UC = 0x1, 2531 MLX5_QPC_ST_UD = 0x2, 2532 MLX5_QPC_ST_XRC = 0x3, 2533 MLX5_QPC_ST_DCI = 0x5, 2534 MLX5_QPC_ST_QP0 = 0x7, 2535 MLX5_QPC_ST_QP1 = 0x8, 2536 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2537 MLX5_QPC_ST_REG_UMR = 0xc, 2538 }; 2539 2540 enum { 2541 MLX5_QPC_PM_STATE_ARMED = 0x0, 2542 MLX5_QPC_PM_STATE_REARM = 0x1, 2543 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2544 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2545 }; 2546 2547 enum { 2548 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2549 }; 2550 2551 enum { 2552 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2553 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2554 }; 2555 2556 enum { 2557 MLX5_QPC_MTU_256_BYTES = 0x1, 2558 MLX5_QPC_MTU_512_BYTES = 0x2, 2559 MLX5_QPC_MTU_1K_BYTES = 0x3, 2560 MLX5_QPC_MTU_2K_BYTES = 0x4, 2561 MLX5_QPC_MTU_4K_BYTES = 0x5, 2562 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2563 }; 2564 2565 enum { 2566 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2567 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2568 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2569 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2570 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2571 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2572 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2573 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2574 }; 2575 2576 enum { 2577 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2578 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2579 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2580 }; 2581 2582 enum { 2583 MLX5_QPC_CS_RES_DISABLE = 0x0, 2584 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2585 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2586 }; 2587 2588 struct mlx5_ifc_qpc_bits { 2589 u8 state[0x4]; 2590 u8 lag_tx_port_affinity[0x4]; 2591 u8 st[0x8]; 2592 u8 reserved_at_10[0x3]; 2593 u8 pm_state[0x2]; 2594 u8 reserved_at_15[0x1]; 2595 u8 req_e2e_credit_mode[0x2]; 2596 u8 offload_type[0x4]; 2597 u8 end_padding_mode[0x2]; 2598 u8 reserved_at_1e[0x2]; 2599 2600 u8 wq_signature[0x1]; 2601 u8 block_lb_mc[0x1]; 2602 u8 atomic_like_write_en[0x1]; 2603 u8 latency_sensitive[0x1]; 2604 u8 reserved_at_24[0x1]; 2605 u8 drain_sigerr[0x1]; 2606 u8 reserved_at_26[0x2]; 2607 u8 pd[0x18]; 2608 2609 u8 mtu[0x3]; 2610 u8 log_msg_max[0x5]; 2611 u8 reserved_at_48[0x1]; 2612 u8 log_rq_size[0x4]; 2613 u8 log_rq_stride[0x3]; 2614 u8 no_sq[0x1]; 2615 u8 log_sq_size[0x4]; 2616 u8 reserved_at_55[0x6]; 2617 u8 rlky[0x1]; 2618 u8 ulp_stateless_offload_mode[0x4]; 2619 2620 u8 counter_set_id[0x8]; 2621 u8 uar_page[0x18]; 2622 2623 u8 reserved_at_80[0x8]; 2624 u8 user_index[0x18]; 2625 2626 u8 reserved_at_a0[0x3]; 2627 u8 log_page_size[0x5]; 2628 u8 remote_qpn[0x18]; 2629 2630 struct mlx5_ifc_ads_bits primary_address_path; 2631 2632 struct mlx5_ifc_ads_bits secondary_address_path; 2633 2634 u8 log_ack_req_freq[0x4]; 2635 u8 reserved_at_384[0x4]; 2636 u8 log_sra_max[0x3]; 2637 u8 reserved_at_38b[0x2]; 2638 u8 retry_count[0x3]; 2639 u8 rnr_retry[0x3]; 2640 u8 reserved_at_393[0x1]; 2641 u8 fre[0x1]; 2642 u8 cur_rnr_retry[0x3]; 2643 u8 cur_retry_count[0x3]; 2644 u8 reserved_at_39b[0x5]; 2645 2646 u8 reserved_at_3a0[0x20]; 2647 2648 u8 reserved_at_3c0[0x8]; 2649 u8 next_send_psn[0x18]; 2650 2651 u8 reserved_at_3e0[0x8]; 2652 u8 cqn_snd[0x18]; 2653 2654 u8 reserved_at_400[0x8]; 2655 u8 deth_sqpn[0x18]; 2656 2657 u8 reserved_at_420[0x20]; 2658 2659 u8 reserved_at_440[0x8]; 2660 u8 last_acked_psn[0x18]; 2661 2662 u8 reserved_at_460[0x8]; 2663 u8 ssn[0x18]; 2664 2665 u8 reserved_at_480[0x8]; 2666 u8 log_rra_max[0x3]; 2667 u8 reserved_at_48b[0x1]; 2668 u8 atomic_mode[0x4]; 2669 u8 rre[0x1]; 2670 u8 rwe[0x1]; 2671 u8 rae[0x1]; 2672 u8 reserved_at_493[0x1]; 2673 u8 page_offset[0x6]; 2674 u8 reserved_at_49a[0x3]; 2675 u8 cd_slave_receive[0x1]; 2676 u8 cd_slave_send[0x1]; 2677 u8 cd_master[0x1]; 2678 2679 u8 reserved_at_4a0[0x3]; 2680 u8 min_rnr_nak[0x5]; 2681 u8 next_rcv_psn[0x18]; 2682 2683 u8 reserved_at_4c0[0x8]; 2684 u8 xrcd[0x18]; 2685 2686 u8 reserved_at_4e0[0x8]; 2687 u8 cqn_rcv[0x18]; 2688 2689 u8 dbr_addr[0x40]; 2690 2691 u8 q_key[0x20]; 2692 2693 u8 reserved_at_560[0x5]; 2694 u8 rq_type[0x3]; 2695 u8 srqn_rmpn_xrqn[0x18]; 2696 2697 u8 reserved_at_580[0x8]; 2698 u8 rmsn[0x18]; 2699 2700 u8 hw_sq_wqebb_counter[0x10]; 2701 u8 sw_sq_wqebb_counter[0x10]; 2702 2703 u8 hw_rq_counter[0x20]; 2704 2705 u8 sw_rq_counter[0x20]; 2706 2707 u8 reserved_at_600[0x20]; 2708 2709 u8 reserved_at_620[0xf]; 2710 u8 cgs[0x1]; 2711 u8 cs_req[0x8]; 2712 u8 cs_res[0x8]; 2713 2714 u8 dc_access_key[0x40]; 2715 2716 u8 reserved_at_680[0x3]; 2717 u8 dbr_umem_valid[0x1]; 2718 2719 u8 reserved_at_684[0xbc]; 2720 }; 2721 2722 struct mlx5_ifc_roce_addr_layout_bits { 2723 u8 source_l3_address[16][0x8]; 2724 2725 u8 reserved_at_80[0x3]; 2726 u8 vlan_valid[0x1]; 2727 u8 vlan_id[0xc]; 2728 u8 source_mac_47_32[0x10]; 2729 2730 u8 source_mac_31_0[0x20]; 2731 2732 u8 reserved_at_c0[0x14]; 2733 u8 roce_l3_type[0x4]; 2734 u8 roce_version[0x8]; 2735 2736 u8 reserved_at_e0[0x20]; 2737 }; 2738 2739 union mlx5_ifc_hca_cap_union_bits { 2740 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2741 struct mlx5_ifc_odp_cap_bits odp_cap; 2742 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2743 struct mlx5_ifc_roce_cap_bits roce_cap; 2744 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2745 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2746 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2747 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2748 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2749 struct mlx5_ifc_qos_cap_bits qos_cap; 2750 struct mlx5_ifc_debug_cap_bits debug_cap; 2751 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2752 struct mlx5_ifc_tls_cap_bits tls_cap; 2753 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2754 u8 reserved_at_0[0x8000]; 2755 }; 2756 2757 enum { 2758 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2759 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2760 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2761 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2762 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2763 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2764 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2765 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2766 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2767 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2768 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2769 }; 2770 2771 enum { 2772 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2773 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2774 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2775 }; 2776 2777 struct mlx5_ifc_vlan_bits { 2778 u8 ethtype[0x10]; 2779 u8 prio[0x3]; 2780 u8 cfi[0x1]; 2781 u8 vid[0xc]; 2782 }; 2783 2784 struct mlx5_ifc_flow_context_bits { 2785 struct mlx5_ifc_vlan_bits push_vlan; 2786 2787 u8 group_id[0x20]; 2788 2789 u8 reserved_at_40[0x8]; 2790 u8 flow_tag[0x18]; 2791 2792 u8 reserved_at_60[0x10]; 2793 u8 action[0x10]; 2794 2795 u8 extended_destination[0x1]; 2796 u8 reserved_at_81[0x1]; 2797 u8 flow_source[0x2]; 2798 u8 reserved_at_84[0x4]; 2799 u8 destination_list_size[0x18]; 2800 2801 u8 reserved_at_a0[0x8]; 2802 u8 flow_counter_list_size[0x18]; 2803 2804 u8 packet_reformat_id[0x20]; 2805 2806 u8 modify_header_id[0x20]; 2807 2808 struct mlx5_ifc_vlan_bits push_vlan_2; 2809 2810 u8 reserved_at_120[0xe0]; 2811 2812 struct mlx5_ifc_fte_match_param_bits match_value; 2813 2814 u8 reserved_at_1200[0x600]; 2815 2816 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2817 }; 2818 2819 enum { 2820 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2821 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2822 }; 2823 2824 struct mlx5_ifc_xrc_srqc_bits { 2825 u8 state[0x4]; 2826 u8 log_xrc_srq_size[0x4]; 2827 u8 reserved_at_8[0x18]; 2828 2829 u8 wq_signature[0x1]; 2830 u8 cont_srq[0x1]; 2831 u8 reserved_at_22[0x1]; 2832 u8 rlky[0x1]; 2833 u8 basic_cyclic_rcv_wqe[0x1]; 2834 u8 log_rq_stride[0x3]; 2835 u8 xrcd[0x18]; 2836 2837 u8 page_offset[0x6]; 2838 u8 reserved_at_46[0x1]; 2839 u8 dbr_umem_valid[0x1]; 2840 u8 cqn[0x18]; 2841 2842 u8 reserved_at_60[0x20]; 2843 2844 u8 user_index_equal_xrc_srqn[0x1]; 2845 u8 reserved_at_81[0x1]; 2846 u8 log_page_size[0x6]; 2847 u8 user_index[0x18]; 2848 2849 u8 reserved_at_a0[0x20]; 2850 2851 u8 reserved_at_c0[0x8]; 2852 u8 pd[0x18]; 2853 2854 u8 lwm[0x10]; 2855 u8 wqe_cnt[0x10]; 2856 2857 u8 reserved_at_100[0x40]; 2858 2859 u8 db_record_addr_h[0x20]; 2860 2861 u8 db_record_addr_l[0x1e]; 2862 u8 reserved_at_17e[0x2]; 2863 2864 u8 reserved_at_180[0x80]; 2865 }; 2866 2867 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2868 u8 counter_error_queues[0x20]; 2869 2870 u8 total_error_queues[0x20]; 2871 2872 u8 send_queue_priority_update_flow[0x20]; 2873 2874 u8 reserved_at_60[0x20]; 2875 2876 u8 nic_receive_steering_discard[0x40]; 2877 2878 u8 receive_discard_vport_down[0x40]; 2879 2880 u8 transmit_discard_vport_down[0x40]; 2881 2882 u8 reserved_at_140[0xa0]; 2883 2884 u8 internal_rq_out_of_buffer[0x20]; 2885 2886 u8 reserved_at_200[0xe00]; 2887 }; 2888 2889 struct mlx5_ifc_traffic_counter_bits { 2890 u8 packets[0x40]; 2891 2892 u8 octets[0x40]; 2893 }; 2894 2895 struct mlx5_ifc_tisc_bits { 2896 u8 strict_lag_tx_port_affinity[0x1]; 2897 u8 tls_en[0x1]; 2898 u8 reserved_at_2[0x2]; 2899 u8 lag_tx_port_affinity[0x04]; 2900 2901 u8 reserved_at_8[0x4]; 2902 u8 prio[0x4]; 2903 u8 reserved_at_10[0x10]; 2904 2905 u8 reserved_at_20[0x100]; 2906 2907 u8 reserved_at_120[0x8]; 2908 u8 transport_domain[0x18]; 2909 2910 u8 reserved_at_140[0x8]; 2911 u8 underlay_qpn[0x18]; 2912 2913 u8 reserved_at_160[0x8]; 2914 u8 pd[0x18]; 2915 2916 u8 reserved_at_180[0x380]; 2917 }; 2918 2919 enum { 2920 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2921 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2922 }; 2923 2924 enum { 2925 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2926 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2927 }; 2928 2929 enum { 2930 MLX5_RX_HASH_FN_NONE = 0x0, 2931 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2932 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2933 }; 2934 2935 enum { 2936 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2937 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2938 }; 2939 2940 struct mlx5_ifc_tirc_bits { 2941 u8 reserved_at_0[0x20]; 2942 2943 u8 disp_type[0x4]; 2944 u8 reserved_at_24[0x1c]; 2945 2946 u8 reserved_at_40[0x40]; 2947 2948 u8 reserved_at_80[0x4]; 2949 u8 lro_timeout_period_usecs[0x10]; 2950 u8 lro_enable_mask[0x4]; 2951 u8 lro_max_ip_payload_size[0x8]; 2952 2953 u8 reserved_at_a0[0x40]; 2954 2955 u8 reserved_at_e0[0x8]; 2956 u8 inline_rqn[0x18]; 2957 2958 u8 rx_hash_symmetric[0x1]; 2959 u8 reserved_at_101[0x1]; 2960 u8 tunneled_offload_en[0x1]; 2961 u8 reserved_at_103[0x5]; 2962 u8 indirect_table[0x18]; 2963 2964 u8 rx_hash_fn[0x4]; 2965 u8 reserved_at_124[0x2]; 2966 u8 self_lb_block[0x2]; 2967 u8 transport_domain[0x18]; 2968 2969 u8 rx_hash_toeplitz_key[10][0x20]; 2970 2971 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2972 2973 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2974 2975 u8 reserved_at_2c0[0x4c0]; 2976 }; 2977 2978 enum { 2979 MLX5_SRQC_STATE_GOOD = 0x0, 2980 MLX5_SRQC_STATE_ERROR = 0x1, 2981 }; 2982 2983 struct mlx5_ifc_srqc_bits { 2984 u8 state[0x4]; 2985 u8 log_srq_size[0x4]; 2986 u8 reserved_at_8[0x18]; 2987 2988 u8 wq_signature[0x1]; 2989 u8 cont_srq[0x1]; 2990 u8 reserved_at_22[0x1]; 2991 u8 rlky[0x1]; 2992 u8 reserved_at_24[0x1]; 2993 u8 log_rq_stride[0x3]; 2994 u8 xrcd[0x18]; 2995 2996 u8 page_offset[0x6]; 2997 u8 reserved_at_46[0x2]; 2998 u8 cqn[0x18]; 2999 3000 u8 reserved_at_60[0x20]; 3001 3002 u8 reserved_at_80[0x2]; 3003 u8 log_page_size[0x6]; 3004 u8 reserved_at_88[0x18]; 3005 3006 u8 reserved_at_a0[0x20]; 3007 3008 u8 reserved_at_c0[0x8]; 3009 u8 pd[0x18]; 3010 3011 u8 lwm[0x10]; 3012 u8 wqe_cnt[0x10]; 3013 3014 u8 reserved_at_100[0x40]; 3015 3016 u8 dbr_addr[0x40]; 3017 3018 u8 reserved_at_180[0x80]; 3019 }; 3020 3021 enum { 3022 MLX5_SQC_STATE_RST = 0x0, 3023 MLX5_SQC_STATE_RDY = 0x1, 3024 MLX5_SQC_STATE_ERR = 0x3, 3025 }; 3026 3027 struct mlx5_ifc_sqc_bits { 3028 u8 rlky[0x1]; 3029 u8 cd_master[0x1]; 3030 u8 fre[0x1]; 3031 u8 flush_in_error_en[0x1]; 3032 u8 allow_multi_pkt_send_wqe[0x1]; 3033 u8 min_wqe_inline_mode[0x3]; 3034 u8 state[0x4]; 3035 u8 reg_umr[0x1]; 3036 u8 allow_swp[0x1]; 3037 u8 hairpin[0x1]; 3038 u8 reserved_at_f[0x11]; 3039 3040 u8 reserved_at_20[0x8]; 3041 u8 user_index[0x18]; 3042 3043 u8 reserved_at_40[0x8]; 3044 u8 cqn[0x18]; 3045 3046 u8 reserved_at_60[0x8]; 3047 u8 hairpin_peer_rq[0x18]; 3048 3049 u8 reserved_at_80[0x10]; 3050 u8 hairpin_peer_vhca[0x10]; 3051 3052 u8 reserved_at_a0[0x50]; 3053 3054 u8 packet_pacing_rate_limit_index[0x10]; 3055 u8 tis_lst_sz[0x10]; 3056 u8 reserved_at_110[0x10]; 3057 3058 u8 reserved_at_120[0x40]; 3059 3060 u8 reserved_at_160[0x8]; 3061 u8 tis_num_0[0x18]; 3062 3063 struct mlx5_ifc_wq_bits wq; 3064 }; 3065 3066 enum { 3067 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3068 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3069 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3070 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3071 }; 3072 3073 enum { 3074 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3075 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3076 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3077 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3078 }; 3079 3080 struct mlx5_ifc_scheduling_context_bits { 3081 u8 element_type[0x8]; 3082 u8 reserved_at_8[0x18]; 3083 3084 u8 element_attributes[0x20]; 3085 3086 u8 parent_element_id[0x20]; 3087 3088 u8 reserved_at_60[0x40]; 3089 3090 u8 bw_share[0x20]; 3091 3092 u8 max_average_bw[0x20]; 3093 3094 u8 reserved_at_e0[0x120]; 3095 }; 3096 3097 struct mlx5_ifc_rqtc_bits { 3098 u8 reserved_at_0[0xa0]; 3099 3100 u8 reserved_at_a0[0x10]; 3101 u8 rqt_max_size[0x10]; 3102 3103 u8 reserved_at_c0[0x10]; 3104 u8 rqt_actual_size[0x10]; 3105 3106 u8 reserved_at_e0[0x6a0]; 3107 3108 struct mlx5_ifc_rq_num_bits rq_num[0]; 3109 }; 3110 3111 enum { 3112 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3113 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3114 }; 3115 3116 enum { 3117 MLX5_RQC_STATE_RST = 0x0, 3118 MLX5_RQC_STATE_RDY = 0x1, 3119 MLX5_RQC_STATE_ERR = 0x3, 3120 }; 3121 3122 struct mlx5_ifc_rqc_bits { 3123 u8 rlky[0x1]; 3124 u8 delay_drop_en[0x1]; 3125 u8 scatter_fcs[0x1]; 3126 u8 vsd[0x1]; 3127 u8 mem_rq_type[0x4]; 3128 u8 state[0x4]; 3129 u8 reserved_at_c[0x1]; 3130 u8 flush_in_error_en[0x1]; 3131 u8 hairpin[0x1]; 3132 u8 reserved_at_f[0x11]; 3133 3134 u8 reserved_at_20[0x8]; 3135 u8 user_index[0x18]; 3136 3137 u8 reserved_at_40[0x8]; 3138 u8 cqn[0x18]; 3139 3140 u8 counter_set_id[0x8]; 3141 u8 reserved_at_68[0x18]; 3142 3143 u8 reserved_at_80[0x8]; 3144 u8 rmpn[0x18]; 3145 3146 u8 reserved_at_a0[0x8]; 3147 u8 hairpin_peer_sq[0x18]; 3148 3149 u8 reserved_at_c0[0x10]; 3150 u8 hairpin_peer_vhca[0x10]; 3151 3152 u8 reserved_at_e0[0xa0]; 3153 3154 struct mlx5_ifc_wq_bits wq; 3155 }; 3156 3157 enum { 3158 MLX5_RMPC_STATE_RDY = 0x1, 3159 MLX5_RMPC_STATE_ERR = 0x3, 3160 }; 3161 3162 struct mlx5_ifc_rmpc_bits { 3163 u8 reserved_at_0[0x8]; 3164 u8 state[0x4]; 3165 u8 reserved_at_c[0x14]; 3166 3167 u8 basic_cyclic_rcv_wqe[0x1]; 3168 u8 reserved_at_21[0x1f]; 3169 3170 u8 reserved_at_40[0x140]; 3171 3172 struct mlx5_ifc_wq_bits wq; 3173 }; 3174 3175 struct mlx5_ifc_nic_vport_context_bits { 3176 u8 reserved_at_0[0x5]; 3177 u8 min_wqe_inline_mode[0x3]; 3178 u8 reserved_at_8[0x15]; 3179 u8 disable_mc_local_lb[0x1]; 3180 u8 disable_uc_local_lb[0x1]; 3181 u8 roce_en[0x1]; 3182 3183 u8 arm_change_event[0x1]; 3184 u8 reserved_at_21[0x1a]; 3185 u8 event_on_mtu[0x1]; 3186 u8 event_on_promisc_change[0x1]; 3187 u8 event_on_vlan_change[0x1]; 3188 u8 event_on_mc_address_change[0x1]; 3189 u8 event_on_uc_address_change[0x1]; 3190 3191 u8 reserved_at_40[0xc]; 3192 3193 u8 affiliation_criteria[0x4]; 3194 u8 affiliated_vhca_id[0x10]; 3195 3196 u8 reserved_at_60[0xd0]; 3197 3198 u8 mtu[0x10]; 3199 3200 u8 system_image_guid[0x40]; 3201 u8 port_guid[0x40]; 3202 u8 node_guid[0x40]; 3203 3204 u8 reserved_at_200[0x140]; 3205 u8 qkey_violation_counter[0x10]; 3206 u8 reserved_at_350[0x430]; 3207 3208 u8 promisc_uc[0x1]; 3209 u8 promisc_mc[0x1]; 3210 u8 promisc_all[0x1]; 3211 u8 reserved_at_783[0x2]; 3212 u8 allowed_list_type[0x3]; 3213 u8 reserved_at_788[0xc]; 3214 u8 allowed_list_size[0xc]; 3215 3216 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3217 3218 u8 reserved_at_7e0[0x20]; 3219 3220 u8 current_uc_mac_address[0][0x40]; 3221 }; 3222 3223 enum { 3224 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3225 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3226 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3227 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3228 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3229 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3230 }; 3231 3232 struct mlx5_ifc_mkc_bits { 3233 u8 reserved_at_0[0x1]; 3234 u8 free[0x1]; 3235 u8 reserved_at_2[0x1]; 3236 u8 access_mode_4_2[0x3]; 3237 u8 reserved_at_6[0x7]; 3238 u8 relaxed_ordering_write[0x1]; 3239 u8 reserved_at_e[0x1]; 3240 u8 small_fence_on_rdma_read_response[0x1]; 3241 u8 umr_en[0x1]; 3242 u8 a[0x1]; 3243 u8 rw[0x1]; 3244 u8 rr[0x1]; 3245 u8 lw[0x1]; 3246 u8 lr[0x1]; 3247 u8 access_mode_1_0[0x2]; 3248 u8 reserved_at_18[0x8]; 3249 3250 u8 qpn[0x18]; 3251 u8 mkey_7_0[0x8]; 3252 3253 u8 reserved_at_40[0x20]; 3254 3255 u8 length64[0x1]; 3256 u8 bsf_en[0x1]; 3257 u8 sync_umr[0x1]; 3258 u8 reserved_at_63[0x2]; 3259 u8 expected_sigerr_count[0x1]; 3260 u8 reserved_at_66[0x1]; 3261 u8 en_rinval[0x1]; 3262 u8 pd[0x18]; 3263 3264 u8 start_addr[0x40]; 3265 3266 u8 len[0x40]; 3267 3268 u8 bsf_octword_size[0x20]; 3269 3270 u8 reserved_at_120[0x80]; 3271 3272 u8 translations_octword_size[0x20]; 3273 3274 u8 reserved_at_1c0[0x1b]; 3275 u8 log_page_size[0x5]; 3276 3277 u8 reserved_at_1e0[0x20]; 3278 }; 3279 3280 struct mlx5_ifc_pkey_bits { 3281 u8 reserved_at_0[0x10]; 3282 u8 pkey[0x10]; 3283 }; 3284 3285 struct mlx5_ifc_array128_auto_bits { 3286 u8 array128_auto[16][0x8]; 3287 }; 3288 3289 struct mlx5_ifc_hca_vport_context_bits { 3290 u8 field_select[0x20]; 3291 3292 u8 reserved_at_20[0xe0]; 3293 3294 u8 sm_virt_aware[0x1]; 3295 u8 has_smi[0x1]; 3296 u8 has_raw[0x1]; 3297 u8 grh_required[0x1]; 3298 u8 reserved_at_104[0xc]; 3299 u8 port_physical_state[0x4]; 3300 u8 vport_state_policy[0x4]; 3301 u8 port_state[0x4]; 3302 u8 vport_state[0x4]; 3303 3304 u8 reserved_at_120[0x20]; 3305 3306 u8 system_image_guid[0x40]; 3307 3308 u8 port_guid[0x40]; 3309 3310 u8 node_guid[0x40]; 3311 3312 u8 cap_mask1[0x20]; 3313 3314 u8 cap_mask1_field_select[0x20]; 3315 3316 u8 cap_mask2[0x20]; 3317 3318 u8 cap_mask2_field_select[0x20]; 3319 3320 u8 reserved_at_280[0x80]; 3321 3322 u8 lid[0x10]; 3323 u8 reserved_at_310[0x4]; 3324 u8 init_type_reply[0x4]; 3325 u8 lmc[0x3]; 3326 u8 subnet_timeout[0x5]; 3327 3328 u8 sm_lid[0x10]; 3329 u8 sm_sl[0x4]; 3330 u8 reserved_at_334[0xc]; 3331 3332 u8 qkey_violation_counter[0x10]; 3333 u8 pkey_violation_counter[0x10]; 3334 3335 u8 reserved_at_360[0xca0]; 3336 }; 3337 3338 struct mlx5_ifc_esw_vport_context_bits { 3339 u8 fdb_to_vport_reg_c[0x1]; 3340 u8 reserved_at_1[0x2]; 3341 u8 vport_svlan_strip[0x1]; 3342 u8 vport_cvlan_strip[0x1]; 3343 u8 vport_svlan_insert[0x1]; 3344 u8 vport_cvlan_insert[0x2]; 3345 u8 fdb_to_vport_reg_c_id[0x8]; 3346 u8 reserved_at_10[0x10]; 3347 3348 u8 reserved_at_20[0x20]; 3349 3350 u8 svlan_cfi[0x1]; 3351 u8 svlan_pcp[0x3]; 3352 u8 svlan_id[0xc]; 3353 u8 cvlan_cfi[0x1]; 3354 u8 cvlan_pcp[0x3]; 3355 u8 cvlan_id[0xc]; 3356 3357 u8 reserved_at_60[0x720]; 3358 3359 u8 sw_steering_vport_icm_address_rx[0x40]; 3360 3361 u8 sw_steering_vport_icm_address_tx[0x40]; 3362 }; 3363 3364 enum { 3365 MLX5_EQC_STATUS_OK = 0x0, 3366 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3367 }; 3368 3369 enum { 3370 MLX5_EQC_ST_ARMED = 0x9, 3371 MLX5_EQC_ST_FIRED = 0xa, 3372 }; 3373 3374 struct mlx5_ifc_eqc_bits { 3375 u8 status[0x4]; 3376 u8 reserved_at_4[0x9]; 3377 u8 ec[0x1]; 3378 u8 oi[0x1]; 3379 u8 reserved_at_f[0x5]; 3380 u8 st[0x4]; 3381 u8 reserved_at_18[0x8]; 3382 3383 u8 reserved_at_20[0x20]; 3384 3385 u8 reserved_at_40[0x14]; 3386 u8 page_offset[0x6]; 3387 u8 reserved_at_5a[0x6]; 3388 3389 u8 reserved_at_60[0x3]; 3390 u8 log_eq_size[0x5]; 3391 u8 uar_page[0x18]; 3392 3393 u8 reserved_at_80[0x20]; 3394 3395 u8 reserved_at_a0[0x18]; 3396 u8 intr[0x8]; 3397 3398 u8 reserved_at_c0[0x3]; 3399 u8 log_page_size[0x5]; 3400 u8 reserved_at_c8[0x18]; 3401 3402 u8 reserved_at_e0[0x60]; 3403 3404 u8 reserved_at_140[0x8]; 3405 u8 consumer_counter[0x18]; 3406 3407 u8 reserved_at_160[0x8]; 3408 u8 producer_counter[0x18]; 3409 3410 u8 reserved_at_180[0x80]; 3411 }; 3412 3413 enum { 3414 MLX5_DCTC_STATE_ACTIVE = 0x0, 3415 MLX5_DCTC_STATE_DRAINING = 0x1, 3416 MLX5_DCTC_STATE_DRAINED = 0x2, 3417 }; 3418 3419 enum { 3420 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3421 MLX5_DCTC_CS_RES_NA = 0x1, 3422 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3423 }; 3424 3425 enum { 3426 MLX5_DCTC_MTU_256_BYTES = 0x1, 3427 MLX5_DCTC_MTU_512_BYTES = 0x2, 3428 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3429 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3430 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3431 }; 3432 3433 struct mlx5_ifc_dctc_bits { 3434 u8 reserved_at_0[0x4]; 3435 u8 state[0x4]; 3436 u8 reserved_at_8[0x18]; 3437 3438 u8 reserved_at_20[0x8]; 3439 u8 user_index[0x18]; 3440 3441 u8 reserved_at_40[0x8]; 3442 u8 cqn[0x18]; 3443 3444 u8 counter_set_id[0x8]; 3445 u8 atomic_mode[0x4]; 3446 u8 rre[0x1]; 3447 u8 rwe[0x1]; 3448 u8 rae[0x1]; 3449 u8 atomic_like_write_en[0x1]; 3450 u8 latency_sensitive[0x1]; 3451 u8 rlky[0x1]; 3452 u8 free_ar[0x1]; 3453 u8 reserved_at_73[0xd]; 3454 3455 u8 reserved_at_80[0x8]; 3456 u8 cs_res[0x8]; 3457 u8 reserved_at_90[0x3]; 3458 u8 min_rnr_nak[0x5]; 3459 u8 reserved_at_98[0x8]; 3460 3461 u8 reserved_at_a0[0x8]; 3462 u8 srqn_xrqn[0x18]; 3463 3464 u8 reserved_at_c0[0x8]; 3465 u8 pd[0x18]; 3466 3467 u8 tclass[0x8]; 3468 u8 reserved_at_e8[0x4]; 3469 u8 flow_label[0x14]; 3470 3471 u8 dc_access_key[0x40]; 3472 3473 u8 reserved_at_140[0x5]; 3474 u8 mtu[0x3]; 3475 u8 port[0x8]; 3476 u8 pkey_index[0x10]; 3477 3478 u8 reserved_at_160[0x8]; 3479 u8 my_addr_index[0x8]; 3480 u8 reserved_at_170[0x8]; 3481 u8 hop_limit[0x8]; 3482 3483 u8 dc_access_key_violation_count[0x20]; 3484 3485 u8 reserved_at_1a0[0x14]; 3486 u8 dei_cfi[0x1]; 3487 u8 eth_prio[0x3]; 3488 u8 ecn[0x2]; 3489 u8 dscp[0x6]; 3490 3491 u8 reserved_at_1c0[0x40]; 3492 }; 3493 3494 enum { 3495 MLX5_CQC_STATUS_OK = 0x0, 3496 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3497 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3498 }; 3499 3500 enum { 3501 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3502 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3503 }; 3504 3505 enum { 3506 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3507 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3508 MLX5_CQC_ST_FIRED = 0xa, 3509 }; 3510 3511 enum { 3512 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3513 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3514 MLX5_CQ_PERIOD_NUM_MODES 3515 }; 3516 3517 struct mlx5_ifc_cqc_bits { 3518 u8 status[0x4]; 3519 u8 reserved_at_4[0x2]; 3520 u8 dbr_umem_valid[0x1]; 3521 u8 reserved_at_7[0x1]; 3522 u8 cqe_sz[0x3]; 3523 u8 cc[0x1]; 3524 u8 reserved_at_c[0x1]; 3525 u8 scqe_break_moderation_en[0x1]; 3526 u8 oi[0x1]; 3527 u8 cq_period_mode[0x2]; 3528 u8 cqe_comp_en[0x1]; 3529 u8 mini_cqe_res_format[0x2]; 3530 u8 st[0x4]; 3531 u8 reserved_at_18[0x8]; 3532 3533 u8 reserved_at_20[0x20]; 3534 3535 u8 reserved_at_40[0x14]; 3536 u8 page_offset[0x6]; 3537 u8 reserved_at_5a[0x6]; 3538 3539 u8 reserved_at_60[0x3]; 3540 u8 log_cq_size[0x5]; 3541 u8 uar_page[0x18]; 3542 3543 u8 reserved_at_80[0x4]; 3544 u8 cq_period[0xc]; 3545 u8 cq_max_count[0x10]; 3546 3547 u8 reserved_at_a0[0x18]; 3548 u8 c_eqn[0x8]; 3549 3550 u8 reserved_at_c0[0x3]; 3551 u8 log_page_size[0x5]; 3552 u8 reserved_at_c8[0x18]; 3553 3554 u8 reserved_at_e0[0x20]; 3555 3556 u8 reserved_at_100[0x8]; 3557 u8 last_notified_index[0x18]; 3558 3559 u8 reserved_at_120[0x8]; 3560 u8 last_solicit_index[0x18]; 3561 3562 u8 reserved_at_140[0x8]; 3563 u8 consumer_counter[0x18]; 3564 3565 u8 reserved_at_160[0x8]; 3566 u8 producer_counter[0x18]; 3567 3568 u8 reserved_at_180[0x40]; 3569 3570 u8 dbr_addr[0x40]; 3571 }; 3572 3573 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3574 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3575 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3576 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3577 u8 reserved_at_0[0x800]; 3578 }; 3579 3580 struct mlx5_ifc_query_adapter_param_block_bits { 3581 u8 reserved_at_0[0xc0]; 3582 3583 u8 reserved_at_c0[0x8]; 3584 u8 ieee_vendor_id[0x18]; 3585 3586 u8 reserved_at_e0[0x10]; 3587 u8 vsd_vendor_id[0x10]; 3588 3589 u8 vsd[208][0x8]; 3590 3591 u8 vsd_contd_psid[16][0x8]; 3592 }; 3593 3594 enum { 3595 MLX5_XRQC_STATE_GOOD = 0x0, 3596 MLX5_XRQC_STATE_ERROR = 0x1, 3597 }; 3598 3599 enum { 3600 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3601 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3602 }; 3603 3604 enum { 3605 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3606 }; 3607 3608 struct mlx5_ifc_tag_matching_topology_context_bits { 3609 u8 log_matching_list_sz[0x4]; 3610 u8 reserved_at_4[0xc]; 3611 u8 append_next_index[0x10]; 3612 3613 u8 sw_phase_cnt[0x10]; 3614 u8 hw_phase_cnt[0x10]; 3615 3616 u8 reserved_at_40[0x40]; 3617 }; 3618 3619 struct mlx5_ifc_xrqc_bits { 3620 u8 state[0x4]; 3621 u8 rlkey[0x1]; 3622 u8 reserved_at_5[0xf]; 3623 u8 topology[0x4]; 3624 u8 reserved_at_18[0x4]; 3625 u8 offload[0x4]; 3626 3627 u8 reserved_at_20[0x8]; 3628 u8 user_index[0x18]; 3629 3630 u8 reserved_at_40[0x8]; 3631 u8 cqn[0x18]; 3632 3633 u8 reserved_at_60[0xa0]; 3634 3635 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3636 3637 u8 reserved_at_180[0x280]; 3638 3639 struct mlx5_ifc_wq_bits wq; 3640 }; 3641 3642 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3643 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3644 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3645 u8 reserved_at_0[0x20]; 3646 }; 3647 3648 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3649 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3650 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3651 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3652 u8 reserved_at_0[0x20]; 3653 }; 3654 3655 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3656 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3657 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3658 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3659 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3660 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3661 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3662 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3663 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3664 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3665 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3666 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3667 u8 reserved_at_0[0x7c0]; 3668 }; 3669 3670 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3671 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3672 u8 reserved_at_0[0x7c0]; 3673 }; 3674 3675 union mlx5_ifc_event_auto_bits { 3676 struct mlx5_ifc_comp_event_bits comp_event; 3677 struct mlx5_ifc_dct_events_bits dct_events; 3678 struct mlx5_ifc_qp_events_bits qp_events; 3679 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3680 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3681 struct mlx5_ifc_cq_error_bits cq_error; 3682 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3683 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3684 struct mlx5_ifc_gpio_event_bits gpio_event; 3685 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3686 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3687 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3688 u8 reserved_at_0[0xe0]; 3689 }; 3690 3691 struct mlx5_ifc_health_buffer_bits { 3692 u8 reserved_at_0[0x100]; 3693 3694 u8 assert_existptr[0x20]; 3695 3696 u8 assert_callra[0x20]; 3697 3698 u8 reserved_at_140[0x40]; 3699 3700 u8 fw_version[0x20]; 3701 3702 u8 hw_id[0x20]; 3703 3704 u8 reserved_at_1c0[0x20]; 3705 3706 u8 irisc_index[0x8]; 3707 u8 synd[0x8]; 3708 u8 ext_synd[0x10]; 3709 }; 3710 3711 struct mlx5_ifc_register_loopback_control_bits { 3712 u8 no_lb[0x1]; 3713 u8 reserved_at_1[0x7]; 3714 u8 port[0x8]; 3715 u8 reserved_at_10[0x10]; 3716 3717 u8 reserved_at_20[0x60]; 3718 }; 3719 3720 struct mlx5_ifc_vport_tc_element_bits { 3721 u8 traffic_class[0x4]; 3722 u8 reserved_at_4[0xc]; 3723 u8 vport_number[0x10]; 3724 }; 3725 3726 struct mlx5_ifc_vport_element_bits { 3727 u8 reserved_at_0[0x10]; 3728 u8 vport_number[0x10]; 3729 }; 3730 3731 enum { 3732 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3733 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3734 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3735 }; 3736 3737 struct mlx5_ifc_tsar_element_bits { 3738 u8 reserved_at_0[0x8]; 3739 u8 tsar_type[0x8]; 3740 u8 reserved_at_10[0x10]; 3741 }; 3742 3743 enum { 3744 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3745 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3746 }; 3747 3748 struct mlx5_ifc_teardown_hca_out_bits { 3749 u8 status[0x8]; 3750 u8 reserved_at_8[0x18]; 3751 3752 u8 syndrome[0x20]; 3753 3754 u8 reserved_at_40[0x3f]; 3755 3756 u8 state[0x1]; 3757 }; 3758 3759 enum { 3760 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3761 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3762 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3763 }; 3764 3765 struct mlx5_ifc_teardown_hca_in_bits { 3766 u8 opcode[0x10]; 3767 u8 reserved_at_10[0x10]; 3768 3769 u8 reserved_at_20[0x10]; 3770 u8 op_mod[0x10]; 3771 3772 u8 reserved_at_40[0x10]; 3773 u8 profile[0x10]; 3774 3775 u8 reserved_at_60[0x20]; 3776 }; 3777 3778 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3779 u8 status[0x8]; 3780 u8 reserved_at_8[0x18]; 3781 3782 u8 syndrome[0x20]; 3783 3784 u8 reserved_at_40[0x40]; 3785 }; 3786 3787 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3788 u8 opcode[0x10]; 3789 u8 uid[0x10]; 3790 3791 u8 reserved_at_20[0x10]; 3792 u8 op_mod[0x10]; 3793 3794 u8 reserved_at_40[0x8]; 3795 u8 qpn[0x18]; 3796 3797 u8 reserved_at_60[0x20]; 3798 3799 u8 opt_param_mask[0x20]; 3800 3801 u8 reserved_at_a0[0x20]; 3802 3803 struct mlx5_ifc_qpc_bits qpc; 3804 3805 u8 reserved_at_800[0x80]; 3806 }; 3807 3808 struct mlx5_ifc_sqd2rts_qp_out_bits { 3809 u8 status[0x8]; 3810 u8 reserved_at_8[0x18]; 3811 3812 u8 syndrome[0x20]; 3813 3814 u8 reserved_at_40[0x40]; 3815 }; 3816 3817 struct mlx5_ifc_sqd2rts_qp_in_bits { 3818 u8 opcode[0x10]; 3819 u8 uid[0x10]; 3820 3821 u8 reserved_at_20[0x10]; 3822 u8 op_mod[0x10]; 3823 3824 u8 reserved_at_40[0x8]; 3825 u8 qpn[0x18]; 3826 3827 u8 reserved_at_60[0x20]; 3828 3829 u8 opt_param_mask[0x20]; 3830 3831 u8 reserved_at_a0[0x20]; 3832 3833 struct mlx5_ifc_qpc_bits qpc; 3834 3835 u8 reserved_at_800[0x80]; 3836 }; 3837 3838 struct mlx5_ifc_set_roce_address_out_bits { 3839 u8 status[0x8]; 3840 u8 reserved_at_8[0x18]; 3841 3842 u8 syndrome[0x20]; 3843 3844 u8 reserved_at_40[0x40]; 3845 }; 3846 3847 struct mlx5_ifc_set_roce_address_in_bits { 3848 u8 opcode[0x10]; 3849 u8 reserved_at_10[0x10]; 3850 3851 u8 reserved_at_20[0x10]; 3852 u8 op_mod[0x10]; 3853 3854 u8 roce_address_index[0x10]; 3855 u8 reserved_at_50[0xc]; 3856 u8 vhca_port_num[0x4]; 3857 3858 u8 reserved_at_60[0x20]; 3859 3860 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3861 }; 3862 3863 struct mlx5_ifc_set_mad_demux_out_bits { 3864 u8 status[0x8]; 3865 u8 reserved_at_8[0x18]; 3866 3867 u8 syndrome[0x20]; 3868 3869 u8 reserved_at_40[0x40]; 3870 }; 3871 3872 enum { 3873 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3874 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3875 }; 3876 3877 struct mlx5_ifc_set_mad_demux_in_bits { 3878 u8 opcode[0x10]; 3879 u8 reserved_at_10[0x10]; 3880 3881 u8 reserved_at_20[0x10]; 3882 u8 op_mod[0x10]; 3883 3884 u8 reserved_at_40[0x20]; 3885 3886 u8 reserved_at_60[0x6]; 3887 u8 demux_mode[0x2]; 3888 u8 reserved_at_68[0x18]; 3889 }; 3890 3891 struct mlx5_ifc_set_l2_table_entry_out_bits { 3892 u8 status[0x8]; 3893 u8 reserved_at_8[0x18]; 3894 3895 u8 syndrome[0x20]; 3896 3897 u8 reserved_at_40[0x40]; 3898 }; 3899 3900 struct mlx5_ifc_set_l2_table_entry_in_bits { 3901 u8 opcode[0x10]; 3902 u8 reserved_at_10[0x10]; 3903 3904 u8 reserved_at_20[0x10]; 3905 u8 op_mod[0x10]; 3906 3907 u8 reserved_at_40[0x60]; 3908 3909 u8 reserved_at_a0[0x8]; 3910 u8 table_index[0x18]; 3911 3912 u8 reserved_at_c0[0x20]; 3913 3914 u8 reserved_at_e0[0x13]; 3915 u8 vlan_valid[0x1]; 3916 u8 vlan[0xc]; 3917 3918 struct mlx5_ifc_mac_address_layout_bits mac_address; 3919 3920 u8 reserved_at_140[0xc0]; 3921 }; 3922 3923 struct mlx5_ifc_set_issi_out_bits { 3924 u8 status[0x8]; 3925 u8 reserved_at_8[0x18]; 3926 3927 u8 syndrome[0x20]; 3928 3929 u8 reserved_at_40[0x40]; 3930 }; 3931 3932 struct mlx5_ifc_set_issi_in_bits { 3933 u8 opcode[0x10]; 3934 u8 reserved_at_10[0x10]; 3935 3936 u8 reserved_at_20[0x10]; 3937 u8 op_mod[0x10]; 3938 3939 u8 reserved_at_40[0x10]; 3940 u8 current_issi[0x10]; 3941 3942 u8 reserved_at_60[0x20]; 3943 }; 3944 3945 struct mlx5_ifc_set_hca_cap_out_bits { 3946 u8 status[0x8]; 3947 u8 reserved_at_8[0x18]; 3948 3949 u8 syndrome[0x20]; 3950 3951 u8 reserved_at_40[0x40]; 3952 }; 3953 3954 struct mlx5_ifc_set_hca_cap_in_bits { 3955 u8 opcode[0x10]; 3956 u8 reserved_at_10[0x10]; 3957 3958 u8 reserved_at_20[0x10]; 3959 u8 op_mod[0x10]; 3960 3961 u8 reserved_at_40[0x40]; 3962 3963 union mlx5_ifc_hca_cap_union_bits capability; 3964 }; 3965 3966 enum { 3967 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3968 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3969 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3970 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3971 }; 3972 3973 struct mlx5_ifc_set_fte_out_bits { 3974 u8 status[0x8]; 3975 u8 reserved_at_8[0x18]; 3976 3977 u8 syndrome[0x20]; 3978 3979 u8 reserved_at_40[0x40]; 3980 }; 3981 3982 struct mlx5_ifc_set_fte_in_bits { 3983 u8 opcode[0x10]; 3984 u8 reserved_at_10[0x10]; 3985 3986 u8 reserved_at_20[0x10]; 3987 u8 op_mod[0x10]; 3988 3989 u8 other_vport[0x1]; 3990 u8 reserved_at_41[0xf]; 3991 u8 vport_number[0x10]; 3992 3993 u8 reserved_at_60[0x20]; 3994 3995 u8 table_type[0x8]; 3996 u8 reserved_at_88[0x18]; 3997 3998 u8 reserved_at_a0[0x8]; 3999 u8 table_id[0x18]; 4000 4001 u8 reserved_at_c0[0x18]; 4002 u8 modify_enable_mask[0x8]; 4003 4004 u8 reserved_at_e0[0x20]; 4005 4006 u8 flow_index[0x20]; 4007 4008 u8 reserved_at_120[0xe0]; 4009 4010 struct mlx5_ifc_flow_context_bits flow_context; 4011 }; 4012 4013 struct mlx5_ifc_rts2rts_qp_out_bits { 4014 u8 status[0x8]; 4015 u8 reserved_at_8[0x18]; 4016 4017 u8 syndrome[0x20]; 4018 4019 u8 reserved_at_40[0x40]; 4020 }; 4021 4022 struct mlx5_ifc_rts2rts_qp_in_bits { 4023 u8 opcode[0x10]; 4024 u8 uid[0x10]; 4025 4026 u8 reserved_at_20[0x10]; 4027 u8 op_mod[0x10]; 4028 4029 u8 reserved_at_40[0x8]; 4030 u8 qpn[0x18]; 4031 4032 u8 reserved_at_60[0x20]; 4033 4034 u8 opt_param_mask[0x20]; 4035 4036 u8 reserved_at_a0[0x20]; 4037 4038 struct mlx5_ifc_qpc_bits qpc; 4039 4040 u8 reserved_at_800[0x80]; 4041 }; 4042 4043 struct mlx5_ifc_rtr2rts_qp_out_bits { 4044 u8 status[0x8]; 4045 u8 reserved_at_8[0x18]; 4046 4047 u8 syndrome[0x20]; 4048 4049 u8 reserved_at_40[0x40]; 4050 }; 4051 4052 struct mlx5_ifc_rtr2rts_qp_in_bits { 4053 u8 opcode[0x10]; 4054 u8 uid[0x10]; 4055 4056 u8 reserved_at_20[0x10]; 4057 u8 op_mod[0x10]; 4058 4059 u8 reserved_at_40[0x8]; 4060 u8 qpn[0x18]; 4061 4062 u8 reserved_at_60[0x20]; 4063 4064 u8 opt_param_mask[0x20]; 4065 4066 u8 reserved_at_a0[0x20]; 4067 4068 struct mlx5_ifc_qpc_bits qpc; 4069 4070 u8 reserved_at_800[0x80]; 4071 }; 4072 4073 struct mlx5_ifc_rst2init_qp_out_bits { 4074 u8 status[0x8]; 4075 u8 reserved_at_8[0x18]; 4076 4077 u8 syndrome[0x20]; 4078 4079 u8 reserved_at_40[0x40]; 4080 }; 4081 4082 struct mlx5_ifc_rst2init_qp_in_bits { 4083 u8 opcode[0x10]; 4084 u8 uid[0x10]; 4085 4086 u8 reserved_at_20[0x10]; 4087 u8 op_mod[0x10]; 4088 4089 u8 reserved_at_40[0x8]; 4090 u8 qpn[0x18]; 4091 4092 u8 reserved_at_60[0x20]; 4093 4094 u8 opt_param_mask[0x20]; 4095 4096 u8 reserved_at_a0[0x20]; 4097 4098 struct mlx5_ifc_qpc_bits qpc; 4099 4100 u8 reserved_at_800[0x80]; 4101 }; 4102 4103 struct mlx5_ifc_query_xrq_out_bits { 4104 u8 status[0x8]; 4105 u8 reserved_at_8[0x18]; 4106 4107 u8 syndrome[0x20]; 4108 4109 u8 reserved_at_40[0x40]; 4110 4111 struct mlx5_ifc_xrqc_bits xrq_context; 4112 }; 4113 4114 struct mlx5_ifc_query_xrq_in_bits { 4115 u8 opcode[0x10]; 4116 u8 reserved_at_10[0x10]; 4117 4118 u8 reserved_at_20[0x10]; 4119 u8 op_mod[0x10]; 4120 4121 u8 reserved_at_40[0x8]; 4122 u8 xrqn[0x18]; 4123 4124 u8 reserved_at_60[0x20]; 4125 }; 4126 4127 struct mlx5_ifc_query_xrc_srq_out_bits { 4128 u8 status[0x8]; 4129 u8 reserved_at_8[0x18]; 4130 4131 u8 syndrome[0x20]; 4132 4133 u8 reserved_at_40[0x40]; 4134 4135 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4136 4137 u8 reserved_at_280[0x600]; 4138 4139 u8 pas[0][0x40]; 4140 }; 4141 4142 struct mlx5_ifc_query_xrc_srq_in_bits { 4143 u8 opcode[0x10]; 4144 u8 reserved_at_10[0x10]; 4145 4146 u8 reserved_at_20[0x10]; 4147 u8 op_mod[0x10]; 4148 4149 u8 reserved_at_40[0x8]; 4150 u8 xrc_srqn[0x18]; 4151 4152 u8 reserved_at_60[0x20]; 4153 }; 4154 4155 enum { 4156 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4157 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4158 }; 4159 4160 struct mlx5_ifc_query_vport_state_out_bits { 4161 u8 status[0x8]; 4162 u8 reserved_at_8[0x18]; 4163 4164 u8 syndrome[0x20]; 4165 4166 u8 reserved_at_40[0x20]; 4167 4168 u8 reserved_at_60[0x18]; 4169 u8 admin_state[0x4]; 4170 u8 state[0x4]; 4171 }; 4172 4173 enum { 4174 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4175 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4176 }; 4177 4178 struct mlx5_ifc_arm_monitor_counter_in_bits { 4179 u8 opcode[0x10]; 4180 u8 uid[0x10]; 4181 4182 u8 reserved_at_20[0x10]; 4183 u8 op_mod[0x10]; 4184 4185 u8 reserved_at_40[0x20]; 4186 4187 u8 reserved_at_60[0x20]; 4188 }; 4189 4190 struct mlx5_ifc_arm_monitor_counter_out_bits { 4191 u8 status[0x8]; 4192 u8 reserved_at_8[0x18]; 4193 4194 u8 syndrome[0x20]; 4195 4196 u8 reserved_at_40[0x40]; 4197 }; 4198 4199 enum { 4200 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4201 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4202 }; 4203 4204 enum mlx5_monitor_counter_ppcnt { 4205 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4206 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4207 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4208 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4209 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4210 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4211 }; 4212 4213 enum { 4214 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4215 }; 4216 4217 struct mlx5_ifc_monitor_counter_output_bits { 4218 u8 reserved_at_0[0x4]; 4219 u8 type[0x4]; 4220 u8 reserved_at_8[0x8]; 4221 u8 counter[0x10]; 4222 4223 u8 counter_group_id[0x20]; 4224 }; 4225 4226 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4227 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4228 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4229 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4230 4231 struct mlx5_ifc_set_monitor_counter_in_bits { 4232 u8 opcode[0x10]; 4233 u8 uid[0x10]; 4234 4235 u8 reserved_at_20[0x10]; 4236 u8 op_mod[0x10]; 4237 4238 u8 reserved_at_40[0x10]; 4239 u8 num_of_counters[0x10]; 4240 4241 u8 reserved_at_60[0x20]; 4242 4243 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4244 }; 4245 4246 struct mlx5_ifc_set_monitor_counter_out_bits { 4247 u8 status[0x8]; 4248 u8 reserved_at_8[0x18]; 4249 4250 u8 syndrome[0x20]; 4251 4252 u8 reserved_at_40[0x40]; 4253 }; 4254 4255 struct mlx5_ifc_query_vport_state_in_bits { 4256 u8 opcode[0x10]; 4257 u8 reserved_at_10[0x10]; 4258 4259 u8 reserved_at_20[0x10]; 4260 u8 op_mod[0x10]; 4261 4262 u8 other_vport[0x1]; 4263 u8 reserved_at_41[0xf]; 4264 u8 vport_number[0x10]; 4265 4266 u8 reserved_at_60[0x20]; 4267 }; 4268 4269 struct mlx5_ifc_query_vnic_env_out_bits { 4270 u8 status[0x8]; 4271 u8 reserved_at_8[0x18]; 4272 4273 u8 syndrome[0x20]; 4274 4275 u8 reserved_at_40[0x40]; 4276 4277 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4278 }; 4279 4280 enum { 4281 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4282 }; 4283 4284 struct mlx5_ifc_query_vnic_env_in_bits { 4285 u8 opcode[0x10]; 4286 u8 reserved_at_10[0x10]; 4287 4288 u8 reserved_at_20[0x10]; 4289 u8 op_mod[0x10]; 4290 4291 u8 other_vport[0x1]; 4292 u8 reserved_at_41[0xf]; 4293 u8 vport_number[0x10]; 4294 4295 u8 reserved_at_60[0x20]; 4296 }; 4297 4298 struct mlx5_ifc_query_vport_counter_out_bits { 4299 u8 status[0x8]; 4300 u8 reserved_at_8[0x18]; 4301 4302 u8 syndrome[0x20]; 4303 4304 u8 reserved_at_40[0x40]; 4305 4306 struct mlx5_ifc_traffic_counter_bits received_errors; 4307 4308 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4309 4310 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4311 4312 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4313 4314 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4315 4316 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4317 4318 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4319 4320 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4321 4322 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4323 4324 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4325 4326 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4327 4328 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4329 4330 u8 reserved_at_680[0xa00]; 4331 }; 4332 4333 enum { 4334 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4335 }; 4336 4337 struct mlx5_ifc_query_vport_counter_in_bits { 4338 u8 opcode[0x10]; 4339 u8 reserved_at_10[0x10]; 4340 4341 u8 reserved_at_20[0x10]; 4342 u8 op_mod[0x10]; 4343 4344 u8 other_vport[0x1]; 4345 u8 reserved_at_41[0xb]; 4346 u8 port_num[0x4]; 4347 u8 vport_number[0x10]; 4348 4349 u8 reserved_at_60[0x60]; 4350 4351 u8 clear[0x1]; 4352 u8 reserved_at_c1[0x1f]; 4353 4354 u8 reserved_at_e0[0x20]; 4355 }; 4356 4357 struct mlx5_ifc_query_tis_out_bits { 4358 u8 status[0x8]; 4359 u8 reserved_at_8[0x18]; 4360 4361 u8 syndrome[0x20]; 4362 4363 u8 reserved_at_40[0x40]; 4364 4365 struct mlx5_ifc_tisc_bits tis_context; 4366 }; 4367 4368 struct mlx5_ifc_query_tis_in_bits { 4369 u8 opcode[0x10]; 4370 u8 reserved_at_10[0x10]; 4371 4372 u8 reserved_at_20[0x10]; 4373 u8 op_mod[0x10]; 4374 4375 u8 reserved_at_40[0x8]; 4376 u8 tisn[0x18]; 4377 4378 u8 reserved_at_60[0x20]; 4379 }; 4380 4381 struct mlx5_ifc_query_tir_out_bits { 4382 u8 status[0x8]; 4383 u8 reserved_at_8[0x18]; 4384 4385 u8 syndrome[0x20]; 4386 4387 u8 reserved_at_40[0xc0]; 4388 4389 struct mlx5_ifc_tirc_bits tir_context; 4390 }; 4391 4392 struct mlx5_ifc_query_tir_in_bits { 4393 u8 opcode[0x10]; 4394 u8 reserved_at_10[0x10]; 4395 4396 u8 reserved_at_20[0x10]; 4397 u8 op_mod[0x10]; 4398 4399 u8 reserved_at_40[0x8]; 4400 u8 tirn[0x18]; 4401 4402 u8 reserved_at_60[0x20]; 4403 }; 4404 4405 struct mlx5_ifc_query_srq_out_bits { 4406 u8 status[0x8]; 4407 u8 reserved_at_8[0x18]; 4408 4409 u8 syndrome[0x20]; 4410 4411 u8 reserved_at_40[0x40]; 4412 4413 struct mlx5_ifc_srqc_bits srq_context_entry; 4414 4415 u8 reserved_at_280[0x600]; 4416 4417 u8 pas[0][0x40]; 4418 }; 4419 4420 struct mlx5_ifc_query_srq_in_bits { 4421 u8 opcode[0x10]; 4422 u8 reserved_at_10[0x10]; 4423 4424 u8 reserved_at_20[0x10]; 4425 u8 op_mod[0x10]; 4426 4427 u8 reserved_at_40[0x8]; 4428 u8 srqn[0x18]; 4429 4430 u8 reserved_at_60[0x20]; 4431 }; 4432 4433 struct mlx5_ifc_query_sq_out_bits { 4434 u8 status[0x8]; 4435 u8 reserved_at_8[0x18]; 4436 4437 u8 syndrome[0x20]; 4438 4439 u8 reserved_at_40[0xc0]; 4440 4441 struct mlx5_ifc_sqc_bits sq_context; 4442 }; 4443 4444 struct mlx5_ifc_query_sq_in_bits { 4445 u8 opcode[0x10]; 4446 u8 reserved_at_10[0x10]; 4447 4448 u8 reserved_at_20[0x10]; 4449 u8 op_mod[0x10]; 4450 4451 u8 reserved_at_40[0x8]; 4452 u8 sqn[0x18]; 4453 4454 u8 reserved_at_60[0x20]; 4455 }; 4456 4457 struct mlx5_ifc_query_special_contexts_out_bits { 4458 u8 status[0x8]; 4459 u8 reserved_at_8[0x18]; 4460 4461 u8 syndrome[0x20]; 4462 4463 u8 dump_fill_mkey[0x20]; 4464 4465 u8 resd_lkey[0x20]; 4466 4467 u8 null_mkey[0x20]; 4468 4469 u8 reserved_at_a0[0x60]; 4470 }; 4471 4472 struct mlx5_ifc_query_special_contexts_in_bits { 4473 u8 opcode[0x10]; 4474 u8 reserved_at_10[0x10]; 4475 4476 u8 reserved_at_20[0x10]; 4477 u8 op_mod[0x10]; 4478 4479 u8 reserved_at_40[0x40]; 4480 }; 4481 4482 struct mlx5_ifc_query_scheduling_element_out_bits { 4483 u8 opcode[0x10]; 4484 u8 reserved_at_10[0x10]; 4485 4486 u8 reserved_at_20[0x10]; 4487 u8 op_mod[0x10]; 4488 4489 u8 reserved_at_40[0xc0]; 4490 4491 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4492 4493 u8 reserved_at_300[0x100]; 4494 }; 4495 4496 enum { 4497 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4498 }; 4499 4500 struct mlx5_ifc_query_scheduling_element_in_bits { 4501 u8 opcode[0x10]; 4502 u8 reserved_at_10[0x10]; 4503 4504 u8 reserved_at_20[0x10]; 4505 u8 op_mod[0x10]; 4506 4507 u8 scheduling_hierarchy[0x8]; 4508 u8 reserved_at_48[0x18]; 4509 4510 u8 scheduling_element_id[0x20]; 4511 4512 u8 reserved_at_80[0x180]; 4513 }; 4514 4515 struct mlx5_ifc_query_rqt_out_bits { 4516 u8 status[0x8]; 4517 u8 reserved_at_8[0x18]; 4518 4519 u8 syndrome[0x20]; 4520 4521 u8 reserved_at_40[0xc0]; 4522 4523 struct mlx5_ifc_rqtc_bits rqt_context; 4524 }; 4525 4526 struct mlx5_ifc_query_rqt_in_bits { 4527 u8 opcode[0x10]; 4528 u8 reserved_at_10[0x10]; 4529 4530 u8 reserved_at_20[0x10]; 4531 u8 op_mod[0x10]; 4532 4533 u8 reserved_at_40[0x8]; 4534 u8 rqtn[0x18]; 4535 4536 u8 reserved_at_60[0x20]; 4537 }; 4538 4539 struct mlx5_ifc_query_rq_out_bits { 4540 u8 status[0x8]; 4541 u8 reserved_at_8[0x18]; 4542 4543 u8 syndrome[0x20]; 4544 4545 u8 reserved_at_40[0xc0]; 4546 4547 struct mlx5_ifc_rqc_bits rq_context; 4548 }; 4549 4550 struct mlx5_ifc_query_rq_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_at_10[0x10]; 4553 4554 u8 reserved_at_20[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 reserved_at_40[0x8]; 4558 u8 rqn[0x18]; 4559 4560 u8 reserved_at_60[0x20]; 4561 }; 4562 4563 struct mlx5_ifc_query_roce_address_out_bits { 4564 u8 status[0x8]; 4565 u8 reserved_at_8[0x18]; 4566 4567 u8 syndrome[0x20]; 4568 4569 u8 reserved_at_40[0x40]; 4570 4571 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4572 }; 4573 4574 struct mlx5_ifc_query_roce_address_in_bits { 4575 u8 opcode[0x10]; 4576 u8 reserved_at_10[0x10]; 4577 4578 u8 reserved_at_20[0x10]; 4579 u8 op_mod[0x10]; 4580 4581 u8 roce_address_index[0x10]; 4582 u8 reserved_at_50[0xc]; 4583 u8 vhca_port_num[0x4]; 4584 4585 u8 reserved_at_60[0x20]; 4586 }; 4587 4588 struct mlx5_ifc_query_rmp_out_bits { 4589 u8 status[0x8]; 4590 u8 reserved_at_8[0x18]; 4591 4592 u8 syndrome[0x20]; 4593 4594 u8 reserved_at_40[0xc0]; 4595 4596 struct mlx5_ifc_rmpc_bits rmp_context; 4597 }; 4598 4599 struct mlx5_ifc_query_rmp_in_bits { 4600 u8 opcode[0x10]; 4601 u8 reserved_at_10[0x10]; 4602 4603 u8 reserved_at_20[0x10]; 4604 u8 op_mod[0x10]; 4605 4606 u8 reserved_at_40[0x8]; 4607 u8 rmpn[0x18]; 4608 4609 u8 reserved_at_60[0x20]; 4610 }; 4611 4612 struct mlx5_ifc_query_qp_out_bits { 4613 u8 status[0x8]; 4614 u8 reserved_at_8[0x18]; 4615 4616 u8 syndrome[0x20]; 4617 4618 u8 reserved_at_40[0x40]; 4619 4620 u8 opt_param_mask[0x20]; 4621 4622 u8 reserved_at_a0[0x20]; 4623 4624 struct mlx5_ifc_qpc_bits qpc; 4625 4626 u8 reserved_at_800[0x80]; 4627 4628 u8 pas[0][0x40]; 4629 }; 4630 4631 struct mlx5_ifc_query_qp_in_bits { 4632 u8 opcode[0x10]; 4633 u8 reserved_at_10[0x10]; 4634 4635 u8 reserved_at_20[0x10]; 4636 u8 op_mod[0x10]; 4637 4638 u8 reserved_at_40[0x8]; 4639 u8 qpn[0x18]; 4640 4641 u8 reserved_at_60[0x20]; 4642 }; 4643 4644 struct mlx5_ifc_query_q_counter_out_bits { 4645 u8 status[0x8]; 4646 u8 reserved_at_8[0x18]; 4647 4648 u8 syndrome[0x20]; 4649 4650 u8 reserved_at_40[0x40]; 4651 4652 u8 rx_write_requests[0x20]; 4653 4654 u8 reserved_at_a0[0x20]; 4655 4656 u8 rx_read_requests[0x20]; 4657 4658 u8 reserved_at_e0[0x20]; 4659 4660 u8 rx_atomic_requests[0x20]; 4661 4662 u8 reserved_at_120[0x20]; 4663 4664 u8 rx_dct_connect[0x20]; 4665 4666 u8 reserved_at_160[0x20]; 4667 4668 u8 out_of_buffer[0x20]; 4669 4670 u8 reserved_at_1a0[0x20]; 4671 4672 u8 out_of_sequence[0x20]; 4673 4674 u8 reserved_at_1e0[0x20]; 4675 4676 u8 duplicate_request[0x20]; 4677 4678 u8 reserved_at_220[0x20]; 4679 4680 u8 rnr_nak_retry_err[0x20]; 4681 4682 u8 reserved_at_260[0x20]; 4683 4684 u8 packet_seq_err[0x20]; 4685 4686 u8 reserved_at_2a0[0x20]; 4687 4688 u8 implied_nak_seq_err[0x20]; 4689 4690 u8 reserved_at_2e0[0x20]; 4691 4692 u8 local_ack_timeout_err[0x20]; 4693 4694 u8 reserved_at_320[0xa0]; 4695 4696 u8 resp_local_length_error[0x20]; 4697 4698 u8 req_local_length_error[0x20]; 4699 4700 u8 resp_local_qp_error[0x20]; 4701 4702 u8 local_operation_error[0x20]; 4703 4704 u8 resp_local_protection[0x20]; 4705 4706 u8 req_local_protection[0x20]; 4707 4708 u8 resp_cqe_error[0x20]; 4709 4710 u8 req_cqe_error[0x20]; 4711 4712 u8 req_mw_binding[0x20]; 4713 4714 u8 req_bad_response[0x20]; 4715 4716 u8 req_remote_invalid_request[0x20]; 4717 4718 u8 resp_remote_invalid_request[0x20]; 4719 4720 u8 req_remote_access_errors[0x20]; 4721 4722 u8 resp_remote_access_errors[0x20]; 4723 4724 u8 req_remote_operation_errors[0x20]; 4725 4726 u8 req_transport_retries_exceeded[0x20]; 4727 4728 u8 cq_overflow[0x20]; 4729 4730 u8 resp_cqe_flush_error[0x20]; 4731 4732 u8 req_cqe_flush_error[0x20]; 4733 4734 u8 reserved_at_620[0x1e0]; 4735 }; 4736 4737 struct mlx5_ifc_query_q_counter_in_bits { 4738 u8 opcode[0x10]; 4739 u8 reserved_at_10[0x10]; 4740 4741 u8 reserved_at_20[0x10]; 4742 u8 op_mod[0x10]; 4743 4744 u8 reserved_at_40[0x80]; 4745 4746 u8 clear[0x1]; 4747 u8 reserved_at_c1[0x1f]; 4748 4749 u8 reserved_at_e0[0x18]; 4750 u8 counter_set_id[0x8]; 4751 }; 4752 4753 struct mlx5_ifc_query_pages_out_bits { 4754 u8 status[0x8]; 4755 u8 reserved_at_8[0x18]; 4756 4757 u8 syndrome[0x20]; 4758 4759 u8 embedded_cpu_function[0x1]; 4760 u8 reserved_at_41[0xf]; 4761 u8 function_id[0x10]; 4762 4763 u8 num_pages[0x20]; 4764 }; 4765 4766 enum { 4767 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4768 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4769 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4770 }; 4771 4772 struct mlx5_ifc_query_pages_in_bits { 4773 u8 opcode[0x10]; 4774 u8 reserved_at_10[0x10]; 4775 4776 u8 reserved_at_20[0x10]; 4777 u8 op_mod[0x10]; 4778 4779 u8 embedded_cpu_function[0x1]; 4780 u8 reserved_at_41[0xf]; 4781 u8 function_id[0x10]; 4782 4783 u8 reserved_at_60[0x20]; 4784 }; 4785 4786 struct mlx5_ifc_query_nic_vport_context_out_bits { 4787 u8 status[0x8]; 4788 u8 reserved_at_8[0x18]; 4789 4790 u8 syndrome[0x20]; 4791 4792 u8 reserved_at_40[0x40]; 4793 4794 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4795 }; 4796 4797 struct mlx5_ifc_query_nic_vport_context_in_bits { 4798 u8 opcode[0x10]; 4799 u8 reserved_at_10[0x10]; 4800 4801 u8 reserved_at_20[0x10]; 4802 u8 op_mod[0x10]; 4803 4804 u8 other_vport[0x1]; 4805 u8 reserved_at_41[0xf]; 4806 u8 vport_number[0x10]; 4807 4808 u8 reserved_at_60[0x5]; 4809 u8 allowed_list_type[0x3]; 4810 u8 reserved_at_68[0x18]; 4811 }; 4812 4813 struct mlx5_ifc_query_mkey_out_bits { 4814 u8 status[0x8]; 4815 u8 reserved_at_8[0x18]; 4816 4817 u8 syndrome[0x20]; 4818 4819 u8 reserved_at_40[0x40]; 4820 4821 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4822 4823 u8 reserved_at_280[0x600]; 4824 4825 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4826 4827 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4828 }; 4829 4830 struct mlx5_ifc_query_mkey_in_bits { 4831 u8 opcode[0x10]; 4832 u8 reserved_at_10[0x10]; 4833 4834 u8 reserved_at_20[0x10]; 4835 u8 op_mod[0x10]; 4836 4837 u8 reserved_at_40[0x8]; 4838 u8 mkey_index[0x18]; 4839 4840 u8 pg_access[0x1]; 4841 u8 reserved_at_61[0x1f]; 4842 }; 4843 4844 struct mlx5_ifc_query_mad_demux_out_bits { 4845 u8 status[0x8]; 4846 u8 reserved_at_8[0x18]; 4847 4848 u8 syndrome[0x20]; 4849 4850 u8 reserved_at_40[0x40]; 4851 4852 u8 mad_dumux_parameters_block[0x20]; 4853 }; 4854 4855 struct mlx5_ifc_query_mad_demux_in_bits { 4856 u8 opcode[0x10]; 4857 u8 reserved_at_10[0x10]; 4858 4859 u8 reserved_at_20[0x10]; 4860 u8 op_mod[0x10]; 4861 4862 u8 reserved_at_40[0x40]; 4863 }; 4864 4865 struct mlx5_ifc_query_l2_table_entry_out_bits { 4866 u8 status[0x8]; 4867 u8 reserved_at_8[0x18]; 4868 4869 u8 syndrome[0x20]; 4870 4871 u8 reserved_at_40[0xa0]; 4872 4873 u8 reserved_at_e0[0x13]; 4874 u8 vlan_valid[0x1]; 4875 u8 vlan[0xc]; 4876 4877 struct mlx5_ifc_mac_address_layout_bits mac_address; 4878 4879 u8 reserved_at_140[0xc0]; 4880 }; 4881 4882 struct mlx5_ifc_query_l2_table_entry_in_bits { 4883 u8 opcode[0x10]; 4884 u8 reserved_at_10[0x10]; 4885 4886 u8 reserved_at_20[0x10]; 4887 u8 op_mod[0x10]; 4888 4889 u8 reserved_at_40[0x60]; 4890 4891 u8 reserved_at_a0[0x8]; 4892 u8 table_index[0x18]; 4893 4894 u8 reserved_at_c0[0x140]; 4895 }; 4896 4897 struct mlx5_ifc_query_issi_out_bits { 4898 u8 status[0x8]; 4899 u8 reserved_at_8[0x18]; 4900 4901 u8 syndrome[0x20]; 4902 4903 u8 reserved_at_40[0x10]; 4904 u8 current_issi[0x10]; 4905 4906 u8 reserved_at_60[0xa0]; 4907 4908 u8 reserved_at_100[76][0x8]; 4909 u8 supported_issi_dw0[0x20]; 4910 }; 4911 4912 struct mlx5_ifc_query_issi_in_bits { 4913 u8 opcode[0x10]; 4914 u8 reserved_at_10[0x10]; 4915 4916 u8 reserved_at_20[0x10]; 4917 u8 op_mod[0x10]; 4918 4919 u8 reserved_at_40[0x40]; 4920 }; 4921 4922 struct mlx5_ifc_set_driver_version_out_bits { 4923 u8 status[0x8]; 4924 u8 reserved_0[0x18]; 4925 4926 u8 syndrome[0x20]; 4927 u8 reserved_1[0x40]; 4928 }; 4929 4930 struct mlx5_ifc_set_driver_version_in_bits { 4931 u8 opcode[0x10]; 4932 u8 reserved_0[0x10]; 4933 4934 u8 reserved_1[0x10]; 4935 u8 op_mod[0x10]; 4936 4937 u8 reserved_2[0x40]; 4938 u8 driver_version[64][0x8]; 4939 }; 4940 4941 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_at_8[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_at_40[0x40]; 4948 4949 struct mlx5_ifc_pkey_bits pkey[0]; 4950 }; 4951 4952 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4953 u8 opcode[0x10]; 4954 u8 reserved_at_10[0x10]; 4955 4956 u8 reserved_at_20[0x10]; 4957 u8 op_mod[0x10]; 4958 4959 u8 other_vport[0x1]; 4960 u8 reserved_at_41[0xb]; 4961 u8 port_num[0x4]; 4962 u8 vport_number[0x10]; 4963 4964 u8 reserved_at_60[0x10]; 4965 u8 pkey_index[0x10]; 4966 }; 4967 4968 enum { 4969 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4970 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4971 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4972 }; 4973 4974 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4975 u8 status[0x8]; 4976 u8 reserved_at_8[0x18]; 4977 4978 u8 syndrome[0x20]; 4979 4980 u8 reserved_at_40[0x20]; 4981 4982 u8 gids_num[0x10]; 4983 u8 reserved_at_70[0x10]; 4984 4985 struct mlx5_ifc_array128_auto_bits gid[0]; 4986 }; 4987 4988 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4989 u8 opcode[0x10]; 4990 u8 reserved_at_10[0x10]; 4991 4992 u8 reserved_at_20[0x10]; 4993 u8 op_mod[0x10]; 4994 4995 u8 other_vport[0x1]; 4996 u8 reserved_at_41[0xb]; 4997 u8 port_num[0x4]; 4998 u8 vport_number[0x10]; 4999 5000 u8 reserved_at_60[0x10]; 5001 u8 gid_index[0x10]; 5002 }; 5003 5004 struct mlx5_ifc_query_hca_vport_context_out_bits { 5005 u8 status[0x8]; 5006 u8 reserved_at_8[0x18]; 5007 5008 u8 syndrome[0x20]; 5009 5010 u8 reserved_at_40[0x40]; 5011 5012 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5013 }; 5014 5015 struct mlx5_ifc_query_hca_vport_context_in_bits { 5016 u8 opcode[0x10]; 5017 u8 reserved_at_10[0x10]; 5018 5019 u8 reserved_at_20[0x10]; 5020 u8 op_mod[0x10]; 5021 5022 u8 other_vport[0x1]; 5023 u8 reserved_at_41[0xb]; 5024 u8 port_num[0x4]; 5025 u8 vport_number[0x10]; 5026 5027 u8 reserved_at_60[0x20]; 5028 }; 5029 5030 struct mlx5_ifc_query_hca_cap_out_bits { 5031 u8 status[0x8]; 5032 u8 reserved_at_8[0x18]; 5033 5034 u8 syndrome[0x20]; 5035 5036 u8 reserved_at_40[0x40]; 5037 5038 union mlx5_ifc_hca_cap_union_bits capability; 5039 }; 5040 5041 struct mlx5_ifc_query_hca_cap_in_bits { 5042 u8 opcode[0x10]; 5043 u8 reserved_at_10[0x10]; 5044 5045 u8 reserved_at_20[0x10]; 5046 u8 op_mod[0x10]; 5047 5048 u8 other_function[0x1]; 5049 u8 reserved_at_41[0xf]; 5050 u8 function_id[0x10]; 5051 5052 u8 reserved_at_60[0x20]; 5053 }; 5054 5055 struct mlx5_ifc_other_hca_cap_bits { 5056 u8 roce[0x1]; 5057 u8 reserved_at_1[0x27f]; 5058 }; 5059 5060 struct mlx5_ifc_query_other_hca_cap_out_bits { 5061 u8 status[0x8]; 5062 u8 reserved_at_8[0x18]; 5063 5064 u8 syndrome[0x20]; 5065 5066 u8 reserved_at_40[0x40]; 5067 5068 struct mlx5_ifc_other_hca_cap_bits other_capability; 5069 }; 5070 5071 struct mlx5_ifc_query_other_hca_cap_in_bits { 5072 u8 opcode[0x10]; 5073 u8 reserved_at_10[0x10]; 5074 5075 u8 reserved_at_20[0x10]; 5076 u8 op_mod[0x10]; 5077 5078 u8 reserved_at_40[0x10]; 5079 u8 function_id[0x10]; 5080 5081 u8 reserved_at_60[0x20]; 5082 }; 5083 5084 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5085 u8 status[0x8]; 5086 u8 reserved_at_8[0x18]; 5087 5088 u8 syndrome[0x20]; 5089 5090 u8 reserved_at_40[0x40]; 5091 }; 5092 5093 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5094 u8 opcode[0x10]; 5095 u8 reserved_at_10[0x10]; 5096 5097 u8 reserved_at_20[0x10]; 5098 u8 op_mod[0x10]; 5099 5100 u8 reserved_at_40[0x10]; 5101 u8 function_id[0x10]; 5102 u8 field_select[0x20]; 5103 5104 struct mlx5_ifc_other_hca_cap_bits other_capability; 5105 }; 5106 5107 struct mlx5_ifc_flow_table_context_bits { 5108 u8 reformat_en[0x1]; 5109 u8 decap_en[0x1]; 5110 u8 sw_owner[0x1]; 5111 u8 termination_table[0x1]; 5112 u8 table_miss_action[0x4]; 5113 u8 level[0x8]; 5114 u8 reserved_at_10[0x8]; 5115 u8 log_size[0x8]; 5116 5117 u8 reserved_at_20[0x8]; 5118 u8 table_miss_id[0x18]; 5119 5120 u8 reserved_at_40[0x8]; 5121 u8 lag_master_next_table_id[0x18]; 5122 5123 u8 reserved_at_60[0x60]; 5124 5125 u8 sw_owner_icm_root_1[0x40]; 5126 5127 u8 sw_owner_icm_root_0[0x40]; 5128 5129 }; 5130 5131 struct mlx5_ifc_query_flow_table_out_bits { 5132 u8 status[0x8]; 5133 u8 reserved_at_8[0x18]; 5134 5135 u8 syndrome[0x20]; 5136 5137 u8 reserved_at_40[0x80]; 5138 5139 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5140 }; 5141 5142 struct mlx5_ifc_query_flow_table_in_bits { 5143 u8 opcode[0x10]; 5144 u8 reserved_at_10[0x10]; 5145 5146 u8 reserved_at_20[0x10]; 5147 u8 op_mod[0x10]; 5148 5149 u8 reserved_at_40[0x40]; 5150 5151 u8 table_type[0x8]; 5152 u8 reserved_at_88[0x18]; 5153 5154 u8 reserved_at_a0[0x8]; 5155 u8 table_id[0x18]; 5156 5157 u8 reserved_at_c0[0x140]; 5158 }; 5159 5160 struct mlx5_ifc_query_fte_out_bits { 5161 u8 status[0x8]; 5162 u8 reserved_at_8[0x18]; 5163 5164 u8 syndrome[0x20]; 5165 5166 u8 reserved_at_40[0x1c0]; 5167 5168 struct mlx5_ifc_flow_context_bits flow_context; 5169 }; 5170 5171 struct mlx5_ifc_query_fte_in_bits { 5172 u8 opcode[0x10]; 5173 u8 reserved_at_10[0x10]; 5174 5175 u8 reserved_at_20[0x10]; 5176 u8 op_mod[0x10]; 5177 5178 u8 reserved_at_40[0x40]; 5179 5180 u8 table_type[0x8]; 5181 u8 reserved_at_88[0x18]; 5182 5183 u8 reserved_at_a0[0x8]; 5184 u8 table_id[0x18]; 5185 5186 u8 reserved_at_c0[0x40]; 5187 5188 u8 flow_index[0x20]; 5189 5190 u8 reserved_at_120[0xe0]; 5191 }; 5192 5193 enum { 5194 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5195 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5196 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5197 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5198 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5199 }; 5200 5201 struct mlx5_ifc_query_flow_group_out_bits { 5202 u8 status[0x8]; 5203 u8 reserved_at_8[0x18]; 5204 5205 u8 syndrome[0x20]; 5206 5207 u8 reserved_at_40[0xa0]; 5208 5209 u8 start_flow_index[0x20]; 5210 5211 u8 reserved_at_100[0x20]; 5212 5213 u8 end_flow_index[0x20]; 5214 5215 u8 reserved_at_140[0xa0]; 5216 5217 u8 reserved_at_1e0[0x18]; 5218 u8 match_criteria_enable[0x8]; 5219 5220 struct mlx5_ifc_fte_match_param_bits match_criteria; 5221 5222 u8 reserved_at_1200[0xe00]; 5223 }; 5224 5225 struct mlx5_ifc_query_flow_group_in_bits { 5226 u8 opcode[0x10]; 5227 u8 reserved_at_10[0x10]; 5228 5229 u8 reserved_at_20[0x10]; 5230 u8 op_mod[0x10]; 5231 5232 u8 reserved_at_40[0x40]; 5233 5234 u8 table_type[0x8]; 5235 u8 reserved_at_88[0x18]; 5236 5237 u8 reserved_at_a0[0x8]; 5238 u8 table_id[0x18]; 5239 5240 u8 group_id[0x20]; 5241 5242 u8 reserved_at_e0[0x120]; 5243 }; 5244 5245 struct mlx5_ifc_query_flow_counter_out_bits { 5246 u8 status[0x8]; 5247 u8 reserved_at_8[0x18]; 5248 5249 u8 syndrome[0x20]; 5250 5251 u8 reserved_at_40[0x40]; 5252 5253 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5254 }; 5255 5256 struct mlx5_ifc_query_flow_counter_in_bits { 5257 u8 opcode[0x10]; 5258 u8 reserved_at_10[0x10]; 5259 5260 u8 reserved_at_20[0x10]; 5261 u8 op_mod[0x10]; 5262 5263 u8 reserved_at_40[0x80]; 5264 5265 u8 clear[0x1]; 5266 u8 reserved_at_c1[0xf]; 5267 u8 num_of_counters[0x10]; 5268 5269 u8 flow_counter_id[0x20]; 5270 }; 5271 5272 struct mlx5_ifc_query_esw_vport_context_out_bits { 5273 u8 status[0x8]; 5274 u8 reserved_at_8[0x18]; 5275 5276 u8 syndrome[0x20]; 5277 5278 u8 reserved_at_40[0x40]; 5279 5280 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5281 }; 5282 5283 struct mlx5_ifc_query_esw_vport_context_in_bits { 5284 u8 opcode[0x10]; 5285 u8 reserved_at_10[0x10]; 5286 5287 u8 reserved_at_20[0x10]; 5288 u8 op_mod[0x10]; 5289 5290 u8 other_vport[0x1]; 5291 u8 reserved_at_41[0xf]; 5292 u8 vport_number[0x10]; 5293 5294 u8 reserved_at_60[0x20]; 5295 }; 5296 5297 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5298 u8 status[0x8]; 5299 u8 reserved_at_8[0x18]; 5300 5301 u8 syndrome[0x20]; 5302 5303 u8 reserved_at_40[0x40]; 5304 }; 5305 5306 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5307 u8 reserved_at_0[0x1b]; 5308 u8 fdb_to_vport_reg_c_id[0x1]; 5309 u8 vport_cvlan_insert[0x1]; 5310 u8 vport_svlan_insert[0x1]; 5311 u8 vport_cvlan_strip[0x1]; 5312 u8 vport_svlan_strip[0x1]; 5313 }; 5314 5315 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5316 u8 opcode[0x10]; 5317 u8 reserved_at_10[0x10]; 5318 5319 u8 reserved_at_20[0x10]; 5320 u8 op_mod[0x10]; 5321 5322 u8 other_vport[0x1]; 5323 u8 reserved_at_41[0xf]; 5324 u8 vport_number[0x10]; 5325 5326 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5327 5328 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5329 }; 5330 5331 struct mlx5_ifc_query_eq_out_bits { 5332 u8 status[0x8]; 5333 u8 reserved_at_8[0x18]; 5334 5335 u8 syndrome[0x20]; 5336 5337 u8 reserved_at_40[0x40]; 5338 5339 struct mlx5_ifc_eqc_bits eq_context_entry; 5340 5341 u8 reserved_at_280[0x40]; 5342 5343 u8 event_bitmask[0x40]; 5344 5345 u8 reserved_at_300[0x580]; 5346 5347 u8 pas[0][0x40]; 5348 }; 5349 5350 struct mlx5_ifc_query_eq_in_bits { 5351 u8 opcode[0x10]; 5352 u8 reserved_at_10[0x10]; 5353 5354 u8 reserved_at_20[0x10]; 5355 u8 op_mod[0x10]; 5356 5357 u8 reserved_at_40[0x18]; 5358 u8 eq_number[0x8]; 5359 5360 u8 reserved_at_60[0x20]; 5361 }; 5362 5363 struct mlx5_ifc_packet_reformat_context_in_bits { 5364 u8 reserved_at_0[0x5]; 5365 u8 reformat_type[0x3]; 5366 u8 reserved_at_8[0xe]; 5367 u8 reformat_data_size[0xa]; 5368 5369 u8 reserved_at_20[0x10]; 5370 u8 reformat_data[2][0x8]; 5371 5372 u8 more_reformat_data[0][0x8]; 5373 }; 5374 5375 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5376 u8 status[0x8]; 5377 u8 reserved_at_8[0x18]; 5378 5379 u8 syndrome[0x20]; 5380 5381 u8 reserved_at_40[0xa0]; 5382 5383 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5384 }; 5385 5386 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5387 u8 opcode[0x10]; 5388 u8 reserved_at_10[0x10]; 5389 5390 u8 reserved_at_20[0x10]; 5391 u8 op_mod[0x10]; 5392 5393 u8 packet_reformat_id[0x20]; 5394 5395 u8 reserved_at_60[0xa0]; 5396 }; 5397 5398 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5399 u8 status[0x8]; 5400 u8 reserved_at_8[0x18]; 5401 5402 u8 syndrome[0x20]; 5403 5404 u8 packet_reformat_id[0x20]; 5405 5406 u8 reserved_at_60[0x20]; 5407 }; 5408 5409 enum mlx5_reformat_ctx_type { 5410 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5411 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5412 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5413 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5414 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5415 }; 5416 5417 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5418 u8 opcode[0x10]; 5419 u8 reserved_at_10[0x10]; 5420 5421 u8 reserved_at_20[0x10]; 5422 u8 op_mod[0x10]; 5423 5424 u8 reserved_at_40[0xa0]; 5425 5426 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5427 }; 5428 5429 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5430 u8 status[0x8]; 5431 u8 reserved_at_8[0x18]; 5432 5433 u8 syndrome[0x20]; 5434 5435 u8 reserved_at_40[0x40]; 5436 }; 5437 5438 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5439 u8 opcode[0x10]; 5440 u8 reserved_at_10[0x10]; 5441 5442 u8 reserved_20[0x10]; 5443 u8 op_mod[0x10]; 5444 5445 u8 packet_reformat_id[0x20]; 5446 5447 u8 reserved_60[0x20]; 5448 }; 5449 5450 struct mlx5_ifc_set_action_in_bits { 5451 u8 action_type[0x4]; 5452 u8 field[0xc]; 5453 u8 reserved_at_10[0x3]; 5454 u8 offset[0x5]; 5455 u8 reserved_at_18[0x3]; 5456 u8 length[0x5]; 5457 5458 u8 data[0x20]; 5459 }; 5460 5461 struct mlx5_ifc_add_action_in_bits { 5462 u8 action_type[0x4]; 5463 u8 field[0xc]; 5464 u8 reserved_at_10[0x10]; 5465 5466 u8 data[0x20]; 5467 }; 5468 5469 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5470 struct mlx5_ifc_set_action_in_bits set_action_in; 5471 struct mlx5_ifc_add_action_in_bits add_action_in; 5472 u8 reserved_at_0[0x40]; 5473 }; 5474 5475 enum { 5476 MLX5_ACTION_TYPE_SET = 0x1, 5477 MLX5_ACTION_TYPE_ADD = 0x2, 5478 }; 5479 5480 enum { 5481 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5482 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5483 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5484 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5485 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5486 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5487 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5488 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5489 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5490 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5491 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5492 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5493 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5494 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5495 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5496 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5497 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5498 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5499 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5500 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5501 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5502 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5503 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5504 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5505 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5506 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5507 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5508 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5509 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5510 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5511 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5512 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5513 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5514 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5515 }; 5516 5517 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5518 u8 status[0x8]; 5519 u8 reserved_at_8[0x18]; 5520 5521 u8 syndrome[0x20]; 5522 5523 u8 modify_header_id[0x20]; 5524 5525 u8 reserved_at_60[0x20]; 5526 }; 5527 5528 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5529 u8 opcode[0x10]; 5530 u8 reserved_at_10[0x10]; 5531 5532 u8 reserved_at_20[0x10]; 5533 u8 op_mod[0x10]; 5534 5535 u8 reserved_at_40[0x20]; 5536 5537 u8 table_type[0x8]; 5538 u8 reserved_at_68[0x10]; 5539 u8 num_of_actions[0x8]; 5540 5541 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5542 }; 5543 5544 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5545 u8 status[0x8]; 5546 u8 reserved_at_8[0x18]; 5547 5548 u8 syndrome[0x20]; 5549 5550 u8 reserved_at_40[0x40]; 5551 }; 5552 5553 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5554 u8 opcode[0x10]; 5555 u8 reserved_at_10[0x10]; 5556 5557 u8 reserved_at_20[0x10]; 5558 u8 op_mod[0x10]; 5559 5560 u8 modify_header_id[0x20]; 5561 5562 u8 reserved_at_60[0x20]; 5563 }; 5564 5565 struct mlx5_ifc_query_dct_out_bits { 5566 u8 status[0x8]; 5567 u8 reserved_at_8[0x18]; 5568 5569 u8 syndrome[0x20]; 5570 5571 u8 reserved_at_40[0x40]; 5572 5573 struct mlx5_ifc_dctc_bits dct_context_entry; 5574 5575 u8 reserved_at_280[0x180]; 5576 }; 5577 5578 struct mlx5_ifc_query_dct_in_bits { 5579 u8 opcode[0x10]; 5580 u8 reserved_at_10[0x10]; 5581 5582 u8 reserved_at_20[0x10]; 5583 u8 op_mod[0x10]; 5584 5585 u8 reserved_at_40[0x8]; 5586 u8 dctn[0x18]; 5587 5588 u8 reserved_at_60[0x20]; 5589 }; 5590 5591 struct mlx5_ifc_query_cq_out_bits { 5592 u8 status[0x8]; 5593 u8 reserved_at_8[0x18]; 5594 5595 u8 syndrome[0x20]; 5596 5597 u8 reserved_at_40[0x40]; 5598 5599 struct mlx5_ifc_cqc_bits cq_context; 5600 5601 u8 reserved_at_280[0x600]; 5602 5603 u8 pas[0][0x40]; 5604 }; 5605 5606 struct mlx5_ifc_query_cq_in_bits { 5607 u8 opcode[0x10]; 5608 u8 reserved_at_10[0x10]; 5609 5610 u8 reserved_at_20[0x10]; 5611 u8 op_mod[0x10]; 5612 5613 u8 reserved_at_40[0x8]; 5614 u8 cqn[0x18]; 5615 5616 u8 reserved_at_60[0x20]; 5617 }; 5618 5619 struct mlx5_ifc_query_cong_status_out_bits { 5620 u8 status[0x8]; 5621 u8 reserved_at_8[0x18]; 5622 5623 u8 syndrome[0x20]; 5624 5625 u8 reserved_at_40[0x20]; 5626 5627 u8 enable[0x1]; 5628 u8 tag_enable[0x1]; 5629 u8 reserved_at_62[0x1e]; 5630 }; 5631 5632 struct mlx5_ifc_query_cong_status_in_bits { 5633 u8 opcode[0x10]; 5634 u8 reserved_at_10[0x10]; 5635 5636 u8 reserved_at_20[0x10]; 5637 u8 op_mod[0x10]; 5638 5639 u8 reserved_at_40[0x18]; 5640 u8 priority[0x4]; 5641 u8 cong_protocol[0x4]; 5642 5643 u8 reserved_at_60[0x20]; 5644 }; 5645 5646 struct mlx5_ifc_query_cong_statistics_out_bits { 5647 u8 status[0x8]; 5648 u8 reserved_at_8[0x18]; 5649 5650 u8 syndrome[0x20]; 5651 5652 u8 reserved_at_40[0x40]; 5653 5654 u8 rp_cur_flows[0x20]; 5655 5656 u8 sum_flows[0x20]; 5657 5658 u8 rp_cnp_ignored_high[0x20]; 5659 5660 u8 rp_cnp_ignored_low[0x20]; 5661 5662 u8 rp_cnp_handled_high[0x20]; 5663 5664 u8 rp_cnp_handled_low[0x20]; 5665 5666 u8 reserved_at_140[0x100]; 5667 5668 u8 time_stamp_high[0x20]; 5669 5670 u8 time_stamp_low[0x20]; 5671 5672 u8 accumulators_period[0x20]; 5673 5674 u8 np_ecn_marked_roce_packets_high[0x20]; 5675 5676 u8 np_ecn_marked_roce_packets_low[0x20]; 5677 5678 u8 np_cnp_sent_high[0x20]; 5679 5680 u8 np_cnp_sent_low[0x20]; 5681 5682 u8 reserved_at_320[0x560]; 5683 }; 5684 5685 struct mlx5_ifc_query_cong_statistics_in_bits { 5686 u8 opcode[0x10]; 5687 u8 reserved_at_10[0x10]; 5688 5689 u8 reserved_at_20[0x10]; 5690 u8 op_mod[0x10]; 5691 5692 u8 clear[0x1]; 5693 u8 reserved_at_41[0x1f]; 5694 5695 u8 reserved_at_60[0x20]; 5696 }; 5697 5698 struct mlx5_ifc_query_cong_params_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_at_8[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_at_40[0x40]; 5705 5706 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5707 }; 5708 5709 struct mlx5_ifc_query_cong_params_in_bits { 5710 u8 opcode[0x10]; 5711 u8 reserved_at_10[0x10]; 5712 5713 u8 reserved_at_20[0x10]; 5714 u8 op_mod[0x10]; 5715 5716 u8 reserved_at_40[0x1c]; 5717 u8 cong_protocol[0x4]; 5718 5719 u8 reserved_at_60[0x20]; 5720 }; 5721 5722 struct mlx5_ifc_query_adapter_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_at_8[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_at_40[0x40]; 5729 5730 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5731 }; 5732 5733 struct mlx5_ifc_query_adapter_in_bits { 5734 u8 opcode[0x10]; 5735 u8 reserved_at_10[0x10]; 5736 5737 u8 reserved_at_20[0x10]; 5738 u8 op_mod[0x10]; 5739 5740 u8 reserved_at_40[0x40]; 5741 }; 5742 5743 struct mlx5_ifc_qp_2rst_out_bits { 5744 u8 status[0x8]; 5745 u8 reserved_at_8[0x18]; 5746 5747 u8 syndrome[0x20]; 5748 5749 u8 reserved_at_40[0x40]; 5750 }; 5751 5752 struct mlx5_ifc_qp_2rst_in_bits { 5753 u8 opcode[0x10]; 5754 u8 uid[0x10]; 5755 5756 u8 reserved_at_20[0x10]; 5757 u8 op_mod[0x10]; 5758 5759 u8 reserved_at_40[0x8]; 5760 u8 qpn[0x18]; 5761 5762 u8 reserved_at_60[0x20]; 5763 }; 5764 5765 struct mlx5_ifc_qp_2err_out_bits { 5766 u8 status[0x8]; 5767 u8 reserved_at_8[0x18]; 5768 5769 u8 syndrome[0x20]; 5770 5771 u8 reserved_at_40[0x40]; 5772 }; 5773 5774 struct mlx5_ifc_qp_2err_in_bits { 5775 u8 opcode[0x10]; 5776 u8 uid[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 reserved_at_40[0x8]; 5782 u8 qpn[0x18]; 5783 5784 u8 reserved_at_60[0x20]; 5785 }; 5786 5787 struct mlx5_ifc_page_fault_resume_out_bits { 5788 u8 status[0x8]; 5789 u8 reserved_at_8[0x18]; 5790 5791 u8 syndrome[0x20]; 5792 5793 u8 reserved_at_40[0x40]; 5794 }; 5795 5796 struct mlx5_ifc_page_fault_resume_in_bits { 5797 u8 opcode[0x10]; 5798 u8 reserved_at_10[0x10]; 5799 5800 u8 reserved_at_20[0x10]; 5801 u8 op_mod[0x10]; 5802 5803 u8 error[0x1]; 5804 u8 reserved_at_41[0x4]; 5805 u8 page_fault_type[0x3]; 5806 u8 wq_number[0x18]; 5807 5808 u8 reserved_at_60[0x8]; 5809 u8 token[0x18]; 5810 }; 5811 5812 struct mlx5_ifc_nop_out_bits { 5813 u8 status[0x8]; 5814 u8 reserved_at_8[0x18]; 5815 5816 u8 syndrome[0x20]; 5817 5818 u8 reserved_at_40[0x40]; 5819 }; 5820 5821 struct mlx5_ifc_nop_in_bits { 5822 u8 opcode[0x10]; 5823 u8 reserved_at_10[0x10]; 5824 5825 u8 reserved_at_20[0x10]; 5826 u8 op_mod[0x10]; 5827 5828 u8 reserved_at_40[0x40]; 5829 }; 5830 5831 struct mlx5_ifc_modify_vport_state_out_bits { 5832 u8 status[0x8]; 5833 u8 reserved_at_8[0x18]; 5834 5835 u8 syndrome[0x20]; 5836 5837 u8 reserved_at_40[0x40]; 5838 }; 5839 5840 struct mlx5_ifc_modify_vport_state_in_bits { 5841 u8 opcode[0x10]; 5842 u8 reserved_at_10[0x10]; 5843 5844 u8 reserved_at_20[0x10]; 5845 u8 op_mod[0x10]; 5846 5847 u8 other_vport[0x1]; 5848 u8 reserved_at_41[0xf]; 5849 u8 vport_number[0x10]; 5850 5851 u8 reserved_at_60[0x18]; 5852 u8 admin_state[0x4]; 5853 u8 reserved_at_7c[0x4]; 5854 }; 5855 5856 struct mlx5_ifc_modify_tis_out_bits { 5857 u8 status[0x8]; 5858 u8 reserved_at_8[0x18]; 5859 5860 u8 syndrome[0x20]; 5861 5862 u8 reserved_at_40[0x40]; 5863 }; 5864 5865 struct mlx5_ifc_modify_tis_bitmask_bits { 5866 u8 reserved_at_0[0x20]; 5867 5868 u8 reserved_at_20[0x1d]; 5869 u8 lag_tx_port_affinity[0x1]; 5870 u8 strict_lag_tx_port_affinity[0x1]; 5871 u8 prio[0x1]; 5872 }; 5873 5874 struct mlx5_ifc_modify_tis_in_bits { 5875 u8 opcode[0x10]; 5876 u8 uid[0x10]; 5877 5878 u8 reserved_at_20[0x10]; 5879 u8 op_mod[0x10]; 5880 5881 u8 reserved_at_40[0x8]; 5882 u8 tisn[0x18]; 5883 5884 u8 reserved_at_60[0x20]; 5885 5886 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5887 5888 u8 reserved_at_c0[0x40]; 5889 5890 struct mlx5_ifc_tisc_bits ctx; 5891 }; 5892 5893 struct mlx5_ifc_modify_tir_bitmask_bits { 5894 u8 reserved_at_0[0x20]; 5895 5896 u8 reserved_at_20[0x1b]; 5897 u8 self_lb_en[0x1]; 5898 u8 reserved_at_3c[0x1]; 5899 u8 hash[0x1]; 5900 u8 reserved_at_3e[0x1]; 5901 u8 lro[0x1]; 5902 }; 5903 5904 struct mlx5_ifc_modify_tir_out_bits { 5905 u8 status[0x8]; 5906 u8 reserved_at_8[0x18]; 5907 5908 u8 syndrome[0x20]; 5909 5910 u8 reserved_at_40[0x40]; 5911 }; 5912 5913 struct mlx5_ifc_modify_tir_in_bits { 5914 u8 opcode[0x10]; 5915 u8 uid[0x10]; 5916 5917 u8 reserved_at_20[0x10]; 5918 u8 op_mod[0x10]; 5919 5920 u8 reserved_at_40[0x8]; 5921 u8 tirn[0x18]; 5922 5923 u8 reserved_at_60[0x20]; 5924 5925 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5926 5927 u8 reserved_at_c0[0x40]; 5928 5929 struct mlx5_ifc_tirc_bits ctx; 5930 }; 5931 5932 struct mlx5_ifc_modify_sq_out_bits { 5933 u8 status[0x8]; 5934 u8 reserved_at_8[0x18]; 5935 5936 u8 syndrome[0x20]; 5937 5938 u8 reserved_at_40[0x40]; 5939 }; 5940 5941 struct mlx5_ifc_modify_sq_in_bits { 5942 u8 opcode[0x10]; 5943 u8 uid[0x10]; 5944 5945 u8 reserved_at_20[0x10]; 5946 u8 op_mod[0x10]; 5947 5948 u8 sq_state[0x4]; 5949 u8 reserved_at_44[0x4]; 5950 u8 sqn[0x18]; 5951 5952 u8 reserved_at_60[0x20]; 5953 5954 u8 modify_bitmask[0x40]; 5955 5956 u8 reserved_at_c0[0x40]; 5957 5958 struct mlx5_ifc_sqc_bits ctx; 5959 }; 5960 5961 struct mlx5_ifc_modify_scheduling_element_out_bits { 5962 u8 status[0x8]; 5963 u8 reserved_at_8[0x18]; 5964 5965 u8 syndrome[0x20]; 5966 5967 u8 reserved_at_40[0x1c0]; 5968 }; 5969 5970 enum { 5971 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5972 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5973 }; 5974 5975 struct mlx5_ifc_modify_scheduling_element_in_bits { 5976 u8 opcode[0x10]; 5977 u8 reserved_at_10[0x10]; 5978 5979 u8 reserved_at_20[0x10]; 5980 u8 op_mod[0x10]; 5981 5982 u8 scheduling_hierarchy[0x8]; 5983 u8 reserved_at_48[0x18]; 5984 5985 u8 scheduling_element_id[0x20]; 5986 5987 u8 reserved_at_80[0x20]; 5988 5989 u8 modify_bitmask[0x20]; 5990 5991 u8 reserved_at_c0[0x40]; 5992 5993 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5994 5995 u8 reserved_at_300[0x100]; 5996 }; 5997 5998 struct mlx5_ifc_modify_rqt_out_bits { 5999 u8 status[0x8]; 6000 u8 reserved_at_8[0x18]; 6001 6002 u8 syndrome[0x20]; 6003 6004 u8 reserved_at_40[0x40]; 6005 }; 6006 6007 struct mlx5_ifc_rqt_bitmask_bits { 6008 u8 reserved_at_0[0x20]; 6009 6010 u8 reserved_at_20[0x1f]; 6011 u8 rqn_list[0x1]; 6012 }; 6013 6014 struct mlx5_ifc_modify_rqt_in_bits { 6015 u8 opcode[0x10]; 6016 u8 uid[0x10]; 6017 6018 u8 reserved_at_20[0x10]; 6019 u8 op_mod[0x10]; 6020 6021 u8 reserved_at_40[0x8]; 6022 u8 rqtn[0x18]; 6023 6024 u8 reserved_at_60[0x20]; 6025 6026 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6027 6028 u8 reserved_at_c0[0x40]; 6029 6030 struct mlx5_ifc_rqtc_bits ctx; 6031 }; 6032 6033 struct mlx5_ifc_modify_rq_out_bits { 6034 u8 status[0x8]; 6035 u8 reserved_at_8[0x18]; 6036 6037 u8 syndrome[0x20]; 6038 6039 u8 reserved_at_40[0x40]; 6040 }; 6041 6042 enum { 6043 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6044 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6045 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6046 }; 6047 6048 struct mlx5_ifc_modify_rq_in_bits { 6049 u8 opcode[0x10]; 6050 u8 uid[0x10]; 6051 6052 u8 reserved_at_20[0x10]; 6053 u8 op_mod[0x10]; 6054 6055 u8 rq_state[0x4]; 6056 u8 reserved_at_44[0x4]; 6057 u8 rqn[0x18]; 6058 6059 u8 reserved_at_60[0x20]; 6060 6061 u8 modify_bitmask[0x40]; 6062 6063 u8 reserved_at_c0[0x40]; 6064 6065 struct mlx5_ifc_rqc_bits ctx; 6066 }; 6067 6068 struct mlx5_ifc_modify_rmp_out_bits { 6069 u8 status[0x8]; 6070 u8 reserved_at_8[0x18]; 6071 6072 u8 syndrome[0x20]; 6073 6074 u8 reserved_at_40[0x40]; 6075 }; 6076 6077 struct mlx5_ifc_rmp_bitmask_bits { 6078 u8 reserved_at_0[0x20]; 6079 6080 u8 reserved_at_20[0x1f]; 6081 u8 lwm[0x1]; 6082 }; 6083 6084 struct mlx5_ifc_modify_rmp_in_bits { 6085 u8 opcode[0x10]; 6086 u8 uid[0x10]; 6087 6088 u8 reserved_at_20[0x10]; 6089 u8 op_mod[0x10]; 6090 6091 u8 rmp_state[0x4]; 6092 u8 reserved_at_44[0x4]; 6093 u8 rmpn[0x18]; 6094 6095 u8 reserved_at_60[0x20]; 6096 6097 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6098 6099 u8 reserved_at_c0[0x40]; 6100 6101 struct mlx5_ifc_rmpc_bits ctx; 6102 }; 6103 6104 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6105 u8 status[0x8]; 6106 u8 reserved_at_8[0x18]; 6107 6108 u8 syndrome[0x20]; 6109 6110 u8 reserved_at_40[0x40]; 6111 }; 6112 6113 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6114 u8 reserved_at_0[0x12]; 6115 u8 affiliation[0x1]; 6116 u8 reserved_at_13[0x1]; 6117 u8 disable_uc_local_lb[0x1]; 6118 u8 disable_mc_local_lb[0x1]; 6119 u8 node_guid[0x1]; 6120 u8 port_guid[0x1]; 6121 u8 min_inline[0x1]; 6122 u8 mtu[0x1]; 6123 u8 change_event[0x1]; 6124 u8 promisc[0x1]; 6125 u8 permanent_address[0x1]; 6126 u8 addresses_list[0x1]; 6127 u8 roce_en[0x1]; 6128 u8 reserved_at_1f[0x1]; 6129 }; 6130 6131 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6132 u8 opcode[0x10]; 6133 u8 reserved_at_10[0x10]; 6134 6135 u8 reserved_at_20[0x10]; 6136 u8 op_mod[0x10]; 6137 6138 u8 other_vport[0x1]; 6139 u8 reserved_at_41[0xf]; 6140 u8 vport_number[0x10]; 6141 6142 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6143 6144 u8 reserved_at_80[0x780]; 6145 6146 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6147 }; 6148 6149 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6150 u8 status[0x8]; 6151 u8 reserved_at_8[0x18]; 6152 6153 u8 syndrome[0x20]; 6154 6155 u8 reserved_at_40[0x40]; 6156 }; 6157 6158 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6159 u8 opcode[0x10]; 6160 u8 reserved_at_10[0x10]; 6161 6162 u8 reserved_at_20[0x10]; 6163 u8 op_mod[0x10]; 6164 6165 u8 other_vport[0x1]; 6166 u8 reserved_at_41[0xb]; 6167 u8 port_num[0x4]; 6168 u8 vport_number[0x10]; 6169 6170 u8 reserved_at_60[0x20]; 6171 6172 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6173 }; 6174 6175 struct mlx5_ifc_modify_cq_out_bits { 6176 u8 status[0x8]; 6177 u8 reserved_at_8[0x18]; 6178 6179 u8 syndrome[0x20]; 6180 6181 u8 reserved_at_40[0x40]; 6182 }; 6183 6184 enum { 6185 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6186 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6187 }; 6188 6189 struct mlx5_ifc_modify_cq_in_bits { 6190 u8 opcode[0x10]; 6191 u8 uid[0x10]; 6192 6193 u8 reserved_at_20[0x10]; 6194 u8 op_mod[0x10]; 6195 6196 u8 reserved_at_40[0x8]; 6197 u8 cqn[0x18]; 6198 6199 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6200 6201 struct mlx5_ifc_cqc_bits cq_context; 6202 6203 u8 reserved_at_280[0x60]; 6204 6205 u8 cq_umem_valid[0x1]; 6206 u8 reserved_at_2e1[0x1f]; 6207 6208 u8 reserved_at_300[0x580]; 6209 6210 u8 pas[0][0x40]; 6211 }; 6212 6213 struct mlx5_ifc_modify_cong_status_out_bits { 6214 u8 status[0x8]; 6215 u8 reserved_at_8[0x18]; 6216 6217 u8 syndrome[0x20]; 6218 6219 u8 reserved_at_40[0x40]; 6220 }; 6221 6222 struct mlx5_ifc_modify_cong_status_in_bits { 6223 u8 opcode[0x10]; 6224 u8 reserved_at_10[0x10]; 6225 6226 u8 reserved_at_20[0x10]; 6227 u8 op_mod[0x10]; 6228 6229 u8 reserved_at_40[0x18]; 6230 u8 priority[0x4]; 6231 u8 cong_protocol[0x4]; 6232 6233 u8 enable[0x1]; 6234 u8 tag_enable[0x1]; 6235 u8 reserved_at_62[0x1e]; 6236 }; 6237 6238 struct mlx5_ifc_modify_cong_params_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 }; 6246 6247 struct mlx5_ifc_modify_cong_params_in_bits { 6248 u8 opcode[0x10]; 6249 u8 reserved_at_10[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 reserved_at_40[0x1c]; 6255 u8 cong_protocol[0x4]; 6256 6257 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6258 6259 u8 reserved_at_80[0x80]; 6260 6261 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6262 }; 6263 6264 struct mlx5_ifc_manage_pages_out_bits { 6265 u8 status[0x8]; 6266 u8 reserved_at_8[0x18]; 6267 6268 u8 syndrome[0x20]; 6269 6270 u8 output_num_entries[0x20]; 6271 6272 u8 reserved_at_60[0x20]; 6273 6274 u8 pas[0][0x40]; 6275 }; 6276 6277 enum { 6278 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6279 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6280 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6281 }; 6282 6283 struct mlx5_ifc_manage_pages_in_bits { 6284 u8 opcode[0x10]; 6285 u8 reserved_at_10[0x10]; 6286 6287 u8 reserved_at_20[0x10]; 6288 u8 op_mod[0x10]; 6289 6290 u8 embedded_cpu_function[0x1]; 6291 u8 reserved_at_41[0xf]; 6292 u8 function_id[0x10]; 6293 6294 u8 input_num_entries[0x20]; 6295 6296 u8 pas[0][0x40]; 6297 }; 6298 6299 struct mlx5_ifc_mad_ifc_out_bits { 6300 u8 status[0x8]; 6301 u8 reserved_at_8[0x18]; 6302 6303 u8 syndrome[0x20]; 6304 6305 u8 reserved_at_40[0x40]; 6306 6307 u8 response_mad_packet[256][0x8]; 6308 }; 6309 6310 struct mlx5_ifc_mad_ifc_in_bits { 6311 u8 opcode[0x10]; 6312 u8 reserved_at_10[0x10]; 6313 6314 u8 reserved_at_20[0x10]; 6315 u8 op_mod[0x10]; 6316 6317 u8 remote_lid[0x10]; 6318 u8 reserved_at_50[0x8]; 6319 u8 port[0x8]; 6320 6321 u8 reserved_at_60[0x20]; 6322 6323 u8 mad[256][0x8]; 6324 }; 6325 6326 struct mlx5_ifc_init_hca_out_bits { 6327 u8 status[0x8]; 6328 u8 reserved_at_8[0x18]; 6329 6330 u8 syndrome[0x20]; 6331 6332 u8 reserved_at_40[0x40]; 6333 }; 6334 6335 struct mlx5_ifc_init_hca_in_bits { 6336 u8 opcode[0x10]; 6337 u8 reserved_at_10[0x10]; 6338 6339 u8 reserved_at_20[0x10]; 6340 u8 op_mod[0x10]; 6341 6342 u8 reserved_at_40[0x40]; 6343 u8 sw_owner_id[4][0x20]; 6344 }; 6345 6346 struct mlx5_ifc_init2rtr_qp_out_bits { 6347 u8 status[0x8]; 6348 u8 reserved_at_8[0x18]; 6349 6350 u8 syndrome[0x20]; 6351 6352 u8 reserved_at_40[0x40]; 6353 }; 6354 6355 struct mlx5_ifc_init2rtr_qp_in_bits { 6356 u8 opcode[0x10]; 6357 u8 uid[0x10]; 6358 6359 u8 reserved_at_20[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 reserved_at_40[0x8]; 6363 u8 qpn[0x18]; 6364 6365 u8 reserved_at_60[0x20]; 6366 6367 u8 opt_param_mask[0x20]; 6368 6369 u8 reserved_at_a0[0x20]; 6370 6371 struct mlx5_ifc_qpc_bits qpc; 6372 6373 u8 reserved_at_800[0x80]; 6374 }; 6375 6376 struct mlx5_ifc_init2init_qp_out_bits { 6377 u8 status[0x8]; 6378 u8 reserved_at_8[0x18]; 6379 6380 u8 syndrome[0x20]; 6381 6382 u8 reserved_at_40[0x40]; 6383 }; 6384 6385 struct mlx5_ifc_init2init_qp_in_bits { 6386 u8 opcode[0x10]; 6387 u8 uid[0x10]; 6388 6389 u8 reserved_at_20[0x10]; 6390 u8 op_mod[0x10]; 6391 6392 u8 reserved_at_40[0x8]; 6393 u8 qpn[0x18]; 6394 6395 u8 reserved_at_60[0x20]; 6396 6397 u8 opt_param_mask[0x20]; 6398 6399 u8 reserved_at_a0[0x20]; 6400 6401 struct mlx5_ifc_qpc_bits qpc; 6402 6403 u8 reserved_at_800[0x80]; 6404 }; 6405 6406 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6407 u8 status[0x8]; 6408 u8 reserved_at_8[0x18]; 6409 6410 u8 syndrome[0x20]; 6411 6412 u8 reserved_at_40[0x40]; 6413 6414 u8 packet_headers_log[128][0x8]; 6415 6416 u8 packet_syndrome[64][0x8]; 6417 }; 6418 6419 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6420 u8 opcode[0x10]; 6421 u8 reserved_at_10[0x10]; 6422 6423 u8 reserved_at_20[0x10]; 6424 u8 op_mod[0x10]; 6425 6426 u8 reserved_at_40[0x40]; 6427 }; 6428 6429 struct mlx5_ifc_gen_eqe_in_bits { 6430 u8 opcode[0x10]; 6431 u8 reserved_at_10[0x10]; 6432 6433 u8 reserved_at_20[0x10]; 6434 u8 op_mod[0x10]; 6435 6436 u8 reserved_at_40[0x18]; 6437 u8 eq_number[0x8]; 6438 6439 u8 reserved_at_60[0x20]; 6440 6441 u8 eqe[64][0x8]; 6442 }; 6443 6444 struct mlx5_ifc_gen_eq_out_bits { 6445 u8 status[0x8]; 6446 u8 reserved_at_8[0x18]; 6447 6448 u8 syndrome[0x20]; 6449 6450 u8 reserved_at_40[0x40]; 6451 }; 6452 6453 struct mlx5_ifc_enable_hca_out_bits { 6454 u8 status[0x8]; 6455 u8 reserved_at_8[0x18]; 6456 6457 u8 syndrome[0x20]; 6458 6459 u8 reserved_at_40[0x20]; 6460 }; 6461 6462 struct mlx5_ifc_enable_hca_in_bits { 6463 u8 opcode[0x10]; 6464 u8 reserved_at_10[0x10]; 6465 6466 u8 reserved_at_20[0x10]; 6467 u8 op_mod[0x10]; 6468 6469 u8 embedded_cpu_function[0x1]; 6470 u8 reserved_at_41[0xf]; 6471 u8 function_id[0x10]; 6472 6473 u8 reserved_at_60[0x20]; 6474 }; 6475 6476 struct mlx5_ifc_drain_dct_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_at_8[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_at_40[0x40]; 6483 }; 6484 6485 struct mlx5_ifc_drain_dct_in_bits { 6486 u8 opcode[0x10]; 6487 u8 uid[0x10]; 6488 6489 u8 reserved_at_20[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 reserved_at_40[0x8]; 6493 u8 dctn[0x18]; 6494 6495 u8 reserved_at_60[0x20]; 6496 }; 6497 6498 struct mlx5_ifc_disable_hca_out_bits { 6499 u8 status[0x8]; 6500 u8 reserved_at_8[0x18]; 6501 6502 u8 syndrome[0x20]; 6503 6504 u8 reserved_at_40[0x20]; 6505 }; 6506 6507 struct mlx5_ifc_disable_hca_in_bits { 6508 u8 opcode[0x10]; 6509 u8 reserved_at_10[0x10]; 6510 6511 u8 reserved_at_20[0x10]; 6512 u8 op_mod[0x10]; 6513 6514 u8 embedded_cpu_function[0x1]; 6515 u8 reserved_at_41[0xf]; 6516 u8 function_id[0x10]; 6517 6518 u8 reserved_at_60[0x20]; 6519 }; 6520 6521 struct mlx5_ifc_detach_from_mcg_out_bits { 6522 u8 status[0x8]; 6523 u8 reserved_at_8[0x18]; 6524 6525 u8 syndrome[0x20]; 6526 6527 u8 reserved_at_40[0x40]; 6528 }; 6529 6530 struct mlx5_ifc_detach_from_mcg_in_bits { 6531 u8 opcode[0x10]; 6532 u8 uid[0x10]; 6533 6534 u8 reserved_at_20[0x10]; 6535 u8 op_mod[0x10]; 6536 6537 u8 reserved_at_40[0x8]; 6538 u8 qpn[0x18]; 6539 6540 u8 reserved_at_60[0x20]; 6541 6542 u8 multicast_gid[16][0x8]; 6543 }; 6544 6545 struct mlx5_ifc_destroy_xrq_out_bits { 6546 u8 status[0x8]; 6547 u8 reserved_at_8[0x18]; 6548 6549 u8 syndrome[0x20]; 6550 6551 u8 reserved_at_40[0x40]; 6552 }; 6553 6554 struct mlx5_ifc_destroy_xrq_in_bits { 6555 u8 opcode[0x10]; 6556 u8 uid[0x10]; 6557 6558 u8 reserved_at_20[0x10]; 6559 u8 op_mod[0x10]; 6560 6561 u8 reserved_at_40[0x8]; 6562 u8 xrqn[0x18]; 6563 6564 u8 reserved_at_60[0x20]; 6565 }; 6566 6567 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6568 u8 status[0x8]; 6569 u8 reserved_at_8[0x18]; 6570 6571 u8 syndrome[0x20]; 6572 6573 u8 reserved_at_40[0x40]; 6574 }; 6575 6576 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6577 u8 opcode[0x10]; 6578 u8 uid[0x10]; 6579 6580 u8 reserved_at_20[0x10]; 6581 u8 op_mod[0x10]; 6582 6583 u8 reserved_at_40[0x8]; 6584 u8 xrc_srqn[0x18]; 6585 6586 u8 reserved_at_60[0x20]; 6587 }; 6588 6589 struct mlx5_ifc_destroy_tis_out_bits { 6590 u8 status[0x8]; 6591 u8 reserved_at_8[0x18]; 6592 6593 u8 syndrome[0x20]; 6594 6595 u8 reserved_at_40[0x40]; 6596 }; 6597 6598 struct mlx5_ifc_destroy_tis_in_bits { 6599 u8 opcode[0x10]; 6600 u8 uid[0x10]; 6601 6602 u8 reserved_at_20[0x10]; 6603 u8 op_mod[0x10]; 6604 6605 u8 reserved_at_40[0x8]; 6606 u8 tisn[0x18]; 6607 6608 u8 reserved_at_60[0x20]; 6609 }; 6610 6611 struct mlx5_ifc_destroy_tir_out_bits { 6612 u8 status[0x8]; 6613 u8 reserved_at_8[0x18]; 6614 6615 u8 syndrome[0x20]; 6616 6617 u8 reserved_at_40[0x40]; 6618 }; 6619 6620 struct mlx5_ifc_destroy_tir_in_bits { 6621 u8 opcode[0x10]; 6622 u8 uid[0x10]; 6623 6624 u8 reserved_at_20[0x10]; 6625 u8 op_mod[0x10]; 6626 6627 u8 reserved_at_40[0x8]; 6628 u8 tirn[0x18]; 6629 6630 u8 reserved_at_60[0x20]; 6631 }; 6632 6633 struct mlx5_ifc_destroy_srq_out_bits { 6634 u8 status[0x8]; 6635 u8 reserved_at_8[0x18]; 6636 6637 u8 syndrome[0x20]; 6638 6639 u8 reserved_at_40[0x40]; 6640 }; 6641 6642 struct mlx5_ifc_destroy_srq_in_bits { 6643 u8 opcode[0x10]; 6644 u8 uid[0x10]; 6645 6646 u8 reserved_at_20[0x10]; 6647 u8 op_mod[0x10]; 6648 6649 u8 reserved_at_40[0x8]; 6650 u8 srqn[0x18]; 6651 6652 u8 reserved_at_60[0x20]; 6653 }; 6654 6655 struct mlx5_ifc_destroy_sq_out_bits { 6656 u8 status[0x8]; 6657 u8 reserved_at_8[0x18]; 6658 6659 u8 syndrome[0x20]; 6660 6661 u8 reserved_at_40[0x40]; 6662 }; 6663 6664 struct mlx5_ifc_destroy_sq_in_bits { 6665 u8 opcode[0x10]; 6666 u8 uid[0x10]; 6667 6668 u8 reserved_at_20[0x10]; 6669 u8 op_mod[0x10]; 6670 6671 u8 reserved_at_40[0x8]; 6672 u8 sqn[0x18]; 6673 6674 u8 reserved_at_60[0x20]; 6675 }; 6676 6677 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6678 u8 status[0x8]; 6679 u8 reserved_at_8[0x18]; 6680 6681 u8 syndrome[0x20]; 6682 6683 u8 reserved_at_40[0x1c0]; 6684 }; 6685 6686 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6687 u8 opcode[0x10]; 6688 u8 reserved_at_10[0x10]; 6689 6690 u8 reserved_at_20[0x10]; 6691 u8 op_mod[0x10]; 6692 6693 u8 scheduling_hierarchy[0x8]; 6694 u8 reserved_at_48[0x18]; 6695 6696 u8 scheduling_element_id[0x20]; 6697 6698 u8 reserved_at_80[0x180]; 6699 }; 6700 6701 struct mlx5_ifc_destroy_rqt_out_bits { 6702 u8 status[0x8]; 6703 u8 reserved_at_8[0x18]; 6704 6705 u8 syndrome[0x20]; 6706 6707 u8 reserved_at_40[0x40]; 6708 }; 6709 6710 struct mlx5_ifc_destroy_rqt_in_bits { 6711 u8 opcode[0x10]; 6712 u8 uid[0x10]; 6713 6714 u8 reserved_at_20[0x10]; 6715 u8 op_mod[0x10]; 6716 6717 u8 reserved_at_40[0x8]; 6718 u8 rqtn[0x18]; 6719 6720 u8 reserved_at_60[0x20]; 6721 }; 6722 6723 struct mlx5_ifc_destroy_rq_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_at_8[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 reserved_at_40[0x40]; 6730 }; 6731 6732 struct mlx5_ifc_destroy_rq_in_bits { 6733 u8 opcode[0x10]; 6734 u8 uid[0x10]; 6735 6736 u8 reserved_at_20[0x10]; 6737 u8 op_mod[0x10]; 6738 6739 u8 reserved_at_40[0x8]; 6740 u8 rqn[0x18]; 6741 6742 u8 reserved_at_60[0x20]; 6743 }; 6744 6745 struct mlx5_ifc_set_delay_drop_params_in_bits { 6746 u8 opcode[0x10]; 6747 u8 reserved_at_10[0x10]; 6748 6749 u8 reserved_at_20[0x10]; 6750 u8 op_mod[0x10]; 6751 6752 u8 reserved_at_40[0x20]; 6753 6754 u8 reserved_at_60[0x10]; 6755 u8 delay_drop_timeout[0x10]; 6756 }; 6757 6758 struct mlx5_ifc_set_delay_drop_params_out_bits { 6759 u8 status[0x8]; 6760 u8 reserved_at_8[0x18]; 6761 6762 u8 syndrome[0x20]; 6763 6764 u8 reserved_at_40[0x40]; 6765 }; 6766 6767 struct mlx5_ifc_destroy_rmp_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_at_8[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 reserved_at_40[0x40]; 6774 }; 6775 6776 struct mlx5_ifc_destroy_rmp_in_bits { 6777 u8 opcode[0x10]; 6778 u8 uid[0x10]; 6779 6780 u8 reserved_at_20[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 reserved_at_40[0x8]; 6784 u8 rmpn[0x18]; 6785 6786 u8 reserved_at_60[0x20]; 6787 }; 6788 6789 struct mlx5_ifc_destroy_qp_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_at_8[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 reserved_at_40[0x40]; 6796 }; 6797 6798 struct mlx5_ifc_destroy_qp_in_bits { 6799 u8 opcode[0x10]; 6800 u8 uid[0x10]; 6801 6802 u8 reserved_at_20[0x10]; 6803 u8 op_mod[0x10]; 6804 6805 u8 reserved_at_40[0x8]; 6806 u8 qpn[0x18]; 6807 6808 u8 reserved_at_60[0x20]; 6809 }; 6810 6811 struct mlx5_ifc_destroy_psv_out_bits { 6812 u8 status[0x8]; 6813 u8 reserved_at_8[0x18]; 6814 6815 u8 syndrome[0x20]; 6816 6817 u8 reserved_at_40[0x40]; 6818 }; 6819 6820 struct mlx5_ifc_destroy_psv_in_bits { 6821 u8 opcode[0x10]; 6822 u8 reserved_at_10[0x10]; 6823 6824 u8 reserved_at_20[0x10]; 6825 u8 op_mod[0x10]; 6826 6827 u8 reserved_at_40[0x8]; 6828 u8 psvn[0x18]; 6829 6830 u8 reserved_at_60[0x20]; 6831 }; 6832 6833 struct mlx5_ifc_destroy_mkey_out_bits { 6834 u8 status[0x8]; 6835 u8 reserved_at_8[0x18]; 6836 6837 u8 syndrome[0x20]; 6838 6839 u8 reserved_at_40[0x40]; 6840 }; 6841 6842 struct mlx5_ifc_destroy_mkey_in_bits { 6843 u8 opcode[0x10]; 6844 u8 reserved_at_10[0x10]; 6845 6846 u8 reserved_at_20[0x10]; 6847 u8 op_mod[0x10]; 6848 6849 u8 reserved_at_40[0x8]; 6850 u8 mkey_index[0x18]; 6851 6852 u8 reserved_at_60[0x20]; 6853 }; 6854 6855 struct mlx5_ifc_destroy_flow_table_out_bits { 6856 u8 status[0x8]; 6857 u8 reserved_at_8[0x18]; 6858 6859 u8 syndrome[0x20]; 6860 6861 u8 reserved_at_40[0x40]; 6862 }; 6863 6864 struct mlx5_ifc_destroy_flow_table_in_bits { 6865 u8 opcode[0x10]; 6866 u8 reserved_at_10[0x10]; 6867 6868 u8 reserved_at_20[0x10]; 6869 u8 op_mod[0x10]; 6870 6871 u8 other_vport[0x1]; 6872 u8 reserved_at_41[0xf]; 6873 u8 vport_number[0x10]; 6874 6875 u8 reserved_at_60[0x20]; 6876 6877 u8 table_type[0x8]; 6878 u8 reserved_at_88[0x18]; 6879 6880 u8 reserved_at_a0[0x8]; 6881 u8 table_id[0x18]; 6882 6883 u8 reserved_at_c0[0x140]; 6884 }; 6885 6886 struct mlx5_ifc_destroy_flow_group_out_bits { 6887 u8 status[0x8]; 6888 u8 reserved_at_8[0x18]; 6889 6890 u8 syndrome[0x20]; 6891 6892 u8 reserved_at_40[0x40]; 6893 }; 6894 6895 struct mlx5_ifc_destroy_flow_group_in_bits { 6896 u8 opcode[0x10]; 6897 u8 reserved_at_10[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 other_vport[0x1]; 6903 u8 reserved_at_41[0xf]; 6904 u8 vport_number[0x10]; 6905 6906 u8 reserved_at_60[0x20]; 6907 6908 u8 table_type[0x8]; 6909 u8 reserved_at_88[0x18]; 6910 6911 u8 reserved_at_a0[0x8]; 6912 u8 table_id[0x18]; 6913 6914 u8 group_id[0x20]; 6915 6916 u8 reserved_at_e0[0x120]; 6917 }; 6918 6919 struct mlx5_ifc_destroy_eq_out_bits { 6920 u8 status[0x8]; 6921 u8 reserved_at_8[0x18]; 6922 6923 u8 syndrome[0x20]; 6924 6925 u8 reserved_at_40[0x40]; 6926 }; 6927 6928 struct mlx5_ifc_destroy_eq_in_bits { 6929 u8 opcode[0x10]; 6930 u8 reserved_at_10[0x10]; 6931 6932 u8 reserved_at_20[0x10]; 6933 u8 op_mod[0x10]; 6934 6935 u8 reserved_at_40[0x18]; 6936 u8 eq_number[0x8]; 6937 6938 u8 reserved_at_60[0x20]; 6939 }; 6940 6941 struct mlx5_ifc_destroy_dct_out_bits { 6942 u8 status[0x8]; 6943 u8 reserved_at_8[0x18]; 6944 6945 u8 syndrome[0x20]; 6946 6947 u8 reserved_at_40[0x40]; 6948 }; 6949 6950 struct mlx5_ifc_destroy_dct_in_bits { 6951 u8 opcode[0x10]; 6952 u8 uid[0x10]; 6953 6954 u8 reserved_at_20[0x10]; 6955 u8 op_mod[0x10]; 6956 6957 u8 reserved_at_40[0x8]; 6958 u8 dctn[0x18]; 6959 6960 u8 reserved_at_60[0x20]; 6961 }; 6962 6963 struct mlx5_ifc_destroy_cq_out_bits { 6964 u8 status[0x8]; 6965 u8 reserved_at_8[0x18]; 6966 6967 u8 syndrome[0x20]; 6968 6969 u8 reserved_at_40[0x40]; 6970 }; 6971 6972 struct mlx5_ifc_destroy_cq_in_bits { 6973 u8 opcode[0x10]; 6974 u8 uid[0x10]; 6975 6976 u8 reserved_at_20[0x10]; 6977 u8 op_mod[0x10]; 6978 6979 u8 reserved_at_40[0x8]; 6980 u8 cqn[0x18]; 6981 6982 u8 reserved_at_60[0x20]; 6983 }; 6984 6985 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6986 u8 status[0x8]; 6987 u8 reserved_at_8[0x18]; 6988 6989 u8 syndrome[0x20]; 6990 6991 u8 reserved_at_40[0x40]; 6992 }; 6993 6994 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6995 u8 opcode[0x10]; 6996 u8 reserved_at_10[0x10]; 6997 6998 u8 reserved_at_20[0x10]; 6999 u8 op_mod[0x10]; 7000 7001 u8 reserved_at_40[0x20]; 7002 7003 u8 reserved_at_60[0x10]; 7004 u8 vxlan_udp_port[0x10]; 7005 }; 7006 7007 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7008 u8 status[0x8]; 7009 u8 reserved_at_8[0x18]; 7010 7011 u8 syndrome[0x20]; 7012 7013 u8 reserved_at_40[0x40]; 7014 }; 7015 7016 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7017 u8 opcode[0x10]; 7018 u8 reserved_at_10[0x10]; 7019 7020 u8 reserved_at_20[0x10]; 7021 u8 op_mod[0x10]; 7022 7023 u8 reserved_at_40[0x60]; 7024 7025 u8 reserved_at_a0[0x8]; 7026 u8 table_index[0x18]; 7027 7028 u8 reserved_at_c0[0x140]; 7029 }; 7030 7031 struct mlx5_ifc_delete_fte_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x40]; 7038 }; 7039 7040 struct mlx5_ifc_delete_fte_in_bits { 7041 u8 opcode[0x10]; 7042 u8 reserved_at_10[0x10]; 7043 7044 u8 reserved_at_20[0x10]; 7045 u8 op_mod[0x10]; 7046 7047 u8 other_vport[0x1]; 7048 u8 reserved_at_41[0xf]; 7049 u8 vport_number[0x10]; 7050 7051 u8 reserved_at_60[0x20]; 7052 7053 u8 table_type[0x8]; 7054 u8 reserved_at_88[0x18]; 7055 7056 u8 reserved_at_a0[0x8]; 7057 u8 table_id[0x18]; 7058 7059 u8 reserved_at_c0[0x40]; 7060 7061 u8 flow_index[0x20]; 7062 7063 u8 reserved_at_120[0xe0]; 7064 }; 7065 7066 struct mlx5_ifc_dealloc_xrcd_out_bits { 7067 u8 status[0x8]; 7068 u8 reserved_at_8[0x18]; 7069 7070 u8 syndrome[0x20]; 7071 7072 u8 reserved_at_40[0x40]; 7073 }; 7074 7075 struct mlx5_ifc_dealloc_xrcd_in_bits { 7076 u8 opcode[0x10]; 7077 u8 uid[0x10]; 7078 7079 u8 reserved_at_20[0x10]; 7080 u8 op_mod[0x10]; 7081 7082 u8 reserved_at_40[0x8]; 7083 u8 xrcd[0x18]; 7084 7085 u8 reserved_at_60[0x20]; 7086 }; 7087 7088 struct mlx5_ifc_dealloc_uar_out_bits { 7089 u8 status[0x8]; 7090 u8 reserved_at_8[0x18]; 7091 7092 u8 syndrome[0x20]; 7093 7094 u8 reserved_at_40[0x40]; 7095 }; 7096 7097 struct mlx5_ifc_dealloc_uar_in_bits { 7098 u8 opcode[0x10]; 7099 u8 reserved_at_10[0x10]; 7100 7101 u8 reserved_at_20[0x10]; 7102 u8 op_mod[0x10]; 7103 7104 u8 reserved_at_40[0x8]; 7105 u8 uar[0x18]; 7106 7107 u8 reserved_at_60[0x20]; 7108 }; 7109 7110 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7111 u8 status[0x8]; 7112 u8 reserved_at_8[0x18]; 7113 7114 u8 syndrome[0x20]; 7115 7116 u8 reserved_at_40[0x40]; 7117 }; 7118 7119 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7120 u8 opcode[0x10]; 7121 u8 uid[0x10]; 7122 7123 u8 reserved_at_20[0x10]; 7124 u8 op_mod[0x10]; 7125 7126 u8 reserved_at_40[0x8]; 7127 u8 transport_domain[0x18]; 7128 7129 u8 reserved_at_60[0x20]; 7130 }; 7131 7132 struct mlx5_ifc_dealloc_q_counter_out_bits { 7133 u8 status[0x8]; 7134 u8 reserved_at_8[0x18]; 7135 7136 u8 syndrome[0x20]; 7137 7138 u8 reserved_at_40[0x40]; 7139 }; 7140 7141 struct mlx5_ifc_dealloc_q_counter_in_bits { 7142 u8 opcode[0x10]; 7143 u8 reserved_at_10[0x10]; 7144 7145 u8 reserved_at_20[0x10]; 7146 u8 op_mod[0x10]; 7147 7148 u8 reserved_at_40[0x18]; 7149 u8 counter_set_id[0x8]; 7150 7151 u8 reserved_at_60[0x20]; 7152 }; 7153 7154 struct mlx5_ifc_dealloc_pd_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_at_8[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_at_40[0x40]; 7161 }; 7162 7163 struct mlx5_ifc_dealloc_pd_in_bits { 7164 u8 opcode[0x10]; 7165 u8 uid[0x10]; 7166 7167 u8 reserved_at_20[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_at_40[0x8]; 7171 u8 pd[0x18]; 7172 7173 u8 reserved_at_60[0x20]; 7174 }; 7175 7176 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7177 u8 status[0x8]; 7178 u8 reserved_at_8[0x18]; 7179 7180 u8 syndrome[0x20]; 7181 7182 u8 reserved_at_40[0x40]; 7183 }; 7184 7185 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7186 u8 opcode[0x10]; 7187 u8 reserved_at_10[0x10]; 7188 7189 u8 reserved_at_20[0x10]; 7190 u8 op_mod[0x10]; 7191 7192 u8 flow_counter_id[0x20]; 7193 7194 u8 reserved_at_60[0x20]; 7195 }; 7196 7197 struct mlx5_ifc_create_xrq_out_bits { 7198 u8 status[0x8]; 7199 u8 reserved_at_8[0x18]; 7200 7201 u8 syndrome[0x20]; 7202 7203 u8 reserved_at_40[0x8]; 7204 u8 xrqn[0x18]; 7205 7206 u8 reserved_at_60[0x20]; 7207 }; 7208 7209 struct mlx5_ifc_create_xrq_in_bits { 7210 u8 opcode[0x10]; 7211 u8 uid[0x10]; 7212 7213 u8 reserved_at_20[0x10]; 7214 u8 op_mod[0x10]; 7215 7216 u8 reserved_at_40[0x40]; 7217 7218 struct mlx5_ifc_xrqc_bits xrq_context; 7219 }; 7220 7221 struct mlx5_ifc_create_xrc_srq_out_bits { 7222 u8 status[0x8]; 7223 u8 reserved_at_8[0x18]; 7224 7225 u8 syndrome[0x20]; 7226 7227 u8 reserved_at_40[0x8]; 7228 u8 xrc_srqn[0x18]; 7229 7230 u8 reserved_at_60[0x20]; 7231 }; 7232 7233 struct mlx5_ifc_create_xrc_srq_in_bits { 7234 u8 opcode[0x10]; 7235 u8 uid[0x10]; 7236 7237 u8 reserved_at_20[0x10]; 7238 u8 op_mod[0x10]; 7239 7240 u8 reserved_at_40[0x40]; 7241 7242 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7243 7244 u8 reserved_at_280[0x60]; 7245 7246 u8 xrc_srq_umem_valid[0x1]; 7247 u8 reserved_at_2e1[0x1f]; 7248 7249 u8 reserved_at_300[0x580]; 7250 7251 u8 pas[0][0x40]; 7252 }; 7253 7254 struct mlx5_ifc_create_tis_out_bits { 7255 u8 status[0x8]; 7256 u8 reserved_at_8[0x18]; 7257 7258 u8 syndrome[0x20]; 7259 7260 u8 reserved_at_40[0x8]; 7261 u8 tisn[0x18]; 7262 7263 u8 reserved_at_60[0x20]; 7264 }; 7265 7266 struct mlx5_ifc_create_tis_in_bits { 7267 u8 opcode[0x10]; 7268 u8 uid[0x10]; 7269 7270 u8 reserved_at_20[0x10]; 7271 u8 op_mod[0x10]; 7272 7273 u8 reserved_at_40[0xc0]; 7274 7275 struct mlx5_ifc_tisc_bits ctx; 7276 }; 7277 7278 struct mlx5_ifc_create_tir_out_bits { 7279 u8 status[0x8]; 7280 u8 icm_address_63_40[0x18]; 7281 7282 u8 syndrome[0x20]; 7283 7284 u8 icm_address_39_32[0x8]; 7285 u8 tirn[0x18]; 7286 7287 u8 icm_address_31_0[0x20]; 7288 }; 7289 7290 struct mlx5_ifc_create_tir_in_bits { 7291 u8 opcode[0x10]; 7292 u8 uid[0x10]; 7293 7294 u8 reserved_at_20[0x10]; 7295 u8 op_mod[0x10]; 7296 7297 u8 reserved_at_40[0xc0]; 7298 7299 struct mlx5_ifc_tirc_bits ctx; 7300 }; 7301 7302 struct mlx5_ifc_create_srq_out_bits { 7303 u8 status[0x8]; 7304 u8 reserved_at_8[0x18]; 7305 7306 u8 syndrome[0x20]; 7307 7308 u8 reserved_at_40[0x8]; 7309 u8 srqn[0x18]; 7310 7311 u8 reserved_at_60[0x20]; 7312 }; 7313 7314 struct mlx5_ifc_create_srq_in_bits { 7315 u8 opcode[0x10]; 7316 u8 uid[0x10]; 7317 7318 u8 reserved_at_20[0x10]; 7319 u8 op_mod[0x10]; 7320 7321 u8 reserved_at_40[0x40]; 7322 7323 struct mlx5_ifc_srqc_bits srq_context_entry; 7324 7325 u8 reserved_at_280[0x600]; 7326 7327 u8 pas[0][0x40]; 7328 }; 7329 7330 struct mlx5_ifc_create_sq_out_bits { 7331 u8 status[0x8]; 7332 u8 reserved_at_8[0x18]; 7333 7334 u8 syndrome[0x20]; 7335 7336 u8 reserved_at_40[0x8]; 7337 u8 sqn[0x18]; 7338 7339 u8 reserved_at_60[0x20]; 7340 }; 7341 7342 struct mlx5_ifc_create_sq_in_bits { 7343 u8 opcode[0x10]; 7344 u8 uid[0x10]; 7345 7346 u8 reserved_at_20[0x10]; 7347 u8 op_mod[0x10]; 7348 7349 u8 reserved_at_40[0xc0]; 7350 7351 struct mlx5_ifc_sqc_bits ctx; 7352 }; 7353 7354 struct mlx5_ifc_create_scheduling_element_out_bits { 7355 u8 status[0x8]; 7356 u8 reserved_at_8[0x18]; 7357 7358 u8 syndrome[0x20]; 7359 7360 u8 reserved_at_40[0x40]; 7361 7362 u8 scheduling_element_id[0x20]; 7363 7364 u8 reserved_at_a0[0x160]; 7365 }; 7366 7367 struct mlx5_ifc_create_scheduling_element_in_bits { 7368 u8 opcode[0x10]; 7369 u8 reserved_at_10[0x10]; 7370 7371 u8 reserved_at_20[0x10]; 7372 u8 op_mod[0x10]; 7373 7374 u8 scheduling_hierarchy[0x8]; 7375 u8 reserved_at_48[0x18]; 7376 7377 u8 reserved_at_60[0xa0]; 7378 7379 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7380 7381 u8 reserved_at_300[0x100]; 7382 }; 7383 7384 struct mlx5_ifc_create_rqt_out_bits { 7385 u8 status[0x8]; 7386 u8 reserved_at_8[0x18]; 7387 7388 u8 syndrome[0x20]; 7389 7390 u8 reserved_at_40[0x8]; 7391 u8 rqtn[0x18]; 7392 7393 u8 reserved_at_60[0x20]; 7394 }; 7395 7396 struct mlx5_ifc_create_rqt_in_bits { 7397 u8 opcode[0x10]; 7398 u8 uid[0x10]; 7399 7400 u8 reserved_at_20[0x10]; 7401 u8 op_mod[0x10]; 7402 7403 u8 reserved_at_40[0xc0]; 7404 7405 struct mlx5_ifc_rqtc_bits rqt_context; 7406 }; 7407 7408 struct mlx5_ifc_create_rq_out_bits { 7409 u8 status[0x8]; 7410 u8 reserved_at_8[0x18]; 7411 7412 u8 syndrome[0x20]; 7413 7414 u8 reserved_at_40[0x8]; 7415 u8 rqn[0x18]; 7416 7417 u8 reserved_at_60[0x20]; 7418 }; 7419 7420 struct mlx5_ifc_create_rq_in_bits { 7421 u8 opcode[0x10]; 7422 u8 uid[0x10]; 7423 7424 u8 reserved_at_20[0x10]; 7425 u8 op_mod[0x10]; 7426 7427 u8 reserved_at_40[0xc0]; 7428 7429 struct mlx5_ifc_rqc_bits ctx; 7430 }; 7431 7432 struct mlx5_ifc_create_rmp_out_bits { 7433 u8 status[0x8]; 7434 u8 reserved_at_8[0x18]; 7435 7436 u8 syndrome[0x20]; 7437 7438 u8 reserved_at_40[0x8]; 7439 u8 rmpn[0x18]; 7440 7441 u8 reserved_at_60[0x20]; 7442 }; 7443 7444 struct mlx5_ifc_create_rmp_in_bits { 7445 u8 opcode[0x10]; 7446 u8 uid[0x10]; 7447 7448 u8 reserved_at_20[0x10]; 7449 u8 op_mod[0x10]; 7450 7451 u8 reserved_at_40[0xc0]; 7452 7453 struct mlx5_ifc_rmpc_bits ctx; 7454 }; 7455 7456 struct mlx5_ifc_create_qp_out_bits { 7457 u8 status[0x8]; 7458 u8 reserved_at_8[0x18]; 7459 7460 u8 syndrome[0x20]; 7461 7462 u8 reserved_at_40[0x8]; 7463 u8 qpn[0x18]; 7464 7465 u8 reserved_at_60[0x20]; 7466 }; 7467 7468 struct mlx5_ifc_create_qp_in_bits { 7469 u8 opcode[0x10]; 7470 u8 uid[0x10]; 7471 7472 u8 reserved_at_20[0x10]; 7473 u8 op_mod[0x10]; 7474 7475 u8 reserved_at_40[0x40]; 7476 7477 u8 opt_param_mask[0x20]; 7478 7479 u8 reserved_at_a0[0x20]; 7480 7481 struct mlx5_ifc_qpc_bits qpc; 7482 7483 u8 reserved_at_800[0x60]; 7484 7485 u8 wq_umem_valid[0x1]; 7486 u8 reserved_at_861[0x1f]; 7487 7488 u8 pas[0][0x40]; 7489 }; 7490 7491 struct mlx5_ifc_create_psv_out_bits { 7492 u8 status[0x8]; 7493 u8 reserved_at_8[0x18]; 7494 7495 u8 syndrome[0x20]; 7496 7497 u8 reserved_at_40[0x40]; 7498 7499 u8 reserved_at_80[0x8]; 7500 u8 psv0_index[0x18]; 7501 7502 u8 reserved_at_a0[0x8]; 7503 u8 psv1_index[0x18]; 7504 7505 u8 reserved_at_c0[0x8]; 7506 u8 psv2_index[0x18]; 7507 7508 u8 reserved_at_e0[0x8]; 7509 u8 psv3_index[0x18]; 7510 }; 7511 7512 struct mlx5_ifc_create_psv_in_bits { 7513 u8 opcode[0x10]; 7514 u8 reserved_at_10[0x10]; 7515 7516 u8 reserved_at_20[0x10]; 7517 u8 op_mod[0x10]; 7518 7519 u8 num_psv[0x4]; 7520 u8 reserved_at_44[0x4]; 7521 u8 pd[0x18]; 7522 7523 u8 reserved_at_60[0x20]; 7524 }; 7525 7526 struct mlx5_ifc_create_mkey_out_bits { 7527 u8 status[0x8]; 7528 u8 reserved_at_8[0x18]; 7529 7530 u8 syndrome[0x20]; 7531 7532 u8 reserved_at_40[0x8]; 7533 u8 mkey_index[0x18]; 7534 7535 u8 reserved_at_60[0x20]; 7536 }; 7537 7538 struct mlx5_ifc_create_mkey_in_bits { 7539 u8 opcode[0x10]; 7540 u8 reserved_at_10[0x10]; 7541 7542 u8 reserved_at_20[0x10]; 7543 u8 op_mod[0x10]; 7544 7545 u8 reserved_at_40[0x20]; 7546 7547 u8 pg_access[0x1]; 7548 u8 mkey_umem_valid[0x1]; 7549 u8 reserved_at_62[0x1e]; 7550 7551 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7552 7553 u8 reserved_at_280[0x80]; 7554 7555 u8 translations_octword_actual_size[0x20]; 7556 7557 u8 reserved_at_320[0x560]; 7558 7559 u8 klm_pas_mtt[0][0x20]; 7560 }; 7561 7562 enum { 7563 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7564 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7565 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7566 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7567 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7568 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7569 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7570 }; 7571 7572 struct mlx5_ifc_create_flow_table_out_bits { 7573 u8 status[0x8]; 7574 u8 icm_address_63_40[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 icm_address_39_32[0x8]; 7579 u8 table_id[0x18]; 7580 7581 u8 icm_address_31_0[0x20]; 7582 }; 7583 7584 struct mlx5_ifc_create_flow_table_in_bits { 7585 u8 opcode[0x10]; 7586 u8 reserved_at_10[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 other_vport[0x1]; 7592 u8 reserved_at_41[0xf]; 7593 u8 vport_number[0x10]; 7594 7595 u8 reserved_at_60[0x20]; 7596 7597 u8 table_type[0x8]; 7598 u8 reserved_at_88[0x18]; 7599 7600 u8 reserved_at_a0[0x20]; 7601 7602 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7603 }; 7604 7605 struct mlx5_ifc_create_flow_group_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_at_8[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_at_40[0x8]; 7612 u8 group_id[0x18]; 7613 7614 u8 reserved_at_60[0x20]; 7615 }; 7616 7617 enum { 7618 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7619 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7620 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7621 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7622 }; 7623 7624 struct mlx5_ifc_create_flow_group_in_bits { 7625 u8 opcode[0x10]; 7626 u8 reserved_at_10[0x10]; 7627 7628 u8 reserved_at_20[0x10]; 7629 u8 op_mod[0x10]; 7630 7631 u8 other_vport[0x1]; 7632 u8 reserved_at_41[0xf]; 7633 u8 vport_number[0x10]; 7634 7635 u8 reserved_at_60[0x20]; 7636 7637 u8 table_type[0x8]; 7638 u8 reserved_at_88[0x18]; 7639 7640 u8 reserved_at_a0[0x8]; 7641 u8 table_id[0x18]; 7642 7643 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7644 7645 u8 reserved_at_c1[0x1f]; 7646 7647 u8 start_flow_index[0x20]; 7648 7649 u8 reserved_at_100[0x20]; 7650 7651 u8 end_flow_index[0x20]; 7652 7653 u8 reserved_at_140[0xa0]; 7654 7655 u8 reserved_at_1e0[0x18]; 7656 u8 match_criteria_enable[0x8]; 7657 7658 struct mlx5_ifc_fte_match_param_bits match_criteria; 7659 7660 u8 reserved_at_1200[0xe00]; 7661 }; 7662 7663 struct mlx5_ifc_create_eq_out_bits { 7664 u8 status[0x8]; 7665 u8 reserved_at_8[0x18]; 7666 7667 u8 syndrome[0x20]; 7668 7669 u8 reserved_at_40[0x18]; 7670 u8 eq_number[0x8]; 7671 7672 u8 reserved_at_60[0x20]; 7673 }; 7674 7675 struct mlx5_ifc_create_eq_in_bits { 7676 u8 opcode[0x10]; 7677 u8 uid[0x10]; 7678 7679 u8 reserved_at_20[0x10]; 7680 u8 op_mod[0x10]; 7681 7682 u8 reserved_at_40[0x40]; 7683 7684 struct mlx5_ifc_eqc_bits eq_context_entry; 7685 7686 u8 reserved_at_280[0x40]; 7687 7688 u8 event_bitmask[4][0x40]; 7689 7690 u8 reserved_at_3c0[0x4c0]; 7691 7692 u8 pas[0][0x40]; 7693 }; 7694 7695 struct mlx5_ifc_create_dct_out_bits { 7696 u8 status[0x8]; 7697 u8 reserved_at_8[0x18]; 7698 7699 u8 syndrome[0x20]; 7700 7701 u8 reserved_at_40[0x8]; 7702 u8 dctn[0x18]; 7703 7704 u8 reserved_at_60[0x20]; 7705 }; 7706 7707 struct mlx5_ifc_create_dct_in_bits { 7708 u8 opcode[0x10]; 7709 u8 uid[0x10]; 7710 7711 u8 reserved_at_20[0x10]; 7712 u8 op_mod[0x10]; 7713 7714 u8 reserved_at_40[0x40]; 7715 7716 struct mlx5_ifc_dctc_bits dct_context_entry; 7717 7718 u8 reserved_at_280[0x180]; 7719 }; 7720 7721 struct mlx5_ifc_create_cq_out_bits { 7722 u8 status[0x8]; 7723 u8 reserved_at_8[0x18]; 7724 7725 u8 syndrome[0x20]; 7726 7727 u8 reserved_at_40[0x8]; 7728 u8 cqn[0x18]; 7729 7730 u8 reserved_at_60[0x20]; 7731 }; 7732 7733 struct mlx5_ifc_create_cq_in_bits { 7734 u8 opcode[0x10]; 7735 u8 uid[0x10]; 7736 7737 u8 reserved_at_20[0x10]; 7738 u8 op_mod[0x10]; 7739 7740 u8 reserved_at_40[0x40]; 7741 7742 struct mlx5_ifc_cqc_bits cq_context; 7743 7744 u8 reserved_at_280[0x60]; 7745 7746 u8 cq_umem_valid[0x1]; 7747 u8 reserved_at_2e1[0x59f]; 7748 7749 u8 pas[0][0x40]; 7750 }; 7751 7752 struct mlx5_ifc_config_int_moderation_out_bits { 7753 u8 status[0x8]; 7754 u8 reserved_at_8[0x18]; 7755 7756 u8 syndrome[0x20]; 7757 7758 u8 reserved_at_40[0x4]; 7759 u8 min_delay[0xc]; 7760 u8 int_vector[0x10]; 7761 7762 u8 reserved_at_60[0x20]; 7763 }; 7764 7765 enum { 7766 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7767 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7768 }; 7769 7770 struct mlx5_ifc_config_int_moderation_in_bits { 7771 u8 opcode[0x10]; 7772 u8 reserved_at_10[0x10]; 7773 7774 u8 reserved_at_20[0x10]; 7775 u8 op_mod[0x10]; 7776 7777 u8 reserved_at_40[0x4]; 7778 u8 min_delay[0xc]; 7779 u8 int_vector[0x10]; 7780 7781 u8 reserved_at_60[0x20]; 7782 }; 7783 7784 struct mlx5_ifc_attach_to_mcg_out_bits { 7785 u8 status[0x8]; 7786 u8 reserved_at_8[0x18]; 7787 7788 u8 syndrome[0x20]; 7789 7790 u8 reserved_at_40[0x40]; 7791 }; 7792 7793 struct mlx5_ifc_attach_to_mcg_in_bits { 7794 u8 opcode[0x10]; 7795 u8 uid[0x10]; 7796 7797 u8 reserved_at_20[0x10]; 7798 u8 op_mod[0x10]; 7799 7800 u8 reserved_at_40[0x8]; 7801 u8 qpn[0x18]; 7802 7803 u8 reserved_at_60[0x20]; 7804 7805 u8 multicast_gid[16][0x8]; 7806 }; 7807 7808 struct mlx5_ifc_arm_xrq_out_bits { 7809 u8 status[0x8]; 7810 u8 reserved_at_8[0x18]; 7811 7812 u8 syndrome[0x20]; 7813 7814 u8 reserved_at_40[0x40]; 7815 }; 7816 7817 struct mlx5_ifc_arm_xrq_in_bits { 7818 u8 opcode[0x10]; 7819 u8 reserved_at_10[0x10]; 7820 7821 u8 reserved_at_20[0x10]; 7822 u8 op_mod[0x10]; 7823 7824 u8 reserved_at_40[0x8]; 7825 u8 xrqn[0x18]; 7826 7827 u8 reserved_at_60[0x10]; 7828 u8 lwm[0x10]; 7829 }; 7830 7831 struct mlx5_ifc_arm_xrc_srq_out_bits { 7832 u8 status[0x8]; 7833 u8 reserved_at_8[0x18]; 7834 7835 u8 syndrome[0x20]; 7836 7837 u8 reserved_at_40[0x40]; 7838 }; 7839 7840 enum { 7841 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7842 }; 7843 7844 struct mlx5_ifc_arm_xrc_srq_in_bits { 7845 u8 opcode[0x10]; 7846 u8 uid[0x10]; 7847 7848 u8 reserved_at_20[0x10]; 7849 u8 op_mod[0x10]; 7850 7851 u8 reserved_at_40[0x8]; 7852 u8 xrc_srqn[0x18]; 7853 7854 u8 reserved_at_60[0x10]; 7855 u8 lwm[0x10]; 7856 }; 7857 7858 struct mlx5_ifc_arm_rq_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 enum { 7868 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7869 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7870 }; 7871 7872 struct mlx5_ifc_arm_rq_in_bits { 7873 u8 opcode[0x10]; 7874 u8 uid[0x10]; 7875 7876 u8 reserved_at_20[0x10]; 7877 u8 op_mod[0x10]; 7878 7879 u8 reserved_at_40[0x8]; 7880 u8 srq_number[0x18]; 7881 7882 u8 reserved_at_60[0x10]; 7883 u8 lwm[0x10]; 7884 }; 7885 7886 struct mlx5_ifc_arm_dct_out_bits { 7887 u8 status[0x8]; 7888 u8 reserved_at_8[0x18]; 7889 7890 u8 syndrome[0x20]; 7891 7892 u8 reserved_at_40[0x40]; 7893 }; 7894 7895 struct mlx5_ifc_arm_dct_in_bits { 7896 u8 opcode[0x10]; 7897 u8 reserved_at_10[0x10]; 7898 7899 u8 reserved_at_20[0x10]; 7900 u8 op_mod[0x10]; 7901 7902 u8 reserved_at_40[0x8]; 7903 u8 dct_number[0x18]; 7904 7905 u8 reserved_at_60[0x20]; 7906 }; 7907 7908 struct mlx5_ifc_alloc_xrcd_out_bits { 7909 u8 status[0x8]; 7910 u8 reserved_at_8[0x18]; 7911 7912 u8 syndrome[0x20]; 7913 7914 u8 reserved_at_40[0x8]; 7915 u8 xrcd[0x18]; 7916 7917 u8 reserved_at_60[0x20]; 7918 }; 7919 7920 struct mlx5_ifc_alloc_xrcd_in_bits { 7921 u8 opcode[0x10]; 7922 u8 uid[0x10]; 7923 7924 u8 reserved_at_20[0x10]; 7925 u8 op_mod[0x10]; 7926 7927 u8 reserved_at_40[0x40]; 7928 }; 7929 7930 struct mlx5_ifc_alloc_uar_out_bits { 7931 u8 status[0x8]; 7932 u8 reserved_at_8[0x18]; 7933 7934 u8 syndrome[0x20]; 7935 7936 u8 reserved_at_40[0x8]; 7937 u8 uar[0x18]; 7938 7939 u8 reserved_at_60[0x20]; 7940 }; 7941 7942 struct mlx5_ifc_alloc_uar_in_bits { 7943 u8 opcode[0x10]; 7944 u8 reserved_at_10[0x10]; 7945 7946 u8 reserved_at_20[0x10]; 7947 u8 op_mod[0x10]; 7948 7949 u8 reserved_at_40[0x40]; 7950 }; 7951 7952 struct mlx5_ifc_alloc_transport_domain_out_bits { 7953 u8 status[0x8]; 7954 u8 reserved_at_8[0x18]; 7955 7956 u8 syndrome[0x20]; 7957 7958 u8 reserved_at_40[0x8]; 7959 u8 transport_domain[0x18]; 7960 7961 u8 reserved_at_60[0x20]; 7962 }; 7963 7964 struct mlx5_ifc_alloc_transport_domain_in_bits { 7965 u8 opcode[0x10]; 7966 u8 uid[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x40]; 7972 }; 7973 7974 struct mlx5_ifc_alloc_q_counter_out_bits { 7975 u8 status[0x8]; 7976 u8 reserved_at_8[0x18]; 7977 7978 u8 syndrome[0x20]; 7979 7980 u8 reserved_at_40[0x18]; 7981 u8 counter_set_id[0x8]; 7982 7983 u8 reserved_at_60[0x20]; 7984 }; 7985 7986 struct mlx5_ifc_alloc_q_counter_in_bits { 7987 u8 opcode[0x10]; 7988 u8 uid[0x10]; 7989 7990 u8 reserved_at_20[0x10]; 7991 u8 op_mod[0x10]; 7992 7993 u8 reserved_at_40[0x40]; 7994 }; 7995 7996 struct mlx5_ifc_alloc_pd_out_bits { 7997 u8 status[0x8]; 7998 u8 reserved_at_8[0x18]; 7999 8000 u8 syndrome[0x20]; 8001 8002 u8 reserved_at_40[0x8]; 8003 u8 pd[0x18]; 8004 8005 u8 reserved_at_60[0x20]; 8006 }; 8007 8008 struct mlx5_ifc_alloc_pd_in_bits { 8009 u8 opcode[0x10]; 8010 u8 uid[0x10]; 8011 8012 u8 reserved_at_20[0x10]; 8013 u8 op_mod[0x10]; 8014 8015 u8 reserved_at_40[0x40]; 8016 }; 8017 8018 struct mlx5_ifc_alloc_flow_counter_out_bits { 8019 u8 status[0x8]; 8020 u8 reserved_at_8[0x18]; 8021 8022 u8 syndrome[0x20]; 8023 8024 u8 flow_counter_id[0x20]; 8025 8026 u8 reserved_at_60[0x20]; 8027 }; 8028 8029 struct mlx5_ifc_alloc_flow_counter_in_bits { 8030 u8 opcode[0x10]; 8031 u8 reserved_at_10[0x10]; 8032 8033 u8 reserved_at_20[0x10]; 8034 u8 op_mod[0x10]; 8035 8036 u8 reserved_at_40[0x38]; 8037 u8 flow_counter_bulk[0x8]; 8038 }; 8039 8040 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8041 u8 status[0x8]; 8042 u8 reserved_at_8[0x18]; 8043 8044 u8 syndrome[0x20]; 8045 8046 u8 reserved_at_40[0x40]; 8047 }; 8048 8049 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8050 u8 opcode[0x10]; 8051 u8 reserved_at_10[0x10]; 8052 8053 u8 reserved_at_20[0x10]; 8054 u8 op_mod[0x10]; 8055 8056 u8 reserved_at_40[0x20]; 8057 8058 u8 reserved_at_60[0x10]; 8059 u8 vxlan_udp_port[0x10]; 8060 }; 8061 8062 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8063 u8 status[0x8]; 8064 u8 reserved_at_8[0x18]; 8065 8066 u8 syndrome[0x20]; 8067 8068 u8 reserved_at_40[0x40]; 8069 }; 8070 8071 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8072 u8 opcode[0x10]; 8073 u8 reserved_at_10[0x10]; 8074 8075 u8 reserved_at_20[0x10]; 8076 u8 op_mod[0x10]; 8077 8078 u8 reserved_at_40[0x10]; 8079 u8 rate_limit_index[0x10]; 8080 8081 u8 reserved_at_60[0x20]; 8082 8083 u8 rate_limit[0x20]; 8084 8085 u8 burst_upper_bound[0x20]; 8086 8087 u8 reserved_at_c0[0x10]; 8088 u8 typical_packet_size[0x10]; 8089 8090 u8 reserved_at_e0[0x120]; 8091 }; 8092 8093 struct mlx5_ifc_access_register_out_bits { 8094 u8 status[0x8]; 8095 u8 reserved_at_8[0x18]; 8096 8097 u8 syndrome[0x20]; 8098 8099 u8 reserved_at_40[0x40]; 8100 8101 u8 register_data[0][0x20]; 8102 }; 8103 8104 enum { 8105 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8106 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8107 }; 8108 8109 struct mlx5_ifc_access_register_in_bits { 8110 u8 opcode[0x10]; 8111 u8 reserved_at_10[0x10]; 8112 8113 u8 reserved_at_20[0x10]; 8114 u8 op_mod[0x10]; 8115 8116 u8 reserved_at_40[0x10]; 8117 u8 register_id[0x10]; 8118 8119 u8 argument[0x20]; 8120 8121 u8 register_data[0][0x20]; 8122 }; 8123 8124 struct mlx5_ifc_sltp_reg_bits { 8125 u8 status[0x4]; 8126 u8 version[0x4]; 8127 u8 local_port[0x8]; 8128 u8 pnat[0x2]; 8129 u8 reserved_at_12[0x2]; 8130 u8 lane[0x4]; 8131 u8 reserved_at_18[0x8]; 8132 8133 u8 reserved_at_20[0x20]; 8134 8135 u8 reserved_at_40[0x7]; 8136 u8 polarity[0x1]; 8137 u8 ob_tap0[0x8]; 8138 u8 ob_tap1[0x8]; 8139 u8 ob_tap2[0x8]; 8140 8141 u8 reserved_at_60[0xc]; 8142 u8 ob_preemp_mode[0x4]; 8143 u8 ob_reg[0x8]; 8144 u8 ob_bias[0x8]; 8145 8146 u8 reserved_at_80[0x20]; 8147 }; 8148 8149 struct mlx5_ifc_slrg_reg_bits { 8150 u8 status[0x4]; 8151 u8 version[0x4]; 8152 u8 local_port[0x8]; 8153 u8 pnat[0x2]; 8154 u8 reserved_at_12[0x2]; 8155 u8 lane[0x4]; 8156 u8 reserved_at_18[0x8]; 8157 8158 u8 time_to_link_up[0x10]; 8159 u8 reserved_at_30[0xc]; 8160 u8 grade_lane_speed[0x4]; 8161 8162 u8 grade_version[0x8]; 8163 u8 grade[0x18]; 8164 8165 u8 reserved_at_60[0x4]; 8166 u8 height_grade_type[0x4]; 8167 u8 height_grade[0x18]; 8168 8169 u8 height_dz[0x10]; 8170 u8 height_dv[0x10]; 8171 8172 u8 reserved_at_a0[0x10]; 8173 u8 height_sigma[0x10]; 8174 8175 u8 reserved_at_c0[0x20]; 8176 8177 u8 reserved_at_e0[0x4]; 8178 u8 phase_grade_type[0x4]; 8179 u8 phase_grade[0x18]; 8180 8181 u8 reserved_at_100[0x8]; 8182 u8 phase_eo_pos[0x8]; 8183 u8 reserved_at_110[0x8]; 8184 u8 phase_eo_neg[0x8]; 8185 8186 u8 ffe_set_tested[0x10]; 8187 u8 test_errors_per_lane[0x10]; 8188 }; 8189 8190 struct mlx5_ifc_pvlc_reg_bits { 8191 u8 reserved_at_0[0x8]; 8192 u8 local_port[0x8]; 8193 u8 reserved_at_10[0x10]; 8194 8195 u8 reserved_at_20[0x1c]; 8196 u8 vl_hw_cap[0x4]; 8197 8198 u8 reserved_at_40[0x1c]; 8199 u8 vl_admin[0x4]; 8200 8201 u8 reserved_at_60[0x1c]; 8202 u8 vl_operational[0x4]; 8203 }; 8204 8205 struct mlx5_ifc_pude_reg_bits { 8206 u8 swid[0x8]; 8207 u8 local_port[0x8]; 8208 u8 reserved_at_10[0x4]; 8209 u8 admin_status[0x4]; 8210 u8 reserved_at_18[0x4]; 8211 u8 oper_status[0x4]; 8212 8213 u8 reserved_at_20[0x60]; 8214 }; 8215 8216 struct mlx5_ifc_ptys_reg_bits { 8217 u8 reserved_at_0[0x1]; 8218 u8 an_disable_admin[0x1]; 8219 u8 an_disable_cap[0x1]; 8220 u8 reserved_at_3[0x5]; 8221 u8 local_port[0x8]; 8222 u8 reserved_at_10[0xd]; 8223 u8 proto_mask[0x3]; 8224 8225 u8 an_status[0x4]; 8226 u8 reserved_at_24[0x1c]; 8227 8228 u8 ext_eth_proto_capability[0x20]; 8229 8230 u8 eth_proto_capability[0x20]; 8231 8232 u8 ib_link_width_capability[0x10]; 8233 u8 ib_proto_capability[0x10]; 8234 8235 u8 ext_eth_proto_admin[0x20]; 8236 8237 u8 eth_proto_admin[0x20]; 8238 8239 u8 ib_link_width_admin[0x10]; 8240 u8 ib_proto_admin[0x10]; 8241 8242 u8 ext_eth_proto_oper[0x20]; 8243 8244 u8 eth_proto_oper[0x20]; 8245 8246 u8 ib_link_width_oper[0x10]; 8247 u8 ib_proto_oper[0x10]; 8248 8249 u8 reserved_at_160[0x1c]; 8250 u8 connector_type[0x4]; 8251 8252 u8 eth_proto_lp_advertise[0x20]; 8253 8254 u8 reserved_at_1a0[0x60]; 8255 }; 8256 8257 struct mlx5_ifc_mlcr_reg_bits { 8258 u8 reserved_at_0[0x8]; 8259 u8 local_port[0x8]; 8260 u8 reserved_at_10[0x20]; 8261 8262 u8 beacon_duration[0x10]; 8263 u8 reserved_at_40[0x10]; 8264 8265 u8 beacon_remain[0x10]; 8266 }; 8267 8268 struct mlx5_ifc_ptas_reg_bits { 8269 u8 reserved_at_0[0x20]; 8270 8271 u8 algorithm_options[0x10]; 8272 u8 reserved_at_30[0x4]; 8273 u8 repetitions_mode[0x4]; 8274 u8 num_of_repetitions[0x8]; 8275 8276 u8 grade_version[0x8]; 8277 u8 height_grade_type[0x4]; 8278 u8 phase_grade_type[0x4]; 8279 u8 height_grade_weight[0x8]; 8280 u8 phase_grade_weight[0x8]; 8281 8282 u8 gisim_measure_bits[0x10]; 8283 u8 adaptive_tap_measure_bits[0x10]; 8284 8285 u8 ber_bath_high_error_threshold[0x10]; 8286 u8 ber_bath_mid_error_threshold[0x10]; 8287 8288 u8 ber_bath_low_error_threshold[0x10]; 8289 u8 one_ratio_high_threshold[0x10]; 8290 8291 u8 one_ratio_high_mid_threshold[0x10]; 8292 u8 one_ratio_low_mid_threshold[0x10]; 8293 8294 u8 one_ratio_low_threshold[0x10]; 8295 u8 ndeo_error_threshold[0x10]; 8296 8297 u8 mixer_offset_step_size[0x10]; 8298 u8 reserved_at_110[0x8]; 8299 u8 mix90_phase_for_voltage_bath[0x8]; 8300 8301 u8 mixer_offset_start[0x10]; 8302 u8 mixer_offset_end[0x10]; 8303 8304 u8 reserved_at_140[0x15]; 8305 u8 ber_test_time[0xb]; 8306 }; 8307 8308 struct mlx5_ifc_pspa_reg_bits { 8309 u8 swid[0x8]; 8310 u8 local_port[0x8]; 8311 u8 sub_port[0x8]; 8312 u8 reserved_at_18[0x8]; 8313 8314 u8 reserved_at_20[0x20]; 8315 }; 8316 8317 struct mlx5_ifc_pqdr_reg_bits { 8318 u8 reserved_at_0[0x8]; 8319 u8 local_port[0x8]; 8320 u8 reserved_at_10[0x5]; 8321 u8 prio[0x3]; 8322 u8 reserved_at_18[0x6]; 8323 u8 mode[0x2]; 8324 8325 u8 reserved_at_20[0x20]; 8326 8327 u8 reserved_at_40[0x10]; 8328 u8 min_threshold[0x10]; 8329 8330 u8 reserved_at_60[0x10]; 8331 u8 max_threshold[0x10]; 8332 8333 u8 reserved_at_80[0x10]; 8334 u8 mark_probability_denominator[0x10]; 8335 8336 u8 reserved_at_a0[0x60]; 8337 }; 8338 8339 struct mlx5_ifc_ppsc_reg_bits { 8340 u8 reserved_at_0[0x8]; 8341 u8 local_port[0x8]; 8342 u8 reserved_at_10[0x10]; 8343 8344 u8 reserved_at_20[0x60]; 8345 8346 u8 reserved_at_80[0x1c]; 8347 u8 wrps_admin[0x4]; 8348 8349 u8 reserved_at_a0[0x1c]; 8350 u8 wrps_status[0x4]; 8351 8352 u8 reserved_at_c0[0x8]; 8353 u8 up_threshold[0x8]; 8354 u8 reserved_at_d0[0x8]; 8355 u8 down_threshold[0x8]; 8356 8357 u8 reserved_at_e0[0x20]; 8358 8359 u8 reserved_at_100[0x1c]; 8360 u8 srps_admin[0x4]; 8361 8362 u8 reserved_at_120[0x1c]; 8363 u8 srps_status[0x4]; 8364 8365 u8 reserved_at_140[0x40]; 8366 }; 8367 8368 struct mlx5_ifc_pplr_reg_bits { 8369 u8 reserved_at_0[0x8]; 8370 u8 local_port[0x8]; 8371 u8 reserved_at_10[0x10]; 8372 8373 u8 reserved_at_20[0x8]; 8374 u8 lb_cap[0x8]; 8375 u8 reserved_at_30[0x8]; 8376 u8 lb_en[0x8]; 8377 }; 8378 8379 struct mlx5_ifc_pplm_reg_bits { 8380 u8 reserved_at_0[0x8]; 8381 u8 local_port[0x8]; 8382 u8 reserved_at_10[0x10]; 8383 8384 u8 reserved_at_20[0x20]; 8385 8386 u8 port_profile_mode[0x8]; 8387 u8 static_port_profile[0x8]; 8388 u8 active_port_profile[0x8]; 8389 u8 reserved_at_58[0x8]; 8390 8391 u8 retransmission_active[0x8]; 8392 u8 fec_mode_active[0x18]; 8393 8394 u8 rs_fec_correction_bypass_cap[0x4]; 8395 u8 reserved_at_84[0x8]; 8396 u8 fec_override_cap_56g[0x4]; 8397 u8 fec_override_cap_100g[0x4]; 8398 u8 fec_override_cap_50g[0x4]; 8399 u8 fec_override_cap_25g[0x4]; 8400 u8 fec_override_cap_10g_40g[0x4]; 8401 8402 u8 rs_fec_correction_bypass_admin[0x4]; 8403 u8 reserved_at_a4[0x8]; 8404 u8 fec_override_admin_56g[0x4]; 8405 u8 fec_override_admin_100g[0x4]; 8406 u8 fec_override_admin_50g[0x4]; 8407 u8 fec_override_admin_25g[0x4]; 8408 u8 fec_override_admin_10g_40g[0x4]; 8409 }; 8410 8411 struct mlx5_ifc_ppcnt_reg_bits { 8412 u8 swid[0x8]; 8413 u8 local_port[0x8]; 8414 u8 pnat[0x2]; 8415 u8 reserved_at_12[0x8]; 8416 u8 grp[0x6]; 8417 8418 u8 clr[0x1]; 8419 u8 reserved_at_21[0x1c]; 8420 u8 prio_tc[0x3]; 8421 8422 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8423 }; 8424 8425 struct mlx5_ifc_mpein_reg_bits { 8426 u8 reserved_at_0[0x2]; 8427 u8 depth[0x6]; 8428 u8 pcie_index[0x8]; 8429 u8 node[0x8]; 8430 u8 reserved_at_18[0x8]; 8431 8432 u8 capability_mask[0x20]; 8433 8434 u8 reserved_at_40[0x8]; 8435 u8 link_width_enabled[0x8]; 8436 u8 link_speed_enabled[0x10]; 8437 8438 u8 lane0_physical_position[0x8]; 8439 u8 link_width_active[0x8]; 8440 u8 link_speed_active[0x10]; 8441 8442 u8 num_of_pfs[0x10]; 8443 u8 num_of_vfs[0x10]; 8444 8445 u8 bdf0[0x10]; 8446 u8 reserved_at_b0[0x10]; 8447 8448 u8 max_read_request_size[0x4]; 8449 u8 max_payload_size[0x4]; 8450 u8 reserved_at_c8[0x5]; 8451 u8 pwr_status[0x3]; 8452 u8 port_type[0x4]; 8453 u8 reserved_at_d4[0xb]; 8454 u8 lane_reversal[0x1]; 8455 8456 u8 reserved_at_e0[0x14]; 8457 u8 pci_power[0xc]; 8458 8459 u8 reserved_at_100[0x20]; 8460 8461 u8 device_status[0x10]; 8462 u8 port_state[0x8]; 8463 u8 reserved_at_138[0x8]; 8464 8465 u8 reserved_at_140[0x10]; 8466 u8 receiver_detect_result[0x10]; 8467 8468 u8 reserved_at_160[0x20]; 8469 }; 8470 8471 struct mlx5_ifc_mpcnt_reg_bits { 8472 u8 reserved_at_0[0x8]; 8473 u8 pcie_index[0x8]; 8474 u8 reserved_at_10[0xa]; 8475 u8 grp[0x6]; 8476 8477 u8 clr[0x1]; 8478 u8 reserved_at_21[0x1f]; 8479 8480 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8481 }; 8482 8483 struct mlx5_ifc_ppad_reg_bits { 8484 u8 reserved_at_0[0x3]; 8485 u8 single_mac[0x1]; 8486 u8 reserved_at_4[0x4]; 8487 u8 local_port[0x8]; 8488 u8 mac_47_32[0x10]; 8489 8490 u8 mac_31_0[0x20]; 8491 8492 u8 reserved_at_40[0x40]; 8493 }; 8494 8495 struct mlx5_ifc_pmtu_reg_bits { 8496 u8 reserved_at_0[0x8]; 8497 u8 local_port[0x8]; 8498 u8 reserved_at_10[0x10]; 8499 8500 u8 max_mtu[0x10]; 8501 u8 reserved_at_30[0x10]; 8502 8503 u8 admin_mtu[0x10]; 8504 u8 reserved_at_50[0x10]; 8505 8506 u8 oper_mtu[0x10]; 8507 u8 reserved_at_70[0x10]; 8508 }; 8509 8510 struct mlx5_ifc_pmpr_reg_bits { 8511 u8 reserved_at_0[0x8]; 8512 u8 module[0x8]; 8513 u8 reserved_at_10[0x10]; 8514 8515 u8 reserved_at_20[0x18]; 8516 u8 attenuation_5g[0x8]; 8517 8518 u8 reserved_at_40[0x18]; 8519 u8 attenuation_7g[0x8]; 8520 8521 u8 reserved_at_60[0x18]; 8522 u8 attenuation_12g[0x8]; 8523 }; 8524 8525 struct mlx5_ifc_pmpe_reg_bits { 8526 u8 reserved_at_0[0x8]; 8527 u8 module[0x8]; 8528 u8 reserved_at_10[0xc]; 8529 u8 module_status[0x4]; 8530 8531 u8 reserved_at_20[0x60]; 8532 }; 8533 8534 struct mlx5_ifc_pmpc_reg_bits { 8535 u8 module_state_updated[32][0x8]; 8536 }; 8537 8538 struct mlx5_ifc_pmlpn_reg_bits { 8539 u8 reserved_at_0[0x4]; 8540 u8 mlpn_status[0x4]; 8541 u8 local_port[0x8]; 8542 u8 reserved_at_10[0x10]; 8543 8544 u8 e[0x1]; 8545 u8 reserved_at_21[0x1f]; 8546 }; 8547 8548 struct mlx5_ifc_pmlp_reg_bits { 8549 u8 rxtx[0x1]; 8550 u8 reserved_at_1[0x7]; 8551 u8 local_port[0x8]; 8552 u8 reserved_at_10[0x8]; 8553 u8 width[0x8]; 8554 8555 u8 lane0_module_mapping[0x20]; 8556 8557 u8 lane1_module_mapping[0x20]; 8558 8559 u8 lane2_module_mapping[0x20]; 8560 8561 u8 lane3_module_mapping[0x20]; 8562 8563 u8 reserved_at_a0[0x160]; 8564 }; 8565 8566 struct mlx5_ifc_pmaos_reg_bits { 8567 u8 reserved_at_0[0x8]; 8568 u8 module[0x8]; 8569 u8 reserved_at_10[0x4]; 8570 u8 admin_status[0x4]; 8571 u8 reserved_at_18[0x4]; 8572 u8 oper_status[0x4]; 8573 8574 u8 ase[0x1]; 8575 u8 ee[0x1]; 8576 u8 reserved_at_22[0x1c]; 8577 u8 e[0x2]; 8578 8579 u8 reserved_at_40[0x40]; 8580 }; 8581 8582 struct mlx5_ifc_plpc_reg_bits { 8583 u8 reserved_at_0[0x4]; 8584 u8 profile_id[0xc]; 8585 u8 reserved_at_10[0x4]; 8586 u8 proto_mask[0x4]; 8587 u8 reserved_at_18[0x8]; 8588 8589 u8 reserved_at_20[0x10]; 8590 u8 lane_speed[0x10]; 8591 8592 u8 reserved_at_40[0x17]; 8593 u8 lpbf[0x1]; 8594 u8 fec_mode_policy[0x8]; 8595 8596 u8 retransmission_capability[0x8]; 8597 u8 fec_mode_capability[0x18]; 8598 8599 u8 retransmission_support_admin[0x8]; 8600 u8 fec_mode_support_admin[0x18]; 8601 8602 u8 retransmission_request_admin[0x8]; 8603 u8 fec_mode_request_admin[0x18]; 8604 8605 u8 reserved_at_c0[0x80]; 8606 }; 8607 8608 struct mlx5_ifc_plib_reg_bits { 8609 u8 reserved_at_0[0x8]; 8610 u8 local_port[0x8]; 8611 u8 reserved_at_10[0x8]; 8612 u8 ib_port[0x8]; 8613 8614 u8 reserved_at_20[0x60]; 8615 }; 8616 8617 struct mlx5_ifc_plbf_reg_bits { 8618 u8 reserved_at_0[0x8]; 8619 u8 local_port[0x8]; 8620 u8 reserved_at_10[0xd]; 8621 u8 lbf_mode[0x3]; 8622 8623 u8 reserved_at_20[0x20]; 8624 }; 8625 8626 struct mlx5_ifc_pipg_reg_bits { 8627 u8 reserved_at_0[0x8]; 8628 u8 local_port[0x8]; 8629 u8 reserved_at_10[0x10]; 8630 8631 u8 dic[0x1]; 8632 u8 reserved_at_21[0x19]; 8633 u8 ipg[0x4]; 8634 u8 reserved_at_3e[0x2]; 8635 }; 8636 8637 struct mlx5_ifc_pifr_reg_bits { 8638 u8 reserved_at_0[0x8]; 8639 u8 local_port[0x8]; 8640 u8 reserved_at_10[0x10]; 8641 8642 u8 reserved_at_20[0xe0]; 8643 8644 u8 port_filter[8][0x20]; 8645 8646 u8 port_filter_update_en[8][0x20]; 8647 }; 8648 8649 struct mlx5_ifc_pfcc_reg_bits { 8650 u8 reserved_at_0[0x8]; 8651 u8 local_port[0x8]; 8652 u8 reserved_at_10[0xb]; 8653 u8 ppan_mask_n[0x1]; 8654 u8 minor_stall_mask[0x1]; 8655 u8 critical_stall_mask[0x1]; 8656 u8 reserved_at_1e[0x2]; 8657 8658 u8 ppan[0x4]; 8659 u8 reserved_at_24[0x4]; 8660 u8 prio_mask_tx[0x8]; 8661 u8 reserved_at_30[0x8]; 8662 u8 prio_mask_rx[0x8]; 8663 8664 u8 pptx[0x1]; 8665 u8 aptx[0x1]; 8666 u8 pptx_mask_n[0x1]; 8667 u8 reserved_at_43[0x5]; 8668 u8 pfctx[0x8]; 8669 u8 reserved_at_50[0x10]; 8670 8671 u8 pprx[0x1]; 8672 u8 aprx[0x1]; 8673 u8 pprx_mask_n[0x1]; 8674 u8 reserved_at_63[0x5]; 8675 u8 pfcrx[0x8]; 8676 u8 reserved_at_70[0x10]; 8677 8678 u8 device_stall_minor_watermark[0x10]; 8679 u8 device_stall_critical_watermark[0x10]; 8680 8681 u8 reserved_at_a0[0x60]; 8682 }; 8683 8684 struct mlx5_ifc_pelc_reg_bits { 8685 u8 op[0x4]; 8686 u8 reserved_at_4[0x4]; 8687 u8 local_port[0x8]; 8688 u8 reserved_at_10[0x10]; 8689 8690 u8 op_admin[0x8]; 8691 u8 op_capability[0x8]; 8692 u8 op_request[0x8]; 8693 u8 op_active[0x8]; 8694 8695 u8 admin[0x40]; 8696 8697 u8 capability[0x40]; 8698 8699 u8 request[0x40]; 8700 8701 u8 active[0x40]; 8702 8703 u8 reserved_at_140[0x80]; 8704 }; 8705 8706 struct mlx5_ifc_peir_reg_bits { 8707 u8 reserved_at_0[0x8]; 8708 u8 local_port[0x8]; 8709 u8 reserved_at_10[0x10]; 8710 8711 u8 reserved_at_20[0xc]; 8712 u8 error_count[0x4]; 8713 u8 reserved_at_30[0x10]; 8714 8715 u8 reserved_at_40[0xc]; 8716 u8 lane[0x4]; 8717 u8 reserved_at_50[0x8]; 8718 u8 error_type[0x8]; 8719 }; 8720 8721 struct mlx5_ifc_mpegc_reg_bits { 8722 u8 reserved_at_0[0x30]; 8723 u8 field_select[0x10]; 8724 8725 u8 tx_overflow_sense[0x1]; 8726 u8 mark_cqe[0x1]; 8727 u8 mark_cnp[0x1]; 8728 u8 reserved_at_43[0x1b]; 8729 u8 tx_lossy_overflow_oper[0x2]; 8730 8731 u8 reserved_at_60[0x100]; 8732 }; 8733 8734 struct mlx5_ifc_pcam_enhanced_features_bits { 8735 u8 reserved_at_0[0x6d]; 8736 u8 rx_icrc_encapsulated_counter[0x1]; 8737 u8 reserved_at_6e[0x4]; 8738 u8 ptys_extended_ethernet[0x1]; 8739 u8 reserved_at_73[0x3]; 8740 u8 pfcc_mask[0x1]; 8741 u8 reserved_at_77[0x3]; 8742 u8 per_lane_error_counters[0x1]; 8743 u8 rx_buffer_fullness_counters[0x1]; 8744 u8 ptys_connector_type[0x1]; 8745 u8 reserved_at_7d[0x1]; 8746 u8 ppcnt_discard_group[0x1]; 8747 u8 ppcnt_statistical_group[0x1]; 8748 }; 8749 8750 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8751 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8752 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8753 8754 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8755 u8 pplm[0x1]; 8756 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8757 8758 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8759 u8 pbmc[0x1]; 8760 u8 pptb[0x1]; 8761 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8762 u8 ppcnt[0x1]; 8763 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8764 }; 8765 8766 struct mlx5_ifc_pcam_reg_bits { 8767 u8 reserved_at_0[0x8]; 8768 u8 feature_group[0x8]; 8769 u8 reserved_at_10[0x8]; 8770 u8 access_reg_group[0x8]; 8771 8772 u8 reserved_at_20[0x20]; 8773 8774 union { 8775 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8776 u8 reserved_at_0[0x80]; 8777 } port_access_reg_cap_mask; 8778 8779 u8 reserved_at_c0[0x80]; 8780 8781 union { 8782 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8783 u8 reserved_at_0[0x80]; 8784 } feature_cap_mask; 8785 8786 u8 reserved_at_1c0[0xc0]; 8787 }; 8788 8789 struct mlx5_ifc_mcam_enhanced_features_bits { 8790 u8 reserved_at_0[0x6e]; 8791 u8 pci_status_and_power[0x1]; 8792 u8 reserved_at_6f[0x5]; 8793 u8 mark_tx_action_cnp[0x1]; 8794 u8 mark_tx_action_cqe[0x1]; 8795 u8 dynamic_tx_overflow[0x1]; 8796 u8 reserved_at_77[0x4]; 8797 u8 pcie_outbound_stalled[0x1]; 8798 u8 tx_overflow_buffer_pkt[0x1]; 8799 u8 mtpps_enh_out_per_adj[0x1]; 8800 u8 mtpps_fs[0x1]; 8801 u8 pcie_performance_group[0x1]; 8802 }; 8803 8804 struct mlx5_ifc_mcam_access_reg_bits { 8805 u8 reserved_at_0[0x1c]; 8806 u8 mcda[0x1]; 8807 u8 mcc[0x1]; 8808 u8 mcqi[0x1]; 8809 u8 mcqs[0x1]; 8810 8811 u8 regs_95_to_87[0x9]; 8812 u8 mpegc[0x1]; 8813 u8 regs_85_to_68[0x12]; 8814 u8 tracer_registers[0x4]; 8815 8816 u8 regs_63_to_32[0x20]; 8817 u8 regs_31_to_0[0x20]; 8818 }; 8819 8820 struct mlx5_ifc_mcam_reg_bits { 8821 u8 reserved_at_0[0x8]; 8822 u8 feature_group[0x8]; 8823 u8 reserved_at_10[0x8]; 8824 u8 access_reg_group[0x8]; 8825 8826 u8 reserved_at_20[0x20]; 8827 8828 union { 8829 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8830 u8 reserved_at_0[0x80]; 8831 } mng_access_reg_cap_mask; 8832 8833 u8 reserved_at_c0[0x80]; 8834 8835 union { 8836 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8837 u8 reserved_at_0[0x80]; 8838 } mng_feature_cap_mask; 8839 8840 u8 reserved_at_1c0[0x80]; 8841 }; 8842 8843 struct mlx5_ifc_qcam_access_reg_cap_mask { 8844 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8845 u8 qpdpm[0x1]; 8846 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8847 u8 qdpm[0x1]; 8848 u8 qpts[0x1]; 8849 u8 qcap[0x1]; 8850 u8 qcam_access_reg_cap_mask_0[0x1]; 8851 }; 8852 8853 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8854 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8855 u8 qpts_trust_both[0x1]; 8856 }; 8857 8858 struct mlx5_ifc_qcam_reg_bits { 8859 u8 reserved_at_0[0x8]; 8860 u8 feature_group[0x8]; 8861 u8 reserved_at_10[0x8]; 8862 u8 access_reg_group[0x8]; 8863 u8 reserved_at_20[0x20]; 8864 8865 union { 8866 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8867 u8 reserved_at_0[0x80]; 8868 } qos_access_reg_cap_mask; 8869 8870 u8 reserved_at_c0[0x80]; 8871 8872 union { 8873 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8874 u8 reserved_at_0[0x80]; 8875 } qos_feature_cap_mask; 8876 8877 u8 reserved_at_1c0[0x80]; 8878 }; 8879 8880 struct mlx5_ifc_core_dump_reg_bits { 8881 u8 reserved_at_0[0x18]; 8882 u8 core_dump_type[0x8]; 8883 8884 u8 reserved_at_20[0x30]; 8885 u8 vhca_id[0x10]; 8886 8887 u8 reserved_at_60[0x8]; 8888 u8 qpn[0x18]; 8889 u8 reserved_at_80[0x180]; 8890 }; 8891 8892 struct mlx5_ifc_pcap_reg_bits { 8893 u8 reserved_at_0[0x8]; 8894 u8 local_port[0x8]; 8895 u8 reserved_at_10[0x10]; 8896 8897 u8 port_capability_mask[4][0x20]; 8898 }; 8899 8900 struct mlx5_ifc_paos_reg_bits { 8901 u8 swid[0x8]; 8902 u8 local_port[0x8]; 8903 u8 reserved_at_10[0x4]; 8904 u8 admin_status[0x4]; 8905 u8 reserved_at_18[0x4]; 8906 u8 oper_status[0x4]; 8907 8908 u8 ase[0x1]; 8909 u8 ee[0x1]; 8910 u8 reserved_at_22[0x1c]; 8911 u8 e[0x2]; 8912 8913 u8 reserved_at_40[0x40]; 8914 }; 8915 8916 struct mlx5_ifc_pamp_reg_bits { 8917 u8 reserved_at_0[0x8]; 8918 u8 opamp_group[0x8]; 8919 u8 reserved_at_10[0xc]; 8920 u8 opamp_group_type[0x4]; 8921 8922 u8 start_index[0x10]; 8923 u8 reserved_at_30[0x4]; 8924 u8 num_of_indices[0xc]; 8925 8926 u8 index_data[18][0x10]; 8927 }; 8928 8929 struct mlx5_ifc_pcmr_reg_bits { 8930 u8 reserved_at_0[0x8]; 8931 u8 local_port[0x8]; 8932 u8 reserved_at_10[0x10]; 8933 u8 entropy_force_cap[0x1]; 8934 u8 entropy_calc_cap[0x1]; 8935 u8 entropy_gre_calc_cap[0x1]; 8936 u8 reserved_at_23[0x1b]; 8937 u8 fcs_cap[0x1]; 8938 u8 reserved_at_3f[0x1]; 8939 u8 entropy_force[0x1]; 8940 u8 entropy_calc[0x1]; 8941 u8 entropy_gre_calc[0x1]; 8942 u8 reserved_at_43[0x1b]; 8943 u8 fcs_chk[0x1]; 8944 u8 reserved_at_5f[0x1]; 8945 }; 8946 8947 struct mlx5_ifc_lane_2_module_mapping_bits { 8948 u8 reserved_at_0[0x6]; 8949 u8 rx_lane[0x2]; 8950 u8 reserved_at_8[0x6]; 8951 u8 tx_lane[0x2]; 8952 u8 reserved_at_10[0x8]; 8953 u8 module[0x8]; 8954 }; 8955 8956 struct mlx5_ifc_bufferx_reg_bits { 8957 u8 reserved_at_0[0x6]; 8958 u8 lossy[0x1]; 8959 u8 epsb[0x1]; 8960 u8 reserved_at_8[0xc]; 8961 u8 size[0xc]; 8962 8963 u8 xoff_threshold[0x10]; 8964 u8 xon_threshold[0x10]; 8965 }; 8966 8967 struct mlx5_ifc_set_node_in_bits { 8968 u8 node_description[64][0x8]; 8969 }; 8970 8971 struct mlx5_ifc_register_power_settings_bits { 8972 u8 reserved_at_0[0x18]; 8973 u8 power_settings_level[0x8]; 8974 8975 u8 reserved_at_20[0x60]; 8976 }; 8977 8978 struct mlx5_ifc_register_host_endianness_bits { 8979 u8 he[0x1]; 8980 u8 reserved_at_1[0x1f]; 8981 8982 u8 reserved_at_20[0x60]; 8983 }; 8984 8985 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8986 u8 reserved_at_0[0x20]; 8987 8988 u8 mkey[0x20]; 8989 8990 u8 addressh_63_32[0x20]; 8991 8992 u8 addressl_31_0[0x20]; 8993 }; 8994 8995 struct mlx5_ifc_ud_adrs_vector_bits { 8996 u8 dc_key[0x40]; 8997 8998 u8 ext[0x1]; 8999 u8 reserved_at_41[0x7]; 9000 u8 destination_qp_dct[0x18]; 9001 9002 u8 static_rate[0x4]; 9003 u8 sl_eth_prio[0x4]; 9004 u8 fl[0x1]; 9005 u8 mlid[0x7]; 9006 u8 rlid_udp_sport[0x10]; 9007 9008 u8 reserved_at_80[0x20]; 9009 9010 u8 rmac_47_16[0x20]; 9011 9012 u8 rmac_15_0[0x10]; 9013 u8 tclass[0x8]; 9014 u8 hop_limit[0x8]; 9015 9016 u8 reserved_at_e0[0x1]; 9017 u8 grh[0x1]; 9018 u8 reserved_at_e2[0x2]; 9019 u8 src_addr_index[0x8]; 9020 u8 flow_label[0x14]; 9021 9022 u8 rgid_rip[16][0x8]; 9023 }; 9024 9025 struct mlx5_ifc_pages_req_event_bits { 9026 u8 reserved_at_0[0x10]; 9027 u8 function_id[0x10]; 9028 9029 u8 num_pages[0x20]; 9030 9031 u8 reserved_at_40[0xa0]; 9032 }; 9033 9034 struct mlx5_ifc_eqe_bits { 9035 u8 reserved_at_0[0x8]; 9036 u8 event_type[0x8]; 9037 u8 reserved_at_10[0x8]; 9038 u8 event_sub_type[0x8]; 9039 9040 u8 reserved_at_20[0xe0]; 9041 9042 union mlx5_ifc_event_auto_bits event_data; 9043 9044 u8 reserved_at_1e0[0x10]; 9045 u8 signature[0x8]; 9046 u8 reserved_at_1f8[0x7]; 9047 u8 owner[0x1]; 9048 }; 9049 9050 enum { 9051 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9052 }; 9053 9054 struct mlx5_ifc_cmd_queue_entry_bits { 9055 u8 type[0x8]; 9056 u8 reserved_at_8[0x18]; 9057 9058 u8 input_length[0x20]; 9059 9060 u8 input_mailbox_pointer_63_32[0x20]; 9061 9062 u8 input_mailbox_pointer_31_9[0x17]; 9063 u8 reserved_at_77[0x9]; 9064 9065 u8 command_input_inline_data[16][0x8]; 9066 9067 u8 command_output_inline_data[16][0x8]; 9068 9069 u8 output_mailbox_pointer_63_32[0x20]; 9070 9071 u8 output_mailbox_pointer_31_9[0x17]; 9072 u8 reserved_at_1b7[0x9]; 9073 9074 u8 output_length[0x20]; 9075 9076 u8 token[0x8]; 9077 u8 signature[0x8]; 9078 u8 reserved_at_1f0[0x8]; 9079 u8 status[0x7]; 9080 u8 ownership[0x1]; 9081 }; 9082 9083 struct mlx5_ifc_cmd_out_bits { 9084 u8 status[0x8]; 9085 u8 reserved_at_8[0x18]; 9086 9087 u8 syndrome[0x20]; 9088 9089 u8 command_output[0x20]; 9090 }; 9091 9092 struct mlx5_ifc_cmd_in_bits { 9093 u8 opcode[0x10]; 9094 u8 reserved_at_10[0x10]; 9095 9096 u8 reserved_at_20[0x10]; 9097 u8 op_mod[0x10]; 9098 9099 u8 command[0][0x20]; 9100 }; 9101 9102 struct mlx5_ifc_cmd_if_box_bits { 9103 u8 mailbox_data[512][0x8]; 9104 9105 u8 reserved_at_1000[0x180]; 9106 9107 u8 next_pointer_63_32[0x20]; 9108 9109 u8 next_pointer_31_10[0x16]; 9110 u8 reserved_at_11b6[0xa]; 9111 9112 u8 block_number[0x20]; 9113 9114 u8 reserved_at_11e0[0x8]; 9115 u8 token[0x8]; 9116 u8 ctrl_signature[0x8]; 9117 u8 signature[0x8]; 9118 }; 9119 9120 struct mlx5_ifc_mtt_bits { 9121 u8 ptag_63_32[0x20]; 9122 9123 u8 ptag_31_8[0x18]; 9124 u8 reserved_at_38[0x6]; 9125 u8 wr_en[0x1]; 9126 u8 rd_en[0x1]; 9127 }; 9128 9129 struct mlx5_ifc_query_wol_rol_out_bits { 9130 u8 status[0x8]; 9131 u8 reserved_at_8[0x18]; 9132 9133 u8 syndrome[0x20]; 9134 9135 u8 reserved_at_40[0x10]; 9136 u8 rol_mode[0x8]; 9137 u8 wol_mode[0x8]; 9138 9139 u8 reserved_at_60[0x20]; 9140 }; 9141 9142 struct mlx5_ifc_query_wol_rol_in_bits { 9143 u8 opcode[0x10]; 9144 u8 reserved_at_10[0x10]; 9145 9146 u8 reserved_at_20[0x10]; 9147 u8 op_mod[0x10]; 9148 9149 u8 reserved_at_40[0x40]; 9150 }; 9151 9152 struct mlx5_ifc_set_wol_rol_out_bits { 9153 u8 status[0x8]; 9154 u8 reserved_at_8[0x18]; 9155 9156 u8 syndrome[0x20]; 9157 9158 u8 reserved_at_40[0x40]; 9159 }; 9160 9161 struct mlx5_ifc_set_wol_rol_in_bits { 9162 u8 opcode[0x10]; 9163 u8 reserved_at_10[0x10]; 9164 9165 u8 reserved_at_20[0x10]; 9166 u8 op_mod[0x10]; 9167 9168 u8 rol_mode_valid[0x1]; 9169 u8 wol_mode_valid[0x1]; 9170 u8 reserved_at_42[0xe]; 9171 u8 rol_mode[0x8]; 9172 u8 wol_mode[0x8]; 9173 9174 u8 reserved_at_60[0x20]; 9175 }; 9176 9177 enum { 9178 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9179 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9180 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9181 }; 9182 9183 enum { 9184 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9185 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9186 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9187 }; 9188 9189 enum { 9190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9198 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9199 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9200 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9201 }; 9202 9203 struct mlx5_ifc_initial_seg_bits { 9204 u8 fw_rev_minor[0x10]; 9205 u8 fw_rev_major[0x10]; 9206 9207 u8 cmd_interface_rev[0x10]; 9208 u8 fw_rev_subminor[0x10]; 9209 9210 u8 reserved_at_40[0x40]; 9211 9212 u8 cmdq_phy_addr_63_32[0x20]; 9213 9214 u8 cmdq_phy_addr_31_12[0x14]; 9215 u8 reserved_at_b4[0x2]; 9216 u8 nic_interface[0x2]; 9217 u8 log_cmdq_size[0x4]; 9218 u8 log_cmdq_stride[0x4]; 9219 9220 u8 command_doorbell_vector[0x20]; 9221 9222 u8 reserved_at_e0[0xf00]; 9223 9224 u8 initializing[0x1]; 9225 u8 reserved_at_fe1[0x4]; 9226 u8 nic_interface_supported[0x3]; 9227 u8 embedded_cpu[0x1]; 9228 u8 reserved_at_fe9[0x17]; 9229 9230 struct mlx5_ifc_health_buffer_bits health_buffer; 9231 9232 u8 no_dram_nic_offset[0x20]; 9233 9234 u8 reserved_at_1220[0x6e40]; 9235 9236 u8 reserved_at_8060[0x1f]; 9237 u8 clear_int[0x1]; 9238 9239 u8 health_syndrome[0x8]; 9240 u8 health_counter[0x18]; 9241 9242 u8 reserved_at_80a0[0x17fc0]; 9243 }; 9244 9245 struct mlx5_ifc_mtpps_reg_bits { 9246 u8 reserved_at_0[0xc]; 9247 u8 cap_number_of_pps_pins[0x4]; 9248 u8 reserved_at_10[0x4]; 9249 u8 cap_max_num_of_pps_in_pins[0x4]; 9250 u8 reserved_at_18[0x4]; 9251 u8 cap_max_num_of_pps_out_pins[0x4]; 9252 9253 u8 reserved_at_20[0x24]; 9254 u8 cap_pin_3_mode[0x4]; 9255 u8 reserved_at_48[0x4]; 9256 u8 cap_pin_2_mode[0x4]; 9257 u8 reserved_at_50[0x4]; 9258 u8 cap_pin_1_mode[0x4]; 9259 u8 reserved_at_58[0x4]; 9260 u8 cap_pin_0_mode[0x4]; 9261 9262 u8 reserved_at_60[0x4]; 9263 u8 cap_pin_7_mode[0x4]; 9264 u8 reserved_at_68[0x4]; 9265 u8 cap_pin_6_mode[0x4]; 9266 u8 reserved_at_70[0x4]; 9267 u8 cap_pin_5_mode[0x4]; 9268 u8 reserved_at_78[0x4]; 9269 u8 cap_pin_4_mode[0x4]; 9270 9271 u8 field_select[0x20]; 9272 u8 reserved_at_a0[0x60]; 9273 9274 u8 enable[0x1]; 9275 u8 reserved_at_101[0xb]; 9276 u8 pattern[0x4]; 9277 u8 reserved_at_110[0x4]; 9278 u8 pin_mode[0x4]; 9279 u8 pin[0x8]; 9280 9281 u8 reserved_at_120[0x20]; 9282 9283 u8 time_stamp[0x40]; 9284 9285 u8 out_pulse_duration[0x10]; 9286 u8 out_periodic_adjustment[0x10]; 9287 u8 enhanced_out_periodic_adjustment[0x20]; 9288 9289 u8 reserved_at_1c0[0x20]; 9290 }; 9291 9292 struct mlx5_ifc_mtppse_reg_bits { 9293 u8 reserved_at_0[0x18]; 9294 u8 pin[0x8]; 9295 u8 event_arm[0x1]; 9296 u8 reserved_at_21[0x1b]; 9297 u8 event_generation_mode[0x4]; 9298 u8 reserved_at_40[0x40]; 9299 }; 9300 9301 struct mlx5_ifc_mcqs_reg_bits { 9302 u8 last_index_flag[0x1]; 9303 u8 reserved_at_1[0x7]; 9304 u8 fw_device[0x8]; 9305 u8 component_index[0x10]; 9306 9307 u8 reserved_at_20[0x10]; 9308 u8 identifier[0x10]; 9309 9310 u8 reserved_at_40[0x17]; 9311 u8 component_status[0x5]; 9312 u8 component_update_state[0x4]; 9313 9314 u8 last_update_state_changer_type[0x4]; 9315 u8 last_update_state_changer_host_id[0x4]; 9316 u8 reserved_at_68[0x18]; 9317 }; 9318 9319 struct mlx5_ifc_mcqi_cap_bits { 9320 u8 supported_info_bitmask[0x20]; 9321 9322 u8 component_size[0x20]; 9323 9324 u8 max_component_size[0x20]; 9325 9326 u8 log_mcda_word_size[0x4]; 9327 u8 reserved_at_64[0xc]; 9328 u8 mcda_max_write_size[0x10]; 9329 9330 u8 rd_en[0x1]; 9331 u8 reserved_at_81[0x1]; 9332 u8 match_chip_id[0x1]; 9333 u8 match_psid[0x1]; 9334 u8 check_user_timestamp[0x1]; 9335 u8 match_base_guid_mac[0x1]; 9336 u8 reserved_at_86[0x1a]; 9337 }; 9338 9339 struct mlx5_ifc_mcqi_version_bits { 9340 u8 reserved_at_0[0x2]; 9341 u8 build_time_valid[0x1]; 9342 u8 user_defined_time_valid[0x1]; 9343 u8 reserved_at_4[0x14]; 9344 u8 version_string_length[0x8]; 9345 9346 u8 version[0x20]; 9347 9348 u8 build_time[0x40]; 9349 9350 u8 user_defined_time[0x40]; 9351 9352 u8 build_tool_version[0x20]; 9353 9354 u8 reserved_at_e0[0x20]; 9355 9356 u8 version_string[92][0x8]; 9357 }; 9358 9359 struct mlx5_ifc_mcqi_activation_method_bits { 9360 u8 pending_server_ac_power_cycle[0x1]; 9361 u8 pending_server_dc_power_cycle[0x1]; 9362 u8 pending_server_reboot[0x1]; 9363 u8 pending_fw_reset[0x1]; 9364 u8 auto_activate[0x1]; 9365 u8 all_hosts_sync[0x1]; 9366 u8 device_hw_reset[0x1]; 9367 u8 reserved_at_7[0x19]; 9368 }; 9369 9370 union mlx5_ifc_mcqi_reg_data_bits { 9371 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9372 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9373 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9374 }; 9375 9376 struct mlx5_ifc_mcqi_reg_bits { 9377 u8 read_pending_component[0x1]; 9378 u8 reserved_at_1[0xf]; 9379 u8 component_index[0x10]; 9380 9381 u8 reserved_at_20[0x20]; 9382 9383 u8 reserved_at_40[0x1b]; 9384 u8 info_type[0x5]; 9385 9386 u8 info_size[0x20]; 9387 9388 u8 offset[0x20]; 9389 9390 u8 reserved_at_a0[0x10]; 9391 u8 data_size[0x10]; 9392 9393 union mlx5_ifc_mcqi_reg_data_bits data[0]; 9394 }; 9395 9396 struct mlx5_ifc_mcc_reg_bits { 9397 u8 reserved_at_0[0x4]; 9398 u8 time_elapsed_since_last_cmd[0xc]; 9399 u8 reserved_at_10[0x8]; 9400 u8 instruction[0x8]; 9401 9402 u8 reserved_at_20[0x10]; 9403 u8 component_index[0x10]; 9404 9405 u8 reserved_at_40[0x8]; 9406 u8 update_handle[0x18]; 9407 9408 u8 handle_owner_type[0x4]; 9409 u8 handle_owner_host_id[0x4]; 9410 u8 reserved_at_68[0x1]; 9411 u8 control_progress[0x7]; 9412 u8 error_code[0x8]; 9413 u8 reserved_at_78[0x4]; 9414 u8 control_state[0x4]; 9415 9416 u8 component_size[0x20]; 9417 9418 u8 reserved_at_a0[0x60]; 9419 }; 9420 9421 struct mlx5_ifc_mcda_reg_bits { 9422 u8 reserved_at_0[0x8]; 9423 u8 update_handle[0x18]; 9424 9425 u8 offset[0x20]; 9426 9427 u8 reserved_at_40[0x10]; 9428 u8 size[0x10]; 9429 9430 u8 reserved_at_60[0x20]; 9431 9432 u8 data[0][0x20]; 9433 }; 9434 9435 union mlx5_ifc_ports_control_registers_document_bits { 9436 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9437 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9438 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9439 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9440 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9441 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9442 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9443 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9444 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9445 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9446 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9447 struct mlx5_ifc_paos_reg_bits paos_reg; 9448 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9449 struct mlx5_ifc_peir_reg_bits peir_reg; 9450 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9451 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9452 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9453 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9454 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9455 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9456 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9457 struct mlx5_ifc_plib_reg_bits plib_reg; 9458 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9459 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9460 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9461 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9462 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9463 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9464 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9465 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9466 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9467 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9468 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9469 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9470 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9471 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9472 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9473 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9474 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9475 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9476 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9477 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9478 struct mlx5_ifc_pude_reg_bits pude_reg; 9479 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9480 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9481 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9482 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9483 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9484 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9485 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9486 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9487 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9488 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9489 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9490 u8 reserved_at_0[0x60e0]; 9491 }; 9492 9493 union mlx5_ifc_debug_enhancements_document_bits { 9494 struct mlx5_ifc_health_buffer_bits health_buffer; 9495 u8 reserved_at_0[0x200]; 9496 }; 9497 9498 union mlx5_ifc_uplink_pci_interface_document_bits { 9499 struct mlx5_ifc_initial_seg_bits initial_seg; 9500 u8 reserved_at_0[0x20060]; 9501 }; 9502 9503 struct mlx5_ifc_set_flow_table_root_out_bits { 9504 u8 status[0x8]; 9505 u8 reserved_at_8[0x18]; 9506 9507 u8 syndrome[0x20]; 9508 9509 u8 reserved_at_40[0x40]; 9510 }; 9511 9512 struct mlx5_ifc_set_flow_table_root_in_bits { 9513 u8 opcode[0x10]; 9514 u8 reserved_at_10[0x10]; 9515 9516 u8 reserved_at_20[0x10]; 9517 u8 op_mod[0x10]; 9518 9519 u8 other_vport[0x1]; 9520 u8 reserved_at_41[0xf]; 9521 u8 vport_number[0x10]; 9522 9523 u8 reserved_at_60[0x20]; 9524 9525 u8 table_type[0x8]; 9526 u8 reserved_at_88[0x18]; 9527 9528 u8 reserved_at_a0[0x8]; 9529 u8 table_id[0x18]; 9530 9531 u8 reserved_at_c0[0x8]; 9532 u8 underlay_qpn[0x18]; 9533 u8 reserved_at_e0[0x120]; 9534 }; 9535 9536 enum { 9537 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9538 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9539 }; 9540 9541 struct mlx5_ifc_modify_flow_table_out_bits { 9542 u8 status[0x8]; 9543 u8 reserved_at_8[0x18]; 9544 9545 u8 syndrome[0x20]; 9546 9547 u8 reserved_at_40[0x40]; 9548 }; 9549 9550 struct mlx5_ifc_modify_flow_table_in_bits { 9551 u8 opcode[0x10]; 9552 u8 reserved_at_10[0x10]; 9553 9554 u8 reserved_at_20[0x10]; 9555 u8 op_mod[0x10]; 9556 9557 u8 other_vport[0x1]; 9558 u8 reserved_at_41[0xf]; 9559 u8 vport_number[0x10]; 9560 9561 u8 reserved_at_60[0x10]; 9562 u8 modify_field_select[0x10]; 9563 9564 u8 table_type[0x8]; 9565 u8 reserved_at_88[0x18]; 9566 9567 u8 reserved_at_a0[0x8]; 9568 u8 table_id[0x18]; 9569 9570 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9571 }; 9572 9573 struct mlx5_ifc_ets_tcn_config_reg_bits { 9574 u8 g[0x1]; 9575 u8 b[0x1]; 9576 u8 r[0x1]; 9577 u8 reserved_at_3[0x9]; 9578 u8 group[0x4]; 9579 u8 reserved_at_10[0x9]; 9580 u8 bw_allocation[0x7]; 9581 9582 u8 reserved_at_20[0xc]; 9583 u8 max_bw_units[0x4]; 9584 u8 reserved_at_30[0x8]; 9585 u8 max_bw_value[0x8]; 9586 }; 9587 9588 struct mlx5_ifc_ets_global_config_reg_bits { 9589 u8 reserved_at_0[0x2]; 9590 u8 r[0x1]; 9591 u8 reserved_at_3[0x1d]; 9592 9593 u8 reserved_at_20[0xc]; 9594 u8 max_bw_units[0x4]; 9595 u8 reserved_at_30[0x8]; 9596 u8 max_bw_value[0x8]; 9597 }; 9598 9599 struct mlx5_ifc_qetc_reg_bits { 9600 u8 reserved_at_0[0x8]; 9601 u8 port_number[0x8]; 9602 u8 reserved_at_10[0x30]; 9603 9604 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9605 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9606 }; 9607 9608 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9609 u8 e[0x1]; 9610 u8 reserved_at_01[0x0b]; 9611 u8 prio[0x04]; 9612 }; 9613 9614 struct mlx5_ifc_qpdpm_reg_bits { 9615 u8 reserved_at_0[0x8]; 9616 u8 local_port[0x8]; 9617 u8 reserved_at_10[0x10]; 9618 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9619 }; 9620 9621 struct mlx5_ifc_qpts_reg_bits { 9622 u8 reserved_at_0[0x8]; 9623 u8 local_port[0x8]; 9624 u8 reserved_at_10[0x2d]; 9625 u8 trust_state[0x3]; 9626 }; 9627 9628 struct mlx5_ifc_pptb_reg_bits { 9629 u8 reserved_at_0[0x2]; 9630 u8 mm[0x2]; 9631 u8 reserved_at_4[0x4]; 9632 u8 local_port[0x8]; 9633 u8 reserved_at_10[0x6]; 9634 u8 cm[0x1]; 9635 u8 um[0x1]; 9636 u8 pm[0x8]; 9637 9638 u8 prio_x_buff[0x20]; 9639 9640 u8 pm_msb[0x8]; 9641 u8 reserved_at_48[0x10]; 9642 u8 ctrl_buff[0x4]; 9643 u8 untagged_buff[0x4]; 9644 }; 9645 9646 struct mlx5_ifc_pbmc_reg_bits { 9647 u8 reserved_at_0[0x8]; 9648 u8 local_port[0x8]; 9649 u8 reserved_at_10[0x10]; 9650 9651 u8 xoff_timer_value[0x10]; 9652 u8 xoff_refresh[0x10]; 9653 9654 u8 reserved_at_40[0x9]; 9655 u8 fullness_threshold[0x7]; 9656 u8 port_buffer_size[0x10]; 9657 9658 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9659 9660 u8 reserved_at_2e0[0x40]; 9661 }; 9662 9663 struct mlx5_ifc_qtct_reg_bits { 9664 u8 reserved_at_0[0x8]; 9665 u8 port_number[0x8]; 9666 u8 reserved_at_10[0xd]; 9667 u8 prio[0x3]; 9668 9669 u8 reserved_at_20[0x1d]; 9670 u8 tclass[0x3]; 9671 }; 9672 9673 struct mlx5_ifc_mcia_reg_bits { 9674 u8 l[0x1]; 9675 u8 reserved_at_1[0x7]; 9676 u8 module[0x8]; 9677 u8 reserved_at_10[0x8]; 9678 u8 status[0x8]; 9679 9680 u8 i2c_device_address[0x8]; 9681 u8 page_number[0x8]; 9682 u8 device_address[0x10]; 9683 9684 u8 reserved_at_40[0x10]; 9685 u8 size[0x10]; 9686 9687 u8 reserved_at_60[0x20]; 9688 9689 u8 dword_0[0x20]; 9690 u8 dword_1[0x20]; 9691 u8 dword_2[0x20]; 9692 u8 dword_3[0x20]; 9693 u8 dword_4[0x20]; 9694 u8 dword_5[0x20]; 9695 u8 dword_6[0x20]; 9696 u8 dword_7[0x20]; 9697 u8 dword_8[0x20]; 9698 u8 dword_9[0x20]; 9699 u8 dword_10[0x20]; 9700 u8 dword_11[0x20]; 9701 }; 9702 9703 struct mlx5_ifc_dcbx_param_bits { 9704 u8 dcbx_cee_cap[0x1]; 9705 u8 dcbx_ieee_cap[0x1]; 9706 u8 dcbx_standby_cap[0x1]; 9707 u8 reserved_at_3[0x5]; 9708 u8 port_number[0x8]; 9709 u8 reserved_at_10[0xa]; 9710 u8 max_application_table_size[6]; 9711 u8 reserved_at_20[0x15]; 9712 u8 version_oper[0x3]; 9713 u8 reserved_at_38[5]; 9714 u8 version_admin[0x3]; 9715 u8 willing_admin[0x1]; 9716 u8 reserved_at_41[0x3]; 9717 u8 pfc_cap_oper[0x4]; 9718 u8 reserved_at_48[0x4]; 9719 u8 pfc_cap_admin[0x4]; 9720 u8 reserved_at_50[0x4]; 9721 u8 num_of_tc_oper[0x4]; 9722 u8 reserved_at_58[0x4]; 9723 u8 num_of_tc_admin[0x4]; 9724 u8 remote_willing[0x1]; 9725 u8 reserved_at_61[3]; 9726 u8 remote_pfc_cap[4]; 9727 u8 reserved_at_68[0x14]; 9728 u8 remote_num_of_tc[0x4]; 9729 u8 reserved_at_80[0x18]; 9730 u8 error[0x8]; 9731 u8 reserved_at_a0[0x160]; 9732 }; 9733 9734 struct mlx5_ifc_lagc_bits { 9735 u8 reserved_at_0[0x1d]; 9736 u8 lag_state[0x3]; 9737 9738 u8 reserved_at_20[0x14]; 9739 u8 tx_remap_affinity_2[0x4]; 9740 u8 reserved_at_38[0x4]; 9741 u8 tx_remap_affinity_1[0x4]; 9742 }; 9743 9744 struct mlx5_ifc_create_lag_out_bits { 9745 u8 status[0x8]; 9746 u8 reserved_at_8[0x18]; 9747 9748 u8 syndrome[0x20]; 9749 9750 u8 reserved_at_40[0x40]; 9751 }; 9752 9753 struct mlx5_ifc_create_lag_in_bits { 9754 u8 opcode[0x10]; 9755 u8 reserved_at_10[0x10]; 9756 9757 u8 reserved_at_20[0x10]; 9758 u8 op_mod[0x10]; 9759 9760 struct mlx5_ifc_lagc_bits ctx; 9761 }; 9762 9763 struct mlx5_ifc_modify_lag_out_bits { 9764 u8 status[0x8]; 9765 u8 reserved_at_8[0x18]; 9766 9767 u8 syndrome[0x20]; 9768 9769 u8 reserved_at_40[0x40]; 9770 }; 9771 9772 struct mlx5_ifc_modify_lag_in_bits { 9773 u8 opcode[0x10]; 9774 u8 reserved_at_10[0x10]; 9775 9776 u8 reserved_at_20[0x10]; 9777 u8 op_mod[0x10]; 9778 9779 u8 reserved_at_40[0x20]; 9780 u8 field_select[0x20]; 9781 9782 struct mlx5_ifc_lagc_bits ctx; 9783 }; 9784 9785 struct mlx5_ifc_query_lag_out_bits { 9786 u8 status[0x8]; 9787 u8 reserved_at_8[0x18]; 9788 9789 u8 syndrome[0x20]; 9790 9791 struct mlx5_ifc_lagc_bits ctx; 9792 }; 9793 9794 struct mlx5_ifc_query_lag_in_bits { 9795 u8 opcode[0x10]; 9796 u8 reserved_at_10[0x10]; 9797 9798 u8 reserved_at_20[0x10]; 9799 u8 op_mod[0x10]; 9800 9801 u8 reserved_at_40[0x40]; 9802 }; 9803 9804 struct mlx5_ifc_destroy_lag_out_bits { 9805 u8 status[0x8]; 9806 u8 reserved_at_8[0x18]; 9807 9808 u8 syndrome[0x20]; 9809 9810 u8 reserved_at_40[0x40]; 9811 }; 9812 9813 struct mlx5_ifc_destroy_lag_in_bits { 9814 u8 opcode[0x10]; 9815 u8 reserved_at_10[0x10]; 9816 9817 u8 reserved_at_20[0x10]; 9818 u8 op_mod[0x10]; 9819 9820 u8 reserved_at_40[0x40]; 9821 }; 9822 9823 struct mlx5_ifc_create_vport_lag_out_bits { 9824 u8 status[0x8]; 9825 u8 reserved_at_8[0x18]; 9826 9827 u8 syndrome[0x20]; 9828 9829 u8 reserved_at_40[0x40]; 9830 }; 9831 9832 struct mlx5_ifc_create_vport_lag_in_bits { 9833 u8 opcode[0x10]; 9834 u8 reserved_at_10[0x10]; 9835 9836 u8 reserved_at_20[0x10]; 9837 u8 op_mod[0x10]; 9838 9839 u8 reserved_at_40[0x40]; 9840 }; 9841 9842 struct mlx5_ifc_destroy_vport_lag_out_bits { 9843 u8 status[0x8]; 9844 u8 reserved_at_8[0x18]; 9845 9846 u8 syndrome[0x20]; 9847 9848 u8 reserved_at_40[0x40]; 9849 }; 9850 9851 struct mlx5_ifc_destroy_vport_lag_in_bits { 9852 u8 opcode[0x10]; 9853 u8 reserved_at_10[0x10]; 9854 9855 u8 reserved_at_20[0x10]; 9856 u8 op_mod[0x10]; 9857 9858 u8 reserved_at_40[0x40]; 9859 }; 9860 9861 struct mlx5_ifc_alloc_memic_in_bits { 9862 u8 opcode[0x10]; 9863 u8 reserved_at_10[0x10]; 9864 9865 u8 reserved_at_20[0x10]; 9866 u8 op_mod[0x10]; 9867 9868 u8 reserved_at_30[0x20]; 9869 9870 u8 reserved_at_40[0x18]; 9871 u8 log_memic_addr_alignment[0x8]; 9872 9873 u8 range_start_addr[0x40]; 9874 9875 u8 range_size[0x20]; 9876 9877 u8 memic_size[0x20]; 9878 }; 9879 9880 struct mlx5_ifc_alloc_memic_out_bits { 9881 u8 status[0x8]; 9882 u8 reserved_at_8[0x18]; 9883 9884 u8 syndrome[0x20]; 9885 9886 u8 memic_start_addr[0x40]; 9887 }; 9888 9889 struct mlx5_ifc_dealloc_memic_in_bits { 9890 u8 opcode[0x10]; 9891 u8 reserved_at_10[0x10]; 9892 9893 u8 reserved_at_20[0x10]; 9894 u8 op_mod[0x10]; 9895 9896 u8 reserved_at_40[0x40]; 9897 9898 u8 memic_start_addr[0x40]; 9899 9900 u8 memic_size[0x20]; 9901 9902 u8 reserved_at_e0[0x20]; 9903 }; 9904 9905 struct mlx5_ifc_dealloc_memic_out_bits { 9906 u8 status[0x8]; 9907 u8 reserved_at_8[0x18]; 9908 9909 u8 syndrome[0x20]; 9910 9911 u8 reserved_at_40[0x40]; 9912 }; 9913 9914 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9915 u8 opcode[0x10]; 9916 u8 uid[0x10]; 9917 9918 u8 vhca_tunnel_id[0x10]; 9919 u8 obj_type[0x10]; 9920 9921 u8 obj_id[0x20]; 9922 9923 u8 reserved_at_60[0x20]; 9924 }; 9925 9926 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9927 u8 status[0x8]; 9928 u8 reserved_at_8[0x18]; 9929 9930 u8 syndrome[0x20]; 9931 9932 u8 obj_id[0x20]; 9933 9934 u8 reserved_at_60[0x20]; 9935 }; 9936 9937 struct mlx5_ifc_umem_bits { 9938 u8 reserved_at_0[0x80]; 9939 9940 u8 reserved_at_80[0x1b]; 9941 u8 log_page_size[0x5]; 9942 9943 u8 page_offset[0x20]; 9944 9945 u8 num_of_mtt[0x40]; 9946 9947 struct mlx5_ifc_mtt_bits mtt[0]; 9948 }; 9949 9950 struct mlx5_ifc_uctx_bits { 9951 u8 cap[0x20]; 9952 9953 u8 reserved_at_20[0x160]; 9954 }; 9955 9956 struct mlx5_ifc_sw_icm_bits { 9957 u8 modify_field_select[0x40]; 9958 9959 u8 reserved_at_40[0x18]; 9960 u8 log_sw_icm_size[0x8]; 9961 9962 u8 reserved_at_60[0x20]; 9963 9964 u8 sw_icm_start_addr[0x40]; 9965 9966 u8 reserved_at_c0[0x140]; 9967 }; 9968 9969 struct mlx5_ifc_geneve_tlv_option_bits { 9970 u8 modify_field_select[0x40]; 9971 9972 u8 reserved_at_40[0x18]; 9973 u8 geneve_option_fte_index[0x8]; 9974 9975 u8 option_class[0x10]; 9976 u8 option_type[0x8]; 9977 u8 reserved_at_78[0x3]; 9978 u8 option_data_length[0x5]; 9979 9980 u8 reserved_at_80[0x180]; 9981 }; 9982 9983 struct mlx5_ifc_create_umem_in_bits { 9984 u8 opcode[0x10]; 9985 u8 uid[0x10]; 9986 9987 u8 reserved_at_20[0x10]; 9988 u8 op_mod[0x10]; 9989 9990 u8 reserved_at_40[0x40]; 9991 9992 struct mlx5_ifc_umem_bits umem; 9993 }; 9994 9995 struct mlx5_ifc_create_uctx_in_bits { 9996 u8 opcode[0x10]; 9997 u8 reserved_at_10[0x10]; 9998 9999 u8 reserved_at_20[0x10]; 10000 u8 op_mod[0x10]; 10001 10002 u8 reserved_at_40[0x40]; 10003 10004 struct mlx5_ifc_uctx_bits uctx; 10005 }; 10006 10007 struct mlx5_ifc_destroy_uctx_in_bits { 10008 u8 opcode[0x10]; 10009 u8 reserved_at_10[0x10]; 10010 10011 u8 reserved_at_20[0x10]; 10012 u8 op_mod[0x10]; 10013 10014 u8 reserved_at_40[0x10]; 10015 u8 uid[0x10]; 10016 10017 u8 reserved_at_60[0x20]; 10018 }; 10019 10020 struct mlx5_ifc_create_sw_icm_in_bits { 10021 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10022 struct mlx5_ifc_sw_icm_bits sw_icm; 10023 }; 10024 10025 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10026 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10027 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10028 }; 10029 10030 struct mlx5_ifc_mtrc_string_db_param_bits { 10031 u8 string_db_base_address[0x20]; 10032 10033 u8 reserved_at_20[0x8]; 10034 u8 string_db_size[0x18]; 10035 }; 10036 10037 struct mlx5_ifc_mtrc_cap_bits { 10038 u8 trace_owner[0x1]; 10039 u8 trace_to_memory[0x1]; 10040 u8 reserved_at_2[0x4]; 10041 u8 trc_ver[0x2]; 10042 u8 reserved_at_8[0x14]; 10043 u8 num_string_db[0x4]; 10044 10045 u8 first_string_trace[0x8]; 10046 u8 num_string_trace[0x8]; 10047 u8 reserved_at_30[0x28]; 10048 10049 u8 log_max_trace_buffer_size[0x8]; 10050 10051 u8 reserved_at_60[0x20]; 10052 10053 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10054 10055 u8 reserved_at_280[0x180]; 10056 }; 10057 10058 struct mlx5_ifc_mtrc_conf_bits { 10059 u8 reserved_at_0[0x1c]; 10060 u8 trace_mode[0x4]; 10061 u8 reserved_at_20[0x18]; 10062 u8 log_trace_buffer_size[0x8]; 10063 u8 trace_mkey[0x20]; 10064 u8 reserved_at_60[0x3a0]; 10065 }; 10066 10067 struct mlx5_ifc_mtrc_stdb_bits { 10068 u8 string_db_index[0x4]; 10069 u8 reserved_at_4[0x4]; 10070 u8 read_size[0x18]; 10071 u8 start_offset[0x20]; 10072 u8 string_db_data[0]; 10073 }; 10074 10075 struct mlx5_ifc_mtrc_ctrl_bits { 10076 u8 trace_status[0x2]; 10077 u8 reserved_at_2[0x2]; 10078 u8 arm_event[0x1]; 10079 u8 reserved_at_5[0xb]; 10080 u8 modify_field_select[0x10]; 10081 u8 reserved_at_20[0x2b]; 10082 u8 current_timestamp52_32[0x15]; 10083 u8 current_timestamp31_0[0x20]; 10084 u8 reserved_at_80[0x180]; 10085 }; 10086 10087 struct mlx5_ifc_host_params_context_bits { 10088 u8 host_number[0x8]; 10089 u8 reserved_at_8[0x7]; 10090 u8 host_pf_disabled[0x1]; 10091 u8 host_num_of_vfs[0x10]; 10092 10093 u8 host_total_vfs[0x10]; 10094 u8 host_pci_bus[0x10]; 10095 10096 u8 reserved_at_40[0x10]; 10097 u8 host_pci_device[0x10]; 10098 10099 u8 reserved_at_60[0x10]; 10100 u8 host_pci_function[0x10]; 10101 10102 u8 reserved_at_80[0x180]; 10103 }; 10104 10105 struct mlx5_ifc_query_esw_functions_in_bits { 10106 u8 opcode[0x10]; 10107 u8 reserved_at_10[0x10]; 10108 10109 u8 reserved_at_20[0x10]; 10110 u8 op_mod[0x10]; 10111 10112 u8 reserved_at_40[0x40]; 10113 }; 10114 10115 struct mlx5_ifc_query_esw_functions_out_bits { 10116 u8 status[0x8]; 10117 u8 reserved_at_8[0x18]; 10118 10119 u8 syndrome[0x20]; 10120 10121 u8 reserved_at_40[0x40]; 10122 10123 struct mlx5_ifc_host_params_context_bits host_params_context; 10124 10125 u8 reserved_at_280[0x180]; 10126 u8 host_sf_enable[0][0x40]; 10127 }; 10128 10129 struct mlx5_ifc_sf_partition_bits { 10130 u8 reserved_at_0[0x10]; 10131 u8 log_num_sf[0x8]; 10132 u8 log_sf_bar_size[0x8]; 10133 }; 10134 10135 struct mlx5_ifc_query_sf_partitions_out_bits { 10136 u8 status[0x8]; 10137 u8 reserved_at_8[0x18]; 10138 10139 u8 syndrome[0x20]; 10140 10141 u8 reserved_at_40[0x18]; 10142 u8 num_sf_partitions[0x8]; 10143 10144 u8 reserved_at_60[0x20]; 10145 10146 struct mlx5_ifc_sf_partition_bits sf_partition[0]; 10147 }; 10148 10149 struct mlx5_ifc_query_sf_partitions_in_bits { 10150 u8 opcode[0x10]; 10151 u8 reserved_at_10[0x10]; 10152 10153 u8 reserved_at_20[0x10]; 10154 u8 op_mod[0x10]; 10155 10156 u8 reserved_at_40[0x40]; 10157 }; 10158 10159 struct mlx5_ifc_dealloc_sf_out_bits { 10160 u8 status[0x8]; 10161 u8 reserved_at_8[0x18]; 10162 10163 u8 syndrome[0x20]; 10164 10165 u8 reserved_at_40[0x40]; 10166 }; 10167 10168 struct mlx5_ifc_dealloc_sf_in_bits { 10169 u8 opcode[0x10]; 10170 u8 reserved_at_10[0x10]; 10171 10172 u8 reserved_at_20[0x10]; 10173 u8 op_mod[0x10]; 10174 10175 u8 reserved_at_40[0x10]; 10176 u8 function_id[0x10]; 10177 10178 u8 reserved_at_60[0x20]; 10179 }; 10180 10181 struct mlx5_ifc_alloc_sf_out_bits { 10182 u8 status[0x8]; 10183 u8 reserved_at_8[0x18]; 10184 10185 u8 syndrome[0x20]; 10186 10187 u8 reserved_at_40[0x40]; 10188 }; 10189 10190 struct mlx5_ifc_alloc_sf_in_bits { 10191 u8 opcode[0x10]; 10192 u8 reserved_at_10[0x10]; 10193 10194 u8 reserved_at_20[0x10]; 10195 u8 op_mod[0x10]; 10196 10197 u8 reserved_at_40[0x10]; 10198 u8 function_id[0x10]; 10199 10200 u8 reserved_at_60[0x20]; 10201 }; 10202 10203 struct mlx5_ifc_affiliated_event_header_bits { 10204 u8 reserved_at_0[0x10]; 10205 u8 obj_type[0x10]; 10206 10207 u8 obj_id[0x20]; 10208 }; 10209 10210 enum { 10211 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10212 }; 10213 10214 enum { 10215 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10216 }; 10217 10218 struct mlx5_ifc_encryption_key_obj_bits { 10219 u8 modify_field_select[0x40]; 10220 10221 u8 reserved_at_40[0x14]; 10222 u8 key_size[0x4]; 10223 u8 reserved_at_58[0x4]; 10224 u8 key_type[0x4]; 10225 10226 u8 reserved_at_60[0x8]; 10227 u8 pd[0x18]; 10228 10229 u8 reserved_at_80[0x180]; 10230 u8 key[8][0x20]; 10231 10232 u8 reserved_at_300[0x500]; 10233 }; 10234 10235 struct mlx5_ifc_create_encryption_key_in_bits { 10236 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10237 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10238 }; 10239 10240 enum { 10241 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10242 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10243 }; 10244 10245 enum { 10246 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 10247 }; 10248 10249 struct mlx5_ifc_tls_static_params_bits { 10250 u8 const_2[0x2]; 10251 u8 tls_version[0x4]; 10252 u8 const_1[0x2]; 10253 u8 reserved_at_8[0x14]; 10254 u8 encryption_standard[0x4]; 10255 10256 u8 reserved_at_20[0x20]; 10257 10258 u8 initial_record_number[0x40]; 10259 10260 u8 resync_tcp_sn[0x20]; 10261 10262 u8 gcm_iv[0x20]; 10263 10264 u8 implicit_iv[0x40]; 10265 10266 u8 reserved_at_100[0x8]; 10267 u8 dek_index[0x18]; 10268 10269 u8 reserved_at_120[0xe0]; 10270 }; 10271 10272 struct mlx5_ifc_tls_progress_params_bits { 10273 u8 reserved_at_0[0x8]; 10274 u8 tisn[0x18]; 10275 10276 u8 next_record_tcp_sn[0x20]; 10277 10278 u8 hw_resync_tcp_sn[0x20]; 10279 10280 u8 record_tracker_state[0x2]; 10281 u8 auth_state[0x2]; 10282 u8 reserved_at_64[0x4]; 10283 u8 hw_offset_record_number[0x18]; 10284 }; 10285 10286 #endif /* MLX5_IFC_H */ 10287