1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 82 }; 83 84 enum { 85 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 86 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 87 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 88 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 89 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 90 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 96 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 99 MLX5_OBJ_TYPE_MKEY = 0xff01, 100 MLX5_OBJ_TYPE_QP = 0xff02, 101 MLX5_OBJ_TYPE_PSV = 0xff03, 102 MLX5_OBJ_TYPE_RMP = 0xff04, 103 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 104 MLX5_OBJ_TYPE_RQ = 0xff06, 105 MLX5_OBJ_TYPE_SQ = 0xff07, 106 MLX5_OBJ_TYPE_TIR = 0xff08, 107 MLX5_OBJ_TYPE_TIS = 0xff09, 108 MLX5_OBJ_TYPE_DCT = 0xff0a, 109 MLX5_OBJ_TYPE_XRQ = 0xff0b, 110 MLX5_OBJ_TYPE_RQT = 0xff0e, 111 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 112 MLX5_OBJ_TYPE_CQ = 0xff10, 113 }; 114 115 enum { 116 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 117 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 118 MLX5_CMD_OP_INIT_HCA = 0x102, 119 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 120 MLX5_CMD_OP_ENABLE_HCA = 0x104, 121 MLX5_CMD_OP_DISABLE_HCA = 0x105, 122 MLX5_CMD_OP_QUERY_PAGES = 0x107, 123 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 124 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 125 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 126 MLX5_CMD_OP_SET_ISSI = 0x10b, 127 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 128 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 129 MLX5_CMD_OP_ALLOC_SF = 0x113, 130 MLX5_CMD_OP_DEALLOC_SF = 0x114, 131 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 132 MLX5_CMD_OP_RESUME_VHCA = 0x116, 133 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 134 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 135 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 136 MLX5_CMD_OP_CREATE_MKEY = 0x200, 137 MLX5_CMD_OP_QUERY_MKEY = 0x201, 138 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 139 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 140 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 141 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 142 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 143 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 144 MLX5_CMD_OP_CREATE_EQ = 0x301, 145 MLX5_CMD_OP_DESTROY_EQ = 0x302, 146 MLX5_CMD_OP_QUERY_EQ = 0x303, 147 MLX5_CMD_OP_GEN_EQE = 0x304, 148 MLX5_CMD_OP_CREATE_CQ = 0x400, 149 MLX5_CMD_OP_DESTROY_CQ = 0x401, 150 MLX5_CMD_OP_QUERY_CQ = 0x402, 151 MLX5_CMD_OP_MODIFY_CQ = 0x403, 152 MLX5_CMD_OP_CREATE_QP = 0x500, 153 MLX5_CMD_OP_DESTROY_QP = 0x501, 154 MLX5_CMD_OP_RST2INIT_QP = 0x502, 155 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 156 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 157 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 158 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 159 MLX5_CMD_OP_2ERR_QP = 0x507, 160 MLX5_CMD_OP_2RST_QP = 0x50a, 161 MLX5_CMD_OP_QUERY_QP = 0x50b, 162 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 163 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 164 MLX5_CMD_OP_CREATE_PSV = 0x600, 165 MLX5_CMD_OP_DESTROY_PSV = 0x601, 166 MLX5_CMD_OP_CREATE_SRQ = 0x700, 167 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 168 MLX5_CMD_OP_QUERY_SRQ = 0x702, 169 MLX5_CMD_OP_ARM_RQ = 0x703, 170 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 171 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 172 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 173 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 174 MLX5_CMD_OP_CREATE_DCT = 0x710, 175 MLX5_CMD_OP_DESTROY_DCT = 0x711, 176 MLX5_CMD_OP_DRAIN_DCT = 0x712, 177 MLX5_CMD_OP_QUERY_DCT = 0x713, 178 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 179 MLX5_CMD_OP_CREATE_XRQ = 0x717, 180 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 181 MLX5_CMD_OP_QUERY_XRQ = 0x719, 182 MLX5_CMD_OP_ARM_XRQ = 0x71a, 183 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 184 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 185 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 186 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 187 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 188 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 189 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 190 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 191 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 192 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 193 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 194 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 195 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 196 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 198 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 200 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 201 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 202 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 203 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 204 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 205 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 206 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 207 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 208 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 209 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 210 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 211 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 212 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 213 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 214 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 215 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 216 MLX5_CMD_OP_ALLOC_PD = 0x800, 217 MLX5_CMD_OP_DEALLOC_PD = 0x801, 218 MLX5_CMD_OP_ALLOC_UAR = 0x802, 219 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 220 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 221 MLX5_CMD_OP_ACCESS_REG = 0x805, 222 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 223 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 224 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 225 MLX5_CMD_OP_MAD_IFC = 0x50d, 226 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 227 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 228 MLX5_CMD_OP_NOP = 0x80d, 229 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 230 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 231 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 232 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 233 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 234 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 235 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 236 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 237 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 238 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 239 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 240 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 241 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 242 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 243 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 244 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 245 MLX5_CMD_OP_CREATE_LAG = 0x840, 246 MLX5_CMD_OP_MODIFY_LAG = 0x841, 247 MLX5_CMD_OP_QUERY_LAG = 0x842, 248 MLX5_CMD_OP_DESTROY_LAG = 0x843, 249 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 250 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 251 MLX5_CMD_OP_CREATE_TIR = 0x900, 252 MLX5_CMD_OP_MODIFY_TIR = 0x901, 253 MLX5_CMD_OP_DESTROY_TIR = 0x902, 254 MLX5_CMD_OP_QUERY_TIR = 0x903, 255 MLX5_CMD_OP_CREATE_SQ = 0x904, 256 MLX5_CMD_OP_MODIFY_SQ = 0x905, 257 MLX5_CMD_OP_DESTROY_SQ = 0x906, 258 MLX5_CMD_OP_QUERY_SQ = 0x907, 259 MLX5_CMD_OP_CREATE_RQ = 0x908, 260 MLX5_CMD_OP_MODIFY_RQ = 0x909, 261 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 262 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 263 MLX5_CMD_OP_QUERY_RQ = 0x90b, 264 MLX5_CMD_OP_CREATE_RMP = 0x90c, 265 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 266 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 267 MLX5_CMD_OP_QUERY_RMP = 0x90f, 268 MLX5_CMD_OP_CREATE_TIS = 0x912, 269 MLX5_CMD_OP_MODIFY_TIS = 0x913, 270 MLX5_CMD_OP_DESTROY_TIS = 0x914, 271 MLX5_CMD_OP_QUERY_TIS = 0x915, 272 MLX5_CMD_OP_CREATE_RQT = 0x916, 273 MLX5_CMD_OP_MODIFY_RQT = 0x917, 274 MLX5_CMD_OP_DESTROY_RQT = 0x918, 275 MLX5_CMD_OP_QUERY_RQT = 0x919, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 277 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 278 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 279 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 280 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 281 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 282 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 284 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 285 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 286 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 287 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 288 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 289 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 290 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 291 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 292 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 293 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 294 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 295 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 296 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 297 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 298 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 299 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 301 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 302 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 303 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 304 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 305 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 306 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 307 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 308 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 309 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 310 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 311 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 312 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 313 MLX5_CMD_OP_MAX 314 }; 315 316 /* Valid range for general commands that don't work over an object */ 317 enum { 318 MLX5_CMD_OP_GENERAL_START = 0xb00, 319 MLX5_CMD_OP_GENERAL_END = 0xd00, 320 }; 321 322 enum { 323 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 324 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 325 }; 326 327 enum { 328 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 329 }; 330 331 struct mlx5_ifc_flow_table_fields_supported_bits { 332 u8 outer_dmac[0x1]; 333 u8 outer_smac[0x1]; 334 u8 outer_ether_type[0x1]; 335 u8 outer_ip_version[0x1]; 336 u8 outer_first_prio[0x1]; 337 u8 outer_first_cfi[0x1]; 338 u8 outer_first_vid[0x1]; 339 u8 outer_ipv4_ttl[0x1]; 340 u8 outer_second_prio[0x1]; 341 u8 outer_second_cfi[0x1]; 342 u8 outer_second_vid[0x1]; 343 u8 reserved_at_b[0x1]; 344 u8 outer_sip[0x1]; 345 u8 outer_dip[0x1]; 346 u8 outer_frag[0x1]; 347 u8 outer_ip_protocol[0x1]; 348 u8 outer_ip_ecn[0x1]; 349 u8 outer_ip_dscp[0x1]; 350 u8 outer_udp_sport[0x1]; 351 u8 outer_udp_dport[0x1]; 352 u8 outer_tcp_sport[0x1]; 353 u8 outer_tcp_dport[0x1]; 354 u8 outer_tcp_flags[0x1]; 355 u8 outer_gre_protocol[0x1]; 356 u8 outer_gre_key[0x1]; 357 u8 outer_vxlan_vni[0x1]; 358 u8 outer_geneve_vni[0x1]; 359 u8 outer_geneve_oam[0x1]; 360 u8 outer_geneve_protocol_type[0x1]; 361 u8 outer_geneve_opt_len[0x1]; 362 u8 source_vhca_port[0x1]; 363 u8 source_eswitch_port[0x1]; 364 365 u8 inner_dmac[0x1]; 366 u8 inner_smac[0x1]; 367 u8 inner_ether_type[0x1]; 368 u8 inner_ip_version[0x1]; 369 u8 inner_first_prio[0x1]; 370 u8 inner_first_cfi[0x1]; 371 u8 inner_first_vid[0x1]; 372 u8 reserved_at_27[0x1]; 373 u8 inner_second_prio[0x1]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0x1]; 376 u8 reserved_at_2b[0x1]; 377 u8 inner_sip[0x1]; 378 u8 inner_dip[0x1]; 379 u8 inner_frag[0x1]; 380 u8 inner_ip_protocol[0x1]; 381 u8 inner_ip_ecn[0x1]; 382 u8 inner_ip_dscp[0x1]; 383 u8 inner_udp_sport[0x1]; 384 u8 inner_udp_dport[0x1]; 385 u8 inner_tcp_sport[0x1]; 386 u8 inner_tcp_dport[0x1]; 387 u8 inner_tcp_flags[0x1]; 388 u8 reserved_at_37[0x9]; 389 390 u8 geneve_tlv_option_0_data[0x1]; 391 u8 geneve_tlv_option_0_exist[0x1]; 392 u8 reserved_at_42[0x3]; 393 u8 outer_first_mpls_over_udp[0x4]; 394 u8 outer_first_mpls_over_gre[0x4]; 395 u8 inner_first_mpls[0x4]; 396 u8 outer_first_mpls[0x4]; 397 u8 reserved_at_55[0x2]; 398 u8 outer_esp_spi[0x1]; 399 u8 reserved_at_58[0x2]; 400 u8 bth_dst_qp[0x1]; 401 u8 reserved_at_5b[0x5]; 402 403 u8 reserved_at_60[0x18]; 404 u8 metadata_reg_c_7[0x1]; 405 u8 metadata_reg_c_6[0x1]; 406 u8 metadata_reg_c_5[0x1]; 407 u8 metadata_reg_c_4[0x1]; 408 u8 metadata_reg_c_3[0x1]; 409 u8 metadata_reg_c_2[0x1]; 410 u8 metadata_reg_c_1[0x1]; 411 u8 metadata_reg_c_0[0x1]; 412 }; 413 414 /* Table 2170 - Flow Table Fields Supported 2 Format */ 415 struct mlx5_ifc_flow_table_fields_supported_2_bits { 416 u8 reserved_at_0[0xe]; 417 u8 bth_opcode[0x1]; 418 u8 reserved_at_f[0x1]; 419 u8 tunnel_header_0_1[0x1]; 420 u8 reserved_at_11[0xf]; 421 422 u8 reserved_at_20[0x60]; 423 }; 424 425 struct mlx5_ifc_flow_table_prop_layout_bits { 426 u8 ft_support[0x1]; 427 u8 reserved_at_1[0x1]; 428 u8 flow_counter[0x1]; 429 u8 flow_modify_en[0x1]; 430 u8 modify_root[0x1]; 431 u8 identified_miss_table_mode[0x1]; 432 u8 flow_table_modify[0x1]; 433 u8 reformat[0x1]; 434 u8 decap[0x1]; 435 u8 reserved_at_9[0x1]; 436 u8 pop_vlan[0x1]; 437 u8 push_vlan[0x1]; 438 u8 reserved_at_c[0x1]; 439 u8 pop_vlan_2[0x1]; 440 u8 push_vlan_2[0x1]; 441 u8 reformat_and_vlan_action[0x1]; 442 u8 reserved_at_10[0x1]; 443 u8 sw_owner[0x1]; 444 u8 reformat_l3_tunnel_to_l2[0x1]; 445 u8 reformat_l2_to_l3_tunnel[0x1]; 446 u8 reformat_and_modify_action[0x1]; 447 u8 ignore_flow_level[0x1]; 448 u8 reserved_at_16[0x1]; 449 u8 table_miss_action_domain[0x1]; 450 u8 termination_table[0x1]; 451 u8 reformat_and_fwd_to_table[0x1]; 452 u8 reserved_at_1a[0x2]; 453 u8 ipsec_encrypt[0x1]; 454 u8 ipsec_decrypt[0x1]; 455 u8 sw_owner_v2[0x1]; 456 u8 reserved_at_1f[0x1]; 457 458 u8 termination_table_raw_traffic[0x1]; 459 u8 reserved_at_21[0x1]; 460 u8 log_max_ft_size[0x6]; 461 u8 log_max_modify_header_context[0x8]; 462 u8 max_modify_header_actions[0x8]; 463 u8 max_ft_level[0x8]; 464 465 u8 reformat_add_esp_trasport[0x1]; 466 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 467 u8 reserved_at_42[0x1]; 468 u8 reformat_del_esp_trasport[0x1]; 469 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 470 u8 reserved_at_45[0x1]; 471 u8 execute_aso[0x1]; 472 u8 reserved_at_47[0x19]; 473 474 u8 reserved_at_60[0x2]; 475 u8 reformat_insert[0x1]; 476 u8 reformat_remove[0x1]; 477 u8 macsec_encrypt[0x1]; 478 u8 macsec_decrypt[0x1]; 479 u8 reserved_at_66[0x2]; 480 u8 reformat_add_macsec[0x1]; 481 u8 reformat_remove_macsec[0x1]; 482 u8 reserved_at_6a[0xe]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_at_6[0x1a]; 507 }; 508 509 struct mlx5_ifc_ipv4_layout_bits { 510 u8 reserved_at_0[0x60]; 511 512 u8 ipv4[0x20]; 513 }; 514 515 struct mlx5_ifc_ipv6_layout_bits { 516 u8 ipv6[16][0x8]; 517 }; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 520 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 521 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 522 u8 reserved_at_0[0x80]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 526 u8 smac_47_16[0x20]; 527 528 u8 smac_15_0[0x10]; 529 u8 ethertype[0x10]; 530 531 u8 dmac_47_16[0x20]; 532 533 u8 dmac_15_0[0x10]; 534 u8 first_prio[0x3]; 535 u8 first_cfi[0x1]; 536 u8 first_vid[0xc]; 537 538 u8 ip_protocol[0x8]; 539 u8 ip_dscp[0x6]; 540 u8 ip_ecn[0x2]; 541 u8 cvlan_tag[0x1]; 542 u8 svlan_tag[0x1]; 543 u8 frag[0x1]; 544 u8 ip_version[0x4]; 545 u8 tcp_flags[0x9]; 546 547 u8 tcp_sport[0x10]; 548 u8 tcp_dport[0x10]; 549 550 u8 reserved_at_c0[0x10]; 551 u8 ipv4_ihl[0x4]; 552 u8 reserved_at_c4[0x4]; 553 554 u8 ttl_hoplimit[0x8]; 555 556 u8 udp_sport[0x10]; 557 u8 udp_dport[0x10]; 558 559 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 560 561 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 562 }; 563 564 struct mlx5_ifc_nvgre_key_bits { 565 u8 hi[0x18]; 566 u8 lo[0x8]; 567 }; 568 569 union mlx5_ifc_gre_key_bits { 570 struct mlx5_ifc_nvgre_key_bits nvgre; 571 u8 key[0x20]; 572 }; 573 574 struct mlx5_ifc_fte_match_set_misc_bits { 575 u8 gre_c_present[0x1]; 576 u8 reserved_at_1[0x1]; 577 u8 gre_k_present[0x1]; 578 u8 gre_s_present[0x1]; 579 u8 source_vhca_port[0x4]; 580 u8 source_sqn[0x18]; 581 582 u8 source_eswitch_owner_vhca_id[0x10]; 583 u8 source_port[0x10]; 584 585 u8 outer_second_prio[0x3]; 586 u8 outer_second_cfi[0x1]; 587 u8 outer_second_vid[0xc]; 588 u8 inner_second_prio[0x3]; 589 u8 inner_second_cfi[0x1]; 590 u8 inner_second_vid[0xc]; 591 592 u8 outer_second_cvlan_tag[0x1]; 593 u8 inner_second_cvlan_tag[0x1]; 594 u8 outer_second_svlan_tag[0x1]; 595 u8 inner_second_svlan_tag[0x1]; 596 u8 reserved_at_64[0xc]; 597 u8 gre_protocol[0x10]; 598 599 union mlx5_ifc_gre_key_bits gre_key; 600 601 u8 vxlan_vni[0x18]; 602 u8 bth_opcode[0x8]; 603 604 u8 geneve_vni[0x18]; 605 u8 reserved_at_d8[0x6]; 606 u8 geneve_tlv_option_0_exist[0x1]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_at_e0[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_at_100[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_120[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_at_140[0x8]; 620 u8 bth_dst_qp[0x18]; 621 u8 reserved_at_160[0x20]; 622 u8 outer_esp_spi[0x20]; 623 u8 reserved_at_1a0[0x60]; 624 }; 625 626 struct mlx5_ifc_fte_match_mpls_bits { 627 u8 mpls_label[0x14]; 628 u8 mpls_exp[0x3]; 629 u8 mpls_s_bos[0x1]; 630 u8 mpls_ttl[0x8]; 631 }; 632 633 struct mlx5_ifc_fte_match_set_misc2_bits { 634 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 635 636 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 637 638 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 639 640 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 641 642 u8 metadata_reg_c_7[0x20]; 643 644 u8 metadata_reg_c_6[0x20]; 645 646 u8 metadata_reg_c_5[0x20]; 647 648 u8 metadata_reg_c_4[0x20]; 649 650 u8 metadata_reg_c_3[0x20]; 651 652 u8 metadata_reg_c_2[0x20]; 653 654 u8 metadata_reg_c_1[0x20]; 655 656 u8 metadata_reg_c_0[0x20]; 657 658 u8 metadata_reg_a[0x20]; 659 660 u8 reserved_at_1a0[0x8]; 661 662 u8 macsec_syndrome[0x8]; 663 u8 ipsec_syndrome[0x8]; 664 u8 reserved_at_1b8[0x8]; 665 666 u8 reserved_at_1c0[0x40]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc3_bits { 670 u8 inner_tcp_seq_num[0x20]; 671 672 u8 outer_tcp_seq_num[0x20]; 673 674 u8 inner_tcp_ack_num[0x20]; 675 676 u8 outer_tcp_ack_num[0x20]; 677 678 u8 reserved_at_80[0x8]; 679 u8 outer_vxlan_gpe_vni[0x18]; 680 681 u8 outer_vxlan_gpe_next_protocol[0x8]; 682 u8 outer_vxlan_gpe_flags[0x8]; 683 u8 reserved_at_b0[0x10]; 684 685 u8 icmp_header_data[0x20]; 686 687 u8 icmpv6_header_data[0x20]; 688 689 u8 icmp_type[0x8]; 690 u8 icmp_code[0x8]; 691 u8 icmpv6_type[0x8]; 692 u8 icmpv6_code[0x8]; 693 694 u8 geneve_tlv_option_0_data[0x20]; 695 696 u8 gtpu_teid[0x20]; 697 698 u8 gtpu_msg_type[0x8]; 699 u8 gtpu_msg_flags[0x8]; 700 u8 reserved_at_170[0x10]; 701 702 u8 gtpu_dw_2[0x20]; 703 704 u8 gtpu_first_ext_dw_0[0x20]; 705 706 u8 gtpu_dw_0[0x20]; 707 708 u8 reserved_at_1e0[0x20]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc4_bits { 712 u8 prog_sample_field_value_0[0x20]; 713 714 u8 prog_sample_field_id_0[0x20]; 715 716 u8 prog_sample_field_value_1[0x20]; 717 718 u8 prog_sample_field_id_1[0x20]; 719 720 u8 prog_sample_field_value_2[0x20]; 721 722 u8 prog_sample_field_id_2[0x20]; 723 724 u8 prog_sample_field_value_3[0x20]; 725 726 u8 prog_sample_field_id_3[0x20]; 727 728 u8 reserved_at_100[0x100]; 729 }; 730 731 struct mlx5_ifc_fte_match_set_misc5_bits { 732 u8 macsec_tag_0[0x20]; 733 734 u8 macsec_tag_1[0x20]; 735 736 u8 macsec_tag_2[0x20]; 737 738 u8 macsec_tag_3[0x20]; 739 740 u8 tunnel_header_0[0x20]; 741 742 u8 tunnel_header_1[0x20]; 743 744 u8 tunnel_header_2[0x20]; 745 746 u8 tunnel_header_3[0x20]; 747 748 u8 reserved_at_100[0x100]; 749 }; 750 751 struct mlx5_ifc_cmd_pas_bits { 752 u8 pa_h[0x20]; 753 754 u8 pa_l[0x14]; 755 u8 reserved_at_34[0xc]; 756 }; 757 758 struct mlx5_ifc_uint64_bits { 759 u8 hi[0x20]; 760 761 u8 lo[0x20]; 762 }; 763 764 enum { 765 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 766 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 767 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 768 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 769 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 770 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 771 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 772 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 773 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 774 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 775 }; 776 777 struct mlx5_ifc_ads_bits { 778 u8 fl[0x1]; 779 u8 free_ar[0x1]; 780 u8 reserved_at_2[0xe]; 781 u8 pkey_index[0x10]; 782 783 u8 reserved_at_20[0x8]; 784 u8 grh[0x1]; 785 u8 mlid[0x7]; 786 u8 rlid[0x10]; 787 788 u8 ack_timeout[0x5]; 789 u8 reserved_at_45[0x3]; 790 u8 src_addr_index[0x8]; 791 u8 reserved_at_50[0x4]; 792 u8 stat_rate[0x4]; 793 u8 hop_limit[0x8]; 794 795 u8 reserved_at_60[0x4]; 796 u8 tclass[0x8]; 797 u8 flow_label[0x14]; 798 799 u8 rgid_rip[16][0x8]; 800 801 u8 reserved_at_100[0x4]; 802 u8 f_dscp[0x1]; 803 u8 f_ecn[0x1]; 804 u8 reserved_at_106[0x1]; 805 u8 f_eth_prio[0x1]; 806 u8 ecn[0x2]; 807 u8 dscp[0x6]; 808 u8 udp_sport[0x10]; 809 810 u8 dei_cfi[0x1]; 811 u8 eth_prio[0x3]; 812 u8 sl[0x4]; 813 u8 vhca_port_num[0x8]; 814 u8 rmac_47_32[0x10]; 815 816 u8 rmac_31_0[0x20]; 817 }; 818 819 struct mlx5_ifc_flow_table_nic_cap_bits { 820 u8 nic_rx_multi_path_tirs[0x1]; 821 u8 nic_rx_multi_path_tirs_fts[0x1]; 822 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 823 u8 reserved_at_3[0x4]; 824 u8 sw_owner_reformat_supported[0x1]; 825 u8 reserved_at_8[0x18]; 826 827 u8 encap_general_header[0x1]; 828 u8 reserved_at_21[0xa]; 829 u8 log_max_packet_reformat_context[0x5]; 830 u8 reserved_at_30[0x6]; 831 u8 max_encap_header_size[0xa]; 832 u8 reserved_at_40[0x1c0]; 833 834 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 835 836 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 837 838 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 839 840 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 841 842 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 843 844 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 845 846 u8 reserved_at_e00[0x700]; 847 848 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 849 850 u8 reserved_at_1580[0x280]; 851 852 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 853 854 u8 reserved_at_1880[0x780]; 855 856 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 857 858 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 859 860 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 861 862 u8 reserved_at_20c0[0x5f40]; 863 }; 864 865 struct mlx5_ifc_port_selection_cap_bits { 866 u8 reserved_at_0[0x10]; 867 u8 port_select_flow_table[0x1]; 868 u8 reserved_at_11[0x1]; 869 u8 port_select_flow_table_bypass[0x1]; 870 u8 reserved_at_13[0xd]; 871 872 u8 reserved_at_20[0x1e0]; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 875 876 u8 reserved_at_400[0x7c00]; 877 }; 878 879 enum { 880 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 881 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 882 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 883 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 884 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 885 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 886 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 887 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 888 }; 889 890 struct mlx5_ifc_flow_table_eswitch_cap_bits { 891 u8 fdb_to_vport_reg_c_id[0x8]; 892 u8 reserved_at_8[0x5]; 893 u8 fdb_uplink_hairpin[0x1]; 894 u8 fdb_multi_path_any_table_limit_regc[0x1]; 895 u8 reserved_at_f[0x3]; 896 u8 fdb_multi_path_any_table[0x1]; 897 u8 reserved_at_13[0x2]; 898 u8 fdb_modify_header_fwd_to_table[0x1]; 899 u8 fdb_ipv4_ttl_modify[0x1]; 900 u8 flow_source[0x1]; 901 u8 reserved_at_18[0x2]; 902 u8 multi_fdb_encap[0x1]; 903 u8 egress_acl_forward_to_vport[0x1]; 904 u8 fdb_multi_path_to_table[0x1]; 905 u8 reserved_at_1d[0x3]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 910 911 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 912 913 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 914 915 u8 reserved_at_800[0xC00]; 916 917 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 918 919 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 920 921 u8 reserved_at_1500[0x300]; 922 923 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 924 925 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 926 927 u8 sw_steering_uplink_icm_address_rx[0x40]; 928 929 u8 sw_steering_uplink_icm_address_tx[0x40]; 930 931 u8 reserved_at_1900[0x6700]; 932 }; 933 934 enum { 935 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 936 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 937 }; 938 939 struct mlx5_ifc_e_switch_cap_bits { 940 u8 vport_svlan_strip[0x1]; 941 u8 vport_cvlan_strip[0x1]; 942 u8 vport_svlan_insert[0x1]; 943 u8 vport_cvlan_insert_if_not_exist[0x1]; 944 u8 vport_cvlan_insert_overwrite[0x1]; 945 u8 reserved_at_5[0x1]; 946 u8 vport_cvlan_insert_always[0x1]; 947 u8 esw_shared_ingress_acl[0x1]; 948 u8 esw_uplink_ingress_acl[0x1]; 949 u8 root_ft_on_other_esw[0x1]; 950 u8 reserved_at_a[0xf]; 951 u8 esw_functions_changed[0x1]; 952 u8 reserved_at_1a[0x1]; 953 u8 ecpf_vport_exists[0x1]; 954 u8 counter_eswitch_affinity[0x1]; 955 u8 merged_eswitch[0x1]; 956 u8 nic_vport_node_guid_modify[0x1]; 957 u8 nic_vport_port_guid_modify[0x1]; 958 959 u8 vxlan_encap_decap[0x1]; 960 u8 nvgre_encap_decap[0x1]; 961 u8 reserved_at_22[0x1]; 962 u8 log_max_fdb_encap_uplink[0x5]; 963 u8 reserved_at_21[0x3]; 964 u8 log_max_packet_reformat_context[0x5]; 965 u8 reserved_2b[0x6]; 966 u8 max_encap_header_size[0xa]; 967 968 u8 reserved_at_40[0xb]; 969 u8 log_max_esw_sf[0x5]; 970 u8 esw_sf_base_id[0x10]; 971 972 u8 reserved_at_60[0x7a0]; 973 974 }; 975 976 struct mlx5_ifc_qos_cap_bits { 977 u8 packet_pacing[0x1]; 978 u8 esw_scheduling[0x1]; 979 u8 esw_bw_share[0x1]; 980 u8 esw_rate_limit[0x1]; 981 u8 reserved_at_4[0x1]; 982 u8 packet_pacing_burst_bound[0x1]; 983 u8 packet_pacing_typical_size[0x1]; 984 u8 reserved_at_7[0x1]; 985 u8 nic_sq_scheduling[0x1]; 986 u8 nic_bw_share[0x1]; 987 u8 nic_rate_limit[0x1]; 988 u8 packet_pacing_uid[0x1]; 989 u8 log_esw_max_sched_depth[0x4]; 990 u8 reserved_at_10[0x10]; 991 992 u8 reserved_at_20[0xb]; 993 u8 log_max_qos_nic_queue_group[0x5]; 994 u8 reserved_at_30[0x10]; 995 996 u8 packet_pacing_max_rate[0x20]; 997 998 u8 packet_pacing_min_rate[0x20]; 999 1000 u8 reserved_at_80[0x10]; 1001 u8 packet_pacing_rate_table_size[0x10]; 1002 1003 u8 esw_element_type[0x10]; 1004 u8 esw_tsar_type[0x10]; 1005 1006 u8 reserved_at_c0[0x10]; 1007 u8 max_qos_para_vport[0x10]; 1008 1009 u8 max_tsar_bw_share[0x20]; 1010 1011 u8 reserved_at_100[0x20]; 1012 1013 u8 reserved_at_120[0x3]; 1014 u8 log_meter_aso_granularity[0x5]; 1015 u8 reserved_at_128[0x3]; 1016 u8 log_meter_aso_max_alloc[0x5]; 1017 u8 reserved_at_130[0x3]; 1018 u8 log_max_num_meter_aso[0x5]; 1019 u8 reserved_at_138[0x8]; 1020 1021 u8 reserved_at_140[0x6c0]; 1022 }; 1023 1024 struct mlx5_ifc_debug_cap_bits { 1025 u8 core_dump_general[0x1]; 1026 u8 core_dump_qp[0x1]; 1027 u8 reserved_at_2[0x7]; 1028 u8 resource_dump[0x1]; 1029 u8 reserved_at_a[0x16]; 1030 1031 u8 reserved_at_20[0x2]; 1032 u8 stall_detect[0x1]; 1033 u8 reserved_at_23[0x1d]; 1034 1035 u8 reserved_at_40[0x7c0]; 1036 }; 1037 1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1039 u8 csum_cap[0x1]; 1040 u8 vlan_cap[0x1]; 1041 u8 lro_cap[0x1]; 1042 u8 lro_psh_flag[0x1]; 1043 u8 lro_time_stamp[0x1]; 1044 u8 reserved_at_5[0x2]; 1045 u8 wqe_vlan_insert[0x1]; 1046 u8 self_lb_en_modifiable[0x1]; 1047 u8 reserved_at_9[0x2]; 1048 u8 max_lso_cap[0x5]; 1049 u8 multi_pkt_send_wqe[0x2]; 1050 u8 wqe_inline_mode[0x2]; 1051 u8 rss_ind_tbl_cap[0x4]; 1052 u8 reg_umr_sq[0x1]; 1053 u8 scatter_fcs[0x1]; 1054 u8 enhanced_multi_pkt_send_wqe[0x1]; 1055 u8 tunnel_lso_const_out_ip_id[0x1]; 1056 u8 tunnel_lro_gre[0x1]; 1057 u8 tunnel_lro_vxlan[0x1]; 1058 u8 tunnel_stateless_gre[0x1]; 1059 u8 tunnel_stateless_vxlan[0x1]; 1060 1061 u8 swp[0x1]; 1062 u8 swp_csum[0x1]; 1063 u8 swp_lso[0x1]; 1064 u8 cqe_checksum_full[0x1]; 1065 u8 tunnel_stateless_geneve_tx[0x1]; 1066 u8 tunnel_stateless_mpls_over_udp[0x1]; 1067 u8 tunnel_stateless_mpls_over_gre[0x1]; 1068 u8 tunnel_stateless_vxlan_gpe[0x1]; 1069 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1070 u8 tunnel_stateless_ip_over_ip[0x1]; 1071 u8 insert_trailer[0x1]; 1072 u8 reserved_at_2b[0x1]; 1073 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1074 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1075 u8 reserved_at_2e[0x2]; 1076 u8 max_vxlan_udp_ports[0x8]; 1077 u8 reserved_at_38[0x6]; 1078 u8 max_geneve_opt_len[0x1]; 1079 u8 tunnel_stateless_geneve_rx[0x1]; 1080 1081 u8 reserved_at_40[0x10]; 1082 u8 lro_min_mss_size[0x10]; 1083 1084 u8 reserved_at_60[0x120]; 1085 1086 u8 lro_timer_supported_periods[4][0x20]; 1087 1088 u8 reserved_at_200[0x600]; 1089 }; 1090 1091 enum { 1092 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1093 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1094 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1095 }; 1096 1097 struct mlx5_ifc_roce_cap_bits { 1098 u8 roce_apm[0x1]; 1099 u8 reserved_at_1[0x3]; 1100 u8 sw_r_roce_src_udp_port[0x1]; 1101 u8 fl_rc_qp_when_roce_disabled[0x1]; 1102 u8 fl_rc_qp_when_roce_enabled[0x1]; 1103 u8 reserved_at_7[0x1]; 1104 u8 qp_ooo_transmit_default[0x1]; 1105 u8 reserved_at_9[0x15]; 1106 u8 qp_ts_format[0x2]; 1107 1108 u8 reserved_at_20[0x60]; 1109 1110 u8 reserved_at_80[0xc]; 1111 u8 l3_type[0x4]; 1112 u8 reserved_at_90[0x8]; 1113 u8 roce_version[0x8]; 1114 1115 u8 reserved_at_a0[0x10]; 1116 u8 r_roce_dest_udp_port[0x10]; 1117 1118 u8 r_roce_max_src_udp_port[0x10]; 1119 u8 r_roce_min_src_udp_port[0x10]; 1120 1121 u8 reserved_at_e0[0x10]; 1122 u8 roce_address_table_size[0x10]; 1123 1124 u8 reserved_at_100[0x700]; 1125 }; 1126 1127 struct mlx5_ifc_sync_steering_in_bits { 1128 u8 opcode[0x10]; 1129 u8 uid[0x10]; 1130 1131 u8 reserved_at_20[0x10]; 1132 u8 op_mod[0x10]; 1133 1134 u8 reserved_at_40[0xc0]; 1135 }; 1136 1137 struct mlx5_ifc_sync_steering_out_bits { 1138 u8 status[0x8]; 1139 u8 reserved_at_8[0x18]; 1140 1141 u8 syndrome[0x20]; 1142 1143 u8 reserved_at_40[0x40]; 1144 }; 1145 1146 struct mlx5_ifc_sync_crypto_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0x20]; 1154 1155 u8 reserved_at_60[0x10]; 1156 u8 crypto_type[0x10]; 1157 1158 u8 reserved_at_80[0x80]; 1159 }; 1160 1161 struct mlx5_ifc_sync_crypto_out_bits { 1162 u8 status[0x8]; 1163 u8 reserved_at_8[0x18]; 1164 1165 u8 syndrome[0x20]; 1166 1167 u8 reserved_at_40[0x40]; 1168 }; 1169 1170 struct mlx5_ifc_device_mem_cap_bits { 1171 u8 memic[0x1]; 1172 u8 reserved_at_1[0x1f]; 1173 1174 u8 reserved_at_20[0xb]; 1175 u8 log_min_memic_alloc_size[0x5]; 1176 u8 reserved_at_30[0x8]; 1177 u8 log_max_memic_addr_alignment[0x8]; 1178 1179 u8 memic_bar_start_addr[0x40]; 1180 1181 u8 memic_bar_size[0x20]; 1182 1183 u8 max_memic_size[0x20]; 1184 1185 u8 steering_sw_icm_start_address[0x40]; 1186 1187 u8 reserved_at_100[0x8]; 1188 u8 log_header_modify_sw_icm_size[0x8]; 1189 u8 reserved_at_110[0x2]; 1190 u8 log_sw_icm_alloc_granularity[0x6]; 1191 u8 log_steering_sw_icm_size[0x8]; 1192 1193 u8 reserved_at_120[0x18]; 1194 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1195 1196 u8 header_modify_sw_icm_start_address[0x40]; 1197 1198 u8 reserved_at_180[0x40]; 1199 1200 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1201 1202 u8 memic_operations[0x20]; 1203 1204 u8 reserved_at_220[0x5e0]; 1205 }; 1206 1207 struct mlx5_ifc_device_event_cap_bits { 1208 u8 user_affiliated_events[4][0x40]; 1209 1210 u8 user_unaffiliated_events[4][0x40]; 1211 }; 1212 1213 struct mlx5_ifc_virtio_emulation_cap_bits { 1214 u8 desc_tunnel_offload_type[0x1]; 1215 u8 eth_frame_offload_type[0x1]; 1216 u8 virtio_version_1_0[0x1]; 1217 u8 device_features_bits_mask[0xd]; 1218 u8 event_mode[0x8]; 1219 u8 virtio_queue_type[0x8]; 1220 1221 u8 max_tunnel_desc[0x10]; 1222 u8 reserved_at_30[0x3]; 1223 u8 log_doorbell_stride[0x5]; 1224 u8 reserved_at_38[0x3]; 1225 u8 log_doorbell_bar_size[0x5]; 1226 1227 u8 doorbell_bar_offset[0x40]; 1228 1229 u8 max_emulated_devices[0x8]; 1230 u8 max_num_virtio_queues[0x18]; 1231 1232 u8 reserved_at_a0[0x60]; 1233 1234 u8 umem_1_buffer_param_a[0x20]; 1235 1236 u8 umem_1_buffer_param_b[0x20]; 1237 1238 u8 umem_2_buffer_param_a[0x20]; 1239 1240 u8 umem_2_buffer_param_b[0x20]; 1241 1242 u8 umem_3_buffer_param_a[0x20]; 1243 1244 u8 umem_3_buffer_param_b[0x20]; 1245 1246 u8 reserved_at_1c0[0x640]; 1247 }; 1248 1249 enum { 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1257 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1258 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1259 }; 1260 1261 enum { 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1271 }; 1272 1273 struct mlx5_ifc_atomic_caps_bits { 1274 u8 reserved_at_0[0x40]; 1275 1276 u8 atomic_req_8B_endianness_mode[0x2]; 1277 u8 reserved_at_42[0x4]; 1278 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1279 1280 u8 reserved_at_47[0x19]; 1281 1282 u8 reserved_at_60[0x20]; 1283 1284 u8 reserved_at_80[0x10]; 1285 u8 atomic_operations[0x10]; 1286 1287 u8 reserved_at_a0[0x10]; 1288 u8 atomic_size_qp[0x10]; 1289 1290 u8 reserved_at_c0[0x10]; 1291 u8 atomic_size_dc[0x10]; 1292 1293 u8 reserved_at_e0[0x720]; 1294 }; 1295 1296 struct mlx5_ifc_odp_cap_bits { 1297 u8 reserved_at_0[0x40]; 1298 1299 u8 sig[0x1]; 1300 u8 reserved_at_41[0x1f]; 1301 1302 u8 reserved_at_60[0x20]; 1303 1304 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1305 1306 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1307 1308 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1309 1310 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1311 1312 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1313 1314 u8 reserved_at_120[0x6E0]; 1315 }; 1316 1317 struct mlx5_ifc_calc_op { 1318 u8 reserved_at_0[0x10]; 1319 u8 reserved_at_10[0x9]; 1320 u8 op_swap_endianness[0x1]; 1321 u8 op_min[0x1]; 1322 u8 op_xor[0x1]; 1323 u8 op_or[0x1]; 1324 u8 op_and[0x1]; 1325 u8 op_max[0x1]; 1326 u8 op_add[0x1]; 1327 }; 1328 1329 struct mlx5_ifc_vector_calc_cap_bits { 1330 u8 calc_matrix[0x1]; 1331 u8 reserved_at_1[0x1f]; 1332 u8 reserved_at_20[0x8]; 1333 u8 max_vec_count[0x8]; 1334 u8 reserved_at_30[0xd]; 1335 u8 max_chunk_size[0x3]; 1336 struct mlx5_ifc_calc_op calc0; 1337 struct mlx5_ifc_calc_op calc1; 1338 struct mlx5_ifc_calc_op calc2; 1339 struct mlx5_ifc_calc_op calc3; 1340 1341 u8 reserved_at_c0[0x720]; 1342 }; 1343 1344 struct mlx5_ifc_tls_cap_bits { 1345 u8 tls_1_2_aes_gcm_128[0x1]; 1346 u8 tls_1_3_aes_gcm_128[0x1]; 1347 u8 tls_1_2_aes_gcm_256[0x1]; 1348 u8 tls_1_3_aes_gcm_256[0x1]; 1349 u8 reserved_at_4[0x1c]; 1350 1351 u8 reserved_at_20[0x7e0]; 1352 }; 1353 1354 struct mlx5_ifc_ipsec_cap_bits { 1355 u8 ipsec_full_offload[0x1]; 1356 u8 ipsec_crypto_offload[0x1]; 1357 u8 ipsec_esn[0x1]; 1358 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1359 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1360 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1361 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1362 u8 reserved_at_7[0x4]; 1363 u8 log_max_ipsec_offload[0x5]; 1364 u8 reserved_at_10[0x10]; 1365 1366 u8 min_log_ipsec_full_replay_window[0x8]; 1367 u8 max_log_ipsec_full_replay_window[0x8]; 1368 u8 reserved_at_30[0x7d0]; 1369 }; 1370 1371 struct mlx5_ifc_macsec_cap_bits { 1372 u8 macsec_epn[0x1]; 1373 u8 reserved_at_1[0x2]; 1374 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1375 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1376 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1377 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1378 u8 reserved_at_7[0x4]; 1379 u8 log_max_macsec_offload[0x5]; 1380 u8 reserved_at_10[0x10]; 1381 1382 u8 min_log_macsec_full_replay_window[0x8]; 1383 u8 max_log_macsec_full_replay_window[0x8]; 1384 u8 reserved_at_30[0x10]; 1385 1386 u8 reserved_at_40[0x7c0]; 1387 }; 1388 1389 enum { 1390 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1391 MLX5_WQ_TYPE_CYCLIC = 0x1, 1392 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1393 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1394 }; 1395 1396 enum { 1397 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1398 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1399 }; 1400 1401 enum { 1402 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1403 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1404 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1405 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1407 }; 1408 1409 enum { 1410 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1411 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1412 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1413 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1416 }; 1417 1418 enum { 1419 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1420 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1425 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1426 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1427 }; 1428 1429 enum { 1430 MLX5_CAP_PORT_TYPE_IB = 0x0, 1431 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1436 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1437 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1438 }; 1439 1440 enum { 1441 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1442 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1443 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1444 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1445 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1446 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1447 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1448 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1449 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1450 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1451 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1452 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1453 }; 1454 1455 enum { 1456 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1457 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1458 }; 1459 1460 #define MLX5_FC_BULK_SIZE_FACTOR 128 1461 1462 enum mlx5_fc_bulk_alloc_bitmask { 1463 MLX5_FC_BULK_128 = (1 << 0), 1464 MLX5_FC_BULK_256 = (1 << 1), 1465 MLX5_FC_BULK_512 = (1 << 2), 1466 MLX5_FC_BULK_1024 = (1 << 3), 1467 MLX5_FC_BULK_2048 = (1 << 4), 1468 MLX5_FC_BULK_4096 = (1 << 5), 1469 MLX5_FC_BULK_8192 = (1 << 6), 1470 MLX5_FC_BULK_16384 = (1 << 7), 1471 }; 1472 1473 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1474 1475 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1476 1477 enum { 1478 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1479 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1480 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1481 }; 1482 1483 struct mlx5_ifc_cmd_hca_cap_bits { 1484 u8 reserved_at_0[0x10]; 1485 u8 shared_object_to_user_object_allowed[0x1]; 1486 u8 reserved_at_13[0xe]; 1487 u8 vhca_resource_manager[0x1]; 1488 1489 u8 hca_cap_2[0x1]; 1490 u8 create_lag_when_not_master_up[0x1]; 1491 u8 dtor[0x1]; 1492 u8 event_on_vhca_state_teardown_request[0x1]; 1493 u8 event_on_vhca_state_in_use[0x1]; 1494 u8 event_on_vhca_state_active[0x1]; 1495 u8 event_on_vhca_state_allocated[0x1]; 1496 u8 event_on_vhca_state_invalid[0x1]; 1497 u8 reserved_at_28[0x8]; 1498 u8 vhca_id[0x10]; 1499 1500 u8 reserved_at_40[0x40]; 1501 1502 u8 log_max_srq_sz[0x8]; 1503 u8 log_max_qp_sz[0x8]; 1504 u8 event_cap[0x1]; 1505 u8 reserved_at_91[0x2]; 1506 u8 isolate_vl_tc_new[0x1]; 1507 u8 reserved_at_94[0x4]; 1508 u8 prio_tag_required[0x1]; 1509 u8 reserved_at_99[0x2]; 1510 u8 log_max_qp[0x5]; 1511 1512 u8 reserved_at_a0[0x3]; 1513 u8 ece_support[0x1]; 1514 u8 reserved_at_a4[0x5]; 1515 u8 reg_c_preserve[0x1]; 1516 u8 reserved_at_aa[0x1]; 1517 u8 log_max_srq[0x5]; 1518 u8 reserved_at_b0[0x1]; 1519 u8 uplink_follow[0x1]; 1520 u8 ts_cqe_to_dest_cqn[0x1]; 1521 u8 reserved_at_b3[0x6]; 1522 u8 go_back_n[0x1]; 1523 u8 shampo[0x1]; 1524 u8 reserved_at_bb[0x5]; 1525 1526 u8 max_sgl_for_optimized_performance[0x8]; 1527 u8 log_max_cq_sz[0x8]; 1528 u8 relaxed_ordering_write_umr[0x1]; 1529 u8 relaxed_ordering_read_umr[0x1]; 1530 u8 reserved_at_d2[0x7]; 1531 u8 virtio_net_device_emualtion_manager[0x1]; 1532 u8 virtio_blk_device_emualtion_manager[0x1]; 1533 u8 log_max_cq[0x5]; 1534 1535 u8 log_max_eq_sz[0x8]; 1536 u8 relaxed_ordering_write[0x1]; 1537 u8 relaxed_ordering_read_pci_enabled[0x1]; 1538 u8 log_max_mkey[0x6]; 1539 u8 reserved_at_f0[0x6]; 1540 u8 terminate_scatter_list_mkey[0x1]; 1541 u8 repeated_mkey[0x1]; 1542 u8 dump_fill_mkey[0x1]; 1543 u8 reserved_at_f9[0x2]; 1544 u8 fast_teardown[0x1]; 1545 u8 log_max_eq[0x4]; 1546 1547 u8 max_indirection[0x8]; 1548 u8 fixed_buffer_size[0x1]; 1549 u8 log_max_mrw_sz[0x7]; 1550 u8 force_teardown[0x1]; 1551 u8 reserved_at_111[0x1]; 1552 u8 log_max_bsf_list_size[0x6]; 1553 u8 umr_extended_translation_offset[0x1]; 1554 u8 null_mkey[0x1]; 1555 u8 log_max_klm_list_size[0x6]; 1556 1557 u8 reserved_at_120[0x2]; 1558 u8 qpc_extension[0x1]; 1559 u8 reserved_at_123[0x7]; 1560 u8 log_max_ra_req_dc[0x6]; 1561 u8 reserved_at_130[0x2]; 1562 u8 eth_wqe_too_small[0x1]; 1563 u8 reserved_at_133[0x6]; 1564 u8 vnic_env_cq_overrun[0x1]; 1565 u8 log_max_ra_res_dc[0x6]; 1566 1567 u8 reserved_at_140[0x5]; 1568 u8 release_all_pages[0x1]; 1569 u8 must_not_use[0x1]; 1570 u8 reserved_at_147[0x2]; 1571 u8 roce_accl[0x1]; 1572 u8 log_max_ra_req_qp[0x6]; 1573 u8 reserved_at_150[0xa]; 1574 u8 log_max_ra_res_qp[0x6]; 1575 1576 u8 end_pad[0x1]; 1577 u8 cc_query_allowed[0x1]; 1578 u8 cc_modify_allowed[0x1]; 1579 u8 start_pad[0x1]; 1580 u8 cache_line_128byte[0x1]; 1581 u8 reserved_at_165[0x4]; 1582 u8 rts2rts_qp_counters_set_id[0x1]; 1583 u8 reserved_at_16a[0x2]; 1584 u8 vnic_env_int_rq_oob[0x1]; 1585 u8 sbcam_reg[0x1]; 1586 u8 reserved_at_16e[0x1]; 1587 u8 qcam_reg[0x1]; 1588 u8 gid_table_size[0x10]; 1589 1590 u8 out_of_seq_cnt[0x1]; 1591 u8 vport_counters[0x1]; 1592 u8 retransmission_q_counters[0x1]; 1593 u8 debug[0x1]; 1594 u8 modify_rq_counter_set_id[0x1]; 1595 u8 rq_delay_drop[0x1]; 1596 u8 max_qp_cnt[0xa]; 1597 u8 pkey_table_size[0x10]; 1598 1599 u8 vport_group_manager[0x1]; 1600 u8 vhca_group_manager[0x1]; 1601 u8 ib_virt[0x1]; 1602 u8 eth_virt[0x1]; 1603 u8 vnic_env_queue_counters[0x1]; 1604 u8 ets[0x1]; 1605 u8 nic_flow_table[0x1]; 1606 u8 eswitch_manager[0x1]; 1607 u8 device_memory[0x1]; 1608 u8 mcam_reg[0x1]; 1609 u8 pcam_reg[0x1]; 1610 u8 local_ca_ack_delay[0x5]; 1611 u8 port_module_event[0x1]; 1612 u8 enhanced_error_q_counters[0x1]; 1613 u8 ports_check[0x1]; 1614 u8 reserved_at_1b3[0x1]; 1615 u8 disable_link_up[0x1]; 1616 u8 beacon_led[0x1]; 1617 u8 port_type[0x2]; 1618 u8 num_ports[0x8]; 1619 1620 u8 reserved_at_1c0[0x1]; 1621 u8 pps[0x1]; 1622 u8 pps_modify[0x1]; 1623 u8 log_max_msg[0x5]; 1624 u8 reserved_at_1c8[0x4]; 1625 u8 max_tc[0x4]; 1626 u8 temp_warn_event[0x1]; 1627 u8 dcbx[0x1]; 1628 u8 general_notification_event[0x1]; 1629 u8 reserved_at_1d3[0x2]; 1630 u8 fpga[0x1]; 1631 u8 rol_s[0x1]; 1632 u8 rol_g[0x1]; 1633 u8 reserved_at_1d8[0x1]; 1634 u8 wol_s[0x1]; 1635 u8 wol_g[0x1]; 1636 u8 wol_a[0x1]; 1637 u8 wol_b[0x1]; 1638 u8 wol_m[0x1]; 1639 u8 wol_u[0x1]; 1640 u8 wol_p[0x1]; 1641 1642 u8 stat_rate_support[0x10]; 1643 u8 reserved_at_1f0[0x1]; 1644 u8 pci_sync_for_fw_update_event[0x1]; 1645 u8 reserved_at_1f2[0x6]; 1646 u8 init2_lag_tx_port_affinity[0x1]; 1647 u8 reserved_at_1fa[0x3]; 1648 u8 cqe_version[0x4]; 1649 1650 u8 compact_address_vector[0x1]; 1651 u8 striding_rq[0x1]; 1652 u8 reserved_at_202[0x1]; 1653 u8 ipoib_enhanced_offloads[0x1]; 1654 u8 ipoib_basic_offloads[0x1]; 1655 u8 reserved_at_205[0x1]; 1656 u8 repeated_block_disabled[0x1]; 1657 u8 umr_modify_entity_size_disabled[0x1]; 1658 u8 umr_modify_atomic_disabled[0x1]; 1659 u8 umr_indirect_mkey_disabled[0x1]; 1660 u8 umr_fence[0x2]; 1661 u8 dc_req_scat_data_cqe[0x1]; 1662 u8 reserved_at_20d[0x2]; 1663 u8 drain_sigerr[0x1]; 1664 u8 cmdif_checksum[0x2]; 1665 u8 sigerr_cqe[0x1]; 1666 u8 reserved_at_213[0x1]; 1667 u8 wq_signature[0x1]; 1668 u8 sctr_data_cqe[0x1]; 1669 u8 reserved_at_216[0x1]; 1670 u8 sho[0x1]; 1671 u8 tph[0x1]; 1672 u8 rf[0x1]; 1673 u8 dct[0x1]; 1674 u8 qos[0x1]; 1675 u8 eth_net_offloads[0x1]; 1676 u8 roce[0x1]; 1677 u8 atomic[0x1]; 1678 u8 reserved_at_21f[0x1]; 1679 1680 u8 cq_oi[0x1]; 1681 u8 cq_resize[0x1]; 1682 u8 cq_moderation[0x1]; 1683 u8 reserved_at_223[0x3]; 1684 u8 cq_eq_remap[0x1]; 1685 u8 pg[0x1]; 1686 u8 block_lb_mc[0x1]; 1687 u8 reserved_at_229[0x1]; 1688 u8 scqe_break_moderation[0x1]; 1689 u8 cq_period_start_from_cqe[0x1]; 1690 u8 cd[0x1]; 1691 u8 reserved_at_22d[0x1]; 1692 u8 apm[0x1]; 1693 u8 vector_calc[0x1]; 1694 u8 umr_ptr_rlky[0x1]; 1695 u8 imaicl[0x1]; 1696 u8 qp_packet_based[0x1]; 1697 u8 reserved_at_233[0x3]; 1698 u8 qkv[0x1]; 1699 u8 pkv[0x1]; 1700 u8 set_deth_sqpn[0x1]; 1701 u8 reserved_at_239[0x3]; 1702 u8 xrc[0x1]; 1703 u8 ud[0x1]; 1704 u8 uc[0x1]; 1705 u8 rc[0x1]; 1706 1707 u8 uar_4k[0x1]; 1708 u8 reserved_at_241[0x9]; 1709 u8 uar_sz[0x6]; 1710 u8 port_selection_cap[0x1]; 1711 u8 reserved_at_248[0x1]; 1712 u8 umem_uid_0[0x1]; 1713 u8 reserved_at_250[0x5]; 1714 u8 log_pg_sz[0x8]; 1715 1716 u8 bf[0x1]; 1717 u8 driver_version[0x1]; 1718 u8 pad_tx_eth_packet[0x1]; 1719 u8 reserved_at_263[0x3]; 1720 u8 mkey_by_name[0x1]; 1721 u8 reserved_at_267[0x4]; 1722 1723 u8 log_bf_reg_size[0x5]; 1724 1725 u8 reserved_at_270[0x3]; 1726 u8 qp_error_syndrome[0x1]; 1727 u8 reserved_at_274[0x2]; 1728 u8 lag_dct[0x2]; 1729 u8 lag_tx_port_affinity[0x1]; 1730 u8 lag_native_fdb_selection[0x1]; 1731 u8 reserved_at_27a[0x1]; 1732 u8 lag_master[0x1]; 1733 u8 num_lag_ports[0x4]; 1734 1735 u8 reserved_at_280[0x10]; 1736 u8 max_wqe_sz_sq[0x10]; 1737 1738 u8 reserved_at_2a0[0x10]; 1739 u8 max_wqe_sz_rq[0x10]; 1740 1741 u8 max_flow_counter_31_16[0x10]; 1742 u8 max_wqe_sz_sq_dc[0x10]; 1743 1744 u8 reserved_at_2e0[0x7]; 1745 u8 max_qp_mcg[0x19]; 1746 1747 u8 reserved_at_300[0x10]; 1748 u8 flow_counter_bulk_alloc[0x8]; 1749 u8 log_max_mcg[0x8]; 1750 1751 u8 reserved_at_320[0x3]; 1752 u8 log_max_transport_domain[0x5]; 1753 u8 reserved_at_328[0x2]; 1754 u8 relaxed_ordering_read[0x1]; 1755 u8 log_max_pd[0x5]; 1756 u8 reserved_at_330[0x9]; 1757 u8 q_counter_aggregation[0x1]; 1758 u8 q_counter_other_vport[0x1]; 1759 u8 log_max_xrcd[0x5]; 1760 1761 u8 nic_receive_steering_discard[0x1]; 1762 u8 receive_discard_vport_down[0x1]; 1763 u8 transmit_discard_vport_down[0x1]; 1764 u8 eq_overrun_count[0x1]; 1765 u8 reserved_at_344[0x1]; 1766 u8 invalid_command_count[0x1]; 1767 u8 quota_exceeded_count[0x1]; 1768 u8 reserved_at_347[0x1]; 1769 u8 log_max_flow_counter_bulk[0x8]; 1770 u8 max_flow_counter_15_0[0x10]; 1771 1772 1773 u8 reserved_at_360[0x3]; 1774 u8 log_max_rq[0x5]; 1775 u8 reserved_at_368[0x3]; 1776 u8 log_max_sq[0x5]; 1777 u8 reserved_at_370[0x3]; 1778 u8 log_max_tir[0x5]; 1779 u8 reserved_at_378[0x3]; 1780 u8 log_max_tis[0x5]; 1781 1782 u8 basic_cyclic_rcv_wqe[0x1]; 1783 u8 reserved_at_381[0x2]; 1784 u8 log_max_rmp[0x5]; 1785 u8 reserved_at_388[0x3]; 1786 u8 log_max_rqt[0x5]; 1787 u8 reserved_at_390[0x3]; 1788 u8 log_max_rqt_size[0x5]; 1789 u8 reserved_at_398[0x3]; 1790 u8 log_max_tis_per_sq[0x5]; 1791 1792 u8 ext_stride_num_range[0x1]; 1793 u8 roce_rw_supported[0x1]; 1794 u8 log_max_current_uc_list_wr_supported[0x1]; 1795 u8 log_max_stride_sz_rq[0x5]; 1796 u8 reserved_at_3a8[0x3]; 1797 u8 log_min_stride_sz_rq[0x5]; 1798 u8 reserved_at_3b0[0x3]; 1799 u8 log_max_stride_sz_sq[0x5]; 1800 u8 reserved_at_3b8[0x3]; 1801 u8 log_min_stride_sz_sq[0x5]; 1802 1803 u8 hairpin[0x1]; 1804 u8 reserved_at_3c1[0x2]; 1805 u8 log_max_hairpin_queues[0x5]; 1806 u8 reserved_at_3c8[0x3]; 1807 u8 log_max_hairpin_wq_data_sz[0x5]; 1808 u8 reserved_at_3d0[0x3]; 1809 u8 log_max_hairpin_num_packets[0x5]; 1810 u8 reserved_at_3d8[0x3]; 1811 u8 log_max_wq_sz[0x5]; 1812 1813 u8 nic_vport_change_event[0x1]; 1814 u8 disable_local_lb_uc[0x1]; 1815 u8 disable_local_lb_mc[0x1]; 1816 u8 log_min_hairpin_wq_data_sz[0x5]; 1817 u8 reserved_at_3e8[0x2]; 1818 u8 vhca_state[0x1]; 1819 u8 log_max_vlan_list[0x5]; 1820 u8 reserved_at_3f0[0x3]; 1821 u8 log_max_current_mc_list[0x5]; 1822 u8 reserved_at_3f8[0x3]; 1823 u8 log_max_current_uc_list[0x5]; 1824 1825 u8 general_obj_types[0x40]; 1826 1827 u8 sq_ts_format[0x2]; 1828 u8 rq_ts_format[0x2]; 1829 u8 steering_format_version[0x4]; 1830 u8 create_qp_start_hint[0x18]; 1831 1832 u8 reserved_at_460[0x1]; 1833 u8 ats[0x1]; 1834 u8 reserved_at_462[0x1]; 1835 u8 log_max_uctx[0x5]; 1836 u8 reserved_at_468[0x1]; 1837 u8 crypto[0x1]; 1838 u8 ipsec_offload[0x1]; 1839 u8 log_max_umem[0x5]; 1840 u8 max_num_eqs[0x10]; 1841 1842 u8 reserved_at_480[0x1]; 1843 u8 tls_tx[0x1]; 1844 u8 tls_rx[0x1]; 1845 u8 log_max_l2_table[0x5]; 1846 u8 reserved_at_488[0x8]; 1847 u8 log_uar_page_sz[0x10]; 1848 1849 u8 reserved_at_4a0[0x20]; 1850 u8 device_frequency_mhz[0x20]; 1851 u8 device_frequency_khz[0x20]; 1852 1853 u8 reserved_at_500[0x20]; 1854 u8 num_of_uars_per_page[0x20]; 1855 1856 u8 flex_parser_protocols[0x20]; 1857 1858 u8 max_geneve_tlv_options[0x8]; 1859 u8 reserved_at_568[0x3]; 1860 u8 max_geneve_tlv_option_data_len[0x5]; 1861 u8 reserved_at_570[0x9]; 1862 u8 adv_virtualization[0x1]; 1863 u8 reserved_at_57a[0x6]; 1864 1865 u8 reserved_at_580[0xb]; 1866 u8 log_max_dci_stream_channels[0x5]; 1867 u8 reserved_at_590[0x3]; 1868 u8 log_max_dci_errored_streams[0x5]; 1869 u8 reserved_at_598[0x8]; 1870 1871 u8 reserved_at_5a0[0x10]; 1872 u8 enhanced_cqe_compression[0x1]; 1873 u8 reserved_at_5b1[0x2]; 1874 u8 log_max_dek[0x5]; 1875 u8 reserved_at_5b8[0x4]; 1876 u8 mini_cqe_resp_stride_index[0x1]; 1877 u8 cqe_128_always[0x1]; 1878 u8 cqe_compression_128[0x1]; 1879 u8 cqe_compression[0x1]; 1880 1881 u8 cqe_compression_timeout[0x10]; 1882 u8 cqe_compression_max_num[0x10]; 1883 1884 u8 reserved_at_5e0[0x8]; 1885 u8 flex_parser_id_gtpu_dw_0[0x4]; 1886 u8 reserved_at_5ec[0x4]; 1887 u8 tag_matching[0x1]; 1888 u8 rndv_offload_rc[0x1]; 1889 u8 rndv_offload_dc[0x1]; 1890 u8 log_tag_matching_list_sz[0x5]; 1891 u8 reserved_at_5f8[0x3]; 1892 u8 log_max_xrq[0x5]; 1893 1894 u8 affiliate_nic_vport_criteria[0x8]; 1895 u8 native_port_num[0x8]; 1896 u8 num_vhca_ports[0x8]; 1897 u8 flex_parser_id_gtpu_teid[0x4]; 1898 u8 reserved_at_61c[0x2]; 1899 u8 sw_owner_id[0x1]; 1900 u8 reserved_at_61f[0x1]; 1901 1902 u8 max_num_of_monitor_counters[0x10]; 1903 u8 num_ppcnt_monitor_counters[0x10]; 1904 1905 u8 max_num_sf[0x10]; 1906 u8 num_q_monitor_counters[0x10]; 1907 1908 u8 reserved_at_660[0x20]; 1909 1910 u8 sf[0x1]; 1911 u8 sf_set_partition[0x1]; 1912 u8 reserved_at_682[0x1]; 1913 u8 log_max_sf[0x5]; 1914 u8 apu[0x1]; 1915 u8 reserved_at_689[0x4]; 1916 u8 migration[0x1]; 1917 u8 reserved_at_68e[0x2]; 1918 u8 log_min_sf_size[0x8]; 1919 u8 max_num_sf_partitions[0x8]; 1920 1921 u8 uctx_cap[0x20]; 1922 1923 u8 reserved_at_6c0[0x4]; 1924 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1925 u8 flex_parser_id_icmp_dw1[0x4]; 1926 u8 flex_parser_id_icmp_dw0[0x4]; 1927 u8 flex_parser_id_icmpv6_dw1[0x4]; 1928 u8 flex_parser_id_icmpv6_dw0[0x4]; 1929 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1930 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1931 1932 u8 max_num_match_definer[0x10]; 1933 u8 sf_base_id[0x10]; 1934 1935 u8 flex_parser_id_gtpu_dw_2[0x4]; 1936 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1937 u8 num_total_dynamic_vf_msix[0x18]; 1938 u8 reserved_at_720[0x14]; 1939 u8 dynamic_msix_table_size[0xc]; 1940 u8 reserved_at_740[0xc]; 1941 u8 min_dynamic_vf_msix_table_size[0x4]; 1942 u8 reserved_at_750[0x4]; 1943 u8 max_dynamic_vf_msix_table_size[0xc]; 1944 1945 u8 reserved_at_760[0x3]; 1946 u8 log_max_num_header_modify_argument[0x5]; 1947 u8 reserved_at_768[0x4]; 1948 u8 log_header_modify_argument_granularity[0x4]; 1949 u8 reserved_at_770[0x3]; 1950 u8 log_header_modify_argument_max_alloc[0x5]; 1951 u8 reserved_at_778[0x8]; 1952 1953 u8 vhca_tunnel_commands[0x40]; 1954 u8 match_definer_format_supported[0x40]; 1955 }; 1956 1957 struct mlx5_ifc_cmd_hca_cap_2_bits { 1958 u8 reserved_at_0[0x80]; 1959 1960 u8 migratable[0x1]; 1961 u8 reserved_at_81[0x1f]; 1962 1963 u8 max_reformat_insert_size[0x8]; 1964 u8 max_reformat_insert_offset[0x8]; 1965 u8 max_reformat_remove_size[0x8]; 1966 u8 max_reformat_remove_offset[0x8]; 1967 1968 u8 reserved_at_c0[0x8]; 1969 u8 migration_multi_load[0x1]; 1970 u8 migration_tracking_state[0x1]; 1971 u8 reserved_at_ca[0x16]; 1972 1973 u8 reserved_at_e0[0xc0]; 1974 1975 u8 flow_table_type_2_type[0x8]; 1976 u8 reserved_at_1a8[0x3]; 1977 u8 log_min_mkey_entity_size[0x5]; 1978 u8 reserved_at_1b0[0x10]; 1979 1980 u8 reserved_at_1c0[0x60]; 1981 1982 u8 reserved_at_220[0x1]; 1983 u8 sw_vhca_id_valid[0x1]; 1984 u8 sw_vhca_id[0xe]; 1985 u8 reserved_at_230[0x10]; 1986 1987 u8 reserved_at_240[0xb]; 1988 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1989 u8 reserved_at_250[0x10]; 1990 1991 u8 reserved_at_260[0x5a0]; 1992 }; 1993 1994 enum mlx5_ifc_flow_destination_type { 1995 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1996 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1997 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1998 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1999 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2000 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2001 }; 2002 2003 enum mlx5_flow_table_miss_action { 2004 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2005 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2006 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2007 }; 2008 2009 struct mlx5_ifc_dest_format_struct_bits { 2010 u8 destination_type[0x8]; 2011 u8 destination_id[0x18]; 2012 2013 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2014 u8 packet_reformat[0x1]; 2015 u8 reserved_at_22[0x6]; 2016 u8 destination_table_type[0x8]; 2017 u8 destination_eswitch_owner_vhca_id[0x10]; 2018 }; 2019 2020 struct mlx5_ifc_flow_counter_list_bits { 2021 u8 flow_counter_id[0x20]; 2022 2023 u8 reserved_at_20[0x20]; 2024 }; 2025 2026 struct mlx5_ifc_extended_dest_format_bits { 2027 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2028 2029 u8 packet_reformat_id[0x20]; 2030 2031 u8 reserved_at_60[0x20]; 2032 }; 2033 2034 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2035 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2036 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2037 }; 2038 2039 struct mlx5_ifc_fte_match_param_bits { 2040 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2041 2042 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2043 2044 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2045 2046 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2047 2048 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2049 2050 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2051 2052 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2053 2054 u8 reserved_at_e00[0x200]; 2055 }; 2056 2057 enum { 2058 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2059 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2061 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2062 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2063 }; 2064 2065 struct mlx5_ifc_rx_hash_field_select_bits { 2066 u8 l3_prot_type[0x1]; 2067 u8 l4_prot_type[0x1]; 2068 u8 selected_fields[0x1e]; 2069 }; 2070 2071 enum { 2072 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2073 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2074 }; 2075 2076 enum { 2077 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2078 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2079 }; 2080 2081 struct mlx5_ifc_wq_bits { 2082 u8 wq_type[0x4]; 2083 u8 wq_signature[0x1]; 2084 u8 end_padding_mode[0x2]; 2085 u8 cd_slave[0x1]; 2086 u8 reserved_at_8[0x18]; 2087 2088 u8 hds_skip_first_sge[0x1]; 2089 u8 log2_hds_buf_size[0x3]; 2090 u8 reserved_at_24[0x7]; 2091 u8 page_offset[0x5]; 2092 u8 lwm[0x10]; 2093 2094 u8 reserved_at_40[0x8]; 2095 u8 pd[0x18]; 2096 2097 u8 reserved_at_60[0x8]; 2098 u8 uar_page[0x18]; 2099 2100 u8 dbr_addr[0x40]; 2101 2102 u8 hw_counter[0x20]; 2103 2104 u8 sw_counter[0x20]; 2105 2106 u8 reserved_at_100[0xc]; 2107 u8 log_wq_stride[0x4]; 2108 u8 reserved_at_110[0x3]; 2109 u8 log_wq_pg_sz[0x5]; 2110 u8 reserved_at_118[0x3]; 2111 u8 log_wq_sz[0x5]; 2112 2113 u8 dbr_umem_valid[0x1]; 2114 u8 wq_umem_valid[0x1]; 2115 u8 reserved_at_122[0x1]; 2116 u8 log_hairpin_num_packets[0x5]; 2117 u8 reserved_at_128[0x3]; 2118 u8 log_hairpin_data_sz[0x5]; 2119 2120 u8 reserved_at_130[0x4]; 2121 u8 log_wqe_num_of_strides[0x4]; 2122 u8 two_byte_shift_en[0x1]; 2123 u8 reserved_at_139[0x4]; 2124 u8 log_wqe_stride_size[0x3]; 2125 2126 u8 reserved_at_140[0x80]; 2127 2128 u8 headers_mkey[0x20]; 2129 2130 u8 shampo_enable[0x1]; 2131 u8 reserved_at_1e1[0x4]; 2132 u8 log_reservation_size[0x3]; 2133 u8 reserved_at_1e8[0x5]; 2134 u8 log_max_num_of_packets_per_reservation[0x3]; 2135 u8 reserved_at_1f0[0x6]; 2136 u8 log_headers_entry_size[0x2]; 2137 u8 reserved_at_1f8[0x4]; 2138 u8 log_headers_buffer_entry_num[0x4]; 2139 2140 u8 reserved_at_200[0x400]; 2141 2142 struct mlx5_ifc_cmd_pas_bits pas[]; 2143 }; 2144 2145 struct mlx5_ifc_rq_num_bits { 2146 u8 reserved_at_0[0x8]; 2147 u8 rq_num[0x18]; 2148 }; 2149 2150 struct mlx5_ifc_mac_address_layout_bits { 2151 u8 reserved_at_0[0x10]; 2152 u8 mac_addr_47_32[0x10]; 2153 2154 u8 mac_addr_31_0[0x20]; 2155 }; 2156 2157 struct mlx5_ifc_vlan_layout_bits { 2158 u8 reserved_at_0[0x14]; 2159 u8 vlan[0x0c]; 2160 2161 u8 reserved_at_20[0x20]; 2162 }; 2163 2164 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2165 u8 reserved_at_0[0xa0]; 2166 2167 u8 min_time_between_cnps[0x20]; 2168 2169 u8 reserved_at_c0[0x12]; 2170 u8 cnp_dscp[0x6]; 2171 u8 reserved_at_d8[0x4]; 2172 u8 cnp_prio_mode[0x1]; 2173 u8 cnp_802p_prio[0x3]; 2174 2175 u8 reserved_at_e0[0x720]; 2176 }; 2177 2178 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2179 u8 reserved_at_0[0x60]; 2180 2181 u8 reserved_at_60[0x4]; 2182 u8 clamp_tgt_rate[0x1]; 2183 u8 reserved_at_65[0x3]; 2184 u8 clamp_tgt_rate_after_time_inc[0x1]; 2185 u8 reserved_at_69[0x17]; 2186 2187 u8 reserved_at_80[0x20]; 2188 2189 u8 rpg_time_reset[0x20]; 2190 2191 u8 rpg_byte_reset[0x20]; 2192 2193 u8 rpg_threshold[0x20]; 2194 2195 u8 rpg_max_rate[0x20]; 2196 2197 u8 rpg_ai_rate[0x20]; 2198 2199 u8 rpg_hai_rate[0x20]; 2200 2201 u8 rpg_gd[0x20]; 2202 2203 u8 rpg_min_dec_fac[0x20]; 2204 2205 u8 rpg_min_rate[0x20]; 2206 2207 u8 reserved_at_1c0[0xe0]; 2208 2209 u8 rate_to_set_on_first_cnp[0x20]; 2210 2211 u8 dce_tcp_g[0x20]; 2212 2213 u8 dce_tcp_rtt[0x20]; 2214 2215 u8 rate_reduce_monitor_period[0x20]; 2216 2217 u8 reserved_at_320[0x20]; 2218 2219 u8 initial_alpha_value[0x20]; 2220 2221 u8 reserved_at_360[0x4a0]; 2222 }; 2223 2224 struct mlx5_ifc_cong_control_r_roce_general_bits { 2225 u8 reserved_at_0[0x80]; 2226 2227 u8 reserved_at_80[0x10]; 2228 u8 rtt_resp_dscp_valid[0x1]; 2229 u8 reserved_at_91[0x9]; 2230 u8 rtt_resp_dscp[0x6]; 2231 2232 u8 reserved_at_a0[0x760]; 2233 }; 2234 2235 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2236 u8 reserved_at_0[0x80]; 2237 2238 u8 rppp_max_rps[0x20]; 2239 2240 u8 rpg_time_reset[0x20]; 2241 2242 u8 rpg_byte_reset[0x20]; 2243 2244 u8 rpg_threshold[0x20]; 2245 2246 u8 rpg_max_rate[0x20]; 2247 2248 u8 rpg_ai_rate[0x20]; 2249 2250 u8 rpg_hai_rate[0x20]; 2251 2252 u8 rpg_gd[0x20]; 2253 2254 u8 rpg_min_dec_fac[0x20]; 2255 2256 u8 rpg_min_rate[0x20]; 2257 2258 u8 reserved_at_1c0[0x640]; 2259 }; 2260 2261 enum { 2262 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2263 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2264 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2265 }; 2266 2267 struct mlx5_ifc_resize_field_select_bits { 2268 u8 resize_field_select[0x20]; 2269 }; 2270 2271 struct mlx5_ifc_resource_dump_bits { 2272 u8 more_dump[0x1]; 2273 u8 inline_dump[0x1]; 2274 u8 reserved_at_2[0xa]; 2275 u8 seq_num[0x4]; 2276 u8 segment_type[0x10]; 2277 2278 u8 reserved_at_20[0x10]; 2279 u8 vhca_id[0x10]; 2280 2281 u8 index1[0x20]; 2282 2283 u8 index2[0x20]; 2284 2285 u8 num_of_obj1[0x10]; 2286 u8 num_of_obj2[0x10]; 2287 2288 u8 reserved_at_a0[0x20]; 2289 2290 u8 device_opaque[0x40]; 2291 2292 u8 mkey[0x20]; 2293 2294 u8 size[0x20]; 2295 2296 u8 address[0x40]; 2297 2298 u8 inline_data[52][0x20]; 2299 }; 2300 2301 struct mlx5_ifc_resource_dump_menu_record_bits { 2302 u8 reserved_at_0[0x4]; 2303 u8 num_of_obj2_supports_active[0x1]; 2304 u8 num_of_obj2_supports_all[0x1]; 2305 u8 must_have_num_of_obj2[0x1]; 2306 u8 support_num_of_obj2[0x1]; 2307 u8 num_of_obj1_supports_active[0x1]; 2308 u8 num_of_obj1_supports_all[0x1]; 2309 u8 must_have_num_of_obj1[0x1]; 2310 u8 support_num_of_obj1[0x1]; 2311 u8 must_have_index2[0x1]; 2312 u8 support_index2[0x1]; 2313 u8 must_have_index1[0x1]; 2314 u8 support_index1[0x1]; 2315 u8 segment_type[0x10]; 2316 2317 u8 segment_name[4][0x20]; 2318 2319 u8 index1_name[4][0x20]; 2320 2321 u8 index2_name[4][0x20]; 2322 }; 2323 2324 struct mlx5_ifc_resource_dump_segment_header_bits { 2325 u8 length_dw[0x10]; 2326 u8 segment_type[0x10]; 2327 }; 2328 2329 struct mlx5_ifc_resource_dump_command_segment_bits { 2330 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2331 2332 u8 segment_called[0x10]; 2333 u8 vhca_id[0x10]; 2334 2335 u8 index1[0x20]; 2336 2337 u8 index2[0x20]; 2338 2339 u8 num_of_obj1[0x10]; 2340 u8 num_of_obj2[0x10]; 2341 }; 2342 2343 struct mlx5_ifc_resource_dump_error_segment_bits { 2344 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2345 2346 u8 reserved_at_20[0x10]; 2347 u8 syndrome_id[0x10]; 2348 2349 u8 reserved_at_40[0x40]; 2350 2351 u8 error[8][0x20]; 2352 }; 2353 2354 struct mlx5_ifc_resource_dump_info_segment_bits { 2355 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2356 2357 u8 reserved_at_20[0x18]; 2358 u8 dump_version[0x8]; 2359 2360 u8 hw_version[0x20]; 2361 2362 u8 fw_version[0x20]; 2363 }; 2364 2365 struct mlx5_ifc_resource_dump_menu_segment_bits { 2366 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2367 2368 u8 reserved_at_20[0x10]; 2369 u8 num_of_records[0x10]; 2370 2371 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2372 }; 2373 2374 struct mlx5_ifc_resource_dump_resource_segment_bits { 2375 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2376 2377 u8 reserved_at_20[0x20]; 2378 2379 u8 index1[0x20]; 2380 2381 u8 index2[0x20]; 2382 2383 u8 payload[][0x20]; 2384 }; 2385 2386 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2387 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2388 }; 2389 2390 struct mlx5_ifc_menu_resource_dump_response_bits { 2391 struct mlx5_ifc_resource_dump_info_segment_bits info; 2392 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2393 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2394 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2395 }; 2396 2397 enum { 2398 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2399 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2400 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2401 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2402 }; 2403 2404 struct mlx5_ifc_modify_field_select_bits { 2405 u8 modify_field_select[0x20]; 2406 }; 2407 2408 struct mlx5_ifc_field_select_r_roce_np_bits { 2409 u8 field_select_r_roce_np[0x20]; 2410 }; 2411 2412 struct mlx5_ifc_field_select_r_roce_rp_bits { 2413 u8 field_select_r_roce_rp[0x20]; 2414 }; 2415 2416 enum { 2417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2425 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2426 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2427 }; 2428 2429 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2430 u8 field_select_8021qaurp[0x20]; 2431 }; 2432 2433 struct mlx5_ifc_phys_layer_cntrs_bits { 2434 u8 time_since_last_clear_high[0x20]; 2435 2436 u8 time_since_last_clear_low[0x20]; 2437 2438 u8 symbol_errors_high[0x20]; 2439 2440 u8 symbol_errors_low[0x20]; 2441 2442 u8 sync_headers_errors_high[0x20]; 2443 2444 u8 sync_headers_errors_low[0x20]; 2445 2446 u8 edpl_bip_errors_lane0_high[0x20]; 2447 2448 u8 edpl_bip_errors_lane0_low[0x20]; 2449 2450 u8 edpl_bip_errors_lane1_high[0x20]; 2451 2452 u8 edpl_bip_errors_lane1_low[0x20]; 2453 2454 u8 edpl_bip_errors_lane2_high[0x20]; 2455 2456 u8 edpl_bip_errors_lane2_low[0x20]; 2457 2458 u8 edpl_bip_errors_lane3_high[0x20]; 2459 2460 u8 edpl_bip_errors_lane3_low[0x20]; 2461 2462 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2463 2464 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2465 2466 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2467 2468 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2469 2470 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2471 2472 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2473 2474 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2475 2476 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2477 2478 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2479 2480 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2481 2482 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2483 2484 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2485 2486 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2487 2488 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2489 2490 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2491 2492 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2493 2494 u8 rs_fec_corrected_blocks_high[0x20]; 2495 2496 u8 rs_fec_corrected_blocks_low[0x20]; 2497 2498 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2499 2500 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2501 2502 u8 rs_fec_no_errors_blocks_high[0x20]; 2503 2504 u8 rs_fec_no_errors_blocks_low[0x20]; 2505 2506 u8 rs_fec_single_error_blocks_high[0x20]; 2507 2508 u8 rs_fec_single_error_blocks_low[0x20]; 2509 2510 u8 rs_fec_corrected_symbols_total_high[0x20]; 2511 2512 u8 rs_fec_corrected_symbols_total_low[0x20]; 2513 2514 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2515 2516 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2517 2518 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2519 2520 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2521 2522 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2523 2524 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2525 2526 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2527 2528 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2529 2530 u8 link_down_events[0x20]; 2531 2532 u8 successful_recovery_events[0x20]; 2533 2534 u8 reserved_at_640[0x180]; 2535 }; 2536 2537 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2538 u8 time_since_last_clear_high[0x20]; 2539 2540 u8 time_since_last_clear_low[0x20]; 2541 2542 u8 phy_received_bits_high[0x20]; 2543 2544 u8 phy_received_bits_low[0x20]; 2545 2546 u8 phy_symbol_errors_high[0x20]; 2547 2548 u8 phy_symbol_errors_low[0x20]; 2549 2550 u8 phy_corrected_bits_high[0x20]; 2551 2552 u8 phy_corrected_bits_low[0x20]; 2553 2554 u8 phy_corrected_bits_lane0_high[0x20]; 2555 2556 u8 phy_corrected_bits_lane0_low[0x20]; 2557 2558 u8 phy_corrected_bits_lane1_high[0x20]; 2559 2560 u8 phy_corrected_bits_lane1_low[0x20]; 2561 2562 u8 phy_corrected_bits_lane2_high[0x20]; 2563 2564 u8 phy_corrected_bits_lane2_low[0x20]; 2565 2566 u8 phy_corrected_bits_lane3_high[0x20]; 2567 2568 u8 phy_corrected_bits_lane3_low[0x20]; 2569 2570 u8 reserved_at_200[0x5c0]; 2571 }; 2572 2573 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2574 u8 symbol_error_counter[0x10]; 2575 2576 u8 link_error_recovery_counter[0x8]; 2577 2578 u8 link_downed_counter[0x8]; 2579 2580 u8 port_rcv_errors[0x10]; 2581 2582 u8 port_rcv_remote_physical_errors[0x10]; 2583 2584 u8 port_rcv_switch_relay_errors[0x10]; 2585 2586 u8 port_xmit_discards[0x10]; 2587 2588 u8 port_xmit_constraint_errors[0x8]; 2589 2590 u8 port_rcv_constraint_errors[0x8]; 2591 2592 u8 reserved_at_70[0x8]; 2593 2594 u8 link_overrun_errors[0x8]; 2595 2596 u8 reserved_at_80[0x10]; 2597 2598 u8 vl_15_dropped[0x10]; 2599 2600 u8 reserved_at_a0[0x80]; 2601 2602 u8 port_xmit_wait[0x20]; 2603 }; 2604 2605 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2606 u8 transmit_queue_high[0x20]; 2607 2608 u8 transmit_queue_low[0x20]; 2609 2610 u8 no_buffer_discard_uc_high[0x20]; 2611 2612 u8 no_buffer_discard_uc_low[0x20]; 2613 2614 u8 reserved_at_80[0x740]; 2615 }; 2616 2617 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2618 u8 wred_discard_high[0x20]; 2619 2620 u8 wred_discard_low[0x20]; 2621 2622 u8 ecn_marked_tc_high[0x20]; 2623 2624 u8 ecn_marked_tc_low[0x20]; 2625 2626 u8 reserved_at_80[0x740]; 2627 }; 2628 2629 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2630 u8 rx_octets_high[0x20]; 2631 2632 u8 rx_octets_low[0x20]; 2633 2634 u8 reserved_at_40[0xc0]; 2635 2636 u8 rx_frames_high[0x20]; 2637 2638 u8 rx_frames_low[0x20]; 2639 2640 u8 tx_octets_high[0x20]; 2641 2642 u8 tx_octets_low[0x20]; 2643 2644 u8 reserved_at_180[0xc0]; 2645 2646 u8 tx_frames_high[0x20]; 2647 2648 u8 tx_frames_low[0x20]; 2649 2650 u8 rx_pause_high[0x20]; 2651 2652 u8 rx_pause_low[0x20]; 2653 2654 u8 rx_pause_duration_high[0x20]; 2655 2656 u8 rx_pause_duration_low[0x20]; 2657 2658 u8 tx_pause_high[0x20]; 2659 2660 u8 tx_pause_low[0x20]; 2661 2662 u8 tx_pause_duration_high[0x20]; 2663 2664 u8 tx_pause_duration_low[0x20]; 2665 2666 u8 rx_pause_transition_high[0x20]; 2667 2668 u8 rx_pause_transition_low[0x20]; 2669 2670 u8 rx_discards_high[0x20]; 2671 2672 u8 rx_discards_low[0x20]; 2673 2674 u8 device_stall_minor_watermark_cnt_high[0x20]; 2675 2676 u8 device_stall_minor_watermark_cnt_low[0x20]; 2677 2678 u8 device_stall_critical_watermark_cnt_high[0x20]; 2679 2680 u8 device_stall_critical_watermark_cnt_low[0x20]; 2681 2682 u8 reserved_at_480[0x340]; 2683 }; 2684 2685 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2686 u8 port_transmit_wait_high[0x20]; 2687 2688 u8 port_transmit_wait_low[0x20]; 2689 2690 u8 reserved_at_40[0x100]; 2691 2692 u8 rx_buffer_almost_full_high[0x20]; 2693 2694 u8 rx_buffer_almost_full_low[0x20]; 2695 2696 u8 rx_buffer_full_high[0x20]; 2697 2698 u8 rx_buffer_full_low[0x20]; 2699 2700 u8 rx_icrc_encapsulated_high[0x20]; 2701 2702 u8 rx_icrc_encapsulated_low[0x20]; 2703 2704 u8 reserved_at_200[0x5c0]; 2705 }; 2706 2707 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2708 u8 dot3stats_alignment_errors_high[0x20]; 2709 2710 u8 dot3stats_alignment_errors_low[0x20]; 2711 2712 u8 dot3stats_fcs_errors_high[0x20]; 2713 2714 u8 dot3stats_fcs_errors_low[0x20]; 2715 2716 u8 dot3stats_single_collision_frames_high[0x20]; 2717 2718 u8 dot3stats_single_collision_frames_low[0x20]; 2719 2720 u8 dot3stats_multiple_collision_frames_high[0x20]; 2721 2722 u8 dot3stats_multiple_collision_frames_low[0x20]; 2723 2724 u8 dot3stats_sqe_test_errors_high[0x20]; 2725 2726 u8 dot3stats_sqe_test_errors_low[0x20]; 2727 2728 u8 dot3stats_deferred_transmissions_high[0x20]; 2729 2730 u8 dot3stats_deferred_transmissions_low[0x20]; 2731 2732 u8 dot3stats_late_collisions_high[0x20]; 2733 2734 u8 dot3stats_late_collisions_low[0x20]; 2735 2736 u8 dot3stats_excessive_collisions_high[0x20]; 2737 2738 u8 dot3stats_excessive_collisions_low[0x20]; 2739 2740 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2741 2742 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2743 2744 u8 dot3stats_carrier_sense_errors_high[0x20]; 2745 2746 u8 dot3stats_carrier_sense_errors_low[0x20]; 2747 2748 u8 dot3stats_frame_too_longs_high[0x20]; 2749 2750 u8 dot3stats_frame_too_longs_low[0x20]; 2751 2752 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2753 2754 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2755 2756 u8 dot3stats_symbol_errors_high[0x20]; 2757 2758 u8 dot3stats_symbol_errors_low[0x20]; 2759 2760 u8 dot3control_in_unknown_opcodes_high[0x20]; 2761 2762 u8 dot3control_in_unknown_opcodes_low[0x20]; 2763 2764 u8 dot3in_pause_frames_high[0x20]; 2765 2766 u8 dot3in_pause_frames_low[0x20]; 2767 2768 u8 dot3out_pause_frames_high[0x20]; 2769 2770 u8 dot3out_pause_frames_low[0x20]; 2771 2772 u8 reserved_at_400[0x3c0]; 2773 }; 2774 2775 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2776 u8 ether_stats_drop_events_high[0x20]; 2777 2778 u8 ether_stats_drop_events_low[0x20]; 2779 2780 u8 ether_stats_octets_high[0x20]; 2781 2782 u8 ether_stats_octets_low[0x20]; 2783 2784 u8 ether_stats_pkts_high[0x20]; 2785 2786 u8 ether_stats_pkts_low[0x20]; 2787 2788 u8 ether_stats_broadcast_pkts_high[0x20]; 2789 2790 u8 ether_stats_broadcast_pkts_low[0x20]; 2791 2792 u8 ether_stats_multicast_pkts_high[0x20]; 2793 2794 u8 ether_stats_multicast_pkts_low[0x20]; 2795 2796 u8 ether_stats_crc_align_errors_high[0x20]; 2797 2798 u8 ether_stats_crc_align_errors_low[0x20]; 2799 2800 u8 ether_stats_undersize_pkts_high[0x20]; 2801 2802 u8 ether_stats_undersize_pkts_low[0x20]; 2803 2804 u8 ether_stats_oversize_pkts_high[0x20]; 2805 2806 u8 ether_stats_oversize_pkts_low[0x20]; 2807 2808 u8 ether_stats_fragments_high[0x20]; 2809 2810 u8 ether_stats_fragments_low[0x20]; 2811 2812 u8 ether_stats_jabbers_high[0x20]; 2813 2814 u8 ether_stats_jabbers_low[0x20]; 2815 2816 u8 ether_stats_collisions_high[0x20]; 2817 2818 u8 ether_stats_collisions_low[0x20]; 2819 2820 u8 ether_stats_pkts64octets_high[0x20]; 2821 2822 u8 ether_stats_pkts64octets_low[0x20]; 2823 2824 u8 ether_stats_pkts65to127octets_high[0x20]; 2825 2826 u8 ether_stats_pkts65to127octets_low[0x20]; 2827 2828 u8 ether_stats_pkts128to255octets_high[0x20]; 2829 2830 u8 ether_stats_pkts128to255octets_low[0x20]; 2831 2832 u8 ether_stats_pkts256to511octets_high[0x20]; 2833 2834 u8 ether_stats_pkts256to511octets_low[0x20]; 2835 2836 u8 ether_stats_pkts512to1023octets_high[0x20]; 2837 2838 u8 ether_stats_pkts512to1023octets_low[0x20]; 2839 2840 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2841 2842 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2843 2844 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2845 2846 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2847 2848 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2849 2850 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2851 2852 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2853 2854 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2855 2856 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2857 2858 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2859 2860 u8 reserved_at_540[0x280]; 2861 }; 2862 2863 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2864 u8 if_in_octets_high[0x20]; 2865 2866 u8 if_in_octets_low[0x20]; 2867 2868 u8 if_in_ucast_pkts_high[0x20]; 2869 2870 u8 if_in_ucast_pkts_low[0x20]; 2871 2872 u8 if_in_discards_high[0x20]; 2873 2874 u8 if_in_discards_low[0x20]; 2875 2876 u8 if_in_errors_high[0x20]; 2877 2878 u8 if_in_errors_low[0x20]; 2879 2880 u8 if_in_unknown_protos_high[0x20]; 2881 2882 u8 if_in_unknown_protos_low[0x20]; 2883 2884 u8 if_out_octets_high[0x20]; 2885 2886 u8 if_out_octets_low[0x20]; 2887 2888 u8 if_out_ucast_pkts_high[0x20]; 2889 2890 u8 if_out_ucast_pkts_low[0x20]; 2891 2892 u8 if_out_discards_high[0x20]; 2893 2894 u8 if_out_discards_low[0x20]; 2895 2896 u8 if_out_errors_high[0x20]; 2897 2898 u8 if_out_errors_low[0x20]; 2899 2900 u8 if_in_multicast_pkts_high[0x20]; 2901 2902 u8 if_in_multicast_pkts_low[0x20]; 2903 2904 u8 if_in_broadcast_pkts_high[0x20]; 2905 2906 u8 if_in_broadcast_pkts_low[0x20]; 2907 2908 u8 if_out_multicast_pkts_high[0x20]; 2909 2910 u8 if_out_multicast_pkts_low[0x20]; 2911 2912 u8 if_out_broadcast_pkts_high[0x20]; 2913 2914 u8 if_out_broadcast_pkts_low[0x20]; 2915 2916 u8 reserved_at_340[0x480]; 2917 }; 2918 2919 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2920 u8 a_frames_transmitted_ok_high[0x20]; 2921 2922 u8 a_frames_transmitted_ok_low[0x20]; 2923 2924 u8 a_frames_received_ok_high[0x20]; 2925 2926 u8 a_frames_received_ok_low[0x20]; 2927 2928 u8 a_frame_check_sequence_errors_high[0x20]; 2929 2930 u8 a_frame_check_sequence_errors_low[0x20]; 2931 2932 u8 a_alignment_errors_high[0x20]; 2933 2934 u8 a_alignment_errors_low[0x20]; 2935 2936 u8 a_octets_transmitted_ok_high[0x20]; 2937 2938 u8 a_octets_transmitted_ok_low[0x20]; 2939 2940 u8 a_octets_received_ok_high[0x20]; 2941 2942 u8 a_octets_received_ok_low[0x20]; 2943 2944 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2945 2946 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2947 2948 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2949 2950 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2951 2952 u8 a_multicast_frames_received_ok_high[0x20]; 2953 2954 u8 a_multicast_frames_received_ok_low[0x20]; 2955 2956 u8 a_broadcast_frames_received_ok_high[0x20]; 2957 2958 u8 a_broadcast_frames_received_ok_low[0x20]; 2959 2960 u8 a_in_range_length_errors_high[0x20]; 2961 2962 u8 a_in_range_length_errors_low[0x20]; 2963 2964 u8 a_out_of_range_length_field_high[0x20]; 2965 2966 u8 a_out_of_range_length_field_low[0x20]; 2967 2968 u8 a_frame_too_long_errors_high[0x20]; 2969 2970 u8 a_frame_too_long_errors_low[0x20]; 2971 2972 u8 a_symbol_error_during_carrier_high[0x20]; 2973 2974 u8 a_symbol_error_during_carrier_low[0x20]; 2975 2976 u8 a_mac_control_frames_transmitted_high[0x20]; 2977 2978 u8 a_mac_control_frames_transmitted_low[0x20]; 2979 2980 u8 a_mac_control_frames_received_high[0x20]; 2981 2982 u8 a_mac_control_frames_received_low[0x20]; 2983 2984 u8 a_unsupported_opcodes_received_high[0x20]; 2985 2986 u8 a_unsupported_opcodes_received_low[0x20]; 2987 2988 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2989 2990 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2991 2992 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2993 2994 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2995 2996 u8 reserved_at_4c0[0x300]; 2997 }; 2998 2999 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3000 u8 life_time_counter_high[0x20]; 3001 3002 u8 life_time_counter_low[0x20]; 3003 3004 u8 rx_errors[0x20]; 3005 3006 u8 tx_errors[0x20]; 3007 3008 u8 l0_to_recovery_eieos[0x20]; 3009 3010 u8 l0_to_recovery_ts[0x20]; 3011 3012 u8 l0_to_recovery_framing[0x20]; 3013 3014 u8 l0_to_recovery_retrain[0x20]; 3015 3016 u8 crc_error_dllp[0x20]; 3017 3018 u8 crc_error_tlp[0x20]; 3019 3020 u8 tx_overflow_buffer_pkt_high[0x20]; 3021 3022 u8 tx_overflow_buffer_pkt_low[0x20]; 3023 3024 u8 outbound_stalled_reads[0x20]; 3025 3026 u8 outbound_stalled_writes[0x20]; 3027 3028 u8 outbound_stalled_reads_events[0x20]; 3029 3030 u8 outbound_stalled_writes_events[0x20]; 3031 3032 u8 reserved_at_200[0x5c0]; 3033 }; 3034 3035 struct mlx5_ifc_cmd_inter_comp_event_bits { 3036 u8 command_completion_vector[0x20]; 3037 3038 u8 reserved_at_20[0xc0]; 3039 }; 3040 3041 struct mlx5_ifc_stall_vl_event_bits { 3042 u8 reserved_at_0[0x18]; 3043 u8 port_num[0x1]; 3044 u8 reserved_at_19[0x3]; 3045 u8 vl[0x4]; 3046 3047 u8 reserved_at_20[0xa0]; 3048 }; 3049 3050 struct mlx5_ifc_db_bf_congestion_event_bits { 3051 u8 event_subtype[0x8]; 3052 u8 reserved_at_8[0x8]; 3053 u8 congestion_level[0x8]; 3054 u8 reserved_at_18[0x8]; 3055 3056 u8 reserved_at_20[0xa0]; 3057 }; 3058 3059 struct mlx5_ifc_gpio_event_bits { 3060 u8 reserved_at_0[0x60]; 3061 3062 u8 gpio_event_hi[0x20]; 3063 3064 u8 gpio_event_lo[0x20]; 3065 3066 u8 reserved_at_a0[0x40]; 3067 }; 3068 3069 struct mlx5_ifc_port_state_change_event_bits { 3070 u8 reserved_at_0[0x40]; 3071 3072 u8 port_num[0x4]; 3073 u8 reserved_at_44[0x1c]; 3074 3075 u8 reserved_at_60[0x80]; 3076 }; 3077 3078 struct mlx5_ifc_dropped_packet_logged_bits { 3079 u8 reserved_at_0[0xe0]; 3080 }; 3081 3082 struct mlx5_ifc_default_timeout_bits { 3083 u8 to_multiplier[0x3]; 3084 u8 reserved_at_3[0x9]; 3085 u8 to_value[0x14]; 3086 }; 3087 3088 struct mlx5_ifc_dtor_reg_bits { 3089 u8 reserved_at_0[0x20]; 3090 3091 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3092 3093 u8 reserved_at_40[0x60]; 3094 3095 struct mlx5_ifc_default_timeout_bits health_poll_to; 3096 3097 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3098 3099 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3100 3101 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3102 3103 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3104 3105 struct mlx5_ifc_default_timeout_bits tear_down_to; 3106 3107 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3108 3109 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3110 3111 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3112 3113 u8 reserved_at_1c0[0x40]; 3114 }; 3115 3116 enum { 3117 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3118 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3119 }; 3120 3121 struct mlx5_ifc_cq_error_bits { 3122 u8 reserved_at_0[0x8]; 3123 u8 cqn[0x18]; 3124 3125 u8 reserved_at_20[0x20]; 3126 3127 u8 reserved_at_40[0x18]; 3128 u8 syndrome[0x8]; 3129 3130 u8 reserved_at_60[0x80]; 3131 }; 3132 3133 struct mlx5_ifc_rdma_page_fault_event_bits { 3134 u8 bytes_committed[0x20]; 3135 3136 u8 r_key[0x20]; 3137 3138 u8 reserved_at_40[0x10]; 3139 u8 packet_len[0x10]; 3140 3141 u8 rdma_op_len[0x20]; 3142 3143 u8 rdma_va[0x40]; 3144 3145 u8 reserved_at_c0[0x5]; 3146 u8 rdma[0x1]; 3147 u8 write[0x1]; 3148 u8 requestor[0x1]; 3149 u8 qp_number[0x18]; 3150 }; 3151 3152 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3153 u8 bytes_committed[0x20]; 3154 3155 u8 reserved_at_20[0x10]; 3156 u8 wqe_index[0x10]; 3157 3158 u8 reserved_at_40[0x10]; 3159 u8 len[0x10]; 3160 3161 u8 reserved_at_60[0x60]; 3162 3163 u8 reserved_at_c0[0x5]; 3164 u8 rdma[0x1]; 3165 u8 write_read[0x1]; 3166 u8 requestor[0x1]; 3167 u8 qpn[0x18]; 3168 }; 3169 3170 struct mlx5_ifc_qp_events_bits { 3171 u8 reserved_at_0[0xa0]; 3172 3173 u8 type[0x8]; 3174 u8 reserved_at_a8[0x18]; 3175 3176 u8 reserved_at_c0[0x8]; 3177 u8 qpn_rqn_sqn[0x18]; 3178 }; 3179 3180 struct mlx5_ifc_dct_events_bits { 3181 u8 reserved_at_0[0xc0]; 3182 3183 u8 reserved_at_c0[0x8]; 3184 u8 dct_number[0x18]; 3185 }; 3186 3187 struct mlx5_ifc_comp_event_bits { 3188 u8 reserved_at_0[0xc0]; 3189 3190 u8 reserved_at_c0[0x8]; 3191 u8 cq_number[0x18]; 3192 }; 3193 3194 enum { 3195 MLX5_QPC_STATE_RST = 0x0, 3196 MLX5_QPC_STATE_INIT = 0x1, 3197 MLX5_QPC_STATE_RTR = 0x2, 3198 MLX5_QPC_STATE_RTS = 0x3, 3199 MLX5_QPC_STATE_SQER = 0x4, 3200 MLX5_QPC_STATE_ERR = 0x6, 3201 MLX5_QPC_STATE_SQD = 0x7, 3202 MLX5_QPC_STATE_SUSPENDED = 0x9, 3203 }; 3204 3205 enum { 3206 MLX5_QPC_ST_RC = 0x0, 3207 MLX5_QPC_ST_UC = 0x1, 3208 MLX5_QPC_ST_UD = 0x2, 3209 MLX5_QPC_ST_XRC = 0x3, 3210 MLX5_QPC_ST_DCI = 0x5, 3211 MLX5_QPC_ST_QP0 = 0x7, 3212 MLX5_QPC_ST_QP1 = 0x8, 3213 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3214 MLX5_QPC_ST_REG_UMR = 0xc, 3215 }; 3216 3217 enum { 3218 MLX5_QPC_PM_STATE_ARMED = 0x0, 3219 MLX5_QPC_PM_STATE_REARM = 0x1, 3220 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3221 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3222 }; 3223 3224 enum { 3225 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3226 }; 3227 3228 enum { 3229 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3230 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3231 }; 3232 3233 enum { 3234 MLX5_QPC_MTU_256_BYTES = 0x1, 3235 MLX5_QPC_MTU_512_BYTES = 0x2, 3236 MLX5_QPC_MTU_1K_BYTES = 0x3, 3237 MLX5_QPC_MTU_2K_BYTES = 0x4, 3238 MLX5_QPC_MTU_4K_BYTES = 0x5, 3239 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3240 }; 3241 3242 enum { 3243 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3244 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3245 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3246 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3247 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3248 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3249 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3250 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3251 }; 3252 3253 enum { 3254 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3255 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3256 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3257 }; 3258 3259 enum { 3260 MLX5_QPC_CS_RES_DISABLE = 0x0, 3261 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3262 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3263 }; 3264 3265 enum { 3266 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3267 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3268 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3269 }; 3270 3271 struct mlx5_ifc_qpc_bits { 3272 u8 state[0x4]; 3273 u8 lag_tx_port_affinity[0x4]; 3274 u8 st[0x8]; 3275 u8 reserved_at_10[0x2]; 3276 u8 isolate_vl_tc[0x1]; 3277 u8 pm_state[0x2]; 3278 u8 reserved_at_15[0x1]; 3279 u8 req_e2e_credit_mode[0x2]; 3280 u8 offload_type[0x4]; 3281 u8 end_padding_mode[0x2]; 3282 u8 reserved_at_1e[0x2]; 3283 3284 u8 wq_signature[0x1]; 3285 u8 block_lb_mc[0x1]; 3286 u8 atomic_like_write_en[0x1]; 3287 u8 latency_sensitive[0x1]; 3288 u8 reserved_at_24[0x1]; 3289 u8 drain_sigerr[0x1]; 3290 u8 reserved_at_26[0x2]; 3291 u8 pd[0x18]; 3292 3293 u8 mtu[0x3]; 3294 u8 log_msg_max[0x5]; 3295 u8 reserved_at_48[0x1]; 3296 u8 log_rq_size[0x4]; 3297 u8 log_rq_stride[0x3]; 3298 u8 no_sq[0x1]; 3299 u8 log_sq_size[0x4]; 3300 u8 reserved_at_55[0x1]; 3301 u8 retry_mode[0x2]; 3302 u8 ts_format[0x2]; 3303 u8 reserved_at_5a[0x1]; 3304 u8 rlky[0x1]; 3305 u8 ulp_stateless_offload_mode[0x4]; 3306 3307 u8 counter_set_id[0x8]; 3308 u8 uar_page[0x18]; 3309 3310 u8 reserved_at_80[0x8]; 3311 u8 user_index[0x18]; 3312 3313 u8 reserved_at_a0[0x3]; 3314 u8 log_page_size[0x5]; 3315 u8 remote_qpn[0x18]; 3316 3317 struct mlx5_ifc_ads_bits primary_address_path; 3318 3319 struct mlx5_ifc_ads_bits secondary_address_path; 3320 3321 u8 log_ack_req_freq[0x4]; 3322 u8 reserved_at_384[0x4]; 3323 u8 log_sra_max[0x3]; 3324 u8 reserved_at_38b[0x2]; 3325 u8 retry_count[0x3]; 3326 u8 rnr_retry[0x3]; 3327 u8 reserved_at_393[0x1]; 3328 u8 fre[0x1]; 3329 u8 cur_rnr_retry[0x3]; 3330 u8 cur_retry_count[0x3]; 3331 u8 reserved_at_39b[0x5]; 3332 3333 u8 reserved_at_3a0[0x20]; 3334 3335 u8 reserved_at_3c0[0x8]; 3336 u8 next_send_psn[0x18]; 3337 3338 u8 reserved_at_3e0[0x3]; 3339 u8 log_num_dci_stream_channels[0x5]; 3340 u8 cqn_snd[0x18]; 3341 3342 u8 reserved_at_400[0x3]; 3343 u8 log_num_dci_errored_streams[0x5]; 3344 u8 deth_sqpn[0x18]; 3345 3346 u8 reserved_at_420[0x20]; 3347 3348 u8 reserved_at_440[0x8]; 3349 u8 last_acked_psn[0x18]; 3350 3351 u8 reserved_at_460[0x8]; 3352 u8 ssn[0x18]; 3353 3354 u8 reserved_at_480[0x8]; 3355 u8 log_rra_max[0x3]; 3356 u8 reserved_at_48b[0x1]; 3357 u8 atomic_mode[0x4]; 3358 u8 rre[0x1]; 3359 u8 rwe[0x1]; 3360 u8 rae[0x1]; 3361 u8 reserved_at_493[0x1]; 3362 u8 page_offset[0x6]; 3363 u8 reserved_at_49a[0x3]; 3364 u8 cd_slave_receive[0x1]; 3365 u8 cd_slave_send[0x1]; 3366 u8 cd_master[0x1]; 3367 3368 u8 reserved_at_4a0[0x3]; 3369 u8 min_rnr_nak[0x5]; 3370 u8 next_rcv_psn[0x18]; 3371 3372 u8 reserved_at_4c0[0x8]; 3373 u8 xrcd[0x18]; 3374 3375 u8 reserved_at_4e0[0x8]; 3376 u8 cqn_rcv[0x18]; 3377 3378 u8 dbr_addr[0x40]; 3379 3380 u8 q_key[0x20]; 3381 3382 u8 reserved_at_560[0x5]; 3383 u8 rq_type[0x3]; 3384 u8 srqn_rmpn_xrqn[0x18]; 3385 3386 u8 reserved_at_580[0x8]; 3387 u8 rmsn[0x18]; 3388 3389 u8 hw_sq_wqebb_counter[0x10]; 3390 u8 sw_sq_wqebb_counter[0x10]; 3391 3392 u8 hw_rq_counter[0x20]; 3393 3394 u8 sw_rq_counter[0x20]; 3395 3396 u8 reserved_at_600[0x20]; 3397 3398 u8 reserved_at_620[0xf]; 3399 u8 cgs[0x1]; 3400 u8 cs_req[0x8]; 3401 u8 cs_res[0x8]; 3402 3403 u8 dc_access_key[0x40]; 3404 3405 u8 reserved_at_680[0x3]; 3406 u8 dbr_umem_valid[0x1]; 3407 3408 u8 reserved_at_684[0xbc]; 3409 }; 3410 3411 struct mlx5_ifc_roce_addr_layout_bits { 3412 u8 source_l3_address[16][0x8]; 3413 3414 u8 reserved_at_80[0x3]; 3415 u8 vlan_valid[0x1]; 3416 u8 vlan_id[0xc]; 3417 u8 source_mac_47_32[0x10]; 3418 3419 u8 source_mac_31_0[0x20]; 3420 3421 u8 reserved_at_c0[0x14]; 3422 u8 roce_l3_type[0x4]; 3423 u8 roce_version[0x8]; 3424 3425 u8 reserved_at_e0[0x20]; 3426 }; 3427 3428 struct mlx5_ifc_shampo_cap_bits { 3429 u8 reserved_at_0[0x3]; 3430 u8 shampo_log_max_reservation_size[0x5]; 3431 u8 reserved_at_8[0x3]; 3432 u8 shampo_log_min_reservation_size[0x5]; 3433 u8 shampo_min_mss_size[0x10]; 3434 3435 u8 reserved_at_20[0x3]; 3436 u8 shampo_max_log_headers_entry_size[0x5]; 3437 u8 reserved_at_28[0x18]; 3438 3439 u8 reserved_at_40[0x7c0]; 3440 }; 3441 3442 struct mlx5_ifc_crypto_cap_bits { 3443 u8 reserved_at_0[0x3]; 3444 u8 synchronize_dek[0x1]; 3445 u8 int_kek_manual[0x1]; 3446 u8 int_kek_auto[0x1]; 3447 u8 reserved_at_6[0x1a]; 3448 3449 u8 reserved_at_20[0x3]; 3450 u8 log_dek_max_alloc[0x5]; 3451 u8 reserved_at_28[0x3]; 3452 u8 log_max_num_deks[0x5]; 3453 u8 reserved_at_30[0x10]; 3454 3455 u8 reserved_at_40[0x20]; 3456 3457 u8 reserved_at_60[0x3]; 3458 u8 log_dek_granularity[0x5]; 3459 u8 reserved_at_68[0x3]; 3460 u8 log_max_num_int_kek[0x5]; 3461 u8 sw_wrapped_dek[0x10]; 3462 3463 u8 reserved_at_80[0x780]; 3464 }; 3465 3466 union mlx5_ifc_hca_cap_union_bits { 3467 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3468 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3469 struct mlx5_ifc_odp_cap_bits odp_cap; 3470 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3471 struct mlx5_ifc_roce_cap_bits roce_cap; 3472 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3473 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3474 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3475 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3476 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3477 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3478 struct mlx5_ifc_qos_cap_bits qos_cap; 3479 struct mlx5_ifc_debug_cap_bits debug_cap; 3480 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3481 struct mlx5_ifc_tls_cap_bits tls_cap; 3482 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3483 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3484 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3485 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3486 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3487 u8 reserved_at_0[0x8000]; 3488 }; 3489 3490 enum { 3491 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3492 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3493 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3494 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3495 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3496 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3497 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3498 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3499 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3500 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3501 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3502 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3503 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3504 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3505 }; 3506 3507 enum { 3508 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3509 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3510 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3511 }; 3512 3513 enum { 3514 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3515 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3516 }; 3517 3518 struct mlx5_ifc_vlan_bits { 3519 u8 ethtype[0x10]; 3520 u8 prio[0x3]; 3521 u8 cfi[0x1]; 3522 u8 vid[0xc]; 3523 }; 3524 3525 enum { 3526 MLX5_FLOW_METER_COLOR_RED = 0x0, 3527 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3528 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3529 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3530 }; 3531 3532 enum { 3533 MLX5_EXE_ASO_FLOW_METER = 0x2, 3534 }; 3535 3536 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3537 u8 return_reg_id[0x4]; 3538 u8 aso_type[0x4]; 3539 u8 reserved_at_8[0x14]; 3540 u8 action[0x1]; 3541 u8 init_color[0x2]; 3542 u8 meter_id[0x1]; 3543 }; 3544 3545 union mlx5_ifc_exe_aso_ctrl { 3546 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3547 }; 3548 3549 struct mlx5_ifc_execute_aso_bits { 3550 u8 valid[0x1]; 3551 u8 reserved_at_1[0x7]; 3552 u8 aso_object_id[0x18]; 3553 3554 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3555 }; 3556 3557 struct mlx5_ifc_flow_context_bits { 3558 struct mlx5_ifc_vlan_bits push_vlan; 3559 3560 u8 group_id[0x20]; 3561 3562 u8 reserved_at_40[0x8]; 3563 u8 flow_tag[0x18]; 3564 3565 u8 reserved_at_60[0x10]; 3566 u8 action[0x10]; 3567 3568 u8 extended_destination[0x1]; 3569 u8 reserved_at_81[0x1]; 3570 u8 flow_source[0x2]; 3571 u8 encrypt_decrypt_type[0x4]; 3572 u8 destination_list_size[0x18]; 3573 3574 u8 reserved_at_a0[0x8]; 3575 u8 flow_counter_list_size[0x18]; 3576 3577 u8 packet_reformat_id[0x20]; 3578 3579 u8 modify_header_id[0x20]; 3580 3581 struct mlx5_ifc_vlan_bits push_vlan_2; 3582 3583 u8 encrypt_decrypt_obj_id[0x20]; 3584 u8 reserved_at_140[0xc0]; 3585 3586 struct mlx5_ifc_fte_match_param_bits match_value; 3587 3588 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3589 3590 u8 reserved_at_1300[0x500]; 3591 3592 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3593 }; 3594 3595 enum { 3596 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3597 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3598 }; 3599 3600 struct mlx5_ifc_xrc_srqc_bits { 3601 u8 state[0x4]; 3602 u8 log_xrc_srq_size[0x4]; 3603 u8 reserved_at_8[0x18]; 3604 3605 u8 wq_signature[0x1]; 3606 u8 cont_srq[0x1]; 3607 u8 reserved_at_22[0x1]; 3608 u8 rlky[0x1]; 3609 u8 basic_cyclic_rcv_wqe[0x1]; 3610 u8 log_rq_stride[0x3]; 3611 u8 xrcd[0x18]; 3612 3613 u8 page_offset[0x6]; 3614 u8 reserved_at_46[0x1]; 3615 u8 dbr_umem_valid[0x1]; 3616 u8 cqn[0x18]; 3617 3618 u8 reserved_at_60[0x20]; 3619 3620 u8 user_index_equal_xrc_srqn[0x1]; 3621 u8 reserved_at_81[0x1]; 3622 u8 log_page_size[0x6]; 3623 u8 user_index[0x18]; 3624 3625 u8 reserved_at_a0[0x20]; 3626 3627 u8 reserved_at_c0[0x8]; 3628 u8 pd[0x18]; 3629 3630 u8 lwm[0x10]; 3631 u8 wqe_cnt[0x10]; 3632 3633 u8 reserved_at_100[0x40]; 3634 3635 u8 db_record_addr_h[0x20]; 3636 3637 u8 db_record_addr_l[0x1e]; 3638 u8 reserved_at_17e[0x2]; 3639 3640 u8 reserved_at_180[0x80]; 3641 }; 3642 3643 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3644 u8 counter_error_queues[0x20]; 3645 3646 u8 total_error_queues[0x20]; 3647 3648 u8 send_queue_priority_update_flow[0x20]; 3649 3650 u8 reserved_at_60[0x20]; 3651 3652 u8 nic_receive_steering_discard[0x40]; 3653 3654 u8 receive_discard_vport_down[0x40]; 3655 3656 u8 transmit_discard_vport_down[0x40]; 3657 3658 u8 async_eq_overrun[0x20]; 3659 3660 u8 comp_eq_overrun[0x20]; 3661 3662 u8 reserved_at_180[0x20]; 3663 3664 u8 invalid_command[0x20]; 3665 3666 u8 quota_exceeded_command[0x20]; 3667 3668 u8 internal_rq_out_of_buffer[0x20]; 3669 3670 u8 cq_overrun[0x20]; 3671 3672 u8 eth_wqe_too_small[0x20]; 3673 3674 u8 reserved_at_220[0xdc0]; 3675 }; 3676 3677 struct mlx5_ifc_traffic_counter_bits { 3678 u8 packets[0x40]; 3679 3680 u8 octets[0x40]; 3681 }; 3682 3683 struct mlx5_ifc_tisc_bits { 3684 u8 strict_lag_tx_port_affinity[0x1]; 3685 u8 tls_en[0x1]; 3686 u8 reserved_at_2[0x2]; 3687 u8 lag_tx_port_affinity[0x04]; 3688 3689 u8 reserved_at_8[0x4]; 3690 u8 prio[0x4]; 3691 u8 reserved_at_10[0x10]; 3692 3693 u8 reserved_at_20[0x100]; 3694 3695 u8 reserved_at_120[0x8]; 3696 u8 transport_domain[0x18]; 3697 3698 u8 reserved_at_140[0x8]; 3699 u8 underlay_qpn[0x18]; 3700 3701 u8 reserved_at_160[0x8]; 3702 u8 pd[0x18]; 3703 3704 u8 reserved_at_180[0x380]; 3705 }; 3706 3707 enum { 3708 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3709 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3710 }; 3711 3712 enum { 3713 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3714 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3715 }; 3716 3717 enum { 3718 MLX5_RX_HASH_FN_NONE = 0x0, 3719 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3720 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3721 }; 3722 3723 enum { 3724 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3725 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3726 }; 3727 3728 struct mlx5_ifc_tirc_bits { 3729 u8 reserved_at_0[0x20]; 3730 3731 u8 disp_type[0x4]; 3732 u8 tls_en[0x1]; 3733 u8 reserved_at_25[0x1b]; 3734 3735 u8 reserved_at_40[0x40]; 3736 3737 u8 reserved_at_80[0x4]; 3738 u8 lro_timeout_period_usecs[0x10]; 3739 u8 packet_merge_mask[0x4]; 3740 u8 lro_max_ip_payload_size[0x8]; 3741 3742 u8 reserved_at_a0[0x40]; 3743 3744 u8 reserved_at_e0[0x8]; 3745 u8 inline_rqn[0x18]; 3746 3747 u8 rx_hash_symmetric[0x1]; 3748 u8 reserved_at_101[0x1]; 3749 u8 tunneled_offload_en[0x1]; 3750 u8 reserved_at_103[0x5]; 3751 u8 indirect_table[0x18]; 3752 3753 u8 rx_hash_fn[0x4]; 3754 u8 reserved_at_124[0x2]; 3755 u8 self_lb_block[0x2]; 3756 u8 transport_domain[0x18]; 3757 3758 u8 rx_hash_toeplitz_key[10][0x20]; 3759 3760 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3761 3762 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3763 3764 u8 reserved_at_2c0[0x4c0]; 3765 }; 3766 3767 enum { 3768 MLX5_SRQC_STATE_GOOD = 0x0, 3769 MLX5_SRQC_STATE_ERROR = 0x1, 3770 }; 3771 3772 struct mlx5_ifc_srqc_bits { 3773 u8 state[0x4]; 3774 u8 log_srq_size[0x4]; 3775 u8 reserved_at_8[0x18]; 3776 3777 u8 wq_signature[0x1]; 3778 u8 cont_srq[0x1]; 3779 u8 reserved_at_22[0x1]; 3780 u8 rlky[0x1]; 3781 u8 reserved_at_24[0x1]; 3782 u8 log_rq_stride[0x3]; 3783 u8 xrcd[0x18]; 3784 3785 u8 page_offset[0x6]; 3786 u8 reserved_at_46[0x2]; 3787 u8 cqn[0x18]; 3788 3789 u8 reserved_at_60[0x20]; 3790 3791 u8 reserved_at_80[0x2]; 3792 u8 log_page_size[0x6]; 3793 u8 reserved_at_88[0x18]; 3794 3795 u8 reserved_at_a0[0x20]; 3796 3797 u8 reserved_at_c0[0x8]; 3798 u8 pd[0x18]; 3799 3800 u8 lwm[0x10]; 3801 u8 wqe_cnt[0x10]; 3802 3803 u8 reserved_at_100[0x40]; 3804 3805 u8 dbr_addr[0x40]; 3806 3807 u8 reserved_at_180[0x80]; 3808 }; 3809 3810 enum { 3811 MLX5_SQC_STATE_RST = 0x0, 3812 MLX5_SQC_STATE_RDY = 0x1, 3813 MLX5_SQC_STATE_ERR = 0x3, 3814 }; 3815 3816 struct mlx5_ifc_sqc_bits { 3817 u8 rlky[0x1]; 3818 u8 cd_master[0x1]; 3819 u8 fre[0x1]; 3820 u8 flush_in_error_en[0x1]; 3821 u8 allow_multi_pkt_send_wqe[0x1]; 3822 u8 min_wqe_inline_mode[0x3]; 3823 u8 state[0x4]; 3824 u8 reg_umr[0x1]; 3825 u8 allow_swp[0x1]; 3826 u8 hairpin[0x1]; 3827 u8 reserved_at_f[0xb]; 3828 u8 ts_format[0x2]; 3829 u8 reserved_at_1c[0x4]; 3830 3831 u8 reserved_at_20[0x8]; 3832 u8 user_index[0x18]; 3833 3834 u8 reserved_at_40[0x8]; 3835 u8 cqn[0x18]; 3836 3837 u8 reserved_at_60[0x8]; 3838 u8 hairpin_peer_rq[0x18]; 3839 3840 u8 reserved_at_80[0x10]; 3841 u8 hairpin_peer_vhca[0x10]; 3842 3843 u8 reserved_at_a0[0x20]; 3844 3845 u8 reserved_at_c0[0x8]; 3846 u8 ts_cqe_to_dest_cqn[0x18]; 3847 3848 u8 reserved_at_e0[0x10]; 3849 u8 packet_pacing_rate_limit_index[0x10]; 3850 u8 tis_lst_sz[0x10]; 3851 u8 qos_queue_group_id[0x10]; 3852 3853 u8 reserved_at_120[0x40]; 3854 3855 u8 reserved_at_160[0x8]; 3856 u8 tis_num_0[0x18]; 3857 3858 struct mlx5_ifc_wq_bits wq; 3859 }; 3860 3861 enum { 3862 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3863 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3864 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3865 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3866 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3867 }; 3868 3869 enum { 3870 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3871 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3872 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3873 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3874 }; 3875 3876 struct mlx5_ifc_scheduling_context_bits { 3877 u8 element_type[0x8]; 3878 u8 reserved_at_8[0x18]; 3879 3880 u8 element_attributes[0x20]; 3881 3882 u8 parent_element_id[0x20]; 3883 3884 u8 reserved_at_60[0x40]; 3885 3886 u8 bw_share[0x20]; 3887 3888 u8 max_average_bw[0x20]; 3889 3890 u8 reserved_at_e0[0x120]; 3891 }; 3892 3893 struct mlx5_ifc_rqtc_bits { 3894 u8 reserved_at_0[0xa0]; 3895 3896 u8 reserved_at_a0[0x5]; 3897 u8 list_q_type[0x3]; 3898 u8 reserved_at_a8[0x8]; 3899 u8 rqt_max_size[0x10]; 3900 3901 u8 rq_vhca_id_format[0x1]; 3902 u8 reserved_at_c1[0xf]; 3903 u8 rqt_actual_size[0x10]; 3904 3905 u8 reserved_at_e0[0x6a0]; 3906 3907 struct mlx5_ifc_rq_num_bits rq_num[]; 3908 }; 3909 3910 enum { 3911 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3912 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3913 }; 3914 3915 enum { 3916 MLX5_RQC_STATE_RST = 0x0, 3917 MLX5_RQC_STATE_RDY = 0x1, 3918 MLX5_RQC_STATE_ERR = 0x3, 3919 }; 3920 3921 enum { 3922 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3923 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3924 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3925 }; 3926 3927 enum { 3928 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3929 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3930 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3931 }; 3932 3933 struct mlx5_ifc_rqc_bits { 3934 u8 rlky[0x1]; 3935 u8 delay_drop_en[0x1]; 3936 u8 scatter_fcs[0x1]; 3937 u8 vsd[0x1]; 3938 u8 mem_rq_type[0x4]; 3939 u8 state[0x4]; 3940 u8 reserved_at_c[0x1]; 3941 u8 flush_in_error_en[0x1]; 3942 u8 hairpin[0x1]; 3943 u8 reserved_at_f[0xb]; 3944 u8 ts_format[0x2]; 3945 u8 reserved_at_1c[0x4]; 3946 3947 u8 reserved_at_20[0x8]; 3948 u8 user_index[0x18]; 3949 3950 u8 reserved_at_40[0x8]; 3951 u8 cqn[0x18]; 3952 3953 u8 counter_set_id[0x8]; 3954 u8 reserved_at_68[0x18]; 3955 3956 u8 reserved_at_80[0x8]; 3957 u8 rmpn[0x18]; 3958 3959 u8 reserved_at_a0[0x8]; 3960 u8 hairpin_peer_sq[0x18]; 3961 3962 u8 reserved_at_c0[0x10]; 3963 u8 hairpin_peer_vhca[0x10]; 3964 3965 u8 reserved_at_e0[0x46]; 3966 u8 shampo_no_match_alignment_granularity[0x2]; 3967 u8 reserved_at_128[0x6]; 3968 u8 shampo_match_criteria_type[0x2]; 3969 u8 reservation_timeout[0x10]; 3970 3971 u8 reserved_at_140[0x40]; 3972 3973 struct mlx5_ifc_wq_bits wq; 3974 }; 3975 3976 enum { 3977 MLX5_RMPC_STATE_RDY = 0x1, 3978 MLX5_RMPC_STATE_ERR = 0x3, 3979 }; 3980 3981 struct mlx5_ifc_rmpc_bits { 3982 u8 reserved_at_0[0x8]; 3983 u8 state[0x4]; 3984 u8 reserved_at_c[0x14]; 3985 3986 u8 basic_cyclic_rcv_wqe[0x1]; 3987 u8 reserved_at_21[0x1f]; 3988 3989 u8 reserved_at_40[0x140]; 3990 3991 struct mlx5_ifc_wq_bits wq; 3992 }; 3993 3994 enum { 3995 VHCA_ID_TYPE_HW = 0, 3996 VHCA_ID_TYPE_SW = 1, 3997 }; 3998 3999 struct mlx5_ifc_nic_vport_context_bits { 4000 u8 reserved_at_0[0x5]; 4001 u8 min_wqe_inline_mode[0x3]; 4002 u8 reserved_at_8[0x15]; 4003 u8 disable_mc_local_lb[0x1]; 4004 u8 disable_uc_local_lb[0x1]; 4005 u8 roce_en[0x1]; 4006 4007 u8 arm_change_event[0x1]; 4008 u8 reserved_at_21[0x1a]; 4009 u8 event_on_mtu[0x1]; 4010 u8 event_on_promisc_change[0x1]; 4011 u8 event_on_vlan_change[0x1]; 4012 u8 event_on_mc_address_change[0x1]; 4013 u8 event_on_uc_address_change[0x1]; 4014 4015 u8 vhca_id_type[0x1]; 4016 u8 reserved_at_41[0xb]; 4017 u8 affiliation_criteria[0x4]; 4018 u8 affiliated_vhca_id[0x10]; 4019 4020 u8 reserved_at_60[0xd0]; 4021 4022 u8 mtu[0x10]; 4023 4024 u8 system_image_guid[0x40]; 4025 u8 port_guid[0x40]; 4026 u8 node_guid[0x40]; 4027 4028 u8 reserved_at_200[0x140]; 4029 u8 qkey_violation_counter[0x10]; 4030 u8 reserved_at_350[0x430]; 4031 4032 u8 promisc_uc[0x1]; 4033 u8 promisc_mc[0x1]; 4034 u8 promisc_all[0x1]; 4035 u8 reserved_at_783[0x2]; 4036 u8 allowed_list_type[0x3]; 4037 u8 reserved_at_788[0xc]; 4038 u8 allowed_list_size[0xc]; 4039 4040 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4041 4042 u8 reserved_at_7e0[0x20]; 4043 4044 u8 current_uc_mac_address[][0x40]; 4045 }; 4046 4047 enum { 4048 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4049 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4050 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4051 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4052 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4053 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4054 }; 4055 4056 struct mlx5_ifc_mkc_bits { 4057 u8 reserved_at_0[0x1]; 4058 u8 free[0x1]; 4059 u8 reserved_at_2[0x1]; 4060 u8 access_mode_4_2[0x3]; 4061 u8 reserved_at_6[0x7]; 4062 u8 relaxed_ordering_write[0x1]; 4063 u8 reserved_at_e[0x1]; 4064 u8 small_fence_on_rdma_read_response[0x1]; 4065 u8 umr_en[0x1]; 4066 u8 a[0x1]; 4067 u8 rw[0x1]; 4068 u8 rr[0x1]; 4069 u8 lw[0x1]; 4070 u8 lr[0x1]; 4071 u8 access_mode_1_0[0x2]; 4072 u8 reserved_at_18[0x2]; 4073 u8 ma_translation_mode[0x2]; 4074 u8 reserved_at_1c[0x4]; 4075 4076 u8 qpn[0x18]; 4077 u8 mkey_7_0[0x8]; 4078 4079 u8 reserved_at_40[0x20]; 4080 4081 u8 length64[0x1]; 4082 u8 bsf_en[0x1]; 4083 u8 sync_umr[0x1]; 4084 u8 reserved_at_63[0x2]; 4085 u8 expected_sigerr_count[0x1]; 4086 u8 reserved_at_66[0x1]; 4087 u8 en_rinval[0x1]; 4088 u8 pd[0x18]; 4089 4090 u8 start_addr[0x40]; 4091 4092 u8 len[0x40]; 4093 4094 u8 bsf_octword_size[0x20]; 4095 4096 u8 reserved_at_120[0x80]; 4097 4098 u8 translations_octword_size[0x20]; 4099 4100 u8 reserved_at_1c0[0x19]; 4101 u8 relaxed_ordering_read[0x1]; 4102 u8 reserved_at_1d9[0x1]; 4103 u8 log_page_size[0x5]; 4104 4105 u8 reserved_at_1e0[0x20]; 4106 }; 4107 4108 struct mlx5_ifc_pkey_bits { 4109 u8 reserved_at_0[0x10]; 4110 u8 pkey[0x10]; 4111 }; 4112 4113 struct mlx5_ifc_array128_auto_bits { 4114 u8 array128_auto[16][0x8]; 4115 }; 4116 4117 struct mlx5_ifc_hca_vport_context_bits { 4118 u8 field_select[0x20]; 4119 4120 u8 reserved_at_20[0xe0]; 4121 4122 u8 sm_virt_aware[0x1]; 4123 u8 has_smi[0x1]; 4124 u8 has_raw[0x1]; 4125 u8 grh_required[0x1]; 4126 u8 reserved_at_104[0xc]; 4127 u8 port_physical_state[0x4]; 4128 u8 vport_state_policy[0x4]; 4129 u8 port_state[0x4]; 4130 u8 vport_state[0x4]; 4131 4132 u8 reserved_at_120[0x20]; 4133 4134 u8 system_image_guid[0x40]; 4135 4136 u8 port_guid[0x40]; 4137 4138 u8 node_guid[0x40]; 4139 4140 u8 cap_mask1[0x20]; 4141 4142 u8 cap_mask1_field_select[0x20]; 4143 4144 u8 cap_mask2[0x20]; 4145 4146 u8 cap_mask2_field_select[0x20]; 4147 4148 u8 reserved_at_280[0x80]; 4149 4150 u8 lid[0x10]; 4151 u8 reserved_at_310[0x4]; 4152 u8 init_type_reply[0x4]; 4153 u8 lmc[0x3]; 4154 u8 subnet_timeout[0x5]; 4155 4156 u8 sm_lid[0x10]; 4157 u8 sm_sl[0x4]; 4158 u8 reserved_at_334[0xc]; 4159 4160 u8 qkey_violation_counter[0x10]; 4161 u8 pkey_violation_counter[0x10]; 4162 4163 u8 reserved_at_360[0xca0]; 4164 }; 4165 4166 struct mlx5_ifc_esw_vport_context_bits { 4167 u8 fdb_to_vport_reg_c[0x1]; 4168 u8 reserved_at_1[0x2]; 4169 u8 vport_svlan_strip[0x1]; 4170 u8 vport_cvlan_strip[0x1]; 4171 u8 vport_svlan_insert[0x1]; 4172 u8 vport_cvlan_insert[0x2]; 4173 u8 fdb_to_vport_reg_c_id[0x8]; 4174 u8 reserved_at_10[0x10]; 4175 4176 u8 reserved_at_20[0x20]; 4177 4178 u8 svlan_cfi[0x1]; 4179 u8 svlan_pcp[0x3]; 4180 u8 svlan_id[0xc]; 4181 u8 cvlan_cfi[0x1]; 4182 u8 cvlan_pcp[0x3]; 4183 u8 cvlan_id[0xc]; 4184 4185 u8 reserved_at_60[0x720]; 4186 4187 u8 sw_steering_vport_icm_address_rx[0x40]; 4188 4189 u8 sw_steering_vport_icm_address_tx[0x40]; 4190 }; 4191 4192 enum { 4193 MLX5_EQC_STATUS_OK = 0x0, 4194 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4195 }; 4196 4197 enum { 4198 MLX5_EQC_ST_ARMED = 0x9, 4199 MLX5_EQC_ST_FIRED = 0xa, 4200 }; 4201 4202 struct mlx5_ifc_eqc_bits { 4203 u8 status[0x4]; 4204 u8 reserved_at_4[0x9]; 4205 u8 ec[0x1]; 4206 u8 oi[0x1]; 4207 u8 reserved_at_f[0x5]; 4208 u8 st[0x4]; 4209 u8 reserved_at_18[0x8]; 4210 4211 u8 reserved_at_20[0x20]; 4212 4213 u8 reserved_at_40[0x14]; 4214 u8 page_offset[0x6]; 4215 u8 reserved_at_5a[0x6]; 4216 4217 u8 reserved_at_60[0x3]; 4218 u8 log_eq_size[0x5]; 4219 u8 uar_page[0x18]; 4220 4221 u8 reserved_at_80[0x20]; 4222 4223 u8 reserved_at_a0[0x14]; 4224 u8 intr[0xc]; 4225 4226 u8 reserved_at_c0[0x3]; 4227 u8 log_page_size[0x5]; 4228 u8 reserved_at_c8[0x18]; 4229 4230 u8 reserved_at_e0[0x60]; 4231 4232 u8 reserved_at_140[0x8]; 4233 u8 consumer_counter[0x18]; 4234 4235 u8 reserved_at_160[0x8]; 4236 u8 producer_counter[0x18]; 4237 4238 u8 reserved_at_180[0x80]; 4239 }; 4240 4241 enum { 4242 MLX5_DCTC_STATE_ACTIVE = 0x0, 4243 MLX5_DCTC_STATE_DRAINING = 0x1, 4244 MLX5_DCTC_STATE_DRAINED = 0x2, 4245 }; 4246 4247 enum { 4248 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4249 MLX5_DCTC_CS_RES_NA = 0x1, 4250 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4251 }; 4252 4253 enum { 4254 MLX5_DCTC_MTU_256_BYTES = 0x1, 4255 MLX5_DCTC_MTU_512_BYTES = 0x2, 4256 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4257 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4258 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4259 }; 4260 4261 struct mlx5_ifc_dctc_bits { 4262 u8 reserved_at_0[0x4]; 4263 u8 state[0x4]; 4264 u8 reserved_at_8[0x18]; 4265 4266 u8 reserved_at_20[0x8]; 4267 u8 user_index[0x18]; 4268 4269 u8 reserved_at_40[0x8]; 4270 u8 cqn[0x18]; 4271 4272 u8 counter_set_id[0x8]; 4273 u8 atomic_mode[0x4]; 4274 u8 rre[0x1]; 4275 u8 rwe[0x1]; 4276 u8 rae[0x1]; 4277 u8 atomic_like_write_en[0x1]; 4278 u8 latency_sensitive[0x1]; 4279 u8 rlky[0x1]; 4280 u8 free_ar[0x1]; 4281 u8 reserved_at_73[0xd]; 4282 4283 u8 reserved_at_80[0x8]; 4284 u8 cs_res[0x8]; 4285 u8 reserved_at_90[0x3]; 4286 u8 min_rnr_nak[0x5]; 4287 u8 reserved_at_98[0x8]; 4288 4289 u8 reserved_at_a0[0x8]; 4290 u8 srqn_xrqn[0x18]; 4291 4292 u8 reserved_at_c0[0x8]; 4293 u8 pd[0x18]; 4294 4295 u8 tclass[0x8]; 4296 u8 reserved_at_e8[0x4]; 4297 u8 flow_label[0x14]; 4298 4299 u8 dc_access_key[0x40]; 4300 4301 u8 reserved_at_140[0x5]; 4302 u8 mtu[0x3]; 4303 u8 port[0x8]; 4304 u8 pkey_index[0x10]; 4305 4306 u8 reserved_at_160[0x8]; 4307 u8 my_addr_index[0x8]; 4308 u8 reserved_at_170[0x8]; 4309 u8 hop_limit[0x8]; 4310 4311 u8 dc_access_key_violation_count[0x20]; 4312 4313 u8 reserved_at_1a0[0x14]; 4314 u8 dei_cfi[0x1]; 4315 u8 eth_prio[0x3]; 4316 u8 ecn[0x2]; 4317 u8 dscp[0x6]; 4318 4319 u8 reserved_at_1c0[0x20]; 4320 u8 ece[0x20]; 4321 }; 4322 4323 enum { 4324 MLX5_CQC_STATUS_OK = 0x0, 4325 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4326 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4327 }; 4328 4329 enum { 4330 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4331 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4332 }; 4333 4334 enum { 4335 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4336 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4337 MLX5_CQC_ST_FIRED = 0xa, 4338 }; 4339 4340 enum { 4341 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4342 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4343 MLX5_CQ_PERIOD_NUM_MODES 4344 }; 4345 4346 struct mlx5_ifc_cqc_bits { 4347 u8 status[0x4]; 4348 u8 reserved_at_4[0x2]; 4349 u8 dbr_umem_valid[0x1]; 4350 u8 apu_cq[0x1]; 4351 u8 cqe_sz[0x3]; 4352 u8 cc[0x1]; 4353 u8 reserved_at_c[0x1]; 4354 u8 scqe_break_moderation_en[0x1]; 4355 u8 oi[0x1]; 4356 u8 cq_period_mode[0x2]; 4357 u8 cqe_comp_en[0x1]; 4358 u8 mini_cqe_res_format[0x2]; 4359 u8 st[0x4]; 4360 u8 reserved_at_18[0x6]; 4361 u8 cqe_compression_layout[0x2]; 4362 4363 u8 reserved_at_20[0x20]; 4364 4365 u8 reserved_at_40[0x14]; 4366 u8 page_offset[0x6]; 4367 u8 reserved_at_5a[0x6]; 4368 4369 u8 reserved_at_60[0x3]; 4370 u8 log_cq_size[0x5]; 4371 u8 uar_page[0x18]; 4372 4373 u8 reserved_at_80[0x4]; 4374 u8 cq_period[0xc]; 4375 u8 cq_max_count[0x10]; 4376 4377 u8 c_eqn_or_apu_element[0x20]; 4378 4379 u8 reserved_at_c0[0x3]; 4380 u8 log_page_size[0x5]; 4381 u8 reserved_at_c8[0x18]; 4382 4383 u8 reserved_at_e0[0x20]; 4384 4385 u8 reserved_at_100[0x8]; 4386 u8 last_notified_index[0x18]; 4387 4388 u8 reserved_at_120[0x8]; 4389 u8 last_solicit_index[0x18]; 4390 4391 u8 reserved_at_140[0x8]; 4392 u8 consumer_counter[0x18]; 4393 4394 u8 reserved_at_160[0x8]; 4395 u8 producer_counter[0x18]; 4396 4397 u8 reserved_at_180[0x40]; 4398 4399 u8 dbr_addr[0x40]; 4400 }; 4401 4402 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4403 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4404 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4405 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4406 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4407 u8 reserved_at_0[0x800]; 4408 }; 4409 4410 struct mlx5_ifc_query_adapter_param_block_bits { 4411 u8 reserved_at_0[0xc0]; 4412 4413 u8 reserved_at_c0[0x8]; 4414 u8 ieee_vendor_id[0x18]; 4415 4416 u8 reserved_at_e0[0x10]; 4417 u8 vsd_vendor_id[0x10]; 4418 4419 u8 vsd[208][0x8]; 4420 4421 u8 vsd_contd_psid[16][0x8]; 4422 }; 4423 4424 enum { 4425 MLX5_XRQC_STATE_GOOD = 0x0, 4426 MLX5_XRQC_STATE_ERROR = 0x1, 4427 }; 4428 4429 enum { 4430 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4431 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4432 }; 4433 4434 enum { 4435 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4436 }; 4437 4438 struct mlx5_ifc_tag_matching_topology_context_bits { 4439 u8 log_matching_list_sz[0x4]; 4440 u8 reserved_at_4[0xc]; 4441 u8 append_next_index[0x10]; 4442 4443 u8 sw_phase_cnt[0x10]; 4444 u8 hw_phase_cnt[0x10]; 4445 4446 u8 reserved_at_40[0x40]; 4447 }; 4448 4449 struct mlx5_ifc_xrqc_bits { 4450 u8 state[0x4]; 4451 u8 rlkey[0x1]; 4452 u8 reserved_at_5[0xf]; 4453 u8 topology[0x4]; 4454 u8 reserved_at_18[0x4]; 4455 u8 offload[0x4]; 4456 4457 u8 reserved_at_20[0x8]; 4458 u8 user_index[0x18]; 4459 4460 u8 reserved_at_40[0x8]; 4461 u8 cqn[0x18]; 4462 4463 u8 reserved_at_60[0xa0]; 4464 4465 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4466 4467 u8 reserved_at_180[0x280]; 4468 4469 struct mlx5_ifc_wq_bits wq; 4470 }; 4471 4472 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4473 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4474 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4475 u8 reserved_at_0[0x20]; 4476 }; 4477 4478 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4479 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4480 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4481 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4482 u8 reserved_at_0[0x20]; 4483 }; 4484 4485 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4486 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4487 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4488 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4489 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4490 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4491 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4492 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4493 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4494 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4495 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4496 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4497 u8 reserved_at_0[0x7c0]; 4498 }; 4499 4500 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4501 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4502 u8 reserved_at_0[0x7c0]; 4503 }; 4504 4505 union mlx5_ifc_event_auto_bits { 4506 struct mlx5_ifc_comp_event_bits comp_event; 4507 struct mlx5_ifc_dct_events_bits dct_events; 4508 struct mlx5_ifc_qp_events_bits qp_events; 4509 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4510 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4511 struct mlx5_ifc_cq_error_bits cq_error; 4512 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4513 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4514 struct mlx5_ifc_gpio_event_bits gpio_event; 4515 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4516 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4517 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4518 u8 reserved_at_0[0xe0]; 4519 }; 4520 4521 struct mlx5_ifc_health_buffer_bits { 4522 u8 reserved_at_0[0x100]; 4523 4524 u8 assert_existptr[0x20]; 4525 4526 u8 assert_callra[0x20]; 4527 4528 u8 reserved_at_140[0x20]; 4529 4530 u8 time[0x20]; 4531 4532 u8 fw_version[0x20]; 4533 4534 u8 hw_id[0x20]; 4535 4536 u8 rfr[0x1]; 4537 u8 reserved_at_1c1[0x3]; 4538 u8 valid[0x1]; 4539 u8 severity[0x3]; 4540 u8 reserved_at_1c8[0x18]; 4541 4542 u8 irisc_index[0x8]; 4543 u8 synd[0x8]; 4544 u8 ext_synd[0x10]; 4545 }; 4546 4547 struct mlx5_ifc_register_loopback_control_bits { 4548 u8 no_lb[0x1]; 4549 u8 reserved_at_1[0x7]; 4550 u8 port[0x8]; 4551 u8 reserved_at_10[0x10]; 4552 4553 u8 reserved_at_20[0x60]; 4554 }; 4555 4556 struct mlx5_ifc_vport_tc_element_bits { 4557 u8 traffic_class[0x4]; 4558 u8 reserved_at_4[0xc]; 4559 u8 vport_number[0x10]; 4560 }; 4561 4562 struct mlx5_ifc_vport_element_bits { 4563 u8 reserved_at_0[0x10]; 4564 u8 vport_number[0x10]; 4565 }; 4566 4567 enum { 4568 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4569 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4570 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4571 }; 4572 4573 struct mlx5_ifc_tsar_element_bits { 4574 u8 reserved_at_0[0x8]; 4575 u8 tsar_type[0x8]; 4576 u8 reserved_at_10[0x10]; 4577 }; 4578 4579 enum { 4580 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4581 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4582 }; 4583 4584 struct mlx5_ifc_teardown_hca_out_bits { 4585 u8 status[0x8]; 4586 u8 reserved_at_8[0x18]; 4587 4588 u8 syndrome[0x20]; 4589 4590 u8 reserved_at_40[0x3f]; 4591 4592 u8 state[0x1]; 4593 }; 4594 4595 enum { 4596 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4597 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4598 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4599 }; 4600 4601 struct mlx5_ifc_teardown_hca_in_bits { 4602 u8 opcode[0x10]; 4603 u8 reserved_at_10[0x10]; 4604 4605 u8 reserved_at_20[0x10]; 4606 u8 op_mod[0x10]; 4607 4608 u8 reserved_at_40[0x10]; 4609 u8 profile[0x10]; 4610 4611 u8 reserved_at_60[0x20]; 4612 }; 4613 4614 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4615 u8 status[0x8]; 4616 u8 reserved_at_8[0x18]; 4617 4618 u8 syndrome[0x20]; 4619 4620 u8 reserved_at_40[0x40]; 4621 }; 4622 4623 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4624 u8 opcode[0x10]; 4625 u8 uid[0x10]; 4626 4627 u8 reserved_at_20[0x10]; 4628 u8 op_mod[0x10]; 4629 4630 u8 reserved_at_40[0x8]; 4631 u8 qpn[0x18]; 4632 4633 u8 reserved_at_60[0x20]; 4634 4635 u8 opt_param_mask[0x20]; 4636 4637 u8 reserved_at_a0[0x20]; 4638 4639 struct mlx5_ifc_qpc_bits qpc; 4640 4641 u8 reserved_at_800[0x80]; 4642 }; 4643 4644 struct mlx5_ifc_sqd2rts_qp_out_bits { 4645 u8 status[0x8]; 4646 u8 reserved_at_8[0x18]; 4647 4648 u8 syndrome[0x20]; 4649 4650 u8 reserved_at_40[0x40]; 4651 }; 4652 4653 struct mlx5_ifc_sqd2rts_qp_in_bits { 4654 u8 opcode[0x10]; 4655 u8 uid[0x10]; 4656 4657 u8 reserved_at_20[0x10]; 4658 u8 op_mod[0x10]; 4659 4660 u8 reserved_at_40[0x8]; 4661 u8 qpn[0x18]; 4662 4663 u8 reserved_at_60[0x20]; 4664 4665 u8 opt_param_mask[0x20]; 4666 4667 u8 reserved_at_a0[0x20]; 4668 4669 struct mlx5_ifc_qpc_bits qpc; 4670 4671 u8 reserved_at_800[0x80]; 4672 }; 4673 4674 struct mlx5_ifc_set_roce_address_out_bits { 4675 u8 status[0x8]; 4676 u8 reserved_at_8[0x18]; 4677 4678 u8 syndrome[0x20]; 4679 4680 u8 reserved_at_40[0x40]; 4681 }; 4682 4683 struct mlx5_ifc_set_roce_address_in_bits { 4684 u8 opcode[0x10]; 4685 u8 reserved_at_10[0x10]; 4686 4687 u8 reserved_at_20[0x10]; 4688 u8 op_mod[0x10]; 4689 4690 u8 roce_address_index[0x10]; 4691 u8 reserved_at_50[0xc]; 4692 u8 vhca_port_num[0x4]; 4693 4694 u8 reserved_at_60[0x20]; 4695 4696 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4697 }; 4698 4699 struct mlx5_ifc_set_mad_demux_out_bits { 4700 u8 status[0x8]; 4701 u8 reserved_at_8[0x18]; 4702 4703 u8 syndrome[0x20]; 4704 4705 u8 reserved_at_40[0x40]; 4706 }; 4707 4708 enum { 4709 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4710 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4711 }; 4712 4713 struct mlx5_ifc_set_mad_demux_in_bits { 4714 u8 opcode[0x10]; 4715 u8 reserved_at_10[0x10]; 4716 4717 u8 reserved_at_20[0x10]; 4718 u8 op_mod[0x10]; 4719 4720 u8 reserved_at_40[0x20]; 4721 4722 u8 reserved_at_60[0x6]; 4723 u8 demux_mode[0x2]; 4724 u8 reserved_at_68[0x18]; 4725 }; 4726 4727 struct mlx5_ifc_set_l2_table_entry_out_bits { 4728 u8 status[0x8]; 4729 u8 reserved_at_8[0x18]; 4730 4731 u8 syndrome[0x20]; 4732 4733 u8 reserved_at_40[0x40]; 4734 }; 4735 4736 struct mlx5_ifc_set_l2_table_entry_in_bits { 4737 u8 opcode[0x10]; 4738 u8 reserved_at_10[0x10]; 4739 4740 u8 reserved_at_20[0x10]; 4741 u8 op_mod[0x10]; 4742 4743 u8 reserved_at_40[0x60]; 4744 4745 u8 reserved_at_a0[0x8]; 4746 u8 table_index[0x18]; 4747 4748 u8 reserved_at_c0[0x20]; 4749 4750 u8 reserved_at_e0[0x13]; 4751 u8 vlan_valid[0x1]; 4752 u8 vlan[0xc]; 4753 4754 struct mlx5_ifc_mac_address_layout_bits mac_address; 4755 4756 u8 reserved_at_140[0xc0]; 4757 }; 4758 4759 struct mlx5_ifc_set_issi_out_bits { 4760 u8 status[0x8]; 4761 u8 reserved_at_8[0x18]; 4762 4763 u8 syndrome[0x20]; 4764 4765 u8 reserved_at_40[0x40]; 4766 }; 4767 4768 struct mlx5_ifc_set_issi_in_bits { 4769 u8 opcode[0x10]; 4770 u8 reserved_at_10[0x10]; 4771 4772 u8 reserved_at_20[0x10]; 4773 u8 op_mod[0x10]; 4774 4775 u8 reserved_at_40[0x10]; 4776 u8 current_issi[0x10]; 4777 4778 u8 reserved_at_60[0x20]; 4779 }; 4780 4781 struct mlx5_ifc_set_hca_cap_out_bits { 4782 u8 status[0x8]; 4783 u8 reserved_at_8[0x18]; 4784 4785 u8 syndrome[0x20]; 4786 4787 u8 reserved_at_40[0x40]; 4788 }; 4789 4790 struct mlx5_ifc_set_hca_cap_in_bits { 4791 u8 opcode[0x10]; 4792 u8 reserved_at_10[0x10]; 4793 4794 u8 reserved_at_20[0x10]; 4795 u8 op_mod[0x10]; 4796 4797 u8 other_function[0x1]; 4798 u8 reserved_at_41[0xf]; 4799 u8 function_id[0x10]; 4800 4801 u8 reserved_at_60[0x20]; 4802 4803 union mlx5_ifc_hca_cap_union_bits capability; 4804 }; 4805 4806 enum { 4807 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4808 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4809 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4810 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4811 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4812 }; 4813 4814 struct mlx5_ifc_set_fte_out_bits { 4815 u8 status[0x8]; 4816 u8 reserved_at_8[0x18]; 4817 4818 u8 syndrome[0x20]; 4819 4820 u8 reserved_at_40[0x40]; 4821 }; 4822 4823 struct mlx5_ifc_set_fte_in_bits { 4824 u8 opcode[0x10]; 4825 u8 reserved_at_10[0x10]; 4826 4827 u8 reserved_at_20[0x10]; 4828 u8 op_mod[0x10]; 4829 4830 u8 other_vport[0x1]; 4831 u8 reserved_at_41[0xf]; 4832 u8 vport_number[0x10]; 4833 4834 u8 reserved_at_60[0x20]; 4835 4836 u8 table_type[0x8]; 4837 u8 reserved_at_88[0x18]; 4838 4839 u8 reserved_at_a0[0x8]; 4840 u8 table_id[0x18]; 4841 4842 u8 ignore_flow_level[0x1]; 4843 u8 reserved_at_c1[0x17]; 4844 u8 modify_enable_mask[0x8]; 4845 4846 u8 reserved_at_e0[0x20]; 4847 4848 u8 flow_index[0x20]; 4849 4850 u8 reserved_at_120[0xe0]; 4851 4852 struct mlx5_ifc_flow_context_bits flow_context; 4853 }; 4854 4855 struct mlx5_ifc_rts2rts_qp_out_bits { 4856 u8 status[0x8]; 4857 u8 reserved_at_8[0x18]; 4858 4859 u8 syndrome[0x20]; 4860 4861 u8 reserved_at_40[0x20]; 4862 u8 ece[0x20]; 4863 }; 4864 4865 struct mlx5_ifc_rts2rts_qp_in_bits { 4866 u8 opcode[0x10]; 4867 u8 uid[0x10]; 4868 4869 u8 reserved_at_20[0x10]; 4870 u8 op_mod[0x10]; 4871 4872 u8 reserved_at_40[0x8]; 4873 u8 qpn[0x18]; 4874 4875 u8 reserved_at_60[0x20]; 4876 4877 u8 opt_param_mask[0x20]; 4878 4879 u8 ece[0x20]; 4880 4881 struct mlx5_ifc_qpc_bits qpc; 4882 4883 u8 reserved_at_800[0x80]; 4884 }; 4885 4886 struct mlx5_ifc_rtr2rts_qp_out_bits { 4887 u8 status[0x8]; 4888 u8 reserved_at_8[0x18]; 4889 4890 u8 syndrome[0x20]; 4891 4892 u8 reserved_at_40[0x20]; 4893 u8 ece[0x20]; 4894 }; 4895 4896 struct mlx5_ifc_rtr2rts_qp_in_bits { 4897 u8 opcode[0x10]; 4898 u8 uid[0x10]; 4899 4900 u8 reserved_at_20[0x10]; 4901 u8 op_mod[0x10]; 4902 4903 u8 reserved_at_40[0x8]; 4904 u8 qpn[0x18]; 4905 4906 u8 reserved_at_60[0x20]; 4907 4908 u8 opt_param_mask[0x20]; 4909 4910 u8 ece[0x20]; 4911 4912 struct mlx5_ifc_qpc_bits qpc; 4913 4914 u8 reserved_at_800[0x80]; 4915 }; 4916 4917 struct mlx5_ifc_rst2init_qp_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_at_8[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_at_40[0x20]; 4924 u8 ece[0x20]; 4925 }; 4926 4927 struct mlx5_ifc_rst2init_qp_in_bits { 4928 u8 opcode[0x10]; 4929 u8 uid[0x10]; 4930 4931 u8 reserved_at_20[0x10]; 4932 u8 op_mod[0x10]; 4933 4934 u8 reserved_at_40[0x8]; 4935 u8 qpn[0x18]; 4936 4937 u8 reserved_at_60[0x20]; 4938 4939 u8 opt_param_mask[0x20]; 4940 4941 u8 ece[0x20]; 4942 4943 struct mlx5_ifc_qpc_bits qpc; 4944 4945 u8 reserved_at_800[0x80]; 4946 }; 4947 4948 struct mlx5_ifc_query_xrq_out_bits { 4949 u8 status[0x8]; 4950 u8 reserved_at_8[0x18]; 4951 4952 u8 syndrome[0x20]; 4953 4954 u8 reserved_at_40[0x40]; 4955 4956 struct mlx5_ifc_xrqc_bits xrq_context; 4957 }; 4958 4959 struct mlx5_ifc_query_xrq_in_bits { 4960 u8 opcode[0x10]; 4961 u8 reserved_at_10[0x10]; 4962 4963 u8 reserved_at_20[0x10]; 4964 u8 op_mod[0x10]; 4965 4966 u8 reserved_at_40[0x8]; 4967 u8 xrqn[0x18]; 4968 4969 u8 reserved_at_60[0x20]; 4970 }; 4971 4972 struct mlx5_ifc_query_xrc_srq_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_at_8[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_at_40[0x40]; 4979 4980 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4981 4982 u8 reserved_at_280[0x600]; 4983 4984 u8 pas[][0x40]; 4985 }; 4986 4987 struct mlx5_ifc_query_xrc_srq_in_bits { 4988 u8 opcode[0x10]; 4989 u8 reserved_at_10[0x10]; 4990 4991 u8 reserved_at_20[0x10]; 4992 u8 op_mod[0x10]; 4993 4994 u8 reserved_at_40[0x8]; 4995 u8 xrc_srqn[0x18]; 4996 4997 u8 reserved_at_60[0x20]; 4998 }; 4999 5000 enum { 5001 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5002 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5003 }; 5004 5005 struct mlx5_ifc_query_vport_state_out_bits { 5006 u8 status[0x8]; 5007 u8 reserved_at_8[0x18]; 5008 5009 u8 syndrome[0x20]; 5010 5011 u8 reserved_at_40[0x20]; 5012 5013 u8 reserved_at_60[0x18]; 5014 u8 admin_state[0x4]; 5015 u8 state[0x4]; 5016 }; 5017 5018 enum { 5019 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5020 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5021 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5022 }; 5023 5024 struct mlx5_ifc_arm_monitor_counter_in_bits { 5025 u8 opcode[0x10]; 5026 u8 uid[0x10]; 5027 5028 u8 reserved_at_20[0x10]; 5029 u8 op_mod[0x10]; 5030 5031 u8 reserved_at_40[0x20]; 5032 5033 u8 reserved_at_60[0x20]; 5034 }; 5035 5036 struct mlx5_ifc_arm_monitor_counter_out_bits { 5037 u8 status[0x8]; 5038 u8 reserved_at_8[0x18]; 5039 5040 u8 syndrome[0x20]; 5041 5042 u8 reserved_at_40[0x40]; 5043 }; 5044 5045 enum { 5046 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5047 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5048 }; 5049 5050 enum mlx5_monitor_counter_ppcnt { 5051 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5052 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5053 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5054 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5055 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5056 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5057 }; 5058 5059 enum { 5060 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5061 }; 5062 5063 struct mlx5_ifc_monitor_counter_output_bits { 5064 u8 reserved_at_0[0x4]; 5065 u8 type[0x4]; 5066 u8 reserved_at_8[0x8]; 5067 u8 counter[0x10]; 5068 5069 u8 counter_group_id[0x20]; 5070 }; 5071 5072 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5073 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5074 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5075 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5076 5077 struct mlx5_ifc_set_monitor_counter_in_bits { 5078 u8 opcode[0x10]; 5079 u8 uid[0x10]; 5080 5081 u8 reserved_at_20[0x10]; 5082 u8 op_mod[0x10]; 5083 5084 u8 reserved_at_40[0x10]; 5085 u8 num_of_counters[0x10]; 5086 5087 u8 reserved_at_60[0x20]; 5088 5089 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5090 }; 5091 5092 struct mlx5_ifc_set_monitor_counter_out_bits { 5093 u8 status[0x8]; 5094 u8 reserved_at_8[0x18]; 5095 5096 u8 syndrome[0x20]; 5097 5098 u8 reserved_at_40[0x40]; 5099 }; 5100 5101 struct mlx5_ifc_query_vport_state_in_bits { 5102 u8 opcode[0x10]; 5103 u8 reserved_at_10[0x10]; 5104 5105 u8 reserved_at_20[0x10]; 5106 u8 op_mod[0x10]; 5107 5108 u8 other_vport[0x1]; 5109 u8 reserved_at_41[0xf]; 5110 u8 vport_number[0x10]; 5111 5112 u8 reserved_at_60[0x20]; 5113 }; 5114 5115 struct mlx5_ifc_query_vnic_env_out_bits { 5116 u8 status[0x8]; 5117 u8 reserved_at_8[0x18]; 5118 5119 u8 syndrome[0x20]; 5120 5121 u8 reserved_at_40[0x40]; 5122 5123 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5124 }; 5125 5126 enum { 5127 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5128 }; 5129 5130 struct mlx5_ifc_query_vnic_env_in_bits { 5131 u8 opcode[0x10]; 5132 u8 reserved_at_10[0x10]; 5133 5134 u8 reserved_at_20[0x10]; 5135 u8 op_mod[0x10]; 5136 5137 u8 other_vport[0x1]; 5138 u8 reserved_at_41[0xf]; 5139 u8 vport_number[0x10]; 5140 5141 u8 reserved_at_60[0x20]; 5142 }; 5143 5144 struct mlx5_ifc_query_vport_counter_out_bits { 5145 u8 status[0x8]; 5146 u8 reserved_at_8[0x18]; 5147 5148 u8 syndrome[0x20]; 5149 5150 u8 reserved_at_40[0x40]; 5151 5152 struct mlx5_ifc_traffic_counter_bits received_errors; 5153 5154 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5155 5156 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5157 5158 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5159 5160 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5161 5162 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5163 5164 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5165 5166 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5167 5168 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5169 5170 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5171 5172 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5173 5174 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5175 5176 u8 reserved_at_680[0xa00]; 5177 }; 5178 5179 enum { 5180 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5181 }; 5182 5183 struct mlx5_ifc_query_vport_counter_in_bits { 5184 u8 opcode[0x10]; 5185 u8 reserved_at_10[0x10]; 5186 5187 u8 reserved_at_20[0x10]; 5188 u8 op_mod[0x10]; 5189 5190 u8 other_vport[0x1]; 5191 u8 reserved_at_41[0xb]; 5192 u8 port_num[0x4]; 5193 u8 vport_number[0x10]; 5194 5195 u8 reserved_at_60[0x60]; 5196 5197 u8 clear[0x1]; 5198 u8 reserved_at_c1[0x1f]; 5199 5200 u8 reserved_at_e0[0x20]; 5201 }; 5202 5203 struct mlx5_ifc_query_tis_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_at_8[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_at_40[0x40]; 5210 5211 struct mlx5_ifc_tisc_bits tis_context; 5212 }; 5213 5214 struct mlx5_ifc_query_tis_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_at_10[0x10]; 5217 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 reserved_at_40[0x8]; 5222 u8 tisn[0x18]; 5223 5224 u8 reserved_at_60[0x20]; 5225 }; 5226 5227 struct mlx5_ifc_query_tir_out_bits { 5228 u8 status[0x8]; 5229 u8 reserved_at_8[0x18]; 5230 5231 u8 syndrome[0x20]; 5232 5233 u8 reserved_at_40[0xc0]; 5234 5235 struct mlx5_ifc_tirc_bits tir_context; 5236 }; 5237 5238 struct mlx5_ifc_query_tir_in_bits { 5239 u8 opcode[0x10]; 5240 u8 reserved_at_10[0x10]; 5241 5242 u8 reserved_at_20[0x10]; 5243 u8 op_mod[0x10]; 5244 5245 u8 reserved_at_40[0x8]; 5246 u8 tirn[0x18]; 5247 5248 u8 reserved_at_60[0x20]; 5249 }; 5250 5251 struct mlx5_ifc_query_srq_out_bits { 5252 u8 status[0x8]; 5253 u8 reserved_at_8[0x18]; 5254 5255 u8 syndrome[0x20]; 5256 5257 u8 reserved_at_40[0x40]; 5258 5259 struct mlx5_ifc_srqc_bits srq_context_entry; 5260 5261 u8 reserved_at_280[0x600]; 5262 5263 u8 pas[][0x40]; 5264 }; 5265 5266 struct mlx5_ifc_query_srq_in_bits { 5267 u8 opcode[0x10]; 5268 u8 reserved_at_10[0x10]; 5269 5270 u8 reserved_at_20[0x10]; 5271 u8 op_mod[0x10]; 5272 5273 u8 reserved_at_40[0x8]; 5274 u8 srqn[0x18]; 5275 5276 u8 reserved_at_60[0x20]; 5277 }; 5278 5279 struct mlx5_ifc_query_sq_out_bits { 5280 u8 status[0x8]; 5281 u8 reserved_at_8[0x18]; 5282 5283 u8 syndrome[0x20]; 5284 5285 u8 reserved_at_40[0xc0]; 5286 5287 struct mlx5_ifc_sqc_bits sq_context; 5288 }; 5289 5290 struct mlx5_ifc_query_sq_in_bits { 5291 u8 opcode[0x10]; 5292 u8 reserved_at_10[0x10]; 5293 5294 u8 reserved_at_20[0x10]; 5295 u8 op_mod[0x10]; 5296 5297 u8 reserved_at_40[0x8]; 5298 u8 sqn[0x18]; 5299 5300 u8 reserved_at_60[0x20]; 5301 }; 5302 5303 struct mlx5_ifc_query_special_contexts_out_bits { 5304 u8 status[0x8]; 5305 u8 reserved_at_8[0x18]; 5306 5307 u8 syndrome[0x20]; 5308 5309 u8 dump_fill_mkey[0x20]; 5310 5311 u8 resd_lkey[0x20]; 5312 5313 u8 null_mkey[0x20]; 5314 5315 u8 terminate_scatter_list_mkey[0x20]; 5316 5317 u8 repeated_mkey[0x20]; 5318 5319 u8 reserved_at_a0[0x20]; 5320 }; 5321 5322 struct mlx5_ifc_query_special_contexts_in_bits { 5323 u8 opcode[0x10]; 5324 u8 reserved_at_10[0x10]; 5325 5326 u8 reserved_at_20[0x10]; 5327 u8 op_mod[0x10]; 5328 5329 u8 reserved_at_40[0x40]; 5330 }; 5331 5332 struct mlx5_ifc_query_scheduling_element_out_bits { 5333 u8 opcode[0x10]; 5334 u8 reserved_at_10[0x10]; 5335 5336 u8 reserved_at_20[0x10]; 5337 u8 op_mod[0x10]; 5338 5339 u8 reserved_at_40[0xc0]; 5340 5341 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5342 5343 u8 reserved_at_300[0x100]; 5344 }; 5345 5346 enum { 5347 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5348 SCHEDULING_HIERARCHY_NIC = 0x3, 5349 }; 5350 5351 struct mlx5_ifc_query_scheduling_element_in_bits { 5352 u8 opcode[0x10]; 5353 u8 reserved_at_10[0x10]; 5354 5355 u8 reserved_at_20[0x10]; 5356 u8 op_mod[0x10]; 5357 5358 u8 scheduling_hierarchy[0x8]; 5359 u8 reserved_at_48[0x18]; 5360 5361 u8 scheduling_element_id[0x20]; 5362 5363 u8 reserved_at_80[0x180]; 5364 }; 5365 5366 struct mlx5_ifc_query_rqt_out_bits { 5367 u8 status[0x8]; 5368 u8 reserved_at_8[0x18]; 5369 5370 u8 syndrome[0x20]; 5371 5372 u8 reserved_at_40[0xc0]; 5373 5374 struct mlx5_ifc_rqtc_bits rqt_context; 5375 }; 5376 5377 struct mlx5_ifc_query_rqt_in_bits { 5378 u8 opcode[0x10]; 5379 u8 reserved_at_10[0x10]; 5380 5381 u8 reserved_at_20[0x10]; 5382 u8 op_mod[0x10]; 5383 5384 u8 reserved_at_40[0x8]; 5385 u8 rqtn[0x18]; 5386 5387 u8 reserved_at_60[0x20]; 5388 }; 5389 5390 struct mlx5_ifc_query_rq_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_at_8[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_at_40[0xc0]; 5397 5398 struct mlx5_ifc_rqc_bits rq_context; 5399 }; 5400 5401 struct mlx5_ifc_query_rq_in_bits { 5402 u8 opcode[0x10]; 5403 u8 reserved_at_10[0x10]; 5404 5405 u8 reserved_at_20[0x10]; 5406 u8 op_mod[0x10]; 5407 5408 u8 reserved_at_40[0x8]; 5409 u8 rqn[0x18]; 5410 5411 u8 reserved_at_60[0x20]; 5412 }; 5413 5414 struct mlx5_ifc_query_roce_address_out_bits { 5415 u8 status[0x8]; 5416 u8 reserved_at_8[0x18]; 5417 5418 u8 syndrome[0x20]; 5419 5420 u8 reserved_at_40[0x40]; 5421 5422 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5423 }; 5424 5425 struct mlx5_ifc_query_roce_address_in_bits { 5426 u8 opcode[0x10]; 5427 u8 reserved_at_10[0x10]; 5428 5429 u8 reserved_at_20[0x10]; 5430 u8 op_mod[0x10]; 5431 5432 u8 roce_address_index[0x10]; 5433 u8 reserved_at_50[0xc]; 5434 u8 vhca_port_num[0x4]; 5435 5436 u8 reserved_at_60[0x20]; 5437 }; 5438 5439 struct mlx5_ifc_query_rmp_out_bits { 5440 u8 status[0x8]; 5441 u8 reserved_at_8[0x18]; 5442 5443 u8 syndrome[0x20]; 5444 5445 u8 reserved_at_40[0xc0]; 5446 5447 struct mlx5_ifc_rmpc_bits rmp_context; 5448 }; 5449 5450 struct mlx5_ifc_query_rmp_in_bits { 5451 u8 opcode[0x10]; 5452 u8 reserved_at_10[0x10]; 5453 5454 u8 reserved_at_20[0x10]; 5455 u8 op_mod[0x10]; 5456 5457 u8 reserved_at_40[0x8]; 5458 u8 rmpn[0x18]; 5459 5460 u8 reserved_at_60[0x20]; 5461 }; 5462 5463 struct mlx5_ifc_cqe_error_syndrome_bits { 5464 u8 hw_error_syndrome[0x8]; 5465 u8 hw_syndrome_type[0x4]; 5466 u8 reserved_at_c[0x4]; 5467 u8 vendor_error_syndrome[0x8]; 5468 u8 syndrome[0x8]; 5469 }; 5470 5471 struct mlx5_ifc_qp_context_extension_bits { 5472 u8 reserved_at_0[0x60]; 5473 5474 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5475 5476 u8 reserved_at_80[0x580]; 5477 }; 5478 5479 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5480 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5481 5482 u8 pas[0][0x40]; 5483 }; 5484 5485 struct mlx5_ifc_qp_pas_list_in_bits { 5486 struct mlx5_ifc_cmd_pas_bits pas[0]; 5487 }; 5488 5489 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5490 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5491 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5492 }; 5493 5494 struct mlx5_ifc_query_qp_out_bits { 5495 u8 status[0x8]; 5496 u8 reserved_at_8[0x18]; 5497 5498 u8 syndrome[0x20]; 5499 5500 u8 reserved_at_40[0x40]; 5501 5502 u8 opt_param_mask[0x20]; 5503 5504 u8 ece[0x20]; 5505 5506 struct mlx5_ifc_qpc_bits qpc; 5507 5508 u8 reserved_at_800[0x80]; 5509 5510 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5511 }; 5512 5513 struct mlx5_ifc_query_qp_in_bits { 5514 u8 opcode[0x10]; 5515 u8 reserved_at_10[0x10]; 5516 5517 u8 reserved_at_20[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 qpc_ext[0x1]; 5521 u8 reserved_at_41[0x7]; 5522 u8 qpn[0x18]; 5523 5524 u8 reserved_at_60[0x20]; 5525 }; 5526 5527 struct mlx5_ifc_query_q_counter_out_bits { 5528 u8 status[0x8]; 5529 u8 reserved_at_8[0x18]; 5530 5531 u8 syndrome[0x20]; 5532 5533 u8 reserved_at_40[0x40]; 5534 5535 u8 rx_write_requests[0x20]; 5536 5537 u8 reserved_at_a0[0x20]; 5538 5539 u8 rx_read_requests[0x20]; 5540 5541 u8 reserved_at_e0[0x20]; 5542 5543 u8 rx_atomic_requests[0x20]; 5544 5545 u8 reserved_at_120[0x20]; 5546 5547 u8 rx_dct_connect[0x20]; 5548 5549 u8 reserved_at_160[0x20]; 5550 5551 u8 out_of_buffer[0x20]; 5552 5553 u8 reserved_at_1a0[0x20]; 5554 5555 u8 out_of_sequence[0x20]; 5556 5557 u8 reserved_at_1e0[0x20]; 5558 5559 u8 duplicate_request[0x20]; 5560 5561 u8 reserved_at_220[0x20]; 5562 5563 u8 rnr_nak_retry_err[0x20]; 5564 5565 u8 reserved_at_260[0x20]; 5566 5567 u8 packet_seq_err[0x20]; 5568 5569 u8 reserved_at_2a0[0x20]; 5570 5571 u8 implied_nak_seq_err[0x20]; 5572 5573 u8 reserved_at_2e0[0x20]; 5574 5575 u8 local_ack_timeout_err[0x20]; 5576 5577 u8 reserved_at_320[0xa0]; 5578 5579 u8 resp_local_length_error[0x20]; 5580 5581 u8 req_local_length_error[0x20]; 5582 5583 u8 resp_local_qp_error[0x20]; 5584 5585 u8 local_operation_error[0x20]; 5586 5587 u8 resp_local_protection[0x20]; 5588 5589 u8 req_local_protection[0x20]; 5590 5591 u8 resp_cqe_error[0x20]; 5592 5593 u8 req_cqe_error[0x20]; 5594 5595 u8 req_mw_binding[0x20]; 5596 5597 u8 req_bad_response[0x20]; 5598 5599 u8 req_remote_invalid_request[0x20]; 5600 5601 u8 resp_remote_invalid_request[0x20]; 5602 5603 u8 req_remote_access_errors[0x20]; 5604 5605 u8 resp_remote_access_errors[0x20]; 5606 5607 u8 req_remote_operation_errors[0x20]; 5608 5609 u8 req_transport_retries_exceeded[0x20]; 5610 5611 u8 cq_overflow[0x20]; 5612 5613 u8 resp_cqe_flush_error[0x20]; 5614 5615 u8 req_cqe_flush_error[0x20]; 5616 5617 u8 reserved_at_620[0x20]; 5618 5619 u8 roce_adp_retrans[0x20]; 5620 5621 u8 roce_adp_retrans_to[0x20]; 5622 5623 u8 roce_slow_restart[0x20]; 5624 5625 u8 roce_slow_restart_cnps[0x20]; 5626 5627 u8 roce_slow_restart_trans[0x20]; 5628 5629 u8 reserved_at_6e0[0x120]; 5630 }; 5631 5632 struct mlx5_ifc_query_q_counter_in_bits { 5633 u8 opcode[0x10]; 5634 u8 reserved_at_10[0x10]; 5635 5636 u8 reserved_at_20[0x10]; 5637 u8 op_mod[0x10]; 5638 5639 u8 other_vport[0x1]; 5640 u8 reserved_at_41[0xf]; 5641 u8 vport_number[0x10]; 5642 5643 u8 reserved_at_60[0x60]; 5644 5645 u8 clear[0x1]; 5646 u8 aggregate[0x1]; 5647 u8 reserved_at_c2[0x1e]; 5648 5649 u8 reserved_at_e0[0x18]; 5650 u8 counter_set_id[0x8]; 5651 }; 5652 5653 struct mlx5_ifc_query_pages_out_bits { 5654 u8 status[0x8]; 5655 u8 reserved_at_8[0x18]; 5656 5657 u8 syndrome[0x20]; 5658 5659 u8 embedded_cpu_function[0x1]; 5660 u8 reserved_at_41[0xf]; 5661 u8 function_id[0x10]; 5662 5663 u8 num_pages[0x20]; 5664 }; 5665 5666 enum { 5667 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5668 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5669 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5670 }; 5671 5672 struct mlx5_ifc_query_pages_in_bits { 5673 u8 opcode[0x10]; 5674 u8 reserved_at_10[0x10]; 5675 5676 u8 reserved_at_20[0x10]; 5677 u8 op_mod[0x10]; 5678 5679 u8 embedded_cpu_function[0x1]; 5680 u8 reserved_at_41[0xf]; 5681 u8 function_id[0x10]; 5682 5683 u8 reserved_at_60[0x20]; 5684 }; 5685 5686 struct mlx5_ifc_query_nic_vport_context_out_bits { 5687 u8 status[0x8]; 5688 u8 reserved_at_8[0x18]; 5689 5690 u8 syndrome[0x20]; 5691 5692 u8 reserved_at_40[0x40]; 5693 5694 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5695 }; 5696 5697 struct mlx5_ifc_query_nic_vport_context_in_bits { 5698 u8 opcode[0x10]; 5699 u8 reserved_at_10[0x10]; 5700 5701 u8 reserved_at_20[0x10]; 5702 u8 op_mod[0x10]; 5703 5704 u8 other_vport[0x1]; 5705 u8 reserved_at_41[0xf]; 5706 u8 vport_number[0x10]; 5707 5708 u8 reserved_at_60[0x5]; 5709 u8 allowed_list_type[0x3]; 5710 u8 reserved_at_68[0x18]; 5711 }; 5712 5713 struct mlx5_ifc_query_mkey_out_bits { 5714 u8 status[0x8]; 5715 u8 reserved_at_8[0x18]; 5716 5717 u8 syndrome[0x20]; 5718 5719 u8 reserved_at_40[0x40]; 5720 5721 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5722 5723 u8 reserved_at_280[0x600]; 5724 5725 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5726 5727 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5728 }; 5729 5730 struct mlx5_ifc_query_mkey_in_bits { 5731 u8 opcode[0x10]; 5732 u8 reserved_at_10[0x10]; 5733 5734 u8 reserved_at_20[0x10]; 5735 u8 op_mod[0x10]; 5736 5737 u8 reserved_at_40[0x8]; 5738 u8 mkey_index[0x18]; 5739 5740 u8 pg_access[0x1]; 5741 u8 reserved_at_61[0x1f]; 5742 }; 5743 5744 struct mlx5_ifc_query_mad_demux_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_at_8[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_at_40[0x40]; 5751 5752 u8 mad_dumux_parameters_block[0x20]; 5753 }; 5754 5755 struct mlx5_ifc_query_mad_demux_in_bits { 5756 u8 opcode[0x10]; 5757 u8 reserved_at_10[0x10]; 5758 5759 u8 reserved_at_20[0x10]; 5760 u8 op_mod[0x10]; 5761 5762 u8 reserved_at_40[0x40]; 5763 }; 5764 5765 struct mlx5_ifc_query_l2_table_entry_out_bits { 5766 u8 status[0x8]; 5767 u8 reserved_at_8[0x18]; 5768 5769 u8 syndrome[0x20]; 5770 5771 u8 reserved_at_40[0xa0]; 5772 5773 u8 reserved_at_e0[0x13]; 5774 u8 vlan_valid[0x1]; 5775 u8 vlan[0xc]; 5776 5777 struct mlx5_ifc_mac_address_layout_bits mac_address; 5778 5779 u8 reserved_at_140[0xc0]; 5780 }; 5781 5782 struct mlx5_ifc_query_l2_table_entry_in_bits { 5783 u8 opcode[0x10]; 5784 u8 reserved_at_10[0x10]; 5785 5786 u8 reserved_at_20[0x10]; 5787 u8 op_mod[0x10]; 5788 5789 u8 reserved_at_40[0x60]; 5790 5791 u8 reserved_at_a0[0x8]; 5792 u8 table_index[0x18]; 5793 5794 u8 reserved_at_c0[0x140]; 5795 }; 5796 5797 struct mlx5_ifc_query_issi_out_bits { 5798 u8 status[0x8]; 5799 u8 reserved_at_8[0x18]; 5800 5801 u8 syndrome[0x20]; 5802 5803 u8 reserved_at_40[0x10]; 5804 u8 current_issi[0x10]; 5805 5806 u8 reserved_at_60[0xa0]; 5807 5808 u8 reserved_at_100[76][0x8]; 5809 u8 supported_issi_dw0[0x20]; 5810 }; 5811 5812 struct mlx5_ifc_query_issi_in_bits { 5813 u8 opcode[0x10]; 5814 u8 reserved_at_10[0x10]; 5815 5816 u8 reserved_at_20[0x10]; 5817 u8 op_mod[0x10]; 5818 5819 u8 reserved_at_40[0x40]; 5820 }; 5821 5822 struct mlx5_ifc_set_driver_version_out_bits { 5823 u8 status[0x8]; 5824 u8 reserved_0[0x18]; 5825 5826 u8 syndrome[0x20]; 5827 u8 reserved_1[0x40]; 5828 }; 5829 5830 struct mlx5_ifc_set_driver_version_in_bits { 5831 u8 opcode[0x10]; 5832 u8 reserved_0[0x10]; 5833 5834 u8 reserved_1[0x10]; 5835 u8 op_mod[0x10]; 5836 5837 u8 reserved_2[0x40]; 5838 u8 driver_version[64][0x8]; 5839 }; 5840 5841 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5842 u8 status[0x8]; 5843 u8 reserved_at_8[0x18]; 5844 5845 u8 syndrome[0x20]; 5846 5847 u8 reserved_at_40[0x40]; 5848 5849 struct mlx5_ifc_pkey_bits pkey[]; 5850 }; 5851 5852 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5853 u8 opcode[0x10]; 5854 u8 reserved_at_10[0x10]; 5855 5856 u8 reserved_at_20[0x10]; 5857 u8 op_mod[0x10]; 5858 5859 u8 other_vport[0x1]; 5860 u8 reserved_at_41[0xb]; 5861 u8 port_num[0x4]; 5862 u8 vport_number[0x10]; 5863 5864 u8 reserved_at_60[0x10]; 5865 u8 pkey_index[0x10]; 5866 }; 5867 5868 enum { 5869 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5870 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5871 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5872 }; 5873 5874 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5875 u8 status[0x8]; 5876 u8 reserved_at_8[0x18]; 5877 5878 u8 syndrome[0x20]; 5879 5880 u8 reserved_at_40[0x20]; 5881 5882 u8 gids_num[0x10]; 5883 u8 reserved_at_70[0x10]; 5884 5885 struct mlx5_ifc_array128_auto_bits gid[]; 5886 }; 5887 5888 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5889 u8 opcode[0x10]; 5890 u8 reserved_at_10[0x10]; 5891 5892 u8 reserved_at_20[0x10]; 5893 u8 op_mod[0x10]; 5894 5895 u8 other_vport[0x1]; 5896 u8 reserved_at_41[0xb]; 5897 u8 port_num[0x4]; 5898 u8 vport_number[0x10]; 5899 5900 u8 reserved_at_60[0x10]; 5901 u8 gid_index[0x10]; 5902 }; 5903 5904 struct mlx5_ifc_query_hca_vport_context_out_bits { 5905 u8 status[0x8]; 5906 u8 reserved_at_8[0x18]; 5907 5908 u8 syndrome[0x20]; 5909 5910 u8 reserved_at_40[0x40]; 5911 5912 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5913 }; 5914 5915 struct mlx5_ifc_query_hca_vport_context_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_at_10[0x10]; 5918 5919 u8 reserved_at_20[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 other_vport[0x1]; 5923 u8 reserved_at_41[0xb]; 5924 u8 port_num[0x4]; 5925 u8 vport_number[0x10]; 5926 5927 u8 reserved_at_60[0x20]; 5928 }; 5929 5930 struct mlx5_ifc_query_hca_cap_out_bits { 5931 u8 status[0x8]; 5932 u8 reserved_at_8[0x18]; 5933 5934 u8 syndrome[0x20]; 5935 5936 u8 reserved_at_40[0x40]; 5937 5938 union mlx5_ifc_hca_cap_union_bits capability; 5939 }; 5940 5941 struct mlx5_ifc_query_hca_cap_in_bits { 5942 u8 opcode[0x10]; 5943 u8 reserved_at_10[0x10]; 5944 5945 u8 reserved_at_20[0x10]; 5946 u8 op_mod[0x10]; 5947 5948 u8 other_function[0x1]; 5949 u8 reserved_at_41[0xf]; 5950 u8 function_id[0x10]; 5951 5952 u8 reserved_at_60[0x20]; 5953 }; 5954 5955 struct mlx5_ifc_other_hca_cap_bits { 5956 u8 roce[0x1]; 5957 u8 reserved_at_1[0x27f]; 5958 }; 5959 5960 struct mlx5_ifc_query_other_hca_cap_out_bits { 5961 u8 status[0x8]; 5962 u8 reserved_at_8[0x18]; 5963 5964 u8 syndrome[0x20]; 5965 5966 u8 reserved_at_40[0x40]; 5967 5968 struct mlx5_ifc_other_hca_cap_bits other_capability; 5969 }; 5970 5971 struct mlx5_ifc_query_other_hca_cap_in_bits { 5972 u8 opcode[0x10]; 5973 u8 reserved_at_10[0x10]; 5974 5975 u8 reserved_at_20[0x10]; 5976 u8 op_mod[0x10]; 5977 5978 u8 reserved_at_40[0x10]; 5979 u8 function_id[0x10]; 5980 5981 u8 reserved_at_60[0x20]; 5982 }; 5983 5984 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5985 u8 status[0x8]; 5986 u8 reserved_at_8[0x18]; 5987 5988 u8 syndrome[0x20]; 5989 5990 u8 reserved_at_40[0x40]; 5991 }; 5992 5993 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5994 u8 opcode[0x10]; 5995 u8 reserved_at_10[0x10]; 5996 5997 u8 reserved_at_20[0x10]; 5998 u8 op_mod[0x10]; 5999 6000 u8 reserved_at_40[0x10]; 6001 u8 function_id[0x10]; 6002 u8 field_select[0x20]; 6003 6004 struct mlx5_ifc_other_hca_cap_bits other_capability; 6005 }; 6006 6007 struct mlx5_ifc_flow_table_context_bits { 6008 u8 reformat_en[0x1]; 6009 u8 decap_en[0x1]; 6010 u8 sw_owner[0x1]; 6011 u8 termination_table[0x1]; 6012 u8 table_miss_action[0x4]; 6013 u8 level[0x8]; 6014 u8 reserved_at_10[0x8]; 6015 u8 log_size[0x8]; 6016 6017 u8 reserved_at_20[0x8]; 6018 u8 table_miss_id[0x18]; 6019 6020 u8 reserved_at_40[0x8]; 6021 u8 lag_master_next_table_id[0x18]; 6022 6023 u8 reserved_at_60[0x60]; 6024 6025 u8 sw_owner_icm_root_1[0x40]; 6026 6027 u8 sw_owner_icm_root_0[0x40]; 6028 6029 }; 6030 6031 struct mlx5_ifc_query_flow_table_out_bits { 6032 u8 status[0x8]; 6033 u8 reserved_at_8[0x18]; 6034 6035 u8 syndrome[0x20]; 6036 6037 u8 reserved_at_40[0x80]; 6038 6039 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6040 }; 6041 6042 struct mlx5_ifc_query_flow_table_in_bits { 6043 u8 opcode[0x10]; 6044 u8 reserved_at_10[0x10]; 6045 6046 u8 reserved_at_20[0x10]; 6047 u8 op_mod[0x10]; 6048 6049 u8 reserved_at_40[0x40]; 6050 6051 u8 table_type[0x8]; 6052 u8 reserved_at_88[0x18]; 6053 6054 u8 reserved_at_a0[0x8]; 6055 u8 table_id[0x18]; 6056 6057 u8 reserved_at_c0[0x140]; 6058 }; 6059 6060 struct mlx5_ifc_query_fte_out_bits { 6061 u8 status[0x8]; 6062 u8 reserved_at_8[0x18]; 6063 6064 u8 syndrome[0x20]; 6065 6066 u8 reserved_at_40[0x1c0]; 6067 6068 struct mlx5_ifc_flow_context_bits flow_context; 6069 }; 6070 6071 struct mlx5_ifc_query_fte_in_bits { 6072 u8 opcode[0x10]; 6073 u8 reserved_at_10[0x10]; 6074 6075 u8 reserved_at_20[0x10]; 6076 u8 op_mod[0x10]; 6077 6078 u8 reserved_at_40[0x40]; 6079 6080 u8 table_type[0x8]; 6081 u8 reserved_at_88[0x18]; 6082 6083 u8 reserved_at_a0[0x8]; 6084 u8 table_id[0x18]; 6085 6086 u8 reserved_at_c0[0x40]; 6087 6088 u8 flow_index[0x20]; 6089 6090 u8 reserved_at_120[0xe0]; 6091 }; 6092 6093 struct mlx5_ifc_match_definer_format_0_bits { 6094 u8 reserved_at_0[0x100]; 6095 6096 u8 metadata_reg_c_0[0x20]; 6097 6098 u8 metadata_reg_c_1[0x20]; 6099 6100 u8 outer_dmac_47_16[0x20]; 6101 6102 u8 outer_dmac_15_0[0x10]; 6103 u8 outer_ethertype[0x10]; 6104 6105 u8 reserved_at_180[0x1]; 6106 u8 sx_sniffer[0x1]; 6107 u8 functional_lb[0x1]; 6108 u8 outer_ip_frag[0x1]; 6109 u8 outer_qp_type[0x2]; 6110 u8 outer_encap_type[0x2]; 6111 u8 port_number[0x2]; 6112 u8 outer_l3_type[0x2]; 6113 u8 outer_l4_type[0x2]; 6114 u8 outer_first_vlan_type[0x2]; 6115 u8 outer_first_vlan_prio[0x3]; 6116 u8 outer_first_vlan_cfi[0x1]; 6117 u8 outer_first_vlan_vid[0xc]; 6118 6119 u8 outer_l4_type_ext[0x4]; 6120 u8 reserved_at_1a4[0x2]; 6121 u8 outer_ipsec_layer[0x2]; 6122 u8 outer_l2_type[0x2]; 6123 u8 force_lb[0x1]; 6124 u8 outer_l2_ok[0x1]; 6125 u8 outer_l3_ok[0x1]; 6126 u8 outer_l4_ok[0x1]; 6127 u8 outer_second_vlan_type[0x2]; 6128 u8 outer_second_vlan_prio[0x3]; 6129 u8 outer_second_vlan_cfi[0x1]; 6130 u8 outer_second_vlan_vid[0xc]; 6131 6132 u8 outer_smac_47_16[0x20]; 6133 6134 u8 outer_smac_15_0[0x10]; 6135 u8 inner_ipv4_checksum_ok[0x1]; 6136 u8 inner_l4_checksum_ok[0x1]; 6137 u8 outer_ipv4_checksum_ok[0x1]; 6138 u8 outer_l4_checksum_ok[0x1]; 6139 u8 inner_l3_ok[0x1]; 6140 u8 inner_l4_ok[0x1]; 6141 u8 outer_l3_ok_duplicate[0x1]; 6142 u8 outer_l4_ok_duplicate[0x1]; 6143 u8 outer_tcp_cwr[0x1]; 6144 u8 outer_tcp_ece[0x1]; 6145 u8 outer_tcp_urg[0x1]; 6146 u8 outer_tcp_ack[0x1]; 6147 u8 outer_tcp_psh[0x1]; 6148 u8 outer_tcp_rst[0x1]; 6149 u8 outer_tcp_syn[0x1]; 6150 u8 outer_tcp_fin[0x1]; 6151 }; 6152 6153 struct mlx5_ifc_match_definer_format_22_bits { 6154 u8 reserved_at_0[0x100]; 6155 6156 u8 outer_ip_src_addr[0x20]; 6157 6158 u8 outer_ip_dest_addr[0x20]; 6159 6160 u8 outer_l4_sport[0x10]; 6161 u8 outer_l4_dport[0x10]; 6162 6163 u8 reserved_at_160[0x1]; 6164 u8 sx_sniffer[0x1]; 6165 u8 functional_lb[0x1]; 6166 u8 outer_ip_frag[0x1]; 6167 u8 outer_qp_type[0x2]; 6168 u8 outer_encap_type[0x2]; 6169 u8 port_number[0x2]; 6170 u8 outer_l3_type[0x2]; 6171 u8 outer_l4_type[0x2]; 6172 u8 outer_first_vlan_type[0x2]; 6173 u8 outer_first_vlan_prio[0x3]; 6174 u8 outer_first_vlan_cfi[0x1]; 6175 u8 outer_first_vlan_vid[0xc]; 6176 6177 u8 metadata_reg_c_0[0x20]; 6178 6179 u8 outer_dmac_47_16[0x20]; 6180 6181 u8 outer_smac_47_16[0x20]; 6182 6183 u8 outer_smac_15_0[0x10]; 6184 u8 outer_dmac_15_0[0x10]; 6185 }; 6186 6187 struct mlx5_ifc_match_definer_format_23_bits { 6188 u8 reserved_at_0[0x100]; 6189 6190 u8 inner_ip_src_addr[0x20]; 6191 6192 u8 inner_ip_dest_addr[0x20]; 6193 6194 u8 inner_l4_sport[0x10]; 6195 u8 inner_l4_dport[0x10]; 6196 6197 u8 reserved_at_160[0x1]; 6198 u8 sx_sniffer[0x1]; 6199 u8 functional_lb[0x1]; 6200 u8 inner_ip_frag[0x1]; 6201 u8 inner_qp_type[0x2]; 6202 u8 inner_encap_type[0x2]; 6203 u8 port_number[0x2]; 6204 u8 inner_l3_type[0x2]; 6205 u8 inner_l4_type[0x2]; 6206 u8 inner_first_vlan_type[0x2]; 6207 u8 inner_first_vlan_prio[0x3]; 6208 u8 inner_first_vlan_cfi[0x1]; 6209 u8 inner_first_vlan_vid[0xc]; 6210 6211 u8 tunnel_header_0[0x20]; 6212 6213 u8 inner_dmac_47_16[0x20]; 6214 6215 u8 inner_smac_47_16[0x20]; 6216 6217 u8 inner_smac_15_0[0x10]; 6218 u8 inner_dmac_15_0[0x10]; 6219 }; 6220 6221 struct mlx5_ifc_match_definer_format_29_bits { 6222 u8 reserved_at_0[0xc0]; 6223 6224 u8 outer_ip_dest_addr[0x80]; 6225 6226 u8 outer_ip_src_addr[0x80]; 6227 6228 u8 outer_l4_sport[0x10]; 6229 u8 outer_l4_dport[0x10]; 6230 6231 u8 reserved_at_1e0[0x20]; 6232 }; 6233 6234 struct mlx5_ifc_match_definer_format_30_bits { 6235 u8 reserved_at_0[0xa0]; 6236 6237 u8 outer_ip_dest_addr[0x80]; 6238 6239 u8 outer_ip_src_addr[0x80]; 6240 6241 u8 outer_dmac_47_16[0x20]; 6242 6243 u8 outer_smac_47_16[0x20]; 6244 6245 u8 outer_smac_15_0[0x10]; 6246 u8 outer_dmac_15_0[0x10]; 6247 }; 6248 6249 struct mlx5_ifc_match_definer_format_31_bits { 6250 u8 reserved_at_0[0xc0]; 6251 6252 u8 inner_ip_dest_addr[0x80]; 6253 6254 u8 inner_ip_src_addr[0x80]; 6255 6256 u8 inner_l4_sport[0x10]; 6257 u8 inner_l4_dport[0x10]; 6258 6259 u8 reserved_at_1e0[0x20]; 6260 }; 6261 6262 struct mlx5_ifc_match_definer_format_32_bits { 6263 u8 reserved_at_0[0xa0]; 6264 6265 u8 inner_ip_dest_addr[0x80]; 6266 6267 u8 inner_ip_src_addr[0x80]; 6268 6269 u8 inner_dmac_47_16[0x20]; 6270 6271 u8 inner_smac_47_16[0x20]; 6272 6273 u8 inner_smac_15_0[0x10]; 6274 u8 inner_dmac_15_0[0x10]; 6275 }; 6276 6277 enum { 6278 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6279 }; 6280 6281 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6282 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6283 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6284 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6285 6286 struct mlx5_ifc_match_definer_match_mask_bits { 6287 u8 reserved_at_1c0[5][0x20]; 6288 u8 match_dw_8[0x20]; 6289 u8 match_dw_7[0x20]; 6290 u8 match_dw_6[0x20]; 6291 u8 match_dw_5[0x20]; 6292 u8 match_dw_4[0x20]; 6293 u8 match_dw_3[0x20]; 6294 u8 match_dw_2[0x20]; 6295 u8 match_dw_1[0x20]; 6296 u8 match_dw_0[0x20]; 6297 6298 u8 match_byte_7[0x8]; 6299 u8 match_byte_6[0x8]; 6300 u8 match_byte_5[0x8]; 6301 u8 match_byte_4[0x8]; 6302 6303 u8 match_byte_3[0x8]; 6304 u8 match_byte_2[0x8]; 6305 u8 match_byte_1[0x8]; 6306 u8 match_byte_0[0x8]; 6307 }; 6308 6309 struct mlx5_ifc_match_definer_bits { 6310 u8 modify_field_select[0x40]; 6311 6312 u8 reserved_at_40[0x40]; 6313 6314 u8 reserved_at_80[0x10]; 6315 u8 format_id[0x10]; 6316 6317 u8 reserved_at_a0[0x60]; 6318 6319 u8 format_select_dw3[0x8]; 6320 u8 format_select_dw2[0x8]; 6321 u8 format_select_dw1[0x8]; 6322 u8 format_select_dw0[0x8]; 6323 6324 u8 format_select_dw7[0x8]; 6325 u8 format_select_dw6[0x8]; 6326 u8 format_select_dw5[0x8]; 6327 u8 format_select_dw4[0x8]; 6328 6329 u8 reserved_at_100[0x18]; 6330 u8 format_select_dw8[0x8]; 6331 6332 u8 reserved_at_120[0x20]; 6333 6334 u8 format_select_byte3[0x8]; 6335 u8 format_select_byte2[0x8]; 6336 u8 format_select_byte1[0x8]; 6337 u8 format_select_byte0[0x8]; 6338 6339 u8 format_select_byte7[0x8]; 6340 u8 format_select_byte6[0x8]; 6341 u8 format_select_byte5[0x8]; 6342 u8 format_select_byte4[0x8]; 6343 6344 u8 reserved_at_180[0x40]; 6345 6346 union { 6347 struct { 6348 u8 match_mask[16][0x20]; 6349 }; 6350 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6351 }; 6352 }; 6353 6354 struct mlx5_ifc_general_obj_create_param_bits { 6355 u8 alias_object[0x1]; 6356 u8 reserved_at_1[0x2]; 6357 u8 log_obj_range[0x5]; 6358 u8 reserved_at_8[0x18]; 6359 }; 6360 6361 struct mlx5_ifc_general_obj_query_param_bits { 6362 u8 alias_object[0x1]; 6363 u8 obj_offset[0x1f]; 6364 }; 6365 6366 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6367 u8 opcode[0x10]; 6368 u8 uid[0x10]; 6369 6370 u8 vhca_tunnel_id[0x10]; 6371 u8 obj_type[0x10]; 6372 6373 u8 obj_id[0x20]; 6374 6375 union { 6376 struct mlx5_ifc_general_obj_create_param_bits create; 6377 struct mlx5_ifc_general_obj_query_param_bits query; 6378 } op_param; 6379 }; 6380 6381 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6382 u8 status[0x8]; 6383 u8 reserved_at_8[0x18]; 6384 6385 u8 syndrome[0x20]; 6386 6387 u8 obj_id[0x20]; 6388 6389 u8 reserved_at_60[0x20]; 6390 }; 6391 6392 struct mlx5_ifc_modify_header_arg_bits { 6393 u8 reserved_at_0[0x80]; 6394 6395 u8 reserved_at_80[0x8]; 6396 u8 access_pd[0x18]; 6397 }; 6398 6399 struct mlx5_ifc_create_modify_header_arg_in_bits { 6400 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6401 struct mlx5_ifc_modify_header_arg_bits arg; 6402 }; 6403 6404 struct mlx5_ifc_create_match_definer_in_bits { 6405 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6406 6407 struct mlx5_ifc_match_definer_bits obj_context; 6408 }; 6409 6410 struct mlx5_ifc_create_match_definer_out_bits { 6411 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6412 }; 6413 6414 enum { 6415 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6416 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6417 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6418 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6419 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6420 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6421 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6422 }; 6423 6424 struct mlx5_ifc_query_flow_group_out_bits { 6425 u8 status[0x8]; 6426 u8 reserved_at_8[0x18]; 6427 6428 u8 syndrome[0x20]; 6429 6430 u8 reserved_at_40[0xa0]; 6431 6432 u8 start_flow_index[0x20]; 6433 6434 u8 reserved_at_100[0x20]; 6435 6436 u8 end_flow_index[0x20]; 6437 6438 u8 reserved_at_140[0xa0]; 6439 6440 u8 reserved_at_1e0[0x18]; 6441 u8 match_criteria_enable[0x8]; 6442 6443 struct mlx5_ifc_fte_match_param_bits match_criteria; 6444 6445 u8 reserved_at_1200[0xe00]; 6446 }; 6447 6448 struct mlx5_ifc_query_flow_group_in_bits { 6449 u8 opcode[0x10]; 6450 u8 reserved_at_10[0x10]; 6451 6452 u8 reserved_at_20[0x10]; 6453 u8 op_mod[0x10]; 6454 6455 u8 reserved_at_40[0x40]; 6456 6457 u8 table_type[0x8]; 6458 u8 reserved_at_88[0x18]; 6459 6460 u8 reserved_at_a0[0x8]; 6461 u8 table_id[0x18]; 6462 6463 u8 group_id[0x20]; 6464 6465 u8 reserved_at_e0[0x120]; 6466 }; 6467 6468 struct mlx5_ifc_query_flow_counter_out_bits { 6469 u8 status[0x8]; 6470 u8 reserved_at_8[0x18]; 6471 6472 u8 syndrome[0x20]; 6473 6474 u8 reserved_at_40[0x40]; 6475 6476 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6477 }; 6478 6479 struct mlx5_ifc_query_flow_counter_in_bits { 6480 u8 opcode[0x10]; 6481 u8 reserved_at_10[0x10]; 6482 6483 u8 reserved_at_20[0x10]; 6484 u8 op_mod[0x10]; 6485 6486 u8 reserved_at_40[0x80]; 6487 6488 u8 clear[0x1]; 6489 u8 reserved_at_c1[0xf]; 6490 u8 num_of_counters[0x10]; 6491 6492 u8 flow_counter_id[0x20]; 6493 }; 6494 6495 struct mlx5_ifc_query_esw_vport_context_out_bits { 6496 u8 status[0x8]; 6497 u8 reserved_at_8[0x18]; 6498 6499 u8 syndrome[0x20]; 6500 6501 u8 reserved_at_40[0x40]; 6502 6503 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6504 }; 6505 6506 struct mlx5_ifc_query_esw_vport_context_in_bits { 6507 u8 opcode[0x10]; 6508 u8 reserved_at_10[0x10]; 6509 6510 u8 reserved_at_20[0x10]; 6511 u8 op_mod[0x10]; 6512 6513 u8 other_vport[0x1]; 6514 u8 reserved_at_41[0xf]; 6515 u8 vport_number[0x10]; 6516 6517 u8 reserved_at_60[0x20]; 6518 }; 6519 6520 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6521 u8 status[0x8]; 6522 u8 reserved_at_8[0x18]; 6523 6524 u8 syndrome[0x20]; 6525 6526 u8 reserved_at_40[0x40]; 6527 }; 6528 6529 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6530 u8 reserved_at_0[0x1b]; 6531 u8 fdb_to_vport_reg_c_id[0x1]; 6532 u8 vport_cvlan_insert[0x1]; 6533 u8 vport_svlan_insert[0x1]; 6534 u8 vport_cvlan_strip[0x1]; 6535 u8 vport_svlan_strip[0x1]; 6536 }; 6537 6538 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6539 u8 opcode[0x10]; 6540 u8 reserved_at_10[0x10]; 6541 6542 u8 reserved_at_20[0x10]; 6543 u8 op_mod[0x10]; 6544 6545 u8 other_vport[0x1]; 6546 u8 reserved_at_41[0xf]; 6547 u8 vport_number[0x10]; 6548 6549 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6550 6551 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6552 }; 6553 6554 struct mlx5_ifc_query_eq_out_bits { 6555 u8 status[0x8]; 6556 u8 reserved_at_8[0x18]; 6557 6558 u8 syndrome[0x20]; 6559 6560 u8 reserved_at_40[0x40]; 6561 6562 struct mlx5_ifc_eqc_bits eq_context_entry; 6563 6564 u8 reserved_at_280[0x40]; 6565 6566 u8 event_bitmask[0x40]; 6567 6568 u8 reserved_at_300[0x580]; 6569 6570 u8 pas[][0x40]; 6571 }; 6572 6573 struct mlx5_ifc_query_eq_in_bits { 6574 u8 opcode[0x10]; 6575 u8 reserved_at_10[0x10]; 6576 6577 u8 reserved_at_20[0x10]; 6578 u8 op_mod[0x10]; 6579 6580 u8 reserved_at_40[0x18]; 6581 u8 eq_number[0x8]; 6582 6583 u8 reserved_at_60[0x20]; 6584 }; 6585 6586 struct mlx5_ifc_packet_reformat_context_in_bits { 6587 u8 reformat_type[0x8]; 6588 u8 reserved_at_8[0x4]; 6589 u8 reformat_param_0[0x4]; 6590 u8 reserved_at_10[0x6]; 6591 u8 reformat_data_size[0xa]; 6592 6593 u8 reformat_param_1[0x8]; 6594 u8 reserved_at_28[0x8]; 6595 u8 reformat_data[2][0x8]; 6596 6597 u8 more_reformat_data[][0x8]; 6598 }; 6599 6600 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6601 u8 status[0x8]; 6602 u8 reserved_at_8[0x18]; 6603 6604 u8 syndrome[0x20]; 6605 6606 u8 reserved_at_40[0xa0]; 6607 6608 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6609 }; 6610 6611 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6612 u8 opcode[0x10]; 6613 u8 reserved_at_10[0x10]; 6614 6615 u8 reserved_at_20[0x10]; 6616 u8 op_mod[0x10]; 6617 6618 u8 packet_reformat_id[0x20]; 6619 6620 u8 reserved_at_60[0xa0]; 6621 }; 6622 6623 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6624 u8 status[0x8]; 6625 u8 reserved_at_8[0x18]; 6626 6627 u8 syndrome[0x20]; 6628 6629 u8 packet_reformat_id[0x20]; 6630 6631 u8 reserved_at_60[0x20]; 6632 }; 6633 6634 enum { 6635 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6636 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6637 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6638 }; 6639 6640 enum mlx5_reformat_ctx_type { 6641 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6642 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6643 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6644 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6645 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6646 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6647 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6648 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6649 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6650 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6651 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6652 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6653 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6654 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6655 }; 6656 6657 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6658 u8 opcode[0x10]; 6659 u8 reserved_at_10[0x10]; 6660 6661 u8 reserved_at_20[0x10]; 6662 u8 op_mod[0x10]; 6663 6664 u8 reserved_at_40[0xa0]; 6665 6666 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6667 }; 6668 6669 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6670 u8 status[0x8]; 6671 u8 reserved_at_8[0x18]; 6672 6673 u8 syndrome[0x20]; 6674 6675 u8 reserved_at_40[0x40]; 6676 }; 6677 6678 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6679 u8 opcode[0x10]; 6680 u8 reserved_at_10[0x10]; 6681 6682 u8 reserved_20[0x10]; 6683 u8 op_mod[0x10]; 6684 6685 u8 packet_reformat_id[0x20]; 6686 6687 u8 reserved_60[0x20]; 6688 }; 6689 6690 struct mlx5_ifc_set_action_in_bits { 6691 u8 action_type[0x4]; 6692 u8 field[0xc]; 6693 u8 reserved_at_10[0x3]; 6694 u8 offset[0x5]; 6695 u8 reserved_at_18[0x3]; 6696 u8 length[0x5]; 6697 6698 u8 data[0x20]; 6699 }; 6700 6701 struct mlx5_ifc_add_action_in_bits { 6702 u8 action_type[0x4]; 6703 u8 field[0xc]; 6704 u8 reserved_at_10[0x10]; 6705 6706 u8 data[0x20]; 6707 }; 6708 6709 struct mlx5_ifc_copy_action_in_bits { 6710 u8 action_type[0x4]; 6711 u8 src_field[0xc]; 6712 u8 reserved_at_10[0x3]; 6713 u8 src_offset[0x5]; 6714 u8 reserved_at_18[0x3]; 6715 u8 length[0x5]; 6716 6717 u8 reserved_at_20[0x4]; 6718 u8 dst_field[0xc]; 6719 u8 reserved_at_30[0x3]; 6720 u8 dst_offset[0x5]; 6721 u8 reserved_at_38[0x8]; 6722 }; 6723 6724 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6725 struct mlx5_ifc_set_action_in_bits set_action_in; 6726 struct mlx5_ifc_add_action_in_bits add_action_in; 6727 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6728 u8 reserved_at_0[0x40]; 6729 }; 6730 6731 enum { 6732 MLX5_ACTION_TYPE_SET = 0x1, 6733 MLX5_ACTION_TYPE_ADD = 0x2, 6734 MLX5_ACTION_TYPE_COPY = 0x3, 6735 }; 6736 6737 enum { 6738 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6739 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6740 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6741 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6742 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6743 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6744 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6745 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6746 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6747 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6748 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6749 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6750 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6751 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6752 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6753 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6754 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6755 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6756 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6757 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6758 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6759 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6760 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6761 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6762 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6763 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6764 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6765 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6766 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6767 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6768 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6769 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6770 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6771 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6772 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6773 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6774 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6775 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6776 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6777 }; 6778 6779 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6780 u8 status[0x8]; 6781 u8 reserved_at_8[0x18]; 6782 6783 u8 syndrome[0x20]; 6784 6785 u8 modify_header_id[0x20]; 6786 6787 u8 reserved_at_60[0x20]; 6788 }; 6789 6790 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6791 u8 opcode[0x10]; 6792 u8 reserved_at_10[0x10]; 6793 6794 u8 reserved_at_20[0x10]; 6795 u8 op_mod[0x10]; 6796 6797 u8 reserved_at_40[0x20]; 6798 6799 u8 table_type[0x8]; 6800 u8 reserved_at_68[0x10]; 6801 u8 num_of_actions[0x8]; 6802 6803 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6804 }; 6805 6806 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6807 u8 status[0x8]; 6808 u8 reserved_at_8[0x18]; 6809 6810 u8 syndrome[0x20]; 6811 6812 u8 reserved_at_40[0x40]; 6813 }; 6814 6815 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6816 u8 opcode[0x10]; 6817 u8 reserved_at_10[0x10]; 6818 6819 u8 reserved_at_20[0x10]; 6820 u8 op_mod[0x10]; 6821 6822 u8 modify_header_id[0x20]; 6823 6824 u8 reserved_at_60[0x20]; 6825 }; 6826 6827 struct mlx5_ifc_query_modify_header_context_in_bits { 6828 u8 opcode[0x10]; 6829 u8 uid[0x10]; 6830 6831 u8 reserved_at_20[0x10]; 6832 u8 op_mod[0x10]; 6833 6834 u8 modify_header_id[0x20]; 6835 6836 u8 reserved_at_60[0xa0]; 6837 }; 6838 6839 struct mlx5_ifc_query_dct_out_bits { 6840 u8 status[0x8]; 6841 u8 reserved_at_8[0x18]; 6842 6843 u8 syndrome[0x20]; 6844 6845 u8 reserved_at_40[0x40]; 6846 6847 struct mlx5_ifc_dctc_bits dct_context_entry; 6848 6849 u8 reserved_at_280[0x180]; 6850 }; 6851 6852 struct mlx5_ifc_query_dct_in_bits { 6853 u8 opcode[0x10]; 6854 u8 reserved_at_10[0x10]; 6855 6856 u8 reserved_at_20[0x10]; 6857 u8 op_mod[0x10]; 6858 6859 u8 reserved_at_40[0x8]; 6860 u8 dctn[0x18]; 6861 6862 u8 reserved_at_60[0x20]; 6863 }; 6864 6865 struct mlx5_ifc_query_cq_out_bits { 6866 u8 status[0x8]; 6867 u8 reserved_at_8[0x18]; 6868 6869 u8 syndrome[0x20]; 6870 6871 u8 reserved_at_40[0x40]; 6872 6873 struct mlx5_ifc_cqc_bits cq_context; 6874 6875 u8 reserved_at_280[0x600]; 6876 6877 u8 pas[][0x40]; 6878 }; 6879 6880 struct mlx5_ifc_query_cq_in_bits { 6881 u8 opcode[0x10]; 6882 u8 reserved_at_10[0x10]; 6883 6884 u8 reserved_at_20[0x10]; 6885 u8 op_mod[0x10]; 6886 6887 u8 reserved_at_40[0x8]; 6888 u8 cqn[0x18]; 6889 6890 u8 reserved_at_60[0x20]; 6891 }; 6892 6893 struct mlx5_ifc_query_cong_status_out_bits { 6894 u8 status[0x8]; 6895 u8 reserved_at_8[0x18]; 6896 6897 u8 syndrome[0x20]; 6898 6899 u8 reserved_at_40[0x20]; 6900 6901 u8 enable[0x1]; 6902 u8 tag_enable[0x1]; 6903 u8 reserved_at_62[0x1e]; 6904 }; 6905 6906 struct mlx5_ifc_query_cong_status_in_bits { 6907 u8 opcode[0x10]; 6908 u8 reserved_at_10[0x10]; 6909 6910 u8 reserved_at_20[0x10]; 6911 u8 op_mod[0x10]; 6912 6913 u8 reserved_at_40[0x18]; 6914 u8 priority[0x4]; 6915 u8 cong_protocol[0x4]; 6916 6917 u8 reserved_at_60[0x20]; 6918 }; 6919 6920 struct mlx5_ifc_query_cong_statistics_out_bits { 6921 u8 status[0x8]; 6922 u8 reserved_at_8[0x18]; 6923 6924 u8 syndrome[0x20]; 6925 6926 u8 reserved_at_40[0x40]; 6927 6928 u8 rp_cur_flows[0x20]; 6929 6930 u8 sum_flows[0x20]; 6931 6932 u8 rp_cnp_ignored_high[0x20]; 6933 6934 u8 rp_cnp_ignored_low[0x20]; 6935 6936 u8 rp_cnp_handled_high[0x20]; 6937 6938 u8 rp_cnp_handled_low[0x20]; 6939 6940 u8 reserved_at_140[0x100]; 6941 6942 u8 time_stamp_high[0x20]; 6943 6944 u8 time_stamp_low[0x20]; 6945 6946 u8 accumulators_period[0x20]; 6947 6948 u8 np_ecn_marked_roce_packets_high[0x20]; 6949 6950 u8 np_ecn_marked_roce_packets_low[0x20]; 6951 6952 u8 np_cnp_sent_high[0x20]; 6953 6954 u8 np_cnp_sent_low[0x20]; 6955 6956 u8 reserved_at_320[0x560]; 6957 }; 6958 6959 struct mlx5_ifc_query_cong_statistics_in_bits { 6960 u8 opcode[0x10]; 6961 u8 reserved_at_10[0x10]; 6962 6963 u8 reserved_at_20[0x10]; 6964 u8 op_mod[0x10]; 6965 6966 u8 clear[0x1]; 6967 u8 reserved_at_41[0x1f]; 6968 6969 u8 reserved_at_60[0x20]; 6970 }; 6971 6972 struct mlx5_ifc_query_cong_params_out_bits { 6973 u8 status[0x8]; 6974 u8 reserved_at_8[0x18]; 6975 6976 u8 syndrome[0x20]; 6977 6978 u8 reserved_at_40[0x40]; 6979 6980 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6981 }; 6982 6983 struct mlx5_ifc_query_cong_params_in_bits { 6984 u8 opcode[0x10]; 6985 u8 reserved_at_10[0x10]; 6986 6987 u8 reserved_at_20[0x10]; 6988 u8 op_mod[0x10]; 6989 6990 u8 reserved_at_40[0x1c]; 6991 u8 cong_protocol[0x4]; 6992 6993 u8 reserved_at_60[0x20]; 6994 }; 6995 6996 struct mlx5_ifc_query_adapter_out_bits { 6997 u8 status[0x8]; 6998 u8 reserved_at_8[0x18]; 6999 7000 u8 syndrome[0x20]; 7001 7002 u8 reserved_at_40[0x40]; 7003 7004 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7005 }; 7006 7007 struct mlx5_ifc_query_adapter_in_bits { 7008 u8 opcode[0x10]; 7009 u8 reserved_at_10[0x10]; 7010 7011 u8 reserved_at_20[0x10]; 7012 u8 op_mod[0x10]; 7013 7014 u8 reserved_at_40[0x40]; 7015 }; 7016 7017 struct mlx5_ifc_qp_2rst_out_bits { 7018 u8 status[0x8]; 7019 u8 reserved_at_8[0x18]; 7020 7021 u8 syndrome[0x20]; 7022 7023 u8 reserved_at_40[0x40]; 7024 }; 7025 7026 struct mlx5_ifc_qp_2rst_in_bits { 7027 u8 opcode[0x10]; 7028 u8 uid[0x10]; 7029 7030 u8 reserved_at_20[0x10]; 7031 u8 op_mod[0x10]; 7032 7033 u8 reserved_at_40[0x8]; 7034 u8 qpn[0x18]; 7035 7036 u8 reserved_at_60[0x20]; 7037 }; 7038 7039 struct mlx5_ifc_qp_2err_out_bits { 7040 u8 status[0x8]; 7041 u8 reserved_at_8[0x18]; 7042 7043 u8 syndrome[0x20]; 7044 7045 u8 reserved_at_40[0x40]; 7046 }; 7047 7048 struct mlx5_ifc_qp_2err_in_bits { 7049 u8 opcode[0x10]; 7050 u8 uid[0x10]; 7051 7052 u8 reserved_at_20[0x10]; 7053 u8 op_mod[0x10]; 7054 7055 u8 reserved_at_40[0x8]; 7056 u8 qpn[0x18]; 7057 7058 u8 reserved_at_60[0x20]; 7059 }; 7060 7061 struct mlx5_ifc_page_fault_resume_out_bits { 7062 u8 status[0x8]; 7063 u8 reserved_at_8[0x18]; 7064 7065 u8 syndrome[0x20]; 7066 7067 u8 reserved_at_40[0x40]; 7068 }; 7069 7070 struct mlx5_ifc_page_fault_resume_in_bits { 7071 u8 opcode[0x10]; 7072 u8 reserved_at_10[0x10]; 7073 7074 u8 reserved_at_20[0x10]; 7075 u8 op_mod[0x10]; 7076 7077 u8 error[0x1]; 7078 u8 reserved_at_41[0x4]; 7079 u8 page_fault_type[0x3]; 7080 u8 wq_number[0x18]; 7081 7082 u8 reserved_at_60[0x8]; 7083 u8 token[0x18]; 7084 }; 7085 7086 struct mlx5_ifc_nop_out_bits { 7087 u8 status[0x8]; 7088 u8 reserved_at_8[0x18]; 7089 7090 u8 syndrome[0x20]; 7091 7092 u8 reserved_at_40[0x40]; 7093 }; 7094 7095 struct mlx5_ifc_nop_in_bits { 7096 u8 opcode[0x10]; 7097 u8 reserved_at_10[0x10]; 7098 7099 u8 reserved_at_20[0x10]; 7100 u8 op_mod[0x10]; 7101 7102 u8 reserved_at_40[0x40]; 7103 }; 7104 7105 struct mlx5_ifc_modify_vport_state_out_bits { 7106 u8 status[0x8]; 7107 u8 reserved_at_8[0x18]; 7108 7109 u8 syndrome[0x20]; 7110 7111 u8 reserved_at_40[0x40]; 7112 }; 7113 7114 struct mlx5_ifc_modify_vport_state_in_bits { 7115 u8 opcode[0x10]; 7116 u8 reserved_at_10[0x10]; 7117 7118 u8 reserved_at_20[0x10]; 7119 u8 op_mod[0x10]; 7120 7121 u8 other_vport[0x1]; 7122 u8 reserved_at_41[0xf]; 7123 u8 vport_number[0x10]; 7124 7125 u8 reserved_at_60[0x18]; 7126 u8 admin_state[0x4]; 7127 u8 reserved_at_7c[0x4]; 7128 }; 7129 7130 struct mlx5_ifc_modify_tis_out_bits { 7131 u8 status[0x8]; 7132 u8 reserved_at_8[0x18]; 7133 7134 u8 syndrome[0x20]; 7135 7136 u8 reserved_at_40[0x40]; 7137 }; 7138 7139 struct mlx5_ifc_modify_tis_bitmask_bits { 7140 u8 reserved_at_0[0x20]; 7141 7142 u8 reserved_at_20[0x1d]; 7143 u8 lag_tx_port_affinity[0x1]; 7144 u8 strict_lag_tx_port_affinity[0x1]; 7145 u8 prio[0x1]; 7146 }; 7147 7148 struct mlx5_ifc_modify_tis_in_bits { 7149 u8 opcode[0x10]; 7150 u8 uid[0x10]; 7151 7152 u8 reserved_at_20[0x10]; 7153 u8 op_mod[0x10]; 7154 7155 u8 reserved_at_40[0x8]; 7156 u8 tisn[0x18]; 7157 7158 u8 reserved_at_60[0x20]; 7159 7160 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7161 7162 u8 reserved_at_c0[0x40]; 7163 7164 struct mlx5_ifc_tisc_bits ctx; 7165 }; 7166 7167 struct mlx5_ifc_modify_tir_bitmask_bits { 7168 u8 reserved_at_0[0x20]; 7169 7170 u8 reserved_at_20[0x1b]; 7171 u8 self_lb_en[0x1]; 7172 u8 reserved_at_3c[0x1]; 7173 u8 hash[0x1]; 7174 u8 reserved_at_3e[0x1]; 7175 u8 packet_merge[0x1]; 7176 }; 7177 7178 struct mlx5_ifc_modify_tir_out_bits { 7179 u8 status[0x8]; 7180 u8 reserved_at_8[0x18]; 7181 7182 u8 syndrome[0x20]; 7183 7184 u8 reserved_at_40[0x40]; 7185 }; 7186 7187 struct mlx5_ifc_modify_tir_in_bits { 7188 u8 opcode[0x10]; 7189 u8 uid[0x10]; 7190 7191 u8 reserved_at_20[0x10]; 7192 u8 op_mod[0x10]; 7193 7194 u8 reserved_at_40[0x8]; 7195 u8 tirn[0x18]; 7196 7197 u8 reserved_at_60[0x20]; 7198 7199 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7200 7201 u8 reserved_at_c0[0x40]; 7202 7203 struct mlx5_ifc_tirc_bits ctx; 7204 }; 7205 7206 struct mlx5_ifc_modify_sq_out_bits { 7207 u8 status[0x8]; 7208 u8 reserved_at_8[0x18]; 7209 7210 u8 syndrome[0x20]; 7211 7212 u8 reserved_at_40[0x40]; 7213 }; 7214 7215 struct mlx5_ifc_modify_sq_in_bits { 7216 u8 opcode[0x10]; 7217 u8 uid[0x10]; 7218 7219 u8 reserved_at_20[0x10]; 7220 u8 op_mod[0x10]; 7221 7222 u8 sq_state[0x4]; 7223 u8 reserved_at_44[0x4]; 7224 u8 sqn[0x18]; 7225 7226 u8 reserved_at_60[0x20]; 7227 7228 u8 modify_bitmask[0x40]; 7229 7230 u8 reserved_at_c0[0x40]; 7231 7232 struct mlx5_ifc_sqc_bits ctx; 7233 }; 7234 7235 struct mlx5_ifc_modify_scheduling_element_out_bits { 7236 u8 status[0x8]; 7237 u8 reserved_at_8[0x18]; 7238 7239 u8 syndrome[0x20]; 7240 7241 u8 reserved_at_40[0x1c0]; 7242 }; 7243 7244 enum { 7245 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7246 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7247 }; 7248 7249 struct mlx5_ifc_modify_scheduling_element_in_bits { 7250 u8 opcode[0x10]; 7251 u8 reserved_at_10[0x10]; 7252 7253 u8 reserved_at_20[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 scheduling_hierarchy[0x8]; 7257 u8 reserved_at_48[0x18]; 7258 7259 u8 scheduling_element_id[0x20]; 7260 7261 u8 reserved_at_80[0x20]; 7262 7263 u8 modify_bitmask[0x20]; 7264 7265 u8 reserved_at_c0[0x40]; 7266 7267 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7268 7269 u8 reserved_at_300[0x100]; 7270 }; 7271 7272 struct mlx5_ifc_modify_rqt_out_bits { 7273 u8 status[0x8]; 7274 u8 reserved_at_8[0x18]; 7275 7276 u8 syndrome[0x20]; 7277 7278 u8 reserved_at_40[0x40]; 7279 }; 7280 7281 struct mlx5_ifc_rqt_bitmask_bits { 7282 u8 reserved_at_0[0x20]; 7283 7284 u8 reserved_at_20[0x1f]; 7285 u8 rqn_list[0x1]; 7286 }; 7287 7288 struct mlx5_ifc_modify_rqt_in_bits { 7289 u8 opcode[0x10]; 7290 u8 uid[0x10]; 7291 7292 u8 reserved_at_20[0x10]; 7293 u8 op_mod[0x10]; 7294 7295 u8 reserved_at_40[0x8]; 7296 u8 rqtn[0x18]; 7297 7298 u8 reserved_at_60[0x20]; 7299 7300 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7301 7302 u8 reserved_at_c0[0x40]; 7303 7304 struct mlx5_ifc_rqtc_bits ctx; 7305 }; 7306 7307 struct mlx5_ifc_modify_rq_out_bits { 7308 u8 status[0x8]; 7309 u8 reserved_at_8[0x18]; 7310 7311 u8 syndrome[0x20]; 7312 7313 u8 reserved_at_40[0x40]; 7314 }; 7315 7316 enum { 7317 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7318 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7319 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7320 }; 7321 7322 struct mlx5_ifc_modify_rq_in_bits { 7323 u8 opcode[0x10]; 7324 u8 uid[0x10]; 7325 7326 u8 reserved_at_20[0x10]; 7327 u8 op_mod[0x10]; 7328 7329 u8 rq_state[0x4]; 7330 u8 reserved_at_44[0x4]; 7331 u8 rqn[0x18]; 7332 7333 u8 reserved_at_60[0x20]; 7334 7335 u8 modify_bitmask[0x40]; 7336 7337 u8 reserved_at_c0[0x40]; 7338 7339 struct mlx5_ifc_rqc_bits ctx; 7340 }; 7341 7342 struct mlx5_ifc_modify_rmp_out_bits { 7343 u8 status[0x8]; 7344 u8 reserved_at_8[0x18]; 7345 7346 u8 syndrome[0x20]; 7347 7348 u8 reserved_at_40[0x40]; 7349 }; 7350 7351 struct mlx5_ifc_rmp_bitmask_bits { 7352 u8 reserved_at_0[0x20]; 7353 7354 u8 reserved_at_20[0x1f]; 7355 u8 lwm[0x1]; 7356 }; 7357 7358 struct mlx5_ifc_modify_rmp_in_bits { 7359 u8 opcode[0x10]; 7360 u8 uid[0x10]; 7361 7362 u8 reserved_at_20[0x10]; 7363 u8 op_mod[0x10]; 7364 7365 u8 rmp_state[0x4]; 7366 u8 reserved_at_44[0x4]; 7367 u8 rmpn[0x18]; 7368 7369 u8 reserved_at_60[0x20]; 7370 7371 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7372 7373 u8 reserved_at_c0[0x40]; 7374 7375 struct mlx5_ifc_rmpc_bits ctx; 7376 }; 7377 7378 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7379 u8 status[0x8]; 7380 u8 reserved_at_8[0x18]; 7381 7382 u8 syndrome[0x20]; 7383 7384 u8 reserved_at_40[0x40]; 7385 }; 7386 7387 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7388 u8 reserved_at_0[0x12]; 7389 u8 affiliation[0x1]; 7390 u8 reserved_at_13[0x1]; 7391 u8 disable_uc_local_lb[0x1]; 7392 u8 disable_mc_local_lb[0x1]; 7393 u8 node_guid[0x1]; 7394 u8 port_guid[0x1]; 7395 u8 min_inline[0x1]; 7396 u8 mtu[0x1]; 7397 u8 change_event[0x1]; 7398 u8 promisc[0x1]; 7399 u8 permanent_address[0x1]; 7400 u8 addresses_list[0x1]; 7401 u8 roce_en[0x1]; 7402 u8 reserved_at_1f[0x1]; 7403 }; 7404 7405 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7406 u8 opcode[0x10]; 7407 u8 reserved_at_10[0x10]; 7408 7409 u8 reserved_at_20[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 other_vport[0x1]; 7413 u8 reserved_at_41[0xf]; 7414 u8 vport_number[0x10]; 7415 7416 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7417 7418 u8 reserved_at_80[0x780]; 7419 7420 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7421 }; 7422 7423 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7424 u8 status[0x8]; 7425 u8 reserved_at_8[0x18]; 7426 7427 u8 syndrome[0x20]; 7428 7429 u8 reserved_at_40[0x40]; 7430 }; 7431 7432 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7433 u8 opcode[0x10]; 7434 u8 reserved_at_10[0x10]; 7435 7436 u8 reserved_at_20[0x10]; 7437 u8 op_mod[0x10]; 7438 7439 u8 other_vport[0x1]; 7440 u8 reserved_at_41[0xb]; 7441 u8 port_num[0x4]; 7442 u8 vport_number[0x10]; 7443 7444 u8 reserved_at_60[0x20]; 7445 7446 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7447 }; 7448 7449 struct mlx5_ifc_modify_cq_out_bits { 7450 u8 status[0x8]; 7451 u8 reserved_at_8[0x18]; 7452 7453 u8 syndrome[0x20]; 7454 7455 u8 reserved_at_40[0x40]; 7456 }; 7457 7458 enum { 7459 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7460 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7461 }; 7462 7463 struct mlx5_ifc_modify_cq_in_bits { 7464 u8 opcode[0x10]; 7465 u8 uid[0x10]; 7466 7467 u8 reserved_at_20[0x10]; 7468 u8 op_mod[0x10]; 7469 7470 u8 reserved_at_40[0x8]; 7471 u8 cqn[0x18]; 7472 7473 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7474 7475 struct mlx5_ifc_cqc_bits cq_context; 7476 7477 u8 reserved_at_280[0x60]; 7478 7479 u8 cq_umem_valid[0x1]; 7480 u8 reserved_at_2e1[0x1f]; 7481 7482 u8 reserved_at_300[0x580]; 7483 7484 u8 pas[][0x40]; 7485 }; 7486 7487 struct mlx5_ifc_modify_cong_status_out_bits { 7488 u8 status[0x8]; 7489 u8 reserved_at_8[0x18]; 7490 7491 u8 syndrome[0x20]; 7492 7493 u8 reserved_at_40[0x40]; 7494 }; 7495 7496 struct mlx5_ifc_modify_cong_status_in_bits { 7497 u8 opcode[0x10]; 7498 u8 reserved_at_10[0x10]; 7499 7500 u8 reserved_at_20[0x10]; 7501 u8 op_mod[0x10]; 7502 7503 u8 reserved_at_40[0x18]; 7504 u8 priority[0x4]; 7505 u8 cong_protocol[0x4]; 7506 7507 u8 enable[0x1]; 7508 u8 tag_enable[0x1]; 7509 u8 reserved_at_62[0x1e]; 7510 }; 7511 7512 struct mlx5_ifc_modify_cong_params_out_bits { 7513 u8 status[0x8]; 7514 u8 reserved_at_8[0x18]; 7515 7516 u8 syndrome[0x20]; 7517 7518 u8 reserved_at_40[0x40]; 7519 }; 7520 7521 struct mlx5_ifc_modify_cong_params_in_bits { 7522 u8 opcode[0x10]; 7523 u8 reserved_at_10[0x10]; 7524 7525 u8 reserved_at_20[0x10]; 7526 u8 op_mod[0x10]; 7527 7528 u8 reserved_at_40[0x1c]; 7529 u8 cong_protocol[0x4]; 7530 7531 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7532 7533 u8 reserved_at_80[0x80]; 7534 7535 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7536 }; 7537 7538 struct mlx5_ifc_manage_pages_out_bits { 7539 u8 status[0x8]; 7540 u8 reserved_at_8[0x18]; 7541 7542 u8 syndrome[0x20]; 7543 7544 u8 output_num_entries[0x20]; 7545 7546 u8 reserved_at_60[0x20]; 7547 7548 u8 pas[][0x40]; 7549 }; 7550 7551 enum { 7552 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7553 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7554 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7555 }; 7556 7557 struct mlx5_ifc_manage_pages_in_bits { 7558 u8 opcode[0x10]; 7559 u8 reserved_at_10[0x10]; 7560 7561 u8 reserved_at_20[0x10]; 7562 u8 op_mod[0x10]; 7563 7564 u8 embedded_cpu_function[0x1]; 7565 u8 reserved_at_41[0xf]; 7566 u8 function_id[0x10]; 7567 7568 u8 input_num_entries[0x20]; 7569 7570 u8 pas[][0x40]; 7571 }; 7572 7573 struct mlx5_ifc_mad_ifc_out_bits { 7574 u8 status[0x8]; 7575 u8 reserved_at_8[0x18]; 7576 7577 u8 syndrome[0x20]; 7578 7579 u8 reserved_at_40[0x40]; 7580 7581 u8 response_mad_packet[256][0x8]; 7582 }; 7583 7584 struct mlx5_ifc_mad_ifc_in_bits { 7585 u8 opcode[0x10]; 7586 u8 reserved_at_10[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 remote_lid[0x10]; 7592 u8 reserved_at_50[0x8]; 7593 u8 port[0x8]; 7594 7595 u8 reserved_at_60[0x20]; 7596 7597 u8 mad[256][0x8]; 7598 }; 7599 7600 struct mlx5_ifc_init_hca_out_bits { 7601 u8 status[0x8]; 7602 u8 reserved_at_8[0x18]; 7603 7604 u8 syndrome[0x20]; 7605 7606 u8 reserved_at_40[0x40]; 7607 }; 7608 7609 struct mlx5_ifc_init_hca_in_bits { 7610 u8 opcode[0x10]; 7611 u8 reserved_at_10[0x10]; 7612 7613 u8 reserved_at_20[0x10]; 7614 u8 op_mod[0x10]; 7615 7616 u8 reserved_at_40[0x20]; 7617 7618 u8 reserved_at_60[0x2]; 7619 u8 sw_vhca_id[0xe]; 7620 u8 reserved_at_70[0x10]; 7621 7622 u8 sw_owner_id[4][0x20]; 7623 }; 7624 7625 struct mlx5_ifc_init2rtr_qp_out_bits { 7626 u8 status[0x8]; 7627 u8 reserved_at_8[0x18]; 7628 7629 u8 syndrome[0x20]; 7630 7631 u8 reserved_at_40[0x20]; 7632 u8 ece[0x20]; 7633 }; 7634 7635 struct mlx5_ifc_init2rtr_qp_in_bits { 7636 u8 opcode[0x10]; 7637 u8 uid[0x10]; 7638 7639 u8 reserved_at_20[0x10]; 7640 u8 op_mod[0x10]; 7641 7642 u8 reserved_at_40[0x8]; 7643 u8 qpn[0x18]; 7644 7645 u8 reserved_at_60[0x20]; 7646 7647 u8 opt_param_mask[0x20]; 7648 7649 u8 ece[0x20]; 7650 7651 struct mlx5_ifc_qpc_bits qpc; 7652 7653 u8 reserved_at_800[0x80]; 7654 }; 7655 7656 struct mlx5_ifc_init2init_qp_out_bits { 7657 u8 status[0x8]; 7658 u8 reserved_at_8[0x18]; 7659 7660 u8 syndrome[0x20]; 7661 7662 u8 reserved_at_40[0x20]; 7663 u8 ece[0x20]; 7664 }; 7665 7666 struct mlx5_ifc_init2init_qp_in_bits { 7667 u8 opcode[0x10]; 7668 u8 uid[0x10]; 7669 7670 u8 reserved_at_20[0x10]; 7671 u8 op_mod[0x10]; 7672 7673 u8 reserved_at_40[0x8]; 7674 u8 qpn[0x18]; 7675 7676 u8 reserved_at_60[0x20]; 7677 7678 u8 opt_param_mask[0x20]; 7679 7680 u8 ece[0x20]; 7681 7682 struct mlx5_ifc_qpc_bits qpc; 7683 7684 u8 reserved_at_800[0x80]; 7685 }; 7686 7687 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7688 u8 status[0x8]; 7689 u8 reserved_at_8[0x18]; 7690 7691 u8 syndrome[0x20]; 7692 7693 u8 reserved_at_40[0x40]; 7694 7695 u8 packet_headers_log[128][0x8]; 7696 7697 u8 packet_syndrome[64][0x8]; 7698 }; 7699 7700 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7701 u8 opcode[0x10]; 7702 u8 reserved_at_10[0x10]; 7703 7704 u8 reserved_at_20[0x10]; 7705 u8 op_mod[0x10]; 7706 7707 u8 reserved_at_40[0x40]; 7708 }; 7709 7710 struct mlx5_ifc_gen_eqe_in_bits { 7711 u8 opcode[0x10]; 7712 u8 reserved_at_10[0x10]; 7713 7714 u8 reserved_at_20[0x10]; 7715 u8 op_mod[0x10]; 7716 7717 u8 reserved_at_40[0x18]; 7718 u8 eq_number[0x8]; 7719 7720 u8 reserved_at_60[0x20]; 7721 7722 u8 eqe[64][0x8]; 7723 }; 7724 7725 struct mlx5_ifc_gen_eq_out_bits { 7726 u8 status[0x8]; 7727 u8 reserved_at_8[0x18]; 7728 7729 u8 syndrome[0x20]; 7730 7731 u8 reserved_at_40[0x40]; 7732 }; 7733 7734 struct mlx5_ifc_enable_hca_out_bits { 7735 u8 status[0x8]; 7736 u8 reserved_at_8[0x18]; 7737 7738 u8 syndrome[0x20]; 7739 7740 u8 reserved_at_40[0x20]; 7741 }; 7742 7743 struct mlx5_ifc_enable_hca_in_bits { 7744 u8 opcode[0x10]; 7745 u8 reserved_at_10[0x10]; 7746 7747 u8 reserved_at_20[0x10]; 7748 u8 op_mod[0x10]; 7749 7750 u8 embedded_cpu_function[0x1]; 7751 u8 reserved_at_41[0xf]; 7752 u8 function_id[0x10]; 7753 7754 u8 reserved_at_60[0x20]; 7755 }; 7756 7757 struct mlx5_ifc_drain_dct_out_bits { 7758 u8 status[0x8]; 7759 u8 reserved_at_8[0x18]; 7760 7761 u8 syndrome[0x20]; 7762 7763 u8 reserved_at_40[0x40]; 7764 }; 7765 7766 struct mlx5_ifc_drain_dct_in_bits { 7767 u8 opcode[0x10]; 7768 u8 uid[0x10]; 7769 7770 u8 reserved_at_20[0x10]; 7771 u8 op_mod[0x10]; 7772 7773 u8 reserved_at_40[0x8]; 7774 u8 dctn[0x18]; 7775 7776 u8 reserved_at_60[0x20]; 7777 }; 7778 7779 struct mlx5_ifc_disable_hca_out_bits { 7780 u8 status[0x8]; 7781 u8 reserved_at_8[0x18]; 7782 7783 u8 syndrome[0x20]; 7784 7785 u8 reserved_at_40[0x20]; 7786 }; 7787 7788 struct mlx5_ifc_disable_hca_in_bits { 7789 u8 opcode[0x10]; 7790 u8 reserved_at_10[0x10]; 7791 7792 u8 reserved_at_20[0x10]; 7793 u8 op_mod[0x10]; 7794 7795 u8 embedded_cpu_function[0x1]; 7796 u8 reserved_at_41[0xf]; 7797 u8 function_id[0x10]; 7798 7799 u8 reserved_at_60[0x20]; 7800 }; 7801 7802 struct mlx5_ifc_detach_from_mcg_out_bits { 7803 u8 status[0x8]; 7804 u8 reserved_at_8[0x18]; 7805 7806 u8 syndrome[0x20]; 7807 7808 u8 reserved_at_40[0x40]; 7809 }; 7810 7811 struct mlx5_ifc_detach_from_mcg_in_bits { 7812 u8 opcode[0x10]; 7813 u8 uid[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 reserved_at_40[0x8]; 7819 u8 qpn[0x18]; 7820 7821 u8 reserved_at_60[0x20]; 7822 7823 u8 multicast_gid[16][0x8]; 7824 }; 7825 7826 struct mlx5_ifc_destroy_xrq_out_bits { 7827 u8 status[0x8]; 7828 u8 reserved_at_8[0x18]; 7829 7830 u8 syndrome[0x20]; 7831 7832 u8 reserved_at_40[0x40]; 7833 }; 7834 7835 struct mlx5_ifc_destroy_xrq_in_bits { 7836 u8 opcode[0x10]; 7837 u8 uid[0x10]; 7838 7839 u8 reserved_at_20[0x10]; 7840 u8 op_mod[0x10]; 7841 7842 u8 reserved_at_40[0x8]; 7843 u8 xrqn[0x18]; 7844 7845 u8 reserved_at_60[0x20]; 7846 }; 7847 7848 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7849 u8 status[0x8]; 7850 u8 reserved_at_8[0x18]; 7851 7852 u8 syndrome[0x20]; 7853 7854 u8 reserved_at_40[0x40]; 7855 }; 7856 7857 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7858 u8 opcode[0x10]; 7859 u8 uid[0x10]; 7860 7861 u8 reserved_at_20[0x10]; 7862 u8 op_mod[0x10]; 7863 7864 u8 reserved_at_40[0x8]; 7865 u8 xrc_srqn[0x18]; 7866 7867 u8 reserved_at_60[0x20]; 7868 }; 7869 7870 struct mlx5_ifc_destroy_tis_out_bits { 7871 u8 status[0x8]; 7872 u8 reserved_at_8[0x18]; 7873 7874 u8 syndrome[0x20]; 7875 7876 u8 reserved_at_40[0x40]; 7877 }; 7878 7879 struct mlx5_ifc_destroy_tis_in_bits { 7880 u8 opcode[0x10]; 7881 u8 uid[0x10]; 7882 7883 u8 reserved_at_20[0x10]; 7884 u8 op_mod[0x10]; 7885 7886 u8 reserved_at_40[0x8]; 7887 u8 tisn[0x18]; 7888 7889 u8 reserved_at_60[0x20]; 7890 }; 7891 7892 struct mlx5_ifc_destroy_tir_out_bits { 7893 u8 status[0x8]; 7894 u8 reserved_at_8[0x18]; 7895 7896 u8 syndrome[0x20]; 7897 7898 u8 reserved_at_40[0x40]; 7899 }; 7900 7901 struct mlx5_ifc_destroy_tir_in_bits { 7902 u8 opcode[0x10]; 7903 u8 uid[0x10]; 7904 7905 u8 reserved_at_20[0x10]; 7906 u8 op_mod[0x10]; 7907 7908 u8 reserved_at_40[0x8]; 7909 u8 tirn[0x18]; 7910 7911 u8 reserved_at_60[0x20]; 7912 }; 7913 7914 struct mlx5_ifc_destroy_srq_out_bits { 7915 u8 status[0x8]; 7916 u8 reserved_at_8[0x18]; 7917 7918 u8 syndrome[0x20]; 7919 7920 u8 reserved_at_40[0x40]; 7921 }; 7922 7923 struct mlx5_ifc_destroy_srq_in_bits { 7924 u8 opcode[0x10]; 7925 u8 uid[0x10]; 7926 7927 u8 reserved_at_20[0x10]; 7928 u8 op_mod[0x10]; 7929 7930 u8 reserved_at_40[0x8]; 7931 u8 srqn[0x18]; 7932 7933 u8 reserved_at_60[0x20]; 7934 }; 7935 7936 struct mlx5_ifc_destroy_sq_out_bits { 7937 u8 status[0x8]; 7938 u8 reserved_at_8[0x18]; 7939 7940 u8 syndrome[0x20]; 7941 7942 u8 reserved_at_40[0x40]; 7943 }; 7944 7945 struct mlx5_ifc_destroy_sq_in_bits { 7946 u8 opcode[0x10]; 7947 u8 uid[0x10]; 7948 7949 u8 reserved_at_20[0x10]; 7950 u8 op_mod[0x10]; 7951 7952 u8 reserved_at_40[0x8]; 7953 u8 sqn[0x18]; 7954 7955 u8 reserved_at_60[0x20]; 7956 }; 7957 7958 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7959 u8 status[0x8]; 7960 u8 reserved_at_8[0x18]; 7961 7962 u8 syndrome[0x20]; 7963 7964 u8 reserved_at_40[0x1c0]; 7965 }; 7966 7967 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7968 u8 opcode[0x10]; 7969 u8 reserved_at_10[0x10]; 7970 7971 u8 reserved_at_20[0x10]; 7972 u8 op_mod[0x10]; 7973 7974 u8 scheduling_hierarchy[0x8]; 7975 u8 reserved_at_48[0x18]; 7976 7977 u8 scheduling_element_id[0x20]; 7978 7979 u8 reserved_at_80[0x180]; 7980 }; 7981 7982 struct mlx5_ifc_destroy_rqt_out_bits { 7983 u8 status[0x8]; 7984 u8 reserved_at_8[0x18]; 7985 7986 u8 syndrome[0x20]; 7987 7988 u8 reserved_at_40[0x40]; 7989 }; 7990 7991 struct mlx5_ifc_destroy_rqt_in_bits { 7992 u8 opcode[0x10]; 7993 u8 uid[0x10]; 7994 7995 u8 reserved_at_20[0x10]; 7996 u8 op_mod[0x10]; 7997 7998 u8 reserved_at_40[0x8]; 7999 u8 rqtn[0x18]; 8000 8001 u8 reserved_at_60[0x20]; 8002 }; 8003 8004 struct mlx5_ifc_destroy_rq_out_bits { 8005 u8 status[0x8]; 8006 u8 reserved_at_8[0x18]; 8007 8008 u8 syndrome[0x20]; 8009 8010 u8 reserved_at_40[0x40]; 8011 }; 8012 8013 struct mlx5_ifc_destroy_rq_in_bits { 8014 u8 opcode[0x10]; 8015 u8 uid[0x10]; 8016 8017 u8 reserved_at_20[0x10]; 8018 u8 op_mod[0x10]; 8019 8020 u8 reserved_at_40[0x8]; 8021 u8 rqn[0x18]; 8022 8023 u8 reserved_at_60[0x20]; 8024 }; 8025 8026 struct mlx5_ifc_set_delay_drop_params_in_bits { 8027 u8 opcode[0x10]; 8028 u8 reserved_at_10[0x10]; 8029 8030 u8 reserved_at_20[0x10]; 8031 u8 op_mod[0x10]; 8032 8033 u8 reserved_at_40[0x20]; 8034 8035 u8 reserved_at_60[0x10]; 8036 u8 delay_drop_timeout[0x10]; 8037 }; 8038 8039 struct mlx5_ifc_set_delay_drop_params_out_bits { 8040 u8 status[0x8]; 8041 u8 reserved_at_8[0x18]; 8042 8043 u8 syndrome[0x20]; 8044 8045 u8 reserved_at_40[0x40]; 8046 }; 8047 8048 struct mlx5_ifc_destroy_rmp_out_bits { 8049 u8 status[0x8]; 8050 u8 reserved_at_8[0x18]; 8051 8052 u8 syndrome[0x20]; 8053 8054 u8 reserved_at_40[0x40]; 8055 }; 8056 8057 struct mlx5_ifc_destroy_rmp_in_bits { 8058 u8 opcode[0x10]; 8059 u8 uid[0x10]; 8060 8061 u8 reserved_at_20[0x10]; 8062 u8 op_mod[0x10]; 8063 8064 u8 reserved_at_40[0x8]; 8065 u8 rmpn[0x18]; 8066 8067 u8 reserved_at_60[0x20]; 8068 }; 8069 8070 struct mlx5_ifc_destroy_qp_out_bits { 8071 u8 status[0x8]; 8072 u8 reserved_at_8[0x18]; 8073 8074 u8 syndrome[0x20]; 8075 8076 u8 reserved_at_40[0x40]; 8077 }; 8078 8079 struct mlx5_ifc_destroy_qp_in_bits { 8080 u8 opcode[0x10]; 8081 u8 uid[0x10]; 8082 8083 u8 reserved_at_20[0x10]; 8084 u8 op_mod[0x10]; 8085 8086 u8 reserved_at_40[0x8]; 8087 u8 qpn[0x18]; 8088 8089 u8 reserved_at_60[0x20]; 8090 }; 8091 8092 struct mlx5_ifc_destroy_psv_out_bits { 8093 u8 status[0x8]; 8094 u8 reserved_at_8[0x18]; 8095 8096 u8 syndrome[0x20]; 8097 8098 u8 reserved_at_40[0x40]; 8099 }; 8100 8101 struct mlx5_ifc_destroy_psv_in_bits { 8102 u8 opcode[0x10]; 8103 u8 reserved_at_10[0x10]; 8104 8105 u8 reserved_at_20[0x10]; 8106 u8 op_mod[0x10]; 8107 8108 u8 reserved_at_40[0x8]; 8109 u8 psvn[0x18]; 8110 8111 u8 reserved_at_60[0x20]; 8112 }; 8113 8114 struct mlx5_ifc_destroy_mkey_out_bits { 8115 u8 status[0x8]; 8116 u8 reserved_at_8[0x18]; 8117 8118 u8 syndrome[0x20]; 8119 8120 u8 reserved_at_40[0x40]; 8121 }; 8122 8123 struct mlx5_ifc_destroy_mkey_in_bits { 8124 u8 opcode[0x10]; 8125 u8 uid[0x10]; 8126 8127 u8 reserved_at_20[0x10]; 8128 u8 op_mod[0x10]; 8129 8130 u8 reserved_at_40[0x8]; 8131 u8 mkey_index[0x18]; 8132 8133 u8 reserved_at_60[0x20]; 8134 }; 8135 8136 struct mlx5_ifc_destroy_flow_table_out_bits { 8137 u8 status[0x8]; 8138 u8 reserved_at_8[0x18]; 8139 8140 u8 syndrome[0x20]; 8141 8142 u8 reserved_at_40[0x40]; 8143 }; 8144 8145 struct mlx5_ifc_destroy_flow_table_in_bits { 8146 u8 opcode[0x10]; 8147 u8 reserved_at_10[0x10]; 8148 8149 u8 reserved_at_20[0x10]; 8150 u8 op_mod[0x10]; 8151 8152 u8 other_vport[0x1]; 8153 u8 reserved_at_41[0xf]; 8154 u8 vport_number[0x10]; 8155 8156 u8 reserved_at_60[0x20]; 8157 8158 u8 table_type[0x8]; 8159 u8 reserved_at_88[0x18]; 8160 8161 u8 reserved_at_a0[0x8]; 8162 u8 table_id[0x18]; 8163 8164 u8 reserved_at_c0[0x140]; 8165 }; 8166 8167 struct mlx5_ifc_destroy_flow_group_out_bits { 8168 u8 status[0x8]; 8169 u8 reserved_at_8[0x18]; 8170 8171 u8 syndrome[0x20]; 8172 8173 u8 reserved_at_40[0x40]; 8174 }; 8175 8176 struct mlx5_ifc_destroy_flow_group_in_bits { 8177 u8 opcode[0x10]; 8178 u8 reserved_at_10[0x10]; 8179 8180 u8 reserved_at_20[0x10]; 8181 u8 op_mod[0x10]; 8182 8183 u8 other_vport[0x1]; 8184 u8 reserved_at_41[0xf]; 8185 u8 vport_number[0x10]; 8186 8187 u8 reserved_at_60[0x20]; 8188 8189 u8 table_type[0x8]; 8190 u8 reserved_at_88[0x18]; 8191 8192 u8 reserved_at_a0[0x8]; 8193 u8 table_id[0x18]; 8194 8195 u8 group_id[0x20]; 8196 8197 u8 reserved_at_e0[0x120]; 8198 }; 8199 8200 struct mlx5_ifc_destroy_eq_out_bits { 8201 u8 status[0x8]; 8202 u8 reserved_at_8[0x18]; 8203 8204 u8 syndrome[0x20]; 8205 8206 u8 reserved_at_40[0x40]; 8207 }; 8208 8209 struct mlx5_ifc_destroy_eq_in_bits { 8210 u8 opcode[0x10]; 8211 u8 reserved_at_10[0x10]; 8212 8213 u8 reserved_at_20[0x10]; 8214 u8 op_mod[0x10]; 8215 8216 u8 reserved_at_40[0x18]; 8217 u8 eq_number[0x8]; 8218 8219 u8 reserved_at_60[0x20]; 8220 }; 8221 8222 struct mlx5_ifc_destroy_dct_out_bits { 8223 u8 status[0x8]; 8224 u8 reserved_at_8[0x18]; 8225 8226 u8 syndrome[0x20]; 8227 8228 u8 reserved_at_40[0x40]; 8229 }; 8230 8231 struct mlx5_ifc_destroy_dct_in_bits { 8232 u8 opcode[0x10]; 8233 u8 uid[0x10]; 8234 8235 u8 reserved_at_20[0x10]; 8236 u8 op_mod[0x10]; 8237 8238 u8 reserved_at_40[0x8]; 8239 u8 dctn[0x18]; 8240 8241 u8 reserved_at_60[0x20]; 8242 }; 8243 8244 struct mlx5_ifc_destroy_cq_out_bits { 8245 u8 status[0x8]; 8246 u8 reserved_at_8[0x18]; 8247 8248 u8 syndrome[0x20]; 8249 8250 u8 reserved_at_40[0x40]; 8251 }; 8252 8253 struct mlx5_ifc_destroy_cq_in_bits { 8254 u8 opcode[0x10]; 8255 u8 uid[0x10]; 8256 8257 u8 reserved_at_20[0x10]; 8258 u8 op_mod[0x10]; 8259 8260 u8 reserved_at_40[0x8]; 8261 u8 cqn[0x18]; 8262 8263 u8 reserved_at_60[0x20]; 8264 }; 8265 8266 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8267 u8 status[0x8]; 8268 u8 reserved_at_8[0x18]; 8269 8270 u8 syndrome[0x20]; 8271 8272 u8 reserved_at_40[0x40]; 8273 }; 8274 8275 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8276 u8 opcode[0x10]; 8277 u8 reserved_at_10[0x10]; 8278 8279 u8 reserved_at_20[0x10]; 8280 u8 op_mod[0x10]; 8281 8282 u8 reserved_at_40[0x20]; 8283 8284 u8 reserved_at_60[0x10]; 8285 u8 vxlan_udp_port[0x10]; 8286 }; 8287 8288 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8289 u8 status[0x8]; 8290 u8 reserved_at_8[0x18]; 8291 8292 u8 syndrome[0x20]; 8293 8294 u8 reserved_at_40[0x40]; 8295 }; 8296 8297 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8298 u8 opcode[0x10]; 8299 u8 reserved_at_10[0x10]; 8300 8301 u8 reserved_at_20[0x10]; 8302 u8 op_mod[0x10]; 8303 8304 u8 reserved_at_40[0x60]; 8305 8306 u8 reserved_at_a0[0x8]; 8307 u8 table_index[0x18]; 8308 8309 u8 reserved_at_c0[0x140]; 8310 }; 8311 8312 struct mlx5_ifc_delete_fte_out_bits { 8313 u8 status[0x8]; 8314 u8 reserved_at_8[0x18]; 8315 8316 u8 syndrome[0x20]; 8317 8318 u8 reserved_at_40[0x40]; 8319 }; 8320 8321 struct mlx5_ifc_delete_fte_in_bits { 8322 u8 opcode[0x10]; 8323 u8 reserved_at_10[0x10]; 8324 8325 u8 reserved_at_20[0x10]; 8326 u8 op_mod[0x10]; 8327 8328 u8 other_vport[0x1]; 8329 u8 reserved_at_41[0xf]; 8330 u8 vport_number[0x10]; 8331 8332 u8 reserved_at_60[0x20]; 8333 8334 u8 table_type[0x8]; 8335 u8 reserved_at_88[0x18]; 8336 8337 u8 reserved_at_a0[0x8]; 8338 u8 table_id[0x18]; 8339 8340 u8 reserved_at_c0[0x40]; 8341 8342 u8 flow_index[0x20]; 8343 8344 u8 reserved_at_120[0xe0]; 8345 }; 8346 8347 struct mlx5_ifc_dealloc_xrcd_out_bits { 8348 u8 status[0x8]; 8349 u8 reserved_at_8[0x18]; 8350 8351 u8 syndrome[0x20]; 8352 8353 u8 reserved_at_40[0x40]; 8354 }; 8355 8356 struct mlx5_ifc_dealloc_xrcd_in_bits { 8357 u8 opcode[0x10]; 8358 u8 uid[0x10]; 8359 8360 u8 reserved_at_20[0x10]; 8361 u8 op_mod[0x10]; 8362 8363 u8 reserved_at_40[0x8]; 8364 u8 xrcd[0x18]; 8365 8366 u8 reserved_at_60[0x20]; 8367 }; 8368 8369 struct mlx5_ifc_dealloc_uar_out_bits { 8370 u8 status[0x8]; 8371 u8 reserved_at_8[0x18]; 8372 8373 u8 syndrome[0x20]; 8374 8375 u8 reserved_at_40[0x40]; 8376 }; 8377 8378 struct mlx5_ifc_dealloc_uar_in_bits { 8379 u8 opcode[0x10]; 8380 u8 uid[0x10]; 8381 8382 u8 reserved_at_20[0x10]; 8383 u8 op_mod[0x10]; 8384 8385 u8 reserved_at_40[0x8]; 8386 u8 uar[0x18]; 8387 8388 u8 reserved_at_60[0x20]; 8389 }; 8390 8391 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8392 u8 status[0x8]; 8393 u8 reserved_at_8[0x18]; 8394 8395 u8 syndrome[0x20]; 8396 8397 u8 reserved_at_40[0x40]; 8398 }; 8399 8400 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8401 u8 opcode[0x10]; 8402 u8 uid[0x10]; 8403 8404 u8 reserved_at_20[0x10]; 8405 u8 op_mod[0x10]; 8406 8407 u8 reserved_at_40[0x8]; 8408 u8 transport_domain[0x18]; 8409 8410 u8 reserved_at_60[0x20]; 8411 }; 8412 8413 struct mlx5_ifc_dealloc_q_counter_out_bits { 8414 u8 status[0x8]; 8415 u8 reserved_at_8[0x18]; 8416 8417 u8 syndrome[0x20]; 8418 8419 u8 reserved_at_40[0x40]; 8420 }; 8421 8422 struct mlx5_ifc_dealloc_q_counter_in_bits { 8423 u8 opcode[0x10]; 8424 u8 reserved_at_10[0x10]; 8425 8426 u8 reserved_at_20[0x10]; 8427 u8 op_mod[0x10]; 8428 8429 u8 reserved_at_40[0x18]; 8430 u8 counter_set_id[0x8]; 8431 8432 u8 reserved_at_60[0x20]; 8433 }; 8434 8435 struct mlx5_ifc_dealloc_pd_out_bits { 8436 u8 status[0x8]; 8437 u8 reserved_at_8[0x18]; 8438 8439 u8 syndrome[0x20]; 8440 8441 u8 reserved_at_40[0x40]; 8442 }; 8443 8444 struct mlx5_ifc_dealloc_pd_in_bits { 8445 u8 opcode[0x10]; 8446 u8 uid[0x10]; 8447 8448 u8 reserved_at_20[0x10]; 8449 u8 op_mod[0x10]; 8450 8451 u8 reserved_at_40[0x8]; 8452 u8 pd[0x18]; 8453 8454 u8 reserved_at_60[0x20]; 8455 }; 8456 8457 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8458 u8 status[0x8]; 8459 u8 reserved_at_8[0x18]; 8460 8461 u8 syndrome[0x20]; 8462 8463 u8 reserved_at_40[0x40]; 8464 }; 8465 8466 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8467 u8 opcode[0x10]; 8468 u8 reserved_at_10[0x10]; 8469 8470 u8 reserved_at_20[0x10]; 8471 u8 op_mod[0x10]; 8472 8473 u8 flow_counter_id[0x20]; 8474 8475 u8 reserved_at_60[0x20]; 8476 }; 8477 8478 struct mlx5_ifc_create_xrq_out_bits { 8479 u8 status[0x8]; 8480 u8 reserved_at_8[0x18]; 8481 8482 u8 syndrome[0x20]; 8483 8484 u8 reserved_at_40[0x8]; 8485 u8 xrqn[0x18]; 8486 8487 u8 reserved_at_60[0x20]; 8488 }; 8489 8490 struct mlx5_ifc_create_xrq_in_bits { 8491 u8 opcode[0x10]; 8492 u8 uid[0x10]; 8493 8494 u8 reserved_at_20[0x10]; 8495 u8 op_mod[0x10]; 8496 8497 u8 reserved_at_40[0x40]; 8498 8499 struct mlx5_ifc_xrqc_bits xrq_context; 8500 }; 8501 8502 struct mlx5_ifc_create_xrc_srq_out_bits { 8503 u8 status[0x8]; 8504 u8 reserved_at_8[0x18]; 8505 8506 u8 syndrome[0x20]; 8507 8508 u8 reserved_at_40[0x8]; 8509 u8 xrc_srqn[0x18]; 8510 8511 u8 reserved_at_60[0x20]; 8512 }; 8513 8514 struct mlx5_ifc_create_xrc_srq_in_bits { 8515 u8 opcode[0x10]; 8516 u8 uid[0x10]; 8517 8518 u8 reserved_at_20[0x10]; 8519 u8 op_mod[0x10]; 8520 8521 u8 reserved_at_40[0x40]; 8522 8523 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8524 8525 u8 reserved_at_280[0x60]; 8526 8527 u8 xrc_srq_umem_valid[0x1]; 8528 u8 reserved_at_2e1[0x1f]; 8529 8530 u8 reserved_at_300[0x580]; 8531 8532 u8 pas[][0x40]; 8533 }; 8534 8535 struct mlx5_ifc_create_tis_out_bits { 8536 u8 status[0x8]; 8537 u8 reserved_at_8[0x18]; 8538 8539 u8 syndrome[0x20]; 8540 8541 u8 reserved_at_40[0x8]; 8542 u8 tisn[0x18]; 8543 8544 u8 reserved_at_60[0x20]; 8545 }; 8546 8547 struct mlx5_ifc_create_tis_in_bits { 8548 u8 opcode[0x10]; 8549 u8 uid[0x10]; 8550 8551 u8 reserved_at_20[0x10]; 8552 u8 op_mod[0x10]; 8553 8554 u8 reserved_at_40[0xc0]; 8555 8556 struct mlx5_ifc_tisc_bits ctx; 8557 }; 8558 8559 struct mlx5_ifc_create_tir_out_bits { 8560 u8 status[0x8]; 8561 u8 icm_address_63_40[0x18]; 8562 8563 u8 syndrome[0x20]; 8564 8565 u8 icm_address_39_32[0x8]; 8566 u8 tirn[0x18]; 8567 8568 u8 icm_address_31_0[0x20]; 8569 }; 8570 8571 struct mlx5_ifc_create_tir_in_bits { 8572 u8 opcode[0x10]; 8573 u8 uid[0x10]; 8574 8575 u8 reserved_at_20[0x10]; 8576 u8 op_mod[0x10]; 8577 8578 u8 reserved_at_40[0xc0]; 8579 8580 struct mlx5_ifc_tirc_bits ctx; 8581 }; 8582 8583 struct mlx5_ifc_create_srq_out_bits { 8584 u8 status[0x8]; 8585 u8 reserved_at_8[0x18]; 8586 8587 u8 syndrome[0x20]; 8588 8589 u8 reserved_at_40[0x8]; 8590 u8 srqn[0x18]; 8591 8592 u8 reserved_at_60[0x20]; 8593 }; 8594 8595 struct mlx5_ifc_create_srq_in_bits { 8596 u8 opcode[0x10]; 8597 u8 uid[0x10]; 8598 8599 u8 reserved_at_20[0x10]; 8600 u8 op_mod[0x10]; 8601 8602 u8 reserved_at_40[0x40]; 8603 8604 struct mlx5_ifc_srqc_bits srq_context_entry; 8605 8606 u8 reserved_at_280[0x600]; 8607 8608 u8 pas[][0x40]; 8609 }; 8610 8611 struct mlx5_ifc_create_sq_out_bits { 8612 u8 status[0x8]; 8613 u8 reserved_at_8[0x18]; 8614 8615 u8 syndrome[0x20]; 8616 8617 u8 reserved_at_40[0x8]; 8618 u8 sqn[0x18]; 8619 8620 u8 reserved_at_60[0x20]; 8621 }; 8622 8623 struct mlx5_ifc_create_sq_in_bits { 8624 u8 opcode[0x10]; 8625 u8 uid[0x10]; 8626 8627 u8 reserved_at_20[0x10]; 8628 u8 op_mod[0x10]; 8629 8630 u8 reserved_at_40[0xc0]; 8631 8632 struct mlx5_ifc_sqc_bits ctx; 8633 }; 8634 8635 struct mlx5_ifc_create_scheduling_element_out_bits { 8636 u8 status[0x8]; 8637 u8 reserved_at_8[0x18]; 8638 8639 u8 syndrome[0x20]; 8640 8641 u8 reserved_at_40[0x40]; 8642 8643 u8 scheduling_element_id[0x20]; 8644 8645 u8 reserved_at_a0[0x160]; 8646 }; 8647 8648 struct mlx5_ifc_create_scheduling_element_in_bits { 8649 u8 opcode[0x10]; 8650 u8 reserved_at_10[0x10]; 8651 8652 u8 reserved_at_20[0x10]; 8653 u8 op_mod[0x10]; 8654 8655 u8 scheduling_hierarchy[0x8]; 8656 u8 reserved_at_48[0x18]; 8657 8658 u8 reserved_at_60[0xa0]; 8659 8660 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8661 8662 u8 reserved_at_300[0x100]; 8663 }; 8664 8665 struct mlx5_ifc_create_rqt_out_bits { 8666 u8 status[0x8]; 8667 u8 reserved_at_8[0x18]; 8668 8669 u8 syndrome[0x20]; 8670 8671 u8 reserved_at_40[0x8]; 8672 u8 rqtn[0x18]; 8673 8674 u8 reserved_at_60[0x20]; 8675 }; 8676 8677 struct mlx5_ifc_create_rqt_in_bits { 8678 u8 opcode[0x10]; 8679 u8 uid[0x10]; 8680 8681 u8 reserved_at_20[0x10]; 8682 u8 op_mod[0x10]; 8683 8684 u8 reserved_at_40[0xc0]; 8685 8686 struct mlx5_ifc_rqtc_bits rqt_context; 8687 }; 8688 8689 struct mlx5_ifc_create_rq_out_bits { 8690 u8 status[0x8]; 8691 u8 reserved_at_8[0x18]; 8692 8693 u8 syndrome[0x20]; 8694 8695 u8 reserved_at_40[0x8]; 8696 u8 rqn[0x18]; 8697 8698 u8 reserved_at_60[0x20]; 8699 }; 8700 8701 struct mlx5_ifc_create_rq_in_bits { 8702 u8 opcode[0x10]; 8703 u8 uid[0x10]; 8704 8705 u8 reserved_at_20[0x10]; 8706 u8 op_mod[0x10]; 8707 8708 u8 reserved_at_40[0xc0]; 8709 8710 struct mlx5_ifc_rqc_bits ctx; 8711 }; 8712 8713 struct mlx5_ifc_create_rmp_out_bits { 8714 u8 status[0x8]; 8715 u8 reserved_at_8[0x18]; 8716 8717 u8 syndrome[0x20]; 8718 8719 u8 reserved_at_40[0x8]; 8720 u8 rmpn[0x18]; 8721 8722 u8 reserved_at_60[0x20]; 8723 }; 8724 8725 struct mlx5_ifc_create_rmp_in_bits { 8726 u8 opcode[0x10]; 8727 u8 uid[0x10]; 8728 8729 u8 reserved_at_20[0x10]; 8730 u8 op_mod[0x10]; 8731 8732 u8 reserved_at_40[0xc0]; 8733 8734 struct mlx5_ifc_rmpc_bits ctx; 8735 }; 8736 8737 struct mlx5_ifc_create_qp_out_bits { 8738 u8 status[0x8]; 8739 u8 reserved_at_8[0x18]; 8740 8741 u8 syndrome[0x20]; 8742 8743 u8 reserved_at_40[0x8]; 8744 u8 qpn[0x18]; 8745 8746 u8 ece[0x20]; 8747 }; 8748 8749 struct mlx5_ifc_create_qp_in_bits { 8750 u8 opcode[0x10]; 8751 u8 uid[0x10]; 8752 8753 u8 reserved_at_20[0x10]; 8754 u8 op_mod[0x10]; 8755 8756 u8 qpc_ext[0x1]; 8757 u8 reserved_at_41[0x7]; 8758 u8 input_qpn[0x18]; 8759 8760 u8 reserved_at_60[0x20]; 8761 u8 opt_param_mask[0x20]; 8762 8763 u8 ece[0x20]; 8764 8765 struct mlx5_ifc_qpc_bits qpc; 8766 8767 u8 reserved_at_800[0x60]; 8768 8769 u8 wq_umem_valid[0x1]; 8770 u8 reserved_at_861[0x1f]; 8771 8772 u8 pas[][0x40]; 8773 }; 8774 8775 struct mlx5_ifc_create_psv_out_bits { 8776 u8 status[0x8]; 8777 u8 reserved_at_8[0x18]; 8778 8779 u8 syndrome[0x20]; 8780 8781 u8 reserved_at_40[0x40]; 8782 8783 u8 reserved_at_80[0x8]; 8784 u8 psv0_index[0x18]; 8785 8786 u8 reserved_at_a0[0x8]; 8787 u8 psv1_index[0x18]; 8788 8789 u8 reserved_at_c0[0x8]; 8790 u8 psv2_index[0x18]; 8791 8792 u8 reserved_at_e0[0x8]; 8793 u8 psv3_index[0x18]; 8794 }; 8795 8796 struct mlx5_ifc_create_psv_in_bits { 8797 u8 opcode[0x10]; 8798 u8 reserved_at_10[0x10]; 8799 8800 u8 reserved_at_20[0x10]; 8801 u8 op_mod[0x10]; 8802 8803 u8 num_psv[0x4]; 8804 u8 reserved_at_44[0x4]; 8805 u8 pd[0x18]; 8806 8807 u8 reserved_at_60[0x20]; 8808 }; 8809 8810 struct mlx5_ifc_create_mkey_out_bits { 8811 u8 status[0x8]; 8812 u8 reserved_at_8[0x18]; 8813 8814 u8 syndrome[0x20]; 8815 8816 u8 reserved_at_40[0x8]; 8817 u8 mkey_index[0x18]; 8818 8819 u8 reserved_at_60[0x20]; 8820 }; 8821 8822 struct mlx5_ifc_create_mkey_in_bits { 8823 u8 opcode[0x10]; 8824 u8 uid[0x10]; 8825 8826 u8 reserved_at_20[0x10]; 8827 u8 op_mod[0x10]; 8828 8829 u8 reserved_at_40[0x20]; 8830 8831 u8 pg_access[0x1]; 8832 u8 mkey_umem_valid[0x1]; 8833 u8 reserved_at_62[0x1e]; 8834 8835 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8836 8837 u8 reserved_at_280[0x80]; 8838 8839 u8 translations_octword_actual_size[0x20]; 8840 8841 u8 reserved_at_320[0x560]; 8842 8843 u8 klm_pas_mtt[][0x20]; 8844 }; 8845 8846 enum { 8847 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8848 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8849 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8850 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8851 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8852 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8853 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8854 }; 8855 8856 struct mlx5_ifc_create_flow_table_out_bits { 8857 u8 status[0x8]; 8858 u8 icm_address_63_40[0x18]; 8859 8860 u8 syndrome[0x20]; 8861 8862 u8 icm_address_39_32[0x8]; 8863 u8 table_id[0x18]; 8864 8865 u8 icm_address_31_0[0x20]; 8866 }; 8867 8868 struct mlx5_ifc_create_flow_table_in_bits { 8869 u8 opcode[0x10]; 8870 u8 uid[0x10]; 8871 8872 u8 reserved_at_20[0x10]; 8873 u8 op_mod[0x10]; 8874 8875 u8 other_vport[0x1]; 8876 u8 reserved_at_41[0xf]; 8877 u8 vport_number[0x10]; 8878 8879 u8 reserved_at_60[0x20]; 8880 8881 u8 table_type[0x8]; 8882 u8 reserved_at_88[0x18]; 8883 8884 u8 reserved_at_a0[0x20]; 8885 8886 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8887 }; 8888 8889 struct mlx5_ifc_create_flow_group_out_bits { 8890 u8 status[0x8]; 8891 u8 reserved_at_8[0x18]; 8892 8893 u8 syndrome[0x20]; 8894 8895 u8 reserved_at_40[0x8]; 8896 u8 group_id[0x18]; 8897 8898 u8 reserved_at_60[0x20]; 8899 }; 8900 8901 enum { 8902 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8903 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8904 }; 8905 8906 enum { 8907 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8908 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8909 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8910 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8911 }; 8912 8913 struct mlx5_ifc_create_flow_group_in_bits { 8914 u8 opcode[0x10]; 8915 u8 reserved_at_10[0x10]; 8916 8917 u8 reserved_at_20[0x10]; 8918 u8 op_mod[0x10]; 8919 8920 u8 other_vport[0x1]; 8921 u8 reserved_at_41[0xf]; 8922 u8 vport_number[0x10]; 8923 8924 u8 reserved_at_60[0x20]; 8925 8926 u8 table_type[0x8]; 8927 u8 reserved_at_88[0x4]; 8928 u8 group_type[0x4]; 8929 u8 reserved_at_90[0x10]; 8930 8931 u8 reserved_at_a0[0x8]; 8932 u8 table_id[0x18]; 8933 8934 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8935 8936 u8 reserved_at_c1[0x1f]; 8937 8938 u8 start_flow_index[0x20]; 8939 8940 u8 reserved_at_100[0x20]; 8941 8942 u8 end_flow_index[0x20]; 8943 8944 u8 reserved_at_140[0x10]; 8945 u8 match_definer_id[0x10]; 8946 8947 u8 reserved_at_160[0x80]; 8948 8949 u8 reserved_at_1e0[0x18]; 8950 u8 match_criteria_enable[0x8]; 8951 8952 struct mlx5_ifc_fte_match_param_bits match_criteria; 8953 8954 u8 reserved_at_1200[0xe00]; 8955 }; 8956 8957 struct mlx5_ifc_create_eq_out_bits { 8958 u8 status[0x8]; 8959 u8 reserved_at_8[0x18]; 8960 8961 u8 syndrome[0x20]; 8962 8963 u8 reserved_at_40[0x18]; 8964 u8 eq_number[0x8]; 8965 8966 u8 reserved_at_60[0x20]; 8967 }; 8968 8969 struct mlx5_ifc_create_eq_in_bits { 8970 u8 opcode[0x10]; 8971 u8 uid[0x10]; 8972 8973 u8 reserved_at_20[0x10]; 8974 u8 op_mod[0x10]; 8975 8976 u8 reserved_at_40[0x40]; 8977 8978 struct mlx5_ifc_eqc_bits eq_context_entry; 8979 8980 u8 reserved_at_280[0x40]; 8981 8982 u8 event_bitmask[4][0x40]; 8983 8984 u8 reserved_at_3c0[0x4c0]; 8985 8986 u8 pas[][0x40]; 8987 }; 8988 8989 struct mlx5_ifc_create_dct_out_bits { 8990 u8 status[0x8]; 8991 u8 reserved_at_8[0x18]; 8992 8993 u8 syndrome[0x20]; 8994 8995 u8 reserved_at_40[0x8]; 8996 u8 dctn[0x18]; 8997 8998 u8 ece[0x20]; 8999 }; 9000 9001 struct mlx5_ifc_create_dct_in_bits { 9002 u8 opcode[0x10]; 9003 u8 uid[0x10]; 9004 9005 u8 reserved_at_20[0x10]; 9006 u8 op_mod[0x10]; 9007 9008 u8 reserved_at_40[0x40]; 9009 9010 struct mlx5_ifc_dctc_bits dct_context_entry; 9011 9012 u8 reserved_at_280[0x180]; 9013 }; 9014 9015 struct mlx5_ifc_create_cq_out_bits { 9016 u8 status[0x8]; 9017 u8 reserved_at_8[0x18]; 9018 9019 u8 syndrome[0x20]; 9020 9021 u8 reserved_at_40[0x8]; 9022 u8 cqn[0x18]; 9023 9024 u8 reserved_at_60[0x20]; 9025 }; 9026 9027 struct mlx5_ifc_create_cq_in_bits { 9028 u8 opcode[0x10]; 9029 u8 uid[0x10]; 9030 9031 u8 reserved_at_20[0x10]; 9032 u8 op_mod[0x10]; 9033 9034 u8 reserved_at_40[0x40]; 9035 9036 struct mlx5_ifc_cqc_bits cq_context; 9037 9038 u8 reserved_at_280[0x60]; 9039 9040 u8 cq_umem_valid[0x1]; 9041 u8 reserved_at_2e1[0x59f]; 9042 9043 u8 pas[][0x40]; 9044 }; 9045 9046 struct mlx5_ifc_config_int_moderation_out_bits { 9047 u8 status[0x8]; 9048 u8 reserved_at_8[0x18]; 9049 9050 u8 syndrome[0x20]; 9051 9052 u8 reserved_at_40[0x4]; 9053 u8 min_delay[0xc]; 9054 u8 int_vector[0x10]; 9055 9056 u8 reserved_at_60[0x20]; 9057 }; 9058 9059 enum { 9060 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9061 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9062 }; 9063 9064 struct mlx5_ifc_config_int_moderation_in_bits { 9065 u8 opcode[0x10]; 9066 u8 reserved_at_10[0x10]; 9067 9068 u8 reserved_at_20[0x10]; 9069 u8 op_mod[0x10]; 9070 9071 u8 reserved_at_40[0x4]; 9072 u8 min_delay[0xc]; 9073 u8 int_vector[0x10]; 9074 9075 u8 reserved_at_60[0x20]; 9076 }; 9077 9078 struct mlx5_ifc_attach_to_mcg_out_bits { 9079 u8 status[0x8]; 9080 u8 reserved_at_8[0x18]; 9081 9082 u8 syndrome[0x20]; 9083 9084 u8 reserved_at_40[0x40]; 9085 }; 9086 9087 struct mlx5_ifc_attach_to_mcg_in_bits { 9088 u8 opcode[0x10]; 9089 u8 uid[0x10]; 9090 9091 u8 reserved_at_20[0x10]; 9092 u8 op_mod[0x10]; 9093 9094 u8 reserved_at_40[0x8]; 9095 u8 qpn[0x18]; 9096 9097 u8 reserved_at_60[0x20]; 9098 9099 u8 multicast_gid[16][0x8]; 9100 }; 9101 9102 struct mlx5_ifc_arm_xrq_out_bits { 9103 u8 status[0x8]; 9104 u8 reserved_at_8[0x18]; 9105 9106 u8 syndrome[0x20]; 9107 9108 u8 reserved_at_40[0x40]; 9109 }; 9110 9111 struct mlx5_ifc_arm_xrq_in_bits { 9112 u8 opcode[0x10]; 9113 u8 reserved_at_10[0x10]; 9114 9115 u8 reserved_at_20[0x10]; 9116 u8 op_mod[0x10]; 9117 9118 u8 reserved_at_40[0x8]; 9119 u8 xrqn[0x18]; 9120 9121 u8 reserved_at_60[0x10]; 9122 u8 lwm[0x10]; 9123 }; 9124 9125 struct mlx5_ifc_arm_xrc_srq_out_bits { 9126 u8 status[0x8]; 9127 u8 reserved_at_8[0x18]; 9128 9129 u8 syndrome[0x20]; 9130 9131 u8 reserved_at_40[0x40]; 9132 }; 9133 9134 enum { 9135 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9136 }; 9137 9138 struct mlx5_ifc_arm_xrc_srq_in_bits { 9139 u8 opcode[0x10]; 9140 u8 uid[0x10]; 9141 9142 u8 reserved_at_20[0x10]; 9143 u8 op_mod[0x10]; 9144 9145 u8 reserved_at_40[0x8]; 9146 u8 xrc_srqn[0x18]; 9147 9148 u8 reserved_at_60[0x10]; 9149 u8 lwm[0x10]; 9150 }; 9151 9152 struct mlx5_ifc_arm_rq_out_bits { 9153 u8 status[0x8]; 9154 u8 reserved_at_8[0x18]; 9155 9156 u8 syndrome[0x20]; 9157 9158 u8 reserved_at_40[0x40]; 9159 }; 9160 9161 enum { 9162 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9163 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9164 }; 9165 9166 struct mlx5_ifc_arm_rq_in_bits { 9167 u8 opcode[0x10]; 9168 u8 uid[0x10]; 9169 9170 u8 reserved_at_20[0x10]; 9171 u8 op_mod[0x10]; 9172 9173 u8 reserved_at_40[0x8]; 9174 u8 srq_number[0x18]; 9175 9176 u8 reserved_at_60[0x10]; 9177 u8 lwm[0x10]; 9178 }; 9179 9180 struct mlx5_ifc_arm_dct_out_bits { 9181 u8 status[0x8]; 9182 u8 reserved_at_8[0x18]; 9183 9184 u8 syndrome[0x20]; 9185 9186 u8 reserved_at_40[0x40]; 9187 }; 9188 9189 struct mlx5_ifc_arm_dct_in_bits { 9190 u8 opcode[0x10]; 9191 u8 reserved_at_10[0x10]; 9192 9193 u8 reserved_at_20[0x10]; 9194 u8 op_mod[0x10]; 9195 9196 u8 reserved_at_40[0x8]; 9197 u8 dct_number[0x18]; 9198 9199 u8 reserved_at_60[0x20]; 9200 }; 9201 9202 struct mlx5_ifc_alloc_xrcd_out_bits { 9203 u8 status[0x8]; 9204 u8 reserved_at_8[0x18]; 9205 9206 u8 syndrome[0x20]; 9207 9208 u8 reserved_at_40[0x8]; 9209 u8 xrcd[0x18]; 9210 9211 u8 reserved_at_60[0x20]; 9212 }; 9213 9214 struct mlx5_ifc_alloc_xrcd_in_bits { 9215 u8 opcode[0x10]; 9216 u8 uid[0x10]; 9217 9218 u8 reserved_at_20[0x10]; 9219 u8 op_mod[0x10]; 9220 9221 u8 reserved_at_40[0x40]; 9222 }; 9223 9224 struct mlx5_ifc_alloc_uar_out_bits { 9225 u8 status[0x8]; 9226 u8 reserved_at_8[0x18]; 9227 9228 u8 syndrome[0x20]; 9229 9230 u8 reserved_at_40[0x8]; 9231 u8 uar[0x18]; 9232 9233 u8 reserved_at_60[0x20]; 9234 }; 9235 9236 struct mlx5_ifc_alloc_uar_in_bits { 9237 u8 opcode[0x10]; 9238 u8 uid[0x10]; 9239 9240 u8 reserved_at_20[0x10]; 9241 u8 op_mod[0x10]; 9242 9243 u8 reserved_at_40[0x40]; 9244 }; 9245 9246 struct mlx5_ifc_alloc_transport_domain_out_bits { 9247 u8 status[0x8]; 9248 u8 reserved_at_8[0x18]; 9249 9250 u8 syndrome[0x20]; 9251 9252 u8 reserved_at_40[0x8]; 9253 u8 transport_domain[0x18]; 9254 9255 u8 reserved_at_60[0x20]; 9256 }; 9257 9258 struct mlx5_ifc_alloc_transport_domain_in_bits { 9259 u8 opcode[0x10]; 9260 u8 uid[0x10]; 9261 9262 u8 reserved_at_20[0x10]; 9263 u8 op_mod[0x10]; 9264 9265 u8 reserved_at_40[0x40]; 9266 }; 9267 9268 struct mlx5_ifc_alloc_q_counter_out_bits { 9269 u8 status[0x8]; 9270 u8 reserved_at_8[0x18]; 9271 9272 u8 syndrome[0x20]; 9273 9274 u8 reserved_at_40[0x18]; 9275 u8 counter_set_id[0x8]; 9276 9277 u8 reserved_at_60[0x20]; 9278 }; 9279 9280 struct mlx5_ifc_alloc_q_counter_in_bits { 9281 u8 opcode[0x10]; 9282 u8 uid[0x10]; 9283 9284 u8 reserved_at_20[0x10]; 9285 u8 op_mod[0x10]; 9286 9287 u8 reserved_at_40[0x40]; 9288 }; 9289 9290 struct mlx5_ifc_alloc_pd_out_bits { 9291 u8 status[0x8]; 9292 u8 reserved_at_8[0x18]; 9293 9294 u8 syndrome[0x20]; 9295 9296 u8 reserved_at_40[0x8]; 9297 u8 pd[0x18]; 9298 9299 u8 reserved_at_60[0x20]; 9300 }; 9301 9302 struct mlx5_ifc_alloc_pd_in_bits { 9303 u8 opcode[0x10]; 9304 u8 uid[0x10]; 9305 9306 u8 reserved_at_20[0x10]; 9307 u8 op_mod[0x10]; 9308 9309 u8 reserved_at_40[0x40]; 9310 }; 9311 9312 struct mlx5_ifc_alloc_flow_counter_out_bits { 9313 u8 status[0x8]; 9314 u8 reserved_at_8[0x18]; 9315 9316 u8 syndrome[0x20]; 9317 9318 u8 flow_counter_id[0x20]; 9319 9320 u8 reserved_at_60[0x20]; 9321 }; 9322 9323 struct mlx5_ifc_alloc_flow_counter_in_bits { 9324 u8 opcode[0x10]; 9325 u8 reserved_at_10[0x10]; 9326 9327 u8 reserved_at_20[0x10]; 9328 u8 op_mod[0x10]; 9329 9330 u8 reserved_at_40[0x33]; 9331 u8 flow_counter_bulk_log_size[0x5]; 9332 u8 flow_counter_bulk[0x8]; 9333 }; 9334 9335 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9336 u8 status[0x8]; 9337 u8 reserved_at_8[0x18]; 9338 9339 u8 syndrome[0x20]; 9340 9341 u8 reserved_at_40[0x40]; 9342 }; 9343 9344 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9345 u8 opcode[0x10]; 9346 u8 reserved_at_10[0x10]; 9347 9348 u8 reserved_at_20[0x10]; 9349 u8 op_mod[0x10]; 9350 9351 u8 reserved_at_40[0x20]; 9352 9353 u8 reserved_at_60[0x10]; 9354 u8 vxlan_udp_port[0x10]; 9355 }; 9356 9357 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9358 u8 status[0x8]; 9359 u8 reserved_at_8[0x18]; 9360 9361 u8 syndrome[0x20]; 9362 9363 u8 reserved_at_40[0x40]; 9364 }; 9365 9366 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9367 u8 rate_limit[0x20]; 9368 9369 u8 burst_upper_bound[0x20]; 9370 9371 u8 reserved_at_40[0x10]; 9372 u8 typical_packet_size[0x10]; 9373 9374 u8 reserved_at_60[0x120]; 9375 }; 9376 9377 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9378 u8 opcode[0x10]; 9379 u8 uid[0x10]; 9380 9381 u8 reserved_at_20[0x10]; 9382 u8 op_mod[0x10]; 9383 9384 u8 reserved_at_40[0x10]; 9385 u8 rate_limit_index[0x10]; 9386 9387 u8 reserved_at_60[0x20]; 9388 9389 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9390 }; 9391 9392 struct mlx5_ifc_access_register_out_bits { 9393 u8 status[0x8]; 9394 u8 reserved_at_8[0x18]; 9395 9396 u8 syndrome[0x20]; 9397 9398 u8 reserved_at_40[0x40]; 9399 9400 u8 register_data[][0x20]; 9401 }; 9402 9403 enum { 9404 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9405 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9406 }; 9407 9408 struct mlx5_ifc_access_register_in_bits { 9409 u8 opcode[0x10]; 9410 u8 reserved_at_10[0x10]; 9411 9412 u8 reserved_at_20[0x10]; 9413 u8 op_mod[0x10]; 9414 9415 u8 reserved_at_40[0x10]; 9416 u8 register_id[0x10]; 9417 9418 u8 argument[0x20]; 9419 9420 u8 register_data[][0x20]; 9421 }; 9422 9423 struct mlx5_ifc_sltp_reg_bits { 9424 u8 status[0x4]; 9425 u8 version[0x4]; 9426 u8 local_port[0x8]; 9427 u8 pnat[0x2]; 9428 u8 reserved_at_12[0x2]; 9429 u8 lane[0x4]; 9430 u8 reserved_at_18[0x8]; 9431 9432 u8 reserved_at_20[0x20]; 9433 9434 u8 reserved_at_40[0x7]; 9435 u8 polarity[0x1]; 9436 u8 ob_tap0[0x8]; 9437 u8 ob_tap1[0x8]; 9438 u8 ob_tap2[0x8]; 9439 9440 u8 reserved_at_60[0xc]; 9441 u8 ob_preemp_mode[0x4]; 9442 u8 ob_reg[0x8]; 9443 u8 ob_bias[0x8]; 9444 9445 u8 reserved_at_80[0x20]; 9446 }; 9447 9448 struct mlx5_ifc_slrg_reg_bits { 9449 u8 status[0x4]; 9450 u8 version[0x4]; 9451 u8 local_port[0x8]; 9452 u8 pnat[0x2]; 9453 u8 reserved_at_12[0x2]; 9454 u8 lane[0x4]; 9455 u8 reserved_at_18[0x8]; 9456 9457 u8 time_to_link_up[0x10]; 9458 u8 reserved_at_30[0xc]; 9459 u8 grade_lane_speed[0x4]; 9460 9461 u8 grade_version[0x8]; 9462 u8 grade[0x18]; 9463 9464 u8 reserved_at_60[0x4]; 9465 u8 height_grade_type[0x4]; 9466 u8 height_grade[0x18]; 9467 9468 u8 height_dz[0x10]; 9469 u8 height_dv[0x10]; 9470 9471 u8 reserved_at_a0[0x10]; 9472 u8 height_sigma[0x10]; 9473 9474 u8 reserved_at_c0[0x20]; 9475 9476 u8 reserved_at_e0[0x4]; 9477 u8 phase_grade_type[0x4]; 9478 u8 phase_grade[0x18]; 9479 9480 u8 reserved_at_100[0x8]; 9481 u8 phase_eo_pos[0x8]; 9482 u8 reserved_at_110[0x8]; 9483 u8 phase_eo_neg[0x8]; 9484 9485 u8 ffe_set_tested[0x10]; 9486 u8 test_errors_per_lane[0x10]; 9487 }; 9488 9489 struct mlx5_ifc_pvlc_reg_bits { 9490 u8 reserved_at_0[0x8]; 9491 u8 local_port[0x8]; 9492 u8 reserved_at_10[0x10]; 9493 9494 u8 reserved_at_20[0x1c]; 9495 u8 vl_hw_cap[0x4]; 9496 9497 u8 reserved_at_40[0x1c]; 9498 u8 vl_admin[0x4]; 9499 9500 u8 reserved_at_60[0x1c]; 9501 u8 vl_operational[0x4]; 9502 }; 9503 9504 struct mlx5_ifc_pude_reg_bits { 9505 u8 swid[0x8]; 9506 u8 local_port[0x8]; 9507 u8 reserved_at_10[0x4]; 9508 u8 admin_status[0x4]; 9509 u8 reserved_at_18[0x4]; 9510 u8 oper_status[0x4]; 9511 9512 u8 reserved_at_20[0x60]; 9513 }; 9514 9515 struct mlx5_ifc_ptys_reg_bits { 9516 u8 reserved_at_0[0x1]; 9517 u8 an_disable_admin[0x1]; 9518 u8 an_disable_cap[0x1]; 9519 u8 reserved_at_3[0x5]; 9520 u8 local_port[0x8]; 9521 u8 reserved_at_10[0xd]; 9522 u8 proto_mask[0x3]; 9523 9524 u8 an_status[0x4]; 9525 u8 reserved_at_24[0xc]; 9526 u8 data_rate_oper[0x10]; 9527 9528 u8 ext_eth_proto_capability[0x20]; 9529 9530 u8 eth_proto_capability[0x20]; 9531 9532 u8 ib_link_width_capability[0x10]; 9533 u8 ib_proto_capability[0x10]; 9534 9535 u8 ext_eth_proto_admin[0x20]; 9536 9537 u8 eth_proto_admin[0x20]; 9538 9539 u8 ib_link_width_admin[0x10]; 9540 u8 ib_proto_admin[0x10]; 9541 9542 u8 ext_eth_proto_oper[0x20]; 9543 9544 u8 eth_proto_oper[0x20]; 9545 9546 u8 ib_link_width_oper[0x10]; 9547 u8 ib_proto_oper[0x10]; 9548 9549 u8 reserved_at_160[0x1c]; 9550 u8 connector_type[0x4]; 9551 9552 u8 eth_proto_lp_advertise[0x20]; 9553 9554 u8 reserved_at_1a0[0x60]; 9555 }; 9556 9557 struct mlx5_ifc_mlcr_reg_bits { 9558 u8 reserved_at_0[0x8]; 9559 u8 local_port[0x8]; 9560 u8 reserved_at_10[0x20]; 9561 9562 u8 beacon_duration[0x10]; 9563 u8 reserved_at_40[0x10]; 9564 9565 u8 beacon_remain[0x10]; 9566 }; 9567 9568 struct mlx5_ifc_ptas_reg_bits { 9569 u8 reserved_at_0[0x20]; 9570 9571 u8 algorithm_options[0x10]; 9572 u8 reserved_at_30[0x4]; 9573 u8 repetitions_mode[0x4]; 9574 u8 num_of_repetitions[0x8]; 9575 9576 u8 grade_version[0x8]; 9577 u8 height_grade_type[0x4]; 9578 u8 phase_grade_type[0x4]; 9579 u8 height_grade_weight[0x8]; 9580 u8 phase_grade_weight[0x8]; 9581 9582 u8 gisim_measure_bits[0x10]; 9583 u8 adaptive_tap_measure_bits[0x10]; 9584 9585 u8 ber_bath_high_error_threshold[0x10]; 9586 u8 ber_bath_mid_error_threshold[0x10]; 9587 9588 u8 ber_bath_low_error_threshold[0x10]; 9589 u8 one_ratio_high_threshold[0x10]; 9590 9591 u8 one_ratio_high_mid_threshold[0x10]; 9592 u8 one_ratio_low_mid_threshold[0x10]; 9593 9594 u8 one_ratio_low_threshold[0x10]; 9595 u8 ndeo_error_threshold[0x10]; 9596 9597 u8 mixer_offset_step_size[0x10]; 9598 u8 reserved_at_110[0x8]; 9599 u8 mix90_phase_for_voltage_bath[0x8]; 9600 9601 u8 mixer_offset_start[0x10]; 9602 u8 mixer_offset_end[0x10]; 9603 9604 u8 reserved_at_140[0x15]; 9605 u8 ber_test_time[0xb]; 9606 }; 9607 9608 struct mlx5_ifc_pspa_reg_bits { 9609 u8 swid[0x8]; 9610 u8 local_port[0x8]; 9611 u8 sub_port[0x8]; 9612 u8 reserved_at_18[0x8]; 9613 9614 u8 reserved_at_20[0x20]; 9615 }; 9616 9617 struct mlx5_ifc_pqdr_reg_bits { 9618 u8 reserved_at_0[0x8]; 9619 u8 local_port[0x8]; 9620 u8 reserved_at_10[0x5]; 9621 u8 prio[0x3]; 9622 u8 reserved_at_18[0x6]; 9623 u8 mode[0x2]; 9624 9625 u8 reserved_at_20[0x20]; 9626 9627 u8 reserved_at_40[0x10]; 9628 u8 min_threshold[0x10]; 9629 9630 u8 reserved_at_60[0x10]; 9631 u8 max_threshold[0x10]; 9632 9633 u8 reserved_at_80[0x10]; 9634 u8 mark_probability_denominator[0x10]; 9635 9636 u8 reserved_at_a0[0x60]; 9637 }; 9638 9639 struct mlx5_ifc_ppsc_reg_bits { 9640 u8 reserved_at_0[0x8]; 9641 u8 local_port[0x8]; 9642 u8 reserved_at_10[0x10]; 9643 9644 u8 reserved_at_20[0x60]; 9645 9646 u8 reserved_at_80[0x1c]; 9647 u8 wrps_admin[0x4]; 9648 9649 u8 reserved_at_a0[0x1c]; 9650 u8 wrps_status[0x4]; 9651 9652 u8 reserved_at_c0[0x8]; 9653 u8 up_threshold[0x8]; 9654 u8 reserved_at_d0[0x8]; 9655 u8 down_threshold[0x8]; 9656 9657 u8 reserved_at_e0[0x20]; 9658 9659 u8 reserved_at_100[0x1c]; 9660 u8 srps_admin[0x4]; 9661 9662 u8 reserved_at_120[0x1c]; 9663 u8 srps_status[0x4]; 9664 9665 u8 reserved_at_140[0x40]; 9666 }; 9667 9668 struct mlx5_ifc_pplr_reg_bits { 9669 u8 reserved_at_0[0x8]; 9670 u8 local_port[0x8]; 9671 u8 reserved_at_10[0x10]; 9672 9673 u8 reserved_at_20[0x8]; 9674 u8 lb_cap[0x8]; 9675 u8 reserved_at_30[0x8]; 9676 u8 lb_en[0x8]; 9677 }; 9678 9679 struct mlx5_ifc_pplm_reg_bits { 9680 u8 reserved_at_0[0x8]; 9681 u8 local_port[0x8]; 9682 u8 reserved_at_10[0x10]; 9683 9684 u8 reserved_at_20[0x20]; 9685 9686 u8 port_profile_mode[0x8]; 9687 u8 static_port_profile[0x8]; 9688 u8 active_port_profile[0x8]; 9689 u8 reserved_at_58[0x8]; 9690 9691 u8 retransmission_active[0x8]; 9692 u8 fec_mode_active[0x18]; 9693 9694 u8 rs_fec_correction_bypass_cap[0x4]; 9695 u8 reserved_at_84[0x8]; 9696 u8 fec_override_cap_56g[0x4]; 9697 u8 fec_override_cap_100g[0x4]; 9698 u8 fec_override_cap_50g[0x4]; 9699 u8 fec_override_cap_25g[0x4]; 9700 u8 fec_override_cap_10g_40g[0x4]; 9701 9702 u8 rs_fec_correction_bypass_admin[0x4]; 9703 u8 reserved_at_a4[0x8]; 9704 u8 fec_override_admin_56g[0x4]; 9705 u8 fec_override_admin_100g[0x4]; 9706 u8 fec_override_admin_50g[0x4]; 9707 u8 fec_override_admin_25g[0x4]; 9708 u8 fec_override_admin_10g_40g[0x4]; 9709 9710 u8 fec_override_cap_400g_8x[0x10]; 9711 u8 fec_override_cap_200g_4x[0x10]; 9712 9713 u8 fec_override_cap_100g_2x[0x10]; 9714 u8 fec_override_cap_50g_1x[0x10]; 9715 9716 u8 fec_override_admin_400g_8x[0x10]; 9717 u8 fec_override_admin_200g_4x[0x10]; 9718 9719 u8 fec_override_admin_100g_2x[0x10]; 9720 u8 fec_override_admin_50g_1x[0x10]; 9721 9722 u8 reserved_at_140[0x140]; 9723 }; 9724 9725 struct mlx5_ifc_ppcnt_reg_bits { 9726 u8 swid[0x8]; 9727 u8 local_port[0x8]; 9728 u8 pnat[0x2]; 9729 u8 reserved_at_12[0x8]; 9730 u8 grp[0x6]; 9731 9732 u8 clr[0x1]; 9733 u8 reserved_at_21[0x1c]; 9734 u8 prio_tc[0x3]; 9735 9736 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9737 }; 9738 9739 struct mlx5_ifc_mpein_reg_bits { 9740 u8 reserved_at_0[0x2]; 9741 u8 depth[0x6]; 9742 u8 pcie_index[0x8]; 9743 u8 node[0x8]; 9744 u8 reserved_at_18[0x8]; 9745 9746 u8 capability_mask[0x20]; 9747 9748 u8 reserved_at_40[0x8]; 9749 u8 link_width_enabled[0x8]; 9750 u8 link_speed_enabled[0x10]; 9751 9752 u8 lane0_physical_position[0x8]; 9753 u8 link_width_active[0x8]; 9754 u8 link_speed_active[0x10]; 9755 9756 u8 num_of_pfs[0x10]; 9757 u8 num_of_vfs[0x10]; 9758 9759 u8 bdf0[0x10]; 9760 u8 reserved_at_b0[0x10]; 9761 9762 u8 max_read_request_size[0x4]; 9763 u8 max_payload_size[0x4]; 9764 u8 reserved_at_c8[0x5]; 9765 u8 pwr_status[0x3]; 9766 u8 port_type[0x4]; 9767 u8 reserved_at_d4[0xb]; 9768 u8 lane_reversal[0x1]; 9769 9770 u8 reserved_at_e0[0x14]; 9771 u8 pci_power[0xc]; 9772 9773 u8 reserved_at_100[0x20]; 9774 9775 u8 device_status[0x10]; 9776 u8 port_state[0x8]; 9777 u8 reserved_at_138[0x8]; 9778 9779 u8 reserved_at_140[0x10]; 9780 u8 receiver_detect_result[0x10]; 9781 9782 u8 reserved_at_160[0x20]; 9783 }; 9784 9785 struct mlx5_ifc_mpcnt_reg_bits { 9786 u8 reserved_at_0[0x8]; 9787 u8 pcie_index[0x8]; 9788 u8 reserved_at_10[0xa]; 9789 u8 grp[0x6]; 9790 9791 u8 clr[0x1]; 9792 u8 reserved_at_21[0x1f]; 9793 9794 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9795 }; 9796 9797 struct mlx5_ifc_ppad_reg_bits { 9798 u8 reserved_at_0[0x3]; 9799 u8 single_mac[0x1]; 9800 u8 reserved_at_4[0x4]; 9801 u8 local_port[0x8]; 9802 u8 mac_47_32[0x10]; 9803 9804 u8 mac_31_0[0x20]; 9805 9806 u8 reserved_at_40[0x40]; 9807 }; 9808 9809 struct mlx5_ifc_pmtu_reg_bits { 9810 u8 reserved_at_0[0x8]; 9811 u8 local_port[0x8]; 9812 u8 reserved_at_10[0x10]; 9813 9814 u8 max_mtu[0x10]; 9815 u8 reserved_at_30[0x10]; 9816 9817 u8 admin_mtu[0x10]; 9818 u8 reserved_at_50[0x10]; 9819 9820 u8 oper_mtu[0x10]; 9821 u8 reserved_at_70[0x10]; 9822 }; 9823 9824 struct mlx5_ifc_pmpr_reg_bits { 9825 u8 reserved_at_0[0x8]; 9826 u8 module[0x8]; 9827 u8 reserved_at_10[0x10]; 9828 9829 u8 reserved_at_20[0x18]; 9830 u8 attenuation_5g[0x8]; 9831 9832 u8 reserved_at_40[0x18]; 9833 u8 attenuation_7g[0x8]; 9834 9835 u8 reserved_at_60[0x18]; 9836 u8 attenuation_12g[0x8]; 9837 }; 9838 9839 struct mlx5_ifc_pmpe_reg_bits { 9840 u8 reserved_at_0[0x8]; 9841 u8 module[0x8]; 9842 u8 reserved_at_10[0xc]; 9843 u8 module_status[0x4]; 9844 9845 u8 reserved_at_20[0x60]; 9846 }; 9847 9848 struct mlx5_ifc_pmpc_reg_bits { 9849 u8 module_state_updated[32][0x8]; 9850 }; 9851 9852 struct mlx5_ifc_pmlpn_reg_bits { 9853 u8 reserved_at_0[0x4]; 9854 u8 mlpn_status[0x4]; 9855 u8 local_port[0x8]; 9856 u8 reserved_at_10[0x10]; 9857 9858 u8 e[0x1]; 9859 u8 reserved_at_21[0x1f]; 9860 }; 9861 9862 struct mlx5_ifc_pmlp_reg_bits { 9863 u8 rxtx[0x1]; 9864 u8 reserved_at_1[0x7]; 9865 u8 local_port[0x8]; 9866 u8 reserved_at_10[0x8]; 9867 u8 width[0x8]; 9868 9869 u8 lane0_module_mapping[0x20]; 9870 9871 u8 lane1_module_mapping[0x20]; 9872 9873 u8 lane2_module_mapping[0x20]; 9874 9875 u8 lane3_module_mapping[0x20]; 9876 9877 u8 reserved_at_a0[0x160]; 9878 }; 9879 9880 struct mlx5_ifc_pmaos_reg_bits { 9881 u8 reserved_at_0[0x8]; 9882 u8 module[0x8]; 9883 u8 reserved_at_10[0x4]; 9884 u8 admin_status[0x4]; 9885 u8 reserved_at_18[0x4]; 9886 u8 oper_status[0x4]; 9887 9888 u8 ase[0x1]; 9889 u8 ee[0x1]; 9890 u8 reserved_at_22[0x1c]; 9891 u8 e[0x2]; 9892 9893 u8 reserved_at_40[0x40]; 9894 }; 9895 9896 struct mlx5_ifc_plpc_reg_bits { 9897 u8 reserved_at_0[0x4]; 9898 u8 profile_id[0xc]; 9899 u8 reserved_at_10[0x4]; 9900 u8 proto_mask[0x4]; 9901 u8 reserved_at_18[0x8]; 9902 9903 u8 reserved_at_20[0x10]; 9904 u8 lane_speed[0x10]; 9905 9906 u8 reserved_at_40[0x17]; 9907 u8 lpbf[0x1]; 9908 u8 fec_mode_policy[0x8]; 9909 9910 u8 retransmission_capability[0x8]; 9911 u8 fec_mode_capability[0x18]; 9912 9913 u8 retransmission_support_admin[0x8]; 9914 u8 fec_mode_support_admin[0x18]; 9915 9916 u8 retransmission_request_admin[0x8]; 9917 u8 fec_mode_request_admin[0x18]; 9918 9919 u8 reserved_at_c0[0x80]; 9920 }; 9921 9922 struct mlx5_ifc_plib_reg_bits { 9923 u8 reserved_at_0[0x8]; 9924 u8 local_port[0x8]; 9925 u8 reserved_at_10[0x8]; 9926 u8 ib_port[0x8]; 9927 9928 u8 reserved_at_20[0x60]; 9929 }; 9930 9931 struct mlx5_ifc_plbf_reg_bits { 9932 u8 reserved_at_0[0x8]; 9933 u8 local_port[0x8]; 9934 u8 reserved_at_10[0xd]; 9935 u8 lbf_mode[0x3]; 9936 9937 u8 reserved_at_20[0x20]; 9938 }; 9939 9940 struct mlx5_ifc_pipg_reg_bits { 9941 u8 reserved_at_0[0x8]; 9942 u8 local_port[0x8]; 9943 u8 reserved_at_10[0x10]; 9944 9945 u8 dic[0x1]; 9946 u8 reserved_at_21[0x19]; 9947 u8 ipg[0x4]; 9948 u8 reserved_at_3e[0x2]; 9949 }; 9950 9951 struct mlx5_ifc_pifr_reg_bits { 9952 u8 reserved_at_0[0x8]; 9953 u8 local_port[0x8]; 9954 u8 reserved_at_10[0x10]; 9955 9956 u8 reserved_at_20[0xe0]; 9957 9958 u8 port_filter[8][0x20]; 9959 9960 u8 port_filter_update_en[8][0x20]; 9961 }; 9962 9963 struct mlx5_ifc_pfcc_reg_bits { 9964 u8 reserved_at_0[0x8]; 9965 u8 local_port[0x8]; 9966 u8 reserved_at_10[0xb]; 9967 u8 ppan_mask_n[0x1]; 9968 u8 minor_stall_mask[0x1]; 9969 u8 critical_stall_mask[0x1]; 9970 u8 reserved_at_1e[0x2]; 9971 9972 u8 ppan[0x4]; 9973 u8 reserved_at_24[0x4]; 9974 u8 prio_mask_tx[0x8]; 9975 u8 reserved_at_30[0x8]; 9976 u8 prio_mask_rx[0x8]; 9977 9978 u8 pptx[0x1]; 9979 u8 aptx[0x1]; 9980 u8 pptx_mask_n[0x1]; 9981 u8 reserved_at_43[0x5]; 9982 u8 pfctx[0x8]; 9983 u8 reserved_at_50[0x10]; 9984 9985 u8 pprx[0x1]; 9986 u8 aprx[0x1]; 9987 u8 pprx_mask_n[0x1]; 9988 u8 reserved_at_63[0x5]; 9989 u8 pfcrx[0x8]; 9990 u8 reserved_at_70[0x10]; 9991 9992 u8 device_stall_minor_watermark[0x10]; 9993 u8 device_stall_critical_watermark[0x10]; 9994 9995 u8 reserved_at_a0[0x60]; 9996 }; 9997 9998 struct mlx5_ifc_pelc_reg_bits { 9999 u8 op[0x4]; 10000 u8 reserved_at_4[0x4]; 10001 u8 local_port[0x8]; 10002 u8 reserved_at_10[0x10]; 10003 10004 u8 op_admin[0x8]; 10005 u8 op_capability[0x8]; 10006 u8 op_request[0x8]; 10007 u8 op_active[0x8]; 10008 10009 u8 admin[0x40]; 10010 10011 u8 capability[0x40]; 10012 10013 u8 request[0x40]; 10014 10015 u8 active[0x40]; 10016 10017 u8 reserved_at_140[0x80]; 10018 }; 10019 10020 struct mlx5_ifc_peir_reg_bits { 10021 u8 reserved_at_0[0x8]; 10022 u8 local_port[0x8]; 10023 u8 reserved_at_10[0x10]; 10024 10025 u8 reserved_at_20[0xc]; 10026 u8 error_count[0x4]; 10027 u8 reserved_at_30[0x10]; 10028 10029 u8 reserved_at_40[0xc]; 10030 u8 lane[0x4]; 10031 u8 reserved_at_50[0x8]; 10032 u8 error_type[0x8]; 10033 }; 10034 10035 struct mlx5_ifc_mpegc_reg_bits { 10036 u8 reserved_at_0[0x30]; 10037 u8 field_select[0x10]; 10038 10039 u8 tx_overflow_sense[0x1]; 10040 u8 mark_cqe[0x1]; 10041 u8 mark_cnp[0x1]; 10042 u8 reserved_at_43[0x1b]; 10043 u8 tx_lossy_overflow_oper[0x2]; 10044 10045 u8 reserved_at_60[0x100]; 10046 }; 10047 10048 enum { 10049 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10050 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10051 }; 10052 10053 enum { 10054 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10055 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10056 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10057 }; 10058 10059 struct mlx5_ifc_mtutc_reg_bits { 10060 u8 reserved_at_0[0x5]; 10061 u8 freq_adj_units[0x3]; 10062 u8 reserved_at_8[0x14]; 10063 u8 operation[0x4]; 10064 10065 u8 freq_adjustment[0x20]; 10066 10067 u8 reserved_at_40[0x40]; 10068 10069 u8 utc_sec[0x20]; 10070 10071 u8 reserved_at_a0[0x2]; 10072 u8 utc_nsec[0x1e]; 10073 10074 u8 time_adjustment[0x20]; 10075 }; 10076 10077 struct mlx5_ifc_pcam_enhanced_features_bits { 10078 u8 reserved_at_0[0x68]; 10079 u8 fec_50G_per_lane_in_pplm[0x1]; 10080 u8 reserved_at_69[0x4]; 10081 u8 rx_icrc_encapsulated_counter[0x1]; 10082 u8 reserved_at_6e[0x4]; 10083 u8 ptys_extended_ethernet[0x1]; 10084 u8 reserved_at_73[0x3]; 10085 u8 pfcc_mask[0x1]; 10086 u8 reserved_at_77[0x3]; 10087 u8 per_lane_error_counters[0x1]; 10088 u8 rx_buffer_fullness_counters[0x1]; 10089 u8 ptys_connector_type[0x1]; 10090 u8 reserved_at_7d[0x1]; 10091 u8 ppcnt_discard_group[0x1]; 10092 u8 ppcnt_statistical_group[0x1]; 10093 }; 10094 10095 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10096 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10097 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10098 10099 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10100 u8 pplm[0x1]; 10101 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10102 10103 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10104 u8 pbmc[0x1]; 10105 u8 pptb[0x1]; 10106 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10107 u8 ppcnt[0x1]; 10108 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10109 }; 10110 10111 struct mlx5_ifc_pcam_reg_bits { 10112 u8 reserved_at_0[0x8]; 10113 u8 feature_group[0x8]; 10114 u8 reserved_at_10[0x8]; 10115 u8 access_reg_group[0x8]; 10116 10117 u8 reserved_at_20[0x20]; 10118 10119 union { 10120 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10121 u8 reserved_at_0[0x80]; 10122 } port_access_reg_cap_mask; 10123 10124 u8 reserved_at_c0[0x80]; 10125 10126 union { 10127 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10128 u8 reserved_at_0[0x80]; 10129 } feature_cap_mask; 10130 10131 u8 reserved_at_1c0[0xc0]; 10132 }; 10133 10134 struct mlx5_ifc_mcam_enhanced_features_bits { 10135 u8 reserved_at_0[0x50]; 10136 u8 mtutc_freq_adj_units[0x1]; 10137 u8 mtutc_time_adjustment_extended_range[0x1]; 10138 u8 reserved_at_52[0xb]; 10139 u8 mcia_32dwords[0x1]; 10140 u8 out_pulse_duration_ns[0x1]; 10141 u8 npps_period[0x1]; 10142 u8 reserved_at_60[0xa]; 10143 u8 reset_state[0x1]; 10144 u8 ptpcyc2realtime_modify[0x1]; 10145 u8 reserved_at_6c[0x2]; 10146 u8 pci_status_and_power[0x1]; 10147 u8 reserved_at_6f[0x5]; 10148 u8 mark_tx_action_cnp[0x1]; 10149 u8 mark_tx_action_cqe[0x1]; 10150 u8 dynamic_tx_overflow[0x1]; 10151 u8 reserved_at_77[0x4]; 10152 u8 pcie_outbound_stalled[0x1]; 10153 u8 tx_overflow_buffer_pkt[0x1]; 10154 u8 mtpps_enh_out_per_adj[0x1]; 10155 u8 mtpps_fs[0x1]; 10156 u8 pcie_performance_group[0x1]; 10157 }; 10158 10159 struct mlx5_ifc_mcam_access_reg_bits { 10160 u8 reserved_at_0[0x1c]; 10161 u8 mcda[0x1]; 10162 u8 mcc[0x1]; 10163 u8 mcqi[0x1]; 10164 u8 mcqs[0x1]; 10165 10166 u8 regs_95_to_87[0x9]; 10167 u8 mpegc[0x1]; 10168 u8 mtutc[0x1]; 10169 u8 regs_84_to_68[0x11]; 10170 u8 tracer_registers[0x4]; 10171 10172 u8 regs_63_to_46[0x12]; 10173 u8 mrtc[0x1]; 10174 u8 regs_44_to_32[0xd]; 10175 10176 u8 regs_31_to_0[0x20]; 10177 }; 10178 10179 struct mlx5_ifc_mcam_access_reg_bits1 { 10180 u8 regs_127_to_96[0x20]; 10181 10182 u8 regs_95_to_64[0x20]; 10183 10184 u8 regs_63_to_32[0x20]; 10185 10186 u8 regs_31_to_0[0x20]; 10187 }; 10188 10189 struct mlx5_ifc_mcam_access_reg_bits2 { 10190 u8 regs_127_to_99[0x1d]; 10191 u8 mirc[0x1]; 10192 u8 regs_97_to_96[0x2]; 10193 10194 u8 regs_95_to_64[0x20]; 10195 10196 u8 regs_63_to_32[0x20]; 10197 10198 u8 regs_31_to_0[0x20]; 10199 }; 10200 10201 struct mlx5_ifc_mcam_reg_bits { 10202 u8 reserved_at_0[0x8]; 10203 u8 feature_group[0x8]; 10204 u8 reserved_at_10[0x8]; 10205 u8 access_reg_group[0x8]; 10206 10207 u8 reserved_at_20[0x20]; 10208 10209 union { 10210 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10211 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10212 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10213 u8 reserved_at_0[0x80]; 10214 } mng_access_reg_cap_mask; 10215 10216 u8 reserved_at_c0[0x80]; 10217 10218 union { 10219 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10220 u8 reserved_at_0[0x80]; 10221 } mng_feature_cap_mask; 10222 10223 u8 reserved_at_1c0[0x80]; 10224 }; 10225 10226 struct mlx5_ifc_qcam_access_reg_cap_mask { 10227 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10228 u8 qpdpm[0x1]; 10229 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10230 u8 qdpm[0x1]; 10231 u8 qpts[0x1]; 10232 u8 qcap[0x1]; 10233 u8 qcam_access_reg_cap_mask_0[0x1]; 10234 }; 10235 10236 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10237 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10238 u8 qpts_trust_both[0x1]; 10239 }; 10240 10241 struct mlx5_ifc_qcam_reg_bits { 10242 u8 reserved_at_0[0x8]; 10243 u8 feature_group[0x8]; 10244 u8 reserved_at_10[0x8]; 10245 u8 access_reg_group[0x8]; 10246 u8 reserved_at_20[0x20]; 10247 10248 union { 10249 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10250 u8 reserved_at_0[0x80]; 10251 } qos_access_reg_cap_mask; 10252 10253 u8 reserved_at_c0[0x80]; 10254 10255 union { 10256 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10257 u8 reserved_at_0[0x80]; 10258 } qos_feature_cap_mask; 10259 10260 u8 reserved_at_1c0[0x80]; 10261 }; 10262 10263 struct mlx5_ifc_core_dump_reg_bits { 10264 u8 reserved_at_0[0x18]; 10265 u8 core_dump_type[0x8]; 10266 10267 u8 reserved_at_20[0x30]; 10268 u8 vhca_id[0x10]; 10269 10270 u8 reserved_at_60[0x8]; 10271 u8 qpn[0x18]; 10272 u8 reserved_at_80[0x180]; 10273 }; 10274 10275 struct mlx5_ifc_pcap_reg_bits { 10276 u8 reserved_at_0[0x8]; 10277 u8 local_port[0x8]; 10278 u8 reserved_at_10[0x10]; 10279 10280 u8 port_capability_mask[4][0x20]; 10281 }; 10282 10283 struct mlx5_ifc_paos_reg_bits { 10284 u8 swid[0x8]; 10285 u8 local_port[0x8]; 10286 u8 reserved_at_10[0x4]; 10287 u8 admin_status[0x4]; 10288 u8 reserved_at_18[0x4]; 10289 u8 oper_status[0x4]; 10290 10291 u8 ase[0x1]; 10292 u8 ee[0x1]; 10293 u8 reserved_at_22[0x1c]; 10294 u8 e[0x2]; 10295 10296 u8 reserved_at_40[0x40]; 10297 }; 10298 10299 struct mlx5_ifc_pamp_reg_bits { 10300 u8 reserved_at_0[0x8]; 10301 u8 opamp_group[0x8]; 10302 u8 reserved_at_10[0xc]; 10303 u8 opamp_group_type[0x4]; 10304 10305 u8 start_index[0x10]; 10306 u8 reserved_at_30[0x4]; 10307 u8 num_of_indices[0xc]; 10308 10309 u8 index_data[18][0x10]; 10310 }; 10311 10312 struct mlx5_ifc_pcmr_reg_bits { 10313 u8 reserved_at_0[0x8]; 10314 u8 local_port[0x8]; 10315 u8 reserved_at_10[0x10]; 10316 10317 u8 entropy_force_cap[0x1]; 10318 u8 entropy_calc_cap[0x1]; 10319 u8 entropy_gre_calc_cap[0x1]; 10320 u8 reserved_at_23[0xf]; 10321 u8 rx_ts_over_crc_cap[0x1]; 10322 u8 reserved_at_33[0xb]; 10323 u8 fcs_cap[0x1]; 10324 u8 reserved_at_3f[0x1]; 10325 10326 u8 entropy_force[0x1]; 10327 u8 entropy_calc[0x1]; 10328 u8 entropy_gre_calc[0x1]; 10329 u8 reserved_at_43[0xf]; 10330 u8 rx_ts_over_crc[0x1]; 10331 u8 reserved_at_53[0xb]; 10332 u8 fcs_chk[0x1]; 10333 u8 reserved_at_5f[0x1]; 10334 }; 10335 10336 struct mlx5_ifc_lane_2_module_mapping_bits { 10337 u8 reserved_at_0[0x4]; 10338 u8 rx_lane[0x4]; 10339 u8 reserved_at_8[0x4]; 10340 u8 tx_lane[0x4]; 10341 u8 reserved_at_10[0x8]; 10342 u8 module[0x8]; 10343 }; 10344 10345 struct mlx5_ifc_bufferx_reg_bits { 10346 u8 reserved_at_0[0x6]; 10347 u8 lossy[0x1]; 10348 u8 epsb[0x1]; 10349 u8 reserved_at_8[0x8]; 10350 u8 size[0x10]; 10351 10352 u8 xoff_threshold[0x10]; 10353 u8 xon_threshold[0x10]; 10354 }; 10355 10356 struct mlx5_ifc_set_node_in_bits { 10357 u8 node_description[64][0x8]; 10358 }; 10359 10360 struct mlx5_ifc_register_power_settings_bits { 10361 u8 reserved_at_0[0x18]; 10362 u8 power_settings_level[0x8]; 10363 10364 u8 reserved_at_20[0x60]; 10365 }; 10366 10367 struct mlx5_ifc_register_host_endianness_bits { 10368 u8 he[0x1]; 10369 u8 reserved_at_1[0x1f]; 10370 10371 u8 reserved_at_20[0x60]; 10372 }; 10373 10374 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10375 u8 reserved_at_0[0x20]; 10376 10377 u8 mkey[0x20]; 10378 10379 u8 addressh_63_32[0x20]; 10380 10381 u8 addressl_31_0[0x20]; 10382 }; 10383 10384 struct mlx5_ifc_ud_adrs_vector_bits { 10385 u8 dc_key[0x40]; 10386 10387 u8 ext[0x1]; 10388 u8 reserved_at_41[0x7]; 10389 u8 destination_qp_dct[0x18]; 10390 10391 u8 static_rate[0x4]; 10392 u8 sl_eth_prio[0x4]; 10393 u8 fl[0x1]; 10394 u8 mlid[0x7]; 10395 u8 rlid_udp_sport[0x10]; 10396 10397 u8 reserved_at_80[0x20]; 10398 10399 u8 rmac_47_16[0x20]; 10400 10401 u8 rmac_15_0[0x10]; 10402 u8 tclass[0x8]; 10403 u8 hop_limit[0x8]; 10404 10405 u8 reserved_at_e0[0x1]; 10406 u8 grh[0x1]; 10407 u8 reserved_at_e2[0x2]; 10408 u8 src_addr_index[0x8]; 10409 u8 flow_label[0x14]; 10410 10411 u8 rgid_rip[16][0x8]; 10412 }; 10413 10414 struct mlx5_ifc_pages_req_event_bits { 10415 u8 reserved_at_0[0x10]; 10416 u8 function_id[0x10]; 10417 10418 u8 num_pages[0x20]; 10419 10420 u8 reserved_at_40[0xa0]; 10421 }; 10422 10423 struct mlx5_ifc_eqe_bits { 10424 u8 reserved_at_0[0x8]; 10425 u8 event_type[0x8]; 10426 u8 reserved_at_10[0x8]; 10427 u8 event_sub_type[0x8]; 10428 10429 u8 reserved_at_20[0xe0]; 10430 10431 union mlx5_ifc_event_auto_bits event_data; 10432 10433 u8 reserved_at_1e0[0x10]; 10434 u8 signature[0x8]; 10435 u8 reserved_at_1f8[0x7]; 10436 u8 owner[0x1]; 10437 }; 10438 10439 enum { 10440 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10441 }; 10442 10443 struct mlx5_ifc_cmd_queue_entry_bits { 10444 u8 type[0x8]; 10445 u8 reserved_at_8[0x18]; 10446 10447 u8 input_length[0x20]; 10448 10449 u8 input_mailbox_pointer_63_32[0x20]; 10450 10451 u8 input_mailbox_pointer_31_9[0x17]; 10452 u8 reserved_at_77[0x9]; 10453 10454 u8 command_input_inline_data[16][0x8]; 10455 10456 u8 command_output_inline_data[16][0x8]; 10457 10458 u8 output_mailbox_pointer_63_32[0x20]; 10459 10460 u8 output_mailbox_pointer_31_9[0x17]; 10461 u8 reserved_at_1b7[0x9]; 10462 10463 u8 output_length[0x20]; 10464 10465 u8 token[0x8]; 10466 u8 signature[0x8]; 10467 u8 reserved_at_1f0[0x8]; 10468 u8 status[0x7]; 10469 u8 ownership[0x1]; 10470 }; 10471 10472 struct mlx5_ifc_cmd_out_bits { 10473 u8 status[0x8]; 10474 u8 reserved_at_8[0x18]; 10475 10476 u8 syndrome[0x20]; 10477 10478 u8 command_output[0x20]; 10479 }; 10480 10481 struct mlx5_ifc_cmd_in_bits { 10482 u8 opcode[0x10]; 10483 u8 reserved_at_10[0x10]; 10484 10485 u8 reserved_at_20[0x10]; 10486 u8 op_mod[0x10]; 10487 10488 u8 command[][0x20]; 10489 }; 10490 10491 struct mlx5_ifc_cmd_if_box_bits { 10492 u8 mailbox_data[512][0x8]; 10493 10494 u8 reserved_at_1000[0x180]; 10495 10496 u8 next_pointer_63_32[0x20]; 10497 10498 u8 next_pointer_31_10[0x16]; 10499 u8 reserved_at_11b6[0xa]; 10500 10501 u8 block_number[0x20]; 10502 10503 u8 reserved_at_11e0[0x8]; 10504 u8 token[0x8]; 10505 u8 ctrl_signature[0x8]; 10506 u8 signature[0x8]; 10507 }; 10508 10509 struct mlx5_ifc_mtt_bits { 10510 u8 ptag_63_32[0x20]; 10511 10512 u8 ptag_31_8[0x18]; 10513 u8 reserved_at_38[0x6]; 10514 u8 wr_en[0x1]; 10515 u8 rd_en[0x1]; 10516 }; 10517 10518 struct mlx5_ifc_query_wol_rol_out_bits { 10519 u8 status[0x8]; 10520 u8 reserved_at_8[0x18]; 10521 10522 u8 syndrome[0x20]; 10523 10524 u8 reserved_at_40[0x10]; 10525 u8 rol_mode[0x8]; 10526 u8 wol_mode[0x8]; 10527 10528 u8 reserved_at_60[0x20]; 10529 }; 10530 10531 struct mlx5_ifc_query_wol_rol_in_bits { 10532 u8 opcode[0x10]; 10533 u8 reserved_at_10[0x10]; 10534 10535 u8 reserved_at_20[0x10]; 10536 u8 op_mod[0x10]; 10537 10538 u8 reserved_at_40[0x40]; 10539 }; 10540 10541 struct mlx5_ifc_set_wol_rol_out_bits { 10542 u8 status[0x8]; 10543 u8 reserved_at_8[0x18]; 10544 10545 u8 syndrome[0x20]; 10546 10547 u8 reserved_at_40[0x40]; 10548 }; 10549 10550 struct mlx5_ifc_set_wol_rol_in_bits { 10551 u8 opcode[0x10]; 10552 u8 reserved_at_10[0x10]; 10553 10554 u8 reserved_at_20[0x10]; 10555 u8 op_mod[0x10]; 10556 10557 u8 rol_mode_valid[0x1]; 10558 u8 wol_mode_valid[0x1]; 10559 u8 reserved_at_42[0xe]; 10560 u8 rol_mode[0x8]; 10561 u8 wol_mode[0x8]; 10562 10563 u8 reserved_at_60[0x20]; 10564 }; 10565 10566 enum { 10567 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10568 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10569 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10570 }; 10571 10572 enum { 10573 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10574 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10575 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10576 }; 10577 10578 enum { 10579 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10580 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10581 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10582 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10583 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10584 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10585 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10586 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10587 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10588 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10589 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10590 }; 10591 10592 struct mlx5_ifc_initial_seg_bits { 10593 u8 fw_rev_minor[0x10]; 10594 u8 fw_rev_major[0x10]; 10595 10596 u8 cmd_interface_rev[0x10]; 10597 u8 fw_rev_subminor[0x10]; 10598 10599 u8 reserved_at_40[0x40]; 10600 10601 u8 cmdq_phy_addr_63_32[0x20]; 10602 10603 u8 cmdq_phy_addr_31_12[0x14]; 10604 u8 reserved_at_b4[0x2]; 10605 u8 nic_interface[0x2]; 10606 u8 log_cmdq_size[0x4]; 10607 u8 log_cmdq_stride[0x4]; 10608 10609 u8 command_doorbell_vector[0x20]; 10610 10611 u8 reserved_at_e0[0xf00]; 10612 10613 u8 initializing[0x1]; 10614 u8 reserved_at_fe1[0x4]; 10615 u8 nic_interface_supported[0x3]; 10616 u8 embedded_cpu[0x1]; 10617 u8 reserved_at_fe9[0x17]; 10618 10619 struct mlx5_ifc_health_buffer_bits health_buffer; 10620 10621 u8 no_dram_nic_offset[0x20]; 10622 10623 u8 reserved_at_1220[0x6e40]; 10624 10625 u8 reserved_at_8060[0x1f]; 10626 u8 clear_int[0x1]; 10627 10628 u8 health_syndrome[0x8]; 10629 u8 health_counter[0x18]; 10630 10631 u8 reserved_at_80a0[0x17fc0]; 10632 }; 10633 10634 struct mlx5_ifc_mtpps_reg_bits { 10635 u8 reserved_at_0[0xc]; 10636 u8 cap_number_of_pps_pins[0x4]; 10637 u8 reserved_at_10[0x4]; 10638 u8 cap_max_num_of_pps_in_pins[0x4]; 10639 u8 reserved_at_18[0x4]; 10640 u8 cap_max_num_of_pps_out_pins[0x4]; 10641 10642 u8 reserved_at_20[0x13]; 10643 u8 cap_log_min_npps_period[0x5]; 10644 u8 reserved_at_38[0x3]; 10645 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10646 10647 u8 reserved_at_40[0x4]; 10648 u8 cap_pin_3_mode[0x4]; 10649 u8 reserved_at_48[0x4]; 10650 u8 cap_pin_2_mode[0x4]; 10651 u8 reserved_at_50[0x4]; 10652 u8 cap_pin_1_mode[0x4]; 10653 u8 reserved_at_58[0x4]; 10654 u8 cap_pin_0_mode[0x4]; 10655 10656 u8 reserved_at_60[0x4]; 10657 u8 cap_pin_7_mode[0x4]; 10658 u8 reserved_at_68[0x4]; 10659 u8 cap_pin_6_mode[0x4]; 10660 u8 reserved_at_70[0x4]; 10661 u8 cap_pin_5_mode[0x4]; 10662 u8 reserved_at_78[0x4]; 10663 u8 cap_pin_4_mode[0x4]; 10664 10665 u8 field_select[0x20]; 10666 u8 reserved_at_a0[0x20]; 10667 10668 u8 npps_period[0x40]; 10669 10670 u8 enable[0x1]; 10671 u8 reserved_at_101[0xb]; 10672 u8 pattern[0x4]; 10673 u8 reserved_at_110[0x4]; 10674 u8 pin_mode[0x4]; 10675 u8 pin[0x8]; 10676 10677 u8 reserved_at_120[0x2]; 10678 u8 out_pulse_duration_ns[0x1e]; 10679 10680 u8 time_stamp[0x40]; 10681 10682 u8 out_pulse_duration[0x10]; 10683 u8 out_periodic_adjustment[0x10]; 10684 u8 enhanced_out_periodic_adjustment[0x20]; 10685 10686 u8 reserved_at_1c0[0x20]; 10687 }; 10688 10689 struct mlx5_ifc_mtppse_reg_bits { 10690 u8 reserved_at_0[0x18]; 10691 u8 pin[0x8]; 10692 u8 event_arm[0x1]; 10693 u8 reserved_at_21[0x1b]; 10694 u8 event_generation_mode[0x4]; 10695 u8 reserved_at_40[0x40]; 10696 }; 10697 10698 struct mlx5_ifc_mcqs_reg_bits { 10699 u8 last_index_flag[0x1]; 10700 u8 reserved_at_1[0x7]; 10701 u8 fw_device[0x8]; 10702 u8 component_index[0x10]; 10703 10704 u8 reserved_at_20[0x10]; 10705 u8 identifier[0x10]; 10706 10707 u8 reserved_at_40[0x17]; 10708 u8 component_status[0x5]; 10709 u8 component_update_state[0x4]; 10710 10711 u8 last_update_state_changer_type[0x4]; 10712 u8 last_update_state_changer_host_id[0x4]; 10713 u8 reserved_at_68[0x18]; 10714 }; 10715 10716 struct mlx5_ifc_mcqi_cap_bits { 10717 u8 supported_info_bitmask[0x20]; 10718 10719 u8 component_size[0x20]; 10720 10721 u8 max_component_size[0x20]; 10722 10723 u8 log_mcda_word_size[0x4]; 10724 u8 reserved_at_64[0xc]; 10725 u8 mcda_max_write_size[0x10]; 10726 10727 u8 rd_en[0x1]; 10728 u8 reserved_at_81[0x1]; 10729 u8 match_chip_id[0x1]; 10730 u8 match_psid[0x1]; 10731 u8 check_user_timestamp[0x1]; 10732 u8 match_base_guid_mac[0x1]; 10733 u8 reserved_at_86[0x1a]; 10734 }; 10735 10736 struct mlx5_ifc_mcqi_version_bits { 10737 u8 reserved_at_0[0x2]; 10738 u8 build_time_valid[0x1]; 10739 u8 user_defined_time_valid[0x1]; 10740 u8 reserved_at_4[0x14]; 10741 u8 version_string_length[0x8]; 10742 10743 u8 version[0x20]; 10744 10745 u8 build_time[0x40]; 10746 10747 u8 user_defined_time[0x40]; 10748 10749 u8 build_tool_version[0x20]; 10750 10751 u8 reserved_at_e0[0x20]; 10752 10753 u8 version_string[92][0x8]; 10754 }; 10755 10756 struct mlx5_ifc_mcqi_activation_method_bits { 10757 u8 pending_server_ac_power_cycle[0x1]; 10758 u8 pending_server_dc_power_cycle[0x1]; 10759 u8 pending_server_reboot[0x1]; 10760 u8 pending_fw_reset[0x1]; 10761 u8 auto_activate[0x1]; 10762 u8 all_hosts_sync[0x1]; 10763 u8 device_hw_reset[0x1]; 10764 u8 reserved_at_7[0x19]; 10765 }; 10766 10767 union mlx5_ifc_mcqi_reg_data_bits { 10768 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10769 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10770 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10771 }; 10772 10773 struct mlx5_ifc_mcqi_reg_bits { 10774 u8 read_pending_component[0x1]; 10775 u8 reserved_at_1[0xf]; 10776 u8 component_index[0x10]; 10777 10778 u8 reserved_at_20[0x20]; 10779 10780 u8 reserved_at_40[0x1b]; 10781 u8 info_type[0x5]; 10782 10783 u8 info_size[0x20]; 10784 10785 u8 offset[0x20]; 10786 10787 u8 reserved_at_a0[0x10]; 10788 u8 data_size[0x10]; 10789 10790 union mlx5_ifc_mcqi_reg_data_bits data[]; 10791 }; 10792 10793 struct mlx5_ifc_mcc_reg_bits { 10794 u8 reserved_at_0[0x4]; 10795 u8 time_elapsed_since_last_cmd[0xc]; 10796 u8 reserved_at_10[0x8]; 10797 u8 instruction[0x8]; 10798 10799 u8 reserved_at_20[0x10]; 10800 u8 component_index[0x10]; 10801 10802 u8 reserved_at_40[0x8]; 10803 u8 update_handle[0x18]; 10804 10805 u8 handle_owner_type[0x4]; 10806 u8 handle_owner_host_id[0x4]; 10807 u8 reserved_at_68[0x1]; 10808 u8 control_progress[0x7]; 10809 u8 error_code[0x8]; 10810 u8 reserved_at_78[0x4]; 10811 u8 control_state[0x4]; 10812 10813 u8 component_size[0x20]; 10814 10815 u8 reserved_at_a0[0x60]; 10816 }; 10817 10818 struct mlx5_ifc_mcda_reg_bits { 10819 u8 reserved_at_0[0x8]; 10820 u8 update_handle[0x18]; 10821 10822 u8 offset[0x20]; 10823 10824 u8 reserved_at_40[0x10]; 10825 u8 size[0x10]; 10826 10827 u8 reserved_at_60[0x20]; 10828 10829 u8 data[][0x20]; 10830 }; 10831 10832 enum { 10833 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10834 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10835 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10836 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10837 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10838 }; 10839 10840 enum { 10841 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10842 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10843 }; 10844 10845 enum { 10846 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10847 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10848 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10849 }; 10850 10851 struct mlx5_ifc_mfrl_reg_bits { 10852 u8 reserved_at_0[0x20]; 10853 10854 u8 reserved_at_20[0x2]; 10855 u8 pci_sync_for_fw_update_start[0x1]; 10856 u8 pci_sync_for_fw_update_resp[0x2]; 10857 u8 rst_type_sel[0x3]; 10858 u8 reserved_at_28[0x4]; 10859 u8 reset_state[0x4]; 10860 u8 reset_type[0x8]; 10861 u8 reset_level[0x8]; 10862 }; 10863 10864 struct mlx5_ifc_mirc_reg_bits { 10865 u8 reserved_at_0[0x18]; 10866 u8 status_code[0x8]; 10867 10868 u8 reserved_at_20[0x20]; 10869 }; 10870 10871 struct mlx5_ifc_pddr_monitor_opcode_bits { 10872 u8 reserved_at_0[0x10]; 10873 u8 monitor_opcode[0x10]; 10874 }; 10875 10876 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10877 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10878 u8 reserved_at_0[0x20]; 10879 }; 10880 10881 enum { 10882 /* Monitor opcodes */ 10883 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10884 }; 10885 10886 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10887 u8 reserved_at_0[0x10]; 10888 u8 group_opcode[0x10]; 10889 10890 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10891 10892 u8 reserved_at_40[0x20]; 10893 10894 u8 status_message[59][0x20]; 10895 }; 10896 10897 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10898 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10899 u8 reserved_at_0[0x7c0]; 10900 }; 10901 10902 enum { 10903 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10904 }; 10905 10906 struct mlx5_ifc_pddr_reg_bits { 10907 u8 reserved_at_0[0x8]; 10908 u8 local_port[0x8]; 10909 u8 pnat[0x2]; 10910 u8 reserved_at_12[0xe]; 10911 10912 u8 reserved_at_20[0x18]; 10913 u8 page_select[0x8]; 10914 10915 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10916 }; 10917 10918 struct mlx5_ifc_mrtc_reg_bits { 10919 u8 time_synced[0x1]; 10920 u8 reserved_at_1[0x1f]; 10921 10922 u8 reserved_at_20[0x20]; 10923 10924 u8 time_h[0x20]; 10925 10926 u8 time_l[0x20]; 10927 }; 10928 10929 struct mlx5_ifc_mtmp_reg_bits { 10930 u8 reserved_at_0[0x14]; 10931 u8 sensor_index[0xc]; 10932 10933 u8 reserved_at_20[0x10]; 10934 u8 temperature[0x10]; 10935 10936 u8 mte[0x1]; 10937 u8 mtr[0x1]; 10938 u8 reserved_at_42[0xe]; 10939 u8 max_temperature[0x10]; 10940 10941 u8 tee[0x2]; 10942 u8 reserved_at_62[0xe]; 10943 u8 temp_threshold_hi[0x10]; 10944 10945 u8 reserved_at_80[0x10]; 10946 u8 temp_threshold_lo[0x10]; 10947 10948 u8 reserved_at_a0[0x20]; 10949 10950 u8 sensor_name_hi[0x20]; 10951 u8 sensor_name_lo[0x20]; 10952 }; 10953 10954 union mlx5_ifc_ports_control_registers_document_bits { 10955 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10956 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10957 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10958 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10959 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10960 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10961 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10962 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10963 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10964 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10965 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10966 struct mlx5_ifc_paos_reg_bits paos_reg; 10967 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10968 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10969 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10970 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10971 struct mlx5_ifc_peir_reg_bits peir_reg; 10972 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10973 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10974 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10975 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10976 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10977 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10978 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10979 struct mlx5_ifc_plib_reg_bits plib_reg; 10980 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10981 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10982 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10983 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10984 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10985 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10986 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10987 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10988 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10989 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10990 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10991 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10992 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10993 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10994 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10995 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10996 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10997 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10998 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10999 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11000 struct mlx5_ifc_pude_reg_bits pude_reg; 11001 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11002 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11003 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11004 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11005 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11006 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11007 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11008 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11009 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11010 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11011 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11012 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11013 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11014 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11015 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11016 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11017 u8 reserved_at_0[0x60e0]; 11018 }; 11019 11020 union mlx5_ifc_debug_enhancements_document_bits { 11021 struct mlx5_ifc_health_buffer_bits health_buffer; 11022 u8 reserved_at_0[0x200]; 11023 }; 11024 11025 union mlx5_ifc_uplink_pci_interface_document_bits { 11026 struct mlx5_ifc_initial_seg_bits initial_seg; 11027 u8 reserved_at_0[0x20060]; 11028 }; 11029 11030 struct mlx5_ifc_set_flow_table_root_out_bits { 11031 u8 status[0x8]; 11032 u8 reserved_at_8[0x18]; 11033 11034 u8 syndrome[0x20]; 11035 11036 u8 reserved_at_40[0x40]; 11037 }; 11038 11039 struct mlx5_ifc_set_flow_table_root_in_bits { 11040 u8 opcode[0x10]; 11041 u8 reserved_at_10[0x10]; 11042 11043 u8 reserved_at_20[0x10]; 11044 u8 op_mod[0x10]; 11045 11046 u8 other_vport[0x1]; 11047 u8 reserved_at_41[0xf]; 11048 u8 vport_number[0x10]; 11049 11050 u8 reserved_at_60[0x20]; 11051 11052 u8 table_type[0x8]; 11053 u8 reserved_at_88[0x7]; 11054 u8 table_of_other_vport[0x1]; 11055 u8 table_vport_number[0x10]; 11056 11057 u8 reserved_at_a0[0x8]; 11058 u8 table_id[0x18]; 11059 11060 u8 reserved_at_c0[0x8]; 11061 u8 underlay_qpn[0x18]; 11062 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11063 u8 reserved_at_e1[0xf]; 11064 u8 table_eswitch_owner_vhca_id[0x10]; 11065 u8 reserved_at_100[0x100]; 11066 }; 11067 11068 enum { 11069 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11070 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11071 }; 11072 11073 struct mlx5_ifc_modify_flow_table_out_bits { 11074 u8 status[0x8]; 11075 u8 reserved_at_8[0x18]; 11076 11077 u8 syndrome[0x20]; 11078 11079 u8 reserved_at_40[0x40]; 11080 }; 11081 11082 struct mlx5_ifc_modify_flow_table_in_bits { 11083 u8 opcode[0x10]; 11084 u8 reserved_at_10[0x10]; 11085 11086 u8 reserved_at_20[0x10]; 11087 u8 op_mod[0x10]; 11088 11089 u8 other_vport[0x1]; 11090 u8 reserved_at_41[0xf]; 11091 u8 vport_number[0x10]; 11092 11093 u8 reserved_at_60[0x10]; 11094 u8 modify_field_select[0x10]; 11095 11096 u8 table_type[0x8]; 11097 u8 reserved_at_88[0x18]; 11098 11099 u8 reserved_at_a0[0x8]; 11100 u8 table_id[0x18]; 11101 11102 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11103 }; 11104 11105 struct mlx5_ifc_ets_tcn_config_reg_bits { 11106 u8 g[0x1]; 11107 u8 b[0x1]; 11108 u8 r[0x1]; 11109 u8 reserved_at_3[0x9]; 11110 u8 group[0x4]; 11111 u8 reserved_at_10[0x9]; 11112 u8 bw_allocation[0x7]; 11113 11114 u8 reserved_at_20[0xc]; 11115 u8 max_bw_units[0x4]; 11116 u8 reserved_at_30[0x8]; 11117 u8 max_bw_value[0x8]; 11118 }; 11119 11120 struct mlx5_ifc_ets_global_config_reg_bits { 11121 u8 reserved_at_0[0x2]; 11122 u8 r[0x1]; 11123 u8 reserved_at_3[0x1d]; 11124 11125 u8 reserved_at_20[0xc]; 11126 u8 max_bw_units[0x4]; 11127 u8 reserved_at_30[0x8]; 11128 u8 max_bw_value[0x8]; 11129 }; 11130 11131 struct mlx5_ifc_qetc_reg_bits { 11132 u8 reserved_at_0[0x8]; 11133 u8 port_number[0x8]; 11134 u8 reserved_at_10[0x30]; 11135 11136 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11137 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11138 }; 11139 11140 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11141 u8 e[0x1]; 11142 u8 reserved_at_01[0x0b]; 11143 u8 prio[0x04]; 11144 }; 11145 11146 struct mlx5_ifc_qpdpm_reg_bits { 11147 u8 reserved_at_0[0x8]; 11148 u8 local_port[0x8]; 11149 u8 reserved_at_10[0x10]; 11150 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11151 }; 11152 11153 struct mlx5_ifc_qpts_reg_bits { 11154 u8 reserved_at_0[0x8]; 11155 u8 local_port[0x8]; 11156 u8 reserved_at_10[0x2d]; 11157 u8 trust_state[0x3]; 11158 }; 11159 11160 struct mlx5_ifc_pptb_reg_bits { 11161 u8 reserved_at_0[0x2]; 11162 u8 mm[0x2]; 11163 u8 reserved_at_4[0x4]; 11164 u8 local_port[0x8]; 11165 u8 reserved_at_10[0x6]; 11166 u8 cm[0x1]; 11167 u8 um[0x1]; 11168 u8 pm[0x8]; 11169 11170 u8 prio_x_buff[0x20]; 11171 11172 u8 pm_msb[0x8]; 11173 u8 reserved_at_48[0x10]; 11174 u8 ctrl_buff[0x4]; 11175 u8 untagged_buff[0x4]; 11176 }; 11177 11178 struct mlx5_ifc_sbcam_reg_bits { 11179 u8 reserved_at_0[0x8]; 11180 u8 feature_group[0x8]; 11181 u8 reserved_at_10[0x8]; 11182 u8 access_reg_group[0x8]; 11183 11184 u8 reserved_at_20[0x20]; 11185 11186 u8 sb_access_reg_cap_mask[4][0x20]; 11187 11188 u8 reserved_at_c0[0x80]; 11189 11190 u8 sb_feature_cap_mask[4][0x20]; 11191 11192 u8 reserved_at_1c0[0x40]; 11193 11194 u8 cap_total_buffer_size[0x20]; 11195 11196 u8 cap_cell_size[0x10]; 11197 u8 cap_max_pg_buffers[0x8]; 11198 u8 cap_num_pool_supported[0x8]; 11199 11200 u8 reserved_at_240[0x8]; 11201 u8 cap_sbsr_stat_size[0x8]; 11202 u8 cap_max_tclass_data[0x8]; 11203 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11204 }; 11205 11206 struct mlx5_ifc_pbmc_reg_bits { 11207 u8 reserved_at_0[0x8]; 11208 u8 local_port[0x8]; 11209 u8 reserved_at_10[0x10]; 11210 11211 u8 xoff_timer_value[0x10]; 11212 u8 xoff_refresh[0x10]; 11213 11214 u8 reserved_at_40[0x9]; 11215 u8 fullness_threshold[0x7]; 11216 u8 port_buffer_size[0x10]; 11217 11218 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11219 11220 u8 reserved_at_2e0[0x80]; 11221 }; 11222 11223 struct mlx5_ifc_sbpr_reg_bits { 11224 u8 desc[0x1]; 11225 u8 snap[0x1]; 11226 u8 reserved_at_2[0x4]; 11227 u8 dir[0x2]; 11228 u8 reserved_at_8[0x14]; 11229 u8 pool[0x4]; 11230 11231 u8 infi_size[0x1]; 11232 u8 reserved_at_21[0x7]; 11233 u8 size[0x18]; 11234 11235 u8 reserved_at_40[0x1c]; 11236 u8 mode[0x4]; 11237 11238 u8 reserved_at_60[0x8]; 11239 u8 buff_occupancy[0x18]; 11240 11241 u8 clr[0x1]; 11242 u8 reserved_at_81[0x7]; 11243 u8 max_buff_occupancy[0x18]; 11244 11245 u8 reserved_at_a0[0x8]; 11246 u8 ext_buff_occupancy[0x18]; 11247 }; 11248 11249 struct mlx5_ifc_sbcm_reg_bits { 11250 u8 desc[0x1]; 11251 u8 snap[0x1]; 11252 u8 reserved_at_2[0x6]; 11253 u8 local_port[0x8]; 11254 u8 pnat[0x2]; 11255 u8 pg_buff[0x6]; 11256 u8 reserved_at_18[0x6]; 11257 u8 dir[0x2]; 11258 11259 u8 reserved_at_20[0x1f]; 11260 u8 exc[0x1]; 11261 11262 u8 reserved_at_40[0x40]; 11263 11264 u8 reserved_at_80[0x8]; 11265 u8 buff_occupancy[0x18]; 11266 11267 u8 clr[0x1]; 11268 u8 reserved_at_a1[0x7]; 11269 u8 max_buff_occupancy[0x18]; 11270 11271 u8 reserved_at_c0[0x8]; 11272 u8 min_buff[0x18]; 11273 11274 u8 infi_max[0x1]; 11275 u8 reserved_at_e1[0x7]; 11276 u8 max_buff[0x18]; 11277 11278 u8 reserved_at_100[0x20]; 11279 11280 u8 reserved_at_120[0x1c]; 11281 u8 pool[0x4]; 11282 }; 11283 11284 struct mlx5_ifc_qtct_reg_bits { 11285 u8 reserved_at_0[0x8]; 11286 u8 port_number[0x8]; 11287 u8 reserved_at_10[0xd]; 11288 u8 prio[0x3]; 11289 11290 u8 reserved_at_20[0x1d]; 11291 u8 tclass[0x3]; 11292 }; 11293 11294 struct mlx5_ifc_mcia_reg_bits { 11295 u8 l[0x1]; 11296 u8 reserved_at_1[0x7]; 11297 u8 module[0x8]; 11298 u8 reserved_at_10[0x8]; 11299 u8 status[0x8]; 11300 11301 u8 i2c_device_address[0x8]; 11302 u8 page_number[0x8]; 11303 u8 device_address[0x10]; 11304 11305 u8 reserved_at_40[0x10]; 11306 u8 size[0x10]; 11307 11308 u8 reserved_at_60[0x20]; 11309 11310 u8 dword_0[0x20]; 11311 u8 dword_1[0x20]; 11312 u8 dword_2[0x20]; 11313 u8 dword_3[0x20]; 11314 u8 dword_4[0x20]; 11315 u8 dword_5[0x20]; 11316 u8 dword_6[0x20]; 11317 u8 dword_7[0x20]; 11318 u8 dword_8[0x20]; 11319 u8 dword_9[0x20]; 11320 u8 dword_10[0x20]; 11321 u8 dword_11[0x20]; 11322 }; 11323 11324 struct mlx5_ifc_dcbx_param_bits { 11325 u8 dcbx_cee_cap[0x1]; 11326 u8 dcbx_ieee_cap[0x1]; 11327 u8 dcbx_standby_cap[0x1]; 11328 u8 reserved_at_3[0x5]; 11329 u8 port_number[0x8]; 11330 u8 reserved_at_10[0xa]; 11331 u8 max_application_table_size[6]; 11332 u8 reserved_at_20[0x15]; 11333 u8 version_oper[0x3]; 11334 u8 reserved_at_38[5]; 11335 u8 version_admin[0x3]; 11336 u8 willing_admin[0x1]; 11337 u8 reserved_at_41[0x3]; 11338 u8 pfc_cap_oper[0x4]; 11339 u8 reserved_at_48[0x4]; 11340 u8 pfc_cap_admin[0x4]; 11341 u8 reserved_at_50[0x4]; 11342 u8 num_of_tc_oper[0x4]; 11343 u8 reserved_at_58[0x4]; 11344 u8 num_of_tc_admin[0x4]; 11345 u8 remote_willing[0x1]; 11346 u8 reserved_at_61[3]; 11347 u8 remote_pfc_cap[4]; 11348 u8 reserved_at_68[0x14]; 11349 u8 remote_num_of_tc[0x4]; 11350 u8 reserved_at_80[0x18]; 11351 u8 error[0x8]; 11352 u8 reserved_at_a0[0x160]; 11353 }; 11354 11355 enum { 11356 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11357 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11358 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11359 }; 11360 11361 struct mlx5_ifc_lagc_bits { 11362 u8 fdb_selection_mode[0x1]; 11363 u8 reserved_at_1[0x14]; 11364 u8 port_select_mode[0x3]; 11365 u8 reserved_at_18[0x5]; 11366 u8 lag_state[0x3]; 11367 11368 u8 reserved_at_20[0xc]; 11369 u8 active_port[0x4]; 11370 u8 reserved_at_30[0x4]; 11371 u8 tx_remap_affinity_2[0x4]; 11372 u8 reserved_at_38[0x4]; 11373 u8 tx_remap_affinity_1[0x4]; 11374 }; 11375 11376 struct mlx5_ifc_create_lag_out_bits { 11377 u8 status[0x8]; 11378 u8 reserved_at_8[0x18]; 11379 11380 u8 syndrome[0x20]; 11381 11382 u8 reserved_at_40[0x40]; 11383 }; 11384 11385 struct mlx5_ifc_create_lag_in_bits { 11386 u8 opcode[0x10]; 11387 u8 reserved_at_10[0x10]; 11388 11389 u8 reserved_at_20[0x10]; 11390 u8 op_mod[0x10]; 11391 11392 struct mlx5_ifc_lagc_bits ctx; 11393 }; 11394 11395 struct mlx5_ifc_modify_lag_out_bits { 11396 u8 status[0x8]; 11397 u8 reserved_at_8[0x18]; 11398 11399 u8 syndrome[0x20]; 11400 11401 u8 reserved_at_40[0x40]; 11402 }; 11403 11404 struct mlx5_ifc_modify_lag_in_bits { 11405 u8 opcode[0x10]; 11406 u8 reserved_at_10[0x10]; 11407 11408 u8 reserved_at_20[0x10]; 11409 u8 op_mod[0x10]; 11410 11411 u8 reserved_at_40[0x20]; 11412 u8 field_select[0x20]; 11413 11414 struct mlx5_ifc_lagc_bits ctx; 11415 }; 11416 11417 struct mlx5_ifc_query_lag_out_bits { 11418 u8 status[0x8]; 11419 u8 reserved_at_8[0x18]; 11420 11421 u8 syndrome[0x20]; 11422 11423 struct mlx5_ifc_lagc_bits ctx; 11424 }; 11425 11426 struct mlx5_ifc_query_lag_in_bits { 11427 u8 opcode[0x10]; 11428 u8 reserved_at_10[0x10]; 11429 11430 u8 reserved_at_20[0x10]; 11431 u8 op_mod[0x10]; 11432 11433 u8 reserved_at_40[0x40]; 11434 }; 11435 11436 struct mlx5_ifc_destroy_lag_out_bits { 11437 u8 status[0x8]; 11438 u8 reserved_at_8[0x18]; 11439 11440 u8 syndrome[0x20]; 11441 11442 u8 reserved_at_40[0x40]; 11443 }; 11444 11445 struct mlx5_ifc_destroy_lag_in_bits { 11446 u8 opcode[0x10]; 11447 u8 reserved_at_10[0x10]; 11448 11449 u8 reserved_at_20[0x10]; 11450 u8 op_mod[0x10]; 11451 11452 u8 reserved_at_40[0x40]; 11453 }; 11454 11455 struct mlx5_ifc_create_vport_lag_out_bits { 11456 u8 status[0x8]; 11457 u8 reserved_at_8[0x18]; 11458 11459 u8 syndrome[0x20]; 11460 11461 u8 reserved_at_40[0x40]; 11462 }; 11463 11464 struct mlx5_ifc_create_vport_lag_in_bits { 11465 u8 opcode[0x10]; 11466 u8 reserved_at_10[0x10]; 11467 11468 u8 reserved_at_20[0x10]; 11469 u8 op_mod[0x10]; 11470 11471 u8 reserved_at_40[0x40]; 11472 }; 11473 11474 struct mlx5_ifc_destroy_vport_lag_out_bits { 11475 u8 status[0x8]; 11476 u8 reserved_at_8[0x18]; 11477 11478 u8 syndrome[0x20]; 11479 11480 u8 reserved_at_40[0x40]; 11481 }; 11482 11483 struct mlx5_ifc_destroy_vport_lag_in_bits { 11484 u8 opcode[0x10]; 11485 u8 reserved_at_10[0x10]; 11486 11487 u8 reserved_at_20[0x10]; 11488 u8 op_mod[0x10]; 11489 11490 u8 reserved_at_40[0x40]; 11491 }; 11492 11493 enum { 11494 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11495 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11496 }; 11497 11498 struct mlx5_ifc_modify_memic_in_bits { 11499 u8 opcode[0x10]; 11500 u8 uid[0x10]; 11501 11502 u8 reserved_at_20[0x10]; 11503 u8 op_mod[0x10]; 11504 11505 u8 reserved_at_40[0x20]; 11506 11507 u8 reserved_at_60[0x18]; 11508 u8 memic_operation_type[0x8]; 11509 11510 u8 memic_start_addr[0x40]; 11511 11512 u8 reserved_at_c0[0x140]; 11513 }; 11514 11515 struct mlx5_ifc_modify_memic_out_bits { 11516 u8 status[0x8]; 11517 u8 reserved_at_8[0x18]; 11518 11519 u8 syndrome[0x20]; 11520 11521 u8 reserved_at_40[0x40]; 11522 11523 u8 memic_operation_addr[0x40]; 11524 11525 u8 reserved_at_c0[0x140]; 11526 }; 11527 11528 struct mlx5_ifc_alloc_memic_in_bits { 11529 u8 opcode[0x10]; 11530 u8 reserved_at_10[0x10]; 11531 11532 u8 reserved_at_20[0x10]; 11533 u8 op_mod[0x10]; 11534 11535 u8 reserved_at_30[0x20]; 11536 11537 u8 reserved_at_40[0x18]; 11538 u8 log_memic_addr_alignment[0x8]; 11539 11540 u8 range_start_addr[0x40]; 11541 11542 u8 range_size[0x20]; 11543 11544 u8 memic_size[0x20]; 11545 }; 11546 11547 struct mlx5_ifc_alloc_memic_out_bits { 11548 u8 status[0x8]; 11549 u8 reserved_at_8[0x18]; 11550 11551 u8 syndrome[0x20]; 11552 11553 u8 memic_start_addr[0x40]; 11554 }; 11555 11556 struct mlx5_ifc_dealloc_memic_in_bits { 11557 u8 opcode[0x10]; 11558 u8 reserved_at_10[0x10]; 11559 11560 u8 reserved_at_20[0x10]; 11561 u8 op_mod[0x10]; 11562 11563 u8 reserved_at_40[0x40]; 11564 11565 u8 memic_start_addr[0x40]; 11566 11567 u8 memic_size[0x20]; 11568 11569 u8 reserved_at_e0[0x20]; 11570 }; 11571 11572 struct mlx5_ifc_dealloc_memic_out_bits { 11573 u8 status[0x8]; 11574 u8 reserved_at_8[0x18]; 11575 11576 u8 syndrome[0x20]; 11577 11578 u8 reserved_at_40[0x40]; 11579 }; 11580 11581 struct mlx5_ifc_umem_bits { 11582 u8 reserved_at_0[0x80]; 11583 11584 u8 ats[0x1]; 11585 u8 reserved_at_81[0x1a]; 11586 u8 log_page_size[0x5]; 11587 11588 u8 page_offset[0x20]; 11589 11590 u8 num_of_mtt[0x40]; 11591 11592 struct mlx5_ifc_mtt_bits mtt[]; 11593 }; 11594 11595 struct mlx5_ifc_uctx_bits { 11596 u8 cap[0x20]; 11597 11598 u8 reserved_at_20[0x160]; 11599 }; 11600 11601 struct mlx5_ifc_sw_icm_bits { 11602 u8 modify_field_select[0x40]; 11603 11604 u8 reserved_at_40[0x18]; 11605 u8 log_sw_icm_size[0x8]; 11606 11607 u8 reserved_at_60[0x20]; 11608 11609 u8 sw_icm_start_addr[0x40]; 11610 11611 u8 reserved_at_c0[0x140]; 11612 }; 11613 11614 struct mlx5_ifc_geneve_tlv_option_bits { 11615 u8 modify_field_select[0x40]; 11616 11617 u8 reserved_at_40[0x18]; 11618 u8 geneve_option_fte_index[0x8]; 11619 11620 u8 option_class[0x10]; 11621 u8 option_type[0x8]; 11622 u8 reserved_at_78[0x3]; 11623 u8 option_data_length[0x5]; 11624 11625 u8 reserved_at_80[0x180]; 11626 }; 11627 11628 struct mlx5_ifc_create_umem_in_bits { 11629 u8 opcode[0x10]; 11630 u8 uid[0x10]; 11631 11632 u8 reserved_at_20[0x10]; 11633 u8 op_mod[0x10]; 11634 11635 u8 reserved_at_40[0x40]; 11636 11637 struct mlx5_ifc_umem_bits umem; 11638 }; 11639 11640 struct mlx5_ifc_create_umem_out_bits { 11641 u8 status[0x8]; 11642 u8 reserved_at_8[0x18]; 11643 11644 u8 syndrome[0x20]; 11645 11646 u8 reserved_at_40[0x8]; 11647 u8 umem_id[0x18]; 11648 11649 u8 reserved_at_60[0x20]; 11650 }; 11651 11652 struct mlx5_ifc_destroy_umem_in_bits { 11653 u8 opcode[0x10]; 11654 u8 uid[0x10]; 11655 11656 u8 reserved_at_20[0x10]; 11657 u8 op_mod[0x10]; 11658 11659 u8 reserved_at_40[0x8]; 11660 u8 umem_id[0x18]; 11661 11662 u8 reserved_at_60[0x20]; 11663 }; 11664 11665 struct mlx5_ifc_destroy_umem_out_bits { 11666 u8 status[0x8]; 11667 u8 reserved_at_8[0x18]; 11668 11669 u8 syndrome[0x20]; 11670 11671 u8 reserved_at_40[0x40]; 11672 }; 11673 11674 struct mlx5_ifc_create_uctx_in_bits { 11675 u8 opcode[0x10]; 11676 u8 reserved_at_10[0x10]; 11677 11678 u8 reserved_at_20[0x10]; 11679 u8 op_mod[0x10]; 11680 11681 u8 reserved_at_40[0x40]; 11682 11683 struct mlx5_ifc_uctx_bits uctx; 11684 }; 11685 11686 struct mlx5_ifc_create_uctx_out_bits { 11687 u8 status[0x8]; 11688 u8 reserved_at_8[0x18]; 11689 11690 u8 syndrome[0x20]; 11691 11692 u8 reserved_at_40[0x10]; 11693 u8 uid[0x10]; 11694 11695 u8 reserved_at_60[0x20]; 11696 }; 11697 11698 struct mlx5_ifc_destroy_uctx_in_bits { 11699 u8 opcode[0x10]; 11700 u8 reserved_at_10[0x10]; 11701 11702 u8 reserved_at_20[0x10]; 11703 u8 op_mod[0x10]; 11704 11705 u8 reserved_at_40[0x10]; 11706 u8 uid[0x10]; 11707 11708 u8 reserved_at_60[0x20]; 11709 }; 11710 11711 struct mlx5_ifc_destroy_uctx_out_bits { 11712 u8 status[0x8]; 11713 u8 reserved_at_8[0x18]; 11714 11715 u8 syndrome[0x20]; 11716 11717 u8 reserved_at_40[0x40]; 11718 }; 11719 11720 struct mlx5_ifc_create_sw_icm_in_bits { 11721 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11722 struct mlx5_ifc_sw_icm_bits sw_icm; 11723 }; 11724 11725 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11726 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11727 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11728 }; 11729 11730 struct mlx5_ifc_mtrc_string_db_param_bits { 11731 u8 string_db_base_address[0x20]; 11732 11733 u8 reserved_at_20[0x8]; 11734 u8 string_db_size[0x18]; 11735 }; 11736 11737 struct mlx5_ifc_mtrc_cap_bits { 11738 u8 trace_owner[0x1]; 11739 u8 trace_to_memory[0x1]; 11740 u8 reserved_at_2[0x4]; 11741 u8 trc_ver[0x2]; 11742 u8 reserved_at_8[0x14]; 11743 u8 num_string_db[0x4]; 11744 11745 u8 first_string_trace[0x8]; 11746 u8 num_string_trace[0x8]; 11747 u8 reserved_at_30[0x28]; 11748 11749 u8 log_max_trace_buffer_size[0x8]; 11750 11751 u8 reserved_at_60[0x20]; 11752 11753 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11754 11755 u8 reserved_at_280[0x180]; 11756 }; 11757 11758 struct mlx5_ifc_mtrc_conf_bits { 11759 u8 reserved_at_0[0x1c]; 11760 u8 trace_mode[0x4]; 11761 u8 reserved_at_20[0x18]; 11762 u8 log_trace_buffer_size[0x8]; 11763 u8 trace_mkey[0x20]; 11764 u8 reserved_at_60[0x3a0]; 11765 }; 11766 11767 struct mlx5_ifc_mtrc_stdb_bits { 11768 u8 string_db_index[0x4]; 11769 u8 reserved_at_4[0x4]; 11770 u8 read_size[0x18]; 11771 u8 start_offset[0x20]; 11772 u8 string_db_data[]; 11773 }; 11774 11775 struct mlx5_ifc_mtrc_ctrl_bits { 11776 u8 trace_status[0x2]; 11777 u8 reserved_at_2[0x2]; 11778 u8 arm_event[0x1]; 11779 u8 reserved_at_5[0xb]; 11780 u8 modify_field_select[0x10]; 11781 u8 reserved_at_20[0x2b]; 11782 u8 current_timestamp52_32[0x15]; 11783 u8 current_timestamp31_0[0x20]; 11784 u8 reserved_at_80[0x180]; 11785 }; 11786 11787 struct mlx5_ifc_host_params_context_bits { 11788 u8 host_number[0x8]; 11789 u8 reserved_at_8[0x7]; 11790 u8 host_pf_disabled[0x1]; 11791 u8 host_num_of_vfs[0x10]; 11792 11793 u8 host_total_vfs[0x10]; 11794 u8 host_pci_bus[0x10]; 11795 11796 u8 reserved_at_40[0x10]; 11797 u8 host_pci_device[0x10]; 11798 11799 u8 reserved_at_60[0x10]; 11800 u8 host_pci_function[0x10]; 11801 11802 u8 reserved_at_80[0x180]; 11803 }; 11804 11805 struct mlx5_ifc_query_esw_functions_in_bits { 11806 u8 opcode[0x10]; 11807 u8 reserved_at_10[0x10]; 11808 11809 u8 reserved_at_20[0x10]; 11810 u8 op_mod[0x10]; 11811 11812 u8 reserved_at_40[0x40]; 11813 }; 11814 11815 struct mlx5_ifc_query_esw_functions_out_bits { 11816 u8 status[0x8]; 11817 u8 reserved_at_8[0x18]; 11818 11819 u8 syndrome[0x20]; 11820 11821 u8 reserved_at_40[0x40]; 11822 11823 struct mlx5_ifc_host_params_context_bits host_params_context; 11824 11825 u8 reserved_at_280[0x180]; 11826 u8 host_sf_enable[][0x40]; 11827 }; 11828 11829 struct mlx5_ifc_sf_partition_bits { 11830 u8 reserved_at_0[0x10]; 11831 u8 log_num_sf[0x8]; 11832 u8 log_sf_bar_size[0x8]; 11833 }; 11834 11835 struct mlx5_ifc_query_sf_partitions_out_bits { 11836 u8 status[0x8]; 11837 u8 reserved_at_8[0x18]; 11838 11839 u8 syndrome[0x20]; 11840 11841 u8 reserved_at_40[0x18]; 11842 u8 num_sf_partitions[0x8]; 11843 11844 u8 reserved_at_60[0x20]; 11845 11846 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11847 }; 11848 11849 struct mlx5_ifc_query_sf_partitions_in_bits { 11850 u8 opcode[0x10]; 11851 u8 reserved_at_10[0x10]; 11852 11853 u8 reserved_at_20[0x10]; 11854 u8 op_mod[0x10]; 11855 11856 u8 reserved_at_40[0x40]; 11857 }; 11858 11859 struct mlx5_ifc_dealloc_sf_out_bits { 11860 u8 status[0x8]; 11861 u8 reserved_at_8[0x18]; 11862 11863 u8 syndrome[0x20]; 11864 11865 u8 reserved_at_40[0x40]; 11866 }; 11867 11868 struct mlx5_ifc_dealloc_sf_in_bits { 11869 u8 opcode[0x10]; 11870 u8 reserved_at_10[0x10]; 11871 11872 u8 reserved_at_20[0x10]; 11873 u8 op_mod[0x10]; 11874 11875 u8 reserved_at_40[0x10]; 11876 u8 function_id[0x10]; 11877 11878 u8 reserved_at_60[0x20]; 11879 }; 11880 11881 struct mlx5_ifc_alloc_sf_out_bits { 11882 u8 status[0x8]; 11883 u8 reserved_at_8[0x18]; 11884 11885 u8 syndrome[0x20]; 11886 11887 u8 reserved_at_40[0x40]; 11888 }; 11889 11890 struct mlx5_ifc_alloc_sf_in_bits { 11891 u8 opcode[0x10]; 11892 u8 reserved_at_10[0x10]; 11893 11894 u8 reserved_at_20[0x10]; 11895 u8 op_mod[0x10]; 11896 11897 u8 reserved_at_40[0x10]; 11898 u8 function_id[0x10]; 11899 11900 u8 reserved_at_60[0x20]; 11901 }; 11902 11903 struct mlx5_ifc_affiliated_event_header_bits { 11904 u8 reserved_at_0[0x10]; 11905 u8 obj_type[0x10]; 11906 11907 u8 obj_id[0x20]; 11908 }; 11909 11910 enum { 11911 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11912 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11913 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11914 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11915 }; 11916 11917 enum { 11918 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11919 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11920 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11921 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11922 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11923 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11924 }; 11925 11926 enum { 11927 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11928 }; 11929 11930 enum { 11931 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11932 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11933 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11934 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11935 }; 11936 11937 enum { 11938 MLX5_IPSEC_ASO_MODE = 0x0, 11939 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11940 MLX5_IPSEC_ASO_INC_SN = 0x2, 11941 }; 11942 11943 struct mlx5_ifc_ipsec_aso_bits { 11944 u8 valid[0x1]; 11945 u8 reserved_at_201[0x1]; 11946 u8 mode[0x2]; 11947 u8 window_sz[0x2]; 11948 u8 soft_lft_arm[0x1]; 11949 u8 hard_lft_arm[0x1]; 11950 u8 remove_flow_enable[0x1]; 11951 u8 esn_event_arm[0x1]; 11952 u8 reserved_at_20a[0x16]; 11953 11954 u8 remove_flow_pkt_cnt[0x20]; 11955 11956 u8 remove_flow_soft_lft[0x20]; 11957 11958 u8 reserved_at_260[0x80]; 11959 11960 u8 mode_parameter[0x20]; 11961 11962 u8 replay_protection_window[0x100]; 11963 }; 11964 11965 struct mlx5_ifc_ipsec_obj_bits { 11966 u8 modify_field_select[0x40]; 11967 u8 full_offload[0x1]; 11968 u8 reserved_at_41[0x1]; 11969 u8 esn_en[0x1]; 11970 u8 esn_overlap[0x1]; 11971 u8 reserved_at_44[0x2]; 11972 u8 icv_length[0x2]; 11973 u8 reserved_at_48[0x4]; 11974 u8 aso_return_reg[0x4]; 11975 u8 reserved_at_50[0x10]; 11976 11977 u8 esn_msb[0x20]; 11978 11979 u8 reserved_at_80[0x8]; 11980 u8 dekn[0x18]; 11981 11982 u8 salt[0x20]; 11983 11984 u8 implicit_iv[0x40]; 11985 11986 u8 reserved_at_100[0x8]; 11987 u8 ipsec_aso_access_pd[0x18]; 11988 u8 reserved_at_120[0xe0]; 11989 11990 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11991 }; 11992 11993 struct mlx5_ifc_create_ipsec_obj_in_bits { 11994 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11995 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11996 }; 11997 11998 enum { 11999 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12000 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12001 }; 12002 12003 struct mlx5_ifc_query_ipsec_obj_out_bits { 12004 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12005 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12006 }; 12007 12008 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12009 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12010 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12011 }; 12012 12013 enum { 12014 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12015 }; 12016 12017 enum { 12018 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12019 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12020 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12021 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12022 }; 12023 12024 #define MLX5_MACSEC_ASO_INC_SN 0x2 12025 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12026 12027 struct mlx5_ifc_macsec_aso_bits { 12028 u8 valid[0x1]; 12029 u8 reserved_at_1[0x1]; 12030 u8 mode[0x2]; 12031 u8 window_size[0x2]; 12032 u8 soft_lifetime_arm[0x1]; 12033 u8 hard_lifetime_arm[0x1]; 12034 u8 remove_flow_enable[0x1]; 12035 u8 epn_event_arm[0x1]; 12036 u8 reserved_at_a[0x16]; 12037 12038 u8 remove_flow_packet_count[0x20]; 12039 12040 u8 remove_flow_soft_lifetime[0x20]; 12041 12042 u8 reserved_at_60[0x80]; 12043 12044 u8 mode_parameter[0x20]; 12045 12046 u8 replay_protection_window[8][0x20]; 12047 }; 12048 12049 struct mlx5_ifc_macsec_offload_obj_bits { 12050 u8 modify_field_select[0x40]; 12051 12052 u8 confidentiality_en[0x1]; 12053 u8 reserved_at_41[0x1]; 12054 u8 epn_en[0x1]; 12055 u8 epn_overlap[0x1]; 12056 u8 reserved_at_44[0x2]; 12057 u8 confidentiality_offset[0x2]; 12058 u8 reserved_at_48[0x4]; 12059 u8 aso_return_reg[0x4]; 12060 u8 reserved_at_50[0x10]; 12061 12062 u8 epn_msb[0x20]; 12063 12064 u8 reserved_at_80[0x8]; 12065 u8 dekn[0x18]; 12066 12067 u8 reserved_at_a0[0x20]; 12068 12069 u8 sci[0x40]; 12070 12071 u8 reserved_at_100[0x8]; 12072 u8 macsec_aso_access_pd[0x18]; 12073 12074 u8 reserved_at_120[0x60]; 12075 12076 u8 salt[3][0x20]; 12077 12078 u8 reserved_at_1e0[0x20]; 12079 12080 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12081 }; 12082 12083 struct mlx5_ifc_create_macsec_obj_in_bits { 12084 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12085 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12086 }; 12087 12088 struct mlx5_ifc_modify_macsec_obj_in_bits { 12089 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12090 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12091 }; 12092 12093 enum { 12094 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12095 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12096 }; 12097 12098 struct mlx5_ifc_query_macsec_obj_out_bits { 12099 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12100 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12101 }; 12102 12103 struct mlx5_ifc_wrapped_dek_bits { 12104 u8 gcm_iv[0x60]; 12105 12106 u8 reserved_at_60[0x20]; 12107 12108 u8 const0[0x1]; 12109 u8 key_size[0x1]; 12110 u8 reserved_at_82[0x2]; 12111 u8 key2_invalid[0x1]; 12112 u8 reserved_at_85[0x3]; 12113 u8 pd[0x18]; 12114 12115 u8 key_purpose[0x5]; 12116 u8 reserved_at_a5[0x13]; 12117 u8 kek_id[0x8]; 12118 12119 u8 reserved_at_c0[0x40]; 12120 12121 u8 key1[0x8][0x20]; 12122 12123 u8 key2[0x8][0x20]; 12124 12125 u8 reserved_at_300[0x40]; 12126 12127 u8 const1[0x1]; 12128 u8 reserved_at_341[0x1f]; 12129 12130 u8 reserved_at_360[0x20]; 12131 12132 u8 auth_tag[0x80]; 12133 }; 12134 12135 struct mlx5_ifc_encryption_key_obj_bits { 12136 u8 modify_field_select[0x40]; 12137 12138 u8 state[0x8]; 12139 u8 sw_wrapped[0x1]; 12140 u8 reserved_at_49[0xb]; 12141 u8 key_size[0x4]; 12142 u8 reserved_at_58[0x4]; 12143 u8 key_purpose[0x4]; 12144 12145 u8 reserved_at_60[0x8]; 12146 u8 pd[0x18]; 12147 12148 u8 reserved_at_80[0x100]; 12149 12150 u8 opaque[0x40]; 12151 12152 u8 reserved_at_1c0[0x40]; 12153 12154 u8 key[8][0x80]; 12155 12156 u8 sw_wrapped_dek[8][0x80]; 12157 12158 u8 reserved_at_a00[0x600]; 12159 }; 12160 12161 struct mlx5_ifc_create_encryption_key_in_bits { 12162 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12163 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12164 }; 12165 12166 struct mlx5_ifc_modify_encryption_key_in_bits { 12167 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12168 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12169 }; 12170 12171 enum { 12172 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12173 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12174 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12175 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12176 }; 12177 12178 struct mlx5_ifc_flow_meter_parameters_bits { 12179 u8 valid[0x1]; 12180 u8 bucket_overflow[0x1]; 12181 u8 start_color[0x2]; 12182 u8 both_buckets_on_green[0x1]; 12183 u8 reserved_at_5[0x1]; 12184 u8 meter_mode[0x2]; 12185 u8 reserved_at_8[0x18]; 12186 12187 u8 reserved_at_20[0x20]; 12188 12189 u8 reserved_at_40[0x3]; 12190 u8 cbs_exponent[0x5]; 12191 u8 cbs_mantissa[0x8]; 12192 u8 reserved_at_50[0x3]; 12193 u8 cir_exponent[0x5]; 12194 u8 cir_mantissa[0x8]; 12195 12196 u8 reserved_at_60[0x20]; 12197 12198 u8 reserved_at_80[0x3]; 12199 u8 ebs_exponent[0x5]; 12200 u8 ebs_mantissa[0x8]; 12201 u8 reserved_at_90[0x3]; 12202 u8 eir_exponent[0x5]; 12203 u8 eir_mantissa[0x8]; 12204 12205 u8 reserved_at_a0[0x60]; 12206 }; 12207 12208 struct mlx5_ifc_flow_meter_aso_obj_bits { 12209 u8 modify_field_select[0x40]; 12210 12211 u8 reserved_at_40[0x40]; 12212 12213 u8 reserved_at_80[0x8]; 12214 u8 meter_aso_access_pd[0x18]; 12215 12216 u8 reserved_at_a0[0x160]; 12217 12218 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12219 }; 12220 12221 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12222 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12223 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12224 }; 12225 12226 struct mlx5_ifc_int_kek_obj_bits { 12227 u8 modify_field_select[0x40]; 12228 12229 u8 state[0x8]; 12230 u8 auto_gen[0x1]; 12231 u8 reserved_at_49[0xb]; 12232 u8 key_size[0x4]; 12233 u8 reserved_at_58[0x8]; 12234 12235 u8 reserved_at_60[0x8]; 12236 u8 pd[0x18]; 12237 12238 u8 reserved_at_80[0x180]; 12239 u8 key[8][0x80]; 12240 12241 u8 reserved_at_600[0x200]; 12242 }; 12243 12244 struct mlx5_ifc_create_int_kek_obj_in_bits { 12245 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12246 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12247 }; 12248 12249 struct mlx5_ifc_create_int_kek_obj_out_bits { 12250 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12251 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12252 }; 12253 12254 struct mlx5_ifc_sampler_obj_bits { 12255 u8 modify_field_select[0x40]; 12256 12257 u8 table_type[0x8]; 12258 u8 level[0x8]; 12259 u8 reserved_at_50[0xf]; 12260 u8 ignore_flow_level[0x1]; 12261 12262 u8 sample_ratio[0x20]; 12263 12264 u8 reserved_at_80[0x8]; 12265 u8 sample_table_id[0x18]; 12266 12267 u8 reserved_at_a0[0x8]; 12268 u8 default_table_id[0x18]; 12269 12270 u8 sw_steering_icm_address_rx[0x40]; 12271 u8 sw_steering_icm_address_tx[0x40]; 12272 12273 u8 reserved_at_140[0xa0]; 12274 }; 12275 12276 struct mlx5_ifc_create_sampler_obj_in_bits { 12277 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12278 struct mlx5_ifc_sampler_obj_bits sampler_object; 12279 }; 12280 12281 struct mlx5_ifc_query_sampler_obj_out_bits { 12282 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12283 struct mlx5_ifc_sampler_obj_bits sampler_object; 12284 }; 12285 12286 enum { 12287 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12288 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12289 }; 12290 12291 enum { 12292 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12293 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12294 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12295 }; 12296 12297 struct mlx5_ifc_tls_static_params_bits { 12298 u8 const_2[0x2]; 12299 u8 tls_version[0x4]; 12300 u8 const_1[0x2]; 12301 u8 reserved_at_8[0x14]; 12302 u8 encryption_standard[0x4]; 12303 12304 u8 reserved_at_20[0x20]; 12305 12306 u8 initial_record_number[0x40]; 12307 12308 u8 resync_tcp_sn[0x20]; 12309 12310 u8 gcm_iv[0x20]; 12311 12312 u8 implicit_iv[0x40]; 12313 12314 u8 reserved_at_100[0x8]; 12315 u8 dek_index[0x18]; 12316 12317 u8 reserved_at_120[0xe0]; 12318 }; 12319 12320 struct mlx5_ifc_tls_progress_params_bits { 12321 u8 next_record_tcp_sn[0x20]; 12322 12323 u8 hw_resync_tcp_sn[0x20]; 12324 12325 u8 record_tracker_state[0x2]; 12326 u8 auth_state[0x2]; 12327 u8 reserved_at_44[0x4]; 12328 u8 hw_offset_record_number[0x18]; 12329 }; 12330 12331 enum { 12332 MLX5_MTT_PERM_READ = 1 << 0, 12333 MLX5_MTT_PERM_WRITE = 1 << 1, 12334 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12335 }; 12336 12337 enum { 12338 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12339 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12340 }; 12341 12342 struct mlx5_ifc_suspend_vhca_in_bits { 12343 u8 opcode[0x10]; 12344 u8 uid[0x10]; 12345 12346 u8 reserved_at_20[0x10]; 12347 u8 op_mod[0x10]; 12348 12349 u8 reserved_at_40[0x10]; 12350 u8 vhca_id[0x10]; 12351 12352 u8 reserved_at_60[0x20]; 12353 }; 12354 12355 struct mlx5_ifc_suspend_vhca_out_bits { 12356 u8 status[0x8]; 12357 u8 reserved_at_8[0x18]; 12358 12359 u8 syndrome[0x20]; 12360 12361 u8 reserved_at_40[0x40]; 12362 }; 12363 12364 enum { 12365 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12366 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12367 }; 12368 12369 struct mlx5_ifc_resume_vhca_in_bits { 12370 u8 opcode[0x10]; 12371 u8 uid[0x10]; 12372 12373 u8 reserved_at_20[0x10]; 12374 u8 op_mod[0x10]; 12375 12376 u8 reserved_at_40[0x10]; 12377 u8 vhca_id[0x10]; 12378 12379 u8 reserved_at_60[0x20]; 12380 }; 12381 12382 struct mlx5_ifc_resume_vhca_out_bits { 12383 u8 status[0x8]; 12384 u8 reserved_at_8[0x18]; 12385 12386 u8 syndrome[0x20]; 12387 12388 u8 reserved_at_40[0x40]; 12389 }; 12390 12391 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12392 u8 opcode[0x10]; 12393 u8 uid[0x10]; 12394 12395 u8 reserved_at_20[0x10]; 12396 u8 op_mod[0x10]; 12397 12398 u8 incremental[0x1]; 12399 u8 reserved_at_41[0xf]; 12400 u8 vhca_id[0x10]; 12401 12402 u8 reserved_at_60[0x20]; 12403 }; 12404 12405 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12406 u8 status[0x8]; 12407 u8 reserved_at_8[0x18]; 12408 12409 u8 syndrome[0x20]; 12410 12411 u8 reserved_at_40[0x40]; 12412 12413 u8 required_umem_size[0x20]; 12414 12415 u8 reserved_at_a0[0x160]; 12416 }; 12417 12418 struct mlx5_ifc_save_vhca_state_in_bits { 12419 u8 opcode[0x10]; 12420 u8 uid[0x10]; 12421 12422 u8 reserved_at_20[0x10]; 12423 u8 op_mod[0x10]; 12424 12425 u8 incremental[0x1]; 12426 u8 set_track[0x1]; 12427 u8 reserved_at_42[0xe]; 12428 u8 vhca_id[0x10]; 12429 12430 u8 reserved_at_60[0x20]; 12431 12432 u8 va[0x40]; 12433 12434 u8 mkey[0x20]; 12435 12436 u8 size[0x20]; 12437 }; 12438 12439 struct mlx5_ifc_save_vhca_state_out_bits { 12440 u8 status[0x8]; 12441 u8 reserved_at_8[0x18]; 12442 12443 u8 syndrome[0x20]; 12444 12445 u8 actual_image_size[0x20]; 12446 12447 u8 reserved_at_60[0x20]; 12448 }; 12449 12450 struct mlx5_ifc_load_vhca_state_in_bits { 12451 u8 opcode[0x10]; 12452 u8 uid[0x10]; 12453 12454 u8 reserved_at_20[0x10]; 12455 u8 op_mod[0x10]; 12456 12457 u8 reserved_at_40[0x10]; 12458 u8 vhca_id[0x10]; 12459 12460 u8 reserved_at_60[0x20]; 12461 12462 u8 va[0x40]; 12463 12464 u8 mkey[0x20]; 12465 12466 u8 size[0x20]; 12467 }; 12468 12469 struct mlx5_ifc_load_vhca_state_out_bits { 12470 u8 status[0x8]; 12471 u8 reserved_at_8[0x18]; 12472 12473 u8 syndrome[0x20]; 12474 12475 u8 reserved_at_40[0x40]; 12476 }; 12477 12478 struct mlx5_ifc_adv_virtualization_cap_bits { 12479 u8 reserved_at_0[0x3]; 12480 u8 pg_track_log_max_num[0x5]; 12481 u8 pg_track_max_num_range[0x8]; 12482 u8 pg_track_log_min_addr_space[0x8]; 12483 u8 pg_track_log_max_addr_space[0x8]; 12484 12485 u8 reserved_at_20[0x3]; 12486 u8 pg_track_log_min_msg_size[0x5]; 12487 u8 reserved_at_28[0x3]; 12488 u8 pg_track_log_max_msg_size[0x5]; 12489 u8 reserved_at_30[0x3]; 12490 u8 pg_track_log_min_page_size[0x5]; 12491 u8 reserved_at_38[0x3]; 12492 u8 pg_track_log_max_page_size[0x5]; 12493 12494 u8 reserved_at_40[0x7c0]; 12495 }; 12496 12497 struct mlx5_ifc_page_track_report_entry_bits { 12498 u8 dirty_address_high[0x20]; 12499 12500 u8 dirty_address_low[0x20]; 12501 }; 12502 12503 enum { 12504 MLX5_PAGE_TRACK_STATE_TRACKING, 12505 MLX5_PAGE_TRACK_STATE_REPORTING, 12506 MLX5_PAGE_TRACK_STATE_ERROR, 12507 }; 12508 12509 struct mlx5_ifc_page_track_range_bits { 12510 u8 start_address[0x40]; 12511 12512 u8 length[0x40]; 12513 }; 12514 12515 struct mlx5_ifc_page_track_bits { 12516 u8 modify_field_select[0x40]; 12517 12518 u8 reserved_at_40[0x10]; 12519 u8 vhca_id[0x10]; 12520 12521 u8 reserved_at_60[0x20]; 12522 12523 u8 state[0x4]; 12524 u8 track_type[0x4]; 12525 u8 log_addr_space_size[0x8]; 12526 u8 reserved_at_90[0x3]; 12527 u8 log_page_size[0x5]; 12528 u8 reserved_at_98[0x3]; 12529 u8 log_msg_size[0x5]; 12530 12531 u8 reserved_at_a0[0x8]; 12532 u8 reporting_qpn[0x18]; 12533 12534 u8 reserved_at_c0[0x18]; 12535 u8 num_ranges[0x8]; 12536 12537 u8 reserved_at_e0[0x20]; 12538 12539 u8 range_start_address[0x40]; 12540 12541 u8 length[0x40]; 12542 12543 struct mlx5_ifc_page_track_range_bits track_range[0]; 12544 }; 12545 12546 struct mlx5_ifc_create_page_track_obj_in_bits { 12547 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12548 struct mlx5_ifc_page_track_bits obj_context; 12549 }; 12550 12551 struct mlx5_ifc_modify_page_track_obj_in_bits { 12552 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12553 struct mlx5_ifc_page_track_bits obj_context; 12554 }; 12555 12556 #endif /* MLX5_IFC_H */ 12557