1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 reserved_at_1e[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 reserved_at_41[0x4]; 375 u8 outer_first_mpls_over_udp[0x4]; 376 u8 outer_first_mpls_over_gre[0x4]; 377 u8 inner_first_mpls[0x4]; 378 u8 outer_first_mpls[0x4]; 379 u8 reserved_at_55[0x2]; 380 u8 outer_esp_spi[0x1]; 381 u8 reserved_at_58[0x2]; 382 u8 bth_dst_qp[0x1]; 383 u8 reserved_at_5b[0x5]; 384 385 u8 reserved_at_60[0x18]; 386 u8 metadata_reg_c_7[0x1]; 387 u8 metadata_reg_c_6[0x1]; 388 u8 metadata_reg_c_5[0x1]; 389 u8 metadata_reg_c_4[0x1]; 390 u8 metadata_reg_c_3[0x1]; 391 u8 metadata_reg_c_2[0x1]; 392 u8 metadata_reg_c_1[0x1]; 393 u8 metadata_reg_c_0[0x1]; 394 }; 395 396 struct mlx5_ifc_flow_table_prop_layout_bits { 397 u8 ft_support[0x1]; 398 u8 reserved_at_1[0x1]; 399 u8 flow_counter[0x1]; 400 u8 flow_modify_en[0x1]; 401 u8 modify_root[0x1]; 402 u8 identified_miss_table_mode[0x1]; 403 u8 flow_table_modify[0x1]; 404 u8 reformat[0x1]; 405 u8 decap[0x1]; 406 u8 reserved_at_9[0x1]; 407 u8 pop_vlan[0x1]; 408 u8 push_vlan[0x1]; 409 u8 reserved_at_c[0x1]; 410 u8 pop_vlan_2[0x1]; 411 u8 push_vlan_2[0x1]; 412 u8 reformat_and_vlan_action[0x1]; 413 u8 reserved_at_10[0x1]; 414 u8 sw_owner[0x1]; 415 u8 reformat_l3_tunnel_to_l2[0x1]; 416 u8 reformat_l2_to_l3_tunnel[0x1]; 417 u8 reformat_and_modify_action[0x1]; 418 u8 ignore_flow_level[0x1]; 419 u8 reserved_at_16[0x1]; 420 u8 table_miss_action_domain[0x1]; 421 u8 termination_table[0x1]; 422 u8 reformat_and_fwd_to_table[0x1]; 423 u8 reserved_at_1a[0x2]; 424 u8 ipsec_encrypt[0x1]; 425 u8 ipsec_decrypt[0x1]; 426 u8 sw_owner_v2[0x1]; 427 u8 reserved_at_1f[0x1]; 428 429 u8 termination_table_raw_traffic[0x1]; 430 u8 reserved_at_21[0x1]; 431 u8 log_max_ft_size[0x6]; 432 u8 log_max_modify_header_context[0x8]; 433 u8 max_modify_header_actions[0x8]; 434 u8 max_ft_level[0x8]; 435 436 u8 reserved_at_40[0x20]; 437 438 u8 reserved_at_60[0x2]; 439 u8 reformat_insert[0x1]; 440 u8 reformat_remove[0x1]; 441 u8 reserver_at_64[0x14]; 442 u8 log_max_ft_num[0x8]; 443 444 u8 reserved_at_80[0x10]; 445 u8 log_max_flow_counter[0x8]; 446 u8 log_max_destination[0x8]; 447 448 u8 reserved_at_a0[0x18]; 449 u8 log_max_flow[0x8]; 450 451 u8 reserved_at_c0[0x40]; 452 453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 454 455 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 456 }; 457 458 struct mlx5_ifc_odp_per_transport_service_cap_bits { 459 u8 send[0x1]; 460 u8 receive[0x1]; 461 u8 write[0x1]; 462 u8 read[0x1]; 463 u8 atomic[0x1]; 464 u8 srq_receive[0x1]; 465 u8 reserved_at_6[0x1a]; 466 }; 467 468 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 469 u8 smac_47_16[0x20]; 470 471 u8 smac_15_0[0x10]; 472 u8 ethertype[0x10]; 473 474 u8 dmac_47_16[0x20]; 475 476 u8 dmac_15_0[0x10]; 477 u8 first_prio[0x3]; 478 u8 first_cfi[0x1]; 479 u8 first_vid[0xc]; 480 481 u8 ip_protocol[0x8]; 482 u8 ip_dscp[0x6]; 483 u8 ip_ecn[0x2]; 484 u8 cvlan_tag[0x1]; 485 u8 svlan_tag[0x1]; 486 u8 frag[0x1]; 487 u8 ip_version[0x4]; 488 u8 tcp_flags[0x9]; 489 490 u8 tcp_sport[0x10]; 491 u8 tcp_dport[0x10]; 492 493 u8 reserved_at_c0[0x18]; 494 u8 ttl_hoplimit[0x8]; 495 496 u8 udp_sport[0x10]; 497 u8 udp_dport[0x10]; 498 499 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 500 501 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 502 }; 503 504 struct mlx5_ifc_nvgre_key_bits { 505 u8 hi[0x18]; 506 u8 lo[0x8]; 507 }; 508 509 union mlx5_ifc_gre_key_bits { 510 struct mlx5_ifc_nvgre_key_bits nvgre; 511 u8 key[0x20]; 512 }; 513 514 struct mlx5_ifc_fte_match_set_misc_bits { 515 u8 gre_c_present[0x1]; 516 u8 reserved_at_1[0x1]; 517 u8 gre_k_present[0x1]; 518 u8 gre_s_present[0x1]; 519 u8 source_vhca_port[0x4]; 520 u8 source_sqn[0x18]; 521 522 u8 source_eswitch_owner_vhca_id[0x10]; 523 u8 source_port[0x10]; 524 525 u8 outer_second_prio[0x3]; 526 u8 outer_second_cfi[0x1]; 527 u8 outer_second_vid[0xc]; 528 u8 inner_second_prio[0x3]; 529 u8 inner_second_cfi[0x1]; 530 u8 inner_second_vid[0xc]; 531 532 u8 outer_second_cvlan_tag[0x1]; 533 u8 inner_second_cvlan_tag[0x1]; 534 u8 outer_second_svlan_tag[0x1]; 535 u8 inner_second_svlan_tag[0x1]; 536 u8 reserved_at_64[0xc]; 537 u8 gre_protocol[0x10]; 538 539 union mlx5_ifc_gre_key_bits gre_key; 540 541 u8 vxlan_vni[0x18]; 542 u8 reserved_at_b8[0x8]; 543 544 u8 geneve_vni[0x18]; 545 u8 reserved_at_d8[0x7]; 546 u8 geneve_oam[0x1]; 547 548 u8 reserved_at_e0[0xc]; 549 u8 outer_ipv6_flow_label[0x14]; 550 551 u8 reserved_at_100[0xc]; 552 u8 inner_ipv6_flow_label[0x14]; 553 554 u8 reserved_at_120[0xa]; 555 u8 geneve_opt_len[0x6]; 556 u8 geneve_protocol_type[0x10]; 557 558 u8 reserved_at_140[0x8]; 559 u8 bth_dst_qp[0x18]; 560 u8 reserved_at_160[0x20]; 561 u8 outer_esp_spi[0x20]; 562 u8 reserved_at_1a0[0x60]; 563 }; 564 565 struct mlx5_ifc_fte_match_mpls_bits { 566 u8 mpls_label[0x14]; 567 u8 mpls_exp[0x3]; 568 u8 mpls_s_bos[0x1]; 569 u8 mpls_ttl[0x8]; 570 }; 571 572 struct mlx5_ifc_fte_match_set_misc2_bits { 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 574 575 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 576 577 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 578 579 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 580 581 u8 metadata_reg_c_7[0x20]; 582 583 u8 metadata_reg_c_6[0x20]; 584 585 u8 metadata_reg_c_5[0x20]; 586 587 u8 metadata_reg_c_4[0x20]; 588 589 u8 metadata_reg_c_3[0x20]; 590 591 u8 metadata_reg_c_2[0x20]; 592 593 u8 metadata_reg_c_1[0x20]; 594 595 u8 metadata_reg_c_0[0x20]; 596 597 u8 metadata_reg_a[0x20]; 598 599 u8 reserved_at_1a0[0x60]; 600 }; 601 602 struct mlx5_ifc_fte_match_set_misc3_bits { 603 u8 inner_tcp_seq_num[0x20]; 604 605 u8 outer_tcp_seq_num[0x20]; 606 607 u8 inner_tcp_ack_num[0x20]; 608 609 u8 outer_tcp_ack_num[0x20]; 610 611 u8 reserved_at_80[0x8]; 612 u8 outer_vxlan_gpe_vni[0x18]; 613 614 u8 outer_vxlan_gpe_next_protocol[0x8]; 615 u8 outer_vxlan_gpe_flags[0x8]; 616 u8 reserved_at_b0[0x10]; 617 618 u8 icmp_header_data[0x20]; 619 620 u8 icmpv6_header_data[0x20]; 621 622 u8 icmp_type[0x8]; 623 u8 icmp_code[0x8]; 624 u8 icmpv6_type[0x8]; 625 u8 icmpv6_code[0x8]; 626 627 u8 geneve_tlv_option_0_data[0x20]; 628 629 u8 gtpu_teid[0x20]; 630 631 u8 gtpu_msg_type[0x8]; 632 u8 gtpu_msg_flags[0x8]; 633 u8 reserved_at_170[0x10]; 634 635 u8 gtpu_dw_2[0x20]; 636 637 u8 gtpu_first_ext_dw_0[0x20]; 638 639 u8 gtpu_dw_0[0x20]; 640 641 u8 reserved_at_1e0[0x20]; 642 }; 643 644 struct mlx5_ifc_fte_match_set_misc4_bits { 645 u8 prog_sample_field_value_0[0x20]; 646 647 u8 prog_sample_field_id_0[0x20]; 648 649 u8 prog_sample_field_value_1[0x20]; 650 651 u8 prog_sample_field_id_1[0x20]; 652 653 u8 prog_sample_field_value_2[0x20]; 654 655 u8 prog_sample_field_id_2[0x20]; 656 657 u8 prog_sample_field_value_3[0x20]; 658 659 u8 prog_sample_field_id_3[0x20]; 660 661 u8 reserved_at_100[0x100]; 662 }; 663 664 struct mlx5_ifc_cmd_pas_bits { 665 u8 pa_h[0x20]; 666 667 u8 pa_l[0x14]; 668 u8 reserved_at_34[0xc]; 669 }; 670 671 struct mlx5_ifc_uint64_bits { 672 u8 hi[0x20]; 673 674 u8 lo[0x20]; 675 }; 676 677 enum { 678 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 679 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 680 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 681 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 682 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 683 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 684 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 685 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 686 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 687 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 688 }; 689 690 struct mlx5_ifc_ads_bits { 691 u8 fl[0x1]; 692 u8 free_ar[0x1]; 693 u8 reserved_at_2[0xe]; 694 u8 pkey_index[0x10]; 695 696 u8 reserved_at_20[0x8]; 697 u8 grh[0x1]; 698 u8 mlid[0x7]; 699 u8 rlid[0x10]; 700 701 u8 ack_timeout[0x5]; 702 u8 reserved_at_45[0x3]; 703 u8 src_addr_index[0x8]; 704 u8 reserved_at_50[0x4]; 705 u8 stat_rate[0x4]; 706 u8 hop_limit[0x8]; 707 708 u8 reserved_at_60[0x4]; 709 u8 tclass[0x8]; 710 u8 flow_label[0x14]; 711 712 u8 rgid_rip[16][0x8]; 713 714 u8 reserved_at_100[0x4]; 715 u8 f_dscp[0x1]; 716 u8 f_ecn[0x1]; 717 u8 reserved_at_106[0x1]; 718 u8 f_eth_prio[0x1]; 719 u8 ecn[0x2]; 720 u8 dscp[0x6]; 721 u8 udp_sport[0x10]; 722 723 u8 dei_cfi[0x1]; 724 u8 eth_prio[0x3]; 725 u8 sl[0x4]; 726 u8 vhca_port_num[0x8]; 727 u8 rmac_47_32[0x10]; 728 729 u8 rmac_31_0[0x20]; 730 }; 731 732 struct mlx5_ifc_flow_table_nic_cap_bits { 733 u8 nic_rx_multi_path_tirs[0x1]; 734 u8 nic_rx_multi_path_tirs_fts[0x1]; 735 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 736 u8 reserved_at_3[0x4]; 737 u8 sw_owner_reformat_supported[0x1]; 738 u8 reserved_at_8[0x18]; 739 740 u8 encap_general_header[0x1]; 741 u8 reserved_at_21[0xa]; 742 u8 log_max_packet_reformat_context[0x5]; 743 u8 reserved_at_30[0x6]; 744 u8 max_encap_header_size[0xa]; 745 u8 reserved_at_40[0x1c0]; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 758 759 u8 reserved_at_e00[0x1200]; 760 761 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 762 763 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 764 765 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 766 767 u8 reserved_at_20c0[0x5f40]; 768 }; 769 770 enum { 771 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 772 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 773 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 774 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 775 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 776 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 777 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 778 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 779 }; 780 781 struct mlx5_ifc_flow_table_eswitch_cap_bits { 782 u8 fdb_to_vport_reg_c_id[0x8]; 783 u8 reserved_at_8[0xd]; 784 u8 fdb_modify_header_fwd_to_table[0x1]; 785 u8 reserved_at_16[0x1]; 786 u8 flow_source[0x1]; 787 u8 reserved_at_18[0x2]; 788 u8 multi_fdb_encap[0x1]; 789 u8 egress_acl_forward_to_vport[0x1]; 790 u8 fdb_multi_path_to_table[0x1]; 791 u8 reserved_at_1d[0x3]; 792 793 u8 reserved_at_20[0x1e0]; 794 795 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 796 797 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 798 799 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 800 801 u8 reserved_at_800[0x1000]; 802 803 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 804 805 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 806 807 u8 sw_steering_uplink_icm_address_rx[0x40]; 808 809 u8 sw_steering_uplink_icm_address_tx[0x40]; 810 811 u8 reserved_at_1900[0x6700]; 812 }; 813 814 enum { 815 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 816 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 817 }; 818 819 struct mlx5_ifc_e_switch_cap_bits { 820 u8 vport_svlan_strip[0x1]; 821 u8 vport_cvlan_strip[0x1]; 822 u8 vport_svlan_insert[0x1]; 823 u8 vport_cvlan_insert_if_not_exist[0x1]; 824 u8 vport_cvlan_insert_overwrite[0x1]; 825 u8 reserved_at_5[0x2]; 826 u8 esw_shared_ingress_acl[0x1]; 827 u8 esw_uplink_ingress_acl[0x1]; 828 u8 root_ft_on_other_esw[0x1]; 829 u8 reserved_at_a[0xf]; 830 u8 esw_functions_changed[0x1]; 831 u8 reserved_at_1a[0x1]; 832 u8 ecpf_vport_exists[0x1]; 833 u8 counter_eswitch_affinity[0x1]; 834 u8 merged_eswitch[0x1]; 835 u8 nic_vport_node_guid_modify[0x1]; 836 u8 nic_vport_port_guid_modify[0x1]; 837 838 u8 vxlan_encap_decap[0x1]; 839 u8 nvgre_encap_decap[0x1]; 840 u8 reserved_at_22[0x1]; 841 u8 log_max_fdb_encap_uplink[0x5]; 842 u8 reserved_at_21[0x3]; 843 u8 log_max_packet_reformat_context[0x5]; 844 u8 reserved_2b[0x6]; 845 u8 max_encap_header_size[0xa]; 846 847 u8 reserved_at_40[0xb]; 848 u8 log_max_esw_sf[0x5]; 849 u8 esw_sf_base_id[0x10]; 850 851 u8 reserved_at_60[0x7a0]; 852 853 }; 854 855 struct mlx5_ifc_qos_cap_bits { 856 u8 packet_pacing[0x1]; 857 u8 esw_scheduling[0x1]; 858 u8 esw_bw_share[0x1]; 859 u8 esw_rate_limit[0x1]; 860 u8 reserved_at_4[0x1]; 861 u8 packet_pacing_burst_bound[0x1]; 862 u8 packet_pacing_typical_size[0x1]; 863 u8 reserved_at_7[0x1]; 864 u8 nic_sq_scheduling[0x1]; 865 u8 nic_bw_share[0x1]; 866 u8 nic_rate_limit[0x1]; 867 u8 packet_pacing_uid[0x1]; 868 u8 reserved_at_c[0x14]; 869 870 u8 reserved_at_20[0xb]; 871 u8 log_max_qos_nic_queue_group[0x5]; 872 u8 reserved_at_30[0x10]; 873 874 u8 packet_pacing_max_rate[0x20]; 875 876 u8 packet_pacing_min_rate[0x20]; 877 878 u8 reserved_at_80[0x10]; 879 u8 packet_pacing_rate_table_size[0x10]; 880 881 u8 esw_element_type[0x10]; 882 u8 esw_tsar_type[0x10]; 883 884 u8 reserved_at_c0[0x10]; 885 u8 max_qos_para_vport[0x10]; 886 887 u8 max_tsar_bw_share[0x20]; 888 889 u8 reserved_at_100[0x700]; 890 }; 891 892 struct mlx5_ifc_debug_cap_bits { 893 u8 core_dump_general[0x1]; 894 u8 core_dump_qp[0x1]; 895 u8 reserved_at_2[0x7]; 896 u8 resource_dump[0x1]; 897 u8 reserved_at_a[0x16]; 898 899 u8 reserved_at_20[0x2]; 900 u8 stall_detect[0x1]; 901 u8 reserved_at_23[0x1d]; 902 903 u8 reserved_at_40[0x7c0]; 904 }; 905 906 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 907 u8 csum_cap[0x1]; 908 u8 vlan_cap[0x1]; 909 u8 lro_cap[0x1]; 910 u8 lro_psh_flag[0x1]; 911 u8 lro_time_stamp[0x1]; 912 u8 reserved_at_5[0x2]; 913 u8 wqe_vlan_insert[0x1]; 914 u8 self_lb_en_modifiable[0x1]; 915 u8 reserved_at_9[0x2]; 916 u8 max_lso_cap[0x5]; 917 u8 multi_pkt_send_wqe[0x2]; 918 u8 wqe_inline_mode[0x2]; 919 u8 rss_ind_tbl_cap[0x4]; 920 u8 reg_umr_sq[0x1]; 921 u8 scatter_fcs[0x1]; 922 u8 enhanced_multi_pkt_send_wqe[0x1]; 923 u8 tunnel_lso_const_out_ip_id[0x1]; 924 u8 reserved_at_1c[0x2]; 925 u8 tunnel_stateless_gre[0x1]; 926 u8 tunnel_stateless_vxlan[0x1]; 927 928 u8 swp[0x1]; 929 u8 swp_csum[0x1]; 930 u8 swp_lso[0x1]; 931 u8 cqe_checksum_full[0x1]; 932 u8 tunnel_stateless_geneve_tx[0x1]; 933 u8 tunnel_stateless_mpls_over_udp[0x1]; 934 u8 tunnel_stateless_mpls_over_gre[0x1]; 935 u8 tunnel_stateless_vxlan_gpe[0x1]; 936 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 937 u8 tunnel_stateless_ip_over_ip[0x1]; 938 u8 insert_trailer[0x1]; 939 u8 reserved_at_2b[0x1]; 940 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 941 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 942 u8 reserved_at_2e[0x2]; 943 u8 max_vxlan_udp_ports[0x8]; 944 u8 reserved_at_38[0x6]; 945 u8 max_geneve_opt_len[0x1]; 946 u8 tunnel_stateless_geneve_rx[0x1]; 947 948 u8 reserved_at_40[0x10]; 949 u8 lro_min_mss_size[0x10]; 950 951 u8 reserved_at_60[0x120]; 952 953 u8 lro_timer_supported_periods[4][0x20]; 954 955 u8 reserved_at_200[0x600]; 956 }; 957 958 enum { 959 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 960 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 961 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 962 }; 963 964 struct mlx5_ifc_roce_cap_bits { 965 u8 roce_apm[0x1]; 966 u8 reserved_at_1[0x3]; 967 u8 sw_r_roce_src_udp_port[0x1]; 968 u8 fl_rc_qp_when_roce_disabled[0x1]; 969 u8 fl_rc_qp_when_roce_enabled[0x1]; 970 u8 reserved_at_7[0x17]; 971 u8 qp_ts_format[0x2]; 972 973 u8 reserved_at_20[0x60]; 974 975 u8 reserved_at_80[0xc]; 976 u8 l3_type[0x4]; 977 u8 reserved_at_90[0x8]; 978 u8 roce_version[0x8]; 979 980 u8 reserved_at_a0[0x10]; 981 u8 r_roce_dest_udp_port[0x10]; 982 983 u8 r_roce_max_src_udp_port[0x10]; 984 u8 r_roce_min_src_udp_port[0x10]; 985 986 u8 reserved_at_e0[0x10]; 987 u8 roce_address_table_size[0x10]; 988 989 u8 reserved_at_100[0x700]; 990 }; 991 992 struct mlx5_ifc_sync_steering_in_bits { 993 u8 opcode[0x10]; 994 u8 uid[0x10]; 995 996 u8 reserved_at_20[0x10]; 997 u8 op_mod[0x10]; 998 999 u8 reserved_at_40[0xc0]; 1000 }; 1001 1002 struct mlx5_ifc_sync_steering_out_bits { 1003 u8 status[0x8]; 1004 u8 reserved_at_8[0x18]; 1005 1006 u8 syndrome[0x20]; 1007 1008 u8 reserved_at_40[0x40]; 1009 }; 1010 1011 struct mlx5_ifc_device_mem_cap_bits { 1012 u8 memic[0x1]; 1013 u8 reserved_at_1[0x1f]; 1014 1015 u8 reserved_at_20[0xb]; 1016 u8 log_min_memic_alloc_size[0x5]; 1017 u8 reserved_at_30[0x8]; 1018 u8 log_max_memic_addr_alignment[0x8]; 1019 1020 u8 memic_bar_start_addr[0x40]; 1021 1022 u8 memic_bar_size[0x20]; 1023 1024 u8 max_memic_size[0x20]; 1025 1026 u8 steering_sw_icm_start_address[0x40]; 1027 1028 u8 reserved_at_100[0x8]; 1029 u8 log_header_modify_sw_icm_size[0x8]; 1030 u8 reserved_at_110[0x2]; 1031 u8 log_sw_icm_alloc_granularity[0x6]; 1032 u8 log_steering_sw_icm_size[0x8]; 1033 1034 u8 reserved_at_120[0x20]; 1035 1036 u8 header_modify_sw_icm_start_address[0x40]; 1037 1038 u8 reserved_at_180[0x80]; 1039 1040 u8 memic_operations[0x20]; 1041 1042 u8 reserved_at_220[0x5e0]; 1043 }; 1044 1045 struct mlx5_ifc_device_event_cap_bits { 1046 u8 user_affiliated_events[4][0x40]; 1047 1048 u8 user_unaffiliated_events[4][0x40]; 1049 }; 1050 1051 struct mlx5_ifc_virtio_emulation_cap_bits { 1052 u8 desc_tunnel_offload_type[0x1]; 1053 u8 eth_frame_offload_type[0x1]; 1054 u8 virtio_version_1_0[0x1]; 1055 u8 device_features_bits_mask[0xd]; 1056 u8 event_mode[0x8]; 1057 u8 virtio_queue_type[0x8]; 1058 1059 u8 max_tunnel_desc[0x10]; 1060 u8 reserved_at_30[0x3]; 1061 u8 log_doorbell_stride[0x5]; 1062 u8 reserved_at_38[0x3]; 1063 u8 log_doorbell_bar_size[0x5]; 1064 1065 u8 doorbell_bar_offset[0x40]; 1066 1067 u8 max_emulated_devices[0x8]; 1068 u8 max_num_virtio_queues[0x18]; 1069 1070 u8 reserved_at_a0[0x60]; 1071 1072 u8 umem_1_buffer_param_a[0x20]; 1073 1074 u8 umem_1_buffer_param_b[0x20]; 1075 1076 u8 umem_2_buffer_param_a[0x20]; 1077 1078 u8 umem_2_buffer_param_b[0x20]; 1079 1080 u8 umem_3_buffer_param_a[0x20]; 1081 1082 u8 umem_3_buffer_param_b[0x20]; 1083 1084 u8 reserved_at_1c0[0x640]; 1085 }; 1086 1087 enum { 1088 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1089 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1090 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1091 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1092 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1093 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1094 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1095 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1096 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1097 }; 1098 1099 enum { 1100 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1101 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1102 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1103 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1104 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1105 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1106 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1107 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1108 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1109 }; 1110 1111 struct mlx5_ifc_atomic_caps_bits { 1112 u8 reserved_at_0[0x40]; 1113 1114 u8 atomic_req_8B_endianness_mode[0x2]; 1115 u8 reserved_at_42[0x4]; 1116 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1117 1118 u8 reserved_at_47[0x19]; 1119 1120 u8 reserved_at_60[0x20]; 1121 1122 u8 reserved_at_80[0x10]; 1123 u8 atomic_operations[0x10]; 1124 1125 u8 reserved_at_a0[0x10]; 1126 u8 atomic_size_qp[0x10]; 1127 1128 u8 reserved_at_c0[0x10]; 1129 u8 atomic_size_dc[0x10]; 1130 1131 u8 reserved_at_e0[0x720]; 1132 }; 1133 1134 struct mlx5_ifc_odp_cap_bits { 1135 u8 reserved_at_0[0x40]; 1136 1137 u8 sig[0x1]; 1138 u8 reserved_at_41[0x1f]; 1139 1140 u8 reserved_at_60[0x20]; 1141 1142 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1143 1144 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1145 1146 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1147 1148 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1149 1150 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1151 1152 u8 reserved_at_120[0x6E0]; 1153 }; 1154 1155 struct mlx5_ifc_calc_op { 1156 u8 reserved_at_0[0x10]; 1157 u8 reserved_at_10[0x9]; 1158 u8 op_swap_endianness[0x1]; 1159 u8 op_min[0x1]; 1160 u8 op_xor[0x1]; 1161 u8 op_or[0x1]; 1162 u8 op_and[0x1]; 1163 u8 op_max[0x1]; 1164 u8 op_add[0x1]; 1165 }; 1166 1167 struct mlx5_ifc_vector_calc_cap_bits { 1168 u8 calc_matrix[0x1]; 1169 u8 reserved_at_1[0x1f]; 1170 u8 reserved_at_20[0x8]; 1171 u8 max_vec_count[0x8]; 1172 u8 reserved_at_30[0xd]; 1173 u8 max_chunk_size[0x3]; 1174 struct mlx5_ifc_calc_op calc0; 1175 struct mlx5_ifc_calc_op calc1; 1176 struct mlx5_ifc_calc_op calc2; 1177 struct mlx5_ifc_calc_op calc3; 1178 1179 u8 reserved_at_c0[0x720]; 1180 }; 1181 1182 struct mlx5_ifc_tls_cap_bits { 1183 u8 tls_1_2_aes_gcm_128[0x1]; 1184 u8 tls_1_3_aes_gcm_128[0x1]; 1185 u8 tls_1_2_aes_gcm_256[0x1]; 1186 u8 tls_1_3_aes_gcm_256[0x1]; 1187 u8 reserved_at_4[0x1c]; 1188 1189 u8 reserved_at_20[0x7e0]; 1190 }; 1191 1192 struct mlx5_ifc_ipsec_cap_bits { 1193 u8 ipsec_full_offload[0x1]; 1194 u8 ipsec_crypto_offload[0x1]; 1195 u8 ipsec_esn[0x1]; 1196 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1197 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1198 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1199 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1200 u8 reserved_at_7[0x4]; 1201 u8 log_max_ipsec_offload[0x5]; 1202 u8 reserved_at_10[0x10]; 1203 1204 u8 min_log_ipsec_full_replay_window[0x8]; 1205 u8 max_log_ipsec_full_replay_window[0x8]; 1206 u8 reserved_at_30[0x7d0]; 1207 }; 1208 1209 enum { 1210 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1211 MLX5_WQ_TYPE_CYCLIC = 0x1, 1212 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1213 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1214 }; 1215 1216 enum { 1217 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1218 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1219 }; 1220 1221 enum { 1222 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1223 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1224 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1225 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1226 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1227 }; 1228 1229 enum { 1230 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1231 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1232 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1233 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1234 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1235 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1236 }; 1237 1238 enum { 1239 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1240 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1241 }; 1242 1243 enum { 1244 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1245 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1246 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1247 }; 1248 1249 enum { 1250 MLX5_CAP_PORT_TYPE_IB = 0x0, 1251 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1252 }; 1253 1254 enum { 1255 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1256 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1257 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1258 }; 1259 1260 enum { 1261 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1262 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1263 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1264 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1265 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1266 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1267 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1268 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1269 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1270 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1271 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1272 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1273 }; 1274 1275 enum { 1276 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1277 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1278 }; 1279 1280 #define MLX5_FC_BULK_SIZE_FACTOR 128 1281 1282 enum mlx5_fc_bulk_alloc_bitmask { 1283 MLX5_FC_BULK_128 = (1 << 0), 1284 MLX5_FC_BULK_256 = (1 << 1), 1285 MLX5_FC_BULK_512 = (1 << 2), 1286 MLX5_FC_BULK_1024 = (1 << 3), 1287 MLX5_FC_BULK_2048 = (1 << 4), 1288 MLX5_FC_BULK_4096 = (1 << 5), 1289 MLX5_FC_BULK_8192 = (1 << 6), 1290 MLX5_FC_BULK_16384 = (1 << 7), 1291 }; 1292 1293 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1294 1295 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1296 1297 enum { 1298 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1299 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1300 }; 1301 1302 struct mlx5_ifc_cmd_hca_cap_bits { 1303 u8 reserved_at_0[0x1f]; 1304 u8 vhca_resource_manager[0x1]; 1305 1306 u8 hca_cap_2[0x1]; 1307 u8 reserved_at_21[0x2]; 1308 u8 event_on_vhca_state_teardown_request[0x1]; 1309 u8 event_on_vhca_state_in_use[0x1]; 1310 u8 event_on_vhca_state_active[0x1]; 1311 u8 event_on_vhca_state_allocated[0x1]; 1312 u8 event_on_vhca_state_invalid[0x1]; 1313 u8 reserved_at_28[0x8]; 1314 u8 vhca_id[0x10]; 1315 1316 u8 reserved_at_40[0x40]; 1317 1318 u8 log_max_srq_sz[0x8]; 1319 u8 log_max_qp_sz[0x8]; 1320 u8 event_cap[0x1]; 1321 u8 reserved_at_91[0x2]; 1322 u8 isolate_vl_tc_new[0x1]; 1323 u8 reserved_at_94[0x4]; 1324 u8 prio_tag_required[0x1]; 1325 u8 reserved_at_99[0x2]; 1326 u8 log_max_qp[0x5]; 1327 1328 u8 reserved_at_a0[0x3]; 1329 u8 ece_support[0x1]; 1330 u8 reserved_at_a4[0x5]; 1331 u8 reg_c_preserve[0x1]; 1332 u8 reserved_at_aa[0x1]; 1333 u8 log_max_srq[0x5]; 1334 u8 reserved_at_b0[0x1]; 1335 u8 uplink_follow[0x1]; 1336 u8 ts_cqe_to_dest_cqn[0x1]; 1337 u8 reserved_at_b3[0xd]; 1338 1339 u8 max_sgl_for_optimized_performance[0x8]; 1340 u8 log_max_cq_sz[0x8]; 1341 u8 relaxed_ordering_write_umr[0x1]; 1342 u8 relaxed_ordering_read_umr[0x1]; 1343 u8 reserved_at_d2[0x7]; 1344 u8 virtio_net_device_emualtion_manager[0x1]; 1345 u8 virtio_blk_device_emualtion_manager[0x1]; 1346 u8 log_max_cq[0x5]; 1347 1348 u8 log_max_eq_sz[0x8]; 1349 u8 relaxed_ordering_write[0x1]; 1350 u8 relaxed_ordering_read[0x1]; 1351 u8 log_max_mkey[0x6]; 1352 u8 reserved_at_f0[0x8]; 1353 u8 dump_fill_mkey[0x1]; 1354 u8 reserved_at_f9[0x2]; 1355 u8 fast_teardown[0x1]; 1356 u8 log_max_eq[0x4]; 1357 1358 u8 max_indirection[0x8]; 1359 u8 fixed_buffer_size[0x1]; 1360 u8 log_max_mrw_sz[0x7]; 1361 u8 force_teardown[0x1]; 1362 u8 reserved_at_111[0x1]; 1363 u8 log_max_bsf_list_size[0x6]; 1364 u8 umr_extended_translation_offset[0x1]; 1365 u8 null_mkey[0x1]; 1366 u8 log_max_klm_list_size[0x6]; 1367 1368 u8 reserved_at_120[0xa]; 1369 u8 log_max_ra_req_dc[0x6]; 1370 u8 reserved_at_130[0xa]; 1371 u8 log_max_ra_res_dc[0x6]; 1372 1373 u8 reserved_at_140[0x6]; 1374 u8 release_all_pages[0x1]; 1375 u8 reserved_at_147[0x2]; 1376 u8 roce_accl[0x1]; 1377 u8 log_max_ra_req_qp[0x6]; 1378 u8 reserved_at_150[0xa]; 1379 u8 log_max_ra_res_qp[0x6]; 1380 1381 u8 end_pad[0x1]; 1382 u8 cc_query_allowed[0x1]; 1383 u8 cc_modify_allowed[0x1]; 1384 u8 start_pad[0x1]; 1385 u8 cache_line_128byte[0x1]; 1386 u8 reserved_at_165[0x4]; 1387 u8 rts2rts_qp_counters_set_id[0x1]; 1388 u8 reserved_at_16a[0x2]; 1389 u8 vnic_env_int_rq_oob[0x1]; 1390 u8 sbcam_reg[0x1]; 1391 u8 reserved_at_16e[0x1]; 1392 u8 qcam_reg[0x1]; 1393 u8 gid_table_size[0x10]; 1394 1395 u8 out_of_seq_cnt[0x1]; 1396 u8 vport_counters[0x1]; 1397 u8 retransmission_q_counters[0x1]; 1398 u8 debug[0x1]; 1399 u8 modify_rq_counter_set_id[0x1]; 1400 u8 rq_delay_drop[0x1]; 1401 u8 max_qp_cnt[0xa]; 1402 u8 pkey_table_size[0x10]; 1403 1404 u8 vport_group_manager[0x1]; 1405 u8 vhca_group_manager[0x1]; 1406 u8 ib_virt[0x1]; 1407 u8 eth_virt[0x1]; 1408 u8 vnic_env_queue_counters[0x1]; 1409 u8 ets[0x1]; 1410 u8 nic_flow_table[0x1]; 1411 u8 eswitch_manager[0x1]; 1412 u8 device_memory[0x1]; 1413 u8 mcam_reg[0x1]; 1414 u8 pcam_reg[0x1]; 1415 u8 local_ca_ack_delay[0x5]; 1416 u8 port_module_event[0x1]; 1417 u8 enhanced_error_q_counters[0x1]; 1418 u8 ports_check[0x1]; 1419 u8 reserved_at_1b3[0x1]; 1420 u8 disable_link_up[0x1]; 1421 u8 beacon_led[0x1]; 1422 u8 port_type[0x2]; 1423 u8 num_ports[0x8]; 1424 1425 u8 reserved_at_1c0[0x1]; 1426 u8 pps[0x1]; 1427 u8 pps_modify[0x1]; 1428 u8 log_max_msg[0x5]; 1429 u8 reserved_at_1c8[0x4]; 1430 u8 max_tc[0x4]; 1431 u8 temp_warn_event[0x1]; 1432 u8 dcbx[0x1]; 1433 u8 general_notification_event[0x1]; 1434 u8 reserved_at_1d3[0x2]; 1435 u8 fpga[0x1]; 1436 u8 rol_s[0x1]; 1437 u8 rol_g[0x1]; 1438 u8 reserved_at_1d8[0x1]; 1439 u8 wol_s[0x1]; 1440 u8 wol_g[0x1]; 1441 u8 wol_a[0x1]; 1442 u8 wol_b[0x1]; 1443 u8 wol_m[0x1]; 1444 u8 wol_u[0x1]; 1445 u8 wol_p[0x1]; 1446 1447 u8 stat_rate_support[0x10]; 1448 u8 reserved_at_1f0[0x1]; 1449 u8 pci_sync_for_fw_update_event[0x1]; 1450 u8 reserved_at_1f2[0x6]; 1451 u8 init2_lag_tx_port_affinity[0x1]; 1452 u8 reserved_at_1fa[0x3]; 1453 u8 cqe_version[0x4]; 1454 1455 u8 compact_address_vector[0x1]; 1456 u8 striding_rq[0x1]; 1457 u8 reserved_at_202[0x1]; 1458 u8 ipoib_enhanced_offloads[0x1]; 1459 u8 ipoib_basic_offloads[0x1]; 1460 u8 reserved_at_205[0x1]; 1461 u8 repeated_block_disabled[0x1]; 1462 u8 umr_modify_entity_size_disabled[0x1]; 1463 u8 umr_modify_atomic_disabled[0x1]; 1464 u8 umr_indirect_mkey_disabled[0x1]; 1465 u8 umr_fence[0x2]; 1466 u8 dc_req_scat_data_cqe[0x1]; 1467 u8 reserved_at_20d[0x2]; 1468 u8 drain_sigerr[0x1]; 1469 u8 cmdif_checksum[0x2]; 1470 u8 sigerr_cqe[0x1]; 1471 u8 reserved_at_213[0x1]; 1472 u8 wq_signature[0x1]; 1473 u8 sctr_data_cqe[0x1]; 1474 u8 reserved_at_216[0x1]; 1475 u8 sho[0x1]; 1476 u8 tph[0x1]; 1477 u8 rf[0x1]; 1478 u8 dct[0x1]; 1479 u8 qos[0x1]; 1480 u8 eth_net_offloads[0x1]; 1481 u8 roce[0x1]; 1482 u8 atomic[0x1]; 1483 u8 reserved_at_21f[0x1]; 1484 1485 u8 cq_oi[0x1]; 1486 u8 cq_resize[0x1]; 1487 u8 cq_moderation[0x1]; 1488 u8 reserved_at_223[0x3]; 1489 u8 cq_eq_remap[0x1]; 1490 u8 pg[0x1]; 1491 u8 block_lb_mc[0x1]; 1492 u8 reserved_at_229[0x1]; 1493 u8 scqe_break_moderation[0x1]; 1494 u8 cq_period_start_from_cqe[0x1]; 1495 u8 cd[0x1]; 1496 u8 reserved_at_22d[0x1]; 1497 u8 apm[0x1]; 1498 u8 vector_calc[0x1]; 1499 u8 umr_ptr_rlky[0x1]; 1500 u8 imaicl[0x1]; 1501 u8 qp_packet_based[0x1]; 1502 u8 reserved_at_233[0x3]; 1503 u8 qkv[0x1]; 1504 u8 pkv[0x1]; 1505 u8 set_deth_sqpn[0x1]; 1506 u8 reserved_at_239[0x3]; 1507 u8 xrc[0x1]; 1508 u8 ud[0x1]; 1509 u8 uc[0x1]; 1510 u8 rc[0x1]; 1511 1512 u8 uar_4k[0x1]; 1513 u8 reserved_at_241[0x9]; 1514 u8 uar_sz[0x6]; 1515 u8 reserved_at_250[0x8]; 1516 u8 log_pg_sz[0x8]; 1517 1518 u8 bf[0x1]; 1519 u8 driver_version[0x1]; 1520 u8 pad_tx_eth_packet[0x1]; 1521 u8 reserved_at_263[0x3]; 1522 u8 mkey_by_name[0x1]; 1523 u8 reserved_at_267[0x4]; 1524 1525 u8 log_bf_reg_size[0x5]; 1526 1527 u8 reserved_at_270[0x6]; 1528 u8 lag_dct[0x2]; 1529 u8 lag_tx_port_affinity[0x1]; 1530 u8 lag_native_fdb_selection[0x1]; 1531 u8 reserved_at_27a[0x1]; 1532 u8 lag_master[0x1]; 1533 u8 num_lag_ports[0x4]; 1534 1535 u8 reserved_at_280[0x10]; 1536 u8 max_wqe_sz_sq[0x10]; 1537 1538 u8 reserved_at_2a0[0x10]; 1539 u8 max_wqe_sz_rq[0x10]; 1540 1541 u8 max_flow_counter_31_16[0x10]; 1542 u8 max_wqe_sz_sq_dc[0x10]; 1543 1544 u8 reserved_at_2e0[0x7]; 1545 u8 max_qp_mcg[0x19]; 1546 1547 u8 reserved_at_300[0x10]; 1548 u8 flow_counter_bulk_alloc[0x8]; 1549 u8 log_max_mcg[0x8]; 1550 1551 u8 reserved_at_320[0x3]; 1552 u8 log_max_transport_domain[0x5]; 1553 u8 reserved_at_328[0x3]; 1554 u8 log_max_pd[0x5]; 1555 u8 reserved_at_330[0xb]; 1556 u8 log_max_xrcd[0x5]; 1557 1558 u8 nic_receive_steering_discard[0x1]; 1559 u8 receive_discard_vport_down[0x1]; 1560 u8 transmit_discard_vport_down[0x1]; 1561 u8 reserved_at_343[0x5]; 1562 u8 log_max_flow_counter_bulk[0x8]; 1563 u8 max_flow_counter_15_0[0x10]; 1564 1565 1566 u8 reserved_at_360[0x3]; 1567 u8 log_max_rq[0x5]; 1568 u8 reserved_at_368[0x3]; 1569 u8 log_max_sq[0x5]; 1570 u8 reserved_at_370[0x3]; 1571 u8 log_max_tir[0x5]; 1572 u8 reserved_at_378[0x3]; 1573 u8 log_max_tis[0x5]; 1574 1575 u8 basic_cyclic_rcv_wqe[0x1]; 1576 u8 reserved_at_381[0x2]; 1577 u8 log_max_rmp[0x5]; 1578 u8 reserved_at_388[0x3]; 1579 u8 log_max_rqt[0x5]; 1580 u8 reserved_at_390[0x3]; 1581 u8 log_max_rqt_size[0x5]; 1582 u8 reserved_at_398[0x3]; 1583 u8 log_max_tis_per_sq[0x5]; 1584 1585 u8 ext_stride_num_range[0x1]; 1586 u8 reserved_at_3a1[0x2]; 1587 u8 log_max_stride_sz_rq[0x5]; 1588 u8 reserved_at_3a8[0x3]; 1589 u8 log_min_stride_sz_rq[0x5]; 1590 u8 reserved_at_3b0[0x3]; 1591 u8 log_max_stride_sz_sq[0x5]; 1592 u8 reserved_at_3b8[0x3]; 1593 u8 log_min_stride_sz_sq[0x5]; 1594 1595 u8 hairpin[0x1]; 1596 u8 reserved_at_3c1[0x2]; 1597 u8 log_max_hairpin_queues[0x5]; 1598 u8 reserved_at_3c8[0x3]; 1599 u8 log_max_hairpin_wq_data_sz[0x5]; 1600 u8 reserved_at_3d0[0x3]; 1601 u8 log_max_hairpin_num_packets[0x5]; 1602 u8 reserved_at_3d8[0x3]; 1603 u8 log_max_wq_sz[0x5]; 1604 1605 u8 nic_vport_change_event[0x1]; 1606 u8 disable_local_lb_uc[0x1]; 1607 u8 disable_local_lb_mc[0x1]; 1608 u8 log_min_hairpin_wq_data_sz[0x5]; 1609 u8 reserved_at_3e8[0x2]; 1610 u8 vhca_state[0x1]; 1611 u8 log_max_vlan_list[0x5]; 1612 u8 reserved_at_3f0[0x3]; 1613 u8 log_max_current_mc_list[0x5]; 1614 u8 reserved_at_3f8[0x3]; 1615 u8 log_max_current_uc_list[0x5]; 1616 1617 u8 general_obj_types[0x40]; 1618 1619 u8 sq_ts_format[0x2]; 1620 u8 rq_ts_format[0x2]; 1621 u8 steering_format_version[0x4]; 1622 u8 create_qp_start_hint[0x18]; 1623 1624 u8 reserved_at_460[0x3]; 1625 u8 log_max_uctx[0x5]; 1626 u8 reserved_at_468[0x2]; 1627 u8 ipsec_offload[0x1]; 1628 u8 log_max_umem[0x5]; 1629 u8 max_num_eqs[0x10]; 1630 1631 u8 reserved_at_480[0x1]; 1632 u8 tls_tx[0x1]; 1633 u8 tls_rx[0x1]; 1634 u8 log_max_l2_table[0x5]; 1635 u8 reserved_at_488[0x8]; 1636 u8 log_uar_page_sz[0x10]; 1637 1638 u8 reserved_at_4a0[0x20]; 1639 u8 device_frequency_mhz[0x20]; 1640 u8 device_frequency_khz[0x20]; 1641 1642 u8 reserved_at_500[0x20]; 1643 u8 num_of_uars_per_page[0x20]; 1644 1645 u8 flex_parser_protocols[0x20]; 1646 1647 u8 max_geneve_tlv_options[0x8]; 1648 u8 reserved_at_568[0x3]; 1649 u8 max_geneve_tlv_option_data_len[0x5]; 1650 u8 reserved_at_570[0x10]; 1651 1652 u8 reserved_at_580[0x33]; 1653 u8 log_max_dek[0x5]; 1654 u8 reserved_at_5b8[0x4]; 1655 u8 mini_cqe_resp_stride_index[0x1]; 1656 u8 cqe_128_always[0x1]; 1657 u8 cqe_compression_128[0x1]; 1658 u8 cqe_compression[0x1]; 1659 1660 u8 cqe_compression_timeout[0x10]; 1661 u8 cqe_compression_max_num[0x10]; 1662 1663 u8 reserved_at_5e0[0x8]; 1664 u8 flex_parser_id_gtpu_dw_0[0x4]; 1665 u8 reserved_at_5ec[0x4]; 1666 u8 tag_matching[0x1]; 1667 u8 rndv_offload_rc[0x1]; 1668 u8 rndv_offload_dc[0x1]; 1669 u8 log_tag_matching_list_sz[0x5]; 1670 u8 reserved_at_5f8[0x3]; 1671 u8 log_max_xrq[0x5]; 1672 1673 u8 affiliate_nic_vport_criteria[0x8]; 1674 u8 native_port_num[0x8]; 1675 u8 num_vhca_ports[0x8]; 1676 u8 flex_parser_id_gtpu_teid[0x4]; 1677 u8 reserved_at_61c[0x2]; 1678 u8 sw_owner_id[0x1]; 1679 u8 reserved_at_61f[0x1]; 1680 1681 u8 max_num_of_monitor_counters[0x10]; 1682 u8 num_ppcnt_monitor_counters[0x10]; 1683 1684 u8 max_num_sf[0x10]; 1685 u8 num_q_monitor_counters[0x10]; 1686 1687 u8 reserved_at_660[0x20]; 1688 1689 u8 sf[0x1]; 1690 u8 sf_set_partition[0x1]; 1691 u8 reserved_at_682[0x1]; 1692 u8 log_max_sf[0x5]; 1693 u8 apu[0x1]; 1694 u8 reserved_at_689[0x7]; 1695 u8 log_min_sf_size[0x8]; 1696 u8 max_num_sf_partitions[0x8]; 1697 1698 u8 uctx_cap[0x20]; 1699 1700 u8 reserved_at_6c0[0x4]; 1701 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1702 u8 flex_parser_id_icmp_dw1[0x4]; 1703 u8 flex_parser_id_icmp_dw0[0x4]; 1704 u8 flex_parser_id_icmpv6_dw1[0x4]; 1705 u8 flex_parser_id_icmpv6_dw0[0x4]; 1706 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1707 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1708 1709 u8 reserved_at_6e0[0x10]; 1710 u8 sf_base_id[0x10]; 1711 1712 u8 flex_parser_id_gtpu_dw_2[0x4]; 1713 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1714 u8 num_total_dynamic_vf_msix[0x18]; 1715 u8 reserved_at_720[0x14]; 1716 u8 dynamic_msix_table_size[0xc]; 1717 u8 reserved_at_740[0xc]; 1718 u8 min_dynamic_vf_msix_table_size[0x4]; 1719 u8 reserved_at_750[0x4]; 1720 u8 max_dynamic_vf_msix_table_size[0xc]; 1721 1722 u8 reserved_at_760[0x20]; 1723 u8 vhca_tunnel_commands[0x40]; 1724 u8 reserved_at_7c0[0x40]; 1725 }; 1726 1727 struct mlx5_ifc_cmd_hca_cap_2_bits { 1728 u8 reserved_at_0[0xa0]; 1729 1730 u8 max_reformat_insert_size[0x8]; 1731 u8 max_reformat_insert_offset[0x8]; 1732 u8 max_reformat_remove_size[0x8]; 1733 u8 max_reformat_remove_offset[0x8]; 1734 1735 u8 reserved_at_c0[0x740]; 1736 }; 1737 1738 enum mlx5_flow_destination_type { 1739 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1740 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1741 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1742 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1743 1744 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1745 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1746 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1747 }; 1748 1749 enum mlx5_flow_table_miss_action { 1750 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1751 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1752 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1753 }; 1754 1755 struct mlx5_ifc_dest_format_struct_bits { 1756 u8 destination_type[0x8]; 1757 u8 destination_id[0x18]; 1758 1759 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1760 u8 packet_reformat[0x1]; 1761 u8 reserved_at_22[0xe]; 1762 u8 destination_eswitch_owner_vhca_id[0x10]; 1763 }; 1764 1765 struct mlx5_ifc_flow_counter_list_bits { 1766 u8 flow_counter_id[0x20]; 1767 1768 u8 reserved_at_20[0x20]; 1769 }; 1770 1771 struct mlx5_ifc_extended_dest_format_bits { 1772 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1773 1774 u8 packet_reformat_id[0x20]; 1775 1776 u8 reserved_at_60[0x20]; 1777 }; 1778 1779 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1780 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1781 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1782 }; 1783 1784 struct mlx5_ifc_fte_match_param_bits { 1785 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1786 1787 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1788 1789 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1790 1791 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1792 1793 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1794 1795 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1796 1797 u8 reserved_at_c00[0x400]; 1798 }; 1799 1800 enum { 1801 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1802 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1803 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1804 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1805 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1806 }; 1807 1808 struct mlx5_ifc_rx_hash_field_select_bits { 1809 u8 l3_prot_type[0x1]; 1810 u8 l4_prot_type[0x1]; 1811 u8 selected_fields[0x1e]; 1812 }; 1813 1814 enum { 1815 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1816 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1817 }; 1818 1819 enum { 1820 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1821 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1822 }; 1823 1824 struct mlx5_ifc_wq_bits { 1825 u8 wq_type[0x4]; 1826 u8 wq_signature[0x1]; 1827 u8 end_padding_mode[0x2]; 1828 u8 cd_slave[0x1]; 1829 u8 reserved_at_8[0x18]; 1830 1831 u8 hds_skip_first_sge[0x1]; 1832 u8 log2_hds_buf_size[0x3]; 1833 u8 reserved_at_24[0x7]; 1834 u8 page_offset[0x5]; 1835 u8 lwm[0x10]; 1836 1837 u8 reserved_at_40[0x8]; 1838 u8 pd[0x18]; 1839 1840 u8 reserved_at_60[0x8]; 1841 u8 uar_page[0x18]; 1842 1843 u8 dbr_addr[0x40]; 1844 1845 u8 hw_counter[0x20]; 1846 1847 u8 sw_counter[0x20]; 1848 1849 u8 reserved_at_100[0xc]; 1850 u8 log_wq_stride[0x4]; 1851 u8 reserved_at_110[0x3]; 1852 u8 log_wq_pg_sz[0x5]; 1853 u8 reserved_at_118[0x3]; 1854 u8 log_wq_sz[0x5]; 1855 1856 u8 dbr_umem_valid[0x1]; 1857 u8 wq_umem_valid[0x1]; 1858 u8 reserved_at_122[0x1]; 1859 u8 log_hairpin_num_packets[0x5]; 1860 u8 reserved_at_128[0x3]; 1861 u8 log_hairpin_data_sz[0x5]; 1862 1863 u8 reserved_at_130[0x4]; 1864 u8 log_wqe_num_of_strides[0x4]; 1865 u8 two_byte_shift_en[0x1]; 1866 u8 reserved_at_139[0x4]; 1867 u8 log_wqe_stride_size[0x3]; 1868 1869 u8 reserved_at_140[0x4c0]; 1870 1871 struct mlx5_ifc_cmd_pas_bits pas[]; 1872 }; 1873 1874 struct mlx5_ifc_rq_num_bits { 1875 u8 reserved_at_0[0x8]; 1876 u8 rq_num[0x18]; 1877 }; 1878 1879 struct mlx5_ifc_mac_address_layout_bits { 1880 u8 reserved_at_0[0x10]; 1881 u8 mac_addr_47_32[0x10]; 1882 1883 u8 mac_addr_31_0[0x20]; 1884 }; 1885 1886 struct mlx5_ifc_vlan_layout_bits { 1887 u8 reserved_at_0[0x14]; 1888 u8 vlan[0x0c]; 1889 1890 u8 reserved_at_20[0x20]; 1891 }; 1892 1893 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1894 u8 reserved_at_0[0xa0]; 1895 1896 u8 min_time_between_cnps[0x20]; 1897 1898 u8 reserved_at_c0[0x12]; 1899 u8 cnp_dscp[0x6]; 1900 u8 reserved_at_d8[0x4]; 1901 u8 cnp_prio_mode[0x1]; 1902 u8 cnp_802p_prio[0x3]; 1903 1904 u8 reserved_at_e0[0x720]; 1905 }; 1906 1907 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1908 u8 reserved_at_0[0x60]; 1909 1910 u8 reserved_at_60[0x4]; 1911 u8 clamp_tgt_rate[0x1]; 1912 u8 reserved_at_65[0x3]; 1913 u8 clamp_tgt_rate_after_time_inc[0x1]; 1914 u8 reserved_at_69[0x17]; 1915 1916 u8 reserved_at_80[0x20]; 1917 1918 u8 rpg_time_reset[0x20]; 1919 1920 u8 rpg_byte_reset[0x20]; 1921 1922 u8 rpg_threshold[0x20]; 1923 1924 u8 rpg_max_rate[0x20]; 1925 1926 u8 rpg_ai_rate[0x20]; 1927 1928 u8 rpg_hai_rate[0x20]; 1929 1930 u8 rpg_gd[0x20]; 1931 1932 u8 rpg_min_dec_fac[0x20]; 1933 1934 u8 rpg_min_rate[0x20]; 1935 1936 u8 reserved_at_1c0[0xe0]; 1937 1938 u8 rate_to_set_on_first_cnp[0x20]; 1939 1940 u8 dce_tcp_g[0x20]; 1941 1942 u8 dce_tcp_rtt[0x20]; 1943 1944 u8 rate_reduce_monitor_period[0x20]; 1945 1946 u8 reserved_at_320[0x20]; 1947 1948 u8 initial_alpha_value[0x20]; 1949 1950 u8 reserved_at_360[0x4a0]; 1951 }; 1952 1953 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1954 u8 reserved_at_0[0x80]; 1955 1956 u8 rppp_max_rps[0x20]; 1957 1958 u8 rpg_time_reset[0x20]; 1959 1960 u8 rpg_byte_reset[0x20]; 1961 1962 u8 rpg_threshold[0x20]; 1963 1964 u8 rpg_max_rate[0x20]; 1965 1966 u8 rpg_ai_rate[0x20]; 1967 1968 u8 rpg_hai_rate[0x20]; 1969 1970 u8 rpg_gd[0x20]; 1971 1972 u8 rpg_min_dec_fac[0x20]; 1973 1974 u8 rpg_min_rate[0x20]; 1975 1976 u8 reserved_at_1c0[0x640]; 1977 }; 1978 1979 enum { 1980 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1981 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1982 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1983 }; 1984 1985 struct mlx5_ifc_resize_field_select_bits { 1986 u8 resize_field_select[0x20]; 1987 }; 1988 1989 struct mlx5_ifc_resource_dump_bits { 1990 u8 more_dump[0x1]; 1991 u8 inline_dump[0x1]; 1992 u8 reserved_at_2[0xa]; 1993 u8 seq_num[0x4]; 1994 u8 segment_type[0x10]; 1995 1996 u8 reserved_at_20[0x10]; 1997 u8 vhca_id[0x10]; 1998 1999 u8 index1[0x20]; 2000 2001 u8 index2[0x20]; 2002 2003 u8 num_of_obj1[0x10]; 2004 u8 num_of_obj2[0x10]; 2005 2006 u8 reserved_at_a0[0x20]; 2007 2008 u8 device_opaque[0x40]; 2009 2010 u8 mkey[0x20]; 2011 2012 u8 size[0x20]; 2013 2014 u8 address[0x40]; 2015 2016 u8 inline_data[52][0x20]; 2017 }; 2018 2019 struct mlx5_ifc_resource_dump_menu_record_bits { 2020 u8 reserved_at_0[0x4]; 2021 u8 num_of_obj2_supports_active[0x1]; 2022 u8 num_of_obj2_supports_all[0x1]; 2023 u8 must_have_num_of_obj2[0x1]; 2024 u8 support_num_of_obj2[0x1]; 2025 u8 num_of_obj1_supports_active[0x1]; 2026 u8 num_of_obj1_supports_all[0x1]; 2027 u8 must_have_num_of_obj1[0x1]; 2028 u8 support_num_of_obj1[0x1]; 2029 u8 must_have_index2[0x1]; 2030 u8 support_index2[0x1]; 2031 u8 must_have_index1[0x1]; 2032 u8 support_index1[0x1]; 2033 u8 segment_type[0x10]; 2034 2035 u8 segment_name[4][0x20]; 2036 2037 u8 index1_name[4][0x20]; 2038 2039 u8 index2_name[4][0x20]; 2040 }; 2041 2042 struct mlx5_ifc_resource_dump_segment_header_bits { 2043 u8 length_dw[0x10]; 2044 u8 segment_type[0x10]; 2045 }; 2046 2047 struct mlx5_ifc_resource_dump_command_segment_bits { 2048 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2049 2050 u8 segment_called[0x10]; 2051 u8 vhca_id[0x10]; 2052 2053 u8 index1[0x20]; 2054 2055 u8 index2[0x20]; 2056 2057 u8 num_of_obj1[0x10]; 2058 u8 num_of_obj2[0x10]; 2059 }; 2060 2061 struct mlx5_ifc_resource_dump_error_segment_bits { 2062 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2063 2064 u8 reserved_at_20[0x10]; 2065 u8 syndrome_id[0x10]; 2066 2067 u8 reserved_at_40[0x40]; 2068 2069 u8 error[8][0x20]; 2070 }; 2071 2072 struct mlx5_ifc_resource_dump_info_segment_bits { 2073 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2074 2075 u8 reserved_at_20[0x18]; 2076 u8 dump_version[0x8]; 2077 2078 u8 hw_version[0x20]; 2079 2080 u8 fw_version[0x20]; 2081 }; 2082 2083 struct mlx5_ifc_resource_dump_menu_segment_bits { 2084 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2085 2086 u8 reserved_at_20[0x10]; 2087 u8 num_of_records[0x10]; 2088 2089 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2090 }; 2091 2092 struct mlx5_ifc_resource_dump_resource_segment_bits { 2093 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2094 2095 u8 reserved_at_20[0x20]; 2096 2097 u8 index1[0x20]; 2098 2099 u8 index2[0x20]; 2100 2101 u8 payload[][0x20]; 2102 }; 2103 2104 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2105 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2106 }; 2107 2108 struct mlx5_ifc_menu_resource_dump_response_bits { 2109 struct mlx5_ifc_resource_dump_info_segment_bits info; 2110 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2111 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2112 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2113 }; 2114 2115 enum { 2116 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2117 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2118 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2119 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2120 }; 2121 2122 struct mlx5_ifc_modify_field_select_bits { 2123 u8 modify_field_select[0x20]; 2124 }; 2125 2126 struct mlx5_ifc_field_select_r_roce_np_bits { 2127 u8 field_select_r_roce_np[0x20]; 2128 }; 2129 2130 struct mlx5_ifc_field_select_r_roce_rp_bits { 2131 u8 field_select_r_roce_rp[0x20]; 2132 }; 2133 2134 enum { 2135 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2136 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2137 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2138 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2139 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2140 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2141 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2142 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2143 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2144 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2145 }; 2146 2147 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2148 u8 field_select_8021qaurp[0x20]; 2149 }; 2150 2151 struct mlx5_ifc_phys_layer_cntrs_bits { 2152 u8 time_since_last_clear_high[0x20]; 2153 2154 u8 time_since_last_clear_low[0x20]; 2155 2156 u8 symbol_errors_high[0x20]; 2157 2158 u8 symbol_errors_low[0x20]; 2159 2160 u8 sync_headers_errors_high[0x20]; 2161 2162 u8 sync_headers_errors_low[0x20]; 2163 2164 u8 edpl_bip_errors_lane0_high[0x20]; 2165 2166 u8 edpl_bip_errors_lane0_low[0x20]; 2167 2168 u8 edpl_bip_errors_lane1_high[0x20]; 2169 2170 u8 edpl_bip_errors_lane1_low[0x20]; 2171 2172 u8 edpl_bip_errors_lane2_high[0x20]; 2173 2174 u8 edpl_bip_errors_lane2_low[0x20]; 2175 2176 u8 edpl_bip_errors_lane3_high[0x20]; 2177 2178 u8 edpl_bip_errors_lane3_low[0x20]; 2179 2180 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2181 2182 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2183 2184 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2185 2186 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2187 2188 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2189 2190 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2191 2192 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2193 2194 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2195 2196 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2197 2198 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2199 2200 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2201 2202 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2203 2204 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2205 2206 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2207 2208 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2209 2210 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2211 2212 u8 rs_fec_corrected_blocks_high[0x20]; 2213 2214 u8 rs_fec_corrected_blocks_low[0x20]; 2215 2216 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2217 2218 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2219 2220 u8 rs_fec_no_errors_blocks_high[0x20]; 2221 2222 u8 rs_fec_no_errors_blocks_low[0x20]; 2223 2224 u8 rs_fec_single_error_blocks_high[0x20]; 2225 2226 u8 rs_fec_single_error_blocks_low[0x20]; 2227 2228 u8 rs_fec_corrected_symbols_total_high[0x20]; 2229 2230 u8 rs_fec_corrected_symbols_total_low[0x20]; 2231 2232 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2233 2234 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2235 2236 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2237 2238 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2239 2240 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2241 2242 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2243 2244 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2245 2246 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2247 2248 u8 link_down_events[0x20]; 2249 2250 u8 successful_recovery_events[0x20]; 2251 2252 u8 reserved_at_640[0x180]; 2253 }; 2254 2255 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2256 u8 time_since_last_clear_high[0x20]; 2257 2258 u8 time_since_last_clear_low[0x20]; 2259 2260 u8 phy_received_bits_high[0x20]; 2261 2262 u8 phy_received_bits_low[0x20]; 2263 2264 u8 phy_symbol_errors_high[0x20]; 2265 2266 u8 phy_symbol_errors_low[0x20]; 2267 2268 u8 phy_corrected_bits_high[0x20]; 2269 2270 u8 phy_corrected_bits_low[0x20]; 2271 2272 u8 phy_corrected_bits_lane0_high[0x20]; 2273 2274 u8 phy_corrected_bits_lane0_low[0x20]; 2275 2276 u8 phy_corrected_bits_lane1_high[0x20]; 2277 2278 u8 phy_corrected_bits_lane1_low[0x20]; 2279 2280 u8 phy_corrected_bits_lane2_high[0x20]; 2281 2282 u8 phy_corrected_bits_lane2_low[0x20]; 2283 2284 u8 phy_corrected_bits_lane3_high[0x20]; 2285 2286 u8 phy_corrected_bits_lane3_low[0x20]; 2287 2288 u8 reserved_at_200[0x5c0]; 2289 }; 2290 2291 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2292 u8 symbol_error_counter[0x10]; 2293 2294 u8 link_error_recovery_counter[0x8]; 2295 2296 u8 link_downed_counter[0x8]; 2297 2298 u8 port_rcv_errors[0x10]; 2299 2300 u8 port_rcv_remote_physical_errors[0x10]; 2301 2302 u8 port_rcv_switch_relay_errors[0x10]; 2303 2304 u8 port_xmit_discards[0x10]; 2305 2306 u8 port_xmit_constraint_errors[0x8]; 2307 2308 u8 port_rcv_constraint_errors[0x8]; 2309 2310 u8 reserved_at_70[0x8]; 2311 2312 u8 link_overrun_errors[0x8]; 2313 2314 u8 reserved_at_80[0x10]; 2315 2316 u8 vl_15_dropped[0x10]; 2317 2318 u8 reserved_at_a0[0x80]; 2319 2320 u8 port_xmit_wait[0x20]; 2321 }; 2322 2323 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2324 u8 transmit_queue_high[0x20]; 2325 2326 u8 transmit_queue_low[0x20]; 2327 2328 u8 no_buffer_discard_uc_high[0x20]; 2329 2330 u8 no_buffer_discard_uc_low[0x20]; 2331 2332 u8 reserved_at_80[0x740]; 2333 }; 2334 2335 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2336 u8 wred_discard_high[0x20]; 2337 2338 u8 wred_discard_low[0x20]; 2339 2340 u8 ecn_marked_tc_high[0x20]; 2341 2342 u8 ecn_marked_tc_low[0x20]; 2343 2344 u8 reserved_at_80[0x740]; 2345 }; 2346 2347 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2348 u8 rx_octets_high[0x20]; 2349 2350 u8 rx_octets_low[0x20]; 2351 2352 u8 reserved_at_40[0xc0]; 2353 2354 u8 rx_frames_high[0x20]; 2355 2356 u8 rx_frames_low[0x20]; 2357 2358 u8 tx_octets_high[0x20]; 2359 2360 u8 tx_octets_low[0x20]; 2361 2362 u8 reserved_at_180[0xc0]; 2363 2364 u8 tx_frames_high[0x20]; 2365 2366 u8 tx_frames_low[0x20]; 2367 2368 u8 rx_pause_high[0x20]; 2369 2370 u8 rx_pause_low[0x20]; 2371 2372 u8 rx_pause_duration_high[0x20]; 2373 2374 u8 rx_pause_duration_low[0x20]; 2375 2376 u8 tx_pause_high[0x20]; 2377 2378 u8 tx_pause_low[0x20]; 2379 2380 u8 tx_pause_duration_high[0x20]; 2381 2382 u8 tx_pause_duration_low[0x20]; 2383 2384 u8 rx_pause_transition_high[0x20]; 2385 2386 u8 rx_pause_transition_low[0x20]; 2387 2388 u8 rx_discards_high[0x20]; 2389 2390 u8 rx_discards_low[0x20]; 2391 2392 u8 device_stall_minor_watermark_cnt_high[0x20]; 2393 2394 u8 device_stall_minor_watermark_cnt_low[0x20]; 2395 2396 u8 device_stall_critical_watermark_cnt_high[0x20]; 2397 2398 u8 device_stall_critical_watermark_cnt_low[0x20]; 2399 2400 u8 reserved_at_480[0x340]; 2401 }; 2402 2403 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2404 u8 port_transmit_wait_high[0x20]; 2405 2406 u8 port_transmit_wait_low[0x20]; 2407 2408 u8 reserved_at_40[0x100]; 2409 2410 u8 rx_buffer_almost_full_high[0x20]; 2411 2412 u8 rx_buffer_almost_full_low[0x20]; 2413 2414 u8 rx_buffer_full_high[0x20]; 2415 2416 u8 rx_buffer_full_low[0x20]; 2417 2418 u8 rx_icrc_encapsulated_high[0x20]; 2419 2420 u8 rx_icrc_encapsulated_low[0x20]; 2421 2422 u8 reserved_at_200[0x5c0]; 2423 }; 2424 2425 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2426 u8 dot3stats_alignment_errors_high[0x20]; 2427 2428 u8 dot3stats_alignment_errors_low[0x20]; 2429 2430 u8 dot3stats_fcs_errors_high[0x20]; 2431 2432 u8 dot3stats_fcs_errors_low[0x20]; 2433 2434 u8 dot3stats_single_collision_frames_high[0x20]; 2435 2436 u8 dot3stats_single_collision_frames_low[0x20]; 2437 2438 u8 dot3stats_multiple_collision_frames_high[0x20]; 2439 2440 u8 dot3stats_multiple_collision_frames_low[0x20]; 2441 2442 u8 dot3stats_sqe_test_errors_high[0x20]; 2443 2444 u8 dot3stats_sqe_test_errors_low[0x20]; 2445 2446 u8 dot3stats_deferred_transmissions_high[0x20]; 2447 2448 u8 dot3stats_deferred_transmissions_low[0x20]; 2449 2450 u8 dot3stats_late_collisions_high[0x20]; 2451 2452 u8 dot3stats_late_collisions_low[0x20]; 2453 2454 u8 dot3stats_excessive_collisions_high[0x20]; 2455 2456 u8 dot3stats_excessive_collisions_low[0x20]; 2457 2458 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2459 2460 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2461 2462 u8 dot3stats_carrier_sense_errors_high[0x20]; 2463 2464 u8 dot3stats_carrier_sense_errors_low[0x20]; 2465 2466 u8 dot3stats_frame_too_longs_high[0x20]; 2467 2468 u8 dot3stats_frame_too_longs_low[0x20]; 2469 2470 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2471 2472 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2473 2474 u8 dot3stats_symbol_errors_high[0x20]; 2475 2476 u8 dot3stats_symbol_errors_low[0x20]; 2477 2478 u8 dot3control_in_unknown_opcodes_high[0x20]; 2479 2480 u8 dot3control_in_unknown_opcodes_low[0x20]; 2481 2482 u8 dot3in_pause_frames_high[0x20]; 2483 2484 u8 dot3in_pause_frames_low[0x20]; 2485 2486 u8 dot3out_pause_frames_high[0x20]; 2487 2488 u8 dot3out_pause_frames_low[0x20]; 2489 2490 u8 reserved_at_400[0x3c0]; 2491 }; 2492 2493 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2494 u8 ether_stats_drop_events_high[0x20]; 2495 2496 u8 ether_stats_drop_events_low[0x20]; 2497 2498 u8 ether_stats_octets_high[0x20]; 2499 2500 u8 ether_stats_octets_low[0x20]; 2501 2502 u8 ether_stats_pkts_high[0x20]; 2503 2504 u8 ether_stats_pkts_low[0x20]; 2505 2506 u8 ether_stats_broadcast_pkts_high[0x20]; 2507 2508 u8 ether_stats_broadcast_pkts_low[0x20]; 2509 2510 u8 ether_stats_multicast_pkts_high[0x20]; 2511 2512 u8 ether_stats_multicast_pkts_low[0x20]; 2513 2514 u8 ether_stats_crc_align_errors_high[0x20]; 2515 2516 u8 ether_stats_crc_align_errors_low[0x20]; 2517 2518 u8 ether_stats_undersize_pkts_high[0x20]; 2519 2520 u8 ether_stats_undersize_pkts_low[0x20]; 2521 2522 u8 ether_stats_oversize_pkts_high[0x20]; 2523 2524 u8 ether_stats_oversize_pkts_low[0x20]; 2525 2526 u8 ether_stats_fragments_high[0x20]; 2527 2528 u8 ether_stats_fragments_low[0x20]; 2529 2530 u8 ether_stats_jabbers_high[0x20]; 2531 2532 u8 ether_stats_jabbers_low[0x20]; 2533 2534 u8 ether_stats_collisions_high[0x20]; 2535 2536 u8 ether_stats_collisions_low[0x20]; 2537 2538 u8 ether_stats_pkts64octets_high[0x20]; 2539 2540 u8 ether_stats_pkts64octets_low[0x20]; 2541 2542 u8 ether_stats_pkts65to127octets_high[0x20]; 2543 2544 u8 ether_stats_pkts65to127octets_low[0x20]; 2545 2546 u8 ether_stats_pkts128to255octets_high[0x20]; 2547 2548 u8 ether_stats_pkts128to255octets_low[0x20]; 2549 2550 u8 ether_stats_pkts256to511octets_high[0x20]; 2551 2552 u8 ether_stats_pkts256to511octets_low[0x20]; 2553 2554 u8 ether_stats_pkts512to1023octets_high[0x20]; 2555 2556 u8 ether_stats_pkts512to1023octets_low[0x20]; 2557 2558 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2559 2560 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2561 2562 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2563 2564 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2565 2566 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2567 2568 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2569 2570 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2571 2572 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2573 2574 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2575 2576 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2577 2578 u8 reserved_at_540[0x280]; 2579 }; 2580 2581 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2582 u8 if_in_octets_high[0x20]; 2583 2584 u8 if_in_octets_low[0x20]; 2585 2586 u8 if_in_ucast_pkts_high[0x20]; 2587 2588 u8 if_in_ucast_pkts_low[0x20]; 2589 2590 u8 if_in_discards_high[0x20]; 2591 2592 u8 if_in_discards_low[0x20]; 2593 2594 u8 if_in_errors_high[0x20]; 2595 2596 u8 if_in_errors_low[0x20]; 2597 2598 u8 if_in_unknown_protos_high[0x20]; 2599 2600 u8 if_in_unknown_protos_low[0x20]; 2601 2602 u8 if_out_octets_high[0x20]; 2603 2604 u8 if_out_octets_low[0x20]; 2605 2606 u8 if_out_ucast_pkts_high[0x20]; 2607 2608 u8 if_out_ucast_pkts_low[0x20]; 2609 2610 u8 if_out_discards_high[0x20]; 2611 2612 u8 if_out_discards_low[0x20]; 2613 2614 u8 if_out_errors_high[0x20]; 2615 2616 u8 if_out_errors_low[0x20]; 2617 2618 u8 if_in_multicast_pkts_high[0x20]; 2619 2620 u8 if_in_multicast_pkts_low[0x20]; 2621 2622 u8 if_in_broadcast_pkts_high[0x20]; 2623 2624 u8 if_in_broadcast_pkts_low[0x20]; 2625 2626 u8 if_out_multicast_pkts_high[0x20]; 2627 2628 u8 if_out_multicast_pkts_low[0x20]; 2629 2630 u8 if_out_broadcast_pkts_high[0x20]; 2631 2632 u8 if_out_broadcast_pkts_low[0x20]; 2633 2634 u8 reserved_at_340[0x480]; 2635 }; 2636 2637 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2638 u8 a_frames_transmitted_ok_high[0x20]; 2639 2640 u8 a_frames_transmitted_ok_low[0x20]; 2641 2642 u8 a_frames_received_ok_high[0x20]; 2643 2644 u8 a_frames_received_ok_low[0x20]; 2645 2646 u8 a_frame_check_sequence_errors_high[0x20]; 2647 2648 u8 a_frame_check_sequence_errors_low[0x20]; 2649 2650 u8 a_alignment_errors_high[0x20]; 2651 2652 u8 a_alignment_errors_low[0x20]; 2653 2654 u8 a_octets_transmitted_ok_high[0x20]; 2655 2656 u8 a_octets_transmitted_ok_low[0x20]; 2657 2658 u8 a_octets_received_ok_high[0x20]; 2659 2660 u8 a_octets_received_ok_low[0x20]; 2661 2662 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2663 2664 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2665 2666 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2667 2668 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2669 2670 u8 a_multicast_frames_received_ok_high[0x20]; 2671 2672 u8 a_multicast_frames_received_ok_low[0x20]; 2673 2674 u8 a_broadcast_frames_received_ok_high[0x20]; 2675 2676 u8 a_broadcast_frames_received_ok_low[0x20]; 2677 2678 u8 a_in_range_length_errors_high[0x20]; 2679 2680 u8 a_in_range_length_errors_low[0x20]; 2681 2682 u8 a_out_of_range_length_field_high[0x20]; 2683 2684 u8 a_out_of_range_length_field_low[0x20]; 2685 2686 u8 a_frame_too_long_errors_high[0x20]; 2687 2688 u8 a_frame_too_long_errors_low[0x20]; 2689 2690 u8 a_symbol_error_during_carrier_high[0x20]; 2691 2692 u8 a_symbol_error_during_carrier_low[0x20]; 2693 2694 u8 a_mac_control_frames_transmitted_high[0x20]; 2695 2696 u8 a_mac_control_frames_transmitted_low[0x20]; 2697 2698 u8 a_mac_control_frames_received_high[0x20]; 2699 2700 u8 a_mac_control_frames_received_low[0x20]; 2701 2702 u8 a_unsupported_opcodes_received_high[0x20]; 2703 2704 u8 a_unsupported_opcodes_received_low[0x20]; 2705 2706 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2707 2708 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2709 2710 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2711 2712 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2713 2714 u8 reserved_at_4c0[0x300]; 2715 }; 2716 2717 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2718 u8 life_time_counter_high[0x20]; 2719 2720 u8 life_time_counter_low[0x20]; 2721 2722 u8 rx_errors[0x20]; 2723 2724 u8 tx_errors[0x20]; 2725 2726 u8 l0_to_recovery_eieos[0x20]; 2727 2728 u8 l0_to_recovery_ts[0x20]; 2729 2730 u8 l0_to_recovery_framing[0x20]; 2731 2732 u8 l0_to_recovery_retrain[0x20]; 2733 2734 u8 crc_error_dllp[0x20]; 2735 2736 u8 crc_error_tlp[0x20]; 2737 2738 u8 tx_overflow_buffer_pkt_high[0x20]; 2739 2740 u8 tx_overflow_buffer_pkt_low[0x20]; 2741 2742 u8 outbound_stalled_reads[0x20]; 2743 2744 u8 outbound_stalled_writes[0x20]; 2745 2746 u8 outbound_stalled_reads_events[0x20]; 2747 2748 u8 outbound_stalled_writes_events[0x20]; 2749 2750 u8 reserved_at_200[0x5c0]; 2751 }; 2752 2753 struct mlx5_ifc_cmd_inter_comp_event_bits { 2754 u8 command_completion_vector[0x20]; 2755 2756 u8 reserved_at_20[0xc0]; 2757 }; 2758 2759 struct mlx5_ifc_stall_vl_event_bits { 2760 u8 reserved_at_0[0x18]; 2761 u8 port_num[0x1]; 2762 u8 reserved_at_19[0x3]; 2763 u8 vl[0x4]; 2764 2765 u8 reserved_at_20[0xa0]; 2766 }; 2767 2768 struct mlx5_ifc_db_bf_congestion_event_bits { 2769 u8 event_subtype[0x8]; 2770 u8 reserved_at_8[0x8]; 2771 u8 congestion_level[0x8]; 2772 u8 reserved_at_18[0x8]; 2773 2774 u8 reserved_at_20[0xa0]; 2775 }; 2776 2777 struct mlx5_ifc_gpio_event_bits { 2778 u8 reserved_at_0[0x60]; 2779 2780 u8 gpio_event_hi[0x20]; 2781 2782 u8 gpio_event_lo[0x20]; 2783 2784 u8 reserved_at_a0[0x40]; 2785 }; 2786 2787 struct mlx5_ifc_port_state_change_event_bits { 2788 u8 reserved_at_0[0x40]; 2789 2790 u8 port_num[0x4]; 2791 u8 reserved_at_44[0x1c]; 2792 2793 u8 reserved_at_60[0x80]; 2794 }; 2795 2796 struct mlx5_ifc_dropped_packet_logged_bits { 2797 u8 reserved_at_0[0xe0]; 2798 }; 2799 2800 enum { 2801 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2802 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2803 }; 2804 2805 struct mlx5_ifc_cq_error_bits { 2806 u8 reserved_at_0[0x8]; 2807 u8 cqn[0x18]; 2808 2809 u8 reserved_at_20[0x20]; 2810 2811 u8 reserved_at_40[0x18]; 2812 u8 syndrome[0x8]; 2813 2814 u8 reserved_at_60[0x80]; 2815 }; 2816 2817 struct mlx5_ifc_rdma_page_fault_event_bits { 2818 u8 bytes_committed[0x20]; 2819 2820 u8 r_key[0x20]; 2821 2822 u8 reserved_at_40[0x10]; 2823 u8 packet_len[0x10]; 2824 2825 u8 rdma_op_len[0x20]; 2826 2827 u8 rdma_va[0x40]; 2828 2829 u8 reserved_at_c0[0x5]; 2830 u8 rdma[0x1]; 2831 u8 write[0x1]; 2832 u8 requestor[0x1]; 2833 u8 qp_number[0x18]; 2834 }; 2835 2836 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2837 u8 bytes_committed[0x20]; 2838 2839 u8 reserved_at_20[0x10]; 2840 u8 wqe_index[0x10]; 2841 2842 u8 reserved_at_40[0x10]; 2843 u8 len[0x10]; 2844 2845 u8 reserved_at_60[0x60]; 2846 2847 u8 reserved_at_c0[0x5]; 2848 u8 rdma[0x1]; 2849 u8 write_read[0x1]; 2850 u8 requestor[0x1]; 2851 u8 qpn[0x18]; 2852 }; 2853 2854 struct mlx5_ifc_qp_events_bits { 2855 u8 reserved_at_0[0xa0]; 2856 2857 u8 type[0x8]; 2858 u8 reserved_at_a8[0x18]; 2859 2860 u8 reserved_at_c0[0x8]; 2861 u8 qpn_rqn_sqn[0x18]; 2862 }; 2863 2864 struct mlx5_ifc_dct_events_bits { 2865 u8 reserved_at_0[0xc0]; 2866 2867 u8 reserved_at_c0[0x8]; 2868 u8 dct_number[0x18]; 2869 }; 2870 2871 struct mlx5_ifc_comp_event_bits { 2872 u8 reserved_at_0[0xc0]; 2873 2874 u8 reserved_at_c0[0x8]; 2875 u8 cq_number[0x18]; 2876 }; 2877 2878 enum { 2879 MLX5_QPC_STATE_RST = 0x0, 2880 MLX5_QPC_STATE_INIT = 0x1, 2881 MLX5_QPC_STATE_RTR = 0x2, 2882 MLX5_QPC_STATE_RTS = 0x3, 2883 MLX5_QPC_STATE_SQER = 0x4, 2884 MLX5_QPC_STATE_ERR = 0x6, 2885 MLX5_QPC_STATE_SQD = 0x7, 2886 MLX5_QPC_STATE_SUSPENDED = 0x9, 2887 }; 2888 2889 enum { 2890 MLX5_QPC_ST_RC = 0x0, 2891 MLX5_QPC_ST_UC = 0x1, 2892 MLX5_QPC_ST_UD = 0x2, 2893 MLX5_QPC_ST_XRC = 0x3, 2894 MLX5_QPC_ST_DCI = 0x5, 2895 MLX5_QPC_ST_QP0 = 0x7, 2896 MLX5_QPC_ST_QP1 = 0x8, 2897 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2898 MLX5_QPC_ST_REG_UMR = 0xc, 2899 }; 2900 2901 enum { 2902 MLX5_QPC_PM_STATE_ARMED = 0x0, 2903 MLX5_QPC_PM_STATE_REARM = 0x1, 2904 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2905 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2906 }; 2907 2908 enum { 2909 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2910 }; 2911 2912 enum { 2913 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2914 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2915 }; 2916 2917 enum { 2918 MLX5_QPC_MTU_256_BYTES = 0x1, 2919 MLX5_QPC_MTU_512_BYTES = 0x2, 2920 MLX5_QPC_MTU_1K_BYTES = 0x3, 2921 MLX5_QPC_MTU_2K_BYTES = 0x4, 2922 MLX5_QPC_MTU_4K_BYTES = 0x5, 2923 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2924 }; 2925 2926 enum { 2927 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2928 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2929 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2930 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2931 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2932 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2933 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2934 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2935 }; 2936 2937 enum { 2938 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2939 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2940 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2941 }; 2942 2943 enum { 2944 MLX5_QPC_CS_RES_DISABLE = 0x0, 2945 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2946 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2947 }; 2948 2949 enum { 2950 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2951 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2952 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2953 }; 2954 2955 struct mlx5_ifc_qpc_bits { 2956 u8 state[0x4]; 2957 u8 lag_tx_port_affinity[0x4]; 2958 u8 st[0x8]; 2959 u8 reserved_at_10[0x2]; 2960 u8 isolate_vl_tc[0x1]; 2961 u8 pm_state[0x2]; 2962 u8 reserved_at_15[0x1]; 2963 u8 req_e2e_credit_mode[0x2]; 2964 u8 offload_type[0x4]; 2965 u8 end_padding_mode[0x2]; 2966 u8 reserved_at_1e[0x2]; 2967 2968 u8 wq_signature[0x1]; 2969 u8 block_lb_mc[0x1]; 2970 u8 atomic_like_write_en[0x1]; 2971 u8 latency_sensitive[0x1]; 2972 u8 reserved_at_24[0x1]; 2973 u8 drain_sigerr[0x1]; 2974 u8 reserved_at_26[0x2]; 2975 u8 pd[0x18]; 2976 2977 u8 mtu[0x3]; 2978 u8 log_msg_max[0x5]; 2979 u8 reserved_at_48[0x1]; 2980 u8 log_rq_size[0x4]; 2981 u8 log_rq_stride[0x3]; 2982 u8 no_sq[0x1]; 2983 u8 log_sq_size[0x4]; 2984 u8 reserved_at_55[0x3]; 2985 u8 ts_format[0x2]; 2986 u8 reserved_at_5a[0x1]; 2987 u8 rlky[0x1]; 2988 u8 ulp_stateless_offload_mode[0x4]; 2989 2990 u8 counter_set_id[0x8]; 2991 u8 uar_page[0x18]; 2992 2993 u8 reserved_at_80[0x8]; 2994 u8 user_index[0x18]; 2995 2996 u8 reserved_at_a0[0x3]; 2997 u8 log_page_size[0x5]; 2998 u8 remote_qpn[0x18]; 2999 3000 struct mlx5_ifc_ads_bits primary_address_path; 3001 3002 struct mlx5_ifc_ads_bits secondary_address_path; 3003 3004 u8 log_ack_req_freq[0x4]; 3005 u8 reserved_at_384[0x4]; 3006 u8 log_sra_max[0x3]; 3007 u8 reserved_at_38b[0x2]; 3008 u8 retry_count[0x3]; 3009 u8 rnr_retry[0x3]; 3010 u8 reserved_at_393[0x1]; 3011 u8 fre[0x1]; 3012 u8 cur_rnr_retry[0x3]; 3013 u8 cur_retry_count[0x3]; 3014 u8 reserved_at_39b[0x5]; 3015 3016 u8 reserved_at_3a0[0x20]; 3017 3018 u8 reserved_at_3c0[0x8]; 3019 u8 next_send_psn[0x18]; 3020 3021 u8 reserved_at_3e0[0x8]; 3022 u8 cqn_snd[0x18]; 3023 3024 u8 reserved_at_400[0x8]; 3025 u8 deth_sqpn[0x18]; 3026 3027 u8 reserved_at_420[0x20]; 3028 3029 u8 reserved_at_440[0x8]; 3030 u8 last_acked_psn[0x18]; 3031 3032 u8 reserved_at_460[0x8]; 3033 u8 ssn[0x18]; 3034 3035 u8 reserved_at_480[0x8]; 3036 u8 log_rra_max[0x3]; 3037 u8 reserved_at_48b[0x1]; 3038 u8 atomic_mode[0x4]; 3039 u8 rre[0x1]; 3040 u8 rwe[0x1]; 3041 u8 rae[0x1]; 3042 u8 reserved_at_493[0x1]; 3043 u8 page_offset[0x6]; 3044 u8 reserved_at_49a[0x3]; 3045 u8 cd_slave_receive[0x1]; 3046 u8 cd_slave_send[0x1]; 3047 u8 cd_master[0x1]; 3048 3049 u8 reserved_at_4a0[0x3]; 3050 u8 min_rnr_nak[0x5]; 3051 u8 next_rcv_psn[0x18]; 3052 3053 u8 reserved_at_4c0[0x8]; 3054 u8 xrcd[0x18]; 3055 3056 u8 reserved_at_4e0[0x8]; 3057 u8 cqn_rcv[0x18]; 3058 3059 u8 dbr_addr[0x40]; 3060 3061 u8 q_key[0x20]; 3062 3063 u8 reserved_at_560[0x5]; 3064 u8 rq_type[0x3]; 3065 u8 srqn_rmpn_xrqn[0x18]; 3066 3067 u8 reserved_at_580[0x8]; 3068 u8 rmsn[0x18]; 3069 3070 u8 hw_sq_wqebb_counter[0x10]; 3071 u8 sw_sq_wqebb_counter[0x10]; 3072 3073 u8 hw_rq_counter[0x20]; 3074 3075 u8 sw_rq_counter[0x20]; 3076 3077 u8 reserved_at_600[0x20]; 3078 3079 u8 reserved_at_620[0xf]; 3080 u8 cgs[0x1]; 3081 u8 cs_req[0x8]; 3082 u8 cs_res[0x8]; 3083 3084 u8 dc_access_key[0x40]; 3085 3086 u8 reserved_at_680[0x3]; 3087 u8 dbr_umem_valid[0x1]; 3088 3089 u8 reserved_at_684[0xbc]; 3090 }; 3091 3092 struct mlx5_ifc_roce_addr_layout_bits { 3093 u8 source_l3_address[16][0x8]; 3094 3095 u8 reserved_at_80[0x3]; 3096 u8 vlan_valid[0x1]; 3097 u8 vlan_id[0xc]; 3098 u8 source_mac_47_32[0x10]; 3099 3100 u8 source_mac_31_0[0x20]; 3101 3102 u8 reserved_at_c0[0x14]; 3103 u8 roce_l3_type[0x4]; 3104 u8 roce_version[0x8]; 3105 3106 u8 reserved_at_e0[0x20]; 3107 }; 3108 3109 union mlx5_ifc_hca_cap_union_bits { 3110 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3111 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3112 struct mlx5_ifc_odp_cap_bits odp_cap; 3113 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3114 struct mlx5_ifc_roce_cap_bits roce_cap; 3115 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3116 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3117 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3118 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3119 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3120 struct mlx5_ifc_qos_cap_bits qos_cap; 3121 struct mlx5_ifc_debug_cap_bits debug_cap; 3122 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3123 struct mlx5_ifc_tls_cap_bits tls_cap; 3124 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3125 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3126 u8 reserved_at_0[0x8000]; 3127 }; 3128 3129 enum { 3130 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3131 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3132 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3133 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3134 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3135 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3136 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3137 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3138 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3139 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3140 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3141 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3142 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3143 }; 3144 3145 enum { 3146 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3147 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3148 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3149 }; 3150 3151 struct mlx5_ifc_vlan_bits { 3152 u8 ethtype[0x10]; 3153 u8 prio[0x3]; 3154 u8 cfi[0x1]; 3155 u8 vid[0xc]; 3156 }; 3157 3158 struct mlx5_ifc_flow_context_bits { 3159 struct mlx5_ifc_vlan_bits push_vlan; 3160 3161 u8 group_id[0x20]; 3162 3163 u8 reserved_at_40[0x8]; 3164 u8 flow_tag[0x18]; 3165 3166 u8 reserved_at_60[0x10]; 3167 u8 action[0x10]; 3168 3169 u8 extended_destination[0x1]; 3170 u8 reserved_at_81[0x1]; 3171 u8 flow_source[0x2]; 3172 u8 reserved_at_84[0x4]; 3173 u8 destination_list_size[0x18]; 3174 3175 u8 reserved_at_a0[0x8]; 3176 u8 flow_counter_list_size[0x18]; 3177 3178 u8 packet_reformat_id[0x20]; 3179 3180 u8 modify_header_id[0x20]; 3181 3182 struct mlx5_ifc_vlan_bits push_vlan_2; 3183 3184 u8 ipsec_obj_id[0x20]; 3185 u8 reserved_at_140[0xc0]; 3186 3187 struct mlx5_ifc_fte_match_param_bits match_value; 3188 3189 u8 reserved_at_1200[0x600]; 3190 3191 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3192 }; 3193 3194 enum { 3195 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3196 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3197 }; 3198 3199 struct mlx5_ifc_xrc_srqc_bits { 3200 u8 state[0x4]; 3201 u8 log_xrc_srq_size[0x4]; 3202 u8 reserved_at_8[0x18]; 3203 3204 u8 wq_signature[0x1]; 3205 u8 cont_srq[0x1]; 3206 u8 reserved_at_22[0x1]; 3207 u8 rlky[0x1]; 3208 u8 basic_cyclic_rcv_wqe[0x1]; 3209 u8 log_rq_stride[0x3]; 3210 u8 xrcd[0x18]; 3211 3212 u8 page_offset[0x6]; 3213 u8 reserved_at_46[0x1]; 3214 u8 dbr_umem_valid[0x1]; 3215 u8 cqn[0x18]; 3216 3217 u8 reserved_at_60[0x20]; 3218 3219 u8 user_index_equal_xrc_srqn[0x1]; 3220 u8 reserved_at_81[0x1]; 3221 u8 log_page_size[0x6]; 3222 u8 user_index[0x18]; 3223 3224 u8 reserved_at_a0[0x20]; 3225 3226 u8 reserved_at_c0[0x8]; 3227 u8 pd[0x18]; 3228 3229 u8 lwm[0x10]; 3230 u8 wqe_cnt[0x10]; 3231 3232 u8 reserved_at_100[0x40]; 3233 3234 u8 db_record_addr_h[0x20]; 3235 3236 u8 db_record_addr_l[0x1e]; 3237 u8 reserved_at_17e[0x2]; 3238 3239 u8 reserved_at_180[0x80]; 3240 }; 3241 3242 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3243 u8 counter_error_queues[0x20]; 3244 3245 u8 total_error_queues[0x20]; 3246 3247 u8 send_queue_priority_update_flow[0x20]; 3248 3249 u8 reserved_at_60[0x20]; 3250 3251 u8 nic_receive_steering_discard[0x40]; 3252 3253 u8 receive_discard_vport_down[0x40]; 3254 3255 u8 transmit_discard_vport_down[0x40]; 3256 3257 u8 reserved_at_140[0xa0]; 3258 3259 u8 internal_rq_out_of_buffer[0x20]; 3260 3261 u8 reserved_at_200[0xe00]; 3262 }; 3263 3264 struct mlx5_ifc_traffic_counter_bits { 3265 u8 packets[0x40]; 3266 3267 u8 octets[0x40]; 3268 }; 3269 3270 struct mlx5_ifc_tisc_bits { 3271 u8 strict_lag_tx_port_affinity[0x1]; 3272 u8 tls_en[0x1]; 3273 u8 reserved_at_2[0x2]; 3274 u8 lag_tx_port_affinity[0x04]; 3275 3276 u8 reserved_at_8[0x4]; 3277 u8 prio[0x4]; 3278 u8 reserved_at_10[0x10]; 3279 3280 u8 reserved_at_20[0x100]; 3281 3282 u8 reserved_at_120[0x8]; 3283 u8 transport_domain[0x18]; 3284 3285 u8 reserved_at_140[0x8]; 3286 u8 underlay_qpn[0x18]; 3287 3288 u8 reserved_at_160[0x8]; 3289 u8 pd[0x18]; 3290 3291 u8 reserved_at_180[0x380]; 3292 }; 3293 3294 enum { 3295 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3296 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3297 }; 3298 3299 enum { 3300 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3301 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3302 }; 3303 3304 enum { 3305 MLX5_RX_HASH_FN_NONE = 0x0, 3306 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3307 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3308 }; 3309 3310 enum { 3311 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3312 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3313 }; 3314 3315 struct mlx5_ifc_tirc_bits { 3316 u8 reserved_at_0[0x20]; 3317 3318 u8 disp_type[0x4]; 3319 u8 tls_en[0x1]; 3320 u8 reserved_at_25[0x1b]; 3321 3322 u8 reserved_at_40[0x40]; 3323 3324 u8 reserved_at_80[0x4]; 3325 u8 lro_timeout_period_usecs[0x10]; 3326 u8 lro_enable_mask[0x4]; 3327 u8 lro_max_ip_payload_size[0x8]; 3328 3329 u8 reserved_at_a0[0x40]; 3330 3331 u8 reserved_at_e0[0x8]; 3332 u8 inline_rqn[0x18]; 3333 3334 u8 rx_hash_symmetric[0x1]; 3335 u8 reserved_at_101[0x1]; 3336 u8 tunneled_offload_en[0x1]; 3337 u8 reserved_at_103[0x5]; 3338 u8 indirect_table[0x18]; 3339 3340 u8 rx_hash_fn[0x4]; 3341 u8 reserved_at_124[0x2]; 3342 u8 self_lb_block[0x2]; 3343 u8 transport_domain[0x18]; 3344 3345 u8 rx_hash_toeplitz_key[10][0x20]; 3346 3347 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3348 3349 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3350 3351 u8 reserved_at_2c0[0x4c0]; 3352 }; 3353 3354 enum { 3355 MLX5_SRQC_STATE_GOOD = 0x0, 3356 MLX5_SRQC_STATE_ERROR = 0x1, 3357 }; 3358 3359 struct mlx5_ifc_srqc_bits { 3360 u8 state[0x4]; 3361 u8 log_srq_size[0x4]; 3362 u8 reserved_at_8[0x18]; 3363 3364 u8 wq_signature[0x1]; 3365 u8 cont_srq[0x1]; 3366 u8 reserved_at_22[0x1]; 3367 u8 rlky[0x1]; 3368 u8 reserved_at_24[0x1]; 3369 u8 log_rq_stride[0x3]; 3370 u8 xrcd[0x18]; 3371 3372 u8 page_offset[0x6]; 3373 u8 reserved_at_46[0x2]; 3374 u8 cqn[0x18]; 3375 3376 u8 reserved_at_60[0x20]; 3377 3378 u8 reserved_at_80[0x2]; 3379 u8 log_page_size[0x6]; 3380 u8 reserved_at_88[0x18]; 3381 3382 u8 reserved_at_a0[0x20]; 3383 3384 u8 reserved_at_c0[0x8]; 3385 u8 pd[0x18]; 3386 3387 u8 lwm[0x10]; 3388 u8 wqe_cnt[0x10]; 3389 3390 u8 reserved_at_100[0x40]; 3391 3392 u8 dbr_addr[0x40]; 3393 3394 u8 reserved_at_180[0x80]; 3395 }; 3396 3397 enum { 3398 MLX5_SQC_STATE_RST = 0x0, 3399 MLX5_SQC_STATE_RDY = 0x1, 3400 MLX5_SQC_STATE_ERR = 0x3, 3401 }; 3402 3403 struct mlx5_ifc_sqc_bits { 3404 u8 rlky[0x1]; 3405 u8 cd_master[0x1]; 3406 u8 fre[0x1]; 3407 u8 flush_in_error_en[0x1]; 3408 u8 allow_multi_pkt_send_wqe[0x1]; 3409 u8 min_wqe_inline_mode[0x3]; 3410 u8 state[0x4]; 3411 u8 reg_umr[0x1]; 3412 u8 allow_swp[0x1]; 3413 u8 hairpin[0x1]; 3414 u8 reserved_at_f[0xb]; 3415 u8 ts_format[0x2]; 3416 u8 reserved_at_1c[0x4]; 3417 3418 u8 reserved_at_20[0x8]; 3419 u8 user_index[0x18]; 3420 3421 u8 reserved_at_40[0x8]; 3422 u8 cqn[0x18]; 3423 3424 u8 reserved_at_60[0x8]; 3425 u8 hairpin_peer_rq[0x18]; 3426 3427 u8 reserved_at_80[0x10]; 3428 u8 hairpin_peer_vhca[0x10]; 3429 3430 u8 reserved_at_a0[0x20]; 3431 3432 u8 reserved_at_c0[0x8]; 3433 u8 ts_cqe_to_dest_cqn[0x18]; 3434 3435 u8 reserved_at_e0[0x10]; 3436 u8 packet_pacing_rate_limit_index[0x10]; 3437 u8 tis_lst_sz[0x10]; 3438 u8 qos_queue_group_id[0x10]; 3439 3440 u8 reserved_at_120[0x40]; 3441 3442 u8 reserved_at_160[0x8]; 3443 u8 tis_num_0[0x18]; 3444 3445 struct mlx5_ifc_wq_bits wq; 3446 }; 3447 3448 enum { 3449 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3450 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3451 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3452 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3453 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3454 }; 3455 3456 enum { 3457 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3458 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3459 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3460 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3461 }; 3462 3463 struct mlx5_ifc_scheduling_context_bits { 3464 u8 element_type[0x8]; 3465 u8 reserved_at_8[0x18]; 3466 3467 u8 element_attributes[0x20]; 3468 3469 u8 parent_element_id[0x20]; 3470 3471 u8 reserved_at_60[0x40]; 3472 3473 u8 bw_share[0x20]; 3474 3475 u8 max_average_bw[0x20]; 3476 3477 u8 reserved_at_e0[0x120]; 3478 }; 3479 3480 struct mlx5_ifc_rqtc_bits { 3481 u8 reserved_at_0[0xa0]; 3482 3483 u8 reserved_at_a0[0x5]; 3484 u8 list_q_type[0x3]; 3485 u8 reserved_at_a8[0x8]; 3486 u8 rqt_max_size[0x10]; 3487 3488 u8 rq_vhca_id_format[0x1]; 3489 u8 reserved_at_c1[0xf]; 3490 u8 rqt_actual_size[0x10]; 3491 3492 u8 reserved_at_e0[0x6a0]; 3493 3494 struct mlx5_ifc_rq_num_bits rq_num[]; 3495 }; 3496 3497 enum { 3498 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3499 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3500 }; 3501 3502 enum { 3503 MLX5_RQC_STATE_RST = 0x0, 3504 MLX5_RQC_STATE_RDY = 0x1, 3505 MLX5_RQC_STATE_ERR = 0x3, 3506 }; 3507 3508 struct mlx5_ifc_rqc_bits { 3509 u8 rlky[0x1]; 3510 u8 delay_drop_en[0x1]; 3511 u8 scatter_fcs[0x1]; 3512 u8 vsd[0x1]; 3513 u8 mem_rq_type[0x4]; 3514 u8 state[0x4]; 3515 u8 reserved_at_c[0x1]; 3516 u8 flush_in_error_en[0x1]; 3517 u8 hairpin[0x1]; 3518 u8 reserved_at_f[0xb]; 3519 u8 ts_format[0x2]; 3520 u8 reserved_at_1c[0x4]; 3521 3522 u8 reserved_at_20[0x8]; 3523 u8 user_index[0x18]; 3524 3525 u8 reserved_at_40[0x8]; 3526 u8 cqn[0x18]; 3527 3528 u8 counter_set_id[0x8]; 3529 u8 reserved_at_68[0x18]; 3530 3531 u8 reserved_at_80[0x8]; 3532 u8 rmpn[0x18]; 3533 3534 u8 reserved_at_a0[0x8]; 3535 u8 hairpin_peer_sq[0x18]; 3536 3537 u8 reserved_at_c0[0x10]; 3538 u8 hairpin_peer_vhca[0x10]; 3539 3540 u8 reserved_at_e0[0xa0]; 3541 3542 struct mlx5_ifc_wq_bits wq; 3543 }; 3544 3545 enum { 3546 MLX5_RMPC_STATE_RDY = 0x1, 3547 MLX5_RMPC_STATE_ERR = 0x3, 3548 }; 3549 3550 struct mlx5_ifc_rmpc_bits { 3551 u8 reserved_at_0[0x8]; 3552 u8 state[0x4]; 3553 u8 reserved_at_c[0x14]; 3554 3555 u8 basic_cyclic_rcv_wqe[0x1]; 3556 u8 reserved_at_21[0x1f]; 3557 3558 u8 reserved_at_40[0x140]; 3559 3560 struct mlx5_ifc_wq_bits wq; 3561 }; 3562 3563 struct mlx5_ifc_nic_vport_context_bits { 3564 u8 reserved_at_0[0x5]; 3565 u8 min_wqe_inline_mode[0x3]; 3566 u8 reserved_at_8[0x15]; 3567 u8 disable_mc_local_lb[0x1]; 3568 u8 disable_uc_local_lb[0x1]; 3569 u8 roce_en[0x1]; 3570 3571 u8 arm_change_event[0x1]; 3572 u8 reserved_at_21[0x1a]; 3573 u8 event_on_mtu[0x1]; 3574 u8 event_on_promisc_change[0x1]; 3575 u8 event_on_vlan_change[0x1]; 3576 u8 event_on_mc_address_change[0x1]; 3577 u8 event_on_uc_address_change[0x1]; 3578 3579 u8 reserved_at_40[0xc]; 3580 3581 u8 affiliation_criteria[0x4]; 3582 u8 affiliated_vhca_id[0x10]; 3583 3584 u8 reserved_at_60[0xd0]; 3585 3586 u8 mtu[0x10]; 3587 3588 u8 system_image_guid[0x40]; 3589 u8 port_guid[0x40]; 3590 u8 node_guid[0x40]; 3591 3592 u8 reserved_at_200[0x140]; 3593 u8 qkey_violation_counter[0x10]; 3594 u8 reserved_at_350[0x430]; 3595 3596 u8 promisc_uc[0x1]; 3597 u8 promisc_mc[0x1]; 3598 u8 promisc_all[0x1]; 3599 u8 reserved_at_783[0x2]; 3600 u8 allowed_list_type[0x3]; 3601 u8 reserved_at_788[0xc]; 3602 u8 allowed_list_size[0xc]; 3603 3604 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3605 3606 u8 reserved_at_7e0[0x20]; 3607 3608 u8 current_uc_mac_address[][0x40]; 3609 }; 3610 3611 enum { 3612 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3613 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3614 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3615 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3616 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3617 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3618 }; 3619 3620 struct mlx5_ifc_mkc_bits { 3621 u8 reserved_at_0[0x1]; 3622 u8 free[0x1]; 3623 u8 reserved_at_2[0x1]; 3624 u8 access_mode_4_2[0x3]; 3625 u8 reserved_at_6[0x7]; 3626 u8 relaxed_ordering_write[0x1]; 3627 u8 reserved_at_e[0x1]; 3628 u8 small_fence_on_rdma_read_response[0x1]; 3629 u8 umr_en[0x1]; 3630 u8 a[0x1]; 3631 u8 rw[0x1]; 3632 u8 rr[0x1]; 3633 u8 lw[0x1]; 3634 u8 lr[0x1]; 3635 u8 access_mode_1_0[0x2]; 3636 u8 reserved_at_18[0x8]; 3637 3638 u8 qpn[0x18]; 3639 u8 mkey_7_0[0x8]; 3640 3641 u8 reserved_at_40[0x20]; 3642 3643 u8 length64[0x1]; 3644 u8 bsf_en[0x1]; 3645 u8 sync_umr[0x1]; 3646 u8 reserved_at_63[0x2]; 3647 u8 expected_sigerr_count[0x1]; 3648 u8 reserved_at_66[0x1]; 3649 u8 en_rinval[0x1]; 3650 u8 pd[0x18]; 3651 3652 u8 start_addr[0x40]; 3653 3654 u8 len[0x40]; 3655 3656 u8 bsf_octword_size[0x20]; 3657 3658 u8 reserved_at_120[0x80]; 3659 3660 u8 translations_octword_size[0x20]; 3661 3662 u8 reserved_at_1c0[0x19]; 3663 u8 relaxed_ordering_read[0x1]; 3664 u8 reserved_at_1d9[0x1]; 3665 u8 log_page_size[0x5]; 3666 3667 u8 reserved_at_1e0[0x20]; 3668 }; 3669 3670 struct mlx5_ifc_pkey_bits { 3671 u8 reserved_at_0[0x10]; 3672 u8 pkey[0x10]; 3673 }; 3674 3675 struct mlx5_ifc_array128_auto_bits { 3676 u8 array128_auto[16][0x8]; 3677 }; 3678 3679 struct mlx5_ifc_hca_vport_context_bits { 3680 u8 field_select[0x20]; 3681 3682 u8 reserved_at_20[0xe0]; 3683 3684 u8 sm_virt_aware[0x1]; 3685 u8 has_smi[0x1]; 3686 u8 has_raw[0x1]; 3687 u8 grh_required[0x1]; 3688 u8 reserved_at_104[0xc]; 3689 u8 port_physical_state[0x4]; 3690 u8 vport_state_policy[0x4]; 3691 u8 port_state[0x4]; 3692 u8 vport_state[0x4]; 3693 3694 u8 reserved_at_120[0x20]; 3695 3696 u8 system_image_guid[0x40]; 3697 3698 u8 port_guid[0x40]; 3699 3700 u8 node_guid[0x40]; 3701 3702 u8 cap_mask1[0x20]; 3703 3704 u8 cap_mask1_field_select[0x20]; 3705 3706 u8 cap_mask2[0x20]; 3707 3708 u8 cap_mask2_field_select[0x20]; 3709 3710 u8 reserved_at_280[0x80]; 3711 3712 u8 lid[0x10]; 3713 u8 reserved_at_310[0x4]; 3714 u8 init_type_reply[0x4]; 3715 u8 lmc[0x3]; 3716 u8 subnet_timeout[0x5]; 3717 3718 u8 sm_lid[0x10]; 3719 u8 sm_sl[0x4]; 3720 u8 reserved_at_334[0xc]; 3721 3722 u8 qkey_violation_counter[0x10]; 3723 u8 pkey_violation_counter[0x10]; 3724 3725 u8 reserved_at_360[0xca0]; 3726 }; 3727 3728 struct mlx5_ifc_esw_vport_context_bits { 3729 u8 fdb_to_vport_reg_c[0x1]; 3730 u8 reserved_at_1[0x2]; 3731 u8 vport_svlan_strip[0x1]; 3732 u8 vport_cvlan_strip[0x1]; 3733 u8 vport_svlan_insert[0x1]; 3734 u8 vport_cvlan_insert[0x2]; 3735 u8 fdb_to_vport_reg_c_id[0x8]; 3736 u8 reserved_at_10[0x10]; 3737 3738 u8 reserved_at_20[0x20]; 3739 3740 u8 svlan_cfi[0x1]; 3741 u8 svlan_pcp[0x3]; 3742 u8 svlan_id[0xc]; 3743 u8 cvlan_cfi[0x1]; 3744 u8 cvlan_pcp[0x3]; 3745 u8 cvlan_id[0xc]; 3746 3747 u8 reserved_at_60[0x720]; 3748 3749 u8 sw_steering_vport_icm_address_rx[0x40]; 3750 3751 u8 sw_steering_vport_icm_address_tx[0x40]; 3752 }; 3753 3754 enum { 3755 MLX5_EQC_STATUS_OK = 0x0, 3756 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3757 }; 3758 3759 enum { 3760 MLX5_EQC_ST_ARMED = 0x9, 3761 MLX5_EQC_ST_FIRED = 0xa, 3762 }; 3763 3764 struct mlx5_ifc_eqc_bits { 3765 u8 status[0x4]; 3766 u8 reserved_at_4[0x9]; 3767 u8 ec[0x1]; 3768 u8 oi[0x1]; 3769 u8 reserved_at_f[0x5]; 3770 u8 st[0x4]; 3771 u8 reserved_at_18[0x8]; 3772 3773 u8 reserved_at_20[0x20]; 3774 3775 u8 reserved_at_40[0x14]; 3776 u8 page_offset[0x6]; 3777 u8 reserved_at_5a[0x6]; 3778 3779 u8 reserved_at_60[0x3]; 3780 u8 log_eq_size[0x5]; 3781 u8 uar_page[0x18]; 3782 3783 u8 reserved_at_80[0x20]; 3784 3785 u8 reserved_at_a0[0x14]; 3786 u8 intr[0xc]; 3787 3788 u8 reserved_at_c0[0x3]; 3789 u8 log_page_size[0x5]; 3790 u8 reserved_at_c8[0x18]; 3791 3792 u8 reserved_at_e0[0x60]; 3793 3794 u8 reserved_at_140[0x8]; 3795 u8 consumer_counter[0x18]; 3796 3797 u8 reserved_at_160[0x8]; 3798 u8 producer_counter[0x18]; 3799 3800 u8 reserved_at_180[0x80]; 3801 }; 3802 3803 enum { 3804 MLX5_DCTC_STATE_ACTIVE = 0x0, 3805 MLX5_DCTC_STATE_DRAINING = 0x1, 3806 MLX5_DCTC_STATE_DRAINED = 0x2, 3807 }; 3808 3809 enum { 3810 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3811 MLX5_DCTC_CS_RES_NA = 0x1, 3812 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3813 }; 3814 3815 enum { 3816 MLX5_DCTC_MTU_256_BYTES = 0x1, 3817 MLX5_DCTC_MTU_512_BYTES = 0x2, 3818 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3819 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3820 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3821 }; 3822 3823 struct mlx5_ifc_dctc_bits { 3824 u8 reserved_at_0[0x4]; 3825 u8 state[0x4]; 3826 u8 reserved_at_8[0x18]; 3827 3828 u8 reserved_at_20[0x8]; 3829 u8 user_index[0x18]; 3830 3831 u8 reserved_at_40[0x8]; 3832 u8 cqn[0x18]; 3833 3834 u8 counter_set_id[0x8]; 3835 u8 atomic_mode[0x4]; 3836 u8 rre[0x1]; 3837 u8 rwe[0x1]; 3838 u8 rae[0x1]; 3839 u8 atomic_like_write_en[0x1]; 3840 u8 latency_sensitive[0x1]; 3841 u8 rlky[0x1]; 3842 u8 free_ar[0x1]; 3843 u8 reserved_at_73[0xd]; 3844 3845 u8 reserved_at_80[0x8]; 3846 u8 cs_res[0x8]; 3847 u8 reserved_at_90[0x3]; 3848 u8 min_rnr_nak[0x5]; 3849 u8 reserved_at_98[0x8]; 3850 3851 u8 reserved_at_a0[0x8]; 3852 u8 srqn_xrqn[0x18]; 3853 3854 u8 reserved_at_c0[0x8]; 3855 u8 pd[0x18]; 3856 3857 u8 tclass[0x8]; 3858 u8 reserved_at_e8[0x4]; 3859 u8 flow_label[0x14]; 3860 3861 u8 dc_access_key[0x40]; 3862 3863 u8 reserved_at_140[0x5]; 3864 u8 mtu[0x3]; 3865 u8 port[0x8]; 3866 u8 pkey_index[0x10]; 3867 3868 u8 reserved_at_160[0x8]; 3869 u8 my_addr_index[0x8]; 3870 u8 reserved_at_170[0x8]; 3871 u8 hop_limit[0x8]; 3872 3873 u8 dc_access_key_violation_count[0x20]; 3874 3875 u8 reserved_at_1a0[0x14]; 3876 u8 dei_cfi[0x1]; 3877 u8 eth_prio[0x3]; 3878 u8 ecn[0x2]; 3879 u8 dscp[0x6]; 3880 3881 u8 reserved_at_1c0[0x20]; 3882 u8 ece[0x20]; 3883 }; 3884 3885 enum { 3886 MLX5_CQC_STATUS_OK = 0x0, 3887 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3888 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3889 }; 3890 3891 enum { 3892 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3893 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3894 }; 3895 3896 enum { 3897 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3898 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3899 MLX5_CQC_ST_FIRED = 0xa, 3900 }; 3901 3902 enum { 3903 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3904 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3905 MLX5_CQ_PERIOD_NUM_MODES 3906 }; 3907 3908 struct mlx5_ifc_cqc_bits { 3909 u8 status[0x4]; 3910 u8 reserved_at_4[0x2]; 3911 u8 dbr_umem_valid[0x1]; 3912 u8 apu_thread_cq[0x1]; 3913 u8 cqe_sz[0x3]; 3914 u8 cc[0x1]; 3915 u8 reserved_at_c[0x1]; 3916 u8 scqe_break_moderation_en[0x1]; 3917 u8 oi[0x1]; 3918 u8 cq_period_mode[0x2]; 3919 u8 cqe_comp_en[0x1]; 3920 u8 mini_cqe_res_format[0x2]; 3921 u8 st[0x4]; 3922 u8 reserved_at_18[0x8]; 3923 3924 u8 reserved_at_20[0x20]; 3925 3926 u8 reserved_at_40[0x14]; 3927 u8 page_offset[0x6]; 3928 u8 reserved_at_5a[0x6]; 3929 3930 u8 reserved_at_60[0x3]; 3931 u8 log_cq_size[0x5]; 3932 u8 uar_page[0x18]; 3933 3934 u8 reserved_at_80[0x4]; 3935 u8 cq_period[0xc]; 3936 u8 cq_max_count[0x10]; 3937 3938 u8 reserved_at_a0[0x18]; 3939 u8 c_eqn[0x8]; 3940 3941 u8 reserved_at_c0[0x3]; 3942 u8 log_page_size[0x5]; 3943 u8 reserved_at_c8[0x18]; 3944 3945 u8 reserved_at_e0[0x20]; 3946 3947 u8 reserved_at_100[0x8]; 3948 u8 last_notified_index[0x18]; 3949 3950 u8 reserved_at_120[0x8]; 3951 u8 last_solicit_index[0x18]; 3952 3953 u8 reserved_at_140[0x8]; 3954 u8 consumer_counter[0x18]; 3955 3956 u8 reserved_at_160[0x8]; 3957 u8 producer_counter[0x18]; 3958 3959 u8 reserved_at_180[0x40]; 3960 3961 u8 dbr_addr[0x40]; 3962 }; 3963 3964 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3965 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3966 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3967 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3968 u8 reserved_at_0[0x800]; 3969 }; 3970 3971 struct mlx5_ifc_query_adapter_param_block_bits { 3972 u8 reserved_at_0[0xc0]; 3973 3974 u8 reserved_at_c0[0x8]; 3975 u8 ieee_vendor_id[0x18]; 3976 3977 u8 reserved_at_e0[0x10]; 3978 u8 vsd_vendor_id[0x10]; 3979 3980 u8 vsd[208][0x8]; 3981 3982 u8 vsd_contd_psid[16][0x8]; 3983 }; 3984 3985 enum { 3986 MLX5_XRQC_STATE_GOOD = 0x0, 3987 MLX5_XRQC_STATE_ERROR = 0x1, 3988 }; 3989 3990 enum { 3991 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3992 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3993 }; 3994 3995 enum { 3996 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3997 }; 3998 3999 struct mlx5_ifc_tag_matching_topology_context_bits { 4000 u8 log_matching_list_sz[0x4]; 4001 u8 reserved_at_4[0xc]; 4002 u8 append_next_index[0x10]; 4003 4004 u8 sw_phase_cnt[0x10]; 4005 u8 hw_phase_cnt[0x10]; 4006 4007 u8 reserved_at_40[0x40]; 4008 }; 4009 4010 struct mlx5_ifc_xrqc_bits { 4011 u8 state[0x4]; 4012 u8 rlkey[0x1]; 4013 u8 reserved_at_5[0xf]; 4014 u8 topology[0x4]; 4015 u8 reserved_at_18[0x4]; 4016 u8 offload[0x4]; 4017 4018 u8 reserved_at_20[0x8]; 4019 u8 user_index[0x18]; 4020 4021 u8 reserved_at_40[0x8]; 4022 u8 cqn[0x18]; 4023 4024 u8 reserved_at_60[0xa0]; 4025 4026 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4027 4028 u8 reserved_at_180[0x280]; 4029 4030 struct mlx5_ifc_wq_bits wq; 4031 }; 4032 4033 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4034 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4035 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4036 u8 reserved_at_0[0x20]; 4037 }; 4038 4039 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4040 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4041 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4042 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4043 u8 reserved_at_0[0x20]; 4044 }; 4045 4046 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4047 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4048 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4049 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4050 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4051 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4052 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4053 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4054 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4055 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4056 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4057 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4058 u8 reserved_at_0[0x7c0]; 4059 }; 4060 4061 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4062 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4063 u8 reserved_at_0[0x7c0]; 4064 }; 4065 4066 union mlx5_ifc_event_auto_bits { 4067 struct mlx5_ifc_comp_event_bits comp_event; 4068 struct mlx5_ifc_dct_events_bits dct_events; 4069 struct mlx5_ifc_qp_events_bits qp_events; 4070 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4071 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4072 struct mlx5_ifc_cq_error_bits cq_error; 4073 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4074 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4075 struct mlx5_ifc_gpio_event_bits gpio_event; 4076 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4077 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4078 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4079 u8 reserved_at_0[0xe0]; 4080 }; 4081 4082 struct mlx5_ifc_health_buffer_bits { 4083 u8 reserved_at_0[0x100]; 4084 4085 u8 assert_existptr[0x20]; 4086 4087 u8 assert_callra[0x20]; 4088 4089 u8 reserved_at_140[0x40]; 4090 4091 u8 fw_version[0x20]; 4092 4093 u8 hw_id[0x20]; 4094 4095 u8 reserved_at_1c0[0x20]; 4096 4097 u8 irisc_index[0x8]; 4098 u8 synd[0x8]; 4099 u8 ext_synd[0x10]; 4100 }; 4101 4102 struct mlx5_ifc_register_loopback_control_bits { 4103 u8 no_lb[0x1]; 4104 u8 reserved_at_1[0x7]; 4105 u8 port[0x8]; 4106 u8 reserved_at_10[0x10]; 4107 4108 u8 reserved_at_20[0x60]; 4109 }; 4110 4111 struct mlx5_ifc_vport_tc_element_bits { 4112 u8 traffic_class[0x4]; 4113 u8 reserved_at_4[0xc]; 4114 u8 vport_number[0x10]; 4115 }; 4116 4117 struct mlx5_ifc_vport_element_bits { 4118 u8 reserved_at_0[0x10]; 4119 u8 vport_number[0x10]; 4120 }; 4121 4122 enum { 4123 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4124 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4125 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4126 }; 4127 4128 struct mlx5_ifc_tsar_element_bits { 4129 u8 reserved_at_0[0x8]; 4130 u8 tsar_type[0x8]; 4131 u8 reserved_at_10[0x10]; 4132 }; 4133 4134 enum { 4135 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4136 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4137 }; 4138 4139 struct mlx5_ifc_teardown_hca_out_bits { 4140 u8 status[0x8]; 4141 u8 reserved_at_8[0x18]; 4142 4143 u8 syndrome[0x20]; 4144 4145 u8 reserved_at_40[0x3f]; 4146 4147 u8 state[0x1]; 4148 }; 4149 4150 enum { 4151 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4152 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4153 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4154 }; 4155 4156 struct mlx5_ifc_teardown_hca_in_bits { 4157 u8 opcode[0x10]; 4158 u8 reserved_at_10[0x10]; 4159 4160 u8 reserved_at_20[0x10]; 4161 u8 op_mod[0x10]; 4162 4163 u8 reserved_at_40[0x10]; 4164 u8 profile[0x10]; 4165 4166 u8 reserved_at_60[0x20]; 4167 }; 4168 4169 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4170 u8 status[0x8]; 4171 u8 reserved_at_8[0x18]; 4172 4173 u8 syndrome[0x20]; 4174 4175 u8 reserved_at_40[0x40]; 4176 }; 4177 4178 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4179 u8 opcode[0x10]; 4180 u8 uid[0x10]; 4181 4182 u8 reserved_at_20[0x10]; 4183 u8 op_mod[0x10]; 4184 4185 u8 reserved_at_40[0x8]; 4186 u8 qpn[0x18]; 4187 4188 u8 reserved_at_60[0x20]; 4189 4190 u8 opt_param_mask[0x20]; 4191 4192 u8 reserved_at_a0[0x20]; 4193 4194 struct mlx5_ifc_qpc_bits qpc; 4195 4196 u8 reserved_at_800[0x80]; 4197 }; 4198 4199 struct mlx5_ifc_sqd2rts_qp_out_bits { 4200 u8 status[0x8]; 4201 u8 reserved_at_8[0x18]; 4202 4203 u8 syndrome[0x20]; 4204 4205 u8 reserved_at_40[0x40]; 4206 }; 4207 4208 struct mlx5_ifc_sqd2rts_qp_in_bits { 4209 u8 opcode[0x10]; 4210 u8 uid[0x10]; 4211 4212 u8 reserved_at_20[0x10]; 4213 u8 op_mod[0x10]; 4214 4215 u8 reserved_at_40[0x8]; 4216 u8 qpn[0x18]; 4217 4218 u8 reserved_at_60[0x20]; 4219 4220 u8 opt_param_mask[0x20]; 4221 4222 u8 reserved_at_a0[0x20]; 4223 4224 struct mlx5_ifc_qpc_bits qpc; 4225 4226 u8 reserved_at_800[0x80]; 4227 }; 4228 4229 struct mlx5_ifc_set_roce_address_out_bits { 4230 u8 status[0x8]; 4231 u8 reserved_at_8[0x18]; 4232 4233 u8 syndrome[0x20]; 4234 4235 u8 reserved_at_40[0x40]; 4236 }; 4237 4238 struct mlx5_ifc_set_roce_address_in_bits { 4239 u8 opcode[0x10]; 4240 u8 reserved_at_10[0x10]; 4241 4242 u8 reserved_at_20[0x10]; 4243 u8 op_mod[0x10]; 4244 4245 u8 roce_address_index[0x10]; 4246 u8 reserved_at_50[0xc]; 4247 u8 vhca_port_num[0x4]; 4248 4249 u8 reserved_at_60[0x20]; 4250 4251 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4252 }; 4253 4254 struct mlx5_ifc_set_mad_demux_out_bits { 4255 u8 status[0x8]; 4256 u8 reserved_at_8[0x18]; 4257 4258 u8 syndrome[0x20]; 4259 4260 u8 reserved_at_40[0x40]; 4261 }; 4262 4263 enum { 4264 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4265 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4266 }; 4267 4268 struct mlx5_ifc_set_mad_demux_in_bits { 4269 u8 opcode[0x10]; 4270 u8 reserved_at_10[0x10]; 4271 4272 u8 reserved_at_20[0x10]; 4273 u8 op_mod[0x10]; 4274 4275 u8 reserved_at_40[0x20]; 4276 4277 u8 reserved_at_60[0x6]; 4278 u8 demux_mode[0x2]; 4279 u8 reserved_at_68[0x18]; 4280 }; 4281 4282 struct mlx5_ifc_set_l2_table_entry_out_bits { 4283 u8 status[0x8]; 4284 u8 reserved_at_8[0x18]; 4285 4286 u8 syndrome[0x20]; 4287 4288 u8 reserved_at_40[0x40]; 4289 }; 4290 4291 struct mlx5_ifc_set_l2_table_entry_in_bits { 4292 u8 opcode[0x10]; 4293 u8 reserved_at_10[0x10]; 4294 4295 u8 reserved_at_20[0x10]; 4296 u8 op_mod[0x10]; 4297 4298 u8 reserved_at_40[0x60]; 4299 4300 u8 reserved_at_a0[0x8]; 4301 u8 table_index[0x18]; 4302 4303 u8 reserved_at_c0[0x20]; 4304 4305 u8 reserved_at_e0[0x13]; 4306 u8 vlan_valid[0x1]; 4307 u8 vlan[0xc]; 4308 4309 struct mlx5_ifc_mac_address_layout_bits mac_address; 4310 4311 u8 reserved_at_140[0xc0]; 4312 }; 4313 4314 struct mlx5_ifc_set_issi_out_bits { 4315 u8 status[0x8]; 4316 u8 reserved_at_8[0x18]; 4317 4318 u8 syndrome[0x20]; 4319 4320 u8 reserved_at_40[0x40]; 4321 }; 4322 4323 struct mlx5_ifc_set_issi_in_bits { 4324 u8 opcode[0x10]; 4325 u8 reserved_at_10[0x10]; 4326 4327 u8 reserved_at_20[0x10]; 4328 u8 op_mod[0x10]; 4329 4330 u8 reserved_at_40[0x10]; 4331 u8 current_issi[0x10]; 4332 4333 u8 reserved_at_60[0x20]; 4334 }; 4335 4336 struct mlx5_ifc_set_hca_cap_out_bits { 4337 u8 status[0x8]; 4338 u8 reserved_at_8[0x18]; 4339 4340 u8 syndrome[0x20]; 4341 4342 u8 reserved_at_40[0x40]; 4343 }; 4344 4345 struct mlx5_ifc_set_hca_cap_in_bits { 4346 u8 opcode[0x10]; 4347 u8 reserved_at_10[0x10]; 4348 4349 u8 reserved_at_20[0x10]; 4350 u8 op_mod[0x10]; 4351 4352 u8 other_function[0x1]; 4353 u8 reserved_at_41[0xf]; 4354 u8 function_id[0x10]; 4355 4356 u8 reserved_at_60[0x20]; 4357 4358 union mlx5_ifc_hca_cap_union_bits capability; 4359 }; 4360 4361 enum { 4362 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4363 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4364 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4365 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4366 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4367 }; 4368 4369 struct mlx5_ifc_set_fte_out_bits { 4370 u8 status[0x8]; 4371 u8 reserved_at_8[0x18]; 4372 4373 u8 syndrome[0x20]; 4374 4375 u8 reserved_at_40[0x40]; 4376 }; 4377 4378 struct mlx5_ifc_set_fte_in_bits { 4379 u8 opcode[0x10]; 4380 u8 reserved_at_10[0x10]; 4381 4382 u8 reserved_at_20[0x10]; 4383 u8 op_mod[0x10]; 4384 4385 u8 other_vport[0x1]; 4386 u8 reserved_at_41[0xf]; 4387 u8 vport_number[0x10]; 4388 4389 u8 reserved_at_60[0x20]; 4390 4391 u8 table_type[0x8]; 4392 u8 reserved_at_88[0x18]; 4393 4394 u8 reserved_at_a0[0x8]; 4395 u8 table_id[0x18]; 4396 4397 u8 ignore_flow_level[0x1]; 4398 u8 reserved_at_c1[0x17]; 4399 u8 modify_enable_mask[0x8]; 4400 4401 u8 reserved_at_e0[0x20]; 4402 4403 u8 flow_index[0x20]; 4404 4405 u8 reserved_at_120[0xe0]; 4406 4407 struct mlx5_ifc_flow_context_bits flow_context; 4408 }; 4409 4410 struct mlx5_ifc_rts2rts_qp_out_bits { 4411 u8 status[0x8]; 4412 u8 reserved_at_8[0x18]; 4413 4414 u8 syndrome[0x20]; 4415 4416 u8 reserved_at_40[0x20]; 4417 u8 ece[0x20]; 4418 }; 4419 4420 struct mlx5_ifc_rts2rts_qp_in_bits { 4421 u8 opcode[0x10]; 4422 u8 uid[0x10]; 4423 4424 u8 reserved_at_20[0x10]; 4425 u8 op_mod[0x10]; 4426 4427 u8 reserved_at_40[0x8]; 4428 u8 qpn[0x18]; 4429 4430 u8 reserved_at_60[0x20]; 4431 4432 u8 opt_param_mask[0x20]; 4433 4434 u8 ece[0x20]; 4435 4436 struct mlx5_ifc_qpc_bits qpc; 4437 4438 u8 reserved_at_800[0x80]; 4439 }; 4440 4441 struct mlx5_ifc_rtr2rts_qp_out_bits { 4442 u8 status[0x8]; 4443 u8 reserved_at_8[0x18]; 4444 4445 u8 syndrome[0x20]; 4446 4447 u8 reserved_at_40[0x20]; 4448 u8 ece[0x20]; 4449 }; 4450 4451 struct mlx5_ifc_rtr2rts_qp_in_bits { 4452 u8 opcode[0x10]; 4453 u8 uid[0x10]; 4454 4455 u8 reserved_at_20[0x10]; 4456 u8 op_mod[0x10]; 4457 4458 u8 reserved_at_40[0x8]; 4459 u8 qpn[0x18]; 4460 4461 u8 reserved_at_60[0x20]; 4462 4463 u8 opt_param_mask[0x20]; 4464 4465 u8 ece[0x20]; 4466 4467 struct mlx5_ifc_qpc_bits qpc; 4468 4469 u8 reserved_at_800[0x80]; 4470 }; 4471 4472 struct mlx5_ifc_rst2init_qp_out_bits { 4473 u8 status[0x8]; 4474 u8 reserved_at_8[0x18]; 4475 4476 u8 syndrome[0x20]; 4477 4478 u8 reserved_at_40[0x20]; 4479 u8 ece[0x20]; 4480 }; 4481 4482 struct mlx5_ifc_rst2init_qp_in_bits { 4483 u8 opcode[0x10]; 4484 u8 uid[0x10]; 4485 4486 u8 reserved_at_20[0x10]; 4487 u8 op_mod[0x10]; 4488 4489 u8 reserved_at_40[0x8]; 4490 u8 qpn[0x18]; 4491 4492 u8 reserved_at_60[0x20]; 4493 4494 u8 opt_param_mask[0x20]; 4495 4496 u8 ece[0x20]; 4497 4498 struct mlx5_ifc_qpc_bits qpc; 4499 4500 u8 reserved_at_800[0x80]; 4501 }; 4502 4503 struct mlx5_ifc_query_xrq_out_bits { 4504 u8 status[0x8]; 4505 u8 reserved_at_8[0x18]; 4506 4507 u8 syndrome[0x20]; 4508 4509 u8 reserved_at_40[0x40]; 4510 4511 struct mlx5_ifc_xrqc_bits xrq_context; 4512 }; 4513 4514 struct mlx5_ifc_query_xrq_in_bits { 4515 u8 opcode[0x10]; 4516 u8 reserved_at_10[0x10]; 4517 4518 u8 reserved_at_20[0x10]; 4519 u8 op_mod[0x10]; 4520 4521 u8 reserved_at_40[0x8]; 4522 u8 xrqn[0x18]; 4523 4524 u8 reserved_at_60[0x20]; 4525 }; 4526 4527 struct mlx5_ifc_query_xrc_srq_out_bits { 4528 u8 status[0x8]; 4529 u8 reserved_at_8[0x18]; 4530 4531 u8 syndrome[0x20]; 4532 4533 u8 reserved_at_40[0x40]; 4534 4535 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4536 4537 u8 reserved_at_280[0x600]; 4538 4539 u8 pas[][0x40]; 4540 }; 4541 4542 struct mlx5_ifc_query_xrc_srq_in_bits { 4543 u8 opcode[0x10]; 4544 u8 reserved_at_10[0x10]; 4545 4546 u8 reserved_at_20[0x10]; 4547 u8 op_mod[0x10]; 4548 4549 u8 reserved_at_40[0x8]; 4550 u8 xrc_srqn[0x18]; 4551 4552 u8 reserved_at_60[0x20]; 4553 }; 4554 4555 enum { 4556 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4557 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4558 }; 4559 4560 struct mlx5_ifc_query_vport_state_out_bits { 4561 u8 status[0x8]; 4562 u8 reserved_at_8[0x18]; 4563 4564 u8 syndrome[0x20]; 4565 4566 u8 reserved_at_40[0x20]; 4567 4568 u8 reserved_at_60[0x18]; 4569 u8 admin_state[0x4]; 4570 u8 state[0x4]; 4571 }; 4572 4573 enum { 4574 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4575 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4576 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4577 }; 4578 4579 struct mlx5_ifc_arm_monitor_counter_in_bits { 4580 u8 opcode[0x10]; 4581 u8 uid[0x10]; 4582 4583 u8 reserved_at_20[0x10]; 4584 u8 op_mod[0x10]; 4585 4586 u8 reserved_at_40[0x20]; 4587 4588 u8 reserved_at_60[0x20]; 4589 }; 4590 4591 struct mlx5_ifc_arm_monitor_counter_out_bits { 4592 u8 status[0x8]; 4593 u8 reserved_at_8[0x18]; 4594 4595 u8 syndrome[0x20]; 4596 4597 u8 reserved_at_40[0x40]; 4598 }; 4599 4600 enum { 4601 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4602 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4603 }; 4604 4605 enum mlx5_monitor_counter_ppcnt { 4606 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4607 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4608 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4609 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4610 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4611 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4612 }; 4613 4614 enum { 4615 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4616 }; 4617 4618 struct mlx5_ifc_monitor_counter_output_bits { 4619 u8 reserved_at_0[0x4]; 4620 u8 type[0x4]; 4621 u8 reserved_at_8[0x8]; 4622 u8 counter[0x10]; 4623 4624 u8 counter_group_id[0x20]; 4625 }; 4626 4627 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4628 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4629 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4630 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4631 4632 struct mlx5_ifc_set_monitor_counter_in_bits { 4633 u8 opcode[0x10]; 4634 u8 uid[0x10]; 4635 4636 u8 reserved_at_20[0x10]; 4637 u8 op_mod[0x10]; 4638 4639 u8 reserved_at_40[0x10]; 4640 u8 num_of_counters[0x10]; 4641 4642 u8 reserved_at_60[0x20]; 4643 4644 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4645 }; 4646 4647 struct mlx5_ifc_set_monitor_counter_out_bits { 4648 u8 status[0x8]; 4649 u8 reserved_at_8[0x18]; 4650 4651 u8 syndrome[0x20]; 4652 4653 u8 reserved_at_40[0x40]; 4654 }; 4655 4656 struct mlx5_ifc_query_vport_state_in_bits { 4657 u8 opcode[0x10]; 4658 u8 reserved_at_10[0x10]; 4659 4660 u8 reserved_at_20[0x10]; 4661 u8 op_mod[0x10]; 4662 4663 u8 other_vport[0x1]; 4664 u8 reserved_at_41[0xf]; 4665 u8 vport_number[0x10]; 4666 4667 u8 reserved_at_60[0x20]; 4668 }; 4669 4670 struct mlx5_ifc_query_vnic_env_out_bits { 4671 u8 status[0x8]; 4672 u8 reserved_at_8[0x18]; 4673 4674 u8 syndrome[0x20]; 4675 4676 u8 reserved_at_40[0x40]; 4677 4678 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4679 }; 4680 4681 enum { 4682 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4683 }; 4684 4685 struct mlx5_ifc_query_vnic_env_in_bits { 4686 u8 opcode[0x10]; 4687 u8 reserved_at_10[0x10]; 4688 4689 u8 reserved_at_20[0x10]; 4690 u8 op_mod[0x10]; 4691 4692 u8 other_vport[0x1]; 4693 u8 reserved_at_41[0xf]; 4694 u8 vport_number[0x10]; 4695 4696 u8 reserved_at_60[0x20]; 4697 }; 4698 4699 struct mlx5_ifc_query_vport_counter_out_bits { 4700 u8 status[0x8]; 4701 u8 reserved_at_8[0x18]; 4702 4703 u8 syndrome[0x20]; 4704 4705 u8 reserved_at_40[0x40]; 4706 4707 struct mlx5_ifc_traffic_counter_bits received_errors; 4708 4709 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4710 4711 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4712 4713 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4714 4715 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4716 4717 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4718 4719 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4720 4721 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4722 4723 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4724 4725 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4726 4727 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4728 4729 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4730 4731 u8 reserved_at_680[0xa00]; 4732 }; 4733 4734 enum { 4735 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4736 }; 4737 4738 struct mlx5_ifc_query_vport_counter_in_bits { 4739 u8 opcode[0x10]; 4740 u8 reserved_at_10[0x10]; 4741 4742 u8 reserved_at_20[0x10]; 4743 u8 op_mod[0x10]; 4744 4745 u8 other_vport[0x1]; 4746 u8 reserved_at_41[0xb]; 4747 u8 port_num[0x4]; 4748 u8 vport_number[0x10]; 4749 4750 u8 reserved_at_60[0x60]; 4751 4752 u8 clear[0x1]; 4753 u8 reserved_at_c1[0x1f]; 4754 4755 u8 reserved_at_e0[0x20]; 4756 }; 4757 4758 struct mlx5_ifc_query_tis_out_bits { 4759 u8 status[0x8]; 4760 u8 reserved_at_8[0x18]; 4761 4762 u8 syndrome[0x20]; 4763 4764 u8 reserved_at_40[0x40]; 4765 4766 struct mlx5_ifc_tisc_bits tis_context; 4767 }; 4768 4769 struct mlx5_ifc_query_tis_in_bits { 4770 u8 opcode[0x10]; 4771 u8 reserved_at_10[0x10]; 4772 4773 u8 reserved_at_20[0x10]; 4774 u8 op_mod[0x10]; 4775 4776 u8 reserved_at_40[0x8]; 4777 u8 tisn[0x18]; 4778 4779 u8 reserved_at_60[0x20]; 4780 }; 4781 4782 struct mlx5_ifc_query_tir_out_bits { 4783 u8 status[0x8]; 4784 u8 reserved_at_8[0x18]; 4785 4786 u8 syndrome[0x20]; 4787 4788 u8 reserved_at_40[0xc0]; 4789 4790 struct mlx5_ifc_tirc_bits tir_context; 4791 }; 4792 4793 struct mlx5_ifc_query_tir_in_bits { 4794 u8 opcode[0x10]; 4795 u8 reserved_at_10[0x10]; 4796 4797 u8 reserved_at_20[0x10]; 4798 u8 op_mod[0x10]; 4799 4800 u8 reserved_at_40[0x8]; 4801 u8 tirn[0x18]; 4802 4803 u8 reserved_at_60[0x20]; 4804 }; 4805 4806 struct mlx5_ifc_query_srq_out_bits { 4807 u8 status[0x8]; 4808 u8 reserved_at_8[0x18]; 4809 4810 u8 syndrome[0x20]; 4811 4812 u8 reserved_at_40[0x40]; 4813 4814 struct mlx5_ifc_srqc_bits srq_context_entry; 4815 4816 u8 reserved_at_280[0x600]; 4817 4818 u8 pas[][0x40]; 4819 }; 4820 4821 struct mlx5_ifc_query_srq_in_bits { 4822 u8 opcode[0x10]; 4823 u8 reserved_at_10[0x10]; 4824 4825 u8 reserved_at_20[0x10]; 4826 u8 op_mod[0x10]; 4827 4828 u8 reserved_at_40[0x8]; 4829 u8 srqn[0x18]; 4830 4831 u8 reserved_at_60[0x20]; 4832 }; 4833 4834 struct mlx5_ifc_query_sq_out_bits { 4835 u8 status[0x8]; 4836 u8 reserved_at_8[0x18]; 4837 4838 u8 syndrome[0x20]; 4839 4840 u8 reserved_at_40[0xc0]; 4841 4842 struct mlx5_ifc_sqc_bits sq_context; 4843 }; 4844 4845 struct mlx5_ifc_query_sq_in_bits { 4846 u8 opcode[0x10]; 4847 u8 reserved_at_10[0x10]; 4848 4849 u8 reserved_at_20[0x10]; 4850 u8 op_mod[0x10]; 4851 4852 u8 reserved_at_40[0x8]; 4853 u8 sqn[0x18]; 4854 4855 u8 reserved_at_60[0x20]; 4856 }; 4857 4858 struct mlx5_ifc_query_special_contexts_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_at_8[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 dump_fill_mkey[0x20]; 4865 4866 u8 resd_lkey[0x20]; 4867 4868 u8 null_mkey[0x20]; 4869 4870 u8 reserved_at_a0[0x60]; 4871 }; 4872 4873 struct mlx5_ifc_query_special_contexts_in_bits { 4874 u8 opcode[0x10]; 4875 u8 reserved_at_10[0x10]; 4876 4877 u8 reserved_at_20[0x10]; 4878 u8 op_mod[0x10]; 4879 4880 u8 reserved_at_40[0x40]; 4881 }; 4882 4883 struct mlx5_ifc_query_scheduling_element_out_bits { 4884 u8 opcode[0x10]; 4885 u8 reserved_at_10[0x10]; 4886 4887 u8 reserved_at_20[0x10]; 4888 u8 op_mod[0x10]; 4889 4890 u8 reserved_at_40[0xc0]; 4891 4892 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4893 4894 u8 reserved_at_300[0x100]; 4895 }; 4896 4897 enum { 4898 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4899 SCHEDULING_HIERARCHY_NIC = 0x3, 4900 }; 4901 4902 struct mlx5_ifc_query_scheduling_element_in_bits { 4903 u8 opcode[0x10]; 4904 u8 reserved_at_10[0x10]; 4905 4906 u8 reserved_at_20[0x10]; 4907 u8 op_mod[0x10]; 4908 4909 u8 scheduling_hierarchy[0x8]; 4910 u8 reserved_at_48[0x18]; 4911 4912 u8 scheduling_element_id[0x20]; 4913 4914 u8 reserved_at_80[0x180]; 4915 }; 4916 4917 struct mlx5_ifc_query_rqt_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_at_8[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_at_40[0xc0]; 4924 4925 struct mlx5_ifc_rqtc_bits rqt_context; 4926 }; 4927 4928 struct mlx5_ifc_query_rqt_in_bits { 4929 u8 opcode[0x10]; 4930 u8 reserved_at_10[0x10]; 4931 4932 u8 reserved_at_20[0x10]; 4933 u8 op_mod[0x10]; 4934 4935 u8 reserved_at_40[0x8]; 4936 u8 rqtn[0x18]; 4937 4938 u8 reserved_at_60[0x20]; 4939 }; 4940 4941 struct mlx5_ifc_query_rq_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_at_8[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_at_40[0xc0]; 4948 4949 struct mlx5_ifc_rqc_bits rq_context; 4950 }; 4951 4952 struct mlx5_ifc_query_rq_in_bits { 4953 u8 opcode[0x10]; 4954 u8 reserved_at_10[0x10]; 4955 4956 u8 reserved_at_20[0x10]; 4957 u8 op_mod[0x10]; 4958 4959 u8 reserved_at_40[0x8]; 4960 u8 rqn[0x18]; 4961 4962 u8 reserved_at_60[0x20]; 4963 }; 4964 4965 struct mlx5_ifc_query_roce_address_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0x40]; 4972 4973 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4974 }; 4975 4976 struct mlx5_ifc_query_roce_address_in_bits { 4977 u8 opcode[0x10]; 4978 u8 reserved_at_10[0x10]; 4979 4980 u8 reserved_at_20[0x10]; 4981 u8 op_mod[0x10]; 4982 4983 u8 roce_address_index[0x10]; 4984 u8 reserved_at_50[0xc]; 4985 u8 vhca_port_num[0x4]; 4986 4987 u8 reserved_at_60[0x20]; 4988 }; 4989 4990 struct mlx5_ifc_query_rmp_out_bits { 4991 u8 status[0x8]; 4992 u8 reserved_at_8[0x18]; 4993 4994 u8 syndrome[0x20]; 4995 4996 u8 reserved_at_40[0xc0]; 4997 4998 struct mlx5_ifc_rmpc_bits rmp_context; 4999 }; 5000 5001 struct mlx5_ifc_query_rmp_in_bits { 5002 u8 opcode[0x10]; 5003 u8 reserved_at_10[0x10]; 5004 5005 u8 reserved_at_20[0x10]; 5006 u8 op_mod[0x10]; 5007 5008 u8 reserved_at_40[0x8]; 5009 u8 rmpn[0x18]; 5010 5011 u8 reserved_at_60[0x20]; 5012 }; 5013 5014 struct mlx5_ifc_query_qp_out_bits { 5015 u8 status[0x8]; 5016 u8 reserved_at_8[0x18]; 5017 5018 u8 syndrome[0x20]; 5019 5020 u8 reserved_at_40[0x20]; 5021 u8 ece[0x20]; 5022 5023 u8 opt_param_mask[0x20]; 5024 5025 u8 reserved_at_a0[0x20]; 5026 5027 struct mlx5_ifc_qpc_bits qpc; 5028 5029 u8 reserved_at_800[0x80]; 5030 5031 u8 pas[][0x40]; 5032 }; 5033 5034 struct mlx5_ifc_query_qp_in_bits { 5035 u8 opcode[0x10]; 5036 u8 reserved_at_10[0x10]; 5037 5038 u8 reserved_at_20[0x10]; 5039 u8 op_mod[0x10]; 5040 5041 u8 reserved_at_40[0x8]; 5042 u8 qpn[0x18]; 5043 5044 u8 reserved_at_60[0x20]; 5045 }; 5046 5047 struct mlx5_ifc_query_q_counter_out_bits { 5048 u8 status[0x8]; 5049 u8 reserved_at_8[0x18]; 5050 5051 u8 syndrome[0x20]; 5052 5053 u8 reserved_at_40[0x40]; 5054 5055 u8 rx_write_requests[0x20]; 5056 5057 u8 reserved_at_a0[0x20]; 5058 5059 u8 rx_read_requests[0x20]; 5060 5061 u8 reserved_at_e0[0x20]; 5062 5063 u8 rx_atomic_requests[0x20]; 5064 5065 u8 reserved_at_120[0x20]; 5066 5067 u8 rx_dct_connect[0x20]; 5068 5069 u8 reserved_at_160[0x20]; 5070 5071 u8 out_of_buffer[0x20]; 5072 5073 u8 reserved_at_1a0[0x20]; 5074 5075 u8 out_of_sequence[0x20]; 5076 5077 u8 reserved_at_1e0[0x20]; 5078 5079 u8 duplicate_request[0x20]; 5080 5081 u8 reserved_at_220[0x20]; 5082 5083 u8 rnr_nak_retry_err[0x20]; 5084 5085 u8 reserved_at_260[0x20]; 5086 5087 u8 packet_seq_err[0x20]; 5088 5089 u8 reserved_at_2a0[0x20]; 5090 5091 u8 implied_nak_seq_err[0x20]; 5092 5093 u8 reserved_at_2e0[0x20]; 5094 5095 u8 local_ack_timeout_err[0x20]; 5096 5097 u8 reserved_at_320[0xa0]; 5098 5099 u8 resp_local_length_error[0x20]; 5100 5101 u8 req_local_length_error[0x20]; 5102 5103 u8 resp_local_qp_error[0x20]; 5104 5105 u8 local_operation_error[0x20]; 5106 5107 u8 resp_local_protection[0x20]; 5108 5109 u8 req_local_protection[0x20]; 5110 5111 u8 resp_cqe_error[0x20]; 5112 5113 u8 req_cqe_error[0x20]; 5114 5115 u8 req_mw_binding[0x20]; 5116 5117 u8 req_bad_response[0x20]; 5118 5119 u8 req_remote_invalid_request[0x20]; 5120 5121 u8 resp_remote_invalid_request[0x20]; 5122 5123 u8 req_remote_access_errors[0x20]; 5124 5125 u8 resp_remote_access_errors[0x20]; 5126 5127 u8 req_remote_operation_errors[0x20]; 5128 5129 u8 req_transport_retries_exceeded[0x20]; 5130 5131 u8 cq_overflow[0x20]; 5132 5133 u8 resp_cqe_flush_error[0x20]; 5134 5135 u8 req_cqe_flush_error[0x20]; 5136 5137 u8 reserved_at_620[0x20]; 5138 5139 u8 roce_adp_retrans[0x20]; 5140 5141 u8 roce_adp_retrans_to[0x20]; 5142 5143 u8 roce_slow_restart[0x20]; 5144 5145 u8 roce_slow_restart_cnps[0x20]; 5146 5147 u8 roce_slow_restart_trans[0x20]; 5148 5149 u8 reserved_at_6e0[0x120]; 5150 }; 5151 5152 struct mlx5_ifc_query_q_counter_in_bits { 5153 u8 opcode[0x10]; 5154 u8 reserved_at_10[0x10]; 5155 5156 u8 reserved_at_20[0x10]; 5157 u8 op_mod[0x10]; 5158 5159 u8 reserved_at_40[0x80]; 5160 5161 u8 clear[0x1]; 5162 u8 reserved_at_c1[0x1f]; 5163 5164 u8 reserved_at_e0[0x18]; 5165 u8 counter_set_id[0x8]; 5166 }; 5167 5168 struct mlx5_ifc_query_pages_out_bits { 5169 u8 status[0x8]; 5170 u8 reserved_at_8[0x18]; 5171 5172 u8 syndrome[0x20]; 5173 5174 u8 embedded_cpu_function[0x1]; 5175 u8 reserved_at_41[0xf]; 5176 u8 function_id[0x10]; 5177 5178 u8 num_pages[0x20]; 5179 }; 5180 5181 enum { 5182 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5183 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5184 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5185 }; 5186 5187 struct mlx5_ifc_query_pages_in_bits { 5188 u8 opcode[0x10]; 5189 u8 reserved_at_10[0x10]; 5190 5191 u8 reserved_at_20[0x10]; 5192 u8 op_mod[0x10]; 5193 5194 u8 embedded_cpu_function[0x1]; 5195 u8 reserved_at_41[0xf]; 5196 u8 function_id[0x10]; 5197 5198 u8 reserved_at_60[0x20]; 5199 }; 5200 5201 struct mlx5_ifc_query_nic_vport_context_out_bits { 5202 u8 status[0x8]; 5203 u8 reserved_at_8[0x18]; 5204 5205 u8 syndrome[0x20]; 5206 5207 u8 reserved_at_40[0x40]; 5208 5209 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5210 }; 5211 5212 struct mlx5_ifc_query_nic_vport_context_in_bits { 5213 u8 opcode[0x10]; 5214 u8 reserved_at_10[0x10]; 5215 5216 u8 reserved_at_20[0x10]; 5217 u8 op_mod[0x10]; 5218 5219 u8 other_vport[0x1]; 5220 u8 reserved_at_41[0xf]; 5221 u8 vport_number[0x10]; 5222 5223 u8 reserved_at_60[0x5]; 5224 u8 allowed_list_type[0x3]; 5225 u8 reserved_at_68[0x18]; 5226 }; 5227 5228 struct mlx5_ifc_query_mkey_out_bits { 5229 u8 status[0x8]; 5230 u8 reserved_at_8[0x18]; 5231 5232 u8 syndrome[0x20]; 5233 5234 u8 reserved_at_40[0x40]; 5235 5236 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5237 5238 u8 reserved_at_280[0x600]; 5239 5240 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5241 5242 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5243 }; 5244 5245 struct mlx5_ifc_query_mkey_in_bits { 5246 u8 opcode[0x10]; 5247 u8 reserved_at_10[0x10]; 5248 5249 u8 reserved_at_20[0x10]; 5250 u8 op_mod[0x10]; 5251 5252 u8 reserved_at_40[0x8]; 5253 u8 mkey_index[0x18]; 5254 5255 u8 pg_access[0x1]; 5256 u8 reserved_at_61[0x1f]; 5257 }; 5258 5259 struct mlx5_ifc_query_mad_demux_out_bits { 5260 u8 status[0x8]; 5261 u8 reserved_at_8[0x18]; 5262 5263 u8 syndrome[0x20]; 5264 5265 u8 reserved_at_40[0x40]; 5266 5267 u8 mad_dumux_parameters_block[0x20]; 5268 }; 5269 5270 struct mlx5_ifc_query_mad_demux_in_bits { 5271 u8 opcode[0x10]; 5272 u8 reserved_at_10[0x10]; 5273 5274 u8 reserved_at_20[0x10]; 5275 u8 op_mod[0x10]; 5276 5277 u8 reserved_at_40[0x40]; 5278 }; 5279 5280 struct mlx5_ifc_query_l2_table_entry_out_bits { 5281 u8 status[0x8]; 5282 u8 reserved_at_8[0x18]; 5283 5284 u8 syndrome[0x20]; 5285 5286 u8 reserved_at_40[0xa0]; 5287 5288 u8 reserved_at_e0[0x13]; 5289 u8 vlan_valid[0x1]; 5290 u8 vlan[0xc]; 5291 5292 struct mlx5_ifc_mac_address_layout_bits mac_address; 5293 5294 u8 reserved_at_140[0xc0]; 5295 }; 5296 5297 struct mlx5_ifc_query_l2_table_entry_in_bits { 5298 u8 opcode[0x10]; 5299 u8 reserved_at_10[0x10]; 5300 5301 u8 reserved_at_20[0x10]; 5302 u8 op_mod[0x10]; 5303 5304 u8 reserved_at_40[0x60]; 5305 5306 u8 reserved_at_a0[0x8]; 5307 u8 table_index[0x18]; 5308 5309 u8 reserved_at_c0[0x140]; 5310 }; 5311 5312 struct mlx5_ifc_query_issi_out_bits { 5313 u8 status[0x8]; 5314 u8 reserved_at_8[0x18]; 5315 5316 u8 syndrome[0x20]; 5317 5318 u8 reserved_at_40[0x10]; 5319 u8 current_issi[0x10]; 5320 5321 u8 reserved_at_60[0xa0]; 5322 5323 u8 reserved_at_100[76][0x8]; 5324 u8 supported_issi_dw0[0x20]; 5325 }; 5326 5327 struct mlx5_ifc_query_issi_in_bits { 5328 u8 opcode[0x10]; 5329 u8 reserved_at_10[0x10]; 5330 5331 u8 reserved_at_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 reserved_at_40[0x40]; 5335 }; 5336 5337 struct mlx5_ifc_set_driver_version_out_bits { 5338 u8 status[0x8]; 5339 u8 reserved_0[0x18]; 5340 5341 u8 syndrome[0x20]; 5342 u8 reserved_1[0x40]; 5343 }; 5344 5345 struct mlx5_ifc_set_driver_version_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_0[0x10]; 5348 5349 u8 reserved_1[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 reserved_2[0x40]; 5353 u8 driver_version[64][0x8]; 5354 }; 5355 5356 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5357 u8 status[0x8]; 5358 u8 reserved_at_8[0x18]; 5359 5360 u8 syndrome[0x20]; 5361 5362 u8 reserved_at_40[0x40]; 5363 5364 struct mlx5_ifc_pkey_bits pkey[]; 5365 }; 5366 5367 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5368 u8 opcode[0x10]; 5369 u8 reserved_at_10[0x10]; 5370 5371 u8 reserved_at_20[0x10]; 5372 u8 op_mod[0x10]; 5373 5374 u8 other_vport[0x1]; 5375 u8 reserved_at_41[0xb]; 5376 u8 port_num[0x4]; 5377 u8 vport_number[0x10]; 5378 5379 u8 reserved_at_60[0x10]; 5380 u8 pkey_index[0x10]; 5381 }; 5382 5383 enum { 5384 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5385 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5386 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5387 }; 5388 5389 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5390 u8 status[0x8]; 5391 u8 reserved_at_8[0x18]; 5392 5393 u8 syndrome[0x20]; 5394 5395 u8 reserved_at_40[0x20]; 5396 5397 u8 gids_num[0x10]; 5398 u8 reserved_at_70[0x10]; 5399 5400 struct mlx5_ifc_array128_auto_bits gid[]; 5401 }; 5402 5403 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5404 u8 opcode[0x10]; 5405 u8 reserved_at_10[0x10]; 5406 5407 u8 reserved_at_20[0x10]; 5408 u8 op_mod[0x10]; 5409 5410 u8 other_vport[0x1]; 5411 u8 reserved_at_41[0xb]; 5412 u8 port_num[0x4]; 5413 u8 vport_number[0x10]; 5414 5415 u8 reserved_at_60[0x10]; 5416 u8 gid_index[0x10]; 5417 }; 5418 5419 struct mlx5_ifc_query_hca_vport_context_out_bits { 5420 u8 status[0x8]; 5421 u8 reserved_at_8[0x18]; 5422 5423 u8 syndrome[0x20]; 5424 5425 u8 reserved_at_40[0x40]; 5426 5427 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5428 }; 5429 5430 struct mlx5_ifc_query_hca_vport_context_in_bits { 5431 u8 opcode[0x10]; 5432 u8 reserved_at_10[0x10]; 5433 5434 u8 reserved_at_20[0x10]; 5435 u8 op_mod[0x10]; 5436 5437 u8 other_vport[0x1]; 5438 u8 reserved_at_41[0xb]; 5439 u8 port_num[0x4]; 5440 u8 vport_number[0x10]; 5441 5442 u8 reserved_at_60[0x20]; 5443 }; 5444 5445 struct mlx5_ifc_query_hca_cap_out_bits { 5446 u8 status[0x8]; 5447 u8 reserved_at_8[0x18]; 5448 5449 u8 syndrome[0x20]; 5450 5451 u8 reserved_at_40[0x40]; 5452 5453 union mlx5_ifc_hca_cap_union_bits capability; 5454 }; 5455 5456 struct mlx5_ifc_query_hca_cap_in_bits { 5457 u8 opcode[0x10]; 5458 u8 reserved_at_10[0x10]; 5459 5460 u8 reserved_at_20[0x10]; 5461 u8 op_mod[0x10]; 5462 5463 u8 other_function[0x1]; 5464 u8 reserved_at_41[0xf]; 5465 u8 function_id[0x10]; 5466 5467 u8 reserved_at_60[0x20]; 5468 }; 5469 5470 struct mlx5_ifc_other_hca_cap_bits { 5471 u8 roce[0x1]; 5472 u8 reserved_at_1[0x27f]; 5473 }; 5474 5475 struct mlx5_ifc_query_other_hca_cap_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_at_8[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 reserved_at_40[0x40]; 5482 5483 struct mlx5_ifc_other_hca_cap_bits other_capability; 5484 }; 5485 5486 struct mlx5_ifc_query_other_hca_cap_in_bits { 5487 u8 opcode[0x10]; 5488 u8 reserved_at_10[0x10]; 5489 5490 u8 reserved_at_20[0x10]; 5491 u8 op_mod[0x10]; 5492 5493 u8 reserved_at_40[0x10]; 5494 u8 function_id[0x10]; 5495 5496 u8 reserved_at_60[0x20]; 5497 }; 5498 5499 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5500 u8 status[0x8]; 5501 u8 reserved_at_8[0x18]; 5502 5503 u8 syndrome[0x20]; 5504 5505 u8 reserved_at_40[0x40]; 5506 }; 5507 5508 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5509 u8 opcode[0x10]; 5510 u8 reserved_at_10[0x10]; 5511 5512 u8 reserved_at_20[0x10]; 5513 u8 op_mod[0x10]; 5514 5515 u8 reserved_at_40[0x10]; 5516 u8 function_id[0x10]; 5517 u8 field_select[0x20]; 5518 5519 struct mlx5_ifc_other_hca_cap_bits other_capability; 5520 }; 5521 5522 struct mlx5_ifc_flow_table_context_bits { 5523 u8 reformat_en[0x1]; 5524 u8 decap_en[0x1]; 5525 u8 sw_owner[0x1]; 5526 u8 termination_table[0x1]; 5527 u8 table_miss_action[0x4]; 5528 u8 level[0x8]; 5529 u8 reserved_at_10[0x8]; 5530 u8 log_size[0x8]; 5531 5532 u8 reserved_at_20[0x8]; 5533 u8 table_miss_id[0x18]; 5534 5535 u8 reserved_at_40[0x8]; 5536 u8 lag_master_next_table_id[0x18]; 5537 5538 u8 reserved_at_60[0x60]; 5539 5540 u8 sw_owner_icm_root_1[0x40]; 5541 5542 u8 sw_owner_icm_root_0[0x40]; 5543 5544 }; 5545 5546 struct mlx5_ifc_query_flow_table_out_bits { 5547 u8 status[0x8]; 5548 u8 reserved_at_8[0x18]; 5549 5550 u8 syndrome[0x20]; 5551 5552 u8 reserved_at_40[0x80]; 5553 5554 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5555 }; 5556 5557 struct mlx5_ifc_query_flow_table_in_bits { 5558 u8 opcode[0x10]; 5559 u8 reserved_at_10[0x10]; 5560 5561 u8 reserved_at_20[0x10]; 5562 u8 op_mod[0x10]; 5563 5564 u8 reserved_at_40[0x40]; 5565 5566 u8 table_type[0x8]; 5567 u8 reserved_at_88[0x18]; 5568 5569 u8 reserved_at_a0[0x8]; 5570 u8 table_id[0x18]; 5571 5572 u8 reserved_at_c0[0x140]; 5573 }; 5574 5575 struct mlx5_ifc_query_fte_out_bits { 5576 u8 status[0x8]; 5577 u8 reserved_at_8[0x18]; 5578 5579 u8 syndrome[0x20]; 5580 5581 u8 reserved_at_40[0x1c0]; 5582 5583 struct mlx5_ifc_flow_context_bits flow_context; 5584 }; 5585 5586 struct mlx5_ifc_query_fte_in_bits { 5587 u8 opcode[0x10]; 5588 u8 reserved_at_10[0x10]; 5589 5590 u8 reserved_at_20[0x10]; 5591 u8 op_mod[0x10]; 5592 5593 u8 reserved_at_40[0x40]; 5594 5595 u8 table_type[0x8]; 5596 u8 reserved_at_88[0x18]; 5597 5598 u8 reserved_at_a0[0x8]; 5599 u8 table_id[0x18]; 5600 5601 u8 reserved_at_c0[0x40]; 5602 5603 u8 flow_index[0x20]; 5604 5605 u8 reserved_at_120[0xe0]; 5606 }; 5607 5608 enum { 5609 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5610 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5611 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5612 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5613 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5614 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5615 }; 5616 5617 struct mlx5_ifc_query_flow_group_out_bits { 5618 u8 status[0x8]; 5619 u8 reserved_at_8[0x18]; 5620 5621 u8 syndrome[0x20]; 5622 5623 u8 reserved_at_40[0xa0]; 5624 5625 u8 start_flow_index[0x20]; 5626 5627 u8 reserved_at_100[0x20]; 5628 5629 u8 end_flow_index[0x20]; 5630 5631 u8 reserved_at_140[0xa0]; 5632 5633 u8 reserved_at_1e0[0x18]; 5634 u8 match_criteria_enable[0x8]; 5635 5636 struct mlx5_ifc_fte_match_param_bits match_criteria; 5637 5638 u8 reserved_at_1200[0xe00]; 5639 }; 5640 5641 struct mlx5_ifc_query_flow_group_in_bits { 5642 u8 opcode[0x10]; 5643 u8 reserved_at_10[0x10]; 5644 5645 u8 reserved_at_20[0x10]; 5646 u8 op_mod[0x10]; 5647 5648 u8 reserved_at_40[0x40]; 5649 5650 u8 table_type[0x8]; 5651 u8 reserved_at_88[0x18]; 5652 5653 u8 reserved_at_a0[0x8]; 5654 u8 table_id[0x18]; 5655 5656 u8 group_id[0x20]; 5657 5658 u8 reserved_at_e0[0x120]; 5659 }; 5660 5661 struct mlx5_ifc_query_flow_counter_out_bits { 5662 u8 status[0x8]; 5663 u8 reserved_at_8[0x18]; 5664 5665 u8 syndrome[0x20]; 5666 5667 u8 reserved_at_40[0x40]; 5668 5669 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5670 }; 5671 5672 struct mlx5_ifc_query_flow_counter_in_bits { 5673 u8 opcode[0x10]; 5674 u8 reserved_at_10[0x10]; 5675 5676 u8 reserved_at_20[0x10]; 5677 u8 op_mod[0x10]; 5678 5679 u8 reserved_at_40[0x80]; 5680 5681 u8 clear[0x1]; 5682 u8 reserved_at_c1[0xf]; 5683 u8 num_of_counters[0x10]; 5684 5685 u8 flow_counter_id[0x20]; 5686 }; 5687 5688 struct mlx5_ifc_query_esw_vport_context_out_bits { 5689 u8 status[0x8]; 5690 u8 reserved_at_8[0x18]; 5691 5692 u8 syndrome[0x20]; 5693 5694 u8 reserved_at_40[0x40]; 5695 5696 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5697 }; 5698 5699 struct mlx5_ifc_query_esw_vport_context_in_bits { 5700 u8 opcode[0x10]; 5701 u8 reserved_at_10[0x10]; 5702 5703 u8 reserved_at_20[0x10]; 5704 u8 op_mod[0x10]; 5705 5706 u8 other_vport[0x1]; 5707 u8 reserved_at_41[0xf]; 5708 u8 vport_number[0x10]; 5709 5710 u8 reserved_at_60[0x20]; 5711 }; 5712 5713 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5714 u8 status[0x8]; 5715 u8 reserved_at_8[0x18]; 5716 5717 u8 syndrome[0x20]; 5718 5719 u8 reserved_at_40[0x40]; 5720 }; 5721 5722 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5723 u8 reserved_at_0[0x1b]; 5724 u8 fdb_to_vport_reg_c_id[0x1]; 5725 u8 vport_cvlan_insert[0x1]; 5726 u8 vport_svlan_insert[0x1]; 5727 u8 vport_cvlan_strip[0x1]; 5728 u8 vport_svlan_strip[0x1]; 5729 }; 5730 5731 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 other_vport[0x1]; 5739 u8 reserved_at_41[0xf]; 5740 u8 vport_number[0x10]; 5741 5742 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5743 5744 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5745 }; 5746 5747 struct mlx5_ifc_query_eq_out_bits { 5748 u8 status[0x8]; 5749 u8 reserved_at_8[0x18]; 5750 5751 u8 syndrome[0x20]; 5752 5753 u8 reserved_at_40[0x40]; 5754 5755 struct mlx5_ifc_eqc_bits eq_context_entry; 5756 5757 u8 reserved_at_280[0x40]; 5758 5759 u8 event_bitmask[0x40]; 5760 5761 u8 reserved_at_300[0x580]; 5762 5763 u8 pas[][0x40]; 5764 }; 5765 5766 struct mlx5_ifc_query_eq_in_bits { 5767 u8 opcode[0x10]; 5768 u8 reserved_at_10[0x10]; 5769 5770 u8 reserved_at_20[0x10]; 5771 u8 op_mod[0x10]; 5772 5773 u8 reserved_at_40[0x18]; 5774 u8 eq_number[0x8]; 5775 5776 u8 reserved_at_60[0x20]; 5777 }; 5778 5779 struct mlx5_ifc_packet_reformat_context_in_bits { 5780 u8 reformat_type[0x8]; 5781 u8 reserved_at_8[0x4]; 5782 u8 reformat_param_0[0x4]; 5783 u8 reserved_at_10[0x6]; 5784 u8 reformat_data_size[0xa]; 5785 5786 u8 reformat_param_1[0x8]; 5787 u8 reserved_at_28[0x8]; 5788 u8 reformat_data[2][0x8]; 5789 5790 u8 more_reformat_data[][0x8]; 5791 }; 5792 5793 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5794 u8 status[0x8]; 5795 u8 reserved_at_8[0x18]; 5796 5797 u8 syndrome[0x20]; 5798 5799 u8 reserved_at_40[0xa0]; 5800 5801 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5802 }; 5803 5804 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5805 u8 opcode[0x10]; 5806 u8 reserved_at_10[0x10]; 5807 5808 u8 reserved_at_20[0x10]; 5809 u8 op_mod[0x10]; 5810 5811 u8 packet_reformat_id[0x20]; 5812 5813 u8 reserved_at_60[0xa0]; 5814 }; 5815 5816 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_at_8[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 5822 u8 packet_reformat_id[0x20]; 5823 5824 u8 reserved_at_60[0x20]; 5825 }; 5826 5827 enum { 5828 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 5829 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 5830 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 5831 }; 5832 5833 enum mlx5_reformat_ctx_type { 5834 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5835 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5836 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5837 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5838 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5839 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 5840 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 5841 }; 5842 5843 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5844 u8 opcode[0x10]; 5845 u8 reserved_at_10[0x10]; 5846 5847 u8 reserved_at_20[0x10]; 5848 u8 op_mod[0x10]; 5849 5850 u8 reserved_at_40[0xa0]; 5851 5852 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5853 }; 5854 5855 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5856 u8 status[0x8]; 5857 u8 reserved_at_8[0x18]; 5858 5859 u8 syndrome[0x20]; 5860 5861 u8 reserved_at_40[0x40]; 5862 }; 5863 5864 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5865 u8 opcode[0x10]; 5866 u8 reserved_at_10[0x10]; 5867 5868 u8 reserved_20[0x10]; 5869 u8 op_mod[0x10]; 5870 5871 u8 packet_reformat_id[0x20]; 5872 5873 u8 reserved_60[0x20]; 5874 }; 5875 5876 struct mlx5_ifc_set_action_in_bits { 5877 u8 action_type[0x4]; 5878 u8 field[0xc]; 5879 u8 reserved_at_10[0x3]; 5880 u8 offset[0x5]; 5881 u8 reserved_at_18[0x3]; 5882 u8 length[0x5]; 5883 5884 u8 data[0x20]; 5885 }; 5886 5887 struct mlx5_ifc_add_action_in_bits { 5888 u8 action_type[0x4]; 5889 u8 field[0xc]; 5890 u8 reserved_at_10[0x10]; 5891 5892 u8 data[0x20]; 5893 }; 5894 5895 struct mlx5_ifc_copy_action_in_bits { 5896 u8 action_type[0x4]; 5897 u8 src_field[0xc]; 5898 u8 reserved_at_10[0x3]; 5899 u8 src_offset[0x5]; 5900 u8 reserved_at_18[0x3]; 5901 u8 length[0x5]; 5902 5903 u8 reserved_at_20[0x4]; 5904 u8 dst_field[0xc]; 5905 u8 reserved_at_30[0x3]; 5906 u8 dst_offset[0x5]; 5907 u8 reserved_at_38[0x8]; 5908 }; 5909 5910 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5911 struct mlx5_ifc_set_action_in_bits set_action_in; 5912 struct mlx5_ifc_add_action_in_bits add_action_in; 5913 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5914 u8 reserved_at_0[0x40]; 5915 }; 5916 5917 enum { 5918 MLX5_ACTION_TYPE_SET = 0x1, 5919 MLX5_ACTION_TYPE_ADD = 0x2, 5920 MLX5_ACTION_TYPE_COPY = 0x3, 5921 }; 5922 5923 enum { 5924 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5925 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5926 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5927 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5928 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5929 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5930 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5931 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5932 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5933 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5934 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5935 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5936 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5937 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5938 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5939 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5940 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5941 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5942 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5943 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5944 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5945 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5946 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5947 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5948 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5949 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5950 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5951 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5952 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5953 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5954 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5955 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5956 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5957 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5958 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5959 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5960 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5961 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 5962 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 5963 }; 5964 5965 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5966 u8 status[0x8]; 5967 u8 reserved_at_8[0x18]; 5968 5969 u8 syndrome[0x20]; 5970 5971 u8 modify_header_id[0x20]; 5972 5973 u8 reserved_at_60[0x20]; 5974 }; 5975 5976 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5977 u8 opcode[0x10]; 5978 u8 reserved_at_10[0x10]; 5979 5980 u8 reserved_at_20[0x10]; 5981 u8 op_mod[0x10]; 5982 5983 u8 reserved_at_40[0x20]; 5984 5985 u8 table_type[0x8]; 5986 u8 reserved_at_68[0x10]; 5987 u8 num_of_actions[0x8]; 5988 5989 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5990 }; 5991 5992 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5993 u8 status[0x8]; 5994 u8 reserved_at_8[0x18]; 5995 5996 u8 syndrome[0x20]; 5997 5998 u8 reserved_at_40[0x40]; 5999 }; 6000 6001 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6002 u8 opcode[0x10]; 6003 u8 reserved_at_10[0x10]; 6004 6005 u8 reserved_at_20[0x10]; 6006 u8 op_mod[0x10]; 6007 6008 u8 modify_header_id[0x20]; 6009 6010 u8 reserved_at_60[0x20]; 6011 }; 6012 6013 struct mlx5_ifc_query_modify_header_context_in_bits { 6014 u8 opcode[0x10]; 6015 u8 uid[0x10]; 6016 6017 u8 reserved_at_20[0x10]; 6018 u8 op_mod[0x10]; 6019 6020 u8 modify_header_id[0x20]; 6021 6022 u8 reserved_at_60[0xa0]; 6023 }; 6024 6025 struct mlx5_ifc_query_dct_out_bits { 6026 u8 status[0x8]; 6027 u8 reserved_at_8[0x18]; 6028 6029 u8 syndrome[0x20]; 6030 6031 u8 reserved_at_40[0x40]; 6032 6033 struct mlx5_ifc_dctc_bits dct_context_entry; 6034 6035 u8 reserved_at_280[0x180]; 6036 }; 6037 6038 struct mlx5_ifc_query_dct_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_at_10[0x10]; 6041 6042 u8 reserved_at_20[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 reserved_at_40[0x8]; 6046 u8 dctn[0x18]; 6047 6048 u8 reserved_at_60[0x20]; 6049 }; 6050 6051 struct mlx5_ifc_query_cq_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_at_8[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_at_40[0x40]; 6058 6059 struct mlx5_ifc_cqc_bits cq_context; 6060 6061 u8 reserved_at_280[0x600]; 6062 6063 u8 pas[][0x40]; 6064 }; 6065 6066 struct mlx5_ifc_query_cq_in_bits { 6067 u8 opcode[0x10]; 6068 u8 reserved_at_10[0x10]; 6069 6070 u8 reserved_at_20[0x10]; 6071 u8 op_mod[0x10]; 6072 6073 u8 reserved_at_40[0x8]; 6074 u8 cqn[0x18]; 6075 6076 u8 reserved_at_60[0x20]; 6077 }; 6078 6079 struct mlx5_ifc_query_cong_status_out_bits { 6080 u8 status[0x8]; 6081 u8 reserved_at_8[0x18]; 6082 6083 u8 syndrome[0x20]; 6084 6085 u8 reserved_at_40[0x20]; 6086 6087 u8 enable[0x1]; 6088 u8 tag_enable[0x1]; 6089 u8 reserved_at_62[0x1e]; 6090 }; 6091 6092 struct mlx5_ifc_query_cong_status_in_bits { 6093 u8 opcode[0x10]; 6094 u8 reserved_at_10[0x10]; 6095 6096 u8 reserved_at_20[0x10]; 6097 u8 op_mod[0x10]; 6098 6099 u8 reserved_at_40[0x18]; 6100 u8 priority[0x4]; 6101 u8 cong_protocol[0x4]; 6102 6103 u8 reserved_at_60[0x20]; 6104 }; 6105 6106 struct mlx5_ifc_query_cong_statistics_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_at_8[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_at_40[0x40]; 6113 6114 u8 rp_cur_flows[0x20]; 6115 6116 u8 sum_flows[0x20]; 6117 6118 u8 rp_cnp_ignored_high[0x20]; 6119 6120 u8 rp_cnp_ignored_low[0x20]; 6121 6122 u8 rp_cnp_handled_high[0x20]; 6123 6124 u8 rp_cnp_handled_low[0x20]; 6125 6126 u8 reserved_at_140[0x100]; 6127 6128 u8 time_stamp_high[0x20]; 6129 6130 u8 time_stamp_low[0x20]; 6131 6132 u8 accumulators_period[0x20]; 6133 6134 u8 np_ecn_marked_roce_packets_high[0x20]; 6135 6136 u8 np_ecn_marked_roce_packets_low[0x20]; 6137 6138 u8 np_cnp_sent_high[0x20]; 6139 6140 u8 np_cnp_sent_low[0x20]; 6141 6142 u8 reserved_at_320[0x560]; 6143 }; 6144 6145 struct mlx5_ifc_query_cong_statistics_in_bits { 6146 u8 opcode[0x10]; 6147 u8 reserved_at_10[0x10]; 6148 6149 u8 reserved_at_20[0x10]; 6150 u8 op_mod[0x10]; 6151 6152 u8 clear[0x1]; 6153 u8 reserved_at_41[0x1f]; 6154 6155 u8 reserved_at_60[0x20]; 6156 }; 6157 6158 struct mlx5_ifc_query_cong_params_out_bits { 6159 u8 status[0x8]; 6160 u8 reserved_at_8[0x18]; 6161 6162 u8 syndrome[0x20]; 6163 6164 u8 reserved_at_40[0x40]; 6165 6166 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6167 }; 6168 6169 struct mlx5_ifc_query_cong_params_in_bits { 6170 u8 opcode[0x10]; 6171 u8 reserved_at_10[0x10]; 6172 6173 u8 reserved_at_20[0x10]; 6174 u8 op_mod[0x10]; 6175 6176 u8 reserved_at_40[0x1c]; 6177 u8 cong_protocol[0x4]; 6178 6179 u8 reserved_at_60[0x20]; 6180 }; 6181 6182 struct mlx5_ifc_query_adapter_out_bits { 6183 u8 status[0x8]; 6184 u8 reserved_at_8[0x18]; 6185 6186 u8 syndrome[0x20]; 6187 6188 u8 reserved_at_40[0x40]; 6189 6190 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6191 }; 6192 6193 struct mlx5_ifc_query_adapter_in_bits { 6194 u8 opcode[0x10]; 6195 u8 reserved_at_10[0x10]; 6196 6197 u8 reserved_at_20[0x10]; 6198 u8 op_mod[0x10]; 6199 6200 u8 reserved_at_40[0x40]; 6201 }; 6202 6203 struct mlx5_ifc_qp_2rst_out_bits { 6204 u8 status[0x8]; 6205 u8 reserved_at_8[0x18]; 6206 6207 u8 syndrome[0x20]; 6208 6209 u8 reserved_at_40[0x40]; 6210 }; 6211 6212 struct mlx5_ifc_qp_2rst_in_bits { 6213 u8 opcode[0x10]; 6214 u8 uid[0x10]; 6215 6216 u8 reserved_at_20[0x10]; 6217 u8 op_mod[0x10]; 6218 6219 u8 reserved_at_40[0x8]; 6220 u8 qpn[0x18]; 6221 6222 u8 reserved_at_60[0x20]; 6223 }; 6224 6225 struct mlx5_ifc_qp_2err_out_bits { 6226 u8 status[0x8]; 6227 u8 reserved_at_8[0x18]; 6228 6229 u8 syndrome[0x20]; 6230 6231 u8 reserved_at_40[0x40]; 6232 }; 6233 6234 struct mlx5_ifc_qp_2err_in_bits { 6235 u8 opcode[0x10]; 6236 u8 uid[0x10]; 6237 6238 u8 reserved_at_20[0x10]; 6239 u8 op_mod[0x10]; 6240 6241 u8 reserved_at_40[0x8]; 6242 u8 qpn[0x18]; 6243 6244 u8 reserved_at_60[0x20]; 6245 }; 6246 6247 struct mlx5_ifc_page_fault_resume_out_bits { 6248 u8 status[0x8]; 6249 u8 reserved_at_8[0x18]; 6250 6251 u8 syndrome[0x20]; 6252 6253 u8 reserved_at_40[0x40]; 6254 }; 6255 6256 struct mlx5_ifc_page_fault_resume_in_bits { 6257 u8 opcode[0x10]; 6258 u8 reserved_at_10[0x10]; 6259 6260 u8 reserved_at_20[0x10]; 6261 u8 op_mod[0x10]; 6262 6263 u8 error[0x1]; 6264 u8 reserved_at_41[0x4]; 6265 u8 page_fault_type[0x3]; 6266 u8 wq_number[0x18]; 6267 6268 u8 reserved_at_60[0x8]; 6269 u8 token[0x18]; 6270 }; 6271 6272 struct mlx5_ifc_nop_out_bits { 6273 u8 status[0x8]; 6274 u8 reserved_at_8[0x18]; 6275 6276 u8 syndrome[0x20]; 6277 6278 u8 reserved_at_40[0x40]; 6279 }; 6280 6281 struct mlx5_ifc_nop_in_bits { 6282 u8 opcode[0x10]; 6283 u8 reserved_at_10[0x10]; 6284 6285 u8 reserved_at_20[0x10]; 6286 u8 op_mod[0x10]; 6287 6288 u8 reserved_at_40[0x40]; 6289 }; 6290 6291 struct mlx5_ifc_modify_vport_state_out_bits { 6292 u8 status[0x8]; 6293 u8 reserved_at_8[0x18]; 6294 6295 u8 syndrome[0x20]; 6296 6297 u8 reserved_at_40[0x40]; 6298 }; 6299 6300 struct mlx5_ifc_modify_vport_state_in_bits { 6301 u8 opcode[0x10]; 6302 u8 reserved_at_10[0x10]; 6303 6304 u8 reserved_at_20[0x10]; 6305 u8 op_mod[0x10]; 6306 6307 u8 other_vport[0x1]; 6308 u8 reserved_at_41[0xf]; 6309 u8 vport_number[0x10]; 6310 6311 u8 reserved_at_60[0x18]; 6312 u8 admin_state[0x4]; 6313 u8 reserved_at_7c[0x4]; 6314 }; 6315 6316 struct mlx5_ifc_modify_tis_out_bits { 6317 u8 status[0x8]; 6318 u8 reserved_at_8[0x18]; 6319 6320 u8 syndrome[0x20]; 6321 6322 u8 reserved_at_40[0x40]; 6323 }; 6324 6325 struct mlx5_ifc_modify_tis_bitmask_bits { 6326 u8 reserved_at_0[0x20]; 6327 6328 u8 reserved_at_20[0x1d]; 6329 u8 lag_tx_port_affinity[0x1]; 6330 u8 strict_lag_tx_port_affinity[0x1]; 6331 u8 prio[0x1]; 6332 }; 6333 6334 struct mlx5_ifc_modify_tis_in_bits { 6335 u8 opcode[0x10]; 6336 u8 uid[0x10]; 6337 6338 u8 reserved_at_20[0x10]; 6339 u8 op_mod[0x10]; 6340 6341 u8 reserved_at_40[0x8]; 6342 u8 tisn[0x18]; 6343 6344 u8 reserved_at_60[0x20]; 6345 6346 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6347 6348 u8 reserved_at_c0[0x40]; 6349 6350 struct mlx5_ifc_tisc_bits ctx; 6351 }; 6352 6353 struct mlx5_ifc_modify_tir_bitmask_bits { 6354 u8 reserved_at_0[0x20]; 6355 6356 u8 reserved_at_20[0x1b]; 6357 u8 self_lb_en[0x1]; 6358 u8 reserved_at_3c[0x1]; 6359 u8 hash[0x1]; 6360 u8 reserved_at_3e[0x1]; 6361 u8 lro[0x1]; 6362 }; 6363 6364 struct mlx5_ifc_modify_tir_out_bits { 6365 u8 status[0x8]; 6366 u8 reserved_at_8[0x18]; 6367 6368 u8 syndrome[0x20]; 6369 6370 u8 reserved_at_40[0x40]; 6371 }; 6372 6373 struct mlx5_ifc_modify_tir_in_bits { 6374 u8 opcode[0x10]; 6375 u8 uid[0x10]; 6376 6377 u8 reserved_at_20[0x10]; 6378 u8 op_mod[0x10]; 6379 6380 u8 reserved_at_40[0x8]; 6381 u8 tirn[0x18]; 6382 6383 u8 reserved_at_60[0x20]; 6384 6385 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6386 6387 u8 reserved_at_c0[0x40]; 6388 6389 struct mlx5_ifc_tirc_bits ctx; 6390 }; 6391 6392 struct mlx5_ifc_modify_sq_out_bits { 6393 u8 status[0x8]; 6394 u8 reserved_at_8[0x18]; 6395 6396 u8 syndrome[0x20]; 6397 6398 u8 reserved_at_40[0x40]; 6399 }; 6400 6401 struct mlx5_ifc_modify_sq_in_bits { 6402 u8 opcode[0x10]; 6403 u8 uid[0x10]; 6404 6405 u8 reserved_at_20[0x10]; 6406 u8 op_mod[0x10]; 6407 6408 u8 sq_state[0x4]; 6409 u8 reserved_at_44[0x4]; 6410 u8 sqn[0x18]; 6411 6412 u8 reserved_at_60[0x20]; 6413 6414 u8 modify_bitmask[0x40]; 6415 6416 u8 reserved_at_c0[0x40]; 6417 6418 struct mlx5_ifc_sqc_bits ctx; 6419 }; 6420 6421 struct mlx5_ifc_modify_scheduling_element_out_bits { 6422 u8 status[0x8]; 6423 u8 reserved_at_8[0x18]; 6424 6425 u8 syndrome[0x20]; 6426 6427 u8 reserved_at_40[0x1c0]; 6428 }; 6429 6430 enum { 6431 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6432 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6433 }; 6434 6435 struct mlx5_ifc_modify_scheduling_element_in_bits { 6436 u8 opcode[0x10]; 6437 u8 reserved_at_10[0x10]; 6438 6439 u8 reserved_at_20[0x10]; 6440 u8 op_mod[0x10]; 6441 6442 u8 scheduling_hierarchy[0x8]; 6443 u8 reserved_at_48[0x18]; 6444 6445 u8 scheduling_element_id[0x20]; 6446 6447 u8 reserved_at_80[0x20]; 6448 6449 u8 modify_bitmask[0x20]; 6450 6451 u8 reserved_at_c0[0x40]; 6452 6453 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6454 6455 u8 reserved_at_300[0x100]; 6456 }; 6457 6458 struct mlx5_ifc_modify_rqt_out_bits { 6459 u8 status[0x8]; 6460 u8 reserved_at_8[0x18]; 6461 6462 u8 syndrome[0x20]; 6463 6464 u8 reserved_at_40[0x40]; 6465 }; 6466 6467 struct mlx5_ifc_rqt_bitmask_bits { 6468 u8 reserved_at_0[0x20]; 6469 6470 u8 reserved_at_20[0x1f]; 6471 u8 rqn_list[0x1]; 6472 }; 6473 6474 struct mlx5_ifc_modify_rqt_in_bits { 6475 u8 opcode[0x10]; 6476 u8 uid[0x10]; 6477 6478 u8 reserved_at_20[0x10]; 6479 u8 op_mod[0x10]; 6480 6481 u8 reserved_at_40[0x8]; 6482 u8 rqtn[0x18]; 6483 6484 u8 reserved_at_60[0x20]; 6485 6486 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6487 6488 u8 reserved_at_c0[0x40]; 6489 6490 struct mlx5_ifc_rqtc_bits ctx; 6491 }; 6492 6493 struct mlx5_ifc_modify_rq_out_bits { 6494 u8 status[0x8]; 6495 u8 reserved_at_8[0x18]; 6496 6497 u8 syndrome[0x20]; 6498 6499 u8 reserved_at_40[0x40]; 6500 }; 6501 6502 enum { 6503 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6504 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6505 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6506 }; 6507 6508 struct mlx5_ifc_modify_rq_in_bits { 6509 u8 opcode[0x10]; 6510 u8 uid[0x10]; 6511 6512 u8 reserved_at_20[0x10]; 6513 u8 op_mod[0x10]; 6514 6515 u8 rq_state[0x4]; 6516 u8 reserved_at_44[0x4]; 6517 u8 rqn[0x18]; 6518 6519 u8 reserved_at_60[0x20]; 6520 6521 u8 modify_bitmask[0x40]; 6522 6523 u8 reserved_at_c0[0x40]; 6524 6525 struct mlx5_ifc_rqc_bits ctx; 6526 }; 6527 6528 struct mlx5_ifc_modify_rmp_out_bits { 6529 u8 status[0x8]; 6530 u8 reserved_at_8[0x18]; 6531 6532 u8 syndrome[0x20]; 6533 6534 u8 reserved_at_40[0x40]; 6535 }; 6536 6537 struct mlx5_ifc_rmp_bitmask_bits { 6538 u8 reserved_at_0[0x20]; 6539 6540 u8 reserved_at_20[0x1f]; 6541 u8 lwm[0x1]; 6542 }; 6543 6544 struct mlx5_ifc_modify_rmp_in_bits { 6545 u8 opcode[0x10]; 6546 u8 uid[0x10]; 6547 6548 u8 reserved_at_20[0x10]; 6549 u8 op_mod[0x10]; 6550 6551 u8 rmp_state[0x4]; 6552 u8 reserved_at_44[0x4]; 6553 u8 rmpn[0x18]; 6554 6555 u8 reserved_at_60[0x20]; 6556 6557 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6558 6559 u8 reserved_at_c0[0x40]; 6560 6561 struct mlx5_ifc_rmpc_bits ctx; 6562 }; 6563 6564 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_at_8[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_at_40[0x40]; 6571 }; 6572 6573 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6574 u8 reserved_at_0[0x12]; 6575 u8 affiliation[0x1]; 6576 u8 reserved_at_13[0x1]; 6577 u8 disable_uc_local_lb[0x1]; 6578 u8 disable_mc_local_lb[0x1]; 6579 u8 node_guid[0x1]; 6580 u8 port_guid[0x1]; 6581 u8 min_inline[0x1]; 6582 u8 mtu[0x1]; 6583 u8 change_event[0x1]; 6584 u8 promisc[0x1]; 6585 u8 permanent_address[0x1]; 6586 u8 addresses_list[0x1]; 6587 u8 roce_en[0x1]; 6588 u8 reserved_at_1f[0x1]; 6589 }; 6590 6591 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6592 u8 opcode[0x10]; 6593 u8 reserved_at_10[0x10]; 6594 6595 u8 reserved_at_20[0x10]; 6596 u8 op_mod[0x10]; 6597 6598 u8 other_vport[0x1]; 6599 u8 reserved_at_41[0xf]; 6600 u8 vport_number[0x10]; 6601 6602 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6603 6604 u8 reserved_at_80[0x780]; 6605 6606 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6607 }; 6608 6609 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6610 u8 status[0x8]; 6611 u8 reserved_at_8[0x18]; 6612 6613 u8 syndrome[0x20]; 6614 6615 u8 reserved_at_40[0x40]; 6616 }; 6617 6618 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6619 u8 opcode[0x10]; 6620 u8 reserved_at_10[0x10]; 6621 6622 u8 reserved_at_20[0x10]; 6623 u8 op_mod[0x10]; 6624 6625 u8 other_vport[0x1]; 6626 u8 reserved_at_41[0xb]; 6627 u8 port_num[0x4]; 6628 u8 vport_number[0x10]; 6629 6630 u8 reserved_at_60[0x20]; 6631 6632 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6633 }; 6634 6635 struct mlx5_ifc_modify_cq_out_bits { 6636 u8 status[0x8]; 6637 u8 reserved_at_8[0x18]; 6638 6639 u8 syndrome[0x20]; 6640 6641 u8 reserved_at_40[0x40]; 6642 }; 6643 6644 enum { 6645 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6646 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6647 }; 6648 6649 struct mlx5_ifc_modify_cq_in_bits { 6650 u8 opcode[0x10]; 6651 u8 uid[0x10]; 6652 6653 u8 reserved_at_20[0x10]; 6654 u8 op_mod[0x10]; 6655 6656 u8 reserved_at_40[0x8]; 6657 u8 cqn[0x18]; 6658 6659 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6660 6661 struct mlx5_ifc_cqc_bits cq_context; 6662 6663 u8 reserved_at_280[0x60]; 6664 6665 u8 cq_umem_valid[0x1]; 6666 u8 reserved_at_2e1[0x1f]; 6667 6668 u8 reserved_at_300[0x580]; 6669 6670 u8 pas[][0x40]; 6671 }; 6672 6673 struct mlx5_ifc_modify_cong_status_out_bits { 6674 u8 status[0x8]; 6675 u8 reserved_at_8[0x18]; 6676 6677 u8 syndrome[0x20]; 6678 6679 u8 reserved_at_40[0x40]; 6680 }; 6681 6682 struct mlx5_ifc_modify_cong_status_in_bits { 6683 u8 opcode[0x10]; 6684 u8 reserved_at_10[0x10]; 6685 6686 u8 reserved_at_20[0x10]; 6687 u8 op_mod[0x10]; 6688 6689 u8 reserved_at_40[0x18]; 6690 u8 priority[0x4]; 6691 u8 cong_protocol[0x4]; 6692 6693 u8 enable[0x1]; 6694 u8 tag_enable[0x1]; 6695 u8 reserved_at_62[0x1e]; 6696 }; 6697 6698 struct mlx5_ifc_modify_cong_params_out_bits { 6699 u8 status[0x8]; 6700 u8 reserved_at_8[0x18]; 6701 6702 u8 syndrome[0x20]; 6703 6704 u8 reserved_at_40[0x40]; 6705 }; 6706 6707 struct mlx5_ifc_modify_cong_params_in_bits { 6708 u8 opcode[0x10]; 6709 u8 reserved_at_10[0x10]; 6710 6711 u8 reserved_at_20[0x10]; 6712 u8 op_mod[0x10]; 6713 6714 u8 reserved_at_40[0x1c]; 6715 u8 cong_protocol[0x4]; 6716 6717 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6718 6719 u8 reserved_at_80[0x80]; 6720 6721 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6722 }; 6723 6724 struct mlx5_ifc_manage_pages_out_bits { 6725 u8 status[0x8]; 6726 u8 reserved_at_8[0x18]; 6727 6728 u8 syndrome[0x20]; 6729 6730 u8 output_num_entries[0x20]; 6731 6732 u8 reserved_at_60[0x20]; 6733 6734 u8 pas[][0x40]; 6735 }; 6736 6737 enum { 6738 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6739 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6740 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6741 }; 6742 6743 struct mlx5_ifc_manage_pages_in_bits { 6744 u8 opcode[0x10]; 6745 u8 reserved_at_10[0x10]; 6746 6747 u8 reserved_at_20[0x10]; 6748 u8 op_mod[0x10]; 6749 6750 u8 embedded_cpu_function[0x1]; 6751 u8 reserved_at_41[0xf]; 6752 u8 function_id[0x10]; 6753 6754 u8 input_num_entries[0x20]; 6755 6756 u8 pas[][0x40]; 6757 }; 6758 6759 struct mlx5_ifc_mad_ifc_out_bits { 6760 u8 status[0x8]; 6761 u8 reserved_at_8[0x18]; 6762 6763 u8 syndrome[0x20]; 6764 6765 u8 reserved_at_40[0x40]; 6766 6767 u8 response_mad_packet[256][0x8]; 6768 }; 6769 6770 struct mlx5_ifc_mad_ifc_in_bits { 6771 u8 opcode[0x10]; 6772 u8 reserved_at_10[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 remote_lid[0x10]; 6778 u8 reserved_at_50[0x8]; 6779 u8 port[0x8]; 6780 6781 u8 reserved_at_60[0x20]; 6782 6783 u8 mad[256][0x8]; 6784 }; 6785 6786 struct mlx5_ifc_init_hca_out_bits { 6787 u8 status[0x8]; 6788 u8 reserved_at_8[0x18]; 6789 6790 u8 syndrome[0x20]; 6791 6792 u8 reserved_at_40[0x40]; 6793 }; 6794 6795 struct mlx5_ifc_init_hca_in_bits { 6796 u8 opcode[0x10]; 6797 u8 reserved_at_10[0x10]; 6798 6799 u8 reserved_at_20[0x10]; 6800 u8 op_mod[0x10]; 6801 6802 u8 reserved_at_40[0x40]; 6803 u8 sw_owner_id[4][0x20]; 6804 }; 6805 6806 struct mlx5_ifc_init2rtr_qp_out_bits { 6807 u8 status[0x8]; 6808 u8 reserved_at_8[0x18]; 6809 6810 u8 syndrome[0x20]; 6811 6812 u8 reserved_at_40[0x20]; 6813 u8 ece[0x20]; 6814 }; 6815 6816 struct mlx5_ifc_init2rtr_qp_in_bits { 6817 u8 opcode[0x10]; 6818 u8 uid[0x10]; 6819 6820 u8 reserved_at_20[0x10]; 6821 u8 op_mod[0x10]; 6822 6823 u8 reserved_at_40[0x8]; 6824 u8 qpn[0x18]; 6825 6826 u8 reserved_at_60[0x20]; 6827 6828 u8 opt_param_mask[0x20]; 6829 6830 u8 ece[0x20]; 6831 6832 struct mlx5_ifc_qpc_bits qpc; 6833 6834 u8 reserved_at_800[0x80]; 6835 }; 6836 6837 struct mlx5_ifc_init2init_qp_out_bits { 6838 u8 status[0x8]; 6839 u8 reserved_at_8[0x18]; 6840 6841 u8 syndrome[0x20]; 6842 6843 u8 reserved_at_40[0x20]; 6844 u8 ece[0x20]; 6845 }; 6846 6847 struct mlx5_ifc_init2init_qp_in_bits { 6848 u8 opcode[0x10]; 6849 u8 uid[0x10]; 6850 6851 u8 reserved_at_20[0x10]; 6852 u8 op_mod[0x10]; 6853 6854 u8 reserved_at_40[0x8]; 6855 u8 qpn[0x18]; 6856 6857 u8 reserved_at_60[0x20]; 6858 6859 u8 opt_param_mask[0x20]; 6860 6861 u8 ece[0x20]; 6862 6863 struct mlx5_ifc_qpc_bits qpc; 6864 6865 u8 reserved_at_800[0x80]; 6866 }; 6867 6868 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6869 u8 status[0x8]; 6870 u8 reserved_at_8[0x18]; 6871 6872 u8 syndrome[0x20]; 6873 6874 u8 reserved_at_40[0x40]; 6875 6876 u8 packet_headers_log[128][0x8]; 6877 6878 u8 packet_syndrome[64][0x8]; 6879 }; 6880 6881 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6882 u8 opcode[0x10]; 6883 u8 reserved_at_10[0x10]; 6884 6885 u8 reserved_at_20[0x10]; 6886 u8 op_mod[0x10]; 6887 6888 u8 reserved_at_40[0x40]; 6889 }; 6890 6891 struct mlx5_ifc_gen_eqe_in_bits { 6892 u8 opcode[0x10]; 6893 u8 reserved_at_10[0x10]; 6894 6895 u8 reserved_at_20[0x10]; 6896 u8 op_mod[0x10]; 6897 6898 u8 reserved_at_40[0x18]; 6899 u8 eq_number[0x8]; 6900 6901 u8 reserved_at_60[0x20]; 6902 6903 u8 eqe[64][0x8]; 6904 }; 6905 6906 struct mlx5_ifc_gen_eq_out_bits { 6907 u8 status[0x8]; 6908 u8 reserved_at_8[0x18]; 6909 6910 u8 syndrome[0x20]; 6911 6912 u8 reserved_at_40[0x40]; 6913 }; 6914 6915 struct mlx5_ifc_enable_hca_out_bits { 6916 u8 status[0x8]; 6917 u8 reserved_at_8[0x18]; 6918 6919 u8 syndrome[0x20]; 6920 6921 u8 reserved_at_40[0x20]; 6922 }; 6923 6924 struct mlx5_ifc_enable_hca_in_bits { 6925 u8 opcode[0x10]; 6926 u8 reserved_at_10[0x10]; 6927 6928 u8 reserved_at_20[0x10]; 6929 u8 op_mod[0x10]; 6930 6931 u8 embedded_cpu_function[0x1]; 6932 u8 reserved_at_41[0xf]; 6933 u8 function_id[0x10]; 6934 6935 u8 reserved_at_60[0x20]; 6936 }; 6937 6938 struct mlx5_ifc_drain_dct_out_bits { 6939 u8 status[0x8]; 6940 u8 reserved_at_8[0x18]; 6941 6942 u8 syndrome[0x20]; 6943 6944 u8 reserved_at_40[0x40]; 6945 }; 6946 6947 struct mlx5_ifc_drain_dct_in_bits { 6948 u8 opcode[0x10]; 6949 u8 uid[0x10]; 6950 6951 u8 reserved_at_20[0x10]; 6952 u8 op_mod[0x10]; 6953 6954 u8 reserved_at_40[0x8]; 6955 u8 dctn[0x18]; 6956 6957 u8 reserved_at_60[0x20]; 6958 }; 6959 6960 struct mlx5_ifc_disable_hca_out_bits { 6961 u8 status[0x8]; 6962 u8 reserved_at_8[0x18]; 6963 6964 u8 syndrome[0x20]; 6965 6966 u8 reserved_at_40[0x20]; 6967 }; 6968 6969 struct mlx5_ifc_disable_hca_in_bits { 6970 u8 opcode[0x10]; 6971 u8 reserved_at_10[0x10]; 6972 6973 u8 reserved_at_20[0x10]; 6974 u8 op_mod[0x10]; 6975 6976 u8 embedded_cpu_function[0x1]; 6977 u8 reserved_at_41[0xf]; 6978 u8 function_id[0x10]; 6979 6980 u8 reserved_at_60[0x20]; 6981 }; 6982 6983 struct mlx5_ifc_detach_from_mcg_out_bits { 6984 u8 status[0x8]; 6985 u8 reserved_at_8[0x18]; 6986 6987 u8 syndrome[0x20]; 6988 6989 u8 reserved_at_40[0x40]; 6990 }; 6991 6992 struct mlx5_ifc_detach_from_mcg_in_bits { 6993 u8 opcode[0x10]; 6994 u8 uid[0x10]; 6995 6996 u8 reserved_at_20[0x10]; 6997 u8 op_mod[0x10]; 6998 6999 u8 reserved_at_40[0x8]; 7000 u8 qpn[0x18]; 7001 7002 u8 reserved_at_60[0x20]; 7003 7004 u8 multicast_gid[16][0x8]; 7005 }; 7006 7007 struct mlx5_ifc_destroy_xrq_out_bits { 7008 u8 status[0x8]; 7009 u8 reserved_at_8[0x18]; 7010 7011 u8 syndrome[0x20]; 7012 7013 u8 reserved_at_40[0x40]; 7014 }; 7015 7016 struct mlx5_ifc_destroy_xrq_in_bits { 7017 u8 opcode[0x10]; 7018 u8 uid[0x10]; 7019 7020 u8 reserved_at_20[0x10]; 7021 u8 op_mod[0x10]; 7022 7023 u8 reserved_at_40[0x8]; 7024 u8 xrqn[0x18]; 7025 7026 u8 reserved_at_60[0x20]; 7027 }; 7028 7029 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7030 u8 status[0x8]; 7031 u8 reserved_at_8[0x18]; 7032 7033 u8 syndrome[0x20]; 7034 7035 u8 reserved_at_40[0x40]; 7036 }; 7037 7038 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7039 u8 opcode[0x10]; 7040 u8 uid[0x10]; 7041 7042 u8 reserved_at_20[0x10]; 7043 u8 op_mod[0x10]; 7044 7045 u8 reserved_at_40[0x8]; 7046 u8 xrc_srqn[0x18]; 7047 7048 u8 reserved_at_60[0x20]; 7049 }; 7050 7051 struct mlx5_ifc_destroy_tis_out_bits { 7052 u8 status[0x8]; 7053 u8 reserved_at_8[0x18]; 7054 7055 u8 syndrome[0x20]; 7056 7057 u8 reserved_at_40[0x40]; 7058 }; 7059 7060 struct mlx5_ifc_destroy_tis_in_bits { 7061 u8 opcode[0x10]; 7062 u8 uid[0x10]; 7063 7064 u8 reserved_at_20[0x10]; 7065 u8 op_mod[0x10]; 7066 7067 u8 reserved_at_40[0x8]; 7068 u8 tisn[0x18]; 7069 7070 u8 reserved_at_60[0x20]; 7071 }; 7072 7073 struct mlx5_ifc_destroy_tir_out_bits { 7074 u8 status[0x8]; 7075 u8 reserved_at_8[0x18]; 7076 7077 u8 syndrome[0x20]; 7078 7079 u8 reserved_at_40[0x40]; 7080 }; 7081 7082 struct mlx5_ifc_destroy_tir_in_bits { 7083 u8 opcode[0x10]; 7084 u8 uid[0x10]; 7085 7086 u8 reserved_at_20[0x10]; 7087 u8 op_mod[0x10]; 7088 7089 u8 reserved_at_40[0x8]; 7090 u8 tirn[0x18]; 7091 7092 u8 reserved_at_60[0x20]; 7093 }; 7094 7095 struct mlx5_ifc_destroy_srq_out_bits { 7096 u8 status[0x8]; 7097 u8 reserved_at_8[0x18]; 7098 7099 u8 syndrome[0x20]; 7100 7101 u8 reserved_at_40[0x40]; 7102 }; 7103 7104 struct mlx5_ifc_destroy_srq_in_bits { 7105 u8 opcode[0x10]; 7106 u8 uid[0x10]; 7107 7108 u8 reserved_at_20[0x10]; 7109 u8 op_mod[0x10]; 7110 7111 u8 reserved_at_40[0x8]; 7112 u8 srqn[0x18]; 7113 7114 u8 reserved_at_60[0x20]; 7115 }; 7116 7117 struct mlx5_ifc_destroy_sq_out_bits { 7118 u8 status[0x8]; 7119 u8 reserved_at_8[0x18]; 7120 7121 u8 syndrome[0x20]; 7122 7123 u8 reserved_at_40[0x40]; 7124 }; 7125 7126 struct mlx5_ifc_destroy_sq_in_bits { 7127 u8 opcode[0x10]; 7128 u8 uid[0x10]; 7129 7130 u8 reserved_at_20[0x10]; 7131 u8 op_mod[0x10]; 7132 7133 u8 reserved_at_40[0x8]; 7134 u8 sqn[0x18]; 7135 7136 u8 reserved_at_60[0x20]; 7137 }; 7138 7139 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7140 u8 status[0x8]; 7141 u8 reserved_at_8[0x18]; 7142 7143 u8 syndrome[0x20]; 7144 7145 u8 reserved_at_40[0x1c0]; 7146 }; 7147 7148 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7149 u8 opcode[0x10]; 7150 u8 reserved_at_10[0x10]; 7151 7152 u8 reserved_at_20[0x10]; 7153 u8 op_mod[0x10]; 7154 7155 u8 scheduling_hierarchy[0x8]; 7156 u8 reserved_at_48[0x18]; 7157 7158 u8 scheduling_element_id[0x20]; 7159 7160 u8 reserved_at_80[0x180]; 7161 }; 7162 7163 struct mlx5_ifc_destroy_rqt_out_bits { 7164 u8 status[0x8]; 7165 u8 reserved_at_8[0x18]; 7166 7167 u8 syndrome[0x20]; 7168 7169 u8 reserved_at_40[0x40]; 7170 }; 7171 7172 struct mlx5_ifc_destroy_rqt_in_bits { 7173 u8 opcode[0x10]; 7174 u8 uid[0x10]; 7175 7176 u8 reserved_at_20[0x10]; 7177 u8 op_mod[0x10]; 7178 7179 u8 reserved_at_40[0x8]; 7180 u8 rqtn[0x18]; 7181 7182 u8 reserved_at_60[0x20]; 7183 }; 7184 7185 struct mlx5_ifc_destroy_rq_out_bits { 7186 u8 status[0x8]; 7187 u8 reserved_at_8[0x18]; 7188 7189 u8 syndrome[0x20]; 7190 7191 u8 reserved_at_40[0x40]; 7192 }; 7193 7194 struct mlx5_ifc_destroy_rq_in_bits { 7195 u8 opcode[0x10]; 7196 u8 uid[0x10]; 7197 7198 u8 reserved_at_20[0x10]; 7199 u8 op_mod[0x10]; 7200 7201 u8 reserved_at_40[0x8]; 7202 u8 rqn[0x18]; 7203 7204 u8 reserved_at_60[0x20]; 7205 }; 7206 7207 struct mlx5_ifc_set_delay_drop_params_in_bits { 7208 u8 opcode[0x10]; 7209 u8 reserved_at_10[0x10]; 7210 7211 u8 reserved_at_20[0x10]; 7212 u8 op_mod[0x10]; 7213 7214 u8 reserved_at_40[0x20]; 7215 7216 u8 reserved_at_60[0x10]; 7217 u8 delay_drop_timeout[0x10]; 7218 }; 7219 7220 struct mlx5_ifc_set_delay_drop_params_out_bits { 7221 u8 status[0x8]; 7222 u8 reserved_at_8[0x18]; 7223 7224 u8 syndrome[0x20]; 7225 7226 u8 reserved_at_40[0x40]; 7227 }; 7228 7229 struct mlx5_ifc_destroy_rmp_out_bits { 7230 u8 status[0x8]; 7231 u8 reserved_at_8[0x18]; 7232 7233 u8 syndrome[0x20]; 7234 7235 u8 reserved_at_40[0x40]; 7236 }; 7237 7238 struct mlx5_ifc_destroy_rmp_in_bits { 7239 u8 opcode[0x10]; 7240 u8 uid[0x10]; 7241 7242 u8 reserved_at_20[0x10]; 7243 u8 op_mod[0x10]; 7244 7245 u8 reserved_at_40[0x8]; 7246 u8 rmpn[0x18]; 7247 7248 u8 reserved_at_60[0x20]; 7249 }; 7250 7251 struct mlx5_ifc_destroy_qp_out_bits { 7252 u8 status[0x8]; 7253 u8 reserved_at_8[0x18]; 7254 7255 u8 syndrome[0x20]; 7256 7257 u8 reserved_at_40[0x40]; 7258 }; 7259 7260 struct mlx5_ifc_destroy_qp_in_bits { 7261 u8 opcode[0x10]; 7262 u8 uid[0x10]; 7263 7264 u8 reserved_at_20[0x10]; 7265 u8 op_mod[0x10]; 7266 7267 u8 reserved_at_40[0x8]; 7268 u8 qpn[0x18]; 7269 7270 u8 reserved_at_60[0x20]; 7271 }; 7272 7273 struct mlx5_ifc_destroy_psv_out_bits { 7274 u8 status[0x8]; 7275 u8 reserved_at_8[0x18]; 7276 7277 u8 syndrome[0x20]; 7278 7279 u8 reserved_at_40[0x40]; 7280 }; 7281 7282 struct mlx5_ifc_destroy_psv_in_bits { 7283 u8 opcode[0x10]; 7284 u8 reserved_at_10[0x10]; 7285 7286 u8 reserved_at_20[0x10]; 7287 u8 op_mod[0x10]; 7288 7289 u8 reserved_at_40[0x8]; 7290 u8 psvn[0x18]; 7291 7292 u8 reserved_at_60[0x20]; 7293 }; 7294 7295 struct mlx5_ifc_destroy_mkey_out_bits { 7296 u8 status[0x8]; 7297 u8 reserved_at_8[0x18]; 7298 7299 u8 syndrome[0x20]; 7300 7301 u8 reserved_at_40[0x40]; 7302 }; 7303 7304 struct mlx5_ifc_destroy_mkey_in_bits { 7305 u8 opcode[0x10]; 7306 u8 uid[0x10]; 7307 7308 u8 reserved_at_20[0x10]; 7309 u8 op_mod[0x10]; 7310 7311 u8 reserved_at_40[0x8]; 7312 u8 mkey_index[0x18]; 7313 7314 u8 reserved_at_60[0x20]; 7315 }; 7316 7317 struct mlx5_ifc_destroy_flow_table_out_bits { 7318 u8 status[0x8]; 7319 u8 reserved_at_8[0x18]; 7320 7321 u8 syndrome[0x20]; 7322 7323 u8 reserved_at_40[0x40]; 7324 }; 7325 7326 struct mlx5_ifc_destroy_flow_table_in_bits { 7327 u8 opcode[0x10]; 7328 u8 reserved_at_10[0x10]; 7329 7330 u8 reserved_at_20[0x10]; 7331 u8 op_mod[0x10]; 7332 7333 u8 other_vport[0x1]; 7334 u8 reserved_at_41[0xf]; 7335 u8 vport_number[0x10]; 7336 7337 u8 reserved_at_60[0x20]; 7338 7339 u8 table_type[0x8]; 7340 u8 reserved_at_88[0x18]; 7341 7342 u8 reserved_at_a0[0x8]; 7343 u8 table_id[0x18]; 7344 7345 u8 reserved_at_c0[0x140]; 7346 }; 7347 7348 struct mlx5_ifc_destroy_flow_group_out_bits { 7349 u8 status[0x8]; 7350 u8 reserved_at_8[0x18]; 7351 7352 u8 syndrome[0x20]; 7353 7354 u8 reserved_at_40[0x40]; 7355 }; 7356 7357 struct mlx5_ifc_destroy_flow_group_in_bits { 7358 u8 opcode[0x10]; 7359 u8 reserved_at_10[0x10]; 7360 7361 u8 reserved_at_20[0x10]; 7362 u8 op_mod[0x10]; 7363 7364 u8 other_vport[0x1]; 7365 u8 reserved_at_41[0xf]; 7366 u8 vport_number[0x10]; 7367 7368 u8 reserved_at_60[0x20]; 7369 7370 u8 table_type[0x8]; 7371 u8 reserved_at_88[0x18]; 7372 7373 u8 reserved_at_a0[0x8]; 7374 u8 table_id[0x18]; 7375 7376 u8 group_id[0x20]; 7377 7378 u8 reserved_at_e0[0x120]; 7379 }; 7380 7381 struct mlx5_ifc_destroy_eq_out_bits { 7382 u8 status[0x8]; 7383 u8 reserved_at_8[0x18]; 7384 7385 u8 syndrome[0x20]; 7386 7387 u8 reserved_at_40[0x40]; 7388 }; 7389 7390 struct mlx5_ifc_destroy_eq_in_bits { 7391 u8 opcode[0x10]; 7392 u8 reserved_at_10[0x10]; 7393 7394 u8 reserved_at_20[0x10]; 7395 u8 op_mod[0x10]; 7396 7397 u8 reserved_at_40[0x18]; 7398 u8 eq_number[0x8]; 7399 7400 u8 reserved_at_60[0x20]; 7401 }; 7402 7403 struct mlx5_ifc_destroy_dct_out_bits { 7404 u8 status[0x8]; 7405 u8 reserved_at_8[0x18]; 7406 7407 u8 syndrome[0x20]; 7408 7409 u8 reserved_at_40[0x40]; 7410 }; 7411 7412 struct mlx5_ifc_destroy_dct_in_bits { 7413 u8 opcode[0x10]; 7414 u8 uid[0x10]; 7415 7416 u8 reserved_at_20[0x10]; 7417 u8 op_mod[0x10]; 7418 7419 u8 reserved_at_40[0x8]; 7420 u8 dctn[0x18]; 7421 7422 u8 reserved_at_60[0x20]; 7423 }; 7424 7425 struct mlx5_ifc_destroy_cq_out_bits { 7426 u8 status[0x8]; 7427 u8 reserved_at_8[0x18]; 7428 7429 u8 syndrome[0x20]; 7430 7431 u8 reserved_at_40[0x40]; 7432 }; 7433 7434 struct mlx5_ifc_destroy_cq_in_bits { 7435 u8 opcode[0x10]; 7436 u8 uid[0x10]; 7437 7438 u8 reserved_at_20[0x10]; 7439 u8 op_mod[0x10]; 7440 7441 u8 reserved_at_40[0x8]; 7442 u8 cqn[0x18]; 7443 7444 u8 reserved_at_60[0x20]; 7445 }; 7446 7447 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7448 u8 status[0x8]; 7449 u8 reserved_at_8[0x18]; 7450 7451 u8 syndrome[0x20]; 7452 7453 u8 reserved_at_40[0x40]; 7454 }; 7455 7456 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7457 u8 opcode[0x10]; 7458 u8 reserved_at_10[0x10]; 7459 7460 u8 reserved_at_20[0x10]; 7461 u8 op_mod[0x10]; 7462 7463 u8 reserved_at_40[0x20]; 7464 7465 u8 reserved_at_60[0x10]; 7466 u8 vxlan_udp_port[0x10]; 7467 }; 7468 7469 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7470 u8 status[0x8]; 7471 u8 reserved_at_8[0x18]; 7472 7473 u8 syndrome[0x20]; 7474 7475 u8 reserved_at_40[0x40]; 7476 }; 7477 7478 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7479 u8 opcode[0x10]; 7480 u8 reserved_at_10[0x10]; 7481 7482 u8 reserved_at_20[0x10]; 7483 u8 op_mod[0x10]; 7484 7485 u8 reserved_at_40[0x60]; 7486 7487 u8 reserved_at_a0[0x8]; 7488 u8 table_index[0x18]; 7489 7490 u8 reserved_at_c0[0x140]; 7491 }; 7492 7493 struct mlx5_ifc_delete_fte_out_bits { 7494 u8 status[0x8]; 7495 u8 reserved_at_8[0x18]; 7496 7497 u8 syndrome[0x20]; 7498 7499 u8 reserved_at_40[0x40]; 7500 }; 7501 7502 struct mlx5_ifc_delete_fte_in_bits { 7503 u8 opcode[0x10]; 7504 u8 reserved_at_10[0x10]; 7505 7506 u8 reserved_at_20[0x10]; 7507 u8 op_mod[0x10]; 7508 7509 u8 other_vport[0x1]; 7510 u8 reserved_at_41[0xf]; 7511 u8 vport_number[0x10]; 7512 7513 u8 reserved_at_60[0x20]; 7514 7515 u8 table_type[0x8]; 7516 u8 reserved_at_88[0x18]; 7517 7518 u8 reserved_at_a0[0x8]; 7519 u8 table_id[0x18]; 7520 7521 u8 reserved_at_c0[0x40]; 7522 7523 u8 flow_index[0x20]; 7524 7525 u8 reserved_at_120[0xe0]; 7526 }; 7527 7528 struct mlx5_ifc_dealloc_xrcd_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x40]; 7535 }; 7536 7537 struct mlx5_ifc_dealloc_xrcd_in_bits { 7538 u8 opcode[0x10]; 7539 u8 uid[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 reserved_at_40[0x8]; 7545 u8 xrcd[0x18]; 7546 7547 u8 reserved_at_60[0x20]; 7548 }; 7549 7550 struct mlx5_ifc_dealloc_uar_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x40]; 7557 }; 7558 7559 struct mlx5_ifc_dealloc_uar_in_bits { 7560 u8 opcode[0x10]; 7561 u8 reserved_at_10[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 reserved_at_40[0x8]; 7567 u8 uar[0x18]; 7568 7569 u8 reserved_at_60[0x20]; 7570 }; 7571 7572 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7573 u8 status[0x8]; 7574 u8 reserved_at_8[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 reserved_at_40[0x40]; 7579 }; 7580 7581 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7582 u8 opcode[0x10]; 7583 u8 uid[0x10]; 7584 7585 u8 reserved_at_20[0x10]; 7586 u8 op_mod[0x10]; 7587 7588 u8 reserved_at_40[0x8]; 7589 u8 transport_domain[0x18]; 7590 7591 u8 reserved_at_60[0x20]; 7592 }; 7593 7594 struct mlx5_ifc_dealloc_q_counter_out_bits { 7595 u8 status[0x8]; 7596 u8 reserved_at_8[0x18]; 7597 7598 u8 syndrome[0x20]; 7599 7600 u8 reserved_at_40[0x40]; 7601 }; 7602 7603 struct mlx5_ifc_dealloc_q_counter_in_bits { 7604 u8 opcode[0x10]; 7605 u8 reserved_at_10[0x10]; 7606 7607 u8 reserved_at_20[0x10]; 7608 u8 op_mod[0x10]; 7609 7610 u8 reserved_at_40[0x18]; 7611 u8 counter_set_id[0x8]; 7612 7613 u8 reserved_at_60[0x20]; 7614 }; 7615 7616 struct mlx5_ifc_dealloc_pd_out_bits { 7617 u8 status[0x8]; 7618 u8 reserved_at_8[0x18]; 7619 7620 u8 syndrome[0x20]; 7621 7622 u8 reserved_at_40[0x40]; 7623 }; 7624 7625 struct mlx5_ifc_dealloc_pd_in_bits { 7626 u8 opcode[0x10]; 7627 u8 uid[0x10]; 7628 7629 u8 reserved_at_20[0x10]; 7630 u8 op_mod[0x10]; 7631 7632 u8 reserved_at_40[0x8]; 7633 u8 pd[0x18]; 7634 7635 u8 reserved_at_60[0x20]; 7636 }; 7637 7638 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7639 u8 status[0x8]; 7640 u8 reserved_at_8[0x18]; 7641 7642 u8 syndrome[0x20]; 7643 7644 u8 reserved_at_40[0x40]; 7645 }; 7646 7647 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7648 u8 opcode[0x10]; 7649 u8 reserved_at_10[0x10]; 7650 7651 u8 reserved_at_20[0x10]; 7652 u8 op_mod[0x10]; 7653 7654 u8 flow_counter_id[0x20]; 7655 7656 u8 reserved_at_60[0x20]; 7657 }; 7658 7659 struct mlx5_ifc_create_xrq_out_bits { 7660 u8 status[0x8]; 7661 u8 reserved_at_8[0x18]; 7662 7663 u8 syndrome[0x20]; 7664 7665 u8 reserved_at_40[0x8]; 7666 u8 xrqn[0x18]; 7667 7668 u8 reserved_at_60[0x20]; 7669 }; 7670 7671 struct mlx5_ifc_create_xrq_in_bits { 7672 u8 opcode[0x10]; 7673 u8 uid[0x10]; 7674 7675 u8 reserved_at_20[0x10]; 7676 u8 op_mod[0x10]; 7677 7678 u8 reserved_at_40[0x40]; 7679 7680 struct mlx5_ifc_xrqc_bits xrq_context; 7681 }; 7682 7683 struct mlx5_ifc_create_xrc_srq_out_bits { 7684 u8 status[0x8]; 7685 u8 reserved_at_8[0x18]; 7686 7687 u8 syndrome[0x20]; 7688 7689 u8 reserved_at_40[0x8]; 7690 u8 xrc_srqn[0x18]; 7691 7692 u8 reserved_at_60[0x20]; 7693 }; 7694 7695 struct mlx5_ifc_create_xrc_srq_in_bits { 7696 u8 opcode[0x10]; 7697 u8 uid[0x10]; 7698 7699 u8 reserved_at_20[0x10]; 7700 u8 op_mod[0x10]; 7701 7702 u8 reserved_at_40[0x40]; 7703 7704 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7705 7706 u8 reserved_at_280[0x60]; 7707 7708 u8 xrc_srq_umem_valid[0x1]; 7709 u8 reserved_at_2e1[0x1f]; 7710 7711 u8 reserved_at_300[0x580]; 7712 7713 u8 pas[][0x40]; 7714 }; 7715 7716 struct mlx5_ifc_create_tis_out_bits { 7717 u8 status[0x8]; 7718 u8 reserved_at_8[0x18]; 7719 7720 u8 syndrome[0x20]; 7721 7722 u8 reserved_at_40[0x8]; 7723 u8 tisn[0x18]; 7724 7725 u8 reserved_at_60[0x20]; 7726 }; 7727 7728 struct mlx5_ifc_create_tis_in_bits { 7729 u8 opcode[0x10]; 7730 u8 uid[0x10]; 7731 7732 u8 reserved_at_20[0x10]; 7733 u8 op_mod[0x10]; 7734 7735 u8 reserved_at_40[0xc0]; 7736 7737 struct mlx5_ifc_tisc_bits ctx; 7738 }; 7739 7740 struct mlx5_ifc_create_tir_out_bits { 7741 u8 status[0x8]; 7742 u8 icm_address_63_40[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 icm_address_39_32[0x8]; 7747 u8 tirn[0x18]; 7748 7749 u8 icm_address_31_0[0x20]; 7750 }; 7751 7752 struct mlx5_ifc_create_tir_in_bits { 7753 u8 opcode[0x10]; 7754 u8 uid[0x10]; 7755 7756 u8 reserved_at_20[0x10]; 7757 u8 op_mod[0x10]; 7758 7759 u8 reserved_at_40[0xc0]; 7760 7761 struct mlx5_ifc_tirc_bits ctx; 7762 }; 7763 7764 struct mlx5_ifc_create_srq_out_bits { 7765 u8 status[0x8]; 7766 u8 reserved_at_8[0x18]; 7767 7768 u8 syndrome[0x20]; 7769 7770 u8 reserved_at_40[0x8]; 7771 u8 srqn[0x18]; 7772 7773 u8 reserved_at_60[0x20]; 7774 }; 7775 7776 struct mlx5_ifc_create_srq_in_bits { 7777 u8 opcode[0x10]; 7778 u8 uid[0x10]; 7779 7780 u8 reserved_at_20[0x10]; 7781 u8 op_mod[0x10]; 7782 7783 u8 reserved_at_40[0x40]; 7784 7785 struct mlx5_ifc_srqc_bits srq_context_entry; 7786 7787 u8 reserved_at_280[0x600]; 7788 7789 u8 pas[][0x40]; 7790 }; 7791 7792 struct mlx5_ifc_create_sq_out_bits { 7793 u8 status[0x8]; 7794 u8 reserved_at_8[0x18]; 7795 7796 u8 syndrome[0x20]; 7797 7798 u8 reserved_at_40[0x8]; 7799 u8 sqn[0x18]; 7800 7801 u8 reserved_at_60[0x20]; 7802 }; 7803 7804 struct mlx5_ifc_create_sq_in_bits { 7805 u8 opcode[0x10]; 7806 u8 uid[0x10]; 7807 7808 u8 reserved_at_20[0x10]; 7809 u8 op_mod[0x10]; 7810 7811 u8 reserved_at_40[0xc0]; 7812 7813 struct mlx5_ifc_sqc_bits ctx; 7814 }; 7815 7816 struct mlx5_ifc_create_scheduling_element_out_bits { 7817 u8 status[0x8]; 7818 u8 reserved_at_8[0x18]; 7819 7820 u8 syndrome[0x20]; 7821 7822 u8 reserved_at_40[0x40]; 7823 7824 u8 scheduling_element_id[0x20]; 7825 7826 u8 reserved_at_a0[0x160]; 7827 }; 7828 7829 struct mlx5_ifc_create_scheduling_element_in_bits { 7830 u8 opcode[0x10]; 7831 u8 reserved_at_10[0x10]; 7832 7833 u8 reserved_at_20[0x10]; 7834 u8 op_mod[0x10]; 7835 7836 u8 scheduling_hierarchy[0x8]; 7837 u8 reserved_at_48[0x18]; 7838 7839 u8 reserved_at_60[0xa0]; 7840 7841 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7842 7843 u8 reserved_at_300[0x100]; 7844 }; 7845 7846 struct mlx5_ifc_create_rqt_out_bits { 7847 u8 status[0x8]; 7848 u8 reserved_at_8[0x18]; 7849 7850 u8 syndrome[0x20]; 7851 7852 u8 reserved_at_40[0x8]; 7853 u8 rqtn[0x18]; 7854 7855 u8 reserved_at_60[0x20]; 7856 }; 7857 7858 struct mlx5_ifc_create_rqt_in_bits { 7859 u8 opcode[0x10]; 7860 u8 uid[0x10]; 7861 7862 u8 reserved_at_20[0x10]; 7863 u8 op_mod[0x10]; 7864 7865 u8 reserved_at_40[0xc0]; 7866 7867 struct mlx5_ifc_rqtc_bits rqt_context; 7868 }; 7869 7870 struct mlx5_ifc_create_rq_out_bits { 7871 u8 status[0x8]; 7872 u8 reserved_at_8[0x18]; 7873 7874 u8 syndrome[0x20]; 7875 7876 u8 reserved_at_40[0x8]; 7877 u8 rqn[0x18]; 7878 7879 u8 reserved_at_60[0x20]; 7880 }; 7881 7882 struct mlx5_ifc_create_rq_in_bits { 7883 u8 opcode[0x10]; 7884 u8 uid[0x10]; 7885 7886 u8 reserved_at_20[0x10]; 7887 u8 op_mod[0x10]; 7888 7889 u8 reserved_at_40[0xc0]; 7890 7891 struct mlx5_ifc_rqc_bits ctx; 7892 }; 7893 7894 struct mlx5_ifc_create_rmp_out_bits { 7895 u8 status[0x8]; 7896 u8 reserved_at_8[0x18]; 7897 7898 u8 syndrome[0x20]; 7899 7900 u8 reserved_at_40[0x8]; 7901 u8 rmpn[0x18]; 7902 7903 u8 reserved_at_60[0x20]; 7904 }; 7905 7906 struct mlx5_ifc_create_rmp_in_bits { 7907 u8 opcode[0x10]; 7908 u8 uid[0x10]; 7909 7910 u8 reserved_at_20[0x10]; 7911 u8 op_mod[0x10]; 7912 7913 u8 reserved_at_40[0xc0]; 7914 7915 struct mlx5_ifc_rmpc_bits ctx; 7916 }; 7917 7918 struct mlx5_ifc_create_qp_out_bits { 7919 u8 status[0x8]; 7920 u8 reserved_at_8[0x18]; 7921 7922 u8 syndrome[0x20]; 7923 7924 u8 reserved_at_40[0x8]; 7925 u8 qpn[0x18]; 7926 7927 u8 ece[0x20]; 7928 }; 7929 7930 struct mlx5_ifc_create_qp_in_bits { 7931 u8 opcode[0x10]; 7932 u8 uid[0x10]; 7933 7934 u8 reserved_at_20[0x10]; 7935 u8 op_mod[0x10]; 7936 7937 u8 reserved_at_40[0x8]; 7938 u8 input_qpn[0x18]; 7939 7940 u8 reserved_at_60[0x20]; 7941 u8 opt_param_mask[0x20]; 7942 7943 u8 ece[0x20]; 7944 7945 struct mlx5_ifc_qpc_bits qpc; 7946 7947 u8 reserved_at_800[0x60]; 7948 7949 u8 wq_umem_valid[0x1]; 7950 u8 reserved_at_861[0x1f]; 7951 7952 u8 pas[][0x40]; 7953 }; 7954 7955 struct mlx5_ifc_create_psv_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x40]; 7962 7963 u8 reserved_at_80[0x8]; 7964 u8 psv0_index[0x18]; 7965 7966 u8 reserved_at_a0[0x8]; 7967 u8 psv1_index[0x18]; 7968 7969 u8 reserved_at_c0[0x8]; 7970 u8 psv2_index[0x18]; 7971 7972 u8 reserved_at_e0[0x8]; 7973 u8 psv3_index[0x18]; 7974 }; 7975 7976 struct mlx5_ifc_create_psv_in_bits { 7977 u8 opcode[0x10]; 7978 u8 reserved_at_10[0x10]; 7979 7980 u8 reserved_at_20[0x10]; 7981 u8 op_mod[0x10]; 7982 7983 u8 num_psv[0x4]; 7984 u8 reserved_at_44[0x4]; 7985 u8 pd[0x18]; 7986 7987 u8 reserved_at_60[0x20]; 7988 }; 7989 7990 struct mlx5_ifc_create_mkey_out_bits { 7991 u8 status[0x8]; 7992 u8 reserved_at_8[0x18]; 7993 7994 u8 syndrome[0x20]; 7995 7996 u8 reserved_at_40[0x8]; 7997 u8 mkey_index[0x18]; 7998 7999 u8 reserved_at_60[0x20]; 8000 }; 8001 8002 struct mlx5_ifc_create_mkey_in_bits { 8003 u8 opcode[0x10]; 8004 u8 uid[0x10]; 8005 8006 u8 reserved_at_20[0x10]; 8007 u8 op_mod[0x10]; 8008 8009 u8 reserved_at_40[0x20]; 8010 8011 u8 pg_access[0x1]; 8012 u8 mkey_umem_valid[0x1]; 8013 u8 reserved_at_62[0x1e]; 8014 8015 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8016 8017 u8 reserved_at_280[0x80]; 8018 8019 u8 translations_octword_actual_size[0x20]; 8020 8021 u8 reserved_at_320[0x560]; 8022 8023 u8 klm_pas_mtt[][0x20]; 8024 }; 8025 8026 enum { 8027 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8028 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8029 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8030 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8031 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8032 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8033 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8034 }; 8035 8036 struct mlx5_ifc_create_flow_table_out_bits { 8037 u8 status[0x8]; 8038 u8 icm_address_63_40[0x18]; 8039 8040 u8 syndrome[0x20]; 8041 8042 u8 icm_address_39_32[0x8]; 8043 u8 table_id[0x18]; 8044 8045 u8 icm_address_31_0[0x20]; 8046 }; 8047 8048 struct mlx5_ifc_create_flow_table_in_bits { 8049 u8 opcode[0x10]; 8050 u8 reserved_at_10[0x10]; 8051 8052 u8 reserved_at_20[0x10]; 8053 u8 op_mod[0x10]; 8054 8055 u8 other_vport[0x1]; 8056 u8 reserved_at_41[0xf]; 8057 u8 vport_number[0x10]; 8058 8059 u8 reserved_at_60[0x20]; 8060 8061 u8 table_type[0x8]; 8062 u8 reserved_at_88[0x18]; 8063 8064 u8 reserved_at_a0[0x20]; 8065 8066 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8067 }; 8068 8069 struct mlx5_ifc_create_flow_group_out_bits { 8070 u8 status[0x8]; 8071 u8 reserved_at_8[0x18]; 8072 8073 u8 syndrome[0x20]; 8074 8075 u8 reserved_at_40[0x8]; 8076 u8 group_id[0x18]; 8077 8078 u8 reserved_at_60[0x20]; 8079 }; 8080 8081 enum { 8082 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8083 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8084 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8085 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8086 }; 8087 8088 struct mlx5_ifc_create_flow_group_in_bits { 8089 u8 opcode[0x10]; 8090 u8 reserved_at_10[0x10]; 8091 8092 u8 reserved_at_20[0x10]; 8093 u8 op_mod[0x10]; 8094 8095 u8 other_vport[0x1]; 8096 u8 reserved_at_41[0xf]; 8097 u8 vport_number[0x10]; 8098 8099 u8 reserved_at_60[0x20]; 8100 8101 u8 table_type[0x8]; 8102 u8 reserved_at_88[0x18]; 8103 8104 u8 reserved_at_a0[0x8]; 8105 u8 table_id[0x18]; 8106 8107 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8108 8109 u8 reserved_at_c1[0x1f]; 8110 8111 u8 start_flow_index[0x20]; 8112 8113 u8 reserved_at_100[0x20]; 8114 8115 u8 end_flow_index[0x20]; 8116 8117 u8 reserved_at_140[0xa0]; 8118 8119 u8 reserved_at_1e0[0x18]; 8120 u8 match_criteria_enable[0x8]; 8121 8122 struct mlx5_ifc_fte_match_param_bits match_criteria; 8123 8124 u8 reserved_at_1200[0xe00]; 8125 }; 8126 8127 struct mlx5_ifc_create_eq_out_bits { 8128 u8 status[0x8]; 8129 u8 reserved_at_8[0x18]; 8130 8131 u8 syndrome[0x20]; 8132 8133 u8 reserved_at_40[0x18]; 8134 u8 eq_number[0x8]; 8135 8136 u8 reserved_at_60[0x20]; 8137 }; 8138 8139 struct mlx5_ifc_create_eq_in_bits { 8140 u8 opcode[0x10]; 8141 u8 uid[0x10]; 8142 8143 u8 reserved_at_20[0x10]; 8144 u8 op_mod[0x10]; 8145 8146 u8 reserved_at_40[0x40]; 8147 8148 struct mlx5_ifc_eqc_bits eq_context_entry; 8149 8150 u8 reserved_at_280[0x40]; 8151 8152 u8 event_bitmask[4][0x40]; 8153 8154 u8 reserved_at_3c0[0x4c0]; 8155 8156 u8 pas[][0x40]; 8157 }; 8158 8159 struct mlx5_ifc_create_dct_out_bits { 8160 u8 status[0x8]; 8161 u8 reserved_at_8[0x18]; 8162 8163 u8 syndrome[0x20]; 8164 8165 u8 reserved_at_40[0x8]; 8166 u8 dctn[0x18]; 8167 8168 u8 ece[0x20]; 8169 }; 8170 8171 struct mlx5_ifc_create_dct_in_bits { 8172 u8 opcode[0x10]; 8173 u8 uid[0x10]; 8174 8175 u8 reserved_at_20[0x10]; 8176 u8 op_mod[0x10]; 8177 8178 u8 reserved_at_40[0x40]; 8179 8180 struct mlx5_ifc_dctc_bits dct_context_entry; 8181 8182 u8 reserved_at_280[0x180]; 8183 }; 8184 8185 struct mlx5_ifc_create_cq_out_bits { 8186 u8 status[0x8]; 8187 u8 reserved_at_8[0x18]; 8188 8189 u8 syndrome[0x20]; 8190 8191 u8 reserved_at_40[0x8]; 8192 u8 cqn[0x18]; 8193 8194 u8 reserved_at_60[0x20]; 8195 }; 8196 8197 struct mlx5_ifc_create_cq_in_bits { 8198 u8 opcode[0x10]; 8199 u8 uid[0x10]; 8200 8201 u8 reserved_at_20[0x10]; 8202 u8 op_mod[0x10]; 8203 8204 u8 reserved_at_40[0x40]; 8205 8206 struct mlx5_ifc_cqc_bits cq_context; 8207 8208 u8 reserved_at_280[0x60]; 8209 8210 u8 cq_umem_valid[0x1]; 8211 u8 reserved_at_2e1[0x59f]; 8212 8213 u8 pas[][0x40]; 8214 }; 8215 8216 struct mlx5_ifc_config_int_moderation_out_bits { 8217 u8 status[0x8]; 8218 u8 reserved_at_8[0x18]; 8219 8220 u8 syndrome[0x20]; 8221 8222 u8 reserved_at_40[0x4]; 8223 u8 min_delay[0xc]; 8224 u8 int_vector[0x10]; 8225 8226 u8 reserved_at_60[0x20]; 8227 }; 8228 8229 enum { 8230 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8231 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8232 }; 8233 8234 struct mlx5_ifc_config_int_moderation_in_bits { 8235 u8 opcode[0x10]; 8236 u8 reserved_at_10[0x10]; 8237 8238 u8 reserved_at_20[0x10]; 8239 u8 op_mod[0x10]; 8240 8241 u8 reserved_at_40[0x4]; 8242 u8 min_delay[0xc]; 8243 u8 int_vector[0x10]; 8244 8245 u8 reserved_at_60[0x20]; 8246 }; 8247 8248 struct mlx5_ifc_attach_to_mcg_out_bits { 8249 u8 status[0x8]; 8250 u8 reserved_at_8[0x18]; 8251 8252 u8 syndrome[0x20]; 8253 8254 u8 reserved_at_40[0x40]; 8255 }; 8256 8257 struct mlx5_ifc_attach_to_mcg_in_bits { 8258 u8 opcode[0x10]; 8259 u8 uid[0x10]; 8260 8261 u8 reserved_at_20[0x10]; 8262 u8 op_mod[0x10]; 8263 8264 u8 reserved_at_40[0x8]; 8265 u8 qpn[0x18]; 8266 8267 u8 reserved_at_60[0x20]; 8268 8269 u8 multicast_gid[16][0x8]; 8270 }; 8271 8272 struct mlx5_ifc_arm_xrq_out_bits { 8273 u8 status[0x8]; 8274 u8 reserved_at_8[0x18]; 8275 8276 u8 syndrome[0x20]; 8277 8278 u8 reserved_at_40[0x40]; 8279 }; 8280 8281 struct mlx5_ifc_arm_xrq_in_bits { 8282 u8 opcode[0x10]; 8283 u8 reserved_at_10[0x10]; 8284 8285 u8 reserved_at_20[0x10]; 8286 u8 op_mod[0x10]; 8287 8288 u8 reserved_at_40[0x8]; 8289 u8 xrqn[0x18]; 8290 8291 u8 reserved_at_60[0x10]; 8292 u8 lwm[0x10]; 8293 }; 8294 8295 struct mlx5_ifc_arm_xrc_srq_out_bits { 8296 u8 status[0x8]; 8297 u8 reserved_at_8[0x18]; 8298 8299 u8 syndrome[0x20]; 8300 8301 u8 reserved_at_40[0x40]; 8302 }; 8303 8304 enum { 8305 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8306 }; 8307 8308 struct mlx5_ifc_arm_xrc_srq_in_bits { 8309 u8 opcode[0x10]; 8310 u8 uid[0x10]; 8311 8312 u8 reserved_at_20[0x10]; 8313 u8 op_mod[0x10]; 8314 8315 u8 reserved_at_40[0x8]; 8316 u8 xrc_srqn[0x18]; 8317 8318 u8 reserved_at_60[0x10]; 8319 u8 lwm[0x10]; 8320 }; 8321 8322 struct mlx5_ifc_arm_rq_out_bits { 8323 u8 status[0x8]; 8324 u8 reserved_at_8[0x18]; 8325 8326 u8 syndrome[0x20]; 8327 8328 u8 reserved_at_40[0x40]; 8329 }; 8330 8331 enum { 8332 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8333 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8334 }; 8335 8336 struct mlx5_ifc_arm_rq_in_bits { 8337 u8 opcode[0x10]; 8338 u8 uid[0x10]; 8339 8340 u8 reserved_at_20[0x10]; 8341 u8 op_mod[0x10]; 8342 8343 u8 reserved_at_40[0x8]; 8344 u8 srq_number[0x18]; 8345 8346 u8 reserved_at_60[0x10]; 8347 u8 lwm[0x10]; 8348 }; 8349 8350 struct mlx5_ifc_arm_dct_out_bits { 8351 u8 status[0x8]; 8352 u8 reserved_at_8[0x18]; 8353 8354 u8 syndrome[0x20]; 8355 8356 u8 reserved_at_40[0x40]; 8357 }; 8358 8359 struct mlx5_ifc_arm_dct_in_bits { 8360 u8 opcode[0x10]; 8361 u8 reserved_at_10[0x10]; 8362 8363 u8 reserved_at_20[0x10]; 8364 u8 op_mod[0x10]; 8365 8366 u8 reserved_at_40[0x8]; 8367 u8 dct_number[0x18]; 8368 8369 u8 reserved_at_60[0x20]; 8370 }; 8371 8372 struct mlx5_ifc_alloc_xrcd_out_bits { 8373 u8 status[0x8]; 8374 u8 reserved_at_8[0x18]; 8375 8376 u8 syndrome[0x20]; 8377 8378 u8 reserved_at_40[0x8]; 8379 u8 xrcd[0x18]; 8380 8381 u8 reserved_at_60[0x20]; 8382 }; 8383 8384 struct mlx5_ifc_alloc_xrcd_in_bits { 8385 u8 opcode[0x10]; 8386 u8 uid[0x10]; 8387 8388 u8 reserved_at_20[0x10]; 8389 u8 op_mod[0x10]; 8390 8391 u8 reserved_at_40[0x40]; 8392 }; 8393 8394 struct mlx5_ifc_alloc_uar_out_bits { 8395 u8 status[0x8]; 8396 u8 reserved_at_8[0x18]; 8397 8398 u8 syndrome[0x20]; 8399 8400 u8 reserved_at_40[0x8]; 8401 u8 uar[0x18]; 8402 8403 u8 reserved_at_60[0x20]; 8404 }; 8405 8406 struct mlx5_ifc_alloc_uar_in_bits { 8407 u8 opcode[0x10]; 8408 u8 reserved_at_10[0x10]; 8409 8410 u8 reserved_at_20[0x10]; 8411 u8 op_mod[0x10]; 8412 8413 u8 reserved_at_40[0x40]; 8414 }; 8415 8416 struct mlx5_ifc_alloc_transport_domain_out_bits { 8417 u8 status[0x8]; 8418 u8 reserved_at_8[0x18]; 8419 8420 u8 syndrome[0x20]; 8421 8422 u8 reserved_at_40[0x8]; 8423 u8 transport_domain[0x18]; 8424 8425 u8 reserved_at_60[0x20]; 8426 }; 8427 8428 struct mlx5_ifc_alloc_transport_domain_in_bits { 8429 u8 opcode[0x10]; 8430 u8 uid[0x10]; 8431 8432 u8 reserved_at_20[0x10]; 8433 u8 op_mod[0x10]; 8434 8435 u8 reserved_at_40[0x40]; 8436 }; 8437 8438 struct mlx5_ifc_alloc_q_counter_out_bits { 8439 u8 status[0x8]; 8440 u8 reserved_at_8[0x18]; 8441 8442 u8 syndrome[0x20]; 8443 8444 u8 reserved_at_40[0x18]; 8445 u8 counter_set_id[0x8]; 8446 8447 u8 reserved_at_60[0x20]; 8448 }; 8449 8450 struct mlx5_ifc_alloc_q_counter_in_bits { 8451 u8 opcode[0x10]; 8452 u8 uid[0x10]; 8453 8454 u8 reserved_at_20[0x10]; 8455 u8 op_mod[0x10]; 8456 8457 u8 reserved_at_40[0x40]; 8458 }; 8459 8460 struct mlx5_ifc_alloc_pd_out_bits { 8461 u8 status[0x8]; 8462 u8 reserved_at_8[0x18]; 8463 8464 u8 syndrome[0x20]; 8465 8466 u8 reserved_at_40[0x8]; 8467 u8 pd[0x18]; 8468 8469 u8 reserved_at_60[0x20]; 8470 }; 8471 8472 struct mlx5_ifc_alloc_pd_in_bits { 8473 u8 opcode[0x10]; 8474 u8 uid[0x10]; 8475 8476 u8 reserved_at_20[0x10]; 8477 u8 op_mod[0x10]; 8478 8479 u8 reserved_at_40[0x40]; 8480 }; 8481 8482 struct mlx5_ifc_alloc_flow_counter_out_bits { 8483 u8 status[0x8]; 8484 u8 reserved_at_8[0x18]; 8485 8486 u8 syndrome[0x20]; 8487 8488 u8 flow_counter_id[0x20]; 8489 8490 u8 reserved_at_60[0x20]; 8491 }; 8492 8493 struct mlx5_ifc_alloc_flow_counter_in_bits { 8494 u8 opcode[0x10]; 8495 u8 reserved_at_10[0x10]; 8496 8497 u8 reserved_at_20[0x10]; 8498 u8 op_mod[0x10]; 8499 8500 u8 reserved_at_40[0x38]; 8501 u8 flow_counter_bulk[0x8]; 8502 }; 8503 8504 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8505 u8 status[0x8]; 8506 u8 reserved_at_8[0x18]; 8507 8508 u8 syndrome[0x20]; 8509 8510 u8 reserved_at_40[0x40]; 8511 }; 8512 8513 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8514 u8 opcode[0x10]; 8515 u8 reserved_at_10[0x10]; 8516 8517 u8 reserved_at_20[0x10]; 8518 u8 op_mod[0x10]; 8519 8520 u8 reserved_at_40[0x20]; 8521 8522 u8 reserved_at_60[0x10]; 8523 u8 vxlan_udp_port[0x10]; 8524 }; 8525 8526 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8527 u8 status[0x8]; 8528 u8 reserved_at_8[0x18]; 8529 8530 u8 syndrome[0x20]; 8531 8532 u8 reserved_at_40[0x40]; 8533 }; 8534 8535 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8536 u8 rate_limit[0x20]; 8537 8538 u8 burst_upper_bound[0x20]; 8539 8540 u8 reserved_at_40[0x10]; 8541 u8 typical_packet_size[0x10]; 8542 8543 u8 reserved_at_60[0x120]; 8544 }; 8545 8546 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8547 u8 opcode[0x10]; 8548 u8 uid[0x10]; 8549 8550 u8 reserved_at_20[0x10]; 8551 u8 op_mod[0x10]; 8552 8553 u8 reserved_at_40[0x10]; 8554 u8 rate_limit_index[0x10]; 8555 8556 u8 reserved_at_60[0x20]; 8557 8558 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8559 }; 8560 8561 struct mlx5_ifc_access_register_out_bits { 8562 u8 status[0x8]; 8563 u8 reserved_at_8[0x18]; 8564 8565 u8 syndrome[0x20]; 8566 8567 u8 reserved_at_40[0x40]; 8568 8569 u8 register_data[][0x20]; 8570 }; 8571 8572 enum { 8573 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8574 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8575 }; 8576 8577 struct mlx5_ifc_access_register_in_bits { 8578 u8 opcode[0x10]; 8579 u8 reserved_at_10[0x10]; 8580 8581 u8 reserved_at_20[0x10]; 8582 u8 op_mod[0x10]; 8583 8584 u8 reserved_at_40[0x10]; 8585 u8 register_id[0x10]; 8586 8587 u8 argument[0x20]; 8588 8589 u8 register_data[][0x20]; 8590 }; 8591 8592 struct mlx5_ifc_sltp_reg_bits { 8593 u8 status[0x4]; 8594 u8 version[0x4]; 8595 u8 local_port[0x8]; 8596 u8 pnat[0x2]; 8597 u8 reserved_at_12[0x2]; 8598 u8 lane[0x4]; 8599 u8 reserved_at_18[0x8]; 8600 8601 u8 reserved_at_20[0x20]; 8602 8603 u8 reserved_at_40[0x7]; 8604 u8 polarity[0x1]; 8605 u8 ob_tap0[0x8]; 8606 u8 ob_tap1[0x8]; 8607 u8 ob_tap2[0x8]; 8608 8609 u8 reserved_at_60[0xc]; 8610 u8 ob_preemp_mode[0x4]; 8611 u8 ob_reg[0x8]; 8612 u8 ob_bias[0x8]; 8613 8614 u8 reserved_at_80[0x20]; 8615 }; 8616 8617 struct mlx5_ifc_slrg_reg_bits { 8618 u8 status[0x4]; 8619 u8 version[0x4]; 8620 u8 local_port[0x8]; 8621 u8 pnat[0x2]; 8622 u8 reserved_at_12[0x2]; 8623 u8 lane[0x4]; 8624 u8 reserved_at_18[0x8]; 8625 8626 u8 time_to_link_up[0x10]; 8627 u8 reserved_at_30[0xc]; 8628 u8 grade_lane_speed[0x4]; 8629 8630 u8 grade_version[0x8]; 8631 u8 grade[0x18]; 8632 8633 u8 reserved_at_60[0x4]; 8634 u8 height_grade_type[0x4]; 8635 u8 height_grade[0x18]; 8636 8637 u8 height_dz[0x10]; 8638 u8 height_dv[0x10]; 8639 8640 u8 reserved_at_a0[0x10]; 8641 u8 height_sigma[0x10]; 8642 8643 u8 reserved_at_c0[0x20]; 8644 8645 u8 reserved_at_e0[0x4]; 8646 u8 phase_grade_type[0x4]; 8647 u8 phase_grade[0x18]; 8648 8649 u8 reserved_at_100[0x8]; 8650 u8 phase_eo_pos[0x8]; 8651 u8 reserved_at_110[0x8]; 8652 u8 phase_eo_neg[0x8]; 8653 8654 u8 ffe_set_tested[0x10]; 8655 u8 test_errors_per_lane[0x10]; 8656 }; 8657 8658 struct mlx5_ifc_pvlc_reg_bits { 8659 u8 reserved_at_0[0x8]; 8660 u8 local_port[0x8]; 8661 u8 reserved_at_10[0x10]; 8662 8663 u8 reserved_at_20[0x1c]; 8664 u8 vl_hw_cap[0x4]; 8665 8666 u8 reserved_at_40[0x1c]; 8667 u8 vl_admin[0x4]; 8668 8669 u8 reserved_at_60[0x1c]; 8670 u8 vl_operational[0x4]; 8671 }; 8672 8673 struct mlx5_ifc_pude_reg_bits { 8674 u8 swid[0x8]; 8675 u8 local_port[0x8]; 8676 u8 reserved_at_10[0x4]; 8677 u8 admin_status[0x4]; 8678 u8 reserved_at_18[0x4]; 8679 u8 oper_status[0x4]; 8680 8681 u8 reserved_at_20[0x60]; 8682 }; 8683 8684 struct mlx5_ifc_ptys_reg_bits { 8685 u8 reserved_at_0[0x1]; 8686 u8 an_disable_admin[0x1]; 8687 u8 an_disable_cap[0x1]; 8688 u8 reserved_at_3[0x5]; 8689 u8 local_port[0x8]; 8690 u8 reserved_at_10[0xd]; 8691 u8 proto_mask[0x3]; 8692 8693 u8 an_status[0x4]; 8694 u8 reserved_at_24[0xc]; 8695 u8 data_rate_oper[0x10]; 8696 8697 u8 ext_eth_proto_capability[0x20]; 8698 8699 u8 eth_proto_capability[0x20]; 8700 8701 u8 ib_link_width_capability[0x10]; 8702 u8 ib_proto_capability[0x10]; 8703 8704 u8 ext_eth_proto_admin[0x20]; 8705 8706 u8 eth_proto_admin[0x20]; 8707 8708 u8 ib_link_width_admin[0x10]; 8709 u8 ib_proto_admin[0x10]; 8710 8711 u8 ext_eth_proto_oper[0x20]; 8712 8713 u8 eth_proto_oper[0x20]; 8714 8715 u8 ib_link_width_oper[0x10]; 8716 u8 ib_proto_oper[0x10]; 8717 8718 u8 reserved_at_160[0x1c]; 8719 u8 connector_type[0x4]; 8720 8721 u8 eth_proto_lp_advertise[0x20]; 8722 8723 u8 reserved_at_1a0[0x60]; 8724 }; 8725 8726 struct mlx5_ifc_mlcr_reg_bits { 8727 u8 reserved_at_0[0x8]; 8728 u8 local_port[0x8]; 8729 u8 reserved_at_10[0x20]; 8730 8731 u8 beacon_duration[0x10]; 8732 u8 reserved_at_40[0x10]; 8733 8734 u8 beacon_remain[0x10]; 8735 }; 8736 8737 struct mlx5_ifc_ptas_reg_bits { 8738 u8 reserved_at_0[0x20]; 8739 8740 u8 algorithm_options[0x10]; 8741 u8 reserved_at_30[0x4]; 8742 u8 repetitions_mode[0x4]; 8743 u8 num_of_repetitions[0x8]; 8744 8745 u8 grade_version[0x8]; 8746 u8 height_grade_type[0x4]; 8747 u8 phase_grade_type[0x4]; 8748 u8 height_grade_weight[0x8]; 8749 u8 phase_grade_weight[0x8]; 8750 8751 u8 gisim_measure_bits[0x10]; 8752 u8 adaptive_tap_measure_bits[0x10]; 8753 8754 u8 ber_bath_high_error_threshold[0x10]; 8755 u8 ber_bath_mid_error_threshold[0x10]; 8756 8757 u8 ber_bath_low_error_threshold[0x10]; 8758 u8 one_ratio_high_threshold[0x10]; 8759 8760 u8 one_ratio_high_mid_threshold[0x10]; 8761 u8 one_ratio_low_mid_threshold[0x10]; 8762 8763 u8 one_ratio_low_threshold[0x10]; 8764 u8 ndeo_error_threshold[0x10]; 8765 8766 u8 mixer_offset_step_size[0x10]; 8767 u8 reserved_at_110[0x8]; 8768 u8 mix90_phase_for_voltage_bath[0x8]; 8769 8770 u8 mixer_offset_start[0x10]; 8771 u8 mixer_offset_end[0x10]; 8772 8773 u8 reserved_at_140[0x15]; 8774 u8 ber_test_time[0xb]; 8775 }; 8776 8777 struct mlx5_ifc_pspa_reg_bits { 8778 u8 swid[0x8]; 8779 u8 local_port[0x8]; 8780 u8 sub_port[0x8]; 8781 u8 reserved_at_18[0x8]; 8782 8783 u8 reserved_at_20[0x20]; 8784 }; 8785 8786 struct mlx5_ifc_pqdr_reg_bits { 8787 u8 reserved_at_0[0x8]; 8788 u8 local_port[0x8]; 8789 u8 reserved_at_10[0x5]; 8790 u8 prio[0x3]; 8791 u8 reserved_at_18[0x6]; 8792 u8 mode[0x2]; 8793 8794 u8 reserved_at_20[0x20]; 8795 8796 u8 reserved_at_40[0x10]; 8797 u8 min_threshold[0x10]; 8798 8799 u8 reserved_at_60[0x10]; 8800 u8 max_threshold[0x10]; 8801 8802 u8 reserved_at_80[0x10]; 8803 u8 mark_probability_denominator[0x10]; 8804 8805 u8 reserved_at_a0[0x60]; 8806 }; 8807 8808 struct mlx5_ifc_ppsc_reg_bits { 8809 u8 reserved_at_0[0x8]; 8810 u8 local_port[0x8]; 8811 u8 reserved_at_10[0x10]; 8812 8813 u8 reserved_at_20[0x60]; 8814 8815 u8 reserved_at_80[0x1c]; 8816 u8 wrps_admin[0x4]; 8817 8818 u8 reserved_at_a0[0x1c]; 8819 u8 wrps_status[0x4]; 8820 8821 u8 reserved_at_c0[0x8]; 8822 u8 up_threshold[0x8]; 8823 u8 reserved_at_d0[0x8]; 8824 u8 down_threshold[0x8]; 8825 8826 u8 reserved_at_e0[0x20]; 8827 8828 u8 reserved_at_100[0x1c]; 8829 u8 srps_admin[0x4]; 8830 8831 u8 reserved_at_120[0x1c]; 8832 u8 srps_status[0x4]; 8833 8834 u8 reserved_at_140[0x40]; 8835 }; 8836 8837 struct mlx5_ifc_pplr_reg_bits { 8838 u8 reserved_at_0[0x8]; 8839 u8 local_port[0x8]; 8840 u8 reserved_at_10[0x10]; 8841 8842 u8 reserved_at_20[0x8]; 8843 u8 lb_cap[0x8]; 8844 u8 reserved_at_30[0x8]; 8845 u8 lb_en[0x8]; 8846 }; 8847 8848 struct mlx5_ifc_pplm_reg_bits { 8849 u8 reserved_at_0[0x8]; 8850 u8 local_port[0x8]; 8851 u8 reserved_at_10[0x10]; 8852 8853 u8 reserved_at_20[0x20]; 8854 8855 u8 port_profile_mode[0x8]; 8856 u8 static_port_profile[0x8]; 8857 u8 active_port_profile[0x8]; 8858 u8 reserved_at_58[0x8]; 8859 8860 u8 retransmission_active[0x8]; 8861 u8 fec_mode_active[0x18]; 8862 8863 u8 rs_fec_correction_bypass_cap[0x4]; 8864 u8 reserved_at_84[0x8]; 8865 u8 fec_override_cap_56g[0x4]; 8866 u8 fec_override_cap_100g[0x4]; 8867 u8 fec_override_cap_50g[0x4]; 8868 u8 fec_override_cap_25g[0x4]; 8869 u8 fec_override_cap_10g_40g[0x4]; 8870 8871 u8 rs_fec_correction_bypass_admin[0x4]; 8872 u8 reserved_at_a4[0x8]; 8873 u8 fec_override_admin_56g[0x4]; 8874 u8 fec_override_admin_100g[0x4]; 8875 u8 fec_override_admin_50g[0x4]; 8876 u8 fec_override_admin_25g[0x4]; 8877 u8 fec_override_admin_10g_40g[0x4]; 8878 8879 u8 fec_override_cap_400g_8x[0x10]; 8880 u8 fec_override_cap_200g_4x[0x10]; 8881 8882 u8 fec_override_cap_100g_2x[0x10]; 8883 u8 fec_override_cap_50g_1x[0x10]; 8884 8885 u8 fec_override_admin_400g_8x[0x10]; 8886 u8 fec_override_admin_200g_4x[0x10]; 8887 8888 u8 fec_override_admin_100g_2x[0x10]; 8889 u8 fec_override_admin_50g_1x[0x10]; 8890 8891 u8 reserved_at_140[0x140]; 8892 }; 8893 8894 struct mlx5_ifc_ppcnt_reg_bits { 8895 u8 swid[0x8]; 8896 u8 local_port[0x8]; 8897 u8 pnat[0x2]; 8898 u8 reserved_at_12[0x8]; 8899 u8 grp[0x6]; 8900 8901 u8 clr[0x1]; 8902 u8 reserved_at_21[0x1c]; 8903 u8 prio_tc[0x3]; 8904 8905 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8906 }; 8907 8908 struct mlx5_ifc_mpein_reg_bits { 8909 u8 reserved_at_0[0x2]; 8910 u8 depth[0x6]; 8911 u8 pcie_index[0x8]; 8912 u8 node[0x8]; 8913 u8 reserved_at_18[0x8]; 8914 8915 u8 capability_mask[0x20]; 8916 8917 u8 reserved_at_40[0x8]; 8918 u8 link_width_enabled[0x8]; 8919 u8 link_speed_enabled[0x10]; 8920 8921 u8 lane0_physical_position[0x8]; 8922 u8 link_width_active[0x8]; 8923 u8 link_speed_active[0x10]; 8924 8925 u8 num_of_pfs[0x10]; 8926 u8 num_of_vfs[0x10]; 8927 8928 u8 bdf0[0x10]; 8929 u8 reserved_at_b0[0x10]; 8930 8931 u8 max_read_request_size[0x4]; 8932 u8 max_payload_size[0x4]; 8933 u8 reserved_at_c8[0x5]; 8934 u8 pwr_status[0x3]; 8935 u8 port_type[0x4]; 8936 u8 reserved_at_d4[0xb]; 8937 u8 lane_reversal[0x1]; 8938 8939 u8 reserved_at_e0[0x14]; 8940 u8 pci_power[0xc]; 8941 8942 u8 reserved_at_100[0x20]; 8943 8944 u8 device_status[0x10]; 8945 u8 port_state[0x8]; 8946 u8 reserved_at_138[0x8]; 8947 8948 u8 reserved_at_140[0x10]; 8949 u8 receiver_detect_result[0x10]; 8950 8951 u8 reserved_at_160[0x20]; 8952 }; 8953 8954 struct mlx5_ifc_mpcnt_reg_bits { 8955 u8 reserved_at_0[0x8]; 8956 u8 pcie_index[0x8]; 8957 u8 reserved_at_10[0xa]; 8958 u8 grp[0x6]; 8959 8960 u8 clr[0x1]; 8961 u8 reserved_at_21[0x1f]; 8962 8963 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8964 }; 8965 8966 struct mlx5_ifc_ppad_reg_bits { 8967 u8 reserved_at_0[0x3]; 8968 u8 single_mac[0x1]; 8969 u8 reserved_at_4[0x4]; 8970 u8 local_port[0x8]; 8971 u8 mac_47_32[0x10]; 8972 8973 u8 mac_31_0[0x20]; 8974 8975 u8 reserved_at_40[0x40]; 8976 }; 8977 8978 struct mlx5_ifc_pmtu_reg_bits { 8979 u8 reserved_at_0[0x8]; 8980 u8 local_port[0x8]; 8981 u8 reserved_at_10[0x10]; 8982 8983 u8 max_mtu[0x10]; 8984 u8 reserved_at_30[0x10]; 8985 8986 u8 admin_mtu[0x10]; 8987 u8 reserved_at_50[0x10]; 8988 8989 u8 oper_mtu[0x10]; 8990 u8 reserved_at_70[0x10]; 8991 }; 8992 8993 struct mlx5_ifc_pmpr_reg_bits { 8994 u8 reserved_at_0[0x8]; 8995 u8 module[0x8]; 8996 u8 reserved_at_10[0x10]; 8997 8998 u8 reserved_at_20[0x18]; 8999 u8 attenuation_5g[0x8]; 9000 9001 u8 reserved_at_40[0x18]; 9002 u8 attenuation_7g[0x8]; 9003 9004 u8 reserved_at_60[0x18]; 9005 u8 attenuation_12g[0x8]; 9006 }; 9007 9008 struct mlx5_ifc_pmpe_reg_bits { 9009 u8 reserved_at_0[0x8]; 9010 u8 module[0x8]; 9011 u8 reserved_at_10[0xc]; 9012 u8 module_status[0x4]; 9013 9014 u8 reserved_at_20[0x60]; 9015 }; 9016 9017 struct mlx5_ifc_pmpc_reg_bits { 9018 u8 module_state_updated[32][0x8]; 9019 }; 9020 9021 struct mlx5_ifc_pmlpn_reg_bits { 9022 u8 reserved_at_0[0x4]; 9023 u8 mlpn_status[0x4]; 9024 u8 local_port[0x8]; 9025 u8 reserved_at_10[0x10]; 9026 9027 u8 e[0x1]; 9028 u8 reserved_at_21[0x1f]; 9029 }; 9030 9031 struct mlx5_ifc_pmlp_reg_bits { 9032 u8 rxtx[0x1]; 9033 u8 reserved_at_1[0x7]; 9034 u8 local_port[0x8]; 9035 u8 reserved_at_10[0x8]; 9036 u8 width[0x8]; 9037 9038 u8 lane0_module_mapping[0x20]; 9039 9040 u8 lane1_module_mapping[0x20]; 9041 9042 u8 lane2_module_mapping[0x20]; 9043 9044 u8 lane3_module_mapping[0x20]; 9045 9046 u8 reserved_at_a0[0x160]; 9047 }; 9048 9049 struct mlx5_ifc_pmaos_reg_bits { 9050 u8 reserved_at_0[0x8]; 9051 u8 module[0x8]; 9052 u8 reserved_at_10[0x4]; 9053 u8 admin_status[0x4]; 9054 u8 reserved_at_18[0x4]; 9055 u8 oper_status[0x4]; 9056 9057 u8 ase[0x1]; 9058 u8 ee[0x1]; 9059 u8 reserved_at_22[0x1c]; 9060 u8 e[0x2]; 9061 9062 u8 reserved_at_40[0x40]; 9063 }; 9064 9065 struct mlx5_ifc_plpc_reg_bits { 9066 u8 reserved_at_0[0x4]; 9067 u8 profile_id[0xc]; 9068 u8 reserved_at_10[0x4]; 9069 u8 proto_mask[0x4]; 9070 u8 reserved_at_18[0x8]; 9071 9072 u8 reserved_at_20[0x10]; 9073 u8 lane_speed[0x10]; 9074 9075 u8 reserved_at_40[0x17]; 9076 u8 lpbf[0x1]; 9077 u8 fec_mode_policy[0x8]; 9078 9079 u8 retransmission_capability[0x8]; 9080 u8 fec_mode_capability[0x18]; 9081 9082 u8 retransmission_support_admin[0x8]; 9083 u8 fec_mode_support_admin[0x18]; 9084 9085 u8 retransmission_request_admin[0x8]; 9086 u8 fec_mode_request_admin[0x18]; 9087 9088 u8 reserved_at_c0[0x80]; 9089 }; 9090 9091 struct mlx5_ifc_plib_reg_bits { 9092 u8 reserved_at_0[0x8]; 9093 u8 local_port[0x8]; 9094 u8 reserved_at_10[0x8]; 9095 u8 ib_port[0x8]; 9096 9097 u8 reserved_at_20[0x60]; 9098 }; 9099 9100 struct mlx5_ifc_plbf_reg_bits { 9101 u8 reserved_at_0[0x8]; 9102 u8 local_port[0x8]; 9103 u8 reserved_at_10[0xd]; 9104 u8 lbf_mode[0x3]; 9105 9106 u8 reserved_at_20[0x20]; 9107 }; 9108 9109 struct mlx5_ifc_pipg_reg_bits { 9110 u8 reserved_at_0[0x8]; 9111 u8 local_port[0x8]; 9112 u8 reserved_at_10[0x10]; 9113 9114 u8 dic[0x1]; 9115 u8 reserved_at_21[0x19]; 9116 u8 ipg[0x4]; 9117 u8 reserved_at_3e[0x2]; 9118 }; 9119 9120 struct mlx5_ifc_pifr_reg_bits { 9121 u8 reserved_at_0[0x8]; 9122 u8 local_port[0x8]; 9123 u8 reserved_at_10[0x10]; 9124 9125 u8 reserved_at_20[0xe0]; 9126 9127 u8 port_filter[8][0x20]; 9128 9129 u8 port_filter_update_en[8][0x20]; 9130 }; 9131 9132 struct mlx5_ifc_pfcc_reg_bits { 9133 u8 reserved_at_0[0x8]; 9134 u8 local_port[0x8]; 9135 u8 reserved_at_10[0xb]; 9136 u8 ppan_mask_n[0x1]; 9137 u8 minor_stall_mask[0x1]; 9138 u8 critical_stall_mask[0x1]; 9139 u8 reserved_at_1e[0x2]; 9140 9141 u8 ppan[0x4]; 9142 u8 reserved_at_24[0x4]; 9143 u8 prio_mask_tx[0x8]; 9144 u8 reserved_at_30[0x8]; 9145 u8 prio_mask_rx[0x8]; 9146 9147 u8 pptx[0x1]; 9148 u8 aptx[0x1]; 9149 u8 pptx_mask_n[0x1]; 9150 u8 reserved_at_43[0x5]; 9151 u8 pfctx[0x8]; 9152 u8 reserved_at_50[0x10]; 9153 9154 u8 pprx[0x1]; 9155 u8 aprx[0x1]; 9156 u8 pprx_mask_n[0x1]; 9157 u8 reserved_at_63[0x5]; 9158 u8 pfcrx[0x8]; 9159 u8 reserved_at_70[0x10]; 9160 9161 u8 device_stall_minor_watermark[0x10]; 9162 u8 device_stall_critical_watermark[0x10]; 9163 9164 u8 reserved_at_a0[0x60]; 9165 }; 9166 9167 struct mlx5_ifc_pelc_reg_bits { 9168 u8 op[0x4]; 9169 u8 reserved_at_4[0x4]; 9170 u8 local_port[0x8]; 9171 u8 reserved_at_10[0x10]; 9172 9173 u8 op_admin[0x8]; 9174 u8 op_capability[0x8]; 9175 u8 op_request[0x8]; 9176 u8 op_active[0x8]; 9177 9178 u8 admin[0x40]; 9179 9180 u8 capability[0x40]; 9181 9182 u8 request[0x40]; 9183 9184 u8 active[0x40]; 9185 9186 u8 reserved_at_140[0x80]; 9187 }; 9188 9189 struct mlx5_ifc_peir_reg_bits { 9190 u8 reserved_at_0[0x8]; 9191 u8 local_port[0x8]; 9192 u8 reserved_at_10[0x10]; 9193 9194 u8 reserved_at_20[0xc]; 9195 u8 error_count[0x4]; 9196 u8 reserved_at_30[0x10]; 9197 9198 u8 reserved_at_40[0xc]; 9199 u8 lane[0x4]; 9200 u8 reserved_at_50[0x8]; 9201 u8 error_type[0x8]; 9202 }; 9203 9204 struct mlx5_ifc_mpegc_reg_bits { 9205 u8 reserved_at_0[0x30]; 9206 u8 field_select[0x10]; 9207 9208 u8 tx_overflow_sense[0x1]; 9209 u8 mark_cqe[0x1]; 9210 u8 mark_cnp[0x1]; 9211 u8 reserved_at_43[0x1b]; 9212 u8 tx_lossy_overflow_oper[0x2]; 9213 9214 u8 reserved_at_60[0x100]; 9215 }; 9216 9217 enum { 9218 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9219 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9220 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9221 }; 9222 9223 struct mlx5_ifc_mtutc_reg_bits { 9224 u8 reserved_at_0[0x1c]; 9225 u8 operation[0x4]; 9226 9227 u8 freq_adjustment[0x20]; 9228 9229 u8 reserved_at_40[0x40]; 9230 9231 u8 utc_sec[0x20]; 9232 9233 u8 reserved_at_a0[0x2]; 9234 u8 utc_nsec[0x1e]; 9235 9236 u8 time_adjustment[0x20]; 9237 }; 9238 9239 struct mlx5_ifc_pcam_enhanced_features_bits { 9240 u8 reserved_at_0[0x68]; 9241 u8 fec_50G_per_lane_in_pplm[0x1]; 9242 u8 reserved_at_69[0x4]; 9243 u8 rx_icrc_encapsulated_counter[0x1]; 9244 u8 reserved_at_6e[0x4]; 9245 u8 ptys_extended_ethernet[0x1]; 9246 u8 reserved_at_73[0x3]; 9247 u8 pfcc_mask[0x1]; 9248 u8 reserved_at_77[0x3]; 9249 u8 per_lane_error_counters[0x1]; 9250 u8 rx_buffer_fullness_counters[0x1]; 9251 u8 ptys_connector_type[0x1]; 9252 u8 reserved_at_7d[0x1]; 9253 u8 ppcnt_discard_group[0x1]; 9254 u8 ppcnt_statistical_group[0x1]; 9255 }; 9256 9257 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9258 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9259 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9260 9261 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9262 u8 pplm[0x1]; 9263 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9264 9265 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9266 u8 pbmc[0x1]; 9267 u8 pptb[0x1]; 9268 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9269 u8 ppcnt[0x1]; 9270 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9271 }; 9272 9273 struct mlx5_ifc_pcam_reg_bits { 9274 u8 reserved_at_0[0x8]; 9275 u8 feature_group[0x8]; 9276 u8 reserved_at_10[0x8]; 9277 u8 access_reg_group[0x8]; 9278 9279 u8 reserved_at_20[0x20]; 9280 9281 union { 9282 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9283 u8 reserved_at_0[0x80]; 9284 } port_access_reg_cap_mask; 9285 9286 u8 reserved_at_c0[0x80]; 9287 9288 union { 9289 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9290 u8 reserved_at_0[0x80]; 9291 } feature_cap_mask; 9292 9293 u8 reserved_at_1c0[0xc0]; 9294 }; 9295 9296 struct mlx5_ifc_mcam_enhanced_features_bits { 9297 u8 reserved_at_0[0x6b]; 9298 u8 ptpcyc2realtime_modify[0x1]; 9299 u8 reserved_at_6c[0x2]; 9300 u8 pci_status_and_power[0x1]; 9301 u8 reserved_at_6f[0x5]; 9302 u8 mark_tx_action_cnp[0x1]; 9303 u8 mark_tx_action_cqe[0x1]; 9304 u8 dynamic_tx_overflow[0x1]; 9305 u8 reserved_at_77[0x4]; 9306 u8 pcie_outbound_stalled[0x1]; 9307 u8 tx_overflow_buffer_pkt[0x1]; 9308 u8 mtpps_enh_out_per_adj[0x1]; 9309 u8 mtpps_fs[0x1]; 9310 u8 pcie_performance_group[0x1]; 9311 }; 9312 9313 struct mlx5_ifc_mcam_access_reg_bits { 9314 u8 reserved_at_0[0x1c]; 9315 u8 mcda[0x1]; 9316 u8 mcc[0x1]; 9317 u8 mcqi[0x1]; 9318 u8 mcqs[0x1]; 9319 9320 u8 regs_95_to_87[0x9]; 9321 u8 mpegc[0x1]; 9322 u8 mtutc[0x1]; 9323 u8 regs_84_to_68[0x11]; 9324 u8 tracer_registers[0x4]; 9325 9326 u8 regs_63_to_32[0x20]; 9327 u8 regs_31_to_0[0x20]; 9328 }; 9329 9330 struct mlx5_ifc_mcam_access_reg_bits1 { 9331 u8 regs_127_to_96[0x20]; 9332 9333 u8 regs_95_to_64[0x20]; 9334 9335 u8 regs_63_to_32[0x20]; 9336 9337 u8 regs_31_to_0[0x20]; 9338 }; 9339 9340 struct mlx5_ifc_mcam_access_reg_bits2 { 9341 u8 regs_127_to_99[0x1d]; 9342 u8 mirc[0x1]; 9343 u8 regs_97_to_96[0x2]; 9344 9345 u8 regs_95_to_64[0x20]; 9346 9347 u8 regs_63_to_32[0x20]; 9348 9349 u8 regs_31_to_0[0x20]; 9350 }; 9351 9352 struct mlx5_ifc_mcam_reg_bits { 9353 u8 reserved_at_0[0x8]; 9354 u8 feature_group[0x8]; 9355 u8 reserved_at_10[0x8]; 9356 u8 access_reg_group[0x8]; 9357 9358 u8 reserved_at_20[0x20]; 9359 9360 union { 9361 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9362 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9363 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9364 u8 reserved_at_0[0x80]; 9365 } mng_access_reg_cap_mask; 9366 9367 u8 reserved_at_c0[0x80]; 9368 9369 union { 9370 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9371 u8 reserved_at_0[0x80]; 9372 } mng_feature_cap_mask; 9373 9374 u8 reserved_at_1c0[0x80]; 9375 }; 9376 9377 struct mlx5_ifc_qcam_access_reg_cap_mask { 9378 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9379 u8 qpdpm[0x1]; 9380 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9381 u8 qdpm[0x1]; 9382 u8 qpts[0x1]; 9383 u8 qcap[0x1]; 9384 u8 qcam_access_reg_cap_mask_0[0x1]; 9385 }; 9386 9387 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9388 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9389 u8 qpts_trust_both[0x1]; 9390 }; 9391 9392 struct mlx5_ifc_qcam_reg_bits { 9393 u8 reserved_at_0[0x8]; 9394 u8 feature_group[0x8]; 9395 u8 reserved_at_10[0x8]; 9396 u8 access_reg_group[0x8]; 9397 u8 reserved_at_20[0x20]; 9398 9399 union { 9400 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9401 u8 reserved_at_0[0x80]; 9402 } qos_access_reg_cap_mask; 9403 9404 u8 reserved_at_c0[0x80]; 9405 9406 union { 9407 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9408 u8 reserved_at_0[0x80]; 9409 } qos_feature_cap_mask; 9410 9411 u8 reserved_at_1c0[0x80]; 9412 }; 9413 9414 struct mlx5_ifc_core_dump_reg_bits { 9415 u8 reserved_at_0[0x18]; 9416 u8 core_dump_type[0x8]; 9417 9418 u8 reserved_at_20[0x30]; 9419 u8 vhca_id[0x10]; 9420 9421 u8 reserved_at_60[0x8]; 9422 u8 qpn[0x18]; 9423 u8 reserved_at_80[0x180]; 9424 }; 9425 9426 struct mlx5_ifc_pcap_reg_bits { 9427 u8 reserved_at_0[0x8]; 9428 u8 local_port[0x8]; 9429 u8 reserved_at_10[0x10]; 9430 9431 u8 port_capability_mask[4][0x20]; 9432 }; 9433 9434 struct mlx5_ifc_paos_reg_bits { 9435 u8 swid[0x8]; 9436 u8 local_port[0x8]; 9437 u8 reserved_at_10[0x4]; 9438 u8 admin_status[0x4]; 9439 u8 reserved_at_18[0x4]; 9440 u8 oper_status[0x4]; 9441 9442 u8 ase[0x1]; 9443 u8 ee[0x1]; 9444 u8 reserved_at_22[0x1c]; 9445 u8 e[0x2]; 9446 9447 u8 reserved_at_40[0x40]; 9448 }; 9449 9450 struct mlx5_ifc_pamp_reg_bits { 9451 u8 reserved_at_0[0x8]; 9452 u8 opamp_group[0x8]; 9453 u8 reserved_at_10[0xc]; 9454 u8 opamp_group_type[0x4]; 9455 9456 u8 start_index[0x10]; 9457 u8 reserved_at_30[0x4]; 9458 u8 num_of_indices[0xc]; 9459 9460 u8 index_data[18][0x10]; 9461 }; 9462 9463 struct mlx5_ifc_pcmr_reg_bits { 9464 u8 reserved_at_0[0x8]; 9465 u8 local_port[0x8]; 9466 u8 reserved_at_10[0x10]; 9467 u8 entropy_force_cap[0x1]; 9468 u8 entropy_calc_cap[0x1]; 9469 u8 entropy_gre_calc_cap[0x1]; 9470 u8 reserved_at_23[0x1b]; 9471 u8 fcs_cap[0x1]; 9472 u8 reserved_at_3f[0x1]; 9473 u8 entropy_force[0x1]; 9474 u8 entropy_calc[0x1]; 9475 u8 entropy_gre_calc[0x1]; 9476 u8 reserved_at_43[0x1b]; 9477 u8 fcs_chk[0x1]; 9478 u8 reserved_at_5f[0x1]; 9479 }; 9480 9481 struct mlx5_ifc_lane_2_module_mapping_bits { 9482 u8 reserved_at_0[0x6]; 9483 u8 rx_lane[0x2]; 9484 u8 reserved_at_8[0x6]; 9485 u8 tx_lane[0x2]; 9486 u8 reserved_at_10[0x8]; 9487 u8 module[0x8]; 9488 }; 9489 9490 struct mlx5_ifc_bufferx_reg_bits { 9491 u8 reserved_at_0[0x6]; 9492 u8 lossy[0x1]; 9493 u8 epsb[0x1]; 9494 u8 reserved_at_8[0xc]; 9495 u8 size[0xc]; 9496 9497 u8 xoff_threshold[0x10]; 9498 u8 xon_threshold[0x10]; 9499 }; 9500 9501 struct mlx5_ifc_set_node_in_bits { 9502 u8 node_description[64][0x8]; 9503 }; 9504 9505 struct mlx5_ifc_register_power_settings_bits { 9506 u8 reserved_at_0[0x18]; 9507 u8 power_settings_level[0x8]; 9508 9509 u8 reserved_at_20[0x60]; 9510 }; 9511 9512 struct mlx5_ifc_register_host_endianness_bits { 9513 u8 he[0x1]; 9514 u8 reserved_at_1[0x1f]; 9515 9516 u8 reserved_at_20[0x60]; 9517 }; 9518 9519 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9520 u8 reserved_at_0[0x20]; 9521 9522 u8 mkey[0x20]; 9523 9524 u8 addressh_63_32[0x20]; 9525 9526 u8 addressl_31_0[0x20]; 9527 }; 9528 9529 struct mlx5_ifc_ud_adrs_vector_bits { 9530 u8 dc_key[0x40]; 9531 9532 u8 ext[0x1]; 9533 u8 reserved_at_41[0x7]; 9534 u8 destination_qp_dct[0x18]; 9535 9536 u8 static_rate[0x4]; 9537 u8 sl_eth_prio[0x4]; 9538 u8 fl[0x1]; 9539 u8 mlid[0x7]; 9540 u8 rlid_udp_sport[0x10]; 9541 9542 u8 reserved_at_80[0x20]; 9543 9544 u8 rmac_47_16[0x20]; 9545 9546 u8 rmac_15_0[0x10]; 9547 u8 tclass[0x8]; 9548 u8 hop_limit[0x8]; 9549 9550 u8 reserved_at_e0[0x1]; 9551 u8 grh[0x1]; 9552 u8 reserved_at_e2[0x2]; 9553 u8 src_addr_index[0x8]; 9554 u8 flow_label[0x14]; 9555 9556 u8 rgid_rip[16][0x8]; 9557 }; 9558 9559 struct mlx5_ifc_pages_req_event_bits { 9560 u8 reserved_at_0[0x10]; 9561 u8 function_id[0x10]; 9562 9563 u8 num_pages[0x20]; 9564 9565 u8 reserved_at_40[0xa0]; 9566 }; 9567 9568 struct mlx5_ifc_eqe_bits { 9569 u8 reserved_at_0[0x8]; 9570 u8 event_type[0x8]; 9571 u8 reserved_at_10[0x8]; 9572 u8 event_sub_type[0x8]; 9573 9574 u8 reserved_at_20[0xe0]; 9575 9576 union mlx5_ifc_event_auto_bits event_data; 9577 9578 u8 reserved_at_1e0[0x10]; 9579 u8 signature[0x8]; 9580 u8 reserved_at_1f8[0x7]; 9581 u8 owner[0x1]; 9582 }; 9583 9584 enum { 9585 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9586 }; 9587 9588 struct mlx5_ifc_cmd_queue_entry_bits { 9589 u8 type[0x8]; 9590 u8 reserved_at_8[0x18]; 9591 9592 u8 input_length[0x20]; 9593 9594 u8 input_mailbox_pointer_63_32[0x20]; 9595 9596 u8 input_mailbox_pointer_31_9[0x17]; 9597 u8 reserved_at_77[0x9]; 9598 9599 u8 command_input_inline_data[16][0x8]; 9600 9601 u8 command_output_inline_data[16][0x8]; 9602 9603 u8 output_mailbox_pointer_63_32[0x20]; 9604 9605 u8 output_mailbox_pointer_31_9[0x17]; 9606 u8 reserved_at_1b7[0x9]; 9607 9608 u8 output_length[0x20]; 9609 9610 u8 token[0x8]; 9611 u8 signature[0x8]; 9612 u8 reserved_at_1f0[0x8]; 9613 u8 status[0x7]; 9614 u8 ownership[0x1]; 9615 }; 9616 9617 struct mlx5_ifc_cmd_out_bits { 9618 u8 status[0x8]; 9619 u8 reserved_at_8[0x18]; 9620 9621 u8 syndrome[0x20]; 9622 9623 u8 command_output[0x20]; 9624 }; 9625 9626 struct mlx5_ifc_cmd_in_bits { 9627 u8 opcode[0x10]; 9628 u8 reserved_at_10[0x10]; 9629 9630 u8 reserved_at_20[0x10]; 9631 u8 op_mod[0x10]; 9632 9633 u8 command[][0x20]; 9634 }; 9635 9636 struct mlx5_ifc_cmd_if_box_bits { 9637 u8 mailbox_data[512][0x8]; 9638 9639 u8 reserved_at_1000[0x180]; 9640 9641 u8 next_pointer_63_32[0x20]; 9642 9643 u8 next_pointer_31_10[0x16]; 9644 u8 reserved_at_11b6[0xa]; 9645 9646 u8 block_number[0x20]; 9647 9648 u8 reserved_at_11e0[0x8]; 9649 u8 token[0x8]; 9650 u8 ctrl_signature[0x8]; 9651 u8 signature[0x8]; 9652 }; 9653 9654 struct mlx5_ifc_mtt_bits { 9655 u8 ptag_63_32[0x20]; 9656 9657 u8 ptag_31_8[0x18]; 9658 u8 reserved_at_38[0x6]; 9659 u8 wr_en[0x1]; 9660 u8 rd_en[0x1]; 9661 }; 9662 9663 struct mlx5_ifc_query_wol_rol_out_bits { 9664 u8 status[0x8]; 9665 u8 reserved_at_8[0x18]; 9666 9667 u8 syndrome[0x20]; 9668 9669 u8 reserved_at_40[0x10]; 9670 u8 rol_mode[0x8]; 9671 u8 wol_mode[0x8]; 9672 9673 u8 reserved_at_60[0x20]; 9674 }; 9675 9676 struct mlx5_ifc_query_wol_rol_in_bits { 9677 u8 opcode[0x10]; 9678 u8 reserved_at_10[0x10]; 9679 9680 u8 reserved_at_20[0x10]; 9681 u8 op_mod[0x10]; 9682 9683 u8 reserved_at_40[0x40]; 9684 }; 9685 9686 struct mlx5_ifc_set_wol_rol_out_bits { 9687 u8 status[0x8]; 9688 u8 reserved_at_8[0x18]; 9689 9690 u8 syndrome[0x20]; 9691 9692 u8 reserved_at_40[0x40]; 9693 }; 9694 9695 struct mlx5_ifc_set_wol_rol_in_bits { 9696 u8 opcode[0x10]; 9697 u8 reserved_at_10[0x10]; 9698 9699 u8 reserved_at_20[0x10]; 9700 u8 op_mod[0x10]; 9701 9702 u8 rol_mode_valid[0x1]; 9703 u8 wol_mode_valid[0x1]; 9704 u8 reserved_at_42[0xe]; 9705 u8 rol_mode[0x8]; 9706 u8 wol_mode[0x8]; 9707 9708 u8 reserved_at_60[0x20]; 9709 }; 9710 9711 enum { 9712 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9713 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9714 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9715 }; 9716 9717 enum { 9718 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9719 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9720 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9721 }; 9722 9723 enum { 9724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9731 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9732 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9733 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9734 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9735 }; 9736 9737 struct mlx5_ifc_initial_seg_bits { 9738 u8 fw_rev_minor[0x10]; 9739 u8 fw_rev_major[0x10]; 9740 9741 u8 cmd_interface_rev[0x10]; 9742 u8 fw_rev_subminor[0x10]; 9743 9744 u8 reserved_at_40[0x40]; 9745 9746 u8 cmdq_phy_addr_63_32[0x20]; 9747 9748 u8 cmdq_phy_addr_31_12[0x14]; 9749 u8 reserved_at_b4[0x2]; 9750 u8 nic_interface[0x2]; 9751 u8 log_cmdq_size[0x4]; 9752 u8 log_cmdq_stride[0x4]; 9753 9754 u8 command_doorbell_vector[0x20]; 9755 9756 u8 reserved_at_e0[0xf00]; 9757 9758 u8 initializing[0x1]; 9759 u8 reserved_at_fe1[0x4]; 9760 u8 nic_interface_supported[0x3]; 9761 u8 embedded_cpu[0x1]; 9762 u8 reserved_at_fe9[0x17]; 9763 9764 struct mlx5_ifc_health_buffer_bits health_buffer; 9765 9766 u8 no_dram_nic_offset[0x20]; 9767 9768 u8 reserved_at_1220[0x6e40]; 9769 9770 u8 reserved_at_8060[0x1f]; 9771 u8 clear_int[0x1]; 9772 9773 u8 health_syndrome[0x8]; 9774 u8 health_counter[0x18]; 9775 9776 u8 reserved_at_80a0[0x17fc0]; 9777 }; 9778 9779 struct mlx5_ifc_mtpps_reg_bits { 9780 u8 reserved_at_0[0xc]; 9781 u8 cap_number_of_pps_pins[0x4]; 9782 u8 reserved_at_10[0x4]; 9783 u8 cap_max_num_of_pps_in_pins[0x4]; 9784 u8 reserved_at_18[0x4]; 9785 u8 cap_max_num_of_pps_out_pins[0x4]; 9786 9787 u8 reserved_at_20[0x24]; 9788 u8 cap_pin_3_mode[0x4]; 9789 u8 reserved_at_48[0x4]; 9790 u8 cap_pin_2_mode[0x4]; 9791 u8 reserved_at_50[0x4]; 9792 u8 cap_pin_1_mode[0x4]; 9793 u8 reserved_at_58[0x4]; 9794 u8 cap_pin_0_mode[0x4]; 9795 9796 u8 reserved_at_60[0x4]; 9797 u8 cap_pin_7_mode[0x4]; 9798 u8 reserved_at_68[0x4]; 9799 u8 cap_pin_6_mode[0x4]; 9800 u8 reserved_at_70[0x4]; 9801 u8 cap_pin_5_mode[0x4]; 9802 u8 reserved_at_78[0x4]; 9803 u8 cap_pin_4_mode[0x4]; 9804 9805 u8 field_select[0x20]; 9806 u8 reserved_at_a0[0x60]; 9807 9808 u8 enable[0x1]; 9809 u8 reserved_at_101[0xb]; 9810 u8 pattern[0x4]; 9811 u8 reserved_at_110[0x4]; 9812 u8 pin_mode[0x4]; 9813 u8 pin[0x8]; 9814 9815 u8 reserved_at_120[0x20]; 9816 9817 u8 time_stamp[0x40]; 9818 9819 u8 out_pulse_duration[0x10]; 9820 u8 out_periodic_adjustment[0x10]; 9821 u8 enhanced_out_periodic_adjustment[0x20]; 9822 9823 u8 reserved_at_1c0[0x20]; 9824 }; 9825 9826 struct mlx5_ifc_mtppse_reg_bits { 9827 u8 reserved_at_0[0x18]; 9828 u8 pin[0x8]; 9829 u8 event_arm[0x1]; 9830 u8 reserved_at_21[0x1b]; 9831 u8 event_generation_mode[0x4]; 9832 u8 reserved_at_40[0x40]; 9833 }; 9834 9835 struct mlx5_ifc_mcqs_reg_bits { 9836 u8 last_index_flag[0x1]; 9837 u8 reserved_at_1[0x7]; 9838 u8 fw_device[0x8]; 9839 u8 component_index[0x10]; 9840 9841 u8 reserved_at_20[0x10]; 9842 u8 identifier[0x10]; 9843 9844 u8 reserved_at_40[0x17]; 9845 u8 component_status[0x5]; 9846 u8 component_update_state[0x4]; 9847 9848 u8 last_update_state_changer_type[0x4]; 9849 u8 last_update_state_changer_host_id[0x4]; 9850 u8 reserved_at_68[0x18]; 9851 }; 9852 9853 struct mlx5_ifc_mcqi_cap_bits { 9854 u8 supported_info_bitmask[0x20]; 9855 9856 u8 component_size[0x20]; 9857 9858 u8 max_component_size[0x20]; 9859 9860 u8 log_mcda_word_size[0x4]; 9861 u8 reserved_at_64[0xc]; 9862 u8 mcda_max_write_size[0x10]; 9863 9864 u8 rd_en[0x1]; 9865 u8 reserved_at_81[0x1]; 9866 u8 match_chip_id[0x1]; 9867 u8 match_psid[0x1]; 9868 u8 check_user_timestamp[0x1]; 9869 u8 match_base_guid_mac[0x1]; 9870 u8 reserved_at_86[0x1a]; 9871 }; 9872 9873 struct mlx5_ifc_mcqi_version_bits { 9874 u8 reserved_at_0[0x2]; 9875 u8 build_time_valid[0x1]; 9876 u8 user_defined_time_valid[0x1]; 9877 u8 reserved_at_4[0x14]; 9878 u8 version_string_length[0x8]; 9879 9880 u8 version[0x20]; 9881 9882 u8 build_time[0x40]; 9883 9884 u8 user_defined_time[0x40]; 9885 9886 u8 build_tool_version[0x20]; 9887 9888 u8 reserved_at_e0[0x20]; 9889 9890 u8 version_string[92][0x8]; 9891 }; 9892 9893 struct mlx5_ifc_mcqi_activation_method_bits { 9894 u8 pending_server_ac_power_cycle[0x1]; 9895 u8 pending_server_dc_power_cycle[0x1]; 9896 u8 pending_server_reboot[0x1]; 9897 u8 pending_fw_reset[0x1]; 9898 u8 auto_activate[0x1]; 9899 u8 all_hosts_sync[0x1]; 9900 u8 device_hw_reset[0x1]; 9901 u8 reserved_at_7[0x19]; 9902 }; 9903 9904 union mlx5_ifc_mcqi_reg_data_bits { 9905 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9906 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9907 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9908 }; 9909 9910 struct mlx5_ifc_mcqi_reg_bits { 9911 u8 read_pending_component[0x1]; 9912 u8 reserved_at_1[0xf]; 9913 u8 component_index[0x10]; 9914 9915 u8 reserved_at_20[0x20]; 9916 9917 u8 reserved_at_40[0x1b]; 9918 u8 info_type[0x5]; 9919 9920 u8 info_size[0x20]; 9921 9922 u8 offset[0x20]; 9923 9924 u8 reserved_at_a0[0x10]; 9925 u8 data_size[0x10]; 9926 9927 union mlx5_ifc_mcqi_reg_data_bits data[]; 9928 }; 9929 9930 struct mlx5_ifc_mcc_reg_bits { 9931 u8 reserved_at_0[0x4]; 9932 u8 time_elapsed_since_last_cmd[0xc]; 9933 u8 reserved_at_10[0x8]; 9934 u8 instruction[0x8]; 9935 9936 u8 reserved_at_20[0x10]; 9937 u8 component_index[0x10]; 9938 9939 u8 reserved_at_40[0x8]; 9940 u8 update_handle[0x18]; 9941 9942 u8 handle_owner_type[0x4]; 9943 u8 handle_owner_host_id[0x4]; 9944 u8 reserved_at_68[0x1]; 9945 u8 control_progress[0x7]; 9946 u8 error_code[0x8]; 9947 u8 reserved_at_78[0x4]; 9948 u8 control_state[0x4]; 9949 9950 u8 component_size[0x20]; 9951 9952 u8 reserved_at_a0[0x60]; 9953 }; 9954 9955 struct mlx5_ifc_mcda_reg_bits { 9956 u8 reserved_at_0[0x8]; 9957 u8 update_handle[0x18]; 9958 9959 u8 offset[0x20]; 9960 9961 u8 reserved_at_40[0x10]; 9962 u8 size[0x10]; 9963 9964 u8 reserved_at_60[0x20]; 9965 9966 u8 data[][0x20]; 9967 }; 9968 9969 enum { 9970 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9971 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9972 }; 9973 9974 enum { 9975 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9976 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9977 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9978 }; 9979 9980 struct mlx5_ifc_mfrl_reg_bits { 9981 u8 reserved_at_0[0x20]; 9982 9983 u8 reserved_at_20[0x2]; 9984 u8 pci_sync_for_fw_update_start[0x1]; 9985 u8 pci_sync_for_fw_update_resp[0x2]; 9986 u8 rst_type_sel[0x3]; 9987 u8 reserved_at_28[0x8]; 9988 u8 reset_type[0x8]; 9989 u8 reset_level[0x8]; 9990 }; 9991 9992 struct mlx5_ifc_mirc_reg_bits { 9993 u8 reserved_at_0[0x18]; 9994 u8 status_code[0x8]; 9995 9996 u8 reserved_at_20[0x20]; 9997 }; 9998 9999 struct mlx5_ifc_pddr_monitor_opcode_bits { 10000 u8 reserved_at_0[0x10]; 10001 u8 monitor_opcode[0x10]; 10002 }; 10003 10004 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10005 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10006 u8 reserved_at_0[0x20]; 10007 }; 10008 10009 enum { 10010 /* Monitor opcodes */ 10011 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10012 }; 10013 10014 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10015 u8 reserved_at_0[0x10]; 10016 u8 group_opcode[0x10]; 10017 10018 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10019 10020 u8 reserved_at_40[0x20]; 10021 10022 u8 status_message[59][0x20]; 10023 }; 10024 10025 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10026 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10027 u8 reserved_at_0[0x7c0]; 10028 }; 10029 10030 enum { 10031 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10032 }; 10033 10034 struct mlx5_ifc_pddr_reg_bits { 10035 u8 reserved_at_0[0x8]; 10036 u8 local_port[0x8]; 10037 u8 pnat[0x2]; 10038 u8 reserved_at_12[0xe]; 10039 10040 u8 reserved_at_20[0x18]; 10041 u8 page_select[0x8]; 10042 10043 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10044 }; 10045 10046 union mlx5_ifc_ports_control_registers_document_bits { 10047 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10048 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10049 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10050 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10051 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10052 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10053 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10054 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10055 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10056 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10057 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10058 struct mlx5_ifc_paos_reg_bits paos_reg; 10059 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10060 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10061 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10062 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10063 struct mlx5_ifc_peir_reg_bits peir_reg; 10064 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10065 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10066 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10067 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10068 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10069 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10070 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10071 struct mlx5_ifc_plib_reg_bits plib_reg; 10072 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10073 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10074 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10075 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10076 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10077 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10078 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10079 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10080 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10081 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10082 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10083 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10084 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10085 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10086 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10087 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10088 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10089 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10090 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10091 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10092 struct mlx5_ifc_pude_reg_bits pude_reg; 10093 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10094 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10095 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10096 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10097 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10098 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10099 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10100 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10101 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10102 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10103 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10104 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10105 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10106 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10107 u8 reserved_at_0[0x60e0]; 10108 }; 10109 10110 union mlx5_ifc_debug_enhancements_document_bits { 10111 struct mlx5_ifc_health_buffer_bits health_buffer; 10112 u8 reserved_at_0[0x200]; 10113 }; 10114 10115 union mlx5_ifc_uplink_pci_interface_document_bits { 10116 struct mlx5_ifc_initial_seg_bits initial_seg; 10117 u8 reserved_at_0[0x20060]; 10118 }; 10119 10120 struct mlx5_ifc_set_flow_table_root_out_bits { 10121 u8 status[0x8]; 10122 u8 reserved_at_8[0x18]; 10123 10124 u8 syndrome[0x20]; 10125 10126 u8 reserved_at_40[0x40]; 10127 }; 10128 10129 struct mlx5_ifc_set_flow_table_root_in_bits { 10130 u8 opcode[0x10]; 10131 u8 reserved_at_10[0x10]; 10132 10133 u8 reserved_at_20[0x10]; 10134 u8 op_mod[0x10]; 10135 10136 u8 other_vport[0x1]; 10137 u8 reserved_at_41[0xf]; 10138 u8 vport_number[0x10]; 10139 10140 u8 reserved_at_60[0x20]; 10141 10142 u8 table_type[0x8]; 10143 u8 reserved_at_88[0x7]; 10144 u8 table_of_other_vport[0x1]; 10145 u8 table_vport_number[0x10]; 10146 10147 u8 reserved_at_a0[0x8]; 10148 u8 table_id[0x18]; 10149 10150 u8 reserved_at_c0[0x8]; 10151 u8 underlay_qpn[0x18]; 10152 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10153 u8 reserved_at_e1[0xf]; 10154 u8 table_eswitch_owner_vhca_id[0x10]; 10155 u8 reserved_at_100[0x100]; 10156 }; 10157 10158 enum { 10159 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10160 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10161 }; 10162 10163 struct mlx5_ifc_modify_flow_table_out_bits { 10164 u8 status[0x8]; 10165 u8 reserved_at_8[0x18]; 10166 10167 u8 syndrome[0x20]; 10168 10169 u8 reserved_at_40[0x40]; 10170 }; 10171 10172 struct mlx5_ifc_modify_flow_table_in_bits { 10173 u8 opcode[0x10]; 10174 u8 reserved_at_10[0x10]; 10175 10176 u8 reserved_at_20[0x10]; 10177 u8 op_mod[0x10]; 10178 10179 u8 other_vport[0x1]; 10180 u8 reserved_at_41[0xf]; 10181 u8 vport_number[0x10]; 10182 10183 u8 reserved_at_60[0x10]; 10184 u8 modify_field_select[0x10]; 10185 10186 u8 table_type[0x8]; 10187 u8 reserved_at_88[0x18]; 10188 10189 u8 reserved_at_a0[0x8]; 10190 u8 table_id[0x18]; 10191 10192 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10193 }; 10194 10195 struct mlx5_ifc_ets_tcn_config_reg_bits { 10196 u8 g[0x1]; 10197 u8 b[0x1]; 10198 u8 r[0x1]; 10199 u8 reserved_at_3[0x9]; 10200 u8 group[0x4]; 10201 u8 reserved_at_10[0x9]; 10202 u8 bw_allocation[0x7]; 10203 10204 u8 reserved_at_20[0xc]; 10205 u8 max_bw_units[0x4]; 10206 u8 reserved_at_30[0x8]; 10207 u8 max_bw_value[0x8]; 10208 }; 10209 10210 struct mlx5_ifc_ets_global_config_reg_bits { 10211 u8 reserved_at_0[0x2]; 10212 u8 r[0x1]; 10213 u8 reserved_at_3[0x1d]; 10214 10215 u8 reserved_at_20[0xc]; 10216 u8 max_bw_units[0x4]; 10217 u8 reserved_at_30[0x8]; 10218 u8 max_bw_value[0x8]; 10219 }; 10220 10221 struct mlx5_ifc_qetc_reg_bits { 10222 u8 reserved_at_0[0x8]; 10223 u8 port_number[0x8]; 10224 u8 reserved_at_10[0x30]; 10225 10226 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10227 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10228 }; 10229 10230 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10231 u8 e[0x1]; 10232 u8 reserved_at_01[0x0b]; 10233 u8 prio[0x04]; 10234 }; 10235 10236 struct mlx5_ifc_qpdpm_reg_bits { 10237 u8 reserved_at_0[0x8]; 10238 u8 local_port[0x8]; 10239 u8 reserved_at_10[0x10]; 10240 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10241 }; 10242 10243 struct mlx5_ifc_qpts_reg_bits { 10244 u8 reserved_at_0[0x8]; 10245 u8 local_port[0x8]; 10246 u8 reserved_at_10[0x2d]; 10247 u8 trust_state[0x3]; 10248 }; 10249 10250 struct mlx5_ifc_pptb_reg_bits { 10251 u8 reserved_at_0[0x2]; 10252 u8 mm[0x2]; 10253 u8 reserved_at_4[0x4]; 10254 u8 local_port[0x8]; 10255 u8 reserved_at_10[0x6]; 10256 u8 cm[0x1]; 10257 u8 um[0x1]; 10258 u8 pm[0x8]; 10259 10260 u8 prio_x_buff[0x20]; 10261 10262 u8 pm_msb[0x8]; 10263 u8 reserved_at_48[0x10]; 10264 u8 ctrl_buff[0x4]; 10265 u8 untagged_buff[0x4]; 10266 }; 10267 10268 struct mlx5_ifc_sbcam_reg_bits { 10269 u8 reserved_at_0[0x8]; 10270 u8 feature_group[0x8]; 10271 u8 reserved_at_10[0x8]; 10272 u8 access_reg_group[0x8]; 10273 10274 u8 reserved_at_20[0x20]; 10275 10276 u8 sb_access_reg_cap_mask[4][0x20]; 10277 10278 u8 reserved_at_c0[0x80]; 10279 10280 u8 sb_feature_cap_mask[4][0x20]; 10281 10282 u8 reserved_at_1c0[0x40]; 10283 10284 u8 cap_total_buffer_size[0x20]; 10285 10286 u8 cap_cell_size[0x10]; 10287 u8 cap_max_pg_buffers[0x8]; 10288 u8 cap_num_pool_supported[0x8]; 10289 10290 u8 reserved_at_240[0x8]; 10291 u8 cap_sbsr_stat_size[0x8]; 10292 u8 cap_max_tclass_data[0x8]; 10293 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10294 }; 10295 10296 struct mlx5_ifc_pbmc_reg_bits { 10297 u8 reserved_at_0[0x8]; 10298 u8 local_port[0x8]; 10299 u8 reserved_at_10[0x10]; 10300 10301 u8 xoff_timer_value[0x10]; 10302 u8 xoff_refresh[0x10]; 10303 10304 u8 reserved_at_40[0x9]; 10305 u8 fullness_threshold[0x7]; 10306 u8 port_buffer_size[0x10]; 10307 10308 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10309 10310 u8 reserved_at_2e0[0x80]; 10311 }; 10312 10313 struct mlx5_ifc_qtct_reg_bits { 10314 u8 reserved_at_0[0x8]; 10315 u8 port_number[0x8]; 10316 u8 reserved_at_10[0xd]; 10317 u8 prio[0x3]; 10318 10319 u8 reserved_at_20[0x1d]; 10320 u8 tclass[0x3]; 10321 }; 10322 10323 struct mlx5_ifc_mcia_reg_bits { 10324 u8 l[0x1]; 10325 u8 reserved_at_1[0x7]; 10326 u8 module[0x8]; 10327 u8 reserved_at_10[0x8]; 10328 u8 status[0x8]; 10329 10330 u8 i2c_device_address[0x8]; 10331 u8 page_number[0x8]; 10332 u8 device_address[0x10]; 10333 10334 u8 reserved_at_40[0x10]; 10335 u8 size[0x10]; 10336 10337 u8 reserved_at_60[0x20]; 10338 10339 u8 dword_0[0x20]; 10340 u8 dword_1[0x20]; 10341 u8 dword_2[0x20]; 10342 u8 dword_3[0x20]; 10343 u8 dword_4[0x20]; 10344 u8 dword_5[0x20]; 10345 u8 dword_6[0x20]; 10346 u8 dword_7[0x20]; 10347 u8 dword_8[0x20]; 10348 u8 dword_9[0x20]; 10349 u8 dword_10[0x20]; 10350 u8 dword_11[0x20]; 10351 }; 10352 10353 struct mlx5_ifc_dcbx_param_bits { 10354 u8 dcbx_cee_cap[0x1]; 10355 u8 dcbx_ieee_cap[0x1]; 10356 u8 dcbx_standby_cap[0x1]; 10357 u8 reserved_at_3[0x5]; 10358 u8 port_number[0x8]; 10359 u8 reserved_at_10[0xa]; 10360 u8 max_application_table_size[6]; 10361 u8 reserved_at_20[0x15]; 10362 u8 version_oper[0x3]; 10363 u8 reserved_at_38[5]; 10364 u8 version_admin[0x3]; 10365 u8 willing_admin[0x1]; 10366 u8 reserved_at_41[0x3]; 10367 u8 pfc_cap_oper[0x4]; 10368 u8 reserved_at_48[0x4]; 10369 u8 pfc_cap_admin[0x4]; 10370 u8 reserved_at_50[0x4]; 10371 u8 num_of_tc_oper[0x4]; 10372 u8 reserved_at_58[0x4]; 10373 u8 num_of_tc_admin[0x4]; 10374 u8 remote_willing[0x1]; 10375 u8 reserved_at_61[3]; 10376 u8 remote_pfc_cap[4]; 10377 u8 reserved_at_68[0x14]; 10378 u8 remote_num_of_tc[0x4]; 10379 u8 reserved_at_80[0x18]; 10380 u8 error[0x8]; 10381 u8 reserved_at_a0[0x160]; 10382 }; 10383 10384 struct mlx5_ifc_lagc_bits { 10385 u8 fdb_selection_mode[0x1]; 10386 u8 reserved_at_1[0x1c]; 10387 u8 lag_state[0x3]; 10388 10389 u8 reserved_at_20[0x14]; 10390 u8 tx_remap_affinity_2[0x4]; 10391 u8 reserved_at_38[0x4]; 10392 u8 tx_remap_affinity_1[0x4]; 10393 }; 10394 10395 struct mlx5_ifc_create_lag_out_bits { 10396 u8 status[0x8]; 10397 u8 reserved_at_8[0x18]; 10398 10399 u8 syndrome[0x20]; 10400 10401 u8 reserved_at_40[0x40]; 10402 }; 10403 10404 struct mlx5_ifc_create_lag_in_bits { 10405 u8 opcode[0x10]; 10406 u8 reserved_at_10[0x10]; 10407 10408 u8 reserved_at_20[0x10]; 10409 u8 op_mod[0x10]; 10410 10411 struct mlx5_ifc_lagc_bits ctx; 10412 }; 10413 10414 struct mlx5_ifc_modify_lag_out_bits { 10415 u8 status[0x8]; 10416 u8 reserved_at_8[0x18]; 10417 10418 u8 syndrome[0x20]; 10419 10420 u8 reserved_at_40[0x40]; 10421 }; 10422 10423 struct mlx5_ifc_modify_lag_in_bits { 10424 u8 opcode[0x10]; 10425 u8 reserved_at_10[0x10]; 10426 10427 u8 reserved_at_20[0x10]; 10428 u8 op_mod[0x10]; 10429 10430 u8 reserved_at_40[0x20]; 10431 u8 field_select[0x20]; 10432 10433 struct mlx5_ifc_lagc_bits ctx; 10434 }; 10435 10436 struct mlx5_ifc_query_lag_out_bits { 10437 u8 status[0x8]; 10438 u8 reserved_at_8[0x18]; 10439 10440 u8 syndrome[0x20]; 10441 10442 struct mlx5_ifc_lagc_bits ctx; 10443 }; 10444 10445 struct mlx5_ifc_query_lag_in_bits { 10446 u8 opcode[0x10]; 10447 u8 reserved_at_10[0x10]; 10448 10449 u8 reserved_at_20[0x10]; 10450 u8 op_mod[0x10]; 10451 10452 u8 reserved_at_40[0x40]; 10453 }; 10454 10455 struct mlx5_ifc_destroy_lag_out_bits { 10456 u8 status[0x8]; 10457 u8 reserved_at_8[0x18]; 10458 10459 u8 syndrome[0x20]; 10460 10461 u8 reserved_at_40[0x40]; 10462 }; 10463 10464 struct mlx5_ifc_destroy_lag_in_bits { 10465 u8 opcode[0x10]; 10466 u8 reserved_at_10[0x10]; 10467 10468 u8 reserved_at_20[0x10]; 10469 u8 op_mod[0x10]; 10470 10471 u8 reserved_at_40[0x40]; 10472 }; 10473 10474 struct mlx5_ifc_create_vport_lag_out_bits { 10475 u8 status[0x8]; 10476 u8 reserved_at_8[0x18]; 10477 10478 u8 syndrome[0x20]; 10479 10480 u8 reserved_at_40[0x40]; 10481 }; 10482 10483 struct mlx5_ifc_create_vport_lag_in_bits { 10484 u8 opcode[0x10]; 10485 u8 reserved_at_10[0x10]; 10486 10487 u8 reserved_at_20[0x10]; 10488 u8 op_mod[0x10]; 10489 10490 u8 reserved_at_40[0x40]; 10491 }; 10492 10493 struct mlx5_ifc_destroy_vport_lag_out_bits { 10494 u8 status[0x8]; 10495 u8 reserved_at_8[0x18]; 10496 10497 u8 syndrome[0x20]; 10498 10499 u8 reserved_at_40[0x40]; 10500 }; 10501 10502 struct mlx5_ifc_destroy_vport_lag_in_bits { 10503 u8 opcode[0x10]; 10504 u8 reserved_at_10[0x10]; 10505 10506 u8 reserved_at_20[0x10]; 10507 u8 op_mod[0x10]; 10508 10509 u8 reserved_at_40[0x40]; 10510 }; 10511 10512 enum { 10513 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10514 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10515 }; 10516 10517 struct mlx5_ifc_modify_memic_in_bits { 10518 u8 opcode[0x10]; 10519 u8 uid[0x10]; 10520 10521 u8 reserved_at_20[0x10]; 10522 u8 op_mod[0x10]; 10523 10524 u8 reserved_at_40[0x20]; 10525 10526 u8 reserved_at_60[0x18]; 10527 u8 memic_operation_type[0x8]; 10528 10529 u8 memic_start_addr[0x40]; 10530 10531 u8 reserved_at_c0[0x140]; 10532 }; 10533 10534 struct mlx5_ifc_modify_memic_out_bits { 10535 u8 status[0x8]; 10536 u8 reserved_at_8[0x18]; 10537 10538 u8 syndrome[0x20]; 10539 10540 u8 reserved_at_40[0x40]; 10541 10542 u8 memic_operation_addr[0x40]; 10543 10544 u8 reserved_at_c0[0x140]; 10545 }; 10546 10547 struct mlx5_ifc_alloc_memic_in_bits { 10548 u8 opcode[0x10]; 10549 u8 reserved_at_10[0x10]; 10550 10551 u8 reserved_at_20[0x10]; 10552 u8 op_mod[0x10]; 10553 10554 u8 reserved_at_30[0x20]; 10555 10556 u8 reserved_at_40[0x18]; 10557 u8 log_memic_addr_alignment[0x8]; 10558 10559 u8 range_start_addr[0x40]; 10560 10561 u8 range_size[0x20]; 10562 10563 u8 memic_size[0x20]; 10564 }; 10565 10566 struct mlx5_ifc_alloc_memic_out_bits { 10567 u8 status[0x8]; 10568 u8 reserved_at_8[0x18]; 10569 10570 u8 syndrome[0x20]; 10571 10572 u8 memic_start_addr[0x40]; 10573 }; 10574 10575 struct mlx5_ifc_dealloc_memic_in_bits { 10576 u8 opcode[0x10]; 10577 u8 reserved_at_10[0x10]; 10578 10579 u8 reserved_at_20[0x10]; 10580 u8 op_mod[0x10]; 10581 10582 u8 reserved_at_40[0x40]; 10583 10584 u8 memic_start_addr[0x40]; 10585 10586 u8 memic_size[0x20]; 10587 10588 u8 reserved_at_e0[0x20]; 10589 }; 10590 10591 struct mlx5_ifc_dealloc_memic_out_bits { 10592 u8 status[0x8]; 10593 u8 reserved_at_8[0x18]; 10594 10595 u8 syndrome[0x20]; 10596 10597 u8 reserved_at_40[0x40]; 10598 }; 10599 10600 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10601 u8 opcode[0x10]; 10602 u8 uid[0x10]; 10603 10604 u8 vhca_tunnel_id[0x10]; 10605 u8 obj_type[0x10]; 10606 10607 u8 obj_id[0x20]; 10608 10609 u8 reserved_at_60[0x20]; 10610 }; 10611 10612 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10613 u8 status[0x8]; 10614 u8 reserved_at_8[0x18]; 10615 10616 u8 syndrome[0x20]; 10617 10618 u8 obj_id[0x20]; 10619 10620 u8 reserved_at_60[0x20]; 10621 }; 10622 10623 struct mlx5_ifc_umem_bits { 10624 u8 reserved_at_0[0x80]; 10625 10626 u8 reserved_at_80[0x1b]; 10627 u8 log_page_size[0x5]; 10628 10629 u8 page_offset[0x20]; 10630 10631 u8 num_of_mtt[0x40]; 10632 10633 struct mlx5_ifc_mtt_bits mtt[]; 10634 }; 10635 10636 struct mlx5_ifc_uctx_bits { 10637 u8 cap[0x20]; 10638 10639 u8 reserved_at_20[0x160]; 10640 }; 10641 10642 struct mlx5_ifc_sw_icm_bits { 10643 u8 modify_field_select[0x40]; 10644 10645 u8 reserved_at_40[0x18]; 10646 u8 log_sw_icm_size[0x8]; 10647 10648 u8 reserved_at_60[0x20]; 10649 10650 u8 sw_icm_start_addr[0x40]; 10651 10652 u8 reserved_at_c0[0x140]; 10653 }; 10654 10655 struct mlx5_ifc_geneve_tlv_option_bits { 10656 u8 modify_field_select[0x40]; 10657 10658 u8 reserved_at_40[0x18]; 10659 u8 geneve_option_fte_index[0x8]; 10660 10661 u8 option_class[0x10]; 10662 u8 option_type[0x8]; 10663 u8 reserved_at_78[0x3]; 10664 u8 option_data_length[0x5]; 10665 10666 u8 reserved_at_80[0x180]; 10667 }; 10668 10669 struct mlx5_ifc_create_umem_in_bits { 10670 u8 opcode[0x10]; 10671 u8 uid[0x10]; 10672 10673 u8 reserved_at_20[0x10]; 10674 u8 op_mod[0x10]; 10675 10676 u8 reserved_at_40[0x40]; 10677 10678 struct mlx5_ifc_umem_bits umem; 10679 }; 10680 10681 struct mlx5_ifc_create_umem_out_bits { 10682 u8 status[0x8]; 10683 u8 reserved_at_8[0x18]; 10684 10685 u8 syndrome[0x20]; 10686 10687 u8 reserved_at_40[0x8]; 10688 u8 umem_id[0x18]; 10689 10690 u8 reserved_at_60[0x20]; 10691 }; 10692 10693 struct mlx5_ifc_destroy_umem_in_bits { 10694 u8 opcode[0x10]; 10695 u8 uid[0x10]; 10696 10697 u8 reserved_at_20[0x10]; 10698 u8 op_mod[0x10]; 10699 10700 u8 reserved_at_40[0x8]; 10701 u8 umem_id[0x18]; 10702 10703 u8 reserved_at_60[0x20]; 10704 }; 10705 10706 struct mlx5_ifc_destroy_umem_out_bits { 10707 u8 status[0x8]; 10708 u8 reserved_at_8[0x18]; 10709 10710 u8 syndrome[0x20]; 10711 10712 u8 reserved_at_40[0x40]; 10713 }; 10714 10715 struct mlx5_ifc_create_uctx_in_bits { 10716 u8 opcode[0x10]; 10717 u8 reserved_at_10[0x10]; 10718 10719 u8 reserved_at_20[0x10]; 10720 u8 op_mod[0x10]; 10721 10722 u8 reserved_at_40[0x40]; 10723 10724 struct mlx5_ifc_uctx_bits uctx; 10725 }; 10726 10727 struct mlx5_ifc_create_uctx_out_bits { 10728 u8 status[0x8]; 10729 u8 reserved_at_8[0x18]; 10730 10731 u8 syndrome[0x20]; 10732 10733 u8 reserved_at_40[0x10]; 10734 u8 uid[0x10]; 10735 10736 u8 reserved_at_60[0x20]; 10737 }; 10738 10739 struct mlx5_ifc_destroy_uctx_in_bits { 10740 u8 opcode[0x10]; 10741 u8 reserved_at_10[0x10]; 10742 10743 u8 reserved_at_20[0x10]; 10744 u8 op_mod[0x10]; 10745 10746 u8 reserved_at_40[0x10]; 10747 u8 uid[0x10]; 10748 10749 u8 reserved_at_60[0x20]; 10750 }; 10751 10752 struct mlx5_ifc_destroy_uctx_out_bits { 10753 u8 status[0x8]; 10754 u8 reserved_at_8[0x18]; 10755 10756 u8 syndrome[0x20]; 10757 10758 u8 reserved_at_40[0x40]; 10759 }; 10760 10761 struct mlx5_ifc_create_sw_icm_in_bits { 10762 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10763 struct mlx5_ifc_sw_icm_bits sw_icm; 10764 }; 10765 10766 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10767 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10768 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10769 }; 10770 10771 struct mlx5_ifc_mtrc_string_db_param_bits { 10772 u8 string_db_base_address[0x20]; 10773 10774 u8 reserved_at_20[0x8]; 10775 u8 string_db_size[0x18]; 10776 }; 10777 10778 struct mlx5_ifc_mtrc_cap_bits { 10779 u8 trace_owner[0x1]; 10780 u8 trace_to_memory[0x1]; 10781 u8 reserved_at_2[0x4]; 10782 u8 trc_ver[0x2]; 10783 u8 reserved_at_8[0x14]; 10784 u8 num_string_db[0x4]; 10785 10786 u8 first_string_trace[0x8]; 10787 u8 num_string_trace[0x8]; 10788 u8 reserved_at_30[0x28]; 10789 10790 u8 log_max_trace_buffer_size[0x8]; 10791 10792 u8 reserved_at_60[0x20]; 10793 10794 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10795 10796 u8 reserved_at_280[0x180]; 10797 }; 10798 10799 struct mlx5_ifc_mtrc_conf_bits { 10800 u8 reserved_at_0[0x1c]; 10801 u8 trace_mode[0x4]; 10802 u8 reserved_at_20[0x18]; 10803 u8 log_trace_buffer_size[0x8]; 10804 u8 trace_mkey[0x20]; 10805 u8 reserved_at_60[0x3a0]; 10806 }; 10807 10808 struct mlx5_ifc_mtrc_stdb_bits { 10809 u8 string_db_index[0x4]; 10810 u8 reserved_at_4[0x4]; 10811 u8 read_size[0x18]; 10812 u8 start_offset[0x20]; 10813 u8 string_db_data[]; 10814 }; 10815 10816 struct mlx5_ifc_mtrc_ctrl_bits { 10817 u8 trace_status[0x2]; 10818 u8 reserved_at_2[0x2]; 10819 u8 arm_event[0x1]; 10820 u8 reserved_at_5[0xb]; 10821 u8 modify_field_select[0x10]; 10822 u8 reserved_at_20[0x2b]; 10823 u8 current_timestamp52_32[0x15]; 10824 u8 current_timestamp31_0[0x20]; 10825 u8 reserved_at_80[0x180]; 10826 }; 10827 10828 struct mlx5_ifc_host_params_context_bits { 10829 u8 host_number[0x8]; 10830 u8 reserved_at_8[0x7]; 10831 u8 host_pf_disabled[0x1]; 10832 u8 host_num_of_vfs[0x10]; 10833 10834 u8 host_total_vfs[0x10]; 10835 u8 host_pci_bus[0x10]; 10836 10837 u8 reserved_at_40[0x10]; 10838 u8 host_pci_device[0x10]; 10839 10840 u8 reserved_at_60[0x10]; 10841 u8 host_pci_function[0x10]; 10842 10843 u8 reserved_at_80[0x180]; 10844 }; 10845 10846 struct mlx5_ifc_query_esw_functions_in_bits { 10847 u8 opcode[0x10]; 10848 u8 reserved_at_10[0x10]; 10849 10850 u8 reserved_at_20[0x10]; 10851 u8 op_mod[0x10]; 10852 10853 u8 reserved_at_40[0x40]; 10854 }; 10855 10856 struct mlx5_ifc_query_esw_functions_out_bits { 10857 u8 status[0x8]; 10858 u8 reserved_at_8[0x18]; 10859 10860 u8 syndrome[0x20]; 10861 10862 u8 reserved_at_40[0x40]; 10863 10864 struct mlx5_ifc_host_params_context_bits host_params_context; 10865 10866 u8 reserved_at_280[0x180]; 10867 u8 host_sf_enable[][0x40]; 10868 }; 10869 10870 struct mlx5_ifc_sf_partition_bits { 10871 u8 reserved_at_0[0x10]; 10872 u8 log_num_sf[0x8]; 10873 u8 log_sf_bar_size[0x8]; 10874 }; 10875 10876 struct mlx5_ifc_query_sf_partitions_out_bits { 10877 u8 status[0x8]; 10878 u8 reserved_at_8[0x18]; 10879 10880 u8 syndrome[0x20]; 10881 10882 u8 reserved_at_40[0x18]; 10883 u8 num_sf_partitions[0x8]; 10884 10885 u8 reserved_at_60[0x20]; 10886 10887 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10888 }; 10889 10890 struct mlx5_ifc_query_sf_partitions_in_bits { 10891 u8 opcode[0x10]; 10892 u8 reserved_at_10[0x10]; 10893 10894 u8 reserved_at_20[0x10]; 10895 u8 op_mod[0x10]; 10896 10897 u8 reserved_at_40[0x40]; 10898 }; 10899 10900 struct mlx5_ifc_dealloc_sf_out_bits { 10901 u8 status[0x8]; 10902 u8 reserved_at_8[0x18]; 10903 10904 u8 syndrome[0x20]; 10905 10906 u8 reserved_at_40[0x40]; 10907 }; 10908 10909 struct mlx5_ifc_dealloc_sf_in_bits { 10910 u8 opcode[0x10]; 10911 u8 reserved_at_10[0x10]; 10912 10913 u8 reserved_at_20[0x10]; 10914 u8 op_mod[0x10]; 10915 10916 u8 reserved_at_40[0x10]; 10917 u8 function_id[0x10]; 10918 10919 u8 reserved_at_60[0x20]; 10920 }; 10921 10922 struct mlx5_ifc_alloc_sf_out_bits { 10923 u8 status[0x8]; 10924 u8 reserved_at_8[0x18]; 10925 10926 u8 syndrome[0x20]; 10927 10928 u8 reserved_at_40[0x40]; 10929 }; 10930 10931 struct mlx5_ifc_alloc_sf_in_bits { 10932 u8 opcode[0x10]; 10933 u8 reserved_at_10[0x10]; 10934 10935 u8 reserved_at_20[0x10]; 10936 u8 op_mod[0x10]; 10937 10938 u8 reserved_at_40[0x10]; 10939 u8 function_id[0x10]; 10940 10941 u8 reserved_at_60[0x20]; 10942 }; 10943 10944 struct mlx5_ifc_affiliated_event_header_bits { 10945 u8 reserved_at_0[0x10]; 10946 u8 obj_type[0x10]; 10947 10948 u8 obj_id[0x20]; 10949 }; 10950 10951 enum { 10952 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10953 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10954 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10955 }; 10956 10957 enum { 10958 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10959 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10960 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10961 }; 10962 10963 enum { 10964 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10965 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10966 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10967 }; 10968 10969 struct mlx5_ifc_ipsec_obj_bits { 10970 u8 modify_field_select[0x40]; 10971 u8 full_offload[0x1]; 10972 u8 reserved_at_41[0x1]; 10973 u8 esn_en[0x1]; 10974 u8 esn_overlap[0x1]; 10975 u8 reserved_at_44[0x2]; 10976 u8 icv_length[0x2]; 10977 u8 reserved_at_48[0x4]; 10978 u8 aso_return_reg[0x4]; 10979 u8 reserved_at_50[0x10]; 10980 10981 u8 esn_msb[0x20]; 10982 10983 u8 reserved_at_80[0x8]; 10984 u8 dekn[0x18]; 10985 10986 u8 salt[0x20]; 10987 10988 u8 implicit_iv[0x40]; 10989 10990 u8 reserved_at_100[0x700]; 10991 }; 10992 10993 struct mlx5_ifc_create_ipsec_obj_in_bits { 10994 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10995 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10996 }; 10997 10998 enum { 10999 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11000 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11001 }; 11002 11003 struct mlx5_ifc_query_ipsec_obj_out_bits { 11004 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11005 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11006 }; 11007 11008 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11009 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11010 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11011 }; 11012 11013 struct mlx5_ifc_encryption_key_obj_bits { 11014 u8 modify_field_select[0x40]; 11015 11016 u8 reserved_at_40[0x14]; 11017 u8 key_size[0x4]; 11018 u8 reserved_at_58[0x4]; 11019 u8 key_type[0x4]; 11020 11021 u8 reserved_at_60[0x8]; 11022 u8 pd[0x18]; 11023 11024 u8 reserved_at_80[0x180]; 11025 u8 key[8][0x20]; 11026 11027 u8 reserved_at_300[0x500]; 11028 }; 11029 11030 struct mlx5_ifc_create_encryption_key_in_bits { 11031 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11032 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11033 }; 11034 11035 struct mlx5_ifc_sampler_obj_bits { 11036 u8 modify_field_select[0x40]; 11037 11038 u8 table_type[0x8]; 11039 u8 level[0x8]; 11040 u8 reserved_at_50[0xf]; 11041 u8 ignore_flow_level[0x1]; 11042 11043 u8 sample_ratio[0x20]; 11044 11045 u8 reserved_at_80[0x8]; 11046 u8 sample_table_id[0x18]; 11047 11048 u8 reserved_at_a0[0x8]; 11049 u8 default_table_id[0x18]; 11050 11051 u8 sw_steering_icm_address_rx[0x40]; 11052 u8 sw_steering_icm_address_tx[0x40]; 11053 11054 u8 reserved_at_140[0xa0]; 11055 }; 11056 11057 struct mlx5_ifc_create_sampler_obj_in_bits { 11058 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11059 struct mlx5_ifc_sampler_obj_bits sampler_object; 11060 }; 11061 11062 struct mlx5_ifc_query_sampler_obj_out_bits { 11063 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11064 struct mlx5_ifc_sampler_obj_bits sampler_object; 11065 }; 11066 11067 enum { 11068 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11069 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11070 }; 11071 11072 enum { 11073 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11074 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11075 }; 11076 11077 struct mlx5_ifc_tls_static_params_bits { 11078 u8 const_2[0x2]; 11079 u8 tls_version[0x4]; 11080 u8 const_1[0x2]; 11081 u8 reserved_at_8[0x14]; 11082 u8 encryption_standard[0x4]; 11083 11084 u8 reserved_at_20[0x20]; 11085 11086 u8 initial_record_number[0x40]; 11087 11088 u8 resync_tcp_sn[0x20]; 11089 11090 u8 gcm_iv[0x20]; 11091 11092 u8 implicit_iv[0x40]; 11093 11094 u8 reserved_at_100[0x8]; 11095 u8 dek_index[0x18]; 11096 11097 u8 reserved_at_120[0xe0]; 11098 }; 11099 11100 struct mlx5_ifc_tls_progress_params_bits { 11101 u8 next_record_tcp_sn[0x20]; 11102 11103 u8 hw_resync_tcp_sn[0x20]; 11104 11105 u8 record_tracker_state[0x2]; 11106 u8 auth_state[0x2]; 11107 u8 reserved_at_44[0x4]; 11108 u8 hw_offset_record_number[0x18]; 11109 }; 11110 11111 enum { 11112 MLX5_MTT_PERM_READ = 1 << 0, 11113 MLX5_MTT_PERM_WRITE = 1 << 1, 11114 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11115 }; 11116 11117 #endif /* MLX5_IFC_H */ 11118