1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 82 }; 83 84 enum { 85 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 86 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 87 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 88 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 89 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 90 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 96 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 99 MLX5_OBJ_TYPE_MKEY = 0xff01, 100 MLX5_OBJ_TYPE_QP = 0xff02, 101 MLX5_OBJ_TYPE_PSV = 0xff03, 102 MLX5_OBJ_TYPE_RMP = 0xff04, 103 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 104 MLX5_OBJ_TYPE_RQ = 0xff06, 105 MLX5_OBJ_TYPE_SQ = 0xff07, 106 MLX5_OBJ_TYPE_TIR = 0xff08, 107 MLX5_OBJ_TYPE_TIS = 0xff09, 108 MLX5_OBJ_TYPE_DCT = 0xff0a, 109 MLX5_OBJ_TYPE_XRQ = 0xff0b, 110 MLX5_OBJ_TYPE_RQT = 0xff0e, 111 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 112 MLX5_OBJ_TYPE_CQ = 0xff10, 113 }; 114 115 enum { 116 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 117 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 118 MLX5_CMD_OP_INIT_HCA = 0x102, 119 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 120 MLX5_CMD_OP_ENABLE_HCA = 0x104, 121 MLX5_CMD_OP_DISABLE_HCA = 0x105, 122 MLX5_CMD_OP_QUERY_PAGES = 0x107, 123 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 124 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 125 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 126 MLX5_CMD_OP_SET_ISSI = 0x10b, 127 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 128 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 129 MLX5_CMD_OP_ALLOC_SF = 0x113, 130 MLX5_CMD_OP_DEALLOC_SF = 0x114, 131 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 132 MLX5_CMD_OP_RESUME_VHCA = 0x116, 133 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 134 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 135 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 136 MLX5_CMD_OP_CREATE_MKEY = 0x200, 137 MLX5_CMD_OP_QUERY_MKEY = 0x201, 138 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 139 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 140 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 141 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 142 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 143 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 144 MLX5_CMD_OP_CREATE_EQ = 0x301, 145 MLX5_CMD_OP_DESTROY_EQ = 0x302, 146 MLX5_CMD_OP_QUERY_EQ = 0x303, 147 MLX5_CMD_OP_GEN_EQE = 0x304, 148 MLX5_CMD_OP_CREATE_CQ = 0x400, 149 MLX5_CMD_OP_DESTROY_CQ = 0x401, 150 MLX5_CMD_OP_QUERY_CQ = 0x402, 151 MLX5_CMD_OP_MODIFY_CQ = 0x403, 152 MLX5_CMD_OP_CREATE_QP = 0x500, 153 MLX5_CMD_OP_DESTROY_QP = 0x501, 154 MLX5_CMD_OP_RST2INIT_QP = 0x502, 155 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 156 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 157 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 158 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 159 MLX5_CMD_OP_2ERR_QP = 0x507, 160 MLX5_CMD_OP_2RST_QP = 0x50a, 161 MLX5_CMD_OP_QUERY_QP = 0x50b, 162 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 163 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 164 MLX5_CMD_OP_CREATE_PSV = 0x600, 165 MLX5_CMD_OP_DESTROY_PSV = 0x601, 166 MLX5_CMD_OP_CREATE_SRQ = 0x700, 167 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 168 MLX5_CMD_OP_QUERY_SRQ = 0x702, 169 MLX5_CMD_OP_ARM_RQ = 0x703, 170 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 171 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 172 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 173 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 174 MLX5_CMD_OP_CREATE_DCT = 0x710, 175 MLX5_CMD_OP_DESTROY_DCT = 0x711, 176 MLX5_CMD_OP_DRAIN_DCT = 0x712, 177 MLX5_CMD_OP_QUERY_DCT = 0x713, 178 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 179 MLX5_CMD_OP_CREATE_XRQ = 0x717, 180 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 181 MLX5_CMD_OP_QUERY_XRQ = 0x719, 182 MLX5_CMD_OP_ARM_XRQ = 0x71a, 183 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 184 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 185 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 186 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 187 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 188 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 189 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 190 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 191 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 192 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 193 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 194 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 195 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 196 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 198 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 200 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 201 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 202 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 203 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 204 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 205 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 206 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 207 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 208 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 209 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 210 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 211 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 212 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 213 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 214 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 215 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 216 MLX5_CMD_OP_ALLOC_PD = 0x800, 217 MLX5_CMD_OP_DEALLOC_PD = 0x801, 218 MLX5_CMD_OP_ALLOC_UAR = 0x802, 219 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 220 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 221 MLX5_CMD_OP_ACCESS_REG = 0x805, 222 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 223 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 224 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 225 MLX5_CMD_OP_MAD_IFC = 0x50d, 226 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 227 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 228 MLX5_CMD_OP_NOP = 0x80d, 229 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 230 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 231 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 232 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 233 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 234 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 235 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 236 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 237 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 238 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 239 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 240 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 241 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 242 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 243 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 244 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 245 MLX5_CMD_OP_CREATE_LAG = 0x840, 246 MLX5_CMD_OP_MODIFY_LAG = 0x841, 247 MLX5_CMD_OP_QUERY_LAG = 0x842, 248 MLX5_CMD_OP_DESTROY_LAG = 0x843, 249 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 250 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 251 MLX5_CMD_OP_CREATE_TIR = 0x900, 252 MLX5_CMD_OP_MODIFY_TIR = 0x901, 253 MLX5_CMD_OP_DESTROY_TIR = 0x902, 254 MLX5_CMD_OP_QUERY_TIR = 0x903, 255 MLX5_CMD_OP_CREATE_SQ = 0x904, 256 MLX5_CMD_OP_MODIFY_SQ = 0x905, 257 MLX5_CMD_OP_DESTROY_SQ = 0x906, 258 MLX5_CMD_OP_QUERY_SQ = 0x907, 259 MLX5_CMD_OP_CREATE_RQ = 0x908, 260 MLX5_CMD_OP_MODIFY_RQ = 0x909, 261 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 262 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 263 MLX5_CMD_OP_QUERY_RQ = 0x90b, 264 MLX5_CMD_OP_CREATE_RMP = 0x90c, 265 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 266 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 267 MLX5_CMD_OP_QUERY_RMP = 0x90f, 268 MLX5_CMD_OP_CREATE_TIS = 0x912, 269 MLX5_CMD_OP_MODIFY_TIS = 0x913, 270 MLX5_CMD_OP_DESTROY_TIS = 0x914, 271 MLX5_CMD_OP_QUERY_TIS = 0x915, 272 MLX5_CMD_OP_CREATE_RQT = 0x916, 273 MLX5_CMD_OP_MODIFY_RQT = 0x917, 274 MLX5_CMD_OP_DESTROY_RQT = 0x918, 275 MLX5_CMD_OP_QUERY_RQT = 0x919, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 277 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 278 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 279 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 280 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 281 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 282 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 284 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 285 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 286 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 287 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 288 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 289 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 290 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 291 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 292 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 293 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 294 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 295 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 296 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 297 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 298 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 299 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 301 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 302 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 303 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 304 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 305 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 306 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 307 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 308 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 309 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 310 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 311 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 312 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 313 MLX5_CMD_OP_MAX 314 }; 315 316 /* Valid range for general commands that don't work over an object */ 317 enum { 318 MLX5_CMD_OP_GENERAL_START = 0xb00, 319 MLX5_CMD_OP_GENERAL_END = 0xd00, 320 }; 321 322 enum { 323 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 324 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 325 }; 326 327 enum { 328 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 329 }; 330 331 struct mlx5_ifc_flow_table_fields_supported_bits { 332 u8 outer_dmac[0x1]; 333 u8 outer_smac[0x1]; 334 u8 outer_ether_type[0x1]; 335 u8 outer_ip_version[0x1]; 336 u8 outer_first_prio[0x1]; 337 u8 outer_first_cfi[0x1]; 338 u8 outer_first_vid[0x1]; 339 u8 outer_ipv4_ttl[0x1]; 340 u8 outer_second_prio[0x1]; 341 u8 outer_second_cfi[0x1]; 342 u8 outer_second_vid[0x1]; 343 u8 reserved_at_b[0x1]; 344 u8 outer_sip[0x1]; 345 u8 outer_dip[0x1]; 346 u8 outer_frag[0x1]; 347 u8 outer_ip_protocol[0x1]; 348 u8 outer_ip_ecn[0x1]; 349 u8 outer_ip_dscp[0x1]; 350 u8 outer_udp_sport[0x1]; 351 u8 outer_udp_dport[0x1]; 352 u8 outer_tcp_sport[0x1]; 353 u8 outer_tcp_dport[0x1]; 354 u8 outer_tcp_flags[0x1]; 355 u8 outer_gre_protocol[0x1]; 356 u8 outer_gre_key[0x1]; 357 u8 outer_vxlan_vni[0x1]; 358 u8 outer_geneve_vni[0x1]; 359 u8 outer_geneve_oam[0x1]; 360 u8 outer_geneve_protocol_type[0x1]; 361 u8 outer_geneve_opt_len[0x1]; 362 u8 source_vhca_port[0x1]; 363 u8 source_eswitch_port[0x1]; 364 365 u8 inner_dmac[0x1]; 366 u8 inner_smac[0x1]; 367 u8 inner_ether_type[0x1]; 368 u8 inner_ip_version[0x1]; 369 u8 inner_first_prio[0x1]; 370 u8 inner_first_cfi[0x1]; 371 u8 inner_first_vid[0x1]; 372 u8 reserved_at_27[0x1]; 373 u8 inner_second_prio[0x1]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0x1]; 376 u8 reserved_at_2b[0x1]; 377 u8 inner_sip[0x1]; 378 u8 inner_dip[0x1]; 379 u8 inner_frag[0x1]; 380 u8 inner_ip_protocol[0x1]; 381 u8 inner_ip_ecn[0x1]; 382 u8 inner_ip_dscp[0x1]; 383 u8 inner_udp_sport[0x1]; 384 u8 inner_udp_dport[0x1]; 385 u8 inner_tcp_sport[0x1]; 386 u8 inner_tcp_dport[0x1]; 387 u8 inner_tcp_flags[0x1]; 388 u8 reserved_at_37[0x9]; 389 390 u8 geneve_tlv_option_0_data[0x1]; 391 u8 geneve_tlv_option_0_exist[0x1]; 392 u8 reserved_at_42[0x3]; 393 u8 outer_first_mpls_over_udp[0x4]; 394 u8 outer_first_mpls_over_gre[0x4]; 395 u8 inner_first_mpls[0x4]; 396 u8 outer_first_mpls[0x4]; 397 u8 reserved_at_55[0x2]; 398 u8 outer_esp_spi[0x1]; 399 u8 reserved_at_58[0x2]; 400 u8 bth_dst_qp[0x1]; 401 u8 reserved_at_5b[0x5]; 402 403 u8 reserved_at_60[0x18]; 404 u8 metadata_reg_c_7[0x1]; 405 u8 metadata_reg_c_6[0x1]; 406 u8 metadata_reg_c_5[0x1]; 407 u8 metadata_reg_c_4[0x1]; 408 u8 metadata_reg_c_3[0x1]; 409 u8 metadata_reg_c_2[0x1]; 410 u8 metadata_reg_c_1[0x1]; 411 u8 metadata_reg_c_0[0x1]; 412 }; 413 414 /* Table 2170 - Flow Table Fields Supported 2 Format */ 415 struct mlx5_ifc_flow_table_fields_supported_2_bits { 416 u8 reserved_at_0[0xe]; 417 u8 bth_opcode[0x1]; 418 u8 reserved_at_f[0x1]; 419 u8 tunnel_header_0_1[0x1]; 420 u8 reserved_at_11[0xf]; 421 422 u8 reserved_at_20[0x60]; 423 }; 424 425 struct mlx5_ifc_flow_table_prop_layout_bits { 426 u8 ft_support[0x1]; 427 u8 reserved_at_1[0x1]; 428 u8 flow_counter[0x1]; 429 u8 flow_modify_en[0x1]; 430 u8 modify_root[0x1]; 431 u8 identified_miss_table_mode[0x1]; 432 u8 flow_table_modify[0x1]; 433 u8 reformat[0x1]; 434 u8 decap[0x1]; 435 u8 reserved_at_9[0x1]; 436 u8 pop_vlan[0x1]; 437 u8 push_vlan[0x1]; 438 u8 reserved_at_c[0x1]; 439 u8 pop_vlan_2[0x1]; 440 u8 push_vlan_2[0x1]; 441 u8 reformat_and_vlan_action[0x1]; 442 u8 reserved_at_10[0x1]; 443 u8 sw_owner[0x1]; 444 u8 reformat_l3_tunnel_to_l2[0x1]; 445 u8 reformat_l2_to_l3_tunnel[0x1]; 446 u8 reformat_and_modify_action[0x1]; 447 u8 ignore_flow_level[0x1]; 448 u8 reserved_at_16[0x1]; 449 u8 table_miss_action_domain[0x1]; 450 u8 termination_table[0x1]; 451 u8 reformat_and_fwd_to_table[0x1]; 452 u8 reserved_at_1a[0x2]; 453 u8 ipsec_encrypt[0x1]; 454 u8 ipsec_decrypt[0x1]; 455 u8 sw_owner_v2[0x1]; 456 u8 reserved_at_1f[0x1]; 457 458 u8 termination_table_raw_traffic[0x1]; 459 u8 reserved_at_21[0x1]; 460 u8 log_max_ft_size[0x6]; 461 u8 log_max_modify_header_context[0x8]; 462 u8 max_modify_header_actions[0x8]; 463 u8 max_ft_level[0x8]; 464 465 u8 reformat_add_esp_trasport[0x1]; 466 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 467 u8 reserved_at_42[0x1]; 468 u8 reformat_del_esp_trasport[0x1]; 469 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 470 u8 reserved_at_45[0x1]; 471 u8 execute_aso[0x1]; 472 u8 reserved_at_47[0x19]; 473 474 u8 reserved_at_60[0x2]; 475 u8 reformat_insert[0x1]; 476 u8 reformat_remove[0x1]; 477 u8 macsec_encrypt[0x1]; 478 u8 macsec_decrypt[0x1]; 479 u8 reserved_at_66[0x2]; 480 u8 reformat_add_macsec[0x1]; 481 u8 reformat_remove_macsec[0x1]; 482 u8 reserved_at_6a[0xe]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_at_6[0x1a]; 507 }; 508 509 struct mlx5_ifc_ipv4_layout_bits { 510 u8 reserved_at_0[0x60]; 511 512 u8 ipv4[0x20]; 513 }; 514 515 struct mlx5_ifc_ipv6_layout_bits { 516 u8 ipv6[16][0x8]; 517 }; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 520 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 521 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 522 u8 reserved_at_0[0x80]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 526 u8 smac_47_16[0x20]; 527 528 u8 smac_15_0[0x10]; 529 u8 ethertype[0x10]; 530 531 u8 dmac_47_16[0x20]; 532 533 u8 dmac_15_0[0x10]; 534 u8 first_prio[0x3]; 535 u8 first_cfi[0x1]; 536 u8 first_vid[0xc]; 537 538 u8 ip_protocol[0x8]; 539 u8 ip_dscp[0x6]; 540 u8 ip_ecn[0x2]; 541 u8 cvlan_tag[0x1]; 542 u8 svlan_tag[0x1]; 543 u8 frag[0x1]; 544 u8 ip_version[0x4]; 545 u8 tcp_flags[0x9]; 546 547 u8 tcp_sport[0x10]; 548 u8 tcp_dport[0x10]; 549 550 u8 reserved_at_c0[0x10]; 551 u8 ipv4_ihl[0x4]; 552 u8 reserved_at_c4[0x4]; 553 554 u8 ttl_hoplimit[0x8]; 555 556 u8 udp_sport[0x10]; 557 u8 udp_dport[0x10]; 558 559 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 560 561 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 562 }; 563 564 struct mlx5_ifc_nvgre_key_bits { 565 u8 hi[0x18]; 566 u8 lo[0x8]; 567 }; 568 569 union mlx5_ifc_gre_key_bits { 570 struct mlx5_ifc_nvgre_key_bits nvgre; 571 u8 key[0x20]; 572 }; 573 574 struct mlx5_ifc_fte_match_set_misc_bits { 575 u8 gre_c_present[0x1]; 576 u8 reserved_at_1[0x1]; 577 u8 gre_k_present[0x1]; 578 u8 gre_s_present[0x1]; 579 u8 source_vhca_port[0x4]; 580 u8 source_sqn[0x18]; 581 582 u8 source_eswitch_owner_vhca_id[0x10]; 583 u8 source_port[0x10]; 584 585 u8 outer_second_prio[0x3]; 586 u8 outer_second_cfi[0x1]; 587 u8 outer_second_vid[0xc]; 588 u8 inner_second_prio[0x3]; 589 u8 inner_second_cfi[0x1]; 590 u8 inner_second_vid[0xc]; 591 592 u8 outer_second_cvlan_tag[0x1]; 593 u8 inner_second_cvlan_tag[0x1]; 594 u8 outer_second_svlan_tag[0x1]; 595 u8 inner_second_svlan_tag[0x1]; 596 u8 reserved_at_64[0xc]; 597 u8 gre_protocol[0x10]; 598 599 union mlx5_ifc_gre_key_bits gre_key; 600 601 u8 vxlan_vni[0x18]; 602 u8 bth_opcode[0x8]; 603 604 u8 geneve_vni[0x18]; 605 u8 reserved_at_d8[0x6]; 606 u8 geneve_tlv_option_0_exist[0x1]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_at_e0[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_at_100[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_120[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_at_140[0x8]; 620 u8 bth_dst_qp[0x18]; 621 u8 reserved_at_160[0x20]; 622 u8 outer_esp_spi[0x20]; 623 u8 reserved_at_1a0[0x60]; 624 }; 625 626 struct mlx5_ifc_fte_match_mpls_bits { 627 u8 mpls_label[0x14]; 628 u8 mpls_exp[0x3]; 629 u8 mpls_s_bos[0x1]; 630 u8 mpls_ttl[0x8]; 631 }; 632 633 struct mlx5_ifc_fte_match_set_misc2_bits { 634 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 635 636 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 637 638 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 639 640 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 641 642 u8 metadata_reg_c_7[0x20]; 643 644 u8 metadata_reg_c_6[0x20]; 645 646 u8 metadata_reg_c_5[0x20]; 647 648 u8 metadata_reg_c_4[0x20]; 649 650 u8 metadata_reg_c_3[0x20]; 651 652 u8 metadata_reg_c_2[0x20]; 653 654 u8 metadata_reg_c_1[0x20]; 655 656 u8 metadata_reg_c_0[0x20]; 657 658 u8 metadata_reg_a[0x20]; 659 660 u8 reserved_at_1a0[0x8]; 661 662 u8 macsec_syndrome[0x8]; 663 u8 ipsec_syndrome[0x8]; 664 u8 reserved_at_1b8[0x8]; 665 666 u8 reserved_at_1c0[0x40]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc3_bits { 670 u8 inner_tcp_seq_num[0x20]; 671 672 u8 outer_tcp_seq_num[0x20]; 673 674 u8 inner_tcp_ack_num[0x20]; 675 676 u8 outer_tcp_ack_num[0x20]; 677 678 u8 reserved_at_80[0x8]; 679 u8 outer_vxlan_gpe_vni[0x18]; 680 681 u8 outer_vxlan_gpe_next_protocol[0x8]; 682 u8 outer_vxlan_gpe_flags[0x8]; 683 u8 reserved_at_b0[0x10]; 684 685 u8 icmp_header_data[0x20]; 686 687 u8 icmpv6_header_data[0x20]; 688 689 u8 icmp_type[0x8]; 690 u8 icmp_code[0x8]; 691 u8 icmpv6_type[0x8]; 692 u8 icmpv6_code[0x8]; 693 694 u8 geneve_tlv_option_0_data[0x20]; 695 696 u8 gtpu_teid[0x20]; 697 698 u8 gtpu_msg_type[0x8]; 699 u8 gtpu_msg_flags[0x8]; 700 u8 reserved_at_170[0x10]; 701 702 u8 gtpu_dw_2[0x20]; 703 704 u8 gtpu_first_ext_dw_0[0x20]; 705 706 u8 gtpu_dw_0[0x20]; 707 708 u8 reserved_at_1e0[0x20]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc4_bits { 712 u8 prog_sample_field_value_0[0x20]; 713 714 u8 prog_sample_field_id_0[0x20]; 715 716 u8 prog_sample_field_value_1[0x20]; 717 718 u8 prog_sample_field_id_1[0x20]; 719 720 u8 prog_sample_field_value_2[0x20]; 721 722 u8 prog_sample_field_id_2[0x20]; 723 724 u8 prog_sample_field_value_3[0x20]; 725 726 u8 prog_sample_field_id_3[0x20]; 727 728 u8 reserved_at_100[0x100]; 729 }; 730 731 struct mlx5_ifc_fte_match_set_misc5_bits { 732 u8 macsec_tag_0[0x20]; 733 734 u8 macsec_tag_1[0x20]; 735 736 u8 macsec_tag_2[0x20]; 737 738 u8 macsec_tag_3[0x20]; 739 740 u8 tunnel_header_0[0x20]; 741 742 u8 tunnel_header_1[0x20]; 743 744 u8 tunnel_header_2[0x20]; 745 746 u8 tunnel_header_3[0x20]; 747 748 u8 reserved_at_100[0x100]; 749 }; 750 751 struct mlx5_ifc_cmd_pas_bits { 752 u8 pa_h[0x20]; 753 754 u8 pa_l[0x14]; 755 u8 reserved_at_34[0xc]; 756 }; 757 758 struct mlx5_ifc_uint64_bits { 759 u8 hi[0x20]; 760 761 u8 lo[0x20]; 762 }; 763 764 enum { 765 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 766 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 767 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 768 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 769 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 770 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 771 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 772 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 773 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 774 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 775 }; 776 777 struct mlx5_ifc_ads_bits { 778 u8 fl[0x1]; 779 u8 free_ar[0x1]; 780 u8 reserved_at_2[0xe]; 781 u8 pkey_index[0x10]; 782 783 u8 reserved_at_20[0x8]; 784 u8 grh[0x1]; 785 u8 mlid[0x7]; 786 u8 rlid[0x10]; 787 788 u8 ack_timeout[0x5]; 789 u8 reserved_at_45[0x3]; 790 u8 src_addr_index[0x8]; 791 u8 reserved_at_50[0x4]; 792 u8 stat_rate[0x4]; 793 u8 hop_limit[0x8]; 794 795 u8 reserved_at_60[0x4]; 796 u8 tclass[0x8]; 797 u8 flow_label[0x14]; 798 799 u8 rgid_rip[16][0x8]; 800 801 u8 reserved_at_100[0x4]; 802 u8 f_dscp[0x1]; 803 u8 f_ecn[0x1]; 804 u8 reserved_at_106[0x1]; 805 u8 f_eth_prio[0x1]; 806 u8 ecn[0x2]; 807 u8 dscp[0x6]; 808 u8 udp_sport[0x10]; 809 810 u8 dei_cfi[0x1]; 811 u8 eth_prio[0x3]; 812 u8 sl[0x4]; 813 u8 vhca_port_num[0x8]; 814 u8 rmac_47_32[0x10]; 815 816 u8 rmac_31_0[0x20]; 817 }; 818 819 struct mlx5_ifc_flow_table_nic_cap_bits { 820 u8 nic_rx_multi_path_tirs[0x1]; 821 u8 nic_rx_multi_path_tirs_fts[0x1]; 822 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 823 u8 reserved_at_3[0x4]; 824 u8 sw_owner_reformat_supported[0x1]; 825 u8 reserved_at_8[0x18]; 826 827 u8 encap_general_header[0x1]; 828 u8 reserved_at_21[0xa]; 829 u8 log_max_packet_reformat_context[0x5]; 830 u8 reserved_at_30[0x6]; 831 u8 max_encap_header_size[0xa]; 832 u8 reserved_at_40[0x1c0]; 833 834 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 835 836 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 837 838 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 839 840 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 841 842 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 843 844 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 845 846 u8 reserved_at_e00[0x700]; 847 848 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 849 850 u8 reserved_at_1580[0x280]; 851 852 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 853 854 u8 reserved_at_1880[0x780]; 855 856 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 857 858 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 859 860 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 861 862 u8 reserved_at_20c0[0x5f40]; 863 }; 864 865 struct mlx5_ifc_port_selection_cap_bits { 866 u8 reserved_at_0[0x10]; 867 u8 port_select_flow_table[0x1]; 868 u8 reserved_at_11[0x1]; 869 u8 port_select_flow_table_bypass[0x1]; 870 u8 reserved_at_13[0xd]; 871 872 u8 reserved_at_20[0x1e0]; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 875 876 u8 reserved_at_400[0x7c00]; 877 }; 878 879 enum { 880 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 881 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 882 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 883 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 884 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 885 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 886 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 887 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 888 }; 889 890 struct mlx5_ifc_flow_table_eswitch_cap_bits { 891 u8 fdb_to_vport_reg_c_id[0x8]; 892 u8 reserved_at_8[0x5]; 893 u8 fdb_uplink_hairpin[0x1]; 894 u8 fdb_multi_path_any_table_limit_regc[0x1]; 895 u8 reserved_at_f[0x3]; 896 u8 fdb_multi_path_any_table[0x1]; 897 u8 reserved_at_13[0x2]; 898 u8 fdb_modify_header_fwd_to_table[0x1]; 899 u8 fdb_ipv4_ttl_modify[0x1]; 900 u8 flow_source[0x1]; 901 u8 reserved_at_18[0x2]; 902 u8 multi_fdb_encap[0x1]; 903 u8 egress_acl_forward_to_vport[0x1]; 904 u8 fdb_multi_path_to_table[0x1]; 905 u8 reserved_at_1d[0x3]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 910 911 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 912 913 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 914 915 u8 reserved_at_800[0xC00]; 916 917 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 918 919 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 920 921 u8 reserved_at_1500[0x300]; 922 923 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 924 925 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 926 927 u8 sw_steering_uplink_icm_address_rx[0x40]; 928 929 u8 sw_steering_uplink_icm_address_tx[0x40]; 930 931 u8 reserved_at_1900[0x6700]; 932 }; 933 934 enum { 935 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 936 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 937 }; 938 939 struct mlx5_ifc_e_switch_cap_bits { 940 u8 vport_svlan_strip[0x1]; 941 u8 vport_cvlan_strip[0x1]; 942 u8 vport_svlan_insert[0x1]; 943 u8 vport_cvlan_insert_if_not_exist[0x1]; 944 u8 vport_cvlan_insert_overwrite[0x1]; 945 u8 reserved_at_5[0x1]; 946 u8 vport_cvlan_insert_always[0x1]; 947 u8 esw_shared_ingress_acl[0x1]; 948 u8 esw_uplink_ingress_acl[0x1]; 949 u8 root_ft_on_other_esw[0x1]; 950 u8 reserved_at_a[0xf]; 951 u8 esw_functions_changed[0x1]; 952 u8 reserved_at_1a[0x1]; 953 u8 ecpf_vport_exists[0x1]; 954 u8 counter_eswitch_affinity[0x1]; 955 u8 merged_eswitch[0x1]; 956 u8 nic_vport_node_guid_modify[0x1]; 957 u8 nic_vport_port_guid_modify[0x1]; 958 959 u8 vxlan_encap_decap[0x1]; 960 u8 nvgre_encap_decap[0x1]; 961 u8 reserved_at_22[0x1]; 962 u8 log_max_fdb_encap_uplink[0x5]; 963 u8 reserved_at_21[0x3]; 964 u8 log_max_packet_reformat_context[0x5]; 965 u8 reserved_2b[0x6]; 966 u8 max_encap_header_size[0xa]; 967 968 u8 reserved_at_40[0xb]; 969 u8 log_max_esw_sf[0x5]; 970 u8 esw_sf_base_id[0x10]; 971 972 u8 reserved_at_60[0x7a0]; 973 974 }; 975 976 struct mlx5_ifc_qos_cap_bits { 977 u8 packet_pacing[0x1]; 978 u8 esw_scheduling[0x1]; 979 u8 esw_bw_share[0x1]; 980 u8 esw_rate_limit[0x1]; 981 u8 reserved_at_4[0x1]; 982 u8 packet_pacing_burst_bound[0x1]; 983 u8 packet_pacing_typical_size[0x1]; 984 u8 reserved_at_7[0x1]; 985 u8 nic_sq_scheduling[0x1]; 986 u8 nic_bw_share[0x1]; 987 u8 nic_rate_limit[0x1]; 988 u8 packet_pacing_uid[0x1]; 989 u8 log_esw_max_sched_depth[0x4]; 990 u8 reserved_at_10[0x10]; 991 992 u8 reserved_at_20[0xb]; 993 u8 log_max_qos_nic_queue_group[0x5]; 994 u8 reserved_at_30[0x10]; 995 996 u8 packet_pacing_max_rate[0x20]; 997 998 u8 packet_pacing_min_rate[0x20]; 999 1000 u8 reserved_at_80[0x10]; 1001 u8 packet_pacing_rate_table_size[0x10]; 1002 1003 u8 esw_element_type[0x10]; 1004 u8 esw_tsar_type[0x10]; 1005 1006 u8 reserved_at_c0[0x10]; 1007 u8 max_qos_para_vport[0x10]; 1008 1009 u8 max_tsar_bw_share[0x20]; 1010 1011 u8 reserved_at_100[0x20]; 1012 1013 u8 reserved_at_120[0x3]; 1014 u8 log_meter_aso_granularity[0x5]; 1015 u8 reserved_at_128[0x3]; 1016 u8 log_meter_aso_max_alloc[0x5]; 1017 u8 reserved_at_130[0x3]; 1018 u8 log_max_num_meter_aso[0x5]; 1019 u8 reserved_at_138[0x8]; 1020 1021 u8 reserved_at_140[0x6c0]; 1022 }; 1023 1024 struct mlx5_ifc_debug_cap_bits { 1025 u8 core_dump_general[0x1]; 1026 u8 core_dump_qp[0x1]; 1027 u8 reserved_at_2[0x7]; 1028 u8 resource_dump[0x1]; 1029 u8 reserved_at_a[0x16]; 1030 1031 u8 reserved_at_20[0x2]; 1032 u8 stall_detect[0x1]; 1033 u8 reserved_at_23[0x1d]; 1034 1035 u8 reserved_at_40[0x7c0]; 1036 }; 1037 1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1039 u8 csum_cap[0x1]; 1040 u8 vlan_cap[0x1]; 1041 u8 lro_cap[0x1]; 1042 u8 lro_psh_flag[0x1]; 1043 u8 lro_time_stamp[0x1]; 1044 u8 reserved_at_5[0x2]; 1045 u8 wqe_vlan_insert[0x1]; 1046 u8 self_lb_en_modifiable[0x1]; 1047 u8 reserved_at_9[0x2]; 1048 u8 max_lso_cap[0x5]; 1049 u8 multi_pkt_send_wqe[0x2]; 1050 u8 wqe_inline_mode[0x2]; 1051 u8 rss_ind_tbl_cap[0x4]; 1052 u8 reg_umr_sq[0x1]; 1053 u8 scatter_fcs[0x1]; 1054 u8 enhanced_multi_pkt_send_wqe[0x1]; 1055 u8 tunnel_lso_const_out_ip_id[0x1]; 1056 u8 tunnel_lro_gre[0x1]; 1057 u8 tunnel_lro_vxlan[0x1]; 1058 u8 tunnel_stateless_gre[0x1]; 1059 u8 tunnel_stateless_vxlan[0x1]; 1060 1061 u8 swp[0x1]; 1062 u8 swp_csum[0x1]; 1063 u8 swp_lso[0x1]; 1064 u8 cqe_checksum_full[0x1]; 1065 u8 tunnel_stateless_geneve_tx[0x1]; 1066 u8 tunnel_stateless_mpls_over_udp[0x1]; 1067 u8 tunnel_stateless_mpls_over_gre[0x1]; 1068 u8 tunnel_stateless_vxlan_gpe[0x1]; 1069 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1070 u8 tunnel_stateless_ip_over_ip[0x1]; 1071 u8 insert_trailer[0x1]; 1072 u8 reserved_at_2b[0x1]; 1073 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1074 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1075 u8 reserved_at_2e[0x2]; 1076 u8 max_vxlan_udp_ports[0x8]; 1077 u8 reserved_at_38[0x6]; 1078 u8 max_geneve_opt_len[0x1]; 1079 u8 tunnel_stateless_geneve_rx[0x1]; 1080 1081 u8 reserved_at_40[0x10]; 1082 u8 lro_min_mss_size[0x10]; 1083 1084 u8 reserved_at_60[0x120]; 1085 1086 u8 lro_timer_supported_periods[4][0x20]; 1087 1088 u8 reserved_at_200[0x600]; 1089 }; 1090 1091 enum { 1092 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1093 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1094 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1095 }; 1096 1097 struct mlx5_ifc_roce_cap_bits { 1098 u8 roce_apm[0x1]; 1099 u8 reserved_at_1[0x3]; 1100 u8 sw_r_roce_src_udp_port[0x1]; 1101 u8 fl_rc_qp_when_roce_disabled[0x1]; 1102 u8 fl_rc_qp_when_roce_enabled[0x1]; 1103 u8 reserved_at_7[0x1]; 1104 u8 qp_ooo_transmit_default[0x1]; 1105 u8 reserved_at_9[0x15]; 1106 u8 qp_ts_format[0x2]; 1107 1108 u8 reserved_at_20[0x60]; 1109 1110 u8 reserved_at_80[0xc]; 1111 u8 l3_type[0x4]; 1112 u8 reserved_at_90[0x8]; 1113 u8 roce_version[0x8]; 1114 1115 u8 reserved_at_a0[0x10]; 1116 u8 r_roce_dest_udp_port[0x10]; 1117 1118 u8 r_roce_max_src_udp_port[0x10]; 1119 u8 r_roce_min_src_udp_port[0x10]; 1120 1121 u8 reserved_at_e0[0x10]; 1122 u8 roce_address_table_size[0x10]; 1123 1124 u8 reserved_at_100[0x700]; 1125 }; 1126 1127 struct mlx5_ifc_sync_steering_in_bits { 1128 u8 opcode[0x10]; 1129 u8 uid[0x10]; 1130 1131 u8 reserved_at_20[0x10]; 1132 u8 op_mod[0x10]; 1133 1134 u8 reserved_at_40[0xc0]; 1135 }; 1136 1137 struct mlx5_ifc_sync_steering_out_bits { 1138 u8 status[0x8]; 1139 u8 reserved_at_8[0x18]; 1140 1141 u8 syndrome[0x20]; 1142 1143 u8 reserved_at_40[0x40]; 1144 }; 1145 1146 struct mlx5_ifc_sync_crypto_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0x20]; 1154 1155 u8 reserved_at_60[0x10]; 1156 u8 crypto_type[0x10]; 1157 1158 u8 reserved_at_80[0x80]; 1159 }; 1160 1161 struct mlx5_ifc_sync_crypto_out_bits { 1162 u8 status[0x8]; 1163 u8 reserved_at_8[0x18]; 1164 1165 u8 syndrome[0x20]; 1166 1167 u8 reserved_at_40[0x40]; 1168 }; 1169 1170 struct mlx5_ifc_device_mem_cap_bits { 1171 u8 memic[0x1]; 1172 u8 reserved_at_1[0x1f]; 1173 1174 u8 reserved_at_20[0xb]; 1175 u8 log_min_memic_alloc_size[0x5]; 1176 u8 reserved_at_30[0x8]; 1177 u8 log_max_memic_addr_alignment[0x8]; 1178 1179 u8 memic_bar_start_addr[0x40]; 1180 1181 u8 memic_bar_size[0x20]; 1182 1183 u8 max_memic_size[0x20]; 1184 1185 u8 steering_sw_icm_start_address[0x40]; 1186 1187 u8 reserved_at_100[0x8]; 1188 u8 log_header_modify_sw_icm_size[0x8]; 1189 u8 reserved_at_110[0x2]; 1190 u8 log_sw_icm_alloc_granularity[0x6]; 1191 u8 log_steering_sw_icm_size[0x8]; 1192 1193 u8 reserved_at_120[0x18]; 1194 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1195 1196 u8 header_modify_sw_icm_start_address[0x40]; 1197 1198 u8 reserved_at_180[0x40]; 1199 1200 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1201 1202 u8 memic_operations[0x20]; 1203 1204 u8 reserved_at_220[0x5e0]; 1205 }; 1206 1207 struct mlx5_ifc_device_event_cap_bits { 1208 u8 user_affiliated_events[4][0x40]; 1209 1210 u8 user_unaffiliated_events[4][0x40]; 1211 }; 1212 1213 struct mlx5_ifc_virtio_emulation_cap_bits { 1214 u8 desc_tunnel_offload_type[0x1]; 1215 u8 eth_frame_offload_type[0x1]; 1216 u8 virtio_version_1_0[0x1]; 1217 u8 device_features_bits_mask[0xd]; 1218 u8 event_mode[0x8]; 1219 u8 virtio_queue_type[0x8]; 1220 1221 u8 max_tunnel_desc[0x10]; 1222 u8 reserved_at_30[0x3]; 1223 u8 log_doorbell_stride[0x5]; 1224 u8 reserved_at_38[0x3]; 1225 u8 log_doorbell_bar_size[0x5]; 1226 1227 u8 doorbell_bar_offset[0x40]; 1228 1229 u8 max_emulated_devices[0x8]; 1230 u8 max_num_virtio_queues[0x18]; 1231 1232 u8 reserved_at_a0[0x60]; 1233 1234 u8 umem_1_buffer_param_a[0x20]; 1235 1236 u8 umem_1_buffer_param_b[0x20]; 1237 1238 u8 umem_2_buffer_param_a[0x20]; 1239 1240 u8 umem_2_buffer_param_b[0x20]; 1241 1242 u8 umem_3_buffer_param_a[0x20]; 1243 1244 u8 umem_3_buffer_param_b[0x20]; 1245 1246 u8 reserved_at_1c0[0x640]; 1247 }; 1248 1249 enum { 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1257 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1258 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1259 }; 1260 1261 enum { 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1271 }; 1272 1273 struct mlx5_ifc_atomic_caps_bits { 1274 u8 reserved_at_0[0x40]; 1275 1276 u8 atomic_req_8B_endianness_mode[0x2]; 1277 u8 reserved_at_42[0x4]; 1278 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1279 1280 u8 reserved_at_47[0x19]; 1281 1282 u8 reserved_at_60[0x20]; 1283 1284 u8 reserved_at_80[0x10]; 1285 u8 atomic_operations[0x10]; 1286 1287 u8 reserved_at_a0[0x10]; 1288 u8 atomic_size_qp[0x10]; 1289 1290 u8 reserved_at_c0[0x10]; 1291 u8 atomic_size_dc[0x10]; 1292 1293 u8 reserved_at_e0[0x720]; 1294 }; 1295 1296 struct mlx5_ifc_odp_cap_bits { 1297 u8 reserved_at_0[0x40]; 1298 1299 u8 sig[0x1]; 1300 u8 reserved_at_41[0x1f]; 1301 1302 u8 reserved_at_60[0x20]; 1303 1304 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1305 1306 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1307 1308 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1309 1310 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1311 1312 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1313 1314 u8 reserved_at_120[0x6E0]; 1315 }; 1316 1317 struct mlx5_ifc_calc_op { 1318 u8 reserved_at_0[0x10]; 1319 u8 reserved_at_10[0x9]; 1320 u8 op_swap_endianness[0x1]; 1321 u8 op_min[0x1]; 1322 u8 op_xor[0x1]; 1323 u8 op_or[0x1]; 1324 u8 op_and[0x1]; 1325 u8 op_max[0x1]; 1326 u8 op_add[0x1]; 1327 }; 1328 1329 struct mlx5_ifc_vector_calc_cap_bits { 1330 u8 calc_matrix[0x1]; 1331 u8 reserved_at_1[0x1f]; 1332 u8 reserved_at_20[0x8]; 1333 u8 max_vec_count[0x8]; 1334 u8 reserved_at_30[0xd]; 1335 u8 max_chunk_size[0x3]; 1336 struct mlx5_ifc_calc_op calc0; 1337 struct mlx5_ifc_calc_op calc1; 1338 struct mlx5_ifc_calc_op calc2; 1339 struct mlx5_ifc_calc_op calc3; 1340 1341 u8 reserved_at_c0[0x720]; 1342 }; 1343 1344 struct mlx5_ifc_tls_cap_bits { 1345 u8 tls_1_2_aes_gcm_128[0x1]; 1346 u8 tls_1_3_aes_gcm_128[0x1]; 1347 u8 tls_1_2_aes_gcm_256[0x1]; 1348 u8 tls_1_3_aes_gcm_256[0x1]; 1349 u8 reserved_at_4[0x1c]; 1350 1351 u8 reserved_at_20[0x7e0]; 1352 }; 1353 1354 struct mlx5_ifc_ipsec_cap_bits { 1355 u8 ipsec_full_offload[0x1]; 1356 u8 ipsec_crypto_offload[0x1]; 1357 u8 ipsec_esn[0x1]; 1358 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1359 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1360 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1361 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1362 u8 reserved_at_7[0x4]; 1363 u8 log_max_ipsec_offload[0x5]; 1364 u8 reserved_at_10[0x10]; 1365 1366 u8 min_log_ipsec_full_replay_window[0x8]; 1367 u8 max_log_ipsec_full_replay_window[0x8]; 1368 u8 reserved_at_30[0x7d0]; 1369 }; 1370 1371 struct mlx5_ifc_macsec_cap_bits { 1372 u8 macsec_epn[0x1]; 1373 u8 reserved_at_1[0x2]; 1374 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1375 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1376 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1377 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1378 u8 reserved_at_7[0x4]; 1379 u8 log_max_macsec_offload[0x5]; 1380 u8 reserved_at_10[0x10]; 1381 1382 u8 min_log_macsec_full_replay_window[0x8]; 1383 u8 max_log_macsec_full_replay_window[0x8]; 1384 u8 reserved_at_30[0x10]; 1385 1386 u8 reserved_at_40[0x7c0]; 1387 }; 1388 1389 enum { 1390 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1391 MLX5_WQ_TYPE_CYCLIC = 0x1, 1392 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1393 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1394 }; 1395 1396 enum { 1397 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1398 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1399 }; 1400 1401 enum { 1402 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1403 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1404 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1405 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1407 }; 1408 1409 enum { 1410 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1411 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1412 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1413 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1416 }; 1417 1418 enum { 1419 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1420 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1425 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1426 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1427 }; 1428 1429 enum { 1430 MLX5_CAP_PORT_TYPE_IB = 0x0, 1431 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1436 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1437 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1438 }; 1439 1440 enum { 1441 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1442 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1443 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1444 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1445 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1446 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1447 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1448 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1449 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1450 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1451 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1452 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1453 }; 1454 1455 enum { 1456 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1457 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1458 }; 1459 1460 #define MLX5_FC_BULK_SIZE_FACTOR 128 1461 1462 enum mlx5_fc_bulk_alloc_bitmask { 1463 MLX5_FC_BULK_128 = (1 << 0), 1464 MLX5_FC_BULK_256 = (1 << 1), 1465 MLX5_FC_BULK_512 = (1 << 2), 1466 MLX5_FC_BULK_1024 = (1 << 3), 1467 MLX5_FC_BULK_2048 = (1 << 4), 1468 MLX5_FC_BULK_4096 = (1 << 5), 1469 MLX5_FC_BULK_8192 = (1 << 6), 1470 MLX5_FC_BULK_16384 = (1 << 7), 1471 }; 1472 1473 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1474 1475 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1476 1477 enum { 1478 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1479 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1480 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1481 }; 1482 1483 struct mlx5_ifc_cmd_hca_cap_bits { 1484 u8 reserved_at_0[0x10]; 1485 u8 shared_object_to_user_object_allowed[0x1]; 1486 u8 reserved_at_13[0xe]; 1487 u8 vhca_resource_manager[0x1]; 1488 1489 u8 hca_cap_2[0x1]; 1490 u8 create_lag_when_not_master_up[0x1]; 1491 u8 dtor[0x1]; 1492 u8 event_on_vhca_state_teardown_request[0x1]; 1493 u8 event_on_vhca_state_in_use[0x1]; 1494 u8 event_on_vhca_state_active[0x1]; 1495 u8 event_on_vhca_state_allocated[0x1]; 1496 u8 event_on_vhca_state_invalid[0x1]; 1497 u8 reserved_at_28[0x8]; 1498 u8 vhca_id[0x10]; 1499 1500 u8 reserved_at_40[0x40]; 1501 1502 u8 log_max_srq_sz[0x8]; 1503 u8 log_max_qp_sz[0x8]; 1504 u8 event_cap[0x1]; 1505 u8 reserved_at_91[0x2]; 1506 u8 isolate_vl_tc_new[0x1]; 1507 u8 reserved_at_94[0x4]; 1508 u8 prio_tag_required[0x1]; 1509 u8 reserved_at_99[0x2]; 1510 u8 log_max_qp[0x5]; 1511 1512 u8 reserved_at_a0[0x3]; 1513 u8 ece_support[0x1]; 1514 u8 reserved_at_a4[0x5]; 1515 u8 reg_c_preserve[0x1]; 1516 u8 reserved_at_aa[0x1]; 1517 u8 log_max_srq[0x5]; 1518 u8 reserved_at_b0[0x1]; 1519 u8 uplink_follow[0x1]; 1520 u8 ts_cqe_to_dest_cqn[0x1]; 1521 u8 reserved_at_b3[0x6]; 1522 u8 go_back_n[0x1]; 1523 u8 shampo[0x1]; 1524 u8 reserved_at_bb[0x5]; 1525 1526 u8 max_sgl_for_optimized_performance[0x8]; 1527 u8 log_max_cq_sz[0x8]; 1528 u8 relaxed_ordering_write_umr[0x1]; 1529 u8 relaxed_ordering_read_umr[0x1]; 1530 u8 reserved_at_d2[0x7]; 1531 u8 virtio_net_device_emualtion_manager[0x1]; 1532 u8 virtio_blk_device_emualtion_manager[0x1]; 1533 u8 log_max_cq[0x5]; 1534 1535 u8 log_max_eq_sz[0x8]; 1536 u8 relaxed_ordering_write[0x1]; 1537 u8 relaxed_ordering_read_pci_enabled[0x1]; 1538 u8 log_max_mkey[0x6]; 1539 u8 reserved_at_f0[0x6]; 1540 u8 terminate_scatter_list_mkey[0x1]; 1541 u8 repeated_mkey[0x1]; 1542 u8 dump_fill_mkey[0x1]; 1543 u8 reserved_at_f9[0x2]; 1544 u8 fast_teardown[0x1]; 1545 u8 log_max_eq[0x4]; 1546 1547 u8 max_indirection[0x8]; 1548 u8 fixed_buffer_size[0x1]; 1549 u8 log_max_mrw_sz[0x7]; 1550 u8 force_teardown[0x1]; 1551 u8 reserved_at_111[0x1]; 1552 u8 log_max_bsf_list_size[0x6]; 1553 u8 umr_extended_translation_offset[0x1]; 1554 u8 null_mkey[0x1]; 1555 u8 log_max_klm_list_size[0x6]; 1556 1557 u8 reserved_at_120[0x2]; 1558 u8 qpc_extension[0x1]; 1559 u8 reserved_at_123[0x7]; 1560 u8 log_max_ra_req_dc[0x6]; 1561 u8 reserved_at_130[0x2]; 1562 u8 eth_wqe_too_small[0x1]; 1563 u8 reserved_at_133[0x6]; 1564 u8 vnic_env_cq_overrun[0x1]; 1565 u8 log_max_ra_res_dc[0x6]; 1566 1567 u8 reserved_at_140[0x5]; 1568 u8 release_all_pages[0x1]; 1569 u8 must_not_use[0x1]; 1570 u8 reserved_at_147[0x2]; 1571 u8 roce_accl[0x1]; 1572 u8 log_max_ra_req_qp[0x6]; 1573 u8 reserved_at_150[0xa]; 1574 u8 log_max_ra_res_qp[0x6]; 1575 1576 u8 end_pad[0x1]; 1577 u8 cc_query_allowed[0x1]; 1578 u8 cc_modify_allowed[0x1]; 1579 u8 start_pad[0x1]; 1580 u8 cache_line_128byte[0x1]; 1581 u8 reserved_at_165[0x4]; 1582 u8 rts2rts_qp_counters_set_id[0x1]; 1583 u8 reserved_at_16a[0x2]; 1584 u8 vnic_env_int_rq_oob[0x1]; 1585 u8 sbcam_reg[0x1]; 1586 u8 reserved_at_16e[0x1]; 1587 u8 qcam_reg[0x1]; 1588 u8 gid_table_size[0x10]; 1589 1590 u8 out_of_seq_cnt[0x1]; 1591 u8 vport_counters[0x1]; 1592 u8 retransmission_q_counters[0x1]; 1593 u8 debug[0x1]; 1594 u8 modify_rq_counter_set_id[0x1]; 1595 u8 rq_delay_drop[0x1]; 1596 u8 max_qp_cnt[0xa]; 1597 u8 pkey_table_size[0x10]; 1598 1599 u8 vport_group_manager[0x1]; 1600 u8 vhca_group_manager[0x1]; 1601 u8 ib_virt[0x1]; 1602 u8 eth_virt[0x1]; 1603 u8 vnic_env_queue_counters[0x1]; 1604 u8 ets[0x1]; 1605 u8 nic_flow_table[0x1]; 1606 u8 eswitch_manager[0x1]; 1607 u8 device_memory[0x1]; 1608 u8 mcam_reg[0x1]; 1609 u8 pcam_reg[0x1]; 1610 u8 local_ca_ack_delay[0x5]; 1611 u8 port_module_event[0x1]; 1612 u8 enhanced_error_q_counters[0x1]; 1613 u8 ports_check[0x1]; 1614 u8 reserved_at_1b3[0x1]; 1615 u8 disable_link_up[0x1]; 1616 u8 beacon_led[0x1]; 1617 u8 port_type[0x2]; 1618 u8 num_ports[0x8]; 1619 1620 u8 reserved_at_1c0[0x1]; 1621 u8 pps[0x1]; 1622 u8 pps_modify[0x1]; 1623 u8 log_max_msg[0x5]; 1624 u8 reserved_at_1c8[0x4]; 1625 u8 max_tc[0x4]; 1626 u8 temp_warn_event[0x1]; 1627 u8 dcbx[0x1]; 1628 u8 general_notification_event[0x1]; 1629 u8 reserved_at_1d3[0x2]; 1630 u8 fpga[0x1]; 1631 u8 rol_s[0x1]; 1632 u8 rol_g[0x1]; 1633 u8 reserved_at_1d8[0x1]; 1634 u8 wol_s[0x1]; 1635 u8 wol_g[0x1]; 1636 u8 wol_a[0x1]; 1637 u8 wol_b[0x1]; 1638 u8 wol_m[0x1]; 1639 u8 wol_u[0x1]; 1640 u8 wol_p[0x1]; 1641 1642 u8 stat_rate_support[0x10]; 1643 u8 reserved_at_1f0[0x1]; 1644 u8 pci_sync_for_fw_update_event[0x1]; 1645 u8 reserved_at_1f2[0x6]; 1646 u8 init2_lag_tx_port_affinity[0x1]; 1647 u8 reserved_at_1fa[0x3]; 1648 u8 cqe_version[0x4]; 1649 1650 u8 compact_address_vector[0x1]; 1651 u8 striding_rq[0x1]; 1652 u8 reserved_at_202[0x1]; 1653 u8 ipoib_enhanced_offloads[0x1]; 1654 u8 ipoib_basic_offloads[0x1]; 1655 u8 reserved_at_205[0x1]; 1656 u8 repeated_block_disabled[0x1]; 1657 u8 umr_modify_entity_size_disabled[0x1]; 1658 u8 umr_modify_atomic_disabled[0x1]; 1659 u8 umr_indirect_mkey_disabled[0x1]; 1660 u8 umr_fence[0x2]; 1661 u8 dc_req_scat_data_cqe[0x1]; 1662 u8 reserved_at_20d[0x2]; 1663 u8 drain_sigerr[0x1]; 1664 u8 cmdif_checksum[0x2]; 1665 u8 sigerr_cqe[0x1]; 1666 u8 reserved_at_213[0x1]; 1667 u8 wq_signature[0x1]; 1668 u8 sctr_data_cqe[0x1]; 1669 u8 reserved_at_216[0x1]; 1670 u8 sho[0x1]; 1671 u8 tph[0x1]; 1672 u8 rf[0x1]; 1673 u8 dct[0x1]; 1674 u8 qos[0x1]; 1675 u8 eth_net_offloads[0x1]; 1676 u8 roce[0x1]; 1677 u8 atomic[0x1]; 1678 u8 reserved_at_21f[0x1]; 1679 1680 u8 cq_oi[0x1]; 1681 u8 cq_resize[0x1]; 1682 u8 cq_moderation[0x1]; 1683 u8 reserved_at_223[0x3]; 1684 u8 cq_eq_remap[0x1]; 1685 u8 pg[0x1]; 1686 u8 block_lb_mc[0x1]; 1687 u8 reserved_at_229[0x1]; 1688 u8 scqe_break_moderation[0x1]; 1689 u8 cq_period_start_from_cqe[0x1]; 1690 u8 cd[0x1]; 1691 u8 reserved_at_22d[0x1]; 1692 u8 apm[0x1]; 1693 u8 vector_calc[0x1]; 1694 u8 umr_ptr_rlky[0x1]; 1695 u8 imaicl[0x1]; 1696 u8 qp_packet_based[0x1]; 1697 u8 reserved_at_233[0x3]; 1698 u8 qkv[0x1]; 1699 u8 pkv[0x1]; 1700 u8 set_deth_sqpn[0x1]; 1701 u8 reserved_at_239[0x3]; 1702 u8 xrc[0x1]; 1703 u8 ud[0x1]; 1704 u8 uc[0x1]; 1705 u8 rc[0x1]; 1706 1707 u8 uar_4k[0x1]; 1708 u8 reserved_at_241[0x7]; 1709 u8 fl_rc_qp_when_roce_disabled[0x1]; 1710 u8 regexp_params[0x1]; 1711 u8 uar_sz[0x6]; 1712 u8 port_selection_cap[0x1]; 1713 u8 reserved_at_248[0x1]; 1714 u8 umem_uid_0[0x1]; 1715 u8 reserved_at_250[0x5]; 1716 u8 log_pg_sz[0x8]; 1717 1718 u8 bf[0x1]; 1719 u8 driver_version[0x1]; 1720 u8 pad_tx_eth_packet[0x1]; 1721 u8 reserved_at_263[0x3]; 1722 u8 mkey_by_name[0x1]; 1723 u8 reserved_at_267[0x4]; 1724 1725 u8 log_bf_reg_size[0x5]; 1726 1727 u8 reserved_at_270[0x3]; 1728 u8 qp_error_syndrome[0x1]; 1729 u8 reserved_at_274[0x2]; 1730 u8 lag_dct[0x2]; 1731 u8 lag_tx_port_affinity[0x1]; 1732 u8 lag_native_fdb_selection[0x1]; 1733 u8 reserved_at_27a[0x1]; 1734 u8 lag_master[0x1]; 1735 u8 num_lag_ports[0x4]; 1736 1737 u8 reserved_at_280[0x10]; 1738 u8 max_wqe_sz_sq[0x10]; 1739 1740 u8 reserved_at_2a0[0x10]; 1741 u8 max_wqe_sz_rq[0x10]; 1742 1743 u8 max_flow_counter_31_16[0x10]; 1744 u8 max_wqe_sz_sq_dc[0x10]; 1745 1746 u8 reserved_at_2e0[0x7]; 1747 u8 max_qp_mcg[0x19]; 1748 1749 u8 reserved_at_300[0x10]; 1750 u8 flow_counter_bulk_alloc[0x8]; 1751 u8 log_max_mcg[0x8]; 1752 1753 u8 reserved_at_320[0x3]; 1754 u8 log_max_transport_domain[0x5]; 1755 u8 reserved_at_328[0x2]; 1756 u8 relaxed_ordering_read[0x1]; 1757 u8 log_max_pd[0x5]; 1758 u8 reserved_at_330[0x7]; 1759 u8 vnic_env_cnt_steering_fail[0x1]; 1760 u8 reserved_at_338[0x1]; 1761 u8 q_counter_aggregation[0x1]; 1762 u8 q_counter_other_vport[0x1]; 1763 u8 log_max_xrcd[0x5]; 1764 1765 u8 nic_receive_steering_discard[0x1]; 1766 u8 receive_discard_vport_down[0x1]; 1767 u8 transmit_discard_vport_down[0x1]; 1768 u8 eq_overrun_count[0x1]; 1769 u8 reserved_at_344[0x1]; 1770 u8 invalid_command_count[0x1]; 1771 u8 quota_exceeded_count[0x1]; 1772 u8 reserved_at_347[0x1]; 1773 u8 log_max_flow_counter_bulk[0x8]; 1774 u8 max_flow_counter_15_0[0x10]; 1775 1776 1777 u8 reserved_at_360[0x3]; 1778 u8 log_max_rq[0x5]; 1779 u8 reserved_at_368[0x3]; 1780 u8 log_max_sq[0x5]; 1781 u8 reserved_at_370[0x3]; 1782 u8 log_max_tir[0x5]; 1783 u8 reserved_at_378[0x3]; 1784 u8 log_max_tis[0x5]; 1785 1786 u8 basic_cyclic_rcv_wqe[0x1]; 1787 u8 reserved_at_381[0x2]; 1788 u8 log_max_rmp[0x5]; 1789 u8 reserved_at_388[0x3]; 1790 u8 log_max_rqt[0x5]; 1791 u8 reserved_at_390[0x3]; 1792 u8 log_max_rqt_size[0x5]; 1793 u8 reserved_at_398[0x3]; 1794 u8 log_max_tis_per_sq[0x5]; 1795 1796 u8 ext_stride_num_range[0x1]; 1797 u8 roce_rw_supported[0x1]; 1798 u8 log_max_current_uc_list_wr_supported[0x1]; 1799 u8 log_max_stride_sz_rq[0x5]; 1800 u8 reserved_at_3a8[0x3]; 1801 u8 log_min_stride_sz_rq[0x5]; 1802 u8 reserved_at_3b0[0x3]; 1803 u8 log_max_stride_sz_sq[0x5]; 1804 u8 reserved_at_3b8[0x3]; 1805 u8 log_min_stride_sz_sq[0x5]; 1806 1807 u8 hairpin[0x1]; 1808 u8 reserved_at_3c1[0x2]; 1809 u8 log_max_hairpin_queues[0x5]; 1810 u8 reserved_at_3c8[0x3]; 1811 u8 log_max_hairpin_wq_data_sz[0x5]; 1812 u8 reserved_at_3d0[0x3]; 1813 u8 log_max_hairpin_num_packets[0x5]; 1814 u8 reserved_at_3d8[0x3]; 1815 u8 log_max_wq_sz[0x5]; 1816 1817 u8 nic_vport_change_event[0x1]; 1818 u8 disable_local_lb_uc[0x1]; 1819 u8 disable_local_lb_mc[0x1]; 1820 u8 log_min_hairpin_wq_data_sz[0x5]; 1821 u8 reserved_at_3e8[0x2]; 1822 u8 vhca_state[0x1]; 1823 u8 log_max_vlan_list[0x5]; 1824 u8 reserved_at_3f0[0x3]; 1825 u8 log_max_current_mc_list[0x5]; 1826 u8 reserved_at_3f8[0x3]; 1827 u8 log_max_current_uc_list[0x5]; 1828 1829 u8 general_obj_types[0x40]; 1830 1831 u8 sq_ts_format[0x2]; 1832 u8 rq_ts_format[0x2]; 1833 u8 steering_format_version[0x4]; 1834 u8 create_qp_start_hint[0x18]; 1835 1836 u8 reserved_at_460[0x1]; 1837 u8 ats[0x1]; 1838 u8 reserved_at_462[0x1]; 1839 u8 log_max_uctx[0x5]; 1840 u8 reserved_at_468[0x1]; 1841 u8 crypto[0x1]; 1842 u8 ipsec_offload[0x1]; 1843 u8 log_max_umem[0x5]; 1844 u8 max_num_eqs[0x10]; 1845 1846 u8 reserved_at_480[0x1]; 1847 u8 tls_tx[0x1]; 1848 u8 tls_rx[0x1]; 1849 u8 log_max_l2_table[0x5]; 1850 u8 reserved_at_488[0x8]; 1851 u8 log_uar_page_sz[0x10]; 1852 1853 u8 reserved_at_4a0[0x20]; 1854 u8 device_frequency_mhz[0x20]; 1855 u8 device_frequency_khz[0x20]; 1856 1857 u8 reserved_at_500[0x20]; 1858 u8 num_of_uars_per_page[0x20]; 1859 1860 u8 flex_parser_protocols[0x20]; 1861 1862 u8 max_geneve_tlv_options[0x8]; 1863 u8 reserved_at_568[0x3]; 1864 u8 max_geneve_tlv_option_data_len[0x5]; 1865 u8 reserved_at_570[0x9]; 1866 u8 adv_virtualization[0x1]; 1867 u8 reserved_at_57a[0x6]; 1868 1869 u8 reserved_at_580[0xb]; 1870 u8 log_max_dci_stream_channels[0x5]; 1871 u8 reserved_at_590[0x3]; 1872 u8 log_max_dci_errored_streams[0x5]; 1873 u8 reserved_at_598[0x8]; 1874 1875 u8 reserved_at_5a0[0x10]; 1876 u8 enhanced_cqe_compression[0x1]; 1877 u8 reserved_at_5b1[0x2]; 1878 u8 log_max_dek[0x5]; 1879 u8 reserved_at_5b8[0x4]; 1880 u8 mini_cqe_resp_stride_index[0x1]; 1881 u8 cqe_128_always[0x1]; 1882 u8 cqe_compression_128[0x1]; 1883 u8 cqe_compression[0x1]; 1884 1885 u8 cqe_compression_timeout[0x10]; 1886 u8 cqe_compression_max_num[0x10]; 1887 1888 u8 reserved_at_5e0[0x8]; 1889 u8 flex_parser_id_gtpu_dw_0[0x4]; 1890 u8 reserved_at_5ec[0x4]; 1891 u8 tag_matching[0x1]; 1892 u8 rndv_offload_rc[0x1]; 1893 u8 rndv_offload_dc[0x1]; 1894 u8 log_tag_matching_list_sz[0x5]; 1895 u8 reserved_at_5f8[0x3]; 1896 u8 log_max_xrq[0x5]; 1897 1898 u8 affiliate_nic_vport_criteria[0x8]; 1899 u8 native_port_num[0x8]; 1900 u8 num_vhca_ports[0x8]; 1901 u8 flex_parser_id_gtpu_teid[0x4]; 1902 u8 reserved_at_61c[0x2]; 1903 u8 sw_owner_id[0x1]; 1904 u8 reserved_at_61f[0x1]; 1905 1906 u8 max_num_of_monitor_counters[0x10]; 1907 u8 num_ppcnt_monitor_counters[0x10]; 1908 1909 u8 max_num_sf[0x10]; 1910 u8 num_q_monitor_counters[0x10]; 1911 1912 u8 reserved_at_660[0x20]; 1913 1914 u8 sf[0x1]; 1915 u8 sf_set_partition[0x1]; 1916 u8 reserved_at_682[0x1]; 1917 u8 log_max_sf[0x5]; 1918 u8 apu[0x1]; 1919 u8 reserved_at_689[0x4]; 1920 u8 migration[0x1]; 1921 u8 reserved_at_68e[0x2]; 1922 u8 log_min_sf_size[0x8]; 1923 u8 max_num_sf_partitions[0x8]; 1924 1925 u8 uctx_cap[0x20]; 1926 1927 u8 reserved_at_6c0[0x4]; 1928 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1929 u8 flex_parser_id_icmp_dw1[0x4]; 1930 u8 flex_parser_id_icmp_dw0[0x4]; 1931 u8 flex_parser_id_icmpv6_dw1[0x4]; 1932 u8 flex_parser_id_icmpv6_dw0[0x4]; 1933 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1934 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1935 1936 u8 max_num_match_definer[0x10]; 1937 u8 sf_base_id[0x10]; 1938 1939 u8 flex_parser_id_gtpu_dw_2[0x4]; 1940 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1941 u8 num_total_dynamic_vf_msix[0x18]; 1942 u8 reserved_at_720[0x14]; 1943 u8 dynamic_msix_table_size[0xc]; 1944 u8 reserved_at_740[0xc]; 1945 u8 min_dynamic_vf_msix_table_size[0x4]; 1946 u8 reserved_at_750[0x4]; 1947 u8 max_dynamic_vf_msix_table_size[0xc]; 1948 1949 u8 reserved_at_760[0x3]; 1950 u8 log_max_num_header_modify_argument[0x5]; 1951 u8 reserved_at_768[0x4]; 1952 u8 log_header_modify_argument_granularity[0x4]; 1953 u8 reserved_at_770[0x3]; 1954 u8 log_header_modify_argument_max_alloc[0x5]; 1955 u8 reserved_at_778[0x8]; 1956 1957 u8 vhca_tunnel_commands[0x40]; 1958 u8 match_definer_format_supported[0x40]; 1959 }; 1960 1961 struct mlx5_ifc_cmd_hca_cap_2_bits { 1962 u8 reserved_at_0[0x80]; 1963 1964 u8 migratable[0x1]; 1965 u8 reserved_at_81[0x1f]; 1966 1967 u8 max_reformat_insert_size[0x8]; 1968 u8 max_reformat_insert_offset[0x8]; 1969 u8 max_reformat_remove_size[0x8]; 1970 u8 max_reformat_remove_offset[0x8]; 1971 1972 u8 reserved_at_c0[0x8]; 1973 u8 migration_multi_load[0x1]; 1974 u8 migration_tracking_state[0x1]; 1975 u8 reserved_at_ca[0x16]; 1976 1977 u8 reserved_at_e0[0xc0]; 1978 1979 u8 flow_table_type_2_type[0x8]; 1980 u8 reserved_at_1a8[0x3]; 1981 u8 log_min_mkey_entity_size[0x5]; 1982 u8 reserved_at_1b0[0x10]; 1983 1984 u8 reserved_at_1c0[0x60]; 1985 1986 u8 reserved_at_220[0x1]; 1987 u8 sw_vhca_id_valid[0x1]; 1988 u8 sw_vhca_id[0xe]; 1989 u8 reserved_at_230[0x10]; 1990 1991 u8 reserved_at_240[0xb]; 1992 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1993 u8 reserved_at_250[0x10]; 1994 1995 u8 reserved_at_260[0x120]; 1996 u8 reserved_at_380[0x10]; 1997 u8 ec_vf_vport_base[0x10]; 1998 u8 reserved_at_3a0[0x460]; 1999 }; 2000 2001 enum mlx5_ifc_flow_destination_type { 2002 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2003 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2004 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2005 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2006 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2007 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2008 }; 2009 2010 enum mlx5_flow_table_miss_action { 2011 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2012 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2013 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2014 }; 2015 2016 struct mlx5_ifc_dest_format_struct_bits { 2017 u8 destination_type[0x8]; 2018 u8 destination_id[0x18]; 2019 2020 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2021 u8 packet_reformat[0x1]; 2022 u8 reserved_at_22[0x6]; 2023 u8 destination_table_type[0x8]; 2024 u8 destination_eswitch_owner_vhca_id[0x10]; 2025 }; 2026 2027 struct mlx5_ifc_flow_counter_list_bits { 2028 u8 flow_counter_id[0x20]; 2029 2030 u8 reserved_at_20[0x20]; 2031 }; 2032 2033 struct mlx5_ifc_extended_dest_format_bits { 2034 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2035 2036 u8 packet_reformat_id[0x20]; 2037 2038 u8 reserved_at_60[0x20]; 2039 }; 2040 2041 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2042 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2043 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2044 }; 2045 2046 struct mlx5_ifc_fte_match_param_bits { 2047 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2048 2049 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2050 2051 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2052 2053 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2054 2055 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2056 2057 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2058 2059 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2060 2061 u8 reserved_at_e00[0x200]; 2062 }; 2063 2064 enum { 2065 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2066 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2067 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2068 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2069 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2070 }; 2071 2072 struct mlx5_ifc_rx_hash_field_select_bits { 2073 u8 l3_prot_type[0x1]; 2074 u8 l4_prot_type[0x1]; 2075 u8 selected_fields[0x1e]; 2076 }; 2077 2078 enum { 2079 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2080 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2081 }; 2082 2083 enum { 2084 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2085 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2086 }; 2087 2088 struct mlx5_ifc_wq_bits { 2089 u8 wq_type[0x4]; 2090 u8 wq_signature[0x1]; 2091 u8 end_padding_mode[0x2]; 2092 u8 cd_slave[0x1]; 2093 u8 reserved_at_8[0x18]; 2094 2095 u8 hds_skip_first_sge[0x1]; 2096 u8 log2_hds_buf_size[0x3]; 2097 u8 reserved_at_24[0x7]; 2098 u8 page_offset[0x5]; 2099 u8 lwm[0x10]; 2100 2101 u8 reserved_at_40[0x8]; 2102 u8 pd[0x18]; 2103 2104 u8 reserved_at_60[0x8]; 2105 u8 uar_page[0x18]; 2106 2107 u8 dbr_addr[0x40]; 2108 2109 u8 hw_counter[0x20]; 2110 2111 u8 sw_counter[0x20]; 2112 2113 u8 reserved_at_100[0xc]; 2114 u8 log_wq_stride[0x4]; 2115 u8 reserved_at_110[0x3]; 2116 u8 log_wq_pg_sz[0x5]; 2117 u8 reserved_at_118[0x3]; 2118 u8 log_wq_sz[0x5]; 2119 2120 u8 dbr_umem_valid[0x1]; 2121 u8 wq_umem_valid[0x1]; 2122 u8 reserved_at_122[0x1]; 2123 u8 log_hairpin_num_packets[0x5]; 2124 u8 reserved_at_128[0x3]; 2125 u8 log_hairpin_data_sz[0x5]; 2126 2127 u8 reserved_at_130[0x4]; 2128 u8 log_wqe_num_of_strides[0x4]; 2129 u8 two_byte_shift_en[0x1]; 2130 u8 reserved_at_139[0x4]; 2131 u8 log_wqe_stride_size[0x3]; 2132 2133 u8 reserved_at_140[0x80]; 2134 2135 u8 headers_mkey[0x20]; 2136 2137 u8 shampo_enable[0x1]; 2138 u8 reserved_at_1e1[0x4]; 2139 u8 log_reservation_size[0x3]; 2140 u8 reserved_at_1e8[0x5]; 2141 u8 log_max_num_of_packets_per_reservation[0x3]; 2142 u8 reserved_at_1f0[0x6]; 2143 u8 log_headers_entry_size[0x2]; 2144 u8 reserved_at_1f8[0x4]; 2145 u8 log_headers_buffer_entry_num[0x4]; 2146 2147 u8 reserved_at_200[0x400]; 2148 2149 struct mlx5_ifc_cmd_pas_bits pas[]; 2150 }; 2151 2152 struct mlx5_ifc_rq_num_bits { 2153 u8 reserved_at_0[0x8]; 2154 u8 rq_num[0x18]; 2155 }; 2156 2157 struct mlx5_ifc_mac_address_layout_bits { 2158 u8 reserved_at_0[0x10]; 2159 u8 mac_addr_47_32[0x10]; 2160 2161 u8 mac_addr_31_0[0x20]; 2162 }; 2163 2164 struct mlx5_ifc_vlan_layout_bits { 2165 u8 reserved_at_0[0x14]; 2166 u8 vlan[0x0c]; 2167 2168 u8 reserved_at_20[0x20]; 2169 }; 2170 2171 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2172 u8 reserved_at_0[0xa0]; 2173 2174 u8 min_time_between_cnps[0x20]; 2175 2176 u8 reserved_at_c0[0x12]; 2177 u8 cnp_dscp[0x6]; 2178 u8 reserved_at_d8[0x4]; 2179 u8 cnp_prio_mode[0x1]; 2180 u8 cnp_802p_prio[0x3]; 2181 2182 u8 reserved_at_e0[0x720]; 2183 }; 2184 2185 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2186 u8 reserved_at_0[0x60]; 2187 2188 u8 reserved_at_60[0x4]; 2189 u8 clamp_tgt_rate[0x1]; 2190 u8 reserved_at_65[0x3]; 2191 u8 clamp_tgt_rate_after_time_inc[0x1]; 2192 u8 reserved_at_69[0x17]; 2193 2194 u8 reserved_at_80[0x20]; 2195 2196 u8 rpg_time_reset[0x20]; 2197 2198 u8 rpg_byte_reset[0x20]; 2199 2200 u8 rpg_threshold[0x20]; 2201 2202 u8 rpg_max_rate[0x20]; 2203 2204 u8 rpg_ai_rate[0x20]; 2205 2206 u8 rpg_hai_rate[0x20]; 2207 2208 u8 rpg_gd[0x20]; 2209 2210 u8 rpg_min_dec_fac[0x20]; 2211 2212 u8 rpg_min_rate[0x20]; 2213 2214 u8 reserved_at_1c0[0xe0]; 2215 2216 u8 rate_to_set_on_first_cnp[0x20]; 2217 2218 u8 dce_tcp_g[0x20]; 2219 2220 u8 dce_tcp_rtt[0x20]; 2221 2222 u8 rate_reduce_monitor_period[0x20]; 2223 2224 u8 reserved_at_320[0x20]; 2225 2226 u8 initial_alpha_value[0x20]; 2227 2228 u8 reserved_at_360[0x4a0]; 2229 }; 2230 2231 struct mlx5_ifc_cong_control_r_roce_general_bits { 2232 u8 reserved_at_0[0x80]; 2233 2234 u8 reserved_at_80[0x10]; 2235 u8 rtt_resp_dscp_valid[0x1]; 2236 u8 reserved_at_91[0x9]; 2237 u8 rtt_resp_dscp[0x6]; 2238 2239 u8 reserved_at_a0[0x760]; 2240 }; 2241 2242 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2243 u8 reserved_at_0[0x80]; 2244 2245 u8 rppp_max_rps[0x20]; 2246 2247 u8 rpg_time_reset[0x20]; 2248 2249 u8 rpg_byte_reset[0x20]; 2250 2251 u8 rpg_threshold[0x20]; 2252 2253 u8 rpg_max_rate[0x20]; 2254 2255 u8 rpg_ai_rate[0x20]; 2256 2257 u8 rpg_hai_rate[0x20]; 2258 2259 u8 rpg_gd[0x20]; 2260 2261 u8 rpg_min_dec_fac[0x20]; 2262 2263 u8 rpg_min_rate[0x20]; 2264 2265 u8 reserved_at_1c0[0x640]; 2266 }; 2267 2268 enum { 2269 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2270 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2271 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2272 }; 2273 2274 struct mlx5_ifc_resize_field_select_bits { 2275 u8 resize_field_select[0x20]; 2276 }; 2277 2278 struct mlx5_ifc_resource_dump_bits { 2279 u8 more_dump[0x1]; 2280 u8 inline_dump[0x1]; 2281 u8 reserved_at_2[0xa]; 2282 u8 seq_num[0x4]; 2283 u8 segment_type[0x10]; 2284 2285 u8 reserved_at_20[0x10]; 2286 u8 vhca_id[0x10]; 2287 2288 u8 index1[0x20]; 2289 2290 u8 index2[0x20]; 2291 2292 u8 num_of_obj1[0x10]; 2293 u8 num_of_obj2[0x10]; 2294 2295 u8 reserved_at_a0[0x20]; 2296 2297 u8 device_opaque[0x40]; 2298 2299 u8 mkey[0x20]; 2300 2301 u8 size[0x20]; 2302 2303 u8 address[0x40]; 2304 2305 u8 inline_data[52][0x20]; 2306 }; 2307 2308 struct mlx5_ifc_resource_dump_menu_record_bits { 2309 u8 reserved_at_0[0x4]; 2310 u8 num_of_obj2_supports_active[0x1]; 2311 u8 num_of_obj2_supports_all[0x1]; 2312 u8 must_have_num_of_obj2[0x1]; 2313 u8 support_num_of_obj2[0x1]; 2314 u8 num_of_obj1_supports_active[0x1]; 2315 u8 num_of_obj1_supports_all[0x1]; 2316 u8 must_have_num_of_obj1[0x1]; 2317 u8 support_num_of_obj1[0x1]; 2318 u8 must_have_index2[0x1]; 2319 u8 support_index2[0x1]; 2320 u8 must_have_index1[0x1]; 2321 u8 support_index1[0x1]; 2322 u8 segment_type[0x10]; 2323 2324 u8 segment_name[4][0x20]; 2325 2326 u8 index1_name[4][0x20]; 2327 2328 u8 index2_name[4][0x20]; 2329 }; 2330 2331 struct mlx5_ifc_resource_dump_segment_header_bits { 2332 u8 length_dw[0x10]; 2333 u8 segment_type[0x10]; 2334 }; 2335 2336 struct mlx5_ifc_resource_dump_command_segment_bits { 2337 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2338 2339 u8 segment_called[0x10]; 2340 u8 vhca_id[0x10]; 2341 2342 u8 index1[0x20]; 2343 2344 u8 index2[0x20]; 2345 2346 u8 num_of_obj1[0x10]; 2347 u8 num_of_obj2[0x10]; 2348 }; 2349 2350 struct mlx5_ifc_resource_dump_error_segment_bits { 2351 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2352 2353 u8 reserved_at_20[0x10]; 2354 u8 syndrome_id[0x10]; 2355 2356 u8 reserved_at_40[0x40]; 2357 2358 u8 error[8][0x20]; 2359 }; 2360 2361 struct mlx5_ifc_resource_dump_info_segment_bits { 2362 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2363 2364 u8 reserved_at_20[0x18]; 2365 u8 dump_version[0x8]; 2366 2367 u8 hw_version[0x20]; 2368 2369 u8 fw_version[0x20]; 2370 }; 2371 2372 struct mlx5_ifc_resource_dump_menu_segment_bits { 2373 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2374 2375 u8 reserved_at_20[0x10]; 2376 u8 num_of_records[0x10]; 2377 2378 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2379 }; 2380 2381 struct mlx5_ifc_resource_dump_resource_segment_bits { 2382 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2383 2384 u8 reserved_at_20[0x20]; 2385 2386 u8 index1[0x20]; 2387 2388 u8 index2[0x20]; 2389 2390 u8 payload[][0x20]; 2391 }; 2392 2393 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2394 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2395 }; 2396 2397 struct mlx5_ifc_menu_resource_dump_response_bits { 2398 struct mlx5_ifc_resource_dump_info_segment_bits info; 2399 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2400 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2401 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2402 }; 2403 2404 enum { 2405 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2406 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2407 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2408 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2409 }; 2410 2411 struct mlx5_ifc_modify_field_select_bits { 2412 u8 modify_field_select[0x20]; 2413 }; 2414 2415 struct mlx5_ifc_field_select_r_roce_np_bits { 2416 u8 field_select_r_roce_np[0x20]; 2417 }; 2418 2419 struct mlx5_ifc_field_select_r_roce_rp_bits { 2420 u8 field_select_r_roce_rp[0x20]; 2421 }; 2422 2423 enum { 2424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2425 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2426 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2427 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2428 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2429 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2430 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2431 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2432 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2433 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2434 }; 2435 2436 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2437 u8 field_select_8021qaurp[0x20]; 2438 }; 2439 2440 struct mlx5_ifc_phys_layer_cntrs_bits { 2441 u8 time_since_last_clear_high[0x20]; 2442 2443 u8 time_since_last_clear_low[0x20]; 2444 2445 u8 symbol_errors_high[0x20]; 2446 2447 u8 symbol_errors_low[0x20]; 2448 2449 u8 sync_headers_errors_high[0x20]; 2450 2451 u8 sync_headers_errors_low[0x20]; 2452 2453 u8 edpl_bip_errors_lane0_high[0x20]; 2454 2455 u8 edpl_bip_errors_lane0_low[0x20]; 2456 2457 u8 edpl_bip_errors_lane1_high[0x20]; 2458 2459 u8 edpl_bip_errors_lane1_low[0x20]; 2460 2461 u8 edpl_bip_errors_lane2_high[0x20]; 2462 2463 u8 edpl_bip_errors_lane2_low[0x20]; 2464 2465 u8 edpl_bip_errors_lane3_high[0x20]; 2466 2467 u8 edpl_bip_errors_lane3_low[0x20]; 2468 2469 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2470 2471 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2472 2473 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2474 2475 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2476 2477 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2478 2479 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2480 2481 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2482 2483 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2484 2485 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2486 2487 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2488 2489 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2490 2491 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2492 2493 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2494 2495 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2496 2497 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2498 2499 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2500 2501 u8 rs_fec_corrected_blocks_high[0x20]; 2502 2503 u8 rs_fec_corrected_blocks_low[0x20]; 2504 2505 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2506 2507 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2508 2509 u8 rs_fec_no_errors_blocks_high[0x20]; 2510 2511 u8 rs_fec_no_errors_blocks_low[0x20]; 2512 2513 u8 rs_fec_single_error_blocks_high[0x20]; 2514 2515 u8 rs_fec_single_error_blocks_low[0x20]; 2516 2517 u8 rs_fec_corrected_symbols_total_high[0x20]; 2518 2519 u8 rs_fec_corrected_symbols_total_low[0x20]; 2520 2521 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2522 2523 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2524 2525 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2526 2527 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2528 2529 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2530 2531 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2532 2533 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2534 2535 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2536 2537 u8 link_down_events[0x20]; 2538 2539 u8 successful_recovery_events[0x20]; 2540 2541 u8 reserved_at_640[0x180]; 2542 }; 2543 2544 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2545 u8 time_since_last_clear_high[0x20]; 2546 2547 u8 time_since_last_clear_low[0x20]; 2548 2549 u8 phy_received_bits_high[0x20]; 2550 2551 u8 phy_received_bits_low[0x20]; 2552 2553 u8 phy_symbol_errors_high[0x20]; 2554 2555 u8 phy_symbol_errors_low[0x20]; 2556 2557 u8 phy_corrected_bits_high[0x20]; 2558 2559 u8 phy_corrected_bits_low[0x20]; 2560 2561 u8 phy_corrected_bits_lane0_high[0x20]; 2562 2563 u8 phy_corrected_bits_lane0_low[0x20]; 2564 2565 u8 phy_corrected_bits_lane1_high[0x20]; 2566 2567 u8 phy_corrected_bits_lane1_low[0x20]; 2568 2569 u8 phy_corrected_bits_lane2_high[0x20]; 2570 2571 u8 phy_corrected_bits_lane2_low[0x20]; 2572 2573 u8 phy_corrected_bits_lane3_high[0x20]; 2574 2575 u8 phy_corrected_bits_lane3_low[0x20]; 2576 2577 u8 reserved_at_200[0x5c0]; 2578 }; 2579 2580 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2581 u8 symbol_error_counter[0x10]; 2582 2583 u8 link_error_recovery_counter[0x8]; 2584 2585 u8 link_downed_counter[0x8]; 2586 2587 u8 port_rcv_errors[0x10]; 2588 2589 u8 port_rcv_remote_physical_errors[0x10]; 2590 2591 u8 port_rcv_switch_relay_errors[0x10]; 2592 2593 u8 port_xmit_discards[0x10]; 2594 2595 u8 port_xmit_constraint_errors[0x8]; 2596 2597 u8 port_rcv_constraint_errors[0x8]; 2598 2599 u8 reserved_at_70[0x8]; 2600 2601 u8 link_overrun_errors[0x8]; 2602 2603 u8 reserved_at_80[0x10]; 2604 2605 u8 vl_15_dropped[0x10]; 2606 2607 u8 reserved_at_a0[0x80]; 2608 2609 u8 port_xmit_wait[0x20]; 2610 }; 2611 2612 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2613 u8 transmit_queue_high[0x20]; 2614 2615 u8 transmit_queue_low[0x20]; 2616 2617 u8 no_buffer_discard_uc_high[0x20]; 2618 2619 u8 no_buffer_discard_uc_low[0x20]; 2620 2621 u8 reserved_at_80[0x740]; 2622 }; 2623 2624 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2625 u8 wred_discard_high[0x20]; 2626 2627 u8 wred_discard_low[0x20]; 2628 2629 u8 ecn_marked_tc_high[0x20]; 2630 2631 u8 ecn_marked_tc_low[0x20]; 2632 2633 u8 reserved_at_80[0x740]; 2634 }; 2635 2636 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2637 u8 rx_octets_high[0x20]; 2638 2639 u8 rx_octets_low[0x20]; 2640 2641 u8 reserved_at_40[0xc0]; 2642 2643 u8 rx_frames_high[0x20]; 2644 2645 u8 rx_frames_low[0x20]; 2646 2647 u8 tx_octets_high[0x20]; 2648 2649 u8 tx_octets_low[0x20]; 2650 2651 u8 reserved_at_180[0xc0]; 2652 2653 u8 tx_frames_high[0x20]; 2654 2655 u8 tx_frames_low[0x20]; 2656 2657 u8 rx_pause_high[0x20]; 2658 2659 u8 rx_pause_low[0x20]; 2660 2661 u8 rx_pause_duration_high[0x20]; 2662 2663 u8 rx_pause_duration_low[0x20]; 2664 2665 u8 tx_pause_high[0x20]; 2666 2667 u8 tx_pause_low[0x20]; 2668 2669 u8 tx_pause_duration_high[0x20]; 2670 2671 u8 tx_pause_duration_low[0x20]; 2672 2673 u8 rx_pause_transition_high[0x20]; 2674 2675 u8 rx_pause_transition_low[0x20]; 2676 2677 u8 rx_discards_high[0x20]; 2678 2679 u8 rx_discards_low[0x20]; 2680 2681 u8 device_stall_minor_watermark_cnt_high[0x20]; 2682 2683 u8 device_stall_minor_watermark_cnt_low[0x20]; 2684 2685 u8 device_stall_critical_watermark_cnt_high[0x20]; 2686 2687 u8 device_stall_critical_watermark_cnt_low[0x20]; 2688 2689 u8 reserved_at_480[0x340]; 2690 }; 2691 2692 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2693 u8 port_transmit_wait_high[0x20]; 2694 2695 u8 port_transmit_wait_low[0x20]; 2696 2697 u8 reserved_at_40[0x100]; 2698 2699 u8 rx_buffer_almost_full_high[0x20]; 2700 2701 u8 rx_buffer_almost_full_low[0x20]; 2702 2703 u8 rx_buffer_full_high[0x20]; 2704 2705 u8 rx_buffer_full_low[0x20]; 2706 2707 u8 rx_icrc_encapsulated_high[0x20]; 2708 2709 u8 rx_icrc_encapsulated_low[0x20]; 2710 2711 u8 reserved_at_200[0x5c0]; 2712 }; 2713 2714 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2715 u8 dot3stats_alignment_errors_high[0x20]; 2716 2717 u8 dot3stats_alignment_errors_low[0x20]; 2718 2719 u8 dot3stats_fcs_errors_high[0x20]; 2720 2721 u8 dot3stats_fcs_errors_low[0x20]; 2722 2723 u8 dot3stats_single_collision_frames_high[0x20]; 2724 2725 u8 dot3stats_single_collision_frames_low[0x20]; 2726 2727 u8 dot3stats_multiple_collision_frames_high[0x20]; 2728 2729 u8 dot3stats_multiple_collision_frames_low[0x20]; 2730 2731 u8 dot3stats_sqe_test_errors_high[0x20]; 2732 2733 u8 dot3stats_sqe_test_errors_low[0x20]; 2734 2735 u8 dot3stats_deferred_transmissions_high[0x20]; 2736 2737 u8 dot3stats_deferred_transmissions_low[0x20]; 2738 2739 u8 dot3stats_late_collisions_high[0x20]; 2740 2741 u8 dot3stats_late_collisions_low[0x20]; 2742 2743 u8 dot3stats_excessive_collisions_high[0x20]; 2744 2745 u8 dot3stats_excessive_collisions_low[0x20]; 2746 2747 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2748 2749 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2750 2751 u8 dot3stats_carrier_sense_errors_high[0x20]; 2752 2753 u8 dot3stats_carrier_sense_errors_low[0x20]; 2754 2755 u8 dot3stats_frame_too_longs_high[0x20]; 2756 2757 u8 dot3stats_frame_too_longs_low[0x20]; 2758 2759 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2760 2761 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2762 2763 u8 dot3stats_symbol_errors_high[0x20]; 2764 2765 u8 dot3stats_symbol_errors_low[0x20]; 2766 2767 u8 dot3control_in_unknown_opcodes_high[0x20]; 2768 2769 u8 dot3control_in_unknown_opcodes_low[0x20]; 2770 2771 u8 dot3in_pause_frames_high[0x20]; 2772 2773 u8 dot3in_pause_frames_low[0x20]; 2774 2775 u8 dot3out_pause_frames_high[0x20]; 2776 2777 u8 dot3out_pause_frames_low[0x20]; 2778 2779 u8 reserved_at_400[0x3c0]; 2780 }; 2781 2782 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2783 u8 ether_stats_drop_events_high[0x20]; 2784 2785 u8 ether_stats_drop_events_low[0x20]; 2786 2787 u8 ether_stats_octets_high[0x20]; 2788 2789 u8 ether_stats_octets_low[0x20]; 2790 2791 u8 ether_stats_pkts_high[0x20]; 2792 2793 u8 ether_stats_pkts_low[0x20]; 2794 2795 u8 ether_stats_broadcast_pkts_high[0x20]; 2796 2797 u8 ether_stats_broadcast_pkts_low[0x20]; 2798 2799 u8 ether_stats_multicast_pkts_high[0x20]; 2800 2801 u8 ether_stats_multicast_pkts_low[0x20]; 2802 2803 u8 ether_stats_crc_align_errors_high[0x20]; 2804 2805 u8 ether_stats_crc_align_errors_low[0x20]; 2806 2807 u8 ether_stats_undersize_pkts_high[0x20]; 2808 2809 u8 ether_stats_undersize_pkts_low[0x20]; 2810 2811 u8 ether_stats_oversize_pkts_high[0x20]; 2812 2813 u8 ether_stats_oversize_pkts_low[0x20]; 2814 2815 u8 ether_stats_fragments_high[0x20]; 2816 2817 u8 ether_stats_fragments_low[0x20]; 2818 2819 u8 ether_stats_jabbers_high[0x20]; 2820 2821 u8 ether_stats_jabbers_low[0x20]; 2822 2823 u8 ether_stats_collisions_high[0x20]; 2824 2825 u8 ether_stats_collisions_low[0x20]; 2826 2827 u8 ether_stats_pkts64octets_high[0x20]; 2828 2829 u8 ether_stats_pkts64octets_low[0x20]; 2830 2831 u8 ether_stats_pkts65to127octets_high[0x20]; 2832 2833 u8 ether_stats_pkts65to127octets_low[0x20]; 2834 2835 u8 ether_stats_pkts128to255octets_high[0x20]; 2836 2837 u8 ether_stats_pkts128to255octets_low[0x20]; 2838 2839 u8 ether_stats_pkts256to511octets_high[0x20]; 2840 2841 u8 ether_stats_pkts256to511octets_low[0x20]; 2842 2843 u8 ether_stats_pkts512to1023octets_high[0x20]; 2844 2845 u8 ether_stats_pkts512to1023octets_low[0x20]; 2846 2847 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2848 2849 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2850 2851 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2852 2853 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2854 2855 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2856 2857 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2858 2859 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2860 2861 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2862 2863 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2864 2865 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2866 2867 u8 reserved_at_540[0x280]; 2868 }; 2869 2870 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2871 u8 if_in_octets_high[0x20]; 2872 2873 u8 if_in_octets_low[0x20]; 2874 2875 u8 if_in_ucast_pkts_high[0x20]; 2876 2877 u8 if_in_ucast_pkts_low[0x20]; 2878 2879 u8 if_in_discards_high[0x20]; 2880 2881 u8 if_in_discards_low[0x20]; 2882 2883 u8 if_in_errors_high[0x20]; 2884 2885 u8 if_in_errors_low[0x20]; 2886 2887 u8 if_in_unknown_protos_high[0x20]; 2888 2889 u8 if_in_unknown_protos_low[0x20]; 2890 2891 u8 if_out_octets_high[0x20]; 2892 2893 u8 if_out_octets_low[0x20]; 2894 2895 u8 if_out_ucast_pkts_high[0x20]; 2896 2897 u8 if_out_ucast_pkts_low[0x20]; 2898 2899 u8 if_out_discards_high[0x20]; 2900 2901 u8 if_out_discards_low[0x20]; 2902 2903 u8 if_out_errors_high[0x20]; 2904 2905 u8 if_out_errors_low[0x20]; 2906 2907 u8 if_in_multicast_pkts_high[0x20]; 2908 2909 u8 if_in_multicast_pkts_low[0x20]; 2910 2911 u8 if_in_broadcast_pkts_high[0x20]; 2912 2913 u8 if_in_broadcast_pkts_low[0x20]; 2914 2915 u8 if_out_multicast_pkts_high[0x20]; 2916 2917 u8 if_out_multicast_pkts_low[0x20]; 2918 2919 u8 if_out_broadcast_pkts_high[0x20]; 2920 2921 u8 if_out_broadcast_pkts_low[0x20]; 2922 2923 u8 reserved_at_340[0x480]; 2924 }; 2925 2926 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2927 u8 a_frames_transmitted_ok_high[0x20]; 2928 2929 u8 a_frames_transmitted_ok_low[0x20]; 2930 2931 u8 a_frames_received_ok_high[0x20]; 2932 2933 u8 a_frames_received_ok_low[0x20]; 2934 2935 u8 a_frame_check_sequence_errors_high[0x20]; 2936 2937 u8 a_frame_check_sequence_errors_low[0x20]; 2938 2939 u8 a_alignment_errors_high[0x20]; 2940 2941 u8 a_alignment_errors_low[0x20]; 2942 2943 u8 a_octets_transmitted_ok_high[0x20]; 2944 2945 u8 a_octets_transmitted_ok_low[0x20]; 2946 2947 u8 a_octets_received_ok_high[0x20]; 2948 2949 u8 a_octets_received_ok_low[0x20]; 2950 2951 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2952 2953 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2954 2955 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2956 2957 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2958 2959 u8 a_multicast_frames_received_ok_high[0x20]; 2960 2961 u8 a_multicast_frames_received_ok_low[0x20]; 2962 2963 u8 a_broadcast_frames_received_ok_high[0x20]; 2964 2965 u8 a_broadcast_frames_received_ok_low[0x20]; 2966 2967 u8 a_in_range_length_errors_high[0x20]; 2968 2969 u8 a_in_range_length_errors_low[0x20]; 2970 2971 u8 a_out_of_range_length_field_high[0x20]; 2972 2973 u8 a_out_of_range_length_field_low[0x20]; 2974 2975 u8 a_frame_too_long_errors_high[0x20]; 2976 2977 u8 a_frame_too_long_errors_low[0x20]; 2978 2979 u8 a_symbol_error_during_carrier_high[0x20]; 2980 2981 u8 a_symbol_error_during_carrier_low[0x20]; 2982 2983 u8 a_mac_control_frames_transmitted_high[0x20]; 2984 2985 u8 a_mac_control_frames_transmitted_low[0x20]; 2986 2987 u8 a_mac_control_frames_received_high[0x20]; 2988 2989 u8 a_mac_control_frames_received_low[0x20]; 2990 2991 u8 a_unsupported_opcodes_received_high[0x20]; 2992 2993 u8 a_unsupported_opcodes_received_low[0x20]; 2994 2995 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2996 2997 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2998 2999 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3000 3001 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3002 3003 u8 reserved_at_4c0[0x300]; 3004 }; 3005 3006 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3007 u8 life_time_counter_high[0x20]; 3008 3009 u8 life_time_counter_low[0x20]; 3010 3011 u8 rx_errors[0x20]; 3012 3013 u8 tx_errors[0x20]; 3014 3015 u8 l0_to_recovery_eieos[0x20]; 3016 3017 u8 l0_to_recovery_ts[0x20]; 3018 3019 u8 l0_to_recovery_framing[0x20]; 3020 3021 u8 l0_to_recovery_retrain[0x20]; 3022 3023 u8 crc_error_dllp[0x20]; 3024 3025 u8 crc_error_tlp[0x20]; 3026 3027 u8 tx_overflow_buffer_pkt_high[0x20]; 3028 3029 u8 tx_overflow_buffer_pkt_low[0x20]; 3030 3031 u8 outbound_stalled_reads[0x20]; 3032 3033 u8 outbound_stalled_writes[0x20]; 3034 3035 u8 outbound_stalled_reads_events[0x20]; 3036 3037 u8 outbound_stalled_writes_events[0x20]; 3038 3039 u8 reserved_at_200[0x5c0]; 3040 }; 3041 3042 struct mlx5_ifc_cmd_inter_comp_event_bits { 3043 u8 command_completion_vector[0x20]; 3044 3045 u8 reserved_at_20[0xc0]; 3046 }; 3047 3048 struct mlx5_ifc_stall_vl_event_bits { 3049 u8 reserved_at_0[0x18]; 3050 u8 port_num[0x1]; 3051 u8 reserved_at_19[0x3]; 3052 u8 vl[0x4]; 3053 3054 u8 reserved_at_20[0xa0]; 3055 }; 3056 3057 struct mlx5_ifc_db_bf_congestion_event_bits { 3058 u8 event_subtype[0x8]; 3059 u8 reserved_at_8[0x8]; 3060 u8 congestion_level[0x8]; 3061 u8 reserved_at_18[0x8]; 3062 3063 u8 reserved_at_20[0xa0]; 3064 }; 3065 3066 struct mlx5_ifc_gpio_event_bits { 3067 u8 reserved_at_0[0x60]; 3068 3069 u8 gpio_event_hi[0x20]; 3070 3071 u8 gpio_event_lo[0x20]; 3072 3073 u8 reserved_at_a0[0x40]; 3074 }; 3075 3076 struct mlx5_ifc_port_state_change_event_bits { 3077 u8 reserved_at_0[0x40]; 3078 3079 u8 port_num[0x4]; 3080 u8 reserved_at_44[0x1c]; 3081 3082 u8 reserved_at_60[0x80]; 3083 }; 3084 3085 struct mlx5_ifc_dropped_packet_logged_bits { 3086 u8 reserved_at_0[0xe0]; 3087 }; 3088 3089 struct mlx5_ifc_default_timeout_bits { 3090 u8 to_multiplier[0x3]; 3091 u8 reserved_at_3[0x9]; 3092 u8 to_value[0x14]; 3093 }; 3094 3095 struct mlx5_ifc_dtor_reg_bits { 3096 u8 reserved_at_0[0x20]; 3097 3098 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3099 3100 u8 reserved_at_40[0x60]; 3101 3102 struct mlx5_ifc_default_timeout_bits health_poll_to; 3103 3104 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3105 3106 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3107 3108 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3109 3110 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3111 3112 struct mlx5_ifc_default_timeout_bits tear_down_to; 3113 3114 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3115 3116 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3117 3118 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3119 3120 u8 reserved_at_1c0[0x40]; 3121 }; 3122 3123 enum { 3124 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3125 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3126 }; 3127 3128 struct mlx5_ifc_cq_error_bits { 3129 u8 reserved_at_0[0x8]; 3130 u8 cqn[0x18]; 3131 3132 u8 reserved_at_20[0x20]; 3133 3134 u8 reserved_at_40[0x18]; 3135 u8 syndrome[0x8]; 3136 3137 u8 reserved_at_60[0x80]; 3138 }; 3139 3140 struct mlx5_ifc_rdma_page_fault_event_bits { 3141 u8 bytes_committed[0x20]; 3142 3143 u8 r_key[0x20]; 3144 3145 u8 reserved_at_40[0x10]; 3146 u8 packet_len[0x10]; 3147 3148 u8 rdma_op_len[0x20]; 3149 3150 u8 rdma_va[0x40]; 3151 3152 u8 reserved_at_c0[0x5]; 3153 u8 rdma[0x1]; 3154 u8 write[0x1]; 3155 u8 requestor[0x1]; 3156 u8 qp_number[0x18]; 3157 }; 3158 3159 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3160 u8 bytes_committed[0x20]; 3161 3162 u8 reserved_at_20[0x10]; 3163 u8 wqe_index[0x10]; 3164 3165 u8 reserved_at_40[0x10]; 3166 u8 len[0x10]; 3167 3168 u8 reserved_at_60[0x60]; 3169 3170 u8 reserved_at_c0[0x5]; 3171 u8 rdma[0x1]; 3172 u8 write_read[0x1]; 3173 u8 requestor[0x1]; 3174 u8 qpn[0x18]; 3175 }; 3176 3177 struct mlx5_ifc_qp_events_bits { 3178 u8 reserved_at_0[0xa0]; 3179 3180 u8 type[0x8]; 3181 u8 reserved_at_a8[0x18]; 3182 3183 u8 reserved_at_c0[0x8]; 3184 u8 qpn_rqn_sqn[0x18]; 3185 }; 3186 3187 struct mlx5_ifc_dct_events_bits { 3188 u8 reserved_at_0[0xc0]; 3189 3190 u8 reserved_at_c0[0x8]; 3191 u8 dct_number[0x18]; 3192 }; 3193 3194 struct mlx5_ifc_comp_event_bits { 3195 u8 reserved_at_0[0xc0]; 3196 3197 u8 reserved_at_c0[0x8]; 3198 u8 cq_number[0x18]; 3199 }; 3200 3201 enum { 3202 MLX5_QPC_STATE_RST = 0x0, 3203 MLX5_QPC_STATE_INIT = 0x1, 3204 MLX5_QPC_STATE_RTR = 0x2, 3205 MLX5_QPC_STATE_RTS = 0x3, 3206 MLX5_QPC_STATE_SQER = 0x4, 3207 MLX5_QPC_STATE_ERR = 0x6, 3208 MLX5_QPC_STATE_SQD = 0x7, 3209 MLX5_QPC_STATE_SUSPENDED = 0x9, 3210 }; 3211 3212 enum { 3213 MLX5_QPC_ST_RC = 0x0, 3214 MLX5_QPC_ST_UC = 0x1, 3215 MLX5_QPC_ST_UD = 0x2, 3216 MLX5_QPC_ST_XRC = 0x3, 3217 MLX5_QPC_ST_DCI = 0x5, 3218 MLX5_QPC_ST_QP0 = 0x7, 3219 MLX5_QPC_ST_QP1 = 0x8, 3220 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3221 MLX5_QPC_ST_REG_UMR = 0xc, 3222 }; 3223 3224 enum { 3225 MLX5_QPC_PM_STATE_ARMED = 0x0, 3226 MLX5_QPC_PM_STATE_REARM = 0x1, 3227 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3228 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3229 }; 3230 3231 enum { 3232 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3233 }; 3234 3235 enum { 3236 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3237 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3238 }; 3239 3240 enum { 3241 MLX5_QPC_MTU_256_BYTES = 0x1, 3242 MLX5_QPC_MTU_512_BYTES = 0x2, 3243 MLX5_QPC_MTU_1K_BYTES = 0x3, 3244 MLX5_QPC_MTU_2K_BYTES = 0x4, 3245 MLX5_QPC_MTU_4K_BYTES = 0x5, 3246 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3247 }; 3248 3249 enum { 3250 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3251 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3252 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3253 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3254 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3255 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3256 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3257 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3258 }; 3259 3260 enum { 3261 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3262 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3263 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3264 }; 3265 3266 enum { 3267 MLX5_QPC_CS_RES_DISABLE = 0x0, 3268 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3269 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3270 }; 3271 3272 enum { 3273 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3274 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3275 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3276 }; 3277 3278 struct mlx5_ifc_qpc_bits { 3279 u8 state[0x4]; 3280 u8 lag_tx_port_affinity[0x4]; 3281 u8 st[0x8]; 3282 u8 reserved_at_10[0x2]; 3283 u8 isolate_vl_tc[0x1]; 3284 u8 pm_state[0x2]; 3285 u8 reserved_at_15[0x1]; 3286 u8 req_e2e_credit_mode[0x2]; 3287 u8 offload_type[0x4]; 3288 u8 end_padding_mode[0x2]; 3289 u8 reserved_at_1e[0x2]; 3290 3291 u8 wq_signature[0x1]; 3292 u8 block_lb_mc[0x1]; 3293 u8 atomic_like_write_en[0x1]; 3294 u8 latency_sensitive[0x1]; 3295 u8 reserved_at_24[0x1]; 3296 u8 drain_sigerr[0x1]; 3297 u8 reserved_at_26[0x2]; 3298 u8 pd[0x18]; 3299 3300 u8 mtu[0x3]; 3301 u8 log_msg_max[0x5]; 3302 u8 reserved_at_48[0x1]; 3303 u8 log_rq_size[0x4]; 3304 u8 log_rq_stride[0x3]; 3305 u8 no_sq[0x1]; 3306 u8 log_sq_size[0x4]; 3307 u8 reserved_at_55[0x1]; 3308 u8 retry_mode[0x2]; 3309 u8 ts_format[0x2]; 3310 u8 reserved_at_5a[0x1]; 3311 u8 rlky[0x1]; 3312 u8 ulp_stateless_offload_mode[0x4]; 3313 3314 u8 counter_set_id[0x8]; 3315 u8 uar_page[0x18]; 3316 3317 u8 reserved_at_80[0x8]; 3318 u8 user_index[0x18]; 3319 3320 u8 reserved_at_a0[0x3]; 3321 u8 log_page_size[0x5]; 3322 u8 remote_qpn[0x18]; 3323 3324 struct mlx5_ifc_ads_bits primary_address_path; 3325 3326 struct mlx5_ifc_ads_bits secondary_address_path; 3327 3328 u8 log_ack_req_freq[0x4]; 3329 u8 reserved_at_384[0x4]; 3330 u8 log_sra_max[0x3]; 3331 u8 reserved_at_38b[0x2]; 3332 u8 retry_count[0x3]; 3333 u8 rnr_retry[0x3]; 3334 u8 reserved_at_393[0x1]; 3335 u8 fre[0x1]; 3336 u8 cur_rnr_retry[0x3]; 3337 u8 cur_retry_count[0x3]; 3338 u8 reserved_at_39b[0x5]; 3339 3340 u8 reserved_at_3a0[0x20]; 3341 3342 u8 reserved_at_3c0[0x8]; 3343 u8 next_send_psn[0x18]; 3344 3345 u8 reserved_at_3e0[0x3]; 3346 u8 log_num_dci_stream_channels[0x5]; 3347 u8 cqn_snd[0x18]; 3348 3349 u8 reserved_at_400[0x3]; 3350 u8 log_num_dci_errored_streams[0x5]; 3351 u8 deth_sqpn[0x18]; 3352 3353 u8 reserved_at_420[0x20]; 3354 3355 u8 reserved_at_440[0x8]; 3356 u8 last_acked_psn[0x18]; 3357 3358 u8 reserved_at_460[0x8]; 3359 u8 ssn[0x18]; 3360 3361 u8 reserved_at_480[0x8]; 3362 u8 log_rra_max[0x3]; 3363 u8 reserved_at_48b[0x1]; 3364 u8 atomic_mode[0x4]; 3365 u8 rre[0x1]; 3366 u8 rwe[0x1]; 3367 u8 rae[0x1]; 3368 u8 reserved_at_493[0x1]; 3369 u8 page_offset[0x6]; 3370 u8 reserved_at_49a[0x3]; 3371 u8 cd_slave_receive[0x1]; 3372 u8 cd_slave_send[0x1]; 3373 u8 cd_master[0x1]; 3374 3375 u8 reserved_at_4a0[0x3]; 3376 u8 min_rnr_nak[0x5]; 3377 u8 next_rcv_psn[0x18]; 3378 3379 u8 reserved_at_4c0[0x8]; 3380 u8 xrcd[0x18]; 3381 3382 u8 reserved_at_4e0[0x8]; 3383 u8 cqn_rcv[0x18]; 3384 3385 u8 dbr_addr[0x40]; 3386 3387 u8 q_key[0x20]; 3388 3389 u8 reserved_at_560[0x5]; 3390 u8 rq_type[0x3]; 3391 u8 srqn_rmpn_xrqn[0x18]; 3392 3393 u8 reserved_at_580[0x8]; 3394 u8 rmsn[0x18]; 3395 3396 u8 hw_sq_wqebb_counter[0x10]; 3397 u8 sw_sq_wqebb_counter[0x10]; 3398 3399 u8 hw_rq_counter[0x20]; 3400 3401 u8 sw_rq_counter[0x20]; 3402 3403 u8 reserved_at_600[0x20]; 3404 3405 u8 reserved_at_620[0xf]; 3406 u8 cgs[0x1]; 3407 u8 cs_req[0x8]; 3408 u8 cs_res[0x8]; 3409 3410 u8 dc_access_key[0x40]; 3411 3412 u8 reserved_at_680[0x3]; 3413 u8 dbr_umem_valid[0x1]; 3414 3415 u8 reserved_at_684[0xbc]; 3416 }; 3417 3418 struct mlx5_ifc_roce_addr_layout_bits { 3419 u8 source_l3_address[16][0x8]; 3420 3421 u8 reserved_at_80[0x3]; 3422 u8 vlan_valid[0x1]; 3423 u8 vlan_id[0xc]; 3424 u8 source_mac_47_32[0x10]; 3425 3426 u8 source_mac_31_0[0x20]; 3427 3428 u8 reserved_at_c0[0x14]; 3429 u8 roce_l3_type[0x4]; 3430 u8 roce_version[0x8]; 3431 3432 u8 reserved_at_e0[0x20]; 3433 }; 3434 3435 struct mlx5_ifc_shampo_cap_bits { 3436 u8 reserved_at_0[0x3]; 3437 u8 shampo_log_max_reservation_size[0x5]; 3438 u8 reserved_at_8[0x3]; 3439 u8 shampo_log_min_reservation_size[0x5]; 3440 u8 shampo_min_mss_size[0x10]; 3441 3442 u8 reserved_at_20[0x3]; 3443 u8 shampo_max_log_headers_entry_size[0x5]; 3444 u8 reserved_at_28[0x18]; 3445 3446 u8 reserved_at_40[0x7c0]; 3447 }; 3448 3449 struct mlx5_ifc_crypto_cap_bits { 3450 u8 reserved_at_0[0x3]; 3451 u8 synchronize_dek[0x1]; 3452 u8 int_kek_manual[0x1]; 3453 u8 int_kek_auto[0x1]; 3454 u8 reserved_at_6[0x1a]; 3455 3456 u8 reserved_at_20[0x3]; 3457 u8 log_dek_max_alloc[0x5]; 3458 u8 reserved_at_28[0x3]; 3459 u8 log_max_num_deks[0x5]; 3460 u8 reserved_at_30[0x10]; 3461 3462 u8 reserved_at_40[0x20]; 3463 3464 u8 reserved_at_60[0x3]; 3465 u8 log_dek_granularity[0x5]; 3466 u8 reserved_at_68[0x3]; 3467 u8 log_max_num_int_kek[0x5]; 3468 u8 sw_wrapped_dek[0x10]; 3469 3470 u8 reserved_at_80[0x780]; 3471 }; 3472 3473 union mlx5_ifc_hca_cap_union_bits { 3474 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3475 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3476 struct mlx5_ifc_odp_cap_bits odp_cap; 3477 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3478 struct mlx5_ifc_roce_cap_bits roce_cap; 3479 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3480 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3481 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3482 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3483 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3484 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3485 struct mlx5_ifc_qos_cap_bits qos_cap; 3486 struct mlx5_ifc_debug_cap_bits debug_cap; 3487 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3488 struct mlx5_ifc_tls_cap_bits tls_cap; 3489 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3490 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3491 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3492 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3493 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3494 u8 reserved_at_0[0x8000]; 3495 }; 3496 3497 enum { 3498 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3499 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3500 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3501 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3502 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3503 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3504 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3505 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3506 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3507 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3508 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3509 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3510 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3511 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3512 }; 3513 3514 enum { 3515 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3516 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3517 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3518 }; 3519 3520 enum { 3521 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3522 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3523 }; 3524 3525 struct mlx5_ifc_vlan_bits { 3526 u8 ethtype[0x10]; 3527 u8 prio[0x3]; 3528 u8 cfi[0x1]; 3529 u8 vid[0xc]; 3530 }; 3531 3532 enum { 3533 MLX5_FLOW_METER_COLOR_RED = 0x0, 3534 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3535 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3536 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3537 }; 3538 3539 enum { 3540 MLX5_EXE_ASO_FLOW_METER = 0x2, 3541 }; 3542 3543 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3544 u8 return_reg_id[0x4]; 3545 u8 aso_type[0x4]; 3546 u8 reserved_at_8[0x14]; 3547 u8 action[0x1]; 3548 u8 init_color[0x2]; 3549 u8 meter_id[0x1]; 3550 }; 3551 3552 union mlx5_ifc_exe_aso_ctrl { 3553 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3554 }; 3555 3556 struct mlx5_ifc_execute_aso_bits { 3557 u8 valid[0x1]; 3558 u8 reserved_at_1[0x7]; 3559 u8 aso_object_id[0x18]; 3560 3561 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3562 }; 3563 3564 struct mlx5_ifc_flow_context_bits { 3565 struct mlx5_ifc_vlan_bits push_vlan; 3566 3567 u8 group_id[0x20]; 3568 3569 u8 reserved_at_40[0x8]; 3570 u8 flow_tag[0x18]; 3571 3572 u8 reserved_at_60[0x10]; 3573 u8 action[0x10]; 3574 3575 u8 extended_destination[0x1]; 3576 u8 reserved_at_81[0x1]; 3577 u8 flow_source[0x2]; 3578 u8 encrypt_decrypt_type[0x4]; 3579 u8 destination_list_size[0x18]; 3580 3581 u8 reserved_at_a0[0x8]; 3582 u8 flow_counter_list_size[0x18]; 3583 3584 u8 packet_reformat_id[0x20]; 3585 3586 u8 modify_header_id[0x20]; 3587 3588 struct mlx5_ifc_vlan_bits push_vlan_2; 3589 3590 u8 encrypt_decrypt_obj_id[0x20]; 3591 u8 reserved_at_140[0xc0]; 3592 3593 struct mlx5_ifc_fte_match_param_bits match_value; 3594 3595 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3596 3597 u8 reserved_at_1300[0x500]; 3598 3599 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3600 }; 3601 3602 enum { 3603 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3604 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3605 }; 3606 3607 struct mlx5_ifc_xrc_srqc_bits { 3608 u8 state[0x4]; 3609 u8 log_xrc_srq_size[0x4]; 3610 u8 reserved_at_8[0x18]; 3611 3612 u8 wq_signature[0x1]; 3613 u8 cont_srq[0x1]; 3614 u8 reserved_at_22[0x1]; 3615 u8 rlky[0x1]; 3616 u8 basic_cyclic_rcv_wqe[0x1]; 3617 u8 log_rq_stride[0x3]; 3618 u8 xrcd[0x18]; 3619 3620 u8 page_offset[0x6]; 3621 u8 reserved_at_46[0x1]; 3622 u8 dbr_umem_valid[0x1]; 3623 u8 cqn[0x18]; 3624 3625 u8 reserved_at_60[0x20]; 3626 3627 u8 user_index_equal_xrc_srqn[0x1]; 3628 u8 reserved_at_81[0x1]; 3629 u8 log_page_size[0x6]; 3630 u8 user_index[0x18]; 3631 3632 u8 reserved_at_a0[0x20]; 3633 3634 u8 reserved_at_c0[0x8]; 3635 u8 pd[0x18]; 3636 3637 u8 lwm[0x10]; 3638 u8 wqe_cnt[0x10]; 3639 3640 u8 reserved_at_100[0x40]; 3641 3642 u8 db_record_addr_h[0x20]; 3643 3644 u8 db_record_addr_l[0x1e]; 3645 u8 reserved_at_17e[0x2]; 3646 3647 u8 reserved_at_180[0x80]; 3648 }; 3649 3650 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3651 u8 counter_error_queues[0x20]; 3652 3653 u8 total_error_queues[0x20]; 3654 3655 u8 send_queue_priority_update_flow[0x20]; 3656 3657 u8 reserved_at_60[0x20]; 3658 3659 u8 nic_receive_steering_discard[0x40]; 3660 3661 u8 receive_discard_vport_down[0x40]; 3662 3663 u8 transmit_discard_vport_down[0x40]; 3664 3665 u8 async_eq_overrun[0x20]; 3666 3667 u8 comp_eq_overrun[0x20]; 3668 3669 u8 reserved_at_180[0x20]; 3670 3671 u8 invalid_command[0x20]; 3672 3673 u8 quota_exceeded_command[0x20]; 3674 3675 u8 internal_rq_out_of_buffer[0x20]; 3676 3677 u8 cq_overrun[0x20]; 3678 3679 u8 eth_wqe_too_small[0x20]; 3680 3681 u8 reserved_at_220[0xc0]; 3682 3683 u8 generated_pkt_steering_fail[0x40]; 3684 3685 u8 handled_pkt_steering_fail[0x40]; 3686 3687 u8 reserved_at_360[0xc80]; 3688 }; 3689 3690 struct mlx5_ifc_traffic_counter_bits { 3691 u8 packets[0x40]; 3692 3693 u8 octets[0x40]; 3694 }; 3695 3696 struct mlx5_ifc_tisc_bits { 3697 u8 strict_lag_tx_port_affinity[0x1]; 3698 u8 tls_en[0x1]; 3699 u8 reserved_at_2[0x2]; 3700 u8 lag_tx_port_affinity[0x04]; 3701 3702 u8 reserved_at_8[0x4]; 3703 u8 prio[0x4]; 3704 u8 reserved_at_10[0x10]; 3705 3706 u8 reserved_at_20[0x100]; 3707 3708 u8 reserved_at_120[0x8]; 3709 u8 transport_domain[0x18]; 3710 3711 u8 reserved_at_140[0x8]; 3712 u8 underlay_qpn[0x18]; 3713 3714 u8 reserved_at_160[0x8]; 3715 u8 pd[0x18]; 3716 3717 u8 reserved_at_180[0x380]; 3718 }; 3719 3720 enum { 3721 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3722 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3723 }; 3724 3725 enum { 3726 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3727 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3728 }; 3729 3730 enum { 3731 MLX5_RX_HASH_FN_NONE = 0x0, 3732 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3733 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3734 }; 3735 3736 enum { 3737 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3738 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3739 }; 3740 3741 struct mlx5_ifc_tirc_bits { 3742 u8 reserved_at_0[0x20]; 3743 3744 u8 disp_type[0x4]; 3745 u8 tls_en[0x1]; 3746 u8 reserved_at_25[0x1b]; 3747 3748 u8 reserved_at_40[0x40]; 3749 3750 u8 reserved_at_80[0x4]; 3751 u8 lro_timeout_period_usecs[0x10]; 3752 u8 packet_merge_mask[0x4]; 3753 u8 lro_max_ip_payload_size[0x8]; 3754 3755 u8 reserved_at_a0[0x40]; 3756 3757 u8 reserved_at_e0[0x8]; 3758 u8 inline_rqn[0x18]; 3759 3760 u8 rx_hash_symmetric[0x1]; 3761 u8 reserved_at_101[0x1]; 3762 u8 tunneled_offload_en[0x1]; 3763 u8 reserved_at_103[0x5]; 3764 u8 indirect_table[0x18]; 3765 3766 u8 rx_hash_fn[0x4]; 3767 u8 reserved_at_124[0x2]; 3768 u8 self_lb_block[0x2]; 3769 u8 transport_domain[0x18]; 3770 3771 u8 rx_hash_toeplitz_key[10][0x20]; 3772 3773 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3774 3775 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3776 3777 u8 reserved_at_2c0[0x4c0]; 3778 }; 3779 3780 enum { 3781 MLX5_SRQC_STATE_GOOD = 0x0, 3782 MLX5_SRQC_STATE_ERROR = 0x1, 3783 }; 3784 3785 struct mlx5_ifc_srqc_bits { 3786 u8 state[0x4]; 3787 u8 log_srq_size[0x4]; 3788 u8 reserved_at_8[0x18]; 3789 3790 u8 wq_signature[0x1]; 3791 u8 cont_srq[0x1]; 3792 u8 reserved_at_22[0x1]; 3793 u8 rlky[0x1]; 3794 u8 reserved_at_24[0x1]; 3795 u8 log_rq_stride[0x3]; 3796 u8 xrcd[0x18]; 3797 3798 u8 page_offset[0x6]; 3799 u8 reserved_at_46[0x2]; 3800 u8 cqn[0x18]; 3801 3802 u8 reserved_at_60[0x20]; 3803 3804 u8 reserved_at_80[0x2]; 3805 u8 log_page_size[0x6]; 3806 u8 reserved_at_88[0x18]; 3807 3808 u8 reserved_at_a0[0x20]; 3809 3810 u8 reserved_at_c0[0x8]; 3811 u8 pd[0x18]; 3812 3813 u8 lwm[0x10]; 3814 u8 wqe_cnt[0x10]; 3815 3816 u8 reserved_at_100[0x40]; 3817 3818 u8 dbr_addr[0x40]; 3819 3820 u8 reserved_at_180[0x80]; 3821 }; 3822 3823 enum { 3824 MLX5_SQC_STATE_RST = 0x0, 3825 MLX5_SQC_STATE_RDY = 0x1, 3826 MLX5_SQC_STATE_ERR = 0x3, 3827 }; 3828 3829 struct mlx5_ifc_sqc_bits { 3830 u8 rlky[0x1]; 3831 u8 cd_master[0x1]; 3832 u8 fre[0x1]; 3833 u8 flush_in_error_en[0x1]; 3834 u8 allow_multi_pkt_send_wqe[0x1]; 3835 u8 min_wqe_inline_mode[0x3]; 3836 u8 state[0x4]; 3837 u8 reg_umr[0x1]; 3838 u8 allow_swp[0x1]; 3839 u8 hairpin[0x1]; 3840 u8 reserved_at_f[0xb]; 3841 u8 ts_format[0x2]; 3842 u8 reserved_at_1c[0x4]; 3843 3844 u8 reserved_at_20[0x8]; 3845 u8 user_index[0x18]; 3846 3847 u8 reserved_at_40[0x8]; 3848 u8 cqn[0x18]; 3849 3850 u8 reserved_at_60[0x8]; 3851 u8 hairpin_peer_rq[0x18]; 3852 3853 u8 reserved_at_80[0x10]; 3854 u8 hairpin_peer_vhca[0x10]; 3855 3856 u8 reserved_at_a0[0x20]; 3857 3858 u8 reserved_at_c0[0x8]; 3859 u8 ts_cqe_to_dest_cqn[0x18]; 3860 3861 u8 reserved_at_e0[0x10]; 3862 u8 packet_pacing_rate_limit_index[0x10]; 3863 u8 tis_lst_sz[0x10]; 3864 u8 qos_queue_group_id[0x10]; 3865 3866 u8 reserved_at_120[0x40]; 3867 3868 u8 reserved_at_160[0x8]; 3869 u8 tis_num_0[0x18]; 3870 3871 struct mlx5_ifc_wq_bits wq; 3872 }; 3873 3874 enum { 3875 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3876 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3877 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3878 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3879 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3880 }; 3881 3882 enum { 3883 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3884 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3885 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3886 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3887 }; 3888 3889 struct mlx5_ifc_scheduling_context_bits { 3890 u8 element_type[0x8]; 3891 u8 reserved_at_8[0x18]; 3892 3893 u8 element_attributes[0x20]; 3894 3895 u8 parent_element_id[0x20]; 3896 3897 u8 reserved_at_60[0x40]; 3898 3899 u8 bw_share[0x20]; 3900 3901 u8 max_average_bw[0x20]; 3902 3903 u8 reserved_at_e0[0x120]; 3904 }; 3905 3906 struct mlx5_ifc_rqtc_bits { 3907 u8 reserved_at_0[0xa0]; 3908 3909 u8 reserved_at_a0[0x5]; 3910 u8 list_q_type[0x3]; 3911 u8 reserved_at_a8[0x8]; 3912 u8 rqt_max_size[0x10]; 3913 3914 u8 rq_vhca_id_format[0x1]; 3915 u8 reserved_at_c1[0xf]; 3916 u8 rqt_actual_size[0x10]; 3917 3918 u8 reserved_at_e0[0x6a0]; 3919 3920 struct mlx5_ifc_rq_num_bits rq_num[]; 3921 }; 3922 3923 enum { 3924 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3925 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3926 }; 3927 3928 enum { 3929 MLX5_RQC_STATE_RST = 0x0, 3930 MLX5_RQC_STATE_RDY = 0x1, 3931 MLX5_RQC_STATE_ERR = 0x3, 3932 }; 3933 3934 enum { 3935 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3936 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3937 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3938 }; 3939 3940 enum { 3941 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3942 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3943 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3944 }; 3945 3946 struct mlx5_ifc_rqc_bits { 3947 u8 rlky[0x1]; 3948 u8 delay_drop_en[0x1]; 3949 u8 scatter_fcs[0x1]; 3950 u8 vsd[0x1]; 3951 u8 mem_rq_type[0x4]; 3952 u8 state[0x4]; 3953 u8 reserved_at_c[0x1]; 3954 u8 flush_in_error_en[0x1]; 3955 u8 hairpin[0x1]; 3956 u8 reserved_at_f[0xb]; 3957 u8 ts_format[0x2]; 3958 u8 reserved_at_1c[0x4]; 3959 3960 u8 reserved_at_20[0x8]; 3961 u8 user_index[0x18]; 3962 3963 u8 reserved_at_40[0x8]; 3964 u8 cqn[0x18]; 3965 3966 u8 counter_set_id[0x8]; 3967 u8 reserved_at_68[0x18]; 3968 3969 u8 reserved_at_80[0x8]; 3970 u8 rmpn[0x18]; 3971 3972 u8 reserved_at_a0[0x8]; 3973 u8 hairpin_peer_sq[0x18]; 3974 3975 u8 reserved_at_c0[0x10]; 3976 u8 hairpin_peer_vhca[0x10]; 3977 3978 u8 reserved_at_e0[0x46]; 3979 u8 shampo_no_match_alignment_granularity[0x2]; 3980 u8 reserved_at_128[0x6]; 3981 u8 shampo_match_criteria_type[0x2]; 3982 u8 reservation_timeout[0x10]; 3983 3984 u8 reserved_at_140[0x40]; 3985 3986 struct mlx5_ifc_wq_bits wq; 3987 }; 3988 3989 enum { 3990 MLX5_RMPC_STATE_RDY = 0x1, 3991 MLX5_RMPC_STATE_ERR = 0x3, 3992 }; 3993 3994 struct mlx5_ifc_rmpc_bits { 3995 u8 reserved_at_0[0x8]; 3996 u8 state[0x4]; 3997 u8 reserved_at_c[0x14]; 3998 3999 u8 basic_cyclic_rcv_wqe[0x1]; 4000 u8 reserved_at_21[0x1f]; 4001 4002 u8 reserved_at_40[0x140]; 4003 4004 struct mlx5_ifc_wq_bits wq; 4005 }; 4006 4007 enum { 4008 VHCA_ID_TYPE_HW = 0, 4009 VHCA_ID_TYPE_SW = 1, 4010 }; 4011 4012 struct mlx5_ifc_nic_vport_context_bits { 4013 u8 reserved_at_0[0x5]; 4014 u8 min_wqe_inline_mode[0x3]; 4015 u8 reserved_at_8[0x15]; 4016 u8 disable_mc_local_lb[0x1]; 4017 u8 disable_uc_local_lb[0x1]; 4018 u8 roce_en[0x1]; 4019 4020 u8 arm_change_event[0x1]; 4021 u8 reserved_at_21[0x1a]; 4022 u8 event_on_mtu[0x1]; 4023 u8 event_on_promisc_change[0x1]; 4024 u8 event_on_vlan_change[0x1]; 4025 u8 event_on_mc_address_change[0x1]; 4026 u8 event_on_uc_address_change[0x1]; 4027 4028 u8 vhca_id_type[0x1]; 4029 u8 reserved_at_41[0xb]; 4030 u8 affiliation_criteria[0x4]; 4031 u8 affiliated_vhca_id[0x10]; 4032 4033 u8 reserved_at_60[0xd0]; 4034 4035 u8 mtu[0x10]; 4036 4037 u8 system_image_guid[0x40]; 4038 u8 port_guid[0x40]; 4039 u8 node_guid[0x40]; 4040 4041 u8 reserved_at_200[0x140]; 4042 u8 qkey_violation_counter[0x10]; 4043 u8 reserved_at_350[0x430]; 4044 4045 u8 promisc_uc[0x1]; 4046 u8 promisc_mc[0x1]; 4047 u8 promisc_all[0x1]; 4048 u8 reserved_at_783[0x2]; 4049 u8 allowed_list_type[0x3]; 4050 u8 reserved_at_788[0xc]; 4051 u8 allowed_list_size[0xc]; 4052 4053 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4054 4055 u8 reserved_at_7e0[0x20]; 4056 4057 u8 current_uc_mac_address[][0x40]; 4058 }; 4059 4060 enum { 4061 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4062 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4063 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4064 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4065 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4066 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4067 }; 4068 4069 struct mlx5_ifc_mkc_bits { 4070 u8 reserved_at_0[0x1]; 4071 u8 free[0x1]; 4072 u8 reserved_at_2[0x1]; 4073 u8 access_mode_4_2[0x3]; 4074 u8 reserved_at_6[0x7]; 4075 u8 relaxed_ordering_write[0x1]; 4076 u8 reserved_at_e[0x1]; 4077 u8 small_fence_on_rdma_read_response[0x1]; 4078 u8 umr_en[0x1]; 4079 u8 a[0x1]; 4080 u8 rw[0x1]; 4081 u8 rr[0x1]; 4082 u8 lw[0x1]; 4083 u8 lr[0x1]; 4084 u8 access_mode_1_0[0x2]; 4085 u8 reserved_at_18[0x2]; 4086 u8 ma_translation_mode[0x2]; 4087 u8 reserved_at_1c[0x4]; 4088 4089 u8 qpn[0x18]; 4090 u8 mkey_7_0[0x8]; 4091 4092 u8 reserved_at_40[0x20]; 4093 4094 u8 length64[0x1]; 4095 u8 bsf_en[0x1]; 4096 u8 sync_umr[0x1]; 4097 u8 reserved_at_63[0x2]; 4098 u8 expected_sigerr_count[0x1]; 4099 u8 reserved_at_66[0x1]; 4100 u8 en_rinval[0x1]; 4101 u8 pd[0x18]; 4102 4103 u8 start_addr[0x40]; 4104 4105 u8 len[0x40]; 4106 4107 u8 bsf_octword_size[0x20]; 4108 4109 u8 reserved_at_120[0x80]; 4110 4111 u8 translations_octword_size[0x20]; 4112 4113 u8 reserved_at_1c0[0x19]; 4114 u8 relaxed_ordering_read[0x1]; 4115 u8 reserved_at_1d9[0x1]; 4116 u8 log_page_size[0x5]; 4117 4118 u8 reserved_at_1e0[0x20]; 4119 }; 4120 4121 struct mlx5_ifc_pkey_bits { 4122 u8 reserved_at_0[0x10]; 4123 u8 pkey[0x10]; 4124 }; 4125 4126 struct mlx5_ifc_array128_auto_bits { 4127 u8 array128_auto[16][0x8]; 4128 }; 4129 4130 struct mlx5_ifc_hca_vport_context_bits { 4131 u8 field_select[0x20]; 4132 4133 u8 reserved_at_20[0xe0]; 4134 4135 u8 sm_virt_aware[0x1]; 4136 u8 has_smi[0x1]; 4137 u8 has_raw[0x1]; 4138 u8 grh_required[0x1]; 4139 u8 reserved_at_104[0xc]; 4140 u8 port_physical_state[0x4]; 4141 u8 vport_state_policy[0x4]; 4142 u8 port_state[0x4]; 4143 u8 vport_state[0x4]; 4144 4145 u8 reserved_at_120[0x20]; 4146 4147 u8 system_image_guid[0x40]; 4148 4149 u8 port_guid[0x40]; 4150 4151 u8 node_guid[0x40]; 4152 4153 u8 cap_mask1[0x20]; 4154 4155 u8 cap_mask1_field_select[0x20]; 4156 4157 u8 cap_mask2[0x20]; 4158 4159 u8 cap_mask2_field_select[0x20]; 4160 4161 u8 reserved_at_280[0x80]; 4162 4163 u8 lid[0x10]; 4164 u8 reserved_at_310[0x4]; 4165 u8 init_type_reply[0x4]; 4166 u8 lmc[0x3]; 4167 u8 subnet_timeout[0x5]; 4168 4169 u8 sm_lid[0x10]; 4170 u8 sm_sl[0x4]; 4171 u8 reserved_at_334[0xc]; 4172 4173 u8 qkey_violation_counter[0x10]; 4174 u8 pkey_violation_counter[0x10]; 4175 4176 u8 reserved_at_360[0xca0]; 4177 }; 4178 4179 struct mlx5_ifc_esw_vport_context_bits { 4180 u8 fdb_to_vport_reg_c[0x1]; 4181 u8 reserved_at_1[0x2]; 4182 u8 vport_svlan_strip[0x1]; 4183 u8 vport_cvlan_strip[0x1]; 4184 u8 vport_svlan_insert[0x1]; 4185 u8 vport_cvlan_insert[0x2]; 4186 u8 fdb_to_vport_reg_c_id[0x8]; 4187 u8 reserved_at_10[0x10]; 4188 4189 u8 reserved_at_20[0x20]; 4190 4191 u8 svlan_cfi[0x1]; 4192 u8 svlan_pcp[0x3]; 4193 u8 svlan_id[0xc]; 4194 u8 cvlan_cfi[0x1]; 4195 u8 cvlan_pcp[0x3]; 4196 u8 cvlan_id[0xc]; 4197 4198 u8 reserved_at_60[0x720]; 4199 4200 u8 sw_steering_vport_icm_address_rx[0x40]; 4201 4202 u8 sw_steering_vport_icm_address_tx[0x40]; 4203 }; 4204 4205 enum { 4206 MLX5_EQC_STATUS_OK = 0x0, 4207 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4208 }; 4209 4210 enum { 4211 MLX5_EQC_ST_ARMED = 0x9, 4212 MLX5_EQC_ST_FIRED = 0xa, 4213 }; 4214 4215 struct mlx5_ifc_eqc_bits { 4216 u8 status[0x4]; 4217 u8 reserved_at_4[0x9]; 4218 u8 ec[0x1]; 4219 u8 oi[0x1]; 4220 u8 reserved_at_f[0x5]; 4221 u8 st[0x4]; 4222 u8 reserved_at_18[0x8]; 4223 4224 u8 reserved_at_20[0x20]; 4225 4226 u8 reserved_at_40[0x14]; 4227 u8 page_offset[0x6]; 4228 u8 reserved_at_5a[0x6]; 4229 4230 u8 reserved_at_60[0x3]; 4231 u8 log_eq_size[0x5]; 4232 u8 uar_page[0x18]; 4233 4234 u8 reserved_at_80[0x20]; 4235 4236 u8 reserved_at_a0[0x14]; 4237 u8 intr[0xc]; 4238 4239 u8 reserved_at_c0[0x3]; 4240 u8 log_page_size[0x5]; 4241 u8 reserved_at_c8[0x18]; 4242 4243 u8 reserved_at_e0[0x60]; 4244 4245 u8 reserved_at_140[0x8]; 4246 u8 consumer_counter[0x18]; 4247 4248 u8 reserved_at_160[0x8]; 4249 u8 producer_counter[0x18]; 4250 4251 u8 reserved_at_180[0x80]; 4252 }; 4253 4254 enum { 4255 MLX5_DCTC_STATE_ACTIVE = 0x0, 4256 MLX5_DCTC_STATE_DRAINING = 0x1, 4257 MLX5_DCTC_STATE_DRAINED = 0x2, 4258 }; 4259 4260 enum { 4261 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4262 MLX5_DCTC_CS_RES_NA = 0x1, 4263 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4264 }; 4265 4266 enum { 4267 MLX5_DCTC_MTU_256_BYTES = 0x1, 4268 MLX5_DCTC_MTU_512_BYTES = 0x2, 4269 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4270 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4271 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4272 }; 4273 4274 struct mlx5_ifc_dctc_bits { 4275 u8 reserved_at_0[0x4]; 4276 u8 state[0x4]; 4277 u8 reserved_at_8[0x18]; 4278 4279 u8 reserved_at_20[0x8]; 4280 u8 user_index[0x18]; 4281 4282 u8 reserved_at_40[0x8]; 4283 u8 cqn[0x18]; 4284 4285 u8 counter_set_id[0x8]; 4286 u8 atomic_mode[0x4]; 4287 u8 rre[0x1]; 4288 u8 rwe[0x1]; 4289 u8 rae[0x1]; 4290 u8 atomic_like_write_en[0x1]; 4291 u8 latency_sensitive[0x1]; 4292 u8 rlky[0x1]; 4293 u8 free_ar[0x1]; 4294 u8 reserved_at_73[0xd]; 4295 4296 u8 reserved_at_80[0x8]; 4297 u8 cs_res[0x8]; 4298 u8 reserved_at_90[0x3]; 4299 u8 min_rnr_nak[0x5]; 4300 u8 reserved_at_98[0x8]; 4301 4302 u8 reserved_at_a0[0x8]; 4303 u8 srqn_xrqn[0x18]; 4304 4305 u8 reserved_at_c0[0x8]; 4306 u8 pd[0x18]; 4307 4308 u8 tclass[0x8]; 4309 u8 reserved_at_e8[0x4]; 4310 u8 flow_label[0x14]; 4311 4312 u8 dc_access_key[0x40]; 4313 4314 u8 reserved_at_140[0x5]; 4315 u8 mtu[0x3]; 4316 u8 port[0x8]; 4317 u8 pkey_index[0x10]; 4318 4319 u8 reserved_at_160[0x8]; 4320 u8 my_addr_index[0x8]; 4321 u8 reserved_at_170[0x8]; 4322 u8 hop_limit[0x8]; 4323 4324 u8 dc_access_key_violation_count[0x20]; 4325 4326 u8 reserved_at_1a0[0x14]; 4327 u8 dei_cfi[0x1]; 4328 u8 eth_prio[0x3]; 4329 u8 ecn[0x2]; 4330 u8 dscp[0x6]; 4331 4332 u8 reserved_at_1c0[0x20]; 4333 u8 ece[0x20]; 4334 }; 4335 4336 enum { 4337 MLX5_CQC_STATUS_OK = 0x0, 4338 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4339 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4340 }; 4341 4342 enum { 4343 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4344 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4345 }; 4346 4347 enum { 4348 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4349 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4350 MLX5_CQC_ST_FIRED = 0xa, 4351 }; 4352 4353 enum { 4354 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4355 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4356 MLX5_CQ_PERIOD_NUM_MODES 4357 }; 4358 4359 struct mlx5_ifc_cqc_bits { 4360 u8 status[0x4]; 4361 u8 reserved_at_4[0x2]; 4362 u8 dbr_umem_valid[0x1]; 4363 u8 apu_cq[0x1]; 4364 u8 cqe_sz[0x3]; 4365 u8 cc[0x1]; 4366 u8 reserved_at_c[0x1]; 4367 u8 scqe_break_moderation_en[0x1]; 4368 u8 oi[0x1]; 4369 u8 cq_period_mode[0x2]; 4370 u8 cqe_comp_en[0x1]; 4371 u8 mini_cqe_res_format[0x2]; 4372 u8 st[0x4]; 4373 u8 reserved_at_18[0x6]; 4374 u8 cqe_compression_layout[0x2]; 4375 4376 u8 reserved_at_20[0x20]; 4377 4378 u8 reserved_at_40[0x14]; 4379 u8 page_offset[0x6]; 4380 u8 reserved_at_5a[0x6]; 4381 4382 u8 reserved_at_60[0x3]; 4383 u8 log_cq_size[0x5]; 4384 u8 uar_page[0x18]; 4385 4386 u8 reserved_at_80[0x4]; 4387 u8 cq_period[0xc]; 4388 u8 cq_max_count[0x10]; 4389 4390 u8 c_eqn_or_apu_element[0x20]; 4391 4392 u8 reserved_at_c0[0x3]; 4393 u8 log_page_size[0x5]; 4394 u8 reserved_at_c8[0x18]; 4395 4396 u8 reserved_at_e0[0x20]; 4397 4398 u8 reserved_at_100[0x8]; 4399 u8 last_notified_index[0x18]; 4400 4401 u8 reserved_at_120[0x8]; 4402 u8 last_solicit_index[0x18]; 4403 4404 u8 reserved_at_140[0x8]; 4405 u8 consumer_counter[0x18]; 4406 4407 u8 reserved_at_160[0x8]; 4408 u8 producer_counter[0x18]; 4409 4410 u8 reserved_at_180[0x40]; 4411 4412 u8 dbr_addr[0x40]; 4413 }; 4414 4415 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4416 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4417 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4418 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4419 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4420 u8 reserved_at_0[0x800]; 4421 }; 4422 4423 struct mlx5_ifc_query_adapter_param_block_bits { 4424 u8 reserved_at_0[0xc0]; 4425 4426 u8 reserved_at_c0[0x8]; 4427 u8 ieee_vendor_id[0x18]; 4428 4429 u8 reserved_at_e0[0x10]; 4430 u8 vsd_vendor_id[0x10]; 4431 4432 u8 vsd[208][0x8]; 4433 4434 u8 vsd_contd_psid[16][0x8]; 4435 }; 4436 4437 enum { 4438 MLX5_XRQC_STATE_GOOD = 0x0, 4439 MLX5_XRQC_STATE_ERROR = 0x1, 4440 }; 4441 4442 enum { 4443 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4444 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4445 }; 4446 4447 enum { 4448 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4449 }; 4450 4451 struct mlx5_ifc_tag_matching_topology_context_bits { 4452 u8 log_matching_list_sz[0x4]; 4453 u8 reserved_at_4[0xc]; 4454 u8 append_next_index[0x10]; 4455 4456 u8 sw_phase_cnt[0x10]; 4457 u8 hw_phase_cnt[0x10]; 4458 4459 u8 reserved_at_40[0x40]; 4460 }; 4461 4462 struct mlx5_ifc_xrqc_bits { 4463 u8 state[0x4]; 4464 u8 rlkey[0x1]; 4465 u8 reserved_at_5[0xf]; 4466 u8 topology[0x4]; 4467 u8 reserved_at_18[0x4]; 4468 u8 offload[0x4]; 4469 4470 u8 reserved_at_20[0x8]; 4471 u8 user_index[0x18]; 4472 4473 u8 reserved_at_40[0x8]; 4474 u8 cqn[0x18]; 4475 4476 u8 reserved_at_60[0xa0]; 4477 4478 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4479 4480 u8 reserved_at_180[0x280]; 4481 4482 struct mlx5_ifc_wq_bits wq; 4483 }; 4484 4485 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4486 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4487 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4488 u8 reserved_at_0[0x20]; 4489 }; 4490 4491 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4492 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4493 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4494 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4495 u8 reserved_at_0[0x20]; 4496 }; 4497 4498 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4499 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4500 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4501 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4502 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4503 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4504 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4505 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4506 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4507 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4508 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4509 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4510 u8 reserved_at_0[0x7c0]; 4511 }; 4512 4513 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4514 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4515 u8 reserved_at_0[0x7c0]; 4516 }; 4517 4518 union mlx5_ifc_event_auto_bits { 4519 struct mlx5_ifc_comp_event_bits comp_event; 4520 struct mlx5_ifc_dct_events_bits dct_events; 4521 struct mlx5_ifc_qp_events_bits qp_events; 4522 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4523 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4524 struct mlx5_ifc_cq_error_bits cq_error; 4525 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4526 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4527 struct mlx5_ifc_gpio_event_bits gpio_event; 4528 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4529 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4530 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4531 u8 reserved_at_0[0xe0]; 4532 }; 4533 4534 struct mlx5_ifc_health_buffer_bits { 4535 u8 reserved_at_0[0x100]; 4536 4537 u8 assert_existptr[0x20]; 4538 4539 u8 assert_callra[0x20]; 4540 4541 u8 reserved_at_140[0x20]; 4542 4543 u8 time[0x20]; 4544 4545 u8 fw_version[0x20]; 4546 4547 u8 hw_id[0x20]; 4548 4549 u8 rfr[0x1]; 4550 u8 reserved_at_1c1[0x3]; 4551 u8 valid[0x1]; 4552 u8 severity[0x3]; 4553 u8 reserved_at_1c8[0x18]; 4554 4555 u8 irisc_index[0x8]; 4556 u8 synd[0x8]; 4557 u8 ext_synd[0x10]; 4558 }; 4559 4560 struct mlx5_ifc_register_loopback_control_bits { 4561 u8 no_lb[0x1]; 4562 u8 reserved_at_1[0x7]; 4563 u8 port[0x8]; 4564 u8 reserved_at_10[0x10]; 4565 4566 u8 reserved_at_20[0x60]; 4567 }; 4568 4569 struct mlx5_ifc_vport_tc_element_bits { 4570 u8 traffic_class[0x4]; 4571 u8 reserved_at_4[0xc]; 4572 u8 vport_number[0x10]; 4573 }; 4574 4575 struct mlx5_ifc_vport_element_bits { 4576 u8 reserved_at_0[0x10]; 4577 u8 vport_number[0x10]; 4578 }; 4579 4580 enum { 4581 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4582 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4583 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4584 }; 4585 4586 struct mlx5_ifc_tsar_element_bits { 4587 u8 reserved_at_0[0x8]; 4588 u8 tsar_type[0x8]; 4589 u8 reserved_at_10[0x10]; 4590 }; 4591 4592 enum { 4593 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4594 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4595 }; 4596 4597 struct mlx5_ifc_teardown_hca_out_bits { 4598 u8 status[0x8]; 4599 u8 reserved_at_8[0x18]; 4600 4601 u8 syndrome[0x20]; 4602 4603 u8 reserved_at_40[0x3f]; 4604 4605 u8 state[0x1]; 4606 }; 4607 4608 enum { 4609 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4610 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4611 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4612 }; 4613 4614 struct mlx5_ifc_teardown_hca_in_bits { 4615 u8 opcode[0x10]; 4616 u8 reserved_at_10[0x10]; 4617 4618 u8 reserved_at_20[0x10]; 4619 u8 op_mod[0x10]; 4620 4621 u8 reserved_at_40[0x10]; 4622 u8 profile[0x10]; 4623 4624 u8 reserved_at_60[0x20]; 4625 }; 4626 4627 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4628 u8 status[0x8]; 4629 u8 reserved_at_8[0x18]; 4630 4631 u8 syndrome[0x20]; 4632 4633 u8 reserved_at_40[0x40]; 4634 }; 4635 4636 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4637 u8 opcode[0x10]; 4638 u8 uid[0x10]; 4639 4640 u8 reserved_at_20[0x10]; 4641 u8 op_mod[0x10]; 4642 4643 u8 reserved_at_40[0x8]; 4644 u8 qpn[0x18]; 4645 4646 u8 reserved_at_60[0x20]; 4647 4648 u8 opt_param_mask[0x20]; 4649 4650 u8 reserved_at_a0[0x20]; 4651 4652 struct mlx5_ifc_qpc_bits qpc; 4653 4654 u8 reserved_at_800[0x80]; 4655 }; 4656 4657 struct mlx5_ifc_sqd2rts_qp_out_bits { 4658 u8 status[0x8]; 4659 u8 reserved_at_8[0x18]; 4660 4661 u8 syndrome[0x20]; 4662 4663 u8 reserved_at_40[0x40]; 4664 }; 4665 4666 struct mlx5_ifc_sqd2rts_qp_in_bits { 4667 u8 opcode[0x10]; 4668 u8 uid[0x10]; 4669 4670 u8 reserved_at_20[0x10]; 4671 u8 op_mod[0x10]; 4672 4673 u8 reserved_at_40[0x8]; 4674 u8 qpn[0x18]; 4675 4676 u8 reserved_at_60[0x20]; 4677 4678 u8 opt_param_mask[0x20]; 4679 4680 u8 reserved_at_a0[0x20]; 4681 4682 struct mlx5_ifc_qpc_bits qpc; 4683 4684 u8 reserved_at_800[0x80]; 4685 }; 4686 4687 struct mlx5_ifc_set_roce_address_out_bits { 4688 u8 status[0x8]; 4689 u8 reserved_at_8[0x18]; 4690 4691 u8 syndrome[0x20]; 4692 4693 u8 reserved_at_40[0x40]; 4694 }; 4695 4696 struct mlx5_ifc_set_roce_address_in_bits { 4697 u8 opcode[0x10]; 4698 u8 reserved_at_10[0x10]; 4699 4700 u8 reserved_at_20[0x10]; 4701 u8 op_mod[0x10]; 4702 4703 u8 roce_address_index[0x10]; 4704 u8 reserved_at_50[0xc]; 4705 u8 vhca_port_num[0x4]; 4706 4707 u8 reserved_at_60[0x20]; 4708 4709 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4710 }; 4711 4712 struct mlx5_ifc_set_mad_demux_out_bits { 4713 u8 status[0x8]; 4714 u8 reserved_at_8[0x18]; 4715 4716 u8 syndrome[0x20]; 4717 4718 u8 reserved_at_40[0x40]; 4719 }; 4720 4721 enum { 4722 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4723 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4724 }; 4725 4726 struct mlx5_ifc_set_mad_demux_in_bits { 4727 u8 opcode[0x10]; 4728 u8 reserved_at_10[0x10]; 4729 4730 u8 reserved_at_20[0x10]; 4731 u8 op_mod[0x10]; 4732 4733 u8 reserved_at_40[0x20]; 4734 4735 u8 reserved_at_60[0x6]; 4736 u8 demux_mode[0x2]; 4737 u8 reserved_at_68[0x18]; 4738 }; 4739 4740 struct mlx5_ifc_set_l2_table_entry_out_bits { 4741 u8 status[0x8]; 4742 u8 reserved_at_8[0x18]; 4743 4744 u8 syndrome[0x20]; 4745 4746 u8 reserved_at_40[0x40]; 4747 }; 4748 4749 struct mlx5_ifc_set_l2_table_entry_in_bits { 4750 u8 opcode[0x10]; 4751 u8 reserved_at_10[0x10]; 4752 4753 u8 reserved_at_20[0x10]; 4754 u8 op_mod[0x10]; 4755 4756 u8 reserved_at_40[0x60]; 4757 4758 u8 reserved_at_a0[0x8]; 4759 u8 table_index[0x18]; 4760 4761 u8 reserved_at_c0[0x20]; 4762 4763 u8 reserved_at_e0[0x13]; 4764 u8 vlan_valid[0x1]; 4765 u8 vlan[0xc]; 4766 4767 struct mlx5_ifc_mac_address_layout_bits mac_address; 4768 4769 u8 reserved_at_140[0xc0]; 4770 }; 4771 4772 struct mlx5_ifc_set_issi_out_bits { 4773 u8 status[0x8]; 4774 u8 reserved_at_8[0x18]; 4775 4776 u8 syndrome[0x20]; 4777 4778 u8 reserved_at_40[0x40]; 4779 }; 4780 4781 struct mlx5_ifc_set_issi_in_bits { 4782 u8 opcode[0x10]; 4783 u8 reserved_at_10[0x10]; 4784 4785 u8 reserved_at_20[0x10]; 4786 u8 op_mod[0x10]; 4787 4788 u8 reserved_at_40[0x10]; 4789 u8 current_issi[0x10]; 4790 4791 u8 reserved_at_60[0x20]; 4792 }; 4793 4794 struct mlx5_ifc_set_hca_cap_out_bits { 4795 u8 status[0x8]; 4796 u8 reserved_at_8[0x18]; 4797 4798 u8 syndrome[0x20]; 4799 4800 u8 reserved_at_40[0x40]; 4801 }; 4802 4803 struct mlx5_ifc_set_hca_cap_in_bits { 4804 u8 opcode[0x10]; 4805 u8 reserved_at_10[0x10]; 4806 4807 u8 reserved_at_20[0x10]; 4808 u8 op_mod[0x10]; 4809 4810 u8 other_function[0x1]; 4811 u8 ec_vf_function[0x1]; 4812 u8 reserved_at_42[0xe]; 4813 u8 function_id[0x10]; 4814 4815 u8 reserved_at_60[0x20]; 4816 4817 union mlx5_ifc_hca_cap_union_bits capability; 4818 }; 4819 4820 enum { 4821 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4822 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4823 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4824 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4825 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4826 }; 4827 4828 struct mlx5_ifc_set_fte_out_bits { 4829 u8 status[0x8]; 4830 u8 reserved_at_8[0x18]; 4831 4832 u8 syndrome[0x20]; 4833 4834 u8 reserved_at_40[0x40]; 4835 }; 4836 4837 struct mlx5_ifc_set_fte_in_bits { 4838 u8 opcode[0x10]; 4839 u8 reserved_at_10[0x10]; 4840 4841 u8 reserved_at_20[0x10]; 4842 u8 op_mod[0x10]; 4843 4844 u8 other_vport[0x1]; 4845 u8 reserved_at_41[0xf]; 4846 u8 vport_number[0x10]; 4847 4848 u8 reserved_at_60[0x20]; 4849 4850 u8 table_type[0x8]; 4851 u8 reserved_at_88[0x18]; 4852 4853 u8 reserved_at_a0[0x8]; 4854 u8 table_id[0x18]; 4855 4856 u8 ignore_flow_level[0x1]; 4857 u8 reserved_at_c1[0x17]; 4858 u8 modify_enable_mask[0x8]; 4859 4860 u8 reserved_at_e0[0x20]; 4861 4862 u8 flow_index[0x20]; 4863 4864 u8 reserved_at_120[0xe0]; 4865 4866 struct mlx5_ifc_flow_context_bits flow_context; 4867 }; 4868 4869 struct mlx5_ifc_rts2rts_qp_out_bits { 4870 u8 status[0x8]; 4871 u8 reserved_at_8[0x18]; 4872 4873 u8 syndrome[0x20]; 4874 4875 u8 reserved_at_40[0x20]; 4876 u8 ece[0x20]; 4877 }; 4878 4879 struct mlx5_ifc_rts2rts_qp_in_bits { 4880 u8 opcode[0x10]; 4881 u8 uid[0x10]; 4882 4883 u8 reserved_at_20[0x10]; 4884 u8 op_mod[0x10]; 4885 4886 u8 reserved_at_40[0x8]; 4887 u8 qpn[0x18]; 4888 4889 u8 reserved_at_60[0x20]; 4890 4891 u8 opt_param_mask[0x20]; 4892 4893 u8 ece[0x20]; 4894 4895 struct mlx5_ifc_qpc_bits qpc; 4896 4897 u8 reserved_at_800[0x80]; 4898 }; 4899 4900 struct mlx5_ifc_rtr2rts_qp_out_bits { 4901 u8 status[0x8]; 4902 u8 reserved_at_8[0x18]; 4903 4904 u8 syndrome[0x20]; 4905 4906 u8 reserved_at_40[0x20]; 4907 u8 ece[0x20]; 4908 }; 4909 4910 struct mlx5_ifc_rtr2rts_qp_in_bits { 4911 u8 opcode[0x10]; 4912 u8 uid[0x10]; 4913 4914 u8 reserved_at_20[0x10]; 4915 u8 op_mod[0x10]; 4916 4917 u8 reserved_at_40[0x8]; 4918 u8 qpn[0x18]; 4919 4920 u8 reserved_at_60[0x20]; 4921 4922 u8 opt_param_mask[0x20]; 4923 4924 u8 ece[0x20]; 4925 4926 struct mlx5_ifc_qpc_bits qpc; 4927 4928 u8 reserved_at_800[0x80]; 4929 }; 4930 4931 struct mlx5_ifc_rst2init_qp_out_bits { 4932 u8 status[0x8]; 4933 u8 reserved_at_8[0x18]; 4934 4935 u8 syndrome[0x20]; 4936 4937 u8 reserved_at_40[0x20]; 4938 u8 ece[0x20]; 4939 }; 4940 4941 struct mlx5_ifc_rst2init_qp_in_bits { 4942 u8 opcode[0x10]; 4943 u8 uid[0x10]; 4944 4945 u8 reserved_at_20[0x10]; 4946 u8 op_mod[0x10]; 4947 4948 u8 reserved_at_40[0x8]; 4949 u8 qpn[0x18]; 4950 4951 u8 reserved_at_60[0x20]; 4952 4953 u8 opt_param_mask[0x20]; 4954 4955 u8 ece[0x20]; 4956 4957 struct mlx5_ifc_qpc_bits qpc; 4958 4959 u8 reserved_at_800[0x80]; 4960 }; 4961 4962 struct mlx5_ifc_query_xrq_out_bits { 4963 u8 status[0x8]; 4964 u8 reserved_at_8[0x18]; 4965 4966 u8 syndrome[0x20]; 4967 4968 u8 reserved_at_40[0x40]; 4969 4970 struct mlx5_ifc_xrqc_bits xrq_context; 4971 }; 4972 4973 struct mlx5_ifc_query_xrq_in_bits { 4974 u8 opcode[0x10]; 4975 u8 reserved_at_10[0x10]; 4976 4977 u8 reserved_at_20[0x10]; 4978 u8 op_mod[0x10]; 4979 4980 u8 reserved_at_40[0x8]; 4981 u8 xrqn[0x18]; 4982 4983 u8 reserved_at_60[0x20]; 4984 }; 4985 4986 struct mlx5_ifc_query_xrc_srq_out_bits { 4987 u8 status[0x8]; 4988 u8 reserved_at_8[0x18]; 4989 4990 u8 syndrome[0x20]; 4991 4992 u8 reserved_at_40[0x40]; 4993 4994 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4995 4996 u8 reserved_at_280[0x600]; 4997 4998 u8 pas[][0x40]; 4999 }; 5000 5001 struct mlx5_ifc_query_xrc_srq_in_bits { 5002 u8 opcode[0x10]; 5003 u8 reserved_at_10[0x10]; 5004 5005 u8 reserved_at_20[0x10]; 5006 u8 op_mod[0x10]; 5007 5008 u8 reserved_at_40[0x8]; 5009 u8 xrc_srqn[0x18]; 5010 5011 u8 reserved_at_60[0x20]; 5012 }; 5013 5014 enum { 5015 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5016 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5017 }; 5018 5019 struct mlx5_ifc_query_vport_state_out_bits { 5020 u8 status[0x8]; 5021 u8 reserved_at_8[0x18]; 5022 5023 u8 syndrome[0x20]; 5024 5025 u8 reserved_at_40[0x20]; 5026 5027 u8 reserved_at_60[0x18]; 5028 u8 admin_state[0x4]; 5029 u8 state[0x4]; 5030 }; 5031 5032 enum { 5033 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5034 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5035 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5036 }; 5037 5038 struct mlx5_ifc_arm_monitor_counter_in_bits { 5039 u8 opcode[0x10]; 5040 u8 uid[0x10]; 5041 5042 u8 reserved_at_20[0x10]; 5043 u8 op_mod[0x10]; 5044 5045 u8 reserved_at_40[0x20]; 5046 5047 u8 reserved_at_60[0x20]; 5048 }; 5049 5050 struct mlx5_ifc_arm_monitor_counter_out_bits { 5051 u8 status[0x8]; 5052 u8 reserved_at_8[0x18]; 5053 5054 u8 syndrome[0x20]; 5055 5056 u8 reserved_at_40[0x40]; 5057 }; 5058 5059 enum { 5060 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5061 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5062 }; 5063 5064 enum mlx5_monitor_counter_ppcnt { 5065 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5066 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5067 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5068 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5069 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5070 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5071 }; 5072 5073 enum { 5074 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5075 }; 5076 5077 struct mlx5_ifc_monitor_counter_output_bits { 5078 u8 reserved_at_0[0x4]; 5079 u8 type[0x4]; 5080 u8 reserved_at_8[0x8]; 5081 u8 counter[0x10]; 5082 5083 u8 counter_group_id[0x20]; 5084 }; 5085 5086 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5087 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5088 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5089 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5090 5091 struct mlx5_ifc_set_monitor_counter_in_bits { 5092 u8 opcode[0x10]; 5093 u8 uid[0x10]; 5094 5095 u8 reserved_at_20[0x10]; 5096 u8 op_mod[0x10]; 5097 5098 u8 reserved_at_40[0x10]; 5099 u8 num_of_counters[0x10]; 5100 5101 u8 reserved_at_60[0x20]; 5102 5103 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5104 }; 5105 5106 struct mlx5_ifc_set_monitor_counter_out_bits { 5107 u8 status[0x8]; 5108 u8 reserved_at_8[0x18]; 5109 5110 u8 syndrome[0x20]; 5111 5112 u8 reserved_at_40[0x40]; 5113 }; 5114 5115 struct mlx5_ifc_query_vport_state_in_bits { 5116 u8 opcode[0x10]; 5117 u8 reserved_at_10[0x10]; 5118 5119 u8 reserved_at_20[0x10]; 5120 u8 op_mod[0x10]; 5121 5122 u8 other_vport[0x1]; 5123 u8 reserved_at_41[0xf]; 5124 u8 vport_number[0x10]; 5125 5126 u8 reserved_at_60[0x20]; 5127 }; 5128 5129 struct mlx5_ifc_query_vnic_env_out_bits { 5130 u8 status[0x8]; 5131 u8 reserved_at_8[0x18]; 5132 5133 u8 syndrome[0x20]; 5134 5135 u8 reserved_at_40[0x40]; 5136 5137 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5138 }; 5139 5140 enum { 5141 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5142 }; 5143 5144 struct mlx5_ifc_query_vnic_env_in_bits { 5145 u8 opcode[0x10]; 5146 u8 reserved_at_10[0x10]; 5147 5148 u8 reserved_at_20[0x10]; 5149 u8 op_mod[0x10]; 5150 5151 u8 other_vport[0x1]; 5152 u8 reserved_at_41[0xf]; 5153 u8 vport_number[0x10]; 5154 5155 u8 reserved_at_60[0x20]; 5156 }; 5157 5158 struct mlx5_ifc_query_vport_counter_out_bits { 5159 u8 status[0x8]; 5160 u8 reserved_at_8[0x18]; 5161 5162 u8 syndrome[0x20]; 5163 5164 u8 reserved_at_40[0x40]; 5165 5166 struct mlx5_ifc_traffic_counter_bits received_errors; 5167 5168 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5169 5170 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5171 5172 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5173 5174 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5175 5176 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5177 5178 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5179 5180 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5181 5182 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5183 5184 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5185 5186 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5187 5188 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5189 5190 u8 reserved_at_680[0xa00]; 5191 }; 5192 5193 enum { 5194 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5195 }; 5196 5197 struct mlx5_ifc_query_vport_counter_in_bits { 5198 u8 opcode[0x10]; 5199 u8 reserved_at_10[0x10]; 5200 5201 u8 reserved_at_20[0x10]; 5202 u8 op_mod[0x10]; 5203 5204 u8 other_vport[0x1]; 5205 u8 reserved_at_41[0xb]; 5206 u8 port_num[0x4]; 5207 u8 vport_number[0x10]; 5208 5209 u8 reserved_at_60[0x60]; 5210 5211 u8 clear[0x1]; 5212 u8 reserved_at_c1[0x1f]; 5213 5214 u8 reserved_at_e0[0x20]; 5215 }; 5216 5217 struct mlx5_ifc_query_tis_out_bits { 5218 u8 status[0x8]; 5219 u8 reserved_at_8[0x18]; 5220 5221 u8 syndrome[0x20]; 5222 5223 u8 reserved_at_40[0x40]; 5224 5225 struct mlx5_ifc_tisc_bits tis_context; 5226 }; 5227 5228 struct mlx5_ifc_query_tis_in_bits { 5229 u8 opcode[0x10]; 5230 u8 reserved_at_10[0x10]; 5231 5232 u8 reserved_at_20[0x10]; 5233 u8 op_mod[0x10]; 5234 5235 u8 reserved_at_40[0x8]; 5236 u8 tisn[0x18]; 5237 5238 u8 reserved_at_60[0x20]; 5239 }; 5240 5241 struct mlx5_ifc_query_tir_out_bits { 5242 u8 status[0x8]; 5243 u8 reserved_at_8[0x18]; 5244 5245 u8 syndrome[0x20]; 5246 5247 u8 reserved_at_40[0xc0]; 5248 5249 struct mlx5_ifc_tirc_bits tir_context; 5250 }; 5251 5252 struct mlx5_ifc_query_tir_in_bits { 5253 u8 opcode[0x10]; 5254 u8 reserved_at_10[0x10]; 5255 5256 u8 reserved_at_20[0x10]; 5257 u8 op_mod[0x10]; 5258 5259 u8 reserved_at_40[0x8]; 5260 u8 tirn[0x18]; 5261 5262 u8 reserved_at_60[0x20]; 5263 }; 5264 5265 struct mlx5_ifc_query_srq_out_bits { 5266 u8 status[0x8]; 5267 u8 reserved_at_8[0x18]; 5268 5269 u8 syndrome[0x20]; 5270 5271 u8 reserved_at_40[0x40]; 5272 5273 struct mlx5_ifc_srqc_bits srq_context_entry; 5274 5275 u8 reserved_at_280[0x600]; 5276 5277 u8 pas[][0x40]; 5278 }; 5279 5280 struct mlx5_ifc_query_srq_in_bits { 5281 u8 opcode[0x10]; 5282 u8 reserved_at_10[0x10]; 5283 5284 u8 reserved_at_20[0x10]; 5285 u8 op_mod[0x10]; 5286 5287 u8 reserved_at_40[0x8]; 5288 u8 srqn[0x18]; 5289 5290 u8 reserved_at_60[0x20]; 5291 }; 5292 5293 struct mlx5_ifc_query_sq_out_bits { 5294 u8 status[0x8]; 5295 u8 reserved_at_8[0x18]; 5296 5297 u8 syndrome[0x20]; 5298 5299 u8 reserved_at_40[0xc0]; 5300 5301 struct mlx5_ifc_sqc_bits sq_context; 5302 }; 5303 5304 struct mlx5_ifc_query_sq_in_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 reserved_at_20[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_at_40[0x8]; 5312 u8 sqn[0x18]; 5313 5314 u8 reserved_at_60[0x20]; 5315 }; 5316 5317 struct mlx5_ifc_query_special_contexts_out_bits { 5318 u8 status[0x8]; 5319 u8 reserved_at_8[0x18]; 5320 5321 u8 syndrome[0x20]; 5322 5323 u8 dump_fill_mkey[0x20]; 5324 5325 u8 resd_lkey[0x20]; 5326 5327 u8 null_mkey[0x20]; 5328 5329 u8 terminate_scatter_list_mkey[0x20]; 5330 5331 u8 repeated_mkey[0x20]; 5332 5333 u8 reserved_at_a0[0x20]; 5334 }; 5335 5336 struct mlx5_ifc_query_special_contexts_in_bits { 5337 u8 opcode[0x10]; 5338 u8 reserved_at_10[0x10]; 5339 5340 u8 reserved_at_20[0x10]; 5341 u8 op_mod[0x10]; 5342 5343 u8 reserved_at_40[0x40]; 5344 }; 5345 5346 struct mlx5_ifc_query_scheduling_element_out_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_at_10[0x10]; 5349 5350 u8 reserved_at_20[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 reserved_at_40[0xc0]; 5354 5355 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5356 5357 u8 reserved_at_300[0x100]; 5358 }; 5359 5360 enum { 5361 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5362 SCHEDULING_HIERARCHY_NIC = 0x3, 5363 }; 5364 5365 struct mlx5_ifc_query_scheduling_element_in_bits { 5366 u8 opcode[0x10]; 5367 u8 reserved_at_10[0x10]; 5368 5369 u8 reserved_at_20[0x10]; 5370 u8 op_mod[0x10]; 5371 5372 u8 scheduling_hierarchy[0x8]; 5373 u8 reserved_at_48[0x18]; 5374 5375 u8 scheduling_element_id[0x20]; 5376 5377 u8 reserved_at_80[0x180]; 5378 }; 5379 5380 struct mlx5_ifc_query_rqt_out_bits { 5381 u8 status[0x8]; 5382 u8 reserved_at_8[0x18]; 5383 5384 u8 syndrome[0x20]; 5385 5386 u8 reserved_at_40[0xc0]; 5387 5388 struct mlx5_ifc_rqtc_bits rqt_context; 5389 }; 5390 5391 struct mlx5_ifc_query_rqt_in_bits { 5392 u8 opcode[0x10]; 5393 u8 reserved_at_10[0x10]; 5394 5395 u8 reserved_at_20[0x10]; 5396 u8 op_mod[0x10]; 5397 5398 u8 reserved_at_40[0x8]; 5399 u8 rqtn[0x18]; 5400 5401 u8 reserved_at_60[0x20]; 5402 }; 5403 5404 struct mlx5_ifc_query_rq_out_bits { 5405 u8 status[0x8]; 5406 u8 reserved_at_8[0x18]; 5407 5408 u8 syndrome[0x20]; 5409 5410 u8 reserved_at_40[0xc0]; 5411 5412 struct mlx5_ifc_rqc_bits rq_context; 5413 }; 5414 5415 struct mlx5_ifc_query_rq_in_bits { 5416 u8 opcode[0x10]; 5417 u8 reserved_at_10[0x10]; 5418 5419 u8 reserved_at_20[0x10]; 5420 u8 op_mod[0x10]; 5421 5422 u8 reserved_at_40[0x8]; 5423 u8 rqn[0x18]; 5424 5425 u8 reserved_at_60[0x20]; 5426 }; 5427 5428 struct mlx5_ifc_query_roce_address_out_bits { 5429 u8 status[0x8]; 5430 u8 reserved_at_8[0x18]; 5431 5432 u8 syndrome[0x20]; 5433 5434 u8 reserved_at_40[0x40]; 5435 5436 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5437 }; 5438 5439 struct mlx5_ifc_query_roce_address_in_bits { 5440 u8 opcode[0x10]; 5441 u8 reserved_at_10[0x10]; 5442 5443 u8 reserved_at_20[0x10]; 5444 u8 op_mod[0x10]; 5445 5446 u8 roce_address_index[0x10]; 5447 u8 reserved_at_50[0xc]; 5448 u8 vhca_port_num[0x4]; 5449 5450 u8 reserved_at_60[0x20]; 5451 }; 5452 5453 struct mlx5_ifc_query_rmp_out_bits { 5454 u8 status[0x8]; 5455 u8 reserved_at_8[0x18]; 5456 5457 u8 syndrome[0x20]; 5458 5459 u8 reserved_at_40[0xc0]; 5460 5461 struct mlx5_ifc_rmpc_bits rmp_context; 5462 }; 5463 5464 struct mlx5_ifc_query_rmp_in_bits { 5465 u8 opcode[0x10]; 5466 u8 reserved_at_10[0x10]; 5467 5468 u8 reserved_at_20[0x10]; 5469 u8 op_mod[0x10]; 5470 5471 u8 reserved_at_40[0x8]; 5472 u8 rmpn[0x18]; 5473 5474 u8 reserved_at_60[0x20]; 5475 }; 5476 5477 struct mlx5_ifc_cqe_error_syndrome_bits { 5478 u8 hw_error_syndrome[0x8]; 5479 u8 hw_syndrome_type[0x4]; 5480 u8 reserved_at_c[0x4]; 5481 u8 vendor_error_syndrome[0x8]; 5482 u8 syndrome[0x8]; 5483 }; 5484 5485 struct mlx5_ifc_qp_context_extension_bits { 5486 u8 reserved_at_0[0x60]; 5487 5488 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5489 5490 u8 reserved_at_80[0x580]; 5491 }; 5492 5493 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5494 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5495 5496 u8 pas[0][0x40]; 5497 }; 5498 5499 struct mlx5_ifc_qp_pas_list_in_bits { 5500 struct mlx5_ifc_cmd_pas_bits pas[0]; 5501 }; 5502 5503 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5504 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5505 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5506 }; 5507 5508 struct mlx5_ifc_query_qp_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_at_8[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 5514 u8 reserved_at_40[0x40]; 5515 5516 u8 opt_param_mask[0x20]; 5517 5518 u8 ece[0x20]; 5519 5520 struct mlx5_ifc_qpc_bits qpc; 5521 5522 u8 reserved_at_800[0x80]; 5523 5524 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5525 }; 5526 5527 struct mlx5_ifc_query_qp_in_bits { 5528 u8 opcode[0x10]; 5529 u8 reserved_at_10[0x10]; 5530 5531 u8 reserved_at_20[0x10]; 5532 u8 op_mod[0x10]; 5533 5534 u8 qpc_ext[0x1]; 5535 u8 reserved_at_41[0x7]; 5536 u8 qpn[0x18]; 5537 5538 u8 reserved_at_60[0x20]; 5539 }; 5540 5541 struct mlx5_ifc_query_q_counter_out_bits { 5542 u8 status[0x8]; 5543 u8 reserved_at_8[0x18]; 5544 5545 u8 syndrome[0x20]; 5546 5547 u8 reserved_at_40[0x40]; 5548 5549 u8 rx_write_requests[0x20]; 5550 5551 u8 reserved_at_a0[0x20]; 5552 5553 u8 rx_read_requests[0x20]; 5554 5555 u8 reserved_at_e0[0x20]; 5556 5557 u8 rx_atomic_requests[0x20]; 5558 5559 u8 reserved_at_120[0x20]; 5560 5561 u8 rx_dct_connect[0x20]; 5562 5563 u8 reserved_at_160[0x20]; 5564 5565 u8 out_of_buffer[0x20]; 5566 5567 u8 reserved_at_1a0[0x20]; 5568 5569 u8 out_of_sequence[0x20]; 5570 5571 u8 reserved_at_1e0[0x20]; 5572 5573 u8 duplicate_request[0x20]; 5574 5575 u8 reserved_at_220[0x20]; 5576 5577 u8 rnr_nak_retry_err[0x20]; 5578 5579 u8 reserved_at_260[0x20]; 5580 5581 u8 packet_seq_err[0x20]; 5582 5583 u8 reserved_at_2a0[0x20]; 5584 5585 u8 implied_nak_seq_err[0x20]; 5586 5587 u8 reserved_at_2e0[0x20]; 5588 5589 u8 local_ack_timeout_err[0x20]; 5590 5591 u8 reserved_at_320[0xa0]; 5592 5593 u8 resp_local_length_error[0x20]; 5594 5595 u8 req_local_length_error[0x20]; 5596 5597 u8 resp_local_qp_error[0x20]; 5598 5599 u8 local_operation_error[0x20]; 5600 5601 u8 resp_local_protection[0x20]; 5602 5603 u8 req_local_protection[0x20]; 5604 5605 u8 resp_cqe_error[0x20]; 5606 5607 u8 req_cqe_error[0x20]; 5608 5609 u8 req_mw_binding[0x20]; 5610 5611 u8 req_bad_response[0x20]; 5612 5613 u8 req_remote_invalid_request[0x20]; 5614 5615 u8 resp_remote_invalid_request[0x20]; 5616 5617 u8 req_remote_access_errors[0x20]; 5618 5619 u8 resp_remote_access_errors[0x20]; 5620 5621 u8 req_remote_operation_errors[0x20]; 5622 5623 u8 req_transport_retries_exceeded[0x20]; 5624 5625 u8 cq_overflow[0x20]; 5626 5627 u8 resp_cqe_flush_error[0x20]; 5628 5629 u8 req_cqe_flush_error[0x20]; 5630 5631 u8 reserved_at_620[0x20]; 5632 5633 u8 roce_adp_retrans[0x20]; 5634 5635 u8 roce_adp_retrans_to[0x20]; 5636 5637 u8 roce_slow_restart[0x20]; 5638 5639 u8 roce_slow_restart_cnps[0x20]; 5640 5641 u8 roce_slow_restart_trans[0x20]; 5642 5643 u8 reserved_at_6e0[0x120]; 5644 }; 5645 5646 struct mlx5_ifc_query_q_counter_in_bits { 5647 u8 opcode[0x10]; 5648 u8 reserved_at_10[0x10]; 5649 5650 u8 reserved_at_20[0x10]; 5651 u8 op_mod[0x10]; 5652 5653 u8 other_vport[0x1]; 5654 u8 reserved_at_41[0xf]; 5655 u8 vport_number[0x10]; 5656 5657 u8 reserved_at_60[0x60]; 5658 5659 u8 clear[0x1]; 5660 u8 aggregate[0x1]; 5661 u8 reserved_at_c2[0x1e]; 5662 5663 u8 reserved_at_e0[0x18]; 5664 u8 counter_set_id[0x8]; 5665 }; 5666 5667 struct mlx5_ifc_query_pages_out_bits { 5668 u8 status[0x8]; 5669 u8 reserved_at_8[0x18]; 5670 5671 u8 syndrome[0x20]; 5672 5673 u8 embedded_cpu_function[0x1]; 5674 u8 reserved_at_41[0xf]; 5675 u8 function_id[0x10]; 5676 5677 u8 num_pages[0x20]; 5678 }; 5679 5680 enum { 5681 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5682 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5683 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5684 }; 5685 5686 struct mlx5_ifc_query_pages_in_bits { 5687 u8 opcode[0x10]; 5688 u8 reserved_at_10[0x10]; 5689 5690 u8 reserved_at_20[0x10]; 5691 u8 op_mod[0x10]; 5692 5693 u8 embedded_cpu_function[0x1]; 5694 u8 reserved_at_41[0xf]; 5695 u8 function_id[0x10]; 5696 5697 u8 reserved_at_60[0x20]; 5698 }; 5699 5700 struct mlx5_ifc_query_nic_vport_context_out_bits { 5701 u8 status[0x8]; 5702 u8 reserved_at_8[0x18]; 5703 5704 u8 syndrome[0x20]; 5705 5706 u8 reserved_at_40[0x40]; 5707 5708 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5709 }; 5710 5711 struct mlx5_ifc_query_nic_vport_context_in_bits { 5712 u8 opcode[0x10]; 5713 u8 reserved_at_10[0x10]; 5714 5715 u8 reserved_at_20[0x10]; 5716 u8 op_mod[0x10]; 5717 5718 u8 other_vport[0x1]; 5719 u8 reserved_at_41[0xf]; 5720 u8 vport_number[0x10]; 5721 5722 u8 reserved_at_60[0x5]; 5723 u8 allowed_list_type[0x3]; 5724 u8 reserved_at_68[0x18]; 5725 }; 5726 5727 struct mlx5_ifc_query_mkey_out_bits { 5728 u8 status[0x8]; 5729 u8 reserved_at_8[0x18]; 5730 5731 u8 syndrome[0x20]; 5732 5733 u8 reserved_at_40[0x40]; 5734 5735 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5736 5737 u8 reserved_at_280[0x600]; 5738 5739 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5740 5741 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5742 }; 5743 5744 struct mlx5_ifc_query_mkey_in_bits { 5745 u8 opcode[0x10]; 5746 u8 reserved_at_10[0x10]; 5747 5748 u8 reserved_at_20[0x10]; 5749 u8 op_mod[0x10]; 5750 5751 u8 reserved_at_40[0x8]; 5752 u8 mkey_index[0x18]; 5753 5754 u8 pg_access[0x1]; 5755 u8 reserved_at_61[0x1f]; 5756 }; 5757 5758 struct mlx5_ifc_query_mad_demux_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_at_8[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 reserved_at_40[0x40]; 5765 5766 u8 mad_dumux_parameters_block[0x20]; 5767 }; 5768 5769 struct mlx5_ifc_query_mad_demux_in_bits { 5770 u8 opcode[0x10]; 5771 u8 reserved_at_10[0x10]; 5772 5773 u8 reserved_at_20[0x10]; 5774 u8 op_mod[0x10]; 5775 5776 u8 reserved_at_40[0x40]; 5777 }; 5778 5779 struct mlx5_ifc_query_l2_table_entry_out_bits { 5780 u8 status[0x8]; 5781 u8 reserved_at_8[0x18]; 5782 5783 u8 syndrome[0x20]; 5784 5785 u8 reserved_at_40[0xa0]; 5786 5787 u8 reserved_at_e0[0x13]; 5788 u8 vlan_valid[0x1]; 5789 u8 vlan[0xc]; 5790 5791 struct mlx5_ifc_mac_address_layout_bits mac_address; 5792 5793 u8 reserved_at_140[0xc0]; 5794 }; 5795 5796 struct mlx5_ifc_query_l2_table_entry_in_bits { 5797 u8 opcode[0x10]; 5798 u8 reserved_at_10[0x10]; 5799 5800 u8 reserved_at_20[0x10]; 5801 u8 op_mod[0x10]; 5802 5803 u8 reserved_at_40[0x60]; 5804 5805 u8 reserved_at_a0[0x8]; 5806 u8 table_index[0x18]; 5807 5808 u8 reserved_at_c0[0x140]; 5809 }; 5810 5811 struct mlx5_ifc_query_issi_out_bits { 5812 u8 status[0x8]; 5813 u8 reserved_at_8[0x18]; 5814 5815 u8 syndrome[0x20]; 5816 5817 u8 reserved_at_40[0x10]; 5818 u8 current_issi[0x10]; 5819 5820 u8 reserved_at_60[0xa0]; 5821 5822 u8 reserved_at_100[76][0x8]; 5823 u8 supported_issi_dw0[0x20]; 5824 }; 5825 5826 struct mlx5_ifc_query_issi_in_bits { 5827 u8 opcode[0x10]; 5828 u8 reserved_at_10[0x10]; 5829 5830 u8 reserved_at_20[0x10]; 5831 u8 op_mod[0x10]; 5832 5833 u8 reserved_at_40[0x40]; 5834 }; 5835 5836 struct mlx5_ifc_set_driver_version_out_bits { 5837 u8 status[0x8]; 5838 u8 reserved_0[0x18]; 5839 5840 u8 syndrome[0x20]; 5841 u8 reserved_1[0x40]; 5842 }; 5843 5844 struct mlx5_ifc_set_driver_version_in_bits { 5845 u8 opcode[0x10]; 5846 u8 reserved_0[0x10]; 5847 5848 u8 reserved_1[0x10]; 5849 u8 op_mod[0x10]; 5850 5851 u8 reserved_2[0x40]; 5852 u8 driver_version[64][0x8]; 5853 }; 5854 5855 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5856 u8 status[0x8]; 5857 u8 reserved_at_8[0x18]; 5858 5859 u8 syndrome[0x20]; 5860 5861 u8 reserved_at_40[0x40]; 5862 5863 struct mlx5_ifc_pkey_bits pkey[]; 5864 }; 5865 5866 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5867 u8 opcode[0x10]; 5868 u8 reserved_at_10[0x10]; 5869 5870 u8 reserved_at_20[0x10]; 5871 u8 op_mod[0x10]; 5872 5873 u8 other_vport[0x1]; 5874 u8 reserved_at_41[0xb]; 5875 u8 port_num[0x4]; 5876 u8 vport_number[0x10]; 5877 5878 u8 reserved_at_60[0x10]; 5879 u8 pkey_index[0x10]; 5880 }; 5881 5882 enum { 5883 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5884 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5885 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5886 }; 5887 5888 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5889 u8 status[0x8]; 5890 u8 reserved_at_8[0x18]; 5891 5892 u8 syndrome[0x20]; 5893 5894 u8 reserved_at_40[0x20]; 5895 5896 u8 gids_num[0x10]; 5897 u8 reserved_at_70[0x10]; 5898 5899 struct mlx5_ifc_array128_auto_bits gid[]; 5900 }; 5901 5902 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5903 u8 opcode[0x10]; 5904 u8 reserved_at_10[0x10]; 5905 5906 u8 reserved_at_20[0x10]; 5907 u8 op_mod[0x10]; 5908 5909 u8 other_vport[0x1]; 5910 u8 reserved_at_41[0xb]; 5911 u8 port_num[0x4]; 5912 u8 vport_number[0x10]; 5913 5914 u8 reserved_at_60[0x10]; 5915 u8 gid_index[0x10]; 5916 }; 5917 5918 struct mlx5_ifc_query_hca_vport_context_out_bits { 5919 u8 status[0x8]; 5920 u8 reserved_at_8[0x18]; 5921 5922 u8 syndrome[0x20]; 5923 5924 u8 reserved_at_40[0x40]; 5925 5926 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5927 }; 5928 5929 struct mlx5_ifc_query_hca_vport_context_in_bits { 5930 u8 opcode[0x10]; 5931 u8 reserved_at_10[0x10]; 5932 5933 u8 reserved_at_20[0x10]; 5934 u8 op_mod[0x10]; 5935 5936 u8 other_vport[0x1]; 5937 u8 reserved_at_41[0xb]; 5938 u8 port_num[0x4]; 5939 u8 vport_number[0x10]; 5940 5941 u8 reserved_at_60[0x20]; 5942 }; 5943 5944 struct mlx5_ifc_query_hca_cap_out_bits { 5945 u8 status[0x8]; 5946 u8 reserved_at_8[0x18]; 5947 5948 u8 syndrome[0x20]; 5949 5950 u8 reserved_at_40[0x40]; 5951 5952 union mlx5_ifc_hca_cap_union_bits capability; 5953 }; 5954 5955 struct mlx5_ifc_query_hca_cap_in_bits { 5956 u8 opcode[0x10]; 5957 u8 reserved_at_10[0x10]; 5958 5959 u8 reserved_at_20[0x10]; 5960 u8 op_mod[0x10]; 5961 5962 u8 other_function[0x1]; 5963 u8 ec_vf_function[0x1]; 5964 u8 reserved_at_42[0xe]; 5965 u8 function_id[0x10]; 5966 5967 u8 reserved_at_60[0x20]; 5968 }; 5969 5970 struct mlx5_ifc_other_hca_cap_bits { 5971 u8 roce[0x1]; 5972 u8 reserved_at_1[0x27f]; 5973 }; 5974 5975 struct mlx5_ifc_query_other_hca_cap_out_bits { 5976 u8 status[0x8]; 5977 u8 reserved_at_8[0x18]; 5978 5979 u8 syndrome[0x20]; 5980 5981 u8 reserved_at_40[0x40]; 5982 5983 struct mlx5_ifc_other_hca_cap_bits other_capability; 5984 }; 5985 5986 struct mlx5_ifc_query_other_hca_cap_in_bits { 5987 u8 opcode[0x10]; 5988 u8 reserved_at_10[0x10]; 5989 5990 u8 reserved_at_20[0x10]; 5991 u8 op_mod[0x10]; 5992 5993 u8 reserved_at_40[0x10]; 5994 u8 function_id[0x10]; 5995 5996 u8 reserved_at_60[0x20]; 5997 }; 5998 5999 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6000 u8 status[0x8]; 6001 u8 reserved_at_8[0x18]; 6002 6003 u8 syndrome[0x20]; 6004 6005 u8 reserved_at_40[0x40]; 6006 }; 6007 6008 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6009 u8 opcode[0x10]; 6010 u8 reserved_at_10[0x10]; 6011 6012 u8 reserved_at_20[0x10]; 6013 u8 op_mod[0x10]; 6014 6015 u8 reserved_at_40[0x10]; 6016 u8 function_id[0x10]; 6017 u8 field_select[0x20]; 6018 6019 struct mlx5_ifc_other_hca_cap_bits other_capability; 6020 }; 6021 6022 struct mlx5_ifc_flow_table_context_bits { 6023 u8 reformat_en[0x1]; 6024 u8 decap_en[0x1]; 6025 u8 sw_owner[0x1]; 6026 u8 termination_table[0x1]; 6027 u8 table_miss_action[0x4]; 6028 u8 level[0x8]; 6029 u8 reserved_at_10[0x8]; 6030 u8 log_size[0x8]; 6031 6032 u8 reserved_at_20[0x8]; 6033 u8 table_miss_id[0x18]; 6034 6035 u8 reserved_at_40[0x8]; 6036 u8 lag_master_next_table_id[0x18]; 6037 6038 u8 reserved_at_60[0x60]; 6039 6040 u8 sw_owner_icm_root_1[0x40]; 6041 6042 u8 sw_owner_icm_root_0[0x40]; 6043 6044 }; 6045 6046 struct mlx5_ifc_query_flow_table_out_bits { 6047 u8 status[0x8]; 6048 u8 reserved_at_8[0x18]; 6049 6050 u8 syndrome[0x20]; 6051 6052 u8 reserved_at_40[0x80]; 6053 6054 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6055 }; 6056 6057 struct mlx5_ifc_query_flow_table_in_bits { 6058 u8 opcode[0x10]; 6059 u8 reserved_at_10[0x10]; 6060 6061 u8 reserved_at_20[0x10]; 6062 u8 op_mod[0x10]; 6063 6064 u8 reserved_at_40[0x40]; 6065 6066 u8 table_type[0x8]; 6067 u8 reserved_at_88[0x18]; 6068 6069 u8 reserved_at_a0[0x8]; 6070 u8 table_id[0x18]; 6071 6072 u8 reserved_at_c0[0x140]; 6073 }; 6074 6075 struct mlx5_ifc_query_fte_out_bits { 6076 u8 status[0x8]; 6077 u8 reserved_at_8[0x18]; 6078 6079 u8 syndrome[0x20]; 6080 6081 u8 reserved_at_40[0x1c0]; 6082 6083 struct mlx5_ifc_flow_context_bits flow_context; 6084 }; 6085 6086 struct mlx5_ifc_query_fte_in_bits { 6087 u8 opcode[0x10]; 6088 u8 reserved_at_10[0x10]; 6089 6090 u8 reserved_at_20[0x10]; 6091 u8 op_mod[0x10]; 6092 6093 u8 reserved_at_40[0x40]; 6094 6095 u8 table_type[0x8]; 6096 u8 reserved_at_88[0x18]; 6097 6098 u8 reserved_at_a0[0x8]; 6099 u8 table_id[0x18]; 6100 6101 u8 reserved_at_c0[0x40]; 6102 6103 u8 flow_index[0x20]; 6104 6105 u8 reserved_at_120[0xe0]; 6106 }; 6107 6108 struct mlx5_ifc_match_definer_format_0_bits { 6109 u8 reserved_at_0[0x100]; 6110 6111 u8 metadata_reg_c_0[0x20]; 6112 6113 u8 metadata_reg_c_1[0x20]; 6114 6115 u8 outer_dmac_47_16[0x20]; 6116 6117 u8 outer_dmac_15_0[0x10]; 6118 u8 outer_ethertype[0x10]; 6119 6120 u8 reserved_at_180[0x1]; 6121 u8 sx_sniffer[0x1]; 6122 u8 functional_lb[0x1]; 6123 u8 outer_ip_frag[0x1]; 6124 u8 outer_qp_type[0x2]; 6125 u8 outer_encap_type[0x2]; 6126 u8 port_number[0x2]; 6127 u8 outer_l3_type[0x2]; 6128 u8 outer_l4_type[0x2]; 6129 u8 outer_first_vlan_type[0x2]; 6130 u8 outer_first_vlan_prio[0x3]; 6131 u8 outer_first_vlan_cfi[0x1]; 6132 u8 outer_first_vlan_vid[0xc]; 6133 6134 u8 outer_l4_type_ext[0x4]; 6135 u8 reserved_at_1a4[0x2]; 6136 u8 outer_ipsec_layer[0x2]; 6137 u8 outer_l2_type[0x2]; 6138 u8 force_lb[0x1]; 6139 u8 outer_l2_ok[0x1]; 6140 u8 outer_l3_ok[0x1]; 6141 u8 outer_l4_ok[0x1]; 6142 u8 outer_second_vlan_type[0x2]; 6143 u8 outer_second_vlan_prio[0x3]; 6144 u8 outer_second_vlan_cfi[0x1]; 6145 u8 outer_second_vlan_vid[0xc]; 6146 6147 u8 outer_smac_47_16[0x20]; 6148 6149 u8 outer_smac_15_0[0x10]; 6150 u8 inner_ipv4_checksum_ok[0x1]; 6151 u8 inner_l4_checksum_ok[0x1]; 6152 u8 outer_ipv4_checksum_ok[0x1]; 6153 u8 outer_l4_checksum_ok[0x1]; 6154 u8 inner_l3_ok[0x1]; 6155 u8 inner_l4_ok[0x1]; 6156 u8 outer_l3_ok_duplicate[0x1]; 6157 u8 outer_l4_ok_duplicate[0x1]; 6158 u8 outer_tcp_cwr[0x1]; 6159 u8 outer_tcp_ece[0x1]; 6160 u8 outer_tcp_urg[0x1]; 6161 u8 outer_tcp_ack[0x1]; 6162 u8 outer_tcp_psh[0x1]; 6163 u8 outer_tcp_rst[0x1]; 6164 u8 outer_tcp_syn[0x1]; 6165 u8 outer_tcp_fin[0x1]; 6166 }; 6167 6168 struct mlx5_ifc_match_definer_format_22_bits { 6169 u8 reserved_at_0[0x100]; 6170 6171 u8 outer_ip_src_addr[0x20]; 6172 6173 u8 outer_ip_dest_addr[0x20]; 6174 6175 u8 outer_l4_sport[0x10]; 6176 u8 outer_l4_dport[0x10]; 6177 6178 u8 reserved_at_160[0x1]; 6179 u8 sx_sniffer[0x1]; 6180 u8 functional_lb[0x1]; 6181 u8 outer_ip_frag[0x1]; 6182 u8 outer_qp_type[0x2]; 6183 u8 outer_encap_type[0x2]; 6184 u8 port_number[0x2]; 6185 u8 outer_l3_type[0x2]; 6186 u8 outer_l4_type[0x2]; 6187 u8 outer_first_vlan_type[0x2]; 6188 u8 outer_first_vlan_prio[0x3]; 6189 u8 outer_first_vlan_cfi[0x1]; 6190 u8 outer_first_vlan_vid[0xc]; 6191 6192 u8 metadata_reg_c_0[0x20]; 6193 6194 u8 outer_dmac_47_16[0x20]; 6195 6196 u8 outer_smac_47_16[0x20]; 6197 6198 u8 outer_smac_15_0[0x10]; 6199 u8 outer_dmac_15_0[0x10]; 6200 }; 6201 6202 struct mlx5_ifc_match_definer_format_23_bits { 6203 u8 reserved_at_0[0x100]; 6204 6205 u8 inner_ip_src_addr[0x20]; 6206 6207 u8 inner_ip_dest_addr[0x20]; 6208 6209 u8 inner_l4_sport[0x10]; 6210 u8 inner_l4_dport[0x10]; 6211 6212 u8 reserved_at_160[0x1]; 6213 u8 sx_sniffer[0x1]; 6214 u8 functional_lb[0x1]; 6215 u8 inner_ip_frag[0x1]; 6216 u8 inner_qp_type[0x2]; 6217 u8 inner_encap_type[0x2]; 6218 u8 port_number[0x2]; 6219 u8 inner_l3_type[0x2]; 6220 u8 inner_l4_type[0x2]; 6221 u8 inner_first_vlan_type[0x2]; 6222 u8 inner_first_vlan_prio[0x3]; 6223 u8 inner_first_vlan_cfi[0x1]; 6224 u8 inner_first_vlan_vid[0xc]; 6225 6226 u8 tunnel_header_0[0x20]; 6227 6228 u8 inner_dmac_47_16[0x20]; 6229 6230 u8 inner_smac_47_16[0x20]; 6231 6232 u8 inner_smac_15_0[0x10]; 6233 u8 inner_dmac_15_0[0x10]; 6234 }; 6235 6236 struct mlx5_ifc_match_definer_format_29_bits { 6237 u8 reserved_at_0[0xc0]; 6238 6239 u8 outer_ip_dest_addr[0x80]; 6240 6241 u8 outer_ip_src_addr[0x80]; 6242 6243 u8 outer_l4_sport[0x10]; 6244 u8 outer_l4_dport[0x10]; 6245 6246 u8 reserved_at_1e0[0x20]; 6247 }; 6248 6249 struct mlx5_ifc_match_definer_format_30_bits { 6250 u8 reserved_at_0[0xa0]; 6251 6252 u8 outer_ip_dest_addr[0x80]; 6253 6254 u8 outer_ip_src_addr[0x80]; 6255 6256 u8 outer_dmac_47_16[0x20]; 6257 6258 u8 outer_smac_47_16[0x20]; 6259 6260 u8 outer_smac_15_0[0x10]; 6261 u8 outer_dmac_15_0[0x10]; 6262 }; 6263 6264 struct mlx5_ifc_match_definer_format_31_bits { 6265 u8 reserved_at_0[0xc0]; 6266 6267 u8 inner_ip_dest_addr[0x80]; 6268 6269 u8 inner_ip_src_addr[0x80]; 6270 6271 u8 inner_l4_sport[0x10]; 6272 u8 inner_l4_dport[0x10]; 6273 6274 u8 reserved_at_1e0[0x20]; 6275 }; 6276 6277 struct mlx5_ifc_match_definer_format_32_bits { 6278 u8 reserved_at_0[0xa0]; 6279 6280 u8 inner_ip_dest_addr[0x80]; 6281 6282 u8 inner_ip_src_addr[0x80]; 6283 6284 u8 inner_dmac_47_16[0x20]; 6285 6286 u8 inner_smac_47_16[0x20]; 6287 6288 u8 inner_smac_15_0[0x10]; 6289 u8 inner_dmac_15_0[0x10]; 6290 }; 6291 6292 enum { 6293 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6294 }; 6295 6296 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6297 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6298 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6299 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6300 6301 struct mlx5_ifc_match_definer_match_mask_bits { 6302 u8 reserved_at_1c0[5][0x20]; 6303 u8 match_dw_8[0x20]; 6304 u8 match_dw_7[0x20]; 6305 u8 match_dw_6[0x20]; 6306 u8 match_dw_5[0x20]; 6307 u8 match_dw_4[0x20]; 6308 u8 match_dw_3[0x20]; 6309 u8 match_dw_2[0x20]; 6310 u8 match_dw_1[0x20]; 6311 u8 match_dw_0[0x20]; 6312 6313 u8 match_byte_7[0x8]; 6314 u8 match_byte_6[0x8]; 6315 u8 match_byte_5[0x8]; 6316 u8 match_byte_4[0x8]; 6317 6318 u8 match_byte_3[0x8]; 6319 u8 match_byte_2[0x8]; 6320 u8 match_byte_1[0x8]; 6321 u8 match_byte_0[0x8]; 6322 }; 6323 6324 struct mlx5_ifc_match_definer_bits { 6325 u8 modify_field_select[0x40]; 6326 6327 u8 reserved_at_40[0x40]; 6328 6329 u8 reserved_at_80[0x10]; 6330 u8 format_id[0x10]; 6331 6332 u8 reserved_at_a0[0x60]; 6333 6334 u8 format_select_dw3[0x8]; 6335 u8 format_select_dw2[0x8]; 6336 u8 format_select_dw1[0x8]; 6337 u8 format_select_dw0[0x8]; 6338 6339 u8 format_select_dw7[0x8]; 6340 u8 format_select_dw6[0x8]; 6341 u8 format_select_dw5[0x8]; 6342 u8 format_select_dw4[0x8]; 6343 6344 u8 reserved_at_100[0x18]; 6345 u8 format_select_dw8[0x8]; 6346 6347 u8 reserved_at_120[0x20]; 6348 6349 u8 format_select_byte3[0x8]; 6350 u8 format_select_byte2[0x8]; 6351 u8 format_select_byte1[0x8]; 6352 u8 format_select_byte0[0x8]; 6353 6354 u8 format_select_byte7[0x8]; 6355 u8 format_select_byte6[0x8]; 6356 u8 format_select_byte5[0x8]; 6357 u8 format_select_byte4[0x8]; 6358 6359 u8 reserved_at_180[0x40]; 6360 6361 union { 6362 struct { 6363 u8 match_mask[16][0x20]; 6364 }; 6365 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6366 }; 6367 }; 6368 6369 struct mlx5_ifc_general_obj_create_param_bits { 6370 u8 alias_object[0x1]; 6371 u8 reserved_at_1[0x2]; 6372 u8 log_obj_range[0x5]; 6373 u8 reserved_at_8[0x18]; 6374 }; 6375 6376 struct mlx5_ifc_general_obj_query_param_bits { 6377 u8 alias_object[0x1]; 6378 u8 obj_offset[0x1f]; 6379 }; 6380 6381 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6382 u8 opcode[0x10]; 6383 u8 uid[0x10]; 6384 6385 u8 vhca_tunnel_id[0x10]; 6386 u8 obj_type[0x10]; 6387 6388 u8 obj_id[0x20]; 6389 6390 union { 6391 struct mlx5_ifc_general_obj_create_param_bits create; 6392 struct mlx5_ifc_general_obj_query_param_bits query; 6393 } op_param; 6394 }; 6395 6396 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6397 u8 status[0x8]; 6398 u8 reserved_at_8[0x18]; 6399 6400 u8 syndrome[0x20]; 6401 6402 u8 obj_id[0x20]; 6403 6404 u8 reserved_at_60[0x20]; 6405 }; 6406 6407 struct mlx5_ifc_modify_header_arg_bits { 6408 u8 reserved_at_0[0x80]; 6409 6410 u8 reserved_at_80[0x8]; 6411 u8 access_pd[0x18]; 6412 }; 6413 6414 struct mlx5_ifc_create_modify_header_arg_in_bits { 6415 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6416 struct mlx5_ifc_modify_header_arg_bits arg; 6417 }; 6418 6419 struct mlx5_ifc_create_match_definer_in_bits { 6420 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6421 6422 struct mlx5_ifc_match_definer_bits obj_context; 6423 }; 6424 6425 struct mlx5_ifc_create_match_definer_out_bits { 6426 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6427 }; 6428 6429 enum { 6430 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6431 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6432 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6433 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6434 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6435 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6436 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6437 }; 6438 6439 struct mlx5_ifc_query_flow_group_out_bits { 6440 u8 status[0x8]; 6441 u8 reserved_at_8[0x18]; 6442 6443 u8 syndrome[0x20]; 6444 6445 u8 reserved_at_40[0xa0]; 6446 6447 u8 start_flow_index[0x20]; 6448 6449 u8 reserved_at_100[0x20]; 6450 6451 u8 end_flow_index[0x20]; 6452 6453 u8 reserved_at_140[0xa0]; 6454 6455 u8 reserved_at_1e0[0x18]; 6456 u8 match_criteria_enable[0x8]; 6457 6458 struct mlx5_ifc_fte_match_param_bits match_criteria; 6459 6460 u8 reserved_at_1200[0xe00]; 6461 }; 6462 6463 struct mlx5_ifc_query_flow_group_in_bits { 6464 u8 opcode[0x10]; 6465 u8 reserved_at_10[0x10]; 6466 6467 u8 reserved_at_20[0x10]; 6468 u8 op_mod[0x10]; 6469 6470 u8 reserved_at_40[0x40]; 6471 6472 u8 table_type[0x8]; 6473 u8 reserved_at_88[0x18]; 6474 6475 u8 reserved_at_a0[0x8]; 6476 u8 table_id[0x18]; 6477 6478 u8 group_id[0x20]; 6479 6480 u8 reserved_at_e0[0x120]; 6481 }; 6482 6483 struct mlx5_ifc_query_flow_counter_out_bits { 6484 u8 status[0x8]; 6485 u8 reserved_at_8[0x18]; 6486 6487 u8 syndrome[0x20]; 6488 6489 u8 reserved_at_40[0x40]; 6490 6491 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6492 }; 6493 6494 struct mlx5_ifc_query_flow_counter_in_bits { 6495 u8 opcode[0x10]; 6496 u8 reserved_at_10[0x10]; 6497 6498 u8 reserved_at_20[0x10]; 6499 u8 op_mod[0x10]; 6500 6501 u8 reserved_at_40[0x80]; 6502 6503 u8 clear[0x1]; 6504 u8 reserved_at_c1[0xf]; 6505 u8 num_of_counters[0x10]; 6506 6507 u8 flow_counter_id[0x20]; 6508 }; 6509 6510 struct mlx5_ifc_query_esw_vport_context_out_bits { 6511 u8 status[0x8]; 6512 u8 reserved_at_8[0x18]; 6513 6514 u8 syndrome[0x20]; 6515 6516 u8 reserved_at_40[0x40]; 6517 6518 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6519 }; 6520 6521 struct mlx5_ifc_query_esw_vport_context_in_bits { 6522 u8 opcode[0x10]; 6523 u8 reserved_at_10[0x10]; 6524 6525 u8 reserved_at_20[0x10]; 6526 u8 op_mod[0x10]; 6527 6528 u8 other_vport[0x1]; 6529 u8 reserved_at_41[0xf]; 6530 u8 vport_number[0x10]; 6531 6532 u8 reserved_at_60[0x20]; 6533 }; 6534 6535 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6536 u8 status[0x8]; 6537 u8 reserved_at_8[0x18]; 6538 6539 u8 syndrome[0x20]; 6540 6541 u8 reserved_at_40[0x40]; 6542 }; 6543 6544 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6545 u8 reserved_at_0[0x1b]; 6546 u8 fdb_to_vport_reg_c_id[0x1]; 6547 u8 vport_cvlan_insert[0x1]; 6548 u8 vport_svlan_insert[0x1]; 6549 u8 vport_cvlan_strip[0x1]; 6550 u8 vport_svlan_strip[0x1]; 6551 }; 6552 6553 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6554 u8 opcode[0x10]; 6555 u8 reserved_at_10[0x10]; 6556 6557 u8 reserved_at_20[0x10]; 6558 u8 op_mod[0x10]; 6559 6560 u8 other_vport[0x1]; 6561 u8 reserved_at_41[0xf]; 6562 u8 vport_number[0x10]; 6563 6564 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6565 6566 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6567 }; 6568 6569 struct mlx5_ifc_query_eq_out_bits { 6570 u8 status[0x8]; 6571 u8 reserved_at_8[0x18]; 6572 6573 u8 syndrome[0x20]; 6574 6575 u8 reserved_at_40[0x40]; 6576 6577 struct mlx5_ifc_eqc_bits eq_context_entry; 6578 6579 u8 reserved_at_280[0x40]; 6580 6581 u8 event_bitmask[0x40]; 6582 6583 u8 reserved_at_300[0x580]; 6584 6585 u8 pas[][0x40]; 6586 }; 6587 6588 struct mlx5_ifc_query_eq_in_bits { 6589 u8 opcode[0x10]; 6590 u8 reserved_at_10[0x10]; 6591 6592 u8 reserved_at_20[0x10]; 6593 u8 op_mod[0x10]; 6594 6595 u8 reserved_at_40[0x18]; 6596 u8 eq_number[0x8]; 6597 6598 u8 reserved_at_60[0x20]; 6599 }; 6600 6601 struct mlx5_ifc_packet_reformat_context_in_bits { 6602 u8 reformat_type[0x8]; 6603 u8 reserved_at_8[0x4]; 6604 u8 reformat_param_0[0x4]; 6605 u8 reserved_at_10[0x6]; 6606 u8 reformat_data_size[0xa]; 6607 6608 u8 reformat_param_1[0x8]; 6609 u8 reserved_at_28[0x8]; 6610 u8 reformat_data[2][0x8]; 6611 6612 u8 more_reformat_data[][0x8]; 6613 }; 6614 6615 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6616 u8 status[0x8]; 6617 u8 reserved_at_8[0x18]; 6618 6619 u8 syndrome[0x20]; 6620 6621 u8 reserved_at_40[0xa0]; 6622 6623 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6624 }; 6625 6626 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6627 u8 opcode[0x10]; 6628 u8 reserved_at_10[0x10]; 6629 6630 u8 reserved_at_20[0x10]; 6631 u8 op_mod[0x10]; 6632 6633 u8 packet_reformat_id[0x20]; 6634 6635 u8 reserved_at_60[0xa0]; 6636 }; 6637 6638 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6639 u8 status[0x8]; 6640 u8 reserved_at_8[0x18]; 6641 6642 u8 syndrome[0x20]; 6643 6644 u8 packet_reformat_id[0x20]; 6645 6646 u8 reserved_at_60[0x20]; 6647 }; 6648 6649 enum { 6650 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6651 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6652 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6653 }; 6654 6655 enum mlx5_reformat_ctx_type { 6656 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6657 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6658 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6659 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6660 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6661 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6662 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6663 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6664 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6665 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6666 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6667 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6668 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6669 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6670 }; 6671 6672 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6673 u8 opcode[0x10]; 6674 u8 reserved_at_10[0x10]; 6675 6676 u8 reserved_at_20[0x10]; 6677 u8 op_mod[0x10]; 6678 6679 u8 reserved_at_40[0xa0]; 6680 6681 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6682 }; 6683 6684 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6685 u8 status[0x8]; 6686 u8 reserved_at_8[0x18]; 6687 6688 u8 syndrome[0x20]; 6689 6690 u8 reserved_at_40[0x40]; 6691 }; 6692 6693 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6694 u8 opcode[0x10]; 6695 u8 reserved_at_10[0x10]; 6696 6697 u8 reserved_20[0x10]; 6698 u8 op_mod[0x10]; 6699 6700 u8 packet_reformat_id[0x20]; 6701 6702 u8 reserved_60[0x20]; 6703 }; 6704 6705 struct mlx5_ifc_set_action_in_bits { 6706 u8 action_type[0x4]; 6707 u8 field[0xc]; 6708 u8 reserved_at_10[0x3]; 6709 u8 offset[0x5]; 6710 u8 reserved_at_18[0x3]; 6711 u8 length[0x5]; 6712 6713 u8 data[0x20]; 6714 }; 6715 6716 struct mlx5_ifc_add_action_in_bits { 6717 u8 action_type[0x4]; 6718 u8 field[0xc]; 6719 u8 reserved_at_10[0x10]; 6720 6721 u8 data[0x20]; 6722 }; 6723 6724 struct mlx5_ifc_copy_action_in_bits { 6725 u8 action_type[0x4]; 6726 u8 src_field[0xc]; 6727 u8 reserved_at_10[0x3]; 6728 u8 src_offset[0x5]; 6729 u8 reserved_at_18[0x3]; 6730 u8 length[0x5]; 6731 6732 u8 reserved_at_20[0x4]; 6733 u8 dst_field[0xc]; 6734 u8 reserved_at_30[0x3]; 6735 u8 dst_offset[0x5]; 6736 u8 reserved_at_38[0x8]; 6737 }; 6738 6739 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6740 struct mlx5_ifc_set_action_in_bits set_action_in; 6741 struct mlx5_ifc_add_action_in_bits add_action_in; 6742 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6743 u8 reserved_at_0[0x40]; 6744 }; 6745 6746 enum { 6747 MLX5_ACTION_TYPE_SET = 0x1, 6748 MLX5_ACTION_TYPE_ADD = 0x2, 6749 MLX5_ACTION_TYPE_COPY = 0x3, 6750 }; 6751 6752 enum { 6753 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6754 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6755 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6756 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6757 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6758 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6759 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6760 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6761 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6762 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6763 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6764 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6765 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6766 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6767 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6768 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6769 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6770 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6771 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6772 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6773 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6774 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6775 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6776 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6777 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6778 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6779 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6780 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6781 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6782 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6783 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6784 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6785 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6786 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6787 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6788 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6789 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6790 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6791 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6792 }; 6793 6794 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_at_8[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 modify_header_id[0x20]; 6801 6802 u8 reserved_at_60[0x20]; 6803 }; 6804 6805 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6806 u8 opcode[0x10]; 6807 u8 reserved_at_10[0x10]; 6808 6809 u8 reserved_at_20[0x10]; 6810 u8 op_mod[0x10]; 6811 6812 u8 reserved_at_40[0x20]; 6813 6814 u8 table_type[0x8]; 6815 u8 reserved_at_68[0x10]; 6816 u8 num_of_actions[0x8]; 6817 6818 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6819 }; 6820 6821 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6822 u8 status[0x8]; 6823 u8 reserved_at_8[0x18]; 6824 6825 u8 syndrome[0x20]; 6826 6827 u8 reserved_at_40[0x40]; 6828 }; 6829 6830 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6831 u8 opcode[0x10]; 6832 u8 reserved_at_10[0x10]; 6833 6834 u8 reserved_at_20[0x10]; 6835 u8 op_mod[0x10]; 6836 6837 u8 modify_header_id[0x20]; 6838 6839 u8 reserved_at_60[0x20]; 6840 }; 6841 6842 struct mlx5_ifc_query_modify_header_context_in_bits { 6843 u8 opcode[0x10]; 6844 u8 uid[0x10]; 6845 6846 u8 reserved_at_20[0x10]; 6847 u8 op_mod[0x10]; 6848 6849 u8 modify_header_id[0x20]; 6850 6851 u8 reserved_at_60[0xa0]; 6852 }; 6853 6854 struct mlx5_ifc_query_dct_out_bits { 6855 u8 status[0x8]; 6856 u8 reserved_at_8[0x18]; 6857 6858 u8 syndrome[0x20]; 6859 6860 u8 reserved_at_40[0x40]; 6861 6862 struct mlx5_ifc_dctc_bits dct_context_entry; 6863 6864 u8 reserved_at_280[0x180]; 6865 }; 6866 6867 struct mlx5_ifc_query_dct_in_bits { 6868 u8 opcode[0x10]; 6869 u8 reserved_at_10[0x10]; 6870 6871 u8 reserved_at_20[0x10]; 6872 u8 op_mod[0x10]; 6873 6874 u8 reserved_at_40[0x8]; 6875 u8 dctn[0x18]; 6876 6877 u8 reserved_at_60[0x20]; 6878 }; 6879 6880 struct mlx5_ifc_query_cq_out_bits { 6881 u8 status[0x8]; 6882 u8 reserved_at_8[0x18]; 6883 6884 u8 syndrome[0x20]; 6885 6886 u8 reserved_at_40[0x40]; 6887 6888 struct mlx5_ifc_cqc_bits cq_context; 6889 6890 u8 reserved_at_280[0x600]; 6891 6892 u8 pas[][0x40]; 6893 }; 6894 6895 struct mlx5_ifc_query_cq_in_bits { 6896 u8 opcode[0x10]; 6897 u8 reserved_at_10[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 reserved_at_40[0x8]; 6903 u8 cqn[0x18]; 6904 6905 u8 reserved_at_60[0x20]; 6906 }; 6907 6908 struct mlx5_ifc_query_cong_status_out_bits { 6909 u8 status[0x8]; 6910 u8 reserved_at_8[0x18]; 6911 6912 u8 syndrome[0x20]; 6913 6914 u8 reserved_at_40[0x20]; 6915 6916 u8 enable[0x1]; 6917 u8 tag_enable[0x1]; 6918 u8 reserved_at_62[0x1e]; 6919 }; 6920 6921 struct mlx5_ifc_query_cong_status_in_bits { 6922 u8 opcode[0x10]; 6923 u8 reserved_at_10[0x10]; 6924 6925 u8 reserved_at_20[0x10]; 6926 u8 op_mod[0x10]; 6927 6928 u8 reserved_at_40[0x18]; 6929 u8 priority[0x4]; 6930 u8 cong_protocol[0x4]; 6931 6932 u8 reserved_at_60[0x20]; 6933 }; 6934 6935 struct mlx5_ifc_query_cong_statistics_out_bits { 6936 u8 status[0x8]; 6937 u8 reserved_at_8[0x18]; 6938 6939 u8 syndrome[0x20]; 6940 6941 u8 reserved_at_40[0x40]; 6942 6943 u8 rp_cur_flows[0x20]; 6944 6945 u8 sum_flows[0x20]; 6946 6947 u8 rp_cnp_ignored_high[0x20]; 6948 6949 u8 rp_cnp_ignored_low[0x20]; 6950 6951 u8 rp_cnp_handled_high[0x20]; 6952 6953 u8 rp_cnp_handled_low[0x20]; 6954 6955 u8 reserved_at_140[0x100]; 6956 6957 u8 time_stamp_high[0x20]; 6958 6959 u8 time_stamp_low[0x20]; 6960 6961 u8 accumulators_period[0x20]; 6962 6963 u8 np_ecn_marked_roce_packets_high[0x20]; 6964 6965 u8 np_ecn_marked_roce_packets_low[0x20]; 6966 6967 u8 np_cnp_sent_high[0x20]; 6968 6969 u8 np_cnp_sent_low[0x20]; 6970 6971 u8 reserved_at_320[0x560]; 6972 }; 6973 6974 struct mlx5_ifc_query_cong_statistics_in_bits { 6975 u8 opcode[0x10]; 6976 u8 reserved_at_10[0x10]; 6977 6978 u8 reserved_at_20[0x10]; 6979 u8 op_mod[0x10]; 6980 6981 u8 clear[0x1]; 6982 u8 reserved_at_41[0x1f]; 6983 6984 u8 reserved_at_60[0x20]; 6985 }; 6986 6987 struct mlx5_ifc_query_cong_params_out_bits { 6988 u8 status[0x8]; 6989 u8 reserved_at_8[0x18]; 6990 6991 u8 syndrome[0x20]; 6992 6993 u8 reserved_at_40[0x40]; 6994 6995 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6996 }; 6997 6998 struct mlx5_ifc_query_cong_params_in_bits { 6999 u8 opcode[0x10]; 7000 u8 reserved_at_10[0x10]; 7001 7002 u8 reserved_at_20[0x10]; 7003 u8 op_mod[0x10]; 7004 7005 u8 reserved_at_40[0x1c]; 7006 u8 cong_protocol[0x4]; 7007 7008 u8 reserved_at_60[0x20]; 7009 }; 7010 7011 struct mlx5_ifc_query_adapter_out_bits { 7012 u8 status[0x8]; 7013 u8 reserved_at_8[0x18]; 7014 7015 u8 syndrome[0x20]; 7016 7017 u8 reserved_at_40[0x40]; 7018 7019 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7020 }; 7021 7022 struct mlx5_ifc_query_adapter_in_bits { 7023 u8 opcode[0x10]; 7024 u8 reserved_at_10[0x10]; 7025 7026 u8 reserved_at_20[0x10]; 7027 u8 op_mod[0x10]; 7028 7029 u8 reserved_at_40[0x40]; 7030 }; 7031 7032 struct mlx5_ifc_qp_2rst_out_bits { 7033 u8 status[0x8]; 7034 u8 reserved_at_8[0x18]; 7035 7036 u8 syndrome[0x20]; 7037 7038 u8 reserved_at_40[0x40]; 7039 }; 7040 7041 struct mlx5_ifc_qp_2rst_in_bits { 7042 u8 opcode[0x10]; 7043 u8 uid[0x10]; 7044 7045 u8 reserved_at_20[0x10]; 7046 u8 op_mod[0x10]; 7047 7048 u8 reserved_at_40[0x8]; 7049 u8 qpn[0x18]; 7050 7051 u8 reserved_at_60[0x20]; 7052 }; 7053 7054 struct mlx5_ifc_qp_2err_out_bits { 7055 u8 status[0x8]; 7056 u8 reserved_at_8[0x18]; 7057 7058 u8 syndrome[0x20]; 7059 7060 u8 reserved_at_40[0x40]; 7061 }; 7062 7063 struct mlx5_ifc_qp_2err_in_bits { 7064 u8 opcode[0x10]; 7065 u8 uid[0x10]; 7066 7067 u8 reserved_at_20[0x10]; 7068 u8 op_mod[0x10]; 7069 7070 u8 reserved_at_40[0x8]; 7071 u8 qpn[0x18]; 7072 7073 u8 reserved_at_60[0x20]; 7074 }; 7075 7076 struct mlx5_ifc_page_fault_resume_out_bits { 7077 u8 status[0x8]; 7078 u8 reserved_at_8[0x18]; 7079 7080 u8 syndrome[0x20]; 7081 7082 u8 reserved_at_40[0x40]; 7083 }; 7084 7085 struct mlx5_ifc_page_fault_resume_in_bits { 7086 u8 opcode[0x10]; 7087 u8 reserved_at_10[0x10]; 7088 7089 u8 reserved_at_20[0x10]; 7090 u8 op_mod[0x10]; 7091 7092 u8 error[0x1]; 7093 u8 reserved_at_41[0x4]; 7094 u8 page_fault_type[0x3]; 7095 u8 wq_number[0x18]; 7096 7097 u8 reserved_at_60[0x8]; 7098 u8 token[0x18]; 7099 }; 7100 7101 struct mlx5_ifc_nop_out_bits { 7102 u8 status[0x8]; 7103 u8 reserved_at_8[0x18]; 7104 7105 u8 syndrome[0x20]; 7106 7107 u8 reserved_at_40[0x40]; 7108 }; 7109 7110 struct mlx5_ifc_nop_in_bits { 7111 u8 opcode[0x10]; 7112 u8 reserved_at_10[0x10]; 7113 7114 u8 reserved_at_20[0x10]; 7115 u8 op_mod[0x10]; 7116 7117 u8 reserved_at_40[0x40]; 7118 }; 7119 7120 struct mlx5_ifc_modify_vport_state_out_bits { 7121 u8 status[0x8]; 7122 u8 reserved_at_8[0x18]; 7123 7124 u8 syndrome[0x20]; 7125 7126 u8 reserved_at_40[0x40]; 7127 }; 7128 7129 struct mlx5_ifc_modify_vport_state_in_bits { 7130 u8 opcode[0x10]; 7131 u8 reserved_at_10[0x10]; 7132 7133 u8 reserved_at_20[0x10]; 7134 u8 op_mod[0x10]; 7135 7136 u8 other_vport[0x1]; 7137 u8 reserved_at_41[0xf]; 7138 u8 vport_number[0x10]; 7139 7140 u8 reserved_at_60[0x18]; 7141 u8 admin_state[0x4]; 7142 u8 reserved_at_7c[0x4]; 7143 }; 7144 7145 struct mlx5_ifc_modify_tis_out_bits { 7146 u8 status[0x8]; 7147 u8 reserved_at_8[0x18]; 7148 7149 u8 syndrome[0x20]; 7150 7151 u8 reserved_at_40[0x40]; 7152 }; 7153 7154 struct mlx5_ifc_modify_tis_bitmask_bits { 7155 u8 reserved_at_0[0x20]; 7156 7157 u8 reserved_at_20[0x1d]; 7158 u8 lag_tx_port_affinity[0x1]; 7159 u8 strict_lag_tx_port_affinity[0x1]; 7160 u8 prio[0x1]; 7161 }; 7162 7163 struct mlx5_ifc_modify_tis_in_bits { 7164 u8 opcode[0x10]; 7165 u8 uid[0x10]; 7166 7167 u8 reserved_at_20[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_at_40[0x8]; 7171 u8 tisn[0x18]; 7172 7173 u8 reserved_at_60[0x20]; 7174 7175 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7176 7177 u8 reserved_at_c0[0x40]; 7178 7179 struct mlx5_ifc_tisc_bits ctx; 7180 }; 7181 7182 struct mlx5_ifc_modify_tir_bitmask_bits { 7183 u8 reserved_at_0[0x20]; 7184 7185 u8 reserved_at_20[0x1b]; 7186 u8 self_lb_en[0x1]; 7187 u8 reserved_at_3c[0x1]; 7188 u8 hash[0x1]; 7189 u8 reserved_at_3e[0x1]; 7190 u8 packet_merge[0x1]; 7191 }; 7192 7193 struct mlx5_ifc_modify_tir_out_bits { 7194 u8 status[0x8]; 7195 u8 reserved_at_8[0x18]; 7196 7197 u8 syndrome[0x20]; 7198 7199 u8 reserved_at_40[0x40]; 7200 }; 7201 7202 struct mlx5_ifc_modify_tir_in_bits { 7203 u8 opcode[0x10]; 7204 u8 uid[0x10]; 7205 7206 u8 reserved_at_20[0x10]; 7207 u8 op_mod[0x10]; 7208 7209 u8 reserved_at_40[0x8]; 7210 u8 tirn[0x18]; 7211 7212 u8 reserved_at_60[0x20]; 7213 7214 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7215 7216 u8 reserved_at_c0[0x40]; 7217 7218 struct mlx5_ifc_tirc_bits ctx; 7219 }; 7220 7221 struct mlx5_ifc_modify_sq_out_bits { 7222 u8 status[0x8]; 7223 u8 reserved_at_8[0x18]; 7224 7225 u8 syndrome[0x20]; 7226 7227 u8 reserved_at_40[0x40]; 7228 }; 7229 7230 struct mlx5_ifc_modify_sq_in_bits { 7231 u8 opcode[0x10]; 7232 u8 uid[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 sq_state[0x4]; 7238 u8 reserved_at_44[0x4]; 7239 u8 sqn[0x18]; 7240 7241 u8 reserved_at_60[0x20]; 7242 7243 u8 modify_bitmask[0x40]; 7244 7245 u8 reserved_at_c0[0x40]; 7246 7247 struct mlx5_ifc_sqc_bits ctx; 7248 }; 7249 7250 struct mlx5_ifc_modify_scheduling_element_out_bits { 7251 u8 status[0x8]; 7252 u8 reserved_at_8[0x18]; 7253 7254 u8 syndrome[0x20]; 7255 7256 u8 reserved_at_40[0x1c0]; 7257 }; 7258 7259 enum { 7260 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7261 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7262 }; 7263 7264 struct mlx5_ifc_modify_scheduling_element_in_bits { 7265 u8 opcode[0x10]; 7266 u8 reserved_at_10[0x10]; 7267 7268 u8 reserved_at_20[0x10]; 7269 u8 op_mod[0x10]; 7270 7271 u8 scheduling_hierarchy[0x8]; 7272 u8 reserved_at_48[0x18]; 7273 7274 u8 scheduling_element_id[0x20]; 7275 7276 u8 reserved_at_80[0x20]; 7277 7278 u8 modify_bitmask[0x20]; 7279 7280 u8 reserved_at_c0[0x40]; 7281 7282 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7283 7284 u8 reserved_at_300[0x100]; 7285 }; 7286 7287 struct mlx5_ifc_modify_rqt_out_bits { 7288 u8 status[0x8]; 7289 u8 reserved_at_8[0x18]; 7290 7291 u8 syndrome[0x20]; 7292 7293 u8 reserved_at_40[0x40]; 7294 }; 7295 7296 struct mlx5_ifc_rqt_bitmask_bits { 7297 u8 reserved_at_0[0x20]; 7298 7299 u8 reserved_at_20[0x1f]; 7300 u8 rqn_list[0x1]; 7301 }; 7302 7303 struct mlx5_ifc_modify_rqt_in_bits { 7304 u8 opcode[0x10]; 7305 u8 uid[0x10]; 7306 7307 u8 reserved_at_20[0x10]; 7308 u8 op_mod[0x10]; 7309 7310 u8 reserved_at_40[0x8]; 7311 u8 rqtn[0x18]; 7312 7313 u8 reserved_at_60[0x20]; 7314 7315 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7316 7317 u8 reserved_at_c0[0x40]; 7318 7319 struct mlx5_ifc_rqtc_bits ctx; 7320 }; 7321 7322 struct mlx5_ifc_modify_rq_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_at_8[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_at_40[0x40]; 7329 }; 7330 7331 enum { 7332 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7333 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7334 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7335 }; 7336 7337 struct mlx5_ifc_modify_rq_in_bits { 7338 u8 opcode[0x10]; 7339 u8 uid[0x10]; 7340 7341 u8 reserved_at_20[0x10]; 7342 u8 op_mod[0x10]; 7343 7344 u8 rq_state[0x4]; 7345 u8 reserved_at_44[0x4]; 7346 u8 rqn[0x18]; 7347 7348 u8 reserved_at_60[0x20]; 7349 7350 u8 modify_bitmask[0x40]; 7351 7352 u8 reserved_at_c0[0x40]; 7353 7354 struct mlx5_ifc_rqc_bits ctx; 7355 }; 7356 7357 struct mlx5_ifc_modify_rmp_out_bits { 7358 u8 status[0x8]; 7359 u8 reserved_at_8[0x18]; 7360 7361 u8 syndrome[0x20]; 7362 7363 u8 reserved_at_40[0x40]; 7364 }; 7365 7366 struct mlx5_ifc_rmp_bitmask_bits { 7367 u8 reserved_at_0[0x20]; 7368 7369 u8 reserved_at_20[0x1f]; 7370 u8 lwm[0x1]; 7371 }; 7372 7373 struct mlx5_ifc_modify_rmp_in_bits { 7374 u8 opcode[0x10]; 7375 u8 uid[0x10]; 7376 7377 u8 reserved_at_20[0x10]; 7378 u8 op_mod[0x10]; 7379 7380 u8 rmp_state[0x4]; 7381 u8 reserved_at_44[0x4]; 7382 u8 rmpn[0x18]; 7383 7384 u8 reserved_at_60[0x20]; 7385 7386 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7387 7388 u8 reserved_at_c0[0x40]; 7389 7390 struct mlx5_ifc_rmpc_bits ctx; 7391 }; 7392 7393 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7394 u8 status[0x8]; 7395 u8 reserved_at_8[0x18]; 7396 7397 u8 syndrome[0x20]; 7398 7399 u8 reserved_at_40[0x40]; 7400 }; 7401 7402 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7403 u8 reserved_at_0[0x12]; 7404 u8 affiliation[0x1]; 7405 u8 reserved_at_13[0x1]; 7406 u8 disable_uc_local_lb[0x1]; 7407 u8 disable_mc_local_lb[0x1]; 7408 u8 node_guid[0x1]; 7409 u8 port_guid[0x1]; 7410 u8 min_inline[0x1]; 7411 u8 mtu[0x1]; 7412 u8 change_event[0x1]; 7413 u8 promisc[0x1]; 7414 u8 permanent_address[0x1]; 7415 u8 addresses_list[0x1]; 7416 u8 roce_en[0x1]; 7417 u8 reserved_at_1f[0x1]; 7418 }; 7419 7420 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7421 u8 opcode[0x10]; 7422 u8 reserved_at_10[0x10]; 7423 7424 u8 reserved_at_20[0x10]; 7425 u8 op_mod[0x10]; 7426 7427 u8 other_vport[0x1]; 7428 u8 reserved_at_41[0xf]; 7429 u8 vport_number[0x10]; 7430 7431 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7432 7433 u8 reserved_at_80[0x780]; 7434 7435 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7436 }; 7437 7438 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7439 u8 status[0x8]; 7440 u8 reserved_at_8[0x18]; 7441 7442 u8 syndrome[0x20]; 7443 7444 u8 reserved_at_40[0x40]; 7445 }; 7446 7447 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7448 u8 opcode[0x10]; 7449 u8 reserved_at_10[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 other_vport[0x1]; 7455 u8 reserved_at_41[0xb]; 7456 u8 port_num[0x4]; 7457 u8 vport_number[0x10]; 7458 7459 u8 reserved_at_60[0x20]; 7460 7461 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7462 }; 7463 7464 struct mlx5_ifc_modify_cq_out_bits { 7465 u8 status[0x8]; 7466 u8 reserved_at_8[0x18]; 7467 7468 u8 syndrome[0x20]; 7469 7470 u8 reserved_at_40[0x40]; 7471 }; 7472 7473 enum { 7474 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7475 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7476 }; 7477 7478 struct mlx5_ifc_modify_cq_in_bits { 7479 u8 opcode[0x10]; 7480 u8 uid[0x10]; 7481 7482 u8 reserved_at_20[0x10]; 7483 u8 op_mod[0x10]; 7484 7485 u8 reserved_at_40[0x8]; 7486 u8 cqn[0x18]; 7487 7488 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7489 7490 struct mlx5_ifc_cqc_bits cq_context; 7491 7492 u8 reserved_at_280[0x60]; 7493 7494 u8 cq_umem_valid[0x1]; 7495 u8 reserved_at_2e1[0x1f]; 7496 7497 u8 reserved_at_300[0x580]; 7498 7499 u8 pas[][0x40]; 7500 }; 7501 7502 struct mlx5_ifc_modify_cong_status_out_bits { 7503 u8 status[0x8]; 7504 u8 reserved_at_8[0x18]; 7505 7506 u8 syndrome[0x20]; 7507 7508 u8 reserved_at_40[0x40]; 7509 }; 7510 7511 struct mlx5_ifc_modify_cong_status_in_bits { 7512 u8 opcode[0x10]; 7513 u8 reserved_at_10[0x10]; 7514 7515 u8 reserved_at_20[0x10]; 7516 u8 op_mod[0x10]; 7517 7518 u8 reserved_at_40[0x18]; 7519 u8 priority[0x4]; 7520 u8 cong_protocol[0x4]; 7521 7522 u8 enable[0x1]; 7523 u8 tag_enable[0x1]; 7524 u8 reserved_at_62[0x1e]; 7525 }; 7526 7527 struct mlx5_ifc_modify_cong_params_out_bits { 7528 u8 status[0x8]; 7529 u8 reserved_at_8[0x18]; 7530 7531 u8 syndrome[0x20]; 7532 7533 u8 reserved_at_40[0x40]; 7534 }; 7535 7536 struct mlx5_ifc_modify_cong_params_in_bits { 7537 u8 opcode[0x10]; 7538 u8 reserved_at_10[0x10]; 7539 7540 u8 reserved_at_20[0x10]; 7541 u8 op_mod[0x10]; 7542 7543 u8 reserved_at_40[0x1c]; 7544 u8 cong_protocol[0x4]; 7545 7546 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7547 7548 u8 reserved_at_80[0x80]; 7549 7550 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7551 }; 7552 7553 struct mlx5_ifc_manage_pages_out_bits { 7554 u8 status[0x8]; 7555 u8 reserved_at_8[0x18]; 7556 7557 u8 syndrome[0x20]; 7558 7559 u8 output_num_entries[0x20]; 7560 7561 u8 reserved_at_60[0x20]; 7562 7563 u8 pas[][0x40]; 7564 }; 7565 7566 enum { 7567 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7568 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7569 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7570 }; 7571 7572 struct mlx5_ifc_manage_pages_in_bits { 7573 u8 opcode[0x10]; 7574 u8 reserved_at_10[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 embedded_cpu_function[0x1]; 7580 u8 reserved_at_41[0xf]; 7581 u8 function_id[0x10]; 7582 7583 u8 input_num_entries[0x20]; 7584 7585 u8 pas[][0x40]; 7586 }; 7587 7588 struct mlx5_ifc_mad_ifc_out_bits { 7589 u8 status[0x8]; 7590 u8 reserved_at_8[0x18]; 7591 7592 u8 syndrome[0x20]; 7593 7594 u8 reserved_at_40[0x40]; 7595 7596 u8 response_mad_packet[256][0x8]; 7597 }; 7598 7599 struct mlx5_ifc_mad_ifc_in_bits { 7600 u8 opcode[0x10]; 7601 u8 reserved_at_10[0x10]; 7602 7603 u8 reserved_at_20[0x10]; 7604 u8 op_mod[0x10]; 7605 7606 u8 remote_lid[0x10]; 7607 u8 reserved_at_50[0x8]; 7608 u8 port[0x8]; 7609 7610 u8 reserved_at_60[0x20]; 7611 7612 u8 mad[256][0x8]; 7613 }; 7614 7615 struct mlx5_ifc_init_hca_out_bits { 7616 u8 status[0x8]; 7617 u8 reserved_at_8[0x18]; 7618 7619 u8 syndrome[0x20]; 7620 7621 u8 reserved_at_40[0x40]; 7622 }; 7623 7624 struct mlx5_ifc_init_hca_in_bits { 7625 u8 opcode[0x10]; 7626 u8 reserved_at_10[0x10]; 7627 7628 u8 reserved_at_20[0x10]; 7629 u8 op_mod[0x10]; 7630 7631 u8 reserved_at_40[0x20]; 7632 7633 u8 reserved_at_60[0x2]; 7634 u8 sw_vhca_id[0xe]; 7635 u8 reserved_at_70[0x10]; 7636 7637 u8 sw_owner_id[4][0x20]; 7638 }; 7639 7640 struct mlx5_ifc_init2rtr_qp_out_bits { 7641 u8 status[0x8]; 7642 u8 reserved_at_8[0x18]; 7643 7644 u8 syndrome[0x20]; 7645 7646 u8 reserved_at_40[0x20]; 7647 u8 ece[0x20]; 7648 }; 7649 7650 struct mlx5_ifc_init2rtr_qp_in_bits { 7651 u8 opcode[0x10]; 7652 u8 uid[0x10]; 7653 7654 u8 reserved_at_20[0x10]; 7655 u8 op_mod[0x10]; 7656 7657 u8 reserved_at_40[0x8]; 7658 u8 qpn[0x18]; 7659 7660 u8 reserved_at_60[0x20]; 7661 7662 u8 opt_param_mask[0x20]; 7663 7664 u8 ece[0x20]; 7665 7666 struct mlx5_ifc_qpc_bits qpc; 7667 7668 u8 reserved_at_800[0x80]; 7669 }; 7670 7671 struct mlx5_ifc_init2init_qp_out_bits { 7672 u8 status[0x8]; 7673 u8 reserved_at_8[0x18]; 7674 7675 u8 syndrome[0x20]; 7676 7677 u8 reserved_at_40[0x20]; 7678 u8 ece[0x20]; 7679 }; 7680 7681 struct mlx5_ifc_init2init_qp_in_bits { 7682 u8 opcode[0x10]; 7683 u8 uid[0x10]; 7684 7685 u8 reserved_at_20[0x10]; 7686 u8 op_mod[0x10]; 7687 7688 u8 reserved_at_40[0x8]; 7689 u8 qpn[0x18]; 7690 7691 u8 reserved_at_60[0x20]; 7692 7693 u8 opt_param_mask[0x20]; 7694 7695 u8 ece[0x20]; 7696 7697 struct mlx5_ifc_qpc_bits qpc; 7698 7699 u8 reserved_at_800[0x80]; 7700 }; 7701 7702 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7703 u8 status[0x8]; 7704 u8 reserved_at_8[0x18]; 7705 7706 u8 syndrome[0x20]; 7707 7708 u8 reserved_at_40[0x40]; 7709 7710 u8 packet_headers_log[128][0x8]; 7711 7712 u8 packet_syndrome[64][0x8]; 7713 }; 7714 7715 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7716 u8 opcode[0x10]; 7717 u8 reserved_at_10[0x10]; 7718 7719 u8 reserved_at_20[0x10]; 7720 u8 op_mod[0x10]; 7721 7722 u8 reserved_at_40[0x40]; 7723 }; 7724 7725 struct mlx5_ifc_gen_eqe_in_bits { 7726 u8 opcode[0x10]; 7727 u8 reserved_at_10[0x10]; 7728 7729 u8 reserved_at_20[0x10]; 7730 u8 op_mod[0x10]; 7731 7732 u8 reserved_at_40[0x18]; 7733 u8 eq_number[0x8]; 7734 7735 u8 reserved_at_60[0x20]; 7736 7737 u8 eqe[64][0x8]; 7738 }; 7739 7740 struct mlx5_ifc_gen_eq_out_bits { 7741 u8 status[0x8]; 7742 u8 reserved_at_8[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 reserved_at_40[0x40]; 7747 }; 7748 7749 struct mlx5_ifc_enable_hca_out_bits { 7750 u8 status[0x8]; 7751 u8 reserved_at_8[0x18]; 7752 7753 u8 syndrome[0x20]; 7754 7755 u8 reserved_at_40[0x20]; 7756 }; 7757 7758 struct mlx5_ifc_enable_hca_in_bits { 7759 u8 opcode[0x10]; 7760 u8 reserved_at_10[0x10]; 7761 7762 u8 reserved_at_20[0x10]; 7763 u8 op_mod[0x10]; 7764 7765 u8 embedded_cpu_function[0x1]; 7766 u8 reserved_at_41[0xf]; 7767 u8 function_id[0x10]; 7768 7769 u8 reserved_at_60[0x20]; 7770 }; 7771 7772 struct mlx5_ifc_drain_dct_out_bits { 7773 u8 status[0x8]; 7774 u8 reserved_at_8[0x18]; 7775 7776 u8 syndrome[0x20]; 7777 7778 u8 reserved_at_40[0x40]; 7779 }; 7780 7781 struct mlx5_ifc_drain_dct_in_bits { 7782 u8 opcode[0x10]; 7783 u8 uid[0x10]; 7784 7785 u8 reserved_at_20[0x10]; 7786 u8 op_mod[0x10]; 7787 7788 u8 reserved_at_40[0x8]; 7789 u8 dctn[0x18]; 7790 7791 u8 reserved_at_60[0x20]; 7792 }; 7793 7794 struct mlx5_ifc_disable_hca_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_at_8[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_at_40[0x20]; 7801 }; 7802 7803 struct mlx5_ifc_disable_hca_in_bits { 7804 u8 opcode[0x10]; 7805 u8 reserved_at_10[0x10]; 7806 7807 u8 reserved_at_20[0x10]; 7808 u8 op_mod[0x10]; 7809 7810 u8 embedded_cpu_function[0x1]; 7811 u8 reserved_at_41[0xf]; 7812 u8 function_id[0x10]; 7813 7814 u8 reserved_at_60[0x20]; 7815 }; 7816 7817 struct mlx5_ifc_detach_from_mcg_out_bits { 7818 u8 status[0x8]; 7819 u8 reserved_at_8[0x18]; 7820 7821 u8 syndrome[0x20]; 7822 7823 u8 reserved_at_40[0x40]; 7824 }; 7825 7826 struct mlx5_ifc_detach_from_mcg_in_bits { 7827 u8 opcode[0x10]; 7828 u8 uid[0x10]; 7829 7830 u8 reserved_at_20[0x10]; 7831 u8 op_mod[0x10]; 7832 7833 u8 reserved_at_40[0x8]; 7834 u8 qpn[0x18]; 7835 7836 u8 reserved_at_60[0x20]; 7837 7838 u8 multicast_gid[16][0x8]; 7839 }; 7840 7841 struct mlx5_ifc_destroy_xrq_out_bits { 7842 u8 status[0x8]; 7843 u8 reserved_at_8[0x18]; 7844 7845 u8 syndrome[0x20]; 7846 7847 u8 reserved_at_40[0x40]; 7848 }; 7849 7850 struct mlx5_ifc_destroy_xrq_in_bits { 7851 u8 opcode[0x10]; 7852 u8 uid[0x10]; 7853 7854 u8 reserved_at_20[0x10]; 7855 u8 op_mod[0x10]; 7856 7857 u8 reserved_at_40[0x8]; 7858 u8 xrqn[0x18]; 7859 7860 u8 reserved_at_60[0x20]; 7861 }; 7862 7863 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7864 u8 status[0x8]; 7865 u8 reserved_at_8[0x18]; 7866 7867 u8 syndrome[0x20]; 7868 7869 u8 reserved_at_40[0x40]; 7870 }; 7871 7872 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7873 u8 opcode[0x10]; 7874 u8 uid[0x10]; 7875 7876 u8 reserved_at_20[0x10]; 7877 u8 op_mod[0x10]; 7878 7879 u8 reserved_at_40[0x8]; 7880 u8 xrc_srqn[0x18]; 7881 7882 u8 reserved_at_60[0x20]; 7883 }; 7884 7885 struct mlx5_ifc_destroy_tis_out_bits { 7886 u8 status[0x8]; 7887 u8 reserved_at_8[0x18]; 7888 7889 u8 syndrome[0x20]; 7890 7891 u8 reserved_at_40[0x40]; 7892 }; 7893 7894 struct mlx5_ifc_destroy_tis_in_bits { 7895 u8 opcode[0x10]; 7896 u8 uid[0x10]; 7897 7898 u8 reserved_at_20[0x10]; 7899 u8 op_mod[0x10]; 7900 7901 u8 reserved_at_40[0x8]; 7902 u8 tisn[0x18]; 7903 7904 u8 reserved_at_60[0x20]; 7905 }; 7906 7907 struct mlx5_ifc_destroy_tir_out_bits { 7908 u8 status[0x8]; 7909 u8 reserved_at_8[0x18]; 7910 7911 u8 syndrome[0x20]; 7912 7913 u8 reserved_at_40[0x40]; 7914 }; 7915 7916 struct mlx5_ifc_destroy_tir_in_bits { 7917 u8 opcode[0x10]; 7918 u8 uid[0x10]; 7919 7920 u8 reserved_at_20[0x10]; 7921 u8 op_mod[0x10]; 7922 7923 u8 reserved_at_40[0x8]; 7924 u8 tirn[0x18]; 7925 7926 u8 reserved_at_60[0x20]; 7927 }; 7928 7929 struct mlx5_ifc_destroy_srq_out_bits { 7930 u8 status[0x8]; 7931 u8 reserved_at_8[0x18]; 7932 7933 u8 syndrome[0x20]; 7934 7935 u8 reserved_at_40[0x40]; 7936 }; 7937 7938 struct mlx5_ifc_destroy_srq_in_bits { 7939 u8 opcode[0x10]; 7940 u8 uid[0x10]; 7941 7942 u8 reserved_at_20[0x10]; 7943 u8 op_mod[0x10]; 7944 7945 u8 reserved_at_40[0x8]; 7946 u8 srqn[0x18]; 7947 7948 u8 reserved_at_60[0x20]; 7949 }; 7950 7951 struct mlx5_ifc_destroy_sq_out_bits { 7952 u8 status[0x8]; 7953 u8 reserved_at_8[0x18]; 7954 7955 u8 syndrome[0x20]; 7956 7957 u8 reserved_at_40[0x40]; 7958 }; 7959 7960 struct mlx5_ifc_destroy_sq_in_bits { 7961 u8 opcode[0x10]; 7962 u8 uid[0x10]; 7963 7964 u8 reserved_at_20[0x10]; 7965 u8 op_mod[0x10]; 7966 7967 u8 reserved_at_40[0x8]; 7968 u8 sqn[0x18]; 7969 7970 u8 reserved_at_60[0x20]; 7971 }; 7972 7973 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7974 u8 status[0x8]; 7975 u8 reserved_at_8[0x18]; 7976 7977 u8 syndrome[0x20]; 7978 7979 u8 reserved_at_40[0x1c0]; 7980 }; 7981 7982 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7983 u8 opcode[0x10]; 7984 u8 reserved_at_10[0x10]; 7985 7986 u8 reserved_at_20[0x10]; 7987 u8 op_mod[0x10]; 7988 7989 u8 scheduling_hierarchy[0x8]; 7990 u8 reserved_at_48[0x18]; 7991 7992 u8 scheduling_element_id[0x20]; 7993 7994 u8 reserved_at_80[0x180]; 7995 }; 7996 7997 struct mlx5_ifc_destroy_rqt_out_bits { 7998 u8 status[0x8]; 7999 u8 reserved_at_8[0x18]; 8000 8001 u8 syndrome[0x20]; 8002 8003 u8 reserved_at_40[0x40]; 8004 }; 8005 8006 struct mlx5_ifc_destroy_rqt_in_bits { 8007 u8 opcode[0x10]; 8008 u8 uid[0x10]; 8009 8010 u8 reserved_at_20[0x10]; 8011 u8 op_mod[0x10]; 8012 8013 u8 reserved_at_40[0x8]; 8014 u8 rqtn[0x18]; 8015 8016 u8 reserved_at_60[0x20]; 8017 }; 8018 8019 struct mlx5_ifc_destroy_rq_out_bits { 8020 u8 status[0x8]; 8021 u8 reserved_at_8[0x18]; 8022 8023 u8 syndrome[0x20]; 8024 8025 u8 reserved_at_40[0x40]; 8026 }; 8027 8028 struct mlx5_ifc_destroy_rq_in_bits { 8029 u8 opcode[0x10]; 8030 u8 uid[0x10]; 8031 8032 u8 reserved_at_20[0x10]; 8033 u8 op_mod[0x10]; 8034 8035 u8 reserved_at_40[0x8]; 8036 u8 rqn[0x18]; 8037 8038 u8 reserved_at_60[0x20]; 8039 }; 8040 8041 struct mlx5_ifc_set_delay_drop_params_in_bits { 8042 u8 opcode[0x10]; 8043 u8 reserved_at_10[0x10]; 8044 8045 u8 reserved_at_20[0x10]; 8046 u8 op_mod[0x10]; 8047 8048 u8 reserved_at_40[0x20]; 8049 8050 u8 reserved_at_60[0x10]; 8051 u8 delay_drop_timeout[0x10]; 8052 }; 8053 8054 struct mlx5_ifc_set_delay_drop_params_out_bits { 8055 u8 status[0x8]; 8056 u8 reserved_at_8[0x18]; 8057 8058 u8 syndrome[0x20]; 8059 8060 u8 reserved_at_40[0x40]; 8061 }; 8062 8063 struct mlx5_ifc_destroy_rmp_out_bits { 8064 u8 status[0x8]; 8065 u8 reserved_at_8[0x18]; 8066 8067 u8 syndrome[0x20]; 8068 8069 u8 reserved_at_40[0x40]; 8070 }; 8071 8072 struct mlx5_ifc_destroy_rmp_in_bits { 8073 u8 opcode[0x10]; 8074 u8 uid[0x10]; 8075 8076 u8 reserved_at_20[0x10]; 8077 u8 op_mod[0x10]; 8078 8079 u8 reserved_at_40[0x8]; 8080 u8 rmpn[0x18]; 8081 8082 u8 reserved_at_60[0x20]; 8083 }; 8084 8085 struct mlx5_ifc_destroy_qp_out_bits { 8086 u8 status[0x8]; 8087 u8 reserved_at_8[0x18]; 8088 8089 u8 syndrome[0x20]; 8090 8091 u8 reserved_at_40[0x40]; 8092 }; 8093 8094 struct mlx5_ifc_destroy_qp_in_bits { 8095 u8 opcode[0x10]; 8096 u8 uid[0x10]; 8097 8098 u8 reserved_at_20[0x10]; 8099 u8 op_mod[0x10]; 8100 8101 u8 reserved_at_40[0x8]; 8102 u8 qpn[0x18]; 8103 8104 u8 reserved_at_60[0x20]; 8105 }; 8106 8107 struct mlx5_ifc_destroy_psv_out_bits { 8108 u8 status[0x8]; 8109 u8 reserved_at_8[0x18]; 8110 8111 u8 syndrome[0x20]; 8112 8113 u8 reserved_at_40[0x40]; 8114 }; 8115 8116 struct mlx5_ifc_destroy_psv_in_bits { 8117 u8 opcode[0x10]; 8118 u8 reserved_at_10[0x10]; 8119 8120 u8 reserved_at_20[0x10]; 8121 u8 op_mod[0x10]; 8122 8123 u8 reserved_at_40[0x8]; 8124 u8 psvn[0x18]; 8125 8126 u8 reserved_at_60[0x20]; 8127 }; 8128 8129 struct mlx5_ifc_destroy_mkey_out_bits { 8130 u8 status[0x8]; 8131 u8 reserved_at_8[0x18]; 8132 8133 u8 syndrome[0x20]; 8134 8135 u8 reserved_at_40[0x40]; 8136 }; 8137 8138 struct mlx5_ifc_destroy_mkey_in_bits { 8139 u8 opcode[0x10]; 8140 u8 uid[0x10]; 8141 8142 u8 reserved_at_20[0x10]; 8143 u8 op_mod[0x10]; 8144 8145 u8 reserved_at_40[0x8]; 8146 u8 mkey_index[0x18]; 8147 8148 u8 reserved_at_60[0x20]; 8149 }; 8150 8151 struct mlx5_ifc_destroy_flow_table_out_bits { 8152 u8 status[0x8]; 8153 u8 reserved_at_8[0x18]; 8154 8155 u8 syndrome[0x20]; 8156 8157 u8 reserved_at_40[0x40]; 8158 }; 8159 8160 struct mlx5_ifc_destroy_flow_table_in_bits { 8161 u8 opcode[0x10]; 8162 u8 reserved_at_10[0x10]; 8163 8164 u8 reserved_at_20[0x10]; 8165 u8 op_mod[0x10]; 8166 8167 u8 other_vport[0x1]; 8168 u8 reserved_at_41[0xf]; 8169 u8 vport_number[0x10]; 8170 8171 u8 reserved_at_60[0x20]; 8172 8173 u8 table_type[0x8]; 8174 u8 reserved_at_88[0x18]; 8175 8176 u8 reserved_at_a0[0x8]; 8177 u8 table_id[0x18]; 8178 8179 u8 reserved_at_c0[0x140]; 8180 }; 8181 8182 struct mlx5_ifc_destroy_flow_group_out_bits { 8183 u8 status[0x8]; 8184 u8 reserved_at_8[0x18]; 8185 8186 u8 syndrome[0x20]; 8187 8188 u8 reserved_at_40[0x40]; 8189 }; 8190 8191 struct mlx5_ifc_destroy_flow_group_in_bits { 8192 u8 opcode[0x10]; 8193 u8 reserved_at_10[0x10]; 8194 8195 u8 reserved_at_20[0x10]; 8196 u8 op_mod[0x10]; 8197 8198 u8 other_vport[0x1]; 8199 u8 reserved_at_41[0xf]; 8200 u8 vport_number[0x10]; 8201 8202 u8 reserved_at_60[0x20]; 8203 8204 u8 table_type[0x8]; 8205 u8 reserved_at_88[0x18]; 8206 8207 u8 reserved_at_a0[0x8]; 8208 u8 table_id[0x18]; 8209 8210 u8 group_id[0x20]; 8211 8212 u8 reserved_at_e0[0x120]; 8213 }; 8214 8215 struct mlx5_ifc_destroy_eq_out_bits { 8216 u8 status[0x8]; 8217 u8 reserved_at_8[0x18]; 8218 8219 u8 syndrome[0x20]; 8220 8221 u8 reserved_at_40[0x40]; 8222 }; 8223 8224 struct mlx5_ifc_destroy_eq_in_bits { 8225 u8 opcode[0x10]; 8226 u8 reserved_at_10[0x10]; 8227 8228 u8 reserved_at_20[0x10]; 8229 u8 op_mod[0x10]; 8230 8231 u8 reserved_at_40[0x18]; 8232 u8 eq_number[0x8]; 8233 8234 u8 reserved_at_60[0x20]; 8235 }; 8236 8237 struct mlx5_ifc_destroy_dct_out_bits { 8238 u8 status[0x8]; 8239 u8 reserved_at_8[0x18]; 8240 8241 u8 syndrome[0x20]; 8242 8243 u8 reserved_at_40[0x40]; 8244 }; 8245 8246 struct mlx5_ifc_destroy_dct_in_bits { 8247 u8 opcode[0x10]; 8248 u8 uid[0x10]; 8249 8250 u8 reserved_at_20[0x10]; 8251 u8 op_mod[0x10]; 8252 8253 u8 reserved_at_40[0x8]; 8254 u8 dctn[0x18]; 8255 8256 u8 reserved_at_60[0x20]; 8257 }; 8258 8259 struct mlx5_ifc_destroy_cq_out_bits { 8260 u8 status[0x8]; 8261 u8 reserved_at_8[0x18]; 8262 8263 u8 syndrome[0x20]; 8264 8265 u8 reserved_at_40[0x40]; 8266 }; 8267 8268 struct mlx5_ifc_destroy_cq_in_bits { 8269 u8 opcode[0x10]; 8270 u8 uid[0x10]; 8271 8272 u8 reserved_at_20[0x10]; 8273 u8 op_mod[0x10]; 8274 8275 u8 reserved_at_40[0x8]; 8276 u8 cqn[0x18]; 8277 8278 u8 reserved_at_60[0x20]; 8279 }; 8280 8281 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8282 u8 status[0x8]; 8283 u8 reserved_at_8[0x18]; 8284 8285 u8 syndrome[0x20]; 8286 8287 u8 reserved_at_40[0x40]; 8288 }; 8289 8290 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8291 u8 opcode[0x10]; 8292 u8 reserved_at_10[0x10]; 8293 8294 u8 reserved_at_20[0x10]; 8295 u8 op_mod[0x10]; 8296 8297 u8 reserved_at_40[0x20]; 8298 8299 u8 reserved_at_60[0x10]; 8300 u8 vxlan_udp_port[0x10]; 8301 }; 8302 8303 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8304 u8 status[0x8]; 8305 u8 reserved_at_8[0x18]; 8306 8307 u8 syndrome[0x20]; 8308 8309 u8 reserved_at_40[0x40]; 8310 }; 8311 8312 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8313 u8 opcode[0x10]; 8314 u8 reserved_at_10[0x10]; 8315 8316 u8 reserved_at_20[0x10]; 8317 u8 op_mod[0x10]; 8318 8319 u8 reserved_at_40[0x60]; 8320 8321 u8 reserved_at_a0[0x8]; 8322 u8 table_index[0x18]; 8323 8324 u8 reserved_at_c0[0x140]; 8325 }; 8326 8327 struct mlx5_ifc_delete_fte_out_bits { 8328 u8 status[0x8]; 8329 u8 reserved_at_8[0x18]; 8330 8331 u8 syndrome[0x20]; 8332 8333 u8 reserved_at_40[0x40]; 8334 }; 8335 8336 struct mlx5_ifc_delete_fte_in_bits { 8337 u8 opcode[0x10]; 8338 u8 reserved_at_10[0x10]; 8339 8340 u8 reserved_at_20[0x10]; 8341 u8 op_mod[0x10]; 8342 8343 u8 other_vport[0x1]; 8344 u8 reserved_at_41[0xf]; 8345 u8 vport_number[0x10]; 8346 8347 u8 reserved_at_60[0x20]; 8348 8349 u8 table_type[0x8]; 8350 u8 reserved_at_88[0x18]; 8351 8352 u8 reserved_at_a0[0x8]; 8353 u8 table_id[0x18]; 8354 8355 u8 reserved_at_c0[0x40]; 8356 8357 u8 flow_index[0x20]; 8358 8359 u8 reserved_at_120[0xe0]; 8360 }; 8361 8362 struct mlx5_ifc_dealloc_xrcd_out_bits { 8363 u8 status[0x8]; 8364 u8 reserved_at_8[0x18]; 8365 8366 u8 syndrome[0x20]; 8367 8368 u8 reserved_at_40[0x40]; 8369 }; 8370 8371 struct mlx5_ifc_dealloc_xrcd_in_bits { 8372 u8 opcode[0x10]; 8373 u8 uid[0x10]; 8374 8375 u8 reserved_at_20[0x10]; 8376 u8 op_mod[0x10]; 8377 8378 u8 reserved_at_40[0x8]; 8379 u8 xrcd[0x18]; 8380 8381 u8 reserved_at_60[0x20]; 8382 }; 8383 8384 struct mlx5_ifc_dealloc_uar_out_bits { 8385 u8 status[0x8]; 8386 u8 reserved_at_8[0x18]; 8387 8388 u8 syndrome[0x20]; 8389 8390 u8 reserved_at_40[0x40]; 8391 }; 8392 8393 struct mlx5_ifc_dealloc_uar_in_bits { 8394 u8 opcode[0x10]; 8395 u8 uid[0x10]; 8396 8397 u8 reserved_at_20[0x10]; 8398 u8 op_mod[0x10]; 8399 8400 u8 reserved_at_40[0x8]; 8401 u8 uar[0x18]; 8402 8403 u8 reserved_at_60[0x20]; 8404 }; 8405 8406 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8407 u8 status[0x8]; 8408 u8 reserved_at_8[0x18]; 8409 8410 u8 syndrome[0x20]; 8411 8412 u8 reserved_at_40[0x40]; 8413 }; 8414 8415 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8416 u8 opcode[0x10]; 8417 u8 uid[0x10]; 8418 8419 u8 reserved_at_20[0x10]; 8420 u8 op_mod[0x10]; 8421 8422 u8 reserved_at_40[0x8]; 8423 u8 transport_domain[0x18]; 8424 8425 u8 reserved_at_60[0x20]; 8426 }; 8427 8428 struct mlx5_ifc_dealloc_q_counter_out_bits { 8429 u8 status[0x8]; 8430 u8 reserved_at_8[0x18]; 8431 8432 u8 syndrome[0x20]; 8433 8434 u8 reserved_at_40[0x40]; 8435 }; 8436 8437 struct mlx5_ifc_dealloc_q_counter_in_bits { 8438 u8 opcode[0x10]; 8439 u8 reserved_at_10[0x10]; 8440 8441 u8 reserved_at_20[0x10]; 8442 u8 op_mod[0x10]; 8443 8444 u8 reserved_at_40[0x18]; 8445 u8 counter_set_id[0x8]; 8446 8447 u8 reserved_at_60[0x20]; 8448 }; 8449 8450 struct mlx5_ifc_dealloc_pd_out_bits { 8451 u8 status[0x8]; 8452 u8 reserved_at_8[0x18]; 8453 8454 u8 syndrome[0x20]; 8455 8456 u8 reserved_at_40[0x40]; 8457 }; 8458 8459 struct mlx5_ifc_dealloc_pd_in_bits { 8460 u8 opcode[0x10]; 8461 u8 uid[0x10]; 8462 8463 u8 reserved_at_20[0x10]; 8464 u8 op_mod[0x10]; 8465 8466 u8 reserved_at_40[0x8]; 8467 u8 pd[0x18]; 8468 8469 u8 reserved_at_60[0x20]; 8470 }; 8471 8472 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8473 u8 status[0x8]; 8474 u8 reserved_at_8[0x18]; 8475 8476 u8 syndrome[0x20]; 8477 8478 u8 reserved_at_40[0x40]; 8479 }; 8480 8481 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8482 u8 opcode[0x10]; 8483 u8 reserved_at_10[0x10]; 8484 8485 u8 reserved_at_20[0x10]; 8486 u8 op_mod[0x10]; 8487 8488 u8 flow_counter_id[0x20]; 8489 8490 u8 reserved_at_60[0x20]; 8491 }; 8492 8493 struct mlx5_ifc_create_xrq_out_bits { 8494 u8 status[0x8]; 8495 u8 reserved_at_8[0x18]; 8496 8497 u8 syndrome[0x20]; 8498 8499 u8 reserved_at_40[0x8]; 8500 u8 xrqn[0x18]; 8501 8502 u8 reserved_at_60[0x20]; 8503 }; 8504 8505 struct mlx5_ifc_create_xrq_in_bits { 8506 u8 opcode[0x10]; 8507 u8 uid[0x10]; 8508 8509 u8 reserved_at_20[0x10]; 8510 u8 op_mod[0x10]; 8511 8512 u8 reserved_at_40[0x40]; 8513 8514 struct mlx5_ifc_xrqc_bits xrq_context; 8515 }; 8516 8517 struct mlx5_ifc_create_xrc_srq_out_bits { 8518 u8 status[0x8]; 8519 u8 reserved_at_8[0x18]; 8520 8521 u8 syndrome[0x20]; 8522 8523 u8 reserved_at_40[0x8]; 8524 u8 xrc_srqn[0x18]; 8525 8526 u8 reserved_at_60[0x20]; 8527 }; 8528 8529 struct mlx5_ifc_create_xrc_srq_in_bits { 8530 u8 opcode[0x10]; 8531 u8 uid[0x10]; 8532 8533 u8 reserved_at_20[0x10]; 8534 u8 op_mod[0x10]; 8535 8536 u8 reserved_at_40[0x40]; 8537 8538 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8539 8540 u8 reserved_at_280[0x60]; 8541 8542 u8 xrc_srq_umem_valid[0x1]; 8543 u8 reserved_at_2e1[0x1f]; 8544 8545 u8 reserved_at_300[0x580]; 8546 8547 u8 pas[][0x40]; 8548 }; 8549 8550 struct mlx5_ifc_create_tis_out_bits { 8551 u8 status[0x8]; 8552 u8 reserved_at_8[0x18]; 8553 8554 u8 syndrome[0x20]; 8555 8556 u8 reserved_at_40[0x8]; 8557 u8 tisn[0x18]; 8558 8559 u8 reserved_at_60[0x20]; 8560 }; 8561 8562 struct mlx5_ifc_create_tis_in_bits { 8563 u8 opcode[0x10]; 8564 u8 uid[0x10]; 8565 8566 u8 reserved_at_20[0x10]; 8567 u8 op_mod[0x10]; 8568 8569 u8 reserved_at_40[0xc0]; 8570 8571 struct mlx5_ifc_tisc_bits ctx; 8572 }; 8573 8574 struct mlx5_ifc_create_tir_out_bits { 8575 u8 status[0x8]; 8576 u8 icm_address_63_40[0x18]; 8577 8578 u8 syndrome[0x20]; 8579 8580 u8 icm_address_39_32[0x8]; 8581 u8 tirn[0x18]; 8582 8583 u8 icm_address_31_0[0x20]; 8584 }; 8585 8586 struct mlx5_ifc_create_tir_in_bits { 8587 u8 opcode[0x10]; 8588 u8 uid[0x10]; 8589 8590 u8 reserved_at_20[0x10]; 8591 u8 op_mod[0x10]; 8592 8593 u8 reserved_at_40[0xc0]; 8594 8595 struct mlx5_ifc_tirc_bits ctx; 8596 }; 8597 8598 struct mlx5_ifc_create_srq_out_bits { 8599 u8 status[0x8]; 8600 u8 reserved_at_8[0x18]; 8601 8602 u8 syndrome[0x20]; 8603 8604 u8 reserved_at_40[0x8]; 8605 u8 srqn[0x18]; 8606 8607 u8 reserved_at_60[0x20]; 8608 }; 8609 8610 struct mlx5_ifc_create_srq_in_bits { 8611 u8 opcode[0x10]; 8612 u8 uid[0x10]; 8613 8614 u8 reserved_at_20[0x10]; 8615 u8 op_mod[0x10]; 8616 8617 u8 reserved_at_40[0x40]; 8618 8619 struct mlx5_ifc_srqc_bits srq_context_entry; 8620 8621 u8 reserved_at_280[0x600]; 8622 8623 u8 pas[][0x40]; 8624 }; 8625 8626 struct mlx5_ifc_create_sq_out_bits { 8627 u8 status[0x8]; 8628 u8 reserved_at_8[0x18]; 8629 8630 u8 syndrome[0x20]; 8631 8632 u8 reserved_at_40[0x8]; 8633 u8 sqn[0x18]; 8634 8635 u8 reserved_at_60[0x20]; 8636 }; 8637 8638 struct mlx5_ifc_create_sq_in_bits { 8639 u8 opcode[0x10]; 8640 u8 uid[0x10]; 8641 8642 u8 reserved_at_20[0x10]; 8643 u8 op_mod[0x10]; 8644 8645 u8 reserved_at_40[0xc0]; 8646 8647 struct mlx5_ifc_sqc_bits ctx; 8648 }; 8649 8650 struct mlx5_ifc_create_scheduling_element_out_bits { 8651 u8 status[0x8]; 8652 u8 reserved_at_8[0x18]; 8653 8654 u8 syndrome[0x20]; 8655 8656 u8 reserved_at_40[0x40]; 8657 8658 u8 scheduling_element_id[0x20]; 8659 8660 u8 reserved_at_a0[0x160]; 8661 }; 8662 8663 struct mlx5_ifc_create_scheduling_element_in_bits { 8664 u8 opcode[0x10]; 8665 u8 reserved_at_10[0x10]; 8666 8667 u8 reserved_at_20[0x10]; 8668 u8 op_mod[0x10]; 8669 8670 u8 scheduling_hierarchy[0x8]; 8671 u8 reserved_at_48[0x18]; 8672 8673 u8 reserved_at_60[0xa0]; 8674 8675 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8676 8677 u8 reserved_at_300[0x100]; 8678 }; 8679 8680 struct mlx5_ifc_create_rqt_out_bits { 8681 u8 status[0x8]; 8682 u8 reserved_at_8[0x18]; 8683 8684 u8 syndrome[0x20]; 8685 8686 u8 reserved_at_40[0x8]; 8687 u8 rqtn[0x18]; 8688 8689 u8 reserved_at_60[0x20]; 8690 }; 8691 8692 struct mlx5_ifc_create_rqt_in_bits { 8693 u8 opcode[0x10]; 8694 u8 uid[0x10]; 8695 8696 u8 reserved_at_20[0x10]; 8697 u8 op_mod[0x10]; 8698 8699 u8 reserved_at_40[0xc0]; 8700 8701 struct mlx5_ifc_rqtc_bits rqt_context; 8702 }; 8703 8704 struct mlx5_ifc_create_rq_out_bits { 8705 u8 status[0x8]; 8706 u8 reserved_at_8[0x18]; 8707 8708 u8 syndrome[0x20]; 8709 8710 u8 reserved_at_40[0x8]; 8711 u8 rqn[0x18]; 8712 8713 u8 reserved_at_60[0x20]; 8714 }; 8715 8716 struct mlx5_ifc_create_rq_in_bits { 8717 u8 opcode[0x10]; 8718 u8 uid[0x10]; 8719 8720 u8 reserved_at_20[0x10]; 8721 u8 op_mod[0x10]; 8722 8723 u8 reserved_at_40[0xc0]; 8724 8725 struct mlx5_ifc_rqc_bits ctx; 8726 }; 8727 8728 struct mlx5_ifc_create_rmp_out_bits { 8729 u8 status[0x8]; 8730 u8 reserved_at_8[0x18]; 8731 8732 u8 syndrome[0x20]; 8733 8734 u8 reserved_at_40[0x8]; 8735 u8 rmpn[0x18]; 8736 8737 u8 reserved_at_60[0x20]; 8738 }; 8739 8740 struct mlx5_ifc_create_rmp_in_bits { 8741 u8 opcode[0x10]; 8742 u8 uid[0x10]; 8743 8744 u8 reserved_at_20[0x10]; 8745 u8 op_mod[0x10]; 8746 8747 u8 reserved_at_40[0xc0]; 8748 8749 struct mlx5_ifc_rmpc_bits ctx; 8750 }; 8751 8752 struct mlx5_ifc_create_qp_out_bits { 8753 u8 status[0x8]; 8754 u8 reserved_at_8[0x18]; 8755 8756 u8 syndrome[0x20]; 8757 8758 u8 reserved_at_40[0x8]; 8759 u8 qpn[0x18]; 8760 8761 u8 ece[0x20]; 8762 }; 8763 8764 struct mlx5_ifc_create_qp_in_bits { 8765 u8 opcode[0x10]; 8766 u8 uid[0x10]; 8767 8768 u8 reserved_at_20[0x10]; 8769 u8 op_mod[0x10]; 8770 8771 u8 qpc_ext[0x1]; 8772 u8 reserved_at_41[0x7]; 8773 u8 input_qpn[0x18]; 8774 8775 u8 reserved_at_60[0x20]; 8776 u8 opt_param_mask[0x20]; 8777 8778 u8 ece[0x20]; 8779 8780 struct mlx5_ifc_qpc_bits qpc; 8781 8782 u8 reserved_at_800[0x60]; 8783 8784 u8 wq_umem_valid[0x1]; 8785 u8 reserved_at_861[0x1f]; 8786 8787 u8 pas[][0x40]; 8788 }; 8789 8790 struct mlx5_ifc_create_psv_out_bits { 8791 u8 status[0x8]; 8792 u8 reserved_at_8[0x18]; 8793 8794 u8 syndrome[0x20]; 8795 8796 u8 reserved_at_40[0x40]; 8797 8798 u8 reserved_at_80[0x8]; 8799 u8 psv0_index[0x18]; 8800 8801 u8 reserved_at_a0[0x8]; 8802 u8 psv1_index[0x18]; 8803 8804 u8 reserved_at_c0[0x8]; 8805 u8 psv2_index[0x18]; 8806 8807 u8 reserved_at_e0[0x8]; 8808 u8 psv3_index[0x18]; 8809 }; 8810 8811 struct mlx5_ifc_create_psv_in_bits { 8812 u8 opcode[0x10]; 8813 u8 reserved_at_10[0x10]; 8814 8815 u8 reserved_at_20[0x10]; 8816 u8 op_mod[0x10]; 8817 8818 u8 num_psv[0x4]; 8819 u8 reserved_at_44[0x4]; 8820 u8 pd[0x18]; 8821 8822 u8 reserved_at_60[0x20]; 8823 }; 8824 8825 struct mlx5_ifc_create_mkey_out_bits { 8826 u8 status[0x8]; 8827 u8 reserved_at_8[0x18]; 8828 8829 u8 syndrome[0x20]; 8830 8831 u8 reserved_at_40[0x8]; 8832 u8 mkey_index[0x18]; 8833 8834 u8 reserved_at_60[0x20]; 8835 }; 8836 8837 struct mlx5_ifc_create_mkey_in_bits { 8838 u8 opcode[0x10]; 8839 u8 uid[0x10]; 8840 8841 u8 reserved_at_20[0x10]; 8842 u8 op_mod[0x10]; 8843 8844 u8 reserved_at_40[0x20]; 8845 8846 u8 pg_access[0x1]; 8847 u8 mkey_umem_valid[0x1]; 8848 u8 reserved_at_62[0x1e]; 8849 8850 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8851 8852 u8 reserved_at_280[0x80]; 8853 8854 u8 translations_octword_actual_size[0x20]; 8855 8856 u8 reserved_at_320[0x560]; 8857 8858 u8 klm_pas_mtt[][0x20]; 8859 }; 8860 8861 enum { 8862 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8863 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8864 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8865 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8866 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8867 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8868 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8869 }; 8870 8871 struct mlx5_ifc_create_flow_table_out_bits { 8872 u8 status[0x8]; 8873 u8 icm_address_63_40[0x18]; 8874 8875 u8 syndrome[0x20]; 8876 8877 u8 icm_address_39_32[0x8]; 8878 u8 table_id[0x18]; 8879 8880 u8 icm_address_31_0[0x20]; 8881 }; 8882 8883 struct mlx5_ifc_create_flow_table_in_bits { 8884 u8 opcode[0x10]; 8885 u8 uid[0x10]; 8886 8887 u8 reserved_at_20[0x10]; 8888 u8 op_mod[0x10]; 8889 8890 u8 other_vport[0x1]; 8891 u8 reserved_at_41[0xf]; 8892 u8 vport_number[0x10]; 8893 8894 u8 reserved_at_60[0x20]; 8895 8896 u8 table_type[0x8]; 8897 u8 reserved_at_88[0x18]; 8898 8899 u8 reserved_at_a0[0x20]; 8900 8901 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8902 }; 8903 8904 struct mlx5_ifc_create_flow_group_out_bits { 8905 u8 status[0x8]; 8906 u8 reserved_at_8[0x18]; 8907 8908 u8 syndrome[0x20]; 8909 8910 u8 reserved_at_40[0x8]; 8911 u8 group_id[0x18]; 8912 8913 u8 reserved_at_60[0x20]; 8914 }; 8915 8916 enum { 8917 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8918 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8919 }; 8920 8921 enum { 8922 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8923 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8924 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8925 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8926 }; 8927 8928 struct mlx5_ifc_create_flow_group_in_bits { 8929 u8 opcode[0x10]; 8930 u8 reserved_at_10[0x10]; 8931 8932 u8 reserved_at_20[0x10]; 8933 u8 op_mod[0x10]; 8934 8935 u8 other_vport[0x1]; 8936 u8 reserved_at_41[0xf]; 8937 u8 vport_number[0x10]; 8938 8939 u8 reserved_at_60[0x20]; 8940 8941 u8 table_type[0x8]; 8942 u8 reserved_at_88[0x4]; 8943 u8 group_type[0x4]; 8944 u8 reserved_at_90[0x10]; 8945 8946 u8 reserved_at_a0[0x8]; 8947 u8 table_id[0x18]; 8948 8949 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8950 8951 u8 reserved_at_c1[0x1f]; 8952 8953 u8 start_flow_index[0x20]; 8954 8955 u8 reserved_at_100[0x20]; 8956 8957 u8 end_flow_index[0x20]; 8958 8959 u8 reserved_at_140[0x10]; 8960 u8 match_definer_id[0x10]; 8961 8962 u8 reserved_at_160[0x80]; 8963 8964 u8 reserved_at_1e0[0x18]; 8965 u8 match_criteria_enable[0x8]; 8966 8967 struct mlx5_ifc_fte_match_param_bits match_criteria; 8968 8969 u8 reserved_at_1200[0xe00]; 8970 }; 8971 8972 struct mlx5_ifc_create_eq_out_bits { 8973 u8 status[0x8]; 8974 u8 reserved_at_8[0x18]; 8975 8976 u8 syndrome[0x20]; 8977 8978 u8 reserved_at_40[0x18]; 8979 u8 eq_number[0x8]; 8980 8981 u8 reserved_at_60[0x20]; 8982 }; 8983 8984 struct mlx5_ifc_create_eq_in_bits { 8985 u8 opcode[0x10]; 8986 u8 uid[0x10]; 8987 8988 u8 reserved_at_20[0x10]; 8989 u8 op_mod[0x10]; 8990 8991 u8 reserved_at_40[0x40]; 8992 8993 struct mlx5_ifc_eqc_bits eq_context_entry; 8994 8995 u8 reserved_at_280[0x40]; 8996 8997 u8 event_bitmask[4][0x40]; 8998 8999 u8 reserved_at_3c0[0x4c0]; 9000 9001 u8 pas[][0x40]; 9002 }; 9003 9004 struct mlx5_ifc_create_dct_out_bits { 9005 u8 status[0x8]; 9006 u8 reserved_at_8[0x18]; 9007 9008 u8 syndrome[0x20]; 9009 9010 u8 reserved_at_40[0x8]; 9011 u8 dctn[0x18]; 9012 9013 u8 ece[0x20]; 9014 }; 9015 9016 struct mlx5_ifc_create_dct_in_bits { 9017 u8 opcode[0x10]; 9018 u8 uid[0x10]; 9019 9020 u8 reserved_at_20[0x10]; 9021 u8 op_mod[0x10]; 9022 9023 u8 reserved_at_40[0x40]; 9024 9025 struct mlx5_ifc_dctc_bits dct_context_entry; 9026 9027 u8 reserved_at_280[0x180]; 9028 }; 9029 9030 struct mlx5_ifc_create_cq_out_bits { 9031 u8 status[0x8]; 9032 u8 reserved_at_8[0x18]; 9033 9034 u8 syndrome[0x20]; 9035 9036 u8 reserved_at_40[0x8]; 9037 u8 cqn[0x18]; 9038 9039 u8 reserved_at_60[0x20]; 9040 }; 9041 9042 struct mlx5_ifc_create_cq_in_bits { 9043 u8 opcode[0x10]; 9044 u8 uid[0x10]; 9045 9046 u8 reserved_at_20[0x10]; 9047 u8 op_mod[0x10]; 9048 9049 u8 reserved_at_40[0x40]; 9050 9051 struct mlx5_ifc_cqc_bits cq_context; 9052 9053 u8 reserved_at_280[0x60]; 9054 9055 u8 cq_umem_valid[0x1]; 9056 u8 reserved_at_2e1[0x59f]; 9057 9058 u8 pas[][0x40]; 9059 }; 9060 9061 struct mlx5_ifc_config_int_moderation_out_bits { 9062 u8 status[0x8]; 9063 u8 reserved_at_8[0x18]; 9064 9065 u8 syndrome[0x20]; 9066 9067 u8 reserved_at_40[0x4]; 9068 u8 min_delay[0xc]; 9069 u8 int_vector[0x10]; 9070 9071 u8 reserved_at_60[0x20]; 9072 }; 9073 9074 enum { 9075 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9076 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9077 }; 9078 9079 struct mlx5_ifc_config_int_moderation_in_bits { 9080 u8 opcode[0x10]; 9081 u8 reserved_at_10[0x10]; 9082 9083 u8 reserved_at_20[0x10]; 9084 u8 op_mod[0x10]; 9085 9086 u8 reserved_at_40[0x4]; 9087 u8 min_delay[0xc]; 9088 u8 int_vector[0x10]; 9089 9090 u8 reserved_at_60[0x20]; 9091 }; 9092 9093 struct mlx5_ifc_attach_to_mcg_out_bits { 9094 u8 status[0x8]; 9095 u8 reserved_at_8[0x18]; 9096 9097 u8 syndrome[0x20]; 9098 9099 u8 reserved_at_40[0x40]; 9100 }; 9101 9102 struct mlx5_ifc_attach_to_mcg_in_bits { 9103 u8 opcode[0x10]; 9104 u8 uid[0x10]; 9105 9106 u8 reserved_at_20[0x10]; 9107 u8 op_mod[0x10]; 9108 9109 u8 reserved_at_40[0x8]; 9110 u8 qpn[0x18]; 9111 9112 u8 reserved_at_60[0x20]; 9113 9114 u8 multicast_gid[16][0x8]; 9115 }; 9116 9117 struct mlx5_ifc_arm_xrq_out_bits { 9118 u8 status[0x8]; 9119 u8 reserved_at_8[0x18]; 9120 9121 u8 syndrome[0x20]; 9122 9123 u8 reserved_at_40[0x40]; 9124 }; 9125 9126 struct mlx5_ifc_arm_xrq_in_bits { 9127 u8 opcode[0x10]; 9128 u8 reserved_at_10[0x10]; 9129 9130 u8 reserved_at_20[0x10]; 9131 u8 op_mod[0x10]; 9132 9133 u8 reserved_at_40[0x8]; 9134 u8 xrqn[0x18]; 9135 9136 u8 reserved_at_60[0x10]; 9137 u8 lwm[0x10]; 9138 }; 9139 9140 struct mlx5_ifc_arm_xrc_srq_out_bits { 9141 u8 status[0x8]; 9142 u8 reserved_at_8[0x18]; 9143 9144 u8 syndrome[0x20]; 9145 9146 u8 reserved_at_40[0x40]; 9147 }; 9148 9149 enum { 9150 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9151 }; 9152 9153 struct mlx5_ifc_arm_xrc_srq_in_bits { 9154 u8 opcode[0x10]; 9155 u8 uid[0x10]; 9156 9157 u8 reserved_at_20[0x10]; 9158 u8 op_mod[0x10]; 9159 9160 u8 reserved_at_40[0x8]; 9161 u8 xrc_srqn[0x18]; 9162 9163 u8 reserved_at_60[0x10]; 9164 u8 lwm[0x10]; 9165 }; 9166 9167 struct mlx5_ifc_arm_rq_out_bits { 9168 u8 status[0x8]; 9169 u8 reserved_at_8[0x18]; 9170 9171 u8 syndrome[0x20]; 9172 9173 u8 reserved_at_40[0x40]; 9174 }; 9175 9176 enum { 9177 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9178 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9179 }; 9180 9181 struct mlx5_ifc_arm_rq_in_bits { 9182 u8 opcode[0x10]; 9183 u8 uid[0x10]; 9184 9185 u8 reserved_at_20[0x10]; 9186 u8 op_mod[0x10]; 9187 9188 u8 reserved_at_40[0x8]; 9189 u8 srq_number[0x18]; 9190 9191 u8 reserved_at_60[0x10]; 9192 u8 lwm[0x10]; 9193 }; 9194 9195 struct mlx5_ifc_arm_dct_out_bits { 9196 u8 status[0x8]; 9197 u8 reserved_at_8[0x18]; 9198 9199 u8 syndrome[0x20]; 9200 9201 u8 reserved_at_40[0x40]; 9202 }; 9203 9204 struct mlx5_ifc_arm_dct_in_bits { 9205 u8 opcode[0x10]; 9206 u8 reserved_at_10[0x10]; 9207 9208 u8 reserved_at_20[0x10]; 9209 u8 op_mod[0x10]; 9210 9211 u8 reserved_at_40[0x8]; 9212 u8 dct_number[0x18]; 9213 9214 u8 reserved_at_60[0x20]; 9215 }; 9216 9217 struct mlx5_ifc_alloc_xrcd_out_bits { 9218 u8 status[0x8]; 9219 u8 reserved_at_8[0x18]; 9220 9221 u8 syndrome[0x20]; 9222 9223 u8 reserved_at_40[0x8]; 9224 u8 xrcd[0x18]; 9225 9226 u8 reserved_at_60[0x20]; 9227 }; 9228 9229 struct mlx5_ifc_alloc_xrcd_in_bits { 9230 u8 opcode[0x10]; 9231 u8 uid[0x10]; 9232 9233 u8 reserved_at_20[0x10]; 9234 u8 op_mod[0x10]; 9235 9236 u8 reserved_at_40[0x40]; 9237 }; 9238 9239 struct mlx5_ifc_alloc_uar_out_bits { 9240 u8 status[0x8]; 9241 u8 reserved_at_8[0x18]; 9242 9243 u8 syndrome[0x20]; 9244 9245 u8 reserved_at_40[0x8]; 9246 u8 uar[0x18]; 9247 9248 u8 reserved_at_60[0x20]; 9249 }; 9250 9251 struct mlx5_ifc_alloc_uar_in_bits { 9252 u8 opcode[0x10]; 9253 u8 uid[0x10]; 9254 9255 u8 reserved_at_20[0x10]; 9256 u8 op_mod[0x10]; 9257 9258 u8 reserved_at_40[0x40]; 9259 }; 9260 9261 struct mlx5_ifc_alloc_transport_domain_out_bits { 9262 u8 status[0x8]; 9263 u8 reserved_at_8[0x18]; 9264 9265 u8 syndrome[0x20]; 9266 9267 u8 reserved_at_40[0x8]; 9268 u8 transport_domain[0x18]; 9269 9270 u8 reserved_at_60[0x20]; 9271 }; 9272 9273 struct mlx5_ifc_alloc_transport_domain_in_bits { 9274 u8 opcode[0x10]; 9275 u8 uid[0x10]; 9276 9277 u8 reserved_at_20[0x10]; 9278 u8 op_mod[0x10]; 9279 9280 u8 reserved_at_40[0x40]; 9281 }; 9282 9283 struct mlx5_ifc_alloc_q_counter_out_bits { 9284 u8 status[0x8]; 9285 u8 reserved_at_8[0x18]; 9286 9287 u8 syndrome[0x20]; 9288 9289 u8 reserved_at_40[0x18]; 9290 u8 counter_set_id[0x8]; 9291 9292 u8 reserved_at_60[0x20]; 9293 }; 9294 9295 struct mlx5_ifc_alloc_q_counter_in_bits { 9296 u8 opcode[0x10]; 9297 u8 uid[0x10]; 9298 9299 u8 reserved_at_20[0x10]; 9300 u8 op_mod[0x10]; 9301 9302 u8 reserved_at_40[0x40]; 9303 }; 9304 9305 struct mlx5_ifc_alloc_pd_out_bits { 9306 u8 status[0x8]; 9307 u8 reserved_at_8[0x18]; 9308 9309 u8 syndrome[0x20]; 9310 9311 u8 reserved_at_40[0x8]; 9312 u8 pd[0x18]; 9313 9314 u8 reserved_at_60[0x20]; 9315 }; 9316 9317 struct mlx5_ifc_alloc_pd_in_bits { 9318 u8 opcode[0x10]; 9319 u8 uid[0x10]; 9320 9321 u8 reserved_at_20[0x10]; 9322 u8 op_mod[0x10]; 9323 9324 u8 reserved_at_40[0x40]; 9325 }; 9326 9327 struct mlx5_ifc_alloc_flow_counter_out_bits { 9328 u8 status[0x8]; 9329 u8 reserved_at_8[0x18]; 9330 9331 u8 syndrome[0x20]; 9332 9333 u8 flow_counter_id[0x20]; 9334 9335 u8 reserved_at_60[0x20]; 9336 }; 9337 9338 struct mlx5_ifc_alloc_flow_counter_in_bits { 9339 u8 opcode[0x10]; 9340 u8 reserved_at_10[0x10]; 9341 9342 u8 reserved_at_20[0x10]; 9343 u8 op_mod[0x10]; 9344 9345 u8 reserved_at_40[0x33]; 9346 u8 flow_counter_bulk_log_size[0x5]; 9347 u8 flow_counter_bulk[0x8]; 9348 }; 9349 9350 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9351 u8 status[0x8]; 9352 u8 reserved_at_8[0x18]; 9353 9354 u8 syndrome[0x20]; 9355 9356 u8 reserved_at_40[0x40]; 9357 }; 9358 9359 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9360 u8 opcode[0x10]; 9361 u8 reserved_at_10[0x10]; 9362 9363 u8 reserved_at_20[0x10]; 9364 u8 op_mod[0x10]; 9365 9366 u8 reserved_at_40[0x20]; 9367 9368 u8 reserved_at_60[0x10]; 9369 u8 vxlan_udp_port[0x10]; 9370 }; 9371 9372 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9373 u8 status[0x8]; 9374 u8 reserved_at_8[0x18]; 9375 9376 u8 syndrome[0x20]; 9377 9378 u8 reserved_at_40[0x40]; 9379 }; 9380 9381 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9382 u8 rate_limit[0x20]; 9383 9384 u8 burst_upper_bound[0x20]; 9385 9386 u8 reserved_at_40[0x10]; 9387 u8 typical_packet_size[0x10]; 9388 9389 u8 reserved_at_60[0x120]; 9390 }; 9391 9392 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9393 u8 opcode[0x10]; 9394 u8 uid[0x10]; 9395 9396 u8 reserved_at_20[0x10]; 9397 u8 op_mod[0x10]; 9398 9399 u8 reserved_at_40[0x10]; 9400 u8 rate_limit_index[0x10]; 9401 9402 u8 reserved_at_60[0x20]; 9403 9404 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9405 }; 9406 9407 struct mlx5_ifc_access_register_out_bits { 9408 u8 status[0x8]; 9409 u8 reserved_at_8[0x18]; 9410 9411 u8 syndrome[0x20]; 9412 9413 u8 reserved_at_40[0x40]; 9414 9415 u8 register_data[][0x20]; 9416 }; 9417 9418 enum { 9419 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9420 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9421 }; 9422 9423 struct mlx5_ifc_access_register_in_bits { 9424 u8 opcode[0x10]; 9425 u8 reserved_at_10[0x10]; 9426 9427 u8 reserved_at_20[0x10]; 9428 u8 op_mod[0x10]; 9429 9430 u8 reserved_at_40[0x10]; 9431 u8 register_id[0x10]; 9432 9433 u8 argument[0x20]; 9434 9435 u8 register_data[][0x20]; 9436 }; 9437 9438 struct mlx5_ifc_sltp_reg_bits { 9439 u8 status[0x4]; 9440 u8 version[0x4]; 9441 u8 local_port[0x8]; 9442 u8 pnat[0x2]; 9443 u8 reserved_at_12[0x2]; 9444 u8 lane[0x4]; 9445 u8 reserved_at_18[0x8]; 9446 9447 u8 reserved_at_20[0x20]; 9448 9449 u8 reserved_at_40[0x7]; 9450 u8 polarity[0x1]; 9451 u8 ob_tap0[0x8]; 9452 u8 ob_tap1[0x8]; 9453 u8 ob_tap2[0x8]; 9454 9455 u8 reserved_at_60[0xc]; 9456 u8 ob_preemp_mode[0x4]; 9457 u8 ob_reg[0x8]; 9458 u8 ob_bias[0x8]; 9459 9460 u8 reserved_at_80[0x20]; 9461 }; 9462 9463 struct mlx5_ifc_slrg_reg_bits { 9464 u8 status[0x4]; 9465 u8 version[0x4]; 9466 u8 local_port[0x8]; 9467 u8 pnat[0x2]; 9468 u8 reserved_at_12[0x2]; 9469 u8 lane[0x4]; 9470 u8 reserved_at_18[0x8]; 9471 9472 u8 time_to_link_up[0x10]; 9473 u8 reserved_at_30[0xc]; 9474 u8 grade_lane_speed[0x4]; 9475 9476 u8 grade_version[0x8]; 9477 u8 grade[0x18]; 9478 9479 u8 reserved_at_60[0x4]; 9480 u8 height_grade_type[0x4]; 9481 u8 height_grade[0x18]; 9482 9483 u8 height_dz[0x10]; 9484 u8 height_dv[0x10]; 9485 9486 u8 reserved_at_a0[0x10]; 9487 u8 height_sigma[0x10]; 9488 9489 u8 reserved_at_c0[0x20]; 9490 9491 u8 reserved_at_e0[0x4]; 9492 u8 phase_grade_type[0x4]; 9493 u8 phase_grade[0x18]; 9494 9495 u8 reserved_at_100[0x8]; 9496 u8 phase_eo_pos[0x8]; 9497 u8 reserved_at_110[0x8]; 9498 u8 phase_eo_neg[0x8]; 9499 9500 u8 ffe_set_tested[0x10]; 9501 u8 test_errors_per_lane[0x10]; 9502 }; 9503 9504 struct mlx5_ifc_pvlc_reg_bits { 9505 u8 reserved_at_0[0x8]; 9506 u8 local_port[0x8]; 9507 u8 reserved_at_10[0x10]; 9508 9509 u8 reserved_at_20[0x1c]; 9510 u8 vl_hw_cap[0x4]; 9511 9512 u8 reserved_at_40[0x1c]; 9513 u8 vl_admin[0x4]; 9514 9515 u8 reserved_at_60[0x1c]; 9516 u8 vl_operational[0x4]; 9517 }; 9518 9519 struct mlx5_ifc_pude_reg_bits { 9520 u8 swid[0x8]; 9521 u8 local_port[0x8]; 9522 u8 reserved_at_10[0x4]; 9523 u8 admin_status[0x4]; 9524 u8 reserved_at_18[0x4]; 9525 u8 oper_status[0x4]; 9526 9527 u8 reserved_at_20[0x60]; 9528 }; 9529 9530 struct mlx5_ifc_ptys_reg_bits { 9531 u8 reserved_at_0[0x1]; 9532 u8 an_disable_admin[0x1]; 9533 u8 an_disable_cap[0x1]; 9534 u8 reserved_at_3[0x5]; 9535 u8 local_port[0x8]; 9536 u8 reserved_at_10[0xd]; 9537 u8 proto_mask[0x3]; 9538 9539 u8 an_status[0x4]; 9540 u8 reserved_at_24[0xc]; 9541 u8 data_rate_oper[0x10]; 9542 9543 u8 ext_eth_proto_capability[0x20]; 9544 9545 u8 eth_proto_capability[0x20]; 9546 9547 u8 ib_link_width_capability[0x10]; 9548 u8 ib_proto_capability[0x10]; 9549 9550 u8 ext_eth_proto_admin[0x20]; 9551 9552 u8 eth_proto_admin[0x20]; 9553 9554 u8 ib_link_width_admin[0x10]; 9555 u8 ib_proto_admin[0x10]; 9556 9557 u8 ext_eth_proto_oper[0x20]; 9558 9559 u8 eth_proto_oper[0x20]; 9560 9561 u8 ib_link_width_oper[0x10]; 9562 u8 ib_proto_oper[0x10]; 9563 9564 u8 reserved_at_160[0x1c]; 9565 u8 connector_type[0x4]; 9566 9567 u8 eth_proto_lp_advertise[0x20]; 9568 9569 u8 reserved_at_1a0[0x60]; 9570 }; 9571 9572 struct mlx5_ifc_mlcr_reg_bits { 9573 u8 reserved_at_0[0x8]; 9574 u8 local_port[0x8]; 9575 u8 reserved_at_10[0x20]; 9576 9577 u8 beacon_duration[0x10]; 9578 u8 reserved_at_40[0x10]; 9579 9580 u8 beacon_remain[0x10]; 9581 }; 9582 9583 struct mlx5_ifc_ptas_reg_bits { 9584 u8 reserved_at_0[0x20]; 9585 9586 u8 algorithm_options[0x10]; 9587 u8 reserved_at_30[0x4]; 9588 u8 repetitions_mode[0x4]; 9589 u8 num_of_repetitions[0x8]; 9590 9591 u8 grade_version[0x8]; 9592 u8 height_grade_type[0x4]; 9593 u8 phase_grade_type[0x4]; 9594 u8 height_grade_weight[0x8]; 9595 u8 phase_grade_weight[0x8]; 9596 9597 u8 gisim_measure_bits[0x10]; 9598 u8 adaptive_tap_measure_bits[0x10]; 9599 9600 u8 ber_bath_high_error_threshold[0x10]; 9601 u8 ber_bath_mid_error_threshold[0x10]; 9602 9603 u8 ber_bath_low_error_threshold[0x10]; 9604 u8 one_ratio_high_threshold[0x10]; 9605 9606 u8 one_ratio_high_mid_threshold[0x10]; 9607 u8 one_ratio_low_mid_threshold[0x10]; 9608 9609 u8 one_ratio_low_threshold[0x10]; 9610 u8 ndeo_error_threshold[0x10]; 9611 9612 u8 mixer_offset_step_size[0x10]; 9613 u8 reserved_at_110[0x8]; 9614 u8 mix90_phase_for_voltage_bath[0x8]; 9615 9616 u8 mixer_offset_start[0x10]; 9617 u8 mixer_offset_end[0x10]; 9618 9619 u8 reserved_at_140[0x15]; 9620 u8 ber_test_time[0xb]; 9621 }; 9622 9623 struct mlx5_ifc_pspa_reg_bits { 9624 u8 swid[0x8]; 9625 u8 local_port[0x8]; 9626 u8 sub_port[0x8]; 9627 u8 reserved_at_18[0x8]; 9628 9629 u8 reserved_at_20[0x20]; 9630 }; 9631 9632 struct mlx5_ifc_pqdr_reg_bits { 9633 u8 reserved_at_0[0x8]; 9634 u8 local_port[0x8]; 9635 u8 reserved_at_10[0x5]; 9636 u8 prio[0x3]; 9637 u8 reserved_at_18[0x6]; 9638 u8 mode[0x2]; 9639 9640 u8 reserved_at_20[0x20]; 9641 9642 u8 reserved_at_40[0x10]; 9643 u8 min_threshold[0x10]; 9644 9645 u8 reserved_at_60[0x10]; 9646 u8 max_threshold[0x10]; 9647 9648 u8 reserved_at_80[0x10]; 9649 u8 mark_probability_denominator[0x10]; 9650 9651 u8 reserved_at_a0[0x60]; 9652 }; 9653 9654 struct mlx5_ifc_ppsc_reg_bits { 9655 u8 reserved_at_0[0x8]; 9656 u8 local_port[0x8]; 9657 u8 reserved_at_10[0x10]; 9658 9659 u8 reserved_at_20[0x60]; 9660 9661 u8 reserved_at_80[0x1c]; 9662 u8 wrps_admin[0x4]; 9663 9664 u8 reserved_at_a0[0x1c]; 9665 u8 wrps_status[0x4]; 9666 9667 u8 reserved_at_c0[0x8]; 9668 u8 up_threshold[0x8]; 9669 u8 reserved_at_d0[0x8]; 9670 u8 down_threshold[0x8]; 9671 9672 u8 reserved_at_e0[0x20]; 9673 9674 u8 reserved_at_100[0x1c]; 9675 u8 srps_admin[0x4]; 9676 9677 u8 reserved_at_120[0x1c]; 9678 u8 srps_status[0x4]; 9679 9680 u8 reserved_at_140[0x40]; 9681 }; 9682 9683 struct mlx5_ifc_pplr_reg_bits { 9684 u8 reserved_at_0[0x8]; 9685 u8 local_port[0x8]; 9686 u8 reserved_at_10[0x10]; 9687 9688 u8 reserved_at_20[0x8]; 9689 u8 lb_cap[0x8]; 9690 u8 reserved_at_30[0x8]; 9691 u8 lb_en[0x8]; 9692 }; 9693 9694 struct mlx5_ifc_pplm_reg_bits { 9695 u8 reserved_at_0[0x8]; 9696 u8 local_port[0x8]; 9697 u8 reserved_at_10[0x10]; 9698 9699 u8 reserved_at_20[0x20]; 9700 9701 u8 port_profile_mode[0x8]; 9702 u8 static_port_profile[0x8]; 9703 u8 active_port_profile[0x8]; 9704 u8 reserved_at_58[0x8]; 9705 9706 u8 retransmission_active[0x8]; 9707 u8 fec_mode_active[0x18]; 9708 9709 u8 rs_fec_correction_bypass_cap[0x4]; 9710 u8 reserved_at_84[0x8]; 9711 u8 fec_override_cap_56g[0x4]; 9712 u8 fec_override_cap_100g[0x4]; 9713 u8 fec_override_cap_50g[0x4]; 9714 u8 fec_override_cap_25g[0x4]; 9715 u8 fec_override_cap_10g_40g[0x4]; 9716 9717 u8 rs_fec_correction_bypass_admin[0x4]; 9718 u8 reserved_at_a4[0x8]; 9719 u8 fec_override_admin_56g[0x4]; 9720 u8 fec_override_admin_100g[0x4]; 9721 u8 fec_override_admin_50g[0x4]; 9722 u8 fec_override_admin_25g[0x4]; 9723 u8 fec_override_admin_10g_40g[0x4]; 9724 9725 u8 fec_override_cap_400g_8x[0x10]; 9726 u8 fec_override_cap_200g_4x[0x10]; 9727 9728 u8 fec_override_cap_100g_2x[0x10]; 9729 u8 fec_override_cap_50g_1x[0x10]; 9730 9731 u8 fec_override_admin_400g_8x[0x10]; 9732 u8 fec_override_admin_200g_4x[0x10]; 9733 9734 u8 fec_override_admin_100g_2x[0x10]; 9735 u8 fec_override_admin_50g_1x[0x10]; 9736 9737 u8 reserved_at_140[0x140]; 9738 }; 9739 9740 struct mlx5_ifc_ppcnt_reg_bits { 9741 u8 swid[0x8]; 9742 u8 local_port[0x8]; 9743 u8 pnat[0x2]; 9744 u8 reserved_at_12[0x8]; 9745 u8 grp[0x6]; 9746 9747 u8 clr[0x1]; 9748 u8 reserved_at_21[0x1c]; 9749 u8 prio_tc[0x3]; 9750 9751 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9752 }; 9753 9754 struct mlx5_ifc_mpein_reg_bits { 9755 u8 reserved_at_0[0x2]; 9756 u8 depth[0x6]; 9757 u8 pcie_index[0x8]; 9758 u8 node[0x8]; 9759 u8 reserved_at_18[0x8]; 9760 9761 u8 capability_mask[0x20]; 9762 9763 u8 reserved_at_40[0x8]; 9764 u8 link_width_enabled[0x8]; 9765 u8 link_speed_enabled[0x10]; 9766 9767 u8 lane0_physical_position[0x8]; 9768 u8 link_width_active[0x8]; 9769 u8 link_speed_active[0x10]; 9770 9771 u8 num_of_pfs[0x10]; 9772 u8 num_of_vfs[0x10]; 9773 9774 u8 bdf0[0x10]; 9775 u8 reserved_at_b0[0x10]; 9776 9777 u8 max_read_request_size[0x4]; 9778 u8 max_payload_size[0x4]; 9779 u8 reserved_at_c8[0x5]; 9780 u8 pwr_status[0x3]; 9781 u8 port_type[0x4]; 9782 u8 reserved_at_d4[0xb]; 9783 u8 lane_reversal[0x1]; 9784 9785 u8 reserved_at_e0[0x14]; 9786 u8 pci_power[0xc]; 9787 9788 u8 reserved_at_100[0x20]; 9789 9790 u8 device_status[0x10]; 9791 u8 port_state[0x8]; 9792 u8 reserved_at_138[0x8]; 9793 9794 u8 reserved_at_140[0x10]; 9795 u8 receiver_detect_result[0x10]; 9796 9797 u8 reserved_at_160[0x20]; 9798 }; 9799 9800 struct mlx5_ifc_mpcnt_reg_bits { 9801 u8 reserved_at_0[0x8]; 9802 u8 pcie_index[0x8]; 9803 u8 reserved_at_10[0xa]; 9804 u8 grp[0x6]; 9805 9806 u8 clr[0x1]; 9807 u8 reserved_at_21[0x1f]; 9808 9809 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9810 }; 9811 9812 struct mlx5_ifc_ppad_reg_bits { 9813 u8 reserved_at_0[0x3]; 9814 u8 single_mac[0x1]; 9815 u8 reserved_at_4[0x4]; 9816 u8 local_port[0x8]; 9817 u8 mac_47_32[0x10]; 9818 9819 u8 mac_31_0[0x20]; 9820 9821 u8 reserved_at_40[0x40]; 9822 }; 9823 9824 struct mlx5_ifc_pmtu_reg_bits { 9825 u8 reserved_at_0[0x8]; 9826 u8 local_port[0x8]; 9827 u8 reserved_at_10[0x10]; 9828 9829 u8 max_mtu[0x10]; 9830 u8 reserved_at_30[0x10]; 9831 9832 u8 admin_mtu[0x10]; 9833 u8 reserved_at_50[0x10]; 9834 9835 u8 oper_mtu[0x10]; 9836 u8 reserved_at_70[0x10]; 9837 }; 9838 9839 struct mlx5_ifc_pmpr_reg_bits { 9840 u8 reserved_at_0[0x8]; 9841 u8 module[0x8]; 9842 u8 reserved_at_10[0x10]; 9843 9844 u8 reserved_at_20[0x18]; 9845 u8 attenuation_5g[0x8]; 9846 9847 u8 reserved_at_40[0x18]; 9848 u8 attenuation_7g[0x8]; 9849 9850 u8 reserved_at_60[0x18]; 9851 u8 attenuation_12g[0x8]; 9852 }; 9853 9854 struct mlx5_ifc_pmpe_reg_bits { 9855 u8 reserved_at_0[0x8]; 9856 u8 module[0x8]; 9857 u8 reserved_at_10[0xc]; 9858 u8 module_status[0x4]; 9859 9860 u8 reserved_at_20[0x60]; 9861 }; 9862 9863 struct mlx5_ifc_pmpc_reg_bits { 9864 u8 module_state_updated[32][0x8]; 9865 }; 9866 9867 struct mlx5_ifc_pmlpn_reg_bits { 9868 u8 reserved_at_0[0x4]; 9869 u8 mlpn_status[0x4]; 9870 u8 local_port[0x8]; 9871 u8 reserved_at_10[0x10]; 9872 9873 u8 e[0x1]; 9874 u8 reserved_at_21[0x1f]; 9875 }; 9876 9877 struct mlx5_ifc_pmlp_reg_bits { 9878 u8 rxtx[0x1]; 9879 u8 reserved_at_1[0x7]; 9880 u8 local_port[0x8]; 9881 u8 reserved_at_10[0x8]; 9882 u8 width[0x8]; 9883 9884 u8 lane0_module_mapping[0x20]; 9885 9886 u8 lane1_module_mapping[0x20]; 9887 9888 u8 lane2_module_mapping[0x20]; 9889 9890 u8 lane3_module_mapping[0x20]; 9891 9892 u8 reserved_at_a0[0x160]; 9893 }; 9894 9895 struct mlx5_ifc_pmaos_reg_bits { 9896 u8 reserved_at_0[0x8]; 9897 u8 module[0x8]; 9898 u8 reserved_at_10[0x4]; 9899 u8 admin_status[0x4]; 9900 u8 reserved_at_18[0x4]; 9901 u8 oper_status[0x4]; 9902 9903 u8 ase[0x1]; 9904 u8 ee[0x1]; 9905 u8 reserved_at_22[0x1c]; 9906 u8 e[0x2]; 9907 9908 u8 reserved_at_40[0x40]; 9909 }; 9910 9911 struct mlx5_ifc_plpc_reg_bits { 9912 u8 reserved_at_0[0x4]; 9913 u8 profile_id[0xc]; 9914 u8 reserved_at_10[0x4]; 9915 u8 proto_mask[0x4]; 9916 u8 reserved_at_18[0x8]; 9917 9918 u8 reserved_at_20[0x10]; 9919 u8 lane_speed[0x10]; 9920 9921 u8 reserved_at_40[0x17]; 9922 u8 lpbf[0x1]; 9923 u8 fec_mode_policy[0x8]; 9924 9925 u8 retransmission_capability[0x8]; 9926 u8 fec_mode_capability[0x18]; 9927 9928 u8 retransmission_support_admin[0x8]; 9929 u8 fec_mode_support_admin[0x18]; 9930 9931 u8 retransmission_request_admin[0x8]; 9932 u8 fec_mode_request_admin[0x18]; 9933 9934 u8 reserved_at_c0[0x80]; 9935 }; 9936 9937 struct mlx5_ifc_plib_reg_bits { 9938 u8 reserved_at_0[0x8]; 9939 u8 local_port[0x8]; 9940 u8 reserved_at_10[0x8]; 9941 u8 ib_port[0x8]; 9942 9943 u8 reserved_at_20[0x60]; 9944 }; 9945 9946 struct mlx5_ifc_plbf_reg_bits { 9947 u8 reserved_at_0[0x8]; 9948 u8 local_port[0x8]; 9949 u8 reserved_at_10[0xd]; 9950 u8 lbf_mode[0x3]; 9951 9952 u8 reserved_at_20[0x20]; 9953 }; 9954 9955 struct mlx5_ifc_pipg_reg_bits { 9956 u8 reserved_at_0[0x8]; 9957 u8 local_port[0x8]; 9958 u8 reserved_at_10[0x10]; 9959 9960 u8 dic[0x1]; 9961 u8 reserved_at_21[0x19]; 9962 u8 ipg[0x4]; 9963 u8 reserved_at_3e[0x2]; 9964 }; 9965 9966 struct mlx5_ifc_pifr_reg_bits { 9967 u8 reserved_at_0[0x8]; 9968 u8 local_port[0x8]; 9969 u8 reserved_at_10[0x10]; 9970 9971 u8 reserved_at_20[0xe0]; 9972 9973 u8 port_filter[8][0x20]; 9974 9975 u8 port_filter_update_en[8][0x20]; 9976 }; 9977 9978 struct mlx5_ifc_pfcc_reg_bits { 9979 u8 reserved_at_0[0x8]; 9980 u8 local_port[0x8]; 9981 u8 reserved_at_10[0xb]; 9982 u8 ppan_mask_n[0x1]; 9983 u8 minor_stall_mask[0x1]; 9984 u8 critical_stall_mask[0x1]; 9985 u8 reserved_at_1e[0x2]; 9986 9987 u8 ppan[0x4]; 9988 u8 reserved_at_24[0x4]; 9989 u8 prio_mask_tx[0x8]; 9990 u8 reserved_at_30[0x8]; 9991 u8 prio_mask_rx[0x8]; 9992 9993 u8 pptx[0x1]; 9994 u8 aptx[0x1]; 9995 u8 pptx_mask_n[0x1]; 9996 u8 reserved_at_43[0x5]; 9997 u8 pfctx[0x8]; 9998 u8 reserved_at_50[0x10]; 9999 10000 u8 pprx[0x1]; 10001 u8 aprx[0x1]; 10002 u8 pprx_mask_n[0x1]; 10003 u8 reserved_at_63[0x5]; 10004 u8 pfcrx[0x8]; 10005 u8 reserved_at_70[0x10]; 10006 10007 u8 device_stall_minor_watermark[0x10]; 10008 u8 device_stall_critical_watermark[0x10]; 10009 10010 u8 reserved_at_a0[0x60]; 10011 }; 10012 10013 struct mlx5_ifc_pelc_reg_bits { 10014 u8 op[0x4]; 10015 u8 reserved_at_4[0x4]; 10016 u8 local_port[0x8]; 10017 u8 reserved_at_10[0x10]; 10018 10019 u8 op_admin[0x8]; 10020 u8 op_capability[0x8]; 10021 u8 op_request[0x8]; 10022 u8 op_active[0x8]; 10023 10024 u8 admin[0x40]; 10025 10026 u8 capability[0x40]; 10027 10028 u8 request[0x40]; 10029 10030 u8 active[0x40]; 10031 10032 u8 reserved_at_140[0x80]; 10033 }; 10034 10035 struct mlx5_ifc_peir_reg_bits { 10036 u8 reserved_at_0[0x8]; 10037 u8 local_port[0x8]; 10038 u8 reserved_at_10[0x10]; 10039 10040 u8 reserved_at_20[0xc]; 10041 u8 error_count[0x4]; 10042 u8 reserved_at_30[0x10]; 10043 10044 u8 reserved_at_40[0xc]; 10045 u8 lane[0x4]; 10046 u8 reserved_at_50[0x8]; 10047 u8 error_type[0x8]; 10048 }; 10049 10050 struct mlx5_ifc_mpegc_reg_bits { 10051 u8 reserved_at_0[0x30]; 10052 u8 field_select[0x10]; 10053 10054 u8 tx_overflow_sense[0x1]; 10055 u8 mark_cqe[0x1]; 10056 u8 mark_cnp[0x1]; 10057 u8 reserved_at_43[0x1b]; 10058 u8 tx_lossy_overflow_oper[0x2]; 10059 10060 u8 reserved_at_60[0x100]; 10061 }; 10062 10063 enum { 10064 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10065 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10066 }; 10067 10068 enum { 10069 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10070 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10071 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10072 }; 10073 10074 struct mlx5_ifc_mtutc_reg_bits { 10075 u8 reserved_at_0[0x5]; 10076 u8 freq_adj_units[0x3]; 10077 u8 reserved_at_8[0x14]; 10078 u8 operation[0x4]; 10079 10080 u8 freq_adjustment[0x20]; 10081 10082 u8 reserved_at_40[0x40]; 10083 10084 u8 utc_sec[0x20]; 10085 10086 u8 reserved_at_a0[0x2]; 10087 u8 utc_nsec[0x1e]; 10088 10089 u8 time_adjustment[0x20]; 10090 }; 10091 10092 struct mlx5_ifc_pcam_enhanced_features_bits { 10093 u8 reserved_at_0[0x68]; 10094 u8 fec_50G_per_lane_in_pplm[0x1]; 10095 u8 reserved_at_69[0x4]; 10096 u8 rx_icrc_encapsulated_counter[0x1]; 10097 u8 reserved_at_6e[0x4]; 10098 u8 ptys_extended_ethernet[0x1]; 10099 u8 reserved_at_73[0x3]; 10100 u8 pfcc_mask[0x1]; 10101 u8 reserved_at_77[0x3]; 10102 u8 per_lane_error_counters[0x1]; 10103 u8 rx_buffer_fullness_counters[0x1]; 10104 u8 ptys_connector_type[0x1]; 10105 u8 reserved_at_7d[0x1]; 10106 u8 ppcnt_discard_group[0x1]; 10107 u8 ppcnt_statistical_group[0x1]; 10108 }; 10109 10110 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10111 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10112 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10113 10114 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10115 u8 pplm[0x1]; 10116 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10117 10118 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10119 u8 pbmc[0x1]; 10120 u8 pptb[0x1]; 10121 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10122 u8 ppcnt[0x1]; 10123 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10124 }; 10125 10126 struct mlx5_ifc_pcam_reg_bits { 10127 u8 reserved_at_0[0x8]; 10128 u8 feature_group[0x8]; 10129 u8 reserved_at_10[0x8]; 10130 u8 access_reg_group[0x8]; 10131 10132 u8 reserved_at_20[0x20]; 10133 10134 union { 10135 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10136 u8 reserved_at_0[0x80]; 10137 } port_access_reg_cap_mask; 10138 10139 u8 reserved_at_c0[0x80]; 10140 10141 union { 10142 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10143 u8 reserved_at_0[0x80]; 10144 } feature_cap_mask; 10145 10146 u8 reserved_at_1c0[0xc0]; 10147 }; 10148 10149 struct mlx5_ifc_mcam_enhanced_features_bits { 10150 u8 reserved_at_0[0x50]; 10151 u8 mtutc_freq_adj_units[0x1]; 10152 u8 mtutc_time_adjustment_extended_range[0x1]; 10153 u8 reserved_at_52[0xb]; 10154 u8 mcia_32dwords[0x1]; 10155 u8 out_pulse_duration_ns[0x1]; 10156 u8 npps_period[0x1]; 10157 u8 reserved_at_60[0xa]; 10158 u8 reset_state[0x1]; 10159 u8 ptpcyc2realtime_modify[0x1]; 10160 u8 reserved_at_6c[0x2]; 10161 u8 pci_status_and_power[0x1]; 10162 u8 reserved_at_6f[0x5]; 10163 u8 mark_tx_action_cnp[0x1]; 10164 u8 mark_tx_action_cqe[0x1]; 10165 u8 dynamic_tx_overflow[0x1]; 10166 u8 reserved_at_77[0x4]; 10167 u8 pcie_outbound_stalled[0x1]; 10168 u8 tx_overflow_buffer_pkt[0x1]; 10169 u8 mtpps_enh_out_per_adj[0x1]; 10170 u8 mtpps_fs[0x1]; 10171 u8 pcie_performance_group[0x1]; 10172 }; 10173 10174 struct mlx5_ifc_mcam_access_reg_bits { 10175 u8 reserved_at_0[0x1c]; 10176 u8 mcda[0x1]; 10177 u8 mcc[0x1]; 10178 u8 mcqi[0x1]; 10179 u8 mcqs[0x1]; 10180 10181 u8 regs_95_to_87[0x9]; 10182 u8 mpegc[0x1]; 10183 u8 mtutc[0x1]; 10184 u8 regs_84_to_68[0x11]; 10185 u8 tracer_registers[0x4]; 10186 10187 u8 regs_63_to_46[0x12]; 10188 u8 mrtc[0x1]; 10189 u8 regs_44_to_32[0xd]; 10190 10191 u8 regs_31_to_0[0x20]; 10192 }; 10193 10194 struct mlx5_ifc_mcam_access_reg_bits1 { 10195 u8 regs_127_to_96[0x20]; 10196 10197 u8 regs_95_to_64[0x20]; 10198 10199 u8 regs_63_to_32[0x20]; 10200 10201 u8 regs_31_to_0[0x20]; 10202 }; 10203 10204 struct mlx5_ifc_mcam_access_reg_bits2 { 10205 u8 regs_127_to_99[0x1d]; 10206 u8 mirc[0x1]; 10207 u8 regs_97_to_96[0x2]; 10208 10209 u8 regs_95_to_64[0x20]; 10210 10211 u8 regs_63_to_32[0x20]; 10212 10213 u8 regs_31_to_0[0x20]; 10214 }; 10215 10216 struct mlx5_ifc_mcam_reg_bits { 10217 u8 reserved_at_0[0x8]; 10218 u8 feature_group[0x8]; 10219 u8 reserved_at_10[0x8]; 10220 u8 access_reg_group[0x8]; 10221 10222 u8 reserved_at_20[0x20]; 10223 10224 union { 10225 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10226 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10227 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10228 u8 reserved_at_0[0x80]; 10229 } mng_access_reg_cap_mask; 10230 10231 u8 reserved_at_c0[0x80]; 10232 10233 union { 10234 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10235 u8 reserved_at_0[0x80]; 10236 } mng_feature_cap_mask; 10237 10238 u8 reserved_at_1c0[0x80]; 10239 }; 10240 10241 struct mlx5_ifc_qcam_access_reg_cap_mask { 10242 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10243 u8 qpdpm[0x1]; 10244 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10245 u8 qdpm[0x1]; 10246 u8 qpts[0x1]; 10247 u8 qcap[0x1]; 10248 u8 qcam_access_reg_cap_mask_0[0x1]; 10249 }; 10250 10251 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10252 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10253 u8 qpts_trust_both[0x1]; 10254 }; 10255 10256 struct mlx5_ifc_qcam_reg_bits { 10257 u8 reserved_at_0[0x8]; 10258 u8 feature_group[0x8]; 10259 u8 reserved_at_10[0x8]; 10260 u8 access_reg_group[0x8]; 10261 u8 reserved_at_20[0x20]; 10262 10263 union { 10264 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10265 u8 reserved_at_0[0x80]; 10266 } qos_access_reg_cap_mask; 10267 10268 u8 reserved_at_c0[0x80]; 10269 10270 union { 10271 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10272 u8 reserved_at_0[0x80]; 10273 } qos_feature_cap_mask; 10274 10275 u8 reserved_at_1c0[0x80]; 10276 }; 10277 10278 struct mlx5_ifc_core_dump_reg_bits { 10279 u8 reserved_at_0[0x18]; 10280 u8 core_dump_type[0x8]; 10281 10282 u8 reserved_at_20[0x30]; 10283 u8 vhca_id[0x10]; 10284 10285 u8 reserved_at_60[0x8]; 10286 u8 qpn[0x18]; 10287 u8 reserved_at_80[0x180]; 10288 }; 10289 10290 struct mlx5_ifc_pcap_reg_bits { 10291 u8 reserved_at_0[0x8]; 10292 u8 local_port[0x8]; 10293 u8 reserved_at_10[0x10]; 10294 10295 u8 port_capability_mask[4][0x20]; 10296 }; 10297 10298 struct mlx5_ifc_paos_reg_bits { 10299 u8 swid[0x8]; 10300 u8 local_port[0x8]; 10301 u8 reserved_at_10[0x4]; 10302 u8 admin_status[0x4]; 10303 u8 reserved_at_18[0x4]; 10304 u8 oper_status[0x4]; 10305 10306 u8 ase[0x1]; 10307 u8 ee[0x1]; 10308 u8 reserved_at_22[0x1c]; 10309 u8 e[0x2]; 10310 10311 u8 reserved_at_40[0x40]; 10312 }; 10313 10314 struct mlx5_ifc_pamp_reg_bits { 10315 u8 reserved_at_0[0x8]; 10316 u8 opamp_group[0x8]; 10317 u8 reserved_at_10[0xc]; 10318 u8 opamp_group_type[0x4]; 10319 10320 u8 start_index[0x10]; 10321 u8 reserved_at_30[0x4]; 10322 u8 num_of_indices[0xc]; 10323 10324 u8 index_data[18][0x10]; 10325 }; 10326 10327 struct mlx5_ifc_pcmr_reg_bits { 10328 u8 reserved_at_0[0x8]; 10329 u8 local_port[0x8]; 10330 u8 reserved_at_10[0x10]; 10331 10332 u8 entropy_force_cap[0x1]; 10333 u8 entropy_calc_cap[0x1]; 10334 u8 entropy_gre_calc_cap[0x1]; 10335 u8 reserved_at_23[0xf]; 10336 u8 rx_ts_over_crc_cap[0x1]; 10337 u8 reserved_at_33[0xb]; 10338 u8 fcs_cap[0x1]; 10339 u8 reserved_at_3f[0x1]; 10340 10341 u8 entropy_force[0x1]; 10342 u8 entropy_calc[0x1]; 10343 u8 entropy_gre_calc[0x1]; 10344 u8 reserved_at_43[0xf]; 10345 u8 rx_ts_over_crc[0x1]; 10346 u8 reserved_at_53[0xb]; 10347 u8 fcs_chk[0x1]; 10348 u8 reserved_at_5f[0x1]; 10349 }; 10350 10351 struct mlx5_ifc_lane_2_module_mapping_bits { 10352 u8 reserved_at_0[0x4]; 10353 u8 rx_lane[0x4]; 10354 u8 reserved_at_8[0x4]; 10355 u8 tx_lane[0x4]; 10356 u8 reserved_at_10[0x8]; 10357 u8 module[0x8]; 10358 }; 10359 10360 struct mlx5_ifc_bufferx_reg_bits { 10361 u8 reserved_at_0[0x6]; 10362 u8 lossy[0x1]; 10363 u8 epsb[0x1]; 10364 u8 reserved_at_8[0x8]; 10365 u8 size[0x10]; 10366 10367 u8 xoff_threshold[0x10]; 10368 u8 xon_threshold[0x10]; 10369 }; 10370 10371 struct mlx5_ifc_set_node_in_bits { 10372 u8 node_description[64][0x8]; 10373 }; 10374 10375 struct mlx5_ifc_register_power_settings_bits { 10376 u8 reserved_at_0[0x18]; 10377 u8 power_settings_level[0x8]; 10378 10379 u8 reserved_at_20[0x60]; 10380 }; 10381 10382 struct mlx5_ifc_register_host_endianness_bits { 10383 u8 he[0x1]; 10384 u8 reserved_at_1[0x1f]; 10385 10386 u8 reserved_at_20[0x60]; 10387 }; 10388 10389 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10390 u8 reserved_at_0[0x20]; 10391 10392 u8 mkey[0x20]; 10393 10394 u8 addressh_63_32[0x20]; 10395 10396 u8 addressl_31_0[0x20]; 10397 }; 10398 10399 struct mlx5_ifc_ud_adrs_vector_bits { 10400 u8 dc_key[0x40]; 10401 10402 u8 ext[0x1]; 10403 u8 reserved_at_41[0x7]; 10404 u8 destination_qp_dct[0x18]; 10405 10406 u8 static_rate[0x4]; 10407 u8 sl_eth_prio[0x4]; 10408 u8 fl[0x1]; 10409 u8 mlid[0x7]; 10410 u8 rlid_udp_sport[0x10]; 10411 10412 u8 reserved_at_80[0x20]; 10413 10414 u8 rmac_47_16[0x20]; 10415 10416 u8 rmac_15_0[0x10]; 10417 u8 tclass[0x8]; 10418 u8 hop_limit[0x8]; 10419 10420 u8 reserved_at_e0[0x1]; 10421 u8 grh[0x1]; 10422 u8 reserved_at_e2[0x2]; 10423 u8 src_addr_index[0x8]; 10424 u8 flow_label[0x14]; 10425 10426 u8 rgid_rip[16][0x8]; 10427 }; 10428 10429 struct mlx5_ifc_pages_req_event_bits { 10430 u8 reserved_at_0[0x10]; 10431 u8 function_id[0x10]; 10432 10433 u8 num_pages[0x20]; 10434 10435 u8 reserved_at_40[0xa0]; 10436 }; 10437 10438 struct mlx5_ifc_eqe_bits { 10439 u8 reserved_at_0[0x8]; 10440 u8 event_type[0x8]; 10441 u8 reserved_at_10[0x8]; 10442 u8 event_sub_type[0x8]; 10443 10444 u8 reserved_at_20[0xe0]; 10445 10446 union mlx5_ifc_event_auto_bits event_data; 10447 10448 u8 reserved_at_1e0[0x10]; 10449 u8 signature[0x8]; 10450 u8 reserved_at_1f8[0x7]; 10451 u8 owner[0x1]; 10452 }; 10453 10454 enum { 10455 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10456 }; 10457 10458 struct mlx5_ifc_cmd_queue_entry_bits { 10459 u8 type[0x8]; 10460 u8 reserved_at_8[0x18]; 10461 10462 u8 input_length[0x20]; 10463 10464 u8 input_mailbox_pointer_63_32[0x20]; 10465 10466 u8 input_mailbox_pointer_31_9[0x17]; 10467 u8 reserved_at_77[0x9]; 10468 10469 u8 command_input_inline_data[16][0x8]; 10470 10471 u8 command_output_inline_data[16][0x8]; 10472 10473 u8 output_mailbox_pointer_63_32[0x20]; 10474 10475 u8 output_mailbox_pointer_31_9[0x17]; 10476 u8 reserved_at_1b7[0x9]; 10477 10478 u8 output_length[0x20]; 10479 10480 u8 token[0x8]; 10481 u8 signature[0x8]; 10482 u8 reserved_at_1f0[0x8]; 10483 u8 status[0x7]; 10484 u8 ownership[0x1]; 10485 }; 10486 10487 struct mlx5_ifc_cmd_out_bits { 10488 u8 status[0x8]; 10489 u8 reserved_at_8[0x18]; 10490 10491 u8 syndrome[0x20]; 10492 10493 u8 command_output[0x20]; 10494 }; 10495 10496 struct mlx5_ifc_cmd_in_bits { 10497 u8 opcode[0x10]; 10498 u8 reserved_at_10[0x10]; 10499 10500 u8 reserved_at_20[0x10]; 10501 u8 op_mod[0x10]; 10502 10503 u8 command[][0x20]; 10504 }; 10505 10506 struct mlx5_ifc_cmd_if_box_bits { 10507 u8 mailbox_data[512][0x8]; 10508 10509 u8 reserved_at_1000[0x180]; 10510 10511 u8 next_pointer_63_32[0x20]; 10512 10513 u8 next_pointer_31_10[0x16]; 10514 u8 reserved_at_11b6[0xa]; 10515 10516 u8 block_number[0x20]; 10517 10518 u8 reserved_at_11e0[0x8]; 10519 u8 token[0x8]; 10520 u8 ctrl_signature[0x8]; 10521 u8 signature[0x8]; 10522 }; 10523 10524 struct mlx5_ifc_mtt_bits { 10525 u8 ptag_63_32[0x20]; 10526 10527 u8 ptag_31_8[0x18]; 10528 u8 reserved_at_38[0x6]; 10529 u8 wr_en[0x1]; 10530 u8 rd_en[0x1]; 10531 }; 10532 10533 struct mlx5_ifc_query_wol_rol_out_bits { 10534 u8 status[0x8]; 10535 u8 reserved_at_8[0x18]; 10536 10537 u8 syndrome[0x20]; 10538 10539 u8 reserved_at_40[0x10]; 10540 u8 rol_mode[0x8]; 10541 u8 wol_mode[0x8]; 10542 10543 u8 reserved_at_60[0x20]; 10544 }; 10545 10546 struct mlx5_ifc_query_wol_rol_in_bits { 10547 u8 opcode[0x10]; 10548 u8 reserved_at_10[0x10]; 10549 10550 u8 reserved_at_20[0x10]; 10551 u8 op_mod[0x10]; 10552 10553 u8 reserved_at_40[0x40]; 10554 }; 10555 10556 struct mlx5_ifc_set_wol_rol_out_bits { 10557 u8 status[0x8]; 10558 u8 reserved_at_8[0x18]; 10559 10560 u8 syndrome[0x20]; 10561 10562 u8 reserved_at_40[0x40]; 10563 }; 10564 10565 struct mlx5_ifc_set_wol_rol_in_bits { 10566 u8 opcode[0x10]; 10567 u8 reserved_at_10[0x10]; 10568 10569 u8 reserved_at_20[0x10]; 10570 u8 op_mod[0x10]; 10571 10572 u8 rol_mode_valid[0x1]; 10573 u8 wol_mode_valid[0x1]; 10574 u8 reserved_at_42[0xe]; 10575 u8 rol_mode[0x8]; 10576 u8 wol_mode[0x8]; 10577 10578 u8 reserved_at_60[0x20]; 10579 }; 10580 10581 enum { 10582 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10583 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10584 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10585 }; 10586 10587 enum { 10588 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10589 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10590 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10591 }; 10592 10593 enum { 10594 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10595 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10596 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10597 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10598 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10599 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10600 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10601 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10602 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10603 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10604 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10605 }; 10606 10607 struct mlx5_ifc_initial_seg_bits { 10608 u8 fw_rev_minor[0x10]; 10609 u8 fw_rev_major[0x10]; 10610 10611 u8 cmd_interface_rev[0x10]; 10612 u8 fw_rev_subminor[0x10]; 10613 10614 u8 reserved_at_40[0x40]; 10615 10616 u8 cmdq_phy_addr_63_32[0x20]; 10617 10618 u8 cmdq_phy_addr_31_12[0x14]; 10619 u8 reserved_at_b4[0x2]; 10620 u8 nic_interface[0x2]; 10621 u8 log_cmdq_size[0x4]; 10622 u8 log_cmdq_stride[0x4]; 10623 10624 u8 command_doorbell_vector[0x20]; 10625 10626 u8 reserved_at_e0[0xf00]; 10627 10628 u8 initializing[0x1]; 10629 u8 reserved_at_fe1[0x4]; 10630 u8 nic_interface_supported[0x3]; 10631 u8 embedded_cpu[0x1]; 10632 u8 reserved_at_fe9[0x17]; 10633 10634 struct mlx5_ifc_health_buffer_bits health_buffer; 10635 10636 u8 no_dram_nic_offset[0x20]; 10637 10638 u8 reserved_at_1220[0x6e40]; 10639 10640 u8 reserved_at_8060[0x1f]; 10641 u8 clear_int[0x1]; 10642 10643 u8 health_syndrome[0x8]; 10644 u8 health_counter[0x18]; 10645 10646 u8 reserved_at_80a0[0x17fc0]; 10647 }; 10648 10649 struct mlx5_ifc_mtpps_reg_bits { 10650 u8 reserved_at_0[0xc]; 10651 u8 cap_number_of_pps_pins[0x4]; 10652 u8 reserved_at_10[0x4]; 10653 u8 cap_max_num_of_pps_in_pins[0x4]; 10654 u8 reserved_at_18[0x4]; 10655 u8 cap_max_num_of_pps_out_pins[0x4]; 10656 10657 u8 reserved_at_20[0x13]; 10658 u8 cap_log_min_npps_period[0x5]; 10659 u8 reserved_at_38[0x3]; 10660 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10661 10662 u8 reserved_at_40[0x4]; 10663 u8 cap_pin_3_mode[0x4]; 10664 u8 reserved_at_48[0x4]; 10665 u8 cap_pin_2_mode[0x4]; 10666 u8 reserved_at_50[0x4]; 10667 u8 cap_pin_1_mode[0x4]; 10668 u8 reserved_at_58[0x4]; 10669 u8 cap_pin_0_mode[0x4]; 10670 10671 u8 reserved_at_60[0x4]; 10672 u8 cap_pin_7_mode[0x4]; 10673 u8 reserved_at_68[0x4]; 10674 u8 cap_pin_6_mode[0x4]; 10675 u8 reserved_at_70[0x4]; 10676 u8 cap_pin_5_mode[0x4]; 10677 u8 reserved_at_78[0x4]; 10678 u8 cap_pin_4_mode[0x4]; 10679 10680 u8 field_select[0x20]; 10681 u8 reserved_at_a0[0x20]; 10682 10683 u8 npps_period[0x40]; 10684 10685 u8 enable[0x1]; 10686 u8 reserved_at_101[0xb]; 10687 u8 pattern[0x4]; 10688 u8 reserved_at_110[0x4]; 10689 u8 pin_mode[0x4]; 10690 u8 pin[0x8]; 10691 10692 u8 reserved_at_120[0x2]; 10693 u8 out_pulse_duration_ns[0x1e]; 10694 10695 u8 time_stamp[0x40]; 10696 10697 u8 out_pulse_duration[0x10]; 10698 u8 out_periodic_adjustment[0x10]; 10699 u8 enhanced_out_periodic_adjustment[0x20]; 10700 10701 u8 reserved_at_1c0[0x20]; 10702 }; 10703 10704 struct mlx5_ifc_mtppse_reg_bits { 10705 u8 reserved_at_0[0x18]; 10706 u8 pin[0x8]; 10707 u8 event_arm[0x1]; 10708 u8 reserved_at_21[0x1b]; 10709 u8 event_generation_mode[0x4]; 10710 u8 reserved_at_40[0x40]; 10711 }; 10712 10713 struct mlx5_ifc_mcqs_reg_bits { 10714 u8 last_index_flag[0x1]; 10715 u8 reserved_at_1[0x7]; 10716 u8 fw_device[0x8]; 10717 u8 component_index[0x10]; 10718 10719 u8 reserved_at_20[0x10]; 10720 u8 identifier[0x10]; 10721 10722 u8 reserved_at_40[0x17]; 10723 u8 component_status[0x5]; 10724 u8 component_update_state[0x4]; 10725 10726 u8 last_update_state_changer_type[0x4]; 10727 u8 last_update_state_changer_host_id[0x4]; 10728 u8 reserved_at_68[0x18]; 10729 }; 10730 10731 struct mlx5_ifc_mcqi_cap_bits { 10732 u8 supported_info_bitmask[0x20]; 10733 10734 u8 component_size[0x20]; 10735 10736 u8 max_component_size[0x20]; 10737 10738 u8 log_mcda_word_size[0x4]; 10739 u8 reserved_at_64[0xc]; 10740 u8 mcda_max_write_size[0x10]; 10741 10742 u8 rd_en[0x1]; 10743 u8 reserved_at_81[0x1]; 10744 u8 match_chip_id[0x1]; 10745 u8 match_psid[0x1]; 10746 u8 check_user_timestamp[0x1]; 10747 u8 match_base_guid_mac[0x1]; 10748 u8 reserved_at_86[0x1a]; 10749 }; 10750 10751 struct mlx5_ifc_mcqi_version_bits { 10752 u8 reserved_at_0[0x2]; 10753 u8 build_time_valid[0x1]; 10754 u8 user_defined_time_valid[0x1]; 10755 u8 reserved_at_4[0x14]; 10756 u8 version_string_length[0x8]; 10757 10758 u8 version[0x20]; 10759 10760 u8 build_time[0x40]; 10761 10762 u8 user_defined_time[0x40]; 10763 10764 u8 build_tool_version[0x20]; 10765 10766 u8 reserved_at_e0[0x20]; 10767 10768 u8 version_string[92][0x8]; 10769 }; 10770 10771 struct mlx5_ifc_mcqi_activation_method_bits { 10772 u8 pending_server_ac_power_cycle[0x1]; 10773 u8 pending_server_dc_power_cycle[0x1]; 10774 u8 pending_server_reboot[0x1]; 10775 u8 pending_fw_reset[0x1]; 10776 u8 auto_activate[0x1]; 10777 u8 all_hosts_sync[0x1]; 10778 u8 device_hw_reset[0x1]; 10779 u8 reserved_at_7[0x19]; 10780 }; 10781 10782 union mlx5_ifc_mcqi_reg_data_bits { 10783 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10784 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10785 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10786 }; 10787 10788 struct mlx5_ifc_mcqi_reg_bits { 10789 u8 read_pending_component[0x1]; 10790 u8 reserved_at_1[0xf]; 10791 u8 component_index[0x10]; 10792 10793 u8 reserved_at_20[0x20]; 10794 10795 u8 reserved_at_40[0x1b]; 10796 u8 info_type[0x5]; 10797 10798 u8 info_size[0x20]; 10799 10800 u8 offset[0x20]; 10801 10802 u8 reserved_at_a0[0x10]; 10803 u8 data_size[0x10]; 10804 10805 union mlx5_ifc_mcqi_reg_data_bits data[]; 10806 }; 10807 10808 struct mlx5_ifc_mcc_reg_bits { 10809 u8 reserved_at_0[0x4]; 10810 u8 time_elapsed_since_last_cmd[0xc]; 10811 u8 reserved_at_10[0x8]; 10812 u8 instruction[0x8]; 10813 10814 u8 reserved_at_20[0x10]; 10815 u8 component_index[0x10]; 10816 10817 u8 reserved_at_40[0x8]; 10818 u8 update_handle[0x18]; 10819 10820 u8 handle_owner_type[0x4]; 10821 u8 handle_owner_host_id[0x4]; 10822 u8 reserved_at_68[0x1]; 10823 u8 control_progress[0x7]; 10824 u8 error_code[0x8]; 10825 u8 reserved_at_78[0x4]; 10826 u8 control_state[0x4]; 10827 10828 u8 component_size[0x20]; 10829 10830 u8 reserved_at_a0[0x60]; 10831 }; 10832 10833 struct mlx5_ifc_mcda_reg_bits { 10834 u8 reserved_at_0[0x8]; 10835 u8 update_handle[0x18]; 10836 10837 u8 offset[0x20]; 10838 10839 u8 reserved_at_40[0x10]; 10840 u8 size[0x10]; 10841 10842 u8 reserved_at_60[0x20]; 10843 10844 u8 data[][0x20]; 10845 }; 10846 10847 enum { 10848 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10849 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10850 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10851 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10852 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10853 }; 10854 10855 enum { 10856 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10857 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10858 }; 10859 10860 enum { 10861 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10862 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10863 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10864 }; 10865 10866 struct mlx5_ifc_mfrl_reg_bits { 10867 u8 reserved_at_0[0x20]; 10868 10869 u8 reserved_at_20[0x2]; 10870 u8 pci_sync_for_fw_update_start[0x1]; 10871 u8 pci_sync_for_fw_update_resp[0x2]; 10872 u8 rst_type_sel[0x3]; 10873 u8 reserved_at_28[0x4]; 10874 u8 reset_state[0x4]; 10875 u8 reset_type[0x8]; 10876 u8 reset_level[0x8]; 10877 }; 10878 10879 struct mlx5_ifc_mirc_reg_bits { 10880 u8 reserved_at_0[0x18]; 10881 u8 status_code[0x8]; 10882 10883 u8 reserved_at_20[0x20]; 10884 }; 10885 10886 struct mlx5_ifc_pddr_monitor_opcode_bits { 10887 u8 reserved_at_0[0x10]; 10888 u8 monitor_opcode[0x10]; 10889 }; 10890 10891 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10892 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10893 u8 reserved_at_0[0x20]; 10894 }; 10895 10896 enum { 10897 /* Monitor opcodes */ 10898 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10899 }; 10900 10901 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10902 u8 reserved_at_0[0x10]; 10903 u8 group_opcode[0x10]; 10904 10905 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10906 10907 u8 reserved_at_40[0x20]; 10908 10909 u8 status_message[59][0x20]; 10910 }; 10911 10912 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10913 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10914 u8 reserved_at_0[0x7c0]; 10915 }; 10916 10917 enum { 10918 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10919 }; 10920 10921 struct mlx5_ifc_pddr_reg_bits { 10922 u8 reserved_at_0[0x8]; 10923 u8 local_port[0x8]; 10924 u8 pnat[0x2]; 10925 u8 reserved_at_12[0xe]; 10926 10927 u8 reserved_at_20[0x18]; 10928 u8 page_select[0x8]; 10929 10930 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10931 }; 10932 10933 struct mlx5_ifc_mrtc_reg_bits { 10934 u8 time_synced[0x1]; 10935 u8 reserved_at_1[0x1f]; 10936 10937 u8 reserved_at_20[0x20]; 10938 10939 u8 time_h[0x20]; 10940 10941 u8 time_l[0x20]; 10942 }; 10943 10944 struct mlx5_ifc_mtmp_reg_bits { 10945 u8 reserved_at_0[0x14]; 10946 u8 sensor_index[0xc]; 10947 10948 u8 reserved_at_20[0x10]; 10949 u8 temperature[0x10]; 10950 10951 u8 mte[0x1]; 10952 u8 mtr[0x1]; 10953 u8 reserved_at_42[0xe]; 10954 u8 max_temperature[0x10]; 10955 10956 u8 tee[0x2]; 10957 u8 reserved_at_62[0xe]; 10958 u8 temp_threshold_hi[0x10]; 10959 10960 u8 reserved_at_80[0x10]; 10961 u8 temp_threshold_lo[0x10]; 10962 10963 u8 reserved_at_a0[0x20]; 10964 10965 u8 sensor_name_hi[0x20]; 10966 u8 sensor_name_lo[0x20]; 10967 }; 10968 10969 union mlx5_ifc_ports_control_registers_document_bits { 10970 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10971 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10972 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10973 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10974 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10975 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10976 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10977 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10978 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10979 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10980 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10981 struct mlx5_ifc_paos_reg_bits paos_reg; 10982 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10983 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10984 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10985 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10986 struct mlx5_ifc_peir_reg_bits peir_reg; 10987 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10988 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10989 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10990 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10991 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10992 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10993 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10994 struct mlx5_ifc_plib_reg_bits plib_reg; 10995 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10996 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10997 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10998 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10999 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11000 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11001 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11002 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11003 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11004 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11005 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11006 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11007 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11008 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11009 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11010 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11011 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11012 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11013 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11014 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11015 struct mlx5_ifc_pude_reg_bits pude_reg; 11016 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11017 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11018 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11019 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11020 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11021 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11022 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11023 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11024 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11025 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11026 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11027 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11028 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11029 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11030 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11031 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11032 u8 reserved_at_0[0x60e0]; 11033 }; 11034 11035 union mlx5_ifc_debug_enhancements_document_bits { 11036 struct mlx5_ifc_health_buffer_bits health_buffer; 11037 u8 reserved_at_0[0x200]; 11038 }; 11039 11040 union mlx5_ifc_uplink_pci_interface_document_bits { 11041 struct mlx5_ifc_initial_seg_bits initial_seg; 11042 u8 reserved_at_0[0x20060]; 11043 }; 11044 11045 struct mlx5_ifc_set_flow_table_root_out_bits { 11046 u8 status[0x8]; 11047 u8 reserved_at_8[0x18]; 11048 11049 u8 syndrome[0x20]; 11050 11051 u8 reserved_at_40[0x40]; 11052 }; 11053 11054 struct mlx5_ifc_set_flow_table_root_in_bits { 11055 u8 opcode[0x10]; 11056 u8 reserved_at_10[0x10]; 11057 11058 u8 reserved_at_20[0x10]; 11059 u8 op_mod[0x10]; 11060 11061 u8 other_vport[0x1]; 11062 u8 reserved_at_41[0xf]; 11063 u8 vport_number[0x10]; 11064 11065 u8 reserved_at_60[0x20]; 11066 11067 u8 table_type[0x8]; 11068 u8 reserved_at_88[0x7]; 11069 u8 table_of_other_vport[0x1]; 11070 u8 table_vport_number[0x10]; 11071 11072 u8 reserved_at_a0[0x8]; 11073 u8 table_id[0x18]; 11074 11075 u8 reserved_at_c0[0x8]; 11076 u8 underlay_qpn[0x18]; 11077 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11078 u8 reserved_at_e1[0xf]; 11079 u8 table_eswitch_owner_vhca_id[0x10]; 11080 u8 reserved_at_100[0x100]; 11081 }; 11082 11083 enum { 11084 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11085 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11086 }; 11087 11088 struct mlx5_ifc_modify_flow_table_out_bits { 11089 u8 status[0x8]; 11090 u8 reserved_at_8[0x18]; 11091 11092 u8 syndrome[0x20]; 11093 11094 u8 reserved_at_40[0x40]; 11095 }; 11096 11097 struct mlx5_ifc_modify_flow_table_in_bits { 11098 u8 opcode[0x10]; 11099 u8 reserved_at_10[0x10]; 11100 11101 u8 reserved_at_20[0x10]; 11102 u8 op_mod[0x10]; 11103 11104 u8 other_vport[0x1]; 11105 u8 reserved_at_41[0xf]; 11106 u8 vport_number[0x10]; 11107 11108 u8 reserved_at_60[0x10]; 11109 u8 modify_field_select[0x10]; 11110 11111 u8 table_type[0x8]; 11112 u8 reserved_at_88[0x18]; 11113 11114 u8 reserved_at_a0[0x8]; 11115 u8 table_id[0x18]; 11116 11117 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11118 }; 11119 11120 struct mlx5_ifc_ets_tcn_config_reg_bits { 11121 u8 g[0x1]; 11122 u8 b[0x1]; 11123 u8 r[0x1]; 11124 u8 reserved_at_3[0x9]; 11125 u8 group[0x4]; 11126 u8 reserved_at_10[0x9]; 11127 u8 bw_allocation[0x7]; 11128 11129 u8 reserved_at_20[0xc]; 11130 u8 max_bw_units[0x4]; 11131 u8 reserved_at_30[0x8]; 11132 u8 max_bw_value[0x8]; 11133 }; 11134 11135 struct mlx5_ifc_ets_global_config_reg_bits { 11136 u8 reserved_at_0[0x2]; 11137 u8 r[0x1]; 11138 u8 reserved_at_3[0x1d]; 11139 11140 u8 reserved_at_20[0xc]; 11141 u8 max_bw_units[0x4]; 11142 u8 reserved_at_30[0x8]; 11143 u8 max_bw_value[0x8]; 11144 }; 11145 11146 struct mlx5_ifc_qetc_reg_bits { 11147 u8 reserved_at_0[0x8]; 11148 u8 port_number[0x8]; 11149 u8 reserved_at_10[0x30]; 11150 11151 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11152 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11153 }; 11154 11155 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11156 u8 e[0x1]; 11157 u8 reserved_at_01[0x0b]; 11158 u8 prio[0x04]; 11159 }; 11160 11161 struct mlx5_ifc_qpdpm_reg_bits { 11162 u8 reserved_at_0[0x8]; 11163 u8 local_port[0x8]; 11164 u8 reserved_at_10[0x10]; 11165 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11166 }; 11167 11168 struct mlx5_ifc_qpts_reg_bits { 11169 u8 reserved_at_0[0x8]; 11170 u8 local_port[0x8]; 11171 u8 reserved_at_10[0x2d]; 11172 u8 trust_state[0x3]; 11173 }; 11174 11175 struct mlx5_ifc_pptb_reg_bits { 11176 u8 reserved_at_0[0x2]; 11177 u8 mm[0x2]; 11178 u8 reserved_at_4[0x4]; 11179 u8 local_port[0x8]; 11180 u8 reserved_at_10[0x6]; 11181 u8 cm[0x1]; 11182 u8 um[0x1]; 11183 u8 pm[0x8]; 11184 11185 u8 prio_x_buff[0x20]; 11186 11187 u8 pm_msb[0x8]; 11188 u8 reserved_at_48[0x10]; 11189 u8 ctrl_buff[0x4]; 11190 u8 untagged_buff[0x4]; 11191 }; 11192 11193 struct mlx5_ifc_sbcam_reg_bits { 11194 u8 reserved_at_0[0x8]; 11195 u8 feature_group[0x8]; 11196 u8 reserved_at_10[0x8]; 11197 u8 access_reg_group[0x8]; 11198 11199 u8 reserved_at_20[0x20]; 11200 11201 u8 sb_access_reg_cap_mask[4][0x20]; 11202 11203 u8 reserved_at_c0[0x80]; 11204 11205 u8 sb_feature_cap_mask[4][0x20]; 11206 11207 u8 reserved_at_1c0[0x40]; 11208 11209 u8 cap_total_buffer_size[0x20]; 11210 11211 u8 cap_cell_size[0x10]; 11212 u8 cap_max_pg_buffers[0x8]; 11213 u8 cap_num_pool_supported[0x8]; 11214 11215 u8 reserved_at_240[0x8]; 11216 u8 cap_sbsr_stat_size[0x8]; 11217 u8 cap_max_tclass_data[0x8]; 11218 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11219 }; 11220 11221 struct mlx5_ifc_pbmc_reg_bits { 11222 u8 reserved_at_0[0x8]; 11223 u8 local_port[0x8]; 11224 u8 reserved_at_10[0x10]; 11225 11226 u8 xoff_timer_value[0x10]; 11227 u8 xoff_refresh[0x10]; 11228 11229 u8 reserved_at_40[0x9]; 11230 u8 fullness_threshold[0x7]; 11231 u8 port_buffer_size[0x10]; 11232 11233 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11234 11235 u8 reserved_at_2e0[0x80]; 11236 }; 11237 11238 struct mlx5_ifc_sbpr_reg_bits { 11239 u8 desc[0x1]; 11240 u8 snap[0x1]; 11241 u8 reserved_at_2[0x4]; 11242 u8 dir[0x2]; 11243 u8 reserved_at_8[0x14]; 11244 u8 pool[0x4]; 11245 11246 u8 infi_size[0x1]; 11247 u8 reserved_at_21[0x7]; 11248 u8 size[0x18]; 11249 11250 u8 reserved_at_40[0x1c]; 11251 u8 mode[0x4]; 11252 11253 u8 reserved_at_60[0x8]; 11254 u8 buff_occupancy[0x18]; 11255 11256 u8 clr[0x1]; 11257 u8 reserved_at_81[0x7]; 11258 u8 max_buff_occupancy[0x18]; 11259 11260 u8 reserved_at_a0[0x8]; 11261 u8 ext_buff_occupancy[0x18]; 11262 }; 11263 11264 struct mlx5_ifc_sbcm_reg_bits { 11265 u8 desc[0x1]; 11266 u8 snap[0x1]; 11267 u8 reserved_at_2[0x6]; 11268 u8 local_port[0x8]; 11269 u8 pnat[0x2]; 11270 u8 pg_buff[0x6]; 11271 u8 reserved_at_18[0x6]; 11272 u8 dir[0x2]; 11273 11274 u8 reserved_at_20[0x1f]; 11275 u8 exc[0x1]; 11276 11277 u8 reserved_at_40[0x40]; 11278 11279 u8 reserved_at_80[0x8]; 11280 u8 buff_occupancy[0x18]; 11281 11282 u8 clr[0x1]; 11283 u8 reserved_at_a1[0x7]; 11284 u8 max_buff_occupancy[0x18]; 11285 11286 u8 reserved_at_c0[0x8]; 11287 u8 min_buff[0x18]; 11288 11289 u8 infi_max[0x1]; 11290 u8 reserved_at_e1[0x7]; 11291 u8 max_buff[0x18]; 11292 11293 u8 reserved_at_100[0x20]; 11294 11295 u8 reserved_at_120[0x1c]; 11296 u8 pool[0x4]; 11297 }; 11298 11299 struct mlx5_ifc_qtct_reg_bits { 11300 u8 reserved_at_0[0x8]; 11301 u8 port_number[0x8]; 11302 u8 reserved_at_10[0xd]; 11303 u8 prio[0x3]; 11304 11305 u8 reserved_at_20[0x1d]; 11306 u8 tclass[0x3]; 11307 }; 11308 11309 struct mlx5_ifc_mcia_reg_bits { 11310 u8 l[0x1]; 11311 u8 reserved_at_1[0x7]; 11312 u8 module[0x8]; 11313 u8 reserved_at_10[0x8]; 11314 u8 status[0x8]; 11315 11316 u8 i2c_device_address[0x8]; 11317 u8 page_number[0x8]; 11318 u8 device_address[0x10]; 11319 11320 u8 reserved_at_40[0x10]; 11321 u8 size[0x10]; 11322 11323 u8 reserved_at_60[0x20]; 11324 11325 u8 dword_0[0x20]; 11326 u8 dword_1[0x20]; 11327 u8 dword_2[0x20]; 11328 u8 dword_3[0x20]; 11329 u8 dword_4[0x20]; 11330 u8 dword_5[0x20]; 11331 u8 dword_6[0x20]; 11332 u8 dword_7[0x20]; 11333 u8 dword_8[0x20]; 11334 u8 dword_9[0x20]; 11335 u8 dword_10[0x20]; 11336 u8 dword_11[0x20]; 11337 }; 11338 11339 struct mlx5_ifc_dcbx_param_bits { 11340 u8 dcbx_cee_cap[0x1]; 11341 u8 dcbx_ieee_cap[0x1]; 11342 u8 dcbx_standby_cap[0x1]; 11343 u8 reserved_at_3[0x5]; 11344 u8 port_number[0x8]; 11345 u8 reserved_at_10[0xa]; 11346 u8 max_application_table_size[6]; 11347 u8 reserved_at_20[0x15]; 11348 u8 version_oper[0x3]; 11349 u8 reserved_at_38[5]; 11350 u8 version_admin[0x3]; 11351 u8 willing_admin[0x1]; 11352 u8 reserved_at_41[0x3]; 11353 u8 pfc_cap_oper[0x4]; 11354 u8 reserved_at_48[0x4]; 11355 u8 pfc_cap_admin[0x4]; 11356 u8 reserved_at_50[0x4]; 11357 u8 num_of_tc_oper[0x4]; 11358 u8 reserved_at_58[0x4]; 11359 u8 num_of_tc_admin[0x4]; 11360 u8 remote_willing[0x1]; 11361 u8 reserved_at_61[3]; 11362 u8 remote_pfc_cap[4]; 11363 u8 reserved_at_68[0x14]; 11364 u8 remote_num_of_tc[0x4]; 11365 u8 reserved_at_80[0x18]; 11366 u8 error[0x8]; 11367 u8 reserved_at_a0[0x160]; 11368 }; 11369 11370 enum { 11371 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11372 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11373 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11374 }; 11375 11376 struct mlx5_ifc_lagc_bits { 11377 u8 fdb_selection_mode[0x1]; 11378 u8 reserved_at_1[0x14]; 11379 u8 port_select_mode[0x3]; 11380 u8 reserved_at_18[0x5]; 11381 u8 lag_state[0x3]; 11382 11383 u8 reserved_at_20[0xc]; 11384 u8 active_port[0x4]; 11385 u8 reserved_at_30[0x4]; 11386 u8 tx_remap_affinity_2[0x4]; 11387 u8 reserved_at_38[0x4]; 11388 u8 tx_remap_affinity_1[0x4]; 11389 }; 11390 11391 struct mlx5_ifc_create_lag_out_bits { 11392 u8 status[0x8]; 11393 u8 reserved_at_8[0x18]; 11394 11395 u8 syndrome[0x20]; 11396 11397 u8 reserved_at_40[0x40]; 11398 }; 11399 11400 struct mlx5_ifc_create_lag_in_bits { 11401 u8 opcode[0x10]; 11402 u8 reserved_at_10[0x10]; 11403 11404 u8 reserved_at_20[0x10]; 11405 u8 op_mod[0x10]; 11406 11407 struct mlx5_ifc_lagc_bits ctx; 11408 }; 11409 11410 struct mlx5_ifc_modify_lag_out_bits { 11411 u8 status[0x8]; 11412 u8 reserved_at_8[0x18]; 11413 11414 u8 syndrome[0x20]; 11415 11416 u8 reserved_at_40[0x40]; 11417 }; 11418 11419 struct mlx5_ifc_modify_lag_in_bits { 11420 u8 opcode[0x10]; 11421 u8 reserved_at_10[0x10]; 11422 11423 u8 reserved_at_20[0x10]; 11424 u8 op_mod[0x10]; 11425 11426 u8 reserved_at_40[0x20]; 11427 u8 field_select[0x20]; 11428 11429 struct mlx5_ifc_lagc_bits ctx; 11430 }; 11431 11432 struct mlx5_ifc_query_lag_out_bits { 11433 u8 status[0x8]; 11434 u8 reserved_at_8[0x18]; 11435 11436 u8 syndrome[0x20]; 11437 11438 struct mlx5_ifc_lagc_bits ctx; 11439 }; 11440 11441 struct mlx5_ifc_query_lag_in_bits { 11442 u8 opcode[0x10]; 11443 u8 reserved_at_10[0x10]; 11444 11445 u8 reserved_at_20[0x10]; 11446 u8 op_mod[0x10]; 11447 11448 u8 reserved_at_40[0x40]; 11449 }; 11450 11451 struct mlx5_ifc_destroy_lag_out_bits { 11452 u8 status[0x8]; 11453 u8 reserved_at_8[0x18]; 11454 11455 u8 syndrome[0x20]; 11456 11457 u8 reserved_at_40[0x40]; 11458 }; 11459 11460 struct mlx5_ifc_destroy_lag_in_bits { 11461 u8 opcode[0x10]; 11462 u8 reserved_at_10[0x10]; 11463 11464 u8 reserved_at_20[0x10]; 11465 u8 op_mod[0x10]; 11466 11467 u8 reserved_at_40[0x40]; 11468 }; 11469 11470 struct mlx5_ifc_create_vport_lag_out_bits { 11471 u8 status[0x8]; 11472 u8 reserved_at_8[0x18]; 11473 11474 u8 syndrome[0x20]; 11475 11476 u8 reserved_at_40[0x40]; 11477 }; 11478 11479 struct mlx5_ifc_create_vport_lag_in_bits { 11480 u8 opcode[0x10]; 11481 u8 reserved_at_10[0x10]; 11482 11483 u8 reserved_at_20[0x10]; 11484 u8 op_mod[0x10]; 11485 11486 u8 reserved_at_40[0x40]; 11487 }; 11488 11489 struct mlx5_ifc_destroy_vport_lag_out_bits { 11490 u8 status[0x8]; 11491 u8 reserved_at_8[0x18]; 11492 11493 u8 syndrome[0x20]; 11494 11495 u8 reserved_at_40[0x40]; 11496 }; 11497 11498 struct mlx5_ifc_destroy_vport_lag_in_bits { 11499 u8 opcode[0x10]; 11500 u8 reserved_at_10[0x10]; 11501 11502 u8 reserved_at_20[0x10]; 11503 u8 op_mod[0x10]; 11504 11505 u8 reserved_at_40[0x40]; 11506 }; 11507 11508 enum { 11509 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11510 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11511 }; 11512 11513 struct mlx5_ifc_modify_memic_in_bits { 11514 u8 opcode[0x10]; 11515 u8 uid[0x10]; 11516 11517 u8 reserved_at_20[0x10]; 11518 u8 op_mod[0x10]; 11519 11520 u8 reserved_at_40[0x20]; 11521 11522 u8 reserved_at_60[0x18]; 11523 u8 memic_operation_type[0x8]; 11524 11525 u8 memic_start_addr[0x40]; 11526 11527 u8 reserved_at_c0[0x140]; 11528 }; 11529 11530 struct mlx5_ifc_modify_memic_out_bits { 11531 u8 status[0x8]; 11532 u8 reserved_at_8[0x18]; 11533 11534 u8 syndrome[0x20]; 11535 11536 u8 reserved_at_40[0x40]; 11537 11538 u8 memic_operation_addr[0x40]; 11539 11540 u8 reserved_at_c0[0x140]; 11541 }; 11542 11543 struct mlx5_ifc_alloc_memic_in_bits { 11544 u8 opcode[0x10]; 11545 u8 reserved_at_10[0x10]; 11546 11547 u8 reserved_at_20[0x10]; 11548 u8 op_mod[0x10]; 11549 11550 u8 reserved_at_30[0x20]; 11551 11552 u8 reserved_at_40[0x18]; 11553 u8 log_memic_addr_alignment[0x8]; 11554 11555 u8 range_start_addr[0x40]; 11556 11557 u8 range_size[0x20]; 11558 11559 u8 memic_size[0x20]; 11560 }; 11561 11562 struct mlx5_ifc_alloc_memic_out_bits { 11563 u8 status[0x8]; 11564 u8 reserved_at_8[0x18]; 11565 11566 u8 syndrome[0x20]; 11567 11568 u8 memic_start_addr[0x40]; 11569 }; 11570 11571 struct mlx5_ifc_dealloc_memic_in_bits { 11572 u8 opcode[0x10]; 11573 u8 reserved_at_10[0x10]; 11574 11575 u8 reserved_at_20[0x10]; 11576 u8 op_mod[0x10]; 11577 11578 u8 reserved_at_40[0x40]; 11579 11580 u8 memic_start_addr[0x40]; 11581 11582 u8 memic_size[0x20]; 11583 11584 u8 reserved_at_e0[0x20]; 11585 }; 11586 11587 struct mlx5_ifc_dealloc_memic_out_bits { 11588 u8 status[0x8]; 11589 u8 reserved_at_8[0x18]; 11590 11591 u8 syndrome[0x20]; 11592 11593 u8 reserved_at_40[0x40]; 11594 }; 11595 11596 struct mlx5_ifc_umem_bits { 11597 u8 reserved_at_0[0x80]; 11598 11599 u8 ats[0x1]; 11600 u8 reserved_at_81[0x1a]; 11601 u8 log_page_size[0x5]; 11602 11603 u8 page_offset[0x20]; 11604 11605 u8 num_of_mtt[0x40]; 11606 11607 struct mlx5_ifc_mtt_bits mtt[]; 11608 }; 11609 11610 struct mlx5_ifc_uctx_bits { 11611 u8 cap[0x20]; 11612 11613 u8 reserved_at_20[0x160]; 11614 }; 11615 11616 struct mlx5_ifc_sw_icm_bits { 11617 u8 modify_field_select[0x40]; 11618 11619 u8 reserved_at_40[0x18]; 11620 u8 log_sw_icm_size[0x8]; 11621 11622 u8 reserved_at_60[0x20]; 11623 11624 u8 sw_icm_start_addr[0x40]; 11625 11626 u8 reserved_at_c0[0x140]; 11627 }; 11628 11629 struct mlx5_ifc_geneve_tlv_option_bits { 11630 u8 modify_field_select[0x40]; 11631 11632 u8 reserved_at_40[0x18]; 11633 u8 geneve_option_fte_index[0x8]; 11634 11635 u8 option_class[0x10]; 11636 u8 option_type[0x8]; 11637 u8 reserved_at_78[0x3]; 11638 u8 option_data_length[0x5]; 11639 11640 u8 reserved_at_80[0x180]; 11641 }; 11642 11643 struct mlx5_ifc_create_umem_in_bits { 11644 u8 opcode[0x10]; 11645 u8 uid[0x10]; 11646 11647 u8 reserved_at_20[0x10]; 11648 u8 op_mod[0x10]; 11649 11650 u8 reserved_at_40[0x40]; 11651 11652 struct mlx5_ifc_umem_bits umem; 11653 }; 11654 11655 struct mlx5_ifc_create_umem_out_bits { 11656 u8 status[0x8]; 11657 u8 reserved_at_8[0x18]; 11658 11659 u8 syndrome[0x20]; 11660 11661 u8 reserved_at_40[0x8]; 11662 u8 umem_id[0x18]; 11663 11664 u8 reserved_at_60[0x20]; 11665 }; 11666 11667 struct mlx5_ifc_destroy_umem_in_bits { 11668 u8 opcode[0x10]; 11669 u8 uid[0x10]; 11670 11671 u8 reserved_at_20[0x10]; 11672 u8 op_mod[0x10]; 11673 11674 u8 reserved_at_40[0x8]; 11675 u8 umem_id[0x18]; 11676 11677 u8 reserved_at_60[0x20]; 11678 }; 11679 11680 struct mlx5_ifc_destroy_umem_out_bits { 11681 u8 status[0x8]; 11682 u8 reserved_at_8[0x18]; 11683 11684 u8 syndrome[0x20]; 11685 11686 u8 reserved_at_40[0x40]; 11687 }; 11688 11689 struct mlx5_ifc_create_uctx_in_bits { 11690 u8 opcode[0x10]; 11691 u8 reserved_at_10[0x10]; 11692 11693 u8 reserved_at_20[0x10]; 11694 u8 op_mod[0x10]; 11695 11696 u8 reserved_at_40[0x40]; 11697 11698 struct mlx5_ifc_uctx_bits uctx; 11699 }; 11700 11701 struct mlx5_ifc_create_uctx_out_bits { 11702 u8 status[0x8]; 11703 u8 reserved_at_8[0x18]; 11704 11705 u8 syndrome[0x20]; 11706 11707 u8 reserved_at_40[0x10]; 11708 u8 uid[0x10]; 11709 11710 u8 reserved_at_60[0x20]; 11711 }; 11712 11713 struct mlx5_ifc_destroy_uctx_in_bits { 11714 u8 opcode[0x10]; 11715 u8 reserved_at_10[0x10]; 11716 11717 u8 reserved_at_20[0x10]; 11718 u8 op_mod[0x10]; 11719 11720 u8 reserved_at_40[0x10]; 11721 u8 uid[0x10]; 11722 11723 u8 reserved_at_60[0x20]; 11724 }; 11725 11726 struct mlx5_ifc_destroy_uctx_out_bits { 11727 u8 status[0x8]; 11728 u8 reserved_at_8[0x18]; 11729 11730 u8 syndrome[0x20]; 11731 11732 u8 reserved_at_40[0x40]; 11733 }; 11734 11735 struct mlx5_ifc_create_sw_icm_in_bits { 11736 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11737 struct mlx5_ifc_sw_icm_bits sw_icm; 11738 }; 11739 11740 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11741 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11742 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11743 }; 11744 11745 struct mlx5_ifc_mtrc_string_db_param_bits { 11746 u8 string_db_base_address[0x20]; 11747 11748 u8 reserved_at_20[0x8]; 11749 u8 string_db_size[0x18]; 11750 }; 11751 11752 struct mlx5_ifc_mtrc_cap_bits { 11753 u8 trace_owner[0x1]; 11754 u8 trace_to_memory[0x1]; 11755 u8 reserved_at_2[0x4]; 11756 u8 trc_ver[0x2]; 11757 u8 reserved_at_8[0x14]; 11758 u8 num_string_db[0x4]; 11759 11760 u8 first_string_trace[0x8]; 11761 u8 num_string_trace[0x8]; 11762 u8 reserved_at_30[0x28]; 11763 11764 u8 log_max_trace_buffer_size[0x8]; 11765 11766 u8 reserved_at_60[0x20]; 11767 11768 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11769 11770 u8 reserved_at_280[0x180]; 11771 }; 11772 11773 struct mlx5_ifc_mtrc_conf_bits { 11774 u8 reserved_at_0[0x1c]; 11775 u8 trace_mode[0x4]; 11776 u8 reserved_at_20[0x18]; 11777 u8 log_trace_buffer_size[0x8]; 11778 u8 trace_mkey[0x20]; 11779 u8 reserved_at_60[0x3a0]; 11780 }; 11781 11782 struct mlx5_ifc_mtrc_stdb_bits { 11783 u8 string_db_index[0x4]; 11784 u8 reserved_at_4[0x4]; 11785 u8 read_size[0x18]; 11786 u8 start_offset[0x20]; 11787 u8 string_db_data[]; 11788 }; 11789 11790 struct mlx5_ifc_mtrc_ctrl_bits { 11791 u8 trace_status[0x2]; 11792 u8 reserved_at_2[0x2]; 11793 u8 arm_event[0x1]; 11794 u8 reserved_at_5[0xb]; 11795 u8 modify_field_select[0x10]; 11796 u8 reserved_at_20[0x2b]; 11797 u8 current_timestamp52_32[0x15]; 11798 u8 current_timestamp31_0[0x20]; 11799 u8 reserved_at_80[0x180]; 11800 }; 11801 11802 struct mlx5_ifc_host_params_context_bits { 11803 u8 host_number[0x8]; 11804 u8 reserved_at_8[0x7]; 11805 u8 host_pf_disabled[0x1]; 11806 u8 host_num_of_vfs[0x10]; 11807 11808 u8 host_total_vfs[0x10]; 11809 u8 host_pci_bus[0x10]; 11810 11811 u8 reserved_at_40[0x10]; 11812 u8 host_pci_device[0x10]; 11813 11814 u8 reserved_at_60[0x10]; 11815 u8 host_pci_function[0x10]; 11816 11817 u8 reserved_at_80[0x180]; 11818 }; 11819 11820 struct mlx5_ifc_query_esw_functions_in_bits { 11821 u8 opcode[0x10]; 11822 u8 reserved_at_10[0x10]; 11823 11824 u8 reserved_at_20[0x10]; 11825 u8 op_mod[0x10]; 11826 11827 u8 reserved_at_40[0x40]; 11828 }; 11829 11830 struct mlx5_ifc_query_esw_functions_out_bits { 11831 u8 status[0x8]; 11832 u8 reserved_at_8[0x18]; 11833 11834 u8 syndrome[0x20]; 11835 11836 u8 reserved_at_40[0x40]; 11837 11838 struct mlx5_ifc_host_params_context_bits host_params_context; 11839 11840 u8 reserved_at_280[0x180]; 11841 u8 host_sf_enable[][0x40]; 11842 }; 11843 11844 struct mlx5_ifc_sf_partition_bits { 11845 u8 reserved_at_0[0x10]; 11846 u8 log_num_sf[0x8]; 11847 u8 log_sf_bar_size[0x8]; 11848 }; 11849 11850 struct mlx5_ifc_query_sf_partitions_out_bits { 11851 u8 status[0x8]; 11852 u8 reserved_at_8[0x18]; 11853 11854 u8 syndrome[0x20]; 11855 11856 u8 reserved_at_40[0x18]; 11857 u8 num_sf_partitions[0x8]; 11858 11859 u8 reserved_at_60[0x20]; 11860 11861 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11862 }; 11863 11864 struct mlx5_ifc_query_sf_partitions_in_bits { 11865 u8 opcode[0x10]; 11866 u8 reserved_at_10[0x10]; 11867 11868 u8 reserved_at_20[0x10]; 11869 u8 op_mod[0x10]; 11870 11871 u8 reserved_at_40[0x40]; 11872 }; 11873 11874 struct mlx5_ifc_dealloc_sf_out_bits { 11875 u8 status[0x8]; 11876 u8 reserved_at_8[0x18]; 11877 11878 u8 syndrome[0x20]; 11879 11880 u8 reserved_at_40[0x40]; 11881 }; 11882 11883 struct mlx5_ifc_dealloc_sf_in_bits { 11884 u8 opcode[0x10]; 11885 u8 reserved_at_10[0x10]; 11886 11887 u8 reserved_at_20[0x10]; 11888 u8 op_mod[0x10]; 11889 11890 u8 reserved_at_40[0x10]; 11891 u8 function_id[0x10]; 11892 11893 u8 reserved_at_60[0x20]; 11894 }; 11895 11896 struct mlx5_ifc_alloc_sf_out_bits { 11897 u8 status[0x8]; 11898 u8 reserved_at_8[0x18]; 11899 11900 u8 syndrome[0x20]; 11901 11902 u8 reserved_at_40[0x40]; 11903 }; 11904 11905 struct mlx5_ifc_alloc_sf_in_bits { 11906 u8 opcode[0x10]; 11907 u8 reserved_at_10[0x10]; 11908 11909 u8 reserved_at_20[0x10]; 11910 u8 op_mod[0x10]; 11911 11912 u8 reserved_at_40[0x10]; 11913 u8 function_id[0x10]; 11914 11915 u8 reserved_at_60[0x20]; 11916 }; 11917 11918 struct mlx5_ifc_affiliated_event_header_bits { 11919 u8 reserved_at_0[0x10]; 11920 u8 obj_type[0x10]; 11921 11922 u8 obj_id[0x20]; 11923 }; 11924 11925 enum { 11926 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11927 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11928 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11929 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11930 }; 11931 11932 enum { 11933 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11934 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11935 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11936 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11937 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11938 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11939 }; 11940 11941 enum { 11942 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11943 }; 11944 11945 enum { 11946 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11947 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11948 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11949 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11950 }; 11951 11952 enum { 11953 MLX5_IPSEC_ASO_MODE = 0x0, 11954 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11955 MLX5_IPSEC_ASO_INC_SN = 0x2, 11956 }; 11957 11958 struct mlx5_ifc_ipsec_aso_bits { 11959 u8 valid[0x1]; 11960 u8 reserved_at_201[0x1]; 11961 u8 mode[0x2]; 11962 u8 window_sz[0x2]; 11963 u8 soft_lft_arm[0x1]; 11964 u8 hard_lft_arm[0x1]; 11965 u8 remove_flow_enable[0x1]; 11966 u8 esn_event_arm[0x1]; 11967 u8 reserved_at_20a[0x16]; 11968 11969 u8 remove_flow_pkt_cnt[0x20]; 11970 11971 u8 remove_flow_soft_lft[0x20]; 11972 11973 u8 reserved_at_260[0x80]; 11974 11975 u8 mode_parameter[0x20]; 11976 11977 u8 replay_protection_window[0x100]; 11978 }; 11979 11980 struct mlx5_ifc_ipsec_obj_bits { 11981 u8 modify_field_select[0x40]; 11982 u8 full_offload[0x1]; 11983 u8 reserved_at_41[0x1]; 11984 u8 esn_en[0x1]; 11985 u8 esn_overlap[0x1]; 11986 u8 reserved_at_44[0x2]; 11987 u8 icv_length[0x2]; 11988 u8 reserved_at_48[0x4]; 11989 u8 aso_return_reg[0x4]; 11990 u8 reserved_at_50[0x10]; 11991 11992 u8 esn_msb[0x20]; 11993 11994 u8 reserved_at_80[0x8]; 11995 u8 dekn[0x18]; 11996 11997 u8 salt[0x20]; 11998 11999 u8 implicit_iv[0x40]; 12000 12001 u8 reserved_at_100[0x8]; 12002 u8 ipsec_aso_access_pd[0x18]; 12003 u8 reserved_at_120[0xe0]; 12004 12005 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12006 }; 12007 12008 struct mlx5_ifc_create_ipsec_obj_in_bits { 12009 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12010 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12011 }; 12012 12013 enum { 12014 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12015 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12016 }; 12017 12018 struct mlx5_ifc_query_ipsec_obj_out_bits { 12019 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12020 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12021 }; 12022 12023 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12024 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12025 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12026 }; 12027 12028 enum { 12029 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12030 }; 12031 12032 enum { 12033 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12034 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12035 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12036 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12037 }; 12038 12039 #define MLX5_MACSEC_ASO_INC_SN 0x2 12040 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12041 12042 struct mlx5_ifc_macsec_aso_bits { 12043 u8 valid[0x1]; 12044 u8 reserved_at_1[0x1]; 12045 u8 mode[0x2]; 12046 u8 window_size[0x2]; 12047 u8 soft_lifetime_arm[0x1]; 12048 u8 hard_lifetime_arm[0x1]; 12049 u8 remove_flow_enable[0x1]; 12050 u8 epn_event_arm[0x1]; 12051 u8 reserved_at_a[0x16]; 12052 12053 u8 remove_flow_packet_count[0x20]; 12054 12055 u8 remove_flow_soft_lifetime[0x20]; 12056 12057 u8 reserved_at_60[0x80]; 12058 12059 u8 mode_parameter[0x20]; 12060 12061 u8 replay_protection_window[8][0x20]; 12062 }; 12063 12064 struct mlx5_ifc_macsec_offload_obj_bits { 12065 u8 modify_field_select[0x40]; 12066 12067 u8 confidentiality_en[0x1]; 12068 u8 reserved_at_41[0x1]; 12069 u8 epn_en[0x1]; 12070 u8 epn_overlap[0x1]; 12071 u8 reserved_at_44[0x2]; 12072 u8 confidentiality_offset[0x2]; 12073 u8 reserved_at_48[0x4]; 12074 u8 aso_return_reg[0x4]; 12075 u8 reserved_at_50[0x10]; 12076 12077 u8 epn_msb[0x20]; 12078 12079 u8 reserved_at_80[0x8]; 12080 u8 dekn[0x18]; 12081 12082 u8 reserved_at_a0[0x20]; 12083 12084 u8 sci[0x40]; 12085 12086 u8 reserved_at_100[0x8]; 12087 u8 macsec_aso_access_pd[0x18]; 12088 12089 u8 reserved_at_120[0x60]; 12090 12091 u8 salt[3][0x20]; 12092 12093 u8 reserved_at_1e0[0x20]; 12094 12095 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12096 }; 12097 12098 struct mlx5_ifc_create_macsec_obj_in_bits { 12099 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12100 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12101 }; 12102 12103 struct mlx5_ifc_modify_macsec_obj_in_bits { 12104 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12105 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12106 }; 12107 12108 enum { 12109 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12110 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12111 }; 12112 12113 struct mlx5_ifc_query_macsec_obj_out_bits { 12114 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12115 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12116 }; 12117 12118 struct mlx5_ifc_wrapped_dek_bits { 12119 u8 gcm_iv[0x60]; 12120 12121 u8 reserved_at_60[0x20]; 12122 12123 u8 const0[0x1]; 12124 u8 key_size[0x1]; 12125 u8 reserved_at_82[0x2]; 12126 u8 key2_invalid[0x1]; 12127 u8 reserved_at_85[0x3]; 12128 u8 pd[0x18]; 12129 12130 u8 key_purpose[0x5]; 12131 u8 reserved_at_a5[0x13]; 12132 u8 kek_id[0x8]; 12133 12134 u8 reserved_at_c0[0x40]; 12135 12136 u8 key1[0x8][0x20]; 12137 12138 u8 key2[0x8][0x20]; 12139 12140 u8 reserved_at_300[0x40]; 12141 12142 u8 const1[0x1]; 12143 u8 reserved_at_341[0x1f]; 12144 12145 u8 reserved_at_360[0x20]; 12146 12147 u8 auth_tag[0x80]; 12148 }; 12149 12150 struct mlx5_ifc_encryption_key_obj_bits { 12151 u8 modify_field_select[0x40]; 12152 12153 u8 state[0x8]; 12154 u8 sw_wrapped[0x1]; 12155 u8 reserved_at_49[0xb]; 12156 u8 key_size[0x4]; 12157 u8 reserved_at_58[0x4]; 12158 u8 key_purpose[0x4]; 12159 12160 u8 reserved_at_60[0x8]; 12161 u8 pd[0x18]; 12162 12163 u8 reserved_at_80[0x100]; 12164 12165 u8 opaque[0x40]; 12166 12167 u8 reserved_at_1c0[0x40]; 12168 12169 u8 key[8][0x80]; 12170 12171 u8 sw_wrapped_dek[8][0x80]; 12172 12173 u8 reserved_at_a00[0x600]; 12174 }; 12175 12176 struct mlx5_ifc_create_encryption_key_in_bits { 12177 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12178 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12179 }; 12180 12181 struct mlx5_ifc_modify_encryption_key_in_bits { 12182 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12183 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12184 }; 12185 12186 enum { 12187 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12188 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12189 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12190 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12191 }; 12192 12193 struct mlx5_ifc_flow_meter_parameters_bits { 12194 u8 valid[0x1]; 12195 u8 bucket_overflow[0x1]; 12196 u8 start_color[0x2]; 12197 u8 both_buckets_on_green[0x1]; 12198 u8 reserved_at_5[0x1]; 12199 u8 meter_mode[0x2]; 12200 u8 reserved_at_8[0x18]; 12201 12202 u8 reserved_at_20[0x20]; 12203 12204 u8 reserved_at_40[0x3]; 12205 u8 cbs_exponent[0x5]; 12206 u8 cbs_mantissa[0x8]; 12207 u8 reserved_at_50[0x3]; 12208 u8 cir_exponent[0x5]; 12209 u8 cir_mantissa[0x8]; 12210 12211 u8 reserved_at_60[0x20]; 12212 12213 u8 reserved_at_80[0x3]; 12214 u8 ebs_exponent[0x5]; 12215 u8 ebs_mantissa[0x8]; 12216 u8 reserved_at_90[0x3]; 12217 u8 eir_exponent[0x5]; 12218 u8 eir_mantissa[0x8]; 12219 12220 u8 reserved_at_a0[0x60]; 12221 }; 12222 12223 struct mlx5_ifc_flow_meter_aso_obj_bits { 12224 u8 modify_field_select[0x40]; 12225 12226 u8 reserved_at_40[0x40]; 12227 12228 u8 reserved_at_80[0x8]; 12229 u8 meter_aso_access_pd[0x18]; 12230 12231 u8 reserved_at_a0[0x160]; 12232 12233 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12234 }; 12235 12236 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12237 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12238 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12239 }; 12240 12241 struct mlx5_ifc_int_kek_obj_bits { 12242 u8 modify_field_select[0x40]; 12243 12244 u8 state[0x8]; 12245 u8 auto_gen[0x1]; 12246 u8 reserved_at_49[0xb]; 12247 u8 key_size[0x4]; 12248 u8 reserved_at_58[0x8]; 12249 12250 u8 reserved_at_60[0x8]; 12251 u8 pd[0x18]; 12252 12253 u8 reserved_at_80[0x180]; 12254 u8 key[8][0x80]; 12255 12256 u8 reserved_at_600[0x200]; 12257 }; 12258 12259 struct mlx5_ifc_create_int_kek_obj_in_bits { 12260 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12261 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12262 }; 12263 12264 struct mlx5_ifc_create_int_kek_obj_out_bits { 12265 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12266 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12267 }; 12268 12269 struct mlx5_ifc_sampler_obj_bits { 12270 u8 modify_field_select[0x40]; 12271 12272 u8 table_type[0x8]; 12273 u8 level[0x8]; 12274 u8 reserved_at_50[0xf]; 12275 u8 ignore_flow_level[0x1]; 12276 12277 u8 sample_ratio[0x20]; 12278 12279 u8 reserved_at_80[0x8]; 12280 u8 sample_table_id[0x18]; 12281 12282 u8 reserved_at_a0[0x8]; 12283 u8 default_table_id[0x18]; 12284 12285 u8 sw_steering_icm_address_rx[0x40]; 12286 u8 sw_steering_icm_address_tx[0x40]; 12287 12288 u8 reserved_at_140[0xa0]; 12289 }; 12290 12291 struct mlx5_ifc_create_sampler_obj_in_bits { 12292 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12293 struct mlx5_ifc_sampler_obj_bits sampler_object; 12294 }; 12295 12296 struct mlx5_ifc_query_sampler_obj_out_bits { 12297 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12298 struct mlx5_ifc_sampler_obj_bits sampler_object; 12299 }; 12300 12301 enum { 12302 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12303 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12304 }; 12305 12306 enum { 12307 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12308 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12309 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12310 }; 12311 12312 struct mlx5_ifc_tls_static_params_bits { 12313 u8 const_2[0x2]; 12314 u8 tls_version[0x4]; 12315 u8 const_1[0x2]; 12316 u8 reserved_at_8[0x14]; 12317 u8 encryption_standard[0x4]; 12318 12319 u8 reserved_at_20[0x20]; 12320 12321 u8 initial_record_number[0x40]; 12322 12323 u8 resync_tcp_sn[0x20]; 12324 12325 u8 gcm_iv[0x20]; 12326 12327 u8 implicit_iv[0x40]; 12328 12329 u8 reserved_at_100[0x8]; 12330 u8 dek_index[0x18]; 12331 12332 u8 reserved_at_120[0xe0]; 12333 }; 12334 12335 struct mlx5_ifc_tls_progress_params_bits { 12336 u8 next_record_tcp_sn[0x20]; 12337 12338 u8 hw_resync_tcp_sn[0x20]; 12339 12340 u8 record_tracker_state[0x2]; 12341 u8 auth_state[0x2]; 12342 u8 reserved_at_44[0x4]; 12343 u8 hw_offset_record_number[0x18]; 12344 }; 12345 12346 enum { 12347 MLX5_MTT_PERM_READ = 1 << 0, 12348 MLX5_MTT_PERM_WRITE = 1 << 1, 12349 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12350 }; 12351 12352 enum { 12353 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12354 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12355 }; 12356 12357 struct mlx5_ifc_suspend_vhca_in_bits { 12358 u8 opcode[0x10]; 12359 u8 uid[0x10]; 12360 12361 u8 reserved_at_20[0x10]; 12362 u8 op_mod[0x10]; 12363 12364 u8 reserved_at_40[0x10]; 12365 u8 vhca_id[0x10]; 12366 12367 u8 reserved_at_60[0x20]; 12368 }; 12369 12370 struct mlx5_ifc_suspend_vhca_out_bits { 12371 u8 status[0x8]; 12372 u8 reserved_at_8[0x18]; 12373 12374 u8 syndrome[0x20]; 12375 12376 u8 reserved_at_40[0x40]; 12377 }; 12378 12379 enum { 12380 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12381 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12382 }; 12383 12384 struct mlx5_ifc_resume_vhca_in_bits { 12385 u8 opcode[0x10]; 12386 u8 uid[0x10]; 12387 12388 u8 reserved_at_20[0x10]; 12389 u8 op_mod[0x10]; 12390 12391 u8 reserved_at_40[0x10]; 12392 u8 vhca_id[0x10]; 12393 12394 u8 reserved_at_60[0x20]; 12395 }; 12396 12397 struct mlx5_ifc_resume_vhca_out_bits { 12398 u8 status[0x8]; 12399 u8 reserved_at_8[0x18]; 12400 12401 u8 syndrome[0x20]; 12402 12403 u8 reserved_at_40[0x40]; 12404 }; 12405 12406 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12407 u8 opcode[0x10]; 12408 u8 uid[0x10]; 12409 12410 u8 reserved_at_20[0x10]; 12411 u8 op_mod[0x10]; 12412 12413 u8 incremental[0x1]; 12414 u8 reserved_at_41[0xf]; 12415 u8 vhca_id[0x10]; 12416 12417 u8 reserved_at_60[0x20]; 12418 }; 12419 12420 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12421 u8 status[0x8]; 12422 u8 reserved_at_8[0x18]; 12423 12424 u8 syndrome[0x20]; 12425 12426 u8 reserved_at_40[0x40]; 12427 12428 u8 required_umem_size[0x20]; 12429 12430 u8 reserved_at_a0[0x160]; 12431 }; 12432 12433 struct mlx5_ifc_save_vhca_state_in_bits { 12434 u8 opcode[0x10]; 12435 u8 uid[0x10]; 12436 12437 u8 reserved_at_20[0x10]; 12438 u8 op_mod[0x10]; 12439 12440 u8 incremental[0x1]; 12441 u8 set_track[0x1]; 12442 u8 reserved_at_42[0xe]; 12443 u8 vhca_id[0x10]; 12444 12445 u8 reserved_at_60[0x20]; 12446 12447 u8 va[0x40]; 12448 12449 u8 mkey[0x20]; 12450 12451 u8 size[0x20]; 12452 }; 12453 12454 struct mlx5_ifc_save_vhca_state_out_bits { 12455 u8 status[0x8]; 12456 u8 reserved_at_8[0x18]; 12457 12458 u8 syndrome[0x20]; 12459 12460 u8 actual_image_size[0x20]; 12461 12462 u8 reserved_at_60[0x20]; 12463 }; 12464 12465 struct mlx5_ifc_load_vhca_state_in_bits { 12466 u8 opcode[0x10]; 12467 u8 uid[0x10]; 12468 12469 u8 reserved_at_20[0x10]; 12470 u8 op_mod[0x10]; 12471 12472 u8 reserved_at_40[0x10]; 12473 u8 vhca_id[0x10]; 12474 12475 u8 reserved_at_60[0x20]; 12476 12477 u8 va[0x40]; 12478 12479 u8 mkey[0x20]; 12480 12481 u8 size[0x20]; 12482 }; 12483 12484 struct mlx5_ifc_load_vhca_state_out_bits { 12485 u8 status[0x8]; 12486 u8 reserved_at_8[0x18]; 12487 12488 u8 syndrome[0x20]; 12489 12490 u8 reserved_at_40[0x40]; 12491 }; 12492 12493 struct mlx5_ifc_adv_virtualization_cap_bits { 12494 u8 reserved_at_0[0x3]; 12495 u8 pg_track_log_max_num[0x5]; 12496 u8 pg_track_max_num_range[0x8]; 12497 u8 pg_track_log_min_addr_space[0x8]; 12498 u8 pg_track_log_max_addr_space[0x8]; 12499 12500 u8 reserved_at_20[0x3]; 12501 u8 pg_track_log_min_msg_size[0x5]; 12502 u8 reserved_at_28[0x3]; 12503 u8 pg_track_log_max_msg_size[0x5]; 12504 u8 reserved_at_30[0x3]; 12505 u8 pg_track_log_min_page_size[0x5]; 12506 u8 reserved_at_38[0x3]; 12507 u8 pg_track_log_max_page_size[0x5]; 12508 12509 u8 reserved_at_40[0x7c0]; 12510 }; 12511 12512 struct mlx5_ifc_page_track_report_entry_bits { 12513 u8 dirty_address_high[0x20]; 12514 12515 u8 dirty_address_low[0x20]; 12516 }; 12517 12518 enum { 12519 MLX5_PAGE_TRACK_STATE_TRACKING, 12520 MLX5_PAGE_TRACK_STATE_REPORTING, 12521 MLX5_PAGE_TRACK_STATE_ERROR, 12522 }; 12523 12524 struct mlx5_ifc_page_track_range_bits { 12525 u8 start_address[0x40]; 12526 12527 u8 length[0x40]; 12528 }; 12529 12530 struct mlx5_ifc_page_track_bits { 12531 u8 modify_field_select[0x40]; 12532 12533 u8 reserved_at_40[0x10]; 12534 u8 vhca_id[0x10]; 12535 12536 u8 reserved_at_60[0x20]; 12537 12538 u8 state[0x4]; 12539 u8 track_type[0x4]; 12540 u8 log_addr_space_size[0x8]; 12541 u8 reserved_at_90[0x3]; 12542 u8 log_page_size[0x5]; 12543 u8 reserved_at_98[0x3]; 12544 u8 log_msg_size[0x5]; 12545 12546 u8 reserved_at_a0[0x8]; 12547 u8 reporting_qpn[0x18]; 12548 12549 u8 reserved_at_c0[0x18]; 12550 u8 num_ranges[0x8]; 12551 12552 u8 reserved_at_e0[0x20]; 12553 12554 u8 range_start_address[0x40]; 12555 12556 u8 length[0x40]; 12557 12558 struct mlx5_ifc_page_track_range_bits track_range[0]; 12559 }; 12560 12561 struct mlx5_ifc_create_page_track_obj_in_bits { 12562 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12563 struct mlx5_ifc_page_track_bits obj_context; 12564 }; 12565 12566 struct mlx5_ifc_modify_page_track_obj_in_bits { 12567 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12568 struct mlx5_ifc_page_track_bits obj_context; 12569 }; 12570 12571 #endif /* MLX5_IFC_H */ 12572