1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 86 }; 87 88 enum { 89 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 90 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 91 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 92 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 }; 108 109 enum { 110 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 111 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 112 MLX5_CMD_OP_INIT_HCA = 0x102, 113 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 114 MLX5_CMD_OP_ENABLE_HCA = 0x104, 115 MLX5_CMD_OP_DISABLE_HCA = 0x105, 116 MLX5_CMD_OP_QUERY_PAGES = 0x107, 117 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 118 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 119 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 120 MLX5_CMD_OP_SET_ISSI = 0x10b, 121 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 122 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 123 MLX5_CMD_OP_ALLOC_SF = 0x113, 124 MLX5_CMD_OP_DEALLOC_SF = 0x114, 125 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 126 MLX5_CMD_OP_RESUME_VHCA = 0x116, 127 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 128 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 129 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 130 MLX5_CMD_OP_CREATE_MKEY = 0x200, 131 MLX5_CMD_OP_QUERY_MKEY = 0x201, 132 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 133 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 134 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 135 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 136 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 137 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 138 MLX5_CMD_OP_CREATE_EQ = 0x301, 139 MLX5_CMD_OP_DESTROY_EQ = 0x302, 140 MLX5_CMD_OP_QUERY_EQ = 0x303, 141 MLX5_CMD_OP_GEN_EQE = 0x304, 142 MLX5_CMD_OP_CREATE_CQ = 0x400, 143 MLX5_CMD_OP_DESTROY_CQ = 0x401, 144 MLX5_CMD_OP_QUERY_CQ = 0x402, 145 MLX5_CMD_OP_MODIFY_CQ = 0x403, 146 MLX5_CMD_OP_CREATE_QP = 0x500, 147 MLX5_CMD_OP_DESTROY_QP = 0x501, 148 MLX5_CMD_OP_RST2INIT_QP = 0x502, 149 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 150 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 151 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 152 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 153 MLX5_CMD_OP_2ERR_QP = 0x507, 154 MLX5_CMD_OP_2RST_QP = 0x50a, 155 MLX5_CMD_OP_QUERY_QP = 0x50b, 156 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 157 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 158 MLX5_CMD_OP_CREATE_PSV = 0x600, 159 MLX5_CMD_OP_DESTROY_PSV = 0x601, 160 MLX5_CMD_OP_CREATE_SRQ = 0x700, 161 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 162 MLX5_CMD_OP_QUERY_SRQ = 0x702, 163 MLX5_CMD_OP_ARM_RQ = 0x703, 164 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 165 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 166 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 167 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 168 MLX5_CMD_OP_CREATE_DCT = 0x710, 169 MLX5_CMD_OP_DESTROY_DCT = 0x711, 170 MLX5_CMD_OP_DRAIN_DCT = 0x712, 171 MLX5_CMD_OP_QUERY_DCT = 0x713, 172 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 173 MLX5_CMD_OP_CREATE_XRQ = 0x717, 174 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 175 MLX5_CMD_OP_QUERY_XRQ = 0x719, 176 MLX5_CMD_OP_ARM_XRQ = 0x71a, 177 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 178 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 179 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 180 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 181 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 182 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 183 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 184 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 185 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 186 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 187 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 188 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 189 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 190 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 192 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 195 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 196 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 197 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 198 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 199 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 200 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 201 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 202 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 203 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 204 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 205 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 206 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 207 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 208 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 209 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 210 MLX5_CMD_OP_ALLOC_PD = 0x800, 211 MLX5_CMD_OP_DEALLOC_PD = 0x801, 212 MLX5_CMD_OP_ALLOC_UAR = 0x802, 213 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 214 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 215 MLX5_CMD_OP_ACCESS_REG = 0x805, 216 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 217 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 218 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 219 MLX5_CMD_OP_MAD_IFC = 0x50d, 220 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 221 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 222 MLX5_CMD_OP_NOP = 0x80d, 223 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 224 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 225 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 226 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 227 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 228 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 229 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 230 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 231 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 232 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 233 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 234 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 235 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 236 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 237 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 238 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 239 MLX5_CMD_OP_CREATE_LAG = 0x840, 240 MLX5_CMD_OP_MODIFY_LAG = 0x841, 241 MLX5_CMD_OP_QUERY_LAG = 0x842, 242 MLX5_CMD_OP_DESTROY_LAG = 0x843, 243 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 244 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 245 MLX5_CMD_OP_CREATE_TIR = 0x900, 246 MLX5_CMD_OP_MODIFY_TIR = 0x901, 247 MLX5_CMD_OP_DESTROY_TIR = 0x902, 248 MLX5_CMD_OP_QUERY_TIR = 0x903, 249 MLX5_CMD_OP_CREATE_SQ = 0x904, 250 MLX5_CMD_OP_MODIFY_SQ = 0x905, 251 MLX5_CMD_OP_DESTROY_SQ = 0x906, 252 MLX5_CMD_OP_QUERY_SQ = 0x907, 253 MLX5_CMD_OP_CREATE_RQ = 0x908, 254 MLX5_CMD_OP_MODIFY_RQ = 0x909, 255 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 256 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 257 MLX5_CMD_OP_QUERY_RQ = 0x90b, 258 MLX5_CMD_OP_CREATE_RMP = 0x90c, 259 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 260 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 261 MLX5_CMD_OP_QUERY_RMP = 0x90f, 262 MLX5_CMD_OP_CREATE_TIS = 0x912, 263 MLX5_CMD_OP_MODIFY_TIS = 0x913, 264 MLX5_CMD_OP_DESTROY_TIS = 0x914, 265 MLX5_CMD_OP_QUERY_TIS = 0x915, 266 MLX5_CMD_OP_CREATE_RQT = 0x916, 267 MLX5_CMD_OP_MODIFY_RQT = 0x917, 268 MLX5_CMD_OP_DESTROY_RQT = 0x918, 269 MLX5_CMD_OP_QUERY_RQT = 0x919, 270 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 271 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 272 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 273 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 274 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 275 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 276 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 277 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 278 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 279 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 280 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 281 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 282 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 283 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 284 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 285 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 286 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 287 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 288 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 289 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 290 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 291 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 292 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 293 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 294 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 295 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 296 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 297 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 298 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 299 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 300 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 301 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 302 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 303 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 304 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 305 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 306 MLX5_CMD_OP_MAX 307 }; 308 309 /* Valid range for general commands that don't work over an object */ 310 enum { 311 MLX5_CMD_OP_GENERAL_START = 0xb00, 312 MLX5_CMD_OP_GENERAL_END = 0xd00, 313 }; 314 315 struct mlx5_ifc_flow_table_fields_supported_bits { 316 u8 outer_dmac[0x1]; 317 u8 outer_smac[0x1]; 318 u8 outer_ether_type[0x1]; 319 u8 outer_ip_version[0x1]; 320 u8 outer_first_prio[0x1]; 321 u8 outer_first_cfi[0x1]; 322 u8 outer_first_vid[0x1]; 323 u8 outer_ipv4_ttl[0x1]; 324 u8 outer_second_prio[0x1]; 325 u8 outer_second_cfi[0x1]; 326 u8 outer_second_vid[0x1]; 327 u8 reserved_at_b[0x1]; 328 u8 outer_sip[0x1]; 329 u8 outer_dip[0x1]; 330 u8 outer_frag[0x1]; 331 u8 outer_ip_protocol[0x1]; 332 u8 outer_ip_ecn[0x1]; 333 u8 outer_ip_dscp[0x1]; 334 u8 outer_udp_sport[0x1]; 335 u8 outer_udp_dport[0x1]; 336 u8 outer_tcp_sport[0x1]; 337 u8 outer_tcp_dport[0x1]; 338 u8 outer_tcp_flags[0x1]; 339 u8 outer_gre_protocol[0x1]; 340 u8 outer_gre_key[0x1]; 341 u8 outer_vxlan_vni[0x1]; 342 u8 outer_geneve_vni[0x1]; 343 u8 outer_geneve_oam[0x1]; 344 u8 outer_geneve_protocol_type[0x1]; 345 u8 outer_geneve_opt_len[0x1]; 346 u8 source_vhca_port[0x1]; 347 u8 source_eswitch_port[0x1]; 348 349 u8 inner_dmac[0x1]; 350 u8 inner_smac[0x1]; 351 u8 inner_ether_type[0x1]; 352 u8 inner_ip_version[0x1]; 353 u8 inner_first_prio[0x1]; 354 u8 inner_first_cfi[0x1]; 355 u8 inner_first_vid[0x1]; 356 u8 reserved_at_27[0x1]; 357 u8 inner_second_prio[0x1]; 358 u8 inner_second_cfi[0x1]; 359 u8 inner_second_vid[0x1]; 360 u8 reserved_at_2b[0x1]; 361 u8 inner_sip[0x1]; 362 u8 inner_dip[0x1]; 363 u8 inner_frag[0x1]; 364 u8 inner_ip_protocol[0x1]; 365 u8 inner_ip_ecn[0x1]; 366 u8 inner_ip_dscp[0x1]; 367 u8 inner_udp_sport[0x1]; 368 u8 inner_udp_dport[0x1]; 369 u8 inner_tcp_sport[0x1]; 370 u8 inner_tcp_dport[0x1]; 371 u8 inner_tcp_flags[0x1]; 372 u8 reserved_at_37[0x9]; 373 374 u8 geneve_tlv_option_0_data[0x1]; 375 u8 geneve_tlv_option_0_exist[0x1]; 376 u8 reserved_at_42[0x3]; 377 u8 outer_first_mpls_over_udp[0x4]; 378 u8 outer_first_mpls_over_gre[0x4]; 379 u8 inner_first_mpls[0x4]; 380 u8 outer_first_mpls[0x4]; 381 u8 reserved_at_55[0x2]; 382 u8 outer_esp_spi[0x1]; 383 u8 reserved_at_58[0x2]; 384 u8 bth_dst_qp[0x1]; 385 u8 reserved_at_5b[0x5]; 386 387 u8 reserved_at_60[0x18]; 388 u8 metadata_reg_c_7[0x1]; 389 u8 metadata_reg_c_6[0x1]; 390 u8 metadata_reg_c_5[0x1]; 391 u8 metadata_reg_c_4[0x1]; 392 u8 metadata_reg_c_3[0x1]; 393 u8 metadata_reg_c_2[0x1]; 394 u8 metadata_reg_c_1[0x1]; 395 u8 metadata_reg_c_0[0x1]; 396 }; 397 398 struct mlx5_ifc_flow_table_fields_supported_2_bits { 399 u8 reserved_at_0[0xe]; 400 u8 bth_opcode[0x1]; 401 u8 reserved_at_f[0x11]; 402 403 u8 reserved_at_20[0x60]; 404 }; 405 406 struct mlx5_ifc_flow_table_prop_layout_bits { 407 u8 ft_support[0x1]; 408 u8 reserved_at_1[0x1]; 409 u8 flow_counter[0x1]; 410 u8 flow_modify_en[0x1]; 411 u8 modify_root[0x1]; 412 u8 identified_miss_table_mode[0x1]; 413 u8 flow_table_modify[0x1]; 414 u8 reformat[0x1]; 415 u8 decap[0x1]; 416 u8 reserved_at_9[0x1]; 417 u8 pop_vlan[0x1]; 418 u8 push_vlan[0x1]; 419 u8 reserved_at_c[0x1]; 420 u8 pop_vlan_2[0x1]; 421 u8 push_vlan_2[0x1]; 422 u8 reformat_and_vlan_action[0x1]; 423 u8 reserved_at_10[0x1]; 424 u8 sw_owner[0x1]; 425 u8 reformat_l3_tunnel_to_l2[0x1]; 426 u8 reformat_l2_to_l3_tunnel[0x1]; 427 u8 reformat_and_modify_action[0x1]; 428 u8 ignore_flow_level[0x1]; 429 u8 reserved_at_16[0x1]; 430 u8 table_miss_action_domain[0x1]; 431 u8 termination_table[0x1]; 432 u8 reformat_and_fwd_to_table[0x1]; 433 u8 reserved_at_1a[0x2]; 434 u8 ipsec_encrypt[0x1]; 435 u8 ipsec_decrypt[0x1]; 436 u8 sw_owner_v2[0x1]; 437 u8 reserved_at_1f[0x1]; 438 439 u8 termination_table_raw_traffic[0x1]; 440 u8 reserved_at_21[0x1]; 441 u8 log_max_ft_size[0x6]; 442 u8 log_max_modify_header_context[0x8]; 443 u8 max_modify_header_actions[0x8]; 444 u8 max_ft_level[0x8]; 445 446 u8 reserved_at_40[0x6]; 447 u8 execute_aso[0x1]; 448 u8 reserved_at_47[0x19]; 449 450 u8 reserved_at_60[0x2]; 451 u8 reformat_insert[0x1]; 452 u8 reformat_remove[0x1]; 453 u8 macsec_encrypt[0x1]; 454 u8 macsec_decrypt[0x1]; 455 u8 reserved_at_66[0x2]; 456 u8 reformat_add_macsec[0x1]; 457 u8 reformat_remove_macsec[0x1]; 458 u8 reserved_at_6a[0xe]; 459 u8 log_max_ft_num[0x8]; 460 461 u8 reserved_at_80[0x10]; 462 u8 log_max_flow_counter[0x8]; 463 u8 log_max_destination[0x8]; 464 465 u8 reserved_at_a0[0x18]; 466 u8 log_max_flow[0x8]; 467 468 u8 reserved_at_c0[0x40]; 469 470 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 471 472 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 473 }; 474 475 struct mlx5_ifc_odp_per_transport_service_cap_bits { 476 u8 send[0x1]; 477 u8 receive[0x1]; 478 u8 write[0x1]; 479 u8 read[0x1]; 480 u8 atomic[0x1]; 481 u8 srq_receive[0x1]; 482 u8 reserved_at_6[0x1a]; 483 }; 484 485 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 486 u8 smac_47_16[0x20]; 487 488 u8 smac_15_0[0x10]; 489 u8 ethertype[0x10]; 490 491 u8 dmac_47_16[0x20]; 492 493 u8 dmac_15_0[0x10]; 494 u8 first_prio[0x3]; 495 u8 first_cfi[0x1]; 496 u8 first_vid[0xc]; 497 498 u8 ip_protocol[0x8]; 499 u8 ip_dscp[0x6]; 500 u8 ip_ecn[0x2]; 501 u8 cvlan_tag[0x1]; 502 u8 svlan_tag[0x1]; 503 u8 frag[0x1]; 504 u8 ip_version[0x4]; 505 u8 tcp_flags[0x9]; 506 507 u8 tcp_sport[0x10]; 508 u8 tcp_dport[0x10]; 509 510 u8 reserved_at_c0[0x10]; 511 u8 ipv4_ihl[0x4]; 512 u8 reserved_at_c4[0x4]; 513 514 u8 ttl_hoplimit[0x8]; 515 516 u8 udp_sport[0x10]; 517 u8 udp_dport[0x10]; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 520 521 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 522 }; 523 524 struct mlx5_ifc_nvgre_key_bits { 525 u8 hi[0x18]; 526 u8 lo[0x8]; 527 }; 528 529 union mlx5_ifc_gre_key_bits { 530 struct mlx5_ifc_nvgre_key_bits nvgre; 531 u8 key[0x20]; 532 }; 533 534 struct mlx5_ifc_fte_match_set_misc_bits { 535 u8 gre_c_present[0x1]; 536 u8 reserved_at_1[0x1]; 537 u8 gre_k_present[0x1]; 538 u8 gre_s_present[0x1]; 539 u8 source_vhca_port[0x4]; 540 u8 source_sqn[0x18]; 541 542 u8 source_eswitch_owner_vhca_id[0x10]; 543 u8 source_port[0x10]; 544 545 u8 outer_second_prio[0x3]; 546 u8 outer_second_cfi[0x1]; 547 u8 outer_second_vid[0xc]; 548 u8 inner_second_prio[0x3]; 549 u8 inner_second_cfi[0x1]; 550 u8 inner_second_vid[0xc]; 551 552 u8 outer_second_cvlan_tag[0x1]; 553 u8 inner_second_cvlan_tag[0x1]; 554 u8 outer_second_svlan_tag[0x1]; 555 u8 inner_second_svlan_tag[0x1]; 556 u8 reserved_at_64[0xc]; 557 u8 gre_protocol[0x10]; 558 559 union mlx5_ifc_gre_key_bits gre_key; 560 561 u8 vxlan_vni[0x18]; 562 u8 bth_opcode[0x8]; 563 564 u8 geneve_vni[0x18]; 565 u8 reserved_at_d8[0x6]; 566 u8 geneve_tlv_option_0_exist[0x1]; 567 u8 geneve_oam[0x1]; 568 569 u8 reserved_at_e0[0xc]; 570 u8 outer_ipv6_flow_label[0x14]; 571 572 u8 reserved_at_100[0xc]; 573 u8 inner_ipv6_flow_label[0x14]; 574 575 u8 reserved_at_120[0xa]; 576 u8 geneve_opt_len[0x6]; 577 u8 geneve_protocol_type[0x10]; 578 579 u8 reserved_at_140[0x8]; 580 u8 bth_dst_qp[0x18]; 581 u8 reserved_at_160[0x20]; 582 u8 outer_esp_spi[0x20]; 583 u8 reserved_at_1a0[0x60]; 584 }; 585 586 struct mlx5_ifc_fte_match_mpls_bits { 587 u8 mpls_label[0x14]; 588 u8 mpls_exp[0x3]; 589 u8 mpls_s_bos[0x1]; 590 u8 mpls_ttl[0x8]; 591 }; 592 593 struct mlx5_ifc_fte_match_set_misc2_bits { 594 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 595 596 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 597 598 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 599 600 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 601 602 u8 metadata_reg_c_7[0x20]; 603 604 u8 metadata_reg_c_6[0x20]; 605 606 u8 metadata_reg_c_5[0x20]; 607 608 u8 metadata_reg_c_4[0x20]; 609 610 u8 metadata_reg_c_3[0x20]; 611 612 u8 metadata_reg_c_2[0x20]; 613 614 u8 metadata_reg_c_1[0x20]; 615 616 u8 metadata_reg_c_0[0x20]; 617 618 u8 metadata_reg_a[0x20]; 619 620 u8 reserved_at_1a0[0x8]; 621 622 u8 macsec_syndrome[0x8]; 623 624 u8 reserved_at_1b0[0x50]; 625 }; 626 627 struct mlx5_ifc_fte_match_set_misc3_bits { 628 u8 inner_tcp_seq_num[0x20]; 629 630 u8 outer_tcp_seq_num[0x20]; 631 632 u8 inner_tcp_ack_num[0x20]; 633 634 u8 outer_tcp_ack_num[0x20]; 635 636 u8 reserved_at_80[0x8]; 637 u8 outer_vxlan_gpe_vni[0x18]; 638 639 u8 outer_vxlan_gpe_next_protocol[0x8]; 640 u8 outer_vxlan_gpe_flags[0x8]; 641 u8 reserved_at_b0[0x10]; 642 643 u8 icmp_header_data[0x20]; 644 645 u8 icmpv6_header_data[0x20]; 646 647 u8 icmp_type[0x8]; 648 u8 icmp_code[0x8]; 649 u8 icmpv6_type[0x8]; 650 u8 icmpv6_code[0x8]; 651 652 u8 geneve_tlv_option_0_data[0x20]; 653 654 u8 gtpu_teid[0x20]; 655 656 u8 gtpu_msg_type[0x8]; 657 u8 gtpu_msg_flags[0x8]; 658 u8 reserved_at_170[0x10]; 659 660 u8 gtpu_dw_2[0x20]; 661 662 u8 gtpu_first_ext_dw_0[0x20]; 663 664 u8 gtpu_dw_0[0x20]; 665 666 u8 reserved_at_1e0[0x20]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc4_bits { 670 u8 prog_sample_field_value_0[0x20]; 671 672 u8 prog_sample_field_id_0[0x20]; 673 674 u8 prog_sample_field_value_1[0x20]; 675 676 u8 prog_sample_field_id_1[0x20]; 677 678 u8 prog_sample_field_value_2[0x20]; 679 680 u8 prog_sample_field_id_2[0x20]; 681 682 u8 prog_sample_field_value_3[0x20]; 683 684 u8 prog_sample_field_id_3[0x20]; 685 686 u8 reserved_at_100[0x100]; 687 }; 688 689 struct mlx5_ifc_fte_match_set_misc5_bits { 690 u8 macsec_tag_0[0x20]; 691 692 u8 macsec_tag_1[0x20]; 693 694 u8 macsec_tag_2[0x20]; 695 696 u8 macsec_tag_3[0x20]; 697 698 u8 tunnel_header_0[0x20]; 699 700 u8 tunnel_header_1[0x20]; 701 702 u8 tunnel_header_2[0x20]; 703 704 u8 tunnel_header_3[0x20]; 705 706 u8 reserved_at_100[0x100]; 707 }; 708 709 struct mlx5_ifc_cmd_pas_bits { 710 u8 pa_h[0x20]; 711 712 u8 pa_l[0x14]; 713 u8 reserved_at_34[0xc]; 714 }; 715 716 struct mlx5_ifc_uint64_bits { 717 u8 hi[0x20]; 718 719 u8 lo[0x20]; 720 }; 721 722 enum { 723 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 724 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 725 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 726 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 727 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 728 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 729 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 730 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 731 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 732 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 733 }; 734 735 struct mlx5_ifc_ads_bits { 736 u8 fl[0x1]; 737 u8 free_ar[0x1]; 738 u8 reserved_at_2[0xe]; 739 u8 pkey_index[0x10]; 740 741 u8 reserved_at_20[0x8]; 742 u8 grh[0x1]; 743 u8 mlid[0x7]; 744 u8 rlid[0x10]; 745 746 u8 ack_timeout[0x5]; 747 u8 reserved_at_45[0x3]; 748 u8 src_addr_index[0x8]; 749 u8 reserved_at_50[0x4]; 750 u8 stat_rate[0x4]; 751 u8 hop_limit[0x8]; 752 753 u8 reserved_at_60[0x4]; 754 u8 tclass[0x8]; 755 u8 flow_label[0x14]; 756 757 u8 rgid_rip[16][0x8]; 758 759 u8 reserved_at_100[0x4]; 760 u8 f_dscp[0x1]; 761 u8 f_ecn[0x1]; 762 u8 reserved_at_106[0x1]; 763 u8 f_eth_prio[0x1]; 764 u8 ecn[0x2]; 765 u8 dscp[0x6]; 766 u8 udp_sport[0x10]; 767 768 u8 dei_cfi[0x1]; 769 u8 eth_prio[0x3]; 770 u8 sl[0x4]; 771 u8 vhca_port_num[0x8]; 772 u8 rmac_47_32[0x10]; 773 774 u8 rmac_31_0[0x20]; 775 }; 776 777 struct mlx5_ifc_flow_table_nic_cap_bits { 778 u8 nic_rx_multi_path_tirs[0x1]; 779 u8 nic_rx_multi_path_tirs_fts[0x1]; 780 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 781 u8 reserved_at_3[0x4]; 782 u8 sw_owner_reformat_supported[0x1]; 783 u8 reserved_at_8[0x18]; 784 785 u8 encap_general_header[0x1]; 786 u8 reserved_at_21[0xa]; 787 u8 log_max_packet_reformat_context[0x5]; 788 u8 reserved_at_30[0x6]; 789 u8 max_encap_header_size[0xa]; 790 u8 reserved_at_40[0x1c0]; 791 792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 793 794 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 795 796 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 797 798 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 799 800 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 801 802 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 803 804 u8 reserved_at_e00[0x700]; 805 806 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 807 808 u8 reserved_at_1580[0x280]; 809 810 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 811 812 u8 reserved_at_1880[0x780]; 813 814 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 815 816 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 817 818 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 819 820 u8 reserved_at_20c0[0x5f40]; 821 }; 822 823 struct mlx5_ifc_port_selection_cap_bits { 824 u8 reserved_at_0[0x10]; 825 u8 port_select_flow_table[0x1]; 826 u8 reserved_at_11[0xf]; 827 828 u8 reserved_at_20[0x1e0]; 829 830 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 831 832 u8 reserved_at_400[0x7c00]; 833 }; 834 835 enum { 836 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 837 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 838 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 839 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 840 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 841 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 842 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 843 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 844 }; 845 846 struct mlx5_ifc_flow_table_eswitch_cap_bits { 847 u8 fdb_to_vport_reg_c_id[0x8]; 848 u8 reserved_at_8[0xd]; 849 u8 fdb_modify_header_fwd_to_table[0x1]; 850 u8 fdb_ipv4_ttl_modify[0x1]; 851 u8 flow_source[0x1]; 852 u8 reserved_at_18[0x2]; 853 u8 multi_fdb_encap[0x1]; 854 u8 egress_acl_forward_to_vport[0x1]; 855 u8 fdb_multi_path_to_table[0x1]; 856 u8 reserved_at_1d[0x3]; 857 858 u8 reserved_at_20[0x1e0]; 859 860 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 861 862 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 863 864 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 865 866 u8 reserved_at_800[0x1000]; 867 868 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 869 870 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 871 872 u8 sw_steering_uplink_icm_address_rx[0x40]; 873 874 u8 sw_steering_uplink_icm_address_tx[0x40]; 875 876 u8 reserved_at_1900[0x6700]; 877 }; 878 879 enum { 880 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 881 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 882 }; 883 884 struct mlx5_ifc_e_switch_cap_bits { 885 u8 vport_svlan_strip[0x1]; 886 u8 vport_cvlan_strip[0x1]; 887 u8 vport_svlan_insert[0x1]; 888 u8 vport_cvlan_insert_if_not_exist[0x1]; 889 u8 vport_cvlan_insert_overwrite[0x1]; 890 u8 reserved_at_5[0x2]; 891 u8 esw_shared_ingress_acl[0x1]; 892 u8 esw_uplink_ingress_acl[0x1]; 893 u8 root_ft_on_other_esw[0x1]; 894 u8 reserved_at_a[0xf]; 895 u8 esw_functions_changed[0x1]; 896 u8 reserved_at_1a[0x1]; 897 u8 ecpf_vport_exists[0x1]; 898 u8 counter_eswitch_affinity[0x1]; 899 u8 merged_eswitch[0x1]; 900 u8 nic_vport_node_guid_modify[0x1]; 901 u8 nic_vport_port_guid_modify[0x1]; 902 903 u8 vxlan_encap_decap[0x1]; 904 u8 nvgre_encap_decap[0x1]; 905 u8 reserved_at_22[0x1]; 906 u8 log_max_fdb_encap_uplink[0x5]; 907 u8 reserved_at_21[0x3]; 908 u8 log_max_packet_reformat_context[0x5]; 909 u8 reserved_2b[0x6]; 910 u8 max_encap_header_size[0xa]; 911 912 u8 reserved_at_40[0xb]; 913 u8 log_max_esw_sf[0x5]; 914 u8 esw_sf_base_id[0x10]; 915 916 u8 reserved_at_60[0x7a0]; 917 918 }; 919 920 struct mlx5_ifc_qos_cap_bits { 921 u8 packet_pacing[0x1]; 922 u8 esw_scheduling[0x1]; 923 u8 esw_bw_share[0x1]; 924 u8 esw_rate_limit[0x1]; 925 u8 reserved_at_4[0x1]; 926 u8 packet_pacing_burst_bound[0x1]; 927 u8 packet_pacing_typical_size[0x1]; 928 u8 reserved_at_7[0x1]; 929 u8 nic_sq_scheduling[0x1]; 930 u8 nic_bw_share[0x1]; 931 u8 nic_rate_limit[0x1]; 932 u8 packet_pacing_uid[0x1]; 933 u8 log_esw_max_sched_depth[0x4]; 934 u8 reserved_at_10[0x10]; 935 936 u8 reserved_at_20[0xb]; 937 u8 log_max_qos_nic_queue_group[0x5]; 938 u8 reserved_at_30[0x10]; 939 940 u8 packet_pacing_max_rate[0x20]; 941 942 u8 packet_pacing_min_rate[0x20]; 943 944 u8 reserved_at_80[0x10]; 945 u8 packet_pacing_rate_table_size[0x10]; 946 947 u8 esw_element_type[0x10]; 948 u8 esw_tsar_type[0x10]; 949 950 u8 reserved_at_c0[0x10]; 951 u8 max_qos_para_vport[0x10]; 952 953 u8 max_tsar_bw_share[0x20]; 954 955 u8 reserved_at_100[0x20]; 956 957 u8 reserved_at_120[0x3]; 958 u8 log_meter_aso_granularity[0x5]; 959 u8 reserved_at_128[0x3]; 960 u8 log_meter_aso_max_alloc[0x5]; 961 u8 reserved_at_130[0x3]; 962 u8 log_max_num_meter_aso[0x5]; 963 u8 reserved_at_138[0x8]; 964 965 u8 reserved_at_140[0x6c0]; 966 }; 967 968 struct mlx5_ifc_debug_cap_bits { 969 u8 core_dump_general[0x1]; 970 u8 core_dump_qp[0x1]; 971 u8 reserved_at_2[0x7]; 972 u8 resource_dump[0x1]; 973 u8 reserved_at_a[0x16]; 974 975 u8 reserved_at_20[0x2]; 976 u8 stall_detect[0x1]; 977 u8 reserved_at_23[0x1d]; 978 979 u8 reserved_at_40[0x7c0]; 980 }; 981 982 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 983 u8 csum_cap[0x1]; 984 u8 vlan_cap[0x1]; 985 u8 lro_cap[0x1]; 986 u8 lro_psh_flag[0x1]; 987 u8 lro_time_stamp[0x1]; 988 u8 reserved_at_5[0x2]; 989 u8 wqe_vlan_insert[0x1]; 990 u8 self_lb_en_modifiable[0x1]; 991 u8 reserved_at_9[0x2]; 992 u8 max_lso_cap[0x5]; 993 u8 multi_pkt_send_wqe[0x2]; 994 u8 wqe_inline_mode[0x2]; 995 u8 rss_ind_tbl_cap[0x4]; 996 u8 reg_umr_sq[0x1]; 997 u8 scatter_fcs[0x1]; 998 u8 enhanced_multi_pkt_send_wqe[0x1]; 999 u8 tunnel_lso_const_out_ip_id[0x1]; 1000 u8 tunnel_lro_gre[0x1]; 1001 u8 tunnel_lro_vxlan[0x1]; 1002 u8 tunnel_stateless_gre[0x1]; 1003 u8 tunnel_stateless_vxlan[0x1]; 1004 1005 u8 swp[0x1]; 1006 u8 swp_csum[0x1]; 1007 u8 swp_lso[0x1]; 1008 u8 cqe_checksum_full[0x1]; 1009 u8 tunnel_stateless_geneve_tx[0x1]; 1010 u8 tunnel_stateless_mpls_over_udp[0x1]; 1011 u8 tunnel_stateless_mpls_over_gre[0x1]; 1012 u8 tunnel_stateless_vxlan_gpe[0x1]; 1013 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1014 u8 tunnel_stateless_ip_over_ip[0x1]; 1015 u8 insert_trailer[0x1]; 1016 u8 reserved_at_2b[0x1]; 1017 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1018 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1019 u8 reserved_at_2e[0x2]; 1020 u8 max_vxlan_udp_ports[0x8]; 1021 u8 reserved_at_38[0x6]; 1022 u8 max_geneve_opt_len[0x1]; 1023 u8 tunnel_stateless_geneve_rx[0x1]; 1024 1025 u8 reserved_at_40[0x10]; 1026 u8 lro_min_mss_size[0x10]; 1027 1028 u8 reserved_at_60[0x120]; 1029 1030 u8 lro_timer_supported_periods[4][0x20]; 1031 1032 u8 reserved_at_200[0x600]; 1033 }; 1034 1035 enum { 1036 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1037 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1038 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1039 }; 1040 1041 struct mlx5_ifc_roce_cap_bits { 1042 u8 roce_apm[0x1]; 1043 u8 reserved_at_1[0x3]; 1044 u8 sw_r_roce_src_udp_port[0x1]; 1045 u8 fl_rc_qp_when_roce_disabled[0x1]; 1046 u8 fl_rc_qp_when_roce_enabled[0x1]; 1047 u8 reserved_at_7[0x17]; 1048 u8 qp_ts_format[0x2]; 1049 1050 u8 reserved_at_20[0x60]; 1051 1052 u8 reserved_at_80[0xc]; 1053 u8 l3_type[0x4]; 1054 u8 reserved_at_90[0x8]; 1055 u8 roce_version[0x8]; 1056 1057 u8 reserved_at_a0[0x10]; 1058 u8 r_roce_dest_udp_port[0x10]; 1059 1060 u8 r_roce_max_src_udp_port[0x10]; 1061 u8 r_roce_min_src_udp_port[0x10]; 1062 1063 u8 reserved_at_e0[0x10]; 1064 u8 roce_address_table_size[0x10]; 1065 1066 u8 reserved_at_100[0x700]; 1067 }; 1068 1069 struct mlx5_ifc_sync_steering_in_bits { 1070 u8 opcode[0x10]; 1071 u8 uid[0x10]; 1072 1073 u8 reserved_at_20[0x10]; 1074 u8 op_mod[0x10]; 1075 1076 u8 reserved_at_40[0xc0]; 1077 }; 1078 1079 struct mlx5_ifc_sync_steering_out_bits { 1080 u8 status[0x8]; 1081 u8 reserved_at_8[0x18]; 1082 1083 u8 syndrome[0x20]; 1084 1085 u8 reserved_at_40[0x40]; 1086 }; 1087 1088 struct mlx5_ifc_device_mem_cap_bits { 1089 u8 memic[0x1]; 1090 u8 reserved_at_1[0x1f]; 1091 1092 u8 reserved_at_20[0xb]; 1093 u8 log_min_memic_alloc_size[0x5]; 1094 u8 reserved_at_30[0x8]; 1095 u8 log_max_memic_addr_alignment[0x8]; 1096 1097 u8 memic_bar_start_addr[0x40]; 1098 1099 u8 memic_bar_size[0x20]; 1100 1101 u8 max_memic_size[0x20]; 1102 1103 u8 steering_sw_icm_start_address[0x40]; 1104 1105 u8 reserved_at_100[0x8]; 1106 u8 log_header_modify_sw_icm_size[0x8]; 1107 u8 reserved_at_110[0x2]; 1108 u8 log_sw_icm_alloc_granularity[0x6]; 1109 u8 log_steering_sw_icm_size[0x8]; 1110 1111 u8 reserved_at_120[0x18]; 1112 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1113 1114 u8 header_modify_sw_icm_start_address[0x40]; 1115 1116 u8 reserved_at_180[0x40]; 1117 1118 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1119 1120 u8 memic_operations[0x20]; 1121 1122 u8 reserved_at_220[0x5e0]; 1123 }; 1124 1125 struct mlx5_ifc_device_event_cap_bits { 1126 u8 user_affiliated_events[4][0x40]; 1127 1128 u8 user_unaffiliated_events[4][0x40]; 1129 }; 1130 1131 struct mlx5_ifc_virtio_emulation_cap_bits { 1132 u8 desc_tunnel_offload_type[0x1]; 1133 u8 eth_frame_offload_type[0x1]; 1134 u8 virtio_version_1_0[0x1]; 1135 u8 device_features_bits_mask[0xd]; 1136 u8 event_mode[0x8]; 1137 u8 virtio_queue_type[0x8]; 1138 1139 u8 max_tunnel_desc[0x10]; 1140 u8 reserved_at_30[0x3]; 1141 u8 log_doorbell_stride[0x5]; 1142 u8 reserved_at_38[0x3]; 1143 u8 log_doorbell_bar_size[0x5]; 1144 1145 u8 doorbell_bar_offset[0x40]; 1146 1147 u8 max_emulated_devices[0x8]; 1148 u8 max_num_virtio_queues[0x18]; 1149 1150 u8 reserved_at_a0[0x60]; 1151 1152 u8 umem_1_buffer_param_a[0x20]; 1153 1154 u8 umem_1_buffer_param_b[0x20]; 1155 1156 u8 umem_2_buffer_param_a[0x20]; 1157 1158 u8 umem_2_buffer_param_b[0x20]; 1159 1160 u8 umem_3_buffer_param_a[0x20]; 1161 1162 u8 umem_3_buffer_param_b[0x20]; 1163 1164 u8 reserved_at_1c0[0x640]; 1165 }; 1166 1167 enum { 1168 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1169 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1170 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1171 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1172 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1173 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1174 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1175 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1176 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1177 }; 1178 1179 enum { 1180 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1181 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1182 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1183 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1184 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1185 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1186 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1187 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1188 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1189 }; 1190 1191 struct mlx5_ifc_atomic_caps_bits { 1192 u8 reserved_at_0[0x40]; 1193 1194 u8 atomic_req_8B_endianness_mode[0x2]; 1195 u8 reserved_at_42[0x4]; 1196 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1197 1198 u8 reserved_at_47[0x19]; 1199 1200 u8 reserved_at_60[0x20]; 1201 1202 u8 reserved_at_80[0x10]; 1203 u8 atomic_operations[0x10]; 1204 1205 u8 reserved_at_a0[0x10]; 1206 u8 atomic_size_qp[0x10]; 1207 1208 u8 reserved_at_c0[0x10]; 1209 u8 atomic_size_dc[0x10]; 1210 1211 u8 reserved_at_e0[0x720]; 1212 }; 1213 1214 struct mlx5_ifc_odp_cap_bits { 1215 u8 reserved_at_0[0x40]; 1216 1217 u8 sig[0x1]; 1218 u8 reserved_at_41[0x1f]; 1219 1220 u8 reserved_at_60[0x20]; 1221 1222 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1223 1224 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1225 1226 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1227 1228 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1229 1230 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1231 1232 u8 reserved_at_120[0x6E0]; 1233 }; 1234 1235 struct mlx5_ifc_calc_op { 1236 u8 reserved_at_0[0x10]; 1237 u8 reserved_at_10[0x9]; 1238 u8 op_swap_endianness[0x1]; 1239 u8 op_min[0x1]; 1240 u8 op_xor[0x1]; 1241 u8 op_or[0x1]; 1242 u8 op_and[0x1]; 1243 u8 op_max[0x1]; 1244 u8 op_add[0x1]; 1245 }; 1246 1247 struct mlx5_ifc_vector_calc_cap_bits { 1248 u8 calc_matrix[0x1]; 1249 u8 reserved_at_1[0x1f]; 1250 u8 reserved_at_20[0x8]; 1251 u8 max_vec_count[0x8]; 1252 u8 reserved_at_30[0xd]; 1253 u8 max_chunk_size[0x3]; 1254 struct mlx5_ifc_calc_op calc0; 1255 struct mlx5_ifc_calc_op calc1; 1256 struct mlx5_ifc_calc_op calc2; 1257 struct mlx5_ifc_calc_op calc3; 1258 1259 u8 reserved_at_c0[0x720]; 1260 }; 1261 1262 struct mlx5_ifc_tls_cap_bits { 1263 u8 tls_1_2_aes_gcm_128[0x1]; 1264 u8 tls_1_3_aes_gcm_128[0x1]; 1265 u8 tls_1_2_aes_gcm_256[0x1]; 1266 u8 tls_1_3_aes_gcm_256[0x1]; 1267 u8 reserved_at_4[0x1c]; 1268 1269 u8 reserved_at_20[0x7e0]; 1270 }; 1271 1272 struct mlx5_ifc_ipsec_cap_bits { 1273 u8 ipsec_full_offload[0x1]; 1274 u8 ipsec_crypto_offload[0x1]; 1275 u8 ipsec_esn[0x1]; 1276 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1277 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1278 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1279 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1280 u8 reserved_at_7[0x4]; 1281 u8 log_max_ipsec_offload[0x5]; 1282 u8 reserved_at_10[0x10]; 1283 1284 u8 min_log_ipsec_full_replay_window[0x8]; 1285 u8 max_log_ipsec_full_replay_window[0x8]; 1286 u8 reserved_at_30[0x7d0]; 1287 }; 1288 1289 struct mlx5_ifc_macsec_cap_bits { 1290 u8 macsec_epn[0x1]; 1291 u8 reserved_at_1[0x2]; 1292 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1293 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1294 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1295 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1296 u8 reserved_at_7[0x4]; 1297 u8 log_max_macsec_offload[0x5]; 1298 u8 reserved_at_10[0x10]; 1299 1300 u8 min_log_macsec_full_replay_window[0x8]; 1301 u8 max_log_macsec_full_replay_window[0x8]; 1302 u8 reserved_at_30[0x10]; 1303 1304 u8 reserved_at_40[0x7c0]; 1305 }; 1306 1307 enum { 1308 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1309 MLX5_WQ_TYPE_CYCLIC = 0x1, 1310 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1311 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1312 }; 1313 1314 enum { 1315 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1316 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1317 }; 1318 1319 enum { 1320 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1321 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1322 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1323 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1324 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1325 }; 1326 1327 enum { 1328 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1329 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1330 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1331 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1332 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1333 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1334 }; 1335 1336 enum { 1337 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1338 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1339 }; 1340 1341 enum { 1342 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1343 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1344 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1345 }; 1346 1347 enum { 1348 MLX5_CAP_PORT_TYPE_IB = 0x0, 1349 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1350 }; 1351 1352 enum { 1353 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1354 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1355 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1356 }; 1357 1358 enum { 1359 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1360 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1361 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1362 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1363 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1364 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1365 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1366 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1367 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1368 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1369 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1370 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1371 }; 1372 1373 enum { 1374 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1375 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1376 }; 1377 1378 #define MLX5_FC_BULK_SIZE_FACTOR 128 1379 1380 enum mlx5_fc_bulk_alloc_bitmask { 1381 MLX5_FC_BULK_128 = (1 << 0), 1382 MLX5_FC_BULK_256 = (1 << 1), 1383 MLX5_FC_BULK_512 = (1 << 2), 1384 MLX5_FC_BULK_1024 = (1 << 3), 1385 MLX5_FC_BULK_2048 = (1 << 4), 1386 MLX5_FC_BULK_4096 = (1 << 5), 1387 MLX5_FC_BULK_8192 = (1 << 6), 1388 MLX5_FC_BULK_16384 = (1 << 7), 1389 }; 1390 1391 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1392 1393 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1394 1395 enum { 1396 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1397 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1398 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1399 }; 1400 1401 struct mlx5_ifc_cmd_hca_cap_bits { 1402 u8 reserved_at_0[0x10]; 1403 u8 shared_object_to_user_object_allowed[0x1]; 1404 u8 reserved_at_13[0xe]; 1405 u8 vhca_resource_manager[0x1]; 1406 1407 u8 hca_cap_2[0x1]; 1408 u8 create_lag_when_not_master_up[0x1]; 1409 u8 dtor[0x1]; 1410 u8 event_on_vhca_state_teardown_request[0x1]; 1411 u8 event_on_vhca_state_in_use[0x1]; 1412 u8 event_on_vhca_state_active[0x1]; 1413 u8 event_on_vhca_state_allocated[0x1]; 1414 u8 event_on_vhca_state_invalid[0x1]; 1415 u8 reserved_at_28[0x8]; 1416 u8 vhca_id[0x10]; 1417 1418 u8 reserved_at_40[0x40]; 1419 1420 u8 log_max_srq_sz[0x8]; 1421 u8 log_max_qp_sz[0x8]; 1422 u8 event_cap[0x1]; 1423 u8 reserved_at_91[0x2]; 1424 u8 isolate_vl_tc_new[0x1]; 1425 u8 reserved_at_94[0x4]; 1426 u8 prio_tag_required[0x1]; 1427 u8 reserved_at_99[0x2]; 1428 u8 log_max_qp[0x5]; 1429 1430 u8 reserved_at_a0[0x3]; 1431 u8 ece_support[0x1]; 1432 u8 reserved_at_a4[0x5]; 1433 u8 reg_c_preserve[0x1]; 1434 u8 reserved_at_aa[0x1]; 1435 u8 log_max_srq[0x5]; 1436 u8 reserved_at_b0[0x1]; 1437 u8 uplink_follow[0x1]; 1438 u8 ts_cqe_to_dest_cqn[0x1]; 1439 u8 reserved_at_b3[0x7]; 1440 u8 shampo[0x1]; 1441 u8 reserved_at_bb[0x5]; 1442 1443 u8 max_sgl_for_optimized_performance[0x8]; 1444 u8 log_max_cq_sz[0x8]; 1445 u8 relaxed_ordering_write_umr[0x1]; 1446 u8 relaxed_ordering_read_umr[0x1]; 1447 u8 reserved_at_d2[0x7]; 1448 u8 virtio_net_device_emualtion_manager[0x1]; 1449 u8 virtio_blk_device_emualtion_manager[0x1]; 1450 u8 log_max_cq[0x5]; 1451 1452 u8 log_max_eq_sz[0x8]; 1453 u8 relaxed_ordering_write[0x1]; 1454 u8 relaxed_ordering_read[0x1]; 1455 u8 log_max_mkey[0x6]; 1456 u8 reserved_at_f0[0x8]; 1457 u8 dump_fill_mkey[0x1]; 1458 u8 reserved_at_f9[0x2]; 1459 u8 fast_teardown[0x1]; 1460 u8 log_max_eq[0x4]; 1461 1462 u8 max_indirection[0x8]; 1463 u8 fixed_buffer_size[0x1]; 1464 u8 log_max_mrw_sz[0x7]; 1465 u8 force_teardown[0x1]; 1466 u8 reserved_at_111[0x1]; 1467 u8 log_max_bsf_list_size[0x6]; 1468 u8 umr_extended_translation_offset[0x1]; 1469 u8 null_mkey[0x1]; 1470 u8 log_max_klm_list_size[0x6]; 1471 1472 u8 reserved_at_120[0xa]; 1473 u8 log_max_ra_req_dc[0x6]; 1474 u8 reserved_at_130[0x9]; 1475 u8 vnic_env_cq_overrun[0x1]; 1476 u8 log_max_ra_res_dc[0x6]; 1477 1478 u8 reserved_at_140[0x5]; 1479 u8 release_all_pages[0x1]; 1480 u8 must_not_use[0x1]; 1481 u8 reserved_at_147[0x2]; 1482 u8 roce_accl[0x1]; 1483 u8 log_max_ra_req_qp[0x6]; 1484 u8 reserved_at_150[0xa]; 1485 u8 log_max_ra_res_qp[0x6]; 1486 1487 u8 end_pad[0x1]; 1488 u8 cc_query_allowed[0x1]; 1489 u8 cc_modify_allowed[0x1]; 1490 u8 start_pad[0x1]; 1491 u8 cache_line_128byte[0x1]; 1492 u8 reserved_at_165[0x4]; 1493 u8 rts2rts_qp_counters_set_id[0x1]; 1494 u8 reserved_at_16a[0x2]; 1495 u8 vnic_env_int_rq_oob[0x1]; 1496 u8 sbcam_reg[0x1]; 1497 u8 reserved_at_16e[0x1]; 1498 u8 qcam_reg[0x1]; 1499 u8 gid_table_size[0x10]; 1500 1501 u8 out_of_seq_cnt[0x1]; 1502 u8 vport_counters[0x1]; 1503 u8 retransmission_q_counters[0x1]; 1504 u8 debug[0x1]; 1505 u8 modify_rq_counter_set_id[0x1]; 1506 u8 rq_delay_drop[0x1]; 1507 u8 max_qp_cnt[0xa]; 1508 u8 pkey_table_size[0x10]; 1509 1510 u8 vport_group_manager[0x1]; 1511 u8 vhca_group_manager[0x1]; 1512 u8 ib_virt[0x1]; 1513 u8 eth_virt[0x1]; 1514 u8 vnic_env_queue_counters[0x1]; 1515 u8 ets[0x1]; 1516 u8 nic_flow_table[0x1]; 1517 u8 eswitch_manager[0x1]; 1518 u8 device_memory[0x1]; 1519 u8 mcam_reg[0x1]; 1520 u8 pcam_reg[0x1]; 1521 u8 local_ca_ack_delay[0x5]; 1522 u8 port_module_event[0x1]; 1523 u8 enhanced_error_q_counters[0x1]; 1524 u8 ports_check[0x1]; 1525 u8 reserved_at_1b3[0x1]; 1526 u8 disable_link_up[0x1]; 1527 u8 beacon_led[0x1]; 1528 u8 port_type[0x2]; 1529 u8 num_ports[0x8]; 1530 1531 u8 reserved_at_1c0[0x1]; 1532 u8 pps[0x1]; 1533 u8 pps_modify[0x1]; 1534 u8 log_max_msg[0x5]; 1535 u8 reserved_at_1c8[0x4]; 1536 u8 max_tc[0x4]; 1537 u8 temp_warn_event[0x1]; 1538 u8 dcbx[0x1]; 1539 u8 general_notification_event[0x1]; 1540 u8 reserved_at_1d3[0x2]; 1541 u8 fpga[0x1]; 1542 u8 rol_s[0x1]; 1543 u8 rol_g[0x1]; 1544 u8 reserved_at_1d8[0x1]; 1545 u8 wol_s[0x1]; 1546 u8 wol_g[0x1]; 1547 u8 wol_a[0x1]; 1548 u8 wol_b[0x1]; 1549 u8 wol_m[0x1]; 1550 u8 wol_u[0x1]; 1551 u8 wol_p[0x1]; 1552 1553 u8 stat_rate_support[0x10]; 1554 u8 reserved_at_1f0[0x1]; 1555 u8 pci_sync_for_fw_update_event[0x1]; 1556 u8 reserved_at_1f2[0x6]; 1557 u8 init2_lag_tx_port_affinity[0x1]; 1558 u8 reserved_at_1fa[0x3]; 1559 u8 cqe_version[0x4]; 1560 1561 u8 compact_address_vector[0x1]; 1562 u8 striding_rq[0x1]; 1563 u8 reserved_at_202[0x1]; 1564 u8 ipoib_enhanced_offloads[0x1]; 1565 u8 ipoib_basic_offloads[0x1]; 1566 u8 reserved_at_205[0x1]; 1567 u8 repeated_block_disabled[0x1]; 1568 u8 umr_modify_entity_size_disabled[0x1]; 1569 u8 umr_modify_atomic_disabled[0x1]; 1570 u8 umr_indirect_mkey_disabled[0x1]; 1571 u8 umr_fence[0x2]; 1572 u8 dc_req_scat_data_cqe[0x1]; 1573 u8 reserved_at_20d[0x2]; 1574 u8 drain_sigerr[0x1]; 1575 u8 cmdif_checksum[0x2]; 1576 u8 sigerr_cqe[0x1]; 1577 u8 reserved_at_213[0x1]; 1578 u8 wq_signature[0x1]; 1579 u8 sctr_data_cqe[0x1]; 1580 u8 reserved_at_216[0x1]; 1581 u8 sho[0x1]; 1582 u8 tph[0x1]; 1583 u8 rf[0x1]; 1584 u8 dct[0x1]; 1585 u8 qos[0x1]; 1586 u8 eth_net_offloads[0x1]; 1587 u8 roce[0x1]; 1588 u8 atomic[0x1]; 1589 u8 reserved_at_21f[0x1]; 1590 1591 u8 cq_oi[0x1]; 1592 u8 cq_resize[0x1]; 1593 u8 cq_moderation[0x1]; 1594 u8 reserved_at_223[0x3]; 1595 u8 cq_eq_remap[0x1]; 1596 u8 pg[0x1]; 1597 u8 block_lb_mc[0x1]; 1598 u8 reserved_at_229[0x1]; 1599 u8 scqe_break_moderation[0x1]; 1600 u8 cq_period_start_from_cqe[0x1]; 1601 u8 cd[0x1]; 1602 u8 reserved_at_22d[0x1]; 1603 u8 apm[0x1]; 1604 u8 vector_calc[0x1]; 1605 u8 umr_ptr_rlky[0x1]; 1606 u8 imaicl[0x1]; 1607 u8 qp_packet_based[0x1]; 1608 u8 reserved_at_233[0x3]; 1609 u8 qkv[0x1]; 1610 u8 pkv[0x1]; 1611 u8 set_deth_sqpn[0x1]; 1612 u8 reserved_at_239[0x3]; 1613 u8 xrc[0x1]; 1614 u8 ud[0x1]; 1615 u8 uc[0x1]; 1616 u8 rc[0x1]; 1617 1618 u8 uar_4k[0x1]; 1619 u8 reserved_at_241[0x9]; 1620 u8 uar_sz[0x6]; 1621 u8 port_selection_cap[0x1]; 1622 u8 reserved_at_248[0x1]; 1623 u8 umem_uid_0[0x1]; 1624 u8 reserved_at_250[0x5]; 1625 u8 log_pg_sz[0x8]; 1626 1627 u8 bf[0x1]; 1628 u8 driver_version[0x1]; 1629 u8 pad_tx_eth_packet[0x1]; 1630 u8 reserved_at_263[0x3]; 1631 u8 mkey_by_name[0x1]; 1632 u8 reserved_at_267[0x4]; 1633 1634 u8 log_bf_reg_size[0x5]; 1635 1636 u8 reserved_at_270[0x6]; 1637 u8 lag_dct[0x2]; 1638 u8 lag_tx_port_affinity[0x1]; 1639 u8 lag_native_fdb_selection[0x1]; 1640 u8 reserved_at_27a[0x1]; 1641 u8 lag_master[0x1]; 1642 u8 num_lag_ports[0x4]; 1643 1644 u8 reserved_at_280[0x10]; 1645 u8 max_wqe_sz_sq[0x10]; 1646 1647 u8 reserved_at_2a0[0x10]; 1648 u8 max_wqe_sz_rq[0x10]; 1649 1650 u8 max_flow_counter_31_16[0x10]; 1651 u8 max_wqe_sz_sq_dc[0x10]; 1652 1653 u8 reserved_at_2e0[0x7]; 1654 u8 max_qp_mcg[0x19]; 1655 1656 u8 reserved_at_300[0x10]; 1657 u8 flow_counter_bulk_alloc[0x8]; 1658 u8 log_max_mcg[0x8]; 1659 1660 u8 reserved_at_320[0x3]; 1661 u8 log_max_transport_domain[0x5]; 1662 u8 reserved_at_328[0x3]; 1663 u8 log_max_pd[0x5]; 1664 u8 reserved_at_330[0xb]; 1665 u8 log_max_xrcd[0x5]; 1666 1667 u8 nic_receive_steering_discard[0x1]; 1668 u8 receive_discard_vport_down[0x1]; 1669 u8 transmit_discard_vport_down[0x1]; 1670 u8 eq_overrun_count[0x1]; 1671 u8 reserved_at_344[0x1]; 1672 u8 invalid_command_count[0x1]; 1673 u8 quota_exceeded_count[0x1]; 1674 u8 reserved_at_347[0x1]; 1675 u8 log_max_flow_counter_bulk[0x8]; 1676 u8 max_flow_counter_15_0[0x10]; 1677 1678 1679 u8 reserved_at_360[0x3]; 1680 u8 log_max_rq[0x5]; 1681 u8 reserved_at_368[0x3]; 1682 u8 log_max_sq[0x5]; 1683 u8 reserved_at_370[0x3]; 1684 u8 log_max_tir[0x5]; 1685 u8 reserved_at_378[0x3]; 1686 u8 log_max_tis[0x5]; 1687 1688 u8 basic_cyclic_rcv_wqe[0x1]; 1689 u8 reserved_at_381[0x2]; 1690 u8 log_max_rmp[0x5]; 1691 u8 reserved_at_388[0x3]; 1692 u8 log_max_rqt[0x5]; 1693 u8 reserved_at_390[0x3]; 1694 u8 log_max_rqt_size[0x5]; 1695 u8 reserved_at_398[0x3]; 1696 u8 log_max_tis_per_sq[0x5]; 1697 1698 u8 ext_stride_num_range[0x1]; 1699 u8 roce_rw_supported[0x1]; 1700 u8 log_max_current_uc_list_wr_supported[0x1]; 1701 u8 log_max_stride_sz_rq[0x5]; 1702 u8 reserved_at_3a8[0x3]; 1703 u8 log_min_stride_sz_rq[0x5]; 1704 u8 reserved_at_3b0[0x3]; 1705 u8 log_max_stride_sz_sq[0x5]; 1706 u8 reserved_at_3b8[0x3]; 1707 u8 log_min_stride_sz_sq[0x5]; 1708 1709 u8 hairpin[0x1]; 1710 u8 reserved_at_3c1[0x2]; 1711 u8 log_max_hairpin_queues[0x5]; 1712 u8 reserved_at_3c8[0x3]; 1713 u8 log_max_hairpin_wq_data_sz[0x5]; 1714 u8 reserved_at_3d0[0x3]; 1715 u8 log_max_hairpin_num_packets[0x5]; 1716 u8 reserved_at_3d8[0x3]; 1717 u8 log_max_wq_sz[0x5]; 1718 1719 u8 nic_vport_change_event[0x1]; 1720 u8 disable_local_lb_uc[0x1]; 1721 u8 disable_local_lb_mc[0x1]; 1722 u8 log_min_hairpin_wq_data_sz[0x5]; 1723 u8 reserved_at_3e8[0x2]; 1724 u8 vhca_state[0x1]; 1725 u8 log_max_vlan_list[0x5]; 1726 u8 reserved_at_3f0[0x3]; 1727 u8 log_max_current_mc_list[0x5]; 1728 u8 reserved_at_3f8[0x3]; 1729 u8 log_max_current_uc_list[0x5]; 1730 1731 u8 general_obj_types[0x40]; 1732 1733 u8 sq_ts_format[0x2]; 1734 u8 rq_ts_format[0x2]; 1735 u8 steering_format_version[0x4]; 1736 u8 create_qp_start_hint[0x18]; 1737 1738 u8 reserved_at_460[0x3]; 1739 u8 log_max_uctx[0x5]; 1740 u8 reserved_at_468[0x2]; 1741 u8 ipsec_offload[0x1]; 1742 u8 log_max_umem[0x5]; 1743 u8 max_num_eqs[0x10]; 1744 1745 u8 reserved_at_480[0x1]; 1746 u8 tls_tx[0x1]; 1747 u8 tls_rx[0x1]; 1748 u8 log_max_l2_table[0x5]; 1749 u8 reserved_at_488[0x8]; 1750 u8 log_uar_page_sz[0x10]; 1751 1752 u8 reserved_at_4a0[0x20]; 1753 u8 device_frequency_mhz[0x20]; 1754 u8 device_frequency_khz[0x20]; 1755 1756 u8 reserved_at_500[0x20]; 1757 u8 num_of_uars_per_page[0x20]; 1758 1759 u8 flex_parser_protocols[0x20]; 1760 1761 u8 max_geneve_tlv_options[0x8]; 1762 u8 reserved_at_568[0x3]; 1763 u8 max_geneve_tlv_option_data_len[0x5]; 1764 u8 reserved_at_570[0x10]; 1765 1766 u8 reserved_at_580[0xb]; 1767 u8 log_max_dci_stream_channels[0x5]; 1768 u8 reserved_at_590[0x3]; 1769 u8 log_max_dci_errored_streams[0x5]; 1770 u8 reserved_at_598[0x8]; 1771 1772 u8 reserved_at_5a0[0x10]; 1773 u8 enhanced_cqe_compression[0x1]; 1774 u8 reserved_at_5b1[0x2]; 1775 u8 log_max_dek[0x5]; 1776 u8 reserved_at_5b8[0x4]; 1777 u8 mini_cqe_resp_stride_index[0x1]; 1778 u8 cqe_128_always[0x1]; 1779 u8 cqe_compression_128[0x1]; 1780 u8 cqe_compression[0x1]; 1781 1782 u8 cqe_compression_timeout[0x10]; 1783 u8 cqe_compression_max_num[0x10]; 1784 1785 u8 reserved_at_5e0[0x8]; 1786 u8 flex_parser_id_gtpu_dw_0[0x4]; 1787 u8 reserved_at_5ec[0x4]; 1788 u8 tag_matching[0x1]; 1789 u8 rndv_offload_rc[0x1]; 1790 u8 rndv_offload_dc[0x1]; 1791 u8 log_tag_matching_list_sz[0x5]; 1792 u8 reserved_at_5f8[0x3]; 1793 u8 log_max_xrq[0x5]; 1794 1795 u8 affiliate_nic_vport_criteria[0x8]; 1796 u8 native_port_num[0x8]; 1797 u8 num_vhca_ports[0x8]; 1798 u8 flex_parser_id_gtpu_teid[0x4]; 1799 u8 reserved_at_61c[0x2]; 1800 u8 sw_owner_id[0x1]; 1801 u8 reserved_at_61f[0x1]; 1802 1803 u8 max_num_of_monitor_counters[0x10]; 1804 u8 num_ppcnt_monitor_counters[0x10]; 1805 1806 u8 max_num_sf[0x10]; 1807 u8 num_q_monitor_counters[0x10]; 1808 1809 u8 reserved_at_660[0x20]; 1810 1811 u8 sf[0x1]; 1812 u8 sf_set_partition[0x1]; 1813 u8 reserved_at_682[0x1]; 1814 u8 log_max_sf[0x5]; 1815 u8 apu[0x1]; 1816 u8 reserved_at_689[0x4]; 1817 u8 migration[0x1]; 1818 u8 reserved_at_68e[0x2]; 1819 u8 log_min_sf_size[0x8]; 1820 u8 max_num_sf_partitions[0x8]; 1821 1822 u8 uctx_cap[0x20]; 1823 1824 u8 reserved_at_6c0[0x4]; 1825 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1826 u8 flex_parser_id_icmp_dw1[0x4]; 1827 u8 flex_parser_id_icmp_dw0[0x4]; 1828 u8 flex_parser_id_icmpv6_dw1[0x4]; 1829 u8 flex_parser_id_icmpv6_dw0[0x4]; 1830 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1831 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1832 1833 u8 max_num_match_definer[0x10]; 1834 u8 sf_base_id[0x10]; 1835 1836 u8 flex_parser_id_gtpu_dw_2[0x4]; 1837 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1838 u8 num_total_dynamic_vf_msix[0x18]; 1839 u8 reserved_at_720[0x14]; 1840 u8 dynamic_msix_table_size[0xc]; 1841 u8 reserved_at_740[0xc]; 1842 u8 min_dynamic_vf_msix_table_size[0x4]; 1843 u8 reserved_at_750[0x4]; 1844 u8 max_dynamic_vf_msix_table_size[0xc]; 1845 1846 u8 reserved_at_760[0x20]; 1847 u8 vhca_tunnel_commands[0x40]; 1848 u8 match_definer_format_supported[0x40]; 1849 }; 1850 1851 struct mlx5_ifc_cmd_hca_cap_2_bits { 1852 u8 reserved_at_0[0xa0]; 1853 1854 u8 max_reformat_insert_size[0x8]; 1855 u8 max_reformat_insert_offset[0x8]; 1856 u8 max_reformat_remove_size[0x8]; 1857 u8 max_reformat_remove_offset[0x8]; 1858 1859 u8 reserved_at_c0[0x160]; 1860 1861 u8 reserved_at_220[0x1]; 1862 u8 sw_vhca_id_valid[0x1]; 1863 u8 sw_vhca_id[0xe]; 1864 u8 reserved_at_230[0x10]; 1865 1866 u8 reserved_at_240[0xb]; 1867 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1868 u8 reserved_at_250[0x10]; 1869 1870 u8 reserved_at_260[0x5a0]; 1871 }; 1872 1873 enum mlx5_ifc_flow_destination_type { 1874 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1875 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1876 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1877 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1878 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1879 }; 1880 1881 enum mlx5_flow_table_miss_action { 1882 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1883 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1884 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1885 }; 1886 1887 struct mlx5_ifc_dest_format_struct_bits { 1888 u8 destination_type[0x8]; 1889 u8 destination_id[0x18]; 1890 1891 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1892 u8 packet_reformat[0x1]; 1893 u8 reserved_at_22[0xe]; 1894 u8 destination_eswitch_owner_vhca_id[0x10]; 1895 }; 1896 1897 struct mlx5_ifc_flow_counter_list_bits { 1898 u8 flow_counter_id[0x20]; 1899 1900 u8 reserved_at_20[0x20]; 1901 }; 1902 1903 struct mlx5_ifc_extended_dest_format_bits { 1904 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1905 1906 u8 packet_reformat_id[0x20]; 1907 1908 u8 reserved_at_60[0x20]; 1909 }; 1910 1911 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1912 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1913 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1914 }; 1915 1916 struct mlx5_ifc_fte_match_param_bits { 1917 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1918 1919 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1920 1921 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1922 1923 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1924 1925 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1926 1927 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1928 1929 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1930 1931 u8 reserved_at_e00[0x200]; 1932 }; 1933 1934 enum { 1935 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1936 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1937 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1938 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1939 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1940 }; 1941 1942 struct mlx5_ifc_rx_hash_field_select_bits { 1943 u8 l3_prot_type[0x1]; 1944 u8 l4_prot_type[0x1]; 1945 u8 selected_fields[0x1e]; 1946 }; 1947 1948 enum { 1949 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1950 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1951 }; 1952 1953 enum { 1954 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1955 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1956 }; 1957 1958 struct mlx5_ifc_wq_bits { 1959 u8 wq_type[0x4]; 1960 u8 wq_signature[0x1]; 1961 u8 end_padding_mode[0x2]; 1962 u8 cd_slave[0x1]; 1963 u8 reserved_at_8[0x18]; 1964 1965 u8 hds_skip_first_sge[0x1]; 1966 u8 log2_hds_buf_size[0x3]; 1967 u8 reserved_at_24[0x7]; 1968 u8 page_offset[0x5]; 1969 u8 lwm[0x10]; 1970 1971 u8 reserved_at_40[0x8]; 1972 u8 pd[0x18]; 1973 1974 u8 reserved_at_60[0x8]; 1975 u8 uar_page[0x18]; 1976 1977 u8 dbr_addr[0x40]; 1978 1979 u8 hw_counter[0x20]; 1980 1981 u8 sw_counter[0x20]; 1982 1983 u8 reserved_at_100[0xc]; 1984 u8 log_wq_stride[0x4]; 1985 u8 reserved_at_110[0x3]; 1986 u8 log_wq_pg_sz[0x5]; 1987 u8 reserved_at_118[0x3]; 1988 u8 log_wq_sz[0x5]; 1989 1990 u8 dbr_umem_valid[0x1]; 1991 u8 wq_umem_valid[0x1]; 1992 u8 reserved_at_122[0x1]; 1993 u8 log_hairpin_num_packets[0x5]; 1994 u8 reserved_at_128[0x3]; 1995 u8 log_hairpin_data_sz[0x5]; 1996 1997 u8 reserved_at_130[0x4]; 1998 u8 log_wqe_num_of_strides[0x4]; 1999 u8 two_byte_shift_en[0x1]; 2000 u8 reserved_at_139[0x4]; 2001 u8 log_wqe_stride_size[0x3]; 2002 2003 u8 reserved_at_140[0x80]; 2004 2005 u8 headers_mkey[0x20]; 2006 2007 u8 shampo_enable[0x1]; 2008 u8 reserved_at_1e1[0x4]; 2009 u8 log_reservation_size[0x3]; 2010 u8 reserved_at_1e8[0x5]; 2011 u8 log_max_num_of_packets_per_reservation[0x3]; 2012 u8 reserved_at_1f0[0x6]; 2013 u8 log_headers_entry_size[0x2]; 2014 u8 reserved_at_1f8[0x4]; 2015 u8 log_headers_buffer_entry_num[0x4]; 2016 2017 u8 reserved_at_200[0x400]; 2018 2019 struct mlx5_ifc_cmd_pas_bits pas[]; 2020 }; 2021 2022 struct mlx5_ifc_rq_num_bits { 2023 u8 reserved_at_0[0x8]; 2024 u8 rq_num[0x18]; 2025 }; 2026 2027 struct mlx5_ifc_mac_address_layout_bits { 2028 u8 reserved_at_0[0x10]; 2029 u8 mac_addr_47_32[0x10]; 2030 2031 u8 mac_addr_31_0[0x20]; 2032 }; 2033 2034 struct mlx5_ifc_vlan_layout_bits { 2035 u8 reserved_at_0[0x14]; 2036 u8 vlan[0x0c]; 2037 2038 u8 reserved_at_20[0x20]; 2039 }; 2040 2041 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2042 u8 reserved_at_0[0xa0]; 2043 2044 u8 min_time_between_cnps[0x20]; 2045 2046 u8 reserved_at_c0[0x12]; 2047 u8 cnp_dscp[0x6]; 2048 u8 reserved_at_d8[0x4]; 2049 u8 cnp_prio_mode[0x1]; 2050 u8 cnp_802p_prio[0x3]; 2051 2052 u8 reserved_at_e0[0x720]; 2053 }; 2054 2055 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2056 u8 reserved_at_0[0x60]; 2057 2058 u8 reserved_at_60[0x4]; 2059 u8 clamp_tgt_rate[0x1]; 2060 u8 reserved_at_65[0x3]; 2061 u8 clamp_tgt_rate_after_time_inc[0x1]; 2062 u8 reserved_at_69[0x17]; 2063 2064 u8 reserved_at_80[0x20]; 2065 2066 u8 rpg_time_reset[0x20]; 2067 2068 u8 rpg_byte_reset[0x20]; 2069 2070 u8 rpg_threshold[0x20]; 2071 2072 u8 rpg_max_rate[0x20]; 2073 2074 u8 rpg_ai_rate[0x20]; 2075 2076 u8 rpg_hai_rate[0x20]; 2077 2078 u8 rpg_gd[0x20]; 2079 2080 u8 rpg_min_dec_fac[0x20]; 2081 2082 u8 rpg_min_rate[0x20]; 2083 2084 u8 reserved_at_1c0[0xe0]; 2085 2086 u8 rate_to_set_on_first_cnp[0x20]; 2087 2088 u8 dce_tcp_g[0x20]; 2089 2090 u8 dce_tcp_rtt[0x20]; 2091 2092 u8 rate_reduce_monitor_period[0x20]; 2093 2094 u8 reserved_at_320[0x20]; 2095 2096 u8 initial_alpha_value[0x20]; 2097 2098 u8 reserved_at_360[0x4a0]; 2099 }; 2100 2101 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2102 u8 reserved_at_0[0x80]; 2103 2104 u8 rppp_max_rps[0x20]; 2105 2106 u8 rpg_time_reset[0x20]; 2107 2108 u8 rpg_byte_reset[0x20]; 2109 2110 u8 rpg_threshold[0x20]; 2111 2112 u8 rpg_max_rate[0x20]; 2113 2114 u8 rpg_ai_rate[0x20]; 2115 2116 u8 rpg_hai_rate[0x20]; 2117 2118 u8 rpg_gd[0x20]; 2119 2120 u8 rpg_min_dec_fac[0x20]; 2121 2122 u8 rpg_min_rate[0x20]; 2123 2124 u8 reserved_at_1c0[0x640]; 2125 }; 2126 2127 enum { 2128 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2129 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2130 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2131 }; 2132 2133 struct mlx5_ifc_resize_field_select_bits { 2134 u8 resize_field_select[0x20]; 2135 }; 2136 2137 struct mlx5_ifc_resource_dump_bits { 2138 u8 more_dump[0x1]; 2139 u8 inline_dump[0x1]; 2140 u8 reserved_at_2[0xa]; 2141 u8 seq_num[0x4]; 2142 u8 segment_type[0x10]; 2143 2144 u8 reserved_at_20[0x10]; 2145 u8 vhca_id[0x10]; 2146 2147 u8 index1[0x20]; 2148 2149 u8 index2[0x20]; 2150 2151 u8 num_of_obj1[0x10]; 2152 u8 num_of_obj2[0x10]; 2153 2154 u8 reserved_at_a0[0x20]; 2155 2156 u8 device_opaque[0x40]; 2157 2158 u8 mkey[0x20]; 2159 2160 u8 size[0x20]; 2161 2162 u8 address[0x40]; 2163 2164 u8 inline_data[52][0x20]; 2165 }; 2166 2167 struct mlx5_ifc_resource_dump_menu_record_bits { 2168 u8 reserved_at_0[0x4]; 2169 u8 num_of_obj2_supports_active[0x1]; 2170 u8 num_of_obj2_supports_all[0x1]; 2171 u8 must_have_num_of_obj2[0x1]; 2172 u8 support_num_of_obj2[0x1]; 2173 u8 num_of_obj1_supports_active[0x1]; 2174 u8 num_of_obj1_supports_all[0x1]; 2175 u8 must_have_num_of_obj1[0x1]; 2176 u8 support_num_of_obj1[0x1]; 2177 u8 must_have_index2[0x1]; 2178 u8 support_index2[0x1]; 2179 u8 must_have_index1[0x1]; 2180 u8 support_index1[0x1]; 2181 u8 segment_type[0x10]; 2182 2183 u8 segment_name[4][0x20]; 2184 2185 u8 index1_name[4][0x20]; 2186 2187 u8 index2_name[4][0x20]; 2188 }; 2189 2190 struct mlx5_ifc_resource_dump_segment_header_bits { 2191 u8 length_dw[0x10]; 2192 u8 segment_type[0x10]; 2193 }; 2194 2195 struct mlx5_ifc_resource_dump_command_segment_bits { 2196 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2197 2198 u8 segment_called[0x10]; 2199 u8 vhca_id[0x10]; 2200 2201 u8 index1[0x20]; 2202 2203 u8 index2[0x20]; 2204 2205 u8 num_of_obj1[0x10]; 2206 u8 num_of_obj2[0x10]; 2207 }; 2208 2209 struct mlx5_ifc_resource_dump_error_segment_bits { 2210 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2211 2212 u8 reserved_at_20[0x10]; 2213 u8 syndrome_id[0x10]; 2214 2215 u8 reserved_at_40[0x40]; 2216 2217 u8 error[8][0x20]; 2218 }; 2219 2220 struct mlx5_ifc_resource_dump_info_segment_bits { 2221 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2222 2223 u8 reserved_at_20[0x18]; 2224 u8 dump_version[0x8]; 2225 2226 u8 hw_version[0x20]; 2227 2228 u8 fw_version[0x20]; 2229 }; 2230 2231 struct mlx5_ifc_resource_dump_menu_segment_bits { 2232 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2233 2234 u8 reserved_at_20[0x10]; 2235 u8 num_of_records[0x10]; 2236 2237 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2238 }; 2239 2240 struct mlx5_ifc_resource_dump_resource_segment_bits { 2241 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2242 2243 u8 reserved_at_20[0x20]; 2244 2245 u8 index1[0x20]; 2246 2247 u8 index2[0x20]; 2248 2249 u8 payload[][0x20]; 2250 }; 2251 2252 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2253 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2254 }; 2255 2256 struct mlx5_ifc_menu_resource_dump_response_bits { 2257 struct mlx5_ifc_resource_dump_info_segment_bits info; 2258 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2259 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2260 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2261 }; 2262 2263 enum { 2264 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2265 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2266 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2267 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2268 }; 2269 2270 struct mlx5_ifc_modify_field_select_bits { 2271 u8 modify_field_select[0x20]; 2272 }; 2273 2274 struct mlx5_ifc_field_select_r_roce_np_bits { 2275 u8 field_select_r_roce_np[0x20]; 2276 }; 2277 2278 struct mlx5_ifc_field_select_r_roce_rp_bits { 2279 u8 field_select_r_roce_rp[0x20]; 2280 }; 2281 2282 enum { 2283 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2284 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2285 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2286 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2287 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2288 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2289 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2290 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2291 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2292 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2293 }; 2294 2295 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2296 u8 field_select_8021qaurp[0x20]; 2297 }; 2298 2299 struct mlx5_ifc_phys_layer_cntrs_bits { 2300 u8 time_since_last_clear_high[0x20]; 2301 2302 u8 time_since_last_clear_low[0x20]; 2303 2304 u8 symbol_errors_high[0x20]; 2305 2306 u8 symbol_errors_low[0x20]; 2307 2308 u8 sync_headers_errors_high[0x20]; 2309 2310 u8 sync_headers_errors_low[0x20]; 2311 2312 u8 edpl_bip_errors_lane0_high[0x20]; 2313 2314 u8 edpl_bip_errors_lane0_low[0x20]; 2315 2316 u8 edpl_bip_errors_lane1_high[0x20]; 2317 2318 u8 edpl_bip_errors_lane1_low[0x20]; 2319 2320 u8 edpl_bip_errors_lane2_high[0x20]; 2321 2322 u8 edpl_bip_errors_lane2_low[0x20]; 2323 2324 u8 edpl_bip_errors_lane3_high[0x20]; 2325 2326 u8 edpl_bip_errors_lane3_low[0x20]; 2327 2328 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2329 2330 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2331 2332 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2333 2334 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2335 2336 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2337 2338 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2339 2340 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2341 2342 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2343 2344 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2345 2346 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2347 2348 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2349 2350 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2351 2352 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2353 2354 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2355 2356 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2357 2358 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2359 2360 u8 rs_fec_corrected_blocks_high[0x20]; 2361 2362 u8 rs_fec_corrected_blocks_low[0x20]; 2363 2364 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2365 2366 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2367 2368 u8 rs_fec_no_errors_blocks_high[0x20]; 2369 2370 u8 rs_fec_no_errors_blocks_low[0x20]; 2371 2372 u8 rs_fec_single_error_blocks_high[0x20]; 2373 2374 u8 rs_fec_single_error_blocks_low[0x20]; 2375 2376 u8 rs_fec_corrected_symbols_total_high[0x20]; 2377 2378 u8 rs_fec_corrected_symbols_total_low[0x20]; 2379 2380 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2381 2382 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2383 2384 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2385 2386 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2387 2388 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2389 2390 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2391 2392 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2393 2394 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2395 2396 u8 link_down_events[0x20]; 2397 2398 u8 successful_recovery_events[0x20]; 2399 2400 u8 reserved_at_640[0x180]; 2401 }; 2402 2403 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2404 u8 time_since_last_clear_high[0x20]; 2405 2406 u8 time_since_last_clear_low[0x20]; 2407 2408 u8 phy_received_bits_high[0x20]; 2409 2410 u8 phy_received_bits_low[0x20]; 2411 2412 u8 phy_symbol_errors_high[0x20]; 2413 2414 u8 phy_symbol_errors_low[0x20]; 2415 2416 u8 phy_corrected_bits_high[0x20]; 2417 2418 u8 phy_corrected_bits_low[0x20]; 2419 2420 u8 phy_corrected_bits_lane0_high[0x20]; 2421 2422 u8 phy_corrected_bits_lane0_low[0x20]; 2423 2424 u8 phy_corrected_bits_lane1_high[0x20]; 2425 2426 u8 phy_corrected_bits_lane1_low[0x20]; 2427 2428 u8 phy_corrected_bits_lane2_high[0x20]; 2429 2430 u8 phy_corrected_bits_lane2_low[0x20]; 2431 2432 u8 phy_corrected_bits_lane3_high[0x20]; 2433 2434 u8 phy_corrected_bits_lane3_low[0x20]; 2435 2436 u8 reserved_at_200[0x5c0]; 2437 }; 2438 2439 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2440 u8 symbol_error_counter[0x10]; 2441 2442 u8 link_error_recovery_counter[0x8]; 2443 2444 u8 link_downed_counter[0x8]; 2445 2446 u8 port_rcv_errors[0x10]; 2447 2448 u8 port_rcv_remote_physical_errors[0x10]; 2449 2450 u8 port_rcv_switch_relay_errors[0x10]; 2451 2452 u8 port_xmit_discards[0x10]; 2453 2454 u8 port_xmit_constraint_errors[0x8]; 2455 2456 u8 port_rcv_constraint_errors[0x8]; 2457 2458 u8 reserved_at_70[0x8]; 2459 2460 u8 link_overrun_errors[0x8]; 2461 2462 u8 reserved_at_80[0x10]; 2463 2464 u8 vl_15_dropped[0x10]; 2465 2466 u8 reserved_at_a0[0x80]; 2467 2468 u8 port_xmit_wait[0x20]; 2469 }; 2470 2471 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2472 u8 transmit_queue_high[0x20]; 2473 2474 u8 transmit_queue_low[0x20]; 2475 2476 u8 no_buffer_discard_uc_high[0x20]; 2477 2478 u8 no_buffer_discard_uc_low[0x20]; 2479 2480 u8 reserved_at_80[0x740]; 2481 }; 2482 2483 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2484 u8 wred_discard_high[0x20]; 2485 2486 u8 wred_discard_low[0x20]; 2487 2488 u8 ecn_marked_tc_high[0x20]; 2489 2490 u8 ecn_marked_tc_low[0x20]; 2491 2492 u8 reserved_at_80[0x740]; 2493 }; 2494 2495 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2496 u8 rx_octets_high[0x20]; 2497 2498 u8 rx_octets_low[0x20]; 2499 2500 u8 reserved_at_40[0xc0]; 2501 2502 u8 rx_frames_high[0x20]; 2503 2504 u8 rx_frames_low[0x20]; 2505 2506 u8 tx_octets_high[0x20]; 2507 2508 u8 tx_octets_low[0x20]; 2509 2510 u8 reserved_at_180[0xc0]; 2511 2512 u8 tx_frames_high[0x20]; 2513 2514 u8 tx_frames_low[0x20]; 2515 2516 u8 rx_pause_high[0x20]; 2517 2518 u8 rx_pause_low[0x20]; 2519 2520 u8 rx_pause_duration_high[0x20]; 2521 2522 u8 rx_pause_duration_low[0x20]; 2523 2524 u8 tx_pause_high[0x20]; 2525 2526 u8 tx_pause_low[0x20]; 2527 2528 u8 tx_pause_duration_high[0x20]; 2529 2530 u8 tx_pause_duration_low[0x20]; 2531 2532 u8 rx_pause_transition_high[0x20]; 2533 2534 u8 rx_pause_transition_low[0x20]; 2535 2536 u8 rx_discards_high[0x20]; 2537 2538 u8 rx_discards_low[0x20]; 2539 2540 u8 device_stall_minor_watermark_cnt_high[0x20]; 2541 2542 u8 device_stall_minor_watermark_cnt_low[0x20]; 2543 2544 u8 device_stall_critical_watermark_cnt_high[0x20]; 2545 2546 u8 device_stall_critical_watermark_cnt_low[0x20]; 2547 2548 u8 reserved_at_480[0x340]; 2549 }; 2550 2551 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2552 u8 port_transmit_wait_high[0x20]; 2553 2554 u8 port_transmit_wait_low[0x20]; 2555 2556 u8 reserved_at_40[0x100]; 2557 2558 u8 rx_buffer_almost_full_high[0x20]; 2559 2560 u8 rx_buffer_almost_full_low[0x20]; 2561 2562 u8 rx_buffer_full_high[0x20]; 2563 2564 u8 rx_buffer_full_low[0x20]; 2565 2566 u8 rx_icrc_encapsulated_high[0x20]; 2567 2568 u8 rx_icrc_encapsulated_low[0x20]; 2569 2570 u8 reserved_at_200[0x5c0]; 2571 }; 2572 2573 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2574 u8 dot3stats_alignment_errors_high[0x20]; 2575 2576 u8 dot3stats_alignment_errors_low[0x20]; 2577 2578 u8 dot3stats_fcs_errors_high[0x20]; 2579 2580 u8 dot3stats_fcs_errors_low[0x20]; 2581 2582 u8 dot3stats_single_collision_frames_high[0x20]; 2583 2584 u8 dot3stats_single_collision_frames_low[0x20]; 2585 2586 u8 dot3stats_multiple_collision_frames_high[0x20]; 2587 2588 u8 dot3stats_multiple_collision_frames_low[0x20]; 2589 2590 u8 dot3stats_sqe_test_errors_high[0x20]; 2591 2592 u8 dot3stats_sqe_test_errors_low[0x20]; 2593 2594 u8 dot3stats_deferred_transmissions_high[0x20]; 2595 2596 u8 dot3stats_deferred_transmissions_low[0x20]; 2597 2598 u8 dot3stats_late_collisions_high[0x20]; 2599 2600 u8 dot3stats_late_collisions_low[0x20]; 2601 2602 u8 dot3stats_excessive_collisions_high[0x20]; 2603 2604 u8 dot3stats_excessive_collisions_low[0x20]; 2605 2606 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2607 2608 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2609 2610 u8 dot3stats_carrier_sense_errors_high[0x20]; 2611 2612 u8 dot3stats_carrier_sense_errors_low[0x20]; 2613 2614 u8 dot3stats_frame_too_longs_high[0x20]; 2615 2616 u8 dot3stats_frame_too_longs_low[0x20]; 2617 2618 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2619 2620 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2621 2622 u8 dot3stats_symbol_errors_high[0x20]; 2623 2624 u8 dot3stats_symbol_errors_low[0x20]; 2625 2626 u8 dot3control_in_unknown_opcodes_high[0x20]; 2627 2628 u8 dot3control_in_unknown_opcodes_low[0x20]; 2629 2630 u8 dot3in_pause_frames_high[0x20]; 2631 2632 u8 dot3in_pause_frames_low[0x20]; 2633 2634 u8 dot3out_pause_frames_high[0x20]; 2635 2636 u8 dot3out_pause_frames_low[0x20]; 2637 2638 u8 reserved_at_400[0x3c0]; 2639 }; 2640 2641 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2642 u8 ether_stats_drop_events_high[0x20]; 2643 2644 u8 ether_stats_drop_events_low[0x20]; 2645 2646 u8 ether_stats_octets_high[0x20]; 2647 2648 u8 ether_stats_octets_low[0x20]; 2649 2650 u8 ether_stats_pkts_high[0x20]; 2651 2652 u8 ether_stats_pkts_low[0x20]; 2653 2654 u8 ether_stats_broadcast_pkts_high[0x20]; 2655 2656 u8 ether_stats_broadcast_pkts_low[0x20]; 2657 2658 u8 ether_stats_multicast_pkts_high[0x20]; 2659 2660 u8 ether_stats_multicast_pkts_low[0x20]; 2661 2662 u8 ether_stats_crc_align_errors_high[0x20]; 2663 2664 u8 ether_stats_crc_align_errors_low[0x20]; 2665 2666 u8 ether_stats_undersize_pkts_high[0x20]; 2667 2668 u8 ether_stats_undersize_pkts_low[0x20]; 2669 2670 u8 ether_stats_oversize_pkts_high[0x20]; 2671 2672 u8 ether_stats_oversize_pkts_low[0x20]; 2673 2674 u8 ether_stats_fragments_high[0x20]; 2675 2676 u8 ether_stats_fragments_low[0x20]; 2677 2678 u8 ether_stats_jabbers_high[0x20]; 2679 2680 u8 ether_stats_jabbers_low[0x20]; 2681 2682 u8 ether_stats_collisions_high[0x20]; 2683 2684 u8 ether_stats_collisions_low[0x20]; 2685 2686 u8 ether_stats_pkts64octets_high[0x20]; 2687 2688 u8 ether_stats_pkts64octets_low[0x20]; 2689 2690 u8 ether_stats_pkts65to127octets_high[0x20]; 2691 2692 u8 ether_stats_pkts65to127octets_low[0x20]; 2693 2694 u8 ether_stats_pkts128to255octets_high[0x20]; 2695 2696 u8 ether_stats_pkts128to255octets_low[0x20]; 2697 2698 u8 ether_stats_pkts256to511octets_high[0x20]; 2699 2700 u8 ether_stats_pkts256to511octets_low[0x20]; 2701 2702 u8 ether_stats_pkts512to1023octets_high[0x20]; 2703 2704 u8 ether_stats_pkts512to1023octets_low[0x20]; 2705 2706 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2707 2708 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2709 2710 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2711 2712 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2713 2714 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2715 2716 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2717 2718 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2719 2720 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2721 2722 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2723 2724 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2725 2726 u8 reserved_at_540[0x280]; 2727 }; 2728 2729 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2730 u8 if_in_octets_high[0x20]; 2731 2732 u8 if_in_octets_low[0x20]; 2733 2734 u8 if_in_ucast_pkts_high[0x20]; 2735 2736 u8 if_in_ucast_pkts_low[0x20]; 2737 2738 u8 if_in_discards_high[0x20]; 2739 2740 u8 if_in_discards_low[0x20]; 2741 2742 u8 if_in_errors_high[0x20]; 2743 2744 u8 if_in_errors_low[0x20]; 2745 2746 u8 if_in_unknown_protos_high[0x20]; 2747 2748 u8 if_in_unknown_protos_low[0x20]; 2749 2750 u8 if_out_octets_high[0x20]; 2751 2752 u8 if_out_octets_low[0x20]; 2753 2754 u8 if_out_ucast_pkts_high[0x20]; 2755 2756 u8 if_out_ucast_pkts_low[0x20]; 2757 2758 u8 if_out_discards_high[0x20]; 2759 2760 u8 if_out_discards_low[0x20]; 2761 2762 u8 if_out_errors_high[0x20]; 2763 2764 u8 if_out_errors_low[0x20]; 2765 2766 u8 if_in_multicast_pkts_high[0x20]; 2767 2768 u8 if_in_multicast_pkts_low[0x20]; 2769 2770 u8 if_in_broadcast_pkts_high[0x20]; 2771 2772 u8 if_in_broadcast_pkts_low[0x20]; 2773 2774 u8 if_out_multicast_pkts_high[0x20]; 2775 2776 u8 if_out_multicast_pkts_low[0x20]; 2777 2778 u8 if_out_broadcast_pkts_high[0x20]; 2779 2780 u8 if_out_broadcast_pkts_low[0x20]; 2781 2782 u8 reserved_at_340[0x480]; 2783 }; 2784 2785 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2786 u8 a_frames_transmitted_ok_high[0x20]; 2787 2788 u8 a_frames_transmitted_ok_low[0x20]; 2789 2790 u8 a_frames_received_ok_high[0x20]; 2791 2792 u8 a_frames_received_ok_low[0x20]; 2793 2794 u8 a_frame_check_sequence_errors_high[0x20]; 2795 2796 u8 a_frame_check_sequence_errors_low[0x20]; 2797 2798 u8 a_alignment_errors_high[0x20]; 2799 2800 u8 a_alignment_errors_low[0x20]; 2801 2802 u8 a_octets_transmitted_ok_high[0x20]; 2803 2804 u8 a_octets_transmitted_ok_low[0x20]; 2805 2806 u8 a_octets_received_ok_high[0x20]; 2807 2808 u8 a_octets_received_ok_low[0x20]; 2809 2810 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2811 2812 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2813 2814 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2815 2816 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2817 2818 u8 a_multicast_frames_received_ok_high[0x20]; 2819 2820 u8 a_multicast_frames_received_ok_low[0x20]; 2821 2822 u8 a_broadcast_frames_received_ok_high[0x20]; 2823 2824 u8 a_broadcast_frames_received_ok_low[0x20]; 2825 2826 u8 a_in_range_length_errors_high[0x20]; 2827 2828 u8 a_in_range_length_errors_low[0x20]; 2829 2830 u8 a_out_of_range_length_field_high[0x20]; 2831 2832 u8 a_out_of_range_length_field_low[0x20]; 2833 2834 u8 a_frame_too_long_errors_high[0x20]; 2835 2836 u8 a_frame_too_long_errors_low[0x20]; 2837 2838 u8 a_symbol_error_during_carrier_high[0x20]; 2839 2840 u8 a_symbol_error_during_carrier_low[0x20]; 2841 2842 u8 a_mac_control_frames_transmitted_high[0x20]; 2843 2844 u8 a_mac_control_frames_transmitted_low[0x20]; 2845 2846 u8 a_mac_control_frames_received_high[0x20]; 2847 2848 u8 a_mac_control_frames_received_low[0x20]; 2849 2850 u8 a_unsupported_opcodes_received_high[0x20]; 2851 2852 u8 a_unsupported_opcodes_received_low[0x20]; 2853 2854 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2855 2856 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2857 2858 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2859 2860 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2861 2862 u8 reserved_at_4c0[0x300]; 2863 }; 2864 2865 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2866 u8 life_time_counter_high[0x20]; 2867 2868 u8 life_time_counter_low[0x20]; 2869 2870 u8 rx_errors[0x20]; 2871 2872 u8 tx_errors[0x20]; 2873 2874 u8 l0_to_recovery_eieos[0x20]; 2875 2876 u8 l0_to_recovery_ts[0x20]; 2877 2878 u8 l0_to_recovery_framing[0x20]; 2879 2880 u8 l0_to_recovery_retrain[0x20]; 2881 2882 u8 crc_error_dllp[0x20]; 2883 2884 u8 crc_error_tlp[0x20]; 2885 2886 u8 tx_overflow_buffer_pkt_high[0x20]; 2887 2888 u8 tx_overflow_buffer_pkt_low[0x20]; 2889 2890 u8 outbound_stalled_reads[0x20]; 2891 2892 u8 outbound_stalled_writes[0x20]; 2893 2894 u8 outbound_stalled_reads_events[0x20]; 2895 2896 u8 outbound_stalled_writes_events[0x20]; 2897 2898 u8 reserved_at_200[0x5c0]; 2899 }; 2900 2901 struct mlx5_ifc_cmd_inter_comp_event_bits { 2902 u8 command_completion_vector[0x20]; 2903 2904 u8 reserved_at_20[0xc0]; 2905 }; 2906 2907 struct mlx5_ifc_stall_vl_event_bits { 2908 u8 reserved_at_0[0x18]; 2909 u8 port_num[0x1]; 2910 u8 reserved_at_19[0x3]; 2911 u8 vl[0x4]; 2912 2913 u8 reserved_at_20[0xa0]; 2914 }; 2915 2916 struct mlx5_ifc_db_bf_congestion_event_bits { 2917 u8 event_subtype[0x8]; 2918 u8 reserved_at_8[0x8]; 2919 u8 congestion_level[0x8]; 2920 u8 reserved_at_18[0x8]; 2921 2922 u8 reserved_at_20[0xa0]; 2923 }; 2924 2925 struct mlx5_ifc_gpio_event_bits { 2926 u8 reserved_at_0[0x60]; 2927 2928 u8 gpio_event_hi[0x20]; 2929 2930 u8 gpio_event_lo[0x20]; 2931 2932 u8 reserved_at_a0[0x40]; 2933 }; 2934 2935 struct mlx5_ifc_port_state_change_event_bits { 2936 u8 reserved_at_0[0x40]; 2937 2938 u8 port_num[0x4]; 2939 u8 reserved_at_44[0x1c]; 2940 2941 u8 reserved_at_60[0x80]; 2942 }; 2943 2944 struct mlx5_ifc_dropped_packet_logged_bits { 2945 u8 reserved_at_0[0xe0]; 2946 }; 2947 2948 struct mlx5_ifc_default_timeout_bits { 2949 u8 to_multiplier[0x3]; 2950 u8 reserved_at_3[0x9]; 2951 u8 to_value[0x14]; 2952 }; 2953 2954 struct mlx5_ifc_dtor_reg_bits { 2955 u8 reserved_at_0[0x20]; 2956 2957 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2958 2959 u8 reserved_at_40[0x60]; 2960 2961 struct mlx5_ifc_default_timeout_bits health_poll_to; 2962 2963 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2964 2965 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2966 2967 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2968 2969 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2970 2971 struct mlx5_ifc_default_timeout_bits tear_down_to; 2972 2973 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2974 2975 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2976 2977 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2978 2979 u8 reserved_at_1c0[0x40]; 2980 }; 2981 2982 enum { 2983 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2984 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2985 }; 2986 2987 struct mlx5_ifc_cq_error_bits { 2988 u8 reserved_at_0[0x8]; 2989 u8 cqn[0x18]; 2990 2991 u8 reserved_at_20[0x20]; 2992 2993 u8 reserved_at_40[0x18]; 2994 u8 syndrome[0x8]; 2995 2996 u8 reserved_at_60[0x80]; 2997 }; 2998 2999 struct mlx5_ifc_rdma_page_fault_event_bits { 3000 u8 bytes_committed[0x20]; 3001 3002 u8 r_key[0x20]; 3003 3004 u8 reserved_at_40[0x10]; 3005 u8 packet_len[0x10]; 3006 3007 u8 rdma_op_len[0x20]; 3008 3009 u8 rdma_va[0x40]; 3010 3011 u8 reserved_at_c0[0x5]; 3012 u8 rdma[0x1]; 3013 u8 write[0x1]; 3014 u8 requestor[0x1]; 3015 u8 qp_number[0x18]; 3016 }; 3017 3018 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3019 u8 bytes_committed[0x20]; 3020 3021 u8 reserved_at_20[0x10]; 3022 u8 wqe_index[0x10]; 3023 3024 u8 reserved_at_40[0x10]; 3025 u8 len[0x10]; 3026 3027 u8 reserved_at_60[0x60]; 3028 3029 u8 reserved_at_c0[0x5]; 3030 u8 rdma[0x1]; 3031 u8 write_read[0x1]; 3032 u8 requestor[0x1]; 3033 u8 qpn[0x18]; 3034 }; 3035 3036 struct mlx5_ifc_qp_events_bits { 3037 u8 reserved_at_0[0xa0]; 3038 3039 u8 type[0x8]; 3040 u8 reserved_at_a8[0x18]; 3041 3042 u8 reserved_at_c0[0x8]; 3043 u8 qpn_rqn_sqn[0x18]; 3044 }; 3045 3046 struct mlx5_ifc_dct_events_bits { 3047 u8 reserved_at_0[0xc0]; 3048 3049 u8 reserved_at_c0[0x8]; 3050 u8 dct_number[0x18]; 3051 }; 3052 3053 struct mlx5_ifc_comp_event_bits { 3054 u8 reserved_at_0[0xc0]; 3055 3056 u8 reserved_at_c0[0x8]; 3057 u8 cq_number[0x18]; 3058 }; 3059 3060 enum { 3061 MLX5_QPC_STATE_RST = 0x0, 3062 MLX5_QPC_STATE_INIT = 0x1, 3063 MLX5_QPC_STATE_RTR = 0x2, 3064 MLX5_QPC_STATE_RTS = 0x3, 3065 MLX5_QPC_STATE_SQER = 0x4, 3066 MLX5_QPC_STATE_ERR = 0x6, 3067 MLX5_QPC_STATE_SQD = 0x7, 3068 MLX5_QPC_STATE_SUSPENDED = 0x9, 3069 }; 3070 3071 enum { 3072 MLX5_QPC_ST_RC = 0x0, 3073 MLX5_QPC_ST_UC = 0x1, 3074 MLX5_QPC_ST_UD = 0x2, 3075 MLX5_QPC_ST_XRC = 0x3, 3076 MLX5_QPC_ST_DCI = 0x5, 3077 MLX5_QPC_ST_QP0 = 0x7, 3078 MLX5_QPC_ST_QP1 = 0x8, 3079 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3080 MLX5_QPC_ST_REG_UMR = 0xc, 3081 }; 3082 3083 enum { 3084 MLX5_QPC_PM_STATE_ARMED = 0x0, 3085 MLX5_QPC_PM_STATE_REARM = 0x1, 3086 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3087 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3088 }; 3089 3090 enum { 3091 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3092 }; 3093 3094 enum { 3095 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3096 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3097 }; 3098 3099 enum { 3100 MLX5_QPC_MTU_256_BYTES = 0x1, 3101 MLX5_QPC_MTU_512_BYTES = 0x2, 3102 MLX5_QPC_MTU_1K_BYTES = 0x3, 3103 MLX5_QPC_MTU_2K_BYTES = 0x4, 3104 MLX5_QPC_MTU_4K_BYTES = 0x5, 3105 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3106 }; 3107 3108 enum { 3109 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3110 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3111 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3112 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3113 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3114 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3115 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3116 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3117 }; 3118 3119 enum { 3120 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3121 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3122 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3123 }; 3124 3125 enum { 3126 MLX5_QPC_CS_RES_DISABLE = 0x0, 3127 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3128 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3129 }; 3130 3131 enum { 3132 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3133 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3134 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3135 }; 3136 3137 struct mlx5_ifc_qpc_bits { 3138 u8 state[0x4]; 3139 u8 lag_tx_port_affinity[0x4]; 3140 u8 st[0x8]; 3141 u8 reserved_at_10[0x2]; 3142 u8 isolate_vl_tc[0x1]; 3143 u8 pm_state[0x2]; 3144 u8 reserved_at_15[0x1]; 3145 u8 req_e2e_credit_mode[0x2]; 3146 u8 offload_type[0x4]; 3147 u8 end_padding_mode[0x2]; 3148 u8 reserved_at_1e[0x2]; 3149 3150 u8 wq_signature[0x1]; 3151 u8 block_lb_mc[0x1]; 3152 u8 atomic_like_write_en[0x1]; 3153 u8 latency_sensitive[0x1]; 3154 u8 reserved_at_24[0x1]; 3155 u8 drain_sigerr[0x1]; 3156 u8 reserved_at_26[0x2]; 3157 u8 pd[0x18]; 3158 3159 u8 mtu[0x3]; 3160 u8 log_msg_max[0x5]; 3161 u8 reserved_at_48[0x1]; 3162 u8 log_rq_size[0x4]; 3163 u8 log_rq_stride[0x3]; 3164 u8 no_sq[0x1]; 3165 u8 log_sq_size[0x4]; 3166 u8 reserved_at_55[0x3]; 3167 u8 ts_format[0x2]; 3168 u8 reserved_at_5a[0x1]; 3169 u8 rlky[0x1]; 3170 u8 ulp_stateless_offload_mode[0x4]; 3171 3172 u8 counter_set_id[0x8]; 3173 u8 uar_page[0x18]; 3174 3175 u8 reserved_at_80[0x8]; 3176 u8 user_index[0x18]; 3177 3178 u8 reserved_at_a0[0x3]; 3179 u8 log_page_size[0x5]; 3180 u8 remote_qpn[0x18]; 3181 3182 struct mlx5_ifc_ads_bits primary_address_path; 3183 3184 struct mlx5_ifc_ads_bits secondary_address_path; 3185 3186 u8 log_ack_req_freq[0x4]; 3187 u8 reserved_at_384[0x4]; 3188 u8 log_sra_max[0x3]; 3189 u8 reserved_at_38b[0x2]; 3190 u8 retry_count[0x3]; 3191 u8 rnr_retry[0x3]; 3192 u8 reserved_at_393[0x1]; 3193 u8 fre[0x1]; 3194 u8 cur_rnr_retry[0x3]; 3195 u8 cur_retry_count[0x3]; 3196 u8 reserved_at_39b[0x5]; 3197 3198 u8 reserved_at_3a0[0x20]; 3199 3200 u8 reserved_at_3c0[0x8]; 3201 u8 next_send_psn[0x18]; 3202 3203 u8 reserved_at_3e0[0x3]; 3204 u8 log_num_dci_stream_channels[0x5]; 3205 u8 cqn_snd[0x18]; 3206 3207 u8 reserved_at_400[0x3]; 3208 u8 log_num_dci_errored_streams[0x5]; 3209 u8 deth_sqpn[0x18]; 3210 3211 u8 reserved_at_420[0x20]; 3212 3213 u8 reserved_at_440[0x8]; 3214 u8 last_acked_psn[0x18]; 3215 3216 u8 reserved_at_460[0x8]; 3217 u8 ssn[0x18]; 3218 3219 u8 reserved_at_480[0x8]; 3220 u8 log_rra_max[0x3]; 3221 u8 reserved_at_48b[0x1]; 3222 u8 atomic_mode[0x4]; 3223 u8 rre[0x1]; 3224 u8 rwe[0x1]; 3225 u8 rae[0x1]; 3226 u8 reserved_at_493[0x1]; 3227 u8 page_offset[0x6]; 3228 u8 reserved_at_49a[0x3]; 3229 u8 cd_slave_receive[0x1]; 3230 u8 cd_slave_send[0x1]; 3231 u8 cd_master[0x1]; 3232 3233 u8 reserved_at_4a0[0x3]; 3234 u8 min_rnr_nak[0x5]; 3235 u8 next_rcv_psn[0x18]; 3236 3237 u8 reserved_at_4c0[0x8]; 3238 u8 xrcd[0x18]; 3239 3240 u8 reserved_at_4e0[0x8]; 3241 u8 cqn_rcv[0x18]; 3242 3243 u8 dbr_addr[0x40]; 3244 3245 u8 q_key[0x20]; 3246 3247 u8 reserved_at_560[0x5]; 3248 u8 rq_type[0x3]; 3249 u8 srqn_rmpn_xrqn[0x18]; 3250 3251 u8 reserved_at_580[0x8]; 3252 u8 rmsn[0x18]; 3253 3254 u8 hw_sq_wqebb_counter[0x10]; 3255 u8 sw_sq_wqebb_counter[0x10]; 3256 3257 u8 hw_rq_counter[0x20]; 3258 3259 u8 sw_rq_counter[0x20]; 3260 3261 u8 reserved_at_600[0x20]; 3262 3263 u8 reserved_at_620[0xf]; 3264 u8 cgs[0x1]; 3265 u8 cs_req[0x8]; 3266 u8 cs_res[0x8]; 3267 3268 u8 dc_access_key[0x40]; 3269 3270 u8 reserved_at_680[0x3]; 3271 u8 dbr_umem_valid[0x1]; 3272 3273 u8 reserved_at_684[0xbc]; 3274 }; 3275 3276 struct mlx5_ifc_roce_addr_layout_bits { 3277 u8 source_l3_address[16][0x8]; 3278 3279 u8 reserved_at_80[0x3]; 3280 u8 vlan_valid[0x1]; 3281 u8 vlan_id[0xc]; 3282 u8 source_mac_47_32[0x10]; 3283 3284 u8 source_mac_31_0[0x20]; 3285 3286 u8 reserved_at_c0[0x14]; 3287 u8 roce_l3_type[0x4]; 3288 u8 roce_version[0x8]; 3289 3290 u8 reserved_at_e0[0x20]; 3291 }; 3292 3293 struct mlx5_ifc_shampo_cap_bits { 3294 u8 reserved_at_0[0x3]; 3295 u8 shampo_log_max_reservation_size[0x5]; 3296 u8 reserved_at_8[0x3]; 3297 u8 shampo_log_min_reservation_size[0x5]; 3298 u8 shampo_min_mss_size[0x10]; 3299 3300 u8 reserved_at_20[0x3]; 3301 u8 shampo_max_log_headers_entry_size[0x5]; 3302 u8 reserved_at_28[0x18]; 3303 3304 u8 reserved_at_40[0x7c0]; 3305 }; 3306 3307 union mlx5_ifc_hca_cap_union_bits { 3308 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3309 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3310 struct mlx5_ifc_odp_cap_bits odp_cap; 3311 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3312 struct mlx5_ifc_roce_cap_bits roce_cap; 3313 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3314 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3315 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3316 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3317 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3318 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3319 struct mlx5_ifc_qos_cap_bits qos_cap; 3320 struct mlx5_ifc_debug_cap_bits debug_cap; 3321 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3322 struct mlx5_ifc_tls_cap_bits tls_cap; 3323 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3324 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3325 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3326 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3327 u8 reserved_at_0[0x8000]; 3328 }; 3329 3330 enum { 3331 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3332 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3333 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3334 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3335 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3336 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3337 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3338 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3339 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3340 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3341 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3342 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3343 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3344 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3345 }; 3346 3347 enum { 3348 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3349 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3350 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3351 }; 3352 3353 enum { 3354 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3355 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3356 }; 3357 3358 struct mlx5_ifc_vlan_bits { 3359 u8 ethtype[0x10]; 3360 u8 prio[0x3]; 3361 u8 cfi[0x1]; 3362 u8 vid[0xc]; 3363 }; 3364 3365 enum { 3366 MLX5_FLOW_METER_COLOR_RED = 0x0, 3367 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3368 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3369 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3370 }; 3371 3372 enum { 3373 MLX5_EXE_ASO_FLOW_METER = 0x2, 3374 }; 3375 3376 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3377 u8 return_reg_id[0x4]; 3378 u8 aso_type[0x4]; 3379 u8 reserved_at_8[0x14]; 3380 u8 action[0x1]; 3381 u8 init_color[0x2]; 3382 u8 meter_id[0x1]; 3383 }; 3384 3385 union mlx5_ifc_exe_aso_ctrl { 3386 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3387 }; 3388 3389 struct mlx5_ifc_execute_aso_bits { 3390 u8 valid[0x1]; 3391 u8 reserved_at_1[0x7]; 3392 u8 aso_object_id[0x18]; 3393 3394 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3395 }; 3396 3397 struct mlx5_ifc_flow_context_bits { 3398 struct mlx5_ifc_vlan_bits push_vlan; 3399 3400 u8 group_id[0x20]; 3401 3402 u8 reserved_at_40[0x8]; 3403 u8 flow_tag[0x18]; 3404 3405 u8 reserved_at_60[0x10]; 3406 u8 action[0x10]; 3407 3408 u8 extended_destination[0x1]; 3409 u8 reserved_at_81[0x1]; 3410 u8 flow_source[0x2]; 3411 u8 encrypt_decrypt_type[0x4]; 3412 u8 destination_list_size[0x18]; 3413 3414 u8 reserved_at_a0[0x8]; 3415 u8 flow_counter_list_size[0x18]; 3416 3417 u8 packet_reformat_id[0x20]; 3418 3419 u8 modify_header_id[0x20]; 3420 3421 struct mlx5_ifc_vlan_bits push_vlan_2; 3422 3423 u8 encrypt_decrypt_obj_id[0x20]; 3424 u8 reserved_at_140[0xc0]; 3425 3426 struct mlx5_ifc_fte_match_param_bits match_value; 3427 3428 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3429 3430 u8 reserved_at_1300[0x500]; 3431 3432 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3433 }; 3434 3435 enum { 3436 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3437 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3438 }; 3439 3440 struct mlx5_ifc_xrc_srqc_bits { 3441 u8 state[0x4]; 3442 u8 log_xrc_srq_size[0x4]; 3443 u8 reserved_at_8[0x18]; 3444 3445 u8 wq_signature[0x1]; 3446 u8 cont_srq[0x1]; 3447 u8 reserved_at_22[0x1]; 3448 u8 rlky[0x1]; 3449 u8 basic_cyclic_rcv_wqe[0x1]; 3450 u8 log_rq_stride[0x3]; 3451 u8 xrcd[0x18]; 3452 3453 u8 page_offset[0x6]; 3454 u8 reserved_at_46[0x1]; 3455 u8 dbr_umem_valid[0x1]; 3456 u8 cqn[0x18]; 3457 3458 u8 reserved_at_60[0x20]; 3459 3460 u8 user_index_equal_xrc_srqn[0x1]; 3461 u8 reserved_at_81[0x1]; 3462 u8 log_page_size[0x6]; 3463 u8 user_index[0x18]; 3464 3465 u8 reserved_at_a0[0x20]; 3466 3467 u8 reserved_at_c0[0x8]; 3468 u8 pd[0x18]; 3469 3470 u8 lwm[0x10]; 3471 u8 wqe_cnt[0x10]; 3472 3473 u8 reserved_at_100[0x40]; 3474 3475 u8 db_record_addr_h[0x20]; 3476 3477 u8 db_record_addr_l[0x1e]; 3478 u8 reserved_at_17e[0x2]; 3479 3480 u8 reserved_at_180[0x80]; 3481 }; 3482 3483 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3484 u8 counter_error_queues[0x20]; 3485 3486 u8 total_error_queues[0x20]; 3487 3488 u8 send_queue_priority_update_flow[0x20]; 3489 3490 u8 reserved_at_60[0x20]; 3491 3492 u8 nic_receive_steering_discard[0x40]; 3493 3494 u8 receive_discard_vport_down[0x40]; 3495 3496 u8 transmit_discard_vport_down[0x40]; 3497 3498 u8 async_eq_overrun[0x20]; 3499 3500 u8 comp_eq_overrun[0x20]; 3501 3502 u8 reserved_at_180[0x20]; 3503 3504 u8 invalid_command[0x20]; 3505 3506 u8 quota_exceeded_command[0x20]; 3507 3508 u8 internal_rq_out_of_buffer[0x20]; 3509 3510 u8 cq_overrun[0x20]; 3511 3512 u8 reserved_at_220[0xde0]; 3513 }; 3514 3515 struct mlx5_ifc_traffic_counter_bits { 3516 u8 packets[0x40]; 3517 3518 u8 octets[0x40]; 3519 }; 3520 3521 struct mlx5_ifc_tisc_bits { 3522 u8 strict_lag_tx_port_affinity[0x1]; 3523 u8 tls_en[0x1]; 3524 u8 reserved_at_2[0x2]; 3525 u8 lag_tx_port_affinity[0x04]; 3526 3527 u8 reserved_at_8[0x4]; 3528 u8 prio[0x4]; 3529 u8 reserved_at_10[0x10]; 3530 3531 u8 reserved_at_20[0x100]; 3532 3533 u8 reserved_at_120[0x8]; 3534 u8 transport_domain[0x18]; 3535 3536 u8 reserved_at_140[0x8]; 3537 u8 underlay_qpn[0x18]; 3538 3539 u8 reserved_at_160[0x8]; 3540 u8 pd[0x18]; 3541 3542 u8 reserved_at_180[0x380]; 3543 }; 3544 3545 enum { 3546 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3547 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3548 }; 3549 3550 enum { 3551 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3552 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3553 }; 3554 3555 enum { 3556 MLX5_RX_HASH_FN_NONE = 0x0, 3557 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3558 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3559 }; 3560 3561 enum { 3562 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3563 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3564 }; 3565 3566 struct mlx5_ifc_tirc_bits { 3567 u8 reserved_at_0[0x20]; 3568 3569 u8 disp_type[0x4]; 3570 u8 tls_en[0x1]; 3571 u8 reserved_at_25[0x1b]; 3572 3573 u8 reserved_at_40[0x40]; 3574 3575 u8 reserved_at_80[0x4]; 3576 u8 lro_timeout_period_usecs[0x10]; 3577 u8 packet_merge_mask[0x4]; 3578 u8 lro_max_ip_payload_size[0x8]; 3579 3580 u8 reserved_at_a0[0x40]; 3581 3582 u8 reserved_at_e0[0x8]; 3583 u8 inline_rqn[0x18]; 3584 3585 u8 rx_hash_symmetric[0x1]; 3586 u8 reserved_at_101[0x1]; 3587 u8 tunneled_offload_en[0x1]; 3588 u8 reserved_at_103[0x5]; 3589 u8 indirect_table[0x18]; 3590 3591 u8 rx_hash_fn[0x4]; 3592 u8 reserved_at_124[0x2]; 3593 u8 self_lb_block[0x2]; 3594 u8 transport_domain[0x18]; 3595 3596 u8 rx_hash_toeplitz_key[10][0x20]; 3597 3598 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3599 3600 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3601 3602 u8 reserved_at_2c0[0x4c0]; 3603 }; 3604 3605 enum { 3606 MLX5_SRQC_STATE_GOOD = 0x0, 3607 MLX5_SRQC_STATE_ERROR = 0x1, 3608 }; 3609 3610 struct mlx5_ifc_srqc_bits { 3611 u8 state[0x4]; 3612 u8 log_srq_size[0x4]; 3613 u8 reserved_at_8[0x18]; 3614 3615 u8 wq_signature[0x1]; 3616 u8 cont_srq[0x1]; 3617 u8 reserved_at_22[0x1]; 3618 u8 rlky[0x1]; 3619 u8 reserved_at_24[0x1]; 3620 u8 log_rq_stride[0x3]; 3621 u8 xrcd[0x18]; 3622 3623 u8 page_offset[0x6]; 3624 u8 reserved_at_46[0x2]; 3625 u8 cqn[0x18]; 3626 3627 u8 reserved_at_60[0x20]; 3628 3629 u8 reserved_at_80[0x2]; 3630 u8 log_page_size[0x6]; 3631 u8 reserved_at_88[0x18]; 3632 3633 u8 reserved_at_a0[0x20]; 3634 3635 u8 reserved_at_c0[0x8]; 3636 u8 pd[0x18]; 3637 3638 u8 lwm[0x10]; 3639 u8 wqe_cnt[0x10]; 3640 3641 u8 reserved_at_100[0x40]; 3642 3643 u8 dbr_addr[0x40]; 3644 3645 u8 reserved_at_180[0x80]; 3646 }; 3647 3648 enum { 3649 MLX5_SQC_STATE_RST = 0x0, 3650 MLX5_SQC_STATE_RDY = 0x1, 3651 MLX5_SQC_STATE_ERR = 0x3, 3652 }; 3653 3654 struct mlx5_ifc_sqc_bits { 3655 u8 rlky[0x1]; 3656 u8 cd_master[0x1]; 3657 u8 fre[0x1]; 3658 u8 flush_in_error_en[0x1]; 3659 u8 allow_multi_pkt_send_wqe[0x1]; 3660 u8 min_wqe_inline_mode[0x3]; 3661 u8 state[0x4]; 3662 u8 reg_umr[0x1]; 3663 u8 allow_swp[0x1]; 3664 u8 hairpin[0x1]; 3665 u8 reserved_at_f[0xb]; 3666 u8 ts_format[0x2]; 3667 u8 reserved_at_1c[0x4]; 3668 3669 u8 reserved_at_20[0x8]; 3670 u8 user_index[0x18]; 3671 3672 u8 reserved_at_40[0x8]; 3673 u8 cqn[0x18]; 3674 3675 u8 reserved_at_60[0x8]; 3676 u8 hairpin_peer_rq[0x18]; 3677 3678 u8 reserved_at_80[0x10]; 3679 u8 hairpin_peer_vhca[0x10]; 3680 3681 u8 reserved_at_a0[0x20]; 3682 3683 u8 reserved_at_c0[0x8]; 3684 u8 ts_cqe_to_dest_cqn[0x18]; 3685 3686 u8 reserved_at_e0[0x10]; 3687 u8 packet_pacing_rate_limit_index[0x10]; 3688 u8 tis_lst_sz[0x10]; 3689 u8 qos_queue_group_id[0x10]; 3690 3691 u8 reserved_at_120[0x40]; 3692 3693 u8 reserved_at_160[0x8]; 3694 u8 tis_num_0[0x18]; 3695 3696 struct mlx5_ifc_wq_bits wq; 3697 }; 3698 3699 enum { 3700 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3701 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3702 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3703 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3704 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3705 }; 3706 3707 enum { 3708 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3709 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3710 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3711 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3712 }; 3713 3714 struct mlx5_ifc_scheduling_context_bits { 3715 u8 element_type[0x8]; 3716 u8 reserved_at_8[0x18]; 3717 3718 u8 element_attributes[0x20]; 3719 3720 u8 parent_element_id[0x20]; 3721 3722 u8 reserved_at_60[0x40]; 3723 3724 u8 bw_share[0x20]; 3725 3726 u8 max_average_bw[0x20]; 3727 3728 u8 reserved_at_e0[0x120]; 3729 }; 3730 3731 struct mlx5_ifc_rqtc_bits { 3732 u8 reserved_at_0[0xa0]; 3733 3734 u8 reserved_at_a0[0x5]; 3735 u8 list_q_type[0x3]; 3736 u8 reserved_at_a8[0x8]; 3737 u8 rqt_max_size[0x10]; 3738 3739 u8 rq_vhca_id_format[0x1]; 3740 u8 reserved_at_c1[0xf]; 3741 u8 rqt_actual_size[0x10]; 3742 3743 u8 reserved_at_e0[0x6a0]; 3744 3745 struct mlx5_ifc_rq_num_bits rq_num[]; 3746 }; 3747 3748 enum { 3749 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3750 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3751 }; 3752 3753 enum { 3754 MLX5_RQC_STATE_RST = 0x0, 3755 MLX5_RQC_STATE_RDY = 0x1, 3756 MLX5_RQC_STATE_ERR = 0x3, 3757 }; 3758 3759 enum { 3760 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3761 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3762 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3763 }; 3764 3765 enum { 3766 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3767 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3768 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3769 }; 3770 3771 struct mlx5_ifc_rqc_bits { 3772 u8 rlky[0x1]; 3773 u8 delay_drop_en[0x1]; 3774 u8 scatter_fcs[0x1]; 3775 u8 vsd[0x1]; 3776 u8 mem_rq_type[0x4]; 3777 u8 state[0x4]; 3778 u8 reserved_at_c[0x1]; 3779 u8 flush_in_error_en[0x1]; 3780 u8 hairpin[0x1]; 3781 u8 reserved_at_f[0xb]; 3782 u8 ts_format[0x2]; 3783 u8 reserved_at_1c[0x4]; 3784 3785 u8 reserved_at_20[0x8]; 3786 u8 user_index[0x18]; 3787 3788 u8 reserved_at_40[0x8]; 3789 u8 cqn[0x18]; 3790 3791 u8 counter_set_id[0x8]; 3792 u8 reserved_at_68[0x18]; 3793 3794 u8 reserved_at_80[0x8]; 3795 u8 rmpn[0x18]; 3796 3797 u8 reserved_at_a0[0x8]; 3798 u8 hairpin_peer_sq[0x18]; 3799 3800 u8 reserved_at_c0[0x10]; 3801 u8 hairpin_peer_vhca[0x10]; 3802 3803 u8 reserved_at_e0[0x46]; 3804 u8 shampo_no_match_alignment_granularity[0x2]; 3805 u8 reserved_at_128[0x6]; 3806 u8 shampo_match_criteria_type[0x2]; 3807 u8 reservation_timeout[0x10]; 3808 3809 u8 reserved_at_140[0x40]; 3810 3811 struct mlx5_ifc_wq_bits wq; 3812 }; 3813 3814 enum { 3815 MLX5_RMPC_STATE_RDY = 0x1, 3816 MLX5_RMPC_STATE_ERR = 0x3, 3817 }; 3818 3819 struct mlx5_ifc_rmpc_bits { 3820 u8 reserved_at_0[0x8]; 3821 u8 state[0x4]; 3822 u8 reserved_at_c[0x14]; 3823 3824 u8 basic_cyclic_rcv_wqe[0x1]; 3825 u8 reserved_at_21[0x1f]; 3826 3827 u8 reserved_at_40[0x140]; 3828 3829 struct mlx5_ifc_wq_bits wq; 3830 }; 3831 3832 enum { 3833 VHCA_ID_TYPE_HW = 0, 3834 VHCA_ID_TYPE_SW = 1, 3835 }; 3836 3837 struct mlx5_ifc_nic_vport_context_bits { 3838 u8 reserved_at_0[0x5]; 3839 u8 min_wqe_inline_mode[0x3]; 3840 u8 reserved_at_8[0x15]; 3841 u8 disable_mc_local_lb[0x1]; 3842 u8 disable_uc_local_lb[0x1]; 3843 u8 roce_en[0x1]; 3844 3845 u8 arm_change_event[0x1]; 3846 u8 reserved_at_21[0x1a]; 3847 u8 event_on_mtu[0x1]; 3848 u8 event_on_promisc_change[0x1]; 3849 u8 event_on_vlan_change[0x1]; 3850 u8 event_on_mc_address_change[0x1]; 3851 u8 event_on_uc_address_change[0x1]; 3852 3853 u8 vhca_id_type[0x1]; 3854 u8 reserved_at_41[0xb]; 3855 u8 affiliation_criteria[0x4]; 3856 u8 affiliated_vhca_id[0x10]; 3857 3858 u8 reserved_at_60[0xd0]; 3859 3860 u8 mtu[0x10]; 3861 3862 u8 system_image_guid[0x40]; 3863 u8 port_guid[0x40]; 3864 u8 node_guid[0x40]; 3865 3866 u8 reserved_at_200[0x140]; 3867 u8 qkey_violation_counter[0x10]; 3868 u8 reserved_at_350[0x430]; 3869 3870 u8 promisc_uc[0x1]; 3871 u8 promisc_mc[0x1]; 3872 u8 promisc_all[0x1]; 3873 u8 reserved_at_783[0x2]; 3874 u8 allowed_list_type[0x3]; 3875 u8 reserved_at_788[0xc]; 3876 u8 allowed_list_size[0xc]; 3877 3878 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3879 3880 u8 reserved_at_7e0[0x20]; 3881 3882 u8 current_uc_mac_address[][0x40]; 3883 }; 3884 3885 enum { 3886 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3887 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3888 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3889 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3890 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3891 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3892 }; 3893 3894 struct mlx5_ifc_mkc_bits { 3895 u8 reserved_at_0[0x1]; 3896 u8 free[0x1]; 3897 u8 reserved_at_2[0x1]; 3898 u8 access_mode_4_2[0x3]; 3899 u8 reserved_at_6[0x7]; 3900 u8 relaxed_ordering_write[0x1]; 3901 u8 reserved_at_e[0x1]; 3902 u8 small_fence_on_rdma_read_response[0x1]; 3903 u8 umr_en[0x1]; 3904 u8 a[0x1]; 3905 u8 rw[0x1]; 3906 u8 rr[0x1]; 3907 u8 lw[0x1]; 3908 u8 lr[0x1]; 3909 u8 access_mode_1_0[0x2]; 3910 u8 reserved_at_18[0x8]; 3911 3912 u8 qpn[0x18]; 3913 u8 mkey_7_0[0x8]; 3914 3915 u8 reserved_at_40[0x20]; 3916 3917 u8 length64[0x1]; 3918 u8 bsf_en[0x1]; 3919 u8 sync_umr[0x1]; 3920 u8 reserved_at_63[0x2]; 3921 u8 expected_sigerr_count[0x1]; 3922 u8 reserved_at_66[0x1]; 3923 u8 en_rinval[0x1]; 3924 u8 pd[0x18]; 3925 3926 u8 start_addr[0x40]; 3927 3928 u8 len[0x40]; 3929 3930 u8 bsf_octword_size[0x20]; 3931 3932 u8 reserved_at_120[0x80]; 3933 3934 u8 translations_octword_size[0x20]; 3935 3936 u8 reserved_at_1c0[0x19]; 3937 u8 relaxed_ordering_read[0x1]; 3938 u8 reserved_at_1d9[0x1]; 3939 u8 log_page_size[0x5]; 3940 3941 u8 reserved_at_1e0[0x20]; 3942 }; 3943 3944 struct mlx5_ifc_pkey_bits { 3945 u8 reserved_at_0[0x10]; 3946 u8 pkey[0x10]; 3947 }; 3948 3949 struct mlx5_ifc_array128_auto_bits { 3950 u8 array128_auto[16][0x8]; 3951 }; 3952 3953 struct mlx5_ifc_hca_vport_context_bits { 3954 u8 field_select[0x20]; 3955 3956 u8 reserved_at_20[0xe0]; 3957 3958 u8 sm_virt_aware[0x1]; 3959 u8 has_smi[0x1]; 3960 u8 has_raw[0x1]; 3961 u8 grh_required[0x1]; 3962 u8 reserved_at_104[0xc]; 3963 u8 port_physical_state[0x4]; 3964 u8 vport_state_policy[0x4]; 3965 u8 port_state[0x4]; 3966 u8 vport_state[0x4]; 3967 3968 u8 reserved_at_120[0x20]; 3969 3970 u8 system_image_guid[0x40]; 3971 3972 u8 port_guid[0x40]; 3973 3974 u8 node_guid[0x40]; 3975 3976 u8 cap_mask1[0x20]; 3977 3978 u8 cap_mask1_field_select[0x20]; 3979 3980 u8 cap_mask2[0x20]; 3981 3982 u8 cap_mask2_field_select[0x20]; 3983 3984 u8 reserved_at_280[0x80]; 3985 3986 u8 lid[0x10]; 3987 u8 reserved_at_310[0x4]; 3988 u8 init_type_reply[0x4]; 3989 u8 lmc[0x3]; 3990 u8 subnet_timeout[0x5]; 3991 3992 u8 sm_lid[0x10]; 3993 u8 sm_sl[0x4]; 3994 u8 reserved_at_334[0xc]; 3995 3996 u8 qkey_violation_counter[0x10]; 3997 u8 pkey_violation_counter[0x10]; 3998 3999 u8 reserved_at_360[0xca0]; 4000 }; 4001 4002 struct mlx5_ifc_esw_vport_context_bits { 4003 u8 fdb_to_vport_reg_c[0x1]; 4004 u8 reserved_at_1[0x2]; 4005 u8 vport_svlan_strip[0x1]; 4006 u8 vport_cvlan_strip[0x1]; 4007 u8 vport_svlan_insert[0x1]; 4008 u8 vport_cvlan_insert[0x2]; 4009 u8 fdb_to_vport_reg_c_id[0x8]; 4010 u8 reserved_at_10[0x10]; 4011 4012 u8 reserved_at_20[0x20]; 4013 4014 u8 svlan_cfi[0x1]; 4015 u8 svlan_pcp[0x3]; 4016 u8 svlan_id[0xc]; 4017 u8 cvlan_cfi[0x1]; 4018 u8 cvlan_pcp[0x3]; 4019 u8 cvlan_id[0xc]; 4020 4021 u8 reserved_at_60[0x720]; 4022 4023 u8 sw_steering_vport_icm_address_rx[0x40]; 4024 4025 u8 sw_steering_vport_icm_address_tx[0x40]; 4026 }; 4027 4028 enum { 4029 MLX5_EQC_STATUS_OK = 0x0, 4030 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4031 }; 4032 4033 enum { 4034 MLX5_EQC_ST_ARMED = 0x9, 4035 MLX5_EQC_ST_FIRED = 0xa, 4036 }; 4037 4038 struct mlx5_ifc_eqc_bits { 4039 u8 status[0x4]; 4040 u8 reserved_at_4[0x9]; 4041 u8 ec[0x1]; 4042 u8 oi[0x1]; 4043 u8 reserved_at_f[0x5]; 4044 u8 st[0x4]; 4045 u8 reserved_at_18[0x8]; 4046 4047 u8 reserved_at_20[0x20]; 4048 4049 u8 reserved_at_40[0x14]; 4050 u8 page_offset[0x6]; 4051 u8 reserved_at_5a[0x6]; 4052 4053 u8 reserved_at_60[0x3]; 4054 u8 log_eq_size[0x5]; 4055 u8 uar_page[0x18]; 4056 4057 u8 reserved_at_80[0x20]; 4058 4059 u8 reserved_at_a0[0x14]; 4060 u8 intr[0xc]; 4061 4062 u8 reserved_at_c0[0x3]; 4063 u8 log_page_size[0x5]; 4064 u8 reserved_at_c8[0x18]; 4065 4066 u8 reserved_at_e0[0x60]; 4067 4068 u8 reserved_at_140[0x8]; 4069 u8 consumer_counter[0x18]; 4070 4071 u8 reserved_at_160[0x8]; 4072 u8 producer_counter[0x18]; 4073 4074 u8 reserved_at_180[0x80]; 4075 }; 4076 4077 enum { 4078 MLX5_DCTC_STATE_ACTIVE = 0x0, 4079 MLX5_DCTC_STATE_DRAINING = 0x1, 4080 MLX5_DCTC_STATE_DRAINED = 0x2, 4081 }; 4082 4083 enum { 4084 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4085 MLX5_DCTC_CS_RES_NA = 0x1, 4086 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4087 }; 4088 4089 enum { 4090 MLX5_DCTC_MTU_256_BYTES = 0x1, 4091 MLX5_DCTC_MTU_512_BYTES = 0x2, 4092 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4093 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4094 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4095 }; 4096 4097 struct mlx5_ifc_dctc_bits { 4098 u8 reserved_at_0[0x4]; 4099 u8 state[0x4]; 4100 u8 reserved_at_8[0x18]; 4101 4102 u8 reserved_at_20[0x8]; 4103 u8 user_index[0x18]; 4104 4105 u8 reserved_at_40[0x8]; 4106 u8 cqn[0x18]; 4107 4108 u8 counter_set_id[0x8]; 4109 u8 atomic_mode[0x4]; 4110 u8 rre[0x1]; 4111 u8 rwe[0x1]; 4112 u8 rae[0x1]; 4113 u8 atomic_like_write_en[0x1]; 4114 u8 latency_sensitive[0x1]; 4115 u8 rlky[0x1]; 4116 u8 free_ar[0x1]; 4117 u8 reserved_at_73[0xd]; 4118 4119 u8 reserved_at_80[0x8]; 4120 u8 cs_res[0x8]; 4121 u8 reserved_at_90[0x3]; 4122 u8 min_rnr_nak[0x5]; 4123 u8 reserved_at_98[0x8]; 4124 4125 u8 reserved_at_a0[0x8]; 4126 u8 srqn_xrqn[0x18]; 4127 4128 u8 reserved_at_c0[0x8]; 4129 u8 pd[0x18]; 4130 4131 u8 tclass[0x8]; 4132 u8 reserved_at_e8[0x4]; 4133 u8 flow_label[0x14]; 4134 4135 u8 dc_access_key[0x40]; 4136 4137 u8 reserved_at_140[0x5]; 4138 u8 mtu[0x3]; 4139 u8 port[0x8]; 4140 u8 pkey_index[0x10]; 4141 4142 u8 reserved_at_160[0x8]; 4143 u8 my_addr_index[0x8]; 4144 u8 reserved_at_170[0x8]; 4145 u8 hop_limit[0x8]; 4146 4147 u8 dc_access_key_violation_count[0x20]; 4148 4149 u8 reserved_at_1a0[0x14]; 4150 u8 dei_cfi[0x1]; 4151 u8 eth_prio[0x3]; 4152 u8 ecn[0x2]; 4153 u8 dscp[0x6]; 4154 4155 u8 reserved_at_1c0[0x20]; 4156 u8 ece[0x20]; 4157 }; 4158 4159 enum { 4160 MLX5_CQC_STATUS_OK = 0x0, 4161 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4162 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4163 }; 4164 4165 enum { 4166 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4167 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4168 }; 4169 4170 enum { 4171 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4172 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4173 MLX5_CQC_ST_FIRED = 0xa, 4174 }; 4175 4176 enum { 4177 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4178 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4179 MLX5_CQ_PERIOD_NUM_MODES 4180 }; 4181 4182 struct mlx5_ifc_cqc_bits { 4183 u8 status[0x4]; 4184 u8 reserved_at_4[0x2]; 4185 u8 dbr_umem_valid[0x1]; 4186 u8 apu_cq[0x1]; 4187 u8 cqe_sz[0x3]; 4188 u8 cc[0x1]; 4189 u8 reserved_at_c[0x1]; 4190 u8 scqe_break_moderation_en[0x1]; 4191 u8 oi[0x1]; 4192 u8 cq_period_mode[0x2]; 4193 u8 cqe_comp_en[0x1]; 4194 u8 mini_cqe_res_format[0x2]; 4195 u8 st[0x4]; 4196 u8 reserved_at_18[0x6]; 4197 u8 cqe_compression_layout[0x2]; 4198 4199 u8 reserved_at_20[0x20]; 4200 4201 u8 reserved_at_40[0x14]; 4202 u8 page_offset[0x6]; 4203 u8 reserved_at_5a[0x6]; 4204 4205 u8 reserved_at_60[0x3]; 4206 u8 log_cq_size[0x5]; 4207 u8 uar_page[0x18]; 4208 4209 u8 reserved_at_80[0x4]; 4210 u8 cq_period[0xc]; 4211 u8 cq_max_count[0x10]; 4212 4213 u8 c_eqn_or_apu_element[0x20]; 4214 4215 u8 reserved_at_c0[0x3]; 4216 u8 log_page_size[0x5]; 4217 u8 reserved_at_c8[0x18]; 4218 4219 u8 reserved_at_e0[0x20]; 4220 4221 u8 reserved_at_100[0x8]; 4222 u8 last_notified_index[0x18]; 4223 4224 u8 reserved_at_120[0x8]; 4225 u8 last_solicit_index[0x18]; 4226 4227 u8 reserved_at_140[0x8]; 4228 u8 consumer_counter[0x18]; 4229 4230 u8 reserved_at_160[0x8]; 4231 u8 producer_counter[0x18]; 4232 4233 u8 reserved_at_180[0x40]; 4234 4235 u8 dbr_addr[0x40]; 4236 }; 4237 4238 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4239 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4240 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4241 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4242 u8 reserved_at_0[0x800]; 4243 }; 4244 4245 struct mlx5_ifc_query_adapter_param_block_bits { 4246 u8 reserved_at_0[0xc0]; 4247 4248 u8 reserved_at_c0[0x8]; 4249 u8 ieee_vendor_id[0x18]; 4250 4251 u8 reserved_at_e0[0x10]; 4252 u8 vsd_vendor_id[0x10]; 4253 4254 u8 vsd[208][0x8]; 4255 4256 u8 vsd_contd_psid[16][0x8]; 4257 }; 4258 4259 enum { 4260 MLX5_XRQC_STATE_GOOD = 0x0, 4261 MLX5_XRQC_STATE_ERROR = 0x1, 4262 }; 4263 4264 enum { 4265 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4266 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4267 }; 4268 4269 enum { 4270 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4271 }; 4272 4273 struct mlx5_ifc_tag_matching_topology_context_bits { 4274 u8 log_matching_list_sz[0x4]; 4275 u8 reserved_at_4[0xc]; 4276 u8 append_next_index[0x10]; 4277 4278 u8 sw_phase_cnt[0x10]; 4279 u8 hw_phase_cnt[0x10]; 4280 4281 u8 reserved_at_40[0x40]; 4282 }; 4283 4284 struct mlx5_ifc_xrqc_bits { 4285 u8 state[0x4]; 4286 u8 rlkey[0x1]; 4287 u8 reserved_at_5[0xf]; 4288 u8 topology[0x4]; 4289 u8 reserved_at_18[0x4]; 4290 u8 offload[0x4]; 4291 4292 u8 reserved_at_20[0x8]; 4293 u8 user_index[0x18]; 4294 4295 u8 reserved_at_40[0x8]; 4296 u8 cqn[0x18]; 4297 4298 u8 reserved_at_60[0xa0]; 4299 4300 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4301 4302 u8 reserved_at_180[0x280]; 4303 4304 struct mlx5_ifc_wq_bits wq; 4305 }; 4306 4307 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4308 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4309 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4310 u8 reserved_at_0[0x20]; 4311 }; 4312 4313 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4314 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4315 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4316 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4317 u8 reserved_at_0[0x20]; 4318 }; 4319 4320 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4321 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4322 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4323 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4324 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4325 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4326 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4327 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4328 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4329 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4330 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4331 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4332 u8 reserved_at_0[0x7c0]; 4333 }; 4334 4335 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4336 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4337 u8 reserved_at_0[0x7c0]; 4338 }; 4339 4340 union mlx5_ifc_event_auto_bits { 4341 struct mlx5_ifc_comp_event_bits comp_event; 4342 struct mlx5_ifc_dct_events_bits dct_events; 4343 struct mlx5_ifc_qp_events_bits qp_events; 4344 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4345 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4346 struct mlx5_ifc_cq_error_bits cq_error; 4347 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4348 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4349 struct mlx5_ifc_gpio_event_bits gpio_event; 4350 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4351 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4352 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4353 u8 reserved_at_0[0xe0]; 4354 }; 4355 4356 struct mlx5_ifc_health_buffer_bits { 4357 u8 reserved_at_0[0x100]; 4358 4359 u8 assert_existptr[0x20]; 4360 4361 u8 assert_callra[0x20]; 4362 4363 u8 reserved_at_140[0x20]; 4364 4365 u8 time[0x20]; 4366 4367 u8 fw_version[0x20]; 4368 4369 u8 hw_id[0x20]; 4370 4371 u8 rfr[0x1]; 4372 u8 reserved_at_1c1[0x3]; 4373 u8 valid[0x1]; 4374 u8 severity[0x3]; 4375 u8 reserved_at_1c8[0x18]; 4376 4377 u8 irisc_index[0x8]; 4378 u8 synd[0x8]; 4379 u8 ext_synd[0x10]; 4380 }; 4381 4382 struct mlx5_ifc_register_loopback_control_bits { 4383 u8 no_lb[0x1]; 4384 u8 reserved_at_1[0x7]; 4385 u8 port[0x8]; 4386 u8 reserved_at_10[0x10]; 4387 4388 u8 reserved_at_20[0x60]; 4389 }; 4390 4391 struct mlx5_ifc_vport_tc_element_bits { 4392 u8 traffic_class[0x4]; 4393 u8 reserved_at_4[0xc]; 4394 u8 vport_number[0x10]; 4395 }; 4396 4397 struct mlx5_ifc_vport_element_bits { 4398 u8 reserved_at_0[0x10]; 4399 u8 vport_number[0x10]; 4400 }; 4401 4402 enum { 4403 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4404 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4405 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4406 }; 4407 4408 struct mlx5_ifc_tsar_element_bits { 4409 u8 reserved_at_0[0x8]; 4410 u8 tsar_type[0x8]; 4411 u8 reserved_at_10[0x10]; 4412 }; 4413 4414 enum { 4415 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4416 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4417 }; 4418 4419 struct mlx5_ifc_teardown_hca_out_bits { 4420 u8 status[0x8]; 4421 u8 reserved_at_8[0x18]; 4422 4423 u8 syndrome[0x20]; 4424 4425 u8 reserved_at_40[0x3f]; 4426 4427 u8 state[0x1]; 4428 }; 4429 4430 enum { 4431 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4432 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4433 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4434 }; 4435 4436 struct mlx5_ifc_teardown_hca_in_bits { 4437 u8 opcode[0x10]; 4438 u8 reserved_at_10[0x10]; 4439 4440 u8 reserved_at_20[0x10]; 4441 u8 op_mod[0x10]; 4442 4443 u8 reserved_at_40[0x10]; 4444 u8 profile[0x10]; 4445 4446 u8 reserved_at_60[0x20]; 4447 }; 4448 4449 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4450 u8 status[0x8]; 4451 u8 reserved_at_8[0x18]; 4452 4453 u8 syndrome[0x20]; 4454 4455 u8 reserved_at_40[0x40]; 4456 }; 4457 4458 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4459 u8 opcode[0x10]; 4460 u8 uid[0x10]; 4461 4462 u8 reserved_at_20[0x10]; 4463 u8 op_mod[0x10]; 4464 4465 u8 reserved_at_40[0x8]; 4466 u8 qpn[0x18]; 4467 4468 u8 reserved_at_60[0x20]; 4469 4470 u8 opt_param_mask[0x20]; 4471 4472 u8 reserved_at_a0[0x20]; 4473 4474 struct mlx5_ifc_qpc_bits qpc; 4475 4476 u8 reserved_at_800[0x80]; 4477 }; 4478 4479 struct mlx5_ifc_sqd2rts_qp_out_bits { 4480 u8 status[0x8]; 4481 u8 reserved_at_8[0x18]; 4482 4483 u8 syndrome[0x20]; 4484 4485 u8 reserved_at_40[0x40]; 4486 }; 4487 4488 struct mlx5_ifc_sqd2rts_qp_in_bits { 4489 u8 opcode[0x10]; 4490 u8 uid[0x10]; 4491 4492 u8 reserved_at_20[0x10]; 4493 u8 op_mod[0x10]; 4494 4495 u8 reserved_at_40[0x8]; 4496 u8 qpn[0x18]; 4497 4498 u8 reserved_at_60[0x20]; 4499 4500 u8 opt_param_mask[0x20]; 4501 4502 u8 reserved_at_a0[0x20]; 4503 4504 struct mlx5_ifc_qpc_bits qpc; 4505 4506 u8 reserved_at_800[0x80]; 4507 }; 4508 4509 struct mlx5_ifc_set_roce_address_out_bits { 4510 u8 status[0x8]; 4511 u8 reserved_at_8[0x18]; 4512 4513 u8 syndrome[0x20]; 4514 4515 u8 reserved_at_40[0x40]; 4516 }; 4517 4518 struct mlx5_ifc_set_roce_address_in_bits { 4519 u8 opcode[0x10]; 4520 u8 reserved_at_10[0x10]; 4521 4522 u8 reserved_at_20[0x10]; 4523 u8 op_mod[0x10]; 4524 4525 u8 roce_address_index[0x10]; 4526 u8 reserved_at_50[0xc]; 4527 u8 vhca_port_num[0x4]; 4528 4529 u8 reserved_at_60[0x20]; 4530 4531 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4532 }; 4533 4534 struct mlx5_ifc_set_mad_demux_out_bits { 4535 u8 status[0x8]; 4536 u8 reserved_at_8[0x18]; 4537 4538 u8 syndrome[0x20]; 4539 4540 u8 reserved_at_40[0x40]; 4541 }; 4542 4543 enum { 4544 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4545 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4546 }; 4547 4548 struct mlx5_ifc_set_mad_demux_in_bits { 4549 u8 opcode[0x10]; 4550 u8 reserved_at_10[0x10]; 4551 4552 u8 reserved_at_20[0x10]; 4553 u8 op_mod[0x10]; 4554 4555 u8 reserved_at_40[0x20]; 4556 4557 u8 reserved_at_60[0x6]; 4558 u8 demux_mode[0x2]; 4559 u8 reserved_at_68[0x18]; 4560 }; 4561 4562 struct mlx5_ifc_set_l2_table_entry_out_bits { 4563 u8 status[0x8]; 4564 u8 reserved_at_8[0x18]; 4565 4566 u8 syndrome[0x20]; 4567 4568 u8 reserved_at_40[0x40]; 4569 }; 4570 4571 struct mlx5_ifc_set_l2_table_entry_in_bits { 4572 u8 opcode[0x10]; 4573 u8 reserved_at_10[0x10]; 4574 4575 u8 reserved_at_20[0x10]; 4576 u8 op_mod[0x10]; 4577 4578 u8 reserved_at_40[0x60]; 4579 4580 u8 reserved_at_a0[0x8]; 4581 u8 table_index[0x18]; 4582 4583 u8 reserved_at_c0[0x20]; 4584 4585 u8 reserved_at_e0[0x13]; 4586 u8 vlan_valid[0x1]; 4587 u8 vlan[0xc]; 4588 4589 struct mlx5_ifc_mac_address_layout_bits mac_address; 4590 4591 u8 reserved_at_140[0xc0]; 4592 }; 4593 4594 struct mlx5_ifc_set_issi_out_bits { 4595 u8 status[0x8]; 4596 u8 reserved_at_8[0x18]; 4597 4598 u8 syndrome[0x20]; 4599 4600 u8 reserved_at_40[0x40]; 4601 }; 4602 4603 struct mlx5_ifc_set_issi_in_bits { 4604 u8 opcode[0x10]; 4605 u8 reserved_at_10[0x10]; 4606 4607 u8 reserved_at_20[0x10]; 4608 u8 op_mod[0x10]; 4609 4610 u8 reserved_at_40[0x10]; 4611 u8 current_issi[0x10]; 4612 4613 u8 reserved_at_60[0x20]; 4614 }; 4615 4616 struct mlx5_ifc_set_hca_cap_out_bits { 4617 u8 status[0x8]; 4618 u8 reserved_at_8[0x18]; 4619 4620 u8 syndrome[0x20]; 4621 4622 u8 reserved_at_40[0x40]; 4623 }; 4624 4625 struct mlx5_ifc_set_hca_cap_in_bits { 4626 u8 opcode[0x10]; 4627 u8 reserved_at_10[0x10]; 4628 4629 u8 reserved_at_20[0x10]; 4630 u8 op_mod[0x10]; 4631 4632 u8 other_function[0x1]; 4633 u8 reserved_at_41[0xf]; 4634 u8 function_id[0x10]; 4635 4636 u8 reserved_at_60[0x20]; 4637 4638 union mlx5_ifc_hca_cap_union_bits capability; 4639 }; 4640 4641 enum { 4642 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4643 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4644 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4645 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4646 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4647 }; 4648 4649 struct mlx5_ifc_set_fte_out_bits { 4650 u8 status[0x8]; 4651 u8 reserved_at_8[0x18]; 4652 4653 u8 syndrome[0x20]; 4654 4655 u8 reserved_at_40[0x40]; 4656 }; 4657 4658 struct mlx5_ifc_set_fte_in_bits { 4659 u8 opcode[0x10]; 4660 u8 reserved_at_10[0x10]; 4661 4662 u8 reserved_at_20[0x10]; 4663 u8 op_mod[0x10]; 4664 4665 u8 other_vport[0x1]; 4666 u8 reserved_at_41[0xf]; 4667 u8 vport_number[0x10]; 4668 4669 u8 reserved_at_60[0x20]; 4670 4671 u8 table_type[0x8]; 4672 u8 reserved_at_88[0x18]; 4673 4674 u8 reserved_at_a0[0x8]; 4675 u8 table_id[0x18]; 4676 4677 u8 ignore_flow_level[0x1]; 4678 u8 reserved_at_c1[0x17]; 4679 u8 modify_enable_mask[0x8]; 4680 4681 u8 reserved_at_e0[0x20]; 4682 4683 u8 flow_index[0x20]; 4684 4685 u8 reserved_at_120[0xe0]; 4686 4687 struct mlx5_ifc_flow_context_bits flow_context; 4688 }; 4689 4690 struct mlx5_ifc_rts2rts_qp_out_bits { 4691 u8 status[0x8]; 4692 u8 reserved_at_8[0x18]; 4693 4694 u8 syndrome[0x20]; 4695 4696 u8 reserved_at_40[0x20]; 4697 u8 ece[0x20]; 4698 }; 4699 4700 struct mlx5_ifc_rts2rts_qp_in_bits { 4701 u8 opcode[0x10]; 4702 u8 uid[0x10]; 4703 4704 u8 reserved_at_20[0x10]; 4705 u8 op_mod[0x10]; 4706 4707 u8 reserved_at_40[0x8]; 4708 u8 qpn[0x18]; 4709 4710 u8 reserved_at_60[0x20]; 4711 4712 u8 opt_param_mask[0x20]; 4713 4714 u8 ece[0x20]; 4715 4716 struct mlx5_ifc_qpc_bits qpc; 4717 4718 u8 reserved_at_800[0x80]; 4719 }; 4720 4721 struct mlx5_ifc_rtr2rts_qp_out_bits { 4722 u8 status[0x8]; 4723 u8 reserved_at_8[0x18]; 4724 4725 u8 syndrome[0x20]; 4726 4727 u8 reserved_at_40[0x20]; 4728 u8 ece[0x20]; 4729 }; 4730 4731 struct mlx5_ifc_rtr2rts_qp_in_bits { 4732 u8 opcode[0x10]; 4733 u8 uid[0x10]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 op_mod[0x10]; 4737 4738 u8 reserved_at_40[0x8]; 4739 u8 qpn[0x18]; 4740 4741 u8 reserved_at_60[0x20]; 4742 4743 u8 opt_param_mask[0x20]; 4744 4745 u8 ece[0x20]; 4746 4747 struct mlx5_ifc_qpc_bits qpc; 4748 4749 u8 reserved_at_800[0x80]; 4750 }; 4751 4752 struct mlx5_ifc_rst2init_qp_out_bits { 4753 u8 status[0x8]; 4754 u8 reserved_at_8[0x18]; 4755 4756 u8 syndrome[0x20]; 4757 4758 u8 reserved_at_40[0x20]; 4759 u8 ece[0x20]; 4760 }; 4761 4762 struct mlx5_ifc_rst2init_qp_in_bits { 4763 u8 opcode[0x10]; 4764 u8 uid[0x10]; 4765 4766 u8 reserved_at_20[0x10]; 4767 u8 op_mod[0x10]; 4768 4769 u8 reserved_at_40[0x8]; 4770 u8 qpn[0x18]; 4771 4772 u8 reserved_at_60[0x20]; 4773 4774 u8 opt_param_mask[0x20]; 4775 4776 u8 ece[0x20]; 4777 4778 struct mlx5_ifc_qpc_bits qpc; 4779 4780 u8 reserved_at_800[0x80]; 4781 }; 4782 4783 struct mlx5_ifc_query_xrq_out_bits { 4784 u8 status[0x8]; 4785 u8 reserved_at_8[0x18]; 4786 4787 u8 syndrome[0x20]; 4788 4789 u8 reserved_at_40[0x40]; 4790 4791 struct mlx5_ifc_xrqc_bits xrq_context; 4792 }; 4793 4794 struct mlx5_ifc_query_xrq_in_bits { 4795 u8 opcode[0x10]; 4796 u8 reserved_at_10[0x10]; 4797 4798 u8 reserved_at_20[0x10]; 4799 u8 op_mod[0x10]; 4800 4801 u8 reserved_at_40[0x8]; 4802 u8 xrqn[0x18]; 4803 4804 u8 reserved_at_60[0x20]; 4805 }; 4806 4807 struct mlx5_ifc_query_xrc_srq_out_bits { 4808 u8 status[0x8]; 4809 u8 reserved_at_8[0x18]; 4810 4811 u8 syndrome[0x20]; 4812 4813 u8 reserved_at_40[0x40]; 4814 4815 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4816 4817 u8 reserved_at_280[0x600]; 4818 4819 u8 pas[][0x40]; 4820 }; 4821 4822 struct mlx5_ifc_query_xrc_srq_in_bits { 4823 u8 opcode[0x10]; 4824 u8 reserved_at_10[0x10]; 4825 4826 u8 reserved_at_20[0x10]; 4827 u8 op_mod[0x10]; 4828 4829 u8 reserved_at_40[0x8]; 4830 u8 xrc_srqn[0x18]; 4831 4832 u8 reserved_at_60[0x20]; 4833 }; 4834 4835 enum { 4836 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4837 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4838 }; 4839 4840 struct mlx5_ifc_query_vport_state_out_bits { 4841 u8 status[0x8]; 4842 u8 reserved_at_8[0x18]; 4843 4844 u8 syndrome[0x20]; 4845 4846 u8 reserved_at_40[0x20]; 4847 4848 u8 reserved_at_60[0x18]; 4849 u8 admin_state[0x4]; 4850 u8 state[0x4]; 4851 }; 4852 4853 enum { 4854 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4855 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4856 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4857 }; 4858 4859 struct mlx5_ifc_arm_monitor_counter_in_bits { 4860 u8 opcode[0x10]; 4861 u8 uid[0x10]; 4862 4863 u8 reserved_at_20[0x10]; 4864 u8 op_mod[0x10]; 4865 4866 u8 reserved_at_40[0x20]; 4867 4868 u8 reserved_at_60[0x20]; 4869 }; 4870 4871 struct mlx5_ifc_arm_monitor_counter_out_bits { 4872 u8 status[0x8]; 4873 u8 reserved_at_8[0x18]; 4874 4875 u8 syndrome[0x20]; 4876 4877 u8 reserved_at_40[0x40]; 4878 }; 4879 4880 enum { 4881 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4882 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4883 }; 4884 4885 enum mlx5_monitor_counter_ppcnt { 4886 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4887 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4888 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4889 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4890 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4891 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4892 }; 4893 4894 enum { 4895 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4896 }; 4897 4898 struct mlx5_ifc_monitor_counter_output_bits { 4899 u8 reserved_at_0[0x4]; 4900 u8 type[0x4]; 4901 u8 reserved_at_8[0x8]; 4902 u8 counter[0x10]; 4903 4904 u8 counter_group_id[0x20]; 4905 }; 4906 4907 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4908 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4909 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4910 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4911 4912 struct mlx5_ifc_set_monitor_counter_in_bits { 4913 u8 opcode[0x10]; 4914 u8 uid[0x10]; 4915 4916 u8 reserved_at_20[0x10]; 4917 u8 op_mod[0x10]; 4918 4919 u8 reserved_at_40[0x10]; 4920 u8 num_of_counters[0x10]; 4921 4922 u8 reserved_at_60[0x20]; 4923 4924 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4925 }; 4926 4927 struct mlx5_ifc_set_monitor_counter_out_bits { 4928 u8 status[0x8]; 4929 u8 reserved_at_8[0x18]; 4930 4931 u8 syndrome[0x20]; 4932 4933 u8 reserved_at_40[0x40]; 4934 }; 4935 4936 struct mlx5_ifc_query_vport_state_in_bits { 4937 u8 opcode[0x10]; 4938 u8 reserved_at_10[0x10]; 4939 4940 u8 reserved_at_20[0x10]; 4941 u8 op_mod[0x10]; 4942 4943 u8 other_vport[0x1]; 4944 u8 reserved_at_41[0xf]; 4945 u8 vport_number[0x10]; 4946 4947 u8 reserved_at_60[0x20]; 4948 }; 4949 4950 struct mlx5_ifc_query_vnic_env_out_bits { 4951 u8 status[0x8]; 4952 u8 reserved_at_8[0x18]; 4953 4954 u8 syndrome[0x20]; 4955 4956 u8 reserved_at_40[0x40]; 4957 4958 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4959 }; 4960 4961 enum { 4962 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4963 }; 4964 4965 struct mlx5_ifc_query_vnic_env_in_bits { 4966 u8 opcode[0x10]; 4967 u8 reserved_at_10[0x10]; 4968 4969 u8 reserved_at_20[0x10]; 4970 u8 op_mod[0x10]; 4971 4972 u8 other_vport[0x1]; 4973 u8 reserved_at_41[0xf]; 4974 u8 vport_number[0x10]; 4975 4976 u8 reserved_at_60[0x20]; 4977 }; 4978 4979 struct mlx5_ifc_query_vport_counter_out_bits { 4980 u8 status[0x8]; 4981 u8 reserved_at_8[0x18]; 4982 4983 u8 syndrome[0x20]; 4984 4985 u8 reserved_at_40[0x40]; 4986 4987 struct mlx5_ifc_traffic_counter_bits received_errors; 4988 4989 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4990 4991 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4992 4993 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4994 4995 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4996 4997 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4998 4999 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5000 5001 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5002 5003 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5004 5005 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5006 5007 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5008 5009 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5010 5011 u8 reserved_at_680[0xa00]; 5012 }; 5013 5014 enum { 5015 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5016 }; 5017 5018 struct mlx5_ifc_query_vport_counter_in_bits { 5019 u8 opcode[0x10]; 5020 u8 reserved_at_10[0x10]; 5021 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 other_vport[0x1]; 5026 u8 reserved_at_41[0xb]; 5027 u8 port_num[0x4]; 5028 u8 vport_number[0x10]; 5029 5030 u8 reserved_at_60[0x60]; 5031 5032 u8 clear[0x1]; 5033 u8 reserved_at_c1[0x1f]; 5034 5035 u8 reserved_at_e0[0x20]; 5036 }; 5037 5038 struct mlx5_ifc_query_tis_out_bits { 5039 u8 status[0x8]; 5040 u8 reserved_at_8[0x18]; 5041 5042 u8 syndrome[0x20]; 5043 5044 u8 reserved_at_40[0x40]; 5045 5046 struct mlx5_ifc_tisc_bits tis_context; 5047 }; 5048 5049 struct mlx5_ifc_query_tis_in_bits { 5050 u8 opcode[0x10]; 5051 u8 reserved_at_10[0x10]; 5052 5053 u8 reserved_at_20[0x10]; 5054 u8 op_mod[0x10]; 5055 5056 u8 reserved_at_40[0x8]; 5057 u8 tisn[0x18]; 5058 5059 u8 reserved_at_60[0x20]; 5060 }; 5061 5062 struct mlx5_ifc_query_tir_out_bits { 5063 u8 status[0x8]; 5064 u8 reserved_at_8[0x18]; 5065 5066 u8 syndrome[0x20]; 5067 5068 u8 reserved_at_40[0xc0]; 5069 5070 struct mlx5_ifc_tirc_bits tir_context; 5071 }; 5072 5073 struct mlx5_ifc_query_tir_in_bits { 5074 u8 opcode[0x10]; 5075 u8 reserved_at_10[0x10]; 5076 5077 u8 reserved_at_20[0x10]; 5078 u8 op_mod[0x10]; 5079 5080 u8 reserved_at_40[0x8]; 5081 u8 tirn[0x18]; 5082 5083 u8 reserved_at_60[0x20]; 5084 }; 5085 5086 struct mlx5_ifc_query_srq_out_bits { 5087 u8 status[0x8]; 5088 u8 reserved_at_8[0x18]; 5089 5090 u8 syndrome[0x20]; 5091 5092 u8 reserved_at_40[0x40]; 5093 5094 struct mlx5_ifc_srqc_bits srq_context_entry; 5095 5096 u8 reserved_at_280[0x600]; 5097 5098 u8 pas[][0x40]; 5099 }; 5100 5101 struct mlx5_ifc_query_srq_in_bits { 5102 u8 opcode[0x10]; 5103 u8 reserved_at_10[0x10]; 5104 5105 u8 reserved_at_20[0x10]; 5106 u8 op_mod[0x10]; 5107 5108 u8 reserved_at_40[0x8]; 5109 u8 srqn[0x18]; 5110 5111 u8 reserved_at_60[0x20]; 5112 }; 5113 5114 struct mlx5_ifc_query_sq_out_bits { 5115 u8 status[0x8]; 5116 u8 reserved_at_8[0x18]; 5117 5118 u8 syndrome[0x20]; 5119 5120 u8 reserved_at_40[0xc0]; 5121 5122 struct mlx5_ifc_sqc_bits sq_context; 5123 }; 5124 5125 struct mlx5_ifc_query_sq_in_bits { 5126 u8 opcode[0x10]; 5127 u8 reserved_at_10[0x10]; 5128 5129 u8 reserved_at_20[0x10]; 5130 u8 op_mod[0x10]; 5131 5132 u8 reserved_at_40[0x8]; 5133 u8 sqn[0x18]; 5134 5135 u8 reserved_at_60[0x20]; 5136 }; 5137 5138 struct mlx5_ifc_query_special_contexts_out_bits { 5139 u8 status[0x8]; 5140 u8 reserved_at_8[0x18]; 5141 5142 u8 syndrome[0x20]; 5143 5144 u8 dump_fill_mkey[0x20]; 5145 5146 u8 resd_lkey[0x20]; 5147 5148 u8 null_mkey[0x20]; 5149 5150 u8 reserved_at_a0[0x60]; 5151 }; 5152 5153 struct mlx5_ifc_query_special_contexts_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 reserved_at_40[0x40]; 5161 }; 5162 5163 struct mlx5_ifc_query_scheduling_element_out_bits { 5164 u8 opcode[0x10]; 5165 u8 reserved_at_10[0x10]; 5166 5167 u8 reserved_at_20[0x10]; 5168 u8 op_mod[0x10]; 5169 5170 u8 reserved_at_40[0xc0]; 5171 5172 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5173 5174 u8 reserved_at_300[0x100]; 5175 }; 5176 5177 enum { 5178 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5179 SCHEDULING_HIERARCHY_NIC = 0x3, 5180 }; 5181 5182 struct mlx5_ifc_query_scheduling_element_in_bits { 5183 u8 opcode[0x10]; 5184 u8 reserved_at_10[0x10]; 5185 5186 u8 reserved_at_20[0x10]; 5187 u8 op_mod[0x10]; 5188 5189 u8 scheduling_hierarchy[0x8]; 5190 u8 reserved_at_48[0x18]; 5191 5192 u8 scheduling_element_id[0x20]; 5193 5194 u8 reserved_at_80[0x180]; 5195 }; 5196 5197 struct mlx5_ifc_query_rqt_out_bits { 5198 u8 status[0x8]; 5199 u8 reserved_at_8[0x18]; 5200 5201 u8 syndrome[0x20]; 5202 5203 u8 reserved_at_40[0xc0]; 5204 5205 struct mlx5_ifc_rqtc_bits rqt_context; 5206 }; 5207 5208 struct mlx5_ifc_query_rqt_in_bits { 5209 u8 opcode[0x10]; 5210 u8 reserved_at_10[0x10]; 5211 5212 u8 reserved_at_20[0x10]; 5213 u8 op_mod[0x10]; 5214 5215 u8 reserved_at_40[0x8]; 5216 u8 rqtn[0x18]; 5217 5218 u8 reserved_at_60[0x20]; 5219 }; 5220 5221 struct mlx5_ifc_query_rq_out_bits { 5222 u8 status[0x8]; 5223 u8 reserved_at_8[0x18]; 5224 5225 u8 syndrome[0x20]; 5226 5227 u8 reserved_at_40[0xc0]; 5228 5229 struct mlx5_ifc_rqc_bits rq_context; 5230 }; 5231 5232 struct mlx5_ifc_query_rq_in_bits { 5233 u8 opcode[0x10]; 5234 u8 reserved_at_10[0x10]; 5235 5236 u8 reserved_at_20[0x10]; 5237 u8 op_mod[0x10]; 5238 5239 u8 reserved_at_40[0x8]; 5240 u8 rqn[0x18]; 5241 5242 u8 reserved_at_60[0x20]; 5243 }; 5244 5245 struct mlx5_ifc_query_roce_address_out_bits { 5246 u8 status[0x8]; 5247 u8 reserved_at_8[0x18]; 5248 5249 u8 syndrome[0x20]; 5250 5251 u8 reserved_at_40[0x40]; 5252 5253 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5254 }; 5255 5256 struct mlx5_ifc_query_roce_address_in_bits { 5257 u8 opcode[0x10]; 5258 u8 reserved_at_10[0x10]; 5259 5260 u8 reserved_at_20[0x10]; 5261 u8 op_mod[0x10]; 5262 5263 u8 roce_address_index[0x10]; 5264 u8 reserved_at_50[0xc]; 5265 u8 vhca_port_num[0x4]; 5266 5267 u8 reserved_at_60[0x20]; 5268 }; 5269 5270 struct mlx5_ifc_query_rmp_out_bits { 5271 u8 status[0x8]; 5272 u8 reserved_at_8[0x18]; 5273 5274 u8 syndrome[0x20]; 5275 5276 u8 reserved_at_40[0xc0]; 5277 5278 struct mlx5_ifc_rmpc_bits rmp_context; 5279 }; 5280 5281 struct mlx5_ifc_query_rmp_in_bits { 5282 u8 opcode[0x10]; 5283 u8 reserved_at_10[0x10]; 5284 5285 u8 reserved_at_20[0x10]; 5286 u8 op_mod[0x10]; 5287 5288 u8 reserved_at_40[0x8]; 5289 u8 rmpn[0x18]; 5290 5291 u8 reserved_at_60[0x20]; 5292 }; 5293 5294 struct mlx5_ifc_query_qp_out_bits { 5295 u8 status[0x8]; 5296 u8 reserved_at_8[0x18]; 5297 5298 u8 syndrome[0x20]; 5299 5300 u8 reserved_at_40[0x40]; 5301 5302 u8 opt_param_mask[0x20]; 5303 5304 u8 ece[0x20]; 5305 5306 struct mlx5_ifc_qpc_bits qpc; 5307 5308 u8 reserved_at_800[0x80]; 5309 5310 u8 pas[][0x40]; 5311 }; 5312 5313 struct mlx5_ifc_query_qp_in_bits { 5314 u8 opcode[0x10]; 5315 u8 reserved_at_10[0x10]; 5316 5317 u8 reserved_at_20[0x10]; 5318 u8 op_mod[0x10]; 5319 5320 u8 reserved_at_40[0x8]; 5321 u8 qpn[0x18]; 5322 5323 u8 reserved_at_60[0x20]; 5324 }; 5325 5326 struct mlx5_ifc_query_q_counter_out_bits { 5327 u8 status[0x8]; 5328 u8 reserved_at_8[0x18]; 5329 5330 u8 syndrome[0x20]; 5331 5332 u8 reserved_at_40[0x40]; 5333 5334 u8 rx_write_requests[0x20]; 5335 5336 u8 reserved_at_a0[0x20]; 5337 5338 u8 rx_read_requests[0x20]; 5339 5340 u8 reserved_at_e0[0x20]; 5341 5342 u8 rx_atomic_requests[0x20]; 5343 5344 u8 reserved_at_120[0x20]; 5345 5346 u8 rx_dct_connect[0x20]; 5347 5348 u8 reserved_at_160[0x20]; 5349 5350 u8 out_of_buffer[0x20]; 5351 5352 u8 reserved_at_1a0[0x20]; 5353 5354 u8 out_of_sequence[0x20]; 5355 5356 u8 reserved_at_1e0[0x20]; 5357 5358 u8 duplicate_request[0x20]; 5359 5360 u8 reserved_at_220[0x20]; 5361 5362 u8 rnr_nak_retry_err[0x20]; 5363 5364 u8 reserved_at_260[0x20]; 5365 5366 u8 packet_seq_err[0x20]; 5367 5368 u8 reserved_at_2a0[0x20]; 5369 5370 u8 implied_nak_seq_err[0x20]; 5371 5372 u8 reserved_at_2e0[0x20]; 5373 5374 u8 local_ack_timeout_err[0x20]; 5375 5376 u8 reserved_at_320[0xa0]; 5377 5378 u8 resp_local_length_error[0x20]; 5379 5380 u8 req_local_length_error[0x20]; 5381 5382 u8 resp_local_qp_error[0x20]; 5383 5384 u8 local_operation_error[0x20]; 5385 5386 u8 resp_local_protection[0x20]; 5387 5388 u8 req_local_protection[0x20]; 5389 5390 u8 resp_cqe_error[0x20]; 5391 5392 u8 req_cqe_error[0x20]; 5393 5394 u8 req_mw_binding[0x20]; 5395 5396 u8 req_bad_response[0x20]; 5397 5398 u8 req_remote_invalid_request[0x20]; 5399 5400 u8 resp_remote_invalid_request[0x20]; 5401 5402 u8 req_remote_access_errors[0x20]; 5403 5404 u8 resp_remote_access_errors[0x20]; 5405 5406 u8 req_remote_operation_errors[0x20]; 5407 5408 u8 req_transport_retries_exceeded[0x20]; 5409 5410 u8 cq_overflow[0x20]; 5411 5412 u8 resp_cqe_flush_error[0x20]; 5413 5414 u8 req_cqe_flush_error[0x20]; 5415 5416 u8 reserved_at_620[0x20]; 5417 5418 u8 roce_adp_retrans[0x20]; 5419 5420 u8 roce_adp_retrans_to[0x20]; 5421 5422 u8 roce_slow_restart[0x20]; 5423 5424 u8 roce_slow_restart_cnps[0x20]; 5425 5426 u8 roce_slow_restart_trans[0x20]; 5427 5428 u8 reserved_at_6e0[0x120]; 5429 }; 5430 5431 struct mlx5_ifc_query_q_counter_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_at_10[0x10]; 5434 5435 u8 reserved_at_20[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 reserved_at_40[0x80]; 5439 5440 u8 clear[0x1]; 5441 u8 reserved_at_c1[0x1f]; 5442 5443 u8 reserved_at_e0[0x18]; 5444 u8 counter_set_id[0x8]; 5445 }; 5446 5447 struct mlx5_ifc_query_pages_out_bits { 5448 u8 status[0x8]; 5449 u8 reserved_at_8[0x18]; 5450 5451 u8 syndrome[0x20]; 5452 5453 u8 embedded_cpu_function[0x1]; 5454 u8 reserved_at_41[0xf]; 5455 u8 function_id[0x10]; 5456 5457 u8 num_pages[0x20]; 5458 }; 5459 5460 enum { 5461 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5462 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5463 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5464 }; 5465 5466 struct mlx5_ifc_query_pages_in_bits { 5467 u8 opcode[0x10]; 5468 u8 reserved_at_10[0x10]; 5469 5470 u8 reserved_at_20[0x10]; 5471 u8 op_mod[0x10]; 5472 5473 u8 embedded_cpu_function[0x1]; 5474 u8 reserved_at_41[0xf]; 5475 u8 function_id[0x10]; 5476 5477 u8 reserved_at_60[0x20]; 5478 }; 5479 5480 struct mlx5_ifc_query_nic_vport_context_out_bits { 5481 u8 status[0x8]; 5482 u8 reserved_at_8[0x18]; 5483 5484 u8 syndrome[0x20]; 5485 5486 u8 reserved_at_40[0x40]; 5487 5488 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5489 }; 5490 5491 struct mlx5_ifc_query_nic_vport_context_in_bits { 5492 u8 opcode[0x10]; 5493 u8 reserved_at_10[0x10]; 5494 5495 u8 reserved_at_20[0x10]; 5496 u8 op_mod[0x10]; 5497 5498 u8 other_vport[0x1]; 5499 u8 reserved_at_41[0xf]; 5500 u8 vport_number[0x10]; 5501 5502 u8 reserved_at_60[0x5]; 5503 u8 allowed_list_type[0x3]; 5504 u8 reserved_at_68[0x18]; 5505 }; 5506 5507 struct mlx5_ifc_query_mkey_out_bits { 5508 u8 status[0x8]; 5509 u8 reserved_at_8[0x18]; 5510 5511 u8 syndrome[0x20]; 5512 5513 u8 reserved_at_40[0x40]; 5514 5515 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5516 5517 u8 reserved_at_280[0x600]; 5518 5519 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5520 5521 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5522 }; 5523 5524 struct mlx5_ifc_query_mkey_in_bits { 5525 u8 opcode[0x10]; 5526 u8 reserved_at_10[0x10]; 5527 5528 u8 reserved_at_20[0x10]; 5529 u8 op_mod[0x10]; 5530 5531 u8 reserved_at_40[0x8]; 5532 u8 mkey_index[0x18]; 5533 5534 u8 pg_access[0x1]; 5535 u8 reserved_at_61[0x1f]; 5536 }; 5537 5538 struct mlx5_ifc_query_mad_demux_out_bits { 5539 u8 status[0x8]; 5540 u8 reserved_at_8[0x18]; 5541 5542 u8 syndrome[0x20]; 5543 5544 u8 reserved_at_40[0x40]; 5545 5546 u8 mad_dumux_parameters_block[0x20]; 5547 }; 5548 5549 struct mlx5_ifc_query_mad_demux_in_bits { 5550 u8 opcode[0x10]; 5551 u8 reserved_at_10[0x10]; 5552 5553 u8 reserved_at_20[0x10]; 5554 u8 op_mod[0x10]; 5555 5556 u8 reserved_at_40[0x40]; 5557 }; 5558 5559 struct mlx5_ifc_query_l2_table_entry_out_bits { 5560 u8 status[0x8]; 5561 u8 reserved_at_8[0x18]; 5562 5563 u8 syndrome[0x20]; 5564 5565 u8 reserved_at_40[0xa0]; 5566 5567 u8 reserved_at_e0[0x13]; 5568 u8 vlan_valid[0x1]; 5569 u8 vlan[0xc]; 5570 5571 struct mlx5_ifc_mac_address_layout_bits mac_address; 5572 5573 u8 reserved_at_140[0xc0]; 5574 }; 5575 5576 struct mlx5_ifc_query_l2_table_entry_in_bits { 5577 u8 opcode[0x10]; 5578 u8 reserved_at_10[0x10]; 5579 5580 u8 reserved_at_20[0x10]; 5581 u8 op_mod[0x10]; 5582 5583 u8 reserved_at_40[0x60]; 5584 5585 u8 reserved_at_a0[0x8]; 5586 u8 table_index[0x18]; 5587 5588 u8 reserved_at_c0[0x140]; 5589 }; 5590 5591 struct mlx5_ifc_query_issi_out_bits { 5592 u8 status[0x8]; 5593 u8 reserved_at_8[0x18]; 5594 5595 u8 syndrome[0x20]; 5596 5597 u8 reserved_at_40[0x10]; 5598 u8 current_issi[0x10]; 5599 5600 u8 reserved_at_60[0xa0]; 5601 5602 u8 reserved_at_100[76][0x8]; 5603 u8 supported_issi_dw0[0x20]; 5604 }; 5605 5606 struct mlx5_ifc_query_issi_in_bits { 5607 u8 opcode[0x10]; 5608 u8 reserved_at_10[0x10]; 5609 5610 u8 reserved_at_20[0x10]; 5611 u8 op_mod[0x10]; 5612 5613 u8 reserved_at_40[0x40]; 5614 }; 5615 5616 struct mlx5_ifc_set_driver_version_out_bits { 5617 u8 status[0x8]; 5618 u8 reserved_0[0x18]; 5619 5620 u8 syndrome[0x20]; 5621 u8 reserved_1[0x40]; 5622 }; 5623 5624 struct mlx5_ifc_set_driver_version_in_bits { 5625 u8 opcode[0x10]; 5626 u8 reserved_0[0x10]; 5627 5628 u8 reserved_1[0x10]; 5629 u8 op_mod[0x10]; 5630 5631 u8 reserved_2[0x40]; 5632 u8 driver_version[64][0x8]; 5633 }; 5634 5635 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5636 u8 status[0x8]; 5637 u8 reserved_at_8[0x18]; 5638 5639 u8 syndrome[0x20]; 5640 5641 u8 reserved_at_40[0x40]; 5642 5643 struct mlx5_ifc_pkey_bits pkey[]; 5644 }; 5645 5646 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5647 u8 opcode[0x10]; 5648 u8 reserved_at_10[0x10]; 5649 5650 u8 reserved_at_20[0x10]; 5651 u8 op_mod[0x10]; 5652 5653 u8 other_vport[0x1]; 5654 u8 reserved_at_41[0xb]; 5655 u8 port_num[0x4]; 5656 u8 vport_number[0x10]; 5657 5658 u8 reserved_at_60[0x10]; 5659 u8 pkey_index[0x10]; 5660 }; 5661 5662 enum { 5663 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5664 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5665 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5666 }; 5667 5668 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5669 u8 status[0x8]; 5670 u8 reserved_at_8[0x18]; 5671 5672 u8 syndrome[0x20]; 5673 5674 u8 reserved_at_40[0x20]; 5675 5676 u8 gids_num[0x10]; 5677 u8 reserved_at_70[0x10]; 5678 5679 struct mlx5_ifc_array128_auto_bits gid[]; 5680 }; 5681 5682 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5683 u8 opcode[0x10]; 5684 u8 reserved_at_10[0x10]; 5685 5686 u8 reserved_at_20[0x10]; 5687 u8 op_mod[0x10]; 5688 5689 u8 other_vport[0x1]; 5690 u8 reserved_at_41[0xb]; 5691 u8 port_num[0x4]; 5692 u8 vport_number[0x10]; 5693 5694 u8 reserved_at_60[0x10]; 5695 u8 gid_index[0x10]; 5696 }; 5697 5698 struct mlx5_ifc_query_hca_vport_context_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_at_8[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_at_40[0x40]; 5705 5706 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5707 }; 5708 5709 struct mlx5_ifc_query_hca_vport_context_in_bits { 5710 u8 opcode[0x10]; 5711 u8 reserved_at_10[0x10]; 5712 5713 u8 reserved_at_20[0x10]; 5714 u8 op_mod[0x10]; 5715 5716 u8 other_vport[0x1]; 5717 u8 reserved_at_41[0xb]; 5718 u8 port_num[0x4]; 5719 u8 vport_number[0x10]; 5720 5721 u8 reserved_at_60[0x20]; 5722 }; 5723 5724 struct mlx5_ifc_query_hca_cap_out_bits { 5725 u8 status[0x8]; 5726 u8 reserved_at_8[0x18]; 5727 5728 u8 syndrome[0x20]; 5729 5730 u8 reserved_at_40[0x40]; 5731 5732 union mlx5_ifc_hca_cap_union_bits capability; 5733 }; 5734 5735 struct mlx5_ifc_query_hca_cap_in_bits { 5736 u8 opcode[0x10]; 5737 u8 reserved_at_10[0x10]; 5738 5739 u8 reserved_at_20[0x10]; 5740 u8 op_mod[0x10]; 5741 5742 u8 other_function[0x1]; 5743 u8 reserved_at_41[0xf]; 5744 u8 function_id[0x10]; 5745 5746 u8 reserved_at_60[0x20]; 5747 }; 5748 5749 struct mlx5_ifc_other_hca_cap_bits { 5750 u8 roce[0x1]; 5751 u8 reserved_at_1[0x27f]; 5752 }; 5753 5754 struct mlx5_ifc_query_other_hca_cap_out_bits { 5755 u8 status[0x8]; 5756 u8 reserved_at_8[0x18]; 5757 5758 u8 syndrome[0x20]; 5759 5760 u8 reserved_at_40[0x40]; 5761 5762 struct mlx5_ifc_other_hca_cap_bits other_capability; 5763 }; 5764 5765 struct mlx5_ifc_query_other_hca_cap_in_bits { 5766 u8 opcode[0x10]; 5767 u8 reserved_at_10[0x10]; 5768 5769 u8 reserved_at_20[0x10]; 5770 u8 op_mod[0x10]; 5771 5772 u8 reserved_at_40[0x10]; 5773 u8 function_id[0x10]; 5774 5775 u8 reserved_at_60[0x20]; 5776 }; 5777 5778 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5779 u8 status[0x8]; 5780 u8 reserved_at_8[0x18]; 5781 5782 u8 syndrome[0x20]; 5783 5784 u8 reserved_at_40[0x40]; 5785 }; 5786 5787 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5788 u8 opcode[0x10]; 5789 u8 reserved_at_10[0x10]; 5790 5791 u8 reserved_at_20[0x10]; 5792 u8 op_mod[0x10]; 5793 5794 u8 reserved_at_40[0x10]; 5795 u8 function_id[0x10]; 5796 u8 field_select[0x20]; 5797 5798 struct mlx5_ifc_other_hca_cap_bits other_capability; 5799 }; 5800 5801 struct mlx5_ifc_flow_table_context_bits { 5802 u8 reformat_en[0x1]; 5803 u8 decap_en[0x1]; 5804 u8 sw_owner[0x1]; 5805 u8 termination_table[0x1]; 5806 u8 table_miss_action[0x4]; 5807 u8 level[0x8]; 5808 u8 reserved_at_10[0x8]; 5809 u8 log_size[0x8]; 5810 5811 u8 reserved_at_20[0x8]; 5812 u8 table_miss_id[0x18]; 5813 5814 u8 reserved_at_40[0x8]; 5815 u8 lag_master_next_table_id[0x18]; 5816 5817 u8 reserved_at_60[0x60]; 5818 5819 u8 sw_owner_icm_root_1[0x40]; 5820 5821 u8 sw_owner_icm_root_0[0x40]; 5822 5823 }; 5824 5825 struct mlx5_ifc_query_flow_table_out_bits { 5826 u8 status[0x8]; 5827 u8 reserved_at_8[0x18]; 5828 5829 u8 syndrome[0x20]; 5830 5831 u8 reserved_at_40[0x80]; 5832 5833 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5834 }; 5835 5836 struct mlx5_ifc_query_flow_table_in_bits { 5837 u8 opcode[0x10]; 5838 u8 reserved_at_10[0x10]; 5839 5840 u8 reserved_at_20[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 reserved_at_40[0x40]; 5844 5845 u8 table_type[0x8]; 5846 u8 reserved_at_88[0x18]; 5847 5848 u8 reserved_at_a0[0x8]; 5849 u8 table_id[0x18]; 5850 5851 u8 reserved_at_c0[0x140]; 5852 }; 5853 5854 struct mlx5_ifc_query_fte_out_bits { 5855 u8 status[0x8]; 5856 u8 reserved_at_8[0x18]; 5857 5858 u8 syndrome[0x20]; 5859 5860 u8 reserved_at_40[0x1c0]; 5861 5862 struct mlx5_ifc_flow_context_bits flow_context; 5863 }; 5864 5865 struct mlx5_ifc_query_fte_in_bits { 5866 u8 opcode[0x10]; 5867 u8 reserved_at_10[0x10]; 5868 5869 u8 reserved_at_20[0x10]; 5870 u8 op_mod[0x10]; 5871 5872 u8 reserved_at_40[0x40]; 5873 5874 u8 table_type[0x8]; 5875 u8 reserved_at_88[0x18]; 5876 5877 u8 reserved_at_a0[0x8]; 5878 u8 table_id[0x18]; 5879 5880 u8 reserved_at_c0[0x40]; 5881 5882 u8 flow_index[0x20]; 5883 5884 u8 reserved_at_120[0xe0]; 5885 }; 5886 5887 struct mlx5_ifc_match_definer_format_0_bits { 5888 u8 reserved_at_0[0x100]; 5889 5890 u8 metadata_reg_c_0[0x20]; 5891 5892 u8 metadata_reg_c_1[0x20]; 5893 5894 u8 outer_dmac_47_16[0x20]; 5895 5896 u8 outer_dmac_15_0[0x10]; 5897 u8 outer_ethertype[0x10]; 5898 5899 u8 reserved_at_180[0x1]; 5900 u8 sx_sniffer[0x1]; 5901 u8 functional_lb[0x1]; 5902 u8 outer_ip_frag[0x1]; 5903 u8 outer_qp_type[0x2]; 5904 u8 outer_encap_type[0x2]; 5905 u8 port_number[0x2]; 5906 u8 outer_l3_type[0x2]; 5907 u8 outer_l4_type[0x2]; 5908 u8 outer_first_vlan_type[0x2]; 5909 u8 outer_first_vlan_prio[0x3]; 5910 u8 outer_first_vlan_cfi[0x1]; 5911 u8 outer_first_vlan_vid[0xc]; 5912 5913 u8 outer_l4_type_ext[0x4]; 5914 u8 reserved_at_1a4[0x2]; 5915 u8 outer_ipsec_layer[0x2]; 5916 u8 outer_l2_type[0x2]; 5917 u8 force_lb[0x1]; 5918 u8 outer_l2_ok[0x1]; 5919 u8 outer_l3_ok[0x1]; 5920 u8 outer_l4_ok[0x1]; 5921 u8 outer_second_vlan_type[0x2]; 5922 u8 outer_second_vlan_prio[0x3]; 5923 u8 outer_second_vlan_cfi[0x1]; 5924 u8 outer_second_vlan_vid[0xc]; 5925 5926 u8 outer_smac_47_16[0x20]; 5927 5928 u8 outer_smac_15_0[0x10]; 5929 u8 inner_ipv4_checksum_ok[0x1]; 5930 u8 inner_l4_checksum_ok[0x1]; 5931 u8 outer_ipv4_checksum_ok[0x1]; 5932 u8 outer_l4_checksum_ok[0x1]; 5933 u8 inner_l3_ok[0x1]; 5934 u8 inner_l4_ok[0x1]; 5935 u8 outer_l3_ok_duplicate[0x1]; 5936 u8 outer_l4_ok_duplicate[0x1]; 5937 u8 outer_tcp_cwr[0x1]; 5938 u8 outer_tcp_ece[0x1]; 5939 u8 outer_tcp_urg[0x1]; 5940 u8 outer_tcp_ack[0x1]; 5941 u8 outer_tcp_psh[0x1]; 5942 u8 outer_tcp_rst[0x1]; 5943 u8 outer_tcp_syn[0x1]; 5944 u8 outer_tcp_fin[0x1]; 5945 }; 5946 5947 struct mlx5_ifc_match_definer_format_22_bits { 5948 u8 reserved_at_0[0x100]; 5949 5950 u8 outer_ip_src_addr[0x20]; 5951 5952 u8 outer_ip_dest_addr[0x20]; 5953 5954 u8 outer_l4_sport[0x10]; 5955 u8 outer_l4_dport[0x10]; 5956 5957 u8 reserved_at_160[0x1]; 5958 u8 sx_sniffer[0x1]; 5959 u8 functional_lb[0x1]; 5960 u8 outer_ip_frag[0x1]; 5961 u8 outer_qp_type[0x2]; 5962 u8 outer_encap_type[0x2]; 5963 u8 port_number[0x2]; 5964 u8 outer_l3_type[0x2]; 5965 u8 outer_l4_type[0x2]; 5966 u8 outer_first_vlan_type[0x2]; 5967 u8 outer_first_vlan_prio[0x3]; 5968 u8 outer_first_vlan_cfi[0x1]; 5969 u8 outer_first_vlan_vid[0xc]; 5970 5971 u8 metadata_reg_c_0[0x20]; 5972 5973 u8 outer_dmac_47_16[0x20]; 5974 5975 u8 outer_smac_47_16[0x20]; 5976 5977 u8 outer_smac_15_0[0x10]; 5978 u8 outer_dmac_15_0[0x10]; 5979 }; 5980 5981 struct mlx5_ifc_match_definer_format_23_bits { 5982 u8 reserved_at_0[0x100]; 5983 5984 u8 inner_ip_src_addr[0x20]; 5985 5986 u8 inner_ip_dest_addr[0x20]; 5987 5988 u8 inner_l4_sport[0x10]; 5989 u8 inner_l4_dport[0x10]; 5990 5991 u8 reserved_at_160[0x1]; 5992 u8 sx_sniffer[0x1]; 5993 u8 functional_lb[0x1]; 5994 u8 inner_ip_frag[0x1]; 5995 u8 inner_qp_type[0x2]; 5996 u8 inner_encap_type[0x2]; 5997 u8 port_number[0x2]; 5998 u8 inner_l3_type[0x2]; 5999 u8 inner_l4_type[0x2]; 6000 u8 inner_first_vlan_type[0x2]; 6001 u8 inner_first_vlan_prio[0x3]; 6002 u8 inner_first_vlan_cfi[0x1]; 6003 u8 inner_first_vlan_vid[0xc]; 6004 6005 u8 tunnel_header_0[0x20]; 6006 6007 u8 inner_dmac_47_16[0x20]; 6008 6009 u8 inner_smac_47_16[0x20]; 6010 6011 u8 inner_smac_15_0[0x10]; 6012 u8 inner_dmac_15_0[0x10]; 6013 }; 6014 6015 struct mlx5_ifc_match_definer_format_29_bits { 6016 u8 reserved_at_0[0xc0]; 6017 6018 u8 outer_ip_dest_addr[0x80]; 6019 6020 u8 outer_ip_src_addr[0x80]; 6021 6022 u8 outer_l4_sport[0x10]; 6023 u8 outer_l4_dport[0x10]; 6024 6025 u8 reserved_at_1e0[0x20]; 6026 }; 6027 6028 struct mlx5_ifc_match_definer_format_30_bits { 6029 u8 reserved_at_0[0xa0]; 6030 6031 u8 outer_ip_dest_addr[0x80]; 6032 6033 u8 outer_ip_src_addr[0x80]; 6034 6035 u8 outer_dmac_47_16[0x20]; 6036 6037 u8 outer_smac_47_16[0x20]; 6038 6039 u8 outer_smac_15_0[0x10]; 6040 u8 outer_dmac_15_0[0x10]; 6041 }; 6042 6043 struct mlx5_ifc_match_definer_format_31_bits { 6044 u8 reserved_at_0[0xc0]; 6045 6046 u8 inner_ip_dest_addr[0x80]; 6047 6048 u8 inner_ip_src_addr[0x80]; 6049 6050 u8 inner_l4_sport[0x10]; 6051 u8 inner_l4_dport[0x10]; 6052 6053 u8 reserved_at_1e0[0x20]; 6054 }; 6055 6056 struct mlx5_ifc_match_definer_format_32_bits { 6057 u8 reserved_at_0[0xa0]; 6058 6059 u8 inner_ip_dest_addr[0x80]; 6060 6061 u8 inner_ip_src_addr[0x80]; 6062 6063 u8 inner_dmac_47_16[0x20]; 6064 6065 u8 inner_smac_47_16[0x20]; 6066 6067 u8 inner_smac_15_0[0x10]; 6068 u8 inner_dmac_15_0[0x10]; 6069 }; 6070 6071 struct mlx5_ifc_match_definer_bits { 6072 u8 modify_field_select[0x40]; 6073 6074 u8 reserved_at_40[0x40]; 6075 6076 u8 reserved_at_80[0x10]; 6077 u8 format_id[0x10]; 6078 6079 u8 reserved_at_a0[0x160]; 6080 6081 u8 match_mask[16][0x20]; 6082 }; 6083 6084 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6085 u8 opcode[0x10]; 6086 u8 uid[0x10]; 6087 6088 u8 vhca_tunnel_id[0x10]; 6089 u8 obj_type[0x10]; 6090 6091 u8 obj_id[0x20]; 6092 6093 u8 reserved_at_60[0x3]; 6094 u8 log_obj_range[0x5]; 6095 u8 reserved_at_68[0x18]; 6096 }; 6097 6098 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6099 u8 status[0x8]; 6100 u8 reserved_at_8[0x18]; 6101 6102 u8 syndrome[0x20]; 6103 6104 u8 obj_id[0x20]; 6105 6106 u8 reserved_at_60[0x20]; 6107 }; 6108 6109 struct mlx5_ifc_create_match_definer_in_bits { 6110 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6111 6112 struct mlx5_ifc_match_definer_bits obj_context; 6113 }; 6114 6115 struct mlx5_ifc_create_match_definer_out_bits { 6116 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6117 }; 6118 6119 enum { 6120 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6121 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6122 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6123 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6124 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6125 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6126 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6127 }; 6128 6129 struct mlx5_ifc_query_flow_group_out_bits { 6130 u8 status[0x8]; 6131 u8 reserved_at_8[0x18]; 6132 6133 u8 syndrome[0x20]; 6134 6135 u8 reserved_at_40[0xa0]; 6136 6137 u8 start_flow_index[0x20]; 6138 6139 u8 reserved_at_100[0x20]; 6140 6141 u8 end_flow_index[0x20]; 6142 6143 u8 reserved_at_140[0xa0]; 6144 6145 u8 reserved_at_1e0[0x18]; 6146 u8 match_criteria_enable[0x8]; 6147 6148 struct mlx5_ifc_fte_match_param_bits match_criteria; 6149 6150 u8 reserved_at_1200[0xe00]; 6151 }; 6152 6153 struct mlx5_ifc_query_flow_group_in_bits { 6154 u8 opcode[0x10]; 6155 u8 reserved_at_10[0x10]; 6156 6157 u8 reserved_at_20[0x10]; 6158 u8 op_mod[0x10]; 6159 6160 u8 reserved_at_40[0x40]; 6161 6162 u8 table_type[0x8]; 6163 u8 reserved_at_88[0x18]; 6164 6165 u8 reserved_at_a0[0x8]; 6166 u8 table_id[0x18]; 6167 6168 u8 group_id[0x20]; 6169 6170 u8 reserved_at_e0[0x120]; 6171 }; 6172 6173 struct mlx5_ifc_query_flow_counter_out_bits { 6174 u8 status[0x8]; 6175 u8 reserved_at_8[0x18]; 6176 6177 u8 syndrome[0x20]; 6178 6179 u8 reserved_at_40[0x40]; 6180 6181 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6182 }; 6183 6184 struct mlx5_ifc_query_flow_counter_in_bits { 6185 u8 opcode[0x10]; 6186 u8 reserved_at_10[0x10]; 6187 6188 u8 reserved_at_20[0x10]; 6189 u8 op_mod[0x10]; 6190 6191 u8 reserved_at_40[0x80]; 6192 6193 u8 clear[0x1]; 6194 u8 reserved_at_c1[0xf]; 6195 u8 num_of_counters[0x10]; 6196 6197 u8 flow_counter_id[0x20]; 6198 }; 6199 6200 struct mlx5_ifc_query_esw_vport_context_out_bits { 6201 u8 status[0x8]; 6202 u8 reserved_at_8[0x18]; 6203 6204 u8 syndrome[0x20]; 6205 6206 u8 reserved_at_40[0x40]; 6207 6208 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6209 }; 6210 6211 struct mlx5_ifc_query_esw_vport_context_in_bits { 6212 u8 opcode[0x10]; 6213 u8 reserved_at_10[0x10]; 6214 6215 u8 reserved_at_20[0x10]; 6216 u8 op_mod[0x10]; 6217 6218 u8 other_vport[0x1]; 6219 u8 reserved_at_41[0xf]; 6220 u8 vport_number[0x10]; 6221 6222 u8 reserved_at_60[0x20]; 6223 }; 6224 6225 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6226 u8 status[0x8]; 6227 u8 reserved_at_8[0x18]; 6228 6229 u8 syndrome[0x20]; 6230 6231 u8 reserved_at_40[0x40]; 6232 }; 6233 6234 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6235 u8 reserved_at_0[0x1b]; 6236 u8 fdb_to_vport_reg_c_id[0x1]; 6237 u8 vport_cvlan_insert[0x1]; 6238 u8 vport_svlan_insert[0x1]; 6239 u8 vport_cvlan_strip[0x1]; 6240 u8 vport_svlan_strip[0x1]; 6241 }; 6242 6243 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6244 u8 opcode[0x10]; 6245 u8 reserved_at_10[0x10]; 6246 6247 u8 reserved_at_20[0x10]; 6248 u8 op_mod[0x10]; 6249 6250 u8 other_vport[0x1]; 6251 u8 reserved_at_41[0xf]; 6252 u8 vport_number[0x10]; 6253 6254 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6255 6256 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6257 }; 6258 6259 struct mlx5_ifc_query_eq_out_bits { 6260 u8 status[0x8]; 6261 u8 reserved_at_8[0x18]; 6262 6263 u8 syndrome[0x20]; 6264 6265 u8 reserved_at_40[0x40]; 6266 6267 struct mlx5_ifc_eqc_bits eq_context_entry; 6268 6269 u8 reserved_at_280[0x40]; 6270 6271 u8 event_bitmask[0x40]; 6272 6273 u8 reserved_at_300[0x580]; 6274 6275 u8 pas[][0x40]; 6276 }; 6277 6278 struct mlx5_ifc_query_eq_in_bits { 6279 u8 opcode[0x10]; 6280 u8 reserved_at_10[0x10]; 6281 6282 u8 reserved_at_20[0x10]; 6283 u8 op_mod[0x10]; 6284 6285 u8 reserved_at_40[0x18]; 6286 u8 eq_number[0x8]; 6287 6288 u8 reserved_at_60[0x20]; 6289 }; 6290 6291 struct mlx5_ifc_packet_reformat_context_in_bits { 6292 u8 reformat_type[0x8]; 6293 u8 reserved_at_8[0x4]; 6294 u8 reformat_param_0[0x4]; 6295 u8 reserved_at_10[0x6]; 6296 u8 reformat_data_size[0xa]; 6297 6298 u8 reformat_param_1[0x8]; 6299 u8 reserved_at_28[0x8]; 6300 u8 reformat_data[2][0x8]; 6301 6302 u8 more_reformat_data[][0x8]; 6303 }; 6304 6305 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6306 u8 status[0x8]; 6307 u8 reserved_at_8[0x18]; 6308 6309 u8 syndrome[0x20]; 6310 6311 u8 reserved_at_40[0xa0]; 6312 6313 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6314 }; 6315 6316 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6317 u8 opcode[0x10]; 6318 u8 reserved_at_10[0x10]; 6319 6320 u8 reserved_at_20[0x10]; 6321 u8 op_mod[0x10]; 6322 6323 u8 packet_reformat_id[0x20]; 6324 6325 u8 reserved_at_60[0xa0]; 6326 }; 6327 6328 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6329 u8 status[0x8]; 6330 u8 reserved_at_8[0x18]; 6331 6332 u8 syndrome[0x20]; 6333 6334 u8 packet_reformat_id[0x20]; 6335 6336 u8 reserved_at_60[0x20]; 6337 }; 6338 6339 enum { 6340 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6341 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6342 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6343 }; 6344 6345 enum mlx5_reformat_ctx_type { 6346 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6347 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6348 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6349 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6350 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6351 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6352 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6353 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6354 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6355 }; 6356 6357 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6358 u8 opcode[0x10]; 6359 u8 reserved_at_10[0x10]; 6360 6361 u8 reserved_at_20[0x10]; 6362 u8 op_mod[0x10]; 6363 6364 u8 reserved_at_40[0xa0]; 6365 6366 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6367 }; 6368 6369 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6370 u8 status[0x8]; 6371 u8 reserved_at_8[0x18]; 6372 6373 u8 syndrome[0x20]; 6374 6375 u8 reserved_at_40[0x40]; 6376 }; 6377 6378 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6379 u8 opcode[0x10]; 6380 u8 reserved_at_10[0x10]; 6381 6382 u8 reserved_20[0x10]; 6383 u8 op_mod[0x10]; 6384 6385 u8 packet_reformat_id[0x20]; 6386 6387 u8 reserved_60[0x20]; 6388 }; 6389 6390 struct mlx5_ifc_set_action_in_bits { 6391 u8 action_type[0x4]; 6392 u8 field[0xc]; 6393 u8 reserved_at_10[0x3]; 6394 u8 offset[0x5]; 6395 u8 reserved_at_18[0x3]; 6396 u8 length[0x5]; 6397 6398 u8 data[0x20]; 6399 }; 6400 6401 struct mlx5_ifc_add_action_in_bits { 6402 u8 action_type[0x4]; 6403 u8 field[0xc]; 6404 u8 reserved_at_10[0x10]; 6405 6406 u8 data[0x20]; 6407 }; 6408 6409 struct mlx5_ifc_copy_action_in_bits { 6410 u8 action_type[0x4]; 6411 u8 src_field[0xc]; 6412 u8 reserved_at_10[0x3]; 6413 u8 src_offset[0x5]; 6414 u8 reserved_at_18[0x3]; 6415 u8 length[0x5]; 6416 6417 u8 reserved_at_20[0x4]; 6418 u8 dst_field[0xc]; 6419 u8 reserved_at_30[0x3]; 6420 u8 dst_offset[0x5]; 6421 u8 reserved_at_38[0x8]; 6422 }; 6423 6424 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6425 struct mlx5_ifc_set_action_in_bits set_action_in; 6426 struct mlx5_ifc_add_action_in_bits add_action_in; 6427 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6428 u8 reserved_at_0[0x40]; 6429 }; 6430 6431 enum { 6432 MLX5_ACTION_TYPE_SET = 0x1, 6433 MLX5_ACTION_TYPE_ADD = 0x2, 6434 MLX5_ACTION_TYPE_COPY = 0x3, 6435 }; 6436 6437 enum { 6438 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6439 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6440 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6441 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6442 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6443 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6444 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6445 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6446 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6447 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6448 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6449 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6450 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6451 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6452 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6453 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6454 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6455 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6456 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6457 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6458 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6459 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6460 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6461 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6462 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6463 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6464 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6465 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6466 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6467 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6468 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6469 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6470 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6471 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6472 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6473 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6474 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6475 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6476 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6477 }; 6478 6479 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6480 u8 status[0x8]; 6481 u8 reserved_at_8[0x18]; 6482 6483 u8 syndrome[0x20]; 6484 6485 u8 modify_header_id[0x20]; 6486 6487 u8 reserved_at_60[0x20]; 6488 }; 6489 6490 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6491 u8 opcode[0x10]; 6492 u8 reserved_at_10[0x10]; 6493 6494 u8 reserved_at_20[0x10]; 6495 u8 op_mod[0x10]; 6496 6497 u8 reserved_at_40[0x20]; 6498 6499 u8 table_type[0x8]; 6500 u8 reserved_at_68[0x10]; 6501 u8 num_of_actions[0x8]; 6502 6503 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6504 }; 6505 6506 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6507 u8 status[0x8]; 6508 u8 reserved_at_8[0x18]; 6509 6510 u8 syndrome[0x20]; 6511 6512 u8 reserved_at_40[0x40]; 6513 }; 6514 6515 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6516 u8 opcode[0x10]; 6517 u8 reserved_at_10[0x10]; 6518 6519 u8 reserved_at_20[0x10]; 6520 u8 op_mod[0x10]; 6521 6522 u8 modify_header_id[0x20]; 6523 6524 u8 reserved_at_60[0x20]; 6525 }; 6526 6527 struct mlx5_ifc_query_modify_header_context_in_bits { 6528 u8 opcode[0x10]; 6529 u8 uid[0x10]; 6530 6531 u8 reserved_at_20[0x10]; 6532 u8 op_mod[0x10]; 6533 6534 u8 modify_header_id[0x20]; 6535 6536 u8 reserved_at_60[0xa0]; 6537 }; 6538 6539 struct mlx5_ifc_query_dct_out_bits { 6540 u8 status[0x8]; 6541 u8 reserved_at_8[0x18]; 6542 6543 u8 syndrome[0x20]; 6544 6545 u8 reserved_at_40[0x40]; 6546 6547 struct mlx5_ifc_dctc_bits dct_context_entry; 6548 6549 u8 reserved_at_280[0x180]; 6550 }; 6551 6552 struct mlx5_ifc_query_dct_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_at_10[0x10]; 6555 6556 u8 reserved_at_20[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 reserved_at_40[0x8]; 6560 u8 dctn[0x18]; 6561 6562 u8 reserved_at_60[0x20]; 6563 }; 6564 6565 struct mlx5_ifc_query_cq_out_bits { 6566 u8 status[0x8]; 6567 u8 reserved_at_8[0x18]; 6568 6569 u8 syndrome[0x20]; 6570 6571 u8 reserved_at_40[0x40]; 6572 6573 struct mlx5_ifc_cqc_bits cq_context; 6574 6575 u8 reserved_at_280[0x600]; 6576 6577 u8 pas[][0x40]; 6578 }; 6579 6580 struct mlx5_ifc_query_cq_in_bits { 6581 u8 opcode[0x10]; 6582 u8 reserved_at_10[0x10]; 6583 6584 u8 reserved_at_20[0x10]; 6585 u8 op_mod[0x10]; 6586 6587 u8 reserved_at_40[0x8]; 6588 u8 cqn[0x18]; 6589 6590 u8 reserved_at_60[0x20]; 6591 }; 6592 6593 struct mlx5_ifc_query_cong_status_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_at_8[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_at_40[0x20]; 6600 6601 u8 enable[0x1]; 6602 u8 tag_enable[0x1]; 6603 u8 reserved_at_62[0x1e]; 6604 }; 6605 6606 struct mlx5_ifc_query_cong_status_in_bits { 6607 u8 opcode[0x10]; 6608 u8 reserved_at_10[0x10]; 6609 6610 u8 reserved_at_20[0x10]; 6611 u8 op_mod[0x10]; 6612 6613 u8 reserved_at_40[0x18]; 6614 u8 priority[0x4]; 6615 u8 cong_protocol[0x4]; 6616 6617 u8 reserved_at_60[0x20]; 6618 }; 6619 6620 struct mlx5_ifc_query_cong_statistics_out_bits { 6621 u8 status[0x8]; 6622 u8 reserved_at_8[0x18]; 6623 6624 u8 syndrome[0x20]; 6625 6626 u8 reserved_at_40[0x40]; 6627 6628 u8 rp_cur_flows[0x20]; 6629 6630 u8 sum_flows[0x20]; 6631 6632 u8 rp_cnp_ignored_high[0x20]; 6633 6634 u8 rp_cnp_ignored_low[0x20]; 6635 6636 u8 rp_cnp_handled_high[0x20]; 6637 6638 u8 rp_cnp_handled_low[0x20]; 6639 6640 u8 reserved_at_140[0x100]; 6641 6642 u8 time_stamp_high[0x20]; 6643 6644 u8 time_stamp_low[0x20]; 6645 6646 u8 accumulators_period[0x20]; 6647 6648 u8 np_ecn_marked_roce_packets_high[0x20]; 6649 6650 u8 np_ecn_marked_roce_packets_low[0x20]; 6651 6652 u8 np_cnp_sent_high[0x20]; 6653 6654 u8 np_cnp_sent_low[0x20]; 6655 6656 u8 reserved_at_320[0x560]; 6657 }; 6658 6659 struct mlx5_ifc_query_cong_statistics_in_bits { 6660 u8 opcode[0x10]; 6661 u8 reserved_at_10[0x10]; 6662 6663 u8 reserved_at_20[0x10]; 6664 u8 op_mod[0x10]; 6665 6666 u8 clear[0x1]; 6667 u8 reserved_at_41[0x1f]; 6668 6669 u8 reserved_at_60[0x20]; 6670 }; 6671 6672 struct mlx5_ifc_query_cong_params_out_bits { 6673 u8 status[0x8]; 6674 u8 reserved_at_8[0x18]; 6675 6676 u8 syndrome[0x20]; 6677 6678 u8 reserved_at_40[0x40]; 6679 6680 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6681 }; 6682 6683 struct mlx5_ifc_query_cong_params_in_bits { 6684 u8 opcode[0x10]; 6685 u8 reserved_at_10[0x10]; 6686 6687 u8 reserved_at_20[0x10]; 6688 u8 op_mod[0x10]; 6689 6690 u8 reserved_at_40[0x1c]; 6691 u8 cong_protocol[0x4]; 6692 6693 u8 reserved_at_60[0x20]; 6694 }; 6695 6696 struct mlx5_ifc_query_adapter_out_bits { 6697 u8 status[0x8]; 6698 u8 reserved_at_8[0x18]; 6699 6700 u8 syndrome[0x20]; 6701 6702 u8 reserved_at_40[0x40]; 6703 6704 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6705 }; 6706 6707 struct mlx5_ifc_query_adapter_in_bits { 6708 u8 opcode[0x10]; 6709 u8 reserved_at_10[0x10]; 6710 6711 u8 reserved_at_20[0x10]; 6712 u8 op_mod[0x10]; 6713 6714 u8 reserved_at_40[0x40]; 6715 }; 6716 6717 struct mlx5_ifc_qp_2rst_out_bits { 6718 u8 status[0x8]; 6719 u8 reserved_at_8[0x18]; 6720 6721 u8 syndrome[0x20]; 6722 6723 u8 reserved_at_40[0x40]; 6724 }; 6725 6726 struct mlx5_ifc_qp_2rst_in_bits { 6727 u8 opcode[0x10]; 6728 u8 uid[0x10]; 6729 6730 u8 reserved_at_20[0x10]; 6731 u8 op_mod[0x10]; 6732 6733 u8 reserved_at_40[0x8]; 6734 u8 qpn[0x18]; 6735 6736 u8 reserved_at_60[0x20]; 6737 }; 6738 6739 struct mlx5_ifc_qp_2err_out_bits { 6740 u8 status[0x8]; 6741 u8 reserved_at_8[0x18]; 6742 6743 u8 syndrome[0x20]; 6744 6745 u8 reserved_at_40[0x40]; 6746 }; 6747 6748 struct mlx5_ifc_qp_2err_in_bits { 6749 u8 opcode[0x10]; 6750 u8 uid[0x10]; 6751 6752 u8 reserved_at_20[0x10]; 6753 u8 op_mod[0x10]; 6754 6755 u8 reserved_at_40[0x8]; 6756 u8 qpn[0x18]; 6757 6758 u8 reserved_at_60[0x20]; 6759 }; 6760 6761 struct mlx5_ifc_page_fault_resume_out_bits { 6762 u8 status[0x8]; 6763 u8 reserved_at_8[0x18]; 6764 6765 u8 syndrome[0x20]; 6766 6767 u8 reserved_at_40[0x40]; 6768 }; 6769 6770 struct mlx5_ifc_page_fault_resume_in_bits { 6771 u8 opcode[0x10]; 6772 u8 reserved_at_10[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 error[0x1]; 6778 u8 reserved_at_41[0x4]; 6779 u8 page_fault_type[0x3]; 6780 u8 wq_number[0x18]; 6781 6782 u8 reserved_at_60[0x8]; 6783 u8 token[0x18]; 6784 }; 6785 6786 struct mlx5_ifc_nop_out_bits { 6787 u8 status[0x8]; 6788 u8 reserved_at_8[0x18]; 6789 6790 u8 syndrome[0x20]; 6791 6792 u8 reserved_at_40[0x40]; 6793 }; 6794 6795 struct mlx5_ifc_nop_in_bits { 6796 u8 opcode[0x10]; 6797 u8 reserved_at_10[0x10]; 6798 6799 u8 reserved_at_20[0x10]; 6800 u8 op_mod[0x10]; 6801 6802 u8 reserved_at_40[0x40]; 6803 }; 6804 6805 struct mlx5_ifc_modify_vport_state_out_bits { 6806 u8 status[0x8]; 6807 u8 reserved_at_8[0x18]; 6808 6809 u8 syndrome[0x20]; 6810 6811 u8 reserved_at_40[0x40]; 6812 }; 6813 6814 struct mlx5_ifc_modify_vport_state_in_bits { 6815 u8 opcode[0x10]; 6816 u8 reserved_at_10[0x10]; 6817 6818 u8 reserved_at_20[0x10]; 6819 u8 op_mod[0x10]; 6820 6821 u8 other_vport[0x1]; 6822 u8 reserved_at_41[0xf]; 6823 u8 vport_number[0x10]; 6824 6825 u8 reserved_at_60[0x18]; 6826 u8 admin_state[0x4]; 6827 u8 reserved_at_7c[0x4]; 6828 }; 6829 6830 struct mlx5_ifc_modify_tis_out_bits { 6831 u8 status[0x8]; 6832 u8 reserved_at_8[0x18]; 6833 6834 u8 syndrome[0x20]; 6835 6836 u8 reserved_at_40[0x40]; 6837 }; 6838 6839 struct mlx5_ifc_modify_tis_bitmask_bits { 6840 u8 reserved_at_0[0x20]; 6841 6842 u8 reserved_at_20[0x1d]; 6843 u8 lag_tx_port_affinity[0x1]; 6844 u8 strict_lag_tx_port_affinity[0x1]; 6845 u8 prio[0x1]; 6846 }; 6847 6848 struct mlx5_ifc_modify_tis_in_bits { 6849 u8 opcode[0x10]; 6850 u8 uid[0x10]; 6851 6852 u8 reserved_at_20[0x10]; 6853 u8 op_mod[0x10]; 6854 6855 u8 reserved_at_40[0x8]; 6856 u8 tisn[0x18]; 6857 6858 u8 reserved_at_60[0x20]; 6859 6860 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6861 6862 u8 reserved_at_c0[0x40]; 6863 6864 struct mlx5_ifc_tisc_bits ctx; 6865 }; 6866 6867 struct mlx5_ifc_modify_tir_bitmask_bits { 6868 u8 reserved_at_0[0x20]; 6869 6870 u8 reserved_at_20[0x1b]; 6871 u8 self_lb_en[0x1]; 6872 u8 reserved_at_3c[0x1]; 6873 u8 hash[0x1]; 6874 u8 reserved_at_3e[0x1]; 6875 u8 packet_merge[0x1]; 6876 }; 6877 6878 struct mlx5_ifc_modify_tir_out_bits { 6879 u8 status[0x8]; 6880 u8 reserved_at_8[0x18]; 6881 6882 u8 syndrome[0x20]; 6883 6884 u8 reserved_at_40[0x40]; 6885 }; 6886 6887 struct mlx5_ifc_modify_tir_in_bits { 6888 u8 opcode[0x10]; 6889 u8 uid[0x10]; 6890 6891 u8 reserved_at_20[0x10]; 6892 u8 op_mod[0x10]; 6893 6894 u8 reserved_at_40[0x8]; 6895 u8 tirn[0x18]; 6896 6897 u8 reserved_at_60[0x20]; 6898 6899 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6900 6901 u8 reserved_at_c0[0x40]; 6902 6903 struct mlx5_ifc_tirc_bits ctx; 6904 }; 6905 6906 struct mlx5_ifc_modify_sq_out_bits { 6907 u8 status[0x8]; 6908 u8 reserved_at_8[0x18]; 6909 6910 u8 syndrome[0x20]; 6911 6912 u8 reserved_at_40[0x40]; 6913 }; 6914 6915 struct mlx5_ifc_modify_sq_in_bits { 6916 u8 opcode[0x10]; 6917 u8 uid[0x10]; 6918 6919 u8 reserved_at_20[0x10]; 6920 u8 op_mod[0x10]; 6921 6922 u8 sq_state[0x4]; 6923 u8 reserved_at_44[0x4]; 6924 u8 sqn[0x18]; 6925 6926 u8 reserved_at_60[0x20]; 6927 6928 u8 modify_bitmask[0x40]; 6929 6930 u8 reserved_at_c0[0x40]; 6931 6932 struct mlx5_ifc_sqc_bits ctx; 6933 }; 6934 6935 struct mlx5_ifc_modify_scheduling_element_out_bits { 6936 u8 status[0x8]; 6937 u8 reserved_at_8[0x18]; 6938 6939 u8 syndrome[0x20]; 6940 6941 u8 reserved_at_40[0x1c0]; 6942 }; 6943 6944 enum { 6945 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6946 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6947 }; 6948 6949 struct mlx5_ifc_modify_scheduling_element_in_bits { 6950 u8 opcode[0x10]; 6951 u8 reserved_at_10[0x10]; 6952 6953 u8 reserved_at_20[0x10]; 6954 u8 op_mod[0x10]; 6955 6956 u8 scheduling_hierarchy[0x8]; 6957 u8 reserved_at_48[0x18]; 6958 6959 u8 scheduling_element_id[0x20]; 6960 6961 u8 reserved_at_80[0x20]; 6962 6963 u8 modify_bitmask[0x20]; 6964 6965 u8 reserved_at_c0[0x40]; 6966 6967 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6968 6969 u8 reserved_at_300[0x100]; 6970 }; 6971 6972 struct mlx5_ifc_modify_rqt_out_bits { 6973 u8 status[0x8]; 6974 u8 reserved_at_8[0x18]; 6975 6976 u8 syndrome[0x20]; 6977 6978 u8 reserved_at_40[0x40]; 6979 }; 6980 6981 struct mlx5_ifc_rqt_bitmask_bits { 6982 u8 reserved_at_0[0x20]; 6983 6984 u8 reserved_at_20[0x1f]; 6985 u8 rqn_list[0x1]; 6986 }; 6987 6988 struct mlx5_ifc_modify_rqt_in_bits { 6989 u8 opcode[0x10]; 6990 u8 uid[0x10]; 6991 6992 u8 reserved_at_20[0x10]; 6993 u8 op_mod[0x10]; 6994 6995 u8 reserved_at_40[0x8]; 6996 u8 rqtn[0x18]; 6997 6998 u8 reserved_at_60[0x20]; 6999 7000 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7001 7002 u8 reserved_at_c0[0x40]; 7003 7004 struct mlx5_ifc_rqtc_bits ctx; 7005 }; 7006 7007 struct mlx5_ifc_modify_rq_out_bits { 7008 u8 status[0x8]; 7009 u8 reserved_at_8[0x18]; 7010 7011 u8 syndrome[0x20]; 7012 7013 u8 reserved_at_40[0x40]; 7014 }; 7015 7016 enum { 7017 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7018 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7019 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7020 }; 7021 7022 struct mlx5_ifc_modify_rq_in_bits { 7023 u8 opcode[0x10]; 7024 u8 uid[0x10]; 7025 7026 u8 reserved_at_20[0x10]; 7027 u8 op_mod[0x10]; 7028 7029 u8 rq_state[0x4]; 7030 u8 reserved_at_44[0x4]; 7031 u8 rqn[0x18]; 7032 7033 u8 reserved_at_60[0x20]; 7034 7035 u8 modify_bitmask[0x40]; 7036 7037 u8 reserved_at_c0[0x40]; 7038 7039 struct mlx5_ifc_rqc_bits ctx; 7040 }; 7041 7042 struct mlx5_ifc_modify_rmp_out_bits { 7043 u8 status[0x8]; 7044 u8 reserved_at_8[0x18]; 7045 7046 u8 syndrome[0x20]; 7047 7048 u8 reserved_at_40[0x40]; 7049 }; 7050 7051 struct mlx5_ifc_rmp_bitmask_bits { 7052 u8 reserved_at_0[0x20]; 7053 7054 u8 reserved_at_20[0x1f]; 7055 u8 lwm[0x1]; 7056 }; 7057 7058 struct mlx5_ifc_modify_rmp_in_bits { 7059 u8 opcode[0x10]; 7060 u8 uid[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 rmp_state[0x4]; 7066 u8 reserved_at_44[0x4]; 7067 u8 rmpn[0x18]; 7068 7069 u8 reserved_at_60[0x20]; 7070 7071 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7072 7073 u8 reserved_at_c0[0x40]; 7074 7075 struct mlx5_ifc_rmpc_bits ctx; 7076 }; 7077 7078 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7079 u8 status[0x8]; 7080 u8 reserved_at_8[0x18]; 7081 7082 u8 syndrome[0x20]; 7083 7084 u8 reserved_at_40[0x40]; 7085 }; 7086 7087 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7088 u8 reserved_at_0[0x12]; 7089 u8 affiliation[0x1]; 7090 u8 reserved_at_13[0x1]; 7091 u8 disable_uc_local_lb[0x1]; 7092 u8 disable_mc_local_lb[0x1]; 7093 u8 node_guid[0x1]; 7094 u8 port_guid[0x1]; 7095 u8 min_inline[0x1]; 7096 u8 mtu[0x1]; 7097 u8 change_event[0x1]; 7098 u8 promisc[0x1]; 7099 u8 permanent_address[0x1]; 7100 u8 addresses_list[0x1]; 7101 u8 roce_en[0x1]; 7102 u8 reserved_at_1f[0x1]; 7103 }; 7104 7105 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7106 u8 opcode[0x10]; 7107 u8 reserved_at_10[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 other_vport[0x1]; 7113 u8 reserved_at_41[0xf]; 7114 u8 vport_number[0x10]; 7115 7116 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7117 7118 u8 reserved_at_80[0x780]; 7119 7120 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7121 }; 7122 7123 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7124 u8 status[0x8]; 7125 u8 reserved_at_8[0x18]; 7126 7127 u8 syndrome[0x20]; 7128 7129 u8 reserved_at_40[0x40]; 7130 }; 7131 7132 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7133 u8 opcode[0x10]; 7134 u8 reserved_at_10[0x10]; 7135 7136 u8 reserved_at_20[0x10]; 7137 u8 op_mod[0x10]; 7138 7139 u8 other_vport[0x1]; 7140 u8 reserved_at_41[0xb]; 7141 u8 port_num[0x4]; 7142 u8 vport_number[0x10]; 7143 7144 u8 reserved_at_60[0x20]; 7145 7146 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7147 }; 7148 7149 struct mlx5_ifc_modify_cq_out_bits { 7150 u8 status[0x8]; 7151 u8 reserved_at_8[0x18]; 7152 7153 u8 syndrome[0x20]; 7154 7155 u8 reserved_at_40[0x40]; 7156 }; 7157 7158 enum { 7159 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7160 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7161 }; 7162 7163 struct mlx5_ifc_modify_cq_in_bits { 7164 u8 opcode[0x10]; 7165 u8 uid[0x10]; 7166 7167 u8 reserved_at_20[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_at_40[0x8]; 7171 u8 cqn[0x18]; 7172 7173 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7174 7175 struct mlx5_ifc_cqc_bits cq_context; 7176 7177 u8 reserved_at_280[0x60]; 7178 7179 u8 cq_umem_valid[0x1]; 7180 u8 reserved_at_2e1[0x1f]; 7181 7182 u8 reserved_at_300[0x580]; 7183 7184 u8 pas[][0x40]; 7185 }; 7186 7187 struct mlx5_ifc_modify_cong_status_out_bits { 7188 u8 status[0x8]; 7189 u8 reserved_at_8[0x18]; 7190 7191 u8 syndrome[0x20]; 7192 7193 u8 reserved_at_40[0x40]; 7194 }; 7195 7196 struct mlx5_ifc_modify_cong_status_in_bits { 7197 u8 opcode[0x10]; 7198 u8 reserved_at_10[0x10]; 7199 7200 u8 reserved_at_20[0x10]; 7201 u8 op_mod[0x10]; 7202 7203 u8 reserved_at_40[0x18]; 7204 u8 priority[0x4]; 7205 u8 cong_protocol[0x4]; 7206 7207 u8 enable[0x1]; 7208 u8 tag_enable[0x1]; 7209 u8 reserved_at_62[0x1e]; 7210 }; 7211 7212 struct mlx5_ifc_modify_cong_params_out_bits { 7213 u8 status[0x8]; 7214 u8 reserved_at_8[0x18]; 7215 7216 u8 syndrome[0x20]; 7217 7218 u8 reserved_at_40[0x40]; 7219 }; 7220 7221 struct mlx5_ifc_modify_cong_params_in_bits { 7222 u8 opcode[0x10]; 7223 u8 reserved_at_10[0x10]; 7224 7225 u8 reserved_at_20[0x10]; 7226 u8 op_mod[0x10]; 7227 7228 u8 reserved_at_40[0x1c]; 7229 u8 cong_protocol[0x4]; 7230 7231 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7232 7233 u8 reserved_at_80[0x80]; 7234 7235 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7236 }; 7237 7238 struct mlx5_ifc_manage_pages_out_bits { 7239 u8 status[0x8]; 7240 u8 reserved_at_8[0x18]; 7241 7242 u8 syndrome[0x20]; 7243 7244 u8 output_num_entries[0x20]; 7245 7246 u8 reserved_at_60[0x20]; 7247 7248 u8 pas[][0x40]; 7249 }; 7250 7251 enum { 7252 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7253 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7254 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7255 }; 7256 7257 struct mlx5_ifc_manage_pages_in_bits { 7258 u8 opcode[0x10]; 7259 u8 reserved_at_10[0x10]; 7260 7261 u8 reserved_at_20[0x10]; 7262 u8 op_mod[0x10]; 7263 7264 u8 embedded_cpu_function[0x1]; 7265 u8 reserved_at_41[0xf]; 7266 u8 function_id[0x10]; 7267 7268 u8 input_num_entries[0x20]; 7269 7270 u8 pas[][0x40]; 7271 }; 7272 7273 struct mlx5_ifc_mad_ifc_out_bits { 7274 u8 status[0x8]; 7275 u8 reserved_at_8[0x18]; 7276 7277 u8 syndrome[0x20]; 7278 7279 u8 reserved_at_40[0x40]; 7280 7281 u8 response_mad_packet[256][0x8]; 7282 }; 7283 7284 struct mlx5_ifc_mad_ifc_in_bits { 7285 u8 opcode[0x10]; 7286 u8 reserved_at_10[0x10]; 7287 7288 u8 reserved_at_20[0x10]; 7289 u8 op_mod[0x10]; 7290 7291 u8 remote_lid[0x10]; 7292 u8 reserved_at_50[0x8]; 7293 u8 port[0x8]; 7294 7295 u8 reserved_at_60[0x20]; 7296 7297 u8 mad[256][0x8]; 7298 }; 7299 7300 struct mlx5_ifc_init_hca_out_bits { 7301 u8 status[0x8]; 7302 u8 reserved_at_8[0x18]; 7303 7304 u8 syndrome[0x20]; 7305 7306 u8 reserved_at_40[0x40]; 7307 }; 7308 7309 struct mlx5_ifc_init_hca_in_bits { 7310 u8 opcode[0x10]; 7311 u8 reserved_at_10[0x10]; 7312 7313 u8 reserved_at_20[0x10]; 7314 u8 op_mod[0x10]; 7315 7316 u8 reserved_at_40[0x20]; 7317 7318 u8 reserved_at_60[0x2]; 7319 u8 sw_vhca_id[0xe]; 7320 u8 reserved_at_70[0x10]; 7321 7322 u8 sw_owner_id[4][0x20]; 7323 }; 7324 7325 struct mlx5_ifc_init2rtr_qp_out_bits { 7326 u8 status[0x8]; 7327 u8 reserved_at_8[0x18]; 7328 7329 u8 syndrome[0x20]; 7330 7331 u8 reserved_at_40[0x20]; 7332 u8 ece[0x20]; 7333 }; 7334 7335 struct mlx5_ifc_init2rtr_qp_in_bits { 7336 u8 opcode[0x10]; 7337 u8 uid[0x10]; 7338 7339 u8 reserved_at_20[0x10]; 7340 u8 op_mod[0x10]; 7341 7342 u8 reserved_at_40[0x8]; 7343 u8 qpn[0x18]; 7344 7345 u8 reserved_at_60[0x20]; 7346 7347 u8 opt_param_mask[0x20]; 7348 7349 u8 ece[0x20]; 7350 7351 struct mlx5_ifc_qpc_bits qpc; 7352 7353 u8 reserved_at_800[0x80]; 7354 }; 7355 7356 struct mlx5_ifc_init2init_qp_out_bits { 7357 u8 status[0x8]; 7358 u8 reserved_at_8[0x18]; 7359 7360 u8 syndrome[0x20]; 7361 7362 u8 reserved_at_40[0x20]; 7363 u8 ece[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_init2init_qp_in_bits { 7367 u8 opcode[0x10]; 7368 u8 uid[0x10]; 7369 7370 u8 reserved_at_20[0x10]; 7371 u8 op_mod[0x10]; 7372 7373 u8 reserved_at_40[0x8]; 7374 u8 qpn[0x18]; 7375 7376 u8 reserved_at_60[0x20]; 7377 7378 u8 opt_param_mask[0x20]; 7379 7380 u8 ece[0x20]; 7381 7382 struct mlx5_ifc_qpc_bits qpc; 7383 7384 u8 reserved_at_800[0x80]; 7385 }; 7386 7387 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7388 u8 status[0x8]; 7389 u8 reserved_at_8[0x18]; 7390 7391 u8 syndrome[0x20]; 7392 7393 u8 reserved_at_40[0x40]; 7394 7395 u8 packet_headers_log[128][0x8]; 7396 7397 u8 packet_syndrome[64][0x8]; 7398 }; 7399 7400 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7401 u8 opcode[0x10]; 7402 u8 reserved_at_10[0x10]; 7403 7404 u8 reserved_at_20[0x10]; 7405 u8 op_mod[0x10]; 7406 7407 u8 reserved_at_40[0x40]; 7408 }; 7409 7410 struct mlx5_ifc_gen_eqe_in_bits { 7411 u8 opcode[0x10]; 7412 u8 reserved_at_10[0x10]; 7413 7414 u8 reserved_at_20[0x10]; 7415 u8 op_mod[0x10]; 7416 7417 u8 reserved_at_40[0x18]; 7418 u8 eq_number[0x8]; 7419 7420 u8 reserved_at_60[0x20]; 7421 7422 u8 eqe[64][0x8]; 7423 }; 7424 7425 struct mlx5_ifc_gen_eq_out_bits { 7426 u8 status[0x8]; 7427 u8 reserved_at_8[0x18]; 7428 7429 u8 syndrome[0x20]; 7430 7431 u8 reserved_at_40[0x40]; 7432 }; 7433 7434 struct mlx5_ifc_enable_hca_out_bits { 7435 u8 status[0x8]; 7436 u8 reserved_at_8[0x18]; 7437 7438 u8 syndrome[0x20]; 7439 7440 u8 reserved_at_40[0x20]; 7441 }; 7442 7443 struct mlx5_ifc_enable_hca_in_bits { 7444 u8 opcode[0x10]; 7445 u8 reserved_at_10[0x10]; 7446 7447 u8 reserved_at_20[0x10]; 7448 u8 op_mod[0x10]; 7449 7450 u8 embedded_cpu_function[0x1]; 7451 u8 reserved_at_41[0xf]; 7452 u8 function_id[0x10]; 7453 7454 u8 reserved_at_60[0x20]; 7455 }; 7456 7457 struct mlx5_ifc_drain_dct_out_bits { 7458 u8 status[0x8]; 7459 u8 reserved_at_8[0x18]; 7460 7461 u8 syndrome[0x20]; 7462 7463 u8 reserved_at_40[0x40]; 7464 }; 7465 7466 struct mlx5_ifc_drain_dct_in_bits { 7467 u8 opcode[0x10]; 7468 u8 uid[0x10]; 7469 7470 u8 reserved_at_20[0x10]; 7471 u8 op_mod[0x10]; 7472 7473 u8 reserved_at_40[0x8]; 7474 u8 dctn[0x18]; 7475 7476 u8 reserved_at_60[0x20]; 7477 }; 7478 7479 struct mlx5_ifc_disable_hca_out_bits { 7480 u8 status[0x8]; 7481 u8 reserved_at_8[0x18]; 7482 7483 u8 syndrome[0x20]; 7484 7485 u8 reserved_at_40[0x20]; 7486 }; 7487 7488 struct mlx5_ifc_disable_hca_in_bits { 7489 u8 opcode[0x10]; 7490 u8 reserved_at_10[0x10]; 7491 7492 u8 reserved_at_20[0x10]; 7493 u8 op_mod[0x10]; 7494 7495 u8 embedded_cpu_function[0x1]; 7496 u8 reserved_at_41[0xf]; 7497 u8 function_id[0x10]; 7498 7499 u8 reserved_at_60[0x20]; 7500 }; 7501 7502 struct mlx5_ifc_detach_from_mcg_out_bits { 7503 u8 status[0x8]; 7504 u8 reserved_at_8[0x18]; 7505 7506 u8 syndrome[0x20]; 7507 7508 u8 reserved_at_40[0x40]; 7509 }; 7510 7511 struct mlx5_ifc_detach_from_mcg_in_bits { 7512 u8 opcode[0x10]; 7513 u8 uid[0x10]; 7514 7515 u8 reserved_at_20[0x10]; 7516 u8 op_mod[0x10]; 7517 7518 u8 reserved_at_40[0x8]; 7519 u8 qpn[0x18]; 7520 7521 u8 reserved_at_60[0x20]; 7522 7523 u8 multicast_gid[16][0x8]; 7524 }; 7525 7526 struct mlx5_ifc_destroy_xrq_out_bits { 7527 u8 status[0x8]; 7528 u8 reserved_at_8[0x18]; 7529 7530 u8 syndrome[0x20]; 7531 7532 u8 reserved_at_40[0x40]; 7533 }; 7534 7535 struct mlx5_ifc_destroy_xrq_in_bits { 7536 u8 opcode[0x10]; 7537 u8 uid[0x10]; 7538 7539 u8 reserved_at_20[0x10]; 7540 u8 op_mod[0x10]; 7541 7542 u8 reserved_at_40[0x8]; 7543 u8 xrqn[0x18]; 7544 7545 u8 reserved_at_60[0x20]; 7546 }; 7547 7548 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7549 u8 status[0x8]; 7550 u8 reserved_at_8[0x18]; 7551 7552 u8 syndrome[0x20]; 7553 7554 u8 reserved_at_40[0x40]; 7555 }; 7556 7557 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7558 u8 opcode[0x10]; 7559 u8 uid[0x10]; 7560 7561 u8 reserved_at_20[0x10]; 7562 u8 op_mod[0x10]; 7563 7564 u8 reserved_at_40[0x8]; 7565 u8 xrc_srqn[0x18]; 7566 7567 u8 reserved_at_60[0x20]; 7568 }; 7569 7570 struct mlx5_ifc_destroy_tis_out_bits { 7571 u8 status[0x8]; 7572 u8 reserved_at_8[0x18]; 7573 7574 u8 syndrome[0x20]; 7575 7576 u8 reserved_at_40[0x40]; 7577 }; 7578 7579 struct mlx5_ifc_destroy_tis_in_bits { 7580 u8 opcode[0x10]; 7581 u8 uid[0x10]; 7582 7583 u8 reserved_at_20[0x10]; 7584 u8 op_mod[0x10]; 7585 7586 u8 reserved_at_40[0x8]; 7587 u8 tisn[0x18]; 7588 7589 u8 reserved_at_60[0x20]; 7590 }; 7591 7592 struct mlx5_ifc_destroy_tir_out_bits { 7593 u8 status[0x8]; 7594 u8 reserved_at_8[0x18]; 7595 7596 u8 syndrome[0x20]; 7597 7598 u8 reserved_at_40[0x40]; 7599 }; 7600 7601 struct mlx5_ifc_destroy_tir_in_bits { 7602 u8 opcode[0x10]; 7603 u8 uid[0x10]; 7604 7605 u8 reserved_at_20[0x10]; 7606 u8 op_mod[0x10]; 7607 7608 u8 reserved_at_40[0x8]; 7609 u8 tirn[0x18]; 7610 7611 u8 reserved_at_60[0x20]; 7612 }; 7613 7614 struct mlx5_ifc_destroy_srq_out_bits { 7615 u8 status[0x8]; 7616 u8 reserved_at_8[0x18]; 7617 7618 u8 syndrome[0x20]; 7619 7620 u8 reserved_at_40[0x40]; 7621 }; 7622 7623 struct mlx5_ifc_destroy_srq_in_bits { 7624 u8 opcode[0x10]; 7625 u8 uid[0x10]; 7626 7627 u8 reserved_at_20[0x10]; 7628 u8 op_mod[0x10]; 7629 7630 u8 reserved_at_40[0x8]; 7631 u8 srqn[0x18]; 7632 7633 u8 reserved_at_60[0x20]; 7634 }; 7635 7636 struct mlx5_ifc_destroy_sq_out_bits { 7637 u8 status[0x8]; 7638 u8 reserved_at_8[0x18]; 7639 7640 u8 syndrome[0x20]; 7641 7642 u8 reserved_at_40[0x40]; 7643 }; 7644 7645 struct mlx5_ifc_destroy_sq_in_bits { 7646 u8 opcode[0x10]; 7647 u8 uid[0x10]; 7648 7649 u8 reserved_at_20[0x10]; 7650 u8 op_mod[0x10]; 7651 7652 u8 reserved_at_40[0x8]; 7653 u8 sqn[0x18]; 7654 7655 u8 reserved_at_60[0x20]; 7656 }; 7657 7658 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7659 u8 status[0x8]; 7660 u8 reserved_at_8[0x18]; 7661 7662 u8 syndrome[0x20]; 7663 7664 u8 reserved_at_40[0x1c0]; 7665 }; 7666 7667 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7668 u8 opcode[0x10]; 7669 u8 reserved_at_10[0x10]; 7670 7671 u8 reserved_at_20[0x10]; 7672 u8 op_mod[0x10]; 7673 7674 u8 scheduling_hierarchy[0x8]; 7675 u8 reserved_at_48[0x18]; 7676 7677 u8 scheduling_element_id[0x20]; 7678 7679 u8 reserved_at_80[0x180]; 7680 }; 7681 7682 struct mlx5_ifc_destroy_rqt_out_bits { 7683 u8 status[0x8]; 7684 u8 reserved_at_8[0x18]; 7685 7686 u8 syndrome[0x20]; 7687 7688 u8 reserved_at_40[0x40]; 7689 }; 7690 7691 struct mlx5_ifc_destroy_rqt_in_bits { 7692 u8 opcode[0x10]; 7693 u8 uid[0x10]; 7694 7695 u8 reserved_at_20[0x10]; 7696 u8 op_mod[0x10]; 7697 7698 u8 reserved_at_40[0x8]; 7699 u8 rqtn[0x18]; 7700 7701 u8 reserved_at_60[0x20]; 7702 }; 7703 7704 struct mlx5_ifc_destroy_rq_out_bits { 7705 u8 status[0x8]; 7706 u8 reserved_at_8[0x18]; 7707 7708 u8 syndrome[0x20]; 7709 7710 u8 reserved_at_40[0x40]; 7711 }; 7712 7713 struct mlx5_ifc_destroy_rq_in_bits { 7714 u8 opcode[0x10]; 7715 u8 uid[0x10]; 7716 7717 u8 reserved_at_20[0x10]; 7718 u8 op_mod[0x10]; 7719 7720 u8 reserved_at_40[0x8]; 7721 u8 rqn[0x18]; 7722 7723 u8 reserved_at_60[0x20]; 7724 }; 7725 7726 struct mlx5_ifc_set_delay_drop_params_in_bits { 7727 u8 opcode[0x10]; 7728 u8 reserved_at_10[0x10]; 7729 7730 u8 reserved_at_20[0x10]; 7731 u8 op_mod[0x10]; 7732 7733 u8 reserved_at_40[0x20]; 7734 7735 u8 reserved_at_60[0x10]; 7736 u8 delay_drop_timeout[0x10]; 7737 }; 7738 7739 struct mlx5_ifc_set_delay_drop_params_out_bits { 7740 u8 status[0x8]; 7741 u8 reserved_at_8[0x18]; 7742 7743 u8 syndrome[0x20]; 7744 7745 u8 reserved_at_40[0x40]; 7746 }; 7747 7748 struct mlx5_ifc_destroy_rmp_out_bits { 7749 u8 status[0x8]; 7750 u8 reserved_at_8[0x18]; 7751 7752 u8 syndrome[0x20]; 7753 7754 u8 reserved_at_40[0x40]; 7755 }; 7756 7757 struct mlx5_ifc_destroy_rmp_in_bits { 7758 u8 opcode[0x10]; 7759 u8 uid[0x10]; 7760 7761 u8 reserved_at_20[0x10]; 7762 u8 op_mod[0x10]; 7763 7764 u8 reserved_at_40[0x8]; 7765 u8 rmpn[0x18]; 7766 7767 u8 reserved_at_60[0x20]; 7768 }; 7769 7770 struct mlx5_ifc_destroy_qp_out_bits { 7771 u8 status[0x8]; 7772 u8 reserved_at_8[0x18]; 7773 7774 u8 syndrome[0x20]; 7775 7776 u8 reserved_at_40[0x40]; 7777 }; 7778 7779 struct mlx5_ifc_destroy_qp_in_bits { 7780 u8 opcode[0x10]; 7781 u8 uid[0x10]; 7782 7783 u8 reserved_at_20[0x10]; 7784 u8 op_mod[0x10]; 7785 7786 u8 reserved_at_40[0x8]; 7787 u8 qpn[0x18]; 7788 7789 u8 reserved_at_60[0x20]; 7790 }; 7791 7792 struct mlx5_ifc_destroy_psv_out_bits { 7793 u8 status[0x8]; 7794 u8 reserved_at_8[0x18]; 7795 7796 u8 syndrome[0x20]; 7797 7798 u8 reserved_at_40[0x40]; 7799 }; 7800 7801 struct mlx5_ifc_destroy_psv_in_bits { 7802 u8 opcode[0x10]; 7803 u8 reserved_at_10[0x10]; 7804 7805 u8 reserved_at_20[0x10]; 7806 u8 op_mod[0x10]; 7807 7808 u8 reserved_at_40[0x8]; 7809 u8 psvn[0x18]; 7810 7811 u8 reserved_at_60[0x20]; 7812 }; 7813 7814 struct mlx5_ifc_destroy_mkey_out_bits { 7815 u8 status[0x8]; 7816 u8 reserved_at_8[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 reserved_at_40[0x40]; 7821 }; 7822 7823 struct mlx5_ifc_destroy_mkey_in_bits { 7824 u8 opcode[0x10]; 7825 u8 uid[0x10]; 7826 7827 u8 reserved_at_20[0x10]; 7828 u8 op_mod[0x10]; 7829 7830 u8 reserved_at_40[0x8]; 7831 u8 mkey_index[0x18]; 7832 7833 u8 reserved_at_60[0x20]; 7834 }; 7835 7836 struct mlx5_ifc_destroy_flow_table_out_bits { 7837 u8 status[0x8]; 7838 u8 reserved_at_8[0x18]; 7839 7840 u8 syndrome[0x20]; 7841 7842 u8 reserved_at_40[0x40]; 7843 }; 7844 7845 struct mlx5_ifc_destroy_flow_table_in_bits { 7846 u8 opcode[0x10]; 7847 u8 reserved_at_10[0x10]; 7848 7849 u8 reserved_at_20[0x10]; 7850 u8 op_mod[0x10]; 7851 7852 u8 other_vport[0x1]; 7853 u8 reserved_at_41[0xf]; 7854 u8 vport_number[0x10]; 7855 7856 u8 reserved_at_60[0x20]; 7857 7858 u8 table_type[0x8]; 7859 u8 reserved_at_88[0x18]; 7860 7861 u8 reserved_at_a0[0x8]; 7862 u8 table_id[0x18]; 7863 7864 u8 reserved_at_c0[0x140]; 7865 }; 7866 7867 struct mlx5_ifc_destroy_flow_group_out_bits { 7868 u8 status[0x8]; 7869 u8 reserved_at_8[0x18]; 7870 7871 u8 syndrome[0x20]; 7872 7873 u8 reserved_at_40[0x40]; 7874 }; 7875 7876 struct mlx5_ifc_destroy_flow_group_in_bits { 7877 u8 opcode[0x10]; 7878 u8 reserved_at_10[0x10]; 7879 7880 u8 reserved_at_20[0x10]; 7881 u8 op_mod[0x10]; 7882 7883 u8 other_vport[0x1]; 7884 u8 reserved_at_41[0xf]; 7885 u8 vport_number[0x10]; 7886 7887 u8 reserved_at_60[0x20]; 7888 7889 u8 table_type[0x8]; 7890 u8 reserved_at_88[0x18]; 7891 7892 u8 reserved_at_a0[0x8]; 7893 u8 table_id[0x18]; 7894 7895 u8 group_id[0x20]; 7896 7897 u8 reserved_at_e0[0x120]; 7898 }; 7899 7900 struct mlx5_ifc_destroy_eq_out_bits { 7901 u8 status[0x8]; 7902 u8 reserved_at_8[0x18]; 7903 7904 u8 syndrome[0x20]; 7905 7906 u8 reserved_at_40[0x40]; 7907 }; 7908 7909 struct mlx5_ifc_destroy_eq_in_bits { 7910 u8 opcode[0x10]; 7911 u8 reserved_at_10[0x10]; 7912 7913 u8 reserved_at_20[0x10]; 7914 u8 op_mod[0x10]; 7915 7916 u8 reserved_at_40[0x18]; 7917 u8 eq_number[0x8]; 7918 7919 u8 reserved_at_60[0x20]; 7920 }; 7921 7922 struct mlx5_ifc_destroy_dct_out_bits { 7923 u8 status[0x8]; 7924 u8 reserved_at_8[0x18]; 7925 7926 u8 syndrome[0x20]; 7927 7928 u8 reserved_at_40[0x40]; 7929 }; 7930 7931 struct mlx5_ifc_destroy_dct_in_bits { 7932 u8 opcode[0x10]; 7933 u8 uid[0x10]; 7934 7935 u8 reserved_at_20[0x10]; 7936 u8 op_mod[0x10]; 7937 7938 u8 reserved_at_40[0x8]; 7939 u8 dctn[0x18]; 7940 7941 u8 reserved_at_60[0x20]; 7942 }; 7943 7944 struct mlx5_ifc_destroy_cq_out_bits { 7945 u8 status[0x8]; 7946 u8 reserved_at_8[0x18]; 7947 7948 u8 syndrome[0x20]; 7949 7950 u8 reserved_at_40[0x40]; 7951 }; 7952 7953 struct mlx5_ifc_destroy_cq_in_bits { 7954 u8 opcode[0x10]; 7955 u8 uid[0x10]; 7956 7957 u8 reserved_at_20[0x10]; 7958 u8 op_mod[0x10]; 7959 7960 u8 reserved_at_40[0x8]; 7961 u8 cqn[0x18]; 7962 7963 u8 reserved_at_60[0x20]; 7964 }; 7965 7966 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7967 u8 status[0x8]; 7968 u8 reserved_at_8[0x18]; 7969 7970 u8 syndrome[0x20]; 7971 7972 u8 reserved_at_40[0x40]; 7973 }; 7974 7975 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7976 u8 opcode[0x10]; 7977 u8 reserved_at_10[0x10]; 7978 7979 u8 reserved_at_20[0x10]; 7980 u8 op_mod[0x10]; 7981 7982 u8 reserved_at_40[0x20]; 7983 7984 u8 reserved_at_60[0x10]; 7985 u8 vxlan_udp_port[0x10]; 7986 }; 7987 7988 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7989 u8 status[0x8]; 7990 u8 reserved_at_8[0x18]; 7991 7992 u8 syndrome[0x20]; 7993 7994 u8 reserved_at_40[0x40]; 7995 }; 7996 7997 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7998 u8 opcode[0x10]; 7999 u8 reserved_at_10[0x10]; 8000 8001 u8 reserved_at_20[0x10]; 8002 u8 op_mod[0x10]; 8003 8004 u8 reserved_at_40[0x60]; 8005 8006 u8 reserved_at_a0[0x8]; 8007 u8 table_index[0x18]; 8008 8009 u8 reserved_at_c0[0x140]; 8010 }; 8011 8012 struct mlx5_ifc_delete_fte_out_bits { 8013 u8 status[0x8]; 8014 u8 reserved_at_8[0x18]; 8015 8016 u8 syndrome[0x20]; 8017 8018 u8 reserved_at_40[0x40]; 8019 }; 8020 8021 struct mlx5_ifc_delete_fte_in_bits { 8022 u8 opcode[0x10]; 8023 u8 reserved_at_10[0x10]; 8024 8025 u8 reserved_at_20[0x10]; 8026 u8 op_mod[0x10]; 8027 8028 u8 other_vport[0x1]; 8029 u8 reserved_at_41[0xf]; 8030 u8 vport_number[0x10]; 8031 8032 u8 reserved_at_60[0x20]; 8033 8034 u8 table_type[0x8]; 8035 u8 reserved_at_88[0x18]; 8036 8037 u8 reserved_at_a0[0x8]; 8038 u8 table_id[0x18]; 8039 8040 u8 reserved_at_c0[0x40]; 8041 8042 u8 flow_index[0x20]; 8043 8044 u8 reserved_at_120[0xe0]; 8045 }; 8046 8047 struct mlx5_ifc_dealloc_xrcd_out_bits { 8048 u8 status[0x8]; 8049 u8 reserved_at_8[0x18]; 8050 8051 u8 syndrome[0x20]; 8052 8053 u8 reserved_at_40[0x40]; 8054 }; 8055 8056 struct mlx5_ifc_dealloc_xrcd_in_bits { 8057 u8 opcode[0x10]; 8058 u8 uid[0x10]; 8059 8060 u8 reserved_at_20[0x10]; 8061 u8 op_mod[0x10]; 8062 8063 u8 reserved_at_40[0x8]; 8064 u8 xrcd[0x18]; 8065 8066 u8 reserved_at_60[0x20]; 8067 }; 8068 8069 struct mlx5_ifc_dealloc_uar_out_bits { 8070 u8 status[0x8]; 8071 u8 reserved_at_8[0x18]; 8072 8073 u8 syndrome[0x20]; 8074 8075 u8 reserved_at_40[0x40]; 8076 }; 8077 8078 struct mlx5_ifc_dealloc_uar_in_bits { 8079 u8 opcode[0x10]; 8080 u8 uid[0x10]; 8081 8082 u8 reserved_at_20[0x10]; 8083 u8 op_mod[0x10]; 8084 8085 u8 reserved_at_40[0x8]; 8086 u8 uar[0x18]; 8087 8088 u8 reserved_at_60[0x20]; 8089 }; 8090 8091 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8092 u8 status[0x8]; 8093 u8 reserved_at_8[0x18]; 8094 8095 u8 syndrome[0x20]; 8096 8097 u8 reserved_at_40[0x40]; 8098 }; 8099 8100 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8101 u8 opcode[0x10]; 8102 u8 uid[0x10]; 8103 8104 u8 reserved_at_20[0x10]; 8105 u8 op_mod[0x10]; 8106 8107 u8 reserved_at_40[0x8]; 8108 u8 transport_domain[0x18]; 8109 8110 u8 reserved_at_60[0x20]; 8111 }; 8112 8113 struct mlx5_ifc_dealloc_q_counter_out_bits { 8114 u8 status[0x8]; 8115 u8 reserved_at_8[0x18]; 8116 8117 u8 syndrome[0x20]; 8118 8119 u8 reserved_at_40[0x40]; 8120 }; 8121 8122 struct mlx5_ifc_dealloc_q_counter_in_bits { 8123 u8 opcode[0x10]; 8124 u8 reserved_at_10[0x10]; 8125 8126 u8 reserved_at_20[0x10]; 8127 u8 op_mod[0x10]; 8128 8129 u8 reserved_at_40[0x18]; 8130 u8 counter_set_id[0x8]; 8131 8132 u8 reserved_at_60[0x20]; 8133 }; 8134 8135 struct mlx5_ifc_dealloc_pd_out_bits { 8136 u8 status[0x8]; 8137 u8 reserved_at_8[0x18]; 8138 8139 u8 syndrome[0x20]; 8140 8141 u8 reserved_at_40[0x40]; 8142 }; 8143 8144 struct mlx5_ifc_dealloc_pd_in_bits { 8145 u8 opcode[0x10]; 8146 u8 uid[0x10]; 8147 8148 u8 reserved_at_20[0x10]; 8149 u8 op_mod[0x10]; 8150 8151 u8 reserved_at_40[0x8]; 8152 u8 pd[0x18]; 8153 8154 u8 reserved_at_60[0x20]; 8155 }; 8156 8157 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8158 u8 status[0x8]; 8159 u8 reserved_at_8[0x18]; 8160 8161 u8 syndrome[0x20]; 8162 8163 u8 reserved_at_40[0x40]; 8164 }; 8165 8166 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8167 u8 opcode[0x10]; 8168 u8 reserved_at_10[0x10]; 8169 8170 u8 reserved_at_20[0x10]; 8171 u8 op_mod[0x10]; 8172 8173 u8 flow_counter_id[0x20]; 8174 8175 u8 reserved_at_60[0x20]; 8176 }; 8177 8178 struct mlx5_ifc_create_xrq_out_bits { 8179 u8 status[0x8]; 8180 u8 reserved_at_8[0x18]; 8181 8182 u8 syndrome[0x20]; 8183 8184 u8 reserved_at_40[0x8]; 8185 u8 xrqn[0x18]; 8186 8187 u8 reserved_at_60[0x20]; 8188 }; 8189 8190 struct mlx5_ifc_create_xrq_in_bits { 8191 u8 opcode[0x10]; 8192 u8 uid[0x10]; 8193 8194 u8 reserved_at_20[0x10]; 8195 u8 op_mod[0x10]; 8196 8197 u8 reserved_at_40[0x40]; 8198 8199 struct mlx5_ifc_xrqc_bits xrq_context; 8200 }; 8201 8202 struct mlx5_ifc_create_xrc_srq_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 reserved_at_40[0x8]; 8209 u8 xrc_srqn[0x18]; 8210 8211 u8 reserved_at_60[0x20]; 8212 }; 8213 8214 struct mlx5_ifc_create_xrc_srq_in_bits { 8215 u8 opcode[0x10]; 8216 u8 uid[0x10]; 8217 8218 u8 reserved_at_20[0x10]; 8219 u8 op_mod[0x10]; 8220 8221 u8 reserved_at_40[0x40]; 8222 8223 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8224 8225 u8 reserved_at_280[0x60]; 8226 8227 u8 xrc_srq_umem_valid[0x1]; 8228 u8 reserved_at_2e1[0x1f]; 8229 8230 u8 reserved_at_300[0x580]; 8231 8232 u8 pas[][0x40]; 8233 }; 8234 8235 struct mlx5_ifc_create_tis_out_bits { 8236 u8 status[0x8]; 8237 u8 reserved_at_8[0x18]; 8238 8239 u8 syndrome[0x20]; 8240 8241 u8 reserved_at_40[0x8]; 8242 u8 tisn[0x18]; 8243 8244 u8 reserved_at_60[0x20]; 8245 }; 8246 8247 struct mlx5_ifc_create_tis_in_bits { 8248 u8 opcode[0x10]; 8249 u8 uid[0x10]; 8250 8251 u8 reserved_at_20[0x10]; 8252 u8 op_mod[0x10]; 8253 8254 u8 reserved_at_40[0xc0]; 8255 8256 struct mlx5_ifc_tisc_bits ctx; 8257 }; 8258 8259 struct mlx5_ifc_create_tir_out_bits { 8260 u8 status[0x8]; 8261 u8 icm_address_63_40[0x18]; 8262 8263 u8 syndrome[0x20]; 8264 8265 u8 icm_address_39_32[0x8]; 8266 u8 tirn[0x18]; 8267 8268 u8 icm_address_31_0[0x20]; 8269 }; 8270 8271 struct mlx5_ifc_create_tir_in_bits { 8272 u8 opcode[0x10]; 8273 u8 uid[0x10]; 8274 8275 u8 reserved_at_20[0x10]; 8276 u8 op_mod[0x10]; 8277 8278 u8 reserved_at_40[0xc0]; 8279 8280 struct mlx5_ifc_tirc_bits ctx; 8281 }; 8282 8283 struct mlx5_ifc_create_srq_out_bits { 8284 u8 status[0x8]; 8285 u8 reserved_at_8[0x18]; 8286 8287 u8 syndrome[0x20]; 8288 8289 u8 reserved_at_40[0x8]; 8290 u8 srqn[0x18]; 8291 8292 u8 reserved_at_60[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_create_srq_in_bits { 8296 u8 opcode[0x10]; 8297 u8 uid[0x10]; 8298 8299 u8 reserved_at_20[0x10]; 8300 u8 op_mod[0x10]; 8301 8302 u8 reserved_at_40[0x40]; 8303 8304 struct mlx5_ifc_srqc_bits srq_context_entry; 8305 8306 u8 reserved_at_280[0x600]; 8307 8308 u8 pas[][0x40]; 8309 }; 8310 8311 struct mlx5_ifc_create_sq_out_bits { 8312 u8 status[0x8]; 8313 u8 reserved_at_8[0x18]; 8314 8315 u8 syndrome[0x20]; 8316 8317 u8 reserved_at_40[0x8]; 8318 u8 sqn[0x18]; 8319 8320 u8 reserved_at_60[0x20]; 8321 }; 8322 8323 struct mlx5_ifc_create_sq_in_bits { 8324 u8 opcode[0x10]; 8325 u8 uid[0x10]; 8326 8327 u8 reserved_at_20[0x10]; 8328 u8 op_mod[0x10]; 8329 8330 u8 reserved_at_40[0xc0]; 8331 8332 struct mlx5_ifc_sqc_bits ctx; 8333 }; 8334 8335 struct mlx5_ifc_create_scheduling_element_out_bits { 8336 u8 status[0x8]; 8337 u8 reserved_at_8[0x18]; 8338 8339 u8 syndrome[0x20]; 8340 8341 u8 reserved_at_40[0x40]; 8342 8343 u8 scheduling_element_id[0x20]; 8344 8345 u8 reserved_at_a0[0x160]; 8346 }; 8347 8348 struct mlx5_ifc_create_scheduling_element_in_bits { 8349 u8 opcode[0x10]; 8350 u8 reserved_at_10[0x10]; 8351 8352 u8 reserved_at_20[0x10]; 8353 u8 op_mod[0x10]; 8354 8355 u8 scheduling_hierarchy[0x8]; 8356 u8 reserved_at_48[0x18]; 8357 8358 u8 reserved_at_60[0xa0]; 8359 8360 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8361 8362 u8 reserved_at_300[0x100]; 8363 }; 8364 8365 struct mlx5_ifc_create_rqt_out_bits { 8366 u8 status[0x8]; 8367 u8 reserved_at_8[0x18]; 8368 8369 u8 syndrome[0x20]; 8370 8371 u8 reserved_at_40[0x8]; 8372 u8 rqtn[0x18]; 8373 8374 u8 reserved_at_60[0x20]; 8375 }; 8376 8377 struct mlx5_ifc_create_rqt_in_bits { 8378 u8 opcode[0x10]; 8379 u8 uid[0x10]; 8380 8381 u8 reserved_at_20[0x10]; 8382 u8 op_mod[0x10]; 8383 8384 u8 reserved_at_40[0xc0]; 8385 8386 struct mlx5_ifc_rqtc_bits rqt_context; 8387 }; 8388 8389 struct mlx5_ifc_create_rq_out_bits { 8390 u8 status[0x8]; 8391 u8 reserved_at_8[0x18]; 8392 8393 u8 syndrome[0x20]; 8394 8395 u8 reserved_at_40[0x8]; 8396 u8 rqn[0x18]; 8397 8398 u8 reserved_at_60[0x20]; 8399 }; 8400 8401 struct mlx5_ifc_create_rq_in_bits { 8402 u8 opcode[0x10]; 8403 u8 uid[0x10]; 8404 8405 u8 reserved_at_20[0x10]; 8406 u8 op_mod[0x10]; 8407 8408 u8 reserved_at_40[0xc0]; 8409 8410 struct mlx5_ifc_rqc_bits ctx; 8411 }; 8412 8413 struct mlx5_ifc_create_rmp_out_bits { 8414 u8 status[0x8]; 8415 u8 reserved_at_8[0x18]; 8416 8417 u8 syndrome[0x20]; 8418 8419 u8 reserved_at_40[0x8]; 8420 u8 rmpn[0x18]; 8421 8422 u8 reserved_at_60[0x20]; 8423 }; 8424 8425 struct mlx5_ifc_create_rmp_in_bits { 8426 u8 opcode[0x10]; 8427 u8 uid[0x10]; 8428 8429 u8 reserved_at_20[0x10]; 8430 u8 op_mod[0x10]; 8431 8432 u8 reserved_at_40[0xc0]; 8433 8434 struct mlx5_ifc_rmpc_bits ctx; 8435 }; 8436 8437 struct mlx5_ifc_create_qp_out_bits { 8438 u8 status[0x8]; 8439 u8 reserved_at_8[0x18]; 8440 8441 u8 syndrome[0x20]; 8442 8443 u8 reserved_at_40[0x8]; 8444 u8 qpn[0x18]; 8445 8446 u8 ece[0x20]; 8447 }; 8448 8449 struct mlx5_ifc_create_qp_in_bits { 8450 u8 opcode[0x10]; 8451 u8 uid[0x10]; 8452 8453 u8 reserved_at_20[0x10]; 8454 u8 op_mod[0x10]; 8455 8456 u8 reserved_at_40[0x8]; 8457 u8 input_qpn[0x18]; 8458 8459 u8 reserved_at_60[0x20]; 8460 u8 opt_param_mask[0x20]; 8461 8462 u8 ece[0x20]; 8463 8464 struct mlx5_ifc_qpc_bits qpc; 8465 8466 u8 reserved_at_800[0x60]; 8467 8468 u8 wq_umem_valid[0x1]; 8469 u8 reserved_at_861[0x1f]; 8470 8471 u8 pas[][0x40]; 8472 }; 8473 8474 struct mlx5_ifc_create_psv_out_bits { 8475 u8 status[0x8]; 8476 u8 reserved_at_8[0x18]; 8477 8478 u8 syndrome[0x20]; 8479 8480 u8 reserved_at_40[0x40]; 8481 8482 u8 reserved_at_80[0x8]; 8483 u8 psv0_index[0x18]; 8484 8485 u8 reserved_at_a0[0x8]; 8486 u8 psv1_index[0x18]; 8487 8488 u8 reserved_at_c0[0x8]; 8489 u8 psv2_index[0x18]; 8490 8491 u8 reserved_at_e0[0x8]; 8492 u8 psv3_index[0x18]; 8493 }; 8494 8495 struct mlx5_ifc_create_psv_in_bits { 8496 u8 opcode[0x10]; 8497 u8 reserved_at_10[0x10]; 8498 8499 u8 reserved_at_20[0x10]; 8500 u8 op_mod[0x10]; 8501 8502 u8 num_psv[0x4]; 8503 u8 reserved_at_44[0x4]; 8504 u8 pd[0x18]; 8505 8506 u8 reserved_at_60[0x20]; 8507 }; 8508 8509 struct mlx5_ifc_create_mkey_out_bits { 8510 u8 status[0x8]; 8511 u8 reserved_at_8[0x18]; 8512 8513 u8 syndrome[0x20]; 8514 8515 u8 reserved_at_40[0x8]; 8516 u8 mkey_index[0x18]; 8517 8518 u8 reserved_at_60[0x20]; 8519 }; 8520 8521 struct mlx5_ifc_create_mkey_in_bits { 8522 u8 opcode[0x10]; 8523 u8 uid[0x10]; 8524 8525 u8 reserved_at_20[0x10]; 8526 u8 op_mod[0x10]; 8527 8528 u8 reserved_at_40[0x20]; 8529 8530 u8 pg_access[0x1]; 8531 u8 mkey_umem_valid[0x1]; 8532 u8 reserved_at_62[0x1e]; 8533 8534 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8535 8536 u8 reserved_at_280[0x80]; 8537 8538 u8 translations_octword_actual_size[0x20]; 8539 8540 u8 reserved_at_320[0x560]; 8541 8542 u8 klm_pas_mtt[][0x20]; 8543 }; 8544 8545 enum { 8546 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8547 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8548 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8549 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8550 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8551 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8552 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8553 }; 8554 8555 struct mlx5_ifc_create_flow_table_out_bits { 8556 u8 status[0x8]; 8557 u8 icm_address_63_40[0x18]; 8558 8559 u8 syndrome[0x20]; 8560 8561 u8 icm_address_39_32[0x8]; 8562 u8 table_id[0x18]; 8563 8564 u8 icm_address_31_0[0x20]; 8565 }; 8566 8567 struct mlx5_ifc_create_flow_table_in_bits { 8568 u8 opcode[0x10]; 8569 u8 uid[0x10]; 8570 8571 u8 reserved_at_20[0x10]; 8572 u8 op_mod[0x10]; 8573 8574 u8 other_vport[0x1]; 8575 u8 reserved_at_41[0xf]; 8576 u8 vport_number[0x10]; 8577 8578 u8 reserved_at_60[0x20]; 8579 8580 u8 table_type[0x8]; 8581 u8 reserved_at_88[0x18]; 8582 8583 u8 reserved_at_a0[0x20]; 8584 8585 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8586 }; 8587 8588 struct mlx5_ifc_create_flow_group_out_bits { 8589 u8 status[0x8]; 8590 u8 reserved_at_8[0x18]; 8591 8592 u8 syndrome[0x20]; 8593 8594 u8 reserved_at_40[0x8]; 8595 u8 group_id[0x18]; 8596 8597 u8 reserved_at_60[0x20]; 8598 }; 8599 8600 enum { 8601 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8602 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8603 }; 8604 8605 enum { 8606 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8607 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8608 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8609 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8610 }; 8611 8612 struct mlx5_ifc_create_flow_group_in_bits { 8613 u8 opcode[0x10]; 8614 u8 reserved_at_10[0x10]; 8615 8616 u8 reserved_at_20[0x10]; 8617 u8 op_mod[0x10]; 8618 8619 u8 other_vport[0x1]; 8620 u8 reserved_at_41[0xf]; 8621 u8 vport_number[0x10]; 8622 8623 u8 reserved_at_60[0x20]; 8624 8625 u8 table_type[0x8]; 8626 u8 reserved_at_88[0x4]; 8627 u8 group_type[0x4]; 8628 u8 reserved_at_90[0x10]; 8629 8630 u8 reserved_at_a0[0x8]; 8631 u8 table_id[0x18]; 8632 8633 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8634 8635 u8 reserved_at_c1[0x1f]; 8636 8637 u8 start_flow_index[0x20]; 8638 8639 u8 reserved_at_100[0x20]; 8640 8641 u8 end_flow_index[0x20]; 8642 8643 u8 reserved_at_140[0x10]; 8644 u8 match_definer_id[0x10]; 8645 8646 u8 reserved_at_160[0x80]; 8647 8648 u8 reserved_at_1e0[0x18]; 8649 u8 match_criteria_enable[0x8]; 8650 8651 struct mlx5_ifc_fte_match_param_bits match_criteria; 8652 8653 u8 reserved_at_1200[0xe00]; 8654 }; 8655 8656 struct mlx5_ifc_create_eq_out_bits { 8657 u8 status[0x8]; 8658 u8 reserved_at_8[0x18]; 8659 8660 u8 syndrome[0x20]; 8661 8662 u8 reserved_at_40[0x18]; 8663 u8 eq_number[0x8]; 8664 8665 u8 reserved_at_60[0x20]; 8666 }; 8667 8668 struct mlx5_ifc_create_eq_in_bits { 8669 u8 opcode[0x10]; 8670 u8 uid[0x10]; 8671 8672 u8 reserved_at_20[0x10]; 8673 u8 op_mod[0x10]; 8674 8675 u8 reserved_at_40[0x40]; 8676 8677 struct mlx5_ifc_eqc_bits eq_context_entry; 8678 8679 u8 reserved_at_280[0x40]; 8680 8681 u8 event_bitmask[4][0x40]; 8682 8683 u8 reserved_at_3c0[0x4c0]; 8684 8685 u8 pas[][0x40]; 8686 }; 8687 8688 struct mlx5_ifc_create_dct_out_bits { 8689 u8 status[0x8]; 8690 u8 reserved_at_8[0x18]; 8691 8692 u8 syndrome[0x20]; 8693 8694 u8 reserved_at_40[0x8]; 8695 u8 dctn[0x18]; 8696 8697 u8 ece[0x20]; 8698 }; 8699 8700 struct mlx5_ifc_create_dct_in_bits { 8701 u8 opcode[0x10]; 8702 u8 uid[0x10]; 8703 8704 u8 reserved_at_20[0x10]; 8705 u8 op_mod[0x10]; 8706 8707 u8 reserved_at_40[0x40]; 8708 8709 struct mlx5_ifc_dctc_bits dct_context_entry; 8710 8711 u8 reserved_at_280[0x180]; 8712 }; 8713 8714 struct mlx5_ifc_create_cq_out_bits { 8715 u8 status[0x8]; 8716 u8 reserved_at_8[0x18]; 8717 8718 u8 syndrome[0x20]; 8719 8720 u8 reserved_at_40[0x8]; 8721 u8 cqn[0x18]; 8722 8723 u8 reserved_at_60[0x20]; 8724 }; 8725 8726 struct mlx5_ifc_create_cq_in_bits { 8727 u8 opcode[0x10]; 8728 u8 uid[0x10]; 8729 8730 u8 reserved_at_20[0x10]; 8731 u8 op_mod[0x10]; 8732 8733 u8 reserved_at_40[0x40]; 8734 8735 struct mlx5_ifc_cqc_bits cq_context; 8736 8737 u8 reserved_at_280[0x60]; 8738 8739 u8 cq_umem_valid[0x1]; 8740 u8 reserved_at_2e1[0x59f]; 8741 8742 u8 pas[][0x40]; 8743 }; 8744 8745 struct mlx5_ifc_config_int_moderation_out_bits { 8746 u8 status[0x8]; 8747 u8 reserved_at_8[0x18]; 8748 8749 u8 syndrome[0x20]; 8750 8751 u8 reserved_at_40[0x4]; 8752 u8 min_delay[0xc]; 8753 u8 int_vector[0x10]; 8754 8755 u8 reserved_at_60[0x20]; 8756 }; 8757 8758 enum { 8759 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8760 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8761 }; 8762 8763 struct mlx5_ifc_config_int_moderation_in_bits { 8764 u8 opcode[0x10]; 8765 u8 reserved_at_10[0x10]; 8766 8767 u8 reserved_at_20[0x10]; 8768 u8 op_mod[0x10]; 8769 8770 u8 reserved_at_40[0x4]; 8771 u8 min_delay[0xc]; 8772 u8 int_vector[0x10]; 8773 8774 u8 reserved_at_60[0x20]; 8775 }; 8776 8777 struct mlx5_ifc_attach_to_mcg_out_bits { 8778 u8 status[0x8]; 8779 u8 reserved_at_8[0x18]; 8780 8781 u8 syndrome[0x20]; 8782 8783 u8 reserved_at_40[0x40]; 8784 }; 8785 8786 struct mlx5_ifc_attach_to_mcg_in_bits { 8787 u8 opcode[0x10]; 8788 u8 uid[0x10]; 8789 8790 u8 reserved_at_20[0x10]; 8791 u8 op_mod[0x10]; 8792 8793 u8 reserved_at_40[0x8]; 8794 u8 qpn[0x18]; 8795 8796 u8 reserved_at_60[0x20]; 8797 8798 u8 multicast_gid[16][0x8]; 8799 }; 8800 8801 struct mlx5_ifc_arm_xrq_out_bits { 8802 u8 status[0x8]; 8803 u8 reserved_at_8[0x18]; 8804 8805 u8 syndrome[0x20]; 8806 8807 u8 reserved_at_40[0x40]; 8808 }; 8809 8810 struct mlx5_ifc_arm_xrq_in_bits { 8811 u8 opcode[0x10]; 8812 u8 reserved_at_10[0x10]; 8813 8814 u8 reserved_at_20[0x10]; 8815 u8 op_mod[0x10]; 8816 8817 u8 reserved_at_40[0x8]; 8818 u8 xrqn[0x18]; 8819 8820 u8 reserved_at_60[0x10]; 8821 u8 lwm[0x10]; 8822 }; 8823 8824 struct mlx5_ifc_arm_xrc_srq_out_bits { 8825 u8 status[0x8]; 8826 u8 reserved_at_8[0x18]; 8827 8828 u8 syndrome[0x20]; 8829 8830 u8 reserved_at_40[0x40]; 8831 }; 8832 8833 enum { 8834 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8835 }; 8836 8837 struct mlx5_ifc_arm_xrc_srq_in_bits { 8838 u8 opcode[0x10]; 8839 u8 uid[0x10]; 8840 8841 u8 reserved_at_20[0x10]; 8842 u8 op_mod[0x10]; 8843 8844 u8 reserved_at_40[0x8]; 8845 u8 xrc_srqn[0x18]; 8846 8847 u8 reserved_at_60[0x10]; 8848 u8 lwm[0x10]; 8849 }; 8850 8851 struct mlx5_ifc_arm_rq_out_bits { 8852 u8 status[0x8]; 8853 u8 reserved_at_8[0x18]; 8854 8855 u8 syndrome[0x20]; 8856 8857 u8 reserved_at_40[0x40]; 8858 }; 8859 8860 enum { 8861 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8862 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8863 }; 8864 8865 struct mlx5_ifc_arm_rq_in_bits { 8866 u8 opcode[0x10]; 8867 u8 uid[0x10]; 8868 8869 u8 reserved_at_20[0x10]; 8870 u8 op_mod[0x10]; 8871 8872 u8 reserved_at_40[0x8]; 8873 u8 srq_number[0x18]; 8874 8875 u8 reserved_at_60[0x10]; 8876 u8 lwm[0x10]; 8877 }; 8878 8879 struct mlx5_ifc_arm_dct_out_bits { 8880 u8 status[0x8]; 8881 u8 reserved_at_8[0x18]; 8882 8883 u8 syndrome[0x20]; 8884 8885 u8 reserved_at_40[0x40]; 8886 }; 8887 8888 struct mlx5_ifc_arm_dct_in_bits { 8889 u8 opcode[0x10]; 8890 u8 reserved_at_10[0x10]; 8891 8892 u8 reserved_at_20[0x10]; 8893 u8 op_mod[0x10]; 8894 8895 u8 reserved_at_40[0x8]; 8896 u8 dct_number[0x18]; 8897 8898 u8 reserved_at_60[0x20]; 8899 }; 8900 8901 struct mlx5_ifc_alloc_xrcd_out_bits { 8902 u8 status[0x8]; 8903 u8 reserved_at_8[0x18]; 8904 8905 u8 syndrome[0x20]; 8906 8907 u8 reserved_at_40[0x8]; 8908 u8 xrcd[0x18]; 8909 8910 u8 reserved_at_60[0x20]; 8911 }; 8912 8913 struct mlx5_ifc_alloc_xrcd_in_bits { 8914 u8 opcode[0x10]; 8915 u8 uid[0x10]; 8916 8917 u8 reserved_at_20[0x10]; 8918 u8 op_mod[0x10]; 8919 8920 u8 reserved_at_40[0x40]; 8921 }; 8922 8923 struct mlx5_ifc_alloc_uar_out_bits { 8924 u8 status[0x8]; 8925 u8 reserved_at_8[0x18]; 8926 8927 u8 syndrome[0x20]; 8928 8929 u8 reserved_at_40[0x8]; 8930 u8 uar[0x18]; 8931 8932 u8 reserved_at_60[0x20]; 8933 }; 8934 8935 struct mlx5_ifc_alloc_uar_in_bits { 8936 u8 opcode[0x10]; 8937 u8 uid[0x10]; 8938 8939 u8 reserved_at_20[0x10]; 8940 u8 op_mod[0x10]; 8941 8942 u8 reserved_at_40[0x40]; 8943 }; 8944 8945 struct mlx5_ifc_alloc_transport_domain_out_bits { 8946 u8 status[0x8]; 8947 u8 reserved_at_8[0x18]; 8948 8949 u8 syndrome[0x20]; 8950 8951 u8 reserved_at_40[0x8]; 8952 u8 transport_domain[0x18]; 8953 8954 u8 reserved_at_60[0x20]; 8955 }; 8956 8957 struct mlx5_ifc_alloc_transport_domain_in_bits { 8958 u8 opcode[0x10]; 8959 u8 uid[0x10]; 8960 8961 u8 reserved_at_20[0x10]; 8962 u8 op_mod[0x10]; 8963 8964 u8 reserved_at_40[0x40]; 8965 }; 8966 8967 struct mlx5_ifc_alloc_q_counter_out_bits { 8968 u8 status[0x8]; 8969 u8 reserved_at_8[0x18]; 8970 8971 u8 syndrome[0x20]; 8972 8973 u8 reserved_at_40[0x18]; 8974 u8 counter_set_id[0x8]; 8975 8976 u8 reserved_at_60[0x20]; 8977 }; 8978 8979 struct mlx5_ifc_alloc_q_counter_in_bits { 8980 u8 opcode[0x10]; 8981 u8 uid[0x10]; 8982 8983 u8 reserved_at_20[0x10]; 8984 u8 op_mod[0x10]; 8985 8986 u8 reserved_at_40[0x40]; 8987 }; 8988 8989 struct mlx5_ifc_alloc_pd_out_bits { 8990 u8 status[0x8]; 8991 u8 reserved_at_8[0x18]; 8992 8993 u8 syndrome[0x20]; 8994 8995 u8 reserved_at_40[0x8]; 8996 u8 pd[0x18]; 8997 8998 u8 reserved_at_60[0x20]; 8999 }; 9000 9001 struct mlx5_ifc_alloc_pd_in_bits { 9002 u8 opcode[0x10]; 9003 u8 uid[0x10]; 9004 9005 u8 reserved_at_20[0x10]; 9006 u8 op_mod[0x10]; 9007 9008 u8 reserved_at_40[0x40]; 9009 }; 9010 9011 struct mlx5_ifc_alloc_flow_counter_out_bits { 9012 u8 status[0x8]; 9013 u8 reserved_at_8[0x18]; 9014 9015 u8 syndrome[0x20]; 9016 9017 u8 flow_counter_id[0x20]; 9018 9019 u8 reserved_at_60[0x20]; 9020 }; 9021 9022 struct mlx5_ifc_alloc_flow_counter_in_bits { 9023 u8 opcode[0x10]; 9024 u8 reserved_at_10[0x10]; 9025 9026 u8 reserved_at_20[0x10]; 9027 u8 op_mod[0x10]; 9028 9029 u8 reserved_at_40[0x38]; 9030 u8 flow_counter_bulk[0x8]; 9031 }; 9032 9033 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9034 u8 status[0x8]; 9035 u8 reserved_at_8[0x18]; 9036 9037 u8 syndrome[0x20]; 9038 9039 u8 reserved_at_40[0x40]; 9040 }; 9041 9042 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9043 u8 opcode[0x10]; 9044 u8 reserved_at_10[0x10]; 9045 9046 u8 reserved_at_20[0x10]; 9047 u8 op_mod[0x10]; 9048 9049 u8 reserved_at_40[0x20]; 9050 9051 u8 reserved_at_60[0x10]; 9052 u8 vxlan_udp_port[0x10]; 9053 }; 9054 9055 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9056 u8 status[0x8]; 9057 u8 reserved_at_8[0x18]; 9058 9059 u8 syndrome[0x20]; 9060 9061 u8 reserved_at_40[0x40]; 9062 }; 9063 9064 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9065 u8 rate_limit[0x20]; 9066 9067 u8 burst_upper_bound[0x20]; 9068 9069 u8 reserved_at_40[0x10]; 9070 u8 typical_packet_size[0x10]; 9071 9072 u8 reserved_at_60[0x120]; 9073 }; 9074 9075 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9076 u8 opcode[0x10]; 9077 u8 uid[0x10]; 9078 9079 u8 reserved_at_20[0x10]; 9080 u8 op_mod[0x10]; 9081 9082 u8 reserved_at_40[0x10]; 9083 u8 rate_limit_index[0x10]; 9084 9085 u8 reserved_at_60[0x20]; 9086 9087 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9088 }; 9089 9090 struct mlx5_ifc_access_register_out_bits { 9091 u8 status[0x8]; 9092 u8 reserved_at_8[0x18]; 9093 9094 u8 syndrome[0x20]; 9095 9096 u8 reserved_at_40[0x40]; 9097 9098 u8 register_data[][0x20]; 9099 }; 9100 9101 enum { 9102 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9103 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9104 }; 9105 9106 struct mlx5_ifc_access_register_in_bits { 9107 u8 opcode[0x10]; 9108 u8 reserved_at_10[0x10]; 9109 9110 u8 reserved_at_20[0x10]; 9111 u8 op_mod[0x10]; 9112 9113 u8 reserved_at_40[0x10]; 9114 u8 register_id[0x10]; 9115 9116 u8 argument[0x20]; 9117 9118 u8 register_data[][0x20]; 9119 }; 9120 9121 struct mlx5_ifc_sltp_reg_bits { 9122 u8 status[0x4]; 9123 u8 version[0x4]; 9124 u8 local_port[0x8]; 9125 u8 pnat[0x2]; 9126 u8 reserved_at_12[0x2]; 9127 u8 lane[0x4]; 9128 u8 reserved_at_18[0x8]; 9129 9130 u8 reserved_at_20[0x20]; 9131 9132 u8 reserved_at_40[0x7]; 9133 u8 polarity[0x1]; 9134 u8 ob_tap0[0x8]; 9135 u8 ob_tap1[0x8]; 9136 u8 ob_tap2[0x8]; 9137 9138 u8 reserved_at_60[0xc]; 9139 u8 ob_preemp_mode[0x4]; 9140 u8 ob_reg[0x8]; 9141 u8 ob_bias[0x8]; 9142 9143 u8 reserved_at_80[0x20]; 9144 }; 9145 9146 struct mlx5_ifc_slrg_reg_bits { 9147 u8 status[0x4]; 9148 u8 version[0x4]; 9149 u8 local_port[0x8]; 9150 u8 pnat[0x2]; 9151 u8 reserved_at_12[0x2]; 9152 u8 lane[0x4]; 9153 u8 reserved_at_18[0x8]; 9154 9155 u8 time_to_link_up[0x10]; 9156 u8 reserved_at_30[0xc]; 9157 u8 grade_lane_speed[0x4]; 9158 9159 u8 grade_version[0x8]; 9160 u8 grade[0x18]; 9161 9162 u8 reserved_at_60[0x4]; 9163 u8 height_grade_type[0x4]; 9164 u8 height_grade[0x18]; 9165 9166 u8 height_dz[0x10]; 9167 u8 height_dv[0x10]; 9168 9169 u8 reserved_at_a0[0x10]; 9170 u8 height_sigma[0x10]; 9171 9172 u8 reserved_at_c0[0x20]; 9173 9174 u8 reserved_at_e0[0x4]; 9175 u8 phase_grade_type[0x4]; 9176 u8 phase_grade[0x18]; 9177 9178 u8 reserved_at_100[0x8]; 9179 u8 phase_eo_pos[0x8]; 9180 u8 reserved_at_110[0x8]; 9181 u8 phase_eo_neg[0x8]; 9182 9183 u8 ffe_set_tested[0x10]; 9184 u8 test_errors_per_lane[0x10]; 9185 }; 9186 9187 struct mlx5_ifc_pvlc_reg_bits { 9188 u8 reserved_at_0[0x8]; 9189 u8 local_port[0x8]; 9190 u8 reserved_at_10[0x10]; 9191 9192 u8 reserved_at_20[0x1c]; 9193 u8 vl_hw_cap[0x4]; 9194 9195 u8 reserved_at_40[0x1c]; 9196 u8 vl_admin[0x4]; 9197 9198 u8 reserved_at_60[0x1c]; 9199 u8 vl_operational[0x4]; 9200 }; 9201 9202 struct mlx5_ifc_pude_reg_bits { 9203 u8 swid[0x8]; 9204 u8 local_port[0x8]; 9205 u8 reserved_at_10[0x4]; 9206 u8 admin_status[0x4]; 9207 u8 reserved_at_18[0x4]; 9208 u8 oper_status[0x4]; 9209 9210 u8 reserved_at_20[0x60]; 9211 }; 9212 9213 struct mlx5_ifc_ptys_reg_bits { 9214 u8 reserved_at_0[0x1]; 9215 u8 an_disable_admin[0x1]; 9216 u8 an_disable_cap[0x1]; 9217 u8 reserved_at_3[0x5]; 9218 u8 local_port[0x8]; 9219 u8 reserved_at_10[0xd]; 9220 u8 proto_mask[0x3]; 9221 9222 u8 an_status[0x4]; 9223 u8 reserved_at_24[0xc]; 9224 u8 data_rate_oper[0x10]; 9225 9226 u8 ext_eth_proto_capability[0x20]; 9227 9228 u8 eth_proto_capability[0x20]; 9229 9230 u8 ib_link_width_capability[0x10]; 9231 u8 ib_proto_capability[0x10]; 9232 9233 u8 ext_eth_proto_admin[0x20]; 9234 9235 u8 eth_proto_admin[0x20]; 9236 9237 u8 ib_link_width_admin[0x10]; 9238 u8 ib_proto_admin[0x10]; 9239 9240 u8 ext_eth_proto_oper[0x20]; 9241 9242 u8 eth_proto_oper[0x20]; 9243 9244 u8 ib_link_width_oper[0x10]; 9245 u8 ib_proto_oper[0x10]; 9246 9247 u8 reserved_at_160[0x1c]; 9248 u8 connector_type[0x4]; 9249 9250 u8 eth_proto_lp_advertise[0x20]; 9251 9252 u8 reserved_at_1a0[0x60]; 9253 }; 9254 9255 struct mlx5_ifc_mlcr_reg_bits { 9256 u8 reserved_at_0[0x8]; 9257 u8 local_port[0x8]; 9258 u8 reserved_at_10[0x20]; 9259 9260 u8 beacon_duration[0x10]; 9261 u8 reserved_at_40[0x10]; 9262 9263 u8 beacon_remain[0x10]; 9264 }; 9265 9266 struct mlx5_ifc_ptas_reg_bits { 9267 u8 reserved_at_0[0x20]; 9268 9269 u8 algorithm_options[0x10]; 9270 u8 reserved_at_30[0x4]; 9271 u8 repetitions_mode[0x4]; 9272 u8 num_of_repetitions[0x8]; 9273 9274 u8 grade_version[0x8]; 9275 u8 height_grade_type[0x4]; 9276 u8 phase_grade_type[0x4]; 9277 u8 height_grade_weight[0x8]; 9278 u8 phase_grade_weight[0x8]; 9279 9280 u8 gisim_measure_bits[0x10]; 9281 u8 adaptive_tap_measure_bits[0x10]; 9282 9283 u8 ber_bath_high_error_threshold[0x10]; 9284 u8 ber_bath_mid_error_threshold[0x10]; 9285 9286 u8 ber_bath_low_error_threshold[0x10]; 9287 u8 one_ratio_high_threshold[0x10]; 9288 9289 u8 one_ratio_high_mid_threshold[0x10]; 9290 u8 one_ratio_low_mid_threshold[0x10]; 9291 9292 u8 one_ratio_low_threshold[0x10]; 9293 u8 ndeo_error_threshold[0x10]; 9294 9295 u8 mixer_offset_step_size[0x10]; 9296 u8 reserved_at_110[0x8]; 9297 u8 mix90_phase_for_voltage_bath[0x8]; 9298 9299 u8 mixer_offset_start[0x10]; 9300 u8 mixer_offset_end[0x10]; 9301 9302 u8 reserved_at_140[0x15]; 9303 u8 ber_test_time[0xb]; 9304 }; 9305 9306 struct mlx5_ifc_pspa_reg_bits { 9307 u8 swid[0x8]; 9308 u8 local_port[0x8]; 9309 u8 sub_port[0x8]; 9310 u8 reserved_at_18[0x8]; 9311 9312 u8 reserved_at_20[0x20]; 9313 }; 9314 9315 struct mlx5_ifc_pqdr_reg_bits { 9316 u8 reserved_at_0[0x8]; 9317 u8 local_port[0x8]; 9318 u8 reserved_at_10[0x5]; 9319 u8 prio[0x3]; 9320 u8 reserved_at_18[0x6]; 9321 u8 mode[0x2]; 9322 9323 u8 reserved_at_20[0x20]; 9324 9325 u8 reserved_at_40[0x10]; 9326 u8 min_threshold[0x10]; 9327 9328 u8 reserved_at_60[0x10]; 9329 u8 max_threshold[0x10]; 9330 9331 u8 reserved_at_80[0x10]; 9332 u8 mark_probability_denominator[0x10]; 9333 9334 u8 reserved_at_a0[0x60]; 9335 }; 9336 9337 struct mlx5_ifc_ppsc_reg_bits { 9338 u8 reserved_at_0[0x8]; 9339 u8 local_port[0x8]; 9340 u8 reserved_at_10[0x10]; 9341 9342 u8 reserved_at_20[0x60]; 9343 9344 u8 reserved_at_80[0x1c]; 9345 u8 wrps_admin[0x4]; 9346 9347 u8 reserved_at_a0[0x1c]; 9348 u8 wrps_status[0x4]; 9349 9350 u8 reserved_at_c0[0x8]; 9351 u8 up_threshold[0x8]; 9352 u8 reserved_at_d0[0x8]; 9353 u8 down_threshold[0x8]; 9354 9355 u8 reserved_at_e0[0x20]; 9356 9357 u8 reserved_at_100[0x1c]; 9358 u8 srps_admin[0x4]; 9359 9360 u8 reserved_at_120[0x1c]; 9361 u8 srps_status[0x4]; 9362 9363 u8 reserved_at_140[0x40]; 9364 }; 9365 9366 struct mlx5_ifc_pplr_reg_bits { 9367 u8 reserved_at_0[0x8]; 9368 u8 local_port[0x8]; 9369 u8 reserved_at_10[0x10]; 9370 9371 u8 reserved_at_20[0x8]; 9372 u8 lb_cap[0x8]; 9373 u8 reserved_at_30[0x8]; 9374 u8 lb_en[0x8]; 9375 }; 9376 9377 struct mlx5_ifc_pplm_reg_bits { 9378 u8 reserved_at_0[0x8]; 9379 u8 local_port[0x8]; 9380 u8 reserved_at_10[0x10]; 9381 9382 u8 reserved_at_20[0x20]; 9383 9384 u8 port_profile_mode[0x8]; 9385 u8 static_port_profile[0x8]; 9386 u8 active_port_profile[0x8]; 9387 u8 reserved_at_58[0x8]; 9388 9389 u8 retransmission_active[0x8]; 9390 u8 fec_mode_active[0x18]; 9391 9392 u8 rs_fec_correction_bypass_cap[0x4]; 9393 u8 reserved_at_84[0x8]; 9394 u8 fec_override_cap_56g[0x4]; 9395 u8 fec_override_cap_100g[0x4]; 9396 u8 fec_override_cap_50g[0x4]; 9397 u8 fec_override_cap_25g[0x4]; 9398 u8 fec_override_cap_10g_40g[0x4]; 9399 9400 u8 rs_fec_correction_bypass_admin[0x4]; 9401 u8 reserved_at_a4[0x8]; 9402 u8 fec_override_admin_56g[0x4]; 9403 u8 fec_override_admin_100g[0x4]; 9404 u8 fec_override_admin_50g[0x4]; 9405 u8 fec_override_admin_25g[0x4]; 9406 u8 fec_override_admin_10g_40g[0x4]; 9407 9408 u8 fec_override_cap_400g_8x[0x10]; 9409 u8 fec_override_cap_200g_4x[0x10]; 9410 9411 u8 fec_override_cap_100g_2x[0x10]; 9412 u8 fec_override_cap_50g_1x[0x10]; 9413 9414 u8 fec_override_admin_400g_8x[0x10]; 9415 u8 fec_override_admin_200g_4x[0x10]; 9416 9417 u8 fec_override_admin_100g_2x[0x10]; 9418 u8 fec_override_admin_50g_1x[0x10]; 9419 9420 u8 reserved_at_140[0x140]; 9421 }; 9422 9423 struct mlx5_ifc_ppcnt_reg_bits { 9424 u8 swid[0x8]; 9425 u8 local_port[0x8]; 9426 u8 pnat[0x2]; 9427 u8 reserved_at_12[0x8]; 9428 u8 grp[0x6]; 9429 9430 u8 clr[0x1]; 9431 u8 reserved_at_21[0x1c]; 9432 u8 prio_tc[0x3]; 9433 9434 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9435 }; 9436 9437 struct mlx5_ifc_mpein_reg_bits { 9438 u8 reserved_at_0[0x2]; 9439 u8 depth[0x6]; 9440 u8 pcie_index[0x8]; 9441 u8 node[0x8]; 9442 u8 reserved_at_18[0x8]; 9443 9444 u8 capability_mask[0x20]; 9445 9446 u8 reserved_at_40[0x8]; 9447 u8 link_width_enabled[0x8]; 9448 u8 link_speed_enabled[0x10]; 9449 9450 u8 lane0_physical_position[0x8]; 9451 u8 link_width_active[0x8]; 9452 u8 link_speed_active[0x10]; 9453 9454 u8 num_of_pfs[0x10]; 9455 u8 num_of_vfs[0x10]; 9456 9457 u8 bdf0[0x10]; 9458 u8 reserved_at_b0[0x10]; 9459 9460 u8 max_read_request_size[0x4]; 9461 u8 max_payload_size[0x4]; 9462 u8 reserved_at_c8[0x5]; 9463 u8 pwr_status[0x3]; 9464 u8 port_type[0x4]; 9465 u8 reserved_at_d4[0xb]; 9466 u8 lane_reversal[0x1]; 9467 9468 u8 reserved_at_e0[0x14]; 9469 u8 pci_power[0xc]; 9470 9471 u8 reserved_at_100[0x20]; 9472 9473 u8 device_status[0x10]; 9474 u8 port_state[0x8]; 9475 u8 reserved_at_138[0x8]; 9476 9477 u8 reserved_at_140[0x10]; 9478 u8 receiver_detect_result[0x10]; 9479 9480 u8 reserved_at_160[0x20]; 9481 }; 9482 9483 struct mlx5_ifc_mpcnt_reg_bits { 9484 u8 reserved_at_0[0x8]; 9485 u8 pcie_index[0x8]; 9486 u8 reserved_at_10[0xa]; 9487 u8 grp[0x6]; 9488 9489 u8 clr[0x1]; 9490 u8 reserved_at_21[0x1f]; 9491 9492 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9493 }; 9494 9495 struct mlx5_ifc_ppad_reg_bits { 9496 u8 reserved_at_0[0x3]; 9497 u8 single_mac[0x1]; 9498 u8 reserved_at_4[0x4]; 9499 u8 local_port[0x8]; 9500 u8 mac_47_32[0x10]; 9501 9502 u8 mac_31_0[0x20]; 9503 9504 u8 reserved_at_40[0x40]; 9505 }; 9506 9507 struct mlx5_ifc_pmtu_reg_bits { 9508 u8 reserved_at_0[0x8]; 9509 u8 local_port[0x8]; 9510 u8 reserved_at_10[0x10]; 9511 9512 u8 max_mtu[0x10]; 9513 u8 reserved_at_30[0x10]; 9514 9515 u8 admin_mtu[0x10]; 9516 u8 reserved_at_50[0x10]; 9517 9518 u8 oper_mtu[0x10]; 9519 u8 reserved_at_70[0x10]; 9520 }; 9521 9522 struct mlx5_ifc_pmpr_reg_bits { 9523 u8 reserved_at_0[0x8]; 9524 u8 module[0x8]; 9525 u8 reserved_at_10[0x10]; 9526 9527 u8 reserved_at_20[0x18]; 9528 u8 attenuation_5g[0x8]; 9529 9530 u8 reserved_at_40[0x18]; 9531 u8 attenuation_7g[0x8]; 9532 9533 u8 reserved_at_60[0x18]; 9534 u8 attenuation_12g[0x8]; 9535 }; 9536 9537 struct mlx5_ifc_pmpe_reg_bits { 9538 u8 reserved_at_0[0x8]; 9539 u8 module[0x8]; 9540 u8 reserved_at_10[0xc]; 9541 u8 module_status[0x4]; 9542 9543 u8 reserved_at_20[0x60]; 9544 }; 9545 9546 struct mlx5_ifc_pmpc_reg_bits { 9547 u8 module_state_updated[32][0x8]; 9548 }; 9549 9550 struct mlx5_ifc_pmlpn_reg_bits { 9551 u8 reserved_at_0[0x4]; 9552 u8 mlpn_status[0x4]; 9553 u8 local_port[0x8]; 9554 u8 reserved_at_10[0x10]; 9555 9556 u8 e[0x1]; 9557 u8 reserved_at_21[0x1f]; 9558 }; 9559 9560 struct mlx5_ifc_pmlp_reg_bits { 9561 u8 rxtx[0x1]; 9562 u8 reserved_at_1[0x7]; 9563 u8 local_port[0x8]; 9564 u8 reserved_at_10[0x8]; 9565 u8 width[0x8]; 9566 9567 u8 lane0_module_mapping[0x20]; 9568 9569 u8 lane1_module_mapping[0x20]; 9570 9571 u8 lane2_module_mapping[0x20]; 9572 9573 u8 lane3_module_mapping[0x20]; 9574 9575 u8 reserved_at_a0[0x160]; 9576 }; 9577 9578 struct mlx5_ifc_pmaos_reg_bits { 9579 u8 reserved_at_0[0x8]; 9580 u8 module[0x8]; 9581 u8 reserved_at_10[0x4]; 9582 u8 admin_status[0x4]; 9583 u8 reserved_at_18[0x4]; 9584 u8 oper_status[0x4]; 9585 9586 u8 ase[0x1]; 9587 u8 ee[0x1]; 9588 u8 reserved_at_22[0x1c]; 9589 u8 e[0x2]; 9590 9591 u8 reserved_at_40[0x40]; 9592 }; 9593 9594 struct mlx5_ifc_plpc_reg_bits { 9595 u8 reserved_at_0[0x4]; 9596 u8 profile_id[0xc]; 9597 u8 reserved_at_10[0x4]; 9598 u8 proto_mask[0x4]; 9599 u8 reserved_at_18[0x8]; 9600 9601 u8 reserved_at_20[0x10]; 9602 u8 lane_speed[0x10]; 9603 9604 u8 reserved_at_40[0x17]; 9605 u8 lpbf[0x1]; 9606 u8 fec_mode_policy[0x8]; 9607 9608 u8 retransmission_capability[0x8]; 9609 u8 fec_mode_capability[0x18]; 9610 9611 u8 retransmission_support_admin[0x8]; 9612 u8 fec_mode_support_admin[0x18]; 9613 9614 u8 retransmission_request_admin[0x8]; 9615 u8 fec_mode_request_admin[0x18]; 9616 9617 u8 reserved_at_c0[0x80]; 9618 }; 9619 9620 struct mlx5_ifc_plib_reg_bits { 9621 u8 reserved_at_0[0x8]; 9622 u8 local_port[0x8]; 9623 u8 reserved_at_10[0x8]; 9624 u8 ib_port[0x8]; 9625 9626 u8 reserved_at_20[0x60]; 9627 }; 9628 9629 struct mlx5_ifc_plbf_reg_bits { 9630 u8 reserved_at_0[0x8]; 9631 u8 local_port[0x8]; 9632 u8 reserved_at_10[0xd]; 9633 u8 lbf_mode[0x3]; 9634 9635 u8 reserved_at_20[0x20]; 9636 }; 9637 9638 struct mlx5_ifc_pipg_reg_bits { 9639 u8 reserved_at_0[0x8]; 9640 u8 local_port[0x8]; 9641 u8 reserved_at_10[0x10]; 9642 9643 u8 dic[0x1]; 9644 u8 reserved_at_21[0x19]; 9645 u8 ipg[0x4]; 9646 u8 reserved_at_3e[0x2]; 9647 }; 9648 9649 struct mlx5_ifc_pifr_reg_bits { 9650 u8 reserved_at_0[0x8]; 9651 u8 local_port[0x8]; 9652 u8 reserved_at_10[0x10]; 9653 9654 u8 reserved_at_20[0xe0]; 9655 9656 u8 port_filter[8][0x20]; 9657 9658 u8 port_filter_update_en[8][0x20]; 9659 }; 9660 9661 struct mlx5_ifc_pfcc_reg_bits { 9662 u8 reserved_at_0[0x8]; 9663 u8 local_port[0x8]; 9664 u8 reserved_at_10[0xb]; 9665 u8 ppan_mask_n[0x1]; 9666 u8 minor_stall_mask[0x1]; 9667 u8 critical_stall_mask[0x1]; 9668 u8 reserved_at_1e[0x2]; 9669 9670 u8 ppan[0x4]; 9671 u8 reserved_at_24[0x4]; 9672 u8 prio_mask_tx[0x8]; 9673 u8 reserved_at_30[0x8]; 9674 u8 prio_mask_rx[0x8]; 9675 9676 u8 pptx[0x1]; 9677 u8 aptx[0x1]; 9678 u8 pptx_mask_n[0x1]; 9679 u8 reserved_at_43[0x5]; 9680 u8 pfctx[0x8]; 9681 u8 reserved_at_50[0x10]; 9682 9683 u8 pprx[0x1]; 9684 u8 aprx[0x1]; 9685 u8 pprx_mask_n[0x1]; 9686 u8 reserved_at_63[0x5]; 9687 u8 pfcrx[0x8]; 9688 u8 reserved_at_70[0x10]; 9689 9690 u8 device_stall_minor_watermark[0x10]; 9691 u8 device_stall_critical_watermark[0x10]; 9692 9693 u8 reserved_at_a0[0x60]; 9694 }; 9695 9696 struct mlx5_ifc_pelc_reg_bits { 9697 u8 op[0x4]; 9698 u8 reserved_at_4[0x4]; 9699 u8 local_port[0x8]; 9700 u8 reserved_at_10[0x10]; 9701 9702 u8 op_admin[0x8]; 9703 u8 op_capability[0x8]; 9704 u8 op_request[0x8]; 9705 u8 op_active[0x8]; 9706 9707 u8 admin[0x40]; 9708 9709 u8 capability[0x40]; 9710 9711 u8 request[0x40]; 9712 9713 u8 active[0x40]; 9714 9715 u8 reserved_at_140[0x80]; 9716 }; 9717 9718 struct mlx5_ifc_peir_reg_bits { 9719 u8 reserved_at_0[0x8]; 9720 u8 local_port[0x8]; 9721 u8 reserved_at_10[0x10]; 9722 9723 u8 reserved_at_20[0xc]; 9724 u8 error_count[0x4]; 9725 u8 reserved_at_30[0x10]; 9726 9727 u8 reserved_at_40[0xc]; 9728 u8 lane[0x4]; 9729 u8 reserved_at_50[0x8]; 9730 u8 error_type[0x8]; 9731 }; 9732 9733 struct mlx5_ifc_mpegc_reg_bits { 9734 u8 reserved_at_0[0x30]; 9735 u8 field_select[0x10]; 9736 9737 u8 tx_overflow_sense[0x1]; 9738 u8 mark_cqe[0x1]; 9739 u8 mark_cnp[0x1]; 9740 u8 reserved_at_43[0x1b]; 9741 u8 tx_lossy_overflow_oper[0x2]; 9742 9743 u8 reserved_at_60[0x100]; 9744 }; 9745 9746 enum { 9747 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9748 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9749 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9750 }; 9751 9752 struct mlx5_ifc_mtutc_reg_bits { 9753 u8 reserved_at_0[0x1c]; 9754 u8 operation[0x4]; 9755 9756 u8 freq_adjustment[0x20]; 9757 9758 u8 reserved_at_40[0x40]; 9759 9760 u8 utc_sec[0x20]; 9761 9762 u8 reserved_at_a0[0x2]; 9763 u8 utc_nsec[0x1e]; 9764 9765 u8 time_adjustment[0x20]; 9766 }; 9767 9768 struct mlx5_ifc_pcam_enhanced_features_bits { 9769 u8 reserved_at_0[0x68]; 9770 u8 fec_50G_per_lane_in_pplm[0x1]; 9771 u8 reserved_at_69[0x4]; 9772 u8 rx_icrc_encapsulated_counter[0x1]; 9773 u8 reserved_at_6e[0x4]; 9774 u8 ptys_extended_ethernet[0x1]; 9775 u8 reserved_at_73[0x3]; 9776 u8 pfcc_mask[0x1]; 9777 u8 reserved_at_77[0x3]; 9778 u8 per_lane_error_counters[0x1]; 9779 u8 rx_buffer_fullness_counters[0x1]; 9780 u8 ptys_connector_type[0x1]; 9781 u8 reserved_at_7d[0x1]; 9782 u8 ppcnt_discard_group[0x1]; 9783 u8 ppcnt_statistical_group[0x1]; 9784 }; 9785 9786 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9787 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9788 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9789 9790 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9791 u8 pplm[0x1]; 9792 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9793 9794 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9795 u8 pbmc[0x1]; 9796 u8 pptb[0x1]; 9797 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9798 u8 ppcnt[0x1]; 9799 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9800 }; 9801 9802 struct mlx5_ifc_pcam_reg_bits { 9803 u8 reserved_at_0[0x8]; 9804 u8 feature_group[0x8]; 9805 u8 reserved_at_10[0x8]; 9806 u8 access_reg_group[0x8]; 9807 9808 u8 reserved_at_20[0x20]; 9809 9810 union { 9811 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9812 u8 reserved_at_0[0x80]; 9813 } port_access_reg_cap_mask; 9814 9815 u8 reserved_at_c0[0x80]; 9816 9817 union { 9818 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9819 u8 reserved_at_0[0x80]; 9820 } feature_cap_mask; 9821 9822 u8 reserved_at_1c0[0xc0]; 9823 }; 9824 9825 struct mlx5_ifc_mcam_enhanced_features_bits { 9826 u8 reserved_at_0[0x5d]; 9827 u8 mcia_32dwords[0x1]; 9828 u8 reserved_at_5e[0xc]; 9829 u8 reset_state[0x1]; 9830 u8 ptpcyc2realtime_modify[0x1]; 9831 u8 reserved_at_6c[0x2]; 9832 u8 pci_status_and_power[0x1]; 9833 u8 reserved_at_6f[0x5]; 9834 u8 mark_tx_action_cnp[0x1]; 9835 u8 mark_tx_action_cqe[0x1]; 9836 u8 dynamic_tx_overflow[0x1]; 9837 u8 reserved_at_77[0x4]; 9838 u8 pcie_outbound_stalled[0x1]; 9839 u8 tx_overflow_buffer_pkt[0x1]; 9840 u8 mtpps_enh_out_per_adj[0x1]; 9841 u8 mtpps_fs[0x1]; 9842 u8 pcie_performance_group[0x1]; 9843 }; 9844 9845 struct mlx5_ifc_mcam_access_reg_bits { 9846 u8 reserved_at_0[0x1c]; 9847 u8 mcda[0x1]; 9848 u8 mcc[0x1]; 9849 u8 mcqi[0x1]; 9850 u8 mcqs[0x1]; 9851 9852 u8 regs_95_to_87[0x9]; 9853 u8 mpegc[0x1]; 9854 u8 mtutc[0x1]; 9855 u8 regs_84_to_68[0x11]; 9856 u8 tracer_registers[0x4]; 9857 9858 u8 regs_63_to_46[0x12]; 9859 u8 mrtc[0x1]; 9860 u8 regs_44_to_32[0xd]; 9861 9862 u8 regs_31_to_0[0x20]; 9863 }; 9864 9865 struct mlx5_ifc_mcam_access_reg_bits1 { 9866 u8 regs_127_to_96[0x20]; 9867 9868 u8 regs_95_to_64[0x20]; 9869 9870 u8 regs_63_to_32[0x20]; 9871 9872 u8 regs_31_to_0[0x20]; 9873 }; 9874 9875 struct mlx5_ifc_mcam_access_reg_bits2 { 9876 u8 regs_127_to_99[0x1d]; 9877 u8 mirc[0x1]; 9878 u8 regs_97_to_96[0x2]; 9879 9880 u8 regs_95_to_64[0x20]; 9881 9882 u8 regs_63_to_32[0x20]; 9883 9884 u8 regs_31_to_0[0x20]; 9885 }; 9886 9887 struct mlx5_ifc_mcam_reg_bits { 9888 u8 reserved_at_0[0x8]; 9889 u8 feature_group[0x8]; 9890 u8 reserved_at_10[0x8]; 9891 u8 access_reg_group[0x8]; 9892 9893 u8 reserved_at_20[0x20]; 9894 9895 union { 9896 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9897 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9898 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9899 u8 reserved_at_0[0x80]; 9900 } mng_access_reg_cap_mask; 9901 9902 u8 reserved_at_c0[0x80]; 9903 9904 union { 9905 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9906 u8 reserved_at_0[0x80]; 9907 } mng_feature_cap_mask; 9908 9909 u8 reserved_at_1c0[0x80]; 9910 }; 9911 9912 struct mlx5_ifc_qcam_access_reg_cap_mask { 9913 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9914 u8 qpdpm[0x1]; 9915 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9916 u8 qdpm[0x1]; 9917 u8 qpts[0x1]; 9918 u8 qcap[0x1]; 9919 u8 qcam_access_reg_cap_mask_0[0x1]; 9920 }; 9921 9922 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9923 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9924 u8 qpts_trust_both[0x1]; 9925 }; 9926 9927 struct mlx5_ifc_qcam_reg_bits { 9928 u8 reserved_at_0[0x8]; 9929 u8 feature_group[0x8]; 9930 u8 reserved_at_10[0x8]; 9931 u8 access_reg_group[0x8]; 9932 u8 reserved_at_20[0x20]; 9933 9934 union { 9935 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9936 u8 reserved_at_0[0x80]; 9937 } qos_access_reg_cap_mask; 9938 9939 u8 reserved_at_c0[0x80]; 9940 9941 union { 9942 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9943 u8 reserved_at_0[0x80]; 9944 } qos_feature_cap_mask; 9945 9946 u8 reserved_at_1c0[0x80]; 9947 }; 9948 9949 struct mlx5_ifc_core_dump_reg_bits { 9950 u8 reserved_at_0[0x18]; 9951 u8 core_dump_type[0x8]; 9952 9953 u8 reserved_at_20[0x30]; 9954 u8 vhca_id[0x10]; 9955 9956 u8 reserved_at_60[0x8]; 9957 u8 qpn[0x18]; 9958 u8 reserved_at_80[0x180]; 9959 }; 9960 9961 struct mlx5_ifc_pcap_reg_bits { 9962 u8 reserved_at_0[0x8]; 9963 u8 local_port[0x8]; 9964 u8 reserved_at_10[0x10]; 9965 9966 u8 port_capability_mask[4][0x20]; 9967 }; 9968 9969 struct mlx5_ifc_paos_reg_bits { 9970 u8 swid[0x8]; 9971 u8 local_port[0x8]; 9972 u8 reserved_at_10[0x4]; 9973 u8 admin_status[0x4]; 9974 u8 reserved_at_18[0x4]; 9975 u8 oper_status[0x4]; 9976 9977 u8 ase[0x1]; 9978 u8 ee[0x1]; 9979 u8 reserved_at_22[0x1c]; 9980 u8 e[0x2]; 9981 9982 u8 reserved_at_40[0x40]; 9983 }; 9984 9985 struct mlx5_ifc_pamp_reg_bits { 9986 u8 reserved_at_0[0x8]; 9987 u8 opamp_group[0x8]; 9988 u8 reserved_at_10[0xc]; 9989 u8 opamp_group_type[0x4]; 9990 9991 u8 start_index[0x10]; 9992 u8 reserved_at_30[0x4]; 9993 u8 num_of_indices[0xc]; 9994 9995 u8 index_data[18][0x10]; 9996 }; 9997 9998 struct mlx5_ifc_pcmr_reg_bits { 9999 u8 reserved_at_0[0x8]; 10000 u8 local_port[0x8]; 10001 u8 reserved_at_10[0x10]; 10002 10003 u8 entropy_force_cap[0x1]; 10004 u8 entropy_calc_cap[0x1]; 10005 u8 entropy_gre_calc_cap[0x1]; 10006 u8 reserved_at_23[0xf]; 10007 u8 rx_ts_over_crc_cap[0x1]; 10008 u8 reserved_at_33[0xb]; 10009 u8 fcs_cap[0x1]; 10010 u8 reserved_at_3f[0x1]; 10011 10012 u8 entropy_force[0x1]; 10013 u8 entropy_calc[0x1]; 10014 u8 entropy_gre_calc[0x1]; 10015 u8 reserved_at_43[0xf]; 10016 u8 rx_ts_over_crc[0x1]; 10017 u8 reserved_at_53[0xb]; 10018 u8 fcs_chk[0x1]; 10019 u8 reserved_at_5f[0x1]; 10020 }; 10021 10022 struct mlx5_ifc_lane_2_module_mapping_bits { 10023 u8 reserved_at_0[0x4]; 10024 u8 rx_lane[0x4]; 10025 u8 reserved_at_8[0x4]; 10026 u8 tx_lane[0x4]; 10027 u8 reserved_at_10[0x8]; 10028 u8 module[0x8]; 10029 }; 10030 10031 struct mlx5_ifc_bufferx_reg_bits { 10032 u8 reserved_at_0[0x6]; 10033 u8 lossy[0x1]; 10034 u8 epsb[0x1]; 10035 u8 reserved_at_8[0x8]; 10036 u8 size[0x10]; 10037 10038 u8 xoff_threshold[0x10]; 10039 u8 xon_threshold[0x10]; 10040 }; 10041 10042 struct mlx5_ifc_set_node_in_bits { 10043 u8 node_description[64][0x8]; 10044 }; 10045 10046 struct mlx5_ifc_register_power_settings_bits { 10047 u8 reserved_at_0[0x18]; 10048 u8 power_settings_level[0x8]; 10049 10050 u8 reserved_at_20[0x60]; 10051 }; 10052 10053 struct mlx5_ifc_register_host_endianness_bits { 10054 u8 he[0x1]; 10055 u8 reserved_at_1[0x1f]; 10056 10057 u8 reserved_at_20[0x60]; 10058 }; 10059 10060 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10061 u8 reserved_at_0[0x20]; 10062 10063 u8 mkey[0x20]; 10064 10065 u8 addressh_63_32[0x20]; 10066 10067 u8 addressl_31_0[0x20]; 10068 }; 10069 10070 struct mlx5_ifc_ud_adrs_vector_bits { 10071 u8 dc_key[0x40]; 10072 10073 u8 ext[0x1]; 10074 u8 reserved_at_41[0x7]; 10075 u8 destination_qp_dct[0x18]; 10076 10077 u8 static_rate[0x4]; 10078 u8 sl_eth_prio[0x4]; 10079 u8 fl[0x1]; 10080 u8 mlid[0x7]; 10081 u8 rlid_udp_sport[0x10]; 10082 10083 u8 reserved_at_80[0x20]; 10084 10085 u8 rmac_47_16[0x20]; 10086 10087 u8 rmac_15_0[0x10]; 10088 u8 tclass[0x8]; 10089 u8 hop_limit[0x8]; 10090 10091 u8 reserved_at_e0[0x1]; 10092 u8 grh[0x1]; 10093 u8 reserved_at_e2[0x2]; 10094 u8 src_addr_index[0x8]; 10095 u8 flow_label[0x14]; 10096 10097 u8 rgid_rip[16][0x8]; 10098 }; 10099 10100 struct mlx5_ifc_pages_req_event_bits { 10101 u8 reserved_at_0[0x10]; 10102 u8 function_id[0x10]; 10103 10104 u8 num_pages[0x20]; 10105 10106 u8 reserved_at_40[0xa0]; 10107 }; 10108 10109 struct mlx5_ifc_eqe_bits { 10110 u8 reserved_at_0[0x8]; 10111 u8 event_type[0x8]; 10112 u8 reserved_at_10[0x8]; 10113 u8 event_sub_type[0x8]; 10114 10115 u8 reserved_at_20[0xe0]; 10116 10117 union mlx5_ifc_event_auto_bits event_data; 10118 10119 u8 reserved_at_1e0[0x10]; 10120 u8 signature[0x8]; 10121 u8 reserved_at_1f8[0x7]; 10122 u8 owner[0x1]; 10123 }; 10124 10125 enum { 10126 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10127 }; 10128 10129 struct mlx5_ifc_cmd_queue_entry_bits { 10130 u8 type[0x8]; 10131 u8 reserved_at_8[0x18]; 10132 10133 u8 input_length[0x20]; 10134 10135 u8 input_mailbox_pointer_63_32[0x20]; 10136 10137 u8 input_mailbox_pointer_31_9[0x17]; 10138 u8 reserved_at_77[0x9]; 10139 10140 u8 command_input_inline_data[16][0x8]; 10141 10142 u8 command_output_inline_data[16][0x8]; 10143 10144 u8 output_mailbox_pointer_63_32[0x20]; 10145 10146 u8 output_mailbox_pointer_31_9[0x17]; 10147 u8 reserved_at_1b7[0x9]; 10148 10149 u8 output_length[0x20]; 10150 10151 u8 token[0x8]; 10152 u8 signature[0x8]; 10153 u8 reserved_at_1f0[0x8]; 10154 u8 status[0x7]; 10155 u8 ownership[0x1]; 10156 }; 10157 10158 struct mlx5_ifc_cmd_out_bits { 10159 u8 status[0x8]; 10160 u8 reserved_at_8[0x18]; 10161 10162 u8 syndrome[0x20]; 10163 10164 u8 command_output[0x20]; 10165 }; 10166 10167 struct mlx5_ifc_cmd_in_bits { 10168 u8 opcode[0x10]; 10169 u8 reserved_at_10[0x10]; 10170 10171 u8 reserved_at_20[0x10]; 10172 u8 op_mod[0x10]; 10173 10174 u8 command[][0x20]; 10175 }; 10176 10177 struct mlx5_ifc_cmd_if_box_bits { 10178 u8 mailbox_data[512][0x8]; 10179 10180 u8 reserved_at_1000[0x180]; 10181 10182 u8 next_pointer_63_32[0x20]; 10183 10184 u8 next_pointer_31_10[0x16]; 10185 u8 reserved_at_11b6[0xa]; 10186 10187 u8 block_number[0x20]; 10188 10189 u8 reserved_at_11e0[0x8]; 10190 u8 token[0x8]; 10191 u8 ctrl_signature[0x8]; 10192 u8 signature[0x8]; 10193 }; 10194 10195 struct mlx5_ifc_mtt_bits { 10196 u8 ptag_63_32[0x20]; 10197 10198 u8 ptag_31_8[0x18]; 10199 u8 reserved_at_38[0x6]; 10200 u8 wr_en[0x1]; 10201 u8 rd_en[0x1]; 10202 }; 10203 10204 struct mlx5_ifc_query_wol_rol_out_bits { 10205 u8 status[0x8]; 10206 u8 reserved_at_8[0x18]; 10207 10208 u8 syndrome[0x20]; 10209 10210 u8 reserved_at_40[0x10]; 10211 u8 rol_mode[0x8]; 10212 u8 wol_mode[0x8]; 10213 10214 u8 reserved_at_60[0x20]; 10215 }; 10216 10217 struct mlx5_ifc_query_wol_rol_in_bits { 10218 u8 opcode[0x10]; 10219 u8 reserved_at_10[0x10]; 10220 10221 u8 reserved_at_20[0x10]; 10222 u8 op_mod[0x10]; 10223 10224 u8 reserved_at_40[0x40]; 10225 }; 10226 10227 struct mlx5_ifc_set_wol_rol_out_bits { 10228 u8 status[0x8]; 10229 u8 reserved_at_8[0x18]; 10230 10231 u8 syndrome[0x20]; 10232 10233 u8 reserved_at_40[0x40]; 10234 }; 10235 10236 struct mlx5_ifc_set_wol_rol_in_bits { 10237 u8 opcode[0x10]; 10238 u8 reserved_at_10[0x10]; 10239 10240 u8 reserved_at_20[0x10]; 10241 u8 op_mod[0x10]; 10242 10243 u8 rol_mode_valid[0x1]; 10244 u8 wol_mode_valid[0x1]; 10245 u8 reserved_at_42[0xe]; 10246 u8 rol_mode[0x8]; 10247 u8 wol_mode[0x8]; 10248 10249 u8 reserved_at_60[0x20]; 10250 }; 10251 10252 enum { 10253 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10254 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10255 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10256 }; 10257 10258 enum { 10259 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10260 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10261 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10262 }; 10263 10264 enum { 10265 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10266 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10267 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10268 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10269 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10270 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10271 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10272 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10273 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10274 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10275 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10276 }; 10277 10278 struct mlx5_ifc_initial_seg_bits { 10279 u8 fw_rev_minor[0x10]; 10280 u8 fw_rev_major[0x10]; 10281 10282 u8 cmd_interface_rev[0x10]; 10283 u8 fw_rev_subminor[0x10]; 10284 10285 u8 reserved_at_40[0x40]; 10286 10287 u8 cmdq_phy_addr_63_32[0x20]; 10288 10289 u8 cmdq_phy_addr_31_12[0x14]; 10290 u8 reserved_at_b4[0x2]; 10291 u8 nic_interface[0x2]; 10292 u8 log_cmdq_size[0x4]; 10293 u8 log_cmdq_stride[0x4]; 10294 10295 u8 command_doorbell_vector[0x20]; 10296 10297 u8 reserved_at_e0[0xf00]; 10298 10299 u8 initializing[0x1]; 10300 u8 reserved_at_fe1[0x4]; 10301 u8 nic_interface_supported[0x3]; 10302 u8 embedded_cpu[0x1]; 10303 u8 reserved_at_fe9[0x17]; 10304 10305 struct mlx5_ifc_health_buffer_bits health_buffer; 10306 10307 u8 no_dram_nic_offset[0x20]; 10308 10309 u8 reserved_at_1220[0x6e40]; 10310 10311 u8 reserved_at_8060[0x1f]; 10312 u8 clear_int[0x1]; 10313 10314 u8 health_syndrome[0x8]; 10315 u8 health_counter[0x18]; 10316 10317 u8 reserved_at_80a0[0x17fc0]; 10318 }; 10319 10320 struct mlx5_ifc_mtpps_reg_bits { 10321 u8 reserved_at_0[0xc]; 10322 u8 cap_number_of_pps_pins[0x4]; 10323 u8 reserved_at_10[0x4]; 10324 u8 cap_max_num_of_pps_in_pins[0x4]; 10325 u8 reserved_at_18[0x4]; 10326 u8 cap_max_num_of_pps_out_pins[0x4]; 10327 10328 u8 reserved_at_20[0x24]; 10329 u8 cap_pin_3_mode[0x4]; 10330 u8 reserved_at_48[0x4]; 10331 u8 cap_pin_2_mode[0x4]; 10332 u8 reserved_at_50[0x4]; 10333 u8 cap_pin_1_mode[0x4]; 10334 u8 reserved_at_58[0x4]; 10335 u8 cap_pin_0_mode[0x4]; 10336 10337 u8 reserved_at_60[0x4]; 10338 u8 cap_pin_7_mode[0x4]; 10339 u8 reserved_at_68[0x4]; 10340 u8 cap_pin_6_mode[0x4]; 10341 u8 reserved_at_70[0x4]; 10342 u8 cap_pin_5_mode[0x4]; 10343 u8 reserved_at_78[0x4]; 10344 u8 cap_pin_4_mode[0x4]; 10345 10346 u8 field_select[0x20]; 10347 u8 reserved_at_a0[0x60]; 10348 10349 u8 enable[0x1]; 10350 u8 reserved_at_101[0xb]; 10351 u8 pattern[0x4]; 10352 u8 reserved_at_110[0x4]; 10353 u8 pin_mode[0x4]; 10354 u8 pin[0x8]; 10355 10356 u8 reserved_at_120[0x20]; 10357 10358 u8 time_stamp[0x40]; 10359 10360 u8 out_pulse_duration[0x10]; 10361 u8 out_periodic_adjustment[0x10]; 10362 u8 enhanced_out_periodic_adjustment[0x20]; 10363 10364 u8 reserved_at_1c0[0x20]; 10365 }; 10366 10367 struct mlx5_ifc_mtppse_reg_bits { 10368 u8 reserved_at_0[0x18]; 10369 u8 pin[0x8]; 10370 u8 event_arm[0x1]; 10371 u8 reserved_at_21[0x1b]; 10372 u8 event_generation_mode[0x4]; 10373 u8 reserved_at_40[0x40]; 10374 }; 10375 10376 struct mlx5_ifc_mcqs_reg_bits { 10377 u8 last_index_flag[0x1]; 10378 u8 reserved_at_1[0x7]; 10379 u8 fw_device[0x8]; 10380 u8 component_index[0x10]; 10381 10382 u8 reserved_at_20[0x10]; 10383 u8 identifier[0x10]; 10384 10385 u8 reserved_at_40[0x17]; 10386 u8 component_status[0x5]; 10387 u8 component_update_state[0x4]; 10388 10389 u8 last_update_state_changer_type[0x4]; 10390 u8 last_update_state_changer_host_id[0x4]; 10391 u8 reserved_at_68[0x18]; 10392 }; 10393 10394 struct mlx5_ifc_mcqi_cap_bits { 10395 u8 supported_info_bitmask[0x20]; 10396 10397 u8 component_size[0x20]; 10398 10399 u8 max_component_size[0x20]; 10400 10401 u8 log_mcda_word_size[0x4]; 10402 u8 reserved_at_64[0xc]; 10403 u8 mcda_max_write_size[0x10]; 10404 10405 u8 rd_en[0x1]; 10406 u8 reserved_at_81[0x1]; 10407 u8 match_chip_id[0x1]; 10408 u8 match_psid[0x1]; 10409 u8 check_user_timestamp[0x1]; 10410 u8 match_base_guid_mac[0x1]; 10411 u8 reserved_at_86[0x1a]; 10412 }; 10413 10414 struct mlx5_ifc_mcqi_version_bits { 10415 u8 reserved_at_0[0x2]; 10416 u8 build_time_valid[0x1]; 10417 u8 user_defined_time_valid[0x1]; 10418 u8 reserved_at_4[0x14]; 10419 u8 version_string_length[0x8]; 10420 10421 u8 version[0x20]; 10422 10423 u8 build_time[0x40]; 10424 10425 u8 user_defined_time[0x40]; 10426 10427 u8 build_tool_version[0x20]; 10428 10429 u8 reserved_at_e0[0x20]; 10430 10431 u8 version_string[92][0x8]; 10432 }; 10433 10434 struct mlx5_ifc_mcqi_activation_method_bits { 10435 u8 pending_server_ac_power_cycle[0x1]; 10436 u8 pending_server_dc_power_cycle[0x1]; 10437 u8 pending_server_reboot[0x1]; 10438 u8 pending_fw_reset[0x1]; 10439 u8 auto_activate[0x1]; 10440 u8 all_hosts_sync[0x1]; 10441 u8 device_hw_reset[0x1]; 10442 u8 reserved_at_7[0x19]; 10443 }; 10444 10445 union mlx5_ifc_mcqi_reg_data_bits { 10446 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10447 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10448 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10449 }; 10450 10451 struct mlx5_ifc_mcqi_reg_bits { 10452 u8 read_pending_component[0x1]; 10453 u8 reserved_at_1[0xf]; 10454 u8 component_index[0x10]; 10455 10456 u8 reserved_at_20[0x20]; 10457 10458 u8 reserved_at_40[0x1b]; 10459 u8 info_type[0x5]; 10460 10461 u8 info_size[0x20]; 10462 10463 u8 offset[0x20]; 10464 10465 u8 reserved_at_a0[0x10]; 10466 u8 data_size[0x10]; 10467 10468 union mlx5_ifc_mcqi_reg_data_bits data[]; 10469 }; 10470 10471 struct mlx5_ifc_mcc_reg_bits { 10472 u8 reserved_at_0[0x4]; 10473 u8 time_elapsed_since_last_cmd[0xc]; 10474 u8 reserved_at_10[0x8]; 10475 u8 instruction[0x8]; 10476 10477 u8 reserved_at_20[0x10]; 10478 u8 component_index[0x10]; 10479 10480 u8 reserved_at_40[0x8]; 10481 u8 update_handle[0x18]; 10482 10483 u8 handle_owner_type[0x4]; 10484 u8 handle_owner_host_id[0x4]; 10485 u8 reserved_at_68[0x1]; 10486 u8 control_progress[0x7]; 10487 u8 error_code[0x8]; 10488 u8 reserved_at_78[0x4]; 10489 u8 control_state[0x4]; 10490 10491 u8 component_size[0x20]; 10492 10493 u8 reserved_at_a0[0x60]; 10494 }; 10495 10496 struct mlx5_ifc_mcda_reg_bits { 10497 u8 reserved_at_0[0x8]; 10498 u8 update_handle[0x18]; 10499 10500 u8 offset[0x20]; 10501 10502 u8 reserved_at_40[0x10]; 10503 u8 size[0x10]; 10504 10505 u8 reserved_at_60[0x20]; 10506 10507 u8 data[][0x20]; 10508 }; 10509 10510 enum { 10511 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10512 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10513 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10514 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10515 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10516 }; 10517 10518 enum { 10519 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10520 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10521 }; 10522 10523 enum { 10524 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10525 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10526 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10527 }; 10528 10529 struct mlx5_ifc_mfrl_reg_bits { 10530 u8 reserved_at_0[0x20]; 10531 10532 u8 reserved_at_20[0x2]; 10533 u8 pci_sync_for_fw_update_start[0x1]; 10534 u8 pci_sync_for_fw_update_resp[0x2]; 10535 u8 rst_type_sel[0x3]; 10536 u8 reserved_at_28[0x4]; 10537 u8 reset_state[0x4]; 10538 u8 reset_type[0x8]; 10539 u8 reset_level[0x8]; 10540 }; 10541 10542 struct mlx5_ifc_mirc_reg_bits { 10543 u8 reserved_at_0[0x18]; 10544 u8 status_code[0x8]; 10545 10546 u8 reserved_at_20[0x20]; 10547 }; 10548 10549 struct mlx5_ifc_pddr_monitor_opcode_bits { 10550 u8 reserved_at_0[0x10]; 10551 u8 monitor_opcode[0x10]; 10552 }; 10553 10554 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10555 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10556 u8 reserved_at_0[0x20]; 10557 }; 10558 10559 enum { 10560 /* Monitor opcodes */ 10561 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10562 }; 10563 10564 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10565 u8 reserved_at_0[0x10]; 10566 u8 group_opcode[0x10]; 10567 10568 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10569 10570 u8 reserved_at_40[0x20]; 10571 10572 u8 status_message[59][0x20]; 10573 }; 10574 10575 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10576 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10577 u8 reserved_at_0[0x7c0]; 10578 }; 10579 10580 enum { 10581 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10582 }; 10583 10584 struct mlx5_ifc_pddr_reg_bits { 10585 u8 reserved_at_0[0x8]; 10586 u8 local_port[0x8]; 10587 u8 pnat[0x2]; 10588 u8 reserved_at_12[0xe]; 10589 10590 u8 reserved_at_20[0x18]; 10591 u8 page_select[0x8]; 10592 10593 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10594 }; 10595 10596 struct mlx5_ifc_mrtc_reg_bits { 10597 u8 time_synced[0x1]; 10598 u8 reserved_at_1[0x1f]; 10599 10600 u8 reserved_at_20[0x20]; 10601 10602 u8 time_h[0x20]; 10603 10604 u8 time_l[0x20]; 10605 }; 10606 10607 union mlx5_ifc_ports_control_registers_document_bits { 10608 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10609 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10610 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10611 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10612 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10613 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10614 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10615 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10616 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10617 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10618 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10619 struct mlx5_ifc_paos_reg_bits paos_reg; 10620 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10621 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10622 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10623 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10624 struct mlx5_ifc_peir_reg_bits peir_reg; 10625 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10626 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10627 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10628 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10629 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10630 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10631 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10632 struct mlx5_ifc_plib_reg_bits plib_reg; 10633 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10634 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10635 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10636 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10637 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10638 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10639 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10640 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10641 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10642 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10643 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10644 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10645 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10646 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10647 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10648 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10649 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10650 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10651 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10652 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10653 struct mlx5_ifc_pude_reg_bits pude_reg; 10654 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10655 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10656 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10657 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10658 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10659 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10660 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10661 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10662 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10663 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10664 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10665 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10666 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10667 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10668 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10669 u8 reserved_at_0[0x60e0]; 10670 }; 10671 10672 union mlx5_ifc_debug_enhancements_document_bits { 10673 struct mlx5_ifc_health_buffer_bits health_buffer; 10674 u8 reserved_at_0[0x200]; 10675 }; 10676 10677 union mlx5_ifc_uplink_pci_interface_document_bits { 10678 struct mlx5_ifc_initial_seg_bits initial_seg; 10679 u8 reserved_at_0[0x20060]; 10680 }; 10681 10682 struct mlx5_ifc_set_flow_table_root_out_bits { 10683 u8 status[0x8]; 10684 u8 reserved_at_8[0x18]; 10685 10686 u8 syndrome[0x20]; 10687 10688 u8 reserved_at_40[0x40]; 10689 }; 10690 10691 struct mlx5_ifc_set_flow_table_root_in_bits { 10692 u8 opcode[0x10]; 10693 u8 reserved_at_10[0x10]; 10694 10695 u8 reserved_at_20[0x10]; 10696 u8 op_mod[0x10]; 10697 10698 u8 other_vport[0x1]; 10699 u8 reserved_at_41[0xf]; 10700 u8 vport_number[0x10]; 10701 10702 u8 reserved_at_60[0x20]; 10703 10704 u8 table_type[0x8]; 10705 u8 reserved_at_88[0x7]; 10706 u8 table_of_other_vport[0x1]; 10707 u8 table_vport_number[0x10]; 10708 10709 u8 reserved_at_a0[0x8]; 10710 u8 table_id[0x18]; 10711 10712 u8 reserved_at_c0[0x8]; 10713 u8 underlay_qpn[0x18]; 10714 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10715 u8 reserved_at_e1[0xf]; 10716 u8 table_eswitch_owner_vhca_id[0x10]; 10717 u8 reserved_at_100[0x100]; 10718 }; 10719 10720 enum { 10721 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10722 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10723 }; 10724 10725 struct mlx5_ifc_modify_flow_table_out_bits { 10726 u8 status[0x8]; 10727 u8 reserved_at_8[0x18]; 10728 10729 u8 syndrome[0x20]; 10730 10731 u8 reserved_at_40[0x40]; 10732 }; 10733 10734 struct mlx5_ifc_modify_flow_table_in_bits { 10735 u8 opcode[0x10]; 10736 u8 reserved_at_10[0x10]; 10737 10738 u8 reserved_at_20[0x10]; 10739 u8 op_mod[0x10]; 10740 10741 u8 other_vport[0x1]; 10742 u8 reserved_at_41[0xf]; 10743 u8 vport_number[0x10]; 10744 10745 u8 reserved_at_60[0x10]; 10746 u8 modify_field_select[0x10]; 10747 10748 u8 table_type[0x8]; 10749 u8 reserved_at_88[0x18]; 10750 10751 u8 reserved_at_a0[0x8]; 10752 u8 table_id[0x18]; 10753 10754 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10755 }; 10756 10757 struct mlx5_ifc_ets_tcn_config_reg_bits { 10758 u8 g[0x1]; 10759 u8 b[0x1]; 10760 u8 r[0x1]; 10761 u8 reserved_at_3[0x9]; 10762 u8 group[0x4]; 10763 u8 reserved_at_10[0x9]; 10764 u8 bw_allocation[0x7]; 10765 10766 u8 reserved_at_20[0xc]; 10767 u8 max_bw_units[0x4]; 10768 u8 reserved_at_30[0x8]; 10769 u8 max_bw_value[0x8]; 10770 }; 10771 10772 struct mlx5_ifc_ets_global_config_reg_bits { 10773 u8 reserved_at_0[0x2]; 10774 u8 r[0x1]; 10775 u8 reserved_at_3[0x1d]; 10776 10777 u8 reserved_at_20[0xc]; 10778 u8 max_bw_units[0x4]; 10779 u8 reserved_at_30[0x8]; 10780 u8 max_bw_value[0x8]; 10781 }; 10782 10783 struct mlx5_ifc_qetc_reg_bits { 10784 u8 reserved_at_0[0x8]; 10785 u8 port_number[0x8]; 10786 u8 reserved_at_10[0x30]; 10787 10788 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10789 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10790 }; 10791 10792 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10793 u8 e[0x1]; 10794 u8 reserved_at_01[0x0b]; 10795 u8 prio[0x04]; 10796 }; 10797 10798 struct mlx5_ifc_qpdpm_reg_bits { 10799 u8 reserved_at_0[0x8]; 10800 u8 local_port[0x8]; 10801 u8 reserved_at_10[0x10]; 10802 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10803 }; 10804 10805 struct mlx5_ifc_qpts_reg_bits { 10806 u8 reserved_at_0[0x8]; 10807 u8 local_port[0x8]; 10808 u8 reserved_at_10[0x2d]; 10809 u8 trust_state[0x3]; 10810 }; 10811 10812 struct mlx5_ifc_pptb_reg_bits { 10813 u8 reserved_at_0[0x2]; 10814 u8 mm[0x2]; 10815 u8 reserved_at_4[0x4]; 10816 u8 local_port[0x8]; 10817 u8 reserved_at_10[0x6]; 10818 u8 cm[0x1]; 10819 u8 um[0x1]; 10820 u8 pm[0x8]; 10821 10822 u8 prio_x_buff[0x20]; 10823 10824 u8 pm_msb[0x8]; 10825 u8 reserved_at_48[0x10]; 10826 u8 ctrl_buff[0x4]; 10827 u8 untagged_buff[0x4]; 10828 }; 10829 10830 struct mlx5_ifc_sbcam_reg_bits { 10831 u8 reserved_at_0[0x8]; 10832 u8 feature_group[0x8]; 10833 u8 reserved_at_10[0x8]; 10834 u8 access_reg_group[0x8]; 10835 10836 u8 reserved_at_20[0x20]; 10837 10838 u8 sb_access_reg_cap_mask[4][0x20]; 10839 10840 u8 reserved_at_c0[0x80]; 10841 10842 u8 sb_feature_cap_mask[4][0x20]; 10843 10844 u8 reserved_at_1c0[0x40]; 10845 10846 u8 cap_total_buffer_size[0x20]; 10847 10848 u8 cap_cell_size[0x10]; 10849 u8 cap_max_pg_buffers[0x8]; 10850 u8 cap_num_pool_supported[0x8]; 10851 10852 u8 reserved_at_240[0x8]; 10853 u8 cap_sbsr_stat_size[0x8]; 10854 u8 cap_max_tclass_data[0x8]; 10855 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10856 }; 10857 10858 struct mlx5_ifc_pbmc_reg_bits { 10859 u8 reserved_at_0[0x8]; 10860 u8 local_port[0x8]; 10861 u8 reserved_at_10[0x10]; 10862 10863 u8 xoff_timer_value[0x10]; 10864 u8 xoff_refresh[0x10]; 10865 10866 u8 reserved_at_40[0x9]; 10867 u8 fullness_threshold[0x7]; 10868 u8 port_buffer_size[0x10]; 10869 10870 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10871 10872 u8 reserved_at_2e0[0x80]; 10873 }; 10874 10875 struct mlx5_ifc_qtct_reg_bits { 10876 u8 reserved_at_0[0x8]; 10877 u8 port_number[0x8]; 10878 u8 reserved_at_10[0xd]; 10879 u8 prio[0x3]; 10880 10881 u8 reserved_at_20[0x1d]; 10882 u8 tclass[0x3]; 10883 }; 10884 10885 struct mlx5_ifc_mcia_reg_bits { 10886 u8 l[0x1]; 10887 u8 reserved_at_1[0x7]; 10888 u8 module[0x8]; 10889 u8 reserved_at_10[0x8]; 10890 u8 status[0x8]; 10891 10892 u8 i2c_device_address[0x8]; 10893 u8 page_number[0x8]; 10894 u8 device_address[0x10]; 10895 10896 u8 reserved_at_40[0x10]; 10897 u8 size[0x10]; 10898 10899 u8 reserved_at_60[0x20]; 10900 10901 u8 dword_0[0x20]; 10902 u8 dword_1[0x20]; 10903 u8 dword_2[0x20]; 10904 u8 dword_3[0x20]; 10905 u8 dword_4[0x20]; 10906 u8 dword_5[0x20]; 10907 u8 dword_6[0x20]; 10908 u8 dword_7[0x20]; 10909 u8 dword_8[0x20]; 10910 u8 dword_9[0x20]; 10911 u8 dword_10[0x20]; 10912 u8 dword_11[0x20]; 10913 }; 10914 10915 struct mlx5_ifc_dcbx_param_bits { 10916 u8 dcbx_cee_cap[0x1]; 10917 u8 dcbx_ieee_cap[0x1]; 10918 u8 dcbx_standby_cap[0x1]; 10919 u8 reserved_at_3[0x5]; 10920 u8 port_number[0x8]; 10921 u8 reserved_at_10[0xa]; 10922 u8 max_application_table_size[6]; 10923 u8 reserved_at_20[0x15]; 10924 u8 version_oper[0x3]; 10925 u8 reserved_at_38[5]; 10926 u8 version_admin[0x3]; 10927 u8 willing_admin[0x1]; 10928 u8 reserved_at_41[0x3]; 10929 u8 pfc_cap_oper[0x4]; 10930 u8 reserved_at_48[0x4]; 10931 u8 pfc_cap_admin[0x4]; 10932 u8 reserved_at_50[0x4]; 10933 u8 num_of_tc_oper[0x4]; 10934 u8 reserved_at_58[0x4]; 10935 u8 num_of_tc_admin[0x4]; 10936 u8 remote_willing[0x1]; 10937 u8 reserved_at_61[3]; 10938 u8 remote_pfc_cap[4]; 10939 u8 reserved_at_68[0x14]; 10940 u8 remote_num_of_tc[0x4]; 10941 u8 reserved_at_80[0x18]; 10942 u8 error[0x8]; 10943 u8 reserved_at_a0[0x160]; 10944 }; 10945 10946 enum { 10947 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10948 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10949 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10950 }; 10951 10952 struct mlx5_ifc_lagc_bits { 10953 u8 fdb_selection_mode[0x1]; 10954 u8 reserved_at_1[0x14]; 10955 u8 port_select_mode[0x3]; 10956 u8 reserved_at_18[0x5]; 10957 u8 lag_state[0x3]; 10958 10959 u8 reserved_at_20[0x14]; 10960 u8 tx_remap_affinity_2[0x4]; 10961 u8 reserved_at_38[0x4]; 10962 u8 tx_remap_affinity_1[0x4]; 10963 }; 10964 10965 struct mlx5_ifc_create_lag_out_bits { 10966 u8 status[0x8]; 10967 u8 reserved_at_8[0x18]; 10968 10969 u8 syndrome[0x20]; 10970 10971 u8 reserved_at_40[0x40]; 10972 }; 10973 10974 struct mlx5_ifc_create_lag_in_bits { 10975 u8 opcode[0x10]; 10976 u8 reserved_at_10[0x10]; 10977 10978 u8 reserved_at_20[0x10]; 10979 u8 op_mod[0x10]; 10980 10981 struct mlx5_ifc_lagc_bits ctx; 10982 }; 10983 10984 struct mlx5_ifc_modify_lag_out_bits { 10985 u8 status[0x8]; 10986 u8 reserved_at_8[0x18]; 10987 10988 u8 syndrome[0x20]; 10989 10990 u8 reserved_at_40[0x40]; 10991 }; 10992 10993 struct mlx5_ifc_modify_lag_in_bits { 10994 u8 opcode[0x10]; 10995 u8 reserved_at_10[0x10]; 10996 10997 u8 reserved_at_20[0x10]; 10998 u8 op_mod[0x10]; 10999 11000 u8 reserved_at_40[0x20]; 11001 u8 field_select[0x20]; 11002 11003 struct mlx5_ifc_lagc_bits ctx; 11004 }; 11005 11006 struct mlx5_ifc_query_lag_out_bits { 11007 u8 status[0x8]; 11008 u8 reserved_at_8[0x18]; 11009 11010 u8 syndrome[0x20]; 11011 11012 struct mlx5_ifc_lagc_bits ctx; 11013 }; 11014 11015 struct mlx5_ifc_query_lag_in_bits { 11016 u8 opcode[0x10]; 11017 u8 reserved_at_10[0x10]; 11018 11019 u8 reserved_at_20[0x10]; 11020 u8 op_mod[0x10]; 11021 11022 u8 reserved_at_40[0x40]; 11023 }; 11024 11025 struct mlx5_ifc_destroy_lag_out_bits { 11026 u8 status[0x8]; 11027 u8 reserved_at_8[0x18]; 11028 11029 u8 syndrome[0x20]; 11030 11031 u8 reserved_at_40[0x40]; 11032 }; 11033 11034 struct mlx5_ifc_destroy_lag_in_bits { 11035 u8 opcode[0x10]; 11036 u8 reserved_at_10[0x10]; 11037 11038 u8 reserved_at_20[0x10]; 11039 u8 op_mod[0x10]; 11040 11041 u8 reserved_at_40[0x40]; 11042 }; 11043 11044 struct mlx5_ifc_create_vport_lag_out_bits { 11045 u8 status[0x8]; 11046 u8 reserved_at_8[0x18]; 11047 11048 u8 syndrome[0x20]; 11049 11050 u8 reserved_at_40[0x40]; 11051 }; 11052 11053 struct mlx5_ifc_create_vport_lag_in_bits { 11054 u8 opcode[0x10]; 11055 u8 reserved_at_10[0x10]; 11056 11057 u8 reserved_at_20[0x10]; 11058 u8 op_mod[0x10]; 11059 11060 u8 reserved_at_40[0x40]; 11061 }; 11062 11063 struct mlx5_ifc_destroy_vport_lag_out_bits { 11064 u8 status[0x8]; 11065 u8 reserved_at_8[0x18]; 11066 11067 u8 syndrome[0x20]; 11068 11069 u8 reserved_at_40[0x40]; 11070 }; 11071 11072 struct mlx5_ifc_destroy_vport_lag_in_bits { 11073 u8 opcode[0x10]; 11074 u8 reserved_at_10[0x10]; 11075 11076 u8 reserved_at_20[0x10]; 11077 u8 op_mod[0x10]; 11078 11079 u8 reserved_at_40[0x40]; 11080 }; 11081 11082 enum { 11083 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11084 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11085 }; 11086 11087 struct mlx5_ifc_modify_memic_in_bits { 11088 u8 opcode[0x10]; 11089 u8 uid[0x10]; 11090 11091 u8 reserved_at_20[0x10]; 11092 u8 op_mod[0x10]; 11093 11094 u8 reserved_at_40[0x20]; 11095 11096 u8 reserved_at_60[0x18]; 11097 u8 memic_operation_type[0x8]; 11098 11099 u8 memic_start_addr[0x40]; 11100 11101 u8 reserved_at_c0[0x140]; 11102 }; 11103 11104 struct mlx5_ifc_modify_memic_out_bits { 11105 u8 status[0x8]; 11106 u8 reserved_at_8[0x18]; 11107 11108 u8 syndrome[0x20]; 11109 11110 u8 reserved_at_40[0x40]; 11111 11112 u8 memic_operation_addr[0x40]; 11113 11114 u8 reserved_at_c0[0x140]; 11115 }; 11116 11117 struct mlx5_ifc_alloc_memic_in_bits { 11118 u8 opcode[0x10]; 11119 u8 reserved_at_10[0x10]; 11120 11121 u8 reserved_at_20[0x10]; 11122 u8 op_mod[0x10]; 11123 11124 u8 reserved_at_30[0x20]; 11125 11126 u8 reserved_at_40[0x18]; 11127 u8 log_memic_addr_alignment[0x8]; 11128 11129 u8 range_start_addr[0x40]; 11130 11131 u8 range_size[0x20]; 11132 11133 u8 memic_size[0x20]; 11134 }; 11135 11136 struct mlx5_ifc_alloc_memic_out_bits { 11137 u8 status[0x8]; 11138 u8 reserved_at_8[0x18]; 11139 11140 u8 syndrome[0x20]; 11141 11142 u8 memic_start_addr[0x40]; 11143 }; 11144 11145 struct mlx5_ifc_dealloc_memic_in_bits { 11146 u8 opcode[0x10]; 11147 u8 reserved_at_10[0x10]; 11148 11149 u8 reserved_at_20[0x10]; 11150 u8 op_mod[0x10]; 11151 11152 u8 reserved_at_40[0x40]; 11153 11154 u8 memic_start_addr[0x40]; 11155 11156 u8 memic_size[0x20]; 11157 11158 u8 reserved_at_e0[0x20]; 11159 }; 11160 11161 struct mlx5_ifc_dealloc_memic_out_bits { 11162 u8 status[0x8]; 11163 u8 reserved_at_8[0x18]; 11164 11165 u8 syndrome[0x20]; 11166 11167 u8 reserved_at_40[0x40]; 11168 }; 11169 11170 struct mlx5_ifc_umem_bits { 11171 u8 reserved_at_0[0x80]; 11172 11173 u8 reserved_at_80[0x1b]; 11174 u8 log_page_size[0x5]; 11175 11176 u8 page_offset[0x20]; 11177 11178 u8 num_of_mtt[0x40]; 11179 11180 struct mlx5_ifc_mtt_bits mtt[]; 11181 }; 11182 11183 struct mlx5_ifc_uctx_bits { 11184 u8 cap[0x20]; 11185 11186 u8 reserved_at_20[0x160]; 11187 }; 11188 11189 struct mlx5_ifc_sw_icm_bits { 11190 u8 modify_field_select[0x40]; 11191 11192 u8 reserved_at_40[0x18]; 11193 u8 log_sw_icm_size[0x8]; 11194 11195 u8 reserved_at_60[0x20]; 11196 11197 u8 sw_icm_start_addr[0x40]; 11198 11199 u8 reserved_at_c0[0x140]; 11200 }; 11201 11202 struct mlx5_ifc_geneve_tlv_option_bits { 11203 u8 modify_field_select[0x40]; 11204 11205 u8 reserved_at_40[0x18]; 11206 u8 geneve_option_fte_index[0x8]; 11207 11208 u8 option_class[0x10]; 11209 u8 option_type[0x8]; 11210 u8 reserved_at_78[0x3]; 11211 u8 option_data_length[0x5]; 11212 11213 u8 reserved_at_80[0x180]; 11214 }; 11215 11216 struct mlx5_ifc_create_umem_in_bits { 11217 u8 opcode[0x10]; 11218 u8 uid[0x10]; 11219 11220 u8 reserved_at_20[0x10]; 11221 u8 op_mod[0x10]; 11222 11223 u8 reserved_at_40[0x40]; 11224 11225 struct mlx5_ifc_umem_bits umem; 11226 }; 11227 11228 struct mlx5_ifc_create_umem_out_bits { 11229 u8 status[0x8]; 11230 u8 reserved_at_8[0x18]; 11231 11232 u8 syndrome[0x20]; 11233 11234 u8 reserved_at_40[0x8]; 11235 u8 umem_id[0x18]; 11236 11237 u8 reserved_at_60[0x20]; 11238 }; 11239 11240 struct mlx5_ifc_destroy_umem_in_bits { 11241 u8 opcode[0x10]; 11242 u8 uid[0x10]; 11243 11244 u8 reserved_at_20[0x10]; 11245 u8 op_mod[0x10]; 11246 11247 u8 reserved_at_40[0x8]; 11248 u8 umem_id[0x18]; 11249 11250 u8 reserved_at_60[0x20]; 11251 }; 11252 11253 struct mlx5_ifc_destroy_umem_out_bits { 11254 u8 status[0x8]; 11255 u8 reserved_at_8[0x18]; 11256 11257 u8 syndrome[0x20]; 11258 11259 u8 reserved_at_40[0x40]; 11260 }; 11261 11262 struct mlx5_ifc_create_uctx_in_bits { 11263 u8 opcode[0x10]; 11264 u8 reserved_at_10[0x10]; 11265 11266 u8 reserved_at_20[0x10]; 11267 u8 op_mod[0x10]; 11268 11269 u8 reserved_at_40[0x40]; 11270 11271 struct mlx5_ifc_uctx_bits uctx; 11272 }; 11273 11274 struct mlx5_ifc_create_uctx_out_bits { 11275 u8 status[0x8]; 11276 u8 reserved_at_8[0x18]; 11277 11278 u8 syndrome[0x20]; 11279 11280 u8 reserved_at_40[0x10]; 11281 u8 uid[0x10]; 11282 11283 u8 reserved_at_60[0x20]; 11284 }; 11285 11286 struct mlx5_ifc_destroy_uctx_in_bits { 11287 u8 opcode[0x10]; 11288 u8 reserved_at_10[0x10]; 11289 11290 u8 reserved_at_20[0x10]; 11291 u8 op_mod[0x10]; 11292 11293 u8 reserved_at_40[0x10]; 11294 u8 uid[0x10]; 11295 11296 u8 reserved_at_60[0x20]; 11297 }; 11298 11299 struct mlx5_ifc_destroy_uctx_out_bits { 11300 u8 status[0x8]; 11301 u8 reserved_at_8[0x18]; 11302 11303 u8 syndrome[0x20]; 11304 11305 u8 reserved_at_40[0x40]; 11306 }; 11307 11308 struct mlx5_ifc_create_sw_icm_in_bits { 11309 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11310 struct mlx5_ifc_sw_icm_bits sw_icm; 11311 }; 11312 11313 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11314 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11315 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11316 }; 11317 11318 struct mlx5_ifc_mtrc_string_db_param_bits { 11319 u8 string_db_base_address[0x20]; 11320 11321 u8 reserved_at_20[0x8]; 11322 u8 string_db_size[0x18]; 11323 }; 11324 11325 struct mlx5_ifc_mtrc_cap_bits { 11326 u8 trace_owner[0x1]; 11327 u8 trace_to_memory[0x1]; 11328 u8 reserved_at_2[0x4]; 11329 u8 trc_ver[0x2]; 11330 u8 reserved_at_8[0x14]; 11331 u8 num_string_db[0x4]; 11332 11333 u8 first_string_trace[0x8]; 11334 u8 num_string_trace[0x8]; 11335 u8 reserved_at_30[0x28]; 11336 11337 u8 log_max_trace_buffer_size[0x8]; 11338 11339 u8 reserved_at_60[0x20]; 11340 11341 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11342 11343 u8 reserved_at_280[0x180]; 11344 }; 11345 11346 struct mlx5_ifc_mtrc_conf_bits { 11347 u8 reserved_at_0[0x1c]; 11348 u8 trace_mode[0x4]; 11349 u8 reserved_at_20[0x18]; 11350 u8 log_trace_buffer_size[0x8]; 11351 u8 trace_mkey[0x20]; 11352 u8 reserved_at_60[0x3a0]; 11353 }; 11354 11355 struct mlx5_ifc_mtrc_stdb_bits { 11356 u8 string_db_index[0x4]; 11357 u8 reserved_at_4[0x4]; 11358 u8 read_size[0x18]; 11359 u8 start_offset[0x20]; 11360 u8 string_db_data[]; 11361 }; 11362 11363 struct mlx5_ifc_mtrc_ctrl_bits { 11364 u8 trace_status[0x2]; 11365 u8 reserved_at_2[0x2]; 11366 u8 arm_event[0x1]; 11367 u8 reserved_at_5[0xb]; 11368 u8 modify_field_select[0x10]; 11369 u8 reserved_at_20[0x2b]; 11370 u8 current_timestamp52_32[0x15]; 11371 u8 current_timestamp31_0[0x20]; 11372 u8 reserved_at_80[0x180]; 11373 }; 11374 11375 struct mlx5_ifc_host_params_context_bits { 11376 u8 host_number[0x8]; 11377 u8 reserved_at_8[0x7]; 11378 u8 host_pf_disabled[0x1]; 11379 u8 host_num_of_vfs[0x10]; 11380 11381 u8 host_total_vfs[0x10]; 11382 u8 host_pci_bus[0x10]; 11383 11384 u8 reserved_at_40[0x10]; 11385 u8 host_pci_device[0x10]; 11386 11387 u8 reserved_at_60[0x10]; 11388 u8 host_pci_function[0x10]; 11389 11390 u8 reserved_at_80[0x180]; 11391 }; 11392 11393 struct mlx5_ifc_query_esw_functions_in_bits { 11394 u8 opcode[0x10]; 11395 u8 reserved_at_10[0x10]; 11396 11397 u8 reserved_at_20[0x10]; 11398 u8 op_mod[0x10]; 11399 11400 u8 reserved_at_40[0x40]; 11401 }; 11402 11403 struct mlx5_ifc_query_esw_functions_out_bits { 11404 u8 status[0x8]; 11405 u8 reserved_at_8[0x18]; 11406 11407 u8 syndrome[0x20]; 11408 11409 u8 reserved_at_40[0x40]; 11410 11411 struct mlx5_ifc_host_params_context_bits host_params_context; 11412 11413 u8 reserved_at_280[0x180]; 11414 u8 host_sf_enable[][0x40]; 11415 }; 11416 11417 struct mlx5_ifc_sf_partition_bits { 11418 u8 reserved_at_0[0x10]; 11419 u8 log_num_sf[0x8]; 11420 u8 log_sf_bar_size[0x8]; 11421 }; 11422 11423 struct mlx5_ifc_query_sf_partitions_out_bits { 11424 u8 status[0x8]; 11425 u8 reserved_at_8[0x18]; 11426 11427 u8 syndrome[0x20]; 11428 11429 u8 reserved_at_40[0x18]; 11430 u8 num_sf_partitions[0x8]; 11431 11432 u8 reserved_at_60[0x20]; 11433 11434 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11435 }; 11436 11437 struct mlx5_ifc_query_sf_partitions_in_bits { 11438 u8 opcode[0x10]; 11439 u8 reserved_at_10[0x10]; 11440 11441 u8 reserved_at_20[0x10]; 11442 u8 op_mod[0x10]; 11443 11444 u8 reserved_at_40[0x40]; 11445 }; 11446 11447 struct mlx5_ifc_dealloc_sf_out_bits { 11448 u8 status[0x8]; 11449 u8 reserved_at_8[0x18]; 11450 11451 u8 syndrome[0x20]; 11452 11453 u8 reserved_at_40[0x40]; 11454 }; 11455 11456 struct mlx5_ifc_dealloc_sf_in_bits { 11457 u8 opcode[0x10]; 11458 u8 reserved_at_10[0x10]; 11459 11460 u8 reserved_at_20[0x10]; 11461 u8 op_mod[0x10]; 11462 11463 u8 reserved_at_40[0x10]; 11464 u8 function_id[0x10]; 11465 11466 u8 reserved_at_60[0x20]; 11467 }; 11468 11469 struct mlx5_ifc_alloc_sf_out_bits { 11470 u8 status[0x8]; 11471 u8 reserved_at_8[0x18]; 11472 11473 u8 syndrome[0x20]; 11474 11475 u8 reserved_at_40[0x40]; 11476 }; 11477 11478 struct mlx5_ifc_alloc_sf_in_bits { 11479 u8 opcode[0x10]; 11480 u8 reserved_at_10[0x10]; 11481 11482 u8 reserved_at_20[0x10]; 11483 u8 op_mod[0x10]; 11484 11485 u8 reserved_at_40[0x10]; 11486 u8 function_id[0x10]; 11487 11488 u8 reserved_at_60[0x20]; 11489 }; 11490 11491 struct mlx5_ifc_affiliated_event_header_bits { 11492 u8 reserved_at_0[0x10]; 11493 u8 obj_type[0x10]; 11494 11495 u8 obj_id[0x20]; 11496 }; 11497 11498 enum { 11499 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11500 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11501 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11502 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11503 }; 11504 11505 enum { 11506 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11507 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11508 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11509 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11510 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11511 }; 11512 11513 enum { 11514 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11515 }; 11516 11517 struct mlx5_ifc_ipsec_obj_bits { 11518 u8 modify_field_select[0x40]; 11519 u8 full_offload[0x1]; 11520 u8 reserved_at_41[0x1]; 11521 u8 esn_en[0x1]; 11522 u8 esn_overlap[0x1]; 11523 u8 reserved_at_44[0x2]; 11524 u8 icv_length[0x2]; 11525 u8 reserved_at_48[0x4]; 11526 u8 aso_return_reg[0x4]; 11527 u8 reserved_at_50[0x10]; 11528 11529 u8 esn_msb[0x20]; 11530 11531 u8 reserved_at_80[0x8]; 11532 u8 dekn[0x18]; 11533 11534 u8 salt[0x20]; 11535 11536 u8 implicit_iv[0x40]; 11537 11538 u8 reserved_at_100[0x700]; 11539 }; 11540 11541 struct mlx5_ifc_create_ipsec_obj_in_bits { 11542 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11543 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11544 }; 11545 11546 enum { 11547 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11548 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11549 }; 11550 11551 struct mlx5_ifc_query_ipsec_obj_out_bits { 11552 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11553 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11554 }; 11555 11556 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11557 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11558 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11559 }; 11560 11561 struct mlx5_ifc_macsec_aso_bits { 11562 u8 valid[0x1]; 11563 u8 reserved_at_1[0x1]; 11564 u8 mode[0x2]; 11565 u8 window_size[0x2]; 11566 u8 soft_lifetime_arm[0x1]; 11567 u8 hard_lifetime_arm[0x1]; 11568 u8 remove_flow_enable[0x1]; 11569 u8 epn_event_arm[0x1]; 11570 u8 reserved_at_a[0x16]; 11571 11572 u8 remove_flow_packet_count[0x20]; 11573 11574 u8 remove_flow_soft_lifetime[0x20]; 11575 11576 u8 reserved_at_60[0x80]; 11577 11578 u8 mode_parameter[0x20]; 11579 11580 u8 replay_protection_window[8][0x20]; 11581 }; 11582 11583 struct mlx5_ifc_macsec_offload_obj_bits { 11584 u8 modify_field_select[0x40]; 11585 11586 u8 confidentiality_en[0x1]; 11587 u8 reserved_at_41[0x1]; 11588 u8 esn_en[0x1]; 11589 u8 esn_overlap[0x1]; 11590 u8 reserved_at_44[0x2]; 11591 u8 confidentiality_offset[0x2]; 11592 u8 reserved_at_48[0x4]; 11593 u8 aso_return_reg[0x4]; 11594 u8 reserved_at_50[0x10]; 11595 11596 u8 esn_msb[0x20]; 11597 11598 u8 reserved_at_80[0x8]; 11599 u8 dekn[0x18]; 11600 11601 u8 reserved_at_a0[0x20]; 11602 11603 u8 sci[0x40]; 11604 11605 u8 reserved_at_100[0x8]; 11606 u8 macsec_aso_access_pd[0x18]; 11607 11608 u8 reserved_at_120[0x60]; 11609 11610 u8 salt[3][0x20]; 11611 11612 u8 reserved_at_1e0[0x20]; 11613 11614 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11615 }; 11616 11617 struct mlx5_ifc_create_macsec_obj_in_bits { 11618 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11619 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11620 }; 11621 11622 struct mlx5_ifc_encryption_key_obj_bits { 11623 u8 modify_field_select[0x40]; 11624 11625 u8 reserved_at_40[0x14]; 11626 u8 key_size[0x4]; 11627 u8 reserved_at_58[0x4]; 11628 u8 key_type[0x4]; 11629 11630 u8 reserved_at_60[0x8]; 11631 u8 pd[0x18]; 11632 11633 u8 reserved_at_80[0x180]; 11634 u8 key[8][0x20]; 11635 11636 u8 reserved_at_300[0x500]; 11637 }; 11638 11639 struct mlx5_ifc_create_encryption_key_in_bits { 11640 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11641 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11642 }; 11643 11644 enum { 11645 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11646 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11647 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11648 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11649 }; 11650 11651 struct mlx5_ifc_flow_meter_parameters_bits { 11652 u8 valid[0x1]; 11653 u8 bucket_overflow[0x1]; 11654 u8 start_color[0x2]; 11655 u8 both_buckets_on_green[0x1]; 11656 u8 reserved_at_5[0x1]; 11657 u8 meter_mode[0x2]; 11658 u8 reserved_at_8[0x18]; 11659 11660 u8 reserved_at_20[0x20]; 11661 11662 u8 reserved_at_40[0x3]; 11663 u8 cbs_exponent[0x5]; 11664 u8 cbs_mantissa[0x8]; 11665 u8 reserved_at_50[0x3]; 11666 u8 cir_exponent[0x5]; 11667 u8 cir_mantissa[0x8]; 11668 11669 u8 reserved_at_60[0x20]; 11670 11671 u8 reserved_at_80[0x3]; 11672 u8 ebs_exponent[0x5]; 11673 u8 ebs_mantissa[0x8]; 11674 u8 reserved_at_90[0x3]; 11675 u8 eir_exponent[0x5]; 11676 u8 eir_mantissa[0x8]; 11677 11678 u8 reserved_at_a0[0x60]; 11679 }; 11680 11681 struct mlx5_ifc_flow_meter_aso_obj_bits { 11682 u8 modify_field_select[0x40]; 11683 11684 u8 reserved_at_40[0x40]; 11685 11686 u8 reserved_at_80[0x8]; 11687 u8 meter_aso_access_pd[0x18]; 11688 11689 u8 reserved_at_a0[0x160]; 11690 11691 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11692 }; 11693 11694 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11695 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11696 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11697 }; 11698 11699 struct mlx5_ifc_sampler_obj_bits { 11700 u8 modify_field_select[0x40]; 11701 11702 u8 table_type[0x8]; 11703 u8 level[0x8]; 11704 u8 reserved_at_50[0xf]; 11705 u8 ignore_flow_level[0x1]; 11706 11707 u8 sample_ratio[0x20]; 11708 11709 u8 reserved_at_80[0x8]; 11710 u8 sample_table_id[0x18]; 11711 11712 u8 reserved_at_a0[0x8]; 11713 u8 default_table_id[0x18]; 11714 11715 u8 sw_steering_icm_address_rx[0x40]; 11716 u8 sw_steering_icm_address_tx[0x40]; 11717 11718 u8 reserved_at_140[0xa0]; 11719 }; 11720 11721 struct mlx5_ifc_create_sampler_obj_in_bits { 11722 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11723 struct mlx5_ifc_sampler_obj_bits sampler_object; 11724 }; 11725 11726 struct mlx5_ifc_query_sampler_obj_out_bits { 11727 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11728 struct mlx5_ifc_sampler_obj_bits sampler_object; 11729 }; 11730 11731 enum { 11732 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11733 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11734 }; 11735 11736 enum { 11737 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11738 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11739 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4, 11740 }; 11741 11742 struct mlx5_ifc_tls_static_params_bits { 11743 u8 const_2[0x2]; 11744 u8 tls_version[0x4]; 11745 u8 const_1[0x2]; 11746 u8 reserved_at_8[0x14]; 11747 u8 encryption_standard[0x4]; 11748 11749 u8 reserved_at_20[0x20]; 11750 11751 u8 initial_record_number[0x40]; 11752 11753 u8 resync_tcp_sn[0x20]; 11754 11755 u8 gcm_iv[0x20]; 11756 11757 u8 implicit_iv[0x40]; 11758 11759 u8 reserved_at_100[0x8]; 11760 u8 dek_index[0x18]; 11761 11762 u8 reserved_at_120[0xe0]; 11763 }; 11764 11765 struct mlx5_ifc_tls_progress_params_bits { 11766 u8 next_record_tcp_sn[0x20]; 11767 11768 u8 hw_resync_tcp_sn[0x20]; 11769 11770 u8 record_tracker_state[0x2]; 11771 u8 auth_state[0x2]; 11772 u8 reserved_at_44[0x4]; 11773 u8 hw_offset_record_number[0x18]; 11774 }; 11775 11776 enum { 11777 MLX5_MTT_PERM_READ = 1 << 0, 11778 MLX5_MTT_PERM_WRITE = 1 << 1, 11779 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11780 }; 11781 11782 enum { 11783 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11784 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11785 }; 11786 11787 struct mlx5_ifc_suspend_vhca_in_bits { 11788 u8 opcode[0x10]; 11789 u8 uid[0x10]; 11790 11791 u8 reserved_at_20[0x10]; 11792 u8 op_mod[0x10]; 11793 11794 u8 reserved_at_40[0x10]; 11795 u8 vhca_id[0x10]; 11796 11797 u8 reserved_at_60[0x20]; 11798 }; 11799 11800 struct mlx5_ifc_suspend_vhca_out_bits { 11801 u8 status[0x8]; 11802 u8 reserved_at_8[0x18]; 11803 11804 u8 syndrome[0x20]; 11805 11806 u8 reserved_at_40[0x40]; 11807 }; 11808 11809 enum { 11810 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11811 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11812 }; 11813 11814 struct mlx5_ifc_resume_vhca_in_bits { 11815 u8 opcode[0x10]; 11816 u8 uid[0x10]; 11817 11818 u8 reserved_at_20[0x10]; 11819 u8 op_mod[0x10]; 11820 11821 u8 reserved_at_40[0x10]; 11822 u8 vhca_id[0x10]; 11823 11824 u8 reserved_at_60[0x20]; 11825 }; 11826 11827 struct mlx5_ifc_resume_vhca_out_bits { 11828 u8 status[0x8]; 11829 u8 reserved_at_8[0x18]; 11830 11831 u8 syndrome[0x20]; 11832 11833 u8 reserved_at_40[0x40]; 11834 }; 11835 11836 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11837 u8 opcode[0x10]; 11838 u8 uid[0x10]; 11839 11840 u8 reserved_at_20[0x10]; 11841 u8 op_mod[0x10]; 11842 11843 u8 reserved_at_40[0x10]; 11844 u8 vhca_id[0x10]; 11845 11846 u8 reserved_at_60[0x20]; 11847 }; 11848 11849 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11850 u8 status[0x8]; 11851 u8 reserved_at_8[0x18]; 11852 11853 u8 syndrome[0x20]; 11854 11855 u8 reserved_at_40[0x40]; 11856 11857 u8 required_umem_size[0x20]; 11858 11859 u8 reserved_at_a0[0x160]; 11860 }; 11861 11862 struct mlx5_ifc_save_vhca_state_in_bits { 11863 u8 opcode[0x10]; 11864 u8 uid[0x10]; 11865 11866 u8 reserved_at_20[0x10]; 11867 u8 op_mod[0x10]; 11868 11869 u8 reserved_at_40[0x10]; 11870 u8 vhca_id[0x10]; 11871 11872 u8 reserved_at_60[0x20]; 11873 11874 u8 va[0x40]; 11875 11876 u8 mkey[0x20]; 11877 11878 u8 size[0x20]; 11879 }; 11880 11881 struct mlx5_ifc_save_vhca_state_out_bits { 11882 u8 status[0x8]; 11883 u8 reserved_at_8[0x18]; 11884 11885 u8 syndrome[0x20]; 11886 11887 u8 actual_image_size[0x20]; 11888 11889 u8 reserved_at_60[0x20]; 11890 }; 11891 11892 struct mlx5_ifc_load_vhca_state_in_bits { 11893 u8 opcode[0x10]; 11894 u8 uid[0x10]; 11895 11896 u8 reserved_at_20[0x10]; 11897 u8 op_mod[0x10]; 11898 11899 u8 reserved_at_40[0x10]; 11900 u8 vhca_id[0x10]; 11901 11902 u8 reserved_at_60[0x20]; 11903 11904 u8 va[0x40]; 11905 11906 u8 mkey[0x20]; 11907 11908 u8 size[0x20]; 11909 }; 11910 11911 struct mlx5_ifc_load_vhca_state_out_bits { 11912 u8 status[0x8]; 11913 u8 reserved_at_8[0x18]; 11914 11915 u8 syndrome[0x20]; 11916 11917 u8 reserved_at_40[0x40]; 11918 }; 11919 11920 #endif /* MLX5_IFC_H */ 11921