1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 85 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 86 MLX5_CMD_OP_INIT_HCA = 0x102, 87 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 88 MLX5_CMD_OP_ENABLE_HCA = 0x104, 89 MLX5_CMD_OP_DISABLE_HCA = 0x105, 90 MLX5_CMD_OP_QUERY_PAGES = 0x107, 91 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 92 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 93 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 94 MLX5_CMD_OP_SET_ISSI = 0x10b, 95 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 96 MLX5_CMD_OP_CREATE_MKEY = 0x200, 97 MLX5_CMD_OP_QUERY_MKEY = 0x201, 98 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 99 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 100 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 101 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 102 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 103 MLX5_CMD_OP_CREATE_EQ = 0x301, 104 MLX5_CMD_OP_DESTROY_EQ = 0x302, 105 MLX5_CMD_OP_QUERY_EQ = 0x303, 106 MLX5_CMD_OP_GEN_EQE = 0x304, 107 MLX5_CMD_OP_CREATE_CQ = 0x400, 108 MLX5_CMD_OP_DESTROY_CQ = 0x401, 109 MLX5_CMD_OP_QUERY_CQ = 0x402, 110 MLX5_CMD_OP_MODIFY_CQ = 0x403, 111 MLX5_CMD_OP_CREATE_QP = 0x500, 112 MLX5_CMD_OP_DESTROY_QP = 0x501, 113 MLX5_CMD_OP_RST2INIT_QP = 0x502, 114 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 115 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 116 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 117 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 118 MLX5_CMD_OP_2ERR_QP = 0x507, 119 MLX5_CMD_OP_2RST_QP = 0x50a, 120 MLX5_CMD_OP_QUERY_QP = 0x50b, 121 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 122 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 123 MLX5_CMD_OP_CREATE_PSV = 0x600, 124 MLX5_CMD_OP_DESTROY_PSV = 0x601, 125 MLX5_CMD_OP_CREATE_SRQ = 0x700, 126 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 127 MLX5_CMD_OP_QUERY_SRQ = 0x702, 128 MLX5_CMD_OP_ARM_RQ = 0x703, 129 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 130 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 131 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 132 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 133 MLX5_CMD_OP_CREATE_DCT = 0x710, 134 MLX5_CMD_OP_DESTROY_DCT = 0x711, 135 MLX5_CMD_OP_DRAIN_DCT = 0x712, 136 MLX5_CMD_OP_QUERY_DCT = 0x713, 137 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 138 MLX5_CMD_OP_CREATE_XRQ = 0x717, 139 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 140 MLX5_CMD_OP_QUERY_XRQ = 0x719, 141 MLX5_CMD_OP_ARM_XRQ = 0x71a, 142 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 143 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 144 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 145 MLX5_CMD_OP_QUERY_HOST_PARAMS = 0x740, 146 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 147 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 148 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 149 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 150 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 151 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 152 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 153 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 154 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 155 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 156 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 158 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 159 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 160 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 161 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 162 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 163 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 164 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 165 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 166 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 167 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 168 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 169 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 170 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 171 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 172 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 173 MLX5_CMD_OP_ALLOC_PD = 0x800, 174 MLX5_CMD_OP_DEALLOC_PD = 0x801, 175 MLX5_CMD_OP_ALLOC_UAR = 0x802, 176 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 177 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 178 MLX5_CMD_OP_ACCESS_REG = 0x805, 179 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 180 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 181 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 182 MLX5_CMD_OP_MAD_IFC = 0x50d, 183 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 184 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 185 MLX5_CMD_OP_NOP = 0x80d, 186 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 187 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 188 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 189 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 190 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 191 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 192 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 193 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 194 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 195 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 196 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 197 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 198 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 199 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 200 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 201 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 202 MLX5_CMD_OP_CREATE_LAG = 0x840, 203 MLX5_CMD_OP_MODIFY_LAG = 0x841, 204 MLX5_CMD_OP_QUERY_LAG = 0x842, 205 MLX5_CMD_OP_DESTROY_LAG = 0x843, 206 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 207 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 208 MLX5_CMD_OP_CREATE_TIR = 0x900, 209 MLX5_CMD_OP_MODIFY_TIR = 0x901, 210 MLX5_CMD_OP_DESTROY_TIR = 0x902, 211 MLX5_CMD_OP_QUERY_TIR = 0x903, 212 MLX5_CMD_OP_CREATE_SQ = 0x904, 213 MLX5_CMD_OP_MODIFY_SQ = 0x905, 214 MLX5_CMD_OP_DESTROY_SQ = 0x906, 215 MLX5_CMD_OP_QUERY_SQ = 0x907, 216 MLX5_CMD_OP_CREATE_RQ = 0x908, 217 MLX5_CMD_OP_MODIFY_RQ = 0x909, 218 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 219 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 220 MLX5_CMD_OP_QUERY_RQ = 0x90b, 221 MLX5_CMD_OP_CREATE_RMP = 0x90c, 222 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 223 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 224 MLX5_CMD_OP_QUERY_RMP = 0x90f, 225 MLX5_CMD_OP_CREATE_TIS = 0x912, 226 MLX5_CMD_OP_MODIFY_TIS = 0x913, 227 MLX5_CMD_OP_DESTROY_TIS = 0x914, 228 MLX5_CMD_OP_QUERY_TIS = 0x915, 229 MLX5_CMD_OP_CREATE_RQT = 0x916, 230 MLX5_CMD_OP_MODIFY_RQT = 0x917, 231 MLX5_CMD_OP_DESTROY_RQT = 0x918, 232 MLX5_CMD_OP_QUERY_RQT = 0x919, 233 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 234 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 235 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 236 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 237 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 238 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 239 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 240 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 241 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 242 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 243 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 244 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 245 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 246 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 247 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 248 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 249 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 250 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 251 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 252 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 253 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 254 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 255 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 256 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 257 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 258 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 259 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 260 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 261 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 262 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 263 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 264 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 265 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 266 MLX5_CMD_OP_MAX 267 }; 268 269 /* Valid range for general commands that don't work over an object */ 270 enum { 271 MLX5_CMD_OP_GENERAL_START = 0xb00, 272 MLX5_CMD_OP_GENERAL_END = 0xd00, 273 }; 274 275 struct mlx5_ifc_flow_table_fields_supported_bits { 276 u8 outer_dmac[0x1]; 277 u8 outer_smac[0x1]; 278 u8 outer_ether_type[0x1]; 279 u8 outer_ip_version[0x1]; 280 u8 outer_first_prio[0x1]; 281 u8 outer_first_cfi[0x1]; 282 u8 outer_first_vid[0x1]; 283 u8 outer_ipv4_ttl[0x1]; 284 u8 outer_second_prio[0x1]; 285 u8 outer_second_cfi[0x1]; 286 u8 outer_second_vid[0x1]; 287 u8 reserved_at_b[0x1]; 288 u8 outer_sip[0x1]; 289 u8 outer_dip[0x1]; 290 u8 outer_frag[0x1]; 291 u8 outer_ip_protocol[0x1]; 292 u8 outer_ip_ecn[0x1]; 293 u8 outer_ip_dscp[0x1]; 294 u8 outer_udp_sport[0x1]; 295 u8 outer_udp_dport[0x1]; 296 u8 outer_tcp_sport[0x1]; 297 u8 outer_tcp_dport[0x1]; 298 u8 outer_tcp_flags[0x1]; 299 u8 outer_gre_protocol[0x1]; 300 u8 outer_gre_key[0x1]; 301 u8 outer_vxlan_vni[0x1]; 302 u8 reserved_at_1a[0x5]; 303 u8 source_eswitch_port[0x1]; 304 305 u8 inner_dmac[0x1]; 306 u8 inner_smac[0x1]; 307 u8 inner_ether_type[0x1]; 308 u8 inner_ip_version[0x1]; 309 u8 inner_first_prio[0x1]; 310 u8 inner_first_cfi[0x1]; 311 u8 inner_first_vid[0x1]; 312 u8 reserved_at_27[0x1]; 313 u8 inner_second_prio[0x1]; 314 u8 inner_second_cfi[0x1]; 315 u8 inner_second_vid[0x1]; 316 u8 reserved_at_2b[0x1]; 317 u8 inner_sip[0x1]; 318 u8 inner_dip[0x1]; 319 u8 inner_frag[0x1]; 320 u8 inner_ip_protocol[0x1]; 321 u8 inner_ip_ecn[0x1]; 322 u8 inner_ip_dscp[0x1]; 323 u8 inner_udp_sport[0x1]; 324 u8 inner_udp_dport[0x1]; 325 u8 inner_tcp_sport[0x1]; 326 u8 inner_tcp_dport[0x1]; 327 u8 inner_tcp_flags[0x1]; 328 u8 reserved_at_37[0x9]; 329 330 u8 reserved_at_40[0x5]; 331 u8 outer_first_mpls_over_udp[0x4]; 332 u8 outer_first_mpls_over_gre[0x4]; 333 u8 inner_first_mpls[0x4]; 334 u8 outer_first_mpls[0x4]; 335 u8 reserved_at_55[0x2]; 336 u8 outer_esp_spi[0x1]; 337 u8 reserved_at_58[0x2]; 338 u8 bth_dst_qp[0x1]; 339 340 u8 reserved_at_5b[0x25]; 341 }; 342 343 struct mlx5_ifc_flow_table_prop_layout_bits { 344 u8 ft_support[0x1]; 345 u8 reserved_at_1[0x1]; 346 u8 flow_counter[0x1]; 347 u8 flow_modify_en[0x1]; 348 u8 modify_root[0x1]; 349 u8 identified_miss_table_mode[0x1]; 350 u8 flow_table_modify[0x1]; 351 u8 reformat[0x1]; 352 u8 decap[0x1]; 353 u8 reserved_at_9[0x1]; 354 u8 pop_vlan[0x1]; 355 u8 push_vlan[0x1]; 356 u8 reserved_at_c[0x1]; 357 u8 pop_vlan_2[0x1]; 358 u8 push_vlan_2[0x1]; 359 u8 reformat_and_vlan_action[0x1]; 360 u8 reserved_at_10[0x2]; 361 u8 reformat_l3_tunnel_to_l2[0x1]; 362 u8 reformat_l2_to_l3_tunnel[0x1]; 363 u8 reformat_and_modify_action[0x1]; 364 u8 reserved_at_15[0xb]; 365 u8 reserved_at_20[0x2]; 366 u8 log_max_ft_size[0x6]; 367 u8 log_max_modify_header_context[0x8]; 368 u8 max_modify_header_actions[0x8]; 369 u8 max_ft_level[0x8]; 370 371 u8 reserved_at_40[0x20]; 372 373 u8 reserved_at_60[0x18]; 374 u8 log_max_ft_num[0x8]; 375 376 u8 reserved_at_80[0x18]; 377 u8 log_max_destination[0x8]; 378 379 u8 log_max_flow_counter[0x8]; 380 u8 reserved_at_a8[0x10]; 381 u8 log_max_flow[0x8]; 382 383 u8 reserved_at_c0[0x40]; 384 385 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 386 387 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 388 }; 389 390 struct mlx5_ifc_odp_per_transport_service_cap_bits { 391 u8 send[0x1]; 392 u8 receive[0x1]; 393 u8 write[0x1]; 394 u8 read[0x1]; 395 u8 atomic[0x1]; 396 u8 srq_receive[0x1]; 397 u8 reserved_at_6[0x1a]; 398 }; 399 400 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 401 u8 smac_47_16[0x20]; 402 403 u8 smac_15_0[0x10]; 404 u8 ethertype[0x10]; 405 406 u8 dmac_47_16[0x20]; 407 408 u8 dmac_15_0[0x10]; 409 u8 first_prio[0x3]; 410 u8 first_cfi[0x1]; 411 u8 first_vid[0xc]; 412 413 u8 ip_protocol[0x8]; 414 u8 ip_dscp[0x6]; 415 u8 ip_ecn[0x2]; 416 u8 cvlan_tag[0x1]; 417 u8 svlan_tag[0x1]; 418 u8 frag[0x1]; 419 u8 ip_version[0x4]; 420 u8 tcp_flags[0x9]; 421 422 u8 tcp_sport[0x10]; 423 u8 tcp_dport[0x10]; 424 425 u8 reserved_at_c0[0x18]; 426 u8 ttl_hoplimit[0x8]; 427 428 u8 udp_sport[0x10]; 429 u8 udp_dport[0x10]; 430 431 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 432 433 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 434 }; 435 436 struct mlx5_ifc_nvgre_key_bits { 437 u8 hi[0x18]; 438 u8 lo[0x8]; 439 }; 440 441 union mlx5_ifc_gre_key_bits { 442 struct mlx5_ifc_nvgre_key_bits nvgre; 443 u8 key[0x20]; 444 }; 445 446 struct mlx5_ifc_fte_match_set_misc_bits { 447 u8 reserved_at_0[0x8]; 448 u8 source_sqn[0x18]; 449 450 u8 source_eswitch_owner_vhca_id[0x10]; 451 u8 source_port[0x10]; 452 453 u8 outer_second_prio[0x3]; 454 u8 outer_second_cfi[0x1]; 455 u8 outer_second_vid[0xc]; 456 u8 inner_second_prio[0x3]; 457 u8 inner_second_cfi[0x1]; 458 u8 inner_second_vid[0xc]; 459 460 u8 outer_second_cvlan_tag[0x1]; 461 u8 inner_second_cvlan_tag[0x1]; 462 u8 outer_second_svlan_tag[0x1]; 463 u8 inner_second_svlan_tag[0x1]; 464 u8 reserved_at_64[0xc]; 465 u8 gre_protocol[0x10]; 466 467 union mlx5_ifc_gre_key_bits gre_key; 468 469 u8 vxlan_vni[0x18]; 470 u8 reserved_at_b8[0x8]; 471 472 u8 reserved_at_c0[0x20]; 473 474 u8 reserved_at_e0[0xc]; 475 u8 outer_ipv6_flow_label[0x14]; 476 477 u8 reserved_at_100[0xc]; 478 u8 inner_ipv6_flow_label[0x14]; 479 480 u8 reserved_at_120[0x28]; 481 u8 bth_dst_qp[0x18]; 482 u8 reserved_at_160[0x20]; 483 u8 outer_esp_spi[0x20]; 484 u8 reserved_at_1a0[0x60]; 485 }; 486 487 struct mlx5_ifc_fte_match_mpls_bits { 488 u8 mpls_label[0x14]; 489 u8 mpls_exp[0x3]; 490 u8 mpls_s_bos[0x1]; 491 u8 mpls_ttl[0x8]; 492 }; 493 494 struct mlx5_ifc_fte_match_set_misc2_bits { 495 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 496 497 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 498 499 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 500 501 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 502 503 u8 reserved_at_80[0x100]; 504 505 u8 metadata_reg_a[0x20]; 506 507 u8 reserved_at_1a0[0x60]; 508 }; 509 510 struct mlx5_ifc_cmd_pas_bits { 511 u8 pa_h[0x20]; 512 513 u8 pa_l[0x14]; 514 u8 reserved_at_34[0xc]; 515 }; 516 517 struct mlx5_ifc_uint64_bits { 518 u8 hi[0x20]; 519 520 u8 lo[0x20]; 521 }; 522 523 enum { 524 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 525 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 526 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 527 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 528 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 529 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 530 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 531 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 532 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 533 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 534 }; 535 536 struct mlx5_ifc_ads_bits { 537 u8 fl[0x1]; 538 u8 free_ar[0x1]; 539 u8 reserved_at_2[0xe]; 540 u8 pkey_index[0x10]; 541 542 u8 reserved_at_20[0x8]; 543 u8 grh[0x1]; 544 u8 mlid[0x7]; 545 u8 rlid[0x10]; 546 547 u8 ack_timeout[0x5]; 548 u8 reserved_at_45[0x3]; 549 u8 src_addr_index[0x8]; 550 u8 reserved_at_50[0x4]; 551 u8 stat_rate[0x4]; 552 u8 hop_limit[0x8]; 553 554 u8 reserved_at_60[0x4]; 555 u8 tclass[0x8]; 556 u8 flow_label[0x14]; 557 558 u8 rgid_rip[16][0x8]; 559 560 u8 reserved_at_100[0x4]; 561 u8 f_dscp[0x1]; 562 u8 f_ecn[0x1]; 563 u8 reserved_at_106[0x1]; 564 u8 f_eth_prio[0x1]; 565 u8 ecn[0x2]; 566 u8 dscp[0x6]; 567 u8 udp_sport[0x10]; 568 569 u8 dei_cfi[0x1]; 570 u8 eth_prio[0x3]; 571 u8 sl[0x4]; 572 u8 vhca_port_num[0x8]; 573 u8 rmac_47_32[0x10]; 574 575 u8 rmac_31_0[0x20]; 576 }; 577 578 struct mlx5_ifc_flow_table_nic_cap_bits { 579 u8 nic_rx_multi_path_tirs[0x1]; 580 u8 nic_rx_multi_path_tirs_fts[0x1]; 581 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 582 u8 reserved_at_3[0x1d]; 583 u8 encap_general_header[0x1]; 584 u8 reserved_at_21[0xa]; 585 u8 log_max_packet_reformat_context[0x5]; 586 u8 reserved_at_30[0x6]; 587 u8 max_encap_header_size[0xa]; 588 u8 reserved_at_40[0x1c0]; 589 590 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 591 592 u8 reserved_at_400[0x200]; 593 594 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 595 596 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 597 598 u8 reserved_at_a00[0x200]; 599 600 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 601 602 u8 reserved_at_e00[0x7200]; 603 }; 604 605 struct mlx5_ifc_flow_table_eswitch_cap_bits { 606 u8 reserved_at_0[0x1a]; 607 u8 multi_fdb_encap[0x1]; 608 u8 reserved_at_1b[0x1]; 609 u8 fdb_multi_path_to_table[0x1]; 610 u8 reserved_at_1d[0x3]; 611 612 u8 reserved_at_20[0x1e0]; 613 614 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 615 616 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 617 618 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 619 620 u8 reserved_at_800[0x7800]; 621 }; 622 623 enum { 624 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 625 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 626 }; 627 628 struct mlx5_ifc_e_switch_cap_bits { 629 u8 vport_svlan_strip[0x1]; 630 u8 vport_cvlan_strip[0x1]; 631 u8 vport_svlan_insert[0x1]; 632 u8 vport_cvlan_insert_if_not_exist[0x1]; 633 u8 vport_cvlan_insert_overwrite[0x1]; 634 u8 reserved_at_5[0x16]; 635 u8 ecpf_vport_exists[0x1]; 636 u8 counter_eswitch_affinity[0x1]; 637 u8 merged_eswitch[0x1]; 638 u8 nic_vport_node_guid_modify[0x1]; 639 u8 nic_vport_port_guid_modify[0x1]; 640 641 u8 vxlan_encap_decap[0x1]; 642 u8 nvgre_encap_decap[0x1]; 643 u8 reserved_at_22[0x1]; 644 u8 log_max_fdb_encap_uplink[0x5]; 645 u8 reserved_at_21[0x3]; 646 u8 log_max_packet_reformat_context[0x5]; 647 u8 reserved_2b[0x6]; 648 u8 max_encap_header_size[0xa]; 649 650 u8 reserved_40[0x7c0]; 651 652 }; 653 654 struct mlx5_ifc_qos_cap_bits { 655 u8 packet_pacing[0x1]; 656 u8 esw_scheduling[0x1]; 657 u8 esw_bw_share[0x1]; 658 u8 esw_rate_limit[0x1]; 659 u8 reserved_at_4[0x1]; 660 u8 packet_pacing_burst_bound[0x1]; 661 u8 packet_pacing_typical_size[0x1]; 662 u8 reserved_at_7[0x19]; 663 664 u8 reserved_at_20[0x20]; 665 666 u8 packet_pacing_max_rate[0x20]; 667 668 u8 packet_pacing_min_rate[0x20]; 669 670 u8 reserved_at_80[0x10]; 671 u8 packet_pacing_rate_table_size[0x10]; 672 673 u8 esw_element_type[0x10]; 674 u8 esw_tsar_type[0x10]; 675 676 u8 reserved_at_c0[0x10]; 677 u8 max_qos_para_vport[0x10]; 678 679 u8 max_tsar_bw_share[0x20]; 680 681 u8 reserved_at_100[0x700]; 682 }; 683 684 struct mlx5_ifc_debug_cap_bits { 685 u8 reserved_at_0[0x20]; 686 687 u8 reserved_at_20[0x2]; 688 u8 stall_detect[0x1]; 689 u8 reserved_at_23[0x1d]; 690 691 u8 reserved_at_40[0x7c0]; 692 }; 693 694 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 695 u8 csum_cap[0x1]; 696 u8 vlan_cap[0x1]; 697 u8 lro_cap[0x1]; 698 u8 lro_psh_flag[0x1]; 699 u8 lro_time_stamp[0x1]; 700 u8 reserved_at_5[0x2]; 701 u8 wqe_vlan_insert[0x1]; 702 u8 self_lb_en_modifiable[0x1]; 703 u8 reserved_at_9[0x2]; 704 u8 max_lso_cap[0x5]; 705 u8 multi_pkt_send_wqe[0x2]; 706 u8 wqe_inline_mode[0x2]; 707 u8 rss_ind_tbl_cap[0x4]; 708 u8 reg_umr_sq[0x1]; 709 u8 scatter_fcs[0x1]; 710 u8 enhanced_multi_pkt_send_wqe[0x1]; 711 u8 tunnel_lso_const_out_ip_id[0x1]; 712 u8 reserved_at_1c[0x2]; 713 u8 tunnel_stateless_gre[0x1]; 714 u8 tunnel_stateless_vxlan[0x1]; 715 716 u8 swp[0x1]; 717 u8 swp_csum[0x1]; 718 u8 swp_lso[0x1]; 719 u8 reserved_at_23[0xd]; 720 u8 max_vxlan_udp_ports[0x8]; 721 u8 reserved_at_38[0x6]; 722 u8 max_geneve_opt_len[0x1]; 723 u8 tunnel_stateless_geneve_rx[0x1]; 724 725 u8 reserved_at_40[0x10]; 726 u8 lro_min_mss_size[0x10]; 727 728 u8 reserved_at_60[0x120]; 729 730 u8 lro_timer_supported_periods[4][0x20]; 731 732 u8 reserved_at_200[0x600]; 733 }; 734 735 struct mlx5_ifc_roce_cap_bits { 736 u8 roce_apm[0x1]; 737 u8 reserved_at_1[0x1f]; 738 739 u8 reserved_at_20[0x60]; 740 741 u8 reserved_at_80[0xc]; 742 u8 l3_type[0x4]; 743 u8 reserved_at_90[0x8]; 744 u8 roce_version[0x8]; 745 746 u8 reserved_at_a0[0x10]; 747 u8 r_roce_dest_udp_port[0x10]; 748 749 u8 r_roce_max_src_udp_port[0x10]; 750 u8 r_roce_min_src_udp_port[0x10]; 751 752 u8 reserved_at_e0[0x10]; 753 u8 roce_address_table_size[0x10]; 754 755 u8 reserved_at_100[0x700]; 756 }; 757 758 struct mlx5_ifc_device_mem_cap_bits { 759 u8 memic[0x1]; 760 u8 reserved_at_1[0x1f]; 761 762 u8 reserved_at_20[0xb]; 763 u8 log_min_memic_alloc_size[0x5]; 764 u8 reserved_at_30[0x8]; 765 u8 log_max_memic_addr_alignment[0x8]; 766 767 u8 memic_bar_start_addr[0x40]; 768 769 u8 memic_bar_size[0x20]; 770 771 u8 max_memic_size[0x20]; 772 773 u8 reserved_at_c0[0x740]; 774 }; 775 776 enum { 777 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 778 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 779 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 780 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 781 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 782 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 783 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 784 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 785 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 786 }; 787 788 enum { 789 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 790 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 791 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 792 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 793 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 794 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 795 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 796 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 797 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 798 }; 799 800 struct mlx5_ifc_atomic_caps_bits { 801 u8 reserved_at_0[0x40]; 802 803 u8 atomic_req_8B_endianness_mode[0x2]; 804 u8 reserved_at_42[0x4]; 805 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 806 807 u8 reserved_at_47[0x19]; 808 809 u8 reserved_at_60[0x20]; 810 811 u8 reserved_at_80[0x10]; 812 u8 atomic_operations[0x10]; 813 814 u8 reserved_at_a0[0x10]; 815 u8 atomic_size_qp[0x10]; 816 817 u8 reserved_at_c0[0x10]; 818 u8 atomic_size_dc[0x10]; 819 820 u8 reserved_at_e0[0x720]; 821 }; 822 823 struct mlx5_ifc_odp_cap_bits { 824 u8 reserved_at_0[0x40]; 825 826 u8 sig[0x1]; 827 u8 reserved_at_41[0x1f]; 828 829 u8 reserved_at_60[0x20]; 830 831 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 832 833 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 834 835 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 836 837 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 838 839 u8 reserved_at_100[0x700]; 840 }; 841 842 struct mlx5_ifc_calc_op { 843 u8 reserved_at_0[0x10]; 844 u8 reserved_at_10[0x9]; 845 u8 op_swap_endianness[0x1]; 846 u8 op_min[0x1]; 847 u8 op_xor[0x1]; 848 u8 op_or[0x1]; 849 u8 op_and[0x1]; 850 u8 op_max[0x1]; 851 u8 op_add[0x1]; 852 }; 853 854 struct mlx5_ifc_vector_calc_cap_bits { 855 u8 calc_matrix[0x1]; 856 u8 reserved_at_1[0x1f]; 857 u8 reserved_at_20[0x8]; 858 u8 max_vec_count[0x8]; 859 u8 reserved_at_30[0xd]; 860 u8 max_chunk_size[0x3]; 861 struct mlx5_ifc_calc_op calc0; 862 struct mlx5_ifc_calc_op calc1; 863 struct mlx5_ifc_calc_op calc2; 864 struct mlx5_ifc_calc_op calc3; 865 866 u8 reserved_at_c0[0x720]; 867 }; 868 869 enum { 870 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 871 MLX5_WQ_TYPE_CYCLIC = 0x1, 872 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 873 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 874 }; 875 876 enum { 877 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 878 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 879 }; 880 881 enum { 882 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 883 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 884 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 885 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 886 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 887 }; 888 889 enum { 890 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 891 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 892 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 893 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 894 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 895 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 896 }; 897 898 enum { 899 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 900 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 901 }; 902 903 enum { 904 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 905 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 906 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 907 }; 908 909 enum { 910 MLX5_CAP_PORT_TYPE_IB = 0x0, 911 MLX5_CAP_PORT_TYPE_ETH = 0x1, 912 }; 913 914 enum { 915 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 916 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 917 MLX5_CAP_UMR_FENCE_NONE = 0x2, 918 }; 919 920 enum { 921 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 922 }; 923 924 struct mlx5_ifc_cmd_hca_cap_bits { 925 u8 reserved_at_0[0x30]; 926 u8 vhca_id[0x10]; 927 928 u8 reserved_at_40[0x40]; 929 930 u8 log_max_srq_sz[0x8]; 931 u8 log_max_qp_sz[0x8]; 932 u8 reserved_at_90[0xb]; 933 u8 log_max_qp[0x5]; 934 935 u8 reserved_at_a0[0xb]; 936 u8 log_max_srq[0x5]; 937 u8 reserved_at_b0[0x10]; 938 939 u8 reserved_at_c0[0x8]; 940 u8 log_max_cq_sz[0x8]; 941 u8 reserved_at_d0[0xb]; 942 u8 log_max_cq[0x5]; 943 944 u8 log_max_eq_sz[0x8]; 945 u8 reserved_at_e8[0x2]; 946 u8 log_max_mkey[0x6]; 947 u8 reserved_at_f0[0x8]; 948 u8 dump_fill_mkey[0x1]; 949 u8 reserved_at_f9[0x2]; 950 u8 fast_teardown[0x1]; 951 u8 log_max_eq[0x4]; 952 953 u8 max_indirection[0x8]; 954 u8 fixed_buffer_size[0x1]; 955 u8 log_max_mrw_sz[0x7]; 956 u8 force_teardown[0x1]; 957 u8 reserved_at_111[0x1]; 958 u8 log_max_bsf_list_size[0x6]; 959 u8 umr_extended_translation_offset[0x1]; 960 u8 null_mkey[0x1]; 961 u8 log_max_klm_list_size[0x6]; 962 963 u8 reserved_at_120[0xa]; 964 u8 log_max_ra_req_dc[0x6]; 965 u8 reserved_at_130[0xa]; 966 u8 log_max_ra_res_dc[0x6]; 967 968 u8 reserved_at_140[0xa]; 969 u8 log_max_ra_req_qp[0x6]; 970 u8 reserved_at_150[0xa]; 971 u8 log_max_ra_res_qp[0x6]; 972 973 u8 end_pad[0x1]; 974 u8 cc_query_allowed[0x1]; 975 u8 cc_modify_allowed[0x1]; 976 u8 start_pad[0x1]; 977 u8 cache_line_128byte[0x1]; 978 u8 reserved_at_165[0xa]; 979 u8 qcam_reg[0x1]; 980 u8 gid_table_size[0x10]; 981 982 u8 out_of_seq_cnt[0x1]; 983 u8 vport_counters[0x1]; 984 u8 retransmission_q_counters[0x1]; 985 u8 debug[0x1]; 986 u8 modify_rq_counter_set_id[0x1]; 987 u8 rq_delay_drop[0x1]; 988 u8 max_qp_cnt[0xa]; 989 u8 pkey_table_size[0x10]; 990 991 u8 vport_group_manager[0x1]; 992 u8 vhca_group_manager[0x1]; 993 u8 ib_virt[0x1]; 994 u8 eth_virt[0x1]; 995 u8 vnic_env_queue_counters[0x1]; 996 u8 ets[0x1]; 997 u8 nic_flow_table[0x1]; 998 u8 eswitch_manager[0x1]; 999 u8 device_memory[0x1]; 1000 u8 mcam_reg[0x1]; 1001 u8 pcam_reg[0x1]; 1002 u8 local_ca_ack_delay[0x5]; 1003 u8 port_module_event[0x1]; 1004 u8 enhanced_error_q_counters[0x1]; 1005 u8 ports_check[0x1]; 1006 u8 reserved_at_1b3[0x1]; 1007 u8 disable_link_up[0x1]; 1008 u8 beacon_led[0x1]; 1009 u8 port_type[0x2]; 1010 u8 num_ports[0x8]; 1011 1012 u8 reserved_at_1c0[0x1]; 1013 u8 pps[0x1]; 1014 u8 pps_modify[0x1]; 1015 u8 log_max_msg[0x5]; 1016 u8 reserved_at_1c8[0x4]; 1017 u8 max_tc[0x4]; 1018 u8 temp_warn_event[0x1]; 1019 u8 dcbx[0x1]; 1020 u8 general_notification_event[0x1]; 1021 u8 reserved_at_1d3[0x2]; 1022 u8 fpga[0x1]; 1023 u8 rol_s[0x1]; 1024 u8 rol_g[0x1]; 1025 u8 reserved_at_1d8[0x1]; 1026 u8 wol_s[0x1]; 1027 u8 wol_g[0x1]; 1028 u8 wol_a[0x1]; 1029 u8 wol_b[0x1]; 1030 u8 wol_m[0x1]; 1031 u8 wol_u[0x1]; 1032 u8 wol_p[0x1]; 1033 1034 u8 stat_rate_support[0x10]; 1035 u8 reserved_at_1f0[0xc]; 1036 u8 cqe_version[0x4]; 1037 1038 u8 compact_address_vector[0x1]; 1039 u8 striding_rq[0x1]; 1040 u8 reserved_at_202[0x1]; 1041 u8 ipoib_enhanced_offloads[0x1]; 1042 u8 ipoib_basic_offloads[0x1]; 1043 u8 reserved_at_205[0x1]; 1044 u8 repeated_block_disabled[0x1]; 1045 u8 umr_modify_entity_size_disabled[0x1]; 1046 u8 umr_modify_atomic_disabled[0x1]; 1047 u8 umr_indirect_mkey_disabled[0x1]; 1048 u8 umr_fence[0x2]; 1049 u8 dc_req_scat_data_cqe[0x1]; 1050 u8 reserved_at_20d[0x2]; 1051 u8 drain_sigerr[0x1]; 1052 u8 cmdif_checksum[0x2]; 1053 u8 sigerr_cqe[0x1]; 1054 u8 reserved_at_213[0x1]; 1055 u8 wq_signature[0x1]; 1056 u8 sctr_data_cqe[0x1]; 1057 u8 reserved_at_216[0x1]; 1058 u8 sho[0x1]; 1059 u8 tph[0x1]; 1060 u8 rf[0x1]; 1061 u8 dct[0x1]; 1062 u8 qos[0x1]; 1063 u8 eth_net_offloads[0x1]; 1064 u8 roce[0x1]; 1065 u8 atomic[0x1]; 1066 u8 reserved_at_21f[0x1]; 1067 1068 u8 cq_oi[0x1]; 1069 u8 cq_resize[0x1]; 1070 u8 cq_moderation[0x1]; 1071 u8 reserved_at_223[0x3]; 1072 u8 cq_eq_remap[0x1]; 1073 u8 pg[0x1]; 1074 u8 block_lb_mc[0x1]; 1075 u8 reserved_at_229[0x1]; 1076 u8 scqe_break_moderation[0x1]; 1077 u8 cq_period_start_from_cqe[0x1]; 1078 u8 cd[0x1]; 1079 u8 reserved_at_22d[0x1]; 1080 u8 apm[0x1]; 1081 u8 vector_calc[0x1]; 1082 u8 umr_ptr_rlky[0x1]; 1083 u8 imaicl[0x1]; 1084 u8 qp_packet_based[0x1]; 1085 u8 reserved_at_233[0x3]; 1086 u8 qkv[0x1]; 1087 u8 pkv[0x1]; 1088 u8 set_deth_sqpn[0x1]; 1089 u8 reserved_at_239[0x3]; 1090 u8 xrc[0x1]; 1091 u8 ud[0x1]; 1092 u8 uc[0x1]; 1093 u8 rc[0x1]; 1094 1095 u8 uar_4k[0x1]; 1096 u8 reserved_at_241[0x9]; 1097 u8 uar_sz[0x6]; 1098 u8 reserved_at_250[0x8]; 1099 u8 log_pg_sz[0x8]; 1100 1101 u8 bf[0x1]; 1102 u8 driver_version[0x1]; 1103 u8 pad_tx_eth_packet[0x1]; 1104 u8 reserved_at_263[0x8]; 1105 u8 log_bf_reg_size[0x5]; 1106 1107 u8 reserved_at_270[0xb]; 1108 u8 lag_master[0x1]; 1109 u8 num_lag_ports[0x4]; 1110 1111 u8 reserved_at_280[0x10]; 1112 u8 max_wqe_sz_sq[0x10]; 1113 1114 u8 reserved_at_2a0[0x10]; 1115 u8 max_wqe_sz_rq[0x10]; 1116 1117 u8 max_flow_counter_31_16[0x10]; 1118 u8 max_wqe_sz_sq_dc[0x10]; 1119 1120 u8 reserved_at_2e0[0x7]; 1121 u8 max_qp_mcg[0x19]; 1122 1123 u8 reserved_at_300[0x18]; 1124 u8 log_max_mcg[0x8]; 1125 1126 u8 reserved_at_320[0x3]; 1127 u8 log_max_transport_domain[0x5]; 1128 u8 reserved_at_328[0x3]; 1129 u8 log_max_pd[0x5]; 1130 u8 reserved_at_330[0xb]; 1131 u8 log_max_xrcd[0x5]; 1132 1133 u8 nic_receive_steering_discard[0x1]; 1134 u8 receive_discard_vport_down[0x1]; 1135 u8 transmit_discard_vport_down[0x1]; 1136 u8 reserved_at_343[0x5]; 1137 u8 log_max_flow_counter_bulk[0x8]; 1138 u8 max_flow_counter_15_0[0x10]; 1139 1140 1141 u8 reserved_at_360[0x3]; 1142 u8 log_max_rq[0x5]; 1143 u8 reserved_at_368[0x3]; 1144 u8 log_max_sq[0x5]; 1145 u8 reserved_at_370[0x3]; 1146 u8 log_max_tir[0x5]; 1147 u8 reserved_at_378[0x3]; 1148 u8 log_max_tis[0x5]; 1149 1150 u8 basic_cyclic_rcv_wqe[0x1]; 1151 u8 reserved_at_381[0x2]; 1152 u8 log_max_rmp[0x5]; 1153 u8 reserved_at_388[0x3]; 1154 u8 log_max_rqt[0x5]; 1155 u8 reserved_at_390[0x3]; 1156 u8 log_max_rqt_size[0x5]; 1157 u8 reserved_at_398[0x3]; 1158 u8 log_max_tis_per_sq[0x5]; 1159 1160 u8 ext_stride_num_range[0x1]; 1161 u8 reserved_at_3a1[0x2]; 1162 u8 log_max_stride_sz_rq[0x5]; 1163 u8 reserved_at_3a8[0x3]; 1164 u8 log_min_stride_sz_rq[0x5]; 1165 u8 reserved_at_3b0[0x3]; 1166 u8 log_max_stride_sz_sq[0x5]; 1167 u8 reserved_at_3b8[0x3]; 1168 u8 log_min_stride_sz_sq[0x5]; 1169 1170 u8 hairpin[0x1]; 1171 u8 reserved_at_3c1[0x2]; 1172 u8 log_max_hairpin_queues[0x5]; 1173 u8 reserved_at_3c8[0x3]; 1174 u8 log_max_hairpin_wq_data_sz[0x5]; 1175 u8 reserved_at_3d0[0x3]; 1176 u8 log_max_hairpin_num_packets[0x5]; 1177 u8 reserved_at_3d8[0x3]; 1178 u8 log_max_wq_sz[0x5]; 1179 1180 u8 nic_vport_change_event[0x1]; 1181 u8 disable_local_lb_uc[0x1]; 1182 u8 disable_local_lb_mc[0x1]; 1183 u8 log_min_hairpin_wq_data_sz[0x5]; 1184 u8 reserved_at_3e8[0x3]; 1185 u8 log_max_vlan_list[0x5]; 1186 u8 reserved_at_3f0[0x3]; 1187 u8 log_max_current_mc_list[0x5]; 1188 u8 reserved_at_3f8[0x3]; 1189 u8 log_max_current_uc_list[0x5]; 1190 1191 u8 general_obj_types[0x40]; 1192 1193 u8 reserved_at_440[0x20]; 1194 1195 u8 reserved_at_460[0x3]; 1196 u8 log_max_uctx[0x5]; 1197 u8 reserved_at_468[0x3]; 1198 u8 log_max_umem[0x5]; 1199 u8 max_num_eqs[0x10]; 1200 1201 u8 reserved_at_480[0x3]; 1202 u8 log_max_l2_table[0x5]; 1203 u8 reserved_at_488[0x8]; 1204 u8 log_uar_page_sz[0x10]; 1205 1206 u8 reserved_at_4a0[0x20]; 1207 u8 device_frequency_mhz[0x20]; 1208 u8 device_frequency_khz[0x20]; 1209 1210 u8 reserved_at_500[0x20]; 1211 u8 num_of_uars_per_page[0x20]; 1212 1213 u8 flex_parser_protocols[0x20]; 1214 u8 reserved_at_560[0x20]; 1215 1216 u8 reserved_at_580[0x3c]; 1217 u8 mini_cqe_resp_stride_index[0x1]; 1218 u8 cqe_128_always[0x1]; 1219 u8 cqe_compression_128[0x1]; 1220 u8 cqe_compression[0x1]; 1221 1222 u8 cqe_compression_timeout[0x10]; 1223 u8 cqe_compression_max_num[0x10]; 1224 1225 u8 reserved_at_5e0[0x10]; 1226 u8 tag_matching[0x1]; 1227 u8 rndv_offload_rc[0x1]; 1228 u8 rndv_offload_dc[0x1]; 1229 u8 log_tag_matching_list_sz[0x5]; 1230 u8 reserved_at_5f8[0x3]; 1231 u8 log_max_xrq[0x5]; 1232 1233 u8 affiliate_nic_vport_criteria[0x8]; 1234 u8 native_port_num[0x8]; 1235 u8 num_vhca_ports[0x8]; 1236 u8 reserved_at_618[0x6]; 1237 u8 sw_owner_id[0x1]; 1238 u8 reserved_at_61f[0x1]; 1239 1240 u8 max_num_of_monitor_counters[0x10]; 1241 u8 num_ppcnt_monitor_counters[0x10]; 1242 1243 u8 reserved_at_640[0x10]; 1244 u8 num_q_monitor_counters[0x10]; 1245 1246 u8 reserved_at_660[0x40]; 1247 1248 u8 uctx_cap[0x20]; 1249 1250 u8 reserved_at_6c0[0x140]; 1251 }; 1252 1253 enum mlx5_flow_destination_type { 1254 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1255 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1256 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1257 1258 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1259 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1260 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1261 }; 1262 1263 struct mlx5_ifc_dest_format_struct_bits { 1264 u8 destination_type[0x8]; 1265 u8 destination_id[0x18]; 1266 1267 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1268 u8 packet_reformat[0x1]; 1269 u8 reserved_at_22[0xe]; 1270 u8 destination_eswitch_owner_vhca_id[0x10]; 1271 }; 1272 1273 struct mlx5_ifc_flow_counter_list_bits { 1274 u8 flow_counter_id[0x20]; 1275 1276 u8 reserved_at_20[0x20]; 1277 }; 1278 1279 struct mlx5_ifc_extended_dest_format_bits { 1280 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1281 1282 u8 packet_reformat_id[0x20]; 1283 1284 u8 reserved_at_60[0x20]; 1285 }; 1286 1287 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1288 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1289 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1290 u8 reserved_at_0[0x40]; 1291 }; 1292 1293 struct mlx5_ifc_fte_match_param_bits { 1294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1295 1296 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1297 1298 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1299 1300 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1301 1302 u8 reserved_at_800[0x800]; 1303 }; 1304 1305 enum { 1306 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1307 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1308 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1309 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1310 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1311 }; 1312 1313 struct mlx5_ifc_rx_hash_field_select_bits { 1314 u8 l3_prot_type[0x1]; 1315 u8 l4_prot_type[0x1]; 1316 u8 selected_fields[0x1e]; 1317 }; 1318 1319 enum { 1320 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1321 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1322 }; 1323 1324 enum { 1325 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1326 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1327 }; 1328 1329 struct mlx5_ifc_wq_bits { 1330 u8 wq_type[0x4]; 1331 u8 wq_signature[0x1]; 1332 u8 end_padding_mode[0x2]; 1333 u8 cd_slave[0x1]; 1334 u8 reserved_at_8[0x18]; 1335 1336 u8 hds_skip_first_sge[0x1]; 1337 u8 log2_hds_buf_size[0x3]; 1338 u8 reserved_at_24[0x7]; 1339 u8 page_offset[0x5]; 1340 u8 lwm[0x10]; 1341 1342 u8 reserved_at_40[0x8]; 1343 u8 pd[0x18]; 1344 1345 u8 reserved_at_60[0x8]; 1346 u8 uar_page[0x18]; 1347 1348 u8 dbr_addr[0x40]; 1349 1350 u8 hw_counter[0x20]; 1351 1352 u8 sw_counter[0x20]; 1353 1354 u8 reserved_at_100[0xc]; 1355 u8 log_wq_stride[0x4]; 1356 u8 reserved_at_110[0x3]; 1357 u8 log_wq_pg_sz[0x5]; 1358 u8 reserved_at_118[0x3]; 1359 u8 log_wq_sz[0x5]; 1360 1361 u8 dbr_umem_valid[0x1]; 1362 u8 wq_umem_valid[0x1]; 1363 u8 reserved_at_122[0x1]; 1364 u8 log_hairpin_num_packets[0x5]; 1365 u8 reserved_at_128[0x3]; 1366 u8 log_hairpin_data_sz[0x5]; 1367 1368 u8 reserved_at_130[0x4]; 1369 u8 log_wqe_num_of_strides[0x4]; 1370 u8 two_byte_shift_en[0x1]; 1371 u8 reserved_at_139[0x4]; 1372 u8 log_wqe_stride_size[0x3]; 1373 1374 u8 reserved_at_140[0x4c0]; 1375 1376 struct mlx5_ifc_cmd_pas_bits pas[0]; 1377 }; 1378 1379 struct mlx5_ifc_rq_num_bits { 1380 u8 reserved_at_0[0x8]; 1381 u8 rq_num[0x18]; 1382 }; 1383 1384 struct mlx5_ifc_mac_address_layout_bits { 1385 u8 reserved_at_0[0x10]; 1386 u8 mac_addr_47_32[0x10]; 1387 1388 u8 mac_addr_31_0[0x20]; 1389 }; 1390 1391 struct mlx5_ifc_vlan_layout_bits { 1392 u8 reserved_at_0[0x14]; 1393 u8 vlan[0x0c]; 1394 1395 u8 reserved_at_20[0x20]; 1396 }; 1397 1398 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1399 u8 reserved_at_0[0xa0]; 1400 1401 u8 min_time_between_cnps[0x20]; 1402 1403 u8 reserved_at_c0[0x12]; 1404 u8 cnp_dscp[0x6]; 1405 u8 reserved_at_d8[0x4]; 1406 u8 cnp_prio_mode[0x1]; 1407 u8 cnp_802p_prio[0x3]; 1408 1409 u8 reserved_at_e0[0x720]; 1410 }; 1411 1412 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1413 u8 reserved_at_0[0x60]; 1414 1415 u8 reserved_at_60[0x4]; 1416 u8 clamp_tgt_rate[0x1]; 1417 u8 reserved_at_65[0x3]; 1418 u8 clamp_tgt_rate_after_time_inc[0x1]; 1419 u8 reserved_at_69[0x17]; 1420 1421 u8 reserved_at_80[0x20]; 1422 1423 u8 rpg_time_reset[0x20]; 1424 1425 u8 rpg_byte_reset[0x20]; 1426 1427 u8 rpg_threshold[0x20]; 1428 1429 u8 rpg_max_rate[0x20]; 1430 1431 u8 rpg_ai_rate[0x20]; 1432 1433 u8 rpg_hai_rate[0x20]; 1434 1435 u8 rpg_gd[0x20]; 1436 1437 u8 rpg_min_dec_fac[0x20]; 1438 1439 u8 rpg_min_rate[0x20]; 1440 1441 u8 reserved_at_1c0[0xe0]; 1442 1443 u8 rate_to_set_on_first_cnp[0x20]; 1444 1445 u8 dce_tcp_g[0x20]; 1446 1447 u8 dce_tcp_rtt[0x20]; 1448 1449 u8 rate_reduce_monitor_period[0x20]; 1450 1451 u8 reserved_at_320[0x20]; 1452 1453 u8 initial_alpha_value[0x20]; 1454 1455 u8 reserved_at_360[0x4a0]; 1456 }; 1457 1458 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1459 u8 reserved_at_0[0x80]; 1460 1461 u8 rppp_max_rps[0x20]; 1462 1463 u8 rpg_time_reset[0x20]; 1464 1465 u8 rpg_byte_reset[0x20]; 1466 1467 u8 rpg_threshold[0x20]; 1468 1469 u8 rpg_max_rate[0x20]; 1470 1471 u8 rpg_ai_rate[0x20]; 1472 1473 u8 rpg_hai_rate[0x20]; 1474 1475 u8 rpg_gd[0x20]; 1476 1477 u8 rpg_min_dec_fac[0x20]; 1478 1479 u8 rpg_min_rate[0x20]; 1480 1481 u8 reserved_at_1c0[0x640]; 1482 }; 1483 1484 enum { 1485 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1486 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1487 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1488 }; 1489 1490 struct mlx5_ifc_resize_field_select_bits { 1491 u8 resize_field_select[0x20]; 1492 }; 1493 1494 enum { 1495 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1496 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1497 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1498 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1499 }; 1500 1501 struct mlx5_ifc_modify_field_select_bits { 1502 u8 modify_field_select[0x20]; 1503 }; 1504 1505 struct mlx5_ifc_field_select_r_roce_np_bits { 1506 u8 field_select_r_roce_np[0x20]; 1507 }; 1508 1509 struct mlx5_ifc_field_select_r_roce_rp_bits { 1510 u8 field_select_r_roce_rp[0x20]; 1511 }; 1512 1513 enum { 1514 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1515 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1516 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1517 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1518 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1519 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1520 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1521 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1522 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1523 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1524 }; 1525 1526 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1527 u8 field_select_8021qaurp[0x20]; 1528 }; 1529 1530 struct mlx5_ifc_phys_layer_cntrs_bits { 1531 u8 time_since_last_clear_high[0x20]; 1532 1533 u8 time_since_last_clear_low[0x20]; 1534 1535 u8 symbol_errors_high[0x20]; 1536 1537 u8 symbol_errors_low[0x20]; 1538 1539 u8 sync_headers_errors_high[0x20]; 1540 1541 u8 sync_headers_errors_low[0x20]; 1542 1543 u8 edpl_bip_errors_lane0_high[0x20]; 1544 1545 u8 edpl_bip_errors_lane0_low[0x20]; 1546 1547 u8 edpl_bip_errors_lane1_high[0x20]; 1548 1549 u8 edpl_bip_errors_lane1_low[0x20]; 1550 1551 u8 edpl_bip_errors_lane2_high[0x20]; 1552 1553 u8 edpl_bip_errors_lane2_low[0x20]; 1554 1555 u8 edpl_bip_errors_lane3_high[0x20]; 1556 1557 u8 edpl_bip_errors_lane3_low[0x20]; 1558 1559 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1560 1561 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1562 1563 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1564 1565 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1566 1567 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1568 1569 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1570 1571 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1572 1573 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1574 1575 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1576 1577 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1578 1579 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1580 1581 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1582 1583 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1584 1585 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1586 1587 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1588 1589 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1590 1591 u8 rs_fec_corrected_blocks_high[0x20]; 1592 1593 u8 rs_fec_corrected_blocks_low[0x20]; 1594 1595 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1596 1597 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1598 1599 u8 rs_fec_no_errors_blocks_high[0x20]; 1600 1601 u8 rs_fec_no_errors_blocks_low[0x20]; 1602 1603 u8 rs_fec_single_error_blocks_high[0x20]; 1604 1605 u8 rs_fec_single_error_blocks_low[0x20]; 1606 1607 u8 rs_fec_corrected_symbols_total_high[0x20]; 1608 1609 u8 rs_fec_corrected_symbols_total_low[0x20]; 1610 1611 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1612 1613 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1614 1615 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1616 1617 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1618 1619 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1620 1621 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1622 1623 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1624 1625 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1626 1627 u8 link_down_events[0x20]; 1628 1629 u8 successful_recovery_events[0x20]; 1630 1631 u8 reserved_at_640[0x180]; 1632 }; 1633 1634 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1635 u8 time_since_last_clear_high[0x20]; 1636 1637 u8 time_since_last_clear_low[0x20]; 1638 1639 u8 phy_received_bits_high[0x20]; 1640 1641 u8 phy_received_bits_low[0x20]; 1642 1643 u8 phy_symbol_errors_high[0x20]; 1644 1645 u8 phy_symbol_errors_low[0x20]; 1646 1647 u8 phy_corrected_bits_high[0x20]; 1648 1649 u8 phy_corrected_bits_low[0x20]; 1650 1651 u8 phy_corrected_bits_lane0_high[0x20]; 1652 1653 u8 phy_corrected_bits_lane0_low[0x20]; 1654 1655 u8 phy_corrected_bits_lane1_high[0x20]; 1656 1657 u8 phy_corrected_bits_lane1_low[0x20]; 1658 1659 u8 phy_corrected_bits_lane2_high[0x20]; 1660 1661 u8 phy_corrected_bits_lane2_low[0x20]; 1662 1663 u8 phy_corrected_bits_lane3_high[0x20]; 1664 1665 u8 phy_corrected_bits_lane3_low[0x20]; 1666 1667 u8 reserved_at_200[0x5c0]; 1668 }; 1669 1670 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1671 u8 symbol_error_counter[0x10]; 1672 1673 u8 link_error_recovery_counter[0x8]; 1674 1675 u8 link_downed_counter[0x8]; 1676 1677 u8 port_rcv_errors[0x10]; 1678 1679 u8 port_rcv_remote_physical_errors[0x10]; 1680 1681 u8 port_rcv_switch_relay_errors[0x10]; 1682 1683 u8 port_xmit_discards[0x10]; 1684 1685 u8 port_xmit_constraint_errors[0x8]; 1686 1687 u8 port_rcv_constraint_errors[0x8]; 1688 1689 u8 reserved_at_70[0x8]; 1690 1691 u8 link_overrun_errors[0x8]; 1692 1693 u8 reserved_at_80[0x10]; 1694 1695 u8 vl_15_dropped[0x10]; 1696 1697 u8 reserved_at_a0[0x80]; 1698 1699 u8 port_xmit_wait[0x20]; 1700 }; 1701 1702 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1703 u8 transmit_queue_high[0x20]; 1704 1705 u8 transmit_queue_low[0x20]; 1706 1707 u8 reserved_at_40[0x780]; 1708 }; 1709 1710 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1711 u8 rx_octets_high[0x20]; 1712 1713 u8 rx_octets_low[0x20]; 1714 1715 u8 reserved_at_40[0xc0]; 1716 1717 u8 rx_frames_high[0x20]; 1718 1719 u8 rx_frames_low[0x20]; 1720 1721 u8 tx_octets_high[0x20]; 1722 1723 u8 tx_octets_low[0x20]; 1724 1725 u8 reserved_at_180[0xc0]; 1726 1727 u8 tx_frames_high[0x20]; 1728 1729 u8 tx_frames_low[0x20]; 1730 1731 u8 rx_pause_high[0x20]; 1732 1733 u8 rx_pause_low[0x20]; 1734 1735 u8 rx_pause_duration_high[0x20]; 1736 1737 u8 rx_pause_duration_low[0x20]; 1738 1739 u8 tx_pause_high[0x20]; 1740 1741 u8 tx_pause_low[0x20]; 1742 1743 u8 tx_pause_duration_high[0x20]; 1744 1745 u8 tx_pause_duration_low[0x20]; 1746 1747 u8 rx_pause_transition_high[0x20]; 1748 1749 u8 rx_pause_transition_low[0x20]; 1750 1751 u8 reserved_at_3c0[0x40]; 1752 1753 u8 device_stall_minor_watermark_cnt_high[0x20]; 1754 1755 u8 device_stall_minor_watermark_cnt_low[0x20]; 1756 1757 u8 device_stall_critical_watermark_cnt_high[0x20]; 1758 1759 u8 device_stall_critical_watermark_cnt_low[0x20]; 1760 1761 u8 reserved_at_480[0x340]; 1762 }; 1763 1764 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1765 u8 port_transmit_wait_high[0x20]; 1766 1767 u8 port_transmit_wait_low[0x20]; 1768 1769 u8 reserved_at_40[0x100]; 1770 1771 u8 rx_buffer_almost_full_high[0x20]; 1772 1773 u8 rx_buffer_almost_full_low[0x20]; 1774 1775 u8 rx_buffer_full_high[0x20]; 1776 1777 u8 rx_buffer_full_low[0x20]; 1778 1779 u8 rx_icrc_encapsulated_high[0x20]; 1780 1781 u8 rx_icrc_encapsulated_low[0x20]; 1782 1783 u8 reserved_at_200[0x5c0]; 1784 }; 1785 1786 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1787 u8 dot3stats_alignment_errors_high[0x20]; 1788 1789 u8 dot3stats_alignment_errors_low[0x20]; 1790 1791 u8 dot3stats_fcs_errors_high[0x20]; 1792 1793 u8 dot3stats_fcs_errors_low[0x20]; 1794 1795 u8 dot3stats_single_collision_frames_high[0x20]; 1796 1797 u8 dot3stats_single_collision_frames_low[0x20]; 1798 1799 u8 dot3stats_multiple_collision_frames_high[0x20]; 1800 1801 u8 dot3stats_multiple_collision_frames_low[0x20]; 1802 1803 u8 dot3stats_sqe_test_errors_high[0x20]; 1804 1805 u8 dot3stats_sqe_test_errors_low[0x20]; 1806 1807 u8 dot3stats_deferred_transmissions_high[0x20]; 1808 1809 u8 dot3stats_deferred_transmissions_low[0x20]; 1810 1811 u8 dot3stats_late_collisions_high[0x20]; 1812 1813 u8 dot3stats_late_collisions_low[0x20]; 1814 1815 u8 dot3stats_excessive_collisions_high[0x20]; 1816 1817 u8 dot3stats_excessive_collisions_low[0x20]; 1818 1819 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1820 1821 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1822 1823 u8 dot3stats_carrier_sense_errors_high[0x20]; 1824 1825 u8 dot3stats_carrier_sense_errors_low[0x20]; 1826 1827 u8 dot3stats_frame_too_longs_high[0x20]; 1828 1829 u8 dot3stats_frame_too_longs_low[0x20]; 1830 1831 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1832 1833 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1834 1835 u8 dot3stats_symbol_errors_high[0x20]; 1836 1837 u8 dot3stats_symbol_errors_low[0x20]; 1838 1839 u8 dot3control_in_unknown_opcodes_high[0x20]; 1840 1841 u8 dot3control_in_unknown_opcodes_low[0x20]; 1842 1843 u8 dot3in_pause_frames_high[0x20]; 1844 1845 u8 dot3in_pause_frames_low[0x20]; 1846 1847 u8 dot3out_pause_frames_high[0x20]; 1848 1849 u8 dot3out_pause_frames_low[0x20]; 1850 1851 u8 reserved_at_400[0x3c0]; 1852 }; 1853 1854 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1855 u8 ether_stats_drop_events_high[0x20]; 1856 1857 u8 ether_stats_drop_events_low[0x20]; 1858 1859 u8 ether_stats_octets_high[0x20]; 1860 1861 u8 ether_stats_octets_low[0x20]; 1862 1863 u8 ether_stats_pkts_high[0x20]; 1864 1865 u8 ether_stats_pkts_low[0x20]; 1866 1867 u8 ether_stats_broadcast_pkts_high[0x20]; 1868 1869 u8 ether_stats_broadcast_pkts_low[0x20]; 1870 1871 u8 ether_stats_multicast_pkts_high[0x20]; 1872 1873 u8 ether_stats_multicast_pkts_low[0x20]; 1874 1875 u8 ether_stats_crc_align_errors_high[0x20]; 1876 1877 u8 ether_stats_crc_align_errors_low[0x20]; 1878 1879 u8 ether_stats_undersize_pkts_high[0x20]; 1880 1881 u8 ether_stats_undersize_pkts_low[0x20]; 1882 1883 u8 ether_stats_oversize_pkts_high[0x20]; 1884 1885 u8 ether_stats_oversize_pkts_low[0x20]; 1886 1887 u8 ether_stats_fragments_high[0x20]; 1888 1889 u8 ether_stats_fragments_low[0x20]; 1890 1891 u8 ether_stats_jabbers_high[0x20]; 1892 1893 u8 ether_stats_jabbers_low[0x20]; 1894 1895 u8 ether_stats_collisions_high[0x20]; 1896 1897 u8 ether_stats_collisions_low[0x20]; 1898 1899 u8 ether_stats_pkts64octets_high[0x20]; 1900 1901 u8 ether_stats_pkts64octets_low[0x20]; 1902 1903 u8 ether_stats_pkts65to127octets_high[0x20]; 1904 1905 u8 ether_stats_pkts65to127octets_low[0x20]; 1906 1907 u8 ether_stats_pkts128to255octets_high[0x20]; 1908 1909 u8 ether_stats_pkts128to255octets_low[0x20]; 1910 1911 u8 ether_stats_pkts256to511octets_high[0x20]; 1912 1913 u8 ether_stats_pkts256to511octets_low[0x20]; 1914 1915 u8 ether_stats_pkts512to1023octets_high[0x20]; 1916 1917 u8 ether_stats_pkts512to1023octets_low[0x20]; 1918 1919 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1920 1921 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1922 1923 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1924 1925 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1926 1927 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1928 1929 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1930 1931 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1932 1933 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1934 1935 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1936 1937 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1938 1939 u8 reserved_at_540[0x280]; 1940 }; 1941 1942 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1943 u8 if_in_octets_high[0x20]; 1944 1945 u8 if_in_octets_low[0x20]; 1946 1947 u8 if_in_ucast_pkts_high[0x20]; 1948 1949 u8 if_in_ucast_pkts_low[0x20]; 1950 1951 u8 if_in_discards_high[0x20]; 1952 1953 u8 if_in_discards_low[0x20]; 1954 1955 u8 if_in_errors_high[0x20]; 1956 1957 u8 if_in_errors_low[0x20]; 1958 1959 u8 if_in_unknown_protos_high[0x20]; 1960 1961 u8 if_in_unknown_protos_low[0x20]; 1962 1963 u8 if_out_octets_high[0x20]; 1964 1965 u8 if_out_octets_low[0x20]; 1966 1967 u8 if_out_ucast_pkts_high[0x20]; 1968 1969 u8 if_out_ucast_pkts_low[0x20]; 1970 1971 u8 if_out_discards_high[0x20]; 1972 1973 u8 if_out_discards_low[0x20]; 1974 1975 u8 if_out_errors_high[0x20]; 1976 1977 u8 if_out_errors_low[0x20]; 1978 1979 u8 if_in_multicast_pkts_high[0x20]; 1980 1981 u8 if_in_multicast_pkts_low[0x20]; 1982 1983 u8 if_in_broadcast_pkts_high[0x20]; 1984 1985 u8 if_in_broadcast_pkts_low[0x20]; 1986 1987 u8 if_out_multicast_pkts_high[0x20]; 1988 1989 u8 if_out_multicast_pkts_low[0x20]; 1990 1991 u8 if_out_broadcast_pkts_high[0x20]; 1992 1993 u8 if_out_broadcast_pkts_low[0x20]; 1994 1995 u8 reserved_at_340[0x480]; 1996 }; 1997 1998 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1999 u8 a_frames_transmitted_ok_high[0x20]; 2000 2001 u8 a_frames_transmitted_ok_low[0x20]; 2002 2003 u8 a_frames_received_ok_high[0x20]; 2004 2005 u8 a_frames_received_ok_low[0x20]; 2006 2007 u8 a_frame_check_sequence_errors_high[0x20]; 2008 2009 u8 a_frame_check_sequence_errors_low[0x20]; 2010 2011 u8 a_alignment_errors_high[0x20]; 2012 2013 u8 a_alignment_errors_low[0x20]; 2014 2015 u8 a_octets_transmitted_ok_high[0x20]; 2016 2017 u8 a_octets_transmitted_ok_low[0x20]; 2018 2019 u8 a_octets_received_ok_high[0x20]; 2020 2021 u8 a_octets_received_ok_low[0x20]; 2022 2023 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2024 2025 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2026 2027 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2028 2029 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2030 2031 u8 a_multicast_frames_received_ok_high[0x20]; 2032 2033 u8 a_multicast_frames_received_ok_low[0x20]; 2034 2035 u8 a_broadcast_frames_received_ok_high[0x20]; 2036 2037 u8 a_broadcast_frames_received_ok_low[0x20]; 2038 2039 u8 a_in_range_length_errors_high[0x20]; 2040 2041 u8 a_in_range_length_errors_low[0x20]; 2042 2043 u8 a_out_of_range_length_field_high[0x20]; 2044 2045 u8 a_out_of_range_length_field_low[0x20]; 2046 2047 u8 a_frame_too_long_errors_high[0x20]; 2048 2049 u8 a_frame_too_long_errors_low[0x20]; 2050 2051 u8 a_symbol_error_during_carrier_high[0x20]; 2052 2053 u8 a_symbol_error_during_carrier_low[0x20]; 2054 2055 u8 a_mac_control_frames_transmitted_high[0x20]; 2056 2057 u8 a_mac_control_frames_transmitted_low[0x20]; 2058 2059 u8 a_mac_control_frames_received_high[0x20]; 2060 2061 u8 a_mac_control_frames_received_low[0x20]; 2062 2063 u8 a_unsupported_opcodes_received_high[0x20]; 2064 2065 u8 a_unsupported_opcodes_received_low[0x20]; 2066 2067 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2068 2069 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2070 2071 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2072 2073 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2074 2075 u8 reserved_at_4c0[0x300]; 2076 }; 2077 2078 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2079 u8 life_time_counter_high[0x20]; 2080 2081 u8 life_time_counter_low[0x20]; 2082 2083 u8 rx_errors[0x20]; 2084 2085 u8 tx_errors[0x20]; 2086 2087 u8 l0_to_recovery_eieos[0x20]; 2088 2089 u8 l0_to_recovery_ts[0x20]; 2090 2091 u8 l0_to_recovery_framing[0x20]; 2092 2093 u8 l0_to_recovery_retrain[0x20]; 2094 2095 u8 crc_error_dllp[0x20]; 2096 2097 u8 crc_error_tlp[0x20]; 2098 2099 u8 tx_overflow_buffer_pkt_high[0x20]; 2100 2101 u8 tx_overflow_buffer_pkt_low[0x20]; 2102 2103 u8 outbound_stalled_reads[0x20]; 2104 2105 u8 outbound_stalled_writes[0x20]; 2106 2107 u8 outbound_stalled_reads_events[0x20]; 2108 2109 u8 outbound_stalled_writes_events[0x20]; 2110 2111 u8 reserved_at_200[0x5c0]; 2112 }; 2113 2114 struct mlx5_ifc_cmd_inter_comp_event_bits { 2115 u8 command_completion_vector[0x20]; 2116 2117 u8 reserved_at_20[0xc0]; 2118 }; 2119 2120 struct mlx5_ifc_stall_vl_event_bits { 2121 u8 reserved_at_0[0x18]; 2122 u8 port_num[0x1]; 2123 u8 reserved_at_19[0x3]; 2124 u8 vl[0x4]; 2125 2126 u8 reserved_at_20[0xa0]; 2127 }; 2128 2129 struct mlx5_ifc_db_bf_congestion_event_bits { 2130 u8 event_subtype[0x8]; 2131 u8 reserved_at_8[0x8]; 2132 u8 congestion_level[0x8]; 2133 u8 reserved_at_18[0x8]; 2134 2135 u8 reserved_at_20[0xa0]; 2136 }; 2137 2138 struct mlx5_ifc_gpio_event_bits { 2139 u8 reserved_at_0[0x60]; 2140 2141 u8 gpio_event_hi[0x20]; 2142 2143 u8 gpio_event_lo[0x20]; 2144 2145 u8 reserved_at_a0[0x40]; 2146 }; 2147 2148 struct mlx5_ifc_port_state_change_event_bits { 2149 u8 reserved_at_0[0x40]; 2150 2151 u8 port_num[0x4]; 2152 u8 reserved_at_44[0x1c]; 2153 2154 u8 reserved_at_60[0x80]; 2155 }; 2156 2157 struct mlx5_ifc_dropped_packet_logged_bits { 2158 u8 reserved_at_0[0xe0]; 2159 }; 2160 2161 enum { 2162 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2163 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2164 }; 2165 2166 struct mlx5_ifc_cq_error_bits { 2167 u8 reserved_at_0[0x8]; 2168 u8 cqn[0x18]; 2169 2170 u8 reserved_at_20[0x20]; 2171 2172 u8 reserved_at_40[0x18]; 2173 u8 syndrome[0x8]; 2174 2175 u8 reserved_at_60[0x80]; 2176 }; 2177 2178 struct mlx5_ifc_rdma_page_fault_event_bits { 2179 u8 bytes_committed[0x20]; 2180 2181 u8 r_key[0x20]; 2182 2183 u8 reserved_at_40[0x10]; 2184 u8 packet_len[0x10]; 2185 2186 u8 rdma_op_len[0x20]; 2187 2188 u8 rdma_va[0x40]; 2189 2190 u8 reserved_at_c0[0x5]; 2191 u8 rdma[0x1]; 2192 u8 write[0x1]; 2193 u8 requestor[0x1]; 2194 u8 qp_number[0x18]; 2195 }; 2196 2197 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2198 u8 bytes_committed[0x20]; 2199 2200 u8 reserved_at_20[0x10]; 2201 u8 wqe_index[0x10]; 2202 2203 u8 reserved_at_40[0x10]; 2204 u8 len[0x10]; 2205 2206 u8 reserved_at_60[0x60]; 2207 2208 u8 reserved_at_c0[0x5]; 2209 u8 rdma[0x1]; 2210 u8 write_read[0x1]; 2211 u8 requestor[0x1]; 2212 u8 qpn[0x18]; 2213 }; 2214 2215 struct mlx5_ifc_qp_events_bits { 2216 u8 reserved_at_0[0xa0]; 2217 2218 u8 type[0x8]; 2219 u8 reserved_at_a8[0x18]; 2220 2221 u8 reserved_at_c0[0x8]; 2222 u8 qpn_rqn_sqn[0x18]; 2223 }; 2224 2225 struct mlx5_ifc_dct_events_bits { 2226 u8 reserved_at_0[0xc0]; 2227 2228 u8 reserved_at_c0[0x8]; 2229 u8 dct_number[0x18]; 2230 }; 2231 2232 struct mlx5_ifc_comp_event_bits { 2233 u8 reserved_at_0[0xc0]; 2234 2235 u8 reserved_at_c0[0x8]; 2236 u8 cq_number[0x18]; 2237 }; 2238 2239 enum { 2240 MLX5_QPC_STATE_RST = 0x0, 2241 MLX5_QPC_STATE_INIT = 0x1, 2242 MLX5_QPC_STATE_RTR = 0x2, 2243 MLX5_QPC_STATE_RTS = 0x3, 2244 MLX5_QPC_STATE_SQER = 0x4, 2245 MLX5_QPC_STATE_ERR = 0x6, 2246 MLX5_QPC_STATE_SQD = 0x7, 2247 MLX5_QPC_STATE_SUSPENDED = 0x9, 2248 }; 2249 2250 enum { 2251 MLX5_QPC_ST_RC = 0x0, 2252 MLX5_QPC_ST_UC = 0x1, 2253 MLX5_QPC_ST_UD = 0x2, 2254 MLX5_QPC_ST_XRC = 0x3, 2255 MLX5_QPC_ST_DCI = 0x5, 2256 MLX5_QPC_ST_QP0 = 0x7, 2257 MLX5_QPC_ST_QP1 = 0x8, 2258 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2259 MLX5_QPC_ST_REG_UMR = 0xc, 2260 }; 2261 2262 enum { 2263 MLX5_QPC_PM_STATE_ARMED = 0x0, 2264 MLX5_QPC_PM_STATE_REARM = 0x1, 2265 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2266 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2267 }; 2268 2269 enum { 2270 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2271 }; 2272 2273 enum { 2274 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2275 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2276 }; 2277 2278 enum { 2279 MLX5_QPC_MTU_256_BYTES = 0x1, 2280 MLX5_QPC_MTU_512_BYTES = 0x2, 2281 MLX5_QPC_MTU_1K_BYTES = 0x3, 2282 MLX5_QPC_MTU_2K_BYTES = 0x4, 2283 MLX5_QPC_MTU_4K_BYTES = 0x5, 2284 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2285 }; 2286 2287 enum { 2288 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2289 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2290 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2291 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2292 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2293 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2294 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2295 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2296 }; 2297 2298 enum { 2299 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2300 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2301 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2302 }; 2303 2304 enum { 2305 MLX5_QPC_CS_RES_DISABLE = 0x0, 2306 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2307 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2308 }; 2309 2310 struct mlx5_ifc_qpc_bits { 2311 u8 state[0x4]; 2312 u8 lag_tx_port_affinity[0x4]; 2313 u8 st[0x8]; 2314 u8 reserved_at_10[0x3]; 2315 u8 pm_state[0x2]; 2316 u8 reserved_at_15[0x1]; 2317 u8 req_e2e_credit_mode[0x2]; 2318 u8 offload_type[0x4]; 2319 u8 end_padding_mode[0x2]; 2320 u8 reserved_at_1e[0x2]; 2321 2322 u8 wq_signature[0x1]; 2323 u8 block_lb_mc[0x1]; 2324 u8 atomic_like_write_en[0x1]; 2325 u8 latency_sensitive[0x1]; 2326 u8 reserved_at_24[0x1]; 2327 u8 drain_sigerr[0x1]; 2328 u8 reserved_at_26[0x2]; 2329 u8 pd[0x18]; 2330 2331 u8 mtu[0x3]; 2332 u8 log_msg_max[0x5]; 2333 u8 reserved_at_48[0x1]; 2334 u8 log_rq_size[0x4]; 2335 u8 log_rq_stride[0x3]; 2336 u8 no_sq[0x1]; 2337 u8 log_sq_size[0x4]; 2338 u8 reserved_at_55[0x6]; 2339 u8 rlky[0x1]; 2340 u8 ulp_stateless_offload_mode[0x4]; 2341 2342 u8 counter_set_id[0x8]; 2343 u8 uar_page[0x18]; 2344 2345 u8 reserved_at_80[0x8]; 2346 u8 user_index[0x18]; 2347 2348 u8 reserved_at_a0[0x3]; 2349 u8 log_page_size[0x5]; 2350 u8 remote_qpn[0x18]; 2351 2352 struct mlx5_ifc_ads_bits primary_address_path; 2353 2354 struct mlx5_ifc_ads_bits secondary_address_path; 2355 2356 u8 log_ack_req_freq[0x4]; 2357 u8 reserved_at_384[0x4]; 2358 u8 log_sra_max[0x3]; 2359 u8 reserved_at_38b[0x2]; 2360 u8 retry_count[0x3]; 2361 u8 rnr_retry[0x3]; 2362 u8 reserved_at_393[0x1]; 2363 u8 fre[0x1]; 2364 u8 cur_rnr_retry[0x3]; 2365 u8 cur_retry_count[0x3]; 2366 u8 reserved_at_39b[0x5]; 2367 2368 u8 reserved_at_3a0[0x20]; 2369 2370 u8 reserved_at_3c0[0x8]; 2371 u8 next_send_psn[0x18]; 2372 2373 u8 reserved_at_3e0[0x8]; 2374 u8 cqn_snd[0x18]; 2375 2376 u8 reserved_at_400[0x8]; 2377 u8 deth_sqpn[0x18]; 2378 2379 u8 reserved_at_420[0x20]; 2380 2381 u8 reserved_at_440[0x8]; 2382 u8 last_acked_psn[0x18]; 2383 2384 u8 reserved_at_460[0x8]; 2385 u8 ssn[0x18]; 2386 2387 u8 reserved_at_480[0x8]; 2388 u8 log_rra_max[0x3]; 2389 u8 reserved_at_48b[0x1]; 2390 u8 atomic_mode[0x4]; 2391 u8 rre[0x1]; 2392 u8 rwe[0x1]; 2393 u8 rae[0x1]; 2394 u8 reserved_at_493[0x1]; 2395 u8 page_offset[0x6]; 2396 u8 reserved_at_49a[0x3]; 2397 u8 cd_slave_receive[0x1]; 2398 u8 cd_slave_send[0x1]; 2399 u8 cd_master[0x1]; 2400 2401 u8 reserved_at_4a0[0x3]; 2402 u8 min_rnr_nak[0x5]; 2403 u8 next_rcv_psn[0x18]; 2404 2405 u8 reserved_at_4c0[0x8]; 2406 u8 xrcd[0x18]; 2407 2408 u8 reserved_at_4e0[0x8]; 2409 u8 cqn_rcv[0x18]; 2410 2411 u8 dbr_addr[0x40]; 2412 2413 u8 q_key[0x20]; 2414 2415 u8 reserved_at_560[0x5]; 2416 u8 rq_type[0x3]; 2417 u8 srqn_rmpn_xrqn[0x18]; 2418 2419 u8 reserved_at_580[0x8]; 2420 u8 rmsn[0x18]; 2421 2422 u8 hw_sq_wqebb_counter[0x10]; 2423 u8 sw_sq_wqebb_counter[0x10]; 2424 2425 u8 hw_rq_counter[0x20]; 2426 2427 u8 sw_rq_counter[0x20]; 2428 2429 u8 reserved_at_600[0x20]; 2430 2431 u8 reserved_at_620[0xf]; 2432 u8 cgs[0x1]; 2433 u8 cs_req[0x8]; 2434 u8 cs_res[0x8]; 2435 2436 u8 dc_access_key[0x40]; 2437 2438 u8 reserved_at_680[0x3]; 2439 u8 dbr_umem_valid[0x1]; 2440 2441 u8 reserved_at_684[0xbc]; 2442 }; 2443 2444 struct mlx5_ifc_roce_addr_layout_bits { 2445 u8 source_l3_address[16][0x8]; 2446 2447 u8 reserved_at_80[0x3]; 2448 u8 vlan_valid[0x1]; 2449 u8 vlan_id[0xc]; 2450 u8 source_mac_47_32[0x10]; 2451 2452 u8 source_mac_31_0[0x20]; 2453 2454 u8 reserved_at_c0[0x14]; 2455 u8 roce_l3_type[0x4]; 2456 u8 roce_version[0x8]; 2457 2458 u8 reserved_at_e0[0x20]; 2459 }; 2460 2461 union mlx5_ifc_hca_cap_union_bits { 2462 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2463 struct mlx5_ifc_odp_cap_bits odp_cap; 2464 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2465 struct mlx5_ifc_roce_cap_bits roce_cap; 2466 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2467 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2468 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2469 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2470 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2471 struct mlx5_ifc_qos_cap_bits qos_cap; 2472 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2473 u8 reserved_at_0[0x8000]; 2474 }; 2475 2476 enum { 2477 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2478 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2479 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2480 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2481 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2482 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2483 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2484 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2485 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2486 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2487 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2488 }; 2489 2490 struct mlx5_ifc_vlan_bits { 2491 u8 ethtype[0x10]; 2492 u8 prio[0x3]; 2493 u8 cfi[0x1]; 2494 u8 vid[0xc]; 2495 }; 2496 2497 struct mlx5_ifc_flow_context_bits { 2498 struct mlx5_ifc_vlan_bits push_vlan; 2499 2500 u8 group_id[0x20]; 2501 2502 u8 reserved_at_40[0x8]; 2503 u8 flow_tag[0x18]; 2504 2505 u8 reserved_at_60[0x10]; 2506 u8 action[0x10]; 2507 2508 u8 extended_destination[0x1]; 2509 u8 reserved_at_80[0x7]; 2510 u8 destination_list_size[0x18]; 2511 2512 u8 reserved_at_a0[0x8]; 2513 u8 flow_counter_list_size[0x18]; 2514 2515 u8 packet_reformat_id[0x20]; 2516 2517 u8 modify_header_id[0x20]; 2518 2519 struct mlx5_ifc_vlan_bits push_vlan_2; 2520 2521 u8 reserved_at_120[0xe0]; 2522 2523 struct mlx5_ifc_fte_match_param_bits match_value; 2524 2525 u8 reserved_at_1200[0x600]; 2526 2527 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2528 }; 2529 2530 enum { 2531 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2532 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2533 }; 2534 2535 struct mlx5_ifc_xrc_srqc_bits { 2536 u8 state[0x4]; 2537 u8 log_xrc_srq_size[0x4]; 2538 u8 reserved_at_8[0x18]; 2539 2540 u8 wq_signature[0x1]; 2541 u8 cont_srq[0x1]; 2542 u8 reserved_at_22[0x1]; 2543 u8 rlky[0x1]; 2544 u8 basic_cyclic_rcv_wqe[0x1]; 2545 u8 log_rq_stride[0x3]; 2546 u8 xrcd[0x18]; 2547 2548 u8 page_offset[0x6]; 2549 u8 reserved_at_46[0x1]; 2550 u8 dbr_umem_valid[0x1]; 2551 u8 cqn[0x18]; 2552 2553 u8 reserved_at_60[0x20]; 2554 2555 u8 user_index_equal_xrc_srqn[0x1]; 2556 u8 reserved_at_81[0x1]; 2557 u8 log_page_size[0x6]; 2558 u8 user_index[0x18]; 2559 2560 u8 reserved_at_a0[0x20]; 2561 2562 u8 reserved_at_c0[0x8]; 2563 u8 pd[0x18]; 2564 2565 u8 lwm[0x10]; 2566 u8 wqe_cnt[0x10]; 2567 2568 u8 reserved_at_100[0x40]; 2569 2570 u8 db_record_addr_h[0x20]; 2571 2572 u8 db_record_addr_l[0x1e]; 2573 u8 reserved_at_17e[0x2]; 2574 2575 u8 reserved_at_180[0x80]; 2576 }; 2577 2578 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2579 u8 counter_error_queues[0x20]; 2580 2581 u8 total_error_queues[0x20]; 2582 2583 u8 send_queue_priority_update_flow[0x20]; 2584 2585 u8 reserved_at_60[0x20]; 2586 2587 u8 nic_receive_steering_discard[0x40]; 2588 2589 u8 receive_discard_vport_down[0x40]; 2590 2591 u8 transmit_discard_vport_down[0x40]; 2592 2593 u8 reserved_at_140[0xec0]; 2594 }; 2595 2596 struct mlx5_ifc_traffic_counter_bits { 2597 u8 packets[0x40]; 2598 2599 u8 octets[0x40]; 2600 }; 2601 2602 struct mlx5_ifc_tisc_bits { 2603 u8 strict_lag_tx_port_affinity[0x1]; 2604 u8 reserved_at_1[0x3]; 2605 u8 lag_tx_port_affinity[0x04]; 2606 2607 u8 reserved_at_8[0x4]; 2608 u8 prio[0x4]; 2609 u8 reserved_at_10[0x10]; 2610 2611 u8 reserved_at_20[0x100]; 2612 2613 u8 reserved_at_120[0x8]; 2614 u8 transport_domain[0x18]; 2615 2616 u8 reserved_at_140[0x8]; 2617 u8 underlay_qpn[0x18]; 2618 u8 reserved_at_160[0x3a0]; 2619 }; 2620 2621 enum { 2622 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2623 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2624 }; 2625 2626 enum { 2627 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2628 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2629 }; 2630 2631 enum { 2632 MLX5_RX_HASH_FN_NONE = 0x0, 2633 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2634 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2635 }; 2636 2637 enum { 2638 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2639 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2640 }; 2641 2642 struct mlx5_ifc_tirc_bits { 2643 u8 reserved_at_0[0x20]; 2644 2645 u8 disp_type[0x4]; 2646 u8 reserved_at_24[0x1c]; 2647 2648 u8 reserved_at_40[0x40]; 2649 2650 u8 reserved_at_80[0x4]; 2651 u8 lro_timeout_period_usecs[0x10]; 2652 u8 lro_enable_mask[0x4]; 2653 u8 lro_max_ip_payload_size[0x8]; 2654 2655 u8 reserved_at_a0[0x40]; 2656 2657 u8 reserved_at_e0[0x8]; 2658 u8 inline_rqn[0x18]; 2659 2660 u8 rx_hash_symmetric[0x1]; 2661 u8 reserved_at_101[0x1]; 2662 u8 tunneled_offload_en[0x1]; 2663 u8 reserved_at_103[0x5]; 2664 u8 indirect_table[0x18]; 2665 2666 u8 rx_hash_fn[0x4]; 2667 u8 reserved_at_124[0x2]; 2668 u8 self_lb_block[0x2]; 2669 u8 transport_domain[0x18]; 2670 2671 u8 rx_hash_toeplitz_key[10][0x20]; 2672 2673 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2674 2675 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2676 2677 u8 reserved_at_2c0[0x4c0]; 2678 }; 2679 2680 enum { 2681 MLX5_SRQC_STATE_GOOD = 0x0, 2682 MLX5_SRQC_STATE_ERROR = 0x1, 2683 }; 2684 2685 struct mlx5_ifc_srqc_bits { 2686 u8 state[0x4]; 2687 u8 log_srq_size[0x4]; 2688 u8 reserved_at_8[0x18]; 2689 2690 u8 wq_signature[0x1]; 2691 u8 cont_srq[0x1]; 2692 u8 reserved_at_22[0x1]; 2693 u8 rlky[0x1]; 2694 u8 reserved_at_24[0x1]; 2695 u8 log_rq_stride[0x3]; 2696 u8 xrcd[0x18]; 2697 2698 u8 page_offset[0x6]; 2699 u8 reserved_at_46[0x2]; 2700 u8 cqn[0x18]; 2701 2702 u8 reserved_at_60[0x20]; 2703 2704 u8 reserved_at_80[0x2]; 2705 u8 log_page_size[0x6]; 2706 u8 reserved_at_88[0x18]; 2707 2708 u8 reserved_at_a0[0x20]; 2709 2710 u8 reserved_at_c0[0x8]; 2711 u8 pd[0x18]; 2712 2713 u8 lwm[0x10]; 2714 u8 wqe_cnt[0x10]; 2715 2716 u8 reserved_at_100[0x40]; 2717 2718 u8 dbr_addr[0x40]; 2719 2720 u8 reserved_at_180[0x80]; 2721 }; 2722 2723 enum { 2724 MLX5_SQC_STATE_RST = 0x0, 2725 MLX5_SQC_STATE_RDY = 0x1, 2726 MLX5_SQC_STATE_ERR = 0x3, 2727 }; 2728 2729 struct mlx5_ifc_sqc_bits { 2730 u8 rlky[0x1]; 2731 u8 cd_master[0x1]; 2732 u8 fre[0x1]; 2733 u8 flush_in_error_en[0x1]; 2734 u8 allow_multi_pkt_send_wqe[0x1]; 2735 u8 min_wqe_inline_mode[0x3]; 2736 u8 state[0x4]; 2737 u8 reg_umr[0x1]; 2738 u8 allow_swp[0x1]; 2739 u8 hairpin[0x1]; 2740 u8 reserved_at_f[0x11]; 2741 2742 u8 reserved_at_20[0x8]; 2743 u8 user_index[0x18]; 2744 2745 u8 reserved_at_40[0x8]; 2746 u8 cqn[0x18]; 2747 2748 u8 reserved_at_60[0x8]; 2749 u8 hairpin_peer_rq[0x18]; 2750 2751 u8 reserved_at_80[0x10]; 2752 u8 hairpin_peer_vhca[0x10]; 2753 2754 u8 reserved_at_a0[0x50]; 2755 2756 u8 packet_pacing_rate_limit_index[0x10]; 2757 u8 tis_lst_sz[0x10]; 2758 u8 reserved_at_110[0x10]; 2759 2760 u8 reserved_at_120[0x40]; 2761 2762 u8 reserved_at_160[0x8]; 2763 u8 tis_num_0[0x18]; 2764 2765 struct mlx5_ifc_wq_bits wq; 2766 }; 2767 2768 enum { 2769 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2770 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2771 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2772 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2773 }; 2774 2775 struct mlx5_ifc_scheduling_context_bits { 2776 u8 element_type[0x8]; 2777 u8 reserved_at_8[0x18]; 2778 2779 u8 element_attributes[0x20]; 2780 2781 u8 parent_element_id[0x20]; 2782 2783 u8 reserved_at_60[0x40]; 2784 2785 u8 bw_share[0x20]; 2786 2787 u8 max_average_bw[0x20]; 2788 2789 u8 reserved_at_e0[0x120]; 2790 }; 2791 2792 struct mlx5_ifc_rqtc_bits { 2793 u8 reserved_at_0[0xa0]; 2794 2795 u8 reserved_at_a0[0x10]; 2796 u8 rqt_max_size[0x10]; 2797 2798 u8 reserved_at_c0[0x10]; 2799 u8 rqt_actual_size[0x10]; 2800 2801 u8 reserved_at_e0[0x6a0]; 2802 2803 struct mlx5_ifc_rq_num_bits rq_num[0]; 2804 }; 2805 2806 enum { 2807 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2808 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2809 }; 2810 2811 enum { 2812 MLX5_RQC_STATE_RST = 0x0, 2813 MLX5_RQC_STATE_RDY = 0x1, 2814 MLX5_RQC_STATE_ERR = 0x3, 2815 }; 2816 2817 struct mlx5_ifc_rqc_bits { 2818 u8 rlky[0x1]; 2819 u8 delay_drop_en[0x1]; 2820 u8 scatter_fcs[0x1]; 2821 u8 vsd[0x1]; 2822 u8 mem_rq_type[0x4]; 2823 u8 state[0x4]; 2824 u8 reserved_at_c[0x1]; 2825 u8 flush_in_error_en[0x1]; 2826 u8 hairpin[0x1]; 2827 u8 reserved_at_f[0x11]; 2828 2829 u8 reserved_at_20[0x8]; 2830 u8 user_index[0x18]; 2831 2832 u8 reserved_at_40[0x8]; 2833 u8 cqn[0x18]; 2834 2835 u8 counter_set_id[0x8]; 2836 u8 reserved_at_68[0x18]; 2837 2838 u8 reserved_at_80[0x8]; 2839 u8 rmpn[0x18]; 2840 2841 u8 reserved_at_a0[0x8]; 2842 u8 hairpin_peer_sq[0x18]; 2843 2844 u8 reserved_at_c0[0x10]; 2845 u8 hairpin_peer_vhca[0x10]; 2846 2847 u8 reserved_at_e0[0xa0]; 2848 2849 struct mlx5_ifc_wq_bits wq; 2850 }; 2851 2852 enum { 2853 MLX5_RMPC_STATE_RDY = 0x1, 2854 MLX5_RMPC_STATE_ERR = 0x3, 2855 }; 2856 2857 struct mlx5_ifc_rmpc_bits { 2858 u8 reserved_at_0[0x8]; 2859 u8 state[0x4]; 2860 u8 reserved_at_c[0x14]; 2861 2862 u8 basic_cyclic_rcv_wqe[0x1]; 2863 u8 reserved_at_21[0x1f]; 2864 2865 u8 reserved_at_40[0x140]; 2866 2867 struct mlx5_ifc_wq_bits wq; 2868 }; 2869 2870 struct mlx5_ifc_nic_vport_context_bits { 2871 u8 reserved_at_0[0x5]; 2872 u8 min_wqe_inline_mode[0x3]; 2873 u8 reserved_at_8[0x15]; 2874 u8 disable_mc_local_lb[0x1]; 2875 u8 disable_uc_local_lb[0x1]; 2876 u8 roce_en[0x1]; 2877 2878 u8 arm_change_event[0x1]; 2879 u8 reserved_at_21[0x1a]; 2880 u8 event_on_mtu[0x1]; 2881 u8 event_on_promisc_change[0x1]; 2882 u8 event_on_vlan_change[0x1]; 2883 u8 event_on_mc_address_change[0x1]; 2884 u8 event_on_uc_address_change[0x1]; 2885 2886 u8 reserved_at_40[0xc]; 2887 2888 u8 affiliation_criteria[0x4]; 2889 u8 affiliated_vhca_id[0x10]; 2890 2891 u8 reserved_at_60[0xd0]; 2892 2893 u8 mtu[0x10]; 2894 2895 u8 system_image_guid[0x40]; 2896 u8 port_guid[0x40]; 2897 u8 node_guid[0x40]; 2898 2899 u8 reserved_at_200[0x140]; 2900 u8 qkey_violation_counter[0x10]; 2901 u8 reserved_at_350[0x430]; 2902 2903 u8 promisc_uc[0x1]; 2904 u8 promisc_mc[0x1]; 2905 u8 promisc_all[0x1]; 2906 u8 reserved_at_783[0x2]; 2907 u8 allowed_list_type[0x3]; 2908 u8 reserved_at_788[0xc]; 2909 u8 allowed_list_size[0xc]; 2910 2911 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2912 2913 u8 reserved_at_7e0[0x20]; 2914 2915 u8 current_uc_mac_address[0][0x40]; 2916 }; 2917 2918 enum { 2919 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2920 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2921 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2922 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2923 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2924 }; 2925 2926 struct mlx5_ifc_mkc_bits { 2927 u8 reserved_at_0[0x1]; 2928 u8 free[0x1]; 2929 u8 reserved_at_2[0x1]; 2930 u8 access_mode_4_2[0x3]; 2931 u8 reserved_at_6[0x7]; 2932 u8 relaxed_ordering_write[0x1]; 2933 u8 reserved_at_e[0x1]; 2934 u8 small_fence_on_rdma_read_response[0x1]; 2935 u8 umr_en[0x1]; 2936 u8 a[0x1]; 2937 u8 rw[0x1]; 2938 u8 rr[0x1]; 2939 u8 lw[0x1]; 2940 u8 lr[0x1]; 2941 u8 access_mode_1_0[0x2]; 2942 u8 reserved_at_18[0x8]; 2943 2944 u8 qpn[0x18]; 2945 u8 mkey_7_0[0x8]; 2946 2947 u8 reserved_at_40[0x20]; 2948 2949 u8 length64[0x1]; 2950 u8 bsf_en[0x1]; 2951 u8 sync_umr[0x1]; 2952 u8 reserved_at_63[0x2]; 2953 u8 expected_sigerr_count[0x1]; 2954 u8 reserved_at_66[0x1]; 2955 u8 en_rinval[0x1]; 2956 u8 pd[0x18]; 2957 2958 u8 start_addr[0x40]; 2959 2960 u8 len[0x40]; 2961 2962 u8 bsf_octword_size[0x20]; 2963 2964 u8 reserved_at_120[0x80]; 2965 2966 u8 translations_octword_size[0x20]; 2967 2968 u8 reserved_at_1c0[0x1b]; 2969 u8 log_page_size[0x5]; 2970 2971 u8 reserved_at_1e0[0x20]; 2972 }; 2973 2974 struct mlx5_ifc_pkey_bits { 2975 u8 reserved_at_0[0x10]; 2976 u8 pkey[0x10]; 2977 }; 2978 2979 struct mlx5_ifc_array128_auto_bits { 2980 u8 array128_auto[16][0x8]; 2981 }; 2982 2983 struct mlx5_ifc_hca_vport_context_bits { 2984 u8 field_select[0x20]; 2985 2986 u8 reserved_at_20[0xe0]; 2987 2988 u8 sm_virt_aware[0x1]; 2989 u8 has_smi[0x1]; 2990 u8 has_raw[0x1]; 2991 u8 grh_required[0x1]; 2992 u8 reserved_at_104[0xc]; 2993 u8 port_physical_state[0x4]; 2994 u8 vport_state_policy[0x4]; 2995 u8 port_state[0x4]; 2996 u8 vport_state[0x4]; 2997 2998 u8 reserved_at_120[0x20]; 2999 3000 u8 system_image_guid[0x40]; 3001 3002 u8 port_guid[0x40]; 3003 3004 u8 node_guid[0x40]; 3005 3006 u8 cap_mask1[0x20]; 3007 3008 u8 cap_mask1_field_select[0x20]; 3009 3010 u8 cap_mask2[0x20]; 3011 3012 u8 cap_mask2_field_select[0x20]; 3013 3014 u8 reserved_at_280[0x80]; 3015 3016 u8 lid[0x10]; 3017 u8 reserved_at_310[0x4]; 3018 u8 init_type_reply[0x4]; 3019 u8 lmc[0x3]; 3020 u8 subnet_timeout[0x5]; 3021 3022 u8 sm_lid[0x10]; 3023 u8 sm_sl[0x4]; 3024 u8 reserved_at_334[0xc]; 3025 3026 u8 qkey_violation_counter[0x10]; 3027 u8 pkey_violation_counter[0x10]; 3028 3029 u8 reserved_at_360[0xca0]; 3030 }; 3031 3032 struct mlx5_ifc_esw_vport_context_bits { 3033 u8 reserved_at_0[0x3]; 3034 u8 vport_svlan_strip[0x1]; 3035 u8 vport_cvlan_strip[0x1]; 3036 u8 vport_svlan_insert[0x1]; 3037 u8 vport_cvlan_insert[0x2]; 3038 u8 reserved_at_8[0x18]; 3039 3040 u8 reserved_at_20[0x20]; 3041 3042 u8 svlan_cfi[0x1]; 3043 u8 svlan_pcp[0x3]; 3044 u8 svlan_id[0xc]; 3045 u8 cvlan_cfi[0x1]; 3046 u8 cvlan_pcp[0x3]; 3047 u8 cvlan_id[0xc]; 3048 3049 u8 reserved_at_60[0x7a0]; 3050 }; 3051 3052 enum { 3053 MLX5_EQC_STATUS_OK = 0x0, 3054 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3055 }; 3056 3057 enum { 3058 MLX5_EQC_ST_ARMED = 0x9, 3059 MLX5_EQC_ST_FIRED = 0xa, 3060 }; 3061 3062 struct mlx5_ifc_eqc_bits { 3063 u8 status[0x4]; 3064 u8 reserved_at_4[0x9]; 3065 u8 ec[0x1]; 3066 u8 oi[0x1]; 3067 u8 reserved_at_f[0x5]; 3068 u8 st[0x4]; 3069 u8 reserved_at_18[0x8]; 3070 3071 u8 reserved_at_20[0x20]; 3072 3073 u8 reserved_at_40[0x14]; 3074 u8 page_offset[0x6]; 3075 u8 reserved_at_5a[0x6]; 3076 3077 u8 reserved_at_60[0x3]; 3078 u8 log_eq_size[0x5]; 3079 u8 uar_page[0x18]; 3080 3081 u8 reserved_at_80[0x20]; 3082 3083 u8 reserved_at_a0[0x18]; 3084 u8 intr[0x8]; 3085 3086 u8 reserved_at_c0[0x3]; 3087 u8 log_page_size[0x5]; 3088 u8 reserved_at_c8[0x18]; 3089 3090 u8 reserved_at_e0[0x60]; 3091 3092 u8 reserved_at_140[0x8]; 3093 u8 consumer_counter[0x18]; 3094 3095 u8 reserved_at_160[0x8]; 3096 u8 producer_counter[0x18]; 3097 3098 u8 reserved_at_180[0x80]; 3099 }; 3100 3101 enum { 3102 MLX5_DCTC_STATE_ACTIVE = 0x0, 3103 MLX5_DCTC_STATE_DRAINING = 0x1, 3104 MLX5_DCTC_STATE_DRAINED = 0x2, 3105 }; 3106 3107 enum { 3108 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3109 MLX5_DCTC_CS_RES_NA = 0x1, 3110 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3111 }; 3112 3113 enum { 3114 MLX5_DCTC_MTU_256_BYTES = 0x1, 3115 MLX5_DCTC_MTU_512_BYTES = 0x2, 3116 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3117 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3118 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3119 }; 3120 3121 struct mlx5_ifc_dctc_bits { 3122 u8 reserved_at_0[0x4]; 3123 u8 state[0x4]; 3124 u8 reserved_at_8[0x18]; 3125 3126 u8 reserved_at_20[0x8]; 3127 u8 user_index[0x18]; 3128 3129 u8 reserved_at_40[0x8]; 3130 u8 cqn[0x18]; 3131 3132 u8 counter_set_id[0x8]; 3133 u8 atomic_mode[0x4]; 3134 u8 rre[0x1]; 3135 u8 rwe[0x1]; 3136 u8 rae[0x1]; 3137 u8 atomic_like_write_en[0x1]; 3138 u8 latency_sensitive[0x1]; 3139 u8 rlky[0x1]; 3140 u8 free_ar[0x1]; 3141 u8 reserved_at_73[0xd]; 3142 3143 u8 reserved_at_80[0x8]; 3144 u8 cs_res[0x8]; 3145 u8 reserved_at_90[0x3]; 3146 u8 min_rnr_nak[0x5]; 3147 u8 reserved_at_98[0x8]; 3148 3149 u8 reserved_at_a0[0x8]; 3150 u8 srqn_xrqn[0x18]; 3151 3152 u8 reserved_at_c0[0x8]; 3153 u8 pd[0x18]; 3154 3155 u8 tclass[0x8]; 3156 u8 reserved_at_e8[0x4]; 3157 u8 flow_label[0x14]; 3158 3159 u8 dc_access_key[0x40]; 3160 3161 u8 reserved_at_140[0x5]; 3162 u8 mtu[0x3]; 3163 u8 port[0x8]; 3164 u8 pkey_index[0x10]; 3165 3166 u8 reserved_at_160[0x8]; 3167 u8 my_addr_index[0x8]; 3168 u8 reserved_at_170[0x8]; 3169 u8 hop_limit[0x8]; 3170 3171 u8 dc_access_key_violation_count[0x20]; 3172 3173 u8 reserved_at_1a0[0x14]; 3174 u8 dei_cfi[0x1]; 3175 u8 eth_prio[0x3]; 3176 u8 ecn[0x2]; 3177 u8 dscp[0x6]; 3178 3179 u8 reserved_at_1c0[0x40]; 3180 }; 3181 3182 enum { 3183 MLX5_CQC_STATUS_OK = 0x0, 3184 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3185 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3186 }; 3187 3188 enum { 3189 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3190 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3191 }; 3192 3193 enum { 3194 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3195 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3196 MLX5_CQC_ST_FIRED = 0xa, 3197 }; 3198 3199 enum { 3200 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3201 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3202 MLX5_CQ_PERIOD_NUM_MODES 3203 }; 3204 3205 struct mlx5_ifc_cqc_bits { 3206 u8 status[0x4]; 3207 u8 reserved_at_4[0x2]; 3208 u8 dbr_umem_valid[0x1]; 3209 u8 reserved_at_7[0x1]; 3210 u8 cqe_sz[0x3]; 3211 u8 cc[0x1]; 3212 u8 reserved_at_c[0x1]; 3213 u8 scqe_break_moderation_en[0x1]; 3214 u8 oi[0x1]; 3215 u8 cq_period_mode[0x2]; 3216 u8 cqe_comp_en[0x1]; 3217 u8 mini_cqe_res_format[0x2]; 3218 u8 st[0x4]; 3219 u8 reserved_at_18[0x8]; 3220 3221 u8 reserved_at_20[0x20]; 3222 3223 u8 reserved_at_40[0x14]; 3224 u8 page_offset[0x6]; 3225 u8 reserved_at_5a[0x6]; 3226 3227 u8 reserved_at_60[0x3]; 3228 u8 log_cq_size[0x5]; 3229 u8 uar_page[0x18]; 3230 3231 u8 reserved_at_80[0x4]; 3232 u8 cq_period[0xc]; 3233 u8 cq_max_count[0x10]; 3234 3235 u8 reserved_at_a0[0x18]; 3236 u8 c_eqn[0x8]; 3237 3238 u8 reserved_at_c0[0x3]; 3239 u8 log_page_size[0x5]; 3240 u8 reserved_at_c8[0x18]; 3241 3242 u8 reserved_at_e0[0x20]; 3243 3244 u8 reserved_at_100[0x8]; 3245 u8 last_notified_index[0x18]; 3246 3247 u8 reserved_at_120[0x8]; 3248 u8 last_solicit_index[0x18]; 3249 3250 u8 reserved_at_140[0x8]; 3251 u8 consumer_counter[0x18]; 3252 3253 u8 reserved_at_160[0x8]; 3254 u8 producer_counter[0x18]; 3255 3256 u8 reserved_at_180[0x40]; 3257 3258 u8 dbr_addr[0x40]; 3259 }; 3260 3261 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3262 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3263 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3264 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3265 u8 reserved_at_0[0x800]; 3266 }; 3267 3268 struct mlx5_ifc_query_adapter_param_block_bits { 3269 u8 reserved_at_0[0xc0]; 3270 3271 u8 reserved_at_c0[0x8]; 3272 u8 ieee_vendor_id[0x18]; 3273 3274 u8 reserved_at_e0[0x10]; 3275 u8 vsd_vendor_id[0x10]; 3276 3277 u8 vsd[208][0x8]; 3278 3279 u8 vsd_contd_psid[16][0x8]; 3280 }; 3281 3282 enum { 3283 MLX5_XRQC_STATE_GOOD = 0x0, 3284 MLX5_XRQC_STATE_ERROR = 0x1, 3285 }; 3286 3287 enum { 3288 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3289 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3290 }; 3291 3292 enum { 3293 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3294 }; 3295 3296 struct mlx5_ifc_tag_matching_topology_context_bits { 3297 u8 log_matching_list_sz[0x4]; 3298 u8 reserved_at_4[0xc]; 3299 u8 append_next_index[0x10]; 3300 3301 u8 sw_phase_cnt[0x10]; 3302 u8 hw_phase_cnt[0x10]; 3303 3304 u8 reserved_at_40[0x40]; 3305 }; 3306 3307 struct mlx5_ifc_xrqc_bits { 3308 u8 state[0x4]; 3309 u8 rlkey[0x1]; 3310 u8 reserved_at_5[0xf]; 3311 u8 topology[0x4]; 3312 u8 reserved_at_18[0x4]; 3313 u8 offload[0x4]; 3314 3315 u8 reserved_at_20[0x8]; 3316 u8 user_index[0x18]; 3317 3318 u8 reserved_at_40[0x8]; 3319 u8 cqn[0x18]; 3320 3321 u8 reserved_at_60[0xa0]; 3322 3323 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3324 3325 u8 reserved_at_180[0x280]; 3326 3327 struct mlx5_ifc_wq_bits wq; 3328 }; 3329 3330 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3331 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3332 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3333 u8 reserved_at_0[0x20]; 3334 }; 3335 3336 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3337 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3338 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3339 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3340 u8 reserved_at_0[0x20]; 3341 }; 3342 3343 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3344 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3345 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3346 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3347 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3348 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3349 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3350 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3351 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3352 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3353 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3354 u8 reserved_at_0[0x7c0]; 3355 }; 3356 3357 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3358 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3359 u8 reserved_at_0[0x7c0]; 3360 }; 3361 3362 union mlx5_ifc_event_auto_bits { 3363 struct mlx5_ifc_comp_event_bits comp_event; 3364 struct mlx5_ifc_dct_events_bits dct_events; 3365 struct mlx5_ifc_qp_events_bits qp_events; 3366 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3367 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3368 struct mlx5_ifc_cq_error_bits cq_error; 3369 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3370 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3371 struct mlx5_ifc_gpio_event_bits gpio_event; 3372 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3373 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3374 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3375 u8 reserved_at_0[0xe0]; 3376 }; 3377 3378 struct mlx5_ifc_health_buffer_bits { 3379 u8 reserved_at_0[0x100]; 3380 3381 u8 assert_existptr[0x20]; 3382 3383 u8 assert_callra[0x20]; 3384 3385 u8 reserved_at_140[0x40]; 3386 3387 u8 fw_version[0x20]; 3388 3389 u8 hw_id[0x20]; 3390 3391 u8 reserved_at_1c0[0x20]; 3392 3393 u8 irisc_index[0x8]; 3394 u8 synd[0x8]; 3395 u8 ext_synd[0x10]; 3396 }; 3397 3398 struct mlx5_ifc_register_loopback_control_bits { 3399 u8 no_lb[0x1]; 3400 u8 reserved_at_1[0x7]; 3401 u8 port[0x8]; 3402 u8 reserved_at_10[0x10]; 3403 3404 u8 reserved_at_20[0x60]; 3405 }; 3406 3407 struct mlx5_ifc_vport_tc_element_bits { 3408 u8 traffic_class[0x4]; 3409 u8 reserved_at_4[0xc]; 3410 u8 vport_number[0x10]; 3411 }; 3412 3413 struct mlx5_ifc_vport_element_bits { 3414 u8 reserved_at_0[0x10]; 3415 u8 vport_number[0x10]; 3416 }; 3417 3418 enum { 3419 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3420 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3421 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3422 }; 3423 3424 struct mlx5_ifc_tsar_element_bits { 3425 u8 reserved_at_0[0x8]; 3426 u8 tsar_type[0x8]; 3427 u8 reserved_at_10[0x10]; 3428 }; 3429 3430 enum { 3431 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3432 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3433 }; 3434 3435 struct mlx5_ifc_teardown_hca_out_bits { 3436 u8 status[0x8]; 3437 u8 reserved_at_8[0x18]; 3438 3439 u8 syndrome[0x20]; 3440 3441 u8 reserved_at_40[0x3f]; 3442 3443 u8 state[0x1]; 3444 }; 3445 3446 enum { 3447 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3448 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3449 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3450 }; 3451 3452 struct mlx5_ifc_teardown_hca_in_bits { 3453 u8 opcode[0x10]; 3454 u8 reserved_at_10[0x10]; 3455 3456 u8 reserved_at_20[0x10]; 3457 u8 op_mod[0x10]; 3458 3459 u8 reserved_at_40[0x10]; 3460 u8 profile[0x10]; 3461 3462 u8 reserved_at_60[0x20]; 3463 }; 3464 3465 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3466 u8 status[0x8]; 3467 u8 reserved_at_8[0x18]; 3468 3469 u8 syndrome[0x20]; 3470 3471 u8 reserved_at_40[0x40]; 3472 }; 3473 3474 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3475 u8 opcode[0x10]; 3476 u8 uid[0x10]; 3477 3478 u8 reserved_at_20[0x10]; 3479 u8 op_mod[0x10]; 3480 3481 u8 reserved_at_40[0x8]; 3482 u8 qpn[0x18]; 3483 3484 u8 reserved_at_60[0x20]; 3485 3486 u8 opt_param_mask[0x20]; 3487 3488 u8 reserved_at_a0[0x20]; 3489 3490 struct mlx5_ifc_qpc_bits qpc; 3491 3492 u8 reserved_at_800[0x80]; 3493 }; 3494 3495 struct mlx5_ifc_sqd2rts_qp_out_bits { 3496 u8 status[0x8]; 3497 u8 reserved_at_8[0x18]; 3498 3499 u8 syndrome[0x20]; 3500 3501 u8 reserved_at_40[0x40]; 3502 }; 3503 3504 struct mlx5_ifc_sqd2rts_qp_in_bits { 3505 u8 opcode[0x10]; 3506 u8 uid[0x10]; 3507 3508 u8 reserved_at_20[0x10]; 3509 u8 op_mod[0x10]; 3510 3511 u8 reserved_at_40[0x8]; 3512 u8 qpn[0x18]; 3513 3514 u8 reserved_at_60[0x20]; 3515 3516 u8 opt_param_mask[0x20]; 3517 3518 u8 reserved_at_a0[0x20]; 3519 3520 struct mlx5_ifc_qpc_bits qpc; 3521 3522 u8 reserved_at_800[0x80]; 3523 }; 3524 3525 struct mlx5_ifc_set_roce_address_out_bits { 3526 u8 status[0x8]; 3527 u8 reserved_at_8[0x18]; 3528 3529 u8 syndrome[0x20]; 3530 3531 u8 reserved_at_40[0x40]; 3532 }; 3533 3534 struct mlx5_ifc_set_roce_address_in_bits { 3535 u8 opcode[0x10]; 3536 u8 reserved_at_10[0x10]; 3537 3538 u8 reserved_at_20[0x10]; 3539 u8 op_mod[0x10]; 3540 3541 u8 roce_address_index[0x10]; 3542 u8 reserved_at_50[0xc]; 3543 u8 vhca_port_num[0x4]; 3544 3545 u8 reserved_at_60[0x20]; 3546 3547 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3548 }; 3549 3550 struct mlx5_ifc_set_mad_demux_out_bits { 3551 u8 status[0x8]; 3552 u8 reserved_at_8[0x18]; 3553 3554 u8 syndrome[0x20]; 3555 3556 u8 reserved_at_40[0x40]; 3557 }; 3558 3559 enum { 3560 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3561 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3562 }; 3563 3564 struct mlx5_ifc_set_mad_demux_in_bits { 3565 u8 opcode[0x10]; 3566 u8 reserved_at_10[0x10]; 3567 3568 u8 reserved_at_20[0x10]; 3569 u8 op_mod[0x10]; 3570 3571 u8 reserved_at_40[0x20]; 3572 3573 u8 reserved_at_60[0x6]; 3574 u8 demux_mode[0x2]; 3575 u8 reserved_at_68[0x18]; 3576 }; 3577 3578 struct mlx5_ifc_set_l2_table_entry_out_bits { 3579 u8 status[0x8]; 3580 u8 reserved_at_8[0x18]; 3581 3582 u8 syndrome[0x20]; 3583 3584 u8 reserved_at_40[0x40]; 3585 }; 3586 3587 struct mlx5_ifc_set_l2_table_entry_in_bits { 3588 u8 opcode[0x10]; 3589 u8 reserved_at_10[0x10]; 3590 3591 u8 reserved_at_20[0x10]; 3592 u8 op_mod[0x10]; 3593 3594 u8 reserved_at_40[0x60]; 3595 3596 u8 reserved_at_a0[0x8]; 3597 u8 table_index[0x18]; 3598 3599 u8 reserved_at_c0[0x20]; 3600 3601 u8 reserved_at_e0[0x13]; 3602 u8 vlan_valid[0x1]; 3603 u8 vlan[0xc]; 3604 3605 struct mlx5_ifc_mac_address_layout_bits mac_address; 3606 3607 u8 reserved_at_140[0xc0]; 3608 }; 3609 3610 struct mlx5_ifc_set_issi_out_bits { 3611 u8 status[0x8]; 3612 u8 reserved_at_8[0x18]; 3613 3614 u8 syndrome[0x20]; 3615 3616 u8 reserved_at_40[0x40]; 3617 }; 3618 3619 struct mlx5_ifc_set_issi_in_bits { 3620 u8 opcode[0x10]; 3621 u8 reserved_at_10[0x10]; 3622 3623 u8 reserved_at_20[0x10]; 3624 u8 op_mod[0x10]; 3625 3626 u8 reserved_at_40[0x10]; 3627 u8 current_issi[0x10]; 3628 3629 u8 reserved_at_60[0x20]; 3630 }; 3631 3632 struct mlx5_ifc_set_hca_cap_out_bits { 3633 u8 status[0x8]; 3634 u8 reserved_at_8[0x18]; 3635 3636 u8 syndrome[0x20]; 3637 3638 u8 reserved_at_40[0x40]; 3639 }; 3640 3641 struct mlx5_ifc_set_hca_cap_in_bits { 3642 u8 opcode[0x10]; 3643 u8 reserved_at_10[0x10]; 3644 3645 u8 reserved_at_20[0x10]; 3646 u8 op_mod[0x10]; 3647 3648 u8 reserved_at_40[0x40]; 3649 3650 union mlx5_ifc_hca_cap_union_bits capability; 3651 }; 3652 3653 enum { 3654 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3655 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3656 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3657 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3658 }; 3659 3660 struct mlx5_ifc_set_fte_out_bits { 3661 u8 status[0x8]; 3662 u8 reserved_at_8[0x18]; 3663 3664 u8 syndrome[0x20]; 3665 3666 u8 reserved_at_40[0x40]; 3667 }; 3668 3669 struct mlx5_ifc_set_fte_in_bits { 3670 u8 opcode[0x10]; 3671 u8 reserved_at_10[0x10]; 3672 3673 u8 reserved_at_20[0x10]; 3674 u8 op_mod[0x10]; 3675 3676 u8 other_vport[0x1]; 3677 u8 reserved_at_41[0xf]; 3678 u8 vport_number[0x10]; 3679 3680 u8 reserved_at_60[0x20]; 3681 3682 u8 table_type[0x8]; 3683 u8 reserved_at_88[0x18]; 3684 3685 u8 reserved_at_a0[0x8]; 3686 u8 table_id[0x18]; 3687 3688 u8 reserved_at_c0[0x18]; 3689 u8 modify_enable_mask[0x8]; 3690 3691 u8 reserved_at_e0[0x20]; 3692 3693 u8 flow_index[0x20]; 3694 3695 u8 reserved_at_120[0xe0]; 3696 3697 struct mlx5_ifc_flow_context_bits flow_context; 3698 }; 3699 3700 struct mlx5_ifc_rts2rts_qp_out_bits { 3701 u8 status[0x8]; 3702 u8 reserved_at_8[0x18]; 3703 3704 u8 syndrome[0x20]; 3705 3706 u8 reserved_at_40[0x40]; 3707 }; 3708 3709 struct mlx5_ifc_rts2rts_qp_in_bits { 3710 u8 opcode[0x10]; 3711 u8 uid[0x10]; 3712 3713 u8 reserved_at_20[0x10]; 3714 u8 op_mod[0x10]; 3715 3716 u8 reserved_at_40[0x8]; 3717 u8 qpn[0x18]; 3718 3719 u8 reserved_at_60[0x20]; 3720 3721 u8 opt_param_mask[0x20]; 3722 3723 u8 reserved_at_a0[0x20]; 3724 3725 struct mlx5_ifc_qpc_bits qpc; 3726 3727 u8 reserved_at_800[0x80]; 3728 }; 3729 3730 struct mlx5_ifc_rtr2rts_qp_out_bits { 3731 u8 status[0x8]; 3732 u8 reserved_at_8[0x18]; 3733 3734 u8 syndrome[0x20]; 3735 3736 u8 reserved_at_40[0x40]; 3737 }; 3738 3739 struct mlx5_ifc_rtr2rts_qp_in_bits { 3740 u8 opcode[0x10]; 3741 u8 uid[0x10]; 3742 3743 u8 reserved_at_20[0x10]; 3744 u8 op_mod[0x10]; 3745 3746 u8 reserved_at_40[0x8]; 3747 u8 qpn[0x18]; 3748 3749 u8 reserved_at_60[0x20]; 3750 3751 u8 opt_param_mask[0x20]; 3752 3753 u8 reserved_at_a0[0x20]; 3754 3755 struct mlx5_ifc_qpc_bits qpc; 3756 3757 u8 reserved_at_800[0x80]; 3758 }; 3759 3760 struct mlx5_ifc_rst2init_qp_out_bits { 3761 u8 status[0x8]; 3762 u8 reserved_at_8[0x18]; 3763 3764 u8 syndrome[0x20]; 3765 3766 u8 reserved_at_40[0x40]; 3767 }; 3768 3769 struct mlx5_ifc_rst2init_qp_in_bits { 3770 u8 opcode[0x10]; 3771 u8 uid[0x10]; 3772 3773 u8 reserved_at_20[0x10]; 3774 u8 op_mod[0x10]; 3775 3776 u8 reserved_at_40[0x8]; 3777 u8 qpn[0x18]; 3778 3779 u8 reserved_at_60[0x20]; 3780 3781 u8 opt_param_mask[0x20]; 3782 3783 u8 reserved_at_a0[0x20]; 3784 3785 struct mlx5_ifc_qpc_bits qpc; 3786 3787 u8 reserved_at_800[0x80]; 3788 }; 3789 3790 struct mlx5_ifc_query_xrq_out_bits { 3791 u8 status[0x8]; 3792 u8 reserved_at_8[0x18]; 3793 3794 u8 syndrome[0x20]; 3795 3796 u8 reserved_at_40[0x40]; 3797 3798 struct mlx5_ifc_xrqc_bits xrq_context; 3799 }; 3800 3801 struct mlx5_ifc_query_xrq_in_bits { 3802 u8 opcode[0x10]; 3803 u8 reserved_at_10[0x10]; 3804 3805 u8 reserved_at_20[0x10]; 3806 u8 op_mod[0x10]; 3807 3808 u8 reserved_at_40[0x8]; 3809 u8 xrqn[0x18]; 3810 3811 u8 reserved_at_60[0x20]; 3812 }; 3813 3814 struct mlx5_ifc_query_xrc_srq_out_bits { 3815 u8 status[0x8]; 3816 u8 reserved_at_8[0x18]; 3817 3818 u8 syndrome[0x20]; 3819 3820 u8 reserved_at_40[0x40]; 3821 3822 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3823 3824 u8 reserved_at_280[0x600]; 3825 3826 u8 pas[0][0x40]; 3827 }; 3828 3829 struct mlx5_ifc_query_xrc_srq_in_bits { 3830 u8 opcode[0x10]; 3831 u8 reserved_at_10[0x10]; 3832 3833 u8 reserved_at_20[0x10]; 3834 u8 op_mod[0x10]; 3835 3836 u8 reserved_at_40[0x8]; 3837 u8 xrc_srqn[0x18]; 3838 3839 u8 reserved_at_60[0x20]; 3840 }; 3841 3842 enum { 3843 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3844 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3845 }; 3846 3847 struct mlx5_ifc_query_vport_state_out_bits { 3848 u8 status[0x8]; 3849 u8 reserved_at_8[0x18]; 3850 3851 u8 syndrome[0x20]; 3852 3853 u8 reserved_at_40[0x20]; 3854 3855 u8 reserved_at_60[0x18]; 3856 u8 admin_state[0x4]; 3857 u8 state[0x4]; 3858 }; 3859 3860 enum { 3861 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3862 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3863 }; 3864 3865 struct mlx5_ifc_arm_monitor_counter_in_bits { 3866 u8 opcode[0x10]; 3867 u8 uid[0x10]; 3868 3869 u8 reserved_at_20[0x10]; 3870 u8 op_mod[0x10]; 3871 3872 u8 reserved_at_40[0x20]; 3873 3874 u8 reserved_at_60[0x20]; 3875 }; 3876 3877 struct mlx5_ifc_arm_monitor_counter_out_bits { 3878 u8 status[0x8]; 3879 u8 reserved_at_8[0x18]; 3880 3881 u8 syndrome[0x20]; 3882 3883 u8 reserved_at_40[0x40]; 3884 }; 3885 3886 enum { 3887 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3888 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3889 }; 3890 3891 enum mlx5_monitor_counter_ppcnt { 3892 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 3893 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 3894 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 3895 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 3896 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 3897 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 3898 }; 3899 3900 enum { 3901 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 3902 }; 3903 3904 struct mlx5_ifc_monitor_counter_output_bits { 3905 u8 reserved_at_0[0x4]; 3906 u8 type[0x4]; 3907 u8 reserved_at_8[0x8]; 3908 u8 counter[0x10]; 3909 3910 u8 counter_group_id[0x20]; 3911 }; 3912 3913 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 3914 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 3915 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 3916 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 3917 3918 struct mlx5_ifc_set_monitor_counter_in_bits { 3919 u8 opcode[0x10]; 3920 u8 uid[0x10]; 3921 3922 u8 reserved_at_20[0x10]; 3923 u8 op_mod[0x10]; 3924 3925 u8 reserved_at_40[0x10]; 3926 u8 num_of_counters[0x10]; 3927 3928 u8 reserved_at_60[0x20]; 3929 3930 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 3931 }; 3932 3933 struct mlx5_ifc_set_monitor_counter_out_bits { 3934 u8 status[0x8]; 3935 u8 reserved_at_8[0x18]; 3936 3937 u8 syndrome[0x20]; 3938 3939 u8 reserved_at_40[0x40]; 3940 }; 3941 3942 struct mlx5_ifc_query_vport_state_in_bits { 3943 u8 opcode[0x10]; 3944 u8 reserved_at_10[0x10]; 3945 3946 u8 reserved_at_20[0x10]; 3947 u8 op_mod[0x10]; 3948 3949 u8 other_vport[0x1]; 3950 u8 reserved_at_41[0xf]; 3951 u8 vport_number[0x10]; 3952 3953 u8 reserved_at_60[0x20]; 3954 }; 3955 3956 struct mlx5_ifc_query_vnic_env_out_bits { 3957 u8 status[0x8]; 3958 u8 reserved_at_8[0x18]; 3959 3960 u8 syndrome[0x20]; 3961 3962 u8 reserved_at_40[0x40]; 3963 3964 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3965 }; 3966 3967 enum { 3968 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3969 }; 3970 3971 struct mlx5_ifc_query_vnic_env_in_bits { 3972 u8 opcode[0x10]; 3973 u8 reserved_at_10[0x10]; 3974 3975 u8 reserved_at_20[0x10]; 3976 u8 op_mod[0x10]; 3977 3978 u8 other_vport[0x1]; 3979 u8 reserved_at_41[0xf]; 3980 u8 vport_number[0x10]; 3981 3982 u8 reserved_at_60[0x20]; 3983 }; 3984 3985 struct mlx5_ifc_query_vport_counter_out_bits { 3986 u8 status[0x8]; 3987 u8 reserved_at_8[0x18]; 3988 3989 u8 syndrome[0x20]; 3990 3991 u8 reserved_at_40[0x40]; 3992 3993 struct mlx5_ifc_traffic_counter_bits received_errors; 3994 3995 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3996 3997 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3998 3999 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4000 4001 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4002 4003 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4004 4005 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4006 4007 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4008 4009 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4010 4011 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4012 4013 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4014 4015 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4016 4017 u8 reserved_at_680[0xa00]; 4018 }; 4019 4020 enum { 4021 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4022 }; 4023 4024 struct mlx5_ifc_query_vport_counter_in_bits { 4025 u8 opcode[0x10]; 4026 u8 reserved_at_10[0x10]; 4027 4028 u8 reserved_at_20[0x10]; 4029 u8 op_mod[0x10]; 4030 4031 u8 other_vport[0x1]; 4032 u8 reserved_at_41[0xb]; 4033 u8 port_num[0x4]; 4034 u8 vport_number[0x10]; 4035 4036 u8 reserved_at_60[0x60]; 4037 4038 u8 clear[0x1]; 4039 u8 reserved_at_c1[0x1f]; 4040 4041 u8 reserved_at_e0[0x20]; 4042 }; 4043 4044 struct mlx5_ifc_query_tis_out_bits { 4045 u8 status[0x8]; 4046 u8 reserved_at_8[0x18]; 4047 4048 u8 syndrome[0x20]; 4049 4050 u8 reserved_at_40[0x40]; 4051 4052 struct mlx5_ifc_tisc_bits tis_context; 4053 }; 4054 4055 struct mlx5_ifc_query_tis_in_bits { 4056 u8 opcode[0x10]; 4057 u8 reserved_at_10[0x10]; 4058 4059 u8 reserved_at_20[0x10]; 4060 u8 op_mod[0x10]; 4061 4062 u8 reserved_at_40[0x8]; 4063 u8 tisn[0x18]; 4064 4065 u8 reserved_at_60[0x20]; 4066 }; 4067 4068 struct mlx5_ifc_query_tir_out_bits { 4069 u8 status[0x8]; 4070 u8 reserved_at_8[0x18]; 4071 4072 u8 syndrome[0x20]; 4073 4074 u8 reserved_at_40[0xc0]; 4075 4076 struct mlx5_ifc_tirc_bits tir_context; 4077 }; 4078 4079 struct mlx5_ifc_query_tir_in_bits { 4080 u8 opcode[0x10]; 4081 u8 reserved_at_10[0x10]; 4082 4083 u8 reserved_at_20[0x10]; 4084 u8 op_mod[0x10]; 4085 4086 u8 reserved_at_40[0x8]; 4087 u8 tirn[0x18]; 4088 4089 u8 reserved_at_60[0x20]; 4090 }; 4091 4092 struct mlx5_ifc_query_srq_out_bits { 4093 u8 status[0x8]; 4094 u8 reserved_at_8[0x18]; 4095 4096 u8 syndrome[0x20]; 4097 4098 u8 reserved_at_40[0x40]; 4099 4100 struct mlx5_ifc_srqc_bits srq_context_entry; 4101 4102 u8 reserved_at_280[0x600]; 4103 4104 u8 pas[0][0x40]; 4105 }; 4106 4107 struct mlx5_ifc_query_srq_in_bits { 4108 u8 opcode[0x10]; 4109 u8 reserved_at_10[0x10]; 4110 4111 u8 reserved_at_20[0x10]; 4112 u8 op_mod[0x10]; 4113 4114 u8 reserved_at_40[0x8]; 4115 u8 srqn[0x18]; 4116 4117 u8 reserved_at_60[0x20]; 4118 }; 4119 4120 struct mlx5_ifc_query_sq_out_bits { 4121 u8 status[0x8]; 4122 u8 reserved_at_8[0x18]; 4123 4124 u8 syndrome[0x20]; 4125 4126 u8 reserved_at_40[0xc0]; 4127 4128 struct mlx5_ifc_sqc_bits sq_context; 4129 }; 4130 4131 struct mlx5_ifc_query_sq_in_bits { 4132 u8 opcode[0x10]; 4133 u8 reserved_at_10[0x10]; 4134 4135 u8 reserved_at_20[0x10]; 4136 u8 op_mod[0x10]; 4137 4138 u8 reserved_at_40[0x8]; 4139 u8 sqn[0x18]; 4140 4141 u8 reserved_at_60[0x20]; 4142 }; 4143 4144 struct mlx5_ifc_query_special_contexts_out_bits { 4145 u8 status[0x8]; 4146 u8 reserved_at_8[0x18]; 4147 4148 u8 syndrome[0x20]; 4149 4150 u8 dump_fill_mkey[0x20]; 4151 4152 u8 resd_lkey[0x20]; 4153 4154 u8 null_mkey[0x20]; 4155 4156 u8 reserved_at_a0[0x60]; 4157 }; 4158 4159 struct mlx5_ifc_query_special_contexts_in_bits { 4160 u8 opcode[0x10]; 4161 u8 reserved_at_10[0x10]; 4162 4163 u8 reserved_at_20[0x10]; 4164 u8 op_mod[0x10]; 4165 4166 u8 reserved_at_40[0x40]; 4167 }; 4168 4169 struct mlx5_ifc_query_scheduling_element_out_bits { 4170 u8 opcode[0x10]; 4171 u8 reserved_at_10[0x10]; 4172 4173 u8 reserved_at_20[0x10]; 4174 u8 op_mod[0x10]; 4175 4176 u8 reserved_at_40[0xc0]; 4177 4178 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4179 4180 u8 reserved_at_300[0x100]; 4181 }; 4182 4183 enum { 4184 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4185 }; 4186 4187 struct mlx5_ifc_query_scheduling_element_in_bits { 4188 u8 opcode[0x10]; 4189 u8 reserved_at_10[0x10]; 4190 4191 u8 reserved_at_20[0x10]; 4192 u8 op_mod[0x10]; 4193 4194 u8 scheduling_hierarchy[0x8]; 4195 u8 reserved_at_48[0x18]; 4196 4197 u8 scheduling_element_id[0x20]; 4198 4199 u8 reserved_at_80[0x180]; 4200 }; 4201 4202 struct mlx5_ifc_query_rqt_out_bits { 4203 u8 status[0x8]; 4204 u8 reserved_at_8[0x18]; 4205 4206 u8 syndrome[0x20]; 4207 4208 u8 reserved_at_40[0xc0]; 4209 4210 struct mlx5_ifc_rqtc_bits rqt_context; 4211 }; 4212 4213 struct mlx5_ifc_query_rqt_in_bits { 4214 u8 opcode[0x10]; 4215 u8 reserved_at_10[0x10]; 4216 4217 u8 reserved_at_20[0x10]; 4218 u8 op_mod[0x10]; 4219 4220 u8 reserved_at_40[0x8]; 4221 u8 rqtn[0x18]; 4222 4223 u8 reserved_at_60[0x20]; 4224 }; 4225 4226 struct mlx5_ifc_query_rq_out_bits { 4227 u8 status[0x8]; 4228 u8 reserved_at_8[0x18]; 4229 4230 u8 syndrome[0x20]; 4231 4232 u8 reserved_at_40[0xc0]; 4233 4234 struct mlx5_ifc_rqc_bits rq_context; 4235 }; 4236 4237 struct mlx5_ifc_query_rq_in_bits { 4238 u8 opcode[0x10]; 4239 u8 reserved_at_10[0x10]; 4240 4241 u8 reserved_at_20[0x10]; 4242 u8 op_mod[0x10]; 4243 4244 u8 reserved_at_40[0x8]; 4245 u8 rqn[0x18]; 4246 4247 u8 reserved_at_60[0x20]; 4248 }; 4249 4250 struct mlx5_ifc_query_roce_address_out_bits { 4251 u8 status[0x8]; 4252 u8 reserved_at_8[0x18]; 4253 4254 u8 syndrome[0x20]; 4255 4256 u8 reserved_at_40[0x40]; 4257 4258 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4259 }; 4260 4261 struct mlx5_ifc_query_roce_address_in_bits { 4262 u8 opcode[0x10]; 4263 u8 reserved_at_10[0x10]; 4264 4265 u8 reserved_at_20[0x10]; 4266 u8 op_mod[0x10]; 4267 4268 u8 roce_address_index[0x10]; 4269 u8 reserved_at_50[0xc]; 4270 u8 vhca_port_num[0x4]; 4271 4272 u8 reserved_at_60[0x20]; 4273 }; 4274 4275 struct mlx5_ifc_query_rmp_out_bits { 4276 u8 status[0x8]; 4277 u8 reserved_at_8[0x18]; 4278 4279 u8 syndrome[0x20]; 4280 4281 u8 reserved_at_40[0xc0]; 4282 4283 struct mlx5_ifc_rmpc_bits rmp_context; 4284 }; 4285 4286 struct mlx5_ifc_query_rmp_in_bits { 4287 u8 opcode[0x10]; 4288 u8 reserved_at_10[0x10]; 4289 4290 u8 reserved_at_20[0x10]; 4291 u8 op_mod[0x10]; 4292 4293 u8 reserved_at_40[0x8]; 4294 u8 rmpn[0x18]; 4295 4296 u8 reserved_at_60[0x20]; 4297 }; 4298 4299 struct mlx5_ifc_query_qp_out_bits { 4300 u8 status[0x8]; 4301 u8 reserved_at_8[0x18]; 4302 4303 u8 syndrome[0x20]; 4304 4305 u8 reserved_at_40[0x40]; 4306 4307 u8 opt_param_mask[0x20]; 4308 4309 u8 reserved_at_a0[0x20]; 4310 4311 struct mlx5_ifc_qpc_bits qpc; 4312 4313 u8 reserved_at_800[0x80]; 4314 4315 u8 pas[0][0x40]; 4316 }; 4317 4318 struct mlx5_ifc_query_qp_in_bits { 4319 u8 opcode[0x10]; 4320 u8 reserved_at_10[0x10]; 4321 4322 u8 reserved_at_20[0x10]; 4323 u8 op_mod[0x10]; 4324 4325 u8 reserved_at_40[0x8]; 4326 u8 qpn[0x18]; 4327 4328 u8 reserved_at_60[0x20]; 4329 }; 4330 4331 struct mlx5_ifc_query_q_counter_out_bits { 4332 u8 status[0x8]; 4333 u8 reserved_at_8[0x18]; 4334 4335 u8 syndrome[0x20]; 4336 4337 u8 reserved_at_40[0x40]; 4338 4339 u8 rx_write_requests[0x20]; 4340 4341 u8 reserved_at_a0[0x20]; 4342 4343 u8 rx_read_requests[0x20]; 4344 4345 u8 reserved_at_e0[0x20]; 4346 4347 u8 rx_atomic_requests[0x20]; 4348 4349 u8 reserved_at_120[0x20]; 4350 4351 u8 rx_dct_connect[0x20]; 4352 4353 u8 reserved_at_160[0x20]; 4354 4355 u8 out_of_buffer[0x20]; 4356 4357 u8 reserved_at_1a0[0x20]; 4358 4359 u8 out_of_sequence[0x20]; 4360 4361 u8 reserved_at_1e0[0x20]; 4362 4363 u8 duplicate_request[0x20]; 4364 4365 u8 reserved_at_220[0x20]; 4366 4367 u8 rnr_nak_retry_err[0x20]; 4368 4369 u8 reserved_at_260[0x20]; 4370 4371 u8 packet_seq_err[0x20]; 4372 4373 u8 reserved_at_2a0[0x20]; 4374 4375 u8 implied_nak_seq_err[0x20]; 4376 4377 u8 reserved_at_2e0[0x20]; 4378 4379 u8 local_ack_timeout_err[0x20]; 4380 4381 u8 reserved_at_320[0xa0]; 4382 4383 u8 resp_local_length_error[0x20]; 4384 4385 u8 req_local_length_error[0x20]; 4386 4387 u8 resp_local_qp_error[0x20]; 4388 4389 u8 local_operation_error[0x20]; 4390 4391 u8 resp_local_protection[0x20]; 4392 4393 u8 req_local_protection[0x20]; 4394 4395 u8 resp_cqe_error[0x20]; 4396 4397 u8 req_cqe_error[0x20]; 4398 4399 u8 req_mw_binding[0x20]; 4400 4401 u8 req_bad_response[0x20]; 4402 4403 u8 req_remote_invalid_request[0x20]; 4404 4405 u8 resp_remote_invalid_request[0x20]; 4406 4407 u8 req_remote_access_errors[0x20]; 4408 4409 u8 resp_remote_access_errors[0x20]; 4410 4411 u8 req_remote_operation_errors[0x20]; 4412 4413 u8 req_transport_retries_exceeded[0x20]; 4414 4415 u8 cq_overflow[0x20]; 4416 4417 u8 resp_cqe_flush_error[0x20]; 4418 4419 u8 req_cqe_flush_error[0x20]; 4420 4421 u8 reserved_at_620[0x1e0]; 4422 }; 4423 4424 struct mlx5_ifc_query_q_counter_in_bits { 4425 u8 opcode[0x10]; 4426 u8 reserved_at_10[0x10]; 4427 4428 u8 reserved_at_20[0x10]; 4429 u8 op_mod[0x10]; 4430 4431 u8 reserved_at_40[0x80]; 4432 4433 u8 clear[0x1]; 4434 u8 reserved_at_c1[0x1f]; 4435 4436 u8 reserved_at_e0[0x18]; 4437 u8 counter_set_id[0x8]; 4438 }; 4439 4440 struct mlx5_ifc_query_pages_out_bits { 4441 u8 status[0x8]; 4442 u8 reserved_at_8[0x18]; 4443 4444 u8 syndrome[0x20]; 4445 4446 u8 embedded_cpu_function[0x1]; 4447 u8 reserved_at_41[0xf]; 4448 u8 function_id[0x10]; 4449 4450 u8 num_pages[0x20]; 4451 }; 4452 4453 enum { 4454 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4455 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4456 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4457 }; 4458 4459 struct mlx5_ifc_query_pages_in_bits { 4460 u8 opcode[0x10]; 4461 u8 reserved_at_10[0x10]; 4462 4463 u8 reserved_at_20[0x10]; 4464 u8 op_mod[0x10]; 4465 4466 u8 embedded_cpu_function[0x1]; 4467 u8 reserved_at_41[0xf]; 4468 u8 function_id[0x10]; 4469 4470 u8 reserved_at_60[0x20]; 4471 }; 4472 4473 struct mlx5_ifc_query_nic_vport_context_out_bits { 4474 u8 status[0x8]; 4475 u8 reserved_at_8[0x18]; 4476 4477 u8 syndrome[0x20]; 4478 4479 u8 reserved_at_40[0x40]; 4480 4481 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4482 }; 4483 4484 struct mlx5_ifc_query_nic_vport_context_in_bits { 4485 u8 opcode[0x10]; 4486 u8 reserved_at_10[0x10]; 4487 4488 u8 reserved_at_20[0x10]; 4489 u8 op_mod[0x10]; 4490 4491 u8 other_vport[0x1]; 4492 u8 reserved_at_41[0xf]; 4493 u8 vport_number[0x10]; 4494 4495 u8 reserved_at_60[0x5]; 4496 u8 allowed_list_type[0x3]; 4497 u8 reserved_at_68[0x18]; 4498 }; 4499 4500 struct mlx5_ifc_query_mkey_out_bits { 4501 u8 status[0x8]; 4502 u8 reserved_at_8[0x18]; 4503 4504 u8 syndrome[0x20]; 4505 4506 u8 reserved_at_40[0x40]; 4507 4508 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4509 4510 u8 reserved_at_280[0x600]; 4511 4512 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4513 4514 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4515 }; 4516 4517 struct mlx5_ifc_query_mkey_in_bits { 4518 u8 opcode[0x10]; 4519 u8 reserved_at_10[0x10]; 4520 4521 u8 reserved_at_20[0x10]; 4522 u8 op_mod[0x10]; 4523 4524 u8 reserved_at_40[0x8]; 4525 u8 mkey_index[0x18]; 4526 4527 u8 pg_access[0x1]; 4528 u8 reserved_at_61[0x1f]; 4529 }; 4530 4531 struct mlx5_ifc_query_mad_demux_out_bits { 4532 u8 status[0x8]; 4533 u8 reserved_at_8[0x18]; 4534 4535 u8 syndrome[0x20]; 4536 4537 u8 reserved_at_40[0x40]; 4538 4539 u8 mad_dumux_parameters_block[0x20]; 4540 }; 4541 4542 struct mlx5_ifc_query_mad_demux_in_bits { 4543 u8 opcode[0x10]; 4544 u8 reserved_at_10[0x10]; 4545 4546 u8 reserved_at_20[0x10]; 4547 u8 op_mod[0x10]; 4548 4549 u8 reserved_at_40[0x40]; 4550 }; 4551 4552 struct mlx5_ifc_query_l2_table_entry_out_bits { 4553 u8 status[0x8]; 4554 u8 reserved_at_8[0x18]; 4555 4556 u8 syndrome[0x20]; 4557 4558 u8 reserved_at_40[0xa0]; 4559 4560 u8 reserved_at_e0[0x13]; 4561 u8 vlan_valid[0x1]; 4562 u8 vlan[0xc]; 4563 4564 struct mlx5_ifc_mac_address_layout_bits mac_address; 4565 4566 u8 reserved_at_140[0xc0]; 4567 }; 4568 4569 struct mlx5_ifc_query_l2_table_entry_in_bits { 4570 u8 opcode[0x10]; 4571 u8 reserved_at_10[0x10]; 4572 4573 u8 reserved_at_20[0x10]; 4574 u8 op_mod[0x10]; 4575 4576 u8 reserved_at_40[0x60]; 4577 4578 u8 reserved_at_a0[0x8]; 4579 u8 table_index[0x18]; 4580 4581 u8 reserved_at_c0[0x140]; 4582 }; 4583 4584 struct mlx5_ifc_query_issi_out_bits { 4585 u8 status[0x8]; 4586 u8 reserved_at_8[0x18]; 4587 4588 u8 syndrome[0x20]; 4589 4590 u8 reserved_at_40[0x10]; 4591 u8 current_issi[0x10]; 4592 4593 u8 reserved_at_60[0xa0]; 4594 4595 u8 reserved_at_100[76][0x8]; 4596 u8 supported_issi_dw0[0x20]; 4597 }; 4598 4599 struct mlx5_ifc_query_issi_in_bits { 4600 u8 opcode[0x10]; 4601 u8 reserved_at_10[0x10]; 4602 4603 u8 reserved_at_20[0x10]; 4604 u8 op_mod[0x10]; 4605 4606 u8 reserved_at_40[0x40]; 4607 }; 4608 4609 struct mlx5_ifc_set_driver_version_out_bits { 4610 u8 status[0x8]; 4611 u8 reserved_0[0x18]; 4612 4613 u8 syndrome[0x20]; 4614 u8 reserved_1[0x40]; 4615 }; 4616 4617 struct mlx5_ifc_set_driver_version_in_bits { 4618 u8 opcode[0x10]; 4619 u8 reserved_0[0x10]; 4620 4621 u8 reserved_1[0x10]; 4622 u8 op_mod[0x10]; 4623 4624 u8 reserved_2[0x40]; 4625 u8 driver_version[64][0x8]; 4626 }; 4627 4628 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4629 u8 status[0x8]; 4630 u8 reserved_at_8[0x18]; 4631 4632 u8 syndrome[0x20]; 4633 4634 u8 reserved_at_40[0x40]; 4635 4636 struct mlx5_ifc_pkey_bits pkey[0]; 4637 }; 4638 4639 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4640 u8 opcode[0x10]; 4641 u8 reserved_at_10[0x10]; 4642 4643 u8 reserved_at_20[0x10]; 4644 u8 op_mod[0x10]; 4645 4646 u8 other_vport[0x1]; 4647 u8 reserved_at_41[0xb]; 4648 u8 port_num[0x4]; 4649 u8 vport_number[0x10]; 4650 4651 u8 reserved_at_60[0x10]; 4652 u8 pkey_index[0x10]; 4653 }; 4654 4655 enum { 4656 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4657 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4658 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4659 }; 4660 4661 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4662 u8 status[0x8]; 4663 u8 reserved_at_8[0x18]; 4664 4665 u8 syndrome[0x20]; 4666 4667 u8 reserved_at_40[0x20]; 4668 4669 u8 gids_num[0x10]; 4670 u8 reserved_at_70[0x10]; 4671 4672 struct mlx5_ifc_array128_auto_bits gid[0]; 4673 }; 4674 4675 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4676 u8 opcode[0x10]; 4677 u8 reserved_at_10[0x10]; 4678 4679 u8 reserved_at_20[0x10]; 4680 u8 op_mod[0x10]; 4681 4682 u8 other_vport[0x1]; 4683 u8 reserved_at_41[0xb]; 4684 u8 port_num[0x4]; 4685 u8 vport_number[0x10]; 4686 4687 u8 reserved_at_60[0x10]; 4688 u8 gid_index[0x10]; 4689 }; 4690 4691 struct mlx5_ifc_query_hca_vport_context_out_bits { 4692 u8 status[0x8]; 4693 u8 reserved_at_8[0x18]; 4694 4695 u8 syndrome[0x20]; 4696 4697 u8 reserved_at_40[0x40]; 4698 4699 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4700 }; 4701 4702 struct mlx5_ifc_query_hca_vport_context_in_bits { 4703 u8 opcode[0x10]; 4704 u8 reserved_at_10[0x10]; 4705 4706 u8 reserved_at_20[0x10]; 4707 u8 op_mod[0x10]; 4708 4709 u8 other_vport[0x1]; 4710 u8 reserved_at_41[0xb]; 4711 u8 port_num[0x4]; 4712 u8 vport_number[0x10]; 4713 4714 u8 reserved_at_60[0x20]; 4715 }; 4716 4717 struct mlx5_ifc_query_hca_cap_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_at_8[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_at_40[0x40]; 4724 4725 union mlx5_ifc_hca_cap_union_bits capability; 4726 }; 4727 4728 struct mlx5_ifc_query_hca_cap_in_bits { 4729 u8 opcode[0x10]; 4730 u8 reserved_at_10[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x40]; 4736 }; 4737 4738 struct mlx5_ifc_query_flow_table_out_bits { 4739 u8 status[0x8]; 4740 u8 reserved_at_8[0x18]; 4741 4742 u8 syndrome[0x20]; 4743 4744 u8 reserved_at_40[0x80]; 4745 4746 u8 reserved_at_c0[0x8]; 4747 u8 level[0x8]; 4748 u8 reserved_at_d0[0x8]; 4749 u8 log_size[0x8]; 4750 4751 u8 reserved_at_e0[0x120]; 4752 }; 4753 4754 struct mlx5_ifc_query_flow_table_in_bits { 4755 u8 opcode[0x10]; 4756 u8 reserved_at_10[0x10]; 4757 4758 u8 reserved_at_20[0x10]; 4759 u8 op_mod[0x10]; 4760 4761 u8 reserved_at_40[0x40]; 4762 4763 u8 table_type[0x8]; 4764 u8 reserved_at_88[0x18]; 4765 4766 u8 reserved_at_a0[0x8]; 4767 u8 table_id[0x18]; 4768 4769 u8 reserved_at_c0[0x140]; 4770 }; 4771 4772 struct mlx5_ifc_query_fte_out_bits { 4773 u8 status[0x8]; 4774 u8 reserved_at_8[0x18]; 4775 4776 u8 syndrome[0x20]; 4777 4778 u8 reserved_at_40[0x1c0]; 4779 4780 struct mlx5_ifc_flow_context_bits flow_context; 4781 }; 4782 4783 struct mlx5_ifc_query_fte_in_bits { 4784 u8 opcode[0x10]; 4785 u8 reserved_at_10[0x10]; 4786 4787 u8 reserved_at_20[0x10]; 4788 u8 op_mod[0x10]; 4789 4790 u8 reserved_at_40[0x40]; 4791 4792 u8 table_type[0x8]; 4793 u8 reserved_at_88[0x18]; 4794 4795 u8 reserved_at_a0[0x8]; 4796 u8 table_id[0x18]; 4797 4798 u8 reserved_at_c0[0x40]; 4799 4800 u8 flow_index[0x20]; 4801 4802 u8 reserved_at_120[0xe0]; 4803 }; 4804 4805 enum { 4806 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4807 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4808 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4809 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 4810 }; 4811 4812 struct mlx5_ifc_query_flow_group_out_bits { 4813 u8 status[0x8]; 4814 u8 reserved_at_8[0x18]; 4815 4816 u8 syndrome[0x20]; 4817 4818 u8 reserved_at_40[0xa0]; 4819 4820 u8 start_flow_index[0x20]; 4821 4822 u8 reserved_at_100[0x20]; 4823 4824 u8 end_flow_index[0x20]; 4825 4826 u8 reserved_at_140[0xa0]; 4827 4828 u8 reserved_at_1e0[0x18]; 4829 u8 match_criteria_enable[0x8]; 4830 4831 struct mlx5_ifc_fte_match_param_bits match_criteria; 4832 4833 u8 reserved_at_1200[0xe00]; 4834 }; 4835 4836 struct mlx5_ifc_query_flow_group_in_bits { 4837 u8 opcode[0x10]; 4838 u8 reserved_at_10[0x10]; 4839 4840 u8 reserved_at_20[0x10]; 4841 u8 op_mod[0x10]; 4842 4843 u8 reserved_at_40[0x40]; 4844 4845 u8 table_type[0x8]; 4846 u8 reserved_at_88[0x18]; 4847 4848 u8 reserved_at_a0[0x8]; 4849 u8 table_id[0x18]; 4850 4851 u8 group_id[0x20]; 4852 4853 u8 reserved_at_e0[0x120]; 4854 }; 4855 4856 struct mlx5_ifc_query_flow_counter_out_bits { 4857 u8 status[0x8]; 4858 u8 reserved_at_8[0x18]; 4859 4860 u8 syndrome[0x20]; 4861 4862 u8 reserved_at_40[0x40]; 4863 4864 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4865 }; 4866 4867 struct mlx5_ifc_query_flow_counter_in_bits { 4868 u8 opcode[0x10]; 4869 u8 reserved_at_10[0x10]; 4870 4871 u8 reserved_at_20[0x10]; 4872 u8 op_mod[0x10]; 4873 4874 u8 reserved_at_40[0x80]; 4875 4876 u8 clear[0x1]; 4877 u8 reserved_at_c1[0xf]; 4878 u8 num_of_counters[0x10]; 4879 4880 u8 flow_counter_id[0x20]; 4881 }; 4882 4883 struct mlx5_ifc_query_esw_vport_context_out_bits { 4884 u8 status[0x8]; 4885 u8 reserved_at_8[0x18]; 4886 4887 u8 syndrome[0x20]; 4888 4889 u8 reserved_at_40[0x40]; 4890 4891 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4892 }; 4893 4894 struct mlx5_ifc_query_esw_vport_context_in_bits { 4895 u8 opcode[0x10]; 4896 u8 reserved_at_10[0x10]; 4897 4898 u8 reserved_at_20[0x10]; 4899 u8 op_mod[0x10]; 4900 4901 u8 other_vport[0x1]; 4902 u8 reserved_at_41[0xf]; 4903 u8 vport_number[0x10]; 4904 4905 u8 reserved_at_60[0x20]; 4906 }; 4907 4908 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4909 u8 status[0x8]; 4910 u8 reserved_at_8[0x18]; 4911 4912 u8 syndrome[0x20]; 4913 4914 u8 reserved_at_40[0x40]; 4915 }; 4916 4917 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4918 u8 reserved_at_0[0x1c]; 4919 u8 vport_cvlan_insert[0x1]; 4920 u8 vport_svlan_insert[0x1]; 4921 u8 vport_cvlan_strip[0x1]; 4922 u8 vport_svlan_strip[0x1]; 4923 }; 4924 4925 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4926 u8 opcode[0x10]; 4927 u8 reserved_at_10[0x10]; 4928 4929 u8 reserved_at_20[0x10]; 4930 u8 op_mod[0x10]; 4931 4932 u8 other_vport[0x1]; 4933 u8 reserved_at_41[0xf]; 4934 u8 vport_number[0x10]; 4935 4936 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4937 4938 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4939 }; 4940 4941 struct mlx5_ifc_query_eq_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_at_8[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_at_40[0x40]; 4948 4949 struct mlx5_ifc_eqc_bits eq_context_entry; 4950 4951 u8 reserved_at_280[0x40]; 4952 4953 u8 event_bitmask[0x40]; 4954 4955 u8 reserved_at_300[0x580]; 4956 4957 u8 pas[0][0x40]; 4958 }; 4959 4960 struct mlx5_ifc_query_eq_in_bits { 4961 u8 opcode[0x10]; 4962 u8 reserved_at_10[0x10]; 4963 4964 u8 reserved_at_20[0x10]; 4965 u8 op_mod[0x10]; 4966 4967 u8 reserved_at_40[0x18]; 4968 u8 eq_number[0x8]; 4969 4970 u8 reserved_at_60[0x20]; 4971 }; 4972 4973 struct mlx5_ifc_packet_reformat_context_in_bits { 4974 u8 reserved_at_0[0x5]; 4975 u8 reformat_type[0x3]; 4976 u8 reserved_at_8[0xe]; 4977 u8 reformat_data_size[0xa]; 4978 4979 u8 reserved_at_20[0x10]; 4980 u8 reformat_data[2][0x8]; 4981 4982 u8 more_reformat_data[0][0x8]; 4983 }; 4984 4985 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4986 u8 status[0x8]; 4987 u8 reserved_at_8[0x18]; 4988 4989 u8 syndrome[0x20]; 4990 4991 u8 reserved_at_40[0xa0]; 4992 4993 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4994 }; 4995 4996 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4997 u8 opcode[0x10]; 4998 u8 reserved_at_10[0x10]; 4999 5000 u8 reserved_at_20[0x10]; 5001 u8 op_mod[0x10]; 5002 5003 u8 packet_reformat_id[0x20]; 5004 5005 u8 reserved_at_60[0xa0]; 5006 }; 5007 5008 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5009 u8 status[0x8]; 5010 u8 reserved_at_8[0x18]; 5011 5012 u8 syndrome[0x20]; 5013 5014 u8 packet_reformat_id[0x20]; 5015 5016 u8 reserved_at_60[0x20]; 5017 }; 5018 5019 enum { 5020 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5021 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5022 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5023 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5024 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5025 }; 5026 5027 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5028 u8 opcode[0x10]; 5029 u8 reserved_at_10[0x10]; 5030 5031 u8 reserved_at_20[0x10]; 5032 u8 op_mod[0x10]; 5033 5034 u8 reserved_at_40[0xa0]; 5035 5036 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5037 }; 5038 5039 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5040 u8 status[0x8]; 5041 u8 reserved_at_8[0x18]; 5042 5043 u8 syndrome[0x20]; 5044 5045 u8 reserved_at_40[0x40]; 5046 }; 5047 5048 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5049 u8 opcode[0x10]; 5050 u8 reserved_at_10[0x10]; 5051 5052 u8 reserved_20[0x10]; 5053 u8 op_mod[0x10]; 5054 5055 u8 packet_reformat_id[0x20]; 5056 5057 u8 reserved_60[0x20]; 5058 }; 5059 5060 struct mlx5_ifc_set_action_in_bits { 5061 u8 action_type[0x4]; 5062 u8 field[0xc]; 5063 u8 reserved_at_10[0x3]; 5064 u8 offset[0x5]; 5065 u8 reserved_at_18[0x3]; 5066 u8 length[0x5]; 5067 5068 u8 data[0x20]; 5069 }; 5070 5071 struct mlx5_ifc_add_action_in_bits { 5072 u8 action_type[0x4]; 5073 u8 field[0xc]; 5074 u8 reserved_at_10[0x10]; 5075 5076 u8 data[0x20]; 5077 }; 5078 5079 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5080 struct mlx5_ifc_set_action_in_bits set_action_in; 5081 struct mlx5_ifc_add_action_in_bits add_action_in; 5082 u8 reserved_at_0[0x40]; 5083 }; 5084 5085 enum { 5086 MLX5_ACTION_TYPE_SET = 0x1, 5087 MLX5_ACTION_TYPE_ADD = 0x2, 5088 }; 5089 5090 enum { 5091 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5092 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5093 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5094 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5095 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5096 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5097 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5098 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5099 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5100 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5101 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5102 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5103 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5104 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5105 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5106 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5107 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5108 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5109 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5110 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5111 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5112 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5113 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5114 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5115 }; 5116 5117 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 modify_header_id[0x20]; 5124 5125 u8 reserved_at_60[0x20]; 5126 }; 5127 5128 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5129 u8 opcode[0x10]; 5130 u8 reserved_at_10[0x10]; 5131 5132 u8 reserved_at_20[0x10]; 5133 u8 op_mod[0x10]; 5134 5135 u8 reserved_at_40[0x20]; 5136 5137 u8 table_type[0x8]; 5138 u8 reserved_at_68[0x10]; 5139 u8 num_of_actions[0x8]; 5140 5141 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5142 }; 5143 5144 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5145 u8 status[0x8]; 5146 u8 reserved_at_8[0x18]; 5147 5148 u8 syndrome[0x20]; 5149 5150 u8 reserved_at_40[0x40]; 5151 }; 5152 5153 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 modify_header_id[0x20]; 5161 5162 u8 reserved_at_60[0x20]; 5163 }; 5164 5165 struct mlx5_ifc_query_dct_out_bits { 5166 u8 status[0x8]; 5167 u8 reserved_at_8[0x18]; 5168 5169 u8 syndrome[0x20]; 5170 5171 u8 reserved_at_40[0x40]; 5172 5173 struct mlx5_ifc_dctc_bits dct_context_entry; 5174 5175 u8 reserved_at_280[0x180]; 5176 }; 5177 5178 struct mlx5_ifc_query_dct_in_bits { 5179 u8 opcode[0x10]; 5180 u8 reserved_at_10[0x10]; 5181 5182 u8 reserved_at_20[0x10]; 5183 u8 op_mod[0x10]; 5184 5185 u8 reserved_at_40[0x8]; 5186 u8 dctn[0x18]; 5187 5188 u8 reserved_at_60[0x20]; 5189 }; 5190 5191 struct mlx5_ifc_query_cq_out_bits { 5192 u8 status[0x8]; 5193 u8 reserved_at_8[0x18]; 5194 5195 u8 syndrome[0x20]; 5196 5197 u8 reserved_at_40[0x40]; 5198 5199 struct mlx5_ifc_cqc_bits cq_context; 5200 5201 u8 reserved_at_280[0x600]; 5202 5203 u8 pas[0][0x40]; 5204 }; 5205 5206 struct mlx5_ifc_query_cq_in_bits { 5207 u8 opcode[0x10]; 5208 u8 reserved_at_10[0x10]; 5209 5210 u8 reserved_at_20[0x10]; 5211 u8 op_mod[0x10]; 5212 5213 u8 reserved_at_40[0x8]; 5214 u8 cqn[0x18]; 5215 5216 u8 reserved_at_60[0x20]; 5217 }; 5218 5219 struct mlx5_ifc_query_cong_status_out_bits { 5220 u8 status[0x8]; 5221 u8 reserved_at_8[0x18]; 5222 5223 u8 syndrome[0x20]; 5224 5225 u8 reserved_at_40[0x20]; 5226 5227 u8 enable[0x1]; 5228 u8 tag_enable[0x1]; 5229 u8 reserved_at_62[0x1e]; 5230 }; 5231 5232 struct mlx5_ifc_query_cong_status_in_bits { 5233 u8 opcode[0x10]; 5234 u8 reserved_at_10[0x10]; 5235 5236 u8 reserved_at_20[0x10]; 5237 u8 op_mod[0x10]; 5238 5239 u8 reserved_at_40[0x18]; 5240 u8 priority[0x4]; 5241 u8 cong_protocol[0x4]; 5242 5243 u8 reserved_at_60[0x20]; 5244 }; 5245 5246 struct mlx5_ifc_query_cong_statistics_out_bits { 5247 u8 status[0x8]; 5248 u8 reserved_at_8[0x18]; 5249 5250 u8 syndrome[0x20]; 5251 5252 u8 reserved_at_40[0x40]; 5253 5254 u8 rp_cur_flows[0x20]; 5255 5256 u8 sum_flows[0x20]; 5257 5258 u8 rp_cnp_ignored_high[0x20]; 5259 5260 u8 rp_cnp_ignored_low[0x20]; 5261 5262 u8 rp_cnp_handled_high[0x20]; 5263 5264 u8 rp_cnp_handled_low[0x20]; 5265 5266 u8 reserved_at_140[0x100]; 5267 5268 u8 time_stamp_high[0x20]; 5269 5270 u8 time_stamp_low[0x20]; 5271 5272 u8 accumulators_period[0x20]; 5273 5274 u8 np_ecn_marked_roce_packets_high[0x20]; 5275 5276 u8 np_ecn_marked_roce_packets_low[0x20]; 5277 5278 u8 np_cnp_sent_high[0x20]; 5279 5280 u8 np_cnp_sent_low[0x20]; 5281 5282 u8 reserved_at_320[0x560]; 5283 }; 5284 5285 struct mlx5_ifc_query_cong_statistics_in_bits { 5286 u8 opcode[0x10]; 5287 u8 reserved_at_10[0x10]; 5288 5289 u8 reserved_at_20[0x10]; 5290 u8 op_mod[0x10]; 5291 5292 u8 clear[0x1]; 5293 u8 reserved_at_41[0x1f]; 5294 5295 u8 reserved_at_60[0x20]; 5296 }; 5297 5298 struct mlx5_ifc_query_cong_params_out_bits { 5299 u8 status[0x8]; 5300 u8 reserved_at_8[0x18]; 5301 5302 u8 syndrome[0x20]; 5303 5304 u8 reserved_at_40[0x40]; 5305 5306 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5307 }; 5308 5309 struct mlx5_ifc_query_cong_params_in_bits { 5310 u8 opcode[0x10]; 5311 u8 reserved_at_10[0x10]; 5312 5313 u8 reserved_at_20[0x10]; 5314 u8 op_mod[0x10]; 5315 5316 u8 reserved_at_40[0x1c]; 5317 u8 cong_protocol[0x4]; 5318 5319 u8 reserved_at_60[0x20]; 5320 }; 5321 5322 struct mlx5_ifc_query_adapter_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_at_40[0x40]; 5329 5330 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5331 }; 5332 5333 struct mlx5_ifc_query_adapter_in_bits { 5334 u8 opcode[0x10]; 5335 u8 reserved_at_10[0x10]; 5336 5337 u8 reserved_at_20[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 reserved_at_40[0x40]; 5341 }; 5342 5343 struct mlx5_ifc_qp_2rst_out_bits { 5344 u8 status[0x8]; 5345 u8 reserved_at_8[0x18]; 5346 5347 u8 syndrome[0x20]; 5348 5349 u8 reserved_at_40[0x40]; 5350 }; 5351 5352 struct mlx5_ifc_qp_2rst_in_bits { 5353 u8 opcode[0x10]; 5354 u8 uid[0x10]; 5355 5356 u8 reserved_at_20[0x10]; 5357 u8 op_mod[0x10]; 5358 5359 u8 reserved_at_40[0x8]; 5360 u8 qpn[0x18]; 5361 5362 u8 reserved_at_60[0x20]; 5363 }; 5364 5365 struct mlx5_ifc_qp_2err_out_bits { 5366 u8 status[0x8]; 5367 u8 reserved_at_8[0x18]; 5368 5369 u8 syndrome[0x20]; 5370 5371 u8 reserved_at_40[0x40]; 5372 }; 5373 5374 struct mlx5_ifc_qp_2err_in_bits { 5375 u8 opcode[0x10]; 5376 u8 uid[0x10]; 5377 5378 u8 reserved_at_20[0x10]; 5379 u8 op_mod[0x10]; 5380 5381 u8 reserved_at_40[0x8]; 5382 u8 qpn[0x18]; 5383 5384 u8 reserved_at_60[0x20]; 5385 }; 5386 5387 struct mlx5_ifc_page_fault_resume_out_bits { 5388 u8 status[0x8]; 5389 u8 reserved_at_8[0x18]; 5390 5391 u8 syndrome[0x20]; 5392 5393 u8 reserved_at_40[0x40]; 5394 }; 5395 5396 struct mlx5_ifc_page_fault_resume_in_bits { 5397 u8 opcode[0x10]; 5398 u8 reserved_at_10[0x10]; 5399 5400 u8 reserved_at_20[0x10]; 5401 u8 op_mod[0x10]; 5402 5403 u8 error[0x1]; 5404 u8 reserved_at_41[0x4]; 5405 u8 page_fault_type[0x3]; 5406 u8 wq_number[0x18]; 5407 5408 u8 reserved_at_60[0x8]; 5409 u8 token[0x18]; 5410 }; 5411 5412 struct mlx5_ifc_nop_out_bits { 5413 u8 status[0x8]; 5414 u8 reserved_at_8[0x18]; 5415 5416 u8 syndrome[0x20]; 5417 5418 u8 reserved_at_40[0x40]; 5419 }; 5420 5421 struct mlx5_ifc_nop_in_bits { 5422 u8 opcode[0x10]; 5423 u8 reserved_at_10[0x10]; 5424 5425 u8 reserved_at_20[0x10]; 5426 u8 op_mod[0x10]; 5427 5428 u8 reserved_at_40[0x40]; 5429 }; 5430 5431 struct mlx5_ifc_modify_vport_state_out_bits { 5432 u8 status[0x8]; 5433 u8 reserved_at_8[0x18]; 5434 5435 u8 syndrome[0x20]; 5436 5437 u8 reserved_at_40[0x40]; 5438 }; 5439 5440 struct mlx5_ifc_modify_vport_state_in_bits { 5441 u8 opcode[0x10]; 5442 u8 reserved_at_10[0x10]; 5443 5444 u8 reserved_at_20[0x10]; 5445 u8 op_mod[0x10]; 5446 5447 u8 other_vport[0x1]; 5448 u8 reserved_at_41[0xf]; 5449 u8 vport_number[0x10]; 5450 5451 u8 reserved_at_60[0x18]; 5452 u8 admin_state[0x4]; 5453 u8 reserved_at_7c[0x4]; 5454 }; 5455 5456 struct mlx5_ifc_modify_tis_out_bits { 5457 u8 status[0x8]; 5458 u8 reserved_at_8[0x18]; 5459 5460 u8 syndrome[0x20]; 5461 5462 u8 reserved_at_40[0x40]; 5463 }; 5464 5465 struct mlx5_ifc_modify_tis_bitmask_bits { 5466 u8 reserved_at_0[0x20]; 5467 5468 u8 reserved_at_20[0x1d]; 5469 u8 lag_tx_port_affinity[0x1]; 5470 u8 strict_lag_tx_port_affinity[0x1]; 5471 u8 prio[0x1]; 5472 }; 5473 5474 struct mlx5_ifc_modify_tis_in_bits { 5475 u8 opcode[0x10]; 5476 u8 uid[0x10]; 5477 5478 u8 reserved_at_20[0x10]; 5479 u8 op_mod[0x10]; 5480 5481 u8 reserved_at_40[0x8]; 5482 u8 tisn[0x18]; 5483 5484 u8 reserved_at_60[0x20]; 5485 5486 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5487 5488 u8 reserved_at_c0[0x40]; 5489 5490 struct mlx5_ifc_tisc_bits ctx; 5491 }; 5492 5493 struct mlx5_ifc_modify_tir_bitmask_bits { 5494 u8 reserved_at_0[0x20]; 5495 5496 u8 reserved_at_20[0x1b]; 5497 u8 self_lb_en[0x1]; 5498 u8 reserved_at_3c[0x1]; 5499 u8 hash[0x1]; 5500 u8 reserved_at_3e[0x1]; 5501 u8 lro[0x1]; 5502 }; 5503 5504 struct mlx5_ifc_modify_tir_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_at_8[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_at_40[0x40]; 5511 }; 5512 5513 struct mlx5_ifc_modify_tir_in_bits { 5514 u8 opcode[0x10]; 5515 u8 uid[0x10]; 5516 5517 u8 reserved_at_20[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 reserved_at_40[0x8]; 5521 u8 tirn[0x18]; 5522 5523 u8 reserved_at_60[0x20]; 5524 5525 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5526 5527 u8 reserved_at_c0[0x40]; 5528 5529 struct mlx5_ifc_tirc_bits ctx; 5530 }; 5531 5532 struct mlx5_ifc_modify_sq_out_bits { 5533 u8 status[0x8]; 5534 u8 reserved_at_8[0x18]; 5535 5536 u8 syndrome[0x20]; 5537 5538 u8 reserved_at_40[0x40]; 5539 }; 5540 5541 struct mlx5_ifc_modify_sq_in_bits { 5542 u8 opcode[0x10]; 5543 u8 uid[0x10]; 5544 5545 u8 reserved_at_20[0x10]; 5546 u8 op_mod[0x10]; 5547 5548 u8 sq_state[0x4]; 5549 u8 reserved_at_44[0x4]; 5550 u8 sqn[0x18]; 5551 5552 u8 reserved_at_60[0x20]; 5553 5554 u8 modify_bitmask[0x40]; 5555 5556 u8 reserved_at_c0[0x40]; 5557 5558 struct mlx5_ifc_sqc_bits ctx; 5559 }; 5560 5561 struct mlx5_ifc_modify_scheduling_element_out_bits { 5562 u8 status[0x8]; 5563 u8 reserved_at_8[0x18]; 5564 5565 u8 syndrome[0x20]; 5566 5567 u8 reserved_at_40[0x1c0]; 5568 }; 5569 5570 enum { 5571 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5572 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5573 }; 5574 5575 struct mlx5_ifc_modify_scheduling_element_in_bits { 5576 u8 opcode[0x10]; 5577 u8 reserved_at_10[0x10]; 5578 5579 u8 reserved_at_20[0x10]; 5580 u8 op_mod[0x10]; 5581 5582 u8 scheduling_hierarchy[0x8]; 5583 u8 reserved_at_48[0x18]; 5584 5585 u8 scheduling_element_id[0x20]; 5586 5587 u8 reserved_at_80[0x20]; 5588 5589 u8 modify_bitmask[0x20]; 5590 5591 u8 reserved_at_c0[0x40]; 5592 5593 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5594 5595 u8 reserved_at_300[0x100]; 5596 }; 5597 5598 struct mlx5_ifc_modify_rqt_out_bits { 5599 u8 status[0x8]; 5600 u8 reserved_at_8[0x18]; 5601 5602 u8 syndrome[0x20]; 5603 5604 u8 reserved_at_40[0x40]; 5605 }; 5606 5607 struct mlx5_ifc_rqt_bitmask_bits { 5608 u8 reserved_at_0[0x20]; 5609 5610 u8 reserved_at_20[0x1f]; 5611 u8 rqn_list[0x1]; 5612 }; 5613 5614 struct mlx5_ifc_modify_rqt_in_bits { 5615 u8 opcode[0x10]; 5616 u8 uid[0x10]; 5617 5618 u8 reserved_at_20[0x10]; 5619 u8 op_mod[0x10]; 5620 5621 u8 reserved_at_40[0x8]; 5622 u8 rqtn[0x18]; 5623 5624 u8 reserved_at_60[0x20]; 5625 5626 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5627 5628 u8 reserved_at_c0[0x40]; 5629 5630 struct mlx5_ifc_rqtc_bits ctx; 5631 }; 5632 5633 struct mlx5_ifc_modify_rq_out_bits { 5634 u8 status[0x8]; 5635 u8 reserved_at_8[0x18]; 5636 5637 u8 syndrome[0x20]; 5638 5639 u8 reserved_at_40[0x40]; 5640 }; 5641 5642 enum { 5643 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5644 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5645 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5646 }; 5647 5648 struct mlx5_ifc_modify_rq_in_bits { 5649 u8 opcode[0x10]; 5650 u8 uid[0x10]; 5651 5652 u8 reserved_at_20[0x10]; 5653 u8 op_mod[0x10]; 5654 5655 u8 rq_state[0x4]; 5656 u8 reserved_at_44[0x4]; 5657 u8 rqn[0x18]; 5658 5659 u8 reserved_at_60[0x20]; 5660 5661 u8 modify_bitmask[0x40]; 5662 5663 u8 reserved_at_c0[0x40]; 5664 5665 struct mlx5_ifc_rqc_bits ctx; 5666 }; 5667 5668 struct mlx5_ifc_modify_rmp_out_bits { 5669 u8 status[0x8]; 5670 u8 reserved_at_8[0x18]; 5671 5672 u8 syndrome[0x20]; 5673 5674 u8 reserved_at_40[0x40]; 5675 }; 5676 5677 struct mlx5_ifc_rmp_bitmask_bits { 5678 u8 reserved_at_0[0x20]; 5679 5680 u8 reserved_at_20[0x1f]; 5681 u8 lwm[0x1]; 5682 }; 5683 5684 struct mlx5_ifc_modify_rmp_in_bits { 5685 u8 opcode[0x10]; 5686 u8 uid[0x10]; 5687 5688 u8 reserved_at_20[0x10]; 5689 u8 op_mod[0x10]; 5690 5691 u8 rmp_state[0x4]; 5692 u8 reserved_at_44[0x4]; 5693 u8 rmpn[0x18]; 5694 5695 u8 reserved_at_60[0x20]; 5696 5697 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5698 5699 u8 reserved_at_c0[0x40]; 5700 5701 struct mlx5_ifc_rmpc_bits ctx; 5702 }; 5703 5704 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5705 u8 status[0x8]; 5706 u8 reserved_at_8[0x18]; 5707 5708 u8 syndrome[0x20]; 5709 5710 u8 reserved_at_40[0x40]; 5711 }; 5712 5713 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5714 u8 reserved_at_0[0x12]; 5715 u8 affiliation[0x1]; 5716 u8 reserved_at_13[0x1]; 5717 u8 disable_uc_local_lb[0x1]; 5718 u8 disable_mc_local_lb[0x1]; 5719 u8 node_guid[0x1]; 5720 u8 port_guid[0x1]; 5721 u8 min_inline[0x1]; 5722 u8 mtu[0x1]; 5723 u8 change_event[0x1]; 5724 u8 promisc[0x1]; 5725 u8 permanent_address[0x1]; 5726 u8 addresses_list[0x1]; 5727 u8 roce_en[0x1]; 5728 u8 reserved_at_1f[0x1]; 5729 }; 5730 5731 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 other_vport[0x1]; 5739 u8 reserved_at_41[0xf]; 5740 u8 vport_number[0x10]; 5741 5742 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5743 5744 u8 reserved_at_80[0x780]; 5745 5746 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5747 }; 5748 5749 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5750 u8 status[0x8]; 5751 u8 reserved_at_8[0x18]; 5752 5753 u8 syndrome[0x20]; 5754 5755 u8 reserved_at_40[0x40]; 5756 }; 5757 5758 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5759 u8 opcode[0x10]; 5760 u8 reserved_at_10[0x10]; 5761 5762 u8 reserved_at_20[0x10]; 5763 u8 op_mod[0x10]; 5764 5765 u8 other_vport[0x1]; 5766 u8 reserved_at_41[0xb]; 5767 u8 port_num[0x4]; 5768 u8 vport_number[0x10]; 5769 5770 u8 reserved_at_60[0x20]; 5771 5772 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5773 }; 5774 5775 struct mlx5_ifc_modify_cq_out_bits { 5776 u8 status[0x8]; 5777 u8 reserved_at_8[0x18]; 5778 5779 u8 syndrome[0x20]; 5780 5781 u8 reserved_at_40[0x40]; 5782 }; 5783 5784 enum { 5785 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5786 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5787 }; 5788 5789 struct mlx5_ifc_modify_cq_in_bits { 5790 u8 opcode[0x10]; 5791 u8 uid[0x10]; 5792 5793 u8 reserved_at_20[0x10]; 5794 u8 op_mod[0x10]; 5795 5796 u8 reserved_at_40[0x8]; 5797 u8 cqn[0x18]; 5798 5799 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5800 5801 struct mlx5_ifc_cqc_bits cq_context; 5802 5803 u8 reserved_at_280[0x40]; 5804 5805 u8 cq_umem_valid[0x1]; 5806 u8 reserved_at_2c1[0x5bf]; 5807 5808 u8 pas[0][0x40]; 5809 }; 5810 5811 struct mlx5_ifc_modify_cong_status_out_bits { 5812 u8 status[0x8]; 5813 u8 reserved_at_8[0x18]; 5814 5815 u8 syndrome[0x20]; 5816 5817 u8 reserved_at_40[0x40]; 5818 }; 5819 5820 struct mlx5_ifc_modify_cong_status_in_bits { 5821 u8 opcode[0x10]; 5822 u8 reserved_at_10[0x10]; 5823 5824 u8 reserved_at_20[0x10]; 5825 u8 op_mod[0x10]; 5826 5827 u8 reserved_at_40[0x18]; 5828 u8 priority[0x4]; 5829 u8 cong_protocol[0x4]; 5830 5831 u8 enable[0x1]; 5832 u8 tag_enable[0x1]; 5833 u8 reserved_at_62[0x1e]; 5834 }; 5835 5836 struct mlx5_ifc_modify_cong_params_out_bits { 5837 u8 status[0x8]; 5838 u8 reserved_at_8[0x18]; 5839 5840 u8 syndrome[0x20]; 5841 5842 u8 reserved_at_40[0x40]; 5843 }; 5844 5845 struct mlx5_ifc_modify_cong_params_in_bits { 5846 u8 opcode[0x10]; 5847 u8 reserved_at_10[0x10]; 5848 5849 u8 reserved_at_20[0x10]; 5850 u8 op_mod[0x10]; 5851 5852 u8 reserved_at_40[0x1c]; 5853 u8 cong_protocol[0x4]; 5854 5855 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5856 5857 u8 reserved_at_80[0x80]; 5858 5859 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5860 }; 5861 5862 struct mlx5_ifc_manage_pages_out_bits { 5863 u8 status[0x8]; 5864 u8 reserved_at_8[0x18]; 5865 5866 u8 syndrome[0x20]; 5867 5868 u8 output_num_entries[0x20]; 5869 5870 u8 reserved_at_60[0x20]; 5871 5872 u8 pas[0][0x40]; 5873 }; 5874 5875 enum { 5876 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5877 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5878 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5879 }; 5880 5881 struct mlx5_ifc_manage_pages_in_bits { 5882 u8 opcode[0x10]; 5883 u8 reserved_at_10[0x10]; 5884 5885 u8 reserved_at_20[0x10]; 5886 u8 op_mod[0x10]; 5887 5888 u8 embedded_cpu_function[0x1]; 5889 u8 reserved_at_41[0xf]; 5890 u8 function_id[0x10]; 5891 5892 u8 input_num_entries[0x20]; 5893 5894 u8 pas[0][0x40]; 5895 }; 5896 5897 struct mlx5_ifc_mad_ifc_out_bits { 5898 u8 status[0x8]; 5899 u8 reserved_at_8[0x18]; 5900 5901 u8 syndrome[0x20]; 5902 5903 u8 reserved_at_40[0x40]; 5904 5905 u8 response_mad_packet[256][0x8]; 5906 }; 5907 5908 struct mlx5_ifc_mad_ifc_in_bits { 5909 u8 opcode[0x10]; 5910 u8 reserved_at_10[0x10]; 5911 5912 u8 reserved_at_20[0x10]; 5913 u8 op_mod[0x10]; 5914 5915 u8 remote_lid[0x10]; 5916 u8 reserved_at_50[0x8]; 5917 u8 port[0x8]; 5918 5919 u8 reserved_at_60[0x20]; 5920 5921 u8 mad[256][0x8]; 5922 }; 5923 5924 struct mlx5_ifc_init_hca_out_bits { 5925 u8 status[0x8]; 5926 u8 reserved_at_8[0x18]; 5927 5928 u8 syndrome[0x20]; 5929 5930 u8 reserved_at_40[0x40]; 5931 }; 5932 5933 struct mlx5_ifc_init_hca_in_bits { 5934 u8 opcode[0x10]; 5935 u8 reserved_at_10[0x10]; 5936 5937 u8 reserved_at_20[0x10]; 5938 u8 op_mod[0x10]; 5939 5940 u8 reserved_at_40[0x40]; 5941 u8 sw_owner_id[4][0x20]; 5942 }; 5943 5944 struct mlx5_ifc_init2rtr_qp_out_bits { 5945 u8 status[0x8]; 5946 u8 reserved_at_8[0x18]; 5947 5948 u8 syndrome[0x20]; 5949 5950 u8 reserved_at_40[0x40]; 5951 }; 5952 5953 struct mlx5_ifc_init2rtr_qp_in_bits { 5954 u8 opcode[0x10]; 5955 u8 uid[0x10]; 5956 5957 u8 reserved_at_20[0x10]; 5958 u8 op_mod[0x10]; 5959 5960 u8 reserved_at_40[0x8]; 5961 u8 qpn[0x18]; 5962 5963 u8 reserved_at_60[0x20]; 5964 5965 u8 opt_param_mask[0x20]; 5966 5967 u8 reserved_at_a0[0x20]; 5968 5969 struct mlx5_ifc_qpc_bits qpc; 5970 5971 u8 reserved_at_800[0x80]; 5972 }; 5973 5974 struct mlx5_ifc_init2init_qp_out_bits { 5975 u8 status[0x8]; 5976 u8 reserved_at_8[0x18]; 5977 5978 u8 syndrome[0x20]; 5979 5980 u8 reserved_at_40[0x40]; 5981 }; 5982 5983 struct mlx5_ifc_init2init_qp_in_bits { 5984 u8 opcode[0x10]; 5985 u8 uid[0x10]; 5986 5987 u8 reserved_at_20[0x10]; 5988 u8 op_mod[0x10]; 5989 5990 u8 reserved_at_40[0x8]; 5991 u8 qpn[0x18]; 5992 5993 u8 reserved_at_60[0x20]; 5994 5995 u8 opt_param_mask[0x20]; 5996 5997 u8 reserved_at_a0[0x20]; 5998 5999 struct mlx5_ifc_qpc_bits qpc; 6000 6001 u8 reserved_at_800[0x80]; 6002 }; 6003 6004 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6005 u8 status[0x8]; 6006 u8 reserved_at_8[0x18]; 6007 6008 u8 syndrome[0x20]; 6009 6010 u8 reserved_at_40[0x40]; 6011 6012 u8 packet_headers_log[128][0x8]; 6013 6014 u8 packet_syndrome[64][0x8]; 6015 }; 6016 6017 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6018 u8 opcode[0x10]; 6019 u8 reserved_at_10[0x10]; 6020 6021 u8 reserved_at_20[0x10]; 6022 u8 op_mod[0x10]; 6023 6024 u8 reserved_at_40[0x40]; 6025 }; 6026 6027 struct mlx5_ifc_gen_eqe_in_bits { 6028 u8 opcode[0x10]; 6029 u8 reserved_at_10[0x10]; 6030 6031 u8 reserved_at_20[0x10]; 6032 u8 op_mod[0x10]; 6033 6034 u8 reserved_at_40[0x18]; 6035 u8 eq_number[0x8]; 6036 6037 u8 reserved_at_60[0x20]; 6038 6039 u8 eqe[64][0x8]; 6040 }; 6041 6042 struct mlx5_ifc_gen_eq_out_bits { 6043 u8 status[0x8]; 6044 u8 reserved_at_8[0x18]; 6045 6046 u8 syndrome[0x20]; 6047 6048 u8 reserved_at_40[0x40]; 6049 }; 6050 6051 struct mlx5_ifc_enable_hca_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_at_8[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_at_40[0x20]; 6058 }; 6059 6060 struct mlx5_ifc_enable_hca_in_bits { 6061 u8 opcode[0x10]; 6062 u8 reserved_at_10[0x10]; 6063 6064 u8 reserved_at_20[0x10]; 6065 u8 op_mod[0x10]; 6066 6067 u8 embedded_cpu_function[0x1]; 6068 u8 reserved_at_41[0xf]; 6069 u8 function_id[0x10]; 6070 6071 u8 reserved_at_60[0x20]; 6072 }; 6073 6074 struct mlx5_ifc_drain_dct_out_bits { 6075 u8 status[0x8]; 6076 u8 reserved_at_8[0x18]; 6077 6078 u8 syndrome[0x20]; 6079 6080 u8 reserved_at_40[0x40]; 6081 }; 6082 6083 struct mlx5_ifc_drain_dct_in_bits { 6084 u8 opcode[0x10]; 6085 u8 uid[0x10]; 6086 6087 u8 reserved_at_20[0x10]; 6088 u8 op_mod[0x10]; 6089 6090 u8 reserved_at_40[0x8]; 6091 u8 dctn[0x18]; 6092 6093 u8 reserved_at_60[0x20]; 6094 }; 6095 6096 struct mlx5_ifc_disable_hca_out_bits { 6097 u8 status[0x8]; 6098 u8 reserved_at_8[0x18]; 6099 6100 u8 syndrome[0x20]; 6101 6102 u8 reserved_at_40[0x20]; 6103 }; 6104 6105 struct mlx5_ifc_disable_hca_in_bits { 6106 u8 opcode[0x10]; 6107 u8 reserved_at_10[0x10]; 6108 6109 u8 reserved_at_20[0x10]; 6110 u8 op_mod[0x10]; 6111 6112 u8 embedded_cpu_function[0x1]; 6113 u8 reserved_at_41[0xf]; 6114 u8 function_id[0x10]; 6115 6116 u8 reserved_at_60[0x20]; 6117 }; 6118 6119 struct mlx5_ifc_detach_from_mcg_out_bits { 6120 u8 status[0x8]; 6121 u8 reserved_at_8[0x18]; 6122 6123 u8 syndrome[0x20]; 6124 6125 u8 reserved_at_40[0x40]; 6126 }; 6127 6128 struct mlx5_ifc_detach_from_mcg_in_bits { 6129 u8 opcode[0x10]; 6130 u8 uid[0x10]; 6131 6132 u8 reserved_at_20[0x10]; 6133 u8 op_mod[0x10]; 6134 6135 u8 reserved_at_40[0x8]; 6136 u8 qpn[0x18]; 6137 6138 u8 reserved_at_60[0x20]; 6139 6140 u8 multicast_gid[16][0x8]; 6141 }; 6142 6143 struct mlx5_ifc_destroy_xrq_out_bits { 6144 u8 status[0x8]; 6145 u8 reserved_at_8[0x18]; 6146 6147 u8 syndrome[0x20]; 6148 6149 u8 reserved_at_40[0x40]; 6150 }; 6151 6152 struct mlx5_ifc_destroy_xrq_in_bits { 6153 u8 opcode[0x10]; 6154 u8 uid[0x10]; 6155 6156 u8 reserved_at_20[0x10]; 6157 u8 op_mod[0x10]; 6158 6159 u8 reserved_at_40[0x8]; 6160 u8 xrqn[0x18]; 6161 6162 u8 reserved_at_60[0x20]; 6163 }; 6164 6165 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6166 u8 status[0x8]; 6167 u8 reserved_at_8[0x18]; 6168 6169 u8 syndrome[0x20]; 6170 6171 u8 reserved_at_40[0x40]; 6172 }; 6173 6174 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6175 u8 opcode[0x10]; 6176 u8 uid[0x10]; 6177 6178 u8 reserved_at_20[0x10]; 6179 u8 op_mod[0x10]; 6180 6181 u8 reserved_at_40[0x8]; 6182 u8 xrc_srqn[0x18]; 6183 6184 u8 reserved_at_60[0x20]; 6185 }; 6186 6187 struct mlx5_ifc_destroy_tis_out_bits { 6188 u8 status[0x8]; 6189 u8 reserved_at_8[0x18]; 6190 6191 u8 syndrome[0x20]; 6192 6193 u8 reserved_at_40[0x40]; 6194 }; 6195 6196 struct mlx5_ifc_destroy_tis_in_bits { 6197 u8 opcode[0x10]; 6198 u8 uid[0x10]; 6199 6200 u8 reserved_at_20[0x10]; 6201 u8 op_mod[0x10]; 6202 6203 u8 reserved_at_40[0x8]; 6204 u8 tisn[0x18]; 6205 6206 u8 reserved_at_60[0x20]; 6207 }; 6208 6209 struct mlx5_ifc_destroy_tir_out_bits { 6210 u8 status[0x8]; 6211 u8 reserved_at_8[0x18]; 6212 6213 u8 syndrome[0x20]; 6214 6215 u8 reserved_at_40[0x40]; 6216 }; 6217 6218 struct mlx5_ifc_destroy_tir_in_bits { 6219 u8 opcode[0x10]; 6220 u8 uid[0x10]; 6221 6222 u8 reserved_at_20[0x10]; 6223 u8 op_mod[0x10]; 6224 6225 u8 reserved_at_40[0x8]; 6226 u8 tirn[0x18]; 6227 6228 u8 reserved_at_60[0x20]; 6229 }; 6230 6231 struct mlx5_ifc_destroy_srq_out_bits { 6232 u8 status[0x8]; 6233 u8 reserved_at_8[0x18]; 6234 6235 u8 syndrome[0x20]; 6236 6237 u8 reserved_at_40[0x40]; 6238 }; 6239 6240 struct mlx5_ifc_destroy_srq_in_bits { 6241 u8 opcode[0x10]; 6242 u8 uid[0x10]; 6243 6244 u8 reserved_at_20[0x10]; 6245 u8 op_mod[0x10]; 6246 6247 u8 reserved_at_40[0x8]; 6248 u8 srqn[0x18]; 6249 6250 u8 reserved_at_60[0x20]; 6251 }; 6252 6253 struct mlx5_ifc_destroy_sq_out_bits { 6254 u8 status[0x8]; 6255 u8 reserved_at_8[0x18]; 6256 6257 u8 syndrome[0x20]; 6258 6259 u8 reserved_at_40[0x40]; 6260 }; 6261 6262 struct mlx5_ifc_destroy_sq_in_bits { 6263 u8 opcode[0x10]; 6264 u8 uid[0x10]; 6265 6266 u8 reserved_at_20[0x10]; 6267 u8 op_mod[0x10]; 6268 6269 u8 reserved_at_40[0x8]; 6270 u8 sqn[0x18]; 6271 6272 u8 reserved_at_60[0x20]; 6273 }; 6274 6275 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6276 u8 status[0x8]; 6277 u8 reserved_at_8[0x18]; 6278 6279 u8 syndrome[0x20]; 6280 6281 u8 reserved_at_40[0x1c0]; 6282 }; 6283 6284 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6285 u8 opcode[0x10]; 6286 u8 reserved_at_10[0x10]; 6287 6288 u8 reserved_at_20[0x10]; 6289 u8 op_mod[0x10]; 6290 6291 u8 scheduling_hierarchy[0x8]; 6292 u8 reserved_at_48[0x18]; 6293 6294 u8 scheduling_element_id[0x20]; 6295 6296 u8 reserved_at_80[0x180]; 6297 }; 6298 6299 struct mlx5_ifc_destroy_rqt_out_bits { 6300 u8 status[0x8]; 6301 u8 reserved_at_8[0x18]; 6302 6303 u8 syndrome[0x20]; 6304 6305 u8 reserved_at_40[0x40]; 6306 }; 6307 6308 struct mlx5_ifc_destroy_rqt_in_bits { 6309 u8 opcode[0x10]; 6310 u8 uid[0x10]; 6311 6312 u8 reserved_at_20[0x10]; 6313 u8 op_mod[0x10]; 6314 6315 u8 reserved_at_40[0x8]; 6316 u8 rqtn[0x18]; 6317 6318 u8 reserved_at_60[0x20]; 6319 }; 6320 6321 struct mlx5_ifc_destroy_rq_out_bits { 6322 u8 status[0x8]; 6323 u8 reserved_at_8[0x18]; 6324 6325 u8 syndrome[0x20]; 6326 6327 u8 reserved_at_40[0x40]; 6328 }; 6329 6330 struct mlx5_ifc_destroy_rq_in_bits { 6331 u8 opcode[0x10]; 6332 u8 uid[0x10]; 6333 6334 u8 reserved_at_20[0x10]; 6335 u8 op_mod[0x10]; 6336 6337 u8 reserved_at_40[0x8]; 6338 u8 rqn[0x18]; 6339 6340 u8 reserved_at_60[0x20]; 6341 }; 6342 6343 struct mlx5_ifc_set_delay_drop_params_in_bits { 6344 u8 opcode[0x10]; 6345 u8 reserved_at_10[0x10]; 6346 6347 u8 reserved_at_20[0x10]; 6348 u8 op_mod[0x10]; 6349 6350 u8 reserved_at_40[0x20]; 6351 6352 u8 reserved_at_60[0x10]; 6353 u8 delay_drop_timeout[0x10]; 6354 }; 6355 6356 struct mlx5_ifc_set_delay_drop_params_out_bits { 6357 u8 status[0x8]; 6358 u8 reserved_at_8[0x18]; 6359 6360 u8 syndrome[0x20]; 6361 6362 u8 reserved_at_40[0x40]; 6363 }; 6364 6365 struct mlx5_ifc_destroy_rmp_out_bits { 6366 u8 status[0x8]; 6367 u8 reserved_at_8[0x18]; 6368 6369 u8 syndrome[0x20]; 6370 6371 u8 reserved_at_40[0x40]; 6372 }; 6373 6374 struct mlx5_ifc_destroy_rmp_in_bits { 6375 u8 opcode[0x10]; 6376 u8 uid[0x10]; 6377 6378 u8 reserved_at_20[0x10]; 6379 u8 op_mod[0x10]; 6380 6381 u8 reserved_at_40[0x8]; 6382 u8 rmpn[0x18]; 6383 6384 u8 reserved_at_60[0x20]; 6385 }; 6386 6387 struct mlx5_ifc_destroy_qp_out_bits { 6388 u8 status[0x8]; 6389 u8 reserved_at_8[0x18]; 6390 6391 u8 syndrome[0x20]; 6392 6393 u8 reserved_at_40[0x40]; 6394 }; 6395 6396 struct mlx5_ifc_destroy_qp_in_bits { 6397 u8 opcode[0x10]; 6398 u8 uid[0x10]; 6399 6400 u8 reserved_at_20[0x10]; 6401 u8 op_mod[0x10]; 6402 6403 u8 reserved_at_40[0x8]; 6404 u8 qpn[0x18]; 6405 6406 u8 reserved_at_60[0x20]; 6407 }; 6408 6409 struct mlx5_ifc_destroy_psv_out_bits { 6410 u8 status[0x8]; 6411 u8 reserved_at_8[0x18]; 6412 6413 u8 syndrome[0x20]; 6414 6415 u8 reserved_at_40[0x40]; 6416 }; 6417 6418 struct mlx5_ifc_destroy_psv_in_bits { 6419 u8 opcode[0x10]; 6420 u8 reserved_at_10[0x10]; 6421 6422 u8 reserved_at_20[0x10]; 6423 u8 op_mod[0x10]; 6424 6425 u8 reserved_at_40[0x8]; 6426 u8 psvn[0x18]; 6427 6428 u8 reserved_at_60[0x20]; 6429 }; 6430 6431 struct mlx5_ifc_destroy_mkey_out_bits { 6432 u8 status[0x8]; 6433 u8 reserved_at_8[0x18]; 6434 6435 u8 syndrome[0x20]; 6436 6437 u8 reserved_at_40[0x40]; 6438 }; 6439 6440 struct mlx5_ifc_destroy_mkey_in_bits { 6441 u8 opcode[0x10]; 6442 u8 reserved_at_10[0x10]; 6443 6444 u8 reserved_at_20[0x10]; 6445 u8 op_mod[0x10]; 6446 6447 u8 reserved_at_40[0x8]; 6448 u8 mkey_index[0x18]; 6449 6450 u8 reserved_at_60[0x20]; 6451 }; 6452 6453 struct mlx5_ifc_destroy_flow_table_out_bits { 6454 u8 status[0x8]; 6455 u8 reserved_at_8[0x18]; 6456 6457 u8 syndrome[0x20]; 6458 6459 u8 reserved_at_40[0x40]; 6460 }; 6461 6462 struct mlx5_ifc_destroy_flow_table_in_bits { 6463 u8 opcode[0x10]; 6464 u8 reserved_at_10[0x10]; 6465 6466 u8 reserved_at_20[0x10]; 6467 u8 op_mod[0x10]; 6468 6469 u8 other_vport[0x1]; 6470 u8 reserved_at_41[0xf]; 6471 u8 vport_number[0x10]; 6472 6473 u8 reserved_at_60[0x20]; 6474 6475 u8 table_type[0x8]; 6476 u8 reserved_at_88[0x18]; 6477 6478 u8 reserved_at_a0[0x8]; 6479 u8 table_id[0x18]; 6480 6481 u8 reserved_at_c0[0x140]; 6482 }; 6483 6484 struct mlx5_ifc_destroy_flow_group_out_bits { 6485 u8 status[0x8]; 6486 u8 reserved_at_8[0x18]; 6487 6488 u8 syndrome[0x20]; 6489 6490 u8 reserved_at_40[0x40]; 6491 }; 6492 6493 struct mlx5_ifc_destroy_flow_group_in_bits { 6494 u8 opcode[0x10]; 6495 u8 reserved_at_10[0x10]; 6496 6497 u8 reserved_at_20[0x10]; 6498 u8 op_mod[0x10]; 6499 6500 u8 other_vport[0x1]; 6501 u8 reserved_at_41[0xf]; 6502 u8 vport_number[0x10]; 6503 6504 u8 reserved_at_60[0x20]; 6505 6506 u8 table_type[0x8]; 6507 u8 reserved_at_88[0x18]; 6508 6509 u8 reserved_at_a0[0x8]; 6510 u8 table_id[0x18]; 6511 6512 u8 group_id[0x20]; 6513 6514 u8 reserved_at_e0[0x120]; 6515 }; 6516 6517 struct mlx5_ifc_destroy_eq_out_bits { 6518 u8 status[0x8]; 6519 u8 reserved_at_8[0x18]; 6520 6521 u8 syndrome[0x20]; 6522 6523 u8 reserved_at_40[0x40]; 6524 }; 6525 6526 struct mlx5_ifc_destroy_eq_in_bits { 6527 u8 opcode[0x10]; 6528 u8 reserved_at_10[0x10]; 6529 6530 u8 reserved_at_20[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 reserved_at_40[0x18]; 6534 u8 eq_number[0x8]; 6535 6536 u8 reserved_at_60[0x20]; 6537 }; 6538 6539 struct mlx5_ifc_destroy_dct_out_bits { 6540 u8 status[0x8]; 6541 u8 reserved_at_8[0x18]; 6542 6543 u8 syndrome[0x20]; 6544 6545 u8 reserved_at_40[0x40]; 6546 }; 6547 6548 struct mlx5_ifc_destroy_dct_in_bits { 6549 u8 opcode[0x10]; 6550 u8 uid[0x10]; 6551 6552 u8 reserved_at_20[0x10]; 6553 u8 op_mod[0x10]; 6554 6555 u8 reserved_at_40[0x8]; 6556 u8 dctn[0x18]; 6557 6558 u8 reserved_at_60[0x20]; 6559 }; 6560 6561 struct mlx5_ifc_destroy_cq_out_bits { 6562 u8 status[0x8]; 6563 u8 reserved_at_8[0x18]; 6564 6565 u8 syndrome[0x20]; 6566 6567 u8 reserved_at_40[0x40]; 6568 }; 6569 6570 struct mlx5_ifc_destroy_cq_in_bits { 6571 u8 opcode[0x10]; 6572 u8 uid[0x10]; 6573 6574 u8 reserved_at_20[0x10]; 6575 u8 op_mod[0x10]; 6576 6577 u8 reserved_at_40[0x8]; 6578 u8 cqn[0x18]; 6579 6580 u8 reserved_at_60[0x20]; 6581 }; 6582 6583 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6584 u8 status[0x8]; 6585 u8 reserved_at_8[0x18]; 6586 6587 u8 syndrome[0x20]; 6588 6589 u8 reserved_at_40[0x40]; 6590 }; 6591 6592 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6593 u8 opcode[0x10]; 6594 u8 reserved_at_10[0x10]; 6595 6596 u8 reserved_at_20[0x10]; 6597 u8 op_mod[0x10]; 6598 6599 u8 reserved_at_40[0x20]; 6600 6601 u8 reserved_at_60[0x10]; 6602 u8 vxlan_udp_port[0x10]; 6603 }; 6604 6605 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6606 u8 status[0x8]; 6607 u8 reserved_at_8[0x18]; 6608 6609 u8 syndrome[0x20]; 6610 6611 u8 reserved_at_40[0x40]; 6612 }; 6613 6614 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6615 u8 opcode[0x10]; 6616 u8 reserved_at_10[0x10]; 6617 6618 u8 reserved_at_20[0x10]; 6619 u8 op_mod[0x10]; 6620 6621 u8 reserved_at_40[0x60]; 6622 6623 u8 reserved_at_a0[0x8]; 6624 u8 table_index[0x18]; 6625 6626 u8 reserved_at_c0[0x140]; 6627 }; 6628 6629 struct mlx5_ifc_delete_fte_out_bits { 6630 u8 status[0x8]; 6631 u8 reserved_at_8[0x18]; 6632 6633 u8 syndrome[0x20]; 6634 6635 u8 reserved_at_40[0x40]; 6636 }; 6637 6638 struct mlx5_ifc_delete_fte_in_bits { 6639 u8 opcode[0x10]; 6640 u8 reserved_at_10[0x10]; 6641 6642 u8 reserved_at_20[0x10]; 6643 u8 op_mod[0x10]; 6644 6645 u8 other_vport[0x1]; 6646 u8 reserved_at_41[0xf]; 6647 u8 vport_number[0x10]; 6648 6649 u8 reserved_at_60[0x20]; 6650 6651 u8 table_type[0x8]; 6652 u8 reserved_at_88[0x18]; 6653 6654 u8 reserved_at_a0[0x8]; 6655 u8 table_id[0x18]; 6656 6657 u8 reserved_at_c0[0x40]; 6658 6659 u8 flow_index[0x20]; 6660 6661 u8 reserved_at_120[0xe0]; 6662 }; 6663 6664 struct mlx5_ifc_dealloc_xrcd_out_bits { 6665 u8 status[0x8]; 6666 u8 reserved_at_8[0x18]; 6667 6668 u8 syndrome[0x20]; 6669 6670 u8 reserved_at_40[0x40]; 6671 }; 6672 6673 struct mlx5_ifc_dealloc_xrcd_in_bits { 6674 u8 opcode[0x10]; 6675 u8 uid[0x10]; 6676 6677 u8 reserved_at_20[0x10]; 6678 u8 op_mod[0x10]; 6679 6680 u8 reserved_at_40[0x8]; 6681 u8 xrcd[0x18]; 6682 6683 u8 reserved_at_60[0x20]; 6684 }; 6685 6686 struct mlx5_ifc_dealloc_uar_out_bits { 6687 u8 status[0x8]; 6688 u8 reserved_at_8[0x18]; 6689 6690 u8 syndrome[0x20]; 6691 6692 u8 reserved_at_40[0x40]; 6693 }; 6694 6695 struct mlx5_ifc_dealloc_uar_in_bits { 6696 u8 opcode[0x10]; 6697 u8 reserved_at_10[0x10]; 6698 6699 u8 reserved_at_20[0x10]; 6700 u8 op_mod[0x10]; 6701 6702 u8 reserved_at_40[0x8]; 6703 u8 uar[0x18]; 6704 6705 u8 reserved_at_60[0x20]; 6706 }; 6707 6708 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6709 u8 status[0x8]; 6710 u8 reserved_at_8[0x18]; 6711 6712 u8 syndrome[0x20]; 6713 6714 u8 reserved_at_40[0x40]; 6715 }; 6716 6717 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6718 u8 opcode[0x10]; 6719 u8 uid[0x10]; 6720 6721 u8 reserved_at_20[0x10]; 6722 u8 op_mod[0x10]; 6723 6724 u8 reserved_at_40[0x8]; 6725 u8 transport_domain[0x18]; 6726 6727 u8 reserved_at_60[0x20]; 6728 }; 6729 6730 struct mlx5_ifc_dealloc_q_counter_out_bits { 6731 u8 status[0x8]; 6732 u8 reserved_at_8[0x18]; 6733 6734 u8 syndrome[0x20]; 6735 6736 u8 reserved_at_40[0x40]; 6737 }; 6738 6739 struct mlx5_ifc_dealloc_q_counter_in_bits { 6740 u8 opcode[0x10]; 6741 u8 reserved_at_10[0x10]; 6742 6743 u8 reserved_at_20[0x10]; 6744 u8 op_mod[0x10]; 6745 6746 u8 reserved_at_40[0x18]; 6747 u8 counter_set_id[0x8]; 6748 6749 u8 reserved_at_60[0x20]; 6750 }; 6751 6752 struct mlx5_ifc_dealloc_pd_out_bits { 6753 u8 status[0x8]; 6754 u8 reserved_at_8[0x18]; 6755 6756 u8 syndrome[0x20]; 6757 6758 u8 reserved_at_40[0x40]; 6759 }; 6760 6761 struct mlx5_ifc_dealloc_pd_in_bits { 6762 u8 opcode[0x10]; 6763 u8 uid[0x10]; 6764 6765 u8 reserved_at_20[0x10]; 6766 u8 op_mod[0x10]; 6767 6768 u8 reserved_at_40[0x8]; 6769 u8 pd[0x18]; 6770 6771 u8 reserved_at_60[0x20]; 6772 }; 6773 6774 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6775 u8 status[0x8]; 6776 u8 reserved_at_8[0x18]; 6777 6778 u8 syndrome[0x20]; 6779 6780 u8 reserved_at_40[0x40]; 6781 }; 6782 6783 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6784 u8 opcode[0x10]; 6785 u8 reserved_at_10[0x10]; 6786 6787 u8 reserved_at_20[0x10]; 6788 u8 op_mod[0x10]; 6789 6790 u8 flow_counter_id[0x20]; 6791 6792 u8 reserved_at_60[0x20]; 6793 }; 6794 6795 struct mlx5_ifc_create_xrq_out_bits { 6796 u8 status[0x8]; 6797 u8 reserved_at_8[0x18]; 6798 6799 u8 syndrome[0x20]; 6800 6801 u8 reserved_at_40[0x8]; 6802 u8 xrqn[0x18]; 6803 6804 u8 reserved_at_60[0x20]; 6805 }; 6806 6807 struct mlx5_ifc_create_xrq_in_bits { 6808 u8 opcode[0x10]; 6809 u8 uid[0x10]; 6810 6811 u8 reserved_at_20[0x10]; 6812 u8 op_mod[0x10]; 6813 6814 u8 reserved_at_40[0x40]; 6815 6816 struct mlx5_ifc_xrqc_bits xrq_context; 6817 }; 6818 6819 struct mlx5_ifc_create_xrc_srq_out_bits { 6820 u8 status[0x8]; 6821 u8 reserved_at_8[0x18]; 6822 6823 u8 syndrome[0x20]; 6824 6825 u8 reserved_at_40[0x8]; 6826 u8 xrc_srqn[0x18]; 6827 6828 u8 reserved_at_60[0x20]; 6829 }; 6830 6831 struct mlx5_ifc_create_xrc_srq_in_bits { 6832 u8 opcode[0x10]; 6833 u8 uid[0x10]; 6834 6835 u8 reserved_at_20[0x10]; 6836 u8 op_mod[0x10]; 6837 6838 u8 reserved_at_40[0x40]; 6839 6840 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6841 6842 u8 reserved_at_280[0x60]; 6843 6844 u8 xrc_srq_umem_valid[0x1]; 6845 u8 reserved_at_2e1[0x1f]; 6846 6847 u8 reserved_at_300[0x580]; 6848 6849 u8 pas[0][0x40]; 6850 }; 6851 6852 struct mlx5_ifc_create_tis_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_at_8[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_at_40[0x8]; 6859 u8 tisn[0x18]; 6860 6861 u8 reserved_at_60[0x20]; 6862 }; 6863 6864 struct mlx5_ifc_create_tis_in_bits { 6865 u8 opcode[0x10]; 6866 u8 uid[0x10]; 6867 6868 u8 reserved_at_20[0x10]; 6869 u8 op_mod[0x10]; 6870 6871 u8 reserved_at_40[0xc0]; 6872 6873 struct mlx5_ifc_tisc_bits ctx; 6874 }; 6875 6876 struct mlx5_ifc_create_tir_out_bits { 6877 u8 status[0x8]; 6878 u8 reserved_at_8[0x18]; 6879 6880 u8 syndrome[0x20]; 6881 6882 u8 reserved_at_40[0x8]; 6883 u8 tirn[0x18]; 6884 6885 u8 reserved_at_60[0x20]; 6886 }; 6887 6888 struct mlx5_ifc_create_tir_in_bits { 6889 u8 opcode[0x10]; 6890 u8 uid[0x10]; 6891 6892 u8 reserved_at_20[0x10]; 6893 u8 op_mod[0x10]; 6894 6895 u8 reserved_at_40[0xc0]; 6896 6897 struct mlx5_ifc_tirc_bits ctx; 6898 }; 6899 6900 struct mlx5_ifc_create_srq_out_bits { 6901 u8 status[0x8]; 6902 u8 reserved_at_8[0x18]; 6903 6904 u8 syndrome[0x20]; 6905 6906 u8 reserved_at_40[0x8]; 6907 u8 srqn[0x18]; 6908 6909 u8 reserved_at_60[0x20]; 6910 }; 6911 6912 struct mlx5_ifc_create_srq_in_bits { 6913 u8 opcode[0x10]; 6914 u8 uid[0x10]; 6915 6916 u8 reserved_at_20[0x10]; 6917 u8 op_mod[0x10]; 6918 6919 u8 reserved_at_40[0x40]; 6920 6921 struct mlx5_ifc_srqc_bits srq_context_entry; 6922 6923 u8 reserved_at_280[0x600]; 6924 6925 u8 pas[0][0x40]; 6926 }; 6927 6928 struct mlx5_ifc_create_sq_out_bits { 6929 u8 status[0x8]; 6930 u8 reserved_at_8[0x18]; 6931 6932 u8 syndrome[0x20]; 6933 6934 u8 reserved_at_40[0x8]; 6935 u8 sqn[0x18]; 6936 6937 u8 reserved_at_60[0x20]; 6938 }; 6939 6940 struct mlx5_ifc_create_sq_in_bits { 6941 u8 opcode[0x10]; 6942 u8 uid[0x10]; 6943 6944 u8 reserved_at_20[0x10]; 6945 u8 op_mod[0x10]; 6946 6947 u8 reserved_at_40[0xc0]; 6948 6949 struct mlx5_ifc_sqc_bits ctx; 6950 }; 6951 6952 struct mlx5_ifc_create_scheduling_element_out_bits { 6953 u8 status[0x8]; 6954 u8 reserved_at_8[0x18]; 6955 6956 u8 syndrome[0x20]; 6957 6958 u8 reserved_at_40[0x40]; 6959 6960 u8 scheduling_element_id[0x20]; 6961 6962 u8 reserved_at_a0[0x160]; 6963 }; 6964 6965 struct mlx5_ifc_create_scheduling_element_in_bits { 6966 u8 opcode[0x10]; 6967 u8 reserved_at_10[0x10]; 6968 6969 u8 reserved_at_20[0x10]; 6970 u8 op_mod[0x10]; 6971 6972 u8 scheduling_hierarchy[0x8]; 6973 u8 reserved_at_48[0x18]; 6974 6975 u8 reserved_at_60[0xa0]; 6976 6977 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6978 6979 u8 reserved_at_300[0x100]; 6980 }; 6981 6982 struct mlx5_ifc_create_rqt_out_bits { 6983 u8 status[0x8]; 6984 u8 reserved_at_8[0x18]; 6985 6986 u8 syndrome[0x20]; 6987 6988 u8 reserved_at_40[0x8]; 6989 u8 rqtn[0x18]; 6990 6991 u8 reserved_at_60[0x20]; 6992 }; 6993 6994 struct mlx5_ifc_create_rqt_in_bits { 6995 u8 opcode[0x10]; 6996 u8 uid[0x10]; 6997 6998 u8 reserved_at_20[0x10]; 6999 u8 op_mod[0x10]; 7000 7001 u8 reserved_at_40[0xc0]; 7002 7003 struct mlx5_ifc_rqtc_bits rqt_context; 7004 }; 7005 7006 struct mlx5_ifc_create_rq_out_bits { 7007 u8 status[0x8]; 7008 u8 reserved_at_8[0x18]; 7009 7010 u8 syndrome[0x20]; 7011 7012 u8 reserved_at_40[0x8]; 7013 u8 rqn[0x18]; 7014 7015 u8 reserved_at_60[0x20]; 7016 }; 7017 7018 struct mlx5_ifc_create_rq_in_bits { 7019 u8 opcode[0x10]; 7020 u8 uid[0x10]; 7021 7022 u8 reserved_at_20[0x10]; 7023 u8 op_mod[0x10]; 7024 7025 u8 reserved_at_40[0xc0]; 7026 7027 struct mlx5_ifc_rqc_bits ctx; 7028 }; 7029 7030 struct mlx5_ifc_create_rmp_out_bits { 7031 u8 status[0x8]; 7032 u8 reserved_at_8[0x18]; 7033 7034 u8 syndrome[0x20]; 7035 7036 u8 reserved_at_40[0x8]; 7037 u8 rmpn[0x18]; 7038 7039 u8 reserved_at_60[0x20]; 7040 }; 7041 7042 struct mlx5_ifc_create_rmp_in_bits { 7043 u8 opcode[0x10]; 7044 u8 uid[0x10]; 7045 7046 u8 reserved_at_20[0x10]; 7047 u8 op_mod[0x10]; 7048 7049 u8 reserved_at_40[0xc0]; 7050 7051 struct mlx5_ifc_rmpc_bits ctx; 7052 }; 7053 7054 struct mlx5_ifc_create_qp_out_bits { 7055 u8 status[0x8]; 7056 u8 reserved_at_8[0x18]; 7057 7058 u8 syndrome[0x20]; 7059 7060 u8 reserved_at_40[0x8]; 7061 u8 qpn[0x18]; 7062 7063 u8 reserved_at_60[0x20]; 7064 }; 7065 7066 struct mlx5_ifc_create_qp_in_bits { 7067 u8 opcode[0x10]; 7068 u8 uid[0x10]; 7069 7070 u8 reserved_at_20[0x10]; 7071 u8 op_mod[0x10]; 7072 7073 u8 reserved_at_40[0x40]; 7074 7075 u8 opt_param_mask[0x20]; 7076 7077 u8 reserved_at_a0[0x20]; 7078 7079 struct mlx5_ifc_qpc_bits qpc; 7080 7081 u8 reserved_at_800[0x60]; 7082 7083 u8 wq_umem_valid[0x1]; 7084 u8 reserved_at_861[0x1f]; 7085 7086 u8 pas[0][0x40]; 7087 }; 7088 7089 struct mlx5_ifc_create_psv_out_bits { 7090 u8 status[0x8]; 7091 u8 reserved_at_8[0x18]; 7092 7093 u8 syndrome[0x20]; 7094 7095 u8 reserved_at_40[0x40]; 7096 7097 u8 reserved_at_80[0x8]; 7098 u8 psv0_index[0x18]; 7099 7100 u8 reserved_at_a0[0x8]; 7101 u8 psv1_index[0x18]; 7102 7103 u8 reserved_at_c0[0x8]; 7104 u8 psv2_index[0x18]; 7105 7106 u8 reserved_at_e0[0x8]; 7107 u8 psv3_index[0x18]; 7108 }; 7109 7110 struct mlx5_ifc_create_psv_in_bits { 7111 u8 opcode[0x10]; 7112 u8 reserved_at_10[0x10]; 7113 7114 u8 reserved_at_20[0x10]; 7115 u8 op_mod[0x10]; 7116 7117 u8 num_psv[0x4]; 7118 u8 reserved_at_44[0x4]; 7119 u8 pd[0x18]; 7120 7121 u8 reserved_at_60[0x20]; 7122 }; 7123 7124 struct mlx5_ifc_create_mkey_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x8]; 7131 u8 mkey_index[0x18]; 7132 7133 u8 reserved_at_60[0x20]; 7134 }; 7135 7136 struct mlx5_ifc_create_mkey_in_bits { 7137 u8 opcode[0x10]; 7138 u8 reserved_at_10[0x10]; 7139 7140 u8 reserved_at_20[0x10]; 7141 u8 op_mod[0x10]; 7142 7143 u8 reserved_at_40[0x20]; 7144 7145 u8 pg_access[0x1]; 7146 u8 mkey_umem_valid[0x1]; 7147 u8 reserved_at_62[0x1e]; 7148 7149 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7150 7151 u8 reserved_at_280[0x80]; 7152 7153 u8 translations_octword_actual_size[0x20]; 7154 7155 u8 reserved_at_320[0x560]; 7156 7157 u8 klm_pas_mtt[0][0x20]; 7158 }; 7159 7160 struct mlx5_ifc_create_flow_table_out_bits { 7161 u8 status[0x8]; 7162 u8 reserved_at_8[0x18]; 7163 7164 u8 syndrome[0x20]; 7165 7166 u8 reserved_at_40[0x8]; 7167 u8 table_id[0x18]; 7168 7169 u8 reserved_at_60[0x20]; 7170 }; 7171 7172 struct mlx5_ifc_flow_table_context_bits { 7173 u8 reformat_en[0x1]; 7174 u8 decap_en[0x1]; 7175 u8 reserved_at_2[0x2]; 7176 u8 table_miss_action[0x4]; 7177 u8 level[0x8]; 7178 u8 reserved_at_10[0x8]; 7179 u8 log_size[0x8]; 7180 7181 u8 reserved_at_20[0x8]; 7182 u8 table_miss_id[0x18]; 7183 7184 u8 reserved_at_40[0x8]; 7185 u8 lag_master_next_table_id[0x18]; 7186 7187 u8 reserved_at_60[0xe0]; 7188 }; 7189 7190 struct mlx5_ifc_create_flow_table_in_bits { 7191 u8 opcode[0x10]; 7192 u8 reserved_at_10[0x10]; 7193 7194 u8 reserved_at_20[0x10]; 7195 u8 op_mod[0x10]; 7196 7197 u8 other_vport[0x1]; 7198 u8 reserved_at_41[0xf]; 7199 u8 vport_number[0x10]; 7200 7201 u8 reserved_at_60[0x20]; 7202 7203 u8 table_type[0x8]; 7204 u8 reserved_at_88[0x18]; 7205 7206 u8 reserved_at_a0[0x20]; 7207 7208 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7209 }; 7210 7211 struct mlx5_ifc_create_flow_group_out_bits { 7212 u8 status[0x8]; 7213 u8 reserved_at_8[0x18]; 7214 7215 u8 syndrome[0x20]; 7216 7217 u8 reserved_at_40[0x8]; 7218 u8 group_id[0x18]; 7219 7220 u8 reserved_at_60[0x20]; 7221 }; 7222 7223 enum { 7224 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7225 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7226 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7227 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7228 }; 7229 7230 struct mlx5_ifc_create_flow_group_in_bits { 7231 u8 opcode[0x10]; 7232 u8 reserved_at_10[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 other_vport[0x1]; 7238 u8 reserved_at_41[0xf]; 7239 u8 vport_number[0x10]; 7240 7241 u8 reserved_at_60[0x20]; 7242 7243 u8 table_type[0x8]; 7244 u8 reserved_at_88[0x18]; 7245 7246 u8 reserved_at_a0[0x8]; 7247 u8 table_id[0x18]; 7248 7249 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7250 7251 u8 reserved_at_c1[0x1f]; 7252 7253 u8 start_flow_index[0x20]; 7254 7255 u8 reserved_at_100[0x20]; 7256 7257 u8 end_flow_index[0x20]; 7258 7259 u8 reserved_at_140[0xa0]; 7260 7261 u8 reserved_at_1e0[0x18]; 7262 u8 match_criteria_enable[0x8]; 7263 7264 struct mlx5_ifc_fte_match_param_bits match_criteria; 7265 7266 u8 reserved_at_1200[0xe00]; 7267 }; 7268 7269 struct mlx5_ifc_create_eq_out_bits { 7270 u8 status[0x8]; 7271 u8 reserved_at_8[0x18]; 7272 7273 u8 syndrome[0x20]; 7274 7275 u8 reserved_at_40[0x18]; 7276 u8 eq_number[0x8]; 7277 7278 u8 reserved_at_60[0x20]; 7279 }; 7280 7281 struct mlx5_ifc_create_eq_in_bits { 7282 u8 opcode[0x10]; 7283 u8 reserved_at_10[0x10]; 7284 7285 u8 reserved_at_20[0x10]; 7286 u8 op_mod[0x10]; 7287 7288 u8 reserved_at_40[0x40]; 7289 7290 struct mlx5_ifc_eqc_bits eq_context_entry; 7291 7292 u8 reserved_at_280[0x40]; 7293 7294 u8 event_bitmask[0x40]; 7295 7296 u8 reserved_at_300[0x580]; 7297 7298 u8 pas[0][0x40]; 7299 }; 7300 7301 struct mlx5_ifc_create_dct_out_bits { 7302 u8 status[0x8]; 7303 u8 reserved_at_8[0x18]; 7304 7305 u8 syndrome[0x20]; 7306 7307 u8 reserved_at_40[0x8]; 7308 u8 dctn[0x18]; 7309 7310 u8 reserved_at_60[0x20]; 7311 }; 7312 7313 struct mlx5_ifc_create_dct_in_bits { 7314 u8 opcode[0x10]; 7315 u8 uid[0x10]; 7316 7317 u8 reserved_at_20[0x10]; 7318 u8 op_mod[0x10]; 7319 7320 u8 reserved_at_40[0x40]; 7321 7322 struct mlx5_ifc_dctc_bits dct_context_entry; 7323 7324 u8 reserved_at_280[0x180]; 7325 }; 7326 7327 struct mlx5_ifc_create_cq_out_bits { 7328 u8 status[0x8]; 7329 u8 reserved_at_8[0x18]; 7330 7331 u8 syndrome[0x20]; 7332 7333 u8 reserved_at_40[0x8]; 7334 u8 cqn[0x18]; 7335 7336 u8 reserved_at_60[0x20]; 7337 }; 7338 7339 struct mlx5_ifc_create_cq_in_bits { 7340 u8 opcode[0x10]; 7341 u8 uid[0x10]; 7342 7343 u8 reserved_at_20[0x10]; 7344 u8 op_mod[0x10]; 7345 7346 u8 reserved_at_40[0x40]; 7347 7348 struct mlx5_ifc_cqc_bits cq_context; 7349 7350 u8 reserved_at_280[0x60]; 7351 7352 u8 cq_umem_valid[0x1]; 7353 u8 reserved_at_2e1[0x59f]; 7354 7355 u8 pas[0][0x40]; 7356 }; 7357 7358 struct mlx5_ifc_config_int_moderation_out_bits { 7359 u8 status[0x8]; 7360 u8 reserved_at_8[0x18]; 7361 7362 u8 syndrome[0x20]; 7363 7364 u8 reserved_at_40[0x4]; 7365 u8 min_delay[0xc]; 7366 u8 int_vector[0x10]; 7367 7368 u8 reserved_at_60[0x20]; 7369 }; 7370 7371 enum { 7372 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7373 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7374 }; 7375 7376 struct mlx5_ifc_config_int_moderation_in_bits { 7377 u8 opcode[0x10]; 7378 u8 reserved_at_10[0x10]; 7379 7380 u8 reserved_at_20[0x10]; 7381 u8 op_mod[0x10]; 7382 7383 u8 reserved_at_40[0x4]; 7384 u8 min_delay[0xc]; 7385 u8 int_vector[0x10]; 7386 7387 u8 reserved_at_60[0x20]; 7388 }; 7389 7390 struct mlx5_ifc_attach_to_mcg_out_bits { 7391 u8 status[0x8]; 7392 u8 reserved_at_8[0x18]; 7393 7394 u8 syndrome[0x20]; 7395 7396 u8 reserved_at_40[0x40]; 7397 }; 7398 7399 struct mlx5_ifc_attach_to_mcg_in_bits { 7400 u8 opcode[0x10]; 7401 u8 uid[0x10]; 7402 7403 u8 reserved_at_20[0x10]; 7404 u8 op_mod[0x10]; 7405 7406 u8 reserved_at_40[0x8]; 7407 u8 qpn[0x18]; 7408 7409 u8 reserved_at_60[0x20]; 7410 7411 u8 multicast_gid[16][0x8]; 7412 }; 7413 7414 struct mlx5_ifc_arm_xrq_out_bits { 7415 u8 status[0x8]; 7416 u8 reserved_at_8[0x18]; 7417 7418 u8 syndrome[0x20]; 7419 7420 u8 reserved_at_40[0x40]; 7421 }; 7422 7423 struct mlx5_ifc_arm_xrq_in_bits { 7424 u8 opcode[0x10]; 7425 u8 reserved_at_10[0x10]; 7426 7427 u8 reserved_at_20[0x10]; 7428 u8 op_mod[0x10]; 7429 7430 u8 reserved_at_40[0x8]; 7431 u8 xrqn[0x18]; 7432 7433 u8 reserved_at_60[0x10]; 7434 u8 lwm[0x10]; 7435 }; 7436 7437 struct mlx5_ifc_arm_xrc_srq_out_bits { 7438 u8 status[0x8]; 7439 u8 reserved_at_8[0x18]; 7440 7441 u8 syndrome[0x20]; 7442 7443 u8 reserved_at_40[0x40]; 7444 }; 7445 7446 enum { 7447 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7448 }; 7449 7450 struct mlx5_ifc_arm_xrc_srq_in_bits { 7451 u8 opcode[0x10]; 7452 u8 uid[0x10]; 7453 7454 u8 reserved_at_20[0x10]; 7455 u8 op_mod[0x10]; 7456 7457 u8 reserved_at_40[0x8]; 7458 u8 xrc_srqn[0x18]; 7459 7460 u8 reserved_at_60[0x10]; 7461 u8 lwm[0x10]; 7462 }; 7463 7464 struct mlx5_ifc_arm_rq_out_bits { 7465 u8 status[0x8]; 7466 u8 reserved_at_8[0x18]; 7467 7468 u8 syndrome[0x20]; 7469 7470 u8 reserved_at_40[0x40]; 7471 }; 7472 7473 enum { 7474 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7475 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7476 }; 7477 7478 struct mlx5_ifc_arm_rq_in_bits { 7479 u8 opcode[0x10]; 7480 u8 uid[0x10]; 7481 7482 u8 reserved_at_20[0x10]; 7483 u8 op_mod[0x10]; 7484 7485 u8 reserved_at_40[0x8]; 7486 u8 srq_number[0x18]; 7487 7488 u8 reserved_at_60[0x10]; 7489 u8 lwm[0x10]; 7490 }; 7491 7492 struct mlx5_ifc_arm_dct_out_bits { 7493 u8 status[0x8]; 7494 u8 reserved_at_8[0x18]; 7495 7496 u8 syndrome[0x20]; 7497 7498 u8 reserved_at_40[0x40]; 7499 }; 7500 7501 struct mlx5_ifc_arm_dct_in_bits { 7502 u8 opcode[0x10]; 7503 u8 reserved_at_10[0x10]; 7504 7505 u8 reserved_at_20[0x10]; 7506 u8 op_mod[0x10]; 7507 7508 u8 reserved_at_40[0x8]; 7509 u8 dct_number[0x18]; 7510 7511 u8 reserved_at_60[0x20]; 7512 }; 7513 7514 struct mlx5_ifc_alloc_xrcd_out_bits { 7515 u8 status[0x8]; 7516 u8 reserved_at_8[0x18]; 7517 7518 u8 syndrome[0x20]; 7519 7520 u8 reserved_at_40[0x8]; 7521 u8 xrcd[0x18]; 7522 7523 u8 reserved_at_60[0x20]; 7524 }; 7525 7526 struct mlx5_ifc_alloc_xrcd_in_bits { 7527 u8 opcode[0x10]; 7528 u8 uid[0x10]; 7529 7530 u8 reserved_at_20[0x10]; 7531 u8 op_mod[0x10]; 7532 7533 u8 reserved_at_40[0x40]; 7534 }; 7535 7536 struct mlx5_ifc_alloc_uar_out_bits { 7537 u8 status[0x8]; 7538 u8 reserved_at_8[0x18]; 7539 7540 u8 syndrome[0x20]; 7541 7542 u8 reserved_at_40[0x8]; 7543 u8 uar[0x18]; 7544 7545 u8 reserved_at_60[0x20]; 7546 }; 7547 7548 struct mlx5_ifc_alloc_uar_in_bits { 7549 u8 opcode[0x10]; 7550 u8 reserved_at_10[0x10]; 7551 7552 u8 reserved_at_20[0x10]; 7553 u8 op_mod[0x10]; 7554 7555 u8 reserved_at_40[0x40]; 7556 }; 7557 7558 struct mlx5_ifc_alloc_transport_domain_out_bits { 7559 u8 status[0x8]; 7560 u8 reserved_at_8[0x18]; 7561 7562 u8 syndrome[0x20]; 7563 7564 u8 reserved_at_40[0x8]; 7565 u8 transport_domain[0x18]; 7566 7567 u8 reserved_at_60[0x20]; 7568 }; 7569 7570 struct mlx5_ifc_alloc_transport_domain_in_bits { 7571 u8 opcode[0x10]; 7572 u8 uid[0x10]; 7573 7574 u8 reserved_at_20[0x10]; 7575 u8 op_mod[0x10]; 7576 7577 u8 reserved_at_40[0x40]; 7578 }; 7579 7580 struct mlx5_ifc_alloc_q_counter_out_bits { 7581 u8 status[0x8]; 7582 u8 reserved_at_8[0x18]; 7583 7584 u8 syndrome[0x20]; 7585 7586 u8 reserved_at_40[0x18]; 7587 u8 counter_set_id[0x8]; 7588 7589 u8 reserved_at_60[0x20]; 7590 }; 7591 7592 struct mlx5_ifc_alloc_q_counter_in_bits { 7593 u8 opcode[0x10]; 7594 u8 uid[0x10]; 7595 7596 u8 reserved_at_20[0x10]; 7597 u8 op_mod[0x10]; 7598 7599 u8 reserved_at_40[0x40]; 7600 }; 7601 7602 struct mlx5_ifc_alloc_pd_out_bits { 7603 u8 status[0x8]; 7604 u8 reserved_at_8[0x18]; 7605 7606 u8 syndrome[0x20]; 7607 7608 u8 reserved_at_40[0x8]; 7609 u8 pd[0x18]; 7610 7611 u8 reserved_at_60[0x20]; 7612 }; 7613 7614 struct mlx5_ifc_alloc_pd_in_bits { 7615 u8 opcode[0x10]; 7616 u8 uid[0x10]; 7617 7618 u8 reserved_at_20[0x10]; 7619 u8 op_mod[0x10]; 7620 7621 u8 reserved_at_40[0x40]; 7622 }; 7623 7624 struct mlx5_ifc_alloc_flow_counter_out_bits { 7625 u8 status[0x8]; 7626 u8 reserved_at_8[0x18]; 7627 7628 u8 syndrome[0x20]; 7629 7630 u8 flow_counter_id[0x20]; 7631 7632 u8 reserved_at_60[0x20]; 7633 }; 7634 7635 struct mlx5_ifc_alloc_flow_counter_in_bits { 7636 u8 opcode[0x10]; 7637 u8 reserved_at_10[0x10]; 7638 7639 u8 reserved_at_20[0x10]; 7640 u8 op_mod[0x10]; 7641 7642 u8 reserved_at_40[0x40]; 7643 }; 7644 7645 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_at_8[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_at_40[0x40]; 7652 }; 7653 7654 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7655 u8 opcode[0x10]; 7656 u8 reserved_at_10[0x10]; 7657 7658 u8 reserved_at_20[0x10]; 7659 u8 op_mod[0x10]; 7660 7661 u8 reserved_at_40[0x20]; 7662 7663 u8 reserved_at_60[0x10]; 7664 u8 vxlan_udp_port[0x10]; 7665 }; 7666 7667 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7668 u8 status[0x8]; 7669 u8 reserved_at_8[0x18]; 7670 7671 u8 syndrome[0x20]; 7672 7673 u8 reserved_at_40[0x40]; 7674 }; 7675 7676 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7677 u8 opcode[0x10]; 7678 u8 reserved_at_10[0x10]; 7679 7680 u8 reserved_at_20[0x10]; 7681 u8 op_mod[0x10]; 7682 7683 u8 reserved_at_40[0x10]; 7684 u8 rate_limit_index[0x10]; 7685 7686 u8 reserved_at_60[0x20]; 7687 7688 u8 rate_limit[0x20]; 7689 7690 u8 burst_upper_bound[0x20]; 7691 7692 u8 reserved_at_c0[0x10]; 7693 u8 typical_packet_size[0x10]; 7694 7695 u8 reserved_at_e0[0x120]; 7696 }; 7697 7698 struct mlx5_ifc_access_register_out_bits { 7699 u8 status[0x8]; 7700 u8 reserved_at_8[0x18]; 7701 7702 u8 syndrome[0x20]; 7703 7704 u8 reserved_at_40[0x40]; 7705 7706 u8 register_data[0][0x20]; 7707 }; 7708 7709 enum { 7710 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7711 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7712 }; 7713 7714 struct mlx5_ifc_access_register_in_bits { 7715 u8 opcode[0x10]; 7716 u8 reserved_at_10[0x10]; 7717 7718 u8 reserved_at_20[0x10]; 7719 u8 op_mod[0x10]; 7720 7721 u8 reserved_at_40[0x10]; 7722 u8 register_id[0x10]; 7723 7724 u8 argument[0x20]; 7725 7726 u8 register_data[0][0x20]; 7727 }; 7728 7729 struct mlx5_ifc_sltp_reg_bits { 7730 u8 status[0x4]; 7731 u8 version[0x4]; 7732 u8 local_port[0x8]; 7733 u8 pnat[0x2]; 7734 u8 reserved_at_12[0x2]; 7735 u8 lane[0x4]; 7736 u8 reserved_at_18[0x8]; 7737 7738 u8 reserved_at_20[0x20]; 7739 7740 u8 reserved_at_40[0x7]; 7741 u8 polarity[0x1]; 7742 u8 ob_tap0[0x8]; 7743 u8 ob_tap1[0x8]; 7744 u8 ob_tap2[0x8]; 7745 7746 u8 reserved_at_60[0xc]; 7747 u8 ob_preemp_mode[0x4]; 7748 u8 ob_reg[0x8]; 7749 u8 ob_bias[0x8]; 7750 7751 u8 reserved_at_80[0x20]; 7752 }; 7753 7754 struct mlx5_ifc_slrg_reg_bits { 7755 u8 status[0x4]; 7756 u8 version[0x4]; 7757 u8 local_port[0x8]; 7758 u8 pnat[0x2]; 7759 u8 reserved_at_12[0x2]; 7760 u8 lane[0x4]; 7761 u8 reserved_at_18[0x8]; 7762 7763 u8 time_to_link_up[0x10]; 7764 u8 reserved_at_30[0xc]; 7765 u8 grade_lane_speed[0x4]; 7766 7767 u8 grade_version[0x8]; 7768 u8 grade[0x18]; 7769 7770 u8 reserved_at_60[0x4]; 7771 u8 height_grade_type[0x4]; 7772 u8 height_grade[0x18]; 7773 7774 u8 height_dz[0x10]; 7775 u8 height_dv[0x10]; 7776 7777 u8 reserved_at_a0[0x10]; 7778 u8 height_sigma[0x10]; 7779 7780 u8 reserved_at_c0[0x20]; 7781 7782 u8 reserved_at_e0[0x4]; 7783 u8 phase_grade_type[0x4]; 7784 u8 phase_grade[0x18]; 7785 7786 u8 reserved_at_100[0x8]; 7787 u8 phase_eo_pos[0x8]; 7788 u8 reserved_at_110[0x8]; 7789 u8 phase_eo_neg[0x8]; 7790 7791 u8 ffe_set_tested[0x10]; 7792 u8 test_errors_per_lane[0x10]; 7793 }; 7794 7795 struct mlx5_ifc_pvlc_reg_bits { 7796 u8 reserved_at_0[0x8]; 7797 u8 local_port[0x8]; 7798 u8 reserved_at_10[0x10]; 7799 7800 u8 reserved_at_20[0x1c]; 7801 u8 vl_hw_cap[0x4]; 7802 7803 u8 reserved_at_40[0x1c]; 7804 u8 vl_admin[0x4]; 7805 7806 u8 reserved_at_60[0x1c]; 7807 u8 vl_operational[0x4]; 7808 }; 7809 7810 struct mlx5_ifc_pude_reg_bits { 7811 u8 swid[0x8]; 7812 u8 local_port[0x8]; 7813 u8 reserved_at_10[0x4]; 7814 u8 admin_status[0x4]; 7815 u8 reserved_at_18[0x4]; 7816 u8 oper_status[0x4]; 7817 7818 u8 reserved_at_20[0x60]; 7819 }; 7820 7821 struct mlx5_ifc_ptys_reg_bits { 7822 u8 reserved_at_0[0x1]; 7823 u8 an_disable_admin[0x1]; 7824 u8 an_disable_cap[0x1]; 7825 u8 reserved_at_3[0x5]; 7826 u8 local_port[0x8]; 7827 u8 reserved_at_10[0xd]; 7828 u8 proto_mask[0x3]; 7829 7830 u8 an_status[0x4]; 7831 u8 reserved_at_24[0x1c]; 7832 7833 u8 ext_eth_proto_capability[0x20]; 7834 7835 u8 eth_proto_capability[0x20]; 7836 7837 u8 ib_link_width_capability[0x10]; 7838 u8 ib_proto_capability[0x10]; 7839 7840 u8 ext_eth_proto_admin[0x20]; 7841 7842 u8 eth_proto_admin[0x20]; 7843 7844 u8 ib_link_width_admin[0x10]; 7845 u8 ib_proto_admin[0x10]; 7846 7847 u8 ext_eth_proto_oper[0x20]; 7848 7849 u8 eth_proto_oper[0x20]; 7850 7851 u8 ib_link_width_oper[0x10]; 7852 u8 ib_proto_oper[0x10]; 7853 7854 u8 reserved_at_160[0x1c]; 7855 u8 connector_type[0x4]; 7856 7857 u8 eth_proto_lp_advertise[0x20]; 7858 7859 u8 reserved_at_1a0[0x60]; 7860 }; 7861 7862 struct mlx5_ifc_mlcr_reg_bits { 7863 u8 reserved_at_0[0x8]; 7864 u8 local_port[0x8]; 7865 u8 reserved_at_10[0x20]; 7866 7867 u8 beacon_duration[0x10]; 7868 u8 reserved_at_40[0x10]; 7869 7870 u8 beacon_remain[0x10]; 7871 }; 7872 7873 struct mlx5_ifc_ptas_reg_bits { 7874 u8 reserved_at_0[0x20]; 7875 7876 u8 algorithm_options[0x10]; 7877 u8 reserved_at_30[0x4]; 7878 u8 repetitions_mode[0x4]; 7879 u8 num_of_repetitions[0x8]; 7880 7881 u8 grade_version[0x8]; 7882 u8 height_grade_type[0x4]; 7883 u8 phase_grade_type[0x4]; 7884 u8 height_grade_weight[0x8]; 7885 u8 phase_grade_weight[0x8]; 7886 7887 u8 gisim_measure_bits[0x10]; 7888 u8 adaptive_tap_measure_bits[0x10]; 7889 7890 u8 ber_bath_high_error_threshold[0x10]; 7891 u8 ber_bath_mid_error_threshold[0x10]; 7892 7893 u8 ber_bath_low_error_threshold[0x10]; 7894 u8 one_ratio_high_threshold[0x10]; 7895 7896 u8 one_ratio_high_mid_threshold[0x10]; 7897 u8 one_ratio_low_mid_threshold[0x10]; 7898 7899 u8 one_ratio_low_threshold[0x10]; 7900 u8 ndeo_error_threshold[0x10]; 7901 7902 u8 mixer_offset_step_size[0x10]; 7903 u8 reserved_at_110[0x8]; 7904 u8 mix90_phase_for_voltage_bath[0x8]; 7905 7906 u8 mixer_offset_start[0x10]; 7907 u8 mixer_offset_end[0x10]; 7908 7909 u8 reserved_at_140[0x15]; 7910 u8 ber_test_time[0xb]; 7911 }; 7912 7913 struct mlx5_ifc_pspa_reg_bits { 7914 u8 swid[0x8]; 7915 u8 local_port[0x8]; 7916 u8 sub_port[0x8]; 7917 u8 reserved_at_18[0x8]; 7918 7919 u8 reserved_at_20[0x20]; 7920 }; 7921 7922 struct mlx5_ifc_pqdr_reg_bits { 7923 u8 reserved_at_0[0x8]; 7924 u8 local_port[0x8]; 7925 u8 reserved_at_10[0x5]; 7926 u8 prio[0x3]; 7927 u8 reserved_at_18[0x6]; 7928 u8 mode[0x2]; 7929 7930 u8 reserved_at_20[0x20]; 7931 7932 u8 reserved_at_40[0x10]; 7933 u8 min_threshold[0x10]; 7934 7935 u8 reserved_at_60[0x10]; 7936 u8 max_threshold[0x10]; 7937 7938 u8 reserved_at_80[0x10]; 7939 u8 mark_probability_denominator[0x10]; 7940 7941 u8 reserved_at_a0[0x60]; 7942 }; 7943 7944 struct mlx5_ifc_ppsc_reg_bits { 7945 u8 reserved_at_0[0x8]; 7946 u8 local_port[0x8]; 7947 u8 reserved_at_10[0x10]; 7948 7949 u8 reserved_at_20[0x60]; 7950 7951 u8 reserved_at_80[0x1c]; 7952 u8 wrps_admin[0x4]; 7953 7954 u8 reserved_at_a0[0x1c]; 7955 u8 wrps_status[0x4]; 7956 7957 u8 reserved_at_c0[0x8]; 7958 u8 up_threshold[0x8]; 7959 u8 reserved_at_d0[0x8]; 7960 u8 down_threshold[0x8]; 7961 7962 u8 reserved_at_e0[0x20]; 7963 7964 u8 reserved_at_100[0x1c]; 7965 u8 srps_admin[0x4]; 7966 7967 u8 reserved_at_120[0x1c]; 7968 u8 srps_status[0x4]; 7969 7970 u8 reserved_at_140[0x40]; 7971 }; 7972 7973 struct mlx5_ifc_pplr_reg_bits { 7974 u8 reserved_at_0[0x8]; 7975 u8 local_port[0x8]; 7976 u8 reserved_at_10[0x10]; 7977 7978 u8 reserved_at_20[0x8]; 7979 u8 lb_cap[0x8]; 7980 u8 reserved_at_30[0x8]; 7981 u8 lb_en[0x8]; 7982 }; 7983 7984 struct mlx5_ifc_pplm_reg_bits { 7985 u8 reserved_at_0[0x8]; 7986 u8 local_port[0x8]; 7987 u8 reserved_at_10[0x10]; 7988 7989 u8 reserved_at_20[0x20]; 7990 7991 u8 port_profile_mode[0x8]; 7992 u8 static_port_profile[0x8]; 7993 u8 active_port_profile[0x8]; 7994 u8 reserved_at_58[0x8]; 7995 7996 u8 retransmission_active[0x8]; 7997 u8 fec_mode_active[0x18]; 7998 7999 u8 rs_fec_correction_bypass_cap[0x4]; 8000 u8 reserved_at_84[0x8]; 8001 u8 fec_override_cap_56g[0x4]; 8002 u8 fec_override_cap_100g[0x4]; 8003 u8 fec_override_cap_50g[0x4]; 8004 u8 fec_override_cap_25g[0x4]; 8005 u8 fec_override_cap_10g_40g[0x4]; 8006 8007 u8 rs_fec_correction_bypass_admin[0x4]; 8008 u8 reserved_at_a4[0x8]; 8009 u8 fec_override_admin_56g[0x4]; 8010 u8 fec_override_admin_100g[0x4]; 8011 u8 fec_override_admin_50g[0x4]; 8012 u8 fec_override_admin_25g[0x4]; 8013 u8 fec_override_admin_10g_40g[0x4]; 8014 }; 8015 8016 struct mlx5_ifc_ppcnt_reg_bits { 8017 u8 swid[0x8]; 8018 u8 local_port[0x8]; 8019 u8 pnat[0x2]; 8020 u8 reserved_at_12[0x8]; 8021 u8 grp[0x6]; 8022 8023 u8 clr[0x1]; 8024 u8 reserved_at_21[0x1c]; 8025 u8 prio_tc[0x3]; 8026 8027 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8028 }; 8029 8030 struct mlx5_ifc_mpein_reg_bits { 8031 u8 reserved_at_0[0x2]; 8032 u8 depth[0x6]; 8033 u8 pcie_index[0x8]; 8034 u8 node[0x8]; 8035 u8 reserved_at_18[0x8]; 8036 8037 u8 capability_mask[0x20]; 8038 8039 u8 reserved_at_40[0x8]; 8040 u8 link_width_enabled[0x8]; 8041 u8 link_speed_enabled[0x10]; 8042 8043 u8 lane0_physical_position[0x8]; 8044 u8 link_width_active[0x8]; 8045 u8 link_speed_active[0x10]; 8046 8047 u8 num_of_pfs[0x10]; 8048 u8 num_of_vfs[0x10]; 8049 8050 u8 bdf0[0x10]; 8051 u8 reserved_at_b0[0x10]; 8052 8053 u8 max_read_request_size[0x4]; 8054 u8 max_payload_size[0x4]; 8055 u8 reserved_at_c8[0x5]; 8056 u8 pwr_status[0x3]; 8057 u8 port_type[0x4]; 8058 u8 reserved_at_d4[0xb]; 8059 u8 lane_reversal[0x1]; 8060 8061 u8 reserved_at_e0[0x14]; 8062 u8 pci_power[0xc]; 8063 8064 u8 reserved_at_100[0x20]; 8065 8066 u8 device_status[0x10]; 8067 u8 port_state[0x8]; 8068 u8 reserved_at_138[0x8]; 8069 8070 u8 reserved_at_140[0x10]; 8071 u8 receiver_detect_result[0x10]; 8072 8073 u8 reserved_at_160[0x20]; 8074 }; 8075 8076 struct mlx5_ifc_mpcnt_reg_bits { 8077 u8 reserved_at_0[0x8]; 8078 u8 pcie_index[0x8]; 8079 u8 reserved_at_10[0xa]; 8080 u8 grp[0x6]; 8081 8082 u8 clr[0x1]; 8083 u8 reserved_at_21[0x1f]; 8084 8085 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8086 }; 8087 8088 struct mlx5_ifc_ppad_reg_bits { 8089 u8 reserved_at_0[0x3]; 8090 u8 single_mac[0x1]; 8091 u8 reserved_at_4[0x4]; 8092 u8 local_port[0x8]; 8093 u8 mac_47_32[0x10]; 8094 8095 u8 mac_31_0[0x20]; 8096 8097 u8 reserved_at_40[0x40]; 8098 }; 8099 8100 struct mlx5_ifc_pmtu_reg_bits { 8101 u8 reserved_at_0[0x8]; 8102 u8 local_port[0x8]; 8103 u8 reserved_at_10[0x10]; 8104 8105 u8 max_mtu[0x10]; 8106 u8 reserved_at_30[0x10]; 8107 8108 u8 admin_mtu[0x10]; 8109 u8 reserved_at_50[0x10]; 8110 8111 u8 oper_mtu[0x10]; 8112 u8 reserved_at_70[0x10]; 8113 }; 8114 8115 struct mlx5_ifc_pmpr_reg_bits { 8116 u8 reserved_at_0[0x8]; 8117 u8 module[0x8]; 8118 u8 reserved_at_10[0x10]; 8119 8120 u8 reserved_at_20[0x18]; 8121 u8 attenuation_5g[0x8]; 8122 8123 u8 reserved_at_40[0x18]; 8124 u8 attenuation_7g[0x8]; 8125 8126 u8 reserved_at_60[0x18]; 8127 u8 attenuation_12g[0x8]; 8128 }; 8129 8130 struct mlx5_ifc_pmpe_reg_bits { 8131 u8 reserved_at_0[0x8]; 8132 u8 module[0x8]; 8133 u8 reserved_at_10[0xc]; 8134 u8 module_status[0x4]; 8135 8136 u8 reserved_at_20[0x60]; 8137 }; 8138 8139 struct mlx5_ifc_pmpc_reg_bits { 8140 u8 module_state_updated[32][0x8]; 8141 }; 8142 8143 struct mlx5_ifc_pmlpn_reg_bits { 8144 u8 reserved_at_0[0x4]; 8145 u8 mlpn_status[0x4]; 8146 u8 local_port[0x8]; 8147 u8 reserved_at_10[0x10]; 8148 8149 u8 e[0x1]; 8150 u8 reserved_at_21[0x1f]; 8151 }; 8152 8153 struct mlx5_ifc_pmlp_reg_bits { 8154 u8 rxtx[0x1]; 8155 u8 reserved_at_1[0x7]; 8156 u8 local_port[0x8]; 8157 u8 reserved_at_10[0x8]; 8158 u8 width[0x8]; 8159 8160 u8 lane0_module_mapping[0x20]; 8161 8162 u8 lane1_module_mapping[0x20]; 8163 8164 u8 lane2_module_mapping[0x20]; 8165 8166 u8 lane3_module_mapping[0x20]; 8167 8168 u8 reserved_at_a0[0x160]; 8169 }; 8170 8171 struct mlx5_ifc_pmaos_reg_bits { 8172 u8 reserved_at_0[0x8]; 8173 u8 module[0x8]; 8174 u8 reserved_at_10[0x4]; 8175 u8 admin_status[0x4]; 8176 u8 reserved_at_18[0x4]; 8177 u8 oper_status[0x4]; 8178 8179 u8 ase[0x1]; 8180 u8 ee[0x1]; 8181 u8 reserved_at_22[0x1c]; 8182 u8 e[0x2]; 8183 8184 u8 reserved_at_40[0x40]; 8185 }; 8186 8187 struct mlx5_ifc_plpc_reg_bits { 8188 u8 reserved_at_0[0x4]; 8189 u8 profile_id[0xc]; 8190 u8 reserved_at_10[0x4]; 8191 u8 proto_mask[0x4]; 8192 u8 reserved_at_18[0x8]; 8193 8194 u8 reserved_at_20[0x10]; 8195 u8 lane_speed[0x10]; 8196 8197 u8 reserved_at_40[0x17]; 8198 u8 lpbf[0x1]; 8199 u8 fec_mode_policy[0x8]; 8200 8201 u8 retransmission_capability[0x8]; 8202 u8 fec_mode_capability[0x18]; 8203 8204 u8 retransmission_support_admin[0x8]; 8205 u8 fec_mode_support_admin[0x18]; 8206 8207 u8 retransmission_request_admin[0x8]; 8208 u8 fec_mode_request_admin[0x18]; 8209 8210 u8 reserved_at_c0[0x80]; 8211 }; 8212 8213 struct mlx5_ifc_plib_reg_bits { 8214 u8 reserved_at_0[0x8]; 8215 u8 local_port[0x8]; 8216 u8 reserved_at_10[0x8]; 8217 u8 ib_port[0x8]; 8218 8219 u8 reserved_at_20[0x60]; 8220 }; 8221 8222 struct mlx5_ifc_plbf_reg_bits { 8223 u8 reserved_at_0[0x8]; 8224 u8 local_port[0x8]; 8225 u8 reserved_at_10[0xd]; 8226 u8 lbf_mode[0x3]; 8227 8228 u8 reserved_at_20[0x20]; 8229 }; 8230 8231 struct mlx5_ifc_pipg_reg_bits { 8232 u8 reserved_at_0[0x8]; 8233 u8 local_port[0x8]; 8234 u8 reserved_at_10[0x10]; 8235 8236 u8 dic[0x1]; 8237 u8 reserved_at_21[0x19]; 8238 u8 ipg[0x4]; 8239 u8 reserved_at_3e[0x2]; 8240 }; 8241 8242 struct mlx5_ifc_pifr_reg_bits { 8243 u8 reserved_at_0[0x8]; 8244 u8 local_port[0x8]; 8245 u8 reserved_at_10[0x10]; 8246 8247 u8 reserved_at_20[0xe0]; 8248 8249 u8 port_filter[8][0x20]; 8250 8251 u8 port_filter_update_en[8][0x20]; 8252 }; 8253 8254 struct mlx5_ifc_pfcc_reg_bits { 8255 u8 reserved_at_0[0x8]; 8256 u8 local_port[0x8]; 8257 u8 reserved_at_10[0xb]; 8258 u8 ppan_mask_n[0x1]; 8259 u8 minor_stall_mask[0x1]; 8260 u8 critical_stall_mask[0x1]; 8261 u8 reserved_at_1e[0x2]; 8262 8263 u8 ppan[0x4]; 8264 u8 reserved_at_24[0x4]; 8265 u8 prio_mask_tx[0x8]; 8266 u8 reserved_at_30[0x8]; 8267 u8 prio_mask_rx[0x8]; 8268 8269 u8 pptx[0x1]; 8270 u8 aptx[0x1]; 8271 u8 pptx_mask_n[0x1]; 8272 u8 reserved_at_43[0x5]; 8273 u8 pfctx[0x8]; 8274 u8 reserved_at_50[0x10]; 8275 8276 u8 pprx[0x1]; 8277 u8 aprx[0x1]; 8278 u8 pprx_mask_n[0x1]; 8279 u8 reserved_at_63[0x5]; 8280 u8 pfcrx[0x8]; 8281 u8 reserved_at_70[0x10]; 8282 8283 u8 device_stall_minor_watermark[0x10]; 8284 u8 device_stall_critical_watermark[0x10]; 8285 8286 u8 reserved_at_a0[0x60]; 8287 }; 8288 8289 struct mlx5_ifc_pelc_reg_bits { 8290 u8 op[0x4]; 8291 u8 reserved_at_4[0x4]; 8292 u8 local_port[0x8]; 8293 u8 reserved_at_10[0x10]; 8294 8295 u8 op_admin[0x8]; 8296 u8 op_capability[0x8]; 8297 u8 op_request[0x8]; 8298 u8 op_active[0x8]; 8299 8300 u8 admin[0x40]; 8301 8302 u8 capability[0x40]; 8303 8304 u8 request[0x40]; 8305 8306 u8 active[0x40]; 8307 8308 u8 reserved_at_140[0x80]; 8309 }; 8310 8311 struct mlx5_ifc_peir_reg_bits { 8312 u8 reserved_at_0[0x8]; 8313 u8 local_port[0x8]; 8314 u8 reserved_at_10[0x10]; 8315 8316 u8 reserved_at_20[0xc]; 8317 u8 error_count[0x4]; 8318 u8 reserved_at_30[0x10]; 8319 8320 u8 reserved_at_40[0xc]; 8321 u8 lane[0x4]; 8322 u8 reserved_at_50[0x8]; 8323 u8 error_type[0x8]; 8324 }; 8325 8326 struct mlx5_ifc_mpegc_reg_bits { 8327 u8 reserved_at_0[0x30]; 8328 u8 field_select[0x10]; 8329 8330 u8 tx_overflow_sense[0x1]; 8331 u8 mark_cqe[0x1]; 8332 u8 mark_cnp[0x1]; 8333 u8 reserved_at_43[0x1b]; 8334 u8 tx_lossy_overflow_oper[0x2]; 8335 8336 u8 reserved_at_60[0x100]; 8337 }; 8338 8339 struct mlx5_ifc_pcam_enhanced_features_bits { 8340 u8 reserved_at_0[0x6d]; 8341 u8 rx_icrc_encapsulated_counter[0x1]; 8342 u8 reserved_at_6e[0x4]; 8343 u8 ptys_extended_ethernet[0x1]; 8344 u8 reserved_at_73[0x3]; 8345 u8 pfcc_mask[0x1]; 8346 u8 reserved_at_77[0x3]; 8347 u8 per_lane_error_counters[0x1]; 8348 u8 rx_buffer_fullness_counters[0x1]; 8349 u8 ptys_connector_type[0x1]; 8350 u8 reserved_at_7d[0x1]; 8351 u8 ppcnt_discard_group[0x1]; 8352 u8 ppcnt_statistical_group[0x1]; 8353 }; 8354 8355 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8356 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8357 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8358 8359 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8360 u8 pplm[0x1]; 8361 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8362 8363 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8364 u8 pbmc[0x1]; 8365 u8 pptb[0x1]; 8366 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8367 u8 ppcnt[0x1]; 8368 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8369 }; 8370 8371 struct mlx5_ifc_pcam_reg_bits { 8372 u8 reserved_at_0[0x8]; 8373 u8 feature_group[0x8]; 8374 u8 reserved_at_10[0x8]; 8375 u8 access_reg_group[0x8]; 8376 8377 u8 reserved_at_20[0x20]; 8378 8379 union { 8380 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8381 u8 reserved_at_0[0x80]; 8382 } port_access_reg_cap_mask; 8383 8384 u8 reserved_at_c0[0x80]; 8385 8386 union { 8387 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8388 u8 reserved_at_0[0x80]; 8389 } feature_cap_mask; 8390 8391 u8 reserved_at_1c0[0xc0]; 8392 }; 8393 8394 struct mlx5_ifc_mcam_enhanced_features_bits { 8395 u8 reserved_at_0[0x6e]; 8396 u8 pci_status_and_power[0x1]; 8397 u8 reserved_at_6f[0x5]; 8398 u8 mark_tx_action_cnp[0x1]; 8399 u8 mark_tx_action_cqe[0x1]; 8400 u8 dynamic_tx_overflow[0x1]; 8401 u8 reserved_at_77[0x4]; 8402 u8 pcie_outbound_stalled[0x1]; 8403 u8 tx_overflow_buffer_pkt[0x1]; 8404 u8 mtpps_enh_out_per_adj[0x1]; 8405 u8 mtpps_fs[0x1]; 8406 u8 pcie_performance_group[0x1]; 8407 }; 8408 8409 struct mlx5_ifc_mcam_access_reg_bits { 8410 u8 reserved_at_0[0x1c]; 8411 u8 mcda[0x1]; 8412 u8 mcc[0x1]; 8413 u8 mcqi[0x1]; 8414 u8 reserved_at_1f[0x1]; 8415 8416 u8 regs_95_to_87[0x9]; 8417 u8 mpegc[0x1]; 8418 u8 regs_85_to_68[0x12]; 8419 u8 tracer_registers[0x4]; 8420 8421 u8 regs_63_to_32[0x20]; 8422 u8 regs_31_to_0[0x20]; 8423 }; 8424 8425 struct mlx5_ifc_mcam_reg_bits { 8426 u8 reserved_at_0[0x8]; 8427 u8 feature_group[0x8]; 8428 u8 reserved_at_10[0x8]; 8429 u8 access_reg_group[0x8]; 8430 8431 u8 reserved_at_20[0x20]; 8432 8433 union { 8434 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8435 u8 reserved_at_0[0x80]; 8436 } mng_access_reg_cap_mask; 8437 8438 u8 reserved_at_c0[0x80]; 8439 8440 union { 8441 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8442 u8 reserved_at_0[0x80]; 8443 } mng_feature_cap_mask; 8444 8445 u8 reserved_at_1c0[0x80]; 8446 }; 8447 8448 struct mlx5_ifc_qcam_access_reg_cap_mask { 8449 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8450 u8 qpdpm[0x1]; 8451 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8452 u8 qdpm[0x1]; 8453 u8 qpts[0x1]; 8454 u8 qcap[0x1]; 8455 u8 qcam_access_reg_cap_mask_0[0x1]; 8456 }; 8457 8458 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8459 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8460 u8 qpts_trust_both[0x1]; 8461 }; 8462 8463 struct mlx5_ifc_qcam_reg_bits { 8464 u8 reserved_at_0[0x8]; 8465 u8 feature_group[0x8]; 8466 u8 reserved_at_10[0x8]; 8467 u8 access_reg_group[0x8]; 8468 u8 reserved_at_20[0x20]; 8469 8470 union { 8471 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8472 u8 reserved_at_0[0x80]; 8473 } qos_access_reg_cap_mask; 8474 8475 u8 reserved_at_c0[0x80]; 8476 8477 union { 8478 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8479 u8 reserved_at_0[0x80]; 8480 } qos_feature_cap_mask; 8481 8482 u8 reserved_at_1c0[0x80]; 8483 }; 8484 8485 struct mlx5_ifc_pcap_reg_bits { 8486 u8 reserved_at_0[0x8]; 8487 u8 local_port[0x8]; 8488 u8 reserved_at_10[0x10]; 8489 8490 u8 port_capability_mask[4][0x20]; 8491 }; 8492 8493 struct mlx5_ifc_paos_reg_bits { 8494 u8 swid[0x8]; 8495 u8 local_port[0x8]; 8496 u8 reserved_at_10[0x4]; 8497 u8 admin_status[0x4]; 8498 u8 reserved_at_18[0x4]; 8499 u8 oper_status[0x4]; 8500 8501 u8 ase[0x1]; 8502 u8 ee[0x1]; 8503 u8 reserved_at_22[0x1c]; 8504 u8 e[0x2]; 8505 8506 u8 reserved_at_40[0x40]; 8507 }; 8508 8509 struct mlx5_ifc_pamp_reg_bits { 8510 u8 reserved_at_0[0x8]; 8511 u8 opamp_group[0x8]; 8512 u8 reserved_at_10[0xc]; 8513 u8 opamp_group_type[0x4]; 8514 8515 u8 start_index[0x10]; 8516 u8 reserved_at_30[0x4]; 8517 u8 num_of_indices[0xc]; 8518 8519 u8 index_data[18][0x10]; 8520 }; 8521 8522 struct mlx5_ifc_pcmr_reg_bits { 8523 u8 reserved_at_0[0x8]; 8524 u8 local_port[0x8]; 8525 u8 reserved_at_10[0x10]; 8526 u8 entropy_force_cap[0x1]; 8527 u8 entropy_calc_cap[0x1]; 8528 u8 entropy_gre_calc_cap[0x1]; 8529 u8 reserved_at_23[0x1b]; 8530 u8 fcs_cap[0x1]; 8531 u8 reserved_at_3f[0x1]; 8532 u8 entropy_force[0x1]; 8533 u8 entropy_calc[0x1]; 8534 u8 entropy_gre_calc[0x1]; 8535 u8 reserved_at_43[0x1b]; 8536 u8 fcs_chk[0x1]; 8537 u8 reserved_at_5f[0x1]; 8538 }; 8539 8540 struct mlx5_ifc_lane_2_module_mapping_bits { 8541 u8 reserved_at_0[0x6]; 8542 u8 rx_lane[0x2]; 8543 u8 reserved_at_8[0x6]; 8544 u8 tx_lane[0x2]; 8545 u8 reserved_at_10[0x8]; 8546 u8 module[0x8]; 8547 }; 8548 8549 struct mlx5_ifc_bufferx_reg_bits { 8550 u8 reserved_at_0[0x6]; 8551 u8 lossy[0x1]; 8552 u8 epsb[0x1]; 8553 u8 reserved_at_8[0xc]; 8554 u8 size[0xc]; 8555 8556 u8 xoff_threshold[0x10]; 8557 u8 xon_threshold[0x10]; 8558 }; 8559 8560 struct mlx5_ifc_set_node_in_bits { 8561 u8 node_description[64][0x8]; 8562 }; 8563 8564 struct mlx5_ifc_register_power_settings_bits { 8565 u8 reserved_at_0[0x18]; 8566 u8 power_settings_level[0x8]; 8567 8568 u8 reserved_at_20[0x60]; 8569 }; 8570 8571 struct mlx5_ifc_register_host_endianness_bits { 8572 u8 he[0x1]; 8573 u8 reserved_at_1[0x1f]; 8574 8575 u8 reserved_at_20[0x60]; 8576 }; 8577 8578 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8579 u8 reserved_at_0[0x20]; 8580 8581 u8 mkey[0x20]; 8582 8583 u8 addressh_63_32[0x20]; 8584 8585 u8 addressl_31_0[0x20]; 8586 }; 8587 8588 struct mlx5_ifc_ud_adrs_vector_bits { 8589 u8 dc_key[0x40]; 8590 8591 u8 ext[0x1]; 8592 u8 reserved_at_41[0x7]; 8593 u8 destination_qp_dct[0x18]; 8594 8595 u8 static_rate[0x4]; 8596 u8 sl_eth_prio[0x4]; 8597 u8 fl[0x1]; 8598 u8 mlid[0x7]; 8599 u8 rlid_udp_sport[0x10]; 8600 8601 u8 reserved_at_80[0x20]; 8602 8603 u8 rmac_47_16[0x20]; 8604 8605 u8 rmac_15_0[0x10]; 8606 u8 tclass[0x8]; 8607 u8 hop_limit[0x8]; 8608 8609 u8 reserved_at_e0[0x1]; 8610 u8 grh[0x1]; 8611 u8 reserved_at_e2[0x2]; 8612 u8 src_addr_index[0x8]; 8613 u8 flow_label[0x14]; 8614 8615 u8 rgid_rip[16][0x8]; 8616 }; 8617 8618 struct mlx5_ifc_pages_req_event_bits { 8619 u8 reserved_at_0[0x10]; 8620 u8 function_id[0x10]; 8621 8622 u8 num_pages[0x20]; 8623 8624 u8 reserved_at_40[0xa0]; 8625 }; 8626 8627 struct mlx5_ifc_eqe_bits { 8628 u8 reserved_at_0[0x8]; 8629 u8 event_type[0x8]; 8630 u8 reserved_at_10[0x8]; 8631 u8 event_sub_type[0x8]; 8632 8633 u8 reserved_at_20[0xe0]; 8634 8635 union mlx5_ifc_event_auto_bits event_data; 8636 8637 u8 reserved_at_1e0[0x10]; 8638 u8 signature[0x8]; 8639 u8 reserved_at_1f8[0x7]; 8640 u8 owner[0x1]; 8641 }; 8642 8643 enum { 8644 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8645 }; 8646 8647 struct mlx5_ifc_cmd_queue_entry_bits { 8648 u8 type[0x8]; 8649 u8 reserved_at_8[0x18]; 8650 8651 u8 input_length[0x20]; 8652 8653 u8 input_mailbox_pointer_63_32[0x20]; 8654 8655 u8 input_mailbox_pointer_31_9[0x17]; 8656 u8 reserved_at_77[0x9]; 8657 8658 u8 command_input_inline_data[16][0x8]; 8659 8660 u8 command_output_inline_data[16][0x8]; 8661 8662 u8 output_mailbox_pointer_63_32[0x20]; 8663 8664 u8 output_mailbox_pointer_31_9[0x17]; 8665 u8 reserved_at_1b7[0x9]; 8666 8667 u8 output_length[0x20]; 8668 8669 u8 token[0x8]; 8670 u8 signature[0x8]; 8671 u8 reserved_at_1f0[0x8]; 8672 u8 status[0x7]; 8673 u8 ownership[0x1]; 8674 }; 8675 8676 struct mlx5_ifc_cmd_out_bits { 8677 u8 status[0x8]; 8678 u8 reserved_at_8[0x18]; 8679 8680 u8 syndrome[0x20]; 8681 8682 u8 command_output[0x20]; 8683 }; 8684 8685 struct mlx5_ifc_cmd_in_bits { 8686 u8 opcode[0x10]; 8687 u8 reserved_at_10[0x10]; 8688 8689 u8 reserved_at_20[0x10]; 8690 u8 op_mod[0x10]; 8691 8692 u8 command[0][0x20]; 8693 }; 8694 8695 struct mlx5_ifc_cmd_if_box_bits { 8696 u8 mailbox_data[512][0x8]; 8697 8698 u8 reserved_at_1000[0x180]; 8699 8700 u8 next_pointer_63_32[0x20]; 8701 8702 u8 next_pointer_31_10[0x16]; 8703 u8 reserved_at_11b6[0xa]; 8704 8705 u8 block_number[0x20]; 8706 8707 u8 reserved_at_11e0[0x8]; 8708 u8 token[0x8]; 8709 u8 ctrl_signature[0x8]; 8710 u8 signature[0x8]; 8711 }; 8712 8713 struct mlx5_ifc_mtt_bits { 8714 u8 ptag_63_32[0x20]; 8715 8716 u8 ptag_31_8[0x18]; 8717 u8 reserved_at_38[0x6]; 8718 u8 wr_en[0x1]; 8719 u8 rd_en[0x1]; 8720 }; 8721 8722 struct mlx5_ifc_query_wol_rol_out_bits { 8723 u8 status[0x8]; 8724 u8 reserved_at_8[0x18]; 8725 8726 u8 syndrome[0x20]; 8727 8728 u8 reserved_at_40[0x10]; 8729 u8 rol_mode[0x8]; 8730 u8 wol_mode[0x8]; 8731 8732 u8 reserved_at_60[0x20]; 8733 }; 8734 8735 struct mlx5_ifc_query_wol_rol_in_bits { 8736 u8 opcode[0x10]; 8737 u8 reserved_at_10[0x10]; 8738 8739 u8 reserved_at_20[0x10]; 8740 u8 op_mod[0x10]; 8741 8742 u8 reserved_at_40[0x40]; 8743 }; 8744 8745 struct mlx5_ifc_set_wol_rol_out_bits { 8746 u8 status[0x8]; 8747 u8 reserved_at_8[0x18]; 8748 8749 u8 syndrome[0x20]; 8750 8751 u8 reserved_at_40[0x40]; 8752 }; 8753 8754 struct mlx5_ifc_set_wol_rol_in_bits { 8755 u8 opcode[0x10]; 8756 u8 reserved_at_10[0x10]; 8757 8758 u8 reserved_at_20[0x10]; 8759 u8 op_mod[0x10]; 8760 8761 u8 rol_mode_valid[0x1]; 8762 u8 wol_mode_valid[0x1]; 8763 u8 reserved_at_42[0xe]; 8764 u8 rol_mode[0x8]; 8765 u8 wol_mode[0x8]; 8766 8767 u8 reserved_at_60[0x20]; 8768 }; 8769 8770 enum { 8771 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8772 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8773 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8774 }; 8775 8776 enum { 8777 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8778 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8779 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8780 }; 8781 8782 enum { 8783 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8784 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8785 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8786 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8787 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8788 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8789 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8790 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8791 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8792 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8793 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8794 }; 8795 8796 struct mlx5_ifc_initial_seg_bits { 8797 u8 fw_rev_minor[0x10]; 8798 u8 fw_rev_major[0x10]; 8799 8800 u8 cmd_interface_rev[0x10]; 8801 u8 fw_rev_subminor[0x10]; 8802 8803 u8 reserved_at_40[0x40]; 8804 8805 u8 cmdq_phy_addr_63_32[0x20]; 8806 8807 u8 cmdq_phy_addr_31_12[0x14]; 8808 u8 reserved_at_b4[0x2]; 8809 u8 nic_interface[0x2]; 8810 u8 log_cmdq_size[0x4]; 8811 u8 log_cmdq_stride[0x4]; 8812 8813 u8 command_doorbell_vector[0x20]; 8814 8815 u8 reserved_at_e0[0xf00]; 8816 8817 u8 initializing[0x1]; 8818 u8 reserved_at_fe1[0x4]; 8819 u8 nic_interface_supported[0x3]; 8820 u8 embedded_cpu[0x1]; 8821 u8 reserved_at_fe9[0x17]; 8822 8823 struct mlx5_ifc_health_buffer_bits health_buffer; 8824 8825 u8 no_dram_nic_offset[0x20]; 8826 8827 u8 reserved_at_1220[0x6e40]; 8828 8829 u8 reserved_at_8060[0x1f]; 8830 u8 clear_int[0x1]; 8831 8832 u8 health_syndrome[0x8]; 8833 u8 health_counter[0x18]; 8834 8835 u8 reserved_at_80a0[0x17fc0]; 8836 }; 8837 8838 struct mlx5_ifc_mtpps_reg_bits { 8839 u8 reserved_at_0[0xc]; 8840 u8 cap_number_of_pps_pins[0x4]; 8841 u8 reserved_at_10[0x4]; 8842 u8 cap_max_num_of_pps_in_pins[0x4]; 8843 u8 reserved_at_18[0x4]; 8844 u8 cap_max_num_of_pps_out_pins[0x4]; 8845 8846 u8 reserved_at_20[0x24]; 8847 u8 cap_pin_3_mode[0x4]; 8848 u8 reserved_at_48[0x4]; 8849 u8 cap_pin_2_mode[0x4]; 8850 u8 reserved_at_50[0x4]; 8851 u8 cap_pin_1_mode[0x4]; 8852 u8 reserved_at_58[0x4]; 8853 u8 cap_pin_0_mode[0x4]; 8854 8855 u8 reserved_at_60[0x4]; 8856 u8 cap_pin_7_mode[0x4]; 8857 u8 reserved_at_68[0x4]; 8858 u8 cap_pin_6_mode[0x4]; 8859 u8 reserved_at_70[0x4]; 8860 u8 cap_pin_5_mode[0x4]; 8861 u8 reserved_at_78[0x4]; 8862 u8 cap_pin_4_mode[0x4]; 8863 8864 u8 field_select[0x20]; 8865 u8 reserved_at_a0[0x60]; 8866 8867 u8 enable[0x1]; 8868 u8 reserved_at_101[0xb]; 8869 u8 pattern[0x4]; 8870 u8 reserved_at_110[0x4]; 8871 u8 pin_mode[0x4]; 8872 u8 pin[0x8]; 8873 8874 u8 reserved_at_120[0x20]; 8875 8876 u8 time_stamp[0x40]; 8877 8878 u8 out_pulse_duration[0x10]; 8879 u8 out_periodic_adjustment[0x10]; 8880 u8 enhanced_out_periodic_adjustment[0x20]; 8881 8882 u8 reserved_at_1c0[0x20]; 8883 }; 8884 8885 struct mlx5_ifc_mtppse_reg_bits { 8886 u8 reserved_at_0[0x18]; 8887 u8 pin[0x8]; 8888 u8 event_arm[0x1]; 8889 u8 reserved_at_21[0x1b]; 8890 u8 event_generation_mode[0x4]; 8891 u8 reserved_at_40[0x40]; 8892 }; 8893 8894 struct mlx5_ifc_mcqi_cap_bits { 8895 u8 supported_info_bitmask[0x20]; 8896 8897 u8 component_size[0x20]; 8898 8899 u8 max_component_size[0x20]; 8900 8901 u8 log_mcda_word_size[0x4]; 8902 u8 reserved_at_64[0xc]; 8903 u8 mcda_max_write_size[0x10]; 8904 8905 u8 rd_en[0x1]; 8906 u8 reserved_at_81[0x1]; 8907 u8 match_chip_id[0x1]; 8908 u8 match_psid[0x1]; 8909 u8 check_user_timestamp[0x1]; 8910 u8 match_base_guid_mac[0x1]; 8911 u8 reserved_at_86[0x1a]; 8912 }; 8913 8914 struct mlx5_ifc_mcqi_reg_bits { 8915 u8 read_pending_component[0x1]; 8916 u8 reserved_at_1[0xf]; 8917 u8 component_index[0x10]; 8918 8919 u8 reserved_at_20[0x20]; 8920 8921 u8 reserved_at_40[0x1b]; 8922 u8 info_type[0x5]; 8923 8924 u8 info_size[0x20]; 8925 8926 u8 offset[0x20]; 8927 8928 u8 reserved_at_a0[0x10]; 8929 u8 data_size[0x10]; 8930 8931 u8 data[0][0x20]; 8932 }; 8933 8934 struct mlx5_ifc_mcc_reg_bits { 8935 u8 reserved_at_0[0x4]; 8936 u8 time_elapsed_since_last_cmd[0xc]; 8937 u8 reserved_at_10[0x8]; 8938 u8 instruction[0x8]; 8939 8940 u8 reserved_at_20[0x10]; 8941 u8 component_index[0x10]; 8942 8943 u8 reserved_at_40[0x8]; 8944 u8 update_handle[0x18]; 8945 8946 u8 handle_owner_type[0x4]; 8947 u8 handle_owner_host_id[0x4]; 8948 u8 reserved_at_68[0x1]; 8949 u8 control_progress[0x7]; 8950 u8 error_code[0x8]; 8951 u8 reserved_at_78[0x4]; 8952 u8 control_state[0x4]; 8953 8954 u8 component_size[0x20]; 8955 8956 u8 reserved_at_a0[0x60]; 8957 }; 8958 8959 struct mlx5_ifc_mcda_reg_bits { 8960 u8 reserved_at_0[0x8]; 8961 u8 update_handle[0x18]; 8962 8963 u8 offset[0x20]; 8964 8965 u8 reserved_at_40[0x10]; 8966 u8 size[0x10]; 8967 8968 u8 reserved_at_60[0x20]; 8969 8970 u8 data[0][0x20]; 8971 }; 8972 8973 union mlx5_ifc_ports_control_registers_document_bits { 8974 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8975 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8976 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8977 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8978 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8979 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8980 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8981 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8982 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8983 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8984 struct mlx5_ifc_paos_reg_bits paos_reg; 8985 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8986 struct mlx5_ifc_peir_reg_bits peir_reg; 8987 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8988 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8989 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8990 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8991 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8992 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8993 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8994 struct mlx5_ifc_plib_reg_bits plib_reg; 8995 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8996 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8997 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8998 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8999 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9000 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9001 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9002 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9003 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9004 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9005 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9006 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9007 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9008 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9009 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9010 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9011 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9012 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9013 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9014 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9015 struct mlx5_ifc_pude_reg_bits pude_reg; 9016 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9017 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9018 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9019 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9020 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9021 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9022 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9023 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9024 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9025 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9026 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9027 u8 reserved_at_0[0x60e0]; 9028 }; 9029 9030 union mlx5_ifc_debug_enhancements_document_bits { 9031 struct mlx5_ifc_health_buffer_bits health_buffer; 9032 u8 reserved_at_0[0x200]; 9033 }; 9034 9035 union mlx5_ifc_uplink_pci_interface_document_bits { 9036 struct mlx5_ifc_initial_seg_bits initial_seg; 9037 u8 reserved_at_0[0x20060]; 9038 }; 9039 9040 struct mlx5_ifc_set_flow_table_root_out_bits { 9041 u8 status[0x8]; 9042 u8 reserved_at_8[0x18]; 9043 9044 u8 syndrome[0x20]; 9045 9046 u8 reserved_at_40[0x40]; 9047 }; 9048 9049 struct mlx5_ifc_set_flow_table_root_in_bits { 9050 u8 opcode[0x10]; 9051 u8 reserved_at_10[0x10]; 9052 9053 u8 reserved_at_20[0x10]; 9054 u8 op_mod[0x10]; 9055 9056 u8 other_vport[0x1]; 9057 u8 reserved_at_41[0xf]; 9058 u8 vport_number[0x10]; 9059 9060 u8 reserved_at_60[0x20]; 9061 9062 u8 table_type[0x8]; 9063 u8 reserved_at_88[0x18]; 9064 9065 u8 reserved_at_a0[0x8]; 9066 u8 table_id[0x18]; 9067 9068 u8 reserved_at_c0[0x8]; 9069 u8 underlay_qpn[0x18]; 9070 u8 reserved_at_e0[0x120]; 9071 }; 9072 9073 enum { 9074 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9075 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9076 }; 9077 9078 struct mlx5_ifc_modify_flow_table_out_bits { 9079 u8 status[0x8]; 9080 u8 reserved_at_8[0x18]; 9081 9082 u8 syndrome[0x20]; 9083 9084 u8 reserved_at_40[0x40]; 9085 }; 9086 9087 struct mlx5_ifc_modify_flow_table_in_bits { 9088 u8 opcode[0x10]; 9089 u8 reserved_at_10[0x10]; 9090 9091 u8 reserved_at_20[0x10]; 9092 u8 op_mod[0x10]; 9093 9094 u8 other_vport[0x1]; 9095 u8 reserved_at_41[0xf]; 9096 u8 vport_number[0x10]; 9097 9098 u8 reserved_at_60[0x10]; 9099 u8 modify_field_select[0x10]; 9100 9101 u8 table_type[0x8]; 9102 u8 reserved_at_88[0x18]; 9103 9104 u8 reserved_at_a0[0x8]; 9105 u8 table_id[0x18]; 9106 9107 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9108 }; 9109 9110 struct mlx5_ifc_ets_tcn_config_reg_bits { 9111 u8 g[0x1]; 9112 u8 b[0x1]; 9113 u8 r[0x1]; 9114 u8 reserved_at_3[0x9]; 9115 u8 group[0x4]; 9116 u8 reserved_at_10[0x9]; 9117 u8 bw_allocation[0x7]; 9118 9119 u8 reserved_at_20[0xc]; 9120 u8 max_bw_units[0x4]; 9121 u8 reserved_at_30[0x8]; 9122 u8 max_bw_value[0x8]; 9123 }; 9124 9125 struct mlx5_ifc_ets_global_config_reg_bits { 9126 u8 reserved_at_0[0x2]; 9127 u8 r[0x1]; 9128 u8 reserved_at_3[0x1d]; 9129 9130 u8 reserved_at_20[0xc]; 9131 u8 max_bw_units[0x4]; 9132 u8 reserved_at_30[0x8]; 9133 u8 max_bw_value[0x8]; 9134 }; 9135 9136 struct mlx5_ifc_qetc_reg_bits { 9137 u8 reserved_at_0[0x8]; 9138 u8 port_number[0x8]; 9139 u8 reserved_at_10[0x30]; 9140 9141 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9142 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9143 }; 9144 9145 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9146 u8 e[0x1]; 9147 u8 reserved_at_01[0x0b]; 9148 u8 prio[0x04]; 9149 }; 9150 9151 struct mlx5_ifc_qpdpm_reg_bits { 9152 u8 reserved_at_0[0x8]; 9153 u8 local_port[0x8]; 9154 u8 reserved_at_10[0x10]; 9155 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9156 }; 9157 9158 struct mlx5_ifc_qpts_reg_bits { 9159 u8 reserved_at_0[0x8]; 9160 u8 local_port[0x8]; 9161 u8 reserved_at_10[0x2d]; 9162 u8 trust_state[0x3]; 9163 }; 9164 9165 struct mlx5_ifc_pptb_reg_bits { 9166 u8 reserved_at_0[0x2]; 9167 u8 mm[0x2]; 9168 u8 reserved_at_4[0x4]; 9169 u8 local_port[0x8]; 9170 u8 reserved_at_10[0x6]; 9171 u8 cm[0x1]; 9172 u8 um[0x1]; 9173 u8 pm[0x8]; 9174 9175 u8 prio_x_buff[0x20]; 9176 9177 u8 pm_msb[0x8]; 9178 u8 reserved_at_48[0x10]; 9179 u8 ctrl_buff[0x4]; 9180 u8 untagged_buff[0x4]; 9181 }; 9182 9183 struct mlx5_ifc_pbmc_reg_bits { 9184 u8 reserved_at_0[0x8]; 9185 u8 local_port[0x8]; 9186 u8 reserved_at_10[0x10]; 9187 9188 u8 xoff_timer_value[0x10]; 9189 u8 xoff_refresh[0x10]; 9190 9191 u8 reserved_at_40[0x9]; 9192 u8 fullness_threshold[0x7]; 9193 u8 port_buffer_size[0x10]; 9194 9195 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9196 9197 u8 reserved_at_2e0[0x40]; 9198 }; 9199 9200 struct mlx5_ifc_qtct_reg_bits { 9201 u8 reserved_at_0[0x8]; 9202 u8 port_number[0x8]; 9203 u8 reserved_at_10[0xd]; 9204 u8 prio[0x3]; 9205 9206 u8 reserved_at_20[0x1d]; 9207 u8 tclass[0x3]; 9208 }; 9209 9210 struct mlx5_ifc_mcia_reg_bits { 9211 u8 l[0x1]; 9212 u8 reserved_at_1[0x7]; 9213 u8 module[0x8]; 9214 u8 reserved_at_10[0x8]; 9215 u8 status[0x8]; 9216 9217 u8 i2c_device_address[0x8]; 9218 u8 page_number[0x8]; 9219 u8 device_address[0x10]; 9220 9221 u8 reserved_at_40[0x10]; 9222 u8 size[0x10]; 9223 9224 u8 reserved_at_60[0x20]; 9225 9226 u8 dword_0[0x20]; 9227 u8 dword_1[0x20]; 9228 u8 dword_2[0x20]; 9229 u8 dword_3[0x20]; 9230 u8 dword_4[0x20]; 9231 u8 dword_5[0x20]; 9232 u8 dword_6[0x20]; 9233 u8 dword_7[0x20]; 9234 u8 dword_8[0x20]; 9235 u8 dword_9[0x20]; 9236 u8 dword_10[0x20]; 9237 u8 dword_11[0x20]; 9238 }; 9239 9240 struct mlx5_ifc_dcbx_param_bits { 9241 u8 dcbx_cee_cap[0x1]; 9242 u8 dcbx_ieee_cap[0x1]; 9243 u8 dcbx_standby_cap[0x1]; 9244 u8 reserved_at_3[0x5]; 9245 u8 port_number[0x8]; 9246 u8 reserved_at_10[0xa]; 9247 u8 max_application_table_size[6]; 9248 u8 reserved_at_20[0x15]; 9249 u8 version_oper[0x3]; 9250 u8 reserved_at_38[5]; 9251 u8 version_admin[0x3]; 9252 u8 willing_admin[0x1]; 9253 u8 reserved_at_41[0x3]; 9254 u8 pfc_cap_oper[0x4]; 9255 u8 reserved_at_48[0x4]; 9256 u8 pfc_cap_admin[0x4]; 9257 u8 reserved_at_50[0x4]; 9258 u8 num_of_tc_oper[0x4]; 9259 u8 reserved_at_58[0x4]; 9260 u8 num_of_tc_admin[0x4]; 9261 u8 remote_willing[0x1]; 9262 u8 reserved_at_61[3]; 9263 u8 remote_pfc_cap[4]; 9264 u8 reserved_at_68[0x14]; 9265 u8 remote_num_of_tc[0x4]; 9266 u8 reserved_at_80[0x18]; 9267 u8 error[0x8]; 9268 u8 reserved_at_a0[0x160]; 9269 }; 9270 9271 struct mlx5_ifc_lagc_bits { 9272 u8 reserved_at_0[0x1d]; 9273 u8 lag_state[0x3]; 9274 9275 u8 reserved_at_20[0x14]; 9276 u8 tx_remap_affinity_2[0x4]; 9277 u8 reserved_at_38[0x4]; 9278 u8 tx_remap_affinity_1[0x4]; 9279 }; 9280 9281 struct mlx5_ifc_create_lag_out_bits { 9282 u8 status[0x8]; 9283 u8 reserved_at_8[0x18]; 9284 9285 u8 syndrome[0x20]; 9286 9287 u8 reserved_at_40[0x40]; 9288 }; 9289 9290 struct mlx5_ifc_create_lag_in_bits { 9291 u8 opcode[0x10]; 9292 u8 reserved_at_10[0x10]; 9293 9294 u8 reserved_at_20[0x10]; 9295 u8 op_mod[0x10]; 9296 9297 struct mlx5_ifc_lagc_bits ctx; 9298 }; 9299 9300 struct mlx5_ifc_modify_lag_out_bits { 9301 u8 status[0x8]; 9302 u8 reserved_at_8[0x18]; 9303 9304 u8 syndrome[0x20]; 9305 9306 u8 reserved_at_40[0x40]; 9307 }; 9308 9309 struct mlx5_ifc_modify_lag_in_bits { 9310 u8 opcode[0x10]; 9311 u8 reserved_at_10[0x10]; 9312 9313 u8 reserved_at_20[0x10]; 9314 u8 op_mod[0x10]; 9315 9316 u8 reserved_at_40[0x20]; 9317 u8 field_select[0x20]; 9318 9319 struct mlx5_ifc_lagc_bits ctx; 9320 }; 9321 9322 struct mlx5_ifc_query_lag_out_bits { 9323 u8 status[0x8]; 9324 u8 reserved_at_8[0x18]; 9325 9326 u8 syndrome[0x20]; 9327 9328 u8 reserved_at_40[0x40]; 9329 9330 struct mlx5_ifc_lagc_bits ctx; 9331 }; 9332 9333 struct mlx5_ifc_query_lag_in_bits { 9334 u8 opcode[0x10]; 9335 u8 reserved_at_10[0x10]; 9336 9337 u8 reserved_at_20[0x10]; 9338 u8 op_mod[0x10]; 9339 9340 u8 reserved_at_40[0x40]; 9341 }; 9342 9343 struct mlx5_ifc_destroy_lag_out_bits { 9344 u8 status[0x8]; 9345 u8 reserved_at_8[0x18]; 9346 9347 u8 syndrome[0x20]; 9348 9349 u8 reserved_at_40[0x40]; 9350 }; 9351 9352 struct mlx5_ifc_destroy_lag_in_bits { 9353 u8 opcode[0x10]; 9354 u8 reserved_at_10[0x10]; 9355 9356 u8 reserved_at_20[0x10]; 9357 u8 op_mod[0x10]; 9358 9359 u8 reserved_at_40[0x40]; 9360 }; 9361 9362 struct mlx5_ifc_create_vport_lag_out_bits { 9363 u8 status[0x8]; 9364 u8 reserved_at_8[0x18]; 9365 9366 u8 syndrome[0x20]; 9367 9368 u8 reserved_at_40[0x40]; 9369 }; 9370 9371 struct mlx5_ifc_create_vport_lag_in_bits { 9372 u8 opcode[0x10]; 9373 u8 reserved_at_10[0x10]; 9374 9375 u8 reserved_at_20[0x10]; 9376 u8 op_mod[0x10]; 9377 9378 u8 reserved_at_40[0x40]; 9379 }; 9380 9381 struct mlx5_ifc_destroy_vport_lag_out_bits { 9382 u8 status[0x8]; 9383 u8 reserved_at_8[0x18]; 9384 9385 u8 syndrome[0x20]; 9386 9387 u8 reserved_at_40[0x40]; 9388 }; 9389 9390 struct mlx5_ifc_destroy_vport_lag_in_bits { 9391 u8 opcode[0x10]; 9392 u8 reserved_at_10[0x10]; 9393 9394 u8 reserved_at_20[0x10]; 9395 u8 op_mod[0x10]; 9396 9397 u8 reserved_at_40[0x40]; 9398 }; 9399 9400 struct mlx5_ifc_alloc_memic_in_bits { 9401 u8 opcode[0x10]; 9402 u8 reserved_at_10[0x10]; 9403 9404 u8 reserved_at_20[0x10]; 9405 u8 op_mod[0x10]; 9406 9407 u8 reserved_at_30[0x20]; 9408 9409 u8 reserved_at_40[0x18]; 9410 u8 log_memic_addr_alignment[0x8]; 9411 9412 u8 range_start_addr[0x40]; 9413 9414 u8 range_size[0x20]; 9415 9416 u8 memic_size[0x20]; 9417 }; 9418 9419 struct mlx5_ifc_alloc_memic_out_bits { 9420 u8 status[0x8]; 9421 u8 reserved_at_8[0x18]; 9422 9423 u8 syndrome[0x20]; 9424 9425 u8 memic_start_addr[0x40]; 9426 }; 9427 9428 struct mlx5_ifc_dealloc_memic_in_bits { 9429 u8 opcode[0x10]; 9430 u8 reserved_at_10[0x10]; 9431 9432 u8 reserved_at_20[0x10]; 9433 u8 op_mod[0x10]; 9434 9435 u8 reserved_at_40[0x40]; 9436 9437 u8 memic_start_addr[0x40]; 9438 9439 u8 memic_size[0x20]; 9440 9441 u8 reserved_at_e0[0x20]; 9442 }; 9443 9444 struct mlx5_ifc_dealloc_memic_out_bits { 9445 u8 status[0x8]; 9446 u8 reserved_at_8[0x18]; 9447 9448 u8 syndrome[0x20]; 9449 9450 u8 reserved_at_40[0x40]; 9451 }; 9452 9453 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9454 u8 opcode[0x10]; 9455 u8 uid[0x10]; 9456 9457 u8 reserved_at_20[0x10]; 9458 u8 obj_type[0x10]; 9459 9460 u8 obj_id[0x20]; 9461 9462 u8 reserved_at_60[0x20]; 9463 }; 9464 9465 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9466 u8 status[0x8]; 9467 u8 reserved_at_8[0x18]; 9468 9469 u8 syndrome[0x20]; 9470 9471 u8 obj_id[0x20]; 9472 9473 u8 reserved_at_60[0x20]; 9474 }; 9475 9476 struct mlx5_ifc_umem_bits { 9477 u8 reserved_at_0[0x80]; 9478 9479 u8 reserved_at_80[0x1b]; 9480 u8 log_page_size[0x5]; 9481 9482 u8 page_offset[0x20]; 9483 9484 u8 num_of_mtt[0x40]; 9485 9486 struct mlx5_ifc_mtt_bits mtt[0]; 9487 }; 9488 9489 struct mlx5_ifc_uctx_bits { 9490 u8 cap[0x20]; 9491 9492 u8 reserved_at_20[0x160]; 9493 }; 9494 9495 struct mlx5_ifc_create_umem_in_bits { 9496 u8 opcode[0x10]; 9497 u8 uid[0x10]; 9498 9499 u8 reserved_at_20[0x10]; 9500 u8 op_mod[0x10]; 9501 9502 u8 reserved_at_40[0x40]; 9503 9504 struct mlx5_ifc_umem_bits umem; 9505 }; 9506 9507 struct mlx5_ifc_create_uctx_in_bits { 9508 u8 opcode[0x10]; 9509 u8 reserved_at_10[0x10]; 9510 9511 u8 reserved_at_20[0x10]; 9512 u8 op_mod[0x10]; 9513 9514 u8 reserved_at_40[0x40]; 9515 9516 struct mlx5_ifc_uctx_bits uctx; 9517 }; 9518 9519 struct mlx5_ifc_destroy_uctx_in_bits { 9520 u8 opcode[0x10]; 9521 u8 reserved_at_10[0x10]; 9522 9523 u8 reserved_at_20[0x10]; 9524 u8 op_mod[0x10]; 9525 9526 u8 reserved_at_40[0x10]; 9527 u8 uid[0x10]; 9528 9529 u8 reserved_at_60[0x20]; 9530 }; 9531 9532 struct mlx5_ifc_mtrc_string_db_param_bits { 9533 u8 string_db_base_address[0x20]; 9534 9535 u8 reserved_at_20[0x8]; 9536 u8 string_db_size[0x18]; 9537 }; 9538 9539 struct mlx5_ifc_mtrc_cap_bits { 9540 u8 trace_owner[0x1]; 9541 u8 trace_to_memory[0x1]; 9542 u8 reserved_at_2[0x4]; 9543 u8 trc_ver[0x2]; 9544 u8 reserved_at_8[0x14]; 9545 u8 num_string_db[0x4]; 9546 9547 u8 first_string_trace[0x8]; 9548 u8 num_string_trace[0x8]; 9549 u8 reserved_at_30[0x28]; 9550 9551 u8 log_max_trace_buffer_size[0x8]; 9552 9553 u8 reserved_at_60[0x20]; 9554 9555 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9556 9557 u8 reserved_at_280[0x180]; 9558 }; 9559 9560 struct mlx5_ifc_mtrc_conf_bits { 9561 u8 reserved_at_0[0x1c]; 9562 u8 trace_mode[0x4]; 9563 u8 reserved_at_20[0x18]; 9564 u8 log_trace_buffer_size[0x8]; 9565 u8 trace_mkey[0x20]; 9566 u8 reserved_at_60[0x3a0]; 9567 }; 9568 9569 struct mlx5_ifc_mtrc_stdb_bits { 9570 u8 string_db_index[0x4]; 9571 u8 reserved_at_4[0x4]; 9572 u8 read_size[0x18]; 9573 u8 start_offset[0x20]; 9574 u8 string_db_data[0]; 9575 }; 9576 9577 struct mlx5_ifc_mtrc_ctrl_bits { 9578 u8 trace_status[0x2]; 9579 u8 reserved_at_2[0x2]; 9580 u8 arm_event[0x1]; 9581 u8 reserved_at_5[0xb]; 9582 u8 modify_field_select[0x10]; 9583 u8 reserved_at_20[0x2b]; 9584 u8 current_timestamp52_32[0x15]; 9585 u8 current_timestamp31_0[0x20]; 9586 u8 reserved_at_80[0x180]; 9587 }; 9588 9589 struct mlx5_ifc_host_params_context_bits { 9590 u8 host_number[0x8]; 9591 u8 reserved_at_8[0x8]; 9592 u8 host_num_of_vfs[0x10]; 9593 9594 u8 reserved_at_20[0x10]; 9595 u8 host_pci_bus[0x10]; 9596 9597 u8 reserved_at_40[0x10]; 9598 u8 host_pci_device[0x10]; 9599 9600 u8 reserved_at_60[0x10]; 9601 u8 host_pci_function[0x10]; 9602 9603 u8 reserved_at_80[0x180]; 9604 }; 9605 9606 struct mlx5_ifc_query_host_params_in_bits { 9607 u8 opcode[0x10]; 9608 u8 reserved_at_10[0x10]; 9609 9610 u8 reserved_at_20[0x10]; 9611 u8 op_mod[0x10]; 9612 9613 u8 reserved_at_40[0x40]; 9614 }; 9615 9616 struct mlx5_ifc_query_host_params_out_bits { 9617 u8 status[0x8]; 9618 u8 reserved_at_8[0x18]; 9619 9620 u8 syndrome[0x20]; 9621 9622 u8 reserved_at_40[0x40]; 9623 9624 struct mlx5_ifc_host_params_context_bits host_params_context; 9625 9626 u8 reserved_at_280[0x180]; 9627 }; 9628 9629 #endif /* MLX5_IFC_H */ 9630