1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4), 80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5), 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_UCTX = 0x0004, 85 MLX5_OBJ_TYPE_UMEM = 0x0005, 86 }; 87 88 enum { 89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 91 MLX5_CMD_OP_INIT_HCA = 0x102, 92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 93 MLX5_CMD_OP_ENABLE_HCA = 0x104, 94 MLX5_CMD_OP_DISABLE_HCA = 0x105, 95 MLX5_CMD_OP_QUERY_PAGES = 0x107, 96 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 97 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 98 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 99 MLX5_CMD_OP_SET_ISSI = 0x10b, 100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 108 MLX5_CMD_OP_CREATE_EQ = 0x301, 109 MLX5_CMD_OP_DESTROY_EQ = 0x302, 110 MLX5_CMD_OP_QUERY_EQ = 0x303, 111 MLX5_CMD_OP_GEN_EQE = 0x304, 112 MLX5_CMD_OP_CREATE_CQ = 0x400, 113 MLX5_CMD_OP_DESTROY_CQ = 0x401, 114 MLX5_CMD_OP_QUERY_CQ = 0x402, 115 MLX5_CMD_OP_MODIFY_CQ = 0x403, 116 MLX5_CMD_OP_CREATE_QP = 0x500, 117 MLX5_CMD_OP_DESTROY_QP = 0x501, 118 MLX5_CMD_OP_RST2INIT_QP = 0x502, 119 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 120 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 121 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 123 MLX5_CMD_OP_2ERR_QP = 0x507, 124 MLX5_CMD_OP_2RST_QP = 0x50a, 125 MLX5_CMD_OP_QUERY_QP = 0x50b, 126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 128 MLX5_CMD_OP_CREATE_PSV = 0x600, 129 MLX5_CMD_OP_DESTROY_PSV = 0x601, 130 MLX5_CMD_OP_CREATE_SRQ = 0x700, 131 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 132 MLX5_CMD_OP_QUERY_SRQ = 0x702, 133 MLX5_CMD_OP_ARM_RQ = 0x703, 134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 138 MLX5_CMD_OP_CREATE_DCT = 0x710, 139 MLX5_CMD_OP_DESTROY_DCT = 0x711, 140 MLX5_CMD_OP_DRAIN_DCT = 0x712, 141 MLX5_CMD_OP_QUERY_DCT = 0x713, 142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 143 MLX5_CMD_OP_CREATE_XRQ = 0x717, 144 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 145 MLX5_CMD_OP_QUERY_XRQ = 0x719, 146 MLX5_CMD_OP_ARM_XRQ = 0x71a, 147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 164 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 165 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 166 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 167 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 168 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 169 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 170 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 171 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 172 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 173 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 174 MLX5_CMD_OP_ALLOC_PD = 0x800, 175 MLX5_CMD_OP_DEALLOC_PD = 0x801, 176 MLX5_CMD_OP_ALLOC_UAR = 0x802, 177 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 178 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 179 MLX5_CMD_OP_ACCESS_REG = 0x805, 180 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 181 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 182 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 183 MLX5_CMD_OP_MAD_IFC = 0x50d, 184 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 185 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 186 MLX5_CMD_OP_NOP = 0x80d, 187 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 188 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 189 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 190 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 191 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 192 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 193 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 194 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 195 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 196 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 197 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 198 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 199 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 200 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 201 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 202 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 203 MLX5_CMD_OP_CREATE_LAG = 0x840, 204 MLX5_CMD_OP_MODIFY_LAG = 0x841, 205 MLX5_CMD_OP_QUERY_LAG = 0x842, 206 MLX5_CMD_OP_DESTROY_LAG = 0x843, 207 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 208 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 209 MLX5_CMD_OP_CREATE_TIR = 0x900, 210 MLX5_CMD_OP_MODIFY_TIR = 0x901, 211 MLX5_CMD_OP_DESTROY_TIR = 0x902, 212 MLX5_CMD_OP_QUERY_TIR = 0x903, 213 MLX5_CMD_OP_CREATE_SQ = 0x904, 214 MLX5_CMD_OP_MODIFY_SQ = 0x905, 215 MLX5_CMD_OP_DESTROY_SQ = 0x906, 216 MLX5_CMD_OP_QUERY_SQ = 0x907, 217 MLX5_CMD_OP_CREATE_RQ = 0x908, 218 MLX5_CMD_OP_MODIFY_RQ = 0x909, 219 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 220 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 221 MLX5_CMD_OP_QUERY_RQ = 0x90b, 222 MLX5_CMD_OP_CREATE_RMP = 0x90c, 223 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 224 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 225 MLX5_CMD_OP_QUERY_RMP = 0x90f, 226 MLX5_CMD_OP_CREATE_TIS = 0x912, 227 MLX5_CMD_OP_MODIFY_TIS = 0x913, 228 MLX5_CMD_OP_DESTROY_TIS = 0x914, 229 MLX5_CMD_OP_QUERY_TIS = 0x915, 230 MLX5_CMD_OP_CREATE_RQT = 0x916, 231 MLX5_CMD_OP_MODIFY_RQT = 0x917, 232 MLX5_CMD_OP_DESTROY_RQT = 0x918, 233 MLX5_CMD_OP_QUERY_RQT = 0x919, 234 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 235 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 236 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 238 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 239 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 240 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 241 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 242 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 243 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 244 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 245 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 246 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 247 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 248 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 249 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 250 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 251 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 252 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 253 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 254 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 255 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 256 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 257 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 258 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 259 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 260 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 261 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 262 MLX5_CMD_OP_MAX 263 }; 264 265 struct mlx5_ifc_flow_table_fields_supported_bits { 266 u8 outer_dmac[0x1]; 267 u8 outer_smac[0x1]; 268 u8 outer_ether_type[0x1]; 269 u8 outer_ip_version[0x1]; 270 u8 outer_first_prio[0x1]; 271 u8 outer_first_cfi[0x1]; 272 u8 outer_first_vid[0x1]; 273 u8 outer_ipv4_ttl[0x1]; 274 u8 outer_second_prio[0x1]; 275 u8 outer_second_cfi[0x1]; 276 u8 outer_second_vid[0x1]; 277 u8 reserved_at_b[0x1]; 278 u8 outer_sip[0x1]; 279 u8 outer_dip[0x1]; 280 u8 outer_frag[0x1]; 281 u8 outer_ip_protocol[0x1]; 282 u8 outer_ip_ecn[0x1]; 283 u8 outer_ip_dscp[0x1]; 284 u8 outer_udp_sport[0x1]; 285 u8 outer_udp_dport[0x1]; 286 u8 outer_tcp_sport[0x1]; 287 u8 outer_tcp_dport[0x1]; 288 u8 outer_tcp_flags[0x1]; 289 u8 outer_gre_protocol[0x1]; 290 u8 outer_gre_key[0x1]; 291 u8 outer_vxlan_vni[0x1]; 292 u8 reserved_at_1a[0x5]; 293 u8 source_eswitch_port[0x1]; 294 295 u8 inner_dmac[0x1]; 296 u8 inner_smac[0x1]; 297 u8 inner_ether_type[0x1]; 298 u8 inner_ip_version[0x1]; 299 u8 inner_first_prio[0x1]; 300 u8 inner_first_cfi[0x1]; 301 u8 inner_first_vid[0x1]; 302 u8 reserved_at_27[0x1]; 303 u8 inner_second_prio[0x1]; 304 u8 inner_second_cfi[0x1]; 305 u8 inner_second_vid[0x1]; 306 u8 reserved_at_2b[0x1]; 307 u8 inner_sip[0x1]; 308 u8 inner_dip[0x1]; 309 u8 inner_frag[0x1]; 310 u8 inner_ip_protocol[0x1]; 311 u8 inner_ip_ecn[0x1]; 312 u8 inner_ip_dscp[0x1]; 313 u8 inner_udp_sport[0x1]; 314 u8 inner_udp_dport[0x1]; 315 u8 inner_tcp_sport[0x1]; 316 u8 inner_tcp_dport[0x1]; 317 u8 inner_tcp_flags[0x1]; 318 u8 reserved_at_37[0x9]; 319 320 u8 reserved_at_40[0x5]; 321 u8 outer_first_mpls_over_udp[0x4]; 322 u8 outer_first_mpls_over_gre[0x4]; 323 u8 inner_first_mpls[0x4]; 324 u8 outer_first_mpls[0x4]; 325 u8 reserved_at_55[0x2]; 326 u8 outer_esp_spi[0x1]; 327 u8 reserved_at_58[0x2]; 328 u8 bth_dst_qp[0x1]; 329 330 u8 reserved_at_5b[0x25]; 331 }; 332 333 struct mlx5_ifc_flow_table_prop_layout_bits { 334 u8 ft_support[0x1]; 335 u8 reserved_at_1[0x1]; 336 u8 flow_counter[0x1]; 337 u8 flow_modify_en[0x1]; 338 u8 modify_root[0x1]; 339 u8 identified_miss_table_mode[0x1]; 340 u8 flow_table_modify[0x1]; 341 u8 reformat[0x1]; 342 u8 decap[0x1]; 343 u8 reserved_at_9[0x1]; 344 u8 pop_vlan[0x1]; 345 u8 push_vlan[0x1]; 346 u8 reserved_at_c[0x1]; 347 u8 pop_vlan_2[0x1]; 348 u8 push_vlan_2[0x1]; 349 u8 reformat_and_vlan_action[0x1]; 350 u8 reserved_at_10[0x2]; 351 u8 reformat_l3_tunnel_to_l2[0x1]; 352 u8 reformat_l2_to_l3_tunnel[0x1]; 353 u8 reformat_and_modify_action[0x1]; 354 u8 reserved_at_15[0xb]; 355 u8 reserved_at_20[0x2]; 356 u8 log_max_ft_size[0x6]; 357 u8 log_max_modify_header_context[0x8]; 358 u8 max_modify_header_actions[0x8]; 359 u8 max_ft_level[0x8]; 360 361 u8 reserved_at_40[0x20]; 362 363 u8 reserved_at_60[0x18]; 364 u8 log_max_ft_num[0x8]; 365 366 u8 reserved_at_80[0x18]; 367 u8 log_max_destination[0x8]; 368 369 u8 log_max_flow_counter[0x8]; 370 u8 reserved_at_a8[0x10]; 371 u8 log_max_flow[0x8]; 372 373 u8 reserved_at_c0[0x40]; 374 375 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 376 377 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 378 }; 379 380 struct mlx5_ifc_odp_per_transport_service_cap_bits { 381 u8 send[0x1]; 382 u8 receive[0x1]; 383 u8 write[0x1]; 384 u8 read[0x1]; 385 u8 atomic[0x1]; 386 u8 srq_receive[0x1]; 387 u8 reserved_at_6[0x1a]; 388 }; 389 390 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 391 u8 smac_47_16[0x20]; 392 393 u8 smac_15_0[0x10]; 394 u8 ethertype[0x10]; 395 396 u8 dmac_47_16[0x20]; 397 398 u8 dmac_15_0[0x10]; 399 u8 first_prio[0x3]; 400 u8 first_cfi[0x1]; 401 u8 first_vid[0xc]; 402 403 u8 ip_protocol[0x8]; 404 u8 ip_dscp[0x6]; 405 u8 ip_ecn[0x2]; 406 u8 cvlan_tag[0x1]; 407 u8 svlan_tag[0x1]; 408 u8 frag[0x1]; 409 u8 ip_version[0x4]; 410 u8 tcp_flags[0x9]; 411 412 u8 tcp_sport[0x10]; 413 u8 tcp_dport[0x10]; 414 415 u8 reserved_at_c0[0x18]; 416 u8 ttl_hoplimit[0x8]; 417 418 u8 udp_sport[0x10]; 419 u8 udp_dport[0x10]; 420 421 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 422 423 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 424 }; 425 426 struct mlx5_ifc_nvgre_key_bits { 427 u8 hi[0x18]; 428 u8 lo[0x8]; 429 }; 430 431 union mlx5_ifc_gre_key_bits { 432 struct mlx5_ifc_nvgre_key_bits nvgre; 433 u8 key[0x20]; 434 }; 435 436 struct mlx5_ifc_fte_match_set_misc_bits { 437 u8 reserved_at_0[0x8]; 438 u8 source_sqn[0x18]; 439 440 u8 source_eswitch_owner_vhca_id[0x10]; 441 u8 source_port[0x10]; 442 443 u8 outer_second_prio[0x3]; 444 u8 outer_second_cfi[0x1]; 445 u8 outer_second_vid[0xc]; 446 u8 inner_second_prio[0x3]; 447 u8 inner_second_cfi[0x1]; 448 u8 inner_second_vid[0xc]; 449 450 u8 outer_second_cvlan_tag[0x1]; 451 u8 inner_second_cvlan_tag[0x1]; 452 u8 outer_second_svlan_tag[0x1]; 453 u8 inner_second_svlan_tag[0x1]; 454 u8 reserved_at_64[0xc]; 455 u8 gre_protocol[0x10]; 456 457 union mlx5_ifc_gre_key_bits gre_key; 458 459 u8 vxlan_vni[0x18]; 460 u8 reserved_at_b8[0x8]; 461 462 u8 reserved_at_c0[0x20]; 463 464 u8 reserved_at_e0[0xc]; 465 u8 outer_ipv6_flow_label[0x14]; 466 467 u8 reserved_at_100[0xc]; 468 u8 inner_ipv6_flow_label[0x14]; 469 470 u8 reserved_at_120[0x28]; 471 u8 bth_dst_qp[0x18]; 472 u8 reserved_at_160[0x20]; 473 u8 outer_esp_spi[0x20]; 474 u8 reserved_at_1a0[0x60]; 475 }; 476 477 struct mlx5_ifc_fte_match_mpls_bits { 478 u8 mpls_label[0x14]; 479 u8 mpls_exp[0x3]; 480 u8 mpls_s_bos[0x1]; 481 u8 mpls_ttl[0x8]; 482 }; 483 484 struct mlx5_ifc_fte_match_set_misc2_bits { 485 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 486 487 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 488 489 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 490 491 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 492 493 u8 reserved_at_80[0x100]; 494 495 u8 metadata_reg_a[0x20]; 496 497 u8 reserved_at_1a0[0x60]; 498 }; 499 500 struct mlx5_ifc_cmd_pas_bits { 501 u8 pa_h[0x20]; 502 503 u8 pa_l[0x14]; 504 u8 reserved_at_34[0xc]; 505 }; 506 507 struct mlx5_ifc_uint64_bits { 508 u8 hi[0x20]; 509 510 u8 lo[0x20]; 511 }; 512 513 enum { 514 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 515 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 516 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 517 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 518 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 519 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 520 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 521 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 522 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 523 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 524 }; 525 526 struct mlx5_ifc_ads_bits { 527 u8 fl[0x1]; 528 u8 free_ar[0x1]; 529 u8 reserved_at_2[0xe]; 530 u8 pkey_index[0x10]; 531 532 u8 reserved_at_20[0x8]; 533 u8 grh[0x1]; 534 u8 mlid[0x7]; 535 u8 rlid[0x10]; 536 537 u8 ack_timeout[0x5]; 538 u8 reserved_at_45[0x3]; 539 u8 src_addr_index[0x8]; 540 u8 reserved_at_50[0x4]; 541 u8 stat_rate[0x4]; 542 u8 hop_limit[0x8]; 543 544 u8 reserved_at_60[0x4]; 545 u8 tclass[0x8]; 546 u8 flow_label[0x14]; 547 548 u8 rgid_rip[16][0x8]; 549 550 u8 reserved_at_100[0x4]; 551 u8 f_dscp[0x1]; 552 u8 f_ecn[0x1]; 553 u8 reserved_at_106[0x1]; 554 u8 f_eth_prio[0x1]; 555 u8 ecn[0x2]; 556 u8 dscp[0x6]; 557 u8 udp_sport[0x10]; 558 559 u8 dei_cfi[0x1]; 560 u8 eth_prio[0x3]; 561 u8 sl[0x4]; 562 u8 vhca_port_num[0x8]; 563 u8 rmac_47_32[0x10]; 564 565 u8 rmac_31_0[0x20]; 566 }; 567 568 struct mlx5_ifc_flow_table_nic_cap_bits { 569 u8 nic_rx_multi_path_tirs[0x1]; 570 u8 nic_rx_multi_path_tirs_fts[0x1]; 571 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 572 u8 reserved_at_3[0x1d]; 573 u8 encap_general_header[0x1]; 574 u8 reserved_at_21[0xa]; 575 u8 log_max_packet_reformat_context[0x5]; 576 u8 reserved_at_30[0x6]; 577 u8 max_encap_header_size[0xa]; 578 u8 reserved_at_40[0x1c0]; 579 580 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 581 582 u8 reserved_at_400[0x200]; 583 584 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 585 586 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 587 588 u8 reserved_at_a00[0x200]; 589 590 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 591 592 u8 reserved_at_e00[0x7200]; 593 }; 594 595 struct mlx5_ifc_flow_table_eswitch_cap_bits { 596 u8 reserved_at_0[0x1c]; 597 u8 fdb_multi_path_to_table[0x1]; 598 u8 reserved_at_1d[0x1]; 599 u8 multi_fdb_encap[0x1]; 600 u8 reserved_at_1f[0x1e1]; 601 602 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 603 604 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 605 606 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 607 608 u8 reserved_at_800[0x7800]; 609 }; 610 611 enum { 612 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 613 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 614 }; 615 616 struct mlx5_ifc_e_switch_cap_bits { 617 u8 vport_svlan_strip[0x1]; 618 u8 vport_cvlan_strip[0x1]; 619 u8 vport_svlan_insert[0x1]; 620 u8 vport_cvlan_insert_if_not_exist[0x1]; 621 u8 vport_cvlan_insert_overwrite[0x1]; 622 u8 reserved_at_5[0x17]; 623 u8 counter_eswitch_affinity[0x1]; 624 u8 merged_eswitch[0x1]; 625 u8 nic_vport_node_guid_modify[0x1]; 626 u8 nic_vport_port_guid_modify[0x1]; 627 628 u8 vxlan_encap_decap[0x1]; 629 u8 nvgre_encap_decap[0x1]; 630 u8 reserved_at_22[0x1]; 631 u8 log_max_fdb_encap_uplink[0x5]; 632 u8 reserved_at_21[0x3]; 633 u8 log_max_packet_reformat_context[0x5]; 634 u8 reserved_2b[0x6]; 635 u8 max_encap_header_size[0xa]; 636 637 u8 reserved_40[0x7c0]; 638 639 }; 640 641 struct mlx5_ifc_qos_cap_bits { 642 u8 packet_pacing[0x1]; 643 u8 esw_scheduling[0x1]; 644 u8 esw_bw_share[0x1]; 645 u8 esw_rate_limit[0x1]; 646 u8 reserved_at_4[0x1]; 647 u8 packet_pacing_burst_bound[0x1]; 648 u8 packet_pacing_typical_size[0x1]; 649 u8 reserved_at_7[0x19]; 650 651 u8 reserved_at_20[0x20]; 652 653 u8 packet_pacing_max_rate[0x20]; 654 655 u8 packet_pacing_min_rate[0x20]; 656 657 u8 reserved_at_80[0x10]; 658 u8 packet_pacing_rate_table_size[0x10]; 659 660 u8 esw_element_type[0x10]; 661 u8 esw_tsar_type[0x10]; 662 663 u8 reserved_at_c0[0x10]; 664 u8 max_qos_para_vport[0x10]; 665 666 u8 max_tsar_bw_share[0x20]; 667 668 u8 reserved_at_100[0x700]; 669 }; 670 671 struct mlx5_ifc_debug_cap_bits { 672 u8 reserved_at_0[0x20]; 673 674 u8 reserved_at_20[0x2]; 675 u8 stall_detect[0x1]; 676 u8 reserved_at_23[0x1d]; 677 678 u8 reserved_at_40[0x7c0]; 679 }; 680 681 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 682 u8 csum_cap[0x1]; 683 u8 vlan_cap[0x1]; 684 u8 lro_cap[0x1]; 685 u8 lro_psh_flag[0x1]; 686 u8 lro_time_stamp[0x1]; 687 u8 reserved_at_5[0x2]; 688 u8 wqe_vlan_insert[0x1]; 689 u8 self_lb_en_modifiable[0x1]; 690 u8 reserved_at_9[0x2]; 691 u8 max_lso_cap[0x5]; 692 u8 multi_pkt_send_wqe[0x2]; 693 u8 wqe_inline_mode[0x2]; 694 u8 rss_ind_tbl_cap[0x4]; 695 u8 reg_umr_sq[0x1]; 696 u8 scatter_fcs[0x1]; 697 u8 enhanced_multi_pkt_send_wqe[0x1]; 698 u8 tunnel_lso_const_out_ip_id[0x1]; 699 u8 reserved_at_1c[0x2]; 700 u8 tunnel_stateless_gre[0x1]; 701 u8 tunnel_stateless_vxlan[0x1]; 702 703 u8 swp[0x1]; 704 u8 swp_csum[0x1]; 705 u8 swp_lso[0x1]; 706 u8 reserved_at_23[0xd]; 707 u8 max_vxlan_udp_ports[0x8]; 708 u8 reserved_at_38[0x6]; 709 u8 max_geneve_opt_len[0x1]; 710 u8 tunnel_stateless_geneve_rx[0x1]; 711 712 u8 reserved_at_40[0x10]; 713 u8 lro_min_mss_size[0x10]; 714 715 u8 reserved_at_60[0x120]; 716 717 u8 lro_timer_supported_periods[4][0x20]; 718 719 u8 reserved_at_200[0x600]; 720 }; 721 722 struct mlx5_ifc_roce_cap_bits { 723 u8 roce_apm[0x1]; 724 u8 reserved_at_1[0x1f]; 725 726 u8 reserved_at_20[0x60]; 727 728 u8 reserved_at_80[0xc]; 729 u8 l3_type[0x4]; 730 u8 reserved_at_90[0x8]; 731 u8 roce_version[0x8]; 732 733 u8 reserved_at_a0[0x10]; 734 u8 r_roce_dest_udp_port[0x10]; 735 736 u8 r_roce_max_src_udp_port[0x10]; 737 u8 r_roce_min_src_udp_port[0x10]; 738 739 u8 reserved_at_e0[0x10]; 740 u8 roce_address_table_size[0x10]; 741 742 u8 reserved_at_100[0x700]; 743 }; 744 745 struct mlx5_ifc_device_mem_cap_bits { 746 u8 memic[0x1]; 747 u8 reserved_at_1[0x1f]; 748 749 u8 reserved_at_20[0xb]; 750 u8 log_min_memic_alloc_size[0x5]; 751 u8 reserved_at_30[0x8]; 752 u8 log_max_memic_addr_alignment[0x8]; 753 754 u8 memic_bar_start_addr[0x40]; 755 756 u8 memic_bar_size[0x20]; 757 758 u8 max_memic_size[0x20]; 759 760 u8 reserved_at_c0[0x740]; 761 }; 762 763 enum { 764 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 765 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 766 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 767 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 768 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 769 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 770 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 771 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 772 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 773 }; 774 775 enum { 776 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 777 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 778 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 779 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 780 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 781 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 782 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 783 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 784 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 785 }; 786 787 struct mlx5_ifc_atomic_caps_bits { 788 u8 reserved_at_0[0x40]; 789 790 u8 atomic_req_8B_endianness_mode[0x2]; 791 u8 reserved_at_42[0x4]; 792 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 793 794 u8 reserved_at_47[0x19]; 795 796 u8 reserved_at_60[0x20]; 797 798 u8 reserved_at_80[0x10]; 799 u8 atomic_operations[0x10]; 800 801 u8 reserved_at_a0[0x10]; 802 u8 atomic_size_qp[0x10]; 803 804 u8 reserved_at_c0[0x10]; 805 u8 atomic_size_dc[0x10]; 806 807 u8 reserved_at_e0[0x720]; 808 }; 809 810 struct mlx5_ifc_odp_cap_bits { 811 u8 reserved_at_0[0x40]; 812 813 u8 sig[0x1]; 814 u8 reserved_at_41[0x1f]; 815 816 u8 reserved_at_60[0x20]; 817 818 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 819 820 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 821 822 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 823 824 u8 reserved_at_e0[0x720]; 825 }; 826 827 struct mlx5_ifc_calc_op { 828 u8 reserved_at_0[0x10]; 829 u8 reserved_at_10[0x9]; 830 u8 op_swap_endianness[0x1]; 831 u8 op_min[0x1]; 832 u8 op_xor[0x1]; 833 u8 op_or[0x1]; 834 u8 op_and[0x1]; 835 u8 op_max[0x1]; 836 u8 op_add[0x1]; 837 }; 838 839 struct mlx5_ifc_vector_calc_cap_bits { 840 u8 calc_matrix[0x1]; 841 u8 reserved_at_1[0x1f]; 842 u8 reserved_at_20[0x8]; 843 u8 max_vec_count[0x8]; 844 u8 reserved_at_30[0xd]; 845 u8 max_chunk_size[0x3]; 846 struct mlx5_ifc_calc_op calc0; 847 struct mlx5_ifc_calc_op calc1; 848 struct mlx5_ifc_calc_op calc2; 849 struct mlx5_ifc_calc_op calc3; 850 851 u8 reserved_at_c0[0x720]; 852 }; 853 854 enum { 855 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 856 MLX5_WQ_TYPE_CYCLIC = 0x1, 857 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 858 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 859 }; 860 861 enum { 862 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 863 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 864 }; 865 866 enum { 867 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 868 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 869 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 870 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 871 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 872 }; 873 874 enum { 875 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 876 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 877 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 878 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 879 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 880 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 881 }; 882 883 enum { 884 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 885 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 886 }; 887 888 enum { 889 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 890 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 891 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 892 }; 893 894 enum { 895 MLX5_CAP_PORT_TYPE_IB = 0x0, 896 MLX5_CAP_PORT_TYPE_ETH = 0x1, 897 }; 898 899 enum { 900 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 901 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 902 MLX5_CAP_UMR_FENCE_NONE = 0x2, 903 }; 904 905 enum { 906 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 907 }; 908 909 struct mlx5_ifc_cmd_hca_cap_bits { 910 u8 reserved_at_0[0x30]; 911 u8 vhca_id[0x10]; 912 913 u8 reserved_at_40[0x40]; 914 915 u8 log_max_srq_sz[0x8]; 916 u8 log_max_qp_sz[0x8]; 917 u8 reserved_at_90[0xb]; 918 u8 log_max_qp[0x5]; 919 920 u8 reserved_at_a0[0xb]; 921 u8 log_max_srq[0x5]; 922 u8 reserved_at_b0[0x10]; 923 924 u8 reserved_at_c0[0x8]; 925 u8 log_max_cq_sz[0x8]; 926 u8 reserved_at_d0[0xb]; 927 u8 log_max_cq[0x5]; 928 929 u8 log_max_eq_sz[0x8]; 930 u8 reserved_at_e8[0x2]; 931 u8 log_max_mkey[0x6]; 932 u8 reserved_at_f0[0x8]; 933 u8 dump_fill_mkey[0x1]; 934 u8 reserved_at_f9[0x2]; 935 u8 fast_teardown[0x1]; 936 u8 log_max_eq[0x4]; 937 938 u8 max_indirection[0x8]; 939 u8 fixed_buffer_size[0x1]; 940 u8 log_max_mrw_sz[0x7]; 941 u8 force_teardown[0x1]; 942 u8 reserved_at_111[0x1]; 943 u8 log_max_bsf_list_size[0x6]; 944 u8 umr_extended_translation_offset[0x1]; 945 u8 null_mkey[0x1]; 946 u8 log_max_klm_list_size[0x6]; 947 948 u8 reserved_at_120[0xa]; 949 u8 log_max_ra_req_dc[0x6]; 950 u8 reserved_at_130[0xa]; 951 u8 log_max_ra_res_dc[0x6]; 952 953 u8 reserved_at_140[0xa]; 954 u8 log_max_ra_req_qp[0x6]; 955 u8 reserved_at_150[0xa]; 956 u8 log_max_ra_res_qp[0x6]; 957 958 u8 end_pad[0x1]; 959 u8 cc_query_allowed[0x1]; 960 u8 cc_modify_allowed[0x1]; 961 u8 start_pad[0x1]; 962 u8 cache_line_128byte[0x1]; 963 u8 reserved_at_165[0xa]; 964 u8 qcam_reg[0x1]; 965 u8 gid_table_size[0x10]; 966 967 u8 out_of_seq_cnt[0x1]; 968 u8 vport_counters[0x1]; 969 u8 retransmission_q_counters[0x1]; 970 u8 debug[0x1]; 971 u8 modify_rq_counter_set_id[0x1]; 972 u8 rq_delay_drop[0x1]; 973 u8 max_qp_cnt[0xa]; 974 u8 pkey_table_size[0x10]; 975 976 u8 vport_group_manager[0x1]; 977 u8 vhca_group_manager[0x1]; 978 u8 ib_virt[0x1]; 979 u8 eth_virt[0x1]; 980 u8 vnic_env_queue_counters[0x1]; 981 u8 ets[0x1]; 982 u8 nic_flow_table[0x1]; 983 u8 eswitch_manager[0x1]; 984 u8 device_memory[0x1]; 985 u8 mcam_reg[0x1]; 986 u8 pcam_reg[0x1]; 987 u8 local_ca_ack_delay[0x5]; 988 u8 port_module_event[0x1]; 989 u8 enhanced_error_q_counters[0x1]; 990 u8 ports_check[0x1]; 991 u8 reserved_at_1b3[0x1]; 992 u8 disable_link_up[0x1]; 993 u8 beacon_led[0x1]; 994 u8 port_type[0x2]; 995 u8 num_ports[0x8]; 996 997 u8 reserved_at_1c0[0x1]; 998 u8 pps[0x1]; 999 u8 pps_modify[0x1]; 1000 u8 log_max_msg[0x5]; 1001 u8 reserved_at_1c8[0x4]; 1002 u8 max_tc[0x4]; 1003 u8 temp_warn_event[0x1]; 1004 u8 dcbx[0x1]; 1005 u8 general_notification_event[0x1]; 1006 u8 reserved_at_1d3[0x2]; 1007 u8 fpga[0x1]; 1008 u8 rol_s[0x1]; 1009 u8 rol_g[0x1]; 1010 u8 reserved_at_1d8[0x1]; 1011 u8 wol_s[0x1]; 1012 u8 wol_g[0x1]; 1013 u8 wol_a[0x1]; 1014 u8 wol_b[0x1]; 1015 u8 wol_m[0x1]; 1016 u8 wol_u[0x1]; 1017 u8 wol_p[0x1]; 1018 1019 u8 stat_rate_support[0x10]; 1020 u8 reserved_at_1f0[0xc]; 1021 u8 cqe_version[0x4]; 1022 1023 u8 compact_address_vector[0x1]; 1024 u8 striding_rq[0x1]; 1025 u8 reserved_at_202[0x1]; 1026 u8 ipoib_enhanced_offloads[0x1]; 1027 u8 ipoib_basic_offloads[0x1]; 1028 u8 reserved_at_205[0x1]; 1029 u8 repeated_block_disabled[0x1]; 1030 u8 umr_modify_entity_size_disabled[0x1]; 1031 u8 umr_modify_atomic_disabled[0x1]; 1032 u8 umr_indirect_mkey_disabled[0x1]; 1033 u8 umr_fence[0x2]; 1034 u8 dc_req_scat_data_cqe[0x1]; 1035 u8 reserved_at_20d[0x2]; 1036 u8 drain_sigerr[0x1]; 1037 u8 cmdif_checksum[0x2]; 1038 u8 sigerr_cqe[0x1]; 1039 u8 reserved_at_213[0x1]; 1040 u8 wq_signature[0x1]; 1041 u8 sctr_data_cqe[0x1]; 1042 u8 reserved_at_216[0x1]; 1043 u8 sho[0x1]; 1044 u8 tph[0x1]; 1045 u8 rf[0x1]; 1046 u8 dct[0x1]; 1047 u8 qos[0x1]; 1048 u8 eth_net_offloads[0x1]; 1049 u8 roce[0x1]; 1050 u8 atomic[0x1]; 1051 u8 reserved_at_21f[0x1]; 1052 1053 u8 cq_oi[0x1]; 1054 u8 cq_resize[0x1]; 1055 u8 cq_moderation[0x1]; 1056 u8 reserved_at_223[0x3]; 1057 u8 cq_eq_remap[0x1]; 1058 u8 pg[0x1]; 1059 u8 block_lb_mc[0x1]; 1060 u8 reserved_at_229[0x1]; 1061 u8 scqe_break_moderation[0x1]; 1062 u8 cq_period_start_from_cqe[0x1]; 1063 u8 cd[0x1]; 1064 u8 reserved_at_22d[0x1]; 1065 u8 apm[0x1]; 1066 u8 vector_calc[0x1]; 1067 u8 umr_ptr_rlky[0x1]; 1068 u8 imaicl[0x1]; 1069 u8 qp_packet_based[0x1]; 1070 u8 reserved_at_233[0x3]; 1071 u8 qkv[0x1]; 1072 u8 pkv[0x1]; 1073 u8 set_deth_sqpn[0x1]; 1074 u8 reserved_at_239[0x3]; 1075 u8 xrc[0x1]; 1076 u8 ud[0x1]; 1077 u8 uc[0x1]; 1078 u8 rc[0x1]; 1079 1080 u8 uar_4k[0x1]; 1081 u8 reserved_at_241[0x9]; 1082 u8 uar_sz[0x6]; 1083 u8 reserved_at_250[0x8]; 1084 u8 log_pg_sz[0x8]; 1085 1086 u8 bf[0x1]; 1087 u8 driver_version[0x1]; 1088 u8 pad_tx_eth_packet[0x1]; 1089 u8 reserved_at_263[0x8]; 1090 u8 log_bf_reg_size[0x5]; 1091 1092 u8 reserved_at_270[0xb]; 1093 u8 lag_master[0x1]; 1094 u8 num_lag_ports[0x4]; 1095 1096 u8 reserved_at_280[0x10]; 1097 u8 max_wqe_sz_sq[0x10]; 1098 1099 u8 reserved_at_2a0[0x10]; 1100 u8 max_wqe_sz_rq[0x10]; 1101 1102 u8 max_flow_counter_31_16[0x10]; 1103 u8 max_wqe_sz_sq_dc[0x10]; 1104 1105 u8 reserved_at_2e0[0x7]; 1106 u8 max_qp_mcg[0x19]; 1107 1108 u8 reserved_at_300[0x18]; 1109 u8 log_max_mcg[0x8]; 1110 1111 u8 reserved_at_320[0x3]; 1112 u8 log_max_transport_domain[0x5]; 1113 u8 reserved_at_328[0x3]; 1114 u8 log_max_pd[0x5]; 1115 u8 reserved_at_330[0xb]; 1116 u8 log_max_xrcd[0x5]; 1117 1118 u8 nic_receive_steering_discard[0x1]; 1119 u8 receive_discard_vport_down[0x1]; 1120 u8 transmit_discard_vport_down[0x1]; 1121 u8 reserved_at_343[0x5]; 1122 u8 log_max_flow_counter_bulk[0x8]; 1123 u8 max_flow_counter_15_0[0x10]; 1124 1125 1126 u8 reserved_at_360[0x3]; 1127 u8 log_max_rq[0x5]; 1128 u8 reserved_at_368[0x3]; 1129 u8 log_max_sq[0x5]; 1130 u8 reserved_at_370[0x3]; 1131 u8 log_max_tir[0x5]; 1132 u8 reserved_at_378[0x3]; 1133 u8 log_max_tis[0x5]; 1134 1135 u8 basic_cyclic_rcv_wqe[0x1]; 1136 u8 reserved_at_381[0x2]; 1137 u8 log_max_rmp[0x5]; 1138 u8 reserved_at_388[0x3]; 1139 u8 log_max_rqt[0x5]; 1140 u8 reserved_at_390[0x3]; 1141 u8 log_max_rqt_size[0x5]; 1142 u8 reserved_at_398[0x3]; 1143 u8 log_max_tis_per_sq[0x5]; 1144 1145 u8 ext_stride_num_range[0x1]; 1146 u8 reserved_at_3a1[0x2]; 1147 u8 log_max_stride_sz_rq[0x5]; 1148 u8 reserved_at_3a8[0x3]; 1149 u8 log_min_stride_sz_rq[0x5]; 1150 u8 reserved_at_3b0[0x3]; 1151 u8 log_max_stride_sz_sq[0x5]; 1152 u8 reserved_at_3b8[0x3]; 1153 u8 log_min_stride_sz_sq[0x5]; 1154 1155 u8 hairpin[0x1]; 1156 u8 reserved_at_3c1[0x2]; 1157 u8 log_max_hairpin_queues[0x5]; 1158 u8 reserved_at_3c8[0x3]; 1159 u8 log_max_hairpin_wq_data_sz[0x5]; 1160 u8 reserved_at_3d0[0x3]; 1161 u8 log_max_hairpin_num_packets[0x5]; 1162 u8 reserved_at_3d8[0x3]; 1163 u8 log_max_wq_sz[0x5]; 1164 1165 u8 nic_vport_change_event[0x1]; 1166 u8 disable_local_lb_uc[0x1]; 1167 u8 disable_local_lb_mc[0x1]; 1168 u8 log_min_hairpin_wq_data_sz[0x5]; 1169 u8 reserved_at_3e8[0x3]; 1170 u8 log_max_vlan_list[0x5]; 1171 u8 reserved_at_3f0[0x3]; 1172 u8 log_max_current_mc_list[0x5]; 1173 u8 reserved_at_3f8[0x3]; 1174 u8 log_max_current_uc_list[0x5]; 1175 1176 u8 general_obj_types[0x40]; 1177 1178 u8 reserved_at_440[0x20]; 1179 1180 u8 reserved_at_460[0x10]; 1181 u8 max_num_eqs[0x10]; 1182 1183 u8 reserved_at_480[0x3]; 1184 u8 log_max_l2_table[0x5]; 1185 u8 reserved_at_488[0x8]; 1186 u8 log_uar_page_sz[0x10]; 1187 1188 u8 reserved_at_4a0[0x20]; 1189 u8 device_frequency_mhz[0x20]; 1190 u8 device_frequency_khz[0x20]; 1191 1192 u8 reserved_at_500[0x20]; 1193 u8 num_of_uars_per_page[0x20]; 1194 1195 u8 flex_parser_protocols[0x20]; 1196 u8 reserved_at_560[0x20]; 1197 1198 u8 reserved_at_580[0x3c]; 1199 u8 mini_cqe_resp_stride_index[0x1]; 1200 u8 cqe_128_always[0x1]; 1201 u8 cqe_compression_128[0x1]; 1202 u8 cqe_compression[0x1]; 1203 1204 u8 cqe_compression_timeout[0x10]; 1205 u8 cqe_compression_max_num[0x10]; 1206 1207 u8 reserved_at_5e0[0x10]; 1208 u8 tag_matching[0x1]; 1209 u8 rndv_offload_rc[0x1]; 1210 u8 rndv_offload_dc[0x1]; 1211 u8 log_tag_matching_list_sz[0x5]; 1212 u8 reserved_at_5f8[0x3]; 1213 u8 log_max_xrq[0x5]; 1214 1215 u8 affiliate_nic_vport_criteria[0x8]; 1216 u8 native_port_num[0x8]; 1217 u8 num_vhca_ports[0x8]; 1218 u8 reserved_at_618[0x6]; 1219 u8 sw_owner_id[0x1]; 1220 u8 reserved_at_61f[0x1]; 1221 1222 u8 max_num_of_monitor_counters[0x10]; 1223 u8 num_ppcnt_monitor_counters[0x10]; 1224 1225 u8 reserved_at_640[0x10]; 1226 u8 num_q_monitor_counters[0x10]; 1227 1228 u8 reserved_at_660[0x40]; 1229 1230 u8 uctx_cap[0x20]; 1231 1232 u8 reserved_at_6c0[0x140]; 1233 }; 1234 1235 enum mlx5_flow_destination_type { 1236 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1237 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1238 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1239 1240 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1241 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1242 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1243 }; 1244 1245 struct mlx5_ifc_dest_format_struct_bits { 1246 u8 destination_type[0x8]; 1247 u8 destination_id[0x18]; 1248 1249 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1250 u8 packet_reformat[0x1]; 1251 u8 reserved_at_22[0xe]; 1252 u8 destination_eswitch_owner_vhca_id[0x10]; 1253 }; 1254 1255 struct mlx5_ifc_flow_counter_list_bits { 1256 u8 flow_counter_id[0x20]; 1257 1258 u8 reserved_at_20[0x20]; 1259 }; 1260 1261 struct mlx5_ifc_extended_dest_format_bits { 1262 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1263 1264 u8 packet_reformat_id[0x20]; 1265 1266 u8 reserved_at_60[0x20]; 1267 }; 1268 1269 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1270 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1271 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1272 u8 reserved_at_0[0x40]; 1273 }; 1274 1275 struct mlx5_ifc_fte_match_param_bits { 1276 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1277 1278 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1279 1280 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1281 1282 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1283 1284 u8 reserved_at_800[0x800]; 1285 }; 1286 1287 enum { 1288 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1289 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1290 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1291 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1292 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1293 }; 1294 1295 struct mlx5_ifc_rx_hash_field_select_bits { 1296 u8 l3_prot_type[0x1]; 1297 u8 l4_prot_type[0x1]; 1298 u8 selected_fields[0x1e]; 1299 }; 1300 1301 enum { 1302 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1303 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1304 }; 1305 1306 enum { 1307 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1308 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1309 }; 1310 1311 struct mlx5_ifc_wq_bits { 1312 u8 wq_type[0x4]; 1313 u8 wq_signature[0x1]; 1314 u8 end_padding_mode[0x2]; 1315 u8 cd_slave[0x1]; 1316 u8 reserved_at_8[0x18]; 1317 1318 u8 hds_skip_first_sge[0x1]; 1319 u8 log2_hds_buf_size[0x3]; 1320 u8 reserved_at_24[0x7]; 1321 u8 page_offset[0x5]; 1322 u8 lwm[0x10]; 1323 1324 u8 reserved_at_40[0x8]; 1325 u8 pd[0x18]; 1326 1327 u8 reserved_at_60[0x8]; 1328 u8 uar_page[0x18]; 1329 1330 u8 dbr_addr[0x40]; 1331 1332 u8 hw_counter[0x20]; 1333 1334 u8 sw_counter[0x20]; 1335 1336 u8 reserved_at_100[0xc]; 1337 u8 log_wq_stride[0x4]; 1338 u8 reserved_at_110[0x3]; 1339 u8 log_wq_pg_sz[0x5]; 1340 u8 reserved_at_118[0x3]; 1341 u8 log_wq_sz[0x5]; 1342 1343 u8 dbr_umem_valid[0x1]; 1344 u8 wq_umem_valid[0x1]; 1345 u8 reserved_at_122[0x1]; 1346 u8 log_hairpin_num_packets[0x5]; 1347 u8 reserved_at_128[0x3]; 1348 u8 log_hairpin_data_sz[0x5]; 1349 1350 u8 reserved_at_130[0x4]; 1351 u8 log_wqe_num_of_strides[0x4]; 1352 u8 two_byte_shift_en[0x1]; 1353 u8 reserved_at_139[0x4]; 1354 u8 log_wqe_stride_size[0x3]; 1355 1356 u8 reserved_at_140[0x4c0]; 1357 1358 struct mlx5_ifc_cmd_pas_bits pas[0]; 1359 }; 1360 1361 struct mlx5_ifc_rq_num_bits { 1362 u8 reserved_at_0[0x8]; 1363 u8 rq_num[0x18]; 1364 }; 1365 1366 struct mlx5_ifc_mac_address_layout_bits { 1367 u8 reserved_at_0[0x10]; 1368 u8 mac_addr_47_32[0x10]; 1369 1370 u8 mac_addr_31_0[0x20]; 1371 }; 1372 1373 struct mlx5_ifc_vlan_layout_bits { 1374 u8 reserved_at_0[0x14]; 1375 u8 vlan[0x0c]; 1376 1377 u8 reserved_at_20[0x20]; 1378 }; 1379 1380 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1381 u8 reserved_at_0[0xa0]; 1382 1383 u8 min_time_between_cnps[0x20]; 1384 1385 u8 reserved_at_c0[0x12]; 1386 u8 cnp_dscp[0x6]; 1387 u8 reserved_at_d8[0x4]; 1388 u8 cnp_prio_mode[0x1]; 1389 u8 cnp_802p_prio[0x3]; 1390 1391 u8 reserved_at_e0[0x720]; 1392 }; 1393 1394 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1395 u8 reserved_at_0[0x60]; 1396 1397 u8 reserved_at_60[0x4]; 1398 u8 clamp_tgt_rate[0x1]; 1399 u8 reserved_at_65[0x3]; 1400 u8 clamp_tgt_rate_after_time_inc[0x1]; 1401 u8 reserved_at_69[0x17]; 1402 1403 u8 reserved_at_80[0x20]; 1404 1405 u8 rpg_time_reset[0x20]; 1406 1407 u8 rpg_byte_reset[0x20]; 1408 1409 u8 rpg_threshold[0x20]; 1410 1411 u8 rpg_max_rate[0x20]; 1412 1413 u8 rpg_ai_rate[0x20]; 1414 1415 u8 rpg_hai_rate[0x20]; 1416 1417 u8 rpg_gd[0x20]; 1418 1419 u8 rpg_min_dec_fac[0x20]; 1420 1421 u8 rpg_min_rate[0x20]; 1422 1423 u8 reserved_at_1c0[0xe0]; 1424 1425 u8 rate_to_set_on_first_cnp[0x20]; 1426 1427 u8 dce_tcp_g[0x20]; 1428 1429 u8 dce_tcp_rtt[0x20]; 1430 1431 u8 rate_reduce_monitor_period[0x20]; 1432 1433 u8 reserved_at_320[0x20]; 1434 1435 u8 initial_alpha_value[0x20]; 1436 1437 u8 reserved_at_360[0x4a0]; 1438 }; 1439 1440 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1441 u8 reserved_at_0[0x80]; 1442 1443 u8 rppp_max_rps[0x20]; 1444 1445 u8 rpg_time_reset[0x20]; 1446 1447 u8 rpg_byte_reset[0x20]; 1448 1449 u8 rpg_threshold[0x20]; 1450 1451 u8 rpg_max_rate[0x20]; 1452 1453 u8 rpg_ai_rate[0x20]; 1454 1455 u8 rpg_hai_rate[0x20]; 1456 1457 u8 rpg_gd[0x20]; 1458 1459 u8 rpg_min_dec_fac[0x20]; 1460 1461 u8 rpg_min_rate[0x20]; 1462 1463 u8 reserved_at_1c0[0x640]; 1464 }; 1465 1466 enum { 1467 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1468 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1469 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1470 }; 1471 1472 struct mlx5_ifc_resize_field_select_bits { 1473 u8 resize_field_select[0x20]; 1474 }; 1475 1476 enum { 1477 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1478 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1479 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1480 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1481 }; 1482 1483 struct mlx5_ifc_modify_field_select_bits { 1484 u8 modify_field_select[0x20]; 1485 }; 1486 1487 struct mlx5_ifc_field_select_r_roce_np_bits { 1488 u8 field_select_r_roce_np[0x20]; 1489 }; 1490 1491 struct mlx5_ifc_field_select_r_roce_rp_bits { 1492 u8 field_select_r_roce_rp[0x20]; 1493 }; 1494 1495 enum { 1496 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1497 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1498 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1499 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1500 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1501 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1502 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1503 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1504 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1505 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1506 }; 1507 1508 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1509 u8 field_select_8021qaurp[0x20]; 1510 }; 1511 1512 struct mlx5_ifc_phys_layer_cntrs_bits { 1513 u8 time_since_last_clear_high[0x20]; 1514 1515 u8 time_since_last_clear_low[0x20]; 1516 1517 u8 symbol_errors_high[0x20]; 1518 1519 u8 symbol_errors_low[0x20]; 1520 1521 u8 sync_headers_errors_high[0x20]; 1522 1523 u8 sync_headers_errors_low[0x20]; 1524 1525 u8 edpl_bip_errors_lane0_high[0x20]; 1526 1527 u8 edpl_bip_errors_lane0_low[0x20]; 1528 1529 u8 edpl_bip_errors_lane1_high[0x20]; 1530 1531 u8 edpl_bip_errors_lane1_low[0x20]; 1532 1533 u8 edpl_bip_errors_lane2_high[0x20]; 1534 1535 u8 edpl_bip_errors_lane2_low[0x20]; 1536 1537 u8 edpl_bip_errors_lane3_high[0x20]; 1538 1539 u8 edpl_bip_errors_lane3_low[0x20]; 1540 1541 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1542 1543 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1544 1545 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1546 1547 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1548 1549 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1550 1551 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1552 1553 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1554 1555 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1556 1557 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1558 1559 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1560 1561 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1562 1563 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1564 1565 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1566 1567 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1568 1569 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1570 1571 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1572 1573 u8 rs_fec_corrected_blocks_high[0x20]; 1574 1575 u8 rs_fec_corrected_blocks_low[0x20]; 1576 1577 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1578 1579 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1580 1581 u8 rs_fec_no_errors_blocks_high[0x20]; 1582 1583 u8 rs_fec_no_errors_blocks_low[0x20]; 1584 1585 u8 rs_fec_single_error_blocks_high[0x20]; 1586 1587 u8 rs_fec_single_error_blocks_low[0x20]; 1588 1589 u8 rs_fec_corrected_symbols_total_high[0x20]; 1590 1591 u8 rs_fec_corrected_symbols_total_low[0x20]; 1592 1593 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1594 1595 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1596 1597 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1598 1599 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1600 1601 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1602 1603 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1604 1605 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1606 1607 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1608 1609 u8 link_down_events[0x20]; 1610 1611 u8 successful_recovery_events[0x20]; 1612 1613 u8 reserved_at_640[0x180]; 1614 }; 1615 1616 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1617 u8 time_since_last_clear_high[0x20]; 1618 1619 u8 time_since_last_clear_low[0x20]; 1620 1621 u8 phy_received_bits_high[0x20]; 1622 1623 u8 phy_received_bits_low[0x20]; 1624 1625 u8 phy_symbol_errors_high[0x20]; 1626 1627 u8 phy_symbol_errors_low[0x20]; 1628 1629 u8 phy_corrected_bits_high[0x20]; 1630 1631 u8 phy_corrected_bits_low[0x20]; 1632 1633 u8 phy_corrected_bits_lane0_high[0x20]; 1634 1635 u8 phy_corrected_bits_lane0_low[0x20]; 1636 1637 u8 phy_corrected_bits_lane1_high[0x20]; 1638 1639 u8 phy_corrected_bits_lane1_low[0x20]; 1640 1641 u8 phy_corrected_bits_lane2_high[0x20]; 1642 1643 u8 phy_corrected_bits_lane2_low[0x20]; 1644 1645 u8 phy_corrected_bits_lane3_high[0x20]; 1646 1647 u8 phy_corrected_bits_lane3_low[0x20]; 1648 1649 u8 reserved_at_200[0x5c0]; 1650 }; 1651 1652 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1653 u8 symbol_error_counter[0x10]; 1654 1655 u8 link_error_recovery_counter[0x8]; 1656 1657 u8 link_downed_counter[0x8]; 1658 1659 u8 port_rcv_errors[0x10]; 1660 1661 u8 port_rcv_remote_physical_errors[0x10]; 1662 1663 u8 port_rcv_switch_relay_errors[0x10]; 1664 1665 u8 port_xmit_discards[0x10]; 1666 1667 u8 port_xmit_constraint_errors[0x8]; 1668 1669 u8 port_rcv_constraint_errors[0x8]; 1670 1671 u8 reserved_at_70[0x8]; 1672 1673 u8 link_overrun_errors[0x8]; 1674 1675 u8 reserved_at_80[0x10]; 1676 1677 u8 vl_15_dropped[0x10]; 1678 1679 u8 reserved_at_a0[0x80]; 1680 1681 u8 port_xmit_wait[0x20]; 1682 }; 1683 1684 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1685 u8 transmit_queue_high[0x20]; 1686 1687 u8 transmit_queue_low[0x20]; 1688 1689 u8 reserved_at_40[0x780]; 1690 }; 1691 1692 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1693 u8 rx_octets_high[0x20]; 1694 1695 u8 rx_octets_low[0x20]; 1696 1697 u8 reserved_at_40[0xc0]; 1698 1699 u8 rx_frames_high[0x20]; 1700 1701 u8 rx_frames_low[0x20]; 1702 1703 u8 tx_octets_high[0x20]; 1704 1705 u8 tx_octets_low[0x20]; 1706 1707 u8 reserved_at_180[0xc0]; 1708 1709 u8 tx_frames_high[0x20]; 1710 1711 u8 tx_frames_low[0x20]; 1712 1713 u8 rx_pause_high[0x20]; 1714 1715 u8 rx_pause_low[0x20]; 1716 1717 u8 rx_pause_duration_high[0x20]; 1718 1719 u8 rx_pause_duration_low[0x20]; 1720 1721 u8 tx_pause_high[0x20]; 1722 1723 u8 tx_pause_low[0x20]; 1724 1725 u8 tx_pause_duration_high[0x20]; 1726 1727 u8 tx_pause_duration_low[0x20]; 1728 1729 u8 rx_pause_transition_high[0x20]; 1730 1731 u8 rx_pause_transition_low[0x20]; 1732 1733 u8 reserved_at_3c0[0x40]; 1734 1735 u8 device_stall_minor_watermark_cnt_high[0x20]; 1736 1737 u8 device_stall_minor_watermark_cnt_low[0x20]; 1738 1739 u8 device_stall_critical_watermark_cnt_high[0x20]; 1740 1741 u8 device_stall_critical_watermark_cnt_low[0x20]; 1742 1743 u8 reserved_at_480[0x340]; 1744 }; 1745 1746 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1747 u8 port_transmit_wait_high[0x20]; 1748 1749 u8 port_transmit_wait_low[0x20]; 1750 1751 u8 reserved_at_40[0x100]; 1752 1753 u8 rx_buffer_almost_full_high[0x20]; 1754 1755 u8 rx_buffer_almost_full_low[0x20]; 1756 1757 u8 rx_buffer_full_high[0x20]; 1758 1759 u8 rx_buffer_full_low[0x20]; 1760 1761 u8 rx_icrc_encapsulated_high[0x20]; 1762 1763 u8 rx_icrc_encapsulated_low[0x20]; 1764 1765 u8 reserved_at_200[0x5c0]; 1766 }; 1767 1768 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1769 u8 dot3stats_alignment_errors_high[0x20]; 1770 1771 u8 dot3stats_alignment_errors_low[0x20]; 1772 1773 u8 dot3stats_fcs_errors_high[0x20]; 1774 1775 u8 dot3stats_fcs_errors_low[0x20]; 1776 1777 u8 dot3stats_single_collision_frames_high[0x20]; 1778 1779 u8 dot3stats_single_collision_frames_low[0x20]; 1780 1781 u8 dot3stats_multiple_collision_frames_high[0x20]; 1782 1783 u8 dot3stats_multiple_collision_frames_low[0x20]; 1784 1785 u8 dot3stats_sqe_test_errors_high[0x20]; 1786 1787 u8 dot3stats_sqe_test_errors_low[0x20]; 1788 1789 u8 dot3stats_deferred_transmissions_high[0x20]; 1790 1791 u8 dot3stats_deferred_transmissions_low[0x20]; 1792 1793 u8 dot3stats_late_collisions_high[0x20]; 1794 1795 u8 dot3stats_late_collisions_low[0x20]; 1796 1797 u8 dot3stats_excessive_collisions_high[0x20]; 1798 1799 u8 dot3stats_excessive_collisions_low[0x20]; 1800 1801 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1802 1803 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1804 1805 u8 dot3stats_carrier_sense_errors_high[0x20]; 1806 1807 u8 dot3stats_carrier_sense_errors_low[0x20]; 1808 1809 u8 dot3stats_frame_too_longs_high[0x20]; 1810 1811 u8 dot3stats_frame_too_longs_low[0x20]; 1812 1813 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1814 1815 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1816 1817 u8 dot3stats_symbol_errors_high[0x20]; 1818 1819 u8 dot3stats_symbol_errors_low[0x20]; 1820 1821 u8 dot3control_in_unknown_opcodes_high[0x20]; 1822 1823 u8 dot3control_in_unknown_opcodes_low[0x20]; 1824 1825 u8 dot3in_pause_frames_high[0x20]; 1826 1827 u8 dot3in_pause_frames_low[0x20]; 1828 1829 u8 dot3out_pause_frames_high[0x20]; 1830 1831 u8 dot3out_pause_frames_low[0x20]; 1832 1833 u8 reserved_at_400[0x3c0]; 1834 }; 1835 1836 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1837 u8 ether_stats_drop_events_high[0x20]; 1838 1839 u8 ether_stats_drop_events_low[0x20]; 1840 1841 u8 ether_stats_octets_high[0x20]; 1842 1843 u8 ether_stats_octets_low[0x20]; 1844 1845 u8 ether_stats_pkts_high[0x20]; 1846 1847 u8 ether_stats_pkts_low[0x20]; 1848 1849 u8 ether_stats_broadcast_pkts_high[0x20]; 1850 1851 u8 ether_stats_broadcast_pkts_low[0x20]; 1852 1853 u8 ether_stats_multicast_pkts_high[0x20]; 1854 1855 u8 ether_stats_multicast_pkts_low[0x20]; 1856 1857 u8 ether_stats_crc_align_errors_high[0x20]; 1858 1859 u8 ether_stats_crc_align_errors_low[0x20]; 1860 1861 u8 ether_stats_undersize_pkts_high[0x20]; 1862 1863 u8 ether_stats_undersize_pkts_low[0x20]; 1864 1865 u8 ether_stats_oversize_pkts_high[0x20]; 1866 1867 u8 ether_stats_oversize_pkts_low[0x20]; 1868 1869 u8 ether_stats_fragments_high[0x20]; 1870 1871 u8 ether_stats_fragments_low[0x20]; 1872 1873 u8 ether_stats_jabbers_high[0x20]; 1874 1875 u8 ether_stats_jabbers_low[0x20]; 1876 1877 u8 ether_stats_collisions_high[0x20]; 1878 1879 u8 ether_stats_collisions_low[0x20]; 1880 1881 u8 ether_stats_pkts64octets_high[0x20]; 1882 1883 u8 ether_stats_pkts64octets_low[0x20]; 1884 1885 u8 ether_stats_pkts65to127octets_high[0x20]; 1886 1887 u8 ether_stats_pkts65to127octets_low[0x20]; 1888 1889 u8 ether_stats_pkts128to255octets_high[0x20]; 1890 1891 u8 ether_stats_pkts128to255octets_low[0x20]; 1892 1893 u8 ether_stats_pkts256to511octets_high[0x20]; 1894 1895 u8 ether_stats_pkts256to511octets_low[0x20]; 1896 1897 u8 ether_stats_pkts512to1023octets_high[0x20]; 1898 1899 u8 ether_stats_pkts512to1023octets_low[0x20]; 1900 1901 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1902 1903 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1904 1905 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1906 1907 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1908 1909 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1910 1911 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1912 1913 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1914 1915 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1916 1917 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1918 1919 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1920 1921 u8 reserved_at_540[0x280]; 1922 }; 1923 1924 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1925 u8 if_in_octets_high[0x20]; 1926 1927 u8 if_in_octets_low[0x20]; 1928 1929 u8 if_in_ucast_pkts_high[0x20]; 1930 1931 u8 if_in_ucast_pkts_low[0x20]; 1932 1933 u8 if_in_discards_high[0x20]; 1934 1935 u8 if_in_discards_low[0x20]; 1936 1937 u8 if_in_errors_high[0x20]; 1938 1939 u8 if_in_errors_low[0x20]; 1940 1941 u8 if_in_unknown_protos_high[0x20]; 1942 1943 u8 if_in_unknown_protos_low[0x20]; 1944 1945 u8 if_out_octets_high[0x20]; 1946 1947 u8 if_out_octets_low[0x20]; 1948 1949 u8 if_out_ucast_pkts_high[0x20]; 1950 1951 u8 if_out_ucast_pkts_low[0x20]; 1952 1953 u8 if_out_discards_high[0x20]; 1954 1955 u8 if_out_discards_low[0x20]; 1956 1957 u8 if_out_errors_high[0x20]; 1958 1959 u8 if_out_errors_low[0x20]; 1960 1961 u8 if_in_multicast_pkts_high[0x20]; 1962 1963 u8 if_in_multicast_pkts_low[0x20]; 1964 1965 u8 if_in_broadcast_pkts_high[0x20]; 1966 1967 u8 if_in_broadcast_pkts_low[0x20]; 1968 1969 u8 if_out_multicast_pkts_high[0x20]; 1970 1971 u8 if_out_multicast_pkts_low[0x20]; 1972 1973 u8 if_out_broadcast_pkts_high[0x20]; 1974 1975 u8 if_out_broadcast_pkts_low[0x20]; 1976 1977 u8 reserved_at_340[0x480]; 1978 }; 1979 1980 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1981 u8 a_frames_transmitted_ok_high[0x20]; 1982 1983 u8 a_frames_transmitted_ok_low[0x20]; 1984 1985 u8 a_frames_received_ok_high[0x20]; 1986 1987 u8 a_frames_received_ok_low[0x20]; 1988 1989 u8 a_frame_check_sequence_errors_high[0x20]; 1990 1991 u8 a_frame_check_sequence_errors_low[0x20]; 1992 1993 u8 a_alignment_errors_high[0x20]; 1994 1995 u8 a_alignment_errors_low[0x20]; 1996 1997 u8 a_octets_transmitted_ok_high[0x20]; 1998 1999 u8 a_octets_transmitted_ok_low[0x20]; 2000 2001 u8 a_octets_received_ok_high[0x20]; 2002 2003 u8 a_octets_received_ok_low[0x20]; 2004 2005 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2006 2007 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2008 2009 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2010 2011 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2012 2013 u8 a_multicast_frames_received_ok_high[0x20]; 2014 2015 u8 a_multicast_frames_received_ok_low[0x20]; 2016 2017 u8 a_broadcast_frames_received_ok_high[0x20]; 2018 2019 u8 a_broadcast_frames_received_ok_low[0x20]; 2020 2021 u8 a_in_range_length_errors_high[0x20]; 2022 2023 u8 a_in_range_length_errors_low[0x20]; 2024 2025 u8 a_out_of_range_length_field_high[0x20]; 2026 2027 u8 a_out_of_range_length_field_low[0x20]; 2028 2029 u8 a_frame_too_long_errors_high[0x20]; 2030 2031 u8 a_frame_too_long_errors_low[0x20]; 2032 2033 u8 a_symbol_error_during_carrier_high[0x20]; 2034 2035 u8 a_symbol_error_during_carrier_low[0x20]; 2036 2037 u8 a_mac_control_frames_transmitted_high[0x20]; 2038 2039 u8 a_mac_control_frames_transmitted_low[0x20]; 2040 2041 u8 a_mac_control_frames_received_high[0x20]; 2042 2043 u8 a_mac_control_frames_received_low[0x20]; 2044 2045 u8 a_unsupported_opcodes_received_high[0x20]; 2046 2047 u8 a_unsupported_opcodes_received_low[0x20]; 2048 2049 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2050 2051 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2052 2053 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2054 2055 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2056 2057 u8 reserved_at_4c0[0x300]; 2058 }; 2059 2060 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2061 u8 life_time_counter_high[0x20]; 2062 2063 u8 life_time_counter_low[0x20]; 2064 2065 u8 rx_errors[0x20]; 2066 2067 u8 tx_errors[0x20]; 2068 2069 u8 l0_to_recovery_eieos[0x20]; 2070 2071 u8 l0_to_recovery_ts[0x20]; 2072 2073 u8 l0_to_recovery_framing[0x20]; 2074 2075 u8 l0_to_recovery_retrain[0x20]; 2076 2077 u8 crc_error_dllp[0x20]; 2078 2079 u8 crc_error_tlp[0x20]; 2080 2081 u8 tx_overflow_buffer_pkt_high[0x20]; 2082 2083 u8 tx_overflow_buffer_pkt_low[0x20]; 2084 2085 u8 outbound_stalled_reads[0x20]; 2086 2087 u8 outbound_stalled_writes[0x20]; 2088 2089 u8 outbound_stalled_reads_events[0x20]; 2090 2091 u8 outbound_stalled_writes_events[0x20]; 2092 2093 u8 reserved_at_200[0x5c0]; 2094 }; 2095 2096 struct mlx5_ifc_cmd_inter_comp_event_bits { 2097 u8 command_completion_vector[0x20]; 2098 2099 u8 reserved_at_20[0xc0]; 2100 }; 2101 2102 struct mlx5_ifc_stall_vl_event_bits { 2103 u8 reserved_at_0[0x18]; 2104 u8 port_num[0x1]; 2105 u8 reserved_at_19[0x3]; 2106 u8 vl[0x4]; 2107 2108 u8 reserved_at_20[0xa0]; 2109 }; 2110 2111 struct mlx5_ifc_db_bf_congestion_event_bits { 2112 u8 event_subtype[0x8]; 2113 u8 reserved_at_8[0x8]; 2114 u8 congestion_level[0x8]; 2115 u8 reserved_at_18[0x8]; 2116 2117 u8 reserved_at_20[0xa0]; 2118 }; 2119 2120 struct mlx5_ifc_gpio_event_bits { 2121 u8 reserved_at_0[0x60]; 2122 2123 u8 gpio_event_hi[0x20]; 2124 2125 u8 gpio_event_lo[0x20]; 2126 2127 u8 reserved_at_a0[0x40]; 2128 }; 2129 2130 struct mlx5_ifc_port_state_change_event_bits { 2131 u8 reserved_at_0[0x40]; 2132 2133 u8 port_num[0x4]; 2134 u8 reserved_at_44[0x1c]; 2135 2136 u8 reserved_at_60[0x80]; 2137 }; 2138 2139 struct mlx5_ifc_dropped_packet_logged_bits { 2140 u8 reserved_at_0[0xe0]; 2141 }; 2142 2143 enum { 2144 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2145 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2146 }; 2147 2148 struct mlx5_ifc_cq_error_bits { 2149 u8 reserved_at_0[0x8]; 2150 u8 cqn[0x18]; 2151 2152 u8 reserved_at_20[0x20]; 2153 2154 u8 reserved_at_40[0x18]; 2155 u8 syndrome[0x8]; 2156 2157 u8 reserved_at_60[0x80]; 2158 }; 2159 2160 struct mlx5_ifc_rdma_page_fault_event_bits { 2161 u8 bytes_committed[0x20]; 2162 2163 u8 r_key[0x20]; 2164 2165 u8 reserved_at_40[0x10]; 2166 u8 packet_len[0x10]; 2167 2168 u8 rdma_op_len[0x20]; 2169 2170 u8 rdma_va[0x40]; 2171 2172 u8 reserved_at_c0[0x5]; 2173 u8 rdma[0x1]; 2174 u8 write[0x1]; 2175 u8 requestor[0x1]; 2176 u8 qp_number[0x18]; 2177 }; 2178 2179 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2180 u8 bytes_committed[0x20]; 2181 2182 u8 reserved_at_20[0x10]; 2183 u8 wqe_index[0x10]; 2184 2185 u8 reserved_at_40[0x10]; 2186 u8 len[0x10]; 2187 2188 u8 reserved_at_60[0x60]; 2189 2190 u8 reserved_at_c0[0x5]; 2191 u8 rdma[0x1]; 2192 u8 write_read[0x1]; 2193 u8 requestor[0x1]; 2194 u8 qpn[0x18]; 2195 }; 2196 2197 struct mlx5_ifc_qp_events_bits { 2198 u8 reserved_at_0[0xa0]; 2199 2200 u8 type[0x8]; 2201 u8 reserved_at_a8[0x18]; 2202 2203 u8 reserved_at_c0[0x8]; 2204 u8 qpn_rqn_sqn[0x18]; 2205 }; 2206 2207 struct mlx5_ifc_dct_events_bits { 2208 u8 reserved_at_0[0xc0]; 2209 2210 u8 reserved_at_c0[0x8]; 2211 u8 dct_number[0x18]; 2212 }; 2213 2214 struct mlx5_ifc_comp_event_bits { 2215 u8 reserved_at_0[0xc0]; 2216 2217 u8 reserved_at_c0[0x8]; 2218 u8 cq_number[0x18]; 2219 }; 2220 2221 enum { 2222 MLX5_QPC_STATE_RST = 0x0, 2223 MLX5_QPC_STATE_INIT = 0x1, 2224 MLX5_QPC_STATE_RTR = 0x2, 2225 MLX5_QPC_STATE_RTS = 0x3, 2226 MLX5_QPC_STATE_SQER = 0x4, 2227 MLX5_QPC_STATE_ERR = 0x6, 2228 MLX5_QPC_STATE_SQD = 0x7, 2229 MLX5_QPC_STATE_SUSPENDED = 0x9, 2230 }; 2231 2232 enum { 2233 MLX5_QPC_ST_RC = 0x0, 2234 MLX5_QPC_ST_UC = 0x1, 2235 MLX5_QPC_ST_UD = 0x2, 2236 MLX5_QPC_ST_XRC = 0x3, 2237 MLX5_QPC_ST_DCI = 0x5, 2238 MLX5_QPC_ST_QP0 = 0x7, 2239 MLX5_QPC_ST_QP1 = 0x8, 2240 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2241 MLX5_QPC_ST_REG_UMR = 0xc, 2242 }; 2243 2244 enum { 2245 MLX5_QPC_PM_STATE_ARMED = 0x0, 2246 MLX5_QPC_PM_STATE_REARM = 0x1, 2247 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2248 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2249 }; 2250 2251 enum { 2252 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2253 }; 2254 2255 enum { 2256 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2257 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2258 }; 2259 2260 enum { 2261 MLX5_QPC_MTU_256_BYTES = 0x1, 2262 MLX5_QPC_MTU_512_BYTES = 0x2, 2263 MLX5_QPC_MTU_1K_BYTES = 0x3, 2264 MLX5_QPC_MTU_2K_BYTES = 0x4, 2265 MLX5_QPC_MTU_4K_BYTES = 0x5, 2266 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2267 }; 2268 2269 enum { 2270 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2271 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2272 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2273 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2274 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2275 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2276 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2277 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2278 }; 2279 2280 enum { 2281 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2282 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2283 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2284 }; 2285 2286 enum { 2287 MLX5_QPC_CS_RES_DISABLE = 0x0, 2288 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2289 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2290 }; 2291 2292 struct mlx5_ifc_qpc_bits { 2293 u8 state[0x4]; 2294 u8 lag_tx_port_affinity[0x4]; 2295 u8 st[0x8]; 2296 u8 reserved_at_10[0x3]; 2297 u8 pm_state[0x2]; 2298 u8 reserved_at_15[0x1]; 2299 u8 req_e2e_credit_mode[0x2]; 2300 u8 offload_type[0x4]; 2301 u8 end_padding_mode[0x2]; 2302 u8 reserved_at_1e[0x2]; 2303 2304 u8 wq_signature[0x1]; 2305 u8 block_lb_mc[0x1]; 2306 u8 atomic_like_write_en[0x1]; 2307 u8 latency_sensitive[0x1]; 2308 u8 reserved_at_24[0x1]; 2309 u8 drain_sigerr[0x1]; 2310 u8 reserved_at_26[0x2]; 2311 u8 pd[0x18]; 2312 2313 u8 mtu[0x3]; 2314 u8 log_msg_max[0x5]; 2315 u8 reserved_at_48[0x1]; 2316 u8 log_rq_size[0x4]; 2317 u8 log_rq_stride[0x3]; 2318 u8 no_sq[0x1]; 2319 u8 log_sq_size[0x4]; 2320 u8 reserved_at_55[0x6]; 2321 u8 rlky[0x1]; 2322 u8 ulp_stateless_offload_mode[0x4]; 2323 2324 u8 counter_set_id[0x8]; 2325 u8 uar_page[0x18]; 2326 2327 u8 reserved_at_80[0x8]; 2328 u8 user_index[0x18]; 2329 2330 u8 reserved_at_a0[0x3]; 2331 u8 log_page_size[0x5]; 2332 u8 remote_qpn[0x18]; 2333 2334 struct mlx5_ifc_ads_bits primary_address_path; 2335 2336 struct mlx5_ifc_ads_bits secondary_address_path; 2337 2338 u8 log_ack_req_freq[0x4]; 2339 u8 reserved_at_384[0x4]; 2340 u8 log_sra_max[0x3]; 2341 u8 reserved_at_38b[0x2]; 2342 u8 retry_count[0x3]; 2343 u8 rnr_retry[0x3]; 2344 u8 reserved_at_393[0x1]; 2345 u8 fre[0x1]; 2346 u8 cur_rnr_retry[0x3]; 2347 u8 cur_retry_count[0x3]; 2348 u8 reserved_at_39b[0x5]; 2349 2350 u8 reserved_at_3a0[0x20]; 2351 2352 u8 reserved_at_3c0[0x8]; 2353 u8 next_send_psn[0x18]; 2354 2355 u8 reserved_at_3e0[0x8]; 2356 u8 cqn_snd[0x18]; 2357 2358 u8 reserved_at_400[0x8]; 2359 u8 deth_sqpn[0x18]; 2360 2361 u8 reserved_at_420[0x20]; 2362 2363 u8 reserved_at_440[0x8]; 2364 u8 last_acked_psn[0x18]; 2365 2366 u8 reserved_at_460[0x8]; 2367 u8 ssn[0x18]; 2368 2369 u8 reserved_at_480[0x8]; 2370 u8 log_rra_max[0x3]; 2371 u8 reserved_at_48b[0x1]; 2372 u8 atomic_mode[0x4]; 2373 u8 rre[0x1]; 2374 u8 rwe[0x1]; 2375 u8 rae[0x1]; 2376 u8 reserved_at_493[0x1]; 2377 u8 page_offset[0x6]; 2378 u8 reserved_at_49a[0x3]; 2379 u8 cd_slave_receive[0x1]; 2380 u8 cd_slave_send[0x1]; 2381 u8 cd_master[0x1]; 2382 2383 u8 reserved_at_4a0[0x3]; 2384 u8 min_rnr_nak[0x5]; 2385 u8 next_rcv_psn[0x18]; 2386 2387 u8 reserved_at_4c0[0x8]; 2388 u8 xrcd[0x18]; 2389 2390 u8 reserved_at_4e0[0x8]; 2391 u8 cqn_rcv[0x18]; 2392 2393 u8 dbr_addr[0x40]; 2394 2395 u8 q_key[0x20]; 2396 2397 u8 reserved_at_560[0x5]; 2398 u8 rq_type[0x3]; 2399 u8 srqn_rmpn_xrqn[0x18]; 2400 2401 u8 reserved_at_580[0x8]; 2402 u8 rmsn[0x18]; 2403 2404 u8 hw_sq_wqebb_counter[0x10]; 2405 u8 sw_sq_wqebb_counter[0x10]; 2406 2407 u8 hw_rq_counter[0x20]; 2408 2409 u8 sw_rq_counter[0x20]; 2410 2411 u8 reserved_at_600[0x20]; 2412 2413 u8 reserved_at_620[0xf]; 2414 u8 cgs[0x1]; 2415 u8 cs_req[0x8]; 2416 u8 cs_res[0x8]; 2417 2418 u8 dc_access_key[0x40]; 2419 2420 u8 reserved_at_680[0x3]; 2421 u8 dbr_umem_valid[0x1]; 2422 2423 u8 reserved_at_684[0xbc]; 2424 }; 2425 2426 struct mlx5_ifc_roce_addr_layout_bits { 2427 u8 source_l3_address[16][0x8]; 2428 2429 u8 reserved_at_80[0x3]; 2430 u8 vlan_valid[0x1]; 2431 u8 vlan_id[0xc]; 2432 u8 source_mac_47_32[0x10]; 2433 2434 u8 source_mac_31_0[0x20]; 2435 2436 u8 reserved_at_c0[0x14]; 2437 u8 roce_l3_type[0x4]; 2438 u8 roce_version[0x8]; 2439 2440 u8 reserved_at_e0[0x20]; 2441 }; 2442 2443 union mlx5_ifc_hca_cap_union_bits { 2444 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2445 struct mlx5_ifc_odp_cap_bits odp_cap; 2446 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2447 struct mlx5_ifc_roce_cap_bits roce_cap; 2448 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2449 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2450 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2451 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2452 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2453 struct mlx5_ifc_qos_cap_bits qos_cap; 2454 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2455 u8 reserved_at_0[0x8000]; 2456 }; 2457 2458 enum { 2459 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2460 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2461 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2462 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2463 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2464 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2465 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2466 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2467 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2468 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2469 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2470 }; 2471 2472 struct mlx5_ifc_vlan_bits { 2473 u8 ethtype[0x10]; 2474 u8 prio[0x3]; 2475 u8 cfi[0x1]; 2476 u8 vid[0xc]; 2477 }; 2478 2479 struct mlx5_ifc_flow_context_bits { 2480 struct mlx5_ifc_vlan_bits push_vlan; 2481 2482 u8 group_id[0x20]; 2483 2484 u8 reserved_at_40[0x8]; 2485 u8 flow_tag[0x18]; 2486 2487 u8 reserved_at_60[0x10]; 2488 u8 action[0x10]; 2489 2490 u8 extended_destination[0x1]; 2491 u8 reserved_at_80[0x7]; 2492 u8 destination_list_size[0x18]; 2493 2494 u8 reserved_at_a0[0x8]; 2495 u8 flow_counter_list_size[0x18]; 2496 2497 u8 packet_reformat_id[0x20]; 2498 2499 u8 modify_header_id[0x20]; 2500 2501 struct mlx5_ifc_vlan_bits push_vlan_2; 2502 2503 u8 reserved_at_120[0xe0]; 2504 2505 struct mlx5_ifc_fte_match_param_bits match_value; 2506 2507 u8 reserved_at_1200[0x600]; 2508 2509 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2510 }; 2511 2512 enum { 2513 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2514 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2515 }; 2516 2517 struct mlx5_ifc_xrc_srqc_bits { 2518 u8 state[0x4]; 2519 u8 log_xrc_srq_size[0x4]; 2520 u8 reserved_at_8[0x18]; 2521 2522 u8 wq_signature[0x1]; 2523 u8 cont_srq[0x1]; 2524 u8 reserved_at_22[0x1]; 2525 u8 rlky[0x1]; 2526 u8 basic_cyclic_rcv_wqe[0x1]; 2527 u8 log_rq_stride[0x3]; 2528 u8 xrcd[0x18]; 2529 2530 u8 page_offset[0x6]; 2531 u8 reserved_at_46[0x1]; 2532 u8 dbr_umem_valid[0x1]; 2533 u8 cqn[0x18]; 2534 2535 u8 reserved_at_60[0x20]; 2536 2537 u8 user_index_equal_xrc_srqn[0x1]; 2538 u8 reserved_at_81[0x1]; 2539 u8 log_page_size[0x6]; 2540 u8 user_index[0x18]; 2541 2542 u8 reserved_at_a0[0x20]; 2543 2544 u8 reserved_at_c0[0x8]; 2545 u8 pd[0x18]; 2546 2547 u8 lwm[0x10]; 2548 u8 wqe_cnt[0x10]; 2549 2550 u8 reserved_at_100[0x40]; 2551 2552 u8 db_record_addr_h[0x20]; 2553 2554 u8 db_record_addr_l[0x1e]; 2555 u8 reserved_at_17e[0x2]; 2556 2557 u8 reserved_at_180[0x80]; 2558 }; 2559 2560 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2561 u8 counter_error_queues[0x20]; 2562 2563 u8 total_error_queues[0x20]; 2564 2565 u8 send_queue_priority_update_flow[0x20]; 2566 2567 u8 reserved_at_60[0x20]; 2568 2569 u8 nic_receive_steering_discard[0x40]; 2570 2571 u8 receive_discard_vport_down[0x40]; 2572 2573 u8 transmit_discard_vport_down[0x40]; 2574 2575 u8 reserved_at_140[0xec0]; 2576 }; 2577 2578 struct mlx5_ifc_traffic_counter_bits { 2579 u8 packets[0x40]; 2580 2581 u8 octets[0x40]; 2582 }; 2583 2584 struct mlx5_ifc_tisc_bits { 2585 u8 strict_lag_tx_port_affinity[0x1]; 2586 u8 reserved_at_1[0x3]; 2587 u8 lag_tx_port_affinity[0x04]; 2588 2589 u8 reserved_at_8[0x4]; 2590 u8 prio[0x4]; 2591 u8 reserved_at_10[0x10]; 2592 2593 u8 reserved_at_20[0x100]; 2594 2595 u8 reserved_at_120[0x8]; 2596 u8 transport_domain[0x18]; 2597 2598 u8 reserved_at_140[0x8]; 2599 u8 underlay_qpn[0x18]; 2600 u8 reserved_at_160[0x3a0]; 2601 }; 2602 2603 enum { 2604 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2605 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2606 }; 2607 2608 enum { 2609 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2610 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2611 }; 2612 2613 enum { 2614 MLX5_RX_HASH_FN_NONE = 0x0, 2615 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2616 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2617 }; 2618 2619 enum { 2620 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2621 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2622 }; 2623 2624 struct mlx5_ifc_tirc_bits { 2625 u8 reserved_at_0[0x20]; 2626 2627 u8 disp_type[0x4]; 2628 u8 reserved_at_24[0x1c]; 2629 2630 u8 reserved_at_40[0x40]; 2631 2632 u8 reserved_at_80[0x4]; 2633 u8 lro_timeout_period_usecs[0x10]; 2634 u8 lro_enable_mask[0x4]; 2635 u8 lro_max_ip_payload_size[0x8]; 2636 2637 u8 reserved_at_a0[0x40]; 2638 2639 u8 reserved_at_e0[0x8]; 2640 u8 inline_rqn[0x18]; 2641 2642 u8 rx_hash_symmetric[0x1]; 2643 u8 reserved_at_101[0x1]; 2644 u8 tunneled_offload_en[0x1]; 2645 u8 reserved_at_103[0x5]; 2646 u8 indirect_table[0x18]; 2647 2648 u8 rx_hash_fn[0x4]; 2649 u8 reserved_at_124[0x2]; 2650 u8 self_lb_block[0x2]; 2651 u8 transport_domain[0x18]; 2652 2653 u8 rx_hash_toeplitz_key[10][0x20]; 2654 2655 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2656 2657 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2658 2659 u8 reserved_at_2c0[0x4c0]; 2660 }; 2661 2662 enum { 2663 MLX5_SRQC_STATE_GOOD = 0x0, 2664 MLX5_SRQC_STATE_ERROR = 0x1, 2665 }; 2666 2667 struct mlx5_ifc_srqc_bits { 2668 u8 state[0x4]; 2669 u8 log_srq_size[0x4]; 2670 u8 reserved_at_8[0x18]; 2671 2672 u8 wq_signature[0x1]; 2673 u8 cont_srq[0x1]; 2674 u8 reserved_at_22[0x1]; 2675 u8 rlky[0x1]; 2676 u8 reserved_at_24[0x1]; 2677 u8 log_rq_stride[0x3]; 2678 u8 xrcd[0x18]; 2679 2680 u8 page_offset[0x6]; 2681 u8 reserved_at_46[0x2]; 2682 u8 cqn[0x18]; 2683 2684 u8 reserved_at_60[0x20]; 2685 2686 u8 reserved_at_80[0x2]; 2687 u8 log_page_size[0x6]; 2688 u8 reserved_at_88[0x18]; 2689 2690 u8 reserved_at_a0[0x20]; 2691 2692 u8 reserved_at_c0[0x8]; 2693 u8 pd[0x18]; 2694 2695 u8 lwm[0x10]; 2696 u8 wqe_cnt[0x10]; 2697 2698 u8 reserved_at_100[0x40]; 2699 2700 u8 dbr_addr[0x40]; 2701 2702 u8 reserved_at_180[0x80]; 2703 }; 2704 2705 enum { 2706 MLX5_SQC_STATE_RST = 0x0, 2707 MLX5_SQC_STATE_RDY = 0x1, 2708 MLX5_SQC_STATE_ERR = 0x3, 2709 }; 2710 2711 struct mlx5_ifc_sqc_bits { 2712 u8 rlky[0x1]; 2713 u8 cd_master[0x1]; 2714 u8 fre[0x1]; 2715 u8 flush_in_error_en[0x1]; 2716 u8 allow_multi_pkt_send_wqe[0x1]; 2717 u8 min_wqe_inline_mode[0x3]; 2718 u8 state[0x4]; 2719 u8 reg_umr[0x1]; 2720 u8 allow_swp[0x1]; 2721 u8 hairpin[0x1]; 2722 u8 reserved_at_f[0x11]; 2723 2724 u8 reserved_at_20[0x8]; 2725 u8 user_index[0x18]; 2726 2727 u8 reserved_at_40[0x8]; 2728 u8 cqn[0x18]; 2729 2730 u8 reserved_at_60[0x8]; 2731 u8 hairpin_peer_rq[0x18]; 2732 2733 u8 reserved_at_80[0x10]; 2734 u8 hairpin_peer_vhca[0x10]; 2735 2736 u8 reserved_at_a0[0x50]; 2737 2738 u8 packet_pacing_rate_limit_index[0x10]; 2739 u8 tis_lst_sz[0x10]; 2740 u8 reserved_at_110[0x10]; 2741 2742 u8 reserved_at_120[0x40]; 2743 2744 u8 reserved_at_160[0x8]; 2745 u8 tis_num_0[0x18]; 2746 2747 struct mlx5_ifc_wq_bits wq; 2748 }; 2749 2750 enum { 2751 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2752 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2753 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2754 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2755 }; 2756 2757 struct mlx5_ifc_scheduling_context_bits { 2758 u8 element_type[0x8]; 2759 u8 reserved_at_8[0x18]; 2760 2761 u8 element_attributes[0x20]; 2762 2763 u8 parent_element_id[0x20]; 2764 2765 u8 reserved_at_60[0x40]; 2766 2767 u8 bw_share[0x20]; 2768 2769 u8 max_average_bw[0x20]; 2770 2771 u8 reserved_at_e0[0x120]; 2772 }; 2773 2774 struct mlx5_ifc_rqtc_bits { 2775 u8 reserved_at_0[0xa0]; 2776 2777 u8 reserved_at_a0[0x10]; 2778 u8 rqt_max_size[0x10]; 2779 2780 u8 reserved_at_c0[0x10]; 2781 u8 rqt_actual_size[0x10]; 2782 2783 u8 reserved_at_e0[0x6a0]; 2784 2785 struct mlx5_ifc_rq_num_bits rq_num[0]; 2786 }; 2787 2788 enum { 2789 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2790 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2791 }; 2792 2793 enum { 2794 MLX5_RQC_STATE_RST = 0x0, 2795 MLX5_RQC_STATE_RDY = 0x1, 2796 MLX5_RQC_STATE_ERR = 0x3, 2797 }; 2798 2799 struct mlx5_ifc_rqc_bits { 2800 u8 rlky[0x1]; 2801 u8 delay_drop_en[0x1]; 2802 u8 scatter_fcs[0x1]; 2803 u8 vsd[0x1]; 2804 u8 mem_rq_type[0x4]; 2805 u8 state[0x4]; 2806 u8 reserved_at_c[0x1]; 2807 u8 flush_in_error_en[0x1]; 2808 u8 hairpin[0x1]; 2809 u8 reserved_at_f[0x11]; 2810 2811 u8 reserved_at_20[0x8]; 2812 u8 user_index[0x18]; 2813 2814 u8 reserved_at_40[0x8]; 2815 u8 cqn[0x18]; 2816 2817 u8 counter_set_id[0x8]; 2818 u8 reserved_at_68[0x18]; 2819 2820 u8 reserved_at_80[0x8]; 2821 u8 rmpn[0x18]; 2822 2823 u8 reserved_at_a0[0x8]; 2824 u8 hairpin_peer_sq[0x18]; 2825 2826 u8 reserved_at_c0[0x10]; 2827 u8 hairpin_peer_vhca[0x10]; 2828 2829 u8 reserved_at_e0[0xa0]; 2830 2831 struct mlx5_ifc_wq_bits wq; 2832 }; 2833 2834 enum { 2835 MLX5_RMPC_STATE_RDY = 0x1, 2836 MLX5_RMPC_STATE_ERR = 0x3, 2837 }; 2838 2839 struct mlx5_ifc_rmpc_bits { 2840 u8 reserved_at_0[0x8]; 2841 u8 state[0x4]; 2842 u8 reserved_at_c[0x14]; 2843 2844 u8 basic_cyclic_rcv_wqe[0x1]; 2845 u8 reserved_at_21[0x1f]; 2846 2847 u8 reserved_at_40[0x140]; 2848 2849 struct mlx5_ifc_wq_bits wq; 2850 }; 2851 2852 struct mlx5_ifc_nic_vport_context_bits { 2853 u8 reserved_at_0[0x5]; 2854 u8 min_wqe_inline_mode[0x3]; 2855 u8 reserved_at_8[0x15]; 2856 u8 disable_mc_local_lb[0x1]; 2857 u8 disable_uc_local_lb[0x1]; 2858 u8 roce_en[0x1]; 2859 2860 u8 arm_change_event[0x1]; 2861 u8 reserved_at_21[0x1a]; 2862 u8 event_on_mtu[0x1]; 2863 u8 event_on_promisc_change[0x1]; 2864 u8 event_on_vlan_change[0x1]; 2865 u8 event_on_mc_address_change[0x1]; 2866 u8 event_on_uc_address_change[0x1]; 2867 2868 u8 reserved_at_40[0xc]; 2869 2870 u8 affiliation_criteria[0x4]; 2871 u8 affiliated_vhca_id[0x10]; 2872 2873 u8 reserved_at_60[0xd0]; 2874 2875 u8 mtu[0x10]; 2876 2877 u8 system_image_guid[0x40]; 2878 u8 port_guid[0x40]; 2879 u8 node_guid[0x40]; 2880 2881 u8 reserved_at_200[0x140]; 2882 u8 qkey_violation_counter[0x10]; 2883 u8 reserved_at_350[0x430]; 2884 2885 u8 promisc_uc[0x1]; 2886 u8 promisc_mc[0x1]; 2887 u8 promisc_all[0x1]; 2888 u8 reserved_at_783[0x2]; 2889 u8 allowed_list_type[0x3]; 2890 u8 reserved_at_788[0xc]; 2891 u8 allowed_list_size[0xc]; 2892 2893 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2894 2895 u8 reserved_at_7e0[0x20]; 2896 2897 u8 current_uc_mac_address[0][0x40]; 2898 }; 2899 2900 enum { 2901 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2902 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2903 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2904 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2905 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2906 }; 2907 2908 struct mlx5_ifc_mkc_bits { 2909 u8 reserved_at_0[0x1]; 2910 u8 free[0x1]; 2911 u8 reserved_at_2[0x1]; 2912 u8 access_mode_4_2[0x3]; 2913 u8 reserved_at_6[0x7]; 2914 u8 relaxed_ordering_write[0x1]; 2915 u8 reserved_at_e[0x1]; 2916 u8 small_fence_on_rdma_read_response[0x1]; 2917 u8 umr_en[0x1]; 2918 u8 a[0x1]; 2919 u8 rw[0x1]; 2920 u8 rr[0x1]; 2921 u8 lw[0x1]; 2922 u8 lr[0x1]; 2923 u8 access_mode_1_0[0x2]; 2924 u8 reserved_at_18[0x8]; 2925 2926 u8 qpn[0x18]; 2927 u8 mkey_7_0[0x8]; 2928 2929 u8 reserved_at_40[0x20]; 2930 2931 u8 length64[0x1]; 2932 u8 bsf_en[0x1]; 2933 u8 sync_umr[0x1]; 2934 u8 reserved_at_63[0x2]; 2935 u8 expected_sigerr_count[0x1]; 2936 u8 reserved_at_66[0x1]; 2937 u8 en_rinval[0x1]; 2938 u8 pd[0x18]; 2939 2940 u8 start_addr[0x40]; 2941 2942 u8 len[0x40]; 2943 2944 u8 bsf_octword_size[0x20]; 2945 2946 u8 reserved_at_120[0x80]; 2947 2948 u8 translations_octword_size[0x20]; 2949 2950 u8 reserved_at_1c0[0x1b]; 2951 u8 log_page_size[0x5]; 2952 2953 u8 reserved_at_1e0[0x20]; 2954 }; 2955 2956 struct mlx5_ifc_pkey_bits { 2957 u8 reserved_at_0[0x10]; 2958 u8 pkey[0x10]; 2959 }; 2960 2961 struct mlx5_ifc_array128_auto_bits { 2962 u8 array128_auto[16][0x8]; 2963 }; 2964 2965 struct mlx5_ifc_hca_vport_context_bits { 2966 u8 field_select[0x20]; 2967 2968 u8 reserved_at_20[0xe0]; 2969 2970 u8 sm_virt_aware[0x1]; 2971 u8 has_smi[0x1]; 2972 u8 has_raw[0x1]; 2973 u8 grh_required[0x1]; 2974 u8 reserved_at_104[0xc]; 2975 u8 port_physical_state[0x4]; 2976 u8 vport_state_policy[0x4]; 2977 u8 port_state[0x4]; 2978 u8 vport_state[0x4]; 2979 2980 u8 reserved_at_120[0x20]; 2981 2982 u8 system_image_guid[0x40]; 2983 2984 u8 port_guid[0x40]; 2985 2986 u8 node_guid[0x40]; 2987 2988 u8 cap_mask1[0x20]; 2989 2990 u8 cap_mask1_field_select[0x20]; 2991 2992 u8 cap_mask2[0x20]; 2993 2994 u8 cap_mask2_field_select[0x20]; 2995 2996 u8 reserved_at_280[0x80]; 2997 2998 u8 lid[0x10]; 2999 u8 reserved_at_310[0x4]; 3000 u8 init_type_reply[0x4]; 3001 u8 lmc[0x3]; 3002 u8 subnet_timeout[0x5]; 3003 3004 u8 sm_lid[0x10]; 3005 u8 sm_sl[0x4]; 3006 u8 reserved_at_334[0xc]; 3007 3008 u8 qkey_violation_counter[0x10]; 3009 u8 pkey_violation_counter[0x10]; 3010 3011 u8 reserved_at_360[0xca0]; 3012 }; 3013 3014 struct mlx5_ifc_esw_vport_context_bits { 3015 u8 reserved_at_0[0x3]; 3016 u8 vport_svlan_strip[0x1]; 3017 u8 vport_cvlan_strip[0x1]; 3018 u8 vport_svlan_insert[0x1]; 3019 u8 vport_cvlan_insert[0x2]; 3020 u8 reserved_at_8[0x18]; 3021 3022 u8 reserved_at_20[0x20]; 3023 3024 u8 svlan_cfi[0x1]; 3025 u8 svlan_pcp[0x3]; 3026 u8 svlan_id[0xc]; 3027 u8 cvlan_cfi[0x1]; 3028 u8 cvlan_pcp[0x3]; 3029 u8 cvlan_id[0xc]; 3030 3031 u8 reserved_at_60[0x7a0]; 3032 }; 3033 3034 enum { 3035 MLX5_EQC_STATUS_OK = 0x0, 3036 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3037 }; 3038 3039 enum { 3040 MLX5_EQC_ST_ARMED = 0x9, 3041 MLX5_EQC_ST_FIRED = 0xa, 3042 }; 3043 3044 struct mlx5_ifc_eqc_bits { 3045 u8 status[0x4]; 3046 u8 reserved_at_4[0x9]; 3047 u8 ec[0x1]; 3048 u8 oi[0x1]; 3049 u8 reserved_at_f[0x5]; 3050 u8 st[0x4]; 3051 u8 reserved_at_18[0x8]; 3052 3053 u8 reserved_at_20[0x20]; 3054 3055 u8 reserved_at_40[0x14]; 3056 u8 page_offset[0x6]; 3057 u8 reserved_at_5a[0x6]; 3058 3059 u8 reserved_at_60[0x3]; 3060 u8 log_eq_size[0x5]; 3061 u8 uar_page[0x18]; 3062 3063 u8 reserved_at_80[0x20]; 3064 3065 u8 reserved_at_a0[0x18]; 3066 u8 intr[0x8]; 3067 3068 u8 reserved_at_c0[0x3]; 3069 u8 log_page_size[0x5]; 3070 u8 reserved_at_c8[0x18]; 3071 3072 u8 reserved_at_e0[0x60]; 3073 3074 u8 reserved_at_140[0x8]; 3075 u8 consumer_counter[0x18]; 3076 3077 u8 reserved_at_160[0x8]; 3078 u8 producer_counter[0x18]; 3079 3080 u8 reserved_at_180[0x80]; 3081 }; 3082 3083 enum { 3084 MLX5_DCTC_STATE_ACTIVE = 0x0, 3085 MLX5_DCTC_STATE_DRAINING = 0x1, 3086 MLX5_DCTC_STATE_DRAINED = 0x2, 3087 }; 3088 3089 enum { 3090 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3091 MLX5_DCTC_CS_RES_NA = 0x1, 3092 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3093 }; 3094 3095 enum { 3096 MLX5_DCTC_MTU_256_BYTES = 0x1, 3097 MLX5_DCTC_MTU_512_BYTES = 0x2, 3098 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3099 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3100 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3101 }; 3102 3103 struct mlx5_ifc_dctc_bits { 3104 u8 reserved_at_0[0x4]; 3105 u8 state[0x4]; 3106 u8 reserved_at_8[0x18]; 3107 3108 u8 reserved_at_20[0x8]; 3109 u8 user_index[0x18]; 3110 3111 u8 reserved_at_40[0x8]; 3112 u8 cqn[0x18]; 3113 3114 u8 counter_set_id[0x8]; 3115 u8 atomic_mode[0x4]; 3116 u8 rre[0x1]; 3117 u8 rwe[0x1]; 3118 u8 rae[0x1]; 3119 u8 atomic_like_write_en[0x1]; 3120 u8 latency_sensitive[0x1]; 3121 u8 rlky[0x1]; 3122 u8 free_ar[0x1]; 3123 u8 reserved_at_73[0xd]; 3124 3125 u8 reserved_at_80[0x8]; 3126 u8 cs_res[0x8]; 3127 u8 reserved_at_90[0x3]; 3128 u8 min_rnr_nak[0x5]; 3129 u8 reserved_at_98[0x8]; 3130 3131 u8 reserved_at_a0[0x8]; 3132 u8 srqn_xrqn[0x18]; 3133 3134 u8 reserved_at_c0[0x8]; 3135 u8 pd[0x18]; 3136 3137 u8 tclass[0x8]; 3138 u8 reserved_at_e8[0x4]; 3139 u8 flow_label[0x14]; 3140 3141 u8 dc_access_key[0x40]; 3142 3143 u8 reserved_at_140[0x5]; 3144 u8 mtu[0x3]; 3145 u8 port[0x8]; 3146 u8 pkey_index[0x10]; 3147 3148 u8 reserved_at_160[0x8]; 3149 u8 my_addr_index[0x8]; 3150 u8 reserved_at_170[0x8]; 3151 u8 hop_limit[0x8]; 3152 3153 u8 dc_access_key_violation_count[0x20]; 3154 3155 u8 reserved_at_1a0[0x14]; 3156 u8 dei_cfi[0x1]; 3157 u8 eth_prio[0x3]; 3158 u8 ecn[0x2]; 3159 u8 dscp[0x6]; 3160 3161 u8 reserved_at_1c0[0x40]; 3162 }; 3163 3164 enum { 3165 MLX5_CQC_STATUS_OK = 0x0, 3166 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3167 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3168 }; 3169 3170 enum { 3171 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3172 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3173 }; 3174 3175 enum { 3176 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3177 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3178 MLX5_CQC_ST_FIRED = 0xa, 3179 }; 3180 3181 enum { 3182 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3183 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3184 MLX5_CQ_PERIOD_NUM_MODES 3185 }; 3186 3187 struct mlx5_ifc_cqc_bits { 3188 u8 status[0x4]; 3189 u8 reserved_at_4[0x2]; 3190 u8 dbr_umem_valid[0x1]; 3191 u8 reserved_at_7[0x1]; 3192 u8 cqe_sz[0x3]; 3193 u8 cc[0x1]; 3194 u8 reserved_at_c[0x1]; 3195 u8 scqe_break_moderation_en[0x1]; 3196 u8 oi[0x1]; 3197 u8 cq_period_mode[0x2]; 3198 u8 cqe_comp_en[0x1]; 3199 u8 mini_cqe_res_format[0x2]; 3200 u8 st[0x4]; 3201 u8 reserved_at_18[0x8]; 3202 3203 u8 reserved_at_20[0x20]; 3204 3205 u8 reserved_at_40[0x14]; 3206 u8 page_offset[0x6]; 3207 u8 reserved_at_5a[0x6]; 3208 3209 u8 reserved_at_60[0x3]; 3210 u8 log_cq_size[0x5]; 3211 u8 uar_page[0x18]; 3212 3213 u8 reserved_at_80[0x4]; 3214 u8 cq_period[0xc]; 3215 u8 cq_max_count[0x10]; 3216 3217 u8 reserved_at_a0[0x18]; 3218 u8 c_eqn[0x8]; 3219 3220 u8 reserved_at_c0[0x3]; 3221 u8 log_page_size[0x5]; 3222 u8 reserved_at_c8[0x18]; 3223 3224 u8 reserved_at_e0[0x20]; 3225 3226 u8 reserved_at_100[0x8]; 3227 u8 last_notified_index[0x18]; 3228 3229 u8 reserved_at_120[0x8]; 3230 u8 last_solicit_index[0x18]; 3231 3232 u8 reserved_at_140[0x8]; 3233 u8 consumer_counter[0x18]; 3234 3235 u8 reserved_at_160[0x8]; 3236 u8 producer_counter[0x18]; 3237 3238 u8 reserved_at_180[0x40]; 3239 3240 u8 dbr_addr[0x40]; 3241 }; 3242 3243 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3244 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3245 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3246 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3247 u8 reserved_at_0[0x800]; 3248 }; 3249 3250 struct mlx5_ifc_query_adapter_param_block_bits { 3251 u8 reserved_at_0[0xc0]; 3252 3253 u8 reserved_at_c0[0x8]; 3254 u8 ieee_vendor_id[0x18]; 3255 3256 u8 reserved_at_e0[0x10]; 3257 u8 vsd_vendor_id[0x10]; 3258 3259 u8 vsd[208][0x8]; 3260 3261 u8 vsd_contd_psid[16][0x8]; 3262 }; 3263 3264 enum { 3265 MLX5_XRQC_STATE_GOOD = 0x0, 3266 MLX5_XRQC_STATE_ERROR = 0x1, 3267 }; 3268 3269 enum { 3270 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3271 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3272 }; 3273 3274 enum { 3275 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3276 }; 3277 3278 struct mlx5_ifc_tag_matching_topology_context_bits { 3279 u8 log_matching_list_sz[0x4]; 3280 u8 reserved_at_4[0xc]; 3281 u8 append_next_index[0x10]; 3282 3283 u8 sw_phase_cnt[0x10]; 3284 u8 hw_phase_cnt[0x10]; 3285 3286 u8 reserved_at_40[0x40]; 3287 }; 3288 3289 struct mlx5_ifc_xrqc_bits { 3290 u8 state[0x4]; 3291 u8 rlkey[0x1]; 3292 u8 reserved_at_5[0xf]; 3293 u8 topology[0x4]; 3294 u8 reserved_at_18[0x4]; 3295 u8 offload[0x4]; 3296 3297 u8 reserved_at_20[0x8]; 3298 u8 user_index[0x18]; 3299 3300 u8 reserved_at_40[0x8]; 3301 u8 cqn[0x18]; 3302 3303 u8 reserved_at_60[0xa0]; 3304 3305 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3306 3307 u8 reserved_at_180[0x280]; 3308 3309 struct mlx5_ifc_wq_bits wq; 3310 }; 3311 3312 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3313 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3314 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3315 u8 reserved_at_0[0x20]; 3316 }; 3317 3318 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3319 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3320 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3321 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3322 u8 reserved_at_0[0x20]; 3323 }; 3324 3325 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3326 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3327 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3328 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3329 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3330 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3331 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3332 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3333 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3334 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3335 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3336 u8 reserved_at_0[0x7c0]; 3337 }; 3338 3339 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3340 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3341 u8 reserved_at_0[0x7c0]; 3342 }; 3343 3344 union mlx5_ifc_event_auto_bits { 3345 struct mlx5_ifc_comp_event_bits comp_event; 3346 struct mlx5_ifc_dct_events_bits dct_events; 3347 struct mlx5_ifc_qp_events_bits qp_events; 3348 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3349 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3350 struct mlx5_ifc_cq_error_bits cq_error; 3351 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3352 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3353 struct mlx5_ifc_gpio_event_bits gpio_event; 3354 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3355 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3356 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3357 u8 reserved_at_0[0xe0]; 3358 }; 3359 3360 struct mlx5_ifc_health_buffer_bits { 3361 u8 reserved_at_0[0x100]; 3362 3363 u8 assert_existptr[0x20]; 3364 3365 u8 assert_callra[0x20]; 3366 3367 u8 reserved_at_140[0x40]; 3368 3369 u8 fw_version[0x20]; 3370 3371 u8 hw_id[0x20]; 3372 3373 u8 reserved_at_1c0[0x20]; 3374 3375 u8 irisc_index[0x8]; 3376 u8 synd[0x8]; 3377 u8 ext_synd[0x10]; 3378 }; 3379 3380 struct mlx5_ifc_register_loopback_control_bits { 3381 u8 no_lb[0x1]; 3382 u8 reserved_at_1[0x7]; 3383 u8 port[0x8]; 3384 u8 reserved_at_10[0x10]; 3385 3386 u8 reserved_at_20[0x60]; 3387 }; 3388 3389 struct mlx5_ifc_vport_tc_element_bits { 3390 u8 traffic_class[0x4]; 3391 u8 reserved_at_4[0xc]; 3392 u8 vport_number[0x10]; 3393 }; 3394 3395 struct mlx5_ifc_vport_element_bits { 3396 u8 reserved_at_0[0x10]; 3397 u8 vport_number[0x10]; 3398 }; 3399 3400 enum { 3401 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3402 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3403 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3404 }; 3405 3406 struct mlx5_ifc_tsar_element_bits { 3407 u8 reserved_at_0[0x8]; 3408 u8 tsar_type[0x8]; 3409 u8 reserved_at_10[0x10]; 3410 }; 3411 3412 enum { 3413 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3414 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3415 }; 3416 3417 struct mlx5_ifc_teardown_hca_out_bits { 3418 u8 status[0x8]; 3419 u8 reserved_at_8[0x18]; 3420 3421 u8 syndrome[0x20]; 3422 3423 u8 reserved_at_40[0x3f]; 3424 3425 u8 state[0x1]; 3426 }; 3427 3428 enum { 3429 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3430 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3431 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3432 }; 3433 3434 struct mlx5_ifc_teardown_hca_in_bits { 3435 u8 opcode[0x10]; 3436 u8 reserved_at_10[0x10]; 3437 3438 u8 reserved_at_20[0x10]; 3439 u8 op_mod[0x10]; 3440 3441 u8 reserved_at_40[0x10]; 3442 u8 profile[0x10]; 3443 3444 u8 reserved_at_60[0x20]; 3445 }; 3446 3447 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3448 u8 status[0x8]; 3449 u8 reserved_at_8[0x18]; 3450 3451 u8 syndrome[0x20]; 3452 3453 u8 reserved_at_40[0x40]; 3454 }; 3455 3456 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3457 u8 opcode[0x10]; 3458 u8 uid[0x10]; 3459 3460 u8 reserved_at_20[0x10]; 3461 u8 op_mod[0x10]; 3462 3463 u8 reserved_at_40[0x8]; 3464 u8 qpn[0x18]; 3465 3466 u8 reserved_at_60[0x20]; 3467 3468 u8 opt_param_mask[0x20]; 3469 3470 u8 reserved_at_a0[0x20]; 3471 3472 struct mlx5_ifc_qpc_bits qpc; 3473 3474 u8 reserved_at_800[0x80]; 3475 }; 3476 3477 struct mlx5_ifc_sqd2rts_qp_out_bits { 3478 u8 status[0x8]; 3479 u8 reserved_at_8[0x18]; 3480 3481 u8 syndrome[0x20]; 3482 3483 u8 reserved_at_40[0x40]; 3484 }; 3485 3486 struct mlx5_ifc_sqd2rts_qp_in_bits { 3487 u8 opcode[0x10]; 3488 u8 uid[0x10]; 3489 3490 u8 reserved_at_20[0x10]; 3491 u8 op_mod[0x10]; 3492 3493 u8 reserved_at_40[0x8]; 3494 u8 qpn[0x18]; 3495 3496 u8 reserved_at_60[0x20]; 3497 3498 u8 opt_param_mask[0x20]; 3499 3500 u8 reserved_at_a0[0x20]; 3501 3502 struct mlx5_ifc_qpc_bits qpc; 3503 3504 u8 reserved_at_800[0x80]; 3505 }; 3506 3507 struct mlx5_ifc_set_roce_address_out_bits { 3508 u8 status[0x8]; 3509 u8 reserved_at_8[0x18]; 3510 3511 u8 syndrome[0x20]; 3512 3513 u8 reserved_at_40[0x40]; 3514 }; 3515 3516 struct mlx5_ifc_set_roce_address_in_bits { 3517 u8 opcode[0x10]; 3518 u8 reserved_at_10[0x10]; 3519 3520 u8 reserved_at_20[0x10]; 3521 u8 op_mod[0x10]; 3522 3523 u8 roce_address_index[0x10]; 3524 u8 reserved_at_50[0xc]; 3525 u8 vhca_port_num[0x4]; 3526 3527 u8 reserved_at_60[0x20]; 3528 3529 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3530 }; 3531 3532 struct mlx5_ifc_set_mad_demux_out_bits { 3533 u8 status[0x8]; 3534 u8 reserved_at_8[0x18]; 3535 3536 u8 syndrome[0x20]; 3537 3538 u8 reserved_at_40[0x40]; 3539 }; 3540 3541 enum { 3542 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3543 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3544 }; 3545 3546 struct mlx5_ifc_set_mad_demux_in_bits { 3547 u8 opcode[0x10]; 3548 u8 reserved_at_10[0x10]; 3549 3550 u8 reserved_at_20[0x10]; 3551 u8 op_mod[0x10]; 3552 3553 u8 reserved_at_40[0x20]; 3554 3555 u8 reserved_at_60[0x6]; 3556 u8 demux_mode[0x2]; 3557 u8 reserved_at_68[0x18]; 3558 }; 3559 3560 struct mlx5_ifc_set_l2_table_entry_out_bits { 3561 u8 status[0x8]; 3562 u8 reserved_at_8[0x18]; 3563 3564 u8 syndrome[0x20]; 3565 3566 u8 reserved_at_40[0x40]; 3567 }; 3568 3569 struct mlx5_ifc_set_l2_table_entry_in_bits { 3570 u8 opcode[0x10]; 3571 u8 reserved_at_10[0x10]; 3572 3573 u8 reserved_at_20[0x10]; 3574 u8 op_mod[0x10]; 3575 3576 u8 reserved_at_40[0x60]; 3577 3578 u8 reserved_at_a0[0x8]; 3579 u8 table_index[0x18]; 3580 3581 u8 reserved_at_c0[0x20]; 3582 3583 u8 reserved_at_e0[0x13]; 3584 u8 vlan_valid[0x1]; 3585 u8 vlan[0xc]; 3586 3587 struct mlx5_ifc_mac_address_layout_bits mac_address; 3588 3589 u8 reserved_at_140[0xc0]; 3590 }; 3591 3592 struct mlx5_ifc_set_issi_out_bits { 3593 u8 status[0x8]; 3594 u8 reserved_at_8[0x18]; 3595 3596 u8 syndrome[0x20]; 3597 3598 u8 reserved_at_40[0x40]; 3599 }; 3600 3601 struct mlx5_ifc_set_issi_in_bits { 3602 u8 opcode[0x10]; 3603 u8 reserved_at_10[0x10]; 3604 3605 u8 reserved_at_20[0x10]; 3606 u8 op_mod[0x10]; 3607 3608 u8 reserved_at_40[0x10]; 3609 u8 current_issi[0x10]; 3610 3611 u8 reserved_at_60[0x20]; 3612 }; 3613 3614 struct mlx5_ifc_set_hca_cap_out_bits { 3615 u8 status[0x8]; 3616 u8 reserved_at_8[0x18]; 3617 3618 u8 syndrome[0x20]; 3619 3620 u8 reserved_at_40[0x40]; 3621 }; 3622 3623 struct mlx5_ifc_set_hca_cap_in_bits { 3624 u8 opcode[0x10]; 3625 u8 reserved_at_10[0x10]; 3626 3627 u8 reserved_at_20[0x10]; 3628 u8 op_mod[0x10]; 3629 3630 u8 reserved_at_40[0x40]; 3631 3632 union mlx5_ifc_hca_cap_union_bits capability; 3633 }; 3634 3635 enum { 3636 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3637 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3638 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3639 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3640 }; 3641 3642 struct mlx5_ifc_set_fte_out_bits { 3643 u8 status[0x8]; 3644 u8 reserved_at_8[0x18]; 3645 3646 u8 syndrome[0x20]; 3647 3648 u8 reserved_at_40[0x40]; 3649 }; 3650 3651 struct mlx5_ifc_set_fte_in_bits { 3652 u8 opcode[0x10]; 3653 u8 reserved_at_10[0x10]; 3654 3655 u8 reserved_at_20[0x10]; 3656 u8 op_mod[0x10]; 3657 3658 u8 other_vport[0x1]; 3659 u8 reserved_at_41[0xf]; 3660 u8 vport_number[0x10]; 3661 3662 u8 reserved_at_60[0x20]; 3663 3664 u8 table_type[0x8]; 3665 u8 reserved_at_88[0x18]; 3666 3667 u8 reserved_at_a0[0x8]; 3668 u8 table_id[0x18]; 3669 3670 u8 reserved_at_c0[0x18]; 3671 u8 modify_enable_mask[0x8]; 3672 3673 u8 reserved_at_e0[0x20]; 3674 3675 u8 flow_index[0x20]; 3676 3677 u8 reserved_at_120[0xe0]; 3678 3679 struct mlx5_ifc_flow_context_bits flow_context; 3680 }; 3681 3682 struct mlx5_ifc_rts2rts_qp_out_bits { 3683 u8 status[0x8]; 3684 u8 reserved_at_8[0x18]; 3685 3686 u8 syndrome[0x20]; 3687 3688 u8 reserved_at_40[0x40]; 3689 }; 3690 3691 struct mlx5_ifc_rts2rts_qp_in_bits { 3692 u8 opcode[0x10]; 3693 u8 uid[0x10]; 3694 3695 u8 reserved_at_20[0x10]; 3696 u8 op_mod[0x10]; 3697 3698 u8 reserved_at_40[0x8]; 3699 u8 qpn[0x18]; 3700 3701 u8 reserved_at_60[0x20]; 3702 3703 u8 opt_param_mask[0x20]; 3704 3705 u8 reserved_at_a0[0x20]; 3706 3707 struct mlx5_ifc_qpc_bits qpc; 3708 3709 u8 reserved_at_800[0x80]; 3710 }; 3711 3712 struct mlx5_ifc_rtr2rts_qp_out_bits { 3713 u8 status[0x8]; 3714 u8 reserved_at_8[0x18]; 3715 3716 u8 syndrome[0x20]; 3717 3718 u8 reserved_at_40[0x40]; 3719 }; 3720 3721 struct mlx5_ifc_rtr2rts_qp_in_bits { 3722 u8 opcode[0x10]; 3723 u8 uid[0x10]; 3724 3725 u8 reserved_at_20[0x10]; 3726 u8 op_mod[0x10]; 3727 3728 u8 reserved_at_40[0x8]; 3729 u8 qpn[0x18]; 3730 3731 u8 reserved_at_60[0x20]; 3732 3733 u8 opt_param_mask[0x20]; 3734 3735 u8 reserved_at_a0[0x20]; 3736 3737 struct mlx5_ifc_qpc_bits qpc; 3738 3739 u8 reserved_at_800[0x80]; 3740 }; 3741 3742 struct mlx5_ifc_rst2init_qp_out_bits { 3743 u8 status[0x8]; 3744 u8 reserved_at_8[0x18]; 3745 3746 u8 syndrome[0x20]; 3747 3748 u8 reserved_at_40[0x40]; 3749 }; 3750 3751 struct mlx5_ifc_rst2init_qp_in_bits { 3752 u8 opcode[0x10]; 3753 u8 uid[0x10]; 3754 3755 u8 reserved_at_20[0x10]; 3756 u8 op_mod[0x10]; 3757 3758 u8 reserved_at_40[0x8]; 3759 u8 qpn[0x18]; 3760 3761 u8 reserved_at_60[0x20]; 3762 3763 u8 opt_param_mask[0x20]; 3764 3765 u8 reserved_at_a0[0x20]; 3766 3767 struct mlx5_ifc_qpc_bits qpc; 3768 3769 u8 reserved_at_800[0x80]; 3770 }; 3771 3772 struct mlx5_ifc_query_xrq_out_bits { 3773 u8 status[0x8]; 3774 u8 reserved_at_8[0x18]; 3775 3776 u8 syndrome[0x20]; 3777 3778 u8 reserved_at_40[0x40]; 3779 3780 struct mlx5_ifc_xrqc_bits xrq_context; 3781 }; 3782 3783 struct mlx5_ifc_query_xrq_in_bits { 3784 u8 opcode[0x10]; 3785 u8 reserved_at_10[0x10]; 3786 3787 u8 reserved_at_20[0x10]; 3788 u8 op_mod[0x10]; 3789 3790 u8 reserved_at_40[0x8]; 3791 u8 xrqn[0x18]; 3792 3793 u8 reserved_at_60[0x20]; 3794 }; 3795 3796 struct mlx5_ifc_query_xrc_srq_out_bits { 3797 u8 status[0x8]; 3798 u8 reserved_at_8[0x18]; 3799 3800 u8 syndrome[0x20]; 3801 3802 u8 reserved_at_40[0x40]; 3803 3804 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3805 3806 u8 reserved_at_280[0x600]; 3807 3808 u8 pas[0][0x40]; 3809 }; 3810 3811 struct mlx5_ifc_query_xrc_srq_in_bits { 3812 u8 opcode[0x10]; 3813 u8 reserved_at_10[0x10]; 3814 3815 u8 reserved_at_20[0x10]; 3816 u8 op_mod[0x10]; 3817 3818 u8 reserved_at_40[0x8]; 3819 u8 xrc_srqn[0x18]; 3820 3821 u8 reserved_at_60[0x20]; 3822 }; 3823 3824 enum { 3825 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3826 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3827 }; 3828 3829 struct mlx5_ifc_query_vport_state_out_bits { 3830 u8 status[0x8]; 3831 u8 reserved_at_8[0x18]; 3832 3833 u8 syndrome[0x20]; 3834 3835 u8 reserved_at_40[0x20]; 3836 3837 u8 reserved_at_60[0x18]; 3838 u8 admin_state[0x4]; 3839 u8 state[0x4]; 3840 }; 3841 3842 enum { 3843 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3844 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3845 }; 3846 3847 struct mlx5_ifc_arm_monitor_counter_in_bits { 3848 u8 opcode[0x10]; 3849 u8 uid[0x10]; 3850 3851 u8 reserved_at_20[0x10]; 3852 u8 op_mod[0x10]; 3853 3854 u8 reserved_at_40[0x20]; 3855 3856 u8 reserved_at_60[0x20]; 3857 }; 3858 3859 struct mlx5_ifc_arm_monitor_counter_out_bits { 3860 u8 status[0x8]; 3861 u8 reserved_at_8[0x18]; 3862 3863 u8 syndrome[0x20]; 3864 3865 u8 reserved_at_40[0x40]; 3866 }; 3867 3868 enum { 3869 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3870 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3871 }; 3872 3873 enum mlx5_monitor_counter_ppcnt { 3874 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 3875 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 3876 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 3877 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 3878 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 3879 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 3880 }; 3881 3882 enum { 3883 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 3884 }; 3885 3886 struct mlx5_ifc_monitor_counter_output_bits { 3887 u8 reserved_at_0[0x4]; 3888 u8 type[0x4]; 3889 u8 reserved_at_8[0x8]; 3890 u8 counter[0x10]; 3891 3892 u8 counter_group_id[0x20]; 3893 }; 3894 3895 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 3896 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 3897 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 3898 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 3899 3900 struct mlx5_ifc_set_monitor_counter_in_bits { 3901 u8 opcode[0x10]; 3902 u8 uid[0x10]; 3903 3904 u8 reserved_at_20[0x10]; 3905 u8 op_mod[0x10]; 3906 3907 u8 reserved_at_40[0x10]; 3908 u8 num_of_counters[0x10]; 3909 3910 u8 reserved_at_60[0x20]; 3911 3912 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 3913 }; 3914 3915 struct mlx5_ifc_set_monitor_counter_out_bits { 3916 u8 status[0x8]; 3917 u8 reserved_at_8[0x18]; 3918 3919 u8 syndrome[0x20]; 3920 3921 u8 reserved_at_40[0x40]; 3922 }; 3923 3924 struct mlx5_ifc_query_vport_state_in_bits { 3925 u8 opcode[0x10]; 3926 u8 reserved_at_10[0x10]; 3927 3928 u8 reserved_at_20[0x10]; 3929 u8 op_mod[0x10]; 3930 3931 u8 other_vport[0x1]; 3932 u8 reserved_at_41[0xf]; 3933 u8 vport_number[0x10]; 3934 3935 u8 reserved_at_60[0x20]; 3936 }; 3937 3938 struct mlx5_ifc_query_vnic_env_out_bits { 3939 u8 status[0x8]; 3940 u8 reserved_at_8[0x18]; 3941 3942 u8 syndrome[0x20]; 3943 3944 u8 reserved_at_40[0x40]; 3945 3946 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3947 }; 3948 3949 enum { 3950 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3951 }; 3952 3953 struct mlx5_ifc_query_vnic_env_in_bits { 3954 u8 opcode[0x10]; 3955 u8 reserved_at_10[0x10]; 3956 3957 u8 reserved_at_20[0x10]; 3958 u8 op_mod[0x10]; 3959 3960 u8 other_vport[0x1]; 3961 u8 reserved_at_41[0xf]; 3962 u8 vport_number[0x10]; 3963 3964 u8 reserved_at_60[0x20]; 3965 }; 3966 3967 struct mlx5_ifc_query_vport_counter_out_bits { 3968 u8 status[0x8]; 3969 u8 reserved_at_8[0x18]; 3970 3971 u8 syndrome[0x20]; 3972 3973 u8 reserved_at_40[0x40]; 3974 3975 struct mlx5_ifc_traffic_counter_bits received_errors; 3976 3977 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3978 3979 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3980 3981 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3982 3983 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3984 3985 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3986 3987 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3988 3989 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3990 3991 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3992 3993 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3994 3995 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3996 3997 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3998 3999 u8 reserved_at_680[0xa00]; 4000 }; 4001 4002 enum { 4003 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4004 }; 4005 4006 struct mlx5_ifc_query_vport_counter_in_bits { 4007 u8 opcode[0x10]; 4008 u8 reserved_at_10[0x10]; 4009 4010 u8 reserved_at_20[0x10]; 4011 u8 op_mod[0x10]; 4012 4013 u8 other_vport[0x1]; 4014 u8 reserved_at_41[0xb]; 4015 u8 port_num[0x4]; 4016 u8 vport_number[0x10]; 4017 4018 u8 reserved_at_60[0x60]; 4019 4020 u8 clear[0x1]; 4021 u8 reserved_at_c1[0x1f]; 4022 4023 u8 reserved_at_e0[0x20]; 4024 }; 4025 4026 struct mlx5_ifc_query_tis_out_bits { 4027 u8 status[0x8]; 4028 u8 reserved_at_8[0x18]; 4029 4030 u8 syndrome[0x20]; 4031 4032 u8 reserved_at_40[0x40]; 4033 4034 struct mlx5_ifc_tisc_bits tis_context; 4035 }; 4036 4037 struct mlx5_ifc_query_tis_in_bits { 4038 u8 opcode[0x10]; 4039 u8 reserved_at_10[0x10]; 4040 4041 u8 reserved_at_20[0x10]; 4042 u8 op_mod[0x10]; 4043 4044 u8 reserved_at_40[0x8]; 4045 u8 tisn[0x18]; 4046 4047 u8 reserved_at_60[0x20]; 4048 }; 4049 4050 struct mlx5_ifc_query_tir_out_bits { 4051 u8 status[0x8]; 4052 u8 reserved_at_8[0x18]; 4053 4054 u8 syndrome[0x20]; 4055 4056 u8 reserved_at_40[0xc0]; 4057 4058 struct mlx5_ifc_tirc_bits tir_context; 4059 }; 4060 4061 struct mlx5_ifc_query_tir_in_bits { 4062 u8 opcode[0x10]; 4063 u8 reserved_at_10[0x10]; 4064 4065 u8 reserved_at_20[0x10]; 4066 u8 op_mod[0x10]; 4067 4068 u8 reserved_at_40[0x8]; 4069 u8 tirn[0x18]; 4070 4071 u8 reserved_at_60[0x20]; 4072 }; 4073 4074 struct mlx5_ifc_query_srq_out_bits { 4075 u8 status[0x8]; 4076 u8 reserved_at_8[0x18]; 4077 4078 u8 syndrome[0x20]; 4079 4080 u8 reserved_at_40[0x40]; 4081 4082 struct mlx5_ifc_srqc_bits srq_context_entry; 4083 4084 u8 reserved_at_280[0x600]; 4085 4086 u8 pas[0][0x40]; 4087 }; 4088 4089 struct mlx5_ifc_query_srq_in_bits { 4090 u8 opcode[0x10]; 4091 u8 reserved_at_10[0x10]; 4092 4093 u8 reserved_at_20[0x10]; 4094 u8 op_mod[0x10]; 4095 4096 u8 reserved_at_40[0x8]; 4097 u8 srqn[0x18]; 4098 4099 u8 reserved_at_60[0x20]; 4100 }; 4101 4102 struct mlx5_ifc_query_sq_out_bits { 4103 u8 status[0x8]; 4104 u8 reserved_at_8[0x18]; 4105 4106 u8 syndrome[0x20]; 4107 4108 u8 reserved_at_40[0xc0]; 4109 4110 struct mlx5_ifc_sqc_bits sq_context; 4111 }; 4112 4113 struct mlx5_ifc_query_sq_in_bits { 4114 u8 opcode[0x10]; 4115 u8 reserved_at_10[0x10]; 4116 4117 u8 reserved_at_20[0x10]; 4118 u8 op_mod[0x10]; 4119 4120 u8 reserved_at_40[0x8]; 4121 u8 sqn[0x18]; 4122 4123 u8 reserved_at_60[0x20]; 4124 }; 4125 4126 struct mlx5_ifc_query_special_contexts_out_bits { 4127 u8 status[0x8]; 4128 u8 reserved_at_8[0x18]; 4129 4130 u8 syndrome[0x20]; 4131 4132 u8 dump_fill_mkey[0x20]; 4133 4134 u8 resd_lkey[0x20]; 4135 4136 u8 null_mkey[0x20]; 4137 4138 u8 reserved_at_a0[0x60]; 4139 }; 4140 4141 struct mlx5_ifc_query_special_contexts_in_bits { 4142 u8 opcode[0x10]; 4143 u8 reserved_at_10[0x10]; 4144 4145 u8 reserved_at_20[0x10]; 4146 u8 op_mod[0x10]; 4147 4148 u8 reserved_at_40[0x40]; 4149 }; 4150 4151 struct mlx5_ifc_query_scheduling_element_out_bits { 4152 u8 opcode[0x10]; 4153 u8 reserved_at_10[0x10]; 4154 4155 u8 reserved_at_20[0x10]; 4156 u8 op_mod[0x10]; 4157 4158 u8 reserved_at_40[0xc0]; 4159 4160 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4161 4162 u8 reserved_at_300[0x100]; 4163 }; 4164 4165 enum { 4166 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4167 }; 4168 4169 struct mlx5_ifc_query_scheduling_element_in_bits { 4170 u8 opcode[0x10]; 4171 u8 reserved_at_10[0x10]; 4172 4173 u8 reserved_at_20[0x10]; 4174 u8 op_mod[0x10]; 4175 4176 u8 scheduling_hierarchy[0x8]; 4177 u8 reserved_at_48[0x18]; 4178 4179 u8 scheduling_element_id[0x20]; 4180 4181 u8 reserved_at_80[0x180]; 4182 }; 4183 4184 struct mlx5_ifc_query_rqt_out_bits { 4185 u8 status[0x8]; 4186 u8 reserved_at_8[0x18]; 4187 4188 u8 syndrome[0x20]; 4189 4190 u8 reserved_at_40[0xc0]; 4191 4192 struct mlx5_ifc_rqtc_bits rqt_context; 4193 }; 4194 4195 struct mlx5_ifc_query_rqt_in_bits { 4196 u8 opcode[0x10]; 4197 u8 reserved_at_10[0x10]; 4198 4199 u8 reserved_at_20[0x10]; 4200 u8 op_mod[0x10]; 4201 4202 u8 reserved_at_40[0x8]; 4203 u8 rqtn[0x18]; 4204 4205 u8 reserved_at_60[0x20]; 4206 }; 4207 4208 struct mlx5_ifc_query_rq_out_bits { 4209 u8 status[0x8]; 4210 u8 reserved_at_8[0x18]; 4211 4212 u8 syndrome[0x20]; 4213 4214 u8 reserved_at_40[0xc0]; 4215 4216 struct mlx5_ifc_rqc_bits rq_context; 4217 }; 4218 4219 struct mlx5_ifc_query_rq_in_bits { 4220 u8 opcode[0x10]; 4221 u8 reserved_at_10[0x10]; 4222 4223 u8 reserved_at_20[0x10]; 4224 u8 op_mod[0x10]; 4225 4226 u8 reserved_at_40[0x8]; 4227 u8 rqn[0x18]; 4228 4229 u8 reserved_at_60[0x20]; 4230 }; 4231 4232 struct mlx5_ifc_query_roce_address_out_bits { 4233 u8 status[0x8]; 4234 u8 reserved_at_8[0x18]; 4235 4236 u8 syndrome[0x20]; 4237 4238 u8 reserved_at_40[0x40]; 4239 4240 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4241 }; 4242 4243 struct mlx5_ifc_query_roce_address_in_bits { 4244 u8 opcode[0x10]; 4245 u8 reserved_at_10[0x10]; 4246 4247 u8 reserved_at_20[0x10]; 4248 u8 op_mod[0x10]; 4249 4250 u8 roce_address_index[0x10]; 4251 u8 reserved_at_50[0xc]; 4252 u8 vhca_port_num[0x4]; 4253 4254 u8 reserved_at_60[0x20]; 4255 }; 4256 4257 struct mlx5_ifc_query_rmp_out_bits { 4258 u8 status[0x8]; 4259 u8 reserved_at_8[0x18]; 4260 4261 u8 syndrome[0x20]; 4262 4263 u8 reserved_at_40[0xc0]; 4264 4265 struct mlx5_ifc_rmpc_bits rmp_context; 4266 }; 4267 4268 struct mlx5_ifc_query_rmp_in_bits { 4269 u8 opcode[0x10]; 4270 u8 reserved_at_10[0x10]; 4271 4272 u8 reserved_at_20[0x10]; 4273 u8 op_mod[0x10]; 4274 4275 u8 reserved_at_40[0x8]; 4276 u8 rmpn[0x18]; 4277 4278 u8 reserved_at_60[0x20]; 4279 }; 4280 4281 struct mlx5_ifc_query_qp_out_bits { 4282 u8 status[0x8]; 4283 u8 reserved_at_8[0x18]; 4284 4285 u8 syndrome[0x20]; 4286 4287 u8 reserved_at_40[0x40]; 4288 4289 u8 opt_param_mask[0x20]; 4290 4291 u8 reserved_at_a0[0x20]; 4292 4293 struct mlx5_ifc_qpc_bits qpc; 4294 4295 u8 reserved_at_800[0x80]; 4296 4297 u8 pas[0][0x40]; 4298 }; 4299 4300 struct mlx5_ifc_query_qp_in_bits { 4301 u8 opcode[0x10]; 4302 u8 reserved_at_10[0x10]; 4303 4304 u8 reserved_at_20[0x10]; 4305 u8 op_mod[0x10]; 4306 4307 u8 reserved_at_40[0x8]; 4308 u8 qpn[0x18]; 4309 4310 u8 reserved_at_60[0x20]; 4311 }; 4312 4313 struct mlx5_ifc_query_q_counter_out_bits { 4314 u8 status[0x8]; 4315 u8 reserved_at_8[0x18]; 4316 4317 u8 syndrome[0x20]; 4318 4319 u8 reserved_at_40[0x40]; 4320 4321 u8 rx_write_requests[0x20]; 4322 4323 u8 reserved_at_a0[0x20]; 4324 4325 u8 rx_read_requests[0x20]; 4326 4327 u8 reserved_at_e0[0x20]; 4328 4329 u8 rx_atomic_requests[0x20]; 4330 4331 u8 reserved_at_120[0x20]; 4332 4333 u8 rx_dct_connect[0x20]; 4334 4335 u8 reserved_at_160[0x20]; 4336 4337 u8 out_of_buffer[0x20]; 4338 4339 u8 reserved_at_1a0[0x20]; 4340 4341 u8 out_of_sequence[0x20]; 4342 4343 u8 reserved_at_1e0[0x20]; 4344 4345 u8 duplicate_request[0x20]; 4346 4347 u8 reserved_at_220[0x20]; 4348 4349 u8 rnr_nak_retry_err[0x20]; 4350 4351 u8 reserved_at_260[0x20]; 4352 4353 u8 packet_seq_err[0x20]; 4354 4355 u8 reserved_at_2a0[0x20]; 4356 4357 u8 implied_nak_seq_err[0x20]; 4358 4359 u8 reserved_at_2e0[0x20]; 4360 4361 u8 local_ack_timeout_err[0x20]; 4362 4363 u8 reserved_at_320[0xa0]; 4364 4365 u8 resp_local_length_error[0x20]; 4366 4367 u8 req_local_length_error[0x20]; 4368 4369 u8 resp_local_qp_error[0x20]; 4370 4371 u8 local_operation_error[0x20]; 4372 4373 u8 resp_local_protection[0x20]; 4374 4375 u8 req_local_protection[0x20]; 4376 4377 u8 resp_cqe_error[0x20]; 4378 4379 u8 req_cqe_error[0x20]; 4380 4381 u8 req_mw_binding[0x20]; 4382 4383 u8 req_bad_response[0x20]; 4384 4385 u8 req_remote_invalid_request[0x20]; 4386 4387 u8 resp_remote_invalid_request[0x20]; 4388 4389 u8 req_remote_access_errors[0x20]; 4390 4391 u8 resp_remote_access_errors[0x20]; 4392 4393 u8 req_remote_operation_errors[0x20]; 4394 4395 u8 req_transport_retries_exceeded[0x20]; 4396 4397 u8 cq_overflow[0x20]; 4398 4399 u8 resp_cqe_flush_error[0x20]; 4400 4401 u8 req_cqe_flush_error[0x20]; 4402 4403 u8 reserved_at_620[0x1e0]; 4404 }; 4405 4406 struct mlx5_ifc_query_q_counter_in_bits { 4407 u8 opcode[0x10]; 4408 u8 reserved_at_10[0x10]; 4409 4410 u8 reserved_at_20[0x10]; 4411 u8 op_mod[0x10]; 4412 4413 u8 reserved_at_40[0x80]; 4414 4415 u8 clear[0x1]; 4416 u8 reserved_at_c1[0x1f]; 4417 4418 u8 reserved_at_e0[0x18]; 4419 u8 counter_set_id[0x8]; 4420 }; 4421 4422 struct mlx5_ifc_query_pages_out_bits { 4423 u8 status[0x8]; 4424 u8 reserved_at_8[0x18]; 4425 4426 u8 syndrome[0x20]; 4427 4428 u8 reserved_at_40[0x10]; 4429 u8 function_id[0x10]; 4430 4431 u8 num_pages[0x20]; 4432 }; 4433 4434 enum { 4435 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4436 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4437 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4438 }; 4439 4440 struct mlx5_ifc_query_pages_in_bits { 4441 u8 opcode[0x10]; 4442 u8 reserved_at_10[0x10]; 4443 4444 u8 reserved_at_20[0x10]; 4445 u8 op_mod[0x10]; 4446 4447 u8 reserved_at_40[0x10]; 4448 u8 function_id[0x10]; 4449 4450 u8 reserved_at_60[0x20]; 4451 }; 4452 4453 struct mlx5_ifc_query_nic_vport_context_out_bits { 4454 u8 status[0x8]; 4455 u8 reserved_at_8[0x18]; 4456 4457 u8 syndrome[0x20]; 4458 4459 u8 reserved_at_40[0x40]; 4460 4461 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4462 }; 4463 4464 struct mlx5_ifc_query_nic_vport_context_in_bits { 4465 u8 opcode[0x10]; 4466 u8 reserved_at_10[0x10]; 4467 4468 u8 reserved_at_20[0x10]; 4469 u8 op_mod[0x10]; 4470 4471 u8 other_vport[0x1]; 4472 u8 reserved_at_41[0xf]; 4473 u8 vport_number[0x10]; 4474 4475 u8 reserved_at_60[0x5]; 4476 u8 allowed_list_type[0x3]; 4477 u8 reserved_at_68[0x18]; 4478 }; 4479 4480 struct mlx5_ifc_query_mkey_out_bits { 4481 u8 status[0x8]; 4482 u8 reserved_at_8[0x18]; 4483 4484 u8 syndrome[0x20]; 4485 4486 u8 reserved_at_40[0x40]; 4487 4488 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4489 4490 u8 reserved_at_280[0x600]; 4491 4492 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4493 4494 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4495 }; 4496 4497 struct mlx5_ifc_query_mkey_in_bits { 4498 u8 opcode[0x10]; 4499 u8 reserved_at_10[0x10]; 4500 4501 u8 reserved_at_20[0x10]; 4502 u8 op_mod[0x10]; 4503 4504 u8 reserved_at_40[0x8]; 4505 u8 mkey_index[0x18]; 4506 4507 u8 pg_access[0x1]; 4508 u8 reserved_at_61[0x1f]; 4509 }; 4510 4511 struct mlx5_ifc_query_mad_demux_out_bits { 4512 u8 status[0x8]; 4513 u8 reserved_at_8[0x18]; 4514 4515 u8 syndrome[0x20]; 4516 4517 u8 reserved_at_40[0x40]; 4518 4519 u8 mad_dumux_parameters_block[0x20]; 4520 }; 4521 4522 struct mlx5_ifc_query_mad_demux_in_bits { 4523 u8 opcode[0x10]; 4524 u8 reserved_at_10[0x10]; 4525 4526 u8 reserved_at_20[0x10]; 4527 u8 op_mod[0x10]; 4528 4529 u8 reserved_at_40[0x40]; 4530 }; 4531 4532 struct mlx5_ifc_query_l2_table_entry_out_bits { 4533 u8 status[0x8]; 4534 u8 reserved_at_8[0x18]; 4535 4536 u8 syndrome[0x20]; 4537 4538 u8 reserved_at_40[0xa0]; 4539 4540 u8 reserved_at_e0[0x13]; 4541 u8 vlan_valid[0x1]; 4542 u8 vlan[0xc]; 4543 4544 struct mlx5_ifc_mac_address_layout_bits mac_address; 4545 4546 u8 reserved_at_140[0xc0]; 4547 }; 4548 4549 struct mlx5_ifc_query_l2_table_entry_in_bits { 4550 u8 opcode[0x10]; 4551 u8 reserved_at_10[0x10]; 4552 4553 u8 reserved_at_20[0x10]; 4554 u8 op_mod[0x10]; 4555 4556 u8 reserved_at_40[0x60]; 4557 4558 u8 reserved_at_a0[0x8]; 4559 u8 table_index[0x18]; 4560 4561 u8 reserved_at_c0[0x140]; 4562 }; 4563 4564 struct mlx5_ifc_query_issi_out_bits { 4565 u8 status[0x8]; 4566 u8 reserved_at_8[0x18]; 4567 4568 u8 syndrome[0x20]; 4569 4570 u8 reserved_at_40[0x10]; 4571 u8 current_issi[0x10]; 4572 4573 u8 reserved_at_60[0xa0]; 4574 4575 u8 reserved_at_100[76][0x8]; 4576 u8 supported_issi_dw0[0x20]; 4577 }; 4578 4579 struct mlx5_ifc_query_issi_in_bits { 4580 u8 opcode[0x10]; 4581 u8 reserved_at_10[0x10]; 4582 4583 u8 reserved_at_20[0x10]; 4584 u8 op_mod[0x10]; 4585 4586 u8 reserved_at_40[0x40]; 4587 }; 4588 4589 struct mlx5_ifc_set_driver_version_out_bits { 4590 u8 status[0x8]; 4591 u8 reserved_0[0x18]; 4592 4593 u8 syndrome[0x20]; 4594 u8 reserved_1[0x40]; 4595 }; 4596 4597 struct mlx5_ifc_set_driver_version_in_bits { 4598 u8 opcode[0x10]; 4599 u8 reserved_0[0x10]; 4600 4601 u8 reserved_1[0x10]; 4602 u8 op_mod[0x10]; 4603 4604 u8 reserved_2[0x40]; 4605 u8 driver_version[64][0x8]; 4606 }; 4607 4608 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4609 u8 status[0x8]; 4610 u8 reserved_at_8[0x18]; 4611 4612 u8 syndrome[0x20]; 4613 4614 u8 reserved_at_40[0x40]; 4615 4616 struct mlx5_ifc_pkey_bits pkey[0]; 4617 }; 4618 4619 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4620 u8 opcode[0x10]; 4621 u8 reserved_at_10[0x10]; 4622 4623 u8 reserved_at_20[0x10]; 4624 u8 op_mod[0x10]; 4625 4626 u8 other_vport[0x1]; 4627 u8 reserved_at_41[0xb]; 4628 u8 port_num[0x4]; 4629 u8 vport_number[0x10]; 4630 4631 u8 reserved_at_60[0x10]; 4632 u8 pkey_index[0x10]; 4633 }; 4634 4635 enum { 4636 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4637 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4638 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4639 }; 4640 4641 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4642 u8 status[0x8]; 4643 u8 reserved_at_8[0x18]; 4644 4645 u8 syndrome[0x20]; 4646 4647 u8 reserved_at_40[0x20]; 4648 4649 u8 gids_num[0x10]; 4650 u8 reserved_at_70[0x10]; 4651 4652 struct mlx5_ifc_array128_auto_bits gid[0]; 4653 }; 4654 4655 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4656 u8 opcode[0x10]; 4657 u8 reserved_at_10[0x10]; 4658 4659 u8 reserved_at_20[0x10]; 4660 u8 op_mod[0x10]; 4661 4662 u8 other_vport[0x1]; 4663 u8 reserved_at_41[0xb]; 4664 u8 port_num[0x4]; 4665 u8 vport_number[0x10]; 4666 4667 u8 reserved_at_60[0x10]; 4668 u8 gid_index[0x10]; 4669 }; 4670 4671 struct mlx5_ifc_query_hca_vport_context_out_bits { 4672 u8 status[0x8]; 4673 u8 reserved_at_8[0x18]; 4674 4675 u8 syndrome[0x20]; 4676 4677 u8 reserved_at_40[0x40]; 4678 4679 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4680 }; 4681 4682 struct mlx5_ifc_query_hca_vport_context_in_bits { 4683 u8 opcode[0x10]; 4684 u8 reserved_at_10[0x10]; 4685 4686 u8 reserved_at_20[0x10]; 4687 u8 op_mod[0x10]; 4688 4689 u8 other_vport[0x1]; 4690 u8 reserved_at_41[0xb]; 4691 u8 port_num[0x4]; 4692 u8 vport_number[0x10]; 4693 4694 u8 reserved_at_60[0x20]; 4695 }; 4696 4697 struct mlx5_ifc_query_hca_cap_out_bits { 4698 u8 status[0x8]; 4699 u8 reserved_at_8[0x18]; 4700 4701 u8 syndrome[0x20]; 4702 4703 u8 reserved_at_40[0x40]; 4704 4705 union mlx5_ifc_hca_cap_union_bits capability; 4706 }; 4707 4708 struct mlx5_ifc_query_hca_cap_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 reserved_at_40[0x40]; 4716 }; 4717 4718 struct mlx5_ifc_query_flow_table_out_bits { 4719 u8 status[0x8]; 4720 u8 reserved_at_8[0x18]; 4721 4722 u8 syndrome[0x20]; 4723 4724 u8 reserved_at_40[0x80]; 4725 4726 u8 reserved_at_c0[0x8]; 4727 u8 level[0x8]; 4728 u8 reserved_at_d0[0x8]; 4729 u8 log_size[0x8]; 4730 4731 u8 reserved_at_e0[0x120]; 4732 }; 4733 4734 struct mlx5_ifc_query_flow_table_in_bits { 4735 u8 opcode[0x10]; 4736 u8 reserved_at_10[0x10]; 4737 4738 u8 reserved_at_20[0x10]; 4739 u8 op_mod[0x10]; 4740 4741 u8 reserved_at_40[0x40]; 4742 4743 u8 table_type[0x8]; 4744 u8 reserved_at_88[0x18]; 4745 4746 u8 reserved_at_a0[0x8]; 4747 u8 table_id[0x18]; 4748 4749 u8 reserved_at_c0[0x140]; 4750 }; 4751 4752 struct mlx5_ifc_query_fte_out_bits { 4753 u8 status[0x8]; 4754 u8 reserved_at_8[0x18]; 4755 4756 u8 syndrome[0x20]; 4757 4758 u8 reserved_at_40[0x1c0]; 4759 4760 struct mlx5_ifc_flow_context_bits flow_context; 4761 }; 4762 4763 struct mlx5_ifc_query_fte_in_bits { 4764 u8 opcode[0x10]; 4765 u8 reserved_at_10[0x10]; 4766 4767 u8 reserved_at_20[0x10]; 4768 u8 op_mod[0x10]; 4769 4770 u8 reserved_at_40[0x40]; 4771 4772 u8 table_type[0x8]; 4773 u8 reserved_at_88[0x18]; 4774 4775 u8 reserved_at_a0[0x8]; 4776 u8 table_id[0x18]; 4777 4778 u8 reserved_at_c0[0x40]; 4779 4780 u8 flow_index[0x20]; 4781 4782 u8 reserved_at_120[0xe0]; 4783 }; 4784 4785 enum { 4786 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4787 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4788 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4789 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 4790 }; 4791 4792 struct mlx5_ifc_query_flow_group_out_bits { 4793 u8 status[0x8]; 4794 u8 reserved_at_8[0x18]; 4795 4796 u8 syndrome[0x20]; 4797 4798 u8 reserved_at_40[0xa0]; 4799 4800 u8 start_flow_index[0x20]; 4801 4802 u8 reserved_at_100[0x20]; 4803 4804 u8 end_flow_index[0x20]; 4805 4806 u8 reserved_at_140[0xa0]; 4807 4808 u8 reserved_at_1e0[0x18]; 4809 u8 match_criteria_enable[0x8]; 4810 4811 struct mlx5_ifc_fte_match_param_bits match_criteria; 4812 4813 u8 reserved_at_1200[0xe00]; 4814 }; 4815 4816 struct mlx5_ifc_query_flow_group_in_bits { 4817 u8 opcode[0x10]; 4818 u8 reserved_at_10[0x10]; 4819 4820 u8 reserved_at_20[0x10]; 4821 u8 op_mod[0x10]; 4822 4823 u8 reserved_at_40[0x40]; 4824 4825 u8 table_type[0x8]; 4826 u8 reserved_at_88[0x18]; 4827 4828 u8 reserved_at_a0[0x8]; 4829 u8 table_id[0x18]; 4830 4831 u8 group_id[0x20]; 4832 4833 u8 reserved_at_e0[0x120]; 4834 }; 4835 4836 struct mlx5_ifc_query_flow_counter_out_bits { 4837 u8 status[0x8]; 4838 u8 reserved_at_8[0x18]; 4839 4840 u8 syndrome[0x20]; 4841 4842 u8 reserved_at_40[0x40]; 4843 4844 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4845 }; 4846 4847 struct mlx5_ifc_query_flow_counter_in_bits { 4848 u8 opcode[0x10]; 4849 u8 reserved_at_10[0x10]; 4850 4851 u8 reserved_at_20[0x10]; 4852 u8 op_mod[0x10]; 4853 4854 u8 reserved_at_40[0x80]; 4855 4856 u8 clear[0x1]; 4857 u8 reserved_at_c1[0xf]; 4858 u8 num_of_counters[0x10]; 4859 4860 u8 flow_counter_id[0x20]; 4861 }; 4862 4863 struct mlx5_ifc_query_esw_vport_context_out_bits { 4864 u8 status[0x8]; 4865 u8 reserved_at_8[0x18]; 4866 4867 u8 syndrome[0x20]; 4868 4869 u8 reserved_at_40[0x40]; 4870 4871 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4872 }; 4873 4874 struct mlx5_ifc_query_esw_vport_context_in_bits { 4875 u8 opcode[0x10]; 4876 u8 reserved_at_10[0x10]; 4877 4878 u8 reserved_at_20[0x10]; 4879 u8 op_mod[0x10]; 4880 4881 u8 other_vport[0x1]; 4882 u8 reserved_at_41[0xf]; 4883 u8 vport_number[0x10]; 4884 4885 u8 reserved_at_60[0x20]; 4886 }; 4887 4888 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4889 u8 status[0x8]; 4890 u8 reserved_at_8[0x18]; 4891 4892 u8 syndrome[0x20]; 4893 4894 u8 reserved_at_40[0x40]; 4895 }; 4896 4897 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4898 u8 reserved_at_0[0x1c]; 4899 u8 vport_cvlan_insert[0x1]; 4900 u8 vport_svlan_insert[0x1]; 4901 u8 vport_cvlan_strip[0x1]; 4902 u8 vport_svlan_strip[0x1]; 4903 }; 4904 4905 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4906 u8 opcode[0x10]; 4907 u8 reserved_at_10[0x10]; 4908 4909 u8 reserved_at_20[0x10]; 4910 u8 op_mod[0x10]; 4911 4912 u8 other_vport[0x1]; 4913 u8 reserved_at_41[0xf]; 4914 u8 vport_number[0x10]; 4915 4916 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4917 4918 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4919 }; 4920 4921 struct mlx5_ifc_query_eq_out_bits { 4922 u8 status[0x8]; 4923 u8 reserved_at_8[0x18]; 4924 4925 u8 syndrome[0x20]; 4926 4927 u8 reserved_at_40[0x40]; 4928 4929 struct mlx5_ifc_eqc_bits eq_context_entry; 4930 4931 u8 reserved_at_280[0x40]; 4932 4933 u8 event_bitmask[0x40]; 4934 4935 u8 reserved_at_300[0x580]; 4936 4937 u8 pas[0][0x40]; 4938 }; 4939 4940 struct mlx5_ifc_query_eq_in_bits { 4941 u8 opcode[0x10]; 4942 u8 reserved_at_10[0x10]; 4943 4944 u8 reserved_at_20[0x10]; 4945 u8 op_mod[0x10]; 4946 4947 u8 reserved_at_40[0x18]; 4948 u8 eq_number[0x8]; 4949 4950 u8 reserved_at_60[0x20]; 4951 }; 4952 4953 struct mlx5_ifc_packet_reformat_context_in_bits { 4954 u8 reserved_at_0[0x5]; 4955 u8 reformat_type[0x3]; 4956 u8 reserved_at_8[0xe]; 4957 u8 reformat_data_size[0xa]; 4958 4959 u8 reserved_at_20[0x10]; 4960 u8 reformat_data[2][0x8]; 4961 4962 u8 more_reformat_data[0][0x8]; 4963 }; 4964 4965 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0xa0]; 4972 4973 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4974 }; 4975 4976 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4977 u8 opcode[0x10]; 4978 u8 reserved_at_10[0x10]; 4979 4980 u8 reserved_at_20[0x10]; 4981 u8 op_mod[0x10]; 4982 4983 u8 packet_reformat_id[0x20]; 4984 4985 u8 reserved_at_60[0xa0]; 4986 }; 4987 4988 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 4989 u8 status[0x8]; 4990 u8 reserved_at_8[0x18]; 4991 4992 u8 syndrome[0x20]; 4993 4994 u8 packet_reformat_id[0x20]; 4995 4996 u8 reserved_at_60[0x20]; 4997 }; 4998 4999 enum { 5000 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5001 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5002 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5003 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5004 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5005 }; 5006 5007 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5008 u8 opcode[0x10]; 5009 u8 reserved_at_10[0x10]; 5010 5011 u8 reserved_at_20[0x10]; 5012 u8 op_mod[0x10]; 5013 5014 u8 reserved_at_40[0xa0]; 5015 5016 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5017 }; 5018 5019 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5020 u8 status[0x8]; 5021 u8 reserved_at_8[0x18]; 5022 5023 u8 syndrome[0x20]; 5024 5025 u8 reserved_at_40[0x40]; 5026 }; 5027 5028 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5029 u8 opcode[0x10]; 5030 u8 reserved_at_10[0x10]; 5031 5032 u8 reserved_20[0x10]; 5033 u8 op_mod[0x10]; 5034 5035 u8 packet_reformat_id[0x20]; 5036 5037 u8 reserved_60[0x20]; 5038 }; 5039 5040 struct mlx5_ifc_set_action_in_bits { 5041 u8 action_type[0x4]; 5042 u8 field[0xc]; 5043 u8 reserved_at_10[0x3]; 5044 u8 offset[0x5]; 5045 u8 reserved_at_18[0x3]; 5046 u8 length[0x5]; 5047 5048 u8 data[0x20]; 5049 }; 5050 5051 struct mlx5_ifc_add_action_in_bits { 5052 u8 action_type[0x4]; 5053 u8 field[0xc]; 5054 u8 reserved_at_10[0x10]; 5055 5056 u8 data[0x20]; 5057 }; 5058 5059 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5060 struct mlx5_ifc_set_action_in_bits set_action_in; 5061 struct mlx5_ifc_add_action_in_bits add_action_in; 5062 u8 reserved_at_0[0x40]; 5063 }; 5064 5065 enum { 5066 MLX5_ACTION_TYPE_SET = 0x1, 5067 MLX5_ACTION_TYPE_ADD = 0x2, 5068 }; 5069 5070 enum { 5071 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5072 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5073 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5074 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5075 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5076 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5077 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5078 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5079 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5080 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5081 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5082 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5083 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5084 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5085 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5086 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5087 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5088 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5089 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5090 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5091 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5092 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5093 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5094 }; 5095 5096 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5097 u8 status[0x8]; 5098 u8 reserved_at_8[0x18]; 5099 5100 u8 syndrome[0x20]; 5101 5102 u8 modify_header_id[0x20]; 5103 5104 u8 reserved_at_60[0x20]; 5105 }; 5106 5107 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5108 u8 opcode[0x10]; 5109 u8 reserved_at_10[0x10]; 5110 5111 u8 reserved_at_20[0x10]; 5112 u8 op_mod[0x10]; 5113 5114 u8 reserved_at_40[0x20]; 5115 5116 u8 table_type[0x8]; 5117 u8 reserved_at_68[0x10]; 5118 u8 num_of_actions[0x8]; 5119 5120 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5121 }; 5122 5123 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5124 u8 status[0x8]; 5125 u8 reserved_at_8[0x18]; 5126 5127 u8 syndrome[0x20]; 5128 5129 u8 reserved_at_40[0x40]; 5130 }; 5131 5132 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5133 u8 opcode[0x10]; 5134 u8 reserved_at_10[0x10]; 5135 5136 u8 reserved_at_20[0x10]; 5137 u8 op_mod[0x10]; 5138 5139 u8 modify_header_id[0x20]; 5140 5141 u8 reserved_at_60[0x20]; 5142 }; 5143 5144 struct mlx5_ifc_query_dct_out_bits { 5145 u8 status[0x8]; 5146 u8 reserved_at_8[0x18]; 5147 5148 u8 syndrome[0x20]; 5149 5150 u8 reserved_at_40[0x40]; 5151 5152 struct mlx5_ifc_dctc_bits dct_context_entry; 5153 5154 u8 reserved_at_280[0x180]; 5155 }; 5156 5157 struct mlx5_ifc_query_dct_in_bits { 5158 u8 opcode[0x10]; 5159 u8 reserved_at_10[0x10]; 5160 5161 u8 reserved_at_20[0x10]; 5162 u8 op_mod[0x10]; 5163 5164 u8 reserved_at_40[0x8]; 5165 u8 dctn[0x18]; 5166 5167 u8 reserved_at_60[0x20]; 5168 }; 5169 5170 struct mlx5_ifc_query_cq_out_bits { 5171 u8 status[0x8]; 5172 u8 reserved_at_8[0x18]; 5173 5174 u8 syndrome[0x20]; 5175 5176 u8 reserved_at_40[0x40]; 5177 5178 struct mlx5_ifc_cqc_bits cq_context; 5179 5180 u8 reserved_at_280[0x600]; 5181 5182 u8 pas[0][0x40]; 5183 }; 5184 5185 struct mlx5_ifc_query_cq_in_bits { 5186 u8 opcode[0x10]; 5187 u8 reserved_at_10[0x10]; 5188 5189 u8 reserved_at_20[0x10]; 5190 u8 op_mod[0x10]; 5191 5192 u8 reserved_at_40[0x8]; 5193 u8 cqn[0x18]; 5194 5195 u8 reserved_at_60[0x20]; 5196 }; 5197 5198 struct mlx5_ifc_query_cong_status_out_bits { 5199 u8 status[0x8]; 5200 u8 reserved_at_8[0x18]; 5201 5202 u8 syndrome[0x20]; 5203 5204 u8 reserved_at_40[0x20]; 5205 5206 u8 enable[0x1]; 5207 u8 tag_enable[0x1]; 5208 u8 reserved_at_62[0x1e]; 5209 }; 5210 5211 struct mlx5_ifc_query_cong_status_in_bits { 5212 u8 opcode[0x10]; 5213 u8 reserved_at_10[0x10]; 5214 5215 u8 reserved_at_20[0x10]; 5216 u8 op_mod[0x10]; 5217 5218 u8 reserved_at_40[0x18]; 5219 u8 priority[0x4]; 5220 u8 cong_protocol[0x4]; 5221 5222 u8 reserved_at_60[0x20]; 5223 }; 5224 5225 struct mlx5_ifc_query_cong_statistics_out_bits { 5226 u8 status[0x8]; 5227 u8 reserved_at_8[0x18]; 5228 5229 u8 syndrome[0x20]; 5230 5231 u8 reserved_at_40[0x40]; 5232 5233 u8 rp_cur_flows[0x20]; 5234 5235 u8 sum_flows[0x20]; 5236 5237 u8 rp_cnp_ignored_high[0x20]; 5238 5239 u8 rp_cnp_ignored_low[0x20]; 5240 5241 u8 rp_cnp_handled_high[0x20]; 5242 5243 u8 rp_cnp_handled_low[0x20]; 5244 5245 u8 reserved_at_140[0x100]; 5246 5247 u8 time_stamp_high[0x20]; 5248 5249 u8 time_stamp_low[0x20]; 5250 5251 u8 accumulators_period[0x20]; 5252 5253 u8 np_ecn_marked_roce_packets_high[0x20]; 5254 5255 u8 np_ecn_marked_roce_packets_low[0x20]; 5256 5257 u8 np_cnp_sent_high[0x20]; 5258 5259 u8 np_cnp_sent_low[0x20]; 5260 5261 u8 reserved_at_320[0x560]; 5262 }; 5263 5264 struct mlx5_ifc_query_cong_statistics_in_bits { 5265 u8 opcode[0x10]; 5266 u8 reserved_at_10[0x10]; 5267 5268 u8 reserved_at_20[0x10]; 5269 u8 op_mod[0x10]; 5270 5271 u8 clear[0x1]; 5272 u8 reserved_at_41[0x1f]; 5273 5274 u8 reserved_at_60[0x20]; 5275 }; 5276 5277 struct mlx5_ifc_query_cong_params_out_bits { 5278 u8 status[0x8]; 5279 u8 reserved_at_8[0x18]; 5280 5281 u8 syndrome[0x20]; 5282 5283 u8 reserved_at_40[0x40]; 5284 5285 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5286 }; 5287 5288 struct mlx5_ifc_query_cong_params_in_bits { 5289 u8 opcode[0x10]; 5290 u8 reserved_at_10[0x10]; 5291 5292 u8 reserved_at_20[0x10]; 5293 u8 op_mod[0x10]; 5294 5295 u8 reserved_at_40[0x1c]; 5296 u8 cong_protocol[0x4]; 5297 5298 u8 reserved_at_60[0x20]; 5299 }; 5300 5301 struct mlx5_ifc_query_adapter_out_bits { 5302 u8 status[0x8]; 5303 u8 reserved_at_8[0x18]; 5304 5305 u8 syndrome[0x20]; 5306 5307 u8 reserved_at_40[0x40]; 5308 5309 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5310 }; 5311 5312 struct mlx5_ifc_query_adapter_in_bits { 5313 u8 opcode[0x10]; 5314 u8 reserved_at_10[0x10]; 5315 5316 u8 reserved_at_20[0x10]; 5317 u8 op_mod[0x10]; 5318 5319 u8 reserved_at_40[0x40]; 5320 }; 5321 5322 struct mlx5_ifc_qp_2rst_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_at_40[0x40]; 5329 }; 5330 5331 struct mlx5_ifc_qp_2rst_in_bits { 5332 u8 opcode[0x10]; 5333 u8 uid[0x10]; 5334 5335 u8 reserved_at_20[0x10]; 5336 u8 op_mod[0x10]; 5337 5338 u8 reserved_at_40[0x8]; 5339 u8 qpn[0x18]; 5340 5341 u8 reserved_at_60[0x20]; 5342 }; 5343 5344 struct mlx5_ifc_qp_2err_out_bits { 5345 u8 status[0x8]; 5346 u8 reserved_at_8[0x18]; 5347 5348 u8 syndrome[0x20]; 5349 5350 u8 reserved_at_40[0x40]; 5351 }; 5352 5353 struct mlx5_ifc_qp_2err_in_bits { 5354 u8 opcode[0x10]; 5355 u8 uid[0x10]; 5356 5357 u8 reserved_at_20[0x10]; 5358 u8 op_mod[0x10]; 5359 5360 u8 reserved_at_40[0x8]; 5361 u8 qpn[0x18]; 5362 5363 u8 reserved_at_60[0x20]; 5364 }; 5365 5366 struct mlx5_ifc_page_fault_resume_out_bits { 5367 u8 status[0x8]; 5368 u8 reserved_at_8[0x18]; 5369 5370 u8 syndrome[0x20]; 5371 5372 u8 reserved_at_40[0x40]; 5373 }; 5374 5375 struct mlx5_ifc_page_fault_resume_in_bits { 5376 u8 opcode[0x10]; 5377 u8 reserved_at_10[0x10]; 5378 5379 u8 reserved_at_20[0x10]; 5380 u8 op_mod[0x10]; 5381 5382 u8 error[0x1]; 5383 u8 reserved_at_41[0x4]; 5384 u8 page_fault_type[0x3]; 5385 u8 wq_number[0x18]; 5386 5387 u8 reserved_at_60[0x8]; 5388 u8 token[0x18]; 5389 }; 5390 5391 struct mlx5_ifc_nop_out_bits { 5392 u8 status[0x8]; 5393 u8 reserved_at_8[0x18]; 5394 5395 u8 syndrome[0x20]; 5396 5397 u8 reserved_at_40[0x40]; 5398 }; 5399 5400 struct mlx5_ifc_nop_in_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_at_10[0x10]; 5403 5404 u8 reserved_at_20[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 reserved_at_40[0x40]; 5408 }; 5409 5410 struct mlx5_ifc_modify_vport_state_out_bits { 5411 u8 status[0x8]; 5412 u8 reserved_at_8[0x18]; 5413 5414 u8 syndrome[0x20]; 5415 5416 u8 reserved_at_40[0x40]; 5417 }; 5418 5419 struct mlx5_ifc_modify_vport_state_in_bits { 5420 u8 opcode[0x10]; 5421 u8 reserved_at_10[0x10]; 5422 5423 u8 reserved_at_20[0x10]; 5424 u8 op_mod[0x10]; 5425 5426 u8 other_vport[0x1]; 5427 u8 reserved_at_41[0xf]; 5428 u8 vport_number[0x10]; 5429 5430 u8 reserved_at_60[0x18]; 5431 u8 admin_state[0x4]; 5432 u8 reserved_at_7c[0x4]; 5433 }; 5434 5435 struct mlx5_ifc_modify_tis_out_bits { 5436 u8 status[0x8]; 5437 u8 reserved_at_8[0x18]; 5438 5439 u8 syndrome[0x20]; 5440 5441 u8 reserved_at_40[0x40]; 5442 }; 5443 5444 struct mlx5_ifc_modify_tis_bitmask_bits { 5445 u8 reserved_at_0[0x20]; 5446 5447 u8 reserved_at_20[0x1d]; 5448 u8 lag_tx_port_affinity[0x1]; 5449 u8 strict_lag_tx_port_affinity[0x1]; 5450 u8 prio[0x1]; 5451 }; 5452 5453 struct mlx5_ifc_modify_tis_in_bits { 5454 u8 opcode[0x10]; 5455 u8 uid[0x10]; 5456 5457 u8 reserved_at_20[0x10]; 5458 u8 op_mod[0x10]; 5459 5460 u8 reserved_at_40[0x8]; 5461 u8 tisn[0x18]; 5462 5463 u8 reserved_at_60[0x20]; 5464 5465 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5466 5467 u8 reserved_at_c0[0x40]; 5468 5469 struct mlx5_ifc_tisc_bits ctx; 5470 }; 5471 5472 struct mlx5_ifc_modify_tir_bitmask_bits { 5473 u8 reserved_at_0[0x20]; 5474 5475 u8 reserved_at_20[0x1b]; 5476 u8 self_lb_en[0x1]; 5477 u8 reserved_at_3c[0x1]; 5478 u8 hash[0x1]; 5479 u8 reserved_at_3e[0x1]; 5480 u8 lro[0x1]; 5481 }; 5482 5483 struct mlx5_ifc_modify_tir_out_bits { 5484 u8 status[0x8]; 5485 u8 reserved_at_8[0x18]; 5486 5487 u8 syndrome[0x20]; 5488 5489 u8 reserved_at_40[0x40]; 5490 }; 5491 5492 struct mlx5_ifc_modify_tir_in_bits { 5493 u8 opcode[0x10]; 5494 u8 uid[0x10]; 5495 5496 u8 reserved_at_20[0x10]; 5497 u8 op_mod[0x10]; 5498 5499 u8 reserved_at_40[0x8]; 5500 u8 tirn[0x18]; 5501 5502 u8 reserved_at_60[0x20]; 5503 5504 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5505 5506 u8 reserved_at_c0[0x40]; 5507 5508 struct mlx5_ifc_tirc_bits ctx; 5509 }; 5510 5511 struct mlx5_ifc_modify_sq_out_bits { 5512 u8 status[0x8]; 5513 u8 reserved_at_8[0x18]; 5514 5515 u8 syndrome[0x20]; 5516 5517 u8 reserved_at_40[0x40]; 5518 }; 5519 5520 struct mlx5_ifc_modify_sq_in_bits { 5521 u8 opcode[0x10]; 5522 u8 uid[0x10]; 5523 5524 u8 reserved_at_20[0x10]; 5525 u8 op_mod[0x10]; 5526 5527 u8 sq_state[0x4]; 5528 u8 reserved_at_44[0x4]; 5529 u8 sqn[0x18]; 5530 5531 u8 reserved_at_60[0x20]; 5532 5533 u8 modify_bitmask[0x40]; 5534 5535 u8 reserved_at_c0[0x40]; 5536 5537 struct mlx5_ifc_sqc_bits ctx; 5538 }; 5539 5540 struct mlx5_ifc_modify_scheduling_element_out_bits { 5541 u8 status[0x8]; 5542 u8 reserved_at_8[0x18]; 5543 5544 u8 syndrome[0x20]; 5545 5546 u8 reserved_at_40[0x1c0]; 5547 }; 5548 5549 enum { 5550 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5551 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5552 }; 5553 5554 struct mlx5_ifc_modify_scheduling_element_in_bits { 5555 u8 opcode[0x10]; 5556 u8 reserved_at_10[0x10]; 5557 5558 u8 reserved_at_20[0x10]; 5559 u8 op_mod[0x10]; 5560 5561 u8 scheduling_hierarchy[0x8]; 5562 u8 reserved_at_48[0x18]; 5563 5564 u8 scheduling_element_id[0x20]; 5565 5566 u8 reserved_at_80[0x20]; 5567 5568 u8 modify_bitmask[0x20]; 5569 5570 u8 reserved_at_c0[0x40]; 5571 5572 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5573 5574 u8 reserved_at_300[0x100]; 5575 }; 5576 5577 struct mlx5_ifc_modify_rqt_out_bits { 5578 u8 status[0x8]; 5579 u8 reserved_at_8[0x18]; 5580 5581 u8 syndrome[0x20]; 5582 5583 u8 reserved_at_40[0x40]; 5584 }; 5585 5586 struct mlx5_ifc_rqt_bitmask_bits { 5587 u8 reserved_at_0[0x20]; 5588 5589 u8 reserved_at_20[0x1f]; 5590 u8 rqn_list[0x1]; 5591 }; 5592 5593 struct mlx5_ifc_modify_rqt_in_bits { 5594 u8 opcode[0x10]; 5595 u8 uid[0x10]; 5596 5597 u8 reserved_at_20[0x10]; 5598 u8 op_mod[0x10]; 5599 5600 u8 reserved_at_40[0x8]; 5601 u8 rqtn[0x18]; 5602 5603 u8 reserved_at_60[0x20]; 5604 5605 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5606 5607 u8 reserved_at_c0[0x40]; 5608 5609 struct mlx5_ifc_rqtc_bits ctx; 5610 }; 5611 5612 struct mlx5_ifc_modify_rq_out_bits { 5613 u8 status[0x8]; 5614 u8 reserved_at_8[0x18]; 5615 5616 u8 syndrome[0x20]; 5617 5618 u8 reserved_at_40[0x40]; 5619 }; 5620 5621 enum { 5622 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5623 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5624 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5625 }; 5626 5627 struct mlx5_ifc_modify_rq_in_bits { 5628 u8 opcode[0x10]; 5629 u8 uid[0x10]; 5630 5631 u8 reserved_at_20[0x10]; 5632 u8 op_mod[0x10]; 5633 5634 u8 rq_state[0x4]; 5635 u8 reserved_at_44[0x4]; 5636 u8 rqn[0x18]; 5637 5638 u8 reserved_at_60[0x20]; 5639 5640 u8 modify_bitmask[0x40]; 5641 5642 u8 reserved_at_c0[0x40]; 5643 5644 struct mlx5_ifc_rqc_bits ctx; 5645 }; 5646 5647 struct mlx5_ifc_modify_rmp_out_bits { 5648 u8 status[0x8]; 5649 u8 reserved_at_8[0x18]; 5650 5651 u8 syndrome[0x20]; 5652 5653 u8 reserved_at_40[0x40]; 5654 }; 5655 5656 struct mlx5_ifc_rmp_bitmask_bits { 5657 u8 reserved_at_0[0x20]; 5658 5659 u8 reserved_at_20[0x1f]; 5660 u8 lwm[0x1]; 5661 }; 5662 5663 struct mlx5_ifc_modify_rmp_in_bits { 5664 u8 opcode[0x10]; 5665 u8 uid[0x10]; 5666 5667 u8 reserved_at_20[0x10]; 5668 u8 op_mod[0x10]; 5669 5670 u8 rmp_state[0x4]; 5671 u8 reserved_at_44[0x4]; 5672 u8 rmpn[0x18]; 5673 5674 u8 reserved_at_60[0x20]; 5675 5676 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5677 5678 u8 reserved_at_c0[0x40]; 5679 5680 struct mlx5_ifc_rmpc_bits ctx; 5681 }; 5682 5683 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5684 u8 status[0x8]; 5685 u8 reserved_at_8[0x18]; 5686 5687 u8 syndrome[0x20]; 5688 5689 u8 reserved_at_40[0x40]; 5690 }; 5691 5692 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5693 u8 reserved_at_0[0x12]; 5694 u8 affiliation[0x1]; 5695 u8 reserved_at_13[0x1]; 5696 u8 disable_uc_local_lb[0x1]; 5697 u8 disable_mc_local_lb[0x1]; 5698 u8 node_guid[0x1]; 5699 u8 port_guid[0x1]; 5700 u8 min_inline[0x1]; 5701 u8 mtu[0x1]; 5702 u8 change_event[0x1]; 5703 u8 promisc[0x1]; 5704 u8 permanent_address[0x1]; 5705 u8 addresses_list[0x1]; 5706 u8 roce_en[0x1]; 5707 u8 reserved_at_1f[0x1]; 5708 }; 5709 5710 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5711 u8 opcode[0x10]; 5712 u8 reserved_at_10[0x10]; 5713 5714 u8 reserved_at_20[0x10]; 5715 u8 op_mod[0x10]; 5716 5717 u8 other_vport[0x1]; 5718 u8 reserved_at_41[0xf]; 5719 u8 vport_number[0x10]; 5720 5721 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5722 5723 u8 reserved_at_80[0x780]; 5724 5725 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5726 }; 5727 5728 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5729 u8 status[0x8]; 5730 u8 reserved_at_8[0x18]; 5731 5732 u8 syndrome[0x20]; 5733 5734 u8 reserved_at_40[0x40]; 5735 }; 5736 5737 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5738 u8 opcode[0x10]; 5739 u8 reserved_at_10[0x10]; 5740 5741 u8 reserved_at_20[0x10]; 5742 u8 op_mod[0x10]; 5743 5744 u8 other_vport[0x1]; 5745 u8 reserved_at_41[0xb]; 5746 u8 port_num[0x4]; 5747 u8 vport_number[0x10]; 5748 5749 u8 reserved_at_60[0x20]; 5750 5751 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5752 }; 5753 5754 struct mlx5_ifc_modify_cq_out_bits { 5755 u8 status[0x8]; 5756 u8 reserved_at_8[0x18]; 5757 5758 u8 syndrome[0x20]; 5759 5760 u8 reserved_at_40[0x40]; 5761 }; 5762 5763 enum { 5764 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5765 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5766 }; 5767 5768 struct mlx5_ifc_modify_cq_in_bits { 5769 u8 opcode[0x10]; 5770 u8 uid[0x10]; 5771 5772 u8 reserved_at_20[0x10]; 5773 u8 op_mod[0x10]; 5774 5775 u8 reserved_at_40[0x8]; 5776 u8 cqn[0x18]; 5777 5778 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5779 5780 struct mlx5_ifc_cqc_bits cq_context; 5781 5782 u8 reserved_at_280[0x40]; 5783 5784 u8 cq_umem_valid[0x1]; 5785 u8 reserved_at_2c1[0x5bf]; 5786 5787 u8 pas[0][0x40]; 5788 }; 5789 5790 struct mlx5_ifc_modify_cong_status_out_bits { 5791 u8 status[0x8]; 5792 u8 reserved_at_8[0x18]; 5793 5794 u8 syndrome[0x20]; 5795 5796 u8 reserved_at_40[0x40]; 5797 }; 5798 5799 struct mlx5_ifc_modify_cong_status_in_bits { 5800 u8 opcode[0x10]; 5801 u8 reserved_at_10[0x10]; 5802 5803 u8 reserved_at_20[0x10]; 5804 u8 op_mod[0x10]; 5805 5806 u8 reserved_at_40[0x18]; 5807 u8 priority[0x4]; 5808 u8 cong_protocol[0x4]; 5809 5810 u8 enable[0x1]; 5811 u8 tag_enable[0x1]; 5812 u8 reserved_at_62[0x1e]; 5813 }; 5814 5815 struct mlx5_ifc_modify_cong_params_out_bits { 5816 u8 status[0x8]; 5817 u8 reserved_at_8[0x18]; 5818 5819 u8 syndrome[0x20]; 5820 5821 u8 reserved_at_40[0x40]; 5822 }; 5823 5824 struct mlx5_ifc_modify_cong_params_in_bits { 5825 u8 opcode[0x10]; 5826 u8 reserved_at_10[0x10]; 5827 5828 u8 reserved_at_20[0x10]; 5829 u8 op_mod[0x10]; 5830 5831 u8 reserved_at_40[0x1c]; 5832 u8 cong_protocol[0x4]; 5833 5834 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5835 5836 u8 reserved_at_80[0x80]; 5837 5838 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5839 }; 5840 5841 struct mlx5_ifc_manage_pages_out_bits { 5842 u8 status[0x8]; 5843 u8 reserved_at_8[0x18]; 5844 5845 u8 syndrome[0x20]; 5846 5847 u8 output_num_entries[0x20]; 5848 5849 u8 reserved_at_60[0x20]; 5850 5851 u8 pas[0][0x40]; 5852 }; 5853 5854 enum { 5855 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5856 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5857 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5858 }; 5859 5860 struct mlx5_ifc_manage_pages_in_bits { 5861 u8 opcode[0x10]; 5862 u8 reserved_at_10[0x10]; 5863 5864 u8 reserved_at_20[0x10]; 5865 u8 op_mod[0x10]; 5866 5867 u8 reserved_at_40[0x10]; 5868 u8 function_id[0x10]; 5869 5870 u8 input_num_entries[0x20]; 5871 5872 u8 pas[0][0x40]; 5873 }; 5874 5875 struct mlx5_ifc_mad_ifc_out_bits { 5876 u8 status[0x8]; 5877 u8 reserved_at_8[0x18]; 5878 5879 u8 syndrome[0x20]; 5880 5881 u8 reserved_at_40[0x40]; 5882 5883 u8 response_mad_packet[256][0x8]; 5884 }; 5885 5886 struct mlx5_ifc_mad_ifc_in_bits { 5887 u8 opcode[0x10]; 5888 u8 reserved_at_10[0x10]; 5889 5890 u8 reserved_at_20[0x10]; 5891 u8 op_mod[0x10]; 5892 5893 u8 remote_lid[0x10]; 5894 u8 reserved_at_50[0x8]; 5895 u8 port[0x8]; 5896 5897 u8 reserved_at_60[0x20]; 5898 5899 u8 mad[256][0x8]; 5900 }; 5901 5902 struct mlx5_ifc_init_hca_out_bits { 5903 u8 status[0x8]; 5904 u8 reserved_at_8[0x18]; 5905 5906 u8 syndrome[0x20]; 5907 5908 u8 reserved_at_40[0x40]; 5909 }; 5910 5911 struct mlx5_ifc_init_hca_in_bits { 5912 u8 opcode[0x10]; 5913 u8 reserved_at_10[0x10]; 5914 5915 u8 reserved_at_20[0x10]; 5916 u8 op_mod[0x10]; 5917 5918 u8 reserved_at_40[0x40]; 5919 u8 sw_owner_id[4][0x20]; 5920 }; 5921 5922 struct mlx5_ifc_init2rtr_qp_out_bits { 5923 u8 status[0x8]; 5924 u8 reserved_at_8[0x18]; 5925 5926 u8 syndrome[0x20]; 5927 5928 u8 reserved_at_40[0x40]; 5929 }; 5930 5931 struct mlx5_ifc_init2rtr_qp_in_bits { 5932 u8 opcode[0x10]; 5933 u8 uid[0x10]; 5934 5935 u8 reserved_at_20[0x10]; 5936 u8 op_mod[0x10]; 5937 5938 u8 reserved_at_40[0x8]; 5939 u8 qpn[0x18]; 5940 5941 u8 reserved_at_60[0x20]; 5942 5943 u8 opt_param_mask[0x20]; 5944 5945 u8 reserved_at_a0[0x20]; 5946 5947 struct mlx5_ifc_qpc_bits qpc; 5948 5949 u8 reserved_at_800[0x80]; 5950 }; 5951 5952 struct mlx5_ifc_init2init_qp_out_bits { 5953 u8 status[0x8]; 5954 u8 reserved_at_8[0x18]; 5955 5956 u8 syndrome[0x20]; 5957 5958 u8 reserved_at_40[0x40]; 5959 }; 5960 5961 struct mlx5_ifc_init2init_qp_in_bits { 5962 u8 opcode[0x10]; 5963 u8 uid[0x10]; 5964 5965 u8 reserved_at_20[0x10]; 5966 u8 op_mod[0x10]; 5967 5968 u8 reserved_at_40[0x8]; 5969 u8 qpn[0x18]; 5970 5971 u8 reserved_at_60[0x20]; 5972 5973 u8 opt_param_mask[0x20]; 5974 5975 u8 reserved_at_a0[0x20]; 5976 5977 struct mlx5_ifc_qpc_bits qpc; 5978 5979 u8 reserved_at_800[0x80]; 5980 }; 5981 5982 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5983 u8 status[0x8]; 5984 u8 reserved_at_8[0x18]; 5985 5986 u8 syndrome[0x20]; 5987 5988 u8 reserved_at_40[0x40]; 5989 5990 u8 packet_headers_log[128][0x8]; 5991 5992 u8 packet_syndrome[64][0x8]; 5993 }; 5994 5995 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5996 u8 opcode[0x10]; 5997 u8 reserved_at_10[0x10]; 5998 5999 u8 reserved_at_20[0x10]; 6000 u8 op_mod[0x10]; 6001 6002 u8 reserved_at_40[0x40]; 6003 }; 6004 6005 struct mlx5_ifc_gen_eqe_in_bits { 6006 u8 opcode[0x10]; 6007 u8 reserved_at_10[0x10]; 6008 6009 u8 reserved_at_20[0x10]; 6010 u8 op_mod[0x10]; 6011 6012 u8 reserved_at_40[0x18]; 6013 u8 eq_number[0x8]; 6014 6015 u8 reserved_at_60[0x20]; 6016 6017 u8 eqe[64][0x8]; 6018 }; 6019 6020 struct mlx5_ifc_gen_eq_out_bits { 6021 u8 status[0x8]; 6022 u8 reserved_at_8[0x18]; 6023 6024 u8 syndrome[0x20]; 6025 6026 u8 reserved_at_40[0x40]; 6027 }; 6028 6029 struct mlx5_ifc_enable_hca_out_bits { 6030 u8 status[0x8]; 6031 u8 reserved_at_8[0x18]; 6032 6033 u8 syndrome[0x20]; 6034 6035 u8 reserved_at_40[0x20]; 6036 }; 6037 6038 struct mlx5_ifc_enable_hca_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_at_10[0x10]; 6041 6042 u8 reserved_at_20[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 reserved_at_40[0x10]; 6046 u8 function_id[0x10]; 6047 6048 u8 reserved_at_60[0x20]; 6049 }; 6050 6051 struct mlx5_ifc_drain_dct_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_at_8[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_at_40[0x40]; 6058 }; 6059 6060 struct mlx5_ifc_drain_dct_in_bits { 6061 u8 opcode[0x10]; 6062 u8 uid[0x10]; 6063 6064 u8 reserved_at_20[0x10]; 6065 u8 op_mod[0x10]; 6066 6067 u8 reserved_at_40[0x8]; 6068 u8 dctn[0x18]; 6069 6070 u8 reserved_at_60[0x20]; 6071 }; 6072 6073 struct mlx5_ifc_disable_hca_out_bits { 6074 u8 status[0x8]; 6075 u8 reserved_at_8[0x18]; 6076 6077 u8 syndrome[0x20]; 6078 6079 u8 reserved_at_40[0x20]; 6080 }; 6081 6082 struct mlx5_ifc_disable_hca_in_bits { 6083 u8 opcode[0x10]; 6084 u8 reserved_at_10[0x10]; 6085 6086 u8 reserved_at_20[0x10]; 6087 u8 op_mod[0x10]; 6088 6089 u8 reserved_at_40[0x10]; 6090 u8 function_id[0x10]; 6091 6092 u8 reserved_at_60[0x20]; 6093 }; 6094 6095 struct mlx5_ifc_detach_from_mcg_out_bits { 6096 u8 status[0x8]; 6097 u8 reserved_at_8[0x18]; 6098 6099 u8 syndrome[0x20]; 6100 6101 u8 reserved_at_40[0x40]; 6102 }; 6103 6104 struct mlx5_ifc_detach_from_mcg_in_bits { 6105 u8 opcode[0x10]; 6106 u8 uid[0x10]; 6107 6108 u8 reserved_at_20[0x10]; 6109 u8 op_mod[0x10]; 6110 6111 u8 reserved_at_40[0x8]; 6112 u8 qpn[0x18]; 6113 6114 u8 reserved_at_60[0x20]; 6115 6116 u8 multicast_gid[16][0x8]; 6117 }; 6118 6119 struct mlx5_ifc_destroy_xrq_out_bits { 6120 u8 status[0x8]; 6121 u8 reserved_at_8[0x18]; 6122 6123 u8 syndrome[0x20]; 6124 6125 u8 reserved_at_40[0x40]; 6126 }; 6127 6128 struct mlx5_ifc_destroy_xrq_in_bits { 6129 u8 opcode[0x10]; 6130 u8 uid[0x10]; 6131 6132 u8 reserved_at_20[0x10]; 6133 u8 op_mod[0x10]; 6134 6135 u8 reserved_at_40[0x8]; 6136 u8 xrqn[0x18]; 6137 6138 u8 reserved_at_60[0x20]; 6139 }; 6140 6141 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6142 u8 status[0x8]; 6143 u8 reserved_at_8[0x18]; 6144 6145 u8 syndrome[0x20]; 6146 6147 u8 reserved_at_40[0x40]; 6148 }; 6149 6150 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6151 u8 opcode[0x10]; 6152 u8 uid[0x10]; 6153 6154 u8 reserved_at_20[0x10]; 6155 u8 op_mod[0x10]; 6156 6157 u8 reserved_at_40[0x8]; 6158 u8 xrc_srqn[0x18]; 6159 6160 u8 reserved_at_60[0x20]; 6161 }; 6162 6163 struct mlx5_ifc_destroy_tis_out_bits { 6164 u8 status[0x8]; 6165 u8 reserved_at_8[0x18]; 6166 6167 u8 syndrome[0x20]; 6168 6169 u8 reserved_at_40[0x40]; 6170 }; 6171 6172 struct mlx5_ifc_destroy_tis_in_bits { 6173 u8 opcode[0x10]; 6174 u8 uid[0x10]; 6175 6176 u8 reserved_at_20[0x10]; 6177 u8 op_mod[0x10]; 6178 6179 u8 reserved_at_40[0x8]; 6180 u8 tisn[0x18]; 6181 6182 u8 reserved_at_60[0x20]; 6183 }; 6184 6185 struct mlx5_ifc_destroy_tir_out_bits { 6186 u8 status[0x8]; 6187 u8 reserved_at_8[0x18]; 6188 6189 u8 syndrome[0x20]; 6190 6191 u8 reserved_at_40[0x40]; 6192 }; 6193 6194 struct mlx5_ifc_destroy_tir_in_bits { 6195 u8 opcode[0x10]; 6196 u8 uid[0x10]; 6197 6198 u8 reserved_at_20[0x10]; 6199 u8 op_mod[0x10]; 6200 6201 u8 reserved_at_40[0x8]; 6202 u8 tirn[0x18]; 6203 6204 u8 reserved_at_60[0x20]; 6205 }; 6206 6207 struct mlx5_ifc_destroy_srq_out_bits { 6208 u8 status[0x8]; 6209 u8 reserved_at_8[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 reserved_at_40[0x40]; 6214 }; 6215 6216 struct mlx5_ifc_destroy_srq_in_bits { 6217 u8 opcode[0x10]; 6218 u8 uid[0x10]; 6219 6220 u8 reserved_at_20[0x10]; 6221 u8 op_mod[0x10]; 6222 6223 u8 reserved_at_40[0x8]; 6224 u8 srqn[0x18]; 6225 6226 u8 reserved_at_60[0x20]; 6227 }; 6228 6229 struct mlx5_ifc_destroy_sq_out_bits { 6230 u8 status[0x8]; 6231 u8 reserved_at_8[0x18]; 6232 6233 u8 syndrome[0x20]; 6234 6235 u8 reserved_at_40[0x40]; 6236 }; 6237 6238 struct mlx5_ifc_destroy_sq_in_bits { 6239 u8 opcode[0x10]; 6240 u8 uid[0x10]; 6241 6242 u8 reserved_at_20[0x10]; 6243 u8 op_mod[0x10]; 6244 6245 u8 reserved_at_40[0x8]; 6246 u8 sqn[0x18]; 6247 6248 u8 reserved_at_60[0x20]; 6249 }; 6250 6251 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6252 u8 status[0x8]; 6253 u8 reserved_at_8[0x18]; 6254 6255 u8 syndrome[0x20]; 6256 6257 u8 reserved_at_40[0x1c0]; 6258 }; 6259 6260 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6261 u8 opcode[0x10]; 6262 u8 reserved_at_10[0x10]; 6263 6264 u8 reserved_at_20[0x10]; 6265 u8 op_mod[0x10]; 6266 6267 u8 scheduling_hierarchy[0x8]; 6268 u8 reserved_at_48[0x18]; 6269 6270 u8 scheduling_element_id[0x20]; 6271 6272 u8 reserved_at_80[0x180]; 6273 }; 6274 6275 struct mlx5_ifc_destroy_rqt_out_bits { 6276 u8 status[0x8]; 6277 u8 reserved_at_8[0x18]; 6278 6279 u8 syndrome[0x20]; 6280 6281 u8 reserved_at_40[0x40]; 6282 }; 6283 6284 struct mlx5_ifc_destroy_rqt_in_bits { 6285 u8 opcode[0x10]; 6286 u8 uid[0x10]; 6287 6288 u8 reserved_at_20[0x10]; 6289 u8 op_mod[0x10]; 6290 6291 u8 reserved_at_40[0x8]; 6292 u8 rqtn[0x18]; 6293 6294 u8 reserved_at_60[0x20]; 6295 }; 6296 6297 struct mlx5_ifc_destroy_rq_out_bits { 6298 u8 status[0x8]; 6299 u8 reserved_at_8[0x18]; 6300 6301 u8 syndrome[0x20]; 6302 6303 u8 reserved_at_40[0x40]; 6304 }; 6305 6306 struct mlx5_ifc_destroy_rq_in_bits { 6307 u8 opcode[0x10]; 6308 u8 uid[0x10]; 6309 6310 u8 reserved_at_20[0x10]; 6311 u8 op_mod[0x10]; 6312 6313 u8 reserved_at_40[0x8]; 6314 u8 rqn[0x18]; 6315 6316 u8 reserved_at_60[0x20]; 6317 }; 6318 6319 struct mlx5_ifc_set_delay_drop_params_in_bits { 6320 u8 opcode[0x10]; 6321 u8 reserved_at_10[0x10]; 6322 6323 u8 reserved_at_20[0x10]; 6324 u8 op_mod[0x10]; 6325 6326 u8 reserved_at_40[0x20]; 6327 6328 u8 reserved_at_60[0x10]; 6329 u8 delay_drop_timeout[0x10]; 6330 }; 6331 6332 struct mlx5_ifc_set_delay_drop_params_out_bits { 6333 u8 status[0x8]; 6334 u8 reserved_at_8[0x18]; 6335 6336 u8 syndrome[0x20]; 6337 6338 u8 reserved_at_40[0x40]; 6339 }; 6340 6341 struct mlx5_ifc_destroy_rmp_out_bits { 6342 u8 status[0x8]; 6343 u8 reserved_at_8[0x18]; 6344 6345 u8 syndrome[0x20]; 6346 6347 u8 reserved_at_40[0x40]; 6348 }; 6349 6350 struct mlx5_ifc_destroy_rmp_in_bits { 6351 u8 opcode[0x10]; 6352 u8 uid[0x10]; 6353 6354 u8 reserved_at_20[0x10]; 6355 u8 op_mod[0x10]; 6356 6357 u8 reserved_at_40[0x8]; 6358 u8 rmpn[0x18]; 6359 6360 u8 reserved_at_60[0x20]; 6361 }; 6362 6363 struct mlx5_ifc_destroy_qp_out_bits { 6364 u8 status[0x8]; 6365 u8 reserved_at_8[0x18]; 6366 6367 u8 syndrome[0x20]; 6368 6369 u8 reserved_at_40[0x40]; 6370 }; 6371 6372 struct mlx5_ifc_destroy_qp_in_bits { 6373 u8 opcode[0x10]; 6374 u8 uid[0x10]; 6375 6376 u8 reserved_at_20[0x10]; 6377 u8 op_mod[0x10]; 6378 6379 u8 reserved_at_40[0x8]; 6380 u8 qpn[0x18]; 6381 6382 u8 reserved_at_60[0x20]; 6383 }; 6384 6385 struct mlx5_ifc_destroy_psv_out_bits { 6386 u8 status[0x8]; 6387 u8 reserved_at_8[0x18]; 6388 6389 u8 syndrome[0x20]; 6390 6391 u8 reserved_at_40[0x40]; 6392 }; 6393 6394 struct mlx5_ifc_destroy_psv_in_bits { 6395 u8 opcode[0x10]; 6396 u8 reserved_at_10[0x10]; 6397 6398 u8 reserved_at_20[0x10]; 6399 u8 op_mod[0x10]; 6400 6401 u8 reserved_at_40[0x8]; 6402 u8 psvn[0x18]; 6403 6404 u8 reserved_at_60[0x20]; 6405 }; 6406 6407 struct mlx5_ifc_destroy_mkey_out_bits { 6408 u8 status[0x8]; 6409 u8 reserved_at_8[0x18]; 6410 6411 u8 syndrome[0x20]; 6412 6413 u8 reserved_at_40[0x40]; 6414 }; 6415 6416 struct mlx5_ifc_destroy_mkey_in_bits { 6417 u8 opcode[0x10]; 6418 u8 reserved_at_10[0x10]; 6419 6420 u8 reserved_at_20[0x10]; 6421 u8 op_mod[0x10]; 6422 6423 u8 reserved_at_40[0x8]; 6424 u8 mkey_index[0x18]; 6425 6426 u8 reserved_at_60[0x20]; 6427 }; 6428 6429 struct mlx5_ifc_destroy_flow_table_out_bits { 6430 u8 status[0x8]; 6431 u8 reserved_at_8[0x18]; 6432 6433 u8 syndrome[0x20]; 6434 6435 u8 reserved_at_40[0x40]; 6436 }; 6437 6438 struct mlx5_ifc_destroy_flow_table_in_bits { 6439 u8 opcode[0x10]; 6440 u8 reserved_at_10[0x10]; 6441 6442 u8 reserved_at_20[0x10]; 6443 u8 op_mod[0x10]; 6444 6445 u8 other_vport[0x1]; 6446 u8 reserved_at_41[0xf]; 6447 u8 vport_number[0x10]; 6448 6449 u8 reserved_at_60[0x20]; 6450 6451 u8 table_type[0x8]; 6452 u8 reserved_at_88[0x18]; 6453 6454 u8 reserved_at_a0[0x8]; 6455 u8 table_id[0x18]; 6456 6457 u8 reserved_at_c0[0x140]; 6458 }; 6459 6460 struct mlx5_ifc_destroy_flow_group_out_bits { 6461 u8 status[0x8]; 6462 u8 reserved_at_8[0x18]; 6463 6464 u8 syndrome[0x20]; 6465 6466 u8 reserved_at_40[0x40]; 6467 }; 6468 6469 struct mlx5_ifc_destroy_flow_group_in_bits { 6470 u8 opcode[0x10]; 6471 u8 reserved_at_10[0x10]; 6472 6473 u8 reserved_at_20[0x10]; 6474 u8 op_mod[0x10]; 6475 6476 u8 other_vport[0x1]; 6477 u8 reserved_at_41[0xf]; 6478 u8 vport_number[0x10]; 6479 6480 u8 reserved_at_60[0x20]; 6481 6482 u8 table_type[0x8]; 6483 u8 reserved_at_88[0x18]; 6484 6485 u8 reserved_at_a0[0x8]; 6486 u8 table_id[0x18]; 6487 6488 u8 group_id[0x20]; 6489 6490 u8 reserved_at_e0[0x120]; 6491 }; 6492 6493 struct mlx5_ifc_destroy_eq_out_bits { 6494 u8 status[0x8]; 6495 u8 reserved_at_8[0x18]; 6496 6497 u8 syndrome[0x20]; 6498 6499 u8 reserved_at_40[0x40]; 6500 }; 6501 6502 struct mlx5_ifc_destroy_eq_in_bits { 6503 u8 opcode[0x10]; 6504 u8 reserved_at_10[0x10]; 6505 6506 u8 reserved_at_20[0x10]; 6507 u8 op_mod[0x10]; 6508 6509 u8 reserved_at_40[0x18]; 6510 u8 eq_number[0x8]; 6511 6512 u8 reserved_at_60[0x20]; 6513 }; 6514 6515 struct mlx5_ifc_destroy_dct_out_bits { 6516 u8 status[0x8]; 6517 u8 reserved_at_8[0x18]; 6518 6519 u8 syndrome[0x20]; 6520 6521 u8 reserved_at_40[0x40]; 6522 }; 6523 6524 struct mlx5_ifc_destroy_dct_in_bits { 6525 u8 opcode[0x10]; 6526 u8 uid[0x10]; 6527 6528 u8 reserved_at_20[0x10]; 6529 u8 op_mod[0x10]; 6530 6531 u8 reserved_at_40[0x8]; 6532 u8 dctn[0x18]; 6533 6534 u8 reserved_at_60[0x20]; 6535 }; 6536 6537 struct mlx5_ifc_destroy_cq_out_bits { 6538 u8 status[0x8]; 6539 u8 reserved_at_8[0x18]; 6540 6541 u8 syndrome[0x20]; 6542 6543 u8 reserved_at_40[0x40]; 6544 }; 6545 6546 struct mlx5_ifc_destroy_cq_in_bits { 6547 u8 opcode[0x10]; 6548 u8 uid[0x10]; 6549 6550 u8 reserved_at_20[0x10]; 6551 u8 op_mod[0x10]; 6552 6553 u8 reserved_at_40[0x8]; 6554 u8 cqn[0x18]; 6555 6556 u8 reserved_at_60[0x20]; 6557 }; 6558 6559 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6560 u8 status[0x8]; 6561 u8 reserved_at_8[0x18]; 6562 6563 u8 syndrome[0x20]; 6564 6565 u8 reserved_at_40[0x40]; 6566 }; 6567 6568 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6569 u8 opcode[0x10]; 6570 u8 reserved_at_10[0x10]; 6571 6572 u8 reserved_at_20[0x10]; 6573 u8 op_mod[0x10]; 6574 6575 u8 reserved_at_40[0x20]; 6576 6577 u8 reserved_at_60[0x10]; 6578 u8 vxlan_udp_port[0x10]; 6579 }; 6580 6581 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6582 u8 status[0x8]; 6583 u8 reserved_at_8[0x18]; 6584 6585 u8 syndrome[0x20]; 6586 6587 u8 reserved_at_40[0x40]; 6588 }; 6589 6590 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6591 u8 opcode[0x10]; 6592 u8 reserved_at_10[0x10]; 6593 6594 u8 reserved_at_20[0x10]; 6595 u8 op_mod[0x10]; 6596 6597 u8 reserved_at_40[0x60]; 6598 6599 u8 reserved_at_a0[0x8]; 6600 u8 table_index[0x18]; 6601 6602 u8 reserved_at_c0[0x140]; 6603 }; 6604 6605 struct mlx5_ifc_delete_fte_out_bits { 6606 u8 status[0x8]; 6607 u8 reserved_at_8[0x18]; 6608 6609 u8 syndrome[0x20]; 6610 6611 u8 reserved_at_40[0x40]; 6612 }; 6613 6614 struct mlx5_ifc_delete_fte_in_bits { 6615 u8 opcode[0x10]; 6616 u8 reserved_at_10[0x10]; 6617 6618 u8 reserved_at_20[0x10]; 6619 u8 op_mod[0x10]; 6620 6621 u8 other_vport[0x1]; 6622 u8 reserved_at_41[0xf]; 6623 u8 vport_number[0x10]; 6624 6625 u8 reserved_at_60[0x20]; 6626 6627 u8 table_type[0x8]; 6628 u8 reserved_at_88[0x18]; 6629 6630 u8 reserved_at_a0[0x8]; 6631 u8 table_id[0x18]; 6632 6633 u8 reserved_at_c0[0x40]; 6634 6635 u8 flow_index[0x20]; 6636 6637 u8 reserved_at_120[0xe0]; 6638 }; 6639 6640 struct mlx5_ifc_dealloc_xrcd_out_bits { 6641 u8 status[0x8]; 6642 u8 reserved_at_8[0x18]; 6643 6644 u8 syndrome[0x20]; 6645 6646 u8 reserved_at_40[0x40]; 6647 }; 6648 6649 struct mlx5_ifc_dealloc_xrcd_in_bits { 6650 u8 opcode[0x10]; 6651 u8 uid[0x10]; 6652 6653 u8 reserved_at_20[0x10]; 6654 u8 op_mod[0x10]; 6655 6656 u8 reserved_at_40[0x8]; 6657 u8 xrcd[0x18]; 6658 6659 u8 reserved_at_60[0x20]; 6660 }; 6661 6662 struct mlx5_ifc_dealloc_uar_out_bits { 6663 u8 status[0x8]; 6664 u8 reserved_at_8[0x18]; 6665 6666 u8 syndrome[0x20]; 6667 6668 u8 reserved_at_40[0x40]; 6669 }; 6670 6671 struct mlx5_ifc_dealloc_uar_in_bits { 6672 u8 opcode[0x10]; 6673 u8 reserved_at_10[0x10]; 6674 6675 u8 reserved_at_20[0x10]; 6676 u8 op_mod[0x10]; 6677 6678 u8 reserved_at_40[0x8]; 6679 u8 uar[0x18]; 6680 6681 u8 reserved_at_60[0x20]; 6682 }; 6683 6684 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6685 u8 status[0x8]; 6686 u8 reserved_at_8[0x18]; 6687 6688 u8 syndrome[0x20]; 6689 6690 u8 reserved_at_40[0x40]; 6691 }; 6692 6693 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6694 u8 opcode[0x10]; 6695 u8 reserved_at_10[0x10]; 6696 6697 u8 reserved_at_20[0x10]; 6698 u8 op_mod[0x10]; 6699 6700 u8 reserved_at_40[0x8]; 6701 u8 transport_domain[0x18]; 6702 6703 u8 reserved_at_60[0x20]; 6704 }; 6705 6706 struct mlx5_ifc_dealloc_q_counter_out_bits { 6707 u8 status[0x8]; 6708 u8 reserved_at_8[0x18]; 6709 6710 u8 syndrome[0x20]; 6711 6712 u8 reserved_at_40[0x40]; 6713 }; 6714 6715 struct mlx5_ifc_dealloc_q_counter_in_bits { 6716 u8 opcode[0x10]; 6717 u8 reserved_at_10[0x10]; 6718 6719 u8 reserved_at_20[0x10]; 6720 u8 op_mod[0x10]; 6721 6722 u8 reserved_at_40[0x18]; 6723 u8 counter_set_id[0x8]; 6724 6725 u8 reserved_at_60[0x20]; 6726 }; 6727 6728 struct mlx5_ifc_dealloc_pd_out_bits { 6729 u8 status[0x8]; 6730 u8 reserved_at_8[0x18]; 6731 6732 u8 syndrome[0x20]; 6733 6734 u8 reserved_at_40[0x40]; 6735 }; 6736 6737 struct mlx5_ifc_dealloc_pd_in_bits { 6738 u8 opcode[0x10]; 6739 u8 uid[0x10]; 6740 6741 u8 reserved_at_20[0x10]; 6742 u8 op_mod[0x10]; 6743 6744 u8 reserved_at_40[0x8]; 6745 u8 pd[0x18]; 6746 6747 u8 reserved_at_60[0x20]; 6748 }; 6749 6750 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6751 u8 status[0x8]; 6752 u8 reserved_at_8[0x18]; 6753 6754 u8 syndrome[0x20]; 6755 6756 u8 reserved_at_40[0x40]; 6757 }; 6758 6759 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6760 u8 opcode[0x10]; 6761 u8 reserved_at_10[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 flow_counter_id[0x20]; 6767 6768 u8 reserved_at_60[0x20]; 6769 }; 6770 6771 struct mlx5_ifc_create_xrq_out_bits { 6772 u8 status[0x8]; 6773 u8 reserved_at_8[0x18]; 6774 6775 u8 syndrome[0x20]; 6776 6777 u8 reserved_at_40[0x8]; 6778 u8 xrqn[0x18]; 6779 6780 u8 reserved_at_60[0x20]; 6781 }; 6782 6783 struct mlx5_ifc_create_xrq_in_bits { 6784 u8 opcode[0x10]; 6785 u8 uid[0x10]; 6786 6787 u8 reserved_at_20[0x10]; 6788 u8 op_mod[0x10]; 6789 6790 u8 reserved_at_40[0x40]; 6791 6792 struct mlx5_ifc_xrqc_bits xrq_context; 6793 }; 6794 6795 struct mlx5_ifc_create_xrc_srq_out_bits { 6796 u8 status[0x8]; 6797 u8 reserved_at_8[0x18]; 6798 6799 u8 syndrome[0x20]; 6800 6801 u8 reserved_at_40[0x8]; 6802 u8 xrc_srqn[0x18]; 6803 6804 u8 reserved_at_60[0x20]; 6805 }; 6806 6807 struct mlx5_ifc_create_xrc_srq_in_bits { 6808 u8 opcode[0x10]; 6809 u8 uid[0x10]; 6810 6811 u8 reserved_at_20[0x10]; 6812 u8 op_mod[0x10]; 6813 6814 u8 reserved_at_40[0x40]; 6815 6816 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6817 6818 u8 reserved_at_280[0x60]; 6819 6820 u8 xrc_srq_umem_valid[0x1]; 6821 u8 reserved_at_2e1[0x1f]; 6822 6823 u8 reserved_at_300[0x580]; 6824 6825 u8 pas[0][0x40]; 6826 }; 6827 6828 struct mlx5_ifc_create_tis_out_bits { 6829 u8 status[0x8]; 6830 u8 reserved_at_8[0x18]; 6831 6832 u8 syndrome[0x20]; 6833 6834 u8 reserved_at_40[0x8]; 6835 u8 tisn[0x18]; 6836 6837 u8 reserved_at_60[0x20]; 6838 }; 6839 6840 struct mlx5_ifc_create_tis_in_bits { 6841 u8 opcode[0x10]; 6842 u8 uid[0x10]; 6843 6844 u8 reserved_at_20[0x10]; 6845 u8 op_mod[0x10]; 6846 6847 u8 reserved_at_40[0xc0]; 6848 6849 struct mlx5_ifc_tisc_bits ctx; 6850 }; 6851 6852 struct mlx5_ifc_create_tir_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_at_8[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_at_40[0x8]; 6859 u8 tirn[0x18]; 6860 6861 u8 reserved_at_60[0x20]; 6862 }; 6863 6864 struct mlx5_ifc_create_tir_in_bits { 6865 u8 opcode[0x10]; 6866 u8 uid[0x10]; 6867 6868 u8 reserved_at_20[0x10]; 6869 u8 op_mod[0x10]; 6870 6871 u8 reserved_at_40[0xc0]; 6872 6873 struct mlx5_ifc_tirc_bits ctx; 6874 }; 6875 6876 struct mlx5_ifc_create_srq_out_bits { 6877 u8 status[0x8]; 6878 u8 reserved_at_8[0x18]; 6879 6880 u8 syndrome[0x20]; 6881 6882 u8 reserved_at_40[0x8]; 6883 u8 srqn[0x18]; 6884 6885 u8 reserved_at_60[0x20]; 6886 }; 6887 6888 struct mlx5_ifc_create_srq_in_bits { 6889 u8 opcode[0x10]; 6890 u8 uid[0x10]; 6891 6892 u8 reserved_at_20[0x10]; 6893 u8 op_mod[0x10]; 6894 6895 u8 reserved_at_40[0x40]; 6896 6897 struct mlx5_ifc_srqc_bits srq_context_entry; 6898 6899 u8 reserved_at_280[0x600]; 6900 6901 u8 pas[0][0x40]; 6902 }; 6903 6904 struct mlx5_ifc_create_sq_out_bits { 6905 u8 status[0x8]; 6906 u8 reserved_at_8[0x18]; 6907 6908 u8 syndrome[0x20]; 6909 6910 u8 reserved_at_40[0x8]; 6911 u8 sqn[0x18]; 6912 6913 u8 reserved_at_60[0x20]; 6914 }; 6915 6916 struct mlx5_ifc_create_sq_in_bits { 6917 u8 opcode[0x10]; 6918 u8 uid[0x10]; 6919 6920 u8 reserved_at_20[0x10]; 6921 u8 op_mod[0x10]; 6922 6923 u8 reserved_at_40[0xc0]; 6924 6925 struct mlx5_ifc_sqc_bits ctx; 6926 }; 6927 6928 struct mlx5_ifc_create_scheduling_element_out_bits { 6929 u8 status[0x8]; 6930 u8 reserved_at_8[0x18]; 6931 6932 u8 syndrome[0x20]; 6933 6934 u8 reserved_at_40[0x40]; 6935 6936 u8 scheduling_element_id[0x20]; 6937 6938 u8 reserved_at_a0[0x160]; 6939 }; 6940 6941 struct mlx5_ifc_create_scheduling_element_in_bits { 6942 u8 opcode[0x10]; 6943 u8 reserved_at_10[0x10]; 6944 6945 u8 reserved_at_20[0x10]; 6946 u8 op_mod[0x10]; 6947 6948 u8 scheduling_hierarchy[0x8]; 6949 u8 reserved_at_48[0x18]; 6950 6951 u8 reserved_at_60[0xa0]; 6952 6953 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6954 6955 u8 reserved_at_300[0x100]; 6956 }; 6957 6958 struct mlx5_ifc_create_rqt_out_bits { 6959 u8 status[0x8]; 6960 u8 reserved_at_8[0x18]; 6961 6962 u8 syndrome[0x20]; 6963 6964 u8 reserved_at_40[0x8]; 6965 u8 rqtn[0x18]; 6966 6967 u8 reserved_at_60[0x20]; 6968 }; 6969 6970 struct mlx5_ifc_create_rqt_in_bits { 6971 u8 opcode[0x10]; 6972 u8 uid[0x10]; 6973 6974 u8 reserved_at_20[0x10]; 6975 u8 op_mod[0x10]; 6976 6977 u8 reserved_at_40[0xc0]; 6978 6979 struct mlx5_ifc_rqtc_bits rqt_context; 6980 }; 6981 6982 struct mlx5_ifc_create_rq_out_bits { 6983 u8 status[0x8]; 6984 u8 reserved_at_8[0x18]; 6985 6986 u8 syndrome[0x20]; 6987 6988 u8 reserved_at_40[0x8]; 6989 u8 rqn[0x18]; 6990 6991 u8 reserved_at_60[0x20]; 6992 }; 6993 6994 struct mlx5_ifc_create_rq_in_bits { 6995 u8 opcode[0x10]; 6996 u8 uid[0x10]; 6997 6998 u8 reserved_at_20[0x10]; 6999 u8 op_mod[0x10]; 7000 7001 u8 reserved_at_40[0xc0]; 7002 7003 struct mlx5_ifc_rqc_bits ctx; 7004 }; 7005 7006 struct mlx5_ifc_create_rmp_out_bits { 7007 u8 status[0x8]; 7008 u8 reserved_at_8[0x18]; 7009 7010 u8 syndrome[0x20]; 7011 7012 u8 reserved_at_40[0x8]; 7013 u8 rmpn[0x18]; 7014 7015 u8 reserved_at_60[0x20]; 7016 }; 7017 7018 struct mlx5_ifc_create_rmp_in_bits { 7019 u8 opcode[0x10]; 7020 u8 uid[0x10]; 7021 7022 u8 reserved_at_20[0x10]; 7023 u8 op_mod[0x10]; 7024 7025 u8 reserved_at_40[0xc0]; 7026 7027 struct mlx5_ifc_rmpc_bits ctx; 7028 }; 7029 7030 struct mlx5_ifc_create_qp_out_bits { 7031 u8 status[0x8]; 7032 u8 reserved_at_8[0x18]; 7033 7034 u8 syndrome[0x20]; 7035 7036 u8 reserved_at_40[0x8]; 7037 u8 qpn[0x18]; 7038 7039 u8 reserved_at_60[0x20]; 7040 }; 7041 7042 struct mlx5_ifc_create_qp_in_bits { 7043 u8 opcode[0x10]; 7044 u8 uid[0x10]; 7045 7046 u8 reserved_at_20[0x10]; 7047 u8 op_mod[0x10]; 7048 7049 u8 reserved_at_40[0x40]; 7050 7051 u8 opt_param_mask[0x20]; 7052 7053 u8 reserved_at_a0[0x20]; 7054 7055 struct mlx5_ifc_qpc_bits qpc; 7056 7057 u8 reserved_at_800[0x60]; 7058 7059 u8 wq_umem_valid[0x1]; 7060 u8 reserved_at_861[0x1f]; 7061 7062 u8 pas[0][0x40]; 7063 }; 7064 7065 struct mlx5_ifc_create_psv_out_bits { 7066 u8 status[0x8]; 7067 u8 reserved_at_8[0x18]; 7068 7069 u8 syndrome[0x20]; 7070 7071 u8 reserved_at_40[0x40]; 7072 7073 u8 reserved_at_80[0x8]; 7074 u8 psv0_index[0x18]; 7075 7076 u8 reserved_at_a0[0x8]; 7077 u8 psv1_index[0x18]; 7078 7079 u8 reserved_at_c0[0x8]; 7080 u8 psv2_index[0x18]; 7081 7082 u8 reserved_at_e0[0x8]; 7083 u8 psv3_index[0x18]; 7084 }; 7085 7086 struct mlx5_ifc_create_psv_in_bits { 7087 u8 opcode[0x10]; 7088 u8 reserved_at_10[0x10]; 7089 7090 u8 reserved_at_20[0x10]; 7091 u8 op_mod[0x10]; 7092 7093 u8 num_psv[0x4]; 7094 u8 reserved_at_44[0x4]; 7095 u8 pd[0x18]; 7096 7097 u8 reserved_at_60[0x20]; 7098 }; 7099 7100 struct mlx5_ifc_create_mkey_out_bits { 7101 u8 status[0x8]; 7102 u8 reserved_at_8[0x18]; 7103 7104 u8 syndrome[0x20]; 7105 7106 u8 reserved_at_40[0x8]; 7107 u8 mkey_index[0x18]; 7108 7109 u8 reserved_at_60[0x20]; 7110 }; 7111 7112 struct mlx5_ifc_create_mkey_in_bits { 7113 u8 opcode[0x10]; 7114 u8 reserved_at_10[0x10]; 7115 7116 u8 reserved_at_20[0x10]; 7117 u8 op_mod[0x10]; 7118 7119 u8 reserved_at_40[0x20]; 7120 7121 u8 pg_access[0x1]; 7122 u8 mkey_umem_valid[0x1]; 7123 u8 reserved_at_62[0x1e]; 7124 7125 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7126 7127 u8 reserved_at_280[0x80]; 7128 7129 u8 translations_octword_actual_size[0x20]; 7130 7131 u8 reserved_at_320[0x560]; 7132 7133 u8 klm_pas_mtt[0][0x20]; 7134 }; 7135 7136 struct mlx5_ifc_create_flow_table_out_bits { 7137 u8 status[0x8]; 7138 u8 reserved_at_8[0x18]; 7139 7140 u8 syndrome[0x20]; 7141 7142 u8 reserved_at_40[0x8]; 7143 u8 table_id[0x18]; 7144 7145 u8 reserved_at_60[0x20]; 7146 }; 7147 7148 struct mlx5_ifc_flow_table_context_bits { 7149 u8 reformat_en[0x1]; 7150 u8 decap_en[0x1]; 7151 u8 reserved_at_2[0x2]; 7152 u8 table_miss_action[0x4]; 7153 u8 level[0x8]; 7154 u8 reserved_at_10[0x8]; 7155 u8 log_size[0x8]; 7156 7157 u8 reserved_at_20[0x8]; 7158 u8 table_miss_id[0x18]; 7159 7160 u8 reserved_at_40[0x8]; 7161 u8 lag_master_next_table_id[0x18]; 7162 7163 u8 reserved_at_60[0xe0]; 7164 }; 7165 7166 struct mlx5_ifc_create_flow_table_in_bits { 7167 u8 opcode[0x10]; 7168 u8 reserved_at_10[0x10]; 7169 7170 u8 reserved_at_20[0x10]; 7171 u8 op_mod[0x10]; 7172 7173 u8 other_vport[0x1]; 7174 u8 reserved_at_41[0xf]; 7175 u8 vport_number[0x10]; 7176 7177 u8 reserved_at_60[0x20]; 7178 7179 u8 table_type[0x8]; 7180 u8 reserved_at_88[0x18]; 7181 7182 u8 reserved_at_a0[0x20]; 7183 7184 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7185 }; 7186 7187 struct mlx5_ifc_create_flow_group_out_bits { 7188 u8 status[0x8]; 7189 u8 reserved_at_8[0x18]; 7190 7191 u8 syndrome[0x20]; 7192 7193 u8 reserved_at_40[0x8]; 7194 u8 group_id[0x18]; 7195 7196 u8 reserved_at_60[0x20]; 7197 }; 7198 7199 enum { 7200 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7201 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7202 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7203 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7204 }; 7205 7206 struct mlx5_ifc_create_flow_group_in_bits { 7207 u8 opcode[0x10]; 7208 u8 reserved_at_10[0x10]; 7209 7210 u8 reserved_at_20[0x10]; 7211 u8 op_mod[0x10]; 7212 7213 u8 other_vport[0x1]; 7214 u8 reserved_at_41[0xf]; 7215 u8 vport_number[0x10]; 7216 7217 u8 reserved_at_60[0x20]; 7218 7219 u8 table_type[0x8]; 7220 u8 reserved_at_88[0x18]; 7221 7222 u8 reserved_at_a0[0x8]; 7223 u8 table_id[0x18]; 7224 7225 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7226 7227 u8 reserved_at_c1[0x1f]; 7228 7229 u8 start_flow_index[0x20]; 7230 7231 u8 reserved_at_100[0x20]; 7232 7233 u8 end_flow_index[0x20]; 7234 7235 u8 reserved_at_140[0xa0]; 7236 7237 u8 reserved_at_1e0[0x18]; 7238 u8 match_criteria_enable[0x8]; 7239 7240 struct mlx5_ifc_fte_match_param_bits match_criteria; 7241 7242 u8 reserved_at_1200[0xe00]; 7243 }; 7244 7245 struct mlx5_ifc_create_eq_out_bits { 7246 u8 status[0x8]; 7247 u8 reserved_at_8[0x18]; 7248 7249 u8 syndrome[0x20]; 7250 7251 u8 reserved_at_40[0x18]; 7252 u8 eq_number[0x8]; 7253 7254 u8 reserved_at_60[0x20]; 7255 }; 7256 7257 struct mlx5_ifc_create_eq_in_bits { 7258 u8 opcode[0x10]; 7259 u8 reserved_at_10[0x10]; 7260 7261 u8 reserved_at_20[0x10]; 7262 u8 op_mod[0x10]; 7263 7264 u8 reserved_at_40[0x40]; 7265 7266 struct mlx5_ifc_eqc_bits eq_context_entry; 7267 7268 u8 reserved_at_280[0x40]; 7269 7270 u8 event_bitmask[0x40]; 7271 7272 u8 reserved_at_300[0x580]; 7273 7274 u8 pas[0][0x40]; 7275 }; 7276 7277 struct mlx5_ifc_create_dct_out_bits { 7278 u8 status[0x8]; 7279 u8 reserved_at_8[0x18]; 7280 7281 u8 syndrome[0x20]; 7282 7283 u8 reserved_at_40[0x8]; 7284 u8 dctn[0x18]; 7285 7286 u8 reserved_at_60[0x20]; 7287 }; 7288 7289 struct mlx5_ifc_create_dct_in_bits { 7290 u8 opcode[0x10]; 7291 u8 uid[0x10]; 7292 7293 u8 reserved_at_20[0x10]; 7294 u8 op_mod[0x10]; 7295 7296 u8 reserved_at_40[0x40]; 7297 7298 struct mlx5_ifc_dctc_bits dct_context_entry; 7299 7300 u8 reserved_at_280[0x180]; 7301 }; 7302 7303 struct mlx5_ifc_create_cq_out_bits { 7304 u8 status[0x8]; 7305 u8 reserved_at_8[0x18]; 7306 7307 u8 syndrome[0x20]; 7308 7309 u8 reserved_at_40[0x8]; 7310 u8 cqn[0x18]; 7311 7312 u8 reserved_at_60[0x20]; 7313 }; 7314 7315 struct mlx5_ifc_create_cq_in_bits { 7316 u8 opcode[0x10]; 7317 u8 uid[0x10]; 7318 7319 u8 reserved_at_20[0x10]; 7320 u8 op_mod[0x10]; 7321 7322 u8 reserved_at_40[0x40]; 7323 7324 struct mlx5_ifc_cqc_bits cq_context; 7325 7326 u8 reserved_at_280[0x60]; 7327 7328 u8 cq_umem_valid[0x1]; 7329 u8 reserved_at_2e1[0x59f]; 7330 7331 u8 pas[0][0x40]; 7332 }; 7333 7334 struct mlx5_ifc_config_int_moderation_out_bits { 7335 u8 status[0x8]; 7336 u8 reserved_at_8[0x18]; 7337 7338 u8 syndrome[0x20]; 7339 7340 u8 reserved_at_40[0x4]; 7341 u8 min_delay[0xc]; 7342 u8 int_vector[0x10]; 7343 7344 u8 reserved_at_60[0x20]; 7345 }; 7346 7347 enum { 7348 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7349 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7350 }; 7351 7352 struct mlx5_ifc_config_int_moderation_in_bits { 7353 u8 opcode[0x10]; 7354 u8 reserved_at_10[0x10]; 7355 7356 u8 reserved_at_20[0x10]; 7357 u8 op_mod[0x10]; 7358 7359 u8 reserved_at_40[0x4]; 7360 u8 min_delay[0xc]; 7361 u8 int_vector[0x10]; 7362 7363 u8 reserved_at_60[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_attach_to_mcg_out_bits { 7367 u8 status[0x8]; 7368 u8 reserved_at_8[0x18]; 7369 7370 u8 syndrome[0x20]; 7371 7372 u8 reserved_at_40[0x40]; 7373 }; 7374 7375 struct mlx5_ifc_attach_to_mcg_in_bits { 7376 u8 opcode[0x10]; 7377 u8 uid[0x10]; 7378 7379 u8 reserved_at_20[0x10]; 7380 u8 op_mod[0x10]; 7381 7382 u8 reserved_at_40[0x8]; 7383 u8 qpn[0x18]; 7384 7385 u8 reserved_at_60[0x20]; 7386 7387 u8 multicast_gid[16][0x8]; 7388 }; 7389 7390 struct mlx5_ifc_arm_xrq_out_bits { 7391 u8 status[0x8]; 7392 u8 reserved_at_8[0x18]; 7393 7394 u8 syndrome[0x20]; 7395 7396 u8 reserved_at_40[0x40]; 7397 }; 7398 7399 struct mlx5_ifc_arm_xrq_in_bits { 7400 u8 opcode[0x10]; 7401 u8 reserved_at_10[0x10]; 7402 7403 u8 reserved_at_20[0x10]; 7404 u8 op_mod[0x10]; 7405 7406 u8 reserved_at_40[0x8]; 7407 u8 xrqn[0x18]; 7408 7409 u8 reserved_at_60[0x10]; 7410 u8 lwm[0x10]; 7411 }; 7412 7413 struct mlx5_ifc_arm_xrc_srq_out_bits { 7414 u8 status[0x8]; 7415 u8 reserved_at_8[0x18]; 7416 7417 u8 syndrome[0x20]; 7418 7419 u8 reserved_at_40[0x40]; 7420 }; 7421 7422 enum { 7423 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7424 }; 7425 7426 struct mlx5_ifc_arm_xrc_srq_in_bits { 7427 u8 opcode[0x10]; 7428 u8 uid[0x10]; 7429 7430 u8 reserved_at_20[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 reserved_at_40[0x8]; 7434 u8 xrc_srqn[0x18]; 7435 7436 u8 reserved_at_60[0x10]; 7437 u8 lwm[0x10]; 7438 }; 7439 7440 struct mlx5_ifc_arm_rq_out_bits { 7441 u8 status[0x8]; 7442 u8 reserved_at_8[0x18]; 7443 7444 u8 syndrome[0x20]; 7445 7446 u8 reserved_at_40[0x40]; 7447 }; 7448 7449 enum { 7450 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7451 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7452 }; 7453 7454 struct mlx5_ifc_arm_rq_in_bits { 7455 u8 opcode[0x10]; 7456 u8 uid[0x10]; 7457 7458 u8 reserved_at_20[0x10]; 7459 u8 op_mod[0x10]; 7460 7461 u8 reserved_at_40[0x8]; 7462 u8 srq_number[0x18]; 7463 7464 u8 reserved_at_60[0x10]; 7465 u8 lwm[0x10]; 7466 }; 7467 7468 struct mlx5_ifc_arm_dct_out_bits { 7469 u8 status[0x8]; 7470 u8 reserved_at_8[0x18]; 7471 7472 u8 syndrome[0x20]; 7473 7474 u8 reserved_at_40[0x40]; 7475 }; 7476 7477 struct mlx5_ifc_arm_dct_in_bits { 7478 u8 opcode[0x10]; 7479 u8 reserved_at_10[0x10]; 7480 7481 u8 reserved_at_20[0x10]; 7482 u8 op_mod[0x10]; 7483 7484 u8 reserved_at_40[0x8]; 7485 u8 dct_number[0x18]; 7486 7487 u8 reserved_at_60[0x20]; 7488 }; 7489 7490 struct mlx5_ifc_alloc_xrcd_out_bits { 7491 u8 status[0x8]; 7492 u8 reserved_at_8[0x18]; 7493 7494 u8 syndrome[0x20]; 7495 7496 u8 reserved_at_40[0x8]; 7497 u8 xrcd[0x18]; 7498 7499 u8 reserved_at_60[0x20]; 7500 }; 7501 7502 struct mlx5_ifc_alloc_xrcd_in_bits { 7503 u8 opcode[0x10]; 7504 u8 uid[0x10]; 7505 7506 u8 reserved_at_20[0x10]; 7507 u8 op_mod[0x10]; 7508 7509 u8 reserved_at_40[0x40]; 7510 }; 7511 7512 struct mlx5_ifc_alloc_uar_out_bits { 7513 u8 status[0x8]; 7514 u8 reserved_at_8[0x18]; 7515 7516 u8 syndrome[0x20]; 7517 7518 u8 reserved_at_40[0x8]; 7519 u8 uar[0x18]; 7520 7521 u8 reserved_at_60[0x20]; 7522 }; 7523 7524 struct mlx5_ifc_alloc_uar_in_bits { 7525 u8 opcode[0x10]; 7526 u8 reserved_at_10[0x10]; 7527 7528 u8 reserved_at_20[0x10]; 7529 u8 op_mod[0x10]; 7530 7531 u8 reserved_at_40[0x40]; 7532 }; 7533 7534 struct mlx5_ifc_alloc_transport_domain_out_bits { 7535 u8 status[0x8]; 7536 u8 reserved_at_8[0x18]; 7537 7538 u8 syndrome[0x20]; 7539 7540 u8 reserved_at_40[0x8]; 7541 u8 transport_domain[0x18]; 7542 7543 u8 reserved_at_60[0x20]; 7544 }; 7545 7546 struct mlx5_ifc_alloc_transport_domain_in_bits { 7547 u8 opcode[0x10]; 7548 u8 reserved_at_10[0x10]; 7549 7550 u8 reserved_at_20[0x10]; 7551 u8 op_mod[0x10]; 7552 7553 u8 reserved_at_40[0x40]; 7554 }; 7555 7556 struct mlx5_ifc_alloc_q_counter_out_bits { 7557 u8 status[0x8]; 7558 u8 reserved_at_8[0x18]; 7559 7560 u8 syndrome[0x20]; 7561 7562 u8 reserved_at_40[0x18]; 7563 u8 counter_set_id[0x8]; 7564 7565 u8 reserved_at_60[0x20]; 7566 }; 7567 7568 struct mlx5_ifc_alloc_q_counter_in_bits { 7569 u8 opcode[0x10]; 7570 u8 reserved_at_10[0x10]; 7571 7572 u8 reserved_at_20[0x10]; 7573 u8 op_mod[0x10]; 7574 7575 u8 reserved_at_40[0x40]; 7576 }; 7577 7578 struct mlx5_ifc_alloc_pd_out_bits { 7579 u8 status[0x8]; 7580 u8 reserved_at_8[0x18]; 7581 7582 u8 syndrome[0x20]; 7583 7584 u8 reserved_at_40[0x8]; 7585 u8 pd[0x18]; 7586 7587 u8 reserved_at_60[0x20]; 7588 }; 7589 7590 struct mlx5_ifc_alloc_pd_in_bits { 7591 u8 opcode[0x10]; 7592 u8 uid[0x10]; 7593 7594 u8 reserved_at_20[0x10]; 7595 u8 op_mod[0x10]; 7596 7597 u8 reserved_at_40[0x40]; 7598 }; 7599 7600 struct mlx5_ifc_alloc_flow_counter_out_bits { 7601 u8 status[0x8]; 7602 u8 reserved_at_8[0x18]; 7603 7604 u8 syndrome[0x20]; 7605 7606 u8 flow_counter_id[0x20]; 7607 7608 u8 reserved_at_60[0x20]; 7609 }; 7610 7611 struct mlx5_ifc_alloc_flow_counter_in_bits { 7612 u8 opcode[0x10]; 7613 u8 reserved_at_10[0x10]; 7614 7615 u8 reserved_at_20[0x10]; 7616 u8 op_mod[0x10]; 7617 7618 u8 reserved_at_40[0x40]; 7619 }; 7620 7621 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7622 u8 status[0x8]; 7623 u8 reserved_at_8[0x18]; 7624 7625 u8 syndrome[0x20]; 7626 7627 u8 reserved_at_40[0x40]; 7628 }; 7629 7630 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7631 u8 opcode[0x10]; 7632 u8 reserved_at_10[0x10]; 7633 7634 u8 reserved_at_20[0x10]; 7635 u8 op_mod[0x10]; 7636 7637 u8 reserved_at_40[0x20]; 7638 7639 u8 reserved_at_60[0x10]; 7640 u8 vxlan_udp_port[0x10]; 7641 }; 7642 7643 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7644 u8 status[0x8]; 7645 u8 reserved_at_8[0x18]; 7646 7647 u8 syndrome[0x20]; 7648 7649 u8 reserved_at_40[0x40]; 7650 }; 7651 7652 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7653 u8 opcode[0x10]; 7654 u8 reserved_at_10[0x10]; 7655 7656 u8 reserved_at_20[0x10]; 7657 u8 op_mod[0x10]; 7658 7659 u8 reserved_at_40[0x10]; 7660 u8 rate_limit_index[0x10]; 7661 7662 u8 reserved_at_60[0x20]; 7663 7664 u8 rate_limit[0x20]; 7665 7666 u8 burst_upper_bound[0x20]; 7667 7668 u8 reserved_at_c0[0x10]; 7669 u8 typical_packet_size[0x10]; 7670 7671 u8 reserved_at_e0[0x120]; 7672 }; 7673 7674 struct mlx5_ifc_access_register_out_bits { 7675 u8 status[0x8]; 7676 u8 reserved_at_8[0x18]; 7677 7678 u8 syndrome[0x20]; 7679 7680 u8 reserved_at_40[0x40]; 7681 7682 u8 register_data[0][0x20]; 7683 }; 7684 7685 enum { 7686 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7687 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7688 }; 7689 7690 struct mlx5_ifc_access_register_in_bits { 7691 u8 opcode[0x10]; 7692 u8 reserved_at_10[0x10]; 7693 7694 u8 reserved_at_20[0x10]; 7695 u8 op_mod[0x10]; 7696 7697 u8 reserved_at_40[0x10]; 7698 u8 register_id[0x10]; 7699 7700 u8 argument[0x20]; 7701 7702 u8 register_data[0][0x20]; 7703 }; 7704 7705 struct mlx5_ifc_sltp_reg_bits { 7706 u8 status[0x4]; 7707 u8 version[0x4]; 7708 u8 local_port[0x8]; 7709 u8 pnat[0x2]; 7710 u8 reserved_at_12[0x2]; 7711 u8 lane[0x4]; 7712 u8 reserved_at_18[0x8]; 7713 7714 u8 reserved_at_20[0x20]; 7715 7716 u8 reserved_at_40[0x7]; 7717 u8 polarity[0x1]; 7718 u8 ob_tap0[0x8]; 7719 u8 ob_tap1[0x8]; 7720 u8 ob_tap2[0x8]; 7721 7722 u8 reserved_at_60[0xc]; 7723 u8 ob_preemp_mode[0x4]; 7724 u8 ob_reg[0x8]; 7725 u8 ob_bias[0x8]; 7726 7727 u8 reserved_at_80[0x20]; 7728 }; 7729 7730 struct mlx5_ifc_slrg_reg_bits { 7731 u8 status[0x4]; 7732 u8 version[0x4]; 7733 u8 local_port[0x8]; 7734 u8 pnat[0x2]; 7735 u8 reserved_at_12[0x2]; 7736 u8 lane[0x4]; 7737 u8 reserved_at_18[0x8]; 7738 7739 u8 time_to_link_up[0x10]; 7740 u8 reserved_at_30[0xc]; 7741 u8 grade_lane_speed[0x4]; 7742 7743 u8 grade_version[0x8]; 7744 u8 grade[0x18]; 7745 7746 u8 reserved_at_60[0x4]; 7747 u8 height_grade_type[0x4]; 7748 u8 height_grade[0x18]; 7749 7750 u8 height_dz[0x10]; 7751 u8 height_dv[0x10]; 7752 7753 u8 reserved_at_a0[0x10]; 7754 u8 height_sigma[0x10]; 7755 7756 u8 reserved_at_c0[0x20]; 7757 7758 u8 reserved_at_e0[0x4]; 7759 u8 phase_grade_type[0x4]; 7760 u8 phase_grade[0x18]; 7761 7762 u8 reserved_at_100[0x8]; 7763 u8 phase_eo_pos[0x8]; 7764 u8 reserved_at_110[0x8]; 7765 u8 phase_eo_neg[0x8]; 7766 7767 u8 ffe_set_tested[0x10]; 7768 u8 test_errors_per_lane[0x10]; 7769 }; 7770 7771 struct mlx5_ifc_pvlc_reg_bits { 7772 u8 reserved_at_0[0x8]; 7773 u8 local_port[0x8]; 7774 u8 reserved_at_10[0x10]; 7775 7776 u8 reserved_at_20[0x1c]; 7777 u8 vl_hw_cap[0x4]; 7778 7779 u8 reserved_at_40[0x1c]; 7780 u8 vl_admin[0x4]; 7781 7782 u8 reserved_at_60[0x1c]; 7783 u8 vl_operational[0x4]; 7784 }; 7785 7786 struct mlx5_ifc_pude_reg_bits { 7787 u8 swid[0x8]; 7788 u8 local_port[0x8]; 7789 u8 reserved_at_10[0x4]; 7790 u8 admin_status[0x4]; 7791 u8 reserved_at_18[0x4]; 7792 u8 oper_status[0x4]; 7793 7794 u8 reserved_at_20[0x60]; 7795 }; 7796 7797 struct mlx5_ifc_ptys_reg_bits { 7798 u8 reserved_at_0[0x1]; 7799 u8 an_disable_admin[0x1]; 7800 u8 an_disable_cap[0x1]; 7801 u8 reserved_at_3[0x5]; 7802 u8 local_port[0x8]; 7803 u8 reserved_at_10[0xd]; 7804 u8 proto_mask[0x3]; 7805 7806 u8 an_status[0x4]; 7807 u8 reserved_at_24[0x3c]; 7808 7809 u8 eth_proto_capability[0x20]; 7810 7811 u8 ib_link_width_capability[0x10]; 7812 u8 ib_proto_capability[0x10]; 7813 7814 u8 reserved_at_a0[0x20]; 7815 7816 u8 eth_proto_admin[0x20]; 7817 7818 u8 ib_link_width_admin[0x10]; 7819 u8 ib_proto_admin[0x10]; 7820 7821 u8 reserved_at_100[0x20]; 7822 7823 u8 eth_proto_oper[0x20]; 7824 7825 u8 ib_link_width_oper[0x10]; 7826 u8 ib_proto_oper[0x10]; 7827 7828 u8 reserved_at_160[0x1c]; 7829 u8 connector_type[0x4]; 7830 7831 u8 eth_proto_lp_advertise[0x20]; 7832 7833 u8 reserved_at_1a0[0x60]; 7834 }; 7835 7836 struct mlx5_ifc_mlcr_reg_bits { 7837 u8 reserved_at_0[0x8]; 7838 u8 local_port[0x8]; 7839 u8 reserved_at_10[0x20]; 7840 7841 u8 beacon_duration[0x10]; 7842 u8 reserved_at_40[0x10]; 7843 7844 u8 beacon_remain[0x10]; 7845 }; 7846 7847 struct mlx5_ifc_ptas_reg_bits { 7848 u8 reserved_at_0[0x20]; 7849 7850 u8 algorithm_options[0x10]; 7851 u8 reserved_at_30[0x4]; 7852 u8 repetitions_mode[0x4]; 7853 u8 num_of_repetitions[0x8]; 7854 7855 u8 grade_version[0x8]; 7856 u8 height_grade_type[0x4]; 7857 u8 phase_grade_type[0x4]; 7858 u8 height_grade_weight[0x8]; 7859 u8 phase_grade_weight[0x8]; 7860 7861 u8 gisim_measure_bits[0x10]; 7862 u8 adaptive_tap_measure_bits[0x10]; 7863 7864 u8 ber_bath_high_error_threshold[0x10]; 7865 u8 ber_bath_mid_error_threshold[0x10]; 7866 7867 u8 ber_bath_low_error_threshold[0x10]; 7868 u8 one_ratio_high_threshold[0x10]; 7869 7870 u8 one_ratio_high_mid_threshold[0x10]; 7871 u8 one_ratio_low_mid_threshold[0x10]; 7872 7873 u8 one_ratio_low_threshold[0x10]; 7874 u8 ndeo_error_threshold[0x10]; 7875 7876 u8 mixer_offset_step_size[0x10]; 7877 u8 reserved_at_110[0x8]; 7878 u8 mix90_phase_for_voltage_bath[0x8]; 7879 7880 u8 mixer_offset_start[0x10]; 7881 u8 mixer_offset_end[0x10]; 7882 7883 u8 reserved_at_140[0x15]; 7884 u8 ber_test_time[0xb]; 7885 }; 7886 7887 struct mlx5_ifc_pspa_reg_bits { 7888 u8 swid[0x8]; 7889 u8 local_port[0x8]; 7890 u8 sub_port[0x8]; 7891 u8 reserved_at_18[0x8]; 7892 7893 u8 reserved_at_20[0x20]; 7894 }; 7895 7896 struct mlx5_ifc_pqdr_reg_bits { 7897 u8 reserved_at_0[0x8]; 7898 u8 local_port[0x8]; 7899 u8 reserved_at_10[0x5]; 7900 u8 prio[0x3]; 7901 u8 reserved_at_18[0x6]; 7902 u8 mode[0x2]; 7903 7904 u8 reserved_at_20[0x20]; 7905 7906 u8 reserved_at_40[0x10]; 7907 u8 min_threshold[0x10]; 7908 7909 u8 reserved_at_60[0x10]; 7910 u8 max_threshold[0x10]; 7911 7912 u8 reserved_at_80[0x10]; 7913 u8 mark_probability_denominator[0x10]; 7914 7915 u8 reserved_at_a0[0x60]; 7916 }; 7917 7918 struct mlx5_ifc_ppsc_reg_bits { 7919 u8 reserved_at_0[0x8]; 7920 u8 local_port[0x8]; 7921 u8 reserved_at_10[0x10]; 7922 7923 u8 reserved_at_20[0x60]; 7924 7925 u8 reserved_at_80[0x1c]; 7926 u8 wrps_admin[0x4]; 7927 7928 u8 reserved_at_a0[0x1c]; 7929 u8 wrps_status[0x4]; 7930 7931 u8 reserved_at_c0[0x8]; 7932 u8 up_threshold[0x8]; 7933 u8 reserved_at_d0[0x8]; 7934 u8 down_threshold[0x8]; 7935 7936 u8 reserved_at_e0[0x20]; 7937 7938 u8 reserved_at_100[0x1c]; 7939 u8 srps_admin[0x4]; 7940 7941 u8 reserved_at_120[0x1c]; 7942 u8 srps_status[0x4]; 7943 7944 u8 reserved_at_140[0x40]; 7945 }; 7946 7947 struct mlx5_ifc_pplr_reg_bits { 7948 u8 reserved_at_0[0x8]; 7949 u8 local_port[0x8]; 7950 u8 reserved_at_10[0x10]; 7951 7952 u8 reserved_at_20[0x8]; 7953 u8 lb_cap[0x8]; 7954 u8 reserved_at_30[0x8]; 7955 u8 lb_en[0x8]; 7956 }; 7957 7958 struct mlx5_ifc_pplm_reg_bits { 7959 u8 reserved_at_0[0x8]; 7960 u8 local_port[0x8]; 7961 u8 reserved_at_10[0x10]; 7962 7963 u8 reserved_at_20[0x20]; 7964 7965 u8 port_profile_mode[0x8]; 7966 u8 static_port_profile[0x8]; 7967 u8 active_port_profile[0x8]; 7968 u8 reserved_at_58[0x8]; 7969 7970 u8 retransmission_active[0x8]; 7971 u8 fec_mode_active[0x18]; 7972 7973 u8 rs_fec_correction_bypass_cap[0x4]; 7974 u8 reserved_at_84[0x8]; 7975 u8 fec_override_cap_56g[0x4]; 7976 u8 fec_override_cap_100g[0x4]; 7977 u8 fec_override_cap_50g[0x4]; 7978 u8 fec_override_cap_25g[0x4]; 7979 u8 fec_override_cap_10g_40g[0x4]; 7980 7981 u8 rs_fec_correction_bypass_admin[0x4]; 7982 u8 reserved_at_a4[0x8]; 7983 u8 fec_override_admin_56g[0x4]; 7984 u8 fec_override_admin_100g[0x4]; 7985 u8 fec_override_admin_50g[0x4]; 7986 u8 fec_override_admin_25g[0x4]; 7987 u8 fec_override_admin_10g_40g[0x4]; 7988 }; 7989 7990 struct mlx5_ifc_ppcnt_reg_bits { 7991 u8 swid[0x8]; 7992 u8 local_port[0x8]; 7993 u8 pnat[0x2]; 7994 u8 reserved_at_12[0x8]; 7995 u8 grp[0x6]; 7996 7997 u8 clr[0x1]; 7998 u8 reserved_at_21[0x1c]; 7999 u8 prio_tc[0x3]; 8000 8001 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8002 }; 8003 8004 struct mlx5_ifc_mpcnt_reg_bits { 8005 u8 reserved_at_0[0x8]; 8006 u8 pcie_index[0x8]; 8007 u8 reserved_at_10[0xa]; 8008 u8 grp[0x6]; 8009 8010 u8 clr[0x1]; 8011 u8 reserved_at_21[0x1f]; 8012 8013 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8014 }; 8015 8016 struct mlx5_ifc_ppad_reg_bits { 8017 u8 reserved_at_0[0x3]; 8018 u8 single_mac[0x1]; 8019 u8 reserved_at_4[0x4]; 8020 u8 local_port[0x8]; 8021 u8 mac_47_32[0x10]; 8022 8023 u8 mac_31_0[0x20]; 8024 8025 u8 reserved_at_40[0x40]; 8026 }; 8027 8028 struct mlx5_ifc_pmtu_reg_bits { 8029 u8 reserved_at_0[0x8]; 8030 u8 local_port[0x8]; 8031 u8 reserved_at_10[0x10]; 8032 8033 u8 max_mtu[0x10]; 8034 u8 reserved_at_30[0x10]; 8035 8036 u8 admin_mtu[0x10]; 8037 u8 reserved_at_50[0x10]; 8038 8039 u8 oper_mtu[0x10]; 8040 u8 reserved_at_70[0x10]; 8041 }; 8042 8043 struct mlx5_ifc_pmpr_reg_bits { 8044 u8 reserved_at_0[0x8]; 8045 u8 module[0x8]; 8046 u8 reserved_at_10[0x10]; 8047 8048 u8 reserved_at_20[0x18]; 8049 u8 attenuation_5g[0x8]; 8050 8051 u8 reserved_at_40[0x18]; 8052 u8 attenuation_7g[0x8]; 8053 8054 u8 reserved_at_60[0x18]; 8055 u8 attenuation_12g[0x8]; 8056 }; 8057 8058 struct mlx5_ifc_pmpe_reg_bits { 8059 u8 reserved_at_0[0x8]; 8060 u8 module[0x8]; 8061 u8 reserved_at_10[0xc]; 8062 u8 module_status[0x4]; 8063 8064 u8 reserved_at_20[0x60]; 8065 }; 8066 8067 struct mlx5_ifc_pmpc_reg_bits { 8068 u8 module_state_updated[32][0x8]; 8069 }; 8070 8071 struct mlx5_ifc_pmlpn_reg_bits { 8072 u8 reserved_at_0[0x4]; 8073 u8 mlpn_status[0x4]; 8074 u8 local_port[0x8]; 8075 u8 reserved_at_10[0x10]; 8076 8077 u8 e[0x1]; 8078 u8 reserved_at_21[0x1f]; 8079 }; 8080 8081 struct mlx5_ifc_pmlp_reg_bits { 8082 u8 rxtx[0x1]; 8083 u8 reserved_at_1[0x7]; 8084 u8 local_port[0x8]; 8085 u8 reserved_at_10[0x8]; 8086 u8 width[0x8]; 8087 8088 u8 lane0_module_mapping[0x20]; 8089 8090 u8 lane1_module_mapping[0x20]; 8091 8092 u8 lane2_module_mapping[0x20]; 8093 8094 u8 lane3_module_mapping[0x20]; 8095 8096 u8 reserved_at_a0[0x160]; 8097 }; 8098 8099 struct mlx5_ifc_pmaos_reg_bits { 8100 u8 reserved_at_0[0x8]; 8101 u8 module[0x8]; 8102 u8 reserved_at_10[0x4]; 8103 u8 admin_status[0x4]; 8104 u8 reserved_at_18[0x4]; 8105 u8 oper_status[0x4]; 8106 8107 u8 ase[0x1]; 8108 u8 ee[0x1]; 8109 u8 reserved_at_22[0x1c]; 8110 u8 e[0x2]; 8111 8112 u8 reserved_at_40[0x40]; 8113 }; 8114 8115 struct mlx5_ifc_plpc_reg_bits { 8116 u8 reserved_at_0[0x4]; 8117 u8 profile_id[0xc]; 8118 u8 reserved_at_10[0x4]; 8119 u8 proto_mask[0x4]; 8120 u8 reserved_at_18[0x8]; 8121 8122 u8 reserved_at_20[0x10]; 8123 u8 lane_speed[0x10]; 8124 8125 u8 reserved_at_40[0x17]; 8126 u8 lpbf[0x1]; 8127 u8 fec_mode_policy[0x8]; 8128 8129 u8 retransmission_capability[0x8]; 8130 u8 fec_mode_capability[0x18]; 8131 8132 u8 retransmission_support_admin[0x8]; 8133 u8 fec_mode_support_admin[0x18]; 8134 8135 u8 retransmission_request_admin[0x8]; 8136 u8 fec_mode_request_admin[0x18]; 8137 8138 u8 reserved_at_c0[0x80]; 8139 }; 8140 8141 struct mlx5_ifc_plib_reg_bits { 8142 u8 reserved_at_0[0x8]; 8143 u8 local_port[0x8]; 8144 u8 reserved_at_10[0x8]; 8145 u8 ib_port[0x8]; 8146 8147 u8 reserved_at_20[0x60]; 8148 }; 8149 8150 struct mlx5_ifc_plbf_reg_bits { 8151 u8 reserved_at_0[0x8]; 8152 u8 local_port[0x8]; 8153 u8 reserved_at_10[0xd]; 8154 u8 lbf_mode[0x3]; 8155 8156 u8 reserved_at_20[0x20]; 8157 }; 8158 8159 struct mlx5_ifc_pipg_reg_bits { 8160 u8 reserved_at_0[0x8]; 8161 u8 local_port[0x8]; 8162 u8 reserved_at_10[0x10]; 8163 8164 u8 dic[0x1]; 8165 u8 reserved_at_21[0x19]; 8166 u8 ipg[0x4]; 8167 u8 reserved_at_3e[0x2]; 8168 }; 8169 8170 struct mlx5_ifc_pifr_reg_bits { 8171 u8 reserved_at_0[0x8]; 8172 u8 local_port[0x8]; 8173 u8 reserved_at_10[0x10]; 8174 8175 u8 reserved_at_20[0xe0]; 8176 8177 u8 port_filter[8][0x20]; 8178 8179 u8 port_filter_update_en[8][0x20]; 8180 }; 8181 8182 struct mlx5_ifc_pfcc_reg_bits { 8183 u8 reserved_at_0[0x8]; 8184 u8 local_port[0x8]; 8185 u8 reserved_at_10[0xb]; 8186 u8 ppan_mask_n[0x1]; 8187 u8 minor_stall_mask[0x1]; 8188 u8 critical_stall_mask[0x1]; 8189 u8 reserved_at_1e[0x2]; 8190 8191 u8 ppan[0x4]; 8192 u8 reserved_at_24[0x4]; 8193 u8 prio_mask_tx[0x8]; 8194 u8 reserved_at_30[0x8]; 8195 u8 prio_mask_rx[0x8]; 8196 8197 u8 pptx[0x1]; 8198 u8 aptx[0x1]; 8199 u8 pptx_mask_n[0x1]; 8200 u8 reserved_at_43[0x5]; 8201 u8 pfctx[0x8]; 8202 u8 reserved_at_50[0x10]; 8203 8204 u8 pprx[0x1]; 8205 u8 aprx[0x1]; 8206 u8 pprx_mask_n[0x1]; 8207 u8 reserved_at_63[0x5]; 8208 u8 pfcrx[0x8]; 8209 u8 reserved_at_70[0x10]; 8210 8211 u8 device_stall_minor_watermark[0x10]; 8212 u8 device_stall_critical_watermark[0x10]; 8213 8214 u8 reserved_at_a0[0x60]; 8215 }; 8216 8217 struct mlx5_ifc_pelc_reg_bits { 8218 u8 op[0x4]; 8219 u8 reserved_at_4[0x4]; 8220 u8 local_port[0x8]; 8221 u8 reserved_at_10[0x10]; 8222 8223 u8 op_admin[0x8]; 8224 u8 op_capability[0x8]; 8225 u8 op_request[0x8]; 8226 u8 op_active[0x8]; 8227 8228 u8 admin[0x40]; 8229 8230 u8 capability[0x40]; 8231 8232 u8 request[0x40]; 8233 8234 u8 active[0x40]; 8235 8236 u8 reserved_at_140[0x80]; 8237 }; 8238 8239 struct mlx5_ifc_peir_reg_bits { 8240 u8 reserved_at_0[0x8]; 8241 u8 local_port[0x8]; 8242 u8 reserved_at_10[0x10]; 8243 8244 u8 reserved_at_20[0xc]; 8245 u8 error_count[0x4]; 8246 u8 reserved_at_30[0x10]; 8247 8248 u8 reserved_at_40[0xc]; 8249 u8 lane[0x4]; 8250 u8 reserved_at_50[0x8]; 8251 u8 error_type[0x8]; 8252 }; 8253 8254 struct mlx5_ifc_mpegc_reg_bits { 8255 u8 reserved_at_0[0x30]; 8256 u8 field_select[0x10]; 8257 8258 u8 tx_overflow_sense[0x1]; 8259 u8 mark_cqe[0x1]; 8260 u8 mark_cnp[0x1]; 8261 u8 reserved_at_43[0x1b]; 8262 u8 tx_lossy_overflow_oper[0x2]; 8263 8264 u8 reserved_at_60[0x100]; 8265 }; 8266 8267 struct mlx5_ifc_pcam_enhanced_features_bits { 8268 u8 reserved_at_0[0x6d]; 8269 u8 rx_icrc_encapsulated_counter[0x1]; 8270 u8 reserved_at_6e[0x8]; 8271 u8 pfcc_mask[0x1]; 8272 u8 reserved_at_77[0x3]; 8273 u8 per_lane_error_counters[0x1]; 8274 u8 rx_buffer_fullness_counters[0x1]; 8275 u8 ptys_connector_type[0x1]; 8276 u8 reserved_at_7d[0x1]; 8277 u8 ppcnt_discard_group[0x1]; 8278 u8 ppcnt_statistical_group[0x1]; 8279 }; 8280 8281 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8282 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8283 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8284 8285 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8286 u8 pplm[0x1]; 8287 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8288 8289 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8290 u8 pbmc[0x1]; 8291 u8 pptb[0x1]; 8292 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8293 u8 ppcnt[0x1]; 8294 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8295 }; 8296 8297 struct mlx5_ifc_pcam_reg_bits { 8298 u8 reserved_at_0[0x8]; 8299 u8 feature_group[0x8]; 8300 u8 reserved_at_10[0x8]; 8301 u8 access_reg_group[0x8]; 8302 8303 u8 reserved_at_20[0x20]; 8304 8305 union { 8306 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8307 u8 reserved_at_0[0x80]; 8308 } port_access_reg_cap_mask; 8309 8310 u8 reserved_at_c0[0x80]; 8311 8312 union { 8313 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8314 u8 reserved_at_0[0x80]; 8315 } feature_cap_mask; 8316 8317 u8 reserved_at_1c0[0xc0]; 8318 }; 8319 8320 struct mlx5_ifc_mcam_enhanced_features_bits { 8321 u8 reserved_at_0[0x74]; 8322 u8 mark_tx_action_cnp[0x1]; 8323 u8 mark_tx_action_cqe[0x1]; 8324 u8 dynamic_tx_overflow[0x1]; 8325 u8 reserved_at_77[0x4]; 8326 u8 pcie_outbound_stalled[0x1]; 8327 u8 tx_overflow_buffer_pkt[0x1]; 8328 u8 mtpps_enh_out_per_adj[0x1]; 8329 u8 mtpps_fs[0x1]; 8330 u8 pcie_performance_group[0x1]; 8331 }; 8332 8333 struct mlx5_ifc_mcam_access_reg_bits { 8334 u8 reserved_at_0[0x1c]; 8335 u8 mcda[0x1]; 8336 u8 mcc[0x1]; 8337 u8 mcqi[0x1]; 8338 u8 reserved_at_1f[0x1]; 8339 8340 u8 regs_95_to_87[0x9]; 8341 u8 mpegc[0x1]; 8342 u8 regs_85_to_68[0x12]; 8343 u8 tracer_registers[0x4]; 8344 8345 u8 regs_63_to_32[0x20]; 8346 u8 regs_31_to_0[0x20]; 8347 }; 8348 8349 struct mlx5_ifc_mcam_reg_bits { 8350 u8 reserved_at_0[0x8]; 8351 u8 feature_group[0x8]; 8352 u8 reserved_at_10[0x8]; 8353 u8 access_reg_group[0x8]; 8354 8355 u8 reserved_at_20[0x20]; 8356 8357 union { 8358 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8359 u8 reserved_at_0[0x80]; 8360 } mng_access_reg_cap_mask; 8361 8362 u8 reserved_at_c0[0x80]; 8363 8364 union { 8365 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8366 u8 reserved_at_0[0x80]; 8367 } mng_feature_cap_mask; 8368 8369 u8 reserved_at_1c0[0x80]; 8370 }; 8371 8372 struct mlx5_ifc_qcam_access_reg_cap_mask { 8373 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8374 u8 qpdpm[0x1]; 8375 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8376 u8 qdpm[0x1]; 8377 u8 qpts[0x1]; 8378 u8 qcap[0x1]; 8379 u8 qcam_access_reg_cap_mask_0[0x1]; 8380 }; 8381 8382 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8383 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8384 u8 qpts_trust_both[0x1]; 8385 }; 8386 8387 struct mlx5_ifc_qcam_reg_bits { 8388 u8 reserved_at_0[0x8]; 8389 u8 feature_group[0x8]; 8390 u8 reserved_at_10[0x8]; 8391 u8 access_reg_group[0x8]; 8392 u8 reserved_at_20[0x20]; 8393 8394 union { 8395 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8396 u8 reserved_at_0[0x80]; 8397 } qos_access_reg_cap_mask; 8398 8399 u8 reserved_at_c0[0x80]; 8400 8401 union { 8402 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8403 u8 reserved_at_0[0x80]; 8404 } qos_feature_cap_mask; 8405 8406 u8 reserved_at_1c0[0x80]; 8407 }; 8408 8409 struct mlx5_ifc_pcap_reg_bits { 8410 u8 reserved_at_0[0x8]; 8411 u8 local_port[0x8]; 8412 u8 reserved_at_10[0x10]; 8413 8414 u8 port_capability_mask[4][0x20]; 8415 }; 8416 8417 struct mlx5_ifc_paos_reg_bits { 8418 u8 swid[0x8]; 8419 u8 local_port[0x8]; 8420 u8 reserved_at_10[0x4]; 8421 u8 admin_status[0x4]; 8422 u8 reserved_at_18[0x4]; 8423 u8 oper_status[0x4]; 8424 8425 u8 ase[0x1]; 8426 u8 ee[0x1]; 8427 u8 reserved_at_22[0x1c]; 8428 u8 e[0x2]; 8429 8430 u8 reserved_at_40[0x40]; 8431 }; 8432 8433 struct mlx5_ifc_pamp_reg_bits { 8434 u8 reserved_at_0[0x8]; 8435 u8 opamp_group[0x8]; 8436 u8 reserved_at_10[0xc]; 8437 u8 opamp_group_type[0x4]; 8438 8439 u8 start_index[0x10]; 8440 u8 reserved_at_30[0x4]; 8441 u8 num_of_indices[0xc]; 8442 8443 u8 index_data[18][0x10]; 8444 }; 8445 8446 struct mlx5_ifc_pcmr_reg_bits { 8447 u8 reserved_at_0[0x8]; 8448 u8 local_port[0x8]; 8449 u8 reserved_at_10[0x2e]; 8450 u8 fcs_cap[0x1]; 8451 u8 reserved_at_3f[0x1f]; 8452 u8 fcs_chk[0x1]; 8453 u8 reserved_at_5f[0x1]; 8454 }; 8455 8456 struct mlx5_ifc_lane_2_module_mapping_bits { 8457 u8 reserved_at_0[0x6]; 8458 u8 rx_lane[0x2]; 8459 u8 reserved_at_8[0x6]; 8460 u8 tx_lane[0x2]; 8461 u8 reserved_at_10[0x8]; 8462 u8 module[0x8]; 8463 }; 8464 8465 struct mlx5_ifc_bufferx_reg_bits { 8466 u8 reserved_at_0[0x6]; 8467 u8 lossy[0x1]; 8468 u8 epsb[0x1]; 8469 u8 reserved_at_8[0xc]; 8470 u8 size[0xc]; 8471 8472 u8 xoff_threshold[0x10]; 8473 u8 xon_threshold[0x10]; 8474 }; 8475 8476 struct mlx5_ifc_set_node_in_bits { 8477 u8 node_description[64][0x8]; 8478 }; 8479 8480 struct mlx5_ifc_register_power_settings_bits { 8481 u8 reserved_at_0[0x18]; 8482 u8 power_settings_level[0x8]; 8483 8484 u8 reserved_at_20[0x60]; 8485 }; 8486 8487 struct mlx5_ifc_register_host_endianness_bits { 8488 u8 he[0x1]; 8489 u8 reserved_at_1[0x1f]; 8490 8491 u8 reserved_at_20[0x60]; 8492 }; 8493 8494 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8495 u8 reserved_at_0[0x20]; 8496 8497 u8 mkey[0x20]; 8498 8499 u8 addressh_63_32[0x20]; 8500 8501 u8 addressl_31_0[0x20]; 8502 }; 8503 8504 struct mlx5_ifc_ud_adrs_vector_bits { 8505 u8 dc_key[0x40]; 8506 8507 u8 ext[0x1]; 8508 u8 reserved_at_41[0x7]; 8509 u8 destination_qp_dct[0x18]; 8510 8511 u8 static_rate[0x4]; 8512 u8 sl_eth_prio[0x4]; 8513 u8 fl[0x1]; 8514 u8 mlid[0x7]; 8515 u8 rlid_udp_sport[0x10]; 8516 8517 u8 reserved_at_80[0x20]; 8518 8519 u8 rmac_47_16[0x20]; 8520 8521 u8 rmac_15_0[0x10]; 8522 u8 tclass[0x8]; 8523 u8 hop_limit[0x8]; 8524 8525 u8 reserved_at_e0[0x1]; 8526 u8 grh[0x1]; 8527 u8 reserved_at_e2[0x2]; 8528 u8 src_addr_index[0x8]; 8529 u8 flow_label[0x14]; 8530 8531 u8 rgid_rip[16][0x8]; 8532 }; 8533 8534 struct mlx5_ifc_pages_req_event_bits { 8535 u8 reserved_at_0[0x10]; 8536 u8 function_id[0x10]; 8537 8538 u8 num_pages[0x20]; 8539 8540 u8 reserved_at_40[0xa0]; 8541 }; 8542 8543 struct mlx5_ifc_eqe_bits { 8544 u8 reserved_at_0[0x8]; 8545 u8 event_type[0x8]; 8546 u8 reserved_at_10[0x8]; 8547 u8 event_sub_type[0x8]; 8548 8549 u8 reserved_at_20[0xe0]; 8550 8551 union mlx5_ifc_event_auto_bits event_data; 8552 8553 u8 reserved_at_1e0[0x10]; 8554 u8 signature[0x8]; 8555 u8 reserved_at_1f8[0x7]; 8556 u8 owner[0x1]; 8557 }; 8558 8559 enum { 8560 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8561 }; 8562 8563 struct mlx5_ifc_cmd_queue_entry_bits { 8564 u8 type[0x8]; 8565 u8 reserved_at_8[0x18]; 8566 8567 u8 input_length[0x20]; 8568 8569 u8 input_mailbox_pointer_63_32[0x20]; 8570 8571 u8 input_mailbox_pointer_31_9[0x17]; 8572 u8 reserved_at_77[0x9]; 8573 8574 u8 command_input_inline_data[16][0x8]; 8575 8576 u8 command_output_inline_data[16][0x8]; 8577 8578 u8 output_mailbox_pointer_63_32[0x20]; 8579 8580 u8 output_mailbox_pointer_31_9[0x17]; 8581 u8 reserved_at_1b7[0x9]; 8582 8583 u8 output_length[0x20]; 8584 8585 u8 token[0x8]; 8586 u8 signature[0x8]; 8587 u8 reserved_at_1f0[0x8]; 8588 u8 status[0x7]; 8589 u8 ownership[0x1]; 8590 }; 8591 8592 struct mlx5_ifc_cmd_out_bits { 8593 u8 status[0x8]; 8594 u8 reserved_at_8[0x18]; 8595 8596 u8 syndrome[0x20]; 8597 8598 u8 command_output[0x20]; 8599 }; 8600 8601 struct mlx5_ifc_cmd_in_bits { 8602 u8 opcode[0x10]; 8603 u8 reserved_at_10[0x10]; 8604 8605 u8 reserved_at_20[0x10]; 8606 u8 op_mod[0x10]; 8607 8608 u8 command[0][0x20]; 8609 }; 8610 8611 struct mlx5_ifc_cmd_if_box_bits { 8612 u8 mailbox_data[512][0x8]; 8613 8614 u8 reserved_at_1000[0x180]; 8615 8616 u8 next_pointer_63_32[0x20]; 8617 8618 u8 next_pointer_31_10[0x16]; 8619 u8 reserved_at_11b6[0xa]; 8620 8621 u8 block_number[0x20]; 8622 8623 u8 reserved_at_11e0[0x8]; 8624 u8 token[0x8]; 8625 u8 ctrl_signature[0x8]; 8626 u8 signature[0x8]; 8627 }; 8628 8629 struct mlx5_ifc_mtt_bits { 8630 u8 ptag_63_32[0x20]; 8631 8632 u8 ptag_31_8[0x18]; 8633 u8 reserved_at_38[0x6]; 8634 u8 wr_en[0x1]; 8635 u8 rd_en[0x1]; 8636 }; 8637 8638 struct mlx5_ifc_query_wol_rol_out_bits { 8639 u8 status[0x8]; 8640 u8 reserved_at_8[0x18]; 8641 8642 u8 syndrome[0x20]; 8643 8644 u8 reserved_at_40[0x10]; 8645 u8 rol_mode[0x8]; 8646 u8 wol_mode[0x8]; 8647 8648 u8 reserved_at_60[0x20]; 8649 }; 8650 8651 struct mlx5_ifc_query_wol_rol_in_bits { 8652 u8 opcode[0x10]; 8653 u8 reserved_at_10[0x10]; 8654 8655 u8 reserved_at_20[0x10]; 8656 u8 op_mod[0x10]; 8657 8658 u8 reserved_at_40[0x40]; 8659 }; 8660 8661 struct mlx5_ifc_set_wol_rol_out_bits { 8662 u8 status[0x8]; 8663 u8 reserved_at_8[0x18]; 8664 8665 u8 syndrome[0x20]; 8666 8667 u8 reserved_at_40[0x40]; 8668 }; 8669 8670 struct mlx5_ifc_set_wol_rol_in_bits { 8671 u8 opcode[0x10]; 8672 u8 reserved_at_10[0x10]; 8673 8674 u8 reserved_at_20[0x10]; 8675 u8 op_mod[0x10]; 8676 8677 u8 rol_mode_valid[0x1]; 8678 u8 wol_mode_valid[0x1]; 8679 u8 reserved_at_42[0xe]; 8680 u8 rol_mode[0x8]; 8681 u8 wol_mode[0x8]; 8682 8683 u8 reserved_at_60[0x20]; 8684 }; 8685 8686 enum { 8687 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8688 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8689 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8690 }; 8691 8692 enum { 8693 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8694 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8695 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8696 }; 8697 8698 enum { 8699 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8700 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8701 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8702 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8703 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8704 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8705 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8706 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8707 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8708 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8709 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8710 }; 8711 8712 struct mlx5_ifc_initial_seg_bits { 8713 u8 fw_rev_minor[0x10]; 8714 u8 fw_rev_major[0x10]; 8715 8716 u8 cmd_interface_rev[0x10]; 8717 u8 fw_rev_subminor[0x10]; 8718 8719 u8 reserved_at_40[0x40]; 8720 8721 u8 cmdq_phy_addr_63_32[0x20]; 8722 8723 u8 cmdq_phy_addr_31_12[0x14]; 8724 u8 reserved_at_b4[0x2]; 8725 u8 nic_interface[0x2]; 8726 u8 log_cmdq_size[0x4]; 8727 u8 log_cmdq_stride[0x4]; 8728 8729 u8 command_doorbell_vector[0x20]; 8730 8731 u8 reserved_at_e0[0xf00]; 8732 8733 u8 initializing[0x1]; 8734 u8 reserved_at_fe1[0x4]; 8735 u8 nic_interface_supported[0x3]; 8736 u8 reserved_at_fe8[0x18]; 8737 8738 struct mlx5_ifc_health_buffer_bits health_buffer; 8739 8740 u8 no_dram_nic_offset[0x20]; 8741 8742 u8 reserved_at_1220[0x6e40]; 8743 8744 u8 reserved_at_8060[0x1f]; 8745 u8 clear_int[0x1]; 8746 8747 u8 health_syndrome[0x8]; 8748 u8 health_counter[0x18]; 8749 8750 u8 reserved_at_80a0[0x17fc0]; 8751 }; 8752 8753 struct mlx5_ifc_mtpps_reg_bits { 8754 u8 reserved_at_0[0xc]; 8755 u8 cap_number_of_pps_pins[0x4]; 8756 u8 reserved_at_10[0x4]; 8757 u8 cap_max_num_of_pps_in_pins[0x4]; 8758 u8 reserved_at_18[0x4]; 8759 u8 cap_max_num_of_pps_out_pins[0x4]; 8760 8761 u8 reserved_at_20[0x24]; 8762 u8 cap_pin_3_mode[0x4]; 8763 u8 reserved_at_48[0x4]; 8764 u8 cap_pin_2_mode[0x4]; 8765 u8 reserved_at_50[0x4]; 8766 u8 cap_pin_1_mode[0x4]; 8767 u8 reserved_at_58[0x4]; 8768 u8 cap_pin_0_mode[0x4]; 8769 8770 u8 reserved_at_60[0x4]; 8771 u8 cap_pin_7_mode[0x4]; 8772 u8 reserved_at_68[0x4]; 8773 u8 cap_pin_6_mode[0x4]; 8774 u8 reserved_at_70[0x4]; 8775 u8 cap_pin_5_mode[0x4]; 8776 u8 reserved_at_78[0x4]; 8777 u8 cap_pin_4_mode[0x4]; 8778 8779 u8 field_select[0x20]; 8780 u8 reserved_at_a0[0x60]; 8781 8782 u8 enable[0x1]; 8783 u8 reserved_at_101[0xb]; 8784 u8 pattern[0x4]; 8785 u8 reserved_at_110[0x4]; 8786 u8 pin_mode[0x4]; 8787 u8 pin[0x8]; 8788 8789 u8 reserved_at_120[0x20]; 8790 8791 u8 time_stamp[0x40]; 8792 8793 u8 out_pulse_duration[0x10]; 8794 u8 out_periodic_adjustment[0x10]; 8795 u8 enhanced_out_periodic_adjustment[0x20]; 8796 8797 u8 reserved_at_1c0[0x20]; 8798 }; 8799 8800 struct mlx5_ifc_mtppse_reg_bits { 8801 u8 reserved_at_0[0x18]; 8802 u8 pin[0x8]; 8803 u8 event_arm[0x1]; 8804 u8 reserved_at_21[0x1b]; 8805 u8 event_generation_mode[0x4]; 8806 u8 reserved_at_40[0x40]; 8807 }; 8808 8809 struct mlx5_ifc_mcqi_cap_bits { 8810 u8 supported_info_bitmask[0x20]; 8811 8812 u8 component_size[0x20]; 8813 8814 u8 max_component_size[0x20]; 8815 8816 u8 log_mcda_word_size[0x4]; 8817 u8 reserved_at_64[0xc]; 8818 u8 mcda_max_write_size[0x10]; 8819 8820 u8 rd_en[0x1]; 8821 u8 reserved_at_81[0x1]; 8822 u8 match_chip_id[0x1]; 8823 u8 match_psid[0x1]; 8824 u8 check_user_timestamp[0x1]; 8825 u8 match_base_guid_mac[0x1]; 8826 u8 reserved_at_86[0x1a]; 8827 }; 8828 8829 struct mlx5_ifc_mcqi_reg_bits { 8830 u8 read_pending_component[0x1]; 8831 u8 reserved_at_1[0xf]; 8832 u8 component_index[0x10]; 8833 8834 u8 reserved_at_20[0x20]; 8835 8836 u8 reserved_at_40[0x1b]; 8837 u8 info_type[0x5]; 8838 8839 u8 info_size[0x20]; 8840 8841 u8 offset[0x20]; 8842 8843 u8 reserved_at_a0[0x10]; 8844 u8 data_size[0x10]; 8845 8846 u8 data[0][0x20]; 8847 }; 8848 8849 struct mlx5_ifc_mcc_reg_bits { 8850 u8 reserved_at_0[0x4]; 8851 u8 time_elapsed_since_last_cmd[0xc]; 8852 u8 reserved_at_10[0x8]; 8853 u8 instruction[0x8]; 8854 8855 u8 reserved_at_20[0x10]; 8856 u8 component_index[0x10]; 8857 8858 u8 reserved_at_40[0x8]; 8859 u8 update_handle[0x18]; 8860 8861 u8 handle_owner_type[0x4]; 8862 u8 handle_owner_host_id[0x4]; 8863 u8 reserved_at_68[0x1]; 8864 u8 control_progress[0x7]; 8865 u8 error_code[0x8]; 8866 u8 reserved_at_78[0x4]; 8867 u8 control_state[0x4]; 8868 8869 u8 component_size[0x20]; 8870 8871 u8 reserved_at_a0[0x60]; 8872 }; 8873 8874 struct mlx5_ifc_mcda_reg_bits { 8875 u8 reserved_at_0[0x8]; 8876 u8 update_handle[0x18]; 8877 8878 u8 offset[0x20]; 8879 8880 u8 reserved_at_40[0x10]; 8881 u8 size[0x10]; 8882 8883 u8 reserved_at_60[0x20]; 8884 8885 u8 data[0][0x20]; 8886 }; 8887 8888 union mlx5_ifc_ports_control_registers_document_bits { 8889 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8890 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8891 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8892 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8893 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8894 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8895 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8896 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8897 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8898 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8899 struct mlx5_ifc_paos_reg_bits paos_reg; 8900 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8901 struct mlx5_ifc_peir_reg_bits peir_reg; 8902 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8903 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8904 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8905 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8906 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8907 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8908 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8909 struct mlx5_ifc_plib_reg_bits plib_reg; 8910 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8911 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8912 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8913 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8914 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8915 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8916 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8917 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8918 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8919 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8920 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8921 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8922 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8923 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8924 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8925 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8926 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8927 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8928 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8929 struct mlx5_ifc_pude_reg_bits pude_reg; 8930 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8931 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8932 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8933 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8934 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8935 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8936 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8937 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8938 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8939 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8940 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8941 u8 reserved_at_0[0x60e0]; 8942 }; 8943 8944 union mlx5_ifc_debug_enhancements_document_bits { 8945 struct mlx5_ifc_health_buffer_bits health_buffer; 8946 u8 reserved_at_0[0x200]; 8947 }; 8948 8949 union mlx5_ifc_uplink_pci_interface_document_bits { 8950 struct mlx5_ifc_initial_seg_bits initial_seg; 8951 u8 reserved_at_0[0x20060]; 8952 }; 8953 8954 struct mlx5_ifc_set_flow_table_root_out_bits { 8955 u8 status[0x8]; 8956 u8 reserved_at_8[0x18]; 8957 8958 u8 syndrome[0x20]; 8959 8960 u8 reserved_at_40[0x40]; 8961 }; 8962 8963 struct mlx5_ifc_set_flow_table_root_in_bits { 8964 u8 opcode[0x10]; 8965 u8 reserved_at_10[0x10]; 8966 8967 u8 reserved_at_20[0x10]; 8968 u8 op_mod[0x10]; 8969 8970 u8 other_vport[0x1]; 8971 u8 reserved_at_41[0xf]; 8972 u8 vport_number[0x10]; 8973 8974 u8 reserved_at_60[0x20]; 8975 8976 u8 table_type[0x8]; 8977 u8 reserved_at_88[0x18]; 8978 8979 u8 reserved_at_a0[0x8]; 8980 u8 table_id[0x18]; 8981 8982 u8 reserved_at_c0[0x8]; 8983 u8 underlay_qpn[0x18]; 8984 u8 reserved_at_e0[0x120]; 8985 }; 8986 8987 enum { 8988 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8989 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8990 }; 8991 8992 struct mlx5_ifc_modify_flow_table_out_bits { 8993 u8 status[0x8]; 8994 u8 reserved_at_8[0x18]; 8995 8996 u8 syndrome[0x20]; 8997 8998 u8 reserved_at_40[0x40]; 8999 }; 9000 9001 struct mlx5_ifc_modify_flow_table_in_bits { 9002 u8 opcode[0x10]; 9003 u8 reserved_at_10[0x10]; 9004 9005 u8 reserved_at_20[0x10]; 9006 u8 op_mod[0x10]; 9007 9008 u8 other_vport[0x1]; 9009 u8 reserved_at_41[0xf]; 9010 u8 vport_number[0x10]; 9011 9012 u8 reserved_at_60[0x10]; 9013 u8 modify_field_select[0x10]; 9014 9015 u8 table_type[0x8]; 9016 u8 reserved_at_88[0x18]; 9017 9018 u8 reserved_at_a0[0x8]; 9019 u8 table_id[0x18]; 9020 9021 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9022 }; 9023 9024 struct mlx5_ifc_ets_tcn_config_reg_bits { 9025 u8 g[0x1]; 9026 u8 b[0x1]; 9027 u8 r[0x1]; 9028 u8 reserved_at_3[0x9]; 9029 u8 group[0x4]; 9030 u8 reserved_at_10[0x9]; 9031 u8 bw_allocation[0x7]; 9032 9033 u8 reserved_at_20[0xc]; 9034 u8 max_bw_units[0x4]; 9035 u8 reserved_at_30[0x8]; 9036 u8 max_bw_value[0x8]; 9037 }; 9038 9039 struct mlx5_ifc_ets_global_config_reg_bits { 9040 u8 reserved_at_0[0x2]; 9041 u8 r[0x1]; 9042 u8 reserved_at_3[0x1d]; 9043 9044 u8 reserved_at_20[0xc]; 9045 u8 max_bw_units[0x4]; 9046 u8 reserved_at_30[0x8]; 9047 u8 max_bw_value[0x8]; 9048 }; 9049 9050 struct mlx5_ifc_qetc_reg_bits { 9051 u8 reserved_at_0[0x8]; 9052 u8 port_number[0x8]; 9053 u8 reserved_at_10[0x30]; 9054 9055 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9056 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9057 }; 9058 9059 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9060 u8 e[0x1]; 9061 u8 reserved_at_01[0x0b]; 9062 u8 prio[0x04]; 9063 }; 9064 9065 struct mlx5_ifc_qpdpm_reg_bits { 9066 u8 reserved_at_0[0x8]; 9067 u8 local_port[0x8]; 9068 u8 reserved_at_10[0x10]; 9069 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9070 }; 9071 9072 struct mlx5_ifc_qpts_reg_bits { 9073 u8 reserved_at_0[0x8]; 9074 u8 local_port[0x8]; 9075 u8 reserved_at_10[0x2d]; 9076 u8 trust_state[0x3]; 9077 }; 9078 9079 struct mlx5_ifc_pptb_reg_bits { 9080 u8 reserved_at_0[0x2]; 9081 u8 mm[0x2]; 9082 u8 reserved_at_4[0x4]; 9083 u8 local_port[0x8]; 9084 u8 reserved_at_10[0x6]; 9085 u8 cm[0x1]; 9086 u8 um[0x1]; 9087 u8 pm[0x8]; 9088 9089 u8 prio_x_buff[0x20]; 9090 9091 u8 pm_msb[0x8]; 9092 u8 reserved_at_48[0x10]; 9093 u8 ctrl_buff[0x4]; 9094 u8 untagged_buff[0x4]; 9095 }; 9096 9097 struct mlx5_ifc_pbmc_reg_bits { 9098 u8 reserved_at_0[0x8]; 9099 u8 local_port[0x8]; 9100 u8 reserved_at_10[0x10]; 9101 9102 u8 xoff_timer_value[0x10]; 9103 u8 xoff_refresh[0x10]; 9104 9105 u8 reserved_at_40[0x9]; 9106 u8 fullness_threshold[0x7]; 9107 u8 port_buffer_size[0x10]; 9108 9109 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9110 9111 u8 reserved_at_2e0[0x40]; 9112 }; 9113 9114 struct mlx5_ifc_qtct_reg_bits { 9115 u8 reserved_at_0[0x8]; 9116 u8 port_number[0x8]; 9117 u8 reserved_at_10[0xd]; 9118 u8 prio[0x3]; 9119 9120 u8 reserved_at_20[0x1d]; 9121 u8 tclass[0x3]; 9122 }; 9123 9124 struct mlx5_ifc_mcia_reg_bits { 9125 u8 l[0x1]; 9126 u8 reserved_at_1[0x7]; 9127 u8 module[0x8]; 9128 u8 reserved_at_10[0x8]; 9129 u8 status[0x8]; 9130 9131 u8 i2c_device_address[0x8]; 9132 u8 page_number[0x8]; 9133 u8 device_address[0x10]; 9134 9135 u8 reserved_at_40[0x10]; 9136 u8 size[0x10]; 9137 9138 u8 reserved_at_60[0x20]; 9139 9140 u8 dword_0[0x20]; 9141 u8 dword_1[0x20]; 9142 u8 dword_2[0x20]; 9143 u8 dword_3[0x20]; 9144 u8 dword_4[0x20]; 9145 u8 dword_5[0x20]; 9146 u8 dword_6[0x20]; 9147 u8 dword_7[0x20]; 9148 u8 dword_8[0x20]; 9149 u8 dword_9[0x20]; 9150 u8 dword_10[0x20]; 9151 u8 dword_11[0x20]; 9152 }; 9153 9154 struct mlx5_ifc_dcbx_param_bits { 9155 u8 dcbx_cee_cap[0x1]; 9156 u8 dcbx_ieee_cap[0x1]; 9157 u8 dcbx_standby_cap[0x1]; 9158 u8 reserved_at_3[0x5]; 9159 u8 port_number[0x8]; 9160 u8 reserved_at_10[0xa]; 9161 u8 max_application_table_size[6]; 9162 u8 reserved_at_20[0x15]; 9163 u8 version_oper[0x3]; 9164 u8 reserved_at_38[5]; 9165 u8 version_admin[0x3]; 9166 u8 willing_admin[0x1]; 9167 u8 reserved_at_41[0x3]; 9168 u8 pfc_cap_oper[0x4]; 9169 u8 reserved_at_48[0x4]; 9170 u8 pfc_cap_admin[0x4]; 9171 u8 reserved_at_50[0x4]; 9172 u8 num_of_tc_oper[0x4]; 9173 u8 reserved_at_58[0x4]; 9174 u8 num_of_tc_admin[0x4]; 9175 u8 remote_willing[0x1]; 9176 u8 reserved_at_61[3]; 9177 u8 remote_pfc_cap[4]; 9178 u8 reserved_at_68[0x14]; 9179 u8 remote_num_of_tc[0x4]; 9180 u8 reserved_at_80[0x18]; 9181 u8 error[0x8]; 9182 u8 reserved_at_a0[0x160]; 9183 }; 9184 9185 struct mlx5_ifc_lagc_bits { 9186 u8 reserved_at_0[0x1d]; 9187 u8 lag_state[0x3]; 9188 9189 u8 reserved_at_20[0x14]; 9190 u8 tx_remap_affinity_2[0x4]; 9191 u8 reserved_at_38[0x4]; 9192 u8 tx_remap_affinity_1[0x4]; 9193 }; 9194 9195 struct mlx5_ifc_create_lag_out_bits { 9196 u8 status[0x8]; 9197 u8 reserved_at_8[0x18]; 9198 9199 u8 syndrome[0x20]; 9200 9201 u8 reserved_at_40[0x40]; 9202 }; 9203 9204 struct mlx5_ifc_create_lag_in_bits { 9205 u8 opcode[0x10]; 9206 u8 reserved_at_10[0x10]; 9207 9208 u8 reserved_at_20[0x10]; 9209 u8 op_mod[0x10]; 9210 9211 struct mlx5_ifc_lagc_bits ctx; 9212 }; 9213 9214 struct mlx5_ifc_modify_lag_out_bits { 9215 u8 status[0x8]; 9216 u8 reserved_at_8[0x18]; 9217 9218 u8 syndrome[0x20]; 9219 9220 u8 reserved_at_40[0x40]; 9221 }; 9222 9223 struct mlx5_ifc_modify_lag_in_bits { 9224 u8 opcode[0x10]; 9225 u8 reserved_at_10[0x10]; 9226 9227 u8 reserved_at_20[0x10]; 9228 u8 op_mod[0x10]; 9229 9230 u8 reserved_at_40[0x20]; 9231 u8 field_select[0x20]; 9232 9233 struct mlx5_ifc_lagc_bits ctx; 9234 }; 9235 9236 struct mlx5_ifc_query_lag_out_bits { 9237 u8 status[0x8]; 9238 u8 reserved_at_8[0x18]; 9239 9240 u8 syndrome[0x20]; 9241 9242 u8 reserved_at_40[0x40]; 9243 9244 struct mlx5_ifc_lagc_bits ctx; 9245 }; 9246 9247 struct mlx5_ifc_query_lag_in_bits { 9248 u8 opcode[0x10]; 9249 u8 reserved_at_10[0x10]; 9250 9251 u8 reserved_at_20[0x10]; 9252 u8 op_mod[0x10]; 9253 9254 u8 reserved_at_40[0x40]; 9255 }; 9256 9257 struct mlx5_ifc_destroy_lag_out_bits { 9258 u8 status[0x8]; 9259 u8 reserved_at_8[0x18]; 9260 9261 u8 syndrome[0x20]; 9262 9263 u8 reserved_at_40[0x40]; 9264 }; 9265 9266 struct mlx5_ifc_destroy_lag_in_bits { 9267 u8 opcode[0x10]; 9268 u8 reserved_at_10[0x10]; 9269 9270 u8 reserved_at_20[0x10]; 9271 u8 op_mod[0x10]; 9272 9273 u8 reserved_at_40[0x40]; 9274 }; 9275 9276 struct mlx5_ifc_create_vport_lag_out_bits { 9277 u8 status[0x8]; 9278 u8 reserved_at_8[0x18]; 9279 9280 u8 syndrome[0x20]; 9281 9282 u8 reserved_at_40[0x40]; 9283 }; 9284 9285 struct mlx5_ifc_create_vport_lag_in_bits { 9286 u8 opcode[0x10]; 9287 u8 reserved_at_10[0x10]; 9288 9289 u8 reserved_at_20[0x10]; 9290 u8 op_mod[0x10]; 9291 9292 u8 reserved_at_40[0x40]; 9293 }; 9294 9295 struct mlx5_ifc_destroy_vport_lag_out_bits { 9296 u8 status[0x8]; 9297 u8 reserved_at_8[0x18]; 9298 9299 u8 syndrome[0x20]; 9300 9301 u8 reserved_at_40[0x40]; 9302 }; 9303 9304 struct mlx5_ifc_destroy_vport_lag_in_bits { 9305 u8 opcode[0x10]; 9306 u8 reserved_at_10[0x10]; 9307 9308 u8 reserved_at_20[0x10]; 9309 u8 op_mod[0x10]; 9310 9311 u8 reserved_at_40[0x40]; 9312 }; 9313 9314 struct mlx5_ifc_alloc_memic_in_bits { 9315 u8 opcode[0x10]; 9316 u8 reserved_at_10[0x10]; 9317 9318 u8 reserved_at_20[0x10]; 9319 u8 op_mod[0x10]; 9320 9321 u8 reserved_at_30[0x20]; 9322 9323 u8 reserved_at_40[0x18]; 9324 u8 log_memic_addr_alignment[0x8]; 9325 9326 u8 range_start_addr[0x40]; 9327 9328 u8 range_size[0x20]; 9329 9330 u8 memic_size[0x20]; 9331 }; 9332 9333 struct mlx5_ifc_alloc_memic_out_bits { 9334 u8 status[0x8]; 9335 u8 reserved_at_8[0x18]; 9336 9337 u8 syndrome[0x20]; 9338 9339 u8 memic_start_addr[0x40]; 9340 }; 9341 9342 struct mlx5_ifc_dealloc_memic_in_bits { 9343 u8 opcode[0x10]; 9344 u8 reserved_at_10[0x10]; 9345 9346 u8 reserved_at_20[0x10]; 9347 u8 op_mod[0x10]; 9348 9349 u8 reserved_at_40[0x40]; 9350 9351 u8 memic_start_addr[0x40]; 9352 9353 u8 memic_size[0x20]; 9354 9355 u8 reserved_at_e0[0x20]; 9356 }; 9357 9358 struct mlx5_ifc_dealloc_memic_out_bits { 9359 u8 status[0x8]; 9360 u8 reserved_at_8[0x18]; 9361 9362 u8 syndrome[0x20]; 9363 9364 u8 reserved_at_40[0x40]; 9365 }; 9366 9367 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9368 u8 opcode[0x10]; 9369 u8 uid[0x10]; 9370 9371 u8 reserved_at_20[0x10]; 9372 u8 obj_type[0x10]; 9373 9374 u8 obj_id[0x20]; 9375 9376 u8 reserved_at_60[0x20]; 9377 }; 9378 9379 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9380 u8 status[0x8]; 9381 u8 reserved_at_8[0x18]; 9382 9383 u8 syndrome[0x20]; 9384 9385 u8 obj_id[0x20]; 9386 9387 u8 reserved_at_60[0x20]; 9388 }; 9389 9390 struct mlx5_ifc_umem_bits { 9391 u8 modify_field_select[0x40]; 9392 9393 u8 reserved_at_40[0x5b]; 9394 u8 log_page_size[0x5]; 9395 9396 u8 page_offset[0x20]; 9397 9398 u8 num_of_mtt[0x40]; 9399 9400 struct mlx5_ifc_mtt_bits mtt[0]; 9401 }; 9402 9403 struct mlx5_ifc_uctx_bits { 9404 u8 modify_field_select[0x40]; 9405 9406 u8 cap[0x20]; 9407 9408 u8 reserved_at_60[0x1a0]; 9409 }; 9410 9411 struct mlx5_ifc_create_umem_in_bits { 9412 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9413 struct mlx5_ifc_umem_bits umem; 9414 }; 9415 9416 struct mlx5_ifc_create_uctx_in_bits { 9417 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9418 struct mlx5_ifc_uctx_bits uctx; 9419 }; 9420 9421 struct mlx5_ifc_mtrc_string_db_param_bits { 9422 u8 string_db_base_address[0x20]; 9423 9424 u8 reserved_at_20[0x8]; 9425 u8 string_db_size[0x18]; 9426 }; 9427 9428 struct mlx5_ifc_mtrc_cap_bits { 9429 u8 trace_owner[0x1]; 9430 u8 trace_to_memory[0x1]; 9431 u8 reserved_at_2[0x4]; 9432 u8 trc_ver[0x2]; 9433 u8 reserved_at_8[0x14]; 9434 u8 num_string_db[0x4]; 9435 9436 u8 first_string_trace[0x8]; 9437 u8 num_string_trace[0x8]; 9438 u8 reserved_at_30[0x28]; 9439 9440 u8 log_max_trace_buffer_size[0x8]; 9441 9442 u8 reserved_at_60[0x20]; 9443 9444 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9445 9446 u8 reserved_at_280[0x180]; 9447 }; 9448 9449 struct mlx5_ifc_mtrc_conf_bits { 9450 u8 reserved_at_0[0x1c]; 9451 u8 trace_mode[0x4]; 9452 u8 reserved_at_20[0x18]; 9453 u8 log_trace_buffer_size[0x8]; 9454 u8 trace_mkey[0x20]; 9455 u8 reserved_at_60[0x3a0]; 9456 }; 9457 9458 struct mlx5_ifc_mtrc_stdb_bits { 9459 u8 string_db_index[0x4]; 9460 u8 reserved_at_4[0x4]; 9461 u8 read_size[0x18]; 9462 u8 start_offset[0x20]; 9463 u8 string_db_data[0]; 9464 }; 9465 9466 struct mlx5_ifc_mtrc_ctrl_bits { 9467 u8 trace_status[0x2]; 9468 u8 reserved_at_2[0x2]; 9469 u8 arm_event[0x1]; 9470 u8 reserved_at_5[0xb]; 9471 u8 modify_field_select[0x10]; 9472 u8 reserved_at_20[0x2b]; 9473 u8 current_timestamp52_32[0x15]; 9474 u8 current_timestamp31_0[0x20]; 9475 u8 reserved_at_80[0x180]; 9476 }; 9477 9478 #endif /* MLX5_IFC_H */ 9479