17701707cSSaeed Mahameed /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 27701707cSSaeed Mahameed /* Copyright (c) 2018 Mellanox Technologies. */ 37701707cSSaeed Mahameed 47701707cSSaeed Mahameed #ifndef MLX5_CORE_EQ_H 57701707cSSaeed Mahameed #define MLX5_CORE_EQ_H 67701707cSSaeed Mahameed 77701707cSSaeed Mahameed #include <linux/mlx5/driver.h> 87701707cSSaeed Mahameed 97701707cSSaeed Mahameed enum { 107701707cSSaeed Mahameed MLX5_EQ_PAGEREQ_IDX = 0, 117701707cSSaeed Mahameed MLX5_EQ_CMD_IDX = 1, 127701707cSSaeed Mahameed MLX5_EQ_ASYNC_IDX = 2, 137701707cSSaeed Mahameed /* reserved to be used by mlx5_core ulps (mlx5e/mlx5_ib) */ 147701707cSSaeed Mahameed MLX5_EQ_PFAULT_IDX = 3, 157701707cSSaeed Mahameed MLX5_EQ_MAX_ASYNC_EQS, 167701707cSSaeed Mahameed /* completion eqs vector indices start here */ 177701707cSSaeed Mahameed MLX5_EQ_VEC_COMP_BASE = MLX5_EQ_MAX_ASYNC_EQS, 187701707cSSaeed Mahameed }; 197701707cSSaeed Mahameed 20d5d284b8SSaeed Mahameed #define MLX5_NUM_CMD_EQE (32) 21d5d284b8SSaeed Mahameed #define MLX5_NUM_ASYNC_EQE (0x1000) 22d5d284b8SSaeed Mahameed #define MLX5_NUM_SPARE_EQE (0x80) 23d5d284b8SSaeed Mahameed 247701707cSSaeed Mahameed struct mlx5_eq; 257701707cSSaeed Mahameed 267701707cSSaeed Mahameed struct mlx5_eq_param { 277701707cSSaeed Mahameed u8 index; 287701707cSSaeed Mahameed int nent; 297701707cSSaeed Mahameed u64 mask; 307701707cSSaeed Mahameed void *context; 317701707cSSaeed Mahameed irq_handler_t handler; 327701707cSSaeed Mahameed }; 337701707cSSaeed Mahameed 347701707cSSaeed Mahameed struct mlx5_eq * 357701707cSSaeed Mahameed mlx5_eq_create_generic(struct mlx5_core_dev *dev, const char *name, 367701707cSSaeed Mahameed struct mlx5_eq_param *param); 377701707cSSaeed Mahameed int 387701707cSSaeed Mahameed mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 397701707cSSaeed Mahameed 407701707cSSaeed Mahameed struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc); 417701707cSSaeed Mahameed void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm); 427701707cSSaeed Mahameed 43d5d284b8SSaeed Mahameed /* The HCA will think the queue has overflowed if we 44d5d284b8SSaeed Mahameed * don't tell it we've been processing events. We 45d5d284b8SSaeed Mahameed * create EQs with MLX5_NUM_SPARE_EQE extra entries, 46d5d284b8SSaeed Mahameed * so we must update our consumer index at 47d5d284b8SSaeed Mahameed * least that often. 48d5d284b8SSaeed Mahameed * 49d5d284b8SSaeed Mahameed * mlx5_eq_update_cc must be called on every EQE @EQ irq handler 50d5d284b8SSaeed Mahameed */ 51d5d284b8SSaeed Mahameed static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc) 52d5d284b8SSaeed Mahameed { 53d5d284b8SSaeed Mahameed if (unlikely(cc >= MLX5_NUM_SPARE_EQE)) { 54d5d284b8SSaeed Mahameed mlx5_eq_update_ci(eq, cc, 0); 55d5d284b8SSaeed Mahameed cc = 0; 56d5d284b8SSaeed Mahameed } 57d5d284b8SSaeed Mahameed return cc; 58d5d284b8SSaeed Mahameed } 59d5d284b8SSaeed Mahameed 607701707cSSaeed Mahameed #endif /* MLX5_CORE_EQ_H */ 61