17701707cSSaeed Mahameed /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 27701707cSSaeed Mahameed /* Copyright (c) 2018 Mellanox Technologies. */ 37701707cSSaeed Mahameed 47701707cSSaeed Mahameed #ifndef MLX5_CORE_EQ_H 57701707cSSaeed Mahameed #define MLX5_CORE_EQ_H 67701707cSSaeed Mahameed 77701707cSSaeed Mahameed enum { 87701707cSSaeed Mahameed MLX5_EQ_PAGEREQ_IDX = 0, 97701707cSSaeed Mahameed MLX5_EQ_CMD_IDX = 1, 107701707cSSaeed Mahameed MLX5_EQ_ASYNC_IDX = 2, 117701707cSSaeed Mahameed /* reserved to be used by mlx5_core ulps (mlx5e/mlx5_ib) */ 127701707cSSaeed Mahameed MLX5_EQ_PFAULT_IDX = 3, 137701707cSSaeed Mahameed MLX5_EQ_MAX_ASYNC_EQS, 147701707cSSaeed Mahameed /* completion eqs vector indices start here */ 157701707cSSaeed Mahameed MLX5_EQ_VEC_COMP_BASE = MLX5_EQ_MAX_ASYNC_EQS, 167701707cSSaeed Mahameed }; 177701707cSSaeed Mahameed 18d5d284b8SSaeed Mahameed #define MLX5_NUM_CMD_EQE (32) 19d5d284b8SSaeed Mahameed #define MLX5_NUM_ASYNC_EQE (0x1000) 20d5d284b8SSaeed Mahameed #define MLX5_NUM_SPARE_EQE (0x80) 21d5d284b8SSaeed Mahameed 227701707cSSaeed Mahameed struct mlx5_eq; 230f597ed4SSaeed Mahameed struct mlx5_core_dev; 247701707cSSaeed Mahameed 257701707cSSaeed Mahameed struct mlx5_eq_param { 267701707cSSaeed Mahameed u8 index; 277701707cSSaeed Mahameed int nent; 287701707cSSaeed Mahameed u64 mask; 297701707cSSaeed Mahameed void *context; 307701707cSSaeed Mahameed irq_handler_t handler; 317701707cSSaeed Mahameed }; 327701707cSSaeed Mahameed 337701707cSSaeed Mahameed struct mlx5_eq * 347701707cSSaeed Mahameed mlx5_eq_create_generic(struct mlx5_core_dev *dev, const char *name, 357701707cSSaeed Mahameed struct mlx5_eq_param *param); 367701707cSSaeed Mahameed int 377701707cSSaeed Mahameed mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 387701707cSSaeed Mahameed 397701707cSSaeed Mahameed struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc); 407701707cSSaeed Mahameed void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm); 417701707cSSaeed Mahameed 42d5d284b8SSaeed Mahameed /* The HCA will think the queue has overflowed if we 43d5d284b8SSaeed Mahameed * don't tell it we've been processing events. We 44d5d284b8SSaeed Mahameed * create EQs with MLX5_NUM_SPARE_EQE extra entries, 45d5d284b8SSaeed Mahameed * so we must update our consumer index at 46d5d284b8SSaeed Mahameed * least that often. 47d5d284b8SSaeed Mahameed * 48d5d284b8SSaeed Mahameed * mlx5_eq_update_cc must be called on every EQE @EQ irq handler 49d5d284b8SSaeed Mahameed */ 50d5d284b8SSaeed Mahameed static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc) 51d5d284b8SSaeed Mahameed { 52d5d284b8SSaeed Mahameed if (unlikely(cc >= MLX5_NUM_SPARE_EQE)) { 53d5d284b8SSaeed Mahameed mlx5_eq_update_ci(eq, cc, 0); 54d5d284b8SSaeed Mahameed cc = 0; 55d5d284b8SSaeed Mahameed } 56d5d284b8SSaeed Mahameed return cc; 57d5d284b8SSaeed Mahameed } 58d5d284b8SSaeed Mahameed 590f597ed4SSaeed Mahameed struct mlx5_nb { 600f597ed4SSaeed Mahameed struct notifier_block nb; 610f597ed4SSaeed Mahameed u8 event_type; 620f597ed4SSaeed Mahameed }; 630f597ed4SSaeed Mahameed 640f597ed4SSaeed Mahameed #define mlx5_nb_cof(ptr, type, member) \ 650f597ed4SSaeed Mahameed (container_of(container_of(ptr, struct mlx5_nb, nb), type, member)) 660f597ed4SSaeed Mahameed 670f597ed4SSaeed Mahameed #define MLX5_NB_INIT(name, handler, event) do { \ 680f597ed4SSaeed Mahameed (name)->nb.notifier_call = handler; \ 690f597ed4SSaeed Mahameed (name)->event_type = MLX5_EVENT_TYPE_##event; \ 700f597ed4SSaeed Mahameed } while (0) 710f597ed4SSaeed Mahameed 727701707cSSaeed Mahameed #endif /* MLX5_CORE_EQ_H */ 73