1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/spinlock_types.h> 40 #include <linux/semaphore.h> 41 #include <linux/slab.h> 42 #include <linux/vmalloc.h> 43 #include <linux/radix-tree.h> 44 45 #include <linux/mlx5/device.h> 46 #include <linux/mlx5/doorbell.h> 47 48 enum { 49 MLX5_BOARD_ID_LEN = 64, 50 MLX5_MAX_NAME_LEN = 16, 51 }; 52 53 enum { 54 /* one minute for the sake of bringup. Generally, commands must always 55 * complete and we may need to increase this timeout value 56 */ 57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, 58 MLX5_CMD_WQ_MAX_NAME = 32, 59 }; 60 61 enum { 62 CMD_OWNER_SW = 0x0, 63 CMD_OWNER_HW = 0x1, 64 CMD_STATUS_SUCCESS = 0, 65 }; 66 67 enum mlx5_sqp_t { 68 MLX5_SQP_SMI = 0, 69 MLX5_SQP_GSI = 1, 70 MLX5_SQP_IEEE_1588 = 2, 71 MLX5_SQP_SNIFFER = 3, 72 MLX5_SQP_SYNC_UMR = 4, 73 }; 74 75 enum { 76 MLX5_MAX_PORTS = 2, 77 }; 78 79 enum { 80 MLX5_EQ_VEC_PAGES = 0, 81 MLX5_EQ_VEC_CMD = 1, 82 MLX5_EQ_VEC_ASYNC = 2, 83 MLX5_EQ_VEC_COMP_BASE, 84 }; 85 86 enum { 87 MLX5_MAX_IRQ_NAME = 32 88 }; 89 90 enum { 91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 92 MLX5_ATOMIC_MODE_CX = 2 << 16, 93 MLX5_ATOMIC_MODE_8B = 3 << 16, 94 MLX5_ATOMIC_MODE_16B = 4 << 16, 95 MLX5_ATOMIC_MODE_32B = 5 << 16, 96 MLX5_ATOMIC_MODE_64B = 6 << 16, 97 MLX5_ATOMIC_MODE_128B = 7 << 16, 98 MLX5_ATOMIC_MODE_256B = 8 << 16, 99 }; 100 101 enum { 102 MLX5_REG_PCAP = 0x5001, 103 MLX5_REG_PMTU = 0x5003, 104 MLX5_REG_PTYS = 0x5004, 105 MLX5_REG_PAOS = 0x5006, 106 MLX5_REG_PFCC = 0x5007, 107 MLX5_REG_PPCNT = 0x5008, 108 MLX5_REG_PMAOS = 0x5012, 109 MLX5_REG_PUDE = 0x5009, 110 MLX5_REG_PMPE = 0x5010, 111 MLX5_REG_PELC = 0x500e, 112 MLX5_REG_PVLC = 0x500f, 113 MLX5_REG_PMLP = 0, /* TBD */ 114 MLX5_REG_NODE_DESC = 0x6001, 115 MLX5_REG_HOST_ENDIANNESS = 0x7004, 116 }; 117 118 enum mlx5_page_fault_resume_flags { 119 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 120 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 121 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 122 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 123 }; 124 125 enum dbg_rsc_type { 126 MLX5_DBG_RSC_QP, 127 MLX5_DBG_RSC_EQ, 128 MLX5_DBG_RSC_CQ, 129 }; 130 131 struct mlx5_field_desc { 132 struct dentry *dent; 133 int i; 134 }; 135 136 struct mlx5_rsc_debug { 137 struct mlx5_core_dev *dev; 138 void *object; 139 enum dbg_rsc_type type; 140 struct dentry *root; 141 struct mlx5_field_desc fields[0]; 142 }; 143 144 enum mlx5_dev_event { 145 MLX5_DEV_EVENT_SYS_ERROR, 146 MLX5_DEV_EVENT_PORT_UP, 147 MLX5_DEV_EVENT_PORT_DOWN, 148 MLX5_DEV_EVENT_PORT_INITIALIZED, 149 MLX5_DEV_EVENT_LID_CHANGE, 150 MLX5_DEV_EVENT_PKEY_CHANGE, 151 MLX5_DEV_EVENT_GUID_CHANGE, 152 MLX5_DEV_EVENT_CLIENT_REREG, 153 }; 154 155 enum mlx5_port_status { 156 MLX5_PORT_UP = 1, 157 MLX5_PORT_DOWN = 2, 158 }; 159 160 struct mlx5_uuar_info { 161 struct mlx5_uar *uars; 162 int num_uars; 163 int num_low_latency_uuars; 164 unsigned long *bitmap; 165 unsigned int *count; 166 struct mlx5_bf *bfs; 167 168 /* 169 * protect uuar allocation data structs 170 */ 171 struct mutex lock; 172 u32 ver; 173 }; 174 175 struct mlx5_bf { 176 void __iomem *reg; 177 void __iomem *regreg; 178 int buf_size; 179 struct mlx5_uar *uar; 180 unsigned long offset; 181 int need_lock; 182 /* protect blue flame buffer selection when needed 183 */ 184 spinlock_t lock; 185 186 /* serialize 64 bit writes when done as two 32 bit accesses 187 */ 188 spinlock_t lock32; 189 int uuarn; 190 }; 191 192 struct mlx5_cmd_first { 193 __be32 data[4]; 194 }; 195 196 struct mlx5_cmd_msg { 197 struct list_head list; 198 struct cache_ent *cache; 199 u32 len; 200 struct mlx5_cmd_first first; 201 struct mlx5_cmd_mailbox *next; 202 }; 203 204 struct mlx5_cmd_debug { 205 struct dentry *dbg_root; 206 struct dentry *dbg_in; 207 struct dentry *dbg_out; 208 struct dentry *dbg_outlen; 209 struct dentry *dbg_status; 210 struct dentry *dbg_run; 211 void *in_msg; 212 void *out_msg; 213 u8 status; 214 u16 inlen; 215 u16 outlen; 216 }; 217 218 struct cache_ent { 219 /* protect block chain allocations 220 */ 221 spinlock_t lock; 222 struct list_head head; 223 }; 224 225 struct cmd_msg_cache { 226 struct cache_ent large; 227 struct cache_ent med; 228 229 }; 230 231 struct mlx5_cmd_stats { 232 u64 sum; 233 u64 n; 234 struct dentry *root; 235 struct dentry *avg; 236 struct dentry *count; 237 /* protect command average calculations */ 238 spinlock_t lock; 239 }; 240 241 struct mlx5_cmd { 242 void *cmd_alloc_buf; 243 dma_addr_t alloc_dma; 244 int alloc_size; 245 void *cmd_buf; 246 dma_addr_t dma; 247 u16 cmdif_rev; 248 u8 log_sz; 249 u8 log_stride; 250 int max_reg_cmds; 251 int events; 252 u32 __iomem *vector; 253 254 /* protect command queue allocations 255 */ 256 spinlock_t alloc_lock; 257 258 /* protect token allocations 259 */ 260 spinlock_t token_lock; 261 u8 token; 262 unsigned long bitmask; 263 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 264 struct workqueue_struct *wq; 265 struct semaphore sem; 266 struct semaphore pages_sem; 267 int mode; 268 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 269 struct pci_pool *pool; 270 struct mlx5_cmd_debug dbg; 271 struct cmd_msg_cache cache; 272 int checksum_disabled; 273 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 274 }; 275 276 struct mlx5_port_caps { 277 int gid_table_len; 278 int pkey_table_len; 279 u8 ext_port_cap; 280 }; 281 282 struct mlx5_cmd_mailbox { 283 void *buf; 284 dma_addr_t dma; 285 struct mlx5_cmd_mailbox *next; 286 }; 287 288 struct mlx5_buf_list { 289 void *buf; 290 dma_addr_t map; 291 }; 292 293 struct mlx5_buf { 294 struct mlx5_buf_list direct; 295 int npages; 296 int size; 297 u8 page_shift; 298 }; 299 300 struct mlx5_eq { 301 struct mlx5_core_dev *dev; 302 __be32 __iomem *doorbell; 303 u32 cons_index; 304 struct mlx5_buf buf; 305 int size; 306 u8 irqn; 307 u8 eqn; 308 int nent; 309 u64 mask; 310 struct list_head list; 311 int index; 312 struct mlx5_rsc_debug *dbg; 313 }; 314 315 struct mlx5_core_psv { 316 u32 psv_idx; 317 struct psv_layout { 318 u32 pd; 319 u16 syndrome; 320 u16 reserved; 321 u16 bg; 322 u16 app_tag; 323 u32 ref_tag; 324 } psv; 325 }; 326 327 struct mlx5_core_sig_ctx { 328 struct mlx5_core_psv psv_memory; 329 struct mlx5_core_psv psv_wire; 330 struct ib_sig_err err_item; 331 bool sig_status_checked; 332 bool sig_err_exists; 333 u32 sigerr_count; 334 }; 335 336 struct mlx5_core_mr { 337 u64 iova; 338 u64 size; 339 u32 key; 340 u32 pd; 341 }; 342 343 enum mlx5_res_type { 344 MLX5_RES_QP, 345 MLX5_RES_SRQ, 346 MLX5_RES_XSRQ, 347 }; 348 349 struct mlx5_core_rsc_common { 350 enum mlx5_res_type res; 351 atomic_t refcount; 352 struct completion free; 353 }; 354 355 struct mlx5_core_srq { 356 struct mlx5_core_rsc_common common; /* must be first */ 357 u32 srqn; 358 int max; 359 int max_gs; 360 int max_avail_gather; 361 int wqe_shift; 362 void (*event) (struct mlx5_core_srq *, enum mlx5_event); 363 364 atomic_t refcount; 365 struct completion free; 366 }; 367 368 struct mlx5_eq_table { 369 void __iomem *update_ci; 370 void __iomem *update_arm_ci; 371 struct list_head comp_eqs_list; 372 struct mlx5_eq pages_eq; 373 struct mlx5_eq async_eq; 374 struct mlx5_eq cmd_eq; 375 int num_comp_vectors; 376 /* protect EQs list 377 */ 378 spinlock_t lock; 379 }; 380 381 struct mlx5_uar { 382 u32 index; 383 struct list_head bf_list; 384 unsigned free_bf_bmap; 385 void __iomem *bf_map; 386 void __iomem *map; 387 }; 388 389 390 struct mlx5_core_health { 391 struct health_buffer __iomem *health; 392 __be32 __iomem *health_counter; 393 struct timer_list timer; 394 u32 prev; 395 int miss_counter; 396 bool sick; 397 struct workqueue_struct *wq; 398 struct work_struct work; 399 }; 400 401 struct mlx5_cq_table { 402 /* protect radix tree 403 */ 404 spinlock_t lock; 405 struct radix_tree_root tree; 406 }; 407 408 struct mlx5_qp_table { 409 /* protect radix tree 410 */ 411 spinlock_t lock; 412 struct radix_tree_root tree; 413 }; 414 415 struct mlx5_srq_table { 416 /* protect radix tree 417 */ 418 spinlock_t lock; 419 struct radix_tree_root tree; 420 }; 421 422 struct mlx5_mr_table { 423 /* protect radix tree 424 */ 425 rwlock_t lock; 426 struct radix_tree_root tree; 427 }; 428 429 struct mlx5_irq_info { 430 cpumask_var_t mask; 431 char name[MLX5_MAX_IRQ_NAME]; 432 }; 433 434 struct mlx5_priv { 435 char name[MLX5_MAX_NAME_LEN]; 436 struct mlx5_eq_table eq_table; 437 struct msix_entry *msix_arr; 438 struct mlx5_irq_info *irq_info; 439 struct mlx5_uuar_info uuari; 440 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 441 442 struct io_mapping *bf_mapping; 443 444 /* pages stuff */ 445 struct workqueue_struct *pg_wq; 446 struct rb_root page_root; 447 int fw_pages; 448 atomic_t reg_pages; 449 struct list_head free_list; 450 451 struct mlx5_core_health health; 452 453 struct mlx5_srq_table srq_table; 454 455 /* start: qp staff */ 456 struct mlx5_qp_table qp_table; 457 struct dentry *qp_debugfs; 458 struct dentry *eq_debugfs; 459 struct dentry *cq_debugfs; 460 struct dentry *cmdif_debugfs; 461 /* end: qp staff */ 462 463 /* start: cq staff */ 464 struct mlx5_cq_table cq_table; 465 /* end: cq staff */ 466 467 /* start: mr staff */ 468 struct mlx5_mr_table mr_table; 469 /* end: mr staff */ 470 471 /* start: alloc staff */ 472 /* protect buffer alocation according to numa node */ 473 struct mutex alloc_mutex; 474 int numa_node; 475 476 struct mutex pgdir_mutex; 477 struct list_head pgdir_list; 478 /* end: alloc staff */ 479 struct dentry *dbg_root; 480 481 /* protect mkey key part */ 482 spinlock_t mkey_lock; 483 u8 mkey_key; 484 485 struct list_head dev_list; 486 struct list_head ctx_list; 487 spinlock_t ctx_lock; 488 }; 489 490 enum mlx5_device_state { 491 MLX5_DEVICE_STATE_UP, 492 MLX5_DEVICE_STATE_INTERNAL_ERROR, 493 }; 494 495 enum mlx5_interface_state { 496 MLX5_INTERFACE_STATE_DOWN, 497 MLX5_INTERFACE_STATE_UP, 498 }; 499 500 enum mlx5_pci_status { 501 MLX5_PCI_STATUS_DISABLED, 502 MLX5_PCI_STATUS_ENABLED, 503 }; 504 505 struct mlx5_core_dev { 506 struct pci_dev *pdev; 507 /* sync pci state */ 508 struct mutex pci_status_mutex; 509 enum mlx5_pci_status pci_status; 510 u8 rev_id; 511 char board_id[MLX5_BOARD_ID_LEN]; 512 struct mlx5_cmd cmd; 513 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 514 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 515 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 516 phys_addr_t iseg_base; 517 struct mlx5_init_seg __iomem *iseg; 518 enum mlx5_device_state state; 519 /* sync interface state */ 520 struct mutex intf_state_mutex; 521 enum mlx5_interface_state interface_state; 522 void (*event) (struct mlx5_core_dev *dev, 523 enum mlx5_dev_event event, 524 unsigned long param); 525 struct mlx5_priv priv; 526 struct mlx5_profile *profile; 527 atomic_t num_qps; 528 u32 issi; 529 }; 530 531 struct mlx5_db { 532 __be32 *db; 533 union { 534 struct mlx5_db_pgdir *pgdir; 535 struct mlx5_ib_user_db_page *user_page; 536 } u; 537 dma_addr_t dma; 538 int index; 539 }; 540 541 enum { 542 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, 543 }; 544 545 enum { 546 MLX5_COMP_EQ_SIZE = 1024, 547 }; 548 549 enum { 550 MLX5_PTYS_IB = 1 << 0, 551 MLX5_PTYS_EN = 1 << 2, 552 }; 553 554 struct mlx5_db_pgdir { 555 struct list_head list; 556 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 557 __be32 *db_page; 558 dma_addr_t db_dma; 559 }; 560 561 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 562 563 struct mlx5_cmd_work_ent { 564 struct mlx5_cmd_msg *in; 565 struct mlx5_cmd_msg *out; 566 void *uout; 567 int uout_size; 568 mlx5_cmd_cbk_t callback; 569 void *context; 570 int idx; 571 struct completion done; 572 struct mlx5_cmd *cmd; 573 struct work_struct work; 574 struct mlx5_cmd_layout *lay; 575 int ret; 576 int page_queue; 577 u8 status; 578 u8 token; 579 u64 ts1; 580 u64 ts2; 581 u16 op; 582 }; 583 584 struct mlx5_pas { 585 u64 pa; 586 u8 log_sz; 587 }; 588 589 enum port_state_policy { 590 MLX5_AAA_000 591 }; 592 593 enum phy_port_state { 594 MLX5_AAA_111 595 }; 596 597 struct mlx5_hca_vport_context { 598 u32 field_select; 599 bool sm_virt_aware; 600 bool has_smi; 601 bool has_raw; 602 enum port_state_policy policy; 603 enum phy_port_state phys_state; 604 enum ib_port_state vport_state; 605 u8 port_physical_state; 606 u64 sys_image_guid; 607 u64 port_guid; 608 u64 node_guid; 609 u32 cap_mask1; 610 u32 cap_mask1_perm; 611 u32 cap_mask2; 612 u32 cap_mask2_perm; 613 u16 lid; 614 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 615 u8 lmc; 616 u8 subnet_timeout; 617 u16 sm_lid; 618 u8 sm_sl; 619 u16 qkey_violation_counter; 620 u16 pkey_violation_counter; 621 bool grh_required; 622 }; 623 624 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 625 { 626 return buf->direct.buf + offset; 627 } 628 629 extern struct workqueue_struct *mlx5_core_wq; 630 631 #define STRUCT_FIELD(header, field) \ 632 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 633 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 634 635 struct ib_field { 636 size_t struct_offset_bytes; 637 size_t struct_size_bytes; 638 int offset_bits; 639 int size_bits; 640 }; 641 642 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 643 { 644 return pci_get_drvdata(pdev); 645 } 646 647 extern struct dentry *mlx5_debugfs_root; 648 649 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 650 { 651 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 652 } 653 654 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 655 { 656 return ioread32be(&dev->iseg->fw_rev) >> 16; 657 } 658 659 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 660 { 661 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 662 } 663 664 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 665 { 666 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 667 } 668 669 static inline void *mlx5_vzalloc(unsigned long size) 670 { 671 void *rtn; 672 673 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 674 if (!rtn) 675 rtn = vzalloc(size); 676 return rtn; 677 } 678 679 static inline u32 mlx5_base_mkey(const u32 key) 680 { 681 return key & 0xffffff00u; 682 } 683 684 int mlx5_cmd_init(struct mlx5_core_dev *dev); 685 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 686 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 687 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 688 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 689 int mlx5_cmd_status_to_err_v2(void *ptr); 690 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 691 enum mlx5_cap_mode cap_mode); 692 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 693 int out_size); 694 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 695 void *out, int out_size, mlx5_cmd_cbk_t callback, 696 void *context); 697 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 698 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 699 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 700 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 701 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 702 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 703 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 704 int mlx5_health_init(struct mlx5_core_dev *dev); 705 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 706 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 707 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 708 struct mlx5_buf *buf, int node); 709 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); 710 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 711 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 712 gfp_t flags, int npages); 713 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 714 struct mlx5_cmd_mailbox *head); 715 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 716 struct mlx5_create_srq_mbox_in *in, int inlen, 717 int is_xrc); 718 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 719 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 720 struct mlx5_query_srq_mbox_out *out); 721 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 722 u16 lwm, int is_srq); 723 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 724 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 725 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 726 struct mlx5_create_mkey_mbox_in *in, int inlen, 727 mlx5_cmd_cbk_t callback, void *context, 728 struct mlx5_create_mkey_mbox_out *out); 729 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 730 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 731 struct mlx5_query_mkey_mbox_out *out, int outlen); 732 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 733 u32 *mkey); 734 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 735 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 736 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 737 u16 opmod, u8 port); 738 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 739 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 740 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 741 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 742 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 743 s32 npages); 744 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 745 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 746 void mlx5_register_debugfs(void); 747 void mlx5_unregister_debugfs(void); 748 int mlx5_eq_init(struct mlx5_core_dev *dev); 749 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 750 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 751 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 752 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 753 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 754 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); 755 #endif 756 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 757 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 758 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); 759 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 760 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 761 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 762 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 763 int mlx5_start_eqs(struct mlx5_core_dev *dev); 764 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 765 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 766 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 767 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 768 769 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 770 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 771 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 772 int size_in, void *data_out, int size_out, 773 u16 reg_num, int arg, int write); 774 775 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 776 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 777 int ptys_size, int proto_mask, u8 local_port); 778 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 779 u32 *proto_cap, int proto_mask); 780 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 781 u32 *proto_admin, int proto_mask); 782 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev, 783 u8 *link_width_oper, u8 local_port); 784 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev, 785 u8 *proto_oper, int proto_mask, 786 u8 local_port); 787 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 788 int proto_mask); 789 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, 790 enum mlx5_port_status status); 791 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 792 enum mlx5_port_status *status); 793 794 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port); 795 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port); 796 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu, 797 u8 port); 798 799 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, 800 u8 *vl_hw_cap, u8 local_port); 801 802 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause); 803 int mlx5_query_port_pause(struct mlx5_core_dev *dev, 804 u32 *rx_pause, u32 *tx_pause); 805 806 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 807 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 808 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 809 struct mlx5_query_eq_mbox_out *out, int outlen); 810 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 811 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 812 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 813 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 814 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 815 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 816 int node); 817 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 818 819 const char *mlx5_command_str(int command); 820 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 821 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 822 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 823 int npsvs, u32 *sig_index); 824 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 825 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 826 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 827 struct mlx5_odp_caps *odp_caps); 828 829 static inline int fw_initializing(struct mlx5_core_dev *dev) 830 { 831 return ioread32be(&dev->iseg->initializing) >> 31; 832 } 833 834 static inline u32 mlx5_mkey_to_idx(u32 mkey) 835 { 836 return mkey >> 8; 837 } 838 839 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 840 { 841 return mkey_idx << 8; 842 } 843 844 static inline u8 mlx5_mkey_variant(u32 mkey) 845 { 846 return mkey & 0xff; 847 } 848 849 enum { 850 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 851 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 852 }; 853 854 enum { 855 MAX_MR_CACHE_ENTRIES = 16, 856 }; 857 858 enum { 859 MLX5_INTERFACE_PROTOCOL_IB = 0, 860 MLX5_INTERFACE_PROTOCOL_ETH = 1, 861 }; 862 863 struct mlx5_interface { 864 void * (*add)(struct mlx5_core_dev *dev); 865 void (*remove)(struct mlx5_core_dev *dev, void *context); 866 void (*event)(struct mlx5_core_dev *dev, void *context, 867 enum mlx5_dev_event event, unsigned long param); 868 void * (*get_dev)(void *context); 869 int protocol; 870 struct list_head list; 871 }; 872 873 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 874 int mlx5_register_interface(struct mlx5_interface *intf); 875 void mlx5_unregister_interface(struct mlx5_interface *intf); 876 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 877 878 struct mlx5_profile { 879 u64 mask; 880 u8 log_max_qp; 881 struct { 882 int size; 883 int limit; 884 } mr_cache[MAX_MR_CACHE_ENTRIES]; 885 }; 886 887 static inline int mlx5_get_gid_table_len(u16 param) 888 { 889 if (param > 4) { 890 pr_warn("gid table length is zero\n"); 891 return 0; 892 } 893 894 return 8 * (1 << param); 895 } 896 897 enum { 898 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 899 }; 900 901 #endif /* MLX5_DRIVER_H */ 902