1 /* 2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 39 #if defined(__LITTLE_ENDIAN) 40 #define MLX5_SET_HOST_ENDIANNESS 0 41 #elif defined(__BIG_ENDIAN) 42 #define MLX5_SET_HOST_ENDIANNESS 0x80 43 #else 44 #error Host endianness not defined 45 #endif 46 47 enum { 48 MLX5_MAX_COMMANDS = 32, 49 MLX5_CMD_DATA_BLOCK_SIZE = 512, 50 MLX5_PCI_CMD_XPORT = 7, 51 MLX5_MKEY_BSF_OCTO_SIZE = 4, 52 MLX5_MAX_PSVS = 4, 53 }; 54 55 enum { 56 MLX5_EXTENDED_UD_AV = 0x80000000, 57 }; 58 59 enum { 60 MLX5_CQ_STATE_ARMED = 9, 61 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 62 MLX5_CQ_STATE_FIRED = 0xa, 63 }; 64 65 enum { 66 MLX5_STAT_RATE_OFFSET = 5, 67 }; 68 69 enum { 70 MLX5_INLINE_SEG = 0x80000000, 71 }; 72 73 enum { 74 MLX5_PERM_LOCAL_READ = 1 << 2, 75 MLX5_PERM_LOCAL_WRITE = 1 << 3, 76 MLX5_PERM_REMOTE_READ = 1 << 4, 77 MLX5_PERM_REMOTE_WRITE = 1 << 5, 78 MLX5_PERM_ATOMIC = 1 << 6, 79 MLX5_PERM_UMR_EN = 1 << 7, 80 }; 81 82 enum { 83 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 84 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 85 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 86 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 87 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 88 }; 89 90 enum { 91 MLX5_ACCESS_MODE_PA = 0, 92 MLX5_ACCESS_MODE_MTT = 1, 93 MLX5_ACCESS_MODE_KLM = 2 94 }; 95 96 enum { 97 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 98 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 99 MLX5_MKEY_BSF_EN = 1 << 30, 100 MLX5_MKEY_LEN64 = 1 << 31, 101 }; 102 103 enum { 104 MLX5_EN_RD = (u64)1, 105 MLX5_EN_WR = (u64)2 106 }; 107 108 enum { 109 MLX5_BF_REGS_PER_PAGE = 4, 110 MLX5_MAX_UAR_PAGES = 1 << 8, 111 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 112 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 113 }; 114 115 enum { 116 MLX5_MKEY_MASK_LEN = 1ull << 0, 117 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 118 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 119 MLX5_MKEY_MASK_PD = 1ull << 7, 120 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 121 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 122 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 123 MLX5_MKEY_MASK_KEY = 1ull << 13, 124 MLX5_MKEY_MASK_QPN = 1ull << 14, 125 MLX5_MKEY_MASK_LR = 1ull << 17, 126 MLX5_MKEY_MASK_LW = 1ull << 18, 127 MLX5_MKEY_MASK_RR = 1ull << 19, 128 MLX5_MKEY_MASK_RW = 1ull << 20, 129 MLX5_MKEY_MASK_A = 1ull << 21, 130 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 131 MLX5_MKEY_MASK_FREE = 1ull << 29, 132 }; 133 134 enum mlx5_event { 135 MLX5_EVENT_TYPE_COMP = 0x0, 136 137 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 138 MLX5_EVENT_TYPE_COMM_EST = 0x02, 139 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 140 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 141 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 142 143 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 144 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 145 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 146 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 147 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 148 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 149 150 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 151 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 152 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 153 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 154 155 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 156 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 157 158 MLX5_EVENT_TYPE_CMD = 0x0a, 159 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 160 }; 161 162 enum { 163 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 164 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 165 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 166 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 167 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 168 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 169 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 170 }; 171 172 enum { 173 MLX5_DEV_CAP_FLAG_RC = 1LL << 0, 174 MLX5_DEV_CAP_FLAG_UC = 1LL << 1, 175 MLX5_DEV_CAP_FLAG_UD = 1LL << 2, 176 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 177 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6, 178 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 179 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 180 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 181 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 182 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 183 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 184 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 185 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 186 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32, 187 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38, 188 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39, 189 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 190 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41, 191 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 192 }; 193 194 enum { 195 MLX5_OPCODE_NOP = 0x00, 196 MLX5_OPCODE_SEND_INVAL = 0x01, 197 MLX5_OPCODE_RDMA_WRITE = 0x08, 198 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 199 MLX5_OPCODE_SEND = 0x0a, 200 MLX5_OPCODE_SEND_IMM = 0x0b, 201 MLX5_OPCODE_RDMA_READ = 0x10, 202 MLX5_OPCODE_ATOMIC_CS = 0x11, 203 MLX5_OPCODE_ATOMIC_FA = 0x12, 204 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 205 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 206 MLX5_OPCODE_BIND_MW = 0x18, 207 MLX5_OPCODE_CONFIG_CMD = 0x1f, 208 209 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 210 MLX5_RECV_OPCODE_SEND = 0x01, 211 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 212 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 213 214 MLX5_CQE_OPCODE_ERROR = 0x1e, 215 MLX5_CQE_OPCODE_RESIZE = 0x16, 216 217 MLX5_OPCODE_SET_PSV = 0x20, 218 MLX5_OPCODE_GET_PSV = 0x21, 219 MLX5_OPCODE_CHECK_PSV = 0x22, 220 MLX5_OPCODE_RGET_PSV = 0x26, 221 MLX5_OPCODE_RCHECK_PSV = 0x27, 222 223 MLX5_OPCODE_UMR = 0x25, 224 225 }; 226 227 enum { 228 MLX5_SET_PORT_RESET_QKEY = 0, 229 MLX5_SET_PORT_GUID0 = 16, 230 MLX5_SET_PORT_NODE_GUID = 17, 231 MLX5_SET_PORT_SYS_GUID = 18, 232 MLX5_SET_PORT_GID_TABLE = 19, 233 MLX5_SET_PORT_PKEY_TABLE = 20, 234 }; 235 236 enum { 237 MLX5_MAX_PAGE_SHIFT = 31 238 }; 239 240 enum { 241 MLX5_ADAPTER_PAGE_SHIFT = 12, 242 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 243 }; 244 245 enum { 246 MLX5_CAP_OFF_DCT = 41, 247 MLX5_CAP_OFF_CMDIF_CSUM = 46, 248 }; 249 250 struct mlx5_inbox_hdr { 251 __be16 opcode; 252 u8 rsvd[4]; 253 __be16 opmod; 254 }; 255 256 struct mlx5_outbox_hdr { 257 u8 status; 258 u8 rsvd[3]; 259 __be32 syndrome; 260 }; 261 262 struct mlx5_cmd_query_adapter_mbox_in { 263 struct mlx5_inbox_hdr hdr; 264 u8 rsvd[8]; 265 }; 266 267 struct mlx5_cmd_query_adapter_mbox_out { 268 struct mlx5_outbox_hdr hdr; 269 u8 rsvd0[24]; 270 u8 intapin; 271 u8 rsvd1[13]; 272 __be16 vsd_vendor_id; 273 u8 vsd[208]; 274 u8 vsd_psid[16]; 275 }; 276 277 struct mlx5_hca_cap { 278 u8 rsvd1[16]; 279 u8 log_max_srq_sz; 280 u8 log_max_qp_sz; 281 u8 rsvd2; 282 u8 log_max_qp; 283 u8 log_max_strq_sz; 284 u8 log_max_srqs; 285 u8 rsvd4[2]; 286 u8 rsvd5; 287 u8 log_max_cq_sz; 288 u8 rsvd6; 289 u8 log_max_cq; 290 u8 log_max_eq_sz; 291 u8 log_max_mkey; 292 u8 rsvd7; 293 u8 log_max_eq; 294 u8 max_indirection; 295 u8 log_max_mrw_sz; 296 u8 log_max_bsf_list_sz; 297 u8 log_max_klm_list_sz; 298 u8 rsvd_8_0; 299 u8 log_max_ra_req_dc; 300 u8 rsvd_8_1; 301 u8 log_max_ra_res_dc; 302 u8 rsvd9; 303 u8 log_max_ra_req_qp; 304 u8 rsvd10; 305 u8 log_max_ra_res_qp; 306 u8 rsvd11[4]; 307 __be16 max_qp_count; 308 __be16 rsvd12; 309 u8 rsvd13; 310 u8 local_ca_ack_delay; 311 u8 rsvd14; 312 u8 num_ports; 313 u8 log_max_msg; 314 u8 rsvd15[3]; 315 __be16 stat_rate_support; 316 u8 rsvd16[2]; 317 __be64 flags; 318 u8 rsvd17; 319 u8 uar_sz; 320 u8 rsvd18; 321 u8 log_pg_sz; 322 __be16 bf_log_bf_reg_size; 323 u8 rsvd19[4]; 324 __be16 max_desc_sz_sq; 325 u8 rsvd20[2]; 326 __be16 max_desc_sz_rq; 327 u8 rsvd21[2]; 328 __be16 max_desc_sz_sq_dc; 329 __be32 max_qp_mcg; 330 u8 rsvd22[3]; 331 u8 log_max_mcg; 332 u8 rsvd23; 333 u8 log_max_pd; 334 u8 rsvd24; 335 u8 log_max_xrcd; 336 u8 rsvd25[42]; 337 __be16 log_uar_page_sz; 338 u8 rsvd26[28]; 339 u8 log_max_atomic_size_qp; 340 u8 rsvd27[2]; 341 u8 log_max_atomic_size_dc; 342 u8 rsvd28[76]; 343 }; 344 345 346 struct mlx5_cmd_query_hca_cap_mbox_in { 347 struct mlx5_inbox_hdr hdr; 348 u8 rsvd[8]; 349 }; 350 351 352 struct mlx5_cmd_query_hca_cap_mbox_out { 353 struct mlx5_outbox_hdr hdr; 354 u8 rsvd0[8]; 355 struct mlx5_hca_cap hca_cap; 356 }; 357 358 359 struct mlx5_cmd_set_hca_cap_mbox_in { 360 struct mlx5_inbox_hdr hdr; 361 u8 rsvd[8]; 362 struct mlx5_hca_cap hca_cap; 363 }; 364 365 366 struct mlx5_cmd_set_hca_cap_mbox_out { 367 struct mlx5_outbox_hdr hdr; 368 u8 rsvd0[8]; 369 }; 370 371 372 struct mlx5_cmd_init_hca_mbox_in { 373 struct mlx5_inbox_hdr hdr; 374 u8 rsvd0[2]; 375 __be16 profile; 376 u8 rsvd1[4]; 377 }; 378 379 struct mlx5_cmd_init_hca_mbox_out { 380 struct mlx5_outbox_hdr hdr; 381 u8 rsvd[8]; 382 }; 383 384 struct mlx5_cmd_teardown_hca_mbox_in { 385 struct mlx5_inbox_hdr hdr; 386 u8 rsvd0[2]; 387 __be16 profile; 388 u8 rsvd1[4]; 389 }; 390 391 struct mlx5_cmd_teardown_hca_mbox_out { 392 struct mlx5_outbox_hdr hdr; 393 u8 rsvd[8]; 394 }; 395 396 struct mlx5_cmd_layout { 397 u8 type; 398 u8 rsvd0[3]; 399 __be32 inlen; 400 __be64 in_ptr; 401 __be32 in[4]; 402 __be32 out[4]; 403 __be64 out_ptr; 404 __be32 outlen; 405 u8 token; 406 u8 sig; 407 u8 rsvd1; 408 u8 status_own; 409 }; 410 411 412 struct health_buffer { 413 __be32 assert_var[5]; 414 __be32 rsvd0[3]; 415 __be32 assert_exit_ptr; 416 __be32 assert_callra; 417 __be32 rsvd1[2]; 418 __be32 fw_ver; 419 __be32 hw_id; 420 __be32 rsvd2; 421 u8 irisc_index; 422 u8 synd; 423 __be16 ext_sync; 424 }; 425 426 struct mlx5_init_seg { 427 __be32 fw_rev; 428 __be32 cmdif_rev_fw_sub; 429 __be32 rsvd0[2]; 430 __be32 cmdq_addr_h; 431 __be32 cmdq_addr_l_sz; 432 __be32 cmd_dbell; 433 __be32 rsvd1[121]; 434 struct health_buffer health; 435 __be32 rsvd2[884]; 436 __be32 health_counter; 437 __be32 rsvd3[1019]; 438 __be64 ieee1588_clk; 439 __be32 ieee1588_clk_type; 440 __be32 clr_intx; 441 }; 442 443 struct mlx5_eqe_comp { 444 __be32 reserved[6]; 445 __be32 cqn; 446 }; 447 448 struct mlx5_eqe_qp_srq { 449 __be32 reserved[6]; 450 __be32 qp_srq_n; 451 }; 452 453 struct mlx5_eqe_cq_err { 454 __be32 cqn; 455 u8 reserved1[7]; 456 u8 syndrome; 457 }; 458 459 struct mlx5_eqe_port_state { 460 u8 reserved0[8]; 461 u8 port; 462 }; 463 464 struct mlx5_eqe_gpio { 465 __be32 reserved0[2]; 466 __be64 gpio_event; 467 }; 468 469 struct mlx5_eqe_congestion { 470 u8 type; 471 u8 rsvd0; 472 u8 congestion_level; 473 }; 474 475 struct mlx5_eqe_stall_vl { 476 u8 rsvd0[3]; 477 u8 port_vl; 478 }; 479 480 struct mlx5_eqe_cmd { 481 __be32 vector; 482 __be32 rsvd[6]; 483 }; 484 485 struct mlx5_eqe_page_req { 486 u8 rsvd0[2]; 487 __be16 func_id; 488 __be32 num_pages; 489 __be32 rsvd1[5]; 490 }; 491 492 union ev_data { 493 __be32 raw[7]; 494 struct mlx5_eqe_cmd cmd; 495 struct mlx5_eqe_comp comp; 496 struct mlx5_eqe_qp_srq qp_srq; 497 struct mlx5_eqe_cq_err cq_err; 498 struct mlx5_eqe_port_state port; 499 struct mlx5_eqe_gpio gpio; 500 struct mlx5_eqe_congestion cong; 501 struct mlx5_eqe_stall_vl stall_vl; 502 struct mlx5_eqe_page_req req_pages; 503 } __packed; 504 505 struct mlx5_eqe { 506 u8 rsvd0; 507 u8 type; 508 u8 rsvd1; 509 u8 sub_type; 510 __be32 rsvd2[7]; 511 union ev_data data; 512 __be16 rsvd3; 513 u8 signature; 514 u8 owner; 515 } __packed; 516 517 struct mlx5_cmd_prot_block { 518 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 519 u8 rsvd0[48]; 520 __be64 next; 521 __be32 block_num; 522 u8 rsvd1; 523 u8 token; 524 u8 ctrl_sig; 525 u8 sig; 526 }; 527 528 struct mlx5_err_cqe { 529 u8 rsvd0[32]; 530 __be32 srqn; 531 u8 rsvd1[18]; 532 u8 vendor_err_synd; 533 u8 syndrome; 534 __be32 s_wqe_opcode_qpn; 535 __be16 wqe_counter; 536 u8 signature; 537 u8 op_own; 538 }; 539 540 struct mlx5_cqe64 { 541 u8 rsvd0[17]; 542 u8 ml_path; 543 u8 rsvd20[4]; 544 __be16 slid; 545 __be32 flags_rqpn; 546 u8 rsvd28[4]; 547 __be32 srqn; 548 __be32 imm_inval_pkey; 549 u8 rsvd40[4]; 550 __be32 byte_cnt; 551 __be64 timestamp; 552 __be32 sop_drop_qpn; 553 __be16 wqe_counter; 554 u8 signature; 555 u8 op_own; 556 }; 557 558 struct mlx5_sig_err_cqe { 559 u8 rsvd0[16]; 560 __be32 expected_trans_sig; 561 __be32 actual_trans_sig; 562 __be32 expected_reftag; 563 __be32 actual_reftag; 564 __be16 syndrome; 565 u8 rsvd22[2]; 566 __be32 mkey; 567 __be64 err_offset; 568 u8 rsvd30[8]; 569 __be32 qpn; 570 u8 rsvd38[2]; 571 u8 signature; 572 u8 op_own; 573 }; 574 575 struct mlx5_wqe_srq_next_seg { 576 u8 rsvd0[2]; 577 __be16 next_wqe_index; 578 u8 signature; 579 u8 rsvd1[11]; 580 }; 581 582 union mlx5_ext_cqe { 583 struct ib_grh grh; 584 u8 inl[64]; 585 }; 586 587 struct mlx5_cqe128 { 588 union mlx5_ext_cqe inl_grh; 589 struct mlx5_cqe64 cqe64; 590 }; 591 592 struct mlx5_srq_ctx { 593 u8 state_log_sz; 594 u8 rsvd0[3]; 595 __be32 flags_xrcd; 596 __be32 pgoff_cqn; 597 u8 rsvd1[4]; 598 u8 log_pg_sz; 599 u8 rsvd2[7]; 600 __be32 pd; 601 __be16 lwm; 602 __be16 wqe_cnt; 603 u8 rsvd3[8]; 604 __be64 db_record; 605 }; 606 607 struct mlx5_create_srq_mbox_in { 608 struct mlx5_inbox_hdr hdr; 609 __be32 input_srqn; 610 u8 rsvd0[4]; 611 struct mlx5_srq_ctx ctx; 612 u8 rsvd1[208]; 613 __be64 pas[0]; 614 }; 615 616 struct mlx5_create_srq_mbox_out { 617 struct mlx5_outbox_hdr hdr; 618 __be32 srqn; 619 u8 rsvd[4]; 620 }; 621 622 struct mlx5_destroy_srq_mbox_in { 623 struct mlx5_inbox_hdr hdr; 624 __be32 srqn; 625 u8 rsvd[4]; 626 }; 627 628 struct mlx5_destroy_srq_mbox_out { 629 struct mlx5_outbox_hdr hdr; 630 u8 rsvd[8]; 631 }; 632 633 struct mlx5_query_srq_mbox_in { 634 struct mlx5_inbox_hdr hdr; 635 __be32 srqn; 636 u8 rsvd0[4]; 637 }; 638 639 struct mlx5_query_srq_mbox_out { 640 struct mlx5_outbox_hdr hdr; 641 u8 rsvd0[8]; 642 struct mlx5_srq_ctx ctx; 643 u8 rsvd1[32]; 644 __be64 pas[0]; 645 }; 646 647 struct mlx5_arm_srq_mbox_in { 648 struct mlx5_inbox_hdr hdr; 649 __be32 srqn; 650 __be16 rsvd; 651 __be16 lwm; 652 }; 653 654 struct mlx5_arm_srq_mbox_out { 655 struct mlx5_outbox_hdr hdr; 656 u8 rsvd[8]; 657 }; 658 659 struct mlx5_cq_context { 660 u8 status; 661 u8 cqe_sz_flags; 662 u8 st; 663 u8 rsvd3; 664 u8 rsvd4[6]; 665 __be16 page_offset; 666 __be32 log_sz_usr_page; 667 __be16 cq_period; 668 __be16 cq_max_count; 669 __be16 rsvd20; 670 __be16 c_eqn; 671 u8 log_pg_sz; 672 u8 rsvd25[7]; 673 __be32 last_notified_index; 674 __be32 solicit_producer_index; 675 __be32 consumer_counter; 676 __be32 producer_counter; 677 u8 rsvd48[8]; 678 __be64 db_record_addr; 679 }; 680 681 struct mlx5_create_cq_mbox_in { 682 struct mlx5_inbox_hdr hdr; 683 __be32 input_cqn; 684 u8 rsvdx[4]; 685 struct mlx5_cq_context ctx; 686 u8 rsvd6[192]; 687 __be64 pas[0]; 688 }; 689 690 struct mlx5_create_cq_mbox_out { 691 struct mlx5_outbox_hdr hdr; 692 __be32 cqn; 693 u8 rsvd0[4]; 694 }; 695 696 struct mlx5_destroy_cq_mbox_in { 697 struct mlx5_inbox_hdr hdr; 698 __be32 cqn; 699 u8 rsvd0[4]; 700 }; 701 702 struct mlx5_destroy_cq_mbox_out { 703 struct mlx5_outbox_hdr hdr; 704 u8 rsvd0[8]; 705 }; 706 707 struct mlx5_query_cq_mbox_in { 708 struct mlx5_inbox_hdr hdr; 709 __be32 cqn; 710 u8 rsvd0[4]; 711 }; 712 713 struct mlx5_query_cq_mbox_out { 714 struct mlx5_outbox_hdr hdr; 715 u8 rsvd0[8]; 716 struct mlx5_cq_context ctx; 717 u8 rsvd6[16]; 718 __be64 pas[0]; 719 }; 720 721 struct mlx5_modify_cq_mbox_in { 722 struct mlx5_inbox_hdr hdr; 723 __be32 cqn; 724 __be32 field_select; 725 struct mlx5_cq_context ctx; 726 u8 rsvd[192]; 727 __be64 pas[0]; 728 }; 729 730 struct mlx5_modify_cq_mbox_out { 731 struct mlx5_outbox_hdr hdr; 732 u8 rsvd[8]; 733 }; 734 735 struct mlx5_enable_hca_mbox_in { 736 struct mlx5_inbox_hdr hdr; 737 u8 rsvd[8]; 738 }; 739 740 struct mlx5_enable_hca_mbox_out { 741 struct mlx5_outbox_hdr hdr; 742 u8 rsvd[8]; 743 }; 744 745 struct mlx5_disable_hca_mbox_in { 746 struct mlx5_inbox_hdr hdr; 747 u8 rsvd[8]; 748 }; 749 750 struct mlx5_disable_hca_mbox_out { 751 struct mlx5_outbox_hdr hdr; 752 u8 rsvd[8]; 753 }; 754 755 struct mlx5_eq_context { 756 u8 status; 757 u8 ec_oi; 758 u8 st; 759 u8 rsvd2[7]; 760 __be16 page_pffset; 761 __be32 log_sz_usr_page; 762 u8 rsvd3[7]; 763 u8 intr; 764 u8 log_page_size; 765 u8 rsvd4[15]; 766 __be32 consumer_counter; 767 __be32 produser_counter; 768 u8 rsvd5[16]; 769 }; 770 771 struct mlx5_create_eq_mbox_in { 772 struct mlx5_inbox_hdr hdr; 773 u8 rsvd0[3]; 774 u8 input_eqn; 775 u8 rsvd1[4]; 776 struct mlx5_eq_context ctx; 777 u8 rsvd2[8]; 778 __be64 events_mask; 779 u8 rsvd3[176]; 780 __be64 pas[0]; 781 }; 782 783 struct mlx5_create_eq_mbox_out { 784 struct mlx5_outbox_hdr hdr; 785 u8 rsvd0[3]; 786 u8 eq_number; 787 u8 rsvd1[4]; 788 }; 789 790 struct mlx5_destroy_eq_mbox_in { 791 struct mlx5_inbox_hdr hdr; 792 u8 rsvd0[3]; 793 u8 eqn; 794 u8 rsvd1[4]; 795 }; 796 797 struct mlx5_destroy_eq_mbox_out { 798 struct mlx5_outbox_hdr hdr; 799 u8 rsvd[8]; 800 }; 801 802 struct mlx5_map_eq_mbox_in { 803 struct mlx5_inbox_hdr hdr; 804 __be64 mask; 805 u8 mu; 806 u8 rsvd0[2]; 807 u8 eqn; 808 u8 rsvd1[24]; 809 }; 810 811 struct mlx5_map_eq_mbox_out { 812 struct mlx5_outbox_hdr hdr; 813 u8 rsvd[8]; 814 }; 815 816 struct mlx5_query_eq_mbox_in { 817 struct mlx5_inbox_hdr hdr; 818 u8 rsvd0[3]; 819 u8 eqn; 820 u8 rsvd1[4]; 821 }; 822 823 struct mlx5_query_eq_mbox_out { 824 struct mlx5_outbox_hdr hdr; 825 u8 rsvd[8]; 826 struct mlx5_eq_context ctx; 827 }; 828 829 struct mlx5_mkey_seg { 830 /* This is a two bit field occupying bits 31-30. 831 * bit 31 is always 0, 832 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 833 */ 834 u8 status; 835 u8 pcie_control; 836 u8 flags; 837 u8 version; 838 __be32 qpn_mkey7_0; 839 u8 rsvd1[4]; 840 __be32 flags_pd; 841 __be64 start_addr; 842 __be64 len; 843 __be32 bsfs_octo_size; 844 u8 rsvd2[16]; 845 __be32 xlt_oct_size; 846 u8 rsvd3[3]; 847 u8 log2_page_size; 848 u8 rsvd4[4]; 849 }; 850 851 struct mlx5_query_special_ctxs_mbox_in { 852 struct mlx5_inbox_hdr hdr; 853 u8 rsvd[8]; 854 }; 855 856 struct mlx5_query_special_ctxs_mbox_out { 857 struct mlx5_outbox_hdr hdr; 858 __be32 dump_fill_mkey; 859 __be32 reserved_lkey; 860 }; 861 862 struct mlx5_create_mkey_mbox_in { 863 struct mlx5_inbox_hdr hdr; 864 __be32 input_mkey_index; 865 u8 rsvd0[4]; 866 struct mlx5_mkey_seg seg; 867 u8 rsvd1[16]; 868 __be32 xlat_oct_act_size; 869 __be32 rsvd2; 870 u8 rsvd3[168]; 871 __be64 pas[0]; 872 }; 873 874 struct mlx5_create_mkey_mbox_out { 875 struct mlx5_outbox_hdr hdr; 876 __be32 mkey; 877 u8 rsvd[4]; 878 }; 879 880 struct mlx5_destroy_mkey_mbox_in { 881 struct mlx5_inbox_hdr hdr; 882 __be32 mkey; 883 u8 rsvd[4]; 884 }; 885 886 struct mlx5_destroy_mkey_mbox_out { 887 struct mlx5_outbox_hdr hdr; 888 u8 rsvd[8]; 889 }; 890 891 struct mlx5_query_mkey_mbox_in { 892 struct mlx5_inbox_hdr hdr; 893 __be32 mkey; 894 }; 895 896 struct mlx5_query_mkey_mbox_out { 897 struct mlx5_outbox_hdr hdr; 898 __be64 pas[0]; 899 }; 900 901 struct mlx5_modify_mkey_mbox_in { 902 struct mlx5_inbox_hdr hdr; 903 __be32 mkey; 904 __be64 pas[0]; 905 }; 906 907 struct mlx5_modify_mkey_mbox_out { 908 struct mlx5_outbox_hdr hdr; 909 u8 rsvd[8]; 910 }; 911 912 struct mlx5_dump_mkey_mbox_in { 913 struct mlx5_inbox_hdr hdr; 914 }; 915 916 struct mlx5_dump_mkey_mbox_out { 917 struct mlx5_outbox_hdr hdr; 918 __be32 mkey; 919 }; 920 921 struct mlx5_mad_ifc_mbox_in { 922 struct mlx5_inbox_hdr hdr; 923 __be16 remote_lid; 924 u8 rsvd0; 925 u8 port; 926 u8 rsvd1[4]; 927 u8 data[256]; 928 }; 929 930 struct mlx5_mad_ifc_mbox_out { 931 struct mlx5_outbox_hdr hdr; 932 u8 rsvd[8]; 933 u8 data[256]; 934 }; 935 936 struct mlx5_access_reg_mbox_in { 937 struct mlx5_inbox_hdr hdr; 938 u8 rsvd0[2]; 939 __be16 register_id; 940 __be32 arg; 941 __be32 data[0]; 942 }; 943 944 struct mlx5_access_reg_mbox_out { 945 struct mlx5_outbox_hdr hdr; 946 u8 rsvd[8]; 947 __be32 data[0]; 948 }; 949 950 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 951 952 enum { 953 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 954 }; 955 956 struct mlx5_allocate_psv_in { 957 struct mlx5_inbox_hdr hdr; 958 __be32 npsv_pd; 959 __be32 rsvd_psv0; 960 }; 961 962 struct mlx5_allocate_psv_out { 963 struct mlx5_outbox_hdr hdr; 964 u8 rsvd[8]; 965 __be32 psv_idx[4]; 966 }; 967 968 struct mlx5_destroy_psv_in { 969 struct mlx5_inbox_hdr hdr; 970 __be32 psv_number; 971 u8 rsvd[4]; 972 }; 973 974 struct mlx5_destroy_psv_out { 975 struct mlx5_outbox_hdr hdr; 976 u8 rsvd[8]; 977 }; 978 979 #endif /* MLX5_DEVICE_H */ 980