1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_QP_H 34 #define MLX4_QP_H 35 36 #include <linux/types.h> 37 #include <linux/if_ether.h> 38 39 #include <linux/mlx4/device.h> 40 41 #define MLX4_INVALID_LKEY 0x100 42 43 enum mlx4_qp_optpar { 44 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 45 MLX4_QP_OPTPAR_RRE = 1 << 1, 46 MLX4_QP_OPTPAR_RAE = 1 << 2, 47 MLX4_QP_OPTPAR_RWE = 1 << 3, 48 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 49 MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 50 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 51 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 52 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 53 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 54 MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 55 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 56 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 57 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 58 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 59 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20, 60 MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21, 61 }; 62 63 enum mlx4_qp_state { 64 MLX4_QP_STATE_RST = 0, 65 MLX4_QP_STATE_INIT = 1, 66 MLX4_QP_STATE_RTR = 2, 67 MLX4_QP_STATE_RTS = 3, 68 MLX4_QP_STATE_SQER = 4, 69 MLX4_QP_STATE_SQD = 5, 70 MLX4_QP_STATE_ERR = 6, 71 MLX4_QP_STATE_SQ_DRAINING = 7, 72 MLX4_QP_NUM_STATE 73 }; 74 75 enum { 76 MLX4_QP_ST_RC = 0x0, 77 MLX4_QP_ST_UC = 0x1, 78 MLX4_QP_ST_RD = 0x2, 79 MLX4_QP_ST_UD = 0x3, 80 MLX4_QP_ST_XRC = 0x6, 81 MLX4_QP_ST_MLX = 0x7 82 }; 83 84 enum { 85 MLX4_QP_PM_MIGRATED = 0x3, 86 MLX4_QP_PM_ARMED = 0x0, 87 MLX4_QP_PM_REARM = 0x1 88 }; 89 90 enum { 91 /* params1 */ 92 MLX4_QP_BIT_SRE = 1 << 15, 93 MLX4_QP_BIT_SWE = 1 << 14, 94 MLX4_QP_BIT_SAE = 1 << 13, 95 /* params2 */ 96 MLX4_QP_BIT_RRE = 1 << 15, 97 MLX4_QP_BIT_RWE = 1 << 14, 98 MLX4_QP_BIT_RAE = 1 << 13, 99 MLX4_QP_BIT_FPP = 1 << 3, 100 MLX4_QP_BIT_RIC = 1 << 4, 101 }; 102 103 enum { 104 MLX4_RSS_HASH_XOR = 0, 105 MLX4_RSS_HASH_TOP = 1, 106 107 MLX4_RSS_UDP_IPV6 = 1 << 0, 108 MLX4_RSS_UDP_IPV4 = 1 << 1, 109 MLX4_RSS_TCP_IPV6 = 1 << 2, 110 MLX4_RSS_IPV6 = 1 << 3, 111 MLX4_RSS_TCP_IPV4 = 1 << 4, 112 MLX4_RSS_IPV4 = 1 << 5, 113 114 MLX4_RSS_BY_OUTER_HEADERS = 0 << 6, 115 MLX4_RSS_BY_INNER_HEADERS = 2 << 6, 116 MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6, 117 118 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 119 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 120 /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 121 MLX4_RSS_QPC_FLAG_OFFSET = 13, 122 }; 123 124 #define MLX4_EN_RSS_KEY_SIZE 40 125 126 struct mlx4_rss_context { 127 __be32 base_qpn; 128 __be32 default_qpn; 129 u16 reserved; 130 u8 hash_fn; 131 u8 flags; 132 __be32 rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)]; 133 __be32 base_qpn_udp; 134 }; 135 136 struct mlx4_qp_path { 137 u8 fl; 138 union { 139 u8 vlan_control; 140 u8 control; 141 }; 142 u8 disable_pkey_check; 143 u8 pkey_index; 144 u8 counter_index; 145 u8 grh_mylmc; 146 __be16 rlid; 147 u8 ackto; 148 u8 mgid_index; 149 u8 static_rate; 150 u8 hop_limit; 151 __be32 tclass_flowlabel; 152 u8 rgid[16]; 153 u8 sched_queue; 154 u8 vlan_index; 155 u8 feup; 156 u8 fvl_rx; 157 u8 reserved4[2]; 158 u8 dmac[ETH_ALEN]; 159 }; 160 161 enum { /* fl */ 162 MLX4_FL_CV = 1 << 6, 163 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2, 164 MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1, 165 MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0, 166 }; 167 168 enum { /* control */ 169 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7, 170 }; 171 172 enum { /* vlan_control */ 173 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, 174 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */ 175 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4, 176 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, 177 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */ 178 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 179 }; 180 181 enum { /* feup */ 182 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ 183 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ 184 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ 185 }; 186 187 enum { /* fvl_rx */ 188 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ 189 }; 190 191 struct mlx4_qp_context { 192 __be32 flags; 193 __be32 pd; 194 u8 mtu_msgmax; 195 u8 rq_size_stride; 196 u8 sq_size_stride; 197 u8 rlkey_roce_mode; 198 __be32 usr_page; 199 __be32 local_qpn; 200 __be32 remote_qpn; 201 struct mlx4_qp_path pri_path; 202 struct mlx4_qp_path alt_path; 203 __be32 params1; 204 u32 reserved1; 205 __be32 next_send_psn; 206 __be32 cqn_send; 207 __be16 roce_entropy; 208 __be16 reserved2[3]; 209 __be32 last_acked_psn; 210 __be32 ssn; 211 __be32 params2; 212 __be32 rnr_nextrecvpsn; 213 __be32 xrcd; 214 __be32 cqn_recv; 215 __be64 db_rec_addr; 216 __be32 qkey; 217 __be32 srqn; 218 __be32 msn; 219 __be16 rq_wqe_counter; 220 __be16 sq_wqe_counter; 221 u32 reserved3; 222 __be16 rate_limit_params; 223 u8 reserved4; 224 u8 qos_vport; 225 __be32 param3; 226 __be32 nummmcpeers_basemkey; 227 u8 log_page_size; 228 u8 reserved5[2]; 229 u8 mtt_base_addr_h; 230 __be32 mtt_base_addr_l; 231 u32 reserved6[10]; 232 }; 233 234 struct mlx4_update_qp_context { 235 __be64 qp_mask; 236 __be64 primary_addr_path_mask; 237 __be64 secondary_addr_path_mask; 238 u64 reserved1; 239 struct mlx4_qp_context qp_context; 240 u64 reserved2[58]; 241 }; 242 243 enum { 244 MLX4_UPD_QP_MASK_PM_STATE = 32, 245 MLX4_UPD_QP_MASK_VSD = 33, 246 MLX4_UPD_QP_MASK_QOS_VPP = 34, 247 MLX4_UPD_QP_MASK_RATE_LIMIT = 35, 248 }; 249 250 enum { 251 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, 252 MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, 253 MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, 254 MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, 255 MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, 256 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, 257 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, 258 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, 259 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, 260 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, 261 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, 262 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, 263 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, 264 MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, 265 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, 266 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, 267 MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, 268 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32, 269 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32, 270 }; 271 272 enum { /* param3 */ 273 MLX4_STRIP_VLAN = 1 << 30 274 }; 275 276 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 277 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 278 279 enum { 280 MLX4_WQE_CTRL_NEC = 1 << 29, 281 MLX4_WQE_CTRL_IIP = 1 << 28, 282 MLX4_WQE_CTRL_ILP = 1 << 27, 283 MLX4_WQE_CTRL_FENCE = 1 << 6, 284 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 285 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 286 MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 287 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 288 MLX4_WQE_CTRL_INS_CVLAN = 1 << 6, 289 MLX4_WQE_CTRL_INS_SVLAN = 1 << 7, 290 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 291 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 292 }; 293 294 union mlx4_wqe_qpn_vlan { 295 struct { 296 __be16 vlan_tag; 297 u8 ins_vlan; 298 u8 fence_size; 299 }; 300 __be32 bf_qpn; 301 }; 302 303 struct mlx4_wqe_ctrl_seg { 304 __be32 owner_opcode; 305 union mlx4_wqe_qpn_vlan qpn_vlan; 306 /* 307 * High 24 bits are SRC remote buffer; low 8 bits are flags: 308 * [7] SO (strong ordering) 309 * [5] TCP/UDP checksum 310 * [4] IP checksum 311 * [3:2] C (generate completion queue entry) 312 * [1] SE (solicited event) 313 * [0] FL (force loopback) 314 */ 315 union { 316 __be32 srcrb_flags; 317 __be16 srcrb_flags16[2]; 318 }; 319 /* 320 * imm is immediate data for send/RDMA write w/ immediate; 321 * also invalidation key for send with invalidate; input 322 * modifier for WQEs on CCQs. 323 */ 324 __be32 imm; 325 }; 326 327 enum { 328 MLX4_WQE_MLX_VL15 = 1 << 17, 329 MLX4_WQE_MLX_SLR = 1 << 16 330 }; 331 332 struct mlx4_wqe_mlx_seg { 333 u8 owner; 334 u8 reserved1[2]; 335 u8 opcode; 336 __be16 sched_prio; 337 u8 reserved2; 338 u8 size; 339 /* 340 * [17] VL15 341 * [16] SLR 342 * [15:12] static rate 343 * [11:8] SL 344 * [4] ICRC 345 * [3:2] C 346 * [0] FL (force loopback) 347 */ 348 __be32 flags; 349 __be16 rlid; 350 u16 reserved3; 351 }; 352 353 struct mlx4_wqe_datagram_seg { 354 __be32 av[8]; 355 __be32 dqpn; 356 __be32 qkey; 357 __be16 vlan; 358 u8 mac[ETH_ALEN]; 359 }; 360 361 struct mlx4_wqe_lso_seg { 362 __be32 mss_hdr_size; 363 __be32 header[0]; 364 }; 365 366 enum mlx4_wqe_bind_seg_flags2 { 367 MLX4_WQE_BIND_ZERO_BASED = (1 << 30), 368 MLX4_WQE_BIND_TYPE_2 = (1 << 31), 369 }; 370 371 struct mlx4_wqe_bind_seg { 372 __be32 flags1; 373 __be32 flags2; 374 __be32 new_rkey; 375 __be32 lkey; 376 __be64 addr; 377 __be64 length; 378 }; 379 380 enum { 381 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 382 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 383 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, 384 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, 385 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 386 }; 387 388 struct mlx4_wqe_fmr_seg { 389 __be32 flags; 390 __be32 mem_key; 391 __be64 buf_list; 392 __be64 start_addr; 393 __be64 reg_len; 394 __be32 offset; 395 __be32 page_size; 396 u32 reserved[2]; 397 }; 398 399 struct mlx4_wqe_fmr_ext_seg { 400 u8 flags; 401 u8 reserved; 402 __be16 app_mask; 403 __be16 wire_app_tag; 404 __be16 mem_app_tag; 405 __be32 wire_ref_tag_base; 406 __be32 mem_ref_tag_base; 407 }; 408 409 struct mlx4_wqe_local_inval_seg { 410 u64 reserved1; 411 __be32 mem_key; 412 u32 reserved2; 413 u64 reserved3[2]; 414 }; 415 416 struct mlx4_wqe_raddr_seg { 417 __be64 raddr; 418 __be32 rkey; 419 u32 reserved; 420 }; 421 422 struct mlx4_wqe_atomic_seg { 423 __be64 swap_add; 424 __be64 compare; 425 }; 426 427 struct mlx4_wqe_masked_atomic_seg { 428 __be64 swap_add; 429 __be64 compare; 430 __be64 swap_add_mask; 431 __be64 compare_mask; 432 }; 433 434 struct mlx4_wqe_data_seg { 435 __be32 byte_count; 436 __be32 lkey; 437 __be64 addr; 438 }; 439 440 enum { 441 MLX4_INLINE_ALIGN = 64, 442 MLX4_INLINE_SEG = 1 << 31, 443 }; 444 445 struct mlx4_wqe_inline_seg { 446 __be32 byte_count; 447 }; 448 449 enum mlx4_update_qp_attr { 450 MLX4_UPDATE_QP_SMAC = 1 << 0, 451 MLX4_UPDATE_QP_VSD = 1 << 1, 452 MLX4_UPDATE_QP_RATE_LIMIT = 1 << 2, 453 MLX4_UPDATE_QP_QOS_VPORT = 1 << 3, 454 MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB = 1 << 4, 455 MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 5) - 1 456 }; 457 458 enum mlx4_update_qp_params_flags { 459 MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB = 1 << 0, 460 MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 1, 461 }; 462 463 struct mlx4_update_qp_params { 464 u8 smac_index; 465 u8 qos_vport; 466 u32 flags; 467 u16 rate_unit; 468 u16 rate_val; 469 }; 470 471 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, 472 enum mlx4_update_qp_attr attr, 473 struct mlx4_update_qp_params *params); 474 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 475 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 476 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 477 int sqd_event, struct mlx4_qp *qp); 478 479 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 480 struct mlx4_qp_context *context); 481 482 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 483 struct mlx4_qp_context *context, 484 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 485 486 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 487 { 488 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 489 } 490 491 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 492 493 static inline u16 folded_qp(u32 q) 494 { 495 u16 res; 496 497 res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) | (q & 0xff00); 498 return res; 499 } 500 501 u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn); 502 503 #endif /* MLX4_QP_H */ 504