1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/refcount.h> 44 45 #include <linux/timecounter.h> 46 47 #define DEFAULT_UAR_PAGE_SHIFT 12 48 49 #define MAX_MSIX 128 50 #define MIN_MSIX_P_PORT 5 51 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 52 (dev_cap).num_ports * MIN_MSIX_P_PORT) 53 54 #define MLX4_MAX_100M_UNITS_VAL 255 /* 55 * work around: can't set values 56 * greater then this value when 57 * using 100 Mbps units. 58 */ 59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 61 #define MLX4_RATELIMIT_DEFAULT 0x00ff 62 63 #define MLX4_ROCE_MAX_GIDS 128 64 #define MLX4_ROCE_PF_GIDS 16 65 66 enum { 67 MLX4_FLAG_MSI_X = 1 << 0, 68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 69 MLX4_FLAG_MASTER = 1 << 2, 70 MLX4_FLAG_SLAVE = 1 << 3, 71 MLX4_FLAG_SRIOV = 1 << 4, 72 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 73 MLX4_FLAG_BONDED = 1 << 7, 74 MLX4_FLAG_SECURE_HOST = 1 << 8, 75 }; 76 77 enum { 78 MLX4_PORT_CAP_IS_SM = 1 << 1, 79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 80 }; 81 82 enum { 83 MLX4_MAX_PORTS = 2, 84 MLX4_MAX_PORT_PKEYS = 128, 85 MLX4_MAX_PORT_GIDS = 128 86 }; 87 88 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 89 * These qkeys must not be allowed for general use. This is a 64k range, 90 * and to test for violation, we use the mask (protect against future chg). 91 */ 92 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 93 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 94 95 enum { 96 MLX4_BOARD_ID_LEN = 64 97 }; 98 99 enum { 100 MLX4_MAX_NUM_PF = 16, 101 MLX4_MAX_NUM_VF = 126, 102 MLX4_MAX_NUM_VF_P_PORT = 64, 103 MLX4_MFUNC_MAX = 128, 104 MLX4_MAX_EQ_NUM = 1024, 105 MLX4_MFUNC_EQ_NUM = 4, 106 MLX4_MFUNC_MAX_EQES = 8, 107 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 108 }; 109 110 /* Driver supports 3 different device methods to manage traffic steering: 111 * -device managed - High level API for ib and eth flow steering. FW is 112 * managing flow steering tables. 113 * - B0 steering mode - Common low level API for ib and (if supported) eth. 114 * - A0 steering mode - Limited low level API for eth. In case of IB, 115 * B0 mode is in use. 116 */ 117 enum { 118 MLX4_STEERING_MODE_A0, 119 MLX4_STEERING_MODE_B0, 120 MLX4_STEERING_MODE_DEVICE_MANAGED 121 }; 122 123 enum { 124 MLX4_STEERING_DMFS_A0_DEFAULT, 125 MLX4_STEERING_DMFS_A0_DYNAMIC, 126 MLX4_STEERING_DMFS_A0_STATIC, 127 MLX4_STEERING_DMFS_A0_DISABLE, 128 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 129 }; 130 131 static inline const char *mlx4_steering_mode_str(int steering_mode) 132 { 133 switch (steering_mode) { 134 case MLX4_STEERING_MODE_A0: 135 return "A0 steering"; 136 137 case MLX4_STEERING_MODE_B0: 138 return "B0 steering"; 139 140 case MLX4_STEERING_MODE_DEVICE_MANAGED: 141 return "Device managed flow steering"; 142 143 default: 144 return "Unrecognize steering mode"; 145 } 146 } 147 148 enum { 149 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 150 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 151 }; 152 153 enum { 154 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 155 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 156 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 157 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 158 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 159 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 160 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 161 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 162 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 163 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 164 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 165 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 166 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 167 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 168 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 169 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 170 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 171 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 172 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 173 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 174 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 175 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 176 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 177 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 178 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 179 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 180 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 181 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 185 }; 186 187 enum { 188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 192 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 193 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 194 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 195 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 196 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 197 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 198 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 199 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 200 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 201 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 202 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 203 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 204 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 205 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 207 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 208 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 209 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 210 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 211 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 212 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 213 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 214 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 215 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 216 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 217 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 218 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 219 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 220 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 221 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, 222 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34, 223 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35, 224 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36, 225 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37, 226 MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38, 227 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39, 228 MLX4_DEV_CAP_FLAG2_SW_CQ_INIT = 1ULL << 40, 229 }; 230 231 enum { 232 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 233 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 234 }; 235 236 enum { 237 MLX4_VF_CAP_FLAG_RESET = 1 << 0 238 }; 239 240 /* bit enums for an 8-bit flags field indicating special use 241 * QPs which require special handling in qp_reserve_range. 242 * Currently, this only includes QPs used by the ETH interface, 243 * where we expect to use blueflame. These QPs must not have 244 * bits 6 and 7 set in their qp number. 245 * 246 * This enum may use only bits 0..7. 247 */ 248 enum { 249 MLX4_RESERVE_A0_QP = 1 << 6, 250 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 251 }; 252 253 enum { 254 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 255 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 256 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 257 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 258 }; 259 260 enum { 261 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 262 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 263 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 264 }; 265 266 267 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 268 269 enum { 270 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 271 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 272 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 273 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 274 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 275 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 276 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, 277 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 278 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 279 }; 280 281 enum { 282 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, 283 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 284 }; 285 286 enum mlx4_event { 287 MLX4_EVENT_TYPE_COMP = 0x00, 288 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 289 MLX4_EVENT_TYPE_COMM_EST = 0x02, 290 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 291 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 292 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 293 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 294 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 295 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 296 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 297 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 298 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 299 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 300 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 301 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 302 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 303 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 304 MLX4_EVENT_TYPE_CMD = 0x0a, 305 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 306 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 307 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 308 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 309 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 310 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 311 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 312 MLX4_EVENT_TYPE_NONE = 0xff, 313 }; 314 315 enum { 316 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 317 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 318 }; 319 320 enum { 321 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 322 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 323 }; 324 325 enum { 326 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 327 }; 328 329 enum slave_port_state { 330 SLAVE_PORT_DOWN = 0, 331 SLAVE_PENDING_UP, 332 SLAVE_PORT_UP, 333 }; 334 335 enum slave_port_gen_event { 336 SLAVE_PORT_GEN_EVENT_DOWN = 0, 337 SLAVE_PORT_GEN_EVENT_UP, 338 SLAVE_PORT_GEN_EVENT_NONE, 339 }; 340 341 enum slave_port_state_event { 342 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 343 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 344 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 345 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 346 }; 347 348 enum { 349 MLX4_PERM_LOCAL_READ = 1 << 10, 350 MLX4_PERM_LOCAL_WRITE = 1 << 11, 351 MLX4_PERM_REMOTE_READ = 1 << 12, 352 MLX4_PERM_REMOTE_WRITE = 1 << 13, 353 MLX4_PERM_ATOMIC = 1 << 14, 354 MLX4_PERM_BIND_MW = 1 << 15, 355 MLX4_PERM_MASK = 0xFC00 356 }; 357 358 enum { 359 MLX4_OPCODE_NOP = 0x00, 360 MLX4_OPCODE_SEND_INVAL = 0x01, 361 MLX4_OPCODE_RDMA_WRITE = 0x08, 362 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 363 MLX4_OPCODE_SEND = 0x0a, 364 MLX4_OPCODE_SEND_IMM = 0x0b, 365 MLX4_OPCODE_LSO = 0x0e, 366 MLX4_OPCODE_RDMA_READ = 0x10, 367 MLX4_OPCODE_ATOMIC_CS = 0x11, 368 MLX4_OPCODE_ATOMIC_FA = 0x12, 369 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 370 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 371 MLX4_OPCODE_BIND_MW = 0x18, 372 MLX4_OPCODE_FMR = 0x19, 373 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 374 MLX4_OPCODE_CONFIG_CMD = 0x1f, 375 376 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 377 MLX4_RECV_OPCODE_SEND = 0x01, 378 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 379 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 380 381 MLX4_CQE_OPCODE_ERROR = 0x1e, 382 MLX4_CQE_OPCODE_RESIZE = 0x16, 383 }; 384 385 enum { 386 MLX4_STAT_RATE_OFFSET = 5 387 }; 388 389 enum mlx4_protocol { 390 MLX4_PROT_IB_IPV6 = 0, 391 MLX4_PROT_ETH, 392 MLX4_PROT_IB_IPV4, 393 MLX4_PROT_FCOE 394 }; 395 396 enum { 397 MLX4_MTT_FLAG_PRESENT = 1 398 }; 399 400 enum mlx4_qp_region { 401 MLX4_QP_REGION_FW = 0, 402 MLX4_QP_REGION_RSS_RAW_ETH, 403 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 404 MLX4_QP_REGION_ETH_ADDR, 405 MLX4_QP_REGION_FC_ADDR, 406 MLX4_QP_REGION_FC_EXCH, 407 MLX4_NUM_QP_REGION 408 }; 409 410 enum mlx4_port_type { 411 MLX4_PORT_TYPE_NONE = 0, 412 MLX4_PORT_TYPE_IB = 1, 413 MLX4_PORT_TYPE_ETH = 2, 414 MLX4_PORT_TYPE_AUTO = 3 415 }; 416 417 enum mlx4_special_vlan_idx { 418 MLX4_NO_VLAN_IDX = 0, 419 MLX4_VLAN_MISS_IDX, 420 MLX4_VLAN_REGULAR 421 }; 422 423 enum mlx4_steer_type { 424 MLX4_MC_STEER = 0, 425 MLX4_UC_STEER, 426 MLX4_NUM_STEERS 427 }; 428 429 enum mlx4_resource_usage { 430 MLX4_RES_USAGE_NONE, 431 MLX4_RES_USAGE_DRIVER, 432 MLX4_RES_USAGE_USER_VERBS, 433 }; 434 435 enum { 436 MLX4_NUM_FEXCH = 64 * 1024, 437 }; 438 439 enum { 440 MLX4_MAX_FAST_REG_PAGES = 511, 441 }; 442 443 enum { 444 /* 445 * Max wqe size for rdma read is 512 bytes, so this 446 * limits our max_sge_rd as the wqe needs to fit: 447 * - ctrl segment (16 bytes) 448 * - rdma segment (16 bytes) 449 * - scatter elements (16 bytes each) 450 */ 451 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 452 }; 453 454 enum { 455 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 456 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 457 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 458 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17, 459 }; 460 461 /* Port mgmt change event handling */ 462 enum { 463 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 464 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 465 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 466 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 467 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 468 }; 469 470 union sl2vl_tbl_to_u64 { 471 u8 sl8[8]; 472 u64 sl64; 473 }; 474 475 enum { 476 MLX4_DEVICE_STATE_UP = 1 << 0, 477 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 478 }; 479 480 enum { 481 MLX4_INTERFACE_STATE_UP = 1 << 0, 482 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 483 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2, 484 }; 485 486 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 487 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 488 489 enum mlx4_module_id { 490 MLX4_MODULE_ID_SFP = 0x3, 491 MLX4_MODULE_ID_QSFP = 0xC, 492 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 493 MLX4_MODULE_ID_QSFP28 = 0x11, 494 }; 495 496 enum { /* rl */ 497 MLX4_QP_RATE_LIMIT_NONE = 0, 498 MLX4_QP_RATE_LIMIT_KBS = 1, 499 MLX4_QP_RATE_LIMIT_MBS = 2, 500 MLX4_QP_RATE_LIMIT_GBS = 3 501 }; 502 503 struct mlx4_rate_limit_caps { 504 u16 num_rates; /* Number of different rates */ 505 u8 min_unit; 506 u16 min_val; 507 u8 max_unit; 508 u16 max_val; 509 }; 510 511 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 512 { 513 return (major << 32) | (minor << 16) | subminor; 514 } 515 516 struct mlx4_phys_caps { 517 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 518 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 519 u32 num_phys_eqs; 520 u32 base_sqpn; 521 u32 base_proxy_sqpn; 522 u32 base_tunnel_sqpn; 523 }; 524 525 struct mlx4_spec_qps { 526 u32 qp0_qkey; 527 u32 qp0_proxy; 528 u32 qp0_tunnel; 529 u32 qp1_proxy; 530 u32 qp1_tunnel; 531 }; 532 533 struct mlx4_caps { 534 u64 fw_ver; 535 u32 function; 536 int num_ports; 537 int vl_cap[MLX4_MAX_PORTS + 1]; 538 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 539 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 540 u64 def_mac[MLX4_MAX_PORTS + 1]; 541 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 542 int gid_table_len[MLX4_MAX_PORTS + 1]; 543 int pkey_table_len[MLX4_MAX_PORTS + 1]; 544 int trans_type[MLX4_MAX_PORTS + 1]; 545 int vendor_oui[MLX4_MAX_PORTS + 1]; 546 int wavelength[MLX4_MAX_PORTS + 1]; 547 u64 trans_code[MLX4_MAX_PORTS + 1]; 548 int local_ca_ack_delay; 549 int num_uars; 550 u32 uar_page_size; 551 int bf_reg_size; 552 int bf_regs_per_page; 553 int max_sq_sg; 554 int max_rq_sg; 555 int num_qps; 556 int max_wqes; 557 int max_sq_desc_sz; 558 int max_rq_desc_sz; 559 int max_qp_init_rdma; 560 int max_qp_dest_rdma; 561 int max_tc_eth; 562 struct mlx4_spec_qps *spec_qps; 563 int num_srqs; 564 int max_srq_wqes; 565 int max_srq_sge; 566 int reserved_srqs; 567 int num_cqs; 568 int max_cqes; 569 int reserved_cqs; 570 int num_sys_eqs; 571 int num_eqs; 572 int reserved_eqs; 573 int num_comp_vectors; 574 int num_mpts; 575 int num_mtts; 576 int fmr_reserved_mtts; 577 int reserved_mtts; 578 int reserved_mrws; 579 int reserved_uars; 580 int num_mgms; 581 int num_amgms; 582 int reserved_mcgs; 583 int num_qp_per_mgm; 584 int steering_mode; 585 int dmfs_high_steer_mode; 586 int fs_log_max_ucast_qp_range_size; 587 int num_pds; 588 int reserved_pds; 589 int max_xrcds; 590 int reserved_xrcds; 591 int mtt_entry_sz; 592 u32 max_msg_sz; 593 u32 page_size_cap; 594 u64 flags; 595 u64 flags2; 596 u32 bmme_flags; 597 u32 reserved_lkey; 598 u16 stat_rate_support; 599 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 600 int max_gso_sz; 601 int max_rss_tbl_sz; 602 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 603 int reserved_qps; 604 int reserved_qps_base[MLX4_NUM_QP_REGION]; 605 int log_num_macs; 606 int log_num_vlans; 607 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 608 u8 supported_type[MLX4_MAX_PORTS + 1]; 609 u8 suggested_type[MLX4_MAX_PORTS + 1]; 610 u8 default_sense[MLX4_MAX_PORTS + 1]; 611 u32 port_mask[MLX4_MAX_PORTS + 1]; 612 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 613 u32 max_counters; 614 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 615 u16 sqp_demux; 616 u32 eqe_size; 617 u32 cqe_size; 618 u8 eqe_factor; 619 u32 userspace_caps; /* userspace must be aware of these */ 620 u32 function_caps; /* VFs must be aware of these */ 621 u16 hca_core_clock; 622 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 623 int tunnel_offload_mode; 624 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 625 u8 phv_bit[MLX4_MAX_PORTS + 1]; 626 u8 alloc_res_qp_mask; 627 u32 dmfs_high_rate_qpn_base; 628 u32 dmfs_high_rate_qpn_range; 629 u32 vf_caps; 630 bool wol_port[MLX4_MAX_PORTS + 1]; 631 struct mlx4_rate_limit_caps rl_caps; 632 u32 health_buffer_addrs; 633 }; 634 635 struct mlx4_buf_list { 636 void *buf; 637 dma_addr_t map; 638 }; 639 640 struct mlx4_buf { 641 struct mlx4_buf_list direct; 642 struct mlx4_buf_list *page_list; 643 int nbufs; 644 int npages; 645 int page_shift; 646 }; 647 648 struct mlx4_mtt { 649 u32 offset; 650 int order; 651 int page_shift; 652 }; 653 654 enum { 655 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 656 }; 657 658 struct mlx4_db_pgdir { 659 struct list_head list; 660 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 661 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 662 unsigned long *bits[2]; 663 __be32 *db_page; 664 dma_addr_t db_dma; 665 }; 666 667 struct mlx4_ib_user_db_page; 668 669 struct mlx4_db { 670 __be32 *db; 671 union { 672 struct mlx4_db_pgdir *pgdir; 673 struct mlx4_ib_user_db_page *user_page; 674 } u; 675 dma_addr_t dma; 676 int index; 677 int order; 678 }; 679 680 struct mlx4_hwq_resources { 681 struct mlx4_db db; 682 struct mlx4_mtt mtt; 683 struct mlx4_buf buf; 684 }; 685 686 struct mlx4_mr { 687 struct mlx4_mtt mtt; 688 u64 iova; 689 u64 size; 690 u32 key; 691 u32 pd; 692 u32 access; 693 int enabled; 694 }; 695 696 enum mlx4_mw_type { 697 MLX4_MW_TYPE_1 = 1, 698 MLX4_MW_TYPE_2 = 2, 699 }; 700 701 struct mlx4_mw { 702 u32 key; 703 u32 pd; 704 enum mlx4_mw_type type; 705 int enabled; 706 }; 707 708 struct mlx4_uar { 709 unsigned long pfn; 710 int index; 711 struct list_head bf_list; 712 unsigned free_bf_bmap; 713 void __iomem *map; 714 void __iomem *bf_map; 715 }; 716 717 struct mlx4_bf { 718 unsigned int offset; 719 int buf_size; 720 struct mlx4_uar *uar; 721 void __iomem *reg; 722 }; 723 724 struct mlx4_cq { 725 void (*comp) (struct mlx4_cq *); 726 void (*event) (struct mlx4_cq *, enum mlx4_event); 727 728 struct mlx4_uar *uar; 729 730 u32 cons_index; 731 732 u16 irq; 733 __be32 *set_ci_db; 734 __be32 *arm_db; 735 int arm_sn; 736 737 int cqn; 738 unsigned vector; 739 740 refcount_t refcount; 741 struct completion free; 742 struct { 743 struct list_head list; 744 void (*comp)(struct mlx4_cq *); 745 void *priv; 746 } tasklet_ctx; 747 int reset_notify_added; 748 struct list_head reset_notify; 749 u8 usage; 750 }; 751 752 struct mlx4_qp { 753 void (*event) (struct mlx4_qp *, enum mlx4_event); 754 755 int qpn; 756 757 refcount_t refcount; 758 struct completion free; 759 u8 usage; 760 }; 761 762 struct mlx4_srq { 763 void (*event) (struct mlx4_srq *, enum mlx4_event); 764 765 int srqn; 766 int max; 767 int max_gs; 768 int wqe_shift; 769 770 refcount_t refcount; 771 struct completion free; 772 }; 773 774 struct mlx4_av { 775 __be32 port_pd; 776 u8 reserved1; 777 u8 g_slid; 778 __be16 dlid; 779 u8 reserved2; 780 u8 gid_index; 781 u8 stat_rate; 782 u8 hop_limit; 783 __be32 sl_tclass_flowlabel; 784 u8 dgid[16]; 785 }; 786 787 struct mlx4_eth_av { 788 __be32 port_pd; 789 u8 reserved1; 790 u8 smac_idx; 791 u16 reserved2; 792 u8 reserved3; 793 u8 gid_index; 794 u8 stat_rate; 795 u8 hop_limit; 796 __be32 sl_tclass_flowlabel; 797 u8 dgid[16]; 798 u8 s_mac[6]; 799 u8 reserved4[2]; 800 __be16 vlan; 801 u8 mac[ETH_ALEN]; 802 }; 803 804 union mlx4_ext_av { 805 struct mlx4_av ib; 806 struct mlx4_eth_av eth; 807 }; 808 809 /* Counters should be saturate once they reach their maximum value */ 810 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 811 if ((value) > U32_MAX) \ 812 counter = cpu_to_be32(U32_MAX); \ 813 else \ 814 counter = cpu_to_be32(value); \ 815 } while (0) 816 817 struct mlx4_counter { 818 u8 reserved1[3]; 819 u8 counter_mode; 820 __be32 num_ifc; 821 u32 reserved2[2]; 822 __be64 rx_frames; 823 __be64 rx_bytes; 824 __be64 tx_frames; 825 __be64 tx_bytes; 826 }; 827 828 struct mlx4_quotas { 829 int qp; 830 int cq; 831 int srq; 832 int mpt; 833 int mtt; 834 int counter; 835 int xrcd; 836 }; 837 838 struct mlx4_vf_dev { 839 u8 min_port; 840 u8 n_ports; 841 }; 842 843 struct mlx4_fw_crdump { 844 bool snapshot_enable; 845 struct devlink_region *region_crspace; 846 struct devlink_region *region_fw_health; 847 }; 848 849 enum mlx4_pci_status { 850 MLX4_PCI_STATUS_DISABLED, 851 MLX4_PCI_STATUS_ENABLED, 852 }; 853 854 struct mlx4_dev_persistent { 855 struct pci_dev *pdev; 856 struct mlx4_dev *dev; 857 int nvfs[MLX4_MAX_PORTS + 1]; 858 int num_vfs; 859 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 860 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 861 struct work_struct catas_work; 862 struct workqueue_struct *catas_wq; 863 struct mutex device_state_mutex; /* protect HW state */ 864 u8 state; 865 struct mutex interface_state_mutex; /* protect SW state */ 866 u8 interface_state; 867 struct mutex pci_status_mutex; /* sync pci state */ 868 enum mlx4_pci_status pci_status; 869 struct mlx4_fw_crdump crdump; 870 }; 871 872 struct mlx4_dev { 873 struct mlx4_dev_persistent *persist; 874 unsigned long flags; 875 unsigned long num_slaves; 876 struct mlx4_caps caps; 877 struct mlx4_phys_caps phys_caps; 878 struct mlx4_quotas quotas; 879 struct radix_tree_root qp_table_tree; 880 u8 rev_id; 881 u8 port_random_macs; 882 char board_id[MLX4_BOARD_ID_LEN]; 883 int numa_node; 884 int oper_log_mgm_entry_size; 885 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 886 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 887 struct mlx4_vf_dev *dev_vfs; 888 u8 uar_page_shift; 889 }; 890 891 struct mlx4_clock_params { 892 u64 offset; 893 u8 bar; 894 u8 size; 895 }; 896 897 struct mlx4_eqe { 898 u8 reserved1; 899 u8 type; 900 u8 reserved2; 901 u8 subtype; 902 union { 903 u32 raw[6]; 904 struct { 905 __be32 cqn; 906 } __packed comp; 907 struct { 908 u16 reserved1; 909 __be16 token; 910 u32 reserved2; 911 u8 reserved3[3]; 912 u8 status; 913 __be64 out_param; 914 } __packed cmd; 915 struct { 916 __be32 qpn; 917 } __packed qp; 918 struct { 919 __be32 srqn; 920 } __packed srq; 921 struct { 922 __be32 cqn; 923 u32 reserved1; 924 u8 reserved2[3]; 925 u8 syndrome; 926 } __packed cq_err; 927 struct { 928 u32 reserved1[2]; 929 __be32 port; 930 } __packed port_change; 931 struct { 932 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 933 u32 reserved; 934 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 935 } __packed comm_channel_arm; 936 struct { 937 u8 port; 938 u8 reserved[3]; 939 __be64 mac; 940 } __packed mac_update; 941 struct { 942 __be32 slave_id; 943 } __packed flr_event; 944 struct { 945 __be16 current_temperature; 946 __be16 warning_threshold; 947 } __packed warming; 948 struct { 949 u8 reserved[3]; 950 u8 port; 951 union { 952 struct { 953 __be16 mstr_sm_lid; 954 __be16 port_lid; 955 __be32 changed_attr; 956 u8 reserved[3]; 957 u8 mstr_sm_sl; 958 __be64 gid_prefix; 959 } __packed port_info; 960 struct { 961 __be32 block_ptr; 962 __be32 tbl_entries_mask; 963 } __packed tbl_change_info; 964 struct { 965 u8 sl2vl_table[8]; 966 } __packed sl2vl_tbl_change_info; 967 } params; 968 } __packed port_mgmt_change; 969 struct { 970 u8 reserved[3]; 971 u8 port; 972 u32 reserved1[5]; 973 } __packed bad_cable; 974 } event; 975 u8 slave_id; 976 u8 reserved3[2]; 977 u8 owner; 978 } __packed; 979 980 struct mlx4_init_port_param { 981 int set_guid0; 982 int set_node_guid; 983 int set_si_guid; 984 u16 mtu; 985 int port_width_cap; 986 u16 vl_cap; 987 u16 max_gid; 988 u16 max_pkey; 989 u64 guid0; 990 u64 node_guid; 991 u64 si_guid; 992 }; 993 994 #define MAD_IFC_DATA_SZ 192 995 /* MAD IFC Mailbox */ 996 struct mlx4_mad_ifc { 997 u8 base_version; 998 u8 mgmt_class; 999 u8 class_version; 1000 u8 method; 1001 __be16 status; 1002 __be16 class_specific; 1003 __be64 tid; 1004 __be16 attr_id; 1005 __be16 resv; 1006 __be32 attr_mod; 1007 __be64 mkey; 1008 __be16 dr_slid; 1009 __be16 dr_dlid; 1010 u8 reserved[28]; 1011 u8 data[MAD_IFC_DATA_SZ]; 1012 } __packed; 1013 1014 #define mlx4_foreach_port(port, dev, type) \ 1015 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1016 if ((type) == (dev)->caps.port_mask[(port)]) 1017 1018 #define mlx4_foreach_ib_transport_port(port, dev) \ 1019 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1020 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 1021 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH)) 1022 1023 #define MLX4_INVALID_SLAVE_ID 0xFF 1024 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 1025 1026 void handle_port_mgmt_change_event(struct work_struct *work); 1027 1028 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 1029 { 1030 return dev->caps.function; 1031 } 1032 1033 static inline int mlx4_is_master(struct mlx4_dev *dev) 1034 { 1035 return dev->flags & MLX4_FLAG_MASTER; 1036 } 1037 1038 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 1039 { 1040 return dev->phys_caps.base_sqpn + 8 + 1041 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1042 } 1043 1044 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1045 { 1046 return (qpn < dev->phys_caps.base_sqpn + 8 + 1047 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1048 qpn >= dev->phys_caps.base_sqpn) || 1049 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1050 } 1051 1052 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1053 { 1054 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1055 1056 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1057 return 1; 1058 1059 return 0; 1060 } 1061 1062 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1063 { 1064 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1065 } 1066 1067 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1068 { 1069 return dev->flags & MLX4_FLAG_SLAVE; 1070 } 1071 1072 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1073 { 1074 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1075 } 1076 1077 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1078 struct mlx4_buf *buf); 1079 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1080 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1081 { 1082 if (buf->nbufs == 1) 1083 return buf->direct.buf + offset; 1084 else 1085 return buf->page_list[offset >> PAGE_SHIFT].buf + 1086 (offset & (PAGE_SIZE - 1)); 1087 } 1088 1089 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1090 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1091 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1092 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1093 1094 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1095 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1096 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1097 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1098 1099 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1100 struct mlx4_mtt *mtt); 1101 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1102 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1103 1104 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1105 int npages, int page_shift, struct mlx4_mr *mr); 1106 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1107 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1108 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1109 struct mlx4_mw *mw); 1110 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1111 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1112 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1113 int start_index, int npages, u64 *page_list); 1114 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1115 struct mlx4_buf *buf); 1116 1117 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 1118 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1119 1120 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1121 int size); 1122 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1123 int size); 1124 1125 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1126 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1127 unsigned int vector, int collapsed, int timestamp_en, 1128 void *buf_addr, bool user_cq); 1129 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1130 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1131 int *base, u8 flags, u8 usage); 1132 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1133 1134 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 1135 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1136 1137 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1138 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1139 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1140 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1141 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1142 1143 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1144 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1145 1146 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1147 int block_mcast_loopback, enum mlx4_protocol prot); 1148 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1149 enum mlx4_protocol prot); 1150 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1151 u8 port, int block_mcast_loopback, 1152 enum mlx4_protocol protocol, u64 *reg_id); 1153 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1154 enum mlx4_protocol protocol, u64 reg_id); 1155 1156 enum { 1157 MLX4_DOMAIN_UVERBS = 0x1000, 1158 MLX4_DOMAIN_ETHTOOL = 0x2000, 1159 MLX4_DOMAIN_RFS = 0x3000, 1160 MLX4_DOMAIN_NIC = 0x5000, 1161 }; 1162 1163 enum mlx4_net_trans_rule_id { 1164 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1165 MLX4_NET_TRANS_RULE_ID_IB, 1166 MLX4_NET_TRANS_RULE_ID_IPV6, 1167 MLX4_NET_TRANS_RULE_ID_IPV4, 1168 MLX4_NET_TRANS_RULE_ID_TCP, 1169 MLX4_NET_TRANS_RULE_ID_UDP, 1170 MLX4_NET_TRANS_RULE_ID_VXLAN, 1171 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1172 }; 1173 1174 extern const u16 __sw_id_hw[]; 1175 1176 static inline int map_hw_to_sw_id(u16 header_id) 1177 { 1178 1179 int i; 1180 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1181 if (header_id == __sw_id_hw[i]) 1182 return i; 1183 } 1184 return -EINVAL; 1185 } 1186 1187 enum mlx4_net_trans_promisc_mode { 1188 MLX4_FS_REGULAR = 1, 1189 MLX4_FS_ALL_DEFAULT, 1190 MLX4_FS_MC_DEFAULT, 1191 MLX4_FS_MIRROR_RX_PORT, 1192 MLX4_FS_MIRROR_SX_PORT, 1193 MLX4_FS_UC_SNIFFER, 1194 MLX4_FS_MC_SNIFFER, 1195 MLX4_FS_MODE_NUM, /* should be last */ 1196 }; 1197 1198 struct mlx4_spec_eth { 1199 u8 dst_mac[ETH_ALEN]; 1200 u8 dst_mac_msk[ETH_ALEN]; 1201 u8 src_mac[ETH_ALEN]; 1202 u8 src_mac_msk[ETH_ALEN]; 1203 u8 ether_type_enable; 1204 __be16 ether_type; 1205 __be16 vlan_id_msk; 1206 __be16 vlan_id; 1207 }; 1208 1209 struct mlx4_spec_tcp_udp { 1210 __be16 dst_port; 1211 __be16 dst_port_msk; 1212 __be16 src_port; 1213 __be16 src_port_msk; 1214 }; 1215 1216 struct mlx4_spec_ipv4 { 1217 __be32 dst_ip; 1218 __be32 dst_ip_msk; 1219 __be32 src_ip; 1220 __be32 src_ip_msk; 1221 }; 1222 1223 struct mlx4_spec_ib { 1224 __be32 l3_qpn; 1225 __be32 qpn_msk; 1226 u8 dst_gid[16]; 1227 u8 dst_gid_msk[16]; 1228 }; 1229 1230 struct mlx4_spec_vxlan { 1231 __be32 vni; 1232 __be32 vni_mask; 1233 1234 }; 1235 1236 struct mlx4_spec_list { 1237 struct list_head list; 1238 enum mlx4_net_trans_rule_id id; 1239 union { 1240 struct mlx4_spec_eth eth; 1241 struct mlx4_spec_ib ib; 1242 struct mlx4_spec_ipv4 ipv4; 1243 struct mlx4_spec_tcp_udp tcp_udp; 1244 struct mlx4_spec_vxlan vxlan; 1245 }; 1246 }; 1247 1248 enum mlx4_net_trans_hw_rule_queue { 1249 MLX4_NET_TRANS_Q_FIFO, 1250 MLX4_NET_TRANS_Q_LIFO, 1251 }; 1252 1253 struct mlx4_net_trans_rule { 1254 struct list_head list; 1255 enum mlx4_net_trans_hw_rule_queue queue_mode; 1256 bool exclusive; 1257 bool allow_loopback; 1258 enum mlx4_net_trans_promisc_mode promisc_mode; 1259 u8 port; 1260 u16 priority; 1261 u32 qpn; 1262 }; 1263 1264 struct mlx4_net_trans_rule_hw_ctrl { 1265 __be16 prio; 1266 u8 type; 1267 u8 flags; 1268 u8 rsvd1; 1269 u8 funcid; 1270 u8 vep; 1271 u8 port; 1272 __be32 qpn; 1273 __be32 rsvd2; 1274 }; 1275 1276 struct mlx4_net_trans_rule_hw_ib { 1277 u8 size; 1278 u8 rsvd1; 1279 __be16 id; 1280 u32 rsvd2; 1281 __be32 l3_qpn; 1282 __be32 qpn_mask; 1283 u8 dst_gid[16]; 1284 u8 dst_gid_msk[16]; 1285 } __packed; 1286 1287 struct mlx4_net_trans_rule_hw_eth { 1288 u8 size; 1289 u8 rsvd; 1290 __be16 id; 1291 u8 rsvd1[6]; 1292 u8 dst_mac[6]; 1293 u16 rsvd2; 1294 u8 dst_mac_msk[6]; 1295 u16 rsvd3; 1296 u8 src_mac[6]; 1297 u16 rsvd4; 1298 u8 src_mac_msk[6]; 1299 u8 rsvd5; 1300 u8 ether_type_enable; 1301 __be16 ether_type; 1302 __be16 vlan_tag_msk; 1303 __be16 vlan_tag; 1304 } __packed; 1305 1306 struct mlx4_net_trans_rule_hw_tcp_udp { 1307 u8 size; 1308 u8 rsvd; 1309 __be16 id; 1310 __be16 rsvd1[3]; 1311 __be16 dst_port; 1312 __be16 rsvd2; 1313 __be16 dst_port_msk; 1314 __be16 rsvd3; 1315 __be16 src_port; 1316 __be16 rsvd4; 1317 __be16 src_port_msk; 1318 } __packed; 1319 1320 struct mlx4_net_trans_rule_hw_ipv4 { 1321 u8 size; 1322 u8 rsvd; 1323 __be16 id; 1324 __be32 rsvd1; 1325 __be32 dst_ip; 1326 __be32 dst_ip_msk; 1327 __be32 src_ip; 1328 __be32 src_ip_msk; 1329 } __packed; 1330 1331 struct mlx4_net_trans_rule_hw_vxlan { 1332 u8 size; 1333 u8 rsvd; 1334 __be16 id; 1335 __be32 rsvd1; 1336 __be32 vni; 1337 __be32 vni_mask; 1338 } __packed; 1339 1340 struct _rule_hw { 1341 union { 1342 struct { 1343 u8 size; 1344 u8 rsvd; 1345 __be16 id; 1346 }; 1347 struct mlx4_net_trans_rule_hw_eth eth; 1348 struct mlx4_net_trans_rule_hw_ib ib; 1349 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1350 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1351 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1352 }; 1353 }; 1354 1355 enum { 1356 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1357 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1358 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1359 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1360 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1361 }; 1362 1363 enum { 1364 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2, 1365 }; 1366 1367 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1368 enum mlx4_net_trans_promisc_mode mode); 1369 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1370 enum mlx4_net_trans_promisc_mode mode); 1371 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1372 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1373 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1374 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1375 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1376 1377 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1378 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1379 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1380 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1381 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1382 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1383 int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac); 1384 int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu); 1385 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1386 u8 promisc); 1387 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1388 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1389 u8 ignore_fcs_value); 1390 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1391 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1392 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1393 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, 1394 bool *vlan_offload_disabled); 1395 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 1396 struct _rule_hw *eth_header); 1397 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1398 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1399 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1400 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1401 1402 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1403 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector); 1404 int mlx4_test_async(struct mlx4_dev *dev); 1405 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, 1406 const u32 offset[], u32 value[], 1407 size_t array_len, u8 port); 1408 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1409 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1410 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1411 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1412 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1413 1414 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1415 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1416 1417 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1418 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1419 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1420 1421 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage); 1422 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1423 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1424 1425 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1426 int port); 1427 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1428 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1429 int mlx4_flow_attach(struct mlx4_dev *dev, 1430 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1431 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1432 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1433 enum mlx4_net_trans_promisc_mode flow_type); 1434 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1435 enum mlx4_net_trans_rule_id id); 1436 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1437 1438 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1439 int port, int qpn, u16 prio, u64 *reg_id); 1440 1441 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1442 int i, int val); 1443 1444 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1445 1446 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1447 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1448 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1449 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1450 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1451 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1452 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1453 1454 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1455 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1456 1457 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1458 int *slave_id); 1459 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1460 u8 *gid); 1461 1462 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1463 u32 max_range_qpn); 1464 1465 u64 mlx4_read_clock(struct mlx4_dev *dev); 1466 1467 struct mlx4_active_ports { 1468 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1469 }; 1470 /* Returns a bitmap of the physical ports which are assigned to slave */ 1471 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1472 1473 /* Returns the physical port that represents the virtual port of the slave, */ 1474 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1475 /* mapping is returned. */ 1476 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1477 1478 struct mlx4_slaves_pport { 1479 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1480 }; 1481 /* Returns a bitmap of all slaves that are assigned to port. */ 1482 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1483 int port); 1484 1485 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1486 /* the ports that are set in crit_ports. */ 1487 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1488 struct mlx4_dev *dev, 1489 const struct mlx4_active_ports *crit_ports); 1490 1491 /* Returns the slave's virtual port that represents the physical port. */ 1492 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1493 1494 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1495 1496 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1497 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1498 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); 1499 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1500 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1501 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1502 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1503 int enable); 1504 1505 struct mlx4_mpt_entry; 1506 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1507 struct mlx4_mpt_entry ***mpt_entry); 1508 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1509 struct mlx4_mpt_entry **mpt_entry); 1510 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1511 u32 pdn); 1512 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1513 struct mlx4_mpt_entry *mpt_entry, 1514 u32 access); 1515 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1516 struct mlx4_mpt_entry **mpt_entry); 1517 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1518 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1519 u64 iova, u64 size, int npages, 1520 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1521 1522 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1523 u16 offset, u16 size, u8 *data); 1524 int mlx4_max_tc(struct mlx4_dev *dev); 1525 1526 /* Returns true if running in low memory profile (kdump kernel) */ 1527 static inline bool mlx4_low_memory_profile(void) 1528 { 1529 return is_kdump_kernel(); 1530 } 1531 1532 /* ACCESS REG commands */ 1533 enum mlx4_access_reg_method { 1534 MLX4_ACCESS_REG_QUERY = 0x1, 1535 MLX4_ACCESS_REG_WRITE = 0x2, 1536 }; 1537 1538 /* ACCESS PTYS Reg command */ 1539 enum mlx4_ptys_proto { 1540 MLX4_PTYS_IB = 1<<0, 1541 MLX4_PTYS_EN = 1<<2, 1542 }; 1543 1544 enum mlx4_ptys_flags { 1545 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5, 1546 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6, 1547 }; 1548 1549 struct mlx4_ptys_reg { 1550 u8 flags; 1551 u8 local_port; 1552 u8 resrvd2; 1553 u8 proto_mask; 1554 __be32 resrvd3[2]; 1555 __be32 eth_proto_cap; 1556 __be16 ib_width_cap; 1557 __be16 ib_speed_cap; 1558 __be32 resrvd4; 1559 __be32 eth_proto_admin; 1560 __be16 ib_width_admin; 1561 __be16 ib_speed_admin; 1562 __be32 resrvd5; 1563 __be32 eth_proto_oper; 1564 __be16 ib_width_oper; 1565 __be16 ib_speed_oper; 1566 __be32 resrvd6; 1567 __be32 eth_proto_lp_adv; 1568 } __packed; 1569 1570 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1571 enum mlx4_access_reg_method method, 1572 struct mlx4_ptys_reg *ptys_reg); 1573 1574 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1575 struct mlx4_clock_params *params); 1576 1577 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) 1578 { 1579 return (index << (PAGE_SHIFT - dev->uar_page_shift)); 1580 } 1581 1582 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) 1583 { 1584 /* The first 128 UARs are used for EQ doorbells */ 1585 return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); 1586 } 1587 #endif /* MLX4_DEVICE_H */ 1588