1 /* 2 * twl4030.h - header for TWL4030 PM and audio CODEC device 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Based on tlv320aic23.c: 7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 25 #ifndef __TWL_H_ 26 #define __TWL_H_ 27 28 #include <linux/types.h> 29 #include <linux/input/matrix_keypad.h> 30 31 /* 32 * Using the twl4030 core we address registers using a pair 33 * { module id, relative register offset } 34 * which that core then maps to the relevant 35 * { i2c slave, absolute register address } 36 * 37 * The module IDs are meaningful only to the twl4030 core code, 38 * which uses them as array indices to look up the first register 39 * address each module uses within a given i2c slave. 40 */ 41 42 /* Module IDs for similar functionalities found in twl4030/twl6030 */ 43 enum twl_module_ids { 44 TWL_MODULE_USB, 45 TWL_MODULE_PIH, 46 TWL_MODULE_MAIN_CHARGE, 47 TWL_MODULE_PM_MASTER, 48 TWL_MODULE_PM_RECEIVER, 49 50 TWL_MODULE_RTC, 51 TWL_MODULE_PWM, 52 TWL_MODULE_LED, 53 TWL_MODULE_SECURED_REG, 54 55 TWL_MODULE_LAST, 56 }; 57 58 /* Modules only available in twl4030 series */ 59 enum twl4030_module_ids { 60 TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST, 61 TWL4030_MODULE_GPIO, 62 TWL4030_MODULE_INTBR, 63 TWL4030_MODULE_TEST, 64 TWL4030_MODULE_KEYPAD, 65 66 TWL4030_MODULE_MADC, 67 TWL4030_MODULE_INTERRUPTS, 68 TWL4030_MODULE_PRECHARGE, 69 TWL4030_MODULE_BACKUP, 70 TWL4030_MODULE_INT, 71 72 TWL5031_MODULE_ACCESSORY, 73 TWL5031_MODULE_INTERRUPTS, 74 75 TWL4030_MODULE_LAST, 76 }; 77 78 /* Modules only available in twl6030 series */ 79 enum twl6030_module_ids { 80 TWL6030_MODULE_ID0 = TWL_MODULE_LAST, 81 TWL6030_MODULE_ID1, 82 TWL6030_MODULE_ID2, 83 TWL6030_MODULE_GPADC, 84 TWL6030_MODULE_GASGAUGE, 85 86 TWL6030_MODULE_LAST, 87 }; 88 89 /* Until the clients has been converted to use TWL_MODULE_LED */ 90 #define TWL4030_MODULE_LED TWL_MODULE_LED 91 92 #define GPIO_INTR_OFFSET 0 93 #define KEYPAD_INTR_OFFSET 1 94 #define BCI_INTR_OFFSET 2 95 #define MADC_INTR_OFFSET 3 96 #define USB_INTR_OFFSET 4 97 #define CHARGERFAULT_INTR_OFFSET 5 98 #define BCI_PRES_INTR_OFFSET 9 99 #define USB_PRES_INTR_OFFSET 10 100 #define RTC_INTR_OFFSET 11 101 102 /* 103 * Offset from TWL6030_IRQ_BASE / pdata->irq_base 104 */ 105 #define PWR_INTR_OFFSET 0 106 #define HOTDIE_INTR_OFFSET 12 107 #define SMPSLDO_INTR_OFFSET 13 108 #define BATDETECT_INTR_OFFSET 14 109 #define SIMDETECT_INTR_OFFSET 15 110 #define MMCDETECT_INTR_OFFSET 16 111 #define GASGAUGE_INTR_OFFSET 17 112 #define USBOTG_INTR_OFFSET 4 113 #define CHARGER_INTR_OFFSET 2 114 #define RSV_INTR_OFFSET 0 115 116 /* INT register offsets */ 117 #define REG_INT_STS_A 0x00 118 #define REG_INT_STS_B 0x01 119 #define REG_INT_STS_C 0x02 120 121 #define REG_INT_MSK_LINE_A 0x03 122 #define REG_INT_MSK_LINE_B 0x04 123 #define REG_INT_MSK_LINE_C 0x05 124 125 #define REG_INT_MSK_STS_A 0x06 126 #define REG_INT_MSK_STS_B 0x07 127 #define REG_INT_MSK_STS_C 0x08 128 129 /* MASK INT REG GROUP A */ 130 #define TWL6030_PWR_INT_MASK 0x07 131 #define TWL6030_RTC_INT_MASK 0x18 132 #define TWL6030_HOTDIE_INT_MASK 0x20 133 #define TWL6030_SMPSLDOA_INT_MASK 0xC0 134 135 /* MASK INT REG GROUP B */ 136 #define TWL6030_SMPSLDOB_INT_MASK 0x01 137 #define TWL6030_BATDETECT_INT_MASK 0x02 138 #define TWL6030_SIMDETECT_INT_MASK 0x04 139 #define TWL6030_MMCDETECT_INT_MASK 0x08 140 #define TWL6030_GPADC_INT_MASK 0x60 141 #define TWL6030_GASGAUGE_INT_MASK 0x80 142 143 /* MASK INT REG GROUP C */ 144 #define TWL6030_USBOTG_INT_MASK 0x0F 145 #define TWL6030_CHARGER_CTRL_INT_MASK 0x10 146 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60 147 148 #define TWL6030_MMCCTRL 0xEE 149 #define VMMC_AUTO_OFF (0x1 << 3) 150 #define SW_FC (0x1 << 2) 151 #define STS_MMC 0x1 152 153 #define TWL6030_CFG_INPUT_PUPD3 0xF2 154 #define MMC_PU (0x1 << 3) 155 #define MMC_PD (0x1 << 2) 156 157 #define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF) 158 #define TWL_SIL_REV(rev) ((rev) >> 24) 159 #define TWL_SIL_5030 0x09002F 160 #define TWL5030_REV_1_0 0x00 161 #define TWL5030_REV_1_1 0x10 162 #define TWL5030_REV_1_2 0x30 163 164 #define TWL4030_CLASS_ID 0x4030 165 #define TWL6030_CLASS_ID 0x6030 166 unsigned int twl_rev(void); 167 #define GET_TWL_REV (twl_rev()) 168 #define TWL_CLASS_IS(class, id) \ 169 static inline int twl_class_is_ ##class(void) \ 170 { \ 171 return ((id) == (GET_TWL_REV)) ? 1 : 0; \ 172 } 173 174 TWL_CLASS_IS(4030, TWL4030_CLASS_ID) 175 TWL_CLASS_IS(6030, TWL6030_CLASS_ID) 176 177 /* Set the regcache bypass for the regmap associated with the nodule */ 178 int twl_set_regcache_bypass(u8 mod_no, bool enable); 179 180 /* 181 * Read and write several 8-bit registers at once. 182 */ 183 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 184 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 185 186 /* 187 * Read and write single 8-bit registers 188 */ 189 static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { 190 return twl_i2c_write(mod_no, &val, reg, 1); 191 } 192 193 static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { 194 return twl_i2c_read(mod_no, val, reg, 1); 195 } 196 197 static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { 198 val = cpu_to_le16(val); 199 return twl_i2c_write(mod_no, (u8*) &val, reg, 2); 200 } 201 202 static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { 203 int ret; 204 ret = twl_i2c_read(mod_no, (u8*) val, reg, 2); 205 *val = le16_to_cpu(*val); 206 return ret; 207 } 208 209 int twl_get_type(void); 210 int twl_get_version(void); 211 int twl_get_hfclk_rate(void); 212 213 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); 214 int twl6030_interrupt_mask(u8 bit_mask, u8 offset); 215 216 /* Card detect Configuration for MMC1 Controller on OMAP4 */ 217 #ifdef CONFIG_TWL4030_CORE 218 int twl6030_mmc_card_detect_config(void); 219 #else 220 static inline int twl6030_mmc_card_detect_config(void) 221 { 222 pr_debug("twl6030_mmc_card_detect_config not supported\n"); 223 return 0; 224 } 225 #endif 226 227 /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ 228 #ifdef CONFIG_TWL4030_CORE 229 int twl6030_mmc_card_detect(struct device *dev, int slot); 230 #else 231 static inline int twl6030_mmc_card_detect(struct device *dev, int slot) 232 { 233 pr_debug("Call back twl6030_mmc_card_detect not supported\n"); 234 return -EIO; 235 } 236 #endif 237 /*----------------------------------------------------------------------*/ 238 239 /* 240 * NOTE: at up to 1024 registers, this is a big chip. 241 * 242 * Avoid putting register declarations in this file, instead of into 243 * a driver-private file, unless some of the registers in a block 244 * need to be shared with other drivers. One example is blocks that 245 * have Secondary IRQ Handler (SIH) registers. 246 */ 247 248 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) 249 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) 250 #define TWL4030_SIH_CTRL_COR_MASK BIT(2) 251 252 /*----------------------------------------------------------------------*/ 253 254 /* 255 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) 256 */ 257 258 #define REG_GPIODATAIN1 0x0 259 #define REG_GPIODATAIN2 0x1 260 #define REG_GPIODATAIN3 0x2 261 #define REG_GPIODATADIR1 0x3 262 #define REG_GPIODATADIR2 0x4 263 #define REG_GPIODATADIR3 0x5 264 #define REG_GPIODATAOUT1 0x6 265 #define REG_GPIODATAOUT2 0x7 266 #define REG_GPIODATAOUT3 0x8 267 #define REG_CLEARGPIODATAOUT1 0x9 268 #define REG_CLEARGPIODATAOUT2 0xA 269 #define REG_CLEARGPIODATAOUT3 0xB 270 #define REG_SETGPIODATAOUT1 0xC 271 #define REG_SETGPIODATAOUT2 0xD 272 #define REG_SETGPIODATAOUT3 0xE 273 #define REG_GPIO_DEBEN1 0xF 274 #define REG_GPIO_DEBEN2 0x10 275 #define REG_GPIO_DEBEN3 0x11 276 #define REG_GPIO_CTRL 0x12 277 #define REG_GPIOPUPDCTR1 0x13 278 #define REG_GPIOPUPDCTR2 0x14 279 #define REG_GPIOPUPDCTR3 0x15 280 #define REG_GPIOPUPDCTR4 0x16 281 #define REG_GPIOPUPDCTR5 0x17 282 #define REG_GPIO_ISR1A 0x19 283 #define REG_GPIO_ISR2A 0x1A 284 #define REG_GPIO_ISR3A 0x1B 285 #define REG_GPIO_IMR1A 0x1C 286 #define REG_GPIO_IMR2A 0x1D 287 #define REG_GPIO_IMR3A 0x1E 288 #define REG_GPIO_ISR1B 0x1F 289 #define REG_GPIO_ISR2B 0x20 290 #define REG_GPIO_ISR3B 0x21 291 #define REG_GPIO_IMR1B 0x22 292 #define REG_GPIO_IMR2B 0x23 293 #define REG_GPIO_IMR3B 0x24 294 #define REG_GPIO_EDR1 0x28 295 #define REG_GPIO_EDR2 0x29 296 #define REG_GPIO_EDR3 0x2A 297 #define REG_GPIO_EDR4 0x2B 298 #define REG_GPIO_EDR5 0x2C 299 #define REG_GPIO_SIH_CTRL 0x2D 300 301 /* Up to 18 signals are available as GPIOs, when their 302 * pins are not assigned to another use (such as ULPI/USB). 303 */ 304 #define TWL4030_GPIO_MAX 18 305 306 /*----------------------------------------------------------------------*/ 307 308 /*Interface Bit Register (INTBR) offsets 309 *(Use TWL_4030_MODULE_INTBR) 310 */ 311 312 #define REG_IDCODE_7_0 0x00 313 #define REG_IDCODE_15_8 0x01 314 #define REG_IDCODE_16_23 0x02 315 #define REG_IDCODE_31_24 0x03 316 #define REG_GPPUPDCTR1 0x0F 317 #define REG_UNLOCK_TEST_REG 0x12 318 319 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ 320 321 #define I2C_SCL_CTRL_PU BIT(0) 322 #define I2C_SDA_CTRL_PU BIT(2) 323 #define SR_I2C_SCL_CTRL_PU BIT(4) 324 #define SR_I2C_SDA_CTRL_PU BIT(6) 325 326 #define TWL_EEPROM_R_UNLOCK 0x49 327 328 /*----------------------------------------------------------------------*/ 329 330 /* 331 * Keypad register offsets (use TWL4030_MODULE_KEYPAD) 332 * ... SIH/interrupt only 333 */ 334 335 #define TWL4030_KEYPAD_KEYP_ISR1 0x11 336 #define TWL4030_KEYPAD_KEYP_IMR1 0x12 337 #define TWL4030_KEYPAD_KEYP_ISR2 0x13 338 #define TWL4030_KEYPAD_KEYP_IMR2 0x14 339 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */ 340 #define TWL4030_KEYPAD_KEYP_EDR 0x16 341 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 342 343 /*----------------------------------------------------------------------*/ 344 345 /* 346 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) 347 * ... SIH/interrupt only 348 */ 349 350 #define TWL4030_MADC_ISR1 0x61 351 #define TWL4030_MADC_IMR1 0x62 352 #define TWL4030_MADC_ISR2 0x63 353 #define TWL4030_MADC_IMR2 0x64 354 #define TWL4030_MADC_SIR 0x65 /* test register */ 355 #define TWL4030_MADC_EDR 0x66 356 #define TWL4030_MADC_SIH_CTRL 0x67 357 358 /*----------------------------------------------------------------------*/ 359 360 /* 361 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) 362 */ 363 364 #define TWL4030_INTERRUPTS_BCIISR1A 0x0 365 #define TWL4030_INTERRUPTS_BCIISR2A 0x1 366 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2 367 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3 368 #define TWL4030_INTERRUPTS_BCIISR1B 0x4 369 #define TWL4030_INTERRUPTS_BCIISR2B 0x5 370 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6 371 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7 372 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */ 373 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */ 374 #define TWL4030_INTERRUPTS_BCIEDR1 0xa 375 #define TWL4030_INTERRUPTS_BCIEDR2 0xb 376 #define TWL4030_INTERRUPTS_BCIEDR3 0xc 377 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd 378 379 /*----------------------------------------------------------------------*/ 380 381 /* 382 * Power Interrupt block register offsets (use TWL4030_MODULE_INT) 383 */ 384 385 #define TWL4030_INT_PWR_ISR1 0x0 386 #define TWL4030_INT_PWR_IMR1 0x1 387 #define TWL4030_INT_PWR_ISR2 0x2 388 #define TWL4030_INT_PWR_IMR2 0x3 389 #define TWL4030_INT_PWR_SIR 0x4 /* test register */ 390 #define TWL4030_INT_PWR_EDR1 0x5 391 #define TWL4030_INT_PWR_EDR2 0x6 392 #define TWL4030_INT_PWR_SIH_CTRL 0x7 393 394 /*----------------------------------------------------------------------*/ 395 396 /* 397 * Accessory Interrupts 398 */ 399 #define TWL5031_ACIIMR_LSB 0x05 400 #define TWL5031_ACIIMR_MSB 0x06 401 #define TWL5031_ACIIDR_LSB 0x07 402 #define TWL5031_ACIIDR_MSB 0x08 403 #define TWL5031_ACCISR1 0x0F 404 #define TWL5031_ACCIMR1 0x10 405 #define TWL5031_ACCISR2 0x11 406 #define TWL5031_ACCIMR2 0x12 407 #define TWL5031_ACCSIR 0x13 408 #define TWL5031_ACCEDR1 0x14 409 #define TWL5031_ACCSIHCTRL 0x15 410 411 /*----------------------------------------------------------------------*/ 412 413 /* 414 * Battery Charger Controller 415 */ 416 417 #define TWL5031_INTERRUPTS_BCIISR1 0x0 418 #define TWL5031_INTERRUPTS_BCIIMR1 0x1 419 #define TWL5031_INTERRUPTS_BCIISR2 0x2 420 #define TWL5031_INTERRUPTS_BCIIMR2 0x3 421 #define TWL5031_INTERRUPTS_BCISIR 0x4 422 #define TWL5031_INTERRUPTS_BCIEDR1 0x5 423 #define TWL5031_INTERRUPTS_BCIEDR2 0x6 424 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 425 426 /*----------------------------------------------------------------------*/ 427 428 /* 429 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) 430 */ 431 432 #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00 433 #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01 434 #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02 435 #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03 436 #define TWL4030_PM_MASTER_STS_BOOT 0x04 437 #define TWL4030_PM_MASTER_CFG_BOOT 0x05 438 #define TWL4030_PM_MASTER_SHUNDAN 0x06 439 #define TWL4030_PM_MASTER_BOOT_BCI 0x07 440 #define TWL4030_PM_MASTER_CFG_PWRANA1 0x08 441 #define TWL4030_PM_MASTER_CFG_PWRANA2 0x09 442 #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b 443 #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c 444 #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d 445 #define TWL4030_PM_MASTER_PROTECT_KEY 0x0e 446 #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f 447 #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10 448 #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11 449 #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12 450 #define TWL4030_PM_MASTER_STS_P123_STATE 0x13 451 #define TWL4030_PM_MASTER_PB_CFG 0x14 452 #define TWL4030_PM_MASTER_PB_WORD_MSB 0x15 453 #define TWL4030_PM_MASTER_PB_WORD_LSB 0x16 454 #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c 455 #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d 456 #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e 457 #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f 458 #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20 459 #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21 460 #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22 461 #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23 462 #define TWL4030_PM_MASTER_MEMORY_DATA 0x24 463 464 #define TWL4030_PM_MASTER_KEY_CFG1 0xc0 465 #define TWL4030_PM_MASTER_KEY_CFG2 0x0c 466 467 #define TWL4030_PM_MASTER_KEY_TST1 0xe0 468 #define TWL4030_PM_MASTER_KEY_TST2 0x0e 469 470 #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 471 472 /*----------------------------------------------------------------------*/ 473 474 /* Power bus message definitions */ 475 476 /* The TWL4030/5030 splits its power-management resources (the various 477 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and 478 * P3. These groups can then be configured to transition between sleep, wait-on 479 * and active states by sending messages to the power bus. See Section 5.4.2 480 * Power Resources of TWL4030 TRM 481 */ 482 483 /* Processor groups */ 484 #define DEV_GRP_NULL 0x0 485 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ 486 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */ 487 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ 488 489 /* Resource groups */ 490 #define RES_GRP_RES 0x0 /* Reserved */ 491 #define RES_GRP_PP 0x1 /* Power providers */ 492 #define RES_GRP_RC 0x2 /* Reset and control */ 493 #define RES_GRP_PP_RC 0x3 494 #define RES_GRP_PR 0x4 /* Power references */ 495 #define RES_GRP_PP_PR 0x5 496 #define RES_GRP_RC_PR 0x6 497 #define RES_GRP_ALL 0x7 /* All resource groups */ 498 499 #define RES_TYPE2_R0 0x0 500 #define RES_TYPE2_R1 0x1 501 #define RES_TYPE2_R2 0x2 502 503 #define RES_TYPE_R0 0x0 504 #define RES_TYPE_ALL 0x7 505 506 /* Resource states */ 507 #define RES_STATE_WRST 0xF 508 #define RES_STATE_ACTIVE 0xE 509 #define RES_STATE_SLEEP 0x8 510 #define RES_STATE_OFF 0x0 511 512 /* Power resources */ 513 514 /* Power providers */ 515 #define RES_VAUX1 1 516 #define RES_VAUX2 2 517 #define RES_VAUX3 3 518 #define RES_VAUX4 4 519 #define RES_VMMC1 5 520 #define RES_VMMC2 6 521 #define RES_VPLL1 7 522 #define RES_VPLL2 8 523 #define RES_VSIM 9 524 #define RES_VDAC 10 525 #define RES_VINTANA1 11 526 #define RES_VINTANA2 12 527 #define RES_VINTDIG 13 528 #define RES_VIO 14 529 #define RES_VDD1 15 530 #define RES_VDD2 16 531 #define RES_VUSB_1V5 17 532 #define RES_VUSB_1V8 18 533 #define RES_VUSB_3V1 19 534 #define RES_VUSBCP 20 535 #define RES_REGEN 21 536 /* Reset and control */ 537 #define RES_NRES_PWRON 22 538 #define RES_CLKEN 23 539 #define RES_SYSEN 24 540 #define RES_HFCLKOUT 25 541 #define RES_32KCLKOUT 26 542 #define RES_RESET 27 543 /* Power Reference */ 544 #define RES_MAIN_REF 28 545 546 #define TOTAL_RESOURCES 28 547 /* 548 * Power Bus Message Format ... these can be sent individually by Linux, 549 * but are usually part of downloaded scripts that are run when various 550 * power events are triggered. 551 * 552 * Broadcast Message (16 Bits): 553 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] 554 * RES_STATE[3:0] 555 * 556 * Singular Message (16 Bits): 557 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] 558 */ 559 560 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \ 561 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ 562 | (type) << 4 | (state)) 563 564 #define MSG_SINGULAR(devgrp, id, state) \ 565 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) 566 567 #define MSG_BROADCAST_ALL(devgrp, state) \ 568 ((devgrp) << 5 | (state)) 569 570 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL 571 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL 572 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL 573 /*----------------------------------------------------------------------*/ 574 575 struct twl4030_clock_init_data { 576 bool ck32k_lowpwr_enable; 577 }; 578 579 struct twl4030_bci_platform_data { 580 int *battery_tmp_tbl; 581 unsigned int tblsize; 582 int bb_uvolt; /* voltage to charge backup battery */ 583 int bb_uamp; /* current for backup battery charging */ 584 }; 585 586 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ 587 struct twl4030_gpio_platform_data { 588 /* package the two LED signals as output-only GPIOs? */ 589 bool use_leds; 590 591 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */ 592 u8 mmc_cd; 593 594 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */ 595 u32 debounce; 596 597 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup 598 * should be enabled. Else, if that bit is set in "pulldowns", 599 * that pulldown is enabled. Don't waste power by letting any 600 * digital inputs float... 601 */ 602 u32 pullups; 603 u32 pulldowns; 604 605 int (*setup)(struct device *dev, 606 unsigned gpio, unsigned ngpio); 607 int (*teardown)(struct device *dev, 608 unsigned gpio, unsigned ngpio); 609 }; 610 611 struct twl4030_madc_platform_data { 612 int irq_line; 613 }; 614 615 /* Boards have unique mappings of {row, col} --> keycode. 616 * Column and row are 8 bits each, but range only from 0..7. 617 * a PERSISTENT_KEY is "always on" and never reported. 618 */ 619 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED) 620 621 struct twl4030_keypad_data { 622 const struct matrix_keymap_data *keymap_data; 623 unsigned rows; 624 unsigned cols; 625 bool rep; 626 }; 627 628 enum twl4030_usb_mode { 629 T2_USB_MODE_ULPI = 1, 630 T2_USB_MODE_CEA2011_3PIN = 2, 631 }; 632 633 struct twl4030_usb_data { 634 enum twl4030_usb_mode usb_mode; 635 unsigned long features; 636 637 int (*phy_init)(struct device *dev); 638 int (*phy_exit)(struct device *dev); 639 /* Power on/off the PHY */ 640 int (*phy_power)(struct device *dev, int iD, int on); 641 /* enable/disable phy clocks */ 642 int (*phy_set_clock)(struct device *dev, int on); 643 /* suspend/resume of phy */ 644 int (*phy_suspend)(struct device *dev, int suspend); 645 }; 646 647 struct twl4030_ins { 648 u16 pmb_message; 649 u8 delay; 650 }; 651 652 struct twl4030_script { 653 struct twl4030_ins *script; 654 unsigned size; 655 u8 flags; 656 #define TWL4030_WRST_SCRIPT (1<<0) 657 #define TWL4030_WAKEUP12_SCRIPT (1<<1) 658 #define TWL4030_WAKEUP3_SCRIPT (1<<2) 659 #define TWL4030_SLEEP_SCRIPT (1<<3) 660 }; 661 662 struct twl4030_resconfig { 663 u8 resource; 664 u8 devgroup; /* Processor group that Power resource belongs to */ 665 u8 type; /* Power resource addressed, 6 / broadcast message */ 666 u8 type2; /* Power resource addressed, 3 / broadcast message */ 667 u8 remap_off; /* off state remapping */ 668 u8 remap_sleep; /* sleep state remapping */ 669 }; 670 671 struct twl4030_power_data { 672 struct twl4030_script **scripts; 673 unsigned num; 674 struct twl4030_resconfig *resource_config; 675 struct twl4030_resconfig *board_config; 676 #define TWL4030_RESCONFIG_UNDEF ((u8)-1) 677 bool use_poweroff; /* Board is wired for TWL poweroff */ 678 bool ac_charger_quirk; /* Disable AC charger on board */ 679 }; 680 681 extern int twl4030_remove_script(u8 flags); 682 extern void twl4030_power_off(void); 683 684 struct twl4030_codec_data { 685 unsigned int digimic_delay; /* in ms */ 686 unsigned int ramp_delay_value; 687 unsigned int offset_cncl_path; 688 unsigned int hs_extmute:1; 689 int hs_extmute_gpio; 690 }; 691 692 struct twl4030_vibra_data { 693 unsigned int coexist; 694 }; 695 696 struct twl4030_audio_data { 697 unsigned int audio_mclk; 698 struct twl4030_codec_data *codec; 699 struct twl4030_vibra_data *vibra; 700 701 /* twl6040 */ 702 int audpwron_gpio; /* audio power-on gpio */ 703 int naudint_irq; /* audio interrupt */ 704 unsigned int irq_base; 705 }; 706 707 struct twl4030_platform_data { 708 struct twl4030_clock_init_data *clock; 709 struct twl4030_bci_platform_data *bci; 710 struct twl4030_gpio_platform_data *gpio; 711 struct twl4030_madc_platform_data *madc; 712 struct twl4030_keypad_data *keypad; 713 struct twl4030_usb_data *usb; 714 struct twl4030_power_data *power; 715 struct twl4030_audio_data *audio; 716 717 /* Common LDO regulators for TWL4030/TWL6030 */ 718 struct regulator_init_data *vdac; 719 struct regulator_init_data *vaux1; 720 struct regulator_init_data *vaux2; 721 struct regulator_init_data *vaux3; 722 struct regulator_init_data *vdd1; 723 struct regulator_init_data *vdd2; 724 struct regulator_init_data *vdd3; 725 /* TWL4030 LDO regulators */ 726 struct regulator_init_data *vpll1; 727 struct regulator_init_data *vpll2; 728 struct regulator_init_data *vmmc1; 729 struct regulator_init_data *vmmc2; 730 struct regulator_init_data *vsim; 731 struct regulator_init_data *vaux4; 732 struct regulator_init_data *vio; 733 struct regulator_init_data *vintana1; 734 struct regulator_init_data *vintana2; 735 struct regulator_init_data *vintdig; 736 /* TWL6030 LDO regulators */ 737 struct regulator_init_data *vmmc; 738 struct regulator_init_data *vpp; 739 struct regulator_init_data *vusim; 740 struct regulator_init_data *vana; 741 struct regulator_init_data *vcxio; 742 struct regulator_init_data *vusb; 743 struct regulator_init_data *clk32kg; 744 struct regulator_init_data *v1v8; 745 struct regulator_init_data *v2v1; 746 /* TWL6032 LDO regulators */ 747 struct regulator_init_data *ldo1; 748 struct regulator_init_data *ldo2; 749 struct regulator_init_data *ldo3; 750 struct regulator_init_data *ldo4; 751 struct regulator_init_data *ldo5; 752 struct regulator_init_data *ldo6; 753 struct regulator_init_data *ldo7; 754 struct regulator_init_data *ldoln; 755 struct regulator_init_data *ldousb; 756 /* TWL6032 DCDC regulators */ 757 struct regulator_init_data *smps3; 758 struct regulator_init_data *smps4; 759 struct regulator_init_data *vio6025; 760 }; 761 762 struct twl_regulator_driver_data { 763 int (*set_voltage)(void *data, int target_uV); 764 int (*get_voltage)(void *data); 765 void *data; 766 unsigned long features; 767 }; 768 /* chip-specific feature flags, for twl_regulator_driver_data.features */ 769 #define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */ 770 #define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */ 771 #define TWL5031 BIT(2) /* twl5031 has different registers */ 772 #define TWL6030_CLASS BIT(3) /* TWL6030 class */ 773 #define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */ 774 #define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible 775 * but not officially supported. 776 * This flag is necessary to 777 * enable them. 778 */ 779 780 /*----------------------------------------------------------------------*/ 781 782 int twl4030_sih_setup(struct device *dev, int module, int irq_base); 783 784 /* Offsets to Power Registers */ 785 #define TWL4030_VDAC_DEV_GRP 0x3B 786 #define TWL4030_VDAC_DEDICATED 0x3E 787 #define TWL4030_VAUX1_DEV_GRP 0x17 788 #define TWL4030_VAUX1_DEDICATED 0x1A 789 #define TWL4030_VAUX2_DEV_GRP 0x1B 790 #define TWL4030_VAUX2_DEDICATED 0x1E 791 #define TWL4030_VAUX3_DEV_GRP 0x1F 792 #define TWL4030_VAUX3_DEDICATED 0x22 793 794 static inline int twl4030charger_usb_en(int enable) { return 0; } 795 796 /*----------------------------------------------------------------------*/ 797 798 /* Linux-specific regulator identifiers ... for now, we only support 799 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 800 * need to tie into hardware based voltage scaling (cpufreq etc), while 801 * VIO is generally fixed. 802 */ 803 804 /* TWL4030 SMPS/LDO's */ 805 /* EXTERNAL dc-to-dc buck converters */ 806 #define TWL4030_REG_VDD1 0 807 #define TWL4030_REG_VDD2 1 808 #define TWL4030_REG_VIO 2 809 810 /* EXTERNAL LDOs */ 811 #define TWL4030_REG_VDAC 3 812 #define TWL4030_REG_VPLL1 4 813 #define TWL4030_REG_VPLL2 5 /* not on all chips */ 814 #define TWL4030_REG_VMMC1 6 815 #define TWL4030_REG_VMMC2 7 /* not on all chips */ 816 #define TWL4030_REG_VSIM 8 /* not on all chips */ 817 #define TWL4030_REG_VAUX1 9 /* not on all chips */ 818 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */ 819 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */ 820 #define TWL4030_REG_VAUX3 12 /* not on all chips */ 821 #define TWL4030_REG_VAUX4 13 /* not on all chips */ 822 823 /* INTERNAL LDOs */ 824 #define TWL4030_REG_VINTANA1 14 825 #define TWL4030_REG_VINTANA2 15 826 #define TWL4030_REG_VINTDIG 16 827 #define TWL4030_REG_VUSB1V5 17 828 #define TWL4030_REG_VUSB1V8 18 829 #define TWL4030_REG_VUSB3V1 19 830 831 /* TWL6030 SMPS/LDO's */ 832 /* EXTERNAL dc-to-dc buck convertor controllable via SR */ 833 #define TWL6030_REG_VDD1 30 834 #define TWL6030_REG_VDD2 31 835 #define TWL6030_REG_VDD3 32 836 837 /* Non SR compliant dc-to-dc buck convertors */ 838 #define TWL6030_REG_VMEM 33 839 #define TWL6030_REG_V2V1 34 840 #define TWL6030_REG_V1V29 35 841 #define TWL6030_REG_V1V8 36 842 843 /* EXTERNAL LDOs */ 844 #define TWL6030_REG_VAUX1_6030 37 845 #define TWL6030_REG_VAUX2_6030 38 846 #define TWL6030_REG_VAUX3_6030 39 847 #define TWL6030_REG_VMMC 40 848 #define TWL6030_REG_VPP 41 849 #define TWL6030_REG_VUSIM 42 850 #define TWL6030_REG_VANA 43 851 #define TWL6030_REG_VCXIO 44 852 #define TWL6030_REG_VDAC 45 853 #define TWL6030_REG_VUSB 46 854 855 /* INTERNAL LDOs */ 856 #define TWL6030_REG_VRTC 47 857 #define TWL6030_REG_CLK32KG 48 858 859 /* LDOs on 6025 have different names */ 860 #define TWL6032_REG_LDO2 49 861 #define TWL6032_REG_LDO4 50 862 #define TWL6032_REG_LDO3 51 863 #define TWL6032_REG_LDO5 52 864 #define TWL6032_REG_LDO1 53 865 #define TWL6032_REG_LDO7 54 866 #define TWL6032_REG_LDO6 55 867 #define TWL6032_REG_LDOLN 56 868 #define TWL6032_REG_LDOUSB 57 869 870 /* 6025 DCDC supplies */ 871 #define TWL6032_REG_SMPS3 58 872 #define TWL6032_REG_SMPS4 59 873 #define TWL6032_REG_VIO 60 874 875 876 #endif /* End of __TWL4030_H */ 877