xref: /openbmc/linux/include/linux/mfd/tps65217.h (revision 82003e04)
1 /*
2  * linux/mfd/tps65217.h
3  *
4  * Functions to access TPS65217 power management chip.
5  *
6  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17 
18 #ifndef __LINUX_MFD_TPS65217_H
19 #define __LINUX_MFD_TPS65217_H
20 
21 #include <linux/i2c.h>
22 #include <linux/regulator/driver.h>
23 #include <linux/regulator/machine.h>
24 
25 /* TPS chip id list */
26 #define TPS65217			0xF0
27 
28 /* I2C ID for TPS65217 part */
29 #define TPS65217_I2C_ID			0x24
30 
31 /* All register addresses */
32 #define TPS65217_REG_CHIPID		0X00
33 #define TPS65217_REG_PPATH		0X01
34 #define TPS65217_REG_INT		0X02
35 #define TPS65217_REG_CHGCONFIG0		0X03
36 #define TPS65217_REG_CHGCONFIG1		0X04
37 #define TPS65217_REG_CHGCONFIG2		0X05
38 #define TPS65217_REG_CHGCONFIG3		0X06
39 #define TPS65217_REG_WLEDCTRL1		0X07
40 #define TPS65217_REG_WLEDCTRL2		0X08
41 #define TPS65217_REG_MUXCTRL		0X09
42 #define TPS65217_REG_STATUS		0X0A
43 #define TPS65217_REG_PASSWORD		0X0B
44 #define TPS65217_REG_PGOOD		0X0C
45 #define TPS65217_REG_DEFPG		0X0D
46 #define TPS65217_REG_DEFDCDC1		0X0E
47 #define TPS65217_REG_DEFDCDC2		0X0F
48 #define TPS65217_REG_DEFDCDC3		0X10
49 #define TPS65217_REG_DEFSLEW		0X11
50 #define TPS65217_REG_DEFLDO1		0X12
51 #define TPS65217_REG_DEFLDO2		0X13
52 #define TPS65217_REG_DEFLS1		0X14
53 #define TPS65217_REG_DEFLS2		0X15
54 #define TPS65217_REG_ENABLE		0X16
55 #define TPS65217_REG_DEFUVLO		0X18
56 #define TPS65217_REG_SEQ1		0X19
57 #define TPS65217_REG_SEQ2		0X1A
58 #define TPS65217_REG_SEQ3		0X1B
59 #define TPS65217_REG_SEQ4		0X1C
60 #define TPS65217_REG_SEQ5		0X1D
61 #define TPS65217_REG_SEQ6		0X1E
62 
63 #define TPS65217_REG_MAX		TPS65217_REG_SEQ6
64 
65 /* Register field definitions */
66 #define TPS65217_CHIPID_CHIP_MASK	0xF0
67 #define TPS65217_CHIPID_REV_MASK	0x0F
68 
69 #define TPS65217_PPATH_ACSINK_ENABLE	BIT(7)
70 #define TPS65217_PPATH_USBSINK_ENABLE	BIT(6)
71 #define TPS65217_PPATH_AC_PW_ENABLE	BIT(5)
72 #define TPS65217_PPATH_USB_PW_ENABLE	BIT(4)
73 #define TPS65217_PPATH_AC_CURRENT_MASK	0x0C
74 #define TPS65217_PPATH_USB_CURRENT_MASK	0x03
75 
76 #define TPS65217_INT_RESERVEDM		BIT(7)
77 #define TPS65217_INT_PBM		BIT(6)
78 #define TPS65217_INT_ACM		BIT(5)
79 #define TPS65217_INT_USBM		BIT(4)
80 #define TPS65217_INT_PBI		BIT(2)
81 #define TPS65217_INT_ACI		BIT(1)
82 #define TPS65217_INT_USBI		BIT(0)
83 
84 #define TPS65217_CHGCONFIG0_TREG	BIT(7)
85 #define TPS65217_CHGCONFIG0_DPPM	BIT(6)
86 #define TPS65217_CHGCONFIG0_TSUSP	BIT(5)
87 #define TPS65217_CHGCONFIG0_TERMI	BIT(4)
88 #define TPS65217_CHGCONFIG0_ACTIVE	BIT(3)
89 #define TPS65217_CHGCONFIG0_CHGTOUT	BIT(2)
90 #define TPS65217_CHGCONFIG0_PCHGTOUT	BIT(1)
91 #define TPS65217_CHGCONFIG0_BATTEMP	BIT(0)
92 
93 #define TPS65217_CHGCONFIG1_TMR_MASK	0xC0
94 #define TPS65217_CHGCONFIG1_TMR_ENABLE	BIT(5)
95 #define TPS65217_CHGCONFIG1_NTC_TYPE	BIT(4)
96 #define TPS65217_CHGCONFIG1_RESET	BIT(3)
97 #define TPS65217_CHGCONFIG1_TERM	BIT(2)
98 #define TPS65217_CHGCONFIG1_SUSP	BIT(1)
99 #define TPS65217_CHGCONFIG1_CHG_EN	BIT(0)
100 
101 #define TPS65217_CHGCONFIG2_DYNTMR	BIT(7)
102 #define TPS65217_CHGCONFIG2_VPREGHG	BIT(6)
103 #define TPS65217_CHGCONFIG2_VOREG_MASK	0x30
104 
105 #define TPS65217_CHGCONFIG3_ICHRG_MASK	0xC0
106 #define TPS65217_CHGCONFIG3_DPPMTH_MASK	0x30
107 #define TPS65217_CHGCONFIG2_PCHRGT	BIT(3)
108 #define TPS65217_CHGCONFIG2_TERMIF	0x06
109 #define TPS65217_CHGCONFIG2_TRANGE	BIT(0)
110 
111 #define TPS65217_WLEDCTRL1_ISINK_ENABLE	BIT(3)
112 #define TPS65217_WLEDCTRL1_ISEL		BIT(2)
113 #define TPS65217_WLEDCTRL1_FDIM_MASK	0x03
114 
115 #define TPS65217_WLEDCTRL2_DUTY_MASK	0x7F
116 
117 #define TPS65217_MUXCTRL_MUX_MASK	0x07
118 
119 #define TPS65217_STATUS_OFF		BIT(7)
120 #define TPS65217_STATUS_ACPWR		BIT(3)
121 #define TPS65217_STATUS_USBPWR		BIT(2)
122 #define TPS65217_STATUS_PB		BIT(0)
123 
124 #define TPS65217_PASSWORD_REGS_UNLOCK	0x7D
125 
126 #define TPS65217_PGOOD_LDO3_PG		BIT(6)
127 #define TPS65217_PGOOD_LDO4_PG		BIT(5)
128 #define TPS65217_PGOOD_DC1_PG		BIT(4)
129 #define TPS65217_PGOOD_DC2_PG		BIT(3)
130 #define TPS65217_PGOOD_DC3_PG		BIT(2)
131 #define TPS65217_PGOOD_LDO1_PG		BIT(1)
132 #define TPS65217_PGOOD_LDO2_PG		BIT(0)
133 
134 #define TPS65217_DEFPG_LDO1PGM		BIT(3)
135 #define TPS65217_DEFPG_LDO2PGM		BIT(2)
136 #define TPS65217_DEFPG_PGDLY_MASK	0x03
137 
138 #define TPS65217_DEFDCDCX_XADJX		BIT(7)
139 #define TPS65217_DEFDCDCX_DCDC_MASK	0x3F
140 
141 #define TPS65217_DEFSLEW_GO		BIT(7)
142 #define TPS65217_DEFSLEW_GODSBL		BIT(6)
143 #define TPS65217_DEFSLEW_PFM_EN1	BIT(5)
144 #define TPS65217_DEFSLEW_PFM_EN2	BIT(4)
145 #define TPS65217_DEFSLEW_PFM_EN3	BIT(3)
146 #define TPS65217_DEFSLEW_SLEW_MASK	0x07
147 
148 #define TPS65217_DEFLDO1_LDO1_MASK	0x0F
149 
150 #define TPS65217_DEFLDO2_TRACK		BIT(6)
151 #define TPS65217_DEFLDO2_LDO2_MASK	0x3F
152 
153 #define TPS65217_DEFLDO3_LDO3_EN	BIT(5)
154 #define TPS65217_DEFLDO3_LDO3_MASK	0x1F
155 
156 #define TPS65217_DEFLDO4_LDO4_EN	BIT(5)
157 #define TPS65217_DEFLDO4_LDO4_MASK	0x1F
158 
159 #define TPS65217_ENABLE_LS1_EN		BIT(6)
160 #define TPS65217_ENABLE_LS2_EN		BIT(5)
161 #define TPS65217_ENABLE_DC1_EN		BIT(4)
162 #define TPS65217_ENABLE_DC2_EN		BIT(3)
163 #define TPS65217_ENABLE_DC3_EN		BIT(2)
164 #define TPS65217_ENABLE_LDO1_EN		BIT(1)
165 #define TPS65217_ENABLE_LDO2_EN		BIT(0)
166 
167 #define TPS65217_DEFUVLO_UVLOHYS	BIT(2)
168 #define TPS65217_DEFUVLO_UVLO_MASK	0x03
169 
170 #define TPS65217_SEQ1_DC1_SEQ_MASK	0xF0
171 #define TPS65217_SEQ1_DC2_SEQ_MASK	0x0F
172 
173 #define TPS65217_SEQ2_DC3_SEQ_MASK	0xF0
174 #define TPS65217_SEQ2_LDO1_SEQ_MASK	0x0F
175 
176 #define TPS65217_SEQ3_LDO2_SEQ_MASK	0xF0
177 #define TPS65217_SEQ3_LDO3_SEQ_MASK	0x0F
178 
179 #define TPS65217_SEQ4_LDO4_SEQ_MASK	0xF0
180 
181 #define TPS65217_SEQ5_DLY1_MASK		0xC0
182 #define TPS65217_SEQ5_DLY2_MASK		0x30
183 #define TPS65217_SEQ5_DLY3_MASK		0x0C
184 #define TPS65217_SEQ5_DLY4_MASK		0x03
185 
186 #define TPS65217_SEQ6_DLY5_MASK		0xC0
187 #define TPS65217_SEQ6_DLY6_MASK		0x30
188 #define TPS65217_SEQ6_SEQUP		BIT(2)
189 #define TPS65217_SEQ6_SEQDWN		BIT(1)
190 #define TPS65217_SEQ6_INSTDWN		BIT(0)
191 
192 #define TPS65217_MAX_REGISTER		0x1E
193 #define TPS65217_PROTECT_NONE		0
194 #define TPS65217_PROTECT_L1		1
195 #define TPS65217_PROTECT_L2		2
196 
197 
198 enum tps65217_regulator_id {
199 	/* DCDC's */
200 	TPS65217_DCDC_1,
201 	TPS65217_DCDC_2,
202 	TPS65217_DCDC_3,
203 	/* LDOs */
204 	TPS65217_LDO_1,
205 	TPS65217_LDO_2,
206 	TPS65217_LDO_3,
207 	TPS65217_LDO_4,
208 };
209 
210 #define TPS65217_MAX_REG_ID		TPS65217_LDO_4
211 
212 /* Number of step-down converters available */
213 #define TPS65217_NUM_DCDC		3
214 /* Number of LDO voltage regulators available */
215 #define TPS65217_NUM_LDO		4
216 /* Number of total regulators available */
217 #define TPS65217_NUM_REGULATOR		(TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
218 
219 enum tps65217_bl_isel {
220 	TPS65217_BL_ISET1 = 1,
221 	TPS65217_BL_ISET2,
222 };
223 
224 enum tps65217_bl_fdim {
225 	TPS65217_BL_FDIM_100HZ,
226 	TPS65217_BL_FDIM_200HZ,
227 	TPS65217_BL_FDIM_500HZ,
228 	TPS65217_BL_FDIM_1000HZ,
229 };
230 
231 struct tps65217_bl_pdata {
232 	enum tps65217_bl_isel isel;
233 	enum tps65217_bl_fdim fdim;
234 	int dft_brightness;
235 };
236 
237 enum tps65217_irq_type {
238 	TPS65217_IRQ_PB,
239 	TPS65217_IRQ_AC,
240 	TPS65217_IRQ_USB,
241 	TPS65217_NUM_IRQ
242 };
243 
244 /**
245  * struct tps65217_board - packages regulator init data
246  * @tps65217_regulator_data: regulator initialization values
247  *
248  * Board data may be used to initialize regulator.
249  */
250 struct tps65217_board {
251 	struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
252 	struct device_node *of_node[TPS65217_NUM_REGULATOR];
253 	struct tps65217_bl_pdata *bl_pdata;
254 };
255 
256 /**
257  * struct tps65217 - tps65217 sub-driver chip access routines
258  *
259  * Device data may be used to access the TPS65217 chip
260  */
261 
262 struct tps65217 {
263 	struct device *dev;
264 	struct tps65217_board *pdata;
265 	unsigned long id;
266 	struct regulator_desc desc[TPS65217_NUM_REGULATOR];
267 	struct regmap *regmap;
268 	u8 *strobes;
269 	struct irq_domain *irq_domain;
270 	struct mutex irq_lock;
271 	u8 irq_mask;
272 	int irq;
273 };
274 
275 static inline struct tps65217 *dev_to_tps65217(struct device *dev)
276 {
277 	return dev_get_drvdata(dev);
278 }
279 
280 static inline unsigned long tps65217_chip_id(struct tps65217 *tps65217)
281 {
282 	return tps65217->id;
283 }
284 
285 int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
286 					unsigned int *val);
287 int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
288 			unsigned int val, unsigned int level);
289 int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
290 		unsigned int mask, unsigned int val, unsigned int level);
291 int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
292 		unsigned int mask, unsigned int level);
293 
294 #endif /*  __LINUX_MFD_TPS65217_H */
295