1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * TI Touch Screen / ADC MFD driver 4 * 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 #ifndef __LINUX_TI_AM335X_TSCADC_MFD_H 9 #define __LINUX_TI_AM335X_TSCADC_MFD_H 10 11 #include <linux/bitfield.h> 12 #include <linux/mfd/core.h> 13 #include <linux/units.h> 14 15 #define REG_RAWIRQSTATUS 0x024 16 #define REG_IRQSTATUS 0x028 17 #define REG_IRQENABLE 0x02C 18 #define REG_IRQCLR 0x030 19 #define REG_IRQWAKEUP 0x034 20 #define REG_DMAENABLE_SET 0x038 21 #define REG_DMAENABLE_CLEAR 0x03c 22 #define REG_CTRL 0x040 23 #define REG_ADCFSM 0x044 24 #define REG_CLKDIV 0x04C 25 #define REG_SE 0x054 26 #define REG_IDLECONFIG 0x058 27 #define REG_CHARGECONFIG 0x05C 28 #define REG_CHARGEDELAY 0x060 29 #define REG_STEPCONFIG(n) (0x64 + ((n) * 8)) 30 #define REG_STEPDELAY(n) (0x68 + ((n) * 8)) 31 #define REG_FIFO0CNT 0xE4 32 #define REG_FIFO0THR 0xE8 33 #define REG_FIFO1CNT 0xF0 34 #define REG_FIFO1THR 0xF4 35 #define REG_DMA1REQ 0xF8 36 #define REG_FIFO0 0x100 37 #define REG_FIFO1 0x200 38 39 /* Register Bitfields */ 40 /* IRQ wakeup enable */ 41 #define IRQWKUP_ENB BIT(0) 42 43 /* IRQ enable */ 44 #define IRQENB_HW_PEN BIT(0) 45 #define IRQENB_EOS BIT(1) 46 #define IRQENB_FIFO0THRES BIT(2) 47 #define IRQENB_FIFO0OVRRUN BIT(3) 48 #define IRQENB_FIFO0UNDRFLW BIT(4) 49 #define IRQENB_FIFO1THRES BIT(5) 50 #define IRQENB_FIFO1OVRRUN BIT(6) 51 #define IRQENB_FIFO1UNDRFLW BIT(7) 52 #define IRQENB_PENUP BIT(9) 53 54 /* Step Configuration */ 55 #define STEPCONFIG_MODE(val) FIELD_PREP(GENMASK(1, 0), (val)) 56 #define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1) 57 #define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2) 58 #define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val)) 59 #define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4) 60 #define STEPCONFIG_XPP BIT(5) 61 #define STEPCONFIG_XNN BIT(6) 62 #define STEPCONFIG_YPP BIT(7) 63 #define STEPCONFIG_YNN BIT(8) 64 #define STEPCONFIG_XNP BIT(9) 65 #define STEPCONFIG_YPN BIT(10) 66 #define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val)) 67 #define STEPCONFIG_RFP_VREFP STEPCONFIG_RFP(3) 68 #define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val)) 69 #define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8) 70 #define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val)) 71 #define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4) 72 #define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8) 73 #define STEPCONFIG_FIFO1 BIT(26) 74 #define STEPCONFIG_RFM(val) FIELD_PREP(GENMASK(24, 23), (val)) 75 #define STEPCONFIG_RFM_VREFN STEPCONFIG_RFM(3) 76 77 /* Delay register */ 78 #define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val)) 79 #define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098) 80 #define STEPCONFIG_MAX_OPENDLY GENMASK(17, 0) 81 #define STEPDELAY_SAMPLE(val) FIELD_PREP(GENMASK(31, 24), (val)) 82 #define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0) 83 #define STEPCONFIG_MAX_SAMPLE GENMASK(7, 0) 84 85 /* Charge Config */ 86 #define STEPCHARGE_RFP(val) FIELD_PREP(GENMASK(14, 12), (val)) 87 #define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1) 88 #define STEPCHARGE_INM(val) FIELD_PREP(GENMASK(18, 15), (val)) 89 #define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1) 90 #define STEPCHARGE_INP(val) FIELD_PREP(GENMASK(22, 19), (val)) 91 #define STEPCHARGE_RFM(val) FIELD_PREP(GENMASK(24, 23), (val)) 92 #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1) 93 94 /* Charge delay */ 95 #define CHARGEDLY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val)) 96 #define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400) 97 98 /* Control register */ 99 #define CNTRLREG_SSENB BIT(0) 100 #define CNTRLREG_STEPID BIT(1) 101 #define CNTRLREG_TSC_STEPCONFIGWRT BIT(2) 102 #define CNTRLREG_POWERDOWN BIT(4) 103 #define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(GENMASK(6, 5), (val)) 104 #define CNTRLREG_TSC_4WIRE CNTRLREG_TSC_AFE_CTRL(1) 105 #define CNTRLREG_TSC_5WIRE CNTRLREG_TSC_AFE_CTRL(2) 106 #define CNTRLREG_TSC_8WIRE CNTRLREG_TSC_AFE_CTRL(3) 107 #define CNTRLREG_TSC_ENB BIT(7) 108 109 /*Control registers bitfields for MAGADC IP */ 110 #define CNTRLREG_MAGADCENB BIT(0) 111 #define CNTRLREG_MAG_PREAMP_PWRDOWN BIT(5) 112 #define CNTRLREG_MAG_PREAMP_BYPASS BIT(6) 113 114 /* FIFO READ Register */ 115 #define FIFOREAD_DATA_MASK GENMASK(11, 0) 116 #define FIFOREAD_CHNLID_MASK GENMASK(19, 16) 117 118 /* DMA ENABLE/CLEAR Register */ 119 #define DMA_FIFO0 BIT(0) 120 #define DMA_FIFO1 BIT(1) 121 122 /* Sequencer Status */ 123 #define SEQ_STATUS BIT(5) 124 #define CHARGE_STEP 0x11 125 126 #define TSC_ADC_CLK (3 * HZ_PER_MHZ) 127 #define MAG_ADC_CLK (13 * HZ_PER_MHZ) 128 #define TOTAL_STEPS 16 129 #define TOTAL_CHANNELS 8 130 #define FIFO1_THRESHOLD 19 131 132 /* 133 * time in us for processing a single channel, calculated as follows: 134 * 135 * max num cycles = open delay + (sample delay + conv time) * averaging 136 * 137 * max num cycles: 262143 + (255 + 13) * 16 = 266431 138 * 139 * clock frequency: 26MHz / 8 = 3.25MHz 140 * clock period: 1 / 3.25MHz = 308ns 141 * 142 * max processing time: 266431 * 308ns = 83ms(approx) 143 */ 144 #define IDLE_TIMEOUT_MS 83 /* milliseconds */ 145 146 #define TSCADC_CELLS 2 147 148 struct ti_tscadc_data { 149 char *adc_feature_name; 150 char *adc_feature_compatible; 151 char *secondary_feature_name; 152 char *secondary_feature_compatible; 153 unsigned int target_clk_rate; 154 }; 155 156 struct ti_tscadc_dev { 157 struct device *dev; 158 struct regmap *regmap; 159 void __iomem *tscadc_base; 160 phys_addr_t tscadc_phys_base; 161 const struct ti_tscadc_data *data; 162 int irq; 163 struct mfd_cell cells[TSCADC_CELLS]; 164 u32 ctrl; 165 u32 reg_se_cache; 166 bool adc_waiting; 167 bool adc_in_use; 168 wait_queue_head_t reg_se_wait; 169 spinlock_t reg_lock; 170 unsigned int clk_div; 171 172 /* tsc device */ 173 struct titsc *tsc; 174 175 /* adc device */ 176 struct adc_device *adc; 177 }; 178 179 static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p) 180 { 181 struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data; 182 183 return *tscadc_dev; 184 } 185 186 static inline bool ti_adc_with_touchscreen(struct ti_tscadc_dev *tscadc) 187 { 188 return of_device_is_compatible(tscadc->dev->of_node, 189 "ti,am3359-tscadc"); 190 } 191 192 void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val); 193 void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val); 194 void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val); 195 void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc); 196 197 #endif 198