1 #ifndef __LINUX_TI_AM335X_TSCADC_MFD_H 2 #define __LINUX_TI_AM335X_TSCADC_MFD_H 3 4 /* 5 * TI Touch Screen / ADC MFD driver 6 * 7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 * 13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 14 * kind, whether express or implied; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/mfd/core.h> 20 21 #define REG_RAWIRQSTATUS 0x024 22 #define REG_IRQSTATUS 0x028 23 #define REG_IRQENABLE 0x02C 24 #define REG_IRQCLR 0x030 25 #define REG_IRQWAKEUP 0x034 26 #define REG_CTRL 0x040 27 #define REG_ADCFSM 0x044 28 #define REG_CLKDIV 0x04C 29 #define REG_SE 0x054 30 #define REG_IDLECONFIG 0x058 31 #define REG_CHARGECONFIG 0x05C 32 #define REG_CHARGEDELAY 0x060 33 #define REG_STEPCONFIG(n) (0x64 + ((n) * 8)) 34 #define REG_STEPDELAY(n) (0x68 + ((n) * 8)) 35 #define REG_FIFO0CNT 0xE4 36 #define REG_FIFO0THR 0xE8 37 #define REG_FIFO1CNT 0xF0 38 #define REG_FIFO1THR 0xF4 39 #define REG_FIFO0 0x100 40 #define REG_FIFO1 0x200 41 42 /* Register Bitfields */ 43 /* IRQ wakeup enable */ 44 #define IRQWKUP_ENB BIT(0) 45 46 /* Step Enable */ 47 #define STEPENB_MASK (0x1FFFF << 0) 48 #define STEPENB(val) ((val) << 0) 49 #define ENB(val) (1 << (val)) 50 #define STPENB_STEPENB STEPENB(0x1FFFF) 51 #define STPENB_STEPENB_TC STEPENB(0x1FFF) 52 53 /* IRQ enable */ 54 #define IRQENB_HW_PEN BIT(0) 55 #define IRQENB_EOS BIT(1) 56 #define IRQENB_FIFO0THRES BIT(2) 57 #define IRQENB_FIFO0OVRRUN BIT(3) 58 #define IRQENB_FIFO0UNDRFLW BIT(4) 59 #define IRQENB_FIFO1THRES BIT(5) 60 #define IRQENB_FIFO1OVRRUN BIT(6) 61 #define IRQENB_FIFO1UNDRFLW BIT(7) 62 #define IRQENB_PENUP BIT(9) 63 64 /* Step Configuration */ 65 #define STEPCONFIG_MODE_MASK (3 << 0) 66 #define STEPCONFIG_MODE(val) ((val) << 0) 67 #define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1) 68 #define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2) 69 #define STEPCONFIG_AVG_MASK (7 << 2) 70 #define STEPCONFIG_AVG(val) ((val) << 2) 71 #define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4) 72 #define STEPCONFIG_XPP BIT(5) 73 #define STEPCONFIG_XNN BIT(6) 74 #define STEPCONFIG_YPP BIT(7) 75 #define STEPCONFIG_YNN BIT(8) 76 #define STEPCONFIG_XNP BIT(9) 77 #define STEPCONFIG_YPN BIT(10) 78 #define STEPCONFIG_INM_MASK (0xF << 15) 79 #define STEPCONFIG_INM(val) ((val) << 15) 80 #define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8) 81 #define STEPCONFIG_INP_MASK (0xF << 19) 82 #define STEPCONFIG_INP(val) ((val) << 19) 83 #define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4) 84 #define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8) 85 #define STEPCONFIG_FIFO1 BIT(26) 86 87 /* Delay register */ 88 #define STEPDELAY_OPEN_MASK (0x3FFFF << 0) 89 #define STEPDELAY_OPEN(val) ((val) << 0) 90 #define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098) 91 #define STEPDELAY_SAMPLE_MASK (0xFF << 24) 92 #define STEPDELAY_SAMPLE(val) ((val) << 24) 93 #define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0) 94 95 /* Charge Config */ 96 #define STEPCHARGE_RFP_MASK (7 << 12) 97 #define STEPCHARGE_RFP(val) ((val) << 12) 98 #define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1) 99 #define STEPCHARGE_INM_MASK (0xF << 15) 100 #define STEPCHARGE_INM(val) ((val) << 15) 101 #define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1) 102 #define STEPCHARGE_INP_MASK (0xF << 19) 103 #define STEPCHARGE_INP(val) ((val) << 19) 104 #define STEPCHARGE_RFM_MASK (3 << 23) 105 #define STEPCHARGE_RFM(val) ((val) << 23) 106 #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1) 107 108 /* Charge delay */ 109 #define CHARGEDLY_OPEN_MASK (0x3FFFF << 0) 110 #define CHARGEDLY_OPEN(val) ((val) << 0) 111 #define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400) 112 113 /* Control register */ 114 #define CNTRLREG_TSCSSENB BIT(0) 115 #define CNTRLREG_STEPID BIT(1) 116 #define CNTRLREG_STEPCONFIGWRT BIT(2) 117 #define CNTRLREG_POWERDOWN BIT(4) 118 #define CNTRLREG_AFE_CTRL_MASK (3 << 5) 119 #define CNTRLREG_AFE_CTRL(val) ((val) << 5) 120 #define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1) 121 #define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2) 122 #define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) 123 #define CNTRLREG_TSCENB BIT(7) 124 125 /* FIFO READ Register */ 126 #define FIFOREAD_DATA_MASK (0xfff << 0) 127 #define FIFOREAD_CHNLID_MASK (0xf << 16) 128 129 /* Sequencer Status */ 130 #define SEQ_STATUS BIT(5) 131 #define CHARGE_STEP 0x11 132 133 #define ADC_CLK 3000000 134 #define TOTAL_STEPS 16 135 #define TOTAL_CHANNELS 8 136 #define FIFO1_THRESHOLD 19 137 138 /* 139 * time in us for processing a single channel, calculated as follows: 140 * 141 * num cycles = open delay + (sample delay + conv time) * averaging 142 * 143 * num cycles: 152 + (1 + 13) * 16 = 376 144 * 145 * clock frequency: 26MHz / 8 = 3.25MHz 146 * clock period: 1 / 3.25MHz = 308ns 147 * 148 * processing time: 376 * 308ns = 116us 149 */ 150 #define IDLE_TIMEOUT 116 /* microsec */ 151 152 #define TSCADC_CELLS 2 153 154 struct ti_tscadc_dev { 155 struct device *dev; 156 struct regmap *regmap_tscadc; 157 void __iomem *tscadc_base; 158 int irq; 159 int used_cells; /* 1-2 */ 160 int tsc_wires; 161 int tsc_cell; /* -1 if not used */ 162 int adc_cell; /* -1 if not used */ 163 struct mfd_cell cells[TSCADC_CELLS]; 164 u32 reg_se_cache; 165 bool adc_waiting; 166 bool adc_in_use; 167 wait_queue_head_t reg_se_wait; 168 spinlock_t reg_lock; 169 unsigned int clk_div; 170 171 /* tsc device */ 172 struct titsc *tsc; 173 174 /* adc device */ 175 struct adc_device *adc; 176 }; 177 178 static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p) 179 { 180 struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data; 181 182 return *tscadc_dev; 183 } 184 185 void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val); 186 void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val); 187 void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val); 188 void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc); 189 190 #endif 191