1993c0ba7STudor Ambarus /* SPDX-License-Identifier: GPL-2.0+ */ 21aa15f4eSAlexandre Belloni /* 31aa15f4eSAlexandre Belloni * Copyright (C) 2005 Ivan Kokshaysky 41aa15f4eSAlexandre Belloni * Copyright (C) SAN People 51aa15f4eSAlexandre Belloni * 61aa15f4eSAlexandre Belloni * System Timer (ST) - System peripherals registers. 71aa15f4eSAlexandre Belloni * Based on AT91RM9200 datasheet revision E. 81aa15f4eSAlexandre Belloni */ 91aa15f4eSAlexandre Belloni 101aa15f4eSAlexandre Belloni #ifndef _LINUX_MFD_SYSCON_ATMEL_ST_H 111aa15f4eSAlexandre Belloni #define _LINUX_MFD_SYSCON_ATMEL_ST_H 121aa15f4eSAlexandre Belloni 131aa15f4eSAlexandre Belloni #include <linux/bitops.h> 141aa15f4eSAlexandre Belloni 151aa15f4eSAlexandre Belloni #define AT91_ST_CR 0x00 /* Control Register */ 161aa15f4eSAlexandre Belloni #define AT91_ST_WDRST BIT(0) /* Watchdog Timer Restart */ 171aa15f4eSAlexandre Belloni 181aa15f4eSAlexandre Belloni #define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */ 191aa15f4eSAlexandre Belloni #define AT91_ST_PIV 0xffff /* Period Interval Value */ 201aa15f4eSAlexandre Belloni 211aa15f4eSAlexandre Belloni #define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */ 221aa15f4eSAlexandre Belloni #define AT91_ST_WDV 0xffff /* Watchdog Counter Value */ 231aa15f4eSAlexandre Belloni #define AT91_ST_RSTEN BIT(16) /* Reset Enable */ 241aa15f4eSAlexandre Belloni #define AT91_ST_EXTEN BIT(17) /* External Signal Assertion Enable */ 251aa15f4eSAlexandre Belloni 261aa15f4eSAlexandre Belloni #define AT91_ST_RTMR 0x0c /* Real-time Mode Register */ 271aa15f4eSAlexandre Belloni #define AT91_ST_RTPRES 0xffff /* Real-time Prescalar Value */ 281aa15f4eSAlexandre Belloni 291aa15f4eSAlexandre Belloni #define AT91_ST_SR 0x10 /* Status Register */ 301aa15f4eSAlexandre Belloni #define AT91_ST_PITS BIT(0) /* Period Interval Timer Status */ 311aa15f4eSAlexandre Belloni #define AT91_ST_WDOVF BIT(1) /* Watchdog Overflow */ 321aa15f4eSAlexandre Belloni #define AT91_ST_RTTINC BIT(2) /* Real-time Timer Increment */ 331aa15f4eSAlexandre Belloni #define AT91_ST_ALMS BIT(3) /* Alarm Status */ 341aa15f4eSAlexandre Belloni 351aa15f4eSAlexandre Belloni #define AT91_ST_IER 0x14 /* Interrupt Enable Register */ 361aa15f4eSAlexandre Belloni #define AT91_ST_IDR 0x18 /* Interrupt Disable Register */ 371aa15f4eSAlexandre Belloni #define AT91_ST_IMR 0x1c /* Interrupt Mask Register */ 381aa15f4eSAlexandre Belloni 391aa15f4eSAlexandre Belloni #define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */ 401aa15f4eSAlexandre Belloni #define AT91_ST_ALMV 0xfffff /* Alarm Value */ 411aa15f4eSAlexandre Belloni 421aa15f4eSAlexandre Belloni #define AT91_ST_CRTR 0x24 /* Current Real-time Register */ 431aa15f4eSAlexandre Belloni #define AT91_ST_CRTV 0xfffff /* Current Real-Time Value */ 441aa15f4eSAlexandre Belloni 451aa15f4eSAlexandre Belloni #endif /* _LINUX_MFD_SYSCON_ATMEL_ST_H */ 46