1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * STM32 Low-Power Timer parent driver.
4  * Copyright (C) STMicroelectronics 2017
5  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
6  * Inspired by Benjamin Gaignard's stm32-timers driver
7  */
8 
9 #ifndef _LINUX_STM32_LPTIMER_H_
10 #define _LINUX_STM32_LPTIMER_H_
11 
12 #include <linux/clk.h>
13 #include <linux/regmap.h>
14 
15 #define STM32_LPTIM_ISR		0x00	/* Interrupt and Status Reg  */
16 #define STM32_LPTIM_ICR		0x04	/* Interrupt Clear Reg       */
17 #define STM32_LPTIM_IER		0x08	/* Interrupt Enable Reg      */
18 #define STM32_LPTIM_CFGR	0x0C	/* Configuration Reg         */
19 #define STM32_LPTIM_CR		0x10	/* Control Reg               */
20 #define STM32_LPTIM_CMP		0x14	/* Compare Reg               */
21 #define STM32_LPTIM_ARR		0x18	/* Autoreload Reg            */
22 #define STM32_LPTIM_CNT		0x1C	/* Counter Reg               */
23 
24 /* STM32_LPTIM_ISR - bit fields */
25 #define STM32_LPTIM_CMPOK_ARROK		GENMASK(4, 3)
26 #define STM32_LPTIM_ARROK		BIT(4)
27 #define STM32_LPTIM_CMPOK		BIT(3)
28 
29 /* STM32_LPTIM_ICR - bit fields */
30 #define STM32_LPTIM_CMPOKCF_ARROKCF	GENMASK(4, 3)
31 
32 /* STM32_LPTIM_CR - bit fields */
33 #define STM32_LPTIM_CNTSTRT	BIT(2)
34 #define STM32_LPTIM_ENABLE	BIT(0)
35 
36 /* STM32_LPTIM_CFGR - bit fields */
37 #define STM32_LPTIM_ENC		BIT(24)
38 #define STM32_LPTIM_COUNTMODE	BIT(23)
39 #define STM32_LPTIM_WAVPOL	BIT(21)
40 #define STM32_LPTIM_PRESC	GENMASK(11, 9)
41 #define STM32_LPTIM_CKPOL	GENMASK(2, 1)
42 
43 /* STM32_LPTIM_ARR */
44 #define STM32_LPTIM_MAX_ARR	0xFFFF
45 
46 /**
47  * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device
48  * @clk: clock reference for this instance
49  * @regmap: register map reference for this instance
50  * @has_encoder: indicates this Low-Power Timer supports encoder mode
51  */
52 struct stm32_lptimer {
53 	struct clk *clk;
54 	struct regmap *regmap;
55 	bool has_encoder;
56 };
57 
58 #endif
59