139b27ad9SKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0+ */ 254e8827dSChanwoo Choi /* 354e8827dSChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd 454e8827dSChanwoo Choi * http://www.samsung.com 554e8827dSChanwoo Choi */ 654e8827dSChanwoo Choi 754e8827dSChanwoo Choi #ifndef __LINUX_MFD_S2MPU02_H 854e8827dSChanwoo Choi #define __LINUX_MFD_S2MPU02_H 954e8827dSChanwoo Choi 1054e8827dSChanwoo Choi /* S2MPU02 registers */ 1154e8827dSChanwoo Choi enum S2MPU02_reg { 1254e8827dSChanwoo Choi S2MPU02_REG_ID, 1354e8827dSChanwoo Choi S2MPU02_REG_INT1, 1454e8827dSChanwoo Choi S2MPU02_REG_INT2, 1554e8827dSChanwoo Choi S2MPU02_REG_INT3, 1654e8827dSChanwoo Choi S2MPU02_REG_INT1M, 1754e8827dSChanwoo Choi S2MPU02_REG_INT2M, 1854e8827dSChanwoo Choi S2MPU02_REG_INT3M, 1954e8827dSChanwoo Choi S2MPU02_REG_ST1, 2054e8827dSChanwoo Choi S2MPU02_REG_ST2, 2154e8827dSChanwoo Choi S2MPU02_REG_PWRONSRC, 2254e8827dSChanwoo Choi S2MPU02_REG_OFFSRC, 2354e8827dSChanwoo Choi S2MPU02_REG_BU_CHG, 2454e8827dSChanwoo Choi S2MPU02_REG_RTCCTRL, 2554e8827dSChanwoo Choi S2MPU02_REG_PMCTRL1, 2654e8827dSChanwoo Choi S2MPU02_REG_RSVD1, 2754e8827dSChanwoo Choi S2MPU02_REG_RSVD2, 2854e8827dSChanwoo Choi S2MPU02_REG_RSVD3, 2954e8827dSChanwoo Choi S2MPU02_REG_RSVD4, 3054e8827dSChanwoo Choi S2MPU02_REG_RSVD5, 3154e8827dSChanwoo Choi S2MPU02_REG_RSVD6, 3254e8827dSChanwoo Choi S2MPU02_REG_RSVD7, 3354e8827dSChanwoo Choi S2MPU02_REG_WRSTEN, 3454e8827dSChanwoo Choi S2MPU02_REG_RSVD8, 3554e8827dSChanwoo Choi S2MPU02_REG_RSVD9, 3654e8827dSChanwoo Choi S2MPU02_REG_RSVD10, 3754e8827dSChanwoo Choi S2MPU02_REG_B1CTRL1, 3854e8827dSChanwoo Choi S2MPU02_REG_B1CTRL2, 3954e8827dSChanwoo Choi S2MPU02_REG_B2CTRL1, 4054e8827dSChanwoo Choi S2MPU02_REG_B2CTRL2, 4154e8827dSChanwoo Choi S2MPU02_REG_B3CTRL1, 4254e8827dSChanwoo Choi S2MPU02_REG_B3CTRL2, 4354e8827dSChanwoo Choi S2MPU02_REG_B4CTRL1, 4454e8827dSChanwoo Choi S2MPU02_REG_B4CTRL2, 4554e8827dSChanwoo Choi S2MPU02_REG_B5CTRL1, 4654e8827dSChanwoo Choi S2MPU02_REG_B5CTRL2, 4754e8827dSChanwoo Choi S2MPU02_REG_B5CTRL3, 4854e8827dSChanwoo Choi S2MPU02_REG_B5CTRL4, 4954e8827dSChanwoo Choi S2MPU02_REG_B5CTRL5, 5054e8827dSChanwoo Choi S2MPU02_REG_B6CTRL1, 5154e8827dSChanwoo Choi S2MPU02_REG_B6CTRL2, 5254e8827dSChanwoo Choi S2MPU02_REG_B7CTRL1, 5354e8827dSChanwoo Choi S2MPU02_REG_B7CTRL2, 5454e8827dSChanwoo Choi S2MPU02_REG_RAMP1, 5554e8827dSChanwoo Choi S2MPU02_REG_RAMP2, 5654e8827dSChanwoo Choi S2MPU02_REG_L1CTRL, 5754e8827dSChanwoo Choi S2MPU02_REG_L2CTRL1, 5854e8827dSChanwoo Choi S2MPU02_REG_L2CTRL2, 5954e8827dSChanwoo Choi S2MPU02_REG_L2CTRL3, 6054e8827dSChanwoo Choi S2MPU02_REG_L2CTRL4, 6154e8827dSChanwoo Choi S2MPU02_REG_L3CTRL, 6254e8827dSChanwoo Choi S2MPU02_REG_L4CTRL, 6354e8827dSChanwoo Choi S2MPU02_REG_L5CTRL, 6454e8827dSChanwoo Choi S2MPU02_REG_L6CTRL, 6554e8827dSChanwoo Choi S2MPU02_REG_L7CTRL, 6654e8827dSChanwoo Choi S2MPU02_REG_L8CTRL, 6754e8827dSChanwoo Choi S2MPU02_REG_L9CTRL, 6854e8827dSChanwoo Choi S2MPU02_REG_L10CTRL, 6954e8827dSChanwoo Choi S2MPU02_REG_L11CTRL, 7054e8827dSChanwoo Choi S2MPU02_REG_L12CTRL, 7154e8827dSChanwoo Choi S2MPU02_REG_L13CTRL, 7254e8827dSChanwoo Choi S2MPU02_REG_L14CTRL, 7354e8827dSChanwoo Choi S2MPU02_REG_L15CTRL, 7454e8827dSChanwoo Choi S2MPU02_REG_L16CTRL, 7554e8827dSChanwoo Choi S2MPU02_REG_L17CTRL, 7654e8827dSChanwoo Choi S2MPU02_REG_L18CTRL, 7754e8827dSChanwoo Choi S2MPU02_REG_L19CTRL, 7854e8827dSChanwoo Choi S2MPU02_REG_L20CTRL, 7954e8827dSChanwoo Choi S2MPU02_REG_L21CTRL, 8054e8827dSChanwoo Choi S2MPU02_REG_L22CTRL, 8154e8827dSChanwoo Choi S2MPU02_REG_L23CTRL, 8254e8827dSChanwoo Choi S2MPU02_REG_L24CTRL, 8354e8827dSChanwoo Choi S2MPU02_REG_L25CTRL, 8454e8827dSChanwoo Choi S2MPU02_REG_L26CTRL, 8554e8827dSChanwoo Choi S2MPU02_REG_L27CTRL, 8654e8827dSChanwoo Choi S2MPU02_REG_L28CTRL, 8754e8827dSChanwoo Choi S2MPU02_REG_LDODSCH1, 8854e8827dSChanwoo Choi S2MPU02_REG_LDODSCH2, 8954e8827dSChanwoo Choi S2MPU02_REG_LDODSCH3, 9054e8827dSChanwoo Choi S2MPU02_REG_LDODSCH4, 9154e8827dSChanwoo Choi S2MPU02_REG_SELMIF, 9254e8827dSChanwoo Choi S2MPU02_REG_RSVD11, 9354e8827dSChanwoo Choi S2MPU02_REG_RSVD12, 9454e8827dSChanwoo Choi S2MPU02_REG_RSVD13, 9554e8827dSChanwoo Choi S2MPU02_REG_DVSSEL, 9654e8827dSChanwoo Choi S2MPU02_REG_DVSPTR, 9754e8827dSChanwoo Choi S2MPU02_REG_DVSDATA, 9854e8827dSChanwoo Choi }; 9954e8827dSChanwoo Choi 10054e8827dSChanwoo Choi /* S2MPU02 regulator ids */ 10154e8827dSChanwoo Choi enum S2MPU02_regulators { 10254e8827dSChanwoo Choi S2MPU02_LDO1, 10354e8827dSChanwoo Choi S2MPU02_LDO2, 10454e8827dSChanwoo Choi S2MPU02_LDO3, 10554e8827dSChanwoo Choi S2MPU02_LDO4, 10654e8827dSChanwoo Choi S2MPU02_LDO5, 10754e8827dSChanwoo Choi S2MPU02_LDO6, 10854e8827dSChanwoo Choi S2MPU02_LDO7, 10954e8827dSChanwoo Choi S2MPU02_LDO8, 11054e8827dSChanwoo Choi S2MPU02_LDO9, 11154e8827dSChanwoo Choi S2MPU02_LDO10, 11254e8827dSChanwoo Choi S2MPU02_LDO11, 11354e8827dSChanwoo Choi S2MPU02_LDO12, 11454e8827dSChanwoo Choi S2MPU02_LDO13, 11554e8827dSChanwoo Choi S2MPU02_LDO14, 11654e8827dSChanwoo Choi S2MPU02_LDO15, 11754e8827dSChanwoo Choi S2MPU02_LDO16, 11854e8827dSChanwoo Choi S2MPU02_LDO17, 11954e8827dSChanwoo Choi S2MPU02_LDO18, 12054e8827dSChanwoo Choi S2MPU02_LDO19, 12154e8827dSChanwoo Choi S2MPU02_LDO20, 12254e8827dSChanwoo Choi S2MPU02_LDO21, 12354e8827dSChanwoo Choi S2MPU02_LDO22, 12454e8827dSChanwoo Choi S2MPU02_LDO23, 12554e8827dSChanwoo Choi S2MPU02_LDO24, 12654e8827dSChanwoo Choi S2MPU02_LDO25, 12754e8827dSChanwoo Choi S2MPU02_LDO26, 12854e8827dSChanwoo Choi S2MPU02_LDO27, 12954e8827dSChanwoo Choi S2MPU02_LDO28, 13054e8827dSChanwoo Choi S2MPU02_BUCK1, 13154e8827dSChanwoo Choi S2MPU02_BUCK2, 13254e8827dSChanwoo Choi S2MPU02_BUCK3, 13354e8827dSChanwoo Choi S2MPU02_BUCK4, 13454e8827dSChanwoo Choi S2MPU02_BUCK5, 13554e8827dSChanwoo Choi S2MPU02_BUCK6, 13654e8827dSChanwoo Choi S2MPU02_BUCK7, 13754e8827dSChanwoo Choi 13854e8827dSChanwoo Choi S2MPU02_REGULATOR_MAX, 13954e8827dSChanwoo Choi }; 14054e8827dSChanwoo Choi 14154e8827dSChanwoo Choi /* Regulator constraints for BUCKx */ 14254e8827dSChanwoo Choi #define S2MPU02_BUCK1234_MIN_600MV 600000 14354e8827dSChanwoo Choi #define S2MPU02_BUCK5_MIN_1081_25MV 1081250 14454e8827dSChanwoo Choi #define S2MPU02_BUCK6_MIN_1700MV 1700000 14554e8827dSChanwoo Choi #define S2MPU02_BUCK7_MIN_900MV 900000 14654e8827dSChanwoo Choi 14754e8827dSChanwoo Choi #define S2MPU02_BUCK1234_STEP_6_25MV 6250 14854e8827dSChanwoo Choi #define S2MPU02_BUCK5_STEP_6_25MV 6250 14954e8827dSChanwoo Choi #define S2MPU02_BUCK6_STEP_2_50MV 2500 15054e8827dSChanwoo Choi #define S2MPU02_BUCK7_STEP_6_25MV 6250 15154e8827dSChanwoo Choi 15254e8827dSChanwoo Choi #define S2MPU02_BUCK1234_START_SEL 0x00 15354e8827dSChanwoo Choi #define S2MPU02_BUCK5_START_SEL 0x4D 15454e8827dSChanwoo Choi #define S2MPU02_BUCK6_START_SEL 0x28 15554e8827dSChanwoo Choi #define S2MPU02_BUCK7_START_SEL 0x30 15654e8827dSChanwoo Choi 15754e8827dSChanwoo Choi #define S2MPU02_BUCK_RAMP_DELAY 12500 15854e8827dSChanwoo Choi 15954e8827dSChanwoo Choi /* Regulator constraints for different types of LDOx */ 16054e8827dSChanwoo Choi #define S2MPU02_LDO_MIN_900MV 900000 16154e8827dSChanwoo Choi #define S2MPU02_LDO_MIN_1050MV 1050000 16254e8827dSChanwoo Choi #define S2MPU02_LDO_MIN_1600MV 1600000 16354e8827dSChanwoo Choi #define S2MPU02_LDO_STEP_12_5MV 12500 16454e8827dSChanwoo Choi #define S2MPU02_LDO_STEP_25MV 25000 16554e8827dSChanwoo Choi #define S2MPU02_LDO_STEP_50MV 50000 16654e8827dSChanwoo Choi 16754e8827dSChanwoo Choi #define S2MPU02_LDO_GROUP1_START_SEL 0x8 16854e8827dSChanwoo Choi #define S2MPU02_LDO_GROUP2_START_SEL 0xA 16954e8827dSChanwoo Choi #define S2MPU02_LDO_GROUP3_START_SEL 0x10 17054e8827dSChanwoo Choi 17154e8827dSChanwoo Choi #define S2MPU02_LDO_VSEL_MASK 0x3F 17254e8827dSChanwoo Choi #define S2MPU02_BUCK_VSEL_MASK 0xFF 17354e8827dSChanwoo Choi #define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT) 17454e8827dSChanwoo Choi #define S2MPU02_ENABLE_SHIFT 6 17554e8827dSChanwoo Choi 17654e8827dSChanwoo Choi /* On/Off controlled by PWREN */ 17754e8827dSChanwoo Choi #define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT) 17854e8827dSChanwoo Choi #define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT) 17954e8827dSChanwoo Choi #define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1) 18054e8827dSChanwoo Choi #define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1) 18154e8827dSChanwoo Choi 18254e8827dSChanwoo Choi /* RAMP delay for BUCK1234*/ 18354e8827dSChanwoo Choi #define S2MPU02_BUCK1_RAMP_SHIFT 6 18454e8827dSChanwoo Choi #define S2MPU02_BUCK2_RAMP_SHIFT 4 18554e8827dSChanwoo Choi #define S2MPU02_BUCK3_RAMP_SHIFT 2 18654e8827dSChanwoo Choi #define S2MPU02_BUCK4_RAMP_SHIFT 0 18754e8827dSChanwoo Choi #define S2MPU02_BUCK1234_RAMP_MASK 0x3 18854e8827dSChanwoo Choi 18954e8827dSChanwoo Choi #endif /* __LINUX_MFD_S2MPU02_H */ 190