1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (C) 2018 ROHM Semiconductors */ 3 4 #ifndef __LINUX_MFD_BD71837_H__ 5 #define __LINUX_MFD_BD71837_H__ 6 7 #include <linux/regmap.h> 8 9 enum { 10 BD71837_BUCK1 = 0, 11 BD71837_BUCK2, 12 BD71837_BUCK3, 13 BD71837_BUCK4, 14 BD71837_BUCK5, 15 BD71837_BUCK6, 16 BD71837_BUCK7, 17 BD71837_BUCK8, 18 BD71837_LDO1, 19 BD71837_LDO2, 20 BD71837_LDO3, 21 BD71837_LDO4, 22 BD71837_LDO5, 23 BD71837_LDO6, 24 BD71837_LDO7, 25 BD71837_REGULATOR_CNT, 26 }; 27 28 #define BD71837_BUCK1_VOLTAGE_NUM 0x40 29 #define BD71837_BUCK2_VOLTAGE_NUM 0x40 30 #define BD71837_BUCK3_VOLTAGE_NUM 0x40 31 #define BD71837_BUCK4_VOLTAGE_NUM 0x40 32 33 #define BD71837_BUCK5_VOLTAGE_NUM 0x08 34 #define BD71837_BUCK6_VOLTAGE_NUM 0x04 35 #define BD71837_BUCK7_VOLTAGE_NUM 0x08 36 #define BD71837_BUCK8_VOLTAGE_NUM 0x40 37 38 #define BD71837_LDO1_VOLTAGE_NUM 0x04 39 #define BD71837_LDO2_VOLTAGE_NUM 0x02 40 #define BD71837_LDO3_VOLTAGE_NUM 0x10 41 #define BD71837_LDO4_VOLTAGE_NUM 0x10 42 #define BD71837_LDO5_VOLTAGE_NUM 0x10 43 #define BD71837_LDO6_VOLTAGE_NUM 0x10 44 #define BD71837_LDO7_VOLTAGE_NUM 0x10 45 46 enum { 47 BD71837_REG_REV = 0x00, 48 BD71837_REG_SWRESET = 0x01, 49 BD71837_REG_I2C_DEV = 0x02, 50 BD71837_REG_PWRCTRL0 = 0x03, 51 BD71837_REG_PWRCTRL1 = 0x04, 52 BD71837_REG_BUCK1_CTRL = 0x05, 53 BD71837_REG_BUCK2_CTRL = 0x06, 54 BD71837_REG_BUCK3_CTRL = 0x07, 55 BD71837_REG_BUCK4_CTRL = 0x08, 56 BD71837_REG_BUCK5_CTRL = 0x09, 57 BD71837_REG_BUCK6_CTRL = 0x0A, 58 BD71837_REG_BUCK7_CTRL = 0x0B, 59 BD71837_REG_BUCK8_CTRL = 0x0C, 60 BD71837_REG_BUCK1_VOLT_RUN = 0x0D, 61 BD71837_REG_BUCK1_VOLT_IDLE = 0x0E, 62 BD71837_REG_BUCK1_VOLT_SUSP = 0x0F, 63 BD71837_REG_BUCK2_VOLT_RUN = 0x10, 64 BD71837_REG_BUCK2_VOLT_IDLE = 0x11, 65 BD71837_REG_BUCK3_VOLT_RUN = 0x12, 66 BD71837_REG_BUCK4_VOLT_RUN = 0x13, 67 BD71837_REG_BUCK5_VOLT = 0x14, 68 BD71837_REG_BUCK6_VOLT = 0x15, 69 BD71837_REG_BUCK7_VOLT = 0x16, 70 BD71837_REG_BUCK8_VOLT = 0x17, 71 BD71837_REG_LDO1_VOLT = 0x18, 72 BD71837_REG_LDO2_VOLT = 0x19, 73 BD71837_REG_LDO3_VOLT = 0x1A, 74 BD71837_REG_LDO4_VOLT = 0x1B, 75 BD71837_REG_LDO5_VOLT = 0x1C, 76 BD71837_REG_LDO6_VOLT = 0x1D, 77 BD71837_REG_LDO7_VOLT = 0x1E, 78 BD71837_REG_TRANS_COND0 = 0x1F, 79 BD71837_REG_TRANS_COND1 = 0x20, 80 BD71837_REG_VRFAULTEN = 0x21, 81 BD71837_REG_MVRFLTMASK0 = 0x22, 82 BD71837_REG_MVRFLTMASK1 = 0x23, 83 BD71837_REG_MVRFLTMASK2 = 0x24, 84 BD71837_REG_RCVCFG = 0x25, 85 BD71837_REG_RCVNUM = 0x26, 86 BD71837_REG_PWRONCONFIG0 = 0x27, 87 BD71837_REG_PWRONCONFIG1 = 0x28, 88 BD71837_REG_RESETSRC = 0x29, 89 BD71837_REG_MIRQ = 0x2A, 90 BD71837_REG_IRQ = 0x2B, 91 BD71837_REG_IN_MON = 0x2C, 92 BD71837_REG_POW_STATE = 0x2D, 93 BD71837_REG_OUT32K = 0x2E, 94 BD71837_REG_REGLOCK = 0x2F, 95 BD71837_REG_OTPVER = 0xFF, 96 BD71837_MAX_REGISTER = 0x100, 97 }; 98 99 #define REGLOCK_PWRSEQ 0x1 100 #define REGLOCK_VREG 0x10 101 102 /* Generic BUCK control masks */ 103 #define BD71837_BUCK_SEL 0x02 104 #define BD71837_BUCK_EN 0x01 105 #define BD71837_BUCK_RUN_ON 0x04 106 107 /* Generic LDO masks */ 108 #define BD71837_LDO_SEL 0x80 109 #define BD71837_LDO_EN 0x40 110 111 /* BD71837 BUCK ramp rate CTRL reg bits */ 112 #define BUCK_RAMPRATE_MASK 0xC0 113 #define BUCK_RAMPRATE_10P00MV 0x0 114 #define BUCK_RAMPRATE_5P00MV 0x1 115 #define BUCK_RAMPRATE_2P50MV 0x2 116 #define BUCK_RAMPRATE_1P25MV 0x3 117 118 /* BD71837_REG_BUCK1_VOLT_RUN bits */ 119 #define BUCK1_RUN_MASK 0x3F 120 #define BUCK1_RUN_DEFAULT 0x14 121 122 /* BD71837_REG_BUCK1_VOLT_SUSP bits */ 123 #define BUCK1_SUSP_MASK 0x3F 124 #define BUCK1_SUSP_DEFAULT 0x14 125 126 /* BD71837_REG_BUCK1_VOLT_IDLE bits */ 127 #define BUCK1_IDLE_MASK 0x3F 128 #define BUCK1_IDLE_DEFAULT 0x14 129 130 /* BD71837_REG_BUCK2_VOLT_RUN bits */ 131 #define BUCK2_RUN_MASK 0x3F 132 #define BUCK2_RUN_DEFAULT 0x1E 133 134 /* BD71837_REG_BUCK2_VOLT_IDLE bits */ 135 #define BUCK2_IDLE_MASK 0x3F 136 #define BUCK2_IDLE_DEFAULT 0x14 137 138 /* BD71837_REG_BUCK3_VOLT_RUN bits */ 139 #define BUCK3_RUN_MASK 0x3F 140 #define BUCK3_RUN_DEFAULT 0x1E 141 142 /* BD71837_REG_BUCK4_VOLT_RUN bits */ 143 #define BUCK4_RUN_MASK 0x3F 144 #define BUCK4_RUN_DEFAULT 0x1E 145 146 /* BD71837_REG_BUCK5_VOLT bits */ 147 #define BUCK5_MASK 0x07 148 #define BUCK5_DEFAULT 0x02 149 150 /* BD71837_REG_BUCK6_VOLT bits */ 151 #define BUCK6_MASK 0x03 152 #define BUCK6_DEFAULT 0x03 153 154 /* BD71837_REG_BUCK7_VOLT bits */ 155 #define BUCK7_MASK 0x07 156 #define BUCK7_DEFAULT 0x03 157 158 /* BD71837_REG_BUCK8_VOLT bits */ 159 #define BUCK8_MASK 0x3F 160 #define BUCK8_DEFAULT 0x1E 161 162 /* BD71837_REG_IRQ bits */ 163 #define IRQ_SWRST 0x40 164 #define IRQ_PWRON_S 0x20 165 #define IRQ_PWRON_L 0x10 166 #define IRQ_PWRON 0x08 167 #define IRQ_WDOG 0x04 168 #define IRQ_ON_REQ 0x02 169 #define IRQ_STBY_REQ 0x01 170 171 /* BD71837_REG_OUT32K bits */ 172 #define BD71837_OUT32K_EN 0x01 173 174 /* BD71837 gated clock rate */ 175 #define BD71837_CLK_RATE 32768 176 177 /* ROHM BD71837 irqs */ 178 enum { 179 BD71837_INT_STBY_REQ, 180 BD71837_INT_ON_REQ, 181 BD71837_INT_WDOG, 182 BD71837_INT_PWRBTN, 183 BD71837_INT_PWRBTN_L, 184 BD71837_INT_PWRBTN_S, 185 BD71837_INT_SWRST 186 }; 187 188 /* ROHM BD71837 interrupt masks */ 189 #define BD71837_INT_SWRST_MASK 0x40 190 #define BD71837_INT_PWRBTN_S_MASK 0x20 191 #define BD71837_INT_PWRBTN_L_MASK 0x10 192 #define BD71837_INT_PWRBTN_MASK 0x8 193 #define BD71837_INT_WDOG_MASK 0x4 194 #define BD71837_INT_ON_REQ_MASK 0x2 195 #define BD71837_INT_STBY_REQ_MASK 0x1 196 197 /* BD71837_REG_LDO1_VOLT bits */ 198 #define LDO1_MASK 0x03 199 200 /* BD71837_REG_LDO1_VOLT bits */ 201 #define LDO2_MASK 0x20 202 203 /* BD71837_REG_LDO3_VOLT bits */ 204 #define LDO3_MASK 0x0F 205 206 /* BD71837_REG_LDO4_VOLT bits */ 207 #define LDO4_MASK 0x0F 208 209 /* BD71837_REG_LDO5_VOLT bits */ 210 #define LDO5_MASK 0x0F 211 212 /* BD71837_REG_LDO6_VOLT bits */ 213 #define LDO6_MASK 0x0F 214 215 /* BD71837_REG_LDO7_VOLT bits */ 216 #define LDO7_MASK 0x0F 217 218 /* Register write induced reset settings */ 219 220 /* 221 * Even though the bit zero is not SWRESET type we still want to write zero 222 * to it when changing type. Bit zero is 'SWRESET' trigger bit and if we 223 * write 1 to it we will trigger the action. So always write 0 to it when 224 * changning SWRESET action - no matter what we read from it. 225 */ 226 #define BD71837_SWRESET_TYPE_MASK 7 227 #define BD71837_SWRESET_TYPE_DISABLED 0 228 #define BD71837_SWRESET_TYPE_COLD 4 229 #define BD71837_SWRESET_TYPE_WARM 6 230 231 #define BD71837_SWRESET_RESET_MASK 1 232 #define BD71837_SWRESET_RESET 1 233 234 /* Poweroff state transition conditions */ 235 236 #define BD718XX_ON_REQ_POWEROFF_MASK 1 237 #define BD718XX_SWRESET_POWEROFF_MASK 2 238 #define BD718XX_WDOG_POWEROFF_MASK 4 239 #define BD718XX_KEY_L_POWEROFF_MASK 8 240 241 #define BD718XX_POWOFF_TO_SNVS 0 242 #define BD718XX_POWOFF_TO_RDY 0xF 243 244 #define BD718XX_POWOFF_TIME_MASK 0xF0 245 enum { 246 BD718XX_POWOFF_TIME_5MS = 0, 247 BD718XX_POWOFF_TIME_10MS, 248 BD718XX_POWOFF_TIME_15MS, 249 BD718XX_POWOFF_TIME_20MS, 250 BD718XX_POWOFF_TIME_25MS, 251 BD718XX_POWOFF_TIME_30MS, 252 BD718XX_POWOFF_TIME_35MS, 253 BD718XX_POWOFF_TIME_40MS, 254 BD718XX_POWOFF_TIME_45MS, 255 BD718XX_POWOFF_TIME_50MS, 256 BD718XX_POWOFF_TIME_75MS, 257 BD718XX_POWOFF_TIME_100MS, 258 BD718XX_POWOFF_TIME_250MS, 259 BD718XX_POWOFF_TIME_500MS, 260 BD718XX_POWOFF_TIME_750MS, 261 BD718XX_POWOFF_TIME_1500MS 262 }; 263 264 /* Poweron sequence state transition conditions */ 265 #define BD718XX_RDY_TO_SNVS_MASK 0xF 266 #define BD718XX_SNVS_TO_RUN_MASK 0xF0 267 268 #define BD718XX_PWR_TRIG_KEY_L 1 269 #define BD718XX_PWR_TRIG_KEY_S 2 270 #define BD718XX_PWR_TRIG_PMIC_ON 4 271 #define BD718XX_PWR_TRIG_VSYS_UVLO 8 272 #define BD718XX_RDY_TO_SNVS_SIFT 0 273 #define BD718XX_SNVS_TO_RUN_SIFT 4 274 275 #define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF 276 277 /* Timeout value for detecting short press */ 278 enum { 279 BD718XX_PWRBTN_SHORT_PRESS_10MS = 0, 280 BD718XX_PWRBTN_SHORT_PRESS_500MS, 281 BD718XX_PWRBTN_SHORT_PRESS_1000MS, 282 BD718XX_PWRBTN_SHORT_PRESS_1500MS, 283 BD718XX_PWRBTN_SHORT_PRESS_2000MS, 284 BD718XX_PWRBTN_SHORT_PRESS_2500MS, 285 BD718XX_PWRBTN_SHORT_PRESS_3000MS, 286 BD718XX_PWRBTN_SHORT_PRESS_3500MS, 287 BD718XX_PWRBTN_SHORT_PRESS_4000MS, 288 BD718XX_PWRBTN_SHORT_PRESS_4500MS, 289 BD718XX_PWRBTN_SHORT_PRESS_5000MS, 290 BD718XX_PWRBTN_SHORT_PRESS_5500MS, 291 BD718XX_PWRBTN_SHORT_PRESS_6000MS, 292 BD718XX_PWRBTN_SHORT_PRESS_6500MS, 293 BD718XX_PWRBTN_SHORT_PRESS_7000MS, 294 BD718XX_PWRBTN_SHORT_PRESS_7500MS 295 }; 296 297 /* Timeout value for detecting LONG press */ 298 enum { 299 BD718XX_PWRBTN_LONG_PRESS_10MS = 0, 300 BD718XX_PWRBTN_LONG_PRESS_1S, 301 BD718XX_PWRBTN_LONG_PRESS_2S, 302 BD718XX_PWRBTN_LONG_PRESS_3S, 303 BD718XX_PWRBTN_LONG_PRESS_4S, 304 BD718XX_PWRBTN_LONG_PRESS_5S, 305 BD718XX_PWRBTN_LONG_PRESS_6S, 306 BD718XX_PWRBTN_LONG_PRESS_7S, 307 BD718XX_PWRBTN_LONG_PRESS_8S, 308 BD718XX_PWRBTN_LONG_PRESS_9S, 309 BD718XX_PWRBTN_LONG_PRESS_10S, 310 BD718XX_PWRBTN_LONG_PRESS_11S, 311 BD718XX_PWRBTN_LONG_PRESS_12S, 312 BD718XX_PWRBTN_LONG_PRESS_13S, 313 BD718XX_PWRBTN_LONG_PRESS_14S, 314 BD718XX_PWRBTN_LONG_PRESS_15S 315 }; 316 317 struct bd71837_pmic; 318 struct bd71837_clk; 319 320 struct bd71837 { 321 struct device *dev; 322 struct regmap *regmap; 323 unsigned long int id; 324 325 int chip_irq; 326 struct regmap_irq_chip_data *irq_data; 327 328 struct bd71837_pmic *pmic; 329 struct bd71837_clk *clk; 330 }; 331 332 #endif /* __LINUX_MFD_BD71837_H__ */ 333