1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (C) 2018 ROHM Semiconductors */ 3 4 #ifndef __LINUX_MFD_BD71837_H__ 5 #define __LINUX_MFD_BD71837_H__ 6 7 #include <linux/regmap.h> 8 9 enum { 10 BD71837_BUCK1 = 0, 11 BD71837_BUCK2, 12 BD71837_BUCK3, 13 BD71837_BUCK4, 14 BD71837_BUCK5, 15 BD71837_BUCK6, 16 BD71837_BUCK7, 17 BD71837_BUCK8, 18 BD71837_LDO1, 19 BD71837_LDO2, 20 BD71837_LDO3, 21 BD71837_LDO4, 22 BD71837_LDO5, 23 BD71837_LDO6, 24 BD71837_LDO7, 25 BD71837_REGULATOR_CNT, 26 }; 27 28 #define BD71837_BUCK1_VOLTAGE_NUM 0x40 29 #define BD71837_BUCK2_VOLTAGE_NUM 0x40 30 #define BD71837_BUCK3_VOLTAGE_NUM 0x40 31 #define BD71837_BUCK4_VOLTAGE_NUM 0x40 32 33 #define BD71837_BUCK5_VOLTAGE_NUM 0x08 34 #define BD71837_BUCK6_VOLTAGE_NUM 0x04 35 #define BD71837_BUCK7_VOLTAGE_NUM 0x08 36 #define BD71837_BUCK8_VOLTAGE_NUM 0x40 37 38 #define BD71837_LDO1_VOLTAGE_NUM 0x04 39 #define BD71837_LDO2_VOLTAGE_NUM 0x02 40 #define BD71837_LDO3_VOLTAGE_NUM 0x10 41 #define BD71837_LDO4_VOLTAGE_NUM 0x10 42 #define BD71837_LDO5_VOLTAGE_NUM 0x10 43 #define BD71837_LDO6_VOLTAGE_NUM 0x10 44 #define BD71837_LDO7_VOLTAGE_NUM 0x10 45 46 enum { 47 BD71837_REG_REV = 0x00, 48 BD71837_REG_SWRESET = 0x01, 49 BD71837_REG_I2C_DEV = 0x02, 50 BD71837_REG_PWRCTRL0 = 0x03, 51 BD71837_REG_PWRCTRL1 = 0x04, 52 BD71837_REG_BUCK1_CTRL = 0x05, 53 BD71837_REG_BUCK2_CTRL = 0x06, 54 BD71837_REG_BUCK3_CTRL = 0x07, 55 BD71837_REG_BUCK4_CTRL = 0x08, 56 BD71837_REG_BUCK5_CTRL = 0x09, 57 BD71837_REG_BUCK6_CTRL = 0x0A, 58 BD71837_REG_BUCK7_CTRL = 0x0B, 59 BD71837_REG_BUCK8_CTRL = 0x0C, 60 BD71837_REG_BUCK1_VOLT_RUN = 0x0D, 61 BD71837_REG_BUCK1_VOLT_IDLE = 0x0E, 62 BD71837_REG_BUCK1_VOLT_SUSP = 0x0F, 63 BD71837_REG_BUCK2_VOLT_RUN = 0x10, 64 BD71837_REG_BUCK2_VOLT_IDLE = 0x11, 65 BD71837_REG_BUCK3_VOLT_RUN = 0x12, 66 BD71837_REG_BUCK4_VOLT_RUN = 0x13, 67 BD71837_REG_BUCK5_VOLT = 0x14, 68 BD71837_REG_BUCK6_VOLT = 0x15, 69 BD71837_REG_BUCK7_VOLT = 0x16, 70 BD71837_REG_BUCK8_VOLT = 0x17, 71 BD71837_REG_LDO1_VOLT = 0x18, 72 BD71837_REG_LDO2_VOLT = 0x19, 73 BD71837_REG_LDO3_VOLT = 0x1A, 74 BD71837_REG_LDO4_VOLT = 0x1B, 75 BD71837_REG_LDO5_VOLT = 0x1C, 76 BD71837_REG_LDO6_VOLT = 0x1D, 77 BD71837_REG_LDO7_VOLT = 0x1E, 78 BD71837_REG_TRANS_COND0 = 0x1F, 79 BD71837_REG_TRANS_COND1 = 0x20, 80 BD71837_REG_VRFAULTEN = 0x21, 81 BD718XX_REG_MVRFLTMASK0 = 0x22, 82 BD718XX_REG_MVRFLTMASK1 = 0x23, 83 BD718XX_REG_MVRFLTMASK2 = 0x24, 84 BD71837_REG_RCVCFG = 0x25, 85 BD71837_REG_RCVNUM = 0x26, 86 BD71837_REG_PWRONCONFIG0 = 0x27, 87 BD71837_REG_PWRONCONFIG1 = 0x28, 88 BD71837_REG_RESETSRC = 0x29, 89 BD71837_REG_MIRQ = 0x2A, 90 BD71837_REG_IRQ = 0x2B, 91 BD71837_REG_IN_MON = 0x2C, 92 BD71837_REG_POW_STATE = 0x2D, 93 BD71837_REG_OUT32K = 0x2E, 94 BD71837_REG_REGLOCK = 0x2F, 95 BD71837_REG_OTPVER = 0xFF, 96 BD71837_MAX_REGISTER = 0x100, 97 }; 98 99 #define REGLOCK_PWRSEQ 0x1 100 #define REGLOCK_VREG 0x10 101 102 /* Generic BUCK control masks */ 103 #define BD71837_BUCK_SEL 0x02 104 #define BD71837_BUCK_EN 0x01 105 #define BD71837_BUCK_RUN_ON 0x04 106 107 /* Generic LDO masks */ 108 #define BD71837_LDO_SEL 0x80 109 #define BD71837_LDO_EN 0x40 110 111 /* BD71837 BUCK ramp rate CTRL reg bits */ 112 #define BUCK_RAMPRATE_MASK 0xC0 113 #define BUCK_RAMPRATE_10P00MV 0x0 114 #define BUCK_RAMPRATE_5P00MV 0x1 115 #define BUCK_RAMPRATE_2P50MV 0x2 116 #define BUCK_RAMPRATE_1P25MV 0x3 117 118 /* BD71837_REG_BUCK1_VOLT_RUN bits */ 119 #define BUCK1_RUN_MASK 0x3F 120 #define BUCK1_RUN_DEFAULT 0x14 121 122 /* BD71837_REG_BUCK1_VOLT_SUSP bits */ 123 #define BUCK1_SUSP_MASK 0x3F 124 #define BUCK1_SUSP_DEFAULT 0x14 125 126 /* BD71837_REG_BUCK1_VOLT_IDLE bits */ 127 #define BUCK1_IDLE_MASK 0x3F 128 #define BUCK1_IDLE_DEFAULT 0x14 129 130 /* BD71837_REG_BUCK2_VOLT_RUN bits */ 131 #define BUCK2_RUN_MASK 0x3F 132 #define BUCK2_RUN_DEFAULT 0x1E 133 134 /* BD71837_REG_BUCK2_VOLT_IDLE bits */ 135 #define BUCK2_IDLE_MASK 0x3F 136 #define BUCK2_IDLE_DEFAULT 0x14 137 138 /* BD71837_REG_BUCK3_VOLT_RUN bits */ 139 #define BUCK3_RUN_MASK 0x3F 140 #define BUCK3_RUN_DEFAULT 0x1E 141 142 /* BD71837_REG_BUCK4_VOLT_RUN bits */ 143 #define BUCK4_RUN_MASK 0x3F 144 #define BUCK4_RUN_DEFAULT 0x1E 145 146 /* BD71837_REG_BUCK5_VOLT bits */ 147 #define BUCK5_MASK 0x07 148 #define BUCK5_DEFAULT 0x02 149 150 /* BD71837_REG_BUCK6_VOLT bits */ 151 #define BUCK6_MASK 0x03 152 #define BUCK6_DEFAULT 0x03 153 154 /* BD71837_REG_BUCK7_VOLT bits */ 155 #define BUCK7_MASK 0x07 156 #define BUCK7_DEFAULT 0x03 157 158 /* BD71837_REG_BUCK8_VOLT bits */ 159 #define BUCK8_MASK 0x3F 160 #define BUCK8_DEFAULT 0x1E 161 162 /* BD718XX Voltage monitoring masks */ 163 #define BD718XX_BUCK1_VRMON80 0x1 164 #define BD718XX_BUCK1_VRMON130 0x2 165 #define BD718XX_BUCK2_VRMON80 0x4 166 #define BD718XX_BUCK2_VRMON130 0x8 167 #define BD718XX_1ST_NODVS_BUCK_VRMON80 0x1 168 #define BD718XX_1ST_NODVS_BUCK_VRMON130 0x2 169 #define BD718XX_2ND_NODVS_BUCK_VRMON80 0x4 170 #define BD718XX_2ND_NODVS_BUCK_VRMON130 0x8 171 #define BD718XX_3RD_NODVS_BUCK_VRMON80 0x10 172 #define BD718XX_3RD_NODVS_BUCK_VRMON130 0x20 173 #define BD718XX_4TH_NODVS_BUCK_VRMON80 0x40 174 #define BD718XX_4TH_NODVS_BUCK_VRMON130 0x80 175 #define BD718XX_LDO1_VRMON80 0x1 176 #define BD718XX_LDO2_VRMON80 0x2 177 #define BD718XX_LDO3_VRMON80 0x4 178 #define BD718XX_LDO4_VRMON80 0x8 179 #define BD718XX_LDO5_VRMON80 0x10 180 #define BD718XX_LDO6_VRMON80 0x20 181 182 /* BD71837 specific voltage monitoring masks */ 183 #define BD71837_BUCK3_VRMON80 0x10 184 #define BD71837_BUCK3_VRMON130 0x20 185 #define BD71837_BUCK4_VRMON80 0x40 186 #define BD71837_BUCK4_VRMON130 0x80 187 #define BD71837_LDO7_VRMON80 0x40 188 189 /* BD71837_REG_IRQ bits */ 190 #define IRQ_SWRST 0x40 191 #define IRQ_PWRON_S 0x20 192 #define IRQ_PWRON_L 0x10 193 #define IRQ_PWRON 0x08 194 #define IRQ_WDOG 0x04 195 #define IRQ_ON_REQ 0x02 196 #define IRQ_STBY_REQ 0x01 197 198 /* BD71837_REG_OUT32K bits */ 199 #define BD71837_OUT32K_EN 0x01 200 201 /* BD71837 gated clock rate */ 202 #define BD71837_CLK_RATE 32768 203 204 /* ROHM BD71837 irqs */ 205 enum { 206 BD71837_INT_STBY_REQ, 207 BD71837_INT_ON_REQ, 208 BD71837_INT_WDOG, 209 BD71837_INT_PWRBTN, 210 BD71837_INT_PWRBTN_L, 211 BD71837_INT_PWRBTN_S, 212 BD71837_INT_SWRST 213 }; 214 215 /* ROHM BD71837 interrupt masks */ 216 #define BD71837_INT_SWRST_MASK 0x40 217 #define BD71837_INT_PWRBTN_S_MASK 0x20 218 #define BD71837_INT_PWRBTN_L_MASK 0x10 219 #define BD71837_INT_PWRBTN_MASK 0x8 220 #define BD71837_INT_WDOG_MASK 0x4 221 #define BD71837_INT_ON_REQ_MASK 0x2 222 #define BD71837_INT_STBY_REQ_MASK 0x1 223 224 /* BD71837_REG_LDO1_VOLT bits */ 225 #define LDO1_MASK 0x03 226 227 /* BD71837_REG_LDO1_VOLT bits */ 228 #define LDO2_MASK 0x20 229 230 /* BD71837_REG_LDO3_VOLT bits */ 231 #define LDO3_MASK 0x0F 232 233 /* BD71837_REG_LDO4_VOLT bits */ 234 #define LDO4_MASK 0x0F 235 236 /* BD71837_REG_LDO5_VOLT bits */ 237 #define LDO5_MASK 0x0F 238 239 /* BD71837_REG_LDO6_VOLT bits */ 240 #define LDO6_MASK 0x0F 241 242 /* BD71837_REG_LDO7_VOLT bits */ 243 #define LDO7_MASK 0x0F 244 245 /* Register write induced reset settings */ 246 247 /* 248 * Even though the bit zero is not SWRESET type we still want to write zero 249 * to it when changing type. Bit zero is 'SWRESET' trigger bit and if we 250 * write 1 to it we will trigger the action. So always write 0 to it when 251 * changning SWRESET action - no matter what we read from it. 252 */ 253 #define BD71837_SWRESET_TYPE_MASK 7 254 #define BD71837_SWRESET_TYPE_DISABLED 0 255 #define BD71837_SWRESET_TYPE_COLD 4 256 #define BD71837_SWRESET_TYPE_WARM 6 257 258 #define BD71837_SWRESET_RESET_MASK 1 259 #define BD71837_SWRESET_RESET 1 260 261 /* Poweroff state transition conditions */ 262 263 #define BD718XX_ON_REQ_POWEROFF_MASK 1 264 #define BD718XX_SWRESET_POWEROFF_MASK 2 265 #define BD718XX_WDOG_POWEROFF_MASK 4 266 #define BD718XX_KEY_L_POWEROFF_MASK 8 267 268 #define BD718XX_POWOFF_TO_SNVS 0 269 #define BD718XX_POWOFF_TO_RDY 0xF 270 271 #define BD718XX_POWOFF_TIME_MASK 0xF0 272 enum { 273 BD718XX_POWOFF_TIME_5MS = 0, 274 BD718XX_POWOFF_TIME_10MS, 275 BD718XX_POWOFF_TIME_15MS, 276 BD718XX_POWOFF_TIME_20MS, 277 BD718XX_POWOFF_TIME_25MS, 278 BD718XX_POWOFF_TIME_30MS, 279 BD718XX_POWOFF_TIME_35MS, 280 BD718XX_POWOFF_TIME_40MS, 281 BD718XX_POWOFF_TIME_45MS, 282 BD718XX_POWOFF_TIME_50MS, 283 BD718XX_POWOFF_TIME_75MS, 284 BD718XX_POWOFF_TIME_100MS, 285 BD718XX_POWOFF_TIME_250MS, 286 BD718XX_POWOFF_TIME_500MS, 287 BD718XX_POWOFF_TIME_750MS, 288 BD718XX_POWOFF_TIME_1500MS 289 }; 290 291 /* Poweron sequence state transition conditions */ 292 #define BD718XX_RDY_TO_SNVS_MASK 0xF 293 #define BD718XX_SNVS_TO_RUN_MASK 0xF0 294 295 #define BD718XX_PWR_TRIG_KEY_L 1 296 #define BD718XX_PWR_TRIG_KEY_S 2 297 #define BD718XX_PWR_TRIG_PMIC_ON 4 298 #define BD718XX_PWR_TRIG_VSYS_UVLO 8 299 #define BD718XX_RDY_TO_SNVS_SIFT 0 300 #define BD718XX_SNVS_TO_RUN_SIFT 4 301 302 #define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF 303 304 /* Timeout value for detecting short press */ 305 enum { 306 BD718XX_PWRBTN_SHORT_PRESS_10MS = 0, 307 BD718XX_PWRBTN_SHORT_PRESS_500MS, 308 BD718XX_PWRBTN_SHORT_PRESS_1000MS, 309 BD718XX_PWRBTN_SHORT_PRESS_1500MS, 310 BD718XX_PWRBTN_SHORT_PRESS_2000MS, 311 BD718XX_PWRBTN_SHORT_PRESS_2500MS, 312 BD718XX_PWRBTN_SHORT_PRESS_3000MS, 313 BD718XX_PWRBTN_SHORT_PRESS_3500MS, 314 BD718XX_PWRBTN_SHORT_PRESS_4000MS, 315 BD718XX_PWRBTN_SHORT_PRESS_4500MS, 316 BD718XX_PWRBTN_SHORT_PRESS_5000MS, 317 BD718XX_PWRBTN_SHORT_PRESS_5500MS, 318 BD718XX_PWRBTN_SHORT_PRESS_6000MS, 319 BD718XX_PWRBTN_SHORT_PRESS_6500MS, 320 BD718XX_PWRBTN_SHORT_PRESS_7000MS, 321 BD718XX_PWRBTN_SHORT_PRESS_7500MS 322 }; 323 324 /* Timeout value for detecting LONG press */ 325 enum { 326 BD718XX_PWRBTN_LONG_PRESS_10MS = 0, 327 BD718XX_PWRBTN_LONG_PRESS_1S, 328 BD718XX_PWRBTN_LONG_PRESS_2S, 329 BD718XX_PWRBTN_LONG_PRESS_3S, 330 BD718XX_PWRBTN_LONG_PRESS_4S, 331 BD718XX_PWRBTN_LONG_PRESS_5S, 332 BD718XX_PWRBTN_LONG_PRESS_6S, 333 BD718XX_PWRBTN_LONG_PRESS_7S, 334 BD718XX_PWRBTN_LONG_PRESS_8S, 335 BD718XX_PWRBTN_LONG_PRESS_9S, 336 BD718XX_PWRBTN_LONG_PRESS_10S, 337 BD718XX_PWRBTN_LONG_PRESS_11S, 338 BD718XX_PWRBTN_LONG_PRESS_12S, 339 BD718XX_PWRBTN_LONG_PRESS_13S, 340 BD718XX_PWRBTN_LONG_PRESS_14S, 341 BD718XX_PWRBTN_LONG_PRESS_15S 342 }; 343 344 struct bd71837_pmic; 345 struct bd71837_clk; 346 347 struct bd71837 { 348 struct device *dev; 349 struct regmap *regmap; 350 unsigned long int id; 351 352 int chip_irq; 353 struct regmap_irq_chip_data *irq_data; 354 355 struct bd71837_pmic *pmic; 356 struct bd71837_clk *clk; 357 }; 358 359 #endif /* __LINUX_MFD_BD71837_H__ */ 360