1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (C) 2018 ROHM Semiconductors */ 3 4 #ifndef __LINUX_MFD_BD718XX_H__ 5 #define __LINUX_MFD_BD718XX_H__ 6 7 #include <linux/regmap.h> 8 9 enum { 10 BD718XX_TYPE_BD71837 = 0, 11 BD718XX_TYPE_BD71847, 12 BD718XX_TYPE_AMOUNT 13 }; 14 15 enum { 16 BD718XX_BUCK1 = 0, 17 BD718XX_BUCK2, 18 BD718XX_BUCK3, 19 BD718XX_BUCK4, 20 BD718XX_BUCK5, 21 BD718XX_BUCK6, 22 BD718XX_BUCK7, 23 BD718XX_BUCK8, 24 BD718XX_LDO1, 25 BD718XX_LDO2, 26 BD718XX_LDO3, 27 BD718XX_LDO4, 28 BD718XX_LDO5, 29 BD718XX_LDO6, 30 BD718XX_LDO7, 31 BD718XX_REGULATOR_AMOUNT, 32 }; 33 34 /* Common voltage configurations */ 35 #define BD718XX_DVS_BUCK_VOLTAGE_NUM 0x3D 36 #define BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM 0x3D 37 38 #define BD718XX_LDO1_VOLTAGE_NUM 0x08 39 #define BD718XX_LDO2_VOLTAGE_NUM 0x02 40 #define BD718XX_LDO3_VOLTAGE_NUM 0x10 41 #define BD718XX_LDO4_VOLTAGE_NUM 0x0A 42 #define BD718XX_LDO6_VOLTAGE_NUM 0x0A 43 44 /* BD71837 specific voltage configurations */ 45 #define BD71837_BUCK5_VOLTAGE_NUM 0x10 46 #define BD71837_BUCK6_VOLTAGE_NUM 0x04 47 #define BD71837_BUCK7_VOLTAGE_NUM 0x08 48 #define BD71837_LDO5_VOLTAGE_NUM 0x10 49 #define BD71837_LDO7_VOLTAGE_NUM 0x10 50 51 /* BD71847 specific voltage configurations */ 52 #define BD71847_BUCK3_VOLTAGE_NUM 0x18 53 #define BD71847_BUCK4_VOLTAGE_NUM 0x08 54 #define BD71847_LDO5_VOLTAGE_NUM 0x20 55 56 /* Registers specific to BD71837 */ 57 enum { 58 BD71837_REG_BUCK3_CTRL = 0x07, 59 BD71837_REG_BUCK4_CTRL = 0x08, 60 BD71837_REG_BUCK3_VOLT_RUN = 0x12, 61 BD71837_REG_BUCK4_VOLT_RUN = 0x13, 62 BD71837_REG_LDO7_VOLT = 0x1E, 63 }; 64 65 /* Registers common for BD71837 and BD71847 */ 66 enum { 67 BD718XX_REG_REV = 0x00, 68 BD718XX_REG_SWRESET = 0x01, 69 BD718XX_REG_I2C_DEV = 0x02, 70 BD718XX_REG_PWRCTRL0 = 0x03, 71 BD718XX_REG_PWRCTRL1 = 0x04, 72 BD718XX_REG_BUCK1_CTRL = 0x05, 73 BD718XX_REG_BUCK2_CTRL = 0x06, 74 BD718XX_REG_1ST_NODVS_BUCK_CTRL = 0x09, 75 BD718XX_REG_2ND_NODVS_BUCK_CTRL = 0x0A, 76 BD718XX_REG_3RD_NODVS_BUCK_CTRL = 0x0B, 77 BD718XX_REG_4TH_NODVS_BUCK_CTRL = 0x0C, 78 BD718XX_REG_BUCK1_VOLT_RUN = 0x0D, 79 BD718XX_REG_BUCK1_VOLT_IDLE = 0x0E, 80 BD718XX_REG_BUCK1_VOLT_SUSP = 0x0F, 81 BD718XX_REG_BUCK2_VOLT_RUN = 0x10, 82 BD718XX_REG_BUCK2_VOLT_IDLE = 0x11, 83 BD718XX_REG_1ST_NODVS_BUCK_VOLT = 0x14, 84 BD718XX_REG_2ND_NODVS_BUCK_VOLT = 0x15, 85 BD718XX_REG_3RD_NODVS_BUCK_VOLT = 0x16, 86 BD718XX_REG_4TH_NODVS_BUCK_VOLT = 0x17, 87 BD718XX_REG_LDO1_VOLT = 0x18, 88 BD718XX_REG_LDO2_VOLT = 0x19, 89 BD718XX_REG_LDO3_VOLT = 0x1A, 90 BD718XX_REG_LDO4_VOLT = 0x1B, 91 BD718XX_REG_LDO5_VOLT = 0x1C, 92 BD718XX_REG_LDO6_VOLT = 0x1D, 93 BD718XX_REG_TRANS_COND0 = 0x1F, 94 BD718XX_REG_TRANS_COND1 = 0x20, 95 BD718XX_REG_VRFAULTEN = 0x21, 96 BD718XX_REG_MVRFLTMASK0 = 0x22, 97 BD718XX_REG_MVRFLTMASK1 = 0x23, 98 BD718XX_REG_MVRFLTMASK2 = 0x24, 99 BD718XX_REG_RCVCFG = 0x25, 100 BD718XX_REG_RCVNUM = 0x26, 101 BD718XX_REG_PWRONCONFIG0 = 0x27, 102 BD718XX_REG_PWRONCONFIG1 = 0x28, 103 BD718XX_REG_RESETSRC = 0x29, 104 BD718XX_REG_MIRQ = 0x2A, 105 BD718XX_REG_IRQ = 0x2B, 106 BD718XX_REG_IN_MON = 0x2C, 107 BD718XX_REG_POW_STATE = 0x2D, 108 BD718XX_REG_OUT32K = 0x2E, 109 BD718XX_REG_REGLOCK = 0x2F, 110 BD718XX_REG_OTPVER = 0xFF, 111 BD718XX_MAX_REGISTER = 0x100, 112 }; 113 114 #define REGLOCK_PWRSEQ 0x1 115 #define REGLOCK_VREG 0x10 116 117 /* Generic BUCK control masks */ 118 #define BD718XX_BUCK_SEL 0x02 119 #define BD718XX_BUCK_EN 0x01 120 #define BD718XX_BUCK_RUN_ON 0x04 121 122 /* Generic LDO masks */ 123 #define BD718XX_LDO_SEL 0x80 124 #define BD718XX_LDO_EN 0x40 125 126 /* BD71837 BUCK ramp rate CTRL reg bits */ 127 #define BUCK_RAMPRATE_MASK 0xC0 128 #define BUCK_RAMPRATE_10P00MV 0x0 129 #define BUCK_RAMPRATE_5P00MV 0x1 130 #define BUCK_RAMPRATE_2P50MV 0x2 131 #define BUCK_RAMPRATE_1P25MV 0x3 132 133 #define DVS_BUCK_RUN_MASK 0x3F 134 #define DVS_BUCK_SUSP_MASK 0x3F 135 #define DVS_BUCK_IDLE_MASK 0x3F 136 137 #define BD718XX_1ST_NODVS_BUCK_MASK 0x07 138 #define BD718XX_3RD_NODVS_BUCK_MASK 0x07 139 #define BD718XX_4TH_NODVS_BUCK_MASK 0x3F 140 141 #define BD71847_BUCK3_MASK 0x07 142 #define BD71847_BUCK3_RANGE_MASK 0xC0 143 #define BD71847_BUCK4_MASK 0x03 144 #define BD71847_BUCK4_RANGE_MASK 0x40 145 146 #define BD71837_BUCK5_MASK 0x07 147 #define BD71837_BUCK5_RANGE_MASK 0x80 148 #define BD71837_BUCK6_MASK 0x03 149 150 #define BD718XX_LDO1_MASK 0x03 151 #define BD718XX_LDO1_RANGE_MASK 0x20 152 #define BD718XX_LDO2_MASK 0x20 153 #define BD718XX_LDO3_MASK 0x0F 154 #define BD718XX_LDO4_MASK 0x0F 155 #define BD718XX_LDO6_MASK 0x0F 156 157 #define BD71837_LDO5_MASK 0x0F 158 #define BD71847_LDO5_MASK 0x0F 159 #define BD71847_LDO5_RANGE_MASK 0x20 160 161 #define BD71837_LDO7_MASK 0x0F 162 163 /* BD718XX Voltage monitoring masks */ 164 #define BD718XX_BUCK1_VRMON80 0x1 165 #define BD718XX_BUCK1_VRMON130 0x2 166 #define BD718XX_BUCK2_VRMON80 0x4 167 #define BD718XX_BUCK2_VRMON130 0x8 168 #define BD718XX_1ST_NODVS_BUCK_VRMON80 0x1 169 #define BD718XX_1ST_NODVS_BUCK_VRMON130 0x2 170 #define BD718XX_2ND_NODVS_BUCK_VRMON80 0x4 171 #define BD718XX_2ND_NODVS_BUCK_VRMON130 0x8 172 #define BD718XX_3RD_NODVS_BUCK_VRMON80 0x10 173 #define BD718XX_3RD_NODVS_BUCK_VRMON130 0x20 174 #define BD718XX_4TH_NODVS_BUCK_VRMON80 0x40 175 #define BD718XX_4TH_NODVS_BUCK_VRMON130 0x80 176 #define BD718XX_LDO1_VRMON80 0x1 177 #define BD718XX_LDO2_VRMON80 0x2 178 #define BD718XX_LDO3_VRMON80 0x4 179 #define BD718XX_LDO4_VRMON80 0x8 180 #define BD718XX_LDO5_VRMON80 0x10 181 #define BD718XX_LDO6_VRMON80 0x20 182 183 /* BD71837 specific voltage monitoring masks */ 184 #define BD71837_BUCK3_VRMON80 0x10 185 #define BD71837_BUCK3_VRMON130 0x20 186 #define BD71837_BUCK4_VRMON80 0x40 187 #define BD71837_BUCK4_VRMON130 0x80 188 #define BD71837_LDO7_VRMON80 0x40 189 190 /* BD718XX_REG_IRQ bits */ 191 #define IRQ_SWRST 0x40 192 #define IRQ_PWRON_S 0x20 193 #define IRQ_PWRON_L 0x10 194 #define IRQ_PWRON 0x08 195 #define IRQ_WDOG 0x04 196 #define IRQ_ON_REQ 0x02 197 #define IRQ_STBY_REQ 0x01 198 199 /* BD718XX_REG_OUT32K bits */ 200 #define BD718XX_OUT32K_EN 0x01 201 202 /* BD7183XX gated clock rate */ 203 #define BD718XX_CLK_RATE 32768 204 205 /* ROHM BD718XX irqs */ 206 enum { 207 BD718XX_INT_STBY_REQ, 208 BD718XX_INT_ON_REQ, 209 BD718XX_INT_WDOG, 210 BD718XX_INT_PWRBTN, 211 BD718XX_INT_PWRBTN_L, 212 BD718XX_INT_PWRBTN_S, 213 BD718XX_INT_SWRST 214 }; 215 216 /* ROHM BD718XX interrupt masks */ 217 #define BD718XX_INT_SWRST_MASK 0x40 218 #define BD718XX_INT_PWRBTN_S_MASK 0x20 219 #define BD718XX_INT_PWRBTN_L_MASK 0x10 220 #define BD718XX_INT_PWRBTN_MASK 0x8 221 #define BD718XX_INT_WDOG_MASK 0x4 222 #define BD718XX_INT_ON_REQ_MASK 0x2 223 #define BD718XX_INT_STBY_REQ_MASK 0x1 224 225 /* Register write induced reset settings */ 226 227 /* 228 * Even though the bit zero is not SWRESET type we still want to write zero 229 * to it when changing type. Bit zero is 'SWRESET' trigger bit and if we 230 * write 1 to it we will trigger the action. So always write 0 to it when 231 * changning SWRESET action - no matter what we read from it. 232 */ 233 #define BD718XX_SWRESET_TYPE_MASK 7 234 #define BD718XX_SWRESET_TYPE_DISABLED 0 235 #define BD718XX_SWRESET_TYPE_COLD 4 236 #define BD718XX_SWRESET_TYPE_WARM 6 237 238 #define BD718XX_SWRESET_RESET_MASK 1 239 #define BD718XX_SWRESET_RESET 1 240 241 /* Poweroff state transition conditions */ 242 243 #define BD718XX_ON_REQ_POWEROFF_MASK 1 244 #define BD718XX_SWRESET_POWEROFF_MASK 2 245 #define BD718XX_WDOG_POWEROFF_MASK 4 246 #define BD718XX_KEY_L_POWEROFF_MASK 8 247 248 #define BD718XX_POWOFF_TO_SNVS 0 249 #define BD718XX_POWOFF_TO_RDY 0xF 250 251 #define BD718XX_POWOFF_TIME_MASK 0xF0 252 enum { 253 BD718XX_POWOFF_TIME_5MS = 0, 254 BD718XX_POWOFF_TIME_10MS, 255 BD718XX_POWOFF_TIME_15MS, 256 BD718XX_POWOFF_TIME_20MS, 257 BD718XX_POWOFF_TIME_25MS, 258 BD718XX_POWOFF_TIME_30MS, 259 BD718XX_POWOFF_TIME_35MS, 260 BD718XX_POWOFF_TIME_40MS, 261 BD718XX_POWOFF_TIME_45MS, 262 BD718XX_POWOFF_TIME_50MS, 263 BD718XX_POWOFF_TIME_75MS, 264 BD718XX_POWOFF_TIME_100MS, 265 BD718XX_POWOFF_TIME_250MS, 266 BD718XX_POWOFF_TIME_500MS, 267 BD718XX_POWOFF_TIME_750MS, 268 BD718XX_POWOFF_TIME_1500MS 269 }; 270 271 /* Poweron sequence state transition conditions */ 272 #define BD718XX_RDY_TO_SNVS_MASK 0xF 273 #define BD718XX_SNVS_TO_RUN_MASK 0xF0 274 275 #define BD718XX_PWR_TRIG_KEY_L 1 276 #define BD718XX_PWR_TRIG_KEY_S 2 277 #define BD718XX_PWR_TRIG_PMIC_ON 4 278 #define BD718XX_PWR_TRIG_VSYS_UVLO 8 279 #define BD718XX_RDY_TO_SNVS_SIFT 0 280 #define BD718XX_SNVS_TO_RUN_SIFT 4 281 282 #define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF 283 284 /* Timeout value for detecting short press */ 285 enum { 286 BD718XX_PWRBTN_SHORT_PRESS_10MS = 0, 287 BD718XX_PWRBTN_SHORT_PRESS_500MS, 288 BD718XX_PWRBTN_SHORT_PRESS_1000MS, 289 BD718XX_PWRBTN_SHORT_PRESS_1500MS, 290 BD718XX_PWRBTN_SHORT_PRESS_2000MS, 291 BD718XX_PWRBTN_SHORT_PRESS_2500MS, 292 BD718XX_PWRBTN_SHORT_PRESS_3000MS, 293 BD718XX_PWRBTN_SHORT_PRESS_3500MS, 294 BD718XX_PWRBTN_SHORT_PRESS_4000MS, 295 BD718XX_PWRBTN_SHORT_PRESS_4500MS, 296 BD718XX_PWRBTN_SHORT_PRESS_5000MS, 297 BD718XX_PWRBTN_SHORT_PRESS_5500MS, 298 BD718XX_PWRBTN_SHORT_PRESS_6000MS, 299 BD718XX_PWRBTN_SHORT_PRESS_6500MS, 300 BD718XX_PWRBTN_SHORT_PRESS_7000MS, 301 BD718XX_PWRBTN_SHORT_PRESS_7500MS 302 }; 303 304 /* Timeout value for detecting LONG press */ 305 enum { 306 BD718XX_PWRBTN_LONG_PRESS_10MS = 0, 307 BD718XX_PWRBTN_LONG_PRESS_1S, 308 BD718XX_PWRBTN_LONG_PRESS_2S, 309 BD718XX_PWRBTN_LONG_PRESS_3S, 310 BD718XX_PWRBTN_LONG_PRESS_4S, 311 BD718XX_PWRBTN_LONG_PRESS_5S, 312 BD718XX_PWRBTN_LONG_PRESS_6S, 313 BD718XX_PWRBTN_LONG_PRESS_7S, 314 BD718XX_PWRBTN_LONG_PRESS_8S, 315 BD718XX_PWRBTN_LONG_PRESS_9S, 316 BD718XX_PWRBTN_LONG_PRESS_10S, 317 BD718XX_PWRBTN_LONG_PRESS_11S, 318 BD718XX_PWRBTN_LONG_PRESS_12S, 319 BD718XX_PWRBTN_LONG_PRESS_13S, 320 BD718XX_PWRBTN_LONG_PRESS_14S, 321 BD718XX_PWRBTN_LONG_PRESS_15S 322 }; 323 324 struct bd718xx_clk; 325 326 struct bd718xx { 327 unsigned int chip_type; 328 struct device *dev; 329 struct regmap *regmap; 330 unsigned long int id; 331 332 int chip_irq; 333 struct regmap_irq_chip_data *irq_data; 334 335 struct bd718xx_clk *clk; 336 }; 337 338 #endif /* __LINUX_MFD_BD718XX_H__ */ 339