1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 7 #ifndef __MFD_MT6397_CORE_H__ 8 #define __MFD_MT6397_CORE_H__ 9 10 #include <linux/mutex.h> 11 #include <linux/notifier.h> 12 13 enum chip_id { 14 MT6323_CHIP_ID = 0x23, 15 MT6331_CHIP_ID = 0x20, 16 MT6332_CHIP_ID = 0x20, 17 MT6357_CHIP_ID = 0x57, 18 MT6358_CHIP_ID = 0x58, 19 MT6359_CHIP_ID = 0x59, 20 MT6366_CHIP_ID = 0x66, 21 MT6391_CHIP_ID = 0x91, 22 MT6397_CHIP_ID = 0x97, 23 }; 24 25 enum mt6397_irq_numbers { 26 MT6397_IRQ_SPKL_AB = 0, 27 MT6397_IRQ_SPKR_AB, 28 MT6397_IRQ_SPKL, 29 MT6397_IRQ_SPKR, 30 MT6397_IRQ_BAT_L, 31 MT6397_IRQ_BAT_H, 32 MT6397_IRQ_FG_BAT_L, 33 MT6397_IRQ_FG_BAT_H, 34 MT6397_IRQ_WATCHDOG, 35 MT6397_IRQ_PWRKEY, 36 MT6397_IRQ_THR_L, 37 MT6397_IRQ_THR_H, 38 MT6397_IRQ_VBATON_UNDET, 39 MT6397_IRQ_BVALID_DET, 40 MT6397_IRQ_CHRDET, 41 MT6397_IRQ_OV, 42 MT6397_IRQ_LDO, 43 MT6397_IRQ_HOMEKEY, 44 MT6397_IRQ_ACCDET, 45 MT6397_IRQ_AUDIO, 46 MT6397_IRQ_RTC, 47 MT6397_IRQ_PWRKEY_RSTB, 48 MT6397_IRQ_HDMI_SIFM, 49 MT6397_IRQ_HDMI_CEC, 50 MT6397_IRQ_VCA15, 51 MT6397_IRQ_VSRMCA15, 52 MT6397_IRQ_VCORE, 53 MT6397_IRQ_VGPU, 54 MT6397_IRQ_VIO18, 55 MT6397_IRQ_VPCA7, 56 MT6397_IRQ_VSRMCA7, 57 MT6397_IRQ_VDRM, 58 MT6397_IRQ_NR, 59 }; 60 61 struct mt6397_chip { 62 struct device *dev; 63 struct regmap *regmap; 64 struct notifier_block pm_nb; 65 int irq; 66 struct irq_domain *irq_domain; 67 struct mutex irqlock; 68 u16 wake_mask[2]; 69 u16 irq_masks_cur[2]; 70 u16 irq_masks_cache[2]; 71 u16 int_con[2]; 72 u16 int_status[2]; 73 u16 chip_id; 74 void *irq_data; 75 }; 76 77 int mt6358_irq_init(struct mt6397_chip *chip); 78 int mt6397_irq_init(struct mt6397_chip *chip); 79 80 #endif /* __MFD_MT6397_CORE_H__ */ 81