1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 7 #ifndef __MFD_MT6397_CORE_H__ 8 #define __MFD_MT6397_CORE_H__ 9 10 enum mt6397_irq_numbers { 11 MT6397_IRQ_SPKL_AB = 0, 12 MT6397_IRQ_SPKR_AB, 13 MT6397_IRQ_SPKL, 14 MT6397_IRQ_SPKR, 15 MT6397_IRQ_BAT_L, 16 MT6397_IRQ_BAT_H, 17 MT6397_IRQ_FG_BAT_L, 18 MT6397_IRQ_FG_BAT_H, 19 MT6397_IRQ_WATCHDOG, 20 MT6397_IRQ_PWRKEY, 21 MT6397_IRQ_THR_L, 22 MT6397_IRQ_THR_H, 23 MT6397_IRQ_VBATON_UNDET, 24 MT6397_IRQ_BVALID_DET, 25 MT6397_IRQ_CHRDET, 26 MT6397_IRQ_OV, 27 MT6397_IRQ_LDO, 28 MT6397_IRQ_HOMEKEY, 29 MT6397_IRQ_ACCDET, 30 MT6397_IRQ_AUDIO, 31 MT6397_IRQ_RTC, 32 MT6397_IRQ_PWRKEY_RSTB, 33 MT6397_IRQ_HDMI_SIFM, 34 MT6397_IRQ_HDMI_CEC, 35 MT6397_IRQ_VCA15, 36 MT6397_IRQ_VSRMCA15, 37 MT6397_IRQ_VCORE, 38 MT6397_IRQ_VGPU, 39 MT6397_IRQ_VIO18, 40 MT6397_IRQ_VPCA7, 41 MT6397_IRQ_VSRMCA7, 42 MT6397_IRQ_VDRM, 43 MT6397_IRQ_NR, 44 }; 45 46 struct mt6397_chip { 47 struct device *dev; 48 struct regmap *regmap; 49 int irq; 50 struct irq_domain *irq_domain; 51 struct mutex irqlock; 52 u16 wake_mask[2]; 53 u16 irq_masks_cur[2]; 54 u16 irq_masks_cache[2]; 55 u16 int_con[2]; 56 u16 int_status[2]; 57 }; 58 59 #endif /* __MFD_MT6397_CORE_H__ */ 60