1*3d51ec93SPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */ 2*3d51ec93SPaul Cercueil /* 3*3d51ec93SPaul Cercueil * Header file for the Ingenic JZ47xx TCU driver 4*3d51ec93SPaul Cercueil */ 5*3d51ec93SPaul Cercueil #ifndef __LINUX_MFD_INGENIC_TCU_H_ 6*3d51ec93SPaul Cercueil #define __LINUX_MFD_INGENIC_TCU_H_ 7*3d51ec93SPaul Cercueil 8*3d51ec93SPaul Cercueil #include <linux/bitops.h> 9*3d51ec93SPaul Cercueil 10*3d51ec93SPaul Cercueil #define TCU_REG_WDT_TDR 0x00 11*3d51ec93SPaul Cercueil #define TCU_REG_WDT_TCER 0x04 12*3d51ec93SPaul Cercueil #define TCU_REG_WDT_TCNT 0x08 13*3d51ec93SPaul Cercueil #define TCU_REG_WDT_TCSR 0x0c 14*3d51ec93SPaul Cercueil #define TCU_REG_TER 0x10 15*3d51ec93SPaul Cercueil #define TCU_REG_TESR 0x14 16*3d51ec93SPaul Cercueil #define TCU_REG_TECR 0x18 17*3d51ec93SPaul Cercueil #define TCU_REG_TSR 0x1c 18*3d51ec93SPaul Cercueil #define TCU_REG_TFR 0x20 19*3d51ec93SPaul Cercueil #define TCU_REG_TFSR 0x24 20*3d51ec93SPaul Cercueil #define TCU_REG_TFCR 0x28 21*3d51ec93SPaul Cercueil #define TCU_REG_TSSR 0x2c 22*3d51ec93SPaul Cercueil #define TCU_REG_TMR 0x30 23*3d51ec93SPaul Cercueil #define TCU_REG_TMSR 0x34 24*3d51ec93SPaul Cercueil #define TCU_REG_TMCR 0x38 25*3d51ec93SPaul Cercueil #define TCU_REG_TSCR 0x3c 26*3d51ec93SPaul Cercueil #define TCU_REG_TDFR0 0x40 27*3d51ec93SPaul Cercueil #define TCU_REG_TDHR0 0x44 28*3d51ec93SPaul Cercueil #define TCU_REG_TCNT0 0x48 29*3d51ec93SPaul Cercueil #define TCU_REG_TCSR0 0x4c 30*3d51ec93SPaul Cercueil #define TCU_REG_OST_DR 0xe0 31*3d51ec93SPaul Cercueil #define TCU_REG_OST_CNTL 0xe4 32*3d51ec93SPaul Cercueil #define TCU_REG_OST_CNTH 0xe8 33*3d51ec93SPaul Cercueil #define TCU_REG_OST_TCSR 0xec 34*3d51ec93SPaul Cercueil #define TCU_REG_TSTR 0xf0 35*3d51ec93SPaul Cercueil #define TCU_REG_TSTSR 0xf4 36*3d51ec93SPaul Cercueil #define TCU_REG_TSTCR 0xf8 37*3d51ec93SPaul Cercueil #define TCU_REG_OST_CNTHBUF 0xfc 38*3d51ec93SPaul Cercueil 39*3d51ec93SPaul Cercueil #define TCU_TCSR_RESERVED_BITS 0x3f 40*3d51ec93SPaul Cercueil #define TCU_TCSR_PARENT_CLOCK_MASK 0x07 41*3d51ec93SPaul Cercueil #define TCU_TCSR_PRESCALE_LSB 3 42*3d51ec93SPaul Cercueil #define TCU_TCSR_PRESCALE_MASK 0x38 43*3d51ec93SPaul Cercueil 44*3d51ec93SPaul Cercueil #define TCU_TCSR_PWM_SD BIT(9) /* 0: Shutdown abruptly 1: gracefully */ 45*3d51ec93SPaul Cercueil #define TCU_TCSR_PWM_INITL_HIGH BIT(8) /* Sets the initial output level */ 46*3d51ec93SPaul Cercueil #define TCU_TCSR_PWM_EN BIT(7) /* PWM pin output enable */ 47*3d51ec93SPaul Cercueil 48*3d51ec93SPaul Cercueil #define TCU_WDT_TCER_TCEN BIT(0) /* Watchdog timer enable */ 49*3d51ec93SPaul Cercueil 50*3d51ec93SPaul Cercueil #define TCU_CHANNEL_STRIDE 0x10 51*3d51ec93SPaul Cercueil #define TCU_REG_TDFRc(c) (TCU_REG_TDFR0 + ((c) * TCU_CHANNEL_STRIDE)) 52*3d51ec93SPaul Cercueil #define TCU_REG_TDHRc(c) (TCU_REG_TDHR0 + ((c) * TCU_CHANNEL_STRIDE)) 53*3d51ec93SPaul Cercueil #define TCU_REG_TCNTc(c) (TCU_REG_TCNT0 + ((c) * TCU_CHANNEL_STRIDE)) 54*3d51ec93SPaul Cercueil #define TCU_REG_TCSRc(c) (TCU_REG_TCSR0 + ((c) * TCU_CHANNEL_STRIDE)) 55*3d51ec93SPaul Cercueil 56*3d51ec93SPaul Cercueil #endif /* __LINUX_MFD_INGENIC_TCU_H_ */ 57