1 /* 2 * DaVinci Voice Codec Core Interface for TI platforms 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc 5 * 6 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_ 24 #define __LINUX_MFD_DAVINCI_VOICECODEC_H_ 25 26 #include <linux/kernel.h> 27 #include <linux/platform_device.h> 28 #include <linux/mfd/core.h> 29 #include <linux/platform_data/edma.h> 30 31 struct regmap; 32 33 /* 34 * Register values. 35 */ 36 #define DAVINCI_VC_PID 0x00 37 #define DAVINCI_VC_CTRL 0x04 38 #define DAVINCI_VC_INTEN 0x08 39 #define DAVINCI_VC_INTSTATUS 0x0c 40 #define DAVINCI_VC_INTCLR 0x10 41 #define DAVINCI_VC_EMUL_CTRL 0x14 42 #define DAVINCI_VC_RFIFO 0x20 43 #define DAVINCI_VC_WFIFO 0x24 44 #define DAVINCI_VC_FIFOSTAT 0x28 45 #define DAVINCI_VC_TST_CTRL 0x2C 46 #define DAVINCI_VC_REG05 0x94 47 #define DAVINCI_VC_REG09 0xA4 48 #define DAVINCI_VC_REG12 0xB0 49 50 /* DAVINCI_VC_CTRL bit fields */ 51 #define DAVINCI_VC_CTRL_MASK 0x5500 52 #define DAVINCI_VC_CTRL_RSTADC BIT(0) 53 #define DAVINCI_VC_CTRL_RSTDAC BIT(1) 54 #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4) 55 #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5) 56 #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6) 57 #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7) 58 #define DAVINCI_VC_CTRL_RFIFOEN BIT(8) 59 #define DAVINCI_VC_CTRL_RFIFOCL BIT(9) 60 #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10) 61 #define DAVINCI_VC_CTRL_WFIFOEN BIT(12) 62 #define DAVINCI_VC_CTRL_WFIFOCL BIT(13) 63 #define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14) 64 65 /* DAVINCI_VC_INT bit fields */ 66 #define DAVINCI_VC_INT_MASK 0x3F 67 #define DAVINCI_VC_INT_RDRDY_MASK BIT(0) 68 #define DAVINCI_VC_INT_RERROVF_MASK BIT(1) 69 #define DAVINCI_VC_INT_RERRUDR_MASK BIT(2) 70 #define DAVINCI_VC_INT_WDREQ_MASK BIT(3) 71 #define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4) 72 #define DAVINCI_VC_INT_WERRUDR_MASK BIT(5) 73 74 /* DAVINCI_VC_REG05 bit fields */ 75 #define DAVINCI_VC_REG05_PGA_GAIN 0x07 76 77 /* DAVINCI_VC_REG09 bit fields */ 78 #define DAVINCI_VC_REG09_MUTE 0x40 79 #define DAVINCI_VC_REG09_DIG_ATTEN 0x3F 80 81 /* DAVINCI_VC_REG12 bit fields */ 82 #define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD 83 #define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00 84 85 #define DAVINCI_VC_CELLS 2 86 87 enum davinci_vc_cells { 88 DAVINCI_VC_VCIF_CELL, 89 DAVINCI_VC_CQ93VC_CELL, 90 }; 91 92 struct davinci_vcif { 93 struct platform_device *pdev; 94 u32 dma_tx_channel; 95 u32 dma_rx_channel; 96 dma_addr_t dma_tx_addr; 97 dma_addr_t dma_rx_addr; 98 }; 99 100 struct davinci_vc { 101 /* Device data */ 102 struct device *dev; 103 struct platform_device *pdev; 104 struct clk *clk; 105 106 /* Memory resources */ 107 void __iomem *base; 108 struct regmap *regmap; 109 110 /* MFD cells */ 111 struct mfd_cell cells[DAVINCI_VC_CELLS]; 112 113 /* Client devices */ 114 struct davinci_vcif davinci_vcif; 115 }; 116 117 #endif 118